From 054cffc0553027c830b01a31ae5f51d051ab549b Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Mon, 5 Oct 2020 00:22:58 -0700 Subject: [PATCH 01/30] Changes to build VexRiscv versions with Cfu plugin: - Now submodule ext/VexRiscv uses tip of `dev` branch - Added ext/SpinalHDL submodule, also `dev` branch - Modified `build.sbt` to bring up to date with current `dev` VexRiscv - Modified `src/main/scala/vexriscv/GenCoreDefault.scala` to add a `--cfu` option, to add the CFU interface - Added `VexRiscv_FullCfu.v` and `VexRiscv_FullCfuDebug.v` (and yamls), and updated `Makefile` to build them - I did **not** rebuild the other .v/.yaml files Signed-off-by: Tim Callahan --- .gitmodules | 7 +- pythondata_cpu_vexriscv/verilog/.gitignore | 34 - pythondata_cpu_vexriscv/verilog/.gitmodules | 3 - pythondata_cpu_vexriscv/verilog/Makefile | 6 + pythondata_cpu_vexriscv/verilog/README.md | 10 + .../verilog/VexRiscv_FullCfu.v | 6503 ++++++++++++++++ .../verilog/VexRiscv_FullCfu.yaml | 4 + .../verilog/VexRiscv_FullCfuDebug.v | 6802 +++++++++++++++++ .../verilog/VexRiscv_FullCfuDebug.yaml | 5 + pythondata_cpu_vexriscv/verilog/build.sbt | 8 +- pythondata_cpu_vexriscv/verilog/ext/SpinalHDL | 1 + pythondata_cpu_vexriscv/verilog/ext/VexRiscv | 2 +- .../main/scala/vexriscv/GenCoreDefault.scala | 33 +- 13 files changed, 13376 insertions(+), 42 deletions(-) delete mode 100644 pythondata_cpu_vexriscv/verilog/.gitignore delete mode 100644 pythondata_cpu_vexriscv/verilog/.gitmodules create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.yaml create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml create mode 160000 pythondata_cpu_vexriscv/verilog/ext/SpinalHDL diff --git a/.gitmodules b/.gitmodules index dd91377..77ab592 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,8 @@ -[submodule "litex/data/cpu/vexriscv/verilog/ext/VexRiscv"] +[submodule "pythondata_cpu_vexriscv/verilog/ext/VexRiscv"] path = pythondata_cpu_vexriscv/verilog/ext/VexRiscv url = https://github.com/SpinalHDL/VexRiscv.git + branch = dev +[submodule "pythondata_cpu_vexriscv/verilog/ext/SpinalHDL"] + path = pythondata_cpu_vexriscv/verilog/ext/SpinalHDL + url = https://github.com/SpinalHDL/SpinalHDL.git + branch = dev diff --git a/pythondata_cpu_vexriscv/verilog/.gitignore b/pythondata_cpu_vexriscv/verilog/.gitignore deleted file mode 100644 index 5d70b87..0000000 --- a/pythondata_cpu_vexriscv/verilog/.gitignore +++ /dev/null @@ -1,34 +0,0 @@ -*.class -*.log -*.bak - -# sbt specific -.cache/ -.history/ -.lib/ -dist/* -target -lib_managed/ -src_managed/ -project/boot/ -project/plugins/project/ - -# Scala-IDE specific -.scala_dependencies -.worksheet - -.idea -out - -# Eclipse -bin/ -.classpath -.project -.settings -.cache-main - -#User -*.cf -*.json -*.vcd - diff --git a/pythondata_cpu_vexriscv/verilog/.gitmodules b/pythondata_cpu_vexriscv/verilog/.gitmodules deleted file mode 100644 index 2cef907..0000000 --- a/pythondata_cpu_vexriscv/verilog/.gitmodules +++ /dev/null @@ -1,3 +0,0 @@ -[submodule "ext/VexRiscv"] - path = ext/VexRiscv - url = ../../SpinalHDL/VexRiscv.git diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index c137e7e..d46540e 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -32,6 +32,12 @@ VexRiscv_Full.v: $(SRC) VexRiscv_FullDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --outputFile VexRiscv_FullDebug" +VexRiscv_FullCfu.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --cfu true --outputFile VexRiscv_FullCfu" + +VexRiscv_FullCfuDebug.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --cfu true --outputFile VexRiscv_FullCfuDebug" + VexRiscv_Linux.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal --outputFile VexRiscv_Linux" diff --git a/pythondata_cpu_vexriscv/verilog/README.md b/pythondata_cpu_vexriscv/verilog/README.md index 544daea..2152459 100644 --- a/pythondata_cpu_vexriscv/verilog/README.md +++ b/pythondata_cpu_vexriscv/verilog/README.md @@ -17,6 +17,16 @@ src/main/scala/vexriscv GenCoreDefault.scala - Available in normal an -Debug, with the Debug bus exposed +## Changes in `tcal-x`'s fork + +- Now submodule ext/VexRiscv uses tip of `dev` branch +- Added ext/SpinalHDL submodule, also `dev` branch +- Modified `build.sbt` to bring up to date with current `dev` VexRiscv +- Modified `src/main/scala/vexriscv/GenCoreDefault.scala` to add a `--cfu` option, to add the CFU interface +- Added `VexRiscv_FullCfu.v` and `VexRiscv_FullCfuDebug.v` (and yamls), and updated `Makefile` to build them +- I did **not** rebuild the other .v/.yaml files + + ## Requirements - Java 8 diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v new file mode 100644 index 0000000..80a07d6 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -0,0 +1,6503 @@ +// Generator : SpinalHDL v1.4.2 git head : 654057b2f5cec0f9fc99487dff67861f76fcbe7e +// Component : VexRiscv +// Git hash : 654057b2f5cec0f9fc99487dff67861f76fcbe7e + + +`define Input2Kind_defaultEncoding_type [0:0] +`define Input2Kind_defaultEncoding_RS 1'b0 +`define Input2Kind_defaultEncoding_IMM_I 1'b1 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [2:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input CfuPlugin_bus_rsp_payload_response_ok, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_189; + wire _zz_190; + wire _zz_191; + wire _zz_192; + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + reg _zz_197; + wire _zz_198; + wire [31:0] _zz_199; + wire _zz_200; + wire [31:0] _zz_201; + reg _zz_202; + wire _zz_203; + wire _zz_204; + wire [31:0] _zz_205; + wire _zz_206; + wire _zz_207; + wire _zz_208; + wire _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire [3:0] _zz_214; + wire _zz_215; + wire _zz_216; + reg [31:0] _zz_217; + reg [31:0] _zz_218; + reg [31:0] _zz_219; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_220; + wire _zz_221; + wire _zz_222; + wire _zz_223; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire [1:0] _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire [1:0] _zz_245; + wire _zz_246; + wire _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire [1:0] _zz_254; + wire _zz_255; + wire [1:0] _zz_256; + wire [51:0] _zz_257; + wire [51:0] _zz_258; + wire [51:0] _zz_259; + wire [32:0] _zz_260; + wire [51:0] _zz_261; + wire [49:0] _zz_262; + wire [51:0] _zz_263; + wire [49:0] _zz_264; + wire [51:0] _zz_265; + wire [32:0] _zz_266; + wire [31:0] _zz_267; + wire [32:0] _zz_268; + wire [0:0] _zz_269; + wire [0:0] _zz_270; + wire [0:0] _zz_271; + wire [0:0] _zz_272; + wire [0:0] _zz_273; + wire [0:0] _zz_274; + wire [0:0] _zz_275; + wire [0:0] _zz_276; + wire [0:0] _zz_277; + wire [0:0] _zz_278; + wire [0:0] _zz_279; + wire [0:0] _zz_280; + wire [0:0] _zz_281; + wire [0:0] _zz_282; + wire [0:0] _zz_283; + wire [0:0] _zz_284; + wire [0:0] _zz_285; + wire [0:0] _zz_286; + wire [3:0] _zz_287; + wire [2:0] _zz_288; + wire [31:0] _zz_289; + wire [11:0] _zz_290; + wire [31:0] _zz_291; + wire [19:0] _zz_292; + wire [11:0] _zz_293; + wire [31:0] _zz_294; + wire [31:0] _zz_295; + wire [19:0] _zz_296; + wire [11:0] _zz_297; + wire [2:0] _zz_298; + wire [2:0] _zz_299; + wire [0:0] _zz_300; + wire [2:0] _zz_301; + wire [4:0] _zz_302; + wire [11:0] _zz_303; + wire [11:0] _zz_304; + wire [31:0] _zz_305; + wire [31:0] _zz_306; + wire [31:0] _zz_307; + wire [31:0] _zz_308; + wire [31:0] _zz_309; + wire [31:0] _zz_310; + wire [31:0] _zz_311; + wire [11:0] _zz_312; + wire [19:0] _zz_313; + wire [11:0] _zz_314; + wire [31:0] _zz_315; + wire [31:0] _zz_316; + wire [31:0] _zz_317; + wire [11:0] _zz_318; + wire [19:0] _zz_319; + wire [11:0] _zz_320; + wire [2:0] _zz_321; + wire [1:0] _zz_322; + wire [1:0] _zz_323; + wire [1:0] _zz_324; + wire [1:0] _zz_325; + wire [2:0] _zz_326; + wire [11:0] _zz_327; + wire [65:0] _zz_328; + wire [65:0] _zz_329; + wire [31:0] _zz_330; + wire [31:0] _zz_331; + wire [0:0] _zz_332; + wire [5:0] _zz_333; + wire [32:0] _zz_334; + wire [31:0] _zz_335; + wire [31:0] _zz_336; + wire [32:0] _zz_337; + wire [32:0] _zz_338; + wire [32:0] _zz_339; + wire [32:0] _zz_340; + wire [0:0] _zz_341; + wire [32:0] _zz_342; + wire [0:0] _zz_343; + wire [32:0] _zz_344; + wire [0:0] _zz_345; + wire [31:0] _zz_346; + wire [0:0] _zz_347; + wire [0:0] _zz_348; + wire [0:0] _zz_349; + wire [0:0] _zz_350; + wire [0:0] _zz_351; + wire [0:0] _zz_352; + wire [0:0] _zz_353; + wire [26:0] _zz_354; + wire _zz_355; + wire _zz_356; + wire [1:0] _zz_357; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire [31:0] _zz_360; + wire _zz_361; + wire [0:0] _zz_362; + wire [14:0] _zz_363; + wire [31:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire _zz_367; + wire [0:0] _zz_368; + wire [8:0] _zz_369; + wire [31:0] _zz_370; + wire [31:0] _zz_371; + wire [31:0] _zz_372; + wire _zz_373; + wire [0:0] _zz_374; + wire [2:0] _zz_375; + wire _zz_376; + wire _zz_377; + wire _zz_378; + wire [31:0] _zz_379; + wire [31:0] _zz_380; + wire _zz_381; + wire _zz_382; + wire [0:0] _zz_383; + wire [26:0] _zz_384; + wire [31:0] _zz_385; + wire [31:0] _zz_386; + wire [31:0] _zz_387; + wire [0:0] _zz_388; + wire [0:0] _zz_389; + wire [1:0] _zz_390; + wire [1:0] _zz_391; + wire _zz_392; + wire [0:0] _zz_393; + wire [21:0] _zz_394; + wire [31:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire [31:0] _zz_399; + wire [31:0] _zz_400; + wire [0:0] _zz_401; + wire [0:0] _zz_402; + wire [2:0] _zz_403; + wire [2:0] _zz_404; + wire _zz_405; + wire [0:0] _zz_406; + wire [18:0] _zz_407; + wire [31:0] _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire [31:0] _zz_411; + wire _zz_412; + wire _zz_413; + wire [31:0] _zz_414; + wire [31:0] _zz_415; + wire _zz_416; + wire [0:0] _zz_417; + wire [0:0] _zz_418; + wire _zz_419; + wire [0:0] _zz_420; + wire [15:0] _zz_421; + wire [31:0] _zz_422; + wire _zz_423; + wire _zz_424; + wire _zz_425; + wire [2:0] _zz_426; + wire [2:0] _zz_427; + wire _zz_428; + wire [0:0] _zz_429; + wire [12:0] _zz_430; + wire _zz_431; + wire _zz_432; + wire _zz_433; + wire [0:0] _zz_434; + wire [2:0] _zz_435; + wire _zz_436; + wire [5:0] _zz_437; + wire [5:0] _zz_438; + wire _zz_439; + wire [0:0] _zz_440; + wire [9:0] _zz_441; + wire [31:0] _zz_442; + wire [31:0] _zz_443; + wire [31:0] _zz_444; + wire [31:0] _zz_445; + wire [31:0] _zz_446; + wire _zz_447; + wire [0:0] _zz_448; + wire [0:0] _zz_449; + wire [31:0] _zz_450; + wire _zz_451; + wire [0:0] _zz_452; + wire [3:0] _zz_453; + wire [0:0] _zz_454; + wire [3:0] _zz_455; + wire [5:0] _zz_456; + wire [5:0] _zz_457; + wire _zz_458; + wire [0:0] _zz_459; + wire [7:0] _zz_460; + wire [31:0] _zz_461; + wire [31:0] _zz_462; + wire [31:0] _zz_463; + wire [31:0] _zz_464; + wire [31:0] _zz_465; + wire [31:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [0:0] _zz_469; + wire [1:0] _zz_470; + wire _zz_471; + wire [0:0] _zz_472; + wire [1:0] _zz_473; + wire [0:0] _zz_474; + wire [3:0] _zz_475; + wire [0:0] _zz_476; + wire [0:0] _zz_477; + wire [1:0] _zz_478; + wire [1:0] _zz_479; + wire _zz_480; + wire [0:0] _zz_481; + wire [5:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire _zz_485; + wire _zz_486; + wire [31:0] _zz_487; + wire [31:0] _zz_488; + wire [31:0] _zz_489; + wire _zz_490; + wire _zz_491; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire _zz_494; + wire [0:0] _zz_495; + wire [1:0] _zz_496; + wire [31:0] _zz_497; + wire [31:0] _zz_498; + wire _zz_499; + wire _zz_500; + wire [0:0] _zz_501; + wire [0:0] _zz_502; + wire _zz_503; + wire [0:0] _zz_504; + wire [3:0] _zz_505; + wire [31:0] _zz_506; + wire [31:0] _zz_507; + wire [31:0] _zz_508; + wire [31:0] _zz_509; + wire [31:0] _zz_510; + wire [31:0] _zz_511; + wire [31:0] _zz_512; + wire _zz_513; + wire _zz_514; + wire [31:0] _zz_515; + wire [31:0] _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [0:0] _zz_519; + wire [2:0] _zz_520; + wire [0:0] _zz_521; + wire [0:0] _zz_522; + wire _zz_523; + wire [0:0] _zz_524; + wire [1:0] _zz_525; + wire [31:0] _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; + wire _zz_529; + wire _zz_530; + wire [31:0] _zz_531; + wire _zz_532; + wire [0:0] _zz_533; + wire [0:0] _zz_534; + wire [0:0] _zz_535; + wire [0:0] _zz_536; + wire [1:0] _zz_537; + wire [1:0] _zz_538; + wire [0:0] _zz_539; + wire [0:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire [31:0] _zz_543; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire _zz_547; + wire _zz_548; + wire _zz_549; + wire [31:0] _zz_550; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_ENCODING; + wire `Input2Kind_defaultEncoding_type _zz_1; + wire `Input2Kind_defaultEncoding_type _zz_2; + wire `Input2Kind_defaultEncoding_type _zz_3; + wire decode_CfuPlugin_CFU_ENABLE; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `AluCtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_ENCODING; + wire `Input2Kind_defaultEncoding_type _zz_30; + wire execute_CfuPlugin_CFU_ENABLE; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_31; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_32; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_34; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_35; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_36; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_37; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_38; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_39; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_40; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_41; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_42; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_44; + wire _zz_45; + reg _zz_46; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `Input2Kind_defaultEncoding_type _zz_47; + wire `EnvCtrlEnum_defaultEncoding_type _zz_48; + wire `BranchCtrlEnum_defaultEncoding_type _zz_49; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_50; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_51; + wire `Src2CtrlEnum_defaultEncoding_type _zz_52; + wire `AluCtrlEnum_defaultEncoding_type _zz_53; + wire `Src1CtrlEnum_defaultEncoding_type _zz_54; + reg [31:0] _zz_55; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_56; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_57; + reg [31:0] _zz_58; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + reg CfuPlugin_joinException_valid; + wire [3:0] CfuPlugin_joinException_payload_code; + wire [31:0] CfuPlugin_joinException_payload_badAddr; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_59; + wire [3:0] _zz_60; + wire _zz_61; + wire _zz_62; + wire _zz_63; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_64; + wire _zz_65; + wire _zz_66; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_67; + wire _zz_68; + reg _zz_69; + wire _zz_70; + reg _zz_71; + reg [31:0] _zz_72; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_73; + reg [18:0] _zz_74; + wire _zz_75; + reg [10:0] _zz_76; + wire _zz_77; + reg [18:0] _zz_78; + reg _zz_79; + wire _zz_80; + reg [10:0] _zz_81; + wire _zz_82; + reg [18:0] _zz_83; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_84; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_85; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_86; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_87; + reg [31:0] _zz_88; + wire _zz_89; + reg [31:0] _zz_90; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [33:0] _zz_91; + wire _zz_92; + wire _zz_93; + wire _zz_94; + wire _zz_95; + wire _zz_96; + wire `Src1CtrlEnum_defaultEncoding_type _zz_97; + wire `AluCtrlEnum_defaultEncoding_type _zz_98; + wire `Src2CtrlEnum_defaultEncoding_type _zz_99; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_100; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_101; + wire `BranchCtrlEnum_defaultEncoding_type _zz_102; + wire `EnvCtrlEnum_defaultEncoding_type _zz_103; + wire `Input2Kind_defaultEncoding_type _zz_104; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_105; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_106; + reg [31:0] _zz_107; + wire _zz_108; + reg [19:0] _zz_109; + wire _zz_110; + reg [19:0] _zz_111; + reg [31:0] _zz_112; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_113; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_114; + reg _zz_115; + reg _zz_116; + reg _zz_117; + reg [4:0] _zz_118; + reg [31:0] _zz_119; + wire _zz_120; + wire _zz_121; + wire _zz_122; + wire _zz_123; + wire _zz_124; + wire _zz_125; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_126; + reg _zz_127; + reg _zz_128; + wire _zz_129; + reg [19:0] _zz_130; + wire _zz_131; + reg [10:0] _zz_132; + wire _zz_133; + reg [18:0] _zz_134; + reg _zz_135; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_136; + reg [19:0] _zz_137; + wire _zz_138; + reg [10:0] _zz_139; + wire _zz_140; + reg [18:0] _zz_141; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_142; + wire _zz_143; + wire _zz_144; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_145; + wire _zz_146; + wire [1:0] _zz_147; + wire _zz_148; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire [2:0] execute_CfuPlugin_functionsIds_0; + wire _zz_149; + reg [19:0] _zz_150; + reg [31:0] _zz_151; + wire memory_CfuPlugin_rsp_valid; + reg memory_CfuPlugin_rsp_ready; + wire memory_CfuPlugin_rsp_payload_response_ok; + wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_m2sPipe_rValid; + reg CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_152; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_153; + wire _zz_154; + wire _zz_155; + reg [32:0] _zz_156; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_157; + wire [31:0] _zz_158; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_ENCODING; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [2:0] _zz_180; + reg _zz_181; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_182; + wire _zz_183; + wire _zz_184; + wire _zz_185; + wire _zz_186; + wire _zz_187; + reg _zz_188; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [39:0] _zz_10_string; + reg [31:0] _zz_11_string; + reg [31:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [71:0] _zz_17_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [39:0] _zz_20_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [23:0] _zz_23_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [63:0] _zz_26_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [95:0] _zz_29_string; + reg [39:0] execute_CfuPlugin_CFU_ENCODING_string; + reg [39:0] _zz_30_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_31_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_32_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_33_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_34_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_37_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_38_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_40_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_41_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_42_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_43_string; + reg [39:0] _zz_47_string; + reg [39:0] _zz_48_string; + reg [31:0] _zz_49_string; + reg [71:0] _zz_50_string; + reg [39:0] _zz_51_string; + reg [23:0] _zz_52_string; + reg [63:0] _zz_53_string; + reg [95:0] _zz_54_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_56_string; + reg [95:0] _zz_97_string; + reg [63:0] _zz_98_string; + reg [23:0] _zz_99_string; + reg [39:0] _zz_100_string; + reg [71:0] _zz_101_string; + reg [31:0] _zz_102_string; + reg [39:0] _zz_103_string; + reg [39:0] _zz_104_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_ENCODING_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_220 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_221 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_222 = 1'b1; + assign _zz_223 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_224 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_225 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_226 = ((_zz_194 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_227 = ((_zz_194 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_228 = ((_zz_194 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_229 = ((_zz_194 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_230 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_231 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_232 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_233 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_234 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_235 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_236 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_237 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_238 = (1'b0 || (! 1'b1)); + assign _zz_239 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_240 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_241 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_242 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_243 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_244 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_245 = execute_INSTRUCTION[13 : 12]; + assign _zz_246 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_247 = (! memory_arbitration_isStuck); + assign _zz_248 = (iBus_cmd_valid || (_zz_180 != 3'b000)); + assign _zz_249 = (_zz_216 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_250 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_251 = ((_zz_142 && 1'b1) && (! 1'b0)); + assign _zz_252 = ((_zz_143 && 1'b1) && (! 1'b0)); + assign _zz_253 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_254 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_255 = execute_INSTRUCTION[13]; + assign _zz_256 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_257 = ($signed(_zz_258) + $signed(_zz_263)); + assign _zz_258 = ($signed(_zz_259) + $signed(_zz_261)); + assign _zz_259 = 52'h0; + assign _zz_260 = {1'b0,memory_MUL_LL}; + assign _zz_261 = {{19{_zz_260[32]}}, _zz_260}; + assign _zz_262 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_263 = {{2{_zz_262[49]}}, _zz_262}; + assign _zz_264 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_265 = {{2{_zz_264[49]}}, _zz_264}; + assign _zz_266 = ($signed(_zz_268) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_267 = _zz_266[31 : 0]; + assign _zz_268 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_269 = _zz_91[33 : 33]; + assign _zz_270 = _zz_91[32 : 32]; + assign _zz_271 = _zz_91[31 : 31]; + assign _zz_272 = _zz_91[30 : 30]; + assign _zz_273 = _zz_91[28 : 28]; + assign _zz_274 = _zz_91[25 : 25]; + assign _zz_275 = _zz_91[17 : 17]; + assign _zz_276 = _zz_91[16 : 16]; + assign _zz_277 = _zz_91[13 : 13]; + assign _zz_278 = _zz_91[12 : 12]; + assign _zz_279 = _zz_91[11 : 11]; + assign _zz_280 = _zz_91[15 : 15]; + assign _zz_281 = _zz_91[5 : 5]; + assign _zz_282 = _zz_91[3 : 3]; + assign _zz_283 = _zz_91[20 : 20]; + assign _zz_284 = _zz_91[10 : 10]; + assign _zz_285 = _zz_91[4 : 4]; + assign _zz_286 = _zz_91[0 : 0]; + assign _zz_287 = (_zz_59 - 4'b0001); + assign _zz_288 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_289 = {29'd0, _zz_288}; + assign _zz_290 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_291 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_292 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_293 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_294 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_295 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_296 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_297 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_298 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_299 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_300 = execute_SRC_LESS; + assign _zz_301 = 3'b100; + assign _zz_302 = execute_INSTRUCTION[19 : 15]; + assign _zz_303 = execute_INSTRUCTION[31 : 20]; + assign _zz_304 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_305 = ($signed(_zz_306) + $signed(_zz_309)); + assign _zz_306 = ($signed(_zz_307) + $signed(_zz_308)); + assign _zz_307 = execute_SRC1; + assign _zz_308 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_309 = (execute_SRC_USE_SUB_LESS ? _zz_310 : _zz_311); + assign _zz_310 = 32'h00000001; + assign _zz_311 = 32'h0; + assign _zz_312 = execute_INSTRUCTION[31 : 20]; + assign _zz_313 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_314 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_315 = {_zz_130,execute_INSTRUCTION[31 : 20]}; + assign _zz_316 = {{_zz_132,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_317 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_318 = execute_INSTRUCTION[31 : 20]; + assign _zz_319 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_320 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_321 = 3'b100; + assign _zz_322 = (_zz_145 & (~ _zz_323)); + assign _zz_323 = (_zz_145 - 2'b01); + assign _zz_324 = (_zz_147 & (~ _zz_325)); + assign _zz_325 = (_zz_147 - 2'b01); + assign _zz_326 = execute_INSTRUCTION[14 : 12]; + assign _zz_327 = execute_INSTRUCTION[31 : 20]; + assign _zz_328 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_329 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_330 = writeBack_MUL_LOW[31 : 0]; + assign _zz_331 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_332 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_333 = {5'd0, _zz_332}; + assign _zz_334 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_335 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_336 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_337 = {_zz_152,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_338 = _zz_339; + assign _zz_339 = _zz_340; + assign _zz_340 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_153) : _zz_153)} + _zz_342); + assign _zz_341 = memory_DivPlugin_div_needRevert; + assign _zz_342 = {32'd0, _zz_341}; + assign _zz_343 = _zz_155; + assign _zz_344 = {32'd0, _zz_343}; + assign _zz_345 = _zz_154; + assign _zz_346 = {31'd0, _zz_345}; + assign _zz_347 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_348 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_349 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_350 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_351 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_352 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_353 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_354 = (iBus_cmd_payload_address >>> 5); + assign _zz_355 = 1'b1; + assign _zz_356 = 1'b1; + assign _zz_357 = {_zz_63,_zz_62}; + assign _zz_358 = 32'h0000106f; + assign _zz_359 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_360 = 32'h00001073; + assign _zz_361 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_362 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_363 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_364) == 32'h00000003),{(_zz_365 == _zz_366),{_zz_367,{_zz_368,_zz_369}}}}}}; + assign _zz_364 = 32'h0000207f; + assign _zz_365 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_366 = 32'h00000003; + assign _zz_367 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_368 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_369 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_370) == 32'h00005013),{(_zz_371 == _zz_372),{_zz_373,{_zz_374,_zz_375}}}}}}; + assign _zz_370 = 32'hbc00707f; + assign _zz_371 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_372 = 32'h00001013; + assign _zz_373 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_374 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_375 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_376 = decode_INSTRUCTION[31]; + assign _zz_377 = decode_INSTRUCTION[31]; + assign _zz_378 = decode_INSTRUCTION[7]; + assign _zz_379 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_380 = 32'h02004020; + assign _zz_381 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_382 = (_zz_95 != 1'b0); + assign _zz_383 = (((decode_INSTRUCTION & _zz_385) == 32'h00000050) != 1'b0); + assign _zz_384 = {((_zz_386 == _zz_387) != 1'b0),{({_zz_388,_zz_389} != 2'b00),{(_zz_390 != _zz_391),{_zz_392,{_zz_393,_zz_394}}}}}; + assign _zz_385 = 32'h00203050; + assign _zz_386 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_387 = 32'h00000050; + assign _zz_388 = ((decode_INSTRUCTION & _zz_395) == 32'h00001050); + assign _zz_389 = ((decode_INSTRUCTION & _zz_396) == 32'h00002050); + assign _zz_390 = {_zz_94,(_zz_397 == _zz_398)}; + assign _zz_391 = 2'b00; + assign _zz_392 = ((_zz_399 == _zz_400) != 1'b0); + assign _zz_393 = ({_zz_401,_zz_402} != 2'b00); + assign _zz_394 = {(_zz_403 != _zz_404),{_zz_405,{_zz_406,_zz_407}}}; + assign _zz_395 = 32'h00001050; + assign _zz_396 = 32'h00002050; + assign _zz_397 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_398 = 32'h00000004; + assign _zz_399 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_400 = 32'h00000040; + assign _zz_401 = ((decode_INSTRUCTION & _zz_408) == 32'h00005010); + assign _zz_402 = ((decode_INSTRUCTION & _zz_409) == 32'h00005020); + assign _zz_403 = {(_zz_410 == _zz_411),{_zz_412,_zz_413}}; + assign _zz_404 = 3'b000; + assign _zz_405 = ((_zz_414 == _zz_415) != 1'b0); + assign _zz_406 = (_zz_416 != 1'b0); + assign _zz_407 = {(_zz_417 != _zz_418),{_zz_419,{_zz_420,_zz_421}}}; + assign _zz_408 = 32'h00007034; + assign _zz_409 = 32'h02007064; + assign _zz_410 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_411 = 32'h40001010; + assign _zz_412 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_413 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_414 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_415 = 32'h00000024; + assign _zz_416 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_417 = ((decode_INSTRUCTION & _zz_422) == 32'h00002000); + assign _zz_418 = 1'b0; + assign _zz_419 = ({_zz_423,_zz_424} != 2'b00); + assign _zz_420 = (_zz_425 != 1'b0); + assign _zz_421 = {(_zz_426 != _zz_427),{_zz_428,{_zz_429,_zz_430}}}; + assign _zz_422 = 32'h00003000; + assign _zz_423 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_424 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_425 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_426 = {_zz_95,{_zz_431,_zz_432}}; + assign _zz_427 = 3'b000; + assign _zz_428 = ({_zz_433,{_zz_434,_zz_435}} != 5'h0); + assign _zz_429 = (_zz_436 != 1'b0); + assign _zz_430 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; + assign _zz_431 = ((decode_INSTRUCTION & _zz_442) == 32'h00000020); + assign _zz_432 = ((decode_INSTRUCTION & _zz_443) == 32'h00000020); + assign _zz_433 = ((decode_INSTRUCTION & _zz_444) == 32'h00002040); + assign _zz_434 = (_zz_445 == _zz_446); + assign _zz_435 = {_zz_447,{_zz_448,_zz_449}}; + assign _zz_436 = ((decode_INSTRUCTION & _zz_450) == 32'h00000020); + assign _zz_437 = {_zz_451,{_zz_452,_zz_453}}; + assign _zz_438 = 6'h0; + assign _zz_439 = ({_zz_454,_zz_455} != 5'h0); + assign _zz_440 = (_zz_456 != _zz_457); + assign _zz_441 = {_zz_458,{_zz_459,_zz_460}}; + assign _zz_442 = 32'h00000034; + assign _zz_443 = 32'h00000064; + assign _zz_444 = 32'h00002040; + assign _zz_445 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_446 = 32'h00001040; + assign _zz_447 = ((decode_INSTRUCTION & _zz_461) == 32'h00000040); + assign _zz_448 = (_zz_462 == _zz_463); + assign _zz_449 = (_zz_464 == _zz_465); + assign _zz_450 = 32'h00000020; + assign _zz_451 = ((decode_INSTRUCTION & _zz_466) == 32'h00000008); + assign _zz_452 = (_zz_467 == _zz_468); + assign _zz_453 = {_zz_93,{_zz_469,_zz_470}}; + assign _zz_454 = _zz_93; + assign _zz_455 = {_zz_471,{_zz_472,_zz_473}}; + assign _zz_456 = {_zz_94,{_zz_474,_zz_475}}; + assign _zz_457 = 6'h0; + assign _zz_458 = ({_zz_476,_zz_477} != 2'b00); + assign _zz_459 = (_zz_478 != _zz_479); + assign _zz_460 = {_zz_480,{_zz_481,_zz_482}}; + assign _zz_461 = 32'h00000050; + assign _zz_462 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_463 = 32'h00000040; + assign _zz_464 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_465 = 32'h0; + assign _zz_466 = 32'h00000008; + assign _zz_467 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_468 = 32'h00000040; + assign _zz_469 = (_zz_483 == _zz_484); + assign _zz_470 = {_zz_485,_zz_486}; + assign _zz_471 = ((decode_INSTRUCTION & _zz_487) == 32'h00002010); + assign _zz_472 = (_zz_488 == _zz_489); + assign _zz_473 = {_zz_490,_zz_491}; + assign _zz_474 = (_zz_492 == _zz_493); + assign _zz_475 = {_zz_494,{_zz_495,_zz_496}}; + assign _zz_476 = _zz_93; + assign _zz_477 = (_zz_497 == _zz_498); + assign _zz_478 = {_zz_93,_zz_499}; + assign _zz_479 = 2'b00; + assign _zz_480 = (_zz_500 != 1'b0); + assign _zz_481 = (_zz_501 != _zz_502); + assign _zz_482 = {_zz_503,{_zz_504,_zz_505}}; + assign _zz_483 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_484 = 32'h00004020; + assign _zz_485 = ((decode_INSTRUCTION & _zz_506) == 32'h00000010); + assign _zz_486 = ((decode_INSTRUCTION & _zz_507) == 32'h00000020); + assign _zz_487 = 32'h00002030; + assign _zz_488 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_489 = 32'h00000010; + assign _zz_490 = ((decode_INSTRUCTION & _zz_508) == 32'h00002020); + assign _zz_491 = ((decode_INSTRUCTION & _zz_509) == 32'h00000020); + assign _zz_492 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_493 = 32'h00001010; + assign _zz_494 = ((decode_INSTRUCTION & _zz_510) == 32'h00002010); + assign _zz_495 = (_zz_511 == _zz_512); + assign _zz_496 = {_zz_513,_zz_514}; + assign _zz_497 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_498 = 32'h00000020; + assign _zz_499 = ((decode_INSTRUCTION & _zz_515) == 32'h0); + assign _zz_500 = ((decode_INSTRUCTION & _zz_516) == 32'h00004010); + assign _zz_501 = (_zz_517 == _zz_518); + assign _zz_502 = 1'b0; + assign _zz_503 = ({_zz_519,_zz_520} != 4'b0000); + assign _zz_504 = (_zz_521 != _zz_522); + assign _zz_505 = {_zz_523,{_zz_524,_zz_525}}; + assign _zz_506 = 32'h00000030; + assign _zz_507 = 32'h02000020; + assign _zz_508 = 32'h02002060; + assign _zz_509 = 32'h02003020; + assign _zz_510 = 32'h00002010; + assign _zz_511 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_512 = 32'h00000010; + assign _zz_513 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_514 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_515 = 32'h00000020; + assign _zz_516 = 32'h00004014; + assign _zz_517 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_518 = 32'h00002010; + assign _zz_519 = ((decode_INSTRUCTION & _zz_526) == 32'h0); + assign _zz_520 = {(_zz_527 == _zz_528),{_zz_529,_zz_530}}; + assign _zz_521 = ((decode_INSTRUCTION & _zz_531) == 32'h0); + assign _zz_522 = 1'b0; + assign _zz_523 = ({_zz_532,{_zz_533,_zz_534}} != 3'b000); + assign _zz_524 = ({_zz_535,_zz_536} != 2'b00); + assign _zz_525 = {(_zz_537 != _zz_538),(_zz_539 != _zz_540)}; + assign _zz_526 = 32'h00000044; + assign _zz_527 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_528 = 32'h0; + assign _zz_529 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_530 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_531 = 32'h00000058; + assign _zz_532 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_533 = ((decode_INSTRUCTION & _zz_541) == 32'h00002010); + assign _zz_534 = ((decode_INSTRUCTION & _zz_542) == 32'h40000030); + assign _zz_535 = ((decode_INSTRUCTION & _zz_543) == 32'h00000004); + assign _zz_536 = _zz_92; + assign _zz_537 = {(_zz_544 == _zz_545),_zz_92}; + assign _zz_538 = 2'b00; + assign _zz_539 = ((decode_INSTRUCTION & _zz_546) == 32'h00001004); + assign _zz_540 = 1'b0; + assign _zz_541 = 32'h00002014; + assign _zz_542 = 32'h40000034; + assign _zz_543 = 32'h00000014; + assign _zz_544 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_545 = 32'h00000004; + assign _zz_546 = 32'h00005054; + assign _zz_547 = execute_INSTRUCTION[31]; + assign _zz_548 = execute_INSTRUCTION[31]; + assign _zz_549 = execute_INSTRUCTION[7]; + assign _zz_550 = 32'h0; + always @ (posedge clk) begin + if(_zz_355) begin + _zz_217 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_356) begin + _zz_218 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_46) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_189 ), //i + .io_cpu_prefetch_isValid (_zz_190 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_191 ), //i + .io_cpu_fetch_isStuck (_zz_192 ), //i + .io_cpu_fetch_isRemoved (_zz_193 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_194 ), //i + .io_cpu_decode_isStuck (_zz_195 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_196 ), //i + .io_cpu_fill_valid (_zz_197 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_198 ), //i + .io_cpu_execute_address (_zz_199[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_86[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_memory_isValid (_zz_200 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_201[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_202 ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_203 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_204 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_205[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_206 ), //i + .io_cpu_writeBack_fence_SR (_zz_207 ), //i + .io_cpu_writeBack_fence_SO (_zz_208 ), //i + .io_cpu_writeBack_fence_SI (_zz_209 ), //i + .io_cpu_writeBack_fence_PW (_zz_210 ), //i + .io_cpu_writeBack_fence_PR (_zz_211 ), //i + .io_cpu_writeBack_fence_PO (_zz_212 ), //i + .io_cpu_writeBack_fence_PI (_zz_213 ), //i + .io_cpu_writeBack_fence_FM (_zz_214[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_215 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_216 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_357) + 2'b00 : begin + _zz_219 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_219 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_219 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_219 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_CfuPlugin_CFU_ENCODING) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_ENCODING_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_ENCODING_string = "IMM_I"; + default : decode_CfuPlugin_CFU_ENCODING_string = "?????"; + endcase + end + always @(*) begin + case(_zz_1) + `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; + default : _zz_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_2) + `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; + default : _zz_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_3) + `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; + default : _zz_10_string = "?????"; + endcase + end + always @(*) begin + case(_zz_11) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; + default : _zz_12_string = "????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; + default : _zz_17_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; + default : _zz_20_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(_zz_23) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(_zz_26) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; + default : _zz_26_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_29) + `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; + default : _zz_29_string = "????????????"; + endcase + end + always @(*) begin + case(execute_CfuPlugin_CFU_ENCODING) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_ENCODING_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_ENCODING_string = "IMM_I"; + default : execute_CfuPlugin_CFU_ENCODING_string = "?????"; + endcase + end + always @(*) begin + case(_zz_30) + `Input2Kind_defaultEncoding_RS : _zz_30_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_30_string = "IMM_I"; + default : _zz_30_string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_31) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_31_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_31_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_31_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_31_string = "ECALL"; + default : _zz_31_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_32_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_32_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_32_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32_string = "ECALL"; + default : _zz_32_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_34) + `BranchCtrlEnum_defaultEncoding_INC : _zz_34_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_34_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_34_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_34_string = "JALR"; + default : _zz_34_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_37) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_37_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_37_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_37_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_37_string = "SRA_1 "; + default : _zz_37_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_38) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38_string = "SRA_1 "; + default : _zz_38_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_40) + `Src2CtrlEnum_defaultEncoding_RS : _zz_40_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_40_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_40_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_40_string = "PC "; + default : _zz_40_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_41) + `Src1CtrlEnum_defaultEncoding_RS : _zz_41_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_41_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_41_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_41_string = "URS1 "; + default : _zz_41_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_42) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_42_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_42_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_42_string = "BITWISE "; + default : _zz_42_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_43) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; + default : _zz_43_string = "?????"; + endcase + end + always @(*) begin + case(_zz_47) + `Input2Kind_defaultEncoding_RS : _zz_47_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_47_string = "IMM_I"; + default : _zz_47_string = "?????"; + endcase + end + always @(*) begin + case(_zz_48) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_48_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_48_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_48_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_48_string = "ECALL"; + default : _zz_48_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `BranchCtrlEnum_defaultEncoding_INC : _zz_49_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_49_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_49_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_49_string = "JALR"; + default : _zz_49_string = "????"; + endcase + end + always @(*) begin + case(_zz_50) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_50_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_50_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_50_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_50_string = "SRA_1 "; + default : _zz_50_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_51) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_51_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_51_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_51_string = "AND_1"; + default : _zz_51_string = "?????"; + endcase + end + always @(*) begin + case(_zz_52) + `Src2CtrlEnum_defaultEncoding_RS : _zz_52_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_52_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_52_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_52_string = "PC "; + default : _zz_52_string = "???"; + endcase + end + always @(*) begin + case(_zz_53) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_53_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_53_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_53_string = "BITWISE "; + default : _zz_53_string = "????????"; + endcase + end + always @(*) begin + case(_zz_54) + `Src1CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_54_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54_string = "URS1 "; + default : _zz_54_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_56) + `BranchCtrlEnum_defaultEncoding_INC : _zz_56_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_56_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_56_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_56_string = "JALR"; + default : _zz_56_string = "????"; + endcase + end + always @(*) begin + case(_zz_97) + `Src1CtrlEnum_defaultEncoding_RS : _zz_97_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_97_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_97_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_97_string = "URS1 "; + default : _zz_97_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_98) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_98_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_98_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_98_string = "BITWISE "; + default : _zz_98_string = "????????"; + endcase + end + always @(*) begin + case(_zz_99) + `Src2CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_99_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_99_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_99_string = "PC "; + default : _zz_99_string = "???"; + endcase + end + always @(*) begin + case(_zz_100) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_100_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_100_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_100_string = "AND_1"; + default : _zz_100_string = "?????"; + endcase + end + always @(*) begin + case(_zz_101) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_101_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_101_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_101_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_101_string = "SRA_1 "; + default : _zz_101_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_102) + `BranchCtrlEnum_defaultEncoding_INC : _zz_102_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_102_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_102_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_102_string = "JALR"; + default : _zz_102_string = "????"; + endcase + end + always @(*) begin + case(_zz_103) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_103_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_103_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_103_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_103_string = "ECALL"; + default : _zz_103_string = "?????"; + endcase + end + always @(*) begin + case(_zz_104) + `Input2Kind_defaultEncoding_RS : _zz_104_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_104_string = "IMM_I"; + default : _zz_104_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_CfuPlugin_CFU_ENCODING) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "?????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_257) + $signed(_zz_265)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_267; + assign execute_REGFILE_WRITE_DATA = _zz_106; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_199[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_269[0]; + assign decode_IS_RS1_SIGNED = _zz_270[0]; + assign decode_IS_DIV = _zz_271[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_272[0]; + assign decode_CfuPlugin_CFU_ENCODING = _zz_1; + assign _zz_2 = _zz_3; + assign decode_CfuPlugin_CFU_ENABLE = _zz_273[0]; + assign _zz_4 = _zz_5; + assign _zz_6 = _zz_7; + assign decode_ENV_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_IS_CSR = _zz_274[0]; + assign _zz_11 = _zz_12; + assign _zz_13 = _zz_14; + assign decode_SHIFT_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_ALU_BITWISE_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_SRC_LESS_UNSIGNED = _zz_275[0]; + assign decode_MEMORY_MANAGMENT = _zz_276[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_277[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_278[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_279[0]; + assign decode_SRC2_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_ALU_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_SRC1_CTRL = _zz_27; + assign _zz_28 = _zz_29; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_ENCODING = _zz_30; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_31; + assign execute_ENV_CTRL = _zz_32; + assign writeBack_ENV_CTRL = _zz_33; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_128; + assign execute_BRANCH_CTRL = _zz_34; + assign decode_RS2_USE = _zz_280[0]; + assign decode_RS1_USE = _zz_281[0]; + always @ (*) begin + _zz_35 = execute_REGFILE_WRITE_DATA; + if(_zz_220)begin + _zz_35 = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_117)begin + if((_zz_118 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_119; + end + end + if(_zz_221)begin + if(_zz_222)begin + if(_zz_121)begin + decode_RS2 = _zz_55; + end + end + end + if(_zz_223)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_123)begin + decode_RS2 = _zz_36; + end + end + end + if(_zz_224)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_125)begin + decode_RS2 = _zz_35; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_117)begin + if((_zz_118 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_119; + end + end + if(_zz_221)begin + if(_zz_222)begin + if(_zz_120)begin + decode_RS1 = _zz_55; + end + end + end + if(_zz_223)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_122)begin + decode_RS1 = _zz_36; + end + end + end + if(_zz_224)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_124)begin + decode_RS1 = _zz_35; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_36 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_36 = _zz_114; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_36 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_36 = memory_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_225)begin + _zz_36 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_37; + assign execute_SHIFT_CTRL = _zz_38; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_39 = execute_PC; + assign execute_SRC2_CTRL = _zz_40; + assign execute_SRC1_CTRL = _zz_41; + assign decode_SRC_USE_SUB_LESS = _zz_282[0]; + assign decode_SRC_ADD_ZERO = _zz_283[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_42; + assign execute_SRC2 = _zz_112; + assign execute_SRC1 = _zz_107; + assign execute_ALU_BITWISE_CTRL = _zz_43; + assign _zz_44 = writeBack_INSTRUCTION; + assign _zz_45 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_46 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_46 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_284[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_358) == 32'h00000003),{(_zz_359 == _zz_360),{_zz_361,{_zz_362,_zz_363}}}}}}} != 22'h0); + always @ (*) begin + _zz_55 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_55 = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_256) + 2'b00 : begin + _zz_55 = _zz_330; + end + default : begin + _zz_55 = _zz_331; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_285[0]; + assign decode_FLUSH_ALL = _zz_286[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_226)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_227)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_228)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_229)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_56; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_57 = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_57 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_58 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_58 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_115 || _zz_116)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_230)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_230)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((_zz_215 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + execute_arbitration_haltItself = 1'b1; + end + if(((dataCache_1_io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_231)begin + if((! execute_CsrPlugin_wfiWake))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_220)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if((! memory_CfuPlugin_rsp_valid))begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_225)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(_zz_232)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(_zz_232)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_233)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_234)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_233)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_234)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_231)begin + CsrPlugin_inWfi = 1'b1; + end + end + + assign CsrPlugin_thirdPartyWake = 1'b0; + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_233)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_234)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_233)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_234)begin + case(_zz_235) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_59 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_60 = (_zz_59 & (~ _zz_287)); + assign _zz_61 = _zz_60[3]; + assign _zz_62 = (_zz_60[1] || _zz_61); + assign _zz_63 = (_zz_60[2] || _zz_61); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_219; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_289); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_64 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_64); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_64); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_65 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_67; + assign _zz_67 = ((1'b0 && (! _zz_68)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_68 = _zz_69; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_68; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_70 = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_72; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign _zz_73 = _zz_290[11]; + always @ (*) begin + _zz_74[18] = _zz_73; + _zz_74[17] = _zz_73; + _zz_74[16] = _zz_73; + _zz_74[15] = _zz_73; + _zz_74[14] = _zz_73; + _zz_74[13] = _zz_73; + _zz_74[12] = _zz_73; + _zz_74[11] = _zz_73; + _zz_74[10] = _zz_73; + _zz_74[9] = _zz_73; + _zz_74[8] = _zz_73; + _zz_74[7] = _zz_73; + _zz_74[6] = _zz_73; + _zz_74[5] = _zz_73; + _zz_74[4] = _zz_73; + _zz_74[3] = _zz_73; + _zz_74[2] = _zz_73; + _zz_74[1] = _zz_73; + _zz_74[0] = _zz_73; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_291[31])); + if(_zz_79)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_75 = _zz_292[19]; + always @ (*) begin + _zz_76[10] = _zz_75; + _zz_76[9] = _zz_75; + _zz_76[8] = _zz_75; + _zz_76[7] = _zz_75; + _zz_76[6] = _zz_75; + _zz_76[5] = _zz_75; + _zz_76[4] = _zz_75; + _zz_76[3] = _zz_75; + _zz_76[2] = _zz_75; + _zz_76[1] = _zz_75; + _zz_76[0] = _zz_75; + end + + assign _zz_77 = _zz_293[11]; + always @ (*) begin + _zz_78[18] = _zz_77; + _zz_78[17] = _zz_77; + _zz_78[16] = _zz_77; + _zz_78[15] = _zz_77; + _zz_78[14] = _zz_77; + _zz_78[13] = _zz_77; + _zz_78[12] = _zz_77; + _zz_78[11] = _zz_77; + _zz_78[10] = _zz_77; + _zz_78[9] = _zz_77; + _zz_78[8] = _zz_77; + _zz_78[7] = _zz_77; + _zz_78[6] = _zz_77; + _zz_78[5] = _zz_77; + _zz_78[4] = _zz_77; + _zz_78[3] = _zz_77; + _zz_78[2] = _zz_77; + _zz_78[1] = _zz_77; + _zz_78[0] = _zz_77; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_79 = _zz_294[1]; + end + default : begin + _zz_79 = _zz_295[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_80 = _zz_296[19]; + always @ (*) begin + _zz_81[10] = _zz_80; + _zz_81[9] = _zz_80; + _zz_81[8] = _zz_80; + _zz_81[7] = _zz_80; + _zz_81[6] = _zz_80; + _zz_81[5] = _zz_80; + _zz_81[4] = _zz_80; + _zz_81[3] = _zz_80; + _zz_81[2] = _zz_80; + _zz_81[1] = _zz_80; + _zz_81[0] = _zz_80; + end + + assign _zz_82 = _zz_297[11]; + always @ (*) begin + _zz_83[18] = _zz_82; + _zz_83[17] = _zz_82; + _zz_83[16] = _zz_82; + _zz_83[15] = _zz_82; + _zz_83[14] = _zz_82; + _zz_83[13] = _zz_82; + _zz_83[12] = _zz_82; + _zz_83[11] = _zz_82; + _zz_83[10] = _zz_82; + _zz_83[9] = _zz_82; + _zz_83[8] = _zz_82; + _zz_83[7] = _zz_82; + _zz_83[6] = _zz_82; + _zz_83[5] = _zz_82; + _zz_83[4] = _zz_82; + _zz_83[3] = _zz_82; + _zz_83[2] = _zz_82; + _zz_83[1] = _zz_82; + _zz_83[0] = _zz_82; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_81,{{{_zz_376,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_83,{{{_zz_377,_zz_378},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_190 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_191 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_192 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_191; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_194 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_195 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_196 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_229)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_227)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_197 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_227)begin + _zz_197 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_228)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_226)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_228)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_226)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_189 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_216 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_198 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_199 = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_86 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_86 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_86 = execute_RS2[31 : 0]; + end + endcase + end + + assign _zz_215 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_200 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_201 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_200; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_201; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @ (*) begin + _zz_202 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_202 = 1'b1; + end + end + + assign _zz_203 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_204 = (CsrPlugin_privilege == 2'b00); + assign _zz_205 = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_236)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_236)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_236)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_298}; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_299}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_87 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_88[31] = _zz_87; + _zz_88[30] = _zz_87; + _zz_88[29] = _zz_87; + _zz_88[28] = _zz_87; + _zz_88[27] = _zz_87; + _zz_88[26] = _zz_87; + _zz_88[25] = _zz_87; + _zz_88[24] = _zz_87; + _zz_88[23] = _zz_87; + _zz_88[22] = _zz_87; + _zz_88[21] = _zz_87; + _zz_88[20] = _zz_87; + _zz_88[19] = _zz_87; + _zz_88[18] = _zz_87; + _zz_88[17] = _zz_87; + _zz_88[16] = _zz_87; + _zz_88[15] = _zz_87; + _zz_88[14] = _zz_87; + _zz_88[13] = _zz_87; + _zz_88[12] = _zz_87; + _zz_88[11] = _zz_87; + _zz_88[10] = _zz_87; + _zz_88[9] = _zz_87; + _zz_88[8] = _zz_87; + _zz_88[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_89 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_90[31] = _zz_89; + _zz_90[30] = _zz_89; + _zz_90[29] = _zz_89; + _zz_90[28] = _zz_89; + _zz_90[27] = _zz_89; + _zz_90[26] = _zz_89; + _zz_90[25] = _zz_89; + _zz_90[24] = _zz_89; + _zz_90[23] = _zz_89; + _zz_90[22] = _zz_89; + _zz_90[21] = _zz_89; + _zz_90[20] = _zz_89; + _zz_90[19] = _zz_89; + _zz_90[18] = _zz_89; + _zz_90[17] = _zz_89; + _zz_90[16] = _zz_89; + _zz_90[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_254) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_88; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_90; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_92 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_93 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_94 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_95 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_96 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_91 = {(_zz_96 != 1'b0),{(_zz_96 != 1'b0),{((_zz_379 == _zz_380) != 1'b0),{(_zz_381 != 1'b0),{1'b0,{_zz_382,{_zz_383,_zz_384}}}}}}}; + assign _zz_97 = _zz_91[2 : 1]; + assign _zz_54 = _zz_97; + assign _zz_98 = _zz_91[7 : 6]; + assign _zz_53 = _zz_98; + assign _zz_99 = _zz_91[9 : 8]; + assign _zz_52 = _zz_99; + assign _zz_100 = _zz_91[19 : 18]; + assign _zz_51 = _zz_100; + assign _zz_101 = _zz_91[22 : 21]; + assign _zz_50 = _zz_101; + assign _zz_102 = _zz_91[24 : 23]; + assign _zz_49 = _zz_102; + assign _zz_103 = _zz_91[27 : 26]; + assign _zz_48 = _zz_103; + assign _zz_104 = _zz_91[29 : 29]; + assign _zz_47 = _zz_104; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_217; + assign decode_RegFilePlugin_rs2Data = _zz_218; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); + if(_zz_105)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + assign lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; + assign lastStageRegFileWrite_payload_data = _zz_55; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_106 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_106 = {31'd0, _zz_300}; + end + default : begin + _zz_106 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_107 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_107 = {29'd0, _zz_301}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_107 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_107 = {27'd0, _zz_302}; + end + endcase + end + + assign _zz_108 = _zz_303[11]; + always @ (*) begin + _zz_109[19] = _zz_108; + _zz_109[18] = _zz_108; + _zz_109[17] = _zz_108; + _zz_109[16] = _zz_108; + _zz_109[15] = _zz_108; + _zz_109[14] = _zz_108; + _zz_109[13] = _zz_108; + _zz_109[12] = _zz_108; + _zz_109[11] = _zz_108; + _zz_109[10] = _zz_108; + _zz_109[9] = _zz_108; + _zz_109[8] = _zz_108; + _zz_109[7] = _zz_108; + _zz_109[6] = _zz_108; + _zz_109[5] = _zz_108; + _zz_109[4] = _zz_108; + _zz_109[3] = _zz_108; + _zz_109[2] = _zz_108; + _zz_109[1] = _zz_108; + _zz_109[0] = _zz_108; + end + + assign _zz_110 = _zz_304[11]; + always @ (*) begin + _zz_111[19] = _zz_110; + _zz_111[18] = _zz_110; + _zz_111[17] = _zz_110; + _zz_111[16] = _zz_110; + _zz_111[15] = _zz_110; + _zz_111[14] = _zz_110; + _zz_111[13] = _zz_110; + _zz_111[12] = _zz_110; + _zz_111[11] = _zz_110; + _zz_111[10] = _zz_110; + _zz_111[9] = _zz_110; + _zz_111[8] = _zz_110; + _zz_111[7] = _zz_110; + _zz_111[6] = _zz_110; + _zz_111[5] = _zz_110; + _zz_111[4] = _zz_110; + _zz_111[3] = _zz_110; + _zz_111[2] = _zz_110; + _zz_111[1] = _zz_110; + _zz_111[0] = _zz_110; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_112 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_112 = {_zz_109,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_112 = {_zz_111,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_112 = _zz_39; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_305; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_113[0] = execute_SRC1[31]; + _zz_113[1] = execute_SRC1[30]; + _zz_113[2] = execute_SRC1[29]; + _zz_113[3] = execute_SRC1[28]; + _zz_113[4] = execute_SRC1[27]; + _zz_113[5] = execute_SRC1[26]; + _zz_113[6] = execute_SRC1[25]; + _zz_113[7] = execute_SRC1[24]; + _zz_113[8] = execute_SRC1[23]; + _zz_113[9] = execute_SRC1[22]; + _zz_113[10] = execute_SRC1[21]; + _zz_113[11] = execute_SRC1[20]; + _zz_113[12] = execute_SRC1[19]; + _zz_113[13] = execute_SRC1[18]; + _zz_113[14] = execute_SRC1[17]; + _zz_113[15] = execute_SRC1[16]; + _zz_113[16] = execute_SRC1[15]; + _zz_113[17] = execute_SRC1[14]; + _zz_113[18] = execute_SRC1[13]; + _zz_113[19] = execute_SRC1[12]; + _zz_113[20] = execute_SRC1[11]; + _zz_113[21] = execute_SRC1[10]; + _zz_113[22] = execute_SRC1[9]; + _zz_113[23] = execute_SRC1[8]; + _zz_113[24] = execute_SRC1[7]; + _zz_113[25] = execute_SRC1[6]; + _zz_113[26] = execute_SRC1[5]; + _zz_113[27] = execute_SRC1[4]; + _zz_113[28] = execute_SRC1[3]; + _zz_113[29] = execute_SRC1[2]; + _zz_113[30] = execute_SRC1[1]; + _zz_113[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_113 : execute_SRC1); + always @ (*) begin + _zz_114[0] = memory_SHIFT_RIGHT[31]; + _zz_114[1] = memory_SHIFT_RIGHT[30]; + _zz_114[2] = memory_SHIFT_RIGHT[29]; + _zz_114[3] = memory_SHIFT_RIGHT[28]; + _zz_114[4] = memory_SHIFT_RIGHT[27]; + _zz_114[5] = memory_SHIFT_RIGHT[26]; + _zz_114[6] = memory_SHIFT_RIGHT[25]; + _zz_114[7] = memory_SHIFT_RIGHT[24]; + _zz_114[8] = memory_SHIFT_RIGHT[23]; + _zz_114[9] = memory_SHIFT_RIGHT[22]; + _zz_114[10] = memory_SHIFT_RIGHT[21]; + _zz_114[11] = memory_SHIFT_RIGHT[20]; + _zz_114[12] = memory_SHIFT_RIGHT[19]; + _zz_114[13] = memory_SHIFT_RIGHT[18]; + _zz_114[14] = memory_SHIFT_RIGHT[17]; + _zz_114[15] = memory_SHIFT_RIGHT[16]; + _zz_114[16] = memory_SHIFT_RIGHT[15]; + _zz_114[17] = memory_SHIFT_RIGHT[14]; + _zz_114[18] = memory_SHIFT_RIGHT[13]; + _zz_114[19] = memory_SHIFT_RIGHT[12]; + _zz_114[20] = memory_SHIFT_RIGHT[11]; + _zz_114[21] = memory_SHIFT_RIGHT[10]; + _zz_114[22] = memory_SHIFT_RIGHT[9]; + _zz_114[23] = memory_SHIFT_RIGHT[8]; + _zz_114[24] = memory_SHIFT_RIGHT[7]; + _zz_114[25] = memory_SHIFT_RIGHT[6]; + _zz_114[26] = memory_SHIFT_RIGHT[5]; + _zz_114[27] = memory_SHIFT_RIGHT[4]; + _zz_114[28] = memory_SHIFT_RIGHT[3]; + _zz_114[29] = memory_SHIFT_RIGHT[2]; + _zz_114[30] = memory_SHIFT_RIGHT[1]; + _zz_114[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_115 = 1'b0; + if(_zz_237)begin + if(_zz_238)begin + if(_zz_120)begin + _zz_115 = 1'b1; + end + end + end + if(_zz_239)begin + if(_zz_240)begin + if(_zz_122)begin + _zz_115 = 1'b1; + end + end + end + if(_zz_241)begin + if(_zz_242)begin + if(_zz_124)begin + _zz_115 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_115 = 1'b0; + end + end + + always @ (*) begin + _zz_116 = 1'b0; + if(_zz_237)begin + if(_zz_238)begin + if(_zz_121)begin + _zz_116 = 1'b1; + end + end + end + if(_zz_239)begin + if(_zz_240)begin + if(_zz_123)begin + _zz_116 = 1'b1; + end + end + end + if(_zz_241)begin + if(_zz_242)begin + if(_zz_125)begin + _zz_116 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_116 = 1'b0; + end + end + + assign _zz_120 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_121 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_122 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_123 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_124 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_125 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_126 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_126 == 3'b000)) begin + _zz_127 = execute_BranchPlugin_eq; + end else if((_zz_126 == 3'b001)) begin + _zz_127 = (! execute_BranchPlugin_eq); + end else if((((_zz_126 & 3'b101) == 3'b101))) begin + _zz_127 = (! execute_SRC_LESS); + end else begin + _zz_127 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_128 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_128 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_128 = 1'b1; + end + default : begin + _zz_128 = _zz_127; + end + endcase + end + + assign _zz_129 = _zz_312[11]; + always @ (*) begin + _zz_130[19] = _zz_129; + _zz_130[18] = _zz_129; + _zz_130[17] = _zz_129; + _zz_130[16] = _zz_129; + _zz_130[15] = _zz_129; + _zz_130[14] = _zz_129; + _zz_130[13] = _zz_129; + _zz_130[12] = _zz_129; + _zz_130[11] = _zz_129; + _zz_130[10] = _zz_129; + _zz_130[9] = _zz_129; + _zz_130[8] = _zz_129; + _zz_130[7] = _zz_129; + _zz_130[6] = _zz_129; + _zz_130[5] = _zz_129; + _zz_130[4] = _zz_129; + _zz_130[3] = _zz_129; + _zz_130[2] = _zz_129; + _zz_130[1] = _zz_129; + _zz_130[0] = _zz_129; + end + + assign _zz_131 = _zz_313[19]; + always @ (*) begin + _zz_132[10] = _zz_131; + _zz_132[9] = _zz_131; + _zz_132[8] = _zz_131; + _zz_132[7] = _zz_131; + _zz_132[6] = _zz_131; + _zz_132[5] = _zz_131; + _zz_132[4] = _zz_131; + _zz_132[3] = _zz_131; + _zz_132[2] = _zz_131; + _zz_132[1] = _zz_131; + _zz_132[0] = _zz_131; + end + + assign _zz_133 = _zz_314[11]; + always @ (*) begin + _zz_134[18] = _zz_133; + _zz_134[17] = _zz_133; + _zz_134[16] = _zz_133; + _zz_134[15] = _zz_133; + _zz_134[14] = _zz_133; + _zz_134[13] = _zz_133; + _zz_134[12] = _zz_133; + _zz_134[11] = _zz_133; + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_135 = (_zz_315[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_135 = _zz_316[1]; + end + default : begin + _zz_135 = _zz_317[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_135); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_136 = _zz_318[11]; + always @ (*) begin + _zz_137[19] = _zz_136; + _zz_137[18] = _zz_136; + _zz_137[17] = _zz_136; + _zz_137[16] = _zz_136; + _zz_137[15] = _zz_136; + _zz_137[14] = _zz_136; + _zz_137[13] = _zz_136; + _zz_137[12] = _zz_136; + _zz_137[11] = _zz_136; + _zz_137[10] = _zz_136; + _zz_137[9] = _zz_136; + _zz_137[8] = _zz_136; + _zz_137[7] = _zz_136; + _zz_137[6] = _zz_136; + _zz_137[5] = _zz_136; + _zz_137[4] = _zz_136; + _zz_137[3] = _zz_136; + _zz_137[2] = _zz_136; + _zz_137[1] = _zz_136; + _zz_137[0] = _zz_136; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_137,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_139,{{{_zz_547,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_141,{{{_zz_548,_zz_549},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_321}; + end + end + endcase + end + + assign _zz_138 = _zz_319[19]; + always @ (*) begin + _zz_139[10] = _zz_138; + _zz_139[9] = _zz_138; + _zz_139[8] = _zz_138; + _zz_139[7] = _zz_138; + _zz_139[6] = _zz_138; + _zz_139[5] = _zz_138; + _zz_139[4] = _zz_138; + _zz_139[3] = _zz_138; + _zz_139[2] = _zz_138; + _zz_139[1] = _zz_138; + _zz_139[0] = _zz_138; + end + + assign _zz_140 = _zz_320[11]; + always @ (*) begin + _zz_141[18] = _zz_140; + _zz_141[17] = _zz_140; + _zz_141[16] = _zz_140; + _zz_141[15] = _zz_140; + _zz_141[14] = _zz_140; + _zz_141[13] = _zz_140; + _zz_141[12] = _zz_140; + _zz_141[11] = _zz_140; + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_142 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_143 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_144 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_145 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_146 = _zz_322[0]; + assign _zz_147 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_148 = _zz_324[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_230)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(_zz_232)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_243)begin + CsrPlugin_selfException_valid = 1'b1; + end + if(_zz_244)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_243)begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(_zz_244)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_255) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign execute_CfuPlugin_functionsIds_0 = _zz_326; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_149 = _zz_327[11]; + always @ (*) begin + _zz_150[19] = _zz_149; + _zz_150[18] = _zz_149; + _zz_150[17] = _zz_149; + _zz_150[16] = _zz_149; + _zz_150[15] = _zz_149; + _zz_150[14] = _zz_149; + _zz_150[13] = _zz_149; + _zz_150[12] = _zz_149; + _zz_150[11] = _zz_149; + _zz_150[10] = _zz_149; + _zz_150[9] = _zz_149; + _zz_150[8] = _zz_149; + _zz_150[7] = _zz_149; + _zz_150[6] = _zz_149; + _zz_150[5] = _zz_149; + _zz_150[4] = _zz_149; + _zz_150[3] = _zz_149; + _zz_150[2] = _zz_149; + _zz_150[1] = _zz_149; + _zz_150[0] = _zz_149; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_ENCODING) + `Input2Kind_defaultEncoding_RS : begin + _zz_151 = execute_RS2; + end + default : begin + _zz_151 = {_zz_150,execute_INSTRUCTION[31 : 20]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_151; + assign CfuPlugin_bus_rsp_ready = ((1'b1 && (! memory_CfuPlugin_rsp_valid)) || memory_CfuPlugin_rsp_ready); + assign memory_CfuPlugin_rsp_valid = CfuPlugin_bus_rsp_m2sPipe_rValid; + assign memory_CfuPlugin_rsp_payload_response_ok = CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; + assign memory_CfuPlugin_rsp_payload_outputs_0 = CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0; + always @ (*) begin + CfuPlugin_joinException_valid = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if(memory_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); + end + end + end + + assign CfuPlugin_joinException_payload_code = 4'b1111; + assign CfuPlugin_joinException_payload_badAddr = 32'h0; + always @ (*) begin + memory_CfuPlugin_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_245) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_245) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_328) + $signed(_zz_329)); + assign memory_DivPlugin_frontendOk = 1'b1; + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_225)begin + if(_zz_246)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_247)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_333); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_152 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_152[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_334); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_335 : _zz_336); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_337[31:0]; + assign _zz_153 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_154 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_155 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_156[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_156[31 : 0] = execute_RS1; + end + + assign _zz_158 = (_zz_157 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_158 != 32'h0); + assign _zz_29 = decode_SRC1_CTRL; + assign _zz_27 = _zz_54; + assign _zz_41 = decode_to_execute_SRC1_CTRL; + assign _zz_26 = decode_ALU_CTRL; + assign _zz_24 = _zz_53; + assign _zz_42 = decode_to_execute_ALU_CTRL; + assign _zz_23 = decode_SRC2_CTRL; + assign _zz_21 = _zz_52; + assign _zz_40 = decode_to_execute_SRC2_CTRL; + assign _zz_20 = decode_ALU_BITWISE_CTRL; + assign _zz_18 = _zz_51; + assign _zz_43 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_17 = decode_SHIFT_CTRL; + assign _zz_14 = execute_SHIFT_CTRL; + assign _zz_15 = _zz_50; + assign _zz_38 = decode_to_execute_SHIFT_CTRL; + assign _zz_37 = execute_to_memory_SHIFT_CTRL; + assign _zz_12 = decode_BRANCH_CTRL; + assign _zz_56 = _zz_49; + assign _zz_34 = decode_to_execute_BRANCH_CTRL; + assign _zz_10 = decode_ENV_CTRL; + assign _zz_7 = execute_ENV_CTRL; + assign _zz_5 = memory_ENV_CTRL; + assign _zz_8 = _zz_48; + assign _zz_32 = decode_to_execute_ENV_CTRL; + assign _zz_31 = execute_to_memory_ENV_CTRL; + assign _zz_33 = memory_to_writeBack_ENV_CTRL; + assign _zz_3 = decode_CfuPlugin_CFU_ENCODING; + assign _zz_1 = _zz_47; + assign _zz_30 = decode_to_execute_CfuPlugin_CFU_ENCODING; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_159 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_159[12 : 0] = 13'h1000; + _zz_159[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_160 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_160[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_161 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_161[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_162 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_162[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_163 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_163[31 : 30] = CsrPlugin_misa_base; + _zz_163[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_164 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_164[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_164[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_164[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_165 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_165[11 : 11] = CsrPlugin_mip_MEIP; + _zz_165[7 : 7] = CsrPlugin_mip_MTIP; + _zz_165[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_166 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_166[11 : 11] = CsrPlugin_mie_MEIE; + _zz_166[7 : 7] = CsrPlugin_mie_MTIE; + _zz_166[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_167 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_167[31 : 2] = CsrPlugin_mtvec_base; + _zz_167[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_168 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_168[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_169 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_169[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_170 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_170[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_170[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_171 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_171[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_172 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_172[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_173 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_173[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_174 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_174[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_175 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_175[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_176 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_176[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_177[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_178[31 : 0] = _zz_157; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_179[31 : 0] = _zz_158; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_159 | _zz_160) | (_zz_161 | _zz_162)) | ((_zz_550 | _zz_163) | (_zz_164 | _zz_165))) | (((_zz_166 | _zz_167) | (_zz_168 | _zz_169)) | ((_zz_170 | _zz_171) | (_zz_172 | _zz_173)))) | (((_zz_174 | _zz_175) | (_zz_176 | _zz_177)) | (_zz_178 | _zz_179))); + assign iBusWishbone_ADR = {_zz_354,_zz_180}; + assign iBusWishbone_CTI = ((_zz_180 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'h0; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_248)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_248)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_181; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_187 = (dBus_cmd_payload_length != 3'b000); + assign _zz_183 = dBus_cmd_valid; + assign _zz_185 = dBus_cmd_payload_wr; + assign _zz_186 = (_zz_182 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_184 && (_zz_185 || _zz_186)); + assign dBusWishbone_ADR = ((_zz_187 ? {{dBus_cmd_payload_address[31 : 5],_zz_182},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_187 ? (_zz_186 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_185 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_185; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_184 = (_zz_183 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_183; + assign dBusWishbone_STB = _zz_183; + assign dBus_rsp_valid = _zz_188; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_69 <= 1'b0; + _zz_71 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_84; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_85; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_105 <= 1'b1; + _zz_117 <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_CfuPlugin_hold <= 1'b0; + execute_CfuPlugin_fired <= 1'b0; + CfuPlugin_bus_rsp_m2sPipe_rValid <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_157 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; + memory_to_writeBack_INSTRUCTION <= 32'h0; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; + _zz_180 <= 3'b000; + _zz_181 <= 1'b0; + _zz_182 <= 3'b000; + _zz_188 <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_69 <= 1'b0; + end + if(_zz_67)begin + _zz_69 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_71 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(_zz_249)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_105 <= 1'b0; + _zz_117 <= (_zz_45 && writeBack_arbitration_isFiring); + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_250)begin + if(_zz_251)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_252)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_253)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_233)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_234)begin + case(_zz_235) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_144,{_zz_143,_zz_142}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(execute_CfuPlugin_schedule)begin + execute_CfuPlugin_hold <= 1'b1; + end + if(CfuPlugin_bus_cmd_ready)begin + execute_CfuPlugin_hold <= 1'b0; + end + if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + execute_CfuPlugin_fired <= 1'b1; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_CfuPlugin_fired <= 1'b0; + end + if(CfuPlugin_bus_rsp_ready)begin + CfuPlugin_bus_rsp_m2sPipe_rValid <= CfuPlugin_bus_rsp_valid; + end + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_36; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= execute_CfuPlugin_CFU_IN_FLIGHT; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_347[0]; + CsrPlugin_mstatus_MIE <= _zz_348[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_350[0]; + CsrPlugin_mie_MTIE <= _zz_351[0]; + CsrPlugin_mie_MSIE <= _zz_352[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_248)begin + if(iBusWishbone_ACK)begin + _zz_180 <= (_zz_180 + 3'b001); + end + end + _zz_181 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_183 && _zz_184))begin + _zz_182 <= (_zz_182 + 3'b001); + if(_zz_186)begin + _zz_182 <= 3'b000; + end + end + _zz_188 <= ((_zz_183 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_72 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_249)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + _zz_118 <= _zz_44[11 : 7]; + _zz_119 <= _zz_55; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_230)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_146 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_146 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(_zz_232)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_250)begin + if(_zz_251)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_252)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_253)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_233)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(CfuPlugin_bus_rsp_ready)begin + CfuPlugin_bus_rsp_m2sPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_225)begin + if(_zz_246)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_338[31:0]; + end + end + end + if(_zz_247)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_155 ? (~ _zz_156) : _zz_156) + _zz_344); + memory_DivPlugin_rs2 <= ((_zz_154 ? (~ execute_RS2) : execute_RS2) + _zz_346); + memory_DivPlugin_div_needRevert <= ((_zz_155 ^ (_zz_154 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_39; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_58; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_57; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_28; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_16; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_13; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENCODING <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_35; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_349[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_353[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if(loader_valid)begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9) != 1'b0); + end + end + + assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_9; + reg [21:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [21:0] _zz_15; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_11 = (! lineLoader_flushCounter[7]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_12)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.yaml new file mode 100644 index 0000000..cf27a68 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.yaml @@ -0,0 +1,4 @@ +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v new file mode 100644 index 0000000..a2b21bb --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -0,0 +1,6802 @@ +// Generator : SpinalHDL v1.4.2 git head : 654057b2f5cec0f9fc99487dff67861f76fcbe7e +// Component : VexRiscv +// Git hash : 654057b2f5cec0f9fc99487dff67861f76fcbe7e + + +`define Input2Kind_defaultEncoding_type [0:0] +`define Input2Kind_defaultEncoding_RS 1'b0 +`define Input2Kind_defaultEncoding_IMM_I 1'b1 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [2:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input CfuPlugin_bus_rsp_payload_response_ok, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_192; + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + reg _zz_200; + wire _zz_201; + wire [31:0] _zz_202; + wire _zz_203; + wire [31:0] _zz_204; + reg _zz_205; + wire _zz_206; + wire _zz_207; + wire [31:0] _zz_208; + wire _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire [3:0] _zz_217; + wire _zz_218; + wire _zz_219; + reg [31:0] _zz_220; + reg [31:0] _zz_221; + reg [31:0] _zz_222; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_223; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire [1:0] _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire _zz_245; + wire _zz_246; + wire _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire [1:0] _zz_251; + wire _zz_252; + wire _zz_253; + wire [5:0] _zz_254; + wire _zz_255; + wire _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire [1:0] _zz_261; + wire _zz_262; + wire [1:0] _zz_263; + wire [51:0] _zz_264; + wire [51:0] _zz_265; + wire [51:0] _zz_266; + wire [32:0] _zz_267; + wire [51:0] _zz_268; + wire [49:0] _zz_269; + wire [51:0] _zz_270; + wire [49:0] _zz_271; + wire [51:0] _zz_272; + wire [32:0] _zz_273; + wire [31:0] _zz_274; + wire [32:0] _zz_275; + wire [0:0] _zz_276; + wire [0:0] _zz_277; + wire [0:0] _zz_278; + wire [0:0] _zz_279; + wire [0:0] _zz_280; + wire [0:0] _zz_281; + wire [0:0] _zz_282; + wire [0:0] _zz_283; + wire [0:0] _zz_284; + wire [0:0] _zz_285; + wire [0:0] _zz_286; + wire [0:0] _zz_287; + wire [0:0] _zz_288; + wire [0:0] _zz_289; + wire [0:0] _zz_290; + wire [0:0] _zz_291; + wire [0:0] _zz_292; + wire [0:0] _zz_293; + wire [0:0] _zz_294; + wire [3:0] _zz_295; + wire [2:0] _zz_296; + wire [31:0] _zz_297; + wire [11:0] _zz_298; + wire [31:0] _zz_299; + wire [19:0] _zz_300; + wire [11:0] _zz_301; + wire [31:0] _zz_302; + wire [31:0] _zz_303; + wire [19:0] _zz_304; + wire [11:0] _zz_305; + wire [2:0] _zz_306; + wire [2:0] _zz_307; + wire [0:0] _zz_308; + wire [2:0] _zz_309; + wire [4:0] _zz_310; + wire [11:0] _zz_311; + wire [11:0] _zz_312; + wire [31:0] _zz_313; + wire [31:0] _zz_314; + wire [31:0] _zz_315; + wire [31:0] _zz_316; + wire [31:0] _zz_317; + wire [31:0] _zz_318; + wire [31:0] _zz_319; + wire [11:0] _zz_320; + wire [19:0] _zz_321; + wire [11:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [11:0] _zz_326; + wire [19:0] _zz_327; + wire [11:0] _zz_328; + wire [2:0] _zz_329; + wire [1:0] _zz_330; + wire [1:0] _zz_331; + wire [1:0] _zz_332; + wire [1:0] _zz_333; + wire [2:0] _zz_334; + wire [11:0] _zz_335; + wire [65:0] _zz_336; + wire [65:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [0:0] _zz_340; + wire [5:0] _zz_341; + wire [32:0] _zz_342; + wire [31:0] _zz_343; + wire [31:0] _zz_344; + wire [32:0] _zz_345; + wire [32:0] _zz_346; + wire [32:0] _zz_347; + wire [32:0] _zz_348; + wire [0:0] _zz_349; + wire [32:0] _zz_350; + wire [0:0] _zz_351; + wire [32:0] _zz_352; + wire [0:0] _zz_353; + wire [31:0] _zz_354; + wire [0:0] _zz_355; + wire [0:0] _zz_356; + wire [0:0] _zz_357; + wire [0:0] _zz_358; + wire [0:0] _zz_359; + wire [0:0] _zz_360; + wire [0:0] _zz_361; + wire [26:0] _zz_362; + wire _zz_363; + wire _zz_364; + wire [1:0] _zz_365; + wire [31:0] _zz_366; + wire [31:0] _zz_367; + wire [31:0] _zz_368; + wire _zz_369; + wire [0:0] _zz_370; + wire [14:0] _zz_371; + wire [31:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; + wire _zz_375; + wire [0:0] _zz_376; + wire [8:0] _zz_377; + wire [31:0] _zz_378; + wire [31:0] _zz_379; + wire [31:0] _zz_380; + wire _zz_381; + wire [0:0] _zz_382; + wire [2:0] _zz_383; + wire _zz_384; + wire _zz_385; + wire _zz_386; + wire [31:0] _zz_387; + wire [0:0] _zz_388; + wire [0:0] _zz_389; + wire _zz_390; + wire [0:0] _zz_391; + wire [28:0] _zz_392; + wire [0:0] _zz_393; + wire [0:0] _zz_394; + wire [0:0] _zz_395; + wire [0:0] _zz_396; + wire _zz_397; + wire [0:0] _zz_398; + wire [23:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; + wire [31:0] _zz_402; + wire _zz_403; + wire _zz_404; + wire [0:0] _zz_405; + wire [0:0] _zz_406; + wire [0:0] _zz_407; + wire [0:0] _zz_408; + wire _zz_409; + wire [0:0] _zz_410; + wire [20:0] _zz_411; + wire [31:0] _zz_412; + wire [31:0] _zz_413; + wire _zz_414; + wire _zz_415; + wire [0:0] _zz_416; + wire [1:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire _zz_420; + wire [0:0] _zz_421; + wire [17:0] _zz_422; + wire [31:0] _zz_423; + wire [31:0] _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire [31:0] _zz_427; + wire [31:0] _zz_428; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire _zz_431; + wire [1:0] _zz_432; + wire [1:0] _zz_433; + wire _zz_434; + wire [0:0] _zz_435; + wire [14:0] _zz_436; + wire [31:0] _zz_437; + wire [31:0] _zz_438; + wire [31:0] _zz_439; + wire [31:0] _zz_440; + wire [31:0] _zz_441; + wire [31:0] _zz_442; + wire [0:0] _zz_443; + wire [1:0] _zz_444; + wire [4:0] _zz_445; + wire [4:0] _zz_446; + wire _zz_447; + wire [0:0] _zz_448; + wire [11:0] _zz_449; + wire [31:0] _zz_450; + wire [31:0] _zz_451; + wire [31:0] _zz_452; + wire [31:0] _zz_453; + wire [31:0] _zz_454; + wire [31:0] _zz_455; + wire _zz_456; + wire [0:0] _zz_457; + wire [1:0] _zz_458; + wire [31:0] _zz_459; + wire [31:0] _zz_460; + wire [0:0] _zz_461; + wire [4:0] _zz_462; + wire [4:0] _zz_463; + wire [4:0] _zz_464; + wire _zz_465; + wire [0:0] _zz_466; + wire [8:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire _zz_471; + wire _zz_472; + wire [31:0] _zz_473; + wire [31:0] _zz_474; + wire _zz_475; + wire [0:0] _zz_476; + wire [2:0] _zz_477; + wire [0:0] _zz_478; + wire [2:0] _zz_479; + wire [0:0] _zz_480; + wire [4:0] _zz_481; + wire [1:0] _zz_482; + wire [1:0] _zz_483; + wire _zz_484; + wire [0:0] _zz_485; + wire [6:0] _zz_486; + wire [31:0] _zz_487; + wire [31:0] _zz_488; + wire [31:0] _zz_489; + wire _zz_490; + wire [0:0] _zz_491; + wire [0:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire _zz_495; + wire [0:0] _zz_496; + wire [0:0] _zz_497; + wire _zz_498; + wire [0:0] _zz_499; + wire [2:0] _zz_500; + wire _zz_501; + wire [0:0] _zz_502; + wire [0:0] _zz_503; + wire [0:0] _zz_504; + wire [0:0] _zz_505; + wire _zz_506; + wire [0:0] _zz_507; + wire [4:0] _zz_508; + wire [31:0] _zz_509; + wire [31:0] _zz_510; + wire [31:0] _zz_511; + wire [31:0] _zz_512; + wire [31:0] _zz_513; + wire [31:0] _zz_514; + wire [31:0] _zz_515; + wire [31:0] _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire [31:0] _zz_520; + wire [31:0] _zz_521; + wire _zz_522; + wire [0:0] _zz_523; + wire [0:0] _zz_524; + wire [31:0] _zz_525; + wire [31:0] _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; + wire [31:0] _zz_529; + wire _zz_530; + wire [3:0] _zz_531; + wire [3:0] _zz_532; + wire _zz_533; + wire [0:0] _zz_534; + wire [2:0] _zz_535; + wire [31:0] _zz_536; + wire [31:0] _zz_537; + wire [31:0] _zz_538; + wire [31:0] _zz_539; + wire [31:0] _zz_540; + wire [31:0] _zz_541; + wire _zz_542; + wire [0:0] _zz_543; + wire [1:0] _zz_544; + wire _zz_545; + wire [2:0] _zz_546; + wire [2:0] _zz_547; + wire _zz_548; + wire [0:0] _zz_549; + wire [0:0] _zz_550; + wire [31:0] _zz_551; + wire [31:0] _zz_552; + wire [31:0] _zz_553; + wire [31:0] _zz_554; + wire [31:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire _zz_558; + wire _zz_559; + wire _zz_560; + wire [0:0] _zz_561; + wire [0:0] _zz_562; + wire _zz_563; + wire _zz_564; + wire _zz_565; + wire _zz_566; + wire [31:0] _zz_567; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_ENCODING; + wire `Input2Kind_defaultEncoding_type _zz_1; + wire `Input2Kind_defaultEncoding_type _zz_2; + wire `Input2Kind_defaultEncoding_type _zz_3; + wire decode_CfuPlugin_CFU_ENABLE; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `AluCtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_ENCODING; + wire `Input2Kind_defaultEncoding_type _zz_30; + wire execute_CfuPlugin_CFU_ENABLE; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_31; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_32; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_34; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_35; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_36; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_37; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_38; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_39; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_40; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_41; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_42; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_44; + wire _zz_45; + reg _zz_46; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `Input2Kind_defaultEncoding_type _zz_47; + wire `EnvCtrlEnum_defaultEncoding_type _zz_48; + wire `BranchCtrlEnum_defaultEncoding_type _zz_49; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_50; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_51; + wire `Src2CtrlEnum_defaultEncoding_type _zz_52; + wire `AluCtrlEnum_defaultEncoding_type _zz_53; + wire `Src1CtrlEnum_defaultEncoding_type _zz_54; + reg [31:0] _zz_55; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_56; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_57; + reg [31:0] _zz_58; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_59; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CfuPlugin_joinException_valid; + wire [3:0] CfuPlugin_joinException_payload_code; + wire [31:0] CfuPlugin_joinException_payload_badAddr; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_60; + wire [3:0] _zz_61; + wire _zz_62; + wire _zz_63; + wire _zz_64; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_65; + wire _zz_66; + wire _zz_67; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_68; + wire _zz_69; + reg _zz_70; + wire _zz_71; + reg _zz_72; + reg [31:0] _zz_73; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_74; + reg [18:0] _zz_75; + wire _zz_76; + reg [10:0] _zz_77; + wire _zz_78; + reg [18:0] _zz_79; + reg _zz_80; + wire _zz_81; + reg [10:0] _zz_82; + wire _zz_83; + reg [18:0] _zz_84; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_85; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_86; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_87; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_88; + reg [31:0] _zz_89; + wire _zz_90; + reg [31:0] _zz_91; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [34:0] _zz_92; + wire _zz_93; + wire _zz_94; + wire _zz_95; + wire _zz_96; + wire _zz_97; + wire `Src1CtrlEnum_defaultEncoding_type _zz_98; + wire `AluCtrlEnum_defaultEncoding_type _zz_99; + wire `Src2CtrlEnum_defaultEncoding_type _zz_100; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_101; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_102; + wire `BranchCtrlEnum_defaultEncoding_type _zz_103; + wire `EnvCtrlEnum_defaultEncoding_type _zz_104; + wire `Input2Kind_defaultEncoding_type _zz_105; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_106; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_107; + reg [31:0] _zz_108; + wire _zz_109; + reg [19:0] _zz_110; + wire _zz_111; + reg [19:0] _zz_112; + reg [31:0] _zz_113; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_114; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_115; + reg _zz_116; + reg _zz_117; + reg _zz_118; + reg [4:0] _zz_119; + reg [31:0] _zz_120; + wire _zz_121; + wire _zz_122; + wire _zz_123; + wire _zz_124; + wire _zz_125; + wire _zz_126; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_127; + reg _zz_128; + reg _zz_129; + wire _zz_130; + reg [19:0] _zz_131; + wire _zz_132; + reg [10:0] _zz_133; + wire _zz_134; + reg [18:0] _zz_135; + reg _zz_136; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_137; + reg [19:0] _zz_138; + wire _zz_139; + reg [10:0] _zz_140; + wire _zz_141; + reg [18:0] _zz_142; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_143; + wire _zz_144; + wire _zz_145; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_146; + wire _zz_147; + wire [1:0] _zz_148; + wire _zz_149; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire [2:0] execute_CfuPlugin_functionsIds_0; + wire _zz_150; + reg [19:0] _zz_151; + reg [31:0] _zz_152; + wire memory_CfuPlugin_rsp_valid; + reg memory_CfuPlugin_rsp_ready; + wire memory_CfuPlugin_rsp_payload_response_ok; + wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_m2sPipe_rValid; + reg CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_153; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_154; + wire _zz_155; + wire _zz_156; + reg [32:0] _zz_157; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_158; + wire [31:0] _zz_159; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_160; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_ENCODING; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_161; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [2:0] _zz_183; + reg _zz_184; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_185; + wire _zz_186; + wire _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + reg _zz_191; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [39:0] _zz_10_string; + reg [31:0] _zz_11_string; + reg [31:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [71:0] _zz_17_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [39:0] _zz_20_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [23:0] _zz_23_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [63:0] _zz_26_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [95:0] _zz_29_string; + reg [39:0] execute_CfuPlugin_CFU_ENCODING_string; + reg [39:0] _zz_30_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_31_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_32_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_33_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_34_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_37_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_38_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_40_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_41_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_42_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_43_string; + reg [39:0] _zz_47_string; + reg [39:0] _zz_48_string; + reg [31:0] _zz_49_string; + reg [71:0] _zz_50_string; + reg [39:0] _zz_51_string; + reg [23:0] _zz_52_string; + reg [63:0] _zz_53_string; + reg [95:0] _zz_54_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_56_string; + reg [95:0] _zz_98_string; + reg [63:0] _zz_99_string; + reg [23:0] _zz_100_string; + reg [39:0] _zz_101_string; + reg [71:0] _zz_102_string; + reg [31:0] _zz_103_string; + reg [39:0] _zz_104_string; + reg [39:0] _zz_105_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_ENCODING_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_223 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_224 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_225 = 1'b1; + assign _zz_226 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_227 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_228 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_229 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_230 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_231 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_232 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_233 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_234 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_235 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_236 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_237 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_238 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_239 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_240 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_241 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_242 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_243 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_244 = (1'b0 || (! 1'b1)); + assign _zz_245 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_246 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_247 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_248 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_249 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_250 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_251 = execute_INSTRUCTION[13 : 12]; + assign _zz_252 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_253 = (! memory_arbitration_isStuck); + assign _zz_254 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_255 = (iBus_cmd_valid || (_zz_183 != 3'b000)); + assign _zz_256 = (_zz_219 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_257 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_258 = ((_zz_143 && 1'b1) && (! 1'b0)); + assign _zz_259 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_260 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_261 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_262 = execute_INSTRUCTION[13]; + assign _zz_263 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_264 = ($signed(_zz_265) + $signed(_zz_270)); + assign _zz_265 = ($signed(_zz_266) + $signed(_zz_268)); + assign _zz_266 = 52'h0; + assign _zz_267 = {1'b0,memory_MUL_LL}; + assign _zz_268 = {{19{_zz_267[32]}}, _zz_267}; + assign _zz_269 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_270 = {{2{_zz_269[49]}}, _zz_269}; + assign _zz_271 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_272 = {{2{_zz_271[49]}}, _zz_271}; + assign _zz_273 = ($signed(_zz_275) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_274 = _zz_273[31 : 0]; + assign _zz_275 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_276 = _zz_92[33 : 33]; + assign _zz_277 = _zz_92[32 : 32]; + assign _zz_278 = _zz_92[31 : 31]; + assign _zz_279 = _zz_92[30 : 30]; + assign _zz_280 = _zz_92[28 : 28]; + assign _zz_281 = _zz_92[25 : 25]; + assign _zz_282 = _zz_92[17 : 17]; + assign _zz_283 = _zz_92[16 : 16]; + assign _zz_284 = _zz_92[13 : 13]; + assign _zz_285 = _zz_92[12 : 12]; + assign _zz_286 = _zz_92[11 : 11]; + assign _zz_287 = _zz_92[34 : 34]; + assign _zz_288 = _zz_92[15 : 15]; + assign _zz_289 = _zz_92[5 : 5]; + assign _zz_290 = _zz_92[3 : 3]; + assign _zz_291 = _zz_92[20 : 20]; + assign _zz_292 = _zz_92[10 : 10]; + assign _zz_293 = _zz_92[4 : 4]; + assign _zz_294 = _zz_92[0 : 0]; + assign _zz_295 = (_zz_60 - 4'b0001); + assign _zz_296 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_297 = {29'd0, _zz_296}; + assign _zz_298 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_299 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_300 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_301 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_302 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_303 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_304 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_305 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_306 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_307 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_308 = execute_SRC_LESS; + assign _zz_309 = 3'b100; + assign _zz_310 = execute_INSTRUCTION[19 : 15]; + assign _zz_311 = execute_INSTRUCTION[31 : 20]; + assign _zz_312 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_313 = ($signed(_zz_314) + $signed(_zz_317)); + assign _zz_314 = ($signed(_zz_315) + $signed(_zz_316)); + assign _zz_315 = execute_SRC1; + assign _zz_316 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_317 = (execute_SRC_USE_SUB_LESS ? _zz_318 : _zz_319); + assign _zz_318 = 32'h00000001; + assign _zz_319 = 32'h0; + assign _zz_320 = execute_INSTRUCTION[31 : 20]; + assign _zz_321 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_322 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_323 = {_zz_131,execute_INSTRUCTION[31 : 20]}; + assign _zz_324 = {{_zz_133,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_325 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_326 = execute_INSTRUCTION[31 : 20]; + assign _zz_327 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_329 = 3'b100; + assign _zz_330 = (_zz_146 & (~ _zz_331)); + assign _zz_331 = (_zz_146 - 2'b01); + assign _zz_332 = (_zz_148 & (~ _zz_333)); + assign _zz_333 = (_zz_148 - 2'b01); + assign _zz_334 = execute_INSTRUCTION[14 : 12]; + assign _zz_335 = execute_INSTRUCTION[31 : 20]; + assign _zz_336 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_337 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_338 = writeBack_MUL_LOW[31 : 0]; + assign _zz_339 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_340 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_341 = {5'd0, _zz_340}; + assign _zz_342 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_343 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_344 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_345 = {_zz_153,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_346 = _zz_347; + assign _zz_347 = _zz_348; + assign _zz_348 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_154) : _zz_154)} + _zz_350); + assign _zz_349 = memory_DivPlugin_div_needRevert; + assign _zz_350 = {32'd0, _zz_349}; + assign _zz_351 = _zz_156; + assign _zz_352 = {32'd0, _zz_351}; + assign _zz_353 = _zz_155; + assign _zz_354 = {31'd0, _zz_353}; + assign _zz_355 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_356 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_357 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_358 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_359 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_360 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_361 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_362 = (iBus_cmd_payload_address >>> 5); + assign _zz_363 = 1'b1; + assign _zz_364 = 1'b1; + assign _zz_365 = {_zz_64,_zz_63}; + assign _zz_366 = 32'h0000106f; + assign _zz_367 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_368 = 32'h00001073; + assign _zz_369 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_370 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_371 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_372) == 32'h00000003),{(_zz_373 == _zz_374),{_zz_375,{_zz_376,_zz_377}}}}}}; + assign _zz_372 = 32'h0000207f; + assign _zz_373 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_374 = 32'h00000003; + assign _zz_375 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_376 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_377 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_378) == 32'h00005013),{(_zz_379 == _zz_380),{_zz_381,{_zz_382,_zz_383}}}}}}; + assign _zz_378 = 32'hbc00707f; + assign _zz_379 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_380 = 32'h00001013; + assign _zz_381 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_382 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_383 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_384 = decode_INSTRUCTION[31]; + assign _zz_385 = decode_INSTRUCTION[31]; + assign _zz_386 = decode_INSTRUCTION[7]; + assign _zz_387 = 32'h10103050; + assign _zz_388 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_389 = 1'b0; + assign _zz_390 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_391 = 1'b0; + assign _zz_392 = {(_zz_96 != 1'b0),{({_zz_393,_zz_394} != 2'b00),{(_zz_395 != _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}; + assign _zz_393 = ((decode_INSTRUCTION & _zz_400) == 32'h10000050); + assign _zz_394 = ((decode_INSTRUCTION & _zz_401) == 32'h00000050); + assign _zz_395 = ((decode_INSTRUCTION & _zz_402) == 32'h00000050); + assign _zz_396 = 1'b0; + assign _zz_397 = ({_zz_403,_zz_404} != 2'b00); + assign _zz_398 = ({_zz_405,_zz_406} != 2'b00); + assign _zz_399 = {(_zz_407 != _zz_408),{_zz_409,{_zz_410,_zz_411}}}; + assign _zz_400 = 32'h10203050; + assign _zz_401 = 32'h10103050; + assign _zz_402 = 32'h00103050; + assign _zz_403 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_404 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_405 = _zz_95; + assign _zz_406 = ((decode_INSTRUCTION & _zz_412) == 32'h00000004); + assign _zz_407 = ((decode_INSTRUCTION & _zz_413) == 32'h00000040); + assign _zz_408 = 1'b0; + assign _zz_409 = ({_zz_414,_zz_415} != 2'b00); + assign _zz_410 = ({_zz_416,_zz_417} != 3'b000); + assign _zz_411 = {(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}; + assign _zz_412 = 32'h0000001c; + assign _zz_413 = 32'h00000058; + assign _zz_414 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_415 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_416 = ((decode_INSTRUCTION & _zz_423) == 32'h40001010); + assign _zz_417 = {(_zz_424 == _zz_425),(_zz_426 == _zz_427)}; + assign _zz_418 = ((decode_INSTRUCTION & _zz_428) == 32'h00000024); + assign _zz_419 = 1'b0; + assign _zz_420 = ((_zz_429 == _zz_430) != 1'b0); + assign _zz_421 = (_zz_431 != 1'b0); + assign _zz_422 = {(_zz_432 != _zz_433),{_zz_434,{_zz_435,_zz_436}}}; + assign _zz_423 = 32'h40003054; + assign _zz_424 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_425 = 32'h00001010; + assign _zz_426 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_427 = 32'h00001010; + assign _zz_428 = 32'h00000064; + assign _zz_429 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_430 = 32'h00001000; + assign _zz_431 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_432 = {(_zz_437 == _zz_438),(_zz_439 == _zz_440)}; + assign _zz_433 = 2'b00; + assign _zz_434 = ((_zz_441 == _zz_442) != 1'b0); + assign _zz_435 = ({_zz_443,_zz_444} != 3'b000); + assign _zz_436 = {(_zz_445 != _zz_446),{_zz_447,{_zz_448,_zz_449}}}; + assign _zz_437 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_438 = 32'h00002000; + assign _zz_439 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_440 = 32'h00001000; + assign _zz_441 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_442 = 32'h00004004; + assign _zz_443 = _zz_96; + assign _zz_444 = {(_zz_450 == _zz_451),(_zz_452 == _zz_453)}; + assign _zz_445 = {(_zz_454 == _zz_455),{_zz_456,{_zz_457,_zz_458}}}; + assign _zz_446 = 5'h0; + assign _zz_447 = ((_zz_459 == _zz_460) != 1'b0); + assign _zz_448 = ({_zz_461,_zz_462} != 6'h0); + assign _zz_449 = {(_zz_463 != _zz_464),{_zz_465,{_zz_466,_zz_467}}}; + assign _zz_450 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_451 = 32'h00000020; + assign _zz_452 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_453 = 32'h00000020; + assign _zz_454 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_455 = 32'h00002040; + assign _zz_456 = ((decode_INSTRUCTION & _zz_468) == 32'h00001040); + assign _zz_457 = (_zz_469 == _zz_470); + assign _zz_458 = {_zz_471,_zz_472}; + assign _zz_459 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_460 = 32'h00000020; + assign _zz_461 = (_zz_473 == _zz_474); + assign _zz_462 = {_zz_475,{_zz_476,_zz_477}}; + assign _zz_463 = {_zz_94,{_zz_478,_zz_479}}; + assign _zz_464 = 5'h0; + assign _zz_465 = ({_zz_480,_zz_481} != 6'h0); + assign _zz_466 = (_zz_482 != _zz_483); + assign _zz_467 = {_zz_484,{_zz_485,_zz_486}}; + assign _zz_468 = 32'h00001040; + assign _zz_469 = (decode_INSTRUCTION & 32'h00100040); + assign _zz_470 = 32'h00000040; + assign _zz_471 = ((decode_INSTRUCTION & _zz_487) == 32'h00000040); + assign _zz_472 = ((decode_INSTRUCTION & _zz_488) == 32'h0); + assign _zz_473 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_474 = 32'h00000008; + assign _zz_475 = ((decode_INSTRUCTION & _zz_489) == 32'h00000040); + assign _zz_476 = _zz_94; + assign _zz_477 = {_zz_490,{_zz_491,_zz_492}}; + assign _zz_478 = (_zz_493 == _zz_494); + assign _zz_479 = {_zz_495,{_zz_496,_zz_497}}; + assign _zz_480 = _zz_95; + assign _zz_481 = {_zz_498,{_zz_499,_zz_500}}; + assign _zz_482 = {_zz_94,_zz_501}; + assign _zz_483 = 2'b00; + assign _zz_484 = ({_zz_502,_zz_503} != 2'b00); + assign _zz_485 = (_zz_504 != _zz_505); + assign _zz_486 = {_zz_506,{_zz_507,_zz_508}}; + assign _zz_487 = 32'h00000050; + assign _zz_488 = 32'h00000038; + assign _zz_489 = 32'h00000040; + assign _zz_490 = ((decode_INSTRUCTION & _zz_509) == 32'h00004020); + assign _zz_491 = (_zz_510 == _zz_511); + assign _zz_492 = (_zz_512 == _zz_513); + assign _zz_493 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_494 = 32'h00002010; + assign _zz_495 = ((decode_INSTRUCTION & _zz_514) == 32'h00000010); + assign _zz_496 = (_zz_515 == _zz_516); + assign _zz_497 = (_zz_517 == _zz_518); + assign _zz_498 = ((decode_INSTRUCTION & _zz_519) == 32'h00001010); + assign _zz_499 = (_zz_520 == _zz_521); + assign _zz_500 = {_zz_522,{_zz_523,_zz_524}}; + assign _zz_501 = ((decode_INSTRUCTION & _zz_525) == 32'h00000020); + assign _zz_502 = _zz_94; + assign _zz_503 = (_zz_526 == _zz_527); + assign _zz_504 = (_zz_528 == _zz_529); + assign _zz_505 = 1'b0; + assign _zz_506 = (_zz_530 != 1'b0); + assign _zz_507 = (_zz_531 != _zz_532); + assign _zz_508 = {_zz_533,{_zz_534,_zz_535}}; + assign _zz_509 = 32'h00004020; + assign _zz_510 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_511 = 32'h00000010; + assign _zz_512 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_513 = 32'h00000020; + assign _zz_514 = 32'h00001030; + assign _zz_515 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_516 = 32'h00002020; + assign _zz_517 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_518 = 32'h00000020; + assign _zz_519 = 32'h00001010; + assign _zz_520 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_521 = 32'h00002010; + assign _zz_522 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); + assign _zz_523 = (_zz_537 == _zz_538); + assign _zz_524 = (_zz_539 == _zz_540); + assign _zz_525 = 32'h00000070; + assign _zz_526 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_527 = 32'h0; + assign _zz_528 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_529 = 32'h00004010; + assign _zz_530 = ((decode_INSTRUCTION & _zz_541) == 32'h00002010); + assign _zz_531 = {_zz_542,{_zz_543,_zz_544}}; + assign _zz_532 = 4'b0000; + assign _zz_533 = (_zz_545 != 1'b0); + assign _zz_534 = (_zz_546 != _zz_547); + assign _zz_535 = {_zz_548,{_zz_549,_zz_550}}; + assign _zz_536 = 32'h00000050; + assign _zz_537 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_538 = 32'h00000004; + assign _zz_539 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_540 = 32'h0; + assign _zz_541 = 32'h00006014; + assign _zz_542 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_543 = ((decode_INSTRUCTION & _zz_551) == 32'h0); + assign _zz_544 = {(_zz_552 == _zz_553),(_zz_554 == _zz_555)}; + assign _zz_545 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_546 = {(_zz_556 == _zz_557),{_zz_558,_zz_559}}; + assign _zz_547 = 3'b000; + assign _zz_548 = ({_zz_560,_zz_93} != 2'b00); + assign _zz_549 = ({_zz_561,_zz_562} != 2'b00); + assign _zz_550 = (_zz_563 != 1'b0); + assign _zz_551 = 32'h00000018; + assign _zz_552 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_553 = 32'h00002000; + assign _zz_554 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_555 = 32'h00001000; + assign _zz_556 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_557 = 32'h00000040; + assign _zz_558 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_559 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_560 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_561 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_562 = _zz_93; + assign _zz_563 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_564 = execute_INSTRUCTION[31]; + assign _zz_565 = execute_INSTRUCTION[31]; + assign _zz_566 = execute_INSTRUCTION[7]; + assign _zz_567 = 32'h0; + always @ (posedge clk) begin + if(_zz_363) begin + _zz_220 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_364) begin + _zz_221 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_46) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_192 ), //i + .io_cpu_prefetch_isValid (_zz_193 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_194 ), //i + .io_cpu_fetch_isStuck (_zz_195 ), //i + .io_cpu_fetch_isRemoved (_zz_196 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_197 ), //i + .io_cpu_decode_isStuck (_zz_198 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_199 ), //i + .io_cpu_fill_valid (_zz_200 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_9 (_zz_161[2:0] ), //i + ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_201 ), //i + .io_cpu_execute_address (_zz_202[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_87[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_memory_isValid (_zz_203 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_204[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_205 ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_206 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_207 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_208[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_209 ), //i + .io_cpu_writeBack_fence_SR (_zz_210 ), //i + .io_cpu_writeBack_fence_SO (_zz_211 ), //i + .io_cpu_writeBack_fence_SI (_zz_212 ), //i + .io_cpu_writeBack_fence_PW (_zz_213 ), //i + .io_cpu_writeBack_fence_PR (_zz_214 ), //i + .io_cpu_writeBack_fence_PO (_zz_215 ), //i + .io_cpu_writeBack_fence_PI (_zz_216 ), //i + .io_cpu_writeBack_fence_FM (_zz_217[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_218 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_219 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_365) + 2'b00 : begin + _zz_222 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_222 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_222 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_222 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_CfuPlugin_CFU_ENCODING) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_ENCODING_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_ENCODING_string = "IMM_I"; + default : decode_CfuPlugin_CFU_ENCODING_string = "?????"; + endcase + end + always @(*) begin + case(_zz_1) + `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; + default : _zz_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_2) + `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; + default : _zz_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_3) + `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; + default : _zz_10_string = "?????"; + endcase + end + always @(*) begin + case(_zz_11) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; + default : _zz_12_string = "????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; + default : _zz_17_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; + default : _zz_20_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(_zz_23) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(_zz_26) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; + default : _zz_26_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_29) + `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; + default : _zz_29_string = "????????????"; + endcase + end + always @(*) begin + case(execute_CfuPlugin_CFU_ENCODING) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_ENCODING_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_ENCODING_string = "IMM_I"; + default : execute_CfuPlugin_CFU_ENCODING_string = "?????"; + endcase + end + always @(*) begin + case(_zz_30) + `Input2Kind_defaultEncoding_RS : _zz_30_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_30_string = "IMM_I"; + default : _zz_30_string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_31) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_31_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_31_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_31_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_31_string = "ECALL"; + default : _zz_31_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_32_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_32_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_32_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32_string = "ECALL"; + default : _zz_32_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_34) + `BranchCtrlEnum_defaultEncoding_INC : _zz_34_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_34_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_34_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_34_string = "JALR"; + default : _zz_34_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_37) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_37_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_37_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_37_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_37_string = "SRA_1 "; + default : _zz_37_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_38) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38_string = "SRA_1 "; + default : _zz_38_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_40) + `Src2CtrlEnum_defaultEncoding_RS : _zz_40_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_40_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_40_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_40_string = "PC "; + default : _zz_40_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_41) + `Src1CtrlEnum_defaultEncoding_RS : _zz_41_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_41_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_41_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_41_string = "URS1 "; + default : _zz_41_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_42) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_42_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_42_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_42_string = "BITWISE "; + default : _zz_42_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_43) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; + default : _zz_43_string = "?????"; + endcase + end + always @(*) begin + case(_zz_47) + `Input2Kind_defaultEncoding_RS : _zz_47_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_47_string = "IMM_I"; + default : _zz_47_string = "?????"; + endcase + end + always @(*) begin + case(_zz_48) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_48_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_48_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_48_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_48_string = "ECALL"; + default : _zz_48_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `BranchCtrlEnum_defaultEncoding_INC : _zz_49_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_49_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_49_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_49_string = "JALR"; + default : _zz_49_string = "????"; + endcase + end + always @(*) begin + case(_zz_50) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_50_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_50_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_50_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_50_string = "SRA_1 "; + default : _zz_50_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_51) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_51_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_51_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_51_string = "AND_1"; + default : _zz_51_string = "?????"; + endcase + end + always @(*) begin + case(_zz_52) + `Src2CtrlEnum_defaultEncoding_RS : _zz_52_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_52_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_52_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_52_string = "PC "; + default : _zz_52_string = "???"; + endcase + end + always @(*) begin + case(_zz_53) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_53_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_53_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_53_string = "BITWISE "; + default : _zz_53_string = "????????"; + endcase + end + always @(*) begin + case(_zz_54) + `Src1CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_54_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54_string = "URS1 "; + default : _zz_54_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_56) + `BranchCtrlEnum_defaultEncoding_INC : _zz_56_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_56_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_56_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_56_string = "JALR"; + default : _zz_56_string = "????"; + endcase + end + always @(*) begin + case(_zz_98) + `Src1CtrlEnum_defaultEncoding_RS : _zz_98_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_98_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_98_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_98_string = "URS1 "; + default : _zz_98_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_99) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_99_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_99_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_99_string = "BITWISE "; + default : _zz_99_string = "????????"; + endcase + end + always @(*) begin + case(_zz_100) + `Src2CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_100_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_100_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_100_string = "PC "; + default : _zz_100_string = "???"; + endcase + end + always @(*) begin + case(_zz_101) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_101_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_101_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_101_string = "AND_1"; + default : _zz_101_string = "?????"; + endcase + end + always @(*) begin + case(_zz_102) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_102_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_102_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_102_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_102_string = "SRA_1 "; + default : _zz_102_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_103) + `BranchCtrlEnum_defaultEncoding_INC : _zz_103_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_103_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_103_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_103_string = "JALR"; + default : _zz_103_string = "????"; + endcase + end + always @(*) begin + case(_zz_104) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_104_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_104_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_104_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_104_string = "ECALL"; + default : _zz_104_string = "?????"; + endcase + end + always @(*) begin + case(_zz_105) + `Input2Kind_defaultEncoding_RS : _zz_105_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_105_string = "IMM_I"; + default : _zz_105_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_CfuPlugin_CFU_ENCODING) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "?????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_264) + $signed(_zz_272)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_274; + assign execute_REGFILE_WRITE_DATA = _zz_107; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_202[1 : 0]; + assign decode_DO_EBREAK = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_276[0]; + assign decode_IS_RS1_SIGNED = _zz_277[0]; + assign decode_IS_DIV = _zz_278[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_279[0]; + assign decode_CfuPlugin_CFU_ENCODING = _zz_1; + assign _zz_2 = _zz_3; + assign decode_CfuPlugin_CFU_ENABLE = _zz_280[0]; + assign _zz_4 = _zz_5; + assign _zz_6 = _zz_7; + assign decode_ENV_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_IS_CSR = _zz_281[0]; + assign _zz_11 = _zz_12; + assign _zz_13 = _zz_14; + assign decode_SHIFT_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_ALU_BITWISE_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_SRC_LESS_UNSIGNED = _zz_282[0]; + assign decode_MEMORY_MANAGMENT = _zz_283[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_284[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_285[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_286[0]; + assign decode_SRC2_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_ALU_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_SRC1_CTRL = _zz_27; + assign _zz_28 = _zz_29; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_287[0]; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_ENCODING = _zz_30; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_31; + assign execute_ENV_CTRL = _zz_32; + assign writeBack_ENV_CTRL = _zz_33; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_129; + assign execute_BRANCH_CTRL = _zz_34; + assign decode_RS2_USE = _zz_288[0]; + assign decode_RS1_USE = _zz_289[0]; + always @ (*) begin + _zz_35 = execute_REGFILE_WRITE_DATA; + if(_zz_223)begin + _zz_35 = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_118)begin + if((_zz_119 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_120; + end + end + if(_zz_224)begin + if(_zz_225)begin + if(_zz_122)begin + decode_RS2 = _zz_55; + end + end + end + if(_zz_226)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_124)begin + decode_RS2 = _zz_36; + end + end + end + if(_zz_227)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_126)begin + decode_RS2 = _zz_35; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_118)begin + if((_zz_119 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_120; + end + end + if(_zz_224)begin + if(_zz_225)begin + if(_zz_121)begin + decode_RS1 = _zz_55; + end + end + end + if(_zz_226)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_123)begin + decode_RS1 = _zz_36; + end + end + end + if(_zz_227)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_125)begin + decode_RS1 = _zz_35; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_36 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_36 = _zz_115; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_36 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_36 = memory_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_228)begin + _zz_36 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_37; + assign execute_SHIFT_CTRL = _zz_38; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_39 = execute_PC; + assign execute_SRC2_CTRL = _zz_40; + assign execute_SRC1_CTRL = _zz_41; + assign decode_SRC_USE_SUB_LESS = _zz_290[0]; + assign decode_SRC_ADD_ZERO = _zz_291[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_42; + assign execute_SRC2 = _zz_113; + assign execute_SRC1 = _zz_108; + assign execute_ALU_BITWISE_CTRL = _zz_43; + assign _zz_44 = writeBack_INSTRUCTION; + assign _zz_45 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_46 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_46 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_292[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_366) == 32'h00000003),{(_zz_367 == _zz_368),{_zz_369,{_zz_370,_zz_371}}}}}}} != 22'h0); + always @ (*) begin + _zz_55 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_55 = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_263) + 2'b00 : begin + _zz_55 = _zz_338; + end + default : begin + _zz_55 = _zz_339; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_293[0]; + assign decode_FLUSH_ALL = _zz_294[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_229)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_230)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_231)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_232)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_56; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_57 = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_57 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_58 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_58 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + case(_zz_161) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_116 || _zz_117)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_233)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_233)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((_zz_218 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + execute_arbitration_haltItself = 1'b1; + end + if(((dataCache_1_io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_234)begin + if((! execute_CsrPlugin_wfiWake))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_223)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if(_zz_235)begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushIt = 1'b0; + if(_zz_235)begin + if(_zz_236)begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_235)begin + if(_zz_236)begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if((! memory_CfuPlugin_rsp_valid))begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_228)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(_zz_237)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(_zz_237)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_238)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_239)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_238)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_239)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_235)begin + if(_zz_236)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_240)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + _zz_59 = 1'b0; + if(DebugPlugin_godmode)begin + _zz_59 = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_234)begin + CsrPlugin_inWfi = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_238)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_239)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_238)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_239)begin + case(_zz_241) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode)begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + end + end + + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_60 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_61 = (_zz_60 & (~ _zz_295)); + assign _zz_62 = _zz_61[3]; + assign _zz_63 = (_zz_61[1] || _zz_62); + assign _zz_64 = (_zz_61[2] || _zz_62); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_222; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_297); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_65 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_68; + assign _zz_68 = ((1'b0 && (! _zz_69)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_69 = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_69; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_71 = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_73; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + always @ (*) begin + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_161) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + end + + assign _zz_74 = _zz_298[11]; + always @ (*) begin + _zz_75[18] = _zz_74; + _zz_75[17] = _zz_74; + _zz_75[16] = _zz_74; + _zz_75[15] = _zz_74; + _zz_75[14] = _zz_74; + _zz_75[13] = _zz_74; + _zz_75[12] = _zz_74; + _zz_75[11] = _zz_74; + _zz_75[10] = _zz_74; + _zz_75[9] = _zz_74; + _zz_75[8] = _zz_74; + _zz_75[7] = _zz_74; + _zz_75[6] = _zz_74; + _zz_75[5] = _zz_74; + _zz_75[4] = _zz_74; + _zz_75[3] = _zz_74; + _zz_75[2] = _zz_74; + _zz_75[1] = _zz_74; + _zz_75[0] = _zz_74; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_299[31])); + if(_zz_80)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_76 = _zz_300[19]; + always @ (*) begin + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7] = _zz_76; + _zz_77[6] = _zz_76; + _zz_77[5] = _zz_76; + _zz_77[4] = _zz_76; + _zz_77[3] = _zz_76; + _zz_77[2] = _zz_76; + _zz_77[1] = _zz_76; + _zz_77[0] = _zz_76; + end + + assign _zz_78 = _zz_301[11]; + always @ (*) begin + _zz_79[18] = _zz_78; + _zz_79[17] = _zz_78; + _zz_79[16] = _zz_78; + _zz_79[15] = _zz_78; + _zz_79[14] = _zz_78; + _zz_79[13] = _zz_78; + _zz_79[12] = _zz_78; + _zz_79[11] = _zz_78; + _zz_79[10] = _zz_78; + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7] = _zz_78; + _zz_79[6] = _zz_78; + _zz_79[5] = _zz_78; + _zz_79[4] = _zz_78; + _zz_79[3] = _zz_78; + _zz_79[2] = _zz_78; + _zz_79[1] = _zz_78; + _zz_79[0] = _zz_78; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_80 = _zz_302[1]; + end + default : begin + _zz_80 = _zz_303[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_81 = _zz_304[19]; + always @ (*) begin + _zz_82[10] = _zz_81; + _zz_82[9] = _zz_81; + _zz_82[8] = _zz_81; + _zz_82[7] = _zz_81; + _zz_82[6] = _zz_81; + _zz_82[5] = _zz_81; + _zz_82[4] = _zz_81; + _zz_82[3] = _zz_81; + _zz_82[2] = _zz_81; + _zz_82[1] = _zz_81; + _zz_82[0] = _zz_81; + end + + assign _zz_83 = _zz_305[11]; + always @ (*) begin + _zz_84[18] = _zz_83; + _zz_84[17] = _zz_83; + _zz_84[16] = _zz_83; + _zz_84[15] = _zz_83; + _zz_84[14] = _zz_83; + _zz_84[13] = _zz_83; + _zz_84[12] = _zz_83; + _zz_84[11] = _zz_83; + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7] = _zz_83; + _zz_84[6] = _zz_83; + _zz_84[5] = _zz_83; + _zz_84[4] = _zz_83; + _zz_84[3] = _zz_83; + _zz_84[2] = _zz_83; + _zz_84[1] = _zz_83; + _zz_84[0] = _zz_83; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_82,{{{_zz_384,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_84,{{{_zz_385,_zz_386},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_193 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_194 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_195 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_194; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_197 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_198 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_199 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_232)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_230)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_200 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_230)begin + _zz_200 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_231)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_229)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_231)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_229)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_192 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_219 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_201 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_202 = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_87 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_87 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_87 = execute_RS2[31 : 0]; + end + endcase + end + + assign _zz_218 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_203 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_204 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_203; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_204; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @ (*) begin + _zz_205 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_59 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_205 = 1'b1; + end + end + + assign _zz_206 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_207 = (CsrPlugin_privilege == 2'b00); + assign _zz_208 = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_242)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_242)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_242)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_306}; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_307}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_88 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_89[31] = _zz_88; + _zz_89[30] = _zz_88; + _zz_89[29] = _zz_88; + _zz_89[28] = _zz_88; + _zz_89[27] = _zz_88; + _zz_89[26] = _zz_88; + _zz_89[25] = _zz_88; + _zz_89[24] = _zz_88; + _zz_89[23] = _zz_88; + _zz_89[22] = _zz_88; + _zz_89[21] = _zz_88; + _zz_89[20] = _zz_88; + _zz_89[19] = _zz_88; + _zz_89[18] = _zz_88; + _zz_89[17] = _zz_88; + _zz_89[16] = _zz_88; + _zz_89[15] = _zz_88; + _zz_89[14] = _zz_88; + _zz_89[13] = _zz_88; + _zz_89[12] = _zz_88; + _zz_89[11] = _zz_88; + _zz_89[10] = _zz_88; + _zz_89[9] = _zz_88; + _zz_89[8] = _zz_88; + _zz_89[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_90 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_91[31] = _zz_90; + _zz_91[30] = _zz_90; + _zz_91[29] = _zz_90; + _zz_91[28] = _zz_90; + _zz_91[27] = _zz_90; + _zz_91[26] = _zz_90; + _zz_91[25] = _zz_90; + _zz_91[24] = _zz_90; + _zz_91[23] = _zz_90; + _zz_91[22] = _zz_90; + _zz_91[21] = _zz_90; + _zz_91[20] = _zz_90; + _zz_91[19] = _zz_90; + _zz_91[18] = _zz_90; + _zz_91[17] = _zz_90; + _zz_91[16] = _zz_90; + _zz_91[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_261) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_89; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_91; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_93 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_94 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_95 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_96 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_97 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_92 = {(((decode_INSTRUCTION & _zz_387) == 32'h00100050) != 1'b0),{(_zz_97 != 1'b0),{(_zz_97 != 1'b0),{(_zz_388 != _zz_389),{_zz_390,{_zz_391,_zz_392}}}}}}; + assign _zz_98 = _zz_92[2 : 1]; + assign _zz_54 = _zz_98; + assign _zz_99 = _zz_92[7 : 6]; + assign _zz_53 = _zz_99; + assign _zz_100 = _zz_92[9 : 8]; + assign _zz_52 = _zz_100; + assign _zz_101 = _zz_92[19 : 18]; + assign _zz_51 = _zz_101; + assign _zz_102 = _zz_92[22 : 21]; + assign _zz_50 = _zz_102; + assign _zz_103 = _zz_92[24 : 23]; + assign _zz_49 = _zz_103; + assign _zz_104 = _zz_92[27 : 26]; + assign _zz_48 = _zz_104; + assign _zz_105 = _zz_92[29 : 29]; + assign _zz_47 = _zz_105; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_220; + assign decode_RegFilePlugin_rs2Data = _zz_221; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); + if(_zz_106)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + assign lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; + assign lastStageRegFileWrite_payload_data = _zz_55; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_107 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_107 = {31'd0, _zz_308}; + end + default : begin + _zz_107 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_108 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_108 = {29'd0, _zz_309}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_108 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_108 = {27'd0, _zz_310}; + end + endcase + end + + assign _zz_109 = _zz_311[11]; + always @ (*) begin + _zz_110[19] = _zz_109; + _zz_110[18] = _zz_109; + _zz_110[17] = _zz_109; + _zz_110[16] = _zz_109; + _zz_110[15] = _zz_109; + _zz_110[14] = _zz_109; + _zz_110[13] = _zz_109; + _zz_110[12] = _zz_109; + _zz_110[11] = _zz_109; + _zz_110[10] = _zz_109; + _zz_110[9] = _zz_109; + _zz_110[8] = _zz_109; + _zz_110[7] = _zz_109; + _zz_110[6] = _zz_109; + _zz_110[5] = _zz_109; + _zz_110[4] = _zz_109; + _zz_110[3] = _zz_109; + _zz_110[2] = _zz_109; + _zz_110[1] = _zz_109; + _zz_110[0] = _zz_109; + end + + assign _zz_111 = _zz_312[11]; + always @ (*) begin + _zz_112[19] = _zz_111; + _zz_112[18] = _zz_111; + _zz_112[17] = _zz_111; + _zz_112[16] = _zz_111; + _zz_112[15] = _zz_111; + _zz_112[14] = _zz_111; + _zz_112[13] = _zz_111; + _zz_112[12] = _zz_111; + _zz_112[11] = _zz_111; + _zz_112[10] = _zz_111; + _zz_112[9] = _zz_111; + _zz_112[8] = _zz_111; + _zz_112[7] = _zz_111; + _zz_112[6] = _zz_111; + _zz_112[5] = _zz_111; + _zz_112[4] = _zz_111; + _zz_112[3] = _zz_111; + _zz_112[2] = _zz_111; + _zz_112[1] = _zz_111; + _zz_112[0] = _zz_111; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_113 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_113 = {_zz_110,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_113 = {_zz_112,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_113 = _zz_39; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_313; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_114[0] = execute_SRC1[31]; + _zz_114[1] = execute_SRC1[30]; + _zz_114[2] = execute_SRC1[29]; + _zz_114[3] = execute_SRC1[28]; + _zz_114[4] = execute_SRC1[27]; + _zz_114[5] = execute_SRC1[26]; + _zz_114[6] = execute_SRC1[25]; + _zz_114[7] = execute_SRC1[24]; + _zz_114[8] = execute_SRC1[23]; + _zz_114[9] = execute_SRC1[22]; + _zz_114[10] = execute_SRC1[21]; + _zz_114[11] = execute_SRC1[20]; + _zz_114[12] = execute_SRC1[19]; + _zz_114[13] = execute_SRC1[18]; + _zz_114[14] = execute_SRC1[17]; + _zz_114[15] = execute_SRC1[16]; + _zz_114[16] = execute_SRC1[15]; + _zz_114[17] = execute_SRC1[14]; + _zz_114[18] = execute_SRC1[13]; + _zz_114[19] = execute_SRC1[12]; + _zz_114[20] = execute_SRC1[11]; + _zz_114[21] = execute_SRC1[10]; + _zz_114[22] = execute_SRC1[9]; + _zz_114[23] = execute_SRC1[8]; + _zz_114[24] = execute_SRC1[7]; + _zz_114[25] = execute_SRC1[6]; + _zz_114[26] = execute_SRC1[5]; + _zz_114[27] = execute_SRC1[4]; + _zz_114[28] = execute_SRC1[3]; + _zz_114[29] = execute_SRC1[2]; + _zz_114[30] = execute_SRC1[1]; + _zz_114[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_114 : execute_SRC1); + always @ (*) begin + _zz_115[0] = memory_SHIFT_RIGHT[31]; + _zz_115[1] = memory_SHIFT_RIGHT[30]; + _zz_115[2] = memory_SHIFT_RIGHT[29]; + _zz_115[3] = memory_SHIFT_RIGHT[28]; + _zz_115[4] = memory_SHIFT_RIGHT[27]; + _zz_115[5] = memory_SHIFT_RIGHT[26]; + _zz_115[6] = memory_SHIFT_RIGHT[25]; + _zz_115[7] = memory_SHIFT_RIGHT[24]; + _zz_115[8] = memory_SHIFT_RIGHT[23]; + _zz_115[9] = memory_SHIFT_RIGHT[22]; + _zz_115[10] = memory_SHIFT_RIGHT[21]; + _zz_115[11] = memory_SHIFT_RIGHT[20]; + _zz_115[12] = memory_SHIFT_RIGHT[19]; + _zz_115[13] = memory_SHIFT_RIGHT[18]; + _zz_115[14] = memory_SHIFT_RIGHT[17]; + _zz_115[15] = memory_SHIFT_RIGHT[16]; + _zz_115[16] = memory_SHIFT_RIGHT[15]; + _zz_115[17] = memory_SHIFT_RIGHT[14]; + _zz_115[18] = memory_SHIFT_RIGHT[13]; + _zz_115[19] = memory_SHIFT_RIGHT[12]; + _zz_115[20] = memory_SHIFT_RIGHT[11]; + _zz_115[21] = memory_SHIFT_RIGHT[10]; + _zz_115[22] = memory_SHIFT_RIGHT[9]; + _zz_115[23] = memory_SHIFT_RIGHT[8]; + _zz_115[24] = memory_SHIFT_RIGHT[7]; + _zz_115[25] = memory_SHIFT_RIGHT[6]; + _zz_115[26] = memory_SHIFT_RIGHT[5]; + _zz_115[27] = memory_SHIFT_RIGHT[4]; + _zz_115[28] = memory_SHIFT_RIGHT[3]; + _zz_115[29] = memory_SHIFT_RIGHT[2]; + _zz_115[30] = memory_SHIFT_RIGHT[1]; + _zz_115[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_116 = 1'b0; + if(_zz_243)begin + if(_zz_244)begin + if(_zz_121)begin + _zz_116 = 1'b1; + end + end + end + if(_zz_245)begin + if(_zz_246)begin + if(_zz_123)begin + _zz_116 = 1'b1; + end + end + end + if(_zz_247)begin + if(_zz_248)begin + if(_zz_125)begin + _zz_116 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_116 = 1'b0; + end + end + + always @ (*) begin + _zz_117 = 1'b0; + if(_zz_243)begin + if(_zz_244)begin + if(_zz_122)begin + _zz_117 = 1'b1; + end + end + end + if(_zz_245)begin + if(_zz_246)begin + if(_zz_124)begin + _zz_117 = 1'b1; + end + end + end + if(_zz_247)begin + if(_zz_248)begin + if(_zz_126)begin + _zz_117 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_117 = 1'b0; + end + end + + assign _zz_121 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_123 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_125 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_127 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_127 == 3'b000)) begin + _zz_128 = execute_BranchPlugin_eq; + end else if((_zz_127 == 3'b001)) begin + _zz_128 = (! execute_BranchPlugin_eq); + end else if((((_zz_127 & 3'b101) == 3'b101))) begin + _zz_128 = (! execute_SRC_LESS); + end else begin + _zz_128 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_129 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_129 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_129 = 1'b1; + end + default : begin + _zz_129 = _zz_128; + end + endcase + end + + assign _zz_130 = _zz_320[11]; + always @ (*) begin + _zz_131[19] = _zz_130; + _zz_131[18] = _zz_130; + _zz_131[17] = _zz_130; + _zz_131[16] = _zz_130; + _zz_131[15] = _zz_130; + _zz_131[14] = _zz_130; + _zz_131[13] = _zz_130; + _zz_131[12] = _zz_130; + _zz_131[11] = _zz_130; + _zz_131[10] = _zz_130; + _zz_131[9] = _zz_130; + _zz_131[8] = _zz_130; + _zz_131[7] = _zz_130; + _zz_131[6] = _zz_130; + _zz_131[5] = _zz_130; + _zz_131[4] = _zz_130; + _zz_131[3] = _zz_130; + _zz_131[2] = _zz_130; + _zz_131[1] = _zz_130; + _zz_131[0] = _zz_130; + end + + assign _zz_132 = _zz_321[19]; + always @ (*) begin + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; + end + + assign _zz_134 = _zz_322[11]; + always @ (*) begin + _zz_135[18] = _zz_134; + _zz_135[17] = _zz_134; + _zz_135[16] = _zz_134; + _zz_135[15] = _zz_134; + _zz_135[14] = _zz_134; + _zz_135[13] = _zz_134; + _zz_135[12] = _zz_134; + _zz_135[11] = _zz_134; + _zz_135[10] = _zz_134; + _zz_135[9] = _zz_134; + _zz_135[8] = _zz_134; + _zz_135[7] = _zz_134; + _zz_135[6] = _zz_134; + _zz_135[5] = _zz_134; + _zz_135[4] = _zz_134; + _zz_135[3] = _zz_134; + _zz_135[2] = _zz_134; + _zz_135[1] = _zz_134; + _zz_135[0] = _zz_134; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_136 = (_zz_323[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_136 = _zz_324[1]; + end + default : begin + _zz_136 = _zz_325[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_136); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_137 = _zz_326[11]; + always @ (*) begin + _zz_138[19] = _zz_137; + _zz_138[18] = _zz_137; + _zz_138[17] = _zz_137; + _zz_138[16] = _zz_137; + _zz_138[15] = _zz_137; + _zz_138[14] = _zz_137; + _zz_138[13] = _zz_137; + _zz_138[12] = _zz_137; + _zz_138[11] = _zz_137; + _zz_138[10] = _zz_137; + _zz_138[9] = _zz_137; + _zz_138[8] = _zz_137; + _zz_138[7] = _zz_137; + _zz_138[6] = _zz_137; + _zz_138[5] = _zz_137; + _zz_138[4] = _zz_137; + _zz_138[3] = _zz_137; + _zz_138[2] = _zz_137; + _zz_138[1] = _zz_137; + _zz_138[0] = _zz_137; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_138,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_140,{{{_zz_564,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_142,{{{_zz_565,_zz_566},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_329}; + end + end + endcase + end + + assign _zz_139 = _zz_327[19]; + always @ (*) begin + _zz_140[10] = _zz_139; + _zz_140[9] = _zz_139; + _zz_140[8] = _zz_139; + _zz_140[7] = _zz_139; + _zz_140[6] = _zz_139; + _zz_140[5] = _zz_139; + _zz_140[4] = _zz_139; + _zz_140[3] = _zz_139; + _zz_140[2] = _zz_139; + _zz_140[1] = _zz_139; + _zz_140[0] = _zz_139; + end + + assign _zz_141 = _zz_328[11]; + always @ (*) begin + _zz_142[18] = _zz_141; + _zz_142[17] = _zz_141; + _zz_142[16] = _zz_141; + _zz_142[15] = _zz_141; + _zz_142[14] = _zz_141; + _zz_142[13] = _zz_141; + _zz_142[12] = _zz_141; + _zz_142[11] = _zz_141; + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_143 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_144 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_145 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_146 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_147 = _zz_330[0]; + assign _zz_148 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_149 = _zz_332[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_233)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(_zz_237)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_249)begin + CsrPlugin_selfException_valid = 1'b1; + end + if(_zz_250)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_249)begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(_zz_250)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_262) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign execute_CfuPlugin_functionsIds_0 = _zz_334; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_150 = _zz_335[11]; + always @ (*) begin + _zz_151[19] = _zz_150; + _zz_151[18] = _zz_150; + _zz_151[17] = _zz_150; + _zz_151[16] = _zz_150; + _zz_151[15] = _zz_150; + _zz_151[14] = _zz_150; + _zz_151[13] = _zz_150; + _zz_151[12] = _zz_150; + _zz_151[11] = _zz_150; + _zz_151[10] = _zz_150; + _zz_151[9] = _zz_150; + _zz_151[8] = _zz_150; + _zz_151[7] = _zz_150; + _zz_151[6] = _zz_150; + _zz_151[5] = _zz_150; + _zz_151[4] = _zz_150; + _zz_151[3] = _zz_150; + _zz_151[2] = _zz_150; + _zz_151[1] = _zz_150; + _zz_151[0] = _zz_150; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_ENCODING) + `Input2Kind_defaultEncoding_RS : begin + _zz_152 = execute_RS2; + end + default : begin + _zz_152 = {_zz_151,execute_INSTRUCTION[31 : 20]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_152; + assign CfuPlugin_bus_rsp_ready = ((1'b1 && (! memory_CfuPlugin_rsp_valid)) || memory_CfuPlugin_rsp_ready); + assign memory_CfuPlugin_rsp_valid = CfuPlugin_bus_rsp_m2sPipe_rValid; + assign memory_CfuPlugin_rsp_payload_response_ok = CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; + assign memory_CfuPlugin_rsp_payload_outputs_0 = CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0; + always @ (*) begin + CfuPlugin_joinException_valid = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if(memory_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); + end + end + end + + assign CfuPlugin_joinException_payload_code = 4'b1111; + assign CfuPlugin_joinException_payload_badAddr = 32'h0; + always @ (*) begin + memory_CfuPlugin_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_251) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_251) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_336) + $signed(_zz_337)); + assign memory_DivPlugin_frontendOk = 1'b1; + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_228)begin + if(_zz_252)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_253)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_341); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_153 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_153[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_342); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_343 : _zz_344); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_345[31:0]; + assign _zz_154 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_155 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_156 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_157[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_157[31 : 0] = execute_RS1; + end + + assign _zz_159 = (_zz_158 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_159 != 32'h0); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_254) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_160))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + always @ (*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_254) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_29 = decode_SRC1_CTRL; + assign _zz_27 = _zz_54; + assign _zz_41 = decode_to_execute_SRC1_CTRL; + assign _zz_26 = decode_ALU_CTRL; + assign _zz_24 = _zz_53; + assign _zz_42 = decode_to_execute_ALU_CTRL; + assign _zz_23 = decode_SRC2_CTRL; + assign _zz_21 = _zz_52; + assign _zz_40 = decode_to_execute_SRC2_CTRL; + assign _zz_20 = decode_ALU_BITWISE_CTRL; + assign _zz_18 = _zz_51; + assign _zz_43 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_17 = decode_SHIFT_CTRL; + assign _zz_14 = execute_SHIFT_CTRL; + assign _zz_15 = _zz_50; + assign _zz_38 = decode_to_execute_SHIFT_CTRL; + assign _zz_37 = execute_to_memory_SHIFT_CTRL; + assign _zz_12 = decode_BRANCH_CTRL; + assign _zz_56 = _zz_49; + assign _zz_34 = decode_to_execute_BRANCH_CTRL; + assign _zz_10 = decode_ENV_CTRL; + assign _zz_7 = execute_ENV_CTRL; + assign _zz_5 = memory_ENV_CTRL; + assign _zz_8 = _zz_48; + assign _zz_32 = decode_to_execute_ENV_CTRL; + assign _zz_31 = execute_to_memory_ENV_CTRL; + assign _zz_33 = memory_to_writeBack_ENV_CTRL; + assign _zz_3 = decode_CfuPlugin_CFU_ENCODING; + assign _zz_1 = _zz_47; + assign _zz_30 = decode_to_execute_CfuPlugin_CFU_ENCODING; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(_zz_161) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_162 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_162[12 : 0] = 13'h1000; + _zz_162[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_163 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_163[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_164 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_164[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_165 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_165[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_166 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_166[31 : 30] = CsrPlugin_misa_base; + _zz_166[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_167 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_167[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_167[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_167[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_168 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_168[11 : 11] = CsrPlugin_mip_MEIP; + _zz_168[7 : 7] = CsrPlugin_mip_MTIP; + _zz_168[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_169 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_169[11 : 11] = CsrPlugin_mie_MEIE; + _zz_169[7 : 7] = CsrPlugin_mie_MTIE; + _zz_169[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_170 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_170[31 : 2] = CsrPlugin_mtvec_base; + _zz_170[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_171 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_171[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_172 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_172[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_173 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_173[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_173[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_174 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_174[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_175 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_175[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_176 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_176[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_177[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_178[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_179[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_180[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_181[31 : 0] = _zz_158; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_182[31 : 0] = _zz_159; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_162 | _zz_163) | (_zz_164 | _zz_165)) | ((_zz_567 | _zz_166) | (_zz_167 | _zz_168))) | (((_zz_169 | _zz_170) | (_zz_171 | _zz_172)) | ((_zz_173 | _zz_174) | (_zz_175 | _zz_176)))) | (((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | (_zz_181 | _zz_182))); + assign iBusWishbone_ADR = {_zz_362,_zz_183}; + assign iBusWishbone_CTI = ((_zz_183 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'h0; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_255)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_255)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_184; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_190 = (dBus_cmd_payload_length != 3'b000); + assign _zz_186 = dBus_cmd_valid; + assign _zz_188 = dBus_cmd_payload_wr; + assign _zz_189 = (_zz_185 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_187 && (_zz_188 || _zz_189)); + assign dBusWishbone_ADR = ((_zz_190 ? {{dBus_cmd_payload_address[31 : 5],_zz_185},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_190 ? (_zz_189 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_188 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_188; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_187 = (_zz_186 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_186; + assign dBusWishbone_STB = _zz_186; + assign dBus_rsp_valid = _zz_191; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_70 <= 1'b0; + _zz_72 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_85; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_86; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_106 <= 1'b1; + _zz_118 <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_CfuPlugin_hold <= 1'b0; + execute_CfuPlugin_fired <= 1'b0; + CfuPlugin_bus_rsp_m2sPipe_rValid <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_158 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_161 <= 3'b000; + memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; + memory_to_writeBack_INSTRUCTION <= 32'h0; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; + _zz_183 <= 3'b000; + _zz_184 <= 1'b0; + _zz_185 <= 3'b000; + _zz_191 <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_70 <= 1'b0; + end + if(_zz_68)begin + _zz_70 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_72 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(_zz_256)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_106 <= 1'b0; + _zz_118 <= (_zz_45 && writeBack_arbitration_isFiring); + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_257)begin + if(_zz_258)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_259)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_260)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_238)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_239)begin + case(_zz_241) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_145,{_zz_144,_zz_143}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(execute_CfuPlugin_schedule)begin + execute_CfuPlugin_hold <= 1'b1; + end + if(CfuPlugin_bus_cmd_ready)begin + execute_CfuPlugin_hold <= 1'b0; + end + if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + execute_CfuPlugin_fired <= 1'b1; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_CfuPlugin_fired <= 1'b0; + end + if(CfuPlugin_bus_rsp_ready)begin + CfuPlugin_bus_rsp_m2sPipe_rValid <= CfuPlugin_bus_rsp_valid; + end + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_36; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= execute_CfuPlugin_CFU_IN_FLIGHT; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_161) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_161 <= 3'b001; + end + end + 3'b001 : begin + _zz_161 <= 3'b010; + end + 3'b010 : begin + _zz_161 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_161 <= 3'b100; + end + end + 3'b100 : begin + _zz_161 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_355[0]; + CsrPlugin_mstatus_MIE <= _zz_356[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_358[0]; + CsrPlugin_mie_MTIE <= _zz_359[0]; + CsrPlugin_mie_MSIE <= _zz_360[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_255)begin + if(iBusWishbone_ACK)begin + _zz_183 <= (_zz_183 + 3'b001); + end + end + _zz_184 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_186 && _zz_187))begin + _zz_185 <= (_zz_185 + 3'b001); + if(_zz_189)begin + _zz_185 <= 3'b000; + end + end + _zz_191 <= ((_zz_186 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_73 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_256)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + _zz_119 <= _zz_44[11 : 7]; + _zz_120 <= _zz_55; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_233)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_147 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_147 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(_zz_237)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_257)begin + if(_zz_258)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_259)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_260)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_238)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(CfuPlugin_bus_rsp_ready)begin + CfuPlugin_bus_rsp_m2sPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_228)begin + if(_zz_252)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_346[31:0]; + end + end + end + if(_zz_253)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_156 ? (~ _zz_157) : _zz_157) + _zz_352); + memory_DivPlugin_rs2 <= ((_zz_155 ? (~ execute_RS2) : execute_RS2) + _zz_354); + memory_DivPlugin_div_needRevert <= ((_zz_156 ^ (_zz_155 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_39; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_58; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_57; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_28; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_16; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_13; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENCODING <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_35; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_357[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_361[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_55; + end + _zz_160 <= debug_bus_cmd_payload_address[2]; + if(_zz_235)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_254) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(_zz_235)begin + if(_zz_236)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_240)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if(loader_valid)begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9) != 1'b0); + end + end + + assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_9, + input [31:0] _zz_10, + input clk, + input reset +); + reg [31:0] _zz_11; + reg [21:0] _zz_12; + wire _zz_13; + wire _zz_14; + wire [0:0] _zz_15; + wire [0:0] _zz_16; + wire [21:0] _zz_17; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_13 = (! lineLoader_flushCounter[7]); + assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_15 = _zz_8[0 : 0]; + assign _zz_16 = _zz_8[1 : 1]; + assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_11 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_12 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_13)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_12; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_14)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_13)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_14)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + if((_zz_9 != 3'b000))begin + io_cpu_fetch_data_regNextWhen <= _zz_10; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml new file mode 100644 index 0000000..24597c0 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml @@ -0,0 +1,5 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/build.sbt b/pythondata_cpu_vexriscv/verilog/build.sbt index 05f6edf..5e90117 100644 --- a/pythondata_cpu_vexriscv/verilog/build.sbt +++ b/pythondata_cpu_vexriscv/verilog/build.sbt @@ -1,3 +1,4 @@ +val spinalVersion = "1.4.2" lazy val root = (project in file(".")). settings( @@ -6,8 +7,11 @@ lazy val root = (project in file(".")). scalaVersion := "2.11.12", version := "0.1.0-SNAPSHOT" )), - name := "VexRiscvOnWishbone" + name := "VexRiscvOnWishbone", + scalacOptions += s"-Xplugin:${new File(baseDirectory.value + s"/ext/SpinalHDL/idslplugin/target/scala-2.11/spinalhdl-idsl-plugin_2.11-$spinalVersion.jar")}", + scalacOptions += s"-Xplugin-require:idsl-plugin", ).dependsOn(vexRiscv) -lazy val vexRiscv = RootProject(file("ext/VexRiscv")) +lazy val vexRiscv = RootProject(file("./ext/VexRiscv")) + fork := true diff --git a/pythondata_cpu_vexriscv/verilog/ext/SpinalHDL b/pythondata_cpu_vexriscv/verilog/ext/SpinalHDL new file mode 160000 index 0000000..f7a9fa2 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/ext/SpinalHDL @@ -0,0 +1 @@ +Subproject commit f7a9fa258904b963b2b96a3f91c6bdf75083d096 diff --git a/pythondata_cpu_vexriscv/verilog/ext/VexRiscv b/pythondata_cpu_vexriscv/verilog/ext/VexRiscv index 5f0c7a7..8bd1785 160000 --- a/pythondata_cpu_vexriscv/verilog/ext/VexRiscv +++ b/pythondata_cpu_vexriscv/verilog/ext/VexRiscv @@ -1 +1 @@ -Subproject commit 5f0c7a7faf6b65c907a93be6e3723e297d37ee71 +Subproject commit 8bd1785233dfeb18ce264b2752a0730c1061c62e diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index fd3e7f3..1ab87db 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -24,6 +24,7 @@ case class ArgConfig( iCacheSize : Int = 4096, dCacheSize : Int = 4096, mulDiv : Boolean = true, + cfu : Boolean = false, atomics: Boolean = false, compressedGen: Boolean = false, singleCycleMulDiv : Boolean = true, @@ -60,6 +61,7 @@ object GenCoreDefault{ // ex : -dCacheSize=XXX opt[Int]("dCacheSize") action { (v, c) => c.copy(dCacheSize = v) } text("Set data cache size, 0 mean no cache") opt[Boolean]("mulDiv") action { (v, c) => c.copy(mulDiv = v) } text("set RV32IM") + opt[Boolean]("cfu") action { (v, c) => c.copy(cfu = v) } text("If true, add SIMD ADD custom function unit") opt[Boolean]("atomics") action { (v, c) => c.copy(mulDiv = v) } text("set RV32I[A]") opt[Boolean]("compressedGen") action { (v, c) => c.copy(compressedGen = v) } text("set RV32I[C]") opt[Boolean]("singleCycleMulDiv") action { (v, c) => c.copy(singleCycleMulDiv = v) } text("If true, MUL/DIV are single-cycle") @@ -192,6 +194,35 @@ object GenCoreDefault{ new YamlPlugin(argConfig.outputFile.concat(".yaml")) ) + if(argConfig.cfu) { + plugins ++= List( + new CfuPlugin( + stageCount = 1, + allowZeroLatency = true, + encodings = List( + CfuPluginEncoding ( + instruction = M"-------------------------0001011", + functionId = List(14 downto 12), + input2Kind = CfuPlugin.Input2Kind.RS + ) + ), + busParameter = CfuBusParameter( + CFU_VERSION = 0, + CFU_INTERFACE_ID_W = 0, + CFU_FUNCTION_ID_W = 3, + CFU_REORDER_ID_W = 0, + CFU_REQ_RESP_ID_W = 0, + CFU_INPUTS = 2, + CFU_INPUT_DATA_W = 32, + CFU_OUTPUTS = 1, + CFU_OUTPUT_DATA_W = 32, + CFU_FLOW_REQ_READY_ALWAYS = false, + CFU_FLOW_RESP_READY_ALWAYS = false + ) + ) + ) + } + if(argConfig.mulDiv) { if(argConfig.singleCycleMulDiv) { plugins ++= List( @@ -274,4 +305,4 @@ class ForceRamBlockPhase() extends spinal.core.internals.Phase{ } } override def hasNetlistImpact: Boolean = false -} \ No newline at end of file +} From 7374fad28f2147e727b47783529824ffde6ebea2 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Tue, 6 Oct 2020 13:12:36 -0700 Subject: [PATCH 02/30] Set up wrappers to contain the cpu+cfu. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 8 ++ .../verilog/VexRiscv_FullCfu.v | 6 +- .../verilog/VexRiscv_FullCfuDebug.v | 6 +- pythondata_cpu_vexriscv/verilog/genWrapper.py | 110 ++++++++++++++++ .../verilog/wrapVexRiscv_FullCfu.v | 103 +++++++++++++++ .../verilog/wrapVexRiscv_FullCfuDebug.v | 119 ++++++++++++++++++ 6 files changed, 346 insertions(+), 6 deletions(-) create mode 100755 pythondata_cpu_vexriscv/verilog/genWrapper.py create mode 100644 pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v create mode 100644 pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index d46540e..b427867 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -32,11 +32,19 @@ VexRiscv_Full.v: $(SRC) VexRiscv_FullDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --outputFile VexRiscv_FullDebug" +# CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfu.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --cfu true --outputFile VexRiscv_FullCfu" + sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v + /bin/mv tmp.v $@ + ./genWrapper.py $@ > wrap$@ +# CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfuDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --cfu true --outputFile VexRiscv_FullCfuDebug" + sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v + /bin/mv tmp.v $@ + ./genWrapper.py $@ > wrap$@ VexRiscv_Linux.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal --outputFile VexRiscv_Linux" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index 80a07d6..a5bcb28 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : 654057b2f5cec0f9fc99487dff67861f76fcbe7e +// Generator : SpinalHDL v1.4.2 git head : f8290e79928d331d21410a57fea40abaca0e8d55 // Component : VexRiscv -// Git hash : 654057b2f5cec0f9fc99487dff67861f76fcbe7e +// Git hash : f8290e79928d331d21410a57fea40abaca0e8d55 `define Input2Kind_defaultEncoding_type [0:0] @@ -48,7 +48,7 @@ `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -module VexRiscv ( +module VexRiscv_inner ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index a2b21bb..0cc7887 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : 654057b2f5cec0f9fc99487dff67861f76fcbe7e +// Generator : SpinalHDL v1.4.2 git head : f8290e79928d331d21410a57fea40abaca0e8d55 // Component : VexRiscv -// Git hash : 654057b2f5cec0f9fc99487dff67861f76fcbe7e +// Git hash : f8290e79928d331d21410a57fea40abaca0e8d55 `define Input2Kind_defaultEncoding_type [0:0] @@ -48,7 +48,7 @@ `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -module VexRiscv ( +module VexRiscv_inner ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, diff --git a/pythondata_cpu_vexriscv/verilog/genWrapper.py b/pythondata_cpu_vexriscv/verilog/genWrapper.py new file mode 100755 index 0000000..dda538d --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/genWrapper.py @@ -0,0 +1,110 @@ +#!/usr/bin/python + +import sys +import re + + +args = sys.argv +vexfilename = args[1] + +vexv = open(vexfilename, 'r') +lines = vexv.readlines() + + +# record port info +pnames = list() +pdirs = dict() +ppins = dict() +started = False; +for line in lines: + if not started: + if re.match('module VexRiscv', line): + started = True + else: + parts = line.split() + n = len(parts) + if n <= 1: + break + + pdir = parts[0] + pname = parts[-1] + pname = pname.rstrip(',') + + if re.match("\);$", pname): + pname.rstrip(");") + started = False + + pnames.append(pname) + + assert pdir == "input" or pdir == "output" + pdirs[pname] = pdir + + ppins[pname] = "" + if n == 4: + assert parts[1] == "reg" + ppins[pname] = parts[2] + if n == 3: + if parts[1] != "reg": + ppins[pname] = parts[1] + + + +# +# Wrapper port declaration +# +print("//") +print("// wrapper auto-generated from {}".format(vexfilename)) +print("//") +print("") +print("module VexRiscv (") +for pname in pnames: + if not re.match("CfuPlugin_bus", pname): + comma = "," if (pname != pnames[-1]) else "" + print(" {:10} {:10} {}{}".format(pdirs[pname], ppins[pname], pname, comma)) +print(");\n\n") + + + + +# +# CFU bus signals +# +for pname in pnames: + if re.match("CfuPlugin_bus", pname): + print(" wire {:10} {};".format(ppins[pname], pname)) + last_cfu_port = pname +print("\n\n") + + + +# +# inner VexRiscv instantiation +# +print("VexRiscv_inner VexRiscv_inner(") +for pname in pnames: + comma = "," if (pname != pnames[-1]) else "" + print(" .{}({}){}".format(pname, pname, comma)) +print(");\n\n") + + +# +# inner CFU instantiation +# +print("Cfu Cfu(") +for pname in pnames: + if re.match("CfuPlugin_bus_", pname): + parts = pname.split("_"); + parts[0] = "io" + cfu_pname = "_".join(parts) + comma = "," if (pname != last_cfu_port) else "" + print(" .{}({}){}".format(cfu_pname, pname, comma)) +print(");\n\n") + + +# +# finish wrapper modules +# +print("endmodule") + + + diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v new file mode 100644 index 0000000..95660f6 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v @@ -0,0 +1,103 @@ +// +// wrapper auto-generated from VexRiscv_FullCfu.v +// + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output iBusWishbone_CYC, + output iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + + + wire CfuPlugin_bus_cmd_valid; + wire CfuPlugin_bus_cmd_ready; + wire [2:0] CfuPlugin_bus_cmd_payload_function_id; + wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; + wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; + wire CfuPlugin_bus_rsp_valid; + wire CfuPlugin_bus_rsp_ready; + wire CfuPlugin_bus_rsp_payload_response_ok; + wire [31:0] CfuPlugin_bus_rsp_payload_outputs_0; + + + +VexRiscv_inner VexRiscv_inner( + .externalResetVector(externalResetVector), + .timerInterrupt(timerInterrupt), + .softwareInterrupt(softwareInterrupt), + .CfuPlugin_bus_cmd_valid(CfuPlugin_bus_cmd_valid), + .CfuPlugin_bus_cmd_ready(CfuPlugin_bus_cmd_ready), + .CfuPlugin_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), + .CfuPlugin_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), + .CfuPlugin_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), + .CfuPlugin_bus_rsp_valid(CfuPlugin_bus_rsp_valid), + .CfuPlugin_bus_rsp_ready(CfuPlugin_bus_rsp_ready), + .CfuPlugin_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), + .CfuPlugin_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), + .externalInterruptArray(externalInterruptArray), + .iBusWishbone_CYC(iBusWishbone_CYC), + .iBusWishbone_STB(iBusWishbone_STB), + .iBusWishbone_ACK(iBusWishbone_ACK), + .iBusWishbone_WE(iBusWishbone_WE), + .iBusWishbone_ADR(iBusWishbone_ADR), + .iBusWishbone_DAT_MISO(iBusWishbone_DAT_MISO), + .iBusWishbone_DAT_MOSI(iBusWishbone_DAT_MOSI), + .iBusWishbone_SEL(iBusWishbone_SEL), + .iBusWishbone_ERR(iBusWishbone_ERR), + .iBusWishbone_CTI(iBusWishbone_CTI), + .iBusWishbone_BTE(iBusWishbone_BTE), + .dBusWishbone_CYC(dBusWishbone_CYC), + .dBusWishbone_STB(dBusWishbone_STB), + .dBusWishbone_ACK(dBusWishbone_ACK), + .dBusWishbone_WE(dBusWishbone_WE), + .dBusWishbone_ADR(dBusWishbone_ADR), + .dBusWishbone_DAT_MISO(dBusWishbone_DAT_MISO), + .dBusWishbone_DAT_MOSI(dBusWishbone_DAT_MOSI), + .dBusWishbone_SEL(dBusWishbone_SEL), + .dBusWishbone_ERR(dBusWishbone_ERR), + .dBusWishbone_CTI(dBusWishbone_CTI), + .dBusWishbone_BTE(dBusWishbone_BTE), + .clk(clk), + .reset(reset) +); + + +Cfu Cfu( + .io_bus_cmd_valid(CfuPlugin_bus_cmd_valid), + .io_bus_cmd_ready(CfuPlugin_bus_cmd_ready), + .io_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), + .io_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), + .io_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), + .io_bus_rsp_valid(CfuPlugin_bus_rsp_valid), + .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), + .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), + .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0) +); + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v new file mode 100644 index 0000000..4190c12 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v @@ -0,0 +1,119 @@ +// +// wrapper auto-generated from VexRiscv_FullCfuDebug.v +// + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBusWishbone_CYC, + output iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + + + wire CfuPlugin_bus_cmd_valid; + wire CfuPlugin_bus_cmd_ready; + wire [2:0] CfuPlugin_bus_cmd_payload_function_id; + wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; + wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; + wire CfuPlugin_bus_rsp_valid; + wire CfuPlugin_bus_rsp_ready; + wire CfuPlugin_bus_rsp_payload_response_ok; + wire [31:0] CfuPlugin_bus_rsp_payload_outputs_0; + + + +VexRiscv_inner VexRiscv_inner( + .externalResetVector(externalResetVector), + .timerInterrupt(timerInterrupt), + .softwareInterrupt(softwareInterrupt), + .CfuPlugin_bus_cmd_valid(CfuPlugin_bus_cmd_valid), + .CfuPlugin_bus_cmd_ready(CfuPlugin_bus_cmd_ready), + .CfuPlugin_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), + .CfuPlugin_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), + .CfuPlugin_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), + .CfuPlugin_bus_rsp_valid(CfuPlugin_bus_rsp_valid), + .CfuPlugin_bus_rsp_ready(CfuPlugin_bus_rsp_ready), + .CfuPlugin_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), + .CfuPlugin_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), + .externalInterruptArray(externalInterruptArray), + .debug_bus_cmd_valid(debug_bus_cmd_valid), + .debug_bus_cmd_ready(debug_bus_cmd_ready), + .debug_bus_cmd_payload_wr(debug_bus_cmd_payload_wr), + .debug_bus_cmd_payload_address(debug_bus_cmd_payload_address), + .debug_bus_cmd_payload_data(debug_bus_cmd_payload_data), + .debug_bus_rsp_data(debug_bus_rsp_data), + .debug_resetOut(debug_resetOut), + .iBusWishbone_CYC(iBusWishbone_CYC), + .iBusWishbone_STB(iBusWishbone_STB), + .iBusWishbone_ACK(iBusWishbone_ACK), + .iBusWishbone_WE(iBusWishbone_WE), + .iBusWishbone_ADR(iBusWishbone_ADR), + .iBusWishbone_DAT_MISO(iBusWishbone_DAT_MISO), + .iBusWishbone_DAT_MOSI(iBusWishbone_DAT_MOSI), + .iBusWishbone_SEL(iBusWishbone_SEL), + .iBusWishbone_ERR(iBusWishbone_ERR), + .iBusWishbone_CTI(iBusWishbone_CTI), + .iBusWishbone_BTE(iBusWishbone_BTE), + .dBusWishbone_CYC(dBusWishbone_CYC), + .dBusWishbone_STB(dBusWishbone_STB), + .dBusWishbone_ACK(dBusWishbone_ACK), + .dBusWishbone_WE(dBusWishbone_WE), + .dBusWishbone_ADR(dBusWishbone_ADR), + .dBusWishbone_DAT_MISO(dBusWishbone_DAT_MISO), + .dBusWishbone_DAT_MOSI(dBusWishbone_DAT_MOSI), + .dBusWishbone_SEL(dBusWishbone_SEL), + .dBusWishbone_ERR(dBusWishbone_ERR), + .dBusWishbone_CTI(dBusWishbone_CTI), + .dBusWishbone_BTE(dBusWishbone_BTE), + .clk(clk), + .reset(reset), + .debugReset(debugReset) +); + + +Cfu Cfu( + .io_bus_cmd_valid(CfuPlugin_bus_cmd_valid), + .io_bus_cmd_ready(CfuPlugin_bus_cmd_ready), + .io_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), + .io_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), + .io_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), + .io_bus_rsp_valid(CfuPlugin_bus_rsp_valid), + .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), + .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), + .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0) +); + + +endmodule From ae3d1d7153024aab052ec3fbf108a667a0b1141f Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Wed, 7 Oct 2020 19:58:31 -0700 Subject: [PATCH 03/30] Add 'clk' input to CFU modules. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v | 4 ++-- pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v | 4 ++-- pythondata_cpu_vexriscv/verilog/genWrapper.py | 7 +++++-- pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v | 3 ++- .../verilog/wrapVexRiscv_FullCfuDebug.v | 3 ++- 5 files changed, 13 insertions(+), 8 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index a5bcb28..86a8ccc 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : f8290e79928d331d21410a57fea40abaca0e8d55 +// Generator : SpinalHDL v1.4.2 git head : e62dbc9f8bc45343959057cc2eae3a18943f0abf // Component : VexRiscv -// Git hash : f8290e79928d331d21410a57fea40abaca0e8d55 +// Git hash : e62dbc9f8bc45343959057cc2eae3a18943f0abf `define Input2Kind_defaultEncoding_type [0:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index 0cc7887..8954a5c 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : f8290e79928d331d21410a57fea40abaca0e8d55 +// Generator : SpinalHDL v1.4.2 git head : e62dbc9f8bc45343959057cc2eae3a18943f0abf // Component : VexRiscv -// Git hash : f8290e79928d331d21410a57fea40abaca0e8d55 +// Git hash : e62dbc9f8bc45343959057cc2eae3a18943f0abf `define Input2Kind_defaultEncoding_type [0:0] diff --git a/pythondata_cpu_vexriscv/verilog/genWrapper.py b/pythondata_cpu_vexriscv/verilog/genWrapper.py index dda538d..c850a71 100755 --- a/pythondata_cpu_vexriscv/verilog/genWrapper.py +++ b/pythondata_cpu_vexriscv/verilog/genWrapper.py @@ -73,6 +73,8 @@ if re.match("CfuPlugin_bus", pname): print(" wire {:10} {};".format(ppins[pname], pname)) last_cfu_port = pname + if pname == "clk": + last_cfu_port = pname print("\n\n") @@ -92,9 +94,10 @@ # print("Cfu Cfu(") for pname in pnames: - if re.match("CfuPlugin_bus_", pname): + if re.match("CfuPlugin_bus_|^clk$", pname): parts = pname.split("_"); - parts[0] = "io" + if parts[0] == "CfuPlugin": + parts[0] = "io" cfu_pname = "_".join(parts) comma = "," if (pname != last_cfu_port) else "" print(" .{}({}){}".format(cfu_pname, pname, comma)) diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v index 95660f6..d9dcf76 100644 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v @@ -96,7 +96,8 @@ Cfu Cfu( .io_bus_rsp_valid(CfuPlugin_bus_rsp_valid), .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), - .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0) + .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), + .clk(clk) ); diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v index 4190c12..3e71b34 100644 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v @@ -112,7 +112,8 @@ Cfu Cfu( .io_bus_rsp_valid(CfuPlugin_bus_rsp_valid), .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), - .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0) + .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), + .clk(clk) ); From 07a72e20035b64cf586cbf04df799cb4bf961010 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Wed, 4 Nov 2020 19:02:59 -0800 Subject: [PATCH 04/30] Add perf count CSRs; rebuild CFU VexRiscv Verilogs. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 4 +- .../verilog/VexRiscv_FullCfu.v | 2145 +++++++++------- .../verilog/VexRiscv_FullCfuDebug.v | 2243 +++++++++-------- pythondata_cpu_vexriscv/verilog/genWrapper.py | 2 +- .../main/scala/vexriscv/GenCoreDefault.scala | 32 + 5 files changed, 2424 insertions(+), 2002 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index b427867..bdc4398 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -34,14 +34,14 @@ VexRiscv_FullDebug.v: $(SRC) # CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --cfu true --outputFile VexRiscv_FullCfu" + sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --cfu true --perfCSRs 5 --outputFile VexRiscv_FullCfu" sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v /bin/mv tmp.v $@ ./genWrapper.py $@ > wrap$@ # CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfuDebug.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --cfu true --outputFile VexRiscv_FullCfuDebug" + sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --cfu true --perfCSRs 5 --outputFile VexRiscv_FullCfuDebug" sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v /bin/mv tmp.v $@ ./genWrapper.py $@ > wrap$@ diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index 86a8ccc..5d8ccda 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : e62dbc9f8bc45343959057cc2eae3a18943f0abf +// Generator : SpinalHDL v1.4.2 git head : b386c12cdfb49fee6855bbbd273eefd149b82dfe // Component : VexRiscv -// Git hash : e62dbc9f8bc45343959057cc2eae3a18943f0abf +// Git hash : b386c12cdfb49fee6855bbbd273eefd149b82dfe `define Input2Kind_defaultEncoding_type [0:0] @@ -87,37 +87,37 @@ module VexRiscv_inner ( input clk, input reset ); - wire _zz_189; - wire _zz_190; - wire _zz_191; - wire _zz_192; - wire _zz_193; - wire _zz_194; - wire _zz_195; - wire _zz_196; - reg _zz_197; - wire _zz_198; - wire [31:0] _zz_199; - wire _zz_200; - wire [31:0] _zz_201; - reg _zz_202; - wire _zz_203; wire _zz_204; - wire [31:0] _zz_205; + wire _zz_205; wire _zz_206; wire _zz_207; wire _zz_208; wire _zz_209; wire _zz_210; wire _zz_211; - wire _zz_212; + reg _zz_212; wire _zz_213; - wire [3:0] _zz_214; + wire [31:0] _zz_214; wire _zz_215; - wire _zz_216; - reg [31:0] _zz_217; - reg [31:0] _zz_218; - reg [31:0] _zz_219; + wire [31:0] _zz_216; + reg _zz_217; + wire _zz_218; + wire _zz_219; + wire [31:0] _zz_220; + wire _zz_221; + wire _zz_222; + wire _zz_223; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire [3:0] _zz_229; + wire _zz_230; + wire _zz_231; + reg [31:0] _zz_232; + reg [31:0] _zz_233; + reg [31:0] _zz_234; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -149,22 +149,7 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - wire _zz_228; - wire _zz_229; - wire _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire [1:0] _zz_235; + wire _zz_235; wire _zz_236; wire _zz_237; wire _zz_238; @@ -174,312 +159,327 @@ module VexRiscv_inner ( wire _zz_242; wire _zz_243; wire _zz_244; - wire [1:0] _zz_245; + wire _zz_245; wire _zz_246; wire _zz_247; wire _zz_248; wire _zz_249; - wire _zz_250; + wire [1:0] _zz_250; wire _zz_251; wire _zz_252; wire _zz_253; - wire [1:0] _zz_254; + wire _zz_254; wire _zz_255; - wire [1:0] _zz_256; - wire [51:0] _zz_257; - wire [51:0] _zz_258; - wire [51:0] _zz_259; - wire [32:0] _zz_260; - wire [51:0] _zz_261; - wire [49:0] _zz_262; - wire [51:0] _zz_263; - wire [49:0] _zz_264; - wire [51:0] _zz_265; - wire [32:0] _zz_266; - wire [31:0] _zz_267; - wire [32:0] _zz_268; - wire [0:0] _zz_269; - wire [0:0] _zz_270; - wire [0:0] _zz_271; - wire [0:0] _zz_272; - wire [0:0] _zz_273; - wire [0:0] _zz_274; - wire [0:0] _zz_275; - wire [0:0] _zz_276; - wire [0:0] _zz_277; - wire [0:0] _zz_278; - wire [0:0] _zz_279; - wire [0:0] _zz_280; - wire [0:0] _zz_281; - wire [0:0] _zz_282; - wire [0:0] _zz_283; + wire _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire [1:0] _zz_260; + wire _zz_261; + wire _zz_262; + wire _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire [1:0] _zz_269; + wire _zz_270; + wire [1:0] _zz_271; + wire [51:0] _zz_272; + wire [51:0] _zz_273; + wire [51:0] _zz_274; + wire [32:0] _zz_275; + wire [51:0] _zz_276; + wire [49:0] _zz_277; + wire [51:0] _zz_278; + wire [49:0] _zz_279; + wire [51:0] _zz_280; + wire [32:0] _zz_281; + wire [31:0] _zz_282; + wire [32:0] _zz_283; wire [0:0] _zz_284; wire [0:0] _zz_285; wire [0:0] _zz_286; - wire [3:0] _zz_287; - wire [2:0] _zz_288; - wire [31:0] _zz_289; - wire [11:0] _zz_290; - wire [31:0] _zz_291; - wire [19:0] _zz_292; - wire [11:0] _zz_293; - wire [31:0] _zz_294; - wire [31:0] _zz_295; - wire [19:0] _zz_296; - wire [11:0] _zz_297; - wire [2:0] _zz_298; - wire [2:0] _zz_299; + wire [0:0] _zz_287; + wire [0:0] _zz_288; + wire [0:0] _zz_289; + wire [0:0] _zz_290; + wire [0:0] _zz_291; + wire [0:0] _zz_292; + wire [0:0] _zz_293; + wire [0:0] _zz_294; + wire [0:0] _zz_295; + wire [0:0] _zz_296; + wire [0:0] _zz_297; + wire [0:0] _zz_298; + wire [0:0] _zz_299; wire [0:0] _zz_300; - wire [2:0] _zz_301; - wire [4:0] _zz_302; - wire [11:0] _zz_303; - wire [11:0] _zz_304; - wire [31:0] _zz_305; + wire [0:0] _zz_301; + wire [3:0] _zz_302; + wire [2:0] _zz_303; + wire [31:0] _zz_304; + wire [11:0] _zz_305; wire [31:0] _zz_306; - wire [31:0] _zz_307; - wire [31:0] _zz_308; + wire [19:0] _zz_307; + wire [11:0] _zz_308; wire [31:0] _zz_309; wire [31:0] _zz_310; - wire [31:0] _zz_311; + wire [19:0] _zz_311; wire [11:0] _zz_312; - wire [19:0] _zz_313; - wire [11:0] _zz_314; - wire [31:0] _zz_315; - wire [31:0] _zz_316; - wire [31:0] _zz_317; + wire [2:0] _zz_313; + wire [2:0] _zz_314; + wire [0:0] _zz_315; + wire [2:0] _zz_316; + wire [4:0] _zz_317; wire [11:0] _zz_318; - wire [19:0] _zz_319; - wire [11:0] _zz_320; - wire [2:0] _zz_321; - wire [1:0] _zz_322; - wire [1:0] _zz_323; - wire [1:0] _zz_324; - wire [1:0] _zz_325; - wire [2:0] _zz_326; + wire [11:0] _zz_319; + wire [31:0] _zz_320; + wire [31:0] _zz_321; + wire [31:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [31:0] _zz_326; wire [11:0] _zz_327; - wire [65:0] _zz_328; - wire [65:0] _zz_329; + wire [19:0] _zz_328; + wire [11:0] _zz_329; wire [31:0] _zz_330; wire [31:0] _zz_331; - wire [0:0] _zz_332; - wire [5:0] _zz_333; - wire [32:0] _zz_334; - wire [31:0] _zz_335; - wire [31:0] _zz_336; - wire [32:0] _zz_337; - wire [32:0] _zz_338; - wire [32:0] _zz_339; - wire [32:0] _zz_340; - wire [0:0] _zz_341; - wire [32:0] _zz_342; - wire [0:0] _zz_343; - wire [32:0] _zz_344; - wire [0:0] _zz_345; + wire [31:0] _zz_332; + wire [11:0] _zz_333; + wire [19:0] _zz_334; + wire [11:0] _zz_335; + wire [2:0] _zz_336; + wire [1:0] _zz_337; + wire [1:0] _zz_338; + wire [1:0] _zz_339; + wire [1:0] _zz_340; + wire [2:0] _zz_341; + wire [11:0] _zz_342; + wire [65:0] _zz_343; + wire [65:0] _zz_344; + wire [31:0] _zz_345; wire [31:0] _zz_346; wire [0:0] _zz_347; - wire [0:0] _zz_348; - wire [0:0] _zz_349; - wire [0:0] _zz_350; - wire [0:0] _zz_351; - wire [0:0] _zz_352; - wire [0:0] _zz_353; - wire [26:0] _zz_354; - wire _zz_355; - wire _zz_356; - wire [1:0] _zz_357; - wire [31:0] _zz_358; - wire [31:0] _zz_359; - wire [31:0] _zz_360; - wire _zz_361; + wire [5:0] _zz_348; + wire [32:0] _zz_349; + wire [31:0] _zz_350; + wire [31:0] _zz_351; + wire [32:0] _zz_352; + wire [32:0] _zz_353; + wire [32:0] _zz_354; + wire [32:0] _zz_355; + wire [0:0] _zz_356; + wire [32:0] _zz_357; + wire [0:0] _zz_358; + wire [32:0] _zz_359; + wire [0:0] _zz_360; + wire [31:0] _zz_361; wire [0:0] _zz_362; - wire [14:0] _zz_363; - wire [31:0] _zz_364; - wire [31:0] _zz_365; - wire [31:0] _zz_366; - wire _zz_367; + wire [0:0] _zz_363; + wire [0:0] _zz_364; + wire [0:0] _zz_365; + wire [0:0] _zz_366; + wire [0:0] _zz_367; wire [0:0] _zz_368; - wire [8:0] _zz_369; - wire [31:0] _zz_370; - wire [31:0] _zz_371; - wire [31:0] _zz_372; - wire _zz_373; - wire [0:0] _zz_374; - wire [2:0] _zz_375; + wire [26:0] _zz_369; + wire _zz_370; + wire _zz_371; + wire [1:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; + wire [31:0] _zz_375; wire _zz_376; - wire _zz_377; - wire _zz_378; + wire [0:0] _zz_377; + wire [14:0] _zz_378; wire [31:0] _zz_379; wire [31:0] _zz_380; - wire _zz_381; + wire [31:0] _zz_381; wire _zz_382; wire [0:0] _zz_383; - wire [26:0] _zz_384; + wire [8:0] _zz_384; wire [31:0] _zz_385; wire [31:0] _zz_386; wire [31:0] _zz_387; - wire [0:0] _zz_388; + wire _zz_388; wire [0:0] _zz_389; - wire [1:0] _zz_390; - wire [1:0] _zz_391; + wire [2:0] _zz_390; + wire _zz_391; wire _zz_392; - wire [0:0] _zz_393; - wire [21:0] _zz_394; + wire _zz_393; + wire [31:0] _zz_394; wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire [31:0] _zz_399; + wire _zz_396; + wire _zz_397; + wire [0:0] _zz_398; + wire [26:0] _zz_399; wire [31:0] _zz_400; - wire [0:0] _zz_401; - wire [0:0] _zz_402; - wire [2:0] _zz_403; - wire [2:0] _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [18:0] _zz_407; - wire [31:0] _zz_408; - wire [31:0] _zz_409; + wire [31:0] _zz_401; + wire [31:0] _zz_402; + wire [0:0] _zz_403; + wire [0:0] _zz_404; + wire [1:0] _zz_405; + wire [1:0] _zz_406; + wire _zz_407; + wire [0:0] _zz_408; + wire [21:0] _zz_409; wire [31:0] _zz_410; wire [31:0] _zz_411; - wire _zz_412; - wire _zz_413; + wire [31:0] _zz_412; + wire [31:0] _zz_413; wire [31:0] _zz_414; wire [31:0] _zz_415; - wire _zz_416; + wire [0:0] _zz_416; wire [0:0] _zz_417; - wire [0:0] _zz_418; - wire _zz_419; - wire [0:0] _zz_420; - wire [15:0] _zz_421; - wire [31:0] _zz_422; - wire _zz_423; - wire _zz_424; - wire _zz_425; - wire [2:0] _zz_426; - wire [2:0] _zz_427; + wire [2:0] _zz_418; + wire [2:0] _zz_419; + wire _zz_420; + wire [0:0] _zz_421; + wire [18:0] _zz_422; + wire [31:0] _zz_423; + wire [31:0] _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire _zz_427; wire _zz_428; - wire [0:0] _zz_429; - wire [12:0] _zz_430; + wire [31:0] _zz_429; + wire [31:0] _zz_430; wire _zz_431; - wire _zz_432; - wire _zz_433; - wire [0:0] _zz_434; - wire [2:0] _zz_435; - wire _zz_436; - wire [5:0] _zz_437; - wire [5:0] _zz_438; + wire [0:0] _zz_432; + wire [0:0] _zz_433; + wire _zz_434; + wire [0:0] _zz_435; + wire [15:0] _zz_436; + wire [31:0] _zz_437; + wire _zz_438; wire _zz_439; - wire [0:0] _zz_440; - wire [9:0] _zz_441; - wire [31:0] _zz_442; - wire [31:0] _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire [31:0] _zz_446; + wire _zz_440; + wire [2:0] _zz_441; + wire [2:0] _zz_442; + wire _zz_443; + wire [0:0] _zz_444; + wire [12:0] _zz_445; + wire _zz_446; wire _zz_447; - wire [0:0] _zz_448; + wire _zz_448; wire [0:0] _zz_449; - wire [31:0] _zz_450; + wire [2:0] _zz_450; wire _zz_451; - wire [0:0] _zz_452; - wire [3:0] _zz_453; - wire [0:0] _zz_454; - wire [3:0] _zz_455; - wire [5:0] _zz_456; - wire [5:0] _zz_457; - wire _zz_458; - wire [0:0] _zz_459; - wire [7:0] _zz_460; + wire [5:0] _zz_452; + wire [5:0] _zz_453; + wire _zz_454; + wire [0:0] _zz_455; + wire [9:0] _zz_456; + wire [31:0] _zz_457; + wire [31:0] _zz_458; + wire [31:0] _zz_459; + wire [31:0] _zz_460; wire [31:0] _zz_461; - wire [31:0] _zz_462; - wire [31:0] _zz_463; - wire [31:0] _zz_464; + wire _zz_462; + wire [0:0] _zz_463; + wire [0:0] _zz_464; wire [31:0] _zz_465; - wire [31:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; + wire _zz_466; + wire [0:0] _zz_467; + wire [3:0] _zz_468; wire [0:0] _zz_469; - wire [1:0] _zz_470; - wire _zz_471; - wire [0:0] _zz_472; - wire [1:0] _zz_473; + wire [3:0] _zz_470; + wire [5:0] _zz_471; + wire [5:0] _zz_472; + wire _zz_473; wire [0:0] _zz_474; - wire [3:0] _zz_475; - wire [0:0] _zz_476; - wire [0:0] _zz_477; - wire [1:0] _zz_478; - wire [1:0] _zz_479; - wire _zz_480; - wire [0:0] _zz_481; - wire [5:0] _zz_482; + wire [7:0] _zz_475; + wire [31:0] _zz_476; + wire [31:0] _zz_477; + wire [31:0] _zz_478; + wire [31:0] _zz_479; + wire [31:0] _zz_480; + wire [31:0] _zz_481; + wire [31:0] _zz_482; wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire _zz_485; + wire [0:0] _zz_484; + wire [1:0] _zz_485; wire _zz_486; - wire [31:0] _zz_487; - wire [31:0] _zz_488; - wire [31:0] _zz_489; - wire _zz_490; - wire _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire _zz_494; - wire [0:0] _zz_495; - wire [1:0] _zz_496; - wire [31:0] _zz_497; + wire [0:0] _zz_487; + wire [1:0] _zz_488; + wire [0:0] _zz_489; + wire [3:0] _zz_490; + wire [0:0] _zz_491; + wire [0:0] _zz_492; + wire [1:0] _zz_493; + wire [1:0] _zz_494; + wire _zz_495; + wire [0:0] _zz_496; + wire [5:0] _zz_497; wire [31:0] _zz_498; - wire _zz_499; + wire [31:0] _zz_499; wire _zz_500; - wire [0:0] _zz_501; - wire [0:0] _zz_502; - wire _zz_503; - wire [0:0] _zz_504; - wire [3:0] _zz_505; - wire [31:0] _zz_506; + wire _zz_501; + wire [31:0] _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire _zz_505; + wire _zz_506; wire [31:0] _zz_507; wire [31:0] _zz_508; - wire [31:0] _zz_509; - wire [31:0] _zz_510; - wire [31:0] _zz_511; + wire _zz_509; + wire [0:0] _zz_510; + wire [1:0] _zz_511; wire [31:0] _zz_512; - wire _zz_513; + wire [31:0] _zz_513; wire _zz_514; - wire [31:0] _zz_515; - wire [31:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; + wire _zz_515; + wire [0:0] _zz_516; + wire [0:0] _zz_517; + wire _zz_518; wire [0:0] _zz_519; - wire [2:0] _zz_520; - wire [0:0] _zz_521; - wire [0:0] _zz_522; - wire _zz_523; - wire [0:0] _zz_524; - wire [1:0] _zz_525; + wire [3:0] _zz_520; + wire [31:0] _zz_521; + wire [31:0] _zz_522; + wire [31:0] _zz_523; + wire [31:0] _zz_524; + wire [31:0] _zz_525; wire [31:0] _zz_526; wire [31:0] _zz_527; - wire [31:0] _zz_528; + wire _zz_528; wire _zz_529; - wire _zz_530; + wire [31:0] _zz_530; wire [31:0] _zz_531; - wire _zz_532; - wire [0:0] _zz_533; + wire [31:0] _zz_532; + wire [31:0] _zz_533; wire [0:0] _zz_534; - wire [0:0] _zz_535; + wire [2:0] _zz_535; wire [0:0] _zz_536; - wire [1:0] _zz_537; - wire [1:0] _zz_538; + wire [0:0] _zz_537; + wire _zz_538; wire [0:0] _zz_539; - wire [0:0] _zz_540; + wire [1:0] _zz_540; wire [31:0] _zz_541; wire [31:0] _zz_542; wire [31:0] _zz_543; - wire [31:0] _zz_544; - wire [31:0] _zz_545; + wire _zz_544; + wire _zz_545; wire [31:0] _zz_546; wire _zz_547; - wire _zz_548; - wire _zz_549; - wire [31:0] _zz_550; + wire [0:0] _zz_548; + wire [0:0] _zz_549; + wire [0:0] _zz_550; + wire [0:0] _zz_551; + wire [1:0] _zz_552; + wire [1:0] _zz_553; + wire [0:0] _zz_554; + wire [0:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire [31:0] _zz_559; + wire [31:0] _zz_560; + wire [31:0] _zz_561; + wire _zz_562; + wire _zz_563; + wire _zz_564; + wire [31:0] _zz_565; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1068,13 +1068,23 @@ module VexRiscv_inner ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_149; + reg [31:0] _zz_150; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [2:0] execute_CfuPlugin_functionsIds_0; - wire _zz_149; - reg [19:0] _zz_150; - reg [31:0] _zz_151; + wire _zz_159; + reg [19:0] _zz_160; + reg [31:0] _zz_161; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1106,18 +1116,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_152; + wire [31:0] _zz_162; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_153; - wire _zz_154; - wire _zz_155; - reg [32:0] _zz_156; + wire [31:0] _zz_163; + wire _zz_164; + wire _zz_165; + reg [32:0] _zz_166; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_157; - wire [31:0] _zz_158; + reg [31:0] _zz_167; + wire [31:0] _zz_168; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1203,18 +1213,18 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2946; reg execute_CsrPlugin_csr_3072; reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_2820; + reg execute_CsrPlugin_csr_2821; + reg execute_CsrPlugin_csr_2822; + reg execute_CsrPlugin_csr_2823; + reg execute_CsrPlugin_csr_2824; + reg execute_CsrPlugin_csr_2825; + reg execute_CsrPlugin_csr_2826; + reg execute_CsrPlugin_csr_2827; + reg execute_CsrPlugin_csr_2828; + reg execute_CsrPlugin_csr_2829; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; reg [31:0] _zz_169; reg [31:0] _zz_170; reg [31:0] _zz_171; @@ -1226,16 +1236,31 @@ module VexRiscv_inner ( reg [31:0] _zz_177; reg [31:0] _zz_178; reg [31:0] _zz_179; - reg [2:0] _zz_180; - reg _zz_181; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [2:0] _zz_195; + reg _zz_196; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_182; - wire _zz_183; - wire _zz_184; - wire _zz_185; - wire _zz_186; - wire _zz_187; - reg _zz_188; + reg [2:0] _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + wire _zz_201; + wire _zz_202; + reg _zz_203; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; @@ -1329,346 +1354,346 @@ module VexRiscv_inner ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_220 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_221 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_222 = 1'b1; - assign _zz_223 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_224 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_225 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_226 = ((_zz_194 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_227 = ((_zz_194 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_228 = ((_zz_194 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_229 = ((_zz_194 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_230 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_231 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_232 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_233 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_234 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_235 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_236 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_237 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_238 = (1'b0 || (! 1'b1)); - assign _zz_239 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_240 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_241 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_242 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_243 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_244 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_245 = execute_INSTRUCTION[13 : 12]; - assign _zz_246 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_247 = (! memory_arbitration_isStuck); - assign _zz_248 = (iBus_cmd_valid || (_zz_180 != 3'b000)); - assign _zz_249 = (_zz_216 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_250 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_251 = ((_zz_142 && 1'b1) && (! 1'b0)); - assign _zz_252 = ((_zz_143 && 1'b1) && (! 1'b0)); - assign _zz_253 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_254 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_255 = execute_INSTRUCTION[13]; - assign _zz_256 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_257 = ($signed(_zz_258) + $signed(_zz_263)); - assign _zz_258 = ($signed(_zz_259) + $signed(_zz_261)); - assign _zz_259 = 52'h0; - assign _zz_260 = {1'b0,memory_MUL_LL}; - assign _zz_261 = {{19{_zz_260[32]}}, _zz_260}; - assign _zz_262 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_263 = {{2{_zz_262[49]}}, _zz_262}; - assign _zz_264 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_265 = {{2{_zz_264[49]}}, _zz_264}; - assign _zz_266 = ($signed(_zz_268) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_267 = _zz_266[31 : 0]; - assign _zz_268 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_269 = _zz_91[33 : 33]; - assign _zz_270 = _zz_91[32 : 32]; - assign _zz_271 = _zz_91[31 : 31]; - assign _zz_272 = _zz_91[30 : 30]; - assign _zz_273 = _zz_91[28 : 28]; - assign _zz_274 = _zz_91[25 : 25]; - assign _zz_275 = _zz_91[17 : 17]; - assign _zz_276 = _zz_91[16 : 16]; - assign _zz_277 = _zz_91[13 : 13]; - assign _zz_278 = _zz_91[12 : 12]; - assign _zz_279 = _zz_91[11 : 11]; - assign _zz_280 = _zz_91[15 : 15]; - assign _zz_281 = _zz_91[5 : 5]; - assign _zz_282 = _zz_91[3 : 3]; - assign _zz_283 = _zz_91[20 : 20]; - assign _zz_284 = _zz_91[10 : 10]; - assign _zz_285 = _zz_91[4 : 4]; - assign _zz_286 = _zz_91[0 : 0]; - assign _zz_287 = (_zz_59 - 4'b0001); - assign _zz_288 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_289 = {29'd0, _zz_288}; - assign _zz_290 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_291 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_292 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_293 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_294 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_295 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_296 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_297 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_298 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_299 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_300 = execute_SRC_LESS; - assign _zz_301 = 3'b100; - assign _zz_302 = execute_INSTRUCTION[19 : 15]; - assign _zz_303 = execute_INSTRUCTION[31 : 20]; - assign _zz_304 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_305 = ($signed(_zz_306) + $signed(_zz_309)); - assign _zz_306 = ($signed(_zz_307) + $signed(_zz_308)); - assign _zz_307 = execute_SRC1; - assign _zz_308 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_309 = (execute_SRC_USE_SUB_LESS ? _zz_310 : _zz_311); - assign _zz_310 = 32'h00000001; - assign _zz_311 = 32'h0; - assign _zz_312 = execute_INSTRUCTION[31 : 20]; - assign _zz_313 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_314 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_315 = {_zz_130,execute_INSTRUCTION[31 : 20]}; - assign _zz_316 = {{_zz_132,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_317 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_235 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_236 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_237 = 1'b1; + assign _zz_238 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_239 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_240 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_241 = ((_zz_209 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_242 = ((_zz_209 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_243 = ((_zz_209 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_244 = ((_zz_209 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_245 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_246 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_247 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_248 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_249 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_250 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_251 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_253 = (1'b0 || (! 1'b1)); + assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_255 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_256 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_257 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_258 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_260 = execute_INSTRUCTION[13 : 12]; + assign _zz_261 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_262 = (! memory_arbitration_isStuck); + assign _zz_263 = (iBus_cmd_valid || (_zz_195 != 3'b000)); + assign _zz_264 = (_zz_231 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_265 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_266 = ((_zz_142 && 1'b1) && (! 1'b0)); + assign _zz_267 = ((_zz_143 && 1'b1) && (! 1'b0)); + assign _zz_268 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_269 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_270 = execute_INSTRUCTION[13]; + assign _zz_271 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_272 = ($signed(_zz_273) + $signed(_zz_278)); + assign _zz_273 = ($signed(_zz_274) + $signed(_zz_276)); + assign _zz_274 = 52'h0; + assign _zz_275 = {1'b0,memory_MUL_LL}; + assign _zz_276 = {{19{_zz_275[32]}}, _zz_275}; + assign _zz_277 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_278 = {{2{_zz_277[49]}}, _zz_277}; + assign _zz_279 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_280 = {{2{_zz_279[49]}}, _zz_279}; + assign _zz_281 = ($signed(_zz_283) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_282 = _zz_281[31 : 0]; + assign _zz_283 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_284 = _zz_91[33 : 33]; + assign _zz_285 = _zz_91[32 : 32]; + assign _zz_286 = _zz_91[31 : 31]; + assign _zz_287 = _zz_91[30 : 30]; + assign _zz_288 = _zz_91[28 : 28]; + assign _zz_289 = _zz_91[25 : 25]; + assign _zz_290 = _zz_91[17 : 17]; + assign _zz_291 = _zz_91[16 : 16]; + assign _zz_292 = _zz_91[13 : 13]; + assign _zz_293 = _zz_91[12 : 12]; + assign _zz_294 = _zz_91[11 : 11]; + assign _zz_295 = _zz_91[15 : 15]; + assign _zz_296 = _zz_91[5 : 5]; + assign _zz_297 = _zz_91[3 : 3]; + assign _zz_298 = _zz_91[20 : 20]; + assign _zz_299 = _zz_91[10 : 10]; + assign _zz_300 = _zz_91[4 : 4]; + assign _zz_301 = _zz_91[0 : 0]; + assign _zz_302 = (_zz_59 - 4'b0001); + assign _zz_303 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_304 = {29'd0, _zz_303}; + assign _zz_305 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_306 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_307 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_308 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_309 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_310 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_311 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_312 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_313 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_314 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_315 = execute_SRC_LESS; + assign _zz_316 = 3'b100; + assign _zz_317 = execute_INSTRUCTION[19 : 15]; assign _zz_318 = execute_INSTRUCTION[31 : 20]; - assign _zz_319 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_320 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_321 = 3'b100; - assign _zz_322 = (_zz_145 & (~ _zz_323)); - assign _zz_323 = (_zz_145 - 2'b01); - assign _zz_324 = (_zz_147 & (~ _zz_325)); - assign _zz_325 = (_zz_147 - 2'b01); - assign _zz_326 = execute_INSTRUCTION[14 : 12]; + assign _zz_319 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_320 = ($signed(_zz_321) + $signed(_zz_324)); + assign _zz_321 = ($signed(_zz_322) + $signed(_zz_323)); + assign _zz_322 = execute_SRC1; + assign _zz_323 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_324 = (execute_SRC_USE_SUB_LESS ? _zz_325 : _zz_326); + assign _zz_325 = 32'h00000001; + assign _zz_326 = 32'h0; assign _zz_327 = execute_INSTRUCTION[31 : 20]; - assign _zz_328 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_329 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_330 = writeBack_MUL_LOW[31 : 0]; - assign _zz_331 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_332 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_333 = {5'd0, _zz_332}; - assign _zz_334 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_335 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_336 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_337 = {_zz_152,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_338 = _zz_339; - assign _zz_339 = _zz_340; - assign _zz_340 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_153) : _zz_153)} + _zz_342); - assign _zz_341 = memory_DivPlugin_div_needRevert; - assign _zz_342 = {32'd0, _zz_341}; - assign _zz_343 = _zz_155; - assign _zz_344 = {32'd0, _zz_343}; - assign _zz_345 = _zz_154; - assign _zz_346 = {31'd0, _zz_345}; - assign _zz_347 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_348 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_349 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_350 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_351 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_352 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_353 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_354 = (iBus_cmd_payload_address >>> 5); - assign _zz_355 = 1'b1; - assign _zz_356 = 1'b1; - assign _zz_357 = {_zz_63,_zz_62}; - assign _zz_358 = 32'h0000106f; - assign _zz_359 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_360 = 32'h00001073; - assign _zz_361 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_362 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_363 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_364) == 32'h00000003),{(_zz_365 == _zz_366),{_zz_367,{_zz_368,_zz_369}}}}}}; - assign _zz_364 = 32'h0000207f; - assign _zz_365 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_366 = 32'h00000003; - assign _zz_367 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_368 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_369 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_370) == 32'h00005013),{(_zz_371 == _zz_372),{_zz_373,{_zz_374,_zz_375}}}}}}; - assign _zz_370 = 32'hbc00707f; - assign _zz_371 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_372 = 32'h00001013; - assign _zz_373 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_374 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_375 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_376 = decode_INSTRUCTION[31]; - assign _zz_377 = decode_INSTRUCTION[31]; - assign _zz_378 = decode_INSTRUCTION[7]; - assign _zz_379 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_380 = 32'h02004020; - assign _zz_381 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_382 = (_zz_95 != 1'b0); - assign _zz_383 = (((decode_INSTRUCTION & _zz_385) == 32'h00000050) != 1'b0); - assign _zz_384 = {((_zz_386 == _zz_387) != 1'b0),{({_zz_388,_zz_389} != 2'b00),{(_zz_390 != _zz_391),{_zz_392,{_zz_393,_zz_394}}}}}; - assign _zz_385 = 32'h00203050; - assign _zz_386 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_387 = 32'h00000050; - assign _zz_388 = ((decode_INSTRUCTION & _zz_395) == 32'h00001050); - assign _zz_389 = ((decode_INSTRUCTION & _zz_396) == 32'h00002050); - assign _zz_390 = {_zz_94,(_zz_397 == _zz_398)}; - assign _zz_391 = 2'b00; - assign _zz_392 = ((_zz_399 == _zz_400) != 1'b0); - assign _zz_393 = ({_zz_401,_zz_402} != 2'b00); - assign _zz_394 = {(_zz_403 != _zz_404),{_zz_405,{_zz_406,_zz_407}}}; - assign _zz_395 = 32'h00001050; - assign _zz_396 = 32'h00002050; - assign _zz_397 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_398 = 32'h00000004; - assign _zz_399 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_400 = 32'h00000040; - assign _zz_401 = ((decode_INSTRUCTION & _zz_408) == 32'h00005010); - assign _zz_402 = ((decode_INSTRUCTION & _zz_409) == 32'h00005020); - assign _zz_403 = {(_zz_410 == _zz_411),{_zz_412,_zz_413}}; - assign _zz_404 = 3'b000; - assign _zz_405 = ((_zz_414 == _zz_415) != 1'b0); - assign _zz_406 = (_zz_416 != 1'b0); - assign _zz_407 = {(_zz_417 != _zz_418),{_zz_419,{_zz_420,_zz_421}}}; - assign _zz_408 = 32'h00007034; - assign _zz_409 = 32'h02007064; - assign _zz_410 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_411 = 32'h40001010; - assign _zz_412 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_413 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_414 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_415 = 32'h00000024; - assign _zz_416 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_417 = ((decode_INSTRUCTION & _zz_422) == 32'h00002000); - assign _zz_418 = 1'b0; - assign _zz_419 = ({_zz_423,_zz_424} != 2'b00); - assign _zz_420 = (_zz_425 != 1'b0); - assign _zz_421 = {(_zz_426 != _zz_427),{_zz_428,{_zz_429,_zz_430}}}; - assign _zz_422 = 32'h00003000; - assign _zz_423 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_424 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_425 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_426 = {_zz_95,{_zz_431,_zz_432}}; - assign _zz_427 = 3'b000; - assign _zz_428 = ({_zz_433,{_zz_434,_zz_435}} != 5'h0); - assign _zz_429 = (_zz_436 != 1'b0); - assign _zz_430 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; - assign _zz_431 = ((decode_INSTRUCTION & _zz_442) == 32'h00000020); - assign _zz_432 = ((decode_INSTRUCTION & _zz_443) == 32'h00000020); - assign _zz_433 = ((decode_INSTRUCTION & _zz_444) == 32'h00002040); - assign _zz_434 = (_zz_445 == _zz_446); - assign _zz_435 = {_zz_447,{_zz_448,_zz_449}}; - assign _zz_436 = ((decode_INSTRUCTION & _zz_450) == 32'h00000020); - assign _zz_437 = {_zz_451,{_zz_452,_zz_453}}; - assign _zz_438 = 6'h0; - assign _zz_439 = ({_zz_454,_zz_455} != 5'h0); - assign _zz_440 = (_zz_456 != _zz_457); - assign _zz_441 = {_zz_458,{_zz_459,_zz_460}}; - assign _zz_442 = 32'h00000034; - assign _zz_443 = 32'h00000064; - assign _zz_444 = 32'h00002040; - assign _zz_445 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_446 = 32'h00001040; - assign _zz_447 = ((decode_INSTRUCTION & _zz_461) == 32'h00000040); - assign _zz_448 = (_zz_462 == _zz_463); - assign _zz_449 = (_zz_464 == _zz_465); - assign _zz_450 = 32'h00000020; - assign _zz_451 = ((decode_INSTRUCTION & _zz_466) == 32'h00000008); - assign _zz_452 = (_zz_467 == _zz_468); - assign _zz_453 = {_zz_93,{_zz_469,_zz_470}}; - assign _zz_454 = _zz_93; - assign _zz_455 = {_zz_471,{_zz_472,_zz_473}}; - assign _zz_456 = {_zz_94,{_zz_474,_zz_475}}; - assign _zz_457 = 6'h0; - assign _zz_458 = ({_zz_476,_zz_477} != 2'b00); - assign _zz_459 = (_zz_478 != _zz_479); - assign _zz_460 = {_zz_480,{_zz_481,_zz_482}}; - assign _zz_461 = 32'h00000050; - assign _zz_462 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_463 = 32'h00000040; - assign _zz_464 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_465 = 32'h0; - assign _zz_466 = 32'h00000008; - assign _zz_467 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_468 = 32'h00000040; - assign _zz_469 = (_zz_483 == _zz_484); - assign _zz_470 = {_zz_485,_zz_486}; - assign _zz_471 = ((decode_INSTRUCTION & _zz_487) == 32'h00002010); - assign _zz_472 = (_zz_488 == _zz_489); - assign _zz_473 = {_zz_490,_zz_491}; - assign _zz_474 = (_zz_492 == _zz_493); - assign _zz_475 = {_zz_494,{_zz_495,_zz_496}}; - assign _zz_476 = _zz_93; - assign _zz_477 = (_zz_497 == _zz_498); - assign _zz_478 = {_zz_93,_zz_499}; - assign _zz_479 = 2'b00; - assign _zz_480 = (_zz_500 != 1'b0); - assign _zz_481 = (_zz_501 != _zz_502); - assign _zz_482 = {_zz_503,{_zz_504,_zz_505}}; - assign _zz_483 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_484 = 32'h00004020; - assign _zz_485 = ((decode_INSTRUCTION & _zz_506) == 32'h00000010); - assign _zz_486 = ((decode_INSTRUCTION & _zz_507) == 32'h00000020); - assign _zz_487 = 32'h00002030; - assign _zz_488 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_489 = 32'h00000010; - assign _zz_490 = ((decode_INSTRUCTION & _zz_508) == 32'h00002020); - assign _zz_491 = ((decode_INSTRUCTION & _zz_509) == 32'h00000020); - assign _zz_492 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_493 = 32'h00001010; - assign _zz_494 = ((decode_INSTRUCTION & _zz_510) == 32'h00002010); - assign _zz_495 = (_zz_511 == _zz_512); - assign _zz_496 = {_zz_513,_zz_514}; - assign _zz_497 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_498 = 32'h00000020; - assign _zz_499 = ((decode_INSTRUCTION & _zz_515) == 32'h0); - assign _zz_500 = ((decode_INSTRUCTION & _zz_516) == 32'h00004010); - assign _zz_501 = (_zz_517 == _zz_518); - assign _zz_502 = 1'b0; - assign _zz_503 = ({_zz_519,_zz_520} != 4'b0000); - assign _zz_504 = (_zz_521 != _zz_522); - assign _zz_505 = {_zz_523,{_zz_524,_zz_525}}; - assign _zz_506 = 32'h00000030; - assign _zz_507 = 32'h02000020; - assign _zz_508 = 32'h02002060; - assign _zz_509 = 32'h02003020; - assign _zz_510 = 32'h00002010; - assign _zz_511 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_512 = 32'h00000010; - assign _zz_513 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_514 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_515 = 32'h00000020; - assign _zz_516 = 32'h00004014; - assign _zz_517 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_518 = 32'h00002010; - assign _zz_519 = ((decode_INSTRUCTION & _zz_526) == 32'h0); - assign _zz_520 = {(_zz_527 == _zz_528),{_zz_529,_zz_530}}; - assign _zz_521 = ((decode_INSTRUCTION & _zz_531) == 32'h0); - assign _zz_522 = 1'b0; - assign _zz_523 = ({_zz_532,{_zz_533,_zz_534}} != 3'b000); - assign _zz_524 = ({_zz_535,_zz_536} != 2'b00); - assign _zz_525 = {(_zz_537 != _zz_538),(_zz_539 != _zz_540)}; - assign _zz_526 = 32'h00000044; - assign _zz_527 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_528 = 32'h0; - assign _zz_529 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_530 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_531 = 32'h00000058; - assign _zz_532 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_533 = ((decode_INSTRUCTION & _zz_541) == 32'h00002010); - assign _zz_534 = ((decode_INSTRUCTION & _zz_542) == 32'h40000030); - assign _zz_535 = ((decode_INSTRUCTION & _zz_543) == 32'h00000004); - assign _zz_536 = _zz_92; - assign _zz_537 = {(_zz_544 == _zz_545),_zz_92}; - assign _zz_538 = 2'b00; - assign _zz_539 = ((decode_INSTRUCTION & _zz_546) == 32'h00001004); - assign _zz_540 = 1'b0; - assign _zz_541 = 32'h00002014; - assign _zz_542 = 32'h40000034; - assign _zz_543 = 32'h00000014; - assign _zz_544 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_545 = 32'h00000004; - assign _zz_546 = 32'h00005054; - assign _zz_547 = execute_INSTRUCTION[31]; - assign _zz_548 = execute_INSTRUCTION[31]; - assign _zz_549 = execute_INSTRUCTION[7]; - assign _zz_550 = 32'h0; + assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_329 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_330 = {_zz_130,execute_INSTRUCTION[31 : 20]}; + assign _zz_331 = {{_zz_132,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_332 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_333 = execute_INSTRUCTION[31 : 20]; + assign _zz_334 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_335 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_336 = 3'b100; + assign _zz_337 = (_zz_145 & (~ _zz_338)); + assign _zz_338 = (_zz_145 - 2'b01); + assign _zz_339 = (_zz_147 & (~ _zz_340)); + assign _zz_340 = (_zz_147 - 2'b01); + assign _zz_341 = execute_INSTRUCTION[14 : 12]; + assign _zz_342 = execute_INSTRUCTION[31 : 20]; + assign _zz_343 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_344 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_345 = writeBack_MUL_LOW[31 : 0]; + assign _zz_346 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_347 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_348 = {5'd0, _zz_347}; + assign _zz_349 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_350 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_351 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_352 = {_zz_162,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_353 = _zz_354; + assign _zz_354 = _zz_355; + assign _zz_355 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_163) : _zz_163)} + _zz_357); + assign _zz_356 = memory_DivPlugin_div_needRevert; + assign _zz_357 = {32'd0, _zz_356}; + assign _zz_358 = _zz_165; + assign _zz_359 = {32'd0, _zz_358}; + assign _zz_360 = _zz_164; + assign _zz_361 = {31'd0, _zz_360}; + assign _zz_362 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_363 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_364 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_365 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_366 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_367 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_368 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_369 = (iBus_cmd_payload_address >>> 5); + assign _zz_370 = 1'b1; + assign _zz_371 = 1'b1; + assign _zz_372 = {_zz_63,_zz_62}; + assign _zz_373 = 32'h0000106f; + assign _zz_374 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_375 = 32'h00001073; + assign _zz_376 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_377 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_378 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_379) == 32'h00000003),{(_zz_380 == _zz_381),{_zz_382,{_zz_383,_zz_384}}}}}}; + assign _zz_379 = 32'h0000207f; + assign _zz_380 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_381 = 32'h00000003; + assign _zz_382 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_383 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_384 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_385) == 32'h00005013),{(_zz_386 == _zz_387),{_zz_388,{_zz_389,_zz_390}}}}}}; + assign _zz_385 = 32'hbc00707f; + assign _zz_386 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_387 = 32'h00001013; + assign _zz_388 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_389 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_390 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_391 = decode_INSTRUCTION[31]; + assign _zz_392 = decode_INSTRUCTION[31]; + assign _zz_393 = decode_INSTRUCTION[7]; + assign _zz_394 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_395 = 32'h02004020; + assign _zz_396 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_397 = (_zz_95 != 1'b0); + assign _zz_398 = (((decode_INSTRUCTION & _zz_400) == 32'h00000050) != 1'b0); + assign _zz_399 = {((_zz_401 == _zz_402) != 1'b0),{({_zz_403,_zz_404} != 2'b00),{(_zz_405 != _zz_406),{_zz_407,{_zz_408,_zz_409}}}}}; + assign _zz_400 = 32'h00203050; + assign _zz_401 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_402 = 32'h00000050; + assign _zz_403 = ((decode_INSTRUCTION & _zz_410) == 32'h00001050); + assign _zz_404 = ((decode_INSTRUCTION & _zz_411) == 32'h00002050); + assign _zz_405 = {_zz_94,(_zz_412 == _zz_413)}; + assign _zz_406 = 2'b00; + assign _zz_407 = ((_zz_414 == _zz_415) != 1'b0); + assign _zz_408 = ({_zz_416,_zz_417} != 2'b00); + assign _zz_409 = {(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}; + assign _zz_410 = 32'h00001050; + assign _zz_411 = 32'h00002050; + assign _zz_412 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_413 = 32'h00000004; + assign _zz_414 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_415 = 32'h00000040; + assign _zz_416 = ((decode_INSTRUCTION & _zz_423) == 32'h00005010); + assign _zz_417 = ((decode_INSTRUCTION & _zz_424) == 32'h00005020); + assign _zz_418 = {(_zz_425 == _zz_426),{_zz_427,_zz_428}}; + assign _zz_419 = 3'b000; + assign _zz_420 = ((_zz_429 == _zz_430) != 1'b0); + assign _zz_421 = (_zz_431 != 1'b0); + assign _zz_422 = {(_zz_432 != _zz_433),{_zz_434,{_zz_435,_zz_436}}}; + assign _zz_423 = 32'h00007034; + assign _zz_424 = 32'h02007064; + assign _zz_425 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_426 = 32'h40001010; + assign _zz_427 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_428 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_429 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_430 = 32'h00000024; + assign _zz_431 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_432 = ((decode_INSTRUCTION & _zz_437) == 32'h00002000); + assign _zz_433 = 1'b0; + assign _zz_434 = ({_zz_438,_zz_439} != 2'b00); + assign _zz_435 = (_zz_440 != 1'b0); + assign _zz_436 = {(_zz_441 != _zz_442),{_zz_443,{_zz_444,_zz_445}}}; + assign _zz_437 = 32'h00003000; + assign _zz_438 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_439 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_440 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_441 = {_zz_95,{_zz_446,_zz_447}}; + assign _zz_442 = 3'b000; + assign _zz_443 = ({_zz_448,{_zz_449,_zz_450}} != 5'h0); + assign _zz_444 = (_zz_451 != 1'b0); + assign _zz_445 = {(_zz_452 != _zz_453),{_zz_454,{_zz_455,_zz_456}}}; + assign _zz_446 = ((decode_INSTRUCTION & _zz_457) == 32'h00000020); + assign _zz_447 = ((decode_INSTRUCTION & _zz_458) == 32'h00000020); + assign _zz_448 = ((decode_INSTRUCTION & _zz_459) == 32'h00002040); + assign _zz_449 = (_zz_460 == _zz_461); + assign _zz_450 = {_zz_462,{_zz_463,_zz_464}}; + assign _zz_451 = ((decode_INSTRUCTION & _zz_465) == 32'h00000020); + assign _zz_452 = {_zz_466,{_zz_467,_zz_468}}; + assign _zz_453 = 6'h0; + assign _zz_454 = ({_zz_469,_zz_470} != 5'h0); + assign _zz_455 = (_zz_471 != _zz_472); + assign _zz_456 = {_zz_473,{_zz_474,_zz_475}}; + assign _zz_457 = 32'h00000034; + assign _zz_458 = 32'h00000064; + assign _zz_459 = 32'h00002040; + assign _zz_460 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_461 = 32'h00001040; + assign _zz_462 = ((decode_INSTRUCTION & _zz_476) == 32'h00000040); + assign _zz_463 = (_zz_477 == _zz_478); + assign _zz_464 = (_zz_479 == _zz_480); + assign _zz_465 = 32'h00000020; + assign _zz_466 = ((decode_INSTRUCTION & _zz_481) == 32'h00000008); + assign _zz_467 = (_zz_482 == _zz_483); + assign _zz_468 = {_zz_93,{_zz_484,_zz_485}}; + assign _zz_469 = _zz_93; + assign _zz_470 = {_zz_486,{_zz_487,_zz_488}}; + assign _zz_471 = {_zz_94,{_zz_489,_zz_490}}; + assign _zz_472 = 6'h0; + assign _zz_473 = ({_zz_491,_zz_492} != 2'b00); + assign _zz_474 = (_zz_493 != _zz_494); + assign _zz_475 = {_zz_495,{_zz_496,_zz_497}}; + assign _zz_476 = 32'h00000050; + assign _zz_477 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_478 = 32'h00000040; + assign _zz_479 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_480 = 32'h0; + assign _zz_481 = 32'h00000008; + assign _zz_482 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_483 = 32'h00000040; + assign _zz_484 = (_zz_498 == _zz_499); + assign _zz_485 = {_zz_500,_zz_501}; + assign _zz_486 = ((decode_INSTRUCTION & _zz_502) == 32'h00002010); + assign _zz_487 = (_zz_503 == _zz_504); + assign _zz_488 = {_zz_505,_zz_506}; + assign _zz_489 = (_zz_507 == _zz_508); + assign _zz_490 = {_zz_509,{_zz_510,_zz_511}}; + assign _zz_491 = _zz_93; + assign _zz_492 = (_zz_512 == _zz_513); + assign _zz_493 = {_zz_93,_zz_514}; + assign _zz_494 = 2'b00; + assign _zz_495 = (_zz_515 != 1'b0); + assign _zz_496 = (_zz_516 != _zz_517); + assign _zz_497 = {_zz_518,{_zz_519,_zz_520}}; + assign _zz_498 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_499 = 32'h00004020; + assign _zz_500 = ((decode_INSTRUCTION & _zz_521) == 32'h00000010); + assign _zz_501 = ((decode_INSTRUCTION & _zz_522) == 32'h00000020); + assign _zz_502 = 32'h00002030; + assign _zz_503 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_504 = 32'h00000010; + assign _zz_505 = ((decode_INSTRUCTION & _zz_523) == 32'h00002020); + assign _zz_506 = ((decode_INSTRUCTION & _zz_524) == 32'h00000020); + assign _zz_507 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_508 = 32'h00001010; + assign _zz_509 = ((decode_INSTRUCTION & _zz_525) == 32'h00002010); + assign _zz_510 = (_zz_526 == _zz_527); + assign _zz_511 = {_zz_528,_zz_529}; + assign _zz_512 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_513 = 32'h00000020; + assign _zz_514 = ((decode_INSTRUCTION & _zz_530) == 32'h0); + assign _zz_515 = ((decode_INSTRUCTION & _zz_531) == 32'h00004010); + assign _zz_516 = (_zz_532 == _zz_533); + assign _zz_517 = 1'b0; + assign _zz_518 = ({_zz_534,_zz_535} != 4'b0000); + assign _zz_519 = (_zz_536 != _zz_537); + assign _zz_520 = {_zz_538,{_zz_539,_zz_540}}; + assign _zz_521 = 32'h00000030; + assign _zz_522 = 32'h02000020; + assign _zz_523 = 32'h02002060; + assign _zz_524 = 32'h02003020; + assign _zz_525 = 32'h00002010; + assign _zz_526 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_527 = 32'h00000010; + assign _zz_528 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_529 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_530 = 32'h00000020; + assign _zz_531 = 32'h00004014; + assign _zz_532 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_533 = 32'h00002010; + assign _zz_534 = ((decode_INSTRUCTION & _zz_541) == 32'h0); + assign _zz_535 = {(_zz_542 == _zz_543),{_zz_544,_zz_545}}; + assign _zz_536 = ((decode_INSTRUCTION & _zz_546) == 32'h0); + assign _zz_537 = 1'b0; + assign _zz_538 = ({_zz_547,{_zz_548,_zz_549}} != 3'b000); + assign _zz_539 = ({_zz_550,_zz_551} != 2'b00); + assign _zz_540 = {(_zz_552 != _zz_553),(_zz_554 != _zz_555)}; + assign _zz_541 = 32'h00000044; + assign _zz_542 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_543 = 32'h0; + assign _zz_544 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_545 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_546 = 32'h00000058; + assign _zz_547 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_548 = ((decode_INSTRUCTION & _zz_556) == 32'h00002010); + assign _zz_549 = ((decode_INSTRUCTION & _zz_557) == 32'h40000030); + assign _zz_550 = ((decode_INSTRUCTION & _zz_558) == 32'h00000004); + assign _zz_551 = _zz_92; + assign _zz_552 = {(_zz_559 == _zz_560),_zz_92}; + assign _zz_553 = 2'b00; + assign _zz_554 = ((decode_INSTRUCTION & _zz_561) == 32'h00001004); + assign _zz_555 = 1'b0; + assign _zz_556 = 32'h00002014; + assign _zz_557 = 32'h40000034; + assign _zz_558 = 32'h00000014; + assign _zz_559 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_560 = 32'h00000004; + assign _zz_561 = 32'h00005054; + assign _zz_562 = execute_INSTRUCTION[31]; + assign _zz_563 = execute_INSTRUCTION[31]; + assign _zz_564 = execute_INSTRUCTION[7]; + assign _zz_565 = 32'h0; always @ (posedge clk) begin - if(_zz_355) begin - _zz_217 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_370) begin + _zz_232 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_356) begin - _zz_218 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_371) begin + _zz_233 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1679,13 +1704,13 @@ module VexRiscv_inner ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_189 ), //i - .io_cpu_prefetch_isValid (_zz_190 ), //i + .io_flush (_zz_204 ), //i + .io_cpu_prefetch_isValid (_zz_205 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_191 ), //i - .io_cpu_fetch_isStuck (_zz_192 ), //i - .io_cpu_fetch_isRemoved (_zz_193 ), //i + .io_cpu_fetch_isValid (_zz_206 ), //i + .io_cpu_fetch_isStuck (_zz_207 ), //i + .io_cpu_fetch_isRemoved (_zz_208 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1697,8 +1722,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_194 ), //i - .io_cpu_decode_isStuck (_zz_195 ), //i + .io_cpu_decode_isValid (_zz_209 ), //i + .io_cpu_decode_isStuck (_zz_210 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1706,8 +1731,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_196 ), //i - .io_cpu_fill_valid (_zz_197 ), //i + .io_cpu_decode_isUser (_zz_211 ), //i + .io_cpu_fill_valid (_zz_212 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1720,50 +1745,50 @@ module VexRiscv_inner ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_198 ), //i - .io_cpu_execute_address (_zz_199[31:0] ), //i + .io_cpu_execute_isValid (_zz_213 ), //i + .io_cpu_execute_address (_zz_214[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_86[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_memory_isValid (_zz_200 ), //i + .io_cpu_memory_isValid (_zz_215 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_201[31:0] ), //i + .io_cpu_memory_address (_zz_216[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_202 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_217 ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_203 ), //i + .io_cpu_writeBack_isValid (_zz_218 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_204 ), //i + .io_cpu_writeBack_isUser (_zz_219 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_205[31:0] ), //i + .io_cpu_writeBack_address (_zz_220[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_206 ), //i - .io_cpu_writeBack_fence_SR (_zz_207 ), //i - .io_cpu_writeBack_fence_SO (_zz_208 ), //i - .io_cpu_writeBack_fence_SI (_zz_209 ), //i - .io_cpu_writeBack_fence_PW (_zz_210 ), //i - .io_cpu_writeBack_fence_PR (_zz_211 ), //i - .io_cpu_writeBack_fence_PO (_zz_212 ), //i - .io_cpu_writeBack_fence_PI (_zz_213 ), //i - .io_cpu_writeBack_fence_FM (_zz_214[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_221 ), //i + .io_cpu_writeBack_fence_SR (_zz_222 ), //i + .io_cpu_writeBack_fence_SO (_zz_223 ), //i + .io_cpu_writeBack_fence_SI (_zz_224 ), //i + .io_cpu_writeBack_fence_PW (_zz_225 ), //i + .io_cpu_writeBack_fence_PR (_zz_226 ), //i + .io_cpu_writeBack_fence_PO (_zz_227 ), //i + .io_cpu_writeBack_fence_PI (_zz_228 ), //i + .io_cpu_writeBack_fence_FM (_zz_229[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_215 ), //i + .io_cpu_flush_valid (_zz_230 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_216 ), //i + .io_mem_cmd_ready (_zz_231 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1779,18 +1804,18 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_357) + case(_zz_372) 2'b00 : begin - _zz_219 = DBusCachedPlugin_redoBranch_payload; + _zz_234 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_219 = CsrPlugin_jumpInterface_payload; + _zz_234 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_219 = BranchPlugin_jumpInterface_payload; + _zz_234 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_219 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_234 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2545,7 +2570,7 @@ module VexRiscv_inner ( end `endif - assign memory_MUL_LOW = ($signed(_zz_257) + $signed(_zz_265)); + assign memory_MUL_LOW = ($signed(_zz_272) + $signed(_zz_280)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2554,41 +2579,41 @@ module VexRiscv_inner ( assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_267; + assign execute_SHIFT_RIGHT = _zz_282; assign execute_REGFILE_WRITE_DATA = _zz_106; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_199[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_214[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_269[0]; - assign decode_IS_RS1_SIGNED = _zz_270[0]; - assign decode_IS_DIV = _zz_271[0]; + assign decode_IS_RS2_SIGNED = _zz_284[0]; + assign decode_IS_RS1_SIGNED = _zz_285[0]; + assign decode_IS_DIV = _zz_286[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_272[0]; + assign decode_IS_MUL = _zz_287[0]; assign decode_CfuPlugin_CFU_ENCODING = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_273[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_288[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_274[0]; + assign decode_IS_CSR = _zz_289[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_275[0]; - assign decode_MEMORY_MANAGMENT = _zz_276[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_290[0]; + assign decode_MEMORY_MANAGMENT = _zz_291[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_277[0]; + assign decode_MEMORY_WR = _zz_292[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_278[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_279[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_293[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_294[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2627,11 +2652,11 @@ module VexRiscv_inner ( assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_COND_RESULT = _zz_128; assign execute_BRANCH_CTRL = _zz_34; - assign decode_RS2_USE = _zz_280[0]; - assign decode_RS1_USE = _zz_281[0]; + assign decode_RS2_USE = _zz_295[0]; + assign decode_RS1_USE = _zz_296[0]; always @ (*) begin _zz_35 = execute_REGFILE_WRITE_DATA; - if(_zz_220)begin + if(_zz_235)begin _zz_35 = execute_CsrPlugin_readData; end end @@ -2649,21 +2674,21 @@ module VexRiscv_inner ( decode_RS2 = _zz_119; end end - if(_zz_221)begin - if(_zz_222)begin + if(_zz_236)begin + if(_zz_237)begin if(_zz_121)begin decode_RS2 = _zz_55; end end end - if(_zz_223)begin + if(_zz_238)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_123)begin decode_RS2 = _zz_36; end end end - if(_zz_224)begin + if(_zz_239)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_125)begin decode_RS2 = _zz_35; @@ -2679,21 +2704,21 @@ module VexRiscv_inner ( decode_RS1 = _zz_119; end end - if(_zz_221)begin - if(_zz_222)begin + if(_zz_236)begin + if(_zz_237)begin if(_zz_120)begin decode_RS1 = _zz_55; end end end - if(_zz_223)begin + if(_zz_238)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_122)begin decode_RS1 = _zz_36; end end end - if(_zz_224)begin + if(_zz_239)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_124)begin decode_RS1 = _zz_35; @@ -2720,7 +2745,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_36 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_225)begin + if(_zz_240)begin _zz_36 = memory_DivPlugin_div_result; end end @@ -2733,8 +2758,8 @@ module VexRiscv_inner ( assign _zz_39 = execute_PC; assign execute_SRC2_CTRL = _zz_40; assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_282[0]; - assign decode_SRC_ADD_ZERO = _zz_283[0]; + assign decode_SRC_USE_SUB_LESS = _zz_297[0]; + assign decode_SRC_ADD_ZERO = _zz_298[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_42; @@ -2752,25 +2777,25 @@ module VexRiscv_inner ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_284[0]; + decode_REGFILE_WRITE_VALID = _zz_299[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_358) == 32'h00000003),{(_zz_359 == _zz_360),{_zz_361,{_zz_362,_zz_363}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_373) == 32'h00000003),{(_zz_374 == _zz_375),{_zz_376,{_zz_377,_zz_378}}}}}}} != 22'h0); always @ (*) begin _zz_55 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_55 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_256) + case(_zz_271) 2'b00 : begin - _zz_55 = _zz_330; + _zz_55 = _zz_345; end default : begin - _zz_55 = _zz_331; + _zz_55 = _zz_346; end endcase end @@ -2789,32 +2814,32 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_285[0]; - assign decode_FLUSH_ALL = _zz_286[0]; + assign decode_MEMORY_ENABLE = _zz_300[0]; + assign decode_FLUSH_ALL = _zz_301[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_226)begin + if(_zz_241)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_227)begin + if(_zz_242)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_228)begin + if(_zz_243)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_229)begin + if(_zz_244)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2860,7 +2885,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_230)begin + if(_zz_245)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2874,25 +2899,25 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_230)begin + if(_zz_245)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_215 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_230 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end if(((dataCache_1_io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_231)begin + if(_zz_246)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_220)begin + if(_zz_235)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2928,7 +2953,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_225)begin + if(_zz_240)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2938,7 +2963,7 @@ module VexRiscv_inner ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_232)begin + if(_zz_247)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2952,7 +2977,7 @@ module VexRiscv_inner ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_232)begin + if(_zz_247)begin memory_arbitration_flushNext = 1'b1; end end @@ -2990,10 +3015,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_233)begin + if(_zz_248)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_234)begin + if(_zz_249)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3007,10 +3032,10 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_233)begin + if(_zz_248)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_234)begin + if(_zz_249)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3024,7 +3049,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_231)begin + if(_zz_246)begin CsrPlugin_inWfi = 1'b1; end end @@ -3032,21 +3057,21 @@ module VexRiscv_inner ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_233)begin + if(_zz_248)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_234)begin + if(_zz_249)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_233)begin + if(_zz_248)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_234)begin - case(_zz_235) + if(_zz_249)begin + case(_zz_250) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3062,11 +3087,11 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_59 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_60 = (_zz_59 & (~ _zz_287)); + assign _zz_60 = (_zz_59 & (~ _zz_302)); assign _zz_61 = _zz_60[3]; assign _zz_62 = (_zz_60[1] || _zz_61); assign _zz_63 = (_zz_60[2] || _zz_61); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_219; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_234; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3086,7 +3111,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_289); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_304); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3177,7 +3202,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_73 = _zz_290[11]; + assign _zz_73 = _zz_305[11]; always @ (*) begin _zz_74[18] = _zz_73; _zz_74[17] = _zz_73; @@ -3201,13 +3226,13 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_291[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_306[31])); if(_zz_79)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_75 = _zz_292[19]; + assign _zz_75 = _zz_307[19]; always @ (*) begin _zz_76[10] = _zz_75; _zz_76[9] = _zz_75; @@ -3222,7 +3247,7 @@ module VexRiscv_inner ( _zz_76[0] = _zz_75; end - assign _zz_77 = _zz_293[11]; + assign _zz_77 = _zz_308[11]; always @ (*) begin _zz_78[18] = _zz_77; _zz_78[17] = _zz_77; @@ -3248,16 +3273,16 @@ module VexRiscv_inner ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_79 = _zz_294[1]; + _zz_79 = _zz_309[1]; end default : begin - _zz_79 = _zz_295[1]; + _zz_79 = _zz_310[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_80 = _zz_296[19]; + assign _zz_80 = _zz_311[19]; always @ (*) begin _zz_81[10] = _zz_80; _zz_81[9] = _zz_80; @@ -3272,7 +3297,7 @@ module VexRiscv_inner ( _zz_81[0] = _zz_80; end - assign _zz_82 = _zz_297[11]; + assign _zz_82 = _zz_312[11]; always @ (*) begin _zz_83[18] = _zz_82; _zz_83[17] = _zz_82; @@ -3295,7 +3320,7 @@ module VexRiscv_inner ( _zz_83[0] = _zz_82; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_81,{{{_zz_376,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_83,{{{_zz_377,_zz_378},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_81,{{{_zz_391,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_83,{{{_zz_392,_zz_393},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3304,52 +3329,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_190 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_191 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_192 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_191; + assign _zz_205 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_206 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_207 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_206; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_194 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_195 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_196 = (CsrPlugin_privilege == 2'b00); + assign _zz_209 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_210 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_211 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_229)begin + if(_zz_244)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_227)begin + if(_zz_242)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_197 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_227)begin - _zz_197 = 1'b1; + _zz_212 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_242)begin + _zz_212 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_228)begin + if(_zz_243)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_226)begin + if(_zz_241)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_228)begin + if(_zz_243)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_226)begin + if(_zz_241)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3359,9 +3384,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_189 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_204 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_216 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_231 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3388,8 +3413,8 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_198 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_199 = execute_SRC_ADD; + assign _zz_213 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_214 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3404,27 +3429,27 @@ module VexRiscv_inner ( endcase end - assign _zz_215 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_200 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_201 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_200; + assign _zz_230 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_215 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_216 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_215; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_201; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_216; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_202 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_217 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_202 = 1'b1; + _zz_217 = 1'b1; end end - assign _zz_203 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_204 = (CsrPlugin_privilege == 2'b00); - assign _zz_205 = writeBack_REGFILE_WRITE_DATA; + assign _zz_218 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_219 = (CsrPlugin_privilege == 2'b00); + assign _zz_220 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_236)begin + if(_zz_251)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3434,7 +3459,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_236)begin + if(_zz_251)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3453,12 +3478,12 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_236)begin + if(_zz_251)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_298}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_313}; end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_299}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_314}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); @@ -3534,7 +3559,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_254) + case(_zz_269) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_88; end @@ -3568,7 +3593,7 @@ module VexRiscv_inner ( assign _zz_94 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_95 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); assign _zz_96 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_91 = {(_zz_96 != 1'b0),{(_zz_96 != 1'b0),{((_zz_379 == _zz_380) != 1'b0),{(_zz_381 != 1'b0),{1'b0,{_zz_382,{_zz_383,_zz_384}}}}}}}; + assign _zz_91 = {(_zz_96 != 1'b0),{(_zz_96 != 1'b0),{((_zz_394 == _zz_395) != 1'b0),{(_zz_396 != 1'b0),{1'b0,{_zz_397,{_zz_398,_zz_399}}}}}}}; assign _zz_97 = _zz_91[2 : 1]; assign _zz_54 = _zz_97; assign _zz_98 = _zz_91[7 : 6]; @@ -3590,8 +3615,8 @@ module VexRiscv_inner ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_217; - assign decode_RegFilePlugin_rs2Data = _zz_218; + assign decode_RegFilePlugin_rs1Data = _zz_232; + assign decode_RegFilePlugin_rs2Data = _zz_233; always @ (*) begin lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); if(_zz_105)begin @@ -3621,7 +3646,7 @@ module VexRiscv_inner ( _zz_106 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_106 = {31'd0, _zz_300}; + _zz_106 = {31'd0, _zz_315}; end default : begin _zz_106 = execute_SRC_ADD_SUB; @@ -3635,18 +3660,18 @@ module VexRiscv_inner ( _zz_107 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_107 = {29'd0, _zz_301}; + _zz_107 = {29'd0, _zz_316}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_107 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_107 = {27'd0, _zz_302}; + _zz_107 = {27'd0, _zz_317}; end endcase end - assign _zz_108 = _zz_303[11]; + assign _zz_108 = _zz_318[11]; always @ (*) begin _zz_109[19] = _zz_108; _zz_109[18] = _zz_108; @@ -3670,7 +3695,7 @@ module VexRiscv_inner ( _zz_109[0] = _zz_108; end - assign _zz_110 = _zz_304[11]; + assign _zz_110 = _zz_319[11]; always @ (*) begin _zz_111[19] = _zz_110; _zz_111[18] = _zz_110; @@ -3712,7 +3737,7 @@ module VexRiscv_inner ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_305; + execute_SrcPlugin_addSub = _zz_320; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3793,22 +3818,22 @@ module VexRiscv_inner ( always @ (*) begin _zz_115 = 1'b0; - if(_zz_237)begin - if(_zz_238)begin + if(_zz_252)begin + if(_zz_253)begin if(_zz_120)begin _zz_115 = 1'b1; end end end - if(_zz_239)begin - if(_zz_240)begin + if(_zz_254)begin + if(_zz_255)begin if(_zz_122)begin _zz_115 = 1'b1; end end end - if(_zz_241)begin - if(_zz_242)begin + if(_zz_256)begin + if(_zz_257)begin if(_zz_124)begin _zz_115 = 1'b1; end @@ -3821,22 +3846,22 @@ module VexRiscv_inner ( always @ (*) begin _zz_116 = 1'b0; - if(_zz_237)begin - if(_zz_238)begin + if(_zz_252)begin + if(_zz_253)begin if(_zz_121)begin _zz_116 = 1'b1; end end end - if(_zz_239)begin - if(_zz_240)begin + if(_zz_254)begin + if(_zz_255)begin if(_zz_123)begin _zz_116 = 1'b1; end end end - if(_zz_241)begin - if(_zz_242)begin + if(_zz_256)begin + if(_zz_257)begin if(_zz_125)begin _zz_116 = 1'b1; end @@ -3884,7 +3909,7 @@ module VexRiscv_inner ( endcase end - assign _zz_129 = _zz_312[11]; + assign _zz_129 = _zz_327[11]; always @ (*) begin _zz_130[19] = _zz_129; _zz_130[18] = _zz_129; @@ -3908,7 +3933,7 @@ module VexRiscv_inner ( _zz_130[0] = _zz_129; end - assign _zz_131 = _zz_313[19]; + assign _zz_131 = _zz_328[19]; always @ (*) begin _zz_132[10] = _zz_131; _zz_132[9] = _zz_131; @@ -3923,7 +3948,7 @@ module VexRiscv_inner ( _zz_132[0] = _zz_131; end - assign _zz_133 = _zz_314[11]; + assign _zz_133 = _zz_329[11]; always @ (*) begin _zz_134[18] = _zz_133; _zz_134[17] = _zz_133; @@ -3949,13 +3974,13 @@ module VexRiscv_inner ( always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_135 = (_zz_315[1] ^ execute_RS1[1]); + _zz_135 = (_zz_330[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_135 = _zz_316[1]; + _zz_135 = _zz_331[1]; end default : begin - _zz_135 = _zz_317[1]; + _zz_135 = _zz_332[1]; end endcase end @@ -3972,7 +3997,7 @@ module VexRiscv_inner ( endcase end - assign _zz_136 = _zz_318[11]; + assign _zz_136 = _zz_333[11]; always @ (*) begin _zz_137[19] = _zz_136; _zz_137[18] = _zz_136; @@ -4002,15 +4027,15 @@ module VexRiscv_inner ( execute_BranchPlugin_branch_src2 = {_zz_137,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_139,{{{_zz_547,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_141,{{{_zz_548,_zz_549},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_139,{{{_zz_562,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_141,{{{_zz_563,_zz_564},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_321}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_336}; end end endcase end - assign _zz_138 = _zz_319[19]; + assign _zz_138 = _zz_334[19]; always @ (*) begin _zz_139[10] = _zz_138; _zz_139[9] = _zz_138; @@ -4025,7 +4050,7 @@ module VexRiscv_inner ( _zz_139[0] = _zz_138; end - assign _zz_140 = _zz_320[11]; + assign _zz_140 = _zz_335[11]; always @ (*) begin _zz_141[18] = _zz_140; _zz_141[17] = _zz_140; @@ -4068,12 +4093,12 @@ module VexRiscv_inner ( assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); assign _zz_145 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_146 = _zz_322[0]; + assign _zz_146 = _zz_337[0]; assign _zz_147 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_148 = _zz_324[0]; + assign _zz_148 = _zz_339[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_230)begin + if(_zz_245)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4093,7 +4118,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_232)begin + if(_zz_247)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4242,6 +4267,46 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end + if(execute_CsrPlugin_csr_2820)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2822)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2824)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2826)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2828)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end if(execute_CsrPlugin_csr_3008)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4269,20 +4334,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_243)begin + if(_zz_258)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_244)begin + if(_zz_259)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_243)begin + if(_zz_258)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_244)begin + if(_zz_259)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4301,7 +4366,7 @@ module VexRiscv_inner ( assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_255) + case(_zz_270) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4314,45 +4379,45 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_326; + assign execute_CfuPlugin_functionsIds_0 = _zz_341; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_149 = _zz_327[11]; - always @ (*) begin - _zz_150[19] = _zz_149; - _zz_150[18] = _zz_149; - _zz_150[17] = _zz_149; - _zz_150[16] = _zz_149; - _zz_150[15] = _zz_149; - _zz_150[14] = _zz_149; - _zz_150[13] = _zz_149; - _zz_150[12] = _zz_149; - _zz_150[11] = _zz_149; - _zz_150[10] = _zz_149; - _zz_150[9] = _zz_149; - _zz_150[8] = _zz_149; - _zz_150[7] = _zz_149; - _zz_150[6] = _zz_149; - _zz_150[5] = _zz_149; - _zz_150[4] = _zz_149; - _zz_150[3] = _zz_149; - _zz_150[2] = _zz_149; - _zz_150[1] = _zz_149; - _zz_150[0] = _zz_149; + assign _zz_159 = _zz_342[11]; + always @ (*) begin + _zz_160[19] = _zz_159; + _zz_160[18] = _zz_159; + _zz_160[17] = _zz_159; + _zz_160[16] = _zz_159; + _zz_160[15] = _zz_159; + _zz_160[14] = _zz_159; + _zz_160[13] = _zz_159; + _zz_160[12] = _zz_159; + _zz_160[11] = _zz_159; + _zz_160[10] = _zz_159; + _zz_160[9] = _zz_159; + _zz_160[8] = _zz_159; + _zz_160[7] = _zz_159; + _zz_160[6] = _zz_159; + _zz_160[5] = _zz_159; + _zz_160[4] = _zz_159; + _zz_160[3] = _zz_159; + _zz_160[2] = _zz_159; + _zz_160[1] = _zz_159; + _zz_160[0] = _zz_159; end always @ (*) begin case(execute_CfuPlugin_CFU_ENCODING) `Input2Kind_defaultEncoding_RS : begin - _zz_151 = execute_RS2; + _zz_161 = execute_RS2; end default : begin - _zz_151 = {_zz_150,execute_INSTRUCTION[31 : 20]}; + _zz_161 = {_zz_160,execute_INSTRUCTION[31 : 20]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_151; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_161; assign CfuPlugin_bus_rsp_ready = ((1'b1 && (! memory_CfuPlugin_rsp_valid)) || memory_CfuPlugin_rsp_ready); assign memory_CfuPlugin_rsp_valid = CfuPlugin_bus_rsp_m2sPipe_rValid; assign memory_CfuPlugin_rsp_payload_response_ok = CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; @@ -4378,7 +4443,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_245) + case(_zz_260) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4392,7 +4457,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_245) + case(_zz_260) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4411,12 +4476,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_328) + $signed(_zz_329)); + assign writeBack_MulPlugin_result = ($signed(_zz_343) + $signed(_zz_344)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_225)begin - if(_zz_246)begin + if(_zz_240)begin + if(_zz_261)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4424,7 +4489,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_247)begin + if(_zz_262)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4435,28 +4500,28 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_333); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_348); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_152 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_152[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_334); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_335 : _zz_336); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_337[31:0]; - assign _zz_153 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_154 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_155 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_162 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_162[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_349); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_350 : _zz_351); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_352[31:0]; + assign _zz_163 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_164 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_165 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_156[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_156[31 : 0] = execute_RS1; + _zz_166[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_166[31 : 0] = execute_RS1; end - assign _zz_158 = (_zz_157 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_158 != 32'h0); + assign _zz_168 = (_zz_167 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_168 != 32'h0); assign _zz_29 = decode_SRC1_CTRL; assign _zz_27 = _zz_54; assign _zz_41 = decode_to_execute_SRC1_CTRL; @@ -4508,202 +4573,237 @@ module VexRiscv_inner ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_159 = 32'h0; + _zz_169 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_159[12 : 0] = 13'h1000; - _zz_159[25 : 20] = 6'h20; + _zz_169[12 : 0] = 13'h1000; + _zz_169[25 : 20] = 6'h20; end end always @ (*) begin - _zz_160 = 32'h0; + _zz_170 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_160[3 : 0] = 4'b1011; + _zz_170[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_161 = 32'h0; + _zz_171 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_161[4 : 0] = 5'h16; + _zz_171[4 : 0] = 5'h16; end end always @ (*) begin - _zz_162 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_162[5 : 0] = 6'h21; + _zz_172[5 : 0] = 6'h21; end end always @ (*) begin - _zz_163 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_163[31 : 30] = CsrPlugin_misa_base; - _zz_163[25 : 0] = CsrPlugin_misa_extensions; + _zz_173[31 : 30] = CsrPlugin_misa_base; + _zz_173[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_164 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_164[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_164[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_164[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_174[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_174[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_174[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_165 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_165[11 : 11] = CsrPlugin_mip_MEIP; - _zz_165[7 : 7] = CsrPlugin_mip_MTIP; - _zz_165[3 : 3] = CsrPlugin_mip_MSIP; + _zz_175[11 : 11] = CsrPlugin_mip_MEIP; + _zz_175[7 : 7] = CsrPlugin_mip_MTIP; + _zz_175[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_166 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_166[11 : 11] = CsrPlugin_mie_MEIE; - _zz_166[7 : 7] = CsrPlugin_mie_MTIE; - _zz_166[3 : 3] = CsrPlugin_mie_MSIE; + _zz_176[11 : 11] = CsrPlugin_mie_MEIE; + _zz_176[7 : 7] = CsrPlugin_mie_MTIE; + _zz_176[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_167 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_167[31 : 2] = CsrPlugin_mtvec_base; - _zz_167[1 : 0] = CsrPlugin_mtvec_mode; + _zz_177[31 : 2] = CsrPlugin_mtvec_base; + _zz_177[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_168 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_168[31 : 0] = CsrPlugin_mepc; + _zz_178[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_169 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_169[31 : 0] = CsrPlugin_mscratch; + _zz_179[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_170 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_170[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_170[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_180[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_180[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_171[31 : 0] = CsrPlugin_mtval; + _zz_181[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_172[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_182[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_173[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_183[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_174[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_184[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_175[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_185[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_176[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_186[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_177[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_187[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_188 = 32'h0; + if(execute_CsrPlugin_csr_2820)begin + _zz_188[31 : 0] = _zz_149; + end + end + + always @ (*) begin + _zz_189 = 32'h0; + if(execute_CsrPlugin_csr_2822)begin + _zz_189[31 : 0] = _zz_151; + end + end + + always @ (*) begin + _zz_190 = 32'h0; + if(execute_CsrPlugin_csr_2824)begin + _zz_190[31 : 0] = _zz_153; + end + end + + always @ (*) begin + _zz_191 = 32'h0; + if(execute_CsrPlugin_csr_2826)begin + _zz_191[31 : 0] = _zz_155; + end + end + + always @ (*) begin + _zz_192 = 32'h0; + if(execute_CsrPlugin_csr_2828)begin + _zz_192[31 : 0] = _zz_157; + end + end + + always @ (*) begin + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_178[31 : 0] = _zz_157; + _zz_193[31 : 0] = _zz_167; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_179[31 : 0] = _zz_158; + _zz_194[31 : 0] = _zz_168; end end - assign execute_CsrPlugin_readData = (((((_zz_159 | _zz_160) | (_zz_161 | _zz_162)) | ((_zz_550 | _zz_163) | (_zz_164 | _zz_165))) | (((_zz_166 | _zz_167) | (_zz_168 | _zz_169)) | ((_zz_170 | _zz_171) | (_zz_172 | _zz_173)))) | (((_zz_174 | _zz_175) | (_zz_176 | _zz_177)) | (_zz_178 | _zz_179))); - assign iBusWishbone_ADR = {_zz_354,_zz_180}; - assign iBusWishbone_CTI = ((_zz_180 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_169 | _zz_170) | (_zz_171 | _zz_172)) | ((_zz_565 | _zz_173) | (_zz_174 | _zz_175))) | (((_zz_176 | _zz_177) | (_zz_178 | _zz_179)) | ((_zz_180 | _zz_181) | (_zz_182 | _zz_183)))) | ((((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191))) | ((_zz_192 | _zz_193) | _zz_194))); + assign iBusWishbone_ADR = {_zz_369,_zz_195}; + assign iBusWishbone_CTI = ((_zz_195 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_248)begin + if(_zz_263)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_248)begin + if(_zz_263)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_181; + assign iBus_rsp_valid = _zz_196; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_187 = (dBus_cmd_payload_length != 3'b000); - assign _zz_183 = dBus_cmd_valid; - assign _zz_185 = dBus_cmd_payload_wr; - assign _zz_186 = (_zz_182 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_184 && (_zz_185 || _zz_186)); - assign dBusWishbone_ADR = ((_zz_187 ? {{dBus_cmd_payload_address[31 : 5],_zz_182},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_187 ? (_zz_186 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_202 = (dBus_cmd_payload_length != 3'b000); + assign _zz_198 = dBus_cmd_valid; + assign _zz_200 = dBus_cmd_payload_wr; + assign _zz_201 = (_zz_197 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_199 && (_zz_200 || _zz_201)); + assign dBusWishbone_ADR = ((_zz_202 ? {{dBus_cmd_payload_address[31 : 5],_zz_197},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_202 ? (_zz_201 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_185 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_185; + assign dBusWishbone_SEL = (_zz_200 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_200; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_184 = (_zz_183 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_183; - assign dBusWishbone_STB = _zz_183; - assign dBus_rsp_valid = _zz_188; + assign _zz_199 = (_zz_198 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_198; + assign dBusWishbone_STB = _zz_198; + assign dBus_rsp_valid = _zz_203; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4750,17 +4850,17 @@ module VexRiscv_inner ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_m2sPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_157 <= 32'h0; + _zz_167 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; memory_to_writeBack_INSTRUCTION <= 32'h0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_180 <= 3'b000; - _zz_181 <= 1'b0; - _zz_182 <= 3'b000; - _zz_188 <= 1'b0; + _zz_195 <= 3'b000; + _zz_196 <= 1'b0; + _zz_197 <= 3'b000; + _zz_203 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -4841,7 +4941,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_249)begin + if(_zz_264)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -4873,14 +4973,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_250)begin - if(_zz_251)begin + if(_zz_265)begin + if(_zz_266)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_252)begin + if(_zz_267)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_253)begin + if(_zz_268)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4905,7 +5005,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_233)begin + if(_zz_248)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4916,8 +5016,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_234)begin - case(_zz_235) + if(_zz_249)begin + case(_zz_250) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4980,35 +5080,35 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_347[0]; - CsrPlugin_mstatus_MIE <= _zz_348[0]; + CsrPlugin_mstatus_MPIE <= _zz_362[0]; + CsrPlugin_mstatus_MIE <= _zz_363[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_350[0]; - CsrPlugin_mie_MTIE <= _zz_351[0]; - CsrPlugin_mie_MSIE <= _zz_352[0]; + CsrPlugin_mie_MEIE <= _zz_365[0]; + CsrPlugin_mie_MTIE <= _zz_366[0]; + CsrPlugin_mie_MSIE <= _zz_367[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_248)begin + if(_zz_263)begin if(iBusWishbone_ACK)begin - _zz_180 <= (_zz_180 + 3'b001); + _zz_195 <= (_zz_195 + 3'b001); end end - _zz_181 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_183 && _zz_184))begin - _zz_182 <= (_zz_182 + 3'b001); - if(_zz_186)begin - _zz_182 <= 3'b000; + _zz_196 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_198 && _zz_199))begin + _zz_197 <= (_zz_197 + 3'b001); + if(_zz_201)begin + _zz_197 <= 3'b000; end end - _zz_188 <= ((_zz_183 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_203 <= ((_zz_198 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5022,7 +5122,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_249)begin + if(_zz_264)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5049,7 +5149,7 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_230)begin + if(_zz_245)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_146 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_146 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end @@ -5057,7 +5157,7 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_232)begin + if(_zz_247)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); end @@ -5065,21 +5165,21 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_250)begin - if(_zz_251)begin + if(_zz_265)begin + if(_zz_266)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_252)begin + if(_zz_267)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_253)begin + if(_zz_268)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_233)begin + if(_zz_248)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5093,6 +5193,21 @@ module VexRiscv_inner ( end endcase end + if(_zz_150[0])begin + _zz_149 <= (_zz_149 + 32'h00000001); + end + if(_zz_152[0])begin + _zz_151 <= (_zz_151 + 32'h00000001); + end + if(_zz_154[0])begin + _zz_153 <= (_zz_153 + 32'h00000001); + end + if(_zz_156[0])begin + _zz_155 <= (_zz_155 + 32'h00000001); + end + if(_zz_158[0])begin + _zz_157 <= (_zz_157 + 32'h00000001); + end if(CfuPlugin_bus_rsp_ready)begin CfuPlugin_bus_rsp_m2sPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; @@ -5103,20 +5218,20 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_225)begin - if(_zz_246)begin + if(_zz_240)begin + if(_zz_261)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_338[31:0]; + memory_DivPlugin_div_result <= _zz_353[31:0]; end end end - if(_zz_247)begin + if(_zz_262)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_155 ? (~ _zz_156) : _zz_156) + _zz_344); - memory_DivPlugin_rs2 <= ((_zz_154 ? (~ execute_RS2) : execute_RS2) + _zz_346); - memory_DivPlugin_div_needRevert <= ((_zz_155 ^ (_zz_154 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_165 ? (~ _zz_166) : _zz_166) + _zz_359); + memory_DivPlugin_rs2 <= ((_zz_164 ? (~ execute_RS2) : execute_RS2) + _zz_361); + memory_DivPlugin_div_needRevert <= ((_zz_165 ^ (_zz_164 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5365,6 +5480,36 @@ module VexRiscv_inner ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end @@ -5373,7 +5518,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_349[0]; + CsrPlugin_mip_MSIP <= _zz_364[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5394,7 +5539,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_353[0]; + CsrPlugin_mcause_interrupt <= _zz_368[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5423,6 +5568,56 @@ module VexRiscv_inner ( CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end end + if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_149 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_150 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index 8954a5c..0e42a8b 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : e62dbc9f8bc45343959057cc2eae3a18943f0abf +// Generator : SpinalHDL v1.4.2 git head : b386c12cdfb49fee6855bbbd273eefd149b82dfe // Component : VexRiscv -// Git hash : e62dbc9f8bc45343959057cc2eae3a18943f0abf +// Git hash : b386c12cdfb49fee6855bbbd273eefd149b82dfe `define Input2Kind_defaultEncoding_type [0:0] @@ -95,37 +95,37 @@ module VexRiscv_inner ( input reset, input debugReset ); - wire _zz_192; - wire _zz_193; - wire _zz_194; - wire _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - reg _zz_200; - wire _zz_201; - wire [31:0] _zz_202; - wire _zz_203; - wire [31:0] _zz_204; - reg _zz_205; - wire _zz_206; wire _zz_207; - wire [31:0] _zz_208; + wire _zz_208; wire _zz_209; wire _zz_210; wire _zz_211; wire _zz_212; wire _zz_213; wire _zz_214; - wire _zz_215; + reg _zz_215; wire _zz_216; - wire [3:0] _zz_217; + wire [31:0] _zz_217; wire _zz_218; - wire _zz_219; - reg [31:0] _zz_220; - reg [31:0] _zz_221; - reg [31:0] _zz_222; + wire [31:0] _zz_219; + reg _zz_220; + wire _zz_221; + wire _zz_222; + wire [31:0] _zz_223; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire [3:0] _zz_232; + wire _zz_233; + wire _zz_234; + reg [31:0] _zz_235; + reg [31:0] _zz_236; + reg [31:0] _zz_237; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -157,25 +157,10 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_223; - wire _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - wire _zz_228; - wire _zz_229; - wire _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; wire _zz_238; wire _zz_239; wire _zz_240; - wire [1:0] _zz_241; + wire _zz_241; wire _zz_242; wire _zz_243; wire _zz_244; @@ -185,323 +170,338 @@ module VexRiscv_inner ( wire _zz_248; wire _zz_249; wire _zz_250; - wire [1:0] _zz_251; + wire _zz_251; wire _zz_252; wire _zz_253; - wire [5:0] _zz_254; + wire _zz_254; wire _zz_255; - wire _zz_256; + wire [1:0] _zz_256; wire _zz_257; wire _zz_258; wire _zz_259; wire _zz_260; - wire [1:0] _zz_261; + wire _zz_261; wire _zz_262; - wire [1:0] _zz_263; - wire [51:0] _zz_264; - wire [51:0] _zz_265; - wire [51:0] _zz_266; - wire [32:0] _zz_267; - wire [51:0] _zz_268; - wire [49:0] _zz_269; - wire [51:0] _zz_270; - wire [49:0] _zz_271; - wire [51:0] _zz_272; - wire [32:0] _zz_273; - wire [31:0] _zz_274; - wire [32:0] _zz_275; - wire [0:0] _zz_276; - wire [0:0] _zz_277; - wire [0:0] _zz_278; - wire [0:0] _zz_279; - wire [0:0] _zz_280; - wire [0:0] _zz_281; - wire [0:0] _zz_282; - wire [0:0] _zz_283; - wire [0:0] _zz_284; - wire [0:0] _zz_285; - wire [0:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; - wire [0:0] _zz_289; - wire [0:0] _zz_290; + wire _zz_263; + wire _zz_264; + wire _zz_265; + wire [1:0] _zz_266; + wire _zz_267; + wire _zz_268; + wire [5:0] _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire _zz_274; + wire _zz_275; + wire [1:0] _zz_276; + wire _zz_277; + wire [1:0] _zz_278; + wire [51:0] _zz_279; + wire [51:0] _zz_280; + wire [51:0] _zz_281; + wire [32:0] _zz_282; + wire [51:0] _zz_283; + wire [49:0] _zz_284; + wire [51:0] _zz_285; + wire [49:0] _zz_286; + wire [51:0] _zz_287; + wire [32:0] _zz_288; + wire [31:0] _zz_289; + wire [32:0] _zz_290; wire [0:0] _zz_291; wire [0:0] _zz_292; wire [0:0] _zz_293; wire [0:0] _zz_294; - wire [3:0] _zz_295; - wire [2:0] _zz_296; - wire [31:0] _zz_297; - wire [11:0] _zz_298; - wire [31:0] _zz_299; - wire [19:0] _zz_300; - wire [11:0] _zz_301; - wire [31:0] _zz_302; - wire [31:0] _zz_303; - wire [19:0] _zz_304; - wire [11:0] _zz_305; - wire [2:0] _zz_306; - wire [2:0] _zz_307; + wire [0:0] _zz_295; + wire [0:0] _zz_296; + wire [0:0] _zz_297; + wire [0:0] _zz_298; + wire [0:0] _zz_299; + wire [0:0] _zz_300; + wire [0:0] _zz_301; + wire [0:0] _zz_302; + wire [0:0] _zz_303; + wire [0:0] _zz_304; + wire [0:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; wire [0:0] _zz_308; - wire [2:0] _zz_309; - wire [4:0] _zz_310; - wire [11:0] _zz_311; - wire [11:0] _zz_312; - wire [31:0] _zz_313; + wire [0:0] _zz_309; + wire [3:0] _zz_310; + wire [2:0] _zz_311; + wire [31:0] _zz_312; + wire [11:0] _zz_313; wire [31:0] _zz_314; - wire [31:0] _zz_315; - wire [31:0] _zz_316; + wire [19:0] _zz_315; + wire [11:0] _zz_316; wire [31:0] _zz_317; wire [31:0] _zz_318; - wire [31:0] _zz_319; + wire [19:0] _zz_319; wire [11:0] _zz_320; - wire [19:0] _zz_321; - wire [11:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; + wire [2:0] _zz_321; + wire [2:0] _zz_322; + wire [0:0] _zz_323; + wire [2:0] _zz_324; + wire [4:0] _zz_325; wire [11:0] _zz_326; - wire [19:0] _zz_327; - wire [11:0] _zz_328; - wire [2:0] _zz_329; - wire [1:0] _zz_330; - wire [1:0] _zz_331; - wire [1:0] _zz_332; - wire [1:0] _zz_333; - wire [2:0] _zz_334; + wire [11:0] _zz_327; + wire [31:0] _zz_328; + wire [31:0] _zz_329; + wire [31:0] _zz_330; + wire [31:0] _zz_331; + wire [31:0] _zz_332; + wire [31:0] _zz_333; + wire [31:0] _zz_334; wire [11:0] _zz_335; - wire [65:0] _zz_336; - wire [65:0] _zz_337; + wire [19:0] _zz_336; + wire [11:0] _zz_337; wire [31:0] _zz_338; wire [31:0] _zz_339; - wire [0:0] _zz_340; - wire [5:0] _zz_341; - wire [32:0] _zz_342; - wire [31:0] _zz_343; - wire [31:0] _zz_344; - wire [32:0] _zz_345; - wire [32:0] _zz_346; - wire [32:0] _zz_347; - wire [32:0] _zz_348; - wire [0:0] _zz_349; - wire [32:0] _zz_350; - wire [0:0] _zz_351; - wire [32:0] _zz_352; - wire [0:0] _zz_353; + wire [31:0] _zz_340; + wire [11:0] _zz_341; + wire [19:0] _zz_342; + wire [11:0] _zz_343; + wire [2:0] _zz_344; + wire [1:0] _zz_345; + wire [1:0] _zz_346; + wire [1:0] _zz_347; + wire [1:0] _zz_348; + wire [2:0] _zz_349; + wire [11:0] _zz_350; + wire [65:0] _zz_351; + wire [65:0] _zz_352; + wire [31:0] _zz_353; wire [31:0] _zz_354; wire [0:0] _zz_355; - wire [0:0] _zz_356; - wire [0:0] _zz_357; - wire [0:0] _zz_358; - wire [0:0] _zz_359; - wire [0:0] _zz_360; - wire [0:0] _zz_361; - wire [26:0] _zz_362; - wire _zz_363; - wire _zz_364; - wire [1:0] _zz_365; - wire [31:0] _zz_366; - wire [31:0] _zz_367; - wire [31:0] _zz_368; - wire _zz_369; + wire [5:0] _zz_356; + wire [32:0] _zz_357; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire [32:0] _zz_360; + wire [32:0] _zz_361; + wire [32:0] _zz_362; + wire [32:0] _zz_363; + wire [0:0] _zz_364; + wire [32:0] _zz_365; + wire [0:0] _zz_366; + wire [32:0] _zz_367; + wire [0:0] _zz_368; + wire [31:0] _zz_369; wire [0:0] _zz_370; - wire [14:0] _zz_371; - wire [31:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire _zz_375; + wire [0:0] _zz_371; + wire [0:0] _zz_372; + wire [0:0] _zz_373; + wire [0:0] _zz_374; + wire [0:0] _zz_375; wire [0:0] _zz_376; - wire [8:0] _zz_377; - wire [31:0] _zz_378; - wire [31:0] _zz_379; - wire [31:0] _zz_380; - wire _zz_381; - wire [0:0] _zz_382; - wire [2:0] _zz_383; + wire [26:0] _zz_377; + wire _zz_378; + wire _zz_379; + wire [1:0] _zz_380; + wire [31:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; wire _zz_384; - wire _zz_385; - wire _zz_386; + wire [0:0] _zz_385; + wire [14:0] _zz_386; wire [31:0] _zz_387; - wire [0:0] _zz_388; - wire [0:0] _zz_389; + wire [31:0] _zz_388; + wire [31:0] _zz_389; wire _zz_390; wire [0:0] _zz_391; - wire [28:0] _zz_392; - wire [0:0] _zz_393; - wire [0:0] _zz_394; - wire [0:0] _zz_395; - wire [0:0] _zz_396; - wire _zz_397; - wire [0:0] _zz_398; - wire [23:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; + wire [8:0] _zz_392; + wire [31:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire _zz_396; + wire [0:0] _zz_397; + wire [2:0] _zz_398; + wire _zz_399; + wire _zz_400; + wire _zz_401; wire [31:0] _zz_402; - wire _zz_403; - wire _zz_404; - wire [0:0] _zz_405; + wire [0:0] _zz_403; + wire [0:0] _zz_404; + wire _zz_405; wire [0:0] _zz_406; - wire [0:0] _zz_407; + wire [28:0] _zz_407; wire [0:0] _zz_408; - wire _zz_409; + wire [0:0] _zz_409; wire [0:0] _zz_410; - wire [20:0] _zz_411; - wire [31:0] _zz_412; - wire [31:0] _zz_413; - wire _zz_414; - wire _zz_415; - wire [0:0] _zz_416; - wire [1:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire _zz_420; + wire [0:0] _zz_411; + wire _zz_412; + wire [0:0] _zz_413; + wire [23:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire _zz_418; + wire _zz_419; + wire [0:0] _zz_420; wire [0:0] _zz_421; - wire [17:0] _zz_422; - wire [31:0] _zz_423; - wire [31:0] _zz_424; - wire [31:0] _zz_425; - wire [31:0] _zz_426; + wire [0:0] _zz_422; + wire [0:0] _zz_423; + wire _zz_424; + wire [0:0] _zz_425; + wire [20:0] _zz_426; wire [31:0] _zz_427; wire [31:0] _zz_428; - wire [31:0] _zz_429; - wire [31:0] _zz_430; - wire _zz_431; + wire _zz_429; + wire _zz_430; + wire [0:0] _zz_431; wire [1:0] _zz_432; - wire [1:0] _zz_433; - wire _zz_434; - wire [0:0] _zz_435; - wire [14:0] _zz_436; - wire [31:0] _zz_437; + wire [0:0] _zz_433; + wire [0:0] _zz_434; + wire _zz_435; + wire [0:0] _zz_436; + wire [17:0] _zz_437; wire [31:0] _zz_438; wire [31:0] _zz_439; wire [31:0] _zz_440; wire [31:0] _zz_441; wire [31:0] _zz_442; - wire [0:0] _zz_443; - wire [1:0] _zz_444; - wire [4:0] _zz_445; - wire [4:0] _zz_446; - wire _zz_447; - wire [0:0] _zz_448; - wire [11:0] _zz_449; - wire [31:0] _zz_450; - wire [31:0] _zz_451; + wire [31:0] _zz_443; + wire [31:0] _zz_444; + wire [31:0] _zz_445; + wire _zz_446; + wire [1:0] _zz_447; + wire [1:0] _zz_448; + wire _zz_449; + wire [0:0] _zz_450; + wire [14:0] _zz_451; wire [31:0] _zz_452; wire [31:0] _zz_453; wire [31:0] _zz_454; wire [31:0] _zz_455; - wire _zz_456; - wire [0:0] _zz_457; - wire [1:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire [0:0] _zz_461; - wire [4:0] _zz_462; - wire [4:0] _zz_463; - wire [4:0] _zz_464; - wire _zz_465; - wire [0:0] _zz_466; - wire [8:0] _zz_467; + wire [31:0] _zz_456; + wire [31:0] _zz_457; + wire [0:0] _zz_458; + wire [1:0] _zz_459; + wire [4:0] _zz_460; + wire [4:0] _zz_461; + wire _zz_462; + wire [0:0] _zz_463; + wire [11:0] _zz_464; + wire [31:0] _zz_465; + wire [31:0] _zz_466; + wire [31:0] _zz_467; wire [31:0] _zz_468; wire [31:0] _zz_469; wire [31:0] _zz_470; wire _zz_471; - wire _zz_472; - wire [31:0] _zz_473; + wire [0:0] _zz_472; + wire [1:0] _zz_473; wire [31:0] _zz_474; - wire _zz_475; + wire [31:0] _zz_475; wire [0:0] _zz_476; - wire [2:0] _zz_477; - wire [0:0] _zz_478; - wire [2:0] _zz_479; - wire [0:0] _zz_480; - wire [4:0] _zz_481; - wire [1:0] _zz_482; - wire [1:0] _zz_483; - wire _zz_484; - wire [0:0] _zz_485; - wire [6:0] _zz_486; - wire [31:0] _zz_487; + wire [4:0] _zz_477; + wire [4:0] _zz_478; + wire [4:0] _zz_479; + wire _zz_480; + wire [0:0] _zz_481; + wire [8:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire _zz_486; + wire _zz_487; wire [31:0] _zz_488; wire [31:0] _zz_489; wire _zz_490; wire [0:0] _zz_491; - wire [0:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire _zz_495; - wire [0:0] _zz_496; - wire [0:0] _zz_497; - wire _zz_498; - wire [0:0] _zz_499; - wire [2:0] _zz_500; - wire _zz_501; - wire [0:0] _zz_502; - wire [0:0] _zz_503; - wire [0:0] _zz_504; - wire [0:0] _zz_505; - wire _zz_506; + wire [2:0] _zz_492; + wire [0:0] _zz_493; + wire [2:0] _zz_494; + wire [0:0] _zz_495; + wire [4:0] _zz_496; + wire [1:0] _zz_497; + wire [1:0] _zz_498; + wire _zz_499; + wire [0:0] _zz_500; + wire [6:0] _zz_501; + wire [31:0] _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire _zz_505; + wire [0:0] _zz_506; wire [0:0] _zz_507; - wire [4:0] _zz_508; + wire [31:0] _zz_508; wire [31:0] _zz_509; - wire [31:0] _zz_510; - wire [31:0] _zz_511; - wire [31:0] _zz_512; - wire [31:0] _zz_513; - wire [31:0] _zz_514; - wire [31:0] _zz_515; - wire [31:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire [31:0] _zz_520; - wire [31:0] _zz_521; - wire _zz_522; - wire [0:0] _zz_523; - wire [0:0] _zz_524; + wire _zz_510; + wire [0:0] _zz_511; + wire [0:0] _zz_512; + wire _zz_513; + wire [0:0] _zz_514; + wire [2:0] _zz_515; + wire _zz_516; + wire [0:0] _zz_517; + wire [0:0] _zz_518; + wire [0:0] _zz_519; + wire [0:0] _zz_520; + wire _zz_521; + wire [0:0] _zz_522; + wire [4:0] _zz_523; + wire [31:0] _zz_524; wire [31:0] _zz_525; wire [31:0] _zz_526; wire [31:0] _zz_527; wire [31:0] _zz_528; wire [31:0] _zz_529; - wire _zz_530; - wire [3:0] _zz_531; - wire [3:0] _zz_532; - wire _zz_533; - wire [0:0] _zz_534; - wire [2:0] _zz_535; + wire [31:0] _zz_530; + wire [31:0] _zz_531; + wire [31:0] _zz_532; + wire [31:0] _zz_533; + wire [31:0] _zz_534; + wire [31:0] _zz_535; wire [31:0] _zz_536; - wire [31:0] _zz_537; - wire [31:0] _zz_538; - wire [31:0] _zz_539; + wire _zz_537; + wire [0:0] _zz_538; + wire [0:0] _zz_539; wire [31:0] _zz_540; wire [31:0] _zz_541; - wire _zz_542; - wire [0:0] _zz_543; - wire [1:0] _zz_544; + wire [31:0] _zz_542; + wire [31:0] _zz_543; + wire [31:0] _zz_544; wire _zz_545; - wire [2:0] _zz_546; - wire [2:0] _zz_547; + wire [3:0] _zz_546; + wire [3:0] _zz_547; wire _zz_548; wire [0:0] _zz_549; - wire [0:0] _zz_550; + wire [2:0] _zz_550; wire [31:0] _zz_551; wire [31:0] _zz_552; wire [31:0] _zz_553; wire [31:0] _zz_554; wire [31:0] _zz_555; wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire _zz_558; - wire _zz_559; + wire _zz_557; + wire [0:0] _zz_558; + wire [1:0] _zz_559; wire _zz_560; - wire [0:0] _zz_561; - wire [0:0] _zz_562; + wire [2:0] _zz_561; + wire [2:0] _zz_562; wire _zz_563; - wire _zz_564; - wire _zz_565; - wire _zz_566; + wire [0:0] _zz_564; + wire [0:0] _zz_565; + wire [31:0] _zz_566; wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [31:0] _zz_570; + wire [31:0] _zz_571; + wire [31:0] _zz_572; + wire _zz_573; + wire _zz_574; + wire _zz_575; + wire [0:0] _zz_576; + wire [0:0] _zz_577; + wire _zz_578; + wire _zz_579; + wire _zz_580; + wire _zz_581; + wire [31:0] _zz_582; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1097,13 +1097,23 @@ module VexRiscv_inner ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_150; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [2:0] execute_CfuPlugin_functionsIds_0; - wire _zz_150; - reg [19:0] _zz_151; - reg [31:0] _zz_152; + wire _zz_160; + reg [19:0] _zz_161; + reg [31:0] _zz_162; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1135,18 +1145,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_153; + wire [31:0] _zz_163; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_154; - wire _zz_155; - wire _zz_156; - reg [32:0] _zz_157; + wire [31:0] _zz_164; + wire _zz_165; + wire _zz_166; + reg [32:0] _zz_167; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_158; - wire [31:0] _zz_159; + reg [31:0] _zz_168; + wire [31:0] _zz_169; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1156,7 +1166,7 @@ module VexRiscv_inner ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_160; + reg _zz_170; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; @@ -1224,7 +1234,7 @@ module VexRiscv_inner ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_161; + reg [2:0] _zz_171; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; @@ -1245,18 +1255,18 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2946; reg execute_CsrPlugin_csr_3072; reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_2820; + reg execute_CsrPlugin_csr_2821; + reg execute_CsrPlugin_csr_2822; + reg execute_CsrPlugin_csr_2823; + reg execute_CsrPlugin_csr_2824; + reg execute_CsrPlugin_csr_2825; + reg execute_CsrPlugin_csr_2826; + reg execute_CsrPlugin_csr_2827; + reg execute_CsrPlugin_csr_2828; + reg execute_CsrPlugin_csr_2829; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; reg [31:0] _zz_172; reg [31:0] _zz_173; reg [31:0] _zz_174; @@ -1268,16 +1278,31 @@ module VexRiscv_inner ( reg [31:0] _zz_180; reg [31:0] _zz_181; reg [31:0] _zz_182; - reg [2:0] _zz_183; - reg _zz_184; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [2:0] _zz_198; + reg _zz_199; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_185; - wire _zz_186; - wire _zz_187; - wire _zz_188; - wire _zz_189; - wire _zz_190; - reg _zz_191; + reg [2:0] _zz_200; + wire _zz_201; + wire _zz_202; + wire _zz_203; + wire _zz_204; + wire _zz_205; + reg _zz_206; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; @@ -1371,360 +1396,360 @@ module VexRiscv_inner ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_223 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_224 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_225 = 1'b1; - assign _zz_226 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_227 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_228 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_229 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_230 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_231 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_232 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_233 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_234 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_235 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_236 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_237 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_238 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_239 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_240 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_241 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_242 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_243 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_244 = (1'b0 || (! 1'b1)); - assign _zz_245 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_246 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_247 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_248 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_249 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_250 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_251 = execute_INSTRUCTION[13 : 12]; - assign _zz_252 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_253 = (! memory_arbitration_isStuck); - assign _zz_254 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_255 = (iBus_cmd_valid || (_zz_183 != 3'b000)); - assign _zz_256 = (_zz_219 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_257 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_258 = ((_zz_143 && 1'b1) && (! 1'b0)); - assign _zz_259 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_260 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_261 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_262 = execute_INSTRUCTION[13]; - assign _zz_263 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_264 = ($signed(_zz_265) + $signed(_zz_270)); - assign _zz_265 = ($signed(_zz_266) + $signed(_zz_268)); - assign _zz_266 = 52'h0; - assign _zz_267 = {1'b0,memory_MUL_LL}; - assign _zz_268 = {{19{_zz_267[32]}}, _zz_267}; - assign _zz_269 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_270 = {{2{_zz_269[49]}}, _zz_269}; - assign _zz_271 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_272 = {{2{_zz_271[49]}}, _zz_271}; - assign _zz_273 = ($signed(_zz_275) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_274 = _zz_273[31 : 0]; - assign _zz_275 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_276 = _zz_92[33 : 33]; - assign _zz_277 = _zz_92[32 : 32]; - assign _zz_278 = _zz_92[31 : 31]; - assign _zz_279 = _zz_92[30 : 30]; - assign _zz_280 = _zz_92[28 : 28]; - assign _zz_281 = _zz_92[25 : 25]; - assign _zz_282 = _zz_92[17 : 17]; - assign _zz_283 = _zz_92[16 : 16]; - assign _zz_284 = _zz_92[13 : 13]; - assign _zz_285 = _zz_92[12 : 12]; - assign _zz_286 = _zz_92[11 : 11]; - assign _zz_287 = _zz_92[34 : 34]; - assign _zz_288 = _zz_92[15 : 15]; - assign _zz_289 = _zz_92[5 : 5]; - assign _zz_290 = _zz_92[3 : 3]; - assign _zz_291 = _zz_92[20 : 20]; - assign _zz_292 = _zz_92[10 : 10]; - assign _zz_293 = _zz_92[4 : 4]; - assign _zz_294 = _zz_92[0 : 0]; - assign _zz_295 = (_zz_60 - 4'b0001); - assign _zz_296 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_297 = {29'd0, _zz_296}; - assign _zz_298 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_299 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_300 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_301 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_302 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_303 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_304 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_305 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_306 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_307 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_308 = execute_SRC_LESS; - assign _zz_309 = 3'b100; - assign _zz_310 = execute_INSTRUCTION[19 : 15]; - assign _zz_311 = execute_INSTRUCTION[31 : 20]; - assign _zz_312 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_313 = ($signed(_zz_314) + $signed(_zz_317)); - assign _zz_314 = ($signed(_zz_315) + $signed(_zz_316)); - assign _zz_315 = execute_SRC1; - assign _zz_316 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_317 = (execute_SRC_USE_SUB_LESS ? _zz_318 : _zz_319); - assign _zz_318 = 32'h00000001; - assign _zz_319 = 32'h0; - assign _zz_320 = execute_INSTRUCTION[31 : 20]; - assign _zz_321 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_322 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_323 = {_zz_131,execute_INSTRUCTION[31 : 20]}; - assign _zz_324 = {{_zz_133,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_325 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_238 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_239 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_240 = 1'b1; + assign _zz_241 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_242 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_243 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_244 = ((_zz_212 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_245 = ((_zz_212 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_246 = ((_zz_212 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_247 = ((_zz_212 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_248 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_249 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_250 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_251 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_252 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_253 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_254 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_255 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_256 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_257 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_258 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_259 = (1'b0 || (! 1'b1)); + assign _zz_260 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_261 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_262 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_263 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_264 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_265 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_266 = execute_INSTRUCTION[13 : 12]; + assign _zz_267 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_268 = (! memory_arbitration_isStuck); + assign _zz_269 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_270 = (iBus_cmd_valid || (_zz_198 != 3'b000)); + assign _zz_271 = (_zz_234 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_272 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_273 = ((_zz_143 && 1'b1) && (! 1'b0)); + assign _zz_274 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_275 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_276 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_277 = execute_INSTRUCTION[13]; + assign _zz_278 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_279 = ($signed(_zz_280) + $signed(_zz_285)); + assign _zz_280 = ($signed(_zz_281) + $signed(_zz_283)); + assign _zz_281 = 52'h0; + assign _zz_282 = {1'b0,memory_MUL_LL}; + assign _zz_283 = {{19{_zz_282[32]}}, _zz_282}; + assign _zz_284 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_285 = {{2{_zz_284[49]}}, _zz_284}; + assign _zz_286 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_287 = {{2{_zz_286[49]}}, _zz_286}; + assign _zz_288 = ($signed(_zz_290) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_289 = _zz_288[31 : 0]; + assign _zz_290 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_291 = _zz_92[33 : 33]; + assign _zz_292 = _zz_92[32 : 32]; + assign _zz_293 = _zz_92[31 : 31]; + assign _zz_294 = _zz_92[30 : 30]; + assign _zz_295 = _zz_92[28 : 28]; + assign _zz_296 = _zz_92[25 : 25]; + assign _zz_297 = _zz_92[17 : 17]; + assign _zz_298 = _zz_92[16 : 16]; + assign _zz_299 = _zz_92[13 : 13]; + assign _zz_300 = _zz_92[12 : 12]; + assign _zz_301 = _zz_92[11 : 11]; + assign _zz_302 = _zz_92[34 : 34]; + assign _zz_303 = _zz_92[15 : 15]; + assign _zz_304 = _zz_92[5 : 5]; + assign _zz_305 = _zz_92[3 : 3]; + assign _zz_306 = _zz_92[20 : 20]; + assign _zz_307 = _zz_92[10 : 10]; + assign _zz_308 = _zz_92[4 : 4]; + assign _zz_309 = _zz_92[0 : 0]; + assign _zz_310 = (_zz_60 - 4'b0001); + assign _zz_311 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_312 = {29'd0, _zz_311}; + assign _zz_313 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_314 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_315 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_316 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_317 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_318 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_319 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_321 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_322 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_323 = execute_SRC_LESS; + assign _zz_324 = 3'b100; + assign _zz_325 = execute_INSTRUCTION[19 : 15]; assign _zz_326 = execute_INSTRUCTION[31 : 20]; - assign _zz_327 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_329 = 3'b100; - assign _zz_330 = (_zz_146 & (~ _zz_331)); - assign _zz_331 = (_zz_146 - 2'b01); - assign _zz_332 = (_zz_148 & (~ _zz_333)); - assign _zz_333 = (_zz_148 - 2'b01); - assign _zz_334 = execute_INSTRUCTION[14 : 12]; + assign _zz_327 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_328 = ($signed(_zz_329) + $signed(_zz_332)); + assign _zz_329 = ($signed(_zz_330) + $signed(_zz_331)); + assign _zz_330 = execute_SRC1; + assign _zz_331 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_332 = (execute_SRC_USE_SUB_LESS ? _zz_333 : _zz_334); + assign _zz_333 = 32'h00000001; + assign _zz_334 = 32'h0; assign _zz_335 = execute_INSTRUCTION[31 : 20]; - assign _zz_336 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_337 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_338 = writeBack_MUL_LOW[31 : 0]; - assign _zz_339 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_340 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_341 = {5'd0, _zz_340}; - assign _zz_342 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_343 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_344 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_345 = {_zz_153,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_346 = _zz_347; - assign _zz_347 = _zz_348; - assign _zz_348 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_154) : _zz_154)} + _zz_350); - assign _zz_349 = memory_DivPlugin_div_needRevert; - assign _zz_350 = {32'd0, _zz_349}; - assign _zz_351 = _zz_156; - assign _zz_352 = {32'd0, _zz_351}; - assign _zz_353 = _zz_155; - assign _zz_354 = {31'd0, _zz_353}; - assign _zz_355 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_356 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_357 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_358 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_359 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_360 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_361 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_362 = (iBus_cmd_payload_address >>> 5); - assign _zz_363 = 1'b1; - assign _zz_364 = 1'b1; - assign _zz_365 = {_zz_64,_zz_63}; - assign _zz_366 = 32'h0000106f; - assign _zz_367 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_368 = 32'h00001073; - assign _zz_369 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_370 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_371 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_372) == 32'h00000003),{(_zz_373 == _zz_374),{_zz_375,{_zz_376,_zz_377}}}}}}; - assign _zz_372 = 32'h0000207f; - assign _zz_373 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_374 = 32'h00000003; - assign _zz_375 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_376 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_377 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_378) == 32'h00005013),{(_zz_379 == _zz_380),{_zz_381,{_zz_382,_zz_383}}}}}}; - assign _zz_378 = 32'hbc00707f; - assign _zz_379 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_380 = 32'h00001013; - assign _zz_381 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_382 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_383 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; - assign _zz_384 = decode_INSTRUCTION[31]; - assign _zz_385 = decode_INSTRUCTION[31]; - assign _zz_386 = decode_INSTRUCTION[7]; - assign _zz_387 = 32'h10103050; - assign _zz_388 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_389 = 1'b0; - assign _zz_390 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_391 = 1'b0; - assign _zz_392 = {(_zz_96 != 1'b0),{({_zz_393,_zz_394} != 2'b00),{(_zz_395 != _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}; - assign _zz_393 = ((decode_INSTRUCTION & _zz_400) == 32'h10000050); - assign _zz_394 = ((decode_INSTRUCTION & _zz_401) == 32'h00000050); - assign _zz_395 = ((decode_INSTRUCTION & _zz_402) == 32'h00000050); - assign _zz_396 = 1'b0; - assign _zz_397 = ({_zz_403,_zz_404} != 2'b00); - assign _zz_398 = ({_zz_405,_zz_406} != 2'b00); - assign _zz_399 = {(_zz_407 != _zz_408),{_zz_409,{_zz_410,_zz_411}}}; - assign _zz_400 = 32'h10203050; - assign _zz_401 = 32'h10103050; - assign _zz_402 = 32'h00103050; - assign _zz_403 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_404 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_405 = _zz_95; - assign _zz_406 = ((decode_INSTRUCTION & _zz_412) == 32'h00000004); - assign _zz_407 = ((decode_INSTRUCTION & _zz_413) == 32'h00000040); - assign _zz_408 = 1'b0; - assign _zz_409 = ({_zz_414,_zz_415} != 2'b00); - assign _zz_410 = ({_zz_416,_zz_417} != 3'b000); - assign _zz_411 = {(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}; - assign _zz_412 = 32'h0000001c; - assign _zz_413 = 32'h00000058; - assign _zz_414 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_415 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_416 = ((decode_INSTRUCTION & _zz_423) == 32'h40001010); - assign _zz_417 = {(_zz_424 == _zz_425),(_zz_426 == _zz_427)}; - assign _zz_418 = ((decode_INSTRUCTION & _zz_428) == 32'h00000024); - assign _zz_419 = 1'b0; - assign _zz_420 = ((_zz_429 == _zz_430) != 1'b0); - assign _zz_421 = (_zz_431 != 1'b0); - assign _zz_422 = {(_zz_432 != _zz_433),{_zz_434,{_zz_435,_zz_436}}}; - assign _zz_423 = 32'h40003054; - assign _zz_424 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_425 = 32'h00001010; - assign _zz_426 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_427 = 32'h00001010; - assign _zz_428 = 32'h00000064; - assign _zz_429 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_430 = 32'h00001000; - assign _zz_431 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_432 = {(_zz_437 == _zz_438),(_zz_439 == _zz_440)}; - assign _zz_433 = 2'b00; - assign _zz_434 = ((_zz_441 == _zz_442) != 1'b0); - assign _zz_435 = ({_zz_443,_zz_444} != 3'b000); - assign _zz_436 = {(_zz_445 != _zz_446),{_zz_447,{_zz_448,_zz_449}}}; - assign _zz_437 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_438 = 32'h00002000; - assign _zz_439 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_440 = 32'h00001000; - assign _zz_441 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_442 = 32'h00004004; - assign _zz_443 = _zz_96; - assign _zz_444 = {(_zz_450 == _zz_451),(_zz_452 == _zz_453)}; - assign _zz_445 = {(_zz_454 == _zz_455),{_zz_456,{_zz_457,_zz_458}}}; - assign _zz_446 = 5'h0; - assign _zz_447 = ((_zz_459 == _zz_460) != 1'b0); - assign _zz_448 = ({_zz_461,_zz_462} != 6'h0); - assign _zz_449 = {(_zz_463 != _zz_464),{_zz_465,{_zz_466,_zz_467}}}; - assign _zz_450 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_451 = 32'h00000020; - assign _zz_452 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_453 = 32'h00000020; - assign _zz_454 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_455 = 32'h00002040; - assign _zz_456 = ((decode_INSTRUCTION & _zz_468) == 32'h00001040); - assign _zz_457 = (_zz_469 == _zz_470); - assign _zz_458 = {_zz_471,_zz_472}; - assign _zz_459 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_460 = 32'h00000020; - assign _zz_461 = (_zz_473 == _zz_474); - assign _zz_462 = {_zz_475,{_zz_476,_zz_477}}; - assign _zz_463 = {_zz_94,{_zz_478,_zz_479}}; - assign _zz_464 = 5'h0; - assign _zz_465 = ({_zz_480,_zz_481} != 6'h0); - assign _zz_466 = (_zz_482 != _zz_483); - assign _zz_467 = {_zz_484,{_zz_485,_zz_486}}; - assign _zz_468 = 32'h00001040; - assign _zz_469 = (decode_INSTRUCTION & 32'h00100040); - assign _zz_470 = 32'h00000040; - assign _zz_471 = ((decode_INSTRUCTION & _zz_487) == 32'h00000040); - assign _zz_472 = ((decode_INSTRUCTION & _zz_488) == 32'h0); - assign _zz_473 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_474 = 32'h00000008; - assign _zz_475 = ((decode_INSTRUCTION & _zz_489) == 32'h00000040); - assign _zz_476 = _zz_94; + assign _zz_336 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_337 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_338 = {_zz_131,execute_INSTRUCTION[31 : 20]}; + assign _zz_339 = {{_zz_133,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_340 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_341 = execute_INSTRUCTION[31 : 20]; + assign _zz_342 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_344 = 3'b100; + assign _zz_345 = (_zz_146 & (~ _zz_346)); + assign _zz_346 = (_zz_146 - 2'b01); + assign _zz_347 = (_zz_148 & (~ _zz_348)); + assign _zz_348 = (_zz_148 - 2'b01); + assign _zz_349 = execute_INSTRUCTION[14 : 12]; + assign _zz_350 = execute_INSTRUCTION[31 : 20]; + assign _zz_351 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_352 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_353 = writeBack_MUL_LOW[31 : 0]; + assign _zz_354 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_355 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_356 = {5'd0, _zz_355}; + assign _zz_357 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_358 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_359 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_360 = {_zz_163,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_361 = _zz_362; + assign _zz_362 = _zz_363; + assign _zz_363 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_164) : _zz_164)} + _zz_365); + assign _zz_364 = memory_DivPlugin_div_needRevert; + assign _zz_365 = {32'd0, _zz_364}; + assign _zz_366 = _zz_166; + assign _zz_367 = {32'd0, _zz_366}; + assign _zz_368 = _zz_165; + assign _zz_369 = {31'd0, _zz_368}; + assign _zz_370 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_371 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_372 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_373 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_374 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_375 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_376 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_377 = (iBus_cmd_payload_address >>> 5); + assign _zz_378 = 1'b1; + assign _zz_379 = 1'b1; + assign _zz_380 = {_zz_64,_zz_63}; + assign _zz_381 = 32'h0000106f; + assign _zz_382 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_383 = 32'h00001073; + assign _zz_384 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_385 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_386 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_387) == 32'h00000003),{(_zz_388 == _zz_389),{_zz_390,{_zz_391,_zz_392}}}}}}; + assign _zz_387 = 32'h0000207f; + assign _zz_388 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_389 = 32'h00000003; + assign _zz_390 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_391 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_392 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_393) == 32'h00005013),{(_zz_394 == _zz_395),{_zz_396,{_zz_397,_zz_398}}}}}}; + assign _zz_393 = 32'hbc00707f; + assign _zz_394 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_395 = 32'h00001013; + assign _zz_396 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_397 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_398 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_399 = decode_INSTRUCTION[31]; + assign _zz_400 = decode_INSTRUCTION[31]; + assign _zz_401 = decode_INSTRUCTION[7]; + assign _zz_402 = 32'h10103050; + assign _zz_403 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_404 = 1'b0; + assign _zz_405 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_406 = 1'b0; + assign _zz_407 = {(_zz_96 != 1'b0),{({_zz_408,_zz_409} != 2'b00),{(_zz_410 != _zz_411),{_zz_412,{_zz_413,_zz_414}}}}}; + assign _zz_408 = ((decode_INSTRUCTION & _zz_415) == 32'h10000050); + assign _zz_409 = ((decode_INSTRUCTION & _zz_416) == 32'h00000050); + assign _zz_410 = ((decode_INSTRUCTION & _zz_417) == 32'h00000050); + assign _zz_411 = 1'b0; + assign _zz_412 = ({_zz_418,_zz_419} != 2'b00); + assign _zz_413 = ({_zz_420,_zz_421} != 2'b00); + assign _zz_414 = {(_zz_422 != _zz_423),{_zz_424,{_zz_425,_zz_426}}}; + assign _zz_415 = 32'h10203050; + assign _zz_416 = 32'h10103050; + assign _zz_417 = 32'h00103050; + assign _zz_418 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_419 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_420 = _zz_95; + assign _zz_421 = ((decode_INSTRUCTION & _zz_427) == 32'h00000004); + assign _zz_422 = ((decode_INSTRUCTION & _zz_428) == 32'h00000040); + assign _zz_423 = 1'b0; + assign _zz_424 = ({_zz_429,_zz_430} != 2'b00); + assign _zz_425 = ({_zz_431,_zz_432} != 3'b000); + assign _zz_426 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; + assign _zz_427 = 32'h0000001c; + assign _zz_428 = 32'h00000058; + assign _zz_429 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_430 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h40001010); + assign _zz_432 = {(_zz_439 == _zz_440),(_zz_441 == _zz_442)}; + assign _zz_433 = ((decode_INSTRUCTION & _zz_443) == 32'h00000024); + assign _zz_434 = 1'b0; + assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); + assign _zz_436 = (_zz_446 != 1'b0); + assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; + assign _zz_438 = 32'h40003054; + assign _zz_439 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_440 = 32'h00001010; + assign _zz_441 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_442 = 32'h00001010; + assign _zz_443 = 32'h00000064; + assign _zz_444 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_445 = 32'h00001000; + assign _zz_446 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_447 = {(_zz_452 == _zz_453),(_zz_454 == _zz_455)}; + assign _zz_448 = 2'b00; + assign _zz_449 = ((_zz_456 == _zz_457) != 1'b0); + assign _zz_450 = ({_zz_458,_zz_459} != 3'b000); + assign _zz_451 = {(_zz_460 != _zz_461),{_zz_462,{_zz_463,_zz_464}}}; + assign _zz_452 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_453 = 32'h00002000; + assign _zz_454 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_455 = 32'h00001000; + assign _zz_456 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_457 = 32'h00004004; + assign _zz_458 = _zz_96; + assign _zz_459 = {(_zz_465 == _zz_466),(_zz_467 == _zz_468)}; + assign _zz_460 = {(_zz_469 == _zz_470),{_zz_471,{_zz_472,_zz_473}}}; + assign _zz_461 = 5'h0; + assign _zz_462 = ((_zz_474 == _zz_475) != 1'b0); + assign _zz_463 = ({_zz_476,_zz_477} != 6'h0); + assign _zz_464 = {(_zz_478 != _zz_479),{_zz_480,{_zz_481,_zz_482}}}; + assign _zz_465 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_466 = 32'h00000020; + assign _zz_467 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_468 = 32'h00000020; + assign _zz_469 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_470 = 32'h00002040; + assign _zz_471 = ((decode_INSTRUCTION & _zz_483) == 32'h00001040); + assign _zz_472 = (_zz_484 == _zz_485); + assign _zz_473 = {_zz_486,_zz_487}; + assign _zz_474 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_475 = 32'h00000020; + assign _zz_476 = (_zz_488 == _zz_489); assign _zz_477 = {_zz_490,{_zz_491,_zz_492}}; - assign _zz_478 = (_zz_493 == _zz_494); - assign _zz_479 = {_zz_495,{_zz_496,_zz_497}}; - assign _zz_480 = _zz_95; - assign _zz_481 = {_zz_498,{_zz_499,_zz_500}}; - assign _zz_482 = {_zz_94,_zz_501}; - assign _zz_483 = 2'b00; - assign _zz_484 = ({_zz_502,_zz_503} != 2'b00); - assign _zz_485 = (_zz_504 != _zz_505); - assign _zz_486 = {_zz_506,{_zz_507,_zz_508}}; - assign _zz_487 = 32'h00000050; - assign _zz_488 = 32'h00000038; - assign _zz_489 = 32'h00000040; - assign _zz_490 = ((decode_INSTRUCTION & _zz_509) == 32'h00004020); - assign _zz_491 = (_zz_510 == _zz_511); - assign _zz_492 = (_zz_512 == _zz_513); - assign _zz_493 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_494 = 32'h00002010; - assign _zz_495 = ((decode_INSTRUCTION & _zz_514) == 32'h00000010); - assign _zz_496 = (_zz_515 == _zz_516); - assign _zz_497 = (_zz_517 == _zz_518); - assign _zz_498 = ((decode_INSTRUCTION & _zz_519) == 32'h00001010); - assign _zz_499 = (_zz_520 == _zz_521); - assign _zz_500 = {_zz_522,{_zz_523,_zz_524}}; - assign _zz_501 = ((decode_INSTRUCTION & _zz_525) == 32'h00000020); - assign _zz_502 = _zz_94; - assign _zz_503 = (_zz_526 == _zz_527); - assign _zz_504 = (_zz_528 == _zz_529); - assign _zz_505 = 1'b0; - assign _zz_506 = (_zz_530 != 1'b0); - assign _zz_507 = (_zz_531 != _zz_532); - assign _zz_508 = {_zz_533,{_zz_534,_zz_535}}; - assign _zz_509 = 32'h00004020; - assign _zz_510 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_511 = 32'h00000010; - assign _zz_512 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_513 = 32'h00000020; - assign _zz_514 = 32'h00001030; - assign _zz_515 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_516 = 32'h00002020; - assign _zz_517 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_518 = 32'h00000020; - assign _zz_519 = 32'h00001010; - assign _zz_520 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_521 = 32'h00002010; - assign _zz_522 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); - assign _zz_523 = (_zz_537 == _zz_538); - assign _zz_524 = (_zz_539 == _zz_540); - assign _zz_525 = 32'h00000070; - assign _zz_526 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_527 = 32'h0; - assign _zz_528 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_529 = 32'h00004010; - assign _zz_530 = ((decode_INSTRUCTION & _zz_541) == 32'h00002010); - assign _zz_531 = {_zz_542,{_zz_543,_zz_544}}; - assign _zz_532 = 4'b0000; - assign _zz_533 = (_zz_545 != 1'b0); - assign _zz_534 = (_zz_546 != _zz_547); - assign _zz_535 = {_zz_548,{_zz_549,_zz_550}}; - assign _zz_536 = 32'h00000050; - assign _zz_537 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_538 = 32'h00000004; - assign _zz_539 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_540 = 32'h0; - assign _zz_541 = 32'h00006014; - assign _zz_542 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_543 = ((decode_INSTRUCTION & _zz_551) == 32'h0); - assign _zz_544 = {(_zz_552 == _zz_553),(_zz_554 == _zz_555)}; - assign _zz_545 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_546 = {(_zz_556 == _zz_557),{_zz_558,_zz_559}}; - assign _zz_547 = 3'b000; - assign _zz_548 = ({_zz_560,_zz_93} != 2'b00); - assign _zz_549 = ({_zz_561,_zz_562} != 2'b00); - assign _zz_550 = (_zz_563 != 1'b0); - assign _zz_551 = 32'h00000018; - assign _zz_552 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_553 = 32'h00002000; - assign _zz_554 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_555 = 32'h00001000; - assign _zz_556 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_557 = 32'h00000040; - assign _zz_558 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_559 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_560 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_561 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_562 = _zz_93; - assign _zz_563 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); - assign _zz_564 = execute_INSTRUCTION[31]; - assign _zz_565 = execute_INSTRUCTION[31]; - assign _zz_566 = execute_INSTRUCTION[7]; - assign _zz_567 = 32'h0; + assign _zz_478 = {_zz_94,{_zz_493,_zz_494}}; + assign _zz_479 = 5'h0; + assign _zz_480 = ({_zz_495,_zz_496} != 6'h0); + assign _zz_481 = (_zz_497 != _zz_498); + assign _zz_482 = {_zz_499,{_zz_500,_zz_501}}; + assign _zz_483 = 32'h00001040; + assign _zz_484 = (decode_INSTRUCTION & 32'h00100040); + assign _zz_485 = 32'h00000040; + assign _zz_486 = ((decode_INSTRUCTION & _zz_502) == 32'h00000040); + assign _zz_487 = ((decode_INSTRUCTION & _zz_503) == 32'h0); + assign _zz_488 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_489 = 32'h00000008; + assign _zz_490 = ((decode_INSTRUCTION & _zz_504) == 32'h00000040); + assign _zz_491 = _zz_94; + assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; + assign _zz_493 = (_zz_508 == _zz_509); + assign _zz_494 = {_zz_510,{_zz_511,_zz_512}}; + assign _zz_495 = _zz_95; + assign _zz_496 = {_zz_513,{_zz_514,_zz_515}}; + assign _zz_497 = {_zz_94,_zz_516}; + assign _zz_498 = 2'b00; + assign _zz_499 = ({_zz_517,_zz_518} != 2'b00); + assign _zz_500 = (_zz_519 != _zz_520); + assign _zz_501 = {_zz_521,{_zz_522,_zz_523}}; + assign _zz_502 = 32'h00000050; + assign _zz_503 = 32'h00000038; + assign _zz_504 = 32'h00000040; + assign _zz_505 = ((decode_INSTRUCTION & _zz_524) == 32'h00004020); + assign _zz_506 = (_zz_525 == _zz_526); + assign _zz_507 = (_zz_527 == _zz_528); + assign _zz_508 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_509 = 32'h00002010; + assign _zz_510 = ((decode_INSTRUCTION & _zz_529) == 32'h00000010); + assign _zz_511 = (_zz_530 == _zz_531); + assign _zz_512 = (_zz_532 == _zz_533); + assign _zz_513 = ((decode_INSTRUCTION & _zz_534) == 32'h00001010); + assign _zz_514 = (_zz_535 == _zz_536); + assign _zz_515 = {_zz_537,{_zz_538,_zz_539}}; + assign _zz_516 = ((decode_INSTRUCTION & _zz_540) == 32'h00000020); + assign _zz_517 = _zz_94; + assign _zz_518 = (_zz_541 == _zz_542); + assign _zz_519 = (_zz_543 == _zz_544); + assign _zz_520 = 1'b0; + assign _zz_521 = (_zz_545 != 1'b0); + assign _zz_522 = (_zz_546 != _zz_547); + assign _zz_523 = {_zz_548,{_zz_549,_zz_550}}; + assign _zz_524 = 32'h00004020; + assign _zz_525 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_526 = 32'h00000010; + assign _zz_527 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_528 = 32'h00000020; + assign _zz_529 = 32'h00001030; + assign _zz_530 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_531 = 32'h00002020; + assign _zz_532 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_533 = 32'h00000020; + assign _zz_534 = 32'h00001010; + assign _zz_535 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_536 = 32'h00002010; + assign _zz_537 = ((decode_INSTRUCTION & _zz_551) == 32'h00000010); + assign _zz_538 = (_zz_552 == _zz_553); + assign _zz_539 = (_zz_554 == _zz_555); + assign _zz_540 = 32'h00000070; + assign _zz_541 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_542 = 32'h0; + assign _zz_543 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_544 = 32'h00004010; + assign _zz_545 = ((decode_INSTRUCTION & _zz_556) == 32'h00002010); + assign _zz_546 = {_zz_557,{_zz_558,_zz_559}}; + assign _zz_547 = 4'b0000; + assign _zz_548 = (_zz_560 != 1'b0); + assign _zz_549 = (_zz_561 != _zz_562); + assign _zz_550 = {_zz_563,{_zz_564,_zz_565}}; + assign _zz_551 = 32'h00000050; + assign _zz_552 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_553 = 32'h00000004; + assign _zz_554 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_555 = 32'h0; + assign _zz_556 = 32'h00006014; + assign _zz_557 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_558 = ((decode_INSTRUCTION & _zz_566) == 32'h0); + assign _zz_559 = {(_zz_567 == _zz_568),(_zz_569 == _zz_570)}; + assign _zz_560 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_561 = {(_zz_571 == _zz_572),{_zz_573,_zz_574}}; + assign _zz_562 = 3'b000; + assign _zz_563 = ({_zz_575,_zz_93} != 2'b00); + assign _zz_564 = ({_zz_576,_zz_577} != 2'b00); + assign _zz_565 = (_zz_578 != 1'b0); + assign _zz_566 = 32'h00000018; + assign _zz_567 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_568 = 32'h00002000; + assign _zz_569 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_570 = 32'h00001000; + assign _zz_571 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_572 = 32'h00000040; + assign _zz_573 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_574 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_575 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_576 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_577 = _zz_93; + assign _zz_578 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_579 = execute_INSTRUCTION[31]; + assign _zz_580 = execute_INSTRUCTION[31]; + assign _zz_581 = execute_INSTRUCTION[7]; + assign _zz_582 = 32'h0; always @ (posedge clk) begin - if(_zz_363) begin - _zz_220 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_378) begin + _zz_235 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_364) begin - _zz_221 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_379) begin + _zz_236 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1735,13 +1760,13 @@ module VexRiscv_inner ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_192 ), //i - .io_cpu_prefetch_isValid (_zz_193 ), //i + .io_flush (_zz_207 ), //i + .io_cpu_prefetch_isValid (_zz_208 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_194 ), //i - .io_cpu_fetch_isStuck (_zz_195 ), //i - .io_cpu_fetch_isRemoved (_zz_196 ), //i + .io_cpu_fetch_isValid (_zz_209 ), //i + .io_cpu_fetch_isStuck (_zz_210 ), //i + .io_cpu_fetch_isRemoved (_zz_211 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1753,8 +1778,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_197 ), //i - .io_cpu_decode_isStuck (_zz_198 ), //i + .io_cpu_decode_isValid (_zz_212 ), //i + .io_cpu_decode_isStuck (_zz_213 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1762,8 +1787,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_199 ), //i - .io_cpu_fill_valid (_zz_200 ), //i + .io_cpu_decode_isUser (_zz_214 ), //i + .io_cpu_fill_valid (_zz_215 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1772,56 +1797,56 @@ module VexRiscv_inner ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_161[2:0] ), //i + ._zz_9 (_zz_171[2:0] ), //i ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_201 ), //i - .io_cpu_execute_address (_zz_202[31:0] ), //i + .io_cpu_execute_isValid (_zz_216 ), //i + .io_cpu_execute_address (_zz_217[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_87[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_memory_isValid (_zz_203 ), //i + .io_cpu_memory_isValid (_zz_218 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_204[31:0] ), //i + .io_cpu_memory_address (_zz_219[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_205 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_220 ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_206 ), //i + .io_cpu_writeBack_isValid (_zz_221 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_207 ), //i + .io_cpu_writeBack_isUser (_zz_222 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_208[31:0] ), //i + .io_cpu_writeBack_address (_zz_223[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_209 ), //i - .io_cpu_writeBack_fence_SR (_zz_210 ), //i - .io_cpu_writeBack_fence_SO (_zz_211 ), //i - .io_cpu_writeBack_fence_SI (_zz_212 ), //i - .io_cpu_writeBack_fence_PW (_zz_213 ), //i - .io_cpu_writeBack_fence_PR (_zz_214 ), //i - .io_cpu_writeBack_fence_PO (_zz_215 ), //i - .io_cpu_writeBack_fence_PI (_zz_216 ), //i - .io_cpu_writeBack_fence_FM (_zz_217[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_224 ), //i + .io_cpu_writeBack_fence_SR (_zz_225 ), //i + .io_cpu_writeBack_fence_SO (_zz_226 ), //i + .io_cpu_writeBack_fence_SI (_zz_227 ), //i + .io_cpu_writeBack_fence_PW (_zz_228 ), //i + .io_cpu_writeBack_fence_PR (_zz_229 ), //i + .io_cpu_writeBack_fence_PO (_zz_230 ), //i + .io_cpu_writeBack_fence_PI (_zz_231 ), //i + .io_cpu_writeBack_fence_FM (_zz_232[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_218 ), //i + .io_cpu_flush_valid (_zz_233 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_219 ), //i + .io_mem_cmd_ready (_zz_234 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1837,18 +1862,18 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_365) + case(_zz_380) 2'b00 : begin - _zz_222 = DBusCachedPlugin_redoBranch_payload; + _zz_237 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_222 = CsrPlugin_jumpInterface_payload; + _zz_237 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_222 = BranchPlugin_jumpInterface_payload; + _zz_237 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_222 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_237 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2603,7 +2628,7 @@ module VexRiscv_inner ( end `endif - assign memory_MUL_LOW = ($signed(_zz_264) + $signed(_zz_272)); + assign memory_MUL_LOW = ($signed(_zz_279) + $signed(_zz_287)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2612,42 +2637,42 @@ module VexRiscv_inner ( assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_274; + assign execute_SHIFT_RIGHT = _zz_289; assign execute_REGFILE_WRITE_DATA = _zz_107; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_202[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_217[1 : 0]; assign decode_DO_EBREAK = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_276[0]; - assign decode_IS_RS1_SIGNED = _zz_277[0]; - assign decode_IS_DIV = _zz_278[0]; + assign decode_IS_RS2_SIGNED = _zz_291[0]; + assign decode_IS_RS1_SIGNED = _zz_292[0]; + assign decode_IS_DIV = _zz_293[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_279[0]; + assign decode_IS_MUL = _zz_294[0]; assign decode_CfuPlugin_CFU_ENCODING = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_280[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_295[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_281[0]; + assign decode_IS_CSR = _zz_296[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_282[0]; - assign decode_MEMORY_MANAGMENT = _zz_283[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_297[0]; + assign decode_MEMORY_MANAGMENT = _zz_298[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_284[0]; + assign decode_MEMORY_WR = _zz_299[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_285[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_286[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_300[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_301[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2661,7 +2686,7 @@ module VexRiscv_inner ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_287[0]; + assign decode_IS_EBREAK = _zz_302[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2688,11 +2713,11 @@ module VexRiscv_inner ( assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_COND_RESULT = _zz_129; assign execute_BRANCH_CTRL = _zz_34; - assign decode_RS2_USE = _zz_288[0]; - assign decode_RS1_USE = _zz_289[0]; + assign decode_RS2_USE = _zz_303[0]; + assign decode_RS1_USE = _zz_304[0]; always @ (*) begin _zz_35 = execute_REGFILE_WRITE_DATA; - if(_zz_223)begin + if(_zz_238)begin _zz_35 = execute_CsrPlugin_readData; end end @@ -2710,21 +2735,21 @@ module VexRiscv_inner ( decode_RS2 = _zz_120; end end - if(_zz_224)begin - if(_zz_225)begin + if(_zz_239)begin + if(_zz_240)begin if(_zz_122)begin decode_RS2 = _zz_55; end end end - if(_zz_226)begin + if(_zz_241)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_124)begin decode_RS2 = _zz_36; end end end - if(_zz_227)begin + if(_zz_242)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_126)begin decode_RS2 = _zz_35; @@ -2740,21 +2765,21 @@ module VexRiscv_inner ( decode_RS1 = _zz_120; end end - if(_zz_224)begin - if(_zz_225)begin + if(_zz_239)begin + if(_zz_240)begin if(_zz_121)begin decode_RS1 = _zz_55; end end end - if(_zz_226)begin + if(_zz_241)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_123)begin decode_RS1 = _zz_36; end end end - if(_zz_227)begin + if(_zz_242)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_125)begin decode_RS1 = _zz_35; @@ -2781,7 +2806,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_36 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_228)begin + if(_zz_243)begin _zz_36 = memory_DivPlugin_div_result; end end @@ -2794,8 +2819,8 @@ module VexRiscv_inner ( assign _zz_39 = execute_PC; assign execute_SRC2_CTRL = _zz_40; assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_290[0]; - assign decode_SRC_ADD_ZERO = _zz_291[0]; + assign decode_SRC_USE_SUB_LESS = _zz_305[0]; + assign decode_SRC_ADD_ZERO = _zz_306[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_42; @@ -2813,25 +2838,25 @@ module VexRiscv_inner ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_292[0]; + decode_REGFILE_WRITE_VALID = _zz_307[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_366) == 32'h00000003),{(_zz_367 == _zz_368),{_zz_369,{_zz_370,_zz_371}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_381) == 32'h00000003),{(_zz_382 == _zz_383),{_zz_384,{_zz_385,_zz_386}}}}}}} != 22'h0); always @ (*) begin _zz_55 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_55 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_263) + case(_zz_278) 2'b00 : begin - _zz_55 = _zz_338; + _zz_55 = _zz_353; end default : begin - _zz_55 = _zz_339; + _zz_55 = _zz_354; end endcase end @@ -2850,32 +2875,32 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_293[0]; - assign decode_FLUSH_ALL = _zz_294[0]; + assign decode_MEMORY_ENABLE = _zz_308[0]; + assign decode_FLUSH_ALL = _zz_309[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_229)begin + if(_zz_244)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_230)begin + if(_zz_245)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_231)begin + if(_zz_246)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_232)begin + if(_zz_247)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2904,7 +2929,7 @@ module VexRiscv_inner ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_161) + case(_zz_171) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2928,7 +2953,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_233)begin + if(_zz_248)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2942,25 +2967,25 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_233)begin + if(_zz_248)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_218 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_233 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end if(((dataCache_1_io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_234)begin + if(_zz_249)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_223)begin + if(_zz_238)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2972,7 +2997,7 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_235)begin + if(_zz_250)begin execute_arbitration_haltByOther = 1'b1; end end @@ -2989,8 +3014,8 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_235)begin - if(_zz_236)begin + if(_zz_250)begin + if(_zz_251)begin execute_arbitration_flushIt = 1'b1; end end @@ -3001,8 +3026,8 @@ module VexRiscv_inner ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_235)begin - if(_zz_236)begin + if(_zz_250)begin + if(_zz_251)begin execute_arbitration_flushNext = 1'b1; end end @@ -3015,7 +3040,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_228)begin + if(_zz_243)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3025,7 +3050,7 @@ module VexRiscv_inner ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_237)begin + if(_zz_252)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3039,7 +3064,7 @@ module VexRiscv_inner ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_237)begin + if(_zz_252)begin memory_arbitration_flushNext = 1'b1; end end @@ -3077,10 +3102,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_238)begin + if(_zz_253)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_239)begin + if(_zz_254)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3094,21 +3119,21 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_238)begin + if(_zz_253)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_239)begin + if(_zz_254)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_235)begin - if(_zz_236)begin + if(_zz_250)begin + if(_zz_251)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_240)begin + if(_zz_255)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3129,7 +3154,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_234)begin + if(_zz_249)begin CsrPlugin_inWfi = 1'b1; end end @@ -3143,21 +3168,21 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_238)begin + if(_zz_253)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_239)begin + if(_zz_254)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_238)begin + if(_zz_253)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_239)begin - case(_zz_241) + if(_zz_254)begin + case(_zz_256) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3191,11 +3216,11 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_60 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_61 = (_zz_60 & (~ _zz_295)); + assign _zz_61 = (_zz_60 & (~ _zz_310)); assign _zz_62 = _zz_61[3]; assign _zz_63 = (_zz_61[1] || _zz_62); assign _zz_64 = (_zz_61[2] || _zz_62); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_222; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_237; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3215,7 +3240,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_297); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_312); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3307,7 +3332,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_161) + case(_zz_171) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3319,7 +3344,7 @@ module VexRiscv_inner ( endcase end - assign _zz_74 = _zz_298[11]; + assign _zz_74 = _zz_313[11]; always @ (*) begin _zz_75[18] = _zz_74; _zz_75[17] = _zz_74; @@ -3343,13 +3368,13 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_299[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_314[31])); if(_zz_80)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_76 = _zz_300[19]; + assign _zz_76 = _zz_315[19]; always @ (*) begin _zz_77[10] = _zz_76; _zz_77[9] = _zz_76; @@ -3364,7 +3389,7 @@ module VexRiscv_inner ( _zz_77[0] = _zz_76; end - assign _zz_78 = _zz_301[11]; + assign _zz_78 = _zz_316[11]; always @ (*) begin _zz_79[18] = _zz_78; _zz_79[17] = _zz_78; @@ -3390,16 +3415,16 @@ module VexRiscv_inner ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_80 = _zz_302[1]; + _zz_80 = _zz_317[1]; end default : begin - _zz_80 = _zz_303[1]; + _zz_80 = _zz_318[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_81 = _zz_304[19]; + assign _zz_81 = _zz_319[19]; always @ (*) begin _zz_82[10] = _zz_81; _zz_82[9] = _zz_81; @@ -3414,7 +3439,7 @@ module VexRiscv_inner ( _zz_82[0] = _zz_81; end - assign _zz_83 = _zz_305[11]; + assign _zz_83 = _zz_320[11]; always @ (*) begin _zz_84[18] = _zz_83; _zz_84[17] = _zz_83; @@ -3437,7 +3462,7 @@ module VexRiscv_inner ( _zz_84[0] = _zz_83; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_82,{{{_zz_384,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_84,{{{_zz_385,_zz_386},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_82,{{{_zz_399,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_84,{{{_zz_400,_zz_401},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3446,52 +3471,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_193 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_194 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_195 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_194; + assign _zz_208 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_209 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_210 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_209; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_197 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_198 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_199 = (CsrPlugin_privilege == 2'b00); + assign _zz_212 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_213 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_214 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_232)begin + if(_zz_247)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_230)begin + if(_zz_245)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_200 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_230)begin - _zz_200 = 1'b1; + _zz_215 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_245)begin + _zz_215 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_231)begin + if(_zz_246)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_229)begin + if(_zz_244)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_231)begin + if(_zz_246)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_229)begin + if(_zz_244)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3501,9 +3526,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_192 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_207 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_219 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_234 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3530,8 +3555,8 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_201 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_202 = execute_SRC_ADD; + assign _zz_216 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_217 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3546,27 +3571,27 @@ module VexRiscv_inner ( endcase end - assign _zz_218 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_203 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_204 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_203; + assign _zz_233 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_218 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_219 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_218; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_204; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_219; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_205 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_220 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_59 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_205 = 1'b1; + _zz_220 = 1'b1; end end - assign _zz_206 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_207 = (CsrPlugin_privilege == 2'b00); - assign _zz_208 = writeBack_REGFILE_WRITE_DATA; + assign _zz_221 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_222 = (CsrPlugin_privilege == 2'b00); + assign _zz_223 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_242)begin + if(_zz_257)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3576,7 +3601,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_242)begin + if(_zz_257)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3595,12 +3620,12 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_242)begin + if(_zz_257)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_306}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_321}; end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_307}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_322}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); @@ -3676,7 +3701,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_261) + case(_zz_276) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_89; end @@ -3710,7 +3735,7 @@ module VexRiscv_inner ( assign _zz_95 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_96 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); assign _zz_97 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_92 = {(((decode_INSTRUCTION & _zz_387) == 32'h00100050) != 1'b0),{(_zz_97 != 1'b0),{(_zz_97 != 1'b0),{(_zz_388 != _zz_389),{_zz_390,{_zz_391,_zz_392}}}}}}; + assign _zz_92 = {(((decode_INSTRUCTION & _zz_402) == 32'h00100050) != 1'b0),{(_zz_97 != 1'b0),{(_zz_97 != 1'b0),{(_zz_403 != _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; assign _zz_98 = _zz_92[2 : 1]; assign _zz_54 = _zz_98; assign _zz_99 = _zz_92[7 : 6]; @@ -3732,8 +3757,8 @@ module VexRiscv_inner ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_220; - assign decode_RegFilePlugin_rs2Data = _zz_221; + assign decode_RegFilePlugin_rs1Data = _zz_235; + assign decode_RegFilePlugin_rs2Data = _zz_236; always @ (*) begin lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); if(_zz_106)begin @@ -3763,7 +3788,7 @@ module VexRiscv_inner ( _zz_107 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_107 = {31'd0, _zz_308}; + _zz_107 = {31'd0, _zz_323}; end default : begin _zz_107 = execute_SRC_ADD_SUB; @@ -3777,18 +3802,18 @@ module VexRiscv_inner ( _zz_108 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_108 = {29'd0, _zz_309}; + _zz_108 = {29'd0, _zz_324}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_108 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_108 = {27'd0, _zz_310}; + _zz_108 = {27'd0, _zz_325}; end endcase end - assign _zz_109 = _zz_311[11]; + assign _zz_109 = _zz_326[11]; always @ (*) begin _zz_110[19] = _zz_109; _zz_110[18] = _zz_109; @@ -3812,7 +3837,7 @@ module VexRiscv_inner ( _zz_110[0] = _zz_109; end - assign _zz_111 = _zz_312[11]; + assign _zz_111 = _zz_327[11]; always @ (*) begin _zz_112[19] = _zz_111; _zz_112[18] = _zz_111; @@ -3854,7 +3879,7 @@ module VexRiscv_inner ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_313; + execute_SrcPlugin_addSub = _zz_328; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3935,22 +3960,22 @@ module VexRiscv_inner ( always @ (*) begin _zz_116 = 1'b0; - if(_zz_243)begin - if(_zz_244)begin + if(_zz_258)begin + if(_zz_259)begin if(_zz_121)begin _zz_116 = 1'b1; end end end - if(_zz_245)begin - if(_zz_246)begin + if(_zz_260)begin + if(_zz_261)begin if(_zz_123)begin _zz_116 = 1'b1; end end end - if(_zz_247)begin - if(_zz_248)begin + if(_zz_262)begin + if(_zz_263)begin if(_zz_125)begin _zz_116 = 1'b1; end @@ -3963,22 +3988,22 @@ module VexRiscv_inner ( always @ (*) begin _zz_117 = 1'b0; - if(_zz_243)begin - if(_zz_244)begin + if(_zz_258)begin + if(_zz_259)begin if(_zz_122)begin _zz_117 = 1'b1; end end end - if(_zz_245)begin - if(_zz_246)begin + if(_zz_260)begin + if(_zz_261)begin if(_zz_124)begin _zz_117 = 1'b1; end end end - if(_zz_247)begin - if(_zz_248)begin + if(_zz_262)begin + if(_zz_263)begin if(_zz_126)begin _zz_117 = 1'b1; end @@ -4026,7 +4051,7 @@ module VexRiscv_inner ( endcase end - assign _zz_130 = _zz_320[11]; + assign _zz_130 = _zz_335[11]; always @ (*) begin _zz_131[19] = _zz_130; _zz_131[18] = _zz_130; @@ -4050,7 +4075,7 @@ module VexRiscv_inner ( _zz_131[0] = _zz_130; end - assign _zz_132 = _zz_321[19]; + assign _zz_132 = _zz_336[19]; always @ (*) begin _zz_133[10] = _zz_132; _zz_133[9] = _zz_132; @@ -4065,7 +4090,7 @@ module VexRiscv_inner ( _zz_133[0] = _zz_132; end - assign _zz_134 = _zz_322[11]; + assign _zz_134 = _zz_337[11]; always @ (*) begin _zz_135[18] = _zz_134; _zz_135[17] = _zz_134; @@ -4091,13 +4116,13 @@ module VexRiscv_inner ( always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_136 = (_zz_323[1] ^ execute_RS1[1]); + _zz_136 = (_zz_338[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_136 = _zz_324[1]; + _zz_136 = _zz_339[1]; end default : begin - _zz_136 = _zz_325[1]; + _zz_136 = _zz_340[1]; end endcase end @@ -4114,7 +4139,7 @@ module VexRiscv_inner ( endcase end - assign _zz_137 = _zz_326[11]; + assign _zz_137 = _zz_341[11]; always @ (*) begin _zz_138[19] = _zz_137; _zz_138[18] = _zz_137; @@ -4144,15 +4169,15 @@ module VexRiscv_inner ( execute_BranchPlugin_branch_src2 = {_zz_138,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_140,{{{_zz_564,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_142,{{{_zz_565,_zz_566},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_140,{{{_zz_579,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_142,{{{_zz_580,_zz_581},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_329}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_344}; end end endcase end - assign _zz_139 = _zz_327[19]; + assign _zz_139 = _zz_342[19]; always @ (*) begin _zz_140[10] = _zz_139; _zz_140[9] = _zz_139; @@ -4167,7 +4192,7 @@ module VexRiscv_inner ( _zz_140[0] = _zz_139; end - assign _zz_141 = _zz_328[11]; + assign _zz_141 = _zz_343[11]; always @ (*) begin _zz_142[18] = _zz_141; _zz_142[17] = _zz_141; @@ -4210,12 +4235,12 @@ module VexRiscv_inner ( assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); assign _zz_146 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_147 = _zz_330[0]; + assign _zz_147 = _zz_345[0]; assign _zz_148 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_149 = _zz_332[0]; + assign _zz_149 = _zz_347[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_233)begin + if(_zz_248)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4235,7 +4260,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_237)begin + if(_zz_252)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4384,6 +4409,46 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end + if(execute_CsrPlugin_csr_2820)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2822)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2824)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2826)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2828)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end if(execute_CsrPlugin_csr_3008)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4411,20 +4476,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_249)begin + if(_zz_264)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_250)begin + if(_zz_265)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_249)begin + if(_zz_264)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_250)begin + if(_zz_265)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4443,7 +4508,7 @@ module VexRiscv_inner ( assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_262) + case(_zz_277) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4456,45 +4521,45 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_334; + assign execute_CfuPlugin_functionsIds_0 = _zz_349; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_150 = _zz_335[11]; - always @ (*) begin - _zz_151[19] = _zz_150; - _zz_151[18] = _zz_150; - _zz_151[17] = _zz_150; - _zz_151[16] = _zz_150; - _zz_151[15] = _zz_150; - _zz_151[14] = _zz_150; - _zz_151[13] = _zz_150; - _zz_151[12] = _zz_150; - _zz_151[11] = _zz_150; - _zz_151[10] = _zz_150; - _zz_151[9] = _zz_150; - _zz_151[8] = _zz_150; - _zz_151[7] = _zz_150; - _zz_151[6] = _zz_150; - _zz_151[5] = _zz_150; - _zz_151[4] = _zz_150; - _zz_151[3] = _zz_150; - _zz_151[2] = _zz_150; - _zz_151[1] = _zz_150; - _zz_151[0] = _zz_150; + assign _zz_160 = _zz_350[11]; + always @ (*) begin + _zz_161[19] = _zz_160; + _zz_161[18] = _zz_160; + _zz_161[17] = _zz_160; + _zz_161[16] = _zz_160; + _zz_161[15] = _zz_160; + _zz_161[14] = _zz_160; + _zz_161[13] = _zz_160; + _zz_161[12] = _zz_160; + _zz_161[11] = _zz_160; + _zz_161[10] = _zz_160; + _zz_161[9] = _zz_160; + _zz_161[8] = _zz_160; + _zz_161[7] = _zz_160; + _zz_161[6] = _zz_160; + _zz_161[5] = _zz_160; + _zz_161[4] = _zz_160; + _zz_161[3] = _zz_160; + _zz_161[2] = _zz_160; + _zz_161[1] = _zz_160; + _zz_161[0] = _zz_160; end always @ (*) begin case(execute_CfuPlugin_CFU_ENCODING) `Input2Kind_defaultEncoding_RS : begin - _zz_152 = execute_RS2; + _zz_162 = execute_RS2; end default : begin - _zz_152 = {_zz_151,execute_INSTRUCTION[31 : 20]}; + _zz_162 = {_zz_161,execute_INSTRUCTION[31 : 20]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_152; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_162; assign CfuPlugin_bus_rsp_ready = ((1'b1 && (! memory_CfuPlugin_rsp_valid)) || memory_CfuPlugin_rsp_ready); assign memory_CfuPlugin_rsp_valid = CfuPlugin_bus_rsp_m2sPipe_rValid; assign memory_CfuPlugin_rsp_payload_response_ok = CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; @@ -4520,7 +4585,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_251) + case(_zz_266) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4534,7 +4599,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_251) + case(_zz_266) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4553,12 +4618,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_336) + $signed(_zz_337)); + assign writeBack_MulPlugin_result = ($signed(_zz_351) + $signed(_zz_352)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_228)begin - if(_zz_252)begin + if(_zz_243)begin + if(_zz_267)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4566,7 +4631,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_253)begin + if(_zz_268)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4577,32 +4642,32 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_341); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_356); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_153 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_153[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_342); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_343 : _zz_344); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_345[31:0]; - assign _zz_154 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_155 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_156 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_163 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_163[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_357); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_358 : _zz_359); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_360[31:0]; + assign _zz_164 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_165 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_166 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_157[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_157[31 : 0] = execute_RS1; + _zz_167[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_167[31 : 0] = execute_RS1; end - assign _zz_159 = (_zz_158 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_159 != 32'h0); + assign _zz_169 = (_zz_168 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_169 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_254) + case(_zz_269) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4616,7 +4681,7 @@ module VexRiscv_inner ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_160))begin + if((! _zz_170))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4628,7 +4693,7 @@ module VexRiscv_inner ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_254) + case(_zz_269) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4694,7 +4759,7 @@ module VexRiscv_inner ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_161) + case(_zz_171) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4704,202 +4769,237 @@ module VexRiscv_inner ( end always @ (*) begin - _zz_162 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_162[12 : 0] = 13'h1000; - _zz_162[25 : 20] = 6'h20; + _zz_172[12 : 0] = 13'h1000; + _zz_172[25 : 20] = 6'h20; end end always @ (*) begin - _zz_163 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_163[3 : 0] = 4'b1011; + _zz_173[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_164 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_164[4 : 0] = 5'h16; + _zz_174[4 : 0] = 5'h16; end end always @ (*) begin - _zz_165 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_165[5 : 0] = 6'h21; + _zz_175[5 : 0] = 6'h21; end end always @ (*) begin - _zz_166 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_166[31 : 30] = CsrPlugin_misa_base; - _zz_166[25 : 0] = CsrPlugin_misa_extensions; + _zz_176[31 : 30] = CsrPlugin_misa_base; + _zz_176[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_167 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_167[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_167[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_167[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_177[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_177[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_177[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_168 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_168[11 : 11] = CsrPlugin_mip_MEIP; - _zz_168[7 : 7] = CsrPlugin_mip_MTIP; - _zz_168[3 : 3] = CsrPlugin_mip_MSIP; + _zz_178[11 : 11] = CsrPlugin_mip_MEIP; + _zz_178[7 : 7] = CsrPlugin_mip_MTIP; + _zz_178[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_169 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_169[11 : 11] = CsrPlugin_mie_MEIE; - _zz_169[7 : 7] = CsrPlugin_mie_MTIE; - _zz_169[3 : 3] = CsrPlugin_mie_MSIE; + _zz_179[11 : 11] = CsrPlugin_mie_MEIE; + _zz_179[7 : 7] = CsrPlugin_mie_MTIE; + _zz_179[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_170 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_170[31 : 2] = CsrPlugin_mtvec_base; - _zz_170[1 : 0] = CsrPlugin_mtvec_mode; + _zz_180[31 : 2] = CsrPlugin_mtvec_base; + _zz_180[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_171[31 : 0] = CsrPlugin_mepc; + _zz_181[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_172[31 : 0] = CsrPlugin_mscratch; + _zz_182[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_173[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_173[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_183[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_183[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_174[31 : 0] = CsrPlugin_mtval; + _zz_184[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_175[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_185[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_176[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_186[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_177[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_187[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_178[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_188[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_179[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_189[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_180[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_190[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_191 = 32'h0; + if(execute_CsrPlugin_csr_2820)begin + _zz_191[31 : 0] = _zz_150; + end + end + + always @ (*) begin + _zz_192 = 32'h0; + if(execute_CsrPlugin_csr_2822)begin + _zz_192[31 : 0] = _zz_152; + end + end + + always @ (*) begin + _zz_193 = 32'h0; + if(execute_CsrPlugin_csr_2824)begin + _zz_193[31 : 0] = _zz_154; + end + end + + always @ (*) begin + _zz_194 = 32'h0; + if(execute_CsrPlugin_csr_2826)begin + _zz_194[31 : 0] = _zz_156; + end + end + + always @ (*) begin + _zz_195 = 32'h0; + if(execute_CsrPlugin_csr_2828)begin + _zz_195[31 : 0] = _zz_158; + end + end + + always @ (*) begin + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_181[31 : 0] = _zz_158; + _zz_196[31 : 0] = _zz_168; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_182[31 : 0] = _zz_159; + _zz_197[31 : 0] = _zz_169; end end - assign execute_CsrPlugin_readData = (((((_zz_162 | _zz_163) | (_zz_164 | _zz_165)) | ((_zz_567 | _zz_166) | (_zz_167 | _zz_168))) | (((_zz_169 | _zz_170) | (_zz_171 | _zz_172)) | ((_zz_173 | _zz_174) | (_zz_175 | _zz_176)))) | (((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | (_zz_181 | _zz_182))); - assign iBusWishbone_ADR = {_zz_362,_zz_183}; - assign iBusWishbone_CTI = ((_zz_183 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_172 | _zz_173) | (_zz_174 | _zz_175)) | ((_zz_582 | _zz_176) | (_zz_177 | _zz_178))) | (((_zz_179 | _zz_180) | (_zz_181 | _zz_182)) | ((_zz_183 | _zz_184) | (_zz_185 | _zz_186)))) | ((((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194))) | ((_zz_195 | _zz_196) | _zz_197))); + assign iBusWishbone_ADR = {_zz_377,_zz_198}; + assign iBusWishbone_CTI = ((_zz_198 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_255)begin + if(_zz_270)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_255)begin + if(_zz_270)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_184; + assign iBus_rsp_valid = _zz_199; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_190 = (dBus_cmd_payload_length != 3'b000); - assign _zz_186 = dBus_cmd_valid; - assign _zz_188 = dBus_cmd_payload_wr; - assign _zz_189 = (_zz_185 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_187 && (_zz_188 || _zz_189)); - assign dBusWishbone_ADR = ((_zz_190 ? {{dBus_cmd_payload_address[31 : 5],_zz_185},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_190 ? (_zz_189 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_205 = (dBus_cmd_payload_length != 3'b000); + assign _zz_201 = dBus_cmd_valid; + assign _zz_203 = dBus_cmd_payload_wr; + assign _zz_204 = (_zz_200 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_202 && (_zz_203 || _zz_204)); + assign dBusWishbone_ADR = ((_zz_205 ? {{dBus_cmd_payload_address[31 : 5],_zz_200},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_205 ? (_zz_204 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_188 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_188; + assign dBusWishbone_SEL = (_zz_203 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_203; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_187 = (_zz_186 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_186; - assign dBusWishbone_STB = _zz_186; - assign dBus_rsp_valid = _zz_191; + assign _zz_202 = (_zz_201 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_201; + assign dBusWishbone_STB = _zz_201; + assign dBus_rsp_valid = _zz_206; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4946,18 +5046,18 @@ module VexRiscv_inner ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_m2sPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_158 <= 32'h0; + _zz_168 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_161 <= 3'b000; + _zz_171 <= 3'b000; memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; memory_to_writeBack_INSTRUCTION <= 32'h0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_183 <= 3'b000; - _zz_184 <= 1'b0; - _zz_185 <= 3'b000; - _zz_191 <= 1'b0; + _zz_198 <= 3'b000; + _zz_199 <= 1'b0; + _zz_200 <= 3'b000; + _zz_206 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5038,7 +5138,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_256)begin + if(_zz_271)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5070,14 +5170,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_257)begin - if(_zz_258)begin + if(_zz_272)begin + if(_zz_273)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_259)begin + if(_zz_274)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_260)begin + if(_zz_275)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5102,7 +5202,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_238)begin + if(_zz_253)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5113,8 +5213,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_239)begin - case(_zz_241) + if(_zz_254)begin + case(_zz_256) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5168,25 +5268,25 @@ module VexRiscv_inner ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_161) + case(_zz_171) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_161 <= 3'b001; + _zz_171 <= 3'b001; end end 3'b001 : begin - _zz_161 <= 3'b010; + _zz_171 <= 3'b010; end 3'b010 : begin - _zz_161 <= 3'b011; + _zz_171 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_161 <= 3'b100; + _zz_171 <= 3'b100; end end 3'b100 : begin - _zz_161 <= 3'b000; + _zz_171 <= 3'b000; end default : begin end @@ -5200,35 +5300,35 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_355[0]; - CsrPlugin_mstatus_MIE <= _zz_356[0]; + CsrPlugin_mstatus_MPIE <= _zz_370[0]; + CsrPlugin_mstatus_MIE <= _zz_371[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_358[0]; - CsrPlugin_mie_MTIE <= _zz_359[0]; - CsrPlugin_mie_MSIE <= _zz_360[0]; + CsrPlugin_mie_MEIE <= _zz_373[0]; + CsrPlugin_mie_MTIE <= _zz_374[0]; + CsrPlugin_mie_MSIE <= _zz_375[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_255)begin + if(_zz_270)begin if(iBusWishbone_ACK)begin - _zz_183 <= (_zz_183 + 3'b001); + _zz_198 <= (_zz_198 + 3'b001); end end - _zz_184 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_186 && _zz_187))begin - _zz_185 <= (_zz_185 + 3'b001); - if(_zz_189)begin - _zz_185 <= 3'b000; + _zz_199 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_201 && _zz_202))begin + _zz_200 <= (_zz_200 + 3'b001); + if(_zz_204)begin + _zz_200 <= 3'b000; end end - _zz_191 <= ((_zz_186 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_206 <= ((_zz_201 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5242,7 +5342,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_256)begin + if(_zz_271)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5269,7 +5369,7 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_233)begin + if(_zz_248)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_147 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_147 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end @@ -5277,7 +5377,7 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_237)begin + if(_zz_252)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); end @@ -5285,21 +5385,21 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_257)begin - if(_zz_258)begin + if(_zz_272)begin + if(_zz_273)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_259)begin + if(_zz_274)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_260)begin + if(_zz_275)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_238)begin + if(_zz_253)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5313,6 +5413,21 @@ module VexRiscv_inner ( end endcase end + if(_zz_151[0])begin + _zz_150 <= (_zz_150 + 32'h00000001); + end + if(_zz_153[0])begin + _zz_152 <= (_zz_152 + 32'h00000001); + end + if(_zz_155[0])begin + _zz_154 <= (_zz_154 + 32'h00000001); + end + if(_zz_157[0])begin + _zz_156 <= (_zz_156 + 32'h00000001); + end + if(_zz_159[0])begin + _zz_158 <= (_zz_158 + 32'h00000001); + end if(CfuPlugin_bus_rsp_ready)begin CfuPlugin_bus_rsp_m2sPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; @@ -5323,20 +5438,20 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_228)begin - if(_zz_252)begin + if(_zz_243)begin + if(_zz_267)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_346[31:0]; + memory_DivPlugin_div_result <= _zz_361[31:0]; end end end - if(_zz_253)begin + if(_zz_268)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_156 ? (~ _zz_157) : _zz_157) + _zz_352); - memory_DivPlugin_rs2 <= ((_zz_155 ? (~ execute_RS2) : execute_RS2) + _zz_354); - memory_DivPlugin_div_needRevert <= ((_zz_156 ^ (_zz_155 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_166 ? (~ _zz_167) : _zz_167) + _zz_367); + memory_DivPlugin_rs2 <= ((_zz_165 ? (~ execute_RS2) : execute_RS2) + _zz_369); + memory_DivPlugin_div_needRevert <= ((_zz_166 ^ (_zz_165 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5588,6 +5703,36 @@ module VexRiscv_inner ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end @@ -5596,7 +5741,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_357[0]; + CsrPlugin_mip_MSIP <= _zz_372[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5617,7 +5762,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_361[0]; + CsrPlugin_mcause_interrupt <= _zz_376[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5646,6 +5791,56 @@ module VexRiscv_inner ( CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end end + if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_150 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + end + end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end @@ -5660,8 +5855,8 @@ module VexRiscv_inner ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_55; end - _zz_160 <= debug_bus_cmd_payload_address[2]; - if(_zz_235)begin + _zz_170 <= debug_bus_cmd_payload_address[2]; + if(_zz_250)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -5679,7 +5874,7 @@ module VexRiscv_inner ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_254) + case(_zz_269) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -5707,13 +5902,13 @@ module VexRiscv_inner ( end endcase end - if(_zz_235)begin - if(_zz_236)begin + if(_zz_250)begin + if(_zz_251)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_240)begin + if(_zz_255)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end diff --git a/pythondata_cpu_vexriscv/verilog/genWrapper.py b/pythondata_cpu_vexriscv/verilog/genWrapper.py index c850a71..a648eba 100755 --- a/pythondata_cpu_vexriscv/verilog/genWrapper.py +++ b/pythondata_cpu_vexriscv/verilog/genWrapper.py @@ -1,4 +1,4 @@ -#!/usr/bin/python +#!/usr/bin/env python3 import sys import re diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index 1ab87db..b4dbad5 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -10,6 +10,7 @@ import vexriscv.plugin._ import scala.collection.mutable.ArrayBuffer + object SpinalConfig extends spinal.core.SpinalConfig( defaultConfigForClockDomains = ClockDomainConfig( resetKind = spinal.core.SYNC @@ -25,6 +26,7 @@ case class ArgConfig( dCacheSize : Int = 4096, mulDiv : Boolean = true, cfu : Boolean = false, + perfCSRs : Int = 0, atomics: Boolean = false, compressedGen: Boolean = false, singleCycleMulDiv : Boolean = true, @@ -62,6 +64,7 @@ object GenCoreDefault{ opt[Int]("dCacheSize") action { (v, c) => c.copy(dCacheSize = v) } text("Set data cache size, 0 mean no cache") opt[Boolean]("mulDiv") action { (v, c) => c.copy(mulDiv = v) } text("set RV32IM") opt[Boolean]("cfu") action { (v, c) => c.copy(cfu = v) } text("If true, add SIMD ADD custom function unit") + opt[Int]("perfCSRs") action { (v, c) => c.copy(perfCSRs = v) } text("Number of pausable performance counter CSRs to add (default 0)") opt[Boolean]("atomics") action { (v, c) => c.copy(mulDiv = v) } text("set RV32I[A]") opt[Boolean]("compressedGen") action { (v, c) => c.copy(compressedGen = v) } text("set RV32I[C]") opt[Boolean]("singleCycleMulDiv") action { (v, c) => c.copy(singleCycleMulDiv = v) } text("If true, MUL/DIV are single-cycle") @@ -194,6 +197,11 @@ object GenCoreDefault{ new YamlPlugin(argConfig.outputFile.concat(".yaml")) ) + if(argConfig.perfCSRs > 0) { + plugins ++= List( + new PerfCsrPlugin(argConfig.perfCSRs) + ) + } if(argConfig.cfu) { plugins ++= List( new CfuPlugin( @@ -306,3 +314,27 @@ class ForceRamBlockPhase() extends spinal.core.internals.Phase{ } override def hasNetlistImpact: Boolean = false } + + +class PerfCsrPlugin( val csrCount : Int ) extends Plugin[VexRiscv]{ + override def build(pipeline: VexRiscv): Unit = { + import pipeline._ + import pipeline.config._ + + pipeline plug new Area{ + for (idx <- 0 until csrCount) { + + val cycleCounter = Reg(UInt(32 bits)) + val enable = Reg(UInt(32 bits)) // only the LSB is used + + when ( enable(0) ) { + cycleCounter := cycleCounter + 1 + } + + val csrService = pipeline.service(classOf[CsrInterface]) + csrService.rw(0xB04 + idx * 2, cycleCounter) + csrService.w( 0xB04 + idx * 2 + 1, enable) + } + } + } +} From f022529bb419c7a04f9ba1b61e931127b7220919 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Thu, 7 Jan 2021 13:41:14 -0800 Subject: [PATCH 05/30] Increase to 8 perf counter CSRs; rebuild. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 4 +- .../verilog/VexRiscv_FullCfu.v | 2073 ++++++++-------- .../verilog/VexRiscv_FullCfuDebug.v | 2189 +++++++++-------- 3 files changed, 2250 insertions(+), 2016 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index bdc4398..c0e4b56 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -34,14 +34,14 @@ VexRiscv_FullDebug.v: $(SRC) # CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --cfu true --perfCSRs 5 --outputFile VexRiscv_FullCfu" + sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfu" sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v /bin/mv tmp.v $@ ./genWrapper.py $@ > wrap$@ # CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfuDebug.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --cfu true --perfCSRs 5 --outputFile VexRiscv_FullCfuDebug" + sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfuDebug" sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v /bin/mv tmp.v $@ ./genWrapper.py $@ > wrap$@ diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index 5d8ccda..e78ca25 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : b386c12cdfb49fee6855bbbd273eefd149b82dfe +// Generator : SpinalHDL v1.4.2 git head : 07a72e20035b64cf586cbf04df799cb4bf961010 // Component : VexRiscv -// Git hash : b386c12cdfb49fee6855bbbd273eefd149b82dfe +// Git hash : 07a72e20035b64cf586cbf04df799cb4bf961010 `define Input2Kind_defaultEncoding_type [0:0] @@ -87,37 +87,37 @@ module VexRiscv_inner ( input clk, input reset ); - wire _zz_204; - wire _zz_205; - wire _zz_206; - wire _zz_207; - wire _zz_208; - wire _zz_209; - wire _zz_210; - wire _zz_211; - reg _zz_212; wire _zz_213; - wire [31:0] _zz_214; + wire _zz_214; wire _zz_215; - wire [31:0] _zz_216; - reg _zz_217; + wire _zz_216; + wire _zz_217; wire _zz_218; wire _zz_219; - wire [31:0] _zz_220; - wire _zz_221; + wire _zz_220; + reg _zz_221; wire _zz_222; - wire _zz_223; + wire [31:0] _zz_223; wire _zz_224; - wire _zz_225; - wire _zz_226; + wire [31:0] _zz_225; + reg _zz_226; wire _zz_227; wire _zz_228; - wire [3:0] _zz_229; + wire [31:0] _zz_229; wire _zz_230; wire _zz_231; - reg [31:0] _zz_232; - reg [31:0] _zz_233; - reg [31:0] _zz_234; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire [3:0] _zz_238; + wire _zz_239; + wire _zz_240; + reg [31:0] _zz_241; + reg [31:0] _zz_242; + reg [31:0] _zz_243; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -149,22 +149,13 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; wire _zz_244; wire _zz_245; wire _zz_246; wire _zz_247; wire _zz_248; wire _zz_249; - wire [1:0] _zz_250; + wire _zz_250; wire _zz_251; wire _zz_252; wire _zz_253; @@ -173,8 +164,8 @@ module VexRiscv_inner ( wire _zz_256; wire _zz_257; wire _zz_258; - wire _zz_259; - wire [1:0] _zz_260; + wire [1:0] _zz_259; + wire _zz_260; wire _zz_261; wire _zz_262; wire _zz_263; @@ -185,28 +176,28 @@ module VexRiscv_inner ( wire _zz_268; wire [1:0] _zz_269; wire _zz_270; - wire [1:0] _zz_271; - wire [51:0] _zz_272; - wire [51:0] _zz_273; - wire [51:0] _zz_274; - wire [32:0] _zz_275; - wire [51:0] _zz_276; - wire [49:0] _zz_277; - wire [51:0] _zz_278; - wire [49:0] _zz_279; - wire [51:0] _zz_280; - wire [32:0] _zz_281; - wire [31:0] _zz_282; - wire [32:0] _zz_283; - wire [0:0] _zz_284; - wire [0:0] _zz_285; - wire [0:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; - wire [0:0] _zz_289; - wire [0:0] _zz_290; - wire [0:0] _zz_291; - wire [0:0] _zz_292; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire [1:0] _zz_278; + wire _zz_279; + wire [1:0] _zz_280; + wire [51:0] _zz_281; + wire [51:0] _zz_282; + wire [51:0] _zz_283; + wire [32:0] _zz_284; + wire [51:0] _zz_285; + wire [49:0] _zz_286; + wire [51:0] _zz_287; + wire [49:0] _zz_288; + wire [51:0] _zz_289; + wire [32:0] _zz_290; + wire [31:0] _zz_291; + wire [32:0] _zz_292; wire [0:0] _zz_293; wire [0:0] _zz_294; wire [0:0] _zz_295; @@ -216,270 +207,279 @@ module VexRiscv_inner ( wire [0:0] _zz_299; wire [0:0] _zz_300; wire [0:0] _zz_301; - wire [3:0] _zz_302; - wire [2:0] _zz_303; - wire [31:0] _zz_304; - wire [11:0] _zz_305; - wire [31:0] _zz_306; - wire [19:0] _zz_307; - wire [11:0] _zz_308; - wire [31:0] _zz_309; - wire [31:0] _zz_310; - wire [19:0] _zz_311; - wire [11:0] _zz_312; - wire [2:0] _zz_313; - wire [2:0] _zz_314; - wire [0:0] _zz_315; - wire [2:0] _zz_316; - wire [4:0] _zz_317; - wire [11:0] _zz_318; - wire [11:0] _zz_319; - wire [31:0] _zz_320; - wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [31:0] _zz_326; + wire [0:0] _zz_302; + wire [0:0] _zz_303; + wire [0:0] _zz_304; + wire [0:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire [3:0] _zz_311; + wire [2:0] _zz_312; + wire [31:0] _zz_313; + wire [11:0] _zz_314; + wire [31:0] _zz_315; + wire [19:0] _zz_316; + wire [11:0] _zz_317; + wire [31:0] _zz_318; + wire [31:0] _zz_319; + wire [19:0] _zz_320; + wire [11:0] _zz_321; + wire [2:0] _zz_322; + wire [2:0] _zz_323; + wire [0:0] _zz_324; + wire [2:0] _zz_325; + wire [4:0] _zz_326; wire [11:0] _zz_327; - wire [19:0] _zz_328; - wire [11:0] _zz_329; + wire [11:0] _zz_328; + wire [31:0] _zz_329; wire [31:0] _zz_330; wire [31:0] _zz_331; wire [31:0] _zz_332; - wire [11:0] _zz_333; - wire [19:0] _zz_334; - wire [11:0] _zz_335; - wire [2:0] _zz_336; - wire [1:0] _zz_337; - wire [1:0] _zz_338; - wire [1:0] _zz_339; - wire [1:0] _zz_340; - wire [2:0] _zz_341; + wire [31:0] _zz_333; + wire [31:0] _zz_334; + wire [31:0] _zz_335; + wire [11:0] _zz_336; + wire [19:0] _zz_337; + wire [11:0] _zz_338; + wire [31:0] _zz_339; + wire [31:0] _zz_340; + wire [31:0] _zz_341; wire [11:0] _zz_342; - wire [65:0] _zz_343; - wire [65:0] _zz_344; - wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [0:0] _zz_347; - wire [5:0] _zz_348; - wire [32:0] _zz_349; - wire [31:0] _zz_350; - wire [31:0] _zz_351; - wire [32:0] _zz_352; - wire [32:0] _zz_353; - wire [32:0] _zz_354; - wire [32:0] _zz_355; + wire [19:0] _zz_343; + wire [11:0] _zz_344; + wire [2:0] _zz_345; + wire [1:0] _zz_346; + wire [1:0] _zz_347; + wire [1:0] _zz_348; + wire [1:0] _zz_349; + wire [2:0] _zz_350; + wire [11:0] _zz_351; + wire [65:0] _zz_352; + wire [65:0] _zz_353; + wire [31:0] _zz_354; + wire [31:0] _zz_355; wire [0:0] _zz_356; - wire [32:0] _zz_357; - wire [0:0] _zz_358; - wire [32:0] _zz_359; - wire [0:0] _zz_360; - wire [31:0] _zz_361; - wire [0:0] _zz_362; - wire [0:0] _zz_363; - wire [0:0] _zz_364; + wire [5:0] _zz_357; + wire [32:0] _zz_358; + wire [31:0] _zz_359; + wire [31:0] _zz_360; + wire [32:0] _zz_361; + wire [32:0] _zz_362; + wire [32:0] _zz_363; + wire [32:0] _zz_364; wire [0:0] _zz_365; - wire [0:0] _zz_366; + wire [32:0] _zz_366; wire [0:0] _zz_367; - wire [0:0] _zz_368; - wire [26:0] _zz_369; - wire _zz_370; - wire _zz_371; - wire [1:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire [31:0] _zz_375; - wire _zz_376; + wire [32:0] _zz_368; + wire [0:0] _zz_369; + wire [31:0] _zz_370; + wire [0:0] _zz_371; + wire [0:0] _zz_372; + wire [0:0] _zz_373; + wire [0:0] _zz_374; + wire [0:0] _zz_375; + wire [0:0] _zz_376; wire [0:0] _zz_377; - wire [14:0] _zz_378; - wire [31:0] _zz_379; - wire [31:0] _zz_380; - wire [31:0] _zz_381; - wire _zz_382; - wire [0:0] _zz_383; - wire [8:0] _zz_384; - wire [31:0] _zz_385; - wire [31:0] _zz_386; - wire [31:0] _zz_387; - wire _zz_388; - wire [0:0] _zz_389; - wire [2:0] _zz_390; + wire [26:0] _zz_378; + wire _zz_379; + wire _zz_380; + wire [1:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire [31:0] _zz_384; + wire _zz_385; + wire [0:0] _zz_386; + wire [14:0] _zz_387; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; wire _zz_391; - wire _zz_392; - wire _zz_393; + wire [0:0] _zz_392; + wire [8:0] _zz_393; wire [31:0] _zz_394; wire [31:0] _zz_395; - wire _zz_396; + wire [31:0] _zz_396; wire _zz_397; wire [0:0] _zz_398; - wire [26:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire [31:0] _zz_402; - wire [0:0] _zz_403; - wire [0:0] _zz_404; - wire [1:0] _zz_405; - wire [1:0] _zz_406; - wire _zz_407; - wire [0:0] _zz_408; - wire [21:0] _zz_409; + wire [2:0] _zz_399; + wire _zz_400; + wire _zz_401; + wire _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire _zz_405; + wire _zz_406; + wire [0:0] _zz_407; + wire [26:0] _zz_408; + wire [31:0] _zz_409; wire [31:0] _zz_410; wire [31:0] _zz_411; - wire [31:0] _zz_412; - wire [31:0] _zz_413; - wire [31:0] _zz_414; - wire [31:0] _zz_415; - wire [0:0] _zz_416; + wire [0:0] _zz_412; + wire [0:0] _zz_413; + wire [1:0] _zz_414; + wire [1:0] _zz_415; + wire _zz_416; wire [0:0] _zz_417; - wire [2:0] _zz_418; - wire [2:0] _zz_419; - wire _zz_420; - wire [0:0] _zz_421; - wire [18:0] _zz_422; + wire [21:0] _zz_418; + wire [31:0] _zz_419; + wire [31:0] _zz_420; + wire [31:0] _zz_421; + wire [31:0] _zz_422; wire [31:0] _zz_423; wire [31:0] _zz_424; - wire [31:0] _zz_425; - wire [31:0] _zz_426; - wire _zz_427; - wire _zz_428; - wire [31:0] _zz_429; - wire [31:0] _zz_430; - wire _zz_431; - wire [0:0] _zz_432; - wire [0:0] _zz_433; - wire _zz_434; - wire [0:0] _zz_435; - wire [15:0] _zz_436; - wire [31:0] _zz_437; - wire _zz_438; - wire _zz_439; + wire [0:0] _zz_425; + wire [0:0] _zz_426; + wire [2:0] _zz_427; + wire [2:0] _zz_428; + wire _zz_429; + wire [0:0] _zz_430; + wire [18:0] _zz_431; + wire [31:0] _zz_432; + wire [31:0] _zz_433; + wire [31:0] _zz_434; + wire [31:0] _zz_435; + wire _zz_436; + wire _zz_437; + wire [31:0] _zz_438; + wire [31:0] _zz_439; wire _zz_440; - wire [2:0] _zz_441; - wire [2:0] _zz_442; + wire [0:0] _zz_441; + wire [0:0] _zz_442; wire _zz_443; wire [0:0] _zz_444; - wire [12:0] _zz_445; - wire _zz_446; + wire [15:0] _zz_445; + wire [31:0] _zz_446; wire _zz_447; wire _zz_448; - wire [0:0] _zz_449; + wire _zz_449; wire [2:0] _zz_450; - wire _zz_451; - wire [5:0] _zz_452; - wire [5:0] _zz_453; - wire _zz_454; - wire [0:0] _zz_455; - wire [9:0] _zz_456; - wire [31:0] _zz_457; - wire [31:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire _zz_462; - wire [0:0] _zz_463; + wire [2:0] _zz_451; + wire _zz_452; + wire [0:0] _zz_453; + wire [12:0] _zz_454; + wire _zz_455; + wire _zz_456; + wire _zz_457; + wire [0:0] _zz_458; + wire [2:0] _zz_459; + wire _zz_460; + wire [5:0] _zz_461; + wire [5:0] _zz_462; + wire _zz_463; wire [0:0] _zz_464; - wire [31:0] _zz_465; - wire _zz_466; - wire [0:0] _zz_467; - wire [3:0] _zz_468; - wire [0:0] _zz_469; - wire [3:0] _zz_470; - wire [5:0] _zz_471; - wire [5:0] _zz_472; - wire _zz_473; - wire [0:0] _zz_474; - wire [7:0] _zz_475; - wire [31:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; - wire [31:0] _zz_479; - wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [0:0] _zz_484; - wire [1:0] _zz_485; - wire _zz_486; - wire [0:0] _zz_487; - wire [1:0] _zz_488; - wire [0:0] _zz_489; - wire [3:0] _zz_490; - wire [0:0] _zz_491; - wire [0:0] _zz_492; - wire [1:0] _zz_493; + wire [9:0] _zz_465; + wire [31:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire _zz_471; + wire [0:0] _zz_472; + wire [0:0] _zz_473; + wire [31:0] _zz_474; + wire _zz_475; + wire [0:0] _zz_476; + wire [3:0] _zz_477; + wire [0:0] _zz_478; + wire [3:0] _zz_479; + wire [5:0] _zz_480; + wire [5:0] _zz_481; + wire _zz_482; + wire [0:0] _zz_483; + wire [7:0] _zz_484; + wire [31:0] _zz_485; + wire [31:0] _zz_486; + wire [31:0] _zz_487; + wire [31:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; + wire [31:0] _zz_491; + wire [31:0] _zz_492; + wire [0:0] _zz_493; wire [1:0] _zz_494; wire _zz_495; wire [0:0] _zz_496; - wire [5:0] _zz_497; - wire [31:0] _zz_498; - wire [31:0] _zz_499; - wire _zz_500; - wire _zz_501; - wire [31:0] _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire _zz_505; - wire _zz_506; + wire [1:0] _zz_497; + wire [0:0] _zz_498; + wire [3:0] _zz_499; + wire [0:0] _zz_500; + wire [0:0] _zz_501; + wire [1:0] _zz_502; + wire [1:0] _zz_503; + wire _zz_504; + wire [0:0] _zz_505; + wire [5:0] _zz_506; wire [31:0] _zz_507; wire [31:0] _zz_508; wire _zz_509; - wire [0:0] _zz_510; - wire [1:0] _zz_511; + wire _zz_510; + wire [31:0] _zz_511; wire [31:0] _zz_512; wire [31:0] _zz_513; wire _zz_514; wire _zz_515; - wire [0:0] _zz_516; - wire [0:0] _zz_517; + wire [31:0] _zz_516; + wire [31:0] _zz_517; wire _zz_518; wire [0:0] _zz_519; - wire [3:0] _zz_520; + wire [1:0] _zz_520; wire [31:0] _zz_521; wire [31:0] _zz_522; - wire [31:0] _zz_523; - wire [31:0] _zz_524; - wire [31:0] _zz_525; - wire [31:0] _zz_526; - wire [31:0] _zz_527; - wire _zz_528; - wire _zz_529; + wire _zz_523; + wire _zz_524; + wire [0:0] _zz_525; + wire [0:0] _zz_526; + wire _zz_527; + wire [0:0] _zz_528; + wire [3:0] _zz_529; wire [31:0] _zz_530; wire [31:0] _zz_531; wire [31:0] _zz_532; wire [31:0] _zz_533; - wire [0:0] _zz_534; - wire [2:0] _zz_535; - wire [0:0] _zz_536; - wire [0:0] _zz_537; + wire [31:0] _zz_534; + wire [31:0] _zz_535; + wire [31:0] _zz_536; + wire _zz_537; wire _zz_538; - wire [0:0] _zz_539; - wire [1:0] _zz_540; + wire [31:0] _zz_539; + wire [31:0] _zz_540; wire [31:0] _zz_541; wire [31:0] _zz_542; - wire [31:0] _zz_543; - wire _zz_544; - wire _zz_545; - wire [31:0] _zz_546; + wire [0:0] _zz_543; + wire [2:0] _zz_544; + wire [0:0] _zz_545; + wire [0:0] _zz_546; wire _zz_547; wire [0:0] _zz_548; - wire [0:0] _zz_549; - wire [0:0] _zz_550; - wire [0:0] _zz_551; - wire [1:0] _zz_552; - wire [1:0] _zz_553; - wire [0:0] _zz_554; - wire [0:0] _zz_555; - wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire [31:0] _zz_559; - wire [31:0] _zz_560; - wire [31:0] _zz_561; - wire _zz_562; - wire _zz_563; - wire _zz_564; + wire [1:0] _zz_549; + wire [31:0] _zz_550; + wire [31:0] _zz_551; + wire [31:0] _zz_552; + wire _zz_553; + wire _zz_554; + wire [31:0] _zz_555; + wire _zz_556; + wire [0:0] _zz_557; + wire [0:0] _zz_558; + wire [0:0] _zz_559; + wire [0:0] _zz_560; + wire [1:0] _zz_561; + wire [1:0] _zz_562; + wire [0:0] _zz_563; + wire [0:0] _zz_564; wire [31:0] _zz_565; + wire [31:0] _zz_566; + wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [31:0] _zz_570; + wire _zz_571; + wire _zz_572; + wire _zz_573; + wire [31:0] _zz_574; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1078,13 +1078,19 @@ module VexRiscv_inner ( reg [31:0] _zz_156; reg [31:0] _zz_157; reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [2:0] execute_CfuPlugin_functionsIds_0; - wire _zz_159; - reg [19:0] _zz_160; - reg [31:0] _zz_161; + wire _zz_165; + reg [19:0] _zz_166; + reg [31:0] _zz_167; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1116,18 +1122,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_162; + wire [31:0] _zz_168; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_163; - wire _zz_164; - wire _zz_165; - reg [32:0] _zz_166; + wire [31:0] _zz_169; + wire _zz_170; + wire _zz_171; + reg [32:0] _zz_172; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_167; - wire [31:0] _zz_168; + reg [31:0] _zz_173; + wire [31:0] _zz_174; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1223,14 +1229,14 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2827; reg execute_CsrPlugin_csr_2828; reg execute_CsrPlugin_csr_2829; + reg execute_CsrPlugin_csr_2830; + reg execute_CsrPlugin_csr_2831; + reg execute_CsrPlugin_csr_2832; + reg execute_CsrPlugin_csr_2833; + reg execute_CsrPlugin_csr_2834; + reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; reg [31:0] _zz_175; reg [31:0] _zz_176; reg [31:0] _zz_177; @@ -1251,16 +1257,25 @@ module VexRiscv_inner ( reg [31:0] _zz_192; reg [31:0] _zz_193; reg [31:0] _zz_194; - reg [2:0] _zz_195; - reg _zz_196; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; + reg [31:0] _zz_199; + reg [31:0] _zz_200; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [2:0] _zz_204; + reg _zz_205; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - reg _zz_203; + reg [2:0] _zz_206; + wire _zz_207; + wire _zz_208; + wire _zz_209; + wire _zz_210; + wire _zz_211; + reg _zz_212; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; @@ -1354,346 +1369,346 @@ module VexRiscv_inner ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_235 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_236 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_237 = 1'b1; - assign _zz_238 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_239 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_240 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_241 = ((_zz_209 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_242 = ((_zz_209 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_243 = ((_zz_209 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_244 = ((_zz_209 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_245 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_246 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_247 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_248 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_249 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_250 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_251 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_253 = (1'b0 || (! 1'b1)); - assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_255 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_256 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_257 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_258 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_260 = execute_INSTRUCTION[13 : 12]; - assign _zz_261 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_262 = (! memory_arbitration_isStuck); - assign _zz_263 = (iBus_cmd_valid || (_zz_195 != 3'b000)); - assign _zz_264 = (_zz_231 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_265 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_266 = ((_zz_142 && 1'b1) && (! 1'b0)); - assign _zz_267 = ((_zz_143 && 1'b1) && (! 1'b0)); - assign _zz_268 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_269 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_270 = execute_INSTRUCTION[13]; - assign _zz_271 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_272 = ($signed(_zz_273) + $signed(_zz_278)); - assign _zz_273 = ($signed(_zz_274) + $signed(_zz_276)); - assign _zz_274 = 52'h0; - assign _zz_275 = {1'b0,memory_MUL_LL}; - assign _zz_276 = {{19{_zz_275[32]}}, _zz_275}; - assign _zz_277 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_278 = {{2{_zz_277[49]}}, _zz_277}; - assign _zz_279 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_280 = {{2{_zz_279[49]}}, _zz_279}; - assign _zz_281 = ($signed(_zz_283) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_282 = _zz_281[31 : 0]; - assign _zz_283 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_284 = _zz_91[33 : 33]; - assign _zz_285 = _zz_91[32 : 32]; - assign _zz_286 = _zz_91[31 : 31]; - assign _zz_287 = _zz_91[30 : 30]; - assign _zz_288 = _zz_91[28 : 28]; - assign _zz_289 = _zz_91[25 : 25]; - assign _zz_290 = _zz_91[17 : 17]; - assign _zz_291 = _zz_91[16 : 16]; - assign _zz_292 = _zz_91[13 : 13]; - assign _zz_293 = _zz_91[12 : 12]; - assign _zz_294 = _zz_91[11 : 11]; - assign _zz_295 = _zz_91[15 : 15]; - assign _zz_296 = _zz_91[5 : 5]; - assign _zz_297 = _zz_91[3 : 3]; - assign _zz_298 = _zz_91[20 : 20]; - assign _zz_299 = _zz_91[10 : 10]; - assign _zz_300 = _zz_91[4 : 4]; - assign _zz_301 = _zz_91[0 : 0]; - assign _zz_302 = (_zz_59 - 4'b0001); - assign _zz_303 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_304 = {29'd0, _zz_303}; - assign _zz_305 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_306 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_307 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_308 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_309 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_310 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_311 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_312 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_313 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_314 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_315 = execute_SRC_LESS; - assign _zz_316 = 3'b100; - assign _zz_317 = execute_INSTRUCTION[19 : 15]; - assign _zz_318 = execute_INSTRUCTION[31 : 20]; - assign _zz_319 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_320 = ($signed(_zz_321) + $signed(_zz_324)); - assign _zz_321 = ($signed(_zz_322) + $signed(_zz_323)); - assign _zz_322 = execute_SRC1; - assign _zz_323 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_324 = (execute_SRC_USE_SUB_LESS ? _zz_325 : _zz_326); - assign _zz_325 = 32'h00000001; - assign _zz_326 = 32'h0; + assign _zz_244 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_245 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_246 = 1'b1; + assign _zz_247 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_248 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_249 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_250 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_251 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_252 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_253 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_254 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_255 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_256 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_257 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_258 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_259 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_260 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_261 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_262 = (1'b0 || (! 1'b1)); + assign _zz_263 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_264 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_265 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_266 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_267 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_268 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_269 = execute_INSTRUCTION[13 : 12]; + assign _zz_270 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_271 = (! memory_arbitration_isStuck); + assign _zz_272 = (iBus_cmd_valid || (_zz_204 != 3'b000)); + assign _zz_273 = (_zz_240 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_274 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_275 = ((_zz_142 && 1'b1) && (! 1'b0)); + assign _zz_276 = ((_zz_143 && 1'b1) && (! 1'b0)); + assign _zz_277 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_278 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_279 = execute_INSTRUCTION[13]; + assign _zz_280 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_281 = ($signed(_zz_282) + $signed(_zz_287)); + assign _zz_282 = ($signed(_zz_283) + $signed(_zz_285)); + assign _zz_283 = 52'h0; + assign _zz_284 = {1'b0,memory_MUL_LL}; + assign _zz_285 = {{19{_zz_284[32]}}, _zz_284}; + assign _zz_286 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_287 = {{2{_zz_286[49]}}, _zz_286}; + assign _zz_288 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_289 = {{2{_zz_288[49]}}, _zz_288}; + assign _zz_290 = ($signed(_zz_292) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_291 = _zz_290[31 : 0]; + assign _zz_292 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_293 = _zz_91[33 : 33]; + assign _zz_294 = _zz_91[32 : 32]; + assign _zz_295 = _zz_91[31 : 31]; + assign _zz_296 = _zz_91[30 : 30]; + assign _zz_297 = _zz_91[28 : 28]; + assign _zz_298 = _zz_91[25 : 25]; + assign _zz_299 = _zz_91[17 : 17]; + assign _zz_300 = _zz_91[16 : 16]; + assign _zz_301 = _zz_91[13 : 13]; + assign _zz_302 = _zz_91[12 : 12]; + assign _zz_303 = _zz_91[11 : 11]; + assign _zz_304 = _zz_91[15 : 15]; + assign _zz_305 = _zz_91[5 : 5]; + assign _zz_306 = _zz_91[3 : 3]; + assign _zz_307 = _zz_91[20 : 20]; + assign _zz_308 = _zz_91[10 : 10]; + assign _zz_309 = _zz_91[4 : 4]; + assign _zz_310 = _zz_91[0 : 0]; + assign _zz_311 = (_zz_59 - 4'b0001); + assign _zz_312 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_313 = {29'd0, _zz_312}; + assign _zz_314 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_315 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_316 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_317 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_318 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_319 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_321 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_322 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_323 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_324 = execute_SRC_LESS; + assign _zz_325 = 3'b100; + assign _zz_326 = execute_INSTRUCTION[19 : 15]; assign _zz_327 = execute_INSTRUCTION[31 : 20]; - assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_329 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_330 = {_zz_130,execute_INSTRUCTION[31 : 20]}; - assign _zz_331 = {{_zz_132,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_332 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_333 = execute_INSTRUCTION[31 : 20]; - assign _zz_334 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_335 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_336 = 3'b100; - assign _zz_337 = (_zz_145 & (~ _zz_338)); - assign _zz_338 = (_zz_145 - 2'b01); - assign _zz_339 = (_zz_147 & (~ _zz_340)); - assign _zz_340 = (_zz_147 - 2'b01); - assign _zz_341 = execute_INSTRUCTION[14 : 12]; + assign _zz_328 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_329 = ($signed(_zz_330) + $signed(_zz_333)); + assign _zz_330 = ($signed(_zz_331) + $signed(_zz_332)); + assign _zz_331 = execute_SRC1; + assign _zz_332 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_333 = (execute_SRC_USE_SUB_LESS ? _zz_334 : _zz_335); + assign _zz_334 = 32'h00000001; + assign _zz_335 = 32'h0; + assign _zz_336 = execute_INSTRUCTION[31 : 20]; + assign _zz_337 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_338 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_339 = {_zz_130,execute_INSTRUCTION[31 : 20]}; + assign _zz_340 = {{_zz_132,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_341 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; assign _zz_342 = execute_INSTRUCTION[31 : 20]; - assign _zz_343 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_344 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_345 = writeBack_MUL_LOW[31 : 0]; - assign _zz_346 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_347 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_348 = {5'd0, _zz_347}; - assign _zz_349 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_350 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_351 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_352 = {_zz_162,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_353 = _zz_354; - assign _zz_354 = _zz_355; - assign _zz_355 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_163) : _zz_163)} + _zz_357); - assign _zz_356 = memory_DivPlugin_div_needRevert; - assign _zz_357 = {32'd0, _zz_356}; - assign _zz_358 = _zz_165; - assign _zz_359 = {32'd0, _zz_358}; - assign _zz_360 = _zz_164; - assign _zz_361 = {31'd0, _zz_360}; - assign _zz_362 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_363 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_364 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_365 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_366 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_367 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_368 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_369 = (iBus_cmd_payload_address >>> 5); - assign _zz_370 = 1'b1; - assign _zz_371 = 1'b1; - assign _zz_372 = {_zz_63,_zz_62}; - assign _zz_373 = 32'h0000106f; - assign _zz_374 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_375 = 32'h00001073; - assign _zz_376 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_377 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_378 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_379) == 32'h00000003),{(_zz_380 == _zz_381),{_zz_382,{_zz_383,_zz_384}}}}}}; - assign _zz_379 = 32'h0000207f; - assign _zz_380 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_381 = 32'h00000003; - assign _zz_382 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_383 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_384 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_385) == 32'h00005013),{(_zz_386 == _zz_387),{_zz_388,{_zz_389,_zz_390}}}}}}; - assign _zz_385 = 32'hbc00707f; - assign _zz_386 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_387 = 32'h00001013; - assign _zz_388 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_389 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_390 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_391 = decode_INSTRUCTION[31]; - assign _zz_392 = decode_INSTRUCTION[31]; - assign _zz_393 = decode_INSTRUCTION[7]; - assign _zz_394 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_395 = 32'h02004020; - assign _zz_396 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_397 = (_zz_95 != 1'b0); - assign _zz_398 = (((decode_INSTRUCTION & _zz_400) == 32'h00000050) != 1'b0); - assign _zz_399 = {((_zz_401 == _zz_402) != 1'b0),{({_zz_403,_zz_404} != 2'b00),{(_zz_405 != _zz_406),{_zz_407,{_zz_408,_zz_409}}}}}; - assign _zz_400 = 32'h00203050; - assign _zz_401 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_402 = 32'h00000050; - assign _zz_403 = ((decode_INSTRUCTION & _zz_410) == 32'h00001050); - assign _zz_404 = ((decode_INSTRUCTION & _zz_411) == 32'h00002050); - assign _zz_405 = {_zz_94,(_zz_412 == _zz_413)}; - assign _zz_406 = 2'b00; - assign _zz_407 = ((_zz_414 == _zz_415) != 1'b0); - assign _zz_408 = ({_zz_416,_zz_417} != 2'b00); - assign _zz_409 = {(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}; - assign _zz_410 = 32'h00001050; - assign _zz_411 = 32'h00002050; - assign _zz_412 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_413 = 32'h00000004; - assign _zz_414 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_415 = 32'h00000040; - assign _zz_416 = ((decode_INSTRUCTION & _zz_423) == 32'h00005010); - assign _zz_417 = ((decode_INSTRUCTION & _zz_424) == 32'h00005020); - assign _zz_418 = {(_zz_425 == _zz_426),{_zz_427,_zz_428}}; - assign _zz_419 = 3'b000; - assign _zz_420 = ((_zz_429 == _zz_430) != 1'b0); - assign _zz_421 = (_zz_431 != 1'b0); - assign _zz_422 = {(_zz_432 != _zz_433),{_zz_434,{_zz_435,_zz_436}}}; - assign _zz_423 = 32'h00007034; - assign _zz_424 = 32'h02007064; - assign _zz_425 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_426 = 32'h40001010; - assign _zz_427 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_428 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_429 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_430 = 32'h00000024; - assign _zz_431 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_432 = ((decode_INSTRUCTION & _zz_437) == 32'h00002000); - assign _zz_433 = 1'b0; - assign _zz_434 = ({_zz_438,_zz_439} != 2'b00); - assign _zz_435 = (_zz_440 != 1'b0); - assign _zz_436 = {(_zz_441 != _zz_442),{_zz_443,{_zz_444,_zz_445}}}; - assign _zz_437 = 32'h00003000; - assign _zz_438 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_439 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_440 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_441 = {_zz_95,{_zz_446,_zz_447}}; - assign _zz_442 = 3'b000; - assign _zz_443 = ({_zz_448,{_zz_449,_zz_450}} != 5'h0); - assign _zz_444 = (_zz_451 != 1'b0); - assign _zz_445 = {(_zz_452 != _zz_453),{_zz_454,{_zz_455,_zz_456}}}; - assign _zz_446 = ((decode_INSTRUCTION & _zz_457) == 32'h00000020); - assign _zz_447 = ((decode_INSTRUCTION & _zz_458) == 32'h00000020); - assign _zz_448 = ((decode_INSTRUCTION & _zz_459) == 32'h00002040); - assign _zz_449 = (_zz_460 == _zz_461); - assign _zz_450 = {_zz_462,{_zz_463,_zz_464}}; - assign _zz_451 = ((decode_INSTRUCTION & _zz_465) == 32'h00000020); - assign _zz_452 = {_zz_466,{_zz_467,_zz_468}}; - assign _zz_453 = 6'h0; - assign _zz_454 = ({_zz_469,_zz_470} != 5'h0); - assign _zz_455 = (_zz_471 != _zz_472); - assign _zz_456 = {_zz_473,{_zz_474,_zz_475}}; - assign _zz_457 = 32'h00000034; - assign _zz_458 = 32'h00000064; - assign _zz_459 = 32'h00002040; - assign _zz_460 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_461 = 32'h00001040; - assign _zz_462 = ((decode_INSTRUCTION & _zz_476) == 32'h00000040); - assign _zz_463 = (_zz_477 == _zz_478); - assign _zz_464 = (_zz_479 == _zz_480); - assign _zz_465 = 32'h00000020; - assign _zz_466 = ((decode_INSTRUCTION & _zz_481) == 32'h00000008); - assign _zz_467 = (_zz_482 == _zz_483); - assign _zz_468 = {_zz_93,{_zz_484,_zz_485}}; - assign _zz_469 = _zz_93; - assign _zz_470 = {_zz_486,{_zz_487,_zz_488}}; - assign _zz_471 = {_zz_94,{_zz_489,_zz_490}}; - assign _zz_472 = 6'h0; - assign _zz_473 = ({_zz_491,_zz_492} != 2'b00); - assign _zz_474 = (_zz_493 != _zz_494); - assign _zz_475 = {_zz_495,{_zz_496,_zz_497}}; - assign _zz_476 = 32'h00000050; - assign _zz_477 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_478 = 32'h00000040; - assign _zz_479 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_480 = 32'h0; - assign _zz_481 = 32'h00000008; - assign _zz_482 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_483 = 32'h00000040; - assign _zz_484 = (_zz_498 == _zz_499); - assign _zz_485 = {_zz_500,_zz_501}; - assign _zz_486 = ((decode_INSTRUCTION & _zz_502) == 32'h00002010); - assign _zz_487 = (_zz_503 == _zz_504); - assign _zz_488 = {_zz_505,_zz_506}; - assign _zz_489 = (_zz_507 == _zz_508); - assign _zz_490 = {_zz_509,{_zz_510,_zz_511}}; - assign _zz_491 = _zz_93; - assign _zz_492 = (_zz_512 == _zz_513); - assign _zz_493 = {_zz_93,_zz_514}; - assign _zz_494 = 2'b00; - assign _zz_495 = (_zz_515 != 1'b0); - assign _zz_496 = (_zz_516 != _zz_517); - assign _zz_497 = {_zz_518,{_zz_519,_zz_520}}; - assign _zz_498 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_499 = 32'h00004020; - assign _zz_500 = ((decode_INSTRUCTION & _zz_521) == 32'h00000010); - assign _zz_501 = ((decode_INSTRUCTION & _zz_522) == 32'h00000020); - assign _zz_502 = 32'h00002030; - assign _zz_503 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_504 = 32'h00000010; - assign _zz_505 = ((decode_INSTRUCTION & _zz_523) == 32'h00002020); - assign _zz_506 = ((decode_INSTRUCTION & _zz_524) == 32'h00000020); - assign _zz_507 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_508 = 32'h00001010; - assign _zz_509 = ((decode_INSTRUCTION & _zz_525) == 32'h00002010); - assign _zz_510 = (_zz_526 == _zz_527); - assign _zz_511 = {_zz_528,_zz_529}; - assign _zz_512 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_513 = 32'h00000020; - assign _zz_514 = ((decode_INSTRUCTION & _zz_530) == 32'h0); - assign _zz_515 = ((decode_INSTRUCTION & _zz_531) == 32'h00004010); - assign _zz_516 = (_zz_532 == _zz_533); - assign _zz_517 = 1'b0; - assign _zz_518 = ({_zz_534,_zz_535} != 4'b0000); - assign _zz_519 = (_zz_536 != _zz_537); - assign _zz_520 = {_zz_538,{_zz_539,_zz_540}}; - assign _zz_521 = 32'h00000030; - assign _zz_522 = 32'h02000020; - assign _zz_523 = 32'h02002060; - assign _zz_524 = 32'h02003020; - assign _zz_525 = 32'h00002010; - assign _zz_526 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_527 = 32'h00000010; - assign _zz_528 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_529 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_530 = 32'h00000020; - assign _zz_531 = 32'h00004014; - assign _zz_532 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_533 = 32'h00002010; - assign _zz_534 = ((decode_INSTRUCTION & _zz_541) == 32'h0); - assign _zz_535 = {(_zz_542 == _zz_543),{_zz_544,_zz_545}}; - assign _zz_536 = ((decode_INSTRUCTION & _zz_546) == 32'h0); - assign _zz_537 = 1'b0; - assign _zz_538 = ({_zz_547,{_zz_548,_zz_549}} != 3'b000); - assign _zz_539 = ({_zz_550,_zz_551} != 2'b00); - assign _zz_540 = {(_zz_552 != _zz_553),(_zz_554 != _zz_555)}; - assign _zz_541 = 32'h00000044; - assign _zz_542 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_543 = 32'h0; - assign _zz_544 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_545 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_546 = 32'h00000058; - assign _zz_547 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_548 = ((decode_INSTRUCTION & _zz_556) == 32'h00002010); - assign _zz_549 = ((decode_INSTRUCTION & _zz_557) == 32'h40000030); - assign _zz_550 = ((decode_INSTRUCTION & _zz_558) == 32'h00000004); - assign _zz_551 = _zz_92; - assign _zz_552 = {(_zz_559 == _zz_560),_zz_92}; - assign _zz_553 = 2'b00; - assign _zz_554 = ((decode_INSTRUCTION & _zz_561) == 32'h00001004); - assign _zz_555 = 1'b0; - assign _zz_556 = 32'h00002014; - assign _zz_557 = 32'h40000034; - assign _zz_558 = 32'h00000014; - assign _zz_559 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_560 = 32'h00000004; - assign _zz_561 = 32'h00005054; - assign _zz_562 = execute_INSTRUCTION[31]; - assign _zz_563 = execute_INSTRUCTION[31]; - assign _zz_564 = execute_INSTRUCTION[7]; - assign _zz_565 = 32'h0; + assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_345 = 3'b100; + assign _zz_346 = (_zz_145 & (~ _zz_347)); + assign _zz_347 = (_zz_145 - 2'b01); + assign _zz_348 = (_zz_147 & (~ _zz_349)); + assign _zz_349 = (_zz_147 - 2'b01); + assign _zz_350 = execute_INSTRUCTION[14 : 12]; + assign _zz_351 = execute_INSTRUCTION[31 : 20]; + assign _zz_352 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_353 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_354 = writeBack_MUL_LOW[31 : 0]; + assign _zz_355 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_356 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_357 = {5'd0, _zz_356}; + assign _zz_358 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_359 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_360 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_361 = {_zz_168,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_362 = _zz_363; + assign _zz_363 = _zz_364; + assign _zz_364 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_169) : _zz_169)} + _zz_366); + assign _zz_365 = memory_DivPlugin_div_needRevert; + assign _zz_366 = {32'd0, _zz_365}; + assign _zz_367 = _zz_171; + assign _zz_368 = {32'd0, _zz_367}; + assign _zz_369 = _zz_170; + assign _zz_370 = {31'd0, _zz_369}; + assign _zz_371 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_372 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_373 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_374 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_375 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_376 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_377 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_378 = (iBus_cmd_payload_address >>> 5); + assign _zz_379 = 1'b1; + assign _zz_380 = 1'b1; + assign _zz_381 = {_zz_63,_zz_62}; + assign _zz_382 = 32'h0000106f; + assign _zz_383 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_384 = 32'h00001073; + assign _zz_385 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_386 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_387 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}; + assign _zz_388 = 32'h0000207f; + assign _zz_389 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_390 = 32'h00000003; + assign _zz_391 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_392 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_393 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_394) == 32'h00005013),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; + assign _zz_394 = 32'hbc00707f; + assign _zz_395 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_396 = 32'h00001013; + assign _zz_397 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_398 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_399 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_400 = decode_INSTRUCTION[31]; + assign _zz_401 = decode_INSTRUCTION[31]; + assign _zz_402 = decode_INSTRUCTION[7]; + assign _zz_403 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_404 = 32'h02004020; + assign _zz_405 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_406 = (_zz_95 != 1'b0); + assign _zz_407 = (((decode_INSTRUCTION & _zz_409) == 32'h00000050) != 1'b0); + assign _zz_408 = {((_zz_410 == _zz_411) != 1'b0),{({_zz_412,_zz_413} != 2'b00),{(_zz_414 != _zz_415),{_zz_416,{_zz_417,_zz_418}}}}}; + assign _zz_409 = 32'h00203050; + assign _zz_410 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_411 = 32'h00000050; + assign _zz_412 = ((decode_INSTRUCTION & _zz_419) == 32'h00001050); + assign _zz_413 = ((decode_INSTRUCTION & _zz_420) == 32'h00002050); + assign _zz_414 = {_zz_94,(_zz_421 == _zz_422)}; + assign _zz_415 = 2'b00; + assign _zz_416 = ((_zz_423 == _zz_424) != 1'b0); + assign _zz_417 = ({_zz_425,_zz_426} != 2'b00); + assign _zz_418 = {(_zz_427 != _zz_428),{_zz_429,{_zz_430,_zz_431}}}; + assign _zz_419 = 32'h00001050; + assign _zz_420 = 32'h00002050; + assign _zz_421 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_422 = 32'h00000004; + assign _zz_423 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_424 = 32'h00000040; + assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00005010); + assign _zz_426 = ((decode_INSTRUCTION & _zz_433) == 32'h00005020); + assign _zz_427 = {(_zz_434 == _zz_435),{_zz_436,_zz_437}}; + assign _zz_428 = 3'b000; + assign _zz_429 = ((_zz_438 == _zz_439) != 1'b0); + assign _zz_430 = (_zz_440 != 1'b0); + assign _zz_431 = {(_zz_441 != _zz_442),{_zz_443,{_zz_444,_zz_445}}}; + assign _zz_432 = 32'h00007034; + assign _zz_433 = 32'h02007064; + assign _zz_434 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_435 = 32'h40001010; + assign _zz_436 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_437 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_438 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_439 = 32'h00000024; + assign _zz_440 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_441 = ((decode_INSTRUCTION & _zz_446) == 32'h00002000); + assign _zz_442 = 1'b0; + assign _zz_443 = ({_zz_447,_zz_448} != 2'b00); + assign _zz_444 = (_zz_449 != 1'b0); + assign _zz_445 = {(_zz_450 != _zz_451),{_zz_452,{_zz_453,_zz_454}}}; + assign _zz_446 = 32'h00003000; + assign _zz_447 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_448 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_449 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_450 = {_zz_95,{_zz_455,_zz_456}}; + assign _zz_451 = 3'b000; + assign _zz_452 = ({_zz_457,{_zz_458,_zz_459}} != 5'h0); + assign _zz_453 = (_zz_460 != 1'b0); + assign _zz_454 = {(_zz_461 != _zz_462),{_zz_463,{_zz_464,_zz_465}}}; + assign _zz_455 = ((decode_INSTRUCTION & _zz_466) == 32'h00000020); + assign _zz_456 = ((decode_INSTRUCTION & _zz_467) == 32'h00000020); + assign _zz_457 = ((decode_INSTRUCTION & _zz_468) == 32'h00002040); + assign _zz_458 = (_zz_469 == _zz_470); + assign _zz_459 = {_zz_471,{_zz_472,_zz_473}}; + assign _zz_460 = ((decode_INSTRUCTION & _zz_474) == 32'h00000020); + assign _zz_461 = {_zz_475,{_zz_476,_zz_477}}; + assign _zz_462 = 6'h0; + assign _zz_463 = ({_zz_478,_zz_479} != 5'h0); + assign _zz_464 = (_zz_480 != _zz_481); + assign _zz_465 = {_zz_482,{_zz_483,_zz_484}}; + assign _zz_466 = 32'h00000034; + assign _zz_467 = 32'h00000064; + assign _zz_468 = 32'h00002040; + assign _zz_469 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_470 = 32'h00001040; + assign _zz_471 = ((decode_INSTRUCTION & _zz_485) == 32'h00000040); + assign _zz_472 = (_zz_486 == _zz_487); + assign _zz_473 = (_zz_488 == _zz_489); + assign _zz_474 = 32'h00000020; + assign _zz_475 = ((decode_INSTRUCTION & _zz_490) == 32'h00000008); + assign _zz_476 = (_zz_491 == _zz_492); + assign _zz_477 = {_zz_93,{_zz_493,_zz_494}}; + assign _zz_478 = _zz_93; + assign _zz_479 = {_zz_495,{_zz_496,_zz_497}}; + assign _zz_480 = {_zz_94,{_zz_498,_zz_499}}; + assign _zz_481 = 6'h0; + assign _zz_482 = ({_zz_500,_zz_501} != 2'b00); + assign _zz_483 = (_zz_502 != _zz_503); + assign _zz_484 = {_zz_504,{_zz_505,_zz_506}}; + assign _zz_485 = 32'h00000050; + assign _zz_486 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_487 = 32'h00000040; + assign _zz_488 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_489 = 32'h0; + assign _zz_490 = 32'h00000008; + assign _zz_491 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_492 = 32'h00000040; + assign _zz_493 = (_zz_507 == _zz_508); + assign _zz_494 = {_zz_509,_zz_510}; + assign _zz_495 = ((decode_INSTRUCTION & _zz_511) == 32'h00002010); + assign _zz_496 = (_zz_512 == _zz_513); + assign _zz_497 = {_zz_514,_zz_515}; + assign _zz_498 = (_zz_516 == _zz_517); + assign _zz_499 = {_zz_518,{_zz_519,_zz_520}}; + assign _zz_500 = _zz_93; + assign _zz_501 = (_zz_521 == _zz_522); + assign _zz_502 = {_zz_93,_zz_523}; + assign _zz_503 = 2'b00; + assign _zz_504 = (_zz_524 != 1'b0); + assign _zz_505 = (_zz_525 != _zz_526); + assign _zz_506 = {_zz_527,{_zz_528,_zz_529}}; + assign _zz_507 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_508 = 32'h00004020; + assign _zz_509 = ((decode_INSTRUCTION & _zz_530) == 32'h00000010); + assign _zz_510 = ((decode_INSTRUCTION & _zz_531) == 32'h00000020); + assign _zz_511 = 32'h00002030; + assign _zz_512 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_513 = 32'h00000010; + assign _zz_514 = ((decode_INSTRUCTION & _zz_532) == 32'h00002020); + assign _zz_515 = ((decode_INSTRUCTION & _zz_533) == 32'h00000020); + assign _zz_516 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_517 = 32'h00001010; + assign _zz_518 = ((decode_INSTRUCTION & _zz_534) == 32'h00002010); + assign _zz_519 = (_zz_535 == _zz_536); + assign _zz_520 = {_zz_537,_zz_538}; + assign _zz_521 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_522 = 32'h00000020; + assign _zz_523 = ((decode_INSTRUCTION & _zz_539) == 32'h0); + assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00004010); + assign _zz_525 = (_zz_541 == _zz_542); + assign _zz_526 = 1'b0; + assign _zz_527 = ({_zz_543,_zz_544} != 4'b0000); + assign _zz_528 = (_zz_545 != _zz_546); + assign _zz_529 = {_zz_547,{_zz_548,_zz_549}}; + assign _zz_530 = 32'h00000030; + assign _zz_531 = 32'h02000020; + assign _zz_532 = 32'h02002060; + assign _zz_533 = 32'h02003020; + assign _zz_534 = 32'h00002010; + assign _zz_535 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_536 = 32'h00000010; + assign _zz_537 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_538 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_539 = 32'h00000020; + assign _zz_540 = 32'h00004014; + assign _zz_541 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_542 = 32'h00002010; + assign _zz_543 = ((decode_INSTRUCTION & _zz_550) == 32'h0); + assign _zz_544 = {(_zz_551 == _zz_552),{_zz_553,_zz_554}}; + assign _zz_545 = ((decode_INSTRUCTION & _zz_555) == 32'h0); + assign _zz_546 = 1'b0; + assign _zz_547 = ({_zz_556,{_zz_557,_zz_558}} != 3'b000); + assign _zz_548 = ({_zz_559,_zz_560} != 2'b00); + assign _zz_549 = {(_zz_561 != _zz_562),(_zz_563 != _zz_564)}; + assign _zz_550 = 32'h00000044; + assign _zz_551 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_552 = 32'h0; + assign _zz_553 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_554 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_555 = 32'h00000058; + assign _zz_556 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_557 = ((decode_INSTRUCTION & _zz_565) == 32'h00002010); + assign _zz_558 = ((decode_INSTRUCTION & _zz_566) == 32'h40000030); + assign _zz_559 = ((decode_INSTRUCTION & _zz_567) == 32'h00000004); + assign _zz_560 = _zz_92; + assign _zz_561 = {(_zz_568 == _zz_569),_zz_92}; + assign _zz_562 = 2'b00; + assign _zz_563 = ((decode_INSTRUCTION & _zz_570) == 32'h00001004); + assign _zz_564 = 1'b0; + assign _zz_565 = 32'h00002014; + assign _zz_566 = 32'h40000034; + assign _zz_567 = 32'h00000014; + assign _zz_568 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_569 = 32'h00000004; + assign _zz_570 = 32'h00005054; + assign _zz_571 = execute_INSTRUCTION[31]; + assign _zz_572 = execute_INSTRUCTION[31]; + assign _zz_573 = execute_INSTRUCTION[7]; + assign _zz_574 = 32'h0; always @ (posedge clk) begin - if(_zz_370) begin - _zz_232 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_379) begin + _zz_241 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_371) begin - _zz_233 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_380) begin + _zz_242 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1704,13 +1719,13 @@ module VexRiscv_inner ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_204 ), //i - .io_cpu_prefetch_isValid (_zz_205 ), //i + .io_flush (_zz_213 ), //i + .io_cpu_prefetch_isValid (_zz_214 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_206 ), //i - .io_cpu_fetch_isStuck (_zz_207 ), //i - .io_cpu_fetch_isRemoved (_zz_208 ), //i + .io_cpu_fetch_isValid (_zz_215 ), //i + .io_cpu_fetch_isStuck (_zz_216 ), //i + .io_cpu_fetch_isRemoved (_zz_217 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1722,8 +1737,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_209 ), //i - .io_cpu_decode_isStuck (_zz_210 ), //i + .io_cpu_decode_isValid (_zz_218 ), //i + .io_cpu_decode_isStuck (_zz_219 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1731,8 +1746,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_211 ), //i - .io_cpu_fill_valid (_zz_212 ), //i + .io_cpu_decode_isUser (_zz_220 ), //i + .io_cpu_fill_valid (_zz_221 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1745,50 +1760,50 @@ module VexRiscv_inner ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_213 ), //i - .io_cpu_execute_address (_zz_214[31:0] ), //i + .io_cpu_execute_isValid (_zz_222 ), //i + .io_cpu_execute_address (_zz_223[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_86[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_memory_isValid (_zz_215 ), //i + .io_cpu_memory_isValid (_zz_224 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_216[31:0] ), //i + .io_cpu_memory_address (_zz_225[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_217 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_226 ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_218 ), //i + .io_cpu_writeBack_isValid (_zz_227 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_219 ), //i + .io_cpu_writeBack_isUser (_zz_228 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_220[31:0] ), //i + .io_cpu_writeBack_address (_zz_229[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_221 ), //i - .io_cpu_writeBack_fence_SR (_zz_222 ), //i - .io_cpu_writeBack_fence_SO (_zz_223 ), //i - .io_cpu_writeBack_fence_SI (_zz_224 ), //i - .io_cpu_writeBack_fence_PW (_zz_225 ), //i - .io_cpu_writeBack_fence_PR (_zz_226 ), //i - .io_cpu_writeBack_fence_PO (_zz_227 ), //i - .io_cpu_writeBack_fence_PI (_zz_228 ), //i - .io_cpu_writeBack_fence_FM (_zz_229[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_230 ), //i + .io_cpu_writeBack_fence_SR (_zz_231 ), //i + .io_cpu_writeBack_fence_SO (_zz_232 ), //i + .io_cpu_writeBack_fence_SI (_zz_233 ), //i + .io_cpu_writeBack_fence_PW (_zz_234 ), //i + .io_cpu_writeBack_fence_PR (_zz_235 ), //i + .io_cpu_writeBack_fence_PO (_zz_236 ), //i + .io_cpu_writeBack_fence_PI (_zz_237 ), //i + .io_cpu_writeBack_fence_FM (_zz_238[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_230 ), //i + .io_cpu_flush_valid (_zz_239 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_231 ), //i + .io_mem_cmd_ready (_zz_240 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1804,18 +1819,18 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_372) + case(_zz_381) 2'b00 : begin - _zz_234 = DBusCachedPlugin_redoBranch_payload; + _zz_243 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_234 = CsrPlugin_jumpInterface_payload; + _zz_243 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_234 = BranchPlugin_jumpInterface_payload; + _zz_243 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_234 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_243 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2570,7 +2585,7 @@ module VexRiscv_inner ( end `endif - assign memory_MUL_LOW = ($signed(_zz_272) + $signed(_zz_280)); + assign memory_MUL_LOW = ($signed(_zz_281) + $signed(_zz_289)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2579,41 +2594,41 @@ module VexRiscv_inner ( assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_282; + assign execute_SHIFT_RIGHT = _zz_291; assign execute_REGFILE_WRITE_DATA = _zz_106; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_214[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_223[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_284[0]; - assign decode_IS_RS1_SIGNED = _zz_285[0]; - assign decode_IS_DIV = _zz_286[0]; + assign decode_IS_RS2_SIGNED = _zz_293[0]; + assign decode_IS_RS1_SIGNED = _zz_294[0]; + assign decode_IS_DIV = _zz_295[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_287[0]; + assign decode_IS_MUL = _zz_296[0]; assign decode_CfuPlugin_CFU_ENCODING = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_288[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_297[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_289[0]; + assign decode_IS_CSR = _zz_298[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_290[0]; - assign decode_MEMORY_MANAGMENT = _zz_291[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_299[0]; + assign decode_MEMORY_MANAGMENT = _zz_300[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_292[0]; + assign decode_MEMORY_WR = _zz_301[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_293[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_294[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_302[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_303[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2652,11 +2667,11 @@ module VexRiscv_inner ( assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_COND_RESULT = _zz_128; assign execute_BRANCH_CTRL = _zz_34; - assign decode_RS2_USE = _zz_295[0]; - assign decode_RS1_USE = _zz_296[0]; + assign decode_RS2_USE = _zz_304[0]; + assign decode_RS1_USE = _zz_305[0]; always @ (*) begin _zz_35 = execute_REGFILE_WRITE_DATA; - if(_zz_235)begin + if(_zz_244)begin _zz_35 = execute_CsrPlugin_readData; end end @@ -2674,21 +2689,21 @@ module VexRiscv_inner ( decode_RS2 = _zz_119; end end - if(_zz_236)begin - if(_zz_237)begin + if(_zz_245)begin + if(_zz_246)begin if(_zz_121)begin decode_RS2 = _zz_55; end end end - if(_zz_238)begin + if(_zz_247)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_123)begin decode_RS2 = _zz_36; end end end - if(_zz_239)begin + if(_zz_248)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_125)begin decode_RS2 = _zz_35; @@ -2704,21 +2719,21 @@ module VexRiscv_inner ( decode_RS1 = _zz_119; end end - if(_zz_236)begin - if(_zz_237)begin + if(_zz_245)begin + if(_zz_246)begin if(_zz_120)begin decode_RS1 = _zz_55; end end end - if(_zz_238)begin + if(_zz_247)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_122)begin decode_RS1 = _zz_36; end end end - if(_zz_239)begin + if(_zz_248)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_124)begin decode_RS1 = _zz_35; @@ -2745,7 +2760,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_36 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_240)begin + if(_zz_249)begin _zz_36 = memory_DivPlugin_div_result; end end @@ -2758,8 +2773,8 @@ module VexRiscv_inner ( assign _zz_39 = execute_PC; assign execute_SRC2_CTRL = _zz_40; assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_297[0]; - assign decode_SRC_ADD_ZERO = _zz_298[0]; + assign decode_SRC_USE_SUB_LESS = _zz_306[0]; + assign decode_SRC_ADD_ZERO = _zz_307[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_42; @@ -2777,25 +2792,25 @@ module VexRiscv_inner ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_299[0]; + decode_REGFILE_WRITE_VALID = _zz_308[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_373) == 32'h00000003),{(_zz_374 == _zz_375),{_zz_376,{_zz_377,_zz_378}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_382) == 32'h00000003),{(_zz_383 == _zz_384),{_zz_385,{_zz_386,_zz_387}}}}}}} != 22'h0); always @ (*) begin _zz_55 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_55 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_271) + case(_zz_280) 2'b00 : begin - _zz_55 = _zz_345; + _zz_55 = _zz_354; end default : begin - _zz_55 = _zz_346; + _zz_55 = _zz_355; end endcase end @@ -2814,32 +2829,32 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_300[0]; - assign decode_FLUSH_ALL = _zz_301[0]; + assign decode_MEMORY_ENABLE = _zz_309[0]; + assign decode_FLUSH_ALL = _zz_310[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_241)begin + if(_zz_250)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_242)begin + if(_zz_251)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_243)begin + if(_zz_252)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_244)begin + if(_zz_253)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2885,7 +2900,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_245)begin + if(_zz_254)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2899,25 +2914,25 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_245)begin + if(_zz_254)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_230 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_239 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end if(((dataCache_1_io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_246)begin + if(_zz_255)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_235)begin + if(_zz_244)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2953,7 +2968,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_240)begin + if(_zz_249)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2963,7 +2978,7 @@ module VexRiscv_inner ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_247)begin + if(_zz_256)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2977,7 +2992,7 @@ module VexRiscv_inner ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_247)begin + if(_zz_256)begin memory_arbitration_flushNext = 1'b1; end end @@ -3015,10 +3030,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_248)begin + if(_zz_257)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_249)begin + if(_zz_258)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3032,10 +3047,10 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_248)begin + if(_zz_257)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_249)begin + if(_zz_258)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3049,7 +3064,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_246)begin + if(_zz_255)begin CsrPlugin_inWfi = 1'b1; end end @@ -3057,21 +3072,21 @@ module VexRiscv_inner ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_248)begin + if(_zz_257)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_249)begin + if(_zz_258)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_248)begin + if(_zz_257)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_249)begin - case(_zz_250) + if(_zz_258)begin + case(_zz_259) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3087,11 +3102,11 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_59 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_60 = (_zz_59 & (~ _zz_302)); + assign _zz_60 = (_zz_59 & (~ _zz_311)); assign _zz_61 = _zz_60[3]; assign _zz_62 = (_zz_60[1] || _zz_61); assign _zz_63 = (_zz_60[2] || _zz_61); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_234; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_243; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3111,7 +3126,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_304); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_313); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3202,7 +3217,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_73 = _zz_305[11]; + assign _zz_73 = _zz_314[11]; always @ (*) begin _zz_74[18] = _zz_73; _zz_74[17] = _zz_73; @@ -3226,13 +3241,13 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_306[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_315[31])); if(_zz_79)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_75 = _zz_307[19]; + assign _zz_75 = _zz_316[19]; always @ (*) begin _zz_76[10] = _zz_75; _zz_76[9] = _zz_75; @@ -3247,7 +3262,7 @@ module VexRiscv_inner ( _zz_76[0] = _zz_75; end - assign _zz_77 = _zz_308[11]; + assign _zz_77 = _zz_317[11]; always @ (*) begin _zz_78[18] = _zz_77; _zz_78[17] = _zz_77; @@ -3273,16 +3288,16 @@ module VexRiscv_inner ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_79 = _zz_309[1]; + _zz_79 = _zz_318[1]; end default : begin - _zz_79 = _zz_310[1]; + _zz_79 = _zz_319[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_80 = _zz_311[19]; + assign _zz_80 = _zz_320[19]; always @ (*) begin _zz_81[10] = _zz_80; _zz_81[9] = _zz_80; @@ -3297,7 +3312,7 @@ module VexRiscv_inner ( _zz_81[0] = _zz_80; end - assign _zz_82 = _zz_312[11]; + assign _zz_82 = _zz_321[11]; always @ (*) begin _zz_83[18] = _zz_82; _zz_83[17] = _zz_82; @@ -3320,7 +3335,7 @@ module VexRiscv_inner ( _zz_83[0] = _zz_82; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_81,{{{_zz_391,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_83,{{{_zz_392,_zz_393},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_81,{{{_zz_400,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_83,{{{_zz_401,_zz_402},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3329,52 +3344,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_205 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_206 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_207 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_206; + assign _zz_214 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_215 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_216 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_215; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_209 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_210 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_211 = (CsrPlugin_privilege == 2'b00); + assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_219 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_220 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_244)begin + if(_zz_253)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_242)begin + if(_zz_251)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_212 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_242)begin - _zz_212 = 1'b1; + _zz_221 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_251)begin + _zz_221 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_243)begin + if(_zz_252)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_241)begin + if(_zz_250)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_243)begin + if(_zz_252)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_241)begin + if(_zz_250)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3384,9 +3399,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_204 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_213 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_231 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_240 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3413,8 +3428,8 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_213 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_214 = execute_SRC_ADD; + assign _zz_222 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_223 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3429,27 +3444,27 @@ module VexRiscv_inner ( endcase end - assign _zz_230 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_215 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_216 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_215; + assign _zz_239 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_224 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_225 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_224; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_216; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_225; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_217 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_226 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_217 = 1'b1; + _zz_226 = 1'b1; end end - assign _zz_218 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_219 = (CsrPlugin_privilege == 2'b00); - assign _zz_220 = writeBack_REGFILE_WRITE_DATA; + assign _zz_227 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_228 = (CsrPlugin_privilege == 2'b00); + assign _zz_229 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_251)begin + if(_zz_260)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3459,7 +3474,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_251)begin + if(_zz_260)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3478,12 +3493,12 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_251)begin + if(_zz_260)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_313}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_322}; end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_314}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_323}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); @@ -3559,7 +3574,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_269) + case(_zz_278) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_88; end @@ -3593,7 +3608,7 @@ module VexRiscv_inner ( assign _zz_94 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_95 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); assign _zz_96 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_91 = {(_zz_96 != 1'b0),{(_zz_96 != 1'b0),{((_zz_394 == _zz_395) != 1'b0),{(_zz_396 != 1'b0),{1'b0,{_zz_397,{_zz_398,_zz_399}}}}}}}; + assign _zz_91 = {(_zz_96 != 1'b0),{(_zz_96 != 1'b0),{((_zz_403 == _zz_404) != 1'b0),{(_zz_405 != 1'b0),{1'b0,{_zz_406,{_zz_407,_zz_408}}}}}}}; assign _zz_97 = _zz_91[2 : 1]; assign _zz_54 = _zz_97; assign _zz_98 = _zz_91[7 : 6]; @@ -3615,8 +3630,8 @@ module VexRiscv_inner ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_232; - assign decode_RegFilePlugin_rs2Data = _zz_233; + assign decode_RegFilePlugin_rs1Data = _zz_241; + assign decode_RegFilePlugin_rs2Data = _zz_242; always @ (*) begin lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); if(_zz_105)begin @@ -3646,7 +3661,7 @@ module VexRiscv_inner ( _zz_106 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_106 = {31'd0, _zz_315}; + _zz_106 = {31'd0, _zz_324}; end default : begin _zz_106 = execute_SRC_ADD_SUB; @@ -3660,18 +3675,18 @@ module VexRiscv_inner ( _zz_107 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_107 = {29'd0, _zz_316}; + _zz_107 = {29'd0, _zz_325}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_107 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_107 = {27'd0, _zz_317}; + _zz_107 = {27'd0, _zz_326}; end endcase end - assign _zz_108 = _zz_318[11]; + assign _zz_108 = _zz_327[11]; always @ (*) begin _zz_109[19] = _zz_108; _zz_109[18] = _zz_108; @@ -3695,7 +3710,7 @@ module VexRiscv_inner ( _zz_109[0] = _zz_108; end - assign _zz_110 = _zz_319[11]; + assign _zz_110 = _zz_328[11]; always @ (*) begin _zz_111[19] = _zz_110; _zz_111[18] = _zz_110; @@ -3737,7 +3752,7 @@ module VexRiscv_inner ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_320; + execute_SrcPlugin_addSub = _zz_329; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3818,22 +3833,22 @@ module VexRiscv_inner ( always @ (*) begin _zz_115 = 1'b0; - if(_zz_252)begin - if(_zz_253)begin + if(_zz_261)begin + if(_zz_262)begin if(_zz_120)begin _zz_115 = 1'b1; end end end - if(_zz_254)begin - if(_zz_255)begin + if(_zz_263)begin + if(_zz_264)begin if(_zz_122)begin _zz_115 = 1'b1; end end end - if(_zz_256)begin - if(_zz_257)begin + if(_zz_265)begin + if(_zz_266)begin if(_zz_124)begin _zz_115 = 1'b1; end @@ -3846,22 +3861,22 @@ module VexRiscv_inner ( always @ (*) begin _zz_116 = 1'b0; - if(_zz_252)begin - if(_zz_253)begin + if(_zz_261)begin + if(_zz_262)begin if(_zz_121)begin _zz_116 = 1'b1; end end end - if(_zz_254)begin - if(_zz_255)begin + if(_zz_263)begin + if(_zz_264)begin if(_zz_123)begin _zz_116 = 1'b1; end end end - if(_zz_256)begin - if(_zz_257)begin + if(_zz_265)begin + if(_zz_266)begin if(_zz_125)begin _zz_116 = 1'b1; end @@ -3909,7 +3924,7 @@ module VexRiscv_inner ( endcase end - assign _zz_129 = _zz_327[11]; + assign _zz_129 = _zz_336[11]; always @ (*) begin _zz_130[19] = _zz_129; _zz_130[18] = _zz_129; @@ -3933,7 +3948,7 @@ module VexRiscv_inner ( _zz_130[0] = _zz_129; end - assign _zz_131 = _zz_328[19]; + assign _zz_131 = _zz_337[19]; always @ (*) begin _zz_132[10] = _zz_131; _zz_132[9] = _zz_131; @@ -3948,7 +3963,7 @@ module VexRiscv_inner ( _zz_132[0] = _zz_131; end - assign _zz_133 = _zz_329[11]; + assign _zz_133 = _zz_338[11]; always @ (*) begin _zz_134[18] = _zz_133; _zz_134[17] = _zz_133; @@ -3974,13 +3989,13 @@ module VexRiscv_inner ( always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_135 = (_zz_330[1] ^ execute_RS1[1]); + _zz_135 = (_zz_339[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_135 = _zz_331[1]; + _zz_135 = _zz_340[1]; end default : begin - _zz_135 = _zz_332[1]; + _zz_135 = _zz_341[1]; end endcase end @@ -3997,7 +4012,7 @@ module VexRiscv_inner ( endcase end - assign _zz_136 = _zz_333[11]; + assign _zz_136 = _zz_342[11]; always @ (*) begin _zz_137[19] = _zz_136; _zz_137[18] = _zz_136; @@ -4027,15 +4042,15 @@ module VexRiscv_inner ( execute_BranchPlugin_branch_src2 = {_zz_137,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_139,{{{_zz_562,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_141,{{{_zz_563,_zz_564},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_139,{{{_zz_571,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_141,{{{_zz_572,_zz_573},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_336}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_345}; end end endcase end - assign _zz_138 = _zz_334[19]; + assign _zz_138 = _zz_343[19]; always @ (*) begin _zz_139[10] = _zz_138; _zz_139[9] = _zz_138; @@ -4050,7 +4065,7 @@ module VexRiscv_inner ( _zz_139[0] = _zz_138; end - assign _zz_140 = _zz_335[11]; + assign _zz_140 = _zz_344[11]; always @ (*) begin _zz_141[18] = _zz_140; _zz_141[17] = _zz_140; @@ -4093,12 +4108,12 @@ module VexRiscv_inner ( assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); assign _zz_145 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_146 = _zz_337[0]; + assign _zz_146 = _zz_346[0]; assign _zz_147 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_148 = _zz_339[0]; + assign _zz_148 = _zz_348[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_245)begin + if(_zz_254)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4118,7 +4133,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_247)begin + if(_zz_256)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4307,6 +4322,30 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end + if(execute_CsrPlugin_csr_2830)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end if(execute_CsrPlugin_csr_3008)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4334,20 +4373,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_258)begin + if(_zz_267)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_259)begin + if(_zz_268)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_258)begin + if(_zz_267)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_259)begin + if(_zz_268)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4366,7 +4405,7 @@ module VexRiscv_inner ( assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_270) + case(_zz_279) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4379,45 +4418,45 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_341; + assign execute_CfuPlugin_functionsIds_0 = _zz_350; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_159 = _zz_342[11]; - always @ (*) begin - _zz_160[19] = _zz_159; - _zz_160[18] = _zz_159; - _zz_160[17] = _zz_159; - _zz_160[16] = _zz_159; - _zz_160[15] = _zz_159; - _zz_160[14] = _zz_159; - _zz_160[13] = _zz_159; - _zz_160[12] = _zz_159; - _zz_160[11] = _zz_159; - _zz_160[10] = _zz_159; - _zz_160[9] = _zz_159; - _zz_160[8] = _zz_159; - _zz_160[7] = _zz_159; - _zz_160[6] = _zz_159; - _zz_160[5] = _zz_159; - _zz_160[4] = _zz_159; - _zz_160[3] = _zz_159; - _zz_160[2] = _zz_159; - _zz_160[1] = _zz_159; - _zz_160[0] = _zz_159; + assign _zz_165 = _zz_351[11]; + always @ (*) begin + _zz_166[19] = _zz_165; + _zz_166[18] = _zz_165; + _zz_166[17] = _zz_165; + _zz_166[16] = _zz_165; + _zz_166[15] = _zz_165; + _zz_166[14] = _zz_165; + _zz_166[13] = _zz_165; + _zz_166[12] = _zz_165; + _zz_166[11] = _zz_165; + _zz_166[10] = _zz_165; + _zz_166[9] = _zz_165; + _zz_166[8] = _zz_165; + _zz_166[7] = _zz_165; + _zz_166[6] = _zz_165; + _zz_166[5] = _zz_165; + _zz_166[4] = _zz_165; + _zz_166[3] = _zz_165; + _zz_166[2] = _zz_165; + _zz_166[1] = _zz_165; + _zz_166[0] = _zz_165; end always @ (*) begin case(execute_CfuPlugin_CFU_ENCODING) `Input2Kind_defaultEncoding_RS : begin - _zz_161 = execute_RS2; + _zz_167 = execute_RS2; end default : begin - _zz_161 = {_zz_160,execute_INSTRUCTION[31 : 20]}; + _zz_167 = {_zz_166,execute_INSTRUCTION[31 : 20]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_161; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_167; assign CfuPlugin_bus_rsp_ready = ((1'b1 && (! memory_CfuPlugin_rsp_valid)) || memory_CfuPlugin_rsp_ready); assign memory_CfuPlugin_rsp_valid = CfuPlugin_bus_rsp_m2sPipe_rValid; assign memory_CfuPlugin_rsp_payload_response_ok = CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; @@ -4443,7 +4482,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_260) + case(_zz_269) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4457,7 +4496,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_260) + case(_zz_269) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4476,12 +4515,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_343) + $signed(_zz_344)); + assign writeBack_MulPlugin_result = ($signed(_zz_352) + $signed(_zz_353)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_240)begin - if(_zz_261)begin + if(_zz_249)begin + if(_zz_270)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4489,7 +4528,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_262)begin + if(_zz_271)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4500,28 +4539,28 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_348); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_357); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_162 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_162[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_349); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_350 : _zz_351); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_352[31:0]; - assign _zz_163 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_164 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_165 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_168 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_168[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_358); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_359 : _zz_360); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_361[31:0]; + assign _zz_169 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_170 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_171 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_166[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_166[31 : 0] = execute_RS1; + _zz_172[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_172[31 : 0] = execute_RS1; end - assign _zz_168 = (_zz_167 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_168 != 32'h0); + assign _zz_174 = (_zz_173 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_174 != 32'h0); assign _zz_29 = decode_SRC1_CTRL; assign _zz_27 = _zz_54; assign _zz_41 = decode_to_execute_SRC1_CTRL; @@ -4573,237 +4612,258 @@ module VexRiscv_inner ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_169 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_169[12 : 0] = 13'h1000; - _zz_169[25 : 20] = 6'h20; + _zz_175[12 : 0] = 13'h1000; + _zz_175[25 : 20] = 6'h20; end end always @ (*) begin - _zz_170 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_170[3 : 0] = 4'b1011; + _zz_176[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_171[4 : 0] = 5'h16; + _zz_177[4 : 0] = 5'h16; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_172[5 : 0] = 6'h21; + _zz_178[5 : 0] = 6'h21; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_173[31 : 30] = CsrPlugin_misa_base; - _zz_173[25 : 0] = CsrPlugin_misa_extensions; + _zz_179[31 : 30] = CsrPlugin_misa_base; + _zz_179[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_174[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_174[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_174[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_180[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_180[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_180[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_175[11 : 11] = CsrPlugin_mip_MEIP; - _zz_175[7 : 7] = CsrPlugin_mip_MTIP; - _zz_175[3 : 3] = CsrPlugin_mip_MSIP; + _zz_181[11 : 11] = CsrPlugin_mip_MEIP; + _zz_181[7 : 7] = CsrPlugin_mip_MTIP; + _zz_181[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_176[11 : 11] = CsrPlugin_mie_MEIE; - _zz_176[7 : 7] = CsrPlugin_mie_MTIE; - _zz_176[3 : 3] = CsrPlugin_mie_MSIE; + _zz_182[11 : 11] = CsrPlugin_mie_MEIE; + _zz_182[7 : 7] = CsrPlugin_mie_MTIE; + _zz_182[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_177[31 : 2] = CsrPlugin_mtvec_base; - _zz_177[1 : 0] = CsrPlugin_mtvec_mode; + _zz_183[31 : 2] = CsrPlugin_mtvec_base; + _zz_183[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_178[31 : 0] = CsrPlugin_mepc; + _zz_184[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_179[31 : 0] = CsrPlugin_mscratch; + _zz_185[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_180[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_180[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_186[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_186[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_181[31 : 0] = CsrPlugin_mtval; + _zz_187[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_182[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_188[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_183[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_189[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_184[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_190[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_185[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_191[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_186[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_192[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_187[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_193[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_2820)begin - _zz_188[31 : 0] = _zz_149; + _zz_194[31 : 0] = _zz_149; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_2822)begin - _zz_189[31 : 0] = _zz_151; + _zz_195[31 : 0] = _zz_151; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_2824)begin - _zz_190[31 : 0] = _zz_153; + _zz_196[31 : 0] = _zz_153; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_2826)begin - _zz_191[31 : 0] = _zz_155; + _zz_197[31 : 0] = _zz_155; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_2828)begin - _zz_192[31 : 0] = _zz_157; + _zz_198[31 : 0] = _zz_157; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_199 = 32'h0; + if(execute_CsrPlugin_csr_2830)begin + _zz_199[31 : 0] = _zz_159; + end + end + + always @ (*) begin + _zz_200 = 32'h0; + if(execute_CsrPlugin_csr_2832)begin + _zz_200[31 : 0] = _zz_161; + end + end + + always @ (*) begin + _zz_201 = 32'h0; + if(execute_CsrPlugin_csr_2834)begin + _zz_201[31 : 0] = _zz_163; + end + end + + always @ (*) begin + _zz_202 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_193[31 : 0] = _zz_167; + _zz_202[31 : 0] = _zz_173; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_203 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_194[31 : 0] = _zz_168; + _zz_203[31 : 0] = _zz_174; end end - assign execute_CsrPlugin_readData = (((((_zz_169 | _zz_170) | (_zz_171 | _zz_172)) | ((_zz_565 | _zz_173) | (_zz_174 | _zz_175))) | (((_zz_176 | _zz_177) | (_zz_178 | _zz_179)) | ((_zz_180 | _zz_181) | (_zz_182 | _zz_183)))) | ((((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191))) | ((_zz_192 | _zz_193) | _zz_194))); - assign iBusWishbone_ADR = {_zz_369,_zz_195}; - assign iBusWishbone_CTI = ((_zz_195 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_175 | _zz_176) | (_zz_177 | _zz_178)) | ((_zz_574 | _zz_179) | (_zz_180 | _zz_181))) | (((_zz_182 | _zz_183) | (_zz_184 | _zz_185)) | ((_zz_186 | _zz_187) | (_zz_188 | _zz_189)))) | ((((_zz_190 | _zz_191) | (_zz_192 | _zz_193)) | ((_zz_194 | _zz_195) | (_zz_196 | _zz_197))) | (((_zz_198 | _zz_199) | (_zz_200 | _zz_201)) | (_zz_202 | _zz_203)))); + assign iBusWishbone_ADR = {_zz_378,_zz_204}; + assign iBusWishbone_CTI = ((_zz_204 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_263)begin + if(_zz_272)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_263)begin + if(_zz_272)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_196; + assign iBus_rsp_valid = _zz_205; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_202 = (dBus_cmd_payload_length != 3'b000); - assign _zz_198 = dBus_cmd_valid; - assign _zz_200 = dBus_cmd_payload_wr; - assign _zz_201 = (_zz_197 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_199 && (_zz_200 || _zz_201)); - assign dBusWishbone_ADR = ((_zz_202 ? {{dBus_cmd_payload_address[31 : 5],_zz_197},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_202 ? (_zz_201 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_211 = (dBus_cmd_payload_length != 3'b000); + assign _zz_207 = dBus_cmd_valid; + assign _zz_209 = dBus_cmd_payload_wr; + assign _zz_210 = (_zz_206 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_208 && (_zz_209 || _zz_210)); + assign dBusWishbone_ADR = ((_zz_211 ? {{dBus_cmd_payload_address[31 : 5],_zz_206},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_211 ? (_zz_210 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_200 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_200; + assign dBusWishbone_SEL = (_zz_209 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_209; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_199 = (_zz_198 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_198; - assign dBusWishbone_STB = _zz_198; - assign dBus_rsp_valid = _zz_203; + assign _zz_208 = (_zz_207 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_207; + assign dBusWishbone_STB = _zz_207; + assign dBus_rsp_valid = _zz_212; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4850,17 +4910,17 @@ module VexRiscv_inner ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_m2sPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_167 <= 32'h0; + _zz_173 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; memory_to_writeBack_INSTRUCTION <= 32'h0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_195 <= 3'b000; - _zz_196 <= 1'b0; - _zz_197 <= 3'b000; - _zz_203 <= 1'b0; + _zz_204 <= 3'b000; + _zz_205 <= 1'b0; + _zz_206 <= 3'b000; + _zz_212 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -4941,7 +5001,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_264)begin + if(_zz_273)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -4973,14 +5033,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_265)begin - if(_zz_266)begin + if(_zz_274)begin + if(_zz_275)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_267)begin + if(_zz_276)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_268)begin + if(_zz_277)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5005,7 +5065,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_248)begin + if(_zz_257)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5016,8 +5076,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_249)begin - case(_zz_250) + if(_zz_258)begin + case(_zz_259) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5080,35 +5140,35 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_362[0]; - CsrPlugin_mstatus_MIE <= _zz_363[0]; + CsrPlugin_mstatus_MPIE <= _zz_371[0]; + CsrPlugin_mstatus_MIE <= _zz_372[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_365[0]; - CsrPlugin_mie_MTIE <= _zz_366[0]; - CsrPlugin_mie_MSIE <= _zz_367[0]; + CsrPlugin_mie_MEIE <= _zz_374[0]; + CsrPlugin_mie_MTIE <= _zz_375[0]; + CsrPlugin_mie_MSIE <= _zz_376[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_173 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_263)begin + if(_zz_272)begin if(iBusWishbone_ACK)begin - _zz_195 <= (_zz_195 + 3'b001); + _zz_204 <= (_zz_204 + 3'b001); end end - _zz_196 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_198 && _zz_199))begin - _zz_197 <= (_zz_197 + 3'b001); - if(_zz_201)begin - _zz_197 <= 3'b000; + _zz_205 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_207 && _zz_208))begin + _zz_206 <= (_zz_206 + 3'b001); + if(_zz_210)begin + _zz_206 <= 3'b000; end end - _zz_203 <= ((_zz_198 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_212 <= ((_zz_207 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5122,7 +5182,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_264)begin + if(_zz_273)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5149,7 +5209,7 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_245)begin + if(_zz_254)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_146 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_146 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end @@ -5157,7 +5217,7 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_247)begin + if(_zz_256)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); end @@ -5165,21 +5225,21 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_265)begin - if(_zz_266)begin + if(_zz_274)begin + if(_zz_275)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_267)begin + if(_zz_276)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_268)begin + if(_zz_277)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_248)begin + if(_zz_257)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5208,6 +5268,15 @@ module VexRiscv_inner ( if(_zz_158[0])begin _zz_157 <= (_zz_157 + 32'h00000001); end + if(_zz_160[0])begin + _zz_159 <= (_zz_159 + 32'h00000001); + end + if(_zz_162[0])begin + _zz_161 <= (_zz_161 + 32'h00000001); + end + if(_zz_164[0])begin + _zz_163 <= (_zz_163 + 32'h00000001); + end if(CfuPlugin_bus_rsp_ready)begin CfuPlugin_bus_rsp_m2sPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; @@ -5218,20 +5287,20 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_240)begin - if(_zz_261)begin + if(_zz_249)begin + if(_zz_270)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_353[31:0]; + memory_DivPlugin_div_result <= _zz_362[31:0]; end end end - if(_zz_262)begin + if(_zz_271)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_165 ? (~ _zz_166) : _zz_166) + _zz_359); - memory_DivPlugin_rs2 <= ((_zz_164 ? (~ execute_RS2) : execute_RS2) + _zz_361); - memory_DivPlugin_div_needRevert <= ((_zz_165 ^ (_zz_164 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_171 ? (~ _zz_172) : _zz_172) + _zz_368); + memory_DivPlugin_rs2 <= ((_zz_170 ? (~ execute_RS2) : execute_RS2) + _zz_370); + memory_DivPlugin_div_needRevert <= ((_zz_171 ^ (_zz_170 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5510,6 +5579,24 @@ module VexRiscv_inner ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end @@ -5518,7 +5605,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_364[0]; + CsrPlugin_mip_MSIP <= _zz_373[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5539,7 +5626,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_368[0]; + CsrPlugin_mcause_interrupt <= _zz_377[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5618,6 +5705,36 @@ module VexRiscv_inner ( _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; end end + if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + end + end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index 0e42a8b..797c0b7 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : b386c12cdfb49fee6855bbbd273eefd149b82dfe +// Generator : SpinalHDL v1.4.2 git head : 07a72e20035b64cf586cbf04df799cb4bf961010 // Component : VexRiscv -// Git hash : b386c12cdfb49fee6855bbbd273eefd149b82dfe +// Git hash : 07a72e20035b64cf586cbf04df799cb4bf961010 `define Input2Kind_defaultEncoding_type [0:0] @@ -95,37 +95,37 @@ module VexRiscv_inner ( input reset, input debugReset ); - wire _zz_207; - wire _zz_208; - wire _zz_209; - wire _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - reg _zz_215; wire _zz_216; - wire [31:0] _zz_217; + wire _zz_217; wire _zz_218; - wire [31:0] _zz_219; - reg _zz_220; + wire _zz_219; + wire _zz_220; wire _zz_221; wire _zz_222; - wire [31:0] _zz_223; - wire _zz_224; + wire _zz_223; + reg _zz_224; wire _zz_225; - wire _zz_226; + wire [31:0] _zz_226; wire _zz_227; - wire _zz_228; - wire _zz_229; + wire [31:0] _zz_228; + reg _zz_229; wire _zz_230; wire _zz_231; - wire [3:0] _zz_232; + wire [31:0] _zz_232; wire _zz_233; wire _zz_234; - reg [31:0] _zz_235; - reg [31:0] _zz_236; - reg [31:0] _zz_237; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire [3:0] _zz_241; + wire _zz_242; + wire _zz_243; + reg [31:0] _zz_244; + reg [31:0] _zz_245; + reg [31:0] _zz_246; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -157,15 +157,6 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire _zz_245; - wire _zz_246; wire _zz_247; wire _zz_248; wire _zz_249; @@ -175,7 +166,7 @@ module VexRiscv_inner ( wire _zz_253; wire _zz_254; wire _zz_255; - wire [1:0] _zz_256; + wire _zz_256; wire _zz_257; wire _zz_258; wire _zz_259; @@ -184,41 +175,41 @@ module VexRiscv_inner ( wire _zz_262; wire _zz_263; wire _zz_264; - wire _zz_265; - wire [1:0] _zz_266; + wire [1:0] _zz_265; + wire _zz_266; wire _zz_267; wire _zz_268; - wire [5:0] _zz_269; + wire _zz_269; wire _zz_270; wire _zz_271; wire _zz_272; wire _zz_273; wire _zz_274; - wire _zz_275; - wire [1:0] _zz_276; + wire [1:0] _zz_275; + wire _zz_276; wire _zz_277; - wire [1:0] _zz_278; - wire [51:0] _zz_279; - wire [51:0] _zz_280; - wire [51:0] _zz_281; - wire [32:0] _zz_282; - wire [51:0] _zz_283; - wire [49:0] _zz_284; - wire [51:0] _zz_285; - wire [49:0] _zz_286; - wire [51:0] _zz_287; - wire [32:0] _zz_288; - wire [31:0] _zz_289; - wire [32:0] _zz_290; - wire [0:0] _zz_291; - wire [0:0] _zz_292; - wire [0:0] _zz_293; - wire [0:0] _zz_294; - wire [0:0] _zz_295; - wire [0:0] _zz_296; - wire [0:0] _zz_297; - wire [0:0] _zz_298; - wire [0:0] _zz_299; + wire [5:0] _zz_278; + wire _zz_279; + wire _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire _zz_284; + wire [1:0] _zz_285; + wire _zz_286; + wire [1:0] _zz_287; + wire [51:0] _zz_288; + wire [51:0] _zz_289; + wire [51:0] _zz_290; + wire [32:0] _zz_291; + wire [51:0] _zz_292; + wire [49:0] _zz_293; + wire [51:0] _zz_294; + wire [49:0] _zz_295; + wire [51:0] _zz_296; + wire [32:0] _zz_297; + wire [31:0] _zz_298; + wire [32:0] _zz_299; wire [0:0] _zz_300; wire [0:0] _zz_301; wire [0:0] _zz_302; @@ -229,279 +220,288 @@ module VexRiscv_inner ( wire [0:0] _zz_307; wire [0:0] _zz_308; wire [0:0] _zz_309; - wire [3:0] _zz_310; - wire [2:0] _zz_311; - wire [31:0] _zz_312; - wire [11:0] _zz_313; - wire [31:0] _zz_314; - wire [19:0] _zz_315; - wire [11:0] _zz_316; - wire [31:0] _zz_317; - wire [31:0] _zz_318; - wire [19:0] _zz_319; - wire [11:0] _zz_320; - wire [2:0] _zz_321; - wire [2:0] _zz_322; - wire [0:0] _zz_323; - wire [2:0] _zz_324; - wire [4:0] _zz_325; - wire [11:0] _zz_326; - wire [11:0] _zz_327; - wire [31:0] _zz_328; - wire [31:0] _zz_329; - wire [31:0] _zz_330; - wire [31:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [31:0] _zz_334; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire [3:0] _zz_319; + wire [2:0] _zz_320; + wire [31:0] _zz_321; + wire [11:0] _zz_322; + wire [31:0] _zz_323; + wire [19:0] _zz_324; + wire [11:0] _zz_325; + wire [31:0] _zz_326; + wire [31:0] _zz_327; + wire [19:0] _zz_328; + wire [11:0] _zz_329; + wire [2:0] _zz_330; + wire [2:0] _zz_331; + wire [0:0] _zz_332; + wire [2:0] _zz_333; + wire [4:0] _zz_334; wire [11:0] _zz_335; - wire [19:0] _zz_336; - wire [11:0] _zz_337; + wire [11:0] _zz_336; + wire [31:0] _zz_337; wire [31:0] _zz_338; wire [31:0] _zz_339; wire [31:0] _zz_340; - wire [11:0] _zz_341; - wire [19:0] _zz_342; - wire [11:0] _zz_343; - wire [2:0] _zz_344; - wire [1:0] _zz_345; - wire [1:0] _zz_346; - wire [1:0] _zz_347; - wire [1:0] _zz_348; - wire [2:0] _zz_349; + wire [31:0] _zz_341; + wire [31:0] _zz_342; + wire [31:0] _zz_343; + wire [11:0] _zz_344; + wire [19:0] _zz_345; + wire [11:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; + wire [31:0] _zz_349; wire [11:0] _zz_350; - wire [65:0] _zz_351; - wire [65:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire [0:0] _zz_355; - wire [5:0] _zz_356; - wire [32:0] _zz_357; - wire [31:0] _zz_358; - wire [31:0] _zz_359; - wire [32:0] _zz_360; - wire [32:0] _zz_361; - wire [32:0] _zz_362; - wire [32:0] _zz_363; + wire [19:0] _zz_351; + wire [11:0] _zz_352; + wire [2:0] _zz_353; + wire [1:0] _zz_354; + wire [1:0] _zz_355; + wire [1:0] _zz_356; + wire [1:0] _zz_357; + wire [2:0] _zz_358; + wire [11:0] _zz_359; + wire [65:0] _zz_360; + wire [65:0] _zz_361; + wire [31:0] _zz_362; + wire [31:0] _zz_363; wire [0:0] _zz_364; - wire [32:0] _zz_365; - wire [0:0] _zz_366; - wire [32:0] _zz_367; - wire [0:0] _zz_368; - wire [31:0] _zz_369; - wire [0:0] _zz_370; - wire [0:0] _zz_371; - wire [0:0] _zz_372; + wire [5:0] _zz_365; + wire [32:0] _zz_366; + wire [31:0] _zz_367; + wire [31:0] _zz_368; + wire [32:0] _zz_369; + wire [32:0] _zz_370; + wire [32:0] _zz_371; + wire [32:0] _zz_372; wire [0:0] _zz_373; - wire [0:0] _zz_374; + wire [32:0] _zz_374; wire [0:0] _zz_375; - wire [0:0] _zz_376; - wire [26:0] _zz_377; - wire _zz_378; - wire _zz_379; - wire [1:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire _zz_384; + wire [32:0] _zz_376; + wire [0:0] _zz_377; + wire [31:0] _zz_378; + wire [0:0] _zz_379; + wire [0:0] _zz_380; + wire [0:0] _zz_381; + wire [0:0] _zz_382; + wire [0:0] _zz_383; + wire [0:0] _zz_384; wire [0:0] _zz_385; - wire [14:0] _zz_386; - wire [31:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; - wire _zz_390; - wire [0:0] _zz_391; - wire [8:0] _zz_392; - wire [31:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire _zz_396; - wire [0:0] _zz_397; - wire [2:0] _zz_398; + wire [26:0] _zz_386; + wire _zz_387; + wire _zz_388; + wire [1:0] _zz_389; + wire [31:0] _zz_390; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire _zz_393; + wire [0:0] _zz_394; + wire [14:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; wire _zz_399; - wire _zz_400; - wire _zz_401; + wire [0:0] _zz_400; + wire [8:0] _zz_401; wire [31:0] _zz_402; - wire [0:0] _zz_403; - wire [0:0] _zz_404; + wire [31:0] _zz_403; + wire [31:0] _zz_404; wire _zz_405; wire [0:0] _zz_406; - wire [28:0] _zz_407; - wire [0:0] _zz_408; - wire [0:0] _zz_409; - wire [0:0] _zz_410; - wire [0:0] _zz_411; - wire _zz_412; + wire [2:0] _zz_407; + wire _zz_408; + wire _zz_409; + wire _zz_410; + wire [31:0] _zz_411; + wire [0:0] _zz_412; wire [0:0] _zz_413; - wire [23:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; - wire _zz_418; - wire _zz_419; + wire _zz_414; + wire [0:0] _zz_415; + wire [28:0] _zz_416; + wire [0:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; wire [0:0] _zz_420; - wire [0:0] _zz_421; + wire _zz_421; wire [0:0] _zz_422; - wire [0:0] _zz_423; - wire _zz_424; - wire [0:0] _zz_425; - wire [20:0] _zz_426; - wire [31:0] _zz_427; - wire [31:0] _zz_428; - wire _zz_429; - wire _zz_430; + wire [23:0] _zz_423; + wire [31:0] _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire _zz_427; + wire _zz_428; + wire [0:0] _zz_429; + wire [0:0] _zz_430; wire [0:0] _zz_431; - wire [1:0] _zz_432; - wire [0:0] _zz_433; + wire [0:0] _zz_432; + wire _zz_433; wire [0:0] _zz_434; - wire _zz_435; - wire [0:0] _zz_436; - wire [17:0] _zz_437; - wire [31:0] _zz_438; - wire [31:0] _zz_439; - wire [31:0] _zz_440; - wire [31:0] _zz_441; - wire [31:0] _zz_442; - wire [31:0] _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire _zz_446; - wire [1:0] _zz_447; - wire [1:0] _zz_448; - wire _zz_449; - wire [0:0] _zz_450; - wire [14:0] _zz_451; + wire [20:0] _zz_435; + wire [31:0] _zz_436; + wire [31:0] _zz_437; + wire _zz_438; + wire _zz_439; + wire [0:0] _zz_440; + wire [1:0] _zz_441; + wire [0:0] _zz_442; + wire [0:0] _zz_443; + wire _zz_444; + wire [0:0] _zz_445; + wire [17:0] _zz_446; + wire [31:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire [31:0] _zz_450; + wire [31:0] _zz_451; wire [31:0] _zz_452; wire [31:0] _zz_453; wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [31:0] _zz_456; - wire [31:0] _zz_457; - wire [0:0] _zz_458; - wire [1:0] _zz_459; - wire [4:0] _zz_460; - wire [4:0] _zz_461; - wire _zz_462; - wire [0:0] _zz_463; - wire [11:0] _zz_464; + wire _zz_455; + wire [1:0] _zz_456; + wire [1:0] _zz_457; + wire _zz_458; + wire [0:0] _zz_459; + wire [14:0] _zz_460; + wire [31:0] _zz_461; + wire [31:0] _zz_462; + wire [31:0] _zz_463; + wire [31:0] _zz_464; wire [31:0] _zz_465; wire [31:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; + wire [0:0] _zz_467; + wire [1:0] _zz_468; + wire [4:0] _zz_469; + wire [4:0] _zz_470; wire _zz_471; wire [0:0] _zz_472; - wire [1:0] _zz_473; + wire [11:0] _zz_473; wire [31:0] _zz_474; wire [31:0] _zz_475; - wire [0:0] _zz_476; - wire [4:0] _zz_477; - wire [4:0] _zz_478; - wire [4:0] _zz_479; + wire [31:0] _zz_476; + wire [31:0] _zz_477; + wire [31:0] _zz_478; + wire [31:0] _zz_479; wire _zz_480; wire [0:0] _zz_481; - wire [8:0] _zz_482; + wire [1:0] _zz_482; wire [31:0] _zz_483; wire [31:0] _zz_484; - wire [31:0] _zz_485; - wire _zz_486; - wire _zz_487; - wire [31:0] _zz_488; - wire [31:0] _zz_489; - wire _zz_490; - wire [0:0] _zz_491; - wire [2:0] _zz_492; - wire [0:0] _zz_493; - wire [2:0] _zz_494; - wire [0:0] _zz_495; - wire [4:0] _zz_496; - wire [1:0] _zz_497; - wire [1:0] _zz_498; + wire [0:0] _zz_485; + wire [4:0] _zz_486; + wire [4:0] _zz_487; + wire [4:0] _zz_488; + wire _zz_489; + wire [0:0] _zz_490; + wire [8:0] _zz_491; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire _zz_495; + wire _zz_496; + wire [31:0] _zz_497; + wire [31:0] _zz_498; wire _zz_499; wire [0:0] _zz_500; - wire [6:0] _zz_501; - wire [31:0] _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire _zz_505; - wire [0:0] _zz_506; - wire [0:0] _zz_507; - wire [31:0] _zz_508; - wire [31:0] _zz_509; - wire _zz_510; - wire [0:0] _zz_511; - wire [0:0] _zz_512; - wire _zz_513; - wire [0:0] _zz_514; - wire [2:0] _zz_515; - wire _zz_516; - wire [0:0] _zz_517; - wire [0:0] _zz_518; - wire [0:0] _zz_519; + wire [2:0] _zz_501; + wire [0:0] _zz_502; + wire [2:0] _zz_503; + wire [0:0] _zz_504; + wire [4:0] _zz_505; + wire [1:0] _zz_506; + wire [1:0] _zz_507; + wire _zz_508; + wire [0:0] _zz_509; + wire [6:0] _zz_510; + wire [31:0] _zz_511; + wire [31:0] _zz_512; + wire [31:0] _zz_513; + wire _zz_514; + wire [0:0] _zz_515; + wire [0:0] _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire _zz_519; wire [0:0] _zz_520; - wire _zz_521; - wire [0:0] _zz_522; - wire [4:0] _zz_523; - wire [31:0] _zz_524; - wire [31:0] _zz_525; - wire [31:0] _zz_526; - wire [31:0] _zz_527; - wire [31:0] _zz_528; - wire [31:0] _zz_529; - wire [31:0] _zz_530; - wire [31:0] _zz_531; - wire [31:0] _zz_532; + wire [0:0] _zz_521; + wire _zz_522; + wire [0:0] _zz_523; + wire [2:0] _zz_524; + wire _zz_525; + wire [0:0] _zz_526; + wire [0:0] _zz_527; + wire [0:0] _zz_528; + wire [0:0] _zz_529; + wire _zz_530; + wire [0:0] _zz_531; + wire [4:0] _zz_532; wire [31:0] _zz_533; wire [31:0] _zz_534; wire [31:0] _zz_535; wire [31:0] _zz_536; - wire _zz_537; - wire [0:0] _zz_538; - wire [0:0] _zz_539; + wire [31:0] _zz_537; + wire [31:0] _zz_538; + wire [31:0] _zz_539; wire [31:0] _zz_540; wire [31:0] _zz_541; wire [31:0] _zz_542; wire [31:0] _zz_543; wire [31:0] _zz_544; - wire _zz_545; - wire [3:0] _zz_546; - wire [3:0] _zz_547; - wire _zz_548; - wire [0:0] _zz_549; - wire [2:0] _zz_550; + wire [31:0] _zz_545; + wire _zz_546; + wire [0:0] _zz_547; + wire [0:0] _zz_548; + wire [31:0] _zz_549; + wire [31:0] _zz_550; wire [31:0] _zz_551; wire [31:0] _zz_552; wire [31:0] _zz_553; - wire [31:0] _zz_554; - wire [31:0] _zz_555; - wire [31:0] _zz_556; + wire _zz_554; + wire [3:0] _zz_555; + wire [3:0] _zz_556; wire _zz_557; wire [0:0] _zz_558; - wire [1:0] _zz_559; - wire _zz_560; - wire [2:0] _zz_561; - wire [2:0] _zz_562; - wire _zz_563; - wire [0:0] _zz_564; - wire [0:0] _zz_565; - wire [31:0] _zz_566; - wire [31:0] _zz_567; - wire [31:0] _zz_568; - wire [31:0] _zz_569; - wire [31:0] _zz_570; - wire [31:0] _zz_571; - wire [31:0] _zz_572; - wire _zz_573; - wire _zz_574; - wire _zz_575; - wire [0:0] _zz_576; - wire [0:0] _zz_577; - wire _zz_578; - wire _zz_579; - wire _zz_580; - wire _zz_581; - wire [31:0] _zz_582; + wire [2:0] _zz_559; + wire [31:0] _zz_560; + wire [31:0] _zz_561; + wire [31:0] _zz_562; + wire [31:0] _zz_563; + wire [31:0] _zz_564; + wire [31:0] _zz_565; + wire _zz_566; + wire [0:0] _zz_567; + wire [1:0] _zz_568; + wire _zz_569; + wire [2:0] _zz_570; + wire [2:0] _zz_571; + wire _zz_572; + wire [0:0] _zz_573; + wire [0:0] _zz_574; + wire [31:0] _zz_575; + wire [31:0] _zz_576; + wire [31:0] _zz_577; + wire [31:0] _zz_578; + wire [31:0] _zz_579; + wire [31:0] _zz_580; + wire [31:0] _zz_581; + wire _zz_582; + wire _zz_583; + wire _zz_584; + wire [0:0] _zz_585; + wire [0:0] _zz_586; + wire _zz_587; + wire _zz_588; + wire _zz_589; + wire _zz_590; + wire [31:0] _zz_591; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1107,13 +1107,19 @@ module VexRiscv_inner ( reg [31:0] _zz_157; reg [31:0] _zz_158; reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [2:0] execute_CfuPlugin_functionsIds_0; - wire _zz_160; - reg [19:0] _zz_161; - reg [31:0] _zz_162; + wire _zz_166; + reg [19:0] _zz_167; + reg [31:0] _zz_168; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1145,18 +1151,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_163; + wire [31:0] _zz_169; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_164; - wire _zz_165; - wire _zz_166; - reg [32:0] _zz_167; + wire [31:0] _zz_170; + wire _zz_171; + wire _zz_172; + reg [32:0] _zz_173; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_168; - wire [31:0] _zz_169; + reg [31:0] _zz_174; + wire [31:0] _zz_175; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1166,7 +1172,7 @@ module VexRiscv_inner ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_170; + reg _zz_176; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; @@ -1234,7 +1240,7 @@ module VexRiscv_inner ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_171; + reg [2:0] _zz_177; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; @@ -1265,14 +1271,14 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2827; reg execute_CsrPlugin_csr_2828; reg execute_CsrPlugin_csr_2829; + reg execute_CsrPlugin_csr_2830; + reg execute_CsrPlugin_csr_2831; + reg execute_CsrPlugin_csr_2832; + reg execute_CsrPlugin_csr_2833; + reg execute_CsrPlugin_csr_2834; + reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; - reg [31:0] _zz_177; reg [31:0] _zz_178; reg [31:0] _zz_179; reg [31:0] _zz_180; @@ -1293,16 +1299,25 @@ module VexRiscv_inner ( reg [31:0] _zz_195; reg [31:0] _zz_196; reg [31:0] _zz_197; - reg [2:0] _zz_198; - reg _zz_199; + reg [31:0] _zz_198; + reg [31:0] _zz_199; + reg [31:0] _zz_200; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [2:0] _zz_207; + reg _zz_208; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - wire _zz_204; - wire _zz_205; - reg _zz_206; + reg [2:0] _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + reg _zz_215; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; @@ -1396,360 +1411,360 @@ module VexRiscv_inner ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_238 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_239 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_240 = 1'b1; - assign _zz_241 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_242 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_243 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_244 = ((_zz_212 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_245 = ((_zz_212 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_246 = ((_zz_212 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_247 = ((_zz_212 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_248 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_249 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_250 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_251 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_252 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_253 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_254 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_255 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_256 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_257 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_258 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_259 = (1'b0 || (! 1'b1)); - assign _zz_260 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_261 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_262 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_263 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_264 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_265 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_266 = execute_INSTRUCTION[13 : 12]; - assign _zz_267 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_268 = (! memory_arbitration_isStuck); - assign _zz_269 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_270 = (iBus_cmd_valid || (_zz_198 != 3'b000)); - assign _zz_271 = (_zz_234 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_272 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_273 = ((_zz_143 && 1'b1) && (! 1'b0)); - assign _zz_274 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_275 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_276 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_277 = execute_INSTRUCTION[13]; - assign _zz_278 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_279 = ($signed(_zz_280) + $signed(_zz_285)); - assign _zz_280 = ($signed(_zz_281) + $signed(_zz_283)); - assign _zz_281 = 52'h0; - assign _zz_282 = {1'b0,memory_MUL_LL}; - assign _zz_283 = {{19{_zz_282[32]}}, _zz_282}; - assign _zz_284 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_285 = {{2{_zz_284[49]}}, _zz_284}; - assign _zz_286 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_287 = {{2{_zz_286[49]}}, _zz_286}; - assign _zz_288 = ($signed(_zz_290) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_289 = _zz_288[31 : 0]; - assign _zz_290 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_291 = _zz_92[33 : 33]; - assign _zz_292 = _zz_92[32 : 32]; - assign _zz_293 = _zz_92[31 : 31]; - assign _zz_294 = _zz_92[30 : 30]; - assign _zz_295 = _zz_92[28 : 28]; - assign _zz_296 = _zz_92[25 : 25]; - assign _zz_297 = _zz_92[17 : 17]; - assign _zz_298 = _zz_92[16 : 16]; - assign _zz_299 = _zz_92[13 : 13]; - assign _zz_300 = _zz_92[12 : 12]; - assign _zz_301 = _zz_92[11 : 11]; - assign _zz_302 = _zz_92[34 : 34]; - assign _zz_303 = _zz_92[15 : 15]; - assign _zz_304 = _zz_92[5 : 5]; - assign _zz_305 = _zz_92[3 : 3]; - assign _zz_306 = _zz_92[20 : 20]; - assign _zz_307 = _zz_92[10 : 10]; - assign _zz_308 = _zz_92[4 : 4]; - assign _zz_309 = _zz_92[0 : 0]; - assign _zz_310 = (_zz_60 - 4'b0001); - assign _zz_311 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_312 = {29'd0, _zz_311}; - assign _zz_313 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_314 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_315 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_316 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_317 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_318 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_319 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_321 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_322 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_323 = execute_SRC_LESS; - assign _zz_324 = 3'b100; - assign _zz_325 = execute_INSTRUCTION[19 : 15]; - assign _zz_326 = execute_INSTRUCTION[31 : 20]; - assign _zz_327 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_328 = ($signed(_zz_329) + $signed(_zz_332)); - assign _zz_329 = ($signed(_zz_330) + $signed(_zz_331)); - assign _zz_330 = execute_SRC1; - assign _zz_331 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_332 = (execute_SRC_USE_SUB_LESS ? _zz_333 : _zz_334); - assign _zz_333 = 32'h00000001; - assign _zz_334 = 32'h0; + assign _zz_247 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_248 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_249 = 1'b1; + assign _zz_250 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_251 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_252 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_253 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_254 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_255 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_256 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_257 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_258 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_259 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_260 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_261 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_262 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_263 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_264 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_265 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_266 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_267 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_268 = (1'b0 || (! 1'b1)); + assign _zz_269 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_270 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_271 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_272 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_273 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_274 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_275 = execute_INSTRUCTION[13 : 12]; + assign _zz_276 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_277 = (! memory_arbitration_isStuck); + assign _zz_278 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_279 = (iBus_cmd_valid || (_zz_207 != 3'b000)); + assign _zz_280 = (_zz_243 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_281 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_282 = ((_zz_143 && 1'b1) && (! 1'b0)); + assign _zz_283 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_284 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_285 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_286 = execute_INSTRUCTION[13]; + assign _zz_287 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_288 = ($signed(_zz_289) + $signed(_zz_294)); + assign _zz_289 = ($signed(_zz_290) + $signed(_zz_292)); + assign _zz_290 = 52'h0; + assign _zz_291 = {1'b0,memory_MUL_LL}; + assign _zz_292 = {{19{_zz_291[32]}}, _zz_291}; + assign _zz_293 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_294 = {{2{_zz_293[49]}}, _zz_293}; + assign _zz_295 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_296 = {{2{_zz_295[49]}}, _zz_295}; + assign _zz_297 = ($signed(_zz_299) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_298 = _zz_297[31 : 0]; + assign _zz_299 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_300 = _zz_92[33 : 33]; + assign _zz_301 = _zz_92[32 : 32]; + assign _zz_302 = _zz_92[31 : 31]; + assign _zz_303 = _zz_92[30 : 30]; + assign _zz_304 = _zz_92[28 : 28]; + assign _zz_305 = _zz_92[25 : 25]; + assign _zz_306 = _zz_92[17 : 17]; + assign _zz_307 = _zz_92[16 : 16]; + assign _zz_308 = _zz_92[13 : 13]; + assign _zz_309 = _zz_92[12 : 12]; + assign _zz_310 = _zz_92[11 : 11]; + assign _zz_311 = _zz_92[34 : 34]; + assign _zz_312 = _zz_92[15 : 15]; + assign _zz_313 = _zz_92[5 : 5]; + assign _zz_314 = _zz_92[3 : 3]; + assign _zz_315 = _zz_92[20 : 20]; + assign _zz_316 = _zz_92[10 : 10]; + assign _zz_317 = _zz_92[4 : 4]; + assign _zz_318 = _zz_92[0 : 0]; + assign _zz_319 = (_zz_60 - 4'b0001); + assign _zz_320 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_321 = {29'd0, _zz_320}; + assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_323 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_324 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_325 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_326 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_327 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_329 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_330 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_331 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_332 = execute_SRC_LESS; + assign _zz_333 = 3'b100; + assign _zz_334 = execute_INSTRUCTION[19 : 15]; assign _zz_335 = execute_INSTRUCTION[31 : 20]; - assign _zz_336 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_337 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_338 = {_zz_131,execute_INSTRUCTION[31 : 20]}; - assign _zz_339 = {{_zz_133,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_340 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_341 = execute_INSTRUCTION[31 : 20]; - assign _zz_342 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_344 = 3'b100; - assign _zz_345 = (_zz_146 & (~ _zz_346)); - assign _zz_346 = (_zz_146 - 2'b01); - assign _zz_347 = (_zz_148 & (~ _zz_348)); - assign _zz_348 = (_zz_148 - 2'b01); - assign _zz_349 = execute_INSTRUCTION[14 : 12]; + assign _zz_336 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_337 = ($signed(_zz_338) + $signed(_zz_341)); + assign _zz_338 = ($signed(_zz_339) + $signed(_zz_340)); + assign _zz_339 = execute_SRC1; + assign _zz_340 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_341 = (execute_SRC_USE_SUB_LESS ? _zz_342 : _zz_343); + assign _zz_342 = 32'h00000001; + assign _zz_343 = 32'h0; + assign _zz_344 = execute_INSTRUCTION[31 : 20]; + assign _zz_345 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_346 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_347 = {_zz_131,execute_INSTRUCTION[31 : 20]}; + assign _zz_348 = {{_zz_133,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_349 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; assign _zz_350 = execute_INSTRUCTION[31 : 20]; - assign _zz_351 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_352 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_353 = writeBack_MUL_LOW[31 : 0]; - assign _zz_354 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_355 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_356 = {5'd0, _zz_355}; - assign _zz_357 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_358 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_359 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_360 = {_zz_163,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_361 = _zz_362; - assign _zz_362 = _zz_363; - assign _zz_363 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_164) : _zz_164)} + _zz_365); - assign _zz_364 = memory_DivPlugin_div_needRevert; - assign _zz_365 = {32'd0, _zz_364}; - assign _zz_366 = _zz_166; - assign _zz_367 = {32'd0, _zz_366}; - assign _zz_368 = _zz_165; - assign _zz_369 = {31'd0, _zz_368}; - assign _zz_370 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_371 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_372 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_373 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_374 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_375 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_376 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_377 = (iBus_cmd_payload_address >>> 5); - assign _zz_378 = 1'b1; - assign _zz_379 = 1'b1; - assign _zz_380 = {_zz_64,_zz_63}; - assign _zz_381 = 32'h0000106f; - assign _zz_382 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_383 = 32'h00001073; - assign _zz_384 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_385 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_386 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_387) == 32'h00000003),{(_zz_388 == _zz_389),{_zz_390,{_zz_391,_zz_392}}}}}}; - assign _zz_387 = 32'h0000207f; - assign _zz_388 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_389 = 32'h00000003; - assign _zz_390 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_391 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_392 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_393) == 32'h00005013),{(_zz_394 == _zz_395),{_zz_396,{_zz_397,_zz_398}}}}}}; - assign _zz_393 = 32'hbc00707f; - assign _zz_394 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_395 = 32'h00001013; - assign _zz_396 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_397 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_398 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; - assign _zz_399 = decode_INSTRUCTION[31]; - assign _zz_400 = decode_INSTRUCTION[31]; - assign _zz_401 = decode_INSTRUCTION[7]; - assign _zz_402 = 32'h10103050; - assign _zz_403 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_404 = 1'b0; - assign _zz_405 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_406 = 1'b0; - assign _zz_407 = {(_zz_96 != 1'b0),{({_zz_408,_zz_409} != 2'b00),{(_zz_410 != _zz_411),{_zz_412,{_zz_413,_zz_414}}}}}; - assign _zz_408 = ((decode_INSTRUCTION & _zz_415) == 32'h10000050); - assign _zz_409 = ((decode_INSTRUCTION & _zz_416) == 32'h00000050); - assign _zz_410 = ((decode_INSTRUCTION & _zz_417) == 32'h00000050); - assign _zz_411 = 1'b0; - assign _zz_412 = ({_zz_418,_zz_419} != 2'b00); - assign _zz_413 = ({_zz_420,_zz_421} != 2'b00); - assign _zz_414 = {(_zz_422 != _zz_423),{_zz_424,{_zz_425,_zz_426}}}; - assign _zz_415 = 32'h10203050; - assign _zz_416 = 32'h10103050; - assign _zz_417 = 32'h00103050; - assign _zz_418 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_419 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_420 = _zz_95; - assign _zz_421 = ((decode_INSTRUCTION & _zz_427) == 32'h00000004); - assign _zz_422 = ((decode_INSTRUCTION & _zz_428) == 32'h00000040); - assign _zz_423 = 1'b0; - assign _zz_424 = ({_zz_429,_zz_430} != 2'b00); - assign _zz_425 = ({_zz_431,_zz_432} != 3'b000); - assign _zz_426 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; - assign _zz_427 = 32'h0000001c; - assign _zz_428 = 32'h00000058; - assign _zz_429 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_430 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h40001010); - assign _zz_432 = {(_zz_439 == _zz_440),(_zz_441 == _zz_442)}; - assign _zz_433 = ((decode_INSTRUCTION & _zz_443) == 32'h00000024); - assign _zz_434 = 1'b0; - assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); - assign _zz_436 = (_zz_446 != 1'b0); - assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; - assign _zz_438 = 32'h40003054; - assign _zz_439 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_440 = 32'h00001010; - assign _zz_441 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_442 = 32'h00001010; - assign _zz_443 = 32'h00000064; - assign _zz_444 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_445 = 32'h00001000; - assign _zz_446 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_447 = {(_zz_452 == _zz_453),(_zz_454 == _zz_455)}; - assign _zz_448 = 2'b00; - assign _zz_449 = ((_zz_456 == _zz_457) != 1'b0); - assign _zz_450 = ({_zz_458,_zz_459} != 3'b000); - assign _zz_451 = {(_zz_460 != _zz_461),{_zz_462,{_zz_463,_zz_464}}}; - assign _zz_452 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_453 = 32'h00002000; - assign _zz_454 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_455 = 32'h00001000; - assign _zz_456 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_457 = 32'h00004004; - assign _zz_458 = _zz_96; - assign _zz_459 = {(_zz_465 == _zz_466),(_zz_467 == _zz_468)}; - assign _zz_460 = {(_zz_469 == _zz_470),{_zz_471,{_zz_472,_zz_473}}}; - assign _zz_461 = 5'h0; - assign _zz_462 = ((_zz_474 == _zz_475) != 1'b0); - assign _zz_463 = ({_zz_476,_zz_477} != 6'h0); - assign _zz_464 = {(_zz_478 != _zz_479),{_zz_480,{_zz_481,_zz_482}}}; - assign _zz_465 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_466 = 32'h00000020; - assign _zz_467 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_468 = 32'h00000020; - assign _zz_469 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_470 = 32'h00002040; - assign _zz_471 = ((decode_INSTRUCTION & _zz_483) == 32'h00001040); - assign _zz_472 = (_zz_484 == _zz_485); - assign _zz_473 = {_zz_486,_zz_487}; - assign _zz_474 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_353 = 3'b100; + assign _zz_354 = (_zz_146 & (~ _zz_355)); + assign _zz_355 = (_zz_146 - 2'b01); + assign _zz_356 = (_zz_148 & (~ _zz_357)); + assign _zz_357 = (_zz_148 - 2'b01); + assign _zz_358 = execute_INSTRUCTION[14 : 12]; + assign _zz_359 = execute_INSTRUCTION[31 : 20]; + assign _zz_360 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_361 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_362 = writeBack_MUL_LOW[31 : 0]; + assign _zz_363 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_364 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_365 = {5'd0, _zz_364}; + assign _zz_366 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_367 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_368 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_369 = {_zz_169,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_370 = _zz_371; + assign _zz_371 = _zz_372; + assign _zz_372 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_170) : _zz_170)} + _zz_374); + assign _zz_373 = memory_DivPlugin_div_needRevert; + assign _zz_374 = {32'd0, _zz_373}; + assign _zz_375 = _zz_172; + assign _zz_376 = {32'd0, _zz_375}; + assign _zz_377 = _zz_171; + assign _zz_378 = {31'd0, _zz_377}; + assign _zz_379 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_380 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_381 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_382 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_383 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_384 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_385 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_386 = (iBus_cmd_payload_address >>> 5); + assign _zz_387 = 1'b1; + assign _zz_388 = 1'b1; + assign _zz_389 = {_zz_64,_zz_63}; + assign _zz_390 = 32'h0000106f; + assign _zz_391 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_392 = 32'h00001073; + assign _zz_393 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_394 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_395 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}; + assign _zz_396 = 32'h0000207f; + assign _zz_397 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_398 = 32'h00000003; + assign _zz_399 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_400 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_401 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_402) == 32'h00005013),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; + assign _zz_402 = 32'hbc00707f; + assign _zz_403 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_404 = 32'h00001013; + assign _zz_405 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_406 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_407 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_408 = decode_INSTRUCTION[31]; + assign _zz_409 = decode_INSTRUCTION[31]; + assign _zz_410 = decode_INSTRUCTION[7]; + assign _zz_411 = 32'h10103050; + assign _zz_412 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_413 = 1'b0; + assign _zz_414 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_415 = 1'b0; + assign _zz_416 = {(_zz_96 != 1'b0),{({_zz_417,_zz_418} != 2'b00),{(_zz_419 != _zz_420),{_zz_421,{_zz_422,_zz_423}}}}}; + assign _zz_417 = ((decode_INSTRUCTION & _zz_424) == 32'h10000050); + assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00000050); + assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00000050); + assign _zz_420 = 1'b0; + assign _zz_421 = ({_zz_427,_zz_428} != 2'b00); + assign _zz_422 = ({_zz_429,_zz_430} != 2'b00); + assign _zz_423 = {(_zz_431 != _zz_432),{_zz_433,{_zz_434,_zz_435}}}; + assign _zz_424 = 32'h10203050; + assign _zz_425 = 32'h10103050; + assign _zz_426 = 32'h00103050; + assign _zz_427 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_428 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_429 = _zz_95; + assign _zz_430 = ((decode_INSTRUCTION & _zz_436) == 32'h00000004); + assign _zz_431 = ((decode_INSTRUCTION & _zz_437) == 32'h00000040); + assign _zz_432 = 1'b0; + assign _zz_433 = ({_zz_438,_zz_439} != 2'b00); + assign _zz_434 = ({_zz_440,_zz_441} != 3'b000); + assign _zz_435 = {(_zz_442 != _zz_443),{_zz_444,{_zz_445,_zz_446}}}; + assign _zz_436 = 32'h0000001c; + assign _zz_437 = 32'h00000058; + assign _zz_438 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_439 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_440 = ((decode_INSTRUCTION & _zz_447) == 32'h40001010); + assign _zz_441 = {(_zz_448 == _zz_449),(_zz_450 == _zz_451)}; + assign _zz_442 = ((decode_INSTRUCTION & _zz_452) == 32'h00000024); + assign _zz_443 = 1'b0; + assign _zz_444 = ((_zz_453 == _zz_454) != 1'b0); + assign _zz_445 = (_zz_455 != 1'b0); + assign _zz_446 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; + assign _zz_447 = 32'h40003054; + assign _zz_448 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_449 = 32'h00001010; + assign _zz_450 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_451 = 32'h00001010; + assign _zz_452 = 32'h00000064; + assign _zz_453 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_454 = 32'h00001000; + assign _zz_455 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_456 = {(_zz_461 == _zz_462),(_zz_463 == _zz_464)}; + assign _zz_457 = 2'b00; + assign _zz_458 = ((_zz_465 == _zz_466) != 1'b0); + assign _zz_459 = ({_zz_467,_zz_468} != 3'b000); + assign _zz_460 = {(_zz_469 != _zz_470),{_zz_471,{_zz_472,_zz_473}}}; + assign _zz_461 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_462 = 32'h00002000; + assign _zz_463 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_464 = 32'h00001000; + assign _zz_465 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_466 = 32'h00004004; + assign _zz_467 = _zz_96; + assign _zz_468 = {(_zz_474 == _zz_475),(_zz_476 == _zz_477)}; + assign _zz_469 = {(_zz_478 == _zz_479),{_zz_480,{_zz_481,_zz_482}}}; + assign _zz_470 = 5'h0; + assign _zz_471 = ((_zz_483 == _zz_484) != 1'b0); + assign _zz_472 = ({_zz_485,_zz_486} != 6'h0); + assign _zz_473 = {(_zz_487 != _zz_488),{_zz_489,{_zz_490,_zz_491}}}; + assign _zz_474 = (decode_INSTRUCTION & 32'h00000034); assign _zz_475 = 32'h00000020; - assign _zz_476 = (_zz_488 == _zz_489); - assign _zz_477 = {_zz_490,{_zz_491,_zz_492}}; - assign _zz_478 = {_zz_94,{_zz_493,_zz_494}}; - assign _zz_479 = 5'h0; - assign _zz_480 = ({_zz_495,_zz_496} != 6'h0); - assign _zz_481 = (_zz_497 != _zz_498); - assign _zz_482 = {_zz_499,{_zz_500,_zz_501}}; - assign _zz_483 = 32'h00001040; - assign _zz_484 = (decode_INSTRUCTION & 32'h00100040); - assign _zz_485 = 32'h00000040; - assign _zz_486 = ((decode_INSTRUCTION & _zz_502) == 32'h00000040); - assign _zz_487 = ((decode_INSTRUCTION & _zz_503) == 32'h0); - assign _zz_488 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_489 = 32'h00000008; - assign _zz_490 = ((decode_INSTRUCTION & _zz_504) == 32'h00000040); - assign _zz_491 = _zz_94; - assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; - assign _zz_493 = (_zz_508 == _zz_509); - assign _zz_494 = {_zz_510,{_zz_511,_zz_512}}; - assign _zz_495 = _zz_95; - assign _zz_496 = {_zz_513,{_zz_514,_zz_515}}; - assign _zz_497 = {_zz_94,_zz_516}; - assign _zz_498 = 2'b00; - assign _zz_499 = ({_zz_517,_zz_518} != 2'b00); - assign _zz_500 = (_zz_519 != _zz_520); - assign _zz_501 = {_zz_521,{_zz_522,_zz_523}}; - assign _zz_502 = 32'h00000050; - assign _zz_503 = 32'h00000038; - assign _zz_504 = 32'h00000040; - assign _zz_505 = ((decode_INSTRUCTION & _zz_524) == 32'h00004020); - assign _zz_506 = (_zz_525 == _zz_526); - assign _zz_507 = (_zz_527 == _zz_528); - assign _zz_508 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_509 = 32'h00002010; - assign _zz_510 = ((decode_INSTRUCTION & _zz_529) == 32'h00000010); - assign _zz_511 = (_zz_530 == _zz_531); - assign _zz_512 = (_zz_532 == _zz_533); - assign _zz_513 = ((decode_INSTRUCTION & _zz_534) == 32'h00001010); - assign _zz_514 = (_zz_535 == _zz_536); - assign _zz_515 = {_zz_537,{_zz_538,_zz_539}}; - assign _zz_516 = ((decode_INSTRUCTION & _zz_540) == 32'h00000020); - assign _zz_517 = _zz_94; - assign _zz_518 = (_zz_541 == _zz_542); - assign _zz_519 = (_zz_543 == _zz_544); - assign _zz_520 = 1'b0; - assign _zz_521 = (_zz_545 != 1'b0); - assign _zz_522 = (_zz_546 != _zz_547); - assign _zz_523 = {_zz_548,{_zz_549,_zz_550}}; - assign _zz_524 = 32'h00004020; - assign _zz_525 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_526 = 32'h00000010; - assign _zz_527 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_528 = 32'h00000020; - assign _zz_529 = 32'h00001030; - assign _zz_530 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_531 = 32'h00002020; - assign _zz_532 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_533 = 32'h00000020; - assign _zz_534 = 32'h00001010; - assign _zz_535 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_536 = 32'h00002010; - assign _zz_537 = ((decode_INSTRUCTION & _zz_551) == 32'h00000010); - assign _zz_538 = (_zz_552 == _zz_553); - assign _zz_539 = (_zz_554 == _zz_555); - assign _zz_540 = 32'h00000070; - assign _zz_541 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_542 = 32'h0; - assign _zz_543 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_544 = 32'h00004010; - assign _zz_545 = ((decode_INSTRUCTION & _zz_556) == 32'h00002010); - assign _zz_546 = {_zz_557,{_zz_558,_zz_559}}; - assign _zz_547 = 4'b0000; - assign _zz_548 = (_zz_560 != 1'b0); - assign _zz_549 = (_zz_561 != _zz_562); - assign _zz_550 = {_zz_563,{_zz_564,_zz_565}}; - assign _zz_551 = 32'h00000050; - assign _zz_552 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_553 = 32'h00000004; - assign _zz_554 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_555 = 32'h0; - assign _zz_556 = 32'h00006014; - assign _zz_557 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_558 = ((decode_INSTRUCTION & _zz_566) == 32'h0); - assign _zz_559 = {(_zz_567 == _zz_568),(_zz_569 == _zz_570)}; - assign _zz_560 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_561 = {(_zz_571 == _zz_572),{_zz_573,_zz_574}}; - assign _zz_562 = 3'b000; - assign _zz_563 = ({_zz_575,_zz_93} != 2'b00); - assign _zz_564 = ({_zz_576,_zz_577} != 2'b00); - assign _zz_565 = (_zz_578 != 1'b0); - assign _zz_566 = 32'h00000018; - assign _zz_567 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_568 = 32'h00002000; - assign _zz_569 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_570 = 32'h00001000; - assign _zz_571 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_572 = 32'h00000040; - assign _zz_573 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_574 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_575 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_576 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_577 = _zz_93; - assign _zz_578 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); - assign _zz_579 = execute_INSTRUCTION[31]; - assign _zz_580 = execute_INSTRUCTION[31]; - assign _zz_581 = execute_INSTRUCTION[7]; - assign _zz_582 = 32'h0; + assign _zz_476 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_477 = 32'h00000020; + assign _zz_478 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_479 = 32'h00002040; + assign _zz_480 = ((decode_INSTRUCTION & _zz_492) == 32'h00001040); + assign _zz_481 = (_zz_493 == _zz_494); + assign _zz_482 = {_zz_495,_zz_496}; + assign _zz_483 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_484 = 32'h00000020; + assign _zz_485 = (_zz_497 == _zz_498); + assign _zz_486 = {_zz_499,{_zz_500,_zz_501}}; + assign _zz_487 = {_zz_94,{_zz_502,_zz_503}}; + assign _zz_488 = 5'h0; + assign _zz_489 = ({_zz_504,_zz_505} != 6'h0); + assign _zz_490 = (_zz_506 != _zz_507); + assign _zz_491 = {_zz_508,{_zz_509,_zz_510}}; + assign _zz_492 = 32'h00001040; + assign _zz_493 = (decode_INSTRUCTION & 32'h00100040); + assign _zz_494 = 32'h00000040; + assign _zz_495 = ((decode_INSTRUCTION & _zz_511) == 32'h00000040); + assign _zz_496 = ((decode_INSTRUCTION & _zz_512) == 32'h0); + assign _zz_497 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_498 = 32'h00000008; + assign _zz_499 = ((decode_INSTRUCTION & _zz_513) == 32'h00000040); + assign _zz_500 = _zz_94; + assign _zz_501 = {_zz_514,{_zz_515,_zz_516}}; + assign _zz_502 = (_zz_517 == _zz_518); + assign _zz_503 = {_zz_519,{_zz_520,_zz_521}}; + assign _zz_504 = _zz_95; + assign _zz_505 = {_zz_522,{_zz_523,_zz_524}}; + assign _zz_506 = {_zz_94,_zz_525}; + assign _zz_507 = 2'b00; + assign _zz_508 = ({_zz_526,_zz_527} != 2'b00); + assign _zz_509 = (_zz_528 != _zz_529); + assign _zz_510 = {_zz_530,{_zz_531,_zz_532}}; + assign _zz_511 = 32'h00000050; + assign _zz_512 = 32'h00000038; + assign _zz_513 = 32'h00000040; + assign _zz_514 = ((decode_INSTRUCTION & _zz_533) == 32'h00004020); + assign _zz_515 = (_zz_534 == _zz_535); + assign _zz_516 = (_zz_536 == _zz_537); + assign _zz_517 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_518 = 32'h00002010; + assign _zz_519 = ((decode_INSTRUCTION & _zz_538) == 32'h00000010); + assign _zz_520 = (_zz_539 == _zz_540); + assign _zz_521 = (_zz_541 == _zz_542); + assign _zz_522 = ((decode_INSTRUCTION & _zz_543) == 32'h00001010); + assign _zz_523 = (_zz_544 == _zz_545); + assign _zz_524 = {_zz_546,{_zz_547,_zz_548}}; + assign _zz_525 = ((decode_INSTRUCTION & _zz_549) == 32'h00000020); + assign _zz_526 = _zz_94; + assign _zz_527 = (_zz_550 == _zz_551); + assign _zz_528 = (_zz_552 == _zz_553); + assign _zz_529 = 1'b0; + assign _zz_530 = (_zz_554 != 1'b0); + assign _zz_531 = (_zz_555 != _zz_556); + assign _zz_532 = {_zz_557,{_zz_558,_zz_559}}; + assign _zz_533 = 32'h00004020; + assign _zz_534 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_535 = 32'h00000010; + assign _zz_536 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_537 = 32'h00000020; + assign _zz_538 = 32'h00001030; + assign _zz_539 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_540 = 32'h00002020; + assign _zz_541 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_542 = 32'h00000020; + assign _zz_543 = 32'h00001010; + assign _zz_544 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_545 = 32'h00002010; + assign _zz_546 = ((decode_INSTRUCTION & _zz_560) == 32'h00000010); + assign _zz_547 = (_zz_561 == _zz_562); + assign _zz_548 = (_zz_563 == _zz_564); + assign _zz_549 = 32'h00000070; + assign _zz_550 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_551 = 32'h0; + assign _zz_552 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_553 = 32'h00004010; + assign _zz_554 = ((decode_INSTRUCTION & _zz_565) == 32'h00002010); + assign _zz_555 = {_zz_566,{_zz_567,_zz_568}}; + assign _zz_556 = 4'b0000; + assign _zz_557 = (_zz_569 != 1'b0); + assign _zz_558 = (_zz_570 != _zz_571); + assign _zz_559 = {_zz_572,{_zz_573,_zz_574}}; + assign _zz_560 = 32'h00000050; + assign _zz_561 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_562 = 32'h00000004; + assign _zz_563 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_564 = 32'h0; + assign _zz_565 = 32'h00006014; + assign _zz_566 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_567 = ((decode_INSTRUCTION & _zz_575) == 32'h0); + assign _zz_568 = {(_zz_576 == _zz_577),(_zz_578 == _zz_579)}; + assign _zz_569 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_570 = {(_zz_580 == _zz_581),{_zz_582,_zz_583}}; + assign _zz_571 = 3'b000; + assign _zz_572 = ({_zz_584,_zz_93} != 2'b00); + assign _zz_573 = ({_zz_585,_zz_586} != 2'b00); + assign _zz_574 = (_zz_587 != 1'b0); + assign _zz_575 = 32'h00000018; + assign _zz_576 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_577 = 32'h00002000; + assign _zz_578 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_579 = 32'h00001000; + assign _zz_580 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_581 = 32'h00000040; + assign _zz_582 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_583 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_584 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_585 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_586 = _zz_93; + assign _zz_587 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_588 = execute_INSTRUCTION[31]; + assign _zz_589 = execute_INSTRUCTION[31]; + assign _zz_590 = execute_INSTRUCTION[7]; + assign _zz_591 = 32'h0; always @ (posedge clk) begin - if(_zz_378) begin - _zz_235 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_387) begin + _zz_244 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_379) begin - _zz_236 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_388) begin + _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1760,13 +1775,13 @@ module VexRiscv_inner ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_207 ), //i - .io_cpu_prefetch_isValid (_zz_208 ), //i + .io_flush (_zz_216 ), //i + .io_cpu_prefetch_isValid (_zz_217 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_209 ), //i - .io_cpu_fetch_isStuck (_zz_210 ), //i - .io_cpu_fetch_isRemoved (_zz_211 ), //i + .io_cpu_fetch_isValid (_zz_218 ), //i + .io_cpu_fetch_isStuck (_zz_219 ), //i + .io_cpu_fetch_isRemoved (_zz_220 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1778,8 +1793,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_212 ), //i - .io_cpu_decode_isStuck (_zz_213 ), //i + .io_cpu_decode_isValid (_zz_221 ), //i + .io_cpu_decode_isStuck (_zz_222 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1787,8 +1802,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_214 ), //i - .io_cpu_fill_valid (_zz_215 ), //i + .io_cpu_decode_isUser (_zz_223 ), //i + .io_cpu_fill_valid (_zz_224 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1797,56 +1812,56 @@ module VexRiscv_inner ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_171[2:0] ), //i + ._zz_9 (_zz_177[2:0] ), //i ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_216 ), //i - .io_cpu_execute_address (_zz_217[31:0] ), //i + .io_cpu_execute_isValid (_zz_225 ), //i + .io_cpu_execute_address (_zz_226[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_87[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_memory_isValid (_zz_218 ), //i + .io_cpu_memory_isValid (_zz_227 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_219[31:0] ), //i + .io_cpu_memory_address (_zz_228[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_220 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_229 ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_221 ), //i + .io_cpu_writeBack_isValid (_zz_230 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_222 ), //i + .io_cpu_writeBack_isUser (_zz_231 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_223[31:0] ), //i + .io_cpu_writeBack_address (_zz_232[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_224 ), //i - .io_cpu_writeBack_fence_SR (_zz_225 ), //i - .io_cpu_writeBack_fence_SO (_zz_226 ), //i - .io_cpu_writeBack_fence_SI (_zz_227 ), //i - .io_cpu_writeBack_fence_PW (_zz_228 ), //i - .io_cpu_writeBack_fence_PR (_zz_229 ), //i - .io_cpu_writeBack_fence_PO (_zz_230 ), //i - .io_cpu_writeBack_fence_PI (_zz_231 ), //i - .io_cpu_writeBack_fence_FM (_zz_232[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_233 ), //i + .io_cpu_writeBack_fence_SR (_zz_234 ), //i + .io_cpu_writeBack_fence_SO (_zz_235 ), //i + .io_cpu_writeBack_fence_SI (_zz_236 ), //i + .io_cpu_writeBack_fence_PW (_zz_237 ), //i + .io_cpu_writeBack_fence_PR (_zz_238 ), //i + .io_cpu_writeBack_fence_PO (_zz_239 ), //i + .io_cpu_writeBack_fence_PI (_zz_240 ), //i + .io_cpu_writeBack_fence_FM (_zz_241[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_233 ), //i + .io_cpu_flush_valid (_zz_242 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_234 ), //i + .io_mem_cmd_ready (_zz_243 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1862,18 +1877,18 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_380) + case(_zz_389) 2'b00 : begin - _zz_237 = DBusCachedPlugin_redoBranch_payload; + _zz_246 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_237 = CsrPlugin_jumpInterface_payload; + _zz_246 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_237 = BranchPlugin_jumpInterface_payload; + _zz_246 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_237 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_246 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2628,7 +2643,7 @@ module VexRiscv_inner ( end `endif - assign memory_MUL_LOW = ($signed(_zz_279) + $signed(_zz_287)); + assign memory_MUL_LOW = ($signed(_zz_288) + $signed(_zz_296)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2637,42 +2652,42 @@ module VexRiscv_inner ( assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_289; + assign execute_SHIFT_RIGHT = _zz_298; assign execute_REGFILE_WRITE_DATA = _zz_107; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_217[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_226[1 : 0]; assign decode_DO_EBREAK = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_291[0]; - assign decode_IS_RS1_SIGNED = _zz_292[0]; - assign decode_IS_DIV = _zz_293[0]; + assign decode_IS_RS2_SIGNED = _zz_300[0]; + assign decode_IS_RS1_SIGNED = _zz_301[0]; + assign decode_IS_DIV = _zz_302[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_294[0]; + assign decode_IS_MUL = _zz_303[0]; assign decode_CfuPlugin_CFU_ENCODING = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_295[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_304[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_296[0]; + assign decode_IS_CSR = _zz_305[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_297[0]; - assign decode_MEMORY_MANAGMENT = _zz_298[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_306[0]; + assign decode_MEMORY_MANAGMENT = _zz_307[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_299[0]; + assign decode_MEMORY_WR = _zz_308[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_300[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_301[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_309[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_310[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2686,7 +2701,7 @@ module VexRiscv_inner ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_302[0]; + assign decode_IS_EBREAK = _zz_311[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2713,11 +2728,11 @@ module VexRiscv_inner ( assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_COND_RESULT = _zz_129; assign execute_BRANCH_CTRL = _zz_34; - assign decode_RS2_USE = _zz_303[0]; - assign decode_RS1_USE = _zz_304[0]; + assign decode_RS2_USE = _zz_312[0]; + assign decode_RS1_USE = _zz_313[0]; always @ (*) begin _zz_35 = execute_REGFILE_WRITE_DATA; - if(_zz_238)begin + if(_zz_247)begin _zz_35 = execute_CsrPlugin_readData; end end @@ -2735,21 +2750,21 @@ module VexRiscv_inner ( decode_RS2 = _zz_120; end end - if(_zz_239)begin - if(_zz_240)begin + if(_zz_248)begin + if(_zz_249)begin if(_zz_122)begin decode_RS2 = _zz_55; end end end - if(_zz_241)begin + if(_zz_250)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_124)begin decode_RS2 = _zz_36; end end end - if(_zz_242)begin + if(_zz_251)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_126)begin decode_RS2 = _zz_35; @@ -2765,21 +2780,21 @@ module VexRiscv_inner ( decode_RS1 = _zz_120; end end - if(_zz_239)begin - if(_zz_240)begin + if(_zz_248)begin + if(_zz_249)begin if(_zz_121)begin decode_RS1 = _zz_55; end end end - if(_zz_241)begin + if(_zz_250)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_123)begin decode_RS1 = _zz_36; end end end - if(_zz_242)begin + if(_zz_251)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_125)begin decode_RS1 = _zz_35; @@ -2806,7 +2821,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_36 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_243)begin + if(_zz_252)begin _zz_36 = memory_DivPlugin_div_result; end end @@ -2819,8 +2834,8 @@ module VexRiscv_inner ( assign _zz_39 = execute_PC; assign execute_SRC2_CTRL = _zz_40; assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_305[0]; - assign decode_SRC_ADD_ZERO = _zz_306[0]; + assign decode_SRC_USE_SUB_LESS = _zz_314[0]; + assign decode_SRC_ADD_ZERO = _zz_315[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_42; @@ -2838,25 +2853,25 @@ module VexRiscv_inner ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_307[0]; + decode_REGFILE_WRITE_VALID = _zz_316[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_381) == 32'h00000003),{(_zz_382 == _zz_383),{_zz_384,{_zz_385,_zz_386}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_390) == 32'h00000003),{(_zz_391 == _zz_392),{_zz_393,{_zz_394,_zz_395}}}}}}} != 22'h0); always @ (*) begin _zz_55 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_55 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_278) + case(_zz_287) 2'b00 : begin - _zz_55 = _zz_353; + _zz_55 = _zz_362; end default : begin - _zz_55 = _zz_354; + _zz_55 = _zz_363; end endcase end @@ -2875,32 +2890,32 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_308[0]; - assign decode_FLUSH_ALL = _zz_309[0]; + assign decode_MEMORY_ENABLE = _zz_317[0]; + assign decode_FLUSH_ALL = _zz_318[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_244)begin + if(_zz_253)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_245)begin + if(_zz_254)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_246)begin + if(_zz_255)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_247)begin + if(_zz_256)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2929,7 +2944,7 @@ module VexRiscv_inner ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_171) + case(_zz_177) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2953,7 +2968,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_248)begin + if(_zz_257)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2967,25 +2982,25 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_248)begin + if(_zz_257)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_233 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_242 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end if(((dataCache_1_io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_249)begin + if(_zz_258)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_238)begin + if(_zz_247)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2997,7 +3012,7 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_250)begin + if(_zz_259)begin execute_arbitration_haltByOther = 1'b1; end end @@ -3014,8 +3029,8 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_250)begin - if(_zz_251)begin + if(_zz_259)begin + if(_zz_260)begin execute_arbitration_flushIt = 1'b1; end end @@ -3026,8 +3041,8 @@ module VexRiscv_inner ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_250)begin - if(_zz_251)begin + if(_zz_259)begin + if(_zz_260)begin execute_arbitration_flushNext = 1'b1; end end @@ -3040,7 +3055,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_243)begin + if(_zz_252)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3050,7 +3065,7 @@ module VexRiscv_inner ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_252)begin + if(_zz_261)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3064,7 +3079,7 @@ module VexRiscv_inner ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_252)begin + if(_zz_261)begin memory_arbitration_flushNext = 1'b1; end end @@ -3102,10 +3117,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_253)begin + if(_zz_262)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_254)begin + if(_zz_263)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3119,21 +3134,21 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_253)begin + if(_zz_262)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_254)begin + if(_zz_263)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_250)begin - if(_zz_251)begin + if(_zz_259)begin + if(_zz_260)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_255)begin + if(_zz_264)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3154,7 +3169,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_249)begin + if(_zz_258)begin CsrPlugin_inWfi = 1'b1; end end @@ -3168,21 +3183,21 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_253)begin + if(_zz_262)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_254)begin + if(_zz_263)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_253)begin + if(_zz_262)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_254)begin - case(_zz_256) + if(_zz_263)begin + case(_zz_265) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3216,11 +3231,11 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_60 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_61 = (_zz_60 & (~ _zz_310)); + assign _zz_61 = (_zz_60 & (~ _zz_319)); assign _zz_62 = _zz_61[3]; assign _zz_63 = (_zz_61[1] || _zz_62); assign _zz_64 = (_zz_61[2] || _zz_62); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_237; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_246; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3240,7 +3255,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_312); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_321); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3332,7 +3347,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_171) + case(_zz_177) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3344,7 +3359,7 @@ module VexRiscv_inner ( endcase end - assign _zz_74 = _zz_313[11]; + assign _zz_74 = _zz_322[11]; always @ (*) begin _zz_75[18] = _zz_74; _zz_75[17] = _zz_74; @@ -3368,13 +3383,13 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_314[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_323[31])); if(_zz_80)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_76 = _zz_315[19]; + assign _zz_76 = _zz_324[19]; always @ (*) begin _zz_77[10] = _zz_76; _zz_77[9] = _zz_76; @@ -3389,7 +3404,7 @@ module VexRiscv_inner ( _zz_77[0] = _zz_76; end - assign _zz_78 = _zz_316[11]; + assign _zz_78 = _zz_325[11]; always @ (*) begin _zz_79[18] = _zz_78; _zz_79[17] = _zz_78; @@ -3415,16 +3430,16 @@ module VexRiscv_inner ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_80 = _zz_317[1]; + _zz_80 = _zz_326[1]; end default : begin - _zz_80 = _zz_318[1]; + _zz_80 = _zz_327[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_81 = _zz_319[19]; + assign _zz_81 = _zz_328[19]; always @ (*) begin _zz_82[10] = _zz_81; _zz_82[9] = _zz_81; @@ -3439,7 +3454,7 @@ module VexRiscv_inner ( _zz_82[0] = _zz_81; end - assign _zz_83 = _zz_320[11]; + assign _zz_83 = _zz_329[11]; always @ (*) begin _zz_84[18] = _zz_83; _zz_84[17] = _zz_83; @@ -3462,7 +3477,7 @@ module VexRiscv_inner ( _zz_84[0] = _zz_83; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_82,{{{_zz_399,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_84,{{{_zz_400,_zz_401},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_82,{{{_zz_408,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_84,{{{_zz_409,_zz_410},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3471,52 +3486,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_208 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_209 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_210 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_209; + assign _zz_217 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_219 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_218; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_212 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_213 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_214 = (CsrPlugin_privilege == 2'b00); + assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_222 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_223 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_247)begin + if(_zz_256)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_245)begin + if(_zz_254)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_215 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_245)begin - _zz_215 = 1'b1; + _zz_224 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_254)begin + _zz_224 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_246)begin + if(_zz_255)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_244)begin + if(_zz_253)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_246)begin + if(_zz_255)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_244)begin + if(_zz_253)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3526,9 +3541,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_207 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_216 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_234 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_243 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3555,8 +3570,8 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_216 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_217 = execute_SRC_ADD; + assign _zz_225 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_226 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3571,27 +3586,27 @@ module VexRiscv_inner ( endcase end - assign _zz_233 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_218 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_219 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_218; + assign _zz_242 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_227 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_228 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_227; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_219; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_228; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_220 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_229 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_59 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_220 = 1'b1; + _zz_229 = 1'b1; end end - assign _zz_221 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_222 = (CsrPlugin_privilege == 2'b00); - assign _zz_223 = writeBack_REGFILE_WRITE_DATA; + assign _zz_230 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_231 = (CsrPlugin_privilege == 2'b00); + assign _zz_232 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_257)begin + if(_zz_266)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3601,7 +3616,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_257)begin + if(_zz_266)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3620,12 +3635,12 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_257)begin + if(_zz_266)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_321}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_330}; end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_322}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_331}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); @@ -3701,7 +3716,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_276) + case(_zz_285) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_89; end @@ -3735,7 +3750,7 @@ module VexRiscv_inner ( assign _zz_95 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_96 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); assign _zz_97 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_92 = {(((decode_INSTRUCTION & _zz_402) == 32'h00100050) != 1'b0),{(_zz_97 != 1'b0),{(_zz_97 != 1'b0),{(_zz_403 != _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; + assign _zz_92 = {(((decode_INSTRUCTION & _zz_411) == 32'h00100050) != 1'b0),{(_zz_97 != 1'b0),{(_zz_97 != 1'b0),{(_zz_412 != _zz_413),{_zz_414,{_zz_415,_zz_416}}}}}}; assign _zz_98 = _zz_92[2 : 1]; assign _zz_54 = _zz_98; assign _zz_99 = _zz_92[7 : 6]; @@ -3757,8 +3772,8 @@ module VexRiscv_inner ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_235; - assign decode_RegFilePlugin_rs2Data = _zz_236; + assign decode_RegFilePlugin_rs1Data = _zz_244; + assign decode_RegFilePlugin_rs2Data = _zz_245; always @ (*) begin lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); if(_zz_106)begin @@ -3788,7 +3803,7 @@ module VexRiscv_inner ( _zz_107 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_107 = {31'd0, _zz_323}; + _zz_107 = {31'd0, _zz_332}; end default : begin _zz_107 = execute_SRC_ADD_SUB; @@ -3802,18 +3817,18 @@ module VexRiscv_inner ( _zz_108 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_108 = {29'd0, _zz_324}; + _zz_108 = {29'd0, _zz_333}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_108 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_108 = {27'd0, _zz_325}; + _zz_108 = {27'd0, _zz_334}; end endcase end - assign _zz_109 = _zz_326[11]; + assign _zz_109 = _zz_335[11]; always @ (*) begin _zz_110[19] = _zz_109; _zz_110[18] = _zz_109; @@ -3837,7 +3852,7 @@ module VexRiscv_inner ( _zz_110[0] = _zz_109; end - assign _zz_111 = _zz_327[11]; + assign _zz_111 = _zz_336[11]; always @ (*) begin _zz_112[19] = _zz_111; _zz_112[18] = _zz_111; @@ -3879,7 +3894,7 @@ module VexRiscv_inner ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_328; + execute_SrcPlugin_addSub = _zz_337; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3960,22 +3975,22 @@ module VexRiscv_inner ( always @ (*) begin _zz_116 = 1'b0; - if(_zz_258)begin - if(_zz_259)begin + if(_zz_267)begin + if(_zz_268)begin if(_zz_121)begin _zz_116 = 1'b1; end end end - if(_zz_260)begin - if(_zz_261)begin + if(_zz_269)begin + if(_zz_270)begin if(_zz_123)begin _zz_116 = 1'b1; end end end - if(_zz_262)begin - if(_zz_263)begin + if(_zz_271)begin + if(_zz_272)begin if(_zz_125)begin _zz_116 = 1'b1; end @@ -3988,22 +4003,22 @@ module VexRiscv_inner ( always @ (*) begin _zz_117 = 1'b0; - if(_zz_258)begin - if(_zz_259)begin + if(_zz_267)begin + if(_zz_268)begin if(_zz_122)begin _zz_117 = 1'b1; end end end - if(_zz_260)begin - if(_zz_261)begin + if(_zz_269)begin + if(_zz_270)begin if(_zz_124)begin _zz_117 = 1'b1; end end end - if(_zz_262)begin - if(_zz_263)begin + if(_zz_271)begin + if(_zz_272)begin if(_zz_126)begin _zz_117 = 1'b1; end @@ -4051,7 +4066,7 @@ module VexRiscv_inner ( endcase end - assign _zz_130 = _zz_335[11]; + assign _zz_130 = _zz_344[11]; always @ (*) begin _zz_131[19] = _zz_130; _zz_131[18] = _zz_130; @@ -4075,7 +4090,7 @@ module VexRiscv_inner ( _zz_131[0] = _zz_130; end - assign _zz_132 = _zz_336[19]; + assign _zz_132 = _zz_345[19]; always @ (*) begin _zz_133[10] = _zz_132; _zz_133[9] = _zz_132; @@ -4090,7 +4105,7 @@ module VexRiscv_inner ( _zz_133[0] = _zz_132; end - assign _zz_134 = _zz_337[11]; + assign _zz_134 = _zz_346[11]; always @ (*) begin _zz_135[18] = _zz_134; _zz_135[17] = _zz_134; @@ -4116,13 +4131,13 @@ module VexRiscv_inner ( always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_136 = (_zz_338[1] ^ execute_RS1[1]); + _zz_136 = (_zz_347[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_136 = _zz_339[1]; + _zz_136 = _zz_348[1]; end default : begin - _zz_136 = _zz_340[1]; + _zz_136 = _zz_349[1]; end endcase end @@ -4139,7 +4154,7 @@ module VexRiscv_inner ( endcase end - assign _zz_137 = _zz_341[11]; + assign _zz_137 = _zz_350[11]; always @ (*) begin _zz_138[19] = _zz_137; _zz_138[18] = _zz_137; @@ -4169,15 +4184,15 @@ module VexRiscv_inner ( execute_BranchPlugin_branch_src2 = {_zz_138,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_140,{{{_zz_579,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_142,{{{_zz_580,_zz_581},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_140,{{{_zz_588,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_142,{{{_zz_589,_zz_590},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_344}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_353}; end end endcase end - assign _zz_139 = _zz_342[19]; + assign _zz_139 = _zz_351[19]; always @ (*) begin _zz_140[10] = _zz_139; _zz_140[9] = _zz_139; @@ -4192,7 +4207,7 @@ module VexRiscv_inner ( _zz_140[0] = _zz_139; end - assign _zz_141 = _zz_343[11]; + assign _zz_141 = _zz_352[11]; always @ (*) begin _zz_142[18] = _zz_141; _zz_142[17] = _zz_141; @@ -4235,12 +4250,12 @@ module VexRiscv_inner ( assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); assign _zz_146 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_147 = _zz_345[0]; + assign _zz_147 = _zz_354[0]; assign _zz_148 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_149 = _zz_347[0]; + assign _zz_149 = _zz_356[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_248)begin + if(_zz_257)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4260,7 +4275,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_252)begin + if(_zz_261)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4449,6 +4464,30 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end + if(execute_CsrPlugin_csr_2830)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end if(execute_CsrPlugin_csr_3008)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4476,20 +4515,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_264)begin + if(_zz_273)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_265)begin + if(_zz_274)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_264)begin + if(_zz_273)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_265)begin + if(_zz_274)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4508,7 +4547,7 @@ module VexRiscv_inner ( assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_277) + case(_zz_286) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4521,45 +4560,45 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_349; + assign execute_CfuPlugin_functionsIds_0 = _zz_358; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_160 = _zz_350[11]; - always @ (*) begin - _zz_161[19] = _zz_160; - _zz_161[18] = _zz_160; - _zz_161[17] = _zz_160; - _zz_161[16] = _zz_160; - _zz_161[15] = _zz_160; - _zz_161[14] = _zz_160; - _zz_161[13] = _zz_160; - _zz_161[12] = _zz_160; - _zz_161[11] = _zz_160; - _zz_161[10] = _zz_160; - _zz_161[9] = _zz_160; - _zz_161[8] = _zz_160; - _zz_161[7] = _zz_160; - _zz_161[6] = _zz_160; - _zz_161[5] = _zz_160; - _zz_161[4] = _zz_160; - _zz_161[3] = _zz_160; - _zz_161[2] = _zz_160; - _zz_161[1] = _zz_160; - _zz_161[0] = _zz_160; + assign _zz_166 = _zz_359[11]; + always @ (*) begin + _zz_167[19] = _zz_166; + _zz_167[18] = _zz_166; + _zz_167[17] = _zz_166; + _zz_167[16] = _zz_166; + _zz_167[15] = _zz_166; + _zz_167[14] = _zz_166; + _zz_167[13] = _zz_166; + _zz_167[12] = _zz_166; + _zz_167[11] = _zz_166; + _zz_167[10] = _zz_166; + _zz_167[9] = _zz_166; + _zz_167[8] = _zz_166; + _zz_167[7] = _zz_166; + _zz_167[6] = _zz_166; + _zz_167[5] = _zz_166; + _zz_167[4] = _zz_166; + _zz_167[3] = _zz_166; + _zz_167[2] = _zz_166; + _zz_167[1] = _zz_166; + _zz_167[0] = _zz_166; end always @ (*) begin case(execute_CfuPlugin_CFU_ENCODING) `Input2Kind_defaultEncoding_RS : begin - _zz_162 = execute_RS2; + _zz_168 = execute_RS2; end default : begin - _zz_162 = {_zz_161,execute_INSTRUCTION[31 : 20]}; + _zz_168 = {_zz_167,execute_INSTRUCTION[31 : 20]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_162; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_168; assign CfuPlugin_bus_rsp_ready = ((1'b1 && (! memory_CfuPlugin_rsp_valid)) || memory_CfuPlugin_rsp_ready); assign memory_CfuPlugin_rsp_valid = CfuPlugin_bus_rsp_m2sPipe_rValid; assign memory_CfuPlugin_rsp_payload_response_ok = CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; @@ -4585,7 +4624,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_266) + case(_zz_275) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4599,7 +4638,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_266) + case(_zz_275) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4618,12 +4657,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_351) + $signed(_zz_352)); + assign writeBack_MulPlugin_result = ($signed(_zz_360) + $signed(_zz_361)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_243)begin - if(_zz_267)begin + if(_zz_252)begin + if(_zz_276)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4631,7 +4670,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_268)begin + if(_zz_277)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4642,32 +4681,32 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_356); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_365); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_163 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_163[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_357); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_358 : _zz_359); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_360[31:0]; - assign _zz_164 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_165 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_166 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_169 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_169[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_366); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_367 : _zz_368); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_369[31:0]; + assign _zz_170 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_171 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_172 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_167[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_167[31 : 0] = execute_RS1; + _zz_173[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_173[31 : 0] = execute_RS1; end - assign _zz_169 = (_zz_168 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_169 != 32'h0); + assign _zz_175 = (_zz_174 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_175 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_269) + case(_zz_278) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4681,7 +4720,7 @@ module VexRiscv_inner ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_170))begin + if((! _zz_176))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4693,7 +4732,7 @@ module VexRiscv_inner ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_269) + case(_zz_278) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4759,7 +4798,7 @@ module VexRiscv_inner ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_171) + case(_zz_177) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4769,237 +4808,258 @@ module VexRiscv_inner ( end always @ (*) begin - _zz_172 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_172[12 : 0] = 13'h1000; - _zz_172[25 : 20] = 6'h20; + _zz_178[12 : 0] = 13'h1000; + _zz_178[25 : 20] = 6'h20; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_173[3 : 0] = 4'b1011; + _zz_179[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_174[4 : 0] = 5'h16; + _zz_180[4 : 0] = 5'h16; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_175[5 : 0] = 6'h21; + _zz_181[5 : 0] = 6'h21; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_176[31 : 30] = CsrPlugin_misa_base; - _zz_176[25 : 0] = CsrPlugin_misa_extensions; + _zz_182[31 : 30] = CsrPlugin_misa_base; + _zz_182[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_177[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_177[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_177[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_183[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_183[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_183[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_178[11 : 11] = CsrPlugin_mip_MEIP; - _zz_178[7 : 7] = CsrPlugin_mip_MTIP; - _zz_178[3 : 3] = CsrPlugin_mip_MSIP; + _zz_184[11 : 11] = CsrPlugin_mip_MEIP; + _zz_184[7 : 7] = CsrPlugin_mip_MTIP; + _zz_184[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_179[11 : 11] = CsrPlugin_mie_MEIE; - _zz_179[7 : 7] = CsrPlugin_mie_MTIE; - _zz_179[3 : 3] = CsrPlugin_mie_MSIE; + _zz_185[11 : 11] = CsrPlugin_mie_MEIE; + _zz_185[7 : 7] = CsrPlugin_mie_MTIE; + _zz_185[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_180[31 : 2] = CsrPlugin_mtvec_base; - _zz_180[1 : 0] = CsrPlugin_mtvec_mode; + _zz_186[31 : 2] = CsrPlugin_mtvec_base; + _zz_186[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_181[31 : 0] = CsrPlugin_mepc; + _zz_187[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_182[31 : 0] = CsrPlugin_mscratch; + _zz_188[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_183[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_183[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_189[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_189[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_184[31 : 0] = CsrPlugin_mtval; + _zz_190[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_185[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_191[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_186[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_192[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_187[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_193[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_188[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_194[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_189[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_195[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_190[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_196[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_2820)begin - _zz_191[31 : 0] = _zz_150; + _zz_197[31 : 0] = _zz_150; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_2822)begin - _zz_192[31 : 0] = _zz_152; + _zz_198[31 : 0] = _zz_152; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_199 = 32'h0; if(execute_CsrPlugin_csr_2824)begin - _zz_193[31 : 0] = _zz_154; + _zz_199[31 : 0] = _zz_154; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_200 = 32'h0; if(execute_CsrPlugin_csr_2826)begin - _zz_194[31 : 0] = _zz_156; + _zz_200[31 : 0] = _zz_156; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_201 = 32'h0; if(execute_CsrPlugin_csr_2828)begin - _zz_195[31 : 0] = _zz_158; + _zz_201[31 : 0] = _zz_158; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_202 = 32'h0; + if(execute_CsrPlugin_csr_2830)begin + _zz_202[31 : 0] = _zz_160; + end + end + + always @ (*) begin + _zz_203 = 32'h0; + if(execute_CsrPlugin_csr_2832)begin + _zz_203[31 : 0] = _zz_162; + end + end + + always @ (*) begin + _zz_204 = 32'h0; + if(execute_CsrPlugin_csr_2834)begin + _zz_204[31 : 0] = _zz_164; + end + end + + always @ (*) begin + _zz_205 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_196[31 : 0] = _zz_168; + _zz_205[31 : 0] = _zz_174; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_206 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_197[31 : 0] = _zz_169; + _zz_206[31 : 0] = _zz_175; end end - assign execute_CsrPlugin_readData = (((((_zz_172 | _zz_173) | (_zz_174 | _zz_175)) | ((_zz_582 | _zz_176) | (_zz_177 | _zz_178))) | (((_zz_179 | _zz_180) | (_zz_181 | _zz_182)) | ((_zz_183 | _zz_184) | (_zz_185 | _zz_186)))) | ((((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194))) | ((_zz_195 | _zz_196) | _zz_197))); - assign iBusWishbone_ADR = {_zz_377,_zz_198}; - assign iBusWishbone_CTI = ((_zz_198 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_178 | _zz_179) | (_zz_180 | _zz_181)) | ((_zz_591 | _zz_182) | (_zz_183 | _zz_184))) | (((_zz_185 | _zz_186) | (_zz_187 | _zz_188)) | ((_zz_189 | _zz_190) | (_zz_191 | _zz_192)))) | ((((_zz_193 | _zz_194) | (_zz_195 | _zz_196)) | ((_zz_197 | _zz_198) | (_zz_199 | _zz_200))) | (((_zz_201 | _zz_202) | (_zz_203 | _zz_204)) | (_zz_205 | _zz_206)))); + assign iBusWishbone_ADR = {_zz_386,_zz_207}; + assign iBusWishbone_CTI = ((_zz_207 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_270)begin + if(_zz_279)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_270)begin + if(_zz_279)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_199; + assign iBus_rsp_valid = _zz_208; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_205 = (dBus_cmd_payload_length != 3'b000); - assign _zz_201 = dBus_cmd_valid; - assign _zz_203 = dBus_cmd_payload_wr; - assign _zz_204 = (_zz_200 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_202 && (_zz_203 || _zz_204)); - assign dBusWishbone_ADR = ((_zz_205 ? {{dBus_cmd_payload_address[31 : 5],_zz_200},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_205 ? (_zz_204 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_214 = (dBus_cmd_payload_length != 3'b000); + assign _zz_210 = dBus_cmd_valid; + assign _zz_212 = dBus_cmd_payload_wr; + assign _zz_213 = (_zz_209 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_211 && (_zz_212 || _zz_213)); + assign dBusWishbone_ADR = ((_zz_214 ? {{dBus_cmd_payload_address[31 : 5],_zz_209},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_214 ? (_zz_213 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_203 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_203; + assign dBusWishbone_SEL = (_zz_212 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_212; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_202 = (_zz_201 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_201; - assign dBusWishbone_STB = _zz_201; - assign dBus_rsp_valid = _zz_206; + assign _zz_211 = (_zz_210 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_210; + assign dBusWishbone_STB = _zz_210; + assign dBus_rsp_valid = _zz_215; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5046,18 +5106,18 @@ module VexRiscv_inner ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_m2sPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_168 <= 32'h0; + _zz_174 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_171 <= 3'b000; + _zz_177 <= 3'b000; memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; memory_to_writeBack_INSTRUCTION <= 32'h0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_198 <= 3'b000; - _zz_199 <= 1'b0; - _zz_200 <= 3'b000; - _zz_206 <= 1'b0; + _zz_207 <= 3'b000; + _zz_208 <= 1'b0; + _zz_209 <= 3'b000; + _zz_215 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5138,7 +5198,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_271)begin + if(_zz_280)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5170,14 +5230,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_272)begin - if(_zz_273)begin + if(_zz_281)begin + if(_zz_282)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_274)begin + if(_zz_283)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_275)begin + if(_zz_284)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5202,7 +5262,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_253)begin + if(_zz_262)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5213,8 +5273,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_254)begin - case(_zz_256) + if(_zz_263)begin + case(_zz_265) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5268,25 +5328,25 @@ module VexRiscv_inner ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_171) + case(_zz_177) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_171 <= 3'b001; + _zz_177 <= 3'b001; end end 3'b001 : begin - _zz_171 <= 3'b010; + _zz_177 <= 3'b010; end 3'b010 : begin - _zz_171 <= 3'b011; + _zz_177 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_171 <= 3'b100; + _zz_177 <= 3'b100; end end 3'b100 : begin - _zz_171 <= 3'b000; + _zz_177 <= 3'b000; end default : begin end @@ -5300,35 +5360,35 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_370[0]; - CsrPlugin_mstatus_MIE <= _zz_371[0]; + CsrPlugin_mstatus_MPIE <= _zz_379[0]; + CsrPlugin_mstatus_MIE <= _zz_380[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_373[0]; - CsrPlugin_mie_MTIE <= _zz_374[0]; - CsrPlugin_mie_MSIE <= _zz_375[0]; + CsrPlugin_mie_MEIE <= _zz_382[0]; + CsrPlugin_mie_MTIE <= _zz_383[0]; + CsrPlugin_mie_MSIE <= _zz_384[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_174 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_270)begin + if(_zz_279)begin if(iBusWishbone_ACK)begin - _zz_198 <= (_zz_198 + 3'b001); + _zz_207 <= (_zz_207 + 3'b001); end end - _zz_199 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_201 && _zz_202))begin - _zz_200 <= (_zz_200 + 3'b001); - if(_zz_204)begin - _zz_200 <= 3'b000; + _zz_208 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_210 && _zz_211))begin + _zz_209 <= (_zz_209 + 3'b001); + if(_zz_213)begin + _zz_209 <= 3'b000; end end - _zz_206 <= ((_zz_201 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_215 <= ((_zz_210 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5342,7 +5402,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_271)begin + if(_zz_280)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5369,7 +5429,7 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_248)begin + if(_zz_257)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_147 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_147 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end @@ -5377,7 +5437,7 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_252)begin + if(_zz_261)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); end @@ -5385,21 +5445,21 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_272)begin - if(_zz_273)begin + if(_zz_281)begin + if(_zz_282)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_274)begin + if(_zz_283)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_275)begin + if(_zz_284)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_253)begin + if(_zz_262)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5428,6 +5488,15 @@ module VexRiscv_inner ( if(_zz_159[0])begin _zz_158 <= (_zz_158 + 32'h00000001); end + if(_zz_161[0])begin + _zz_160 <= (_zz_160 + 32'h00000001); + end + if(_zz_163[0])begin + _zz_162 <= (_zz_162 + 32'h00000001); + end + if(_zz_165[0])begin + _zz_164 <= (_zz_164 + 32'h00000001); + end if(CfuPlugin_bus_rsp_ready)begin CfuPlugin_bus_rsp_m2sPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; @@ -5438,20 +5507,20 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_243)begin - if(_zz_267)begin + if(_zz_252)begin + if(_zz_276)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_361[31:0]; + memory_DivPlugin_div_result <= _zz_370[31:0]; end end end - if(_zz_268)begin + if(_zz_277)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_166 ? (~ _zz_167) : _zz_167) + _zz_367); - memory_DivPlugin_rs2 <= ((_zz_165 ? (~ execute_RS2) : execute_RS2) + _zz_369); - memory_DivPlugin_div_needRevert <= ((_zz_166 ^ (_zz_165 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_172 ? (~ _zz_173) : _zz_173) + _zz_376); + memory_DivPlugin_rs2 <= ((_zz_171 ? (~ execute_RS2) : execute_RS2) + _zz_378); + memory_DivPlugin_div_needRevert <= ((_zz_172 ^ (_zz_171 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5733,6 +5802,24 @@ module VexRiscv_inner ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end @@ -5741,7 +5828,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_372[0]; + CsrPlugin_mip_MSIP <= _zz_381[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5762,7 +5849,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_376[0]; + CsrPlugin_mcause_interrupt <= _zz_385[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5841,6 +5928,36 @@ module VexRiscv_inner ( _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end + if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + end + end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end @@ -5855,8 +5972,8 @@ module VexRiscv_inner ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_55; end - _zz_170 <= debug_bus_cmd_payload_address[2]; - if(_zz_250)begin + _zz_176 <= debug_bus_cmd_payload_address[2]; + if(_zz_259)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -5874,7 +5991,7 @@ module VexRiscv_inner ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_269) + case(_zz_278) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -5902,13 +6019,13 @@ module VexRiscv_inner ( end endcase end - if(_zz_250)begin - if(_zz_251)begin + if(_zz_259)begin + if(_zz_260)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_255)begin + if(_zz_264)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end From 59f011da0a5ef9d5ed94ef2308e3df290d596e66 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Mon, 11 Jan 2021 23:22:54 -0800 Subject: [PATCH 06/30] Bump both I$, D$ from 4k to 8k. Both L1 caches are changed from 4k direct-mapped to 8k 2-way associative. The change to 2-way was required since each "way" can be 4k max. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 4 +- .../verilog/VexRiscv_FullCfu.v | 616 +++++++++++------ .../verilog/VexRiscv_FullCfu.yaml | 2 +- .../verilog/VexRiscv_FullCfuDebug.v | 628 ++++++++++++------ .../verilog/VexRiscv_FullCfuDebug.yaml | 2 +- .../main/scala/vexriscv/GenCoreDefault.scala | 4 +- 6 files changed, 864 insertions(+), 392 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index c0e4b56..a95cd5f 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -34,14 +34,14 @@ VexRiscv_FullDebug.v: $(SRC) # CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfu" + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfu" sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v /bin/mv tmp.v $@ ./genWrapper.py $@ > wrap$@ # CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfuDebug.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfuDebug" + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfuDebug" sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v /bin/mv tmp.v $@ ./genWrapper.py $@ > wrap$@ diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index e78ca25..f8090d5 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : 07a72e20035b64cf586cbf04df799cb4bf961010 +// Generator : SpinalHDL v1.4.2 git head : f022529bb419c7a04f9ba1b61e931127b7220919 // Component : VexRiscv -// Git hash : 07a72e20035b64cf586cbf04df799cb4bf961010 +// Git hash : f022529bb419c7a04f9ba1b61e931127b7220919 `define Input2Kind_defaultEncoding_type [0:0] @@ -5801,37 +5801,42 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_19; + reg [31:0] _zz_20; + reg [21:0] _zz_21; + reg [31:0] _zz_22; + wire _zz_23; + wire _zz_24; + wire _zz_25; + wire _zz_26; + wire _zz_27; + wire _zz_28; + wire _zz_29; + wire [0:0] _zz_30; + wire [0:0] _zz_31; + wire [0:0] _zz_32; + wire [0:0] _zz_33; + wire [0:0] _zz_34; + wire [0:0] _zz_35; + wire [2:0] _zz_36; + wire [2:0] _zz_37; + wire [21:0] _zz_38; + wire [21:0] _zz_39; reg _zz_1; reg _zz_2; + reg _zz_3; + reg _zz_4; wire haltCpu; reg tagsReadCmd_valid; reg [6:0] tagsReadCmd_payload; reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; + reg [1:0] tagsWriteCmd_payload_way; reg [6:0] tagsWriteCmd_payload_address; reg tagsWriteCmd_payload_data_valid; reg tagsWriteCmd_payload_data_error; reg [19:0] tagsWriteCmd_payload_data_address; reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; + reg [1:0] tagsWriteLastCmd_payload_way; reg [6:0] tagsWriteLastCmd_payload_address; reg tagsWriteLastCmd_payload_data_valid; reg tagsWriteLastCmd_payload_data_error; @@ -5839,25 +5844,35 @@ module DataCache ( reg dataReadCmd_valid; reg [9:0] dataReadCmd_payload; reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; + reg [1:0] dataWriteCmd_payload_way; reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_5; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_6; + wire _zz_7; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire _zz_8; + wire ways_1_tagsReadRsp_valid; + wire ways_1_tagsReadRsp_error; + wire [19:0] ways_1_tagsReadRsp_address; + wire [21:0] _zz_9; + wire _zz_10; + wire [31:0] ways_1_dataReadRspMem; + wire [31:0] ways_1_dataReadRsp; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + reg [3:0] _zz_11; wire [3:0] stage0_mask; - wire [0:0] stage0_dataColisions; - wire [0:0] stage0_wayInvalidate; + reg [1:0] stage0_dataColisions; + wire [9:0] _zz_12; + wire [3:0] _zz_13; + wire [1:0] stage0_wayInvalidate; wire stage0_isAmo; reg stageA_request_wr; reg [31:0] stageA_request_data; @@ -5866,12 +5881,14 @@ module DataCache ( reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; - wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; - reg [0:0] stageA_wayInvalidate; - reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; - wire [0:0] stageA_dataColisions; + wire [1:0] stageA_wayHits; + reg [1:0] _zz_14; + reg [1:0] stageA_wayInvalidate; + reg [1:0] stage0_dataColisions_regNextWhen; + reg [1:0] _zz_15; + wire [9:0] _zz_16; + wire [3:0] _zz_17; + wire [1:0] stageA_dataColisions; reg stageB_request_wr; reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; @@ -5888,13 +5905,17 @@ module DataCache ( reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + reg stageB_tagsReadRsp_1_valid; + reg stageB_tagsReadRsp_1_error; + reg [19:0] stageB_tagsReadRsp_1_address; reg [31:0] stageB_dataReadRsp_0; - reg [0:0] stageB_wayInvalidate; + reg [31:0] stageB_dataReadRsp_1; + reg [1:0] stageB_wayInvalidate; wire stageB_consistancyHazard; - reg [0:0] stageB_dataColisions; + reg [1:0] stageB_dataColisions; reg stageB_unaligned; - reg [0:0] stageB_waysHitsBeforeInvalidate; - wire [0:0] stageB_waysHits; + reg [1:0] stageB_waysHitsBeforeInvalidate; + wire [1:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; reg [3:0] stageB_mask; @@ -5910,7 +5931,7 @@ module DataCache ( wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; wire stageB_bypassCache; - wire [0:0] _zz_9; + reg [1:0] _zz_18; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -5918,7 +5939,7 @@ module DataCache ( reg [2:0] loader_counter_value; wire loader_counter_willOverflowIfInc; wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; + reg [1:0] loader_waysAllocator; reg loader_error; wire loader_kill; reg loader_killReg; @@ -5928,113 +5949,184 @@ module DataCache ( (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + reg [7:0] _zz_40; + reg [7:0] _zz_41; + reg [7:0] _zz_42; + reg [7:0] _zz_43; + (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol3 [0:1023]; + reg [7:0] _zz_44; + reg [7:0] _zz_45; + reg [7:0] _zz_46; + reg [7:0] _zz_47; + + assign _zz_23 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_24 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_25 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_26 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_27 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_28 = (! stageB_flusher_hold); + assign _zz_29 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_30 = _zz_6[0 : 0]; + assign _zz_31 = _zz_6[1 : 1]; + assign _zz_32 = _zz_9[0 : 0]; + assign _zz_33 = _zz_9[1 : 1]; + assign _zz_34 = 1'b1; + assign _zz_35 = loader_counter_willIncrement; + assign _zz_36 = {2'd0, _zz_35}; + assign _zz_37 = {loader_waysAllocator,loader_waysAllocator[1]}; + assign _zz_38 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + assign _zz_39 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + if(_zz_5) begin + _zz_19 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_4) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_38; + end + end + + always @ (*) begin + _zz_20 = {_zz_43, _zz_42, _zz_41, _zz_40}; + end + always @ (posedge clk) begin + if(_zz_7) begin + _zz_40 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_41 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_42 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_43 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_3) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_3) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_3) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_3) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (posedge clk) begin + if(_zz_8) begin + _zz_21 <= ways_1_tags[tagsReadCmd_payload]; end end always @ (posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_1_tags[tagsWriteCmd_payload_address] <= _zz_39; end end always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + _zz_22 = {_zz_47, _zz_46, _zz_45, _zz_44}; end always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + if(_zz_10) begin + _zz_44 <= ways_1_data_symbol0[dataReadCmd_payload]; + _zz_45 <= ways_1_data_symbol1[dataReadCmd_payload]; + _zz_46 <= ways_1_data_symbol2[dataReadCmd_payload]; + _zz_47 <= ways_1_data_symbol3[dataReadCmd_payload]; end end always @ (posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + ways_1_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end if(dataWriteCmd_payload_mask[1] && _zz_1) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + ways_1_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end if(dataWriteCmd_payload_mask[2] && _zz_1) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + ways_1_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end if(dataWriteCmd_payload_mask[3] && _zz_1) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + ways_1_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end end always @ (*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if((dataWriteCmd_valid && dataWriteCmd_payload_way[1]))begin _zz_1 = 1'b1; end end always @ (*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[1]))begin _zz_2 = 1'b1; end end + always @ (*) begin + _zz_3 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_3 = 1'b1; + end + end + + always @ (*) begin + _zz_4 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_4 = 1'b1; + end + end + assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_5 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_6 = _zz_19; + assign ways_0_tagsReadRsp_valid = _zz_30[0]; + assign ways_0_tagsReadRsp_error = _zz_31[0]; + assign ways_0_tagsReadRsp_address = _zz_6[21 : 2]; + assign _zz_7 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_20; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + assign _zz_8 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_9 = _zz_21; + assign ways_1_tagsReadRsp_valid = _zz_32[0]; + assign ways_1_tagsReadRsp_error = _zz_33[0]; + assign ways_1_tagsReadRsp_address = _zz_9[21 : 2]; + assign _zz_10 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_1_dataReadRspMem = _zz_22; + assign ways_1_dataReadRsp = ways_1_dataReadRspMem[31 : 0]; always @ (*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(_zz_23)begin tagsReadCmd_valid = 1'b1; end end always @ (*) begin tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + if(_zz_23)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end always @ (*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(_zz_23)begin dataReadCmd_valid = 1'b1; end end always @ (*) begin dataReadCmd_payload = 10'h0; - if(_zz_12)begin + if(_zz_23)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end @@ -6044,7 +6136,7 @@ module DataCache ( if(stageB_flusher_valid)begin tagsWriteCmd_valid = stageB_flusher_valid; end - if(_zz_13)begin + if(_zz_24)begin tagsWriteCmd_valid = 1'b0; end if(loader_done)begin @@ -6053,9 +6145,9 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_way = 1'bx; + tagsWriteCmd_payload_way = 2'bxx; if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = 1'b1; + tagsWriteCmd_payload_way = 2'b11; end if(loader_done)begin tagsWriteCmd_payload_way = loader_waysAllocator; @@ -6103,20 +6195,20 @@ module DataCache ( dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(_zz_24)begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(_zz_25)begin dataWriteCmd_valid = 1'b1; end end always @ (*) begin - dataWriteCmd_payload_way = 1'bx; + dataWriteCmd_payload_way = 2'bxx; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(_zz_25)begin dataWriteCmd_payload_way = loader_waysAllocator; end end @@ -6126,7 +6218,7 @@ module DataCache ( if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(_zz_25)begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end @@ -6136,7 +6228,7 @@ module DataCache ( if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(_zz_25)begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end @@ -6145,11 +6237,11 @@ module DataCache ( dataWriteCmd_payload_mask = 4'bxxxx; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_34[0])begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(_zz_25)begin dataWriteCmd_payload_mask = 4'b1111; end end @@ -6160,28 +6252,44 @@ module DataCache ( always @ (*) begin case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_11 = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_11 = 4'b0011; end default : begin - _zz_6 = 4'b1111; + _zz_11 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stage0_wayInvalidate = 1'b0; + assign stage0_mask = (_zz_11 <<< io_cpu_execute_address[1 : 0]); + assign _zz_12 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_13 = dataWriteCmd_payload_mask[3 : 0]; + always @ (*) begin + stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); + stage0_dataColisions[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); + end + + assign stage0_wayInvalidate = 2'b00; assign stage0_isAmo = 1'b0; assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + _zz_14[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + _zz_14[1] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_1_tagsReadRsp_address) && ways_1_tagsReadRsp_valid); + end + + assign stageA_wayHits = _zz_14; + assign _zz_16 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_17 = dataWriteCmd_payload_mask[3 : 0]; + always @ (*) begin + _zz_15[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); + _zz_15[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); + end + + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_15); always @ (*) begin stageB_mmuRspFreeze = 1'b0; if((stageB_loaderValid || loader_valid))begin @@ -6191,14 +6299,14 @@ module DataCache ( assign stageB_consistancyHazard = 1'b0; assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); - assign stageB_waysHit = (stageB_waysHits != 1'b0); - assign stageB_dataMux = stageB_dataReadRsp_0; + assign stageB_waysHit = (stageB_waysHits != 2'b00); + assign stageB_dataMux = (stageB_waysHits[0] ? stageB_dataReadRsp_0 : stageB_dataReadRsp_1); always @ (*) begin stageB_loaderValid = 1'b0; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(! _zz_26) begin + if(! _zz_27) begin if(io_mem_cmd_ready)begin stageB_loaderValid = 1'b1; end @@ -6206,7 +6314,7 @@ module DataCache ( end end end - if(_zz_13)begin + if(_zz_24)begin stageB_loaderValid = 1'b0; end end @@ -6219,12 +6327,12 @@ module DataCache ( end if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(_zz_26)begin if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin + if(_zz_27)begin if(((! stageB_request_wr) || io_mem_cmd_ready))begin io_cpu_writeBack_haltIt = 1'b0; end @@ -6232,7 +6340,7 @@ module DataCache ( end end end - if(_zz_13)begin + if(_zz_24)begin io_cpu_writeBack_haltIt = 1'b0; end end @@ -6254,8 +6362,8 @@ module DataCache ( stageB_cpuWriteToCache = 1'b0; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(! _zz_26) begin + if(_zz_27)begin stageB_cpuWriteToCache = 1'b1; end end @@ -6267,9 +6375,9 @@ module DataCache ( io_cpu_redo = 1'b0; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(! _zz_26) begin + if(_zz_27)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 2'b00)))begin io_cpu_redo = 1'b1; end end @@ -6289,7 +6397,7 @@ module DataCache ( if(stageB_bypassCache)begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9) != 1'b0); + io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_18) != 2'b00); end end @@ -6300,10 +6408,10 @@ module DataCache ( io_mem_cmd_valid = 1'b0; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(_zz_26)begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_16)begin + if(_zz_27)begin if(stageB_request_wr)begin io_mem_cmd_valid = 1'b1; end @@ -6315,7 +6423,7 @@ module DataCache ( end end end - if(_zz_13)begin + if(_zz_24)begin io_mem_cmd_valid = 1'b0; end end @@ -6324,8 +6432,8 @@ module DataCache ( io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(! _zz_26) begin + if(_zz_27)begin io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; end else begin io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; @@ -6339,8 +6447,8 @@ module DataCache ( io_mem_cmd_payload_length = 3'b000; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(! _zz_26) begin + if(_zz_27)begin io_mem_cmd_payload_length = 3'b000; end else begin io_mem_cmd_payload_length = 3'b111; @@ -6355,8 +6463,8 @@ module DataCache ( io_mem_cmd_payload_wr = stageB_request_wr; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(! _zz_26) begin + if(! _zz_27) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6377,10 +6485,14 @@ module DataCache ( end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + _zz_18[0] = stageB_tagsReadRsp_0_error; + _zz_18[1] = stageB_tagsReadRsp_1_error; + end + always @ (*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(_zz_25)begin loader_counter_willIncrement = 1'b1; end end @@ -6389,7 +6501,7 @@ module DataCache ( assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); + loader_counter_valueNext = (loader_counter_value + _zz_36); if(loader_counter_willClear)begin loader_counter_valueNext = 3'b000; end @@ -6440,9 +6552,17 @@ module DataCache ( stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_1_valid <= ways_1_tagsReadRsp_valid; + stageB_tagsReadRsp_1_error <= ways_1_tagsReadRsp_error; + stageB_tagsReadRsp_1_address <= ways_1_tagsReadRsp_address; + end if((! io_cpu_writeBack_isStuck))begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_1 <= ways_1_dataReadRsp; + end if((! io_cpu_writeBack_isStuck))begin stageB_wayInvalidate <= stageA_wayInvalidate; end @@ -6459,8 +6579,8 @@ module DataCache ( stageB_mask <= stageA_mask; end if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin + if(_zz_28)begin + if(_zz_29)begin stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); end end @@ -6477,7 +6597,7 @@ module DataCache ( stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; - loader_waysAllocator <= 1'b1; + loader_waysAllocator <= 2'b01; loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin @@ -6488,8 +6608,8 @@ module DataCache ( memCmdSent <= 1'b0; end if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin + if(_zz_28)begin + if(! _zz_29) begin stageB_flusher_valid <= 1'b0; end end @@ -6515,7 +6635,7 @@ module DataCache ( if(loader_kill)begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(_zz_25)begin loader_error <= (loader_error || io_mem_rsp_payload_error); end if(loader_done)begin @@ -6524,7 +6644,7 @@ module DataCache ( loader_killReg <= 1'b0; end if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + loader_waysAllocator <= _zz_37[1:0]; end end end @@ -6573,25 +6693,36 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [21:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [21:0] _zz_15; + reg [31:0] _zz_16; + reg [31:0] _zz_17; + reg [21:0] _zz_18; + reg [21:0] _zz_19; + reg _zz_20; + reg [31:0] _zz_21; + wire _zz_22; + wire _zz_23; + wire [0:0] _zz_24; + wire [0:0] _zz_25; + wire [0:0] _zz_26; + wire [0:0] _zz_27; + wire [21:0] _zz_28; + wire [21:0] _zz_29; reg _zz_1; reg _zz_2; + reg _zz_3; + reg _zz_4; reg lineLoader_fire; reg lineLoader_valid; (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + reg _zz_5; reg lineLoader_cmdSent; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; + reg [0:0] lineLoader_wayToAllocate_valueNext; + reg [0:0] lineLoader_wayToAllocate_value; wire lineLoader_wayToAllocate_willOverflowIfInc; wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; @@ -6600,21 +6731,41 @@ module InstructionCache ( wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_tag_1_valid; + wire [6:0] lineLoader_write_tag_1_payload_address; + wire lineLoader_write_tag_1_payload_data_valid; + wire lineLoader_write_tag_1_payload_data_error; + wire [19:0] lineLoader_write_tag_1_payload_data_address; wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire lineLoader_write_data_1_valid; + wire [9:0] lineLoader_write_data_1_payload_address; + wire [31:0] lineLoader_write_data_1_payload_data; + wire [9:0] _zz_6; + wire _zz_7; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [9:0] _zz_8; + wire _zz_9; + wire [31:0] fetchStage_read_banksValue_1_dataMem; + wire [31:0] fetchStage_read_banksValue_1_data; + wire [6:0] _zz_10; + wire _zz_11; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_12; + wire [6:0] _zz_13; + wire _zz_14; + wire fetchStage_read_waysValues_1_tag_valid; + wire fetchStage_read_waysValues_1_tag_error; + wire [19:0] fetchStage_read_waysValues_1_tag_address; + wire [21:0] _zz_15; wire fetchStage_hit_hits_0; + wire fetchStage_hit_hits_1; wire fetchStage_hit_valid; + wire [0:0] fetchStage_hit_wayId; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; @@ -6630,51 +6781,107 @@ module InstructionCache ( reg decodeStage_hit_valid; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [31:0] banks_1 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; + + assign _zz_22 = (! lineLoader_flushCounter[7]); + assign _zz_23 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_24 = _zz_12[0 : 0]; + assign _zz_25 = _zz_12[1 : 1]; + assign _zz_26 = _zz_15[0 : 0]; + assign _zz_27 = _zz_15[1 : 1]; + assign _zz_28 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + assign _zz_29 = {lineLoader_write_tag_1_payload_data_address,{lineLoader_write_tag_1_payload_data_error,lineLoader_write_tag_1_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_16 <= banks_0[_zz_6]; + end + end - assign _zz_11 = (! lineLoader_flushCounter[7]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; always @ (posedge clk) begin if(_zz_1) begin - banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + banks_1[lineLoader_write_data_1_payload_address] <= lineLoader_write_data_1_payload_data; end end always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + if(_zz_9) begin + _zz_17 <= banks_1[_zz_8]; end end always @ (posedge clk) begin - if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + if(_zz_4) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_28; end end always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + if(_zz_11) begin + _zz_18 <= ways_0_tags[_zz_10]; end end + always @ (posedge clk) begin + if(_zz_3) begin + ways_1_tags[lineLoader_write_tag_1_payload_address] <= _zz_29; + end + end + + always @ (posedge clk) begin + if(_zz_14) begin + _zz_19 <= ways_1_tags[_zz_13]; + end + end + + always @(*) begin + case(fetchStage_hit_wayId) + 1'b0 : begin + _zz_20 = fetchStage_read_waysValues_0_tag_error; + _zz_21 = fetchStage_read_banksValue_0_data; + end + default : begin + _zz_20 = fetchStage_read_waysValues_1_tag_error; + _zz_21 = fetchStage_read_banksValue_1_data; + end + endcase + end + always @ (*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_1_valid)begin _zz_1 = 1'b1; end end always @ (*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_data_0_valid)begin _zz_2 = 1'b1; end end + always @ (*) begin + _zz_3 = 1'b0; + if(lineLoader_write_tag_1_valid)begin + _zz_3 = 1'b1; + end + end + + always @ (*) begin + _zz_4 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_4 = 1'b1; + end + end + always @ (*) begin lineLoader_fire = 1'b0; if(io_mem_rsp_valid)begin @@ -6686,10 +6893,10 @@ module InstructionCache ( always @ (*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(_zz_22)begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if((! _zz_5))begin io_cpu_prefetch_haltIt = 1'b1; end if(io_flush)begin @@ -6708,30 +6915,57 @@ module InstructionCache ( end assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflowIfInc = (lineLoader_wayToAllocate_value == 1'b1); assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + always @ (*) begin + lineLoader_wayToAllocate_valueNext = (lineLoader_wayToAllocate_value + lineLoader_wayToAllocate_willIncrement); + if(lineLoader_wayToAllocate_willClear)begin + lineLoader_wayToAllocate_valueNext = 1'b0; + end + end + + assign lineLoader_write_tag_0_valid = (((lineLoader_wayToAllocate_value == 1'b0) && lineLoader_fire) || (! lineLoader_flushCounter[7])); assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_tag_1_valid = (((lineLoader_wayToAllocate_value == 1'b1) && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_1_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_1_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_1_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_1_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b0)); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; - assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign lineLoader_write_data_1_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b1)); + assign lineLoader_write_data_1_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_1_payload_data = io_mem_rsp_payload_data; + assign _zz_6 = io_cpu_prefetch_pc[11 : 2]; assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_read_banksValue_0_dataMem = _zz_16; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_8 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_9 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_1_dataMem = _zz_17; + assign fetchStage_read_banksValue_1_data = fetchStage_read_banksValue_1_dataMem[31 : 0]; + assign _zz_10 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_11 = (! io_cpu_fetch_isStuck); + assign _zz_12 = _zz_18; + assign fetchStage_read_waysValues_0_tag_valid = _zz_24[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_25[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_12[21 : 2]; + assign _zz_13 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_14 = (! io_cpu_fetch_isStuck); + assign _zz_15 = _zz_19; + assign fetchStage_read_waysValues_1_tag_valid = _zz_26[0]; + assign fetchStage_read_waysValues_1_tag_error = _zz_27[0]; + assign fetchStage_read_waysValues_1_tag_address = _zz_15[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_hits_1 = (fetchStage_read_waysValues_1_tag_valid && (fetchStage_read_waysValues_1_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = ({fetchStage_hit_hits_1,fetchStage_hit_hits_0} != 2'b00); + assign fetchStage_hit_wayId = fetchStage_hit_hits_1; + assign fetchStage_hit_error = _zz_20; + assign fetchStage_hit_data = _zz_21; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; @@ -6747,6 +6981,7 @@ module InstructionCache ( lineLoader_hadError <= 1'b0; lineLoader_flushPending <= 1'b1; lineLoader_cmdSent <= 1'b0; + lineLoader_wayToAllocate_value <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin if(lineLoader_fire)begin @@ -6761,7 +6996,7 @@ module InstructionCache ( if(io_flush)begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(_zz_23)begin lineLoader_flushPending <= 1'b0; end if((io_mem_cmd_valid && io_mem_cmd_ready))begin @@ -6770,6 +7005,7 @@ module InstructionCache ( if(lineLoader_fire)begin lineLoader_cmdSent <= 1'b0; end + lineLoader_wayToAllocate_value <= lineLoader_wayToAllocate_valueNext; if(io_mem_rsp_valid)begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); if(io_mem_rsp_payload_error)begin @@ -6783,11 +7019,11 @@ module InstructionCache ( if(io_cpu_fill_valid)begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(_zz_22)begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_12)begin + _zz_5 <= lineLoader_flushCounter[7]; + if(_zz_23)begin lineLoader_flushCounter <= 8'h0; end if((! io_cpu_decode_isStuck))begin diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.yaml index cf27a68..1f28413 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.yaml +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.yaml @@ -1,4 +1,4 @@ iBus: !!vexriscv.BusReport flushInstructions: [4111, 19, 19, 19] - info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 8192} kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index 797c0b7..b4f2242 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : 07a72e20035b64cf586cbf04df799cb4bf961010 +// Generator : SpinalHDL v1.4.2 git head : f022529bb419c7a04f9ba1b61e931127b7220919 // Component : VexRiscv -// Git hash : 07a72e20035b64cf586cbf04df799cb4bf961010 +// Git hash : f022529bb419c7a04f9ba1b61e931127b7220919 `define Input2Kind_defaultEncoding_type [0:0] @@ -1812,8 +1812,8 @@ module VexRiscv_inner ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_177[2:0] ), //i - ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + ._zz_16 (_zz_177[2:0] ), //i + ._zz_17 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); @@ -6095,37 +6095,42 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_19; + reg [31:0] _zz_20; + reg [21:0] _zz_21; + reg [31:0] _zz_22; + wire _zz_23; + wire _zz_24; + wire _zz_25; + wire _zz_26; + wire _zz_27; + wire _zz_28; + wire _zz_29; + wire [0:0] _zz_30; + wire [0:0] _zz_31; + wire [0:0] _zz_32; + wire [0:0] _zz_33; + wire [0:0] _zz_34; + wire [0:0] _zz_35; + wire [2:0] _zz_36; + wire [2:0] _zz_37; + wire [21:0] _zz_38; + wire [21:0] _zz_39; reg _zz_1; reg _zz_2; + reg _zz_3; + reg _zz_4; wire haltCpu; reg tagsReadCmd_valid; reg [6:0] tagsReadCmd_payload; reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; + reg [1:0] tagsWriteCmd_payload_way; reg [6:0] tagsWriteCmd_payload_address; reg tagsWriteCmd_payload_data_valid; reg tagsWriteCmd_payload_data_error; reg [19:0] tagsWriteCmd_payload_data_address; reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; + reg [1:0] tagsWriteLastCmd_payload_way; reg [6:0] tagsWriteLastCmd_payload_address; reg tagsWriteLastCmd_payload_data_valid; reg tagsWriteLastCmd_payload_data_error; @@ -6133,25 +6138,35 @@ module DataCache ( reg dataReadCmd_valid; reg [9:0] dataReadCmd_payload; reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; + reg [1:0] dataWriteCmd_payload_way; reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_5; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_6; + wire _zz_7; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire _zz_8; + wire ways_1_tagsReadRsp_valid; + wire ways_1_tagsReadRsp_error; + wire [19:0] ways_1_tagsReadRsp_address; + wire [21:0] _zz_9; + wire _zz_10; + wire [31:0] ways_1_dataReadRspMem; + wire [31:0] ways_1_dataReadRsp; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + reg [3:0] _zz_11; wire [3:0] stage0_mask; - wire [0:0] stage0_dataColisions; - wire [0:0] stage0_wayInvalidate; + reg [1:0] stage0_dataColisions; + wire [9:0] _zz_12; + wire [3:0] _zz_13; + wire [1:0] stage0_wayInvalidate; wire stage0_isAmo; reg stageA_request_wr; reg [31:0] stageA_request_data; @@ -6160,12 +6175,14 @@ module DataCache ( reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; - wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; - reg [0:0] stageA_wayInvalidate; - reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; - wire [0:0] stageA_dataColisions; + wire [1:0] stageA_wayHits; + reg [1:0] _zz_14; + reg [1:0] stageA_wayInvalidate; + reg [1:0] stage0_dataColisions_regNextWhen; + reg [1:0] _zz_15; + wire [9:0] _zz_16; + wire [3:0] _zz_17; + wire [1:0] stageA_dataColisions; reg stageB_request_wr; reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; @@ -6182,13 +6199,17 @@ module DataCache ( reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + reg stageB_tagsReadRsp_1_valid; + reg stageB_tagsReadRsp_1_error; + reg [19:0] stageB_tagsReadRsp_1_address; reg [31:0] stageB_dataReadRsp_0; - reg [0:0] stageB_wayInvalidate; + reg [31:0] stageB_dataReadRsp_1; + reg [1:0] stageB_wayInvalidate; wire stageB_consistancyHazard; - reg [0:0] stageB_dataColisions; + reg [1:0] stageB_dataColisions; reg stageB_unaligned; - reg [0:0] stageB_waysHitsBeforeInvalidate; - wire [0:0] stageB_waysHits; + reg [1:0] stageB_waysHitsBeforeInvalidate; + wire [1:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; reg [3:0] stageB_mask; @@ -6204,7 +6225,7 @@ module DataCache ( wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; wire stageB_bypassCache; - wire [0:0] _zz_9; + reg [1:0] _zz_18; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -6212,7 +6233,7 @@ module DataCache ( reg [2:0] loader_counter_value; wire loader_counter_willOverflowIfInc; wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; + reg [1:0] loader_waysAllocator; reg loader_error; wire loader_kill; reg loader_killReg; @@ -6222,113 +6243,184 @@ module DataCache ( (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + reg [7:0] _zz_40; + reg [7:0] _zz_41; + reg [7:0] _zz_42; + reg [7:0] _zz_43; + (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol3 [0:1023]; + reg [7:0] _zz_44; + reg [7:0] _zz_45; + reg [7:0] _zz_46; + reg [7:0] _zz_47; + + assign _zz_23 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_24 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_25 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_26 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_27 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_28 = (! stageB_flusher_hold); + assign _zz_29 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_30 = _zz_6[0 : 0]; + assign _zz_31 = _zz_6[1 : 1]; + assign _zz_32 = _zz_9[0 : 0]; + assign _zz_33 = _zz_9[1 : 1]; + assign _zz_34 = 1'b1; + assign _zz_35 = loader_counter_willIncrement; + assign _zz_36 = {2'd0, _zz_35}; + assign _zz_37 = {loader_waysAllocator,loader_waysAllocator[1]}; + assign _zz_38 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + assign _zz_39 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + if(_zz_5) begin + _zz_19 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_4) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_38; + end + end + + always @ (*) begin + _zz_20 = {_zz_43, _zz_42, _zz_41, _zz_40}; + end + always @ (posedge clk) begin + if(_zz_7) begin + _zz_40 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_41 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_42 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_43 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_3) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_3) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_3) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_3) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (posedge clk) begin + if(_zz_8) begin + _zz_21 <= ways_1_tags[tagsReadCmd_payload]; end end always @ (posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_1_tags[tagsWriteCmd_payload_address] <= _zz_39; end end always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + _zz_22 = {_zz_47, _zz_46, _zz_45, _zz_44}; end always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + if(_zz_10) begin + _zz_44 <= ways_1_data_symbol0[dataReadCmd_payload]; + _zz_45 <= ways_1_data_symbol1[dataReadCmd_payload]; + _zz_46 <= ways_1_data_symbol2[dataReadCmd_payload]; + _zz_47 <= ways_1_data_symbol3[dataReadCmd_payload]; end end always @ (posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + ways_1_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end if(dataWriteCmd_payload_mask[1] && _zz_1) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + ways_1_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end if(dataWriteCmd_payload_mask[2] && _zz_1) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + ways_1_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end if(dataWriteCmd_payload_mask[3] && _zz_1) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + ways_1_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end end always @ (*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if((dataWriteCmd_valid && dataWriteCmd_payload_way[1]))begin _zz_1 = 1'b1; end end always @ (*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[1]))begin _zz_2 = 1'b1; end end + always @ (*) begin + _zz_3 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_3 = 1'b1; + end + end + + always @ (*) begin + _zz_4 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_4 = 1'b1; + end + end + assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_5 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_6 = _zz_19; + assign ways_0_tagsReadRsp_valid = _zz_30[0]; + assign ways_0_tagsReadRsp_error = _zz_31[0]; + assign ways_0_tagsReadRsp_address = _zz_6[21 : 2]; + assign _zz_7 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_20; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + assign _zz_8 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_9 = _zz_21; + assign ways_1_tagsReadRsp_valid = _zz_32[0]; + assign ways_1_tagsReadRsp_error = _zz_33[0]; + assign ways_1_tagsReadRsp_address = _zz_9[21 : 2]; + assign _zz_10 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_1_dataReadRspMem = _zz_22; + assign ways_1_dataReadRsp = ways_1_dataReadRspMem[31 : 0]; always @ (*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(_zz_23)begin tagsReadCmd_valid = 1'b1; end end always @ (*) begin tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + if(_zz_23)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end always @ (*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(_zz_23)begin dataReadCmd_valid = 1'b1; end end always @ (*) begin dataReadCmd_payload = 10'h0; - if(_zz_12)begin + if(_zz_23)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end @@ -6338,7 +6430,7 @@ module DataCache ( if(stageB_flusher_valid)begin tagsWriteCmd_valid = stageB_flusher_valid; end - if(_zz_13)begin + if(_zz_24)begin tagsWriteCmd_valid = 1'b0; end if(loader_done)begin @@ -6347,9 +6439,9 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_way = 1'bx; + tagsWriteCmd_payload_way = 2'bxx; if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = 1'b1; + tagsWriteCmd_payload_way = 2'b11; end if(loader_done)begin tagsWriteCmd_payload_way = loader_waysAllocator; @@ -6397,20 +6489,20 @@ module DataCache ( dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(_zz_24)begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(_zz_25)begin dataWriteCmd_valid = 1'b1; end end always @ (*) begin - dataWriteCmd_payload_way = 1'bx; + dataWriteCmd_payload_way = 2'bxx; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(_zz_25)begin dataWriteCmd_payload_way = loader_waysAllocator; end end @@ -6420,7 +6512,7 @@ module DataCache ( if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(_zz_25)begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end @@ -6430,7 +6522,7 @@ module DataCache ( if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(_zz_25)begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end @@ -6439,11 +6531,11 @@ module DataCache ( dataWriteCmd_payload_mask = 4'bxxxx; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_34[0])begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(_zz_25)begin dataWriteCmd_payload_mask = 4'b1111; end end @@ -6454,28 +6546,44 @@ module DataCache ( always @ (*) begin case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_11 = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_11 = 4'b0011; end default : begin - _zz_6 = 4'b1111; + _zz_11 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stage0_wayInvalidate = 1'b0; + assign stage0_mask = (_zz_11 <<< io_cpu_execute_address[1 : 0]); + assign _zz_12 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_13 = dataWriteCmd_payload_mask[3 : 0]; + always @ (*) begin + stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); + stage0_dataColisions[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); + end + + assign stage0_wayInvalidate = 2'b00; assign stage0_isAmo = 1'b0; assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + _zz_14[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + _zz_14[1] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_1_tagsReadRsp_address) && ways_1_tagsReadRsp_valid); + end + + assign stageA_wayHits = _zz_14; + assign _zz_16 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_17 = dataWriteCmd_payload_mask[3 : 0]; + always @ (*) begin + _zz_15[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); + _zz_15[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); + end + + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_15); always @ (*) begin stageB_mmuRspFreeze = 1'b0; if((stageB_loaderValid || loader_valid))begin @@ -6485,14 +6593,14 @@ module DataCache ( assign stageB_consistancyHazard = 1'b0; assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); - assign stageB_waysHit = (stageB_waysHits != 1'b0); - assign stageB_dataMux = stageB_dataReadRsp_0; + assign stageB_waysHit = (stageB_waysHits != 2'b00); + assign stageB_dataMux = (stageB_waysHits[0] ? stageB_dataReadRsp_0 : stageB_dataReadRsp_1); always @ (*) begin stageB_loaderValid = 1'b0; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(! _zz_26) begin + if(! _zz_27) begin if(io_mem_cmd_ready)begin stageB_loaderValid = 1'b1; end @@ -6500,7 +6608,7 @@ module DataCache ( end end end - if(_zz_13)begin + if(_zz_24)begin stageB_loaderValid = 1'b0; end end @@ -6513,12 +6621,12 @@ module DataCache ( end if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(_zz_26)begin if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin + if(_zz_27)begin if(((! stageB_request_wr) || io_mem_cmd_ready))begin io_cpu_writeBack_haltIt = 1'b0; end @@ -6526,7 +6634,7 @@ module DataCache ( end end end - if(_zz_13)begin + if(_zz_24)begin io_cpu_writeBack_haltIt = 1'b0; end end @@ -6548,8 +6656,8 @@ module DataCache ( stageB_cpuWriteToCache = 1'b0; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(! _zz_26) begin + if(_zz_27)begin stageB_cpuWriteToCache = 1'b1; end end @@ -6561,9 +6669,9 @@ module DataCache ( io_cpu_redo = 1'b0; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(! _zz_26) begin + if(_zz_27)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 2'b00)))begin io_cpu_redo = 1'b1; end end @@ -6583,7 +6691,7 @@ module DataCache ( if(stageB_bypassCache)begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9) != 1'b0); + io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_18) != 2'b00); end end @@ -6594,10 +6702,10 @@ module DataCache ( io_mem_cmd_valid = 1'b0; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(_zz_26)begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_16)begin + if(_zz_27)begin if(stageB_request_wr)begin io_mem_cmd_valid = 1'b1; end @@ -6609,7 +6717,7 @@ module DataCache ( end end end - if(_zz_13)begin + if(_zz_24)begin io_mem_cmd_valid = 1'b0; end end @@ -6618,8 +6726,8 @@ module DataCache ( io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(! _zz_26) begin + if(_zz_27)begin io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; end else begin io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; @@ -6633,8 +6741,8 @@ module DataCache ( io_mem_cmd_payload_length = 3'b000; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(! _zz_26) begin + if(_zz_27)begin io_mem_cmd_payload_length = 3'b000; end else begin io_mem_cmd_payload_length = 3'b111; @@ -6649,8 +6757,8 @@ module DataCache ( io_mem_cmd_payload_wr = stageB_request_wr; if(io_cpu_writeBack_isValid)begin if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(! _zz_26) begin + if(! _zz_27) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6671,10 +6779,14 @@ module DataCache ( end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + _zz_18[0] = stageB_tagsReadRsp_0_error; + _zz_18[1] = stageB_tagsReadRsp_1_error; + end + always @ (*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(_zz_25)begin loader_counter_willIncrement = 1'b1; end end @@ -6683,7 +6795,7 @@ module DataCache ( assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); + loader_counter_valueNext = (loader_counter_value + _zz_36); if(loader_counter_willClear)begin loader_counter_valueNext = 3'b000; end @@ -6734,9 +6846,17 @@ module DataCache ( stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_1_valid <= ways_1_tagsReadRsp_valid; + stageB_tagsReadRsp_1_error <= ways_1_tagsReadRsp_error; + stageB_tagsReadRsp_1_address <= ways_1_tagsReadRsp_address; + end if((! io_cpu_writeBack_isStuck))begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_1 <= ways_1_dataReadRsp; + end if((! io_cpu_writeBack_isStuck))begin stageB_wayInvalidate <= stageA_wayInvalidate; end @@ -6753,8 +6873,8 @@ module DataCache ( stageB_mask <= stageA_mask; end if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin + if(_zz_28)begin + if(_zz_29)begin stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); end end @@ -6771,7 +6891,7 @@ module DataCache ( stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; - loader_waysAllocator <= 1'b1; + loader_waysAllocator <= 2'b01; loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin @@ -6782,8 +6902,8 @@ module DataCache ( memCmdSent <= 1'b0; end if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin + if(_zz_28)begin + if(! _zz_29) begin stageB_flusher_valid <= 1'b0; end end @@ -6809,7 +6929,7 @@ module DataCache ( if(loader_kill)begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(_zz_25)begin loader_error <= (loader_error || io_mem_rsp_payload_error); end if(loader_done)begin @@ -6818,7 +6938,7 @@ module DataCache ( loader_killReg <= 1'b0; end if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + loader_waysAllocator <= _zz_37[1:0]; end end end @@ -6864,30 +6984,41 @@ module InstructionCache ( input io_mem_rsp_valid, input [31:0] io_mem_rsp_payload_data, input io_mem_rsp_payload_error, - input [2:0] _zz_9, - input [31:0] _zz_10, + input [2:0] _zz_16, + input [31:0] _zz_17, input clk, input reset ); - reg [31:0] _zz_11; - reg [21:0] _zz_12; - wire _zz_13; - wire _zz_14; - wire [0:0] _zz_15; - wire [0:0] _zz_16; - wire [21:0] _zz_17; + reg [31:0] _zz_18; + reg [31:0] _zz_19; + reg [21:0] _zz_20; + reg [21:0] _zz_21; + reg _zz_22; + reg [31:0] _zz_23; + wire _zz_24; + wire _zz_25; + wire [0:0] _zz_26; + wire [0:0] _zz_27; + wire [0:0] _zz_28; + wire [0:0] _zz_29; + wire [21:0] _zz_30; + wire [21:0] _zz_31; reg _zz_1; reg _zz_2; + reg _zz_3; + reg _zz_4; reg lineLoader_fire; reg lineLoader_valid; (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + reg _zz_5; reg lineLoader_cmdSent; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; + reg [0:0] lineLoader_wayToAllocate_valueNext; + reg [0:0] lineLoader_wayToAllocate_value; wire lineLoader_wayToAllocate_willOverflowIfInc; wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; @@ -6896,21 +7027,41 @@ module InstructionCache ( wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_tag_1_valid; + wire [6:0] lineLoader_write_tag_1_payload_address; + wire lineLoader_write_tag_1_payload_data_valid; + wire lineLoader_write_tag_1_payload_data_error; + wire [19:0] lineLoader_write_tag_1_payload_data_address; wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire lineLoader_write_data_1_valid; + wire [9:0] lineLoader_write_data_1_payload_address; + wire [31:0] lineLoader_write_data_1_payload_data; + wire [9:0] _zz_6; + wire _zz_7; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [9:0] _zz_8; + wire _zz_9; + wire [31:0] fetchStage_read_banksValue_1_dataMem; + wire [31:0] fetchStage_read_banksValue_1_data; + wire [6:0] _zz_10; + wire _zz_11; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_12; + wire [6:0] _zz_13; + wire _zz_14; + wire fetchStage_read_waysValues_1_tag_valid; + wire fetchStage_read_waysValues_1_tag_error; + wire [19:0] fetchStage_read_waysValues_1_tag_address; + wire [21:0] _zz_15; wire fetchStage_hit_hits_0; + wire fetchStage_hit_hits_1; wire fetchStage_hit_valid; + wire [0:0] fetchStage_hit_wayId; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; @@ -6926,51 +7077,107 @@ module InstructionCache ( reg decodeStage_hit_valid; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [31:0] banks_1 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; + + assign _zz_24 = (! lineLoader_flushCounter[7]); + assign _zz_25 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_26 = _zz_12[0 : 0]; + assign _zz_27 = _zz_12[1 : 1]; + assign _zz_28 = _zz_15[0 : 0]; + assign _zz_29 = _zz_15[1 : 1]; + assign _zz_30 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + assign _zz_31 = {lineLoader_write_tag_1_payload_data_address,{lineLoader_write_tag_1_payload_data_error,lineLoader_write_tag_1_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_18 <= banks_0[_zz_6]; + end + end - assign _zz_13 = (! lineLoader_flushCounter[7]); - assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_15 = _zz_8[0 : 0]; - assign _zz_16 = _zz_8[1 : 1]; - assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; always @ (posedge clk) begin if(_zz_1) begin - banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + banks_1[lineLoader_write_data_1_payload_address] <= lineLoader_write_data_1_payload_data; end end always @ (posedge clk) begin - if(_zz_5) begin - _zz_11 <= banks_0[_zz_4]; + if(_zz_9) begin + _zz_19 <= banks_1[_zz_8]; end end always @ (posedge clk) begin - if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + if(_zz_4) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_30; end end always @ (posedge clk) begin - if(_zz_7) begin - _zz_12 <= ways_0_tags[_zz_6]; + if(_zz_11) begin + _zz_20 <= ways_0_tags[_zz_10]; + end + end + + always @ (posedge clk) begin + if(_zz_3) begin + ways_1_tags[lineLoader_write_tag_1_payload_address] <= _zz_31; end end + always @ (posedge clk) begin + if(_zz_14) begin + _zz_21 <= ways_1_tags[_zz_13]; + end + end + + always @(*) begin + case(fetchStage_hit_wayId) + 1'b0 : begin + _zz_22 = fetchStage_read_waysValues_0_tag_error; + _zz_23 = fetchStage_read_banksValue_0_data; + end + default : begin + _zz_22 = fetchStage_read_waysValues_1_tag_error; + _zz_23 = fetchStage_read_banksValue_1_data; + end + endcase + end + always @ (*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_1_valid)begin _zz_1 = 1'b1; end end always @ (*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_data_0_valid)begin _zz_2 = 1'b1; end end + always @ (*) begin + _zz_3 = 1'b0; + if(lineLoader_write_tag_1_valid)begin + _zz_3 = 1'b1; + end + end + + always @ (*) begin + _zz_4 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_4 = 1'b1; + end + end + always @ (*) begin lineLoader_fire = 1'b0; if(io_mem_rsp_valid)begin @@ -6982,10 +7189,10 @@ module InstructionCache ( always @ (*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_13)begin + if(_zz_24)begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if((! _zz_5))begin io_cpu_prefetch_haltIt = 1'b1; end if(io_flush)begin @@ -7004,30 +7211,57 @@ module InstructionCache ( end assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflowIfInc = (lineLoader_wayToAllocate_value == 1'b1); assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + always @ (*) begin + lineLoader_wayToAllocate_valueNext = (lineLoader_wayToAllocate_value + lineLoader_wayToAllocate_willIncrement); + if(lineLoader_wayToAllocate_willClear)begin + lineLoader_wayToAllocate_valueNext = 1'b0; + end + end + + assign lineLoader_write_tag_0_valid = (((lineLoader_wayToAllocate_value == 1'b0) && lineLoader_fire) || (! lineLoader_flushCounter[7])); assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_tag_1_valid = (((lineLoader_wayToAllocate_value == 1'b1) && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_1_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_1_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_1_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_1_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b0)); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_11; - assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign lineLoader_write_data_1_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b1)); + assign lineLoader_write_data_1_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_1_payload_data = io_mem_rsp_payload_data; + assign _zz_6 = io_cpu_prefetch_pc[11 : 2]; assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_12; - assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_read_banksValue_0_dataMem = _zz_18; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_8 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_9 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_1_dataMem = _zz_19; + assign fetchStage_read_banksValue_1_data = fetchStage_read_banksValue_1_dataMem[31 : 0]; + assign _zz_10 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_11 = (! io_cpu_fetch_isStuck); + assign _zz_12 = _zz_20; + assign fetchStage_read_waysValues_0_tag_valid = _zz_26[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_27[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_12[21 : 2]; + assign _zz_13 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_14 = (! io_cpu_fetch_isStuck); + assign _zz_15 = _zz_21; + assign fetchStage_read_waysValues_1_tag_valid = _zz_28[0]; + assign fetchStage_read_waysValues_1_tag_error = _zz_29[0]; + assign fetchStage_read_waysValues_1_tag_address = _zz_15[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_hits_1 = (fetchStage_read_waysValues_1_tag_valid && (fetchStage_read_waysValues_1_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = ({fetchStage_hit_hits_1,fetchStage_hit_hits_0} != 2'b00); + assign fetchStage_hit_wayId = fetchStage_hit_hits_1; + assign fetchStage_hit_error = _zz_22; + assign fetchStage_hit_data = _zz_23; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; @@ -7043,6 +7277,7 @@ module InstructionCache ( lineLoader_hadError <= 1'b0; lineLoader_flushPending <= 1'b1; lineLoader_cmdSent <= 1'b0; + lineLoader_wayToAllocate_value <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin if(lineLoader_fire)begin @@ -7057,7 +7292,7 @@ module InstructionCache ( if(io_flush)begin lineLoader_flushPending <= 1'b1; end - if(_zz_14)begin + if(_zz_25)begin lineLoader_flushPending <= 1'b0; end if((io_mem_cmd_valid && io_mem_cmd_ready))begin @@ -7066,6 +7301,7 @@ module InstructionCache ( if(lineLoader_fire)begin lineLoader_cmdSent <= 1'b0; end + lineLoader_wayToAllocate_value <= lineLoader_wayToAllocate_valueNext; if(io_mem_rsp_valid)begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); if(io_mem_rsp_payload_error)begin @@ -7079,11 +7315,11 @@ module InstructionCache ( if(io_cpu_fill_valid)begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_13)begin + if(_zz_24)begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_14)begin + _zz_5 <= lineLoader_flushCounter[7]; + if(_zz_25)begin lineLoader_flushCounter <= 8'h0; end if((! io_cpu_decode_isStuck))begin @@ -7105,8 +7341,8 @@ module InstructionCache ( if((! io_cpu_decode_isStuck))begin decodeStage_hit_error <= fetchStage_hit_error; end - if((_zz_9 != 3'b000))begin - io_cpu_fetch_data_regNextWhen <= _zz_10; + if((_zz_16 != 3'b000))begin + io_cpu_fetch_data_regNextWhen <= _zz_17; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml index 24597c0..c869dbe 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.yaml @@ -1,5 +1,5 @@ debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} iBus: !!vexriscv.BusReport flushInstructions: [4111, 19, 19, 19] - info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 8192} kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index b4dbad5..6b56a53 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -107,7 +107,7 @@ object GenCoreDefault{ config = InstructionCacheConfig( cacheSize = argConfig.iCacheSize, bytePerLine = 32, - wayCount = 1, + wayCount = (argConfig.iCacheSize + 4095) / 4096, addressWidth = 32, cpuDataWidth = 32, memDataWidth = 32, @@ -136,7 +136,7 @@ object GenCoreDefault{ config = new DataCacheConfig( cacheSize = argConfig.dCacheSize, bytePerLine = 32, - wayCount = 1, + wayCount = (argConfig.dCacheSize + 4095) / 4096, addressWidth = 32, cpuDataWidth = 32, memDataWidth = 32, From 12ecb67b0542d2b21b2d17d469c07c139f5a042f Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Fri, 19 Feb 2021 11:25:03 -0800 Subject: [PATCH 07/30] Bump SpinalHdl/VexRiscv submodules; rebuild; widen CFU funcid port. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv.v | 10619 ++++++------- .../verilog/VexRiscv_Debug.v | 9551 ++++++------ .../verilog/VexRiscv_Full.v | 9481 ++++++------ .../verilog/VexRiscv_FullCfu.v | 2494 +-- .../verilog/VexRiscv_FullCfuDebug.v | 2583 ++-- .../verilog/VexRiscv_FullDebug.v | 10059 +++++++------ .../verilog/VexRiscv_IMAC.v | 9647 ++++++------ .../verilog/VexRiscv_IMACDebug.v | 10135 +++++++------ .../verilog/VexRiscv_Linux.v | 12294 +++++++-------- .../verilog/VexRiscv_LinuxDebug.v | 12474 ++++++++-------- .../verilog/VexRiscv_LinuxNoDspFmax.v | 11749 ++++++++------- .../verilog/VexRiscv_LinuxNoDspFmax.yaml | 4 + .../verilog/VexRiscv_Lite.v | 6520 ++++---- .../verilog/VexRiscv_LiteDebug.v | 6819 +++++---- .../verilog/VexRiscv_Min.v | 5107 +++---- .../verilog/VexRiscv_MinDebug.v | 5302 +++---- pythondata_cpu_vexriscv/verilog/ext/SpinalHDL | 2 +- pythondata_cpu_vexriscv/verilog/ext/VexRiscv | 2 +- .../main/scala/vexriscv/GenCoreDefault.scala | 5 +- .../verilog/wrapVexRiscv_FullCfu.v | 2 +- .../verilog/wrapVexRiscv_FullCfuDebug.v | 2 +- 22 files changed, 63926 insertions(+), 60927 deletions(-) create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.yaml diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index a95cd5f..187afee 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -1,6 +1,6 @@ SRC := ${shell find . -type f -name \*.scala} -all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v +all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv.v b/pythondata_cpu_vexriscv/verilog/VexRiscv.v index 9ee4975..13d0734 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:06:19 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -8,5842 +8,6005 @@ `define EnvCtrlEnum_defaultEncoding_XRET 2'b01 `define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - `define BranchCtrlEnum_defaultEncoding_type [1:0] `define BranchCtrlEnum_defaultEncoding_INC 2'b00 `define BranchCtrlEnum_defaultEncoding_B 2'b01 `define BranchCtrlEnum_defaultEncoding_JAL 2'b10 `define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + `define Src2CtrlEnum_defaultEncoding_type [1:0] `define Src2CtrlEnum_defaultEncoding_RS 2'b00 `define Src2CtrlEnum_defaultEncoding_IMI 2'b01 `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + `define Src1CtrlEnum_defaultEncoding_type [1:0] `define Src1CtrlEnum_defaultEncoding_RS 2'b00 `define Src1CtrlEnum_defaultEncoding_IMU 2'b01 `define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_160; + wire _zz_161; + wire _zz_162; + wire _zz_163; + wire _zz_164; + wire _zz_165; + wire _zz_166; + wire _zz_167; + reg _zz_168; + wire _zz_169; + wire [31:0] _zz_170; + wire _zz_171; + wire [31:0] _zz_172; + reg _zz_173; + wire _zz_174; + wire _zz_175; + wire [31:0] _zz_176; + wire _zz_177; + wire _zz_178; + wire _zz_179; + wire _zz_180; + wire _zz_181; + wire _zz_182; + wire _zz_183; + wire _zz_184; + wire [3:0] _zz_185; + wire _zz_186; + wire _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_191; + wire _zz_192; + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + wire _zz_201; + wire _zz_202; + wire _zz_203; + wire [1:0] _zz_204; + wire _zz_205; + wire _zz_206; + wire _zz_207; + wire _zz_208; + wire _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire [1:0] _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + wire _zz_219; + wire _zz_220; + wire _zz_221; + wire _zz_222; + wire [1:0] _zz_223; + wire _zz_224; + wire [1:0] _zz_225; + wire [51:0] _zz_226; + wire [51:0] _zz_227; + wire [51:0] _zz_228; + wire [32:0] _zz_229; + wire [51:0] _zz_230; + wire [49:0] _zz_231; + wire [51:0] _zz_232; + wire [49:0] _zz_233; + wire [51:0] _zz_234; + wire [32:0] _zz_235; + wire [31:0] _zz_236; + wire [32:0] _zz_237; + wire [0:0] _zz_238; + wire [0:0] _zz_239; + wire [0:0] _zz_240; + wire [0:0] _zz_241; + wire [0:0] _zz_242; + wire [0:0] _zz_243; + wire [0:0] _zz_244; + wire [0:0] _zz_245; + wire [0:0] _zz_246; + wire [0:0] _zz_247; + wire [0:0] _zz_248; + wire [0:0] _zz_249; + wire [0:0] _zz_250; + wire [0:0] _zz_251; + wire [0:0] _zz_252; + wire [0:0] _zz_253; + wire [0:0] _zz_254; + wire [3:0] _zz_255; + wire [2:0] _zz_256; + wire [31:0] _zz_257; + wire [11:0] _zz_258; + wire [31:0] _zz_259; + wire [19:0] _zz_260; + wire [11:0] _zz_261; + wire [31:0] _zz_262; + wire [31:0] _zz_263; + wire [19:0] _zz_264; + wire [11:0] _zz_265; + wire [2:0] _zz_266; + wire [2:0] _zz_267; + wire [0:0] _zz_268; + wire [2:0] _zz_269; + wire [4:0] _zz_270; + wire [11:0] _zz_271; + wire [11:0] _zz_272; + wire [31:0] _zz_273; + wire [31:0] _zz_274; + wire [31:0] _zz_275; + wire [31:0] _zz_276; + wire [31:0] _zz_277; + wire [31:0] _zz_278; + wire [31:0] _zz_279; + wire [11:0] _zz_280; + wire [19:0] _zz_281; + wire [11:0] _zz_282; + wire [31:0] _zz_283; + wire [31:0] _zz_284; + wire [31:0] _zz_285; + wire [11:0] _zz_286; + wire [19:0] _zz_287; + wire [11:0] _zz_288; + wire [2:0] _zz_289; + wire [1:0] _zz_290; + wire [1:0] _zz_291; + wire [65:0] _zz_292; + wire [65:0] _zz_293; + wire [31:0] _zz_294; + wire [31:0] _zz_295; + wire [0:0] _zz_296; + wire [5:0] _zz_297; + wire [32:0] _zz_298; + wire [31:0] _zz_299; + wire [31:0] _zz_300; + wire [32:0] _zz_301; + wire [32:0] _zz_302; + wire [32:0] _zz_303; + wire [32:0] _zz_304; + wire [0:0] _zz_305; + wire [32:0] _zz_306; + wire [0:0] _zz_307; + wire [32:0] _zz_308; + wire [0:0] _zz_309; + wire [31:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [26:0] _zz_317; + wire _zz_318; + wire _zz_319; + wire [1:0] _zz_320; + wire [31:0] _zz_321; + wire [31:0] _zz_322; + wire [31:0] _zz_323; + wire _zz_324; + wire [0:0] _zz_325; + wire [13:0] _zz_326; + wire [31:0] _zz_327; + wire [31:0] _zz_328; + wire [31:0] _zz_329; + wire _zz_330; + wire [0:0] _zz_331; + wire [7:0] _zz_332; + wire [31:0] _zz_333; + wire [31:0] _zz_334; + wire [31:0] _zz_335; + wire _zz_336; + wire [0:0] _zz_337; + wire [1:0] _zz_338; + wire _zz_339; + wire _zz_340; + wire _zz_341; + wire [31:0] _zz_342; + wire [31:0] _zz_343; + wire _zz_344; + wire [0:0] _zz_345; + wire [0:0] _zz_346; + wire _zz_347; + wire [0:0] _zz_348; + wire [24:0] _zz_349; + wire [31:0] _zz_350; + wire _zz_351; + wire _zz_352; + wire [0:0] _zz_353; + wire [0:0] _zz_354; + wire [0:0] _zz_355; + wire [0:0] _zz_356; + wire _zz_357; + wire [0:0] _zz_358; + wire [20:0] _zz_359; + wire [31:0] _zz_360; + wire [31:0] _zz_361; + wire _zz_362; + wire _zz_363; + wire [0:0] _zz_364; + wire [1:0] _zz_365; + wire [0:0] _zz_366; + wire [0:0] _zz_367; + wire _zz_368; + wire [0:0] _zz_369; + wire [17:0] _zz_370; + wire [31:0] _zz_371; + wire [31:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; + wire [31:0] _zz_375; + wire [31:0] _zz_376; + wire [31:0] _zz_377; + wire [31:0] _zz_378; + wire _zz_379; + wire [1:0] _zz_380; + wire [1:0] _zz_381; + wire _zz_382; + wire [0:0] _zz_383; + wire [14:0] _zz_384; + wire [31:0] _zz_385; + wire [31:0] _zz_386; + wire [31:0] _zz_387; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire [0:0] _zz_391; + wire [0:0] _zz_392; + wire [2:0] _zz_393; + wire [2:0] _zz_394; + wire _zz_395; + wire [0:0] _zz_396; + wire [11:0] _zz_397; + wire [31:0] _zz_398; + wire [31:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; + wire _zz_402; + wire _zz_403; + wire [31:0] _zz_404; + wire [31:0] _zz_405; + wire [0:0] _zz_406; + wire [3:0] _zz_407; + wire [4:0] _zz_408; + wire [4:0] _zz_409; + wire _zz_410; + wire [0:0] _zz_411; + wire [8:0] _zz_412; + wire [31:0] _zz_413; + wire [31:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [0:0] _zz_417; + wire [1:0] _zz_418; + wire [0:0] _zz_419; + wire [2:0] _zz_420; + wire [0:0] _zz_421; + wire [4:0] _zz_422; + wire [1:0] _zz_423; + wire [1:0] _zz_424; + wire _zz_425; + wire [0:0] _zz_426; + wire [6:0] _zz_427; + wire [31:0] _zz_428; + wire [31:0] _zz_429; + wire _zz_430; + wire _zz_431; + wire [31:0] _zz_432; + wire [31:0] _zz_433; + wire _zz_434; + wire [0:0] _zz_435; + wire [0:0] _zz_436; + wire _zz_437; + wire [0:0] _zz_438; + wire [2:0] _zz_439; + wire _zz_440; + wire [0:0] _zz_441; + wire [0:0] _zz_442; + wire [0:0] _zz_443; + wire [0:0] _zz_444; + wire _zz_445; + wire [0:0] _zz_446; + wire [4:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire [31:0] _zz_450; + wire [31:0] _zz_451; + wire [31:0] _zz_452; + wire [31:0] _zz_453; + wire [31:0] _zz_454; + wire [31:0] _zz_455; + wire [31:0] _zz_456; + wire [31:0] _zz_457; + wire _zz_458; + wire [0:0] _zz_459; + wire [0:0] _zz_460; + wire [31:0] _zz_461; + wire [31:0] _zz_462; + wire [31:0] _zz_463; + wire [31:0] _zz_464; + wire [31:0] _zz_465; + wire _zz_466; + wire [3:0] _zz_467; + wire [3:0] _zz_468; + wire _zz_469; + wire [0:0] _zz_470; + wire [2:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; + wire [31:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; + wire [31:0] _zz_477; + wire _zz_478; + wire [0:0] _zz_479; + wire [1:0] _zz_480; + wire _zz_481; + wire [2:0] _zz_482; + wire [2:0] _zz_483; + wire _zz_484; + wire [0:0] _zz_485; + wire [0:0] _zz_486; + wire [31:0] _zz_487; + wire [31:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; + wire [31:0] _zz_491; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire _zz_494; + wire _zz_495; + wire _zz_496; + wire [0:0] _zz_497; + wire [0:0] _zz_498; + wire _zz_499; + wire _zz_500; + wire _zz_501; + wire _zz_502; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_31; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_35; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_36; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; + wire [31:0] _zz_40; + wire _zz_41; + reg _zz_42; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_43; + wire `BranchCtrlEnum_defaultEncoding_type _zz_44; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; + wire `Src2CtrlEnum_defaultEncoding_type _zz_47; + wire `AluCtrlEnum_defaultEncoding_type _zz_48; + wire `Src1CtrlEnum_defaultEncoding_type _zz_49; + reg [31:0] _zz_50; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_52; + reg [31:0] _zz_53; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_54; + wire [3:0] _zz_55; + wire _zz_56; + wire _zz_57; + wire _zz_58; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_59; + wire _zz_60; + wire _zz_61; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_62; + wire _zz_63; + reg _zz_64; + wire _zz_65; + reg _zz_66; + reg [31:0] _zz_67; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_68; + reg [18:0] _zz_69; + wire _zz_70; + reg [10:0] _zz_71; + wire _zz_72; + reg [18:0] _zz_73; + reg _zz_74; + wire _zz_75; + reg [10:0] _zz_76; + wire _zz_77; + reg [18:0] _zz_78; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_79; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_80; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_81; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_82; + reg [31:0] _zz_83; + wire _zz_84; + reg [31:0] _zz_85; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [31:0] _zz_86; + wire _zz_87; + wire _zz_88; + wire _zz_89; + wire _zz_90; + wire `Src1CtrlEnum_defaultEncoding_type _zz_91; + wire `AluCtrlEnum_defaultEncoding_type _zz_92; + wire `Src2CtrlEnum_defaultEncoding_type _zz_93; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_94; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_95; + wire `BranchCtrlEnum_defaultEncoding_type _zz_96; + wire `EnvCtrlEnum_defaultEncoding_type _zz_97; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_98; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_99; + reg [31:0] _zz_100; + wire _zz_101; + reg [19:0] _zz_102; + wire _zz_103; + reg [19:0] _zz_104; + reg [31:0] _zz_105; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_106; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_107; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_108; + wire _zz_109; + wire _zz_110; + wire _zz_111; + wire _zz_112; + wire _zz_113; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_114; + reg _zz_115; + reg _zz_116; + wire _zz_117; + reg [19:0] _zz_118; + wire _zz_119; + reg [10:0] _zz_120; + wire _zz_121; + reg [18:0] _zz_122; + reg _zz_123; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_124; + reg [19:0] _zz_125; + wire _zz_126; + reg [10:0] _zz_127; + wire _zz_128; + reg [18:0] _zz_129; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_130; + wire _zz_131; + wire _zz_132; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_133; + wire _zz_134; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_135; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_136; + wire _zz_137; + wire _zz_138; + reg [32:0] _zz_139; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_140; + wire [31:0] _zz_141; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_142; + reg [31:0] _zz_143; + reg [31:0] _zz_144; + reg [31:0] _zz_145; + reg [31:0] _zz_146; + reg [31:0] _zz_147; + reg [31:0] _zz_148; + reg [31:0] _zz_149; + reg [31:0] _zz_150; + reg [2:0] _zz_151; + reg _zz_152; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_153; + wire _zz_154; + wire _zz_155; + wire _zz_156; + wire _zz_157; + wire _zz_158; + reg _zz_159; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [23:0] _zz_20_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [63:0] _zz_23_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; + reg [95:0] _zz_26_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_27_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_29_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_30_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_33_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_34_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_36_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_37_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_39_string; + reg [39:0] _zz_43_string; + reg [31:0] _zz_44_string; + reg [71:0] _zz_45_string; + reg [39:0] _zz_46_string; + reg [23:0] _zz_47_string; + reg [63:0] _zz_48_string; + reg [95:0] _zz_49_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_51_string; + reg [95:0] _zz_91_string; + reg [63:0] _zz_92_string; + reg [23:0] _zz_93_string; + reg [39:0] _zz_94_string; + reg [71:0] _zz_95_string; + reg [31:0] _zz_96_string; + reg [39:0] _zz_97_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire [0:0] _zz_14_; - wire [0:0] _zz_15_; - wire [21:0] _zz_16_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [6:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_7_; - wire [9:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - reg [31:0] io_cpu_fetch_data_regNextWhen; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_hit_valid; - reg decodeStage_hit_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; - assign _zz_12_ = (! lineLoader_flushCounter[7]); - assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_14_ = _zz_7_[0 : 0]; - assign _zz_15_ = _zz_7_[1 : 1]; - assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; - end - end + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_191 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_192 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_193 = 1'b1; + assign _zz_194 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_195 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_196 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_197 = ((_zz_165 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_198 = ((_zz_165 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_199 = ((_zz_165 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_200 = ((_zz_165 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_201 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_202 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_203 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_204 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_205 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_206 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_207 = (1'b0 || (! 1'b1)); + assign _zz_208 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_209 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_210 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_211 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_212 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_213 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_214 = execute_INSTRUCTION[13 : 12]; + assign _zz_215 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_216 = (! memory_arbitration_isStuck); + assign _zz_217 = (iBus_cmd_valid || (_zz_151 != 3'b000)); + assign _zz_218 = (_zz_187 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_219 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_220 = ((_zz_130 && 1'b1) && (! 1'b0)); + assign _zz_221 = ((_zz_131 && 1'b1) && (! 1'b0)); + assign _zz_222 = ((_zz_132 && 1'b1) && (! 1'b0)); + assign _zz_223 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_224 = execute_INSTRUCTION[13]; + assign _zz_225 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_226 = ($signed(_zz_227) + $signed(_zz_232)); + assign _zz_227 = ($signed(_zz_228) + $signed(_zz_230)); + assign _zz_228 = 52'h0; + assign _zz_229 = {1'b0,memory_MUL_LL}; + assign _zz_230 = {{19{_zz_229[32]}}, _zz_229}; + assign _zz_231 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_232 = {{2{_zz_231[49]}}, _zz_231}; + assign _zz_233 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_234 = {{2{_zz_233[49]}}, _zz_233}; + assign _zz_235 = ($signed(_zz_237) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_236 = _zz_235[31 : 0]; + assign _zz_237 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_238 = _zz_86[31 : 31]; + assign _zz_239 = _zz_86[30 : 30]; + assign _zz_240 = _zz_86[29 : 29]; + assign _zz_241 = _zz_86[28 : 28]; + assign _zz_242 = _zz_86[25 : 25]; + assign _zz_243 = _zz_86[17 : 17]; + assign _zz_244 = _zz_86[16 : 16]; + assign _zz_245 = _zz_86[13 : 13]; + assign _zz_246 = _zz_86[12 : 12]; + assign _zz_247 = _zz_86[11 : 11]; + assign _zz_248 = _zz_86[15 : 15]; + assign _zz_249 = _zz_86[5 : 5]; + assign _zz_250 = _zz_86[3 : 3]; + assign _zz_251 = _zz_86[20 : 20]; + assign _zz_252 = _zz_86[10 : 10]; + assign _zz_253 = _zz_86[4 : 4]; + assign _zz_254 = _zz_86[0 : 0]; + assign _zz_255 = (_zz_54 - 4'b0001); + assign _zz_256 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_257 = {29'd0, _zz_256}; + assign _zz_258 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_259 = {{_zz_69,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_260 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_261 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_262 = {{_zz_71,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_263 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_264 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_265 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_266 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_267 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_268 = execute_SRC_LESS; + assign _zz_269 = 3'b100; + assign _zz_270 = execute_INSTRUCTION[19 : 15]; + assign _zz_271 = execute_INSTRUCTION[31 : 20]; + assign _zz_272 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_273 = ($signed(_zz_274) + $signed(_zz_277)); + assign _zz_274 = ($signed(_zz_275) + $signed(_zz_276)); + assign _zz_275 = execute_SRC1; + assign _zz_276 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_277 = (execute_SRC_USE_SUB_LESS ? _zz_278 : _zz_279); + assign _zz_278 = 32'h00000001; + assign _zz_279 = 32'h0; + assign _zz_280 = execute_INSTRUCTION[31 : 20]; + assign _zz_281 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_282 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_283 = {_zz_118,execute_INSTRUCTION[31 : 20]}; + assign _zz_284 = {{_zz_120,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_285 = {{_zz_122,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_286 = execute_INSTRUCTION[31 : 20]; + assign _zz_287 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_288 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_289 = 3'b100; + assign _zz_290 = (_zz_133 & (~ _zz_291)); + assign _zz_291 = (_zz_133 - 2'b01); + assign _zz_292 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_293 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_294 = writeBack_MUL_LOW[31 : 0]; + assign _zz_295 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_296 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_297 = {5'd0, _zz_296}; + assign _zz_298 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_299 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_300 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_301 = {_zz_135,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_302 = _zz_303; + assign _zz_303 = _zz_304; + assign _zz_304 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_136) : _zz_136)} + _zz_306); + assign _zz_305 = memory_DivPlugin_div_needRevert; + assign _zz_306 = {32'd0, _zz_305}; + assign _zz_307 = _zz_138; + assign _zz_308 = {32'd0, _zz_307}; + assign _zz_309 = _zz_137; + assign _zz_310 = {31'd0, _zz_309}; + assign _zz_311 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_312 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_313 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_314 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_315 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_316 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_317 = (iBus_cmd_payload_address >>> 5); + assign _zz_318 = 1'b1; + assign _zz_319 = 1'b1; + assign _zz_320 = {_zz_58,_zz_57}; + assign _zz_321 = 32'h0000107f; + assign _zz_322 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_323 = 32'h00002073; + assign _zz_324 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_325 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_326 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_327) == 32'h00000003),{(_zz_328 == _zz_329),{_zz_330,{_zz_331,_zz_332}}}}}}; + assign _zz_327 = 32'h0000505f; + assign _zz_328 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_329 = 32'h00000063; + assign _zz_330 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_331 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_332 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_333) == 32'h00001013),{(_zz_334 == _zz_335),{_zz_336,{_zz_337,_zz_338}}}}}}; + assign _zz_333 = 32'hfc00307f; + assign _zz_334 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_335 = 32'h00005033; + assign _zz_336 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_337 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_338 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_339 = decode_INSTRUCTION[31]; + assign _zz_340 = decode_INSTRUCTION[31]; + assign _zz_341 = decode_INSTRUCTION[7]; + assign _zz_342 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_343 = 32'h02004020; + assign _zz_344 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_345 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz_346 = 1'b0; + assign _zz_347 = (((decode_INSTRUCTION & _zz_350) == 32'h10000050) != 1'b0); + assign _zz_348 = ({_zz_351,_zz_352} != 2'b00); + assign _zz_349 = {({_zz_353,_zz_354} != 2'b00),{(_zz_355 != _zz_356),{_zz_357,{_zz_358,_zz_359}}}}; + assign _zz_350 = 32'h10403050; + assign _zz_351 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_352 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_353 = _zz_89; + assign _zz_354 = ((decode_INSTRUCTION & _zz_360) == 32'h00000004); + assign _zz_355 = ((decode_INSTRUCTION & _zz_361) == 32'h00000040); + assign _zz_356 = 1'b0; + assign _zz_357 = ({_zz_362,_zz_363} != 2'b00); + assign _zz_358 = ({_zz_364,_zz_365} != 3'b000); + assign _zz_359 = {(_zz_366 != _zz_367),{_zz_368,{_zz_369,_zz_370}}}; + assign _zz_360 = 32'h0000001c; + assign _zz_361 = 32'h00000058; + assign _zz_362 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_363 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_364 = ((decode_INSTRUCTION & _zz_371) == 32'h40001010); + assign _zz_365 = {(_zz_372 == _zz_373),(_zz_374 == _zz_375)}; + assign _zz_366 = ((decode_INSTRUCTION & _zz_376) == 32'h00000024); + assign _zz_367 = 1'b0; + assign _zz_368 = ((_zz_377 == _zz_378) != 1'b0); + assign _zz_369 = (_zz_379 != 1'b0); + assign _zz_370 = {(_zz_380 != _zz_381),{_zz_382,{_zz_383,_zz_384}}}; + assign _zz_371 = 32'h40003054; + assign _zz_372 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_373 = 32'h00001010; + assign _zz_374 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_375 = 32'h00001010; + assign _zz_376 = 32'h00000064; + assign _zz_377 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_378 = 32'h00001000; + assign _zz_379 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_380 = {(_zz_385 == _zz_386),(_zz_387 == _zz_388)}; + assign _zz_381 = 2'b00; + assign _zz_382 = ((_zz_389 == _zz_390) != 1'b0); + assign _zz_383 = ({_zz_391,_zz_392} != 2'b00); + assign _zz_384 = {(_zz_393 != _zz_394),{_zz_395,{_zz_396,_zz_397}}}; + assign _zz_385 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_386 = 32'h00002000; + assign _zz_387 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_388 = 32'h00001000; + assign _zz_389 = (decode_INSTRUCTION & 32'h00004048); + assign _zz_390 = 32'h00004008; + assign _zz_391 = ((decode_INSTRUCTION & _zz_398) == 32'h00000020); + assign _zz_392 = ((decode_INSTRUCTION & _zz_399) == 32'h00000020); + assign _zz_393 = {(_zz_400 == _zz_401),{_zz_402,_zz_403}}; + assign _zz_394 = 3'b000; + assign _zz_395 = ((_zz_404 == _zz_405) != 1'b0); + assign _zz_396 = ({_zz_406,_zz_407} != 5'h0); + assign _zz_397 = {(_zz_408 != _zz_409),{_zz_410,{_zz_411,_zz_412}}}; + assign _zz_398 = 32'h00000034; + assign _zz_399 = 32'h00000064; + assign _zz_400 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_401 = 32'h00000040; + assign _zz_402 = ((decode_INSTRUCTION & _zz_413) == 32'h0); + assign _zz_403 = ((decode_INSTRUCTION & _zz_414) == 32'h00000040); + assign _zz_404 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_405 = 32'h00000020; + assign _zz_406 = (_zz_415 == _zz_416); + assign _zz_407 = {_zz_88,{_zz_417,_zz_418}}; + assign _zz_408 = {_zz_88,{_zz_419,_zz_420}}; + assign _zz_409 = 5'h0; + assign _zz_410 = ({_zz_421,_zz_422} != 6'h0); + assign _zz_411 = (_zz_423 != _zz_424); + assign _zz_412 = {_zz_425,{_zz_426,_zz_427}}; + assign _zz_413 = 32'h00000038; + assign _zz_414 = 32'h00403040; + assign _zz_415 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_416 = 32'h00000040; + assign _zz_417 = (_zz_428 == _zz_429); + assign _zz_418 = {_zz_430,_zz_431}; + assign _zz_419 = (_zz_432 == _zz_433); + assign _zz_420 = {_zz_434,{_zz_435,_zz_436}}; + assign _zz_421 = _zz_89; + assign _zz_422 = {_zz_437,{_zz_438,_zz_439}}; + assign _zz_423 = {_zz_88,_zz_440}; + assign _zz_424 = 2'b00; + assign _zz_425 = ({_zz_441,_zz_442} != 2'b00); + assign _zz_426 = (_zz_443 != _zz_444); + assign _zz_427 = {_zz_445,{_zz_446,_zz_447}}; + assign _zz_428 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_429 = 32'h00004020; + assign _zz_430 = ((decode_INSTRUCTION & _zz_448) == 32'h00000010); + assign _zz_431 = ((decode_INSTRUCTION & _zz_449) == 32'h00000020); + assign _zz_432 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_433 = 32'h00002010; + assign _zz_434 = ((decode_INSTRUCTION & _zz_450) == 32'h00000010); + assign _zz_435 = (_zz_451 == _zz_452); + assign _zz_436 = (_zz_453 == _zz_454); + assign _zz_437 = ((decode_INSTRUCTION & _zz_455) == 32'h00001010); + assign _zz_438 = (_zz_456 == _zz_457); + assign _zz_439 = {_zz_458,{_zz_459,_zz_460}}; + assign _zz_440 = ((decode_INSTRUCTION & _zz_461) == 32'h00000020); + assign _zz_441 = _zz_88; + assign _zz_442 = (_zz_462 == _zz_463); + assign _zz_443 = (_zz_464 == _zz_465); + assign _zz_444 = 1'b0; + assign _zz_445 = (_zz_466 != 1'b0); + assign _zz_446 = (_zz_467 != _zz_468); + assign _zz_447 = {_zz_469,{_zz_470,_zz_471}}; + assign _zz_448 = 32'h00000030; + assign _zz_449 = 32'h02000020; + assign _zz_450 = 32'h00001030; + assign _zz_451 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_452 = 32'h00002020; + assign _zz_453 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_454 = 32'h00000020; + assign _zz_455 = 32'h00001010; + assign _zz_456 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_457 = 32'h00002010; + assign _zz_458 = ((decode_INSTRUCTION & _zz_472) == 32'h00000010); + assign _zz_459 = (_zz_473 == _zz_474); + assign _zz_460 = (_zz_475 == _zz_476); + assign _zz_461 = 32'h00000070; + assign _zz_462 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_463 = 32'h0; + assign _zz_464 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_465 = 32'h00004010; + assign _zz_466 = ((decode_INSTRUCTION & _zz_477) == 32'h00002010); + assign _zz_467 = {_zz_478,{_zz_479,_zz_480}}; + assign _zz_468 = 4'b0000; + assign _zz_469 = (_zz_481 != 1'b0); + assign _zz_470 = (_zz_482 != _zz_483); + assign _zz_471 = {_zz_484,{_zz_485,_zz_486}}; + assign _zz_472 = 32'h00000050; + assign _zz_473 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_474 = 32'h00000004; + assign _zz_475 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_476 = 32'h0; + assign _zz_477 = 32'h00006014; + assign _zz_478 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_479 = ((decode_INSTRUCTION & _zz_487) == 32'h0); + assign _zz_480 = {(_zz_488 == _zz_489),(_zz_490 == _zz_491)}; + assign _zz_481 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_482 = {(_zz_492 == _zz_493),{_zz_494,_zz_495}}; + assign _zz_483 = 3'b000; + assign _zz_484 = ({_zz_496,_zz_87} != 2'b00); + assign _zz_485 = ({_zz_497,_zz_498} != 2'b00); + assign _zz_486 = (_zz_499 != 1'b0); + assign _zz_487 = 32'h00000018; + assign _zz_488 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_489 = 32'h00002000; + assign _zz_490 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_491 = 32'h00001000; + assign _zz_492 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_493 = 32'h00000040; + assign _zz_494 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_495 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_496 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_497 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_498 = _zz_87; + assign _zz_499 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_500 = execute_INSTRUCTION[31]; + assign _zz_501 = execute_INSTRUCTION[31]; + assign _zz_502 = execute_INSTRUCTION[7]; always @ (posedge clk) begin - if(_zz_6_) begin - _zz_10_ <= ways_0_tags[_zz_5_]; + if(_zz_318) begin + _zz_188 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + if(_zz_319) begin + _zz_189 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_9_) begin - _zz_11_ <= ways_0_datas[_zz_8_]; - end - end - - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; - end - end - - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; - end - end - - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; - end - end - end - - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_12_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; + if(_zz_42) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_10_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_11_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; - end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; - end - if(_zz_13_)begin - lineLoader_flushPending <= 1'b0; + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_160 ), //i + .io_cpu_prefetch_isValid (_zz_161 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_162 ), //i + .io_cpu_fetch_isStuck (_zz_163 ), //i + .io_cpu_fetch_isRemoved (_zz_164 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_165 ), //i + .io_cpu_decode_isStuck (_zz_166 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_167 ), //i + .io_cpu_fill_valid (_zz_168 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_169 ), //i + .io_cpu_execute_address (_zz_170[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_81[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_171 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_172[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_173 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_174 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_175 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_176[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_177 ), //i + .io_cpu_writeBack_fence_SR (_zz_178 ), //i + .io_cpu_writeBack_fence_SO (_zz_179 ), //i + .io_cpu_writeBack_fence_SI (_zz_180 ), //i + .io_cpu_writeBack_fence_PW (_zz_181 ), //i + .io_cpu_writeBack_fence_PR (_zz_182 ), //i + .io_cpu_writeBack_fence_PO (_zz_183 ), //i + .io_cpu_writeBack_fence_PI (_zz_184 ), //i + .io_cpu_writeBack_fence_FM (_zz_185[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_186 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_187 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_320) + 2'b00 : begin + _zz_190 = DBusCachedPlugin_redoBranch_payload; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; + 2'b01 : begin + _zz_190 = CsrPlugin_jumpInterface_payload; end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; + 2'b10 : begin + _zz_190 = BranchPlugin_jumpInterface_payload; end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end + default : begin + _zz_190 = IBusCachedPlugin_predictionJumpInterface_payload; end - end - end - - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_12_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); - end - _zz_3_ <= lineLoader_flushCounter[7]; - if(_zz_13_)begin - lineLoader_flushCounter <= (8'b00000000); - end - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_error <= fetchStage_hit_error; - end + endcase end -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, - input [1:0] io_cpu_execute_args_size, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - input io_cpu_memory_isRemoved, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - output io_cpu_memory_mmuBus_cmd_isValid, - output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, - output io_cpu_memory_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, - input io_cpu_memory_mmuBus_rsp_isIoAccess, - input io_cpu_memory_mmuBus_rsp_allowRead, - input io_cpu_memory_mmuBus_rsp_allowWrite, - input io_cpu_memory_mmuBus_rsp_allowExecute, - input io_cpu_memory_mmuBus_rsp_exception, - input io_cpu_memory_mmuBus_rsp_refilling, - output io_cpu_memory_mmuBus_end, - input io_cpu_memory_mmuBus_busy, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output reg io_cpu_flush_ready, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, - output reg io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire _zz_16_; - wire _zz_17_; - wire [0:0] _zz_18_; - wire [0:0] _zz_19_; - wire [0:0] _zz_20_; - wire [2:0] _zz_21_; - wire [1:0] _zz_22_; - wire [21:0] _zz_23_; - reg _zz_1_; - reg _zz_2_; - wire haltCpu; - reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3_; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4_; - wire _zz_5_; - wire [31:0] ways_0_dataReadRsp; - reg [3:0] _zz_6_; - wire [3:0] stage0_mask; - wire [0:0] stage0_colisions; - reg stageA_request_wr; - reg [31:0] stageA_request_data; - reg [1:0] stageA_request_size; - reg [3:0] stageA_mask; - wire stageA_wayHits_0; - reg [0:0] stage0_colisions_regNextWhen; - wire [0:0] _zz_7_; - wire [0:0] stageA_colisions; - reg stageB_request_wr; - reg [31:0] stageB_request_data; - reg [1:0] stageB_request_size; - reg stageB_mmuRspFreeze; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg [31:0] stageB_dataReadRsp_0; - wire [0:0] _zz_8_; - reg [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - reg [3:0] stageB_mask; - reg [0:0] stageB_colisions; - reg stageB_loaderValid; - reg stageB_flusher_valid; - wire [31:0] stageB_requestDataBypass; - wire stageB_isAmo; - reg stageB_memCmdSent; - wire [0:0] _zz_9_; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [2:0] loader_counter_valueNext; - reg [2:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_24_; - reg [7:0] _zz_25_; - reg [7:0] _zz_26_; - reg [7:0] _zz_27_; - assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); - assign _zz_15_ = (loader_valid && io_mem_rsp_valid); - assign _zz_16_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - assign _zz_17_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign _zz_18_ = _zz_4_[0 : 0]; - assign _zz_19_ = _zz_4_[1 : 1]; - assign _zz_20_ = loader_counter_willIncrement; - assign _zz_21_ = {2'd0, _zz_20_}; - assign _zz_22_ = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_23_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_23_; - end + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_3_) begin - _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; - end + always @(*) begin + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; + endcase end - - always @ (*) begin - _zz_11_ = {_zz_27_, _zz_26_, _zz_25_, _zz_24_}; + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase end - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1_) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1_) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1_) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1_) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_5_) begin - _zz_24_ <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_25_ <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_26_ <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_27_ <= ways_0_data_symbol3[dataReadCmd_payload]; - end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase end - - always @ (*) begin - _zz_1_ = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_1_ = 1'b1; - end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase end - - always @ (*) begin - _zz_2_ = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_2_ = 1'b1; - end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase end - - assign haltCpu = 1'b0; - assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4_ = _zz_10_; - assign ways_0_tagsReadRsp_valid = _zz_18_[0]; - assign ways_0_tagsReadRsp_error = _zz_19_[0]; - assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; - assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRsp = _zz_11_; - always @ (*) begin - tagsReadCmd_valid = 1'b0; - if(_zz_12_)begin - tagsReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase end - - always @ (*) begin - tagsReadCmd_payload = (7'bxxxxxxx); - if(_zz_12_)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; - end + always @(*) begin + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_valid = 1'b0; - if(_zz_12_)begin - dataReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_payload = (10'bxxxxxxxxxx); - if(_zz_12_)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end + always @(*) begin + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; - end - if(_zz_13_)begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_valid = 1'b1; - end - end - - always @ (*) begin - tagsWriteCmd_payload_way = (1'bx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = (1'b1); - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_address = (7'bxxxxxxx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_valid = 1'b1; - end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); - end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase end - - always @ (*) begin - dataWriteCmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((stageB_request_wr && stageB_waysHit))begin - dataWriteCmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - dataWriteCmd_valid = 1'b0; - end - if(_zz_15_)begin - dataWriteCmd_valid = 1'b1; - end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_way = (1'bx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_way = stageB_waysHits; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_address = (10'bxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; - end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_data = stageB_requestDataBypass; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_mask = (4'bxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_mask = stageB_mask; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_mask = (4'b1111); - end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase end - - always @ (*) begin - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_6_ = (4'b0001); - end - 2'b01 : begin - _zz_6_ = (4'b0011); - end - default : begin - _zz_6_ = (4'b1111); - end + always @(*) begin + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; endcase end - - assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); - assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; - assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; - assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); - always @ (*) begin - stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin - stageB_mmuRspFreeze = 1'b1; - end + always @(*) begin + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; + endcase end - - assign _zz_8_[0] = stageA_wayHits_0; - assign stageB_waysHit = (stageB_waysHits != (1'b0)); - assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - if(io_mem_cmd_ready)begin - stageB_loaderValid = 1'b1; - end - end - end - end - if(_zz_13_)begin - stageB_loaderValid = 1'b0; - end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; + endcase end - - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(_zz_14_)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - if(_zz_13_)begin - io_cpu_writeBack_haltIt = 1'b0; - end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(_zz_16_)begin - io_cpu_flush_ready = 1'b1; - end + always @(*) begin + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; + endcase end - - assign stageB_requestDataBypass = stageB_request_data; - assign stageB_isAmo = 1'b0; - always @ (*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin - io_cpu_redo = 1'b1; - end - end - end - end - if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin - io_cpu_redo = 1'b1; - end - if(loader_valid)begin - io_cpu_redo = 1'b1; - end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); - end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase end - - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_valid = (! stageB_memCmdSent); - end else begin - if(_zz_14_)begin - if(stageB_request_wr)begin - io_mem_cmd_valid = 1'b1; - end - end else begin - if((! stageB_memCmdSent))begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - io_mem_cmd_valid = 1'b0; - end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; - end - end - end + always @(*) begin + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_length = (3'bxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - io_mem_cmd_payload_length = (3'b111); - end - end - end + always @(*) begin + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_last = 1'bx; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - io_mem_cmd_payload_last = 1'b1; - end - end - end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - always @ (*) begin - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_data = io_mem_rsp_payload_data; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end + always @(*) begin + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; + endcase end - - assign _zz_9_[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin - loader_counter_willIncrement = 1'b0; - if(_zz_15_)begin - loader_counter_willIncrement = 1'b1; - end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_21_); - if(loader_counter_willClear)begin - loader_counter_valueNext = (3'b000); - end + always @(*) begin + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; + endcase end - - always @ (posedge clk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; - stageA_request_size <= io_cpu_execute_args_size; - end - if((! io_cpu_memory_isStuck))begin - stageA_mask <= stage0_mask; - end - if((! io_cpu_memory_isStuck))begin - stage0_colisions_regNextWhen <= stage0_colisions; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; - stageB_request_size <= stageA_request_size; - end - if(_zz_17_)begin - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_waysHits <= _zz_8_; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_mask <= stageA_mask; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_colisions <= stageA_colisions; - end - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); - end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(reset) begin - stageB_flusher_valid <= 1'b1; - stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); - stageB_memCmdSent <= 1'b0; - loader_valid <= 1'b0; - loader_counter_value <= (3'b000); - loader_waysAllocator <= (1'b1); - loader_error <= 1'b0; - end else begin - if(_zz_17_)begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; - end - if(stageB_flusher_valid)begin - if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); - end else begin - stageB_flusher_valid <= 1'b0; - end - end - if(_zz_16_)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); - stageB_flusher_valid <= 1'b1; - end - if(io_mem_cmd_ready)begin - stageB_memCmdSent <= 1'b1; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_memCmdSent <= 1'b0; - end - if(stageB_loaderValid)begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(_zz_15_)begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_counter_willOverflow)begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - end - if((! loader_valid))begin - loader_waysAllocator <= _zz_22_[0:0]; - end - end + always @(*) begin + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; + endcase end - -endmodule - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset); - wire _zz_221_; - wire _zz_222_; - wire _zz_223_; - wire _zz_224_; - wire [31:0] _zz_225_; - wire _zz_226_; - wire _zz_227_; - wire _zz_228_; - reg _zz_229_; - wire _zz_230_; - wire [31:0] _zz_231_; - wire _zz_232_; - wire [31:0] _zz_233_; - reg _zz_234_; - wire _zz_235_; - wire _zz_236_; - wire [31:0] _zz_237_; - wire _zz_238_; - wire _zz_239_; - reg [31:0] _zz_240_; - reg [31:0] _zz_241_; - reg [31:0] _zz_242_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1__io_cpu_memory_isWrite; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; - wire dataCache_1__io_cpu_memory_mmuBus_end; - wire dataCache_1__io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1__io_cpu_writeBack_data; - wire dataCache_1__io_cpu_writeBack_mmuException; - wire dataCache_1__io_cpu_writeBack_unalignedAccess; - wire dataCache_1__io_cpu_writeBack_accessError; - wire dataCache_1__io_cpu_writeBack_isWrite; - wire dataCache_1__io_cpu_flush_ready; - wire dataCache_1__io_cpu_redo; - wire dataCache_1__io_mem_cmd_valid; - wire dataCache_1__io_mem_cmd_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_payload_length; - wire dataCache_1__io_mem_cmd_payload_last; - wire _zz_243_; - wire _zz_244_; - wire _zz_245_; - wire _zz_246_; - wire _zz_247_; - wire _zz_248_; - wire _zz_249_; - wire _zz_250_; - wire _zz_251_; - wire _zz_252_; - wire _zz_253_; - wire _zz_254_; - wire _zz_255_; - wire _zz_256_; - wire [1:0] _zz_257_; - wire _zz_258_; - wire _zz_259_; - wire _zz_260_; - wire _zz_261_; - wire _zz_262_; - wire _zz_263_; - wire _zz_264_; - wire _zz_265_; - wire _zz_266_; - wire [1:0] _zz_267_; - wire _zz_268_; - wire _zz_269_; - wire _zz_270_; - wire _zz_271_; - wire _zz_272_; - wire _zz_273_; - wire _zz_274_; - wire [1:0] _zz_275_; - wire _zz_276_; - wire [1:0] _zz_277_; - wire [4:0] _zz_278_; - wire [2:0] _zz_279_; - wire [31:0] _zz_280_; - wire [11:0] _zz_281_; - wire [31:0] _zz_282_; - wire [19:0] _zz_283_; - wire [11:0] _zz_284_; - wire [31:0] _zz_285_; - wire [31:0] _zz_286_; - wire [19:0] _zz_287_; - wire [11:0] _zz_288_; - wire [2:0] _zz_289_; - wire [2:0] _zz_290_; - wire [0:0] _zz_291_; - wire [0:0] _zz_292_; - wire [0:0] _zz_293_; - wire [0:0] _zz_294_; - wire [0:0] _zz_295_; - wire [0:0] _zz_296_; - wire [0:0] _zz_297_; - wire [0:0] _zz_298_; - wire [0:0] _zz_299_; - wire [0:0] _zz_300_; - wire [0:0] _zz_301_; - wire [0:0] _zz_302_; - wire [0:0] _zz_303_; - wire [0:0] _zz_304_; - wire [0:0] _zz_305_; - wire [0:0] _zz_306_; - wire [0:0] _zz_307_; - wire [0:0] _zz_308_; - wire [2:0] _zz_309_; - wire [4:0] _zz_310_; - wire [11:0] _zz_311_; - wire [11:0] _zz_312_; - wire [31:0] _zz_313_; - wire [31:0] _zz_314_; - wire [31:0] _zz_315_; - wire [31:0] _zz_316_; - wire [31:0] _zz_317_; - wire [31:0] _zz_318_; - wire [31:0] _zz_319_; - wire [32:0] _zz_320_; - wire [31:0] _zz_321_; - wire [32:0] _zz_322_; - wire [11:0] _zz_323_; - wire [19:0] _zz_324_; - wire [11:0] _zz_325_; - wire [31:0] _zz_326_; - wire [31:0] _zz_327_; - wire [31:0] _zz_328_; - wire [11:0] _zz_329_; - wire [19:0] _zz_330_; - wire [11:0] _zz_331_; - wire [2:0] _zz_332_; - wire [1:0] _zz_333_; - wire [1:0] _zz_334_; - wire [51:0] _zz_335_; - wire [51:0] _zz_336_; - wire [51:0] _zz_337_; - wire [32:0] _zz_338_; - wire [51:0] _zz_339_; - wire [49:0] _zz_340_; - wire [51:0] _zz_341_; - wire [49:0] _zz_342_; - wire [51:0] _zz_343_; - wire [65:0] _zz_344_; - wire [65:0] _zz_345_; - wire [31:0] _zz_346_; - wire [31:0] _zz_347_; - wire [0:0] _zz_348_; - wire [5:0] _zz_349_; - wire [32:0] _zz_350_; - wire [32:0] _zz_351_; - wire [31:0] _zz_352_; - wire [31:0] _zz_353_; - wire [32:0] _zz_354_; - wire [32:0] _zz_355_; - wire [32:0] _zz_356_; - wire [0:0] _zz_357_; - wire [32:0] _zz_358_; - wire [0:0] _zz_359_; - wire [32:0] _zz_360_; - wire [0:0] _zz_361_; - wire [31:0] _zz_362_; - wire [0:0] _zz_363_; - wire [0:0] _zz_364_; - wire [0:0] _zz_365_; - wire [0:0] _zz_366_; - wire [0:0] _zz_367_; - wire [0:0] _zz_368_; - wire [26:0] _zz_369_; - wire _zz_370_; - wire _zz_371_; - wire [2:0] _zz_372_; - wire _zz_373_; - wire _zz_374_; - wire _zz_375_; - wire [31:0] _zz_376_; - wire [31:0] _zz_377_; - wire [31:0] _zz_378_; - wire [0:0] _zz_379_; - wire [2:0] _zz_380_; - wire [0:0] _zz_381_; - wire [0:0] _zz_382_; - wire _zz_383_; - wire [0:0] _zz_384_; - wire [25:0] _zz_385_; - wire [31:0] _zz_386_; - wire [31:0] _zz_387_; - wire [31:0] _zz_388_; - wire _zz_389_; - wire _zz_390_; - wire [31:0] _zz_391_; - wire [0:0] _zz_392_; - wire [2:0] _zz_393_; - wire [0:0] _zz_394_; - wire [0:0] _zz_395_; - wire [0:0] _zz_396_; - wire [0:0] _zz_397_; - wire _zz_398_; - wire [0:0] _zz_399_; - wire [22:0] _zz_400_; - wire [31:0] _zz_401_; - wire [31:0] _zz_402_; - wire [31:0] _zz_403_; - wire [31:0] _zz_404_; - wire _zz_405_; - wire [0:0] _zz_406_; - wire [0:0] _zz_407_; - wire [31:0] _zz_408_; - wire [31:0] _zz_409_; - wire [31:0] _zz_410_; - wire [31:0] _zz_411_; - wire [31:0] _zz_412_; - wire [31:0] _zz_413_; - wire _zz_414_; - wire [0:0] _zz_415_; - wire [0:0] _zz_416_; - wire _zz_417_; - wire [0:0] _zz_418_; - wire [20:0] _zz_419_; - wire [31:0] _zz_420_; - wire [31:0] _zz_421_; - wire [31:0] _zz_422_; - wire [31:0] _zz_423_; - wire [31:0] _zz_424_; - wire [4:0] _zz_425_; - wire [4:0] _zz_426_; - wire _zz_427_; - wire [0:0] _zz_428_; - wire [17:0] _zz_429_; - wire [31:0] _zz_430_; - wire _zz_431_; - wire [0:0] _zz_432_; - wire [0:0] _zz_433_; - wire [31:0] _zz_434_; - wire [31:0] _zz_435_; - wire [31:0] _zz_436_; - wire [1:0] _zz_437_; - wire [1:0] _zz_438_; - wire _zz_439_; - wire [0:0] _zz_440_; - wire [13:0] _zz_441_; - wire [31:0] _zz_442_; - wire [31:0] _zz_443_; - wire [31:0] _zz_444_; - wire [31:0] _zz_445_; - wire _zz_446_; - wire [0:0] _zz_447_; - wire [0:0] _zz_448_; - wire [0:0] _zz_449_; - wire [0:0] _zz_450_; - wire _zz_451_; - wire [0:0] _zz_452_; - wire [10:0] _zz_453_; - wire [31:0] _zz_454_; - wire [31:0] _zz_455_; - wire [0:0] _zz_456_; - wire [3:0] _zz_457_; - wire [0:0] _zz_458_; - wire [0:0] _zz_459_; - wire [0:0] _zz_460_; - wire [0:0] _zz_461_; - wire _zz_462_; - wire [0:0] _zz_463_; - wire [7:0] _zz_464_; - wire [31:0] _zz_465_; - wire [31:0] _zz_466_; - wire [31:0] _zz_467_; - wire _zz_468_; - wire [0:0] _zz_469_; - wire [0:0] _zz_470_; - wire [31:0] _zz_471_; - wire [31:0] _zz_472_; - wire [31:0] _zz_473_; - wire [31:0] _zz_474_; - wire [31:0] _zz_475_; - wire [0:0] _zz_476_; - wire [1:0] _zz_477_; - wire [2:0] _zz_478_; - wire [2:0] _zz_479_; - wire _zz_480_; - wire [0:0] _zz_481_; - wire [4:0] _zz_482_; - wire [31:0] _zz_483_; - wire [31:0] _zz_484_; - wire [31:0] _zz_485_; - wire [31:0] _zz_486_; - wire [31:0] _zz_487_; - wire [31:0] _zz_488_; - wire [31:0] _zz_489_; - wire _zz_490_; - wire _zz_491_; - wire _zz_492_; - wire [0:0] _zz_493_; - wire [0:0] _zz_494_; - wire _zz_495_; - wire [1:0] _zz_496_; - wire [1:0] _zz_497_; - wire _zz_498_; - wire [0:0] _zz_499_; - wire [2:0] _zz_500_; - wire [31:0] _zz_501_; - wire [31:0] _zz_502_; - wire [31:0] _zz_503_; - wire [31:0] _zz_504_; - wire [31:0] _zz_505_; - wire [31:0] _zz_506_; - wire [31:0] _zz_507_; - wire [31:0] _zz_508_; - wire _zz_509_; - wire [0:0] _zz_510_; - wire [0:0] _zz_511_; - wire [1:0] _zz_512_; - wire [1:0] _zz_513_; - wire _zz_514_; - wire [0:0] _zz_515_; - wire [0:0] _zz_516_; - wire [31:0] _zz_517_; - wire [31:0] _zz_518_; - wire [31:0] _zz_519_; - wire [31:0] _zz_520_; - wire [31:0] _zz_521_; - wire _zz_522_; - wire _zz_523_; - wire [0:0] _zz_524_; - wire [1:0] _zz_525_; - wire _zz_526_; - wire [31:0] _zz_527_; - wire [31:0] _zz_528_; - wire [31:0] _zz_529_; - wire _zz_530_; - wire [0:0] _zz_531_; - wire [13:0] _zz_532_; - wire [31:0] _zz_533_; - wire [31:0] _zz_534_; - wire [31:0] _zz_535_; - wire _zz_536_; - wire [0:0] _zz_537_; - wire [7:0] _zz_538_; - wire [31:0] _zz_539_; - wire [31:0] _zz_540_; - wire [31:0] _zz_541_; - wire _zz_542_; - wire [0:0] _zz_543_; - wire [1:0] _zz_544_; - wire _zz_545_; - wire _zz_546_; - wire _zz_547_; - wire decode_SRC_LESS_UNSIGNED; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; - wire execute_BRANCH_DO; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire [31:0] execute_BRANCH_CALC; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire decode_CSR_READ_OPCODE; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_8_; - wire `AluCtrlEnum_defaultEncoding_type _zz_9_; - wire `AluCtrlEnum_defaultEncoding_type _zz_10_; - wire decode_CSR_WRITE_OPCODE; - wire [51:0] memory_MUL_LOW; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12_; - wire decode_IS_RS1_SIGNED; - wire decode_IS_DIV; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_13_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_14_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_15_; - wire decode_PREDICTION_HAD_BRANCHED2; - wire memory_IS_MUL; - wire execute_IS_MUL; - wire decode_IS_MUL; - wire [33:0] execute_MUL_HL; - wire [31:0] execute_SHIFT_RIGHT; - wire decode_IS_RS2_SIGNED; - wire decode_MEMORY_MANAGMENT; - wire [31:0] memory_PC; - wire decode_IS_CSR; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_16_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_17_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_18_; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire decode_SRC2_FORCE_ZERO; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_19_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_; - wire [33:0] execute_MUL_LH; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_24_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_26_; - wire [31:0] execute_MUL_LL; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire [51:0] _zz_27_; - wire [33:0] _zz_28_; - wire [33:0] _zz_29_; - wire [33:0] _zz_30_; - wire [31:0] _zz_31_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_32_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; - wire _zz_34_; - wire _zz_35_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_36_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_37_; - wire [31:0] execute_PC; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_38_; - wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_39_; - wire _zz_40_; - wire _zz_41_; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_42_; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_43_; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_44_; - wire [31:0] _zz_45_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_46_; - wire _zz_47_; - wire [31:0] _zz_48_; - wire [31:0] _zz_49_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_50_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_51_; - wire [31:0] _zz_52_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_53_; - wire [31:0] _zz_54_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_55_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_56_; - wire [31:0] _zz_57_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; - wire [31:0] _zz_59_; - wire _zz_60_; - reg _zz_61_; - wire [31:0] _zz_62_; - wire [31:0] _zz_63_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire `EnvCtrlEnum_defaultEncoding_type _zz_64_; - wire _zz_65_; - wire _zz_66_; - wire _zz_67_; - wire _zz_68_; - wire _zz_69_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_70_; - wire _zz_71_; - wire _zz_72_; - wire _zz_73_; - wire `AluCtrlEnum_defaultEncoding_type _zz_74_; - wire _zz_75_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_76_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_77_; - wire _zz_78_; - wire _zz_79_; - wire _zz_80_; - wire _zz_81_; - wire _zz_82_; - wire _zz_83_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_84_; - wire _zz_85_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_86_; - wire _zz_87_; - wire _zz_88_; - reg [31:0] _zz_89_; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_ENABLE; - wire [1:0] _zz_90_; - wire execute_MEMORY_MANAGMENT; - wire [31:0] execute_RS2; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_91_; - reg _zz_92_; - reg _zz_93_; - wire [31:0] _zz_94_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_95_; - wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_96_; - reg [31:0] _zz_97_; - wire [31:0] decode_PC; - wire [31:0] _zz_98_; - wire [31:0] _zz_99_; - wire [31:0] _zz_100_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - wire decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - wire execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - wire execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_predictionJumpInterface_valid; - (* syn_keep , keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; - reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; - wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire DBusCachedPlugin_mmuBus_rsp_allowRead; - wire DBusCachedPlugin_mmuBus_rsp_allowWrite; - wire DBusCachedPlugin_mmuBus_rsp_allowExecute; - wire DBusCachedPlugin_mmuBus_rsp_exception; - wire DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - wire CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - wire CsrPlugin_allowInterrupts; - wire CsrPlugin_allowException; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_101_; - wire [4:0] _zz_102_; - wire _zz_103_; - wire _zz_104_; - wire _zz_105_; - wire _zz_106_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_107_; - wire _zz_108_; - wire _zz_109_; - wire _zz_110_; - wire _zz_111_; - reg _zz_112_; - wire _zz_113_; - reg _zz_114_; - reg [31:0] _zz_115_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_decodeInput_valid; - wire IBusCachedPlugin_iBusRsp_decodeInput_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - reg IBusCachedPlugin_injector_decodeRemoved; - wire _zz_116_; - reg [18:0] _zz_117_; - wire _zz_118_; - reg [10:0] _zz_119_; - wire _zz_120_; - reg [18:0] _zz_121_; - reg _zz_122_; - wire _zz_123_; - reg [10:0] _zz_124_; - wire _zz_125_; - reg [18:0] _zz_126_; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_127_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; - wire dBus_cmd_payload_last; - wire dBus_rsp_valid; - wire [31:0] dBus_rsp_payload_data; - wire dBus_rsp_payload_error; - wire dataCache_1__io_mem_cmd_s2mPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; - reg _zz_128_; - reg _zz_129_; - reg [31:0] _zz_130_; - reg [31:0] _zz_131_; - reg [3:0] _zz_132_; - reg [2:0] _zz_133_; - reg _zz_134_; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg _zz_135_; - reg _zz_136_; - reg [31:0] _zz_137_; - reg [31:0] _zz_138_; - reg [3:0] _zz_139_; - reg [2:0] _zz_140_; - reg _zz_141_; - wire [31:0] _zz_142_; - reg [31:0] DBusCachedPlugin_rspCounter; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_143_; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_144_; - reg [31:0] _zz_145_; - wire _zz_146_; - reg [31:0] _zz_147_; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [31:0] _zz_148_; - wire _zz_149_; - wire _zz_150_; - wire _zz_151_; - wire _zz_152_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_153_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_154_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_155_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_156_; - wire `AluCtrlEnum_defaultEncoding_type _zz_157_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_158_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_159_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_160_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_161_; - reg [31:0] _zz_162_; - wire _zz_163_; - reg [19:0] _zz_164_; - wire _zz_165_; - reg [19:0] _zz_166_; - reg [31:0] _zz_167_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_168_; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_169_; - reg _zz_170_; - reg _zz_171_; - wire _zz_172_; - reg _zz_173_; - reg [4:0] _zz_174_; - reg [31:0] _zz_175_; - wire _zz_176_; - wire _zz_177_; - wire _zz_178_; - wire _zz_179_; - wire _zz_180_; - wire _zz_181_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_182_; - reg _zz_183_; - reg _zz_184_; - wire _zz_185_; - reg [19:0] _zz_186_; - wire _zz_187_; - reg [10:0] _zz_188_; - wire _zz_189_; - reg [18:0] _zz_190_; - reg _zz_191_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_192_; - reg [19:0] _zz_193_; - wire _zz_194_; - reg [10:0] _zz_195_; - wire _zz_196_; - reg [18:0] _zz_197_; - wire [31:0] execute_BranchPlugin_branchAdder; - wire [1:0] CsrPlugin_misa_base; - wire [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_198_; - wire _zz_199_; - wire _zz_200_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_201_; - wire _zz_202_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - wire [65:0] writeBack_MulPlugin_result; - reg [32:0] memory_DivPlugin_rs1; - reg [31:0] memory_DivPlugin_rs2; - reg [64:0] memory_DivPlugin_accumulator; - reg memory_DivPlugin_div_needRevert; - reg memory_DivPlugin_div_counter_willIncrement; - reg memory_DivPlugin_div_counter_willClear; - reg [5:0] memory_DivPlugin_div_counter_valueNext; - reg [5:0] memory_DivPlugin_div_counter_value; - wire memory_DivPlugin_div_counter_willOverflowIfInc; - wire memory_DivPlugin_div_counter_willOverflow; - reg memory_DivPlugin_div_done; - reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_203_; - wire [32:0] _zz_204_; - wire [32:0] _zz_205_; - wire [31:0] _zz_206_; - wire _zz_207_; - wire _zz_208_; - reg [32:0] _zz_209_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_210_; - wire [31:0] _zz_211_; - reg [31:0] execute_to_memory_MUL_LL; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg [33:0] execute_to_memory_MUL_LH; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg [33:0] execute_to_memory_MUL_HH; - reg [33:0] memory_to_writeBack_MUL_HH; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg decode_to_execute_IS_CSR; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg decode_to_execute_MEMORY_MANAGMENT; - reg decode_to_execute_IS_RS2_SIGNED; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg [31:0] decode_to_execute_RS2; - reg [33:0] execute_to_memory_MUL_HL; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg memory_to_writeBack_IS_MUL; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg decode_to_execute_IS_RS1_SIGNED; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg [51:0] memory_to_writeBack_MUL_LOW; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg decode_to_execute_CSR_READ_OPCODE; - reg [31:0] decode_to_execute_RS1; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg decode_to_execute_MEMORY_WR; - reg execute_to_memory_MEMORY_WR; - reg memory_to_writeBack_MEMORY_WR; - reg execute_to_memory_BRANCH_DO; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg [2:0] _zz_212_; - reg _zz_213_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_214_; - wire _zz_215_; - wire _zz_216_; - wire _zz_217_; - wire _zz_218_; - wire _zz_219_; - reg _zz_220_; - reg [31:0] dBusWishbone_DAT_MISO_regNext; - `ifndef SYNTHESIS - reg [39:0] _zz_1__string; - reg [39:0] _zz_2__string; - reg [39:0] _zz_3__string; - reg [39:0] _zz_4__string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5__string; - reg [39:0] _zz_6__string; - reg [39:0] _zz_7__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_8__string; - reg [63:0] _zz_9__string; - reg [63:0] _zz_10__string; - reg [31:0] _zz_11__string; - reg [31:0] _zz_12__string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_13__string; - reg [23:0] _zz_14__string; - reg [23:0] _zz_15__string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_16__string; - reg [95:0] _zz_17__string; - reg [95:0] _zz_18__string; - reg [71:0] _zz_19__string; - reg [71:0] _zz_20__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_21__string; - reg [71:0] _zz_22__string; - reg [71:0] _zz_23__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_24__string; - reg [39:0] _zz_25__string; - reg [39:0] _zz_26__string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_32__string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_33__string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_36__string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_39__string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_44__string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_46__string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_51__string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_53__string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_56__string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_58__string; - reg [39:0] _zz_64__string; - reg [39:0] _zz_70__string; - reg [63:0] _zz_74__string; - reg [23:0] _zz_76__string; - reg [31:0] _zz_77__string; - reg [95:0] _zz_84__string; - reg [71:0] _zz_86__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_95__string; - reg [71:0] _zz_153__string; - reg [95:0] _zz_154__string; - reg [31:0] _zz_155__string; - reg [23:0] _zz_156__string; - reg [63:0] _zz_157__string; - reg [39:0] _zz_158__string; - reg [39:0] _zz_159__string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; - `endif - - (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_243_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_244_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_245_ = 1'b1; - assign _zz_246_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_247_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_248_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_249_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_91_)); - assign _zz_250_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_92_)); - assign _zz_251_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_93_)); - assign _zz_252_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); - assign _zz_253_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_254_ = (! memory_DivPlugin_div_done); - assign _zz_255_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_256_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_257_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_258_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_259_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_260_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_261_ = (1'b0 || (! 1'b1)); - assign _zz_262_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_263_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_264_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_265_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_266_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_267_ = execute_INSTRUCTION[13 : 12]; - assign _zz_268_ = (! memory_arbitration_isStuck); - assign _zz_269_ = (iBus_cmd_valid || (_zz_212_ != (3'b000))); - assign _zz_270_ = (_zz_239_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); - assign _zz_271_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_272_ = ((_zz_198_ && 1'b1) && (! 1'b0)); - assign _zz_273_ = ((_zz_199_ && 1'b1) && (! 1'b0)); - assign _zz_274_ = ((_zz_200_ && 1'b1) && (! 1'b0)); - assign _zz_275_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_276_ = execute_INSTRUCTION[13]; - assign _zz_277_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_278_ = (_zz_101_ - (5'b00001)); - assign _zz_279_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_280_ = {29'd0, _zz_279_}; - assign _zz_281_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_282_ = {{_zz_117_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_283_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_284_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_285_ = {{_zz_119_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_286_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_287_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_288_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_289_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); - assign _zz_290_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); - assign _zz_291_ = _zz_148_[0 : 0]; - assign _zz_292_ = _zz_148_[3 : 3]; - assign _zz_293_ = _zz_148_[6 : 6]; - assign _zz_294_ = _zz_148_[8 : 8]; - assign _zz_295_ = _zz_148_[9 : 9]; - assign _zz_296_ = _zz_148_[10 : 10]; - assign _zz_297_ = _zz_148_[11 : 11]; - assign _zz_298_ = _zz_148_[12 : 12]; - assign _zz_299_ = _zz_148_[17 : 17]; - assign _zz_300_ = _zz_148_[20 : 20]; - assign _zz_301_ = _zz_148_[21 : 21]; - assign _zz_302_ = _zz_148_[22 : 22]; - assign _zz_303_ = _zz_148_[25 : 25]; - assign _zz_304_ = _zz_148_[26 : 26]; - assign _zz_305_ = _zz_148_[27 : 27]; - assign _zz_306_ = _zz_148_[28 : 28]; - assign _zz_307_ = _zz_148_[29 : 29]; - assign _zz_308_ = execute_SRC_LESS; - assign _zz_309_ = (3'b100); - assign _zz_310_ = execute_INSTRUCTION[19 : 15]; - assign _zz_311_ = execute_INSTRUCTION[31 : 20]; - assign _zz_312_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_313_ = ($signed(_zz_314_) + $signed(_zz_317_)); - assign _zz_314_ = ($signed(_zz_315_) + $signed(_zz_316_)); - assign _zz_315_ = execute_SRC1; - assign _zz_316_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_317_ = (execute_SRC_USE_SUB_LESS ? _zz_318_ : _zz_319_); - assign _zz_318_ = (32'b00000000000000000000000000000001); - assign _zz_319_ = (32'b00000000000000000000000000000000); - assign _zz_320_ = ($signed(_zz_322_) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_321_ = _zz_320_[31 : 0]; - assign _zz_322_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_323_ = execute_INSTRUCTION[31 : 20]; - assign _zz_324_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_325_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_326_ = {_zz_186_,execute_INSTRUCTION[31 : 20]}; - assign _zz_327_ = {{_zz_188_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_328_ = {{_zz_190_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_329_ = execute_INSTRUCTION[31 : 20]; - assign _zz_330_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_331_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_332_ = (3'b100); - assign _zz_333_ = (_zz_201_ & (~ _zz_334_)); - assign _zz_334_ = (_zz_201_ - (2'b01)); - assign _zz_335_ = ($signed(_zz_336_) + $signed(_zz_341_)); - assign _zz_336_ = ($signed(_zz_337_) + $signed(_zz_339_)); - assign _zz_337_ = (52'b0000000000000000000000000000000000000000000000000000); - assign _zz_338_ = {1'b0,memory_MUL_LL}; - assign _zz_339_ = {{19{_zz_338_[32]}}, _zz_338_}; - assign _zz_340_ = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_341_ = {{2{_zz_340_[49]}}, _zz_340_}; - assign _zz_342_ = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_343_ = {{2{_zz_342_[49]}}, _zz_342_}; - assign _zz_344_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_345_ = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_346_ = writeBack_MUL_LOW[31 : 0]; - assign _zz_347_ = writeBack_MulPlugin_result[63 : 32]; - assign _zz_348_ = memory_DivPlugin_div_counter_willIncrement; - assign _zz_349_ = {5'd0, _zz_348_}; - assign _zz_350_ = {1'd0, memory_DivPlugin_rs2}; - assign _zz_351_ = {_zz_203_,(! _zz_205_[32])}; - assign _zz_352_ = _zz_205_[31:0]; - assign _zz_353_ = _zz_204_[31:0]; - assign _zz_354_ = _zz_355_; - assign _zz_355_ = _zz_356_; - assign _zz_356_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_206_) : _zz_206_)} + _zz_358_); - assign _zz_357_ = memory_DivPlugin_div_needRevert; - assign _zz_358_ = {32'd0, _zz_357_}; - assign _zz_359_ = _zz_208_; - assign _zz_360_ = {32'd0, _zz_359_}; - assign _zz_361_ = _zz_207_; - assign _zz_362_ = {31'd0, _zz_361_}; - assign _zz_363_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_364_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_365_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_366_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_367_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_368_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_369_ = (iBus_cmd_payload_address >>> 5); - assign _zz_370_ = 1'b1; - assign _zz_371_ = 1'b1; - assign _zz_372_ = {_zz_104_,{_zz_106_,_zz_105_}}; - assign _zz_373_ = decode_INSTRUCTION[31]; - assign _zz_374_ = decode_INSTRUCTION[31]; - assign _zz_375_ = decode_INSTRUCTION[7]; - assign _zz_376_ = (32'b00010000000000000011000001010000); - assign _zz_377_ = (decode_INSTRUCTION & (32'b00010000010000000011000001010000)); - assign _zz_378_ = (32'b00010000000000000000000001010000); - assign _zz_379_ = ((decode_INSTRUCTION & _zz_386_) == (32'b00000000000000000000000000000000)); - assign _zz_380_ = {(_zz_387_ == _zz_388_),{_zz_389_,_zz_390_}}; - assign _zz_381_ = ((decode_INSTRUCTION & _zz_391_) == (32'b00000000000000000001000000001000)); - assign _zz_382_ = (1'b0); - assign _zz_383_ = ({_zz_151_,{_zz_392_,_zz_393_}} != (5'b00000)); - assign _zz_384_ = ({_zz_394_,_zz_395_} != (2'b00)); - assign _zz_385_ = {(_zz_396_ != _zz_397_),{_zz_398_,{_zz_399_,_zz_400_}}}; - assign _zz_386_ = (32'b00000000000000000000000001000100); - assign _zz_387_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); - assign _zz_388_ = (32'b00000000000000000000000000000000); - assign _zz_389_ = ((decode_INSTRUCTION & _zz_401_) == (32'b00000000000000000010000000000000)); - assign _zz_390_ = ((decode_INSTRUCTION & _zz_402_) == (32'b00000000000000000001000000000000)); - assign _zz_391_ = (32'b00000000000000000101000001001000); - assign _zz_392_ = (_zz_403_ == _zz_404_); - assign _zz_393_ = {_zz_405_,{_zz_406_,_zz_407_}}; - assign _zz_394_ = (_zz_408_ == _zz_409_); - assign _zz_395_ = (_zz_410_ == _zz_411_); - assign _zz_396_ = (_zz_412_ == _zz_413_); - assign _zz_397_ = (1'b0); - assign _zz_398_ = (_zz_414_ != (1'b0)); - assign _zz_399_ = (_zz_415_ != _zz_416_); - assign _zz_400_ = {_zz_417_,{_zz_418_,_zz_419_}}; - assign _zz_401_ = (32'b00000000000000000110000000000100); - assign _zz_402_ = (32'b00000000000000000101000000000100); - assign _zz_403_ = (decode_INSTRUCTION & (32'b00000000000000000010000000110000)); - assign _zz_404_ = (32'b00000000000000000010000000010000); - assign _zz_405_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000110000)) == (32'b00000000000000000000000000010000)); - assign _zz_406_ = ((decode_INSTRUCTION & _zz_420_) == (32'b00000000000000000010000000100000)); - assign _zz_407_ = ((decode_INSTRUCTION & _zz_421_) == (32'b00000000000000000000000000100000)); - assign _zz_408_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); - assign _zz_409_ = (32'b00000000000000000001000001010000); - assign _zz_410_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); - assign _zz_411_ = (32'b00000000000000000010000001010000); - assign _zz_412_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_413_ = (32'b00000000000000000000000000100000); - assign _zz_414_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_415_ = ((decode_INSTRUCTION & _zz_422_) == (32'b00000000000000000010000000000000)); - assign _zz_416_ = (1'b0); - assign _zz_417_ = ((_zz_423_ == _zz_424_) != (1'b0)); - assign _zz_418_ = (_zz_152_ != (1'b0)); - assign _zz_419_ = {(_zz_425_ != _zz_426_),{_zz_427_,{_zz_428_,_zz_429_}}}; - assign _zz_420_ = (32'b00000010000000000010000001100000); - assign _zz_421_ = (32'b00000010000000000011000000100000); - assign _zz_422_ = (32'b00000000000000000011000000000000); - assign _zz_423_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_424_ = (32'b00000000000000000000000000100100); - assign _zz_425_ = {((decode_INSTRUCTION & _zz_430_) == (32'b00000000000000000000000001000000)),{_zz_151_,{_zz_431_,{_zz_432_,_zz_433_}}}}; - assign _zz_426_ = (5'b00000); - assign _zz_427_ = (((decode_INSTRUCTION & _zz_434_) == (32'b00000000000000000100000000010000)) != (1'b0)); - assign _zz_428_ = ((_zz_435_ == _zz_436_) != (1'b0)); - assign _zz_429_ = {(_zz_152_ != (1'b0)),{(_zz_437_ != _zz_438_),{_zz_439_,{_zz_440_,_zz_441_}}}}; - assign _zz_430_ = (32'b00000000000000000000000001000000); - assign _zz_431_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000100000)) == (32'b00000000000000000100000000100000)); - assign _zz_432_ = ((decode_INSTRUCTION & _zz_442_) == (32'b00000000000000000000000000010000)); - assign _zz_433_ = ((decode_INSTRUCTION & _zz_443_) == (32'b00000000000000000000000000100000)); - assign _zz_434_ = (32'b00000000000000000100000000010100); - assign _zz_435_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); - assign _zz_436_ = (32'b00000000000000000010000000010000); - assign _zz_437_ = {_zz_151_,(_zz_444_ == _zz_445_)}; - assign _zz_438_ = (2'b00); - assign _zz_439_ = ({_zz_151_,_zz_446_} != (2'b00)); - assign _zz_440_ = ({_zz_447_,_zz_448_} != (2'b00)); - assign _zz_441_ = {(_zz_449_ != _zz_450_),{_zz_451_,{_zz_452_,_zz_453_}}}; - assign _zz_442_ = (32'b00000000000000000000000000110000); - assign _zz_443_ = (32'b00000010000000000000000000100000); - assign _zz_444_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); - assign _zz_445_ = (32'b00000000000000000000000000100000); - assign _zz_446_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); - assign _zz_447_ = _zz_150_; - assign _zz_448_ = ((decode_INSTRUCTION & _zz_454_) == (32'b00000000000000000000000000000100)); - assign _zz_449_ = ((decode_INSTRUCTION & _zz_455_) == (32'b00000000000000000000000001000000)); - assign _zz_450_ = (1'b0); - assign _zz_451_ = ({_zz_150_,{_zz_456_,_zz_457_}} != (6'b000000)); - assign _zz_452_ = ({_zz_458_,_zz_459_} != (2'b00)); - assign _zz_453_ = {(_zz_460_ != _zz_461_),{_zz_462_,{_zz_463_,_zz_464_}}}; - assign _zz_454_ = (32'b00000000000000000000000000011100); - assign _zz_455_ = (32'b00000000000000000000000001011000); - assign _zz_456_ = ((decode_INSTRUCTION & _zz_465_) == (32'b00000000000000000001000000010000)); - assign _zz_457_ = {(_zz_466_ == _zz_467_),{_zz_468_,{_zz_469_,_zz_470_}}}; - assign _zz_458_ = ((decode_INSTRUCTION & _zz_471_) == (32'b00000000000000000010000000000000)); - assign _zz_459_ = ((decode_INSTRUCTION & _zz_472_) == (32'b00000000000000000001000000000000)); - assign _zz_460_ = ((decode_INSTRUCTION & _zz_473_) == (32'b00000010000000000100000000100000)); - assign _zz_461_ = (1'b0); - assign _zz_462_ = ((_zz_474_ == _zz_475_) != (1'b0)); - assign _zz_463_ = ({_zz_476_,_zz_477_} != (3'b000)); - assign _zz_464_ = {(_zz_478_ != _zz_479_),{_zz_480_,{_zz_481_,_zz_482_}}}; - assign _zz_465_ = (32'b00000000000000000001000000010000); - assign _zz_466_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_467_ = (32'b00000000000000000010000000010000); - assign _zz_468_ = ((decode_INSTRUCTION & _zz_483_) == (32'b00000000000000000000000000010000)); - assign _zz_469_ = (_zz_484_ == _zz_485_); - assign _zz_470_ = (_zz_486_ == _zz_487_); - assign _zz_471_ = (32'b00000000000000000010000000010000); - assign _zz_472_ = (32'b00000000000000000101000000000000); - assign _zz_473_ = (32'b00000010000000000100000001100100); - assign _zz_474_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_475_ = (32'b00000000000000000000000000000000); - assign _zz_476_ = (_zz_488_ == _zz_489_); - assign _zz_477_ = {_zz_490_,_zz_491_}; - assign _zz_478_ = {_zz_492_,{_zz_493_,_zz_494_}}; - assign _zz_479_ = (3'b000); - assign _zz_480_ = (_zz_495_ != (1'b0)); - assign _zz_481_ = (_zz_496_ != _zz_497_); - assign _zz_482_ = {_zz_498_,{_zz_499_,_zz_500_}}; - assign _zz_483_ = (32'b00000000000000000000000001010000); - assign _zz_484_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); - assign _zz_485_ = (32'b00000000000000000000000000000100); - assign _zz_486_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); - assign _zz_487_ = (32'b00000000000000000000000000000000); - assign _zz_488_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_489_ = (32'b00000000000000000000000001000000); - assign _zz_490_ = ((decode_INSTRUCTION & _zz_501_) == (32'b00000000000000000010000000010000)); - assign _zz_491_ = ((decode_INSTRUCTION & _zz_502_) == (32'b01000000000000000000000000110000)); - assign _zz_492_ = ((decode_INSTRUCTION & _zz_503_) == (32'b00000000000000000000000001000000)); - assign _zz_493_ = (_zz_504_ == _zz_505_); - assign _zz_494_ = (_zz_506_ == _zz_507_); - assign _zz_495_ = ((decode_INSTRUCTION & _zz_508_) == (32'b00000000000000000100000000001000)); - assign _zz_496_ = {_zz_509_,_zz_149_}; - assign _zz_497_ = (2'b00); - assign _zz_498_ = ({_zz_510_,_zz_511_} != (2'b00)); - assign _zz_499_ = (_zz_512_ != _zz_513_); - assign _zz_500_ = {_zz_514_,{_zz_515_,_zz_516_}}; - assign _zz_501_ = (32'b00000000000000000010000000010100); - assign _zz_502_ = (32'b01000000000000000000000000110100); - assign _zz_503_ = (32'b00000000000000000000000001010000); - assign _zz_504_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000)); - assign _zz_505_ = (32'b00000000000000000000000000000000); - assign _zz_506_ = (decode_INSTRUCTION & (32'b00000000010000000011000001000000)); - assign _zz_507_ = (32'b00000000000000000000000001000000); - assign _zz_508_ = (32'b00000000000000000100000001001000); - assign _zz_509_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); - assign _zz_510_ = ((decode_INSTRUCTION & _zz_517_) == (32'b00000000000000000000000000000100)); - assign _zz_511_ = _zz_149_; - assign _zz_512_ = {(_zz_518_ == _zz_519_),(_zz_520_ == _zz_521_)}; - assign _zz_513_ = (2'b00); - assign _zz_514_ = ({_zz_522_,_zz_523_} != (2'b00)); - assign _zz_515_ = ({_zz_524_,_zz_525_} != (3'b000)); - assign _zz_516_ = (_zz_526_ != (1'b0)); - assign _zz_517_ = (32'b00000000000000000000000001000100); - assign _zz_518_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); - assign _zz_519_ = (32'b00000000000000000000000000100000); - assign _zz_520_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_521_ = (32'b00000000000000000000000000100000); - assign _zz_522_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000110100)) == (32'b00000000000000000101000000010000)); - assign _zz_523_ = ((decode_INSTRUCTION & (32'b00000010000000000111000001100100)) == (32'b00000000000000000101000000100000)); - assign _zz_524_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); - assign _zz_525_ = {((decode_INSTRUCTION & (32'b00000000000000000111000000110100)) == (32'b00000000000000000001000000010000)),((decode_INSTRUCTION & (32'b00000010000000000111000001010100)) == (32'b00000000000000000001000000010000))}; - assign _zz_526_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001110100)) == (32'b00000010000000000000000000110000)); - assign _zz_527_ = (32'b00000000000000000001000001111111); - assign _zz_528_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_529_ = (32'b00000000000000000010000001110011); - assign _zz_530_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_531_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_532_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_533_) == (32'b00000000000000000000000000000011)),{(_zz_534_ == _zz_535_),{_zz_536_,{_zz_537_,_zz_538_}}}}}}; - assign _zz_533_ = (32'b00000000000000000101000001011111); - assign _zz_534_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_535_ = (32'b00000000000000000000000001100011); - assign _zz_536_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_537_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_538_ = {((decode_INSTRUCTION & (32'b00000001111100000111000001111111)) == (32'b00000000000000000101000000001111)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_539_) == (32'b00000000000000000001000000010011)),{(_zz_540_ == _zz_541_),{_zz_542_,{_zz_543_,_zz_544_}}}}}}; - assign _zz_539_ = (32'b11111100000000000011000001111111); - assign _zz_540_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_541_ = (32'b00000000000000000101000000110011); - assign _zz_542_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_543_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_544_ = {((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)),((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011))}; - assign _zz_545_ = execute_INSTRUCTION[31]; - assign _zz_546_ = execute_INSTRUCTION[31]; - assign _zz_547_ = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_61_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase end - - always @ (posedge clk) begin - if(_zz_370_) begin - _zz_240_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end + always @(*) begin + case(_zz_30) + `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; + default : _zz_30_string = "????"; + endcase end - - always @ (posedge clk) begin - if(_zz_371_) begin - _zz_241_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_221_), - .io_cpu_prefetch_isValid(_zz_222_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_223_), - .io_cpu_fetch_isStuck(_zz_224_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_225_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_226_), - .io_cpu_decode_isStuck(_zz_227_), - .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), - .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), - .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), - .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), - .io_cpu_decode_isUser(_zz_228_), - .io_cpu_fill_valid(_zz_229_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); - DataCache dataCache_1_ ( - .io_cpu_execute_isValid(_zz_230_), - .io_cpu_execute_address(_zz_231_), - .io_cpu_execute_args_wr(execute_MEMORY_WR), - .io_cpu_execute_args_data(_zz_143_), - .io_cpu_execute_args_size(execute_DBusCachedPlugin_size), - .io_cpu_memory_isValid(_zz_232_), - .io_cpu_memory_isStuck(memory_arbitration_isStuck), - .io_cpu_memory_isRemoved(memory_arbitration_removeIt), - .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), - .io_cpu_memory_address(_zz_233_), - .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), - .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), - .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), - .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_234_), - .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), - .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), - .io_cpu_writeBack_isValid(_zz_235_), - .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), - .io_cpu_writeBack_isUser(_zz_236_), - .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), - .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), - .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), - .io_cpu_writeBack_address(_zz_237_), - .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), - .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), - .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), - .io_cpu_redo(dataCache_1__io_cpu_redo), - .io_cpu_flush_valid(_zz_238_), - .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), - .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), - .io_mem_cmd_ready(_zz_239_), - .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), - .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), - .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), - .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), - .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), - .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), - .io_mem_rsp_valid(dBus_rsp_valid), - .io_mem_rsp_payload_data(dBus_rsp_payload_data), - .io_mem_rsp_payload_error(dBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); always @(*) begin - case(_zz_372_) - 3'b000 : begin - _zz_242_ = DBusCachedPlugin_redoBranch_payload; - end - 3'b001 : begin - _zz_242_ = CsrPlugin_jumpInterface_payload; - end - 3'b010 : begin - _zz_242_ = BranchPlugin_jumpInterface_payload; - end - 3'b011 : begin - _zz_242_ = IBusCachedPlugin_redoBranch_payload; - end - default : begin - _zz_242_ = IBusCachedPlugin_predictionJumpInterface_payload; - end + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; endcase end - - `ifndef SYNTHESIS always @(*) begin - case(_zz_1_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL"; - default : _zz_1__string = "?????"; + case(_zz_33) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; + default : _zz_33_string = "?????????"; endcase end always @(*) begin - case(_zz_2_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL"; - default : _zz_2__string = "?????"; + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_3_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL"; - default : _zz_3__string = "?????"; + case(_zz_34) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; + default : _zz_34_string = "?????????"; endcase end always @(*) begin - case(_zz_4_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL"; - default : _zz_4__string = "?????"; + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; + case(_zz_36) + `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; + default : _zz_36_string = "???"; endcase end always @(*) begin - case(_zz_5_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL"; - default : _zz_5__string = "?????"; + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_6_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL"; - default : _zz_6__string = "?????"; + case(_zz_37) + `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; + default : _zz_37_string = "????????????"; endcase end always @(*) begin - case(_zz_7_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL"; - default : _zz_7__string = "?????"; + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(_zz_38) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; + default : _zz_38_string = "????????"; endcase end always @(*) begin - case(_zz_8_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_8__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_8__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_8__string = "BITWISE "; - default : _zz_8__string = "????????"; + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_9_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_9__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_9__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_9__string = "BITWISE "; - default : _zz_9__string = "????????"; + case(_zz_39) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; + default : _zz_39_string = "?????"; endcase end always @(*) begin - case(_zz_10_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10__string = "BITWISE "; - default : _zz_10__string = "????????"; + case(_zz_43) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_11_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR"; - default : _zz_11__string = "????"; + case(_zz_44) + `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; + default : _zz_44_string = "????"; endcase end always @(*) begin - case(_zz_12_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12__string = "JALR"; - default : _zz_12__string = "????"; + case(_zz_45) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; + default : _zz_45_string = "?????????"; endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(_zz_46) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; + default : _zz_46_string = "?????"; endcase end always @(*) begin - case(_zz_13_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_13__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_13__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_13__string = "PC "; - default : _zz_13__string = "???"; + case(_zz_47) + `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; + default : _zz_47_string = "???"; endcase end always @(*) begin - case(_zz_14_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_14__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_14__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_14__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_14__string = "PC "; - default : _zz_14__string = "???"; + case(_zz_48) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; + default : _zz_48_string = "????????"; endcase end always @(*) begin - case(_zz_15_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_15__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_15__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_15__string = "PC "; - default : _zz_15__string = "???"; + case(_zz_49) + `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; + default : _zz_49_string = "????????????"; endcase end always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_16_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_16__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_16__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_16__string = "URS1 "; - default : _zz_16__string = "????????????"; + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; endcase end always @(*) begin - case(_zz_17_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_17__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_17__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_17__string = "URS1 "; - default : _zz_17__string = "????????????"; + case(_zz_91) + `Src1CtrlEnum_defaultEncoding_RS : _zz_91_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_91_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_91_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_91_string = "URS1 "; + default : _zz_91_string = "????????????"; endcase end always @(*) begin - case(_zz_18_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_18__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_18__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_18__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_18__string = "URS1 "; - default : _zz_18__string = "????????????"; + case(_zz_92) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_92_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_92_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_92_string = "BITWISE "; + default : _zz_92_string = "????????"; endcase end always @(*) begin - case(_zz_19_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_19__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_19__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_19__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_19__string = "SRA_1 "; - default : _zz_19__string = "?????????"; + case(_zz_93) + `Src2CtrlEnum_defaultEncoding_RS : _zz_93_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_93_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_93_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_93_string = "PC "; + default : _zz_93_string = "???"; endcase end always @(*) begin - case(_zz_20_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 "; - default : _zz_20__string = "?????????"; + case(_zz_94) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_94_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_94_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_94_string = "AND_1"; + default : _zz_94_string = "?????"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(_zz_95) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_95_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_95_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_95_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_95_string = "SRA_1 "; + default : _zz_95_string = "?????????"; endcase end always @(*) begin - case(_zz_21_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 "; - default : _zz_21__string = "?????????"; + case(_zz_96) + `BranchCtrlEnum_defaultEncoding_INC : _zz_96_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_96_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_96_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_96_string = "JALR"; + default : _zz_96_string = "????"; endcase end always @(*) begin - case(_zz_22_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; - default : _zz_22__string = "?????????"; + case(_zz_97) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_97_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_97_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_97_string = "ECALL"; + default : _zz_97_string = "?????"; endcase end always @(*) begin - case(_zz_23_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 "; - default : _zz_23__string = "?????????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_24__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_24__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_24__string = "AND_1"; - default : _zz_24__string = "?????"; + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_25_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25__string = "AND_1"; - default : _zz_25__string = "?????"; + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_26_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_26__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_26__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_26__string = "AND_1"; - default : _zz_26__string = "?????"; + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_32_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_32__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_32__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32__string = "ECALL"; - default : _zz_32__string = "?????"; + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; - default : execute_ENV_CTRL_string = "?????"; + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_33_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33__string = "ECALL"; - default : _zz_33__string = "?????"; + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; - default : writeBack_ENV_CTRL_string = "?????"; + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end - always @(*) begin - case(_zz_36_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_36__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_36__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_36__string = "ECALL"; - default : _zz_36__string = "?????"; - endcase + `endif + + assign memory_MUL_LOW = ($signed(_zz_226) + $signed(_zz_234)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_236; + assign execute_REGFILE_WRITE_DATA = _zz_99; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_170[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_238[0]; + assign decode_IS_RS1_SIGNED = _zz_239[0]; + assign decode_IS_DIV = _zz_240[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_241[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_242[0]; + assign _zz_8 = _zz_9; + assign _zz_10 = _zz_11; + assign decode_SHIFT_CTRL = _zz_12; + assign _zz_13 = _zz_14; + assign decode_ALU_BITWISE_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_SRC_LESS_UNSIGNED = _zz_243[0]; + assign decode_MEMORY_MANAGMENT = _zz_244[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_245[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_246[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_247[0]; + assign decode_SRC2_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_ALU_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_SRC1_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_27; + assign execute_ENV_CTRL = _zz_28; + assign writeBack_ENV_CTRL = _zz_29; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_116; + assign execute_BRANCH_CTRL = _zz_30; + assign decode_RS2_USE = _zz_248[0]; + assign decode_RS1_USE = _zz_249[0]; + always @ (*) begin + _zz_31 = execute_REGFILE_WRITE_DATA; + if(_zz_191)begin + _zz_31 = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(_zz_192)begin + if(_zz_193)begin + if(_zz_109)begin + decode_RS2 = _zz_50; + end + end + end + if(_zz_194)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_111)begin + decode_RS2 = _zz_32; + end + end + end + if(_zz_195)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_113)begin + decode_RS2 = _zz_31; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(_zz_192)begin + if(_zz_193)begin + if(_zz_108)begin + decode_RS1 = _zz_50; + end + end + end + if(_zz_194)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_110)begin + decode_RS1 = _zz_32; + end + end + end + if(_zz_195)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_112)begin + decode_RS1 = _zz_31; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_32 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_32 = _zz_107; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_32 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(_zz_196)begin + _zz_32 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_33; + assign execute_SHIFT_CTRL = _zz_34; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_35 = execute_PC; + assign execute_SRC2_CTRL = _zz_36; + assign execute_SRC1_CTRL = _zz_37; + assign decode_SRC_USE_SUB_LESS = _zz_250[0]; + assign decode_SRC_ADD_ZERO = _zz_251[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_38; + assign execute_SRC2 = _zz_105; + assign execute_SRC1 = _zz_100; + assign execute_ALU_BITWISE_CTRL = _zz_39; + assign _zz_40 = writeBack_INSTRUCTION; + assign _zz_41 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_42 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_42 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_252[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_321) == 32'h00001073),{(_zz_322 == _zz_323),{_zz_324,{_zz_325,_zz_326}}}}}}} != 21'h0); + always @ (*) begin + _zz_50 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_50 = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_225) + 2'b00 : begin + _zz_50 = _zz_294; + end + default : begin + _zz_50 = _zz_295; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_253[0]; + assign decode_FLUSH_ALL = _zz_254[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_197)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end end - always @(*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_198)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end end - always @(*) begin - case(_zz_39_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_39__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_39__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_39__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_39__string = "JALR"; - default : _zz_39__string = "????"; - endcase + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_199)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end end - always @(*) begin - case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_200)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end end - always @(*) begin - case(_zz_44_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_44__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_44__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_44__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_44__string = "SRA_1 "; - default : _zz_44__string = "?????????"; - endcase + + assign decode_BRANCH_CTRL = _zz_51; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_52 = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_52 = BranchPlugin_jumpInterface_payload; + end end - always @(*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase + + always @ (*) begin + _zz_53 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; + end end - always @(*) begin - case(_zz_46_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46__string = "SRA_1 "; - default : _zz_46__string = "?????????"; - endcase + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end end - always @(*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; - default : execute_SRC2_CTRL_string = "???"; - endcase + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end end - always @(*) begin - case(_zz_51_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_51__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_51__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_51__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_51__string = "PC "; - default : _zz_51__string = "???"; - endcase + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_201)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end end - always @(*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; - default : execute_SRC1_CTRL_string = "????????????"; - endcase + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_201)begin + decode_arbitration_flushNext = 1'b1; + end end - always @(*) begin - case(_zz_53_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_53__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_53__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_53__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_53__string = "URS1 "; - default : _zz_53__string = "????????????"; - endcase + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((_zz_186 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_191)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end end - always @(*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end end - always @(*) begin - case(_zz_56_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; - default : _zz_56__string = "????????"; - endcase + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase + + assign execute_arbitration_flushIt = 1'b0; + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_flushNext = 1'b1; + end end - always @(*) begin - case(_zz_58_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; - default : _zz_58__string = "?????"; - endcase + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(_zz_196)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end end - always @(*) begin - case(_zz_64_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_64__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_64__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_64__string = "ECALL"; - default : _zz_64__string = "?????"; - endcase + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end end - always @(*) begin - case(_zz_70_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_70__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_70__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_70__string = "AND_1"; - default : _zz_70__string = "?????"; - endcase + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_flushNext = 1'b1; + end end - always @(*) begin - case(_zz_74_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_74__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_74__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_74__string = "BITWISE "; - default : _zz_74__string = "????????"; - endcase + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end end - always @(*) begin - case(_zz_76_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_76__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_76__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_76__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_76__string = "PC "; - default : _zz_76__string = "???"; - endcase + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end end - always @(*) begin - case(_zz_77_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_77__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_77__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_77__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_77__string = "JALR"; - default : _zz_77__string = "????"; - endcase + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end end - always @(*) begin - case(_zz_84_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_84__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_84__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_84__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_84__string = "URS1 "; - default : _zz_84__string = "????????????"; - endcase + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_202)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_203)begin + writeBack_arbitration_flushNext = 1'b1; + end end - always @(*) begin - case(_zz_86_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_86__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_86__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_86__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_86__string = "SRA_1 "; - default : _zz_86__string = "?????????"; - endcase + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_202)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_203)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end end - always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; - endcase + + assign CsrPlugin_inWfi = 1'b0; + assign CsrPlugin_thirdPartyWake = 1'b0; + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_202)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_203)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end end - always @(*) begin - case(_zz_95_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR"; - default : _zz_95__string = "????"; - endcase + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_202)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_203)begin + case(_zz_204) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end end - always @(*) begin - case(_zz_153_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_153__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_153__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_153__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_153__string = "SRA_1 "; - default : _zz_153__string = "?????????"; - endcase + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_54 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_55 = (_zz_54 & (~ _zz_255)); + assign _zz_56 = _zz_55[3]; + assign _zz_57 = (_zz_55[1] || _zz_56); + assign _zz_58 = (_zz_55[2] || _zz_56); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_190; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end end - always @(*) begin - case(_zz_154_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_154__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_154__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_154__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_154__string = "URS1 "; - default : _zz_154__string = "????????????"; - endcase + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end end - always @(*) begin - case(_zz_155_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_155__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_155__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_155__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_155__string = "JALR"; - default : _zz_155__string = "????"; - endcase + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_257); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @(*) begin - case(_zz_156_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_156__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_156__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_156__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_156__string = "PC "; - default : _zz_156__string = "???"; - endcase + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end end - always @(*) begin - case(_zz_157_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_157__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_157__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_157__string = "BITWISE "; - default : _zz_157__string = "????????"; - endcase + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end end - always @(*) begin - case(_zz_158_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_158__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_158__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_158__string = "AND_1"; - default : _zz_158__string = "?????"; - endcase + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end end - always @(*) begin - case(_zz_159_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_159__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_159__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_159__string = "ECALL"; - default : _zz_159__string = "?????"; - endcase + + assign _zz_59 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_59); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_59); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase + + assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end end - always @(*) begin - case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase + + assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_62; + assign _zz_62 = ((1'b0 && (! _zz_63)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_63 = _zz_64; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_63; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_65)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_65 = _zz_66; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_65; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_67; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end end - always @(*) begin - case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; - default : execute_to_memory_SHIFT_CTRL_string = "?????????"; - endcase + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign _zz_68 = _zz_258[11]; + always @ (*) begin + _zz_69[18] = _zz_68; + _zz_69[17] = _zz_68; + _zz_69[16] = _zz_68; + _zz_69[15] = _zz_68; + _zz_69[14] = _zz_68; + _zz_69[13] = _zz_68; + _zz_69[12] = _zz_68; + _zz_69[11] = _zz_68; + _zz_69[10] = _zz_68; + _zz_69[9] = _zz_68; + _zz_69[8] = _zz_68; + _zz_69[7] = _zz_68; + _zz_69[6] = _zz_68; + _zz_69[5] = _zz_68; + _zz_69[4] = _zz_68; + _zz_69[3] = _zz_68; + _zz_69[2] = _zz_68; + _zz_69[1] = _zz_68; + _zz_69[0] = _zz_68; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_259[31])); + if(_zz_74)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase + + assign _zz_70 = _zz_260[19]; + always @ (*) begin + _zz_71[10] = _zz_70; + _zz_71[9] = _zz_70; + _zz_71[8] = _zz_70; + _zz_71[7] = _zz_70; + _zz_71[6] = _zz_70; + _zz_71[5] = _zz_70; + _zz_71[4] = _zz_70; + _zz_71[3] = _zz_70; + _zz_71[2] = _zz_70; + _zz_71[1] = _zz_70; + _zz_71[0] = _zz_70; end - always @(*) begin - case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; - default : decode_to_execute_SRC2_CTRL_string = "???"; - endcase + + assign _zz_72 = _zz_261[11]; + always @ (*) begin + _zz_73[18] = _zz_72; + _zz_73[17] = _zz_72; + _zz_73[16] = _zz_72; + _zz_73[15] = _zz_72; + _zz_73[14] = _zz_72; + _zz_73[13] = _zz_72; + _zz_73[12] = _zz_72; + _zz_73[11] = _zz_72; + _zz_73[10] = _zz_72; + _zz_73[9] = _zz_72; + _zz_73[8] = _zz_72; + _zz_73[7] = _zz_72; + _zz_73[6] = _zz_72; + _zz_73[5] = _zz_72; + _zz_73[4] = _zz_72; + _zz_73[3] = _zz_72; + _zz_73[2] = _zz_72; + _zz_73[1] = _zz_72; + _zz_73[0] = _zz_72; end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_74 = _zz_262[1]; + end + default : begin + _zz_74 = _zz_263[1]; + end endcase end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_75 = _zz_264[19]; + always @ (*) begin + _zz_76[10] = _zz_75; + _zz_76[9] = _zz_75; + _zz_76[8] = _zz_75; + _zz_76[7] = _zz_75; + _zz_76[6] = _zz_75; + _zz_76[5] = _zz_75; + _zz_76[4] = _zz_75; + _zz_76[3] = _zz_75; + _zz_76[2] = _zz_75; + _zz_76[1] = _zz_75; + _zz_76[0] = _zz_75; + end + + assign _zz_77 = _zz_265[11]; + always @ (*) begin + _zz_78[18] = _zz_77; + _zz_78[17] = _zz_77; + _zz_78[16] = _zz_77; + _zz_78[15] = _zz_77; + _zz_78[14] = _zz_77; + _zz_78[13] = _zz_77; + _zz_78[12] = _zz_77; + _zz_78[11] = _zz_77; + _zz_78[10] = _zz_77; + _zz_78[9] = _zz_77; + _zz_78[8] = _zz_77; + _zz_78[7] = _zz_77; + _zz_78[6] = _zz_77; + _zz_78[5] = _zz_77; + _zz_78[4] = _zz_77; + _zz_78[3] = _zz_77; + _zz_78[2] = _zz_77; + _zz_78[1] = _zz_77; + _zz_78[0] = _zz_77; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_76,{{{_zz_339,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_78,{{{_zz_340,_zz_341},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end - always @(*) begin - case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; - default : decode_to_execute_ENV_CTRL_string = "?????"; - endcase + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_161 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_162 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_163 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_162; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_165 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_166 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_167 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_200)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_198)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end end - always @(*) begin - case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; - default : execute_to_memory_ENV_CTRL_string = "?????"; - endcase + + always @ (*) begin + _zz_168 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_198)begin + _zz_168 = 1'b1; + end end - always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; - default : memory_to_writeBack_ENV_CTRL_string = "?????"; - endcase + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_199)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_197)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end end - `endif - assign decode_SRC_LESS_UNSIGNED = _zz_79_; - assign _zz_1_ = _zz_2_; - assign _zz_3_ = _zz_4_; - assign decode_ENV_CTRL = _zz_5_; - assign _zz_6_ = _zz_7_; - assign execute_BRANCH_DO = _zz_38_; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_69_; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_73_; - assign execute_BRANCH_CALC = _zz_37_; - assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; - assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; - assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_98_; - assign execute_REGFILE_WRITE_DATA = _zz_57_; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_90_; - assign decode_CSR_READ_OPCODE = _zz_34_; - assign decode_ALU_CTRL = _zz_8_; - assign _zz_9_ = _zz_10_; - assign decode_CSR_WRITE_OPCODE = _zz_35_; - assign memory_MUL_LOW = _zz_27_; - assign _zz_11_ = _zz_12_; - assign decode_IS_RS1_SIGNED = _zz_75_; - assign decode_IS_DIV = _zz_80_; - assign decode_SRC2_CTRL = _zz_13_; - assign _zz_14_ = _zz_15_; - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_41_; - assign memory_IS_MUL = execute_to_memory_IS_MUL; - assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_87_; - assign execute_MUL_HL = _zz_29_; - assign execute_SHIFT_RIGHT = _zz_45_; - assign decode_IS_RS2_SIGNED = _zz_72_; - assign decode_MEMORY_MANAGMENT = _zz_83_; - assign memory_PC = execute_to_memory_PC; - assign decode_IS_CSR = _zz_68_; - assign decode_SRC1_CTRL = _zz_16_; - assign _zz_17_ = _zz_18_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_67_; - assign decode_SRC2_FORCE_ZERO = _zz_55_; - assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = _zz_28_; - assign _zz_19_ = _zz_20_; - assign decode_SHIFT_CTRL = _zz_21_; - assign _zz_22_ = _zz_23_; - assign execute_MUL_LH = _zz_30_; - assign decode_ALU_BITWISE_CTRL = _zz_24_; - assign _zz_25_ = _zz_26_; - assign execute_MUL_LL = _zz_31_; - assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_DIV = decode_to_execute_IS_DIV; - assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; - assign memory_IS_DIV = execute_to_memory_IS_DIV; - assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; - assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; - assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; - assign memory_MUL_HL = execute_to_memory_MUL_HL; - assign memory_MUL_LH = execute_to_memory_MUL_LH; - assign memory_MUL_LL = execute_to_memory_MUL_LL; - assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; - assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; - assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_32_; - assign execute_ENV_CTRL = _zz_33_; - assign writeBack_ENV_CTRL = _zz_36_; - assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; - assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; - assign execute_PC = decode_to_execute_PC; - assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; - assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_40_; - assign execute_BRANCH_CTRL = _zz_39_; - assign decode_RS2_USE = _zz_85_; - assign decode_RS1_USE = _zz_65_; always @ (*) begin - _zz_42_ = execute_REGFILE_WRITE_DATA; - if(_zz_243_)begin - _zz_42_ = execute_CsrPlugin_readData; + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_199)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_197)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_160 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_187 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_169 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_170 = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_81 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_81 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_81 = execute_RS2[31 : 0]; + end + endcase + end + + assign _zz_186 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_171 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_172 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_171; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_172; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @ (*) begin + _zz_173 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_173 = 1'b1; end end - assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; - assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; - assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; - assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + assign _zz_174 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_175 = (CsrPlugin_privilege == 2'b00); + assign _zz_176 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - decode_RS2 = _zz_62_; - if(_zz_173_)begin - if((_zz_174_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_175_; + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_205)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; end end - if(_zz_244_)begin - if(_zz_245_)begin - if(_zz_177_)begin - decode_RS2 = _zz_89_; - end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_205)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; end - end - if(_zz_246_)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_179_)begin - decode_RS2 = _zz_43_; - end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; end - end - if(_zz_247_)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_181_)begin - decode_RS2 = _zz_42_; - end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - decode_RS1 = _zz_63_; - if(_zz_173_)begin - if((_zz_174_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_175_; - end - end - if(_zz_244_)begin - if(_zz_245_)begin - if(_zz_176_)begin - decode_RS1 = _zz_89_; - end + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_205)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_266}; end - end - if(_zz_246_)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_178_)begin - decode_RS1 = _zz_43_; - end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - end - if(_zz_247_)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_180_)begin - decode_RS1 = _zz_42_; - end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_267}; end end end - assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_43_ = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin - case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_43_ = _zz_169_; - end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_43_ = memory_SHIFT_RIGHT; - end - default : begin - end - endcase - end - if(_zz_248_)begin - _zz_43_ = memory_DivPlugin_div_result; - end + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase end - assign memory_SHIFT_CTRL = _zz_44_; - assign execute_SHIFT_CTRL = _zz_46_; - assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; - assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; - assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_50_ = execute_PC; - assign execute_SRC2_CTRL = _zz_51_; - assign execute_SRC1_CTRL = _zz_53_; - assign decode_SRC_USE_SUB_LESS = _zz_82_; - assign decode_SRC_ADD_ZERO = _zz_71_; - assign execute_SRC_ADD_SUB = _zz_49_; - assign execute_SRC_LESS = _zz_47_; - assign execute_ALU_CTRL = _zz_56_; - assign execute_SRC2 = _zz_52_; - assign execute_SRC1 = _zz_54_; - assign execute_ALU_BITWISE_CTRL = _zz_58_; - assign _zz_59_ = writeBack_INSTRUCTION; - assign _zz_60_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_61_ = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_61_ = 1'b1; - end + assign _zz_82 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_83[31] = _zz_82; + _zz_83[30] = _zz_82; + _zz_83[29] = _zz_82; + _zz_83[28] = _zz_82; + _zz_83[27] = _zz_82; + _zz_83[26] = _zz_82; + _zz_83[25] = _zz_82; + _zz_83[24] = _zz_82; + _zz_83[23] = _zz_82; + _zz_83[22] = _zz_82; + _zz_83[21] = _zz_82; + _zz_83[20] = _zz_82; + _zz_83[19] = _zz_82; + _zz_83[18] = _zz_82; + _zz_83[17] = _zz_82; + _zz_83[16] = _zz_82; + _zz_83[15] = _zz_82; + _zz_83[14] = _zz_82; + _zz_83[13] = _zz_82; + _zz_83[12] = _zz_82; + _zz_83[11] = _zz_82; + _zz_83[10] = _zz_82; + _zz_83[9] = _zz_82; + _zz_83[8] = _zz_82; + _zz_83[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_84 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_85[31] = _zz_84; + _zz_85[30] = _zz_84; + _zz_85[29] = _zz_84; + _zz_85[28] = _zz_84; + _zz_85[27] = _zz_84; + _zz_85[26] = _zz_84; + _zz_85[25] = _zz_84; + _zz_85[24] = _zz_84; + _zz_85[23] = _zz_84; + _zz_85[22] = _zz_84; + _zz_85[21] = _zz_84; + _zz_85[20] = _zz_84; + _zz_85[19] = _zz_84; + _zz_85[18] = _zz_84; + _zz_85[17] = _zz_84; + _zz_85[16] = _zz_84; + _zz_85[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_223) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_83; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_85; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase end - assign decode_INSTRUCTION_ANTICIPATED = _zz_94_; + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_87 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_88 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_89 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_90 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_86 = {(_zz_90 != 1'b0),{(_zz_90 != 1'b0),{((_zz_342 == _zz_343) != 1'b0),{(_zz_344 != 1'b0),{(_zz_345 != _zz_346),{_zz_347,{_zz_348,_zz_349}}}}}}}; + assign _zz_91 = _zz_86[2 : 1]; + assign _zz_49 = _zz_91; + assign _zz_92 = _zz_86[7 : 6]; + assign _zz_48 = _zz_92; + assign _zz_93 = _zz_86[9 : 8]; + assign _zz_47 = _zz_93; + assign _zz_94 = _zz_86[19 : 18]; + assign _zz_46 = _zz_94; + assign _zz_95 = _zz_86[22 : 21]; + assign _zz_45 = _zz_95; + assign _zz_96 = _zz_86[24 : 23]; + assign _zz_44 = _zz_96; + assign _zz_97 = _zz_86[27 : 26]; + assign _zz_43 = _zz_97; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_188; + assign decode_RegFilePlugin_rs2Data = _zz_189; always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_78_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin - decode_REGFILE_WRITE_VALID = 1'b0; + lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); + if(_zz_98)begin + lastStageRegFileWrite_valid = 1'b1; end end - assign decode_LEGAL_INSTRUCTION = _zz_88_; - assign decode_INSTRUCTION_READY = 1'b1; always @ (*) begin - _zz_89_ = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_89_ = writeBack_DBusCachedPlugin_rspFormated; - end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_277_) - 2'b00 : begin - _zz_89_ = _zz_346_; - end - default : begin - _zz_89_ = _zz_347_; - end - endcase + lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; + if(_zz_98)begin + lastStageRegFileWrite_payload_address = 5'h0; end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; - assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; - assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; - assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; - assign execute_RS2 = decode_to_execute_RS2; - assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = _zz_48_; - assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_81_; - assign decode_FLUSH_ALL = _zz_66_; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_91_; - if(_zz_249_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + lastStageRegFileWrite_payload_data = _zz_50; + if(_zz_98)begin + lastStageRegFileWrite_payload_data = 32'h0; end end always @ (*) begin - _zz_91_ = _zz_92_; - if(_zz_250_)begin - _zz_91_ = 1'b1; - end + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase end always @ (*) begin - _zz_92_ = _zz_93_; - if(_zz_251_)begin - _zz_92_ = 1'b1; - end + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_99 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_99 = {31'd0, _zz_268}; + end + default : begin + _zz_99 = execute_SRC_ADD_SUB; + end + endcase end always @ (*) begin - _zz_93_ = 1'b0; - if(_zz_252_)begin - _zz_93_ = 1'b1; - end + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_100 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_100 = {29'd0, _zz_269}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_100 = {27'd0, _zz_270}; + end + endcase end - assign decode_BRANCH_CTRL = _zz_95_; - assign decode_INSTRUCTION = _zz_99_; - always @ (*) begin - _zz_96_ = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_96_ = BranchPlugin_jumpInterface_payload; - end + assign _zz_101 = _zz_271[11]; + always @ (*) begin + _zz_102[19] = _zz_101; + _zz_102[18] = _zz_101; + _zz_102[17] = _zz_101; + _zz_102[16] = _zz_101; + _zz_102[15] = _zz_101; + _zz_102[14] = _zz_101; + _zz_102[13] = _zz_101; + _zz_102[12] = _zz_101; + _zz_102[11] = _zz_101; + _zz_102[10] = _zz_101; + _zz_102[9] = _zz_101; + _zz_102[8] = _zz_101; + _zz_102[7] = _zz_101; + _zz_102[6] = _zz_101; + _zz_102[5] = _zz_101; + _zz_102[4] = _zz_101; + _zz_102[3] = _zz_101; + _zz_102[2] = _zz_101; + _zz_102[1] = _zz_101; + _zz_102[0] = _zz_101; + end + + assign _zz_103 = _zz_272[11]; + always @ (*) begin + _zz_104[19] = _zz_103; + _zz_104[18] = _zz_103; + _zz_104[17] = _zz_103; + _zz_104[16] = _zz_103; + _zz_104[15] = _zz_103; + _zz_104[14] = _zz_103; + _zz_104[13] = _zz_103; + _zz_104[12] = _zz_103; + _zz_104[11] = _zz_103; + _zz_104[10] = _zz_103; + _zz_104[9] = _zz_103; + _zz_104[8] = _zz_103; + _zz_104[7] = _zz_103; + _zz_104[6] = _zz_103; + _zz_104[5] = _zz_103; + _zz_104[4] = _zz_103; + _zz_104[3] = _zz_103; + _zz_104[2] = _zz_103; + _zz_104[1] = _zz_103; + _zz_104[0] = _zz_103; end always @ (*) begin - _zz_97_ = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_97_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_97_ = IBusCachedPlugin_redoBranch_payload; - end + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_105 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_105 = {_zz_104,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_105 = _zz_35; + end + endcase end - assign decode_PC = _zz_100_; - assign writeBack_PC = memory_to_writeBack_PC; - assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin - decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin - decode_arbitration_haltItself = 1'b1; + execute_SrcPlugin_addSub = _zz_273; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; end end + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_170_ || _zz_171_)))begin - decode_arbitration_haltByOther = 1'b1; + _zz_106[0] = execute_SRC1[31]; + _zz_106[1] = execute_SRC1[30]; + _zz_106[2] = execute_SRC1[29]; + _zz_106[3] = execute_SRC1[28]; + _zz_106[4] = execute_SRC1[27]; + _zz_106[5] = execute_SRC1[26]; + _zz_106[6] = execute_SRC1[25]; + _zz_106[7] = execute_SRC1[24]; + _zz_106[8] = execute_SRC1[23]; + _zz_106[9] = execute_SRC1[22]; + _zz_106[10] = execute_SRC1[21]; + _zz_106[11] = execute_SRC1[20]; + _zz_106[12] = execute_SRC1[19]; + _zz_106[13] = execute_SRC1[18]; + _zz_106[14] = execute_SRC1[17]; + _zz_106[15] = execute_SRC1[16]; + _zz_106[16] = execute_SRC1[15]; + _zz_106[17] = execute_SRC1[14]; + _zz_106[18] = execute_SRC1[13]; + _zz_106[19] = execute_SRC1[12]; + _zz_106[20] = execute_SRC1[11]; + _zz_106[21] = execute_SRC1[10]; + _zz_106[22] = execute_SRC1[9]; + _zz_106[23] = execute_SRC1[8]; + _zz_106[24] = execute_SRC1[7]; + _zz_106[25] = execute_SRC1[6]; + _zz_106[26] = execute_SRC1[5]; + _zz_106[27] = execute_SRC1[4]; + _zz_106[28] = execute_SRC1[3]; + _zz_106[29] = execute_SRC1[2]; + _zz_106[30] = execute_SRC1[1]; + _zz_106[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_106 : execute_SRC1); + always @ (*) begin + _zz_107[0] = memory_SHIFT_RIGHT[31]; + _zz_107[1] = memory_SHIFT_RIGHT[30]; + _zz_107[2] = memory_SHIFT_RIGHT[29]; + _zz_107[3] = memory_SHIFT_RIGHT[28]; + _zz_107[4] = memory_SHIFT_RIGHT[27]; + _zz_107[5] = memory_SHIFT_RIGHT[26]; + _zz_107[6] = memory_SHIFT_RIGHT[25]; + _zz_107[7] = memory_SHIFT_RIGHT[24]; + _zz_107[8] = memory_SHIFT_RIGHT[23]; + _zz_107[9] = memory_SHIFT_RIGHT[22]; + _zz_107[10] = memory_SHIFT_RIGHT[21]; + _zz_107[11] = memory_SHIFT_RIGHT[20]; + _zz_107[12] = memory_SHIFT_RIGHT[19]; + _zz_107[13] = memory_SHIFT_RIGHT[18]; + _zz_107[14] = memory_SHIFT_RIGHT[17]; + _zz_107[15] = memory_SHIFT_RIGHT[16]; + _zz_107[16] = memory_SHIFT_RIGHT[15]; + _zz_107[17] = memory_SHIFT_RIGHT[14]; + _zz_107[18] = memory_SHIFT_RIGHT[13]; + _zz_107[19] = memory_SHIFT_RIGHT[12]; + _zz_107[20] = memory_SHIFT_RIGHT[11]; + _zz_107[21] = memory_SHIFT_RIGHT[10]; + _zz_107[22] = memory_SHIFT_RIGHT[9]; + _zz_107[23] = memory_SHIFT_RIGHT[8]; + _zz_107[24] = memory_SHIFT_RIGHT[7]; + _zz_107[25] = memory_SHIFT_RIGHT[6]; + _zz_107[26] = memory_SHIFT_RIGHT[5]; + _zz_107[27] = memory_SHIFT_RIGHT[4]; + _zz_107[28] = memory_SHIFT_RIGHT[3]; + _zz_107[29] = memory_SHIFT_RIGHT[2]; + _zz_107[30] = memory_SHIFT_RIGHT[1]; + _zz_107[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_206)begin + if(_zz_207)begin + if(_zz_108)begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(_zz_208)begin + if(_zz_209)begin + if(_zz_110)begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin - decode_arbitration_haltByOther = 1'b1; + if(_zz_210)begin + if(_zz_211)begin + if(_zz_112)begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - decode_arbitration_removeIt = 1'b0; - if(_zz_253_)begin - decode_arbitration_removeIt = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_206)begin + if(_zz_207)begin + if(_zz_109)begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end end - if(decode_arbitration_isFlushed)begin - decode_arbitration_removeIt = 1'b1; + if(_zz_208)begin + if(_zz_209)begin + if(_zz_111)begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(_zz_210)begin + if(_zz_211)begin + if(_zz_113)begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign decode_arbitration_flushIt = 1'b0; + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_108 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_109 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_110 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_111 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_112 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_113 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_114 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_114 == 3'b000)) begin + _zz_115 = execute_BranchPlugin_eq; + end else if((_zz_114 == 3'b001)) begin + _zz_115 = (! execute_BranchPlugin_eq); + end else if((((_zz_114 & 3'b101) == 3'b101))) begin + _zz_115 = (! execute_SRC_LESS); + end else begin + _zz_115 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_116 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_116 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_116 = 1'b1; + end + default : begin + _zz_116 = _zz_115; + end + endcase + end + + assign _zz_117 = _zz_280[11]; + always @ (*) begin + _zz_118[19] = _zz_117; + _zz_118[18] = _zz_117; + _zz_118[17] = _zz_117; + _zz_118[16] = _zz_117; + _zz_118[15] = _zz_117; + _zz_118[14] = _zz_117; + _zz_118[13] = _zz_117; + _zz_118[12] = _zz_117; + _zz_118[11] = _zz_117; + _zz_118[10] = _zz_117; + _zz_118[9] = _zz_117; + _zz_118[8] = _zz_117; + _zz_118[7] = _zz_117; + _zz_118[6] = _zz_117; + _zz_118[5] = _zz_117; + _zz_118[4] = _zz_117; + _zz_118[3] = _zz_117; + _zz_118[2] = _zz_117; + _zz_118[1] = _zz_117; + _zz_118[0] = _zz_117; + end + + assign _zz_119 = _zz_281[19]; + always @ (*) begin + _zz_120[10] = _zz_119; + _zz_120[9] = _zz_119; + _zz_120[8] = _zz_119; + _zz_120[7] = _zz_119; + _zz_120[6] = _zz_119; + _zz_120[5] = _zz_119; + _zz_120[4] = _zz_119; + _zz_120[3] = _zz_119; + _zz_120[2] = _zz_119; + _zz_120[1] = _zz_119; + _zz_120[0] = _zz_119; + end + + assign _zz_121 = _zz_282[11]; + always @ (*) begin + _zz_122[18] = _zz_121; + _zz_122[17] = _zz_121; + _zz_122[16] = _zz_121; + _zz_122[15] = _zz_121; + _zz_122[14] = _zz_121; + _zz_122[13] = _zz_121; + _zz_122[12] = _zz_121; + _zz_122[11] = _zz_121; + _zz_122[10] = _zz_121; + _zz_122[9] = _zz_121; + _zz_122[8] = _zz_121; + _zz_122[7] = _zz_121; + _zz_122[6] = _zz_121; + _zz_122[5] = _zz_121; + _zz_122[4] = _zz_121; + _zz_122[3] = _zz_121; + _zz_122[2] = _zz_121; + _zz_122[1] = _zz_121; + _zz_122[0] = _zz_121; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_123 = (_zz_283[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_123 = _zz_284[1]; + end + default : begin + _zz_123 = _zz_285[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_123); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_124 = _zz_286[11]; + always @ (*) begin + _zz_125[19] = _zz_124; + _zz_125[18] = _zz_124; + _zz_125[17] = _zz_124; + _zz_125[16] = _zz_124; + _zz_125[15] = _zz_124; + _zz_125[14] = _zz_124; + _zz_125[13] = _zz_124; + _zz_125[12] = _zz_124; + _zz_125[11] = _zz_124; + _zz_125[10] = _zz_124; + _zz_125[9] = _zz_124; + _zz_125[8] = _zz_124; + _zz_125[7] = _zz_124; + _zz_125[6] = _zz_124; + _zz_125[5] = _zz_124; + _zz_125[4] = _zz_124; + _zz_125[3] = _zz_124; + _zz_125[2] = _zz_124; + _zz_125[1] = _zz_124; + _zz_125[0] = _zz_124; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_125,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_127,{{{_zz_500,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_129,{{{_zz_501,_zz_502},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_289}; + end + end + endcase + end + + assign _zz_126 = _zz_287[19]; + always @ (*) begin + _zz_127[10] = _zz_126; + _zz_127[9] = _zz_126; + _zz_127[8] = _zz_126; + _zz_127[7] = _zz_126; + _zz_127[6] = _zz_126; + _zz_127[5] = _zz_126; + _zz_127[4] = _zz_126; + _zz_127[3] = _zz_126; + _zz_127[2] = _zz_126; + _zz_127[1] = _zz_126; + _zz_127[0] = _zz_126; + end + + assign _zz_128 = _zz_288[11]; + always @ (*) begin + _zz_129[18] = _zz_128; + _zz_129[17] = _zz_128; + _zz_129[16] = _zz_128; + _zz_129[15] = _zz_128; + _zz_129[14] = _zz_128; + _zz_129[13] = _zz_128; + _zz_129[12] = _zz_128; + _zz_129[11] = _zz_128; + _zz_129[10] = _zz_128; + _zz_129[9] = _zz_128; + _zz_129[8] = _zz_128; + _zz_129[7] = _zz_128; + _zz_129[6] = _zz_128; + _zz_129[5] = _zz_128; + _zz_129[4] = _zz_128; + _zz_129[3] = _zz_128; + _zz_129[2] = _zz_128; + _zz_129[1] = _zz_128; + _zz_129[0] = _zz_128; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin - decode_arbitration_flushNext = 1'b1; - end - if(_zz_253_)begin - decode_arbitration_flushNext = 1'b1; + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; end end + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign _zz_130 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_131 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_132 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_133 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_134 = _zz_290[0]; always @ (*) begin - execute_arbitration_haltItself = 1'b0; - if((_zz_238_ && (! dataCache_1__io_cpu_flush_ready)))begin - execute_arbitration_haltItself = 1'b1; - end - if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin - execute_arbitration_haltItself = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_201)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(_zz_243_)begin - if(execute_CsrPlugin_blockedBySideEffects)begin - execute_arbitration_haltItself = 1'b1; - end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - assign execute_arbitration_haltByOther = 1'b0; always @ (*) begin - execute_arbitration_removeIt = 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; if(CsrPlugin_selfException_valid)begin - execute_arbitration_removeIt = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin - execute_arbitration_removeIt = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - assign execute_arbitration_flushIt = 1'b0; always @ (*) begin - execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin - execute_arbitration_flushNext = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end always @ (*) begin - memory_arbitration_haltItself = 1'b0; - if(_zz_248_)begin - if(_zz_254_)begin - memory_arbitration_haltItself = 1'b1; - end + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end - assign memory_arbitration_haltByOther = 1'b0; + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid)begin - memory_arbitration_removeIt = 1'b1; + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; end - if(memory_arbitration_isFlushed)begin - memory_arbitration_removeIt = 1'b1; + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; end end - assign memory_arbitration_flushIt = 1'b0; + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_branchExceptionPort_valid)begin - memory_arbitration_flushNext = 1'b1; + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end always @ (*) begin - writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1__io_cpu_writeBack_haltIt)begin - writeBack_arbitration_haltItself = 1'b1; + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - assign writeBack_arbitration_haltByOther = 1'b0; always @ (*) begin - writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin - writeBack_arbitration_removeIt = 1'b1; - end - if(writeBack_arbitration_isFlushed)begin - writeBack_arbitration_removeIt = 1'b1; - end + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase end always @ (*) begin - writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin - writeBack_arbitration_flushIt = 1'b1; - end + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase end + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin - writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin - writeBack_arbitration_flushNext = 1'b1; + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end end - if(DBusCachedPlugin_exceptionBus_valid)begin - writeBack_arbitration_flushNext = 1'b1; + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; end - if(_zz_255_)begin - writeBack_arbitration_flushNext = 1'b1; + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; end - if(_zz_256_)begin - writeBack_arbitration_flushNext = 1'b1; + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; end - end - - assign lastStageInstruction = writeBack_INSTRUCTION; - assign lastStagePc = writeBack_PC; - assign lastStageIsValid = writeBack_arbitration_isValid; - assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin - IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherHalt = 1'b1; + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end end - if(_zz_255_)begin - IBusCachedPlugin_fetcherHalt = 1'b1; + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; end - if(_zz_256_)begin - IBusCachedPlugin_fetcherHalt = 1'b1; + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end end - end - - always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end end - if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; + if(_zz_212)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; end end always @ (*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin - IBusCachedPlugin_incomingInstruction = 1'b1; + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end end end always @ (*) begin - CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_255_)begin - CsrPlugin_jumpInterface_valid = 1'b1; - end - if(_zz_256_)begin - CsrPlugin_jumpInterface_valid = 1'b1; + CsrPlugin_selfException_valid = 1'b0; + if(_zz_213)begin + CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_255_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; - end - if(_zz_256_)begin - case(_zz_257_) - 2'b11 : begin - CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_213)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; end default : begin + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end end - assign CsrPlugin_forceMachineWire = 1'b0; - assign CsrPlugin_allowInterrupts = 1'b1; - assign CsrPlugin_allowException = 1'b1; - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); - assign _zz_101_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_102_ = (_zz_101_ & (~ _zz_278_)); - assign _zz_103_ = _zz_102_[3]; - assign _zz_104_ = _zz_102_[4]; - assign _zz_105_ = (_zz_102_[1] || _zz_103_); - assign _zz_106_ = (_zz_102_[2] || _zz_103_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_242_; - always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; - if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_212)begin + execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin - IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin - IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_212)begin + execute_CsrPlugin_readInstruction = 1'b0; end end + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_280_); - if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; - end - IBusCachedPlugin_fetchPc_pc[0] = 1'b0; - IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + case(_zz_224) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase end - assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); - assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; - assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; - assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin - IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; - end + case(_zz_214) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase end - assign _zz_107_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_107_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_107_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin - IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; - end + case(_zz_214) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase end - assign _zz_108_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_108_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_108_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_292) + $signed(_zz_293)); + assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_196)begin + if(_zz_215)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end end end - assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_109_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_109_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_110_; - assign _zz_110_ = ((1'b0 && (! _zz_111_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_111_ = _zz_112_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_111_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_113_ = _zz_114_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_113_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_115_; always @ (*) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_216)begin + memory_DivPlugin_div_counter_willClear = 1'b1; end end - assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; - assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; - assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; - assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); - assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - assign _zz_100_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - assign _zz_99_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - assign _zz_98_ = (decode_PC + (32'b00000000000000000000000000000100)); - assign _zz_116_ = _zz_281_[11]; - always @ (*) begin - _zz_117_[18] = _zz_116_; - _zz_117_[17] = _zz_116_; - _zz_117_[16] = _zz_116_; - _zz_117_[15] = _zz_116_; - _zz_117_[14] = _zz_116_; - _zz_117_[13] = _zz_116_; - _zz_117_[12] = _zz_116_; - _zz_117_[11] = _zz_116_; - _zz_117_[10] = _zz_116_; - _zz_117_[9] = _zz_116_; - _zz_117_[8] = _zz_116_; - _zz_117_[7] = _zz_116_; - _zz_117_[6] = _zz_116_; - _zz_117_[5] = _zz_116_; - _zz_117_[4] = _zz_116_; - _zz_117_[3] = _zz_116_; - _zz_117_[2] = _zz_116_; - _zz_117_[1] = _zz_116_; - _zz_117_[0] = _zz_116_; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_282_[31])); - if(_zz_122_)begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_297); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_135 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_135[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_298); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_299 : _zz_300); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_301[31:0]; + assign _zz_136 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_137 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_138 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_139[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_139[31 : 0] = execute_RS1; + end + + assign _zz_141 = (_zz_140 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_141 != 32'h0); + assign _zz_26 = decode_SRC1_CTRL; + assign _zz_24 = _zz_49; + assign _zz_37 = decode_to_execute_SRC1_CTRL; + assign _zz_23 = decode_ALU_CTRL; + assign _zz_21 = _zz_48; + assign _zz_38 = decode_to_execute_ALU_CTRL; + assign _zz_20 = decode_SRC2_CTRL; + assign _zz_18 = _zz_47; + assign _zz_36 = decode_to_execute_SRC2_CTRL; + assign _zz_17 = decode_ALU_BITWISE_CTRL; + assign _zz_15 = _zz_46; + assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_14 = decode_SHIFT_CTRL; + assign _zz_11 = execute_SHIFT_CTRL; + assign _zz_12 = _zz_45; + assign _zz_34 = decode_to_execute_SHIFT_CTRL; + assign _zz_33 = execute_to_memory_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_51 = _zz_44; + assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_43; + assign _zz_28 = decode_to_execute_ENV_CTRL; + assign _zz_27 = execute_to_memory_ENV_CTRL; + assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_142 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_142[12 : 0] = 13'h1000; + _zz_142[25 : 20] = 6'h20; end end - assign _zz_118_ = _zz_283_[19]; always @ (*) begin - _zz_119_[10] = _zz_118_; - _zz_119_[9] = _zz_118_; - _zz_119_[8] = _zz_118_; - _zz_119_[7] = _zz_118_; - _zz_119_[6] = _zz_118_; - _zz_119_[5] = _zz_118_; - _zz_119_[4] = _zz_118_; - _zz_119_[3] = _zz_118_; - _zz_119_[2] = _zz_118_; - _zz_119_[1] = _zz_118_; - _zz_119_[0] = _zz_118_; + _zz_143 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_143[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_143[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_143[3 : 3] = CsrPlugin_mstatus_MIE; + end end - assign _zz_120_ = _zz_284_[11]; always @ (*) begin - _zz_121_[18] = _zz_120_; - _zz_121_[17] = _zz_120_; - _zz_121_[16] = _zz_120_; - _zz_121_[15] = _zz_120_; - _zz_121_[14] = _zz_120_; - _zz_121_[13] = _zz_120_; - _zz_121_[12] = _zz_120_; - _zz_121_[11] = _zz_120_; - _zz_121_[10] = _zz_120_; - _zz_121_[9] = _zz_120_; - _zz_121_[8] = _zz_120_; - _zz_121_[7] = _zz_120_; - _zz_121_[6] = _zz_120_; - _zz_121_[5] = _zz_120_; - _zz_121_[4] = _zz_120_; - _zz_121_[3] = _zz_120_; - _zz_121_[2] = _zz_120_; - _zz_121_[1] = _zz_120_; - _zz_121_[0] = _zz_120_; + _zz_144 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_144[11 : 11] = CsrPlugin_mip_MEIP; + _zz_144[7 : 7] = CsrPlugin_mip_MTIP; + _zz_144[3 : 3] = CsrPlugin_mip_MSIP; + end end always @ (*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_122_ = _zz_285_[1]; - end - default : begin - _zz_122_ = _zz_286_[1]; - end - endcase + _zz_145 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_145[11 : 11] = CsrPlugin_mie_MEIE; + _zz_145[7 : 7] = CsrPlugin_mie_MTIE; + _zz_145[3 : 3] = CsrPlugin_mie_MSIE; + end end - assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_123_ = _zz_287_[19]; - always @ (*) begin - _zz_124_[10] = _zz_123_; - _zz_124_[9] = _zz_123_; - _zz_124_[8] = _zz_123_; - _zz_124_[7] = _zz_123_; - _zz_124_[6] = _zz_123_; - _zz_124_[5] = _zz_123_; - _zz_124_[4] = _zz_123_; - _zz_124_[3] = _zz_123_; - _zz_124_[2] = _zz_123_; - _zz_124_[1] = _zz_123_; - _zz_124_[0] = _zz_123_; - end - - assign _zz_125_ = _zz_288_[11]; - always @ (*) begin - _zz_126_[18] = _zz_125_; - _zz_126_[17] = _zz_125_; - _zz_126_[16] = _zz_125_; - _zz_126_[15] = _zz_125_; - _zz_126_[14] = _zz_125_; - _zz_126_[13] = _zz_125_; - _zz_126_[12] = _zz_125_; - _zz_126_[11] = _zz_125_; - _zz_126_[10] = _zz_125_; - _zz_126_[9] = _zz_125_; - _zz_126_[8] = _zz_125_; - _zz_126_[7] = _zz_125_; - _zz_126_[6] = _zz_125_; - _zz_126_[5] = _zz_125_; - _zz_126_[4] = _zz_125_; - _zz_126_[3] = _zz_125_; - _zz_126_[2] = _zz_125_; - _zz_126_[1] = _zz_125_; - _zz_126_[0] = _zz_125_; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_124_,{{{_zz_373_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_126_,{{{_zz_374_,_zz_375_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); - assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin - iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; - iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + _zz_146 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_146[31 : 0] = CsrPlugin_mepc; + end end - assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; - assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_222_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_225_ = (32'b00000000000000000000000000000000); - assign _zz_223_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_224_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_226_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_227_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_228_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_94_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; always @ (*) begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_252_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b1; - end - if(_zz_250_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b1; - end - if(_zz_258_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; + _zz_147 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_147[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_147[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_229_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_250_)begin - _zz_229_ = 1'b1; - end - if(_zz_258_)begin - _zz_229_ = 1'b0; + _zz_148 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_148[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_251_)begin - IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; - end - if(_zz_249_)begin - IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + _zz_149 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_149[31 : 0] = _zz_140; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_251_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); - end - if(_zz_249_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_221_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_128_); - assign _zz_239_ = (! _zz_128_); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_128_ ? _zz_129_ : dataCache_1__io_mem_cmd_payload_wr); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_128_ ? _zz_130_ : dataCache_1__io_mem_cmd_payload_address); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_128_ ? _zz_131_ : dataCache_1__io_mem_cmd_payload_data); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_128_ ? _zz_132_ : dataCache_1__io_mem_cmd_payload_mask); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_128_ ? _zz_133_ : dataCache_1__io_mem_cmd_payload_length); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_128_ ? _zz_134_ : dataCache_1__io_mem_cmd_payload_last); - assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_135_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_136_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_137_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_138_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_139_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_140_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_141_; - assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; - assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_230_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_231_ = execute_SRC_ADD; - always @ (*) begin - case(execute_DBusCachedPlugin_size) - 2'b00 : begin - _zz_143_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; - end - 2'b01 : begin - _zz_143_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; - end - default : begin - _zz_143_ = execute_RS2[31 : 0]; - end - endcase + _zz_150 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_150[31 : 0] = _zz_141; + end end - assign _zz_238_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_90_ = _zz_231_[1 : 0]; - assign _zz_232_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_233_ = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + assign execute_CsrPlugin_readData = ((((_zz_142 | _zz_143) | (_zz_144 | _zz_145)) | ((_zz_146 | _zz_147) | (_zz_148 | _zz_149))) | _zz_150); + assign iBusWishbone_ADR = {_zz_317,_zz_151}; + assign iBusWishbone_CTI = ((_zz_151 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; always @ (*) begin - _zz_234_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin - _zz_234_ = 1'b1; + iBusWishbone_CYC = 1'b0; + if(_zz_217)begin + iBusWishbone_CYC = 1'b1; end end - assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; - assign _zz_235_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_236_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_237_ = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_259_)begin - if(dataCache_1__io_cpu_redo)begin - DBusCachedPlugin_redoBranch_valid = 1'b1; - end + iBusWishbone_STB = 1'b0; + if(_zz_217)begin + iBusWishbone_STB = 1'b1; end end - assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin - DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_259_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_152; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_158 = (dBus_cmd_payload_length != 3'b000); + assign _zz_154 = dBus_cmd_valid; + assign _zz_156 = dBus_cmd_payload_wr; + assign _zz_157 = (_zz_153 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_155 && (_zz_156 || _zz_157)); + assign dBusWishbone_ADR = ((_zz_158 ? {{dBus_cmd_payload_address[31 : 5],_zz_153},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_158 ? (_zz_157 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_156 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_156; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_155 = (_zz_154 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_154; + assign dBusWishbone_STB = _zz_154; + assign dBus_rsp_valid = _zz_159; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_64 <= 1'b0; + _zz_66 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_79; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_80; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_98 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_140 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_151 <= 3'b000; + _zz_152 <= 1'b0; + _zz_153 <= 3'b000; + _zz_159 <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end - if(dataCache_1__io_cpu_writeBack_mmuException)begin - DBusCachedPlugin_exceptionBus_valid = 1'b1; + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if(dataCache_1__io_cpu_redo)begin - DBusCachedPlugin_exceptionBus_valid = 1'b0; + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; end - end - end - - assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin - DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); - if(_zz_259_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_289_}; + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_290_}; + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(dataCache_1__io_cpu_writeBack_mmuException)begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_64 <= 1'b0; end - end - end - - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + if(_zz_62)begin + _zz_64 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_66 <= 1'b0; end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_66 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - default : begin + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - endcase - end - - assign _zz_144_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_145_[31] = _zz_144_; - _zz_145_[30] = _zz_144_; - _zz_145_[29] = _zz_144_; - _zz_145_[28] = _zz_144_; - _zz_145_[27] = _zz_144_; - _zz_145_[26] = _zz_144_; - _zz_145_[25] = _zz_144_; - _zz_145_[24] = _zz_144_; - _zz_145_[23] = _zz_144_; - _zz_145_[22] = _zz_144_; - _zz_145_[21] = _zz_144_; - _zz_145_[20] = _zz_144_; - _zz_145_[19] = _zz_144_; - _zz_145_[18] = _zz_144_; - _zz_145_[17] = _zz_144_; - _zz_145_[16] = _zz_144_; - _zz_145_[15] = _zz_144_; - _zz_145_[14] = _zz_144_; - _zz_145_[13] = _zz_144_; - _zz_145_[12] = _zz_144_; - _zz_145_[11] = _zz_144_; - _zz_145_[10] = _zz_144_; - _zz_145_[9] = _zz_144_; - _zz_145_[8] = _zz_144_; - _zz_145_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_146_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_147_[31] = _zz_146_; - _zz_147_[30] = _zz_146_; - _zz_147_[29] = _zz_146_; - _zz_147_[28] = _zz_146_; - _zz_147_[27] = _zz_146_; - _zz_147_[26] = _zz_146_; - _zz_147_[25] = _zz_146_; - _zz_147_[24] = _zz_146_; - _zz_147_[23] = _zz_146_; - _zz_147_[22] = _zz_146_; - _zz_147_[21] = _zz_146_; - _zz_147_[20] = _zz_146_; - _zz_147_[19] = _zz_146_; - _zz_147_[18] = _zz_146_; - _zz_147_[17] = _zz_146_; - _zz_147_[16] = _zz_146_; - _zz_147_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_275_) - 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_145_; + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_147_; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - endcase - end - - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; - assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; - assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; - assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; - assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; - assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_149_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_150_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_151_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_152_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); - assign _zz_148_ = {(((decode_INSTRUCTION & _zz_376_) == (32'b00000000000000000000000001010000)) != (1'b0)),{((_zz_377_ == _zz_378_) != (1'b0)),{({_zz_379_,_zz_380_} != (4'b0000)),{(_zz_381_ != _zz_382_),{_zz_383_,{_zz_384_,_zz_385_}}}}}}; - assign _zz_88_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_527_) == (32'b00000000000000000001000001110011)),{(_zz_528_ == _zz_529_),{_zz_530_,{_zz_531_,_zz_532_}}}}}}} != (21'b000000000000000000000)); - assign _zz_87_ = _zz_291_[0]; - assign _zz_153_ = _zz_148_[2 : 1]; - assign _zz_86_ = _zz_153_; - assign _zz_85_ = _zz_292_[0]; - assign _zz_154_ = _zz_148_[5 : 4]; - assign _zz_84_ = _zz_154_; - assign _zz_83_ = _zz_293_[0]; - assign _zz_82_ = _zz_294_[0]; - assign _zz_81_ = _zz_295_[0]; - assign _zz_80_ = _zz_296_[0]; - assign _zz_79_ = _zz_297_[0]; - assign _zz_78_ = _zz_298_[0]; - assign _zz_155_ = _zz_148_[14 : 13]; - assign _zz_77_ = _zz_155_; - assign _zz_156_ = _zz_148_[16 : 15]; - assign _zz_76_ = _zz_156_; - assign _zz_75_ = _zz_299_[0]; - assign _zz_157_ = _zz_148_[19 : 18]; - assign _zz_74_ = _zz_157_; - assign _zz_73_ = _zz_300_[0]; - assign _zz_72_ = _zz_301_[0]; - assign _zz_71_ = _zz_302_[0]; - assign _zz_158_ = _zz_148_[24 : 23]; - assign _zz_70_ = _zz_158_; - assign _zz_69_ = _zz_303_[0]; - assign _zz_68_ = _zz_304_[0]; - assign _zz_67_ = _zz_305_[0]; - assign _zz_66_ = _zz_306_[0]; - assign _zz_65_ = _zz_307_[0]; - assign _zz_159_ = _zz_148_[31 : 30]; - assign _zz_64_ = _zz_159_; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); - assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; - assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; - assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_240_; - assign decode_RegFilePlugin_rs2Data = _zz_241_; - assign _zz_63_ = decode_RegFilePlugin_rs1Data; - assign _zz_62_ = decode_RegFilePlugin_rs2Data; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_60_ && writeBack_arbitration_isFiring); - if(_zz_160_)begin - lastStageRegFileWrite_valid = 1'b1; - end - end - - assign lastStageRegFileWrite_payload_address = _zz_59_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_89_; - always @ (*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - default : begin - execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - endcase - end - - always @ (*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_161_ = execute_IntAluPlugin_bitwise; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_161_ = {31'd0, _zz_308_}; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - default : begin - _zz_161_ = execute_SRC_ADD_SUB; + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - endcase - end - - assign _zz_57_ = _zz_161_; - assign _zz_55_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - always @ (*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_162_ = execute_RS1; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(_zz_218)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_98 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_219)begin + if(_zz_220)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_221)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_222)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_202)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_203)begin + case(_zz_204) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_132,{_zz_131,_zz_130}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_162_ = {29'd0, _zz_309_}; + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_162_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; end - default : begin - _zz_162_ = {27'd0, _zz_310_}; + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; end - endcase - end - - assign _zz_54_ = _zz_162_; - assign _zz_163_ = _zz_311_[11]; - always @ (*) begin - _zz_164_[19] = _zz_163_; - _zz_164_[18] = _zz_163_; - _zz_164_[17] = _zz_163_; - _zz_164_[16] = _zz_163_; - _zz_164_[15] = _zz_163_; - _zz_164_[14] = _zz_163_; - _zz_164_[13] = _zz_163_; - _zz_164_[12] = _zz_163_; - _zz_164_[11] = _zz_163_; - _zz_164_[10] = _zz_163_; - _zz_164_[9] = _zz_163_; - _zz_164_[8] = _zz_163_; - _zz_164_[7] = _zz_163_; - _zz_164_[6] = _zz_163_; - _zz_164_[5] = _zz_163_; - _zz_164_[4] = _zz_163_; - _zz_164_[3] = _zz_163_; - _zz_164_[2] = _zz_163_; - _zz_164_[1] = _zz_163_; - _zz_164_[0] = _zz_163_; - end - - assign _zz_165_ = _zz_312_[11]; - always @ (*) begin - _zz_166_[19] = _zz_165_; - _zz_166_[18] = _zz_165_; - _zz_166_[17] = _zz_165_; - _zz_166_[16] = _zz_165_; - _zz_166_[15] = _zz_165_; - _zz_166_[14] = _zz_165_; - _zz_166_[13] = _zz_165_; - _zz_166_[12] = _zz_165_; - _zz_166_[11] = _zz_165_; - _zz_166_[10] = _zz_165_; - _zz_166_[9] = _zz_165_; - _zz_166_[8] = _zz_165_; - _zz_166_[7] = _zz_165_; - _zz_166_[6] = _zz_165_; - _zz_166_[5] = _zz_165_; - _zz_166_[4] = _zz_165_; - _zz_166_[3] = _zz_165_; - _zz_166_[2] = _zz_165_; - _zz_166_[1] = _zz_165_; - _zz_166_[0] = _zz_165_; - end - - always @ (*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_167_ = execute_RS2; + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_167_ = {_zz_164_,execute_INSTRUCTION[31 : 20]}; + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_167_ = {_zz_166_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_311[0]; + CsrPlugin_mstatus_MIE <= _zz_312[0]; + end end - default : begin - _zz_167_ = _zz_50_; + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_314[0]; + CsrPlugin_mie_MTIE <= _zz_315[0]; + CsrPlugin_mie_MSIE <= _zz_316[0]; + end end - endcase - end - - assign _zz_52_ = _zz_167_; - always @ (*) begin - execute_SrcPlugin_addSub = _zz_313_; - if(execute_SRC2_FORCE_ZERO)begin - execute_SrcPlugin_addSub = execute_SRC1; - end - end - - assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_49_ = execute_SrcPlugin_addSub; - assign _zz_48_ = execute_SrcPlugin_addSub; - assign _zz_47_ = execute_SrcPlugin_less; - assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_168_[0] = execute_SRC1[31]; - _zz_168_[1] = execute_SRC1[30]; - _zz_168_[2] = execute_SRC1[29]; - _zz_168_[3] = execute_SRC1[28]; - _zz_168_[4] = execute_SRC1[27]; - _zz_168_[5] = execute_SRC1[26]; - _zz_168_[6] = execute_SRC1[25]; - _zz_168_[7] = execute_SRC1[24]; - _zz_168_[8] = execute_SRC1[23]; - _zz_168_[9] = execute_SRC1[22]; - _zz_168_[10] = execute_SRC1[21]; - _zz_168_[11] = execute_SRC1[20]; - _zz_168_[12] = execute_SRC1[19]; - _zz_168_[13] = execute_SRC1[18]; - _zz_168_[14] = execute_SRC1[17]; - _zz_168_[15] = execute_SRC1[16]; - _zz_168_[16] = execute_SRC1[15]; - _zz_168_[17] = execute_SRC1[14]; - _zz_168_[18] = execute_SRC1[13]; - _zz_168_[19] = execute_SRC1[12]; - _zz_168_[20] = execute_SRC1[11]; - _zz_168_[21] = execute_SRC1[10]; - _zz_168_[22] = execute_SRC1[9]; - _zz_168_[23] = execute_SRC1[8]; - _zz_168_[24] = execute_SRC1[7]; - _zz_168_[25] = execute_SRC1[6]; - _zz_168_[26] = execute_SRC1[5]; - _zz_168_[27] = execute_SRC1[4]; - _zz_168_[28] = execute_SRC1[3]; - _zz_168_[29] = execute_SRC1[2]; - _zz_168_[30] = execute_SRC1[1]; - _zz_168_[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_168_ : execute_SRC1); - assign _zz_45_ = _zz_321_; - always @ (*) begin - _zz_169_[0] = memory_SHIFT_RIGHT[31]; - _zz_169_[1] = memory_SHIFT_RIGHT[30]; - _zz_169_[2] = memory_SHIFT_RIGHT[29]; - _zz_169_[3] = memory_SHIFT_RIGHT[28]; - _zz_169_[4] = memory_SHIFT_RIGHT[27]; - _zz_169_[5] = memory_SHIFT_RIGHT[26]; - _zz_169_[6] = memory_SHIFT_RIGHT[25]; - _zz_169_[7] = memory_SHIFT_RIGHT[24]; - _zz_169_[8] = memory_SHIFT_RIGHT[23]; - _zz_169_[9] = memory_SHIFT_RIGHT[22]; - _zz_169_[10] = memory_SHIFT_RIGHT[21]; - _zz_169_[11] = memory_SHIFT_RIGHT[20]; - _zz_169_[12] = memory_SHIFT_RIGHT[19]; - _zz_169_[13] = memory_SHIFT_RIGHT[18]; - _zz_169_[14] = memory_SHIFT_RIGHT[17]; - _zz_169_[15] = memory_SHIFT_RIGHT[16]; - _zz_169_[16] = memory_SHIFT_RIGHT[15]; - _zz_169_[17] = memory_SHIFT_RIGHT[14]; - _zz_169_[18] = memory_SHIFT_RIGHT[13]; - _zz_169_[19] = memory_SHIFT_RIGHT[12]; - _zz_169_[20] = memory_SHIFT_RIGHT[11]; - _zz_169_[21] = memory_SHIFT_RIGHT[10]; - _zz_169_[22] = memory_SHIFT_RIGHT[9]; - _zz_169_[23] = memory_SHIFT_RIGHT[8]; - _zz_169_[24] = memory_SHIFT_RIGHT[7]; - _zz_169_[25] = memory_SHIFT_RIGHT[6]; - _zz_169_[26] = memory_SHIFT_RIGHT[5]; - _zz_169_[27] = memory_SHIFT_RIGHT[4]; - _zz_169_[28] = memory_SHIFT_RIGHT[3]; - _zz_169_[29] = memory_SHIFT_RIGHT[2]; - _zz_169_[30] = memory_SHIFT_RIGHT[1]; - _zz_169_[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_170_ = 1'b0; - if(_zz_260_)begin - if(_zz_261_)begin - if(_zz_176_)begin - _zz_170_ = 1'b1; + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_140 <= execute_CsrPlugin_writeData[31 : 0]; end end - end - if(_zz_262_)begin - if(_zz_263_)begin - if(_zz_178_)begin - _zz_170_ = 1'b1; + if(_zz_217)begin + if(iBusWishbone_ACK)begin + _zz_151 <= (_zz_151 + 3'b001); end end - end - if(_zz_264_)begin - if(_zz_265_)begin - if(_zz_180_)begin - _zz_170_ = 1'b1; + _zz_152 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_154 && _zz_155))begin + _zz_153 <= (_zz_153 + 3'b001); + if(_zz_157)begin + _zz_153 <= 3'b000; end end - end - if((! decode_RS1_USE))begin - _zz_170_ = 1'b0; + _zz_159 <= ((_zz_154 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (*) begin - _zz_171_ = 1'b0; - if(_zz_260_)begin - if(_zz_261_)begin - if(_zz_177_)begin - _zz_171_ = 1'b1; - end - end + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_67 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(_zz_262_)begin - if(_zz_263_)begin - if(_zz_179_)begin - _zz_171_ = 1'b1; - end - end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(_zz_264_)begin - if(_zz_265_)begin - if(_zz_181_)begin - _zz_171_ = 1'b1; - end - end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if((! decode_RS2_USE))begin - _zz_171_ = 1'b0; + if(_zz_218)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - end - - assign _zz_172_ = (_zz_60_ && writeBack_arbitration_isFiring); - assign _zz_176_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_177_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_178_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_179_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_180_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_181_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_41_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; - assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_182_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_182_ == (3'b000))) begin - _zz_183_ = execute_BranchPlugin_eq; - end else if((_zz_182_ == (3'b001))) begin - _zz_183_ = (! execute_BranchPlugin_eq); - end else if((((_zz_182_ & (3'b101)) == (3'b101)))) begin - _zz_183_ = (! execute_SRC_LESS); - end else begin - _zz_183_ = execute_SRC_LESS; + if(_zz_201)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_134 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_134 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - end - - always @ (*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_184_ = 1'b0; - end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_184_ = 1'b1; - end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_184_ = 1'b1; - end - default : begin - _zz_184_ = _zz_183_; - end - endcase - end - - assign _zz_40_ = _zz_184_; - assign _zz_185_ = _zz_323_[11]; - always @ (*) begin - _zz_186_[19] = _zz_185_; - _zz_186_[18] = _zz_185_; - _zz_186_[17] = _zz_185_; - _zz_186_[16] = _zz_185_; - _zz_186_[15] = _zz_185_; - _zz_186_[14] = _zz_185_; - _zz_186_[13] = _zz_185_; - _zz_186_[12] = _zz_185_; - _zz_186_[11] = _zz_185_; - _zz_186_[10] = _zz_185_; - _zz_186_[9] = _zz_185_; - _zz_186_[8] = _zz_185_; - _zz_186_[7] = _zz_185_; - _zz_186_[6] = _zz_185_; - _zz_186_[5] = _zz_185_; - _zz_186_[4] = _zz_185_; - _zz_186_[3] = _zz_185_; - _zz_186_[2] = _zz_185_; - _zz_186_[1] = _zz_185_; - _zz_186_[0] = _zz_185_; - end - - assign _zz_187_ = _zz_324_[19]; - always @ (*) begin - _zz_188_[10] = _zz_187_; - _zz_188_[9] = _zz_187_; - _zz_188_[8] = _zz_187_; - _zz_188_[7] = _zz_187_; - _zz_188_[6] = _zz_187_; - _zz_188_[5] = _zz_187_; - _zz_188_[4] = _zz_187_; - _zz_188_[3] = _zz_187_; - _zz_188_[2] = _zz_187_; - _zz_188_[1] = _zz_187_; - _zz_188_[0] = _zz_187_; - end - - assign _zz_189_ = _zz_325_[11]; - always @ (*) begin - _zz_190_[18] = _zz_189_; - _zz_190_[17] = _zz_189_; - _zz_190_[16] = _zz_189_; - _zz_190_[15] = _zz_189_; - _zz_190_[14] = _zz_189_; - _zz_190_[13] = _zz_189_; - _zz_190_[12] = _zz_189_; - _zz_190_[11] = _zz_189_; - _zz_190_[10] = _zz_189_; - _zz_190_[9] = _zz_189_; - _zz_190_[8] = _zz_189_; - _zz_190_[7] = _zz_189_; - _zz_190_[6] = _zz_189_; - _zz_190_[5] = _zz_189_; - _zz_190_[4] = _zz_189_; - _zz_190_[3] = _zz_189_; - _zz_190_[2] = _zz_189_; - _zz_190_[1] = _zz_189_; - _zz_190_[0] = _zz_189_; - end - - always @ (*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_191_ = (_zz_326_[1] ^ execute_RS1[1]); - end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_191_ = _zz_327_[1]; - end - default : begin - _zz_191_ = _zz_328_[1]; - end - endcase - end - - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_191_); - assign _zz_38_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - always @ (*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src1 = execute_RS1; + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_219)begin + if(_zz_220)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - default : begin - execute_BranchPlugin_branch_src1 = execute_PC; + if(_zz_221)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - endcase - end - - assign _zz_192_ = _zz_329_[11]; - always @ (*) begin - _zz_193_[19] = _zz_192_; - _zz_193_[18] = _zz_192_; - _zz_193_[17] = _zz_192_; - _zz_193_[16] = _zz_192_; - _zz_193_[15] = _zz_192_; - _zz_193_[14] = _zz_192_; - _zz_193_[13] = _zz_192_; - _zz_193_[12] = _zz_192_; - _zz_193_[11] = _zz_192_; - _zz_193_[10] = _zz_192_; - _zz_193_[9] = _zz_192_; - _zz_193_[8] = _zz_192_; - _zz_193_[7] = _zz_192_; - _zz_193_[6] = _zz_192_; - _zz_193_[5] = _zz_192_; - _zz_193_[4] = _zz_192_; - _zz_193_[3] = _zz_192_; - _zz_193_[2] = _zz_192_; - _zz_193_[1] = _zz_192_; - _zz_193_[0] = _zz_192_; - end - - always @ (*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_193_,execute_INSTRUCTION[31 : 20]}; + if(_zz_222)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_195_,{{{_zz_545_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_197_,{{{_zz_546_,_zz_547_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_332_}; + end + if(_zz_202)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_196)begin + if(_zz_215)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_302[31:0]; end end - endcase - end - - assign _zz_194_ = _zz_330_[19]; - always @ (*) begin - _zz_195_[10] = _zz_194_; - _zz_195_[9] = _zz_194_; - _zz_195_[8] = _zz_194_; - _zz_195_[7] = _zz_194_; - _zz_195_[6] = _zz_194_; - _zz_195_[5] = _zz_194_; - _zz_195_[4] = _zz_194_; - _zz_195_[3] = _zz_194_; - _zz_195_[2] = _zz_194_; - _zz_195_[1] = _zz_194_; - _zz_195_[0] = _zz_194_; - end - - assign _zz_196_ = _zz_331_[11]; - always @ (*) begin - _zz_197_[18] = _zz_196_; - _zz_197_[17] = _zz_196_; - _zz_197_[16] = _zz_196_; - _zz_197_[15] = _zz_196_; - _zz_197_[14] = _zz_196_; - _zz_197_[13] = _zz_196_; - _zz_197_[12] = _zz_196_; - _zz_197_[11] = _zz_196_; - _zz_197_[10] = _zz_196_; - _zz_197_[9] = _zz_196_; - _zz_197_[8] = _zz_196_; - _zz_197_[7] = _zz_196_; - _zz_197_[6] = _zz_196_; - _zz_197_[5] = _zz_196_; - _zz_197_[4] = _zz_196_; - _zz_197_[3] = _zz_196_; - _zz_197_[2] = _zz_196_; - _zz_197_[1] = _zz_196_; - _zz_197_[0] = _zz_196_; - end - - assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_37_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; - assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); - assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; - assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); - assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; - assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin - CsrPlugin_privilege = (2'b11); - if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); end - end - - assign CsrPlugin_misa_base = (2'b01); - assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); - assign _zz_198_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_199_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_200_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_201_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_202_ = _zz_333_[0]; - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_253_)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + if(_zz_216)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_138 ? (~ _zz_139) : _zz_139) + _zz_308); + memory_DivPlugin_rs2 <= ((_zz_137 ? (~ execute_RS2) : execute_RS2) + _zz_310); + memory_DivPlugin_div_needRevert <= ((_zz_138 ^ (_zz_137 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_35; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if(decode_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; end - end - - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; end - if(execute_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - end - - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if(memory_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; end - end - - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; end - if(writeBack_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - end - - assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); - assign CsrPlugin_lastStageWasWfi = 1'b0; - always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin - CsrPlugin_pipelineLiberator_done = 1'b0; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if(CsrPlugin_hadException)begin - CsrPlugin_pipelineLiberator_done = 1'b0; + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - end - - assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin - CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin - CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - end - - always @ (*) begin - CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin - CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end - end - - always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; - end - default : begin - end - endcase - end - - always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; - end - default : begin - end - endcase - end - - assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_35_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_34_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - assign execute_CsrPlugin_inWfi = 1'b0; - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); - always @ (*) begin - execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001101000001 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000101 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000100 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b110011000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001101000010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin - execute_CsrPlugin_illegalAccess = 1'b1; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin - execute_CsrPlugin_illegalAccess = 1'b0; + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; end - end - - always @ (*) begin - execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin - execute_CsrPlugin_illegalInstruction = 1'b1; - end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; end - end - - always @ (*) begin - CsrPlugin_selfException_valid = 1'b0; - if(_zz_266_)begin - CsrPlugin_selfException_valid = 1'b1; + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - end - - always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_266_)begin - case(CsrPlugin_privilege) - 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); - end - default : begin - CsrPlugin_selfException_payload_code = (4'b1011); - end - endcase + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - end - - assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_210_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b110011000000 : begin - execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); - execute_CsrPlugin_readData[25 : 20] = (6'b100000); - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_211_; - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_313[0]; end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - default : begin + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end - endcase + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_276_) - 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; - end - default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); - end - endcase - end - assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_MulPlugin_a = execute_SRC1; - assign execute_MulPlugin_b = execute_SRC2; - always @ (*) begin - case(_zz_267_) - 2'b01 : begin - execute_MulPlugin_aSigned = 1'b1; - end - 2'b10 : begin - execute_MulPlugin_aSigned = 1'b1; - end - default : begin - execute_MulPlugin_aSigned = 1'b0; - end - endcase +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + end end always @ (*) begin - case(_zz_267_) - 2'b01 : begin - execute_MulPlugin_bSigned = 1'b1; - end - 2'b10 : begin - execute_MulPlugin_bSigned = 1'b0; - end - default : begin - execute_MulPlugin_bSigned = 1'b0; - end - endcase + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end end - assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; - assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; - assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; - assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; - assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; - assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign _zz_31_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign _zz_30_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - assign _zz_28_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - assign _zz_27_ = ($signed(_zz_335_) + $signed(_zz_343_)); - assign writeBack_MulPlugin_result = ($signed(_zz_344_) + $signed(_zz_345_)); always @ (*) begin - memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_248_)begin - if(_zz_254_)begin - memory_DivPlugin_div_counter_willIncrement = 1'b1; - end + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; end end always @ (*) begin - memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_268_)begin - memory_DivPlugin_div_counter_willClear = 1'b1; + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; end end - assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); - assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); - end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_349_); + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; end - if(memory_DivPlugin_div_counter_willClear)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); - end - end - - assign _zz_203_ = memory_DivPlugin_rs1[31 : 0]; - assign _zz_204_ = {memory_DivPlugin_accumulator[31 : 0],_zz_203_[31]}; - assign _zz_205_ = (_zz_204_ - _zz_350_); - assign _zz_206_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_207_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_208_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_209_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_209_[31 : 0] = execute_RS1; - end - - assign _zz_211_ = (_zz_210_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_211_ != (32'b00000000000000000000000000000000)); - assign _zz_26_ = decode_ALU_BITWISE_CTRL; - assign _zz_24_ = _zz_70_; - assign _zz_58_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_23_ = decode_SHIFT_CTRL; - assign _zz_20_ = execute_SHIFT_CTRL; - assign _zz_21_ = _zz_86_; - assign _zz_46_ = decode_to_execute_SHIFT_CTRL; - assign _zz_44_ = execute_to_memory_SHIFT_CTRL; - assign _zz_18_ = decode_SRC1_CTRL; - assign _zz_16_ = _zz_84_; - assign _zz_53_ = decode_to_execute_SRC1_CTRL; - assign _zz_15_ = decode_SRC2_CTRL; - assign _zz_13_ = _zz_76_; - assign _zz_51_ = decode_to_execute_SRC2_CTRL; - assign _zz_12_ = decode_BRANCH_CTRL; - assign _zz_95_ = _zz_77_; - assign _zz_39_ = decode_to_execute_BRANCH_CTRL; - assign _zz_10_ = decode_ALU_CTRL; - assign _zz_8_ = _zz_74_; - assign _zz_56_ = decode_to_execute_ALU_CTRL; - assign _zz_7_ = decode_ENV_CTRL; - assign _zz_4_ = execute_ENV_CTRL; - assign _zz_2_ = memory_ENV_CTRL; - assign _zz_5_ = _zz_64_; - assign _zz_33_ = decode_to_execute_ENV_CTRL; - assign _zz_32_ = execute_to_memory_ENV_CTRL; - assign _zz_36_ = memory_to_writeBack_ENV_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); - assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); - assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); - assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); - assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); - assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); - assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); - assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); - assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); - assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); - assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); - assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); - assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign iBusWishbone_ADR = {_zz_369_,_zz_212_}; - assign iBusWishbone_CTI = ((_zz_212_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); - assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + end + always @ (*) begin - iBusWishbone_CYC = 1'b0; - if(_zz_269_)begin - iBusWishbone_CYC = 1'b1; + tagsReadCmd_payload = 7'bxxxxxxx; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end always @ (*) begin - iBusWishbone_STB = 1'b0; - if(_zz_269_)begin - iBusWishbone_STB = 1'b1; + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; end end - assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_213_; - assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; - assign iBus_rsp_payload_error = 1'b0; - assign _zz_219_ = (dBus_cmd_payload_length != (3'b000)); - assign _zz_215_ = dBus_cmd_valid; - assign _zz_217_ = dBus_cmd_payload_wr; - assign _zz_218_ = (_zz_214_ == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_216_ && (_zz_217_ || _zz_218_)); - assign dBusWishbone_ADR = ((_zz_219_ ? {{dBus_cmd_payload_address[31 : 5],_zz_214_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); - assign dBusWishbone_CTI = (_zz_219_ ? (_zz_218_ ? (3'b111) : (3'b010)) : (3'b000)); - assign dBusWishbone_BTE = (2'b00); - assign dBusWishbone_SEL = (_zz_217_ ? dBus_cmd_payload_mask : (4'b1111)); - assign dBusWishbone_WE = _zz_217_; - assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_216_ = (_zz_215_ && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_215_; - assign dBusWishbone_STB = _zz_215_; - assign dBus_rsp_valid = _zz_220_; - assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; - assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin - if(reset) begin - IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; - IBusCachedPlugin_fetchPc_booted <= 1'b0; - IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_112_ <= 1'b0; - _zz_114_ <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_127_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_128_ <= 1'b0; - _zz_135_ <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_142_; - DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_160_ <= 1'b1; - _zz_173_ <= 1'b0; - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); - CsrPlugin_mie_MEIE <= 1'b0; - CsrPlugin_mie_MTIE <= 1'b0; - CsrPlugin_mie_MSIE <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - CsrPlugin_interrupt_valid <= 1'b0; - CsrPlugin_hadException <= 1'b0; - execute_CsrPlugin_wfiWake <= 1'b0; - memory_DivPlugin_div_counter_value <= (6'b000000); - _zz_210_ <= (32'b00000000000000000000000000000000); - execute_arbitration_isValid <= 1'b0; - memory_arbitration_isValid <= 1'b0; - writeBack_arbitration_isValid <= 1'b0; - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_212_ <= (3'b000); - _zz_213_ <= 1'b0; - _zz_214_ <= (3'b000); - _zz_220_ <= 1'b0; - end else begin - IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin - IBusCachedPlugin_fetchPc_inc <= 1'b0; - end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin - IBusCachedPlugin_fetchPc_inc <= 1'b1; - end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin - IBusCachedPlugin_fetchPc_inc <= 1'b0; - end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin - IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; - end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_112_ <= 1'b0; - end - if(_zz_110_)begin - _zz_112_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; - end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_114_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; - end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_114_ <= 1'b0; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if((! execute_arbitration_isStuck))begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if((! memory_arbitration_isStuck))begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if((! writeBack_arbitration_isStuck))begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end - if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_128_ <= 1'b0; - end - if(_zz_270_)begin - _zz_128_ <= dataCache_1__io_mem_cmd_valid; - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_135_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; - end - if(dBus_rsp_valid)begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); - end - _zz_160_ <= 1'b0; - _zz_173_ <= _zz_172_; - if((! decode_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - end - if((! execute_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - end - if((! memory_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - end - if((! writeBack_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; - end - CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_271_)begin - if(_zz_272_)begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(_zz_273_)begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(_zz_274_)begin - CsrPlugin_interrupt_valid <= 1'b1; - end - end - CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_255_)begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; - CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; - end - default : begin - end - endcase - end - if(_zz_256_)begin - case(_zz_257_) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); - CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; - CsrPlugin_mstatus_MPIE <= 1'b1; - end - default : begin - end - endcase - end - execute_CsrPlugin_wfiWake <= ({_zz_200_,{_zz_199_,_zz_198_}} != (3'b000)); - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_43_; - end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin - execute_arbitration_isValid <= 1'b0; - end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin - execute_arbitration_isValid <= decode_arbitration_isValid; - end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin - memory_arbitration_isValid <= 1'b0; - end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin - memory_arbitration_isValid <= execute_arbitration_isValid; - end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin - writeBack_arbitration_isValid <= 1'b0; - end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; - end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_210_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_363_[0]; - CsrPlugin_mstatus_MIE <= _zz_364_[0]; - end - end - 12'b001101000001 : begin - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - end - 12'b110011000000 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_366_[0]; - CsrPlugin_mie_MTIE <= _zz_367_[0]; - CsrPlugin_mie_MSIE <= _zz_368_[0]; - end - end - 12'b001101000010 : begin - end - default : begin - end - endcase - if(_zz_269_)begin - if(iBusWishbone_ACK)begin - _zz_212_ <= (_zz_212_ + (3'b001)); - end - end - _zz_213_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_215_ && _zz_216_))begin - _zz_214_ <= (_zz_214_ + (3'b001)); - if(_zz_218_)begin - _zz_214_ <= (3'b000); - end - end - _zz_220_ <= ((_zz_215_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); + always @ (*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_115_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; - end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin - IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; - end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin - IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; end - if(_zz_270_)begin - _zz_129_ <= dataCache_1__io_mem_cmd_payload_wr; - _zz_130_ <= dataCache_1__io_mem_cmd_payload_address; - _zz_131_ <= dataCache_1__io_mem_cmd_payload_data; - _zz_132_ <= dataCache_1__io_mem_cmd_payload_mask; - _zz_133_ <= dataCache_1__io_mem_cmd_payload_length; - _zz_134_ <= dataCache_1__io_mem_cmd_payload_last; - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_136_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - _zz_137_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; - _zz_138_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; - _zz_139_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - _zz_140_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; - _zz_141_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; - end - if(_zz_172_)begin - _zz_174_ <= _zz_59_[11 : 7]; - _zz_175_ <= _zz_89_; + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_253_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_202_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_202_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; end - if(BranchPlugin_branchExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if(DBusCachedPlugin_exceptionBus_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if(_zz_271_)begin - if(_zz_272_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - if(_zz_273_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - if(_zz_274_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; end - if(_zz_255_)begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - default : begin - end - endcase + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_done <= 1'b1; + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end - if(_zz_248_)begin - if(_zz_254_)begin - memory_DivPlugin_rs1[31 : 0] <= _zz_351_[31:0]; - memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_205_[32]) ? _zz_352_ : _zz_353_); - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_result <= _zz_354_[31:0]; - end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; end end - if(_zz_268_)begin - memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_DivPlugin_rs1 <= ((_zz_208_ ? (~ _zz_209_) : _zz_209_) + _zz_360_); - memory_DivPlugin_rs2 <= ((_zz_207_ ? (~ execute_RS2) : execute_RS2) + _zz_362_); - memory_DivPlugin_div_needRevert <= ((_zz_208_ ^ (_zz_207_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); - end - externalInterruptArray_regNext <= externalInterruptArray; - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LL <= execute_MUL_LL; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_25_; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LH <= execute_MUL_LH; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_22_; + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_19_; + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HH <= execute_MUL_HH; + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_17_; + if(_zz_13)begin + stageB_loaderValid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_50_; + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HL <= execute_MUL_HL; + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_MUL <= decode_IS_MUL; + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_14_; + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_11_; + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_9_; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_42_; + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_97_; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_96_; + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_9; + reg [21:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [21:0] _zz_15; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_11 = (! lineLoader_flushCounter[7]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6_; + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3_; + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1_; + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_365_[0]; - end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; end - 12'b110011000000 : begin + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end - 12'b001101000011 : begin + if(io_flush)begin + lineLoader_flushPending <= 1'b1; end - 12'b111111000000 : begin + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; end - 12'b001100000100 : begin + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; end - 12'b001101000010 : begin + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; end - default : begin + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end end - endcase - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end end -endmodule + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_12)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v index e1fbb61..54d517d 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v @@ -1,18 +1,18 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:06:28 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 `define ShiftCtrlEnum_defaultEncoding_type [1:0] `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 @@ -20,12 +20,6 @@ `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - `define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] `define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 @@ -37,3208 +31,2202 @@ `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 - -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input [2:0] _zz_10_, - input [31:0] _zz_11_, - input clk, - input reset); - reg [21:0] _zz_12_; - reg [31:0] _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire [0:0] _zz_16_; - wire [0:0] _zz_17_; - wire [21:0] _zz_18_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [6:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_7_; - wire [9:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - reg [31:0] io_cpu_fetch_data_regNextWhen; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_hit_valid; - reg decodeStage_hit_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; - assign _zz_14_ = (! lineLoader_flushCounter[7]); - assign _zz_15_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_16_ = _zz_7_[0 : 0]; - assign _zz_17_ = _zz_7_[1 : 1]; - assign _zz_18_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_18_; - end - end - - always @ (posedge clk) begin - if(_zz_6_) begin - _zz_12_ <= ways_0_tags[_zz_5_]; - end - end +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - always @ (posedge clk) begin - if(_zz_9_) begin - _zz_13_ <= ways_0_datas[_zz_8_]; - end - end - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; - end - end +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_163; + wire _zz_164; + wire _zz_165; + wire _zz_166; + wire _zz_167; + wire _zz_168; + wire _zz_169; + wire _zz_170; + reg _zz_171; + wire _zz_172; + wire [31:0] _zz_173; + wire _zz_174; + wire [31:0] _zz_175; + reg _zz_176; + wire _zz_177; + wire _zz_178; + wire [31:0] _zz_179; + wire _zz_180; + wire _zz_181; + wire _zz_182; + wire _zz_183; + wire _zz_184; + wire _zz_185; + wire _zz_186; + wire _zz_187; + wire [3:0] _zz_188; + wire _zz_189; + wire _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + wire _zz_201; + wire _zz_202; + wire _zz_203; + wire _zz_204; + wire _zz_205; + wire _zz_206; + wire _zz_207; + wire _zz_208; + wire _zz_209; + wire [1:0] _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + wire _zz_219; + wire [1:0] _zz_220; + wire _zz_221; + wire _zz_222; + wire [5:0] _zz_223; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire [1:0] _zz_230; + wire _zz_231; + wire [1:0] _zz_232; + wire [51:0] _zz_233; + wire [51:0] _zz_234; + wire [51:0] _zz_235; + wire [32:0] _zz_236; + wire [51:0] _zz_237; + wire [49:0] _zz_238; + wire [51:0] _zz_239; + wire [49:0] _zz_240; + wire [51:0] _zz_241; + wire [32:0] _zz_242; + wire [31:0] _zz_243; + wire [32:0] _zz_244; + wire [0:0] _zz_245; + wire [0:0] _zz_246; + wire [0:0] _zz_247; + wire [0:0] _zz_248; + wire [0:0] _zz_249; + wire [0:0] _zz_250; + wire [0:0] _zz_251; + wire [0:0] _zz_252; + wire [0:0] _zz_253; + wire [0:0] _zz_254; + wire [0:0] _zz_255; + wire [0:0] _zz_256; + wire [0:0] _zz_257; + wire [0:0] _zz_258; + wire [0:0] _zz_259; + wire [0:0] _zz_260; + wire [0:0] _zz_261; + wire [0:0] _zz_262; + wire [3:0] _zz_263; + wire [2:0] _zz_264; + wire [31:0] _zz_265; + wire [11:0] _zz_266; + wire [31:0] _zz_267; + wire [19:0] _zz_268; + wire [11:0] _zz_269; + wire [31:0] _zz_270; + wire [31:0] _zz_271; + wire [19:0] _zz_272; + wire [11:0] _zz_273; + wire [2:0] _zz_274; + wire [2:0] _zz_275; + wire [0:0] _zz_276; + wire [2:0] _zz_277; + wire [4:0] _zz_278; + wire [11:0] _zz_279; + wire [11:0] _zz_280; + wire [31:0] _zz_281; + wire [31:0] _zz_282; + wire [31:0] _zz_283; + wire [31:0] _zz_284; + wire [31:0] _zz_285; + wire [31:0] _zz_286; + wire [31:0] _zz_287; + wire [11:0] _zz_288; + wire [19:0] _zz_289; + wire [11:0] _zz_290; + wire [31:0] _zz_291; + wire [31:0] _zz_292; + wire [31:0] _zz_293; + wire [11:0] _zz_294; + wire [19:0] _zz_295; + wire [11:0] _zz_296; + wire [2:0] _zz_297; + wire [1:0] _zz_298; + wire [1:0] _zz_299; + wire [65:0] _zz_300; + wire [65:0] _zz_301; + wire [31:0] _zz_302; + wire [31:0] _zz_303; + wire [0:0] _zz_304; + wire [5:0] _zz_305; + wire [32:0] _zz_306; + wire [31:0] _zz_307; + wire [31:0] _zz_308; + wire [32:0] _zz_309; + wire [32:0] _zz_310; + wire [32:0] _zz_311; + wire [32:0] _zz_312; + wire [0:0] _zz_313; + wire [32:0] _zz_314; + wire [0:0] _zz_315; + wire [32:0] _zz_316; + wire [0:0] _zz_317; + wire [31:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire [0:0] _zz_321; + wire [0:0] _zz_322; + wire [0:0] _zz_323; + wire [0:0] _zz_324; + wire [26:0] _zz_325; + wire _zz_326; + wire _zz_327; + wire [1:0] _zz_328; + wire [31:0] _zz_329; + wire [31:0] _zz_330; + wire [31:0] _zz_331; + wire _zz_332; + wire [0:0] _zz_333; + wire [13:0] _zz_334; + wire [31:0] _zz_335; + wire [31:0] _zz_336; + wire [31:0] _zz_337; + wire _zz_338; + wire [0:0] _zz_339; + wire [7:0] _zz_340; + wire [31:0] _zz_341; + wire [31:0] _zz_342; + wire [31:0] _zz_343; + wire _zz_344; + wire [0:0] _zz_345; + wire [1:0] _zz_346; + wire _zz_347; + wire _zz_348; + wire _zz_349; + wire [31:0] _zz_350; + wire [0:0] _zz_351; + wire [0:0] _zz_352; + wire _zz_353; + wire [0:0] _zz_354; + wire [26:0] _zz_355; + wire [31:0] _zz_356; + wire [31:0] _zz_357; + wire [31:0] _zz_358; + wire _zz_359; + wire [1:0] _zz_360; + wire [1:0] _zz_361; + wire _zz_362; + wire [0:0] _zz_363; + wire [22:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire [31:0] _zz_367; + wire [31:0] _zz_368; + wire _zz_369; + wire _zz_370; + wire [1:0] _zz_371; + wire [1:0] _zz_372; + wire _zz_373; + wire [0:0] _zz_374; + wire [19:0] _zz_375; + wire [31:0] _zz_376; + wire [31:0] _zz_377; + wire [31:0] _zz_378; + wire [31:0] _zz_379; + wire _zz_380; + wire [0:0] _zz_381; + wire [0:0] _zz_382; + wire _zz_383; + wire [0:0] _zz_384; + wire [0:0] _zz_385; + wire _zz_386; + wire [0:0] _zz_387; + wire [16:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire [31:0] _zz_393; + wire [0:0] _zz_394; + wire [0:0] _zz_395; + wire [0:0] _zz_396; + wire [0:0] _zz_397; + wire _zz_398; + wire [0:0] _zz_399; + wire [13:0] _zz_400; + wire [31:0] _zz_401; + wire [31:0] _zz_402; + wire [31:0] _zz_403; + wire _zz_404; + wire _zz_405; + wire [0:0] _zz_406; + wire [1:0] _zz_407; + wire [0:0] _zz_408; + wire [0:0] _zz_409; + wire _zz_410; + wire [0:0] _zz_411; + wire [10:0] _zz_412; + wire [31:0] _zz_413; + wire [31:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire [31:0] _zz_418; + wire _zz_419; + wire [0:0] _zz_420; + wire [2:0] _zz_421; + wire [0:0] _zz_422; + wire [3:0] _zz_423; + wire [5:0] _zz_424; + wire [5:0] _zz_425; + wire _zz_426; + wire [0:0] _zz_427; + wire [7:0] _zz_428; + wire [31:0] _zz_429; + wire _zz_430; + wire [0:0] _zz_431; + wire [0:0] _zz_432; + wire _zz_433; + wire [0:0] _zz_434; + wire [1:0] _zz_435; + wire [0:0] _zz_436; + wire [3:0] _zz_437; + wire [0:0] _zz_438; + wire [0:0] _zz_439; + wire [1:0] _zz_440; + wire [1:0] _zz_441; + wire _zz_442; + wire [0:0] _zz_443; + wire [5:0] _zz_444; + wire [31:0] _zz_445; + wire [31:0] _zz_446; + wire [31:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire [31:0] _zz_450; + wire [31:0] _zz_451; + wire [31:0] _zz_452; + wire _zz_453; + wire _zz_454; + wire [31:0] _zz_455; + wire [31:0] _zz_456; + wire _zz_457; + wire [0:0] _zz_458; + wire [1:0] _zz_459; + wire [31:0] _zz_460; + wire [31:0] _zz_461; + wire _zz_462; + wire _zz_463; + wire [0:0] _zz_464; + wire [0:0] _zz_465; + wire _zz_466; + wire [0:0] _zz_467; + wire [3:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; + wire _zz_474; + wire _zz_475; + wire [31:0] _zz_476; + wire [31:0] _zz_477; + wire [31:0] _zz_478; + wire [31:0] _zz_479; + wire [0:0] _zz_480; + wire [2:0] _zz_481; + wire [0:0] _zz_482; + wire [0:0] _zz_483; + wire _zz_484; + wire [0:0] _zz_485; + wire [1:0] _zz_486; + wire [31:0] _zz_487; + wire [31:0] _zz_488; + wire [31:0] _zz_489; + wire _zz_490; + wire _zz_491; + wire [31:0] _zz_492; + wire _zz_493; + wire [0:0] _zz_494; + wire [0:0] _zz_495; + wire [0:0] _zz_496; + wire [0:0] _zz_497; + wire [1:0] _zz_498; + wire [1:0] _zz_499; + wire [0:0] _zz_500; + wire [0:0] _zz_501; + wire [31:0] _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire [31:0] _zz_505; + wire [31:0] _zz_506; + wire [31:0] _zz_507; + wire _zz_508; + wire _zz_509; + wire _zz_510; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_31; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_35; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_36; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; + wire [31:0] _zz_40; + wire _zz_41; + reg _zz_42; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_43; + wire `BranchCtrlEnum_defaultEncoding_type _zz_44; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; + wire `Src2CtrlEnum_defaultEncoding_type _zz_47; + wire `AluCtrlEnum_defaultEncoding_type _zz_48; + wire `Src1CtrlEnum_defaultEncoding_type _zz_49; + reg [31:0] _zz_50; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_52; + reg [31:0] _zz_53; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_54; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_55; + wire [3:0] _zz_56; + wire _zz_57; + wire _zz_58; + wire _zz_59; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_60; + wire _zz_61; + wire _zz_62; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_63; + wire _zz_64; + reg _zz_65; + wire _zz_66; + reg _zz_67; + reg [31:0] _zz_68; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_69; + reg [18:0] _zz_70; + wire _zz_71; + reg [10:0] _zz_72; + wire _zz_73; + reg [18:0] _zz_74; + reg _zz_75; + wire _zz_76; + reg [10:0] _zz_77; + wire _zz_78; + reg [18:0] _zz_79; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_80; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_81; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_82; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_83; + reg [31:0] _zz_84; + wire _zz_85; + reg [31:0] _zz_86; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [32:0] _zz_87; + wire _zz_88; + wire _zz_89; + wire _zz_90; + wire _zz_91; + wire `Src1CtrlEnum_defaultEncoding_type _zz_92; + wire `AluCtrlEnum_defaultEncoding_type _zz_93; + wire `Src2CtrlEnum_defaultEncoding_type _zz_94; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_95; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_96; + wire `BranchCtrlEnum_defaultEncoding_type _zz_97; + wire `EnvCtrlEnum_defaultEncoding_type _zz_98; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_99; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_100; + reg [31:0] _zz_101; + wire _zz_102; + reg [19:0] _zz_103; + wire _zz_104; + reg [19:0] _zz_105; + reg [31:0] _zz_106; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_107; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_108; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_109; + wire _zz_110; + wire _zz_111; + wire _zz_112; + wire _zz_113; + wire _zz_114; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_115; + reg _zz_116; + reg _zz_117; + wire _zz_118; + reg [19:0] _zz_119; + wire _zz_120; + reg [10:0] _zz_121; + wire _zz_122; + reg [18:0] _zz_123; + reg _zz_124; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_125; + reg [19:0] _zz_126; + wire _zz_127; + reg [10:0] _zz_128; + wire _zz_129; + reg [18:0] _zz_130; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_131; + wire _zz_132; + wire _zz_133; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_134; + wire _zz_135; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_136; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_137; + wire _zz_138; + wire _zz_139; + reg [32:0] _zz_140; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_141; + wire [31:0] _zz_142; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_143; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_144; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_145; + reg [31:0] _zz_146; + reg [31:0] _zz_147; + reg [31:0] _zz_148; + reg [31:0] _zz_149; + reg [31:0] _zz_150; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [2:0] _zz_154; + reg _zz_155; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_156; + wire _zz_157; + wire _zz_158; + wire _zz_159; + wire _zz_160; + wire _zz_161; + reg _zz_162; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [23:0] _zz_20_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [63:0] _zz_23_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; + reg [95:0] _zz_26_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_27_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_29_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_30_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_33_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_34_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_36_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_37_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_39_string; + reg [39:0] _zz_43_string; + reg [31:0] _zz_44_string; + reg [71:0] _zz_45_string; + reg [39:0] _zz_46_string; + reg [23:0] _zz_47_string; + reg [63:0] _zz_48_string; + reg [95:0] _zz_49_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_51_string; + reg [95:0] _zz_92_string; + reg [63:0] _zz_93_string; + reg [23:0] _zz_94_string; + reg [39:0] _zz_95_string; + reg [71:0] _zz_96_string; + reg [31:0] _zz_97_string; + reg [39:0] _zz_98_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; - end - end + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; - end + assign _zz_194 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_195 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_196 = 1'b1; + assign _zz_197 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_198 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_199 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_200 = ((_zz_168 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_201 = ((_zz_168 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_202 = ((_zz_168 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_203 = ((_zz_168 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_204 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_205 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_206 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_207 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_208 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_209 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_210 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_211 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_212 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_213 = (1'b0 || (! 1'b1)); + assign _zz_214 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_215 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_216 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_217 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_218 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_219 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_220 = execute_INSTRUCTION[13 : 12]; + assign _zz_221 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_222 = (! memory_arbitration_isStuck); + assign _zz_223 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_224 = (iBus_cmd_valid || (_zz_154 != 3'b000)); + assign _zz_225 = (_zz_190 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_226 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_227 = ((_zz_131 && 1'b1) && (! 1'b0)); + assign _zz_228 = ((_zz_132 && 1'b1) && (! 1'b0)); + assign _zz_229 = ((_zz_133 && 1'b1) && (! 1'b0)); + assign _zz_230 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_231 = execute_INSTRUCTION[13]; + assign _zz_232 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_233 = ($signed(_zz_234) + $signed(_zz_239)); + assign _zz_234 = ($signed(_zz_235) + $signed(_zz_237)); + assign _zz_235 = 52'h0; + assign _zz_236 = {1'b0,memory_MUL_LL}; + assign _zz_237 = {{19{_zz_236[32]}}, _zz_236}; + assign _zz_238 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_239 = {{2{_zz_238[49]}}, _zz_238}; + assign _zz_240 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_241 = {{2{_zz_240[49]}}, _zz_240}; + assign _zz_242 = ($signed(_zz_244) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_243 = _zz_242[31 : 0]; + assign _zz_244 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_245 = _zz_87[31 : 31]; + assign _zz_246 = _zz_87[30 : 30]; + assign _zz_247 = _zz_87[29 : 29]; + assign _zz_248 = _zz_87[28 : 28]; + assign _zz_249 = _zz_87[25 : 25]; + assign _zz_250 = _zz_87[17 : 17]; + assign _zz_251 = _zz_87[16 : 16]; + assign _zz_252 = _zz_87[13 : 13]; + assign _zz_253 = _zz_87[12 : 12]; + assign _zz_254 = _zz_87[11 : 11]; + assign _zz_255 = _zz_87[32 : 32]; + assign _zz_256 = _zz_87[15 : 15]; + assign _zz_257 = _zz_87[5 : 5]; + assign _zz_258 = _zz_87[3 : 3]; + assign _zz_259 = _zz_87[20 : 20]; + assign _zz_260 = _zz_87[10 : 10]; + assign _zz_261 = _zz_87[4 : 4]; + assign _zz_262 = _zz_87[0 : 0]; + assign _zz_263 = (_zz_55 - 4'b0001); + assign _zz_264 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_265 = {29'd0, _zz_264}; + assign _zz_266 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_267 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_268 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_269 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_270 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_271 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_272 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_273 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_274 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_275 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_276 = execute_SRC_LESS; + assign _zz_277 = 3'b100; + assign _zz_278 = execute_INSTRUCTION[19 : 15]; + assign _zz_279 = execute_INSTRUCTION[31 : 20]; + assign _zz_280 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_281 = ($signed(_zz_282) + $signed(_zz_285)); + assign _zz_282 = ($signed(_zz_283) + $signed(_zz_284)); + assign _zz_283 = execute_SRC1; + assign _zz_284 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_285 = (execute_SRC_USE_SUB_LESS ? _zz_286 : _zz_287); + assign _zz_286 = 32'h00000001; + assign _zz_287 = 32'h0; + assign _zz_288 = execute_INSTRUCTION[31 : 20]; + assign _zz_289 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_290 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_291 = {_zz_119,execute_INSTRUCTION[31 : 20]}; + assign _zz_292 = {{_zz_121,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_293 = {{_zz_123,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_294 = execute_INSTRUCTION[31 : 20]; + assign _zz_295 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_296 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_297 = 3'b100; + assign _zz_298 = (_zz_134 & (~ _zz_299)); + assign _zz_299 = (_zz_134 - 2'b01); + assign _zz_300 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_301 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_302 = writeBack_MUL_LOW[31 : 0]; + assign _zz_303 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_304 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_305 = {5'd0, _zz_304}; + assign _zz_306 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_307 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_308 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_309 = {_zz_136,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_310 = _zz_311; + assign _zz_311 = _zz_312; + assign _zz_312 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_137) : _zz_137)} + _zz_314); + assign _zz_313 = memory_DivPlugin_div_needRevert; + assign _zz_314 = {32'd0, _zz_313}; + assign _zz_315 = _zz_139; + assign _zz_316 = {32'd0, _zz_315}; + assign _zz_317 = _zz_138; + assign _zz_318 = {31'd0, _zz_317}; + assign _zz_319 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_320 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_321 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_322 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_323 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_324 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_325 = (iBus_cmd_payload_address >>> 5); + assign _zz_326 = 1'b1; + assign _zz_327 = 1'b1; + assign _zz_328 = {_zz_59,_zz_58}; + assign _zz_329 = 32'h0000107f; + assign _zz_330 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_331 = 32'h00002073; + assign _zz_332 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_333 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_334 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_335) == 32'h00000003),{(_zz_336 == _zz_337),{_zz_338,{_zz_339,_zz_340}}}}}}; + assign _zz_335 = 32'h0000505f; + assign _zz_336 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_337 = 32'h00000063; + assign _zz_338 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_339 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_340 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_341) == 32'h00001013),{(_zz_342 == _zz_343),{_zz_344,{_zz_345,_zz_346}}}}}}; + assign _zz_341 = 32'hfc00307f; + assign _zz_342 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_343 = 32'h00005033; + assign _zz_344 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_345 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_346 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz_347 = decode_INSTRUCTION[31]; + assign _zz_348 = decode_INSTRUCTION[31]; + assign _zz_349 = decode_INSTRUCTION[7]; + assign _zz_350 = 32'h10103050; + assign _zz_351 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_352 = 1'b0; + assign _zz_353 = (((decode_INSTRUCTION & _zz_356) == 32'h02000030) != 1'b0); + assign _zz_354 = ((_zz_357 == _zz_358) != 1'b0); + assign _zz_355 = {(_zz_359 != 1'b0),{(_zz_360 != _zz_361),{_zz_362,{_zz_363,_zz_364}}}}; + assign _zz_356 = 32'h02004074; + assign _zz_357 = (decode_INSTRUCTION & 32'h10103050); + assign _zz_358 = 32'h00000050; + assign _zz_359 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz_360 = {(_zz_365 == _zz_366),(_zz_367 == _zz_368)}; + assign _zz_361 = 2'b00; + assign _zz_362 = ({_zz_90,_zz_369} != 2'b00); + assign _zz_363 = (_zz_370 != 1'b0); + assign _zz_364 = {(_zz_371 != _zz_372),{_zz_373,{_zz_374,_zz_375}}}; + assign _zz_365 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_366 = 32'h00001050; + assign _zz_367 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_368 = 32'h00002050; + assign _zz_369 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_370 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_371 = {(_zz_376 == _zz_377),(_zz_378 == _zz_379)}; + assign _zz_372 = 2'b00; + assign _zz_373 = ({_zz_380,{_zz_381,_zz_382}} != 3'b000); + assign _zz_374 = (_zz_383 != 1'b0); + assign _zz_375 = {(_zz_384 != _zz_385),{_zz_386,{_zz_387,_zz_388}}}; + assign _zz_376 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_377 = 32'h00005010; + assign _zz_378 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_379 = 32'h00005020; + assign _zz_380 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_381 = ((decode_INSTRUCTION & _zz_389) == 32'h00001010); + assign _zz_382 = ((decode_INSTRUCTION & _zz_390) == 32'h00001010); + assign _zz_383 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_384 = ((decode_INSTRUCTION & _zz_391) == 32'h00001000); + assign _zz_385 = 1'b0; + assign _zz_386 = ((_zz_392 == _zz_393) != 1'b0); + assign _zz_387 = ({_zz_394,_zz_395} != 2'b00); + assign _zz_388 = {(_zz_396 != _zz_397),{_zz_398,{_zz_399,_zz_400}}}; + assign _zz_389 = 32'h00007034; + assign _zz_390 = 32'h02007054; + assign _zz_391 = 32'h00001000; + assign _zz_392 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_393 = 32'h00002000; + assign _zz_394 = ((decode_INSTRUCTION & _zz_401) == 32'h00002000); + assign _zz_395 = ((decode_INSTRUCTION & _zz_402) == 32'h00001000); + assign _zz_396 = ((decode_INSTRUCTION & _zz_403) == 32'h00004008); + assign _zz_397 = 1'b0; + assign _zz_398 = ({_zz_404,_zz_405} != 2'b00); + assign _zz_399 = ({_zz_406,_zz_407} != 3'b000); + assign _zz_400 = {(_zz_408 != _zz_409),{_zz_410,{_zz_411,_zz_412}}}; + assign _zz_401 = 32'h00002010; + assign _zz_402 = 32'h00005000; + assign _zz_403 = 32'h00004048; + assign _zz_404 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_405 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_406 = ((decode_INSTRUCTION & _zz_413) == 32'h00000040); + assign _zz_407 = {(_zz_414 == _zz_415),(_zz_416 == _zz_417)}; + assign _zz_408 = ((decode_INSTRUCTION & _zz_418) == 32'h00000020); + assign _zz_409 = 1'b0; + assign _zz_410 = ({_zz_419,{_zz_420,_zz_421}} != 5'h0); + assign _zz_411 = ({_zz_422,_zz_423} != 5'h0); + assign _zz_412 = {(_zz_424 != _zz_425),{_zz_426,{_zz_427,_zz_428}}}; + assign _zz_413 = 32'h00000050; + assign _zz_414 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_415 = 32'h0; + assign _zz_416 = (decode_INSTRUCTION & 32'h00103040); + assign _zz_417 = 32'h00000040; + assign _zz_418 = 32'h00000020; + assign _zz_419 = ((decode_INSTRUCTION & _zz_429) == 32'h00000040); + assign _zz_420 = _zz_89; + assign _zz_421 = {_zz_430,{_zz_431,_zz_432}}; + assign _zz_422 = _zz_89; + assign _zz_423 = {_zz_433,{_zz_434,_zz_435}}; + assign _zz_424 = {_zz_90,{_zz_436,_zz_437}}; + assign _zz_425 = 6'h0; + assign _zz_426 = ({_zz_438,_zz_439} != 2'b00); + assign _zz_427 = (_zz_440 != _zz_441); + assign _zz_428 = {_zz_442,{_zz_443,_zz_444}}; + assign _zz_429 = 32'h00000040; + assign _zz_430 = ((decode_INSTRUCTION & _zz_445) == 32'h00004020); + assign _zz_431 = (_zz_446 == _zz_447); + assign _zz_432 = (_zz_448 == _zz_449); + assign _zz_433 = ((decode_INSTRUCTION & _zz_450) == 32'h00002010); + assign _zz_434 = (_zz_451 == _zz_452); + assign _zz_435 = {_zz_453,_zz_454}; + assign _zz_436 = (_zz_455 == _zz_456); + assign _zz_437 = {_zz_457,{_zz_458,_zz_459}}; + assign _zz_438 = _zz_89; + assign _zz_439 = (_zz_460 == _zz_461); + assign _zz_440 = {_zz_89,_zz_462}; + assign _zz_441 = 2'b00; + assign _zz_442 = (_zz_463 != 1'b0); + assign _zz_443 = (_zz_464 != _zz_465); + assign _zz_444 = {_zz_466,{_zz_467,_zz_468}}; + assign _zz_445 = 32'h00004020; + assign _zz_446 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_447 = 32'h00000010; + assign _zz_448 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_449 = 32'h00000020; + assign _zz_450 = 32'h00002030; + assign _zz_451 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_452 = 32'h00000010; + assign _zz_453 = ((decode_INSTRUCTION & _zz_469) == 32'h00002020); + assign _zz_454 = ((decode_INSTRUCTION & _zz_470) == 32'h00000020); + assign _zz_455 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_456 = 32'h00001010; + assign _zz_457 = ((decode_INSTRUCTION & _zz_471) == 32'h00002010); + assign _zz_458 = (_zz_472 == _zz_473); + assign _zz_459 = {_zz_474,_zz_475}; + assign _zz_460 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_461 = 32'h00000020; + assign _zz_462 = ((decode_INSTRUCTION & _zz_476) == 32'h0); + assign _zz_463 = ((decode_INSTRUCTION & _zz_477) == 32'h00004010); + assign _zz_464 = (_zz_478 == _zz_479); + assign _zz_465 = 1'b0; + assign _zz_466 = ({_zz_480,_zz_481} != 4'b0000); + assign _zz_467 = (_zz_482 != _zz_483); + assign _zz_468 = {_zz_484,{_zz_485,_zz_486}}; + assign _zz_469 = 32'h02002060; + assign _zz_470 = 32'h02003020; + assign _zz_471 = 32'h00002010; + assign _zz_472 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_473 = 32'h00000010; + assign _zz_474 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_475 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_476 = 32'h00000020; + assign _zz_477 = 32'h00004014; + assign _zz_478 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_479 = 32'h00002010; + assign _zz_480 = ((decode_INSTRUCTION & _zz_487) == 32'h0); + assign _zz_481 = {(_zz_488 == _zz_489),{_zz_490,_zz_491}}; + assign _zz_482 = ((decode_INSTRUCTION & _zz_492) == 32'h0); + assign _zz_483 = 1'b0; + assign _zz_484 = ({_zz_493,{_zz_494,_zz_495}} != 3'b000); + assign _zz_485 = ({_zz_496,_zz_497} != 2'b00); + assign _zz_486 = {(_zz_498 != _zz_499),(_zz_500 != _zz_501)}; + assign _zz_487 = 32'h00000044; + assign _zz_488 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_489 = 32'h0; + assign _zz_490 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_491 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_492 = 32'h00000058; + assign _zz_493 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_494 = ((decode_INSTRUCTION & _zz_502) == 32'h00002010); + assign _zz_495 = ((decode_INSTRUCTION & _zz_503) == 32'h40000030); + assign _zz_496 = ((decode_INSTRUCTION & _zz_504) == 32'h00000004); + assign _zz_497 = _zz_88; + assign _zz_498 = {(_zz_505 == _zz_506),_zz_88}; + assign _zz_499 = 2'b00; + assign _zz_500 = ((decode_INSTRUCTION & _zz_507) == 32'h00001008); + assign _zz_501 = 1'b0; + assign _zz_502 = 32'h00002014; + assign _zz_503 = 32'h40000034; + assign _zz_504 = 32'h00000014; + assign _zz_505 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_506 = 32'h00000004; + assign _zz_507 = 32'h00005048; + assign _zz_508 = execute_INSTRUCTION[31]; + assign _zz_509 = execute_INSTRUCTION[31]; + assign _zz_510 = execute_INSTRUCTION[7]; + always @ (posedge clk) begin + if(_zz_326) begin + _zz_191 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_14_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; + always @ (posedge clk) begin + if(_zz_327) begin + _zz_192 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; + always @ (posedge clk) begin + if(_zz_42) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_12_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_16_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_17_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_13_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; - end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; - end - if(_zz_15_)begin - lineLoader_flushPending <= 1'b0; + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_163 ), //i + .io_cpu_prefetch_isValid (_zz_164 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_165 ), //i + .io_cpu_fetch_isStuck (_zz_166 ), //i + .io_cpu_fetch_isRemoved (_zz_167 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_168 ), //i + .io_cpu_decode_isStuck (_zz_169 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_170 ), //i + .io_cpu_fill_valid (_zz_171 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_9 (_zz_144[2:0] ), //i + ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_172 ), //i + .io_cpu_execute_address (_zz_173[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_82[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_174 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_175[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_176 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_177 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_178 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_179[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_180 ), //i + .io_cpu_writeBack_fence_SR (_zz_181 ), //i + .io_cpu_writeBack_fence_SO (_zz_182 ), //i + .io_cpu_writeBack_fence_SI (_zz_183 ), //i + .io_cpu_writeBack_fence_PW (_zz_184 ), //i + .io_cpu_writeBack_fence_PR (_zz_185 ), //i + .io_cpu_writeBack_fence_PO (_zz_186 ), //i + .io_cpu_writeBack_fence_PI (_zz_187 ), //i + .io_cpu_writeBack_fence_FM (_zz_188[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_189 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_190 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_328) + 2'b00 : begin + _zz_193 = DBusCachedPlugin_redoBranch_payload; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; + 2'b01 : begin + _zz_193 = CsrPlugin_jumpInterface_payload; end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; + 2'b10 : begin + _zz_193 = BranchPlugin_jumpInterface_payload; end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end + default : begin + _zz_193 = IBusCachedPlugin_predictionJumpInterface_payload; end - end + endcase end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_14_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); - end - _zz_3_ <= lineLoader_flushCounter[7]; - if(_zz_15_)begin - lineLoader_flushCounter <= (8'b00000000); - end - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_error <= fetchStage_hit_error; - end - if((_zz_10_ != (3'b000)))begin - io_cpu_fetch_data_regNextWhen <= _zz_11_; - end + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; + endcase end - -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, - input [1:0] io_cpu_execute_args_size, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - input io_cpu_memory_isRemoved, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - output io_cpu_memory_mmuBus_cmd_isValid, - output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, - output io_cpu_memory_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, - input io_cpu_memory_mmuBus_rsp_isIoAccess, - input io_cpu_memory_mmuBus_rsp_allowRead, - input io_cpu_memory_mmuBus_rsp_allowWrite, - input io_cpu_memory_mmuBus_rsp_allowExecute, - input io_cpu_memory_mmuBus_rsp_exception, - input io_cpu_memory_mmuBus_rsp_refilling, - output io_cpu_memory_mmuBus_end, - input io_cpu_memory_mmuBus_busy, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output reg io_cpu_flush_ready, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, - output reg io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire _zz_16_; - wire _zz_17_; - wire [0:0] _zz_18_; - wire [0:0] _zz_19_; - wire [0:0] _zz_20_; - wire [2:0] _zz_21_; - wire [1:0] _zz_22_; - wire [21:0] _zz_23_; - reg _zz_1_; - reg _zz_2_; - wire haltCpu; - reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3_; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4_; - wire _zz_5_; - wire [31:0] ways_0_dataReadRsp; - reg [3:0] _zz_6_; - wire [3:0] stage0_mask; - wire [0:0] stage0_colisions; - reg stageA_request_wr; - reg [31:0] stageA_request_data; - reg [1:0] stageA_request_size; - reg [3:0] stageA_mask; - wire stageA_wayHits_0; - reg [0:0] stage0_colisions_regNextWhen; - wire [0:0] _zz_7_; - wire [0:0] stageA_colisions; - reg stageB_request_wr; - reg [31:0] stageB_request_data; - reg [1:0] stageB_request_size; - reg stageB_mmuRspFreeze; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg [31:0] stageB_dataReadRsp_0; - wire [0:0] _zz_8_; - reg [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - reg [3:0] stageB_mask; - reg [0:0] stageB_colisions; - reg stageB_loaderValid; - reg stageB_flusher_valid; - wire [31:0] stageB_requestDataBypass; - wire stageB_isAmo; - reg stageB_memCmdSent; - wire [0:0] _zz_9_; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [2:0] loader_counter_valueNext; - reg [2:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_24_; - reg [7:0] _zz_25_; - reg [7:0] _zz_26_; - reg [7:0] _zz_27_; - assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); - assign _zz_15_ = (loader_valid && io_mem_rsp_valid); - assign _zz_16_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - assign _zz_17_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign _zz_18_ = _zz_4_[0 : 0]; - assign _zz_19_ = _zz_4_[1 : 1]; - assign _zz_20_ = loader_counter_willIncrement; - assign _zz_21_ = {2'd0, _zz_20_}; - assign _zz_22_ = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_23_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_23_; - end + always @(*) begin + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_3_) begin - _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; - end + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase end - - always @ (*) begin - _zz_11_ = {_zz_27_, _zz_26_, _zz_25_, _zz_24_}; + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase end - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1_) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1_) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1_) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1_) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_5_) begin - _zz_24_ <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_25_ <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_26_ <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_27_ <= ways_0_data_symbol3[dataReadCmd_payload]; - end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase end - - always @ (*) begin - _zz_1_ = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_1_ = 1'b1; - end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase end - - always @ (*) begin - _zz_2_ = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_2_ = 1'b1; - end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase end - - assign haltCpu = 1'b0; - assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4_ = _zz_10_; - assign ways_0_tagsReadRsp_valid = _zz_18_[0]; - assign ways_0_tagsReadRsp_error = _zz_19_[0]; - assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; - assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRsp = _zz_11_; - always @ (*) begin - tagsReadCmd_valid = 1'b0; - if(_zz_12_)begin - tagsReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; + endcase end - - always @ (*) begin - tagsReadCmd_payload = (7'bxxxxxxx); - if(_zz_12_)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; - end + always @(*) begin + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_valid = 1'b0; - if(_zz_12_)begin - dataReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; + endcase end - - always @ (*) begin - dataReadCmd_payload = (10'bxxxxxxxxxx); - if(_zz_12_)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; - end - if(_zz_13_)begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_valid = 1'b1; - end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_way = (1'bx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = (1'b1); - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_address = (7'bxxxxxxx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_valid = 1'b1; - end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); - end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end + always @(*) begin + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((stageB_request_wr && stageB_waysHit))begin - dataWriteCmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - dataWriteCmd_valid = 1'b0; - end - if(_zz_15_)begin - dataWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_way = (1'bx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_way = stageB_waysHits; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_address = (10'bxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; - end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_data = stageB_requestDataBypass; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end + always @(*) begin + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_mask = (4'bxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_mask = stageB_mask; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_mask = (4'b1111); - end + always @(*) begin + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; + endcase end - - always @ (*) begin - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_6_ = (4'b0001); - end - 2'b01 : begin - _zz_6_ = (4'b0011); - end - default : begin - _zz_6_ = (4'b1111); - end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; endcase end - - assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); - assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; - assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; - assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); - always @ (*) begin - stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin - stageB_mmuRspFreeze = 1'b1; - end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase end - - assign _zz_8_[0] = stageA_wayHits_0; - assign stageB_waysHit = (stageB_waysHits != (1'b0)); - assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - if(io_mem_cmd_ready)begin - stageB_loaderValid = 1'b1; - end - end - end - end - if(_zz_13_)begin - stageB_loaderValid = 1'b0; - end + always @(*) begin + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(_zz_14_)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - if(_zz_13_)begin - io_cpu_writeBack_haltIt = 1'b0; - end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(_zz_16_)begin - io_cpu_flush_ready = 1'b1; - end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase end - - assign stageB_requestDataBypass = stageB_request_data; - assign stageB_isAmo = 1'b0; - always @ (*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin - io_cpu_redo = 1'b1; - end - end - end - end - if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin - io_cpu_redo = 1'b1; - end - if(loader_valid)begin - io_cpu_redo = 1'b1; - end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); - end + always @(*) begin + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; + endcase end - - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_valid = (! stageB_memCmdSent); - end else begin - if(_zz_14_)begin - if(stageB_request_wr)begin - io_mem_cmd_valid = 1'b1; - end - end else begin - if((! stageB_memCmdSent))begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - io_mem_cmd_valid = 1'b0; - end + always @(*) begin + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; - end - end - end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_length = (3'bxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - io_mem_cmd_payload_length = (3'b111); - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_last = 1'bx; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - io_mem_cmd_payload_last = 1'b1; - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - always @ (*) begin - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_data = io_mem_rsp_payload_data; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - end - - assign _zz_9_[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin - loader_counter_willIncrement = 1'b0; - if(_zz_15_)begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_21_); - if(loader_counter_willClear)begin - loader_counter_valueNext = (3'b000); - end - end - - always @ (posedge clk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; - stageA_request_size <= io_cpu_execute_args_size; - end - if((! io_cpu_memory_isStuck))begin - stageA_mask <= stage0_mask; - end - if((! io_cpu_memory_isStuck))begin - stage0_colisions_regNextWhen <= stage0_colisions; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; - stageB_request_size <= stageA_request_size; - end - if(_zz_17_)begin - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_waysHits <= _zz_8_; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_mask <= stageA_mask; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_colisions <= stageA_colisions; - end - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); - end - end - - always @ (posedge clk) begin - if(reset) begin - stageB_flusher_valid <= 1'b1; - stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); - stageB_memCmdSent <= 1'b0; - loader_valid <= 1'b0; - loader_counter_value <= (3'b000); - loader_waysAllocator <= (1'b1); - loader_error <= 1'b0; - end else begin - if(_zz_17_)begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; - end - if(stageB_flusher_valid)begin - if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); - end else begin - stageB_flusher_valid <= 1'b0; - end - end - if(_zz_16_)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); - stageB_flusher_valid <= 1'b1; - end - if(io_mem_cmd_ready)begin - stageB_memCmdSent <= 1'b1; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_memCmdSent <= 1'b0; - end - if(stageB_loaderValid)begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(_zz_15_)begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_counter_willOverflow)begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - end - if((! loader_valid))begin - loader_waysAllocator <= _zz_22_[0:0]; - end - end - end - -endmodule - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset, - input debugReset); - wire _zz_226_; - wire _zz_227_; - wire _zz_228_; - wire _zz_229_; - wire [31:0] _zz_230_; - wire _zz_231_; - wire _zz_232_; - wire _zz_233_; - reg _zz_234_; - wire _zz_235_; - wire [31:0] _zz_236_; - wire _zz_237_; - wire [31:0] _zz_238_; - reg _zz_239_; - wire _zz_240_; - wire _zz_241_; - wire [31:0] _zz_242_; - wire _zz_243_; - wire _zz_244_; - reg [31:0] _zz_245_; - reg [31:0] _zz_246_; - reg [31:0] _zz_247_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1__io_cpu_memory_isWrite; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; - wire dataCache_1__io_cpu_memory_mmuBus_end; - wire dataCache_1__io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1__io_cpu_writeBack_data; - wire dataCache_1__io_cpu_writeBack_mmuException; - wire dataCache_1__io_cpu_writeBack_unalignedAccess; - wire dataCache_1__io_cpu_writeBack_accessError; - wire dataCache_1__io_cpu_writeBack_isWrite; - wire dataCache_1__io_cpu_flush_ready; - wire dataCache_1__io_cpu_redo; - wire dataCache_1__io_mem_cmd_valid; - wire dataCache_1__io_mem_cmd_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_payload_length; - wire dataCache_1__io_mem_cmd_payload_last; - wire _zz_248_; - wire _zz_249_; - wire _zz_250_; - wire _zz_251_; - wire _zz_252_; - wire _zz_253_; - wire _zz_254_; - wire _zz_255_; - wire _zz_256_; - wire _zz_257_; - wire _zz_258_; - wire _zz_259_; - wire _zz_260_; - wire _zz_261_; - wire _zz_262_; - wire _zz_263_; - wire _zz_264_; - wire [1:0] _zz_265_; - wire _zz_266_; - wire _zz_267_; - wire _zz_268_; - wire _zz_269_; - wire _zz_270_; - wire _zz_271_; - wire _zz_272_; - wire _zz_273_; - wire _zz_274_; - wire [1:0] _zz_275_; - wire _zz_276_; - wire [5:0] _zz_277_; - wire _zz_278_; - wire _zz_279_; - wire _zz_280_; - wire _zz_281_; - wire _zz_282_; - wire _zz_283_; - wire [1:0] _zz_284_; - wire _zz_285_; - wire [1:0] _zz_286_; - wire [4:0] _zz_287_; - wire [2:0] _zz_288_; - wire [31:0] _zz_289_; - wire [11:0] _zz_290_; - wire [31:0] _zz_291_; - wire [19:0] _zz_292_; - wire [11:0] _zz_293_; - wire [31:0] _zz_294_; - wire [31:0] _zz_295_; - wire [19:0] _zz_296_; - wire [11:0] _zz_297_; - wire [2:0] _zz_298_; - wire [2:0] _zz_299_; - wire [0:0] _zz_300_; - wire [0:0] _zz_301_; - wire [0:0] _zz_302_; - wire [0:0] _zz_303_; - wire [0:0] _zz_304_; - wire [0:0] _zz_305_; - wire [0:0] _zz_306_; - wire [0:0] _zz_307_; - wire [0:0] _zz_308_; - wire [0:0] _zz_309_; - wire [0:0] _zz_310_; - wire [0:0] _zz_311_; - wire [0:0] _zz_312_; - wire [0:0] _zz_313_; - wire [0:0] _zz_314_; - wire [0:0] _zz_315_; - wire [0:0] _zz_316_; - wire [0:0] _zz_317_; - wire [0:0] _zz_318_; - wire [2:0] _zz_319_; - wire [4:0] _zz_320_; - wire [11:0] _zz_321_; - wire [11:0] _zz_322_; - wire [31:0] _zz_323_; - wire [31:0] _zz_324_; - wire [31:0] _zz_325_; - wire [31:0] _zz_326_; - wire [31:0] _zz_327_; - wire [31:0] _zz_328_; - wire [31:0] _zz_329_; - wire [32:0] _zz_330_; - wire [31:0] _zz_331_; - wire [32:0] _zz_332_; - wire [11:0] _zz_333_; - wire [19:0] _zz_334_; - wire [11:0] _zz_335_; - wire [31:0] _zz_336_; - wire [31:0] _zz_337_; - wire [31:0] _zz_338_; - wire [11:0] _zz_339_; - wire [19:0] _zz_340_; - wire [11:0] _zz_341_; - wire [2:0] _zz_342_; - wire [1:0] _zz_343_; - wire [1:0] _zz_344_; - wire [51:0] _zz_345_; - wire [51:0] _zz_346_; - wire [51:0] _zz_347_; - wire [32:0] _zz_348_; - wire [51:0] _zz_349_; - wire [49:0] _zz_350_; - wire [51:0] _zz_351_; - wire [49:0] _zz_352_; - wire [51:0] _zz_353_; - wire [65:0] _zz_354_; - wire [65:0] _zz_355_; - wire [31:0] _zz_356_; - wire [31:0] _zz_357_; - wire [0:0] _zz_358_; - wire [5:0] _zz_359_; - wire [32:0] _zz_360_; - wire [32:0] _zz_361_; - wire [31:0] _zz_362_; - wire [31:0] _zz_363_; - wire [32:0] _zz_364_; - wire [32:0] _zz_365_; - wire [32:0] _zz_366_; - wire [0:0] _zz_367_; - wire [32:0] _zz_368_; - wire [0:0] _zz_369_; - wire [32:0] _zz_370_; - wire [0:0] _zz_371_; - wire [31:0] _zz_372_; - wire [0:0] _zz_373_; - wire [0:0] _zz_374_; - wire [0:0] _zz_375_; - wire [0:0] _zz_376_; - wire [0:0] _zz_377_; - wire [0:0] _zz_378_; - wire [26:0] _zz_379_; - wire _zz_380_; - wire _zz_381_; - wire [2:0] _zz_382_; - wire _zz_383_; - wire _zz_384_; - wire _zz_385_; - wire [31:0] _zz_386_; - wire [31:0] _zz_387_; - wire [31:0] _zz_388_; - wire _zz_389_; - wire [0:0] _zz_390_; - wire [0:0] _zz_391_; - wire _zz_392_; - wire [0:0] _zz_393_; - wire [26:0] _zz_394_; - wire [31:0] _zz_395_; - wire [31:0] _zz_396_; - wire [31:0] _zz_397_; - wire [31:0] _zz_398_; - wire _zz_399_; - wire [0:0] _zz_400_; - wire [1:0] _zz_401_; - wire [0:0] _zz_402_; - wire [3:0] _zz_403_; - wire [0:0] _zz_404_; - wire [0:0] _zz_405_; - wire _zz_406_; - wire [0:0] _zz_407_; - wire [22:0] _zz_408_; - wire [31:0] _zz_409_; - wire [31:0] _zz_410_; - wire [31:0] _zz_411_; - wire _zz_412_; - wire _zz_413_; - wire _zz_414_; - wire [0:0] _zz_415_; - wire [1:0] _zz_416_; - wire [31:0] _zz_417_; - wire [31:0] _zz_418_; - wire _zz_419_; - wire [0:0] _zz_420_; - wire [0:0] _zz_421_; - wire _zz_422_; - wire [0:0] _zz_423_; - wire [20:0] _zz_424_; - wire [31:0] _zz_425_; - wire [31:0] _zz_426_; - wire [31:0] _zz_427_; - wire [31:0] _zz_428_; - wire [31:0] _zz_429_; - wire _zz_430_; - wire _zz_431_; - wire [31:0] _zz_432_; - wire [31:0] _zz_433_; - wire [31:0] _zz_434_; - wire [0:0] _zz_435_; - wire [1:0] _zz_436_; - wire [1:0] _zz_437_; - wire [1:0] _zz_438_; - wire _zz_439_; - wire [0:0] _zz_440_; - wire [18:0] _zz_441_; - wire [31:0] _zz_442_; - wire [31:0] _zz_443_; - wire [31:0] _zz_444_; - wire [31:0] _zz_445_; - wire [31:0] _zz_446_; - wire [31:0] _zz_447_; - wire [31:0] _zz_448_; - wire [31:0] _zz_449_; - wire [31:0] _zz_450_; - wire _zz_451_; - wire [0:0] _zz_452_; - wire [0:0] _zz_453_; - wire [0:0] _zz_454_; - wire [4:0] _zz_455_; - wire [1:0] _zz_456_; - wire [1:0] _zz_457_; - wire _zz_458_; - wire [0:0] _zz_459_; - wire [15:0] _zz_460_; - wire [31:0] _zz_461_; - wire [31:0] _zz_462_; - wire [31:0] _zz_463_; - wire [31:0] _zz_464_; - wire [31:0] _zz_465_; - wire _zz_466_; - wire [0:0] _zz_467_; - wire [2:0] _zz_468_; - wire _zz_469_; - wire [0:0] _zz_470_; - wire [0:0] _zz_471_; - wire [0:0] _zz_472_; - wire [0:0] _zz_473_; - wire _zz_474_; - wire [0:0] _zz_475_; - wire [13:0] _zz_476_; - wire [31:0] _zz_477_; - wire [31:0] _zz_478_; - wire [31:0] _zz_479_; - wire _zz_480_; - wire [0:0] _zz_481_; - wire [0:0] _zz_482_; - wire [31:0] _zz_483_; - wire [31:0] _zz_484_; - wire [31:0] _zz_485_; - wire [31:0] _zz_486_; - wire [31:0] _zz_487_; - wire [0:0] _zz_488_; - wire [0:0] _zz_489_; - wire [4:0] _zz_490_; - wire [4:0] _zz_491_; - wire _zz_492_; - wire [0:0] _zz_493_; - wire [11:0] _zz_494_; - wire [31:0] _zz_495_; - wire [31:0] _zz_496_; - wire [31:0] _zz_497_; - wire [31:0] _zz_498_; - wire [31:0] _zz_499_; - wire [31:0] _zz_500_; - wire [31:0] _zz_501_; - wire [31:0] _zz_502_; - wire [31:0] _zz_503_; - wire _zz_504_; - wire [0:0] _zz_505_; - wire [2:0] _zz_506_; - wire [0:0] _zz_507_; - wire [0:0] _zz_508_; - wire [0:0] _zz_509_; - wire [0:0] _zz_510_; - wire _zz_511_; - wire [0:0] _zz_512_; - wire [9:0] _zz_513_; - wire [31:0] _zz_514_; - wire _zz_515_; - wire [0:0] _zz_516_; - wire [0:0] _zz_517_; - wire [31:0] _zz_518_; - wire [31:0] _zz_519_; - wire [31:0] _zz_520_; - wire [31:0] _zz_521_; - wire [31:0] _zz_522_; - wire [31:0] _zz_523_; - wire _zz_524_; - wire [0:0] _zz_525_; - wire [0:0] _zz_526_; - wire _zz_527_; - wire [0:0] _zz_528_; - wire [7:0] _zz_529_; - wire [31:0] _zz_530_; - wire [31:0] _zz_531_; - wire [31:0] _zz_532_; - wire [31:0] _zz_533_; - wire _zz_534_; - wire [0:0] _zz_535_; - wire [0:0] _zz_536_; - wire _zz_537_; - wire [0:0] _zz_538_; - wire [4:0] _zz_539_; - wire [31:0] _zz_540_; - wire [31:0] _zz_541_; - wire _zz_542_; - wire [0:0] _zz_543_; - wire [0:0] _zz_544_; - wire [0:0] _zz_545_; - wire [0:0] _zz_546_; - wire _zz_547_; - wire [0:0] _zz_548_; - wire [0:0] _zz_549_; - wire [31:0] _zz_550_; - wire [31:0] _zz_551_; - wire _zz_552_; - wire _zz_553_; - wire [31:0] _zz_554_; - wire [31:0] _zz_555_; - wire [31:0] _zz_556_; - wire [31:0] _zz_557_; - wire [31:0] _zz_558_; - wire _zz_559_; - wire [0:0] _zz_560_; - wire [13:0] _zz_561_; - wire [31:0] _zz_562_; - wire [31:0] _zz_563_; - wire [31:0] _zz_564_; - wire _zz_565_; - wire [0:0] _zz_566_; - wire [7:0] _zz_567_; - wire [31:0] _zz_568_; - wire [31:0] _zz_569_; - wire [31:0] _zz_570_; - wire _zz_571_; - wire [0:0] _zz_572_; - wire [1:0] _zz_573_; - wire _zz_574_; - wire _zz_575_; - wire _zz_576_; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire [31:0] execute_BRANCH_CALC; - wire [51:0] memory_MUL_LOW; - wire [31:0] memory_PC; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_1_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_2_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_3_; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_4_; - wire `AluCtrlEnum_defaultEncoding_type _zz_5_; - wire `AluCtrlEnum_defaultEncoding_type _zz_6_; - wire decode_SRC2_FORCE_ZERO; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_7_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_8_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_9_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11_; - wire [33:0] execute_MUL_HL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_13_; - wire decode_IS_CSR; - wire decode_IS_DIV; - wire decode_SRC_LESS_UNSIGNED; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire [33:0] execute_MUL_LH; - wire decode_PREDICTION_HAD_BRANCHED2; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire execute_BRANCH_DO; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16_; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire [31:0] execute_MUL_LL; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_17_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19_; - wire decode_DO_EBREAK; - wire decode_MEMORY_MANAGMENT; - wire decode_CSR_READ_OPCODE; - wire decode_IS_RS2_SIGNED; - wire memory_IS_MUL; - wire execute_IS_MUL; - wire decode_IS_MUL; - wire [31:0] execute_SHIFT_RIGHT; - wire decode_IS_RS1_SIGNED; - wire `EnvCtrlEnum_defaultEncoding_type _zz_20_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_21_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_22_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_23_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_24_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_25_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; - wire decode_CSR_WRITE_OPCODE; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; - wire _zz_27_; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire [51:0] _zz_28_; - wire [33:0] _zz_29_; - wire [33:0] _zz_30_; - wire [33:0] _zz_31_; - wire [31:0] _zz_32_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34_; - wire _zz_35_; - wire _zz_36_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_37_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_38_; - wire [31:0] execute_PC; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_39_; - wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_40_; - wire _zz_41_; - wire _zz_42_; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_43_; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_44_; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45_; - wire [31:0] _zz_46_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_47_; - wire _zz_48_; - wire [31:0] _zz_49_; - wire [31:0] _zz_50_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_51_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_52_; - wire [31:0] _zz_53_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_54_; - wire [31:0] _zz_55_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_56_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_57_; - wire [31:0] _zz_58_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_59_; - wire [31:0] _zz_60_; - wire _zz_61_; - reg _zz_62_; - wire [31:0] _zz_63_; - wire [31:0] _zz_64_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire `EnvCtrlEnum_defaultEncoding_type _zz_65_; - wire _zz_66_; - wire _zz_67_; - wire _zz_68_; - wire _zz_69_; - wire _zz_70_; - wire `AluCtrlEnum_defaultEncoding_type _zz_71_; - wire _zz_72_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_73_; - wire _zz_74_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_75_; - wire _zz_76_; - wire _zz_77_; - wire _zz_78_; - wire _zz_79_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_80_; - wire _zz_81_; - wire _zz_82_; - wire _zz_83_; - wire _zz_84_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_85_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_86_; - wire _zz_87_; - wire _zz_88_; - wire _zz_89_; - wire _zz_90_; - reg [31:0] _zz_91_; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_ENABLE; - wire [1:0] _zz_92_; - wire execute_MEMORY_MANAGMENT; - wire [31:0] execute_RS2; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_93_; - reg _zz_94_; - reg _zz_95_; - wire [31:0] _zz_96_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_97_; - wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_98_; - reg [31:0] _zz_99_; - wire [31:0] decode_PC; - wire [31:0] _zz_100_; - wire [31:0] _zz_101_; - wire [31:0] _zz_102_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_predictionJumpInterface_valid; - (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; - reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; - wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire DBusCachedPlugin_mmuBus_rsp_allowRead; - wire DBusCachedPlugin_mmuBus_rsp_allowWrite; - wire DBusCachedPlugin_mmuBus_rsp_allowExecute; - wire DBusCachedPlugin_mmuBus_rsp_exception; - wire DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_103_; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; - reg IBusCachedPlugin_injectionPort_valid; - reg IBusCachedPlugin_injectionPort_ready; - wire [31:0] IBusCachedPlugin_injectionPort_payload; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_104_; - wire [4:0] _zz_105_; - wire _zz_106_; - wire _zz_107_; - wire _zz_108_; - wire _zz_109_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_110_; - wire _zz_111_; - wire _zz_112_; - wire _zz_113_; - wire _zz_114_; - reg _zz_115_; - wire _zz_116_; - reg _zz_117_; - reg [31:0] _zz_118_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_decodeInput_valid; - wire IBusCachedPlugin_iBusRsp_decodeInput_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - reg IBusCachedPlugin_injector_decodeRemoved; - wire _zz_119_; - reg [18:0] _zz_120_; - wire _zz_121_; - reg [10:0] _zz_122_; - wire _zz_123_; - reg [18:0] _zz_124_; - reg _zz_125_; - wire _zz_126_; - reg [10:0] _zz_127_; - wire _zz_128_; - reg [18:0] _zz_129_; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_130_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; - wire dBus_cmd_payload_last; - wire dBus_rsp_valid; - wire [31:0] dBus_rsp_payload_data; - wire dBus_rsp_payload_error; - wire dataCache_1__io_mem_cmd_s2mPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; - reg _zz_131_; - reg _zz_132_; - reg [31:0] _zz_133_; - reg [31:0] _zz_134_; - reg [3:0] _zz_135_; - reg [2:0] _zz_136_; - reg _zz_137_; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg _zz_138_; - reg _zz_139_; - reg [31:0] _zz_140_; - reg [31:0] _zz_141_; - reg [3:0] _zz_142_; - reg [2:0] _zz_143_; - reg _zz_144_; - wire [31:0] _zz_145_; - reg [31:0] DBusCachedPlugin_rspCounter; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_146_; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_147_; - reg [31:0] _zz_148_; - wire _zz_149_; - reg [31:0] _zz_150_; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [32:0] _zz_151_; - wire _zz_152_; - wire _zz_153_; - wire _zz_154_; - wire _zz_155_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_156_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_157_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_158_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_159_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_160_; - wire `AluCtrlEnum_defaultEncoding_type _zz_161_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_162_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_163_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_164_; - reg [31:0] _zz_165_; - wire _zz_166_; - reg [19:0] _zz_167_; - wire _zz_168_; - reg [19:0] _zz_169_; - reg [31:0] _zz_170_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_171_; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_172_; - reg _zz_173_; - reg _zz_174_; - wire _zz_175_; - reg _zz_176_; - reg [4:0] _zz_177_; - reg [31:0] _zz_178_; - wire _zz_179_; - wire _zz_180_; - wire _zz_181_; - wire _zz_182_; - wire _zz_183_; - wire _zz_184_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_185_; - reg _zz_186_; - reg _zz_187_; - wire _zz_188_; - reg [19:0] _zz_189_; - wire _zz_190_; - reg [10:0] _zz_191_; - wire _zz_192_; - reg [18:0] _zz_193_; - reg _zz_194_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_195_; - reg [19:0] _zz_196_; - wire _zz_197_; - reg [10:0] _zz_198_; - wire _zz_199_; - reg [18:0] _zz_200_; - wire [31:0] execute_BranchPlugin_branchAdder; - wire [1:0] CsrPlugin_misa_base; - wire [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_201_; - wire _zz_202_; - wire _zz_203_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_204_; - wire _zz_205_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - wire [65:0] writeBack_MulPlugin_result; - reg [32:0] memory_DivPlugin_rs1; - reg [31:0] memory_DivPlugin_rs2; - reg [64:0] memory_DivPlugin_accumulator; - reg memory_DivPlugin_div_needRevert; - reg memory_DivPlugin_div_counter_willIncrement; - reg memory_DivPlugin_div_counter_willClear; - reg [5:0] memory_DivPlugin_div_counter_valueNext; - reg [5:0] memory_DivPlugin_div_counter_value; - wire memory_DivPlugin_div_counter_willOverflowIfInc; - wire memory_DivPlugin_div_counter_willOverflow; - reg memory_DivPlugin_div_done; - reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_206_; - wire [32:0] _zz_207_; - wire [32:0] _zz_208_; - wire [31:0] _zz_209_; - wire _zz_210_; - wire _zz_211_; - reg [32:0] _zz_212_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_213_; - wire [31:0] _zz_214_; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_215_; - reg DebugPlugin_resetIt_regNext; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg [31:0] decode_to_execute_RS1; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg decode_to_execute_IS_RS1_SIGNED; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg memory_to_writeBack_IS_MUL; - reg decode_to_execute_IS_RS2_SIGNED; - reg decode_to_execute_CSR_READ_OPCODE; - reg decode_to_execute_MEMORY_MANAGMENT; - reg decode_to_execute_DO_EBREAK; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg [31:0] execute_to_memory_MUL_LL; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg execute_to_memory_BRANCH_DO; - reg decode_to_execute_MEMORY_WR; - reg execute_to_memory_MEMORY_WR; - reg memory_to_writeBack_MEMORY_WR; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg [33:0] execute_to_memory_MUL_HH; - reg [33:0] memory_to_writeBack_MUL_HH; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg [33:0] execute_to_memory_MUL_LH; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg decode_to_execute_IS_CSR; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg [31:0] decode_to_execute_RS2; - reg [33:0] execute_to_memory_MUL_HL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg [51:0] memory_to_writeBack_MUL_LOW; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg [2:0] _zz_216_; - reg [2:0] _zz_217_; - reg _zz_218_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_219_; - wire _zz_220_; - wire _zz_221_; - wire _zz_222_; - wire _zz_223_; - wire _zz_224_; - reg _zz_225_; - reg [31:0] dBusWishbone_DAT_MISO_regNext; - `ifndef SYNTHESIS - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_1__string; - reg [95:0] _zz_2__string; - reg [95:0] _zz_3__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_4__string; - reg [63:0] _zz_5__string; - reg [63:0] _zz_6__string; - reg [71:0] _zz_7__string; - reg [71:0] _zz_8__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_9__string; - reg [71:0] _zz_10__string; - reg [71:0] _zz_11__string; - reg [31:0] _zz_12__string; - reg [31:0] _zz_13__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_14__string; - reg [39:0] _zz_15__string; - reg [39:0] _zz_16__string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_17__string; - reg [23:0] _zz_18__string; - reg [23:0] _zz_19__string; - reg [39:0] _zz_20__string; - reg [39:0] _zz_21__string; - reg [39:0] _zz_22__string; - reg [39:0] _zz_23__string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_24__string; - reg [39:0] _zz_25__string; - reg [39:0] _zz_26__string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33__string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34__string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_37__string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_40__string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_45__string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_47__string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_52__string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_54__string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_57__string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_59__string; - reg [39:0] _zz_65__string; - reg [63:0] _zz_71__string; - reg [71:0] _zz_73__string; - reg [95:0] _zz_75__string; - reg [39:0] _zz_80__string; - reg [23:0] _zz_85__string; - reg [31:0] _zz_86__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_97__string; - reg [31:0] _zz_156__string; - reg [23:0] _zz_157__string; - reg [39:0] _zz_158__string; - reg [95:0] _zz_159__string; - reg [71:0] _zz_160__string; - reg [63:0] _zz_161__string; - reg [39:0] _zz_162__string; - reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - `endif - - (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_248_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_249_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_250_ = 1'b1; - assign _zz_251_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_252_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_253_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_254_ = ((_zz_231_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_93_)); - assign _zz_255_ = ((_zz_231_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_94_)); - assign _zz_256_ = ((_zz_231_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_95_)); - assign _zz_257_ = ((_zz_231_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); - assign _zz_258_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_259_ = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_260_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0); - assign _zz_261_ = (! memory_DivPlugin_div_done); - assign _zz_262_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_263_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_264_ = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_265_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_266_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_267_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_268_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_269_ = (1'b0 || (! 1'b1)); - assign _zz_270_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_271_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_272_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_273_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_274_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_275_ = execute_INSTRUCTION[13 : 12]; - assign _zz_276_ = (! memory_arbitration_isStuck); - assign _zz_277_ = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_278_ = (iBus_cmd_valid || (_zz_217_ != (3'b000))); - assign _zz_279_ = (_zz_244_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); - assign _zz_280_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_281_ = ((_zz_201_ && 1'b1) && (! 1'b0)); - assign _zz_282_ = ((_zz_202_ && 1'b1) && (! 1'b0)); - assign _zz_283_ = ((_zz_203_ && 1'b1) && (! 1'b0)); - assign _zz_284_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_285_ = execute_INSTRUCTION[13]; - assign _zz_286_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_287_ = (_zz_104_ - (5'b00001)); - assign _zz_288_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_289_ = {29'd0, _zz_288_}; - assign _zz_290_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_291_ = {{_zz_120_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_292_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_293_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_294_ = {{_zz_122_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_295_ = {{_zz_124_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_296_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_297_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_298_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); - assign _zz_299_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); - assign _zz_300_ = _zz_151_[0 : 0]; - assign _zz_301_ = _zz_151_[1 : 1]; - assign _zz_302_ = _zz_151_[2 : 2]; - assign _zz_303_ = _zz_151_[7 : 7]; - assign _zz_304_ = _zz_151_[8 : 8]; - assign _zz_305_ = _zz_151_[9 : 9]; - assign _zz_306_ = _zz_151_[10 : 10]; - assign _zz_307_ = _zz_151_[13 : 13]; - assign _zz_308_ = _zz_151_[14 : 14]; - assign _zz_309_ = _zz_151_[15 : 15]; - assign _zz_310_ = _zz_151_[16 : 16]; - assign _zz_311_ = _zz_151_[19 : 19]; - assign _zz_312_ = _zz_151_[23 : 23]; - assign _zz_313_ = _zz_151_[26 : 26]; - assign _zz_314_ = _zz_151_[27 : 27]; - assign _zz_315_ = _zz_151_[28 : 28]; - assign _zz_316_ = _zz_151_[29 : 29]; - assign _zz_317_ = _zz_151_[30 : 30]; - assign _zz_318_ = execute_SRC_LESS; - assign _zz_319_ = (3'b100); - assign _zz_320_ = execute_INSTRUCTION[19 : 15]; - assign _zz_321_ = execute_INSTRUCTION[31 : 20]; - assign _zz_322_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_323_ = ($signed(_zz_324_) + $signed(_zz_327_)); - assign _zz_324_ = ($signed(_zz_325_) + $signed(_zz_326_)); - assign _zz_325_ = execute_SRC1; - assign _zz_326_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_327_ = (execute_SRC_USE_SUB_LESS ? _zz_328_ : _zz_329_); - assign _zz_328_ = (32'b00000000000000000000000000000001); - assign _zz_329_ = (32'b00000000000000000000000000000000); - assign _zz_330_ = ($signed(_zz_332_) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_331_ = _zz_330_[31 : 0]; - assign _zz_332_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_333_ = execute_INSTRUCTION[31 : 20]; - assign _zz_334_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_335_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_336_ = {_zz_189_,execute_INSTRUCTION[31 : 20]}; - assign _zz_337_ = {{_zz_191_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_338_ = {{_zz_193_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_339_ = execute_INSTRUCTION[31 : 20]; - assign _zz_340_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_341_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_342_ = (3'b100); - assign _zz_343_ = (_zz_204_ & (~ _zz_344_)); - assign _zz_344_ = (_zz_204_ - (2'b01)); - assign _zz_345_ = ($signed(_zz_346_) + $signed(_zz_351_)); - assign _zz_346_ = ($signed(_zz_347_) + $signed(_zz_349_)); - assign _zz_347_ = (52'b0000000000000000000000000000000000000000000000000000); - assign _zz_348_ = {1'b0,memory_MUL_LL}; - assign _zz_349_ = {{19{_zz_348_[32]}}, _zz_348_}; - assign _zz_350_ = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_351_ = {{2{_zz_350_[49]}}, _zz_350_}; - assign _zz_352_ = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_353_ = {{2{_zz_352_[49]}}, _zz_352_}; - assign _zz_354_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_355_ = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_356_ = writeBack_MUL_LOW[31 : 0]; - assign _zz_357_ = writeBack_MulPlugin_result[63 : 32]; - assign _zz_358_ = memory_DivPlugin_div_counter_willIncrement; - assign _zz_359_ = {5'd0, _zz_358_}; - assign _zz_360_ = {1'd0, memory_DivPlugin_rs2}; - assign _zz_361_ = {_zz_206_,(! _zz_208_[32])}; - assign _zz_362_ = _zz_208_[31:0]; - assign _zz_363_ = _zz_207_[31:0]; - assign _zz_364_ = _zz_365_; - assign _zz_365_ = _zz_366_; - assign _zz_366_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_209_) : _zz_209_)} + _zz_368_); - assign _zz_367_ = memory_DivPlugin_div_needRevert; - assign _zz_368_ = {32'd0, _zz_367_}; - assign _zz_369_ = _zz_211_; - assign _zz_370_ = {32'd0, _zz_369_}; - assign _zz_371_ = _zz_210_; - assign _zz_372_ = {31'd0, _zz_371_}; - assign _zz_373_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_374_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_375_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_376_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_377_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_378_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_379_ = (iBus_cmd_payload_address >>> 5); - assign _zz_380_ = 1'b1; - assign _zz_381_ = 1'b1; - assign _zz_382_ = {_zz_107_,{_zz_109_,_zz_108_}}; - assign _zz_383_ = decode_INSTRUCTION[31]; - assign _zz_384_ = decode_INSTRUCTION[31]; - assign _zz_385_ = decode_INSTRUCTION[7]; - assign _zz_386_ = (32'b00010000000100000011000001010000); - assign _zz_387_ = (decode_INSTRUCTION & (32'b00010000010000000011000001010000)); - assign _zz_388_ = (32'b00010000000000000000000001010000); - assign _zz_389_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000)); - assign _zz_390_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); - assign _zz_391_ = (1'b0); - assign _zz_392_ = ({(_zz_395_ == _zz_396_),(_zz_397_ == _zz_398_)} != (2'b00)); - assign _zz_393_ = ({_zz_399_,{_zz_400_,_zz_401_}} != (4'b0000)); - assign _zz_394_ = {({_zz_402_,_zz_403_} != (5'b00000)),{(_zz_404_ != _zz_405_),{_zz_406_,{_zz_407_,_zz_408_}}}}; - assign _zz_395_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); - assign _zz_396_ = (32'b00000000000000000001000001010000); - assign _zz_397_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); - assign _zz_398_ = (32'b00000000000000000010000001010000); - assign _zz_399_ = ((decode_INSTRUCTION & _zz_409_) == (32'b00000000000000000000000000000000)); - assign _zz_400_ = (_zz_410_ == _zz_411_); - assign _zz_401_ = {_zz_412_,_zz_413_}; - assign _zz_402_ = _zz_154_; - assign _zz_403_ = {_zz_414_,{_zz_415_,_zz_416_}}; - assign _zz_404_ = (_zz_417_ == _zz_418_); - assign _zz_405_ = (1'b0); - assign _zz_406_ = (_zz_419_ != (1'b0)); - assign _zz_407_ = (_zz_420_ != _zz_421_); - assign _zz_408_ = {_zz_422_,{_zz_423_,_zz_424_}}; - assign _zz_409_ = (32'b00000000000000000000000001000100); - assign _zz_410_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); - assign _zz_411_ = (32'b00000000000000000000000000000000); - assign _zz_412_ = ((decode_INSTRUCTION & _zz_425_) == (32'b00000000000000000010000000000000)); - assign _zz_413_ = ((decode_INSTRUCTION & _zz_426_) == (32'b00000000000000000001000000000000)); - assign _zz_414_ = ((decode_INSTRUCTION & _zz_427_) == (32'b00000000000000000010000000010000)); - assign _zz_415_ = (_zz_428_ == _zz_429_); - assign _zz_416_ = {_zz_430_,_zz_431_}; - assign _zz_417_ = (decode_INSTRUCTION & (32'b00000000000000000100000000010100)); - assign _zz_418_ = (32'b00000000000000000100000000010000); - assign _zz_419_ = ((decode_INSTRUCTION & _zz_432_) == (32'b00000000000000000010000000010000)); - assign _zz_420_ = (_zz_433_ == _zz_434_); - assign _zz_421_ = (1'b0); - assign _zz_422_ = ({_zz_435_,_zz_436_} != (3'b000)); - assign _zz_423_ = (_zz_437_ != _zz_438_); - assign _zz_424_ = {_zz_439_,{_zz_440_,_zz_441_}}; - assign _zz_425_ = (32'b00000000000000000110000000000100); - assign _zz_426_ = (32'b00000000000000000101000000000100); - assign _zz_427_ = (32'b00000000000000000010000000110000); - assign _zz_428_ = (decode_INSTRUCTION & (32'b00000000000000000001000000110000)); - assign _zz_429_ = (32'b00000000000000000000000000010000); - assign _zz_430_ = ((decode_INSTRUCTION & (32'b00000010000000000010000001100000)) == (32'b00000000000000000010000000100000)); - assign _zz_431_ = ((decode_INSTRUCTION & (32'b00000010000000000011000000100000)) == (32'b00000000000000000000000000100000)); - assign _zz_432_ = (32'b00000000000000000110000000010100); - assign _zz_433_ = (decode_INSTRUCTION & (32'b00000010000000000100000001110100)); - assign _zz_434_ = (32'b00000010000000000000000000110000); - assign _zz_435_ = ((decode_INSTRUCTION & _zz_442_) == (32'b00000000000000000000000001000000)); - assign _zz_436_ = {(_zz_443_ == _zz_444_),(_zz_445_ == _zz_446_)}; - assign _zz_437_ = {(_zz_447_ == _zz_448_),(_zz_449_ == _zz_450_)}; - assign _zz_438_ = (2'b00); - assign _zz_439_ = ({_zz_451_,{_zz_452_,_zz_453_}} != (3'b000)); - assign _zz_440_ = ({_zz_454_,_zz_455_} != (6'b000000)); - assign _zz_441_ = {(_zz_456_ != _zz_457_),{_zz_458_,{_zz_459_,_zz_460_}}}; - assign _zz_442_ = (32'b00000000000000000000000001010000); - assign _zz_443_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000)); - assign _zz_444_ = (32'b00000000000000000000000000000000); - assign _zz_445_ = (decode_INSTRUCTION & (32'b00000000000100000011000001000000)); - assign _zz_446_ = (32'b00000000000000000000000001000000); - assign _zz_447_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_448_ = (32'b00000000000000000101000000010000); - assign _zz_449_ = (decode_INSTRUCTION & (32'b00000010000000000111000001100100)); - assign _zz_450_ = (32'b00000000000000000101000000100000); - assign _zz_451_ = ((decode_INSTRUCTION & _zz_461_) == (32'b01000000000000000001000000010000)); - assign _zz_452_ = (_zz_462_ == _zz_463_); - assign _zz_453_ = (_zz_464_ == _zz_465_); - assign _zz_454_ = _zz_153_; - assign _zz_455_ = {_zz_466_,{_zz_467_,_zz_468_}}; - assign _zz_456_ = {_zz_469_,_zz_155_}; - assign _zz_457_ = (2'b00); - assign _zz_458_ = ({_zz_470_,_zz_471_} != (2'b00)); - assign _zz_459_ = (_zz_472_ != _zz_473_); - assign _zz_460_ = {_zz_474_,{_zz_475_,_zz_476_}}; - assign _zz_461_ = (32'b01000000000000000011000001010100); - assign _zz_462_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_463_ = (32'b00000000000000000001000000010000); - assign _zz_464_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100)); - assign _zz_465_ = (32'b00000000000000000001000000010000); - assign _zz_466_ = ((decode_INSTRUCTION & _zz_477_) == (32'b00000000000000000001000000010000)); - assign _zz_467_ = (_zz_478_ == _zz_479_); - assign _zz_468_ = {_zz_480_,{_zz_481_,_zz_482_}}; - assign _zz_469_ = ((decode_INSTRUCTION & _zz_483_) == (32'b00000000000000000000000000000100)); - assign _zz_470_ = (_zz_484_ == _zz_485_); - assign _zz_471_ = _zz_155_; - assign _zz_472_ = (_zz_486_ == _zz_487_); - assign _zz_473_ = (1'b0); - assign _zz_474_ = ({_zz_488_,_zz_489_} != (2'b00)); - assign _zz_475_ = (_zz_490_ != _zz_491_); - assign _zz_476_ = {_zz_492_,{_zz_493_,_zz_494_}}; - assign _zz_477_ = (32'b00000000000000000001000000010000); - assign _zz_478_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_479_ = (32'b00000000000000000010000000010000); - assign _zz_480_ = ((decode_INSTRUCTION & _zz_495_) == (32'b00000000000000000000000000010000)); - assign _zz_481_ = (_zz_496_ == _zz_497_); - assign _zz_482_ = (_zz_498_ == _zz_499_); - assign _zz_483_ = (32'b00000000000000000000000000010100); - assign _zz_484_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_485_ = (32'b00000000000000000000000000000100); - assign _zz_486_ = (decode_INSTRUCTION & (32'b00000000000000000100000001001000)); - assign _zz_487_ = (32'b00000000000000000100000000001000); - assign _zz_488_ = (_zz_500_ == _zz_501_); - assign _zz_489_ = (_zz_502_ == _zz_503_); - assign _zz_490_ = {_zz_504_,{_zz_505_,_zz_506_}}; - assign _zz_491_ = (5'b00000); - assign _zz_492_ = ({_zz_507_,_zz_508_} != (2'b00)); - assign _zz_493_ = (_zz_509_ != _zz_510_); - assign _zz_494_ = {_zz_511_,{_zz_512_,_zz_513_}}; - assign _zz_495_ = (32'b00000000000000000000000001010000); - assign _zz_496_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); - assign _zz_497_ = (32'b00000000000000000000000000000100); - assign _zz_498_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); - assign _zz_499_ = (32'b00000000000000000000000000000000); - assign _zz_500_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); - assign _zz_501_ = (32'b00000000000000000000000000100000); - assign _zz_502_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_503_ = (32'b00000000000000000000000000100000); - assign _zz_504_ = ((decode_INSTRUCTION & _zz_514_) == (32'b00000000000000000000000001000000)); - assign _zz_505_ = _zz_154_; - assign _zz_506_ = {_zz_515_,{_zz_516_,_zz_517_}}; - assign _zz_507_ = (_zz_518_ == _zz_519_); - assign _zz_508_ = (_zz_520_ == _zz_521_); - assign _zz_509_ = (_zz_522_ == _zz_523_); - assign _zz_510_ = (1'b0); - assign _zz_511_ = (_zz_524_ != (1'b0)); - assign _zz_512_ = (_zz_525_ != _zz_526_); - assign _zz_513_ = {_zz_527_,{_zz_528_,_zz_529_}}; - assign _zz_514_ = (32'b00000000000000000000000001000000); - assign _zz_515_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000100000)) == (32'b00000000000000000100000000100000)); - assign _zz_516_ = ((decode_INSTRUCTION & _zz_530_) == (32'b00000000000000000000000000010000)); - assign _zz_517_ = ((decode_INSTRUCTION & _zz_531_) == (32'b00000000000000000000000000100000)); - assign _zz_518_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_519_ = (32'b00000000000000000010000000000000); - assign _zz_520_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); - assign _zz_521_ = (32'b00000000000000000001000000000000); - assign _zz_522_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); - assign _zz_523_ = (32'b00000000000000000001000000000000); - assign _zz_524_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); - assign _zz_525_ = _zz_152_; - assign _zz_526_ = (1'b0); - assign _zz_527_ = ((_zz_532_ == _zz_533_) != (1'b0)); - assign _zz_528_ = (_zz_534_ != (1'b0)); - assign _zz_529_ = {(_zz_535_ != _zz_536_),{_zz_537_,{_zz_538_,_zz_539_}}}; - assign _zz_530_ = (32'b00000000000000000000000000110000); - assign _zz_531_ = (32'b00000010000000000000000000100000); - assign _zz_532_ = (decode_INSTRUCTION & (32'b00010000000100000011000001010000)); - assign _zz_533_ = (32'b00000000000100000000000001010000); - assign _zz_534_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001100100)) == (32'b00000010000000000100000000100000)); - assign _zz_535_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000)); - assign _zz_536_ = (1'b0); - assign _zz_537_ = ({_zz_154_,(_zz_540_ == _zz_541_)} != (2'b00)); - assign _zz_538_ = ({_zz_154_,_zz_542_} != (2'b00)); - assign _zz_539_ = {({_zz_543_,_zz_544_} != (2'b00)),{(_zz_545_ != _zz_546_),{_zz_547_,{_zz_548_,_zz_549_}}}}; - assign _zz_540_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); - assign _zz_541_ = (32'b00000000000000000000000000100000); - assign _zz_542_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); - assign _zz_543_ = _zz_153_; - assign _zz_544_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); - assign _zz_545_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); - assign _zz_546_ = (1'b0); - assign _zz_547_ = ({(_zz_550_ == _zz_551_),{_zz_552_,_zz_553_}} != (3'b000)); - assign _zz_548_ = (_zz_152_ != (1'b0)); - assign _zz_549_ = ((_zz_554_ == _zz_555_) != (1'b0)); - assign _zz_550_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_551_ = (32'b00000000000000000000000001000000); - assign _zz_552_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000010000000010000)); - assign _zz_553_ = ((decode_INSTRUCTION & (32'b01000000000000000000000000110100)) == (32'b01000000000000000000000000110000)); - assign _zz_554_ = (decode_INSTRUCTION & (32'b00000000000000000101000001001000)); - assign _zz_555_ = (32'b00000000000000000001000000001000); - assign _zz_556_ = (32'b00000000000000000001000001111111); - assign _zz_557_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_558_ = (32'b00000000000000000010000001110011); - assign _zz_559_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_560_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_561_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_562_) == (32'b00000000000000000000000000000011)),{(_zz_563_ == _zz_564_),{_zz_565_,{_zz_566_,_zz_567_}}}}}}; - assign _zz_562_ = (32'b00000000000000000101000001011111); - assign _zz_563_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_564_ = (32'b00000000000000000000000001100011); - assign _zz_565_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_566_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_567_ = {((decode_INSTRUCTION & (32'b00000001111100000111000001111111)) == (32'b00000000000000000101000000001111)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_568_) == (32'b00000000000000000001000000010011)),{(_zz_569_ == _zz_570_),{_zz_571_,{_zz_572_,_zz_573_}}}}}}; - assign _zz_568_ = (32'b11111100000000000011000001111111); - assign _zz_569_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_570_ = (32'b00000000000000000101000000110011); - assign _zz_571_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_572_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_573_ = {((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)),((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011))}; - assign _zz_574_ = execute_INSTRUCTION[31]; - assign _zz_575_ = execute_INSTRUCTION[31]; - assign _zz_576_ = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_62_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_380_) begin - _zz_245_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_381_) begin - _zz_246_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_226_), - .io_cpu_prefetch_isValid(_zz_227_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_228_), - .io_cpu_fetch_isStuck(_zz_229_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_230_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_231_), - .io_cpu_decode_isStuck(_zz_232_), - .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), - .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), - .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), - .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), - .io_cpu_decode_isUser(_zz_233_), - .io_cpu_fill_valid(_zz_234_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - ._zz_10_(_zz_216_), - ._zz_11_(IBusCachedPlugin_injectionPort_payload), - .clk(clk), - .reset(reset) - ); - DataCache dataCache_1_ ( - .io_cpu_execute_isValid(_zz_235_), - .io_cpu_execute_address(_zz_236_), - .io_cpu_execute_args_wr(execute_MEMORY_WR), - .io_cpu_execute_args_data(_zz_146_), - .io_cpu_execute_args_size(execute_DBusCachedPlugin_size), - .io_cpu_memory_isValid(_zz_237_), - .io_cpu_memory_isStuck(memory_arbitration_isStuck), - .io_cpu_memory_isRemoved(memory_arbitration_removeIt), - .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), - .io_cpu_memory_address(_zz_238_), - .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), - .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), - .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), - .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_239_), - .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), - .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), - .io_cpu_writeBack_isValid(_zz_240_), - .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), - .io_cpu_writeBack_isUser(_zz_241_), - .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), - .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), - .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), - .io_cpu_writeBack_address(_zz_242_), - .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), - .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), - .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), - .io_cpu_redo(dataCache_1__io_cpu_redo), - .io_cpu_flush_valid(_zz_243_), - .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), - .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), - .io_mem_cmd_ready(_zz_244_), - .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), - .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), - .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), - .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), - .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), - .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), - .io_mem_rsp_valid(dBus_rsp_valid), - .io_mem_rsp_payload_data(dBus_rsp_payload_data), - .io_mem_rsp_payload_error(dBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); - always @(*) begin - case(_zz_382_) - 3'b000 : begin - _zz_247_ = DBusCachedPlugin_redoBranch_payload; - end - 3'b001 : begin - _zz_247_ = CsrPlugin_jumpInterface_payload; - end - 3'b010 : begin - _zz_247_ = BranchPlugin_jumpInterface_payload; - end - 3'b011 : begin - _zz_247_ = IBusCachedPlugin_redoBranch_payload; - end - default : begin - _zz_247_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - endcase - end - - `ifndef SYNTHESIS always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_1_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_1__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_1__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_1__string = "URS1 "; - default : _zz_1__string = "????????????"; + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; endcase end always @(*) begin - case(_zz_2_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_2__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_2__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_2__string = "URS1 "; - default : _zz_2__string = "????????????"; + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_3_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_3__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_3__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_3__string = "URS1 "; - default : _zz_3__string = "????????????"; + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_4__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_4__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_4__string = "BITWISE "; - default : _zz_4__string = "????????"; + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; endcase end always @(*) begin - case(_zz_5_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_5__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_5__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_5__string = "BITWISE "; - default : _zz_5__string = "????????"; + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_6_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_6__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_6__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_6__string = "BITWISE "; - default : _zz_6__string = "????????"; + case(_zz_30) + `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; + default : _zz_30_string = "????"; endcase end always @(*) begin - case(_zz_7_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_7__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_7__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_7__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_7__string = "SRA_1 "; - default : _zz_7__string = "?????????"; + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_8_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_8__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_8__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_8__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_8__string = "SRA_1 "; - default : _zz_8__string = "?????????"; + case(_zz_33) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; + default : _zz_33_string = "?????????"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_9_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_9__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_9__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_9__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_9__string = "SRA_1 "; - default : _zz_9__string = "?????????"; + case(_zz_34) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; + default : _zz_34_string = "?????????"; endcase end always @(*) begin - case(_zz_10_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10__string = "SRA_1 "; - default : _zz_10__string = "?????????"; + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_11_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11__string = "SRA_1 "; - default : _zz_11__string = "?????????"; + case(_zz_36) + `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; + default : _zz_36_string = "???"; endcase end always @(*) begin - case(_zz_12_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12__string = "JALR"; - default : _zz_12__string = "????"; + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_13_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_13__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_13__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_13__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_13__string = "JALR"; - default : _zz_13__string = "????"; + case(_zz_37) + `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; + default : _zz_37_string = "????????????"; endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_14_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14__string = "AND_1"; - default : _zz_14__string = "?????"; + case(_zz_38) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; + default : _zz_38_string = "????????"; endcase end always @(*) begin - case(_zz_15_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15__string = "AND_1"; - default : _zz_15__string = "?????"; + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16__string = "AND_1"; - default : _zz_16__string = "?????"; + case(_zz_39) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; + default : _zz_39_string = "?????"; endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(_zz_43) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_17_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_17__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_17__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_17__string = "PC "; - default : _zz_17__string = "???"; + case(_zz_44) + `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; + default : _zz_44_string = "????"; endcase end always @(*) begin - case(_zz_18_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18__string = "PC "; - default : _zz_18__string = "???"; + case(_zz_45) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; + default : _zz_45_string = "?????????"; endcase end always @(*) begin - case(_zz_19_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19__string = "PC "; - default : _zz_19__string = "???"; + case(_zz_46) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; + default : _zz_46_string = "?????"; endcase end always @(*) begin - case(_zz_20_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_20__string = "ECALL"; - default : _zz_20__string = "?????"; + case(_zz_47) + `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; + default : _zz_47_string = "???"; endcase end always @(*) begin - case(_zz_21_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_21__string = "ECALL"; - default : _zz_21__string = "?????"; + case(_zz_48) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; + default : _zz_48_string = "????????"; endcase end always @(*) begin - case(_zz_22_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_22__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_22__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_22__string = "ECALL"; - default : _zz_22__string = "?????"; - endcase - end - always @(*) begin - case(_zz_23_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_23__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_23__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_23__string = "ECALL"; - default : _zz_23__string = "?????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_24_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_24__string = "ECALL"; - default : _zz_24__string = "?????"; - endcase - end - always @(*) begin - case(_zz_25_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25__string = "ECALL"; - default : _zz_25__string = "?????"; - endcase - end - always @(*) begin - case(_zz_26_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL"; - default : _zz_26__string = "?????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_33_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33__string = "ECALL"; - default : _zz_33__string = "?????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; - default : execute_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_34_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34__string = "ECALL"; - default : _zz_34__string = "?????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; - default : writeBack_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_37_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_37__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_37__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_37__string = "ECALL"; - default : _zz_37__string = "?????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_40_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_40__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_40__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_40__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_40__string = "JALR"; - default : _zz_40__string = "????"; - endcase - end - always @(*) begin - case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_45_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45__string = "SRA_1 "; - default : _zz_45__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_47_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_47__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_47__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_47__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_47__string = "SRA_1 "; - default : _zz_47__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; - default : execute_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_52_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_52__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_52__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_52__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_52__string = "PC "; - default : _zz_52__string = "???"; - endcase - end - always @(*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; - default : execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_54_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_54__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_54__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54__string = "URS1 "; - default : _zz_54__string = "????????????"; - endcase - end - always @(*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_57_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_57__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_57__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_57__string = "BITWISE "; - default : _zz_57__string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_59_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_59__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_59__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_59__string = "AND_1"; - default : _zz_59__string = "?????"; - endcase - end - always @(*) begin - case(_zz_65_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_65__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_65__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_65__string = "ECALL"; - default : _zz_65__string = "?????"; - endcase - end - always @(*) begin - case(_zz_71_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_71__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_71__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_71__string = "BITWISE "; - default : _zz_71__string = "????????"; - endcase - end - always @(*) begin - case(_zz_73_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_73__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_73__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_73__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_73__string = "SRA_1 "; - default : _zz_73__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_75_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_75__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_75__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_75__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_75__string = "URS1 "; - default : _zz_75__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_80_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_80__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_80__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_80__string = "AND_1"; - default : _zz_80__string = "?????"; - endcase - end - always @(*) begin - case(_zz_85_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_85__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_85__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_85__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_85__string = "PC "; - default : _zz_85__string = "???"; - endcase - end - always @(*) begin - case(_zz_86_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_86__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_86__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_86__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_86__string = "JALR"; - default : _zz_86__string = "????"; + case(_zz_49) + `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; + default : _zz_49_string = "????????????"; endcase end always @(*) begin @@ -3251,96 +2239,89 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_97_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_97__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_97__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_97__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_97__string = "JALR"; - default : _zz_97__string = "????"; - endcase - end - always @(*) begin - case(_zz_156_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_156__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_156__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_156__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_156__string = "JALR"; - default : _zz_156__string = "????"; + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; endcase end always @(*) begin - case(_zz_157_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_157__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_157__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_157__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_157__string = "PC "; - default : _zz_157__string = "???"; + case(_zz_92) + `Src1CtrlEnum_defaultEncoding_RS : _zz_92_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_92_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_92_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_92_string = "URS1 "; + default : _zz_92_string = "????????????"; endcase end always @(*) begin - case(_zz_158_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_158__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_158__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_158__string = "AND_1"; - default : _zz_158__string = "?????"; + case(_zz_93) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_93_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_93_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_93_string = "BITWISE "; + default : _zz_93_string = "????????"; endcase end always @(*) begin - case(_zz_159_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_159__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_159__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_159__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_159__string = "URS1 "; - default : _zz_159__string = "????????????"; + case(_zz_94) + `Src2CtrlEnum_defaultEncoding_RS : _zz_94_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_94_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_94_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_94_string = "PC "; + default : _zz_94_string = "???"; endcase end always @(*) begin - case(_zz_160_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_160__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_160__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_160__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_160__string = "SRA_1 "; - default : _zz_160__string = "?????????"; + case(_zz_95) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_95_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_95_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_95_string = "AND_1"; + default : _zz_95_string = "?????"; endcase end always @(*) begin - case(_zz_161_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_161__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_161__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_161__string = "BITWISE "; - default : _zz_161__string = "????????"; + case(_zz_96) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_96_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_96_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_96_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_96_string = "SRA_1 "; + default : _zz_96_string = "?????????"; endcase end always @(*) begin - case(_zz_162_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_162__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_162__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_162__string = "ECALL"; - default : _zz_162__string = "?????"; + case(_zz_97) + `BranchCtrlEnum_defaultEncoding_INC : _zz_97_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_97_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_97_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_97_string = "JALR"; + default : _zz_97_string = "????"; endcase end always @(*) begin - case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; - default : decode_to_execute_ENV_CTRL_string = "?????"; + case(_zz_98) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_98_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_98_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_98_string = "ECALL"; + default : _zz_98_string = "?????"; endcase end always @(*) begin - case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; - default : execute_to_memory_ENV_CTRL_string = "?????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; - default : memory_to_writeBack_ENV_CTRL_string = "?????"; + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin @@ -3360,15 +2341,6 @@ module VexRiscv ( default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end always @(*) begin case(decode_to_execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; @@ -3388,78 +2360,95 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_92_; - assign execute_BRANCH_CALC = _zz_38_; - assign memory_MUL_LOW = _zz_28_; - assign memory_PC = execute_to_memory_PC; - assign decode_SRC1_CTRL = _zz_1_; - assign _zz_2_ = _zz_3_; - assign decode_ALU_CTRL = _zz_4_; - assign _zz_5_ = _zz_6_; - assign decode_SRC2_FORCE_ZERO = _zz_56_; - assign _zz_7_ = _zz_8_; - assign decode_SHIFT_CTRL = _zz_9_; - assign _zz_10_ = _zz_11_; - assign execute_MUL_HL = _zz_30_; - assign _zz_12_ = _zz_13_; - assign decode_IS_CSR = _zz_68_; - assign decode_IS_DIV = _zz_83_; - assign decode_SRC_LESS_UNSIGNED = _zz_79_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_70_; - assign execute_MUL_LH = _zz_31_; - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_42_; + assign memory_MUL_LOW = ($signed(_zz_233) + $signed(_zz_241)); assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = _zz_29_; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_243; + assign execute_REGFILE_WRITE_DATA = _zz_100; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_173[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_245[0]; + assign decode_IS_RS1_SIGNED = _zz_246[0]; + assign decode_IS_DIV = _zz_247[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_248[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_249[0]; + assign _zz_8 = _zz_9; + assign _zz_10 = _zz_11; + assign decode_SHIFT_CTRL = _zz_12; + assign _zz_13 = _zz_14; + assign decode_ALU_BITWISE_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_SRC_LESS_UNSIGNED = _zz_250[0]; + assign decode_MEMORY_MANAGMENT = _zz_251[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_252[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_253[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_254[0]; + assign decode_SRC2_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_ALU_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_SRC1_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_100_; - assign execute_REGFILE_WRITE_DATA = _zz_58_; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_66_; - assign execute_BRANCH_DO = _zz_39_; - assign decode_ALU_BITWISE_CTRL = _zz_14_; - assign _zz_15_ = _zz_16_; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_78_; - assign execute_MUL_LL = _zz_32_; - assign decode_SRC2_CTRL = _zz_17_; - assign _zz_18_ = _zz_19_; - assign decode_DO_EBREAK = _zz_27_; - assign decode_MEMORY_MANAGMENT = _zz_76_; - assign decode_CSR_READ_OPCODE = _zz_35_; - assign decode_IS_RS2_SIGNED = _zz_88_; - assign memory_IS_MUL = execute_to_memory_IS_MUL; - assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_72_; - assign execute_SHIFT_RIGHT = _zz_46_; - assign decode_IS_RS1_SIGNED = _zz_81_; - assign _zz_20_ = _zz_21_; - assign _zz_22_ = _zz_23_; - assign decode_ENV_CTRL = _zz_24_; - assign _zz_25_ = _zz_26_; - assign decode_CSR_WRITE_OPCODE = _zz_36_; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_82_; + assign decode_IS_EBREAK = _zz_255[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -3473,22 +2462,22 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33_; - assign execute_ENV_CTRL = _zz_34_; - assign writeBack_ENV_CTRL = _zz_37_; + assign memory_ENV_CTRL = _zz_27; + assign execute_ENV_CTRL = _zz_28; + assign writeBack_ENV_CTRL = _zz_29; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_41_; - assign execute_BRANCH_CTRL = _zz_40_; - assign decode_RS2_USE = _zz_77_; - assign decode_RS1_USE = _zz_69_; + assign execute_BRANCH_COND_RESULT = _zz_117; + assign execute_BRANCH_CTRL = _zz_30; + assign decode_RS2_USE = _zz_256[0]; + assign decode_RS1_USE = _zz_257[0]; always @ (*) begin - _zz_43_ = execute_REGFILE_WRITE_DATA; - if(_zz_248_)begin - _zz_43_ = execute_CsrPlugin_readData; + _zz_31 = execute_REGFILE_WRITE_DATA; + if(_zz_194)begin + _zz_31 = execute_CsrPlugin_readData; end end @@ -3499,60 +2488,60 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - decode_RS2 = _zz_63_; - if(_zz_176_)begin - if((_zz_177_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_178_; + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_249_)begin - if(_zz_250_)begin - if(_zz_180_)begin - decode_RS2 = _zz_91_; + if(_zz_195)begin + if(_zz_196)begin + if(_zz_110)begin + decode_RS2 = _zz_50; end end end - if(_zz_251_)begin + if(_zz_197)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_182_)begin - decode_RS2 = _zz_44_; + if(_zz_112)begin + decode_RS2 = _zz_32; end end end - if(_zz_252_)begin + if(_zz_198)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_184_)begin - decode_RS2 = _zz_43_; + if(_zz_114)begin + decode_RS2 = _zz_31; end end end end always @ (*) begin - decode_RS1 = _zz_64_; - if(_zz_176_)begin - if((_zz_177_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_178_; + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_249_)begin - if(_zz_250_)begin - if(_zz_179_)begin - decode_RS1 = _zz_91_; + if(_zz_195)begin + if(_zz_196)begin + if(_zz_109)begin + decode_RS1 = _zz_50; end end end - if(_zz_251_)begin + if(_zz_197)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_181_)begin - decode_RS1 = _zz_44_; + if(_zz_111)begin + decode_RS1 = _zz_32; end end end - if(_zz_252_)begin + if(_zz_198)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_183_)begin - decode_RS1 = _zz_43_; + if(_zz_113)begin + decode_RS1 = _zz_31; end end end @@ -3560,71 +2549,70 @@ module VexRiscv ( assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_44_ = memory_REGFILE_WRITE_DATA; + _zz_32 = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_44_ = _zz_172_; + _zz_32 = _zz_108; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_44_ = memory_SHIFT_RIGHT; + _zz_32 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_253_)begin - _zz_44_ = memory_DivPlugin_div_result; + if(_zz_199)begin + _zz_32 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_45_; - assign execute_SHIFT_CTRL = _zz_47_; + assign memory_SHIFT_CTRL = _zz_33; + assign execute_SHIFT_CTRL = _zz_34; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_51_ = execute_PC; - assign execute_SRC2_CTRL = _zz_52_; - assign execute_SRC1_CTRL = _zz_54_; - assign decode_SRC_USE_SUB_LESS = _zz_87_; - assign decode_SRC_ADD_ZERO = _zz_67_; - assign execute_SRC_ADD_SUB = _zz_50_; - assign execute_SRC_LESS = _zz_48_; - assign execute_ALU_CTRL = _zz_57_; - assign execute_SRC2 = _zz_53_; - assign execute_SRC1 = _zz_55_; - assign execute_ALU_BITWISE_CTRL = _zz_59_; - assign _zz_60_ = writeBack_INSTRUCTION; - assign _zz_61_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_62_ = 1'b0; + assign _zz_35 = execute_PC; + assign execute_SRC2_CTRL = _zz_36; + assign execute_SRC1_CTRL = _zz_37; + assign decode_SRC_USE_SUB_LESS = _zz_258[0]; + assign decode_SRC_ADD_ZERO = _zz_259[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_38; + assign execute_SRC2 = _zz_106; + assign execute_SRC1 = _zz_101; + assign execute_ALU_BITWISE_CTRL = _zz_39; + assign _zz_40 = writeBack_INSTRUCTION; + assign _zz_41 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_42 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_62_ = 1'b1; + _zz_42 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_96_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_74_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_260[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_90_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_329) == 32'h00001073),{(_zz_330 == _zz_331),{_zz_332,{_zz_333,_zz_334}}}}}}} != 21'h0); always @ (*) begin - _zz_91_ = writeBack_REGFILE_WRITE_DATA; + _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_91_ = writeBack_DBusCachedPlugin_rspFormated; + _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_286_) + case(_zz_232) 2'b00 : begin - _zz_91_ = _zz_356_; + _zz_50 = _zz_302; end default : begin - _zz_91_ = _zz_357_; + _zz_50 = _zz_303; end endcase end @@ -3636,62 +2624,60 @@ module VexRiscv ( assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = _zz_49_; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_84_; - assign decode_FLUSH_ALL = _zz_89_; + assign decode_MEMORY_ENABLE = _zz_261[0]; + assign decode_FLUSH_ALL = _zz_262[0]; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_93_; - if(_zz_254_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_200)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin - _zz_93_ = _zz_94_; - if(_zz_255_)begin - _zz_93_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_201)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin - _zz_94_ = _zz_95_; - if(_zz_256_)begin - _zz_94_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_202)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_95_ = 1'b0; - if(_zz_257_)begin - _zz_95_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_203)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_97_; - assign decode_INSTRUCTION = _zz_101_; + assign decode_BRANCH_CTRL = _zz_51; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_98_ = memory_FORMAL_PC_NEXT; + _zz_52 = memory_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin - _zz_98_ = BranchPlugin_jumpInterface_payload; + _zz_52 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_99_ = decode_FORMAL_PC_NEXT; + _zz_53 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_99_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_99_ = IBusCachedPlugin_redoBranch_payload; + _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; end end - assign decode_PC = _zz_102_; + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -3699,18 +2685,10 @@ module VexRiscv ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_216_) - 3'b000 : begin - end - 3'b001 : begin - end + case(_zz_144) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end - 3'b011 : begin - end - 3'b100 : begin - end default : begin end endcase @@ -3718,20 +2696,20 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_173_ || _zz_174_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_258_)begin + if(_zz_204)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3742,23 +2720,20 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_258_)begin + if(_zz_204)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if((_zz_243_ && (! dataCache_1__io_cpu_flush_ready)))begin - execute_arbitration_haltItself = 1'b1; - end - if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + if(((_zz_189 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_248_)begin + if(_zz_194)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3767,7 +2742,10 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_259_)begin + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_205)begin execute_arbitration_haltByOther = 1'b1; end end @@ -3784,8 +2762,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_259_)begin - if(_zz_260_)begin + if(_zz_205)begin + if(_zz_206)begin execute_arbitration_flushIt = 1'b1; end end @@ -3796,8 +2774,8 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_259_)begin - if(_zz_260_)begin + if(_zz_205)begin + if(_zz_206)begin execute_arbitration_flushNext = 1'b1; end end @@ -3805,8 +2783,8 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_253_)begin - if(_zz_261_)begin + if(_zz_199)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end end @@ -3836,7 +2814,7 @@ module VexRiscv ( always @ (*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1__io_cpu_writeBack_haltIt)begin + if(dataCache_1_io_cpu_writeBack_haltIt)begin writeBack_arbitration_haltItself = 1'b1; end end @@ -3867,10 +2845,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_262_)begin + if(_zz_207)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_263_)begin + if(_zz_208)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3881,74 +2859,67 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_262_)begin + if(_zz_207)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_263_)begin + if(_zz_208)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_259_)begin - if(_zz_260_)begin + if(_zz_205)begin + if(_zz_206)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_264_)begin + if(_zz_209)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if(_zz_259_)begin - if(_zz_260_)begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; end end always @ (*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin - IBusCachedPlugin_incomingInstruction = 1'b1; + _zz_54 = 1'b0; + if(DebugPlugin_godmode)begin + _zz_54 = 1'b1; end end + assign CsrPlugin_inWfi = 1'b0; always @ (*) begin - _zz_103_ = 1'b0; - if(DebugPlugin_godmode)begin - _zz_103_ = 1'b1; + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_262_)begin + if(_zz_207)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_263_)begin + if(_zz_208)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_262_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_207)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_263_)begin - case(_zz_265_) + if(_zz_208)begin + case(_zz_210) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3979,21 +2950,25 @@ module VexRiscv ( end end - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); - assign _zz_104_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_105_ = (_zz_104_ & (~ _zz_287_)); - assign _zz_106_ = _zz_105_[3]; - assign _zz_107_ = _zz_105_[4]; - assign _zz_108_ = (_zz_105_[1] || _zz_106_); - assign _zz_109_ = (_zz_105_[2] || _zz_106_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247_; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_55 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_56 = (_zz_55 & (~ _zz_263)); + assign _zz_57 = _zz_56[3]; + assign _zz_58 = (_zz_56[1] || _zz_57); + assign _zz_59 = (_zz_56[2] || _zz_57); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_193; always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin @@ -4002,7 +2977,10 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_289_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_265); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end @@ -4010,12 +2988,28 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin @@ -4023,41 +3017,44 @@ module VexRiscv ( end end - assign _zz_110_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_110_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_110_); + assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_60); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + if(IBusCachedPlugin_mmuBus_busy)begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_111_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_111_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_111_); + assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_61); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_112_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_112_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_112_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_113_; - assign _zz_113_ = ((1'b0 && (! _zz_114_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_114_ = _zz_115_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_114_; + assign _zz_62 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_62); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_62); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_63; + assign _zz_63 = ((1'b0 && (! _zz_64)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_64 = _zz_65; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_64; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_116_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_116_ = _zz_117_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_116_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_118_; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_66)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_66 = _zz_67; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_66; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_68; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -4069,149 +3066,140 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin - decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - case(_zz_216_) - 3'b000 : begin - end - 3'b001 : begin - end + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_144) 3'b010 : begin decode_arbitration_isValid = 1'b1; end 3'b011 : begin decode_arbitration_isValid = 1'b1; end - 3'b100 : begin - end default : begin end endcase end - assign _zz_102_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - assign _zz_101_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - assign _zz_100_ = (decode_PC + (32'b00000000000000000000000000000100)); - assign _zz_119_ = _zz_290_[11]; - always @ (*) begin - _zz_120_[18] = _zz_119_; - _zz_120_[17] = _zz_119_; - _zz_120_[16] = _zz_119_; - _zz_120_[15] = _zz_119_; - _zz_120_[14] = _zz_119_; - _zz_120_[13] = _zz_119_; - _zz_120_[12] = _zz_119_; - _zz_120_[11] = _zz_119_; - _zz_120_[10] = _zz_119_; - _zz_120_[9] = _zz_119_; - _zz_120_[8] = _zz_119_; - _zz_120_[7] = _zz_119_; - _zz_120_[6] = _zz_119_; - _zz_120_[5] = _zz_119_; - _zz_120_[4] = _zz_119_; - _zz_120_[3] = _zz_119_; - _zz_120_[2] = _zz_119_; - _zz_120_[1] = _zz_119_; - _zz_120_[0] = _zz_119_; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_291_[31])); - if(_zz_125_)begin + assign _zz_69 = _zz_266[11]; + always @ (*) begin + _zz_70[18] = _zz_69; + _zz_70[17] = _zz_69; + _zz_70[16] = _zz_69; + _zz_70[15] = _zz_69; + _zz_70[14] = _zz_69; + _zz_70[13] = _zz_69; + _zz_70[12] = _zz_69; + _zz_70[11] = _zz_69; + _zz_70[10] = _zz_69; + _zz_70[9] = _zz_69; + _zz_70[8] = _zz_69; + _zz_70[7] = _zz_69; + _zz_70[6] = _zz_69; + _zz_70[5] = _zz_69; + _zz_70[4] = _zz_69; + _zz_70[3] = _zz_69; + _zz_70[2] = _zz_69; + _zz_70[1] = _zz_69; + _zz_70[0] = _zz_69; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_267[31])); + if(_zz_75)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_121_ = _zz_292_[19]; + assign _zz_71 = _zz_268[19]; always @ (*) begin - _zz_122_[10] = _zz_121_; - _zz_122_[9] = _zz_121_; - _zz_122_[8] = _zz_121_; - _zz_122_[7] = _zz_121_; - _zz_122_[6] = _zz_121_; - _zz_122_[5] = _zz_121_; - _zz_122_[4] = _zz_121_; - _zz_122_[3] = _zz_121_; - _zz_122_[2] = _zz_121_; - _zz_122_[1] = _zz_121_; - _zz_122_[0] = _zz_121_; + _zz_72[10] = _zz_71; + _zz_72[9] = _zz_71; + _zz_72[8] = _zz_71; + _zz_72[7] = _zz_71; + _zz_72[6] = _zz_71; + _zz_72[5] = _zz_71; + _zz_72[4] = _zz_71; + _zz_72[3] = _zz_71; + _zz_72[2] = _zz_71; + _zz_72[1] = _zz_71; + _zz_72[0] = _zz_71; end - assign _zz_123_ = _zz_293_[11]; + assign _zz_73 = _zz_269[11]; always @ (*) begin - _zz_124_[18] = _zz_123_; - _zz_124_[17] = _zz_123_; - _zz_124_[16] = _zz_123_; - _zz_124_[15] = _zz_123_; - _zz_124_[14] = _zz_123_; - _zz_124_[13] = _zz_123_; - _zz_124_[12] = _zz_123_; - _zz_124_[11] = _zz_123_; - _zz_124_[10] = _zz_123_; - _zz_124_[9] = _zz_123_; - _zz_124_[8] = _zz_123_; - _zz_124_[7] = _zz_123_; - _zz_124_[6] = _zz_123_; - _zz_124_[5] = _zz_123_; - _zz_124_[4] = _zz_123_; - _zz_124_[3] = _zz_123_; - _zz_124_[2] = _zz_123_; - _zz_124_[1] = _zz_123_; - _zz_124_[0] = _zz_123_; + _zz_74[18] = _zz_73; + _zz_74[17] = _zz_73; + _zz_74[16] = _zz_73; + _zz_74[15] = _zz_73; + _zz_74[14] = _zz_73; + _zz_74[13] = _zz_73; + _zz_74[12] = _zz_73; + _zz_74[11] = _zz_73; + _zz_74[10] = _zz_73; + _zz_74[9] = _zz_73; + _zz_74[8] = _zz_73; + _zz_74[7] = _zz_73; + _zz_74[6] = _zz_73; + _zz_74[5] = _zz_73; + _zz_74[4] = _zz_73; + _zz_74[3] = _zz_73; + _zz_74[2] = _zz_73; + _zz_74[1] = _zz_73; + _zz_74[0] = _zz_73; end always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_125_ = _zz_294_[1]; + _zz_75 = _zz_270[1]; end default : begin - _zz_125_ = _zz_295_[1]; + _zz_75 = _zz_271[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_126_ = _zz_296_[19]; - always @ (*) begin - _zz_127_[10] = _zz_126_; - _zz_127_[9] = _zz_126_; - _zz_127_[8] = _zz_126_; - _zz_127_[7] = _zz_126_; - _zz_127_[6] = _zz_126_; - _zz_127_[5] = _zz_126_; - _zz_127_[4] = _zz_126_; - _zz_127_[3] = _zz_126_; - _zz_127_[2] = _zz_126_; - _zz_127_[1] = _zz_126_; - _zz_127_[0] = _zz_126_; - end - - assign _zz_128_ = _zz_297_[11]; - always @ (*) begin - _zz_129_[18] = _zz_128_; - _zz_129_[17] = _zz_128_; - _zz_129_[16] = _zz_128_; - _zz_129_[15] = _zz_128_; - _zz_129_[14] = _zz_128_; - _zz_129_[13] = _zz_128_; - _zz_129_[12] = _zz_128_; - _zz_129_[11] = _zz_128_; - _zz_129_[10] = _zz_128_; - _zz_129_[9] = _zz_128_; - _zz_129_[8] = _zz_128_; - _zz_129_[7] = _zz_128_; - _zz_129_[6] = _zz_128_; - _zz_129_[5] = _zz_128_; - _zz_129_[4] = _zz_128_; - _zz_129_[3] = _zz_128_; - _zz_129_[2] = _zz_128_; - _zz_129_[1] = _zz_128_; - _zz_129_[0] = _zz_128_; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_127_,{{{_zz_383_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_129_,{{{_zz_384_,_zz_385_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_76 = _zz_272[19]; + always @ (*) begin + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7] = _zz_76; + _zz_77[6] = _zz_76; + _zz_77[5] = _zz_76; + _zz_77[4] = _zz_76; + _zz_77[3] = _zz_76; + _zz_77[2] = _zz_76; + _zz_77[1] = _zz_76; + _zz_77[0] = _zz_76; + end + + assign _zz_78 = _zz_273[11]; + always @ (*) begin + _zz_79[18] = _zz_78; + _zz_79[17] = _zz_78; + _zz_79[16] = _zz_78; + _zz_79[15] = _zz_78; + _zz_79[14] = _zz_78; + _zz_79[13] = _zz_78; + _zz_79[12] = _zz_78; + _zz_79[11] = _zz_78; + _zz_79[10] = _zz_78; + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7] = _zz_78; + _zz_79[6] = _zz_78; + _zz_79[5] = _zz_78; + _zz_79[4] = _zz_78; + _zz_79[3] = _zz_78; + _zz_79[2] = _zz_78; + _zz_79[1] = _zz_78; + _zz_79[0] = _zz_78; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_77,{{{_zz_347,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_79,{{{_zz_348,_zz_349},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -4220,133 +3208,128 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_227_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_230_ = (32'b00000000000000000000000000000000); - assign _zz_228_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_229_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_231_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_232_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_233_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_96_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign _zz_164 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_165 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_166 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_165; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_168 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_169 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_170 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_257_)begin + if(_zz_203)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_255_)begin + if(_zz_201)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_266_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - end end always @ (*) begin - _zz_234_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_255_)begin - _zz_234_ = 1'b1; - end - if(_zz_266_)begin - _zz_234_ = 1'b0; + _zz_171 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_201)begin + _zz_171 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_256_)begin + if(_zz_202)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_254_)begin + if(_zz_200)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_256_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); - end - if(_zz_254_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_226_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_131_); - assign _zz_244_ = (! _zz_131_); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_131_ ? _zz_132_ : dataCache_1__io_mem_cmd_payload_wr); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_131_ ? _zz_133_ : dataCache_1__io_mem_cmd_payload_address); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_131_ ? _zz_134_ : dataCache_1__io_mem_cmd_payload_data); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_131_ ? _zz_135_ : dataCache_1__io_mem_cmd_payload_mask); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_131_ ? _zz_136_ : dataCache_1__io_mem_cmd_payload_length); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_131_ ? _zz_137_ : dataCache_1__io_mem_cmd_payload_last); - assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_138_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_139_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_140_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_141_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_142_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_143_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_144_; - assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_202)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_200)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_163 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_190 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_235_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_236_ = execute_SRC_ADD; + assign _zz_172 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_173 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_146_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_82 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_146_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_82 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_146_ = execute_RS2[31 : 0]; + _zz_82 = execute_RS2[31 : 0]; end endcase end - assign _zz_243_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_92_ = _zz_236_[1 : 0]; - assign _zz_237_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_238_ = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + assign _zz_189 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_174 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_175 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_174; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_175; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_239_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_103_ && (! dataCache_1__io_cpu_memory_isWrite)))begin - _zz_239_ = 1'b1; + _zz_176 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_54 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_176 = 1'b1; end end - assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; - assign _zz_240_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_241_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_242_ = writeBack_REGFILE_WRITE_DATA; + assign _zz_177 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_178 = (CsrPlugin_privilege == 2'b00); + assign _zz_179 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_267_)begin - if(dataCache_1__io_cpu_redo)begin + if(_zz_211)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end @@ -4355,17 +3338,17 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_267_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin + if(_zz_211)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_redo)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end @@ -4373,94 +3356,94 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); - if(_zz_267_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_298_}; + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_211)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_274}; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_299_}; + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1__io_cpu_writeBack_mmuException)begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_275}; end end end always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; end 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; end 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; end default : begin end endcase end - assign _zz_147_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_148_[31] = _zz_147_; - _zz_148_[30] = _zz_147_; - _zz_148_[29] = _zz_147_; - _zz_148_[28] = _zz_147_; - _zz_148_[27] = _zz_147_; - _zz_148_[26] = _zz_147_; - _zz_148_[25] = _zz_147_; - _zz_148_[24] = _zz_147_; - _zz_148_[23] = _zz_147_; - _zz_148_[22] = _zz_147_; - _zz_148_[21] = _zz_147_; - _zz_148_[20] = _zz_147_; - _zz_148_[19] = _zz_147_; - _zz_148_[18] = _zz_147_; - _zz_148_[17] = _zz_147_; - _zz_148_[16] = _zz_147_; - _zz_148_[15] = _zz_147_; - _zz_148_[14] = _zz_147_; - _zz_148_[13] = _zz_147_; - _zz_148_[12] = _zz_147_; - _zz_148_[11] = _zz_147_; - _zz_148_[10] = _zz_147_; - _zz_148_[9] = _zz_147_; - _zz_148_[8] = _zz_147_; - _zz_148_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_149_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_150_[31] = _zz_149_; - _zz_150_[30] = _zz_149_; - _zz_150_[29] = _zz_149_; - _zz_150_[28] = _zz_149_; - _zz_150_[27] = _zz_149_; - _zz_150_[26] = _zz_149_; - _zz_150_[25] = _zz_149_; - _zz_150_[24] = _zz_149_; - _zz_150_[23] = _zz_149_; - _zz_150_[22] = _zz_149_; - _zz_150_[21] = _zz_149_; - _zz_150_[20] = _zz_149_; - _zz_150_[19] = _zz_149_; - _zz_150_[18] = _zz_149_; - _zz_150_[17] = _zz_149_; - _zz_150_[16] = _zz_149_; - _zz_150_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_284_) + assign _zz_83 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_84[31] = _zz_83; + _zz_84[30] = _zz_83; + _zz_84[29] = _zz_83; + _zz_84[28] = _zz_83; + _zz_84[27] = _zz_83; + _zz_84[26] = _zz_83; + _zz_84[25] = _zz_83; + _zz_84[24] = _zz_83; + _zz_84[23] = _zz_83; + _zz_84[22] = _zz_83; + _zz_84[21] = _zz_83; + _zz_84[20] = _zz_83; + _zz_84[19] = _zz_83; + _zz_84[18] = _zz_83; + _zz_84[17] = _zz_83; + _zz_84[16] = _zz_83; + _zz_84[15] = _zz_83; + _zz_84[14] = _zz_83; + _zz_84[13] = _zz_83; + _zz_84[12] = _zz_83; + _zz_84[11] = _zz_83; + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_85 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_86[31] = _zz_85; + _zz_86[30] = _zz_85; + _zz_86[29] = _zz_85; + _zz_86[28] = _zz_85; + _zz_86[27] = _zz_85; + _zz_86[26] = _zz_85; + _zz_86[25] = _zz_85; + _zz_86[24] = _zz_85; + _zz_86[23] = _zz_85; + _zz_86[22] = _zz_85; + _zz_86[21] = _zz_85; + _zz_86[20] = _zz_85; + _zz_86[19] = _zz_85; + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_230) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_148_; + writeBack_DBusCachedPlugin_rspFormated = _zz_84; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_150_; + writeBack_DBusCachedPlugin_rspFormated = _zz_86; end default : begin writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; @@ -4468,78 +3451,71 @@ module VexRiscv ( endcase end - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_152_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); - assign _zz_153_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_154_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_155_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_151_ = {(((decode_INSTRUCTION & _zz_386_) == (32'b00000000000000000000000001010000)) != (1'b0)),{((_zz_387_ == _zz_388_) != (1'b0)),{(_zz_389_ != (1'b0)),{(_zz_390_ != _zz_391_),{_zz_392_,{_zz_393_,_zz_394_}}}}}}; - assign _zz_90_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_556_) == (32'b00000000000000000001000001110011)),{(_zz_557_ == _zz_558_),{_zz_559_,{_zz_560_,_zz_561_}}}}}}} != (21'b000000000000000000000)); - assign _zz_89_ = _zz_300_[0]; - assign _zz_88_ = _zz_301_[0]; - assign _zz_87_ = _zz_302_[0]; - assign _zz_156_ = _zz_151_[4 : 3]; - assign _zz_86_ = _zz_156_; - assign _zz_157_ = _zz_151_[6 : 5]; - assign _zz_85_ = _zz_157_; - assign _zz_84_ = _zz_303_[0]; - assign _zz_83_ = _zz_304_[0]; - assign _zz_82_ = _zz_305_[0]; - assign _zz_81_ = _zz_306_[0]; - assign _zz_158_ = _zz_151_[12 : 11]; - assign _zz_80_ = _zz_158_; - assign _zz_79_ = _zz_307_[0]; - assign _zz_78_ = _zz_308_[0]; - assign _zz_77_ = _zz_309_[0]; - assign _zz_76_ = _zz_310_[0]; - assign _zz_159_ = _zz_151_[18 : 17]; - assign _zz_75_ = _zz_159_; - assign _zz_74_ = _zz_311_[0]; - assign _zz_160_ = _zz_151_[21 : 20]; - assign _zz_73_ = _zz_160_; - assign _zz_72_ = _zz_312_[0]; - assign _zz_161_ = _zz_151_[25 : 24]; - assign _zz_71_ = _zz_161_; - assign _zz_70_ = _zz_313_[0]; - assign _zz_69_ = _zz_314_[0]; - assign _zz_68_ = _zz_315_[0]; - assign _zz_67_ = _zz_316_[0]; - assign _zz_66_ = _zz_317_[0]; - assign _zz_162_ = _zz_151_[32 : 31]; - assign _zz_65_ = _zz_162_; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign _zz_88 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_89 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_90 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_91 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_87 = {(((decode_INSTRUCTION & _zz_350) == 32'h00100050) != 1'b0),{(_zz_91 != 1'b0),{(_zz_91 != 1'b0),{(_zz_351 != _zz_352),{_zz_353,{_zz_354,_zz_355}}}}}}; + assign _zz_92 = _zz_87[2 : 1]; + assign _zz_49 = _zz_92; + assign _zz_93 = _zz_87[7 : 6]; + assign _zz_48 = _zz_93; + assign _zz_94 = _zz_87[9 : 8]; + assign _zz_47 = _zz_94; + assign _zz_95 = _zz_87[19 : 18]; + assign _zz_46 = _zz_95; + assign _zz_96 = _zz_87[22 : 21]; + assign _zz_45 = _zz_96; + assign _zz_97 = _zz_87[24 : 23]; + assign _zz_44 = _zz_97; + assign _zz_98 = _zz_87[27 : 26]; + assign _zz_43 = _zz_98; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_245_; - assign decode_RegFilePlugin_rs2Data = _zz_246_; - assign _zz_64_ = decode_RegFilePlugin_rs1Data; - assign _zz_63_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_191; + assign decode_RegFilePlugin_rs2Data = _zz_192; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_61_ && writeBack_arbitration_isFiring); - if(_zz_163_)begin + lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); + if(_zz_99)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_60_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_91_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; + if(_zz_99)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_50; + if(_zz_99)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -4557,361 +3533,354 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_164_ = execute_IntAluPlugin_bitwise; + _zz_100 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_164_ = {31'd0, _zz_318_}; + _zz_100 = {31'd0, _zz_276}; end default : begin - _zz_164_ = execute_SRC_ADD_SUB; + _zz_100 = execute_SRC_ADD_SUB; end endcase end - assign _zz_58_ = _zz_164_; - assign _zz_56_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_165_ = execute_RS1; + _zz_101 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_165_ = {29'd0, _zz_319_}; + _zz_101 = {29'd0, _zz_277}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_165_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_101 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_165_ = {27'd0, _zz_320_}; + _zz_101 = {27'd0, _zz_278}; end endcase end - assign _zz_55_ = _zz_165_; - assign _zz_166_ = _zz_321_[11]; - always @ (*) begin - _zz_167_[19] = _zz_166_; - _zz_167_[18] = _zz_166_; - _zz_167_[17] = _zz_166_; - _zz_167_[16] = _zz_166_; - _zz_167_[15] = _zz_166_; - _zz_167_[14] = _zz_166_; - _zz_167_[13] = _zz_166_; - _zz_167_[12] = _zz_166_; - _zz_167_[11] = _zz_166_; - _zz_167_[10] = _zz_166_; - _zz_167_[9] = _zz_166_; - _zz_167_[8] = _zz_166_; - _zz_167_[7] = _zz_166_; - _zz_167_[6] = _zz_166_; - _zz_167_[5] = _zz_166_; - _zz_167_[4] = _zz_166_; - _zz_167_[3] = _zz_166_; - _zz_167_[2] = _zz_166_; - _zz_167_[1] = _zz_166_; - _zz_167_[0] = _zz_166_; - end - - assign _zz_168_ = _zz_322_[11]; - always @ (*) begin - _zz_169_[19] = _zz_168_; - _zz_169_[18] = _zz_168_; - _zz_169_[17] = _zz_168_; - _zz_169_[16] = _zz_168_; - _zz_169_[15] = _zz_168_; - _zz_169_[14] = _zz_168_; - _zz_169_[13] = _zz_168_; - _zz_169_[12] = _zz_168_; - _zz_169_[11] = _zz_168_; - _zz_169_[10] = _zz_168_; - _zz_169_[9] = _zz_168_; - _zz_169_[8] = _zz_168_; - _zz_169_[7] = _zz_168_; - _zz_169_[6] = _zz_168_; - _zz_169_[5] = _zz_168_; - _zz_169_[4] = _zz_168_; - _zz_169_[3] = _zz_168_; - _zz_169_[2] = _zz_168_; - _zz_169_[1] = _zz_168_; - _zz_169_[0] = _zz_168_; + assign _zz_102 = _zz_279[11]; + always @ (*) begin + _zz_103[19] = _zz_102; + _zz_103[18] = _zz_102; + _zz_103[17] = _zz_102; + _zz_103[16] = _zz_102; + _zz_103[15] = _zz_102; + _zz_103[14] = _zz_102; + _zz_103[13] = _zz_102; + _zz_103[12] = _zz_102; + _zz_103[11] = _zz_102; + _zz_103[10] = _zz_102; + _zz_103[9] = _zz_102; + _zz_103[8] = _zz_102; + _zz_103[7] = _zz_102; + _zz_103[6] = _zz_102; + _zz_103[5] = _zz_102; + _zz_103[4] = _zz_102; + _zz_103[3] = _zz_102; + _zz_103[2] = _zz_102; + _zz_103[1] = _zz_102; + _zz_103[0] = _zz_102; + end + + assign _zz_104 = _zz_280[11]; + always @ (*) begin + _zz_105[19] = _zz_104; + _zz_105[18] = _zz_104; + _zz_105[17] = _zz_104; + _zz_105[16] = _zz_104; + _zz_105[15] = _zz_104; + _zz_105[14] = _zz_104; + _zz_105[13] = _zz_104; + _zz_105[12] = _zz_104; + _zz_105[11] = _zz_104; + _zz_105[10] = _zz_104; + _zz_105[9] = _zz_104; + _zz_105[8] = _zz_104; + _zz_105[7] = _zz_104; + _zz_105[6] = _zz_104; + _zz_105[5] = _zz_104; + _zz_105[4] = _zz_104; + _zz_105[3] = _zz_104; + _zz_105[2] = _zz_104; + _zz_105[1] = _zz_104; + _zz_105[0] = _zz_104; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_170_ = execute_RS2; + _zz_106 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_170_ = {_zz_167_,execute_INSTRUCTION[31 : 20]}; + _zz_106 = {_zz_103,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_170_ = {_zz_169_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_106 = {_zz_105,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_170_ = _zz_51_; + _zz_106 = _zz_35; end endcase end - assign _zz_53_ = _zz_170_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_323_; + execute_SrcPlugin_addSub = _zz_281; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_50_ = execute_SrcPlugin_addSub; - assign _zz_49_ = execute_SrcPlugin_addSub; - assign _zz_48_ = execute_SrcPlugin_less; assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_171_[0] = execute_SRC1[31]; - _zz_171_[1] = execute_SRC1[30]; - _zz_171_[2] = execute_SRC1[29]; - _zz_171_[3] = execute_SRC1[28]; - _zz_171_[4] = execute_SRC1[27]; - _zz_171_[5] = execute_SRC1[26]; - _zz_171_[6] = execute_SRC1[25]; - _zz_171_[7] = execute_SRC1[24]; - _zz_171_[8] = execute_SRC1[23]; - _zz_171_[9] = execute_SRC1[22]; - _zz_171_[10] = execute_SRC1[21]; - _zz_171_[11] = execute_SRC1[20]; - _zz_171_[12] = execute_SRC1[19]; - _zz_171_[13] = execute_SRC1[18]; - _zz_171_[14] = execute_SRC1[17]; - _zz_171_[15] = execute_SRC1[16]; - _zz_171_[16] = execute_SRC1[15]; - _zz_171_[17] = execute_SRC1[14]; - _zz_171_[18] = execute_SRC1[13]; - _zz_171_[19] = execute_SRC1[12]; - _zz_171_[20] = execute_SRC1[11]; - _zz_171_[21] = execute_SRC1[10]; - _zz_171_[22] = execute_SRC1[9]; - _zz_171_[23] = execute_SRC1[8]; - _zz_171_[24] = execute_SRC1[7]; - _zz_171_[25] = execute_SRC1[6]; - _zz_171_[26] = execute_SRC1[5]; - _zz_171_[27] = execute_SRC1[4]; - _zz_171_[28] = execute_SRC1[3]; - _zz_171_[29] = execute_SRC1[2]; - _zz_171_[30] = execute_SRC1[1]; - _zz_171_[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_171_ : execute_SRC1); - assign _zz_46_ = _zz_331_; - always @ (*) begin - _zz_172_[0] = memory_SHIFT_RIGHT[31]; - _zz_172_[1] = memory_SHIFT_RIGHT[30]; - _zz_172_[2] = memory_SHIFT_RIGHT[29]; - _zz_172_[3] = memory_SHIFT_RIGHT[28]; - _zz_172_[4] = memory_SHIFT_RIGHT[27]; - _zz_172_[5] = memory_SHIFT_RIGHT[26]; - _zz_172_[6] = memory_SHIFT_RIGHT[25]; - _zz_172_[7] = memory_SHIFT_RIGHT[24]; - _zz_172_[8] = memory_SHIFT_RIGHT[23]; - _zz_172_[9] = memory_SHIFT_RIGHT[22]; - _zz_172_[10] = memory_SHIFT_RIGHT[21]; - _zz_172_[11] = memory_SHIFT_RIGHT[20]; - _zz_172_[12] = memory_SHIFT_RIGHT[19]; - _zz_172_[13] = memory_SHIFT_RIGHT[18]; - _zz_172_[14] = memory_SHIFT_RIGHT[17]; - _zz_172_[15] = memory_SHIFT_RIGHT[16]; - _zz_172_[16] = memory_SHIFT_RIGHT[15]; - _zz_172_[17] = memory_SHIFT_RIGHT[14]; - _zz_172_[18] = memory_SHIFT_RIGHT[13]; - _zz_172_[19] = memory_SHIFT_RIGHT[12]; - _zz_172_[20] = memory_SHIFT_RIGHT[11]; - _zz_172_[21] = memory_SHIFT_RIGHT[10]; - _zz_172_[22] = memory_SHIFT_RIGHT[9]; - _zz_172_[23] = memory_SHIFT_RIGHT[8]; - _zz_172_[24] = memory_SHIFT_RIGHT[7]; - _zz_172_[25] = memory_SHIFT_RIGHT[6]; - _zz_172_[26] = memory_SHIFT_RIGHT[5]; - _zz_172_[27] = memory_SHIFT_RIGHT[4]; - _zz_172_[28] = memory_SHIFT_RIGHT[3]; - _zz_172_[29] = memory_SHIFT_RIGHT[2]; - _zz_172_[30] = memory_SHIFT_RIGHT[1]; - _zz_172_[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_173_ = 1'b0; - if(_zz_268_)begin - if(_zz_269_)begin - if(_zz_179_)begin - _zz_173_ = 1'b1; + _zz_107[0] = execute_SRC1[31]; + _zz_107[1] = execute_SRC1[30]; + _zz_107[2] = execute_SRC1[29]; + _zz_107[3] = execute_SRC1[28]; + _zz_107[4] = execute_SRC1[27]; + _zz_107[5] = execute_SRC1[26]; + _zz_107[6] = execute_SRC1[25]; + _zz_107[7] = execute_SRC1[24]; + _zz_107[8] = execute_SRC1[23]; + _zz_107[9] = execute_SRC1[22]; + _zz_107[10] = execute_SRC1[21]; + _zz_107[11] = execute_SRC1[20]; + _zz_107[12] = execute_SRC1[19]; + _zz_107[13] = execute_SRC1[18]; + _zz_107[14] = execute_SRC1[17]; + _zz_107[15] = execute_SRC1[16]; + _zz_107[16] = execute_SRC1[15]; + _zz_107[17] = execute_SRC1[14]; + _zz_107[18] = execute_SRC1[13]; + _zz_107[19] = execute_SRC1[12]; + _zz_107[20] = execute_SRC1[11]; + _zz_107[21] = execute_SRC1[10]; + _zz_107[22] = execute_SRC1[9]; + _zz_107[23] = execute_SRC1[8]; + _zz_107[24] = execute_SRC1[7]; + _zz_107[25] = execute_SRC1[6]; + _zz_107[26] = execute_SRC1[5]; + _zz_107[27] = execute_SRC1[4]; + _zz_107[28] = execute_SRC1[3]; + _zz_107[29] = execute_SRC1[2]; + _zz_107[30] = execute_SRC1[1]; + _zz_107[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_107 : execute_SRC1); + always @ (*) begin + _zz_108[0] = memory_SHIFT_RIGHT[31]; + _zz_108[1] = memory_SHIFT_RIGHT[30]; + _zz_108[2] = memory_SHIFT_RIGHT[29]; + _zz_108[3] = memory_SHIFT_RIGHT[28]; + _zz_108[4] = memory_SHIFT_RIGHT[27]; + _zz_108[5] = memory_SHIFT_RIGHT[26]; + _zz_108[6] = memory_SHIFT_RIGHT[25]; + _zz_108[7] = memory_SHIFT_RIGHT[24]; + _zz_108[8] = memory_SHIFT_RIGHT[23]; + _zz_108[9] = memory_SHIFT_RIGHT[22]; + _zz_108[10] = memory_SHIFT_RIGHT[21]; + _zz_108[11] = memory_SHIFT_RIGHT[20]; + _zz_108[12] = memory_SHIFT_RIGHT[19]; + _zz_108[13] = memory_SHIFT_RIGHT[18]; + _zz_108[14] = memory_SHIFT_RIGHT[17]; + _zz_108[15] = memory_SHIFT_RIGHT[16]; + _zz_108[16] = memory_SHIFT_RIGHT[15]; + _zz_108[17] = memory_SHIFT_RIGHT[14]; + _zz_108[18] = memory_SHIFT_RIGHT[13]; + _zz_108[19] = memory_SHIFT_RIGHT[12]; + _zz_108[20] = memory_SHIFT_RIGHT[11]; + _zz_108[21] = memory_SHIFT_RIGHT[10]; + _zz_108[22] = memory_SHIFT_RIGHT[9]; + _zz_108[23] = memory_SHIFT_RIGHT[8]; + _zz_108[24] = memory_SHIFT_RIGHT[7]; + _zz_108[25] = memory_SHIFT_RIGHT[6]; + _zz_108[26] = memory_SHIFT_RIGHT[5]; + _zz_108[27] = memory_SHIFT_RIGHT[4]; + _zz_108[28] = memory_SHIFT_RIGHT[3]; + _zz_108[29] = memory_SHIFT_RIGHT[2]; + _zz_108[30] = memory_SHIFT_RIGHT[1]; + _zz_108[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_212)begin + if(_zz_213)begin + if(_zz_109)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_270_)begin - if(_zz_271_)begin - if(_zz_181_)begin - _zz_173_ = 1'b1; + if(_zz_214)begin + if(_zz_215)begin + if(_zz_111)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_272_)begin - if(_zz_273_)begin - if(_zz_183_)begin - _zz_173_ = 1'b1; + if(_zz_216)begin + if(_zz_217)begin + if(_zz_113)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_173_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_174_ = 1'b0; - if(_zz_268_)begin - if(_zz_269_)begin - if(_zz_180_)begin - _zz_174_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_212)begin + if(_zz_213)begin + if(_zz_110)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_270_)begin - if(_zz_271_)begin - if(_zz_182_)begin - _zz_174_ = 1'b1; + if(_zz_214)begin + if(_zz_215)begin + if(_zz_112)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_272_)begin - if(_zz_273_)begin - if(_zz_184_)begin - _zz_174_ = 1'b1; + if(_zz_216)begin + if(_zz_217)begin + if(_zz_114)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_174_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_175_ = (_zz_61_ && writeBack_arbitration_isFiring); - assign _zz_179_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_180_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_181_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_182_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_183_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_184_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_42_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_109 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_110 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_111 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_112 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_113 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_114 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_185_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_185_ == (3'b000))) begin - _zz_186_ = execute_BranchPlugin_eq; - end else if((_zz_185_ == (3'b001))) begin - _zz_186_ = (! execute_BranchPlugin_eq); - end else if((((_zz_185_ & (3'b101)) == (3'b101)))) begin - _zz_186_ = (! execute_SRC_LESS); + assign _zz_115 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_115 == 3'b000)) begin + _zz_116 = execute_BranchPlugin_eq; + end else if((_zz_115 == 3'b001)) begin + _zz_116 = (! execute_BranchPlugin_eq); + end else if((((_zz_115 & 3'b101) == 3'b101))) begin + _zz_116 = (! execute_SRC_LESS); end else begin - _zz_186_ = execute_SRC_LESS; + _zz_116 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_187_ = 1'b0; + _zz_117 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_187_ = 1'b1; + _zz_117 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_187_ = 1'b1; + _zz_117 = 1'b1; end default : begin - _zz_187_ = _zz_186_; + _zz_117 = _zz_116; end endcase end - assign _zz_41_ = _zz_187_; - assign _zz_188_ = _zz_333_[11]; - always @ (*) begin - _zz_189_[19] = _zz_188_; - _zz_189_[18] = _zz_188_; - _zz_189_[17] = _zz_188_; - _zz_189_[16] = _zz_188_; - _zz_189_[15] = _zz_188_; - _zz_189_[14] = _zz_188_; - _zz_189_[13] = _zz_188_; - _zz_189_[12] = _zz_188_; - _zz_189_[11] = _zz_188_; - _zz_189_[10] = _zz_188_; - _zz_189_[9] = _zz_188_; - _zz_189_[8] = _zz_188_; - _zz_189_[7] = _zz_188_; - _zz_189_[6] = _zz_188_; - _zz_189_[5] = _zz_188_; - _zz_189_[4] = _zz_188_; - _zz_189_[3] = _zz_188_; - _zz_189_[2] = _zz_188_; - _zz_189_[1] = _zz_188_; - _zz_189_[0] = _zz_188_; - end - - assign _zz_190_ = _zz_334_[19]; - always @ (*) begin - _zz_191_[10] = _zz_190_; - _zz_191_[9] = _zz_190_; - _zz_191_[8] = _zz_190_; - _zz_191_[7] = _zz_190_; - _zz_191_[6] = _zz_190_; - _zz_191_[5] = _zz_190_; - _zz_191_[4] = _zz_190_; - _zz_191_[3] = _zz_190_; - _zz_191_[2] = _zz_190_; - _zz_191_[1] = _zz_190_; - _zz_191_[0] = _zz_190_; - end - - assign _zz_192_ = _zz_335_[11]; - always @ (*) begin - _zz_193_[18] = _zz_192_; - _zz_193_[17] = _zz_192_; - _zz_193_[16] = _zz_192_; - _zz_193_[15] = _zz_192_; - _zz_193_[14] = _zz_192_; - _zz_193_[13] = _zz_192_; - _zz_193_[12] = _zz_192_; - _zz_193_[11] = _zz_192_; - _zz_193_[10] = _zz_192_; - _zz_193_[9] = _zz_192_; - _zz_193_[8] = _zz_192_; - _zz_193_[7] = _zz_192_; - _zz_193_[6] = _zz_192_; - _zz_193_[5] = _zz_192_; - _zz_193_[4] = _zz_192_; - _zz_193_[3] = _zz_192_; - _zz_193_[2] = _zz_192_; - _zz_193_[1] = _zz_192_; - _zz_193_[0] = _zz_192_; + assign _zz_118 = _zz_288[11]; + always @ (*) begin + _zz_119[19] = _zz_118; + _zz_119[18] = _zz_118; + _zz_119[17] = _zz_118; + _zz_119[16] = _zz_118; + _zz_119[15] = _zz_118; + _zz_119[14] = _zz_118; + _zz_119[13] = _zz_118; + _zz_119[12] = _zz_118; + _zz_119[11] = _zz_118; + _zz_119[10] = _zz_118; + _zz_119[9] = _zz_118; + _zz_119[8] = _zz_118; + _zz_119[7] = _zz_118; + _zz_119[6] = _zz_118; + _zz_119[5] = _zz_118; + _zz_119[4] = _zz_118; + _zz_119[3] = _zz_118; + _zz_119[2] = _zz_118; + _zz_119[1] = _zz_118; + _zz_119[0] = _zz_118; + end + + assign _zz_120 = _zz_289[19]; + always @ (*) begin + _zz_121[10] = _zz_120; + _zz_121[9] = _zz_120; + _zz_121[8] = _zz_120; + _zz_121[7] = _zz_120; + _zz_121[6] = _zz_120; + _zz_121[5] = _zz_120; + _zz_121[4] = _zz_120; + _zz_121[3] = _zz_120; + _zz_121[2] = _zz_120; + _zz_121[1] = _zz_120; + _zz_121[0] = _zz_120; + end + + assign _zz_122 = _zz_290[11]; + always @ (*) begin + _zz_123[18] = _zz_122; + _zz_123[17] = _zz_122; + _zz_123[16] = _zz_122; + _zz_123[15] = _zz_122; + _zz_123[14] = _zz_122; + _zz_123[13] = _zz_122; + _zz_123[12] = _zz_122; + _zz_123[11] = _zz_122; + _zz_123[10] = _zz_122; + _zz_123[9] = _zz_122; + _zz_123[8] = _zz_122; + _zz_123[7] = _zz_122; + _zz_123[6] = _zz_122; + _zz_123[5] = _zz_122; + _zz_123[4] = _zz_122; + _zz_123[3] = _zz_122; + _zz_123[2] = _zz_122; + _zz_123[1] = _zz_122; + _zz_123[0] = _zz_122; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_194_ = (_zz_336_[1] ^ execute_RS1[1]); + _zz_124 = (_zz_291[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_194_ = _zz_337_[1]; + _zz_124 = _zz_292[1]; end default : begin - _zz_194_ = _zz_338_[1]; + _zz_124 = _zz_293[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_194_); - assign _zz_39_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_124); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4923,109 +3892,108 @@ module VexRiscv ( endcase end - assign _zz_195_ = _zz_339_[11]; + assign _zz_125 = _zz_294[11]; always @ (*) begin - _zz_196_[19] = _zz_195_; - _zz_196_[18] = _zz_195_; - _zz_196_[17] = _zz_195_; - _zz_196_[16] = _zz_195_; - _zz_196_[15] = _zz_195_; - _zz_196_[14] = _zz_195_; - _zz_196_[13] = _zz_195_; - _zz_196_[12] = _zz_195_; - _zz_196_[11] = _zz_195_; - _zz_196_[10] = _zz_195_; - _zz_196_[9] = _zz_195_; - _zz_196_[8] = _zz_195_; - _zz_196_[7] = _zz_195_; - _zz_196_[6] = _zz_195_; - _zz_196_[5] = _zz_195_; - _zz_196_[4] = _zz_195_; - _zz_196_[3] = _zz_195_; - _zz_196_[2] = _zz_195_; - _zz_196_[1] = _zz_195_; - _zz_196_[0] = _zz_195_; + _zz_126[19] = _zz_125; + _zz_126[18] = _zz_125; + _zz_126[17] = _zz_125; + _zz_126[16] = _zz_125; + _zz_126[15] = _zz_125; + _zz_126[14] = _zz_125; + _zz_126[13] = _zz_125; + _zz_126[12] = _zz_125; + _zz_126[11] = _zz_125; + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_196_,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_126,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_198_,{{{_zz_574_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_200_,{{{_zz_575_,_zz_576_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_128,{{{_zz_508,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_130,{{{_zz_509,_zz_510},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_342_}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_297}; end end endcase end - assign _zz_197_ = _zz_340_[19]; - always @ (*) begin - _zz_198_[10] = _zz_197_; - _zz_198_[9] = _zz_197_; - _zz_198_[8] = _zz_197_; - _zz_198_[7] = _zz_197_; - _zz_198_[6] = _zz_197_; - _zz_198_[5] = _zz_197_; - _zz_198_[4] = _zz_197_; - _zz_198_[3] = _zz_197_; - _zz_198_[2] = _zz_197_; - _zz_198_[1] = _zz_197_; - _zz_198_[0] = _zz_197_; - end - - assign _zz_199_ = _zz_341_[11]; - always @ (*) begin - _zz_200_[18] = _zz_199_; - _zz_200_[17] = _zz_199_; - _zz_200_[16] = _zz_199_; - _zz_200_[15] = _zz_199_; - _zz_200_[14] = _zz_199_; - _zz_200_[13] = _zz_199_; - _zz_200_[12] = _zz_199_; - _zz_200_[11] = _zz_199_; - _zz_200_[10] = _zz_199_; - _zz_200_[9] = _zz_199_; - _zz_200_[8] = _zz_199_; - _zz_200_[7] = _zz_199_; - _zz_200_[6] = _zz_199_; - _zz_200_[5] = _zz_199_; - _zz_200_[4] = _zz_199_; - _zz_200_[3] = _zz_199_; - _zz_200_[2] = _zz_199_; - _zz_200_[1] = _zz_199_; - _zz_200_[0] = _zz_199_; + assign _zz_127 = _zz_295[19]; + always @ (*) begin + _zz_128[10] = _zz_127; + _zz_128[9] = _zz_127; + _zz_128[8] = _zz_127; + _zz_128[7] = _zz_127; + _zz_128[6] = _zz_127; + _zz_128[5] = _zz_127; + _zz_128[4] = _zz_127; + _zz_128[3] = _zz_127; + _zz_128[2] = _zz_127; + _zz_128[1] = _zz_127; + _zz_128[0] = _zz_127; + end + + assign _zz_129 = _zz_296[11]; + always @ (*) begin + _zz_130[18] = _zz_129; + _zz_130[17] = _zz_129; + _zz_130[16] = _zz_129; + _zz_130[15] = _zz_129; + _zz_130[14] = _zz_129; + _zz_130[13] = _zz_129; + _zz_130[12] = _zz_129; + _zz_130[11] = _zz_129; + _zz_130[10] = _zz_129; + _zz_130[9] = _zz_129; + _zz_130[8] = _zz_129; + _zz_130[7] = _zz_129; + _zz_130[6] = _zz_129; + _zz_130[5] = _zz_129; + _zz_130[4] = _zz_129; + _zz_130[3] = _zz_129; + _zz_130[2] = _zz_129; + _zz_130[1] = _zz_129; + _zz_130[0] = _zz_129; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_38_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign CsrPlugin_misa_base = (2'b01); - assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); - assign _zz_201_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_202_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_203_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign _zz_131 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_132 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_133 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_204_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_205_ = _zz_343_[0]; + assign _zz_134 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_135 = _zz_298[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_258_)begin + if(_zz_204)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -5069,9 +4037,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -5095,7 +4064,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; @@ -5106,7 +4075,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -5117,57 +4086,50 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_36_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_35_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - assign execute_CsrPlugin_inWfi = 1'b0; - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000000 : begin + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000001 : begin + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110011000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_218)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -5186,20 +4148,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_274_)begin + if(_zz_219)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_274_)begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_219)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -5207,57 +4169,24 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_213_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b110011000000 : begin - execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); - execute_CsrPlugin_readData[25 : 20] = (6'b100000); - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_214_; - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_218)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_218)begin + execute_CsrPlugin_readInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_285_) + case(_zz_231) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -5268,10 +4197,10 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_MulPlugin_a = execute_SRC1; - assign execute_MulPlugin_b = execute_SRC2; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_275_) + case(_zz_220) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -5285,7 +4214,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_275_) + case(_zz_220) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -5304,16 +4233,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign _zz_32_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign _zz_31_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - assign _zz_30_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - assign _zz_28_ = ($signed(_zz_345_) + $signed(_zz_353_)); - assign writeBack_MulPlugin_result = ($signed(_zz_354_) + $signed(_zz_355_)); + assign writeBack_MulPlugin_result = ($signed(_zz_300) + $signed(_zz_301)); + assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_253_)begin - if(_zz_261_)begin + if(_zz_199)begin + if(_zz_221)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -5321,44 +4246,44 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_276_)begin + if(_zz_222)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end - assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); always @ (*) begin if(memory_DivPlugin_div_counter_willOverflow)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_359_); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_305); end if(memory_DivPlugin_div_counter_willClear)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_206_ = memory_DivPlugin_rs1[31 : 0]; - assign _zz_207_ = {memory_DivPlugin_accumulator[31 : 0],_zz_206_[31]}; - assign _zz_208_ = (_zz_207_ - _zz_360_); - assign _zz_209_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_210_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_211_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_136 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_136[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_306); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_307 : _zz_308); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_309[31:0]; + assign _zz_137 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_138 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_139 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_212_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_212_[31 : 0] = execute_RS1; + _zz_140[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_140[31 : 0] = execute_RS1; end - assign _zz_214_ = (_zz_213_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_214_ != (32'b00000000000000000000000000000000)); + assign _zz_142 = (_zz_141 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_142 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_277_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_223) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end @@ -5371,7 +4296,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_215_))begin + if((! _zz_143))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -5383,10 +4308,8 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_277_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_223) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; end @@ -5398,39 +4321,39 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign _zz_27_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_26_ = decode_ENV_CTRL; - assign _zz_23_ = execute_ENV_CTRL; - assign _zz_21_ = memory_ENV_CTRL; - assign _zz_24_ = _zz_65_; - assign _zz_34_ = decode_to_execute_ENV_CTRL; - assign _zz_33_ = execute_to_memory_ENV_CTRL; - assign _zz_37_ = memory_to_writeBack_ENV_CTRL; - assign _zz_19_ = decode_SRC2_CTRL; - assign _zz_17_ = _zz_85_; - assign _zz_52_ = decode_to_execute_SRC2_CTRL; - assign _zz_16_ = decode_ALU_BITWISE_CTRL; - assign _zz_14_ = _zz_80_; - assign _zz_59_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_13_ = decode_BRANCH_CTRL; - assign _zz_97_ = _zz_86_; - assign _zz_40_ = decode_to_execute_BRANCH_CTRL; - assign _zz_11_ = decode_SHIFT_CTRL; - assign _zz_8_ = execute_SHIFT_CTRL; - assign _zz_9_ = _zz_73_; - assign _zz_47_ = decode_to_execute_SHIFT_CTRL; - assign _zz_45_ = execute_to_memory_SHIFT_CTRL; - assign _zz_6_ = decode_ALU_CTRL; - assign _zz_4_ = _zz_71_; - assign _zz_57_ = decode_to_execute_ALU_CTRL; - assign _zz_3_ = decode_SRC1_CTRL; - assign _zz_1_ = _zz_75_; - assign _zz_54_ = decode_to_execute_SRC1_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign _zz_26 = decode_SRC1_CTRL; + assign _zz_24 = _zz_49; + assign _zz_37 = decode_to_execute_SRC1_CTRL; + assign _zz_23 = decode_ALU_CTRL; + assign _zz_21 = _zz_48; + assign _zz_38 = decode_to_execute_ALU_CTRL; + assign _zz_20 = decode_SRC2_CTRL; + assign _zz_18 = _zz_47; + assign _zz_36 = decode_to_execute_SRC2_CTRL; + assign _zz_17 = decode_ALU_BITWISE_CTRL; + assign _zz_15 = _zz_46; + assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_14 = decode_SHIFT_CTRL; + assign _zz_11 = execute_SHIFT_CTRL; + assign _zz_12 = _zz_45; + assign _zz_34 = decode_to_execute_SHIFT_CTRL; + assign _zz_33 = execute_to_memory_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_51 = _zz_44; + assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_43; + assign _zz_28 = decode_to_execute_ENV_CTRL; + assign _zz_27 = execute_to_memory_ENV_CTRL; + assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -5449,15 +4372,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_216_) - 3'b000 : begin - end - 3'b001 : begin - end - 3'b010 : begin - end - 3'b011 : begin - end + case(_zz_144) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -5466,71 +4381,143 @@ module VexRiscv ( endcase end - assign iBusWishbone_ADR = {_zz_379_,_zz_217_}; - assign iBusWishbone_CTI = ((_zz_217_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); + always @ (*) begin + _zz_145 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_145[12 : 0] = 13'h1000; + _zz_145[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_146 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_146[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_146[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_146[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_147 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_147[11 : 11] = CsrPlugin_mip_MEIP; + _zz_147[7 : 7] = CsrPlugin_mip_MTIP; + _zz_147[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_148 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_148[11 : 11] = CsrPlugin_mie_MEIE; + _zz_148[7 : 7] = CsrPlugin_mie_MTIE; + _zz_148[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_149 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_149[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_150 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_150[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_150[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_151 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_151[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_152 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_152[31 : 0] = _zz_141; + end + end + + always @ (*) begin + _zz_153 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_153[31 : 0] = _zz_142; + end + end + + assign execute_CsrPlugin_readData = ((((_zz_145 | _zz_146) | (_zz_147 | _zz_148)) | ((_zz_149 | _zz_150) | (_zz_151 | _zz_152))) | _zz_153); + assign iBusWishbone_ADR = {_zz_325,_zz_154}; + assign iBusWishbone_CTI = ((_zz_154 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_278_)begin + if(_zz_224)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_278_)begin + if(_zz_224)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_218_; + assign iBus_rsp_valid = _zz_155; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_224_ = (dBus_cmd_payload_length != (3'b000)); - assign _zz_220_ = dBus_cmd_valid; - assign _zz_222_ = dBus_cmd_payload_wr; - assign _zz_223_ = (_zz_219_ == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_221_ && (_zz_222_ || _zz_223_)); - assign dBusWishbone_ADR = ((_zz_224_ ? {{dBus_cmd_payload_address[31 : 5],_zz_219_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); - assign dBusWishbone_CTI = (_zz_224_ ? (_zz_223_ ? (3'b111) : (3'b010)) : (3'b000)); - assign dBusWishbone_BTE = (2'b00); - assign dBusWishbone_SEL = (_zz_222_ ? dBus_cmd_payload_mask : (4'b1111)); - assign dBusWishbone_WE = _zz_222_; + assign _zz_161 = (dBus_cmd_payload_length != 3'b000); + assign _zz_157 = dBus_cmd_valid; + assign _zz_159 = dBus_cmd_payload_wr; + assign _zz_160 = (_zz_156 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_158 && (_zz_159 || _zz_160)); + assign dBusWishbone_ADR = ((_zz_161 ? {{dBus_cmd_payload_address[31 : 5],_zz_156},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_161 ? (_zz_160 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_159 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_159; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_221_ = (_zz_220_ && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_220_; - assign dBusWishbone_STB = _zz_220_; - assign dBus_rsp_valid = _zz_225_; + assign _zz_158 = (_zz_157 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_157; + assign dBusWishbone_STB = _zz_157; + assign dBus_rsp_valid = _zz_162; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_115_ <= 1'b0; - _zz_117_ <= 1'b0; + _zz_65 <= 1'b0; + _zz_67 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_130_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_131_ <= 1'b0; - _zz_138_ <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_145_; - DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_163_ <= 1'b1; - _zz_176_ <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_80; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_81; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_99 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -5539,23 +4526,30 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_DivPlugin_div_counter_value <= (6'b000000); - _zz_213_ <= (32'b00000000000000000000000000000000); + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_141 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_216_ <= (3'b000); - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_217_ <= (3'b000); - _zz_218_ <= 1'b0; - _zz_219_ <= (3'b000); - _zz_225_ <= 1'b0; + _zz_144 <= 3'b000; + _zz_154 <= 3'b000; + _zz_155 <= 1'b0; + _zz_156 <= 3'b000; + _zz_162 <= 1'b0; end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin @@ -5564,86 +4558,80 @@ module VexRiscv ( if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_115_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_65 <= 1'b0; end - if(_zz_113_)begin - _zz_115_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if(_zz_63)begin + _zz_65 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_117_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_67 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_117_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_67 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_131_ <= 1'b0; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_279_)begin - _zz_131_ <= dataCache_1__io_mem_cmd_valid; + if(_zz_225)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_138_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end if(dBus_rsp_valid)begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_163_ <= 1'b0; - _zz_176_ <= _zz_175_; + _zz_99 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5659,541 +4647,1646 @@ module VexRiscv ( end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_226)begin + if(_zz_227)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_228)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_229)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_207)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_208)begin + case(_zz_210) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_133,{_zz_132,_zz_131}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_144) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_144 <= 3'b001; + end + end + 3'b001 : begin + _zz_144 <= 3'b010; + end + 3'b010 : begin + _zz_144 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_144 <= 3'b100; + end + end + 3'b100 : begin + _zz_144 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_319[0]; + CsrPlugin_mstatus_MIE <= _zz_320[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_322[0]; + CsrPlugin_mie_MTIE <= _zz_323[0]; + CsrPlugin_mie_MSIE <= _zz_324[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_141 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_224)begin + if(iBusWishbone_ACK)begin + _zz_154 <= (_zz_154 + 3'b001); + end + end + _zz_155 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_157 && _zz_158))begin + _zz_156 <= (_zz_156 + 3'b001); + if(_zz_160)begin + _zz_156 <= 3'b000; + end + end + _zz_162 <= ((_zz_157 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_68 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_225)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_204)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_135 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_135 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_226)begin + if(_zz_227)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_228)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_229)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_207)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_199)begin + if(_zz_221)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_310[31:0]; + end + end + end + if(_zz_222)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_139 ? (~ _zz_140) : _zz_140) + _zz_316); + memory_DivPlugin_rs2 <= ((_zz_138 ? (~ execute_RS2) : execute_RS2) + _zz_318); + memory_DivPlugin_div_needRevert <= ((_zz_139 ^ (_zz_138 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_35; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_321[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_280_)begin - if(_zz_281_)begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(_zz_282_)begin - CsrPlugin_interrupt_valid <= 1'b1; - end - if(_zz_283_)begin - CsrPlugin_interrupt_valid <= 1'b1; - end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end - CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_262_)begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; - CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; - end - default : begin - end - endcase + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_50; + end + _zz_143 <= debug_bus_cmd_payload_address[2]; + if(_zz_205)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; end - if(_zz_263_)begin - case(_zz_265_) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); - CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; - CsrPlugin_mstatus_MPIE <= 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_223) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end end default : begin end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_203_,{_zz_202_,_zz_201_}} != (3'b000)); - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_44_; - end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin - execute_arbitration_isValid <= 1'b0; - end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin - execute_arbitration_isValid <= decode_arbitration_isValid; - end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin - memory_arbitration_isValid <= 1'b0; - end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin - memory_arbitration_isValid <= execute_arbitration_isValid; - end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin - writeBack_arbitration_isValid <= 1'b0; - end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; - end - case(_zz_216_) - 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_216_ <= (3'b001); - end - end - 3'b001 : begin - _zz_216_ <= (3'b010); - end - 3'b010 : begin - _zz_216_ <= (3'b011); - end - 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_216_ <= (3'b100); - end - end - 3'b100 : begin - _zz_216_ <= (3'b000); - end - default : begin - end - endcase - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_213_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_373_[0]; - CsrPlugin_mstatus_MIE <= _zz_374_[0]; - end - end - 12'b001101000001 : begin - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - end - 12'b110011000000 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_376_[0]; - CsrPlugin_mie_MTIE <= _zz_377_[0]; - CsrPlugin_mie_MSIE <= _zz_378_[0]; - end - end - 12'b001101000010 : begin - end - default : begin - end - endcase - if(_zz_278_)begin - if(iBusWishbone_ACK)begin - _zz_217_ <= (_zz_217_ + (3'b001)); + if(_zz_205)begin + if(_zz_206)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; end end - _zz_218_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_220_ && _zz_221_))begin - _zz_219_ <= (_zz_219_ + (3'b001)); - if(_zz_223_)begin - _zz_219_ <= (3'b000); + if(_zz_209)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; end end - _zz_225_ <= ((_zz_220_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_118_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; - end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin - IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; - end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin - IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; - end - if(_zz_279_)begin - _zz_132_ <= dataCache_1__io_mem_cmd_payload_wr; - _zz_133_ <= dataCache_1__io_mem_cmd_payload_address; - _zz_134_ <= dataCache_1__io_mem_cmd_payload_data; - _zz_135_ <= dataCache_1__io_mem_cmd_payload_mask; - _zz_136_ <= dataCache_1__io_mem_cmd_payload_length; - _zz_137_ <= dataCache_1__io_mem_cmd_payload_last; - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_139_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - _zz_140_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; - _zz_141_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; - _zz_142_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - _zz_143_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; - _zz_144_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; - end - if(_zz_175_)begin - _zz_177_ <= _zz_60_[11 : 7]; - _zz_178_ <= _zz_91_; - end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; end - if(_zz_258_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_205_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_205_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; - end - if(BranchPlugin_branchExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; end - if(DBusCachedPlugin_exceptionBus_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; end - if(_zz_280_)begin - if(_zz_281_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - if(_zz_282_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - if(_zz_283_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end - if(_zz_262_)begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - default : begin - end - endcase + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_done <= 1'b1; + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end - if(_zz_253_)begin - if(_zz_261_)begin - memory_DivPlugin_rs1[31 : 0] <= _zz_361_[31:0]; - memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_208_[32]) ? _zz_362_ : _zz_363_); - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_result <= _zz_364_[31:0]; - end - end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; end - if(_zz_276_)begin - memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_DivPlugin_rs1 <= ((_zz_211_ ? (~ _zz_212_) : _zz_212_) + _zz_370_); - memory_DivPlugin_rs2 <= ((_zz_210_ ? (~ execute_RS2) : execute_RS2) + _zz_372_); - memory_DivPlugin_div_needRevert <= ((_zz_211_ ^ (_zz_210_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + end + + always @ (*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_25_; + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_22_; + end + + always @ (*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_20_; + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_MUL <= decode_IS_MUL; + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_18_; + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LL <= execute_MUL_LL; + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_15_; + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_43_; + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_99_; + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_98_; + if(_zz_13)begin + stageB_loaderValid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HH <= execute_MUL_HH; + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LH <= execute_MUL_LH; + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_12_; + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HL <= execute_MUL_HL; + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_10_; + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_7_; + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_5_; + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_2_; + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_51_; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_375_[0]; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end end end - 12'b110011000000 : begin + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; end - 12'b001101000011 : begin + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; end - 12'b111111000000 : begin + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; end - 12'b001100000100 : begin + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); end - 12'b001101000010 : begin + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; end - default : begin + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; end - endcase - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end end + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_9, + input [31:0] _zz_10, + input clk, + input reset +); + reg [31:0] _zz_11; + reg [21:0] _zz_12; + wire _zz_13; + wire _zz_14; + wire [0:0] _zz_15; + wire [0:0] _zz_16; + wire [21:0] _zz_17; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_13 = (! lineLoader_flushCounter[7]); + assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_15 = _zz_8[0 : 0]; + assign _zz_16 = _zz_8[1 : 1]; + assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; always @ (posedge clk) begin - DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin - DebugPlugin_firstCycle <= 1'b1; + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end - DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_91_; + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_11 <= banks_0[_zz_4]; end - _zz_215_ <= debug_bus_cmd_payload_address[2]; - if(_zz_259_)begin - DebugPlugin_busReadDataReg <= execute_PC; + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; end - DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end always @ (posedge clk) begin - if(debugReset) begin - DebugPlugin_resetIt <= 1'b0; - DebugPlugin_haltIt <= 1'b0; - DebugPlugin_stepIt <= 1'b0; - DebugPlugin_godmode <= 1'b0; - DebugPlugin_haltedByBreak <= 1'b0; + if(_zz_7) begin + _zz_12 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_13)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_12; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin - DebugPlugin_godmode <= 1'b1; + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; end - if(debug_bus_cmd_valid)begin - case(_zz_277_) - 6'b000000 : begin - if(debug_bus_cmd_payload_wr)begin - DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin - DebugPlugin_resetIt <= 1'b1; - end - if(debug_bus_cmd_payload_data[24])begin - DebugPlugin_resetIt <= 1'b0; - end - if(debug_bus_cmd_payload_data[17])begin - DebugPlugin_haltIt <= 1'b1; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_haltIt <= 1'b0; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_haltedByBreak <= 1'b0; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_godmode <= 1'b0; - end - end - end - 6'b000001 : begin - end - default : begin - end - endcase + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; end - if(_zz_259_)begin - if(_zz_260_)begin - DebugPlugin_haltIt <= 1'b1; - DebugPlugin_haltedByBreak <= 1'b1; - end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end - if(_zz_264_)begin - if(decode_arbitration_isValid)begin - DebugPlugin_haltIt <= 1'b1; + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_14)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; end end end end -endmodule + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_13)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_14)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + if((_zz_9 != 3'b000))begin + io_cpu_fetch_data_regNextWhen <= _zz_10; + end + end + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v index cb27701..95dce32 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v @@ -1,30 +1,41 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:07:09 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + `define BranchCtrlEnum_defaultEncoding_type [1:0] `define BranchCtrlEnum_defaultEncoding_INC 2'b00 `define BranchCtrlEnum_defaultEncoding_B 2'b01 `define BranchCtrlEnum_defaultEncoding_JAL 2'b10 `define BranchCtrlEnum_defaultEncoding_JALR 2'b11 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 `define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] `define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 `define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 `define Src1CtrlEnum_defaultEncoding_type [1:0] `define Src1CtrlEnum_defaultEncoding_RS 2'b00 @@ -32,3175 +43,2214 @@ `define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_174; + wire _zz_175; + wire _zz_176; + wire _zz_177; + wire _zz_178; + wire _zz_179; + wire _zz_180; + wire _zz_181; + reg _zz_182; + wire _zz_183; + wire [31:0] _zz_184; + wire _zz_185; + wire [31:0] _zz_186; + reg _zz_187; + wire _zz_188; + wire _zz_189; + wire [31:0] _zz_190; + wire _zz_191; + wire _zz_192; + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire [3:0] _zz_199; + wire _zz_200; + wire _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_205; + wire _zz_206; + wire _zz_207; + wire _zz_208; + wire _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + wire [1:0] _zz_219; + wire _zz_220; + wire _zz_221; + wire _zz_222; + wire _zz_223; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire [1:0] _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire [1:0] _zz_239; + wire _zz_240; + wire [1:0] _zz_241; + wire [51:0] _zz_242; + wire [51:0] _zz_243; + wire [51:0] _zz_244; + wire [32:0] _zz_245; + wire [51:0] _zz_246; + wire [49:0] _zz_247; + wire [51:0] _zz_248; + wire [49:0] _zz_249; + wire [51:0] _zz_250; + wire [32:0] _zz_251; + wire [31:0] _zz_252; + wire [32:0] _zz_253; + wire [0:0] _zz_254; + wire [0:0] _zz_255; + wire [0:0] _zz_256; + wire [0:0] _zz_257; + wire [0:0] _zz_258; + wire [0:0] _zz_259; + wire [0:0] _zz_260; + wire [0:0] _zz_261; + wire [0:0] _zz_262; + wire [0:0] _zz_263; + wire [0:0] _zz_264; + wire [0:0] _zz_265; + wire [0:0] _zz_266; + wire [0:0] _zz_267; + wire [0:0] _zz_268; + wire [0:0] _zz_269; + wire [0:0] _zz_270; + wire [3:0] _zz_271; + wire [2:0] _zz_272; + wire [31:0] _zz_273; + wire [11:0] _zz_274; + wire [31:0] _zz_275; + wire [19:0] _zz_276; + wire [11:0] _zz_277; + wire [31:0] _zz_278; + wire [31:0] _zz_279; + wire [19:0] _zz_280; + wire [11:0] _zz_281; + wire [2:0] _zz_282; + wire [2:0] _zz_283; + wire [0:0] _zz_284; + wire [2:0] _zz_285; + wire [4:0] _zz_286; + wire [11:0] _zz_287; + wire [11:0] _zz_288; + wire [31:0] _zz_289; + wire [31:0] _zz_290; + wire [31:0] _zz_291; + wire [31:0] _zz_292; + wire [31:0] _zz_293; + wire [31:0] _zz_294; + wire [31:0] _zz_295; + wire [11:0] _zz_296; + wire [19:0] _zz_297; + wire [11:0] _zz_298; + wire [31:0] _zz_299; + wire [31:0] _zz_300; + wire [31:0] _zz_301; + wire [11:0] _zz_302; + wire [19:0] _zz_303; + wire [11:0] _zz_304; + wire [2:0] _zz_305; + wire [1:0] _zz_306; + wire [1:0] _zz_307; + wire [65:0] _zz_308; + wire [65:0] _zz_309; + wire [31:0] _zz_310; + wire [31:0] _zz_311; + wire [0:0] _zz_312; + wire [5:0] _zz_313; + wire [32:0] _zz_314; + wire [31:0] _zz_315; + wire [31:0] _zz_316; + wire [32:0] _zz_317; + wire [32:0] _zz_318; + wire [32:0] _zz_319; + wire [32:0] _zz_320; + wire [0:0] _zz_321; + wire [32:0] _zz_322; + wire [0:0] _zz_323; + wire [32:0] _zz_324; + wire [0:0] _zz_325; + wire [31:0] _zz_326; + wire [0:0] _zz_327; + wire [0:0] _zz_328; + wire [0:0] _zz_329; + wire [0:0] _zz_330; + wire [0:0] _zz_331; + wire [0:0] _zz_332; + wire [0:0] _zz_333; + wire [26:0] _zz_334; + wire _zz_335; + wire _zz_336; + wire [1:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [31:0] _zz_340; + wire _zz_341; + wire [0:0] _zz_342; + wire [13:0] _zz_343; + wire [31:0] _zz_344; + wire [31:0] _zz_345; + wire [31:0] _zz_346; + wire _zz_347; + wire [0:0] _zz_348; + wire [7:0] _zz_349; + wire [31:0] _zz_350; + wire [31:0] _zz_351; + wire [31:0] _zz_352; + wire _zz_353; + wire [0:0] _zz_354; + wire [1:0] _zz_355; + wire _zz_356; + wire _zz_357; + wire _zz_358; + wire [31:0] _zz_359; + wire [31:0] _zz_360; + wire _zz_361; + wire [0:0] _zz_362; + wire [0:0] _zz_363; + wire _zz_364; + wire [0:0] _zz_365; + wire [24:0] _zz_366; + wire [31:0] _zz_367; + wire _zz_368; + wire _zz_369; + wire [0:0] _zz_370; + wire [0:0] _zz_371; + wire [0:0] _zz_372; + wire [0:0] _zz_373; + wire _zz_374; + wire [0:0] _zz_375; + wire [20:0] _zz_376; + wire [31:0] _zz_377; + wire [31:0] _zz_378; + wire _zz_379; + wire _zz_380; + wire [0:0] _zz_381; + wire [1:0] _zz_382; + wire [0:0] _zz_383; + wire [0:0] _zz_384; + wire _zz_385; + wire [0:0] _zz_386; + wire [17:0] _zz_387; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire [31:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire _zz_396; + wire [1:0] _zz_397; + wire [1:0] _zz_398; + wire _zz_399; + wire [0:0] _zz_400; + wire [14:0] _zz_401; + wire [31:0] _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire [31:0] _zz_405; + wire [31:0] _zz_406; + wire [31:0] _zz_407; + wire [0:0] _zz_408; + wire [0:0] _zz_409; + wire [4:0] _zz_410; + wire [4:0] _zz_411; + wire _zz_412; + wire [0:0] _zz_413; + wire [11:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire [31:0] _zz_418; + wire _zz_419; + wire [0:0] _zz_420; + wire [1:0] _zz_421; + wire [31:0] _zz_422; + wire [31:0] _zz_423; + wire [0:0] _zz_424; + wire [3:0] _zz_425; + wire [4:0] _zz_426; + wire [4:0] _zz_427; + wire _zz_428; + wire [0:0] _zz_429; + wire [8:0] _zz_430; + wire [31:0] _zz_431; + wire [31:0] _zz_432; + wire [31:0] _zz_433; + wire _zz_434; + wire _zz_435; + wire [31:0] _zz_436; + wire [31:0] _zz_437; + wire [0:0] _zz_438; + wire [1:0] _zz_439; + wire [0:0] _zz_440; + wire [2:0] _zz_441; + wire [0:0] _zz_442; + wire [4:0] _zz_443; + wire [1:0] _zz_444; + wire [1:0] _zz_445; + wire _zz_446; + wire [0:0] _zz_447; + wire [6:0] _zz_448; + wire [31:0] _zz_449; + wire [31:0] _zz_450; + wire [31:0] _zz_451; + wire [31:0] _zz_452; + wire _zz_453; + wire _zz_454; + wire [31:0] _zz_455; + wire [31:0] _zz_456; + wire _zz_457; + wire [0:0] _zz_458; + wire [0:0] _zz_459; + wire _zz_460; + wire [0:0] _zz_461; + wire [2:0] _zz_462; + wire _zz_463; + wire [0:0] _zz_464; + wire [0:0] _zz_465; + wire [0:0] _zz_466; + wire [0:0] _zz_467; + wire _zz_468; + wire [0:0] _zz_469; + wire [4:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; + wire [31:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; + wire [31:0] _zz_477; + wire [31:0] _zz_478; + wire [31:0] _zz_479; + wire [31:0] _zz_480; + wire _zz_481; + wire [0:0] _zz_482; + wire [0:0] _zz_483; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire [31:0] _zz_486; + wire [31:0] _zz_487; + wire [31:0] _zz_488; + wire _zz_489; + wire [3:0] _zz_490; + wire [3:0] _zz_491; + wire _zz_492; + wire [0:0] _zz_493; + wire [2:0] _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire [31:0] _zz_497; + wire [31:0] _zz_498; + wire [31:0] _zz_499; + wire [31:0] _zz_500; + wire _zz_501; + wire [0:0] _zz_502; + wire [1:0] _zz_503; + wire _zz_504; + wire [2:0] _zz_505; + wire [2:0] _zz_506; + wire _zz_507; + wire [0:0] _zz_508; + wire [0:0] _zz_509; + wire [31:0] _zz_510; + wire [31:0] _zz_511; + wire [31:0] _zz_512; + wire [31:0] _zz_513; + wire [31:0] _zz_514; + wire [31:0] _zz_515; + wire [31:0] _zz_516; + wire _zz_517; + wire _zz_518; + wire _zz_519; + wire [0:0] _zz_520; + wire [0:0] _zz_521; + wire _zz_522; + wire _zz_523; + wire _zz_524; + wire _zz_525; + wire [31:0] _zz_526; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_31; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_35; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_36; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; + wire [31:0] _zz_40; + wire _zz_41; + reg _zz_42; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_43; + wire `BranchCtrlEnum_defaultEncoding_type _zz_44; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; + wire `Src2CtrlEnum_defaultEncoding_type _zz_47; + wire `AluCtrlEnum_defaultEncoding_type _zz_48; + wire `Src1CtrlEnum_defaultEncoding_type _zz_49; + reg [31:0] _zz_50; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_52; + reg [31:0] _zz_53; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_54; + wire [3:0] _zz_55; + wire _zz_56; + wire _zz_57; + wire _zz_58; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_59; + wire _zz_60; + wire _zz_61; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_62; + wire _zz_63; + reg _zz_64; + wire _zz_65; + reg _zz_66; + reg [31:0] _zz_67; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_68; + reg [18:0] _zz_69; + wire _zz_70; + reg [10:0] _zz_71; + wire _zz_72; + reg [18:0] _zz_73; + reg _zz_74; + wire _zz_75; + reg [10:0] _zz_76; + wire _zz_77; + reg [18:0] _zz_78; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_79; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_80; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_81; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_82; + reg [31:0] _zz_83; + wire _zz_84; + reg [31:0] _zz_85; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [31:0] _zz_86; + wire _zz_87; + wire _zz_88; + wire _zz_89; + wire _zz_90; + wire `Src1CtrlEnum_defaultEncoding_type _zz_91; + wire `AluCtrlEnum_defaultEncoding_type _zz_92; + wire `Src2CtrlEnum_defaultEncoding_type _zz_93; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_94; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_95; + wire `BranchCtrlEnum_defaultEncoding_type _zz_96; + wire `EnvCtrlEnum_defaultEncoding_type _zz_97; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_98; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_99; + reg [31:0] _zz_100; + wire _zz_101; + reg [19:0] _zz_102; + wire _zz_103; + reg [19:0] _zz_104; + reg [31:0] _zz_105; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_106; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_107; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_108; + wire _zz_109; + wire _zz_110; + wire _zz_111; + wire _zz_112; + wire _zz_113; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_114; + reg _zz_115; + reg _zz_116; + wire _zz_117; + reg [19:0] _zz_118; + wire _zz_119; + reg [10:0] _zz_120; + wire _zz_121; + reg [18:0] _zz_122; + reg _zz_123; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_124; + reg [19:0] _zz_125; + wire _zz_126; + reg [10:0] _zz_127; + wire _zz_128; + reg [18:0] _zz_129; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_130; + wire _zz_131; + wire _zz_132; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_133; + wire _zz_134; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_135; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_136; + wire _zz_137; + wire _zz_138; + reg [32:0] _zz_139; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_140; + wire [31:0] _zz_141; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_142; + reg [31:0] _zz_143; + reg [31:0] _zz_144; + reg [31:0] _zz_145; + reg [31:0] _zz_146; + reg [31:0] _zz_147; + reg [31:0] _zz_148; + reg [31:0] _zz_149; + reg [31:0] _zz_150; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [2:0] _zz_165; + reg _zz_166; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_167; + wire _zz_168; + wire _zz_169; + wire _zz_170; + wire _zz_171; + wire _zz_172; + reg _zz_173; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [23:0] _zz_20_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [63:0] _zz_23_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; + reg [95:0] _zz_26_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_27_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_29_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_30_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_33_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_34_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_36_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_37_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_39_string; + reg [39:0] _zz_43_string; + reg [31:0] _zz_44_string; + reg [71:0] _zz_45_string; + reg [39:0] _zz_46_string; + reg [23:0] _zz_47_string; + reg [63:0] _zz_48_string; + reg [95:0] _zz_49_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_51_string; + reg [95:0] _zz_91_string; + reg [63:0] _zz_92_string; + reg [23:0] _zz_93_string; + reg [39:0] _zz_94_string; + reg [71:0] _zz_95_string; + reg [31:0] _zz_96_string; + reg [39:0] _zz_97_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire [0:0] _zz_14_; - wire [0:0] _zz_15_; - wire [21:0] _zz_16_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [6:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_7_; - wire [9:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - reg [31:0] io_cpu_fetch_data_regNextWhen; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_hit_valid; - reg decodeStage_hit_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; - assign _zz_12_ = (! lineLoader_flushCounter[7]); - assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_14_ = _zz_7_[0 : 0]; - assign _zz_15_ = _zz_7_[1 : 1]; - assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; - end - end + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_205 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_206 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_207 = 1'b1; + assign _zz_208 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_209 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_210 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_211 = ((_zz_179 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_212 = ((_zz_179 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_213 = ((_zz_179 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_214 = ((_zz_179 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_215 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_216 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_217 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_218 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_219 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_220 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_221 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_222 = (1'b0 || (! 1'b1)); + assign _zz_223 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_224 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_225 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_226 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_227 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_228 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_229 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_230 = execute_INSTRUCTION[13 : 12]; + assign _zz_231 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_232 = (! memory_arbitration_isStuck); + assign _zz_233 = (iBus_cmd_valid || (_zz_165 != 3'b000)); + assign _zz_234 = (_zz_201 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_235 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_236 = ((_zz_130 && 1'b1) && (! 1'b0)); + assign _zz_237 = ((_zz_131 && 1'b1) && (! 1'b0)); + assign _zz_238 = ((_zz_132 && 1'b1) && (! 1'b0)); + assign _zz_239 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_240 = execute_INSTRUCTION[13]; + assign _zz_241 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_242 = ($signed(_zz_243) + $signed(_zz_248)); + assign _zz_243 = ($signed(_zz_244) + $signed(_zz_246)); + assign _zz_244 = 52'h0; + assign _zz_245 = {1'b0,memory_MUL_LL}; + assign _zz_246 = {{19{_zz_245[32]}}, _zz_245}; + assign _zz_247 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_248 = {{2{_zz_247[49]}}, _zz_247}; + assign _zz_249 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_250 = {{2{_zz_249[49]}}, _zz_249}; + assign _zz_251 = ($signed(_zz_253) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_252 = _zz_251[31 : 0]; + assign _zz_253 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_254 = _zz_86[31 : 31]; + assign _zz_255 = _zz_86[30 : 30]; + assign _zz_256 = _zz_86[29 : 29]; + assign _zz_257 = _zz_86[28 : 28]; + assign _zz_258 = _zz_86[25 : 25]; + assign _zz_259 = _zz_86[17 : 17]; + assign _zz_260 = _zz_86[16 : 16]; + assign _zz_261 = _zz_86[13 : 13]; + assign _zz_262 = _zz_86[12 : 12]; + assign _zz_263 = _zz_86[11 : 11]; + assign _zz_264 = _zz_86[15 : 15]; + assign _zz_265 = _zz_86[5 : 5]; + assign _zz_266 = _zz_86[3 : 3]; + assign _zz_267 = _zz_86[20 : 20]; + assign _zz_268 = _zz_86[10 : 10]; + assign _zz_269 = _zz_86[4 : 4]; + assign _zz_270 = _zz_86[0 : 0]; + assign _zz_271 = (_zz_54 - 4'b0001); + assign _zz_272 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_273 = {29'd0, _zz_272}; + assign _zz_274 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_275 = {{_zz_69,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_276 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_277 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_278 = {{_zz_71,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_279 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_280 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_281 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_282 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_283 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_284 = execute_SRC_LESS; + assign _zz_285 = 3'b100; + assign _zz_286 = execute_INSTRUCTION[19 : 15]; + assign _zz_287 = execute_INSTRUCTION[31 : 20]; + assign _zz_288 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_289 = ($signed(_zz_290) + $signed(_zz_293)); + assign _zz_290 = ($signed(_zz_291) + $signed(_zz_292)); + assign _zz_291 = execute_SRC1; + assign _zz_292 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_293 = (execute_SRC_USE_SUB_LESS ? _zz_294 : _zz_295); + assign _zz_294 = 32'h00000001; + assign _zz_295 = 32'h0; + assign _zz_296 = execute_INSTRUCTION[31 : 20]; + assign _zz_297 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_298 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_299 = {_zz_118,execute_INSTRUCTION[31 : 20]}; + assign _zz_300 = {{_zz_120,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_301 = {{_zz_122,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_302 = execute_INSTRUCTION[31 : 20]; + assign _zz_303 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_304 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_305 = 3'b100; + assign _zz_306 = (_zz_133 & (~ _zz_307)); + assign _zz_307 = (_zz_133 - 2'b01); + assign _zz_308 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_309 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_310 = writeBack_MUL_LOW[31 : 0]; + assign _zz_311 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_312 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_313 = {5'd0, _zz_312}; + assign _zz_314 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_315 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_316 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_317 = {_zz_135,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_318 = _zz_319; + assign _zz_319 = _zz_320; + assign _zz_320 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_136) : _zz_136)} + _zz_322); + assign _zz_321 = memory_DivPlugin_div_needRevert; + assign _zz_322 = {32'd0, _zz_321}; + assign _zz_323 = _zz_138; + assign _zz_324 = {32'd0, _zz_323}; + assign _zz_325 = _zz_137; + assign _zz_326 = {31'd0, _zz_325}; + assign _zz_327 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_328 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_329 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_330 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_331 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_332 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_333 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_334 = (iBus_cmd_payload_address >>> 5); + assign _zz_335 = 1'b1; + assign _zz_336 = 1'b1; + assign _zz_337 = {_zz_58,_zz_57}; + assign _zz_338 = 32'h0000107f; + assign _zz_339 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_340 = 32'h00002073; + assign _zz_341 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_342 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_343 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_344) == 32'h00000003),{(_zz_345 == _zz_346),{_zz_347,{_zz_348,_zz_349}}}}}}; + assign _zz_344 = 32'h0000505f; + assign _zz_345 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_346 = 32'h00000063; + assign _zz_347 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_348 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_349 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_350) == 32'h00001013),{(_zz_351 == _zz_352),{_zz_353,{_zz_354,_zz_355}}}}}}; + assign _zz_350 = 32'hfc00307f; + assign _zz_351 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_352 = 32'h00005033; + assign _zz_353 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_354 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_355 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_356 = decode_INSTRUCTION[31]; + assign _zz_357 = decode_INSTRUCTION[31]; + assign _zz_358 = decode_INSTRUCTION[7]; + assign _zz_359 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_360 = 32'h02004020; + assign _zz_361 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_362 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); + assign _zz_363 = 1'b0; + assign _zz_364 = (((decode_INSTRUCTION & _zz_367) == 32'h00000050) != 1'b0); + assign _zz_365 = ({_zz_368,_zz_369} != 2'b00); + assign _zz_366 = {({_zz_370,_zz_371} != 2'b00),{(_zz_372 != _zz_373),{_zz_374,{_zz_375,_zz_376}}}}; + assign _zz_367 = 32'h00403050; + assign _zz_368 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_369 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_370 = _zz_89; + assign _zz_371 = ((decode_INSTRUCTION & _zz_377) == 32'h00000004); + assign _zz_372 = ((decode_INSTRUCTION & _zz_378) == 32'h00000040); + assign _zz_373 = 1'b0; + assign _zz_374 = ({_zz_379,_zz_380} != 2'b00); + assign _zz_375 = ({_zz_381,_zz_382} != 3'b000); + assign _zz_376 = {(_zz_383 != _zz_384),{_zz_385,{_zz_386,_zz_387}}}; + assign _zz_377 = 32'h0000001c; + assign _zz_378 = 32'h00000058; + assign _zz_379 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_380 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_381 = ((decode_INSTRUCTION & _zz_388) == 32'h40001010); + assign _zz_382 = {(_zz_389 == _zz_390),(_zz_391 == _zz_392)}; + assign _zz_383 = ((decode_INSTRUCTION & _zz_393) == 32'h00000024); + assign _zz_384 = 1'b0; + assign _zz_385 = ((_zz_394 == _zz_395) != 1'b0); + assign _zz_386 = (_zz_396 != 1'b0); + assign _zz_387 = {(_zz_397 != _zz_398),{_zz_399,{_zz_400,_zz_401}}}; + assign _zz_388 = 32'h40003054; + assign _zz_389 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_390 = 32'h00001010; + assign _zz_391 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_392 = 32'h00001010; + assign _zz_393 = 32'h00000064; + assign _zz_394 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_395 = 32'h00001000; + assign _zz_396 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_397 = {(_zz_402 == _zz_403),(_zz_404 == _zz_405)}; + assign _zz_398 = 2'b00; + assign _zz_399 = ((_zz_406 == _zz_407) != 1'b0); + assign _zz_400 = ({_zz_408,_zz_409} != 2'b00); + assign _zz_401 = {(_zz_410 != _zz_411),{_zz_412,{_zz_413,_zz_414}}}; + assign _zz_402 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_403 = 32'h00002000; + assign _zz_404 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_405 = 32'h00001000; + assign _zz_406 = (decode_INSTRUCTION & 32'h00004048); + assign _zz_407 = 32'h00004008; + assign _zz_408 = ((decode_INSTRUCTION & _zz_415) == 32'h00000020); + assign _zz_409 = ((decode_INSTRUCTION & _zz_416) == 32'h00000020); + assign _zz_410 = {(_zz_417 == _zz_418),{_zz_419,{_zz_420,_zz_421}}}; + assign _zz_411 = 5'h0; + assign _zz_412 = ((_zz_422 == _zz_423) != 1'b0); + assign _zz_413 = ({_zz_424,_zz_425} != 5'h0); + assign _zz_414 = {(_zz_426 != _zz_427),{_zz_428,{_zz_429,_zz_430}}}; + assign _zz_415 = 32'h00000034; + assign _zz_416 = 32'h00000064; + assign _zz_417 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_418 = 32'h00002040; + assign _zz_419 = ((decode_INSTRUCTION & _zz_431) == 32'h00001040); + assign _zz_420 = (_zz_432 == _zz_433); + assign _zz_421 = {_zz_434,_zz_435}; + assign _zz_422 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_423 = 32'h00000020; + assign _zz_424 = (_zz_436 == _zz_437); + assign _zz_425 = {_zz_88,{_zz_438,_zz_439}}; + assign _zz_426 = {_zz_88,{_zz_440,_zz_441}}; + assign _zz_427 = 5'h0; + assign _zz_428 = ({_zz_442,_zz_443} != 6'h0); + assign _zz_429 = (_zz_444 != _zz_445); + assign _zz_430 = {_zz_446,{_zz_447,_zz_448}}; + assign _zz_431 = 32'h00001040; + assign _zz_432 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_433 = 32'h00000040; + assign _zz_434 = ((decode_INSTRUCTION & _zz_449) == 32'h00000040); + assign _zz_435 = ((decode_INSTRUCTION & _zz_450) == 32'h0); + assign _zz_436 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_437 = 32'h00000040; + assign _zz_438 = (_zz_451 == _zz_452); + assign _zz_439 = {_zz_453,_zz_454}; + assign _zz_440 = (_zz_455 == _zz_456); + assign _zz_441 = {_zz_457,{_zz_458,_zz_459}}; + assign _zz_442 = _zz_89; + assign _zz_443 = {_zz_460,{_zz_461,_zz_462}}; + assign _zz_444 = {_zz_88,_zz_463}; + assign _zz_445 = 2'b00; + assign _zz_446 = ({_zz_464,_zz_465} != 2'b00); + assign _zz_447 = (_zz_466 != _zz_467); + assign _zz_448 = {_zz_468,{_zz_469,_zz_470}}; + assign _zz_449 = 32'h00400040; + assign _zz_450 = 32'h00000038; + assign _zz_451 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_452 = 32'h00004020; + assign _zz_453 = ((decode_INSTRUCTION & _zz_471) == 32'h00000010); + assign _zz_454 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); + assign _zz_455 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_456 = 32'h00002010; + assign _zz_457 = ((decode_INSTRUCTION & _zz_473) == 32'h00000010); + assign _zz_458 = (_zz_474 == _zz_475); + assign _zz_459 = (_zz_476 == _zz_477); + assign _zz_460 = ((decode_INSTRUCTION & _zz_478) == 32'h00001010); + assign _zz_461 = (_zz_479 == _zz_480); + assign _zz_462 = {_zz_481,{_zz_482,_zz_483}}; + assign _zz_463 = ((decode_INSTRUCTION & _zz_484) == 32'h00000020); + assign _zz_464 = _zz_88; + assign _zz_465 = (_zz_485 == _zz_486); + assign _zz_466 = (_zz_487 == _zz_488); + assign _zz_467 = 1'b0; + assign _zz_468 = (_zz_489 != 1'b0); + assign _zz_469 = (_zz_490 != _zz_491); + assign _zz_470 = {_zz_492,{_zz_493,_zz_494}}; + assign _zz_471 = 32'h00000030; + assign _zz_472 = 32'h02000020; + assign _zz_473 = 32'h00001030; + assign _zz_474 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_475 = 32'h00002020; + assign _zz_476 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_477 = 32'h00000020; + assign _zz_478 = 32'h00001010; + assign _zz_479 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_480 = 32'h00002010; + assign _zz_481 = ((decode_INSTRUCTION & _zz_495) == 32'h00000010); + assign _zz_482 = (_zz_496 == _zz_497); + assign _zz_483 = (_zz_498 == _zz_499); + assign _zz_484 = 32'h00000070; + assign _zz_485 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_486 = 32'h0; + assign _zz_487 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_488 = 32'h00004010; + assign _zz_489 = ((decode_INSTRUCTION & _zz_500) == 32'h00002010); + assign _zz_490 = {_zz_501,{_zz_502,_zz_503}}; + assign _zz_491 = 4'b0000; + assign _zz_492 = (_zz_504 != 1'b0); + assign _zz_493 = (_zz_505 != _zz_506); + assign _zz_494 = {_zz_507,{_zz_508,_zz_509}}; + assign _zz_495 = 32'h00000050; + assign _zz_496 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_497 = 32'h00000004; + assign _zz_498 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_499 = 32'h0; + assign _zz_500 = 32'h00006014; + assign _zz_501 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_502 = ((decode_INSTRUCTION & _zz_510) == 32'h0); + assign _zz_503 = {(_zz_511 == _zz_512),(_zz_513 == _zz_514)}; + assign _zz_504 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_505 = {(_zz_515 == _zz_516),{_zz_517,_zz_518}}; + assign _zz_506 = 3'b000; + assign _zz_507 = ({_zz_519,_zz_87} != 2'b00); + assign _zz_508 = ({_zz_520,_zz_521} != 2'b00); + assign _zz_509 = (_zz_522 != 1'b0); + assign _zz_510 = 32'h00000018; + assign _zz_511 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_512 = 32'h00002000; + assign _zz_513 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_514 = 32'h00001000; + assign _zz_515 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_516 = 32'h00000040; + assign _zz_517 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_518 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_519 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_520 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_521 = _zz_87; + assign _zz_522 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_523 = execute_INSTRUCTION[31]; + assign _zz_524 = execute_INSTRUCTION[31]; + assign _zz_525 = execute_INSTRUCTION[7]; + assign _zz_526 = 32'h0; always @ (posedge clk) begin - if(_zz_6_) begin - _zz_10_ <= ways_0_tags[_zz_5_]; + if(_zz_335) begin + _zz_202 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + if(_zz_336) begin + _zz_203 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_9_) begin - _zz_11_ <= ways_0_datas[_zz_8_]; - end - end - - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; - end - end - - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; - end - end - - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; - end - end - end - - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_12_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; + if(_zz_42) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_10_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_11_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; - end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; - end - if(_zz_13_)begin - lineLoader_flushPending <= 1'b0; + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_174 ), //i + .io_cpu_prefetch_isValid (_zz_175 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_176 ), //i + .io_cpu_fetch_isStuck (_zz_177 ), //i + .io_cpu_fetch_isRemoved (_zz_178 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_179 ), //i + .io_cpu_decode_isStuck (_zz_180 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_181 ), //i + .io_cpu_fill_valid (_zz_182 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_183 ), //i + .io_cpu_execute_address (_zz_184[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_81[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_185 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_186[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_187 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_188 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_189 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_190[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_191 ), //i + .io_cpu_writeBack_fence_SR (_zz_192 ), //i + .io_cpu_writeBack_fence_SO (_zz_193 ), //i + .io_cpu_writeBack_fence_SI (_zz_194 ), //i + .io_cpu_writeBack_fence_PW (_zz_195 ), //i + .io_cpu_writeBack_fence_PR (_zz_196 ), //i + .io_cpu_writeBack_fence_PO (_zz_197 ), //i + .io_cpu_writeBack_fence_PI (_zz_198 ), //i + .io_cpu_writeBack_fence_FM (_zz_199[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_200 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_201 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_337) + 2'b00 : begin + _zz_204 = DBusCachedPlugin_redoBranch_payload; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; + 2'b01 : begin + _zz_204 = CsrPlugin_jumpInterface_payload; end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; + 2'b10 : begin + _zz_204 = BranchPlugin_jumpInterface_payload; end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end + default : begin + _zz_204 = IBusCachedPlugin_predictionJumpInterface_payload; end - end + endcase end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_12_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); - end - _zz_3_ <= lineLoader_flushCounter[7]; - if(_zz_13_)begin - lineLoader_flushCounter <= (8'b00000000); - end - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_error <= fetchStage_hit_error; - end + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; + endcase end - -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, - input [1:0] io_cpu_execute_args_size, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - input io_cpu_memory_isRemoved, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - output io_cpu_memory_mmuBus_cmd_isValid, - output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, - output io_cpu_memory_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, - input io_cpu_memory_mmuBus_rsp_isIoAccess, - input io_cpu_memory_mmuBus_rsp_allowRead, - input io_cpu_memory_mmuBus_rsp_allowWrite, - input io_cpu_memory_mmuBus_rsp_allowExecute, - input io_cpu_memory_mmuBus_rsp_exception, - input io_cpu_memory_mmuBus_rsp_refilling, - output io_cpu_memory_mmuBus_end, - input io_cpu_memory_mmuBus_busy, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output reg io_cpu_flush_ready, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, - output reg io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire _zz_16_; - wire _zz_17_; - wire [0:0] _zz_18_; - wire [0:0] _zz_19_; - wire [0:0] _zz_20_; - wire [2:0] _zz_21_; - wire [1:0] _zz_22_; - wire [21:0] _zz_23_; - reg _zz_1_; - reg _zz_2_; - wire haltCpu; - reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3_; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4_; - wire _zz_5_; - wire [31:0] ways_0_dataReadRsp; - reg [3:0] _zz_6_; - wire [3:0] stage0_mask; - wire [0:0] stage0_colisions; - reg stageA_request_wr; - reg [31:0] stageA_request_data; - reg [1:0] stageA_request_size; - reg [3:0] stageA_mask; - wire stageA_wayHits_0; - reg [0:0] stage0_colisions_regNextWhen; - wire [0:0] _zz_7_; - wire [0:0] stageA_colisions; - reg stageB_request_wr; - reg [31:0] stageB_request_data; - reg [1:0] stageB_request_size; - reg stageB_mmuRspFreeze; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg [31:0] stageB_dataReadRsp_0; - wire [0:0] _zz_8_; - reg [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - reg [3:0] stageB_mask; - reg [0:0] stageB_colisions; - reg stageB_loaderValid; - reg stageB_flusher_valid; - wire [31:0] stageB_requestDataBypass; - wire stageB_isAmo; - reg stageB_memCmdSent; - wire [0:0] _zz_9_; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [2:0] loader_counter_valueNext; - reg [2:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_24_; - reg [7:0] _zz_25_; - reg [7:0] _zz_26_; - reg [7:0] _zz_27_; - assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); - assign _zz_15_ = (loader_valid && io_mem_rsp_valid); - assign _zz_16_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - assign _zz_17_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign _zz_18_ = _zz_4_[0 : 0]; - assign _zz_19_ = _zz_4_[1 : 1]; - assign _zz_20_ = loader_counter_willIncrement; - assign _zz_21_ = {2'd0, _zz_20_}; - assign _zz_22_ = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_23_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_23_; - end + always @(*) begin + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_3_) begin - _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; - end + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase end - - always @ (*) begin - _zz_11_ = {_zz_27_, _zz_26_, _zz_25_, _zz_24_}; + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase end - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1_) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1_) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1_) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1_) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_5_) begin - _zz_24_ <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_25_ <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_26_ <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_27_ <= ways_0_data_symbol3[dataReadCmd_payload]; - end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase end - - always @ (*) begin - _zz_1_ = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_1_ = 1'b1; - end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase end - - always @ (*) begin - _zz_2_ = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_2_ = 1'b1; - end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase end - - assign haltCpu = 1'b0; - assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4_ = _zz_10_; - assign ways_0_tagsReadRsp_valid = _zz_18_[0]; - assign ways_0_tagsReadRsp_error = _zz_19_[0]; - assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; - assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRsp = _zz_11_; - always @ (*) begin - tagsReadCmd_valid = 1'b0; - if(_zz_12_)begin - tagsReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; + endcase end - - always @ (*) begin - tagsReadCmd_payload = (7'bxxxxxxx); - if(_zz_12_)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; - end + always @(*) begin + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_valid = 1'b0; - if(_zz_12_)begin - dataReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; + endcase end - - always @ (*) begin - dataReadCmd_payload = (10'bxxxxxxxxxx); - if(_zz_12_)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; - end - if(_zz_13_)begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_valid = 1'b1; - end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_way = (1'bx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = (1'b1); - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_address = (7'bxxxxxxx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_valid = 1'b1; - end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); - end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end + always @(*) begin + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((stageB_request_wr && stageB_waysHit))begin - dataWriteCmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - dataWriteCmd_valid = 1'b0; - end - if(_zz_15_)begin - dataWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_way = (1'bx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_way = stageB_waysHits; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_address = (10'bxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; - end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_data = stageB_requestDataBypass; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end + always @(*) begin + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_mask = (4'bxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_mask = stageB_mask; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_mask = (4'b1111); - end + always @(*) begin + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; + endcase end - - always @ (*) begin - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_6_ = (4'b0001); - end - 2'b01 : begin - _zz_6_ = (4'b0011); - end - default : begin - _zz_6_ = (4'b1111); - end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; endcase end - - assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); - assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; - assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; - assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); - always @ (*) begin - stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin - stageB_mmuRspFreeze = 1'b1; - end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase end - - assign _zz_8_[0] = stageA_wayHits_0; - assign stageB_waysHit = (stageB_waysHits != (1'b0)); - assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - if(io_mem_cmd_ready)begin - stageB_loaderValid = 1'b1; - end - end - end - end - if(_zz_13_)begin - stageB_loaderValid = 1'b0; - end + always @(*) begin + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(_zz_14_)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - if(_zz_13_)begin - io_cpu_writeBack_haltIt = 1'b0; - end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(_zz_16_)begin - io_cpu_flush_ready = 1'b1; - end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase end - - assign stageB_requestDataBypass = stageB_request_data; - assign stageB_isAmo = 1'b0; - always @ (*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin - io_cpu_redo = 1'b1; - end - end - end - end - if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin - io_cpu_redo = 1'b1; - end - if(loader_valid)begin - io_cpu_redo = 1'b1; - end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); - end + always @(*) begin + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; + endcase end - - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_valid = (! stageB_memCmdSent); - end else begin - if(_zz_14_)begin - if(stageB_request_wr)begin - io_mem_cmd_valid = 1'b1; - end - end else begin - if((! stageB_memCmdSent))begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - io_mem_cmd_valid = 1'b0; - end + always @(*) begin + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; - end - end - end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_length = (3'bxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - io_mem_cmd_payload_length = (3'b111); - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_last = 1'bx; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - io_mem_cmd_payload_last = 1'b1; - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - always @ (*) begin - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_data = io_mem_rsp_payload_data; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - end - - assign _zz_9_[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin - loader_counter_willIncrement = 1'b0; - if(_zz_15_)begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_21_); - if(loader_counter_willClear)begin - loader_counter_valueNext = (3'b000); - end - end - - always @ (posedge clk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; - stageA_request_size <= io_cpu_execute_args_size; - end - if((! io_cpu_memory_isStuck))begin - stageA_mask <= stage0_mask; - end - if((! io_cpu_memory_isStuck))begin - stage0_colisions_regNextWhen <= stage0_colisions; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; - stageB_request_size <= stageA_request_size; - end - if(_zz_17_)begin - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_waysHits <= _zz_8_; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_mask <= stageA_mask; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_colisions <= stageA_colisions; - end - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); - end - end - - always @ (posedge clk) begin - if(reset) begin - stageB_flusher_valid <= 1'b1; - stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); - stageB_memCmdSent <= 1'b0; - loader_valid <= 1'b0; - loader_counter_value <= (3'b000); - loader_waysAllocator <= (1'b1); - loader_error <= 1'b0; - end else begin - if(_zz_17_)begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; - end - if(stageB_flusher_valid)begin - if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); - end else begin - stageB_flusher_valid <= 1'b0; - end - end - if(_zz_16_)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); - stageB_flusher_valid <= 1'b1; - end - if(io_mem_cmd_ready)begin - stageB_memCmdSent <= 1'b1; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_memCmdSent <= 1'b0; - end - if(stageB_loaderValid)begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(_zz_15_)begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_counter_willOverflow)begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - end - if((! loader_valid))begin - loader_waysAllocator <= _zz_22_[0:0]; - end - end - end - -endmodule - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset); - wire _zz_221_; - wire _zz_222_; - wire _zz_223_; - wire _zz_224_; - wire [31:0] _zz_225_; - wire _zz_226_; - wire _zz_227_; - wire _zz_228_; - reg _zz_229_; - wire _zz_230_; - wire [31:0] _zz_231_; - wire _zz_232_; - wire [31:0] _zz_233_; - reg _zz_234_; - wire _zz_235_; - wire _zz_236_; - wire [31:0] _zz_237_; - wire _zz_238_; - wire _zz_239_; - reg [31:0] _zz_240_; - reg [31:0] _zz_241_; - reg [31:0] _zz_242_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1__io_cpu_memory_isWrite; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; - wire dataCache_1__io_cpu_memory_mmuBus_end; - wire dataCache_1__io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1__io_cpu_writeBack_data; - wire dataCache_1__io_cpu_writeBack_mmuException; - wire dataCache_1__io_cpu_writeBack_unalignedAccess; - wire dataCache_1__io_cpu_writeBack_accessError; - wire dataCache_1__io_cpu_writeBack_isWrite; - wire dataCache_1__io_cpu_flush_ready; - wire dataCache_1__io_cpu_redo; - wire dataCache_1__io_mem_cmd_valid; - wire dataCache_1__io_mem_cmd_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_payload_length; - wire dataCache_1__io_mem_cmd_payload_last; - wire _zz_243_; - wire _zz_244_; - wire _zz_245_; - wire _zz_246_; - wire _zz_247_; - wire _zz_248_; - wire _zz_249_; - wire _zz_250_; - wire _zz_251_; - wire _zz_252_; - wire _zz_253_; - wire _zz_254_; - wire _zz_255_; - wire _zz_256_; - wire _zz_257_; - wire [1:0] _zz_258_; - wire _zz_259_; - wire _zz_260_; - wire _zz_261_; - wire _zz_262_; - wire _zz_263_; - wire _zz_264_; - wire _zz_265_; - wire _zz_266_; - wire _zz_267_; - wire _zz_268_; - wire [1:0] _zz_269_; - wire _zz_270_; - wire _zz_271_; - wire _zz_272_; - wire _zz_273_; - wire _zz_274_; - wire _zz_275_; - wire _zz_276_; - wire [1:0] _zz_277_; - wire _zz_278_; - wire [1:0] _zz_279_; - wire [4:0] _zz_280_; - wire [2:0] _zz_281_; - wire [31:0] _zz_282_; - wire [11:0] _zz_283_; - wire [31:0] _zz_284_; - wire [19:0] _zz_285_; - wire [11:0] _zz_286_; - wire [31:0] _zz_287_; - wire [31:0] _zz_288_; - wire [19:0] _zz_289_; - wire [11:0] _zz_290_; - wire [2:0] _zz_291_; - wire [2:0] _zz_292_; - wire [0:0] _zz_293_; - wire [0:0] _zz_294_; - wire [0:0] _zz_295_; - wire [0:0] _zz_296_; - wire [0:0] _zz_297_; - wire [0:0] _zz_298_; - wire [0:0] _zz_299_; - wire [0:0] _zz_300_; - wire [0:0] _zz_301_; - wire [0:0] _zz_302_; - wire [0:0] _zz_303_; - wire [0:0] _zz_304_; - wire [0:0] _zz_305_; - wire [0:0] _zz_306_; - wire [0:0] _zz_307_; - wire [0:0] _zz_308_; - wire [0:0] _zz_309_; - wire [0:0] _zz_310_; - wire [2:0] _zz_311_; - wire [4:0] _zz_312_; - wire [11:0] _zz_313_; - wire [11:0] _zz_314_; - wire [31:0] _zz_315_; - wire [31:0] _zz_316_; - wire [31:0] _zz_317_; - wire [31:0] _zz_318_; - wire [31:0] _zz_319_; - wire [31:0] _zz_320_; - wire [31:0] _zz_321_; - wire [32:0] _zz_322_; - wire [31:0] _zz_323_; - wire [32:0] _zz_324_; - wire [11:0] _zz_325_; - wire [19:0] _zz_326_; - wire [11:0] _zz_327_; - wire [31:0] _zz_328_; - wire [31:0] _zz_329_; - wire [31:0] _zz_330_; - wire [11:0] _zz_331_; - wire [19:0] _zz_332_; - wire [11:0] _zz_333_; - wire [2:0] _zz_334_; - wire [1:0] _zz_335_; - wire [1:0] _zz_336_; - wire [51:0] _zz_337_; - wire [51:0] _zz_338_; - wire [51:0] _zz_339_; - wire [32:0] _zz_340_; - wire [51:0] _zz_341_; - wire [49:0] _zz_342_; - wire [51:0] _zz_343_; - wire [49:0] _zz_344_; - wire [51:0] _zz_345_; - wire [65:0] _zz_346_; - wire [65:0] _zz_347_; - wire [31:0] _zz_348_; - wire [31:0] _zz_349_; - wire [0:0] _zz_350_; - wire [5:0] _zz_351_; - wire [32:0] _zz_352_; - wire [32:0] _zz_353_; - wire [31:0] _zz_354_; - wire [31:0] _zz_355_; - wire [32:0] _zz_356_; - wire [32:0] _zz_357_; - wire [32:0] _zz_358_; - wire [0:0] _zz_359_; - wire [32:0] _zz_360_; - wire [0:0] _zz_361_; - wire [32:0] _zz_362_; - wire [0:0] _zz_363_; - wire [31:0] _zz_364_; - wire [0:0] _zz_365_; - wire [0:0] _zz_366_; - wire [0:0] _zz_367_; - wire [0:0] _zz_368_; - wire [0:0] _zz_369_; - wire [0:0] _zz_370_; - wire [0:0] _zz_371_; - wire [26:0] _zz_372_; - wire _zz_373_; - wire _zz_374_; - wire [2:0] _zz_375_; - wire _zz_376_; - wire _zz_377_; - wire _zz_378_; - wire _zz_379_; - wire [0:0] _zz_380_; - wire [1:0] _zz_381_; - wire [31:0] _zz_382_; - wire [31:0] _zz_383_; - wire _zz_384_; - wire [0:0] _zz_385_; - wire [0:0] _zz_386_; - wire _zz_387_; - wire [0:0] _zz_388_; - wire [25:0] _zz_389_; - wire [31:0] _zz_390_; - wire [31:0] _zz_391_; - wire [31:0] _zz_392_; - wire [31:0] _zz_393_; - wire [31:0] _zz_394_; - wire [31:0] _zz_395_; - wire _zz_396_; - wire _zz_397_; - wire [4:0] _zz_398_; - wire [4:0] _zz_399_; - wire _zz_400_; - wire [0:0] _zz_401_; - wire [22:0] _zz_402_; - wire [31:0] _zz_403_; - wire [31:0] _zz_404_; - wire _zz_405_; - wire [0:0] _zz_406_; - wire [1:0] _zz_407_; - wire [31:0] _zz_408_; - wire [31:0] _zz_409_; - wire _zz_410_; - wire [1:0] _zz_411_; - wire [1:0] _zz_412_; - wire _zz_413_; - wire [0:0] _zz_414_; - wire [19:0] _zz_415_; - wire [31:0] _zz_416_; - wire [31:0] _zz_417_; - wire [31:0] _zz_418_; - wire [31:0] _zz_419_; - wire [31:0] _zz_420_; - wire [31:0] _zz_421_; - wire [31:0] _zz_422_; - wire [31:0] _zz_423_; - wire [31:0] _zz_424_; - wire [31:0] _zz_425_; - wire [31:0] _zz_426_; - wire [0:0] _zz_427_; - wire [0:0] _zz_428_; - wire [2:0] _zz_429_; - wire [2:0] _zz_430_; - wire _zz_431_; - wire [0:0] _zz_432_; - wire [16:0] _zz_433_; - wire [31:0] _zz_434_; - wire [31:0] _zz_435_; - wire [31:0] _zz_436_; - wire [31:0] _zz_437_; - wire _zz_438_; - wire _zz_439_; - wire [0:0] _zz_440_; - wire [3:0] _zz_441_; - wire _zz_442_; - wire [0:0] _zz_443_; - wire [0:0] _zz_444_; - wire _zz_445_; - wire [0:0] _zz_446_; - wire [13:0] _zz_447_; - wire [31:0] _zz_448_; - wire [31:0] _zz_449_; - wire [31:0] _zz_450_; - wire [31:0] _zz_451_; - wire _zz_452_; - wire [0:0] _zz_453_; - wire [1:0] _zz_454_; - wire [31:0] _zz_455_; - wire [31:0] _zz_456_; - wire [31:0] _zz_457_; - wire [0:0] _zz_458_; - wire [2:0] _zz_459_; - wire [0:0] _zz_460_; - wire [0:0] _zz_461_; - wire _zz_462_; - wire [0:0] _zz_463_; - wire [11:0] _zz_464_; - wire [31:0] _zz_465_; - wire [31:0] _zz_466_; - wire [31:0] _zz_467_; - wire _zz_468_; - wire _zz_469_; - wire [31:0] _zz_470_; - wire [31:0] _zz_471_; - wire _zz_472_; - wire [0:0] _zz_473_; - wire [0:0] _zz_474_; - wire [31:0] _zz_475_; - wire [31:0] _zz_476_; - wire [0:0] _zz_477_; - wire [3:0] _zz_478_; - wire [1:0] _zz_479_; - wire [1:0] _zz_480_; - wire _zz_481_; - wire [0:0] _zz_482_; - wire [9:0] _zz_483_; - wire [31:0] _zz_484_; - wire [31:0] _zz_485_; - wire [31:0] _zz_486_; - wire [31:0] _zz_487_; - wire [31:0] _zz_488_; - wire [31:0] _zz_489_; - wire [31:0] _zz_490_; - wire [31:0] _zz_491_; - wire [31:0] _zz_492_; - wire [0:0] _zz_493_; - wire [1:0] _zz_494_; - wire _zz_495_; - wire [0:0] _zz_496_; - wire [0:0] _zz_497_; - wire [0:0] _zz_498_; - wire [0:0] _zz_499_; - wire _zz_500_; - wire [0:0] _zz_501_; - wire [7:0] _zz_502_; - wire [31:0] _zz_503_; - wire [31:0] _zz_504_; - wire [31:0] _zz_505_; - wire [31:0] _zz_506_; - wire [31:0] _zz_507_; - wire [31:0] _zz_508_; - wire [31:0] _zz_509_; - wire [0:0] _zz_510_; - wire [0:0] _zz_511_; - wire [1:0] _zz_512_; - wire [1:0] _zz_513_; - wire _zz_514_; - wire [0:0] _zz_515_; - wire [4:0] _zz_516_; - wire [31:0] _zz_517_; - wire [31:0] _zz_518_; - wire [31:0] _zz_519_; - wire [31:0] _zz_520_; - wire _zz_521_; - wire [0:0] _zz_522_; - wire [1:0] _zz_523_; - wire [0:0] _zz_524_; - wire [0:0] _zz_525_; - wire _zz_526_; - wire [0:0] _zz_527_; - wire [1:0] _zz_528_; - wire [31:0] _zz_529_; - wire [31:0] _zz_530_; - wire [31:0] _zz_531_; - wire [31:0] _zz_532_; - wire [31:0] _zz_533_; - wire [31:0] _zz_534_; - wire _zz_535_; - wire _zz_536_; - wire _zz_537_; - wire [0:0] _zz_538_; - wire [0:0] _zz_539_; - wire [0:0] _zz_540_; - wire [0:0] _zz_541_; - wire [31:0] _zz_542_; - wire [31:0] _zz_543_; - wire [31:0] _zz_544_; - wire _zz_545_; - wire [0:0] _zz_546_; - wire [13:0] _zz_547_; - wire [31:0] _zz_548_; - wire [31:0] _zz_549_; - wire [31:0] _zz_550_; - wire _zz_551_; - wire [0:0] _zz_552_; - wire [7:0] _zz_553_; - wire [31:0] _zz_554_; - wire [31:0] _zz_555_; - wire [31:0] _zz_556_; - wire _zz_557_; - wire [0:0] _zz_558_; - wire [1:0] _zz_559_; - wire _zz_560_; - wire _zz_561_; - wire _zz_562_; - wire memory_IS_MUL; - wire execute_IS_MUL; - wire decode_IS_MUL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_1_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_2_; - wire decode_IS_RS2_SIGNED; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_3_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_4_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_5_; - wire decode_CSR_READ_OPCODE; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_7_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_8_; - wire [31:0] execute_MUL_LL; - wire decode_IS_CSR; - wire decode_SRC_LESS_UNSIGNED; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_11_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_12_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_13_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_14_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_15_; - wire decode_IS_DIV; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_16_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_17_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_18_; - wire decode_CSR_WRITE_OPCODE; - wire decode_IS_RS1_SIGNED; - wire execute_BRANCH_DO; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire decode_PREDICTION_HAD_BRANCHED2; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire [31:0] memory_PC; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire [33:0] execute_MUL_HL; - wire [51:0] memory_MUL_LOW; - wire [31:0] execute_SHIFT_RIGHT; - wire decode_SRC2_FORCE_ZERO; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_19_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_; - wire [31:0] execute_BRANCH_CALC; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire decode_MEMORY_MANAGMENT; - wire [33:0] execute_MUL_LH; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_24_; - wire `AluCtrlEnum_defaultEncoding_type _zz_25_; - wire `AluCtrlEnum_defaultEncoding_type _zz_26_; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire [51:0] _zz_27_; - wire [33:0] _zz_28_; - wire [33:0] _zz_29_; - wire [33:0] _zz_30_; - wire [31:0] _zz_31_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_32_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; - wire _zz_34_; - wire _zz_35_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_36_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_37_; - wire [31:0] execute_PC; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_38_; - wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_39_; - wire _zz_40_; - wire _zz_41_; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_42_; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_43_; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_44_; - wire [31:0] _zz_45_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_46_; - wire _zz_47_; - wire [31:0] _zz_48_; - wire [31:0] _zz_49_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_50_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_51_; - wire [31:0] _zz_52_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_53_; - wire [31:0] _zz_54_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_55_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_56_; - wire [31:0] _zz_57_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; - wire [31:0] _zz_59_; - wire _zz_60_; - reg _zz_61_; - wire [31:0] _zz_62_; - wire [31:0] _zz_63_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_64_; - wire _zz_65_; - wire _zz_66_; - wire _zz_67_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_68_; - wire `AluCtrlEnum_defaultEncoding_type _zz_69_; - wire _zz_70_; - wire _zz_71_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_72_; - wire _zz_73_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_74_; - wire _zz_75_; - wire _zz_76_; - wire _zz_77_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_78_; - wire _zz_79_; - wire _zz_80_; - wire _zz_81_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_82_; - wire _zz_83_; - wire _zz_84_; - wire _zz_85_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_86_; - wire _zz_87_; - wire _zz_88_; - reg [31:0] _zz_89_; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_ENABLE; - wire [1:0] _zz_90_; - wire execute_MEMORY_MANAGMENT; - wire [31:0] execute_RS2; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_91_; - reg _zz_92_; - reg _zz_93_; - wire [31:0] _zz_94_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_95_; - wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_96_; - reg [31:0] _zz_97_; - wire [31:0] decode_PC; - wire [31:0] _zz_98_; - wire [31:0] _zz_99_; - wire [31:0] _zz_100_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - wire decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - wire execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - wire execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_predictionJumpInterface_valid; - (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; - reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; - wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire DBusCachedPlugin_mmuBus_rsp_allowRead; - wire DBusCachedPlugin_mmuBus_rsp_allowWrite; - wire DBusCachedPlugin_mmuBus_rsp_allowExecute; - wire DBusCachedPlugin_mmuBus_rsp_exception; - wire DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - wire CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - wire CsrPlugin_allowInterrupts; - wire CsrPlugin_allowException; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_101_; - wire [4:0] _zz_102_; - wire _zz_103_; - wire _zz_104_; - wire _zz_105_; - wire _zz_106_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_107_; - wire _zz_108_; - wire _zz_109_; - wire _zz_110_; - wire _zz_111_; - reg _zz_112_; - wire _zz_113_; - reg _zz_114_; - reg [31:0] _zz_115_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_decodeInput_valid; - wire IBusCachedPlugin_iBusRsp_decodeInput_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - reg IBusCachedPlugin_injector_decodeRemoved; - wire _zz_116_; - reg [18:0] _zz_117_; - wire _zz_118_; - reg [10:0] _zz_119_; - wire _zz_120_; - reg [18:0] _zz_121_; - reg _zz_122_; - wire _zz_123_; - reg [10:0] _zz_124_; - wire _zz_125_; - reg [18:0] _zz_126_; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_127_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; - wire dBus_cmd_payload_last; - wire dBus_rsp_valid; - wire [31:0] dBus_rsp_payload_data; - wire dBus_rsp_payload_error; - wire dataCache_1__io_mem_cmd_s2mPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; - reg _zz_128_; - reg _zz_129_; - reg [31:0] _zz_130_; - reg [31:0] _zz_131_; - reg [3:0] _zz_132_; - reg [2:0] _zz_133_; - reg _zz_134_; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg _zz_135_; - reg _zz_136_; - reg [31:0] _zz_137_; - reg [31:0] _zz_138_; - reg [3:0] _zz_139_; - reg [2:0] _zz_140_; - reg _zz_141_; - wire [31:0] _zz_142_; - reg [31:0] DBusCachedPlugin_rspCounter; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_143_; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_144_; - reg [31:0] _zz_145_; - wire _zz_146_; - reg [31:0] _zz_147_; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [31:0] _zz_148_; - wire _zz_149_; - wire _zz_150_; - wire _zz_151_; - wire _zz_152_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_153_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_154_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_155_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_156_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_157_; - wire `AluCtrlEnum_defaultEncoding_type _zz_158_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_159_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_160_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_161_; - reg [31:0] _zz_162_; - wire _zz_163_; - reg [19:0] _zz_164_; - wire _zz_165_; - reg [19:0] _zz_166_; - reg [31:0] _zz_167_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_168_; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_169_; - reg _zz_170_; - reg _zz_171_; - wire _zz_172_; - reg _zz_173_; - reg [4:0] _zz_174_; - reg [31:0] _zz_175_; - wire _zz_176_; - wire _zz_177_; - wire _zz_178_; - wire _zz_179_; - wire _zz_180_; - wire _zz_181_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_182_; - reg _zz_183_; - reg _zz_184_; - wire _zz_185_; - reg [19:0] _zz_186_; - wire _zz_187_; - reg [10:0] _zz_188_; - wire _zz_189_; - reg [18:0] _zz_190_; - reg _zz_191_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_192_; - reg [19:0] _zz_193_; - wire _zz_194_; - reg [10:0] _zz_195_; - wire _zz_196_; - reg [18:0] _zz_197_; - wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] CsrPlugin_misa_base; - reg [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_198_; - wire _zz_199_; - wire _zz_200_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_201_; - wire _zz_202_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - reg CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - reg execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - wire [65:0] writeBack_MulPlugin_result; - reg [32:0] memory_DivPlugin_rs1; - reg [31:0] memory_DivPlugin_rs2; - reg [64:0] memory_DivPlugin_accumulator; - reg memory_DivPlugin_div_needRevert; - reg memory_DivPlugin_div_counter_willIncrement; - reg memory_DivPlugin_div_counter_willClear; - reg [5:0] memory_DivPlugin_div_counter_valueNext; - reg [5:0] memory_DivPlugin_div_counter_value; - wire memory_DivPlugin_div_counter_willOverflowIfInc; - wire memory_DivPlugin_div_counter_willOverflow; - reg memory_DivPlugin_div_done; - reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_203_; - wire [32:0] _zz_204_; - wire [32:0] _zz_205_; - wire [31:0] _zz_206_; - wire _zz_207_; - wire _zz_208_; - reg [32:0] _zz_209_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_210_; - wire [31:0] _zz_211_; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg [33:0] execute_to_memory_MUL_LH; - reg decode_to_execute_MEMORY_MANAGMENT; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_to_execute_RS2; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg [51:0] memory_to_writeBack_MUL_LOW; - reg [33:0] execute_to_memory_MUL_HL; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg [33:0] execute_to_memory_MUL_HH; - reg [33:0] memory_to_writeBack_MUL_HH; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg execute_to_memory_BRANCH_DO; - reg decode_to_execute_IS_RS1_SIGNED; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg decode_to_execute_IS_CSR; - reg [31:0] execute_to_memory_MUL_LL; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg decode_to_execute_CSR_READ_OPCODE; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg decode_to_execute_MEMORY_WR; - reg execute_to_memory_MEMORY_WR; - reg memory_to_writeBack_MEMORY_WR; - reg decode_to_execute_IS_RS2_SIGNED; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg memory_to_writeBack_IS_MUL; - reg [31:0] decode_to_execute_RS1; - reg [2:0] _zz_212_; - reg _zz_213_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_214_; - wire _zz_215_; - wire _zz_216_; - wire _zz_217_; - wire _zz_218_; - wire _zz_219_; - reg _zz_220_; - reg [31:0] dBusWishbone_DAT_MISO_regNext; - `ifndef SYNTHESIS - reg [31:0] _zz_1__string; - reg [31:0] _zz_2__string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_3__string; - reg [23:0] _zz_4__string; - reg [23:0] _zz_5__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_6__string; - reg [39:0] _zz_7__string; - reg [39:0] _zz_8__string; - reg [39:0] _zz_9__string; - reg [39:0] _zz_10__string; - reg [39:0] _zz_11__string; - reg [39:0] _zz_12__string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_13__string; - reg [39:0] _zz_14__string; - reg [39:0] _zz_15__string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_16__string; - reg [95:0] _zz_17__string; - reg [95:0] _zz_18__string; - reg [71:0] _zz_19__string; - reg [71:0] _zz_20__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_21__string; - reg [71:0] _zz_22__string; - reg [71:0] _zz_23__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_24__string; - reg [63:0] _zz_25__string; - reg [63:0] _zz_26__string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_32__string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_33__string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_36__string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_39__string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_44__string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_46__string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_51__string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_53__string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_56__string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_58__string; - reg [31:0] _zz_68__string; - reg [63:0] _zz_69__string; - reg [71:0] _zz_72__string; - reg [39:0] _zz_74__string; - reg [95:0] _zz_78__string; - reg [23:0] _zz_82__string; - reg [39:0] _zz_86__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_95__string; - reg [39:0] _zz_153__string; - reg [23:0] _zz_154__string; - reg [95:0] _zz_155__string; - reg [39:0] _zz_156__string; - reg [71:0] _zz_157__string; - reg [63:0] _zz_158__string; - reg [31:0] _zz_159__string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - `endif - - (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_243_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_244_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_245_ = 1'b1; - assign _zz_246_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_247_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_248_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_249_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_91_)); - assign _zz_250_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_92_)); - assign _zz_251_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_93_)); - assign _zz_252_ = ((_zz_226_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); - assign _zz_253_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_254_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_255_ = (! memory_DivPlugin_div_done); - assign _zz_256_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_257_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_258_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_259_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_260_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_261_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_262_ = (1'b0 || (! 1'b1)); - assign _zz_263_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_264_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_265_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_266_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_267_ = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_268_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_269_ = execute_INSTRUCTION[13 : 12]; - assign _zz_270_ = (! memory_arbitration_isStuck); - assign _zz_271_ = (iBus_cmd_valid || (_zz_212_ != (3'b000))); - assign _zz_272_ = (_zz_239_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); - assign _zz_273_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_274_ = ((_zz_198_ && 1'b1) && (! 1'b0)); - assign _zz_275_ = ((_zz_199_ && 1'b1) && (! 1'b0)); - assign _zz_276_ = ((_zz_200_ && 1'b1) && (! 1'b0)); - assign _zz_277_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_278_ = execute_INSTRUCTION[13]; - assign _zz_279_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_280_ = (_zz_101_ - (5'b00001)); - assign _zz_281_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_282_ = {29'd0, _zz_281_}; - assign _zz_283_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_284_ = {{_zz_117_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_285_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_286_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_287_ = {{_zz_119_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_288_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_289_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_290_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_291_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); - assign _zz_292_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); - assign _zz_293_ = _zz_148_[0 : 0]; - assign _zz_294_ = _zz_148_[3 : 3]; - assign _zz_295_ = _zz_148_[4 : 4]; - assign _zz_296_ = _zz_148_[5 : 5]; - assign _zz_297_ = _zz_148_[8 : 8]; - assign _zz_298_ = _zz_148_[9 : 9]; - assign _zz_299_ = _zz_148_[10 : 10]; - assign _zz_300_ = _zz_148_[13 : 13]; - assign _zz_301_ = _zz_148_[14 : 14]; - assign _zz_302_ = _zz_148_[15 : 15]; - assign _zz_303_ = _zz_148_[18 : 18]; - assign _zz_304_ = _zz_148_[21 : 21]; - assign _zz_305_ = _zz_148_[22 : 22]; - assign _zz_306_ = _zz_148_[28 : 28]; - assign _zz_307_ = _zz_148_[29 : 29]; - assign _zz_308_ = _zz_148_[30 : 30]; - assign _zz_309_ = _zz_148_[31 : 31]; - assign _zz_310_ = execute_SRC_LESS; - assign _zz_311_ = (3'b100); - assign _zz_312_ = execute_INSTRUCTION[19 : 15]; - assign _zz_313_ = execute_INSTRUCTION[31 : 20]; - assign _zz_314_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_315_ = ($signed(_zz_316_) + $signed(_zz_319_)); - assign _zz_316_ = ($signed(_zz_317_) + $signed(_zz_318_)); - assign _zz_317_ = execute_SRC1; - assign _zz_318_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_319_ = (execute_SRC_USE_SUB_LESS ? _zz_320_ : _zz_321_); - assign _zz_320_ = (32'b00000000000000000000000000000001); - assign _zz_321_ = (32'b00000000000000000000000000000000); - assign _zz_322_ = ($signed(_zz_324_) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_323_ = _zz_322_[31 : 0]; - assign _zz_324_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_325_ = execute_INSTRUCTION[31 : 20]; - assign _zz_326_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_327_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_328_ = {_zz_186_,execute_INSTRUCTION[31 : 20]}; - assign _zz_329_ = {{_zz_188_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_330_ = {{_zz_190_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_331_ = execute_INSTRUCTION[31 : 20]; - assign _zz_332_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_333_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_334_ = (3'b100); - assign _zz_335_ = (_zz_201_ & (~ _zz_336_)); - assign _zz_336_ = (_zz_201_ - (2'b01)); - assign _zz_337_ = ($signed(_zz_338_) + $signed(_zz_343_)); - assign _zz_338_ = ($signed(_zz_339_) + $signed(_zz_341_)); - assign _zz_339_ = (52'b0000000000000000000000000000000000000000000000000000); - assign _zz_340_ = {1'b0,memory_MUL_LL}; - assign _zz_341_ = {{19{_zz_340_[32]}}, _zz_340_}; - assign _zz_342_ = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_343_ = {{2{_zz_342_[49]}}, _zz_342_}; - assign _zz_344_ = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_345_ = {{2{_zz_344_[49]}}, _zz_344_}; - assign _zz_346_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_347_ = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_348_ = writeBack_MUL_LOW[31 : 0]; - assign _zz_349_ = writeBack_MulPlugin_result[63 : 32]; - assign _zz_350_ = memory_DivPlugin_div_counter_willIncrement; - assign _zz_351_ = {5'd0, _zz_350_}; - assign _zz_352_ = {1'd0, memory_DivPlugin_rs2}; - assign _zz_353_ = {_zz_203_,(! _zz_205_[32])}; - assign _zz_354_ = _zz_205_[31:0]; - assign _zz_355_ = _zz_204_[31:0]; - assign _zz_356_ = _zz_357_; - assign _zz_357_ = _zz_358_; - assign _zz_358_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_206_) : _zz_206_)} + _zz_360_); - assign _zz_359_ = memory_DivPlugin_div_needRevert; - assign _zz_360_ = {32'd0, _zz_359_}; - assign _zz_361_ = _zz_208_; - assign _zz_362_ = {32'd0, _zz_361_}; - assign _zz_363_ = _zz_207_; - assign _zz_364_ = {31'd0, _zz_363_}; - assign _zz_365_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_366_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_367_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_368_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_369_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_370_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_371_ = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_372_ = (iBus_cmd_payload_address >>> 5); - assign _zz_373_ = 1'b1; - assign _zz_374_ = 1'b1; - assign _zz_375_ = {_zz_104_,{_zz_106_,_zz_105_}}; - assign _zz_376_ = decode_INSTRUCTION[31]; - assign _zz_377_ = decode_INSTRUCTION[31]; - assign _zz_378_ = decode_INSTRUCTION[7]; - assign _zz_379_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000110000)) == (32'b00000000000000000010000000010000)); - assign _zz_380_ = ((decode_INSTRUCTION & _zz_390_) == (32'b00000000000000000000000000010000)); - assign _zz_381_ = {(_zz_391_ == _zz_392_),(_zz_393_ == _zz_394_)}; - assign _zz_382_ = (decode_INSTRUCTION & (32'b00000000000000000100000001001000)); - assign _zz_383_ = (32'b00000000000000000100000000001000); - assign _zz_384_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001110100)) == (32'b00000010000000000000000000110000)); - assign _zz_385_ = ((decode_INSTRUCTION & _zz_395_) == (32'b00000000000000000000000000100100)); - assign _zz_386_ = (1'b0); - assign _zz_387_ = ({_zz_152_,_zz_396_} != (2'b00)); - assign _zz_388_ = (_zz_397_ != (1'b0)); - assign _zz_389_ = {(_zz_398_ != _zz_399_),{_zz_400_,{_zz_401_,_zz_402_}}}; - assign _zz_390_ = (32'b00000000000000000001000000110000); - assign _zz_391_ = (decode_INSTRUCTION & (32'b00000010000000000010000001100000)); - assign _zz_392_ = (32'b00000000000000000010000000100000); - assign _zz_393_ = (decode_INSTRUCTION & (32'b00000010000000000011000000100000)); - assign _zz_394_ = (32'b00000000000000000000000000100000); - assign _zz_395_ = (32'b00000000000000000000000001100100); - assign _zz_396_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); - assign _zz_397_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); - assign _zz_398_ = {(_zz_403_ == _zz_404_),{_zz_405_,{_zz_406_,_zz_407_}}}; - assign _zz_399_ = (5'b00000); - assign _zz_400_ = ((_zz_408_ == _zz_409_) != (1'b0)); - assign _zz_401_ = (_zz_410_ != (1'b0)); - assign _zz_402_ = {(_zz_411_ != _zz_412_),{_zz_413_,{_zz_414_,_zz_415_}}}; - assign _zz_403_ = (decode_INSTRUCTION & (32'b00000000000000000010000001000000)); - assign _zz_404_ = (32'b00000000000000000010000001000000); - assign _zz_405_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001000000)) == (32'b00000000000000000001000001000000)); - assign _zz_406_ = ((decode_INSTRUCTION & _zz_416_) == (32'b00000000000000000000000001000000)); - assign _zz_407_ = {(_zz_417_ == _zz_418_),(_zz_419_ == _zz_420_)}; - assign _zz_408_ = (decode_INSTRUCTION & (32'b00000000000000000100000000010100)); - assign _zz_409_ = (32'b00000000000000000100000000010000); - assign _zz_410_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)); - assign _zz_411_ = {(_zz_421_ == _zz_422_),(_zz_423_ == _zz_424_)}; - assign _zz_412_ = (2'b00); - assign _zz_413_ = ((_zz_425_ == _zz_426_) != (1'b0)); - assign _zz_414_ = ({_zz_427_,_zz_428_} != (2'b00)); - assign _zz_415_ = {(_zz_429_ != _zz_430_),{_zz_431_,{_zz_432_,_zz_433_}}}; - assign _zz_416_ = (32'b00000000000000000000000001010000); - assign _zz_417_ = (decode_INSTRUCTION & (32'b00000000010000000000000001000000)); - assign _zz_418_ = (32'b00000000000000000000000001000000); - assign _zz_419_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000)); - assign _zz_420_ = (32'b00000000000000000000000000000000); - assign _zz_421_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); - assign _zz_422_ = (32'b00000000000000000000000000100000); - assign _zz_423_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_424_ = (32'b00000000000000000000000000100000); - assign _zz_425_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_426_ = (32'b00000000000000000000000000100000); - assign _zz_427_ = ((decode_INSTRUCTION & _zz_434_) == (32'b00000000000000000101000000010000)); - assign _zz_428_ = ((decode_INSTRUCTION & _zz_435_) == (32'b00000000000000000101000000100000)); - assign _zz_429_ = {(_zz_436_ == _zz_437_),{_zz_438_,_zz_439_}}; - assign _zz_430_ = (3'b000); - assign _zz_431_ = ({_zz_152_,{_zz_440_,_zz_441_}} != (6'b000000)); - assign _zz_432_ = (_zz_442_ != (1'b0)); - assign _zz_433_ = {(_zz_443_ != _zz_444_),{_zz_445_,{_zz_446_,_zz_447_}}}; - assign _zz_434_ = (32'b00000000000000000111000000110100); - assign _zz_435_ = (32'b00000010000000000111000001100100); - assign _zz_436_ = (decode_INSTRUCTION & (32'b01000000000000000011000001010100)); - assign _zz_437_ = (32'b01000000000000000001000000010000); - assign _zz_438_ = ((decode_INSTRUCTION & _zz_448_) == (32'b00000000000000000001000000010000)); - assign _zz_439_ = ((decode_INSTRUCTION & _zz_449_) == (32'b00000000000000000001000000010000)); - assign _zz_440_ = (_zz_450_ == _zz_451_); - assign _zz_441_ = {_zz_452_,{_zz_453_,_zz_454_}}; - assign _zz_442_ = ((decode_INSTRUCTION & _zz_455_) == (32'b00000000000000000000000001010000)); - assign _zz_443_ = (_zz_456_ == _zz_457_); - assign _zz_444_ = (1'b0); - assign _zz_445_ = ({_zz_458_,_zz_459_} != (4'b0000)); - assign _zz_446_ = (_zz_460_ != _zz_461_); - assign _zz_447_ = {_zz_462_,{_zz_463_,_zz_464_}}; - assign _zz_448_ = (32'b00000000000000000111000000110100); - assign _zz_449_ = (32'b00000010000000000111000001010100); - assign _zz_450_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); - assign _zz_451_ = (32'b00000000000000000001000000010000); - assign _zz_452_ = ((decode_INSTRUCTION & _zz_465_) == (32'b00000000000000000010000000010000)); - assign _zz_453_ = (_zz_466_ == _zz_467_); - assign _zz_454_ = {_zz_468_,_zz_469_}; - assign _zz_455_ = (32'b00000000001000000011000001010000); - assign _zz_456_ = (decode_INSTRUCTION & (32'b00000000010000000011000001010000)); - assign _zz_457_ = (32'b00000000000000000000000001010000); - assign _zz_458_ = (_zz_470_ == _zz_471_); - assign _zz_459_ = {_zz_472_,{_zz_473_,_zz_474_}}; - assign _zz_460_ = (_zz_475_ == _zz_476_); - assign _zz_461_ = (1'b0); - assign _zz_462_ = ({_zz_477_,_zz_478_} != (5'b00000)); - assign _zz_463_ = (_zz_479_ != _zz_480_); - assign _zz_464_ = {_zz_481_,{_zz_482_,_zz_483_}}; - assign _zz_465_ = (32'b00000000000000000010000000010000); - assign _zz_466_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000)); - assign _zz_467_ = (32'b00000000000000000000000000010000); - assign _zz_468_ = ((decode_INSTRUCTION & _zz_484_) == (32'b00000000000000000000000000000100)); - assign _zz_469_ = ((decode_INSTRUCTION & _zz_485_) == (32'b00000000000000000000000000000000)); - assign _zz_470_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_471_ = (32'b00000000000000000000000000000000); - assign _zz_472_ = ((decode_INSTRUCTION & _zz_486_) == (32'b00000000000000000000000000000000)); - assign _zz_473_ = (_zz_487_ == _zz_488_); - assign _zz_474_ = (_zz_489_ == _zz_490_); - assign _zz_475_ = (decode_INSTRUCTION & (32'b00000010000000000100000001100100)); - assign _zz_476_ = (32'b00000010000000000100000000100000); - assign _zz_477_ = (_zz_491_ == _zz_492_); - assign _zz_478_ = {_zz_150_,{_zz_493_,_zz_494_}}; - assign _zz_479_ = {_zz_495_,_zz_151_}; - assign _zz_480_ = (2'b00); - assign _zz_481_ = ({_zz_496_,_zz_497_} != (2'b00)); - assign _zz_482_ = (_zz_498_ != _zz_499_); - assign _zz_483_ = {_zz_500_,{_zz_501_,_zz_502_}}; - assign _zz_484_ = (32'b00000000000000000000000000001100); - assign _zz_485_ = (32'b00000000000000000000000000101000); - assign _zz_486_ = (32'b00000000000000000000000000011000); - assign _zz_487_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); - assign _zz_488_ = (32'b00000000000000000010000000000000); - assign _zz_489_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); - assign _zz_490_ = (32'b00000000000000000001000000000000); - assign _zz_491_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000000)); - assign _zz_492_ = (32'b00000000000000000000000001000000); - assign _zz_493_ = ((decode_INSTRUCTION & _zz_503_) == (32'b00000000000000000100000000100000)); - assign _zz_494_ = {(_zz_504_ == _zz_505_),(_zz_506_ == _zz_507_)}; - assign _zz_495_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010100)) == (32'b00000000000000000000000000000100)); - assign _zz_496_ = ((decode_INSTRUCTION & _zz_508_) == (32'b00000000000000000000000000000100)); - assign _zz_497_ = _zz_151_; - assign _zz_498_ = ((decode_INSTRUCTION & _zz_509_) == (32'b00000000000000000000000000000000)); - assign _zz_499_ = (1'b0); - assign _zz_500_ = (_zz_149_ != (1'b0)); - assign _zz_501_ = ({_zz_510_,_zz_511_} != (2'b00)); - assign _zz_502_ = {(_zz_512_ != _zz_513_),{_zz_514_,{_zz_515_,_zz_516_}}}; - assign _zz_503_ = (32'b00000000000000000100000000100000); - assign _zz_504_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110000)); - assign _zz_505_ = (32'b00000000000000000000000000010000); - assign _zz_506_ = (decode_INSTRUCTION & (32'b00000010000000000000000000100000)); - assign _zz_507_ = (32'b00000000000000000000000000100000); - assign _zz_508_ = (32'b00000000000000000000000001000100); - assign _zz_509_ = (32'b00000000000000000000000001011000); - assign _zz_510_ = ((decode_INSTRUCTION & _zz_517_) == (32'b00000000000000000010000000000000)); - assign _zz_511_ = ((decode_INSTRUCTION & _zz_518_) == (32'b00000000000000000001000000000000)); - assign _zz_512_ = {_zz_150_,(_zz_519_ == _zz_520_)}; - assign _zz_513_ = (2'b00); - assign _zz_514_ = ({_zz_150_,_zz_521_} != (2'b00)); - assign _zz_515_ = ({_zz_522_,_zz_523_} != (3'b000)); - assign _zz_516_ = {(_zz_524_ != _zz_525_),{_zz_526_,{_zz_527_,_zz_528_}}}; - assign _zz_517_ = (32'b00000000000000000010000000010000); - assign _zz_518_ = (32'b00000000000000000101000000000000); - assign _zz_519_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); - assign _zz_520_ = (32'b00000000000000000000000000100000); - assign _zz_521_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); - assign _zz_522_ = ((decode_INSTRUCTION & _zz_529_) == (32'b00000000000000000000000001000000)); - assign _zz_523_ = {(_zz_530_ == _zz_531_),(_zz_532_ == _zz_533_)}; - assign _zz_524_ = ((decode_INSTRUCTION & _zz_534_) == (32'b00000000000000000001000000001000)); - assign _zz_525_ = (1'b0); - assign _zz_526_ = ({_zz_535_,_zz_536_} != (2'b00)); - assign _zz_527_ = (_zz_537_ != (1'b0)); - assign _zz_528_ = {(_zz_538_ != _zz_539_),(_zz_540_ != _zz_541_)}; - assign _zz_529_ = (32'b00000000000000000000000001000100); - assign _zz_530_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); - assign _zz_531_ = (32'b00000000000000000010000000010000); - assign _zz_532_ = (decode_INSTRUCTION & (32'b01000000000000000000000000110100)); - assign _zz_533_ = (32'b01000000000000000000000000110000); - assign _zz_534_ = (32'b00000000000000000101000001001000); - assign _zz_535_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001010000)) == (32'b00000000000000000001000001010000)); - assign _zz_536_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000001010000)); - assign _zz_537_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_538_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); - assign _zz_539_ = (1'b0); - assign _zz_540_ = _zz_149_; - assign _zz_541_ = (1'b0); - assign _zz_542_ = (32'b00000000000000000001000001111111); - assign _zz_543_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_544_ = (32'b00000000000000000010000001110011); - assign _zz_545_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_546_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_547_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_548_) == (32'b00000000000000000000000000000011)),{(_zz_549_ == _zz_550_),{_zz_551_,{_zz_552_,_zz_553_}}}}}}; - assign _zz_548_ = (32'b00000000000000000101000001011111); - assign _zz_549_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_550_ = (32'b00000000000000000000000001100011); - assign _zz_551_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_552_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_553_ = {((decode_INSTRUCTION & (32'b00000001111100000111000001111111)) == (32'b00000000000000000101000000001111)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_554_) == (32'b00000000000000000001000000010011)),{(_zz_555_ == _zz_556_),{_zz_557_,{_zz_558_,_zz_559_}}}}}}; - assign _zz_554_ = (32'b11111100000000000011000001111111); - assign _zz_555_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_556_ = (32'b00000000000000000101000000110011); - assign _zz_557_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_558_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_559_ = {((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)),((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011))}; - assign _zz_560_ = execute_INSTRUCTION[31]; - assign _zz_561_ = execute_INSTRUCTION[31]; - assign _zz_562_ = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_61_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_373_) begin - _zz_240_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_374_) begin - _zz_241_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_221_), - .io_cpu_prefetch_isValid(_zz_222_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_223_), - .io_cpu_fetch_isStuck(_zz_224_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_225_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_226_), - .io_cpu_decode_isStuck(_zz_227_), - .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), - .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), - .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), - .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), - .io_cpu_decode_isUser(_zz_228_), - .io_cpu_fill_valid(_zz_229_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); - DataCache dataCache_1_ ( - .io_cpu_execute_isValid(_zz_230_), - .io_cpu_execute_address(_zz_231_), - .io_cpu_execute_args_wr(execute_MEMORY_WR), - .io_cpu_execute_args_data(_zz_143_), - .io_cpu_execute_args_size(execute_DBusCachedPlugin_size), - .io_cpu_memory_isValid(_zz_232_), - .io_cpu_memory_isStuck(memory_arbitration_isStuck), - .io_cpu_memory_isRemoved(memory_arbitration_removeIt), - .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), - .io_cpu_memory_address(_zz_233_), - .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), - .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), - .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), - .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_234_), - .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), - .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), - .io_cpu_writeBack_isValid(_zz_235_), - .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), - .io_cpu_writeBack_isUser(_zz_236_), - .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), - .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), - .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), - .io_cpu_writeBack_address(_zz_237_), - .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), - .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), - .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), - .io_cpu_redo(dataCache_1__io_cpu_redo), - .io_cpu_flush_valid(_zz_238_), - .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), - .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), - .io_mem_cmd_ready(_zz_239_), - .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), - .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), - .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), - .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), - .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), - .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), - .io_mem_rsp_valid(dBus_rsp_valid), - .io_mem_rsp_payload_data(dBus_rsp_payload_data), - .io_mem_rsp_payload_error(dBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); - always @(*) begin - case(_zz_375_) - 3'b000 : begin - _zz_242_ = DBusCachedPlugin_redoBranch_payload; - end - 3'b001 : begin - _zz_242_ = CsrPlugin_jumpInterface_payload; - end - 3'b010 : begin - _zz_242_ = BranchPlugin_jumpInterface_payload; - end - 3'b011 : begin - _zz_242_ = IBusCachedPlugin_redoBranch_payload; - end - default : begin - _zz_242_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - endcase - end - - `ifndef SYNTHESIS always @(*) begin - case(_zz_1_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_1__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_1__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_1__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_1__string = "JALR"; - default : _zz_1__string = "????"; + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_2__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_2__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_2__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_2__string = "JALR"; - default : _zz_2__string = "????"; + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_3_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_3__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_3__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_3__string = "PC "; - default : _zz_3__string = "???"; + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; endcase end always @(*) begin - case(_zz_4_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_4__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_4__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_4__string = "PC "; - default : _zz_4__string = "???"; + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_5__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_5__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_5__string = "PC "; - default : _zz_5__string = "???"; + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_6_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1"; - default : _zz_6__string = "?????"; + case(_zz_30) + `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; + default : _zz_30_string = "????"; endcase end always @(*) begin - case(_zz_7_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_7__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_7__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_7__string = "AND_1"; - default : _zz_7__string = "?????"; + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_8_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_8__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_8__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_8__string = "AND_1"; - default : _zz_8__string = "?????"; + case(_zz_33) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; + default : _zz_33_string = "?????????"; endcase end always @(*) begin - case(_zz_9_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_9__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9__string = "ECALL"; - default : _zz_9__string = "?????"; + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_10_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_10__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL"; - default : _zz_10__string = "?????"; + case(_zz_34) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; + default : _zz_34_string = "?????????"; endcase end always @(*) begin - case(_zz_11_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_11__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_11__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_11__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_11__string = "ECALL"; - default : _zz_11__string = "?????"; + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_12_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_12__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_12__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_12__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_12__string = "ECALL"; - default : _zz_12__string = "?????"; + case(_zz_36) + `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; + default : _zz_36_string = "???"; endcase end always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_13_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_13__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_13__string = "ECALL"; - default : _zz_13__string = "?????"; + case(_zz_37) + `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; + default : _zz_37_string = "????????????"; endcase end always @(*) begin - case(_zz_14_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_14__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_14__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_14__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_14__string = "ECALL"; - default : _zz_14__string = "?????"; + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_15_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_15__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_15__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_15__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_15__string = "ECALL"; - default : _zz_15__string = "?????"; + case(_zz_38) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; + default : _zz_38_string = "????????"; endcase end always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_16__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_16__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_16__string = "URS1 "; - default : _zz_16__string = "????????????"; + case(_zz_39) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; + default : _zz_39_string = "?????"; endcase end always @(*) begin - case(_zz_17_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_17__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_17__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_17__string = "URS1 "; - default : _zz_17__string = "????????????"; + case(_zz_43) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_18_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_18__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_18__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_18__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_18__string = "URS1 "; - default : _zz_18__string = "????????????"; + case(_zz_44) + `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; + default : _zz_44_string = "????"; endcase end always @(*) begin - case(_zz_19_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_19__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_19__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_19__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_19__string = "SRA_1 "; - default : _zz_19__string = "?????????"; + case(_zz_45) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; + default : _zz_45_string = "?????????"; endcase end always @(*) begin - case(_zz_20_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 "; - default : _zz_20__string = "?????????"; + case(_zz_46) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; + default : _zz_46_string = "?????"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(_zz_47) + `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; + default : _zz_47_string = "???"; endcase end always @(*) begin - case(_zz_21_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 "; - default : _zz_21__string = "?????????"; + case(_zz_48) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; + default : _zz_48_string = "????????"; endcase end always @(*) begin - case(_zz_22_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; - default : _zz_22__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_23_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 "; - default : _zz_23__string = "?????????"; - endcase - end - always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_24_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24__string = "BITWISE "; - default : _zz_24__string = "????????"; - endcase - end - always @(*) begin - case(_zz_25_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25__string = "BITWISE "; - default : _zz_25__string = "????????"; - endcase - end - always @(*) begin - case(_zz_26_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26__string = "BITWISE "; - default : _zz_26__string = "????????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_32_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_32__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_32__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_32__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32__string = "ECALL"; - default : _zz_32__string = "?????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; - default : execute_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_33_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33__string = "ECALL"; - default : _zz_33__string = "?????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; - default : writeBack_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_36_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_36__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_36__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_36__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_36__string = "ECALL"; - default : _zz_36__string = "?????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_39_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_39__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_39__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_39__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_39__string = "JALR"; - default : _zz_39__string = "????"; - endcase - end - always @(*) begin - case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_44_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_44__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_44__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_44__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_44__string = "SRA_1 "; - default : _zz_44__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_46_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46__string = "SRA_1 "; - default : _zz_46__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; - default : execute_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_51_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_51__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_51__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_51__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_51__string = "PC "; - default : _zz_51__string = "???"; - endcase - end - always @(*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; - default : execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_53_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_53__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_53__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_53__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_53__string = "URS1 "; - default : _zz_53__string = "????????????"; - endcase - end - always @(*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_56_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; - default : _zz_56__string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_58_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; - default : _zz_58__string = "?????"; - endcase - end - always @(*) begin - case(_zz_68_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_68__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_68__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_68__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_68__string = "JALR"; - default : _zz_68__string = "????"; - endcase - end - always @(*) begin - case(_zz_69_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_69__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_69__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_69__string = "BITWISE "; - default : _zz_69__string = "????????"; - endcase - end - always @(*) begin - case(_zz_72_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_72__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_72__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_72__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_72__string = "SRA_1 "; - default : _zz_72__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_74_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_74__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_74__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_74__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_74__string = "ECALL"; - default : _zz_74__string = "?????"; - endcase - end - always @(*) begin - case(_zz_78_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_78__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_78__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_78__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_78__string = "URS1 "; - default : _zz_78__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_82_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_82__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_82__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_82__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_82__string = "PC "; - default : _zz_82__string = "???"; - endcase - end - always @(*) begin - case(_zz_86_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_86__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_86__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_86__string = "AND_1"; - default : _zz_86__string = "?????"; + case(_zz_49) + `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; + default : _zz_49_string = "????????????"; endcase end always @(*) begin @@ -3213,73 +2263,82 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_95_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR"; - default : _zz_95__string = "????"; + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; + endcase + end + always @(*) begin + case(_zz_91) + `Src1CtrlEnum_defaultEncoding_RS : _zz_91_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_91_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_91_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_91_string = "URS1 "; + default : _zz_91_string = "????????????"; endcase end always @(*) begin - case(_zz_153_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_153__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_153__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_153__string = "AND_1"; - default : _zz_153__string = "?????"; + case(_zz_92) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_92_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_92_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_92_string = "BITWISE "; + default : _zz_92_string = "????????"; endcase end always @(*) begin - case(_zz_154_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_154__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_154__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_154__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_154__string = "PC "; - default : _zz_154__string = "???"; + case(_zz_93) + `Src2CtrlEnum_defaultEncoding_RS : _zz_93_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_93_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_93_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_93_string = "PC "; + default : _zz_93_string = "???"; endcase end always @(*) begin - case(_zz_155_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_155__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_155__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_155__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_155__string = "URS1 "; - default : _zz_155__string = "????????????"; + case(_zz_94) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_94_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_94_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_94_string = "AND_1"; + default : _zz_94_string = "?????"; endcase end always @(*) begin - case(_zz_156_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_156__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_156__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_156__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_156__string = "ECALL"; - default : _zz_156__string = "?????"; + case(_zz_95) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_95_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_95_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_95_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_95_string = "SRA_1 "; + default : _zz_95_string = "?????????"; endcase end always @(*) begin - case(_zz_157_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_157__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_157__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_157__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_157__string = "SRA_1 "; - default : _zz_157__string = "?????????"; + case(_zz_96) + `BranchCtrlEnum_defaultEncoding_INC : _zz_96_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_96_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_96_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_96_string = "JALR"; + default : _zz_96_string = "????"; endcase end always @(*) begin - case(_zz_158_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_158__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_158__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_158__string = "BITWISE "; - default : _zz_158__string = "????????"; + case(_zz_97) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_97_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_97_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_97_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_97_string = "ECALL"; + default : _zz_97_string = "?????"; endcase end always @(*) begin - case(_zz_159_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_159__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_159__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_159__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_159__string = "JALR"; - default : _zz_159__string = "????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin @@ -3290,6 +2349,23 @@ module VexRiscv ( default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end always @(*) begin case(decode_to_execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; @@ -3309,12 +2385,12 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin @@ -3344,85 +2420,60 @@ module VexRiscv ( default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; - default : decode_to_execute_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end `endif + assign memory_MUL_LOW = ($signed(_zz_242) + $signed(_zz_250)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_252; + assign execute_REGFILE_WRITE_DATA = _zz_99; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_184[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_254[0]; + assign decode_IS_RS1_SIGNED = _zz_255[0]; + assign decode_IS_DIV = _zz_256[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_66_; - assign _zz_1_ = _zz_2_; - assign decode_IS_RS2_SIGNED = _zz_87_; + assign decode_IS_MUL = _zz_257[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_258[0]; + assign _zz_8 = _zz_9; + assign _zz_10 = _zz_11; + assign decode_SHIFT_CTRL = _zz_12; + assign _zz_13 = _zz_14; + assign decode_ALU_BITWISE_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_SRC_LESS_UNSIGNED = _zz_259[0]; + assign decode_MEMORY_MANAGMENT = _zz_260[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_71_; - assign decode_SRC2_CTRL = _zz_3_; - assign _zz_4_ = _zz_5_; - assign decode_CSR_READ_OPCODE = _zz_34_; - assign decode_ALU_BITWISE_CTRL = _zz_6_; - assign _zz_7_ = _zz_8_; - assign execute_MUL_LL = _zz_31_; - assign decode_IS_CSR = _zz_85_; - assign decode_SRC_LESS_UNSIGNED = _zz_81_; - assign _zz_9_ = _zz_10_; - assign _zz_11_ = _zz_12_; - assign decode_ENV_CTRL = _zz_13_; - assign _zz_14_ = _zz_15_; - assign decode_IS_DIV = _zz_76_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_64_; - assign decode_SRC1_CTRL = _zz_16_; - assign _zz_17_ = _zz_18_; - assign decode_CSR_WRITE_OPCODE = _zz_35_; - assign decode_IS_RS1_SIGNED = _zz_80_; - assign execute_BRANCH_DO = _zz_38_; - assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = _zz_28_; - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_41_; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_90_; - assign execute_REGFILE_WRITE_DATA = _zz_57_; - assign memory_PC = execute_to_memory_PC; + assign decode_MEMORY_WR = _zz_261[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_77_; - assign execute_MUL_HL = _zz_29_; - assign memory_MUL_LOW = _zz_27_; - assign execute_SHIFT_RIGHT = _zz_45_; - assign decode_SRC2_FORCE_ZERO = _zz_55_; - assign _zz_19_ = _zz_20_; - assign decode_SHIFT_CTRL = _zz_21_; - assign _zz_22_ = _zz_23_; - assign execute_BRANCH_CALC = _zz_37_; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_262[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_263[0]; + assign decode_SRC2_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_ALU_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_SRC1_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_98_; - assign decode_MEMORY_MANAGMENT = _zz_65_; - assign execute_MUL_LH = _zz_30_; - assign decode_ALU_CTRL = _zz_24_; - assign _zz_25_ = _zz_26_; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -3436,22 +2487,22 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_32_; - assign execute_ENV_CTRL = _zz_33_; - assign writeBack_ENV_CTRL = _zz_36_; + assign memory_ENV_CTRL = _zz_27; + assign execute_ENV_CTRL = _zz_28; + assign writeBack_ENV_CTRL = _zz_29; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_40_; - assign execute_BRANCH_CTRL = _zz_39_; - assign decode_RS2_USE = _zz_70_; - assign decode_RS1_USE = _zz_75_; + assign execute_BRANCH_COND_RESULT = _zz_116; + assign execute_BRANCH_CTRL = _zz_30; + assign decode_RS2_USE = _zz_264[0]; + assign decode_RS1_USE = _zz_265[0]; always @ (*) begin - _zz_42_ = execute_REGFILE_WRITE_DATA; - if(_zz_243_)begin - _zz_42_ = execute_CsrPlugin_readData; + _zz_31 = execute_REGFILE_WRITE_DATA; + if(_zz_205)begin + _zz_31 = execute_CsrPlugin_readData; end end @@ -3462,60 +2513,60 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - decode_RS2 = _zz_62_; - if(_zz_173_)begin - if((_zz_174_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_175_; + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_244_)begin - if(_zz_245_)begin - if(_zz_177_)begin - decode_RS2 = _zz_89_; + if(_zz_206)begin + if(_zz_207)begin + if(_zz_109)begin + decode_RS2 = _zz_50; end end end - if(_zz_246_)begin + if(_zz_208)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_179_)begin - decode_RS2 = _zz_43_; + if(_zz_111)begin + decode_RS2 = _zz_32; end end end - if(_zz_247_)begin + if(_zz_209)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_181_)begin - decode_RS2 = _zz_42_; + if(_zz_113)begin + decode_RS2 = _zz_31; end end end end always @ (*) begin - decode_RS1 = _zz_63_; - if(_zz_173_)begin - if((_zz_174_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_175_; + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_244_)begin - if(_zz_245_)begin - if(_zz_176_)begin - decode_RS1 = _zz_89_; + if(_zz_206)begin + if(_zz_207)begin + if(_zz_108)begin + decode_RS1 = _zz_50; end end end - if(_zz_246_)begin + if(_zz_208)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_178_)begin - decode_RS1 = _zz_43_; + if(_zz_110)begin + decode_RS1 = _zz_32; end end end - if(_zz_247_)begin + if(_zz_209)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_180_)begin - decode_RS1 = _zz_42_; + if(_zz_112)begin + decode_RS1 = _zz_31; end end end @@ -3523,71 +2574,70 @@ module VexRiscv ( assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_43_ = memory_REGFILE_WRITE_DATA; + _zz_32 = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_43_ = _zz_169_; + _zz_32 = _zz_107; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_43_ = memory_SHIFT_RIGHT; + _zz_32 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_248_)begin - _zz_43_ = memory_DivPlugin_div_result; + if(_zz_210)begin + _zz_32 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_44_; - assign execute_SHIFT_CTRL = _zz_46_; + assign memory_SHIFT_CTRL = _zz_33; + assign execute_SHIFT_CTRL = _zz_34; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_50_ = execute_PC; - assign execute_SRC2_CTRL = _zz_51_; - assign execute_SRC1_CTRL = _zz_53_; - assign decode_SRC_USE_SUB_LESS = _zz_83_; - assign decode_SRC_ADD_ZERO = _zz_67_; - assign execute_SRC_ADD_SUB = _zz_49_; - assign execute_SRC_LESS = _zz_47_; - assign execute_ALU_CTRL = _zz_56_; - assign execute_SRC2 = _zz_52_; - assign execute_SRC1 = _zz_54_; - assign execute_ALU_BITWISE_CTRL = _zz_58_; - assign _zz_59_ = writeBack_INSTRUCTION; - assign _zz_60_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_61_ = 1'b0; + assign _zz_35 = execute_PC; + assign execute_SRC2_CTRL = _zz_36; + assign execute_SRC1_CTRL = _zz_37; + assign decode_SRC_USE_SUB_LESS = _zz_266[0]; + assign decode_SRC_ADD_ZERO = _zz_267[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_38; + assign execute_SRC2 = _zz_105; + assign execute_SRC1 = _zz_100; + assign execute_ALU_BITWISE_CTRL = _zz_39; + assign _zz_40 = writeBack_INSTRUCTION; + assign _zz_41 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_42 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_61_ = 1'b1; + _zz_42 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_94_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_73_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_268[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_88_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_338) == 32'h00001073),{(_zz_339 == _zz_340),{_zz_341,{_zz_342,_zz_343}}}}}}} != 21'h0); always @ (*) begin - _zz_89_ = writeBack_REGFILE_WRITE_DATA; + _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_89_ = writeBack_DBusCachedPlugin_rspFormated; + _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_279_) + case(_zz_241) 2'b00 : begin - _zz_89_ = _zz_348_; + _zz_50 = _zz_310; end default : begin - _zz_89_ = _zz_349_; + _zz_50 = _zz_311; end endcase end @@ -3599,62 +2649,60 @@ module VexRiscv ( assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = _zz_48_; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_79_; - assign decode_FLUSH_ALL = _zz_84_; + assign decode_MEMORY_ENABLE = _zz_269[0]; + assign decode_FLUSH_ALL = _zz_270[0]; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_91_; - if(_zz_249_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_211)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin - _zz_91_ = _zz_92_; - if(_zz_250_)begin - _zz_91_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_212)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin - _zz_92_ = _zz_93_; - if(_zz_251_)begin - _zz_92_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_213)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_93_ = 1'b0; - if(_zz_252_)begin - _zz_93_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_214)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_95_; - assign decode_INSTRUCTION = _zz_99_; + assign decode_BRANCH_CTRL = _zz_51; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_96_ = memory_FORMAL_PC_NEXT; + _zz_52 = memory_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin - _zz_96_ = BranchPlugin_jumpInterface_payload; + _zz_52 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_97_ = decode_FORMAL_PC_NEXT; + _zz_53 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_97_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_97_ = IBusCachedPlugin_redoBranch_payload; + _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; end end - assign decode_PC = _zz_100_; + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -3666,20 +2714,20 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_170_ || _zz_171_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_253_)begin + if(_zz_215)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3690,35 +2738,38 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_253_)begin + if(_zz_215)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if((_zz_238_ && (! dataCache_1__io_cpu_flush_ready)))begin + if(((_zz_200 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin - execute_arbitration_haltItself = 1'b1; - end - if(_zz_254_)begin + if(_zz_216)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_243_)begin + if(_zz_205)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end end end - assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + end + always @ (*) begin execute_arbitration_removeIt = 1'b0; if(CsrPlugin_selfException_valid)begin @@ -3739,8 +2790,8 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_248_)begin - if(_zz_255_)begin + if(_zz_210)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end end @@ -3770,7 +2821,7 @@ module VexRiscv ( always @ (*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1__io_cpu_writeBack_haltIt)begin + if(dataCache_1_io_cpu_writeBack_haltIt)begin writeBack_arbitration_haltItself = 1'b1; end end @@ -3801,10 +2852,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_256_)begin + if(_zz_217)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_257_)begin + if(_zz_218)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3815,51 +2866,49 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_256_)begin + if(_zz_217)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_257_)begin + if(_zz_218)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; end end always @ (*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin - IBusCachedPlugin_incomingInstruction = 1'b1; + CsrPlugin_inWfi = 1'b0; + if(_zz_216)begin + CsrPlugin_inWfi = 1'b1; end end + assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_256_)begin + if(_zz_217)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_257_)begin + if(_zz_218)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_256_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_217)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_257_)begin - case(_zz_258_) + if(_zz_218)begin + case(_zz_219) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3872,21 +2921,25 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); - assign _zz_101_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_102_ = (_zz_101_ & (~ _zz_280_)); - assign _zz_103_ = _zz_102_[3]; - assign _zz_104_ = _zz_102_[4]; - assign _zz_105_ = (_zz_102_[1] || _zz_103_); - assign _zz_106_ = (_zz_102_[2] || _zz_103_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_242_; - always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_54 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_55 = (_zz_54 & (~ _zz_271)); + assign _zz_56 = _zz_55[3]; + assign _zz_57 = (_zz_55[1] || _zz_56); + assign _zz_58 = (_zz_55[2] || _zz_56); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_204; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin @@ -3895,7 +2948,10 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_282_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_273); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end @@ -3903,12 +2959,28 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin @@ -3916,41 +2988,44 @@ module VexRiscv ( end end - assign _zz_107_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_107_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_107_); + assign _zz_59 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_59); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_59); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + if(IBusCachedPlugin_mmuBus_busy)begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_108_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_108_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_108_); + assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_60); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_109_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_109_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_110_; - assign _zz_110_ = ((1'b0 && (! _zz_111_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_111_ = _zz_112_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_111_; + assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_62; + assign _zz_62 = ((1'b0 && (! _zz_63)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_63 = _zz_64; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_63; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_113_ = _zz_114_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_113_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_115_; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_65)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_65 = _zz_66; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_65; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_67; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -3962,130 +3037,127 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); - assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - assign _zz_100_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - assign _zz_99_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - assign _zz_98_ = (decode_PC + (32'b00000000000000000000000000000100)); - assign _zz_116_ = _zz_283_[11]; - always @ (*) begin - _zz_117_[18] = _zz_116_; - _zz_117_[17] = _zz_116_; - _zz_117_[16] = _zz_116_; - _zz_117_[15] = _zz_116_; - _zz_117_[14] = _zz_116_; - _zz_117_[13] = _zz_116_; - _zz_117_[12] = _zz_116_; - _zz_117_[11] = _zz_116_; - _zz_117_[10] = _zz_116_; - _zz_117_[9] = _zz_116_; - _zz_117_[8] = _zz_116_; - _zz_117_[7] = _zz_116_; - _zz_117_[6] = _zz_116_; - _zz_117_[5] = _zz_116_; - _zz_117_[4] = _zz_116_; - _zz_117_[3] = _zz_116_; - _zz_117_[2] = _zz_116_; - _zz_117_[1] = _zz_116_; - _zz_117_[0] = _zz_116_; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_284_[31])); - if(_zz_122_)begin + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign _zz_68 = _zz_274[11]; + always @ (*) begin + _zz_69[18] = _zz_68; + _zz_69[17] = _zz_68; + _zz_69[16] = _zz_68; + _zz_69[15] = _zz_68; + _zz_69[14] = _zz_68; + _zz_69[13] = _zz_68; + _zz_69[12] = _zz_68; + _zz_69[11] = _zz_68; + _zz_69[10] = _zz_68; + _zz_69[9] = _zz_68; + _zz_69[8] = _zz_68; + _zz_69[7] = _zz_68; + _zz_69[6] = _zz_68; + _zz_69[5] = _zz_68; + _zz_69[4] = _zz_68; + _zz_69[3] = _zz_68; + _zz_69[2] = _zz_68; + _zz_69[1] = _zz_68; + _zz_69[0] = _zz_68; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_275[31])); + if(_zz_74)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_118_ = _zz_285_[19]; + assign _zz_70 = _zz_276[19]; always @ (*) begin - _zz_119_[10] = _zz_118_; - _zz_119_[9] = _zz_118_; - _zz_119_[8] = _zz_118_; - _zz_119_[7] = _zz_118_; - _zz_119_[6] = _zz_118_; - _zz_119_[5] = _zz_118_; - _zz_119_[4] = _zz_118_; - _zz_119_[3] = _zz_118_; - _zz_119_[2] = _zz_118_; - _zz_119_[1] = _zz_118_; - _zz_119_[0] = _zz_118_; + _zz_71[10] = _zz_70; + _zz_71[9] = _zz_70; + _zz_71[8] = _zz_70; + _zz_71[7] = _zz_70; + _zz_71[6] = _zz_70; + _zz_71[5] = _zz_70; + _zz_71[4] = _zz_70; + _zz_71[3] = _zz_70; + _zz_71[2] = _zz_70; + _zz_71[1] = _zz_70; + _zz_71[0] = _zz_70; end - assign _zz_120_ = _zz_286_[11]; + assign _zz_72 = _zz_277[11]; always @ (*) begin - _zz_121_[18] = _zz_120_; - _zz_121_[17] = _zz_120_; - _zz_121_[16] = _zz_120_; - _zz_121_[15] = _zz_120_; - _zz_121_[14] = _zz_120_; - _zz_121_[13] = _zz_120_; - _zz_121_[12] = _zz_120_; - _zz_121_[11] = _zz_120_; - _zz_121_[10] = _zz_120_; - _zz_121_[9] = _zz_120_; - _zz_121_[8] = _zz_120_; - _zz_121_[7] = _zz_120_; - _zz_121_[6] = _zz_120_; - _zz_121_[5] = _zz_120_; - _zz_121_[4] = _zz_120_; - _zz_121_[3] = _zz_120_; - _zz_121_[2] = _zz_120_; - _zz_121_[1] = _zz_120_; - _zz_121_[0] = _zz_120_; + _zz_73[18] = _zz_72; + _zz_73[17] = _zz_72; + _zz_73[16] = _zz_72; + _zz_73[15] = _zz_72; + _zz_73[14] = _zz_72; + _zz_73[13] = _zz_72; + _zz_73[12] = _zz_72; + _zz_73[11] = _zz_72; + _zz_73[10] = _zz_72; + _zz_73[9] = _zz_72; + _zz_73[8] = _zz_72; + _zz_73[7] = _zz_72; + _zz_73[6] = _zz_72; + _zz_73[5] = _zz_72; + _zz_73[4] = _zz_72; + _zz_73[3] = _zz_72; + _zz_73[2] = _zz_72; + _zz_73[1] = _zz_72; + _zz_73[0] = _zz_72; end always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_122_ = _zz_287_[1]; + _zz_74 = _zz_278[1]; end default : begin - _zz_122_ = _zz_288_[1]; + _zz_74 = _zz_279[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_123_ = _zz_289_[19]; - always @ (*) begin - _zz_124_[10] = _zz_123_; - _zz_124_[9] = _zz_123_; - _zz_124_[8] = _zz_123_; - _zz_124_[7] = _zz_123_; - _zz_124_[6] = _zz_123_; - _zz_124_[5] = _zz_123_; - _zz_124_[4] = _zz_123_; - _zz_124_[3] = _zz_123_; - _zz_124_[2] = _zz_123_; - _zz_124_[1] = _zz_123_; - _zz_124_[0] = _zz_123_; - end - - assign _zz_125_ = _zz_290_[11]; - always @ (*) begin - _zz_126_[18] = _zz_125_; - _zz_126_[17] = _zz_125_; - _zz_126_[16] = _zz_125_; - _zz_126_[15] = _zz_125_; - _zz_126_[14] = _zz_125_; - _zz_126_[13] = _zz_125_; - _zz_126_[12] = _zz_125_; - _zz_126_[11] = _zz_125_; - _zz_126_[10] = _zz_125_; - _zz_126_[9] = _zz_125_; - _zz_126_[8] = _zz_125_; - _zz_126_[7] = _zz_125_; - _zz_126_[6] = _zz_125_; - _zz_126_[5] = _zz_125_; - _zz_126_[4] = _zz_125_; - _zz_126_[3] = _zz_125_; - _zz_126_[2] = _zz_125_; - _zz_126_[1] = _zz_125_; - _zz_126_[0] = _zz_125_; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_124_,{{{_zz_376_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_126_,{{{_zz_377_,_zz_378_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_75 = _zz_280[19]; + always @ (*) begin + _zz_76[10] = _zz_75; + _zz_76[9] = _zz_75; + _zz_76[8] = _zz_75; + _zz_76[7] = _zz_75; + _zz_76[6] = _zz_75; + _zz_76[5] = _zz_75; + _zz_76[4] = _zz_75; + _zz_76[3] = _zz_75; + _zz_76[2] = _zz_75; + _zz_76[1] = _zz_75; + _zz_76[0] = _zz_75; + end + + assign _zz_77 = _zz_281[11]; + always @ (*) begin + _zz_78[18] = _zz_77; + _zz_78[17] = _zz_77; + _zz_78[16] = _zz_77; + _zz_78[15] = _zz_77; + _zz_78[14] = _zz_77; + _zz_78[13] = _zz_77; + _zz_78[12] = _zz_77; + _zz_78[11] = _zz_77; + _zz_78[10] = _zz_77; + _zz_78[9] = _zz_77; + _zz_78[8] = _zz_77; + _zz_78[7] = _zz_77; + _zz_78[6] = _zz_77; + _zz_78[5] = _zz_77; + _zz_78[4] = _zz_77; + _zz_78[3] = _zz_77; + _zz_78[2] = _zz_77; + _zz_78[1] = _zz_77; + _zz_78[0] = _zz_77; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_76,{{{_zz_356,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_78,{{{_zz_357,_zz_358},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -4094,133 +3166,128 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_222_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_225_ = (32'b00000000000000000000000000000000); - assign _zz_223_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_224_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_226_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_227_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_228_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_94_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign _zz_175 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_176 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_177 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_176; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_179 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_180 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_181 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_252_)begin + if(_zz_214)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_250_)begin + if(_zz_212)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_259_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - end end always @ (*) begin - _zz_229_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_250_)begin - _zz_229_ = 1'b1; - end - if(_zz_259_)begin - _zz_229_ = 1'b0; + _zz_182 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_212)begin + _zz_182 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_251_)begin + if(_zz_213)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_249_)begin + if(_zz_211)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_251_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); - end - if(_zz_249_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_221_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_128_); - assign _zz_239_ = (! _zz_128_); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_128_ ? _zz_129_ : dataCache_1__io_mem_cmd_payload_wr); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_128_ ? _zz_130_ : dataCache_1__io_mem_cmd_payload_address); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_128_ ? _zz_131_ : dataCache_1__io_mem_cmd_payload_data); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_128_ ? _zz_132_ : dataCache_1__io_mem_cmd_payload_mask); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_128_ ? _zz_133_ : dataCache_1__io_mem_cmd_payload_length); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_128_ ? _zz_134_ : dataCache_1__io_mem_cmd_payload_last); - assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_135_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_136_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_137_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_138_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_139_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_140_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_141_; - assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_213)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_211)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_174 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_201 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_230_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_231_ = execute_SRC_ADD; + assign _zz_183 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_184 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_143_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_81 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_143_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_81 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_143_ = execute_RS2[31 : 0]; + _zz_81 = execute_RS2[31 : 0]; end endcase end - assign _zz_238_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_90_ = _zz_231_[1 : 0]; - assign _zz_232_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_233_ = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + assign _zz_200 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_185 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_186 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_185; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_186; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_234_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin - _zz_234_ = 1'b1; + _zz_187 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_187 = 1'b1; end end - assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; - assign _zz_235_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_236_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_237_ = writeBack_REGFILE_WRITE_DATA; + assign _zz_188 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_189 = (CsrPlugin_privilege == 2'b00); + assign _zz_190 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_260_)begin - if(dataCache_1__io_cpu_redo)begin + if(_zz_220)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end @@ -4229,17 +3296,17 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_260_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin + if(_zz_220)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_redo)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end @@ -4247,94 +3314,94 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); - if(_zz_260_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_291_}; + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_220)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_282}; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_292_}; + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1__io_cpu_writeBack_mmuException)begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_283}; end end end always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; end 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; end 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; end default : begin end endcase end - assign _zz_144_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_145_[31] = _zz_144_; - _zz_145_[30] = _zz_144_; - _zz_145_[29] = _zz_144_; - _zz_145_[28] = _zz_144_; - _zz_145_[27] = _zz_144_; - _zz_145_[26] = _zz_144_; - _zz_145_[25] = _zz_144_; - _zz_145_[24] = _zz_144_; - _zz_145_[23] = _zz_144_; - _zz_145_[22] = _zz_144_; - _zz_145_[21] = _zz_144_; - _zz_145_[20] = _zz_144_; - _zz_145_[19] = _zz_144_; - _zz_145_[18] = _zz_144_; - _zz_145_[17] = _zz_144_; - _zz_145_[16] = _zz_144_; - _zz_145_[15] = _zz_144_; - _zz_145_[14] = _zz_144_; - _zz_145_[13] = _zz_144_; - _zz_145_[12] = _zz_144_; - _zz_145_[11] = _zz_144_; - _zz_145_[10] = _zz_144_; - _zz_145_[9] = _zz_144_; - _zz_145_[8] = _zz_144_; - _zz_145_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_146_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_147_[31] = _zz_146_; - _zz_147_[30] = _zz_146_; - _zz_147_[29] = _zz_146_; - _zz_147_[28] = _zz_146_; - _zz_147_[27] = _zz_146_; - _zz_147_[26] = _zz_146_; - _zz_147_[25] = _zz_146_; - _zz_147_[24] = _zz_146_; - _zz_147_[23] = _zz_146_; - _zz_147_[22] = _zz_146_; - _zz_147_[21] = _zz_146_; - _zz_147_[20] = _zz_146_; - _zz_147_[19] = _zz_146_; - _zz_147_[18] = _zz_146_; - _zz_147_[17] = _zz_146_; - _zz_147_[16] = _zz_146_; - _zz_147_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_277_) + assign _zz_82 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_83[31] = _zz_82; + _zz_83[30] = _zz_82; + _zz_83[29] = _zz_82; + _zz_83[28] = _zz_82; + _zz_83[27] = _zz_82; + _zz_83[26] = _zz_82; + _zz_83[25] = _zz_82; + _zz_83[24] = _zz_82; + _zz_83[23] = _zz_82; + _zz_83[22] = _zz_82; + _zz_83[21] = _zz_82; + _zz_83[20] = _zz_82; + _zz_83[19] = _zz_82; + _zz_83[18] = _zz_82; + _zz_83[17] = _zz_82; + _zz_83[16] = _zz_82; + _zz_83[15] = _zz_82; + _zz_83[14] = _zz_82; + _zz_83[13] = _zz_82; + _zz_83[12] = _zz_82; + _zz_83[11] = _zz_82; + _zz_83[10] = _zz_82; + _zz_83[9] = _zz_82; + _zz_83[8] = _zz_82; + _zz_83[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_84 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_85[31] = _zz_84; + _zz_85[30] = _zz_84; + _zz_85[29] = _zz_84; + _zz_85[28] = _zz_84; + _zz_85[27] = _zz_84; + _zz_85[26] = _zz_84; + _zz_85[25] = _zz_84; + _zz_85[24] = _zz_84; + _zz_85[23] = _zz_84; + _zz_85[22] = _zz_84; + _zz_85[21] = _zz_84; + _zz_85[20] = _zz_84; + _zz_85[19] = _zz_84; + _zz_85[18] = _zz_84; + _zz_85[17] = _zz_84; + _zz_85[16] = _zz_84; + _zz_85[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_239) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_145_; + writeBack_DBusCachedPlugin_rspFormated = _zz_83; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_147_; + writeBack_DBusCachedPlugin_rspFormated = _zz_85; end default : begin writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; @@ -4342,77 +3409,71 @@ module VexRiscv ( endcase end - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_149_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); - assign _zz_150_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_151_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_152_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_148_ = {({_zz_150_,{_zz_379_,{_zz_380_,_zz_381_}}} != (5'b00000)),{((_zz_382_ == _zz_383_) != (1'b0)),{(_zz_384_ != (1'b0)),{(_zz_385_ != _zz_386_),{_zz_387_,{_zz_388_,_zz_389_}}}}}}; - assign _zz_88_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_542_) == (32'b00000000000000000001000001110011)),{(_zz_543_ == _zz_544_),{_zz_545_,{_zz_546_,_zz_547_}}}}}}} != (21'b000000000000000000000)); - assign _zz_87_ = _zz_293_[0]; - assign _zz_153_ = _zz_148_[2 : 1]; - assign _zz_86_ = _zz_153_; - assign _zz_85_ = _zz_294_[0]; - assign _zz_84_ = _zz_295_[0]; - assign _zz_83_ = _zz_296_[0]; - assign _zz_154_ = _zz_148_[7 : 6]; - assign _zz_82_ = _zz_154_; - assign _zz_81_ = _zz_297_[0]; - assign _zz_80_ = _zz_298_[0]; - assign _zz_79_ = _zz_299_[0]; - assign _zz_155_ = _zz_148_[12 : 11]; - assign _zz_78_ = _zz_155_; - assign _zz_77_ = _zz_300_[0]; - assign _zz_76_ = _zz_301_[0]; - assign _zz_75_ = _zz_302_[0]; - assign _zz_156_ = _zz_148_[17 : 16]; - assign _zz_74_ = _zz_156_; - assign _zz_73_ = _zz_303_[0]; - assign _zz_157_ = _zz_148_[20 : 19]; - assign _zz_72_ = _zz_157_; - assign _zz_71_ = _zz_304_[0]; - assign _zz_70_ = _zz_305_[0]; - assign _zz_158_ = _zz_148_[24 : 23]; - assign _zz_69_ = _zz_158_; - assign _zz_159_ = _zz_148_[27 : 26]; - assign _zz_68_ = _zz_159_; - assign _zz_67_ = _zz_306_[0]; - assign _zz_66_ = _zz_307_[0]; - assign _zz_65_ = _zz_308_[0]; - assign _zz_64_ = _zz_309_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign _zz_87 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_88 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_89 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_90 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_86 = {(_zz_90 != 1'b0),{(_zz_90 != 1'b0),{((_zz_359 == _zz_360) != 1'b0),{(_zz_361 != 1'b0),{(_zz_362 != _zz_363),{_zz_364,{_zz_365,_zz_366}}}}}}}; + assign _zz_91 = _zz_86[2 : 1]; + assign _zz_49 = _zz_91; + assign _zz_92 = _zz_86[7 : 6]; + assign _zz_48 = _zz_92; + assign _zz_93 = _zz_86[9 : 8]; + assign _zz_47 = _zz_93; + assign _zz_94 = _zz_86[19 : 18]; + assign _zz_46 = _zz_94; + assign _zz_95 = _zz_86[22 : 21]; + assign _zz_45 = _zz_95; + assign _zz_96 = _zz_86[24 : 23]; + assign _zz_44 = _zz_96; + assign _zz_97 = _zz_86[27 : 26]; + assign _zz_43 = _zz_97; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_240_; - assign decode_RegFilePlugin_rs2Data = _zz_241_; - assign _zz_63_ = decode_RegFilePlugin_rs1Data; - assign _zz_62_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_202; + assign decode_RegFilePlugin_rs2Data = _zz_203; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_60_ && writeBack_arbitration_isFiring); - if(_zz_160_)begin + lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); + if(_zz_98)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_59_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_89_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; + if(_zz_98)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_50; + if(_zz_98)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -4430,361 +3491,354 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_161_ = execute_IntAluPlugin_bitwise; + _zz_99 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_161_ = {31'd0, _zz_310_}; + _zz_99 = {31'd0, _zz_284}; end default : begin - _zz_161_ = execute_SRC_ADD_SUB; + _zz_99 = execute_SRC_ADD_SUB; end endcase end - assign _zz_57_ = _zz_161_; - assign _zz_55_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_162_ = execute_RS1; + _zz_100 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_162_ = {29'd0, _zz_311_}; + _zz_100 = {29'd0, _zz_285}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_162_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_162_ = {27'd0, _zz_312_}; + _zz_100 = {27'd0, _zz_286}; end endcase end - assign _zz_54_ = _zz_162_; - assign _zz_163_ = _zz_313_[11]; - always @ (*) begin - _zz_164_[19] = _zz_163_; - _zz_164_[18] = _zz_163_; - _zz_164_[17] = _zz_163_; - _zz_164_[16] = _zz_163_; - _zz_164_[15] = _zz_163_; - _zz_164_[14] = _zz_163_; - _zz_164_[13] = _zz_163_; - _zz_164_[12] = _zz_163_; - _zz_164_[11] = _zz_163_; - _zz_164_[10] = _zz_163_; - _zz_164_[9] = _zz_163_; - _zz_164_[8] = _zz_163_; - _zz_164_[7] = _zz_163_; - _zz_164_[6] = _zz_163_; - _zz_164_[5] = _zz_163_; - _zz_164_[4] = _zz_163_; - _zz_164_[3] = _zz_163_; - _zz_164_[2] = _zz_163_; - _zz_164_[1] = _zz_163_; - _zz_164_[0] = _zz_163_; - end - - assign _zz_165_ = _zz_314_[11]; - always @ (*) begin - _zz_166_[19] = _zz_165_; - _zz_166_[18] = _zz_165_; - _zz_166_[17] = _zz_165_; - _zz_166_[16] = _zz_165_; - _zz_166_[15] = _zz_165_; - _zz_166_[14] = _zz_165_; - _zz_166_[13] = _zz_165_; - _zz_166_[12] = _zz_165_; - _zz_166_[11] = _zz_165_; - _zz_166_[10] = _zz_165_; - _zz_166_[9] = _zz_165_; - _zz_166_[8] = _zz_165_; - _zz_166_[7] = _zz_165_; - _zz_166_[6] = _zz_165_; - _zz_166_[5] = _zz_165_; - _zz_166_[4] = _zz_165_; - _zz_166_[3] = _zz_165_; - _zz_166_[2] = _zz_165_; - _zz_166_[1] = _zz_165_; - _zz_166_[0] = _zz_165_; + assign _zz_101 = _zz_287[11]; + always @ (*) begin + _zz_102[19] = _zz_101; + _zz_102[18] = _zz_101; + _zz_102[17] = _zz_101; + _zz_102[16] = _zz_101; + _zz_102[15] = _zz_101; + _zz_102[14] = _zz_101; + _zz_102[13] = _zz_101; + _zz_102[12] = _zz_101; + _zz_102[11] = _zz_101; + _zz_102[10] = _zz_101; + _zz_102[9] = _zz_101; + _zz_102[8] = _zz_101; + _zz_102[7] = _zz_101; + _zz_102[6] = _zz_101; + _zz_102[5] = _zz_101; + _zz_102[4] = _zz_101; + _zz_102[3] = _zz_101; + _zz_102[2] = _zz_101; + _zz_102[1] = _zz_101; + _zz_102[0] = _zz_101; + end + + assign _zz_103 = _zz_288[11]; + always @ (*) begin + _zz_104[19] = _zz_103; + _zz_104[18] = _zz_103; + _zz_104[17] = _zz_103; + _zz_104[16] = _zz_103; + _zz_104[15] = _zz_103; + _zz_104[14] = _zz_103; + _zz_104[13] = _zz_103; + _zz_104[12] = _zz_103; + _zz_104[11] = _zz_103; + _zz_104[10] = _zz_103; + _zz_104[9] = _zz_103; + _zz_104[8] = _zz_103; + _zz_104[7] = _zz_103; + _zz_104[6] = _zz_103; + _zz_104[5] = _zz_103; + _zz_104[4] = _zz_103; + _zz_104[3] = _zz_103; + _zz_104[2] = _zz_103; + _zz_104[1] = _zz_103; + _zz_104[0] = _zz_103; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_167_ = execute_RS2; + _zz_105 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_167_ = {_zz_164_,execute_INSTRUCTION[31 : 20]}; + _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_167_ = {_zz_166_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_105 = {_zz_104,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_167_ = _zz_50_; + _zz_105 = _zz_35; end endcase end - assign _zz_52_ = _zz_167_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_315_; + execute_SrcPlugin_addSub = _zz_289; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_49_ = execute_SrcPlugin_addSub; - assign _zz_48_ = execute_SrcPlugin_addSub; - assign _zz_47_ = execute_SrcPlugin_less; assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_168_[0] = execute_SRC1[31]; - _zz_168_[1] = execute_SRC1[30]; - _zz_168_[2] = execute_SRC1[29]; - _zz_168_[3] = execute_SRC1[28]; - _zz_168_[4] = execute_SRC1[27]; - _zz_168_[5] = execute_SRC1[26]; - _zz_168_[6] = execute_SRC1[25]; - _zz_168_[7] = execute_SRC1[24]; - _zz_168_[8] = execute_SRC1[23]; - _zz_168_[9] = execute_SRC1[22]; - _zz_168_[10] = execute_SRC1[21]; - _zz_168_[11] = execute_SRC1[20]; - _zz_168_[12] = execute_SRC1[19]; - _zz_168_[13] = execute_SRC1[18]; - _zz_168_[14] = execute_SRC1[17]; - _zz_168_[15] = execute_SRC1[16]; - _zz_168_[16] = execute_SRC1[15]; - _zz_168_[17] = execute_SRC1[14]; - _zz_168_[18] = execute_SRC1[13]; - _zz_168_[19] = execute_SRC1[12]; - _zz_168_[20] = execute_SRC1[11]; - _zz_168_[21] = execute_SRC1[10]; - _zz_168_[22] = execute_SRC1[9]; - _zz_168_[23] = execute_SRC1[8]; - _zz_168_[24] = execute_SRC1[7]; - _zz_168_[25] = execute_SRC1[6]; - _zz_168_[26] = execute_SRC1[5]; - _zz_168_[27] = execute_SRC1[4]; - _zz_168_[28] = execute_SRC1[3]; - _zz_168_[29] = execute_SRC1[2]; - _zz_168_[30] = execute_SRC1[1]; - _zz_168_[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_168_ : execute_SRC1); - assign _zz_45_ = _zz_323_; - always @ (*) begin - _zz_169_[0] = memory_SHIFT_RIGHT[31]; - _zz_169_[1] = memory_SHIFT_RIGHT[30]; - _zz_169_[2] = memory_SHIFT_RIGHT[29]; - _zz_169_[3] = memory_SHIFT_RIGHT[28]; - _zz_169_[4] = memory_SHIFT_RIGHT[27]; - _zz_169_[5] = memory_SHIFT_RIGHT[26]; - _zz_169_[6] = memory_SHIFT_RIGHT[25]; - _zz_169_[7] = memory_SHIFT_RIGHT[24]; - _zz_169_[8] = memory_SHIFT_RIGHT[23]; - _zz_169_[9] = memory_SHIFT_RIGHT[22]; - _zz_169_[10] = memory_SHIFT_RIGHT[21]; - _zz_169_[11] = memory_SHIFT_RIGHT[20]; - _zz_169_[12] = memory_SHIFT_RIGHT[19]; - _zz_169_[13] = memory_SHIFT_RIGHT[18]; - _zz_169_[14] = memory_SHIFT_RIGHT[17]; - _zz_169_[15] = memory_SHIFT_RIGHT[16]; - _zz_169_[16] = memory_SHIFT_RIGHT[15]; - _zz_169_[17] = memory_SHIFT_RIGHT[14]; - _zz_169_[18] = memory_SHIFT_RIGHT[13]; - _zz_169_[19] = memory_SHIFT_RIGHT[12]; - _zz_169_[20] = memory_SHIFT_RIGHT[11]; - _zz_169_[21] = memory_SHIFT_RIGHT[10]; - _zz_169_[22] = memory_SHIFT_RIGHT[9]; - _zz_169_[23] = memory_SHIFT_RIGHT[8]; - _zz_169_[24] = memory_SHIFT_RIGHT[7]; - _zz_169_[25] = memory_SHIFT_RIGHT[6]; - _zz_169_[26] = memory_SHIFT_RIGHT[5]; - _zz_169_[27] = memory_SHIFT_RIGHT[4]; - _zz_169_[28] = memory_SHIFT_RIGHT[3]; - _zz_169_[29] = memory_SHIFT_RIGHT[2]; - _zz_169_[30] = memory_SHIFT_RIGHT[1]; - _zz_169_[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_170_ = 1'b0; - if(_zz_261_)begin - if(_zz_262_)begin - if(_zz_176_)begin - _zz_170_ = 1'b1; + _zz_106[0] = execute_SRC1[31]; + _zz_106[1] = execute_SRC1[30]; + _zz_106[2] = execute_SRC1[29]; + _zz_106[3] = execute_SRC1[28]; + _zz_106[4] = execute_SRC1[27]; + _zz_106[5] = execute_SRC1[26]; + _zz_106[6] = execute_SRC1[25]; + _zz_106[7] = execute_SRC1[24]; + _zz_106[8] = execute_SRC1[23]; + _zz_106[9] = execute_SRC1[22]; + _zz_106[10] = execute_SRC1[21]; + _zz_106[11] = execute_SRC1[20]; + _zz_106[12] = execute_SRC1[19]; + _zz_106[13] = execute_SRC1[18]; + _zz_106[14] = execute_SRC1[17]; + _zz_106[15] = execute_SRC1[16]; + _zz_106[16] = execute_SRC1[15]; + _zz_106[17] = execute_SRC1[14]; + _zz_106[18] = execute_SRC1[13]; + _zz_106[19] = execute_SRC1[12]; + _zz_106[20] = execute_SRC1[11]; + _zz_106[21] = execute_SRC1[10]; + _zz_106[22] = execute_SRC1[9]; + _zz_106[23] = execute_SRC1[8]; + _zz_106[24] = execute_SRC1[7]; + _zz_106[25] = execute_SRC1[6]; + _zz_106[26] = execute_SRC1[5]; + _zz_106[27] = execute_SRC1[4]; + _zz_106[28] = execute_SRC1[3]; + _zz_106[29] = execute_SRC1[2]; + _zz_106[30] = execute_SRC1[1]; + _zz_106[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_106 : execute_SRC1); + always @ (*) begin + _zz_107[0] = memory_SHIFT_RIGHT[31]; + _zz_107[1] = memory_SHIFT_RIGHT[30]; + _zz_107[2] = memory_SHIFT_RIGHT[29]; + _zz_107[3] = memory_SHIFT_RIGHT[28]; + _zz_107[4] = memory_SHIFT_RIGHT[27]; + _zz_107[5] = memory_SHIFT_RIGHT[26]; + _zz_107[6] = memory_SHIFT_RIGHT[25]; + _zz_107[7] = memory_SHIFT_RIGHT[24]; + _zz_107[8] = memory_SHIFT_RIGHT[23]; + _zz_107[9] = memory_SHIFT_RIGHT[22]; + _zz_107[10] = memory_SHIFT_RIGHT[21]; + _zz_107[11] = memory_SHIFT_RIGHT[20]; + _zz_107[12] = memory_SHIFT_RIGHT[19]; + _zz_107[13] = memory_SHIFT_RIGHT[18]; + _zz_107[14] = memory_SHIFT_RIGHT[17]; + _zz_107[15] = memory_SHIFT_RIGHT[16]; + _zz_107[16] = memory_SHIFT_RIGHT[15]; + _zz_107[17] = memory_SHIFT_RIGHT[14]; + _zz_107[18] = memory_SHIFT_RIGHT[13]; + _zz_107[19] = memory_SHIFT_RIGHT[12]; + _zz_107[20] = memory_SHIFT_RIGHT[11]; + _zz_107[21] = memory_SHIFT_RIGHT[10]; + _zz_107[22] = memory_SHIFT_RIGHT[9]; + _zz_107[23] = memory_SHIFT_RIGHT[8]; + _zz_107[24] = memory_SHIFT_RIGHT[7]; + _zz_107[25] = memory_SHIFT_RIGHT[6]; + _zz_107[26] = memory_SHIFT_RIGHT[5]; + _zz_107[27] = memory_SHIFT_RIGHT[4]; + _zz_107[28] = memory_SHIFT_RIGHT[3]; + _zz_107[29] = memory_SHIFT_RIGHT[2]; + _zz_107[30] = memory_SHIFT_RIGHT[1]; + _zz_107[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_221)begin + if(_zz_222)begin + if(_zz_108)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_263_)begin - if(_zz_264_)begin - if(_zz_178_)begin - _zz_170_ = 1'b1; + if(_zz_223)begin + if(_zz_224)begin + if(_zz_110)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_265_)begin - if(_zz_266_)begin - if(_zz_180_)begin - _zz_170_ = 1'b1; + if(_zz_225)begin + if(_zz_226)begin + if(_zz_112)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_170_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_171_ = 1'b0; - if(_zz_261_)begin - if(_zz_262_)begin - if(_zz_177_)begin - _zz_171_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_221)begin + if(_zz_222)begin + if(_zz_109)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_263_)begin - if(_zz_264_)begin - if(_zz_179_)begin - _zz_171_ = 1'b1; + if(_zz_223)begin + if(_zz_224)begin + if(_zz_111)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_265_)begin - if(_zz_266_)begin - if(_zz_181_)begin - _zz_171_ = 1'b1; + if(_zz_225)begin + if(_zz_226)begin + if(_zz_113)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_171_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_172_ = (_zz_60_ && writeBack_arbitration_isFiring); - assign _zz_176_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_177_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_178_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_179_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_180_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_181_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_41_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_108 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_109 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_110 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_111 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_112 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_113 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_182_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_182_ == (3'b000))) begin - _zz_183_ = execute_BranchPlugin_eq; - end else if((_zz_182_ == (3'b001))) begin - _zz_183_ = (! execute_BranchPlugin_eq); - end else if((((_zz_182_ & (3'b101)) == (3'b101)))) begin - _zz_183_ = (! execute_SRC_LESS); + assign _zz_114 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_114 == 3'b000)) begin + _zz_115 = execute_BranchPlugin_eq; + end else if((_zz_114 == 3'b001)) begin + _zz_115 = (! execute_BranchPlugin_eq); + end else if((((_zz_114 & 3'b101) == 3'b101))) begin + _zz_115 = (! execute_SRC_LESS); end else begin - _zz_183_ = execute_SRC_LESS; + _zz_115 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_184_ = 1'b0; + _zz_116 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_184_ = 1'b1; + _zz_116 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_184_ = 1'b1; + _zz_116 = 1'b1; end default : begin - _zz_184_ = _zz_183_; + _zz_116 = _zz_115; end endcase end - assign _zz_40_ = _zz_184_; - assign _zz_185_ = _zz_325_[11]; - always @ (*) begin - _zz_186_[19] = _zz_185_; - _zz_186_[18] = _zz_185_; - _zz_186_[17] = _zz_185_; - _zz_186_[16] = _zz_185_; - _zz_186_[15] = _zz_185_; - _zz_186_[14] = _zz_185_; - _zz_186_[13] = _zz_185_; - _zz_186_[12] = _zz_185_; - _zz_186_[11] = _zz_185_; - _zz_186_[10] = _zz_185_; - _zz_186_[9] = _zz_185_; - _zz_186_[8] = _zz_185_; - _zz_186_[7] = _zz_185_; - _zz_186_[6] = _zz_185_; - _zz_186_[5] = _zz_185_; - _zz_186_[4] = _zz_185_; - _zz_186_[3] = _zz_185_; - _zz_186_[2] = _zz_185_; - _zz_186_[1] = _zz_185_; - _zz_186_[0] = _zz_185_; - end - - assign _zz_187_ = _zz_326_[19]; - always @ (*) begin - _zz_188_[10] = _zz_187_; - _zz_188_[9] = _zz_187_; - _zz_188_[8] = _zz_187_; - _zz_188_[7] = _zz_187_; - _zz_188_[6] = _zz_187_; - _zz_188_[5] = _zz_187_; - _zz_188_[4] = _zz_187_; - _zz_188_[3] = _zz_187_; - _zz_188_[2] = _zz_187_; - _zz_188_[1] = _zz_187_; - _zz_188_[0] = _zz_187_; - end - - assign _zz_189_ = _zz_327_[11]; - always @ (*) begin - _zz_190_[18] = _zz_189_; - _zz_190_[17] = _zz_189_; - _zz_190_[16] = _zz_189_; - _zz_190_[15] = _zz_189_; - _zz_190_[14] = _zz_189_; - _zz_190_[13] = _zz_189_; - _zz_190_[12] = _zz_189_; - _zz_190_[11] = _zz_189_; - _zz_190_[10] = _zz_189_; - _zz_190_[9] = _zz_189_; - _zz_190_[8] = _zz_189_; - _zz_190_[7] = _zz_189_; - _zz_190_[6] = _zz_189_; - _zz_190_[5] = _zz_189_; - _zz_190_[4] = _zz_189_; - _zz_190_[3] = _zz_189_; - _zz_190_[2] = _zz_189_; - _zz_190_[1] = _zz_189_; - _zz_190_[0] = _zz_189_; + assign _zz_117 = _zz_296[11]; + always @ (*) begin + _zz_118[19] = _zz_117; + _zz_118[18] = _zz_117; + _zz_118[17] = _zz_117; + _zz_118[16] = _zz_117; + _zz_118[15] = _zz_117; + _zz_118[14] = _zz_117; + _zz_118[13] = _zz_117; + _zz_118[12] = _zz_117; + _zz_118[11] = _zz_117; + _zz_118[10] = _zz_117; + _zz_118[9] = _zz_117; + _zz_118[8] = _zz_117; + _zz_118[7] = _zz_117; + _zz_118[6] = _zz_117; + _zz_118[5] = _zz_117; + _zz_118[4] = _zz_117; + _zz_118[3] = _zz_117; + _zz_118[2] = _zz_117; + _zz_118[1] = _zz_117; + _zz_118[0] = _zz_117; + end + + assign _zz_119 = _zz_297[19]; + always @ (*) begin + _zz_120[10] = _zz_119; + _zz_120[9] = _zz_119; + _zz_120[8] = _zz_119; + _zz_120[7] = _zz_119; + _zz_120[6] = _zz_119; + _zz_120[5] = _zz_119; + _zz_120[4] = _zz_119; + _zz_120[3] = _zz_119; + _zz_120[2] = _zz_119; + _zz_120[1] = _zz_119; + _zz_120[0] = _zz_119; + end + + assign _zz_121 = _zz_298[11]; + always @ (*) begin + _zz_122[18] = _zz_121; + _zz_122[17] = _zz_121; + _zz_122[16] = _zz_121; + _zz_122[15] = _zz_121; + _zz_122[14] = _zz_121; + _zz_122[13] = _zz_121; + _zz_122[12] = _zz_121; + _zz_122[11] = _zz_121; + _zz_122[10] = _zz_121; + _zz_122[9] = _zz_121; + _zz_122[8] = _zz_121; + _zz_122[7] = _zz_121; + _zz_122[6] = _zz_121; + _zz_122[5] = _zz_121; + _zz_122[4] = _zz_121; + _zz_122[3] = _zz_121; + _zz_122[2] = _zz_121; + _zz_122[1] = _zz_121; + _zz_122[0] = _zz_121; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_191_ = (_zz_328_[1] ^ execute_RS1[1]); + _zz_123 = (_zz_299[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_191_ = _zz_329_[1]; + _zz_123 = _zz_300[1]; end default : begin - _zz_191_ = _zz_330_[1]; + _zz_123 = _zz_301[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_191_); - assign _zz_38_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_123); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4796,107 +3850,106 @@ module VexRiscv ( endcase end - assign _zz_192_ = _zz_331_[11]; + assign _zz_124 = _zz_302[11]; always @ (*) begin - _zz_193_[19] = _zz_192_; - _zz_193_[18] = _zz_192_; - _zz_193_[17] = _zz_192_; - _zz_193_[16] = _zz_192_; - _zz_193_[15] = _zz_192_; - _zz_193_[14] = _zz_192_; - _zz_193_[13] = _zz_192_; - _zz_193_[12] = _zz_192_; - _zz_193_[11] = _zz_192_; - _zz_193_[10] = _zz_192_; - _zz_193_[9] = _zz_192_; - _zz_193_[8] = _zz_192_; - _zz_193_[7] = _zz_192_; - _zz_193_[6] = _zz_192_; - _zz_193_[5] = _zz_192_; - _zz_193_[4] = _zz_192_; - _zz_193_[3] = _zz_192_; - _zz_193_[2] = _zz_192_; - _zz_193_[1] = _zz_192_; - _zz_193_[0] = _zz_192_; + _zz_125[19] = _zz_124; + _zz_125[18] = _zz_124; + _zz_125[17] = _zz_124; + _zz_125[16] = _zz_124; + _zz_125[15] = _zz_124; + _zz_125[14] = _zz_124; + _zz_125[13] = _zz_124; + _zz_125[12] = _zz_124; + _zz_125[11] = _zz_124; + _zz_125[10] = _zz_124; + _zz_125[9] = _zz_124; + _zz_125[8] = _zz_124; + _zz_125[7] = _zz_124; + _zz_125[6] = _zz_124; + _zz_125[5] = _zz_124; + _zz_125[4] = _zz_124; + _zz_125[3] = _zz_124; + _zz_125[2] = _zz_124; + _zz_125[1] = _zz_124; + _zz_125[0] = _zz_124; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_193_,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_125,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_195_,{{{_zz_560_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_197_,{{{_zz_561_,_zz_562_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_127,{{{_zz_523,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_129,{{{_zz_524,_zz_525},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_334_}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_305}; end end endcase end - assign _zz_194_ = _zz_332_[19]; - always @ (*) begin - _zz_195_[10] = _zz_194_; - _zz_195_[9] = _zz_194_; - _zz_195_[8] = _zz_194_; - _zz_195_[7] = _zz_194_; - _zz_195_[6] = _zz_194_; - _zz_195_[5] = _zz_194_; - _zz_195_[4] = _zz_194_; - _zz_195_[3] = _zz_194_; - _zz_195_[2] = _zz_194_; - _zz_195_[1] = _zz_194_; - _zz_195_[0] = _zz_194_; - end - - assign _zz_196_ = _zz_333_[11]; - always @ (*) begin - _zz_197_[18] = _zz_196_; - _zz_197_[17] = _zz_196_; - _zz_197_[16] = _zz_196_; - _zz_197_[15] = _zz_196_; - _zz_197_[14] = _zz_196_; - _zz_197_[13] = _zz_196_; - _zz_197_[12] = _zz_196_; - _zz_197_[11] = _zz_196_; - _zz_197_[10] = _zz_196_; - _zz_197_[9] = _zz_196_; - _zz_197_[8] = _zz_196_; - _zz_197_[7] = _zz_196_; - _zz_197_[6] = _zz_196_; - _zz_197_[5] = _zz_196_; - _zz_197_[4] = _zz_196_; - _zz_197_[3] = _zz_196_; - _zz_197_[2] = _zz_196_; - _zz_197_[1] = _zz_196_; - _zz_197_[0] = _zz_196_; + assign _zz_126 = _zz_303[19]; + always @ (*) begin + _zz_127[10] = _zz_126; + _zz_127[9] = _zz_126; + _zz_127[8] = _zz_126; + _zz_127[7] = _zz_126; + _zz_127[6] = _zz_126; + _zz_127[5] = _zz_126; + _zz_127[4] = _zz_126; + _zz_127[3] = _zz_126; + _zz_127[2] = _zz_126; + _zz_127[1] = _zz_126; + _zz_127[0] = _zz_126; + end + + assign _zz_128 = _zz_304[11]; + always @ (*) begin + _zz_129[18] = _zz_128; + _zz_129[17] = _zz_128; + _zz_129[16] = _zz_128; + _zz_129[15] = _zz_128; + _zz_129[14] = _zz_128; + _zz_129[13] = _zz_128; + _zz_129[12] = _zz_128; + _zz_129[11] = _zz_128; + _zz_129[10] = _zz_128; + _zz_129[9] = _zz_128; + _zz_129[8] = _zz_128; + _zz_129[7] = _zz_128; + _zz_129[6] = _zz_128; + _zz_129[5] = _zz_128; + _zz_129[4] = _zz_128; + _zz_129[3] = _zz_128; + _zz_129[2] = _zz_128; + _zz_129[1] = _zz_128; + _zz_129[0] = _zz_128; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_37_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign _zz_198_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_199_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_200_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign _zz_130 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_131 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_132 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_201_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_202_ = _zz_335_[0]; + assign _zz_133 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_134 = _zz_306[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_253_)begin + if(_zz_215)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4939,9 +3992,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -4965,7 +4019,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; @@ -4976,7 +4030,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4987,105 +4041,102 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_35_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_34_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - always @ (*) begin - execute_CsrPlugin_inWfi = 1'b0; - if(_zz_254_)begin - execute_CsrPlugin_inWfi = 1'b1; - end - end - - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b111100010001 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111100010100 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000001 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b101100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b101110000000 : begin + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110011000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b101100000010 : begin + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000011 : begin + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b110000000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000001 : begin + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000000 : begin + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b101110000010 : begin + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110010000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_227)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -5104,26 +4155,26 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_267_)begin + if(_zz_228)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_268_)begin + if(_zz_229)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_267_)begin - CsrPlugin_selfException_payload_code = (4'b0010); + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_228)begin + CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_268_)begin + if(_zz_229)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -5131,95 +4182,24 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_210_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b111100010001 : begin - execute_CsrPlugin_readData[3 : 0] = (4'b1011); - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b101100000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0]; - end - 12'b101110000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[63 : 32]; - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b001100000101 : begin - execute_CsrPlugin_readData[31 : 2] = CsrPlugin_mtvec_base; - execute_CsrPlugin_readData[1 : 0] = CsrPlugin_mtvec_mode; - end - 12'b110011000000 : begin - execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); - execute_CsrPlugin_readData[25 : 20] = (6'b100000); - end - 12'b101100000010 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[31 : 0]; - end - 12'b111100010011 : begin - execute_CsrPlugin_readData[5 : 0] = (6'b100001); - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_211_; - end - 12'b110000000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0]; - end - 12'b001100000001 : begin - execute_CsrPlugin_readData[31 : 30] = CsrPlugin_misa_base; - execute_CsrPlugin_readData[25 : 0] = CsrPlugin_misa_extensions; - end - 12'b001101000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; - end - 12'b111100010010 : begin - execute_CsrPlugin_readData[4 : 0] = (5'b10110); - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - end - 12'b101110000010 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[63 : 32]; - end - 12'b110010000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[63 : 32]; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_227)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_227)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_278_) + case(_zz_240) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -5230,10 +4210,10 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_MulPlugin_a = execute_SRC1; - assign execute_MulPlugin_b = execute_SRC2; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_269_) + case(_zz_230) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -5247,7 +4227,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_269_) + case(_zz_230) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -5266,16 +4246,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign _zz_31_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign _zz_30_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - assign _zz_28_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - assign _zz_27_ = ($signed(_zz_337_) + $signed(_zz_345_)); - assign writeBack_MulPlugin_result = ($signed(_zz_346_) + $signed(_zz_347_)); + assign writeBack_MulPlugin_result = ($signed(_zz_308) + $signed(_zz_309)); + assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_248_)begin - if(_zz_255_)begin + if(_zz_210)begin + if(_zz_231)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -5283,68 +4259,70 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_270_)begin + if(_zz_232)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end - assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); always @ (*) begin if(memory_DivPlugin_div_counter_willOverflow)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_351_); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_313); end if(memory_DivPlugin_div_counter_willClear)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); - end - end - - assign _zz_203_ = memory_DivPlugin_rs1[31 : 0]; - assign _zz_204_ = {memory_DivPlugin_accumulator[31 : 0],_zz_203_[31]}; - assign _zz_205_ = (_zz_204_ - _zz_352_); - assign _zz_206_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_207_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_208_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_209_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_209_[31 : 0] = execute_RS1; - end - - assign _zz_211_ = (_zz_210_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_211_ != (32'b00000000000000000000000000000000)); - assign _zz_26_ = decode_ALU_CTRL; - assign _zz_24_ = _zz_69_; - assign _zz_56_ = decode_to_execute_ALU_CTRL; - assign _zz_23_ = decode_SHIFT_CTRL; - assign _zz_20_ = execute_SHIFT_CTRL; - assign _zz_21_ = _zz_72_; - assign _zz_46_ = decode_to_execute_SHIFT_CTRL; - assign _zz_44_ = execute_to_memory_SHIFT_CTRL; - assign _zz_18_ = decode_SRC1_CTRL; - assign _zz_16_ = _zz_78_; - assign _zz_53_ = decode_to_execute_SRC1_CTRL; - assign _zz_15_ = decode_ENV_CTRL; - assign _zz_12_ = execute_ENV_CTRL; - assign _zz_10_ = memory_ENV_CTRL; - assign _zz_13_ = _zz_74_; - assign _zz_33_ = decode_to_execute_ENV_CTRL; - assign _zz_32_ = execute_to_memory_ENV_CTRL; - assign _zz_36_ = memory_to_writeBack_ENV_CTRL; - assign _zz_8_ = decode_ALU_BITWISE_CTRL; - assign _zz_6_ = _zz_86_; - assign _zz_58_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_5_ = decode_SRC2_CTRL; - assign _zz_3_ = _zz_82_; - assign _zz_51_ = decode_to_execute_SRC2_CTRL; - assign _zz_2_ = decode_BRANCH_CTRL; - assign _zz_95_ = _zz_68_; - assign _zz_39_ = decode_to_execute_BRANCH_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_135 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_135[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_314); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_315 : _zz_316); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_317[31:0]; + assign _zz_136 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_137 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_138 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_139[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_139[31 : 0] = execute_RS1; + end + + assign _zz_141 = (_zz_140 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_141 != 32'h0); + assign _zz_26 = decode_SRC1_CTRL; + assign _zz_24 = _zz_49; + assign _zz_37 = decode_to_execute_SRC1_CTRL; + assign _zz_23 = decode_ALU_CTRL; + assign _zz_21 = _zz_48; + assign _zz_38 = decode_to_execute_ALU_CTRL; + assign _zz_20 = decode_SRC2_CTRL; + assign _zz_18 = _zz_47; + assign _zz_36 = decode_to_execute_SRC2_CTRL; + assign _zz_17 = decode_ALU_BITWISE_CTRL; + assign _zz_15 = _zz_46; + assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_14 = decode_SHIFT_CTRL; + assign _zz_11 = execute_SHIFT_CTRL; + assign _zz_12 = _zz_45; + assign _zz_34 = decode_to_execute_SHIFT_CTRL; + assign _zz_33 = execute_to_memory_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_51 = _zz_44; + assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_43; + assign _zz_28 = decode_to_execute_ENV_CTRL; + assign _zz_27 = execute_to_memory_ENV_CTRL; + assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -5361,73 +4339,245 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign iBusWishbone_ADR = {_zz_372_,_zz_212_}; - assign iBusWishbone_CTI = ((_zz_212_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); + always @ (*) begin + _zz_142 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_142[12 : 0] = 13'h1000; + _zz_142[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_143 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_143[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_144 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_144[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_145 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_145[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_146 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_146[31 : 30] = CsrPlugin_misa_base; + _zz_146[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_147 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_147[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_147[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_147[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_148 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_148[11 : 11] = CsrPlugin_mip_MEIP; + _zz_148[7 : 7] = CsrPlugin_mip_MTIP; + _zz_148[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_149 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_149[11 : 11] = CsrPlugin_mie_MEIE; + _zz_149[7 : 7] = CsrPlugin_mie_MTIE; + _zz_149[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_150 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_150[31 : 2] = CsrPlugin_mtvec_base; + _zz_150[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_151 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_151[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_152 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_152[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_153 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_153[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_153[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_154 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_154[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_155 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_155[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_156 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_156[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_157 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_157[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_158 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_158[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_159 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_159[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_160 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_160[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_161 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_161[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_162 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_162[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_163 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_163[31 : 0] = _zz_140; + end + end + + always @ (*) begin + _zz_164 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_164[31 : 0] = _zz_141; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_142 | _zz_143) | (_zz_144 | _zz_145)) | ((_zz_526 | _zz_146) | (_zz_147 | _zz_148))) | (((_zz_149 | _zz_150) | (_zz_151 | _zz_152)) | ((_zz_153 | _zz_154) | (_zz_155 | _zz_156)))) | (((_zz_157 | _zz_158) | (_zz_159 | _zz_160)) | ((_zz_161 | _zz_162) | (_zz_163 | _zz_164)))); + assign iBusWishbone_ADR = {_zz_334,_zz_165}; + assign iBusWishbone_CTI = ((_zz_165 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_271_)begin + if(_zz_233)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_271_)begin + if(_zz_233)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_213_; + assign iBus_rsp_valid = _zz_166; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_219_ = (dBus_cmd_payload_length != (3'b000)); - assign _zz_215_ = dBus_cmd_valid; - assign _zz_217_ = dBus_cmd_payload_wr; - assign _zz_218_ = (_zz_214_ == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_216_ && (_zz_217_ || _zz_218_)); - assign dBusWishbone_ADR = ((_zz_219_ ? {{dBus_cmd_payload_address[31 : 5],_zz_214_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); - assign dBusWishbone_CTI = (_zz_219_ ? (_zz_218_ ? (3'b111) : (3'b010)) : (3'b000)); - assign dBusWishbone_BTE = (2'b00); - assign dBusWishbone_SEL = (_zz_217_ ? dBus_cmd_payload_mask : (4'b1111)); - assign dBusWishbone_WE = _zz_217_; + assign _zz_172 = (dBus_cmd_payload_length != 3'b000); + assign _zz_168 = dBus_cmd_valid; + assign _zz_170 = dBus_cmd_payload_wr; + assign _zz_171 = (_zz_167 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_169 && (_zz_170 || _zz_171)); + assign dBusWishbone_ADR = ((_zz_172 ? {{dBus_cmd_payload_address[31 : 5],_zz_167},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_172 ? (_zz_171 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_170 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_170; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_216_ = (_zz_215_ && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_215_; - assign dBusWishbone_STB = _zz_215_; - assign dBus_rsp_valid = _zz_220_; + assign _zz_169 = (_zz_168 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_168; + assign dBusWishbone_STB = _zz_168; + assign dBus_rsp_valid = _zz_173; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_112_ <= 1'b0; - _zz_114_ <= 1'b0; + _zz_64 <= 1'b0; + _zz_66 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_127_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_128_ <= 1'b0; - _zz_135_ <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_142_; - DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_160_ <= 1'b1; - _zz_173_ <= 1'b0; - CsrPlugin_misa_base <= (2'b01); - CsrPlugin_misa_extensions <= (26'b00000000000000000001000010); + IBusCachedPlugin_rspCounter <= _zz_79; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_80; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_98 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -5437,22 +4587,29 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_DivPlugin_div_counter_value <= (6'b000000); - _zz_210_ <= (32'b00000000000000000000000000000000); + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_140 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_212_ <= (3'b000); - _zz_213_ <= 1'b0; - _zz_214_ <= (3'b000); - _zz_220_ <= 1'b0; + _zz_165 <= 3'b000; + _zz_166 <= 1'b0; + _zz_167 <= 3'b000; + _zz_173 <= 1'b0; end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin @@ -5461,86 +4618,80 @@ module VexRiscv ( if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_112_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_64 <= 1'b0; end - if(_zz_110_)begin - _zz_112_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if(_zz_62)begin + _zz_64 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_114_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_66 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_114_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_66 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_128_ <= 1'b0; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_272_)begin - _zz_128_ <= dataCache_1__io_mem_cmd_valid; + if(_zz_234)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_135_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end if(dBus_rsp_valid)begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_160_ <= 1'b0; - _zz_173_ <= _zz_172_; + _zz_98 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5562,20 +4713,39 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_273_)begin - if(_zz_274_)begin + if(_zz_235)begin + if(_zz_236)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_275_)begin + if(_zz_237)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_276_)begin + if(_zz_238)begin CsrPlugin_interrupt_valid <= 1'b1; end end CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_256_)begin + if(_zz_217)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5586,10 +4756,10 @@ module VexRiscv ( end endcase end - if(_zz_257_)begin - case(_zz_258_) + if(_zz_218)begin + case(_zz_219) 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; end @@ -5597,14 +4767,8 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_200_,{_zz_199_,_zz_198_}} != (3'b000)); + execute_CsrPlugin_wfiWake <= (({_zz_132,{_zz_131,_zz_130}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_43_; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -5623,127 +4787,87 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_210_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_365_[0]; - CsrPlugin_mstatus_MIE <= _zz_366_[0]; - end - end - 12'b111100010001 : begin - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - end - 12'b101100000000 : begin - end - 12'b101110000000 : begin - end - 12'b001101000100 : begin - end - 12'b001100000101 : begin - end - 12'b110011000000 : begin - end - 12'b101100000010 : begin - end - 12'b111100010011 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b110000000000 : begin - end - 12'b001100000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; - end - end - 12'b001101000000 : begin - end - 12'b111100010010 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_368_[0]; - CsrPlugin_mie_MTIE <= _zz_369_[0]; - CsrPlugin_mie_MSIE <= _zz_370_[0]; - end - end - 12'b101110000010 : begin + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; end - 12'b110010000000 : begin + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_327[0]; + CsrPlugin_mstatus_MIE <= _zz_328[0]; end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_330[0]; + CsrPlugin_mie_MTIE <= _zz_331[0]; + CsrPlugin_mie_MSIE <= _zz_332[0]; end - default : begin + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_140 <= execute_CsrPlugin_writeData[31 : 0]; end - endcase - if(_zz_271_)begin + end + if(_zz_233)begin if(iBusWishbone_ACK)begin - _zz_212_ <= (_zz_212_ + (3'b001)); + _zz_165 <= (_zz_165 + 3'b001); end end - _zz_213_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_215_ && _zz_216_))begin - _zz_214_ <= (_zz_214_ + (3'b001)); - if(_zz_218_)begin - _zz_214_ <= (3'b000); + _zz_166 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_168 && _zz_169))begin + _zz_167 <= (_zz_167 + 3'b001); + if(_zz_171)begin + _zz_167 <= 3'b000; end end - _zz_220_ <= ((_zz_215_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_173 <= ((_zz_168 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_115_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_67 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_272_)begin - _zz_129_ <= dataCache_1__io_mem_cmd_payload_wr; - _zz_130_ <= dataCache_1__io_mem_cmd_payload_address; - _zz_131_ <= dataCache_1__io_mem_cmd_payload_data; - _zz_132_ <= dataCache_1__io_mem_cmd_payload_mask; - _zz_133_ <= dataCache_1__io_mem_cmd_payload_length; - _zz_134_ <= dataCache_1__io_mem_cmd_payload_last; - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_136_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - _zz_137_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; - _zz_138_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; - _zz_139_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - _zz_140_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; - _zz_141_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; - end - if(_zz_172_)begin - _zz_174_ <= _zz_59_[11 : 7]; - _zz_175_ <= _zz_89_; - end + if(_zz_234)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_253_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_202_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_202_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_215)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_134 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_134 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -5757,21 +4881,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_273_)begin - if(_zz_274_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_235)begin + if(_zz_236)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_275_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_237)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_276_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_238)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_256_)begin + if(_zz_217)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5785,288 +4909,1427 @@ module VexRiscv ( end endcase end - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin + if((memory_DivPlugin_div_counter_value == 6'h20))begin memory_DivPlugin_div_done <= 1'b1; end if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_248_)begin - if(_zz_255_)begin - memory_DivPlugin_rs1[31 : 0] <= _zz_353_[31:0]; - memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_205_[32]) ? _zz_354_ : _zz_355_); - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_result <= _zz_356_[31:0]; - end - end + if(_zz_210)begin + if(_zz_231)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_318[31:0]; + end + end + end + if(_zz_232)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_138 ? (~ _zz_139) : _zz_139) + _zz_324); + memory_DivPlugin_rs2 <= ((_zz_137 ? (~ execute_RS2) : execute_RS2) + _zz_326); + memory_DivPlugin_div_needRevert <= ((_zz_138 ^ (_zz_137 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_35; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_329[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_333[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; end - if(_zz_270_)begin - memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_DivPlugin_rs1 <= ((_zz_208_ ? (~ _zz_209_) : _zz_209_) + _zz_362_); - memory_DivPlugin_rs2 <= ((_zz_207_ ? (~ execute_RS2) : execute_RS2) + _zz_364_); - memory_DivPlugin_div_needRevert <= ((_zz_208_ ^ (_zz_207_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_25_; + end + + always @ (*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LH <= execute_MUL_LH; + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + + always @ (*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_97_; + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_96_; + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_22_; + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_19_; + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HL <= execute_MUL_HL; + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_50_; + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_42_; + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(_zz_13)begin + stageB_loaderValid = 1'b0; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HH <= execute_MUL_HH; + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_17_; + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_14_; + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_11_; + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_9_; + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LL <= execute_MUL_LL; + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_7_; + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_4_; + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_1_; + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_MUL <= decode_IS_MUL; + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b111100010001 : begin - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; end - 12'b101100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; - end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; end - 12'b101110000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end end end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_367_[0]; - end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; end - 12'b110011000000 : begin + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; end - 12'b101100000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; - end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); end - 12'b111100010011 : begin + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; end - 12'b001101000011 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; - end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; end - 12'b111111000000 : begin + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_9; + reg [21:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [21:0] _zz_15; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_11 = (! lineLoader_flushCounter[7]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; end - 12'b110000000000 : begin + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; end - 12'b001100000001 : begin + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; end - 12'b001101000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; - end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end - 12'b111100010010 : begin + if(io_flush)begin + lineLoader_flushPending <= 1'b1; end - 12'b001100000100 : begin + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; end - 12'b101110000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; - end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; end - 12'b110010000000 : begin + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; end - 12'b001101000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_371_[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; end end - default : begin - end - endcase - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end end -endmodule + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_12)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index f8090d5..f2b8055 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : f022529bb419c7a04f9ba1b61e931127b7220919 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv -// Git hash : f022529bb419c7a04f9ba1b61e931127b7220919 +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 `define Input2Kind_defaultEncoding_type [0:0] @@ -54,7 +54,7 @@ module VexRiscv_inner ( input softwareInterrupt, output CfuPlugin_bus_cmd_valid, input CfuPlugin_bus_cmd_ready, - output [2:0] CfuPlugin_bus_cmd_payload_function_id, + output [19:0] CfuPlugin_bus_cmd_payload_function_id, output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, input CfuPlugin_bus_rsp_valid, @@ -87,37 +87,37 @@ module VexRiscv_inner ( input clk, input reset ); + wire _zz_210; + wire _zz_211; + wire _zz_212; wire _zz_213; wire _zz_214; wire _zz_215; wire _zz_216; wire _zz_217; - wire _zz_218; + reg _zz_218; wire _zz_219; - wire _zz_220; - reg _zz_221; - wire _zz_222; - wire [31:0] _zz_223; + wire [31:0] _zz_220; + wire _zz_221; + wire [31:0] _zz_222; + reg _zz_223; wire _zz_224; - wire [31:0] _zz_225; - reg _zz_226; + wire _zz_225; + wire [31:0] _zz_226; wire _zz_227; wire _zz_228; - wire [31:0] _zz_229; + wire _zz_229; wire _zz_230; wire _zz_231; wire _zz_232; wire _zz_233; wire _zz_234; - wire _zz_235; + wire [3:0] _zz_235; wire _zz_236; wire _zz_237; - wire [3:0] _zz_238; - wire _zz_239; - wire _zz_240; - reg [31:0] _zz_241; - reg [31:0] _zz_242; - reg [31:0] _zz_243; + reg [31:0] _zz_238; + reg [31:0] _zz_239; + reg [31:0] _zz_240; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -131,6 +131,7 @@ module VexRiscv_inner ( wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; wire dataCache_1_io_cpu_memory_isWrite; wire dataCache_1_io_cpu_writeBack_haltIt; wire [31:0] dataCache_1_io_cpu_writeBack_data; @@ -149,6 +150,9 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_241; + wire _zz_242; + wire _zz_243; wire _zz_244; wire _zz_245; wire _zz_246; @@ -161,10 +165,10 @@ module VexRiscv_inner ( wire _zz_253; wire _zz_254; wire _zz_255; - wire _zz_256; + wire [1:0] _zz_256; wire _zz_257; wire _zz_258; - wire [1:0] _zz_259; + wire _zz_259; wire _zz_260; wire _zz_261; wire _zz_262; @@ -172,9 +176,9 @@ module VexRiscv_inner ( wire _zz_264; wire _zz_265; wire _zz_266; - wire _zz_267; + wire [1:0] _zz_267; wire _zz_268; - wire [1:0] _zz_269; + wire _zz_269; wire _zz_270; wire _zz_271; wire _zz_272; @@ -182,22 +186,22 @@ module VexRiscv_inner ( wire _zz_274; wire _zz_275; wire _zz_276; - wire _zz_277; - wire [1:0] _zz_278; - wire _zz_279; - wire [1:0] _zz_280; + wire [1:0] _zz_277; + wire _zz_278; + wire [1:0] _zz_279; + wire [51:0] _zz_280; wire [51:0] _zz_281; wire [51:0] _zz_282; - wire [51:0] _zz_283; - wire [32:0] _zz_284; - wire [51:0] _zz_285; - wire [49:0] _zz_286; - wire [51:0] _zz_287; - wire [49:0] _zz_288; - wire [51:0] _zz_289; - wire [32:0] _zz_290; - wire [31:0] _zz_291; - wire [32:0] _zz_292; + wire [32:0] _zz_283; + wire [51:0] _zz_284; + wire [49:0] _zz_285; + wire [51:0] _zz_286; + wire [49:0] _zz_287; + wire [51:0] _zz_288; + wire [32:0] _zz_289; + wire [31:0] _zz_290; + wire [32:0] _zz_291; + wire [0:0] _zz_292; wire [0:0] _zz_293; wire [0:0] _zz_294; wire [0:0] _zz_295; @@ -215,181 +219,181 @@ module VexRiscv_inner ( wire [0:0] _zz_307; wire [0:0] _zz_308; wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [3:0] _zz_311; - wire [2:0] _zz_312; - wire [31:0] _zz_313; - wire [11:0] _zz_314; - wire [31:0] _zz_315; - wire [19:0] _zz_316; - wire [11:0] _zz_317; + wire [3:0] _zz_310; + wire [2:0] _zz_311; + wire [31:0] _zz_312; + wire [11:0] _zz_313; + wire [31:0] _zz_314; + wire [19:0] _zz_315; + wire [11:0] _zz_316; + wire [31:0] _zz_317; wire [31:0] _zz_318; - wire [31:0] _zz_319; - wire [19:0] _zz_320; - wire [11:0] _zz_321; + wire [19:0] _zz_319; + wire [11:0] _zz_320; + wire [2:0] _zz_321; wire [2:0] _zz_322; - wire [2:0] _zz_323; - wire [0:0] _zz_324; - wire [2:0] _zz_325; - wire [4:0] _zz_326; + wire [0:0] _zz_323; + wire [2:0] _zz_324; + wire [4:0] _zz_325; + wire [11:0] _zz_326; wire [11:0] _zz_327; - wire [11:0] _zz_328; + wire [31:0] _zz_328; wire [31:0] _zz_329; wire [31:0] _zz_330; wire [31:0] _zz_331; wire [31:0] _zz_332; wire [31:0] _zz_333; wire [31:0] _zz_334; - wire [31:0] _zz_335; - wire [11:0] _zz_336; - wire [19:0] _zz_337; - wire [11:0] _zz_338; + wire [11:0] _zz_335; + wire [19:0] _zz_336; + wire [11:0] _zz_337; + wire [31:0] _zz_338; wire [31:0] _zz_339; wire [31:0] _zz_340; - wire [31:0] _zz_341; - wire [11:0] _zz_342; - wire [19:0] _zz_343; - wire [11:0] _zz_344; - wire [2:0] _zz_345; + wire [11:0] _zz_341; + wire [19:0] _zz_342; + wire [11:0] _zz_343; + wire [2:0] _zz_344; + wire [1:0] _zz_345; wire [1:0] _zz_346; wire [1:0] _zz_347; wire [1:0] _zz_348; - wire [1:0] _zz_349; - wire [2:0] _zz_350; - wire [11:0] _zz_351; + wire [19:0] _zz_349; + wire [11:0] _zz_350; + wire [65:0] _zz_351; wire [65:0] _zz_352; - wire [65:0] _zz_353; + wire [31:0] _zz_353; wire [31:0] _zz_354; - wire [31:0] _zz_355; - wire [0:0] _zz_356; - wire [5:0] _zz_357; - wire [32:0] _zz_358; + wire [0:0] _zz_355; + wire [5:0] _zz_356; + wire [32:0] _zz_357; + wire [31:0] _zz_358; wire [31:0] _zz_359; - wire [31:0] _zz_360; + wire [32:0] _zz_360; wire [32:0] _zz_361; wire [32:0] _zz_362; wire [32:0] _zz_363; - wire [32:0] _zz_364; - wire [0:0] _zz_365; - wire [32:0] _zz_366; - wire [0:0] _zz_367; - wire [32:0] _zz_368; - wire [0:0] _zz_369; - wire [31:0] _zz_370; + wire [0:0] _zz_364; + wire [32:0] _zz_365; + wire [0:0] _zz_366; + wire [32:0] _zz_367; + wire [0:0] _zz_368; + wire [31:0] _zz_369; + wire [0:0] _zz_370; wire [0:0] _zz_371; wire [0:0] _zz_372; wire [0:0] _zz_373; wire [0:0] _zz_374; wire [0:0] _zz_375; wire [0:0] _zz_376; - wire [0:0] _zz_377; - wire [26:0] _zz_378; + wire [26:0] _zz_377; + wire _zz_378; wire _zz_379; - wire _zz_380; - wire [1:0] _zz_381; + wire [1:0] _zz_380; + wire [31:0] _zz_381; wire [31:0] _zz_382; wire [31:0] _zz_383; - wire [31:0] _zz_384; - wire _zz_385; - wire [0:0] _zz_386; - wire [14:0] _zz_387; + wire _zz_384; + wire [0:0] _zz_385; + wire [14:0] _zz_386; + wire [31:0] _zz_387; wire [31:0] _zz_388; wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire _zz_391; - wire [0:0] _zz_392; - wire [8:0] _zz_393; + wire _zz_390; + wire [0:0] _zz_391; + wire [8:0] _zz_392; + wire [31:0] _zz_393; wire [31:0] _zz_394; wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire _zz_397; - wire [0:0] _zz_398; - wire [2:0] _zz_399; + wire _zz_396; + wire [0:0] _zz_397; + wire [2:0] _zz_398; + wire _zz_399; wire _zz_400; wire _zz_401; - wire _zz_402; + wire [31:0] _zz_402; wire [31:0] _zz_403; - wire [31:0] _zz_404; + wire _zz_404; wire _zz_405; - wire _zz_406; - wire [0:0] _zz_407; - wire [26:0] _zz_408; + wire [0:0] _zz_406; + wire [26:0] _zz_407; + wire [31:0] _zz_408; wire [31:0] _zz_409; wire [31:0] _zz_410; - wire [31:0] _zz_411; + wire [0:0] _zz_411; wire [0:0] _zz_412; - wire [0:0] _zz_413; + wire [1:0] _zz_413; wire [1:0] _zz_414; - wire [1:0] _zz_415; - wire _zz_416; - wire [0:0] _zz_417; - wire [21:0] _zz_418; + wire _zz_415; + wire [0:0] _zz_416; + wire [21:0] _zz_417; + wire [31:0] _zz_418; wire [31:0] _zz_419; wire [31:0] _zz_420; wire [31:0] _zz_421; wire [31:0] _zz_422; wire [31:0] _zz_423; - wire [31:0] _zz_424; + wire [0:0] _zz_424; wire [0:0] _zz_425; - wire [0:0] _zz_426; + wire [2:0] _zz_426; wire [2:0] _zz_427; - wire [2:0] _zz_428; - wire _zz_429; - wire [0:0] _zz_430; - wire [18:0] _zz_431; + wire _zz_428; + wire [0:0] _zz_429; + wire [18:0] _zz_430; + wire [31:0] _zz_431; wire [31:0] _zz_432; wire [31:0] _zz_433; wire [31:0] _zz_434; - wire [31:0] _zz_435; + wire _zz_435; wire _zz_436; - wire _zz_437; + wire [31:0] _zz_437; wire [31:0] _zz_438; - wire [31:0] _zz_439; - wire _zz_440; + wire _zz_439; + wire [0:0] _zz_440; wire [0:0] _zz_441; - wire [0:0] _zz_442; - wire _zz_443; - wire [0:0] _zz_444; - wire [15:0] _zz_445; - wire [31:0] _zz_446; + wire _zz_442; + wire [0:0] _zz_443; + wire [15:0] _zz_444; + wire [31:0] _zz_445; + wire _zz_446; wire _zz_447; wire _zz_448; - wire _zz_449; + wire [2:0] _zz_449; wire [2:0] _zz_450; - wire [2:0] _zz_451; - wire _zz_452; - wire [0:0] _zz_453; - wire [12:0] _zz_454; + wire _zz_451; + wire [0:0] _zz_452; + wire [12:0] _zz_453; + wire _zz_454; wire _zz_455; wire _zz_456; - wire _zz_457; - wire [0:0] _zz_458; - wire [2:0] _zz_459; - wire _zz_460; + wire [0:0] _zz_457; + wire [2:0] _zz_458; + wire _zz_459; + wire [5:0] _zz_460; wire [5:0] _zz_461; - wire [5:0] _zz_462; - wire _zz_463; - wire [0:0] _zz_464; - wire [9:0] _zz_465; + wire _zz_462; + wire [0:0] _zz_463; + wire [9:0] _zz_464; + wire [31:0] _zz_465; wire [31:0] _zz_466; wire [31:0] _zz_467; wire [31:0] _zz_468; wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire _zz_471; + wire _zz_470; + wire [0:0] _zz_471; wire [0:0] _zz_472; - wire [0:0] _zz_473; - wire [31:0] _zz_474; - wire _zz_475; - wire [0:0] _zz_476; - wire [3:0] _zz_477; - wire [0:0] _zz_478; - wire [3:0] _zz_479; + wire [31:0] _zz_473; + wire _zz_474; + wire [0:0] _zz_475; + wire [3:0] _zz_476; + wire [0:0] _zz_477; + wire [3:0] _zz_478; + wire [5:0] _zz_479; wire [5:0] _zz_480; - wire [5:0] _zz_481; - wire _zz_482; - wire [0:0] _zz_483; - wire [7:0] _zz_484; + wire _zz_481; + wire [0:0] _zz_482; + wire [7:0] _zz_483; + wire [31:0] _zz_484; wire [31:0] _zz_485; wire [31:0] _zz_486; wire [31:0] _zz_487; @@ -397,89 +401,88 @@ module VexRiscv_inner ( wire [31:0] _zz_489; wire [31:0] _zz_490; wire [31:0] _zz_491; - wire [31:0] _zz_492; - wire [0:0] _zz_493; - wire [1:0] _zz_494; - wire _zz_495; - wire [0:0] _zz_496; - wire [1:0] _zz_497; - wire [0:0] _zz_498; - wire [3:0] _zz_499; + wire [0:0] _zz_492; + wire [1:0] _zz_493; + wire _zz_494; + wire [0:0] _zz_495; + wire [1:0] _zz_496; + wire [0:0] _zz_497; + wire [3:0] _zz_498; + wire [0:0] _zz_499; wire [0:0] _zz_500; - wire [0:0] _zz_501; + wire [1:0] _zz_501; wire [1:0] _zz_502; - wire [1:0] _zz_503; - wire _zz_504; - wire [0:0] _zz_505; - wire [5:0] _zz_506; + wire _zz_503; + wire [0:0] _zz_504; + wire [5:0] _zz_505; + wire [31:0] _zz_506; wire [31:0] _zz_507; - wire [31:0] _zz_508; + wire _zz_508; wire _zz_509; - wire _zz_510; + wire [31:0] _zz_510; wire [31:0] _zz_511; wire [31:0] _zz_512; - wire [31:0] _zz_513; + wire _zz_513; wire _zz_514; - wire _zz_515; + wire [31:0] _zz_515; wire [31:0] _zz_516; - wire [31:0] _zz_517; - wire _zz_518; - wire [0:0] _zz_519; - wire [1:0] _zz_520; + wire _zz_517; + wire [0:0] _zz_518; + wire [1:0] _zz_519; + wire [31:0] _zz_520; wire [31:0] _zz_521; - wire [31:0] _zz_522; + wire _zz_522; wire _zz_523; - wire _zz_524; + wire [0:0] _zz_524; wire [0:0] _zz_525; - wire [0:0] _zz_526; - wire _zz_527; - wire [0:0] _zz_528; - wire [3:0] _zz_529; + wire _zz_526; + wire [0:0] _zz_527; + wire [3:0] _zz_528; + wire [31:0] _zz_529; wire [31:0] _zz_530; wire [31:0] _zz_531; wire [31:0] _zz_532; wire [31:0] _zz_533; wire [31:0] _zz_534; wire [31:0] _zz_535; - wire [31:0] _zz_536; + wire _zz_536; wire _zz_537; - wire _zz_538; + wire [31:0] _zz_538; wire [31:0] _zz_539; wire [31:0] _zz_540; wire [31:0] _zz_541; - wire [31:0] _zz_542; - wire [0:0] _zz_543; - wire [2:0] _zz_544; + wire [0:0] _zz_542; + wire [2:0] _zz_543; + wire [0:0] _zz_544; wire [0:0] _zz_545; - wire [0:0] _zz_546; - wire _zz_547; - wire [0:0] _zz_548; - wire [1:0] _zz_549; + wire _zz_546; + wire [0:0] _zz_547; + wire [1:0] _zz_548; + wire [31:0] _zz_549; wire [31:0] _zz_550; wire [31:0] _zz_551; - wire [31:0] _zz_552; + wire _zz_552; wire _zz_553; - wire _zz_554; - wire [31:0] _zz_555; - wire _zz_556; + wire [31:0] _zz_554; + wire _zz_555; + wire [0:0] _zz_556; wire [0:0] _zz_557; wire [0:0] _zz_558; wire [0:0] _zz_559; - wire [0:0] _zz_560; + wire [1:0] _zz_560; wire [1:0] _zz_561; - wire [1:0] _zz_562; + wire [0:0] _zz_562; wire [0:0] _zz_563; - wire [0:0] _zz_564; + wire [31:0] _zz_564; wire [31:0] _zz_565; wire [31:0] _zz_566; wire [31:0] _zz_567; wire [31:0] _zz_568; wire [31:0] _zz_569; - wire [31:0] _zz_570; + wire _zz_570; wire _zz_571; wire _zz_572; - wire _zz_573; - wire [31:0] _zz_574; + wire [31:0] _zz_573; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -674,7 +677,7 @@ module VexRiscv_inner ( wire decode_arbitration_isMoving; wire decode_arbitration_isFiring; reg execute_arbitration_haltItself; - wire execute_arbitration_haltByOther; + reg execute_arbitration_haltByOther; reg execute_arbitration_removeIt; wire execute_arbitration_flushIt; reg execute_arbitration_flushNext; @@ -729,6 +732,7 @@ module VexRiscv_inner ( wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; wire IBusCachedPlugin_mmuBus_rsp_allowRead; wire IBusCachedPlugin_mmuBus_rsp_allowWrite; wire IBusCachedPlugin_mmuBus_rsp_allowExecute; @@ -756,6 +760,7 @@ module VexRiscv_inner ( wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; wire DBusCachedPlugin_mmuBus_rsp_allowRead; wire DBusCachedPlugin_mmuBus_rsp_allowWrite; wire DBusCachedPlugin_mmuBus_rsp_allowExecute; @@ -952,8 +957,8 @@ module VexRiscv_inner ( wire [31:0] decode_RegFilePlugin_rs1Data; wire [31:0] decode_RegFilePlugin_rs2Data; reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; reg _zz_105; reg [31:0] execute_IntAluPlugin_bitwise; reg [31:0] _zz_106; @@ -969,37 +974,42 @@ module VexRiscv_inner ( reg [31:0] _zz_113; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_114; - reg _zz_115; - reg _zz_116; - reg _zz_117; - reg [4:0] _zz_118; - reg [31:0] _zz_119; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_115; + wire _zz_116; + wire _zz_117; + wire _zz_118; + wire _zz_119; wire _zz_120; - wire _zz_121; - wire _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; wire execute_BranchPlugin_eq; - wire [2:0] _zz_126; - reg _zz_127; - reg _zz_128; - wire _zz_129; - reg [19:0] _zz_130; - wire _zz_131; - reg [10:0] _zz_132; - wire _zz_133; - reg [18:0] _zz_134; - reg _zz_135; + wire [2:0] _zz_121; + reg _zz_122; + reg _zz_123; + wire _zz_124; + reg [19:0] _zz_125; + wire _zz_126; + reg [10:0] _zz_127; + wire _zz_128; + reg [18:0] _zz_129; + reg _zz_130; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_136; - reg [19:0] _zz_137; - wire _zz_138; - reg [10:0] _zz_139; - wire _zz_140; - reg [18:0] _zz_141; + wire _zz_131; + reg [19:0] _zz_132; + wire _zz_133; + reg [10:0] _zz_134; + wire _zz_135; + reg [18:0] _zz_136; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1021,9 +1031,9 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_142; - wire _zz_143; - wire _zz_144; + wire _zz_137; + wire _zz_138; + wire _zz_139; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1036,10 +1046,10 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_145; - wire _zz_146; - wire [1:0] _zz_147; - wire _zz_148; + wire [1:0] _zz_140; + wire _zz_141; + wire [1:0] _zz_142; + wire _zz_143; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1061,13 +1071,18 @@ module VexRiscv_inner ( reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; wire [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_144; + reg [31:0] _zz_145; + reg [31:0] _zz_146; + reg [31:0] _zz_147; + reg [31:0] _zz_148; reg [31:0] _zz_149; reg [31:0] _zz_150; reg [31:0] _zz_151; @@ -1079,25 +1094,20 @@ module VexRiscv_inner ( reg [31:0] _zz_157; reg [31:0] _zz_158; reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; - wire [2:0] execute_CfuPlugin_functionsIds_0; - wire _zz_165; - reg [19:0] _zz_166; - reg [31:0] _zz_167; + wire [19:0] execute_CfuPlugin_functionsIds_0; + wire _zz_160; + reg [19:0] _zz_161; + reg [31:0] _zz_162; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_m2sPipe_rValid; - reg CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0; + reg CfuPlugin_bus_rsp_s2mPipe_rValid; + reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; @@ -1122,18 +1132,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_168; + wire [31:0] _zz_163; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_169; - wire _zz_170; - wire _zz_171; - reg [32:0] _zz_172; + wire [31:0] _zz_164; + wire _zz_165; + wire _zz_166; + reg [32:0] _zz_167; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_173; - wire [31:0] _zz_174; + reg [31:0] _zz_168; + wire [31:0] _zz_169; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1219,6 +1229,8 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2946; reg execute_CsrPlugin_csr_3072; reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; reg execute_CsrPlugin_csr_2820; reg execute_CsrPlugin_csr_2821; reg execute_CsrPlugin_csr_2822; @@ -1237,6 +1249,11 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; reg [31:0] _zz_175; reg [31:0] _zz_176; reg [31:0] _zz_177; @@ -1263,19 +1280,16 @@ module VexRiscv_inner ( reg [31:0] _zz_198; reg [31:0] _zz_199; reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [2:0] _zz_204; - reg _zz_205; + reg [2:0] _zz_201; + reg _zz_202; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_206; + reg [2:0] _zz_203; + wire _zz_204; + wire _zz_205; + wire _zz_206; wire _zz_207; wire _zz_208; - wire _zz_209; - wire _zz_210; - wire _zz_211; - reg _zz_212; + reg _zz_209; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; @@ -1369,346 +1383,348 @@ module VexRiscv_inner ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_244 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_245 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_246 = 1'b1; - assign _zz_247 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_248 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_249 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_250 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_251 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_252 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_253 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_254 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_255 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_256 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_257 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_258 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_259 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_260 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_261 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_262 = (1'b0 || (! 1'b1)); - assign _zz_263 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_264 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_265 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_266 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_267 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_268 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_269 = execute_INSTRUCTION[13 : 12]; - assign _zz_270 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_271 = (! memory_arbitration_isStuck); - assign _zz_272 = (iBus_cmd_valid || (_zz_204 != 3'b000)); - assign _zz_273 = (_zz_240 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_274 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_275 = ((_zz_142 && 1'b1) && (! 1'b0)); - assign _zz_276 = ((_zz_143 && 1'b1) && (! 1'b0)); - assign _zz_277 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_278 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_279 = execute_INSTRUCTION[13]; - assign _zz_280 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_281 = ($signed(_zz_282) + $signed(_zz_287)); - assign _zz_282 = ($signed(_zz_283) + $signed(_zz_285)); - assign _zz_283 = 52'h0; - assign _zz_284 = {1'b0,memory_MUL_LL}; - assign _zz_285 = {{19{_zz_284[32]}}, _zz_284}; - assign _zz_286 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_287 = {{2{_zz_286[49]}}, _zz_286}; - assign _zz_288 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_289 = {{2{_zz_288[49]}}, _zz_288}; - assign _zz_290 = ($signed(_zz_292) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_291 = _zz_290[31 : 0]; - assign _zz_292 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_293 = _zz_91[33 : 33]; - assign _zz_294 = _zz_91[32 : 32]; - assign _zz_295 = _zz_91[31 : 31]; - assign _zz_296 = _zz_91[30 : 30]; - assign _zz_297 = _zz_91[28 : 28]; - assign _zz_298 = _zz_91[25 : 25]; - assign _zz_299 = _zz_91[17 : 17]; - assign _zz_300 = _zz_91[16 : 16]; - assign _zz_301 = _zz_91[13 : 13]; - assign _zz_302 = _zz_91[12 : 12]; - assign _zz_303 = _zz_91[11 : 11]; - assign _zz_304 = _zz_91[15 : 15]; - assign _zz_305 = _zz_91[5 : 5]; - assign _zz_306 = _zz_91[3 : 3]; - assign _zz_307 = _zz_91[20 : 20]; - assign _zz_308 = _zz_91[10 : 10]; - assign _zz_309 = _zz_91[4 : 4]; - assign _zz_310 = _zz_91[0 : 0]; - assign _zz_311 = (_zz_59 - 4'b0001); - assign _zz_312 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_313 = {29'd0, _zz_312}; - assign _zz_314 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_315 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_316 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_317 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_318 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_319 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_321 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_322 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_323 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_324 = execute_SRC_LESS; - assign _zz_325 = 3'b100; - assign _zz_326 = execute_INSTRUCTION[19 : 15]; - assign _zz_327 = execute_INSTRUCTION[31 : 20]; - assign _zz_328 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_329 = ($signed(_zz_330) + $signed(_zz_333)); - assign _zz_330 = ($signed(_zz_331) + $signed(_zz_332)); - assign _zz_331 = execute_SRC1; - assign _zz_332 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_333 = (execute_SRC_USE_SUB_LESS ? _zz_334 : _zz_335); - assign _zz_334 = 32'h00000001; - assign _zz_335 = 32'h0; - assign _zz_336 = execute_INSTRUCTION[31 : 20]; - assign _zz_337 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_338 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_339 = {_zz_130,execute_INSTRUCTION[31 : 20]}; - assign _zz_340 = {{_zz_132,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_341 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_342 = execute_INSTRUCTION[31 : 20]; - assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_345 = 3'b100; - assign _zz_346 = (_zz_145 & (~ _zz_347)); - assign _zz_347 = (_zz_145 - 2'b01); - assign _zz_348 = (_zz_147 & (~ _zz_349)); - assign _zz_349 = (_zz_147 - 2'b01); - assign _zz_350 = execute_INSTRUCTION[14 : 12]; - assign _zz_351 = execute_INSTRUCTION[31 : 20]; - assign _zz_352 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_353 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_354 = writeBack_MUL_LOW[31 : 0]; - assign _zz_355 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_356 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_357 = {5'd0, _zz_356}; - assign _zz_358 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_359 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_360 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_361 = {_zz_168,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_241 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_242 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_243 = 1'b1; + assign _zz_244 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_245 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_246 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_247 = ((_zz_215 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_248 = ((_zz_215 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_249 = ((_zz_215 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_250 = ((_zz_215 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_251 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_252 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_253 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_254 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_255 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_256 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_257 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_258 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_259 = (1'b0 || (! 1'b1)); + assign _zz_260 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_261 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_262 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_263 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_264 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_265 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_266 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_267 = execute_INSTRUCTION[13 : 12]; + assign _zz_268 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_269 = (! memory_arbitration_isStuck); + assign _zz_270 = (iBus_cmd_valid || (_zz_201 != 3'b000)); + assign _zz_271 = (_zz_237 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_272 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_273 = ((_zz_137 && 1'b1) && (! 1'b0)); + assign _zz_274 = ((_zz_138 && 1'b1) && (! 1'b0)); + assign _zz_275 = ((_zz_139 && 1'b1) && (! 1'b0)); + assign _zz_276 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_277 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_278 = execute_INSTRUCTION[13]; + assign _zz_279 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_280 = ($signed(_zz_281) + $signed(_zz_286)); + assign _zz_281 = ($signed(_zz_282) + $signed(_zz_284)); + assign _zz_282 = 52'h0; + assign _zz_283 = {1'b0,memory_MUL_LL}; + assign _zz_284 = {{19{_zz_283[32]}}, _zz_283}; + assign _zz_285 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_286 = {{2{_zz_285[49]}}, _zz_285}; + assign _zz_287 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_288 = {{2{_zz_287[49]}}, _zz_287}; + assign _zz_289 = ($signed(_zz_291) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_290 = _zz_289[31 : 0]; + assign _zz_291 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_292 = _zz_91[33 : 33]; + assign _zz_293 = _zz_91[32 : 32]; + assign _zz_294 = _zz_91[31 : 31]; + assign _zz_295 = _zz_91[30 : 30]; + assign _zz_296 = _zz_91[28 : 28]; + assign _zz_297 = _zz_91[25 : 25]; + assign _zz_298 = _zz_91[17 : 17]; + assign _zz_299 = _zz_91[16 : 16]; + assign _zz_300 = _zz_91[13 : 13]; + assign _zz_301 = _zz_91[12 : 12]; + assign _zz_302 = _zz_91[11 : 11]; + assign _zz_303 = _zz_91[15 : 15]; + assign _zz_304 = _zz_91[5 : 5]; + assign _zz_305 = _zz_91[3 : 3]; + assign _zz_306 = _zz_91[20 : 20]; + assign _zz_307 = _zz_91[10 : 10]; + assign _zz_308 = _zz_91[4 : 4]; + assign _zz_309 = _zz_91[0 : 0]; + assign _zz_310 = (_zz_59 - 4'b0001); + assign _zz_311 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_312 = {29'd0, _zz_311}; + assign _zz_313 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_314 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_315 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_316 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_317 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_318 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_319 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_321 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_322 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_323 = execute_SRC_LESS; + assign _zz_324 = 3'b100; + assign _zz_325 = execute_INSTRUCTION[19 : 15]; + assign _zz_326 = execute_INSTRUCTION[31 : 20]; + assign _zz_327 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_328 = ($signed(_zz_329) + $signed(_zz_332)); + assign _zz_329 = ($signed(_zz_330) + $signed(_zz_331)); + assign _zz_330 = execute_SRC1; + assign _zz_331 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_332 = (execute_SRC_USE_SUB_LESS ? _zz_333 : _zz_334); + assign _zz_333 = 32'h00000001; + assign _zz_334 = 32'h0; + assign _zz_335 = execute_INSTRUCTION[31 : 20]; + assign _zz_336 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_337 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_338 = {_zz_125,execute_INSTRUCTION[31 : 20]}; + assign _zz_339 = {{_zz_127,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_340 = {{_zz_129,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_341 = execute_INSTRUCTION[31 : 20]; + assign _zz_342 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_344 = 3'b100; + assign _zz_345 = (_zz_140 & (~ _zz_346)); + assign _zz_346 = (_zz_140 - 2'b01); + assign _zz_347 = (_zz_142 & (~ _zz_348)); + assign _zz_348 = (_zz_142 - 2'b01); + assign _zz_349 = execute_INSTRUCTION[31 : 12]; + assign _zz_350 = execute_INSTRUCTION[31 : 20]; + assign _zz_351 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_352 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_353 = writeBack_MUL_LOW[31 : 0]; + assign _zz_354 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_355 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_356 = {5'd0, _zz_355}; + assign _zz_357 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_358 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_359 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_360 = {_zz_163,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_361 = _zz_362; assign _zz_362 = _zz_363; - assign _zz_363 = _zz_364; - assign _zz_364 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_169) : _zz_169)} + _zz_366); - assign _zz_365 = memory_DivPlugin_div_needRevert; - assign _zz_366 = {32'd0, _zz_365}; - assign _zz_367 = _zz_171; - assign _zz_368 = {32'd0, _zz_367}; - assign _zz_369 = _zz_170; - assign _zz_370 = {31'd0, _zz_369}; - assign _zz_371 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_363 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_164) : _zz_164)} + _zz_365); + assign _zz_364 = memory_DivPlugin_div_needRevert; + assign _zz_365 = {32'd0, _zz_364}; + assign _zz_366 = _zz_166; + assign _zz_367 = {32'd0, _zz_366}; + assign _zz_368 = _zz_165; + assign _zz_369 = {31'd0, _zz_368}; + assign _zz_370 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_371 = execute_CsrPlugin_writeData[3 : 3]; assign _zz_372 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_373 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_374 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_375 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_376 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_377 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_378 = (iBus_cmd_payload_address >>> 5); + assign _zz_373 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_374 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_375 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_376 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_377 = (iBus_cmd_payload_address >>> 5); + assign _zz_378 = 1'b1; assign _zz_379 = 1'b1; - assign _zz_380 = 1'b1; - assign _zz_381 = {_zz_63,_zz_62}; - assign _zz_382 = 32'h0000106f; - assign _zz_383 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_384 = 32'h00001073; - assign _zz_385 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_386 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_387 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}; - assign _zz_388 = 32'h0000207f; - assign _zz_389 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_390 = 32'h00000003; - assign _zz_391 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_392 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_393 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_394) == 32'h00005013),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; - assign _zz_394 = 32'hbc00707f; - assign _zz_395 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_396 = 32'h00001013; - assign _zz_397 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_398 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_399 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_380 = {_zz_63,_zz_62}; + assign _zz_381 = 32'h0000106f; + assign _zz_382 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_383 = 32'h00001073; + assign _zz_384 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_385 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_386 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_387) == 32'h00000003),{(_zz_388 == _zz_389),{_zz_390,{_zz_391,_zz_392}}}}}}; + assign _zz_387 = 32'h0000207f; + assign _zz_388 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_389 = 32'h00000003; + assign _zz_390 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_391 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_392 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_393) == 32'h00005013),{(_zz_394 == _zz_395),{_zz_396,{_zz_397,_zz_398}}}}}}; + assign _zz_393 = 32'hbc00707f; + assign _zz_394 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_395 = 32'h00001013; + assign _zz_396 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_397 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_398 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_399 = decode_INSTRUCTION[31]; assign _zz_400 = decode_INSTRUCTION[31]; - assign _zz_401 = decode_INSTRUCTION[31]; - assign _zz_402 = decode_INSTRUCTION[7]; - assign _zz_403 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_404 = 32'h02004020; - assign _zz_405 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_406 = (_zz_95 != 1'b0); - assign _zz_407 = (((decode_INSTRUCTION & _zz_409) == 32'h00000050) != 1'b0); - assign _zz_408 = {((_zz_410 == _zz_411) != 1'b0),{({_zz_412,_zz_413} != 2'b00),{(_zz_414 != _zz_415),{_zz_416,{_zz_417,_zz_418}}}}}; - assign _zz_409 = 32'h00203050; - assign _zz_410 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_411 = 32'h00000050; - assign _zz_412 = ((decode_INSTRUCTION & _zz_419) == 32'h00001050); - assign _zz_413 = ((decode_INSTRUCTION & _zz_420) == 32'h00002050); - assign _zz_414 = {_zz_94,(_zz_421 == _zz_422)}; - assign _zz_415 = 2'b00; - assign _zz_416 = ((_zz_423 == _zz_424) != 1'b0); - assign _zz_417 = ({_zz_425,_zz_426} != 2'b00); - assign _zz_418 = {(_zz_427 != _zz_428),{_zz_429,{_zz_430,_zz_431}}}; - assign _zz_419 = 32'h00001050; - assign _zz_420 = 32'h00002050; - assign _zz_421 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_422 = 32'h00000004; - assign _zz_423 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_424 = 32'h00000040; - assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00005010); - assign _zz_426 = ((decode_INSTRUCTION & _zz_433) == 32'h00005020); - assign _zz_427 = {(_zz_434 == _zz_435),{_zz_436,_zz_437}}; - assign _zz_428 = 3'b000; - assign _zz_429 = ((_zz_438 == _zz_439) != 1'b0); - assign _zz_430 = (_zz_440 != 1'b0); - assign _zz_431 = {(_zz_441 != _zz_442),{_zz_443,{_zz_444,_zz_445}}}; - assign _zz_432 = 32'h00007034; - assign _zz_433 = 32'h02007064; - assign _zz_434 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_435 = 32'h40001010; - assign _zz_436 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_437 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_438 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_439 = 32'h00000024; - assign _zz_440 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_441 = ((decode_INSTRUCTION & _zz_446) == 32'h00002000); - assign _zz_442 = 1'b0; - assign _zz_443 = ({_zz_447,_zz_448} != 2'b00); - assign _zz_444 = (_zz_449 != 1'b0); - assign _zz_445 = {(_zz_450 != _zz_451),{_zz_452,{_zz_453,_zz_454}}}; - assign _zz_446 = 32'h00003000; - assign _zz_447 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_448 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_449 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_450 = {_zz_95,{_zz_455,_zz_456}}; - assign _zz_451 = 3'b000; - assign _zz_452 = ({_zz_457,{_zz_458,_zz_459}} != 5'h0); - assign _zz_453 = (_zz_460 != 1'b0); - assign _zz_454 = {(_zz_461 != _zz_462),{_zz_463,{_zz_464,_zz_465}}}; + assign _zz_401 = decode_INSTRUCTION[7]; + assign _zz_402 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_403 = 32'h02004020; + assign _zz_404 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_405 = (_zz_95 != 1'b0); + assign _zz_406 = (((decode_INSTRUCTION & _zz_408) == 32'h00000050) != 1'b0); + assign _zz_407 = {((_zz_409 == _zz_410) != 1'b0),{({_zz_411,_zz_412} != 2'b00),{(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}}}; + assign _zz_408 = 32'h00203050; + assign _zz_409 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_410 = 32'h00000050; + assign _zz_411 = ((decode_INSTRUCTION & _zz_418) == 32'h00001050); + assign _zz_412 = ((decode_INSTRUCTION & _zz_419) == 32'h00002050); + assign _zz_413 = {_zz_94,(_zz_420 == _zz_421)}; + assign _zz_414 = 2'b00; + assign _zz_415 = ((_zz_422 == _zz_423) != 1'b0); + assign _zz_416 = ({_zz_424,_zz_425} != 2'b00); + assign _zz_417 = {(_zz_426 != _zz_427),{_zz_428,{_zz_429,_zz_430}}}; + assign _zz_418 = 32'h00001050; + assign _zz_419 = 32'h00002050; + assign _zz_420 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_421 = 32'h00000004; + assign _zz_422 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_423 = 32'h00000040; + assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00005010); + assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00005020); + assign _zz_426 = {(_zz_433 == _zz_434),{_zz_435,_zz_436}}; + assign _zz_427 = 3'b000; + assign _zz_428 = ((_zz_437 == _zz_438) != 1'b0); + assign _zz_429 = (_zz_439 != 1'b0); + assign _zz_430 = {(_zz_440 != _zz_441),{_zz_442,{_zz_443,_zz_444}}}; + assign _zz_431 = 32'h00007034; + assign _zz_432 = 32'h02007064; + assign _zz_433 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_434 = 32'h40001010; + assign _zz_435 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_436 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_437 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_438 = 32'h00000024; + assign _zz_439 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_440 = ((decode_INSTRUCTION & _zz_445) == 32'h00002000); + assign _zz_441 = 1'b0; + assign _zz_442 = ({_zz_446,_zz_447} != 2'b00); + assign _zz_443 = (_zz_448 != 1'b0); + assign _zz_444 = {(_zz_449 != _zz_450),{_zz_451,{_zz_452,_zz_453}}}; + assign _zz_445 = 32'h00003000; + assign _zz_446 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_447 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_448 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_449 = {_zz_95,{_zz_454,_zz_455}}; + assign _zz_450 = 3'b000; + assign _zz_451 = ({_zz_456,{_zz_457,_zz_458}} != 5'h0); + assign _zz_452 = (_zz_459 != 1'b0); + assign _zz_453 = {(_zz_460 != _zz_461),{_zz_462,{_zz_463,_zz_464}}}; + assign _zz_454 = ((decode_INSTRUCTION & _zz_465) == 32'h00000020); assign _zz_455 = ((decode_INSTRUCTION & _zz_466) == 32'h00000020); - assign _zz_456 = ((decode_INSTRUCTION & _zz_467) == 32'h00000020); - assign _zz_457 = ((decode_INSTRUCTION & _zz_468) == 32'h00002040); - assign _zz_458 = (_zz_469 == _zz_470); - assign _zz_459 = {_zz_471,{_zz_472,_zz_473}}; - assign _zz_460 = ((decode_INSTRUCTION & _zz_474) == 32'h00000020); - assign _zz_461 = {_zz_475,{_zz_476,_zz_477}}; - assign _zz_462 = 6'h0; - assign _zz_463 = ({_zz_478,_zz_479} != 5'h0); - assign _zz_464 = (_zz_480 != _zz_481); - assign _zz_465 = {_zz_482,{_zz_483,_zz_484}}; - assign _zz_466 = 32'h00000034; - assign _zz_467 = 32'h00000064; - assign _zz_468 = 32'h00002040; - assign _zz_469 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_470 = 32'h00001040; - assign _zz_471 = ((decode_INSTRUCTION & _zz_485) == 32'h00000040); - assign _zz_472 = (_zz_486 == _zz_487); - assign _zz_473 = (_zz_488 == _zz_489); - assign _zz_474 = 32'h00000020; - assign _zz_475 = ((decode_INSTRUCTION & _zz_490) == 32'h00000008); - assign _zz_476 = (_zz_491 == _zz_492); - assign _zz_477 = {_zz_93,{_zz_493,_zz_494}}; - assign _zz_478 = _zz_93; - assign _zz_479 = {_zz_495,{_zz_496,_zz_497}}; - assign _zz_480 = {_zz_94,{_zz_498,_zz_499}}; - assign _zz_481 = 6'h0; - assign _zz_482 = ({_zz_500,_zz_501} != 2'b00); - assign _zz_483 = (_zz_502 != _zz_503); - assign _zz_484 = {_zz_504,{_zz_505,_zz_506}}; - assign _zz_485 = 32'h00000050; - assign _zz_486 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_487 = 32'h00000040; - assign _zz_488 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_489 = 32'h0; - assign _zz_490 = 32'h00000008; - assign _zz_491 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_492 = 32'h00000040; - assign _zz_493 = (_zz_507 == _zz_508); - assign _zz_494 = {_zz_509,_zz_510}; - assign _zz_495 = ((decode_INSTRUCTION & _zz_511) == 32'h00002010); - assign _zz_496 = (_zz_512 == _zz_513); - assign _zz_497 = {_zz_514,_zz_515}; - assign _zz_498 = (_zz_516 == _zz_517); - assign _zz_499 = {_zz_518,{_zz_519,_zz_520}}; - assign _zz_500 = _zz_93; - assign _zz_501 = (_zz_521 == _zz_522); - assign _zz_502 = {_zz_93,_zz_523}; - assign _zz_503 = 2'b00; - assign _zz_504 = (_zz_524 != 1'b0); - assign _zz_505 = (_zz_525 != _zz_526); - assign _zz_506 = {_zz_527,{_zz_528,_zz_529}}; - assign _zz_507 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_508 = 32'h00004020; - assign _zz_509 = ((decode_INSTRUCTION & _zz_530) == 32'h00000010); - assign _zz_510 = ((decode_INSTRUCTION & _zz_531) == 32'h00000020); - assign _zz_511 = 32'h00002030; - assign _zz_512 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_513 = 32'h00000010; - assign _zz_514 = ((decode_INSTRUCTION & _zz_532) == 32'h00002020); - assign _zz_515 = ((decode_INSTRUCTION & _zz_533) == 32'h00000020); - assign _zz_516 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_517 = 32'h00001010; - assign _zz_518 = ((decode_INSTRUCTION & _zz_534) == 32'h00002010); - assign _zz_519 = (_zz_535 == _zz_536); - assign _zz_520 = {_zz_537,_zz_538}; - assign _zz_521 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_522 = 32'h00000020; - assign _zz_523 = ((decode_INSTRUCTION & _zz_539) == 32'h0); - assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00004010); - assign _zz_525 = (_zz_541 == _zz_542); - assign _zz_526 = 1'b0; - assign _zz_527 = ({_zz_543,_zz_544} != 4'b0000); - assign _zz_528 = (_zz_545 != _zz_546); - assign _zz_529 = {_zz_547,{_zz_548,_zz_549}}; - assign _zz_530 = 32'h00000030; - assign _zz_531 = 32'h02000020; - assign _zz_532 = 32'h02002060; - assign _zz_533 = 32'h02003020; - assign _zz_534 = 32'h00002010; - assign _zz_535 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_536 = 32'h00000010; - assign _zz_537 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_538 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_539 = 32'h00000020; - assign _zz_540 = 32'h00004014; - assign _zz_541 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_542 = 32'h00002010; - assign _zz_543 = ((decode_INSTRUCTION & _zz_550) == 32'h0); - assign _zz_544 = {(_zz_551 == _zz_552),{_zz_553,_zz_554}}; - assign _zz_545 = ((decode_INSTRUCTION & _zz_555) == 32'h0); - assign _zz_546 = 1'b0; - assign _zz_547 = ({_zz_556,{_zz_557,_zz_558}} != 3'b000); - assign _zz_548 = ({_zz_559,_zz_560} != 2'b00); - assign _zz_549 = {(_zz_561 != _zz_562),(_zz_563 != _zz_564)}; - assign _zz_550 = 32'h00000044; - assign _zz_551 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_552 = 32'h0; - assign _zz_553 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_554 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_555 = 32'h00000058; - assign _zz_556 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_557 = ((decode_INSTRUCTION & _zz_565) == 32'h00002010); - assign _zz_558 = ((decode_INSTRUCTION & _zz_566) == 32'h40000030); - assign _zz_559 = ((decode_INSTRUCTION & _zz_567) == 32'h00000004); - assign _zz_560 = _zz_92; - assign _zz_561 = {(_zz_568 == _zz_569),_zz_92}; - assign _zz_562 = 2'b00; - assign _zz_563 = ((decode_INSTRUCTION & _zz_570) == 32'h00001004); - assign _zz_564 = 1'b0; - assign _zz_565 = 32'h00002014; - assign _zz_566 = 32'h40000034; - assign _zz_567 = 32'h00000014; - assign _zz_568 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_569 = 32'h00000004; - assign _zz_570 = 32'h00005054; + assign _zz_456 = ((decode_INSTRUCTION & _zz_467) == 32'h00002040); + assign _zz_457 = (_zz_468 == _zz_469); + assign _zz_458 = {_zz_470,{_zz_471,_zz_472}}; + assign _zz_459 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); + assign _zz_460 = {_zz_474,{_zz_475,_zz_476}}; + assign _zz_461 = 6'h0; + assign _zz_462 = ({_zz_477,_zz_478} != 5'h0); + assign _zz_463 = (_zz_479 != _zz_480); + assign _zz_464 = {_zz_481,{_zz_482,_zz_483}}; + assign _zz_465 = 32'h00000034; + assign _zz_466 = 32'h00000064; + assign _zz_467 = 32'h00002040; + assign _zz_468 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_469 = 32'h00001040; + assign _zz_470 = ((decode_INSTRUCTION & _zz_484) == 32'h00000040); + assign _zz_471 = (_zz_485 == _zz_486); + assign _zz_472 = (_zz_487 == _zz_488); + assign _zz_473 = 32'h00000020; + assign _zz_474 = ((decode_INSTRUCTION & _zz_489) == 32'h00000008); + assign _zz_475 = (_zz_490 == _zz_491); + assign _zz_476 = {_zz_93,{_zz_492,_zz_493}}; + assign _zz_477 = _zz_93; + assign _zz_478 = {_zz_494,{_zz_495,_zz_496}}; + assign _zz_479 = {_zz_94,{_zz_497,_zz_498}}; + assign _zz_480 = 6'h0; + assign _zz_481 = ({_zz_499,_zz_500} != 2'b00); + assign _zz_482 = (_zz_501 != _zz_502); + assign _zz_483 = {_zz_503,{_zz_504,_zz_505}}; + assign _zz_484 = 32'h00000050; + assign _zz_485 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_486 = 32'h00000040; + assign _zz_487 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_488 = 32'h0; + assign _zz_489 = 32'h00000008; + assign _zz_490 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_491 = 32'h00000040; + assign _zz_492 = (_zz_506 == _zz_507); + assign _zz_493 = {_zz_508,_zz_509}; + assign _zz_494 = ((decode_INSTRUCTION & _zz_510) == 32'h00002010); + assign _zz_495 = (_zz_511 == _zz_512); + assign _zz_496 = {_zz_513,_zz_514}; + assign _zz_497 = (_zz_515 == _zz_516); + assign _zz_498 = {_zz_517,{_zz_518,_zz_519}}; + assign _zz_499 = _zz_93; + assign _zz_500 = (_zz_520 == _zz_521); + assign _zz_501 = {_zz_93,_zz_522}; + assign _zz_502 = 2'b00; + assign _zz_503 = (_zz_523 != 1'b0); + assign _zz_504 = (_zz_524 != _zz_525); + assign _zz_505 = {_zz_526,{_zz_527,_zz_528}}; + assign _zz_506 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_507 = 32'h00004020; + assign _zz_508 = ((decode_INSTRUCTION & _zz_529) == 32'h00000010); + assign _zz_509 = ((decode_INSTRUCTION & _zz_530) == 32'h00000020); + assign _zz_510 = 32'h00002030; + assign _zz_511 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_512 = 32'h00000010; + assign _zz_513 = ((decode_INSTRUCTION & _zz_531) == 32'h00002020); + assign _zz_514 = ((decode_INSTRUCTION & _zz_532) == 32'h00000020); + assign _zz_515 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_516 = 32'h00001010; + assign _zz_517 = ((decode_INSTRUCTION & _zz_533) == 32'h00002010); + assign _zz_518 = (_zz_534 == _zz_535); + assign _zz_519 = {_zz_536,_zz_537}; + assign _zz_520 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_521 = 32'h00000020; + assign _zz_522 = ((decode_INSTRUCTION & _zz_538) == 32'h0); + assign _zz_523 = ((decode_INSTRUCTION & _zz_539) == 32'h00004010); + assign _zz_524 = (_zz_540 == _zz_541); + assign _zz_525 = 1'b0; + assign _zz_526 = ({_zz_542,_zz_543} != 4'b0000); + assign _zz_527 = (_zz_544 != _zz_545); + assign _zz_528 = {_zz_546,{_zz_547,_zz_548}}; + assign _zz_529 = 32'h00000030; + assign _zz_530 = 32'h02000020; + assign _zz_531 = 32'h02002060; + assign _zz_532 = 32'h02003020; + assign _zz_533 = 32'h00002010; + assign _zz_534 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_535 = 32'h00000010; + assign _zz_536 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_537 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_538 = 32'h00000020; + assign _zz_539 = 32'h00004014; + assign _zz_540 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_541 = 32'h00002010; + assign _zz_542 = ((decode_INSTRUCTION & _zz_549) == 32'h0); + assign _zz_543 = {(_zz_550 == _zz_551),{_zz_552,_zz_553}}; + assign _zz_544 = ((decode_INSTRUCTION & _zz_554) == 32'h0); + assign _zz_545 = 1'b0; + assign _zz_546 = ({_zz_555,{_zz_556,_zz_557}} != 3'b000); + assign _zz_547 = ({_zz_558,_zz_559} != 2'b00); + assign _zz_548 = {(_zz_560 != _zz_561),(_zz_562 != _zz_563)}; + assign _zz_549 = 32'h00000044; + assign _zz_550 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_551 = 32'h0; + assign _zz_552 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_553 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_554 = 32'h00000058; + assign _zz_555 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_556 = ((decode_INSTRUCTION & _zz_564) == 32'h00002010); + assign _zz_557 = ((decode_INSTRUCTION & _zz_565) == 32'h40000030); + assign _zz_558 = ((decode_INSTRUCTION & _zz_566) == 32'h00000004); + assign _zz_559 = _zz_92; + assign _zz_560 = {(_zz_567 == _zz_568),_zz_92}; + assign _zz_561 = 2'b00; + assign _zz_562 = ((decode_INSTRUCTION & _zz_569) == 32'h00001004); + assign _zz_563 = 1'b0; + assign _zz_564 = 32'h00002014; + assign _zz_565 = 32'h40000034; + assign _zz_566 = 32'h00000014; + assign _zz_567 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_568 = 32'h00000004; + assign _zz_569 = 32'h00005054; + assign _zz_570 = execute_INSTRUCTION[31]; assign _zz_571 = execute_INSTRUCTION[31]; - assign _zz_572 = execute_INSTRUCTION[31]; - assign _zz_573 = execute_INSTRUCTION[7]; - assign _zz_574 = 32'h0; + assign _zz_572 = execute_INSTRUCTION[7]; + assign _zz_573 = 32'h0; always @ (posedge clk) begin - if(_zz_379) begin - _zz_241 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_378) begin + _zz_238 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_380) begin - _zz_242 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_379) begin + _zz_239 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1719,17 +1735,18 @@ module VexRiscv_inner ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_213 ), //i - .io_cpu_prefetch_isValid (_zz_214 ), //i + .io_flush (_zz_210 ), //i + .io_cpu_prefetch_isValid (_zz_211 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_215 ), //i - .io_cpu_fetch_isStuck (_zz_216 ), //i - .io_cpu_fetch_isRemoved (_zz_217 ), //i + .io_cpu_fetch_isValid (_zz_212 ), //i + .io_cpu_fetch_isStuck (_zz_213 ), //i + .io_cpu_fetch_isRemoved (_zz_214 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i @@ -1737,8 +1754,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_218 ), //i - .io_cpu_decode_isStuck (_zz_219 ), //i + .io_cpu_decode_isValid (_zz_215 ), //i + .io_cpu_decode_isStuck (_zz_216 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1746,8 +1763,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_220 ), //i - .io_cpu_fill_valid (_zz_221 ), //i + .io_cpu_decode_isUser (_zz_217 ), //i + .io_cpu_fill_valid (_zz_218 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1760,50 +1777,52 @@ module VexRiscv_inner ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_222 ), //i - .io_cpu_execute_address (_zz_223[31:0] ), //i + .io_cpu_execute_isValid (_zz_219 ), //i + .io_cpu_execute_address (_zz_220[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_86[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_memory_isValid (_zz_224 ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_221 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_225[31:0] ), //i + .io_cpu_memory_address (_zz_222[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_226 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_223 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_227 ), //i + .io_cpu_writeBack_isValid (_zz_224 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_228 ), //i + .io_cpu_writeBack_isUser (_zz_225 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_229[31:0] ), //i + .io_cpu_writeBack_address (_zz_226[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_230 ), //i - .io_cpu_writeBack_fence_SR (_zz_231 ), //i - .io_cpu_writeBack_fence_SO (_zz_232 ), //i - .io_cpu_writeBack_fence_SI (_zz_233 ), //i - .io_cpu_writeBack_fence_PW (_zz_234 ), //i - .io_cpu_writeBack_fence_PR (_zz_235 ), //i - .io_cpu_writeBack_fence_PO (_zz_236 ), //i - .io_cpu_writeBack_fence_PI (_zz_237 ), //i - .io_cpu_writeBack_fence_FM (_zz_238[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_227 ), //i + .io_cpu_writeBack_fence_SR (_zz_228 ), //i + .io_cpu_writeBack_fence_SO (_zz_229 ), //i + .io_cpu_writeBack_fence_SI (_zz_230 ), //i + .io_cpu_writeBack_fence_PW (_zz_231 ), //i + .io_cpu_writeBack_fence_PR (_zz_232 ), //i + .io_cpu_writeBack_fence_PO (_zz_233 ), //i + .io_cpu_writeBack_fence_PI (_zz_234 ), //i + .io_cpu_writeBack_fence_FM (_zz_235[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_239 ), //i + .io_cpu_flush_valid (_zz_236 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_240 ), //i + .io_mem_cmd_ready (_zz_237 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1819,18 +1838,18 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_381) + case(_zz_380) 2'b00 : begin - _zz_243 = DBusCachedPlugin_redoBranch_payload; + _zz_240 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_243 = CsrPlugin_jumpInterface_payload; + _zz_240 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_243 = BranchPlugin_jumpInterface_payload; + _zz_240 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_243 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_240 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2585,7 +2604,7 @@ module VexRiscv_inner ( end `endif - assign memory_MUL_LOW = ($signed(_zz_281) + $signed(_zz_289)); + assign memory_MUL_LOW = ($signed(_zz_280) + $signed(_zz_288)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2594,41 +2613,41 @@ module VexRiscv_inner ( assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_291; + assign execute_SHIFT_RIGHT = _zz_290; assign execute_REGFILE_WRITE_DATA = _zz_106; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_223[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_220[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_293[0]; - assign decode_IS_RS1_SIGNED = _zz_294[0]; - assign decode_IS_DIV = _zz_295[0]; + assign decode_IS_RS2_SIGNED = _zz_292[0]; + assign decode_IS_RS1_SIGNED = _zz_293[0]; + assign decode_IS_DIV = _zz_294[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_296[0]; + assign decode_IS_MUL = _zz_295[0]; assign decode_CfuPlugin_CFU_ENCODING = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_297[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_296[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_298[0]; + assign decode_IS_CSR = _zz_297[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_299[0]; - assign decode_MEMORY_MANAGMENT = _zz_300[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_298[0]; + assign decode_MEMORY_MANAGMENT = _zz_299[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_301[0]; + assign decode_MEMORY_WR = _zz_300[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_302[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_303[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_301[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_302[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2665,13 +2684,13 @@ module VexRiscv_inner ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_128; + assign execute_BRANCH_COND_RESULT = _zz_123; assign execute_BRANCH_CTRL = _zz_34; - assign decode_RS2_USE = _zz_304[0]; - assign decode_RS1_USE = _zz_305[0]; + assign decode_RS2_USE = _zz_303[0]; + assign decode_RS1_USE = _zz_304[0]; always @ (*) begin _zz_35 = execute_REGFILE_WRITE_DATA; - if(_zz_244)begin + if(_zz_241)begin _zz_35 = execute_CsrPlugin_readData; end end @@ -2684,28 +2703,28 @@ module VexRiscv_inner ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_117)begin - if((_zz_118 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_119; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_245)begin - if(_zz_246)begin - if(_zz_121)begin + if(_zz_242)begin + if(_zz_243)begin + if(_zz_116)begin decode_RS2 = _zz_55; end end end - if(_zz_247)begin + if(_zz_244)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_123)begin + if(_zz_118)begin decode_RS2 = _zz_36; end end end - if(_zz_248)begin + if(_zz_245)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_125)begin + if(_zz_120)begin decode_RS2 = _zz_35; end end @@ -2714,28 +2733,28 @@ module VexRiscv_inner ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_117)begin - if((_zz_118 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_119; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_245)begin - if(_zz_246)begin - if(_zz_120)begin + if(_zz_242)begin + if(_zz_243)begin + if(_zz_115)begin decode_RS1 = _zz_55; end end end - if(_zz_247)begin + if(_zz_244)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_122)begin + if(_zz_117)begin decode_RS1 = _zz_36; end end end - if(_zz_248)begin + if(_zz_245)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_124)begin + if(_zz_119)begin decode_RS1 = _zz_35; end end @@ -2760,7 +2779,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_36 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_249)begin + if(_zz_246)begin _zz_36 = memory_DivPlugin_div_result; end end @@ -2773,8 +2792,8 @@ module VexRiscv_inner ( assign _zz_39 = execute_PC; assign execute_SRC2_CTRL = _zz_40; assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_306[0]; - assign decode_SRC_ADD_ZERO = _zz_307[0]; + assign decode_SRC_USE_SUB_LESS = _zz_305[0]; + assign decode_SRC_ADD_ZERO = _zz_306[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_42; @@ -2792,25 +2811,25 @@ module VexRiscv_inner ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_308[0]; + decode_REGFILE_WRITE_VALID = _zz_307[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_382) == 32'h00000003),{(_zz_383 == _zz_384),{_zz_385,{_zz_386,_zz_387}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_381) == 32'h00000003),{(_zz_382 == _zz_383),{_zz_384,{_zz_385,_zz_386}}}}}}} != 22'h0); always @ (*) begin _zz_55 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_55 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_280) + case(_zz_279) 2'b00 : begin - _zz_55 = _zz_354; + _zz_55 = _zz_353; end default : begin - _zz_55 = _zz_355; + _zz_55 = _zz_354; end endcase end @@ -2829,32 +2848,32 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_309[0]; - assign decode_FLUSH_ALL = _zz_310[0]; + assign decode_MEMORY_ENABLE = _zz_308[0]; + assign decode_FLUSH_ALL = _zz_309[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_250)begin + if(_zz_247)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_251)begin + if(_zz_248)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_252)begin + if(_zz_249)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_253)begin + if(_zz_250)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2887,7 +2906,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_115 || _zz_116)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2900,7 +2919,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_254)begin + if(_zz_251)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2914,25 +2933,22 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_254)begin + if(_zz_251)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_239 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_236 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(((dataCache_1_io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin - execute_arbitration_haltItself = 1'b1; - end - if(_zz_255)begin + if(_zz_252)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_244)begin + if(_zz_241)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2942,7 +2958,13 @@ module VexRiscv_inner ( end end - assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + end + always @ (*) begin execute_arbitration_removeIt = 1'b0; if(CsrPlugin_selfException_valid)begin @@ -2968,7 +2990,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_249)begin + if(_zz_246)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2978,7 +3000,7 @@ module VexRiscv_inner ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_256)begin + if(_zz_253)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2992,7 +3014,7 @@ module VexRiscv_inner ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_256)begin + if(_zz_253)begin memory_arbitration_flushNext = 1'b1; end end @@ -3030,10 +3052,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_257)begin + if(_zz_254)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_258)begin + if(_zz_255)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3047,10 +3069,10 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_257)begin + if(_zz_254)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_258)begin + if(_zz_255)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3064,7 +3086,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_255)begin + if(_zz_252)begin CsrPlugin_inWfi = 1'b1; end end @@ -3072,21 +3094,21 @@ module VexRiscv_inner ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_257)begin + if(_zz_254)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_258)begin + if(_zz_255)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_257)begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_254)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_258)begin - case(_zz_259) + if(_zz_255)begin + case(_zz_256) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3102,11 +3124,11 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_59 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_60 = (_zz_59 & (~ _zz_311)); + assign _zz_60 = (_zz_59 & (~ _zz_310)); assign _zz_61 = _zz_60[3]; assign _zz_62 = (_zz_60[1] || _zz_61); assign _zz_63 = (_zz_60[2] || _zz_61); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_243; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_240; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3126,7 +3148,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_313); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_312); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3217,7 +3239,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_73 = _zz_314[11]; + assign _zz_73 = _zz_313[11]; always @ (*) begin _zz_74[18] = _zz_73; _zz_74[17] = _zz_73; @@ -3241,13 +3263,13 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_315[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_314[31])); if(_zz_79)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_75 = _zz_316[19]; + assign _zz_75 = _zz_315[19]; always @ (*) begin _zz_76[10] = _zz_75; _zz_76[9] = _zz_75; @@ -3262,7 +3284,7 @@ module VexRiscv_inner ( _zz_76[0] = _zz_75; end - assign _zz_77 = _zz_317[11]; + assign _zz_77 = _zz_316[11]; always @ (*) begin _zz_78[18] = _zz_77; _zz_78[17] = _zz_77; @@ -3288,16 +3310,16 @@ module VexRiscv_inner ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_79 = _zz_318[1]; + _zz_79 = _zz_317[1]; end default : begin - _zz_79 = _zz_319[1]; + _zz_79 = _zz_318[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_80 = _zz_320[19]; + assign _zz_80 = _zz_319[19]; always @ (*) begin _zz_81[10] = _zz_80; _zz_81[9] = _zz_80; @@ -3312,7 +3334,7 @@ module VexRiscv_inner ( _zz_81[0] = _zz_80; end - assign _zz_82 = _zz_321[11]; + assign _zz_82 = _zz_320[11]; always @ (*) begin _zz_83[18] = _zz_82; _zz_83[17] = _zz_82; @@ -3335,7 +3357,7 @@ module VexRiscv_inner ( _zz_83[0] = _zz_82; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_81,{{{_zz_400,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_83,{{{_zz_401,_zz_402},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_81,{{{_zz_399,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_83,{{{_zz_400,_zz_401},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3344,52 +3366,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_214 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_215 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_216 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_215; + assign _zz_211 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_212 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_213 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_212; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_219 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_220 = (CsrPlugin_privilege == 2'b00); + assign _zz_215 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_216 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_217 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_253)begin + if(_zz_250)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_251)begin + if(_zz_248)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_221 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_251)begin - _zz_221 = 1'b1; + _zz_218 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_248)begin + _zz_218 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_252)begin + if(_zz_249)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_250)begin + if(_zz_247)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_252)begin + if(_zz_249)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_250)begin + if(_zz_247)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3399,9 +3421,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_213 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_210 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_240 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_237 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3428,8 +3450,8 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_222 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_223 = execute_SRC_ADD; + assign _zz_219 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_220 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3444,27 +3466,27 @@ module VexRiscv_inner ( endcase end - assign _zz_239 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_224 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_225 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_224; + assign _zz_236 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_221 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_222 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_221; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_225; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_222; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_226 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_223 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_226 = 1'b1; + _zz_223 = 1'b1; end end - assign _zz_227 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_228 = (CsrPlugin_privilege == 2'b00); - assign _zz_229 = writeBack_REGFILE_WRITE_DATA; + assign _zz_224 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_225 = (CsrPlugin_privilege == 2'b00); + assign _zz_226 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_260)begin + if(_zz_257)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3474,14 +3496,14 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_260)begin + if(_zz_257)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end if(dataCache_1_io_cpu_redo)begin @@ -3493,16 +3515,16 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_260)begin + if(_zz_257)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_322}; - end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_323}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_321}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_322}; + end end end @@ -3574,7 +3596,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_278) + case(_zz_277) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_88; end @@ -3592,6 +3614,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; @@ -3600,6 +3623,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; @@ -3608,7 +3632,7 @@ module VexRiscv_inner ( assign _zz_94 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_95 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); assign _zz_96 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_91 = {(_zz_96 != 1'b0),{(_zz_96 != 1'b0),{((_zz_403 == _zz_404) != 1'b0),{(_zz_405 != 1'b0),{1'b0,{_zz_406,{_zz_407,_zz_408}}}}}}}; + assign _zz_91 = {(_zz_96 != 1'b0),{(_zz_96 != 1'b0),{((_zz_402 == _zz_403) != 1'b0),{(_zz_404 != 1'b0),{1'b0,{_zz_405,{_zz_406,_zz_407}}}}}}}; assign _zz_97 = _zz_91[2 : 1]; assign _zz_54 = _zz_97; assign _zz_98 = _zz_91[7 : 6]; @@ -3630,8 +3654,8 @@ module VexRiscv_inner ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_241; - assign decode_RegFilePlugin_rs2Data = _zz_242; + assign decode_RegFilePlugin_rs1Data = _zz_238; + assign decode_RegFilePlugin_rs2Data = _zz_239; always @ (*) begin lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); if(_zz_105)begin @@ -3639,8 +3663,20 @@ module VexRiscv_inner ( end end - assign lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_55; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; + if(_zz_105)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_55; + if(_zz_105)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -3661,7 +3697,7 @@ module VexRiscv_inner ( _zz_106 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_106 = {31'd0, _zz_324}; + _zz_106 = {31'd0, _zz_323}; end default : begin _zz_106 = execute_SRC_ADD_SUB; @@ -3675,18 +3711,18 @@ module VexRiscv_inner ( _zz_107 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_107 = {29'd0, _zz_325}; + _zz_107 = {29'd0, _zz_324}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_107 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_107 = {27'd0, _zz_326}; + _zz_107 = {27'd0, _zz_325}; end endcase end - assign _zz_108 = _zz_327[11]; + assign _zz_108 = _zz_326[11]; always @ (*) begin _zz_109[19] = _zz_108; _zz_109[18] = _zz_108; @@ -3710,7 +3746,7 @@ module VexRiscv_inner ( _zz_109[0] = _zz_108; end - assign _zz_110 = _zz_328[11]; + assign _zz_110 = _zz_327[11]; always @ (*) begin _zz_111[19] = _zz_110; _zz_111[18] = _zz_110; @@ -3752,7 +3788,7 @@ module VexRiscv_inner ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_329; + execute_SrcPlugin_addSub = _zz_328; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3832,175 +3868,180 @@ module VexRiscv_inner ( end always @ (*) begin - _zz_115 = 1'b0; - if(_zz_261)begin - if(_zz_262)begin - if(_zz_120)begin - _zz_115 = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_258)begin + if(_zz_259)begin + if(_zz_115)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_263)begin - if(_zz_264)begin - if(_zz_122)begin - _zz_115 = 1'b1; + if(_zz_260)begin + if(_zz_261)begin + if(_zz_117)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_265)begin - if(_zz_266)begin - if(_zz_124)begin - _zz_115 = 1'b1; + if(_zz_262)begin + if(_zz_263)begin + if(_zz_119)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_115 = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_116 = 1'b0; - if(_zz_261)begin - if(_zz_262)begin - if(_zz_121)begin - _zz_116 = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_258)begin + if(_zz_259)begin + if(_zz_116)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_263)begin - if(_zz_264)begin - if(_zz_123)begin - _zz_116 = 1'b1; + if(_zz_260)begin + if(_zz_261)begin + if(_zz_118)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_265)begin - if(_zz_266)begin - if(_zz_125)begin - _zz_116 = 1'b1; + if(_zz_262)begin + if(_zz_263)begin + if(_zz_120)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_116 = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_120 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_121 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_122 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_123 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_124 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_125 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_45 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_44[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_55; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_115 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_116 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_117 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_118 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_119 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_120 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_126 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_126 == 3'b000)) begin - _zz_127 = execute_BranchPlugin_eq; - end else if((_zz_126 == 3'b001)) begin - _zz_127 = (! execute_BranchPlugin_eq); - end else if((((_zz_126 & 3'b101) == 3'b101))) begin - _zz_127 = (! execute_SRC_LESS); + assign _zz_121 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_121 == 3'b000)) begin + _zz_122 = execute_BranchPlugin_eq; + end else if((_zz_121 == 3'b001)) begin + _zz_122 = (! execute_BranchPlugin_eq); + end else if((((_zz_121 & 3'b101) == 3'b101))) begin + _zz_122 = (! execute_SRC_LESS); end else begin - _zz_127 = execute_SRC_LESS; + _zz_122 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_128 = 1'b0; + _zz_123 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_128 = 1'b1; + _zz_123 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_128 = 1'b1; + _zz_123 = 1'b1; end default : begin - _zz_128 = _zz_127; + _zz_123 = _zz_122; end endcase end - assign _zz_129 = _zz_336[11]; - always @ (*) begin - _zz_130[19] = _zz_129; - _zz_130[18] = _zz_129; - _zz_130[17] = _zz_129; - _zz_130[16] = _zz_129; - _zz_130[15] = _zz_129; - _zz_130[14] = _zz_129; - _zz_130[13] = _zz_129; - _zz_130[12] = _zz_129; - _zz_130[11] = _zz_129; - _zz_130[10] = _zz_129; - _zz_130[9] = _zz_129; - _zz_130[8] = _zz_129; - _zz_130[7] = _zz_129; - _zz_130[6] = _zz_129; - _zz_130[5] = _zz_129; - _zz_130[4] = _zz_129; - _zz_130[3] = _zz_129; - _zz_130[2] = _zz_129; - _zz_130[1] = _zz_129; - _zz_130[0] = _zz_129; - end - - assign _zz_131 = _zz_337[19]; - always @ (*) begin - _zz_132[10] = _zz_131; - _zz_132[9] = _zz_131; - _zz_132[8] = _zz_131; - _zz_132[7] = _zz_131; - _zz_132[6] = _zz_131; - _zz_132[5] = _zz_131; - _zz_132[4] = _zz_131; - _zz_132[3] = _zz_131; - _zz_132[2] = _zz_131; - _zz_132[1] = _zz_131; - _zz_132[0] = _zz_131; - end - - assign _zz_133 = _zz_338[11]; - always @ (*) begin - _zz_134[18] = _zz_133; - _zz_134[17] = _zz_133; - _zz_134[16] = _zz_133; - _zz_134[15] = _zz_133; - _zz_134[14] = _zz_133; - _zz_134[13] = _zz_133; - _zz_134[12] = _zz_133; - _zz_134[11] = _zz_133; - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; + assign _zz_124 = _zz_335[11]; + always @ (*) begin + _zz_125[19] = _zz_124; + _zz_125[18] = _zz_124; + _zz_125[17] = _zz_124; + _zz_125[16] = _zz_124; + _zz_125[15] = _zz_124; + _zz_125[14] = _zz_124; + _zz_125[13] = _zz_124; + _zz_125[12] = _zz_124; + _zz_125[11] = _zz_124; + _zz_125[10] = _zz_124; + _zz_125[9] = _zz_124; + _zz_125[8] = _zz_124; + _zz_125[7] = _zz_124; + _zz_125[6] = _zz_124; + _zz_125[5] = _zz_124; + _zz_125[4] = _zz_124; + _zz_125[3] = _zz_124; + _zz_125[2] = _zz_124; + _zz_125[1] = _zz_124; + _zz_125[0] = _zz_124; + end + + assign _zz_126 = _zz_336[19]; + always @ (*) begin + _zz_127[10] = _zz_126; + _zz_127[9] = _zz_126; + _zz_127[8] = _zz_126; + _zz_127[7] = _zz_126; + _zz_127[6] = _zz_126; + _zz_127[5] = _zz_126; + _zz_127[4] = _zz_126; + _zz_127[3] = _zz_126; + _zz_127[2] = _zz_126; + _zz_127[1] = _zz_126; + _zz_127[0] = _zz_126; + end + + assign _zz_128 = _zz_337[11]; + always @ (*) begin + _zz_129[18] = _zz_128; + _zz_129[17] = _zz_128; + _zz_129[16] = _zz_128; + _zz_129[15] = _zz_128; + _zz_129[14] = _zz_128; + _zz_129[13] = _zz_128; + _zz_129[12] = _zz_128; + _zz_129[11] = _zz_128; + _zz_129[10] = _zz_128; + _zz_129[9] = _zz_128; + _zz_129[8] = _zz_128; + _zz_129[7] = _zz_128; + _zz_129[6] = _zz_128; + _zz_129[5] = _zz_128; + _zz_129[4] = _zz_128; + _zz_129[3] = _zz_128; + _zz_129[2] = _zz_128; + _zz_129[1] = _zz_128; + _zz_129[0] = _zz_128; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_135 = (_zz_339[1] ^ execute_RS1[1]); + _zz_130 = (_zz_338[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_135 = _zz_340[1]; + _zz_130 = _zz_339[1]; end default : begin - _zz_135 = _zz_341[1]; + _zz_130 = _zz_340[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_135); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_130); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4012,80 +4053,80 @@ module VexRiscv_inner ( endcase end - assign _zz_136 = _zz_342[11]; + assign _zz_131 = _zz_341[11]; always @ (*) begin - _zz_137[19] = _zz_136; - _zz_137[18] = _zz_136; - _zz_137[17] = _zz_136; - _zz_137[16] = _zz_136; - _zz_137[15] = _zz_136; - _zz_137[14] = _zz_136; - _zz_137[13] = _zz_136; - _zz_137[12] = _zz_136; - _zz_137[11] = _zz_136; - _zz_137[10] = _zz_136; - _zz_137[9] = _zz_136; - _zz_137[8] = _zz_136; - _zz_137[7] = _zz_136; - _zz_137[6] = _zz_136; - _zz_137[5] = _zz_136; - _zz_137[4] = _zz_136; - _zz_137[3] = _zz_136; - _zz_137[2] = _zz_136; - _zz_137[1] = _zz_136; - _zz_137[0] = _zz_136; + _zz_132[19] = _zz_131; + _zz_132[18] = _zz_131; + _zz_132[17] = _zz_131; + _zz_132[16] = _zz_131; + _zz_132[15] = _zz_131; + _zz_132[14] = _zz_131; + _zz_132[13] = _zz_131; + _zz_132[12] = _zz_131; + _zz_132[11] = _zz_131; + _zz_132[10] = _zz_131; + _zz_132[9] = _zz_131; + _zz_132[8] = _zz_131; + _zz_132[7] = _zz_131; + _zz_132[6] = _zz_131; + _zz_132[5] = _zz_131; + _zz_132[4] = _zz_131; + _zz_132[3] = _zz_131; + _zz_132[2] = _zz_131; + _zz_132[1] = _zz_131; + _zz_132[0] = _zz_131; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_137,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_132,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_139,{{{_zz_571,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_141,{{{_zz_572,_zz_573},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_134,{{{_zz_570,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_136,{{{_zz_571,_zz_572},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_345}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_344}; end end endcase end - assign _zz_138 = _zz_343[19]; - always @ (*) begin - _zz_139[10] = _zz_138; - _zz_139[9] = _zz_138; - _zz_139[8] = _zz_138; - _zz_139[7] = _zz_138; - _zz_139[6] = _zz_138; - _zz_139[5] = _zz_138; - _zz_139[4] = _zz_138; - _zz_139[3] = _zz_138; - _zz_139[2] = _zz_138; - _zz_139[1] = _zz_138; - _zz_139[0] = _zz_138; - end - - assign _zz_140 = _zz_344[11]; - always @ (*) begin - _zz_141[18] = _zz_140; - _zz_141[17] = _zz_140; - _zz_141[16] = _zz_140; - _zz_141[15] = _zz_140; - _zz_141[14] = _zz_140; - _zz_141[13] = _zz_140; - _zz_141[12] = _zz_140; - _zz_141[11] = _zz_140; - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; + assign _zz_133 = _zz_342[19]; + always @ (*) begin + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; + end + + assign _zz_135 = _zz_343[11]; + always @ (*) begin + _zz_136[18] = _zz_135; + _zz_136[17] = _zz_135; + _zz_136[16] = _zz_135; + _zz_136[15] = _zz_135; + _zz_136[14] = _zz_135; + _zz_136[13] = _zz_135; + _zz_136[12] = _zz_135; + _zz_136[11] = _zz_135; + _zz_136[10] = _zz_135; + _zz_136[9] = _zz_135; + _zz_136[8] = _zz_135; + _zz_136[7] = _zz_135; + _zz_136[6] = _zz_135; + _zz_136[5] = _zz_135; + _zz_136[4] = _zz_135; + _zz_136[3] = _zz_135; + _zz_136[2] = _zz_135; + _zz_136[1] = _zz_135; + _zz_136[0] = _zz_135; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -4102,18 +4143,18 @@ module VexRiscv_inner ( end end - assign _zz_142 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_143 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_144 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_137 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_138 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_139 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_145 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_146 = _zz_346[0]; - assign _zz_147 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_148 = _zz_348[0]; + assign _zz_140 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_141 = _zz_345[0]; + assign _zz_142 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_143 = _zz_347[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_254)begin + if(_zz_251)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4133,7 +4174,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_256)begin + if(_zz_253)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4194,7 +4235,7 @@ module VexRiscv_inner ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4282,6 +4323,16 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end if(execute_CsrPlugin_csr_2820)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4354,7 +4405,7 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + if(_zz_264)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4373,20 +4424,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_267)begin + if(_zz_265)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_268)begin + if(_zz_266)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_267)begin + if(_zz_265)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_268)begin + if(_zz_266)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4399,13 +4450,25 @@ module VexRiscv_inner ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_264)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_264)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_279) + case(_zz_278) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4418,49 +4481,49 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_350; + assign execute_CfuPlugin_functionsIds_0 = _zz_349; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_165 = _zz_351[11]; - always @ (*) begin - _zz_166[19] = _zz_165; - _zz_166[18] = _zz_165; - _zz_166[17] = _zz_165; - _zz_166[16] = _zz_165; - _zz_166[15] = _zz_165; - _zz_166[14] = _zz_165; - _zz_166[13] = _zz_165; - _zz_166[12] = _zz_165; - _zz_166[11] = _zz_165; - _zz_166[10] = _zz_165; - _zz_166[9] = _zz_165; - _zz_166[8] = _zz_165; - _zz_166[7] = _zz_165; - _zz_166[6] = _zz_165; - _zz_166[5] = _zz_165; - _zz_166[4] = _zz_165; - _zz_166[3] = _zz_165; - _zz_166[2] = _zz_165; - _zz_166[1] = _zz_165; - _zz_166[0] = _zz_165; + assign _zz_160 = _zz_350[11]; + always @ (*) begin + _zz_161[19] = _zz_160; + _zz_161[18] = _zz_160; + _zz_161[17] = _zz_160; + _zz_161[16] = _zz_160; + _zz_161[15] = _zz_160; + _zz_161[14] = _zz_160; + _zz_161[13] = _zz_160; + _zz_161[12] = _zz_160; + _zz_161[11] = _zz_160; + _zz_161[10] = _zz_160; + _zz_161[9] = _zz_160; + _zz_161[8] = _zz_160; + _zz_161[7] = _zz_160; + _zz_161[6] = _zz_160; + _zz_161[5] = _zz_160; + _zz_161[4] = _zz_160; + _zz_161[3] = _zz_160; + _zz_161[2] = _zz_160; + _zz_161[1] = _zz_160; + _zz_161[0] = _zz_160; end always @ (*) begin case(execute_CfuPlugin_CFU_ENCODING) `Input2Kind_defaultEncoding_RS : begin - _zz_167 = execute_RS2; + _zz_162 = execute_RS2; end default : begin - _zz_167 = {_zz_166,execute_INSTRUCTION[31 : 20]}; + _zz_162 = {_zz_161,execute_INSTRUCTION[31 : 20]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_167; - assign CfuPlugin_bus_rsp_ready = ((1'b1 && (! memory_CfuPlugin_rsp_valid)) || memory_CfuPlugin_rsp_ready); - assign memory_CfuPlugin_rsp_valid = CfuPlugin_bus_rsp_m2sPipe_rValid; - assign memory_CfuPlugin_rsp_payload_response_ok = CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; - assign memory_CfuPlugin_rsp_payload_outputs_0 = CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_162; + assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); + assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); + assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); always @ (*) begin CfuPlugin_joinException_valid = 1'b0; if(memory_CfuPlugin_CFU_IN_FLIGHT)begin @@ -4482,7 +4545,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_269) + case(_zz_267) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4496,7 +4559,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_269) + case(_zz_267) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4515,12 +4578,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_352) + $signed(_zz_353)); + assign writeBack_MulPlugin_result = ($signed(_zz_351) + $signed(_zz_352)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_249)begin - if(_zz_270)begin + if(_zz_246)begin + if(_zz_268)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4528,7 +4591,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_271)begin + if(_zz_269)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4539,28 +4602,28 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_357); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_356); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_168 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_168[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_358); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_359 : _zz_360); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_361[31:0]; - assign _zz_169 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_170 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_171 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_163 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_163[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_357); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_358 : _zz_359); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_360[31:0]; + assign _zz_164 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_165 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_166 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_172[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_172[31 : 0] = execute_RS1; + _zz_167[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_167[31 : 0] = execute_RS1; end - assign _zz_174 = (_zz_173 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_174 != 32'h0); + assign _zz_169 = (_zz_168 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_169 != 32'h0); assign _zz_29 = decode_SRC1_CTRL; assign _zz_27 = _zz_54; assign _zz_41 = decode_to_execute_SRC1_CTRL; @@ -4612,258 +4675,272 @@ module VexRiscv_inner ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_175 = 32'h0; + _zz_170 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_175[12 : 0] = 13'h1000; - _zz_175[25 : 20] = 6'h20; + _zz_170[12 : 0] = 13'h1000; + _zz_170[25 : 20] = 6'h20; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_171 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_176[3 : 0] = 4'b1011; + _zz_171[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_177[4 : 0] = 5'h16; + _zz_172[4 : 0] = 5'h16; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_178[5 : 0] = 6'h21; + _zz_173[5 : 0] = 6'h21; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_179[31 : 30] = CsrPlugin_misa_base; - _zz_179[25 : 0] = CsrPlugin_misa_extensions; + _zz_174[31 : 30] = CsrPlugin_misa_base; + _zz_174[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_180[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_180[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_180[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_175[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_175[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_175[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_181[11 : 11] = CsrPlugin_mip_MEIP; - _zz_181[7 : 7] = CsrPlugin_mip_MTIP; - _zz_181[3 : 3] = CsrPlugin_mip_MSIP; + _zz_176[11 : 11] = CsrPlugin_mip_MEIP; + _zz_176[7 : 7] = CsrPlugin_mip_MTIP; + _zz_176[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_182[11 : 11] = CsrPlugin_mie_MEIE; - _zz_182[7 : 7] = CsrPlugin_mie_MTIE; - _zz_182[3 : 3] = CsrPlugin_mie_MSIE; + _zz_177[11 : 11] = CsrPlugin_mie_MEIE; + _zz_177[7 : 7] = CsrPlugin_mie_MTIE; + _zz_177[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_183[31 : 2] = CsrPlugin_mtvec_base; - _zz_183[1 : 0] = CsrPlugin_mtvec_mode; + _zz_178[31 : 2] = CsrPlugin_mtvec_base; + _zz_178[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_184[31 : 0] = CsrPlugin_mepc; + _zz_179[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_185[31 : 0] = CsrPlugin_mscratch; + _zz_180[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_186[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_186[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_181[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_181[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_187[31 : 0] = CsrPlugin_mtval; + _zz_182[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_188[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_183[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_189[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_184[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_190[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_185[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_191[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_186[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_192[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_187[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_193[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_188[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_189 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_189[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_190 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_190[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_2820)begin - _zz_194[31 : 0] = _zz_149; + _zz_191[31 : 0] = _zz_144; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_2822)begin - _zz_195[31 : 0] = _zz_151; + _zz_192[31 : 0] = _zz_146; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_2824)begin - _zz_196[31 : 0] = _zz_153; + _zz_193[31 : 0] = _zz_148; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_2826)begin - _zz_197[31 : 0] = _zz_155; + _zz_194[31 : 0] = _zz_150; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_2828)begin - _zz_198[31 : 0] = _zz_157; + _zz_195[31 : 0] = _zz_152; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_2830)begin - _zz_199[31 : 0] = _zz_159; + _zz_196[31 : 0] = _zz_154; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_2832)begin - _zz_200[31 : 0] = _zz_161; + _zz_197[31 : 0] = _zz_156; end end always @ (*) begin - _zz_201 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_2834)begin - _zz_201[31 : 0] = _zz_163; + _zz_198[31 : 0] = _zz_158; end end always @ (*) begin - _zz_202 = 32'h0; + _zz_199 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_202[31 : 0] = _zz_173; + _zz_199[31 : 0] = _zz_168; end end always @ (*) begin - _zz_203 = 32'h0; + _zz_200 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_203[31 : 0] = _zz_174; + _zz_200[31 : 0] = _zz_169; end end - assign execute_CsrPlugin_readData = (((((_zz_175 | _zz_176) | (_zz_177 | _zz_178)) | ((_zz_574 | _zz_179) | (_zz_180 | _zz_181))) | (((_zz_182 | _zz_183) | (_zz_184 | _zz_185)) | ((_zz_186 | _zz_187) | (_zz_188 | _zz_189)))) | ((((_zz_190 | _zz_191) | (_zz_192 | _zz_193)) | ((_zz_194 | _zz_195) | (_zz_196 | _zz_197))) | (((_zz_198 | _zz_199) | (_zz_200 | _zz_201)) | (_zz_202 | _zz_203)))); - assign iBusWishbone_ADR = {_zz_378,_zz_204}; - assign iBusWishbone_CTI = ((_zz_204 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_170 | _zz_171) | (_zz_172 | _zz_173)) | ((_zz_573 | _zz_174) | (_zz_175 | _zz_176))) | (((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_181 | _zz_182) | (_zz_183 | _zz_184)))) | ((((_zz_185 | _zz_186) | (_zz_187 | _zz_188)) | ((_zz_189 | _zz_190) | (_zz_191 | _zz_192))) | (((_zz_193 | _zz_194) | (_zz_195 | _zz_196)) | ((_zz_197 | _zz_198) | (_zz_199 | _zz_200))))); + assign iBusWishbone_ADR = {_zz_377,_zz_201}; + assign iBusWishbone_CTI = ((_zz_201 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_272)begin + if(_zz_270)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_272)begin + if(_zz_270)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_205; + assign iBus_rsp_valid = _zz_202; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_211 = (dBus_cmd_payload_length != 3'b000); - assign _zz_207 = dBus_cmd_valid; - assign _zz_209 = dBus_cmd_payload_wr; - assign _zz_210 = (_zz_206 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_208 && (_zz_209 || _zz_210)); - assign dBusWishbone_ADR = ((_zz_211 ? {{dBus_cmd_payload_address[31 : 5],_zz_206},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_211 ? (_zz_210 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_208 = (dBus_cmd_payload_length != 3'b000); + assign _zz_204 = dBus_cmd_valid; + assign _zz_206 = dBus_cmd_payload_wr; + assign _zz_207 = (_zz_203 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_205 && (_zz_206 || _zz_207)); + assign dBusWishbone_ADR = ((_zz_208 ? {{dBus_cmd_payload_address[31 : 5],_zz_203},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_208 ? (_zz_207 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_209 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_209; + assign dBusWishbone_SEL = (_zz_206 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_206; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_208 = (_zz_207 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_207; - assign dBusWishbone_STB = _zz_207; - assign dBus_rsp_valid = _zz_212; + assign _zz_205 = (_zz_204 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_204; + assign dBusWishbone_STB = _zz_204; + assign dBus_rsp_valid = _zz_209; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4886,7 +4963,7 @@ module VexRiscv_inner ( DBusCachedPlugin_rspCounter <= _zz_85; DBusCachedPlugin_rspCounter <= 32'h0; _zz_105 <= 1'b1; - _zz_117 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4908,19 +4985,17 @@ module VexRiscv_inner ( execute_CsrPlugin_wfiWake <= 1'b0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_m2sPipe_rValid <= 1'b0; + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_173 <= 32'h0; + _zz_168 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; - memory_to_writeBack_INSTRUCTION <= 32'h0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_204 <= 3'b000; - _zz_205 <= 1'b0; - _zz_206 <= 3'b000; - _zz_212 <= 1'b0; + _zz_201 <= 3'b000; + _zz_202 <= 1'b0; + _zz_203 <= 3'b000; + _zz_209 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5001,7 +5076,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_273)begin + if(_zz_271)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5011,7 +5086,7 @@ module VexRiscv_inner ( DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end _zz_105 <= 1'b0; - _zz_117 <= (_zz_45 && writeBack_arbitration_isFiring); + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5033,14 +5108,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_274)begin - if(_zz_275)begin + if(_zz_272)begin + if(_zz_273)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_276)begin + if(_zz_274)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_277)begin + if(_zz_275)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5065,7 +5140,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_257)begin + if(_zz_254)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5076,8 +5151,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_258)begin - case(_zz_259) + if(_zz_255)begin + case(_zz_256) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5087,7 +5162,7 @@ module VexRiscv_inner ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_144,{_zz_143,_zz_142}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_139,{_zz_138,_zz_137}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -5100,16 +5175,13 @@ module VexRiscv_inner ( if((! execute_arbitration_isStuckByOthers))begin execute_CfuPlugin_fired <= 1'b0; end - if(CfuPlugin_bus_rsp_ready)begin - CfuPlugin_bus_rsp_m2sPipe_rValid <= CfuPlugin_bus_rsp_valid; - end - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + if(memory_CfuPlugin_rsp_ready)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_36; + if(_zz_276)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if((! memory_arbitration_isStuck))begin execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= execute_CfuPlugin_CFU_IN_FLIGHT; end @@ -5140,35 +5212,35 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_371[0]; - CsrPlugin_mstatus_MIE <= _zz_372[0]; + CsrPlugin_mstatus_MPIE <= _zz_370[0]; + CsrPlugin_mstatus_MIE <= _zz_371[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_374[0]; - CsrPlugin_mie_MTIE <= _zz_375[0]; - CsrPlugin_mie_MSIE <= _zz_376[0]; + CsrPlugin_mie_MEIE <= _zz_373[0]; + CsrPlugin_mie_MTIE <= _zz_374[0]; + CsrPlugin_mie_MSIE <= _zz_375[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_173 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_272)begin + if(_zz_270)begin if(iBusWishbone_ACK)begin - _zz_204 <= (_zz_204 + 3'b001); + _zz_201 <= (_zz_201 + 3'b001); end end - _zz_205 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_207 && _zz_208))begin - _zz_206 <= (_zz_206 + 3'b001); - if(_zz_210)begin - _zz_206 <= 3'b000; + _zz_202 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_204 && _zz_205))begin + _zz_203 <= (_zz_203 + 3'b001); + if(_zz_207)begin + _zz_203 <= 3'b000; end end - _zz_212 <= ((_zz_207 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_209 <= ((_zz_204 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5182,7 +5254,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_273)begin + if(_zz_271)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5200,8 +5272,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - _zz_118 <= _zz_44[11 : 7]; - _zz_119 <= _zz_55; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5209,37 +5281,37 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_254)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_146 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_146 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_251)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_141 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_141 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_256)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(_zz_253)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_143 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_143 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); end if(DBusCachedPlugin_exceptionBus_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_274)begin - if(_zz_275)begin + if(_zz_272)begin + if(_zz_273)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_276)begin + if(_zz_274)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_277)begin + if(_zz_275)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_257)begin + if(_zz_254)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5253,33 +5325,33 @@ module VexRiscv_inner ( end endcase end - if(_zz_150[0])begin - _zz_149 <= (_zz_149 + 32'h00000001); + if(_zz_145[0])begin + _zz_144 <= (_zz_144 + 32'h00000001); end - if(_zz_152[0])begin - _zz_151 <= (_zz_151 + 32'h00000001); + if(_zz_147[0])begin + _zz_146 <= (_zz_146 + 32'h00000001); end - if(_zz_154[0])begin - _zz_153 <= (_zz_153 + 32'h00000001); + if(_zz_149[0])begin + _zz_148 <= (_zz_148 + 32'h00000001); end - if(_zz_156[0])begin - _zz_155 <= (_zz_155 + 32'h00000001); + if(_zz_151[0])begin + _zz_150 <= (_zz_150 + 32'h00000001); end - if(_zz_158[0])begin - _zz_157 <= (_zz_157 + 32'h00000001); + if(_zz_153[0])begin + _zz_152 <= (_zz_152 + 32'h00000001); end - if(_zz_160[0])begin - _zz_159 <= (_zz_159 + 32'h00000001); + if(_zz_155[0])begin + _zz_154 <= (_zz_154 + 32'h00000001); end - if(_zz_162[0])begin - _zz_161 <= (_zz_161 + 32'h00000001); + if(_zz_157[0])begin + _zz_156 <= (_zz_156 + 32'h00000001); end - if(_zz_164[0])begin - _zz_163 <= (_zz_163 + 32'h00000001); + if(_zz_159[0])begin + _zz_158 <= (_zz_158 + 32'h00000001); end - if(CfuPlugin_bus_rsp_ready)begin - CfuPlugin_bus_rsp_m2sPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + if(_zz_276)begin + CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end if((memory_DivPlugin_div_counter_value == 6'h20))begin memory_DivPlugin_div_done <= 1'b1; @@ -5287,20 +5359,20 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_249)begin - if(_zz_270)begin + if(_zz_246)begin + if(_zz_268)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_362[31:0]; + memory_DivPlugin_div_result <= _zz_361[31:0]; end end end - if(_zz_271)begin + if(_zz_269)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_171 ? (~ _zz_172) : _zz_172) + _zz_368); - memory_DivPlugin_rs2 <= ((_zz_170 ? (~ execute_RS2) : execute_RS2) + _zz_370); - memory_DivPlugin_div_needRevert <= ((_zz_171 ^ (_zz_170 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_166 ? (~ _zz_167) : _zz_167) + _zz_367); + memory_DivPlugin_rs2 <= ((_zz_165 ? (~ execute_RS2) : execute_RS2) + _zz_369); + memory_DivPlugin_div_needRevert <= ((_zz_166 ^ (_zz_165 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5318,6 +5390,9 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end if((! execute_arbitration_isStuck))begin decode_to_execute_FORMAL_PC_NEXT <= _zz_58; end @@ -5462,6 +5537,9 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin execute_to_memory_REGFILE_WRITE_DATA <= _zz_35; end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_36; + end if((! memory_arbitration_isStuck))begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end @@ -5549,6 +5627,12 @@ module VexRiscv_inner ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); end @@ -5605,7 +5689,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_373[0]; + CsrPlugin_mip_MSIP <= _zz_372[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5626,7 +5710,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_377[0]; + CsrPlugin_mcause_interrupt <= _zz_376[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5657,82 +5741,82 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_2820)begin if(execute_CsrPlugin_writeEnable)begin - _zz_149 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_144 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2821)begin if(execute_CsrPlugin_writeEnable)begin - _zz_150 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_145 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2822)begin if(execute_CsrPlugin_writeEnable)begin - _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2823)begin if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_147 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2824)begin if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_148 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2825)begin if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_149 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2826)begin if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_150 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2827)begin if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2828)begin if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2829)begin if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2830)begin if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2831)begin if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2832)begin if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2833)begin if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2834)begin if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2835)begin if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -5750,12 +5834,14 @@ module DataCache ( input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, input io_cpu_memory_isValid, input io_cpu_memory_isStuck, output io_cpu_memory_isWrite, input [31:0] io_cpu_memory_address, input [31:0] io_cpu_memory_mmuRsp_physicalAddress, input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, input io_cpu_memory_mmuRsp_allowRead, input io_cpu_memory_mmuRsp_allowWrite, input io_cpu_memory_mmuRsp_allowExecute, @@ -5896,6 +5982,7 @@ module DataCache ( reg stageB_mmuRspFreeze; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; reg stageB_mmuRsp_allowRead; reg stageB_mmuRsp_allowWrite; reg stageB_mmuRsp_allowExecute; @@ -5930,6 +6017,8 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; wire stageB_bypassCache; reg [1:0] _zz_18; reg loader_valid; @@ -5944,6 +6033,7 @@ module DataCache ( wire loader_kill; reg loader_killReg; wire loader_done; + reg loader_valid_regNext; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; @@ -6111,7 +6201,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'h0; + tagsReadCmd_payload = 7'bxxxxxxx; if(_zz_23)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -6125,7 +6215,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'h0; + dataReadCmd_payload = 10'bxxxxxxxxxx; if(_zz_23)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -6155,7 +6245,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; + tagsWriteCmd_payload_address = 7'bxxxxxxx; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -6182,7 +6272,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -6214,7 +6304,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'h0; + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -6224,7 +6314,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'h0; + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end @@ -6371,6 +6461,8 @@ module DataCache ( end end + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); always @ (*) begin io_cpu_redo = 1'b0; if(io_cpu_writeBack_isValid)begin @@ -6387,7 +6479,7 @@ module DataCache ( if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin io_cpu_redo = 1'b1; end - if(loader_valid)begin + if((loader_valid && (! loader_valid_regNext)))begin io_cpu_redo = 1'b1; end end @@ -6397,11 +6489,11 @@ module DataCache ( if(stageB_bypassCache)begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_18) != 2'b00); + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_18) != 2'b00) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; always @ (*) begin @@ -6509,6 +6601,7 @@ module DataCache ( assign loader_kill = 1'b0; assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; always @ (posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; @@ -6540,6 +6633,7 @@ module DataCache ( if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; @@ -6588,6 +6682,7 @@ module DataCache ( if(stageB_flusher_start)begin stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; end + loader_valid_regNext <= loader_valid; end always @ (posedge clk) begin @@ -6620,7 +6715,7 @@ module DataCache ( end `ifndef SYNTHESIS `ifdef FORMAL - assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin $display("FAILURE writeBack stuck by another plugin is not allowed"); @@ -6664,6 +6759,7 @@ module InstructionCache ( output [31:0] io_cpu_fetch_data, input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, input io_cpu_fetch_mmuRsp_allowRead, input io_cpu_fetch_mmuRsp_allowWrite, input io_cpu_fetch_mmuRsp_allowExecute, @@ -6772,6 +6868,7 @@ module InstructionCache ( reg [31:0] io_cpu_fetch_data_regNextWhen; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; reg decodeStage_mmuRsp_allowRead; reg decodeStage_mmuRsp_allowWrite; reg decodeStage_mmuRsp_allowExecute; @@ -6971,9 +7068,9 @@ module InstructionCache ( assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; always @ (posedge clk) begin if(reset) begin @@ -7032,6 +7129,7 @@ module InstructionCache ( if((! io_cpu_decode_isStuck))begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index b4f2242..46a5db4 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.2 git head : f022529bb419c7a04f9ba1b61e931127b7220919 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv -// Git hash : f022529bb419c7a04f9ba1b61e931127b7220919 +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 `define Input2Kind_defaultEncoding_type [0:0] @@ -54,7 +54,7 @@ module VexRiscv_inner ( input softwareInterrupt, output CfuPlugin_bus_cmd_valid, input CfuPlugin_bus_cmd_ready, - output [2:0] CfuPlugin_bus_cmd_payload_function_id, + output [19:0] CfuPlugin_bus_cmd_payload_function_id, output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, input CfuPlugin_bus_rsp_valid, @@ -95,37 +95,37 @@ module VexRiscv_inner ( input reset, input debugReset ); + wire _zz_213; + wire _zz_214; + wire _zz_215; wire _zz_216; wire _zz_217; wire _zz_218; wire _zz_219; wire _zz_220; - wire _zz_221; + reg _zz_221; wire _zz_222; - wire _zz_223; - reg _zz_224; - wire _zz_225; - wire [31:0] _zz_226; + wire [31:0] _zz_223; + wire _zz_224; + wire [31:0] _zz_225; + reg _zz_226; wire _zz_227; - wire [31:0] _zz_228; - reg _zz_229; + wire _zz_228; + wire [31:0] _zz_229; wire _zz_230; wire _zz_231; - wire [31:0] _zz_232; + wire _zz_232; wire _zz_233; wire _zz_234; wire _zz_235; wire _zz_236; wire _zz_237; - wire _zz_238; + wire [3:0] _zz_238; wire _zz_239; wire _zz_240; - wire [3:0] _zz_241; - wire _zz_242; - wire _zz_243; - reg [31:0] _zz_244; - reg [31:0] _zz_245; - reg [31:0] _zz_246; + reg [31:0] _zz_241; + reg [31:0] _zz_242; + reg [31:0] _zz_243; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -139,6 +139,7 @@ module VexRiscv_inner ( wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; wire dataCache_1_io_cpu_memory_isWrite; wire dataCache_1_io_cpu_writeBack_haltIt; wire [31:0] dataCache_1_io_cpu_writeBack_data; @@ -157,6 +158,9 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_244; + wire _zz_245; + wire _zz_246; wire _zz_247; wire _zz_248; wire _zz_249; @@ -172,10 +176,10 @@ module VexRiscv_inner ( wire _zz_259; wire _zz_260; wire _zz_261; - wire _zz_262; + wire [1:0] _zz_262; wire _zz_263; wire _zz_264; - wire [1:0] _zz_265; + wire _zz_265; wire _zz_266; wire _zz_267; wire _zz_268; @@ -183,33 +187,33 @@ module VexRiscv_inner ( wire _zz_270; wire _zz_271; wire _zz_272; - wire _zz_273; + wire [1:0] _zz_273; wire _zz_274; - wire [1:0] _zz_275; - wire _zz_276; + wire _zz_275; + wire [5:0] _zz_276; wire _zz_277; - wire [5:0] _zz_278; + wire _zz_278; wire _zz_279; wire _zz_280; wire _zz_281; wire _zz_282; wire _zz_283; - wire _zz_284; - wire [1:0] _zz_285; - wire _zz_286; - wire [1:0] _zz_287; + wire [1:0] _zz_284; + wire _zz_285; + wire [1:0] _zz_286; + wire [51:0] _zz_287; wire [51:0] _zz_288; wire [51:0] _zz_289; - wire [51:0] _zz_290; - wire [32:0] _zz_291; - wire [51:0] _zz_292; - wire [49:0] _zz_293; - wire [51:0] _zz_294; - wire [49:0] _zz_295; - wire [51:0] _zz_296; - wire [32:0] _zz_297; - wire [31:0] _zz_298; - wire [32:0] _zz_299; + wire [32:0] _zz_290; + wire [51:0] _zz_291; + wire [49:0] _zz_292; + wire [51:0] _zz_293; + wire [49:0] _zz_294; + wire [51:0] _zz_295; + wire [32:0] _zz_296; + wire [31:0] _zz_297; + wire [32:0] _zz_298; + wire [0:0] _zz_299; wire [0:0] _zz_300; wire [0:0] _zz_301; wire [0:0] _zz_302; @@ -228,135 +232,135 @@ module VexRiscv_inner ( wire [0:0] _zz_315; wire [0:0] _zz_316; wire [0:0] _zz_317; - wire [0:0] _zz_318; - wire [3:0] _zz_319; - wire [2:0] _zz_320; - wire [31:0] _zz_321; - wire [11:0] _zz_322; - wire [31:0] _zz_323; - wire [19:0] _zz_324; - wire [11:0] _zz_325; + wire [3:0] _zz_318; + wire [2:0] _zz_319; + wire [31:0] _zz_320; + wire [11:0] _zz_321; + wire [31:0] _zz_322; + wire [19:0] _zz_323; + wire [11:0] _zz_324; + wire [31:0] _zz_325; wire [31:0] _zz_326; - wire [31:0] _zz_327; - wire [19:0] _zz_328; - wire [11:0] _zz_329; + wire [19:0] _zz_327; + wire [11:0] _zz_328; + wire [2:0] _zz_329; wire [2:0] _zz_330; - wire [2:0] _zz_331; - wire [0:0] _zz_332; - wire [2:0] _zz_333; - wire [4:0] _zz_334; + wire [0:0] _zz_331; + wire [2:0] _zz_332; + wire [4:0] _zz_333; + wire [11:0] _zz_334; wire [11:0] _zz_335; - wire [11:0] _zz_336; + wire [31:0] _zz_336; wire [31:0] _zz_337; wire [31:0] _zz_338; wire [31:0] _zz_339; wire [31:0] _zz_340; wire [31:0] _zz_341; wire [31:0] _zz_342; - wire [31:0] _zz_343; - wire [11:0] _zz_344; - wire [19:0] _zz_345; - wire [11:0] _zz_346; + wire [11:0] _zz_343; + wire [19:0] _zz_344; + wire [11:0] _zz_345; + wire [31:0] _zz_346; wire [31:0] _zz_347; wire [31:0] _zz_348; - wire [31:0] _zz_349; - wire [11:0] _zz_350; - wire [19:0] _zz_351; - wire [11:0] _zz_352; - wire [2:0] _zz_353; + wire [11:0] _zz_349; + wire [19:0] _zz_350; + wire [11:0] _zz_351; + wire [2:0] _zz_352; + wire [1:0] _zz_353; wire [1:0] _zz_354; wire [1:0] _zz_355; wire [1:0] _zz_356; - wire [1:0] _zz_357; - wire [2:0] _zz_358; - wire [11:0] _zz_359; + wire [19:0] _zz_357; + wire [11:0] _zz_358; + wire [65:0] _zz_359; wire [65:0] _zz_360; - wire [65:0] _zz_361; + wire [31:0] _zz_361; wire [31:0] _zz_362; - wire [31:0] _zz_363; - wire [0:0] _zz_364; - wire [5:0] _zz_365; - wire [32:0] _zz_366; + wire [0:0] _zz_363; + wire [5:0] _zz_364; + wire [32:0] _zz_365; + wire [31:0] _zz_366; wire [31:0] _zz_367; - wire [31:0] _zz_368; + wire [32:0] _zz_368; wire [32:0] _zz_369; wire [32:0] _zz_370; wire [32:0] _zz_371; - wire [32:0] _zz_372; - wire [0:0] _zz_373; - wire [32:0] _zz_374; - wire [0:0] _zz_375; - wire [32:0] _zz_376; - wire [0:0] _zz_377; - wire [31:0] _zz_378; + wire [0:0] _zz_372; + wire [32:0] _zz_373; + wire [0:0] _zz_374; + wire [32:0] _zz_375; + wire [0:0] _zz_376; + wire [31:0] _zz_377; + wire [0:0] _zz_378; wire [0:0] _zz_379; wire [0:0] _zz_380; wire [0:0] _zz_381; wire [0:0] _zz_382; wire [0:0] _zz_383; wire [0:0] _zz_384; - wire [0:0] _zz_385; - wire [26:0] _zz_386; + wire [26:0] _zz_385; + wire _zz_386; wire _zz_387; - wire _zz_388; - wire [1:0] _zz_389; + wire [1:0] _zz_388; + wire [31:0] _zz_389; wire [31:0] _zz_390; wire [31:0] _zz_391; - wire [31:0] _zz_392; - wire _zz_393; - wire [0:0] _zz_394; - wire [14:0] _zz_395; + wire _zz_392; + wire [0:0] _zz_393; + wire [14:0] _zz_394; + wire [31:0] _zz_395; wire [31:0] _zz_396; wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire _zz_399; - wire [0:0] _zz_400; - wire [8:0] _zz_401; + wire _zz_398; + wire [0:0] _zz_399; + wire [8:0] _zz_400; + wire [31:0] _zz_401; wire [31:0] _zz_402; wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [2:0] _zz_407; + wire _zz_404; + wire [0:0] _zz_405; + wire [2:0] _zz_406; + wire _zz_407; wire _zz_408; wire _zz_409; - wire _zz_410; - wire [31:0] _zz_411; + wire [31:0] _zz_410; + wire [0:0] _zz_411; wire [0:0] _zz_412; - wire [0:0] _zz_413; - wire _zz_414; - wire [0:0] _zz_415; - wire [28:0] _zz_416; + wire _zz_413; + wire [0:0] _zz_414; + wire [28:0] _zz_415; + wire [0:0] _zz_416; wire [0:0] _zz_417; wire [0:0] _zz_418; wire [0:0] _zz_419; - wire [0:0] _zz_420; - wire _zz_421; - wire [0:0] _zz_422; - wire [23:0] _zz_423; + wire _zz_420; + wire [0:0] _zz_421; + wire [23:0] _zz_422; + wire [31:0] _zz_423; wire [31:0] _zz_424; wire [31:0] _zz_425; - wire [31:0] _zz_426; + wire _zz_426; wire _zz_427; - wire _zz_428; + wire [0:0] _zz_428; wire [0:0] _zz_429; wire [0:0] _zz_430; wire [0:0] _zz_431; - wire [0:0] _zz_432; - wire _zz_433; - wire [0:0] _zz_434; - wire [20:0] _zz_435; + wire _zz_432; + wire [0:0] _zz_433; + wire [20:0] _zz_434; + wire [31:0] _zz_435; wire [31:0] _zz_436; - wire [31:0] _zz_437; + wire _zz_437; wire _zz_438; - wire _zz_439; - wire [0:0] _zz_440; - wire [1:0] _zz_441; + wire [0:0] _zz_439; + wire [1:0] _zz_440; + wire [0:0] _zz_441; wire [0:0] _zz_442; - wire [0:0] _zz_443; - wire _zz_444; - wire [0:0] _zz_445; - wire [17:0] _zz_446; + wire _zz_443; + wire [0:0] _zz_444; + wire [17:0] _zz_445; + wire [31:0] _zz_446; wire [31:0] _zz_447; wire [31:0] _zz_448; wire [31:0] _zz_449; @@ -364,85 +368,85 @@ module VexRiscv_inner ( wire [31:0] _zz_451; wire [31:0] _zz_452; wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire _zz_455; + wire _zz_454; + wire [1:0] _zz_455; wire [1:0] _zz_456; - wire [1:0] _zz_457; - wire _zz_458; - wire [0:0] _zz_459; - wire [14:0] _zz_460; + wire _zz_457; + wire [0:0] _zz_458; + wire [14:0] _zz_459; + wire [31:0] _zz_460; wire [31:0] _zz_461; wire [31:0] _zz_462; wire [31:0] _zz_463; wire [31:0] _zz_464; wire [31:0] _zz_465; - wire [31:0] _zz_466; - wire [0:0] _zz_467; - wire [1:0] _zz_468; + wire [0:0] _zz_466; + wire [1:0] _zz_467; + wire [4:0] _zz_468; wire [4:0] _zz_469; - wire [4:0] _zz_470; - wire _zz_471; - wire [0:0] _zz_472; - wire [11:0] _zz_473; + wire _zz_470; + wire [0:0] _zz_471; + wire [11:0] _zz_472; + wire [31:0] _zz_473; wire [31:0] _zz_474; wire [31:0] _zz_475; wire [31:0] _zz_476; wire [31:0] _zz_477; wire [31:0] _zz_478; - wire [31:0] _zz_479; - wire _zz_480; - wire [0:0] _zz_481; - wire [1:0] _zz_482; + wire _zz_479; + wire [0:0] _zz_480; + wire [1:0] _zz_481; + wire [31:0] _zz_482; wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire [0:0] _zz_485; + wire [0:0] _zz_484; + wire [4:0] _zz_485; wire [4:0] _zz_486; wire [4:0] _zz_487; - wire [4:0] _zz_488; - wire _zz_489; - wire [0:0] _zz_490; - wire [8:0] _zz_491; + wire _zz_488; + wire [0:0] _zz_489; + wire [8:0] _zz_490; + wire [31:0] _zz_491; wire [31:0] _zz_492; wire [31:0] _zz_493; - wire [31:0] _zz_494; + wire _zz_494; wire _zz_495; - wire _zz_496; + wire [31:0] _zz_496; wire [31:0] _zz_497; - wire [31:0] _zz_498; - wire _zz_499; - wire [0:0] _zz_500; - wire [2:0] _zz_501; - wire [0:0] _zz_502; - wire [2:0] _zz_503; - wire [0:0] _zz_504; - wire [4:0] _zz_505; + wire _zz_498; + wire [0:0] _zz_499; + wire [2:0] _zz_500; + wire [0:0] _zz_501; + wire [2:0] _zz_502; + wire [0:0] _zz_503; + wire [4:0] _zz_504; + wire [1:0] _zz_505; wire [1:0] _zz_506; - wire [1:0] _zz_507; - wire _zz_508; - wire [0:0] _zz_509; - wire [6:0] _zz_510; + wire _zz_507; + wire [0:0] _zz_508; + wire [6:0] _zz_509; + wire [31:0] _zz_510; wire [31:0] _zz_511; wire [31:0] _zz_512; - wire [31:0] _zz_513; - wire _zz_514; + wire _zz_513; + wire [0:0] _zz_514; wire [0:0] _zz_515; - wire [0:0] _zz_516; + wire [31:0] _zz_516; wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire _zz_519; + wire _zz_518; + wire [0:0] _zz_519; wire [0:0] _zz_520; - wire [0:0] _zz_521; - wire _zz_522; - wire [0:0] _zz_523; - wire [2:0] _zz_524; - wire _zz_525; + wire _zz_521; + wire [0:0] _zz_522; + wire [2:0] _zz_523; + wire _zz_524; + wire [0:0] _zz_525; wire [0:0] _zz_526; wire [0:0] _zz_527; wire [0:0] _zz_528; - wire [0:0] _zz_529; - wire _zz_530; - wire [0:0] _zz_531; - wire [4:0] _zz_532; + wire _zz_529; + wire [0:0] _zz_530; + wire [4:0] _zz_531; + wire [31:0] _zz_532; wire [31:0] _zz_533; wire [31:0] _zz_534; wire [31:0] _zz_535; @@ -455,53 +459,52 @@ module VexRiscv_inner ( wire [31:0] _zz_542; wire [31:0] _zz_543; wire [31:0] _zz_544; - wire [31:0] _zz_545; - wire _zz_546; + wire _zz_545; + wire [0:0] _zz_546; wire [0:0] _zz_547; - wire [0:0] _zz_548; + wire [31:0] _zz_548; wire [31:0] _zz_549; wire [31:0] _zz_550; wire [31:0] _zz_551; wire [31:0] _zz_552; - wire [31:0] _zz_553; - wire _zz_554; + wire _zz_553; + wire [3:0] _zz_554; wire [3:0] _zz_555; - wire [3:0] _zz_556; - wire _zz_557; - wire [0:0] _zz_558; - wire [2:0] _zz_559; + wire _zz_556; + wire [0:0] _zz_557; + wire [2:0] _zz_558; + wire [31:0] _zz_559; wire [31:0] _zz_560; wire [31:0] _zz_561; wire [31:0] _zz_562; wire [31:0] _zz_563; wire [31:0] _zz_564; - wire [31:0] _zz_565; - wire _zz_566; - wire [0:0] _zz_567; - wire [1:0] _zz_568; - wire _zz_569; + wire _zz_565; + wire [0:0] _zz_566; + wire [1:0] _zz_567; + wire _zz_568; + wire [2:0] _zz_569; wire [2:0] _zz_570; - wire [2:0] _zz_571; - wire _zz_572; + wire _zz_571; + wire [0:0] _zz_572; wire [0:0] _zz_573; - wire [0:0] _zz_574; + wire [31:0] _zz_574; wire [31:0] _zz_575; wire [31:0] _zz_576; wire [31:0] _zz_577; wire [31:0] _zz_578; wire [31:0] _zz_579; wire [31:0] _zz_580; - wire [31:0] _zz_581; + wire _zz_581; wire _zz_582; wire _zz_583; - wire _zz_584; + wire [0:0] _zz_584; wire [0:0] _zz_585; - wire [0:0] _zz_586; + wire _zz_586; wire _zz_587; wire _zz_588; wire _zz_589; - wire _zz_590; - wire [31:0] _zz_591; + wire [31:0] _zz_590; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -754,6 +757,7 @@ module VexRiscv_inner ( wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; wire IBusCachedPlugin_mmuBus_rsp_allowRead; wire IBusCachedPlugin_mmuBus_rsp_allowWrite; wire IBusCachedPlugin_mmuBus_rsp_allowExecute; @@ -781,6 +785,7 @@ module VexRiscv_inner ( wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; wire DBusCachedPlugin_mmuBus_rsp_allowRead; wire DBusCachedPlugin_mmuBus_rsp_allowWrite; wire DBusCachedPlugin_mmuBus_rsp_allowExecute; @@ -981,8 +986,8 @@ module VexRiscv_inner ( wire [31:0] decode_RegFilePlugin_rs1Data; wire [31:0] decode_RegFilePlugin_rs2Data; reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; reg _zz_106; reg [31:0] execute_IntAluPlugin_bitwise; reg [31:0] _zz_107; @@ -998,37 +1003,42 @@ module VexRiscv_inner ( reg [31:0] _zz_114; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_115; - reg _zz_116; - reg _zz_117; - reg _zz_118; - reg [4:0] _zz_119; - reg [31:0] _zz_120; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_116; + wire _zz_117; + wire _zz_118; + wire _zz_119; + wire _zz_120; wire _zz_121; - wire _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; - wire _zz_126; wire execute_BranchPlugin_eq; - wire [2:0] _zz_127; - reg _zz_128; - reg _zz_129; - wire _zz_130; - reg [19:0] _zz_131; - wire _zz_132; - reg [10:0] _zz_133; - wire _zz_134; - reg [18:0] _zz_135; - reg _zz_136; + wire [2:0] _zz_122; + reg _zz_123; + reg _zz_124; + wire _zz_125; + reg [19:0] _zz_126; + wire _zz_127; + reg [10:0] _zz_128; + wire _zz_129; + reg [18:0] _zz_130; + reg _zz_131; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_137; - reg [19:0] _zz_138; - wire _zz_139; - reg [10:0] _zz_140; - wire _zz_141; - reg [18:0] _zz_142; + wire _zz_132; + reg [19:0] _zz_133; + wire _zz_134; + reg [10:0] _zz_135; + wire _zz_136; + reg [18:0] _zz_137; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1050,9 +1060,9 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_143; - wire _zz_144; - wire _zz_145; + wire _zz_138; + wire _zz_139; + wire _zz_140; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1065,10 +1075,10 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_146; - wire _zz_147; - wire [1:0] _zz_148; - wire _zz_149; + wire [1:0] _zz_141; + wire _zz_142; + wire [1:0] _zz_143; + wire _zz_144; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1090,13 +1100,18 @@ module VexRiscv_inner ( reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; wire [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_145; + reg [31:0] _zz_146; + reg [31:0] _zz_147; + reg [31:0] _zz_148; + reg [31:0] _zz_149; reg [31:0] _zz_150; reg [31:0] _zz_151; reg [31:0] _zz_152; @@ -1108,25 +1123,20 @@ module VexRiscv_inner ( reg [31:0] _zz_158; reg [31:0] _zz_159; reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; - wire [2:0] execute_CfuPlugin_functionsIds_0; - wire _zz_166; - reg [19:0] _zz_167; - reg [31:0] _zz_168; + wire [19:0] execute_CfuPlugin_functionsIds_0; + wire _zz_161; + reg [19:0] _zz_162; + reg [31:0] _zz_163; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_m2sPipe_rValid; - reg CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0; + reg CfuPlugin_bus_rsp_s2mPipe_rValid; + reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; @@ -1151,18 +1161,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_169; + wire [31:0] _zz_164; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_170; - wire _zz_171; - wire _zz_172; - reg [32:0] _zz_173; + wire [31:0] _zz_165; + wire _zz_166; + wire _zz_167; + reg [32:0] _zz_168; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_174; - wire [31:0] _zz_175; + reg [31:0] _zz_169; + wire [31:0] _zz_170; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1172,7 +1182,8 @@ module VexRiscv_inner ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_176; + reg _zz_171; + wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; @@ -1240,7 +1251,7 @@ module VexRiscv_inner ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_177; + reg [2:0] _zz_172; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; @@ -1261,6 +1272,8 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2946; reg execute_CsrPlugin_csr_3072; reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; reg execute_CsrPlugin_csr_2820; reg execute_CsrPlugin_csr_2821; reg execute_CsrPlugin_csr_2822; @@ -1279,6 +1292,11 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; reg [31:0] _zz_178; reg [31:0] _zz_179; reg [31:0] _zz_180; @@ -1305,19 +1323,16 @@ module VexRiscv_inner ( reg [31:0] _zz_201; reg [31:0] _zz_202; reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [2:0] _zz_207; - reg _zz_208; + reg [2:0] _zz_204; + reg _zz_205; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_209; + reg [2:0] _zz_206; + wire _zz_207; + wire _zz_208; + wire _zz_209; wire _zz_210; wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - reg _zz_215; + reg _zz_212; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; @@ -1411,360 +1426,362 @@ module VexRiscv_inner ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_247 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_248 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_249 = 1'b1; - assign _zz_250 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_251 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_252 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_253 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_254 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_255 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_256 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_257 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_258 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_259 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_260 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_261 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_262 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_263 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_264 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_265 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_266 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_267 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_268 = (1'b0 || (! 1'b1)); - assign _zz_269 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_270 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_271 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_272 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_273 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_274 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_275 = execute_INSTRUCTION[13 : 12]; - assign _zz_276 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_277 = (! memory_arbitration_isStuck); - assign _zz_278 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_279 = (iBus_cmd_valid || (_zz_207 != 3'b000)); - assign _zz_280 = (_zz_243 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_281 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_282 = ((_zz_143 && 1'b1) && (! 1'b0)); - assign _zz_283 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_284 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_285 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_286 = execute_INSTRUCTION[13]; - assign _zz_287 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_288 = ($signed(_zz_289) + $signed(_zz_294)); - assign _zz_289 = ($signed(_zz_290) + $signed(_zz_292)); - assign _zz_290 = 52'h0; - assign _zz_291 = {1'b0,memory_MUL_LL}; - assign _zz_292 = {{19{_zz_291[32]}}, _zz_291}; - assign _zz_293 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_294 = {{2{_zz_293[49]}}, _zz_293}; - assign _zz_295 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_296 = {{2{_zz_295[49]}}, _zz_295}; - assign _zz_297 = ($signed(_zz_299) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_298 = _zz_297[31 : 0]; - assign _zz_299 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_300 = _zz_92[33 : 33]; - assign _zz_301 = _zz_92[32 : 32]; - assign _zz_302 = _zz_92[31 : 31]; - assign _zz_303 = _zz_92[30 : 30]; - assign _zz_304 = _zz_92[28 : 28]; - assign _zz_305 = _zz_92[25 : 25]; - assign _zz_306 = _zz_92[17 : 17]; - assign _zz_307 = _zz_92[16 : 16]; - assign _zz_308 = _zz_92[13 : 13]; - assign _zz_309 = _zz_92[12 : 12]; - assign _zz_310 = _zz_92[11 : 11]; - assign _zz_311 = _zz_92[34 : 34]; - assign _zz_312 = _zz_92[15 : 15]; - assign _zz_313 = _zz_92[5 : 5]; - assign _zz_314 = _zz_92[3 : 3]; - assign _zz_315 = _zz_92[20 : 20]; - assign _zz_316 = _zz_92[10 : 10]; - assign _zz_317 = _zz_92[4 : 4]; - assign _zz_318 = _zz_92[0 : 0]; - assign _zz_319 = (_zz_60 - 4'b0001); - assign _zz_320 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_321 = {29'd0, _zz_320}; - assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_323 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_324 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_325 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_326 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_327 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_329 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_330 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_331 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_332 = execute_SRC_LESS; - assign _zz_333 = 3'b100; - assign _zz_334 = execute_INSTRUCTION[19 : 15]; - assign _zz_335 = execute_INSTRUCTION[31 : 20]; - assign _zz_336 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_337 = ($signed(_zz_338) + $signed(_zz_341)); - assign _zz_338 = ($signed(_zz_339) + $signed(_zz_340)); - assign _zz_339 = execute_SRC1; - assign _zz_340 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_341 = (execute_SRC_USE_SUB_LESS ? _zz_342 : _zz_343); - assign _zz_342 = 32'h00000001; - assign _zz_343 = 32'h0; - assign _zz_344 = execute_INSTRUCTION[31 : 20]; - assign _zz_345 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_346 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_347 = {_zz_131,execute_INSTRUCTION[31 : 20]}; - assign _zz_348 = {{_zz_133,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_349 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_350 = execute_INSTRUCTION[31 : 20]; - assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_353 = 3'b100; - assign _zz_354 = (_zz_146 & (~ _zz_355)); - assign _zz_355 = (_zz_146 - 2'b01); - assign _zz_356 = (_zz_148 & (~ _zz_357)); - assign _zz_357 = (_zz_148 - 2'b01); - assign _zz_358 = execute_INSTRUCTION[14 : 12]; - assign _zz_359 = execute_INSTRUCTION[31 : 20]; - assign _zz_360 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_361 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_362 = writeBack_MUL_LOW[31 : 0]; - assign _zz_363 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_364 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_365 = {5'd0, _zz_364}; - assign _zz_366 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_367 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_368 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_369 = {_zz_169,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_244 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_245 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_246 = 1'b1; + assign _zz_247 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_248 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_249 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_250 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_251 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_252 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_253 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_254 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_255 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_256 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_257 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_258 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_259 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_260 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_261 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_262 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_263 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_264 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_265 = (1'b0 || (! 1'b1)); + assign _zz_266 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_267 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_268 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_269 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_270 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_271 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_272 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_273 = execute_INSTRUCTION[13 : 12]; + assign _zz_274 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_275 = (! memory_arbitration_isStuck); + assign _zz_276 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_277 = (iBus_cmd_valid || (_zz_204 != 3'b000)); + assign _zz_278 = (_zz_240 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_280 = ((_zz_138 && 1'b1) && (! 1'b0)); + assign _zz_281 = ((_zz_139 && 1'b1) && (! 1'b0)); + assign _zz_282 = ((_zz_140 && 1'b1) && (! 1'b0)); + assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_285 = execute_INSTRUCTION[13]; + assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); + assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); + assign _zz_289 = 52'h0; + assign _zz_290 = {1'b0,memory_MUL_LL}; + assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; + assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; + assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; + assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_297 = _zz_296[31 : 0]; + assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_299 = _zz_92[33 : 33]; + assign _zz_300 = _zz_92[32 : 32]; + assign _zz_301 = _zz_92[31 : 31]; + assign _zz_302 = _zz_92[30 : 30]; + assign _zz_303 = _zz_92[28 : 28]; + assign _zz_304 = _zz_92[25 : 25]; + assign _zz_305 = _zz_92[17 : 17]; + assign _zz_306 = _zz_92[16 : 16]; + assign _zz_307 = _zz_92[13 : 13]; + assign _zz_308 = _zz_92[12 : 12]; + assign _zz_309 = _zz_92[11 : 11]; + assign _zz_310 = _zz_92[34 : 34]; + assign _zz_311 = _zz_92[15 : 15]; + assign _zz_312 = _zz_92[5 : 5]; + assign _zz_313 = _zz_92[3 : 3]; + assign _zz_314 = _zz_92[20 : 20]; + assign _zz_315 = _zz_92[10 : 10]; + assign _zz_316 = _zz_92[4 : 4]; + assign _zz_317 = _zz_92[0 : 0]; + assign _zz_318 = (_zz_60 - 4'b0001); + assign _zz_319 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_320 = {29'd0, _zz_319}; + assign _zz_321 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_322 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_324 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_325 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_326 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_329 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_330 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_331 = execute_SRC_LESS; + assign _zz_332 = 3'b100; + assign _zz_333 = execute_INSTRUCTION[19 : 15]; + assign _zz_334 = execute_INSTRUCTION[31 : 20]; + assign _zz_335 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_336 = ($signed(_zz_337) + $signed(_zz_340)); + assign _zz_337 = ($signed(_zz_338) + $signed(_zz_339)); + assign _zz_338 = execute_SRC1; + assign _zz_339 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_340 = (execute_SRC_USE_SUB_LESS ? _zz_341 : _zz_342); + assign _zz_341 = 32'h00000001; + assign _zz_342 = 32'h0; + assign _zz_343 = execute_INSTRUCTION[31 : 20]; + assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_345 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_346 = {_zz_126,execute_INSTRUCTION[31 : 20]}; + assign _zz_347 = {{_zz_128,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_348 = {{_zz_130,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_349 = execute_INSTRUCTION[31 : 20]; + assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_352 = 3'b100; + assign _zz_353 = (_zz_141 & (~ _zz_354)); + assign _zz_354 = (_zz_141 - 2'b01); + assign _zz_355 = (_zz_143 & (~ _zz_356)); + assign _zz_356 = (_zz_143 - 2'b01); + assign _zz_357 = execute_INSTRUCTION[31 : 12]; + assign _zz_358 = execute_INSTRUCTION[31 : 20]; + assign _zz_359 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_360 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_361 = writeBack_MUL_LOW[31 : 0]; + assign _zz_362 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_363 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_364 = {5'd0, _zz_363}; + assign _zz_365 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_366 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_367 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_368 = {_zz_164,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_369 = _zz_370; assign _zz_370 = _zz_371; - assign _zz_371 = _zz_372; - assign _zz_372 = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_170) : _zz_170)} + _zz_374); - assign _zz_373 = memory_DivPlugin_div_needRevert; - assign _zz_374 = {32'd0, _zz_373}; - assign _zz_375 = _zz_172; - assign _zz_376 = {32'd0, _zz_375}; - assign _zz_377 = _zz_171; - assign _zz_378 = {31'd0, _zz_377}; - assign _zz_379 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_371 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_165) : _zz_165)} + _zz_373); + assign _zz_372 = memory_DivPlugin_div_needRevert; + assign _zz_373 = {32'd0, _zz_372}; + assign _zz_374 = _zz_167; + assign _zz_375 = {32'd0, _zz_374}; + assign _zz_376 = _zz_166; + assign _zz_377 = {31'd0, _zz_376}; + assign _zz_378 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; assign _zz_380 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_381 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_382 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_383 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_384 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_385 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_386 = (iBus_cmd_payload_address >>> 5); + assign _zz_381 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_382 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_383 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_384 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_385 = (iBus_cmd_payload_address >>> 5); + assign _zz_386 = 1'b1; assign _zz_387 = 1'b1; - assign _zz_388 = 1'b1; - assign _zz_389 = {_zz_64,_zz_63}; - assign _zz_390 = 32'h0000106f; - assign _zz_391 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_392 = 32'h00001073; - assign _zz_393 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_394 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_395 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}; - assign _zz_396 = 32'h0000207f; - assign _zz_397 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_398 = 32'h00000003; - assign _zz_399 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_400 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_401 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_402) == 32'h00005013),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; - assign _zz_402 = 32'hbc00707f; - assign _zz_403 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_404 = 32'h00001013; - assign _zz_405 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_406 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_407 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_388 = {_zz_64,_zz_63}; + assign _zz_389 = 32'h0000106f; + assign _zz_390 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_391 = 32'h00001073; + assign _zz_392 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_393 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_394 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_395) == 32'h00000003),{(_zz_396 == _zz_397),{_zz_398,{_zz_399,_zz_400}}}}}}; + assign _zz_395 = 32'h0000207f; + assign _zz_396 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_397 = 32'h00000003; + assign _zz_398 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_399 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_400 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_401) == 32'h00005013),{(_zz_402 == _zz_403),{_zz_404,{_zz_405,_zz_406}}}}}}; + assign _zz_401 = 32'hbc00707f; + assign _zz_402 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_403 = 32'h00001013; + assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_405 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_406 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_407 = decode_INSTRUCTION[31]; assign _zz_408 = decode_INSTRUCTION[31]; - assign _zz_409 = decode_INSTRUCTION[31]; - assign _zz_410 = decode_INSTRUCTION[7]; - assign _zz_411 = 32'h10103050; - assign _zz_412 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_413 = 1'b0; - assign _zz_414 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_415 = 1'b0; - assign _zz_416 = {(_zz_96 != 1'b0),{({_zz_417,_zz_418} != 2'b00),{(_zz_419 != _zz_420),{_zz_421,{_zz_422,_zz_423}}}}}; - assign _zz_417 = ((decode_INSTRUCTION & _zz_424) == 32'h10000050); + assign _zz_409 = decode_INSTRUCTION[7]; + assign _zz_410 = 32'h10103050; + assign _zz_411 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_412 = 1'b0; + assign _zz_413 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_414 = 1'b0; + assign _zz_415 = {(_zz_96 != 1'b0),{({_zz_416,_zz_417} != 2'b00),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}; + assign _zz_416 = ((decode_INSTRUCTION & _zz_423) == 32'h10000050); + assign _zz_417 = ((decode_INSTRUCTION & _zz_424) == 32'h00000050); assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00000050); - assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00000050); - assign _zz_420 = 1'b0; - assign _zz_421 = ({_zz_427,_zz_428} != 2'b00); - assign _zz_422 = ({_zz_429,_zz_430} != 2'b00); - assign _zz_423 = {(_zz_431 != _zz_432),{_zz_433,{_zz_434,_zz_435}}}; - assign _zz_424 = 32'h10203050; - assign _zz_425 = 32'h10103050; - assign _zz_426 = 32'h00103050; - assign _zz_427 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_428 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_429 = _zz_95; - assign _zz_430 = ((decode_INSTRUCTION & _zz_436) == 32'h00000004); - assign _zz_431 = ((decode_INSTRUCTION & _zz_437) == 32'h00000040); - assign _zz_432 = 1'b0; - assign _zz_433 = ({_zz_438,_zz_439} != 2'b00); - assign _zz_434 = ({_zz_440,_zz_441} != 3'b000); - assign _zz_435 = {(_zz_442 != _zz_443),{_zz_444,{_zz_445,_zz_446}}}; - assign _zz_436 = 32'h0000001c; - assign _zz_437 = 32'h00000058; - assign _zz_438 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_439 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_440 = ((decode_INSTRUCTION & _zz_447) == 32'h40001010); - assign _zz_441 = {(_zz_448 == _zz_449),(_zz_450 == _zz_451)}; - assign _zz_442 = ((decode_INSTRUCTION & _zz_452) == 32'h00000024); - assign _zz_443 = 1'b0; - assign _zz_444 = ((_zz_453 == _zz_454) != 1'b0); - assign _zz_445 = (_zz_455 != 1'b0); - assign _zz_446 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; - assign _zz_447 = 32'h40003054; - assign _zz_448 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_449 = 32'h00001010; - assign _zz_450 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_451 = 32'h00001010; - assign _zz_452 = 32'h00000064; - assign _zz_453 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_454 = 32'h00001000; - assign _zz_455 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_456 = {(_zz_461 == _zz_462),(_zz_463 == _zz_464)}; - assign _zz_457 = 2'b00; - assign _zz_458 = ((_zz_465 == _zz_466) != 1'b0); - assign _zz_459 = ({_zz_467,_zz_468} != 3'b000); - assign _zz_460 = {(_zz_469 != _zz_470),{_zz_471,{_zz_472,_zz_473}}}; - assign _zz_461 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_462 = 32'h00002000; - assign _zz_463 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_464 = 32'h00001000; - assign _zz_465 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_466 = 32'h00004004; - assign _zz_467 = _zz_96; - assign _zz_468 = {(_zz_474 == _zz_475),(_zz_476 == _zz_477)}; - assign _zz_469 = {(_zz_478 == _zz_479),{_zz_480,{_zz_481,_zz_482}}}; - assign _zz_470 = 5'h0; - assign _zz_471 = ((_zz_483 == _zz_484) != 1'b0); - assign _zz_472 = ({_zz_485,_zz_486} != 6'h0); - assign _zz_473 = {(_zz_487 != _zz_488),{_zz_489,{_zz_490,_zz_491}}}; - assign _zz_474 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_475 = 32'h00000020; - assign _zz_476 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_477 = 32'h00000020; - assign _zz_478 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_479 = 32'h00002040; - assign _zz_480 = ((decode_INSTRUCTION & _zz_492) == 32'h00001040); - assign _zz_481 = (_zz_493 == _zz_494); - assign _zz_482 = {_zz_495,_zz_496}; - assign _zz_483 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_484 = 32'h00000020; - assign _zz_485 = (_zz_497 == _zz_498); - assign _zz_486 = {_zz_499,{_zz_500,_zz_501}}; - assign _zz_487 = {_zz_94,{_zz_502,_zz_503}}; - assign _zz_488 = 5'h0; - assign _zz_489 = ({_zz_504,_zz_505} != 6'h0); - assign _zz_490 = (_zz_506 != _zz_507); - assign _zz_491 = {_zz_508,{_zz_509,_zz_510}}; - assign _zz_492 = 32'h00001040; - assign _zz_493 = (decode_INSTRUCTION & 32'h00100040); - assign _zz_494 = 32'h00000040; - assign _zz_495 = ((decode_INSTRUCTION & _zz_511) == 32'h00000040); - assign _zz_496 = ((decode_INSTRUCTION & _zz_512) == 32'h0); - assign _zz_497 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_498 = 32'h00000008; - assign _zz_499 = ((decode_INSTRUCTION & _zz_513) == 32'h00000040); - assign _zz_500 = _zz_94; - assign _zz_501 = {_zz_514,{_zz_515,_zz_516}}; - assign _zz_502 = (_zz_517 == _zz_518); - assign _zz_503 = {_zz_519,{_zz_520,_zz_521}}; - assign _zz_504 = _zz_95; - assign _zz_505 = {_zz_522,{_zz_523,_zz_524}}; - assign _zz_506 = {_zz_94,_zz_525}; - assign _zz_507 = 2'b00; - assign _zz_508 = ({_zz_526,_zz_527} != 2'b00); - assign _zz_509 = (_zz_528 != _zz_529); - assign _zz_510 = {_zz_530,{_zz_531,_zz_532}}; - assign _zz_511 = 32'h00000050; - assign _zz_512 = 32'h00000038; - assign _zz_513 = 32'h00000040; - assign _zz_514 = ((decode_INSTRUCTION & _zz_533) == 32'h00004020); - assign _zz_515 = (_zz_534 == _zz_535); - assign _zz_516 = (_zz_536 == _zz_537); - assign _zz_517 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_518 = 32'h00002010; - assign _zz_519 = ((decode_INSTRUCTION & _zz_538) == 32'h00000010); - assign _zz_520 = (_zz_539 == _zz_540); - assign _zz_521 = (_zz_541 == _zz_542); - assign _zz_522 = ((decode_INSTRUCTION & _zz_543) == 32'h00001010); - assign _zz_523 = (_zz_544 == _zz_545); - assign _zz_524 = {_zz_546,{_zz_547,_zz_548}}; - assign _zz_525 = ((decode_INSTRUCTION & _zz_549) == 32'h00000020); - assign _zz_526 = _zz_94; - assign _zz_527 = (_zz_550 == _zz_551); - assign _zz_528 = (_zz_552 == _zz_553); - assign _zz_529 = 1'b0; - assign _zz_530 = (_zz_554 != 1'b0); - assign _zz_531 = (_zz_555 != _zz_556); - assign _zz_532 = {_zz_557,{_zz_558,_zz_559}}; - assign _zz_533 = 32'h00004020; - assign _zz_534 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_535 = 32'h00000010; - assign _zz_536 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_537 = 32'h00000020; - assign _zz_538 = 32'h00001030; - assign _zz_539 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_540 = 32'h00002020; - assign _zz_541 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_542 = 32'h00000020; - assign _zz_543 = 32'h00001010; - assign _zz_544 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_545 = 32'h00002010; - assign _zz_546 = ((decode_INSTRUCTION & _zz_560) == 32'h00000010); - assign _zz_547 = (_zz_561 == _zz_562); - assign _zz_548 = (_zz_563 == _zz_564); - assign _zz_549 = 32'h00000070; - assign _zz_550 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_551 = 32'h0; - assign _zz_552 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_553 = 32'h00004010; - assign _zz_554 = ((decode_INSTRUCTION & _zz_565) == 32'h00002010); - assign _zz_555 = {_zz_566,{_zz_567,_zz_568}}; - assign _zz_556 = 4'b0000; - assign _zz_557 = (_zz_569 != 1'b0); - assign _zz_558 = (_zz_570 != _zz_571); - assign _zz_559 = {_zz_572,{_zz_573,_zz_574}}; - assign _zz_560 = 32'h00000050; - assign _zz_561 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_562 = 32'h00000004; - assign _zz_563 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_564 = 32'h0; - assign _zz_565 = 32'h00006014; - assign _zz_566 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_567 = ((decode_INSTRUCTION & _zz_575) == 32'h0); - assign _zz_568 = {(_zz_576 == _zz_577),(_zz_578 == _zz_579)}; - assign _zz_569 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_570 = {(_zz_580 == _zz_581),{_zz_582,_zz_583}}; - assign _zz_571 = 3'b000; - assign _zz_572 = ({_zz_584,_zz_93} != 2'b00); - assign _zz_573 = ({_zz_585,_zz_586} != 2'b00); - assign _zz_574 = (_zz_587 != 1'b0); - assign _zz_575 = 32'h00000018; - assign _zz_576 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_577 = 32'h00002000; - assign _zz_578 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_579 = 32'h00001000; - assign _zz_580 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_581 = 32'h00000040; - assign _zz_582 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_583 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_584 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_585 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_586 = _zz_93; - assign _zz_587 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_419 = 1'b0; + assign _zz_420 = ({_zz_426,_zz_427} != 2'b00); + assign _zz_421 = ({_zz_428,_zz_429} != 2'b00); + assign _zz_422 = {(_zz_430 != _zz_431),{_zz_432,{_zz_433,_zz_434}}}; + assign _zz_423 = 32'h10203050; + assign _zz_424 = 32'h10103050; + assign _zz_425 = 32'h00103050; + assign _zz_426 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_427 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_428 = _zz_95; + assign _zz_429 = ((decode_INSTRUCTION & _zz_435) == 32'h00000004); + assign _zz_430 = ((decode_INSTRUCTION & _zz_436) == 32'h00000040); + assign _zz_431 = 1'b0; + assign _zz_432 = ({_zz_437,_zz_438} != 2'b00); + assign _zz_433 = ({_zz_439,_zz_440} != 3'b000); + assign _zz_434 = {(_zz_441 != _zz_442),{_zz_443,{_zz_444,_zz_445}}}; + assign _zz_435 = 32'h0000001c; + assign _zz_436 = 32'h00000058; + assign _zz_437 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_438 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_439 = ((decode_INSTRUCTION & _zz_446) == 32'h40001010); + assign _zz_440 = {(_zz_447 == _zz_448),(_zz_449 == _zz_450)}; + assign _zz_441 = ((decode_INSTRUCTION & _zz_451) == 32'h00000024); + assign _zz_442 = 1'b0; + assign _zz_443 = ((_zz_452 == _zz_453) != 1'b0); + assign _zz_444 = (_zz_454 != 1'b0); + assign _zz_445 = {(_zz_455 != _zz_456),{_zz_457,{_zz_458,_zz_459}}}; + assign _zz_446 = 32'h40003054; + assign _zz_447 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_448 = 32'h00001010; + assign _zz_449 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_450 = 32'h00001010; + assign _zz_451 = 32'h00000064; + assign _zz_452 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_453 = 32'h00001000; + assign _zz_454 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_455 = {(_zz_460 == _zz_461),(_zz_462 == _zz_463)}; + assign _zz_456 = 2'b00; + assign _zz_457 = ((_zz_464 == _zz_465) != 1'b0); + assign _zz_458 = ({_zz_466,_zz_467} != 3'b000); + assign _zz_459 = {(_zz_468 != _zz_469),{_zz_470,{_zz_471,_zz_472}}}; + assign _zz_460 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_461 = 32'h00002000; + assign _zz_462 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_463 = 32'h00001000; + assign _zz_464 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_465 = 32'h00004004; + assign _zz_466 = _zz_96; + assign _zz_467 = {(_zz_473 == _zz_474),(_zz_475 == _zz_476)}; + assign _zz_468 = {(_zz_477 == _zz_478),{_zz_479,{_zz_480,_zz_481}}}; + assign _zz_469 = 5'h0; + assign _zz_470 = ((_zz_482 == _zz_483) != 1'b0); + assign _zz_471 = ({_zz_484,_zz_485} != 6'h0); + assign _zz_472 = {(_zz_486 != _zz_487),{_zz_488,{_zz_489,_zz_490}}}; + assign _zz_473 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_474 = 32'h00000020; + assign _zz_475 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_476 = 32'h00000020; + assign _zz_477 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_478 = 32'h00002040; + assign _zz_479 = ((decode_INSTRUCTION & _zz_491) == 32'h00001040); + assign _zz_480 = (_zz_492 == _zz_493); + assign _zz_481 = {_zz_494,_zz_495}; + assign _zz_482 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_483 = 32'h00000020; + assign _zz_484 = (_zz_496 == _zz_497); + assign _zz_485 = {_zz_498,{_zz_499,_zz_500}}; + assign _zz_486 = {_zz_94,{_zz_501,_zz_502}}; + assign _zz_487 = 5'h0; + assign _zz_488 = ({_zz_503,_zz_504} != 6'h0); + assign _zz_489 = (_zz_505 != _zz_506); + assign _zz_490 = {_zz_507,{_zz_508,_zz_509}}; + assign _zz_491 = 32'h00001040; + assign _zz_492 = (decode_INSTRUCTION & 32'h00100040); + assign _zz_493 = 32'h00000040; + assign _zz_494 = ((decode_INSTRUCTION & _zz_510) == 32'h00000040); + assign _zz_495 = ((decode_INSTRUCTION & _zz_511) == 32'h0); + assign _zz_496 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_497 = 32'h00000008; + assign _zz_498 = ((decode_INSTRUCTION & _zz_512) == 32'h00000040); + assign _zz_499 = _zz_94; + assign _zz_500 = {_zz_513,{_zz_514,_zz_515}}; + assign _zz_501 = (_zz_516 == _zz_517); + assign _zz_502 = {_zz_518,{_zz_519,_zz_520}}; + assign _zz_503 = _zz_95; + assign _zz_504 = {_zz_521,{_zz_522,_zz_523}}; + assign _zz_505 = {_zz_94,_zz_524}; + assign _zz_506 = 2'b00; + assign _zz_507 = ({_zz_525,_zz_526} != 2'b00); + assign _zz_508 = (_zz_527 != _zz_528); + assign _zz_509 = {_zz_529,{_zz_530,_zz_531}}; + assign _zz_510 = 32'h00000050; + assign _zz_511 = 32'h00000038; + assign _zz_512 = 32'h00000040; + assign _zz_513 = ((decode_INSTRUCTION & _zz_532) == 32'h00004020); + assign _zz_514 = (_zz_533 == _zz_534); + assign _zz_515 = (_zz_535 == _zz_536); + assign _zz_516 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_517 = 32'h00002010; + assign _zz_518 = ((decode_INSTRUCTION & _zz_537) == 32'h00000010); + assign _zz_519 = (_zz_538 == _zz_539); + assign _zz_520 = (_zz_540 == _zz_541); + assign _zz_521 = ((decode_INSTRUCTION & _zz_542) == 32'h00001010); + assign _zz_522 = (_zz_543 == _zz_544); + assign _zz_523 = {_zz_545,{_zz_546,_zz_547}}; + assign _zz_524 = ((decode_INSTRUCTION & _zz_548) == 32'h00000020); + assign _zz_525 = _zz_94; + assign _zz_526 = (_zz_549 == _zz_550); + assign _zz_527 = (_zz_551 == _zz_552); + assign _zz_528 = 1'b0; + assign _zz_529 = (_zz_553 != 1'b0); + assign _zz_530 = (_zz_554 != _zz_555); + assign _zz_531 = {_zz_556,{_zz_557,_zz_558}}; + assign _zz_532 = 32'h00004020; + assign _zz_533 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_534 = 32'h00000010; + assign _zz_535 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_536 = 32'h00000020; + assign _zz_537 = 32'h00001030; + assign _zz_538 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_539 = 32'h00002020; + assign _zz_540 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_541 = 32'h00000020; + assign _zz_542 = 32'h00001010; + assign _zz_543 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_544 = 32'h00002010; + assign _zz_545 = ((decode_INSTRUCTION & _zz_559) == 32'h00000010); + assign _zz_546 = (_zz_560 == _zz_561); + assign _zz_547 = (_zz_562 == _zz_563); + assign _zz_548 = 32'h00000070; + assign _zz_549 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_550 = 32'h0; + assign _zz_551 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_552 = 32'h00004010; + assign _zz_553 = ((decode_INSTRUCTION & _zz_564) == 32'h00002010); + assign _zz_554 = {_zz_565,{_zz_566,_zz_567}}; + assign _zz_555 = 4'b0000; + assign _zz_556 = (_zz_568 != 1'b0); + assign _zz_557 = (_zz_569 != _zz_570); + assign _zz_558 = {_zz_571,{_zz_572,_zz_573}}; + assign _zz_559 = 32'h00000050; + assign _zz_560 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_561 = 32'h00000004; + assign _zz_562 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_563 = 32'h0; + assign _zz_564 = 32'h00006014; + assign _zz_565 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_566 = ((decode_INSTRUCTION & _zz_574) == 32'h0); + assign _zz_567 = {(_zz_575 == _zz_576),(_zz_577 == _zz_578)}; + assign _zz_568 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_569 = {(_zz_579 == _zz_580),{_zz_581,_zz_582}}; + assign _zz_570 = 3'b000; + assign _zz_571 = ({_zz_583,_zz_93} != 2'b00); + assign _zz_572 = ({_zz_584,_zz_585} != 2'b00); + assign _zz_573 = (_zz_586 != 1'b0); + assign _zz_574 = 32'h00000018; + assign _zz_575 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_576 = 32'h00002000; + assign _zz_577 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_578 = 32'h00001000; + assign _zz_579 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_580 = 32'h00000040; + assign _zz_581 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_582 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_583 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_584 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_585 = _zz_93; + assign _zz_586 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_587 = execute_INSTRUCTION[31]; assign _zz_588 = execute_INSTRUCTION[31]; - assign _zz_589 = execute_INSTRUCTION[31]; - assign _zz_590 = execute_INSTRUCTION[7]; - assign _zz_591 = 32'h0; + assign _zz_589 = execute_INSTRUCTION[7]; + assign _zz_590 = 32'h0; always @ (posedge clk) begin - if(_zz_387) begin - _zz_244 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_386) begin + _zz_241 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_388) begin - _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_387) begin + _zz_242 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1775,17 +1792,18 @@ module VexRiscv_inner ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_216 ), //i - .io_cpu_prefetch_isValid (_zz_217 ), //i + .io_flush (_zz_213 ), //i + .io_cpu_prefetch_isValid (_zz_214 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_218 ), //i - .io_cpu_fetch_isStuck (_zz_219 ), //i - .io_cpu_fetch_isRemoved (_zz_220 ), //i + .io_cpu_fetch_isValid (_zz_215 ), //i + .io_cpu_fetch_isStuck (_zz_216 ), //i + .io_cpu_fetch_isRemoved (_zz_217 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i @@ -1793,8 +1811,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_221 ), //i - .io_cpu_decode_isStuck (_zz_222 ), //i + .io_cpu_decode_isValid (_zz_218 ), //i + .io_cpu_decode_isStuck (_zz_219 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1802,8 +1820,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_223 ), //i - .io_cpu_fill_valid (_zz_224 ), //i + .io_cpu_decode_isUser (_zz_220 ), //i + .io_cpu_fill_valid (_zz_221 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1812,56 +1830,58 @@ module VexRiscv_inner ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_16 (_zz_177[2:0] ), //i + ._zz_16 (_zz_172[2:0] ), //i ._zz_17 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_225 ), //i - .io_cpu_execute_address (_zz_226[31:0] ), //i + .io_cpu_execute_isValid (_zz_222 ), //i + .io_cpu_execute_address (_zz_223[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_87[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_memory_isValid (_zz_227 ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_224 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_228[31:0] ), //i + .io_cpu_memory_address (_zz_225[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_229 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_226 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_230 ), //i + .io_cpu_writeBack_isValid (_zz_227 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_231 ), //i + .io_cpu_writeBack_isUser (_zz_228 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_232[31:0] ), //i + .io_cpu_writeBack_address (_zz_229[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_233 ), //i - .io_cpu_writeBack_fence_SR (_zz_234 ), //i - .io_cpu_writeBack_fence_SO (_zz_235 ), //i - .io_cpu_writeBack_fence_SI (_zz_236 ), //i - .io_cpu_writeBack_fence_PW (_zz_237 ), //i - .io_cpu_writeBack_fence_PR (_zz_238 ), //i - .io_cpu_writeBack_fence_PO (_zz_239 ), //i - .io_cpu_writeBack_fence_PI (_zz_240 ), //i - .io_cpu_writeBack_fence_FM (_zz_241[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_230 ), //i + .io_cpu_writeBack_fence_SR (_zz_231 ), //i + .io_cpu_writeBack_fence_SO (_zz_232 ), //i + .io_cpu_writeBack_fence_SI (_zz_233 ), //i + .io_cpu_writeBack_fence_PW (_zz_234 ), //i + .io_cpu_writeBack_fence_PR (_zz_235 ), //i + .io_cpu_writeBack_fence_PO (_zz_236 ), //i + .io_cpu_writeBack_fence_PI (_zz_237 ), //i + .io_cpu_writeBack_fence_FM (_zz_238[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_242 ), //i + .io_cpu_flush_valid (_zz_239 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_243 ), //i + .io_mem_cmd_ready (_zz_240 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1877,18 +1897,18 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_389) + case(_zz_388) 2'b00 : begin - _zz_246 = DBusCachedPlugin_redoBranch_payload; + _zz_243 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_246 = CsrPlugin_jumpInterface_payload; + _zz_243 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_246 = BranchPlugin_jumpInterface_payload; + _zz_243 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_246 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_243 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2643,7 +2663,7 @@ module VexRiscv_inner ( end `endif - assign memory_MUL_LOW = ($signed(_zz_288) + $signed(_zz_296)); + assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2652,42 +2672,42 @@ module VexRiscv_inner ( assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_298; + assign execute_SHIFT_RIGHT = _zz_297; assign execute_REGFILE_WRITE_DATA = _zz_107; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_226[1 : 0]; - assign decode_DO_EBREAK = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); + assign execute_MEMORY_ADDRESS_LOW = _zz_223[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_300[0]; - assign decode_IS_RS1_SIGNED = _zz_301[0]; - assign decode_IS_DIV = _zz_302[0]; + assign decode_IS_RS2_SIGNED = _zz_299[0]; + assign decode_IS_RS1_SIGNED = _zz_300[0]; + assign decode_IS_DIV = _zz_301[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_303[0]; + assign decode_IS_MUL = _zz_302[0]; assign decode_CfuPlugin_CFU_ENCODING = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_304[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_305[0]; + assign decode_IS_CSR = _zz_304[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_306[0]; - assign decode_MEMORY_MANAGMENT = _zz_307[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; + assign decode_MEMORY_MANAGMENT = _zz_306[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_308[0]; + assign decode_MEMORY_WR = _zz_307[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_309[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_310[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2701,7 +2721,7 @@ module VexRiscv_inner ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_311[0]; + assign decode_IS_EBREAK = _zz_310[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2726,13 +2746,13 @@ module VexRiscv_inner ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_129; + assign execute_BRANCH_COND_RESULT = _zz_124; assign execute_BRANCH_CTRL = _zz_34; - assign decode_RS2_USE = _zz_312[0]; - assign decode_RS1_USE = _zz_313[0]; + assign decode_RS2_USE = _zz_311[0]; + assign decode_RS1_USE = _zz_312[0]; always @ (*) begin _zz_35 = execute_REGFILE_WRITE_DATA; - if(_zz_247)begin + if(_zz_244)begin _zz_35 = execute_CsrPlugin_readData; end end @@ -2745,28 +2765,28 @@ module VexRiscv_inner ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_118)begin - if((_zz_119 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_120; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_248)begin - if(_zz_249)begin - if(_zz_122)begin + if(_zz_245)begin + if(_zz_246)begin + if(_zz_117)begin decode_RS2 = _zz_55; end end end - if(_zz_250)begin + if(_zz_247)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_124)begin + if(_zz_119)begin decode_RS2 = _zz_36; end end end - if(_zz_251)begin + if(_zz_248)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_126)begin + if(_zz_121)begin decode_RS2 = _zz_35; end end @@ -2775,28 +2795,28 @@ module VexRiscv_inner ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_118)begin - if((_zz_119 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_120; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_248)begin - if(_zz_249)begin - if(_zz_121)begin + if(_zz_245)begin + if(_zz_246)begin + if(_zz_116)begin decode_RS1 = _zz_55; end end end - if(_zz_250)begin + if(_zz_247)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_123)begin + if(_zz_118)begin decode_RS1 = _zz_36; end end end - if(_zz_251)begin + if(_zz_248)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_125)begin + if(_zz_120)begin decode_RS1 = _zz_35; end end @@ -2821,7 +2841,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_36 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_252)begin + if(_zz_249)begin _zz_36 = memory_DivPlugin_div_result; end end @@ -2834,8 +2854,8 @@ module VexRiscv_inner ( assign _zz_39 = execute_PC; assign execute_SRC2_CTRL = _zz_40; assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_314[0]; - assign decode_SRC_ADD_ZERO = _zz_315[0]; + assign decode_SRC_USE_SUB_LESS = _zz_313[0]; + assign decode_SRC_ADD_ZERO = _zz_314[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_42; @@ -2853,25 +2873,25 @@ module VexRiscv_inner ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_316[0]; + decode_REGFILE_WRITE_VALID = _zz_315[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_390) == 32'h00000003),{(_zz_391 == _zz_392),{_zz_393,{_zz_394,_zz_395}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_389) == 32'h00000003),{(_zz_390 == _zz_391),{_zz_392,{_zz_393,_zz_394}}}}}}} != 22'h0); always @ (*) begin _zz_55 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_55 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_287) + case(_zz_286) 2'b00 : begin - _zz_55 = _zz_362; + _zz_55 = _zz_361; end default : begin - _zz_55 = _zz_363; + _zz_55 = _zz_362; end endcase end @@ -2890,32 +2910,32 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_317[0]; - assign decode_FLUSH_ALL = _zz_318[0]; + assign decode_MEMORY_ENABLE = _zz_316[0]; + assign decode_FLUSH_ALL = _zz_317[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_253)begin + if(_zz_250)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_254)begin + if(_zz_251)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_255)begin + if(_zz_252)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_256)begin + if(_zz_253)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2944,7 +2964,7 @@ module VexRiscv_inner ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_177) + case(_zz_172) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2955,7 +2975,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_116 || _zz_117)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2968,7 +2988,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_257)begin + if(_zz_254)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2982,25 +3002,22 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_257)begin + if(_zz_254)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_242 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_239 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(((dataCache_1_io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin - execute_arbitration_haltItself = 1'b1; - end - if(_zz_258)begin + if(_zz_255)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_247)begin + if(_zz_244)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3012,7 +3029,10 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_259)begin + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_256)begin execute_arbitration_haltByOther = 1'b1; end end @@ -3029,8 +3049,8 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_259)begin - if(_zz_260)begin + if(_zz_256)begin + if(_zz_257)begin execute_arbitration_flushIt = 1'b1; end end @@ -3041,8 +3061,8 @@ module VexRiscv_inner ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_259)begin - if(_zz_260)begin + if(_zz_256)begin + if(_zz_257)begin execute_arbitration_flushNext = 1'b1; end end @@ -3055,7 +3075,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_252)begin + if(_zz_249)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3065,7 +3085,7 @@ module VexRiscv_inner ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_261)begin + if(_zz_258)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3079,7 +3099,7 @@ module VexRiscv_inner ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(_zz_258)begin memory_arbitration_flushNext = 1'b1; end end @@ -3117,10 +3137,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_262)begin + if(_zz_259)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_263)begin + if(_zz_260)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3134,21 +3154,21 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_262)begin + if(_zz_259)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_263)begin + if(_zz_260)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_259)begin - if(_zz_260)begin + if(_zz_256)begin + if(_zz_257)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_264)begin + if(_zz_261)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3169,7 +3189,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_258)begin + if(_zz_255)begin CsrPlugin_inWfi = 1'b1; end end @@ -3183,21 +3203,21 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_262)begin + if(_zz_259)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_263)begin + if(_zz_260)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_262)begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_259)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_263)begin - case(_zz_265) + if(_zz_260)begin + case(_zz_262) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3231,11 +3251,11 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_60 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_61 = (_zz_60 & (~ _zz_319)); + assign _zz_61 = (_zz_60 & (~ _zz_318)); assign _zz_62 = _zz_61[3]; assign _zz_63 = (_zz_61[1] || _zz_62); assign _zz_64 = (_zz_61[2] || _zz_62); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_246; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_243; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3255,7 +3275,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_321); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_320); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3347,7 +3367,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_177) + case(_zz_172) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3359,7 +3379,7 @@ module VexRiscv_inner ( endcase end - assign _zz_74 = _zz_322[11]; + assign _zz_74 = _zz_321[11]; always @ (*) begin _zz_75[18] = _zz_74; _zz_75[17] = _zz_74; @@ -3383,13 +3403,13 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_323[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_322[31])); if(_zz_80)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_76 = _zz_324[19]; + assign _zz_76 = _zz_323[19]; always @ (*) begin _zz_77[10] = _zz_76; _zz_77[9] = _zz_76; @@ -3404,7 +3424,7 @@ module VexRiscv_inner ( _zz_77[0] = _zz_76; end - assign _zz_78 = _zz_325[11]; + assign _zz_78 = _zz_324[11]; always @ (*) begin _zz_79[18] = _zz_78; _zz_79[17] = _zz_78; @@ -3430,16 +3450,16 @@ module VexRiscv_inner ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_80 = _zz_326[1]; + _zz_80 = _zz_325[1]; end default : begin - _zz_80 = _zz_327[1]; + _zz_80 = _zz_326[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_81 = _zz_328[19]; + assign _zz_81 = _zz_327[19]; always @ (*) begin _zz_82[10] = _zz_81; _zz_82[9] = _zz_81; @@ -3454,7 +3474,7 @@ module VexRiscv_inner ( _zz_82[0] = _zz_81; end - assign _zz_83 = _zz_329[11]; + assign _zz_83 = _zz_328[11]; always @ (*) begin _zz_84[18] = _zz_83; _zz_84[17] = _zz_83; @@ -3477,7 +3497,7 @@ module VexRiscv_inner ( _zz_84[0] = _zz_83; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_82,{{{_zz_408,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_84,{{{_zz_409,_zz_410},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_82,{{{_zz_407,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_84,{{{_zz_408,_zz_409},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3486,52 +3506,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_217 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_219 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_218; + assign _zz_214 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_215 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_216 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_215; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_222 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_223 = (CsrPlugin_privilege == 2'b00); + assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_219 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_220 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_256)begin + if(_zz_253)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_254)begin + if(_zz_251)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_224 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_254)begin - _zz_224 = 1'b1; + _zz_221 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_251)begin + _zz_221 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_255)begin + if(_zz_252)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_253)begin + if(_zz_250)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_255)begin + if(_zz_252)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_253)begin + if(_zz_250)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3541,9 +3561,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_216 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_213 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_243 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_240 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3570,8 +3590,8 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_225 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_226 = execute_SRC_ADD; + assign _zz_222 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_223 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3586,27 +3606,27 @@ module VexRiscv_inner ( endcase end - assign _zz_242 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_227 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_228 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_227; + assign _zz_239 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_224 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_225 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_224; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_228; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_225; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_229 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_226 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_59 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_229 = 1'b1; + _zz_226 = 1'b1; end end - assign _zz_230 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_231 = (CsrPlugin_privilege == 2'b00); - assign _zz_232 = writeBack_REGFILE_WRITE_DATA; + assign _zz_227 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_228 = (CsrPlugin_privilege == 2'b00); + assign _zz_229 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_266)begin + if(_zz_263)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3616,14 +3636,14 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_266)begin + if(_zz_263)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end if(dataCache_1_io_cpu_redo)begin @@ -3635,16 +3655,16 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_266)begin + if(_zz_263)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_330}; - end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_331}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_330}; + end end end @@ -3716,7 +3736,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_285) + case(_zz_284) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_89; end @@ -3734,6 +3754,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; @@ -3742,6 +3763,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; @@ -3750,7 +3772,7 @@ module VexRiscv_inner ( assign _zz_95 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_96 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); assign _zz_97 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_92 = {(((decode_INSTRUCTION & _zz_411) == 32'h00100050) != 1'b0),{(_zz_97 != 1'b0),{(_zz_97 != 1'b0),{(_zz_412 != _zz_413),{_zz_414,{_zz_415,_zz_416}}}}}}; + assign _zz_92 = {(((decode_INSTRUCTION & _zz_410) == 32'h00100050) != 1'b0),{(_zz_97 != 1'b0),{(_zz_97 != 1'b0),{(_zz_411 != _zz_412),{_zz_413,{_zz_414,_zz_415}}}}}}; assign _zz_98 = _zz_92[2 : 1]; assign _zz_54 = _zz_98; assign _zz_99 = _zz_92[7 : 6]; @@ -3772,8 +3794,8 @@ module VexRiscv_inner ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_244; - assign decode_RegFilePlugin_rs2Data = _zz_245; + assign decode_RegFilePlugin_rs1Data = _zz_241; + assign decode_RegFilePlugin_rs2Data = _zz_242; always @ (*) begin lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); if(_zz_106)begin @@ -3781,8 +3803,20 @@ module VexRiscv_inner ( end end - assign lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_55; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; + if(_zz_106)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_55; + if(_zz_106)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -3803,7 +3837,7 @@ module VexRiscv_inner ( _zz_107 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_107 = {31'd0, _zz_332}; + _zz_107 = {31'd0, _zz_331}; end default : begin _zz_107 = execute_SRC_ADD_SUB; @@ -3817,18 +3851,18 @@ module VexRiscv_inner ( _zz_108 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_108 = {29'd0, _zz_333}; + _zz_108 = {29'd0, _zz_332}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_108 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_108 = {27'd0, _zz_334}; + _zz_108 = {27'd0, _zz_333}; end endcase end - assign _zz_109 = _zz_335[11]; + assign _zz_109 = _zz_334[11]; always @ (*) begin _zz_110[19] = _zz_109; _zz_110[18] = _zz_109; @@ -3852,7 +3886,7 @@ module VexRiscv_inner ( _zz_110[0] = _zz_109; end - assign _zz_111 = _zz_336[11]; + assign _zz_111 = _zz_335[11]; always @ (*) begin _zz_112[19] = _zz_111; _zz_112[18] = _zz_111; @@ -3894,7 +3928,7 @@ module VexRiscv_inner ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_337; + execute_SrcPlugin_addSub = _zz_336; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3974,175 +4008,180 @@ module VexRiscv_inner ( end always @ (*) begin - _zz_116 = 1'b0; - if(_zz_267)begin - if(_zz_268)begin - if(_zz_121)begin - _zz_116 = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_264)begin + if(_zz_265)begin + if(_zz_116)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_269)begin - if(_zz_270)begin - if(_zz_123)begin - _zz_116 = 1'b1; + if(_zz_266)begin + if(_zz_267)begin + if(_zz_118)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_271)begin - if(_zz_272)begin - if(_zz_125)begin - _zz_116 = 1'b1; + if(_zz_268)begin + if(_zz_269)begin + if(_zz_120)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_116 = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_117 = 1'b0; - if(_zz_267)begin - if(_zz_268)begin - if(_zz_122)begin - _zz_117 = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_264)begin + if(_zz_265)begin + if(_zz_117)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_269)begin - if(_zz_270)begin - if(_zz_124)begin - _zz_117 = 1'b1; + if(_zz_266)begin + if(_zz_267)begin + if(_zz_119)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_271)begin - if(_zz_272)begin - if(_zz_126)begin - _zz_117 = 1'b1; + if(_zz_268)begin + if(_zz_269)begin + if(_zz_121)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_117 = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_121 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_123 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_125 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_45 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_44[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_55; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_116 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_117 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_118 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_119 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_120 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_121 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_127 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_127 == 3'b000)) begin - _zz_128 = execute_BranchPlugin_eq; - end else if((_zz_127 == 3'b001)) begin - _zz_128 = (! execute_BranchPlugin_eq); - end else if((((_zz_127 & 3'b101) == 3'b101))) begin - _zz_128 = (! execute_SRC_LESS); + assign _zz_122 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_122 == 3'b000)) begin + _zz_123 = execute_BranchPlugin_eq; + end else if((_zz_122 == 3'b001)) begin + _zz_123 = (! execute_BranchPlugin_eq); + end else if((((_zz_122 & 3'b101) == 3'b101))) begin + _zz_123 = (! execute_SRC_LESS); end else begin - _zz_128 = execute_SRC_LESS; + _zz_123 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_129 = 1'b0; + _zz_124 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_129 = 1'b1; + _zz_124 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_129 = 1'b1; + _zz_124 = 1'b1; end default : begin - _zz_129 = _zz_128; + _zz_124 = _zz_123; end endcase end - assign _zz_130 = _zz_344[11]; - always @ (*) begin - _zz_131[19] = _zz_130; - _zz_131[18] = _zz_130; - _zz_131[17] = _zz_130; - _zz_131[16] = _zz_130; - _zz_131[15] = _zz_130; - _zz_131[14] = _zz_130; - _zz_131[13] = _zz_130; - _zz_131[12] = _zz_130; - _zz_131[11] = _zz_130; - _zz_131[10] = _zz_130; - _zz_131[9] = _zz_130; - _zz_131[8] = _zz_130; - _zz_131[7] = _zz_130; - _zz_131[6] = _zz_130; - _zz_131[5] = _zz_130; - _zz_131[4] = _zz_130; - _zz_131[3] = _zz_130; - _zz_131[2] = _zz_130; - _zz_131[1] = _zz_130; - _zz_131[0] = _zz_130; - end - - assign _zz_132 = _zz_345[19]; - always @ (*) begin - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; - end - - assign _zz_134 = _zz_346[11]; - always @ (*) begin - _zz_135[18] = _zz_134; - _zz_135[17] = _zz_134; - _zz_135[16] = _zz_134; - _zz_135[15] = _zz_134; - _zz_135[14] = _zz_134; - _zz_135[13] = _zz_134; - _zz_135[12] = _zz_134; - _zz_135[11] = _zz_134; - _zz_135[10] = _zz_134; - _zz_135[9] = _zz_134; - _zz_135[8] = _zz_134; - _zz_135[7] = _zz_134; - _zz_135[6] = _zz_134; - _zz_135[5] = _zz_134; - _zz_135[4] = _zz_134; - _zz_135[3] = _zz_134; - _zz_135[2] = _zz_134; - _zz_135[1] = _zz_134; - _zz_135[0] = _zz_134; + assign _zz_125 = _zz_343[11]; + always @ (*) begin + _zz_126[19] = _zz_125; + _zz_126[18] = _zz_125; + _zz_126[17] = _zz_125; + _zz_126[16] = _zz_125; + _zz_126[15] = _zz_125; + _zz_126[14] = _zz_125; + _zz_126[13] = _zz_125; + _zz_126[12] = _zz_125; + _zz_126[11] = _zz_125; + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; + end + + assign _zz_127 = _zz_344[19]; + always @ (*) begin + _zz_128[10] = _zz_127; + _zz_128[9] = _zz_127; + _zz_128[8] = _zz_127; + _zz_128[7] = _zz_127; + _zz_128[6] = _zz_127; + _zz_128[5] = _zz_127; + _zz_128[4] = _zz_127; + _zz_128[3] = _zz_127; + _zz_128[2] = _zz_127; + _zz_128[1] = _zz_127; + _zz_128[0] = _zz_127; + end + + assign _zz_129 = _zz_345[11]; + always @ (*) begin + _zz_130[18] = _zz_129; + _zz_130[17] = _zz_129; + _zz_130[16] = _zz_129; + _zz_130[15] = _zz_129; + _zz_130[14] = _zz_129; + _zz_130[13] = _zz_129; + _zz_130[12] = _zz_129; + _zz_130[11] = _zz_129; + _zz_130[10] = _zz_129; + _zz_130[9] = _zz_129; + _zz_130[8] = _zz_129; + _zz_130[7] = _zz_129; + _zz_130[6] = _zz_129; + _zz_130[5] = _zz_129; + _zz_130[4] = _zz_129; + _zz_130[3] = _zz_129; + _zz_130[2] = _zz_129; + _zz_130[1] = _zz_129; + _zz_130[0] = _zz_129; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_136 = (_zz_347[1] ^ execute_RS1[1]); + _zz_131 = (_zz_346[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_136 = _zz_348[1]; + _zz_131 = _zz_347[1]; end default : begin - _zz_136 = _zz_349[1]; + _zz_131 = _zz_348[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_136); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_131); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4154,80 +4193,80 @@ module VexRiscv_inner ( endcase end - assign _zz_137 = _zz_350[11]; + assign _zz_132 = _zz_349[11]; always @ (*) begin - _zz_138[19] = _zz_137; - _zz_138[18] = _zz_137; - _zz_138[17] = _zz_137; - _zz_138[16] = _zz_137; - _zz_138[15] = _zz_137; - _zz_138[14] = _zz_137; - _zz_138[13] = _zz_137; - _zz_138[12] = _zz_137; - _zz_138[11] = _zz_137; - _zz_138[10] = _zz_137; - _zz_138[9] = _zz_137; - _zz_138[8] = _zz_137; - _zz_138[7] = _zz_137; - _zz_138[6] = _zz_137; - _zz_138[5] = _zz_137; - _zz_138[4] = _zz_137; - _zz_138[3] = _zz_137; - _zz_138[2] = _zz_137; - _zz_138[1] = _zz_137; - _zz_138[0] = _zz_137; + _zz_133[19] = _zz_132; + _zz_133[18] = _zz_132; + _zz_133[17] = _zz_132; + _zz_133[16] = _zz_132; + _zz_133[15] = _zz_132; + _zz_133[14] = _zz_132; + _zz_133[13] = _zz_132; + _zz_133[12] = _zz_132; + _zz_133[11] = _zz_132; + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_138,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_133,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_140,{{{_zz_588,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_142,{{{_zz_589,_zz_590},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_135,{{{_zz_587,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_137,{{{_zz_588,_zz_589},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_353}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_352}; end end endcase end - assign _zz_139 = _zz_351[19]; - always @ (*) begin - _zz_140[10] = _zz_139; - _zz_140[9] = _zz_139; - _zz_140[8] = _zz_139; - _zz_140[7] = _zz_139; - _zz_140[6] = _zz_139; - _zz_140[5] = _zz_139; - _zz_140[4] = _zz_139; - _zz_140[3] = _zz_139; - _zz_140[2] = _zz_139; - _zz_140[1] = _zz_139; - _zz_140[0] = _zz_139; - end - - assign _zz_141 = _zz_352[11]; - always @ (*) begin - _zz_142[18] = _zz_141; - _zz_142[17] = _zz_141; - _zz_142[16] = _zz_141; - _zz_142[15] = _zz_141; - _zz_142[14] = _zz_141; - _zz_142[13] = _zz_141; - _zz_142[12] = _zz_141; - _zz_142[11] = _zz_141; - _zz_142[10] = _zz_141; - _zz_142[9] = _zz_141; - _zz_142[8] = _zz_141; - _zz_142[7] = _zz_141; - _zz_142[6] = _zz_141; - _zz_142[5] = _zz_141; - _zz_142[4] = _zz_141; - _zz_142[3] = _zz_141; - _zz_142[2] = _zz_141; - _zz_142[1] = _zz_141; - _zz_142[0] = _zz_141; + assign _zz_134 = _zz_350[19]; + always @ (*) begin + _zz_135[10] = _zz_134; + _zz_135[9] = _zz_134; + _zz_135[8] = _zz_134; + _zz_135[7] = _zz_134; + _zz_135[6] = _zz_134; + _zz_135[5] = _zz_134; + _zz_135[4] = _zz_134; + _zz_135[3] = _zz_134; + _zz_135[2] = _zz_134; + _zz_135[1] = _zz_134; + _zz_135[0] = _zz_134; + end + + assign _zz_136 = _zz_351[11]; + always @ (*) begin + _zz_137[18] = _zz_136; + _zz_137[17] = _zz_136; + _zz_137[16] = _zz_136; + _zz_137[15] = _zz_136; + _zz_137[14] = _zz_136; + _zz_137[13] = _zz_136; + _zz_137[12] = _zz_136; + _zz_137[11] = _zz_136; + _zz_137[10] = _zz_136; + _zz_137[9] = _zz_136; + _zz_137[8] = _zz_136; + _zz_137[7] = _zz_136; + _zz_137[6] = _zz_136; + _zz_137[5] = _zz_136; + _zz_137[4] = _zz_136; + _zz_137[3] = _zz_136; + _zz_137[2] = _zz_136; + _zz_137[1] = _zz_136; + _zz_137[0] = _zz_136; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -4244,18 +4283,18 @@ module VexRiscv_inner ( end end - assign _zz_143 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_144 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_145 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_138 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_139 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_140 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_146 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_147 = _zz_354[0]; - assign _zz_148 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_149 = _zz_356[0]; + assign _zz_141 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_142 = _zz_353[0]; + assign _zz_143 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_144 = _zz_355[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_257)begin + if(_zz_254)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4275,7 +4314,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_261)begin + if(_zz_258)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4336,7 +4375,7 @@ module VexRiscv_inner ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4424,6 +4463,16 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end if(execute_CsrPlugin_csr_2820)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4496,7 +4545,7 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + if(_zz_270)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4515,20 +4564,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_273)begin + if(_zz_271)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_274)begin + if(_zz_272)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_273)begin + if(_zz_271)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_274)begin + if(_zz_272)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4541,13 +4590,25 @@ module VexRiscv_inner ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_270)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_270)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_286) + case(_zz_285) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4560,49 +4621,49 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_358; + assign execute_CfuPlugin_functionsIds_0 = _zz_357; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_166 = _zz_359[11]; - always @ (*) begin - _zz_167[19] = _zz_166; - _zz_167[18] = _zz_166; - _zz_167[17] = _zz_166; - _zz_167[16] = _zz_166; - _zz_167[15] = _zz_166; - _zz_167[14] = _zz_166; - _zz_167[13] = _zz_166; - _zz_167[12] = _zz_166; - _zz_167[11] = _zz_166; - _zz_167[10] = _zz_166; - _zz_167[9] = _zz_166; - _zz_167[8] = _zz_166; - _zz_167[7] = _zz_166; - _zz_167[6] = _zz_166; - _zz_167[5] = _zz_166; - _zz_167[4] = _zz_166; - _zz_167[3] = _zz_166; - _zz_167[2] = _zz_166; - _zz_167[1] = _zz_166; - _zz_167[0] = _zz_166; + assign _zz_161 = _zz_358[11]; + always @ (*) begin + _zz_162[19] = _zz_161; + _zz_162[18] = _zz_161; + _zz_162[17] = _zz_161; + _zz_162[16] = _zz_161; + _zz_162[15] = _zz_161; + _zz_162[14] = _zz_161; + _zz_162[13] = _zz_161; + _zz_162[12] = _zz_161; + _zz_162[11] = _zz_161; + _zz_162[10] = _zz_161; + _zz_162[9] = _zz_161; + _zz_162[8] = _zz_161; + _zz_162[7] = _zz_161; + _zz_162[6] = _zz_161; + _zz_162[5] = _zz_161; + _zz_162[4] = _zz_161; + _zz_162[3] = _zz_161; + _zz_162[2] = _zz_161; + _zz_162[1] = _zz_161; + _zz_162[0] = _zz_161; end always @ (*) begin case(execute_CfuPlugin_CFU_ENCODING) `Input2Kind_defaultEncoding_RS : begin - _zz_168 = execute_RS2; + _zz_163 = execute_RS2; end default : begin - _zz_168 = {_zz_167,execute_INSTRUCTION[31 : 20]}; + _zz_163 = {_zz_162,execute_INSTRUCTION[31 : 20]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_168; - assign CfuPlugin_bus_rsp_ready = ((1'b1 && (! memory_CfuPlugin_rsp_valid)) || memory_CfuPlugin_rsp_ready); - assign memory_CfuPlugin_rsp_valid = CfuPlugin_bus_rsp_m2sPipe_rValid; - assign memory_CfuPlugin_rsp_payload_response_ok = CfuPlugin_bus_rsp_m2sPipe_rData_response_ok; - assign memory_CfuPlugin_rsp_payload_outputs_0 = CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_163; + assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); + assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); + assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); always @ (*) begin CfuPlugin_joinException_valid = 1'b0; if(memory_CfuPlugin_CFU_IN_FLIGHT)begin @@ -4624,7 +4685,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_275) + case(_zz_273) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4638,7 +4699,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_275) + case(_zz_273) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4657,12 +4718,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_360) + $signed(_zz_361)); + assign writeBack_MulPlugin_result = ($signed(_zz_359) + $signed(_zz_360)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_252)begin - if(_zz_276)begin + if(_zz_249)begin + if(_zz_274)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4670,7 +4731,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_277)begin + if(_zz_275)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4681,32 +4742,32 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_365); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_364); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_169 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_169[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_366); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_367 : _zz_368); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_369[31:0]; - assign _zz_170 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_171 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_172 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_164 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_164[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_365); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_366 : _zz_367); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_368[31:0]; + assign _zz_165 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_166 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_167 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_173[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_173[31 : 0] = execute_RS1; + _zz_168[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_168[31 : 0] = execute_RS1; end - assign _zz_175 = (_zz_174 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_175 != 32'h0); + assign _zz_170 = (_zz_169 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_170 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_278) + case(_zz_276) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4720,7 +4781,7 @@ module VexRiscv_inner ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_176))begin + if((! _zz_171))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4732,7 +4793,7 @@ module VexRiscv_inner ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_278) + case(_zz_276) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4745,6 +4806,7 @@ module VexRiscv_inner ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); assign debug_resetOut = DebugPlugin_resetIt_regNext; assign _zz_29 = decode_SRC1_CTRL; assign _zz_27 = _zz_54; @@ -4798,7 +4860,7 @@ module VexRiscv_inner ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_177) + case(_zz_172) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4808,258 +4870,272 @@ module VexRiscv_inner ( end always @ (*) begin - _zz_178 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_178[12 : 0] = 13'h1000; - _zz_178[25 : 20] = 6'h20; + _zz_173[12 : 0] = 13'h1000; + _zz_173[25 : 20] = 6'h20; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_179[3 : 0] = 4'b1011; + _zz_174[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_180[4 : 0] = 5'h16; + _zz_175[4 : 0] = 5'h16; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_181[5 : 0] = 6'h21; + _zz_176[5 : 0] = 6'h21; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_182[31 : 30] = CsrPlugin_misa_base; - _zz_182[25 : 0] = CsrPlugin_misa_extensions; + _zz_177[31 : 30] = CsrPlugin_misa_base; + _zz_177[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_183[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_183[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_183[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_178[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_178[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_178[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_184[11 : 11] = CsrPlugin_mip_MEIP; - _zz_184[7 : 7] = CsrPlugin_mip_MTIP; - _zz_184[3 : 3] = CsrPlugin_mip_MSIP; + _zz_179[11 : 11] = CsrPlugin_mip_MEIP; + _zz_179[7 : 7] = CsrPlugin_mip_MTIP; + _zz_179[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_185[11 : 11] = CsrPlugin_mie_MEIE; - _zz_185[7 : 7] = CsrPlugin_mie_MTIE; - _zz_185[3 : 3] = CsrPlugin_mie_MSIE; + _zz_180[11 : 11] = CsrPlugin_mie_MEIE; + _zz_180[7 : 7] = CsrPlugin_mie_MTIE; + _zz_180[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_186[31 : 2] = CsrPlugin_mtvec_base; - _zz_186[1 : 0] = CsrPlugin_mtvec_mode; + _zz_181[31 : 2] = CsrPlugin_mtvec_base; + _zz_181[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_187[31 : 0] = CsrPlugin_mepc; + _zz_182[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_188[31 : 0] = CsrPlugin_mscratch; + _zz_183[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_189[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_189[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_184[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_184[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_190[31 : 0] = CsrPlugin_mtval; + _zz_185[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_191[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_186[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_192[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_187[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_193[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_188[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_194[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_189[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_195[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_196[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_192 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_193 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_2820)begin - _zz_197[31 : 0] = _zz_150; + _zz_194[31 : 0] = _zz_145; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_2822)begin - _zz_198[31 : 0] = _zz_152; + _zz_195[31 : 0] = _zz_147; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_2824)begin - _zz_199[31 : 0] = _zz_154; + _zz_196[31 : 0] = _zz_149; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_2826)begin - _zz_200[31 : 0] = _zz_156; + _zz_197[31 : 0] = _zz_151; end end always @ (*) begin - _zz_201 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_2828)begin - _zz_201[31 : 0] = _zz_158; + _zz_198[31 : 0] = _zz_153; end end always @ (*) begin - _zz_202 = 32'h0; + _zz_199 = 32'h0; if(execute_CsrPlugin_csr_2830)begin - _zz_202[31 : 0] = _zz_160; + _zz_199[31 : 0] = _zz_155; end end always @ (*) begin - _zz_203 = 32'h0; + _zz_200 = 32'h0; if(execute_CsrPlugin_csr_2832)begin - _zz_203[31 : 0] = _zz_162; + _zz_200[31 : 0] = _zz_157; end end always @ (*) begin - _zz_204 = 32'h0; + _zz_201 = 32'h0; if(execute_CsrPlugin_csr_2834)begin - _zz_204[31 : 0] = _zz_164; + _zz_201[31 : 0] = _zz_159; end end always @ (*) begin - _zz_205 = 32'h0; + _zz_202 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_205[31 : 0] = _zz_174; + _zz_202[31 : 0] = _zz_169; end end always @ (*) begin - _zz_206 = 32'h0; + _zz_203 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_206[31 : 0] = _zz_175; + _zz_203[31 : 0] = _zz_170; end end - assign execute_CsrPlugin_readData = (((((_zz_178 | _zz_179) | (_zz_180 | _zz_181)) | ((_zz_591 | _zz_182) | (_zz_183 | _zz_184))) | (((_zz_185 | _zz_186) | (_zz_187 | _zz_188)) | ((_zz_189 | _zz_190) | (_zz_191 | _zz_192)))) | ((((_zz_193 | _zz_194) | (_zz_195 | _zz_196)) | ((_zz_197 | _zz_198) | (_zz_199 | _zz_200))) | (((_zz_201 | _zz_202) | (_zz_203 | _zz_204)) | (_zz_205 | _zz_206)))); - assign iBusWishbone_ADR = {_zz_386,_zz_207}; - assign iBusWishbone_CTI = ((_zz_207 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_173 | _zz_174) | (_zz_175 | _zz_176)) | ((_zz_590 | _zz_177) | (_zz_178 | _zz_179))) | (((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_184 | _zz_185) | (_zz_186 | _zz_187)))) | ((((_zz_188 | _zz_189) | (_zz_190 | _zz_191)) | ((_zz_192 | _zz_193) | (_zz_194 | _zz_195))) | (((_zz_196 | _zz_197) | (_zz_198 | _zz_199)) | ((_zz_200 | _zz_201) | (_zz_202 | _zz_203))))); + assign iBusWishbone_ADR = {_zz_385,_zz_204}; + assign iBusWishbone_CTI = ((_zz_204 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_279)begin + if(_zz_277)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_279)begin + if(_zz_277)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_208; + assign iBus_rsp_valid = _zz_205; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_214 = (dBus_cmd_payload_length != 3'b000); - assign _zz_210 = dBus_cmd_valid; - assign _zz_212 = dBus_cmd_payload_wr; - assign _zz_213 = (_zz_209 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_211 && (_zz_212 || _zz_213)); - assign dBusWishbone_ADR = ((_zz_214 ? {{dBus_cmd_payload_address[31 : 5],_zz_209},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_214 ? (_zz_213 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_211 = (dBus_cmd_payload_length != 3'b000); + assign _zz_207 = dBus_cmd_valid; + assign _zz_209 = dBus_cmd_payload_wr; + assign _zz_210 = (_zz_206 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_208 && (_zz_209 || _zz_210)); + assign dBusWishbone_ADR = ((_zz_211 ? {{dBus_cmd_payload_address[31 : 5],_zz_206},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_211 ? (_zz_210 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_212 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_212; + assign dBusWishbone_SEL = (_zz_209 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_209; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_211 = (_zz_210 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_210; - assign dBusWishbone_STB = _zz_210; - assign dBus_rsp_valid = _zz_215; + assign _zz_208 = (_zz_207 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_207; + assign dBusWishbone_STB = _zz_207; + assign dBus_rsp_valid = _zz_212; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5082,7 +5158,7 @@ module VexRiscv_inner ( DBusCachedPlugin_rspCounter <= _zz_86; DBusCachedPlugin_rspCounter <= 32'h0; _zz_106 <= 1'b1; - _zz_118 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -5104,20 +5180,18 @@ module VexRiscv_inner ( execute_CsrPlugin_wfiWake <= 1'b0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_m2sPipe_rValid <= 1'b0; + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_174 <= 32'h0; + _zz_169 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_177 <= 3'b000; - memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; - memory_to_writeBack_INSTRUCTION <= 32'h0; + _zz_172 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_207 <= 3'b000; - _zz_208 <= 1'b0; - _zz_209 <= 3'b000; - _zz_215 <= 1'b0; + _zz_204 <= 3'b000; + _zz_205 <= 1'b0; + _zz_206 <= 3'b000; + _zz_212 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5198,7 +5272,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_280)begin + if(_zz_278)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5208,7 +5282,7 @@ module VexRiscv_inner ( DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end _zz_106 <= 1'b0; - _zz_118 <= (_zz_45 && writeBack_arbitration_isFiring); + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5230,14 +5304,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_281)begin - if(_zz_282)begin + if(_zz_279)begin + if(_zz_280)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_283)begin + if(_zz_281)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_284)begin + if(_zz_282)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5262,7 +5336,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_262)begin + if(_zz_259)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5273,8 +5347,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_263)begin - case(_zz_265) + if(_zz_260)begin + case(_zz_262) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5284,7 +5358,7 @@ module VexRiscv_inner ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_145,{_zz_144,_zz_143}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_140,{_zz_139,_zz_138}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -5297,16 +5371,13 @@ module VexRiscv_inner ( if((! execute_arbitration_isStuckByOthers))begin execute_CfuPlugin_fired <= 1'b0; end - if(CfuPlugin_bus_rsp_ready)begin - CfuPlugin_bus_rsp_m2sPipe_rValid <= CfuPlugin_bus_rsp_valid; + if(memory_CfuPlugin_rsp_ready)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_36; + if(_zz_283)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if((! memory_arbitration_isStuck))begin execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= execute_CfuPlugin_CFU_IN_FLIGHT; end @@ -5328,25 +5399,25 @@ module VexRiscv_inner ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_177) + case(_zz_172) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_177 <= 3'b001; + _zz_172 <= 3'b001; end end 3'b001 : begin - _zz_177 <= 3'b010; + _zz_172 <= 3'b010; end 3'b010 : begin - _zz_177 <= 3'b011; + _zz_172 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_177 <= 3'b100; + _zz_172 <= 3'b100; end end 3'b100 : begin - _zz_177 <= 3'b000; + _zz_172 <= 3'b000; end default : begin end @@ -5360,35 +5431,35 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_379[0]; - CsrPlugin_mstatus_MIE <= _zz_380[0]; + CsrPlugin_mstatus_MPIE <= _zz_378[0]; + CsrPlugin_mstatus_MIE <= _zz_379[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_382[0]; - CsrPlugin_mie_MTIE <= _zz_383[0]; - CsrPlugin_mie_MSIE <= _zz_384[0]; + CsrPlugin_mie_MEIE <= _zz_381[0]; + CsrPlugin_mie_MTIE <= _zz_382[0]; + CsrPlugin_mie_MSIE <= _zz_383[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_174 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_169 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_279)begin + if(_zz_277)begin if(iBusWishbone_ACK)begin - _zz_207 <= (_zz_207 + 3'b001); + _zz_204 <= (_zz_204 + 3'b001); end end - _zz_208 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_210 && _zz_211))begin - _zz_209 <= (_zz_209 + 3'b001); - if(_zz_213)begin - _zz_209 <= 3'b000; + _zz_205 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_207 && _zz_208))begin + _zz_206 <= (_zz_206 + 3'b001); + if(_zz_210)begin + _zz_206 <= 3'b000; end end - _zz_215 <= ((_zz_210 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_212 <= ((_zz_207 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5402,7 +5473,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_280)begin + if(_zz_278)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5420,8 +5491,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - _zz_119 <= _zz_44[11 : 7]; - _zz_120 <= _zz_55; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5429,37 +5500,37 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_257)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_147 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_147 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_254)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_142 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_142 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_261)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(_zz_258)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_144 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_144 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); end if(DBusCachedPlugin_exceptionBus_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_281)begin - if(_zz_282)begin + if(_zz_279)begin + if(_zz_280)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_283)begin + if(_zz_281)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_284)begin + if(_zz_282)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_262)begin + if(_zz_259)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5473,33 +5544,33 @@ module VexRiscv_inner ( end endcase end - if(_zz_151[0])begin - _zz_150 <= (_zz_150 + 32'h00000001); + if(_zz_146[0])begin + _zz_145 <= (_zz_145 + 32'h00000001); end - if(_zz_153[0])begin - _zz_152 <= (_zz_152 + 32'h00000001); + if(_zz_148[0])begin + _zz_147 <= (_zz_147 + 32'h00000001); end - if(_zz_155[0])begin - _zz_154 <= (_zz_154 + 32'h00000001); + if(_zz_150[0])begin + _zz_149 <= (_zz_149 + 32'h00000001); end - if(_zz_157[0])begin - _zz_156 <= (_zz_156 + 32'h00000001); + if(_zz_152[0])begin + _zz_151 <= (_zz_151 + 32'h00000001); end - if(_zz_159[0])begin - _zz_158 <= (_zz_158 + 32'h00000001); + if(_zz_154[0])begin + _zz_153 <= (_zz_153 + 32'h00000001); end - if(_zz_161[0])begin - _zz_160 <= (_zz_160 + 32'h00000001); + if(_zz_156[0])begin + _zz_155 <= (_zz_155 + 32'h00000001); end - if(_zz_163[0])begin - _zz_162 <= (_zz_162 + 32'h00000001); + if(_zz_158[0])begin + _zz_157 <= (_zz_157 + 32'h00000001); end - if(_zz_165[0])begin - _zz_164 <= (_zz_164 + 32'h00000001); + if(_zz_160[0])begin + _zz_159 <= (_zz_159 + 32'h00000001); end - if(CfuPlugin_bus_rsp_ready)begin - CfuPlugin_bus_rsp_m2sPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_m2sPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + if(_zz_283)begin + CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end if((memory_DivPlugin_div_counter_value == 6'h20))begin memory_DivPlugin_div_done <= 1'b1; @@ -5507,20 +5578,20 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_252)begin - if(_zz_276)begin + if(_zz_249)begin + if(_zz_274)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_370[31:0]; + memory_DivPlugin_div_result <= _zz_369[31:0]; end end end - if(_zz_277)begin + if(_zz_275)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_172 ? (~ _zz_173) : _zz_173) + _zz_376); - memory_DivPlugin_rs2 <= ((_zz_171 ? (~ execute_RS2) : execute_RS2) + _zz_378); - memory_DivPlugin_div_needRevert <= ((_zz_172 ^ (_zz_171 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_167 ? (~ _zz_168) : _zz_168) + _zz_375); + memory_DivPlugin_rs2 <= ((_zz_166 ? (~ execute_RS2) : execute_RS2) + _zz_377); + memory_DivPlugin_div_needRevert <= ((_zz_167 ^ (_zz_166 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5538,6 +5609,9 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end if((! execute_arbitration_isStuck))begin decode_to_execute_FORMAL_PC_NEXT <= _zz_58; end @@ -5685,6 +5759,9 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin execute_to_memory_REGFILE_WRITE_DATA <= _zz_35; end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_36; + end if((! memory_arbitration_isStuck))begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end @@ -5772,6 +5849,12 @@ module VexRiscv_inner ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); end @@ -5828,7 +5911,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_381[0]; + CsrPlugin_mip_MSIP <= _zz_380[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5849,7 +5932,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_385[0]; + CsrPlugin_mcause_interrupt <= _zz_384[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5880,82 +5963,82 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_2820)begin if(execute_CsrPlugin_writeEnable)begin - _zz_150 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_145 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2821)begin if(execute_CsrPlugin_writeEnable)begin - _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2822)begin if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_147 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2823)begin if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_148 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2824)begin if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_149 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2825)begin if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_150 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2826)begin if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2827)begin if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2828)begin if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2829)begin if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2830)begin if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2831)begin if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2832)begin if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2833)begin if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2834)begin if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2835)begin if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -5972,8 +6055,8 @@ module VexRiscv_inner ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_55; end - _zz_176 <= debug_bus_cmd_payload_address[2]; - if(_zz_259)begin + _zz_171 <= debug_bus_cmd_payload_address[2]; + if(_zz_256)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -5991,7 +6074,7 @@ module VexRiscv_inner ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_278) + case(_zz_276) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -6019,13 +6102,13 @@ module VexRiscv_inner ( end endcase end - if(_zz_259)begin - if(_zz_260)begin + if(_zz_256)begin + if(_zz_257)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_264)begin + if(_zz_261)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end @@ -6044,12 +6127,14 @@ module DataCache ( input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, input io_cpu_memory_isValid, input io_cpu_memory_isStuck, output io_cpu_memory_isWrite, input [31:0] io_cpu_memory_address, input [31:0] io_cpu_memory_mmuRsp_physicalAddress, input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, input io_cpu_memory_mmuRsp_allowRead, input io_cpu_memory_mmuRsp_allowWrite, input io_cpu_memory_mmuRsp_allowExecute, @@ -6190,6 +6275,7 @@ module DataCache ( reg stageB_mmuRspFreeze; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; reg stageB_mmuRsp_allowRead; reg stageB_mmuRsp_allowWrite; reg stageB_mmuRsp_allowExecute; @@ -6224,6 +6310,8 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; wire stageB_bypassCache; reg [1:0] _zz_18; reg loader_valid; @@ -6238,6 +6326,7 @@ module DataCache ( wire loader_kill; reg loader_killReg; wire loader_done; + reg loader_valid_regNext; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; @@ -6405,7 +6494,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'h0; + tagsReadCmd_payload = 7'bxxxxxxx; if(_zz_23)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -6419,7 +6508,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'h0; + dataReadCmd_payload = 10'bxxxxxxxxxx; if(_zz_23)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -6449,7 +6538,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; + tagsWriteCmd_payload_address = 7'bxxxxxxx; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -6476,7 +6565,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -6508,7 +6597,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'h0; + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -6518,7 +6607,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'h0; + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end @@ -6665,6 +6754,8 @@ module DataCache ( end end + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); always @ (*) begin io_cpu_redo = 1'b0; if(io_cpu_writeBack_isValid)begin @@ -6681,7 +6772,7 @@ module DataCache ( if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin io_cpu_redo = 1'b1; end - if(loader_valid)begin + if((loader_valid && (! loader_valid_regNext)))begin io_cpu_redo = 1'b1; end end @@ -6691,11 +6782,11 @@ module DataCache ( if(stageB_bypassCache)begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_18) != 2'b00); + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_18) != 2'b00) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; always @ (*) begin @@ -6803,6 +6894,7 @@ module DataCache ( assign loader_kill = 1'b0; assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; always @ (posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; @@ -6834,6 +6926,7 @@ module DataCache ( if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; @@ -6882,6 +6975,7 @@ module DataCache ( if(stageB_flusher_start)begin stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; end + loader_valid_regNext <= loader_valid; end always @ (posedge clk) begin @@ -6914,7 +7008,7 @@ module DataCache ( end `ifndef SYNTHESIS `ifdef FORMAL - assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin $display("FAILURE writeBack stuck by another plugin is not allowed"); @@ -6958,6 +7052,7 @@ module InstructionCache ( output [31:0] io_cpu_fetch_data, input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, input io_cpu_fetch_mmuRsp_allowRead, input io_cpu_fetch_mmuRsp_allowWrite, input io_cpu_fetch_mmuRsp_allowExecute, @@ -7068,6 +7163,7 @@ module InstructionCache ( reg [31:0] io_cpu_fetch_data_regNextWhen; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; reg decodeStage_mmuRsp_allowRead; reg decodeStage_mmuRsp_allowWrite; reg decodeStage_mmuRsp_allowExecute; @@ -7267,9 +7363,9 @@ module InstructionCache ( assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; always @ (posedge clk) begin if(reset) begin @@ -7328,6 +7424,7 @@ module InstructionCache ( if((! io_cpu_decode_isStuck))begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v index b36d5a0..5058753 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v @@ -1,12 +1,19 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:07:17 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 `define ShiftCtrlEnum_defaultEncoding_type [1:0] `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 @@ -14,6 +21,17 @@ `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + `define AluCtrlEnum_defaultEncoding_type [1:0] `define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 `define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 @@ -25,3310 +43,2395 @@ `define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_177; + wire _zz_178; + wire _zz_179; + wire _zz_180; + wire _zz_181; + wire _zz_182; + wire _zz_183; + wire _zz_184; + reg _zz_185; + wire _zz_186; + wire [31:0] _zz_187; + wire _zz_188; + wire [31:0] _zz_189; + reg _zz_190; + wire _zz_191; + wire _zz_192; + wire [31:0] _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + wire _zz_201; + wire [3:0] _zz_202; + wire _zz_203; + wire _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_208; + wire _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + wire _zz_219; + wire _zz_220; + wire _zz_221; + wire _zz_222; + wire _zz_223; + wire _zz_224; + wire [1:0] _zz_225; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire _zz_235; + wire [1:0] _zz_236; + wire _zz_237; + wire _zz_238; + wire [5:0] _zz_239; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire _zz_245; + wire [1:0] _zz_246; + wire _zz_247; + wire [1:0] _zz_248; + wire [51:0] _zz_249; + wire [51:0] _zz_250; + wire [51:0] _zz_251; + wire [32:0] _zz_252; + wire [51:0] _zz_253; + wire [49:0] _zz_254; + wire [51:0] _zz_255; + wire [49:0] _zz_256; + wire [51:0] _zz_257; + wire [32:0] _zz_258; + wire [31:0] _zz_259; + wire [32:0] _zz_260; + wire [0:0] _zz_261; + wire [0:0] _zz_262; + wire [0:0] _zz_263; + wire [0:0] _zz_264; + wire [0:0] _zz_265; + wire [0:0] _zz_266; + wire [0:0] _zz_267; + wire [0:0] _zz_268; + wire [0:0] _zz_269; + wire [0:0] _zz_270; + wire [0:0] _zz_271; + wire [0:0] _zz_272; + wire [0:0] _zz_273; + wire [0:0] _zz_274; + wire [0:0] _zz_275; + wire [0:0] _zz_276; + wire [0:0] _zz_277; + wire [0:0] _zz_278; + wire [3:0] _zz_279; + wire [2:0] _zz_280; + wire [31:0] _zz_281; + wire [11:0] _zz_282; + wire [31:0] _zz_283; + wire [19:0] _zz_284; + wire [11:0] _zz_285; + wire [31:0] _zz_286; + wire [31:0] _zz_287; + wire [19:0] _zz_288; + wire [11:0] _zz_289; + wire [2:0] _zz_290; + wire [2:0] _zz_291; + wire [0:0] _zz_292; + wire [2:0] _zz_293; + wire [4:0] _zz_294; + wire [11:0] _zz_295; + wire [11:0] _zz_296; + wire [31:0] _zz_297; + wire [31:0] _zz_298; + wire [31:0] _zz_299; + wire [31:0] _zz_300; + wire [31:0] _zz_301; + wire [31:0] _zz_302; + wire [31:0] _zz_303; + wire [11:0] _zz_304; + wire [19:0] _zz_305; + wire [11:0] _zz_306; + wire [31:0] _zz_307; + wire [31:0] _zz_308; + wire [31:0] _zz_309; + wire [11:0] _zz_310; + wire [19:0] _zz_311; + wire [11:0] _zz_312; + wire [2:0] _zz_313; + wire [1:0] _zz_314; + wire [1:0] _zz_315; + wire [65:0] _zz_316; + wire [65:0] _zz_317; + wire [31:0] _zz_318; + wire [31:0] _zz_319; + wire [0:0] _zz_320; + wire [5:0] _zz_321; + wire [32:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [32:0] _zz_325; + wire [32:0] _zz_326; + wire [32:0] _zz_327; + wire [32:0] _zz_328; + wire [0:0] _zz_329; + wire [32:0] _zz_330; + wire [0:0] _zz_331; + wire [32:0] _zz_332; + wire [0:0] _zz_333; + wire [31:0] _zz_334; + wire [0:0] _zz_335; + wire [0:0] _zz_336; + wire [0:0] _zz_337; + wire [0:0] _zz_338; + wire [0:0] _zz_339; + wire [0:0] _zz_340; + wire [0:0] _zz_341; + wire [26:0] _zz_342; + wire _zz_343; + wire _zz_344; + wire [1:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; + wire _zz_349; + wire [0:0] _zz_350; + wire [13:0] _zz_351; + wire [31:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; + wire _zz_355; + wire [0:0] _zz_356; + wire [7:0] _zz_357; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire [31:0] _zz_360; + wire _zz_361; + wire [0:0] _zz_362; + wire [1:0] _zz_363; + wire _zz_364; + wire _zz_365; + wire _zz_366; + wire [31:0] _zz_367; + wire [0:0] _zz_368; + wire [0:0] _zz_369; + wire _zz_370; + wire [0:0] _zz_371; + wire [26:0] _zz_372; + wire [31:0] _zz_373; + wire _zz_374; + wire _zz_375; + wire _zz_376; + wire [1:0] _zz_377; + wire [1:0] _zz_378; + wire _zz_379; + wire [0:0] _zz_380; + wire [22:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire [31:0] _zz_384; + wire [31:0] _zz_385; + wire _zz_386; + wire _zz_387; + wire [1:0] _zz_388; + wire [1:0] _zz_389; + wire _zz_390; + wire [0:0] _zz_391; + wire [19:0] _zz_392; + wire [31:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire [31:0] _zz_396; + wire _zz_397; + wire [0:0] _zz_398; + wire [0:0] _zz_399; + wire _zz_400; + wire [0:0] _zz_401; + wire [0:0] _zz_402; + wire _zz_403; + wire [0:0] _zz_404; + wire [16:0] _zz_405; + wire [31:0] _zz_406; + wire [31:0] _zz_407; + wire [31:0] _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire [0:0] _zz_411; + wire [0:0] _zz_412; + wire [0:0] _zz_413; + wire [0:0] _zz_414; + wire _zz_415; + wire [0:0] _zz_416; + wire [13:0] _zz_417; + wire [31:0] _zz_418; + wire [31:0] _zz_419; + wire [31:0] _zz_420; + wire _zz_421; + wire _zz_422; + wire [0:0] _zz_423; + wire [3:0] _zz_424; + wire [0:0] _zz_425; + wire [0:0] _zz_426; + wire _zz_427; + wire [0:0] _zz_428; + wire [10:0] _zz_429; + wire [31:0] _zz_430; + wire [31:0] _zz_431; + wire [31:0] _zz_432; + wire _zz_433; + wire [0:0] _zz_434; + wire [0:0] _zz_435; + wire [31:0] _zz_436; + wire _zz_437; + wire [0:0] _zz_438; + wire [2:0] _zz_439; + wire [0:0] _zz_440; + wire [3:0] _zz_441; + wire [5:0] _zz_442; + wire [5:0] _zz_443; + wire _zz_444; + wire [0:0] _zz_445; + wire [7:0] _zz_446; + wire [31:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire [31:0] _zz_450; + wire [31:0] _zz_451; + wire [31:0] _zz_452; + wire _zz_453; + wire [0:0] _zz_454; + wire [0:0] _zz_455; + wire _zz_456; + wire [0:0] _zz_457; + wire [1:0] _zz_458; + wire [0:0] _zz_459; + wire [3:0] _zz_460; + wire [0:0] _zz_461; + wire [0:0] _zz_462; + wire [1:0] _zz_463; + wire [1:0] _zz_464; + wire _zz_465; + wire [0:0] _zz_466; + wire [5:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; + wire [31:0] _zz_474; + wire [31:0] _zz_475; + wire _zz_476; + wire _zz_477; + wire [31:0] _zz_478; + wire [31:0] _zz_479; + wire _zz_480; + wire [0:0] _zz_481; + wire [1:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire _zz_485; + wire _zz_486; + wire [0:0] _zz_487; + wire [0:0] _zz_488; + wire _zz_489; + wire [0:0] _zz_490; + wire [3:0] _zz_491; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire _zz_497; + wire _zz_498; + wire [31:0] _zz_499; + wire [31:0] _zz_500; + wire [31:0] _zz_501; + wire [31:0] _zz_502; + wire [0:0] _zz_503; + wire [2:0] _zz_504; + wire [0:0] _zz_505; + wire [0:0] _zz_506; + wire _zz_507; + wire [0:0] _zz_508; + wire [1:0] _zz_509; + wire [31:0] _zz_510; + wire [31:0] _zz_511; + wire [31:0] _zz_512; + wire _zz_513; + wire _zz_514; + wire [31:0] _zz_515; + wire _zz_516; + wire [0:0] _zz_517; + wire [0:0] _zz_518; + wire [0:0] _zz_519; + wire [0:0] _zz_520; + wire [1:0] _zz_521; + wire [1:0] _zz_522; + wire [0:0] _zz_523; + wire [0:0] _zz_524; + wire [31:0] _zz_525; + wire [31:0] _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; + wire [31:0] _zz_529; + wire [31:0] _zz_530; + wire _zz_531; + wire _zz_532; + wire _zz_533; + wire [31:0] _zz_534; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_31; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_35; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_36; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; + wire [31:0] _zz_40; + wire _zz_41; + reg _zz_42; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_43; + wire `BranchCtrlEnum_defaultEncoding_type _zz_44; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; + wire `Src2CtrlEnum_defaultEncoding_type _zz_47; + wire `AluCtrlEnum_defaultEncoding_type _zz_48; + wire `Src1CtrlEnum_defaultEncoding_type _zz_49; + reg [31:0] _zz_50; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_52; + reg [31:0] _zz_53; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_54; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_55; + wire [3:0] _zz_56; + wire _zz_57; + wire _zz_58; + wire _zz_59; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_60; + wire _zz_61; + wire _zz_62; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_63; + wire _zz_64; + reg _zz_65; + wire _zz_66; + reg _zz_67; + reg [31:0] _zz_68; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_69; + reg [18:0] _zz_70; + wire _zz_71; + reg [10:0] _zz_72; + wire _zz_73; + reg [18:0] _zz_74; + reg _zz_75; + wire _zz_76; + reg [10:0] _zz_77; + wire _zz_78; + reg [18:0] _zz_79; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_80; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_81; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_82; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_83; + reg [31:0] _zz_84; + wire _zz_85; + reg [31:0] _zz_86; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [32:0] _zz_87; + wire _zz_88; + wire _zz_89; + wire _zz_90; + wire _zz_91; + wire `Src1CtrlEnum_defaultEncoding_type _zz_92; + wire `AluCtrlEnum_defaultEncoding_type _zz_93; + wire `Src2CtrlEnum_defaultEncoding_type _zz_94; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_95; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_96; + wire `BranchCtrlEnum_defaultEncoding_type _zz_97; + wire `EnvCtrlEnum_defaultEncoding_type _zz_98; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_99; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_100; + reg [31:0] _zz_101; + wire _zz_102; + reg [19:0] _zz_103; + wire _zz_104; + reg [19:0] _zz_105; + reg [31:0] _zz_106; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_107; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_108; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_109; + wire _zz_110; + wire _zz_111; + wire _zz_112; + wire _zz_113; + wire _zz_114; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_115; + reg _zz_116; + reg _zz_117; + wire _zz_118; + reg [19:0] _zz_119; + wire _zz_120; + reg [10:0] _zz_121; + wire _zz_122; + reg [18:0] _zz_123; + reg _zz_124; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_125; + reg [19:0] _zz_126; + wire _zz_127; + reg [10:0] _zz_128; + wire _zz_129; + reg [18:0] _zz_130; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_131; + wire _zz_132; + wire _zz_133; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_134; + wire _zz_135; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_136; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_137; + wire _zz_138; + wire _zz_139; + reg [32:0] _zz_140; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_141; + wire [31:0] _zz_142; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_143; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_144; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_145; + reg [31:0] _zz_146; + reg [31:0] _zz_147; + reg [31:0] _zz_148; + reg [31:0] _zz_149; + reg [31:0] _zz_150; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [2:0] _zz_168; + reg _zz_169; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_170; + wire _zz_171; + wire _zz_172; + wire _zz_173; + wire _zz_174; + wire _zz_175; + reg _zz_176; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [23:0] _zz_20_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [63:0] _zz_23_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; + reg [95:0] _zz_26_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_27_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_29_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_30_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_33_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_34_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_36_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_37_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_39_string; + reg [39:0] _zz_43_string; + reg [31:0] _zz_44_string; + reg [71:0] _zz_45_string; + reg [39:0] _zz_46_string; + reg [23:0] _zz_47_string; + reg [63:0] _zz_48_string; + reg [95:0] _zz_49_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_51_string; + reg [95:0] _zz_92_string; + reg [63:0] _zz_93_string; + reg [23:0] _zz_94_string; + reg [39:0] _zz_95_string; + reg [71:0] _zz_96_string; + reg [31:0] _zz_97_string; + reg [39:0] _zz_98_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input [2:0] _zz_10_, - input [31:0] _zz_11_, - input clk, - input reset); - reg [21:0] _zz_12_; - reg [31:0] _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire [0:0] _zz_16_; - wire [0:0] _zz_17_; - wire [21:0] _zz_18_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [6:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_7_; - wire [9:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - reg [31:0] io_cpu_fetch_data_regNextWhen; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_hit_valid; - reg decodeStage_hit_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; - assign _zz_14_ = (! lineLoader_flushCounter[7]); - assign _zz_15_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_16_ = _zz_7_[0 : 0]; - assign _zz_17_ = _zz_7_[1 : 1]; - assign _zz_18_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_18_; - end - end + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_208 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_209 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_210 = 1'b1; + assign _zz_211 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_212 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_213 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_214 = ((_zz_182 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_215 = ((_zz_182 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_216 = ((_zz_182 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_217 = ((_zz_182 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_218 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_219 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_220 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_221 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_222 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_223 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_224 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_225 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_226 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_227 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_228 = (1'b0 || (! 1'b1)); + assign _zz_229 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_230 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_231 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_232 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_233 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_234 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_235 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_236 = execute_INSTRUCTION[13 : 12]; + assign _zz_237 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_238 = (! memory_arbitration_isStuck); + assign _zz_239 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_240 = (iBus_cmd_valid || (_zz_168 != 3'b000)); + assign _zz_241 = (_zz_204 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_242 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_243 = ((_zz_131 && 1'b1) && (! 1'b0)); + assign _zz_244 = ((_zz_132 && 1'b1) && (! 1'b0)); + assign _zz_245 = ((_zz_133 && 1'b1) && (! 1'b0)); + assign _zz_246 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_247 = execute_INSTRUCTION[13]; + assign _zz_248 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_249 = ($signed(_zz_250) + $signed(_zz_255)); + assign _zz_250 = ($signed(_zz_251) + $signed(_zz_253)); + assign _zz_251 = 52'h0; + assign _zz_252 = {1'b0,memory_MUL_LL}; + assign _zz_253 = {{19{_zz_252[32]}}, _zz_252}; + assign _zz_254 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_255 = {{2{_zz_254[49]}}, _zz_254}; + assign _zz_256 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_257 = {{2{_zz_256[49]}}, _zz_256}; + assign _zz_258 = ($signed(_zz_260) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_259 = _zz_258[31 : 0]; + assign _zz_260 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_261 = _zz_87[31 : 31]; + assign _zz_262 = _zz_87[30 : 30]; + assign _zz_263 = _zz_87[29 : 29]; + assign _zz_264 = _zz_87[28 : 28]; + assign _zz_265 = _zz_87[25 : 25]; + assign _zz_266 = _zz_87[17 : 17]; + assign _zz_267 = _zz_87[16 : 16]; + assign _zz_268 = _zz_87[13 : 13]; + assign _zz_269 = _zz_87[12 : 12]; + assign _zz_270 = _zz_87[11 : 11]; + assign _zz_271 = _zz_87[32 : 32]; + assign _zz_272 = _zz_87[15 : 15]; + assign _zz_273 = _zz_87[5 : 5]; + assign _zz_274 = _zz_87[3 : 3]; + assign _zz_275 = _zz_87[20 : 20]; + assign _zz_276 = _zz_87[10 : 10]; + assign _zz_277 = _zz_87[4 : 4]; + assign _zz_278 = _zz_87[0 : 0]; + assign _zz_279 = (_zz_55 - 4'b0001); + assign _zz_280 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_281 = {29'd0, _zz_280}; + assign _zz_282 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_283 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_284 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_285 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_286 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_287 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_288 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_289 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_290 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_291 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_292 = execute_SRC_LESS; + assign _zz_293 = 3'b100; + assign _zz_294 = execute_INSTRUCTION[19 : 15]; + assign _zz_295 = execute_INSTRUCTION[31 : 20]; + assign _zz_296 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_297 = ($signed(_zz_298) + $signed(_zz_301)); + assign _zz_298 = ($signed(_zz_299) + $signed(_zz_300)); + assign _zz_299 = execute_SRC1; + assign _zz_300 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_301 = (execute_SRC_USE_SUB_LESS ? _zz_302 : _zz_303); + assign _zz_302 = 32'h00000001; + assign _zz_303 = 32'h0; + assign _zz_304 = execute_INSTRUCTION[31 : 20]; + assign _zz_305 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_306 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_307 = {_zz_119,execute_INSTRUCTION[31 : 20]}; + assign _zz_308 = {{_zz_121,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_309 = {{_zz_123,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_310 = execute_INSTRUCTION[31 : 20]; + assign _zz_311 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_312 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_313 = 3'b100; + assign _zz_314 = (_zz_134 & (~ _zz_315)); + assign _zz_315 = (_zz_134 - 2'b01); + assign _zz_316 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_317 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_318 = writeBack_MUL_LOW[31 : 0]; + assign _zz_319 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_320 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_321 = {5'd0, _zz_320}; + assign _zz_322 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_323 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_324 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_325 = {_zz_136,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_326 = _zz_327; + assign _zz_327 = _zz_328; + assign _zz_328 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_137) : _zz_137)} + _zz_330); + assign _zz_329 = memory_DivPlugin_div_needRevert; + assign _zz_330 = {32'd0, _zz_329}; + assign _zz_331 = _zz_139; + assign _zz_332 = {32'd0, _zz_331}; + assign _zz_333 = _zz_138; + assign _zz_334 = {31'd0, _zz_333}; + assign _zz_335 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_336 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_337 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_338 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_339 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_340 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_341 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_342 = (iBus_cmd_payload_address >>> 5); + assign _zz_343 = 1'b1; + assign _zz_344 = 1'b1; + assign _zz_345 = {_zz_59,_zz_58}; + assign _zz_346 = 32'h0000107f; + assign _zz_347 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_348 = 32'h00002073; + assign _zz_349 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_350 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_351 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_352) == 32'h00000003),{(_zz_353 == _zz_354),{_zz_355,{_zz_356,_zz_357}}}}}}; + assign _zz_352 = 32'h0000505f; + assign _zz_353 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_354 = 32'h00000063; + assign _zz_355 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_356 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_357 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_358) == 32'h00001013),{(_zz_359 == _zz_360),{_zz_361,{_zz_362,_zz_363}}}}}}; + assign _zz_358 = 32'hfc00307f; + assign _zz_359 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_360 = 32'h00005033; + assign _zz_361 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_362 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_363 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz_364 = decode_INSTRUCTION[31]; + assign _zz_365 = decode_INSTRUCTION[31]; + assign _zz_366 = decode_INSTRUCTION[7]; + assign _zz_367 = 32'h10103050; + assign _zz_368 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_369 = 1'b0; + assign _zz_370 = (((decode_INSTRUCTION & _zz_373) == 32'h02000030) != 1'b0); + assign _zz_371 = ({_zz_374,_zz_375} != 2'b00); + assign _zz_372 = {(_zz_376 != 1'b0),{(_zz_377 != _zz_378),{_zz_379,{_zz_380,_zz_381}}}}; + assign _zz_373 = 32'h02004074; + assign _zz_374 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); + assign _zz_375 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz_376 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz_377 = {(_zz_382 == _zz_383),(_zz_384 == _zz_385)}; + assign _zz_378 = 2'b00; + assign _zz_379 = ({_zz_90,_zz_386} != 2'b00); + assign _zz_380 = (_zz_387 != 1'b0); + assign _zz_381 = {(_zz_388 != _zz_389),{_zz_390,{_zz_391,_zz_392}}}; + assign _zz_382 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_383 = 32'h00001050; + assign _zz_384 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_385 = 32'h00002050; + assign _zz_386 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_387 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_388 = {(_zz_393 == _zz_394),(_zz_395 == _zz_396)}; + assign _zz_389 = 2'b00; + assign _zz_390 = ({_zz_397,{_zz_398,_zz_399}} != 3'b000); + assign _zz_391 = (_zz_400 != 1'b0); + assign _zz_392 = {(_zz_401 != _zz_402),{_zz_403,{_zz_404,_zz_405}}}; + assign _zz_393 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_394 = 32'h00005010; + assign _zz_395 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_396 = 32'h00005020; + assign _zz_397 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_398 = ((decode_INSTRUCTION & _zz_406) == 32'h00001010); + assign _zz_399 = ((decode_INSTRUCTION & _zz_407) == 32'h00001010); + assign _zz_400 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_401 = ((decode_INSTRUCTION & _zz_408) == 32'h00001000); + assign _zz_402 = 1'b0; + assign _zz_403 = ((_zz_409 == _zz_410) != 1'b0); + assign _zz_404 = ({_zz_411,_zz_412} != 2'b00); + assign _zz_405 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; + assign _zz_406 = 32'h00007034; + assign _zz_407 = 32'h02007054; + assign _zz_408 = 32'h00001000; + assign _zz_409 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_410 = 32'h00002000; + assign _zz_411 = ((decode_INSTRUCTION & _zz_418) == 32'h00002000); + assign _zz_412 = ((decode_INSTRUCTION & _zz_419) == 32'h00001000); + assign _zz_413 = ((decode_INSTRUCTION & _zz_420) == 32'h00004008); + assign _zz_414 = 1'b0; + assign _zz_415 = ({_zz_421,_zz_422} != 2'b00); + assign _zz_416 = ({_zz_423,_zz_424} != 5'h0); + assign _zz_417 = {(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}; + assign _zz_418 = 32'h00002010; + assign _zz_419 = 32'h00005000; + assign _zz_420 = 32'h00004048; + assign _zz_421 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_422 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h00002040); + assign _zz_424 = {(_zz_431 == _zz_432),{_zz_433,{_zz_434,_zz_435}}}; + assign _zz_425 = ((decode_INSTRUCTION & _zz_436) == 32'h00000020); + assign _zz_426 = 1'b0; + assign _zz_427 = ({_zz_437,{_zz_438,_zz_439}} != 5'h0); + assign _zz_428 = ({_zz_440,_zz_441} != 5'h0); + assign _zz_429 = {(_zz_442 != _zz_443),{_zz_444,{_zz_445,_zz_446}}}; + assign _zz_430 = 32'h00002040; + assign _zz_431 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_432 = 32'h00001040; + assign _zz_433 = ((decode_INSTRUCTION & _zz_447) == 32'h00000040); + assign _zz_434 = (_zz_448 == _zz_449); + assign _zz_435 = (_zz_450 == _zz_451); + assign _zz_436 = 32'h00000020; + assign _zz_437 = ((decode_INSTRUCTION & _zz_452) == 32'h00000040); + assign _zz_438 = _zz_89; + assign _zz_439 = {_zz_453,{_zz_454,_zz_455}}; + assign _zz_440 = _zz_89; + assign _zz_441 = {_zz_456,{_zz_457,_zz_458}}; + assign _zz_442 = {_zz_90,{_zz_459,_zz_460}}; + assign _zz_443 = 6'h0; + assign _zz_444 = ({_zz_461,_zz_462} != 2'b00); + assign _zz_445 = (_zz_463 != _zz_464); + assign _zz_446 = {_zz_465,{_zz_466,_zz_467}}; + assign _zz_447 = 32'h00100040; + assign _zz_448 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_449 = 32'h00000040; + assign _zz_450 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_451 = 32'h0; + assign _zz_452 = 32'h00000040; + assign _zz_453 = ((decode_INSTRUCTION & _zz_468) == 32'h00004020); + assign _zz_454 = (_zz_469 == _zz_470); + assign _zz_455 = (_zz_471 == _zz_472); + assign _zz_456 = ((decode_INSTRUCTION & _zz_473) == 32'h00002010); + assign _zz_457 = (_zz_474 == _zz_475); + assign _zz_458 = {_zz_476,_zz_477}; + assign _zz_459 = (_zz_478 == _zz_479); + assign _zz_460 = {_zz_480,{_zz_481,_zz_482}}; + assign _zz_461 = _zz_89; + assign _zz_462 = (_zz_483 == _zz_484); + assign _zz_463 = {_zz_89,_zz_485}; + assign _zz_464 = 2'b00; + assign _zz_465 = (_zz_486 != 1'b0); + assign _zz_466 = (_zz_487 != _zz_488); + assign _zz_467 = {_zz_489,{_zz_490,_zz_491}}; + assign _zz_468 = 32'h00004020; + assign _zz_469 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_470 = 32'h00000010; + assign _zz_471 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_472 = 32'h00000020; + assign _zz_473 = 32'h00002030; + assign _zz_474 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_475 = 32'h00000010; + assign _zz_476 = ((decode_INSTRUCTION & _zz_492) == 32'h00002020); + assign _zz_477 = ((decode_INSTRUCTION & _zz_493) == 32'h00000020); + assign _zz_478 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_479 = 32'h00001010; + assign _zz_480 = ((decode_INSTRUCTION & _zz_494) == 32'h00002010); + assign _zz_481 = (_zz_495 == _zz_496); + assign _zz_482 = {_zz_497,_zz_498}; + assign _zz_483 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_484 = 32'h00000020; + assign _zz_485 = ((decode_INSTRUCTION & _zz_499) == 32'h0); + assign _zz_486 = ((decode_INSTRUCTION & _zz_500) == 32'h00004010); + assign _zz_487 = (_zz_501 == _zz_502); + assign _zz_488 = 1'b0; + assign _zz_489 = ({_zz_503,_zz_504} != 4'b0000); + assign _zz_490 = (_zz_505 != _zz_506); + assign _zz_491 = {_zz_507,{_zz_508,_zz_509}}; + assign _zz_492 = 32'h02002060; + assign _zz_493 = 32'h02003020; + assign _zz_494 = 32'h00002010; + assign _zz_495 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_496 = 32'h00000010; + assign _zz_497 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_498 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_499 = 32'h00000020; + assign _zz_500 = 32'h00004014; + assign _zz_501 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_502 = 32'h00002010; + assign _zz_503 = ((decode_INSTRUCTION & _zz_510) == 32'h0); + assign _zz_504 = {(_zz_511 == _zz_512),{_zz_513,_zz_514}}; + assign _zz_505 = ((decode_INSTRUCTION & _zz_515) == 32'h0); + assign _zz_506 = 1'b0; + assign _zz_507 = ({_zz_516,{_zz_517,_zz_518}} != 3'b000); + assign _zz_508 = ({_zz_519,_zz_520} != 2'b00); + assign _zz_509 = {(_zz_521 != _zz_522),(_zz_523 != _zz_524)}; + assign _zz_510 = 32'h00000044; + assign _zz_511 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_512 = 32'h0; + assign _zz_513 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_514 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_515 = 32'h00000058; + assign _zz_516 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_517 = ((decode_INSTRUCTION & _zz_525) == 32'h00002010); + assign _zz_518 = ((decode_INSTRUCTION & _zz_526) == 32'h40000030); + assign _zz_519 = ((decode_INSTRUCTION & _zz_527) == 32'h00000004); + assign _zz_520 = _zz_88; + assign _zz_521 = {(_zz_528 == _zz_529),_zz_88}; + assign _zz_522 = 2'b00; + assign _zz_523 = ((decode_INSTRUCTION & _zz_530) == 32'h00001008); + assign _zz_524 = 1'b0; + assign _zz_525 = 32'h00002014; + assign _zz_526 = 32'h40000034; + assign _zz_527 = 32'h00000014; + assign _zz_528 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_529 = 32'h00000004; + assign _zz_530 = 32'h00005048; + assign _zz_531 = execute_INSTRUCTION[31]; + assign _zz_532 = execute_INSTRUCTION[31]; + assign _zz_533 = execute_INSTRUCTION[7]; + assign _zz_534 = 32'h0; always @ (posedge clk) begin - if(_zz_6_) begin - _zz_12_ <= ways_0_tags[_zz_5_]; + if(_zz_343) begin + _zz_205 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + if(_zz_344) begin + _zz_206 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_9_) begin - _zz_13_ <= ways_0_datas[_zz_8_]; - end - end - - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; - end - end - - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; - end - end - - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; - end - end - end - - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_14_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; + if(_zz_42) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_12_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_16_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_17_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_13_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; - end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; - end - if(_zz_15_)begin - lineLoader_flushPending <= 1'b0; + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_177 ), //i + .io_cpu_prefetch_isValid (_zz_178 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_179 ), //i + .io_cpu_fetch_isStuck (_zz_180 ), //i + .io_cpu_fetch_isRemoved (_zz_181 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_182 ), //i + .io_cpu_decode_isStuck (_zz_183 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_184 ), //i + .io_cpu_fill_valid (_zz_185 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_9 (_zz_144[2:0] ), //i + ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_186 ), //i + .io_cpu_execute_address (_zz_187[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_82[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_188 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_189[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_190 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_191 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_192 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_193[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_194 ), //i + .io_cpu_writeBack_fence_SR (_zz_195 ), //i + .io_cpu_writeBack_fence_SO (_zz_196 ), //i + .io_cpu_writeBack_fence_SI (_zz_197 ), //i + .io_cpu_writeBack_fence_PW (_zz_198 ), //i + .io_cpu_writeBack_fence_PR (_zz_199 ), //i + .io_cpu_writeBack_fence_PO (_zz_200 ), //i + .io_cpu_writeBack_fence_PI (_zz_201 ), //i + .io_cpu_writeBack_fence_FM (_zz_202[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_203 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_204 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_345) + 2'b00 : begin + _zz_207 = DBusCachedPlugin_redoBranch_payload; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; + 2'b01 : begin + _zz_207 = CsrPlugin_jumpInterface_payload; end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; + 2'b10 : begin + _zz_207 = BranchPlugin_jumpInterface_payload; end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end + default : begin + _zz_207 = IBusCachedPlugin_predictionJumpInterface_payload; end - end + endcase end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_14_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); - end - _zz_3_ <= lineLoader_flushCounter[7]; - if(_zz_15_)begin - lineLoader_flushCounter <= (8'b00000000); - end - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_error <= fetchStage_hit_error; - end - if((_zz_10_ != (3'b000)))begin - io_cpu_fetch_data_regNextWhen <= _zz_11_; - end + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; + endcase end - -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, - input [1:0] io_cpu_execute_args_size, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - input io_cpu_memory_isRemoved, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - output io_cpu_memory_mmuBus_cmd_isValid, - output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, - output io_cpu_memory_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, - input io_cpu_memory_mmuBus_rsp_isIoAccess, - input io_cpu_memory_mmuBus_rsp_allowRead, - input io_cpu_memory_mmuBus_rsp_allowWrite, - input io_cpu_memory_mmuBus_rsp_allowExecute, - input io_cpu_memory_mmuBus_rsp_exception, - input io_cpu_memory_mmuBus_rsp_refilling, - output io_cpu_memory_mmuBus_end, - input io_cpu_memory_mmuBus_busy, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output reg io_cpu_flush_ready, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, - output reg io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire _zz_16_; - wire _zz_17_; - wire [0:0] _zz_18_; - wire [0:0] _zz_19_; - wire [0:0] _zz_20_; - wire [2:0] _zz_21_; - wire [1:0] _zz_22_; - wire [21:0] _zz_23_; - reg _zz_1_; - reg _zz_2_; - wire haltCpu; - reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3_; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4_; - wire _zz_5_; - wire [31:0] ways_0_dataReadRsp; - reg [3:0] _zz_6_; - wire [3:0] stage0_mask; - wire [0:0] stage0_colisions; - reg stageA_request_wr; - reg [31:0] stageA_request_data; - reg [1:0] stageA_request_size; - reg [3:0] stageA_mask; - wire stageA_wayHits_0; - reg [0:0] stage0_colisions_regNextWhen; - wire [0:0] _zz_7_; - wire [0:0] stageA_colisions; - reg stageB_request_wr; - reg [31:0] stageB_request_data; - reg [1:0] stageB_request_size; - reg stageB_mmuRspFreeze; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg [31:0] stageB_dataReadRsp_0; - wire [0:0] _zz_8_; - reg [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - reg [3:0] stageB_mask; - reg [0:0] stageB_colisions; - reg stageB_loaderValid; - reg stageB_flusher_valid; - wire [31:0] stageB_requestDataBypass; - wire stageB_isAmo; - reg stageB_memCmdSent; - wire [0:0] _zz_9_; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [2:0] loader_counter_valueNext; - reg [2:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_24_; - reg [7:0] _zz_25_; - reg [7:0] _zz_26_; - reg [7:0] _zz_27_; - assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); - assign _zz_15_ = (loader_valid && io_mem_rsp_valid); - assign _zz_16_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - assign _zz_17_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign _zz_18_ = _zz_4_[0 : 0]; - assign _zz_19_ = _zz_4_[1 : 1]; - assign _zz_20_ = loader_counter_willIncrement; - assign _zz_21_ = {2'd0, _zz_20_}; - assign _zz_22_ = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_23_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_23_; - end + always @(*) begin + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_3_) begin - _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; - end + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase end - - always @ (*) begin - _zz_11_ = {_zz_27_, _zz_26_, _zz_25_, _zz_24_}; + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase end - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1_) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1_) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1_) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1_) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_5_) begin - _zz_24_ <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_25_ <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_26_ <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_27_ <= ways_0_data_symbol3[dataReadCmd_payload]; - end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase end - - always @ (*) begin - _zz_1_ = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_1_ = 1'b1; - end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase end - - always @ (*) begin - _zz_2_ = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_2_ = 1'b1; - end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase end - - assign haltCpu = 1'b0; - assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4_ = _zz_10_; - assign ways_0_tagsReadRsp_valid = _zz_18_[0]; - assign ways_0_tagsReadRsp_error = _zz_19_[0]; - assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; - assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRsp = _zz_11_; - always @ (*) begin - tagsReadCmd_valid = 1'b0; - if(_zz_12_)begin - tagsReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; + endcase end - - always @ (*) begin - tagsReadCmd_payload = (7'bxxxxxxx); - if(_zz_12_)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; - end + always @(*) begin + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_valid = 1'b0; - if(_zz_12_)begin - dataReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; + endcase end - - always @ (*) begin - dataReadCmd_payload = (10'bxxxxxxxxxx); - if(_zz_12_)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; - end - if(_zz_13_)begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_valid = 1'b1; - end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_way = (1'bx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = (1'b1); - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_address = (7'bxxxxxxx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_valid = 1'b1; - end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); - end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end + always @(*) begin + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((stageB_request_wr && stageB_waysHit))begin - dataWriteCmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - dataWriteCmd_valid = 1'b0; - end - if(_zz_15_)begin - dataWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_way = (1'bx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_way = stageB_waysHits; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_address = (10'bxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; - end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_data = stageB_requestDataBypass; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end + always @(*) begin + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_mask = (4'bxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_mask = stageB_mask; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_mask = (4'b1111); - end + always @(*) begin + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; + endcase end - - always @ (*) begin - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_6_ = (4'b0001); - end - 2'b01 : begin - _zz_6_ = (4'b0011); - end - default : begin - _zz_6_ = (4'b1111); - end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; endcase end - - assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); - assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; - assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; - assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); - always @ (*) begin - stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin - stageB_mmuRspFreeze = 1'b1; - end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase end - - assign _zz_8_[0] = stageA_wayHits_0; - assign stageB_waysHit = (stageB_waysHits != (1'b0)); - assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - if(io_mem_cmd_ready)begin - stageB_loaderValid = 1'b1; - end - end - end - end - if(_zz_13_)begin - stageB_loaderValid = 1'b0; - end + always @(*) begin + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(_zz_14_)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - if(_zz_13_)begin - io_cpu_writeBack_haltIt = 1'b0; - end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(_zz_16_)begin - io_cpu_flush_ready = 1'b1; - end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase end - - assign stageB_requestDataBypass = stageB_request_data; - assign stageB_isAmo = 1'b0; - always @ (*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin - io_cpu_redo = 1'b1; - end - end - end - end - if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin - io_cpu_redo = 1'b1; - end - if(loader_valid)begin - io_cpu_redo = 1'b1; - end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); - end + always @(*) begin + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; + endcase end - - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_valid = (! stageB_memCmdSent); - end else begin - if(_zz_14_)begin - if(stageB_request_wr)begin - io_mem_cmd_valid = 1'b1; - end - end else begin - if((! stageB_memCmdSent))begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - io_mem_cmd_valid = 1'b0; - end + always @(*) begin + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; - end - end - end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_length = (3'bxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - io_mem_cmd_payload_length = (3'b111); - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_last = 1'bx; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - io_mem_cmd_payload_last = 1'b1; - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - always @ (*) begin - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_data = io_mem_rsp_payload_data; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - end - - assign _zz_9_[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin - loader_counter_willIncrement = 1'b0; - if(_zz_15_)begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_21_); - if(loader_counter_willClear)begin - loader_counter_valueNext = (3'b000); - end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase end - - always @ (posedge clk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; - stageA_request_size <= io_cpu_execute_args_size; - end - if((! io_cpu_memory_isStuck))begin - stageA_mask <= stage0_mask; - end - if((! io_cpu_memory_isStuck))begin - stage0_colisions_regNextWhen <= stage0_colisions; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; - stageB_request_size <= stageA_request_size; - end - if(_zz_17_)begin - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_waysHits <= _zz_8_; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_mask <= stageA_mask; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_colisions <= stageA_colisions; - end - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); - end + always @(*) begin + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(reset) begin - stageB_flusher_valid <= 1'b1; - stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); - stageB_memCmdSent <= 1'b0; - loader_valid <= 1'b0; - loader_counter_value <= (3'b000); - loader_waysAllocator <= (1'b1); - loader_error <= 1'b0; - end else begin - if(_zz_17_)begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; - end - if(stageB_flusher_valid)begin - if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); - end else begin - stageB_flusher_valid <= 1'b0; - end - end - if(_zz_16_)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); - stageB_flusher_valid <= 1'b1; - end - if(io_mem_cmd_ready)begin - stageB_memCmdSent <= 1'b1; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_memCmdSent <= 1'b0; - end - if(stageB_loaderValid)begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(_zz_15_)begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_counter_willOverflow)begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - end - if((! loader_valid))begin - loader_waysAllocator <= _zz_22_[0:0]; - end - end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase end - -endmodule - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset, - input debugReset); - wire _zz_226_; - wire _zz_227_; - wire _zz_228_; - wire _zz_229_; - wire [31:0] _zz_230_; - wire _zz_231_; - wire _zz_232_; - wire _zz_233_; - reg _zz_234_; - wire _zz_235_; - wire [31:0] _zz_236_; - wire _zz_237_; - wire [31:0] _zz_238_; - reg _zz_239_; - wire _zz_240_; - wire _zz_241_; - wire [31:0] _zz_242_; - wire _zz_243_; - wire _zz_244_; - reg [31:0] _zz_245_; - reg [31:0] _zz_246_; - reg [31:0] _zz_247_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1__io_cpu_memory_isWrite; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; - wire dataCache_1__io_cpu_memory_mmuBus_end; - wire dataCache_1__io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1__io_cpu_writeBack_data; - wire dataCache_1__io_cpu_writeBack_mmuException; - wire dataCache_1__io_cpu_writeBack_unalignedAccess; - wire dataCache_1__io_cpu_writeBack_accessError; - wire dataCache_1__io_cpu_writeBack_isWrite; - wire dataCache_1__io_cpu_flush_ready; - wire dataCache_1__io_cpu_redo; - wire dataCache_1__io_mem_cmd_valid; - wire dataCache_1__io_mem_cmd_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_payload_length; - wire dataCache_1__io_mem_cmd_payload_last; - wire _zz_248_; - wire _zz_249_; - wire _zz_250_; - wire _zz_251_; - wire _zz_252_; - wire _zz_253_; - wire _zz_254_; - wire _zz_255_; - wire _zz_256_; - wire _zz_257_; - wire _zz_258_; - wire _zz_259_; - wire _zz_260_; - wire _zz_261_; - wire _zz_262_; - wire _zz_263_; - wire _zz_264_; - wire _zz_265_; - wire [1:0] _zz_266_; - wire _zz_267_; - wire _zz_268_; - wire _zz_269_; - wire _zz_270_; - wire _zz_271_; - wire _zz_272_; - wire _zz_273_; - wire _zz_274_; - wire _zz_275_; - wire _zz_276_; - wire [1:0] _zz_277_; - wire _zz_278_; - wire [5:0] _zz_279_; - wire _zz_280_; - wire _zz_281_; - wire _zz_282_; - wire _zz_283_; - wire _zz_284_; - wire _zz_285_; - wire [1:0] _zz_286_; - wire _zz_287_; - wire [1:0] _zz_288_; - wire [4:0] _zz_289_; - wire [2:0] _zz_290_; - wire [31:0] _zz_291_; - wire [11:0] _zz_292_; - wire [31:0] _zz_293_; - wire [19:0] _zz_294_; - wire [11:0] _zz_295_; - wire [31:0] _zz_296_; - wire [31:0] _zz_297_; - wire [19:0] _zz_298_; - wire [11:0] _zz_299_; - wire [2:0] _zz_300_; - wire [2:0] _zz_301_; - wire [0:0] _zz_302_; - wire [0:0] _zz_303_; - wire [0:0] _zz_304_; - wire [0:0] _zz_305_; - wire [0:0] _zz_306_; - wire [0:0] _zz_307_; - wire [0:0] _zz_308_; - wire [0:0] _zz_309_; - wire [0:0] _zz_310_; - wire [0:0] _zz_311_; - wire [0:0] _zz_312_; - wire [0:0] _zz_313_; - wire [0:0] _zz_314_; - wire [0:0] _zz_315_; - wire [0:0] _zz_316_; - wire [0:0] _zz_317_; - wire [0:0] _zz_318_; - wire [0:0] _zz_319_; - wire [0:0] _zz_320_; - wire [2:0] _zz_321_; - wire [4:0] _zz_322_; - wire [11:0] _zz_323_; - wire [11:0] _zz_324_; - wire [31:0] _zz_325_; - wire [31:0] _zz_326_; - wire [31:0] _zz_327_; - wire [31:0] _zz_328_; - wire [31:0] _zz_329_; - wire [31:0] _zz_330_; - wire [31:0] _zz_331_; - wire [32:0] _zz_332_; - wire [31:0] _zz_333_; - wire [32:0] _zz_334_; - wire [11:0] _zz_335_; - wire [19:0] _zz_336_; - wire [11:0] _zz_337_; - wire [31:0] _zz_338_; - wire [31:0] _zz_339_; - wire [31:0] _zz_340_; - wire [11:0] _zz_341_; - wire [19:0] _zz_342_; - wire [11:0] _zz_343_; - wire [2:0] _zz_344_; - wire [1:0] _zz_345_; - wire [1:0] _zz_346_; - wire [51:0] _zz_347_; - wire [51:0] _zz_348_; - wire [51:0] _zz_349_; - wire [32:0] _zz_350_; - wire [51:0] _zz_351_; - wire [49:0] _zz_352_; - wire [51:0] _zz_353_; - wire [49:0] _zz_354_; - wire [51:0] _zz_355_; - wire [65:0] _zz_356_; - wire [65:0] _zz_357_; - wire [31:0] _zz_358_; - wire [31:0] _zz_359_; - wire [0:0] _zz_360_; - wire [5:0] _zz_361_; - wire [32:0] _zz_362_; - wire [32:0] _zz_363_; - wire [31:0] _zz_364_; - wire [31:0] _zz_365_; - wire [32:0] _zz_366_; - wire [32:0] _zz_367_; - wire [32:0] _zz_368_; - wire [0:0] _zz_369_; - wire [32:0] _zz_370_; - wire [0:0] _zz_371_; - wire [32:0] _zz_372_; - wire [0:0] _zz_373_; - wire [31:0] _zz_374_; - wire [0:0] _zz_375_; - wire [0:0] _zz_376_; - wire [0:0] _zz_377_; - wire [0:0] _zz_378_; - wire [0:0] _zz_379_; - wire [0:0] _zz_380_; - wire [0:0] _zz_381_; - wire [26:0] _zz_382_; - wire _zz_383_; - wire _zz_384_; - wire [2:0] _zz_385_; - wire _zz_386_; - wire _zz_387_; - wire _zz_388_; - wire [31:0] _zz_389_; - wire _zz_390_; - wire [0:0] _zz_391_; - wire [2:0] _zz_392_; - wire _zz_393_; - wire [0:0] _zz_394_; - wire [0:0] _zz_395_; - wire _zz_396_; - wire [0:0] _zz_397_; - wire [26:0] _zz_398_; - wire [31:0] _zz_399_; - wire [31:0] _zz_400_; - wire [31:0] _zz_401_; - wire _zz_402_; - wire _zz_403_; - wire [31:0] _zz_404_; - wire [0:0] _zz_405_; - wire [3:0] _zz_406_; - wire [0:0] _zz_407_; - wire [0:0] _zz_408_; - wire [2:0] _zz_409_; - wire [2:0] _zz_410_; - wire _zz_411_; - wire [0:0] _zz_412_; - wire [23:0] _zz_413_; - wire [31:0] _zz_414_; - wire [31:0] _zz_415_; - wire [31:0] _zz_416_; - wire [31:0] _zz_417_; - wire _zz_418_; - wire [0:0] _zz_419_; - wire [1:0] _zz_420_; - wire [31:0] _zz_421_; - wire [31:0] _zz_422_; - wire [31:0] _zz_423_; - wire [31:0] _zz_424_; - wire _zz_425_; - wire [0:0] _zz_426_; - wire [0:0] _zz_427_; - wire [0:0] _zz_428_; - wire [3:0] _zz_429_; - wire [1:0] _zz_430_; - wire [1:0] _zz_431_; - wire _zz_432_; - wire [0:0] _zz_433_; - wire [21:0] _zz_434_; - wire [31:0] _zz_435_; - wire [31:0] _zz_436_; - wire [31:0] _zz_437_; - wire _zz_438_; - wire _zz_439_; - wire [31:0] _zz_440_; - wire [31:0] _zz_441_; - wire [31:0] _zz_442_; - wire [31:0] _zz_443_; - wire [31:0] _zz_444_; - wire [31:0] _zz_445_; - wire [31:0] _zz_446_; - wire [0:0] _zz_447_; - wire [1:0] _zz_448_; - wire _zz_449_; - wire [0:0] _zz_450_; - wire [0:0] _zz_451_; - wire [0:0] _zz_452_; - wire [0:0] _zz_453_; - wire _zz_454_; - wire [0:0] _zz_455_; - wire [19:0] _zz_456_; - wire [31:0] _zz_457_; - wire [31:0] _zz_458_; - wire [31:0] _zz_459_; - wire [31:0] _zz_460_; - wire _zz_461_; - wire _zz_462_; - wire [31:0] _zz_463_; - wire [31:0] _zz_464_; - wire [31:0] _zz_465_; - wire [31:0] _zz_466_; - wire [31:0] _zz_467_; - wire _zz_468_; - wire [3:0] _zz_469_; - wire [3:0] _zz_470_; - wire _zz_471_; - wire [0:0] _zz_472_; - wire [17:0] _zz_473_; - wire [31:0] _zz_474_; - wire [31:0] _zz_475_; - wire _zz_476_; - wire [0:0] _zz_477_; - wire [0:0] _zz_478_; - wire _zz_479_; - wire [0:0] _zz_480_; - wire [0:0] _zz_481_; - wire _zz_482_; - wire [0:0] _zz_483_; - wire [0:0] _zz_484_; - wire _zz_485_; - wire [0:0] _zz_486_; - wire [14:0] _zz_487_; - wire [31:0] _zz_488_; - wire [31:0] _zz_489_; - wire [31:0] _zz_490_; - wire [31:0] _zz_491_; - wire [31:0] _zz_492_; - wire [31:0] _zz_493_; - wire [31:0] _zz_494_; - wire [31:0] _zz_495_; - wire [31:0] _zz_496_; - wire [31:0] _zz_497_; - wire [31:0] _zz_498_; - wire [31:0] _zz_499_; - wire [31:0] _zz_500_; - wire [0:0] _zz_501_; - wire [0:0] _zz_502_; - wire [4:0] _zz_503_; - wire [4:0] _zz_504_; - wire _zz_505_; - wire [0:0] _zz_506_; - wire [12:0] _zz_507_; - wire [31:0] _zz_508_; - wire [31:0] _zz_509_; - wire _zz_510_; - wire [0:0] _zz_511_; - wire [1:0] _zz_512_; - wire [31:0] _zz_513_; - wire [31:0] _zz_514_; - wire _zz_515_; - wire [0:0] _zz_516_; - wire [0:0] _zz_517_; - wire _zz_518_; - wire [0:0] _zz_519_; - wire [9:0] _zz_520_; - wire [31:0] _zz_521_; - wire [31:0] _zz_522_; - wire [31:0] _zz_523_; - wire [31:0] _zz_524_; - wire [31:0] _zz_525_; - wire [31:0] _zz_526_; - wire [31:0] _zz_527_; - wire [31:0] _zz_528_; - wire [1:0] _zz_529_; - wire [1:0] _zz_530_; - wire _zz_531_; - wire [0:0] _zz_532_; - wire [6:0] _zz_533_; - wire [31:0] _zz_534_; - wire [31:0] _zz_535_; - wire [31:0] _zz_536_; - wire _zz_537_; - wire _zz_538_; - wire [1:0] _zz_539_; - wire [1:0] _zz_540_; - wire _zz_541_; - wire [0:0] _zz_542_; - wire [2:0] _zz_543_; - wire [31:0] _zz_544_; - wire [31:0] _zz_545_; - wire _zz_546_; - wire [0:0] _zz_547_; - wire [0:0] _zz_548_; - wire [0:0] _zz_549_; - wire [0:0] _zz_550_; - wire _zz_551_; - wire _zz_552_; - wire [31:0] _zz_553_; - wire [31:0] _zz_554_; - wire [31:0] _zz_555_; - wire _zz_556_; - wire [0:0] _zz_557_; - wire [13:0] _zz_558_; - wire [31:0] _zz_559_; - wire [31:0] _zz_560_; - wire [31:0] _zz_561_; - wire _zz_562_; - wire [0:0] _zz_563_; - wire [7:0] _zz_564_; - wire [31:0] _zz_565_; - wire [31:0] _zz_566_; - wire [31:0] _zz_567_; - wire _zz_568_; - wire [0:0] _zz_569_; - wire [1:0] _zz_570_; - wire _zz_571_; - wire _zz_572_; - wire _zz_573_; - wire [31:0] execute_SHIFT_RIGHT; - wire [31:0] execute_BRANCH_CALC; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_1_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_2_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_3_; - wire decode_IS_CSR; - wire decode_CSR_WRITE_OPCODE; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire decode_SRC_LESS_UNSIGNED; - wire memory_IS_MUL; - wire execute_IS_MUL; - wire decode_IS_MUL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_4_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_5_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_6_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_7_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_8_; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_9_; - wire `AluCtrlEnum_defaultEncoding_type _zz_10_; - wire `AluCtrlEnum_defaultEncoding_type _zz_11_; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_12_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_13_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_14_; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_15_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_16_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_17_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_18_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_19_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_20_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_21_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_22_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_23_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_24_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_25_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; - wire decode_IS_DIV; - wire [31:0] execute_MUL_LL; - wire [51:0] memory_MUL_LOW; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire execute_BRANCH_DO; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire [33:0] execute_MUL_HL; - wire decode_CSR_READ_OPCODE; - wire [33:0] execute_MUL_LH; - wire decode_MEMORY_MANAGMENT; - wire [31:0] memory_PC; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire decode_IS_RS2_SIGNED; - wire decode_IS_RS1_SIGNED; - wire decode_SRC2_FORCE_ZERO; - wire decode_DO_EBREAK; - wire decode_PREDICTION_HAD_BRANCHED2; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; - wire _zz_27_; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire [51:0] _zz_28_; - wire [33:0] _zz_29_; - wire [33:0] _zz_30_; - wire [33:0] _zz_31_; - wire [31:0] _zz_32_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34_; - wire _zz_35_; - wire _zz_36_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_37_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_38_; - wire [31:0] execute_PC; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_39_; - wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_40_; - wire _zz_41_; - wire _zz_42_; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_43_; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_44_; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45_; - wire [31:0] _zz_46_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_47_; - wire _zz_48_; - wire [31:0] _zz_49_; - wire [31:0] _zz_50_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_51_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_52_; - wire [31:0] _zz_53_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_54_; - wire [31:0] _zz_55_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_56_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_57_; - wire [31:0] _zz_58_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_59_; - wire [31:0] _zz_60_; - wire _zz_61_; - reg _zz_62_; - wire [31:0] _zz_63_; - wire [31:0] _zz_64_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_65_; - wire `AluCtrlEnum_defaultEncoding_type _zz_66_; - wire _zz_67_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_68_; - wire _zz_69_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_70_; - wire _zz_71_; - wire _zz_72_; - wire _zz_73_; - wire _zz_74_; - wire _zz_75_; - wire _zz_76_; - wire _zz_77_; - wire _zz_78_; - wire _zz_79_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_80_; - wire _zz_81_; - wire _zz_82_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_83_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_84_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_85_; - wire _zz_86_; - wire _zz_87_; - wire _zz_88_; - wire _zz_89_; - wire _zz_90_; - reg [31:0] _zz_91_; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_ENABLE; - wire [1:0] _zz_92_; - wire execute_MEMORY_MANAGMENT; - wire [31:0] execute_RS2; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_93_; - reg _zz_94_; - reg _zz_95_; - wire [31:0] _zz_96_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_97_; - wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_98_; - reg [31:0] _zz_99_; - wire [31:0] decode_PC; - wire [31:0] _zz_100_; - wire [31:0] _zz_101_; - wire [31:0] _zz_102_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_predictionJumpInterface_valid; - (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; - reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; - wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire DBusCachedPlugin_mmuBus_rsp_allowRead; - wire DBusCachedPlugin_mmuBus_rsp_allowWrite; - wire DBusCachedPlugin_mmuBus_rsp_allowExecute; - wire DBusCachedPlugin_mmuBus_rsp_exception; - wire DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_103_; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; - reg IBusCachedPlugin_injectionPort_valid; - reg IBusCachedPlugin_injectionPort_ready; - wire [31:0] IBusCachedPlugin_injectionPort_payload; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_104_; - wire [4:0] _zz_105_; - wire _zz_106_; - wire _zz_107_; - wire _zz_108_; - wire _zz_109_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_110_; - wire _zz_111_; - wire _zz_112_; - wire _zz_113_; - wire _zz_114_; - reg _zz_115_; - wire _zz_116_; - reg _zz_117_; - reg [31:0] _zz_118_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_decodeInput_valid; - wire IBusCachedPlugin_iBusRsp_decodeInput_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - reg IBusCachedPlugin_injector_decodeRemoved; - wire _zz_119_; - reg [18:0] _zz_120_; - wire _zz_121_; - reg [10:0] _zz_122_; - wire _zz_123_; - reg [18:0] _zz_124_; - reg _zz_125_; - wire _zz_126_; - reg [10:0] _zz_127_; - wire _zz_128_; - reg [18:0] _zz_129_; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_130_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; - wire dBus_cmd_payload_last; - wire dBus_rsp_valid; - wire [31:0] dBus_rsp_payload_data; - wire dBus_rsp_payload_error; - wire dataCache_1__io_mem_cmd_s2mPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; - reg _zz_131_; - reg _zz_132_; - reg [31:0] _zz_133_; - reg [31:0] _zz_134_; - reg [3:0] _zz_135_; - reg [2:0] _zz_136_; - reg _zz_137_; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg _zz_138_; - reg _zz_139_; - reg [31:0] _zz_140_; - reg [31:0] _zz_141_; - reg [3:0] _zz_142_; - reg [2:0] _zz_143_; - reg _zz_144_; - wire [31:0] _zz_145_; - reg [31:0] DBusCachedPlugin_rspCounter; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_146_; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_147_; - reg [31:0] _zz_148_; - wire _zz_149_; - reg [31:0] _zz_150_; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [32:0] _zz_151_; - wire _zz_152_; - wire _zz_153_; - wire _zz_154_; - wire _zz_155_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_156_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_157_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_158_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_159_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_160_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_161_; - wire `AluCtrlEnum_defaultEncoding_type _zz_162_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_163_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_164_; - reg [31:0] _zz_165_; - wire _zz_166_; - reg [19:0] _zz_167_; - wire _zz_168_; - reg [19:0] _zz_169_; - reg [31:0] _zz_170_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_171_; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_172_; - reg _zz_173_; - reg _zz_174_; - wire _zz_175_; - reg _zz_176_; - reg [4:0] _zz_177_; - reg [31:0] _zz_178_; - wire _zz_179_; - wire _zz_180_; - wire _zz_181_; - wire _zz_182_; - wire _zz_183_; - wire _zz_184_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_185_; - reg _zz_186_; - reg _zz_187_; - wire _zz_188_; - reg [19:0] _zz_189_; - wire _zz_190_; - reg [10:0] _zz_191_; - wire _zz_192_; - reg [18:0] _zz_193_; - reg _zz_194_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_195_; - reg [19:0] _zz_196_; - wire _zz_197_; - reg [10:0] _zz_198_; - wire _zz_199_; - reg [18:0] _zz_200_; - wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] CsrPlugin_misa_base; - reg [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_201_; - wire _zz_202_; - wire _zz_203_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_204_; - wire _zz_205_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - reg CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - reg execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - wire [65:0] writeBack_MulPlugin_result; - reg [32:0] memory_DivPlugin_rs1; - reg [31:0] memory_DivPlugin_rs2; - reg [64:0] memory_DivPlugin_accumulator; - reg memory_DivPlugin_div_needRevert; - reg memory_DivPlugin_div_counter_willIncrement; - reg memory_DivPlugin_div_counter_willClear; - reg [5:0] memory_DivPlugin_div_counter_valueNext; - reg [5:0] memory_DivPlugin_div_counter_value; - wire memory_DivPlugin_div_counter_willOverflowIfInc; - wire memory_DivPlugin_div_counter_willOverflow; - reg memory_DivPlugin_div_done; - reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_206_; - wire [32:0] _zz_207_; - wire [32:0] _zz_208_; - wire [31:0] _zz_209_; - wire _zz_210_; - wire _zz_211_; - reg [32:0] _zz_212_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_213_; - wire [31:0] _zz_214_; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_215_; - reg DebugPlugin_resetIt_regNext; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg [33:0] execute_to_memory_MUL_HH; - reg [33:0] memory_to_writeBack_MUL_HH; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg decode_to_execute_DO_EBREAK; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg decode_to_execute_IS_RS1_SIGNED; - reg decode_to_execute_IS_RS2_SIGNED; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg decode_to_execute_MEMORY_WR; - reg execute_to_memory_MEMORY_WR; - reg memory_to_writeBack_MEMORY_WR; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg decode_to_execute_MEMORY_MANAGMENT; - reg [33:0] execute_to_memory_MUL_LH; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_to_execute_RS2; - reg decode_to_execute_CSR_READ_OPCODE; - reg [33:0] execute_to_memory_MUL_HL; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_BRANCH_DO; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg [51:0] memory_to_writeBack_MUL_LOW; - reg [31:0] execute_to_memory_MUL_LL; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg [31:0] decode_to_execute_RS1; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg memory_to_writeBack_IS_MUL; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg decode_to_execute_IS_CSR; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg [2:0] _zz_216_; - reg [2:0] _zz_217_; - reg _zz_218_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_219_; - wire _zz_220_; - wire _zz_221_; - wire _zz_222_; - wire _zz_223_; - wire _zz_224_; - reg _zz_225_; - reg [31:0] dBusWishbone_DAT_MISO_regNext; - `ifndef SYNTHESIS - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_1__string; - reg [39:0] _zz_2__string; - reg [39:0] _zz_3__string; - reg [71:0] _zz_4__string; - reg [71:0] _zz_5__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_6__string; - reg [71:0] _zz_7__string; - reg [71:0] _zz_8__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_9__string; - reg [63:0] _zz_10__string; - reg [63:0] _zz_11__string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_12__string; - reg [95:0] _zz_13__string; - reg [95:0] _zz_14__string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_15__string; - reg [23:0] _zz_16__string; - reg [23:0] _zz_17__string; - reg [31:0] _zz_18__string; - reg [31:0] _zz_19__string; - reg [39:0] _zz_20__string; - reg [39:0] _zz_21__string; - reg [39:0] _zz_22__string; - reg [39:0] _zz_23__string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_24__string; - reg [39:0] _zz_25__string; - reg [39:0] _zz_26__string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33__string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34__string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_37__string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_40__string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_45__string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_47__string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_52__string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_54__string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_57__string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_59__string; - reg [63:0] _zz_66__string; - reg [71:0] _zz_68__string; - reg [23:0] _zz_70__string; - reg [39:0] _zz_80__string; - reg [39:0] _zz_83__string; - reg [31:0] _zz_84__string; - reg [95:0] _zz_85__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_97__string; - reg [95:0] _zz_156__string; - reg [31:0] _zz_157__string; - reg [39:0] _zz_158__string; - reg [39:0] _zz_159__string; - reg [23:0] _zz_160__string; - reg [71:0] _zz_161__string; - reg [63:0] _zz_162__string; - reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - `endif - - (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_248_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_249_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_250_ = 1'b1; - assign _zz_251_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_252_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_253_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_254_ = ((_zz_231_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_93_)); - assign _zz_255_ = ((_zz_231_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_94_)); - assign _zz_256_ = ((_zz_231_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_95_)); - assign _zz_257_ = ((_zz_231_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); - assign _zz_258_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_259_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_260_ = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_261_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0); - assign _zz_262_ = (! memory_DivPlugin_div_done); - assign _zz_263_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_264_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_265_ = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_266_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_267_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_268_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_269_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_270_ = (1'b0 || (! 1'b1)); - assign _zz_271_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_272_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_273_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_274_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_275_ = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_276_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_277_ = execute_INSTRUCTION[13 : 12]; - assign _zz_278_ = (! memory_arbitration_isStuck); - assign _zz_279_ = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_280_ = (iBus_cmd_valid || (_zz_217_ != (3'b000))); - assign _zz_281_ = (_zz_244_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); - assign _zz_282_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_283_ = ((_zz_201_ && 1'b1) && (! 1'b0)); - assign _zz_284_ = ((_zz_202_ && 1'b1) && (! 1'b0)); - assign _zz_285_ = ((_zz_203_ && 1'b1) && (! 1'b0)); - assign _zz_286_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_287_ = execute_INSTRUCTION[13]; - assign _zz_288_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_289_ = (_zz_104_ - (5'b00001)); - assign _zz_290_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_291_ = {29'd0, _zz_290_}; - assign _zz_292_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_293_ = {{_zz_120_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_294_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_295_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_296_ = {{_zz_122_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_297_ = {{_zz_124_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_298_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_299_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_300_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); - assign _zz_301_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); - assign _zz_302_ = _zz_151_[0 : 0]; - assign _zz_303_ = _zz_151_[1 : 1]; - assign _zz_304_ = _zz_151_[2 : 2]; - assign _zz_305_ = _zz_151_[3 : 3]; - assign _zz_306_ = _zz_151_[10 : 10]; - assign _zz_307_ = _zz_151_[11 : 11]; - assign _zz_308_ = _zz_151_[14 : 14]; - assign _zz_309_ = _zz_151_[15 : 15]; - assign _zz_310_ = _zz_151_[16 : 16]; - assign _zz_311_ = _zz_151_[17 : 17]; - assign _zz_312_ = _zz_151_[18 : 18]; - assign _zz_313_ = _zz_151_[19 : 19]; - assign _zz_314_ = _zz_151_[20 : 20]; - assign _zz_315_ = _zz_151_[21 : 21]; - assign _zz_316_ = _zz_151_[22 : 22]; - assign _zz_317_ = _zz_151_[25 : 25]; - assign _zz_318_ = _zz_151_[28 : 28]; - assign _zz_319_ = _zz_151_[32 : 32]; - assign _zz_320_ = execute_SRC_LESS; - assign _zz_321_ = (3'b100); - assign _zz_322_ = execute_INSTRUCTION[19 : 15]; - assign _zz_323_ = execute_INSTRUCTION[31 : 20]; - assign _zz_324_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_325_ = ($signed(_zz_326_) + $signed(_zz_329_)); - assign _zz_326_ = ($signed(_zz_327_) + $signed(_zz_328_)); - assign _zz_327_ = execute_SRC1; - assign _zz_328_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_329_ = (execute_SRC_USE_SUB_LESS ? _zz_330_ : _zz_331_); - assign _zz_330_ = (32'b00000000000000000000000000000001); - assign _zz_331_ = (32'b00000000000000000000000000000000); - assign _zz_332_ = ($signed(_zz_334_) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_333_ = _zz_332_[31 : 0]; - assign _zz_334_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_335_ = execute_INSTRUCTION[31 : 20]; - assign _zz_336_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_337_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_338_ = {_zz_189_,execute_INSTRUCTION[31 : 20]}; - assign _zz_339_ = {{_zz_191_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_340_ = {{_zz_193_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_341_ = execute_INSTRUCTION[31 : 20]; - assign _zz_342_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_343_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_344_ = (3'b100); - assign _zz_345_ = (_zz_204_ & (~ _zz_346_)); - assign _zz_346_ = (_zz_204_ - (2'b01)); - assign _zz_347_ = ($signed(_zz_348_) + $signed(_zz_353_)); - assign _zz_348_ = ($signed(_zz_349_) + $signed(_zz_351_)); - assign _zz_349_ = (52'b0000000000000000000000000000000000000000000000000000); - assign _zz_350_ = {1'b0,memory_MUL_LL}; - assign _zz_351_ = {{19{_zz_350_[32]}}, _zz_350_}; - assign _zz_352_ = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_353_ = {{2{_zz_352_[49]}}, _zz_352_}; - assign _zz_354_ = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_355_ = {{2{_zz_354_[49]}}, _zz_354_}; - assign _zz_356_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_357_ = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_358_ = writeBack_MUL_LOW[31 : 0]; - assign _zz_359_ = writeBack_MulPlugin_result[63 : 32]; - assign _zz_360_ = memory_DivPlugin_div_counter_willIncrement; - assign _zz_361_ = {5'd0, _zz_360_}; - assign _zz_362_ = {1'd0, memory_DivPlugin_rs2}; - assign _zz_363_ = {_zz_206_,(! _zz_208_[32])}; - assign _zz_364_ = _zz_208_[31:0]; - assign _zz_365_ = _zz_207_[31:0]; - assign _zz_366_ = _zz_367_; - assign _zz_367_ = _zz_368_; - assign _zz_368_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_209_) : _zz_209_)} + _zz_370_); - assign _zz_369_ = memory_DivPlugin_div_needRevert; - assign _zz_370_ = {32'd0, _zz_369_}; - assign _zz_371_ = _zz_211_; - assign _zz_372_ = {32'd0, _zz_371_}; - assign _zz_373_ = _zz_210_; - assign _zz_374_ = {31'd0, _zz_373_}; - assign _zz_375_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_376_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_377_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_378_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_379_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_380_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_381_ = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_382_ = (iBus_cmd_payload_address >>> 5); - assign _zz_383_ = 1'b1; - assign _zz_384_ = 1'b1; - assign _zz_385_ = {_zz_107_,{_zz_109_,_zz_108_}}; - assign _zz_386_ = decode_INSTRUCTION[31]; - assign _zz_387_ = decode_INSTRUCTION[31]; - assign _zz_388_ = decode_INSTRUCTION[7]; - assign _zz_389_ = (32'b00000000000000000000000001100100); - assign _zz_390_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001000000)) == (32'b00000000000000000010000001000000)); - assign _zz_391_ = ((decode_INSTRUCTION & _zz_399_) == (32'b00000000000000000001000001000000)); - assign _zz_392_ = {(_zz_400_ == _zz_401_),{_zz_402_,_zz_403_}}; - assign _zz_393_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000010100)) == (32'b00000000000000000100000000010000)); - assign _zz_394_ = ((decode_INSTRUCTION & _zz_404_) == (32'b00000000000000000010000000010000)); - assign _zz_395_ = (1'b0); - assign _zz_396_ = ({_zz_154_,{_zz_405_,_zz_406_}} != (6'b000000)); - assign _zz_397_ = ({_zz_407_,_zz_408_} != (2'b00)); - assign _zz_398_ = {(_zz_409_ != _zz_410_),{_zz_411_,{_zz_412_,_zz_413_}}}; - assign _zz_399_ = (32'b00000000000000000001000001000000); - assign _zz_400_ = (decode_INSTRUCTION & (32'b00000000000100000000000001000000)); - assign _zz_401_ = (32'b00000000000000000000000001000000); - assign _zz_402_ = ((decode_INSTRUCTION & _zz_414_) == (32'b00000000000000000000000001000000)); - assign _zz_403_ = ((decode_INSTRUCTION & _zz_415_) == (32'b00000000000000000000000000000000)); - assign _zz_404_ = (32'b00000000000000000110000000010100); - assign _zz_405_ = (_zz_416_ == _zz_417_); - assign _zz_406_ = {_zz_418_,{_zz_419_,_zz_420_}}; - assign _zz_407_ = (_zz_421_ == _zz_422_); - assign _zz_408_ = (_zz_423_ == _zz_424_); - assign _zz_409_ = {_zz_425_,{_zz_426_,_zz_427_}}; - assign _zz_410_ = (3'b000); - assign _zz_411_ = ({_zz_428_,_zz_429_} != (5'b00000)); - assign _zz_412_ = (_zz_430_ != _zz_431_); - assign _zz_413_ = {_zz_432_,{_zz_433_,_zz_434_}}; - assign _zz_414_ = (32'b00000000000000000000000001010000); - assign _zz_415_ = (32'b00000000000000000000000000111000); - assign _zz_416_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); - assign _zz_417_ = (32'b00000000000000000001000000010000); - assign _zz_418_ = ((decode_INSTRUCTION & _zz_435_) == (32'b00000000000000000010000000010000)); - assign _zz_419_ = (_zz_436_ == _zz_437_); - assign _zz_420_ = {_zz_438_,_zz_439_}; - assign _zz_421_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_422_ = (32'b00000000000000000101000000010000); - assign _zz_423_ = (decode_INSTRUCTION & (32'b00000010000000000111000001100100)); - assign _zz_424_ = (32'b00000000000000000101000000100000); - assign _zz_425_ = ((decode_INSTRUCTION & _zz_440_) == (32'b01000000000000000001000000010000)); - assign _zz_426_ = (_zz_441_ == _zz_442_); - assign _zz_427_ = (_zz_443_ == _zz_444_); - assign _zz_428_ = (_zz_445_ == _zz_446_); - assign _zz_429_ = {_zz_155_,{_zz_447_,_zz_448_}}; - assign _zz_430_ = {_zz_155_,_zz_449_}; - assign _zz_431_ = (2'b00); - assign _zz_432_ = ({_zz_450_,_zz_451_} != (2'b00)); - assign _zz_433_ = (_zz_452_ != _zz_453_); - assign _zz_434_ = {_zz_454_,{_zz_455_,_zz_456_}}; - assign _zz_435_ = (32'b00000000000000000010000000010000); - assign _zz_436_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000)); - assign _zz_437_ = (32'b00000000000000000000000000010000); - assign _zz_438_ = ((decode_INSTRUCTION & _zz_457_) == (32'b00000000000000000000000000000100)); - assign _zz_439_ = ((decode_INSTRUCTION & _zz_458_) == (32'b00000000000000000000000000000000)); - assign _zz_440_ = (32'b01000000000000000011000001010100); - assign _zz_441_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_442_ = (32'b00000000000000000001000000010000); - assign _zz_443_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100)); - assign _zz_444_ = (32'b00000000000000000001000000010000); - assign _zz_445_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000000)); - assign _zz_446_ = (32'b00000000000000000000000001000000); - assign _zz_447_ = (_zz_459_ == _zz_460_); - assign _zz_448_ = {_zz_461_,_zz_462_}; - assign _zz_449_ = ((decode_INSTRUCTION & _zz_463_) == (32'b00000000000000000000000000100000)); - assign _zz_450_ = _zz_155_; - assign _zz_451_ = (_zz_464_ == _zz_465_); - assign _zz_452_ = (_zz_466_ == _zz_467_); - assign _zz_453_ = (1'b0); - assign _zz_454_ = (_zz_468_ != (1'b0)); - assign _zz_455_ = (_zz_469_ != _zz_470_); - assign _zz_456_ = {_zz_471_,{_zz_472_,_zz_473_}}; - assign _zz_457_ = (32'b00000000000000000000000000001100); - assign _zz_458_ = (32'b00000000000000000000000000101000); - assign _zz_459_ = (decode_INSTRUCTION & (32'b00000000000000000100000000100000)); - assign _zz_460_ = (32'b00000000000000000100000000100000); - assign _zz_461_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110000)) == (32'b00000000000000000000000000010000)); - assign _zz_462_ = ((decode_INSTRUCTION & (32'b00000010000000000000000000100000)) == (32'b00000000000000000000000000100000)); - assign _zz_463_ = (32'b00000000000000000000000001110000); - assign _zz_464_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_465_ = (32'b00000000000000000000000000000000); - assign _zz_466_ = (decode_INSTRUCTION & (32'b00000000000000000101000001001000)); - assign _zz_467_ = (32'b00000000000000000001000000001000); - assign _zz_468_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000)); - assign _zz_469_ = {(_zz_474_ == _zz_475_),{_zz_476_,{_zz_477_,_zz_478_}}}; - assign _zz_470_ = (4'b0000); - assign _zz_471_ = ({_zz_479_,{_zz_480_,_zz_481_}} != (3'b000)); - assign _zz_472_ = (_zz_482_ != (1'b0)); - assign _zz_473_ = {(_zz_483_ != _zz_484_),{_zz_485_,{_zz_486_,_zz_487_}}}; - assign _zz_474_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_475_ = (32'b00000000000000000000000000000000); - assign _zz_476_ = ((decode_INSTRUCTION & _zz_488_) == (32'b00000000000000000000000000000000)); - assign _zz_477_ = (_zz_489_ == _zz_490_); - assign _zz_478_ = (_zz_491_ == _zz_492_); - assign _zz_479_ = ((decode_INSTRUCTION & _zz_493_) == (32'b00000000000000000000000001000000)); - assign _zz_480_ = (_zz_494_ == _zz_495_); - assign _zz_481_ = (_zz_496_ == _zz_497_); - assign _zz_482_ = ((decode_INSTRUCTION & _zz_498_) == (32'b00000000000000000100000000001000)); - assign _zz_483_ = (_zz_499_ == _zz_500_); - assign _zz_484_ = (1'b0); - assign _zz_485_ = ({_zz_501_,_zz_502_} != (2'b00)); - assign _zz_486_ = (_zz_503_ != _zz_504_); - assign _zz_487_ = {_zz_505_,{_zz_506_,_zz_507_}}; - assign _zz_488_ = (32'b00000000000000000000000000011000); - assign _zz_489_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); - assign _zz_490_ = (32'b00000000000000000010000000000000); - assign _zz_491_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); - assign _zz_492_ = (32'b00000000000000000001000000000000); - assign _zz_493_ = (32'b00000000000000000000000001000100); - assign _zz_494_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); - assign _zz_495_ = (32'b00000000000000000010000000010000); - assign _zz_496_ = (decode_INSTRUCTION & (32'b01000000000000000000000000110100)); - assign _zz_497_ = (32'b01000000000000000000000000110000); - assign _zz_498_ = (32'b00000000000000000100000001001000); - assign _zz_499_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_500_ = (32'b00000000000000000000000000100000); - assign _zz_501_ = ((decode_INSTRUCTION & _zz_508_) == (32'b00000000000000000001000001010000)); - assign _zz_502_ = ((decode_INSTRUCTION & _zz_509_) == (32'b00000000000000000010000001010000)); - assign _zz_503_ = {_zz_155_,{_zz_510_,{_zz_511_,_zz_512_}}}; - assign _zz_504_ = (5'b00000); - assign _zz_505_ = ((_zz_513_ == _zz_514_) != (1'b0)); - assign _zz_506_ = (_zz_515_ != (1'b0)); - assign _zz_507_ = {(_zz_516_ != _zz_517_),{_zz_518_,{_zz_519_,_zz_520_}}}; - assign _zz_508_ = (32'b00000000000000000001000001010000); - assign _zz_509_ = (32'b00000000000000000010000001010000); - assign _zz_510_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000110000)) == (32'b00000000000000000010000000010000)); - assign _zz_511_ = ((decode_INSTRUCTION & _zz_521_) == (32'b00000000000000000000000000010000)); - assign _zz_512_ = {(_zz_522_ == _zz_523_),(_zz_524_ == _zz_525_)}; - assign _zz_513_ = (decode_INSTRUCTION & (32'b00010000000100000011000001010000)); - assign _zz_514_ = (32'b00000000000100000000000001010000); - assign _zz_515_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_516_ = ((decode_INSTRUCTION & _zz_526_) == (32'b00000000000000000010000000000000)); - assign _zz_517_ = (1'b0); - assign _zz_518_ = ((_zz_527_ == _zz_528_) != (1'b0)); - assign _zz_519_ = (_zz_152_ != (1'b0)); - assign _zz_520_ = {(_zz_529_ != _zz_530_),{_zz_531_,{_zz_532_,_zz_533_}}}; - assign _zz_521_ = (32'b00000000000000000001000000110000); - assign _zz_522_ = (decode_INSTRUCTION & (32'b00000010000000000010000001100000)); - assign _zz_523_ = (32'b00000000000000000010000000100000); - assign _zz_524_ = (decode_INSTRUCTION & (32'b00000010000000000011000000100000)); - assign _zz_525_ = (32'b00000000000000000000000000100000); - assign _zz_526_ = (32'b00000000000000000011000000000000); - assign _zz_527_ = (decode_INSTRUCTION & (32'b00000010000000000100000001110100)); - assign _zz_528_ = (32'b00000010000000000000000000110000); - assign _zz_529_ = {((decode_INSTRUCTION & _zz_534_) == (32'b00010000000000000000000001010000)),((decode_INSTRUCTION & _zz_535_) == (32'b00000000000000000000000001010000))}; - assign _zz_530_ = (2'b00); - assign _zz_531_ = (((decode_INSTRUCTION & _zz_536_) == (32'b00000000000000000000000001010000)) != (1'b0)); - assign _zz_532_ = ({_zz_154_,_zz_537_} != (2'b00)); - assign _zz_533_ = {(_zz_538_ != (1'b0)),{(_zz_539_ != _zz_540_),{_zz_541_,{_zz_542_,_zz_543_}}}}; - assign _zz_534_ = (32'b00010000001000000011000001010000); - assign _zz_535_ = (32'b00010000000100000011000001010000); - assign _zz_536_ = (32'b00000000000100000011000001010000); - assign _zz_537_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); - assign _zz_538_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); - assign _zz_539_ = {(_zz_544_ == _zz_545_),_zz_153_}; - assign _zz_540_ = (2'b00); - assign _zz_541_ = ({_zz_546_,_zz_153_} != (2'b00)); - assign _zz_542_ = ({_zz_547_,_zz_548_} != (2'b00)); - assign _zz_543_ = {(_zz_549_ != _zz_550_),{_zz_551_,_zz_552_}}; - assign _zz_544_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100)); - assign _zz_545_ = (32'b00000000000000000000000000000100); - assign _zz_546_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); - assign _zz_547_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)); - assign _zz_548_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_549_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001100100)) == (32'b00000010000000000100000000100000)); - assign _zz_550_ = (1'b0); - assign _zz_551_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000)),((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100000))} != (2'b00)); - assign _zz_552_ = (_zz_152_ != (1'b0)); - assign _zz_553_ = (32'b00000000000000000001000001111111); - assign _zz_554_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_555_ = (32'b00000000000000000010000001110011); - assign _zz_556_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_557_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_558_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_559_) == (32'b00000000000000000000000000000011)),{(_zz_560_ == _zz_561_),{_zz_562_,{_zz_563_,_zz_564_}}}}}}; - assign _zz_559_ = (32'b00000000000000000101000001011111); - assign _zz_560_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_561_ = (32'b00000000000000000000000001100011); - assign _zz_562_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_563_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_564_ = {((decode_INSTRUCTION & (32'b00000001111100000111000001111111)) == (32'b00000000000000000101000000001111)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_565_) == (32'b00000000000000000001000000010011)),{(_zz_566_ == _zz_567_),{_zz_568_,{_zz_569_,_zz_570_}}}}}}; - assign _zz_565_ = (32'b11111100000000000011000001111111); - assign _zz_566_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_567_ = (32'b00000000000000000101000000110011); - assign _zz_568_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_569_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_570_ = {((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)),((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011))}; - assign _zz_571_ = execute_INSTRUCTION[31]; - assign _zz_572_ = execute_INSTRUCTION[31]; - assign _zz_573_ = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_62_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end + always @(*) begin + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_383_) begin - _zz_245_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_384_) begin - _zz_246_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_226_), - .io_cpu_prefetch_isValid(_zz_227_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_228_), - .io_cpu_fetch_isStuck(_zz_229_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_230_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_231_), - .io_cpu_decode_isStuck(_zz_232_), - .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), - .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), - .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), - .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), - .io_cpu_decode_isUser(_zz_233_), - .io_cpu_fill_valid(_zz_234_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - ._zz_10_(_zz_216_), - ._zz_11_(IBusCachedPlugin_injectionPort_payload), - .clk(clk), - .reset(reset) - ); - DataCache dataCache_1_ ( - .io_cpu_execute_isValid(_zz_235_), - .io_cpu_execute_address(_zz_236_), - .io_cpu_execute_args_wr(execute_MEMORY_WR), - .io_cpu_execute_args_data(_zz_146_), - .io_cpu_execute_args_size(execute_DBusCachedPlugin_size), - .io_cpu_memory_isValid(_zz_237_), - .io_cpu_memory_isStuck(memory_arbitration_isStuck), - .io_cpu_memory_isRemoved(memory_arbitration_removeIt), - .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), - .io_cpu_memory_address(_zz_238_), - .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), - .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), - .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), - .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_239_), - .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), - .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), - .io_cpu_writeBack_isValid(_zz_240_), - .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), - .io_cpu_writeBack_isUser(_zz_241_), - .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), - .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), - .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), - .io_cpu_writeBack_address(_zz_242_), - .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), - .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), - .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), - .io_cpu_redo(dataCache_1__io_cpu_redo), - .io_cpu_flush_valid(_zz_243_), - .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), - .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), - .io_mem_cmd_ready(_zz_244_), - .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), - .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), - .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), - .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), - .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), - .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), - .io_mem_rsp_valid(dBus_rsp_valid), - .io_mem_rsp_payload_data(dBus_rsp_payload_data), - .io_mem_rsp_payload_error(dBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); always @(*) begin - case(_zz_385_) - 3'b000 : begin - _zz_247_ = DBusCachedPlugin_redoBranch_payload; - end - 3'b001 : begin - _zz_247_ = CsrPlugin_jumpInterface_payload; - end - 3'b010 : begin - _zz_247_ = BranchPlugin_jumpInterface_payload; - end - 3'b011 : begin - _zz_247_ = IBusCachedPlugin_redoBranch_payload; - end - default : begin - _zz_247_ = IBusCachedPlugin_predictionJumpInterface_payload; - end + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; endcase end - - `ifndef SYNTHESIS always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_1_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_1__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_1__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_1__string = "AND_1"; - default : _zz_1__string = "?????"; + case(_zz_30) + `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; + default : _zz_30_string = "????"; endcase end always @(*) begin - case(_zz_2_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_2__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_2__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_2__string = "AND_1"; - default : _zz_2__string = "?????"; + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_3_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_3__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_3__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_3__string = "AND_1"; - default : _zz_3__string = "?????"; + case(_zz_33) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; + default : _zz_33_string = "?????????"; endcase end always @(*) begin - case(_zz_4_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_4__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_4__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_4__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_4__string = "SRA_1 "; - default : _zz_4__string = "?????????"; + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_5_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_5__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_5__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_5__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_5__string = "SRA_1 "; - default : _zz_5__string = "?????????"; + case(_zz_34) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; + default : _zz_34_string = "?????????"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_6_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_6__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_6__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_6__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_6__string = "SRA_1 "; - default : _zz_6__string = "?????????"; + case(_zz_36) + `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; + default : _zz_36_string = "???"; endcase end always @(*) begin - case(_zz_7_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_7__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_7__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_7__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_7__string = "SRA_1 "; - default : _zz_7__string = "?????????"; + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_8_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_8__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_8__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_8__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_8__string = "SRA_1 "; - default : _zz_8__string = "?????????"; + case(_zz_37) + `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; + default : _zz_37_string = "????????????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_9_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_9__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_9__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_9__string = "BITWISE "; - default : _zz_9__string = "????????"; + case(_zz_38) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; + default : _zz_38_string = "????????"; endcase end always @(*) begin - case(_zz_10_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10__string = "BITWISE "; - default : _zz_10__string = "????????"; + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_11_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_11__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_11__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_11__string = "BITWISE "; - default : _zz_11__string = "????????"; + case(_zz_39) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; + default : _zz_39_string = "?????"; endcase end always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(_zz_43) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_12_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 "; - default : _zz_12__string = "????????????"; + case(_zz_44) + `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; + default : _zz_44_string = "????"; endcase end always @(*) begin - case(_zz_13_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 "; - default : _zz_13__string = "????????????"; + case(_zz_45) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; + default : _zz_45_string = "?????????"; endcase end always @(*) begin - case(_zz_14_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_14__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_14__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_14__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_14__string = "URS1 "; - default : _zz_14__string = "????????????"; + case(_zz_46) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; + default : _zz_46_string = "?????"; endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_15_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_15__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_15__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_15__string = "PC "; - default : _zz_15__string = "???"; - endcase - end - always @(*) begin - case(_zz_16_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_16__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_16__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_16__string = "PC "; - default : _zz_16__string = "???"; - endcase - end - always @(*) begin - case(_zz_17_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_17__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_17__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_17__string = "PC "; - default : _zz_17__string = "???"; - endcase - end - always @(*) begin - case(_zz_18_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_18__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_18__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_18__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_18__string = "JALR"; - default : _zz_18__string = "????"; - endcase - end - always @(*) begin - case(_zz_19_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_19__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_19__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_19__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_19__string = "JALR"; - default : _zz_19__string = "????"; - endcase - end - always @(*) begin - case(_zz_20_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_20__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_20__string = "ECALL"; - default : _zz_20__string = "?????"; - endcase - end - always @(*) begin - case(_zz_21_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_21__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_21__string = "ECALL"; - default : _zz_21__string = "?????"; - endcase - end - always @(*) begin - case(_zz_22_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_22__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_22__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_22__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_22__string = "ECALL"; - default : _zz_22__string = "?????"; - endcase - end - always @(*) begin - case(_zz_23_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_23__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_23__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_23__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_23__string = "ECALL"; - default : _zz_23__string = "?????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_24_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_24__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_24__string = "ECALL"; - default : _zz_24__string = "?????"; - endcase - end - always @(*) begin - case(_zz_25_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_25__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25__string = "ECALL"; - default : _zz_25__string = "?????"; - endcase - end - always @(*) begin - case(_zz_26_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_26__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL"; - default : _zz_26__string = "?????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_33_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33__string = "ECALL"; - default : _zz_33__string = "?????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; - default : execute_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_34_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34__string = "ECALL"; - default : _zz_34__string = "?????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; - default : writeBack_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_37_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_37__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_37__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_37__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_37__string = "ECALL"; - default : _zz_37__string = "?????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_40_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_40__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_40__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_40__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_40__string = "JALR"; - default : _zz_40__string = "????"; - endcase - end - always @(*) begin - case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_45_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45__string = "SRA_1 "; - default : _zz_45__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_47_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_47__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_47__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_47__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_47__string = "SRA_1 "; - default : _zz_47__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; - default : execute_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_52_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_52__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_52__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_52__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_52__string = "PC "; - default : _zz_52__string = "???"; - endcase - end - always @(*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; - default : execute_SRC1_CTRL_string = "????????????"; + case(_zz_47) + `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; + default : _zz_47_string = "???"; endcase end always @(*) begin - case(_zz_54_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_54__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_54__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54__string = "URS1 "; - default : _zz_54__string = "????????????"; - endcase - end - always @(*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_57_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_57__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_57__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_57__string = "BITWISE "; - default : _zz_57__string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; + case(_zz_48) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; + default : _zz_48_string = "????????"; endcase end always @(*) begin - case(_zz_59_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_59__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_59__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_59__string = "AND_1"; - default : _zz_59__string = "?????"; + case(_zz_49) + `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; + default : _zz_49_string = "????????????"; endcase end always @(*) begin - case(_zz_66_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_66__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_66__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_66__string = "BITWISE "; - default : _zz_66__string = "????????"; + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_68_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_68__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_68__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_68__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_68__string = "SRA_1 "; - default : _zz_68__string = "?????????"; + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; endcase end always @(*) begin - case(_zz_70_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_70__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_70__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_70__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_70__string = "PC "; - default : _zz_70__string = "???"; + case(_zz_92) + `Src1CtrlEnum_defaultEncoding_RS : _zz_92_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_92_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_92_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_92_string = "URS1 "; + default : _zz_92_string = "????????????"; endcase end always @(*) begin - case(_zz_80_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_80__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_80__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_80__string = "AND_1"; - default : _zz_80__string = "?????"; + case(_zz_93) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_93_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_93_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_93_string = "BITWISE "; + default : _zz_93_string = "????????"; endcase end always @(*) begin - case(_zz_83_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_83__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_83__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_83__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_83__string = "ECALL"; - default : _zz_83__string = "?????"; + case(_zz_94) + `Src2CtrlEnum_defaultEncoding_RS : _zz_94_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_94_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_94_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_94_string = "PC "; + default : _zz_94_string = "???"; endcase end always @(*) begin - case(_zz_84_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_84__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_84__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_84__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_84__string = "JALR"; - default : _zz_84__string = "????"; + case(_zz_95) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_95_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_95_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_95_string = "AND_1"; + default : _zz_95_string = "?????"; endcase end always @(*) begin - case(_zz_85_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_85__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_85__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_85__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_85__string = "URS1 "; - default : _zz_85__string = "????????????"; + case(_zz_96) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_96_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_96_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_96_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_96_string = "SRA_1 "; + default : _zz_96_string = "?????????"; endcase end always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; + case(_zz_97) + `BranchCtrlEnum_defaultEncoding_INC : _zz_97_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_97_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_97_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_97_string = "JALR"; + default : _zz_97_string = "????"; endcase end always @(*) begin - case(_zz_97_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_97__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_97__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_97__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_97__string = "JALR"; - default : _zz_97__string = "????"; + case(_zz_98) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_98_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_98_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_98_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_98_string = "ECALL"; + default : _zz_98_string = "?????"; endcase end always @(*) begin - case(_zz_156_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_156__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_156__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_156__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_156__string = "URS1 "; - default : _zz_156__string = "????????????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_157_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_157__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_157__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_157__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_157__string = "JALR"; - default : _zz_157__string = "????"; + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_158_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_158__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_158__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_158__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_158__string = "ECALL"; - default : _zz_158__string = "?????"; + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_159_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_159__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_159__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_159__string = "AND_1"; - default : _zz_159__string = "?????"; + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_160_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_160__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_160__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_160__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_160__string = "PC "; - default : _zz_160__string = "???"; + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_161_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_161__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_161__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_161__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_161__string = "SRA_1 "; - default : _zz_161__string = "?????????"; + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_162_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_162__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_162__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_162__string = "BITWISE "; - default : _zz_162__string = "????????"; + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin @@ -3358,153 +2461,93 @@ module VexRiscv ( default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; - default : decode_to_execute_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : decode_to_execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; - default : execute_to_memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - `endif - - assign execute_SHIFT_RIGHT = _zz_46_; - assign execute_BRANCH_CALC = _zz_38_; - assign decode_ALU_BITWISE_CTRL = _zz_1_; - assign _zz_2_ = _zz_3_; - assign decode_IS_CSR = _zz_77_; - assign decode_CSR_WRITE_OPCODE = _zz_36_; - assign execute_REGFILE_WRITE_DATA = _zz_58_; - assign decode_SRC_LESS_UNSIGNED = _zz_86_; - assign memory_IS_MUL = execute_to_memory_IS_MUL; - assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_81_; - assign _zz_4_ = _zz_5_; - assign decode_SHIFT_CTRL = _zz_6_; - assign _zz_7_ = _zz_8_; - assign decode_ALU_CTRL = _zz_9_; - assign _zz_10_ = _zz_11_; - assign decode_SRC1_CTRL = _zz_12_; - assign _zz_13_ = _zz_14_; - assign decode_SRC2_CTRL = _zz_15_; - assign _zz_16_ = _zz_17_; - assign _zz_18_ = _zz_19_; - assign _zz_20_ = _zz_21_; - assign _zz_22_ = _zz_23_; - assign decode_ENV_CTRL = _zz_24_; - assign _zz_25_ = _zz_26_; - assign decode_IS_DIV = _zz_87_; - assign execute_MUL_LL = _zz_32_; - assign memory_MUL_LOW = _zz_28_; - assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; - assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; - assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_100_; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_69_; - assign execute_BRANCH_DO = _zz_39_; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_92_; - assign execute_MUL_HL = _zz_30_; - assign decode_CSR_READ_OPCODE = _zz_35_; - assign execute_MUL_LH = _zz_31_; - assign decode_MEMORY_MANAGMENT = _zz_75_; - assign memory_PC = execute_to_memory_PC; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_76_; - assign decode_IS_RS2_SIGNED = _zz_89_; - assign decode_IS_RS1_SIGNED = _zz_82_; - assign decode_SRC2_FORCE_ZERO = _zz_56_; - assign decode_DO_EBREAK = _zz_27_; - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_42_; - assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = _zz_29_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_78_; - assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_79_; - assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_DIV = decode_to_execute_IS_DIV; - assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; - assign memory_IS_DIV = execute_to_memory_IS_DIV; - assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; - assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; - assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; - assign memory_MUL_HL = execute_to_memory_MUL_HL; - assign memory_MUL_LH = execute_to_memory_MUL_LH; - assign memory_MUL_LL = execute_to_memory_MUL_LL; - assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; - assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; - assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33_; - assign execute_ENV_CTRL = _zz_34_; - assign writeBack_ENV_CTRL = _zz_37_; - assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; - assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; - assign execute_PC = decode_to_execute_PC; - assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; - assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_41_; - assign execute_BRANCH_CTRL = _zz_40_; - assign decode_RS2_USE = _zz_88_; - assign decode_RS1_USE = _zz_73_; - always @ (*) begin - _zz_43_ = execute_REGFILE_WRITE_DATA; - if(_zz_248_)begin - _zz_43_ = execute_CsrPlugin_readData; - end + `endif + + assign memory_MUL_LOW = ($signed(_zz_249) + $signed(_zz_257)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_259; + assign execute_REGFILE_WRITE_DATA = _zz_100; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_187[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_261[0]; + assign decode_IS_RS1_SIGNED = _zz_262[0]; + assign decode_IS_DIV = _zz_263[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_264[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_265[0]; + assign _zz_8 = _zz_9; + assign _zz_10 = _zz_11; + assign decode_SHIFT_CTRL = _zz_12; + assign _zz_13 = _zz_14; + assign decode_ALU_BITWISE_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_SRC_LESS_UNSIGNED = _zz_266[0]; + assign decode_MEMORY_MANAGMENT = _zz_267[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_268[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_269[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_270[0]; + assign decode_SRC2_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_ALU_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_SRC1_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_271[0]; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_27; + assign execute_ENV_CTRL = _zz_28; + assign writeBack_ENV_CTRL = _zz_29; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_117; + assign execute_BRANCH_CTRL = _zz_30; + assign decode_RS2_USE = _zz_272[0]; + assign decode_RS1_USE = _zz_273[0]; + always @ (*) begin + _zz_31 = execute_REGFILE_WRITE_DATA; + if(_zz_208)begin + _zz_31 = execute_CsrPlugin_readData; + end end assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; @@ -3514,60 +2557,60 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - decode_RS2 = _zz_63_; - if(_zz_176_)begin - if((_zz_177_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_178_; + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_249_)begin - if(_zz_250_)begin - if(_zz_180_)begin - decode_RS2 = _zz_91_; + if(_zz_209)begin + if(_zz_210)begin + if(_zz_110)begin + decode_RS2 = _zz_50; end end end - if(_zz_251_)begin + if(_zz_211)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_182_)begin - decode_RS2 = _zz_44_; + if(_zz_112)begin + decode_RS2 = _zz_32; end end end - if(_zz_252_)begin + if(_zz_212)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_184_)begin - decode_RS2 = _zz_43_; + if(_zz_114)begin + decode_RS2 = _zz_31; end end end end always @ (*) begin - decode_RS1 = _zz_64_; - if(_zz_176_)begin - if((_zz_177_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_178_; + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_249_)begin - if(_zz_250_)begin - if(_zz_179_)begin - decode_RS1 = _zz_91_; + if(_zz_209)begin + if(_zz_210)begin + if(_zz_109)begin + decode_RS1 = _zz_50; end end end - if(_zz_251_)begin + if(_zz_211)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_181_)begin - decode_RS1 = _zz_44_; + if(_zz_111)begin + decode_RS1 = _zz_32; end end end - if(_zz_252_)begin + if(_zz_212)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_183_)begin - decode_RS1 = _zz_43_; + if(_zz_113)begin + decode_RS1 = _zz_31; end end end @@ -3575,71 +2618,70 @@ module VexRiscv ( assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_44_ = memory_REGFILE_WRITE_DATA; + _zz_32 = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_44_ = _zz_172_; + _zz_32 = _zz_108; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_44_ = memory_SHIFT_RIGHT; + _zz_32 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_253_)begin - _zz_44_ = memory_DivPlugin_div_result; + if(_zz_213)begin + _zz_32 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_45_; - assign execute_SHIFT_CTRL = _zz_47_; + assign memory_SHIFT_CTRL = _zz_33; + assign execute_SHIFT_CTRL = _zz_34; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_51_ = execute_PC; - assign execute_SRC2_CTRL = _zz_52_; - assign execute_SRC1_CTRL = _zz_54_; - assign decode_SRC_USE_SUB_LESS = _zz_74_; - assign decode_SRC_ADD_ZERO = _zz_65_; - assign execute_SRC_ADD_SUB = _zz_50_; - assign execute_SRC_LESS = _zz_48_; - assign execute_ALU_CTRL = _zz_57_; - assign execute_SRC2 = _zz_53_; - assign execute_SRC1 = _zz_55_; - assign execute_ALU_BITWISE_CTRL = _zz_59_; - assign _zz_60_ = writeBack_INSTRUCTION; - assign _zz_61_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_62_ = 1'b0; + assign _zz_35 = execute_PC; + assign execute_SRC2_CTRL = _zz_36; + assign execute_SRC1_CTRL = _zz_37; + assign decode_SRC_USE_SUB_LESS = _zz_274[0]; + assign decode_SRC_ADD_ZERO = _zz_275[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_38; + assign execute_SRC2 = _zz_106; + assign execute_SRC1 = _zz_101; + assign execute_ALU_BITWISE_CTRL = _zz_39; + assign _zz_40 = writeBack_INSTRUCTION; + assign _zz_41 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_42 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_62_ = 1'b1; + _zz_42 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_96_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_67_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_276[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_90_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_346) == 32'h00001073),{(_zz_347 == _zz_348),{_zz_349,{_zz_350,_zz_351}}}}}}} != 21'h0); always @ (*) begin - _zz_91_ = writeBack_REGFILE_WRITE_DATA; + _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_91_ = writeBack_DBusCachedPlugin_rspFormated; + _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_288_) + case(_zz_248) 2'b00 : begin - _zz_91_ = _zz_358_; + _zz_50 = _zz_318; end default : begin - _zz_91_ = _zz_359_; + _zz_50 = _zz_319; end endcase end @@ -3651,62 +2693,60 @@ module VexRiscv ( assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = _zz_49_; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_72_; - assign decode_FLUSH_ALL = _zz_71_; + assign decode_MEMORY_ENABLE = _zz_277[0]; + assign decode_FLUSH_ALL = _zz_278[0]; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_93_; - if(_zz_254_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_214)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin - _zz_93_ = _zz_94_; - if(_zz_255_)begin - _zz_93_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_215)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin - _zz_94_ = _zz_95_; - if(_zz_256_)begin - _zz_94_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_216)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_95_ = 1'b0; - if(_zz_257_)begin - _zz_95_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_217)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_97_; - assign decode_INSTRUCTION = _zz_101_; + assign decode_BRANCH_CTRL = _zz_51; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_98_ = memory_FORMAL_PC_NEXT; + _zz_52 = memory_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin - _zz_98_ = BranchPlugin_jumpInterface_payload; + _zz_52 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_99_ = decode_FORMAL_PC_NEXT; + _zz_53 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_99_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_99_ = IBusCachedPlugin_redoBranch_payload; + _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; end end - assign decode_PC = _zz_102_; + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -3714,18 +2754,10 @@ module VexRiscv ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_216_) - 3'b000 : begin - end - 3'b001 : begin - end + case(_zz_144) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end - 3'b011 : begin - end - 3'b100 : begin - end default : begin end endcase @@ -3733,20 +2765,20 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_173_ || _zz_174_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_258_)begin + if(_zz_218)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3757,28 +2789,25 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_258_)begin + if(_zz_218)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if((_zz_243_ && (! dataCache_1__io_cpu_flush_ready)))begin - execute_arbitration_haltItself = 1'b1; - end - if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + if(((_zz_203 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_259_)begin + if(_zz_219)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_248_)begin + if(_zz_208)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3787,7 +2816,10 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_260_)begin + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_220)begin execute_arbitration_haltByOther = 1'b1; end end @@ -3804,8 +2836,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_260_)begin - if(_zz_261_)begin + if(_zz_220)begin + if(_zz_221)begin execute_arbitration_flushIt = 1'b1; end end @@ -3816,8 +2848,8 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_260_)begin - if(_zz_261_)begin + if(_zz_220)begin + if(_zz_221)begin execute_arbitration_flushNext = 1'b1; end end @@ -3825,8 +2857,8 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_253_)begin - if(_zz_262_)begin + if(_zz_213)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end end @@ -3856,7 +2888,7 @@ module VexRiscv ( always @ (*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1__io_cpu_writeBack_haltIt)begin + if(dataCache_1_io_cpu_writeBack_haltIt)begin writeBack_arbitration_haltItself = 1'b1; end end @@ -3887,10 +2919,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_263_)begin + if(_zz_222)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_264_)begin + if(_zz_223)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3901,74 +2933,73 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_263_)begin + if(_zz_222)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_264_)begin + if(_zz_223)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_260_)begin - if(_zz_261_)begin + if(_zz_220)begin + if(_zz_221)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_265_)begin + if(_zz_224)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; end - if(_zz_260_)begin - if(_zz_261_)begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end + end + + always @ (*) begin + _zz_54 = 1'b0; + if(DebugPlugin_godmode)begin + _zz_54 = 1'b1; end end always @ (*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin - IBusCachedPlugin_incomingInstruction = 1'b1; + CsrPlugin_inWfi = 1'b0; + if(_zz_219)begin + CsrPlugin_inWfi = 1'b1; end end always @ (*) begin - _zz_103_ = 1'b0; - if(DebugPlugin_godmode)begin - _zz_103_ = 1'b1; + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_263_)begin + if(_zz_222)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_264_)begin + if(_zz_223)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_263_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_222)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_264_)begin - case(_zz_266_) + if(_zz_223)begin + case(_zz_225) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3999,21 +3030,25 @@ module VexRiscv ( end end - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); - assign _zz_104_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_105_ = (_zz_104_ & (~ _zz_289_)); - assign _zz_106_ = _zz_105_[3]; - assign _zz_107_ = _zz_105_[4]; - assign _zz_108_ = (_zz_105_[1] || _zz_106_); - assign _zz_109_ = (_zz_105_[2] || _zz_106_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247_; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_55 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_56 = (_zz_55 & (~ _zz_279)); + assign _zz_57 = _zz_56[3]; + assign _zz_58 = (_zz_56[1] || _zz_57); + assign _zz_59 = (_zz_56[2] || _zz_57); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_207; always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin @@ -4022,7 +3057,10 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_291_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_281); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end @@ -4030,12 +3068,28 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin @@ -4043,41 +3097,44 @@ module VexRiscv ( end end - assign _zz_110_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_110_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_110_); + assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_60); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + if(IBusCachedPlugin_mmuBus_busy)begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_111_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_111_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_111_); + assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_61); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_112_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_112_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_112_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_113_; - assign _zz_113_ = ((1'b0 && (! _zz_114_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_114_ = _zz_115_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_114_; + assign _zz_62 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_62); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_62); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_63; + assign _zz_63 = ((1'b0 && (! _zz_64)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_64 = _zz_65; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_64; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_116_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_116_ = _zz_117_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_116_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_118_; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_66)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_66 = _zz_67; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_66; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_68; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -4089,149 +3146,140 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin - decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - case(_zz_216_) - 3'b000 : begin - end - 3'b001 : begin - end + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_144) 3'b010 : begin decode_arbitration_isValid = 1'b1; end 3'b011 : begin decode_arbitration_isValid = 1'b1; end - 3'b100 : begin - end default : begin end endcase end - assign _zz_102_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - assign _zz_101_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - assign _zz_100_ = (decode_PC + (32'b00000000000000000000000000000100)); - assign _zz_119_ = _zz_292_[11]; - always @ (*) begin - _zz_120_[18] = _zz_119_; - _zz_120_[17] = _zz_119_; - _zz_120_[16] = _zz_119_; - _zz_120_[15] = _zz_119_; - _zz_120_[14] = _zz_119_; - _zz_120_[13] = _zz_119_; - _zz_120_[12] = _zz_119_; - _zz_120_[11] = _zz_119_; - _zz_120_[10] = _zz_119_; - _zz_120_[9] = _zz_119_; - _zz_120_[8] = _zz_119_; - _zz_120_[7] = _zz_119_; - _zz_120_[6] = _zz_119_; - _zz_120_[5] = _zz_119_; - _zz_120_[4] = _zz_119_; - _zz_120_[3] = _zz_119_; - _zz_120_[2] = _zz_119_; - _zz_120_[1] = _zz_119_; - _zz_120_[0] = _zz_119_; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_293_[31])); - if(_zz_125_)begin + assign _zz_69 = _zz_282[11]; + always @ (*) begin + _zz_70[18] = _zz_69; + _zz_70[17] = _zz_69; + _zz_70[16] = _zz_69; + _zz_70[15] = _zz_69; + _zz_70[14] = _zz_69; + _zz_70[13] = _zz_69; + _zz_70[12] = _zz_69; + _zz_70[11] = _zz_69; + _zz_70[10] = _zz_69; + _zz_70[9] = _zz_69; + _zz_70[8] = _zz_69; + _zz_70[7] = _zz_69; + _zz_70[6] = _zz_69; + _zz_70[5] = _zz_69; + _zz_70[4] = _zz_69; + _zz_70[3] = _zz_69; + _zz_70[2] = _zz_69; + _zz_70[1] = _zz_69; + _zz_70[0] = _zz_69; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_283[31])); + if(_zz_75)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_121_ = _zz_294_[19]; + assign _zz_71 = _zz_284[19]; always @ (*) begin - _zz_122_[10] = _zz_121_; - _zz_122_[9] = _zz_121_; - _zz_122_[8] = _zz_121_; - _zz_122_[7] = _zz_121_; - _zz_122_[6] = _zz_121_; - _zz_122_[5] = _zz_121_; - _zz_122_[4] = _zz_121_; - _zz_122_[3] = _zz_121_; - _zz_122_[2] = _zz_121_; - _zz_122_[1] = _zz_121_; - _zz_122_[0] = _zz_121_; + _zz_72[10] = _zz_71; + _zz_72[9] = _zz_71; + _zz_72[8] = _zz_71; + _zz_72[7] = _zz_71; + _zz_72[6] = _zz_71; + _zz_72[5] = _zz_71; + _zz_72[4] = _zz_71; + _zz_72[3] = _zz_71; + _zz_72[2] = _zz_71; + _zz_72[1] = _zz_71; + _zz_72[0] = _zz_71; end - assign _zz_123_ = _zz_295_[11]; + assign _zz_73 = _zz_285[11]; always @ (*) begin - _zz_124_[18] = _zz_123_; - _zz_124_[17] = _zz_123_; - _zz_124_[16] = _zz_123_; - _zz_124_[15] = _zz_123_; - _zz_124_[14] = _zz_123_; - _zz_124_[13] = _zz_123_; - _zz_124_[12] = _zz_123_; - _zz_124_[11] = _zz_123_; - _zz_124_[10] = _zz_123_; - _zz_124_[9] = _zz_123_; - _zz_124_[8] = _zz_123_; - _zz_124_[7] = _zz_123_; - _zz_124_[6] = _zz_123_; - _zz_124_[5] = _zz_123_; - _zz_124_[4] = _zz_123_; - _zz_124_[3] = _zz_123_; - _zz_124_[2] = _zz_123_; - _zz_124_[1] = _zz_123_; - _zz_124_[0] = _zz_123_; + _zz_74[18] = _zz_73; + _zz_74[17] = _zz_73; + _zz_74[16] = _zz_73; + _zz_74[15] = _zz_73; + _zz_74[14] = _zz_73; + _zz_74[13] = _zz_73; + _zz_74[12] = _zz_73; + _zz_74[11] = _zz_73; + _zz_74[10] = _zz_73; + _zz_74[9] = _zz_73; + _zz_74[8] = _zz_73; + _zz_74[7] = _zz_73; + _zz_74[6] = _zz_73; + _zz_74[5] = _zz_73; + _zz_74[4] = _zz_73; + _zz_74[3] = _zz_73; + _zz_74[2] = _zz_73; + _zz_74[1] = _zz_73; + _zz_74[0] = _zz_73; end always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_125_ = _zz_296_[1]; + _zz_75 = _zz_286[1]; end default : begin - _zz_125_ = _zz_297_[1]; + _zz_75 = _zz_287[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_126_ = _zz_298_[19]; - always @ (*) begin - _zz_127_[10] = _zz_126_; - _zz_127_[9] = _zz_126_; - _zz_127_[8] = _zz_126_; - _zz_127_[7] = _zz_126_; - _zz_127_[6] = _zz_126_; - _zz_127_[5] = _zz_126_; - _zz_127_[4] = _zz_126_; - _zz_127_[3] = _zz_126_; - _zz_127_[2] = _zz_126_; - _zz_127_[1] = _zz_126_; - _zz_127_[0] = _zz_126_; - end - - assign _zz_128_ = _zz_299_[11]; - always @ (*) begin - _zz_129_[18] = _zz_128_; - _zz_129_[17] = _zz_128_; - _zz_129_[16] = _zz_128_; - _zz_129_[15] = _zz_128_; - _zz_129_[14] = _zz_128_; - _zz_129_[13] = _zz_128_; - _zz_129_[12] = _zz_128_; - _zz_129_[11] = _zz_128_; - _zz_129_[10] = _zz_128_; - _zz_129_[9] = _zz_128_; - _zz_129_[8] = _zz_128_; - _zz_129_[7] = _zz_128_; - _zz_129_[6] = _zz_128_; - _zz_129_[5] = _zz_128_; - _zz_129_[4] = _zz_128_; - _zz_129_[3] = _zz_128_; - _zz_129_[2] = _zz_128_; - _zz_129_[1] = _zz_128_; - _zz_129_[0] = _zz_128_; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_127_,{{{_zz_386_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_129_,{{{_zz_387_,_zz_388_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_76 = _zz_288[19]; + always @ (*) begin + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7] = _zz_76; + _zz_77[6] = _zz_76; + _zz_77[5] = _zz_76; + _zz_77[4] = _zz_76; + _zz_77[3] = _zz_76; + _zz_77[2] = _zz_76; + _zz_77[1] = _zz_76; + _zz_77[0] = _zz_76; + end + + assign _zz_78 = _zz_289[11]; + always @ (*) begin + _zz_79[18] = _zz_78; + _zz_79[17] = _zz_78; + _zz_79[16] = _zz_78; + _zz_79[15] = _zz_78; + _zz_79[14] = _zz_78; + _zz_79[13] = _zz_78; + _zz_79[12] = _zz_78; + _zz_79[11] = _zz_78; + _zz_79[10] = _zz_78; + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7] = _zz_78; + _zz_79[6] = _zz_78; + _zz_79[5] = _zz_78; + _zz_79[4] = _zz_78; + _zz_79[3] = _zz_78; + _zz_79[2] = _zz_78; + _zz_79[1] = _zz_78; + _zz_79[0] = _zz_78; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_77,{{{_zz_364,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_79,{{{_zz_365,_zz_366},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -4240,133 +3288,128 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_227_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_230_ = (32'b00000000000000000000000000000000); - assign _zz_228_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_229_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_231_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_232_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_233_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_96_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign _zz_178 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_179 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_180 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_179; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_182 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_183 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_184 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_257_)begin + if(_zz_217)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_255_)begin + if(_zz_215)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_267_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - end end always @ (*) begin - _zz_234_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_255_)begin - _zz_234_ = 1'b1; - end - if(_zz_267_)begin - _zz_234_ = 1'b0; + _zz_185 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_215)begin + _zz_185 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_256_)begin + if(_zz_216)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_254_)begin + if(_zz_214)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_256_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); - end - if(_zz_254_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_226_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_131_); - assign _zz_244_ = (! _zz_131_); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_131_ ? _zz_132_ : dataCache_1__io_mem_cmd_payload_wr); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_131_ ? _zz_133_ : dataCache_1__io_mem_cmd_payload_address); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_131_ ? _zz_134_ : dataCache_1__io_mem_cmd_payload_data); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_131_ ? _zz_135_ : dataCache_1__io_mem_cmd_payload_mask); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_131_ ? _zz_136_ : dataCache_1__io_mem_cmd_payload_length); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_131_ ? _zz_137_ : dataCache_1__io_mem_cmd_payload_last); - assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_138_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_139_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_140_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_141_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_142_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_143_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_144_; - assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_216)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_214)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_177 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_204 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_235_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_236_ = execute_SRC_ADD; + assign _zz_186 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_187 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_146_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_82 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_146_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_82 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_146_ = execute_RS2[31 : 0]; + _zz_82 = execute_RS2[31 : 0]; end endcase end - assign _zz_243_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_92_ = _zz_236_[1 : 0]; - assign _zz_237_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_238_ = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + assign _zz_203 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_188 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_189 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_188; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_189; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_239_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_103_ && (! dataCache_1__io_cpu_memory_isWrite)))begin - _zz_239_ = 1'b1; + _zz_190 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_54 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_190 = 1'b1; end end - assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; - assign _zz_240_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_241_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_242_ = writeBack_REGFILE_WRITE_DATA; + assign _zz_191 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_192 = (CsrPlugin_privilege == 2'b00); + assign _zz_193 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_268_)begin - if(dataCache_1__io_cpu_redo)begin + if(_zz_226)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end @@ -4375,17 +3418,17 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_268_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin + if(_zz_226)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_redo)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end @@ -4393,94 +3436,94 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); - if(_zz_268_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_300_}; + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_226)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_290}; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_301_}; + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1__io_cpu_writeBack_mmuException)begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_291}; end end end always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; end 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; end 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; end default : begin end endcase end - assign _zz_147_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_148_[31] = _zz_147_; - _zz_148_[30] = _zz_147_; - _zz_148_[29] = _zz_147_; - _zz_148_[28] = _zz_147_; - _zz_148_[27] = _zz_147_; - _zz_148_[26] = _zz_147_; - _zz_148_[25] = _zz_147_; - _zz_148_[24] = _zz_147_; - _zz_148_[23] = _zz_147_; - _zz_148_[22] = _zz_147_; - _zz_148_[21] = _zz_147_; - _zz_148_[20] = _zz_147_; - _zz_148_[19] = _zz_147_; - _zz_148_[18] = _zz_147_; - _zz_148_[17] = _zz_147_; - _zz_148_[16] = _zz_147_; - _zz_148_[15] = _zz_147_; - _zz_148_[14] = _zz_147_; - _zz_148_[13] = _zz_147_; - _zz_148_[12] = _zz_147_; - _zz_148_[11] = _zz_147_; - _zz_148_[10] = _zz_147_; - _zz_148_[9] = _zz_147_; - _zz_148_[8] = _zz_147_; - _zz_148_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_149_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_150_[31] = _zz_149_; - _zz_150_[30] = _zz_149_; - _zz_150_[29] = _zz_149_; - _zz_150_[28] = _zz_149_; - _zz_150_[27] = _zz_149_; - _zz_150_[26] = _zz_149_; - _zz_150_[25] = _zz_149_; - _zz_150_[24] = _zz_149_; - _zz_150_[23] = _zz_149_; - _zz_150_[22] = _zz_149_; - _zz_150_[21] = _zz_149_; - _zz_150_[20] = _zz_149_; - _zz_150_[19] = _zz_149_; - _zz_150_[18] = _zz_149_; - _zz_150_[17] = _zz_149_; - _zz_150_[16] = _zz_149_; - _zz_150_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_286_) + assign _zz_83 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_84[31] = _zz_83; + _zz_84[30] = _zz_83; + _zz_84[29] = _zz_83; + _zz_84[28] = _zz_83; + _zz_84[27] = _zz_83; + _zz_84[26] = _zz_83; + _zz_84[25] = _zz_83; + _zz_84[24] = _zz_83; + _zz_84[23] = _zz_83; + _zz_84[22] = _zz_83; + _zz_84[21] = _zz_83; + _zz_84[20] = _zz_83; + _zz_84[19] = _zz_83; + _zz_84[18] = _zz_83; + _zz_84[17] = _zz_83; + _zz_84[16] = _zz_83; + _zz_84[15] = _zz_83; + _zz_84[14] = _zz_83; + _zz_84[13] = _zz_83; + _zz_84[12] = _zz_83; + _zz_84[11] = _zz_83; + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_85 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_86[31] = _zz_85; + _zz_86[30] = _zz_85; + _zz_86[29] = _zz_85; + _zz_86[28] = _zz_85; + _zz_86[27] = _zz_85; + _zz_86[26] = _zz_85; + _zz_86[25] = _zz_85; + _zz_86[24] = _zz_85; + _zz_86[23] = _zz_85; + _zz_86[22] = _zz_85; + _zz_86[21] = _zz_85; + _zz_86[20] = _zz_85; + _zz_86[19] = _zz_85; + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_246) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_148_; + writeBack_DBusCachedPlugin_rspFormated = _zz_84; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_150_; + writeBack_DBusCachedPlugin_rspFormated = _zz_86; end default : begin writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; @@ -4488,78 +3531,71 @@ module VexRiscv ( endcase end - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_152_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); - assign _zz_153_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_154_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_155_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_151_ = {(((decode_INSTRUCTION & _zz_389_) == (32'b00000000000000000000000000100100)) != (1'b0)),{({_zz_390_,{_zz_391_,_zz_392_}} != (5'b00000)),{(_zz_393_ != (1'b0)),{(_zz_394_ != _zz_395_),{_zz_396_,{_zz_397_,_zz_398_}}}}}}; - assign _zz_90_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_553_) == (32'b00000000000000000001000001110011)),{(_zz_554_ == _zz_555_),{_zz_556_,{_zz_557_,_zz_558_}}}}}}} != (21'b000000000000000000000)); - assign _zz_89_ = _zz_302_[0]; - assign _zz_88_ = _zz_303_[0]; - assign _zz_87_ = _zz_304_[0]; - assign _zz_86_ = _zz_305_[0]; - assign _zz_156_ = _zz_151_[5 : 4]; - assign _zz_85_ = _zz_156_; - assign _zz_157_ = _zz_151_[7 : 6]; - assign _zz_84_ = _zz_157_; - assign _zz_158_ = _zz_151_[9 : 8]; - assign _zz_83_ = _zz_158_; - assign _zz_82_ = _zz_306_[0]; - assign _zz_81_ = _zz_307_[0]; - assign _zz_159_ = _zz_151_[13 : 12]; - assign _zz_80_ = _zz_159_; - assign _zz_79_ = _zz_308_[0]; - assign _zz_78_ = _zz_309_[0]; - assign _zz_77_ = _zz_310_[0]; - assign _zz_76_ = _zz_311_[0]; - assign _zz_75_ = _zz_312_[0]; - assign _zz_74_ = _zz_313_[0]; - assign _zz_73_ = _zz_314_[0]; - assign _zz_72_ = _zz_315_[0]; - assign _zz_71_ = _zz_316_[0]; - assign _zz_160_ = _zz_151_[24 : 23]; - assign _zz_70_ = _zz_160_; - assign _zz_69_ = _zz_317_[0]; - assign _zz_161_ = _zz_151_[27 : 26]; - assign _zz_68_ = _zz_161_; - assign _zz_67_ = _zz_318_[0]; - assign _zz_162_ = _zz_151_[30 : 29]; - assign _zz_66_ = _zz_162_; - assign _zz_65_ = _zz_319_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign _zz_88 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_89 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_90 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_91 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_87 = {(((decode_INSTRUCTION & _zz_367) == 32'h00100050) != 1'b0),{(_zz_91 != 1'b0),{(_zz_91 != 1'b0),{(_zz_368 != _zz_369),{_zz_370,{_zz_371,_zz_372}}}}}}; + assign _zz_92 = _zz_87[2 : 1]; + assign _zz_49 = _zz_92; + assign _zz_93 = _zz_87[7 : 6]; + assign _zz_48 = _zz_93; + assign _zz_94 = _zz_87[9 : 8]; + assign _zz_47 = _zz_94; + assign _zz_95 = _zz_87[19 : 18]; + assign _zz_46 = _zz_95; + assign _zz_96 = _zz_87[22 : 21]; + assign _zz_45 = _zz_96; + assign _zz_97 = _zz_87[24 : 23]; + assign _zz_44 = _zz_97; + assign _zz_98 = _zz_87[27 : 26]; + assign _zz_43 = _zz_98; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_245_; - assign decode_RegFilePlugin_rs2Data = _zz_246_; - assign _zz_64_ = decode_RegFilePlugin_rs1Data; - assign _zz_63_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_205; + assign decode_RegFilePlugin_rs2Data = _zz_206; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_61_ && writeBack_arbitration_isFiring); - if(_zz_163_)begin + lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); + if(_zz_99)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_60_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_91_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; + if(_zz_99)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_50; + if(_zz_99)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -4577,361 +3613,354 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_164_ = execute_IntAluPlugin_bitwise; + _zz_100 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_164_ = {31'd0, _zz_320_}; + _zz_100 = {31'd0, _zz_292}; end default : begin - _zz_164_ = execute_SRC_ADD_SUB; + _zz_100 = execute_SRC_ADD_SUB; end endcase end - assign _zz_58_ = _zz_164_; - assign _zz_56_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_165_ = execute_RS1; + _zz_101 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_165_ = {29'd0, _zz_321_}; + _zz_101 = {29'd0, _zz_293}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_165_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_101 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_165_ = {27'd0, _zz_322_}; + _zz_101 = {27'd0, _zz_294}; end endcase end - assign _zz_55_ = _zz_165_; - assign _zz_166_ = _zz_323_[11]; - always @ (*) begin - _zz_167_[19] = _zz_166_; - _zz_167_[18] = _zz_166_; - _zz_167_[17] = _zz_166_; - _zz_167_[16] = _zz_166_; - _zz_167_[15] = _zz_166_; - _zz_167_[14] = _zz_166_; - _zz_167_[13] = _zz_166_; - _zz_167_[12] = _zz_166_; - _zz_167_[11] = _zz_166_; - _zz_167_[10] = _zz_166_; - _zz_167_[9] = _zz_166_; - _zz_167_[8] = _zz_166_; - _zz_167_[7] = _zz_166_; - _zz_167_[6] = _zz_166_; - _zz_167_[5] = _zz_166_; - _zz_167_[4] = _zz_166_; - _zz_167_[3] = _zz_166_; - _zz_167_[2] = _zz_166_; - _zz_167_[1] = _zz_166_; - _zz_167_[0] = _zz_166_; - end - - assign _zz_168_ = _zz_324_[11]; - always @ (*) begin - _zz_169_[19] = _zz_168_; - _zz_169_[18] = _zz_168_; - _zz_169_[17] = _zz_168_; - _zz_169_[16] = _zz_168_; - _zz_169_[15] = _zz_168_; - _zz_169_[14] = _zz_168_; - _zz_169_[13] = _zz_168_; - _zz_169_[12] = _zz_168_; - _zz_169_[11] = _zz_168_; - _zz_169_[10] = _zz_168_; - _zz_169_[9] = _zz_168_; - _zz_169_[8] = _zz_168_; - _zz_169_[7] = _zz_168_; - _zz_169_[6] = _zz_168_; - _zz_169_[5] = _zz_168_; - _zz_169_[4] = _zz_168_; - _zz_169_[3] = _zz_168_; - _zz_169_[2] = _zz_168_; - _zz_169_[1] = _zz_168_; - _zz_169_[0] = _zz_168_; + assign _zz_102 = _zz_295[11]; + always @ (*) begin + _zz_103[19] = _zz_102; + _zz_103[18] = _zz_102; + _zz_103[17] = _zz_102; + _zz_103[16] = _zz_102; + _zz_103[15] = _zz_102; + _zz_103[14] = _zz_102; + _zz_103[13] = _zz_102; + _zz_103[12] = _zz_102; + _zz_103[11] = _zz_102; + _zz_103[10] = _zz_102; + _zz_103[9] = _zz_102; + _zz_103[8] = _zz_102; + _zz_103[7] = _zz_102; + _zz_103[6] = _zz_102; + _zz_103[5] = _zz_102; + _zz_103[4] = _zz_102; + _zz_103[3] = _zz_102; + _zz_103[2] = _zz_102; + _zz_103[1] = _zz_102; + _zz_103[0] = _zz_102; + end + + assign _zz_104 = _zz_296[11]; + always @ (*) begin + _zz_105[19] = _zz_104; + _zz_105[18] = _zz_104; + _zz_105[17] = _zz_104; + _zz_105[16] = _zz_104; + _zz_105[15] = _zz_104; + _zz_105[14] = _zz_104; + _zz_105[13] = _zz_104; + _zz_105[12] = _zz_104; + _zz_105[11] = _zz_104; + _zz_105[10] = _zz_104; + _zz_105[9] = _zz_104; + _zz_105[8] = _zz_104; + _zz_105[7] = _zz_104; + _zz_105[6] = _zz_104; + _zz_105[5] = _zz_104; + _zz_105[4] = _zz_104; + _zz_105[3] = _zz_104; + _zz_105[2] = _zz_104; + _zz_105[1] = _zz_104; + _zz_105[0] = _zz_104; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_170_ = execute_RS2; + _zz_106 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_170_ = {_zz_167_,execute_INSTRUCTION[31 : 20]}; + _zz_106 = {_zz_103,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_170_ = {_zz_169_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_106 = {_zz_105,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_170_ = _zz_51_; + _zz_106 = _zz_35; end endcase end - assign _zz_53_ = _zz_170_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_325_; + execute_SrcPlugin_addSub = _zz_297; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_50_ = execute_SrcPlugin_addSub; - assign _zz_49_ = execute_SrcPlugin_addSub; - assign _zz_48_ = execute_SrcPlugin_less; assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_171_[0] = execute_SRC1[31]; - _zz_171_[1] = execute_SRC1[30]; - _zz_171_[2] = execute_SRC1[29]; - _zz_171_[3] = execute_SRC1[28]; - _zz_171_[4] = execute_SRC1[27]; - _zz_171_[5] = execute_SRC1[26]; - _zz_171_[6] = execute_SRC1[25]; - _zz_171_[7] = execute_SRC1[24]; - _zz_171_[8] = execute_SRC1[23]; - _zz_171_[9] = execute_SRC1[22]; - _zz_171_[10] = execute_SRC1[21]; - _zz_171_[11] = execute_SRC1[20]; - _zz_171_[12] = execute_SRC1[19]; - _zz_171_[13] = execute_SRC1[18]; - _zz_171_[14] = execute_SRC1[17]; - _zz_171_[15] = execute_SRC1[16]; - _zz_171_[16] = execute_SRC1[15]; - _zz_171_[17] = execute_SRC1[14]; - _zz_171_[18] = execute_SRC1[13]; - _zz_171_[19] = execute_SRC1[12]; - _zz_171_[20] = execute_SRC1[11]; - _zz_171_[21] = execute_SRC1[10]; - _zz_171_[22] = execute_SRC1[9]; - _zz_171_[23] = execute_SRC1[8]; - _zz_171_[24] = execute_SRC1[7]; - _zz_171_[25] = execute_SRC1[6]; - _zz_171_[26] = execute_SRC1[5]; - _zz_171_[27] = execute_SRC1[4]; - _zz_171_[28] = execute_SRC1[3]; - _zz_171_[29] = execute_SRC1[2]; - _zz_171_[30] = execute_SRC1[1]; - _zz_171_[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_171_ : execute_SRC1); - assign _zz_46_ = _zz_333_; - always @ (*) begin - _zz_172_[0] = memory_SHIFT_RIGHT[31]; - _zz_172_[1] = memory_SHIFT_RIGHT[30]; - _zz_172_[2] = memory_SHIFT_RIGHT[29]; - _zz_172_[3] = memory_SHIFT_RIGHT[28]; - _zz_172_[4] = memory_SHIFT_RIGHT[27]; - _zz_172_[5] = memory_SHIFT_RIGHT[26]; - _zz_172_[6] = memory_SHIFT_RIGHT[25]; - _zz_172_[7] = memory_SHIFT_RIGHT[24]; - _zz_172_[8] = memory_SHIFT_RIGHT[23]; - _zz_172_[9] = memory_SHIFT_RIGHT[22]; - _zz_172_[10] = memory_SHIFT_RIGHT[21]; - _zz_172_[11] = memory_SHIFT_RIGHT[20]; - _zz_172_[12] = memory_SHIFT_RIGHT[19]; - _zz_172_[13] = memory_SHIFT_RIGHT[18]; - _zz_172_[14] = memory_SHIFT_RIGHT[17]; - _zz_172_[15] = memory_SHIFT_RIGHT[16]; - _zz_172_[16] = memory_SHIFT_RIGHT[15]; - _zz_172_[17] = memory_SHIFT_RIGHT[14]; - _zz_172_[18] = memory_SHIFT_RIGHT[13]; - _zz_172_[19] = memory_SHIFT_RIGHT[12]; - _zz_172_[20] = memory_SHIFT_RIGHT[11]; - _zz_172_[21] = memory_SHIFT_RIGHT[10]; - _zz_172_[22] = memory_SHIFT_RIGHT[9]; - _zz_172_[23] = memory_SHIFT_RIGHT[8]; - _zz_172_[24] = memory_SHIFT_RIGHT[7]; - _zz_172_[25] = memory_SHIFT_RIGHT[6]; - _zz_172_[26] = memory_SHIFT_RIGHT[5]; - _zz_172_[27] = memory_SHIFT_RIGHT[4]; - _zz_172_[28] = memory_SHIFT_RIGHT[3]; - _zz_172_[29] = memory_SHIFT_RIGHT[2]; - _zz_172_[30] = memory_SHIFT_RIGHT[1]; - _zz_172_[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_173_ = 1'b0; - if(_zz_269_)begin - if(_zz_270_)begin - if(_zz_179_)begin - _zz_173_ = 1'b1; + _zz_107[0] = execute_SRC1[31]; + _zz_107[1] = execute_SRC1[30]; + _zz_107[2] = execute_SRC1[29]; + _zz_107[3] = execute_SRC1[28]; + _zz_107[4] = execute_SRC1[27]; + _zz_107[5] = execute_SRC1[26]; + _zz_107[6] = execute_SRC1[25]; + _zz_107[7] = execute_SRC1[24]; + _zz_107[8] = execute_SRC1[23]; + _zz_107[9] = execute_SRC1[22]; + _zz_107[10] = execute_SRC1[21]; + _zz_107[11] = execute_SRC1[20]; + _zz_107[12] = execute_SRC1[19]; + _zz_107[13] = execute_SRC1[18]; + _zz_107[14] = execute_SRC1[17]; + _zz_107[15] = execute_SRC1[16]; + _zz_107[16] = execute_SRC1[15]; + _zz_107[17] = execute_SRC1[14]; + _zz_107[18] = execute_SRC1[13]; + _zz_107[19] = execute_SRC1[12]; + _zz_107[20] = execute_SRC1[11]; + _zz_107[21] = execute_SRC1[10]; + _zz_107[22] = execute_SRC1[9]; + _zz_107[23] = execute_SRC1[8]; + _zz_107[24] = execute_SRC1[7]; + _zz_107[25] = execute_SRC1[6]; + _zz_107[26] = execute_SRC1[5]; + _zz_107[27] = execute_SRC1[4]; + _zz_107[28] = execute_SRC1[3]; + _zz_107[29] = execute_SRC1[2]; + _zz_107[30] = execute_SRC1[1]; + _zz_107[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_107 : execute_SRC1); + always @ (*) begin + _zz_108[0] = memory_SHIFT_RIGHT[31]; + _zz_108[1] = memory_SHIFT_RIGHT[30]; + _zz_108[2] = memory_SHIFT_RIGHT[29]; + _zz_108[3] = memory_SHIFT_RIGHT[28]; + _zz_108[4] = memory_SHIFT_RIGHT[27]; + _zz_108[5] = memory_SHIFT_RIGHT[26]; + _zz_108[6] = memory_SHIFT_RIGHT[25]; + _zz_108[7] = memory_SHIFT_RIGHT[24]; + _zz_108[8] = memory_SHIFT_RIGHT[23]; + _zz_108[9] = memory_SHIFT_RIGHT[22]; + _zz_108[10] = memory_SHIFT_RIGHT[21]; + _zz_108[11] = memory_SHIFT_RIGHT[20]; + _zz_108[12] = memory_SHIFT_RIGHT[19]; + _zz_108[13] = memory_SHIFT_RIGHT[18]; + _zz_108[14] = memory_SHIFT_RIGHT[17]; + _zz_108[15] = memory_SHIFT_RIGHT[16]; + _zz_108[16] = memory_SHIFT_RIGHT[15]; + _zz_108[17] = memory_SHIFT_RIGHT[14]; + _zz_108[18] = memory_SHIFT_RIGHT[13]; + _zz_108[19] = memory_SHIFT_RIGHT[12]; + _zz_108[20] = memory_SHIFT_RIGHT[11]; + _zz_108[21] = memory_SHIFT_RIGHT[10]; + _zz_108[22] = memory_SHIFT_RIGHT[9]; + _zz_108[23] = memory_SHIFT_RIGHT[8]; + _zz_108[24] = memory_SHIFT_RIGHT[7]; + _zz_108[25] = memory_SHIFT_RIGHT[6]; + _zz_108[26] = memory_SHIFT_RIGHT[5]; + _zz_108[27] = memory_SHIFT_RIGHT[4]; + _zz_108[28] = memory_SHIFT_RIGHT[3]; + _zz_108[29] = memory_SHIFT_RIGHT[2]; + _zz_108[30] = memory_SHIFT_RIGHT[1]; + _zz_108[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_227)begin + if(_zz_228)begin + if(_zz_109)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_271_)begin - if(_zz_272_)begin - if(_zz_181_)begin - _zz_173_ = 1'b1; + if(_zz_229)begin + if(_zz_230)begin + if(_zz_111)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_273_)begin - if(_zz_274_)begin - if(_zz_183_)begin - _zz_173_ = 1'b1; + if(_zz_231)begin + if(_zz_232)begin + if(_zz_113)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_173_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_174_ = 1'b0; - if(_zz_269_)begin - if(_zz_270_)begin - if(_zz_180_)begin - _zz_174_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_227)begin + if(_zz_228)begin + if(_zz_110)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_271_)begin - if(_zz_272_)begin - if(_zz_182_)begin - _zz_174_ = 1'b1; + if(_zz_229)begin + if(_zz_230)begin + if(_zz_112)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_273_)begin - if(_zz_274_)begin - if(_zz_184_)begin - _zz_174_ = 1'b1; + if(_zz_231)begin + if(_zz_232)begin + if(_zz_114)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_174_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_175_ = (_zz_61_ && writeBack_arbitration_isFiring); - assign _zz_179_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_180_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_181_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_182_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_183_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_184_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_42_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_109 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_110 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_111 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_112 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_113 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_114 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_185_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_185_ == (3'b000))) begin - _zz_186_ = execute_BranchPlugin_eq; - end else if((_zz_185_ == (3'b001))) begin - _zz_186_ = (! execute_BranchPlugin_eq); - end else if((((_zz_185_ & (3'b101)) == (3'b101)))) begin - _zz_186_ = (! execute_SRC_LESS); + assign _zz_115 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_115 == 3'b000)) begin + _zz_116 = execute_BranchPlugin_eq; + end else if((_zz_115 == 3'b001)) begin + _zz_116 = (! execute_BranchPlugin_eq); + end else if((((_zz_115 & 3'b101) == 3'b101))) begin + _zz_116 = (! execute_SRC_LESS); end else begin - _zz_186_ = execute_SRC_LESS; + _zz_116 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_187_ = 1'b0; + _zz_117 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_187_ = 1'b1; + _zz_117 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_187_ = 1'b1; + _zz_117 = 1'b1; end default : begin - _zz_187_ = _zz_186_; + _zz_117 = _zz_116; end endcase end - assign _zz_41_ = _zz_187_; - assign _zz_188_ = _zz_335_[11]; - always @ (*) begin - _zz_189_[19] = _zz_188_; - _zz_189_[18] = _zz_188_; - _zz_189_[17] = _zz_188_; - _zz_189_[16] = _zz_188_; - _zz_189_[15] = _zz_188_; - _zz_189_[14] = _zz_188_; - _zz_189_[13] = _zz_188_; - _zz_189_[12] = _zz_188_; - _zz_189_[11] = _zz_188_; - _zz_189_[10] = _zz_188_; - _zz_189_[9] = _zz_188_; - _zz_189_[8] = _zz_188_; - _zz_189_[7] = _zz_188_; - _zz_189_[6] = _zz_188_; - _zz_189_[5] = _zz_188_; - _zz_189_[4] = _zz_188_; - _zz_189_[3] = _zz_188_; - _zz_189_[2] = _zz_188_; - _zz_189_[1] = _zz_188_; - _zz_189_[0] = _zz_188_; - end - - assign _zz_190_ = _zz_336_[19]; - always @ (*) begin - _zz_191_[10] = _zz_190_; - _zz_191_[9] = _zz_190_; - _zz_191_[8] = _zz_190_; - _zz_191_[7] = _zz_190_; - _zz_191_[6] = _zz_190_; - _zz_191_[5] = _zz_190_; - _zz_191_[4] = _zz_190_; - _zz_191_[3] = _zz_190_; - _zz_191_[2] = _zz_190_; - _zz_191_[1] = _zz_190_; - _zz_191_[0] = _zz_190_; - end - - assign _zz_192_ = _zz_337_[11]; - always @ (*) begin - _zz_193_[18] = _zz_192_; - _zz_193_[17] = _zz_192_; - _zz_193_[16] = _zz_192_; - _zz_193_[15] = _zz_192_; - _zz_193_[14] = _zz_192_; - _zz_193_[13] = _zz_192_; - _zz_193_[12] = _zz_192_; - _zz_193_[11] = _zz_192_; - _zz_193_[10] = _zz_192_; - _zz_193_[9] = _zz_192_; - _zz_193_[8] = _zz_192_; - _zz_193_[7] = _zz_192_; - _zz_193_[6] = _zz_192_; - _zz_193_[5] = _zz_192_; - _zz_193_[4] = _zz_192_; - _zz_193_[3] = _zz_192_; - _zz_193_[2] = _zz_192_; - _zz_193_[1] = _zz_192_; - _zz_193_[0] = _zz_192_; + assign _zz_118 = _zz_304[11]; + always @ (*) begin + _zz_119[19] = _zz_118; + _zz_119[18] = _zz_118; + _zz_119[17] = _zz_118; + _zz_119[16] = _zz_118; + _zz_119[15] = _zz_118; + _zz_119[14] = _zz_118; + _zz_119[13] = _zz_118; + _zz_119[12] = _zz_118; + _zz_119[11] = _zz_118; + _zz_119[10] = _zz_118; + _zz_119[9] = _zz_118; + _zz_119[8] = _zz_118; + _zz_119[7] = _zz_118; + _zz_119[6] = _zz_118; + _zz_119[5] = _zz_118; + _zz_119[4] = _zz_118; + _zz_119[3] = _zz_118; + _zz_119[2] = _zz_118; + _zz_119[1] = _zz_118; + _zz_119[0] = _zz_118; + end + + assign _zz_120 = _zz_305[19]; + always @ (*) begin + _zz_121[10] = _zz_120; + _zz_121[9] = _zz_120; + _zz_121[8] = _zz_120; + _zz_121[7] = _zz_120; + _zz_121[6] = _zz_120; + _zz_121[5] = _zz_120; + _zz_121[4] = _zz_120; + _zz_121[3] = _zz_120; + _zz_121[2] = _zz_120; + _zz_121[1] = _zz_120; + _zz_121[0] = _zz_120; + end + + assign _zz_122 = _zz_306[11]; + always @ (*) begin + _zz_123[18] = _zz_122; + _zz_123[17] = _zz_122; + _zz_123[16] = _zz_122; + _zz_123[15] = _zz_122; + _zz_123[14] = _zz_122; + _zz_123[13] = _zz_122; + _zz_123[12] = _zz_122; + _zz_123[11] = _zz_122; + _zz_123[10] = _zz_122; + _zz_123[9] = _zz_122; + _zz_123[8] = _zz_122; + _zz_123[7] = _zz_122; + _zz_123[6] = _zz_122; + _zz_123[5] = _zz_122; + _zz_123[4] = _zz_122; + _zz_123[3] = _zz_122; + _zz_123[2] = _zz_122; + _zz_123[1] = _zz_122; + _zz_123[0] = _zz_122; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_194_ = (_zz_338_[1] ^ execute_RS1[1]); + _zz_124 = (_zz_307[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_194_ = _zz_339_[1]; + _zz_124 = _zz_308[1]; end default : begin - _zz_194_ = _zz_340_[1]; + _zz_124 = _zz_309[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_194_); - assign _zz_39_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_124); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4943,107 +3972,106 @@ module VexRiscv ( endcase end - assign _zz_195_ = _zz_341_[11]; + assign _zz_125 = _zz_310[11]; always @ (*) begin - _zz_196_[19] = _zz_195_; - _zz_196_[18] = _zz_195_; - _zz_196_[17] = _zz_195_; - _zz_196_[16] = _zz_195_; - _zz_196_[15] = _zz_195_; - _zz_196_[14] = _zz_195_; - _zz_196_[13] = _zz_195_; - _zz_196_[12] = _zz_195_; - _zz_196_[11] = _zz_195_; - _zz_196_[10] = _zz_195_; - _zz_196_[9] = _zz_195_; - _zz_196_[8] = _zz_195_; - _zz_196_[7] = _zz_195_; - _zz_196_[6] = _zz_195_; - _zz_196_[5] = _zz_195_; - _zz_196_[4] = _zz_195_; - _zz_196_[3] = _zz_195_; - _zz_196_[2] = _zz_195_; - _zz_196_[1] = _zz_195_; - _zz_196_[0] = _zz_195_; + _zz_126[19] = _zz_125; + _zz_126[18] = _zz_125; + _zz_126[17] = _zz_125; + _zz_126[16] = _zz_125; + _zz_126[15] = _zz_125; + _zz_126[14] = _zz_125; + _zz_126[13] = _zz_125; + _zz_126[12] = _zz_125; + _zz_126[11] = _zz_125; + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_196_,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_126,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_198_,{{{_zz_571_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_200_,{{{_zz_572_,_zz_573_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_128,{{{_zz_531,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_130,{{{_zz_532,_zz_533},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_344_}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_313}; end end endcase end - assign _zz_197_ = _zz_342_[19]; - always @ (*) begin - _zz_198_[10] = _zz_197_; - _zz_198_[9] = _zz_197_; - _zz_198_[8] = _zz_197_; - _zz_198_[7] = _zz_197_; - _zz_198_[6] = _zz_197_; - _zz_198_[5] = _zz_197_; - _zz_198_[4] = _zz_197_; - _zz_198_[3] = _zz_197_; - _zz_198_[2] = _zz_197_; - _zz_198_[1] = _zz_197_; - _zz_198_[0] = _zz_197_; - end - - assign _zz_199_ = _zz_343_[11]; - always @ (*) begin - _zz_200_[18] = _zz_199_; - _zz_200_[17] = _zz_199_; - _zz_200_[16] = _zz_199_; - _zz_200_[15] = _zz_199_; - _zz_200_[14] = _zz_199_; - _zz_200_[13] = _zz_199_; - _zz_200_[12] = _zz_199_; - _zz_200_[11] = _zz_199_; - _zz_200_[10] = _zz_199_; - _zz_200_[9] = _zz_199_; - _zz_200_[8] = _zz_199_; - _zz_200_[7] = _zz_199_; - _zz_200_[6] = _zz_199_; - _zz_200_[5] = _zz_199_; - _zz_200_[4] = _zz_199_; - _zz_200_[3] = _zz_199_; - _zz_200_[2] = _zz_199_; - _zz_200_[1] = _zz_199_; - _zz_200_[0] = _zz_199_; + assign _zz_127 = _zz_311[19]; + always @ (*) begin + _zz_128[10] = _zz_127; + _zz_128[9] = _zz_127; + _zz_128[8] = _zz_127; + _zz_128[7] = _zz_127; + _zz_128[6] = _zz_127; + _zz_128[5] = _zz_127; + _zz_128[4] = _zz_127; + _zz_128[3] = _zz_127; + _zz_128[2] = _zz_127; + _zz_128[1] = _zz_127; + _zz_128[0] = _zz_127; + end + + assign _zz_129 = _zz_312[11]; + always @ (*) begin + _zz_130[18] = _zz_129; + _zz_130[17] = _zz_129; + _zz_130[16] = _zz_129; + _zz_130[15] = _zz_129; + _zz_130[14] = _zz_129; + _zz_130[13] = _zz_129; + _zz_130[12] = _zz_129; + _zz_130[11] = _zz_129; + _zz_130[10] = _zz_129; + _zz_130[9] = _zz_129; + _zz_130[8] = _zz_129; + _zz_130[7] = _zz_129; + _zz_130[6] = _zz_129; + _zz_130[5] = _zz_129; + _zz_130[4] = _zz_129; + _zz_130[3] = _zz_129; + _zz_130[2] = _zz_129; + _zz_130[1] = _zz_129; + _zz_130[0] = _zz_129; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_38_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign _zz_201_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_202_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_203_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign _zz_131 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_132 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_133 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_204_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_205_ = _zz_345_[0]; + assign _zz_134 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_135 = _zz_314[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_258_)begin + if(_zz_218)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -5086,9 +4114,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -5112,7 +4141,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; @@ -5123,7 +4152,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -5134,105 +4163,102 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_36_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_35_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - always @ (*) begin - execute_CsrPlugin_inWfi = 1'b0; - if(_zz_259_)begin - execute_CsrPlugin_inWfi = 1'b1; - end - end - - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b111100010001 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111100010100 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000001 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b101100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b101110000000 : begin + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110011000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b101100000010 : begin + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000011 : begin + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b110000000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000001 : begin + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000000 : begin + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b101110000010 : begin + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110010000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_233)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -5251,26 +4277,26 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_275_)begin + if(_zz_234)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_276_)begin + if(_zz_235)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_275_)begin - CsrPlugin_selfException_payload_code = (4'b0010); + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_234)begin + CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_276_)begin + if(_zz_235)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -5278,95 +4304,24 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_213_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b111100010001 : begin - execute_CsrPlugin_readData[3 : 0] = (4'b1011); - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b101100000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0]; - end - 12'b101110000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[63 : 32]; - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b001100000101 : begin - execute_CsrPlugin_readData[31 : 2] = CsrPlugin_mtvec_base; - execute_CsrPlugin_readData[1 : 0] = CsrPlugin_mtvec_mode; - end - 12'b110011000000 : begin - execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); - execute_CsrPlugin_readData[25 : 20] = (6'b100000); - end - 12'b101100000010 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[31 : 0]; - end - 12'b111100010011 : begin - execute_CsrPlugin_readData[5 : 0] = (6'b100001); - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_214_; - end - 12'b110000000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0]; - end - 12'b001100000001 : begin - execute_CsrPlugin_readData[31 : 30] = CsrPlugin_misa_base; - execute_CsrPlugin_readData[25 : 0] = CsrPlugin_misa_extensions; - end - 12'b001101000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; - end - 12'b111100010010 : begin - execute_CsrPlugin_readData[4 : 0] = (5'b10110); - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - end - 12'b101110000010 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[63 : 32]; - end - 12'b110010000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[63 : 32]; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_233)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_233)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_287_) + case(_zz_247) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -5377,10 +4332,10 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_MulPlugin_a = execute_SRC1; - assign execute_MulPlugin_b = execute_SRC2; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_277_) + case(_zz_236) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -5394,7 +4349,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_277_) + case(_zz_236) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -5413,16 +4368,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign _zz_32_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign _zz_31_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - assign _zz_30_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - assign _zz_28_ = ($signed(_zz_347_) + $signed(_zz_355_)); - assign writeBack_MulPlugin_result = ($signed(_zz_356_) + $signed(_zz_357_)); + assign writeBack_MulPlugin_result = ($signed(_zz_316) + $signed(_zz_317)); + assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_253_)begin - if(_zz_262_)begin + if(_zz_213)begin + if(_zz_237)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -5430,44 +4381,44 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_278_)begin + if(_zz_238)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end - assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); always @ (*) begin if(memory_DivPlugin_div_counter_willOverflow)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_361_); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_321); end if(memory_DivPlugin_div_counter_willClear)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_206_ = memory_DivPlugin_rs1[31 : 0]; - assign _zz_207_ = {memory_DivPlugin_accumulator[31 : 0],_zz_206_[31]}; - assign _zz_208_ = (_zz_207_ - _zz_362_); - assign _zz_209_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_210_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_211_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_136 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_136[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_322); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_323 : _zz_324); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_325[31:0]; + assign _zz_137 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_138 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_139 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_212_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_212_[31 : 0] = execute_RS1; + _zz_140[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_140[31 : 0] = execute_RS1; end - assign _zz_214_ = (_zz_213_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_214_ != (32'b00000000000000000000000000000000)); + assign _zz_142 = (_zz_141 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_142 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_279_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_239) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end @@ -5480,7 +4431,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_215_))begin + if((! _zz_143))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -5492,10 +4443,8 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_279_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_239) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; end @@ -5507,39 +4456,39 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign _zz_27_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_26_ = decode_ENV_CTRL; - assign _zz_23_ = execute_ENV_CTRL; - assign _zz_21_ = memory_ENV_CTRL; - assign _zz_24_ = _zz_83_; - assign _zz_34_ = decode_to_execute_ENV_CTRL; - assign _zz_33_ = execute_to_memory_ENV_CTRL; - assign _zz_37_ = memory_to_writeBack_ENV_CTRL; - assign _zz_19_ = decode_BRANCH_CTRL; - assign _zz_97_ = _zz_84_; - assign _zz_40_ = decode_to_execute_BRANCH_CTRL; - assign _zz_17_ = decode_SRC2_CTRL; - assign _zz_15_ = _zz_70_; - assign _zz_52_ = decode_to_execute_SRC2_CTRL; - assign _zz_14_ = decode_SRC1_CTRL; - assign _zz_12_ = _zz_85_; - assign _zz_54_ = decode_to_execute_SRC1_CTRL; - assign _zz_11_ = decode_ALU_CTRL; - assign _zz_9_ = _zz_66_; - assign _zz_57_ = decode_to_execute_ALU_CTRL; - assign _zz_8_ = decode_SHIFT_CTRL; - assign _zz_5_ = execute_SHIFT_CTRL; - assign _zz_6_ = _zz_68_; - assign _zz_47_ = decode_to_execute_SHIFT_CTRL; - assign _zz_45_ = execute_to_memory_SHIFT_CTRL; - assign _zz_3_ = decode_ALU_BITWISE_CTRL; - assign _zz_1_ = _zz_80_; - assign _zz_59_ = decode_to_execute_ALU_BITWISE_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign _zz_26 = decode_SRC1_CTRL; + assign _zz_24 = _zz_49; + assign _zz_37 = decode_to_execute_SRC1_CTRL; + assign _zz_23 = decode_ALU_CTRL; + assign _zz_21 = _zz_48; + assign _zz_38 = decode_to_execute_ALU_CTRL; + assign _zz_20 = decode_SRC2_CTRL; + assign _zz_18 = _zz_47; + assign _zz_36 = decode_to_execute_SRC2_CTRL; + assign _zz_17 = decode_ALU_BITWISE_CTRL; + assign _zz_15 = _zz_46; + assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_14 = decode_SHIFT_CTRL; + assign _zz_11 = execute_SHIFT_CTRL; + assign _zz_12 = _zz_45; + assign _zz_34 = decode_to_execute_SHIFT_CTRL; + assign _zz_33 = execute_to_memory_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_51 = _zz_44; + assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_43; + assign _zz_28 = decode_to_execute_ENV_CTRL; + assign _zz_27 = execute_to_memory_ENV_CTRL; + assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -5558,15 +4507,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_216_) - 3'b000 : begin - end - 3'b001 : begin - end - 3'b010 : begin - end - 3'b011 : begin - end + case(_zz_144) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -5575,73 +4516,245 @@ module VexRiscv ( endcase end - assign iBusWishbone_ADR = {_zz_382_,_zz_217_}; - assign iBusWishbone_CTI = ((_zz_217_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); - assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); always @ (*) begin - iBusWishbone_CYC = 1'b0; - if(_zz_280_)begin - iBusWishbone_CYC = 1'b1; + _zz_145 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_145[12 : 0] = 13'h1000; + _zz_145[25 : 20] = 6'h20; end end always @ (*) begin - iBusWishbone_STB = 1'b0; - if(_zz_280_)begin - iBusWishbone_STB = 1'b1; + _zz_146 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_146[3 : 0] = 4'b1011; end end - assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_218_; - assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; - assign iBus_rsp_payload_error = 1'b0; - assign _zz_224_ = (dBus_cmd_payload_length != (3'b000)); - assign _zz_220_ = dBus_cmd_valid; - assign _zz_222_ = dBus_cmd_payload_wr; - assign _zz_223_ = (_zz_219_ == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_221_ && (_zz_222_ || _zz_223_)); - assign dBusWishbone_ADR = ((_zz_224_ ? {{dBus_cmd_payload_address[31 : 5],_zz_219_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); - assign dBusWishbone_CTI = (_zz_224_ ? (_zz_223_ ? (3'b111) : (3'b010)) : (3'b000)); - assign dBusWishbone_BTE = (2'b00); - assign dBusWishbone_SEL = (_zz_222_ ? dBus_cmd_payload_mask : (4'b1111)); - assign dBusWishbone_WE = _zz_222_; - assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_221_ = (_zz_220_ && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_220_; - assign dBusWishbone_STB = _zz_220_; - assign dBus_rsp_valid = _zz_225_; - assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; - assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @ (*) begin + _zz_147 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_147[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_148 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_148[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_149 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_149[31 : 30] = CsrPlugin_misa_base; + _zz_149[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_150 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_150[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_150[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_150[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_151 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_151[11 : 11] = CsrPlugin_mip_MEIP; + _zz_151[7 : 7] = CsrPlugin_mip_MTIP; + _zz_151[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_152 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_152[11 : 11] = CsrPlugin_mie_MEIE; + _zz_152[7 : 7] = CsrPlugin_mie_MTIE; + _zz_152[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_153 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_153[31 : 2] = CsrPlugin_mtvec_base; + _zz_153[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_154 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_154[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_155 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_155[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_156 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_156[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_156[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_157 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_157[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_158 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_158[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_159 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_159[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_160 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_160[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_161 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_161[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_162 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_162[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_163 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_163[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_164 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_164[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_165 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_165[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_166 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_166[31 : 0] = _zz_141; + end + end + + always @ (*) begin + _zz_167 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_167[31 : 0] = _zz_142; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_145 | _zz_146) | (_zz_147 | _zz_148)) | ((_zz_534 | _zz_149) | (_zz_150 | _zz_151))) | (((_zz_152 | _zz_153) | (_zz_154 | _zz_155)) | ((_zz_156 | _zz_157) | (_zz_158 | _zz_159)))) | (((_zz_160 | _zz_161) | (_zz_162 | _zz_163)) | ((_zz_164 | _zz_165) | (_zz_166 | _zz_167)))); + assign iBusWishbone_ADR = {_zz_342,_zz_168}; + assign iBusWishbone_CTI = ((_zz_168 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_240)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_240)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_169; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_175 = (dBus_cmd_payload_length != 3'b000); + assign _zz_171 = dBus_cmd_valid; + assign _zz_173 = dBus_cmd_payload_wr; + assign _zz_174 = (_zz_170 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_172 && (_zz_173 || _zz_174)); + assign dBusWishbone_ADR = ((_zz_175 ? {{dBus_cmd_payload_address[31 : 5],_zz_170},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_175 ? (_zz_174 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_173 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_173; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_172 = (_zz_171 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_171; + assign dBusWishbone_STB = _zz_171; + assign dBus_rsp_valid = _zz_176; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_115_ <= 1'b0; - _zz_117_ <= 1'b0; + _zz_65 <= 1'b0; + _zz_67 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_130_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_131_ <= 1'b0; - _zz_138_ <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_145_; - DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_163_ <= 1'b1; - _zz_176_ <= 1'b0; - CsrPlugin_misa_base <= (2'b01); - CsrPlugin_misa_extensions <= (26'b00000000000000000001000010); + IBusCachedPlugin_rspCounter <= _zz_80; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_81; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_99 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -5651,23 +4764,30 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_DivPlugin_div_counter_value <= (6'b000000); - _zz_213_ <= (32'b00000000000000000000000000000000); + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_141 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_216_ <= (3'b000); - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_217_ <= (3'b000); - _zz_218_ <= 1'b0; - _zz_219_ <= (3'b000); - _zz_225_ <= 1'b0; + _zz_144 <= 3'b000; + _zz_168 <= 3'b000; + _zz_169 <= 1'b0; + _zz_170 <= 3'b000; + _zz_176 <= 1'b0; end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin @@ -5676,86 +4796,80 @@ module VexRiscv ( if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_115_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_65 <= 1'b0; end - if(_zz_113_)begin - _zz_115_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if(_zz_63)begin + _zz_65 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_117_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_67 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_117_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_67 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_131_ <= 1'b0; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_281_)begin - _zz_131_ <= dataCache_1__io_mem_cmd_valid; + if(_zz_241)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_138_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end if(dBus_rsp_valid)begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_163_ <= 1'b0; - _zz_176_ <= _zz_175_; + _zz_99 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5777,20 +4891,39 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_282_)begin - if(_zz_283_)begin + if(_zz_242)begin + if(_zz_243)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_284_)begin + if(_zz_244)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_285_)begin + if(_zz_245)begin CsrPlugin_interrupt_valid <= 1'b1; end end CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_263_)begin + if(_zz_222)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5801,10 +4934,10 @@ module VexRiscv ( end endcase end - if(_zz_264_)begin - case(_zz_266_) + if(_zz_223)begin + case(_zz_225) 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; end @@ -5812,575 +4945,1671 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_203_,{_zz_202_,_zz_201_}} != (3'b000)); + execute_CsrPlugin_wfiWake <= (({_zz_133,{_zz_132,_zz_131}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_144) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_144 <= 3'b001; + end + end + 3'b001 : begin + _zz_144 <= 3'b010; + end + 3'b010 : begin + _zz_144 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_144 <= 3'b100; + end + end + 3'b100 : begin + _zz_144 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_335[0]; + CsrPlugin_mstatus_MIE <= _zz_336[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_338[0]; + CsrPlugin_mie_MTIE <= _zz_339[0]; + CsrPlugin_mie_MSIE <= _zz_340[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_141 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_240)begin + if(iBusWishbone_ACK)begin + _zz_168 <= (_zz_168 + 3'b001); + end + end + _zz_169 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_171 && _zz_172))begin + _zz_170 <= (_zz_170 + 3'b001); + if(_zz_174)begin + _zz_170 <= 3'b000; + end + end + _zz_176 <= ((_zz_171 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_68 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_241)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_218)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_135 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_135 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_242)begin + if(_zz_243)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_244)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_245)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_222)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_213)begin + if(_zz_237)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_326[31:0]; + end + end + end + if(_zz_238)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_139 ? (~ _zz_140) : _zz_140) + _zz_332); + memory_DivPlugin_rs2 <= ((_zz_138 ? (~ execute_RS2) : execute_RS2) + _zz_334); + memory_DivPlugin_div_needRevert <= ((_zz_139 ^ (_zz_138 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_35; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_337[0]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_44_; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin - execute_arbitration_isValid <= 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin - execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin - memory_arbitration_isValid <= 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_341[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin - memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin - writeBack_arbitration_isValid <= 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end - case(_zz_216_) - 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_216_ <= (3'b001); - end - end - 3'b001 : begin - _zz_216_ <= (3'b010); - end - 3'b010 : begin - _zz_216_ <= (3'b011); - end - 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_216_ <= (3'b100); - end - end - 3'b100 : begin - _zz_216_ <= (3'b000); - end - default : begin - end - endcase - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_213_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_375_[0]; - CsrPlugin_mstatus_MIE <= _zz_376_[0]; - end - end - 12'b111100010001 : begin - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - end - 12'b101100000000 : begin - end - 12'b101110000000 : begin - end - 12'b001101000100 : begin - end - 12'b001100000101 : begin - end - 12'b110011000000 : begin - end - 12'b101100000010 : begin - end - 12'b111100010011 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b110000000000 : begin - end - 12'b001100000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; - end - end - 12'b001101000000 : begin - end - 12'b111100010010 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_378_[0]; - CsrPlugin_mie_MTIE <= _zz_379_[0]; - CsrPlugin_mie_MSIE <= _zz_380_[0]; - end - end - 12'b101110000010 : begin - end - 12'b110010000000 : begin - end - 12'b001101000010 : begin - end - default : begin - end - endcase - if(_zz_280_)begin - if(iBusWishbone_ACK)begin - _zz_217_ <= (_zz_217_ + (3'b001)); - end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; end - _zz_218_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_220_ && _zz_221_))begin - _zz_219_ <= (_zz_219_ + (3'b001)); - if(_zz_223_)begin - _zz_219_ <= (3'b000); - end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end - _zz_225_ <= ((_zz_220_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_118_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; - end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin - IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; - end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin - IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; - end - if(_zz_281_)begin - _zz_132_ <= dataCache_1__io_mem_cmd_payload_wr; - _zz_133_ <= dataCache_1__io_mem_cmd_payload_address; - _zz_134_ <= dataCache_1__io_mem_cmd_payload_data; - _zz_135_ <= dataCache_1__io_mem_cmd_payload_mask; - _zz_136_ <= dataCache_1__io_mem_cmd_payload_length; - _zz_137_ <= dataCache_1__io_mem_cmd_payload_last; - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_139_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - _zz_140_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; - _zz_141_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; - _zz_142_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - _zz_143_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; - _zz_144_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; - end - if(_zz_175_)begin - _zz_177_ <= _zz_60_[11 : 7]; - _zz_178_ <= _zz_91_; - end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - end - if(_zz_258_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_205_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_205_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; end - if(BranchPlugin_branchExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_50; end - if(DBusCachedPlugin_exceptionBus_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + _zz_143 <= debug_bus_cmd_payload_address[2]; + if(_zz_220)begin + DebugPlugin_busReadDataReg <= execute_PC; end - if(_zz_282_)begin - if(_zz_283_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - if(_zz_284_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - if(_zz_285_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; end - end - if(_zz_263_)begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + if(debug_bus_cmd_valid)begin + case(_zz_239) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + default : begin end + endcase + end + if(_zz_220)begin + if(_zz_221)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; end - default : begin + end + if(_zz_224)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; end - endcase + end end - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_done <= 1'b1; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; end - if(_zz_253_)begin - if(_zz_262_)begin - memory_DivPlugin_rs1[31 : 0] <= _zz_363_[31:0]; - memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_208_[32]) ? _zz_364_ : _zz_365_); - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_result <= _zz_366_[31:0]; - end - end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end - if(_zz_278_)begin - memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_DivPlugin_rs1 <= ((_zz_211_ ? (~ _zz_212_) : _zz_212_) + _zz_372_); - memory_DivPlugin_rs2 <= ((_zz_210_ ? (~ execute_RS2) : execute_RS2) + _zz_374_); - memory_DivPlugin_div_needRevert <= ((_zz_211_ ^ (_zz_210_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HH <= execute_MUL_HH; + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + + always @ (*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + + always @ (*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_51_; + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LH <= execute_MUL_LH; + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HL <= execute_MUL_HL; + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + if(_zz_13)begin + stageB_loaderValid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_99_; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_98_; + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LL <= execute_MUL_LL; + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_25_; + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_22_; + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_20_; + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_18_; + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_16_; + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_13_; + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_10_; + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_7_; + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_4_; + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_MUL <= decode_IS_MUL; + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_43_; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_2_; + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b111100010001 : begin - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b101100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b101110000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_377_[0]; - end - end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end - end - 12'b110011000000 : begin - end - 12'b101100000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b111100010011 : begin - end - 12'b001101000011 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); end end - 12'b111111000000 : begin - end - 12'b110000000000 : begin + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; end - 12'b001100000001 : begin + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; end - 12'b001101000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end end end - 12'b111100010010 : begin + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; end - 12'b001100000100 : begin + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; end - 12'b101110000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; - end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; end - 12'b110010000000 : begin + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); end - 12'b001101000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_381_[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; - end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; end - default : begin + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; end - endcase - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end end + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_9, + input [31:0] _zz_10, + input clk, + input reset +); + reg [31:0] _zz_11; + reg [21:0] _zz_12; + wire _zz_13; + wire _zz_14; + wire [0:0] _zz_15; + wire [0:0] _zz_16; + wire [21:0] _zz_17; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_13 = (! lineLoader_flushCounter[7]); + assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_15 = _zz_8[0 : 0]; + assign _zz_16 = _zz_8[1 : 1]; + assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; always @ (posedge clk) begin - DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin - DebugPlugin_firstCycle <= 1'b1; + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end - DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_91_; + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_11 <= banks_0[_zz_4]; end - _zz_215_ <= debug_bus_cmd_payload_address[2]; - if(_zz_260_)begin - DebugPlugin_busReadDataReg <= execute_PC; + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; end - DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end always @ (posedge clk) begin - if(debugReset) begin - DebugPlugin_resetIt <= 1'b0; - DebugPlugin_haltIt <= 1'b0; - DebugPlugin_stepIt <= 1'b0; - DebugPlugin_godmode <= 1'b0; - DebugPlugin_haltedByBreak <= 1'b0; + if(_zz_7) begin + _zz_12 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_13)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_12; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin - DebugPlugin_godmode <= 1'b1; + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; end - if(debug_bus_cmd_valid)begin - case(_zz_279_) - 6'b000000 : begin - if(debug_bus_cmd_payload_wr)begin - DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin - DebugPlugin_resetIt <= 1'b1; - end - if(debug_bus_cmd_payload_data[24])begin - DebugPlugin_resetIt <= 1'b0; - end - if(debug_bus_cmd_payload_data[17])begin - DebugPlugin_haltIt <= 1'b1; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_haltIt <= 1'b0; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_haltedByBreak <= 1'b0; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_godmode <= 1'b0; - end - end - end - 6'b000001 : begin - end - default : begin - end - endcase + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; end - if(_zz_260_)begin - if(_zz_261_)begin - DebugPlugin_haltIt <= 1'b1; - DebugPlugin_haltedByBreak <= 1'b1; - end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end - if(_zz_265_)begin - if(decode_arbitration_isValid)begin - DebugPlugin_haltIt <= 1'b1; + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_14)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; end end end end -endmodule + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_13)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_14)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + if((_zz_9 != 3'b000))begin + io_cpu_fetch_data_regNextWhen <= _zz_10; + end + end + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v index ef2d966..592ac6e 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 29/04/2020, 00:19:02 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -9,3273 +9,2417 @@ `define EnvCtrlEnum_defaultEncoding_WFI 2'b10 `define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - `define BranchCtrlEnum_defaultEncoding_type [1:0] `define BranchCtrlEnum_defaultEncoding_INC 2'b00 `define BranchCtrlEnum_defaultEncoding_B 2'b01 `define BranchCtrlEnum_defaultEncoding_JAL 2'b10 `define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + `define Src2CtrlEnum_defaultEncoding_type [1:0] `define Src2CtrlEnum_defaultEncoding_RS 2'b00 `define Src2CtrlEnum_defaultEncoding_IMI 2'b01 `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + `define Src1CtrlEnum_defaultEncoding_type [1:0] `define Src1CtrlEnum_defaultEncoding_RS 2'b00 `define Src1CtrlEnum_defaultEncoding_IMU 2'b01 `define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_190; + wire _zz_191; + wire _zz_192; + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire [31:0] _zz_198; + reg _zz_199; + wire _zz_200; + wire [31:0] _zz_201; + wire _zz_202; + wire [31:0] _zz_203; + reg _zz_204; + wire _zz_205; + wire _zz_206; + wire [31:0] _zz_207; + wire _zz_208; + wire _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire [3:0] _zz_216; + wire _zz_217; + wire _zz_218; + reg [31:0] _zz_219; + reg [31:0] _zz_220; + reg [31:0] _zz_221; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_error; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_222; + wire _zz_223; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire _zz_235; + wire [1:0] _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire _zz_245; + wire _zz_246; + wire _zz_247; + wire [1:0] _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire _zz_255; + wire _zz_256; + wire _zz_257; + wire [4:0] _zz_258; + wire [1:0] _zz_259; + wire [1:0] _zz_260; + wire [1:0] _zz_261; + wire _zz_262; + wire [1:0] _zz_263; + wire [51:0] _zz_264; + wire [51:0] _zz_265; + wire [51:0] _zz_266; + wire [32:0] _zz_267; + wire [51:0] _zz_268; + wire [49:0] _zz_269; + wire [51:0] _zz_270; + wire [49:0] _zz_271; + wire [51:0] _zz_272; + wire [32:0] _zz_273; + wire [31:0] _zz_274; + wire [32:0] _zz_275; + wire [0:0] _zz_276; + wire [0:0] _zz_277; + wire [0:0] _zz_278; + wire [0:0] _zz_279; + wire [0:0] _zz_280; + wire [0:0] _zz_281; + wire [0:0] _zz_282; + wire [0:0] _zz_283; + wire [0:0] _zz_284; + wire [0:0] _zz_285; + wire [2:0] _zz_286; + wire [31:0] _zz_287; + wire [0:0] _zz_288; + wire [0:0] _zz_289; + wire [0:0] _zz_290; + wire [0:0] _zz_291; + wire [0:0] _zz_292; + wire [0:0] _zz_293; + wire [0:0] _zz_294; + wire [3:0] _zz_295; + wire [2:0] _zz_296; + wire [31:0] _zz_297; + wire [2:0] _zz_298; + wire [31:0] _zz_299; + wire [31:0] _zz_300; + wire [11:0] _zz_301; + wire [11:0] _zz_302; + wire [11:0] _zz_303; + wire [31:0] _zz_304; + wire [19:0] _zz_305; + wire [11:0] _zz_306; + wire [2:0] _zz_307; + wire [2:0] _zz_308; + wire [0:0] _zz_309; + wire [2:0] _zz_310; + wire [4:0] _zz_311; + wire [11:0] _zz_312; + wire [11:0] _zz_313; + wire [31:0] _zz_314; + wire [31:0] _zz_315; + wire [31:0] _zz_316; + wire [31:0] _zz_317; + wire [31:0] _zz_318; + wire [31:0] _zz_319; + wire [31:0] _zz_320; + wire [11:0] _zz_321; + wire [19:0] _zz_322; + wire [11:0] _zz_323; + wire [2:0] _zz_324; + wire [1:0] _zz_325; + wire [1:0] _zz_326; + wire [65:0] _zz_327; + wire [65:0] _zz_328; + wire [31:0] _zz_329; + wire [31:0] _zz_330; + wire [0:0] _zz_331; + wire [5:0] _zz_332; + wire [32:0] _zz_333; + wire [31:0] _zz_334; + wire [31:0] _zz_335; + wire [32:0] _zz_336; + wire [32:0] _zz_337; + wire [32:0] _zz_338; + wire [32:0] _zz_339; + wire [0:0] _zz_340; + wire [32:0] _zz_341; + wire [0:0] _zz_342; + wire [32:0] _zz_343; + wire [0:0] _zz_344; + wire [31:0] _zz_345; + wire [0:0] _zz_346; + wire [0:0] _zz_347; + wire [0:0] _zz_348; + wire [0:0] _zz_349; + wire [0:0] _zz_350; + wire [0:0] _zz_351; + wire [0:0] _zz_352; + wire [26:0] _zz_353; + wire _zz_354; + wire _zz_355; + wire [1:0] _zz_356; + wire [31:0] _zz_357; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire _zz_360; + wire [0:0] _zz_361; + wire [13:0] _zz_362; + wire [31:0] _zz_363; + wire [31:0] _zz_364; + wire [31:0] _zz_365; + wire _zz_366; + wire [0:0] _zz_367; + wire [7:0] _zz_368; + wire [31:0] _zz_369; + wire [31:0] _zz_370; + wire [31:0] _zz_371; + wire _zz_372; + wire [0:0] _zz_373; + wire [1:0] _zz_374; + wire _zz_375; + wire _zz_376; + wire [6:0] _zz_377; + wire [4:0] _zz_378; + wire _zz_379; + wire [4:0] _zz_380; + wire [0:0] _zz_381; + wire [7:0] _zz_382; + wire _zz_383; + wire [0:0] _zz_384; + wire [0:0] _zz_385; + wire [31:0] _zz_386; + wire [31:0] _zz_387; + wire _zz_388; + wire [0:0] _zz_389; + wire [0:0] _zz_390; + wire _zz_391; + wire [0:0] _zz_392; + wire [24:0] _zz_393; + wire [31:0] _zz_394; + wire _zz_395; + wire _zz_396; + wire [0:0] _zz_397; + wire [0:0] _zz_398; + wire [0:0] _zz_399; + wire [0:0] _zz_400; + wire _zz_401; + wire [0:0] _zz_402; + wire [20:0] _zz_403; + wire [31:0] _zz_404; + wire [31:0] _zz_405; + wire _zz_406; + wire _zz_407; + wire [0:0] _zz_408; + wire [1:0] _zz_409; + wire [0:0] _zz_410; + wire [0:0] _zz_411; + wire _zz_412; + wire [0:0] _zz_413; + wire [17:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire [31:0] _zz_418; + wire [31:0] _zz_419; + wire [31:0] _zz_420; + wire [31:0] _zz_421; + wire [31:0] _zz_422; + wire _zz_423; + wire [1:0] _zz_424; + wire [1:0] _zz_425; + wire _zz_426; + wire [0:0] _zz_427; + wire [14:0] _zz_428; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire [31:0] _zz_431; + wire [31:0] _zz_432; + wire [31:0] _zz_433; + wire [31:0] _zz_434; + wire [0:0] _zz_435; + wire [0:0] _zz_436; + wire [4:0] _zz_437; + wire [4:0] _zz_438; + wire _zz_439; + wire [0:0] _zz_440; + wire [11:0] _zz_441; + wire [31:0] _zz_442; + wire [31:0] _zz_443; + wire [31:0] _zz_444; + wire [31:0] _zz_445; + wire _zz_446; + wire [0:0] _zz_447; + wire [1:0] _zz_448; + wire [31:0] _zz_449; + wire [31:0] _zz_450; + wire [0:0] _zz_451; + wire [3:0] _zz_452; + wire [4:0] _zz_453; + wire [4:0] _zz_454; + wire _zz_455; + wire [0:0] _zz_456; + wire [8:0] _zz_457; + wire [31:0] _zz_458; + wire [31:0] _zz_459; + wire [31:0] _zz_460; + wire _zz_461; + wire _zz_462; + wire [31:0] _zz_463; + wire [31:0] _zz_464; + wire [0:0] _zz_465; + wire [1:0] _zz_466; + wire [0:0] _zz_467; + wire [2:0] _zz_468; + wire [0:0] _zz_469; + wire [4:0] _zz_470; + wire [1:0] _zz_471; + wire [1:0] _zz_472; + wire _zz_473; + wire [0:0] _zz_474; + wire [6:0] _zz_475; + wire [31:0] _zz_476; + wire [31:0] _zz_477; + wire [31:0] _zz_478; + wire [31:0] _zz_479; + wire _zz_480; + wire _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire _zz_484; + wire [0:0] _zz_485; + wire [0:0] _zz_486; + wire _zz_487; + wire [0:0] _zz_488; + wire [2:0] _zz_489; + wire _zz_490; + wire [0:0] _zz_491; + wire [0:0] _zz_492; + wire [0:0] _zz_493; + wire [0:0] _zz_494; + wire _zz_495; + wire [0:0] _zz_496; + wire [4:0] _zz_497; + wire [31:0] _zz_498; + wire [31:0] _zz_499; + wire [31:0] _zz_500; + wire [31:0] _zz_501; + wire [31:0] _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire [31:0] _zz_505; + wire [31:0] _zz_506; + wire [31:0] _zz_507; + wire _zz_508; + wire [0:0] _zz_509; + wire [0:0] _zz_510; + wire [31:0] _zz_511; + wire [31:0] _zz_512; + wire [31:0] _zz_513; + wire [31:0] _zz_514; + wire [31:0] _zz_515; + wire _zz_516; + wire [3:0] _zz_517; + wire [3:0] _zz_518; + wire _zz_519; + wire [0:0] _zz_520; + wire [2:0] _zz_521; + wire [31:0] _zz_522; + wire [31:0] _zz_523; + wire [31:0] _zz_524; + wire [31:0] _zz_525; + wire [31:0] _zz_526; + wire [31:0] _zz_527; + wire _zz_528; + wire [0:0] _zz_529; + wire [1:0] _zz_530; + wire _zz_531; + wire [2:0] _zz_532; + wire [2:0] _zz_533; + wire _zz_534; + wire [0:0] _zz_535; + wire [0:0] _zz_536; + wire [31:0] _zz_537; + wire [31:0] _zz_538; + wire [31:0] _zz_539; + wire [31:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire [31:0] _zz_543; + wire _zz_544; + wire _zz_545; + wire _zz_546; + wire [0:0] _zz_547; + wire [0:0] _zz_548; + wire _zz_549; + wire _zz_550; + wire _zz_551; + wire _zz_552; + wire [31:0] _zz_553; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire execute_PREDICTION_HAD_BRANCHED2; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_31; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_35; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_36; + wire execute_IS_RVC; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; + wire [31:0] _zz_40; + wire _zz_41; + reg _zz_42; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_43; + wire `BranchCtrlEnum_defaultEncoding_type _zz_44; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; + wire `Src2CtrlEnum_defaultEncoding_type _zz_47; + wire `AluCtrlEnum_defaultEncoding_type _zz_48; + wire `Src1CtrlEnum_defaultEncoding_type _zz_49; + reg [31:0] _zz_50; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + reg [31:0] _zz_52; + reg [31:0] _zz_53; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire decode_IS_RVC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + wire IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_54; + wire [3:0] _zz_55; + wire _zz_56; + wire _zz_57; + wire _zz_58; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + reg [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_decodePc_flushed; + reg [31:0] IBusCachedPlugin_decodePc_pcReg /* verilator public */ ; + wire [31:0] IBusCachedPlugin_decodePc_pcPlus; + wire IBusCachedPlugin_decodePc_injectedDecode; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire _zz_59; + wire _zz_60; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_61; + wire _zz_62; + reg _zz_63; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire IBusCachedPlugin_decompressor_input_valid; + wire IBusCachedPlugin_decompressor_input_ready; + wire [31:0] IBusCachedPlugin_decompressor_input_payload_pc; + wire IBusCachedPlugin_decompressor_input_payload_rsp_error; + wire [31:0] IBusCachedPlugin_decompressor_input_payload_rsp_inst; + wire IBusCachedPlugin_decompressor_input_payload_isRvc; + wire IBusCachedPlugin_decompressor_output_valid; + wire IBusCachedPlugin_decompressor_output_ready; + wire [31:0] IBusCachedPlugin_decompressor_output_payload_pc; + wire IBusCachedPlugin_decompressor_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_decompressor_output_payload_rsp_inst; + wire IBusCachedPlugin_decompressor_output_payload_isRvc; + wire IBusCachedPlugin_decompressor_flushNext; + wire IBusCachedPlugin_decompressor_consumeCurrent; + reg IBusCachedPlugin_decompressor_bufferValid; + reg [15:0] IBusCachedPlugin_decompressor_bufferData; + wire IBusCachedPlugin_decompressor_isInputLowRvc; + wire IBusCachedPlugin_decompressor_isInputHighRvc; + reg IBusCachedPlugin_decompressor_throw2BytesReg; + wire IBusCachedPlugin_decompressor_throw2Bytes; + wire IBusCachedPlugin_decompressor_unaligned; + wire [31:0] IBusCachedPlugin_decompressor_raw; + wire IBusCachedPlugin_decompressor_isRvc; + wire [15:0] _zz_64; + reg [31:0] IBusCachedPlugin_decompressor_decompressed; + wire [4:0] _zz_65; + wire [4:0] _zz_66; + wire [11:0] _zz_67; + wire _zz_68; + reg [11:0] _zz_69; + wire _zz_70; + reg [9:0] _zz_71; + wire [20:0] _zz_72; + wire _zz_73; + reg [14:0] _zz_74; + wire _zz_75; + reg [2:0] _zz_76; + wire _zz_77; + reg [9:0] _zz_78; + wire [20:0] _zz_79; + wire _zz_80; + reg [4:0] _zz_81; + wire [12:0] _zz_82; + wire [4:0] _zz_83; + wire [4:0] _zz_84; + wire [4:0] _zz_85; + wire _zz_86; + reg [2:0] _zz_87; + reg [2:0] _zz_88; + wire _zz_89; + reg [6:0] _zz_90; + wire IBusCachedPlugin_decompressor_bufferFill; + wire IBusCachedPlugin_injector_decodeInput_valid; + wire IBusCachedPlugin_injector_decodeInput_ready; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; + wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; + reg _zz_91; + reg [31:0] _zz_92; + reg _zz_93; + reg [31:0] _zz_94; + reg _zz_95; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; + wire _zz_96; + reg [18:0] _zz_97; + wire _zz_98; + reg [10:0] _zz_99; + wire _zz_100; + reg [18:0] _zz_101; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_102; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_103; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_104; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_105; + reg [31:0] _zz_106; + wire _zz_107; + reg [31:0] _zz_108; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [31:0] _zz_109; + wire _zz_110; + wire _zz_111; + wire _zz_112; + wire _zz_113; + wire `Src1CtrlEnum_defaultEncoding_type _zz_114; + wire `AluCtrlEnum_defaultEncoding_type _zz_115; + wire `Src2CtrlEnum_defaultEncoding_type _zz_116; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_117; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_118; + wire `BranchCtrlEnum_defaultEncoding_type _zz_119; + wire `EnvCtrlEnum_defaultEncoding_type _zz_120; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_121; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_122; + reg [31:0] _zz_123; + wire _zz_124; + reg [19:0] _zz_125; + wire _zz_126; + reg [19:0] _zz_127; + reg [31:0] _zz_128; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_129; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_130; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_131; + wire _zz_132; + wire _zz_133; + wire _zz_134; + wire _zz_135; + wire _zz_136; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_137; + reg _zz_138; + reg _zz_139; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_140; + reg [19:0] _zz_141; + wire _zz_142; + reg [10:0] _zz_143; + wire _zz_144; + reg [18:0] _zz_145; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_146; + wire _zz_147; + wire _zz_148; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_149; + wire _zz_150; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_151; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_152; + wire _zz_153; + wire _zz_154; + reg [32:0] _zz_155; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_156; + wire [31:0] _zz_157; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg decode_to_execute_IS_RVC; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [2:0] _zz_181; + reg _zz_182; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_183; + wire _zz_184; + wire _zz_185; + wire _zz_186; + wire _zz_187; + wire _zz_188; + reg _zz_189; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [23:0] _zz_20_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [63:0] _zz_23_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; + reg [95:0] _zz_26_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_27_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_29_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_30_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_33_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_34_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_36_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_37_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_39_string; + reg [39:0] _zz_43_string; + reg [31:0] _zz_44_string; + reg [71:0] _zz_45_string; + reg [39:0] _zz_46_string; + reg [23:0] _zz_47_string; + reg [63:0] _zz_48_string; + reg [95:0] _zz_49_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_51_string; + reg [95:0] _zz_114_string; + reg [63:0] _zz_115_string; + reg [23:0] _zz_116_string; + reg [39:0] _zz_117_string; + reg [71:0] _zz_118_string; + reg [31:0] _zz_119_string; + reg [39:0] _zz_120_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_cacheMiss, - output io_cpu_fetch_error, - output io_cpu_fetch_mmuRefilling, - output io_cpu_fetch_mmuException, - input io_cpu_fetch_isUser, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire [0:0] _zz_14_; - wire [0:0] _zz_15_; - wire [21:0] _zz_16_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [6:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_7_; - wire [9:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; - assign _zz_12_ = (! lineLoader_flushCounter[7]); - assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_14_ = _zz_7_[0 : 0]; - assign _zz_15_ = _zz_7_[1 : 1]; - assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; - end - end + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_222 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_223 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_224 = 1'b1; + assign _zz_225 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_226 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_227 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_228 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_229 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_230 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_231 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_232 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_233 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_234 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_235 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_236 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_237 = (IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); + assign _zz_238 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_239 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_240 = (1'b0 || (! 1'b1)); + assign _zz_241 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_242 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_243 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_244 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_245 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_246 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_247 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_248 = execute_INSTRUCTION[13 : 12]; + assign _zz_249 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_250 = (! memory_arbitration_isStuck); + assign _zz_251 = (iBus_cmd_valid || (_zz_181 != 3'b000)); + assign _zz_252 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); + assign _zz_253 = (_zz_218 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_254 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_255 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_256 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_257 = ((_zz_148 && 1'b1) && (! 1'b0)); + assign _zz_258 = {_zz_64[1 : 0],_zz_64[15 : 13]}; + assign _zz_259 = _zz_64[6 : 5]; + assign _zz_260 = _zz_64[11 : 10]; + assign _zz_261 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_262 = execute_INSTRUCTION[13]; + assign _zz_263 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_264 = ($signed(_zz_265) + $signed(_zz_270)); + assign _zz_265 = ($signed(_zz_266) + $signed(_zz_268)); + assign _zz_266 = 52'h0; + assign _zz_267 = {1'b0,memory_MUL_LL}; + assign _zz_268 = {{19{_zz_267[32]}}, _zz_267}; + assign _zz_269 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_270 = {{2{_zz_269[49]}}, _zz_269}; + assign _zz_271 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_272 = {{2{_zz_271[49]}}, _zz_271}; + assign _zz_273 = ($signed(_zz_275) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_274 = _zz_273[31 : 0]; + assign _zz_275 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_276 = _zz_109[31 : 31]; + assign _zz_277 = _zz_109[30 : 30]; + assign _zz_278 = _zz_109[29 : 29]; + assign _zz_279 = _zz_109[28 : 28]; + assign _zz_280 = _zz_109[25 : 25]; + assign _zz_281 = _zz_109[17 : 17]; + assign _zz_282 = _zz_109[16 : 16]; + assign _zz_283 = _zz_109[13 : 13]; + assign _zz_284 = _zz_109[12 : 12]; + assign _zz_285 = _zz_109[11 : 11]; + assign _zz_286 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_287 = {29'd0, _zz_286}; + assign _zz_288 = _zz_109[15 : 15]; + assign _zz_289 = _zz_109[5 : 5]; + assign _zz_290 = _zz_109[3 : 3]; + assign _zz_291 = _zz_109[20 : 20]; + assign _zz_292 = _zz_109[10 : 10]; + assign _zz_293 = _zz_109[4 : 4]; + assign _zz_294 = _zz_109[0 : 0]; + assign _zz_295 = (_zz_54 - 4'b0001); + assign _zz_296 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_297 = {29'd0, _zz_296}; + assign _zz_298 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_299 = {29'd0, _zz_298}; + assign _zz_300 = {{_zz_74,_zz_64[6 : 2]},12'h0}; + assign _zz_301 = {{{4'b0000,_zz_64[8 : 7]},_zz_64[12 : 9]},2'b00}; + assign _zz_302 = {{{4'b0000,_zz_64[8 : 7]},_zz_64[12 : 9]},2'b00}; + assign _zz_303 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_304 = {{_zz_97,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_305 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_306 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_307 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_308 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_309 = execute_SRC_LESS; + assign _zz_310 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz_311 = execute_INSTRUCTION[19 : 15]; + assign _zz_312 = execute_INSTRUCTION[31 : 20]; + assign _zz_313 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_314 = ($signed(_zz_315) + $signed(_zz_318)); + assign _zz_315 = ($signed(_zz_316) + $signed(_zz_317)); + assign _zz_316 = execute_SRC1; + assign _zz_317 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_318 = (execute_SRC_USE_SUB_LESS ? _zz_319 : _zz_320); + assign _zz_319 = 32'h00000001; + assign _zz_320 = 32'h0; + assign _zz_321 = execute_INSTRUCTION[31 : 20]; + assign _zz_322 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_323 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_324 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz_325 = (_zz_149 & (~ _zz_326)); + assign _zz_326 = (_zz_149 - 2'b01); + assign _zz_327 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_328 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_329 = writeBack_MUL_LOW[31 : 0]; + assign _zz_330 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_331 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_332 = {5'd0, _zz_331}; + assign _zz_333 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_334 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_335 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_336 = {_zz_151,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_337 = _zz_338; + assign _zz_338 = _zz_339; + assign _zz_339 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_152) : _zz_152)} + _zz_341); + assign _zz_340 = memory_DivPlugin_div_needRevert; + assign _zz_341 = {32'd0, _zz_340}; + assign _zz_342 = _zz_154; + assign _zz_343 = {32'd0, _zz_342}; + assign _zz_344 = _zz_153; + assign _zz_345 = {31'd0, _zz_344}; + assign _zz_346 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_347 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_348 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_349 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_350 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_351 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_352 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_353 = (iBus_cmd_payload_address >>> 5); + assign _zz_354 = 1'b1; + assign _zz_355 = 1'b1; + assign _zz_356 = {_zz_58,_zz_57}; + assign _zz_357 = 32'h0000107f; + assign _zz_358 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_359 = 32'h00002073; + assign _zz_360 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_361 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_362 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_363) == 32'h00000003),{(_zz_364 == _zz_365),{_zz_366,{_zz_367,_zz_368}}}}}}; + assign _zz_363 = 32'h0000505f; + assign _zz_364 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_365 = 32'h00000063; + assign _zz_366 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_367 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_368 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_369) == 32'h00001013),{(_zz_370 == _zz_371),{_zz_372,{_zz_373,_zz_374}}}}}}; + assign _zz_369 = 32'hfc00307f; + assign _zz_370 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_371 = 32'h00005033; + assign _zz_372 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_373 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_374 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_375 = (_zz_64[11 : 10] == 2'b01); + assign _zz_376 = ((_zz_64[11 : 10] == 2'b11) && (_zz_64[6 : 5] == 2'b00)); + assign _zz_377 = 7'h0; + assign _zz_378 = _zz_64[6 : 2]; + assign _zz_379 = _zz_64[12]; + assign _zz_380 = _zz_64[11 : 7]; + assign _zz_381 = decode_INSTRUCTION[31]; + assign _zz_382 = decode_INSTRUCTION[19 : 12]; + assign _zz_383 = decode_INSTRUCTION[20]; + assign _zz_384 = decode_INSTRUCTION[31]; + assign _zz_385 = decode_INSTRUCTION[7]; + assign _zz_386 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_387 = 32'h02004020; + assign _zz_388 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_389 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); + assign _zz_390 = 1'b0; + assign _zz_391 = (((decode_INSTRUCTION & _zz_394) == 32'h00000050) != 1'b0); + assign _zz_392 = ({_zz_395,_zz_396} != 2'b00); + assign _zz_393 = {({_zz_397,_zz_398} != 2'b00),{(_zz_399 != _zz_400),{_zz_401,{_zz_402,_zz_403}}}}; + assign _zz_394 = 32'h00403050; + assign _zz_395 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_396 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_397 = _zz_112; + assign _zz_398 = ((decode_INSTRUCTION & _zz_404) == 32'h00000004); + assign _zz_399 = ((decode_INSTRUCTION & _zz_405) == 32'h00000040); + assign _zz_400 = 1'b0; + assign _zz_401 = ({_zz_406,_zz_407} != 2'b00); + assign _zz_402 = ({_zz_408,_zz_409} != 3'b000); + assign _zz_403 = {(_zz_410 != _zz_411),{_zz_412,{_zz_413,_zz_414}}}; + assign _zz_404 = 32'h0000001c; + assign _zz_405 = 32'h00000058; + assign _zz_406 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_407 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_408 = ((decode_INSTRUCTION & _zz_415) == 32'h40001010); + assign _zz_409 = {(_zz_416 == _zz_417),(_zz_418 == _zz_419)}; + assign _zz_410 = ((decode_INSTRUCTION & _zz_420) == 32'h00000024); + assign _zz_411 = 1'b0; + assign _zz_412 = ((_zz_421 == _zz_422) != 1'b0); + assign _zz_413 = (_zz_423 != 1'b0); + assign _zz_414 = {(_zz_424 != _zz_425),{_zz_426,{_zz_427,_zz_428}}}; + assign _zz_415 = 32'h40003054; + assign _zz_416 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_417 = 32'h00001010; + assign _zz_418 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_419 = 32'h00001010; + assign _zz_420 = 32'h00000064; + assign _zz_421 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_422 = 32'h00001000; + assign _zz_423 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_424 = {(_zz_429 == _zz_430),(_zz_431 == _zz_432)}; + assign _zz_425 = 2'b00; + assign _zz_426 = ((_zz_433 == _zz_434) != 1'b0); + assign _zz_427 = ({_zz_435,_zz_436} != 2'b00); + assign _zz_428 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; + assign _zz_429 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_430 = 32'h00002000; + assign _zz_431 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_432 = 32'h00001000; + assign _zz_433 = (decode_INSTRUCTION & 32'h00004048); + assign _zz_434 = 32'h00004008; + assign _zz_435 = ((decode_INSTRUCTION & _zz_442) == 32'h00000020); + assign _zz_436 = ((decode_INSTRUCTION & _zz_443) == 32'h00000020); + assign _zz_437 = {(_zz_444 == _zz_445),{_zz_446,{_zz_447,_zz_448}}}; + assign _zz_438 = 5'h0; + assign _zz_439 = ((_zz_449 == _zz_450) != 1'b0); + assign _zz_440 = ({_zz_451,_zz_452} != 5'h0); + assign _zz_441 = {(_zz_453 != _zz_454),{_zz_455,{_zz_456,_zz_457}}}; + assign _zz_442 = 32'h00000034; + assign _zz_443 = 32'h00000064; + assign _zz_444 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_445 = 32'h00002040; + assign _zz_446 = ((decode_INSTRUCTION & _zz_458) == 32'h00001040); + assign _zz_447 = (_zz_459 == _zz_460); + assign _zz_448 = {_zz_461,_zz_462}; + assign _zz_449 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_450 = 32'h00000020; + assign _zz_451 = (_zz_463 == _zz_464); + assign _zz_452 = {_zz_111,{_zz_465,_zz_466}}; + assign _zz_453 = {_zz_111,{_zz_467,_zz_468}}; + assign _zz_454 = 5'h0; + assign _zz_455 = ({_zz_469,_zz_470} != 6'h0); + assign _zz_456 = (_zz_471 != _zz_472); + assign _zz_457 = {_zz_473,{_zz_474,_zz_475}}; + assign _zz_458 = 32'h00001040; + assign _zz_459 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_460 = 32'h00000040; + assign _zz_461 = ((decode_INSTRUCTION & _zz_476) == 32'h00000040); + assign _zz_462 = ((decode_INSTRUCTION & _zz_477) == 32'h0); + assign _zz_463 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_464 = 32'h00000040; + assign _zz_465 = (_zz_478 == _zz_479); + assign _zz_466 = {_zz_480,_zz_481}; + assign _zz_467 = (_zz_482 == _zz_483); + assign _zz_468 = {_zz_484,{_zz_485,_zz_486}}; + assign _zz_469 = _zz_112; + assign _zz_470 = {_zz_487,{_zz_488,_zz_489}}; + assign _zz_471 = {_zz_111,_zz_490}; + assign _zz_472 = 2'b00; + assign _zz_473 = ({_zz_491,_zz_492} != 2'b00); + assign _zz_474 = (_zz_493 != _zz_494); + assign _zz_475 = {_zz_495,{_zz_496,_zz_497}}; + assign _zz_476 = 32'h00400040; + assign _zz_477 = 32'h00000038; + assign _zz_478 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_479 = 32'h00004020; + assign _zz_480 = ((decode_INSTRUCTION & _zz_498) == 32'h00000010); + assign _zz_481 = ((decode_INSTRUCTION & _zz_499) == 32'h00000020); + assign _zz_482 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_483 = 32'h00002010; + assign _zz_484 = ((decode_INSTRUCTION & _zz_500) == 32'h00000010); + assign _zz_485 = (_zz_501 == _zz_502); + assign _zz_486 = (_zz_503 == _zz_504); + assign _zz_487 = ((decode_INSTRUCTION & _zz_505) == 32'h00001010); + assign _zz_488 = (_zz_506 == _zz_507); + assign _zz_489 = {_zz_508,{_zz_509,_zz_510}}; + assign _zz_490 = ((decode_INSTRUCTION & _zz_511) == 32'h00000020); + assign _zz_491 = _zz_111; + assign _zz_492 = (_zz_512 == _zz_513); + assign _zz_493 = (_zz_514 == _zz_515); + assign _zz_494 = 1'b0; + assign _zz_495 = (_zz_516 != 1'b0); + assign _zz_496 = (_zz_517 != _zz_518); + assign _zz_497 = {_zz_519,{_zz_520,_zz_521}}; + assign _zz_498 = 32'h00000030; + assign _zz_499 = 32'h02000020; + assign _zz_500 = 32'h00001030; + assign _zz_501 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_502 = 32'h00002020; + assign _zz_503 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_504 = 32'h00000020; + assign _zz_505 = 32'h00001010; + assign _zz_506 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_507 = 32'h00002010; + assign _zz_508 = ((decode_INSTRUCTION & _zz_522) == 32'h00000010); + assign _zz_509 = (_zz_523 == _zz_524); + assign _zz_510 = (_zz_525 == _zz_526); + assign _zz_511 = 32'h00000070; + assign _zz_512 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_513 = 32'h0; + assign _zz_514 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_515 = 32'h00004010; + assign _zz_516 = ((decode_INSTRUCTION & _zz_527) == 32'h00002010); + assign _zz_517 = {_zz_528,{_zz_529,_zz_530}}; + assign _zz_518 = 4'b0000; + assign _zz_519 = (_zz_531 != 1'b0); + assign _zz_520 = (_zz_532 != _zz_533); + assign _zz_521 = {_zz_534,{_zz_535,_zz_536}}; + assign _zz_522 = 32'h00000050; + assign _zz_523 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_524 = 32'h00000004; + assign _zz_525 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_526 = 32'h0; + assign _zz_527 = 32'h00006014; + assign _zz_528 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_529 = ((decode_INSTRUCTION & _zz_537) == 32'h0); + assign _zz_530 = {(_zz_538 == _zz_539),(_zz_540 == _zz_541)}; + assign _zz_531 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_532 = {(_zz_542 == _zz_543),{_zz_544,_zz_545}}; + assign _zz_533 = 3'b000; + assign _zz_534 = ({_zz_546,_zz_110} != 2'b00); + assign _zz_535 = ({_zz_547,_zz_548} != 2'b00); + assign _zz_536 = (_zz_549 != 1'b0); + assign _zz_537 = 32'h00000018; + assign _zz_538 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_539 = 32'h00002000; + assign _zz_540 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_541 = 32'h00001000; + assign _zz_542 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_543 = 32'h00000040; + assign _zz_544 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_545 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_546 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_547 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_548 = _zz_110; + assign _zz_549 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_550 = execute_INSTRUCTION[31]; + assign _zz_551 = execute_INSTRUCTION[31]; + assign _zz_552 = execute_INSTRUCTION[7]; + assign _zz_553 = 32'h0; always @ (posedge clk) begin - if(_zz_6_) begin - _zz_10_ <= ways_0_tags[_zz_5_]; + if(_zz_354) begin + _zz_219 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + if(_zz_355) begin + _zz_220 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_9_) begin - _zz_11_ <= ways_0_datas[_zz_8_]; - end - end - - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; - end - end - - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; - end - end - - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; - end - end - end - - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_12_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; + if(_zz_42) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_10_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_11_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid); - assign io_cpu_fetch_error = fetchStage_hit_error; - assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuBus_rsp_refilling; - assign io_cpu_fetch_mmuException = ((! io_cpu_fetch_mmuBus_rsp_refilling) && (io_cpu_fetch_mmuBus_rsp_exception || (! io_cpu_fetch_mmuBus_rsp_allowExecute))); - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; - end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; - end - if(_zz_13_)begin - lineLoader_flushPending <= 1'b0; + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_190 ), //i + .io_cpu_prefetch_isValid (_zz_191 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_192 ), //i + .io_cpu_fetch_isStuck (_zz_193 ), //i + .io_cpu_fetch_isRemoved (_zz_194 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_fetch_cacheMiss (IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss ), //o + .io_cpu_fetch_error (IBusCachedPlugin_cache_io_cpu_fetch_error ), //o + .io_cpu_fetch_mmuRefilling (IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling ), //o + .io_cpu_fetch_mmuException (IBusCachedPlugin_cache_io_cpu_fetch_mmuException ), //o + .io_cpu_fetch_isUser (_zz_195 ), //i + .io_cpu_decode_isValid (_zz_196 ), //i + .io_cpu_decode_isStuck (_zz_197 ), //i + .io_cpu_decode_pc (_zz_198[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_fill_valid (_zz_199 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_200 ), //i + .io_cpu_execute_address (_zz_201[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_104[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_202 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_203[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_204 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_205 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_206 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_207[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_208 ), //i + .io_cpu_writeBack_fence_SR (_zz_209 ), //i + .io_cpu_writeBack_fence_SO (_zz_210 ), //i + .io_cpu_writeBack_fence_SI (_zz_211 ), //i + .io_cpu_writeBack_fence_PW (_zz_212 ), //i + .io_cpu_writeBack_fence_PR (_zz_213 ), //i + .io_cpu_writeBack_fence_PO (_zz_214 ), //i + .io_cpu_writeBack_fence_PI (_zz_215 ), //i + .io_cpu_writeBack_fence_FM (_zz_216[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_217 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_218 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_356) + 2'b00 : begin + _zz_221 = DBusCachedPlugin_redoBranch_payload; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; + 2'b01 : begin + _zz_221 = CsrPlugin_jumpInterface_payload; end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; + 2'b10 : begin + _zz_221 = BranchPlugin_jumpInterface_payload; end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end + default : begin + _zz_221 = IBusCachedPlugin_predictionJumpInterface_payload; end - end - end - - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_12_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); - end - _zz_3_ <= lineLoader_flushCounter[7]; - if(_zz_13_)begin - lineLoader_flushCounter <= (8'b00000000); - end + endcase end -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, - input [1:0] io_cpu_execute_args_size, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - input io_cpu_memory_isRemoved, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - output io_cpu_memory_mmuBus_cmd_isValid, - output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, - output io_cpu_memory_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, - input io_cpu_memory_mmuBus_rsp_isIoAccess, - input io_cpu_memory_mmuBus_rsp_allowRead, - input io_cpu_memory_mmuBus_rsp_allowWrite, - input io_cpu_memory_mmuBus_rsp_allowExecute, - input io_cpu_memory_mmuBus_rsp_exception, - input io_cpu_memory_mmuBus_rsp_refilling, - output io_cpu_memory_mmuBus_end, - input io_cpu_memory_mmuBus_busy, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output reg io_cpu_flush_ready, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, - output reg io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire _zz_16_; - wire _zz_17_; - wire [0:0] _zz_18_; - wire [0:0] _zz_19_; - wire [0:0] _zz_20_; - wire [2:0] _zz_21_; - wire [1:0] _zz_22_; - wire [21:0] _zz_23_; - reg _zz_1_; - reg _zz_2_; - wire haltCpu; - reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3_; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4_; - wire _zz_5_; - wire [31:0] ways_0_dataReadRsp; - reg [3:0] _zz_6_; - wire [3:0] stage0_mask; - wire [0:0] stage0_colisions; - reg stageA_request_wr; - reg [31:0] stageA_request_data; - reg [1:0] stageA_request_size; - reg [3:0] stageA_mask; - wire stageA_wayHits_0; - reg [0:0] stage0_colisions_regNextWhen; - wire [0:0] _zz_7_; - wire [0:0] stageA_colisions; - reg stageB_request_wr; - reg [31:0] stageB_request_data; - reg [1:0] stageB_request_size; - reg stageB_mmuRspFreeze; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg [31:0] stageB_dataReadRsp_0; - wire [0:0] _zz_8_; - reg [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - reg [3:0] stageB_mask; - reg [0:0] stageB_colisions; - reg stageB_loaderValid; - reg stageB_flusher_valid; - wire [31:0] stageB_requestDataBypass; - wire stageB_isAmo; - reg stageB_memCmdSent; - wire [0:0] _zz_9_; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [2:0] loader_counter_valueNext; - reg [2:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_24_; - reg [7:0] _zz_25_; - reg [7:0] _zz_26_; - reg [7:0] _zz_27_; - assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); - assign _zz_15_ = (loader_valid && io_mem_rsp_valid); - assign _zz_16_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - assign _zz_17_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign _zz_18_ = _zz_4_[0 : 0]; - assign _zz_19_ = _zz_4_[1 : 1]; - assign _zz_20_ = loader_counter_willIncrement; - assign _zz_21_ = {2'd0, _zz_20_}; - assign _zz_22_ = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_23_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_23_; - end + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_3_) begin - _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; - end + always @(*) begin + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; + endcase end - - always @ (*) begin - _zz_11_ = {_zz_27_, _zz_26_, _zz_25_, _zz_24_}; + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase end - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1_) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1_) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1_) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1_) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_5_) begin - _zz_24_ <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_25_ <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_26_ <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_27_ <= ways_0_data_symbol3[dataReadCmd_payload]; - end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase end - - always @ (*) begin - _zz_1_ = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_1_ = 1'b1; - end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase end - - always @ (*) begin - _zz_2_ = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_2_ = 1'b1; - end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase end - - assign haltCpu = 1'b0; - assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4_ = _zz_10_; - assign ways_0_tagsReadRsp_valid = _zz_18_[0]; - assign ways_0_tagsReadRsp_error = _zz_19_[0]; - assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; - assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRsp = _zz_11_; - always @ (*) begin - tagsReadCmd_valid = 1'b0; - if(_zz_12_)begin - tagsReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase end - - always @ (*) begin - tagsReadCmd_payload = (7'bxxxxxxx); - if(_zz_12_)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; - end + always @(*) begin + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_valid = 1'b0; - if(_zz_12_)begin - dataReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_payload = (10'bxxxxxxxxxx); - if(_zz_12_)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end + always @(*) begin + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; - end - if(_zz_13_)begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_way = (1'bx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = (1'b1); - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_address = (7'bxxxxxxx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_valid = 1'b1; - end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); - end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((stageB_request_wr && stageB_waysHit))begin - dataWriteCmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - dataWriteCmd_valid = 1'b0; - end - if(_zz_15_)begin - dataWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_way = (1'bx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_way = stageB_waysHits; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_address = (10'bxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; - end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_data = stageB_requestDataBypass; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_mask = (4'bxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_mask = stageB_mask; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_mask = (4'b1111); - end + always @(*) begin + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; + endcase end - - always @ (*) begin - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_6_ = (4'b0001); - end - 2'b01 : begin - _zz_6_ = (4'b0011); - end - default : begin - _zz_6_ = (4'b1111); - end + always @(*) begin + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; endcase end - - assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); - assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; - assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; - assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); - always @ (*) begin - stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin - stageB_mmuRspFreeze = 1'b1; - end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; + endcase end - - assign _zz_8_[0] = stageA_wayHits_0; - assign stageB_waysHit = (stageB_waysHits != (1'b0)); - assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - if(io_mem_cmd_ready)begin - stageB_loaderValid = 1'b1; - end - end - end - end - if(_zz_13_)begin - stageB_loaderValid = 1'b0; - end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(_zz_14_)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - if(_zz_13_)begin - io_cpu_writeBack_haltIt = 1'b0; - end + always @(*) begin + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(_zz_16_)begin - io_cpu_flush_ready = 1'b1; - end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase end - - assign stageB_requestDataBypass = stageB_request_data; - assign stageB_isAmo = 1'b0; - always @ (*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin - io_cpu_redo = 1'b1; - end - end - end - end - if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin - io_cpu_redo = 1'b1; - end - if(loader_valid)begin - io_cpu_redo = 1'b1; - end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); - end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase end - - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_valid = (! stageB_memCmdSent); - end else begin - if(_zz_14_)begin - if(stageB_request_wr)begin - io_mem_cmd_valid = 1'b1; - end - end else begin - if((! stageB_memCmdSent))begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - io_mem_cmd_valid = 1'b0; - end + always @(*) begin + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; - end - end - end + always @(*) begin + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_length = (3'bxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - io_mem_cmd_payload_length = (3'b111); - end - end - end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_last = 1'bx; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - io_mem_cmd_payload_last = 1'b1; - end - end - end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - always @ (*) begin - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_data = io_mem_rsp_payload_data; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - end - - assign _zz_9_[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin - loader_counter_willIncrement = 1'b0; - if(_zz_15_)begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_21_); - if(loader_counter_willClear)begin - loader_counter_valueNext = (3'b000); - end - end - - always @ (posedge clk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; - stageA_request_size <= io_cpu_execute_args_size; - end - if((! io_cpu_memory_isStuck))begin - stageA_mask <= stage0_mask; - end - if((! io_cpu_memory_isStuck))begin - stage0_colisions_regNextWhen <= stage0_colisions; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; - stageB_request_size <= stageA_request_size; - end - if(_zz_17_)begin - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_waysHits <= _zz_8_; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_mask <= stageA_mask; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_colisions <= stageA_colisions; - end - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); - end - end - - always @ (posedge clk) begin - if(reset) begin - stageB_flusher_valid <= 1'b1; - stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); - stageB_memCmdSent <= 1'b0; - loader_valid <= 1'b0; - loader_counter_value <= (3'b000); - loader_waysAllocator <= (1'b1); - loader_error <= 1'b0; - end else begin - if(_zz_17_)begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; - end - if(stageB_flusher_valid)begin - if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); - end else begin - stageB_flusher_valid <= 1'b0; - end - end - if(_zz_16_)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); - stageB_flusher_valid <= 1'b1; - end - if(io_mem_cmd_ready)begin - stageB_memCmdSent <= 1'b1; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_memCmdSent <= 1'b0; - end - if(stageB_loaderValid)begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(_zz_15_)begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_counter_willOverflow)begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - end - if((! loader_valid))begin - loader_waysAllocator <= _zz_22_[0:0]; - end - end - end - -endmodule - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset); - wire _zz_238_; - wire _zz_239_; - wire _zz_240_; - wire _zz_241_; - wire [31:0] _zz_242_; - wire _zz_243_; - wire _zz_244_; - wire _zz_245_; - wire [31:0] _zz_246_; - reg _zz_247_; - wire _zz_248_; - wire [31:0] _zz_249_; - wire _zz_250_; - wire [31:0] _zz_251_; - reg _zz_252_; - wire _zz_253_; - wire _zz_254_; - wire [31:0] _zz_255_; - wire _zz_256_; - wire _zz_257_; - reg [31:0] _zz_258_; - reg [31:0] _zz_259_; - reg [31:0] _zz_260_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_error; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1__io_cpu_memory_isWrite; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; - wire dataCache_1__io_cpu_memory_mmuBus_end; - wire dataCache_1__io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1__io_cpu_writeBack_data; - wire dataCache_1__io_cpu_writeBack_mmuException; - wire dataCache_1__io_cpu_writeBack_unalignedAccess; - wire dataCache_1__io_cpu_writeBack_accessError; - wire dataCache_1__io_cpu_writeBack_isWrite; - wire dataCache_1__io_cpu_flush_ready; - wire dataCache_1__io_cpu_redo; - wire dataCache_1__io_mem_cmd_valid; - wire dataCache_1__io_mem_cmd_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_payload_length; - wire dataCache_1__io_mem_cmd_payload_last; - wire _zz_261_; - wire _zz_262_; - wire _zz_263_; - wire _zz_264_; - wire _zz_265_; - wire _zz_266_; - wire _zz_267_; - wire _zz_268_; - wire _zz_269_; - wire _zz_270_; - wire _zz_271_; - wire _zz_272_; - wire _zz_273_; - wire _zz_274_; - wire _zz_275_; - wire [1:0] _zz_276_; - wire _zz_277_; - wire _zz_278_; - wire _zz_279_; - wire _zz_280_; - wire _zz_281_; - wire _zz_282_; - wire _zz_283_; - wire _zz_284_; - wire _zz_285_; - wire _zz_286_; - wire _zz_287_; - wire _zz_288_; - wire [1:0] _zz_289_; - wire _zz_290_; - wire _zz_291_; - wire _zz_292_; - wire _zz_293_; - wire _zz_294_; - wire _zz_295_; - wire _zz_296_; - wire [4:0] _zz_297_; - wire [1:0] _zz_298_; - wire [1:0] _zz_299_; - wire [1:0] _zz_300_; - wire _zz_301_; - wire [1:0] _zz_302_; - wire [4:0] _zz_303_; - wire [2:0] _zz_304_; - wire [31:0] _zz_305_; - wire [2:0] _zz_306_; - wire [31:0] _zz_307_; - wire [31:0] _zz_308_; - wire [11:0] _zz_309_; - wire [11:0] _zz_310_; - wire [2:0] _zz_311_; - wire [31:0] _zz_312_; - wire [11:0] _zz_313_; - wire [31:0] _zz_314_; - wire [19:0] _zz_315_; - wire [11:0] _zz_316_; - wire [2:0] _zz_317_; - wire [2:0] _zz_318_; - wire [0:0] _zz_319_; - wire [0:0] _zz_320_; - wire [0:0] _zz_321_; - wire [0:0] _zz_322_; - wire [0:0] _zz_323_; - wire [0:0] _zz_324_; - wire [0:0] _zz_325_; - wire [0:0] _zz_326_; - wire [0:0] _zz_327_; - wire [0:0] _zz_328_; - wire [0:0] _zz_329_; - wire [0:0] _zz_330_; - wire [0:0] _zz_331_; - wire [0:0] _zz_332_; - wire [0:0] _zz_333_; - wire [0:0] _zz_334_; - wire [0:0] _zz_335_; - wire [0:0] _zz_336_; - wire [2:0] _zz_337_; - wire [4:0] _zz_338_; - wire [11:0] _zz_339_; - wire [11:0] _zz_340_; - wire [31:0] _zz_341_; - wire [31:0] _zz_342_; - wire [31:0] _zz_343_; - wire [31:0] _zz_344_; - wire [31:0] _zz_345_; - wire [31:0] _zz_346_; - wire [31:0] _zz_347_; - wire [32:0] _zz_348_; - wire [31:0] _zz_349_; - wire [32:0] _zz_350_; - wire [11:0] _zz_351_; - wire [19:0] _zz_352_; - wire [11:0] _zz_353_; - wire [2:0] _zz_354_; - wire [1:0] _zz_355_; - wire [1:0] _zz_356_; - wire [51:0] _zz_357_; - wire [51:0] _zz_358_; - wire [51:0] _zz_359_; - wire [32:0] _zz_360_; - wire [51:0] _zz_361_; - wire [49:0] _zz_362_; - wire [51:0] _zz_363_; - wire [49:0] _zz_364_; - wire [51:0] _zz_365_; - wire [65:0] _zz_366_; - wire [65:0] _zz_367_; - wire [31:0] _zz_368_; - wire [31:0] _zz_369_; - wire [0:0] _zz_370_; - wire [5:0] _zz_371_; - wire [32:0] _zz_372_; - wire [32:0] _zz_373_; - wire [31:0] _zz_374_; - wire [31:0] _zz_375_; - wire [32:0] _zz_376_; - wire [32:0] _zz_377_; - wire [32:0] _zz_378_; - wire [0:0] _zz_379_; - wire [32:0] _zz_380_; - wire [0:0] _zz_381_; - wire [32:0] _zz_382_; - wire [0:0] _zz_383_; - wire [31:0] _zz_384_; - wire [0:0] _zz_385_; - wire [0:0] _zz_386_; - wire [0:0] _zz_387_; - wire [0:0] _zz_388_; - wire [0:0] _zz_389_; - wire [0:0] _zz_390_; - wire [0:0] _zz_391_; - wire [26:0] _zz_392_; - wire _zz_393_; - wire _zz_394_; - wire [2:0] _zz_395_; - wire _zz_396_; - wire _zz_397_; - wire [6:0] _zz_398_; - wire [4:0] _zz_399_; - wire _zz_400_; - wire [4:0] _zz_401_; - wire [0:0] _zz_402_; - wire [7:0] _zz_403_; - wire _zz_404_; - wire [0:0] _zz_405_; - wire [0:0] _zz_406_; - wire [31:0] _zz_407_; - wire [31:0] _zz_408_; - wire [31:0] _zz_409_; - wire _zz_410_; - wire [0:0] _zz_411_; - wire [0:0] _zz_412_; - wire _zz_413_; - wire [0:0] _zz_414_; - wire [25:0] _zz_415_; - wire [31:0] _zz_416_; - wire [0:0] _zz_417_; - wire [3:0] _zz_418_; - wire [0:0] _zz_419_; - wire [3:0] _zz_420_; - wire [1:0] _zz_421_; - wire [1:0] _zz_422_; - wire _zz_423_; - wire [0:0] _zz_424_; - wire [21:0] _zz_425_; - wire [31:0] _zz_426_; - wire [31:0] _zz_427_; - wire [31:0] _zz_428_; - wire _zz_429_; - wire [0:0] _zz_430_; - wire [0:0] _zz_431_; - wire [31:0] _zz_432_; - wire [31:0] _zz_433_; - wire _zz_434_; - wire [0:0] _zz_435_; - wire [0:0] _zz_436_; - wire [31:0] _zz_437_; - wire [31:0] _zz_438_; - wire [31:0] _zz_439_; - wire [31:0] _zz_440_; - wire [31:0] _zz_441_; - wire [31:0] _zz_442_; - wire _zz_443_; - wire [0:0] _zz_444_; - wire [0:0] _zz_445_; - wire _zz_446_; - wire [0:0] _zz_447_; - wire [18:0] _zz_448_; - wire [31:0] _zz_449_; - wire [31:0] _zz_450_; - wire [31:0] _zz_451_; - wire [31:0] _zz_452_; - wire [31:0] _zz_453_; - wire [31:0] _zz_454_; - wire [31:0] _zz_455_; - wire [31:0] _zz_456_; - wire [31:0] _zz_457_; - wire [31:0] _zz_458_; - wire [31:0] _zz_459_; - wire [31:0] _zz_460_; - wire [31:0] _zz_461_; - wire [0:0] _zz_462_; - wire [0:0] _zz_463_; - wire _zz_464_; - wire [0:0] _zz_465_; - wire [16:0] _zz_466_; - wire [31:0] _zz_467_; - wire [31:0] _zz_468_; - wire [0:0] _zz_469_; - wire [1:0] _zz_470_; - wire _zz_471_; - wire _zz_472_; - wire [0:0] _zz_473_; - wire [0:0] _zz_474_; - wire _zz_475_; - wire [0:0] _zz_476_; - wire [12:0] _zz_477_; - wire [31:0] _zz_478_; - wire [31:0] _zz_479_; - wire [31:0] _zz_480_; - wire [31:0] _zz_481_; - wire [31:0] _zz_482_; - wire [31:0] _zz_483_; - wire [31:0] _zz_484_; - wire [31:0] _zz_485_; - wire [0:0] _zz_486_; - wire [0:0] _zz_487_; - wire [1:0] _zz_488_; - wire [1:0] _zz_489_; - wire _zz_490_; - wire [0:0] _zz_491_; - wire [9:0] _zz_492_; - wire [31:0] _zz_493_; - wire [31:0] _zz_494_; - wire [31:0] _zz_495_; - wire _zz_496_; - wire _zz_497_; - wire [0:0] _zz_498_; - wire [1:0] _zz_499_; - wire [3:0] _zz_500_; - wire [3:0] _zz_501_; - wire _zz_502_; - wire [0:0] _zz_503_; - wire [6:0] _zz_504_; - wire [31:0] _zz_505_; - wire [31:0] _zz_506_; - wire [31:0] _zz_507_; - wire [31:0] _zz_508_; - wire [31:0] _zz_509_; - wire [31:0] _zz_510_; - wire [31:0] _zz_511_; - wire _zz_512_; - wire [0:0] _zz_513_; - wire [0:0] _zz_514_; - wire _zz_515_; - wire _zz_516_; - wire _zz_517_; - wire [2:0] _zz_518_; - wire [2:0] _zz_519_; - wire _zz_520_; - wire [0:0] _zz_521_; - wire [3:0] _zz_522_; - wire [31:0] _zz_523_; - wire [31:0] _zz_524_; - wire [31:0] _zz_525_; - wire [31:0] _zz_526_; - wire [31:0] _zz_527_; - wire [31:0] _zz_528_; - wire [31:0] _zz_529_; - wire [31:0] _zz_530_; - wire _zz_531_; - wire [0:0] _zz_532_; - wire [0:0] _zz_533_; - wire [0:0] _zz_534_; - wire [0:0] _zz_535_; - wire [1:0] _zz_536_; - wire [1:0] _zz_537_; - wire _zz_538_; - wire [0:0] _zz_539_; - wire [1:0] _zz_540_; - wire [31:0] _zz_541_; - wire [31:0] _zz_542_; - wire [31:0] _zz_543_; - wire [31:0] _zz_544_; - wire [31:0] _zz_545_; - wire _zz_546_; - wire _zz_547_; - wire _zz_548_; - wire [0:0] _zz_549_; - wire [0:0] _zz_550_; - wire [4:0] _zz_551_; - wire [4:0] _zz_552_; - wire [31:0] _zz_553_; - wire [31:0] _zz_554_; - wire [31:0] _zz_555_; - wire _zz_556_; - wire _zz_557_; - wire [31:0] _zz_558_; - wire [31:0] _zz_559_; - wire [31:0] _zz_560_; - wire _zz_561_; - wire [0:0] _zz_562_; - wire [13:0] _zz_563_; - wire [31:0] _zz_564_; - wire [31:0] _zz_565_; - wire [31:0] _zz_566_; - wire _zz_567_; - wire [0:0] _zz_568_; - wire [7:0] _zz_569_; - wire [31:0] _zz_570_; - wire [31:0] _zz_571_; - wire [31:0] _zz_572_; - wire _zz_573_; - wire [0:0] _zz_574_; - wire [1:0] _zz_575_; - wire _zz_576_; - wire _zz_577_; - wire _zz_578_; - wire decode_SRC_LESS_UNSIGNED; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire decode_PREDICTION_HAD_BRANCHED2; - wire [31:0] execute_MUL_LL; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_8_; - wire `AluCtrlEnum_defaultEncoding_type _zz_9_; - wire `AluCtrlEnum_defaultEncoding_type _zz_10_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12_; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire decode_IS_DIV; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_13_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_14_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_15_; - wire decode_CSR_WRITE_OPCODE; - wire [33:0] execute_MUL_LH; - wire decode_IS_RS2_SIGNED; - wire [31:0] execute_SHIFT_RIGHT; - wire [51:0] memory_MUL_LOW; - wire memory_IS_MUL; - wire execute_IS_MUL; - wire decode_IS_MUL; - wire [33:0] execute_MUL_HL; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire decode_CSR_READ_OPCODE; - wire decode_SRC2_FORCE_ZERO; - wire decode_IS_RS1_SIGNED; - wire [31:0] memory_PC; - wire decode_IS_CSR; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_16_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_17_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_18_; - wire execute_BRANCH_DO; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_19_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire [31:0] execute_BRANCH_CALC; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_24_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_26_; - wire decode_MEMORY_MANAGMENT; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire [51:0] _zz_27_; - wire [33:0] _zz_28_; - wire [33:0] _zz_29_; - wire [33:0] _zz_30_; - wire [31:0] _zz_31_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_32_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; - wire _zz_34_; - wire _zz_35_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_36_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_37_; - wire [31:0] execute_PC; - wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_38_; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_39_; - wire _zz_40_; - wire _zz_41_; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_42_; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_43_; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_44_; - wire [31:0] _zz_45_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_46_; - wire _zz_47_; - wire [31:0] _zz_48_; - wire [31:0] _zz_49_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_50_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_51_; - wire [31:0] _zz_52_; - wire execute_IS_RVC; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_53_; - wire [31:0] _zz_54_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_55_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_56_; - wire [31:0] _zz_57_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; - wire [31:0] _zz_59_; - wire _zz_60_; - reg _zz_61_; - wire [31:0] _zz_62_; - wire [31:0] _zz_63_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_64_; - wire _zz_65_; - wire _zz_66_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_67_; - wire _zz_68_; - wire _zz_69_; - wire _zz_70_; - wire _zz_71_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_72_; - wire _zz_73_; - wire _zz_74_; - wire _zz_75_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_76_; - wire `AluCtrlEnum_defaultEncoding_type _zz_77_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_78_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_79_; - wire _zz_80_; - wire _zz_81_; - wire _zz_82_; - wire _zz_83_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_84_; - wire _zz_85_; - wire _zz_86_; - wire _zz_87_; - wire _zz_88_; - reg [31:0] _zz_89_; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_ENABLE; - wire [1:0] _zz_90_; - wire execute_MEMORY_MANAGMENT; - wire [31:0] execute_RS2; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_91_; - reg _zz_92_; - reg _zz_93_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_94_; - reg [31:0] _zz_95_; - reg [31:0] _zz_96_; - wire [31:0] decode_PC; - wire [31:0] _zz_97_; - wire _zz_98_; - wire [31:0] _zz_99_; - wire [31:0] _zz_100_; - wire [31:0] decode_INSTRUCTION; - wire [31:0] _zz_101_; - wire decode_IS_RVC; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - wire decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - wire execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - wire execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_predictionJumpInterface_valid; - (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; - wire IBusCachedPlugin_decodePrediction_cmd_hadBranch; - wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire DBusCachedPlugin_mmuBus_rsp_allowRead; - wire DBusCachedPlugin_mmuBus_rsp_allowWrite; - wire DBusCachedPlugin_mmuBus_rsp_allowExecute; - wire DBusCachedPlugin_mmuBus_rsp_exception; - wire DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - wire CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - wire CsrPlugin_allowInterrupts; - wire CsrPlugin_allowException; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_102_; - wire [4:0] _zz_103_; - wire _zz_104_; - wire _zz_105_; - wire _zz_106_; - wire _zz_107_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - reg [31:0] IBusCachedPlugin_decodePc_pcReg /* verilator public */ ; - wire [31:0] IBusCachedPlugin_decodePc_pcPlus; - wire IBusCachedPlugin_decodePc_injectedDecode; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_108_; - wire _zz_109_; - wire _zz_110_; - wire _zz_111_; - reg _zz_112_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_output_valid; - wire IBusCachedPlugin_iBusRsp_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; - wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; - wire IBusCachedPlugin_decompressor_inputBeforeStage_valid; - wire IBusCachedPlugin_decompressor_inputBeforeStage_ready; - wire [31:0] IBusCachedPlugin_decompressor_inputBeforeStage_payload_pc; - wire IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_error; - wire [31:0] IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_inst; - wire IBusCachedPlugin_decompressor_inputBeforeStage_payload_isRvc; - reg IBusCachedPlugin_decompressor_bufferValid; - reg [15:0] IBusCachedPlugin_decompressor_bufferData; - wire [31:0] IBusCachedPlugin_decompressor_raw; - wire IBusCachedPlugin_decompressor_isRvc; - wire [15:0] _zz_113_; - reg [31:0] IBusCachedPlugin_decompressor_decompressed; - wire [4:0] _zz_114_; - wire [4:0] _zz_115_; - wire [11:0] _zz_116_; - wire _zz_117_; - reg [11:0] _zz_118_; - wire _zz_119_; - reg [9:0] _zz_120_; - wire [20:0] _zz_121_; - wire _zz_122_; - reg [14:0] _zz_123_; - wire _zz_124_; - reg [2:0] _zz_125_; - wire _zz_126_; - reg [9:0] _zz_127_; - wire [20:0] _zz_128_; - wire _zz_129_; - reg [4:0] _zz_130_; - wire [12:0] _zz_131_; - wire [4:0] _zz_132_; - wire [4:0] _zz_133_; - wire [4:0] _zz_134_; - wire _zz_135_; - reg [2:0] _zz_136_; - reg [2:0] _zz_137_; - wire _zz_138_; - reg [6:0] _zz_139_; - reg IBusCachedPlugin_decompressor_bufferFill; - wire IBusCachedPlugin_injector_decodeInput_valid; - wire IBusCachedPlugin_injector_decodeInput_ready; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; - wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; - reg _zz_140_; - reg [31:0] _zz_141_; - reg _zz_142_; - reg [31:0] _zz_143_; - reg _zz_144_; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_decodeRemoved; - reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; - wire _zz_145_; - reg [18:0] _zz_146_; - wire _zz_147_; - reg [10:0] _zz_148_; - wire _zz_149_; - reg [18:0] _zz_150_; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_151_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; - wire dBus_cmd_payload_last; - wire dBus_rsp_valid; - wire [31:0] dBus_rsp_payload_data; - wire dBus_rsp_payload_error; - wire dataCache_1__io_mem_cmd_s2mPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; - reg _zz_152_; - reg _zz_153_; - reg [31:0] _zz_154_; - reg [31:0] _zz_155_; - reg [3:0] _zz_156_; - reg [2:0] _zz_157_; - reg _zz_158_; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg _zz_159_; - reg _zz_160_; - reg [31:0] _zz_161_; - reg [31:0] _zz_162_; - reg [3:0] _zz_163_; - reg [2:0] _zz_164_; - reg _zz_165_; - wire [31:0] _zz_166_; - reg [31:0] DBusCachedPlugin_rspCounter; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_167_; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_168_; - reg [31:0] _zz_169_; - wire _zz_170_; - reg [31:0] _zz_171_; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [31:0] _zz_172_; - wire _zz_173_; - wire _zz_174_; - wire _zz_175_; - wire _zz_176_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_177_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_178_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_179_; - wire `AluCtrlEnum_defaultEncoding_type _zz_180_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_181_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_182_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_183_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_184_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_185_; - reg [31:0] _zz_186_; - wire _zz_187_; - reg [19:0] _zz_188_; - wire _zz_189_; - reg [19:0] _zz_190_; - reg [31:0] _zz_191_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_192_; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_193_; - reg _zz_194_; - reg _zz_195_; - wire _zz_196_; - reg _zz_197_; - reg [4:0] _zz_198_; - reg [31:0] _zz_199_; - wire _zz_200_; - wire _zz_201_; - wire _zz_202_; - wire _zz_203_; - wire _zz_204_; - wire _zz_205_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_206_; - reg _zz_207_; - reg _zz_208_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_209_; - reg [19:0] _zz_210_; - wire _zz_211_; - reg [10:0] _zz_212_; - wire _zz_213_; - reg [18:0] _zz_214_; - wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] CsrPlugin_misa_base; - reg [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_215_; - wire _zz_216_; - wire _zz_217_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_218_; - wire _zz_219_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - reg CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - reg execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - wire [65:0] writeBack_MulPlugin_result; - reg [32:0] memory_DivPlugin_rs1; - reg [31:0] memory_DivPlugin_rs2; - reg [64:0] memory_DivPlugin_accumulator; - reg memory_DivPlugin_div_needRevert; - reg memory_DivPlugin_div_counter_willIncrement; - reg memory_DivPlugin_div_counter_willClear; - reg [5:0] memory_DivPlugin_div_counter_valueNext; - reg [5:0] memory_DivPlugin_div_counter_value; - wire memory_DivPlugin_div_counter_willOverflowIfInc; - wire memory_DivPlugin_div_counter_willOverflow; - reg memory_DivPlugin_div_done; - reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_220_; - wire [32:0] _zz_221_; - wire [32:0] _zz_222_; - wire [31:0] _zz_223_; - wire _zz_224_; - wire _zz_225_; - reg [32:0] _zz_226_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_227_; - wire [31:0] _zz_228_; - reg decode_to_execute_MEMORY_MANAGMENT; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg execute_to_memory_BRANCH_DO; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg decode_to_execute_IS_CSR; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg decode_to_execute_IS_RS1_SIGNED; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg decode_to_execute_CSR_READ_OPCODE; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg [33:0] execute_to_memory_MUL_HL; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg memory_to_writeBack_IS_MUL; - reg [51:0] memory_to_writeBack_MUL_LOW; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg decode_to_execute_IS_RS2_SIGNED; - reg [33:0] execute_to_memory_MUL_LH; - reg [31:0] decode_to_execute_RS1; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg [31:0] decode_to_execute_RS2; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg [31:0] execute_to_memory_MUL_LL; - reg decode_to_execute_IS_RVC; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg [33:0] execute_to_memory_MUL_HH; - reg [33:0] memory_to_writeBack_MUL_HH; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg decode_to_execute_MEMORY_WR; - reg execute_to_memory_MEMORY_WR; - reg memory_to_writeBack_MEMORY_WR; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg [2:0] _zz_229_; - reg _zz_230_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_231_; - wire _zz_232_; - wire _zz_233_; - wire _zz_234_; - wire _zz_235_; - wire _zz_236_; - reg _zz_237_; - reg [31:0] dBusWishbone_DAT_MISO_regNext; - `ifndef SYNTHESIS - reg [39:0] _zz_1__string; - reg [39:0] _zz_2__string; - reg [39:0] _zz_3__string; - reg [39:0] _zz_4__string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5__string; - reg [39:0] _zz_6__string; - reg [39:0] _zz_7__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_8__string; - reg [63:0] _zz_9__string; - reg [63:0] _zz_10__string; - reg [31:0] _zz_11__string; - reg [31:0] _zz_12__string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_13__string; - reg [23:0] _zz_14__string; - reg [23:0] _zz_15__string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_16__string; - reg [95:0] _zz_17__string; - reg [95:0] _zz_18__string; - reg [71:0] _zz_19__string; - reg [71:0] _zz_20__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_21__string; - reg [71:0] _zz_22__string; - reg [71:0] _zz_23__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_24__string; - reg [39:0] _zz_25__string; - reg [39:0] _zz_26__string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_32__string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_33__string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_36__string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_39__string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_44__string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_46__string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_51__string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_53__string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_56__string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_58__string; - reg [39:0] _zz_67__string; - reg [39:0] _zz_72__string; - reg [31:0] _zz_76__string; - reg [63:0] _zz_77__string; - reg [23:0] _zz_78__string; - reg [71:0] _zz_79__string; - reg [95:0] _zz_84__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_94__string; - reg [95:0] _zz_177__string; - reg [71:0] _zz_178__string; - reg [23:0] _zz_179__string; - reg [63:0] _zz_180__string; - reg [31:0] _zz_181__string; - reg [39:0] _zz_182__string; - reg [39:0] _zz_183__string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; - `endif - - (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_261_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_262_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_263_ = 1'b1; - assign _zz_264_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_265_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_266_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_267_ = ((_zz_240_ && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! _zz_91_)); - assign _zz_268_ = ((_zz_240_ && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! _zz_92_)); - assign _zz_269_ = ((_zz_240_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! _zz_93_)); - assign _zz_270_ = ((_zz_240_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! 1'b0)); - assign _zz_271_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_272_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_273_ = (! memory_DivPlugin_div_done); - assign _zz_274_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_275_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_276_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_277_ = (IBusCachedPlugin_iBusRsp_output_valid && IBusCachedPlugin_iBusRsp_output_ready); - assign _zz_278_ = ((! (((! IBusCachedPlugin_decompressor_isRvc) && (! IBusCachedPlugin_iBusRsp_output_payload_pc[1])) && (! IBusCachedPlugin_decompressor_bufferValid))) && (! ((IBusCachedPlugin_decompressor_isRvc && IBusCachedPlugin_iBusRsp_output_payload_pc[1]) && IBusCachedPlugin_decompressor_inputBeforeStage_ready))); - assign _zz_279_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_280_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_281_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_282_ = (1'b0 || (! 1'b1)); - assign _zz_283_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_284_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_285_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_286_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_287_ = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_288_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_289_ = execute_INSTRUCTION[13 : 12]; - assign _zz_290_ = (! memory_arbitration_isStuck); - assign _zz_291_ = (iBus_cmd_valid || (_zz_229_ != (3'b000))); - assign _zz_292_ = (_zz_257_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); - assign _zz_293_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_294_ = ((_zz_215_ && 1'b1) && (! 1'b0)); - assign _zz_295_ = ((_zz_216_ && 1'b1) && (! 1'b0)); - assign _zz_296_ = ((_zz_217_ && 1'b1) && (! 1'b0)); - assign _zz_297_ = {_zz_113_[1 : 0],_zz_113_[15 : 13]}; - assign _zz_298_ = _zz_113_[6 : 5]; - assign _zz_299_ = _zz_113_[11 : 10]; - assign _zz_300_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_301_ = execute_INSTRUCTION[13]; - assign _zz_302_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_303_ = (_zz_102_ - (5'b00001)); - assign _zz_304_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_305_ = {29'd0, _zz_304_}; - assign _zz_306_ = (decode_IS_RVC ? (3'b010) : (3'b100)); - assign _zz_307_ = {29'd0, _zz_306_}; - assign _zz_308_ = {{_zz_123_,_zz_113_[6 : 2]},(12'b000000000000)}; - assign _zz_309_ = {{{(4'b0000),_zz_113_[8 : 7]},_zz_113_[12 : 9]},(2'b00)}; - assign _zz_310_ = {{{(4'b0000),_zz_113_[8 : 7]},_zz_113_[12 : 9]},(2'b00)}; - assign _zz_311_ = (decode_IS_RVC ? (3'b010) : (3'b100)); - assign _zz_312_ = {29'd0, _zz_311_}; - assign _zz_313_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_314_ = {{_zz_146_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_315_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_316_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_317_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); - assign _zz_318_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); - assign _zz_319_ = _zz_172_[1 : 1]; - assign _zz_320_ = _zz_172_[2 : 2]; - assign _zz_321_ = _zz_172_[3 : 3]; - assign _zz_322_ = _zz_172_[6 : 6]; - assign _zz_323_ = _zz_172_[7 : 7]; - assign _zz_324_ = _zz_172_[8 : 8]; - assign _zz_325_ = _zz_172_[9 : 9]; - assign _zz_326_ = _zz_172_[18 : 18]; - assign _zz_327_ = _zz_172_[19 : 19]; - assign _zz_328_ = _zz_172_[20 : 20]; - assign _zz_329_ = _zz_172_[23 : 23]; - assign _zz_330_ = _zz_172_[24 : 24]; - assign _zz_331_ = _zz_172_[25 : 25]; - assign _zz_332_ = _zz_172_[26 : 26]; - assign _zz_333_ = _zz_172_[29 : 29]; - assign _zz_334_ = _zz_172_[30 : 30]; - assign _zz_335_ = _zz_172_[31 : 31]; - assign _zz_336_ = execute_SRC_LESS; - assign _zz_337_ = (execute_IS_RVC ? (3'b010) : (3'b100)); - assign _zz_338_ = execute_INSTRUCTION[19 : 15]; - assign _zz_339_ = execute_INSTRUCTION[31 : 20]; - assign _zz_340_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_341_ = ($signed(_zz_342_) + $signed(_zz_345_)); - assign _zz_342_ = ($signed(_zz_343_) + $signed(_zz_344_)); - assign _zz_343_ = execute_SRC1; - assign _zz_344_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_345_ = (execute_SRC_USE_SUB_LESS ? _zz_346_ : _zz_347_); - assign _zz_346_ = (32'b00000000000000000000000000000001); - assign _zz_347_ = (32'b00000000000000000000000000000000); - assign _zz_348_ = ($signed(_zz_350_) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_349_ = _zz_348_[31 : 0]; - assign _zz_350_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_351_ = execute_INSTRUCTION[31 : 20]; - assign _zz_352_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_353_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_354_ = (execute_IS_RVC ? (3'b010) : (3'b100)); - assign _zz_355_ = (_zz_218_ & (~ _zz_356_)); - assign _zz_356_ = (_zz_218_ - (2'b01)); - assign _zz_357_ = ($signed(_zz_358_) + $signed(_zz_363_)); - assign _zz_358_ = ($signed(_zz_359_) + $signed(_zz_361_)); - assign _zz_359_ = (52'b0000000000000000000000000000000000000000000000000000); - assign _zz_360_ = {1'b0,memory_MUL_LL}; - assign _zz_361_ = {{19{_zz_360_[32]}}, _zz_360_}; - assign _zz_362_ = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_363_ = {{2{_zz_362_[49]}}, _zz_362_}; - assign _zz_364_ = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_365_ = {{2{_zz_364_[49]}}, _zz_364_}; - assign _zz_366_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_367_ = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_368_ = writeBack_MUL_LOW[31 : 0]; - assign _zz_369_ = writeBack_MulPlugin_result[63 : 32]; - assign _zz_370_ = memory_DivPlugin_div_counter_willIncrement; - assign _zz_371_ = {5'd0, _zz_370_}; - assign _zz_372_ = {1'd0, memory_DivPlugin_rs2}; - assign _zz_373_ = {_zz_220_,(! _zz_222_[32])}; - assign _zz_374_ = _zz_222_[31:0]; - assign _zz_375_ = _zz_221_[31:0]; - assign _zz_376_ = _zz_377_; - assign _zz_377_ = _zz_378_; - assign _zz_378_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_223_) : _zz_223_)} + _zz_380_); - assign _zz_379_ = memory_DivPlugin_div_needRevert; - assign _zz_380_ = {32'd0, _zz_379_}; - assign _zz_381_ = _zz_225_; - assign _zz_382_ = {32'd0, _zz_381_}; - assign _zz_383_ = _zz_224_; - assign _zz_384_ = {31'd0, _zz_383_}; - assign _zz_385_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_386_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_387_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_388_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_389_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_390_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_391_ = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_392_ = (iBus_cmd_payload_address >>> 5); - assign _zz_393_ = 1'b1; - assign _zz_394_ = 1'b1; - assign _zz_395_ = {_zz_105_,{_zz_107_,_zz_106_}}; - assign _zz_396_ = (_zz_113_[11 : 10] == (2'b01)); - assign _zz_397_ = ((_zz_113_[11 : 10] == (2'b11)) && (_zz_113_[6 : 5] == (2'b00))); - assign _zz_398_ = (7'b0000000); - assign _zz_399_ = _zz_113_[6 : 2]; - assign _zz_400_ = _zz_113_[12]; - assign _zz_401_ = _zz_113_[11 : 7]; - assign _zz_402_ = decode_INSTRUCTION[31]; - assign _zz_403_ = decode_INSTRUCTION[19 : 12]; - assign _zz_404_ = decode_INSTRUCTION[20]; - assign _zz_405_ = decode_INSTRUCTION[31]; - assign _zz_406_ = decode_INSTRUCTION[7]; - assign _zz_407_ = (32'b00000000000000000000000001011000); - assign _zz_408_ = (decode_INSTRUCTION & (32'b00000000000000000100000001001000)); - assign _zz_409_ = (32'b00000000000000000100000000001000); - assign _zz_410_ = ((decode_INSTRUCTION & (32'b00000000000000000101000001001000)) == (32'b00000000000000000001000000001000)); - assign _zz_411_ = ((decode_INSTRUCTION & (32'b00000000001000000011000001010000)) == (32'b00000000000000000000000001010000)); - assign _zz_412_ = (1'b0); - assign _zz_413_ = (((decode_INSTRUCTION & _zz_416_) == (32'b00000000000000000000000001010000)) != (1'b0)); - assign _zz_414_ = ({_zz_175_,{_zz_417_,_zz_418_}} != (6'b000000)); - assign _zz_415_ = {({_zz_419_,_zz_420_} != (5'b00000)),{(_zz_421_ != _zz_422_),{_zz_423_,{_zz_424_,_zz_425_}}}}; - assign _zz_416_ = (32'b00000000010000000011000001010000); - assign _zz_417_ = ((decode_INSTRUCTION & _zz_426_) == (32'b00000000000000000001000000010000)); - assign _zz_418_ = {(_zz_427_ == _zz_428_),{_zz_429_,{_zz_430_,_zz_431_}}}; - assign _zz_419_ = _zz_174_; - assign _zz_420_ = {(_zz_432_ == _zz_433_),{_zz_434_,{_zz_435_,_zz_436_}}}; - assign _zz_421_ = {(_zz_437_ == _zz_438_),(_zz_439_ == _zz_440_)}; - assign _zz_422_ = (2'b00); - assign _zz_423_ = ((_zz_441_ == _zz_442_) != (1'b0)); - assign _zz_424_ = (_zz_443_ != (1'b0)); - assign _zz_425_ = {(_zz_444_ != _zz_445_),{_zz_446_,{_zz_447_,_zz_448_}}}; - assign _zz_426_ = (32'b00000000000000000001000000010000); - assign _zz_427_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_428_ = (32'b00000000000000000010000000010000); - assign _zz_429_ = ((decode_INSTRUCTION & _zz_449_) == (32'b00000000000000000000000000010000)); - assign _zz_430_ = (_zz_450_ == _zz_451_); - assign _zz_431_ = (_zz_452_ == _zz_453_); - assign _zz_432_ = (decode_INSTRUCTION & (32'b00000000000000000010000000110000)); - assign _zz_433_ = (32'b00000000000000000010000000010000); - assign _zz_434_ = ((decode_INSTRUCTION & _zz_454_) == (32'b00000000000000000000000000010000)); - assign _zz_435_ = (_zz_455_ == _zz_456_); - assign _zz_436_ = (_zz_457_ == _zz_458_); - assign _zz_437_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); - assign _zz_438_ = (32'b00000000000000000001000001010000); - assign _zz_439_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); - assign _zz_440_ = (32'b00000000000000000010000001010000); - assign _zz_441_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_442_ = (32'b00000000000000000000000000100000); - assign _zz_443_ = ((decode_INSTRUCTION & _zz_459_) == (32'b00000000000000000001000000000000)); - assign _zz_444_ = (_zz_460_ == _zz_461_); - assign _zz_445_ = (1'b0); - assign _zz_446_ = (_zz_176_ != (1'b0)); - assign _zz_447_ = (_zz_462_ != _zz_463_); - assign _zz_448_ = {_zz_464_,{_zz_465_,_zz_466_}}; - assign _zz_449_ = (32'b00000000000000000000000001010000); - assign _zz_450_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); - assign _zz_451_ = (32'b00000000000000000000000000000100); - assign _zz_452_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); - assign _zz_453_ = (32'b00000000000000000000000000000000); - assign _zz_454_ = (32'b00000000000000000001000000110000); - assign _zz_455_ = (decode_INSTRUCTION & (32'b00000010000000000010000001100000)); - assign _zz_456_ = (32'b00000000000000000010000000100000); - assign _zz_457_ = (decode_INSTRUCTION & (32'b00000010000000000011000000100000)); - assign _zz_458_ = (32'b00000000000000000000000000100000); - assign _zz_459_ = (32'b00000000000000000001000000000000); - assign _zz_460_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000)); - assign _zz_461_ = (32'b00000000000000000010000000000000); - assign _zz_462_ = _zz_176_; - assign _zz_463_ = (1'b0); - assign _zz_464_ = ({(_zz_467_ == _zz_468_),{_zz_174_,{_zz_469_,_zz_470_}}} != (5'b00000)); - assign _zz_465_ = ({_zz_175_,_zz_471_} != (2'b00)); - assign _zz_466_ = {(_zz_472_ != (1'b0)),{(_zz_473_ != _zz_474_),{_zz_475_,{_zz_476_,_zz_477_}}}}; - assign _zz_467_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000000)); - assign _zz_468_ = (32'b00000000000000000000000001000000); - assign _zz_469_ = ((decode_INSTRUCTION & _zz_478_) == (32'b00000000000000000100000000100000)); - assign _zz_470_ = {(_zz_479_ == _zz_480_),(_zz_481_ == _zz_482_)}; - assign _zz_471_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); - assign _zz_472_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); - assign _zz_473_ = ((decode_INSTRUCTION & _zz_483_) == (32'b00000000000000000100000000010000)); - assign _zz_474_ = (1'b0); - assign _zz_475_ = ((_zz_484_ == _zz_485_) != (1'b0)); - assign _zz_476_ = ({_zz_486_,_zz_487_} != (2'b00)); - assign _zz_477_ = {(_zz_488_ != _zz_489_),{_zz_490_,{_zz_491_,_zz_492_}}}; - assign _zz_478_ = (32'b00000000000000000100000000100000); - assign _zz_479_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110000)); - assign _zz_480_ = (32'b00000000000000000000000000010000); - assign _zz_481_ = (decode_INSTRUCTION & (32'b00000010000000000000000000100000)); - assign _zz_482_ = (32'b00000000000000000000000000100000); - assign _zz_483_ = (32'b00000000000000000100000000010100); - assign _zz_484_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); - assign _zz_485_ = (32'b00000000000000000010000000010000); - assign _zz_486_ = _zz_174_; - assign _zz_487_ = ((decode_INSTRUCTION & _zz_493_) == (32'b00000000000000000000000000100000)); - assign _zz_488_ = {_zz_174_,(_zz_494_ == _zz_495_)}; - assign _zz_489_ = (2'b00); - assign _zz_490_ = ({_zz_496_,_zz_497_} != (2'b00)); - assign _zz_491_ = ({_zz_498_,_zz_499_} != (3'b000)); - assign _zz_492_ = {(_zz_500_ != _zz_501_),{_zz_502_,{_zz_503_,_zz_504_}}}; - assign _zz_493_ = (32'b00000000000000000000000001110000); - assign _zz_494_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_495_ = (32'b00000000000000000000000000000000); - assign _zz_496_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000110100)) == (32'b00000000000000000101000000010000)); - assign _zz_497_ = ((decode_INSTRUCTION & (32'b00000010000000000111000001100100)) == (32'b00000000000000000101000000100000)); - assign _zz_498_ = ((decode_INSTRUCTION & _zz_505_) == (32'b01000000000000000001000000010000)); - assign _zz_499_ = {(_zz_506_ == _zz_507_),(_zz_508_ == _zz_509_)}; - assign _zz_500_ = {(_zz_510_ == _zz_511_),{_zz_512_,{_zz_513_,_zz_514_}}}; - assign _zz_501_ = (4'b0000); - assign _zz_502_ = ({_zz_515_,_zz_516_} != (2'b00)); - assign _zz_503_ = (_zz_517_ != (1'b0)); - assign _zz_504_ = {(_zz_518_ != _zz_519_),{_zz_520_,{_zz_521_,_zz_522_}}}; - assign _zz_505_ = (32'b01000000000000000011000001010100); - assign _zz_506_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_507_ = (32'b00000000000000000001000000010000); - assign _zz_508_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100)); - assign _zz_509_ = (32'b00000000000000000001000000010000); - assign _zz_510_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_511_ = (32'b00000000000000000000000000000000); - assign _zz_512_ = ((decode_INSTRUCTION & _zz_523_) == (32'b00000000000000000000000000000000)); - assign _zz_513_ = (_zz_524_ == _zz_525_); - assign _zz_514_ = (_zz_526_ == _zz_527_); - assign _zz_515_ = ((decode_INSTRUCTION & _zz_528_) == (32'b00000000000000000010000000000000)); - assign _zz_516_ = ((decode_INSTRUCTION & _zz_529_) == (32'b00000000000000000001000000000000)); - assign _zz_517_ = ((decode_INSTRUCTION & _zz_530_) == (32'b00000010000000000100000000100000)); - assign _zz_518_ = {_zz_531_,{_zz_532_,_zz_533_}}; - assign _zz_519_ = (3'b000); - assign _zz_520_ = ({_zz_534_,_zz_535_} != (2'b00)); - assign _zz_521_ = (_zz_536_ != _zz_537_); - assign _zz_522_ = {_zz_538_,{_zz_539_,_zz_540_}}; - assign _zz_523_ = (32'b00000000000000000000000000011000); - assign _zz_524_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); - assign _zz_525_ = (32'b00000000000000000010000000000000); - assign _zz_526_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); - assign _zz_527_ = (32'b00000000000000000001000000000000); - assign _zz_528_ = (32'b00000000000000000010000000010000); - assign _zz_529_ = (32'b00000000000000000101000000000000); - assign _zz_530_ = (32'b00000010000000000100000001100100); - assign _zz_531_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); - assign _zz_532_ = ((decode_INSTRUCTION & _zz_541_) == (32'b00000000000000000010000000010000)); - assign _zz_533_ = ((decode_INSTRUCTION & _zz_542_) == (32'b01000000000000000000000000110000)); - assign _zz_534_ = ((decode_INSTRUCTION & _zz_543_) == (32'b00000000000000000000000000000100)); - assign _zz_535_ = _zz_173_; - assign _zz_536_ = {(_zz_544_ == _zz_545_),_zz_173_}; - assign _zz_537_ = (2'b00); - assign _zz_538_ = ({_zz_546_,_zz_547_} != (2'b00)); - assign _zz_539_ = (_zz_548_ != (1'b0)); - assign _zz_540_ = {(_zz_549_ != _zz_550_),(_zz_551_ != _zz_552_)}; - assign _zz_541_ = (32'b00000000000000000010000000010100); - assign _zz_542_ = (32'b01000000000000000000000000110100); - assign _zz_543_ = (32'b00000000000000000000000000010100); - assign _zz_544_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_545_ = (32'b00000000000000000000000000000100); - assign _zz_546_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000)); - assign _zz_547_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100000)); - assign _zz_548_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001110100)) == (32'b00000010000000000000000000110000)); - assign _zz_549_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); - assign _zz_550_ = (1'b0); - assign _zz_551_ = {((decode_INSTRUCTION & (32'b00000000000000000010000001000000)) == (32'b00000000000000000010000001000000)),{((decode_INSTRUCTION & _zz_553_) == (32'b00000000000000000001000001000000)),{(_zz_554_ == _zz_555_),{_zz_556_,_zz_557_}}}}; - assign _zz_552_ = (5'b00000); - assign _zz_553_ = (32'b00000000000000000001000001000000); - assign _zz_554_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000)); - assign _zz_555_ = (32'b00000000000000000000000001000000); - assign _zz_556_ = ((decode_INSTRUCTION & (32'b00000000010000000000000001000000)) == (32'b00000000000000000000000001000000)); - assign _zz_557_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000111000)) == (32'b00000000000000000000000000000000)); - assign _zz_558_ = (32'b00000000000000000001000001111111); - assign _zz_559_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_560_ = (32'b00000000000000000010000001110011); - assign _zz_561_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_562_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_563_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_564_) == (32'b00000000000000000000000000000011)),{(_zz_565_ == _zz_566_),{_zz_567_,{_zz_568_,_zz_569_}}}}}}; - assign _zz_564_ = (32'b00000000000000000101000001011111); - assign _zz_565_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_566_ = (32'b00000000000000000000000001100011); - assign _zz_567_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_568_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_569_ = {((decode_INSTRUCTION & (32'b00000001111100000111000001111111)) == (32'b00000000000000000101000000001111)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_570_) == (32'b00000000000000000001000000010011)),{(_zz_571_ == _zz_572_),{_zz_573_,{_zz_574_,_zz_575_}}}}}}; - assign _zz_570_ = (32'b11111100000000000011000001111111); - assign _zz_571_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_572_ = (32'b00000000000000000101000000110011); - assign _zz_573_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_574_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_575_ = {((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)),((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011))}; - assign _zz_576_ = execute_INSTRUCTION[31]; - assign _zz_577_ = execute_INSTRUCTION[31]; - assign _zz_578_ = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_61_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_393_) begin - _zz_258_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end + always @(*) begin + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_394_) begin - _zz_259_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_238_), - .io_cpu_prefetch_isValid(_zz_239_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_240_), - .io_cpu_fetch_isStuck(_zz_241_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_242_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_cacheMiss(IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss), - .io_cpu_fetch_error(IBusCachedPlugin_cache_io_cpu_fetch_error), - .io_cpu_fetch_mmuRefilling(IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling), - .io_cpu_fetch_mmuException(IBusCachedPlugin_cache_io_cpu_fetch_mmuException), - .io_cpu_fetch_isUser(_zz_243_), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_244_), - .io_cpu_decode_isStuck(_zz_245_), - .io_cpu_decode_pc(_zz_246_), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_fill_valid(_zz_247_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); - DataCache dataCache_1_ ( - .io_cpu_execute_isValid(_zz_248_), - .io_cpu_execute_address(_zz_249_), - .io_cpu_execute_args_wr(execute_MEMORY_WR), - .io_cpu_execute_args_data(_zz_167_), - .io_cpu_execute_args_size(execute_DBusCachedPlugin_size), - .io_cpu_memory_isValid(_zz_250_), - .io_cpu_memory_isStuck(memory_arbitration_isStuck), - .io_cpu_memory_isRemoved(memory_arbitration_removeIt), - .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), - .io_cpu_memory_address(_zz_251_), - .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), - .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), - .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), - .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_252_), - .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), - .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), - .io_cpu_writeBack_isValid(_zz_253_), - .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), - .io_cpu_writeBack_isUser(_zz_254_), - .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), - .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), - .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), - .io_cpu_writeBack_address(_zz_255_), - .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), - .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), - .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), - .io_cpu_redo(dataCache_1__io_cpu_redo), - .io_cpu_flush_valid(_zz_256_), - .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), - .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), - .io_mem_cmd_ready(_zz_257_), - .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), - .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), - .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), - .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), - .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), - .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), - .io_mem_rsp_valid(dBus_rsp_valid), - .io_mem_rsp_payload_data(dBus_rsp_payload_data), - .io_mem_rsp_payload_error(dBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); always @(*) begin - case(_zz_395_) - 3'b000 : begin - _zz_260_ = DBusCachedPlugin_redoBranch_payload; - end - 3'b001 : begin - _zz_260_ = CsrPlugin_jumpInterface_payload; - end - 3'b010 : begin - _zz_260_ = BranchPlugin_jumpInterface_payload; - end - 3'b011 : begin - _zz_260_ = IBusCachedPlugin_redoBranch_payload; - end - default : begin - _zz_260_ = IBusCachedPlugin_predictionJumpInterface_payload; - end + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; endcase end - - `ifndef SYNTHESIS always @(*) begin - case(_zz_1_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_1__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL"; - default : _zz_1__string = "?????"; + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; endcase end always @(*) begin - case(_zz_2_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_2__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL"; - default : _zz_2__string = "?????"; + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_3_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_3__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL"; - default : _zz_3__string = "?????"; + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; endcase end always @(*) begin - case(_zz_4_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL"; - default : _zz_4__string = "?????"; + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; + case(_zz_30) + `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; + default : _zz_30_string = "????"; endcase end always @(*) begin - case(_zz_5_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL"; - default : _zz_5__string = "?????"; + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_6_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL"; - default : _zz_6__string = "?????"; + case(_zz_33) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; + default : _zz_33_string = "?????????"; endcase end always @(*) begin - case(_zz_7_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL"; - default : _zz_7__string = "?????"; + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(_zz_34) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; + default : _zz_34_string = "?????????"; endcase end always @(*) begin - case(_zz_8_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_8__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_8__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_8__string = "BITWISE "; - default : _zz_8__string = "????????"; + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_9_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_9__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_9__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_9__string = "BITWISE "; - default : _zz_9__string = "????????"; + case(_zz_36) + `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; + default : _zz_36_string = "???"; endcase end always @(*) begin - case(_zz_10_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10__string = "BITWISE "; - default : _zz_10__string = "????????"; + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_11_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR"; - default : _zz_11__string = "????"; + case(_zz_37) + `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; + default : _zz_37_string = "????????????"; endcase end always @(*) begin - case(_zz_12_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12__string = "JALR"; - default : _zz_12__string = "????"; + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(_zz_38) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; + default : _zz_38_string = "????????"; endcase end always @(*) begin - case(_zz_13_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_13__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_13__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_13__string = "PC "; - default : _zz_13__string = "???"; + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_14_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_14__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_14__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_14__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_14__string = "PC "; - default : _zz_14__string = "???"; + case(_zz_39) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; + default : _zz_39_string = "?????"; endcase end always @(*) begin - case(_zz_15_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_15__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_15__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_15__string = "PC "; - default : _zz_15__string = "???"; + case(_zz_43) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(_zz_44) + `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; + default : _zz_44_string = "????"; endcase end always @(*) begin - case(_zz_16_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_16__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_16__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_16__string = "URS1 "; - default : _zz_16__string = "????????????"; + case(_zz_45) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; + default : _zz_45_string = "?????????"; endcase end always @(*) begin - case(_zz_17_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_17__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_17__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_17__string = "URS1 "; - default : _zz_17__string = "????????????"; + case(_zz_46) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; + default : _zz_46_string = "?????"; endcase end always @(*) begin - case(_zz_18_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_18__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_18__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_18__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_18__string = "URS1 "; - default : _zz_18__string = "????????????"; + case(_zz_47) + `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; + default : _zz_47_string = "???"; endcase end always @(*) begin - case(_zz_19_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_19__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_19__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_19__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_19__string = "SRA_1 "; - default : _zz_19__string = "?????????"; + case(_zz_48) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; + default : _zz_48_string = "????????"; endcase end always @(*) begin - case(_zz_20_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 "; - default : _zz_20__string = "?????????"; + case(_zz_49) + `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; + default : _zz_49_string = "????????????"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_21_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 "; - default : _zz_21__string = "?????????"; + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; endcase end always @(*) begin - case(_zz_22_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; - default : _zz_22__string = "?????????"; + case(_zz_114) + `Src1CtrlEnum_defaultEncoding_RS : _zz_114_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_114_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_114_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_114_string = "URS1 "; + default : _zz_114_string = "????????????"; endcase end always @(*) begin - case(_zz_23_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 "; - default : _zz_23__string = "?????????"; + case(_zz_115) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_115_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_115_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_115_string = "BITWISE "; + default : _zz_115_string = "????????"; endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(_zz_116) + `Src2CtrlEnum_defaultEncoding_RS : _zz_116_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_116_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_116_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_116_string = "PC "; + default : _zz_116_string = "???"; endcase end always @(*) begin - case(_zz_24_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_24__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_24__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_24__string = "AND_1"; - default : _zz_24__string = "?????"; + case(_zz_117) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_117_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_117_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_117_string = "AND_1"; + default : _zz_117_string = "?????"; endcase end always @(*) begin - case(_zz_25_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25__string = "AND_1"; - default : _zz_25__string = "?????"; + case(_zz_118) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_118_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_118_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_118_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_118_string = "SRA_1 "; + default : _zz_118_string = "?????????"; endcase end always @(*) begin - case(_zz_26_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_26__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_26__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_26__string = "AND_1"; - default : _zz_26__string = "?????"; + case(_zz_119) + `BranchCtrlEnum_defaultEncoding_INC : _zz_119_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_119_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_119_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_119_string = "JALR"; + default : _zz_119_string = "????"; endcase end always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; + case(_zz_120) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_120_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_120_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_120_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_120_string = "ECALL"; + default : _zz_120_string = "?????"; endcase end always @(*) begin - case(_zz_32_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_32__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_32__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_32__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32__string = "ECALL"; - default : _zz_32__string = "?????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; - default : execute_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_33_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33__string = "ECALL"; - default : _zz_33__string = "?????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; - default : writeBack_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_36_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_36__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_36__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_36__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_36__string = "ECALL"; - default : _zz_36__string = "?????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_39_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_39__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_39__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_39__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_39__string = "JALR"; - default : _zz_39__string = "????"; - endcase - end - always @(*) begin - case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_44_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_44__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_44__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_44__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_44__string = "SRA_1 "; - default : _zz_44__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_46_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46__string = "SRA_1 "; - default : _zz_46__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; - default : execute_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_51_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_51__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_51__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_51__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_51__string = "PC "; - default : _zz_51__string = "???"; - endcase - end - always @(*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; - default : execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_53_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_53__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_53__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_53__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_53__string = "URS1 "; - default : _zz_53__string = "????????????"; - endcase - end - always @(*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_56_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; - default : _zz_56__string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_58_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; - default : _zz_58__string = "?????"; - endcase - end - always @(*) begin - case(_zz_67_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_67__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_67__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_67__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_67__string = "ECALL"; - default : _zz_67__string = "?????"; - endcase - end - always @(*) begin - case(_zz_72_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_72__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_72__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_72__string = "AND_1"; - default : _zz_72__string = "?????"; - endcase - end - always @(*) begin - case(_zz_76_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_76__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_76__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_76__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_76__string = "JALR"; - default : _zz_76__string = "????"; - endcase - end - always @(*) begin - case(_zz_77_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_77__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_77__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_77__string = "BITWISE "; - default : _zz_77__string = "????????"; - endcase - end - always @(*) begin - case(_zz_78_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_78__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_78__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_78__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_78__string = "PC "; - default : _zz_78__string = "???"; - endcase - end - always @(*) begin - case(_zz_79_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_79__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_79__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_79__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_79__string = "SRA_1 "; - default : _zz_79__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_84_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_84__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_84__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_84__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_84__string = "URS1 "; - default : _zz_84__string = "????????????"; - endcase - end - always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_94_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_94__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_94__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_94__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_94__string = "JALR"; - default : _zz_94__string = "????"; - endcase - end - always @(*) begin - case(_zz_177_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_177__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_177__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_177__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_177__string = "URS1 "; - default : _zz_177__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_178_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_178__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_178__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_178__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_178__string = "SRA_1 "; - default : _zz_178__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_179_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_179__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_179__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_179__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_179__string = "PC "; - default : _zz_179__string = "???"; - endcase - end - always @(*) begin - case(_zz_180_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_180__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_180__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_180__string = "BITWISE "; - default : _zz_180__string = "????????"; - endcase - end - always @(*) begin - case(_zz_181_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_181__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_181__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_181__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_181__string = "JALR"; - default : _zz_181__string = "????"; - endcase - end - always @(*) begin - case(_zz_182_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_182__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_182__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_182__string = "AND_1"; - default : _zz_182__string = "?????"; + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_183_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_183__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_183__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_183__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_183__string = "ECALL"; - default : _zz_183__string = "?????"; + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin @@ -3304,24 +2448,6 @@ module VexRiscv ( default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; - default : decode_to_execute_SRC2_CTRL_string = "???"; - endcase - end always @(*) begin case(decode_to_execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; @@ -3331,14 +2457,6 @@ module VexRiscv ( default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end always @(*) begin case(decode_to_execute_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; @@ -3368,57 +2486,58 @@ module VexRiscv ( end `endif - assign decode_SRC_LESS_UNSIGNED = _zz_81_; - assign _zz_1_ = _zz_2_; - assign _zz_3_ = _zz_4_; - assign decode_ENV_CTRL = _zz_5_; - assign _zz_6_ = _zz_7_; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_71_; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_75_; + assign memory_MUL_LOW = ($signed(_zz_264) + $signed(_zz_272)); assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = _zz_28_; - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_41_; - assign execute_MUL_LL = _zz_31_; - assign decode_ALU_CTRL = _zz_8_; - assign _zz_9_ = _zz_10_; - assign _zz_11_ = _zz_12_; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_274; + assign execute_REGFILE_WRITE_DATA = _zz_122; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_90_; - assign decode_IS_DIV = _zz_82_; - assign decode_SRC2_CTRL = _zz_13_; - assign _zz_14_ = _zz_15_; - assign decode_CSR_WRITE_OPCODE = _zz_35_; - assign execute_MUL_LH = _zz_30_; - assign decode_IS_RS2_SIGNED = _zz_74_; - assign execute_SHIFT_RIGHT = _zz_45_; - assign memory_MUL_LOW = _zz_27_; + assign execute_MEMORY_ADDRESS_LOW = _zz_201[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_276[0]; + assign decode_IS_RS1_SIGNED = _zz_277[0]; + assign decode_IS_DIV = _zz_278[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_86_; - assign execute_MUL_HL = _zz_29_; - assign execute_REGFILE_WRITE_DATA = _zz_57_; - assign decode_CSR_READ_OPCODE = _zz_34_; - assign decode_SRC2_FORCE_ZERO = _zz_55_; - assign decode_IS_RS1_SIGNED = _zz_73_; - assign memory_PC = execute_to_memory_PC; - assign decode_IS_CSR = _zz_70_; - assign decode_SRC1_CTRL = _zz_16_; - assign _zz_17_ = _zz_18_; - assign execute_BRANCH_DO = _zz_38_; - assign _zz_19_ = _zz_20_; - assign decode_SHIFT_CTRL = _zz_21_; - assign _zz_22_ = _zz_23_; + assign decode_IS_MUL = _zz_279[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_280[0]; + assign _zz_8 = _zz_9; + assign _zz_10 = _zz_11; + assign decode_SHIFT_CTRL = _zz_12; + assign _zz_13 = _zz_14; + assign decode_ALU_BITWISE_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_SRC_LESS_UNSIGNED = _zz_281[0]; + assign decode_MEMORY_MANAGMENT = _zz_282[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_283[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_284[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_285[0]; + assign decode_SRC2_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_ALU_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_SRC1_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_97_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_69_; - assign execute_BRANCH_CALC = _zz_37_; - assign decode_ALU_BITWISE_CTRL = _zz_24_; - assign _zz_25_ = _zz_26_; - assign decode_MEMORY_MANAGMENT = _zz_65_; + assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_287); + assign memory_PC = execute_to_memory_PC; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -3432,22 +2551,22 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_32_; - assign execute_ENV_CTRL = _zz_33_; - assign writeBack_ENV_CTRL = _zz_36_; + assign memory_ENV_CTRL = _zz_27; + assign execute_ENV_CTRL = _zz_28; + assign writeBack_ENV_CTRL = _zz_29; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_40_; + assign execute_BRANCH_COND_RESULT = _zz_139; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; - assign execute_BRANCH_CTRL = _zz_39_; - assign decode_RS2_USE = _zz_85_; - assign decode_RS1_USE = _zz_80_; + assign execute_BRANCH_CTRL = _zz_30; + assign decode_RS2_USE = _zz_288[0]; + assign decode_RS1_USE = _zz_289[0]; always @ (*) begin - _zz_42_ = execute_REGFILE_WRITE_DATA; - if(_zz_261_)begin - _zz_42_ = execute_CsrPlugin_readData; + _zz_31 = execute_REGFILE_WRITE_DATA; + if(_zz_222)begin + _zz_31 = execute_CsrPlugin_readData; end end @@ -3458,60 +2577,60 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - decode_RS2 = _zz_62_; - if(_zz_197_)begin - if((_zz_198_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_199_; + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_262_)begin - if(_zz_263_)begin - if(_zz_201_)begin - decode_RS2 = _zz_89_; + if(_zz_223)begin + if(_zz_224)begin + if(_zz_132)begin + decode_RS2 = _zz_50; end end end - if(_zz_264_)begin + if(_zz_225)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_203_)begin - decode_RS2 = _zz_43_; + if(_zz_134)begin + decode_RS2 = _zz_32; end end end - if(_zz_265_)begin + if(_zz_226)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_205_)begin - decode_RS2 = _zz_42_; + if(_zz_136)begin + decode_RS2 = _zz_31; end end end end always @ (*) begin - decode_RS1 = _zz_63_; - if(_zz_197_)begin - if((_zz_198_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_199_; + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_262_)begin - if(_zz_263_)begin - if(_zz_200_)begin - decode_RS1 = _zz_89_; + if(_zz_223)begin + if(_zz_224)begin + if(_zz_131)begin + decode_RS1 = _zz_50; end end end - if(_zz_264_)begin + if(_zz_225)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_202_)begin - decode_RS1 = _zz_43_; + if(_zz_133)begin + decode_RS1 = _zz_32; end end end - if(_zz_265_)begin + if(_zz_226)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_204_)begin - decode_RS1 = _zz_42_; + if(_zz_135)begin + decode_RS1 = _zz_31; end end end @@ -3519,72 +2638,71 @@ module VexRiscv ( assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_43_ = memory_REGFILE_WRITE_DATA; + _zz_32 = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_43_ = _zz_193_; + _zz_32 = _zz_130; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_43_ = memory_SHIFT_RIGHT; + _zz_32 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_266_)begin - _zz_43_ = memory_DivPlugin_div_result; + if(_zz_227)begin + _zz_32 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_44_; - assign execute_SHIFT_CTRL = _zz_46_; + assign memory_SHIFT_CTRL = _zz_33; + assign execute_SHIFT_CTRL = _zz_34; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_50_ = execute_PC; - assign execute_SRC2_CTRL = _zz_51_; + assign _zz_35 = execute_PC; + assign execute_SRC2_CTRL = _zz_36; assign execute_IS_RVC = decode_to_execute_IS_RVC; - assign execute_SRC1_CTRL = _zz_53_; - assign decode_SRC_USE_SUB_LESS = _zz_83_; - assign decode_SRC_ADD_ZERO = _zz_87_; - assign execute_SRC_ADD_SUB = _zz_49_; - assign execute_SRC_LESS = _zz_47_; - assign execute_ALU_CTRL = _zz_56_; - assign execute_SRC2 = _zz_52_; - assign execute_SRC1 = _zz_54_; - assign execute_ALU_BITWISE_CTRL = _zz_58_; - assign _zz_59_ = writeBack_INSTRUCTION; - assign _zz_60_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_61_ = 1'b0; + assign execute_SRC1_CTRL = _zz_37; + assign decode_SRC_USE_SUB_LESS = _zz_290[0]; + assign decode_SRC_ADD_ZERO = _zz_291[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_38; + assign execute_SRC2 = _zz_128; + assign execute_SRC1 = _zz_123; + assign execute_ALU_BITWISE_CTRL = _zz_39; + assign _zz_40 = writeBack_INSTRUCTION; + assign _zz_41 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_42 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_61_ = 1'b1; + _zz_42 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_101_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_decompressor_output_payload_rsp_inst); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_68_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_292[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_88_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_357) == 32'h00001073),{(_zz_358 == _zz_359),{_zz_360,{_zz_361,_zz_362}}}}}}} != 21'h0); always @ (*) begin - _zz_89_ = writeBack_REGFILE_WRITE_DATA; + _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_89_ = writeBack_DBusCachedPlugin_rspFormated; + _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_302_) + case(_zz_263) 2'b00 : begin - _zz_89_ = _zz_368_; + _zz_50 = _zz_329; end default : begin - _zz_89_ = _zz_369_; + _zz_50 = _zz_330; end endcase end @@ -3596,63 +2714,61 @@ module VexRiscv ( assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = _zz_48_; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_64_; - assign decode_FLUSH_ALL = _zz_66_; + assign decode_MEMORY_ENABLE = _zz_293[0]; + assign decode_FLUSH_ALL = _zz_294[0]; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_91_; - if(_zz_267_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_228)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin - _zz_91_ = _zz_92_; - if(_zz_268_)begin - _zz_91_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_229)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin - _zz_92_ = _zz_93_; - if(_zz_269_)begin - _zz_92_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_230)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_93_ = 1'b0; - if(_zz_270_)begin - _zz_93_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_231)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_94_; + assign decode_BRANCH_CTRL = _zz_51; always @ (*) begin - _zz_95_ = memory_FORMAL_PC_NEXT; + _zz_52 = memory_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin - _zz_95_ = BranchPlugin_jumpInterface_payload; + _zz_52 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_96_ = decode_FORMAL_PC_NEXT; + _zz_53 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_96_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_96_ = IBusCachedPlugin_redoBranch_payload; + _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; end end - assign decode_PC = _zz_100_; - assign decode_INSTRUCTION = _zz_99_; - assign decode_IS_RVC = _zz_98_; + assign decode_PC = IBusCachedPlugin_decodePc_pcReg; + assign decode_INSTRUCTION = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign decode_IS_RVC = IBusCachedPlugin_injector_decodeInput_payload_isRvc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -3664,20 +2780,20 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_194_ || _zz_195_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_271_)begin + if(_zz_232)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3688,35 +2804,38 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_271_)begin + if(_zz_232)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if((_zz_256_ && (! dataCache_1__io_cpu_flush_ready)))begin - execute_arbitration_haltItself = 1'b1; - end - if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + if(((_zz_217 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_272_)begin + if(_zz_233)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_261_)begin + if(_zz_222)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end end end - assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + end + always @ (*) begin execute_arbitration_removeIt = 1'b0; if(CsrPlugin_selfException_valid)begin @@ -3737,8 +2856,8 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_266_)begin - if(_zz_273_)begin + if(_zz_227)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end end @@ -3762,7 +2881,7 @@ module VexRiscv ( always @ (*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1__io_cpu_writeBack_haltIt)begin + if(dataCache_1_io_cpu_writeBack_haltIt)begin writeBack_arbitration_haltItself = 1'b1; end end @@ -3793,10 +2912,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_274_)begin + if(_zz_234)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_275_)begin + if(_zz_235)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3807,33 +2926,20 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_274_)begin + if(_zz_234)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_275_)begin + if(_zz_235)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - end - always @ (*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid)begin - IBusCachedPlugin_incomingInstruction = 1'b1; - end - if((IBusCachedPlugin_decompressor_bufferValid && (IBusCachedPlugin_decompressor_bufferData[1 : 0] != (2'b11))))begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_valid)begin IBusCachedPlugin_incomingInstruction = 1'b1; end if(IBusCachedPlugin_injector_decodeInput_valid)begin @@ -3841,23 +2947,31 @@ module VexRiscv ( end end + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_233)begin + CsrPlugin_inWfi = 1'b1; + end + end + + assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_274_)begin + if(_zz_234)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_275_)begin + if(_zz_235)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_274_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_234)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_275_)begin - case(_zz_276_) + if(_zz_235)begin + case(_zz_236) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3870,47 +2984,77 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); - assign _zz_102_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_103_ = (_zz_102_ & (~ _zz_303_)); - assign _zz_104_ = _zz_103_[3]; - assign _zz_105_ = _zz_103_[4]; - assign _zz_106_ = (_zz_103_[1] || _zz_104_); - assign _zz_107_ = (_zz_103_[2] || _zz_104_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_260_; - always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_54 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_55 = (_zz_54 & (~ _zz_295)); + assign _zz_56 = _zz_55[3]; + assign _zz_57 = (_zz_55[1] || _zz_56); + assign _zz_58 = (_zz_55[2] || _zz_56); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_221; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_305_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_297); if(IBusCachedPlugin_fetchPc_inc)begin IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; end + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_307_); + always @ (*) begin + IBusCachedPlugin_decodePc_flushed = 1'b0; + if(_zz_237)begin + IBusCachedPlugin_decodePc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_299); assign IBusCachedPlugin_decodePc_injectedDecode = 1'b0; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin @@ -3918,320 +3062,325 @@ module VexRiscv ( end end - assign _zz_108_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_108_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_108_); + assign _zz_59 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_59); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_59); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_109_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_109_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_110_; - assign _zz_110_ = ((1'b0 && (! _zz_111_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_111_ = _zz_112_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_111_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; always @ (*) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((IBusCachedPlugin_decompressor_bufferValid && IBusCachedPlugin_decompressor_isRvc))begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + if(IBusCachedPlugin_decompressor_throw2BytesReg)begin + IBusCachedPlugin_fetchPc_redo_payload[1] = 1'b1; end + end + + assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_61; + assign _zz_61 = ((1'b0 && (! _zz_62)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_62 = _zz_63; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_62; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if(IBusCachedPlugin_injector_decodeInput_valid)begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end - assign IBusCachedPlugin_decompressor_raw = (IBusCachedPlugin_decompressor_bufferValid ? {IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[15 : 0],IBusCachedPlugin_decompressor_bufferData} : {IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[31 : 16],(IBusCachedPlugin_iBusRsp_output_payload_pc[1] ? IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[31 : 16] : IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[15 : 0])}); - assign IBusCachedPlugin_decompressor_isRvc = (IBusCachedPlugin_decompressor_raw[1 : 0] != (2'b11)); - assign _zz_113_ = IBusCachedPlugin_decompressor_raw[15 : 0]; + assign IBusCachedPlugin_decompressor_input_valid = (IBusCachedPlugin_iBusRsp_output_valid && (! IBusCachedPlugin_iBusRsp_redoFetch)); + assign IBusCachedPlugin_decompressor_input_payload_pc = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign IBusCachedPlugin_decompressor_input_payload_rsp_error = IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + assign IBusCachedPlugin_decompressor_input_payload_rsp_inst = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + assign IBusCachedPlugin_decompressor_input_payload_isRvc = IBusCachedPlugin_iBusRsp_output_payload_isRvc; + assign IBusCachedPlugin_iBusRsp_output_ready = IBusCachedPlugin_decompressor_input_ready; + assign IBusCachedPlugin_decompressor_flushNext = 1'b0; + assign IBusCachedPlugin_decompressor_consumeCurrent = 1'b0; + assign IBusCachedPlugin_decompressor_isInputLowRvc = (IBusCachedPlugin_decompressor_input_payload_rsp_inst[1 : 0] != 2'b11); + assign IBusCachedPlugin_decompressor_isInputHighRvc = (IBusCachedPlugin_decompressor_input_payload_rsp_inst[17 : 16] != 2'b11); + assign IBusCachedPlugin_decompressor_throw2Bytes = (IBusCachedPlugin_decompressor_throw2BytesReg || IBusCachedPlugin_decompressor_input_payload_pc[1]); + assign IBusCachedPlugin_decompressor_unaligned = (IBusCachedPlugin_decompressor_throw2Bytes || IBusCachedPlugin_decompressor_bufferValid); + assign IBusCachedPlugin_decompressor_raw = (IBusCachedPlugin_decompressor_bufferValid ? {IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0],IBusCachedPlugin_decompressor_bufferData} : {IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16],(IBusCachedPlugin_decompressor_throw2Bytes ? IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16] : IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0])}); + assign IBusCachedPlugin_decompressor_isRvc = (IBusCachedPlugin_decompressor_raw[1 : 0] != 2'b11); + assign _zz_64 = IBusCachedPlugin_decompressor_raw[15 : 0]; always @ (*) begin - IBusCachedPlugin_decompressor_decompressed = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - case(_zz_297_) - 5'b00000 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{{{(2'b00),_zz_113_[10 : 7]},_zz_113_[12 : 11]},_zz_113_[5]},_zz_113_[6]},(2'b00)},(5'b00010)},(3'b000)},_zz_115_},(7'b0010011)}; + IBusCachedPlugin_decompressor_decompressed = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(_zz_258) + 5'h0 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{{{{{2'b00,_zz_64[10 : 7]},_zz_64[12 : 11]},_zz_64[5]},_zz_64[6]},2'b00},5'h02},3'b000},_zz_66},7'h13}; end - 5'b00010 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_116_,_zz_114_},(3'b010)},_zz_115_},(7'b0000011)}; + 5'h02 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_67,_zz_65},3'b010},_zz_66},7'h03}; end - 5'b00110 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_116_[11 : 5],_zz_115_},_zz_114_},(3'b010)},_zz_116_[4 : 0]},(7'b0100011)}; + 5'h06 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_67[11 : 5],_zz_66},_zz_65},3'b010},_zz_67[4 : 0]},7'h23}; end - 5'b01000 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_118_,_zz_113_[11 : 7]},(3'b000)},_zz_113_[11 : 7]},(7'b0010011)}; + 5'h08 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_69,_zz_64[11 : 7]},3'b000},_zz_64[11 : 7]},7'h13}; end - 5'b01001 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_121_[20],_zz_121_[10 : 1]},_zz_121_[11]},_zz_121_[19 : 12]},_zz_133_},(7'b1101111)}; + 5'h09 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_72[20],_zz_72[10 : 1]},_zz_72[11]},_zz_72[19 : 12]},_zz_84},7'h6f}; end - 5'b01010 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_118_,(5'b00000)},(3'b000)},_zz_113_[11 : 7]},(7'b0010011)}; + 5'h0a : begin + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_69,5'h0},3'b000},_zz_64[11 : 7]},7'h13}; end - 5'b01011 : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_113_[11 : 7] == (5'b00010)) ? {{{{{{{{{_zz_125_,_zz_113_[4 : 3]},_zz_113_[5]},_zz_113_[2]},_zz_113_[6]},(4'b0000)},_zz_113_[11 : 7]},(3'b000)},_zz_113_[11 : 7]},(7'b0010011)} : {{_zz_308_[31 : 12],_zz_113_[11 : 7]},(7'b0110111)}); + 5'h0b : begin + IBusCachedPlugin_decompressor_decompressed = ((_zz_64[11 : 7] == 5'h02) ? {{{{{{{{{_zz_76,_zz_64[4 : 3]},_zz_64[5]},_zz_64[2]},_zz_64[6]},4'b0000},_zz_64[11 : 7]},3'b000},_zz_64[11 : 7]},7'h13} : {{_zz_300[31 : 12],_zz_64[11 : 7]},7'h37}); end - 5'b01100 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_113_[11 : 10] == (2'b10)) ? _zz_139_ : {{(1'b0),(_zz_396_ || _zz_397_)},(5'b00000)}),(((! _zz_113_[11]) || _zz_135_) ? _zz_113_[6 : 2] : _zz_115_)},_zz_114_},_zz_137_},_zz_114_},(_zz_135_ ? (7'b0010011) : (7'b0110011))}; + 5'h0c : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_64[11 : 10] == 2'b10) ? _zz_90 : {{1'b0,(_zz_375 || _zz_376)},5'h0}),(((! _zz_64[11]) || _zz_86) ? _zz_64[6 : 2] : _zz_66)},_zz_65},_zz_88},_zz_65},(_zz_86 ? 7'h13 : 7'h33)}; end - 5'b01101 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_128_[20],_zz_128_[10 : 1]},_zz_128_[11]},_zz_128_[19 : 12]},_zz_132_},(7'b1101111)}; + 5'h0d : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_79[20],_zz_79[10 : 1]},_zz_79[11]},_zz_79[19 : 12]},_zz_83},7'h6f}; end - 5'b01110 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_131_[12],_zz_131_[10 : 5]},_zz_132_},_zz_114_},(3'b000)},_zz_131_[4 : 1]},_zz_131_[11]},(7'b1100011)}; + 5'h0e : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_82[12],_zz_82[10 : 5]},_zz_83},_zz_65},3'b000},_zz_82[4 : 1]},_zz_82[11]},7'h63}; end - 5'b01111 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_131_[12],_zz_131_[10 : 5]},_zz_132_},_zz_114_},(3'b001)},_zz_131_[4 : 1]},_zz_131_[11]},(7'b1100011)}; + 5'h0f : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_82[12],_zz_82[10 : 5]},_zz_83},_zz_65},3'b001},_zz_82[4 : 1]},_zz_82[11]},7'h63}; end - 5'b10000 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{(7'b0000000),_zz_113_[6 : 2]},_zz_113_[11 : 7]},(3'b001)},_zz_113_[11 : 7]},(7'b0010011)}; + 5'h10 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{7'h0,_zz_64[6 : 2]},_zz_64[11 : 7]},3'b001},_zz_64[11 : 7]},7'h13}; end - 5'b10010 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{{(4'b0000),_zz_113_[3 : 2]},_zz_113_[12]},_zz_113_[6 : 4]},(2'b00)},_zz_134_},(3'b010)},_zz_113_[11 : 7]},(7'b0000011)}; + 5'h12 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{{{{4'b0000,_zz_64[3 : 2]},_zz_64[12]},_zz_64[6 : 4]},2'b00},_zz_85},3'b010},_zz_64[11 : 7]},7'h03}; end - 5'b10100 : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_113_[12 : 2] == (11'b10000000000)) ? (32'b00000000000100000000000001110011) : ((_zz_113_[6 : 2] == (5'b00000)) ? {{{{(12'b000000000000),_zz_113_[11 : 7]},(3'b000)},(_zz_113_[12] ? _zz_133_ : _zz_132_)},(7'b1100111)} : {{{{{_zz_398_,_zz_399_},(_zz_400_ ? _zz_401_ : _zz_132_)},(3'b000)},_zz_113_[11 : 7]},(7'b0110011)})); + 5'h14 : begin + IBusCachedPlugin_decompressor_decompressed = ((_zz_64[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_64[6 : 2] == 5'h0) ? {{{{12'h0,_zz_64[11 : 7]},3'b000},(_zz_64[12] ? _zz_84 : _zz_83)},7'h67} : {{{{{_zz_377,_zz_378},(_zz_379 ? _zz_380 : _zz_83)},3'b000},_zz_64[11 : 7]},7'h33})); end - 5'b10110 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_309_[11 : 5],_zz_113_[6 : 2]},_zz_134_},(3'b010)},_zz_310_[4 : 0]},(7'b0100011)}; + 5'h16 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_301[11 : 5],_zz_64[6 : 2]},_zz_85},3'b010},_zz_302[4 : 0]},7'h23}; end default : begin end endcase end - assign _zz_114_ = {(2'b01),_zz_113_[9 : 7]}; - assign _zz_115_ = {(2'b01),_zz_113_[4 : 2]}; - assign _zz_116_ = {{{{(5'b00000),_zz_113_[5]},_zz_113_[12 : 10]},_zz_113_[6]},(2'b00)}; - assign _zz_117_ = _zz_113_[12]; - always @ (*) begin - _zz_118_[11] = _zz_117_; - _zz_118_[10] = _zz_117_; - _zz_118_[9] = _zz_117_; - _zz_118_[8] = _zz_117_; - _zz_118_[7] = _zz_117_; - _zz_118_[6] = _zz_117_; - _zz_118_[5] = _zz_117_; - _zz_118_[4 : 0] = _zz_113_[6 : 2]; - end - - assign _zz_119_ = _zz_113_[12]; - always @ (*) begin - _zz_120_[9] = _zz_119_; - _zz_120_[8] = _zz_119_; - _zz_120_[7] = _zz_119_; - _zz_120_[6] = _zz_119_; - _zz_120_[5] = _zz_119_; - _zz_120_[4] = _zz_119_; - _zz_120_[3] = _zz_119_; - _zz_120_[2] = _zz_119_; - _zz_120_[1] = _zz_119_; - _zz_120_[0] = _zz_119_; - end - - assign _zz_121_ = {{{{{{{{_zz_120_,_zz_113_[8]},_zz_113_[10 : 9]},_zz_113_[6]},_zz_113_[7]},_zz_113_[2]},_zz_113_[11]},_zz_113_[5 : 3]},(1'b0)}; - assign _zz_122_ = _zz_113_[12]; - always @ (*) begin - _zz_123_[14] = _zz_122_; - _zz_123_[13] = _zz_122_; - _zz_123_[12] = _zz_122_; - _zz_123_[11] = _zz_122_; - _zz_123_[10] = _zz_122_; - _zz_123_[9] = _zz_122_; - _zz_123_[8] = _zz_122_; - _zz_123_[7] = _zz_122_; - _zz_123_[6] = _zz_122_; - _zz_123_[5] = _zz_122_; - _zz_123_[4] = _zz_122_; - _zz_123_[3] = _zz_122_; - _zz_123_[2] = _zz_122_; - _zz_123_[1] = _zz_122_; - _zz_123_[0] = _zz_122_; - end - - assign _zz_124_ = _zz_113_[12]; - always @ (*) begin - _zz_125_[2] = _zz_124_; - _zz_125_[1] = _zz_124_; - _zz_125_[0] = _zz_124_; - end - - assign _zz_126_ = _zz_113_[12]; - always @ (*) begin - _zz_127_[9] = _zz_126_; - _zz_127_[8] = _zz_126_; - _zz_127_[7] = _zz_126_; - _zz_127_[6] = _zz_126_; - _zz_127_[5] = _zz_126_; - _zz_127_[4] = _zz_126_; - _zz_127_[3] = _zz_126_; - _zz_127_[2] = _zz_126_; - _zz_127_[1] = _zz_126_; - _zz_127_[0] = _zz_126_; - end - - assign _zz_128_ = {{{{{{{{_zz_127_,_zz_113_[8]},_zz_113_[10 : 9]},_zz_113_[6]},_zz_113_[7]},_zz_113_[2]},_zz_113_[11]},_zz_113_[5 : 3]},(1'b0)}; - assign _zz_129_ = _zz_113_[12]; - always @ (*) begin - _zz_130_[4] = _zz_129_; - _zz_130_[3] = _zz_129_; - _zz_130_[2] = _zz_129_; - _zz_130_[1] = _zz_129_; - _zz_130_[0] = _zz_129_; - end - - assign _zz_131_ = {{{{{_zz_130_,_zz_113_[6 : 5]},_zz_113_[2]},_zz_113_[11 : 10]},_zz_113_[4 : 3]},(1'b0)}; - assign _zz_132_ = (5'b00000); - assign _zz_133_ = (5'b00001); - assign _zz_134_ = (5'b00010); - assign _zz_135_ = (_zz_113_[11 : 10] != (2'b11)); - always @ (*) begin - case(_zz_298_) + assign _zz_65 = {2'b01,_zz_64[9 : 7]}; + assign _zz_66 = {2'b01,_zz_64[4 : 2]}; + assign _zz_67 = {{{{5'h0,_zz_64[5]},_zz_64[12 : 10]},_zz_64[6]},2'b00}; + assign _zz_68 = _zz_64[12]; + always @ (*) begin + _zz_69[11] = _zz_68; + _zz_69[10] = _zz_68; + _zz_69[9] = _zz_68; + _zz_69[8] = _zz_68; + _zz_69[7] = _zz_68; + _zz_69[6] = _zz_68; + _zz_69[5] = _zz_68; + _zz_69[4 : 0] = _zz_64[6 : 2]; + end + + assign _zz_70 = _zz_64[12]; + always @ (*) begin + _zz_71[9] = _zz_70; + _zz_71[8] = _zz_70; + _zz_71[7] = _zz_70; + _zz_71[6] = _zz_70; + _zz_71[5] = _zz_70; + _zz_71[4] = _zz_70; + _zz_71[3] = _zz_70; + _zz_71[2] = _zz_70; + _zz_71[1] = _zz_70; + _zz_71[0] = _zz_70; + end + + assign _zz_72 = {{{{{{{{_zz_71,_zz_64[8]},_zz_64[10 : 9]},_zz_64[6]},_zz_64[7]},_zz_64[2]},_zz_64[11]},_zz_64[5 : 3]},1'b0}; + assign _zz_73 = _zz_64[12]; + always @ (*) begin + _zz_74[14] = _zz_73; + _zz_74[13] = _zz_73; + _zz_74[12] = _zz_73; + _zz_74[11] = _zz_73; + _zz_74[10] = _zz_73; + _zz_74[9] = _zz_73; + _zz_74[8] = _zz_73; + _zz_74[7] = _zz_73; + _zz_74[6] = _zz_73; + _zz_74[5] = _zz_73; + _zz_74[4] = _zz_73; + _zz_74[3] = _zz_73; + _zz_74[2] = _zz_73; + _zz_74[1] = _zz_73; + _zz_74[0] = _zz_73; + end + + assign _zz_75 = _zz_64[12]; + always @ (*) begin + _zz_76[2] = _zz_75; + _zz_76[1] = _zz_75; + _zz_76[0] = _zz_75; + end + + assign _zz_77 = _zz_64[12]; + always @ (*) begin + _zz_78[9] = _zz_77; + _zz_78[8] = _zz_77; + _zz_78[7] = _zz_77; + _zz_78[6] = _zz_77; + _zz_78[5] = _zz_77; + _zz_78[4] = _zz_77; + _zz_78[3] = _zz_77; + _zz_78[2] = _zz_77; + _zz_78[1] = _zz_77; + _zz_78[0] = _zz_77; + end + + assign _zz_79 = {{{{{{{{_zz_78,_zz_64[8]},_zz_64[10 : 9]},_zz_64[6]},_zz_64[7]},_zz_64[2]},_zz_64[11]},_zz_64[5 : 3]},1'b0}; + assign _zz_80 = _zz_64[12]; + always @ (*) begin + _zz_81[4] = _zz_80; + _zz_81[3] = _zz_80; + _zz_81[2] = _zz_80; + _zz_81[1] = _zz_80; + _zz_81[0] = _zz_80; + end + + assign _zz_82 = {{{{{_zz_81,_zz_64[6 : 5]},_zz_64[2]},_zz_64[11 : 10]},_zz_64[4 : 3]},1'b0}; + assign _zz_83 = 5'h0; + assign _zz_84 = 5'h01; + assign _zz_85 = 5'h02; + assign _zz_86 = (_zz_64[11 : 10] != 2'b11); + always @ (*) begin + case(_zz_259) 2'b00 : begin - _zz_136_ = (3'b000); + _zz_87 = 3'b000; end 2'b01 : begin - _zz_136_ = (3'b100); + _zz_87 = 3'b100; end 2'b10 : begin - _zz_136_ = (3'b110); + _zz_87 = 3'b110; end default : begin - _zz_136_ = (3'b111); + _zz_87 = 3'b111; end endcase end always @ (*) begin - case(_zz_299_) + case(_zz_260) 2'b00 : begin - _zz_137_ = (3'b101); + _zz_88 = 3'b101; end 2'b01 : begin - _zz_137_ = (3'b101); + _zz_88 = 3'b101; end 2'b10 : begin - _zz_137_ = (3'b111); + _zz_88 = 3'b111; end default : begin - _zz_137_ = _zz_136_; + _zz_88 = _zz_87; end endcase end - assign _zz_138_ = _zz_113_[12]; - always @ (*) begin - _zz_139_[6] = _zz_138_; - _zz_139_[5] = _zz_138_; - _zz_139_[4] = _zz_138_; - _zz_139_[3] = _zz_138_; - _zz_139_[2] = _zz_138_; - _zz_139_[1] = _zz_138_; - _zz_139_[0] = _zz_138_; - end - - assign IBusCachedPlugin_decompressor_inputBeforeStage_valid = (IBusCachedPlugin_decompressor_isRvc ? (IBusCachedPlugin_decompressor_bufferValid || IBusCachedPlugin_iBusRsp_output_valid) : (IBusCachedPlugin_iBusRsp_output_valid && (IBusCachedPlugin_decompressor_bufferValid || (! IBusCachedPlugin_iBusRsp_output_payload_pc[1])))); - assign IBusCachedPlugin_decompressor_inputBeforeStage_payload_pc = IBusCachedPlugin_iBusRsp_output_payload_pc; - assign IBusCachedPlugin_decompressor_inputBeforeStage_payload_isRvc = IBusCachedPlugin_decompressor_isRvc; - assign IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_inst = (IBusCachedPlugin_decompressor_isRvc ? IBusCachedPlugin_decompressor_decompressed : IBusCachedPlugin_decompressor_raw); - assign IBusCachedPlugin_iBusRsp_output_ready = ((! IBusCachedPlugin_decompressor_inputBeforeStage_valid) || (! (((! IBusCachedPlugin_decompressor_inputBeforeStage_ready) || ((IBusCachedPlugin_decompressor_isRvc && (! IBusCachedPlugin_iBusRsp_output_payload_pc[1])) && (IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[17 : 16] != (2'b11)))) || (((! IBusCachedPlugin_decompressor_isRvc) && IBusCachedPlugin_decompressor_bufferValid) && (IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[17 : 16] != (2'b11)))))); - always @ (*) begin - IBusCachedPlugin_decompressor_bufferFill = 1'b0; - if(_zz_277_)begin - if(_zz_278_)begin - IBusCachedPlugin_decompressor_bufferFill = 1'b1; - end - end - end - - assign IBusCachedPlugin_decompressor_inputBeforeStage_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); - assign IBusCachedPlugin_injector_decodeInput_valid = _zz_140_; - assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_141_; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_142_; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_143_; - assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_144_; - assign _zz_101_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_inst); + assign _zz_89 = _zz_64[12]; + always @ (*) begin + _zz_90[6] = _zz_89; + _zz_90[5] = _zz_89; + _zz_90[4] = _zz_89; + _zz_90[3] = _zz_89; + _zz_90[2] = _zz_89; + _zz_90[1] = _zz_89; + _zz_90[0] = _zz_89; + end + + assign IBusCachedPlugin_decompressor_output_valid = (IBusCachedPlugin_decompressor_input_valid && (! ((IBusCachedPlugin_decompressor_throw2Bytes && (! IBusCachedPlugin_decompressor_bufferValid)) && (! IBusCachedPlugin_decompressor_isInputHighRvc)))); + assign IBusCachedPlugin_decompressor_output_payload_pc = IBusCachedPlugin_decompressor_input_payload_pc; + assign IBusCachedPlugin_decompressor_output_payload_isRvc = IBusCachedPlugin_decompressor_isRvc; + assign IBusCachedPlugin_decompressor_output_payload_rsp_inst = (IBusCachedPlugin_decompressor_isRvc ? IBusCachedPlugin_decompressor_decompressed : IBusCachedPlugin_decompressor_raw); + assign IBusCachedPlugin_decompressor_input_ready = (IBusCachedPlugin_decompressor_output_ready && (((! IBusCachedPlugin_iBusRsp_stages_1_input_valid) || IBusCachedPlugin_decompressor_flushNext) || ((! (IBusCachedPlugin_decompressor_bufferValid && IBusCachedPlugin_decompressor_isInputHighRvc)) && (! (((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && IBusCachedPlugin_decompressor_isInputHighRvc))))); + assign IBusCachedPlugin_decompressor_bufferFill = (((((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && (! IBusCachedPlugin_decompressor_isInputHighRvc)) || (IBusCachedPlugin_decompressor_bufferValid && (! IBusCachedPlugin_decompressor_isInputHighRvc))) || ((IBusCachedPlugin_decompressor_throw2Bytes && (! IBusCachedPlugin_decompressor_isRvc)) && (! IBusCachedPlugin_decompressor_isInputHighRvc))); + assign IBusCachedPlugin_decompressor_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); + assign IBusCachedPlugin_injector_decodeInput_valid = _zz_91; + assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_92; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_93; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_94; + assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_95; assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - assign decode_arbitration_isValid = (IBusCachedPlugin_injector_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - assign _zz_100_ = IBusCachedPlugin_decodePc_pcReg; - assign _zz_99_ = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - assign _zz_98_ = IBusCachedPlugin_injector_decodeInput_payload_isRvc; - assign _zz_97_ = (decode_PC + _zz_312_); - assign _zz_145_ = _zz_313_[11]; - always @ (*) begin - _zz_146_[18] = _zz_145_; - _zz_146_[17] = _zz_145_; - _zz_146_[16] = _zz_145_; - _zz_146_[15] = _zz_145_; - _zz_146_[14] = _zz_145_; - _zz_146_[13] = _zz_145_; - _zz_146_[12] = _zz_145_; - _zz_146_[11] = _zz_145_; - _zz_146_[10] = _zz_145_; - _zz_146_[9] = _zz_145_; - _zz_146_[8] = _zz_145_; - _zz_146_[7] = _zz_145_; - _zz_146_[6] = _zz_145_; - _zz_146_[5] = _zz_145_; - _zz_146_[4] = _zz_145_; - _zz_146_[3] = _zz_145_; - _zz_146_[2] = _zz_145_; - _zz_146_[1] = _zz_145_; - _zz_146_[0] = _zz_145_; - end - - assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_314_[31])); + assign decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; + assign _zz_96 = _zz_303[11]; + always @ (*) begin + _zz_97[18] = _zz_96; + _zz_97[17] = _zz_96; + _zz_97[16] = _zz_96; + _zz_97[15] = _zz_96; + _zz_97[14] = _zz_96; + _zz_97[13] = _zz_96; + _zz_97[12] = _zz_96; + _zz_97[11] = _zz_96; + _zz_97[10] = _zz_96; + _zz_97[9] = _zz_96; + _zz_97[8] = _zz_96; + _zz_97[7] = _zz_96; + _zz_97[6] = _zz_96; + _zz_97[5] = _zz_96; + _zz_97[4] = _zz_96; + _zz_97[3] = _zz_96; + _zz_97[2] = _zz_96; + _zz_97[1] = _zz_96; + _zz_97[0] = _zz_96; + end + + assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_304[31])); assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_147_ = _zz_315_[19]; - always @ (*) begin - _zz_148_[10] = _zz_147_; - _zz_148_[9] = _zz_147_; - _zz_148_[8] = _zz_147_; - _zz_148_[7] = _zz_147_; - _zz_148_[6] = _zz_147_; - _zz_148_[5] = _zz_147_; - _zz_148_[4] = _zz_147_; - _zz_148_[3] = _zz_147_; - _zz_148_[2] = _zz_147_; - _zz_148_[1] = _zz_147_; - _zz_148_[0] = _zz_147_; - end - - assign _zz_149_ = _zz_316_[11]; - always @ (*) begin - _zz_150_[18] = _zz_149_; - _zz_150_[17] = _zz_149_; - _zz_150_[16] = _zz_149_; - _zz_150_[15] = _zz_149_; - _zz_150_[14] = _zz_149_; - _zz_150_[13] = _zz_149_; - _zz_150_[12] = _zz_149_; - _zz_150_[11] = _zz_149_; - _zz_150_[10] = _zz_149_; - _zz_150_[9] = _zz_149_; - _zz_150_[8] = _zz_149_; - _zz_150_[7] = _zz_149_; - _zz_150_[6] = _zz_149_; - _zz_150_[5] = _zz_149_; - _zz_150_[4] = _zz_149_; - _zz_150_[3] = _zz_149_; - _zz_150_[2] = _zz_149_; - _zz_150_[1] = _zz_149_; - _zz_150_[0] = _zz_149_; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_148_,{{{_zz_402_,_zz_403_},_zz_404_},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_150_,{{{_zz_405_,_zz_406_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_98 = _zz_305[19]; + always @ (*) begin + _zz_99[10] = _zz_98; + _zz_99[9] = _zz_98; + _zz_99[8] = _zz_98; + _zz_99[7] = _zz_98; + _zz_99[6] = _zz_98; + _zz_99[5] = _zz_98; + _zz_99[4] = _zz_98; + _zz_99[3] = _zz_98; + _zz_99[2] = _zz_98; + _zz_99[1] = _zz_98; + _zz_99[0] = _zz_98; + end + + assign _zz_100 = _zz_306[11]; + always @ (*) begin + _zz_101[18] = _zz_100; + _zz_101[17] = _zz_100; + _zz_101[16] = _zz_100; + _zz_101[15] = _zz_100; + _zz_101[14] = _zz_100; + _zz_101[13] = _zz_100; + _zz_101[12] = _zz_100; + _zz_101[11] = _zz_100; + _zz_101[10] = _zz_100; + _zz_101[9] = _zz_100; + _zz_101[8] = _zz_100; + _zz_101[7] = _zz_100; + _zz_101[6] = _zz_100; + _zz_101[5] = _zz_100; + _zz_101[4] = _zz_100; + _zz_101[3] = _zz_100; + _zz_101[2] = _zz_100; + _zz_101[1] = _zz_100; + _zz_101[0] = _zz_100; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_99,{{{_zz_381,_zz_382},_zz_383},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_101,{{{_zz_384,_zz_385},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -4240,130 +3389,126 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_239_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_242_ = (32'b00000000000000000000000000000000); - assign _zz_240_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_241_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_243_ = (CsrPlugin_privilege == (2'b00)); + assign _zz_191 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_192 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_193 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_192; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_195 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_270_)begin + if(_zz_231)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_268_)begin + if(_zz_229)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_279_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - end end always @ (*) begin - _zz_247_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); - if(_zz_268_)begin - _zz_247_ = 1'b1; - end - if(_zz_279_)begin - _zz_247_ = 1'b0; + _zz_199 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(_zz_229)begin + _zz_199 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_269_)begin + if(_zz_230)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_267_)begin + if(_zz_228)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_269_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_230)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_267_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + if(_zz_228)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = decode_PC; - assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_1_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_1_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; - assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_238_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_152_); - assign _zz_257_ = (! _zz_152_); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_152_ ? _zz_153_ : dataCache_1__io_mem_cmd_payload_wr); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_152_ ? _zz_154_ : dataCache_1__io_mem_cmd_payload_address); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_152_ ? _zz_155_ : dataCache_1__io_mem_cmd_payload_data); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_152_ ? _zz_156_ : dataCache_1__io_mem_cmd_payload_mask); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_152_ ? _zz_157_ : dataCache_1__io_mem_cmd_payload_length); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_152_ ? _zz_158_ : dataCache_1__io_mem_cmd_payload_last); - assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_159_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_160_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_161_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_162_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_163_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_164_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_165_; - assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_1_output_payload; + assign _zz_190 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_218 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_248_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_249_ = execute_SRC_ADD; + assign _zz_200 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_201 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_167_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_104 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_167_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_104 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_167_ = execute_RS2[31 : 0]; + _zz_104 = execute_RS2[31 : 0]; end endcase end - assign _zz_256_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_90_ = _zz_249_[1 : 0]; - assign _zz_250_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_251_ = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + assign _zz_217 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_202 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_203 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_202; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_203; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_252_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin - _zz_252_ = 1'b1; + _zz_204 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_204 = 1'b1; end end - assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; - assign _zz_253_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_254_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_255_ = writeBack_REGFILE_WRITE_DATA; + assign _zz_205 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_206 = (CsrPlugin_privilege == 2'b00); + assign _zz_207 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_280_)begin - if(dataCache_1__io_cpu_redo)begin + if(_zz_238)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end @@ -4372,17 +3517,17 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_280_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin + if(_zz_238)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_redo)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end @@ -4390,94 +3535,94 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); - if(_zz_280_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_317_}; + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_238)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_307}; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_318_}; + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1__io_cpu_writeBack_mmuException)begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_308}; end end end always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; end 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; end 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; end default : begin end endcase end - assign _zz_168_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_169_[31] = _zz_168_; - _zz_169_[30] = _zz_168_; - _zz_169_[29] = _zz_168_; - _zz_169_[28] = _zz_168_; - _zz_169_[27] = _zz_168_; - _zz_169_[26] = _zz_168_; - _zz_169_[25] = _zz_168_; - _zz_169_[24] = _zz_168_; - _zz_169_[23] = _zz_168_; - _zz_169_[22] = _zz_168_; - _zz_169_[21] = _zz_168_; - _zz_169_[20] = _zz_168_; - _zz_169_[19] = _zz_168_; - _zz_169_[18] = _zz_168_; - _zz_169_[17] = _zz_168_; - _zz_169_[16] = _zz_168_; - _zz_169_[15] = _zz_168_; - _zz_169_[14] = _zz_168_; - _zz_169_[13] = _zz_168_; - _zz_169_[12] = _zz_168_; - _zz_169_[11] = _zz_168_; - _zz_169_[10] = _zz_168_; - _zz_169_[9] = _zz_168_; - _zz_169_[8] = _zz_168_; - _zz_169_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_170_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_171_[31] = _zz_170_; - _zz_171_[30] = _zz_170_; - _zz_171_[29] = _zz_170_; - _zz_171_[28] = _zz_170_; - _zz_171_[27] = _zz_170_; - _zz_171_[26] = _zz_170_; - _zz_171_[25] = _zz_170_; - _zz_171_[24] = _zz_170_; - _zz_171_[23] = _zz_170_; - _zz_171_[22] = _zz_170_; - _zz_171_[21] = _zz_170_; - _zz_171_[20] = _zz_170_; - _zz_171_[19] = _zz_170_; - _zz_171_[18] = _zz_170_; - _zz_171_[17] = _zz_170_; - _zz_171_[16] = _zz_170_; - _zz_171_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_300_) + assign _zz_105 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_106[31] = _zz_105; + _zz_106[30] = _zz_105; + _zz_106[29] = _zz_105; + _zz_106[28] = _zz_105; + _zz_106[27] = _zz_105; + _zz_106[26] = _zz_105; + _zz_106[25] = _zz_105; + _zz_106[24] = _zz_105; + _zz_106[23] = _zz_105; + _zz_106[22] = _zz_105; + _zz_106[21] = _zz_105; + _zz_106[20] = _zz_105; + _zz_106[19] = _zz_105; + _zz_106[18] = _zz_105; + _zz_106[17] = _zz_105; + _zz_106[16] = _zz_105; + _zz_106[15] = _zz_105; + _zz_106[14] = _zz_105; + _zz_106[13] = _zz_105; + _zz_106[12] = _zz_105; + _zz_106[11] = _zz_105; + _zz_106[10] = _zz_105; + _zz_106[9] = _zz_105; + _zz_106[8] = _zz_105; + _zz_106[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_107 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_108[31] = _zz_107; + _zz_108[30] = _zz_107; + _zz_108[29] = _zz_107; + _zz_108[28] = _zz_107; + _zz_108[27] = _zz_107; + _zz_108[26] = _zz_107; + _zz_108[25] = _zz_107; + _zz_108[24] = _zz_107; + _zz_108[23] = _zz_107; + _zz_108[22] = _zz_107; + _zz_108[21] = _zz_107; + _zz_108[20] = _zz_107; + _zz_108[19] = _zz_107; + _zz_108[18] = _zz_107; + _zz_108[17] = _zz_107; + _zz_108[16] = _zz_107; + _zz_108[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_261) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_169_; + writeBack_DBusCachedPlugin_rspFormated = _zz_106; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_171_; + writeBack_DBusCachedPlugin_rspFormated = _zz_108; end default : begin writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; @@ -4485,77 +3630,71 @@ module VexRiscv ( endcase end - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_173_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_174_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_175_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_176_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); - assign _zz_172_ = {(((decode_INSTRUCTION & _zz_407_) == (32'b00000000000000000000000000000000)) != (1'b0)),{((_zz_408_ == _zz_409_) != (1'b0)),{(_zz_410_ != (1'b0)),{(_zz_411_ != _zz_412_),{_zz_413_,{_zz_414_,_zz_415_}}}}}}; - assign _zz_88_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_558_) == (32'b00000000000000000001000001110011)),{(_zz_559_ == _zz_560_),{_zz_561_,{_zz_562_,_zz_563_}}}}}}} != (21'b000000000000000000000)); - assign _zz_87_ = _zz_319_[0]; - assign _zz_86_ = _zz_320_[0]; - assign _zz_85_ = _zz_321_[0]; - assign _zz_177_ = _zz_172_[5 : 4]; - assign _zz_84_ = _zz_177_; - assign _zz_83_ = _zz_322_[0]; - assign _zz_82_ = _zz_323_[0]; - assign _zz_81_ = _zz_324_[0]; - assign _zz_80_ = _zz_325_[0]; - assign _zz_178_ = _zz_172_[11 : 10]; - assign _zz_79_ = _zz_178_; - assign _zz_179_ = _zz_172_[13 : 12]; - assign _zz_78_ = _zz_179_; - assign _zz_180_ = _zz_172_[15 : 14]; - assign _zz_77_ = _zz_180_; - assign _zz_181_ = _zz_172_[17 : 16]; - assign _zz_76_ = _zz_181_; - assign _zz_75_ = _zz_326_[0]; - assign _zz_74_ = _zz_327_[0]; - assign _zz_73_ = _zz_328_[0]; - assign _zz_182_ = _zz_172_[22 : 21]; - assign _zz_72_ = _zz_182_; - assign _zz_71_ = _zz_329_[0]; - assign _zz_70_ = _zz_330_[0]; - assign _zz_69_ = _zz_331_[0]; - assign _zz_68_ = _zz_332_[0]; - assign _zz_183_ = _zz_172_[28 : 27]; - assign _zz_67_ = _zz_183_; - assign _zz_66_ = _zz_333_[0]; - assign _zz_65_ = _zz_334_[0]; - assign _zz_64_ = _zz_335_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign _zz_110 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_111 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_112 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_113 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_109 = {(_zz_113 != 1'b0),{(_zz_113 != 1'b0),{((_zz_386 == _zz_387) != 1'b0),{(_zz_388 != 1'b0),{(_zz_389 != _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}}; + assign _zz_114 = _zz_109[2 : 1]; + assign _zz_49 = _zz_114; + assign _zz_115 = _zz_109[7 : 6]; + assign _zz_48 = _zz_115; + assign _zz_116 = _zz_109[9 : 8]; + assign _zz_47 = _zz_116; + assign _zz_117 = _zz_109[19 : 18]; + assign _zz_46 = _zz_117; + assign _zz_118 = _zz_109[22 : 21]; + assign _zz_45 = _zz_118; + assign _zz_119 = _zz_109[24 : 23]; + assign _zz_44 = _zz_119; + assign _zz_120 = _zz_109[27 : 26]; + assign _zz_43 = _zz_120; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_258_; - assign decode_RegFilePlugin_rs2Data = _zz_259_; - assign _zz_63_ = decode_RegFilePlugin_rs1Data; - assign _zz_62_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_219; + assign decode_RegFilePlugin_rs2Data = _zz_220; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_60_ && writeBack_arbitration_isFiring); - if(_zz_184_)begin + lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); + if(_zz_121)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_59_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_89_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; + if(_zz_121)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_50; + if(_zz_121)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -4573,285 +3712,278 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_185_ = execute_IntAluPlugin_bitwise; + _zz_122 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_185_ = {31'd0, _zz_336_}; + _zz_122 = {31'd0, _zz_309}; end default : begin - _zz_185_ = execute_SRC_ADD_SUB; + _zz_122 = execute_SRC_ADD_SUB; end endcase end - assign _zz_57_ = _zz_185_; - assign _zz_55_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_186_ = execute_RS1; + _zz_123 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_186_ = {29'd0, _zz_337_}; + _zz_123 = {29'd0, _zz_310}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_186_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_123 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_186_ = {27'd0, _zz_338_}; + _zz_123 = {27'd0, _zz_311}; end endcase end - assign _zz_54_ = _zz_186_; - assign _zz_187_ = _zz_339_[11]; - always @ (*) begin - _zz_188_[19] = _zz_187_; - _zz_188_[18] = _zz_187_; - _zz_188_[17] = _zz_187_; - _zz_188_[16] = _zz_187_; - _zz_188_[15] = _zz_187_; - _zz_188_[14] = _zz_187_; - _zz_188_[13] = _zz_187_; - _zz_188_[12] = _zz_187_; - _zz_188_[11] = _zz_187_; - _zz_188_[10] = _zz_187_; - _zz_188_[9] = _zz_187_; - _zz_188_[8] = _zz_187_; - _zz_188_[7] = _zz_187_; - _zz_188_[6] = _zz_187_; - _zz_188_[5] = _zz_187_; - _zz_188_[4] = _zz_187_; - _zz_188_[3] = _zz_187_; - _zz_188_[2] = _zz_187_; - _zz_188_[1] = _zz_187_; - _zz_188_[0] = _zz_187_; - end - - assign _zz_189_ = _zz_340_[11]; - always @ (*) begin - _zz_190_[19] = _zz_189_; - _zz_190_[18] = _zz_189_; - _zz_190_[17] = _zz_189_; - _zz_190_[16] = _zz_189_; - _zz_190_[15] = _zz_189_; - _zz_190_[14] = _zz_189_; - _zz_190_[13] = _zz_189_; - _zz_190_[12] = _zz_189_; - _zz_190_[11] = _zz_189_; - _zz_190_[10] = _zz_189_; - _zz_190_[9] = _zz_189_; - _zz_190_[8] = _zz_189_; - _zz_190_[7] = _zz_189_; - _zz_190_[6] = _zz_189_; - _zz_190_[5] = _zz_189_; - _zz_190_[4] = _zz_189_; - _zz_190_[3] = _zz_189_; - _zz_190_[2] = _zz_189_; - _zz_190_[1] = _zz_189_; - _zz_190_[0] = _zz_189_; + assign _zz_124 = _zz_312[11]; + always @ (*) begin + _zz_125[19] = _zz_124; + _zz_125[18] = _zz_124; + _zz_125[17] = _zz_124; + _zz_125[16] = _zz_124; + _zz_125[15] = _zz_124; + _zz_125[14] = _zz_124; + _zz_125[13] = _zz_124; + _zz_125[12] = _zz_124; + _zz_125[11] = _zz_124; + _zz_125[10] = _zz_124; + _zz_125[9] = _zz_124; + _zz_125[8] = _zz_124; + _zz_125[7] = _zz_124; + _zz_125[6] = _zz_124; + _zz_125[5] = _zz_124; + _zz_125[4] = _zz_124; + _zz_125[3] = _zz_124; + _zz_125[2] = _zz_124; + _zz_125[1] = _zz_124; + _zz_125[0] = _zz_124; + end + + assign _zz_126 = _zz_313[11]; + always @ (*) begin + _zz_127[19] = _zz_126; + _zz_127[18] = _zz_126; + _zz_127[17] = _zz_126; + _zz_127[16] = _zz_126; + _zz_127[15] = _zz_126; + _zz_127[14] = _zz_126; + _zz_127[13] = _zz_126; + _zz_127[12] = _zz_126; + _zz_127[11] = _zz_126; + _zz_127[10] = _zz_126; + _zz_127[9] = _zz_126; + _zz_127[8] = _zz_126; + _zz_127[7] = _zz_126; + _zz_127[6] = _zz_126; + _zz_127[5] = _zz_126; + _zz_127[4] = _zz_126; + _zz_127[3] = _zz_126; + _zz_127[2] = _zz_126; + _zz_127[1] = _zz_126; + _zz_127[0] = _zz_126; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_191_ = execute_RS2; + _zz_128 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_191_ = {_zz_188_,execute_INSTRUCTION[31 : 20]}; + _zz_128 = {_zz_125,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_191_ = {_zz_190_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_128 = {_zz_127,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_191_ = _zz_50_; + _zz_128 = _zz_35; end endcase end - assign _zz_52_ = _zz_191_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_341_; + execute_SrcPlugin_addSub = _zz_314; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_49_ = execute_SrcPlugin_addSub; - assign _zz_48_ = execute_SrcPlugin_addSub; - assign _zz_47_ = execute_SrcPlugin_less; assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_192_[0] = execute_SRC1[31]; - _zz_192_[1] = execute_SRC1[30]; - _zz_192_[2] = execute_SRC1[29]; - _zz_192_[3] = execute_SRC1[28]; - _zz_192_[4] = execute_SRC1[27]; - _zz_192_[5] = execute_SRC1[26]; - _zz_192_[6] = execute_SRC1[25]; - _zz_192_[7] = execute_SRC1[24]; - _zz_192_[8] = execute_SRC1[23]; - _zz_192_[9] = execute_SRC1[22]; - _zz_192_[10] = execute_SRC1[21]; - _zz_192_[11] = execute_SRC1[20]; - _zz_192_[12] = execute_SRC1[19]; - _zz_192_[13] = execute_SRC1[18]; - _zz_192_[14] = execute_SRC1[17]; - _zz_192_[15] = execute_SRC1[16]; - _zz_192_[16] = execute_SRC1[15]; - _zz_192_[17] = execute_SRC1[14]; - _zz_192_[18] = execute_SRC1[13]; - _zz_192_[19] = execute_SRC1[12]; - _zz_192_[20] = execute_SRC1[11]; - _zz_192_[21] = execute_SRC1[10]; - _zz_192_[22] = execute_SRC1[9]; - _zz_192_[23] = execute_SRC1[8]; - _zz_192_[24] = execute_SRC1[7]; - _zz_192_[25] = execute_SRC1[6]; - _zz_192_[26] = execute_SRC1[5]; - _zz_192_[27] = execute_SRC1[4]; - _zz_192_[28] = execute_SRC1[3]; - _zz_192_[29] = execute_SRC1[2]; - _zz_192_[30] = execute_SRC1[1]; - _zz_192_[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_192_ : execute_SRC1); - assign _zz_45_ = _zz_349_; - always @ (*) begin - _zz_193_[0] = memory_SHIFT_RIGHT[31]; - _zz_193_[1] = memory_SHIFT_RIGHT[30]; - _zz_193_[2] = memory_SHIFT_RIGHT[29]; - _zz_193_[3] = memory_SHIFT_RIGHT[28]; - _zz_193_[4] = memory_SHIFT_RIGHT[27]; - _zz_193_[5] = memory_SHIFT_RIGHT[26]; - _zz_193_[6] = memory_SHIFT_RIGHT[25]; - _zz_193_[7] = memory_SHIFT_RIGHT[24]; - _zz_193_[8] = memory_SHIFT_RIGHT[23]; - _zz_193_[9] = memory_SHIFT_RIGHT[22]; - _zz_193_[10] = memory_SHIFT_RIGHT[21]; - _zz_193_[11] = memory_SHIFT_RIGHT[20]; - _zz_193_[12] = memory_SHIFT_RIGHT[19]; - _zz_193_[13] = memory_SHIFT_RIGHT[18]; - _zz_193_[14] = memory_SHIFT_RIGHT[17]; - _zz_193_[15] = memory_SHIFT_RIGHT[16]; - _zz_193_[16] = memory_SHIFT_RIGHT[15]; - _zz_193_[17] = memory_SHIFT_RIGHT[14]; - _zz_193_[18] = memory_SHIFT_RIGHT[13]; - _zz_193_[19] = memory_SHIFT_RIGHT[12]; - _zz_193_[20] = memory_SHIFT_RIGHT[11]; - _zz_193_[21] = memory_SHIFT_RIGHT[10]; - _zz_193_[22] = memory_SHIFT_RIGHT[9]; - _zz_193_[23] = memory_SHIFT_RIGHT[8]; - _zz_193_[24] = memory_SHIFT_RIGHT[7]; - _zz_193_[25] = memory_SHIFT_RIGHT[6]; - _zz_193_[26] = memory_SHIFT_RIGHT[5]; - _zz_193_[27] = memory_SHIFT_RIGHT[4]; - _zz_193_[28] = memory_SHIFT_RIGHT[3]; - _zz_193_[29] = memory_SHIFT_RIGHT[2]; - _zz_193_[30] = memory_SHIFT_RIGHT[1]; - _zz_193_[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_194_ = 1'b0; - if(_zz_281_)begin - if(_zz_282_)begin - if(_zz_200_)begin - _zz_194_ = 1'b1; + _zz_129[0] = execute_SRC1[31]; + _zz_129[1] = execute_SRC1[30]; + _zz_129[2] = execute_SRC1[29]; + _zz_129[3] = execute_SRC1[28]; + _zz_129[4] = execute_SRC1[27]; + _zz_129[5] = execute_SRC1[26]; + _zz_129[6] = execute_SRC1[25]; + _zz_129[7] = execute_SRC1[24]; + _zz_129[8] = execute_SRC1[23]; + _zz_129[9] = execute_SRC1[22]; + _zz_129[10] = execute_SRC1[21]; + _zz_129[11] = execute_SRC1[20]; + _zz_129[12] = execute_SRC1[19]; + _zz_129[13] = execute_SRC1[18]; + _zz_129[14] = execute_SRC1[17]; + _zz_129[15] = execute_SRC1[16]; + _zz_129[16] = execute_SRC1[15]; + _zz_129[17] = execute_SRC1[14]; + _zz_129[18] = execute_SRC1[13]; + _zz_129[19] = execute_SRC1[12]; + _zz_129[20] = execute_SRC1[11]; + _zz_129[21] = execute_SRC1[10]; + _zz_129[22] = execute_SRC1[9]; + _zz_129[23] = execute_SRC1[8]; + _zz_129[24] = execute_SRC1[7]; + _zz_129[25] = execute_SRC1[6]; + _zz_129[26] = execute_SRC1[5]; + _zz_129[27] = execute_SRC1[4]; + _zz_129[28] = execute_SRC1[3]; + _zz_129[29] = execute_SRC1[2]; + _zz_129[30] = execute_SRC1[1]; + _zz_129[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_129 : execute_SRC1); + always @ (*) begin + _zz_130[0] = memory_SHIFT_RIGHT[31]; + _zz_130[1] = memory_SHIFT_RIGHT[30]; + _zz_130[2] = memory_SHIFT_RIGHT[29]; + _zz_130[3] = memory_SHIFT_RIGHT[28]; + _zz_130[4] = memory_SHIFT_RIGHT[27]; + _zz_130[5] = memory_SHIFT_RIGHT[26]; + _zz_130[6] = memory_SHIFT_RIGHT[25]; + _zz_130[7] = memory_SHIFT_RIGHT[24]; + _zz_130[8] = memory_SHIFT_RIGHT[23]; + _zz_130[9] = memory_SHIFT_RIGHT[22]; + _zz_130[10] = memory_SHIFT_RIGHT[21]; + _zz_130[11] = memory_SHIFT_RIGHT[20]; + _zz_130[12] = memory_SHIFT_RIGHT[19]; + _zz_130[13] = memory_SHIFT_RIGHT[18]; + _zz_130[14] = memory_SHIFT_RIGHT[17]; + _zz_130[15] = memory_SHIFT_RIGHT[16]; + _zz_130[16] = memory_SHIFT_RIGHT[15]; + _zz_130[17] = memory_SHIFT_RIGHT[14]; + _zz_130[18] = memory_SHIFT_RIGHT[13]; + _zz_130[19] = memory_SHIFT_RIGHT[12]; + _zz_130[20] = memory_SHIFT_RIGHT[11]; + _zz_130[21] = memory_SHIFT_RIGHT[10]; + _zz_130[22] = memory_SHIFT_RIGHT[9]; + _zz_130[23] = memory_SHIFT_RIGHT[8]; + _zz_130[24] = memory_SHIFT_RIGHT[7]; + _zz_130[25] = memory_SHIFT_RIGHT[6]; + _zz_130[26] = memory_SHIFT_RIGHT[5]; + _zz_130[27] = memory_SHIFT_RIGHT[4]; + _zz_130[28] = memory_SHIFT_RIGHT[3]; + _zz_130[29] = memory_SHIFT_RIGHT[2]; + _zz_130[30] = memory_SHIFT_RIGHT[1]; + _zz_130[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_239)begin + if(_zz_240)begin + if(_zz_131)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_283_)begin - if(_zz_284_)begin - if(_zz_202_)begin - _zz_194_ = 1'b1; + if(_zz_241)begin + if(_zz_242)begin + if(_zz_133)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_285_)begin - if(_zz_286_)begin - if(_zz_204_)begin - _zz_194_ = 1'b1; + if(_zz_243)begin + if(_zz_244)begin + if(_zz_135)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_194_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_195_ = 1'b0; - if(_zz_281_)begin - if(_zz_282_)begin - if(_zz_201_)begin - _zz_195_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_239)begin + if(_zz_240)begin + if(_zz_132)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_283_)begin - if(_zz_284_)begin - if(_zz_203_)begin - _zz_195_ = 1'b1; + if(_zz_241)begin + if(_zz_242)begin + if(_zz_134)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_285_)begin - if(_zz_286_)begin - if(_zz_205_)begin - _zz_195_ = 1'b1; + if(_zz_243)begin + if(_zz_244)begin + if(_zz_136)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_195_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_196_ = (_zz_60_ && writeBack_arbitration_isFiring); - assign _zz_200_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_201_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_202_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_203_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_204_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_205_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_41_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_131 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_132 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_133 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_134 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_135 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_136 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_206_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_206_ == (3'b000))) begin - _zz_207_ = execute_BranchPlugin_eq; - end else if((_zz_206_ == (3'b001))) begin - _zz_207_ = (! execute_BranchPlugin_eq); - end else if((((_zz_206_ & (3'b101)) == (3'b101)))) begin - _zz_207_ = (! execute_SRC_LESS); + assign _zz_137 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_137 == 3'b000)) begin + _zz_138 = execute_BranchPlugin_eq; + end else if((_zz_137 == 3'b001)) begin + _zz_138 = (! execute_BranchPlugin_eq); + end else if((((_zz_137 & 3'b101) == 3'b101))) begin + _zz_138 = (! execute_SRC_LESS); end else begin - _zz_207_ = execute_SRC_LESS; + _zz_138 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_208_ = 1'b0; + _zz_139 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_208_ = 1'b1; + _zz_139 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_208_ = 1'b1; + _zz_139 = 1'b1; end default : begin - _zz_208_ = _zz_207_; + _zz_139 = _zz_138; end endcase end - assign _zz_40_ = _zz_208_; assign execute_BranchPlugin_missAlignedTarget = 1'b0; - assign _zz_38_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4863,104 +3995,103 @@ module VexRiscv ( endcase end - assign _zz_209_ = _zz_351_[11]; + assign _zz_140 = _zz_321[11]; always @ (*) begin - _zz_210_[19] = _zz_209_; - _zz_210_[18] = _zz_209_; - _zz_210_[17] = _zz_209_; - _zz_210_[16] = _zz_209_; - _zz_210_[15] = _zz_209_; - _zz_210_[14] = _zz_209_; - _zz_210_[13] = _zz_209_; - _zz_210_[12] = _zz_209_; - _zz_210_[11] = _zz_209_; - _zz_210_[10] = _zz_209_; - _zz_210_[9] = _zz_209_; - _zz_210_[8] = _zz_209_; - _zz_210_[7] = _zz_209_; - _zz_210_[6] = _zz_209_; - _zz_210_[5] = _zz_209_; - _zz_210_[4] = _zz_209_; - _zz_210_[3] = _zz_209_; - _zz_210_[2] = _zz_209_; - _zz_210_[1] = _zz_209_; - _zz_210_[0] = _zz_209_; + _zz_141[19] = _zz_140; + _zz_141[18] = _zz_140; + _zz_141[17] = _zz_140; + _zz_141[16] = _zz_140; + _zz_141[15] = _zz_140; + _zz_141[14] = _zz_140; + _zz_141[13] = _zz_140; + _zz_141[12] = _zz_140; + _zz_141[11] = _zz_140; + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_210_,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_141,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_212_,{{{_zz_576_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_214_,{{{_zz_577_,_zz_578_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_143,{{{_zz_550,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_145,{{{_zz_551,_zz_552},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_354_}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_324}; end end endcase end - assign _zz_211_ = _zz_352_[19]; - always @ (*) begin - _zz_212_[10] = _zz_211_; - _zz_212_[9] = _zz_211_; - _zz_212_[8] = _zz_211_; - _zz_212_[7] = _zz_211_; - _zz_212_[6] = _zz_211_; - _zz_212_[5] = _zz_211_; - _zz_212_[4] = _zz_211_; - _zz_212_[3] = _zz_211_; - _zz_212_[2] = _zz_211_; - _zz_212_[1] = _zz_211_; - _zz_212_[0] = _zz_211_; - end - - assign _zz_213_ = _zz_353_[11]; - always @ (*) begin - _zz_214_[18] = _zz_213_; - _zz_214_[17] = _zz_213_; - _zz_214_[16] = _zz_213_; - _zz_214_[15] = _zz_213_; - _zz_214_[14] = _zz_213_; - _zz_214_[13] = _zz_213_; - _zz_214_[12] = _zz_213_; - _zz_214_[11] = _zz_213_; - _zz_214_[10] = _zz_213_; - _zz_214_[9] = _zz_213_; - _zz_214_[8] = _zz_213_; - _zz_214_[7] = _zz_213_; - _zz_214_[6] = _zz_213_; - _zz_214_[5] = _zz_213_; - _zz_214_[4] = _zz_213_; - _zz_214_[3] = _zz_213_; - _zz_214_[2] = _zz_213_; - _zz_214_[1] = _zz_213_; - _zz_214_[0] = _zz_213_; + assign _zz_142 = _zz_322[19]; + always @ (*) begin + _zz_143[10] = _zz_142; + _zz_143[9] = _zz_142; + _zz_143[8] = _zz_142; + _zz_143[7] = _zz_142; + _zz_143[6] = _zz_142; + _zz_143[5] = _zz_142; + _zz_143[4] = _zz_142; + _zz_143[3] = _zz_142; + _zz_143[2] = _zz_142; + _zz_143[1] = _zz_142; + _zz_143[0] = _zz_142; + end + + assign _zz_144 = _zz_323[11]; + always @ (*) begin + _zz_145[18] = _zz_144; + _zz_145[17] = _zz_144; + _zz_145[16] = _zz_144; + _zz_145[15] = _zz_144; + _zz_145[14] = _zz_144; + _zz_145[13] = _zz_144; + _zz_145[12] = _zz_144; + _zz_145[11] = _zz_144; + _zz_145[10] = _zz_144; + _zz_145[9] = _zz_144; + _zz_145[8] = _zz_144; + _zz_145[7] = _zz_144; + _zz_145[6] = _zz_144; + _zz_145[5] = _zz_144; + _zz_145[4] = _zz_144; + _zz_145[3] = _zz_144; + _zz_145[2] = _zz_144; + _zz_145[1] = _zz_144; + _zz_145[0] = _zz_144; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_37_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign _zz_215_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_216_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_217_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign _zz_146 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_147 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_148 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_218_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_219_ = _zz_355_[0]; + assign _zz_149 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_150 = _zz_325[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_271_)begin + if(_zz_232)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -5000,9 +4131,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -5026,7 +4158,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; @@ -5037,7 +4169,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -5048,105 +4180,102 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_35_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_34_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - always @ (*) begin - execute_CsrPlugin_inWfi = 1'b0; - if(_zz_272_)begin - execute_CsrPlugin_inWfi = 1'b1; - end - end - - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b111100010001 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111100010100 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000001 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b101100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b101110000000 : begin + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110011000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b101100000010 : begin + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000011 : begin + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b110000000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000001 : begin + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000000 : begin + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b101110000010 : begin + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110010000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_245)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -5165,26 +4294,26 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_287_)begin + if(_zz_246)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_288_)begin + if(_zz_247)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_287_)begin - CsrPlugin_selfException_payload_code = (4'b0010); + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_246)begin + CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_288_)begin + if(_zz_247)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -5192,95 +4321,24 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_227_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b111100010001 : begin - execute_CsrPlugin_readData[3 : 0] = (4'b1011); - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b101100000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0]; - end - 12'b101110000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[63 : 32]; - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b001100000101 : begin - execute_CsrPlugin_readData[31 : 2] = CsrPlugin_mtvec_base; - execute_CsrPlugin_readData[1 : 0] = CsrPlugin_mtvec_mode; - end - 12'b110011000000 : begin - execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); - execute_CsrPlugin_readData[25 : 20] = (6'b100000); - end - 12'b101100000010 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[31 : 0]; - end - 12'b111100010011 : begin - execute_CsrPlugin_readData[5 : 0] = (6'b100001); - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_228_; - end - 12'b110000000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0]; - end - 12'b001100000001 : begin - execute_CsrPlugin_readData[31 : 30] = CsrPlugin_misa_base; - execute_CsrPlugin_readData[25 : 0] = CsrPlugin_misa_extensions; - end - 12'b001101000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; - end - 12'b111100010010 : begin - execute_CsrPlugin_readData[4 : 0] = (5'b10110); - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - end - 12'b101110000010 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[63 : 32]; - end - 12'b110010000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[63 : 32]; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_245)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_245)begin + execute_CsrPlugin_readInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_301_) + case(_zz_262) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -5291,10 +4349,10 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_MulPlugin_a = execute_SRC1; - assign execute_MulPlugin_b = execute_SRC2; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_289_) + case(_zz_248) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -5308,7 +4366,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_289_) + case(_zz_248) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -5327,16 +4385,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign _zz_31_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign _zz_30_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - assign _zz_28_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - assign _zz_27_ = ($signed(_zz_357_) + $signed(_zz_365_)); - assign writeBack_MulPlugin_result = ($signed(_zz_366_) + $signed(_zz_367_)); + assign writeBack_MulPlugin_result = ($signed(_zz_327) + $signed(_zz_328)); + assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_266_)begin - if(_zz_273_)begin + if(_zz_227)begin + if(_zz_249)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -5344,68 +4398,70 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_290_)begin + if(_zz_250)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end - assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); always @ (*) begin if(memory_DivPlugin_div_counter_willOverflow)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371_); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_332); end if(memory_DivPlugin_div_counter_willClear)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); - end - end - - assign _zz_220_ = memory_DivPlugin_rs1[31 : 0]; - assign _zz_221_ = {memory_DivPlugin_accumulator[31 : 0],_zz_220_[31]}; - assign _zz_222_ = (_zz_221_ - _zz_372_); - assign _zz_223_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_224_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_225_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_226_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_226_[31 : 0] = execute_RS1; - end - - assign _zz_228_ = (_zz_227_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_228_ != (32'b00000000000000000000000000000000)); - assign _zz_26_ = decode_ALU_BITWISE_CTRL; - assign _zz_24_ = _zz_72_; - assign _zz_58_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_23_ = decode_SHIFT_CTRL; - assign _zz_20_ = execute_SHIFT_CTRL; - assign _zz_21_ = _zz_79_; - assign _zz_46_ = decode_to_execute_SHIFT_CTRL; - assign _zz_44_ = execute_to_memory_SHIFT_CTRL; - assign _zz_18_ = decode_SRC1_CTRL; - assign _zz_16_ = _zz_84_; - assign _zz_53_ = decode_to_execute_SRC1_CTRL; - assign _zz_15_ = decode_SRC2_CTRL; - assign _zz_13_ = _zz_78_; - assign _zz_51_ = decode_to_execute_SRC2_CTRL; - assign _zz_12_ = decode_BRANCH_CTRL; - assign _zz_94_ = _zz_76_; - assign _zz_39_ = decode_to_execute_BRANCH_CTRL; - assign _zz_10_ = decode_ALU_CTRL; - assign _zz_8_ = _zz_77_; - assign _zz_56_ = decode_to_execute_ALU_CTRL; - assign _zz_7_ = decode_ENV_CTRL; - assign _zz_4_ = execute_ENV_CTRL; - assign _zz_2_ = memory_ENV_CTRL; - assign _zz_5_ = _zz_67_; - assign _zz_33_ = decode_to_execute_ENV_CTRL; - assign _zz_32_ = execute_to_memory_ENV_CTRL; - assign _zz_36_ = memory_to_writeBack_ENV_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_151 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_151[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_333); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_334 : _zz_335); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_336[31:0]; + assign _zz_152 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_153 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_154 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_155[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_155[31 : 0] = execute_RS1; + end + + assign _zz_157 = (_zz_156 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_157 != 32'h0); + assign _zz_26 = decode_SRC1_CTRL; + assign _zz_24 = _zz_49; + assign _zz_37 = decode_to_execute_SRC1_CTRL; + assign _zz_23 = decode_ALU_CTRL; + assign _zz_21 = _zz_48; + assign _zz_38 = decode_to_execute_ALU_CTRL; + assign _zz_20 = decode_SRC2_CTRL; + assign _zz_18 = _zz_47; + assign _zz_36 = decode_to_execute_SRC2_CTRL; + assign _zz_17 = decode_ALU_BITWISE_CTRL; + assign _zz_15 = _zz_46; + assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_14 = decode_SHIFT_CTRL; + assign _zz_11 = execute_SHIFT_CTRL; + assign _zz_12 = _zz_45; + assign _zz_34 = decode_to_execute_SHIFT_CTRL; + assign _zz_33 = execute_to_memory_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_51 = _zz_44; + assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_43; + assign _zz_28 = decode_to_execute_ENV_CTRL; + assign _zz_27 = execute_to_memory_ENV_CTRL; + assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -5422,74 +4478,247 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign iBusWishbone_ADR = {_zz_392_,_zz_229_}; - assign iBusWishbone_CTI = ((_zz_229_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); + always @ (*) begin + _zz_158 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_158[12 : 0] = 13'h1000; + _zz_158[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_159 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_159[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_160 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_160[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_161 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_161[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_162 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_162[31 : 30] = CsrPlugin_misa_base; + _zz_162[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_163 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_163[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_163[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_163[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_164 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_164[11 : 11] = CsrPlugin_mip_MEIP; + _zz_164[7 : 7] = CsrPlugin_mip_MTIP; + _zz_164[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_165 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_165[11 : 11] = CsrPlugin_mie_MEIE; + _zz_165[7 : 7] = CsrPlugin_mie_MTIE; + _zz_165[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_166 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_166[31 : 2] = CsrPlugin_mtvec_base; + _zz_166[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_167 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_167[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_168 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_168[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_169 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_169[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_169[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_170 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_170[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_171 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_171[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_172 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_172[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_173 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_173[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_174 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_174[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_175 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_175[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_176 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_176[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_177[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_178[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_179[31 : 0] = _zz_156; + end + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_180[31 : 0] = _zz_157; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_158 | _zz_159) | (_zz_160 | _zz_161)) | ((_zz_553 | _zz_162) | (_zz_163 | _zz_164))) | (((_zz_165 | _zz_166) | (_zz_167 | _zz_168)) | ((_zz_169 | _zz_170) | (_zz_171 | _zz_172)))) | (((_zz_173 | _zz_174) | (_zz_175 | _zz_176)) | ((_zz_177 | _zz_178) | (_zz_179 | _zz_180)))); + assign iBusWishbone_ADR = {_zz_353,_zz_181}; + assign iBusWishbone_CTI = ((_zz_181 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_291_)begin + if(_zz_251)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_291_)begin + if(_zz_251)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_230_; + assign iBus_rsp_valid = _zz_182; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_236_ = (dBus_cmd_payload_length != (3'b000)); - assign _zz_232_ = dBus_cmd_valid; - assign _zz_234_ = dBus_cmd_payload_wr; - assign _zz_235_ = (_zz_231_ == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_233_ && (_zz_234_ || _zz_235_)); - assign dBusWishbone_ADR = ((_zz_236_ ? {{dBus_cmd_payload_address[31 : 5],_zz_231_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); - assign dBusWishbone_CTI = (_zz_236_ ? (_zz_235_ ? (3'b111) : (3'b010)) : (3'b000)); - assign dBusWishbone_BTE = (2'b00); - assign dBusWishbone_SEL = (_zz_234_ ? dBus_cmd_payload_mask : (4'b1111)); - assign dBusWishbone_WE = _zz_234_; + assign _zz_188 = (dBus_cmd_payload_length != 3'b000); + assign _zz_184 = dBus_cmd_valid; + assign _zz_186 = dBus_cmd_payload_wr; + assign _zz_187 = (_zz_183 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_185 && (_zz_186 || _zz_187)); + assign dBusWishbone_ADR = ((_zz_188 ? {{dBus_cmd_payload_address[31 : 5],_zz_183},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_188 ? (_zz_187 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_186 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_186; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_233_ = (_zz_232_ && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_232_; - assign dBusWishbone_STB = _zz_232_; - assign dBus_rsp_valid = _zz_237_; + assign _zz_185 = (_zz_184 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_184; + assign dBusWishbone_STB = _zz_184; + assign dBus_rsp_valid = _zz_189; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; IBusCachedPlugin_decodePc_pcReg <= externalResetVector; - _zz_112_ <= 1'b0; + _zz_63 <= 1'b0; IBusCachedPlugin_decompressor_bufferValid <= 1'b0; - _zz_140_ <= 1'b0; + IBusCachedPlugin_decompressor_throw2BytesReg <= 1'b0; + _zz_91 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_151_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_152_ <= 1'b0; - _zz_159_ <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_166_; - DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_184_ <= 1'b1; - _zz_197_ <= 1'b0; - CsrPlugin_misa_base <= (2'b01); - CsrPlugin_misa_extensions <= (26'b00000000000000000001000010); + IBusCachedPlugin_rspCounter <= _zz_102; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_103; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_121 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -5499,22 +4728,29 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_DivPlugin_div_counter_value <= (6'b000000); - _zz_227_ <= (32'b00000000000000000000000000000000); + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_156 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_229_ <= (3'b000); - _zz_230_ <= 1'b0; - _zz_231_ <= (3'b000); - _zz_237_ <= 1'b0; + _zz_181 <= 3'b000; + _zz_182 <= 1'b0; + _zz_183 <= 3'b000; + _zz_189 <= 1'b0; end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin @@ -5523,87 +4759,83 @@ module VexRiscv ( if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end if((decode_arbitration_isFiring && (! IBusCachedPlugin_decodePc_injectedDecode)))begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_decodePc_pcPlus; end - if((IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)))begin + if(_zz_237)begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_jump_pcLoad_payload; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_112_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_63 <= 1'b0; + end + if(_zz_61)begin + _zz_63 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(_zz_110_)begin - _zz_112_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if((IBusCachedPlugin_decompressor_output_valid && IBusCachedPlugin_decompressor_output_ready))begin + IBusCachedPlugin_decompressor_throw2BytesReg <= ((((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && IBusCachedPlugin_decompressor_isInputHighRvc) || (IBusCachedPlugin_decompressor_bufferValid && IBusCachedPlugin_decompressor_isInputHighRvc)); end - if((IBusCachedPlugin_decompressor_inputBeforeStage_valid && IBusCachedPlugin_decompressor_inputBeforeStage_ready))begin + if((IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid))begin IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end - if(_zz_277_)begin - if(_zz_278_)begin + if(_zz_252)begin + if(IBusCachedPlugin_decompressor_bufferFill)begin IBusCachedPlugin_decompressor_bufferValid <= 1'b1; - end else begin - IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end end - if(IBusCachedPlugin_fetcherflushIt)begin + if((IBusCachedPlugin_externalFlush || IBusCachedPlugin_decompressor_consumeCurrent))begin + IBusCachedPlugin_decompressor_throw2BytesReg <= 1'b0; IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end - if(IBusCachedPlugin_decompressor_inputBeforeStage_ready)begin - _zz_140_ <= IBusCachedPlugin_decompressor_inputBeforeStage_valid; + if(decode_arbitration_removeIt)begin + _zz_91 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_140_ <= 1'b0; + if(IBusCachedPlugin_decompressor_output_ready)begin + _zz_91 <= (IBusCachedPlugin_decompressor_output_valid && (! IBusCachedPlugin_externalFlush)); end if((! 1'b0))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_decodePc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_decodePc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_decodePc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_decodePc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_152_ <= 1'b0; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_292_)begin - _zz_152_ <= dataCache_1__io_mem_cmd_valid; + if(_zz_253)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_159_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end if(dBus_rsp_valid)begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_184_ <= 1'b0; - _zz_197_ <= _zz_196_; + _zz_121 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5625,20 +4857,39 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_293_)begin - if(_zz_294_)begin + if(_zz_254)begin + if(_zz_255)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_295_)begin + if(_zz_256)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_296_)begin + if(_zz_257)begin CsrPlugin_interrupt_valid <= 1'b1; end end CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_274_)begin + if(_zz_234)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5649,10 +4900,10 @@ module VexRiscv ( end endcase end - if(_zz_275_)begin - case(_zz_276_) + if(_zz_235)begin + case(_zz_236) 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; end @@ -5660,14 +4911,8 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_217_,{_zz_216_,_zz_215_}} != (3'b000)); + execute_CsrPlugin_wfiWake <= (({_zz_148,{_zz_147,_zz_146}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_43_; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -5686,136 +4931,93 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if((((! IBusCachedPlugin_iBusRsp_output_ready) && (IBusCachedPlugin_decompressor_inputBeforeStage_valid && IBusCachedPlugin_decompressor_inputBeforeStage_ready)) && (! IBusCachedPlugin_fetcherflushIt)))begin - IBusCachedPlugin_fetchPc_pcReg[1] <= 1'b1; - end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_227_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_385_[0]; - CsrPlugin_mstatus_MIE <= _zz_386_[0]; - end - end - 12'b111100010001 : begin - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - end - 12'b101100000000 : begin - end - 12'b101110000000 : begin - end - 12'b001101000100 : begin - end - 12'b001100000101 : begin - end - 12'b110011000000 : begin - end - 12'b101100000010 : begin - end - 12'b111100010011 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b110000000000 : begin - end - 12'b001100000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; - end - end - 12'b001101000000 : begin - end - 12'b111100010010 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_388_[0]; - CsrPlugin_mie_MTIE <= _zz_389_[0]; - CsrPlugin_mie_MSIE <= _zz_390_[0]; - end - end - 12'b101110000010 : begin + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; end - 12'b110010000000 : begin + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_346[0]; + CsrPlugin_mstatus_MIE <= _zz_347[0]; end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_349[0]; + CsrPlugin_mie_MTIE <= _zz_350[0]; + CsrPlugin_mie_MSIE <= _zz_351[0]; end - default : begin + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; end - endcase - if(_zz_291_)begin + end + if(_zz_251)begin if(iBusWishbone_ACK)begin - _zz_229_ <= (_zz_229_ + (3'b001)); + _zz_181 <= (_zz_181 + 3'b001); end end - _zz_230_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_232_ && _zz_233_))begin - _zz_231_ <= (_zz_231_ + (3'b001)); - if(_zz_235_)begin - _zz_231_ <= (3'b000); + _zz_182 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_184 && _zz_185))begin + _zz_183 <= (_zz_183 + 3'b001); + if(_zz_187)begin + _zz_183 <= 3'b000; end end - _zz_237_ <= ((_zz_232_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_189 <= ((_zz_184 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end always @ (posedge clk) begin - if(_zz_277_)begin - IBusCachedPlugin_decompressor_bufferData <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[31 : 16]; + if(_zz_252)begin + IBusCachedPlugin_decompressor_bufferData <= IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16]; end - if(IBusCachedPlugin_decompressor_inputBeforeStage_ready)begin - _zz_141_ <= IBusCachedPlugin_decompressor_inputBeforeStage_payload_pc; - _zz_142_ <= IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_error; - _zz_143_ <= IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_inst; - _zz_144_ <= IBusCachedPlugin_decompressor_inputBeforeStage_payload_isRvc; + if(IBusCachedPlugin_decompressor_output_ready)begin + _zz_92 <= IBusCachedPlugin_decompressor_output_payload_pc; + _zz_93 <= IBusCachedPlugin_decompressor_output_payload_rsp_error; + _zz_94 <= IBusCachedPlugin_decompressor_output_payload_rsp_inst; + _zz_95 <= IBusCachedPlugin_decompressor_output_payload_isRvc; end if(IBusCachedPlugin_injector_decodeInput_ready)begin IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_decompressor_raw; end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(_zz_292_)begin - _zz_153_ <= dataCache_1__io_mem_cmd_payload_wr; - _zz_154_ <= dataCache_1__io_mem_cmd_payload_address; - _zz_155_ <= dataCache_1__io_mem_cmd_payload_data; - _zz_156_ <= dataCache_1__io_mem_cmd_payload_mask; - _zz_157_ <= dataCache_1__io_mem_cmd_payload_length; - _zz_158_ <= dataCache_1__io_mem_cmd_payload_last; - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_160_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - _zz_161_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; - _zz_162_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; - _zz_163_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - _zz_164_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; - _zz_165_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; - end - if(_zz_196_)begin - _zz_198_ <= _zz_59_[11 : 7]; - _zz_199_ <= _zz_89_; - end + if(_zz_253)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_271_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_219_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_219_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_232)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -5825,21 +5027,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_293_)begin - if(_zz_294_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_254)begin + if(_zz_255)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_295_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_256)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_296_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_257)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_274_)begin + if(_zz_234)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5853,291 +5055,1396 @@ module VexRiscv ( end endcase end - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_done <= 1'b1; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_227)begin + if(_zz_249)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_337[31:0]; + end + end + end + if(_zz_250)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_154 ? (~ _zz_155) : _zz_155) + _zz_343); + memory_DivPlugin_rs2 <= ((_zz_153 ? (~ execute_RS2) : execute_RS2) + _zz_345); + memory_DivPlugin_div_needRevert <= ((_zz_154 ^ (_zz_153 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_35; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RVC <= decode_IS_RVC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_348[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_352[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end - if(_zz_266_)begin - if(_zz_273_)begin - memory_DivPlugin_rs1[31 : 0] <= _zz_373_[31:0]; - memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_222_[32]) ? _zz_374_ : _zz_375_); - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_result <= _zz_376_[31:0]; - end - end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end - if(_zz_290_)begin - memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_DivPlugin_rs1 <= ((_zz_225_ ? (~ _zz_226_) : _zz_226_) + _zz_382_); - memory_DivPlugin_rs2 <= ((_zz_224_ ? (~ execute_RS2) : execute_RS2) + _zz_384_); - memory_DivPlugin_div_needRevert <= ((_zz_225_ ^ (_zz_224_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_25_; + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + + always @ (*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_96_; + end + + always @ (*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_95_; + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_22_; + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_19_; + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_17_; + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_50_; + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_42_; + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HL <= execute_MUL_HL; + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_MUL <= decode_IS_MUL; + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + if(_zz_13)begin + stageB_loaderValid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LH <= execute_MUL_LH; + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_14_; + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_11_; + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_9_; + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LL <= execute_MUL_LL; + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RVC <= decode_IS_RVC; + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HH <= execute_MUL_HH; + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6_; + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3_; + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1_; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b111100010001 : begin - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; end - 12'b101100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; - end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; end - 12'b101110000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end end end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_387_[0]; - end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; end - 12'b110011000000 : begin + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; end - 12'b101100000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; - end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); end - 12'b111100010011 : begin + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; end - 12'b001101000011 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; - end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; end - 12'b111111000000 : begin + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_cacheMiss, + output io_cpu_fetch_error, + output io_cpu_fetch_mmuRefilling, + output io_cpu_fetch_mmuException, + input io_cpu_fetch_isUser, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_9; + reg [21:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [21:0] _zz_15; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_11 = (! lineLoader_flushCounter[7]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; end - 12'b110000000000 : begin + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid); + assign io_cpu_fetch_error = (fetchStage_hit_error || ((! io_cpu_fetch_mmuRsp_isPaging) && (io_cpu_fetch_mmuRsp_exception || (! io_cpu_fetch_mmuRsp_allowExecute)))); + assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuRsp_refilling; + assign io_cpu_fetch_mmuException = (((! io_cpu_fetch_mmuRsp_refilling) && io_cpu_fetch_mmuRsp_isPaging) && (io_cpu_fetch_mmuRsp_exception || (! io_cpu_fetch_mmuRsp_allowExecute))); + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; end - 12'b001100000001 : begin + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; end - 12'b001101000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; - end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end - 12'b111100010010 : begin + if(io_flush)begin + lineLoader_flushPending <= 1'b1; end - 12'b001100000100 : begin + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; end - 12'b101110000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; - end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; end - 12'b110010000000 : begin + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; end - 12'b001101000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_391_[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; end end - default : begin - end - endcase - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end end -endmodule + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_12)begin + lineLoader_flushCounter <= 8'h0; + end + end + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v index 5ada3b9..2dc6158 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 29/04/2020, 00:19:14 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -9,3340 +9,2448 @@ `define EnvCtrlEnum_defaultEncoding_WFI 2'b10 `define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + `define ShiftCtrlEnum_defaultEncoding_type [1:0] `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 `define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - `define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] `define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 `define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - `define Src2CtrlEnum_defaultEncoding_type [1:0] `define Src2CtrlEnum_defaultEncoding_RS 2'b00 `define Src2CtrlEnum_defaultEncoding_IMI 2'b01 `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_cacheMiss, - output io_cpu_fetch_error, - output io_cpu_fetch_mmuRefilling, - output io_cpu_fetch_mmuException, - input io_cpu_fetch_isUser, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire [0:0] _zz_14_; - wire [0:0] _zz_15_; - wire [21:0] _zz_16_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [6:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_7_; - wire [9:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; - assign _zz_12_ = (! lineLoader_flushCounter[7]); - assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_14_ = _zz_7_[0 : 0]; - assign _zz_15_ = _zz_7_[1 : 1]; - assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; - end - end - - always @ (posedge clk) begin - if(_zz_6_) begin - _zz_10_ <= ways_0_tags[_zz_5_]; - end - end +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - always @ (posedge clk) begin - if(_zz_9_) begin - _zz_11_ <= ways_0_datas[_zz_8_]; - end - end - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; - end - end +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + wire _zz_201; + wire [31:0] _zz_202; + reg _zz_203; + wire _zz_204; + wire [31:0] _zz_205; + wire _zz_206; + wire [31:0] _zz_207; + reg _zz_208; + wire _zz_209; + wire _zz_210; + wire [31:0] _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + wire _zz_219; + wire [3:0] _zz_220; + wire _zz_221; + wire _zz_222; + reg [31:0] _zz_223; + reg [31:0] _zz_224; + reg [31:0] _zz_225; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_error; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire [1:0] _zz_243; + wire _zz_244; + wire _zz_245; + wire _zz_246; + wire _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire [1:0] _zz_255; + wire _zz_256; + wire _zz_257; + wire [5:0] _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire _zz_263; + wire _zz_264; + wire _zz_265; + wire [4:0] _zz_266; + wire [1:0] _zz_267; + wire [1:0] _zz_268; + wire [1:0] _zz_269; + wire _zz_270; + wire [1:0] _zz_271; + wire [51:0] _zz_272; + wire [51:0] _zz_273; + wire [51:0] _zz_274; + wire [32:0] _zz_275; + wire [51:0] _zz_276; + wire [49:0] _zz_277; + wire [51:0] _zz_278; + wire [49:0] _zz_279; + wire [51:0] _zz_280; + wire [32:0] _zz_281; + wire [31:0] _zz_282; + wire [32:0] _zz_283; + wire [0:0] _zz_284; + wire [0:0] _zz_285; + wire [0:0] _zz_286; + wire [0:0] _zz_287; + wire [0:0] _zz_288; + wire [0:0] _zz_289; + wire [0:0] _zz_290; + wire [0:0] _zz_291; + wire [0:0] _zz_292; + wire [0:0] _zz_293; + wire [2:0] _zz_294; + wire [31:0] _zz_295; + wire [0:0] _zz_296; + wire [0:0] _zz_297; + wire [0:0] _zz_298; + wire [0:0] _zz_299; + wire [0:0] _zz_300; + wire [0:0] _zz_301; + wire [0:0] _zz_302; + wire [0:0] _zz_303; + wire [3:0] _zz_304; + wire [2:0] _zz_305; + wire [31:0] _zz_306; + wire [2:0] _zz_307; + wire [31:0] _zz_308; + wire [31:0] _zz_309; + wire [11:0] _zz_310; + wire [11:0] _zz_311; + wire [11:0] _zz_312; + wire [31:0] _zz_313; + wire [19:0] _zz_314; + wire [11:0] _zz_315; + wire [2:0] _zz_316; + wire [2:0] _zz_317; + wire [0:0] _zz_318; + wire [2:0] _zz_319; + wire [4:0] _zz_320; + wire [11:0] _zz_321; + wire [11:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [31:0] _zz_326; + wire [31:0] _zz_327; + wire [31:0] _zz_328; + wire [31:0] _zz_329; + wire [11:0] _zz_330; + wire [19:0] _zz_331; + wire [11:0] _zz_332; + wire [2:0] _zz_333; + wire [1:0] _zz_334; + wire [1:0] _zz_335; + wire [65:0] _zz_336; + wire [65:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [0:0] _zz_340; + wire [5:0] _zz_341; + wire [32:0] _zz_342; + wire [31:0] _zz_343; + wire [31:0] _zz_344; + wire [32:0] _zz_345; + wire [32:0] _zz_346; + wire [32:0] _zz_347; + wire [32:0] _zz_348; + wire [0:0] _zz_349; + wire [32:0] _zz_350; + wire [0:0] _zz_351; + wire [32:0] _zz_352; + wire [0:0] _zz_353; + wire [31:0] _zz_354; + wire [0:0] _zz_355; + wire [0:0] _zz_356; + wire [0:0] _zz_357; + wire [0:0] _zz_358; + wire [0:0] _zz_359; + wire [0:0] _zz_360; + wire [0:0] _zz_361; + wire [26:0] _zz_362; + wire _zz_363; + wire _zz_364; + wire [1:0] _zz_365; + wire [31:0] _zz_366; + wire [31:0] _zz_367; + wire [31:0] _zz_368; + wire _zz_369; + wire [0:0] _zz_370; + wire [13:0] _zz_371; + wire [31:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; + wire _zz_375; + wire [0:0] _zz_376; + wire [7:0] _zz_377; + wire [31:0] _zz_378; + wire [31:0] _zz_379; + wire [31:0] _zz_380; + wire _zz_381; + wire [0:0] _zz_382; + wire [1:0] _zz_383; + wire _zz_384; + wire _zz_385; + wire [6:0] _zz_386; + wire [4:0] _zz_387; + wire _zz_388; + wire [4:0] _zz_389; + wire [0:0] _zz_390; + wire [7:0] _zz_391; + wire _zz_392; + wire [0:0] _zz_393; + wire [0:0] _zz_394; + wire [31:0] _zz_395; + wire [0:0] _zz_396; + wire [0:0] _zz_397; + wire _zz_398; + wire [0:0] _zz_399; + wire [26:0] _zz_400; + wire [31:0] _zz_401; + wire _zz_402; + wire _zz_403; + wire _zz_404; + wire [1:0] _zz_405; + wire [1:0] _zz_406; + wire _zz_407; + wire [0:0] _zz_408; + wire [22:0] _zz_409; + wire [31:0] _zz_410; + wire [31:0] _zz_411; + wire [31:0] _zz_412; + wire [31:0] _zz_413; + wire _zz_414; + wire _zz_415; + wire [1:0] _zz_416; + wire [1:0] _zz_417; + wire _zz_418; + wire [0:0] _zz_419; + wire [19:0] _zz_420; + wire [31:0] _zz_421; + wire [31:0] _zz_422; + wire [31:0] _zz_423; + wire [31:0] _zz_424; + wire _zz_425; + wire [0:0] _zz_426; + wire [0:0] _zz_427; + wire _zz_428; + wire [0:0] _zz_429; + wire [0:0] _zz_430; + wire _zz_431; + wire [0:0] _zz_432; + wire [16:0] _zz_433; + wire [31:0] _zz_434; + wire [31:0] _zz_435; + wire [31:0] _zz_436; + wire [31:0] _zz_437; + wire [31:0] _zz_438; + wire [0:0] _zz_439; + wire [0:0] _zz_440; + wire [0:0] _zz_441; + wire [0:0] _zz_442; + wire _zz_443; + wire [0:0] _zz_444; + wire [13:0] _zz_445; + wire [31:0] _zz_446; + wire [31:0] _zz_447; + wire [31:0] _zz_448; + wire _zz_449; + wire _zz_450; + wire [0:0] _zz_451; + wire [3:0] _zz_452; + wire [0:0] _zz_453; + wire [0:0] _zz_454; + wire _zz_455; + wire [0:0] _zz_456; + wire [10:0] _zz_457; + wire [31:0] _zz_458; + wire [31:0] _zz_459; + wire [31:0] _zz_460; + wire _zz_461; + wire [0:0] _zz_462; + wire [0:0] _zz_463; + wire [31:0] _zz_464; + wire _zz_465; + wire [0:0] _zz_466; + wire [2:0] _zz_467; + wire [0:0] _zz_468; + wire [3:0] _zz_469; + wire [5:0] _zz_470; + wire [5:0] _zz_471; + wire _zz_472; + wire [0:0] _zz_473; + wire [7:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; + wire [31:0] _zz_477; + wire [31:0] _zz_478; + wire [31:0] _zz_479; + wire [31:0] _zz_480; + wire _zz_481; + wire [0:0] _zz_482; + wire [0:0] _zz_483; + wire _zz_484; + wire [0:0] _zz_485; + wire [1:0] _zz_486; + wire [0:0] _zz_487; + wire [3:0] _zz_488; + wire [0:0] _zz_489; + wire [0:0] _zz_490; + wire [1:0] _zz_491; + wire [1:0] _zz_492; + wire _zz_493; + wire [0:0] _zz_494; + wire [5:0] _zz_495; + wire [31:0] _zz_496; + wire [31:0] _zz_497; + wire [31:0] _zz_498; + wire [31:0] _zz_499; + wire [31:0] _zz_500; + wire [31:0] _zz_501; + wire [31:0] _zz_502; + wire [31:0] _zz_503; + wire _zz_504; + wire _zz_505; + wire [31:0] _zz_506; + wire [31:0] _zz_507; + wire _zz_508; + wire [0:0] _zz_509; + wire [1:0] _zz_510; + wire [31:0] _zz_511; + wire [31:0] _zz_512; + wire _zz_513; + wire _zz_514; + wire [0:0] _zz_515; + wire [0:0] _zz_516; + wire _zz_517; + wire [0:0] _zz_518; + wire [3:0] _zz_519; + wire [31:0] _zz_520; + wire [31:0] _zz_521; + wire [31:0] _zz_522; + wire [31:0] _zz_523; + wire [31:0] _zz_524; + wire _zz_525; + wire _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; + wire [31:0] _zz_529; + wire [31:0] _zz_530; + wire [0:0] _zz_531; + wire [2:0] _zz_532; + wire [0:0] _zz_533; + wire [0:0] _zz_534; + wire _zz_535; + wire [0:0] _zz_536; + wire [1:0] _zz_537; + wire [31:0] _zz_538; + wire [31:0] _zz_539; + wire [31:0] _zz_540; + wire _zz_541; + wire _zz_542; + wire [31:0] _zz_543; + wire _zz_544; + wire [0:0] _zz_545; + wire [0:0] _zz_546; + wire [0:0] _zz_547; + wire [0:0] _zz_548; + wire [1:0] _zz_549; + wire [1:0] _zz_550; + wire [0:0] _zz_551; + wire [0:0] _zz_552; + wire [31:0] _zz_553; + wire [31:0] _zz_554; + wire [31:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire _zz_559; + wire _zz_560; + wire _zz_561; + wire [31:0] _zz_562; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire execute_PREDICTION_HAD_BRANCHED2; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_31; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_35; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_36; + wire execute_IS_RVC; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; + wire [31:0] _zz_40; + wire _zz_41; + reg _zz_42; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_43; + wire `BranchCtrlEnum_defaultEncoding_type _zz_44; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; + wire `Src2CtrlEnum_defaultEncoding_type _zz_47; + wire `AluCtrlEnum_defaultEncoding_type _zz_48; + wire `Src1CtrlEnum_defaultEncoding_type _zz_49; + reg [31:0] _zz_50; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + reg [31:0] _zz_52; + reg [31:0] _zz_53; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire decode_IS_RVC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + wire IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_54; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_55; + wire [3:0] _zz_56; + wire _zz_57; + wire _zz_58; + wire _zz_59; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + reg [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_decodePc_flushed; + reg [31:0] IBusCachedPlugin_decodePc_pcReg /* verilator public */ ; + wire [31:0] IBusCachedPlugin_decodePc_pcPlus; + reg IBusCachedPlugin_decodePc_injectedDecode; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire _zz_60; + wire _zz_61; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_62; + wire _zz_63; + reg _zz_64; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire IBusCachedPlugin_decompressor_input_valid; + wire IBusCachedPlugin_decompressor_input_ready; + wire [31:0] IBusCachedPlugin_decompressor_input_payload_pc; + wire IBusCachedPlugin_decompressor_input_payload_rsp_error; + wire [31:0] IBusCachedPlugin_decompressor_input_payload_rsp_inst; + wire IBusCachedPlugin_decompressor_input_payload_isRvc; + wire IBusCachedPlugin_decompressor_output_valid; + wire IBusCachedPlugin_decompressor_output_ready; + wire [31:0] IBusCachedPlugin_decompressor_output_payload_pc; + wire IBusCachedPlugin_decompressor_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_decompressor_output_payload_rsp_inst; + wire IBusCachedPlugin_decompressor_output_payload_isRvc; + wire IBusCachedPlugin_decompressor_flushNext; + wire IBusCachedPlugin_decompressor_consumeCurrent; + reg IBusCachedPlugin_decompressor_bufferValid; + reg [15:0] IBusCachedPlugin_decompressor_bufferData; + wire IBusCachedPlugin_decompressor_isInputLowRvc; + wire IBusCachedPlugin_decompressor_isInputHighRvc; + reg IBusCachedPlugin_decompressor_throw2BytesReg; + wire IBusCachedPlugin_decompressor_throw2Bytes; + wire IBusCachedPlugin_decompressor_unaligned; + wire [31:0] IBusCachedPlugin_decompressor_raw; + wire IBusCachedPlugin_decompressor_isRvc; + wire [15:0] _zz_65; + reg [31:0] IBusCachedPlugin_decompressor_decompressed; + wire [4:0] _zz_66; + wire [4:0] _zz_67; + wire [11:0] _zz_68; + wire _zz_69; + reg [11:0] _zz_70; + wire _zz_71; + reg [9:0] _zz_72; + wire [20:0] _zz_73; + wire _zz_74; + reg [14:0] _zz_75; + wire _zz_76; + reg [2:0] _zz_77; + wire _zz_78; + reg [9:0] _zz_79; + wire [20:0] _zz_80; + wire _zz_81; + reg [4:0] _zz_82; + wire [12:0] _zz_83; + wire [4:0] _zz_84; + wire [4:0] _zz_85; + wire [4:0] _zz_86; + wire _zz_87; + reg [2:0] _zz_88; + reg [2:0] _zz_89; + wire _zz_90; + reg [6:0] _zz_91; + wire IBusCachedPlugin_decompressor_bufferFill; + wire IBusCachedPlugin_injector_decodeInput_valid; + wire IBusCachedPlugin_injector_decodeInput_ready; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; + wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; + reg _zz_92; + reg [31:0] _zz_93; + reg _zz_94; + reg [31:0] _zz_95; + reg _zz_96; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; + wire _zz_97; + reg [18:0] _zz_98; + wire _zz_99; + reg [10:0] _zz_100; + wire _zz_101; + reg [18:0] _zz_102; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_103; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_104; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_105; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_106; + reg [31:0] _zz_107; + wire _zz_108; + reg [31:0] _zz_109; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [32:0] _zz_110; + wire _zz_111; + wire _zz_112; + wire _zz_113; + wire _zz_114; + wire `Src1CtrlEnum_defaultEncoding_type _zz_115; + wire `AluCtrlEnum_defaultEncoding_type _zz_116; + wire `Src2CtrlEnum_defaultEncoding_type _zz_117; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_118; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_119; + wire `BranchCtrlEnum_defaultEncoding_type _zz_120; + wire `EnvCtrlEnum_defaultEncoding_type _zz_121; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_122; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_123; + reg [31:0] _zz_124; + wire _zz_125; + reg [19:0] _zz_126; + wire _zz_127; + reg [19:0] _zz_128; + reg [31:0] _zz_129; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_130; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_131; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_132; + wire _zz_133; + wire _zz_134; + wire _zz_135; + wire _zz_136; + wire _zz_137; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_138; + reg _zz_139; + reg _zz_140; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_141; + reg [19:0] _zz_142; + wire _zz_143; + reg [10:0] _zz_144; + wire _zz_145; + reg [18:0] _zz_146; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_147; + wire _zz_148; + wire _zz_149; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_150; + wire _zz_151; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_152; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_153; + wire _zz_154; + wire _zz_155; + reg [32:0] _zz_156; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_157; + wire [31:0] _zz_158; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_159; + wire DebugPlugin_allowEBreak; + reg _zz_160; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg decode_to_execute_IS_RVC; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_161; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [2:0] _zz_185; + reg _zz_186; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + wire _zz_191; + wire _zz_192; + reg _zz_193; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [23:0] _zz_20_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [63:0] _zz_23_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; + reg [95:0] _zz_26_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_27_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_29_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_30_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_33_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_34_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_36_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_37_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_39_string; + reg [39:0] _zz_43_string; + reg [31:0] _zz_44_string; + reg [71:0] _zz_45_string; + reg [39:0] _zz_46_string; + reg [23:0] _zz_47_string; + reg [63:0] _zz_48_string; + reg [95:0] _zz_49_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_51_string; + reg [95:0] _zz_115_string; + reg [63:0] _zz_116_string; + reg [23:0] _zz_117_string; + reg [39:0] _zz_118_string; + reg [71:0] _zz_119_string; + reg [31:0] _zz_120_string; + reg [39:0] _zz_121_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; - end - end + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; - end + assign _zz_226 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_227 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_228 = 1'b1; + assign _zz_229 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_230 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_231 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_232 = ((_zz_196 && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_233 = ((_zz_196 && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_234 = ((_zz_196 && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_235 = ((_zz_196 && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_236 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_237 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_238 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_239 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_240 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_241 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_242 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_243 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_244 = (IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); + assign _zz_245 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_246 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_247 = (1'b0 || (! 1'b1)); + assign _zz_248 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_249 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_250 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_251 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_252 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_253 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_254 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_255 = execute_INSTRUCTION[13 : 12]; + assign _zz_256 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_257 = (! memory_arbitration_isStuck); + assign _zz_258 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_259 = (iBus_cmd_valid || (_zz_185 != 3'b000)); + assign _zz_260 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); + assign _zz_261 = (_zz_222 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_262 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_263 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_264 = ((_zz_148 && 1'b1) && (! 1'b0)); + assign _zz_265 = ((_zz_149 && 1'b1) && (! 1'b0)); + assign _zz_266 = {_zz_65[1 : 0],_zz_65[15 : 13]}; + assign _zz_267 = _zz_65[6 : 5]; + assign _zz_268 = _zz_65[11 : 10]; + assign _zz_269 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_270 = execute_INSTRUCTION[13]; + assign _zz_271 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_272 = ($signed(_zz_273) + $signed(_zz_278)); + assign _zz_273 = ($signed(_zz_274) + $signed(_zz_276)); + assign _zz_274 = 52'h0; + assign _zz_275 = {1'b0,memory_MUL_LL}; + assign _zz_276 = {{19{_zz_275[32]}}, _zz_275}; + assign _zz_277 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_278 = {{2{_zz_277[49]}}, _zz_277}; + assign _zz_279 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_280 = {{2{_zz_279[49]}}, _zz_279}; + assign _zz_281 = ($signed(_zz_283) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_282 = _zz_281[31 : 0]; + assign _zz_283 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_284 = _zz_110[31 : 31]; + assign _zz_285 = _zz_110[30 : 30]; + assign _zz_286 = _zz_110[29 : 29]; + assign _zz_287 = _zz_110[28 : 28]; + assign _zz_288 = _zz_110[25 : 25]; + assign _zz_289 = _zz_110[17 : 17]; + assign _zz_290 = _zz_110[16 : 16]; + assign _zz_291 = _zz_110[13 : 13]; + assign _zz_292 = _zz_110[12 : 12]; + assign _zz_293 = _zz_110[11 : 11]; + assign _zz_294 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_295 = {29'd0, _zz_294}; + assign _zz_296 = _zz_110[32 : 32]; + assign _zz_297 = _zz_110[15 : 15]; + assign _zz_298 = _zz_110[5 : 5]; + assign _zz_299 = _zz_110[3 : 3]; + assign _zz_300 = _zz_110[20 : 20]; + assign _zz_301 = _zz_110[10 : 10]; + assign _zz_302 = _zz_110[4 : 4]; + assign _zz_303 = _zz_110[0 : 0]; + assign _zz_304 = (_zz_55 - 4'b0001); + assign _zz_305 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_306 = {29'd0, _zz_305}; + assign _zz_307 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_308 = {29'd0, _zz_307}; + assign _zz_309 = {{_zz_75,_zz_65[6 : 2]},12'h0}; + assign _zz_310 = {{{4'b0000,_zz_65[8 : 7]},_zz_65[12 : 9]},2'b00}; + assign _zz_311 = {{{4'b0000,_zz_65[8 : 7]},_zz_65[12 : 9]},2'b00}; + assign _zz_312 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_313 = {{_zz_98,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_314 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_315 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_316 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_317 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_318 = execute_SRC_LESS; + assign _zz_319 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz_320 = execute_INSTRUCTION[19 : 15]; + assign _zz_321 = execute_INSTRUCTION[31 : 20]; + assign _zz_322 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_323 = ($signed(_zz_324) + $signed(_zz_327)); + assign _zz_324 = ($signed(_zz_325) + $signed(_zz_326)); + assign _zz_325 = execute_SRC1; + assign _zz_326 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_327 = (execute_SRC_USE_SUB_LESS ? _zz_328 : _zz_329); + assign _zz_328 = 32'h00000001; + assign _zz_329 = 32'h0; + assign _zz_330 = execute_INSTRUCTION[31 : 20]; + assign _zz_331 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_332 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_333 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz_334 = (_zz_150 & (~ _zz_335)); + assign _zz_335 = (_zz_150 - 2'b01); + assign _zz_336 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_337 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_338 = writeBack_MUL_LOW[31 : 0]; + assign _zz_339 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_340 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_341 = {5'd0, _zz_340}; + assign _zz_342 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_343 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_344 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_345 = {_zz_152,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_346 = _zz_347; + assign _zz_347 = _zz_348; + assign _zz_348 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_153) : _zz_153)} + _zz_350); + assign _zz_349 = memory_DivPlugin_div_needRevert; + assign _zz_350 = {32'd0, _zz_349}; + assign _zz_351 = _zz_155; + assign _zz_352 = {32'd0, _zz_351}; + assign _zz_353 = _zz_154; + assign _zz_354 = {31'd0, _zz_353}; + assign _zz_355 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_356 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_357 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_358 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_359 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_360 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_361 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_362 = (iBus_cmd_payload_address >>> 5); + assign _zz_363 = 1'b1; + assign _zz_364 = 1'b1; + assign _zz_365 = {_zz_59,_zz_58}; + assign _zz_366 = 32'h0000107f; + assign _zz_367 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_368 = 32'h00002073; + assign _zz_369 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_370 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_371 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_372) == 32'h00000003),{(_zz_373 == _zz_374),{_zz_375,{_zz_376,_zz_377}}}}}}; + assign _zz_372 = 32'h0000505f; + assign _zz_373 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_374 = 32'h00000063; + assign _zz_375 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_376 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_377 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_378) == 32'h00001013),{(_zz_379 == _zz_380),{_zz_381,{_zz_382,_zz_383}}}}}}; + assign _zz_378 = 32'hfc00307f; + assign _zz_379 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_380 = 32'h00005033; + assign _zz_381 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_382 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_383 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz_384 = (_zz_65[11 : 10] == 2'b01); + assign _zz_385 = ((_zz_65[11 : 10] == 2'b11) && (_zz_65[6 : 5] == 2'b00)); + assign _zz_386 = 7'h0; + assign _zz_387 = _zz_65[6 : 2]; + assign _zz_388 = _zz_65[12]; + assign _zz_389 = _zz_65[11 : 7]; + assign _zz_390 = decode_INSTRUCTION[31]; + assign _zz_391 = decode_INSTRUCTION[19 : 12]; + assign _zz_392 = decode_INSTRUCTION[20]; + assign _zz_393 = decode_INSTRUCTION[31]; + assign _zz_394 = decode_INSTRUCTION[7]; + assign _zz_395 = 32'h10103050; + assign _zz_396 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_397 = 1'b0; + assign _zz_398 = (((decode_INSTRUCTION & _zz_401) == 32'h02000030) != 1'b0); + assign _zz_399 = ({_zz_402,_zz_403} != 2'b00); + assign _zz_400 = {(_zz_404 != 1'b0),{(_zz_405 != _zz_406),{_zz_407,{_zz_408,_zz_409}}}}; + assign _zz_401 = 32'h02004074; + assign _zz_402 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); + assign _zz_403 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz_404 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz_405 = {(_zz_410 == _zz_411),(_zz_412 == _zz_413)}; + assign _zz_406 = 2'b00; + assign _zz_407 = ({_zz_113,_zz_414} != 2'b00); + assign _zz_408 = (_zz_415 != 1'b0); + assign _zz_409 = {(_zz_416 != _zz_417),{_zz_418,{_zz_419,_zz_420}}}; + assign _zz_410 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_411 = 32'h00001050; + assign _zz_412 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_413 = 32'h00002050; + assign _zz_414 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_415 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_416 = {(_zz_421 == _zz_422),(_zz_423 == _zz_424)}; + assign _zz_417 = 2'b00; + assign _zz_418 = ({_zz_425,{_zz_426,_zz_427}} != 3'b000); + assign _zz_419 = (_zz_428 != 1'b0); + assign _zz_420 = {(_zz_429 != _zz_430),{_zz_431,{_zz_432,_zz_433}}}; + assign _zz_421 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_422 = 32'h00005010; + assign _zz_423 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_424 = 32'h00005020; + assign _zz_425 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_426 = ((decode_INSTRUCTION & _zz_434) == 32'h00001010); + assign _zz_427 = ((decode_INSTRUCTION & _zz_435) == 32'h00001010); + assign _zz_428 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_429 = ((decode_INSTRUCTION & _zz_436) == 32'h00001000); + assign _zz_430 = 1'b0; + assign _zz_431 = ((_zz_437 == _zz_438) != 1'b0); + assign _zz_432 = ({_zz_439,_zz_440} != 2'b00); + assign _zz_433 = {(_zz_441 != _zz_442),{_zz_443,{_zz_444,_zz_445}}}; + assign _zz_434 = 32'h00007034; + assign _zz_435 = 32'h02007054; + assign _zz_436 = 32'h00001000; + assign _zz_437 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_438 = 32'h00002000; + assign _zz_439 = ((decode_INSTRUCTION & _zz_446) == 32'h00002000); + assign _zz_440 = ((decode_INSTRUCTION & _zz_447) == 32'h00001000); + assign _zz_441 = ((decode_INSTRUCTION & _zz_448) == 32'h00004008); + assign _zz_442 = 1'b0; + assign _zz_443 = ({_zz_449,_zz_450} != 2'b00); + assign _zz_444 = ({_zz_451,_zz_452} != 5'h0); + assign _zz_445 = {(_zz_453 != _zz_454),{_zz_455,{_zz_456,_zz_457}}}; + assign _zz_446 = 32'h00002010; + assign _zz_447 = 32'h00005000; + assign _zz_448 = 32'h00004048; + assign _zz_449 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_450 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_451 = ((decode_INSTRUCTION & _zz_458) == 32'h00002040); + assign _zz_452 = {(_zz_459 == _zz_460),{_zz_461,{_zz_462,_zz_463}}}; + assign _zz_453 = ((decode_INSTRUCTION & _zz_464) == 32'h00000020); + assign _zz_454 = 1'b0; + assign _zz_455 = ({_zz_465,{_zz_466,_zz_467}} != 5'h0); + assign _zz_456 = ({_zz_468,_zz_469} != 5'h0); + assign _zz_457 = {(_zz_470 != _zz_471),{_zz_472,{_zz_473,_zz_474}}}; + assign _zz_458 = 32'h00002040; + assign _zz_459 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_460 = 32'h00001040; + assign _zz_461 = ((decode_INSTRUCTION & _zz_475) == 32'h00000040); + assign _zz_462 = (_zz_476 == _zz_477); + assign _zz_463 = (_zz_478 == _zz_479); + assign _zz_464 = 32'h00000020; + assign _zz_465 = ((decode_INSTRUCTION & _zz_480) == 32'h00000040); + assign _zz_466 = _zz_112; + assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; + assign _zz_468 = _zz_112; + assign _zz_469 = {_zz_484,{_zz_485,_zz_486}}; + assign _zz_470 = {_zz_113,{_zz_487,_zz_488}}; + assign _zz_471 = 6'h0; + assign _zz_472 = ({_zz_489,_zz_490} != 2'b00); + assign _zz_473 = (_zz_491 != _zz_492); + assign _zz_474 = {_zz_493,{_zz_494,_zz_495}}; + assign _zz_475 = 32'h00100040; + assign _zz_476 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_477 = 32'h00000040; + assign _zz_478 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_479 = 32'h0; + assign _zz_480 = 32'h00000040; + assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00004020); + assign _zz_482 = (_zz_497 == _zz_498); + assign _zz_483 = (_zz_499 == _zz_500); + assign _zz_484 = ((decode_INSTRUCTION & _zz_501) == 32'h00002010); + assign _zz_485 = (_zz_502 == _zz_503); + assign _zz_486 = {_zz_504,_zz_505}; + assign _zz_487 = (_zz_506 == _zz_507); + assign _zz_488 = {_zz_508,{_zz_509,_zz_510}}; + assign _zz_489 = _zz_112; + assign _zz_490 = (_zz_511 == _zz_512); + assign _zz_491 = {_zz_112,_zz_513}; + assign _zz_492 = 2'b00; + assign _zz_493 = (_zz_514 != 1'b0); + assign _zz_494 = (_zz_515 != _zz_516); + assign _zz_495 = {_zz_517,{_zz_518,_zz_519}}; + assign _zz_496 = 32'h00004020; + assign _zz_497 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_498 = 32'h00000010; + assign _zz_499 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_500 = 32'h00000020; + assign _zz_501 = 32'h00002030; + assign _zz_502 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_503 = 32'h00000010; + assign _zz_504 = ((decode_INSTRUCTION & _zz_520) == 32'h00002020); + assign _zz_505 = ((decode_INSTRUCTION & _zz_521) == 32'h00000020); + assign _zz_506 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_507 = 32'h00001010; + assign _zz_508 = ((decode_INSTRUCTION & _zz_522) == 32'h00002010); + assign _zz_509 = (_zz_523 == _zz_524); + assign _zz_510 = {_zz_525,_zz_526}; + assign _zz_511 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_512 = 32'h00000020; + assign _zz_513 = ((decode_INSTRUCTION & _zz_527) == 32'h0); + assign _zz_514 = ((decode_INSTRUCTION & _zz_528) == 32'h00004010); + assign _zz_515 = (_zz_529 == _zz_530); + assign _zz_516 = 1'b0; + assign _zz_517 = ({_zz_531,_zz_532} != 4'b0000); + assign _zz_518 = (_zz_533 != _zz_534); + assign _zz_519 = {_zz_535,{_zz_536,_zz_537}}; + assign _zz_520 = 32'h02002060; + assign _zz_521 = 32'h02003020; + assign _zz_522 = 32'h00002010; + assign _zz_523 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_524 = 32'h00000010; + assign _zz_525 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_526 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_527 = 32'h00000020; + assign _zz_528 = 32'h00004014; + assign _zz_529 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_530 = 32'h00002010; + assign _zz_531 = ((decode_INSTRUCTION & _zz_538) == 32'h0); + assign _zz_532 = {(_zz_539 == _zz_540),{_zz_541,_zz_542}}; + assign _zz_533 = ((decode_INSTRUCTION & _zz_543) == 32'h0); + assign _zz_534 = 1'b0; + assign _zz_535 = ({_zz_544,{_zz_545,_zz_546}} != 3'b000); + assign _zz_536 = ({_zz_547,_zz_548} != 2'b00); + assign _zz_537 = {(_zz_549 != _zz_550),(_zz_551 != _zz_552)}; + assign _zz_538 = 32'h00000044; + assign _zz_539 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_540 = 32'h0; + assign _zz_541 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_542 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_543 = 32'h00000058; + assign _zz_544 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_545 = ((decode_INSTRUCTION & _zz_553) == 32'h00002010); + assign _zz_546 = ((decode_INSTRUCTION & _zz_554) == 32'h40000030); + assign _zz_547 = ((decode_INSTRUCTION & _zz_555) == 32'h00000004); + assign _zz_548 = _zz_111; + assign _zz_549 = {(_zz_556 == _zz_557),_zz_111}; + assign _zz_550 = 2'b00; + assign _zz_551 = ((decode_INSTRUCTION & _zz_558) == 32'h00001008); + assign _zz_552 = 1'b0; + assign _zz_553 = 32'h00002014; + assign _zz_554 = 32'h40000034; + assign _zz_555 = 32'h00000014; + assign _zz_556 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_557 = 32'h00000004; + assign _zz_558 = 32'h00005048; + assign _zz_559 = execute_INSTRUCTION[31]; + assign _zz_560 = execute_INSTRUCTION[31]; + assign _zz_561 = execute_INSTRUCTION[7]; + assign _zz_562 = 32'h0; + always @ (posedge clk) begin + if(_zz_363) begin + _zz_223 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_12_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; + always @ (posedge clk) begin + if(_zz_364) begin + _zz_224 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; + always @ (posedge clk) begin + if(_zz_42) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_10_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_11_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid); - assign io_cpu_fetch_error = fetchStage_hit_error; - assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuBus_rsp_refilling; - assign io_cpu_fetch_mmuException = ((! io_cpu_fetch_mmuBus_rsp_refilling) && (io_cpu_fetch_mmuBus_rsp_exception || (! io_cpu_fetch_mmuBus_rsp_allowExecute))); - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; - end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; - end - if(_zz_13_)begin - lineLoader_flushPending <= 1'b0; + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_194 ), //i + .io_cpu_prefetch_isValid (_zz_195 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_196 ), //i + .io_cpu_fetch_isStuck (_zz_197 ), //i + .io_cpu_fetch_isRemoved (_zz_198 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_fetch_cacheMiss (IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss ), //o + .io_cpu_fetch_error (IBusCachedPlugin_cache_io_cpu_fetch_error ), //o + .io_cpu_fetch_mmuRefilling (IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling ), //o + .io_cpu_fetch_mmuException (IBusCachedPlugin_cache_io_cpu_fetch_mmuException ), //o + .io_cpu_fetch_isUser (_zz_199 ), //i + .io_cpu_decode_isValid (_zz_200 ), //i + .io_cpu_decode_isStuck (_zz_201 ), //i + .io_cpu_decode_pc (_zz_202[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_fill_valid (_zz_203 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_204 ), //i + .io_cpu_execute_address (_zz_205[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_105[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_206 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_207[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_208 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_209 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_210 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_211[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_212 ), //i + .io_cpu_writeBack_fence_SR (_zz_213 ), //i + .io_cpu_writeBack_fence_SO (_zz_214 ), //i + .io_cpu_writeBack_fence_SI (_zz_215 ), //i + .io_cpu_writeBack_fence_PW (_zz_216 ), //i + .io_cpu_writeBack_fence_PR (_zz_217 ), //i + .io_cpu_writeBack_fence_PO (_zz_218 ), //i + .io_cpu_writeBack_fence_PI (_zz_219 ), //i + .io_cpu_writeBack_fence_FM (_zz_220[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_221 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_222 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_365) + 2'b00 : begin + _zz_225 = DBusCachedPlugin_redoBranch_payload; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; + 2'b01 : begin + _zz_225 = CsrPlugin_jumpInterface_payload; end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; + 2'b10 : begin + _zz_225 = BranchPlugin_jumpInterface_payload; end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end + default : begin + _zz_225 = IBusCachedPlugin_predictionJumpInterface_payload; end - end + endcase end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_12_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); - end - _zz_3_ <= lineLoader_flushCounter[7]; - if(_zz_13_)begin - lineLoader_flushCounter <= (8'b00000000); - end + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; + endcase end - -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, - input [1:0] io_cpu_execute_args_size, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - input io_cpu_memory_isRemoved, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - output io_cpu_memory_mmuBus_cmd_isValid, - output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, - output io_cpu_memory_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, - input io_cpu_memory_mmuBus_rsp_isIoAccess, - input io_cpu_memory_mmuBus_rsp_allowRead, - input io_cpu_memory_mmuBus_rsp_allowWrite, - input io_cpu_memory_mmuBus_rsp_allowExecute, - input io_cpu_memory_mmuBus_rsp_exception, - input io_cpu_memory_mmuBus_rsp_refilling, - output io_cpu_memory_mmuBus_end, - input io_cpu_memory_mmuBus_busy, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output reg io_cpu_flush_ready, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, - output reg io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire _zz_16_; - wire _zz_17_; - wire [0:0] _zz_18_; - wire [0:0] _zz_19_; - wire [0:0] _zz_20_; - wire [2:0] _zz_21_; - wire [1:0] _zz_22_; - wire [21:0] _zz_23_; - reg _zz_1_; - reg _zz_2_; - wire haltCpu; - reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3_; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4_; - wire _zz_5_; - wire [31:0] ways_0_dataReadRsp; - reg [3:0] _zz_6_; - wire [3:0] stage0_mask; - wire [0:0] stage0_colisions; - reg stageA_request_wr; - reg [31:0] stageA_request_data; - reg [1:0] stageA_request_size; - reg [3:0] stageA_mask; - wire stageA_wayHits_0; - reg [0:0] stage0_colisions_regNextWhen; - wire [0:0] _zz_7_; - wire [0:0] stageA_colisions; - reg stageB_request_wr; - reg [31:0] stageB_request_data; - reg [1:0] stageB_request_size; - reg stageB_mmuRspFreeze; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg [31:0] stageB_dataReadRsp_0; - wire [0:0] _zz_8_; - reg [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - reg [3:0] stageB_mask; - reg [0:0] stageB_colisions; - reg stageB_loaderValid; - reg stageB_flusher_valid; - wire [31:0] stageB_requestDataBypass; - wire stageB_isAmo; - reg stageB_memCmdSent; - wire [0:0] _zz_9_; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [2:0] loader_counter_valueNext; - reg [2:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_24_; - reg [7:0] _zz_25_; - reg [7:0] _zz_26_; - reg [7:0] _zz_27_; - assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); - assign _zz_15_ = (loader_valid && io_mem_rsp_valid); - assign _zz_16_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - assign _zz_17_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign _zz_18_ = _zz_4_[0 : 0]; - assign _zz_19_ = _zz_4_[1 : 1]; - assign _zz_20_ = loader_counter_willIncrement; - assign _zz_21_ = {2'd0, _zz_20_}; - assign _zz_22_ = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_23_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_23_; - end + always @(*) begin + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_3_) begin - _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; - end + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase end - - always @ (*) begin - _zz_11_ = {_zz_27_, _zz_26_, _zz_25_, _zz_24_}; + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase end - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1_) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1_) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1_) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1_) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_5_) begin - _zz_24_ <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_25_ <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_26_ <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_27_ <= ways_0_data_symbol3[dataReadCmd_payload]; - end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase end - - always @ (*) begin - _zz_1_ = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_1_ = 1'b1; - end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase end - - always @ (*) begin - _zz_2_ = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_2_ = 1'b1; - end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase end - - assign haltCpu = 1'b0; - assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4_ = _zz_10_; - assign ways_0_tagsReadRsp_valid = _zz_18_[0]; - assign ways_0_tagsReadRsp_error = _zz_19_[0]; - assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; - assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRsp = _zz_11_; - always @ (*) begin - tagsReadCmd_valid = 1'b0; - if(_zz_12_)begin - tagsReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; + endcase end - - always @ (*) begin - tagsReadCmd_payload = (7'bxxxxxxx); - if(_zz_12_)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; - end + always @(*) begin + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_valid = 1'b0; - if(_zz_12_)begin - dataReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; + endcase end - - always @ (*) begin - dataReadCmd_payload = (10'bxxxxxxxxxx); - if(_zz_12_)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; - end - if(_zz_13_)begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_valid = 1'b1; - end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_way = (1'bx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = (1'b1); - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_address = (7'bxxxxxxx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_valid = 1'b1; - end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); - end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end + always @(*) begin + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((stageB_request_wr && stageB_waysHit))begin - dataWriteCmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - dataWriteCmd_valid = 1'b0; - end - if(_zz_15_)begin - dataWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_way = (1'bx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_way = stageB_waysHits; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_address = (10'bxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; - end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_data = stageB_requestDataBypass; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end + always @(*) begin + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_mask = (4'bxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_mask = stageB_mask; - end - end - end - if(_zz_15_)begin - dataWriteCmd_payload_mask = (4'b1111); - end + always @(*) begin + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; + endcase end - - always @ (*) begin - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_6_ = (4'b0001); - end - 2'b01 : begin - _zz_6_ = (4'b0011); - end - default : begin - _zz_6_ = (4'b1111); - end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; endcase end - - assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); - assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; - assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; - assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); - always @ (*) begin - stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin - stageB_mmuRspFreeze = 1'b1; - end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase end - - assign _zz_8_[0] = stageA_wayHits_0; - assign stageB_waysHit = (stageB_waysHits != (1'b0)); - assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - if(io_mem_cmd_ready)begin - stageB_loaderValid = 1'b1; - end - end - end - end - if(_zz_13_)begin - stageB_loaderValid = 1'b0; - end + always @(*) begin + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(_zz_14_)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - if(_zz_13_)begin - io_cpu_writeBack_haltIt = 1'b0; - end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(_zz_16_)begin - io_cpu_flush_ready = 1'b1; - end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase end - - assign stageB_requestDataBypass = stageB_request_data; - assign stageB_isAmo = 1'b0; - always @ (*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin - io_cpu_redo = 1'b1; - end - end - end - end - if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin - io_cpu_redo = 1'b1; - end - if(loader_valid)begin - io_cpu_redo = 1'b1; - end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); - end + always @(*) begin + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; + endcase end - - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_valid = (! stageB_memCmdSent); - end else begin - if(_zz_14_)begin - if(stageB_request_wr)begin - io_mem_cmd_valid = 1'b1; - end - end else begin - if((! stageB_memCmdSent))begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - io_mem_cmd_valid = 1'b0; - end + always @(*) begin + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; - end - end - end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_length = (3'bxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - io_mem_cmd_payload_length = (3'b111); - end - end - end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_last = 1'bx; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - io_mem_cmd_payload_last = 1'b1; - end - end - end + always @(*) begin + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - always @ (*) begin - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_data = io_mem_rsp_payload_data; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - end - - assign _zz_9_[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin - loader_counter_willIncrement = 1'b0; - if(_zz_15_)begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_21_); - if(loader_counter_willClear)begin - loader_counter_valueNext = (3'b000); - end - end - - always @ (posedge clk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; - stageA_request_size <= io_cpu_execute_args_size; - end - if((! io_cpu_memory_isStuck))begin - stageA_mask <= stage0_mask; - end - if((! io_cpu_memory_isStuck))begin - stage0_colisions_regNextWhen <= stage0_colisions; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; - stageB_request_size <= stageA_request_size; - end - if(_zz_17_)begin - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_waysHits <= _zz_8_; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_mask <= stageA_mask; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_colisions <= stageA_colisions; - end - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); - end - end - - always @ (posedge clk) begin - if(reset) begin - stageB_flusher_valid <= 1'b1; - stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); - stageB_memCmdSent <= 1'b0; - loader_valid <= 1'b0; - loader_counter_value <= (3'b000); - loader_waysAllocator <= (1'b1); - loader_error <= 1'b0; - end else begin - if(_zz_17_)begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; - end - if(stageB_flusher_valid)begin - if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); - end else begin - stageB_flusher_valid <= 1'b0; - end - end - if(_zz_16_)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); - stageB_flusher_valid <= 1'b1; - end - if(io_mem_cmd_ready)begin - stageB_memCmdSent <= 1'b1; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_memCmdSent <= 1'b0; - end - if(stageB_loaderValid)begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(_zz_15_)begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_counter_willOverflow)begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - end - if((! loader_valid))begin - loader_waysAllocator <= _zz_22_[0:0]; - end - end - end - -endmodule - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset, - input debugReset); - wire _zz_244_; - wire _zz_245_; - wire _zz_246_; - wire _zz_247_; - wire [31:0] _zz_248_; - wire _zz_249_; - wire _zz_250_; - wire _zz_251_; - wire [31:0] _zz_252_; - reg _zz_253_; - wire _zz_254_; - wire [31:0] _zz_255_; - wire _zz_256_; - wire [31:0] _zz_257_; - reg _zz_258_; - wire _zz_259_; - wire _zz_260_; - wire [31:0] _zz_261_; - wire _zz_262_; - wire _zz_263_; - reg [31:0] _zz_264_; - reg [31:0] _zz_265_; - reg [31:0] _zz_266_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_error; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1__io_cpu_memory_isWrite; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; - wire dataCache_1__io_cpu_memory_mmuBus_end; - wire dataCache_1__io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1__io_cpu_writeBack_data; - wire dataCache_1__io_cpu_writeBack_mmuException; - wire dataCache_1__io_cpu_writeBack_unalignedAccess; - wire dataCache_1__io_cpu_writeBack_accessError; - wire dataCache_1__io_cpu_writeBack_isWrite; - wire dataCache_1__io_cpu_flush_ready; - wire dataCache_1__io_cpu_redo; - wire dataCache_1__io_mem_cmd_valid; - wire dataCache_1__io_mem_cmd_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_payload_length; - wire dataCache_1__io_mem_cmd_payload_last; - wire _zz_267_; - wire _zz_268_; - wire _zz_269_; - wire _zz_270_; - wire _zz_271_; - wire _zz_272_; - wire _zz_273_; - wire _zz_274_; - wire _zz_275_; - wire _zz_276_; - wire _zz_277_; - wire _zz_278_; - wire _zz_279_; - wire _zz_280_; - wire _zz_281_; - wire _zz_282_; - wire _zz_283_; - wire _zz_284_; - wire [1:0] _zz_285_; - wire _zz_286_; - wire _zz_287_; - wire _zz_288_; - wire _zz_289_; - wire _zz_290_; - wire _zz_291_; - wire _zz_292_; - wire _zz_293_; - wire _zz_294_; - wire _zz_295_; - wire _zz_296_; - wire _zz_297_; - wire [1:0] _zz_298_; - wire _zz_299_; - wire [5:0] _zz_300_; - wire _zz_301_; - wire _zz_302_; - wire _zz_303_; - wire _zz_304_; - wire _zz_305_; - wire _zz_306_; - wire [4:0] _zz_307_; - wire [1:0] _zz_308_; - wire [1:0] _zz_309_; - wire [1:0] _zz_310_; - wire _zz_311_; - wire [1:0] _zz_312_; - wire [4:0] _zz_313_; - wire [2:0] _zz_314_; - wire [31:0] _zz_315_; - wire [2:0] _zz_316_; - wire [31:0] _zz_317_; - wire [31:0] _zz_318_; - wire [11:0] _zz_319_; - wire [11:0] _zz_320_; - wire [2:0] _zz_321_; - wire [31:0] _zz_322_; - wire [11:0] _zz_323_; - wire [31:0] _zz_324_; - wire [19:0] _zz_325_; - wire [11:0] _zz_326_; - wire [2:0] _zz_327_; - wire [2:0] _zz_328_; - wire [0:0] _zz_329_; - wire [0:0] _zz_330_; - wire [0:0] _zz_331_; - wire [0:0] _zz_332_; - wire [0:0] _zz_333_; - wire [0:0] _zz_334_; - wire [0:0] _zz_335_; - wire [0:0] _zz_336_; - wire [0:0] _zz_337_; - wire [0:0] _zz_338_; - wire [0:0] _zz_339_; - wire [0:0] _zz_340_; - wire [0:0] _zz_341_; - wire [0:0] _zz_342_; - wire [0:0] _zz_343_; - wire [0:0] _zz_344_; - wire [0:0] _zz_345_; - wire [0:0] _zz_346_; - wire [0:0] _zz_347_; - wire [2:0] _zz_348_; - wire [4:0] _zz_349_; - wire [11:0] _zz_350_; - wire [11:0] _zz_351_; - wire [31:0] _zz_352_; - wire [31:0] _zz_353_; - wire [31:0] _zz_354_; - wire [31:0] _zz_355_; - wire [31:0] _zz_356_; - wire [31:0] _zz_357_; - wire [31:0] _zz_358_; - wire [32:0] _zz_359_; - wire [31:0] _zz_360_; - wire [32:0] _zz_361_; - wire [11:0] _zz_362_; - wire [19:0] _zz_363_; - wire [11:0] _zz_364_; - wire [2:0] _zz_365_; - wire [1:0] _zz_366_; - wire [1:0] _zz_367_; - wire [51:0] _zz_368_; - wire [51:0] _zz_369_; - wire [51:0] _zz_370_; - wire [32:0] _zz_371_; - wire [51:0] _zz_372_; - wire [49:0] _zz_373_; - wire [51:0] _zz_374_; - wire [49:0] _zz_375_; - wire [51:0] _zz_376_; - wire [65:0] _zz_377_; - wire [65:0] _zz_378_; - wire [31:0] _zz_379_; - wire [31:0] _zz_380_; - wire [0:0] _zz_381_; - wire [5:0] _zz_382_; - wire [32:0] _zz_383_; - wire [32:0] _zz_384_; - wire [31:0] _zz_385_; - wire [31:0] _zz_386_; - wire [32:0] _zz_387_; - wire [32:0] _zz_388_; - wire [32:0] _zz_389_; - wire [0:0] _zz_390_; - wire [32:0] _zz_391_; - wire [0:0] _zz_392_; - wire [32:0] _zz_393_; - wire [0:0] _zz_394_; - wire [31:0] _zz_395_; - wire [0:0] _zz_396_; - wire [0:0] _zz_397_; - wire [0:0] _zz_398_; - wire [0:0] _zz_399_; - wire [0:0] _zz_400_; - wire [0:0] _zz_401_; - wire [0:0] _zz_402_; - wire [26:0] _zz_403_; - wire _zz_404_; - wire _zz_405_; - wire [2:0] _zz_406_; - wire _zz_407_; - wire _zz_408_; - wire [6:0] _zz_409_; - wire [4:0] _zz_410_; - wire _zz_411_; - wire [4:0] _zz_412_; - wire [0:0] _zz_413_; - wire [7:0] _zz_414_; - wire _zz_415_; - wire [0:0] _zz_416_; - wire [0:0] _zz_417_; - wire [31:0] _zz_418_; - wire [31:0] _zz_419_; - wire [31:0] _zz_420_; - wire [31:0] _zz_421_; - wire _zz_422_; - wire [0:0] _zz_423_; - wire [0:0] _zz_424_; - wire [0:0] _zz_425_; - wire [0:0] _zz_426_; - wire _zz_427_; - wire [0:0] _zz_428_; - wire [26:0] _zz_429_; - wire [31:0] _zz_430_; - wire [31:0] _zz_431_; - wire _zz_432_; - wire [0:0] _zz_433_; - wire [2:0] _zz_434_; - wire _zz_435_; - wire [0:0] _zz_436_; - wire [0:0] _zz_437_; - wire _zz_438_; - wire [0:0] _zz_439_; - wire [23:0] _zz_440_; - wire [31:0] _zz_441_; - wire [31:0] _zz_442_; - wire [31:0] _zz_443_; - wire _zz_444_; - wire _zz_445_; - wire [31:0] _zz_446_; - wire _zz_447_; - wire _zz_448_; - wire _zz_449_; - wire [1:0] _zz_450_; - wire [1:0] _zz_451_; - wire _zz_452_; - wire [0:0] _zz_453_; - wire [20:0] _zz_454_; - wire [31:0] _zz_455_; - wire [31:0] _zz_456_; - wire [31:0] _zz_457_; - wire [31:0] _zz_458_; - wire [31:0] _zz_459_; - wire [31:0] _zz_460_; - wire [0:0] _zz_461_; - wire [0:0] _zz_462_; - wire [0:0] _zz_463_; - wire [0:0] _zz_464_; - wire _zz_465_; - wire [0:0] _zz_466_; - wire [17:0] _zz_467_; - wire [31:0] _zz_468_; - wire [31:0] _zz_469_; - wire [31:0] _zz_470_; - wire [31:0] _zz_471_; - wire [0:0] _zz_472_; - wire [0:0] _zz_473_; - wire [1:0] _zz_474_; - wire [1:0] _zz_475_; - wire _zz_476_; - wire [0:0] _zz_477_; - wire [14:0] _zz_478_; - wire [31:0] _zz_479_; - wire [31:0] _zz_480_; - wire [31:0] _zz_481_; - wire _zz_482_; - wire [0:0] _zz_483_; - wire [1:0] _zz_484_; - wire [0:0] _zz_485_; - wire [0:0] _zz_486_; - wire [2:0] _zz_487_; - wire [2:0] _zz_488_; - wire _zz_489_; - wire [0:0] _zz_490_; - wire [11:0] _zz_491_; - wire [31:0] _zz_492_; - wire [31:0] _zz_493_; - wire [31:0] _zz_494_; - wire _zz_495_; - wire _zz_496_; - wire [31:0] _zz_497_; - wire [31:0] _zz_498_; - wire [31:0] _zz_499_; - wire [31:0] _zz_500_; - wire _zz_501_; - wire [0:0] _zz_502_; - wire [0:0] _zz_503_; - wire _zz_504_; - wire [1:0] _zz_505_; - wire [1:0] _zz_506_; - wire _zz_507_; - wire [0:0] _zz_508_; - wire [9:0] _zz_509_; - wire [31:0] _zz_510_; - wire [31:0] _zz_511_; - wire [31:0] _zz_512_; - wire [31:0] _zz_513_; - wire [31:0] _zz_514_; - wire [31:0] _zz_515_; - wire [31:0] _zz_516_; - wire [31:0] _zz_517_; - wire _zz_518_; - wire _zz_519_; - wire _zz_520_; - wire [0:0] _zz_521_; - wire [0:0] _zz_522_; - wire _zz_523_; - wire [0:0] _zz_524_; - wire [7:0] _zz_525_; - wire [31:0] _zz_526_; - wire _zz_527_; - wire [0:0] _zz_528_; - wire [2:0] _zz_529_; - wire [0:0] _zz_530_; - wire [4:0] _zz_531_; - wire [4:0] _zz_532_; - wire [4:0] _zz_533_; - wire _zz_534_; - wire [0:0] _zz_535_; - wire [4:0] _zz_536_; - wire [31:0] _zz_537_; - wire [31:0] _zz_538_; - wire _zz_539_; - wire _zz_540_; - wire [31:0] _zz_541_; - wire [31:0] _zz_542_; - wire _zz_543_; - wire [0:0] _zz_544_; - wire [1:0] _zz_545_; - wire _zz_546_; - wire [0:0] _zz_547_; - wire [1:0] _zz_548_; - wire _zz_549_; - wire [0:0] _zz_550_; - wire [0:0] _zz_551_; - wire _zz_552_; - wire [0:0] _zz_553_; - wire [0:0] _zz_554_; - wire _zz_555_; - wire [0:0] _zz_556_; - wire [1:0] _zz_557_; - wire [31:0] _zz_558_; - wire [31:0] _zz_559_; - wire [31:0] _zz_560_; - wire [31:0] _zz_561_; - wire [31:0] _zz_562_; - wire _zz_563_; - wire _zz_564_; - wire [31:0] _zz_565_; - wire [31:0] _zz_566_; - wire [31:0] _zz_567_; - wire _zz_568_; - wire _zz_569_; - wire [31:0] _zz_570_; - wire [31:0] _zz_571_; - wire [31:0] _zz_572_; - wire [31:0] _zz_573_; - wire [31:0] _zz_574_; - wire [31:0] _zz_575_; - wire [31:0] _zz_576_; - wire [31:0] _zz_577_; - wire [0:0] _zz_578_; - wire [0:0] _zz_579_; - wire _zz_580_; - wire _zz_581_; - wire [31:0] _zz_582_; - wire [31:0] _zz_583_; - wire [31:0] _zz_584_; - wire _zz_585_; - wire [0:0] _zz_586_; - wire [13:0] _zz_587_; - wire [31:0] _zz_588_; - wire [31:0] _zz_589_; - wire [31:0] _zz_590_; - wire _zz_591_; - wire [0:0] _zz_592_; - wire [7:0] _zz_593_; - wire [31:0] _zz_594_; - wire [31:0] _zz_595_; - wire [31:0] _zz_596_; - wire _zz_597_; - wire [0:0] _zz_598_; - wire [1:0] _zz_599_; - wire _zz_600_; - wire _zz_601_; - wire _zz_602_; - wire [31:0] execute_SHIFT_RIGHT; - wire decode_IS_RS1_SIGNED; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire memory_IS_MUL; - wire execute_IS_MUL; - wire decode_IS_MUL; - wire decode_SRC_LESS_UNSIGNED; - wire decode_SRC2_FORCE_ZERO; - wire decode_IS_RS2_SIGNED; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_8_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_9_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12_; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_13_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_14_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_15_; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_16_; - wire `AluCtrlEnum_defaultEncoding_type _zz_17_; - wire `AluCtrlEnum_defaultEncoding_type _zz_18_; - wire decode_CSR_READ_OPCODE; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire [51:0] memory_MUL_LOW; - wire decode_DO_EBREAK; - wire decode_IS_DIV; - wire decode_IS_CSR; - wire decode_CSR_WRITE_OPCODE; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_21_; - wire [33:0] execute_MUL_HL; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire [31:0] execute_MUL_LL; - wire [33:0] execute_MUL_LH; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire `BranchCtrlEnum_defaultEncoding_type _zz_22_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_23_; - wire [31:0] memory_PC; - wire [31:0] execute_BRANCH_CALC; - wire decode_MEMORY_MANAGMENT; - wire execute_BRANCH_DO; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_24_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_25_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_26_; - wire decode_PREDICTION_HAD_BRANCHED2; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; - wire _zz_27_; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire [51:0] _zz_28_; - wire [33:0] _zz_29_; - wire [33:0] _zz_30_; - wire [33:0] _zz_31_; - wire [31:0] _zz_32_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34_; - wire _zz_35_; - wire _zz_36_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_37_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_38_; - wire [31:0] execute_PC; - wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_39_; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_40_; - wire _zz_41_; - wire _zz_42_; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_43_; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_44_; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45_; - wire [31:0] _zz_46_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_47_; - wire _zz_48_; - wire [31:0] _zz_49_; - wire [31:0] _zz_50_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_51_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_52_; - wire [31:0] _zz_53_; - wire execute_IS_RVC; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_54_; - wire [31:0] _zz_55_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_56_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_57_; - wire [31:0] _zz_58_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_59_; - wire [31:0] _zz_60_; - wire _zz_61_; - reg _zz_62_; - wire [31:0] _zz_63_; - wire [31:0] _zz_64_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_65_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_66_; - wire _zz_67_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_68_; - wire _zz_69_; - wire _zz_70_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_71_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_72_; - wire _zz_73_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_74_; - wire _zz_75_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_76_; - wire _zz_77_; - wire _zz_78_; - wire _zz_79_; - wire _zz_80_; - wire _zz_81_; - wire _zz_82_; - wire _zz_83_; - wire _zz_84_; - wire _zz_85_; - wire _zz_86_; - wire _zz_87_; - wire _zz_88_; - wire `AluCtrlEnum_defaultEncoding_type _zz_89_; - wire _zz_90_; - reg [31:0] _zz_91_; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_ENABLE; - wire [1:0] _zz_92_; - wire execute_MEMORY_MANAGMENT; - wire [31:0] execute_RS2; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_93_; - reg _zz_94_; - reg _zz_95_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_96_; - reg [31:0] _zz_97_; - reg [31:0] _zz_98_; - wire [31:0] decode_PC; - wire [31:0] _zz_99_; - wire _zz_100_; - wire [31:0] _zz_101_; - wire [31:0] _zz_102_; - wire [31:0] decode_INSTRUCTION; - wire [31:0] _zz_103_; - wire decode_IS_RVC; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_predictionJumpInterface_valid; - (* syn_keep , keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; - wire IBusCachedPlugin_decodePrediction_cmd_hadBranch; - wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire DBusCachedPlugin_mmuBus_rsp_allowRead; - wire DBusCachedPlugin_mmuBus_rsp_allowWrite; - wire DBusCachedPlugin_mmuBus_rsp_allowExecute; - wire DBusCachedPlugin_mmuBus_rsp_exception; - wire DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_104_; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; - reg IBusCachedPlugin_injectionPort_valid; - reg IBusCachedPlugin_injectionPort_ready; - wire [31:0] IBusCachedPlugin_injectionPort_payload; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_105_; - wire [4:0] _zz_106_; - wire _zz_107_; - wire _zz_108_; - wire _zz_109_; - wire _zz_110_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - reg [31:0] IBusCachedPlugin_decodePc_pcReg /* verilator public */ ; - wire [31:0] IBusCachedPlugin_decodePc_pcPlus; - reg IBusCachedPlugin_decodePc_injectedDecode; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_111_; - wire _zz_112_; - wire _zz_113_; - wire _zz_114_; - reg _zz_115_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_output_valid; - wire IBusCachedPlugin_iBusRsp_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; - wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; - wire IBusCachedPlugin_decompressor_inputBeforeStage_valid; - wire IBusCachedPlugin_decompressor_inputBeforeStage_ready; - wire [31:0] IBusCachedPlugin_decompressor_inputBeforeStage_payload_pc; - wire IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_error; - wire [31:0] IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_inst; - wire IBusCachedPlugin_decompressor_inputBeforeStage_payload_isRvc; - reg IBusCachedPlugin_decompressor_bufferValid; - reg [15:0] IBusCachedPlugin_decompressor_bufferData; - wire [31:0] IBusCachedPlugin_decompressor_raw; - wire IBusCachedPlugin_decompressor_isRvc; - wire [15:0] _zz_116_; - reg [31:0] IBusCachedPlugin_decompressor_decompressed; - wire [4:0] _zz_117_; - wire [4:0] _zz_118_; - wire [11:0] _zz_119_; - wire _zz_120_; - reg [11:0] _zz_121_; - wire _zz_122_; - reg [9:0] _zz_123_; - wire [20:0] _zz_124_; - wire _zz_125_; - reg [14:0] _zz_126_; - wire _zz_127_; - reg [2:0] _zz_128_; - wire _zz_129_; - reg [9:0] _zz_130_; - wire [20:0] _zz_131_; - wire _zz_132_; - reg [4:0] _zz_133_; - wire [12:0] _zz_134_; - wire [4:0] _zz_135_; - wire [4:0] _zz_136_; - wire [4:0] _zz_137_; - wire _zz_138_; - reg [2:0] _zz_139_; - reg [2:0] _zz_140_; - wire _zz_141_; - reg [6:0] _zz_142_; - reg IBusCachedPlugin_decompressor_bufferFill; - wire IBusCachedPlugin_injector_decodeInput_valid; - wire IBusCachedPlugin_injector_decodeInput_ready; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; - wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; - reg _zz_143_; - reg [31:0] _zz_144_; - reg _zz_145_; - reg [31:0] _zz_146_; - reg _zz_147_; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_decodeRemoved; - reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; - wire _zz_148_; - reg [18:0] _zz_149_; - wire _zz_150_; - reg [10:0] _zz_151_; - wire _zz_152_; - reg [18:0] _zz_153_; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_154_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; - wire dBus_cmd_payload_last; - wire dBus_rsp_valid; - wire [31:0] dBus_rsp_payload_data; - wire dBus_rsp_payload_error; - wire dataCache_1__io_mem_cmd_s2mPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; - reg _zz_155_; - reg _zz_156_; - reg [31:0] _zz_157_; - reg [31:0] _zz_158_; - reg [3:0] _zz_159_; - reg [2:0] _zz_160_; - reg _zz_161_; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg _zz_162_; - reg _zz_163_; - reg [31:0] _zz_164_; - reg [31:0] _zz_165_; - reg [3:0] _zz_166_; - reg [2:0] _zz_167_; - reg _zz_168_; - wire [31:0] _zz_169_; - reg [31:0] DBusCachedPlugin_rspCounter; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_170_; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_171_; - reg [31:0] _zz_172_; - wire _zz_173_; - reg [31:0] _zz_174_; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [32:0] _zz_175_; - wire _zz_176_; - wire _zz_177_; - wire _zz_178_; - wire _zz_179_; - wire `AluCtrlEnum_defaultEncoding_type _zz_180_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_181_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_182_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_183_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_184_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_185_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_186_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_187_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_188_; - reg [31:0] _zz_189_; - wire _zz_190_; - reg [19:0] _zz_191_; - wire _zz_192_; - reg [19:0] _zz_193_; - reg [31:0] _zz_194_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_195_; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_196_; - reg _zz_197_; - reg _zz_198_; - wire _zz_199_; - reg _zz_200_; - reg [4:0] _zz_201_; - reg [31:0] _zz_202_; - wire _zz_203_; - wire _zz_204_; - wire _zz_205_; - wire _zz_206_; - wire _zz_207_; - wire _zz_208_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_209_; - reg _zz_210_; - reg _zz_211_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_212_; - reg [19:0] _zz_213_; - wire _zz_214_; - reg [10:0] _zz_215_; - wire _zz_216_; - reg [18:0] _zz_217_; - wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] CsrPlugin_misa_base; - reg [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_218_; - wire _zz_219_; - wire _zz_220_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_221_; - wire _zz_222_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - reg CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - reg execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - wire [65:0] writeBack_MulPlugin_result; - reg [32:0] memory_DivPlugin_rs1; - reg [31:0] memory_DivPlugin_rs2; - reg [64:0] memory_DivPlugin_accumulator; - reg memory_DivPlugin_div_needRevert; - reg memory_DivPlugin_div_counter_willIncrement; - reg memory_DivPlugin_div_counter_willClear; - reg [5:0] memory_DivPlugin_div_counter_valueNext; - reg [5:0] memory_DivPlugin_div_counter_value; - wire memory_DivPlugin_div_counter_willOverflowIfInc; - wire memory_DivPlugin_div_counter_willOverflow; - reg memory_DivPlugin_div_done; - reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_223_; - wire [32:0] _zz_224_; - wire [32:0] _zz_225_; - wire [31:0] _zz_226_; - wire _zz_227_; - wire _zz_228_; - reg [32:0] _zz_229_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_230_; - wire [31:0] _zz_231_; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_232_; - reg _zz_233_; - reg DebugPlugin_resetIt_regNext; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg execute_to_memory_BRANCH_DO; - reg decode_to_execute_MEMORY_MANAGMENT; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg decode_to_execute_IS_RVC; - reg [33:0] execute_to_memory_MUL_LH; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg [31:0] execute_to_memory_MUL_LL; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg [33:0] execute_to_memory_MUL_HL; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg decode_to_execute_IS_CSR; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg decode_to_execute_DO_EBREAK; - reg [51:0] memory_to_writeBack_MUL_LOW; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg decode_to_execute_CSR_READ_OPCODE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg [33:0] execute_to_memory_MUL_HH; - reg [33:0] memory_to_writeBack_MUL_HH; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg decode_to_execute_IS_RS2_SIGNED; - reg [31:0] decode_to_execute_RS1; - reg [31:0] decode_to_execute_RS2; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg memory_to_writeBack_IS_MUL; - reg decode_to_execute_MEMORY_WR; - reg execute_to_memory_MEMORY_WR; - reg memory_to_writeBack_MEMORY_WR; - reg decode_to_execute_IS_RS1_SIGNED; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg [2:0] _zz_234_; - reg [2:0] _zz_235_; - reg _zz_236_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_237_; - wire _zz_238_; - wire _zz_239_; - wire _zz_240_; - wire _zz_241_; - wire _zz_242_; - reg _zz_243_; - reg [31:0] dBusWishbone_DAT_MISO_regNext; - `ifndef SYNTHESIS - reg [39:0] _zz_1__string; - reg [39:0] _zz_2__string; - reg [39:0] _zz_3__string; - reg [39:0] _zz_4__string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5__string; - reg [39:0] _zz_6__string; - reg [39:0] _zz_7__string; - reg [71:0] _zz_8__string; - reg [71:0] _zz_9__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_10__string; - reg [71:0] _zz_11__string; - reg [71:0] _zz_12__string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_13__string; - reg [95:0] _zz_14__string; - reg [95:0] _zz_15__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_16__string; - reg [63:0] _zz_17__string; - reg [63:0] _zz_18__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_19__string; - reg [39:0] _zz_20__string; - reg [39:0] _zz_21__string; - reg [31:0] _zz_22__string; - reg [31:0] _zz_23__string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_24__string; - reg [23:0] _zz_25__string; - reg [23:0] _zz_26__string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33__string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34__string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_37__string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_40__string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_45__string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_47__string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_52__string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_54__string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_57__string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_59__string; - reg [23:0] _zz_66__string; - reg [39:0] _zz_68__string; - reg [39:0] _zz_71__string; - reg [31:0] _zz_72__string; - reg [95:0] _zz_74__string; - reg [71:0] _zz_76__string; - reg [63:0] _zz_89__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_96__string; - reg [63:0] _zz_180__string; - reg [71:0] _zz_181__string; - reg [95:0] _zz_182__string; - reg [31:0] _zz_183__string; - reg [39:0] _zz_184__string; - reg [39:0] _zz_185__string; - reg [23:0] _zz_186__string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; - `endif - - (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_267_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_268_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_269_ = 1'b1; - assign _zz_270_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_271_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_272_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_273_ = ((_zz_246_ && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! _zz_93_)); - assign _zz_274_ = ((_zz_246_ && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! _zz_94_)); - assign _zz_275_ = ((_zz_246_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! _zz_95_)); - assign _zz_276_ = ((_zz_246_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! 1'b0)); - assign _zz_277_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_278_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_279_ = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_280_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0); - assign _zz_281_ = (! memory_DivPlugin_div_done); - assign _zz_282_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_283_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_284_ = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_285_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_286_ = (IBusCachedPlugin_iBusRsp_output_valid && IBusCachedPlugin_iBusRsp_output_ready); - assign _zz_287_ = ((! (((! IBusCachedPlugin_decompressor_isRvc) && (! IBusCachedPlugin_iBusRsp_output_payload_pc[1])) && (! IBusCachedPlugin_decompressor_bufferValid))) && (! ((IBusCachedPlugin_decompressor_isRvc && IBusCachedPlugin_iBusRsp_output_payload_pc[1]) && IBusCachedPlugin_decompressor_inputBeforeStage_ready))); - assign _zz_288_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_289_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_290_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_291_ = (1'b0 || (! 1'b1)); - assign _zz_292_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_293_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_294_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_295_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_296_ = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_297_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_298_ = execute_INSTRUCTION[13 : 12]; - assign _zz_299_ = (! memory_arbitration_isStuck); - assign _zz_300_ = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_301_ = (iBus_cmd_valid || (_zz_235_ != (3'b000))); - assign _zz_302_ = (_zz_263_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); - assign _zz_303_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_304_ = ((_zz_218_ && 1'b1) && (! 1'b0)); - assign _zz_305_ = ((_zz_219_ && 1'b1) && (! 1'b0)); - assign _zz_306_ = ((_zz_220_ && 1'b1) && (! 1'b0)); - assign _zz_307_ = {_zz_116_[1 : 0],_zz_116_[15 : 13]}; - assign _zz_308_ = _zz_116_[6 : 5]; - assign _zz_309_ = _zz_116_[11 : 10]; - assign _zz_310_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_311_ = execute_INSTRUCTION[13]; - assign _zz_312_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_313_ = (_zz_105_ - (5'b00001)); - assign _zz_314_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_315_ = {29'd0, _zz_314_}; - assign _zz_316_ = (decode_IS_RVC ? (3'b010) : (3'b100)); - assign _zz_317_ = {29'd0, _zz_316_}; - assign _zz_318_ = {{_zz_126_,_zz_116_[6 : 2]},(12'b000000000000)}; - assign _zz_319_ = {{{(4'b0000),_zz_116_[8 : 7]},_zz_116_[12 : 9]},(2'b00)}; - assign _zz_320_ = {{{(4'b0000),_zz_116_[8 : 7]},_zz_116_[12 : 9]},(2'b00)}; - assign _zz_321_ = (decode_IS_RVC ? (3'b010) : (3'b100)); - assign _zz_322_ = {29'd0, _zz_321_}; - assign _zz_323_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_324_ = {{_zz_149_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_325_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_326_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_327_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); - assign _zz_328_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); - assign _zz_329_ = _zz_175_[2 : 2]; - assign _zz_330_ = _zz_175_[3 : 3]; - assign _zz_331_ = _zz_175_[4 : 4]; - assign _zz_332_ = _zz_175_[5 : 5]; - assign _zz_333_ = _zz_175_[6 : 6]; - assign _zz_334_ = _zz_175_[7 : 7]; - assign _zz_335_ = _zz_175_[8 : 8]; - assign _zz_336_ = _zz_175_[9 : 9]; - assign _zz_337_ = _zz_175_[10 : 10]; - assign _zz_338_ = _zz_175_[11 : 11]; - assign _zz_339_ = _zz_175_[12 : 12]; - assign _zz_340_ = _zz_175_[13 : 13]; - assign _zz_341_ = _zz_175_[16 : 16]; - assign _zz_342_ = _zz_175_[19 : 19]; - assign _zz_343_ = _zz_175_[24 : 24]; - assign _zz_344_ = _zz_175_[25 : 25]; - assign _zz_345_ = _zz_175_[29 : 29]; - assign _zz_346_ = _zz_175_[32 : 32]; - assign _zz_347_ = execute_SRC_LESS; - assign _zz_348_ = (execute_IS_RVC ? (3'b010) : (3'b100)); - assign _zz_349_ = execute_INSTRUCTION[19 : 15]; - assign _zz_350_ = execute_INSTRUCTION[31 : 20]; - assign _zz_351_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_352_ = ($signed(_zz_353_) + $signed(_zz_356_)); - assign _zz_353_ = ($signed(_zz_354_) + $signed(_zz_355_)); - assign _zz_354_ = execute_SRC1; - assign _zz_355_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_356_ = (execute_SRC_USE_SUB_LESS ? _zz_357_ : _zz_358_); - assign _zz_357_ = (32'b00000000000000000000000000000001); - assign _zz_358_ = (32'b00000000000000000000000000000000); - assign _zz_359_ = ($signed(_zz_361_) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_360_ = _zz_359_[31 : 0]; - assign _zz_361_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_362_ = execute_INSTRUCTION[31 : 20]; - assign _zz_363_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_364_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_365_ = (execute_IS_RVC ? (3'b010) : (3'b100)); - assign _zz_366_ = (_zz_221_ & (~ _zz_367_)); - assign _zz_367_ = (_zz_221_ - (2'b01)); - assign _zz_368_ = ($signed(_zz_369_) + $signed(_zz_374_)); - assign _zz_369_ = ($signed(_zz_370_) + $signed(_zz_372_)); - assign _zz_370_ = (52'b0000000000000000000000000000000000000000000000000000); - assign _zz_371_ = {1'b0,memory_MUL_LL}; - assign _zz_372_ = {{19{_zz_371_[32]}}, _zz_371_}; - assign _zz_373_ = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_374_ = {{2{_zz_373_[49]}}, _zz_373_}; - assign _zz_375_ = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_376_ = {{2{_zz_375_[49]}}, _zz_375_}; - assign _zz_377_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_378_ = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_379_ = writeBack_MUL_LOW[31 : 0]; - assign _zz_380_ = writeBack_MulPlugin_result[63 : 32]; - assign _zz_381_ = memory_DivPlugin_div_counter_willIncrement; - assign _zz_382_ = {5'd0, _zz_381_}; - assign _zz_383_ = {1'd0, memory_DivPlugin_rs2}; - assign _zz_384_ = {_zz_223_,(! _zz_225_[32])}; - assign _zz_385_ = _zz_225_[31:0]; - assign _zz_386_ = _zz_224_[31:0]; - assign _zz_387_ = _zz_388_; - assign _zz_388_ = _zz_389_; - assign _zz_389_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_226_) : _zz_226_)} + _zz_391_); - assign _zz_390_ = memory_DivPlugin_div_needRevert; - assign _zz_391_ = {32'd0, _zz_390_}; - assign _zz_392_ = _zz_228_; - assign _zz_393_ = {32'd0, _zz_392_}; - assign _zz_394_ = _zz_227_; - assign _zz_395_ = {31'd0, _zz_394_}; - assign _zz_396_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_397_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_398_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_399_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_400_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_401_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_402_ = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_403_ = (iBus_cmd_payload_address >>> 5); - assign _zz_404_ = 1'b1; - assign _zz_405_ = 1'b1; - assign _zz_406_ = {_zz_108_,{_zz_110_,_zz_109_}}; - assign _zz_407_ = (_zz_116_[11 : 10] == (2'b01)); - assign _zz_408_ = ((_zz_116_[11 : 10] == (2'b11)) && (_zz_116_[6 : 5] == (2'b00))); - assign _zz_409_ = (7'b0000000); - assign _zz_410_ = _zz_116_[6 : 2]; - assign _zz_411_ = _zz_116_[12]; - assign _zz_412_ = _zz_116_[11 : 7]; - assign _zz_413_ = decode_INSTRUCTION[31]; - assign _zz_414_ = decode_INSTRUCTION[19 : 12]; - assign _zz_415_ = decode_INSTRUCTION[20]; - assign _zz_416_ = decode_INSTRUCTION[31]; - assign _zz_417_ = decode_INSTRUCTION[7]; - assign _zz_418_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); - assign _zz_419_ = (32'b00000000000000000001000001010000); - assign _zz_420_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); - assign _zz_421_ = (32'b00000000000000000010000001010000); - assign _zz_422_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); - assign _zz_423_ = _zz_177_; - assign _zz_424_ = ((decode_INSTRUCTION & _zz_430_) == (32'b00000000000000000000000000000000)); - assign _zz_425_ = ((decode_INSTRUCTION & _zz_431_) == (32'b00000000000000000001000000001000)); - assign _zz_426_ = (1'b0); - assign _zz_427_ = ({_zz_432_,{_zz_433_,_zz_434_}} != (5'b00000)); - assign _zz_428_ = (_zz_435_ != (1'b0)); - assign _zz_429_ = {(_zz_436_ != _zz_437_),{_zz_438_,{_zz_439_,_zz_440_}}}; - assign _zz_430_ = (32'b00000000000000000000000000100000); - assign _zz_431_ = (32'b00000000000000000101000001001000); - assign _zz_432_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001000000)) == (32'b00000000000000000010000001000000)); - assign _zz_433_ = ((decode_INSTRUCTION & _zz_441_) == (32'b00000000000000000001000001000000)); - assign _zz_434_ = {(_zz_442_ == _zz_443_),{_zz_444_,_zz_445_}}; - assign _zz_435_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_436_ = ((decode_INSTRUCTION & _zz_446_) == (32'b00000000000000000010000000000000)); - assign _zz_437_ = (1'b0); - assign _zz_438_ = ({_zz_447_,_zz_448_} != (2'b00)); - assign _zz_439_ = (_zz_449_ != (1'b0)); - assign _zz_440_ = {(_zz_450_ != _zz_451_),{_zz_452_,{_zz_453_,_zz_454_}}}; - assign _zz_441_ = (32'b00000000000000000001000001000000); - assign _zz_442_ = (decode_INSTRUCTION & (32'b00000000000100000000000001000000)); - assign _zz_443_ = (32'b00000000000000000000000001000000); - assign _zz_444_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000001000000)); - assign _zz_445_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000111000)) == (32'b00000000000000000000000000000000)); - assign _zz_446_ = (32'b00000000000000000011000000000000); - assign _zz_447_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)); - assign _zz_448_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_449_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001110100)) == (32'b00000010000000000000000000110000)); - assign _zz_450_ = {(_zz_455_ == _zz_456_),(_zz_457_ == _zz_458_)}; - assign _zz_451_ = (2'b00); - assign _zz_452_ = ((_zz_459_ == _zz_460_) != (1'b0)); - assign _zz_453_ = ({_zz_461_,_zz_462_} != (2'b00)); - assign _zz_454_ = {(_zz_463_ != _zz_464_),{_zz_465_,{_zz_466_,_zz_467_}}}; - assign _zz_455_ = (decode_INSTRUCTION & (32'b00010000001000000011000001010000)); - assign _zz_456_ = (32'b00010000000000000000000001010000); - assign _zz_457_ = (decode_INSTRUCTION & (32'b00010000000100000011000001010000)); - assign _zz_458_ = (32'b00000000000000000000000001010000); - assign _zz_459_ = (decode_INSTRUCTION & (32'b00000000000100000011000001010000)); - assign _zz_460_ = (32'b00000000000000000000000001010000); - assign _zz_461_ = _zz_178_; - assign _zz_462_ = ((decode_INSTRUCTION & _zz_468_) == (32'b00000000000000000000000000000100)); - assign _zz_463_ = ((decode_INSTRUCTION & _zz_469_) == (32'b00000000000000000000000001000000)); - assign _zz_464_ = (1'b0); - assign _zz_465_ = ((_zz_470_ == _zz_471_) != (1'b0)); - assign _zz_466_ = ({_zz_472_,_zz_473_} != (2'b00)); - assign _zz_467_ = {(_zz_474_ != _zz_475_),{_zz_476_,{_zz_477_,_zz_478_}}}; - assign _zz_468_ = (32'b00000000000000000000000000011100); - assign _zz_469_ = (32'b00000000000000000000000001011000); - assign _zz_470_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_471_ = (32'b00000000000000000000000000000000); - assign _zz_472_ = ((decode_INSTRUCTION & _zz_479_) == (32'b00000000000000000000000000000100)); - assign _zz_473_ = _zz_179_; - assign _zz_474_ = {(_zz_480_ == _zz_481_),_zz_179_}; - assign _zz_475_ = (2'b00); - assign _zz_476_ = ({_zz_482_,{_zz_483_,_zz_484_}} != (4'b0000)); - assign _zz_477_ = ({_zz_485_,_zz_486_} != (2'b00)); - assign _zz_478_ = {(_zz_487_ != _zz_488_),{_zz_489_,{_zz_490_,_zz_491_}}}; - assign _zz_479_ = (32'b00000000000000000000000000010100); - assign _zz_480_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_481_ = (32'b00000000000000000000000000000100); - assign _zz_482_ = ((decode_INSTRUCTION & _zz_492_) == (32'b00000000000000000000000000000000)); - assign _zz_483_ = (_zz_493_ == _zz_494_); - assign _zz_484_ = {_zz_495_,_zz_496_}; - assign _zz_485_ = (_zz_497_ == _zz_498_); - assign _zz_486_ = (_zz_499_ == _zz_500_); - assign _zz_487_ = {_zz_501_,{_zz_502_,_zz_503_}}; - assign _zz_488_ = (3'b000); - assign _zz_489_ = (_zz_504_ != (1'b0)); - assign _zz_490_ = (_zz_505_ != _zz_506_); - assign _zz_491_ = {_zz_507_,{_zz_508_,_zz_509_}}; - assign _zz_492_ = (32'b00000000000000000000000001000100); - assign _zz_493_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); - assign _zz_494_ = (32'b00000000000000000000000000000000); - assign _zz_495_ = ((decode_INSTRUCTION & _zz_510_) == (32'b00000000000000000010000000000000)); - assign _zz_496_ = ((decode_INSTRUCTION & _zz_511_) == (32'b00000000000000000001000000000000)); - assign _zz_497_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_498_ = (32'b00000000000000000101000000010000); - assign _zz_499_ = (decode_INSTRUCTION & (32'b00000010000000000111000001100100)); - assign _zz_500_ = (32'b00000000000000000101000000100000); - assign _zz_501_ = ((decode_INSTRUCTION & _zz_512_) == (32'b01000000000000000001000000010000)); - assign _zz_502_ = (_zz_513_ == _zz_514_); - assign _zz_503_ = (_zz_515_ == _zz_516_); - assign _zz_504_ = ((decode_INSTRUCTION & _zz_517_) == (32'b00000010000000000100000000100000)); - assign _zz_505_ = {_zz_518_,_zz_519_}; - assign _zz_506_ = (2'b00); - assign _zz_507_ = (_zz_520_ != (1'b0)); - assign _zz_508_ = (_zz_521_ != _zz_522_); - assign _zz_509_ = {_zz_523_,{_zz_524_,_zz_525_}}; - assign _zz_510_ = (32'b00000000000000000110000000000100); - assign _zz_511_ = (32'b00000000000000000101000000000100); - assign _zz_512_ = (32'b01000000000000000011000001010100); - assign _zz_513_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_514_ = (32'b00000000000000000001000000010000); - assign _zz_515_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100)); - assign _zz_516_ = (32'b00000000000000000001000000010000); - assign _zz_517_ = (32'b00000010000000000100000001100100); - assign _zz_518_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000)); - assign _zz_519_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100000)); - assign _zz_520_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001001000)) == (32'b00000000000000000100000000001000)); - assign _zz_521_ = ((decode_INSTRUCTION & _zz_526_) == (32'b00000000000000000000000000100100)); - assign _zz_522_ = (1'b0); - assign _zz_523_ = ({_zz_527_,{_zz_528_,_zz_529_}} != (5'b00000)); - assign _zz_524_ = ({_zz_530_,_zz_531_} != (6'b000000)); - assign _zz_525_ = {(_zz_532_ != _zz_533_),{_zz_534_,{_zz_535_,_zz_536_}}}; - assign _zz_526_ = (32'b00000000000000000000000001100100); - assign _zz_527_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000000)) == (32'b00000000000000000000000001000000)); - assign _zz_528_ = _zz_177_; - assign _zz_529_ = {(_zz_537_ == _zz_538_),{_zz_539_,_zz_540_}}; - assign _zz_530_ = _zz_178_; - assign _zz_531_ = {(_zz_541_ == _zz_542_),{_zz_543_,{_zz_544_,_zz_545_}}}; - assign _zz_532_ = {_zz_177_,{_zz_546_,{_zz_547_,_zz_548_}}}; - assign _zz_533_ = (5'b00000); - assign _zz_534_ = ({_zz_549_,{_zz_550_,_zz_551_}} != (3'b000)); - assign _zz_535_ = (_zz_552_ != (1'b0)); - assign _zz_536_ = {(_zz_553_ != _zz_554_),{_zz_555_,{_zz_556_,_zz_557_}}}; - assign _zz_537_ = (decode_INSTRUCTION & (32'b00000000000000000100000000100000)); - assign _zz_538_ = (32'b00000000000000000100000000100000); - assign _zz_539_ = ((decode_INSTRUCTION & _zz_558_) == (32'b00000000000000000000000000010000)); - assign _zz_540_ = ((decode_INSTRUCTION & _zz_559_) == (32'b00000000000000000000000000100000)); - assign _zz_541_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); - assign _zz_542_ = (32'b00000000000000000001000000010000); - assign _zz_543_ = ((decode_INSTRUCTION & _zz_560_) == (32'b00000000000000000010000000010000)); - assign _zz_544_ = (_zz_561_ == _zz_562_); - assign _zz_545_ = {_zz_563_,_zz_564_}; - assign _zz_546_ = ((decode_INSTRUCTION & _zz_565_) == (32'b00000000000000000010000000010000)); - assign _zz_547_ = (_zz_566_ == _zz_567_); - assign _zz_548_ = {_zz_568_,_zz_569_}; - assign _zz_549_ = ((decode_INSTRUCTION & _zz_570_) == (32'b00000000000000000000000001000000)); - assign _zz_550_ = (_zz_571_ == _zz_572_); - assign _zz_551_ = (_zz_573_ == _zz_574_); - assign _zz_552_ = ((decode_INSTRUCTION & _zz_575_) == (32'b00000000000100000000000001010000)); - assign _zz_553_ = (_zz_576_ == _zz_577_); - assign _zz_554_ = (1'b0); - assign _zz_555_ = (_zz_176_ != (1'b0)); - assign _zz_556_ = (_zz_578_ != _zz_579_); - assign _zz_557_ = {_zz_580_,_zz_581_}; - assign _zz_558_ = (32'b00000000000000000000000000110000); - assign _zz_559_ = (32'b00000010000000000000000000100000); - assign _zz_560_ = (32'b00000000000000000010000000010000); - assign _zz_561_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000)); - assign _zz_562_ = (32'b00000000000000000000000000010000); - assign _zz_563_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)); - assign _zz_564_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000)); - assign _zz_565_ = (32'b00000000000000000010000000110000); - assign _zz_566_ = (decode_INSTRUCTION & (32'b00000000000000000001000000110000)); - assign _zz_567_ = (32'b00000000000000000000000000010000); - assign _zz_568_ = ((decode_INSTRUCTION & (32'b00000010000000000010000001100000)) == (32'b00000000000000000010000000100000)); - assign _zz_569_ = ((decode_INSTRUCTION & (32'b00000010000000000011000000100000)) == (32'b00000000000000000000000000100000)); - assign _zz_570_ = (32'b00000000000000000000000001000100); - assign _zz_571_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); - assign _zz_572_ = (32'b00000000000000000010000000010000); - assign _zz_573_ = (decode_INSTRUCTION & (32'b01000000000000000000000000110100)); - assign _zz_574_ = (32'b01000000000000000000000000110000); - assign _zz_575_ = (32'b00010000000100000011000001010000); - assign _zz_576_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_577_ = (32'b00000000000000000000000000100000); - assign _zz_578_ = _zz_176_; - assign _zz_579_ = (1'b0); - assign _zz_580_ = (((decode_INSTRUCTION & (32'b00000000000000000100000000010100)) == (32'b00000000000000000100000000010000)) != (1'b0)); - assign _zz_581_ = (((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)) != (1'b0)); - assign _zz_582_ = (32'b00000000000000000001000001111111); - assign _zz_583_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_584_ = (32'b00000000000000000010000001110011); - assign _zz_585_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_586_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_587_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_588_) == (32'b00000000000000000000000000000011)),{(_zz_589_ == _zz_590_),{_zz_591_,{_zz_592_,_zz_593_}}}}}}; - assign _zz_588_ = (32'b00000000000000000101000001011111); - assign _zz_589_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_590_ = (32'b00000000000000000000000001100011); - assign _zz_591_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_592_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_593_ = {((decode_INSTRUCTION & (32'b00000001111100000111000001111111)) == (32'b00000000000000000101000000001111)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_594_) == (32'b00000000000000000001000000010011)),{(_zz_595_ == _zz_596_),{_zz_597_,{_zz_598_,_zz_599_}}}}}}; - assign _zz_594_ = (32'b11111100000000000011000001111111); - assign _zz_595_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_596_ = (32'b00000000000000000101000000110011); - assign _zz_597_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_598_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_599_ = {((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)),((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011))}; - assign _zz_600_ = execute_INSTRUCTION[31]; - assign _zz_601_ = execute_INSTRUCTION[31]; - assign _zz_602_ = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_62_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_404_) begin - _zz_264_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_405_) begin - _zz_265_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_244_), - .io_cpu_prefetch_isValid(_zz_245_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_246_), - .io_cpu_fetch_isStuck(_zz_247_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_248_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_cacheMiss(IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss), - .io_cpu_fetch_error(IBusCachedPlugin_cache_io_cpu_fetch_error), - .io_cpu_fetch_mmuRefilling(IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling), - .io_cpu_fetch_mmuException(IBusCachedPlugin_cache_io_cpu_fetch_mmuException), - .io_cpu_fetch_isUser(_zz_249_), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_250_), - .io_cpu_decode_isStuck(_zz_251_), - .io_cpu_decode_pc(_zz_252_), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_fill_valid(_zz_253_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); - DataCache dataCache_1_ ( - .io_cpu_execute_isValid(_zz_254_), - .io_cpu_execute_address(_zz_255_), - .io_cpu_execute_args_wr(execute_MEMORY_WR), - .io_cpu_execute_args_data(_zz_170_), - .io_cpu_execute_args_size(execute_DBusCachedPlugin_size), - .io_cpu_memory_isValid(_zz_256_), - .io_cpu_memory_isStuck(memory_arbitration_isStuck), - .io_cpu_memory_isRemoved(memory_arbitration_removeIt), - .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), - .io_cpu_memory_address(_zz_257_), - .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), - .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), - .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), - .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_258_), - .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), - .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), - .io_cpu_writeBack_isValid(_zz_259_), - .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), - .io_cpu_writeBack_isUser(_zz_260_), - .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), - .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), - .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), - .io_cpu_writeBack_address(_zz_261_), - .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), - .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), - .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), - .io_cpu_redo(dataCache_1__io_cpu_redo), - .io_cpu_flush_valid(_zz_262_), - .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), - .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), - .io_mem_cmd_ready(_zz_263_), - .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), - .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), - .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), - .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), - .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), - .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), - .io_mem_rsp_valid(dBus_rsp_valid), - .io_mem_rsp_payload_data(dBus_rsp_payload_data), - .io_mem_rsp_payload_error(dBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); always @(*) begin - case(_zz_406_) - 3'b000 : begin - _zz_266_ = DBusCachedPlugin_redoBranch_payload; - end - 3'b001 : begin - _zz_266_ = CsrPlugin_jumpInterface_payload; - end - 3'b010 : begin - _zz_266_ = BranchPlugin_jumpInterface_payload; - end - 3'b011 : begin - _zz_266_ = IBusCachedPlugin_redoBranch_payload; - end - default : begin - _zz_266_ = IBusCachedPlugin_predictionJumpInterface_payload; - end + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; endcase end - - `ifndef SYNTHESIS always @(*) begin - case(_zz_1_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_1__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL"; - default : _zz_1__string = "?????"; + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; endcase end always @(*) begin - case(_zz_2_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_2__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL"; - default : _zz_2__string = "?????"; + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_3_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_3__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL"; - default : _zz_3__string = "?????"; + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; endcase end always @(*) begin - case(_zz_4_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL"; - default : _zz_4__string = "?????"; + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; + case(_zz_30) + `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; + default : _zz_30_string = "????"; endcase end always @(*) begin - case(_zz_5_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL"; - default : _zz_5__string = "?????"; + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_6_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL"; - default : _zz_6__string = "?????"; + case(_zz_33) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; + default : _zz_33_string = "?????????"; endcase end always @(*) begin - case(_zz_7_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL"; - default : _zz_7__string = "?????"; + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_8_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_8__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_8__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_8__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_8__string = "SRA_1 "; - default : _zz_8__string = "?????????"; + case(_zz_34) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; + default : _zz_34_string = "?????????"; endcase end always @(*) begin - case(_zz_9_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_9__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_9__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_9__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_9__string = "SRA_1 "; - default : _zz_9__string = "?????????"; + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(_zz_36) + `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; + default : _zz_36_string = "???"; endcase end always @(*) begin - case(_zz_10_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10__string = "SRA_1 "; - default : _zz_10__string = "?????????"; + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_11_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11__string = "SRA_1 "; - default : _zz_11__string = "?????????"; + case(_zz_37) + `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; + default : _zz_37_string = "????????????"; endcase end always @(*) begin - case(_zz_12_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12__string = "SRA_1 "; - default : _zz_12__string = "?????????"; + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(_zz_38) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; + default : _zz_38_string = "????????"; endcase end always @(*) begin - case(_zz_13_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 "; - default : _zz_13__string = "????????????"; + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_14_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_14__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_14__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_14__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_14__string = "URS1 "; - default : _zz_14__string = "????????????"; + case(_zz_39) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; + default : _zz_39_string = "?????"; endcase end always @(*) begin - case(_zz_15_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_15__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_15__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_15__string = "URS1 "; - default : _zz_15__string = "????????????"; + case(_zz_43) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(_zz_44) + `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; + default : _zz_44_string = "????"; endcase end always @(*) begin - case(_zz_16_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_16__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_16__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_16__string = "BITWISE "; - default : _zz_16__string = "????????"; + case(_zz_45) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; + default : _zz_45_string = "?????????"; endcase end always @(*) begin - case(_zz_17_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17__string = "BITWISE "; - default : _zz_17__string = "????????"; + case(_zz_46) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; + default : _zz_46_string = "?????"; endcase end always @(*) begin - case(_zz_18_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE "; - default : _zz_18__string = "????????"; + case(_zz_47) + `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; + default : _zz_47_string = "???"; endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(_zz_48) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; + default : _zz_48_string = "????????"; endcase end always @(*) begin - case(_zz_19_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19__string = "AND_1"; - default : _zz_19__string = "?????"; + case(_zz_49) + `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; + default : _zz_49_string = "????????????"; endcase end always @(*) begin - case(_zz_20_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20__string = "AND_1"; - default : _zz_20__string = "?????"; + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_21_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_21__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_21__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_21__string = "AND_1"; - default : _zz_21__string = "?????"; + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; endcase end always @(*) begin - case(_zz_22_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_22__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_22__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_22__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_22__string = "JALR"; - default : _zz_22__string = "????"; + case(_zz_115) + `Src1CtrlEnum_defaultEncoding_RS : _zz_115_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_115_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_115_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_115_string = "URS1 "; + default : _zz_115_string = "????????????"; endcase end always @(*) begin - case(_zz_23_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_23__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_23__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_23__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_23__string = "JALR"; - default : _zz_23__string = "????"; + case(_zz_116) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_116_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_116_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_116_string = "BITWISE "; + default : _zz_116_string = "????????"; endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(_zz_117) + `Src2CtrlEnum_defaultEncoding_RS : _zz_117_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_117_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_117_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_117_string = "PC "; + default : _zz_117_string = "???"; endcase end always @(*) begin - case(_zz_24_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_24__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_24__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_24__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_24__string = "PC "; - default : _zz_24__string = "???"; + case(_zz_118) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_118_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_118_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_118_string = "AND_1"; + default : _zz_118_string = "?????"; endcase end always @(*) begin - case(_zz_25_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_25__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_25__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_25__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_25__string = "PC "; - default : _zz_25__string = "???"; + case(_zz_119) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_119_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_119_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_119_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_119_string = "SRA_1 "; + default : _zz_119_string = "?????????"; endcase end always @(*) begin - case(_zz_26_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_26__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_26__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_26__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_26__string = "PC "; - default : _zz_26__string = "???"; + case(_zz_120) + `BranchCtrlEnum_defaultEncoding_INC : _zz_120_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_120_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_120_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_120_string = "JALR"; + default : _zz_120_string = "????"; endcase end always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; + case(_zz_121) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_121_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_121_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_121_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_121_string = "ECALL"; + default : _zz_121_string = "?????"; endcase end always @(*) begin - case(_zz_33_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33__string = "ECALL"; - default : _zz_33__string = "?????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; - default : execute_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_34_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34__string = "ECALL"; - default : _zz_34__string = "?????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; - default : writeBack_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_37_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_37__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_37__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_37__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_37__string = "ECALL"; - default : _zz_37__string = "?????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_40_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_40__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_40__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_40__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_40__string = "JALR"; - default : _zz_40__string = "????"; - endcase - end - always @(*) begin - case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_45_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45__string = "SRA_1 "; - default : _zz_45__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_47_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_47__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_47__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_47__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_47__string = "SRA_1 "; - default : _zz_47__string = "?????????"; - endcase - end - always @(*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; - default : execute_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_52_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_52__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_52__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_52__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_52__string = "PC "; - default : _zz_52__string = "???"; - endcase - end - always @(*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; - default : execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_54_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_54__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_54__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54__string = "URS1 "; - default : _zz_54__string = "????????????"; - endcase - end - always @(*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_57_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_57__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_57__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_57__string = "BITWISE "; - default : _zz_57__string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_59_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_59__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_59__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_59__string = "AND_1"; - default : _zz_59__string = "?????"; - endcase - end - always @(*) begin - case(_zz_66_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_66__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_66__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_66__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_66__string = "PC "; - default : _zz_66__string = "???"; - endcase - end - always @(*) begin - case(_zz_68_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_68__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_68__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_68__string = "AND_1"; - default : _zz_68__string = "?????"; - endcase - end - always @(*) begin - case(_zz_71_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_71__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_71__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_71__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_71__string = "ECALL"; - default : _zz_71__string = "?????"; - endcase - end - always @(*) begin - case(_zz_72_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_72__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_72__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_72__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_72__string = "JALR"; - default : _zz_72__string = "????"; - endcase - end - always @(*) begin - case(_zz_74_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_74__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_74__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_74__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_74__string = "URS1 "; - default : _zz_74__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_76_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_76__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_76__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_76__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_76__string = "SRA_1 "; - default : _zz_76__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_89_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_89__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_89__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_89__string = "BITWISE "; - default : _zz_89__string = "????????"; - endcase - end - always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_96_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_96__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_96__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_96__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_96__string = "JALR"; - default : _zz_96__string = "????"; - endcase - end - always @(*) begin - case(_zz_180_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_180__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_180__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_180__string = "BITWISE "; - default : _zz_180__string = "????????"; - endcase - end - always @(*) begin - case(_zz_181_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_181__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_181__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_181__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_181__string = "SRA_1 "; - default : _zz_181__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_182_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_182__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_182__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_182__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_182__string = "URS1 "; - default : _zz_182__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_183_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_183__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_183__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_183__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_183__string = "JALR"; - default : _zz_183__string = "????"; - endcase - end - always @(*) begin - case(_zz_184_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_184__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_184__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_184__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_184__string = "ECALL"; - default : _zz_184__string = "?????"; - endcase - end - always @(*) begin - case(_zz_185_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_185__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_185__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_185__string = "AND_1"; - default : _zz_185__string = "?????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_186_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_186__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_186__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_186__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_186__string = "PC "; - default : _zz_186__string = "???"; + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin @@ -3354,15 +2462,6 @@ module VexRiscv ( default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; @@ -3371,23 +2470,6 @@ module VexRiscv ( default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end always @(*) begin case(decode_to_execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; @@ -3406,6 +2488,15 @@ module VexRiscv ( default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end always @(*) begin case(decode_to_execute_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; @@ -3435,60 +2526,61 @@ module VexRiscv ( end `endif - assign execute_SHIFT_RIGHT = _zz_46_; - assign decode_IS_RS1_SIGNED = _zz_88_; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_86_; + assign memory_MUL_LOW = ($signed(_zz_272) + $signed(_zz_280)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_282; + assign execute_REGFILE_WRITE_DATA = _zz_123; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_205[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_284[0]; + assign decode_IS_RS1_SIGNED = _zz_285[0]; + assign decode_IS_DIV = _zz_286[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_70_; - assign decode_SRC_LESS_UNSIGNED = _zz_69_; - assign decode_SRC2_FORCE_ZERO = _zz_56_; - assign decode_IS_RS2_SIGNED = _zz_87_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_83_; - assign _zz_1_ = _zz_2_; - assign _zz_3_ = _zz_4_; - assign decode_ENV_CTRL = _zz_5_; - assign _zz_6_ = _zz_7_; + assign decode_IS_MUL = _zz_287[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_288[0]; + assign _zz_8 = _zz_9; + assign _zz_10 = _zz_11; + assign decode_SHIFT_CTRL = _zz_12; + assign _zz_13 = _zz_14; + assign decode_ALU_BITWISE_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_SRC_LESS_UNSIGNED = _zz_289[0]; + assign decode_MEMORY_MANAGMENT = _zz_290[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_291[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_292[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_293[0]; + assign decode_SRC2_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_ALU_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_SRC1_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_99_; - assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = _zz_29_; - assign _zz_8_ = _zz_9_; - assign decode_SHIFT_CTRL = _zz_10_; - assign _zz_11_ = _zz_12_; - assign decode_SRC1_CTRL = _zz_13_; - assign _zz_14_ = _zz_15_; - assign decode_ALU_CTRL = _zz_16_; - assign _zz_17_ = _zz_18_; - assign decode_CSR_READ_OPCODE = _zz_35_; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_81_; - assign memory_MUL_LOW = _zz_28_; - assign decode_DO_EBREAK = _zz_27_; - assign decode_IS_DIV = _zz_77_; - assign decode_IS_CSR = _zz_65_; - assign decode_CSR_WRITE_OPCODE = _zz_36_; - assign decode_ALU_BITWISE_CTRL = _zz_19_; - assign _zz_20_ = _zz_21_; - assign execute_MUL_HL = _zz_30_; - assign execute_REGFILE_WRITE_DATA = _zz_58_; - assign execute_MUL_LL = _zz_32_; - assign execute_MUL_LH = _zz_31_; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_92_; - assign _zz_22_ = _zz_23_; + assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_295); assign memory_PC = execute_to_memory_PC; - assign execute_BRANCH_CALC = _zz_38_; - assign decode_MEMORY_MANAGMENT = _zz_79_; - assign execute_BRANCH_DO = _zz_39_; - assign decode_SRC2_CTRL = _zz_24_; - assign _zz_25_ = _zz_26_; - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_42_; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_85_; + assign decode_IS_EBREAK = _zz_296[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -3502,22 +2594,22 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33_; - assign execute_ENV_CTRL = _zz_34_; - assign writeBack_ENV_CTRL = _zz_37_; + assign memory_ENV_CTRL = _zz_27; + assign execute_ENV_CTRL = _zz_28; + assign writeBack_ENV_CTRL = _zz_29; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_41_; + assign execute_BRANCH_COND_RESULT = _zz_140; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; - assign execute_BRANCH_CTRL = _zz_40_; - assign decode_RS2_USE = _zz_78_; - assign decode_RS1_USE = _zz_75_; + assign execute_BRANCH_CTRL = _zz_30; + assign decode_RS2_USE = _zz_297[0]; + assign decode_RS1_USE = _zz_298[0]; always @ (*) begin - _zz_43_ = execute_REGFILE_WRITE_DATA; - if(_zz_267_)begin - _zz_43_ = execute_CsrPlugin_readData; + _zz_31 = execute_REGFILE_WRITE_DATA; + if(_zz_226)begin + _zz_31 = execute_CsrPlugin_readData; end end @@ -3528,60 +2620,60 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - decode_RS2 = _zz_63_; - if(_zz_200_)begin - if((_zz_201_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_202_; + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_268_)begin - if(_zz_269_)begin - if(_zz_204_)begin - decode_RS2 = _zz_91_; + if(_zz_227)begin + if(_zz_228)begin + if(_zz_133)begin + decode_RS2 = _zz_50; end end end - if(_zz_270_)begin + if(_zz_229)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_206_)begin - decode_RS2 = _zz_44_; + if(_zz_135)begin + decode_RS2 = _zz_32; end end end - if(_zz_271_)begin + if(_zz_230)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_208_)begin - decode_RS2 = _zz_43_; + if(_zz_137)begin + decode_RS2 = _zz_31; end end end end always @ (*) begin - decode_RS1 = _zz_64_; - if(_zz_200_)begin - if((_zz_201_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_202_; + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_268_)begin - if(_zz_269_)begin - if(_zz_203_)begin - decode_RS1 = _zz_91_; + if(_zz_227)begin + if(_zz_228)begin + if(_zz_132)begin + decode_RS1 = _zz_50; end end end - if(_zz_270_)begin + if(_zz_229)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_205_)begin - decode_RS1 = _zz_44_; + if(_zz_134)begin + decode_RS1 = _zz_32; end end end - if(_zz_271_)begin + if(_zz_230)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_207_)begin - decode_RS1 = _zz_43_; + if(_zz_136)begin + decode_RS1 = _zz_31; end end end @@ -3589,72 +2681,71 @@ module VexRiscv ( assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_44_ = memory_REGFILE_WRITE_DATA; + _zz_32 = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_44_ = _zz_196_; + _zz_32 = _zz_131; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_44_ = memory_SHIFT_RIGHT; + _zz_32 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_272_)begin - _zz_44_ = memory_DivPlugin_div_result; + if(_zz_231)begin + _zz_32 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_45_; - assign execute_SHIFT_CTRL = _zz_47_; + assign memory_SHIFT_CTRL = _zz_33; + assign execute_SHIFT_CTRL = _zz_34; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_51_ = execute_PC; - assign execute_SRC2_CTRL = _zz_52_; + assign _zz_35 = execute_PC; + assign execute_SRC2_CTRL = _zz_36; assign execute_IS_RVC = decode_to_execute_IS_RVC; - assign execute_SRC1_CTRL = _zz_54_; - assign decode_SRC_USE_SUB_LESS = _zz_84_; - assign decode_SRC_ADD_ZERO = _zz_80_; - assign execute_SRC_ADD_SUB = _zz_50_; - assign execute_SRC_LESS = _zz_48_; - assign execute_ALU_CTRL = _zz_57_; - assign execute_SRC2 = _zz_53_; - assign execute_SRC1 = _zz_55_; - assign execute_ALU_BITWISE_CTRL = _zz_59_; - assign _zz_60_ = writeBack_INSTRUCTION; - assign _zz_61_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_62_ = 1'b0; + assign execute_SRC1_CTRL = _zz_37; + assign decode_SRC_USE_SUB_LESS = _zz_299[0]; + assign decode_SRC_ADD_ZERO = _zz_300[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_38; + assign execute_SRC2 = _zz_129; + assign execute_SRC1 = _zz_124; + assign execute_ALU_BITWISE_CTRL = _zz_39; + assign _zz_40 = writeBack_INSTRUCTION; + assign _zz_41 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_42 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_62_ = 1'b1; + _zz_42 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_103_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_decompressor_output_payload_rsp_inst); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_82_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_301[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_90_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_366) == 32'h00001073),{(_zz_367 == _zz_368),{_zz_369,{_zz_370,_zz_371}}}}}}} != 21'h0); always @ (*) begin - _zz_91_ = writeBack_REGFILE_WRITE_DATA; + _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_91_ = writeBack_DBusCachedPlugin_rspFormated; + _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_312_) + case(_zz_271) 2'b00 : begin - _zz_91_ = _zz_379_; + _zz_50 = _zz_338; end default : begin - _zz_91_ = _zz_380_; + _zz_50 = _zz_339; end endcase end @@ -3666,63 +2757,61 @@ module VexRiscv ( assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = _zz_49_; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_73_; - assign decode_FLUSH_ALL = _zz_67_; + assign decode_MEMORY_ENABLE = _zz_302[0]; + assign decode_FLUSH_ALL = _zz_303[0]; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_93_; - if(_zz_273_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_232)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin - _zz_93_ = _zz_94_; - if(_zz_274_)begin - _zz_93_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_233)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin - _zz_94_ = _zz_95_; - if(_zz_275_)begin - _zz_94_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_234)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_95_ = 1'b0; - if(_zz_276_)begin - _zz_95_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_235)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_96_; + assign decode_BRANCH_CTRL = _zz_51; always @ (*) begin - _zz_97_ = memory_FORMAL_PC_NEXT; + _zz_52 = memory_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin - _zz_97_ = BranchPlugin_jumpInterface_payload; + _zz_52 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_98_ = decode_FORMAL_PC_NEXT; + _zz_53 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_98_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_98_ = IBusCachedPlugin_redoBranch_payload; + _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; end end - assign decode_PC = _zz_102_; - assign decode_INSTRUCTION = _zz_101_; - assign decode_IS_RVC = _zz_100_; + assign decode_PC = IBusCachedPlugin_decodePc_pcReg; + assign decode_INSTRUCTION = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign decode_IS_RVC = IBusCachedPlugin_injector_decodeInput_payload_isRvc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -3730,18 +2819,10 @@ module VexRiscv ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_234_) - 3'b000 : begin - end - 3'b001 : begin - end + case(_zz_161) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end - 3'b011 : begin - end - 3'b100 : begin - end default : begin end endcase @@ -3749,23 +2830,20 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_197_ || _zz_198_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_277_)begin - decode_arbitration_removeIt = 1'b1; - end - if(_zz_233_)begin + if(_zz_236)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3776,28 +2854,25 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_277_)begin + if(_zz_236)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if((_zz_262_ && (! dataCache_1__io_cpu_flush_ready)))begin + if(((_zz_221 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin - execute_arbitration_haltItself = 1'b1; - end - if(_zz_278_)begin + if(_zz_237)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_267_)begin + if(_zz_226)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3806,7 +2881,10 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_279_)begin + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_238)begin execute_arbitration_haltByOther = 1'b1; end end @@ -3823,8 +2901,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_279_)begin - if(_zz_280_)begin + if(_zz_238)begin + if(_zz_239)begin execute_arbitration_flushIt = 1'b1; end end @@ -3835,17 +2913,20 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_279_)begin - if(_zz_280_)begin + if(_zz_238)begin + if(_zz_239)begin execute_arbitration_flushNext = 1'b1; end end + if(_zz_160)begin + execute_arbitration_flushNext = 1'b1; + end end always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_272_)begin - if(_zz_281_)begin + if(_zz_231)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end end @@ -3869,7 +2950,7 @@ module VexRiscv ( always @ (*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1__io_cpu_writeBack_haltIt)begin + if(dataCache_1_io_cpu_writeBack_haltIt)begin writeBack_arbitration_haltItself = 1'b1; end end @@ -3900,10 +2981,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_282_)begin + if(_zz_240)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_283_)begin + if(_zz_241)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3914,49 +2995,31 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_282_)begin + if(_zz_240)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_283_)begin + if(_zz_241)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_279_)begin - if(_zz_280_)begin + if(_zz_238)begin + if(_zz_239)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_284_)begin + if(_zz_242)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if(_zz_279_)begin - if(_zz_280_)begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - end - end - always @ (*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid)begin - IBusCachedPlugin_incomingInstruction = 1'b1; - end - if((IBusCachedPlugin_decompressor_bufferValid && (IBusCachedPlugin_decompressor_bufferData[1 : 0] != (2'b11))))begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_valid)begin IBusCachedPlugin_incomingInstruction = 1'b1; end if(IBusCachedPlugin_injector_decodeInput_valid)begin @@ -3965,29 +3028,43 @@ module VexRiscv ( end always @ (*) begin - _zz_104_ = 1'b0; + _zz_54 = 1'b0; if(DebugPlugin_godmode)begin - _zz_104_ = 1'b1; + _zz_54 = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_237)begin + CsrPlugin_inWfi = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_282_)begin + if(_zz_240)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_283_)begin + if(_zz_241)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_282_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_240)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_283_)begin - case(_zz_285_) + if(_zz_241)begin + case(_zz_243) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -4018,53 +3095,83 @@ module VexRiscv ( end end - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); - assign _zz_105_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_106_ = (_zz_105_ & (~ _zz_313_)); - assign _zz_107_ = _zz_106_[3]; - assign _zz_108_ = _zz_106_[4]; - assign _zz_109_ = (_zz_106_[1] || _zz_107_); - assign _zz_110_ = (_zz_106_[2] || _zz_107_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_266_; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_55 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_56 = (_zz_55 & (~ _zz_304)); + assign _zz_57 = _zz_56[3]; + assign _zz_58 = (_zz_56[1] || _zz_57); + assign _zz_59 = (_zz_56[2] || _zz_57); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_225; always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_315_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_306); if(IBusCachedPlugin_fetchPc_inc)begin IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; end + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_317_); + always @ (*) begin + IBusCachedPlugin_decodePc_flushed = 1'b0; + if(_zz_244)begin + IBusCachedPlugin_decodePc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_308); always @ (*) begin IBusCachedPlugin_decodePc_injectedDecode = 1'b0; - if((_zz_234_ != (3'b000)))begin + if((_zz_161 != 3'b000))begin IBusCachedPlugin_decodePc_injectedDecode = 1'b1; end end + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin @@ -4072,339 +3179,338 @@ module VexRiscv ( end end - assign _zz_111_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_111_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_111_); + assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_60); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_112_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_112_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_112_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_113_; - assign _zz_113_ = ((1'b0 && (! _zz_114_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_114_ = _zz_115_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_114_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; always @ (*) begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((IBusCachedPlugin_decompressor_bufferValid && IBusCachedPlugin_decompressor_isRvc))begin - IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + if(IBusCachedPlugin_decompressor_throw2BytesReg)begin + IBusCachedPlugin_fetchPc_redo_payload[1] = 1'b1; end + end + + assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_62; + assign _zz_62 = ((1'b0 && (! _zz_63)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_63 = _zz_64; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_63; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if(IBusCachedPlugin_injector_decodeInput_valid)begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end - assign IBusCachedPlugin_decompressor_raw = (IBusCachedPlugin_decompressor_bufferValid ? {IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[15 : 0],IBusCachedPlugin_decompressor_bufferData} : {IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[31 : 16],(IBusCachedPlugin_iBusRsp_output_payload_pc[1] ? IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[31 : 16] : IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[15 : 0])}); - assign IBusCachedPlugin_decompressor_isRvc = (IBusCachedPlugin_decompressor_raw[1 : 0] != (2'b11)); - assign _zz_116_ = IBusCachedPlugin_decompressor_raw[15 : 0]; + assign IBusCachedPlugin_decompressor_input_valid = (IBusCachedPlugin_iBusRsp_output_valid && (! IBusCachedPlugin_iBusRsp_redoFetch)); + assign IBusCachedPlugin_decompressor_input_payload_pc = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign IBusCachedPlugin_decompressor_input_payload_rsp_error = IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + assign IBusCachedPlugin_decompressor_input_payload_rsp_inst = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + assign IBusCachedPlugin_decompressor_input_payload_isRvc = IBusCachedPlugin_iBusRsp_output_payload_isRvc; + assign IBusCachedPlugin_iBusRsp_output_ready = IBusCachedPlugin_decompressor_input_ready; + assign IBusCachedPlugin_decompressor_flushNext = 1'b0; + assign IBusCachedPlugin_decompressor_consumeCurrent = 1'b0; + assign IBusCachedPlugin_decompressor_isInputLowRvc = (IBusCachedPlugin_decompressor_input_payload_rsp_inst[1 : 0] != 2'b11); + assign IBusCachedPlugin_decompressor_isInputHighRvc = (IBusCachedPlugin_decompressor_input_payload_rsp_inst[17 : 16] != 2'b11); + assign IBusCachedPlugin_decompressor_throw2Bytes = (IBusCachedPlugin_decompressor_throw2BytesReg || IBusCachedPlugin_decompressor_input_payload_pc[1]); + assign IBusCachedPlugin_decompressor_unaligned = (IBusCachedPlugin_decompressor_throw2Bytes || IBusCachedPlugin_decompressor_bufferValid); + assign IBusCachedPlugin_decompressor_raw = (IBusCachedPlugin_decompressor_bufferValid ? {IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0],IBusCachedPlugin_decompressor_bufferData} : {IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16],(IBusCachedPlugin_decompressor_throw2Bytes ? IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16] : IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0])}); + assign IBusCachedPlugin_decompressor_isRvc = (IBusCachedPlugin_decompressor_raw[1 : 0] != 2'b11); + assign _zz_65 = IBusCachedPlugin_decompressor_raw[15 : 0]; always @ (*) begin - IBusCachedPlugin_decompressor_decompressed = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - case(_zz_307_) - 5'b00000 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{{{(2'b00),_zz_116_[10 : 7]},_zz_116_[12 : 11]},_zz_116_[5]},_zz_116_[6]},(2'b00)},(5'b00010)},(3'b000)},_zz_118_},(7'b0010011)}; + IBusCachedPlugin_decompressor_decompressed = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(_zz_266) + 5'h0 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{{{{{2'b00,_zz_65[10 : 7]},_zz_65[12 : 11]},_zz_65[5]},_zz_65[6]},2'b00},5'h02},3'b000},_zz_67},7'h13}; end - 5'b00010 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_119_,_zz_117_},(3'b010)},_zz_118_},(7'b0000011)}; + 5'h02 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_68,_zz_66},3'b010},_zz_67},7'h03}; end - 5'b00110 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_119_[11 : 5],_zz_118_},_zz_117_},(3'b010)},_zz_119_[4 : 0]},(7'b0100011)}; + 5'h06 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_68[11 : 5],_zz_67},_zz_66},3'b010},_zz_68[4 : 0]},7'h23}; end - 5'b01000 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_121_,_zz_116_[11 : 7]},(3'b000)},_zz_116_[11 : 7]},(7'b0010011)}; + 5'h08 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_70,_zz_65[11 : 7]},3'b000},_zz_65[11 : 7]},7'h13}; end - 5'b01001 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_124_[20],_zz_124_[10 : 1]},_zz_124_[11]},_zz_124_[19 : 12]},_zz_136_},(7'b1101111)}; + 5'h09 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_73[20],_zz_73[10 : 1]},_zz_73[11]},_zz_73[19 : 12]},_zz_85},7'h6f}; end - 5'b01010 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_121_,(5'b00000)},(3'b000)},_zz_116_[11 : 7]},(7'b0010011)}; + 5'h0a : begin + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_70,5'h0},3'b000},_zz_65[11 : 7]},7'h13}; end - 5'b01011 : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_116_[11 : 7] == (5'b00010)) ? {{{{{{{{{_zz_128_,_zz_116_[4 : 3]},_zz_116_[5]},_zz_116_[2]},_zz_116_[6]},(4'b0000)},_zz_116_[11 : 7]},(3'b000)},_zz_116_[11 : 7]},(7'b0010011)} : {{_zz_318_[31 : 12],_zz_116_[11 : 7]},(7'b0110111)}); + 5'h0b : begin + IBusCachedPlugin_decompressor_decompressed = ((_zz_65[11 : 7] == 5'h02) ? {{{{{{{{{_zz_77,_zz_65[4 : 3]},_zz_65[5]},_zz_65[2]},_zz_65[6]},4'b0000},_zz_65[11 : 7]},3'b000},_zz_65[11 : 7]},7'h13} : {{_zz_309[31 : 12],_zz_65[11 : 7]},7'h37}); end - 5'b01100 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_116_[11 : 10] == (2'b10)) ? _zz_142_ : {{(1'b0),(_zz_407_ || _zz_408_)},(5'b00000)}),(((! _zz_116_[11]) || _zz_138_) ? _zz_116_[6 : 2] : _zz_118_)},_zz_117_},_zz_140_},_zz_117_},(_zz_138_ ? (7'b0010011) : (7'b0110011))}; + 5'h0c : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_65[11 : 10] == 2'b10) ? _zz_91 : {{1'b0,(_zz_384 || _zz_385)},5'h0}),(((! _zz_65[11]) || _zz_87) ? _zz_65[6 : 2] : _zz_67)},_zz_66},_zz_89},_zz_66},(_zz_87 ? 7'h13 : 7'h33)}; end - 5'b01101 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_131_[20],_zz_131_[10 : 1]},_zz_131_[11]},_zz_131_[19 : 12]},_zz_135_},(7'b1101111)}; + 5'h0d : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_80[20],_zz_80[10 : 1]},_zz_80[11]},_zz_80[19 : 12]},_zz_84},7'h6f}; end - 5'b01110 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_134_[12],_zz_134_[10 : 5]},_zz_135_},_zz_117_},(3'b000)},_zz_134_[4 : 1]},_zz_134_[11]},(7'b1100011)}; + 5'h0e : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_83[12],_zz_83[10 : 5]},_zz_84},_zz_66},3'b000},_zz_83[4 : 1]},_zz_83[11]},7'h63}; end - 5'b01111 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_134_[12],_zz_134_[10 : 5]},_zz_135_},_zz_117_},(3'b001)},_zz_134_[4 : 1]},_zz_134_[11]},(7'b1100011)}; + 5'h0f : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_83[12],_zz_83[10 : 5]},_zz_84},_zz_66},3'b001},_zz_83[4 : 1]},_zz_83[11]},7'h63}; end - 5'b10000 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{(7'b0000000),_zz_116_[6 : 2]},_zz_116_[11 : 7]},(3'b001)},_zz_116_[11 : 7]},(7'b0010011)}; + 5'h10 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{7'h0,_zz_65[6 : 2]},_zz_65[11 : 7]},3'b001},_zz_65[11 : 7]},7'h13}; end - 5'b10010 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{{(4'b0000),_zz_116_[3 : 2]},_zz_116_[12]},_zz_116_[6 : 4]},(2'b00)},_zz_137_},(3'b010)},_zz_116_[11 : 7]},(7'b0000011)}; + 5'h12 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{{{{4'b0000,_zz_65[3 : 2]},_zz_65[12]},_zz_65[6 : 4]},2'b00},_zz_86},3'b010},_zz_65[11 : 7]},7'h03}; end - 5'b10100 : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_116_[12 : 2] == (11'b10000000000)) ? (32'b00000000000100000000000001110011) : ((_zz_116_[6 : 2] == (5'b00000)) ? {{{{(12'b000000000000),_zz_116_[11 : 7]},(3'b000)},(_zz_116_[12] ? _zz_136_ : _zz_135_)},(7'b1100111)} : {{{{{_zz_409_,_zz_410_},(_zz_411_ ? _zz_412_ : _zz_135_)},(3'b000)},_zz_116_[11 : 7]},(7'b0110011)})); + 5'h14 : begin + IBusCachedPlugin_decompressor_decompressed = ((_zz_65[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_65[6 : 2] == 5'h0) ? {{{{12'h0,_zz_65[11 : 7]},3'b000},(_zz_65[12] ? _zz_85 : _zz_84)},7'h67} : {{{{{_zz_386,_zz_387},(_zz_388 ? _zz_389 : _zz_84)},3'b000},_zz_65[11 : 7]},7'h33})); end - 5'b10110 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_319_[11 : 5],_zz_116_[6 : 2]},_zz_137_},(3'b010)},_zz_320_[4 : 0]},(7'b0100011)}; + 5'h16 : begin + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_310[11 : 5],_zz_65[6 : 2]},_zz_86},3'b010},_zz_311[4 : 0]},7'h23}; end default : begin end endcase end - assign _zz_117_ = {(2'b01),_zz_116_[9 : 7]}; - assign _zz_118_ = {(2'b01),_zz_116_[4 : 2]}; - assign _zz_119_ = {{{{(5'b00000),_zz_116_[5]},_zz_116_[12 : 10]},_zz_116_[6]},(2'b00)}; - assign _zz_120_ = _zz_116_[12]; - always @ (*) begin - _zz_121_[11] = _zz_120_; - _zz_121_[10] = _zz_120_; - _zz_121_[9] = _zz_120_; - _zz_121_[8] = _zz_120_; - _zz_121_[7] = _zz_120_; - _zz_121_[6] = _zz_120_; - _zz_121_[5] = _zz_120_; - _zz_121_[4 : 0] = _zz_116_[6 : 2]; - end - - assign _zz_122_ = _zz_116_[12]; - always @ (*) begin - _zz_123_[9] = _zz_122_; - _zz_123_[8] = _zz_122_; - _zz_123_[7] = _zz_122_; - _zz_123_[6] = _zz_122_; - _zz_123_[5] = _zz_122_; - _zz_123_[4] = _zz_122_; - _zz_123_[3] = _zz_122_; - _zz_123_[2] = _zz_122_; - _zz_123_[1] = _zz_122_; - _zz_123_[0] = _zz_122_; - end - - assign _zz_124_ = {{{{{{{{_zz_123_,_zz_116_[8]},_zz_116_[10 : 9]},_zz_116_[6]},_zz_116_[7]},_zz_116_[2]},_zz_116_[11]},_zz_116_[5 : 3]},(1'b0)}; - assign _zz_125_ = _zz_116_[12]; - always @ (*) begin - _zz_126_[14] = _zz_125_; - _zz_126_[13] = _zz_125_; - _zz_126_[12] = _zz_125_; - _zz_126_[11] = _zz_125_; - _zz_126_[10] = _zz_125_; - _zz_126_[9] = _zz_125_; - _zz_126_[8] = _zz_125_; - _zz_126_[7] = _zz_125_; - _zz_126_[6] = _zz_125_; - _zz_126_[5] = _zz_125_; - _zz_126_[4] = _zz_125_; - _zz_126_[3] = _zz_125_; - _zz_126_[2] = _zz_125_; - _zz_126_[1] = _zz_125_; - _zz_126_[0] = _zz_125_; - end - - assign _zz_127_ = _zz_116_[12]; - always @ (*) begin - _zz_128_[2] = _zz_127_; - _zz_128_[1] = _zz_127_; - _zz_128_[0] = _zz_127_; - end - - assign _zz_129_ = _zz_116_[12]; - always @ (*) begin - _zz_130_[9] = _zz_129_; - _zz_130_[8] = _zz_129_; - _zz_130_[7] = _zz_129_; - _zz_130_[6] = _zz_129_; - _zz_130_[5] = _zz_129_; - _zz_130_[4] = _zz_129_; - _zz_130_[3] = _zz_129_; - _zz_130_[2] = _zz_129_; - _zz_130_[1] = _zz_129_; - _zz_130_[0] = _zz_129_; - end - - assign _zz_131_ = {{{{{{{{_zz_130_,_zz_116_[8]},_zz_116_[10 : 9]},_zz_116_[6]},_zz_116_[7]},_zz_116_[2]},_zz_116_[11]},_zz_116_[5 : 3]},(1'b0)}; - assign _zz_132_ = _zz_116_[12]; - always @ (*) begin - _zz_133_[4] = _zz_132_; - _zz_133_[3] = _zz_132_; - _zz_133_[2] = _zz_132_; - _zz_133_[1] = _zz_132_; - _zz_133_[0] = _zz_132_; - end - - assign _zz_134_ = {{{{{_zz_133_,_zz_116_[6 : 5]},_zz_116_[2]},_zz_116_[11 : 10]},_zz_116_[4 : 3]},(1'b0)}; - assign _zz_135_ = (5'b00000); - assign _zz_136_ = (5'b00001); - assign _zz_137_ = (5'b00010); - assign _zz_138_ = (_zz_116_[11 : 10] != (2'b11)); - always @ (*) begin - case(_zz_308_) + assign _zz_66 = {2'b01,_zz_65[9 : 7]}; + assign _zz_67 = {2'b01,_zz_65[4 : 2]}; + assign _zz_68 = {{{{5'h0,_zz_65[5]},_zz_65[12 : 10]},_zz_65[6]},2'b00}; + assign _zz_69 = _zz_65[12]; + always @ (*) begin + _zz_70[11] = _zz_69; + _zz_70[10] = _zz_69; + _zz_70[9] = _zz_69; + _zz_70[8] = _zz_69; + _zz_70[7] = _zz_69; + _zz_70[6] = _zz_69; + _zz_70[5] = _zz_69; + _zz_70[4 : 0] = _zz_65[6 : 2]; + end + + assign _zz_71 = _zz_65[12]; + always @ (*) begin + _zz_72[9] = _zz_71; + _zz_72[8] = _zz_71; + _zz_72[7] = _zz_71; + _zz_72[6] = _zz_71; + _zz_72[5] = _zz_71; + _zz_72[4] = _zz_71; + _zz_72[3] = _zz_71; + _zz_72[2] = _zz_71; + _zz_72[1] = _zz_71; + _zz_72[0] = _zz_71; + end + + assign _zz_73 = {{{{{{{{_zz_72,_zz_65[8]},_zz_65[10 : 9]},_zz_65[6]},_zz_65[7]},_zz_65[2]},_zz_65[11]},_zz_65[5 : 3]},1'b0}; + assign _zz_74 = _zz_65[12]; + always @ (*) begin + _zz_75[14] = _zz_74; + _zz_75[13] = _zz_74; + _zz_75[12] = _zz_74; + _zz_75[11] = _zz_74; + _zz_75[10] = _zz_74; + _zz_75[9] = _zz_74; + _zz_75[8] = _zz_74; + _zz_75[7] = _zz_74; + _zz_75[6] = _zz_74; + _zz_75[5] = _zz_74; + _zz_75[4] = _zz_74; + _zz_75[3] = _zz_74; + _zz_75[2] = _zz_74; + _zz_75[1] = _zz_74; + _zz_75[0] = _zz_74; + end + + assign _zz_76 = _zz_65[12]; + always @ (*) begin + _zz_77[2] = _zz_76; + _zz_77[1] = _zz_76; + _zz_77[0] = _zz_76; + end + + assign _zz_78 = _zz_65[12]; + always @ (*) begin + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7] = _zz_78; + _zz_79[6] = _zz_78; + _zz_79[5] = _zz_78; + _zz_79[4] = _zz_78; + _zz_79[3] = _zz_78; + _zz_79[2] = _zz_78; + _zz_79[1] = _zz_78; + _zz_79[0] = _zz_78; + end + + assign _zz_80 = {{{{{{{{_zz_79,_zz_65[8]},_zz_65[10 : 9]},_zz_65[6]},_zz_65[7]},_zz_65[2]},_zz_65[11]},_zz_65[5 : 3]},1'b0}; + assign _zz_81 = _zz_65[12]; + always @ (*) begin + _zz_82[4] = _zz_81; + _zz_82[3] = _zz_81; + _zz_82[2] = _zz_81; + _zz_82[1] = _zz_81; + _zz_82[0] = _zz_81; + end + + assign _zz_83 = {{{{{_zz_82,_zz_65[6 : 5]},_zz_65[2]},_zz_65[11 : 10]},_zz_65[4 : 3]},1'b0}; + assign _zz_84 = 5'h0; + assign _zz_85 = 5'h01; + assign _zz_86 = 5'h02; + assign _zz_87 = (_zz_65[11 : 10] != 2'b11); + always @ (*) begin + case(_zz_267) 2'b00 : begin - _zz_139_ = (3'b000); + _zz_88 = 3'b000; end 2'b01 : begin - _zz_139_ = (3'b100); + _zz_88 = 3'b100; end 2'b10 : begin - _zz_139_ = (3'b110); + _zz_88 = 3'b110; end default : begin - _zz_139_ = (3'b111); + _zz_88 = 3'b111; end endcase end always @ (*) begin - case(_zz_309_) + case(_zz_268) 2'b00 : begin - _zz_140_ = (3'b101); + _zz_89 = 3'b101; end 2'b01 : begin - _zz_140_ = (3'b101); + _zz_89 = 3'b101; end 2'b10 : begin - _zz_140_ = (3'b111); + _zz_89 = 3'b111; end default : begin - _zz_140_ = _zz_139_; + _zz_89 = _zz_88; end endcase end - assign _zz_141_ = _zz_116_[12]; - always @ (*) begin - _zz_142_[6] = _zz_141_; - _zz_142_[5] = _zz_141_; - _zz_142_[4] = _zz_141_; - _zz_142_[3] = _zz_141_; - _zz_142_[2] = _zz_141_; - _zz_142_[1] = _zz_141_; - _zz_142_[0] = _zz_141_; - end - - assign IBusCachedPlugin_decompressor_inputBeforeStage_valid = (IBusCachedPlugin_decompressor_isRvc ? (IBusCachedPlugin_decompressor_bufferValid || IBusCachedPlugin_iBusRsp_output_valid) : (IBusCachedPlugin_iBusRsp_output_valid && (IBusCachedPlugin_decompressor_bufferValid || (! IBusCachedPlugin_iBusRsp_output_payload_pc[1])))); - assign IBusCachedPlugin_decompressor_inputBeforeStage_payload_pc = IBusCachedPlugin_iBusRsp_output_payload_pc; - assign IBusCachedPlugin_decompressor_inputBeforeStage_payload_isRvc = IBusCachedPlugin_decompressor_isRvc; - assign IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_inst = (IBusCachedPlugin_decompressor_isRvc ? IBusCachedPlugin_decompressor_decompressed : IBusCachedPlugin_decompressor_raw); - assign IBusCachedPlugin_iBusRsp_output_ready = ((! IBusCachedPlugin_decompressor_inputBeforeStage_valid) || (! (((! IBusCachedPlugin_decompressor_inputBeforeStage_ready) || ((IBusCachedPlugin_decompressor_isRvc && (! IBusCachedPlugin_iBusRsp_output_payload_pc[1])) && (IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[17 : 16] != (2'b11)))) || (((! IBusCachedPlugin_decompressor_isRvc) && IBusCachedPlugin_decompressor_bufferValid) && (IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[17 : 16] != (2'b11)))))); - always @ (*) begin - IBusCachedPlugin_decompressor_bufferFill = 1'b0; - if(_zz_286_)begin - if(_zz_287_)begin - IBusCachedPlugin_decompressor_bufferFill = 1'b1; - end - end - end - - assign IBusCachedPlugin_decompressor_inputBeforeStage_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); - assign IBusCachedPlugin_injector_decodeInput_valid = _zz_143_; - assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_144_; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_145_; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_146_; - assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_147_; - assign _zz_103_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_inst); + assign _zz_90 = _zz_65[12]; + always @ (*) begin + _zz_91[6] = _zz_90; + _zz_91[5] = _zz_90; + _zz_91[4] = _zz_90; + _zz_91[3] = _zz_90; + _zz_91[2] = _zz_90; + _zz_91[1] = _zz_90; + _zz_91[0] = _zz_90; + end + + assign IBusCachedPlugin_decompressor_output_valid = (IBusCachedPlugin_decompressor_input_valid && (! ((IBusCachedPlugin_decompressor_throw2Bytes && (! IBusCachedPlugin_decompressor_bufferValid)) && (! IBusCachedPlugin_decompressor_isInputHighRvc)))); + assign IBusCachedPlugin_decompressor_output_payload_pc = IBusCachedPlugin_decompressor_input_payload_pc; + assign IBusCachedPlugin_decompressor_output_payload_isRvc = IBusCachedPlugin_decompressor_isRvc; + assign IBusCachedPlugin_decompressor_output_payload_rsp_inst = (IBusCachedPlugin_decompressor_isRvc ? IBusCachedPlugin_decompressor_decompressed : IBusCachedPlugin_decompressor_raw); + assign IBusCachedPlugin_decompressor_input_ready = (IBusCachedPlugin_decompressor_output_ready && (((! IBusCachedPlugin_iBusRsp_stages_1_input_valid) || IBusCachedPlugin_decompressor_flushNext) || ((! (IBusCachedPlugin_decompressor_bufferValid && IBusCachedPlugin_decompressor_isInputHighRvc)) && (! (((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && IBusCachedPlugin_decompressor_isInputHighRvc))))); + assign IBusCachedPlugin_decompressor_bufferFill = (((((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && (! IBusCachedPlugin_decompressor_isInputHighRvc)) || (IBusCachedPlugin_decompressor_bufferValid && (! IBusCachedPlugin_decompressor_isInputHighRvc))) || ((IBusCachedPlugin_decompressor_throw2Bytes && (! IBusCachedPlugin_decompressor_isRvc)) && (! IBusCachedPlugin_decompressor_isInputHighRvc))); + assign IBusCachedPlugin_decompressor_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); + assign IBusCachedPlugin_injector_decodeInput_valid = _zz_92; + assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_93; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_94; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_95; + assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_96; assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); always @ (*) begin - decode_arbitration_isValid = (IBusCachedPlugin_injector_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - case(_zz_234_) - 3'b000 : begin - end - 3'b001 : begin - end + decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; + case(_zz_161) 3'b010 : begin decode_arbitration_isValid = 1'b1; end 3'b011 : begin decode_arbitration_isValid = 1'b1; end - 3'b100 : begin - end default : begin end endcase end - assign _zz_102_ = IBusCachedPlugin_decodePc_pcReg; - assign _zz_101_ = IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; - assign _zz_100_ = IBusCachedPlugin_injector_decodeInput_payload_isRvc; - assign _zz_99_ = (decode_PC + _zz_322_); - assign _zz_148_ = _zz_323_[11]; - always @ (*) begin - _zz_149_[18] = _zz_148_; - _zz_149_[17] = _zz_148_; - _zz_149_[16] = _zz_148_; - _zz_149_[15] = _zz_148_; - _zz_149_[14] = _zz_148_; - _zz_149_[13] = _zz_148_; - _zz_149_[12] = _zz_148_; - _zz_149_[11] = _zz_148_; - _zz_149_[10] = _zz_148_; - _zz_149_[9] = _zz_148_; - _zz_149_[8] = _zz_148_; - _zz_149_[7] = _zz_148_; - _zz_149_[6] = _zz_148_; - _zz_149_[5] = _zz_148_; - _zz_149_[4] = _zz_148_; - _zz_149_[3] = _zz_148_; - _zz_149_[2] = _zz_148_; - _zz_149_[1] = _zz_148_; - _zz_149_[0] = _zz_148_; - end - - assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_324_[31])); + assign _zz_97 = _zz_312[11]; + always @ (*) begin + _zz_98[18] = _zz_97; + _zz_98[17] = _zz_97; + _zz_98[16] = _zz_97; + _zz_98[15] = _zz_97; + _zz_98[14] = _zz_97; + _zz_98[13] = _zz_97; + _zz_98[12] = _zz_97; + _zz_98[11] = _zz_97; + _zz_98[10] = _zz_97; + _zz_98[9] = _zz_97; + _zz_98[8] = _zz_97; + _zz_98[7] = _zz_97; + _zz_98[6] = _zz_97; + _zz_98[5] = _zz_97; + _zz_98[4] = _zz_97; + _zz_98[3] = _zz_97; + _zz_98[2] = _zz_97; + _zz_98[1] = _zz_97; + _zz_98[0] = _zz_97; + end + + assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_313[31])); assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_150_ = _zz_325_[19]; - always @ (*) begin - _zz_151_[10] = _zz_150_; - _zz_151_[9] = _zz_150_; - _zz_151_[8] = _zz_150_; - _zz_151_[7] = _zz_150_; - _zz_151_[6] = _zz_150_; - _zz_151_[5] = _zz_150_; - _zz_151_[4] = _zz_150_; - _zz_151_[3] = _zz_150_; - _zz_151_[2] = _zz_150_; - _zz_151_[1] = _zz_150_; - _zz_151_[0] = _zz_150_; - end - - assign _zz_152_ = _zz_326_[11]; - always @ (*) begin - _zz_153_[18] = _zz_152_; - _zz_153_[17] = _zz_152_; - _zz_153_[16] = _zz_152_; - _zz_153_[15] = _zz_152_; - _zz_153_[14] = _zz_152_; - _zz_153_[13] = _zz_152_; - _zz_153_[12] = _zz_152_; - _zz_153_[11] = _zz_152_; - _zz_153_[10] = _zz_152_; - _zz_153_[9] = _zz_152_; - _zz_153_[8] = _zz_152_; - _zz_153_[7] = _zz_152_; - _zz_153_[6] = _zz_152_; - _zz_153_[5] = _zz_152_; - _zz_153_[4] = _zz_152_; - _zz_153_[3] = _zz_152_; - _zz_153_[2] = _zz_152_; - _zz_153_[1] = _zz_152_; - _zz_153_[0] = _zz_152_; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_151_,{{{_zz_413_,_zz_414_},_zz_415_},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_153_,{{{_zz_416_,_zz_417_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_99 = _zz_314[19]; + always @ (*) begin + _zz_100[10] = _zz_99; + _zz_100[9] = _zz_99; + _zz_100[8] = _zz_99; + _zz_100[7] = _zz_99; + _zz_100[6] = _zz_99; + _zz_100[5] = _zz_99; + _zz_100[4] = _zz_99; + _zz_100[3] = _zz_99; + _zz_100[2] = _zz_99; + _zz_100[1] = _zz_99; + _zz_100[0] = _zz_99; + end + + assign _zz_101 = _zz_315[11]; + always @ (*) begin + _zz_102[18] = _zz_101; + _zz_102[17] = _zz_101; + _zz_102[16] = _zz_101; + _zz_102[15] = _zz_101; + _zz_102[14] = _zz_101; + _zz_102[13] = _zz_101; + _zz_102[12] = _zz_101; + _zz_102[11] = _zz_101; + _zz_102[10] = _zz_101; + _zz_102[9] = _zz_101; + _zz_102[8] = _zz_101; + _zz_102[7] = _zz_101; + _zz_102[6] = _zz_101; + _zz_102[5] = _zz_101; + _zz_102[4] = _zz_101; + _zz_102[3] = _zz_101; + _zz_102[2] = _zz_101; + _zz_102[1] = _zz_101; + _zz_102[0] = _zz_101; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_100,{{{_zz_390,_zz_391},_zz_392},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_102,{{{_zz_393,_zz_394},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -4413,130 +3519,126 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_245_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_248_ = (32'b00000000000000000000000000000000); - assign _zz_246_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_247_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_249_ = (CsrPlugin_privilege == (2'b00)); + assign _zz_195 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_196 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_197 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_196; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_199 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_276_)begin + if(_zz_235)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_274_)begin + if(_zz_233)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_288_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - end end always @ (*) begin - _zz_253_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); - if(_zz_274_)begin - _zz_253_ = 1'b1; - end - if(_zz_288_)begin - _zz_253_ = 1'b0; + _zz_203 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(_zz_233)begin + _zz_203 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_275_)begin + if(_zz_234)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_273_)begin + if(_zz_232)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_275_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_234)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_273_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + if(_zz_232)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = decode_PC; - assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_1_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_1_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; - assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_244_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_155_); - assign _zz_263_ = (! _zz_155_); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_155_ ? _zz_156_ : dataCache_1__io_mem_cmd_payload_wr); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_155_ ? _zz_157_ : dataCache_1__io_mem_cmd_payload_address); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_155_ ? _zz_158_ : dataCache_1__io_mem_cmd_payload_data); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_155_ ? _zz_159_ : dataCache_1__io_mem_cmd_payload_mask); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_155_ ? _zz_160_ : dataCache_1__io_mem_cmd_payload_length); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_155_ ? _zz_161_ : dataCache_1__io_mem_cmd_payload_last); - assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_162_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_163_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_164_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_165_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_166_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_167_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_168_; - assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_1_output_payload; + assign _zz_194 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_222 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_254_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_255_ = execute_SRC_ADD; + assign _zz_204 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_205 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_170_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_105 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_170_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_105 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_170_ = execute_RS2[31 : 0]; + _zz_105 = execute_RS2[31 : 0]; end endcase end - assign _zz_262_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_92_ = _zz_255_[1 : 0]; - assign _zz_256_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_257_ = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + assign _zz_221 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_206 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_207 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_206; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_207; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_258_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_104_ && (! dataCache_1__io_cpu_memory_isWrite)))begin - _zz_258_ = 1'b1; + _zz_208 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_54 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_208 = 1'b1; end end - assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; - assign _zz_259_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_260_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_261_ = writeBack_REGFILE_WRITE_DATA; + assign _zz_209 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_210 = (CsrPlugin_privilege == 2'b00); + assign _zz_211 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_289_)begin - if(dataCache_1__io_cpu_redo)begin + if(_zz_245)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end @@ -4545,17 +3647,17 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_289_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin + if(_zz_245)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_redo)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end @@ -4563,94 +3665,94 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); - if(_zz_289_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_327_}; + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_245)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_316}; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328_}; + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1__io_cpu_writeBack_mmuException)begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_317}; end end end always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; end 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; end 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; end default : begin end endcase end - assign _zz_171_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_172_[31] = _zz_171_; - _zz_172_[30] = _zz_171_; - _zz_172_[29] = _zz_171_; - _zz_172_[28] = _zz_171_; - _zz_172_[27] = _zz_171_; - _zz_172_[26] = _zz_171_; - _zz_172_[25] = _zz_171_; - _zz_172_[24] = _zz_171_; - _zz_172_[23] = _zz_171_; - _zz_172_[22] = _zz_171_; - _zz_172_[21] = _zz_171_; - _zz_172_[20] = _zz_171_; - _zz_172_[19] = _zz_171_; - _zz_172_[18] = _zz_171_; - _zz_172_[17] = _zz_171_; - _zz_172_[16] = _zz_171_; - _zz_172_[15] = _zz_171_; - _zz_172_[14] = _zz_171_; - _zz_172_[13] = _zz_171_; - _zz_172_[12] = _zz_171_; - _zz_172_[11] = _zz_171_; - _zz_172_[10] = _zz_171_; - _zz_172_[9] = _zz_171_; - _zz_172_[8] = _zz_171_; - _zz_172_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_173_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_174_[31] = _zz_173_; - _zz_174_[30] = _zz_173_; - _zz_174_[29] = _zz_173_; - _zz_174_[28] = _zz_173_; - _zz_174_[27] = _zz_173_; - _zz_174_[26] = _zz_173_; - _zz_174_[25] = _zz_173_; - _zz_174_[24] = _zz_173_; - _zz_174_[23] = _zz_173_; - _zz_174_[22] = _zz_173_; - _zz_174_[21] = _zz_173_; - _zz_174_[20] = _zz_173_; - _zz_174_[19] = _zz_173_; - _zz_174_[18] = _zz_173_; - _zz_174_[17] = _zz_173_; - _zz_174_[16] = _zz_173_; - _zz_174_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_310_) + assign _zz_106 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_107[31] = _zz_106; + _zz_107[30] = _zz_106; + _zz_107[29] = _zz_106; + _zz_107[28] = _zz_106; + _zz_107[27] = _zz_106; + _zz_107[26] = _zz_106; + _zz_107[25] = _zz_106; + _zz_107[24] = _zz_106; + _zz_107[23] = _zz_106; + _zz_107[22] = _zz_106; + _zz_107[21] = _zz_106; + _zz_107[20] = _zz_106; + _zz_107[19] = _zz_106; + _zz_107[18] = _zz_106; + _zz_107[17] = _zz_106; + _zz_107[16] = _zz_106; + _zz_107[15] = _zz_106; + _zz_107[14] = _zz_106; + _zz_107[13] = _zz_106; + _zz_107[12] = _zz_106; + _zz_107[11] = _zz_106; + _zz_107[10] = _zz_106; + _zz_107[9] = _zz_106; + _zz_107[8] = _zz_106; + _zz_107[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_108 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_109[31] = _zz_108; + _zz_109[30] = _zz_108; + _zz_109[29] = _zz_108; + _zz_109[28] = _zz_108; + _zz_109[27] = _zz_108; + _zz_109[26] = _zz_108; + _zz_109[25] = _zz_108; + _zz_109[24] = _zz_108; + _zz_109[23] = _zz_108; + _zz_109[22] = _zz_108; + _zz_109[21] = _zz_108; + _zz_109[20] = _zz_108; + _zz_109[19] = _zz_108; + _zz_109[18] = _zz_108; + _zz_109[17] = _zz_108; + _zz_109[16] = _zz_108; + _zz_109[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_269) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_172_; + writeBack_DBusCachedPlugin_rspFormated = _zz_107; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_174_; + writeBack_DBusCachedPlugin_rspFormated = _zz_109; end default : begin writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; @@ -4658,78 +3760,71 @@ module VexRiscv ( endcase end - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_176_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); - assign _zz_177_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_178_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_179_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_175_ = {({(_zz_418_ == _zz_419_),(_zz_420_ == _zz_421_)} != (2'b00)),{({_zz_177_,_zz_422_} != (2'b00)),{({_zz_423_,_zz_424_} != (2'b00)),{(_zz_425_ != _zz_426_),{_zz_427_,{_zz_428_,_zz_429_}}}}}}; - assign _zz_90_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_582_) == (32'b00000000000000000001000001110011)),{(_zz_583_ == _zz_584_),{_zz_585_,{_zz_586_,_zz_587_}}}}}}} != (21'b000000000000000000000)); - assign _zz_180_ = _zz_175_[1 : 0]; - assign _zz_89_ = _zz_180_; - assign _zz_88_ = _zz_329_[0]; - assign _zz_87_ = _zz_330_[0]; - assign _zz_86_ = _zz_331_[0]; - assign _zz_85_ = _zz_332_[0]; - assign _zz_84_ = _zz_333_[0]; - assign _zz_83_ = _zz_334_[0]; - assign _zz_82_ = _zz_335_[0]; - assign _zz_81_ = _zz_336_[0]; - assign _zz_80_ = _zz_337_[0]; - assign _zz_79_ = _zz_338_[0]; - assign _zz_78_ = _zz_339_[0]; - assign _zz_77_ = _zz_340_[0]; - assign _zz_181_ = _zz_175_[15 : 14]; - assign _zz_76_ = _zz_181_; - assign _zz_75_ = _zz_341_[0]; - assign _zz_182_ = _zz_175_[18 : 17]; - assign _zz_74_ = _zz_182_; - assign _zz_73_ = _zz_342_[0]; - assign _zz_183_ = _zz_175_[21 : 20]; - assign _zz_72_ = _zz_183_; - assign _zz_184_ = _zz_175_[23 : 22]; - assign _zz_71_ = _zz_184_; - assign _zz_70_ = _zz_343_[0]; - assign _zz_69_ = _zz_344_[0]; - assign _zz_185_ = _zz_175_[27 : 26]; - assign _zz_68_ = _zz_185_; - assign _zz_67_ = _zz_345_[0]; - assign _zz_186_ = _zz_175_[31 : 30]; - assign _zz_66_ = _zz_186_; - assign _zz_65_ = _zz_346_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign _zz_111 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_112 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_113 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_114 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_110 = {(((decode_INSTRUCTION & _zz_395) == 32'h00100050) != 1'b0),{(_zz_114 != 1'b0),{(_zz_114 != 1'b0),{(_zz_396 != _zz_397),{_zz_398,{_zz_399,_zz_400}}}}}}; + assign _zz_115 = _zz_110[2 : 1]; + assign _zz_49 = _zz_115; + assign _zz_116 = _zz_110[7 : 6]; + assign _zz_48 = _zz_116; + assign _zz_117 = _zz_110[9 : 8]; + assign _zz_47 = _zz_117; + assign _zz_118 = _zz_110[19 : 18]; + assign _zz_46 = _zz_118; + assign _zz_119 = _zz_110[22 : 21]; + assign _zz_45 = _zz_119; + assign _zz_120 = _zz_110[24 : 23]; + assign _zz_44 = _zz_120; + assign _zz_121 = _zz_110[27 : 26]; + assign _zz_43 = _zz_121; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_264_; - assign decode_RegFilePlugin_rs2Data = _zz_265_; - assign _zz_64_ = decode_RegFilePlugin_rs1Data; - assign _zz_63_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_223; + assign decode_RegFilePlugin_rs2Data = _zz_224; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_61_ && writeBack_arbitration_isFiring); - if(_zz_187_)begin + lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); + if(_zz_122)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_60_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_91_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; + if(_zz_122)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_50; + if(_zz_122)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -4747,285 +3842,278 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_188_ = execute_IntAluPlugin_bitwise; + _zz_123 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_188_ = {31'd0, _zz_347_}; + _zz_123 = {31'd0, _zz_318}; end default : begin - _zz_188_ = execute_SRC_ADD_SUB; + _zz_123 = execute_SRC_ADD_SUB; end endcase end - assign _zz_58_ = _zz_188_; - assign _zz_56_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_189_ = execute_RS1; + _zz_124 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_189_ = {29'd0, _zz_348_}; + _zz_124 = {29'd0, _zz_319}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_189_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_124 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_189_ = {27'd0, _zz_349_}; + _zz_124 = {27'd0, _zz_320}; end endcase end - assign _zz_55_ = _zz_189_; - assign _zz_190_ = _zz_350_[11]; - always @ (*) begin - _zz_191_[19] = _zz_190_; - _zz_191_[18] = _zz_190_; - _zz_191_[17] = _zz_190_; - _zz_191_[16] = _zz_190_; - _zz_191_[15] = _zz_190_; - _zz_191_[14] = _zz_190_; - _zz_191_[13] = _zz_190_; - _zz_191_[12] = _zz_190_; - _zz_191_[11] = _zz_190_; - _zz_191_[10] = _zz_190_; - _zz_191_[9] = _zz_190_; - _zz_191_[8] = _zz_190_; - _zz_191_[7] = _zz_190_; - _zz_191_[6] = _zz_190_; - _zz_191_[5] = _zz_190_; - _zz_191_[4] = _zz_190_; - _zz_191_[3] = _zz_190_; - _zz_191_[2] = _zz_190_; - _zz_191_[1] = _zz_190_; - _zz_191_[0] = _zz_190_; - end - - assign _zz_192_ = _zz_351_[11]; - always @ (*) begin - _zz_193_[19] = _zz_192_; - _zz_193_[18] = _zz_192_; - _zz_193_[17] = _zz_192_; - _zz_193_[16] = _zz_192_; - _zz_193_[15] = _zz_192_; - _zz_193_[14] = _zz_192_; - _zz_193_[13] = _zz_192_; - _zz_193_[12] = _zz_192_; - _zz_193_[11] = _zz_192_; - _zz_193_[10] = _zz_192_; - _zz_193_[9] = _zz_192_; - _zz_193_[8] = _zz_192_; - _zz_193_[7] = _zz_192_; - _zz_193_[6] = _zz_192_; - _zz_193_[5] = _zz_192_; - _zz_193_[4] = _zz_192_; - _zz_193_[3] = _zz_192_; - _zz_193_[2] = _zz_192_; - _zz_193_[1] = _zz_192_; - _zz_193_[0] = _zz_192_; + assign _zz_125 = _zz_321[11]; + always @ (*) begin + _zz_126[19] = _zz_125; + _zz_126[18] = _zz_125; + _zz_126[17] = _zz_125; + _zz_126[16] = _zz_125; + _zz_126[15] = _zz_125; + _zz_126[14] = _zz_125; + _zz_126[13] = _zz_125; + _zz_126[12] = _zz_125; + _zz_126[11] = _zz_125; + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; + end + + assign _zz_127 = _zz_322[11]; + always @ (*) begin + _zz_128[19] = _zz_127; + _zz_128[18] = _zz_127; + _zz_128[17] = _zz_127; + _zz_128[16] = _zz_127; + _zz_128[15] = _zz_127; + _zz_128[14] = _zz_127; + _zz_128[13] = _zz_127; + _zz_128[12] = _zz_127; + _zz_128[11] = _zz_127; + _zz_128[10] = _zz_127; + _zz_128[9] = _zz_127; + _zz_128[8] = _zz_127; + _zz_128[7] = _zz_127; + _zz_128[6] = _zz_127; + _zz_128[5] = _zz_127; + _zz_128[4] = _zz_127; + _zz_128[3] = _zz_127; + _zz_128[2] = _zz_127; + _zz_128[1] = _zz_127; + _zz_128[0] = _zz_127; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_194_ = execute_RS2; + _zz_129 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_194_ = {_zz_191_,execute_INSTRUCTION[31 : 20]}; + _zz_129 = {_zz_126,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_194_ = {_zz_193_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_129 = {_zz_128,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_194_ = _zz_51_; + _zz_129 = _zz_35; end endcase end - assign _zz_53_ = _zz_194_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_352_; + execute_SrcPlugin_addSub = _zz_323; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_50_ = execute_SrcPlugin_addSub; - assign _zz_49_ = execute_SrcPlugin_addSub; - assign _zz_48_ = execute_SrcPlugin_less; assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_195_[0] = execute_SRC1[31]; - _zz_195_[1] = execute_SRC1[30]; - _zz_195_[2] = execute_SRC1[29]; - _zz_195_[3] = execute_SRC1[28]; - _zz_195_[4] = execute_SRC1[27]; - _zz_195_[5] = execute_SRC1[26]; - _zz_195_[6] = execute_SRC1[25]; - _zz_195_[7] = execute_SRC1[24]; - _zz_195_[8] = execute_SRC1[23]; - _zz_195_[9] = execute_SRC1[22]; - _zz_195_[10] = execute_SRC1[21]; - _zz_195_[11] = execute_SRC1[20]; - _zz_195_[12] = execute_SRC1[19]; - _zz_195_[13] = execute_SRC1[18]; - _zz_195_[14] = execute_SRC1[17]; - _zz_195_[15] = execute_SRC1[16]; - _zz_195_[16] = execute_SRC1[15]; - _zz_195_[17] = execute_SRC1[14]; - _zz_195_[18] = execute_SRC1[13]; - _zz_195_[19] = execute_SRC1[12]; - _zz_195_[20] = execute_SRC1[11]; - _zz_195_[21] = execute_SRC1[10]; - _zz_195_[22] = execute_SRC1[9]; - _zz_195_[23] = execute_SRC1[8]; - _zz_195_[24] = execute_SRC1[7]; - _zz_195_[25] = execute_SRC1[6]; - _zz_195_[26] = execute_SRC1[5]; - _zz_195_[27] = execute_SRC1[4]; - _zz_195_[28] = execute_SRC1[3]; - _zz_195_[29] = execute_SRC1[2]; - _zz_195_[30] = execute_SRC1[1]; - _zz_195_[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_195_ : execute_SRC1); - assign _zz_46_ = _zz_360_; - always @ (*) begin - _zz_196_[0] = memory_SHIFT_RIGHT[31]; - _zz_196_[1] = memory_SHIFT_RIGHT[30]; - _zz_196_[2] = memory_SHIFT_RIGHT[29]; - _zz_196_[3] = memory_SHIFT_RIGHT[28]; - _zz_196_[4] = memory_SHIFT_RIGHT[27]; - _zz_196_[5] = memory_SHIFT_RIGHT[26]; - _zz_196_[6] = memory_SHIFT_RIGHT[25]; - _zz_196_[7] = memory_SHIFT_RIGHT[24]; - _zz_196_[8] = memory_SHIFT_RIGHT[23]; - _zz_196_[9] = memory_SHIFT_RIGHT[22]; - _zz_196_[10] = memory_SHIFT_RIGHT[21]; - _zz_196_[11] = memory_SHIFT_RIGHT[20]; - _zz_196_[12] = memory_SHIFT_RIGHT[19]; - _zz_196_[13] = memory_SHIFT_RIGHT[18]; - _zz_196_[14] = memory_SHIFT_RIGHT[17]; - _zz_196_[15] = memory_SHIFT_RIGHT[16]; - _zz_196_[16] = memory_SHIFT_RIGHT[15]; - _zz_196_[17] = memory_SHIFT_RIGHT[14]; - _zz_196_[18] = memory_SHIFT_RIGHT[13]; - _zz_196_[19] = memory_SHIFT_RIGHT[12]; - _zz_196_[20] = memory_SHIFT_RIGHT[11]; - _zz_196_[21] = memory_SHIFT_RIGHT[10]; - _zz_196_[22] = memory_SHIFT_RIGHT[9]; - _zz_196_[23] = memory_SHIFT_RIGHT[8]; - _zz_196_[24] = memory_SHIFT_RIGHT[7]; - _zz_196_[25] = memory_SHIFT_RIGHT[6]; - _zz_196_[26] = memory_SHIFT_RIGHT[5]; - _zz_196_[27] = memory_SHIFT_RIGHT[4]; - _zz_196_[28] = memory_SHIFT_RIGHT[3]; - _zz_196_[29] = memory_SHIFT_RIGHT[2]; - _zz_196_[30] = memory_SHIFT_RIGHT[1]; - _zz_196_[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_197_ = 1'b0; - if(_zz_290_)begin - if(_zz_291_)begin - if(_zz_203_)begin - _zz_197_ = 1'b1; + _zz_130[0] = execute_SRC1[31]; + _zz_130[1] = execute_SRC1[30]; + _zz_130[2] = execute_SRC1[29]; + _zz_130[3] = execute_SRC1[28]; + _zz_130[4] = execute_SRC1[27]; + _zz_130[5] = execute_SRC1[26]; + _zz_130[6] = execute_SRC1[25]; + _zz_130[7] = execute_SRC1[24]; + _zz_130[8] = execute_SRC1[23]; + _zz_130[9] = execute_SRC1[22]; + _zz_130[10] = execute_SRC1[21]; + _zz_130[11] = execute_SRC1[20]; + _zz_130[12] = execute_SRC1[19]; + _zz_130[13] = execute_SRC1[18]; + _zz_130[14] = execute_SRC1[17]; + _zz_130[15] = execute_SRC1[16]; + _zz_130[16] = execute_SRC1[15]; + _zz_130[17] = execute_SRC1[14]; + _zz_130[18] = execute_SRC1[13]; + _zz_130[19] = execute_SRC1[12]; + _zz_130[20] = execute_SRC1[11]; + _zz_130[21] = execute_SRC1[10]; + _zz_130[22] = execute_SRC1[9]; + _zz_130[23] = execute_SRC1[8]; + _zz_130[24] = execute_SRC1[7]; + _zz_130[25] = execute_SRC1[6]; + _zz_130[26] = execute_SRC1[5]; + _zz_130[27] = execute_SRC1[4]; + _zz_130[28] = execute_SRC1[3]; + _zz_130[29] = execute_SRC1[2]; + _zz_130[30] = execute_SRC1[1]; + _zz_130[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_130 : execute_SRC1); + always @ (*) begin + _zz_131[0] = memory_SHIFT_RIGHT[31]; + _zz_131[1] = memory_SHIFT_RIGHT[30]; + _zz_131[2] = memory_SHIFT_RIGHT[29]; + _zz_131[3] = memory_SHIFT_RIGHT[28]; + _zz_131[4] = memory_SHIFT_RIGHT[27]; + _zz_131[5] = memory_SHIFT_RIGHT[26]; + _zz_131[6] = memory_SHIFT_RIGHT[25]; + _zz_131[7] = memory_SHIFT_RIGHT[24]; + _zz_131[8] = memory_SHIFT_RIGHT[23]; + _zz_131[9] = memory_SHIFT_RIGHT[22]; + _zz_131[10] = memory_SHIFT_RIGHT[21]; + _zz_131[11] = memory_SHIFT_RIGHT[20]; + _zz_131[12] = memory_SHIFT_RIGHT[19]; + _zz_131[13] = memory_SHIFT_RIGHT[18]; + _zz_131[14] = memory_SHIFT_RIGHT[17]; + _zz_131[15] = memory_SHIFT_RIGHT[16]; + _zz_131[16] = memory_SHIFT_RIGHT[15]; + _zz_131[17] = memory_SHIFT_RIGHT[14]; + _zz_131[18] = memory_SHIFT_RIGHT[13]; + _zz_131[19] = memory_SHIFT_RIGHT[12]; + _zz_131[20] = memory_SHIFT_RIGHT[11]; + _zz_131[21] = memory_SHIFT_RIGHT[10]; + _zz_131[22] = memory_SHIFT_RIGHT[9]; + _zz_131[23] = memory_SHIFT_RIGHT[8]; + _zz_131[24] = memory_SHIFT_RIGHT[7]; + _zz_131[25] = memory_SHIFT_RIGHT[6]; + _zz_131[26] = memory_SHIFT_RIGHT[5]; + _zz_131[27] = memory_SHIFT_RIGHT[4]; + _zz_131[28] = memory_SHIFT_RIGHT[3]; + _zz_131[29] = memory_SHIFT_RIGHT[2]; + _zz_131[30] = memory_SHIFT_RIGHT[1]; + _zz_131[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_246)begin + if(_zz_247)begin + if(_zz_132)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_292_)begin - if(_zz_293_)begin - if(_zz_205_)begin - _zz_197_ = 1'b1; + if(_zz_248)begin + if(_zz_249)begin + if(_zz_134)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_294_)begin - if(_zz_295_)begin - if(_zz_207_)begin - _zz_197_ = 1'b1; + if(_zz_250)begin + if(_zz_251)begin + if(_zz_136)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_197_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_198_ = 1'b0; - if(_zz_290_)begin - if(_zz_291_)begin - if(_zz_204_)begin - _zz_198_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_246)begin + if(_zz_247)begin + if(_zz_133)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_292_)begin - if(_zz_293_)begin - if(_zz_206_)begin - _zz_198_ = 1'b1; + if(_zz_248)begin + if(_zz_249)begin + if(_zz_135)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_294_)begin - if(_zz_295_)begin - if(_zz_208_)begin - _zz_198_ = 1'b1; + if(_zz_250)begin + if(_zz_251)begin + if(_zz_137)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_198_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_199_ = (_zz_61_ && writeBack_arbitration_isFiring); - assign _zz_203_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_204_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_205_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_206_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_207_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_208_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_42_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_132 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_133 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_134 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_135 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_136 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_137 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_209_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_209_ == (3'b000))) begin - _zz_210_ = execute_BranchPlugin_eq; - end else if((_zz_209_ == (3'b001))) begin - _zz_210_ = (! execute_BranchPlugin_eq); - end else if((((_zz_209_ & (3'b101)) == (3'b101)))) begin - _zz_210_ = (! execute_SRC_LESS); + assign _zz_138 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_138 == 3'b000)) begin + _zz_139 = execute_BranchPlugin_eq; + end else if((_zz_138 == 3'b001)) begin + _zz_139 = (! execute_BranchPlugin_eq); + end else if((((_zz_138 & 3'b101) == 3'b101))) begin + _zz_139 = (! execute_SRC_LESS); end else begin - _zz_210_ = execute_SRC_LESS; + _zz_139 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_211_ = 1'b0; + _zz_140 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_211_ = 1'b1; + _zz_140 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_211_ = 1'b1; + _zz_140 = 1'b1; end default : begin - _zz_211_ = _zz_210_; + _zz_140 = _zz_139; end endcase end - assign _zz_41_ = _zz_211_; assign execute_BranchPlugin_missAlignedTarget = 1'b0; - assign _zz_39_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -5037,104 +4125,103 @@ module VexRiscv ( endcase end - assign _zz_212_ = _zz_362_[11]; + assign _zz_141 = _zz_330[11]; always @ (*) begin - _zz_213_[19] = _zz_212_; - _zz_213_[18] = _zz_212_; - _zz_213_[17] = _zz_212_; - _zz_213_[16] = _zz_212_; - _zz_213_[15] = _zz_212_; - _zz_213_[14] = _zz_212_; - _zz_213_[13] = _zz_212_; - _zz_213_[12] = _zz_212_; - _zz_213_[11] = _zz_212_; - _zz_213_[10] = _zz_212_; - _zz_213_[9] = _zz_212_; - _zz_213_[8] = _zz_212_; - _zz_213_[7] = _zz_212_; - _zz_213_[6] = _zz_212_; - _zz_213_[5] = _zz_212_; - _zz_213_[4] = _zz_212_; - _zz_213_[3] = _zz_212_; - _zz_213_[2] = _zz_212_; - _zz_213_[1] = _zz_212_; - _zz_213_[0] = _zz_212_; + _zz_142[19] = _zz_141; + _zz_142[18] = _zz_141; + _zz_142[17] = _zz_141; + _zz_142[16] = _zz_141; + _zz_142[15] = _zz_141; + _zz_142[14] = _zz_141; + _zz_142[13] = _zz_141; + _zz_142[12] = _zz_141; + _zz_142[11] = _zz_141; + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_213_,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_142,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_215_,{{{_zz_600_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_217_,{{{_zz_601_,_zz_602_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_144,{{{_zz_559,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_146,{{{_zz_560,_zz_561},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_365_}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_333}; end end endcase end - assign _zz_214_ = _zz_363_[19]; - always @ (*) begin - _zz_215_[10] = _zz_214_; - _zz_215_[9] = _zz_214_; - _zz_215_[8] = _zz_214_; - _zz_215_[7] = _zz_214_; - _zz_215_[6] = _zz_214_; - _zz_215_[5] = _zz_214_; - _zz_215_[4] = _zz_214_; - _zz_215_[3] = _zz_214_; - _zz_215_[2] = _zz_214_; - _zz_215_[1] = _zz_214_; - _zz_215_[0] = _zz_214_; - end - - assign _zz_216_ = _zz_364_[11]; - always @ (*) begin - _zz_217_[18] = _zz_216_; - _zz_217_[17] = _zz_216_; - _zz_217_[16] = _zz_216_; - _zz_217_[15] = _zz_216_; - _zz_217_[14] = _zz_216_; - _zz_217_[13] = _zz_216_; - _zz_217_[12] = _zz_216_; - _zz_217_[11] = _zz_216_; - _zz_217_[10] = _zz_216_; - _zz_217_[9] = _zz_216_; - _zz_217_[8] = _zz_216_; - _zz_217_[7] = _zz_216_; - _zz_217_[6] = _zz_216_; - _zz_217_[5] = _zz_216_; - _zz_217_[4] = _zz_216_; - _zz_217_[3] = _zz_216_; - _zz_217_[2] = _zz_216_; - _zz_217_[1] = _zz_216_; - _zz_217_[0] = _zz_216_; + assign _zz_143 = _zz_331[19]; + always @ (*) begin + _zz_144[10] = _zz_143; + _zz_144[9] = _zz_143; + _zz_144[8] = _zz_143; + _zz_144[7] = _zz_143; + _zz_144[6] = _zz_143; + _zz_144[5] = _zz_143; + _zz_144[4] = _zz_143; + _zz_144[3] = _zz_143; + _zz_144[2] = _zz_143; + _zz_144[1] = _zz_143; + _zz_144[0] = _zz_143; + end + + assign _zz_145 = _zz_332[11]; + always @ (*) begin + _zz_146[18] = _zz_145; + _zz_146[17] = _zz_145; + _zz_146[16] = _zz_145; + _zz_146[15] = _zz_145; + _zz_146[14] = _zz_145; + _zz_146[13] = _zz_145; + _zz_146[12] = _zz_145; + _zz_146[11] = _zz_145; + _zz_146[10] = _zz_145; + _zz_146[9] = _zz_145; + _zz_146[8] = _zz_145; + _zz_146[7] = _zz_145; + _zz_146[6] = _zz_145; + _zz_146[5] = _zz_145; + _zz_146[4] = _zz_145; + _zz_146[3] = _zz_145; + _zz_146[2] = _zz_145; + _zz_146[1] = _zz_145; + _zz_146[0] = _zz_145; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_38_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign _zz_218_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_219_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_220_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign _zz_147 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_148 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_149 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_221_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_222_ = _zz_366_[0]; + assign _zz_150 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_151 = _zz_334[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_277_)begin + if(_zz_236)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -5174,9 +4261,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -5200,7 +4288,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; @@ -5211,7 +4299,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -5222,105 +4310,102 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_36_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_35_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - always @ (*) begin - execute_CsrPlugin_inWfi = 1'b0; - if(_zz_278_)begin - execute_CsrPlugin_inWfi = 1'b1; - end - end - - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b111100010001 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111100010100 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000001 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b101100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b101110000000 : begin + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110011000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b101100000010 : begin + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000011 : begin + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b110000000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000001 : begin + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000000 : begin + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b101110000010 : begin + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110010000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_252)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -5339,26 +4424,26 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_296_)begin + if(_zz_253)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_297_)begin + if(_zz_254)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_296_)begin - CsrPlugin_selfException_payload_code = (4'b0010); + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_253)begin + CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_297_)begin + if(_zz_254)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -5366,95 +4451,24 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_230_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b111100010001 : begin - execute_CsrPlugin_readData[3 : 0] = (4'b1011); - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b101100000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0]; - end - 12'b101110000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[63 : 32]; - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b001100000101 : begin - execute_CsrPlugin_readData[31 : 2] = CsrPlugin_mtvec_base; - execute_CsrPlugin_readData[1 : 0] = CsrPlugin_mtvec_mode; - end - 12'b110011000000 : begin - execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); - execute_CsrPlugin_readData[25 : 20] = (6'b100000); - end - 12'b101100000010 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[31 : 0]; - end - 12'b111100010011 : begin - execute_CsrPlugin_readData[5 : 0] = (6'b100001); - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_231_; - end - 12'b110000000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[31 : 0]; - end - 12'b001100000001 : begin - execute_CsrPlugin_readData[31 : 30] = CsrPlugin_misa_base; - execute_CsrPlugin_readData[25 : 0] = CsrPlugin_misa_extensions; - end - 12'b001101000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; - end - 12'b111100010010 : begin - execute_CsrPlugin_readData[4 : 0] = (5'b10110); - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - end - 12'b101110000010 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_minstret[63 : 32]; - end - 12'b110010000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mcycle[63 : 32]; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_252)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_252)begin + execute_CsrPlugin_readInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_311_) + case(_zz_270) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -5465,10 +4479,10 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_MulPlugin_a = execute_SRC1; - assign execute_MulPlugin_b = execute_SRC2; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_298_) + case(_zz_255) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -5482,7 +4496,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_298_) + case(_zz_255) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -5501,16 +4515,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign _zz_32_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign _zz_31_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - assign _zz_30_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - assign _zz_28_ = ($signed(_zz_368_) + $signed(_zz_376_)); - assign writeBack_MulPlugin_result = ($signed(_zz_377_) + $signed(_zz_378_)); + assign writeBack_MulPlugin_result = ($signed(_zz_336) + $signed(_zz_337)); + assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_272_)begin - if(_zz_281_)begin + if(_zz_231)begin + if(_zz_256)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -5518,44 +4528,44 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_299_)begin + if(_zz_257)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end - assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); always @ (*) begin if(memory_DivPlugin_div_counter_willOverflow)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_382_); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_341); end if(memory_DivPlugin_div_counter_willClear)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_223_ = memory_DivPlugin_rs1[31 : 0]; - assign _zz_224_ = {memory_DivPlugin_accumulator[31 : 0],_zz_223_[31]}; - assign _zz_225_ = (_zz_224_ - _zz_383_); - assign _zz_226_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_227_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_228_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_152 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_152[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_342); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_343 : _zz_344); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_345[31:0]; + assign _zz_153 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_154 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_155 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_229_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_229_[31 : 0] = execute_RS1; + _zz_156[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_156[31 : 0] = execute_RS1; end - assign _zz_231_ = (_zz_230_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_231_ != (32'b00000000000000000000000000000000)); + assign _zz_158 = (_zz_157 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_158 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_300_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_258) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end @@ -5568,7 +4578,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_232_))begin + if((! _zz_159))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -5580,10 +4590,8 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_300_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_258) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; end @@ -5595,39 +4603,39 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign _zz_27_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_26_ = decode_SRC2_CTRL; - assign _zz_24_ = _zz_66_; - assign _zz_52_ = decode_to_execute_SRC2_CTRL; - assign _zz_23_ = decode_BRANCH_CTRL; - assign _zz_96_ = _zz_72_; - assign _zz_40_ = decode_to_execute_BRANCH_CTRL; - assign _zz_21_ = decode_ALU_BITWISE_CTRL; - assign _zz_19_ = _zz_68_; - assign _zz_59_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_18_ = decode_ALU_CTRL; - assign _zz_16_ = _zz_89_; - assign _zz_57_ = decode_to_execute_ALU_CTRL; - assign _zz_15_ = decode_SRC1_CTRL; - assign _zz_13_ = _zz_74_; - assign _zz_54_ = decode_to_execute_SRC1_CTRL; - assign _zz_12_ = decode_SHIFT_CTRL; - assign _zz_9_ = execute_SHIFT_CTRL; - assign _zz_10_ = _zz_76_; - assign _zz_47_ = decode_to_execute_SHIFT_CTRL; - assign _zz_45_ = execute_to_memory_SHIFT_CTRL; - assign _zz_7_ = decode_ENV_CTRL; - assign _zz_4_ = execute_ENV_CTRL; - assign _zz_2_ = memory_ENV_CTRL; - assign _zz_5_ = _zz_71_; - assign _zz_34_ = decode_to_execute_ENV_CTRL; - assign _zz_33_ = execute_to_memory_ENV_CTRL; - assign _zz_37_ = memory_to_writeBack_ENV_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign _zz_26 = decode_SRC1_CTRL; + assign _zz_24 = _zz_49; + assign _zz_37 = decode_to_execute_SRC1_CTRL; + assign _zz_23 = decode_ALU_CTRL; + assign _zz_21 = _zz_48; + assign _zz_38 = decode_to_execute_ALU_CTRL; + assign _zz_20 = decode_SRC2_CTRL; + assign _zz_18 = _zz_47; + assign _zz_36 = decode_to_execute_SRC2_CTRL; + assign _zz_17 = decode_ALU_BITWISE_CTRL; + assign _zz_15 = _zz_46; + assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_14 = decode_SHIFT_CTRL; + assign _zz_11 = execute_SHIFT_CTRL; + assign _zz_12 = _zz_45; + assign _zz_34 = decode_to_execute_SHIFT_CTRL; + assign _zz_33 = execute_to_memory_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_51 = _zz_44; + assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_43; + assign _zz_28 = decode_to_execute_ENV_CTRL; + assign _zz_27 = execute_to_memory_ENV_CTRL; + assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -5646,15 +4654,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_234_) - 3'b000 : begin - end - 3'b001 : begin - end - 3'b010 : begin - end - 3'b011 : begin - end + case(_zz_161) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -5663,74 +4663,247 @@ module VexRiscv ( endcase end - assign iBusWishbone_ADR = {_zz_403_,_zz_235_}; - assign iBusWishbone_CTI = ((_zz_235_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); + always @ (*) begin + _zz_162 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_162[12 : 0] = 13'h1000; + _zz_162[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_163 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_163[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_164 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_164[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_165 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_165[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_166 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_166[31 : 30] = CsrPlugin_misa_base; + _zz_166[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_167 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_167[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_167[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_167[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_168 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_168[11 : 11] = CsrPlugin_mip_MEIP; + _zz_168[7 : 7] = CsrPlugin_mip_MTIP; + _zz_168[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_169 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_169[11 : 11] = CsrPlugin_mie_MEIE; + _zz_169[7 : 7] = CsrPlugin_mie_MTIE; + _zz_169[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_170 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_170[31 : 2] = CsrPlugin_mtvec_base; + _zz_170[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_171 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_171[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_172 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_172[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_173 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_173[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_173[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_174 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_174[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_175 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_175[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_176 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_176[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_177[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_178[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_179[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_180[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_181[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_182[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_183[31 : 0] = _zz_157; + end + end + + always @ (*) begin + _zz_184 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_184[31 : 0] = _zz_158; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_162 | _zz_163) | (_zz_164 | _zz_165)) | ((_zz_562 | _zz_166) | (_zz_167 | _zz_168))) | (((_zz_169 | _zz_170) | (_zz_171 | _zz_172)) | ((_zz_173 | _zz_174) | (_zz_175 | _zz_176)))) | (((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_181 | _zz_182) | (_zz_183 | _zz_184)))); + assign iBusWishbone_ADR = {_zz_362,_zz_185}; + assign iBusWishbone_CTI = ((_zz_185 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_301_)begin + if(_zz_259)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_301_)begin + if(_zz_259)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_236_; + assign iBus_rsp_valid = _zz_186; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_242_ = (dBus_cmd_payload_length != (3'b000)); - assign _zz_238_ = dBus_cmd_valid; - assign _zz_240_ = dBus_cmd_payload_wr; - assign _zz_241_ = (_zz_237_ == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_239_ && (_zz_240_ || _zz_241_)); - assign dBusWishbone_ADR = ((_zz_242_ ? {{dBus_cmd_payload_address[31 : 5],_zz_237_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); - assign dBusWishbone_CTI = (_zz_242_ ? (_zz_241_ ? (3'b111) : (3'b010)) : (3'b000)); - assign dBusWishbone_BTE = (2'b00); - assign dBusWishbone_SEL = (_zz_240_ ? dBus_cmd_payload_mask : (4'b1111)); - assign dBusWishbone_WE = _zz_240_; + assign _zz_192 = (dBus_cmd_payload_length != 3'b000); + assign _zz_188 = dBus_cmd_valid; + assign _zz_190 = dBus_cmd_payload_wr; + assign _zz_191 = (_zz_187 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_189 && (_zz_190 || _zz_191)); + assign dBusWishbone_ADR = ((_zz_192 ? {{dBus_cmd_payload_address[31 : 5],_zz_187},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_192 ? (_zz_191 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_190 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_190; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_239_ = (_zz_238_ && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_238_; - assign dBusWishbone_STB = _zz_238_; - assign dBus_rsp_valid = _zz_243_; + assign _zz_189 = (_zz_188 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_188; + assign dBusWishbone_STB = _zz_188; + assign dBus_rsp_valid = _zz_193; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; IBusCachedPlugin_decodePc_pcReg <= externalResetVector; - _zz_115_ <= 1'b0; + _zz_64 <= 1'b0; IBusCachedPlugin_decompressor_bufferValid <= 1'b0; - _zz_143_ <= 1'b0; + IBusCachedPlugin_decompressor_throw2BytesReg <= 1'b0; + _zz_92 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_154_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_155_ <= 1'b0; - _zz_162_ <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_169_; - DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_187_ <= 1'b1; - _zz_200_ <= 1'b0; - CsrPlugin_misa_base <= (2'b01); - CsrPlugin_misa_extensions <= (26'b00000000000000000001000010); + IBusCachedPlugin_rspCounter <= _zz_103; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_104; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_122 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -5740,23 +4913,30 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_DivPlugin_div_counter_value <= (6'b000000); - _zz_230_ <= (32'b00000000000000000000000000000000); + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_157 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_234_ <= (3'b000); - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_235_ <= (3'b000); - _zz_236_ <= 1'b0; - _zz_237_ <= (3'b000); - _zz_243_ <= 1'b0; + _zz_161 <= 3'b000; + _zz_185 <= 3'b000; + _zz_186 <= 1'b0; + _zz_187 <= 3'b000; + _zz_193 <= 1'b0; end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin @@ -5765,87 +4945,83 @@ module VexRiscv ( if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end if((decode_arbitration_isFiring && (! IBusCachedPlugin_decodePc_injectedDecode)))begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_decodePc_pcPlus; end - if((IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)))begin + if(_zz_244)begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_jump_pcLoad_payload; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_115_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_64 <= 1'b0; end - if(_zz_113_)begin - _zz_115_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if(_zz_62)begin + _zz_64 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if((IBusCachedPlugin_decompressor_inputBeforeStage_valid && IBusCachedPlugin_decompressor_inputBeforeStage_ready))begin + if((IBusCachedPlugin_decompressor_output_valid && IBusCachedPlugin_decompressor_output_ready))begin + IBusCachedPlugin_decompressor_throw2BytesReg <= ((((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && IBusCachedPlugin_decompressor_isInputHighRvc) || (IBusCachedPlugin_decompressor_bufferValid && IBusCachedPlugin_decompressor_isInputHighRvc)); + end + if((IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid))begin IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end - if(_zz_286_)begin - if(_zz_287_)begin + if(_zz_260)begin + if(IBusCachedPlugin_decompressor_bufferFill)begin IBusCachedPlugin_decompressor_bufferValid <= 1'b1; - end else begin - IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end end - if(IBusCachedPlugin_fetcherflushIt)begin + if((IBusCachedPlugin_externalFlush || IBusCachedPlugin_decompressor_consumeCurrent))begin + IBusCachedPlugin_decompressor_throw2BytesReg <= 1'b0; IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end - if(IBusCachedPlugin_decompressor_inputBeforeStage_ready)begin - _zz_143_ <= IBusCachedPlugin_decompressor_inputBeforeStage_valid; + if(decode_arbitration_removeIt)begin + _zz_92 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_143_ <= 1'b0; + if(IBusCachedPlugin_decompressor_output_ready)begin + _zz_92 <= (IBusCachedPlugin_decompressor_output_valid && (! IBusCachedPlugin_externalFlush)); end if((! 1'b0))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_decodePc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_decodePc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_decodePc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_decodePc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_155_ <= 1'b0; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_302_)begin - _zz_155_ <= dataCache_1__io_mem_cmd_valid; + if(_zz_261)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_162_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end if(dBus_rsp_valid)begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_187_ <= 1'b0; - _zz_200_ <= _zz_199_; + _zz_122 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5867,20 +5043,39 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_303_)begin - if(_zz_304_)begin + if(_zz_262)begin + if(_zz_263)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_305_)begin + if(_zz_264)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_306_)begin + if(_zz_265)begin CsrPlugin_interrupt_valid <= 1'b1; end end CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_282_)begin + if(_zz_240)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5891,599 +5086,1653 @@ module VexRiscv ( end endcase end - if(_zz_283_)begin - case(_zz_285_) - 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); - CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; - CsrPlugin_mstatus_MPIE <= 1'b1; - end - default : begin - end - endcase + if(_zz_241)begin + case(_zz_243) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_149,{_zz_148,_zz_147}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_161) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_161 <= 3'b001; + end + end + 3'b001 : begin + _zz_161 <= 3'b010; + end + 3'b010 : begin + _zz_161 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_161 <= 3'b100; + end + end + 3'b100 : begin + _zz_161 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_355[0]; + CsrPlugin_mstatus_MIE <= _zz_356[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_358[0]; + CsrPlugin_mie_MTIE <= _zz_359[0]; + CsrPlugin_mie_MSIE <= _zz_360[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_259)begin + if(iBusWishbone_ACK)begin + _zz_185 <= (_zz_185 + 3'b001); + end + end + _zz_186 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_188 && _zz_189))begin + _zz_187 <= (_zz_187 + 3'b001); + if(_zz_191)begin + _zz_187 <= 3'b000; + end + end + _zz_193 <= ((_zz_188 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(_zz_260)begin + IBusCachedPlugin_decompressor_bufferData <= IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16]; + end + if(IBusCachedPlugin_decompressor_output_ready)begin + _zz_93 <= IBusCachedPlugin_decompressor_output_payload_pc; + _zz_94 <= IBusCachedPlugin_decompressor_output_payload_rsp_error; + _zz_95 <= IBusCachedPlugin_decompressor_output_payload_rsp_inst; + _zz_96 <= IBusCachedPlugin_decompressor_output_payload_isRvc; + end + if(IBusCachedPlugin_injector_decodeInput_ready)begin + IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_decompressor_raw; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(_zz_261)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_236)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_262)begin + if(_zz_263)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_264)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_265)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_240)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_231)begin + if(_zz_256)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_346[31:0]; + end + end + end + if(_zz_257)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_155 ? (~ _zz_156) : _zz_156) + _zz_352); + memory_DivPlugin_rs2 <= ((_zz_154 ? (~ execute_RS2) : execute_RS2) + _zz_354); + memory_DivPlugin_div_needRevert <= ((_zz_155 ^ (_zz_154 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_35; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RVC <= decode_IS_RVC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((_zz_161 != 3'b000))begin + _zz_95 <= IBusCachedPlugin_injectionPort_payload; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_357[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - execute_CsrPlugin_wfiWake <= ({_zz_220_,{_zz_219_,_zz_218_}} != (3'b000)); - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_44_; + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin - execute_arbitration_isValid <= 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_361[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin - execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin - memory_arbitration_isValid <= 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin - memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin - writeBack_arbitration_isValid <= 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end - if((((! IBusCachedPlugin_iBusRsp_output_ready) && (IBusCachedPlugin_decompressor_inputBeforeStage_valid && IBusCachedPlugin_decompressor_inputBeforeStage_ready)) && (! IBusCachedPlugin_fetcherflushIt)))begin - IBusCachedPlugin_fetchPc_pcReg[1] <= 1'b1; + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_50; + end + _zz_159 <= debug_bus_cmd_payload_address[2]; + if(_zz_238)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + _zz_160 <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; end - case(_zz_234_) - 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_234_ <= (3'b001); - end - end - 3'b001 : begin - _zz_234_ <= (3'b010); - end - 3'b010 : begin - _zz_234_ <= (3'b011); - end - 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_234_ <= (3'b100); - end - end - 3'b100 : begin - _zz_234_ <= (3'b000); - end - default : begin - end - endcase - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_230_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_396_[0]; - CsrPlugin_mstatus_MIE <= _zz_397_[0]; - end - end - 12'b111100010001 : begin - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - end - 12'b101100000000 : begin - end - 12'b101110000000 : begin - end - 12'b001101000100 : begin - end - 12'b001100000101 : begin - end - 12'b110011000000 : begin - end - 12'b101100000010 : begin - end - 12'b111100010011 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b110000000000 : begin - end - 12'b001100000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(debug_bus_cmd_valid)begin + case(_zz_258) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end end - end - 12'b001101000000 : begin - end - 12'b111100010010 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_399_[0]; - CsrPlugin_mie_MTIE <= _zz_400_[0]; - CsrPlugin_mie_MSIE <= _zz_401_[0]; + default : begin end - end - 12'b101110000010 : begin - end - 12'b110010000000 : begin - end - 12'b001101000010 : begin - end - default : begin - end - endcase - if(_zz_301_)begin - if(iBusWishbone_ACK)begin - _zz_235_ <= (_zz_235_ + (3'b001)); + endcase + end + if(_zz_238)begin + if(_zz_239)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; end end - _zz_236_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_238_ && _zz_239_))begin - _zz_237_ <= (_zz_237_ + (3'b001)); - if(_zz_241_)begin - _zz_237_ <= (3'b000); + if(_zz_242)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; end end - _zz_243_ <= ((_zz_238_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_160 <= (DebugPlugin_stepIt && decode_arbitration_isFiring); end end + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; always @ (posedge clk) begin - if(_zz_286_)begin - IBusCachedPlugin_decompressor_bufferData <= IBusCachedPlugin_iBusRsp_output_payload_rsp_inst[31 : 16]; - end - if(IBusCachedPlugin_decompressor_inputBeforeStage_ready)begin - _zz_144_ <= IBusCachedPlugin_decompressor_inputBeforeStage_payload_pc; - _zz_145_ <= IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_error; - _zz_146_ <= IBusCachedPlugin_decompressor_inputBeforeStage_payload_rsp_inst; - _zz_147_ <= IBusCachedPlugin_decompressor_inputBeforeStage_payload_isRvc; - end - if(IBusCachedPlugin_injector_decodeInput_ready)begin - IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_decompressor_raw; - end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin - IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; - end - if(_zz_302_)begin - _zz_156_ <= dataCache_1__io_mem_cmd_payload_wr; - _zz_157_ <= dataCache_1__io_mem_cmd_payload_address; - _zz_158_ <= dataCache_1__io_mem_cmd_payload_data; - _zz_159_ <= dataCache_1__io_mem_cmd_payload_mask; - _zz_160_ <= dataCache_1__io_mem_cmd_payload_length; - _zz_161_ <= dataCache_1__io_mem_cmd_payload_last; - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_163_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - _zz_164_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; - _zz_165_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; - _zz_166_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - _zz_167_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; - _zz_168_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; - end - if(_zz_199_)begin - _zz_201_ <= _zz_60_[11 : 7]; - _zz_202_ <= _zz_91_; - end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - end - if(_zz_277_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_222_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_222_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; - end - if(DBusCachedPlugin_exceptionBus_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; end - if(_zz_303_)begin - if(_zz_304_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - if(_zz_305_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end - if(_zz_306_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); - end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; end - if(_zz_282_)begin - case(CsrPlugin_targetPrivilege) - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - default : begin - end - endcase + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; end - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_done <= 1'b1; + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end - if(_zz_272_)begin - if(_zz_281_)begin - memory_DivPlugin_rs1[31 : 0] <= _zz_384_[31:0]; - memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_225_[32]) ? _zz_385_ : _zz_386_); - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_result <= _zz_387_[31:0]; - end - end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end - if(_zz_299_)begin - memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_DivPlugin_rs1 <= ((_zz_228_ ? (~ _zz_229_) : _zz_229_) + _zz_393_); - memory_DivPlugin_rs2 <= ((_zz_227_ ? (~ execute_RS2) : execute_RS2) + _zz_395_); - memory_DivPlugin_div_needRevert <= ((_zz_228_ ^ (_zz_227_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_25_; + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + + always @ (*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + end + + always @ (*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_51_; + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_22_; + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RVC <= decode_IS_RVC; + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LH <= execute_MUL_LH; + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LL <= execute_MUL_LL; + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_43_; + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HL <= execute_MUL_HL; + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_20_; + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + if(_zz_13)begin + stageB_loaderValid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_17_; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_14_; + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_11_; + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_8_; + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HH <= execute_MUL_HH; + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_98_; + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_97_; + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6_; + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3_; + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1_; + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_MUL <= decode_IS_MUL; + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end end - if((_zz_234_ != (3'b000)))begin - _zz_146_ <= IBusCachedPlugin_injectionPort_payload; + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b111100010001 : begin - end - 12'b111100010100 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; end - 12'b101100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; - end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; end - 12'b101110000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end end end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_398_[0]; - end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; end - 12'b110011000000 : begin + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; end - 12'b101100000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; - end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); end - 12'b111100010011 : begin + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; end - 12'b001101000011 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; - end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; end - 12'b111111000000 : begin + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_cacheMiss, + output io_cpu_fetch_error, + output io_cpu_fetch_mmuRefilling, + output io_cpu_fetch_mmuException, + input io_cpu_fetch_isUser, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_9; + reg [21:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [21:0] _zz_15; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_11 = (! lineLoader_flushCounter[7]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; end - 12'b110000000000 : begin + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid); + assign io_cpu_fetch_error = (fetchStage_hit_error || ((! io_cpu_fetch_mmuRsp_isPaging) && (io_cpu_fetch_mmuRsp_exception || (! io_cpu_fetch_mmuRsp_allowExecute)))); + assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuRsp_refilling; + assign io_cpu_fetch_mmuException = (((! io_cpu_fetch_mmuRsp_refilling) && io_cpu_fetch_mmuRsp_isPaging) && (io_cpu_fetch_mmuRsp_exception || (! io_cpu_fetch_mmuRsp_allowExecute))); + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; end - 12'b001100000001 : begin + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; end - 12'b001101000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; - end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end - 12'b111100010010 : begin + if(io_flush)begin + lineLoader_flushPending <= 1'b1; end - 12'b001100000100 : begin + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; end - 12'b101110000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; - end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; end - 12'b110010000000 : begin + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; end - 12'b001101000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_402_[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; end end - default : begin - end - endcase - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end end always @ (posedge clk) begin - DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin - DebugPlugin_firstCycle <= 1'b1; + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; end - DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_91_; + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_232_ <= debug_bus_cmd_payload_address[2]; - if(_zz_279_)begin - DebugPlugin_busReadDataReg <= execute_PC; + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_12)begin + lineLoader_flushCounter <= 8'h0; end - DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin - if(debugReset) begin - DebugPlugin_resetIt <= 1'b0; - DebugPlugin_haltIt <= 1'b0; - DebugPlugin_stepIt <= 1'b0; - DebugPlugin_godmode <= 1'b0; - DebugPlugin_haltedByBreak <= 1'b0; - _zz_233_ <= 1'b0; - end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin - DebugPlugin_godmode <= 1'b1; - end - if(debug_bus_cmd_valid)begin - case(_zz_300_) - 6'b000000 : begin - if(debug_bus_cmd_payload_wr)begin - DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin - DebugPlugin_resetIt <= 1'b1; - end - if(debug_bus_cmd_payload_data[24])begin - DebugPlugin_resetIt <= 1'b0; - end - if(debug_bus_cmd_payload_data[17])begin - DebugPlugin_haltIt <= 1'b1; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_haltIt <= 1'b0; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_haltedByBreak <= 1'b0; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_godmode <= 1'b0; - end - end - end - 6'b000001 : begin - end - default : begin - end - endcase - end - if(_zz_279_)begin - if(_zz_280_)begin - DebugPlugin_haltIt <= 1'b1; - DebugPlugin_haltedByBreak <= 1'b1; - end - end - if(_zz_284_)begin - if(decode_arbitration_isValid)begin - DebugPlugin_haltIt <= 1'b1; - end - end - _zz_233_ <= (DebugPlugin_stepIt && decode_arbitration_isFiring); - end - end endmodule - diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v index bf601db..b39bc51 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v @@ -1,8 +1,14 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:07:25 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + `define BranchCtrlEnum_defaultEncoding_type [1:0] `define BranchCtrlEnum_defaultEncoding_INC 2'b00 `define BranchCtrlEnum_defaultEncoding_B 2'b01 @@ -15,17 +21,6 @@ `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - `define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] `define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 @@ -37,11 +32,16 @@ `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 `define MmuPlugin_shared_State_defaultEncoding_type [2:0] `define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000 @@ -50,3697 +50,2676 @@ `define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011 `define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100 -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire [0:0] _zz_14_; - wire [0:0] _zz_15_; - wire [21:0] _zz_16_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [6:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_7_; - wire [9:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - reg [31:0] io_cpu_fetch_data_regNextWhen; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_hit_valid; - reg decodeStage_hit_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; - assign _zz_12_ = (! lineLoader_flushCounter[7]); - assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_14_ = _zz_7_[0 : 0]; - assign _zz_15_ = _zz_7_[1 : 1]; - assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; - end - end - always @ (posedge clk) begin - if(_zz_6_) begin - _zz_10_ <= ways_0_tags[_zz_5_]; - end - end +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_200; + wire _zz_201; + wire _zz_202; + wire _zz_203; + wire _zz_204; + wire _zz_205; + wire _zz_206; + wire _zz_207; + reg _zz_208; + reg _zz_209; + reg [31:0] _zz_210; + reg _zz_211; + reg [31:0] _zz_212; + reg [1:0] _zz_213; + reg _zz_214; + reg _zz_215; + wire _zz_216; + wire [2:0] _zz_217; + reg _zz_218; + wire [31:0] _zz_219; + reg _zz_220; + reg _zz_221; + wire _zz_222; + wire [31:0] _zz_223; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire [3:0] _zz_232; + wire _zz_233; + wire _zz_234; + reg [31:0] _zz_235; + reg [31:0] _zz_236; + reg [31:0] _zz_237; + reg _zz_238; + reg _zz_239; + reg _zz_240; + reg [9:0] _zz_241; + reg [9:0] _zz_242; + reg [9:0] _zz_243; + reg [9:0] _zz_244; + reg _zz_245; + reg _zz_246; + reg _zz_247; + reg _zz_248; + reg _zz_249; + reg _zz_250; + reg _zz_251; + reg [9:0] _zz_252; + reg [9:0] _zz_253; + reg [9:0] _zz_254; + reg [9:0] _zz_255; + reg _zz_256; + reg _zz_257; + reg _zz_258; + reg _zz_259; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire [1:0] _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire _zz_284; + wire _zz_285; + wire _zz_286; + wire _zz_287; + wire _zz_288; + wire _zz_289; + wire [1:0] _zz_290; + wire _zz_291; + wire _zz_292; + wire _zz_293; + wire _zz_294; + wire _zz_295; + wire _zz_296; + wire _zz_297; + wire _zz_298; + wire _zz_299; + wire _zz_300; + wire _zz_301; + wire _zz_302; + wire _zz_303; + wire _zz_304; + wire _zz_305; + wire _zz_306; + wire _zz_307; + wire _zz_308; + wire _zz_309; + wire _zz_310; + wire _zz_311; + wire _zz_312; + wire _zz_313; + wire _zz_314; + wire [1:0] _zz_315; + wire _zz_316; + wire [1:0] _zz_317; + wire [51:0] _zz_318; + wire [51:0] _zz_319; + wire [51:0] _zz_320; + wire [32:0] _zz_321; + wire [51:0] _zz_322; + wire [49:0] _zz_323; + wire [51:0] _zz_324; + wire [49:0] _zz_325; + wire [51:0] _zz_326; + wire [32:0] _zz_327; + wire [31:0] _zz_328; + wire [32:0] _zz_329; + wire [0:0] _zz_330; + wire [0:0] _zz_331; + wire [0:0] _zz_332; + wire [0:0] _zz_333; + wire [0:0] _zz_334; + wire [0:0] _zz_335; + wire [0:0] _zz_336; + wire [0:0] _zz_337; + wire [0:0] _zz_338; + wire [0:0] _zz_339; + wire [0:0] _zz_340; + wire [0:0] _zz_341; + wire [0:0] _zz_342; + wire [0:0] _zz_343; + wire [0:0] _zz_344; + wire [0:0] _zz_345; + wire [0:0] _zz_346; + wire [0:0] _zz_347; + wire [0:0] _zz_348; + wire [0:0] _zz_349; + wire [4:0] _zz_350; + wire [2:0] _zz_351; + wire [31:0] _zz_352; + wire [11:0] _zz_353; + wire [31:0] _zz_354; + wire [19:0] _zz_355; + wire [11:0] _zz_356; + wire [31:0] _zz_357; + wire [31:0] _zz_358; + wire [19:0] _zz_359; + wire [11:0] _zz_360; + wire [2:0] _zz_361; + wire [2:0] _zz_362; + wire [0:0] _zz_363; + wire [1:0] _zz_364; + wire [0:0] _zz_365; + wire [1:0] _zz_366; + wire [0:0] _zz_367; + wire [0:0] _zz_368; + wire [0:0] _zz_369; + wire [0:0] _zz_370; + wire [0:0] _zz_371; + wire [0:0] _zz_372; + wire [0:0] _zz_373; + wire [0:0] _zz_374; + wire [1:0] _zz_375; + wire [0:0] _zz_376; + wire [2:0] _zz_377; + wire [4:0] _zz_378; + wire [11:0] _zz_379; + wire [11:0] _zz_380; + wire [31:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire [31:0] _zz_384; + wire [31:0] _zz_385; + wire [31:0] _zz_386; + wire [31:0] _zz_387; + wire [11:0] _zz_388; + wire [19:0] _zz_389; + wire [11:0] _zz_390; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire [31:0] _zz_393; + wire [11:0] _zz_394; + wire [19:0] _zz_395; + wire [11:0] _zz_396; + wire [2:0] _zz_397; + wire [1:0] _zz_398; + wire [1:0] _zz_399; + wire [65:0] _zz_400; + wire [65:0] _zz_401; + wire [31:0] _zz_402; + wire [31:0] _zz_403; + wire [0:0] _zz_404; + wire [5:0] _zz_405; + wire [32:0] _zz_406; + wire [31:0] _zz_407; + wire [31:0] _zz_408; + wire [32:0] _zz_409; + wire [32:0] _zz_410; + wire [32:0] _zz_411; + wire [32:0] _zz_412; + wire [0:0] _zz_413; + wire [32:0] _zz_414; + wire [0:0] _zz_415; + wire [32:0] _zz_416; + wire [0:0] _zz_417; + wire [31:0] _zz_418; + wire [0:0] _zz_419; + wire [0:0] _zz_420; + wire [0:0] _zz_421; + wire [0:0] _zz_422; + wire [0:0] _zz_423; + wire [0:0] _zz_424; + wire [0:0] _zz_425; + wire [0:0] _zz_426; + wire [0:0] _zz_427; + wire [0:0] _zz_428; + wire [0:0] _zz_429; + wire [0:0] _zz_430; + wire [0:0] _zz_431; + wire [0:0] _zz_432; + wire [0:0] _zz_433; + wire [0:0] _zz_434; + wire [0:0] _zz_435; + wire [0:0] _zz_436; + wire [0:0] _zz_437; + wire [0:0] _zz_438; + wire [0:0] _zz_439; + wire [0:0] _zz_440; + wire [0:0] _zz_441; + wire [0:0] _zz_442; + wire [0:0] _zz_443; + wire [0:0] _zz_444; + wire [0:0] _zz_445; + wire [0:0] _zz_446; + wire [0:0] _zz_447; + wire [0:0] _zz_448; + wire [0:0] _zz_449; + wire [0:0] _zz_450; + wire [0:0] _zz_451; + wire [0:0] _zz_452; + wire [0:0] _zz_453; + wire [0:0] _zz_454; + wire [0:0] _zz_455; + wire [0:0] _zz_456; + wire [0:0] _zz_457; + wire [0:0] _zz_458; + wire [0:0] _zz_459; + wire [0:0] _zz_460; + wire [0:0] _zz_461; + wire [0:0] _zz_462; + wire [0:0] _zz_463; + wire [26:0] _zz_464; + wire _zz_465; + wire _zz_466; + wire [2:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire _zz_471; + wire [0:0] _zz_472; + wire [17:0] _zz_473; + wire [31:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; + wire _zz_477; + wire [0:0] _zz_478; + wire [11:0] _zz_479; + wire [31:0] _zz_480; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire _zz_483; + wire [0:0] _zz_484; + wire [5:0] _zz_485; + wire [31:0] _zz_486; + wire [31:0] _zz_487; + wire [31:0] _zz_488; + wire _zz_489; + wire _zz_490; + wire _zz_491; + wire _zz_492; + wire _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire _zz_496; + wire [0:0] _zz_497; + wire [0:0] _zz_498; + wire _zz_499; + wire [0:0] _zz_500; + wire [27:0] _zz_501; + wire [31:0] _zz_502; + wire _zz_503; + wire _zz_504; + wire [0:0] _zz_505; + wire [0:0] _zz_506; + wire [0:0] _zz_507; + wire [0:0] _zz_508; + wire _zz_509; + wire [0:0] _zz_510; + wire [23:0] _zz_511; + wire [31:0] _zz_512; + wire [31:0] _zz_513; + wire _zz_514; + wire _zz_515; + wire [0:0] _zz_516; + wire [1:0] _zz_517; + wire [0:0] _zz_518; + wire [0:0] _zz_519; + wire _zz_520; + wire [0:0] _zz_521; + wire [20:0] _zz_522; + wire [31:0] _zz_523; + wire [31:0] _zz_524; + wire [31:0] _zz_525; + wire [31:0] _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; + wire [31:0] _zz_529; + wire [31:0] _zz_530; + wire [0:0] _zz_531; + wire [0:0] _zz_532; + wire [0:0] _zz_533; + wire [0:0] _zz_534; + wire _zz_535; + wire [0:0] _zz_536; + wire [17:0] _zz_537; + wire [31:0] _zz_538; + wire [31:0] _zz_539; + wire [31:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire _zz_543; + wire [3:0] _zz_544; + wire [3:0] _zz_545; + wire _zz_546; + wire [0:0] _zz_547; + wire [14:0] _zz_548; + wire [31:0] _zz_549; + wire [31:0] _zz_550; + wire _zz_551; + wire [0:0] _zz_552; + wire [0:0] _zz_553; + wire [31:0] _zz_554; + wire [31:0] _zz_555; + wire _zz_556; + wire [5:0] _zz_557; + wire [5:0] _zz_558; + wire _zz_559; + wire [0:0] _zz_560; + wire [11:0] _zz_561; + wire [31:0] _zz_562; + wire [31:0] _zz_563; + wire [31:0] _zz_564; + wire [31:0] _zz_565; + wire _zz_566; + wire [0:0] _zz_567; + wire [2:0] _zz_568; + wire _zz_569; + wire [0:0] _zz_570; + wire [0:0] _zz_571; + wire [0:0] _zz_572; + wire [3:0] _zz_573; + wire [4:0] _zz_574; + wire [4:0] _zz_575; + wire _zz_576; + wire [0:0] _zz_577; + wire [8:0] _zz_578; + wire [31:0] _zz_579; + wire [31:0] _zz_580; + wire [31:0] _zz_581; + wire _zz_582; + wire [0:0] _zz_583; + wire [0:0] _zz_584; + wire [31:0] _zz_585; + wire [31:0] _zz_586; + wire [31:0] _zz_587; + wire [31:0] _zz_588; + wire [31:0] _zz_589; + wire [31:0] _zz_590; + wire [31:0] _zz_591; + wire _zz_592; + wire [0:0] _zz_593; + wire [1:0] _zz_594; + wire [0:0] _zz_595; + wire [2:0] _zz_596; + wire [0:0] _zz_597; + wire [5:0] _zz_598; + wire [1:0] _zz_599; + wire [1:0] _zz_600; + wire _zz_601; + wire [0:0] _zz_602; + wire [6:0] _zz_603; + wire [31:0] _zz_604; + wire [31:0] _zz_605; + wire [31:0] _zz_606; + wire [31:0] _zz_607; + wire [31:0] _zz_608; + wire [31:0] _zz_609; + wire [31:0] _zz_610; + wire [31:0] _zz_611; + wire _zz_612; + wire [31:0] _zz_613; + wire [31:0] _zz_614; + wire _zz_615; + wire [0:0] _zz_616; + wire [0:0] _zz_617; + wire _zz_618; + wire [0:0] _zz_619; + wire [3:0] _zz_620; + wire _zz_621; + wire [0:0] _zz_622; + wire [0:0] _zz_623; + wire [0:0] _zz_624; + wire [0:0] _zz_625; + wire _zz_626; + wire [0:0] _zz_627; + wire [4:0] _zz_628; + wire [31:0] _zz_629; + wire [31:0] _zz_630; + wire [31:0] _zz_631; + wire [31:0] _zz_632; + wire [31:0] _zz_633; + wire [31:0] _zz_634; + wire [31:0] _zz_635; + wire [31:0] _zz_636; + wire [31:0] _zz_637; + wire _zz_638; + wire [0:0] _zz_639; + wire [1:0] _zz_640; + wire [31:0] _zz_641; + wire [31:0] _zz_642; + wire [31:0] _zz_643; + wire [31:0] _zz_644; + wire [31:0] _zz_645; + wire _zz_646; + wire [4:0] _zz_647; + wire [4:0] _zz_648; + wire _zz_649; + wire [0:0] _zz_650; + wire [2:0] _zz_651; + wire [31:0] _zz_652; + wire [31:0] _zz_653; + wire [31:0] _zz_654; + wire _zz_655; + wire [31:0] _zz_656; + wire _zz_657; + wire [0:0] _zz_658; + wire [2:0] _zz_659; + wire [0:0] _zz_660; + wire [0:0] _zz_661; + wire [2:0] _zz_662; + wire [2:0] _zz_663; + wire _zz_664; + wire [0:0] _zz_665; + wire [0:0] _zz_666; + wire [31:0] _zz_667; + wire [31:0] _zz_668; + wire [31:0] _zz_669; + wire [31:0] _zz_670; + wire _zz_671; + wire [0:0] _zz_672; + wire [0:0] _zz_673; + wire [31:0] _zz_674; + wire [31:0] _zz_675; + wire _zz_676; + wire [0:0] _zz_677; + wire [0:0] _zz_678; + wire [0:0] _zz_679; + wire [1:0] _zz_680; + wire [1:0] _zz_681; + wire [1:0] _zz_682; + wire [0:0] _zz_683; + wire [0:0] _zz_684; + wire [31:0] _zz_685; + wire [31:0] _zz_686; + wire [31:0] _zz_687; + wire [31:0] _zz_688; + wire [31:0] _zz_689; + wire [31:0] _zz_690; + wire [31:0] _zz_691; + wire [31:0] _zz_692; + wire _zz_693; + wire _zz_694; + wire _zz_695; + wire [31:0] _zz_696; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire execute_IS_DBUS_SHARING; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire decode_SRC_LESS_UNSIGNED; + wire memory_IS_SFENCE_VMA; + wire execute_IS_SFENCE_VMA; + wire decode_IS_SFENCE_VMA; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_31; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_35; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_36; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; + wire [31:0] _zz_40; + wire _zz_41; + reg _zz_42; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_43; + wire `BranchCtrlEnum_defaultEncoding_type _zz_44; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; + wire `Src2CtrlEnum_defaultEncoding_type _zz_47; + wire `AluCtrlEnum_defaultEncoding_type _zz_48; + wire `Src1CtrlEnum_defaultEncoding_type _zz_49; + wire writeBack_IS_SFENCE_VMA; + wire writeBack_IS_DBUS_SHARING; + wire memory_IS_DBUS_SHARING; + reg [31:0] _zz_50; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_AMO; + wire execute_MEMORY_LRSC; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_AMO; + wire decode_MEMORY_LRSC; + reg _zz_51; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_52; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_53; + reg [31:0] _zz_54; + reg [31:0] _zz_55; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg IBusCachedPlugin_mmuBus_rsp_isPaging; + reg IBusCachedPlugin_mmuBus_rsp_allowRead; + reg IBusCachedPlugin_mmuBus_rsp_allowWrite; + reg IBusCachedPlugin_mmuBus_rsp_allowExecute; + reg IBusCachedPlugin_mmuBus_rsp_exception; + reg IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + reg DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg DBusCachedPlugin_mmuBus_rsp_isPaging; + reg DBusCachedPlugin_mmuBus_rsp_allowRead; + reg DBusCachedPlugin_mmuBus_rsp_allowWrite; + reg DBusCachedPlugin_mmuBus_rsp_allowExecute; + reg DBusCachedPlugin_mmuBus_rsp_exception; + reg DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg MmuPlugin_dBusAccess_cmd_valid; + reg MmuPlugin_dBusAccess_cmd_ready; + reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; + wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; + wire MmuPlugin_dBusAccess_cmd_payload_write; + wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; + wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; + wire MmuPlugin_dBusAccess_rsp_valid; + wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; + wire MmuPlugin_dBusAccess_rsp_payload_error; + wire MmuPlugin_dBusAccess_rsp_payload_redo; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + reg CsrPlugin_redoInterface_valid; + wire [31:0] CsrPlugin_redoInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire externalInterruptS; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_56; + wire [4:0] _zz_57; + wire _zz_58; + wire _zz_59; + wire _zz_60; + wire _zz_61; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_62; + wire _zz_63; + wire _zz_64; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_65; + wire _zz_66; + reg _zz_67; + wire _zz_68; + reg _zz_69; + reg [31:0] _zz_70; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_71; + reg [18:0] _zz_72; + wire _zz_73; + reg [10:0] _zz_74; + wire _zz_75; + reg [18:0] _zz_76; + reg _zz_77; + wire _zz_78; + reg [10:0] _zz_79; + wire _zz_80; + reg [18:0] _zz_81; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_82; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_83; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_84; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_85; + reg [31:0] _zz_86; + wire _zz_87; + reg [31:0] _zz_88; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + reg DBusCachedPlugin_forceDatapath; + reg MmuPlugin_status_sum; + reg MmuPlugin_status_mxr; + reg MmuPlugin_status_mprv; + reg MmuPlugin_satp_mode; + reg [8:0] MmuPlugin_satp_asid; + reg [19:0] MmuPlugin_satp_ppn; + reg MmuPlugin_ports_0_cache_0_valid; + reg MmuPlugin_ports_0_cache_0_exception; + reg MmuPlugin_ports_0_cache_0_superPage; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; + reg MmuPlugin_ports_0_cache_0_allowRead; + reg MmuPlugin_ports_0_cache_0_allowWrite; + reg MmuPlugin_ports_0_cache_0_allowExecute; + reg MmuPlugin_ports_0_cache_0_allowUser; + reg MmuPlugin_ports_0_cache_1_valid; + reg MmuPlugin_ports_0_cache_1_exception; + reg MmuPlugin_ports_0_cache_1_superPage; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; + reg MmuPlugin_ports_0_cache_1_allowRead; + reg MmuPlugin_ports_0_cache_1_allowWrite; + reg MmuPlugin_ports_0_cache_1_allowExecute; + reg MmuPlugin_ports_0_cache_1_allowUser; + reg MmuPlugin_ports_0_cache_2_valid; + reg MmuPlugin_ports_0_cache_2_exception; + reg MmuPlugin_ports_0_cache_2_superPage; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; + reg MmuPlugin_ports_0_cache_2_allowRead; + reg MmuPlugin_ports_0_cache_2_allowWrite; + reg MmuPlugin_ports_0_cache_2_allowExecute; + reg MmuPlugin_ports_0_cache_2_allowUser; + reg MmuPlugin_ports_0_cache_3_valid; + reg MmuPlugin_ports_0_cache_3_exception; + reg MmuPlugin_ports_0_cache_3_superPage; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; + reg MmuPlugin_ports_0_cache_3_allowRead; + reg MmuPlugin_ports_0_cache_3_allowWrite; + reg MmuPlugin_ports_0_cache_3_allowExecute; + reg MmuPlugin_ports_0_cache_3_allowUser; + wire MmuPlugin_ports_0_dirty; + reg MmuPlugin_ports_0_requireMmuLockupCalc; + reg [3:0] MmuPlugin_ports_0_cacheHitsCalc; + wire MmuPlugin_ports_0_cacheHit; + wire _zz_89; + wire _zz_90; + wire _zz_91; + wire [1:0] _zz_92; + wire MmuPlugin_ports_0_cacheLine_valid; + wire MmuPlugin_ports_0_cacheLine_exception; + wire MmuPlugin_ports_0_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_0_cacheLine_allowRead; + wire MmuPlugin_ports_0_cacheLine_allowWrite; + wire MmuPlugin_ports_0_cacheLine_allowExecute; + wire MmuPlugin_ports_0_cacheLine_allowUser; + reg MmuPlugin_ports_0_entryToReplace_willIncrement; + wire MmuPlugin_ports_0_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_0_entryToReplace_value; + wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_0_entryToReplace_willOverflow; + reg MmuPlugin_ports_1_cache_0_valid; + reg MmuPlugin_ports_1_cache_0_exception; + reg MmuPlugin_ports_1_cache_0_superPage; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; + reg MmuPlugin_ports_1_cache_0_allowRead; + reg MmuPlugin_ports_1_cache_0_allowWrite; + reg MmuPlugin_ports_1_cache_0_allowExecute; + reg MmuPlugin_ports_1_cache_0_allowUser; + reg MmuPlugin_ports_1_cache_1_valid; + reg MmuPlugin_ports_1_cache_1_exception; + reg MmuPlugin_ports_1_cache_1_superPage; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; + reg MmuPlugin_ports_1_cache_1_allowRead; + reg MmuPlugin_ports_1_cache_1_allowWrite; + reg MmuPlugin_ports_1_cache_1_allowExecute; + reg MmuPlugin_ports_1_cache_1_allowUser; + reg MmuPlugin_ports_1_cache_2_valid; + reg MmuPlugin_ports_1_cache_2_exception; + reg MmuPlugin_ports_1_cache_2_superPage; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; + reg MmuPlugin_ports_1_cache_2_allowRead; + reg MmuPlugin_ports_1_cache_2_allowWrite; + reg MmuPlugin_ports_1_cache_2_allowExecute; + reg MmuPlugin_ports_1_cache_2_allowUser; + reg MmuPlugin_ports_1_cache_3_valid; + reg MmuPlugin_ports_1_cache_3_exception; + reg MmuPlugin_ports_1_cache_3_superPage; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; + reg MmuPlugin_ports_1_cache_3_allowRead; + reg MmuPlugin_ports_1_cache_3_allowWrite; + reg MmuPlugin_ports_1_cache_3_allowExecute; + reg MmuPlugin_ports_1_cache_3_allowUser; + wire MmuPlugin_ports_1_dirty; + reg MmuPlugin_ports_1_requireMmuLockupCalc; + reg [3:0] MmuPlugin_ports_1_cacheHitsCalc; + wire MmuPlugin_ports_1_cacheHit; + wire _zz_93; + wire _zz_94; + wire _zz_95; + wire [1:0] _zz_96; + wire MmuPlugin_ports_1_cacheLine_valid; + wire MmuPlugin_ports_1_cacheLine_exception; + wire MmuPlugin_ports_1_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_1_cacheLine_allowRead; + wire MmuPlugin_ports_1_cacheLine_allowWrite; + wire MmuPlugin_ports_1_cacheLine_allowExecute; + wire MmuPlugin_ports_1_cacheLine_allowUser; + reg MmuPlugin_ports_1_entryToReplace_willIncrement; + wire MmuPlugin_ports_1_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_1_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_1_entryToReplace_value; + wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_1_entryToReplace_willOverflow; + reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1; + reg [9:0] MmuPlugin_shared_vpn_0; + reg [9:0] MmuPlugin_shared_vpn_1; + reg [1:0] MmuPlugin_shared_portSortedOh; + reg MmuPlugin_shared_dBusRspStaged_valid; + reg [31:0] MmuPlugin_shared_dBusRspStaged_payload_data; + reg MmuPlugin_shared_dBusRspStaged_payload_error; + reg MmuPlugin_shared_dBusRspStaged_payload_redo; + wire MmuPlugin_shared_dBusRsp_pte_V; + wire MmuPlugin_shared_dBusRsp_pte_R; + wire MmuPlugin_shared_dBusRsp_pte_W; + wire MmuPlugin_shared_dBusRsp_pte_X; + wire MmuPlugin_shared_dBusRsp_pte_U; + wire MmuPlugin_shared_dBusRsp_pte_G; + wire MmuPlugin_shared_dBusRsp_pte_A; + wire MmuPlugin_shared_dBusRsp_pte_D; + wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; + wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; + wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; + wire MmuPlugin_shared_dBusRsp_exception; + wire MmuPlugin_shared_dBusRsp_leaf; + reg MmuPlugin_shared_pteBuffer_V; + reg MmuPlugin_shared_pteBuffer_R; + reg MmuPlugin_shared_pteBuffer_W; + reg MmuPlugin_shared_pteBuffer_X; + reg MmuPlugin_shared_pteBuffer_U; + reg MmuPlugin_shared_pteBuffer_G; + reg MmuPlugin_shared_pteBuffer_A; + reg MmuPlugin_shared_pteBuffer_D; + reg [1:0] MmuPlugin_shared_pteBuffer_RSW; + reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; + reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; + reg [1:0] _zz_97; + wire [1:0] _zz_98; + reg [1:0] _zz_99; + wire [1:0] MmuPlugin_shared_refills; + wire [1:0] _zz_100; + reg [1:0] _zz_101; + wire [31:0] _zz_102; + wire [34:0] _zz_103; + wire _zz_104; + wire _zz_105; + wire _zz_106; + wire _zz_107; + wire _zz_108; + wire _zz_109; + wire `Src1CtrlEnum_defaultEncoding_type _zz_110; + wire `AluCtrlEnum_defaultEncoding_type _zz_111; + wire `Src2CtrlEnum_defaultEncoding_type _zz_112; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_113; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_114; + wire `BranchCtrlEnum_defaultEncoding_type _zz_115; + wire `EnvCtrlEnum_defaultEncoding_type _zz_116; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_117; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_118; + reg [31:0] _zz_119; + wire _zz_120; + reg [19:0] _zz_121; + wire _zz_122; + reg [19:0] _zz_123; + reg [31:0] _zz_124; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_125; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_126; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_127; + wire _zz_128; + wire _zz_129; + wire _zz_130; + wire _zz_131; + wire _zz_132; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_133; + reg _zz_134; + reg _zz_135; + wire _zz_136; + reg [19:0] _zz_137; + wire _zz_138; + reg [10:0] _zz_139; + wire _zz_140; + reg [18:0] _zz_141; + reg _zz_142; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_143; + reg [19:0] _zz_144; + wire _zz_145; + reg [10:0] _zz_146; + wire _zz_147; + reg [18:0] _zz_148; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] _zz_149; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg CsrPlugin_medeleg_IAM; + reg CsrPlugin_medeleg_IAF; + reg CsrPlugin_medeleg_II; + reg CsrPlugin_medeleg_LAM; + reg CsrPlugin_medeleg_LAF; + reg CsrPlugin_medeleg_SAM; + reg CsrPlugin_medeleg_SAF; + reg CsrPlugin_medeleg_EU; + reg CsrPlugin_medeleg_ES; + reg CsrPlugin_medeleg_IPF; + reg CsrPlugin_medeleg_LPF; + reg CsrPlugin_medeleg_SPF; + reg CsrPlugin_mideleg_ST; + reg CsrPlugin_mideleg_SE; + reg CsrPlugin_mideleg_SS; + reg CsrPlugin_sstatus_SIE; + reg CsrPlugin_sstatus_SPIE; + reg [0:0] CsrPlugin_sstatus_SPP; + reg CsrPlugin_sip_SEIP_SOFT; + reg CsrPlugin_sip_SEIP_INPUT; + wire CsrPlugin_sip_SEIP_OR; + reg CsrPlugin_sip_STIP; + reg CsrPlugin_sip_SSIP; + reg CsrPlugin_sie_SEIE; + reg CsrPlugin_sie_STIE; + reg CsrPlugin_sie_SSIE; + reg [1:0] CsrPlugin_stvec_mode; + reg [29:0] CsrPlugin_stvec_base; + reg [31:0] CsrPlugin_sscratch; + reg CsrPlugin_scause_interrupt; + reg [3:0] CsrPlugin_scause_exceptionCode; + reg [31:0] CsrPlugin_stval; + reg [31:0] CsrPlugin_sepc; + reg [21:0] CsrPlugin_satp_PPN; + reg [8:0] CsrPlugin_satp_ASID; + reg [0:0] CsrPlugin_satp_MODE; + wire _zz_150; + wire _zz_151; + wire _zz_152; + wire _zz_153; + wire _zz_154; + wire _zz_155; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_156; + wire _zz_157; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + reg [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_158; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_159; + wire _zz_160; + wire _zz_161; + reg [32:0] _zz_162; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_163; + wire [31:0] _zz_164; + reg [31:0] _zz_165; + wire [31:0] _zz_166; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_LRSC; + reg decode_to_execute_MEMORY_AMO; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_IS_SFENCE_VMA; + reg execute_to_memory_IS_SFENCE_VMA; + reg memory_to_writeBack_IS_SFENCE_VMA; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_IS_DBUS_SHARING; + reg memory_to_writeBack_IS_DBUS_SHARING; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_256; + reg execute_CsrPlugin_csr_384; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_770; + reg execute_CsrPlugin_csr_771; + reg execute_CsrPlugin_csr_324; + reg execute_CsrPlugin_csr_260; + reg execute_CsrPlugin_csr_261; + reg execute_CsrPlugin_csr_321; + reg execute_CsrPlugin_csr_320; + reg execute_CsrPlugin_csr_322; + reg execute_CsrPlugin_csr_323; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg execute_CsrPlugin_csr_2496; + reg execute_CsrPlugin_csr_3520; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [2:0] _zz_191; + reg _zz_192; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + reg _zz_199; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [23:0] _zz_20_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [63:0] _zz_23_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; + reg [95:0] _zz_26_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_27_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_29_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_30_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_33_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_34_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_36_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_37_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_39_string; + reg [39:0] _zz_43_string; + reg [31:0] _zz_44_string; + reg [71:0] _zz_45_string; + reg [39:0] _zz_46_string; + reg [23:0] _zz_47_string; + reg [63:0] _zz_48_string; + reg [95:0] _zz_49_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_52_string; + reg [47:0] MmuPlugin_shared_state_1_string; + reg [95:0] _zz_110_string; + reg [63:0] _zz_111_string; + reg [23:0] _zz_112_string; + reg [39:0] _zz_113_string; + reg [71:0] _zz_114_string; + reg [31:0] _zz_115_string; + reg [39:0] _zz_116_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif - always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_260 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_261 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_262 = 1'b1; + assign _zz_263 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_264 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_265 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_266 = ((_zz_205 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_267 = ((_zz_205 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_268 = ((_zz_205 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_269 = ((_zz_205 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_270 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_271 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_272 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_273 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_274 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_275 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign _zz_276 = (! dataCache_1_io_cpu_execute_refilling); + assign _zz_277 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_278 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign _zz_279 = MmuPlugin_shared_portSortedOh[0]; + assign _zz_280 = MmuPlugin_shared_portSortedOh[1]; + assign _zz_281 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_282 = (1'b0 || (! 1'b1)); + assign _zz_283 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_284 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_285 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_286 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_287 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_288 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_289 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_290 = execute_INSTRUCTION[13 : 12]; + assign _zz_291 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_292 = (! memory_arbitration_isStuck); + assign _zz_293 = (iBus_cmd_valid || (_zz_191 != 3'b000)); + assign _zz_294 = (_zz_234 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_295 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_296 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign _zz_297 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign _zz_298 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign _zz_299 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign _zz_300 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign _zz_301 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign _zz_302 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign _zz_303 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign _zz_304 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign _zz_305 = ((_zz_150 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign _zz_306 = ((_zz_151 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign _zz_307 = ((_zz_152 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign _zz_308 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_309 = ((_zz_150 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign _zz_310 = ((_zz_151 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign _zz_311 = ((_zz_152 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign _zz_312 = ((_zz_153 && 1'b1) && (! 1'b0)); + assign _zz_313 = ((_zz_154 && 1'b1) && (! 1'b0)); + assign _zz_314 = ((_zz_155 && 1'b1) && (! 1'b0)); + assign _zz_315 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_316 = execute_INSTRUCTION[13]; + assign _zz_317 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_318 = ($signed(_zz_319) + $signed(_zz_324)); + assign _zz_319 = ($signed(_zz_320) + $signed(_zz_322)); + assign _zz_320 = 52'h0; + assign _zz_321 = {1'b0,memory_MUL_LL}; + assign _zz_322 = {{19{_zz_321[32]}}, _zz_321}; + assign _zz_323 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_324 = {{2{_zz_323[49]}}, _zz_323}; + assign _zz_325 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_326 = {{2{_zz_325[49]}}, _zz_325}; + assign _zz_327 = ($signed(_zz_329) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_328 = _zz_327[31 : 0]; + assign _zz_329 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_330 = _zz_103[34 : 34]; + assign _zz_331 = _zz_103[33 : 33]; + assign _zz_332 = _zz_103[32 : 32]; + assign _zz_333 = _zz_103[31 : 31]; + assign _zz_334 = _zz_103[28 : 28]; + assign _zz_335 = _zz_103[21 : 21]; + assign _zz_336 = _zz_103[20 : 20]; + assign _zz_337 = _zz_103[19 : 19]; + assign _zz_338 = _zz_103[13 : 13]; + assign _zz_339 = _zz_103[12 : 12]; + assign _zz_340 = _zz_103[11 : 11]; + assign _zz_341 = _zz_103[17 : 17]; + assign _zz_342 = _zz_103[5 : 5]; + assign _zz_343 = _zz_103[3 : 3]; + assign _zz_344 = _zz_103[18 : 18]; + assign _zz_345 = _zz_103[10 : 10]; + assign _zz_346 = _zz_103[16 : 16]; + assign _zz_347 = _zz_103[15 : 15]; + assign _zz_348 = _zz_103[4 : 4]; + assign _zz_349 = _zz_103[0 : 0]; + assign _zz_350 = (_zz_56 - 5'h01); + assign _zz_351 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_352 = {29'd0, _zz_351}; + assign _zz_353 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_354 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_355 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_356 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_357 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_358 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_359 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_360 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_361 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_362 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_363 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_364 = {1'd0, _zz_363}; + assign _zz_365 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_366 = {1'd0, _zz_365}; + assign _zz_367 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; + assign _zz_368 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; + assign _zz_369 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; + assign _zz_370 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; + assign _zz_371 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; + assign _zz_372 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; + assign _zz_373 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; + assign _zz_374 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; + assign _zz_375 = (_zz_99 - 2'b01); + assign _zz_376 = execute_SRC_LESS; + assign _zz_377 = 3'b100; + assign _zz_378 = execute_INSTRUCTION[19 : 15]; + assign _zz_379 = execute_INSTRUCTION[31 : 20]; + assign _zz_380 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_381 = ($signed(_zz_382) + $signed(_zz_385)); + assign _zz_382 = ($signed(_zz_383) + $signed(_zz_384)); + assign _zz_383 = execute_SRC1; + assign _zz_384 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_385 = (execute_SRC_USE_SUB_LESS ? _zz_386 : _zz_387); + assign _zz_386 = 32'h00000001; + assign _zz_387 = 32'h0; + assign _zz_388 = execute_INSTRUCTION[31 : 20]; + assign _zz_389 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_390 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_391 = {_zz_137,execute_INSTRUCTION[31 : 20]}; + assign _zz_392 = {{_zz_139,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_393 = {{_zz_141,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_394 = execute_INSTRUCTION[31 : 20]; + assign _zz_395 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_396 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_397 = 3'b100; + assign _zz_398 = (_zz_156 & (~ _zz_399)); + assign _zz_399 = (_zz_156 - 2'b01); + assign _zz_400 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_401 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_402 = writeBack_MUL_LOW[31 : 0]; + assign _zz_403 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_404 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_405 = {5'd0, _zz_404}; + assign _zz_406 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_407 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_408 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_409 = {_zz_158,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_410 = _zz_411; + assign _zz_411 = _zz_412; + assign _zz_412 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_159) : _zz_159)} + _zz_414); + assign _zz_413 = memory_DivPlugin_div_needRevert; + assign _zz_414 = {32'd0, _zz_413}; + assign _zz_415 = _zz_161; + assign _zz_416 = {32'd0, _zz_415}; + assign _zz_417 = _zz_160; + assign _zz_418 = {31'd0, _zz_417}; + assign _zz_419 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_420 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_421 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_422 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_423 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_424 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_425 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_426 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_427 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_428 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_429 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_430 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_431 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_432 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_433 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_434 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_435 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_436 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_437 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_438 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_439 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_440 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_441 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_442 = execute_CsrPlugin_writeData[0 : 0]; + assign _zz_443 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_444 = execute_CsrPlugin_writeData[2 : 2]; + assign _zz_445 = execute_CsrPlugin_writeData[4 : 4]; + assign _zz_446 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_447 = execute_CsrPlugin_writeData[6 : 6]; + assign _zz_448 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_449 = execute_CsrPlugin_writeData[8 : 8]; + assign _zz_450 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_451 = execute_CsrPlugin_writeData[12 : 12]; + assign _zz_452 = execute_CsrPlugin_writeData[13 : 13]; + assign _zz_453 = execute_CsrPlugin_writeData[15 : 15]; + assign _zz_454 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_455 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_456 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_457 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_458 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_459 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_460 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_461 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_462 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_463 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_464 = (iBus_cmd_payload_address >>> 5); + assign _zz_465 = 1'b1; + assign _zz_466 = 1'b1; + assign _zz_467 = {_zz_59,{_zz_61,_zz_60}}; + assign _zz_468 = 32'h0000107f; + assign _zz_469 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_470 = 32'h00002073; + assign _zz_471 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_472 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_473 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_474) == 32'h00000003),{(_zz_475 == _zz_476),{_zz_477,{_zz_478,_zz_479}}}}}}; + assign _zz_474 = 32'h0000505f; + assign _zz_475 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_476 = 32'h00000063; + assign _zz_477 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_478 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_479 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_480) == 32'h0000500f),{(_zz_481 == _zz_482),{_zz_483,{_zz_484,_zz_485}}}}}}; + assign _zz_480 = 32'h01f0707f; + assign _zz_481 = (decode_INSTRUCTION & 32'hbc00707f); + assign _zz_482 = 32'h00005013; + assign _zz_483 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); + assign _zz_484 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_485 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_486) == 32'h12000073),{(_zz_487 == _zz_488),{_zz_489,_zz_490}}}}}; + assign _zz_486 = 32'hfe007fff; + assign _zz_487 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_488 = 32'h10200073; + assign _zz_489 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_490 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_491 = decode_INSTRUCTION[31]; + assign _zz_492 = decode_INSTRUCTION[31]; + assign _zz_493 = decode_INSTRUCTION[7]; + assign _zz_494 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_495 = 32'h02004020; + assign _zz_496 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_497 = ((decode_INSTRUCTION & 32'h02203050) == 32'h00000050); + assign _zz_498 = 1'b0; + assign _zz_499 = (((decode_INSTRUCTION & _zz_502) == 32'h00000050) != 1'b0); + assign _zz_500 = ({_zz_503,_zz_504} != 2'b00); + assign _zz_501 = {({_zz_505,_zz_506} != 2'b00),{(_zz_507 != _zz_508),{_zz_509,{_zz_510,_zz_511}}}}; + assign _zz_502 = 32'h02403050; + assign _zz_503 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_504 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_505 = _zz_105; + assign _zz_506 = ((decode_INSTRUCTION & _zz_512) == 32'h00000004); + assign _zz_507 = ((decode_INSTRUCTION & _zz_513) == 32'h00000040); + assign _zz_508 = 1'b0; + assign _zz_509 = ({_zz_514,_zz_515} != 2'b00); + assign _zz_510 = ({_zz_516,_zz_517} != 3'b000); + assign _zz_511 = {(_zz_518 != _zz_519),{_zz_520,{_zz_521,_zz_522}}}; + assign _zz_512 = 32'h0000001c; + assign _zz_513 = 32'h00000058; + assign _zz_514 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_515 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_516 = ((decode_INSTRUCTION & _zz_523) == 32'h40001010); + assign _zz_517 = {(_zz_524 == _zz_525),(_zz_526 == _zz_527)}; + assign _zz_518 = ((decode_INSTRUCTION & _zz_528) == 32'h00001000); + assign _zz_519 = 1'b0; + assign _zz_520 = ((_zz_529 == _zz_530) != 1'b0); + assign _zz_521 = ({_zz_531,_zz_532} != 2'b00); + assign _zz_522 = {(_zz_533 != _zz_534),{_zz_535,{_zz_536,_zz_537}}}; + assign _zz_523 = 32'h40003054; + assign _zz_524 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_525 = 32'h00001010; + assign _zz_526 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_527 = 32'h00001010; + assign _zz_528 = 32'h00001000; + assign _zz_529 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_530 = 32'h00002000; + assign _zz_531 = ((decode_INSTRUCTION & _zz_538) == 32'h00002000); + assign _zz_532 = ((decode_INSTRUCTION & _zz_539) == 32'h00001000); + assign _zz_533 = ((decode_INSTRUCTION & _zz_540) == 32'h02000050); + assign _zz_534 = 1'b0; + assign _zz_535 = ((_zz_541 == _zz_542) != 1'b0); + assign _zz_536 = (_zz_543 != 1'b0); + assign _zz_537 = {(_zz_544 != _zz_545),{_zz_546,{_zz_547,_zz_548}}}; + assign _zz_538 = 32'h00002010; + assign _zz_539 = 32'h00005000; + assign _zz_540 = 32'h02003050; + assign _zz_541 = (decode_INSTRUCTION & 32'h00004048); + assign _zz_542 = 32'h00004008; + assign _zz_543 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_544 = {(_zz_549 == _zz_550),{_zz_551,{_zz_552,_zz_553}}}; + assign _zz_545 = 4'b0000; + assign _zz_546 = ((_zz_554 == _zz_555) != 1'b0); + assign _zz_547 = (_zz_556 != 1'b0); + assign _zz_548 = {(_zz_557 != _zz_558),{_zz_559,{_zz_560,_zz_561}}}; + assign _zz_549 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_550 = 32'h00000020; + assign _zz_551 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_552 = ((decode_INSTRUCTION & _zz_562) == 32'h08000020); + assign _zz_553 = ((decode_INSTRUCTION & _zz_563) == 32'h00000020); + assign _zz_554 = (decode_INSTRUCTION & 32'h10000008); + assign _zz_555 = 32'h00000008; + assign _zz_556 = ((decode_INSTRUCTION & 32'h10000008) == 32'h10000008); + assign _zz_557 = {(_zz_564 == _zz_565),{_zz_566,{_zz_567,_zz_568}}}; + assign _zz_558 = 6'h0; + assign _zz_559 = ({_zz_569,{_zz_570,_zz_571}} != 3'b000); + assign _zz_560 = ({_zz_572,_zz_573} != 5'h0); + assign _zz_561 = {(_zz_574 != _zz_575),{_zz_576,{_zz_577,_zz_578}}}; + assign _zz_562 = 32'h08000070; + assign _zz_563 = 32'h10000070; + assign _zz_564 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_565 = 32'h00002040; + assign _zz_566 = ((decode_INSTRUCTION & _zz_579) == 32'h00001040); + assign _zz_567 = (_zz_580 == _zz_581); + assign _zz_568 = {_zz_582,{_zz_583,_zz_584}}; + assign _zz_569 = ((decode_INSTRUCTION & _zz_585) == 32'h08000020); + assign _zz_570 = (_zz_586 == _zz_587); + assign _zz_571 = (_zz_588 == _zz_589); + assign _zz_572 = (_zz_590 == _zz_591); + assign _zz_573 = {_zz_592,{_zz_593,_zz_594}}; + assign _zz_574 = {_zz_108,{_zz_595,_zz_596}}; + assign _zz_575 = 5'h0; + assign _zz_576 = ({_zz_597,_zz_598} != 7'h0); + assign _zz_577 = (_zz_599 != _zz_600); + assign _zz_578 = {_zz_601,{_zz_602,_zz_603}}; + assign _zz_579 = 32'h00001040; + assign _zz_580 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_581 = 32'h00000040; + assign _zz_582 = ((decode_INSTRUCTION & _zz_604) == 32'h00000040); + assign _zz_583 = (_zz_605 == _zz_606); + assign _zz_584 = (_zz_607 == _zz_608); + assign _zz_585 = 32'h08000020; + assign _zz_586 = (decode_INSTRUCTION & 32'h10000020); + assign _zz_587 = 32'h00000020; + assign _zz_588 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_589 = 32'h00000020; + assign _zz_590 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_591 = 32'h00000040; + assign _zz_592 = ((decode_INSTRUCTION & _zz_609) == 32'h00004020); + assign _zz_593 = (_zz_610 == _zz_611); + assign _zz_594 = {_zz_108,_zz_612}; + assign _zz_595 = (_zz_613 == _zz_614); + assign _zz_596 = {_zz_615,{_zz_616,_zz_617}}; + assign _zz_597 = _zz_105; + assign _zz_598 = {_zz_618,{_zz_619,_zz_620}}; + assign _zz_599 = {_zz_107,_zz_621}; + assign _zz_600 = 2'b00; + assign _zz_601 = ({_zz_622,_zz_623} != 2'b00); + assign _zz_602 = (_zz_624 != _zz_625); + assign _zz_603 = {_zz_626,{_zz_627,_zz_628}}; + assign _zz_604 = 32'h02400040; + assign _zz_605 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_606 = 32'h0; + assign _zz_607 = (decode_INSTRUCTION & 32'h18002008); + assign _zz_608 = 32'h10002008; + assign _zz_609 = 32'h00004020; + assign _zz_610 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_611 = 32'h00000010; + assign _zz_612 = ((decode_INSTRUCTION & _zz_629) == 32'h00000020); + assign _zz_613 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_614 = 32'h00002010; + assign _zz_615 = ((decode_INSTRUCTION & _zz_630) == 32'h00000010); + assign _zz_616 = (_zz_631 == _zz_632); + assign _zz_617 = (_zz_633 == _zz_634); + assign _zz_618 = ((decode_INSTRUCTION & _zz_635) == 32'h00001010); + assign _zz_619 = (_zz_636 == _zz_637); + assign _zz_620 = {_zz_638,{_zz_639,_zz_640}}; + assign _zz_621 = ((decode_INSTRUCTION & _zz_641) == 32'h00000020); + assign _zz_622 = _zz_107; + assign _zz_623 = (_zz_642 == _zz_643); + assign _zz_624 = (_zz_644 == _zz_645); + assign _zz_625 = 1'b0; + assign _zz_626 = (_zz_646 != 1'b0); + assign _zz_627 = (_zz_647 != _zz_648); + assign _zz_628 = {_zz_649,{_zz_650,_zz_651}}; + assign _zz_629 = 32'h02000028; + assign _zz_630 = 32'h00001030; + assign _zz_631 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_632 = 32'h00000020; + assign _zz_633 = (decode_INSTRUCTION & 32'h02002068); + assign _zz_634 = 32'h00002020; + assign _zz_635 = 32'h00001010; + assign _zz_636 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_637 = 32'h00002010; + assign _zz_638 = ((decode_INSTRUCTION & _zz_652) == 32'h00002008); + assign _zz_639 = (_zz_653 == _zz_654); + assign _zz_640 = {_zz_108,_zz_655}; + assign _zz_641 = 32'h00000070; + assign _zz_642 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_643 = 32'h0; + assign _zz_644 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_645 = 32'h00004010; + assign _zz_646 = ((decode_INSTRUCTION & _zz_656) == 32'h00002010); + assign _zz_647 = {_zz_657,{_zz_658,_zz_659}}; + assign _zz_648 = 5'h0; + assign _zz_649 = ({_zz_660,_zz_661} != 2'b00); + assign _zz_650 = (_zz_662 != _zz_663); + assign _zz_651 = {_zz_664,{_zz_665,_zz_666}}; + assign _zz_652 = 32'h00002008; + assign _zz_653 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_654 = 32'h00000010; + assign _zz_655 = ((decode_INSTRUCTION & _zz_667) == 32'h0); + assign _zz_656 = 32'h00006014; + assign _zz_657 = ((decode_INSTRUCTION & _zz_668) == 32'h0); + assign _zz_658 = (_zz_669 == _zz_670); + assign _zz_659 = {_zz_671,{_zz_672,_zz_673}}; + assign _zz_660 = _zz_106; + assign _zz_661 = (_zz_674 == _zz_675); + assign _zz_662 = {_zz_676,{_zz_677,_zz_678}}; + assign _zz_663 = 3'b000; + assign _zz_664 = ({_zz_679,_zz_680} != 3'b000); + assign _zz_665 = (_zz_681 != _zz_682); + assign _zz_666 = (_zz_683 != _zz_684); + assign _zz_667 = 32'h00000028; + assign _zz_668 = 32'h00000044; + assign _zz_669 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_670 = 32'h0; + assign _zz_671 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_672 = ((decode_INSTRUCTION & _zz_685) == 32'h00001000); + assign _zz_673 = _zz_106; + assign _zz_674 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_675 = 32'h0; + assign _zz_676 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_677 = ((decode_INSTRUCTION & _zz_686) == 32'h00002010); + assign _zz_678 = ((decode_INSTRUCTION & _zz_687) == 32'h40000030); + assign _zz_679 = _zz_105; + assign _zz_680 = {_zz_104,(_zz_688 == _zz_689)}; + assign _zz_681 = {_zz_104,(_zz_690 == _zz_691)}; + assign _zz_682 = 2'b00; + assign _zz_683 = ((decode_INSTRUCTION & _zz_692) == 32'h00001008); + assign _zz_684 = 1'b0; + assign _zz_685 = 32'h00005004; + assign _zz_686 = 32'h00002014; + assign _zz_687 = 32'h40000034; + assign _zz_688 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_689 = 32'h00000004; + assign _zz_690 = (decode_INSTRUCTION & 32'h0000004c); + assign _zz_691 = 32'h00000004; + assign _zz_692 = 32'h00005048; + assign _zz_693 = execute_INSTRUCTION[31]; + assign _zz_694 = execute_INSTRUCTION[31]; + assign _zz_695 = execute_INSTRUCTION[7]; + assign _zz_696 = 32'h0; always @ (posedge clk) begin - if(_zz_9_) begin - _zz_11_ <= ways_0_datas[_zz_8_]; + if(_zz_465) begin + _zz_235 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; + always @ (posedge clk) begin + if(_zz_466) begin + _zz_236 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; + always @ (posedge clk) begin + if(_zz_42) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_200 ), //i + .io_cpu_prefetch_isValid (_zz_201 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_202 ), //i + .io_cpu_fetch_isStuck (_zz_203 ), //i + .io_cpu_fetch_isRemoved (_zz_204 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_205 ), //i + .io_cpu_decode_isStuck (_zz_206 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_207 ), //i + .io_cpu_fill_valid (_zz_208 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_209 ), //i + .io_cpu_execute_address (_zz_210[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (_zz_211 ), //i + .io_cpu_execute_args_data (_zz_212[31:0] ), //i + .io_cpu_execute_args_size (_zz_213[1:0] ), //i + .io_cpu_execute_args_isLrsc (_zz_214 ), //i + .io_cpu_execute_args_isAmo (_zz_215 ), //i + .io_cpu_execute_args_amoCtrl_swap (_zz_216 ), //i + .io_cpu_execute_args_amoCtrl_alu (_zz_217[2:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_218 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_219[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_220 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_writeBack_isValid (_zz_221 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_222 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_223[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_224 ), //i + .io_cpu_writeBack_fence_SR (_zz_225 ), //i + .io_cpu_writeBack_fence_SO (_zz_226 ), //i + .io_cpu_writeBack_fence_SI (_zz_227 ), //i + .io_cpu_writeBack_fence_PW (_zz_228 ), //i + .io_cpu_writeBack_fence_PR (_zz_229 ), //i + .io_cpu_writeBack_fence_PO (_zz_230 ), //i + .io_cpu_writeBack_fence_PI (_zz_231 ), //i + .io_cpu_writeBack_fence_FM (_zz_232[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_233 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_234 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_467) + 3'b000 : begin + _zz_237 = DBusCachedPlugin_redoBranch_payload; end - end - end - - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_12_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; - end + 3'b001 : begin + _zz_237 = CsrPlugin_jumpInterface_payload; + end + 3'b010 : begin + _zz_237 = BranchPlugin_jumpInterface_payload; + end + 3'b011 : begin + _zz_237 = CsrPlugin_redoInterface_payload; + end + default : begin + _zz_237 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase end - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_10_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_11_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; + always @(*) begin + case(_zz_92) + 2'b00 : begin + _zz_238 = MmuPlugin_ports_0_cache_0_valid; + _zz_239 = MmuPlugin_ports_0_cache_0_exception; + _zz_240 = MmuPlugin_ports_0_cache_0_superPage; + _zz_241 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_242 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_243 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_244 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_245 = MmuPlugin_ports_0_cache_0_allowRead; + _zz_246 = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_247 = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_248 = MmuPlugin_ports_0_cache_0_allowUser; end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; + 2'b01 : begin + _zz_238 = MmuPlugin_ports_0_cache_1_valid; + _zz_239 = MmuPlugin_ports_0_cache_1_exception; + _zz_240 = MmuPlugin_ports_0_cache_1_superPage; + _zz_241 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_242 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_243 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_244 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_245 = MmuPlugin_ports_0_cache_1_allowRead; + _zz_246 = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_247 = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_248 = MmuPlugin_ports_0_cache_1_allowUser; end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; + 2'b10 : begin + _zz_238 = MmuPlugin_ports_0_cache_2_valid; + _zz_239 = MmuPlugin_ports_0_cache_2_exception; + _zz_240 = MmuPlugin_ports_0_cache_2_superPage; + _zz_241 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_242 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_243 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_244 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_245 = MmuPlugin_ports_0_cache_2_allowRead; + _zz_246 = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_247 = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_248 = MmuPlugin_ports_0_cache_2_allowUser; end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; + default : begin + _zz_238 = MmuPlugin_ports_0_cache_3_valid; + _zz_239 = MmuPlugin_ports_0_cache_3_exception; + _zz_240 = MmuPlugin_ports_0_cache_3_superPage; + _zz_241 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_242 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_243 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_244 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_245 = MmuPlugin_ports_0_cache_3_allowRead; + _zz_246 = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_247 = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_248 = MmuPlugin_ports_0_cache_3_allowUser; end - if(_zz_13_)begin - lineLoader_flushPending <= 1'b0; + endcase + end + + always @(*) begin + case(_zz_96) + 2'b00 : begin + _zz_249 = MmuPlugin_ports_1_cache_0_valid; + _zz_250 = MmuPlugin_ports_1_cache_0_exception; + _zz_251 = MmuPlugin_ports_1_cache_0_superPage; + _zz_252 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_253 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_254 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_255 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_256 = MmuPlugin_ports_1_cache_0_allowRead; + _zz_257 = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_258 = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_259 = MmuPlugin_ports_1_cache_0_allowUser; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; + 2'b01 : begin + _zz_249 = MmuPlugin_ports_1_cache_1_valid; + _zz_250 = MmuPlugin_ports_1_cache_1_exception; + _zz_251 = MmuPlugin_ports_1_cache_1_superPage; + _zz_252 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_253 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_254 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_255 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_256 = MmuPlugin_ports_1_cache_1_allowRead; + _zz_257 = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_258 = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_259 = MmuPlugin_ports_1_cache_1_allowUser; end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; + 2'b10 : begin + _zz_249 = MmuPlugin_ports_1_cache_2_valid; + _zz_250 = MmuPlugin_ports_1_cache_2_exception; + _zz_251 = MmuPlugin_ports_1_cache_2_superPage; + _zz_252 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_253 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_254 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_255 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_256 = MmuPlugin_ports_1_cache_2_allowRead; + _zz_257 = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_258 = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_259 = MmuPlugin_ports_1_cache_2_allowUser; end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end + default : begin + _zz_249 = MmuPlugin_ports_1_cache_3_valid; + _zz_250 = MmuPlugin_ports_1_cache_3_exception; + _zz_251 = MmuPlugin_ports_1_cache_3_superPage; + _zz_252 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_253 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_254 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_255 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_256 = MmuPlugin_ports_1_cache_3_allowRead; + _zz_257 = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_258 = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_259 = MmuPlugin_ports_1_cache_3_allowUser; end - end + endcase end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_12_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); - end - _zz_3_ <= lineLoader_flushCounter[7]; - if(_zz_13_)begin - lineLoader_flushCounter <= (8'b00000000); - end - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_error <= fetchStage_hit_error; - end + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; + endcase end - -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, - input [1:0] io_cpu_execute_args_size, - input io_cpu_execute_args_isLrsc, - input io_cpu_execute_args_isAmo, - input io_cpu_execute_args_amoCtrl_swap, - input [2:0] io_cpu_execute_args_amoCtrl_alu, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - input io_cpu_memory_isRemoved, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - output io_cpu_memory_mmuBus_cmd_isValid, - output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, - output io_cpu_memory_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, - input io_cpu_memory_mmuBus_rsp_isIoAccess, - input io_cpu_memory_mmuBus_rsp_allowRead, - input io_cpu_memory_mmuBus_rsp_allowWrite, - input io_cpu_memory_mmuBus_rsp_allowExecute, - input io_cpu_memory_mmuBus_rsp_exception, - input io_cpu_memory_mmuBus_rsp_refilling, - output io_cpu_memory_mmuBus_end, - input io_cpu_memory_mmuBus_busy, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - input io_cpu_writeBack_clearLrsc, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output reg io_cpu_flush_ready, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, - output reg io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire _zz_16_; - wire _zz_17_; - wire _zz_18_; - wire _zz_19_; - wire _zz_20_; - wire _zz_21_; - wire [2:0] _zz_22_; - wire [0:0] _zz_23_; - wire [0:0] _zz_24_; - wire [31:0] _zz_25_; - wire [31:0] _zz_26_; - wire [31:0] _zz_27_; - wire [31:0] _zz_28_; - wire [1:0] _zz_29_; - wire [31:0] _zz_30_; - wire [1:0] _zz_31_; - wire [1:0] _zz_32_; - wire [0:0] _zz_33_; - wire [0:0] _zz_34_; - wire [2:0] _zz_35_; - wire [1:0] _zz_36_; - wire [21:0] _zz_37_; - reg _zz_1_; - reg _zz_2_; - wire haltCpu; - reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3_; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4_; - wire _zz_5_; - wire [31:0] ways_0_dataReadRsp; - reg [3:0] _zz_6_; - wire [3:0] stage0_mask; - wire [0:0] stage0_colisions; - reg stageA_request_wr; - reg [31:0] stageA_request_data; - reg [1:0] stageA_request_size; - reg stageA_request_isLrsc; - reg stageA_request_isAmo; - reg stageA_request_amoCtrl_swap; - reg [2:0] stageA_request_amoCtrl_alu; - reg [3:0] stageA_mask; - wire stageA_wayHits_0; - reg [0:0] stage0_colisions_regNextWhen; - wire [0:0] _zz_7_; - wire [0:0] stageA_colisions; - reg stageB_request_wr; - reg [31:0] stageB_request_data; - reg [1:0] stageB_request_size; - reg stageB_request_isLrsc; - reg stageB_isAmo; - reg stageB_request_amoCtrl_swap; - reg [2:0] stageB_request_amoCtrl_alu; - reg stageB_mmuRspFreeze; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg [31:0] stageB_dataReadRsp_0; - wire [0:0] _zz_8_; - reg [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - reg [3:0] stageB_mask; - reg [0:0] stageB_colisions; - reg stageB_loaderValid; - reg stageB_flusher_valid; - reg stageB_lrsc_reserved; - reg [31:0] stageB_requestDataBypass; - wire stageB_amo_compare; - wire stageB_amo_unsigned; - wire [31:0] stageB_amo_addSub; - wire stageB_amo_less; - wire stageB_amo_selectRf; - reg [31:0] stageB_amo_result; - reg stageB_amo_resultRegValid; - reg [31:0] stageB_amo_resultReg; - reg stageB_memCmdSent; - wire [0:0] _zz_9_; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [2:0] loader_counter_valueNext; - reg [2:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_38_; - reg [7:0] _zz_39_; - reg [7:0] _zz_40_; - reg [7:0] _zz_41_; - assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); - assign _zz_15_ = (! stageB_amo_resultRegValid); - assign _zz_16_ = (stageB_request_isLrsc && (! stageB_lrsc_reserved)); - assign _zz_17_ = (loader_valid && io_mem_rsp_valid); - assign _zz_18_ = (stageB_request_isLrsc && (! stageB_lrsc_reserved)); - assign _zz_19_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - assign _zz_20_ = (((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))); - assign _zz_21_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign _zz_22_ = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,(2'b00)}); - assign _zz_23_ = _zz_4_[0 : 0]; - assign _zz_24_ = _zz_4_[1 : 1]; - assign _zz_25_ = ($signed(_zz_26_) + $signed(_zz_30_)); - assign _zz_26_ = ($signed(_zz_27_) + $signed(_zz_28_)); - assign _zz_27_ = stageB_request_data; - assign _zz_28_ = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux); - assign _zz_29_ = (stageB_amo_compare ? _zz_31_ : _zz_32_); - assign _zz_30_ = {{30{_zz_29_[1]}}, _zz_29_}; - assign _zz_31_ = (2'b01); - assign _zz_32_ = (2'b00); - assign _zz_33_ = (! stageB_lrsc_reserved); - assign _zz_34_ = loader_counter_willIncrement; - assign _zz_35_ = {2'd0, _zz_34_}; - assign _zz_36_ = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_37_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_37_; - end + always @(*) begin + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_3_) begin - _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; - end + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase end - - always @ (*) begin - _zz_11_ = {_zz_41_, _zz_40_, _zz_39_, _zz_38_}; + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase end - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1_) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1_) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1_) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1_) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_5_) begin - _zz_38_ <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_39_ <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_40_ <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_41_ <= ways_0_data_symbol3[dataReadCmd_payload]; - end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase end - - always @ (*) begin - _zz_1_ = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_1_ = 1'b1; - end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase end - - always @ (*) begin - _zz_2_ = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_2_ = 1'b1; - end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase end - - assign haltCpu = 1'b0; - assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4_ = _zz_10_; - assign ways_0_tagsReadRsp_valid = _zz_23_[0]; - assign ways_0_tagsReadRsp_error = _zz_24_[0]; - assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; - assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRsp = _zz_11_; - always @ (*) begin - tagsReadCmd_valid = 1'b0; - if(_zz_12_)begin - tagsReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; + endcase end - - always @ (*) begin - tagsReadCmd_payload = (7'bxxxxxxx); - if(_zz_12_)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; - end - end - - always @ (*) begin - dataReadCmd_valid = 1'b0; - if(_zz_12_)begin - dataReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_payload = (10'bxxxxxxxxxx); - if(_zz_12_)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end + always @(*) begin + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; - end - if(_zz_13_)begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_way = (1'bx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = (1'b1); - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_address = (7'bxxxxxxx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_valid = 1'b1; - end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); - end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((stageB_request_wr && stageB_waysHit))begin - dataWriteCmd_valid = 1'b1; - end - if(stageB_isAmo)begin - if(_zz_15_)begin - dataWriteCmd_valid = 1'b0; - end - end - if(_zz_16_)begin - dataWriteCmd_valid = 1'b0; - end - end - end - end - if(_zz_13_)begin - dataWriteCmd_valid = 1'b0; - end - if(_zz_17_)begin - dataWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_way = (1'bx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_way = stageB_waysHits; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_address = (10'bxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; - end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_data = stageB_requestDataBypass; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_mask = (4'bxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_mask = stageB_mask; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_mask = (4'b1111); - end + always @(*) begin + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; + endcase end - - always @ (*) begin - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_6_ = (4'b0001); - end - 2'b01 : begin - _zz_6_ = (4'b0011); - end - default : begin - _zz_6_ = (4'b1111); - end + always @(*) begin + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; endcase end - - assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); - assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; - assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; - assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); - always @ (*) begin - stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin - stageB_mmuRspFreeze = 1'b1; - end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; + endcase end - - assign _zz_8_[0] = stageA_wayHits_0; - assign stageB_waysHit = (stageB_waysHits != (1'b0)); - assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - if(io_mem_cmd_ready)begin - stageB_loaderValid = 1'b1; - end - end - end - end - if(_zz_13_)begin - stageB_loaderValid = 1'b0; - end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin - io_cpu_writeBack_haltIt = 1'b0; - end - if(_zz_18_)begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(_zz_14_)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin - io_cpu_writeBack_haltIt = 1'b0; - end - if(stageB_isAmo)begin - if(_zz_15_)begin - io_cpu_writeBack_haltIt = 1'b1; - end - end - if(_zz_16_)begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - if(_zz_13_)begin - io_cpu_writeBack_haltIt = 1'b0; - end + always @(*) begin + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(_zz_19_)begin - io_cpu_flush_ready = 1'b1; - end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase end - - always @ (*) begin - stageB_requestDataBypass = stageB_request_data; - if(stageB_isAmo)begin - stageB_requestDataBypass = stageB_amo_resultReg; - end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase end - - assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; - assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == (2'b11)); - assign stageB_amo_addSub = _zz_25_; - assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31])); - assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); - always @ (*) begin - case(_zz_22_) - 3'b000 : begin - stageB_amo_result = stageB_amo_addSub; - end - 3'b001 : begin - stageB_amo_result = (stageB_request_data ^ stageB_dataMux); - end - 3'b010 : begin - stageB_amo_result = (stageB_request_data | stageB_dataMux); - end - 3'b011 : begin - stageB_amo_result = (stageB_request_data & stageB_dataMux); - end - default : begin - stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux); - end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; endcase end - - always @ (*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if(_zz_20_)begin - io_cpu_redo = 1'b1; - end - end - end - end - if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin - io_cpu_redo = 1'b1; - end - if(loader_valid)begin - io_cpu_redo = 1'b1; - end + always @(*) begin + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); - end - end - - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_valid = (! stageB_memCmdSent); - if(_zz_18_)begin - io_mem_cmd_valid = 1'b0; - end - end else begin - if(_zz_14_)begin - if(stageB_request_wr)begin - io_mem_cmd_valid = 1'b1; - end - if(stageB_isAmo)begin - if(_zz_15_)begin - io_mem_cmd_valid = 1'b0; - end - end - if(_zz_20_)begin - io_mem_cmd_valid = 1'b0; - end - if(_zz_16_)begin - io_mem_cmd_valid = 1'b0; - end - end else begin - if((! stageB_memCmdSent))begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - io_mem_cmd_valid = 1'b0; - end - end - - always @ (*) begin - io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = (3'bxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - io_mem_cmd_payload_length = (3'b111); - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_last = 1'bx; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - io_mem_cmd_payload_last = 1'b1; - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - always @ (*) begin - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_data = io_mem_rsp_payload_data; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - if((stageB_request_isLrsc && stageB_request_wr))begin - io_cpu_writeBack_data = {31'd0, _zz_33_}; - end - end - - assign _zz_9_[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin - loader_counter_willIncrement = 1'b0; - if(_zz_17_)begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_35_); - if(loader_counter_willClear)begin - loader_counter_valueNext = (3'b000); - end - end - - always @ (posedge clk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; - stageA_request_size <= io_cpu_execute_args_size; - stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; - stageA_request_isAmo <= io_cpu_execute_args_isAmo; - stageA_request_amoCtrl_swap <= io_cpu_execute_args_amoCtrl_swap; - stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; - end - if((! io_cpu_memory_isStuck))begin - stageA_mask <= stage0_mask; - end - if((! io_cpu_memory_isStuck))begin - stage0_colisions_regNextWhen <= stage0_colisions; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; - stageB_request_size <= stageA_request_size; - stageB_request_isLrsc <= stageA_request_isLrsc; - stageB_isAmo <= stageA_request_isAmo; - stageB_request_amoCtrl_swap <= stageA_request_amoCtrl_swap; - stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; - end - if(_zz_21_)begin - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_waysHits <= _zz_8_; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_mask <= stageA_mask; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_colisions <= stageA_colisions; - end - stageB_amo_resultRegValid <= 1'b1; - if((! io_cpu_writeBack_isStuck))begin - stageB_amo_resultRegValid <= 1'b0; - end - stageB_amo_resultReg <= stageB_amo_result; - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); - end - end - - always @ (posedge clk) begin - if(reset) begin - stageB_flusher_valid <= 1'b1; - stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); - stageB_lrsc_reserved <= 1'b0; - stageB_memCmdSent <= 1'b0; - loader_valid <= 1'b0; - loader_counter_value <= (3'b000); - loader_waysAllocator <= (1'b1); - loader_error <= 1'b0; - end else begin - if(_zz_21_)begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; - end - if(stageB_flusher_valid)begin - if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); - end else begin - stageB_flusher_valid <= 1'b0; - end - end - if(_zz_19_)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); - stageB_flusher_valid <= 1'b1; - end - if(((((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && (! io_cpu_redo)) && stageB_request_isLrsc) && (! stageB_request_wr)))begin - stageB_lrsc_reserved <= 1'b1; - end - if(io_cpu_writeBack_clearLrsc)begin - stageB_lrsc_reserved <= 1'b0; - end - if(io_mem_cmd_ready)begin - stageB_memCmdSent <= 1'b1; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_memCmdSent <= 1'b0; - end - if(stageB_loaderValid)begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(_zz_17_)begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_counter_willOverflow)begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - end - if((! loader_valid))begin - loader_waysAllocator <= _zz_36_[0:0]; - end - end - end - -endmodule - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset); - wire _zz_239_; - wire _zz_240_; - wire _zz_241_; - wire _zz_242_; - wire [31:0] _zz_243_; - wire _zz_244_; - wire _zz_245_; - wire _zz_246_; - reg _zz_247_; - reg _zz_248_; - reg [31:0] _zz_249_; - reg _zz_250_; - reg [31:0] _zz_251_; - reg [1:0] _zz_252_; - reg _zz_253_; - reg _zz_254_; - wire _zz_255_; - wire [2:0] _zz_256_; - reg _zz_257_; - wire [31:0] _zz_258_; - reg _zz_259_; - reg _zz_260_; - wire _zz_261_; - wire [31:0] _zz_262_; - wire _zz_263_; - wire _zz_264_; - reg [31:0] _zz_265_; - reg [31:0] _zz_266_; - reg [31:0] _zz_267_; - reg _zz_268_; - reg _zz_269_; - reg _zz_270_; - reg [9:0] _zz_271_; - reg [9:0] _zz_272_; - reg [9:0] _zz_273_; - reg [9:0] _zz_274_; - reg _zz_275_; - reg _zz_276_; - reg _zz_277_; - reg _zz_278_; - reg _zz_279_; - reg _zz_280_; - reg _zz_281_; - reg [9:0] _zz_282_; - reg [9:0] _zz_283_; - reg [9:0] _zz_284_; - reg [9:0] _zz_285_; - reg _zz_286_; - reg _zz_287_; - reg _zz_288_; - reg _zz_289_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1__io_cpu_memory_isWrite; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; - wire dataCache_1__io_cpu_memory_mmuBus_end; - wire dataCache_1__io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1__io_cpu_writeBack_data; - wire dataCache_1__io_cpu_writeBack_mmuException; - wire dataCache_1__io_cpu_writeBack_unalignedAccess; - wire dataCache_1__io_cpu_writeBack_accessError; - wire dataCache_1__io_cpu_writeBack_isWrite; - wire dataCache_1__io_cpu_flush_ready; - wire dataCache_1__io_cpu_redo; - wire dataCache_1__io_mem_cmd_valid; - wire dataCache_1__io_mem_cmd_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_payload_length; - wire dataCache_1__io_mem_cmd_payload_last; - wire _zz_290_; - wire _zz_291_; - wire _zz_292_; - wire _zz_293_; - wire _zz_294_; - wire _zz_295_; - wire _zz_296_; - wire _zz_297_; - wire _zz_298_; - wire _zz_299_; - wire _zz_300_; - wire _zz_301_; - wire _zz_302_; - wire _zz_303_; - wire _zz_304_; - wire [1:0] _zz_305_; - wire _zz_306_; - wire _zz_307_; - wire _zz_308_; - wire _zz_309_; - wire _zz_310_; - wire _zz_311_; - wire _zz_312_; - wire _zz_313_; - wire _zz_314_; - wire _zz_315_; - wire _zz_316_; - wire _zz_317_; - wire _zz_318_; - wire _zz_319_; - wire _zz_320_; - wire [1:0] _zz_321_; - wire _zz_322_; - wire _zz_323_; - wire _zz_324_; - wire _zz_325_; - wire _zz_326_; - wire _zz_327_; - wire _zz_328_; - wire _zz_329_; - wire _zz_330_; - wire _zz_331_; - wire _zz_332_; - wire _zz_333_; - wire _zz_334_; - wire _zz_335_; - wire _zz_336_; - wire _zz_337_; - wire _zz_338_; - wire _zz_339_; - wire _zz_340_; - wire _zz_341_; - wire _zz_342_; - wire _zz_343_; - wire _zz_344_; - wire _zz_345_; - wire [1:0] _zz_346_; - wire _zz_347_; - wire [1:0] _zz_348_; - wire [4:0] _zz_349_; - wire [2:0] _zz_350_; - wire [31:0] _zz_351_; - wire [11:0] _zz_352_; - wire [31:0] _zz_353_; - wire [19:0] _zz_354_; - wire [11:0] _zz_355_; - wire [31:0] _zz_356_; - wire [31:0] _zz_357_; - wire [19:0] _zz_358_; - wire [11:0] _zz_359_; - wire [2:0] _zz_360_; - wire [2:0] _zz_361_; - wire [0:0] _zz_362_; - wire [1:0] _zz_363_; - wire [0:0] _zz_364_; - wire [1:0] _zz_365_; - wire [0:0] _zz_366_; - wire [0:0] _zz_367_; - wire [0:0] _zz_368_; - wire [0:0] _zz_369_; - wire [0:0] _zz_370_; - wire [0:0] _zz_371_; - wire [0:0] _zz_372_; - wire [0:0] _zz_373_; - wire [0:0] _zz_374_; - wire [0:0] _zz_375_; - wire [0:0] _zz_376_; - wire [0:0] _zz_377_; - wire [0:0] _zz_378_; - wire [0:0] _zz_379_; - wire [0:0] _zz_380_; - wire [0:0] _zz_381_; - wire [0:0] _zz_382_; - wire [0:0] _zz_383_; - wire [0:0] _zz_384_; - wire [0:0] _zz_385_; - wire [0:0] _zz_386_; - wire [0:0] _zz_387_; - wire [0:0] _zz_388_; - wire [0:0] _zz_389_; - wire [0:0] _zz_390_; - wire [0:0] _zz_391_; - wire [0:0] _zz_392_; - wire [0:0] _zz_393_; - wire [0:0] _zz_394_; - wire [2:0] _zz_395_; - wire [4:0] _zz_396_; - wire [11:0] _zz_397_; - wire [11:0] _zz_398_; - wire [31:0] _zz_399_; - wire [31:0] _zz_400_; - wire [31:0] _zz_401_; - wire [31:0] _zz_402_; - wire [31:0] _zz_403_; - wire [31:0] _zz_404_; - wire [31:0] _zz_405_; - wire [32:0] _zz_406_; - wire [31:0] _zz_407_; - wire [32:0] _zz_408_; - wire [11:0] _zz_409_; - wire [19:0] _zz_410_; - wire [11:0] _zz_411_; - wire [31:0] _zz_412_; - wire [31:0] _zz_413_; - wire [31:0] _zz_414_; - wire [11:0] _zz_415_; - wire [19:0] _zz_416_; - wire [11:0] _zz_417_; - wire [2:0] _zz_418_; - wire [1:0] _zz_419_; - wire [1:0] _zz_420_; - wire [51:0] _zz_421_; - wire [51:0] _zz_422_; - wire [51:0] _zz_423_; - wire [32:0] _zz_424_; - wire [51:0] _zz_425_; - wire [49:0] _zz_426_; - wire [51:0] _zz_427_; - wire [49:0] _zz_428_; - wire [51:0] _zz_429_; - wire [65:0] _zz_430_; - wire [65:0] _zz_431_; - wire [31:0] _zz_432_; - wire [31:0] _zz_433_; - wire [0:0] _zz_434_; - wire [5:0] _zz_435_; - wire [32:0] _zz_436_; - wire [32:0] _zz_437_; - wire [31:0] _zz_438_; - wire [31:0] _zz_439_; - wire [32:0] _zz_440_; - wire [32:0] _zz_441_; - wire [32:0] _zz_442_; - wire [0:0] _zz_443_; - wire [32:0] _zz_444_; - wire [0:0] _zz_445_; - wire [32:0] _zz_446_; - wire [0:0] _zz_447_; - wire [31:0] _zz_448_; - wire [0:0] _zz_449_; - wire [0:0] _zz_450_; - wire [0:0] _zz_451_; - wire [0:0] _zz_452_; - wire [0:0] _zz_453_; - wire [0:0] _zz_454_; - wire [0:0] _zz_455_; - wire [0:0] _zz_456_; - wire [0:0] _zz_457_; - wire [0:0] _zz_458_; - wire [0:0] _zz_459_; - wire [0:0] _zz_460_; - wire [0:0] _zz_461_; - wire [0:0] _zz_462_; - wire [0:0] _zz_463_; - wire [0:0] _zz_464_; - wire [0:0] _zz_465_; - wire [0:0] _zz_466_; - wire [0:0] _zz_467_; - wire [0:0] _zz_468_; - wire [0:0] _zz_469_; - wire [0:0] _zz_470_; - wire [0:0] _zz_471_; - wire [0:0] _zz_472_; - wire [0:0] _zz_473_; - wire [0:0] _zz_474_; - wire [0:0] _zz_475_; - wire [0:0] _zz_476_; - wire [0:0] _zz_477_; - wire [0:0] _zz_478_; - wire [0:0] _zz_479_; - wire [0:0] _zz_480_; - wire [0:0] _zz_481_; - wire [0:0] _zz_482_; - wire [0:0] _zz_483_; - wire [0:0] _zz_484_; - wire [0:0] _zz_485_; - wire [0:0] _zz_486_; - wire [0:0] _zz_487_; - wire [0:0] _zz_488_; - wire [0:0] _zz_489_; - wire [0:0] _zz_490_; - wire [0:0] _zz_491_; - wire [0:0] _zz_492_; - wire [0:0] _zz_493_; - wire [26:0] _zz_494_; - wire _zz_495_; - wire _zz_496_; - wire [2:0] _zz_497_; - wire _zz_498_; - wire _zz_499_; - wire _zz_500_; - wire [31:0] _zz_501_; - wire [31:0] _zz_502_; - wire _zz_503_; - wire [0:0] _zz_504_; - wire [1:0] _zz_505_; - wire [31:0] _zz_506_; - wire [31:0] _zz_507_; - wire _zz_508_; - wire [0:0] _zz_509_; - wire [0:0] _zz_510_; - wire _zz_511_; - wire [0:0] _zz_512_; - wire [28:0] _zz_513_; - wire [31:0] _zz_514_; - wire [31:0] _zz_515_; - wire [31:0] _zz_516_; - wire [31:0] _zz_517_; - wire [31:0] _zz_518_; - wire [31:0] _zz_519_; - wire [2:0] _zz_520_; - wire [2:0] _zz_521_; - wire _zz_522_; - wire [0:0] _zz_523_; - wire [25:0] _zz_524_; - wire [31:0] _zz_525_; - wire [31:0] _zz_526_; - wire [31:0] _zz_527_; - wire [31:0] _zz_528_; - wire [31:0] _zz_529_; - wire [31:0] _zz_530_; - wire [31:0] _zz_531_; - wire [31:0] _zz_532_; - wire [31:0] _zz_533_; - wire [0:0] _zz_534_; - wire [0:0] _zz_535_; - wire _zz_536_; - wire [0:0] _zz_537_; - wire [21:0] _zz_538_; - wire [31:0] _zz_539_; - wire [31:0] _zz_540_; - wire [31:0] _zz_541_; - wire [0:0] _zz_542_; - wire [5:0] _zz_543_; - wire [4:0] _zz_544_; - wire [4:0] _zz_545_; - wire _zz_546_; - wire [0:0] _zz_547_; - wire [17:0] _zz_548_; - wire [31:0] _zz_549_; - wire [31:0] _zz_550_; - wire _zz_551_; - wire [0:0] _zz_552_; - wire [2:0] _zz_553_; - wire [31:0] _zz_554_; - wire [31:0] _zz_555_; - wire _zz_556_; - wire [0:0] _zz_557_; - wire [1:0] _zz_558_; - wire [31:0] _zz_559_; - wire [31:0] _zz_560_; - wire [0:0] _zz_561_; - wire [0:0] _zz_562_; - wire [2:0] _zz_563_; - wire [2:0] _zz_564_; - wire _zz_565_; - wire [0:0] _zz_566_; - wire [14:0] _zz_567_; - wire [31:0] _zz_568_; - wire [31:0] _zz_569_; - wire [31:0] _zz_570_; - wire _zz_571_; - wire [0:0] _zz_572_; - wire [0:0] _zz_573_; - wire [31:0] _zz_574_; - wire [31:0] _zz_575_; - wire [31:0] _zz_576_; - wire _zz_577_; - wire [31:0] _zz_578_; - wire [31:0] _zz_579_; - wire [31:0] _zz_580_; - wire [31:0] _zz_581_; - wire _zz_582_; - wire [0:0] _zz_583_; - wire [0:0] _zz_584_; - wire [0:0] _zz_585_; - wire [0:0] _zz_586_; - wire [1:0] _zz_587_; - wire [1:0] _zz_588_; - wire _zz_589_; - wire [0:0] _zz_590_; - wire [12:0] _zz_591_; - wire [31:0] _zz_592_; - wire [31:0] _zz_593_; - wire [31:0] _zz_594_; - wire [31:0] _zz_595_; - wire [31:0] _zz_596_; - wire [31:0] _zz_597_; - wire [31:0] _zz_598_; - wire [31:0] _zz_599_; - wire [31:0] _zz_600_; - wire [31:0] _zz_601_; - wire [31:0] _zz_602_; - wire _zz_603_; - wire [0:0] _zz_604_; - wire [1:0] _zz_605_; - wire [1:0] _zz_606_; - wire [1:0] _zz_607_; - wire _zz_608_; - wire [0:0] _zz_609_; - wire [10:0] _zz_610_; - wire [31:0] _zz_611_; - wire [31:0] _zz_612_; - wire [31:0] _zz_613_; - wire [31:0] _zz_614_; - wire [31:0] _zz_615_; - wire [31:0] _zz_616_; - wire [31:0] _zz_617_; - wire [31:0] _zz_618_; - wire [31:0] _zz_619_; - wire _zz_620_; - wire [0:0] _zz_621_; - wire [3:0] _zz_622_; - wire [0:0] _zz_623_; - wire [1:0] _zz_624_; - wire [1:0] _zz_625_; - wire [1:0] _zz_626_; - wire _zz_627_; - wire [0:0] _zz_628_; - wire [7:0] _zz_629_; - wire [31:0] _zz_630_; - wire [31:0] _zz_631_; - wire [31:0] _zz_632_; - wire _zz_633_; - wire [0:0] _zz_634_; - wire [1:0] _zz_635_; - wire _zz_636_; - wire _zz_637_; - wire _zz_638_; - wire [0:0] _zz_639_; - wire [0:0] _zz_640_; - wire _zz_641_; - wire [0:0] _zz_642_; - wire [5:0] _zz_643_; - wire [31:0] _zz_644_; - wire [31:0] _zz_645_; - wire [31:0] _zz_646_; - wire _zz_647_; - wire _zz_648_; - wire [31:0] _zz_649_; - wire [31:0] _zz_650_; - wire [31:0] _zz_651_; - wire [31:0] _zz_652_; - wire [31:0] _zz_653_; - wire [0:0] _zz_654_; - wire [0:0] _zz_655_; - wire [0:0] _zz_656_; - wire [0:0] _zz_657_; - wire _zz_658_; - wire [0:0] _zz_659_; - wire [3:0] _zz_660_; - wire [31:0] _zz_661_; - wire [31:0] _zz_662_; - wire [31:0] _zz_663_; - wire [31:0] _zz_664_; - wire [0:0] _zz_665_; - wire [2:0] _zz_666_; - wire [4:0] _zz_667_; - wire [4:0] _zz_668_; - wire _zz_669_; - wire [0:0] _zz_670_; - wire [0:0] _zz_671_; - wire [31:0] _zz_672_; - wire [31:0] _zz_673_; - wire [31:0] _zz_674_; - wire _zz_675_; - wire _zz_676_; - wire _zz_677_; - wire [0:0] _zz_678_; - wire [1:0] _zz_679_; - wire [31:0] _zz_680_; - wire [31:0] _zz_681_; - wire [0:0] _zz_682_; - wire [0:0] _zz_683_; - wire _zz_684_; - wire [31:0] _zz_685_; - wire [31:0] _zz_686_; - wire [31:0] _zz_687_; - wire [31:0] _zz_688_; - wire [31:0] _zz_689_; - wire [31:0] _zz_690_; - wire [31:0] _zz_691_; - wire [31:0] _zz_692_; - wire [31:0] _zz_693_; - wire [31:0] _zz_694_; - wire _zz_695_; - wire [0:0] _zz_696_; - wire [17:0] _zz_697_; - wire [31:0] _zz_698_; - wire [31:0] _zz_699_; - wire [31:0] _zz_700_; - wire _zz_701_; - wire [0:0] _zz_702_; - wire [11:0] _zz_703_; - wire [31:0] _zz_704_; - wire [31:0] _zz_705_; - wire [31:0] _zz_706_; - wire _zz_707_; - wire [0:0] _zz_708_; - wire [5:0] _zz_709_; - wire [31:0] _zz_710_; - wire [31:0] _zz_711_; - wire [31:0] _zz_712_; - wire _zz_713_; - wire _zz_714_; - wire _zz_715_; - wire _zz_716_; - wire _zz_717_; - wire decode_IS_RS1_SIGNED; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire memory_IS_MUL; - wire execute_IS_MUL; - wire decode_IS_MUL; - wire decode_IS_DIV; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire `BranchCtrlEnum_defaultEncoding_type _zz_1_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_2_; - wire decode_CSR_WRITE_OPCODE; - wire decode_MEMORY_LRSC; - wire [33:0] execute_MUL_LH; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire execute_IS_DBUS_SHARING; - wire [31:0] memory_PC; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_3_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_4_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_5_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_6_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_7_; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_8_; - wire `AluCtrlEnum_defaultEncoding_type _zz_9_; - wire `AluCtrlEnum_defaultEncoding_type _zz_10_; - wire decode_CSR_READ_OPCODE; - wire execute_BRANCH_DO; - wire decode_PREDICTION_HAD_BRANCHED2; - wire memory_IS_SFENCE_VMA; - wire execute_IS_SFENCE_VMA; - wire decode_IS_SFENCE_VMA; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_11_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_12_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_13_; - wire [33:0] execute_MUL_HL; - wire decode_MEMORY_AMO; - wire decode_SRC_LESS_UNSIGNED; - wire decode_SRC2_FORCE_ZERO; - wire [31:0] execute_MUL_LL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16_; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_17_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19_; - wire [31:0] execute_SHIFT_RIGHT; - wire [31:0] execute_BRANCH_CALC; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire decode_IS_RS2_SIGNED; - wire decode_MEMORY_MANAGMENT; - wire `EnvCtrlEnum_defaultEncoding_type _zz_20_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_21_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_22_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_23_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_24_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_25_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire decode_IS_CSR; - wire [51:0] memory_MUL_LOW; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire [51:0] _zz_27_; - wire [33:0] _zz_28_; - wire [33:0] _zz_29_; - wire [33:0] _zz_30_; - wire [31:0] _zz_31_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_32_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; - wire _zz_34_; - wire _zz_35_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_36_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_37_; - wire [31:0] execute_PC; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_38_; - wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_39_; - wire _zz_40_; - wire _zz_41_; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_42_; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_43_; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_44_; - wire [31:0] _zz_45_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_46_; - wire _zz_47_; - wire [31:0] _zz_48_; - wire [31:0] _zz_49_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_50_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_51_; - wire [31:0] _zz_52_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_53_; - wire [31:0] _zz_54_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_55_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_56_; - wire [31:0] _zz_57_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; - wire [31:0] _zz_59_; - wire _zz_60_; - reg _zz_61_; - wire [31:0] _zz_62_; - wire [31:0] _zz_63_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_64_; - wire _zz_65_; - wire _zz_66_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_67_; - wire _zz_68_; - wire _zz_69_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_70_; - wire _zz_71_; - wire _zz_72_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_73_; - wire _zz_74_; - wire _zz_75_; - wire _zz_76_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_77_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_78_; - wire _zz_79_; - wire _zz_80_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_81_; - wire `AluCtrlEnum_defaultEncoding_type _zz_82_; - wire _zz_83_; - wire _zz_84_; - wire _zz_85_; - wire _zz_86_; - wire _zz_87_; - wire _zz_88_; - wire _zz_89_; - wire _zz_90_; - wire _zz_91_; - wire writeBack_IS_SFENCE_VMA; - wire writeBack_IS_DBUS_SHARING; - wire memory_IS_DBUS_SHARING; - wire _zz_92_; - reg [31:0] _zz_93_; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_ENABLE; - wire [1:0] _zz_94_; - wire execute_MEMORY_AMO; - wire execute_MEMORY_LRSC; - wire execute_MEMORY_MANAGMENT; - wire [31:0] execute_RS2; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_95_; - reg _zz_96_; - reg _zz_97_; - wire [31:0] _zz_98_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_99_; - wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_100_; - reg [31:0] _zz_101_; - wire [31:0] decode_PC; - wire [31:0] _zz_102_; - wire [31:0] _zz_103_; - wire [31:0] _zz_104_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - wire decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - wire execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - wire execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_predictionJumpInterface_valid; - (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; - reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; - wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - reg IBusCachedPlugin_mmuBus_rsp_allowRead; - reg IBusCachedPlugin_mmuBus_rsp_allowWrite; - reg IBusCachedPlugin_mmuBus_rsp_allowExecute; - reg IBusCachedPlugin_mmuBus_rsp_exception; - reg IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; - reg DBusCachedPlugin_mmuBus_cmd_bypassTranslation; - reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - reg DBusCachedPlugin_mmuBus_rsp_allowRead; - reg DBusCachedPlugin_mmuBus_rsp_allowWrite; - reg DBusCachedPlugin_mmuBus_rsp_allowExecute; - reg DBusCachedPlugin_mmuBus_rsp_exception; - reg DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg MmuPlugin_dBusAccess_cmd_valid; - reg MmuPlugin_dBusAccess_cmd_ready; - reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; - wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; - wire MmuPlugin_dBusAccess_cmd_payload_write; - wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; - wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; - wire MmuPlugin_dBusAccess_rsp_valid; - wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; - wire MmuPlugin_dBusAccess_rsp_payload_error; - wire MmuPlugin_dBusAccess_rsp_payload_redo; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire externalInterruptS; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - wire CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - wire CsrPlugin_allowInterrupts; - wire CsrPlugin_allowException; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_105_; - wire [4:0] _zz_106_; - wire _zz_107_; - wire _zz_108_; - wire _zz_109_; - wire _zz_110_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_111_; - wire _zz_112_; - wire _zz_113_; - wire _zz_114_; - wire _zz_115_; - reg _zz_116_; - wire _zz_117_; - reg _zz_118_; - reg [31:0] _zz_119_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_decodeInput_valid; - wire IBusCachedPlugin_iBusRsp_decodeInput_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - reg IBusCachedPlugin_injector_decodeRemoved; - wire _zz_120_; - reg [18:0] _zz_121_; - wire _zz_122_; - reg [10:0] _zz_123_; - wire _zz_124_; - reg [18:0] _zz_125_; - reg _zz_126_; - wire _zz_127_; - reg [10:0] _zz_128_; - wire _zz_129_; - reg [18:0] _zz_130_; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_131_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; - wire dBus_cmd_payload_last; - wire dBus_rsp_valid; - wire [31:0] dBus_rsp_payload_data; - wire dBus_rsp_payload_error; - wire dataCache_1__io_mem_cmd_s2mPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; - reg _zz_132_; - reg _zz_133_; - reg [31:0] _zz_134_; - reg [31:0] _zz_135_; - reg [3:0] _zz_136_; - reg [2:0] _zz_137_; - reg _zz_138_; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg _zz_139_; - reg _zz_140_; - reg [31:0] _zz_141_; - reg [31:0] _zz_142_; - reg [3:0] _zz_143_; - reg [2:0] _zz_144_; - reg _zz_145_; - wire [31:0] _zz_146_; - reg [31:0] DBusCachedPlugin_rspCounter; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_147_; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_148_; - reg [31:0] _zz_149_; - wire _zz_150_; - reg [31:0] _zz_151_; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - reg DBusCachedPlugin_forceDatapath; - reg MmuPlugin_status_sum; - reg MmuPlugin_status_mxr; - reg MmuPlugin_status_mprv; - reg MmuPlugin_satp_mode; - reg [19:0] MmuPlugin_satp_ppn; - reg MmuPlugin_ports_0_cache_0_valid; - reg MmuPlugin_ports_0_cache_0_exception; - reg MmuPlugin_ports_0_cache_0_superPage; - reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; - reg MmuPlugin_ports_0_cache_0_allowRead; - reg MmuPlugin_ports_0_cache_0_allowWrite; - reg MmuPlugin_ports_0_cache_0_allowExecute; - reg MmuPlugin_ports_0_cache_0_allowUser; - reg MmuPlugin_ports_0_cache_1_valid; - reg MmuPlugin_ports_0_cache_1_exception; - reg MmuPlugin_ports_0_cache_1_superPage; - reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; - reg MmuPlugin_ports_0_cache_1_allowRead; - reg MmuPlugin_ports_0_cache_1_allowWrite; - reg MmuPlugin_ports_0_cache_1_allowExecute; - reg MmuPlugin_ports_0_cache_1_allowUser; - reg MmuPlugin_ports_0_cache_2_valid; - reg MmuPlugin_ports_0_cache_2_exception; - reg MmuPlugin_ports_0_cache_2_superPage; - reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; - reg MmuPlugin_ports_0_cache_2_allowRead; - reg MmuPlugin_ports_0_cache_2_allowWrite; - reg MmuPlugin_ports_0_cache_2_allowExecute; - reg MmuPlugin_ports_0_cache_2_allowUser; - reg MmuPlugin_ports_0_cache_3_valid; - reg MmuPlugin_ports_0_cache_3_exception; - reg MmuPlugin_ports_0_cache_3_superPage; - reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; - reg MmuPlugin_ports_0_cache_3_allowRead; - reg MmuPlugin_ports_0_cache_3_allowWrite; - reg MmuPlugin_ports_0_cache_3_allowExecute; - reg MmuPlugin_ports_0_cache_3_allowUser; - wire MmuPlugin_ports_0_cacheHits_0; - wire MmuPlugin_ports_0_cacheHits_1; - wire MmuPlugin_ports_0_cacheHits_2; - wire MmuPlugin_ports_0_cacheHits_3; - wire MmuPlugin_ports_0_cacheHit; - wire _zz_152_; - wire _zz_153_; - wire [1:0] _zz_154_; - wire MmuPlugin_ports_0_cacheLine_valid; - wire MmuPlugin_ports_0_cacheLine_exception; - wire MmuPlugin_ports_0_cacheLine_superPage; - wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; - wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; - wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; - wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; - wire MmuPlugin_ports_0_cacheLine_allowRead; - wire MmuPlugin_ports_0_cacheLine_allowWrite; - wire MmuPlugin_ports_0_cacheLine_allowExecute; - wire MmuPlugin_ports_0_cacheLine_allowUser; - reg MmuPlugin_ports_0_entryToReplace_willIncrement; - wire MmuPlugin_ports_0_entryToReplace_willClear; - reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; - reg [1:0] MmuPlugin_ports_0_entryToReplace_value; - wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; - wire MmuPlugin_ports_0_entryToReplace_willOverflow; - reg MmuPlugin_ports_0_requireMmuLockup; - reg MmuPlugin_ports_1_cache_0_valid; - reg MmuPlugin_ports_1_cache_0_exception; - reg MmuPlugin_ports_1_cache_0_superPage; - reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; - reg MmuPlugin_ports_1_cache_0_allowRead; - reg MmuPlugin_ports_1_cache_0_allowWrite; - reg MmuPlugin_ports_1_cache_0_allowExecute; - reg MmuPlugin_ports_1_cache_0_allowUser; - reg MmuPlugin_ports_1_cache_1_valid; - reg MmuPlugin_ports_1_cache_1_exception; - reg MmuPlugin_ports_1_cache_1_superPage; - reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; - reg MmuPlugin_ports_1_cache_1_allowRead; - reg MmuPlugin_ports_1_cache_1_allowWrite; - reg MmuPlugin_ports_1_cache_1_allowExecute; - reg MmuPlugin_ports_1_cache_1_allowUser; - reg MmuPlugin_ports_1_cache_2_valid; - reg MmuPlugin_ports_1_cache_2_exception; - reg MmuPlugin_ports_1_cache_2_superPage; - reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; - reg MmuPlugin_ports_1_cache_2_allowRead; - reg MmuPlugin_ports_1_cache_2_allowWrite; - reg MmuPlugin_ports_1_cache_2_allowExecute; - reg MmuPlugin_ports_1_cache_2_allowUser; - reg MmuPlugin_ports_1_cache_3_valid; - reg MmuPlugin_ports_1_cache_3_exception; - reg MmuPlugin_ports_1_cache_3_superPage; - reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; - reg MmuPlugin_ports_1_cache_3_allowRead; - reg MmuPlugin_ports_1_cache_3_allowWrite; - reg MmuPlugin_ports_1_cache_3_allowExecute; - reg MmuPlugin_ports_1_cache_3_allowUser; - wire MmuPlugin_ports_1_cacheHits_0; - wire MmuPlugin_ports_1_cacheHits_1; - wire MmuPlugin_ports_1_cacheHits_2; - wire MmuPlugin_ports_1_cacheHits_3; - wire MmuPlugin_ports_1_cacheHit; - wire _zz_155_; - wire _zz_156_; - wire [1:0] _zz_157_; - wire MmuPlugin_ports_1_cacheLine_valid; - wire MmuPlugin_ports_1_cacheLine_exception; - wire MmuPlugin_ports_1_cacheLine_superPage; - wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; - wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; - wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; - wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; - wire MmuPlugin_ports_1_cacheLine_allowRead; - wire MmuPlugin_ports_1_cacheLine_allowWrite; - wire MmuPlugin_ports_1_cacheLine_allowExecute; - wire MmuPlugin_ports_1_cacheLine_allowUser; - reg MmuPlugin_ports_1_entryToReplace_willIncrement; - wire MmuPlugin_ports_1_entryToReplace_willClear; - reg [1:0] MmuPlugin_ports_1_entryToReplace_valueNext; - reg [1:0] MmuPlugin_ports_1_entryToReplace_value; - wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; - wire MmuPlugin_ports_1_entryToReplace_willOverflow; - reg MmuPlugin_ports_1_requireMmuLockup; - reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1_; - reg [9:0] MmuPlugin_shared_vpn_0; - reg [9:0] MmuPlugin_shared_vpn_1; - reg [0:0] MmuPlugin_shared_portId; - wire MmuPlugin_shared_dBusRsp_pte_V; - wire MmuPlugin_shared_dBusRsp_pte_R; - wire MmuPlugin_shared_dBusRsp_pte_W; - wire MmuPlugin_shared_dBusRsp_pte_X; - wire MmuPlugin_shared_dBusRsp_pte_U; - wire MmuPlugin_shared_dBusRsp_pte_G; - wire MmuPlugin_shared_dBusRsp_pte_A; - wire MmuPlugin_shared_dBusRsp_pte_D; - wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; - wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; - wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; - wire MmuPlugin_shared_dBusRsp_exception; - wire MmuPlugin_shared_dBusRsp_leaf; - reg MmuPlugin_shared_pteBuffer_V; - reg MmuPlugin_shared_pteBuffer_R; - reg MmuPlugin_shared_pteBuffer_W; - reg MmuPlugin_shared_pteBuffer_X; - reg MmuPlugin_shared_pteBuffer_U; - reg MmuPlugin_shared_pteBuffer_G; - reg MmuPlugin_shared_pteBuffer_A; - reg MmuPlugin_shared_pteBuffer_D; - reg [1:0] MmuPlugin_shared_pteBuffer_RSW; - reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; - reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; - wire [34:0] _zz_158_; - wire _zz_159_; - wire _zz_160_; - wire _zz_161_; - wire _zz_162_; - wire _zz_163_; - wire _zz_164_; - wire `AluCtrlEnum_defaultEncoding_type _zz_165_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_166_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_167_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_168_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_169_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_170_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_171_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_172_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_173_; - reg [31:0] _zz_174_; - wire _zz_175_; - reg [19:0] _zz_176_; - wire _zz_177_; - reg [19:0] _zz_178_; - reg [31:0] _zz_179_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_180_; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_181_; - reg _zz_182_; - reg _zz_183_; - wire _zz_184_; - reg _zz_185_; - reg [4:0] _zz_186_; - reg [31:0] _zz_187_; - wire _zz_188_; - wire _zz_189_; - wire _zz_190_; - wire _zz_191_; - wire _zz_192_; - wire _zz_193_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_194_; - reg _zz_195_; - reg _zz_196_; - wire _zz_197_; - reg [19:0] _zz_198_; - wire _zz_199_; - reg [10:0] _zz_200_; - wire _zz_201_; - reg [18:0] _zz_202_; - reg _zz_203_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_204_; - reg [19:0] _zz_205_; - wire _zz_206_; - reg [10:0] _zz_207_; - wire _zz_208_; - reg [18:0] _zz_209_; - wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] _zz_210_; - wire [1:0] CsrPlugin_misa_base; - wire [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg CsrPlugin_medeleg_IAM; - reg CsrPlugin_medeleg_IAF; - reg CsrPlugin_medeleg_II; - reg CsrPlugin_medeleg_LAM; - reg CsrPlugin_medeleg_LAF; - reg CsrPlugin_medeleg_SAM; - reg CsrPlugin_medeleg_SAF; - reg CsrPlugin_medeleg_EU; - reg CsrPlugin_medeleg_ES; - reg CsrPlugin_medeleg_IPF; - reg CsrPlugin_medeleg_LPF; - reg CsrPlugin_medeleg_SPF; - reg CsrPlugin_mideleg_ST; - reg CsrPlugin_mideleg_SE; - reg CsrPlugin_mideleg_SS; - reg CsrPlugin_sstatus_SIE; - reg CsrPlugin_sstatus_SPIE; - reg [0:0] CsrPlugin_sstatus_SPP; - reg CsrPlugin_sip_SEIP_SOFT; - reg CsrPlugin_sip_SEIP_INPUT; - wire CsrPlugin_sip_SEIP_OR; - reg CsrPlugin_sip_STIP; - reg CsrPlugin_sip_SSIP; - reg CsrPlugin_sie_SEIE; - reg CsrPlugin_sie_STIE; - reg CsrPlugin_sie_SSIE; - reg [1:0] CsrPlugin_stvec_mode; - reg [29:0] CsrPlugin_stvec_base; - reg [31:0] CsrPlugin_sscratch; - reg CsrPlugin_scause_interrupt; - reg [3:0] CsrPlugin_scause_exceptionCode; - reg [31:0] CsrPlugin_stval; - reg [31:0] CsrPlugin_sepc; - reg [21:0] CsrPlugin_satp_PPN; - reg [8:0] CsrPlugin_satp_ASID; - reg [0:0] CsrPlugin_satp_MODE; - wire _zz_211_; - wire _zz_212_; - wire _zz_213_; - wire _zz_214_; - wire _zz_215_; - wire _zz_216_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_217_; - wire _zz_218_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - reg CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - reg execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - reg [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - wire [65:0] writeBack_MulPlugin_result; - reg [32:0] memory_DivPlugin_rs1; - reg [31:0] memory_DivPlugin_rs2; - reg [64:0] memory_DivPlugin_accumulator; - reg memory_DivPlugin_div_needRevert; - reg memory_DivPlugin_div_counter_willIncrement; - reg memory_DivPlugin_div_counter_willClear; - reg [5:0] memory_DivPlugin_div_counter_valueNext; - reg [5:0] memory_DivPlugin_div_counter_value; - wire memory_DivPlugin_div_counter_willOverflowIfInc; - wire memory_DivPlugin_div_counter_willOverflow; - reg memory_DivPlugin_div_done; - reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_219_; - wire [32:0] _zz_220_; - wire [32:0] _zz_221_; - wire [31:0] _zz_222_; - wire _zz_223_; - wire _zz_224_; - reg [32:0] _zz_225_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_226_; - wire [31:0] _zz_227_; - reg [31:0] _zz_228_; - wire [31:0] _zz_229_; - reg [51:0] memory_to_writeBack_MUL_LOW; - reg decode_to_execute_IS_CSR; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_MEMORY_MANAGMENT; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg decode_to_execute_IS_RS2_SIGNED; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg [31:0] execute_to_memory_MUL_LL; - reg [31:0] decode_to_execute_RS2; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg decode_to_execute_MEMORY_AMO; - reg [33:0] execute_to_memory_MUL_HL; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg [33:0] execute_to_memory_MUL_HH; - reg [33:0] memory_to_writeBack_MUL_HH; - reg decode_to_execute_IS_SFENCE_VMA; - reg execute_to_memory_IS_SFENCE_VMA; - reg memory_to_writeBack_IS_SFENCE_VMA; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg execute_to_memory_BRANCH_DO; - reg decode_to_execute_CSR_READ_OPCODE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg execute_to_memory_IS_DBUS_SHARING; - reg memory_to_writeBack_IS_DBUS_SHARING; - reg decode_to_execute_MEMORY_WR; - reg execute_to_memory_MEMORY_WR; - reg memory_to_writeBack_MEMORY_WR; - reg [33:0] execute_to_memory_MUL_LH; - reg decode_to_execute_MEMORY_LRSC; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg memory_to_writeBack_IS_MUL; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg [31:0] decode_to_execute_RS1; - reg decode_to_execute_IS_RS1_SIGNED; - reg [2:0] _zz_230_; - reg _zz_231_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_232_; - wire _zz_233_; - wire _zz_234_; - wire _zz_235_; - wire _zz_236_; - wire _zz_237_; - reg _zz_238_; - reg [31:0] dBusWishbone_DAT_MISO_regNext; - `ifndef SYNTHESIS - reg [31:0] _zz_1__string; - reg [31:0] _zz_2__string; - reg [71:0] _zz_3__string; - reg [71:0] _zz_4__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_5__string; - reg [71:0] _zz_6__string; - reg [71:0] _zz_7__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_8__string; - reg [63:0] _zz_9__string; - reg [63:0] _zz_10__string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_11__string; - reg [95:0] _zz_12__string; - reg [95:0] _zz_13__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_14__string; - reg [39:0] _zz_15__string; - reg [39:0] _zz_16__string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_17__string; - reg [23:0] _zz_18__string; - reg [23:0] _zz_19__string; - reg [39:0] _zz_20__string; - reg [39:0] _zz_21__string; - reg [39:0] _zz_22__string; - reg [39:0] _zz_23__string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_24__string; - reg [39:0] _zz_25__string; - reg [39:0] _zz_26__string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_32__string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_33__string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_36__string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_39__string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_44__string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_46__string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_51__string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_53__string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_56__string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_58__string; - reg [39:0] _zz_67__string; - reg [31:0] _zz_70__string; - reg [39:0] _zz_73__string; - reg [71:0] _zz_77__string; - reg [23:0] _zz_78__string; - reg [95:0] _zz_81__string; - reg [63:0] _zz_82__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_99__string; - reg [47:0] MmuPlugin_shared_state_1__string; - reg [63:0] _zz_165__string; - reg [95:0] _zz_166__string; - reg [23:0] _zz_167__string; - reg [71:0] _zz_168__string; - reg [39:0] _zz_169__string; - reg [31:0] _zz_170__string; - reg [39:0] _zz_171__string; - reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - `endif - - (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_290_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_291_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_292_ = 1'b1; - assign _zz_293_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_294_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_295_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_296_ = ((_zz_244_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_95_)); - assign _zz_297_ = ((_zz_244_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_96_)); - assign _zz_298_ = ((_zz_244_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_97_)); - assign _zz_299_ = ((_zz_244_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); - assign _zz_300_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_301_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_302_ = (! memory_DivPlugin_div_done); - assign _zz_303_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_304_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_305_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_306_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_307_ = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != (3'b000))); - assign _zz_308_ = (! dataCache_1__io_cpu_redo); - assign _zz_309_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_310_ = ((MmuPlugin_dBusAccess_rsp_valid && (! MmuPlugin_dBusAccess_rsp_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); - assign _zz_311_ = (MmuPlugin_shared_portId == (1'b1)); - assign _zz_312_ = (MmuPlugin_shared_portId == (1'b0)); - assign _zz_313_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_314_ = (1'b0 || (! 1'b1)); - assign _zz_315_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_316_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_317_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_318_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_319_ = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_320_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_321_ = execute_INSTRUCTION[13 : 12]; - assign _zz_322_ = (! memory_arbitration_isStuck); - assign _zz_323_ = (iBus_cmd_valid || (_zz_230_ != (3'b000))); - assign _zz_324_ = (_zz_264_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); - assign _zz_325_ = (IBusCachedPlugin_mmuBus_cmd_isValid && IBusCachedPlugin_mmuBus_rsp_refilling); - assign _zz_326_ = (DBusCachedPlugin_mmuBus_cmd_isValid && DBusCachedPlugin_mmuBus_rsp_refilling); - assign _zz_327_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b00)); - assign _zz_328_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b01)); - assign _zz_329_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b10)); - assign _zz_330_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b11)); - assign _zz_331_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b00)); - assign _zz_332_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b01)); - assign _zz_333_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b10)); - assign _zz_334_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b11)); - assign _zz_335_ = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == (2'b01))) || (CsrPlugin_privilege < (2'b01))); - assign _zz_336_ = ((_zz_211_ && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); - assign _zz_337_ = ((_zz_212_ && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); - assign _zz_338_ = ((_zz_213_ && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); - assign _zz_339_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_340_ = ((_zz_211_ && 1'b1) && (! (CsrPlugin_mideleg_ST != (1'b0)))); - assign _zz_341_ = ((_zz_212_ && 1'b1) && (! (CsrPlugin_mideleg_SS != (1'b0)))); - assign _zz_342_ = ((_zz_213_ && 1'b1) && (! (CsrPlugin_mideleg_SE != (1'b0)))); - assign _zz_343_ = ((_zz_214_ && 1'b1) && (! 1'b0)); - assign _zz_344_ = ((_zz_215_ && 1'b1) && (! 1'b0)); - assign _zz_345_ = ((_zz_216_ && 1'b1) && (! 1'b0)); - assign _zz_346_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_347_ = execute_INSTRUCTION[13]; - assign _zz_348_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_349_ = (_zz_105_ - (5'b00001)); - assign _zz_350_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_351_ = {29'd0, _zz_350_}; - assign _zz_352_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_353_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_354_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_355_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_356_ = {{_zz_123_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_357_ = {{_zz_125_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_358_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_359_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_360_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); - assign _zz_361_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); - assign _zz_362_ = MmuPlugin_ports_0_entryToReplace_willIncrement; - assign _zz_363_ = {1'd0, _zz_362_}; - assign _zz_364_ = MmuPlugin_ports_1_entryToReplace_willIncrement; - assign _zz_365_ = {1'd0, _zz_364_}; - assign _zz_366_ = MmuPlugin_dBusAccess_rsp_payload_data[0 : 0]; - assign _zz_367_ = MmuPlugin_dBusAccess_rsp_payload_data[1 : 1]; - assign _zz_368_ = MmuPlugin_dBusAccess_rsp_payload_data[2 : 2]; - assign _zz_369_ = MmuPlugin_dBusAccess_rsp_payload_data[3 : 3]; - assign _zz_370_ = MmuPlugin_dBusAccess_rsp_payload_data[4 : 4]; - assign _zz_371_ = MmuPlugin_dBusAccess_rsp_payload_data[5 : 5]; - assign _zz_372_ = MmuPlugin_dBusAccess_rsp_payload_data[6 : 6]; - assign _zz_373_ = MmuPlugin_dBusAccess_rsp_payload_data[7 : 7]; - assign _zz_374_ = _zz_158_[0 : 0]; - assign _zz_375_ = _zz_158_[1 : 1]; - assign _zz_376_ = _zz_158_[2 : 2]; - assign _zz_377_ = _zz_158_[3 : 3]; - assign _zz_378_ = _zz_158_[4 : 4]; - assign _zz_379_ = _zz_158_[5 : 5]; - assign _zz_380_ = _zz_158_[6 : 6]; - assign _zz_381_ = _zz_158_[7 : 7]; - assign _zz_382_ = _zz_158_[13 : 13]; - assign _zz_383_ = _zz_158_[14 : 14]; - assign _zz_384_ = _zz_158_[19 : 19]; - assign _zz_385_ = _zz_158_[20 : 20]; - assign _zz_386_ = _zz_158_[21 : 21]; - assign _zz_387_ = _zz_158_[24 : 24]; - assign _zz_388_ = _zz_158_[25 : 25]; - assign _zz_389_ = _zz_158_[28 : 28]; - assign _zz_390_ = _zz_158_[29 : 29]; - assign _zz_391_ = _zz_158_[32 : 32]; - assign _zz_392_ = _zz_158_[33 : 33]; - assign _zz_393_ = _zz_158_[34 : 34]; - assign _zz_394_ = execute_SRC_LESS; - assign _zz_395_ = (3'b100); - assign _zz_396_ = execute_INSTRUCTION[19 : 15]; - assign _zz_397_ = execute_INSTRUCTION[31 : 20]; - assign _zz_398_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_399_ = ($signed(_zz_400_) + $signed(_zz_403_)); - assign _zz_400_ = ($signed(_zz_401_) + $signed(_zz_402_)); - assign _zz_401_ = execute_SRC1; - assign _zz_402_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_403_ = (execute_SRC_USE_SUB_LESS ? _zz_404_ : _zz_405_); - assign _zz_404_ = (32'b00000000000000000000000000000001); - assign _zz_405_ = (32'b00000000000000000000000000000000); - assign _zz_406_ = ($signed(_zz_408_) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_407_ = _zz_406_[31 : 0]; - assign _zz_408_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_409_ = execute_INSTRUCTION[31 : 20]; - assign _zz_410_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_411_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_412_ = {_zz_198_,execute_INSTRUCTION[31 : 20]}; - assign _zz_413_ = {{_zz_200_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_414_ = {{_zz_202_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_415_ = execute_INSTRUCTION[31 : 20]; - assign _zz_416_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_417_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_418_ = (3'b100); - assign _zz_419_ = (_zz_217_ & (~ _zz_420_)); - assign _zz_420_ = (_zz_217_ - (2'b01)); - assign _zz_421_ = ($signed(_zz_422_) + $signed(_zz_427_)); - assign _zz_422_ = ($signed(_zz_423_) + $signed(_zz_425_)); - assign _zz_423_ = (52'b0000000000000000000000000000000000000000000000000000); - assign _zz_424_ = {1'b0,memory_MUL_LL}; - assign _zz_425_ = {{19{_zz_424_[32]}}, _zz_424_}; - assign _zz_426_ = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_427_ = {{2{_zz_426_[49]}}, _zz_426_}; - assign _zz_428_ = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_429_ = {{2{_zz_428_[49]}}, _zz_428_}; - assign _zz_430_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_431_ = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_432_ = writeBack_MUL_LOW[31 : 0]; - assign _zz_433_ = writeBack_MulPlugin_result[63 : 32]; - assign _zz_434_ = memory_DivPlugin_div_counter_willIncrement; - assign _zz_435_ = {5'd0, _zz_434_}; - assign _zz_436_ = {1'd0, memory_DivPlugin_rs2}; - assign _zz_437_ = {_zz_219_,(! _zz_221_[32])}; - assign _zz_438_ = _zz_221_[31:0]; - assign _zz_439_ = _zz_220_[31:0]; - assign _zz_440_ = _zz_441_; - assign _zz_441_ = _zz_442_; - assign _zz_442_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_222_) : _zz_222_)} + _zz_444_); - assign _zz_443_ = memory_DivPlugin_div_needRevert; - assign _zz_444_ = {32'd0, _zz_443_}; - assign _zz_445_ = _zz_224_; - assign _zz_446_ = {32'd0, _zz_445_}; - assign _zz_447_ = _zz_223_; - assign _zz_448_ = {31'd0, _zz_447_}; - assign _zz_449_ = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_450_ = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_451_ = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_452_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_453_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_454_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_455_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_456_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_457_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_458_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_459_ = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_460_ = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_461_ = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_462_ = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_463_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_464_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_465_ = execute_CsrPlugin_writeData[8 : 8]; - assign _zz_466_ = execute_CsrPlugin_writeData[2 : 2]; - assign _zz_467_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_468_ = execute_CsrPlugin_writeData[13 : 13]; - assign _zz_469_ = execute_CsrPlugin_writeData[4 : 4]; - assign _zz_470_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_471_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_472_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_473_ = execute_CsrPlugin_writeData[12 : 12]; - assign _zz_474_ = execute_CsrPlugin_writeData[15 : 15]; - assign _zz_475_ = execute_CsrPlugin_writeData[6 : 6]; - assign _zz_476_ = execute_CsrPlugin_writeData[0 : 0]; - assign _zz_477_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_478_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_479_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_480_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_481_ = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_482_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_483_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_484_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_485_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_486_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_487_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_488_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_489_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_490_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_491_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_492_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_493_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_494_ = (iBus_cmd_payload_address >>> 5); - assign _zz_495_ = 1'b1; - assign _zz_496_ = 1'b1; - assign _zz_497_ = {_zz_108_,{_zz_110_,_zz_109_}}; - assign _zz_498_ = decode_INSTRUCTION[31]; - assign _zz_499_ = decode_INSTRUCTION[31]; - assign _zz_500_ = decode_INSTRUCTION[7]; - assign _zz_501_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000000)); - assign _zz_502_ = (32'b00000000000000000000000001000000); - assign _zz_503_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000100000)) == (32'b00000000000000000100000000100000)); - assign _zz_504_ = ((decode_INSTRUCTION & _zz_514_) == (32'b00000000000000000000000000010000)); - assign _zz_505_ = {_zz_159_,(_zz_515_ == _zz_516_)}; - assign _zz_506_ = (decode_INSTRUCTION & (32'b00000000000000000100000001001000)); - assign _zz_507_ = (32'b00000000000000000100000000001000); - assign _zz_508_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001110100)) == (32'b00000010000000000000000000110000)); - assign _zz_509_ = ((decode_INSTRUCTION & _zz_517_) == (32'b00000000000000000001000000000000)); - assign _zz_510_ = (1'b0); - assign _zz_511_ = ((_zz_518_ == _zz_519_) != (1'b0)); - assign _zz_512_ = (_zz_164_ != (1'b0)); - assign _zz_513_ = {(_zz_520_ != _zz_521_),{_zz_522_,{_zz_523_,_zz_524_}}}; - assign _zz_514_ = (32'b00000000000000000000000000110000); - assign _zz_515_ = (decode_INSTRUCTION & (32'b00000010000000000000000000101000)); - assign _zz_516_ = (32'b00000000000000000000000000100000); - assign _zz_517_ = (32'b00000000000000000001000000000000); - assign _zz_518_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000)); - assign _zz_519_ = (32'b00000000000000000010000000000000); - assign _zz_520_ = {((decode_INSTRUCTION & _zz_525_) == (32'b00000000000000000000000001000000)),{(_zz_526_ == _zz_527_),(_zz_528_ == _zz_529_)}}; - assign _zz_521_ = (3'b000); - assign _zz_522_ = ({_zz_162_,(_zz_530_ == _zz_531_)} != (2'b00)); - assign _zz_523_ = ((_zz_532_ == _zz_533_) != (1'b0)); - assign _zz_524_ = {(_zz_164_ != (1'b0)),{(_zz_534_ != _zz_535_),{_zz_536_,{_zz_537_,_zz_538_}}}}; - assign _zz_525_ = (32'b00000000000000000000000001000100); - assign _zz_526_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); - assign _zz_527_ = (32'b00000000000000000010000000010000); - assign _zz_528_ = (decode_INSTRUCTION & (32'b01000000000000000000000000110100)); - assign _zz_529_ = (32'b01000000000000000000000000110000); - assign _zz_530_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100)); - assign _zz_531_ = (32'b00000000000000000000000000000100); - assign _zz_532_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_533_ = (32'b00000000000000000000000001000000); - assign _zz_534_ = ((decode_INSTRUCTION & (32'b00010000000000000000000000001000)) == (32'b00010000000000000000000000001000)); - assign _zz_535_ = (1'b0); - assign _zz_536_ = (((decode_INSTRUCTION & _zz_539_) == (32'b00000000000000000000000001010000)) != (1'b0)); - assign _zz_537_ = ((_zz_540_ == _zz_541_) != (1'b0)); - assign _zz_538_ = {({_zz_542_,_zz_543_} != (7'b0000000)),{(_zz_544_ != _zz_545_),{_zz_546_,{_zz_547_,_zz_548_}}}}; - assign _zz_539_ = (32'b00000010001000000011000001010000); - assign _zz_540_ = (decode_INSTRUCTION & (32'b00000010010000000011000001010000)); - assign _zz_541_ = (32'b00000000000000000000000001010000); - assign _zz_542_ = _zz_162_; - assign _zz_543_ = {(_zz_549_ == _zz_550_),{_zz_551_,{_zz_552_,_zz_553_}}}; - assign _zz_544_ = {(_zz_554_ == _zz_555_),{_zz_556_,{_zz_557_,_zz_558_}}}; - assign _zz_545_ = (5'b00000); - assign _zz_546_ = ((_zz_559_ == _zz_560_) != (1'b0)); - assign _zz_547_ = ({_zz_561_,_zz_562_} != (2'b00)); - assign _zz_548_ = {(_zz_563_ != _zz_564_),{_zz_565_,{_zz_566_,_zz_567_}}}; - assign _zz_549_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); - assign _zz_550_ = (32'b00000000000000000001000000010000); - assign _zz_551_ = ((decode_INSTRUCTION & _zz_568_) == (32'b00000000000000000010000000010000)); - assign _zz_552_ = (_zz_569_ == _zz_570_); - assign _zz_553_ = {_zz_571_,{_zz_572_,_zz_573_}}; - assign _zz_554_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_555_ = (32'b00000000000000000000000000000000); - assign _zz_556_ = ((decode_INSTRUCTION & _zz_574_) == (32'b00000000000000000000000000000000)); - assign _zz_557_ = (_zz_575_ == _zz_576_); - assign _zz_558_ = {_zz_577_,_zz_160_}; - assign _zz_559_ = (decode_INSTRUCTION & (32'b00000010000000000011000001010000)); - assign _zz_560_ = (32'b00000010000000000000000001010000); - assign _zz_561_ = (_zz_578_ == _zz_579_); - assign _zz_562_ = (_zz_580_ == _zz_581_); - assign _zz_563_ = {_zz_582_,{_zz_583_,_zz_584_}}; - assign _zz_564_ = (3'b000); - assign _zz_565_ = ({_zz_585_,_zz_586_} != (2'b00)); - assign _zz_566_ = (_zz_587_ != _zz_588_); - assign _zz_567_ = {_zz_589_,{_zz_590_,_zz_591_}}; - assign _zz_568_ = (32'b00000000000000000010000000010000); - assign _zz_569_ = (decode_INSTRUCTION & (32'b00000000000000000010000000001000)); - assign _zz_570_ = (32'b00000000000000000010000000001000); - assign _zz_571_ = ((decode_INSTRUCTION & _zz_592_) == (32'b00000000000000000000000000010000)); - assign _zz_572_ = _zz_159_; - assign _zz_573_ = (_zz_593_ == _zz_594_); - assign _zz_574_ = (32'b00000000000000000000000000011000); - assign _zz_575_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); - assign _zz_576_ = (32'b00000000000000000010000000000000); - assign _zz_577_ = ((decode_INSTRUCTION & _zz_595_) == (32'b00000000000000000001000000000000)); - assign _zz_578_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_579_ = (32'b00000000000000000101000000010000); - assign _zz_580_ = (decode_INSTRUCTION & (32'b00000010000000000111000001100100)); - assign _zz_581_ = (32'b00000000000000000101000000100000); - assign _zz_582_ = ((decode_INSTRUCTION & _zz_596_) == (32'b01000000000000000001000000010000)); - assign _zz_583_ = (_zz_597_ == _zz_598_); - assign _zz_584_ = (_zz_599_ == _zz_600_); - assign _zz_585_ = _zz_163_; - assign _zz_586_ = (_zz_601_ == _zz_602_); - assign _zz_587_ = {_zz_163_,_zz_603_}; - assign _zz_588_ = (2'b00); - assign _zz_589_ = ({_zz_604_,_zz_605_} != (3'b000)); - assign _zz_590_ = (_zz_606_ != _zz_607_); - assign _zz_591_ = {_zz_608_,{_zz_609_,_zz_610_}}; - assign _zz_592_ = (32'b00000000000000000000000001010000); - assign _zz_593_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); - assign _zz_594_ = (32'b00000000000000000000000000000000); - assign _zz_595_ = (32'b00000000000000000101000000000100); - assign _zz_596_ = (32'b01000000000000000011000001010100); - assign _zz_597_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_598_ = (32'b00000000000000000001000000010000); - assign _zz_599_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100)); - assign _zz_600_ = (32'b00000000000000000001000000010000); - assign _zz_601_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); - assign _zz_602_ = (32'b00000000000000000000000000100000); - assign _zz_603_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); - assign _zz_604_ = ((decode_INSTRUCTION & _zz_611_) == (32'b00001000000000000000000000100000)); - assign _zz_605_ = {(_zz_612_ == _zz_613_),(_zz_614_ == _zz_615_)}; - assign _zz_606_ = {(_zz_616_ == _zz_617_),(_zz_618_ == _zz_619_)}; - assign _zz_607_ = (2'b00); - assign _zz_608_ = ({_zz_620_,{_zz_621_,_zz_622_}} != (6'b000000)); - assign _zz_609_ = ({_zz_623_,_zz_624_} != (3'b000)); - assign _zz_610_ = {(_zz_625_ != _zz_626_),{_zz_627_,{_zz_628_,_zz_629_}}}; - assign _zz_611_ = (32'b00001000000000000000000000100000); - assign _zz_612_ = (decode_INSTRUCTION & (32'b00010000000000000000000000100000)); - assign _zz_613_ = (32'b00000000000000000000000000100000); - assign _zz_614_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); - assign _zz_615_ = (32'b00000000000000000000000000100000); - assign _zz_616_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); - assign _zz_617_ = (32'b00000000000000000001000001010000); - assign _zz_618_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); - assign _zz_619_ = (32'b00000000000000000010000001010000); - assign _zz_620_ = ((decode_INSTRUCTION & _zz_630_) == (32'b00000000000000000010000001000000)); - assign _zz_621_ = (_zz_631_ == _zz_632_); - assign _zz_622_ = {_zz_633_,{_zz_634_,_zz_635_}}; - assign _zz_623_ = _zz_162_; - assign _zz_624_ = {_zz_161_,_zz_636_}; - assign _zz_625_ = {_zz_161_,_zz_637_}; - assign _zz_626_ = (2'b00); - assign _zz_627_ = (_zz_638_ != (1'b0)); - assign _zz_628_ = (_zz_639_ != _zz_640_); - assign _zz_629_ = {_zz_641_,{_zz_642_,_zz_643_}}; - assign _zz_630_ = (32'b00000000000000000010000001000000); - assign _zz_631_ = (decode_INSTRUCTION & (32'b00000000000000000001000001000000)); - assign _zz_632_ = (32'b00000000000000000001000001000000); - assign _zz_633_ = ((decode_INSTRUCTION & _zz_644_) == (32'b00000000000000000000000001000000)); - assign _zz_634_ = (_zz_645_ == _zz_646_); - assign _zz_635_ = {_zz_647_,_zz_648_}; - assign _zz_636_ = ((decode_INSTRUCTION & _zz_649_) == (32'b00000000000000000000000000000100)); - assign _zz_637_ = ((decode_INSTRUCTION & _zz_650_) == (32'b00000000000000000000000000000100)); - assign _zz_638_ = ((decode_INSTRUCTION & _zz_651_) == (32'b00000000000000000100000000010000)); - assign _zz_639_ = (_zz_652_ == _zz_653_); - assign _zz_640_ = (1'b0); - assign _zz_641_ = ({_zz_654_,_zz_655_} != (2'b00)); - assign _zz_642_ = (_zz_656_ != _zz_657_); - assign _zz_643_ = {_zz_658_,{_zz_659_,_zz_660_}}; - assign _zz_644_ = (32'b00000000000000000000000001010000); - assign _zz_645_ = (decode_INSTRUCTION & (32'b00000010010000000000000001000000)); - assign _zz_646_ = (32'b00000000000000000000000001000000); - assign _zz_647_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000111000)) == (32'b00000000000000000000000000000000)); - assign _zz_648_ = ((decode_INSTRUCTION & (32'b00011000000000000010000000001000)) == (32'b00010000000000000010000000001000)); - assign _zz_649_ = (32'b00000000000000000010000000010100); - assign _zz_650_ = (32'b00000000000000000000000001001100); - assign _zz_651_ = (32'b00000000000000000100000000010100); - assign _zz_652_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); - assign _zz_653_ = (32'b00000000000000000010000000010000); - assign _zz_654_ = _zz_160_; - assign _zz_655_ = ((decode_INSTRUCTION & _zz_661_) == (32'b00000000000000000000000000000000)); - assign _zz_656_ = ((decode_INSTRUCTION & _zz_662_) == (32'b00000010000000000100000000100000)); - assign _zz_657_ = (1'b0); - assign _zz_658_ = ((_zz_663_ == _zz_664_) != (1'b0)); - assign _zz_659_ = ({_zz_665_,_zz_666_} != (4'b0000)); - assign _zz_660_ = {(_zz_667_ != _zz_668_),{_zz_669_,{_zz_670_,_zz_671_}}}; - assign _zz_661_ = (32'b00000000000000000000000001011000); - assign _zz_662_ = (32'b00000010000000000100000001100100); - assign _zz_663_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_664_ = (32'b00000000000000000000000000100100); - assign _zz_665_ = ((decode_INSTRUCTION & _zz_672_) == (32'b00000000000000000000000000100000)); - assign _zz_666_ = {(_zz_673_ == _zz_674_),{_zz_675_,_zz_676_}}; - assign _zz_667_ = {_zz_159_,{_zz_677_,{_zz_678_,_zz_679_}}}; - assign _zz_668_ = (5'b00000); - assign _zz_669_ = ((_zz_680_ == _zz_681_) != (1'b0)); - assign _zz_670_ = ({_zz_682_,_zz_683_} != (2'b00)); - assign _zz_671_ = (_zz_684_ != (1'b0)); - assign _zz_672_ = (32'b00000000000000000000000000110100); - assign _zz_673_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_674_ = (32'b00000000000000000000000000100000); - assign _zz_675_ = ((decode_INSTRUCTION & (32'b00001000000000000000000001110000)) == (32'b00001000000000000000000000100000)); - assign _zz_676_ = ((decode_INSTRUCTION & (32'b00010000000000000000000001110000)) == (32'b00000000000000000000000000100000)); - assign _zz_677_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000110000)) == (32'b00000000000000000010000000010000)); - assign _zz_678_ = ((decode_INSTRUCTION & _zz_685_) == (32'b00000000000000000000000000010000)); - assign _zz_679_ = {(_zz_686_ == _zz_687_),(_zz_688_ == _zz_689_)}; - assign _zz_680_ = (decode_INSTRUCTION & (32'b00010000000000000000000000001000)); - assign _zz_681_ = (32'b00000000000000000000000000001000); - assign _zz_682_ = ((decode_INSTRUCTION & _zz_690_) == (32'b00000000000000000010000000000000)); - assign _zz_683_ = ((decode_INSTRUCTION & _zz_691_) == (32'b00000000000000000001000000000000)); - assign _zz_684_ = ((decode_INSTRUCTION & (32'b00000000000000000101000001001000)) == (32'b00000000000000000001000000001000)); - assign _zz_685_ = (32'b00000000000000000001000000110000); - assign _zz_686_ = (decode_INSTRUCTION & (32'b00000010000000000011000000100000)); - assign _zz_687_ = (32'b00000000000000000000000000100000); - assign _zz_688_ = (decode_INSTRUCTION & (32'b00000010000000000010000001101000)); - assign _zz_689_ = (32'b00000000000000000010000000100000); - assign _zz_690_ = (32'b00000000000000000010000000010000); - assign _zz_691_ = (32'b00000000000000000101000000000000); - assign _zz_692_ = (32'b00000000000000000001000001111111); - assign _zz_693_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_694_ = (32'b00000000000000000010000001110011); - assign _zz_695_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_696_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_697_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_698_) == (32'b00000000000000000000000000000011)),{(_zz_699_ == _zz_700_),{_zz_701_,{_zz_702_,_zz_703_}}}}}}; - assign _zz_698_ = (32'b00000000000000000101000001011111); - assign _zz_699_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_700_ = (32'b00000000000000000000000001100011); - assign _zz_701_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_702_ = ((decode_INSTRUCTION & (32'b00011000000000000111000001111111)) == (32'b00000000000000000010000000101111)); - assign _zz_703_ = {((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & (32'b11101000000000000111000001111111)) == (32'b00001000000000000010000000101111)),{((decode_INSTRUCTION & _zz_704_) == (32'b00000000000000000101000000001111)),{(_zz_705_ == _zz_706_),{_zz_707_,{_zz_708_,_zz_709_}}}}}}; - assign _zz_704_ = (32'b00000001111100000111000001111111); - assign _zz_705_ = (decode_INSTRUCTION & (32'b10111100000000000111000001111111)); - assign _zz_706_ = (32'b00000000000000000101000000010011); - assign _zz_707_ = ((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)); - assign _zz_708_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000101000000110011)); - assign _zz_709_ = {((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & (32'b11111001111100000111000001111111)) == (32'b00010000000000000010000000101111)),{((decode_INSTRUCTION & _zz_710_) == (32'b00010010000000000000000001110011)),{(_zz_711_ == _zz_712_),{_zz_713_,_zz_714_}}}}}; - assign _zz_710_ = (32'b11111110000000000111111111111111); - assign _zz_711_ = (decode_INSTRUCTION & (32'b11011111111111111111111111111111)); - assign _zz_712_ = (32'b00010000001000000000000001110011); - assign _zz_713_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); - assign _zz_714_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011)); - assign _zz_715_ = execute_INSTRUCTION[31]; - assign _zz_716_ = execute_INSTRUCTION[31]; - assign _zz_717_ = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_61_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_495_) begin - _zz_265_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_496_) begin - _zz_266_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_239_), - .io_cpu_prefetch_isValid(_zz_240_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_241_), - .io_cpu_fetch_isStuck(_zz_242_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_243_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_244_), - .io_cpu_decode_isStuck(_zz_245_), - .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), - .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), - .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), - .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), - .io_cpu_decode_isUser(_zz_246_), - .io_cpu_fill_valid(_zz_247_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); - DataCache dataCache_1_ ( - .io_cpu_execute_isValid(_zz_248_), - .io_cpu_execute_address(_zz_249_), - .io_cpu_execute_args_wr(_zz_250_), - .io_cpu_execute_args_data(_zz_251_), - .io_cpu_execute_args_size(_zz_252_), - .io_cpu_execute_args_isLrsc(_zz_253_), - .io_cpu_execute_args_isAmo(_zz_254_), - .io_cpu_execute_args_amoCtrl_swap(_zz_255_), - .io_cpu_execute_args_amoCtrl_alu(_zz_256_), - .io_cpu_memory_isValid(_zz_257_), - .io_cpu_memory_isStuck(memory_arbitration_isStuck), - .io_cpu_memory_isRemoved(memory_arbitration_removeIt), - .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), - .io_cpu_memory_address(_zz_258_), - .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), - .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), - .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), - .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_259_), - .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), - .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), - .io_cpu_writeBack_isValid(_zz_260_), - .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), - .io_cpu_writeBack_isUser(_zz_261_), - .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), - .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), - .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), - .io_cpu_writeBack_address(_zz_262_), - .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), - .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), - .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), - .io_cpu_writeBack_clearLrsc(contextSwitching), - .io_cpu_redo(dataCache_1__io_cpu_redo), - .io_cpu_flush_valid(_zz_263_), - .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), - .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), - .io_mem_cmd_ready(_zz_264_), - .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), - .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), - .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), - .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), - .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), - .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), - .io_mem_rsp_valid(dBus_rsp_valid), - .io_mem_rsp_payload_data(dBus_rsp_payload_data), - .io_mem_rsp_payload_error(dBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); - always @(*) begin - case(_zz_497_) - 3'b000 : begin - _zz_267_ = DBusCachedPlugin_redoBranch_payload; - end - 3'b001 : begin - _zz_267_ = CsrPlugin_jumpInterface_payload; - end - 3'b010 : begin - _zz_267_ = BranchPlugin_jumpInterface_payload; - end - 3'b011 : begin - _zz_267_ = IBusCachedPlugin_redoBranch_payload; - end - default : begin - _zz_267_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - endcase - end - always @(*) begin - case(_zz_154_) - 2'b00 : begin - _zz_268_ = MmuPlugin_ports_0_cache_0_valid; - _zz_269_ = MmuPlugin_ports_0_cache_0_exception; - _zz_270_ = MmuPlugin_ports_0_cache_0_superPage; - _zz_271_ = MmuPlugin_ports_0_cache_0_virtualAddress_0; - _zz_272_ = MmuPlugin_ports_0_cache_0_virtualAddress_1; - _zz_273_ = MmuPlugin_ports_0_cache_0_physicalAddress_0; - _zz_274_ = MmuPlugin_ports_0_cache_0_physicalAddress_1; - _zz_275_ = MmuPlugin_ports_0_cache_0_allowRead; - _zz_276_ = MmuPlugin_ports_0_cache_0_allowWrite; - _zz_277_ = MmuPlugin_ports_0_cache_0_allowExecute; - _zz_278_ = MmuPlugin_ports_0_cache_0_allowUser; - end - 2'b01 : begin - _zz_268_ = MmuPlugin_ports_0_cache_1_valid; - _zz_269_ = MmuPlugin_ports_0_cache_1_exception; - _zz_270_ = MmuPlugin_ports_0_cache_1_superPage; - _zz_271_ = MmuPlugin_ports_0_cache_1_virtualAddress_0; - _zz_272_ = MmuPlugin_ports_0_cache_1_virtualAddress_1; - _zz_273_ = MmuPlugin_ports_0_cache_1_physicalAddress_0; - _zz_274_ = MmuPlugin_ports_0_cache_1_physicalAddress_1; - _zz_275_ = MmuPlugin_ports_0_cache_1_allowRead; - _zz_276_ = MmuPlugin_ports_0_cache_1_allowWrite; - _zz_277_ = MmuPlugin_ports_0_cache_1_allowExecute; - _zz_278_ = MmuPlugin_ports_0_cache_1_allowUser; - end - 2'b10 : begin - _zz_268_ = MmuPlugin_ports_0_cache_2_valid; - _zz_269_ = MmuPlugin_ports_0_cache_2_exception; - _zz_270_ = MmuPlugin_ports_0_cache_2_superPage; - _zz_271_ = MmuPlugin_ports_0_cache_2_virtualAddress_0; - _zz_272_ = MmuPlugin_ports_0_cache_2_virtualAddress_1; - _zz_273_ = MmuPlugin_ports_0_cache_2_physicalAddress_0; - _zz_274_ = MmuPlugin_ports_0_cache_2_physicalAddress_1; - _zz_275_ = MmuPlugin_ports_0_cache_2_allowRead; - _zz_276_ = MmuPlugin_ports_0_cache_2_allowWrite; - _zz_277_ = MmuPlugin_ports_0_cache_2_allowExecute; - _zz_278_ = MmuPlugin_ports_0_cache_2_allowUser; - end - default : begin - _zz_268_ = MmuPlugin_ports_0_cache_3_valid; - _zz_269_ = MmuPlugin_ports_0_cache_3_exception; - _zz_270_ = MmuPlugin_ports_0_cache_3_superPage; - _zz_271_ = MmuPlugin_ports_0_cache_3_virtualAddress_0; - _zz_272_ = MmuPlugin_ports_0_cache_3_virtualAddress_1; - _zz_273_ = MmuPlugin_ports_0_cache_3_physicalAddress_0; - _zz_274_ = MmuPlugin_ports_0_cache_3_physicalAddress_1; - _zz_275_ = MmuPlugin_ports_0_cache_3_allowRead; - _zz_276_ = MmuPlugin_ports_0_cache_3_allowWrite; - _zz_277_ = MmuPlugin_ports_0_cache_3_allowExecute; - _zz_278_ = MmuPlugin_ports_0_cache_3_allowUser; - end + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; endcase end - always @(*) begin - case(_zz_157_) - 2'b00 : begin - _zz_279_ = MmuPlugin_ports_1_cache_0_valid; - _zz_280_ = MmuPlugin_ports_1_cache_0_exception; - _zz_281_ = MmuPlugin_ports_1_cache_0_superPage; - _zz_282_ = MmuPlugin_ports_1_cache_0_virtualAddress_0; - _zz_283_ = MmuPlugin_ports_1_cache_0_virtualAddress_1; - _zz_284_ = MmuPlugin_ports_1_cache_0_physicalAddress_0; - _zz_285_ = MmuPlugin_ports_1_cache_0_physicalAddress_1; - _zz_286_ = MmuPlugin_ports_1_cache_0_allowRead; - _zz_287_ = MmuPlugin_ports_1_cache_0_allowWrite; - _zz_288_ = MmuPlugin_ports_1_cache_0_allowExecute; - _zz_289_ = MmuPlugin_ports_1_cache_0_allowUser; - end - 2'b01 : begin - _zz_279_ = MmuPlugin_ports_1_cache_1_valid; - _zz_280_ = MmuPlugin_ports_1_cache_1_exception; - _zz_281_ = MmuPlugin_ports_1_cache_1_superPage; - _zz_282_ = MmuPlugin_ports_1_cache_1_virtualAddress_0; - _zz_283_ = MmuPlugin_ports_1_cache_1_virtualAddress_1; - _zz_284_ = MmuPlugin_ports_1_cache_1_physicalAddress_0; - _zz_285_ = MmuPlugin_ports_1_cache_1_physicalAddress_1; - _zz_286_ = MmuPlugin_ports_1_cache_1_allowRead; - _zz_287_ = MmuPlugin_ports_1_cache_1_allowWrite; - _zz_288_ = MmuPlugin_ports_1_cache_1_allowExecute; - _zz_289_ = MmuPlugin_ports_1_cache_1_allowUser; - end - 2'b10 : begin - _zz_279_ = MmuPlugin_ports_1_cache_2_valid; - _zz_280_ = MmuPlugin_ports_1_cache_2_exception; - _zz_281_ = MmuPlugin_ports_1_cache_2_superPage; - _zz_282_ = MmuPlugin_ports_1_cache_2_virtualAddress_0; - _zz_283_ = MmuPlugin_ports_1_cache_2_virtualAddress_1; - _zz_284_ = MmuPlugin_ports_1_cache_2_physicalAddress_0; - _zz_285_ = MmuPlugin_ports_1_cache_2_physicalAddress_1; - _zz_286_ = MmuPlugin_ports_1_cache_2_allowRead; - _zz_287_ = MmuPlugin_ports_1_cache_2_allowWrite; - _zz_288_ = MmuPlugin_ports_1_cache_2_allowExecute; - _zz_289_ = MmuPlugin_ports_1_cache_2_allowUser; - end - default : begin - _zz_279_ = MmuPlugin_ports_1_cache_3_valid; - _zz_280_ = MmuPlugin_ports_1_cache_3_exception; - _zz_281_ = MmuPlugin_ports_1_cache_3_superPage; - _zz_282_ = MmuPlugin_ports_1_cache_3_virtualAddress_0; - _zz_283_ = MmuPlugin_ports_1_cache_3_virtualAddress_1; - _zz_284_ = MmuPlugin_ports_1_cache_3_physicalAddress_0; - _zz_285_ = MmuPlugin_ports_1_cache_3_physicalAddress_1; - _zz_286_ = MmuPlugin_ports_1_cache_3_allowRead; - _zz_287_ = MmuPlugin_ports_1_cache_3_allowWrite; - _zz_288_ = MmuPlugin_ports_1_cache_3_allowExecute; - _zz_289_ = MmuPlugin_ports_1_cache_3_allowUser; - end + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; endcase end - - `ifndef SYNTHESIS always @(*) begin - case(_zz_1_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_1__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_1__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_1__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_1__string = "JALR"; - default : _zz_1__string = "????"; + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_2__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_2__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_2__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_2__string = "JALR"; - default : _zz_2__string = "????"; - endcase - end - always @(*) begin - case(_zz_3_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_3__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_3__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_3__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_3__string = "SRA_1 "; - default : _zz_3__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_4_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_4__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_4__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_4__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_4__string = "SRA_1 "; - default : _zz_4__string = "?????????"; - endcase - end - always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_5_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_5__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_5__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_5__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_5__string = "SRA_1 "; - default : _zz_5__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_6_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_6__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_6__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_6__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_6__string = "SRA_1 "; - default : _zz_6__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_7_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_7__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_7__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_7__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_7__string = "SRA_1 "; - default : _zz_7__string = "?????????"; - endcase - end - always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_8_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_8__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_8__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_8__string = "BITWISE "; - default : _zz_8__string = "????????"; - endcase - end - always @(*) begin - case(_zz_9_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_9__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_9__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_9__string = "BITWISE "; - default : _zz_9__string = "????????"; - endcase - end - always @(*) begin - case(_zz_10_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10__string = "BITWISE "; - default : _zz_10__string = "????????"; - endcase - end - always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_11_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_11__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_11__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_11__string = "URS1 "; - default : _zz_11__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_12_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 "; - default : _zz_12__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_13_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 "; - default : _zz_13__string = "????????????"; - endcase - end - always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_14_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14__string = "AND_1"; - default : _zz_14__string = "?????"; - endcase - end - always @(*) begin - case(_zz_15_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15__string = "AND_1"; - default : _zz_15__string = "?????"; - endcase - end - always @(*) begin - case(_zz_16_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16__string = "AND_1"; - default : _zz_16__string = "?????"; - endcase - end - always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_17_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_17__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_17__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_17__string = "PC "; - default : _zz_17__string = "???"; - endcase - end - always @(*) begin - case(_zz_18_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18__string = "PC "; - default : _zz_18__string = "???"; - endcase - end - always @(*) begin - case(_zz_19_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19__string = "PC "; - default : _zz_19__string = "???"; - endcase - end - always @(*) begin - case(_zz_20_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_20__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_20__string = "ECALL"; - default : _zz_20__string = "?????"; - endcase - end - always @(*) begin - case(_zz_21_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_21__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_21__string = "ECALL"; - default : _zz_21__string = "?????"; - endcase - end - always @(*) begin - case(_zz_22_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_22__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_22__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_22__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_22__string = "ECALL"; - default : _zz_22__string = "?????"; - endcase - end - always @(*) begin - case(_zz_23_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_23__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_23__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_23__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_23__string = "ECALL"; - default : _zz_23__string = "?????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_24_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_24__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_24__string = "ECALL"; - default : _zz_24__string = "?????"; - endcase - end - always @(*) begin - case(_zz_25_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_25__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25__string = "ECALL"; - default : _zz_25__string = "?????"; - endcase - end - always @(*) begin - case(_zz_26_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_26__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL"; - default : _zz_26__string = "?????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_32_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_32__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_32__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_32__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32__string = "ECALL"; - default : _zz_32__string = "?????"; + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; endcase end always @(*) begin @@ -3753,12 +2732,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_33_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33__string = "ECALL"; - default : _zz_33__string = "?????"; + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; endcase end always @(*) begin @@ -3771,12 +2750,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_36_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_36__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_36__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_36__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_36__string = "ECALL"; - default : _zz_36__string = "?????"; + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; endcase end always @(*) begin @@ -3789,12 +2768,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_39_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_39__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_39__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_39__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_39__string = "JALR"; - default : _zz_39__string = "????"; + case(_zz_30) + `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; + default : _zz_30_string = "????"; endcase end always @(*) begin @@ -3807,12 +2786,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_44_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_44__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_44__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_44__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_44__string = "SRA_1 "; - default : _zz_44__string = "?????????"; + case(_zz_33) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; + default : _zz_33_string = "?????????"; endcase end always @(*) begin @@ -3825,12 +2804,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_46_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46__string = "SRA_1 "; - default : _zz_46__string = "?????????"; + case(_zz_34) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; + default : _zz_34_string = "?????????"; endcase end always @(*) begin @@ -3843,12 +2822,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_51_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_51__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_51__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_51__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_51__string = "PC "; - default : _zz_51__string = "???"; + case(_zz_36) + `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; + default : _zz_36_string = "???"; endcase end always @(*) begin @@ -3861,12 +2840,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_53_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_53__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_53__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_53__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_53__string = "URS1 "; - default : _zz_53__string = "????????????"; + case(_zz_37) + `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; + default : _zz_37_string = "????????????"; endcase end always @(*) begin @@ -3878,11 +2857,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_56_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; - default : _zz_56__string = "????????"; + case(_zz_38) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; + default : _zz_38_string = "????????"; endcase end always @(*) begin @@ -3894,72 +2873,72 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_58_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; - default : _zz_58__string = "?????"; + case(_zz_39) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; + default : _zz_39_string = "?????"; endcase end always @(*) begin - case(_zz_67_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_67__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_67__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_67__string = "AND_1"; - default : _zz_67__string = "?????"; + case(_zz_43) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_70_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_70__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_70__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_70__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_70__string = "JALR"; - default : _zz_70__string = "????"; + case(_zz_44) + `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; + default : _zz_44_string = "????"; endcase end always @(*) begin - case(_zz_73_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_73__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_73__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_73__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_73__string = "ECALL"; - default : _zz_73__string = "?????"; + case(_zz_45) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; + default : _zz_45_string = "?????????"; endcase end always @(*) begin - case(_zz_77_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_77__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_77__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_77__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_77__string = "SRA_1 "; - default : _zz_77__string = "?????????"; + case(_zz_46) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; + default : _zz_46_string = "?????"; endcase end always @(*) begin - case(_zz_78_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_78__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_78__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_78__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_78__string = "PC "; - default : _zz_78__string = "???"; + case(_zz_47) + `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; + default : _zz_47_string = "???"; endcase end always @(*) begin - case(_zz_81_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_81__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_81__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_81__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_81__string = "URS1 "; - default : _zz_81__string = "????????????"; + case(_zz_48) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; + default : _zz_48_string = "????????"; endcase end always @(*) begin - case(_zz_82_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_82__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_82__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_82__string = "BITWISE "; - default : _zz_82__string = "????????"; + case(_zz_49) + `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; + default : _zz_49_string = "????????????"; endcase end always @(*) begin @@ -3972,110 +2951,100 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_99_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_99__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_99__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_99__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_99__string = "JALR"; - default : _zz_99__string = "????"; + case(_zz_52) + `BranchCtrlEnum_defaultEncoding_INC : _zz_52_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_52_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_52_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_52_string = "JALR"; + default : _zz_52_string = "????"; endcase end always @(*) begin - case(MmuPlugin_shared_state_1_) - `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1__string = "IDLE "; - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1__string = "L1_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1__string = "L1_RSP"; - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1__string = "L0_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1__string = "L0_RSP"; - default : MmuPlugin_shared_state_1__string = "??????"; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; + default : MmuPlugin_shared_state_1_string = "??????"; endcase end always @(*) begin - case(_zz_165_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_165__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_165__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_165__string = "BITWISE "; - default : _zz_165__string = "????????"; + case(_zz_110) + `Src1CtrlEnum_defaultEncoding_RS : _zz_110_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_110_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_110_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_110_string = "URS1 "; + default : _zz_110_string = "????????????"; endcase end always @(*) begin - case(_zz_166_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_166__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_166__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_166__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_166__string = "URS1 "; - default : _zz_166__string = "????????????"; + case(_zz_111) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_111_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_111_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_111_string = "BITWISE "; + default : _zz_111_string = "????????"; endcase end always @(*) begin - case(_zz_167_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_167__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_167__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_167__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_167__string = "PC "; - default : _zz_167__string = "???"; + case(_zz_112) + `Src2CtrlEnum_defaultEncoding_RS : _zz_112_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_112_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_112_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_112_string = "PC "; + default : _zz_112_string = "???"; endcase end always @(*) begin - case(_zz_168_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_168__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_168__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_168__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_168__string = "SRA_1 "; - default : _zz_168__string = "?????????"; + case(_zz_113) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_113_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_113_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_113_string = "AND_1"; + default : _zz_113_string = "?????"; endcase end always @(*) begin - case(_zz_169_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_169__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_169__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_169__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_169__string = "ECALL"; - default : _zz_169__string = "?????"; + case(_zz_114) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_114_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_114_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_114_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_114_string = "SRA_1 "; + default : _zz_114_string = "?????????"; endcase end always @(*) begin - case(_zz_170_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_170__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_170__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_170__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_170__string = "JALR"; - default : _zz_170__string = "????"; + case(_zz_115) + `BranchCtrlEnum_defaultEncoding_INC : _zz_115_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_115_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_115_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_115_string = "JALR"; + default : _zz_115_string = "????"; endcase end always @(*) begin - case(_zz_171_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_171__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_171__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_171__string = "AND_1"; - default : _zz_171__string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; - default : decode_to_execute_ENV_CTRL_string = "?????"; + case(_zz_116) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_116_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_116_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_116_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_116_string = "ECALL"; + default : _zz_116_string = "?????"; endcase end always @(*) begin - case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; - default : execute_to_memory_ENV_CTRL_string = "?????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; - default : memory_to_writeBack_ENV_CTRL_string = "?????"; + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin @@ -4095,23 +3064,6 @@ module VexRiscv ( default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end always @(*) begin case(decode_to_execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; @@ -4139,65 +3091,91 @@ module VexRiscv ( default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end `endif - assign decode_IS_RS1_SIGNED = _zz_68_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_87_; + assign memory_MUL_LOW = ($signed(_zz_318) + $signed(_zz_326)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_328; + assign execute_REGFILE_WRITE_DATA = _zz_118; + assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_210[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_330[0]; + assign decode_IS_RS1_SIGNED = _zz_331[0]; + assign decode_IS_DIV = _zz_332[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_66_; - assign decode_IS_DIV = _zz_84_; + assign decode_IS_MUL = _zz_333[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_334[0]; + assign _zz_8 = _zz_9; + assign _zz_10 = _zz_11; + assign decode_SHIFT_CTRL = _zz_12; + assign _zz_13 = _zz_14; + assign decode_ALU_BITWISE_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_SRC_LESS_UNSIGNED = _zz_335[0]; + assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; + assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; + assign decode_IS_SFENCE_VMA = _zz_336[0]; + assign decode_MEMORY_MANAGMENT = _zz_337[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_338[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_339[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_340[0]; + assign decode_SRC2_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_ALU_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_SRC1_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_51; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_102_; - assign _zz_1_ = _zz_2_; - assign decode_CSR_WRITE_OPCODE = _zz_35_; - assign decode_MEMORY_LRSC = _zz_72_; - assign execute_MUL_LH = _zz_30_; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_79_; - assign execute_IS_DBUS_SHARING = _zz_92_; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; - assign _zz_3_ = _zz_4_; - assign decode_SHIFT_CTRL = _zz_5_; - assign _zz_6_ = _zz_7_; - assign decode_ALU_CTRL = _zz_8_; - assign _zz_9_ = _zz_10_; - assign decode_CSR_READ_OPCODE = _zz_34_; - assign execute_BRANCH_DO = _zz_38_; - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_41_; - assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; - assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; - assign decode_IS_SFENCE_VMA = _zz_76_; - assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = _zz_28_; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_64_; - assign decode_SRC1_CTRL = _zz_11_; - assign _zz_12_ = _zz_13_; - assign execute_MUL_HL = _zz_29_; - assign decode_MEMORY_AMO = _zz_88_; - assign decode_SRC_LESS_UNSIGNED = _zz_89_; - assign decode_SRC2_FORCE_ZERO = _zz_55_; - assign execute_MUL_LL = _zz_31_; - assign decode_ALU_BITWISE_CTRL = _zz_14_; - assign _zz_15_ = _zz_16_; - assign decode_SRC2_CTRL = _zz_17_; - assign _zz_18_ = _zz_19_; - assign execute_SHIFT_RIGHT = _zz_45_; - assign execute_BRANCH_CALC = _zz_37_; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_94_; - assign decode_IS_RS2_SIGNED = _zz_71_; - assign decode_MEMORY_MANAGMENT = _zz_65_; - assign _zz_20_ = _zz_21_; - assign _zz_22_ = _zz_23_; - assign decode_ENV_CTRL = _zz_24_; - assign _zz_25_ = _zz_26_; - assign execute_REGFILE_WRITE_DATA = _zz_57_; - assign decode_IS_CSR = _zz_80_; - assign memory_MUL_LOW = _zz_27_; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -4211,25 +3189,25 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_32_; - assign execute_ENV_CTRL = _zz_33_; - assign writeBack_ENV_CTRL = _zz_36_; + assign memory_ENV_CTRL = _zz_27; + assign execute_ENV_CTRL = _zz_28; + assign writeBack_ENV_CTRL = _zz_29; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_40_; - assign execute_BRANCH_CTRL = _zz_39_; - assign decode_RS2_USE = _zz_86_; - assign decode_RS1_USE = _zz_75_; + assign execute_BRANCH_COND_RESULT = _zz_135; + assign execute_BRANCH_CTRL = _zz_30; + assign decode_RS2_USE = _zz_341[0]; + assign decode_RS1_USE = _zz_342[0]; always @ (*) begin - _zz_42_ = execute_REGFILE_WRITE_DATA; - if(_zz_290_)begin - _zz_42_ = execute_CsrPlugin_readData; + _zz_31 = execute_REGFILE_WRITE_DATA; + if(_zz_260)begin + _zz_31 = execute_CsrPlugin_readData; end if(DBusCachedPlugin_forceDatapath)begin - _zz_42_ = MmuPlugin_dBusAccess_cmd_payload_address; + _zz_31 = MmuPlugin_dBusAccess_cmd_payload_address; end end @@ -4240,60 +3218,60 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - decode_RS2 = _zz_62_; - if(_zz_185_)begin - if((_zz_186_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_187_; + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_291_)begin - if(_zz_292_)begin - if(_zz_189_)begin - decode_RS2 = _zz_93_; + if(_zz_261)begin + if(_zz_262)begin + if(_zz_128)begin + decode_RS2 = _zz_50; end end end - if(_zz_293_)begin + if(_zz_263)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_191_)begin - decode_RS2 = _zz_43_; + if(_zz_130)begin + decode_RS2 = _zz_32; end end end - if(_zz_294_)begin + if(_zz_264)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_193_)begin - decode_RS2 = _zz_42_; + if(_zz_132)begin + decode_RS2 = _zz_31; end end end end always @ (*) begin - decode_RS1 = _zz_63_; - if(_zz_185_)begin - if((_zz_186_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_187_; + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_291_)begin - if(_zz_292_)begin - if(_zz_188_)begin - decode_RS1 = _zz_93_; + if(_zz_261)begin + if(_zz_262)begin + if(_zz_127)begin + decode_RS1 = _zz_50; end end end - if(_zz_293_)begin + if(_zz_263)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_190_)begin - decode_RS1 = _zz_43_; + if(_zz_129)begin + decode_RS1 = _zz_32; end end end - if(_zz_294_)begin + if(_zz_264)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_192_)begin - decode_RS1 = _zz_42_; + if(_zz_131)begin + decode_RS1 = _zz_31; end end end @@ -4301,74 +3279,73 @@ module VexRiscv ( assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_43_ = memory_REGFILE_WRITE_DATA; + _zz_32 = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_43_ = _zz_181_; + _zz_32 = _zz_126; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_43_ = memory_SHIFT_RIGHT; + _zz_32 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_295_)begin - _zz_43_ = memory_DivPlugin_div_result; + if(_zz_265)begin + _zz_32 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_44_; - assign execute_SHIFT_CTRL = _zz_46_; + assign memory_SHIFT_CTRL = _zz_33; + assign execute_SHIFT_CTRL = _zz_34; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_50_ = execute_PC; - assign execute_SRC2_CTRL = _zz_51_; - assign execute_SRC1_CTRL = _zz_53_; - assign decode_SRC_USE_SUB_LESS = _zz_69_; - assign decode_SRC_ADD_ZERO = _zz_85_; - assign execute_SRC_ADD_SUB = _zz_49_; - assign execute_SRC_LESS = _zz_47_; - assign execute_ALU_CTRL = _zz_56_; - assign execute_SRC2 = _zz_52_; - assign execute_SRC1 = _zz_54_; - assign execute_ALU_BITWISE_CTRL = _zz_58_; - assign _zz_59_ = writeBack_INSTRUCTION; - assign _zz_60_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_61_ = 1'b0; + assign _zz_35 = execute_PC; + assign execute_SRC2_CTRL = _zz_36; + assign execute_SRC1_CTRL = _zz_37; + assign decode_SRC_USE_SUB_LESS = _zz_343[0]; + assign decode_SRC_ADD_ZERO = _zz_344[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_38; + assign execute_SRC2 = _zz_124; + assign execute_SRC1 = _zz_119; + assign execute_ALU_BITWISE_CTRL = _zz_39; + assign _zz_40 = writeBack_INSTRUCTION; + assign _zz_41 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_42 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_61_ = 1'b1; + _zz_42 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_98_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_74_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_345[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_91_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_468) == 32'h00001073),{(_zz_469 == _zz_470),{_zz_471,{_zz_472,_zz_473}}}}}}} != 25'h0); assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; always @ (*) begin - _zz_93_ = writeBack_REGFILE_WRITE_DATA; + _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_93_ = writeBack_DBusCachedPlugin_rspFormated; + _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_348_) + case(_zz_317) 2'b00 : begin - _zz_93_ = _zz_432_; + _zz_50 = _zz_402; end default : begin - _zz_93_ = _zz_433_; + _zz_50 = _zz_403; end endcase end @@ -4382,62 +3359,69 @@ module VexRiscv ( assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; assign execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; assign execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = _zz_48_; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_83_; - assign decode_FLUSH_ALL = _zz_90_; + assign decode_MEMORY_AMO = _zz_346[0]; + assign decode_MEMORY_LRSC = _zz_347[0]; + assign decode_MEMORY_ENABLE = _zz_348[0]; + assign decode_FLUSH_ALL = _zz_349[0]; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_95_; - if(_zz_296_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_266)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin - _zz_95_ = _zz_96_; - if(_zz_297_)begin - _zz_95_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_267)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin - _zz_96_ = _zz_97_; - if(_zz_298_)begin - _zz_96_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_268)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_97_ = 1'b0; - if(_zz_299_)begin - _zz_97_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_269)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_99_; - assign decode_INSTRUCTION = _zz_103_; + assign decode_BRANCH_CTRL = _zz_52; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_100_ = memory_FORMAL_PC_NEXT; + _zz_53 = execute_FORMAL_PC_NEXT; + if(CsrPlugin_redoInterface_valid)begin + _zz_53 = CsrPlugin_redoInterface_payload; + end + end + + always @ (*) begin + _zz_54 = memory_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin - _zz_100_ = BranchPlugin_jumpInterface_payload; + _zz_54 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_101_ = decode_FORMAL_PC_NEXT; + _zz_55 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_101_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_101_ = IBusCachedPlugin_redoBranch_payload; + _zz_55 = IBusCachedPlugin_predictionJumpInterface_payload; end end - assign decode_PC = _zz_104_; + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -4452,20 +3436,20 @@ module VexRiscv ( if(MmuPlugin_dBusAccess_cmd_valid)begin decode_arbitration_haltByOther = 1'b1; end - if((decode_arbitration_isValid && (_zz_182_ || _zz_183_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_300_)begin + if(_zz_270)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4476,35 +3460,38 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_300_)begin + if(_zz_270)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if((_zz_263_ && (! dataCache_1__io_cpu_flush_ready)))begin - execute_arbitration_haltItself = 1'b1; - end - if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + if(((_zz_233 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_301_)begin + if(_zz_271)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_290_)begin + if(_zz_260)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end end end - assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + end + always @ (*) begin execute_arbitration_removeIt = 1'b0; if(CsrPlugin_selfException_valid)begin @@ -4521,12 +3508,17 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + execute_arbitration_flushNext = 1'b1; + end + end end always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_295_)begin - if(_zz_302_)begin + if(_zz_265)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end end @@ -4556,7 +3548,7 @@ module VexRiscv ( always @ (*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1__io_cpu_writeBack_haltIt)begin + if(dataCache_1_io_cpu_writeBack_haltIt)begin writeBack_arbitration_haltItself = 1'b1; end end @@ -4587,10 +3579,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_303_)begin + if(_zz_272)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_304_)begin + if(_zz_273)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -4601,51 +3593,49 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_303_)begin + if(_zz_272)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_304_)begin + if(_zz_273)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; end end always @ (*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin - IBusCachedPlugin_incomingInstruction = 1'b1; + CsrPlugin_inWfi = 1'b0; + if(_zz_271)begin + CsrPlugin_inWfi = 1'b1; end end + assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_303_)begin + if(_zz_272)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_304_)begin + if(_zz_273)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_303_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_272)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_304_)begin - case(_zz_305_) + if(_zz_273)begin + case(_zz_274) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -4661,21 +3651,26 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); - assign _zz_105_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_106_ = (_zz_105_ & (~ _zz_349_)); - assign _zz_107_ = _zz_106_[3]; - assign _zz_108_ = _zz_106_[4]; - assign _zz_109_ = (_zz_106_[1] || _zz_107_); - assign _zz_110_ = (_zz_106_[2] || _zz_107_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_267_; - always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != 5'h0); + assign _zz_56 = {IBusCachedPlugin_predictionJumpInterface_valid,{CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; + assign _zz_57 = (_zz_56 & (~ _zz_350)); + assign _zz_58 = _zz_57[3]; + assign _zz_59 = _zz_57[4]; + assign _zz_60 = (_zz_57[1] || _zz_58); + assign _zz_61 = (_zz_57[2] || _zz_58); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_237; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin @@ -4684,7 +3679,10 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_351_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_352); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end @@ -4692,12 +3690,28 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin @@ -4705,41 +3719,44 @@ module VexRiscv ( end end - assign _zz_111_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_111_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_111_); + assign _zz_62 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_62); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_62); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + if(IBusCachedPlugin_mmuBus_busy)begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_112_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_112_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_112_); + assign _zz_63 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_63); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_63); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_113_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_113_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_113_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_114_; - assign _zz_114_ = ((1'b0 && (! _zz_115_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_115_ = _zz_116_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_115_; + assign _zz_64 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_64); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_64); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_65; + assign _zz_65 = ((1'b0 && (! _zz_66)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_66 = _zz_67; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_66; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_117_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_117_ = _zz_118_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_117_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_119_; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_68)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_68 = _zz_69; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_68; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_70; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -4751,130 +3768,127 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); - assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - assign _zz_104_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - assign _zz_103_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - assign _zz_102_ = (decode_PC + (32'b00000000000000000000000000000100)); - assign _zz_120_ = _zz_352_[11]; - always @ (*) begin - _zz_121_[18] = _zz_120_; - _zz_121_[17] = _zz_120_; - _zz_121_[16] = _zz_120_; - _zz_121_[15] = _zz_120_; - _zz_121_[14] = _zz_120_; - _zz_121_[13] = _zz_120_; - _zz_121_[12] = _zz_120_; - _zz_121_[11] = _zz_120_; - _zz_121_[10] = _zz_120_; - _zz_121_[9] = _zz_120_; - _zz_121_[8] = _zz_120_; - _zz_121_[7] = _zz_120_; - _zz_121_[6] = _zz_120_; - _zz_121_[5] = _zz_120_; - _zz_121_[4] = _zz_120_; - _zz_121_[3] = _zz_120_; - _zz_121_[2] = _zz_120_; - _zz_121_[1] = _zz_120_; - _zz_121_[0] = _zz_120_; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_353_[31])); - if(_zz_126_)begin + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign _zz_71 = _zz_353[11]; + always @ (*) begin + _zz_72[18] = _zz_71; + _zz_72[17] = _zz_71; + _zz_72[16] = _zz_71; + _zz_72[15] = _zz_71; + _zz_72[14] = _zz_71; + _zz_72[13] = _zz_71; + _zz_72[12] = _zz_71; + _zz_72[11] = _zz_71; + _zz_72[10] = _zz_71; + _zz_72[9] = _zz_71; + _zz_72[8] = _zz_71; + _zz_72[7] = _zz_71; + _zz_72[6] = _zz_71; + _zz_72[5] = _zz_71; + _zz_72[4] = _zz_71; + _zz_72[3] = _zz_71; + _zz_72[2] = _zz_71; + _zz_72[1] = _zz_71; + _zz_72[0] = _zz_71; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_354[31])); + if(_zz_77)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_122_ = _zz_354_[19]; + assign _zz_73 = _zz_355[19]; always @ (*) begin - _zz_123_[10] = _zz_122_; - _zz_123_[9] = _zz_122_; - _zz_123_[8] = _zz_122_; - _zz_123_[7] = _zz_122_; - _zz_123_[6] = _zz_122_; - _zz_123_[5] = _zz_122_; - _zz_123_[4] = _zz_122_; - _zz_123_[3] = _zz_122_; - _zz_123_[2] = _zz_122_; - _zz_123_[1] = _zz_122_; - _zz_123_[0] = _zz_122_; + _zz_74[10] = _zz_73; + _zz_74[9] = _zz_73; + _zz_74[8] = _zz_73; + _zz_74[7] = _zz_73; + _zz_74[6] = _zz_73; + _zz_74[5] = _zz_73; + _zz_74[4] = _zz_73; + _zz_74[3] = _zz_73; + _zz_74[2] = _zz_73; + _zz_74[1] = _zz_73; + _zz_74[0] = _zz_73; end - assign _zz_124_ = _zz_355_[11]; + assign _zz_75 = _zz_356[11]; always @ (*) begin - _zz_125_[18] = _zz_124_; - _zz_125_[17] = _zz_124_; - _zz_125_[16] = _zz_124_; - _zz_125_[15] = _zz_124_; - _zz_125_[14] = _zz_124_; - _zz_125_[13] = _zz_124_; - _zz_125_[12] = _zz_124_; - _zz_125_[11] = _zz_124_; - _zz_125_[10] = _zz_124_; - _zz_125_[9] = _zz_124_; - _zz_125_[8] = _zz_124_; - _zz_125_[7] = _zz_124_; - _zz_125_[6] = _zz_124_; - _zz_125_[5] = _zz_124_; - _zz_125_[4] = _zz_124_; - _zz_125_[3] = _zz_124_; - _zz_125_[2] = _zz_124_; - _zz_125_[1] = _zz_124_; - _zz_125_[0] = _zz_124_; + _zz_76[18] = _zz_75; + _zz_76[17] = _zz_75; + _zz_76[16] = _zz_75; + _zz_76[15] = _zz_75; + _zz_76[14] = _zz_75; + _zz_76[13] = _zz_75; + _zz_76[12] = _zz_75; + _zz_76[11] = _zz_75; + _zz_76[10] = _zz_75; + _zz_76[9] = _zz_75; + _zz_76[8] = _zz_75; + _zz_76[7] = _zz_75; + _zz_76[6] = _zz_75; + _zz_76[5] = _zz_75; + _zz_76[4] = _zz_75; + _zz_76[3] = _zz_75; + _zz_76[2] = _zz_75; + _zz_76[1] = _zz_75; + _zz_76[0] = _zz_75; end always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_126_ = _zz_356_[1]; + _zz_77 = _zz_357[1]; end default : begin - _zz_126_ = _zz_357_[1]; + _zz_77 = _zz_358[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_127_ = _zz_358_[19]; - always @ (*) begin - _zz_128_[10] = _zz_127_; - _zz_128_[9] = _zz_127_; - _zz_128_[8] = _zz_127_; - _zz_128_[7] = _zz_127_; - _zz_128_[6] = _zz_127_; - _zz_128_[5] = _zz_127_; - _zz_128_[4] = _zz_127_; - _zz_128_[3] = _zz_127_; - _zz_128_[2] = _zz_127_; - _zz_128_[1] = _zz_127_; - _zz_128_[0] = _zz_127_; - end - - assign _zz_129_ = _zz_359_[11]; - always @ (*) begin - _zz_130_[18] = _zz_129_; - _zz_130_[17] = _zz_129_; - _zz_130_[16] = _zz_129_; - _zz_130_[15] = _zz_129_; - _zz_130_[14] = _zz_129_; - _zz_130_[13] = _zz_129_; - _zz_130_[12] = _zz_129_; - _zz_130_[11] = _zz_129_; - _zz_130_[10] = _zz_129_; - _zz_130_[9] = _zz_129_; - _zz_130_[8] = _zz_129_; - _zz_130_[7] = _zz_129_; - _zz_130_[6] = _zz_129_; - _zz_130_[5] = _zz_129_; - _zz_130_[4] = _zz_129_; - _zz_130_[3] = _zz_129_; - _zz_130_[2] = _zz_129_; - _zz_130_[1] = _zz_129_; - _zz_130_[0] = _zz_129_; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_128_,{{{_zz_498_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_130_,{{{_zz_499_,_zz_500_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_78 = _zz_359[19]; + always @ (*) begin + _zz_79[10] = _zz_78; + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7] = _zz_78; + _zz_79[6] = _zz_78; + _zz_79[5] = _zz_78; + _zz_79[4] = _zz_78; + _zz_79[3] = _zz_78; + _zz_79[2] = _zz_78; + _zz_79[1] = _zz_78; + _zz_79[0] = _zz_78; + end + + assign _zz_80 = _zz_360[11]; + always @ (*) begin + _zz_81[18] = _zz_80; + _zz_81[17] = _zz_80; + _zz_81[16] = _zz_80; + _zz_81[15] = _zz_80; + _zz_81[14] = _zz_80; + _zz_81[13] = _zz_80; + _zz_81[12] = _zz_80; + _zz_81[11] = _zz_80; + _zz_81[10] = _zz_80; + _zz_81[9] = _zz_80; + _zz_81[8] = _zz_80; + _zz_81[7] = _zz_80; + _zz_81[6] = _zz_80; + _zz_81[5] = _zz_80; + _zz_81[4] = _zz_80; + _zz_81[3] = _zz_80; + _zz_81[2] = _zz_80; + _zz_81[1] = _zz_80; + _zz_81[0] = _zz_80; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_79,{{{_zz_491,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_81,{{{_zz_492,_zz_493},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -4883,120 +3897,127 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_240_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_243_ = (32'b00000000000000000000000000000000); - assign _zz_241_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_242_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_244_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_245_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_246_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_98_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign _zz_201 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_202 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_203 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_202; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_205 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_206 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_207 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_299_)begin + if(_zz_269)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_297_)begin + if(_zz_267)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_306_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - end end always @ (*) begin - _zz_247_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_297_)begin - _zz_247_ = 1'b1; - end - if(_zz_306_)begin - _zz_247_ = 1'b0; + _zz_208 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_267)begin + _zz_208 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_298_)begin + if(_zz_268)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_296_)begin + if(_zz_266)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_298_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); - end - if(_zz_296_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_239_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_132_); - assign _zz_264_ = (! _zz_132_); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_132_ ? _zz_133_ : dataCache_1__io_mem_cmd_payload_wr); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_132_ ? _zz_134_ : dataCache_1__io_mem_cmd_payload_address); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_132_ ? _zz_135_ : dataCache_1__io_mem_cmd_payload_data); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_132_ ? _zz_136_ : dataCache_1__io_mem_cmd_payload_mask); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_132_ ? _zz_137_ : dataCache_1__io_mem_cmd_payload_length); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_132_ ? _zz_138_ : dataCache_1__io_mem_cmd_payload_last); - assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_139_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_140_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_141_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_142_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_143_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_144_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_145_; - assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_268)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_266)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_200 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_234 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + always @ (*) begin + _zz_51 = 1'b0; + if(decode_INSTRUCTION[25])begin + if(decode_MEMORY_LRSC)begin + _zz_51 = 1'b1; + end + if(decode_MEMORY_AMO)begin + _zz_51 = 1'b1; + end + end + end + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin - _zz_248_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + _zz_209 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_307_)begin - if(_zz_308_)begin - _zz_248_ = 1'b1; + if(_zz_275)begin + if(_zz_276)begin + _zz_209 = 1'b1; end end end end always @ (*) begin - _zz_249_ = execute_SRC_ADD; + _zz_210 = execute_SRC_ADD; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_307_)begin - _zz_249_ = MmuPlugin_dBusAccess_cmd_payload_address; + if(_zz_275)begin + _zz_210 = MmuPlugin_dBusAccess_cmd_payload_address; end end end always @ (*) begin - _zz_250_ = execute_MEMORY_WR; + _zz_211 = execute_MEMORY_WR; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_307_)begin - _zz_250_ = MmuPlugin_dBusAccess_cmd_payload_write; + if(_zz_275)begin + _zz_211 = MmuPlugin_dBusAccess_cmd_payload_write; end end end @@ -5004,98 +4025,98 @@ module VexRiscv ( always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_147_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_84 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_147_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_84 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_147_ = execute_RS2[31 : 0]; + _zz_84 = execute_RS2[31 : 0]; end endcase end always @ (*) begin - _zz_251_ = _zz_147_; + _zz_212 = _zz_84; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_307_)begin - _zz_251_ = MmuPlugin_dBusAccess_cmd_payload_data; + if(_zz_275)begin + _zz_212 = MmuPlugin_dBusAccess_cmd_payload_data; end end end always @ (*) begin - _zz_252_ = execute_DBusCachedPlugin_size; + _zz_213 = execute_DBusCachedPlugin_size; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_307_)begin - _zz_252_ = MmuPlugin_dBusAccess_cmd_payload_size; + if(_zz_275)begin + _zz_213 = MmuPlugin_dBusAccess_cmd_payload_size; end end end - assign _zz_263_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_233 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); always @ (*) begin - _zz_253_ = 1'b0; + _zz_214 = 1'b0; if(execute_MEMORY_LRSC)begin - _zz_253_ = 1'b1; + _zz_214 = 1'b1; end if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_307_)begin - _zz_253_ = 1'b0; + if(_zz_275)begin + _zz_214 = 1'b0; end end end always @ (*) begin - _zz_254_ = execute_MEMORY_AMO; + _zz_215 = execute_MEMORY_AMO; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_307_)begin - _zz_254_ = 1'b0; + if(_zz_275)begin + _zz_215 = 1'b0; end end end - assign _zz_256_ = execute_INSTRUCTION[31 : 29]; - assign _zz_255_ = execute_INSTRUCTION[27]; - assign _zz_94_ = _zz_249_[1 : 0]; + assign _zz_217 = execute_INSTRUCTION[31 : 29]; + assign _zz_216 = execute_INSTRUCTION[27]; always @ (*) begin - _zz_257_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + _zz_218 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); if(memory_IS_DBUS_SHARING)begin - _zz_257_ = 1'b1; + _zz_218 = 1'b1; end end - assign _zz_258_ = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + assign _zz_219 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_218; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_219; always @ (*) begin - DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; if(memory_IS_DBUS_SHARING)begin - DBusCachedPlugin_mmuBus_cmd_bypassTranslation = 1'b1; + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; end end + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_259_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin - _zz_259_ = 1'b1; + _zz_220 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_220 = 1'b1; end end - assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; always @ (*) begin - _zz_260_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + _zz_221 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); if(writeBack_IS_DBUS_SHARING)begin - _zz_260_ = 1'b1; + _zz_221 = 1'b1; end end - assign _zz_261_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_262_ = writeBack_REGFILE_WRITE_DATA; + assign _zz_222 = (CsrPlugin_privilege == 2'b00); + assign _zz_223 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_309_)begin - if(dataCache_1__io_cpu_redo)begin + if(_zz_277)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end @@ -5104,17 +4125,17 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_309_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin + if(_zz_277)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_redo)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end @@ -5122,94 +4143,94 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); - if(_zz_309_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_360_}; + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_277)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_361}; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_361_}; + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1__io_cpu_writeBack_mmuException)begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_362}; end end end always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; end 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; end 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; end default : begin end endcase end - assign _zz_148_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_149_[31] = _zz_148_; - _zz_149_[30] = _zz_148_; - _zz_149_[29] = _zz_148_; - _zz_149_[28] = _zz_148_; - _zz_149_[27] = _zz_148_; - _zz_149_[26] = _zz_148_; - _zz_149_[25] = _zz_148_; - _zz_149_[24] = _zz_148_; - _zz_149_[23] = _zz_148_; - _zz_149_[22] = _zz_148_; - _zz_149_[21] = _zz_148_; - _zz_149_[20] = _zz_148_; - _zz_149_[19] = _zz_148_; - _zz_149_[18] = _zz_148_; - _zz_149_[17] = _zz_148_; - _zz_149_[16] = _zz_148_; - _zz_149_[15] = _zz_148_; - _zz_149_[14] = _zz_148_; - _zz_149_[13] = _zz_148_; - _zz_149_[12] = _zz_148_; - _zz_149_[11] = _zz_148_; - _zz_149_[10] = _zz_148_; - _zz_149_[9] = _zz_148_; - _zz_149_[8] = _zz_148_; - _zz_149_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_150_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_151_[31] = _zz_150_; - _zz_151_[30] = _zz_150_; - _zz_151_[29] = _zz_150_; - _zz_151_[28] = _zz_150_; - _zz_151_[27] = _zz_150_; - _zz_151_[26] = _zz_150_; - _zz_151_[25] = _zz_150_; - _zz_151_[24] = _zz_150_; - _zz_151_[23] = _zz_150_; - _zz_151_[22] = _zz_150_; - _zz_151_[21] = _zz_150_; - _zz_151_[20] = _zz_150_; - _zz_151_[19] = _zz_150_; - _zz_151_[18] = _zz_150_; - _zz_151_[17] = _zz_150_; - _zz_151_[16] = _zz_150_; - _zz_151_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_346_) + assign _zz_85 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_86[31] = _zz_85; + _zz_86[30] = _zz_85; + _zz_86[29] = _zz_85; + _zz_86[28] = _zz_85; + _zz_86[27] = _zz_85; + _zz_86[26] = _zz_85; + _zz_86[25] = _zz_85; + _zz_86[24] = _zz_85; + _zz_86[23] = _zz_85; + _zz_86[22] = _zz_85; + _zz_86[21] = _zz_85; + _zz_86[20] = _zz_85; + _zz_86[19] = _zz_85; + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_87 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_88[31] = _zz_87; + _zz_88[30] = _zz_87; + _zz_88[29] = _zz_87; + _zz_88[28] = _zz_87; + _zz_88[27] = _zz_87; + _zz_88[26] = _zz_87; + _zz_88[25] = _zz_87; + _zz_88[24] = _zz_87; + _zz_88[23] = _zz_87; + _zz_88[22] = _zz_87; + _zz_88[21] = _zz_87; + _zz_88[20] = _zz_87; + _zz_88[19] = _zz_87; + _zz_88[18] = _zz_87; + _zz_88[17] = _zz_87; + _zz_88[16] = _zz_87; + _zz_88[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_315) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_149_; + writeBack_DBusCachedPlugin_rspFormated = _zz_86; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_151_; + writeBack_DBusCachedPlugin_rspFormated = _zz_88; end default : begin writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; @@ -5220,8 +4241,8 @@ module VexRiscv ( always @ (*) begin MmuPlugin_dBusAccess_cmd_ready = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_307_)begin - if(_zz_308_)begin + if(_zz_275)begin + if(_zz_276)begin MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); end end @@ -5231,229 +4252,272 @@ module VexRiscv ( always @ (*) begin DBusCachedPlugin_forceDatapath = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_307_)begin + if(_zz_275)begin DBusCachedPlugin_forceDatapath = 1'b1; end end end - assign _zz_92_ = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); - assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1__io_cpu_writeBack_isWrite)) && (dataCache_1__io_cpu_redo || (! dataCache_1__io_cpu_writeBack_haltIt))); - assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1__io_cpu_writeBack_data; - assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1__io_cpu_writeBack_unalignedAccess || dataCache_1__io_cpu_writeBack_accessError); - assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1__io_cpu_redo; - assign MmuPlugin_ports_0_cacheHits_0 = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHits_1 = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHits_2 = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHits_3 = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHit = ({MmuPlugin_ports_0_cacheHits_3,{MmuPlugin_ports_0_cacheHits_2,{MmuPlugin_ports_0_cacheHits_1,MmuPlugin_ports_0_cacheHits_0}}} != (4'b0000)); - assign _zz_152_ = (MmuPlugin_ports_0_cacheHits_1 || MmuPlugin_ports_0_cacheHits_3); - assign _zz_153_ = (MmuPlugin_ports_0_cacheHits_2 || MmuPlugin_ports_0_cacheHits_3); - assign _zz_154_ = {_zz_153_,_zz_152_}; - assign MmuPlugin_ports_0_cacheLine_valid = _zz_268_; - assign MmuPlugin_ports_0_cacheLine_exception = _zz_269_; - assign MmuPlugin_ports_0_cacheLine_superPage = _zz_270_; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_271_; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_272_; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_273_; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_274_; - assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_275_; - assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_276_; - assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_277_; - assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_278_; + assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); + assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1_io_cpu_writeBack_data; + assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); + assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; + assign MmuPlugin_ports_0_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_0_requireMmuLockupCalc = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + end + + always @ (*) begin + MmuPlugin_ports_0_cacheHitsCalc[0] = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[1] = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[2] = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[3] = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + end + + assign MmuPlugin_ports_0_cacheHit = (MmuPlugin_ports_0_cacheHitsCalc != 4'b0000); + assign _zz_89 = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign _zz_90 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_89); + assign _zz_91 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_89); + assign _zz_92 = {_zz_91,_zz_90}; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_238; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_239; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_240; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_241; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_242; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_243; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_244; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_245; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_246; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_247; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_248; always @ (*) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; - if(_zz_310_)begin - if(_zz_311_)begin + if(_zz_278)begin + if(_zz_279)begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; end end end assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; - assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == (2'b11)); + assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_363_); + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_364); if(MmuPlugin_ports_0_entryToReplace_willClear)begin - MmuPlugin_ports_0_entryToReplace_valueNext = (2'b00); + MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; end end always @ (*) begin - MmuPlugin_ports_0_requireMmuLockup = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == (2'b11))))begin - MmuPlugin_ports_0_requireMmuLockup = 1'b0; - end - if((CsrPlugin_privilege == (2'b11)))begin - if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == (2'b11))))begin - MmuPlugin_ports_0_requireMmuLockup = 1'b0; - end + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_virtualAddress[11 : 0]}; + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); end else begin - DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; end else begin - DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; end else begin - DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin - DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_exception = (MmuPlugin_ports_0_cacheHit && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == (2'b01))) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == (2'b00))))); + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); end else begin - DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_refilling = (! MmuPlugin_ports_0_cacheHit); + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin - DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1011) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1110)) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111)); + assign IBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_0_requireMmuLockupCalc); + assign IBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_0_cacheHitsCalc[0]; + assign IBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_0_cache_0_physicalAddress_1,(MmuPlugin_ports_0_cache_0_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_0_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_0_cacheHitsCalc[1]; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_0_cache_1_physicalAddress_1,(MmuPlugin_ports_0_cache_1_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_1_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_0_cacheHitsCalc[2]; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_0_cache_2_physicalAddress_1,(MmuPlugin_ports_0_cache_2_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_2_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_ports_1_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_1_requireMmuLockupCalc = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end end end - assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1011)) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1110))) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111))); - assign MmuPlugin_ports_1_cacheHits_0 = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHits_1 = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHits_2 = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHits_3 = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHit = ({MmuPlugin_ports_1_cacheHits_3,{MmuPlugin_ports_1_cacheHits_2,{MmuPlugin_ports_1_cacheHits_1,MmuPlugin_ports_1_cacheHits_0}}} != (4'b0000)); - assign _zz_155_ = (MmuPlugin_ports_1_cacheHits_1 || MmuPlugin_ports_1_cacheHits_3); - assign _zz_156_ = (MmuPlugin_ports_1_cacheHits_2 || MmuPlugin_ports_1_cacheHits_3); - assign _zz_157_ = {_zz_156_,_zz_155_}; - assign MmuPlugin_ports_1_cacheLine_valid = _zz_279_; - assign MmuPlugin_ports_1_cacheLine_exception = _zz_280_; - assign MmuPlugin_ports_1_cacheLine_superPage = _zz_281_; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_282_; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_283_; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_284_; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_285_; - assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_286_; - assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_287_; - assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_288_; - assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_289_; + always @ (*) begin + MmuPlugin_ports_1_cacheHitsCalc[0] = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[1] = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[2] = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[3] = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + end + + assign MmuPlugin_ports_1_cacheHit = (MmuPlugin_ports_1_cacheHitsCalc != 4'b0000); + assign _zz_93 = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign _zz_94 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_93); + assign _zz_95 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_93); + assign _zz_96 = {_zz_95,_zz_94}; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_249; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_250; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_251; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_252; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_253; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_254; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_255; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_256; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_257; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_258; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_259; always @ (*) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; - if(_zz_310_)begin - if(_zz_312_)begin + if(_zz_278)begin + if(_zz_280)begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; end end end assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; - assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == (2'b11)); + assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_365_); + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_366); if(MmuPlugin_ports_1_entryToReplace_willClear)begin - MmuPlugin_ports_1_entryToReplace_valueNext = (2'b00); + MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; end end always @ (*) begin - MmuPlugin_ports_1_requireMmuLockup = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == (2'b11))))begin - MmuPlugin_ports_1_requireMmuLockup = 1'b0; - end - if((CsrPlugin_privilege == (2'b11)))begin - MmuPlugin_ports_1_requireMmuLockup = 1'b0; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_virtualAddress[11 : 0]}; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); end else begin - IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; end else begin - IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; end else begin - IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin - IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_exception = (MmuPlugin_ports_1_cacheHit && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == (2'b01))) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == (2'b00))))); + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); end else begin - IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_refilling = (! MmuPlugin_ports_1_cacheHit); + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin - IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - end - end - - assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1011)) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1110))) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111))); - assign MmuPlugin_shared_dBusRsp_pte_V = _zz_366_[0]; - assign MmuPlugin_shared_dBusRsp_pte_R = _zz_367_[0]; - assign MmuPlugin_shared_dBusRsp_pte_W = _zz_368_[0]; - assign MmuPlugin_shared_dBusRsp_pte_X = _zz_369_[0]; - assign MmuPlugin_shared_dBusRsp_pte_U = _zz_370_[0]; - assign MmuPlugin_shared_dBusRsp_pte_G = _zz_371_[0]; - assign MmuPlugin_shared_dBusRsp_pte_A = _zz_372_[0]; - assign MmuPlugin_shared_dBusRsp_pte_D = _zz_373_[0]; - assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_dBusAccess_rsp_payload_data[9 : 8]; - assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_dBusAccess_rsp_payload_data[19 : 10]; - assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_dBusAccess_rsp_payload_data[31 : 20]; - assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_dBusAccess_rsp_payload_error); + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1011) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1110)) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111)); + assign DBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_1_requireMmuLockupCalc); + assign DBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_1_cacheHitsCalc[0]; + assign DBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_1_cache_0_physicalAddress_1,(MmuPlugin_ports_1_cache_0_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_0_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_1_cacheHitsCalc[1]; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_1_cache_1_physicalAddress_1,(MmuPlugin_ports_1_cache_1_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_1_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_1_cacheHitsCalc[2]; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_shared_dBusRsp_pte_V = _zz_367[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = _zz_368[0]; + assign MmuPlugin_shared_dBusRsp_pte_W = _zz_369[0]; + assign MmuPlugin_shared_dBusRsp_pte_X = _zz_370[0]; + assign MmuPlugin_shared_dBusRsp_pte_U = _zz_371[0]; + assign MmuPlugin_shared_dBusRsp_pte_G = _zz_372[0]; + assign MmuPlugin_shared_dBusRsp_pte_A = _zz_373[0]; + assign MmuPlugin_shared_dBusRsp_pte_D = _zz_374[0]; + assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; + assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; + assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; + assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); always @ (*) begin MmuPlugin_dBusAccess_cmd_valid = 1'b0; - case(MmuPlugin_shared_state_1_) + case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin end `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin @@ -5470,89 +4534,97 @@ module VexRiscv ( end assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; - assign MmuPlugin_dBusAccess_cmd_payload_size = (2'b10); + assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; always @ (*) begin - MmuPlugin_dBusAccess_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - case(MmuPlugin_shared_state_1_) + MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin end `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin - MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},(2'b00)}; + MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; end `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin end `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin - MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},(2'b00)}; + MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; end default : begin end endcase end - assign MmuPlugin_dBusAccess_cmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - assign MmuPlugin_dBusAccess_cmd_payload_writeMask = (4'bxxxx); - assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1_ != `MmuPlugin_shared_State_defaultEncoding_IDLE) && (MmuPlugin_shared_portId == (1'b1))); - assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1_ != `MmuPlugin_shared_State_defaultEncoding_IDLE) && (MmuPlugin_shared_portId == (1'b0))); - assign _zz_159_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)); - assign _zz_160_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000000000000)); - assign _zz_161_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_162_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_163_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_164_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); - assign _zz_158_ = {({(_zz_501_ == _zz_502_),{_zz_503_,{_zz_504_,_zz_505_}}} != (5'b00000)),{((_zz_506_ == _zz_507_) != (1'b0)),{(_zz_508_ != (1'b0)),{(_zz_509_ != _zz_510_),{_zz_511_,{_zz_512_,_zz_513_}}}}}}; - assign _zz_91_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_692_) == (32'b00000000000000000001000001110011)),{(_zz_693_ == _zz_694_),{_zz_695_,{_zz_696_,_zz_697_}}}}}}} != (25'b0000000000000000000000000)); - assign _zz_90_ = _zz_374_[0]; - assign _zz_89_ = _zz_375_[0]; - assign _zz_88_ = _zz_376_[0]; - assign _zz_87_ = _zz_377_[0]; - assign _zz_86_ = _zz_378_[0]; - assign _zz_85_ = _zz_379_[0]; - assign _zz_84_ = _zz_380_[0]; - assign _zz_83_ = _zz_381_[0]; - assign _zz_165_ = _zz_158_[9 : 8]; - assign _zz_82_ = _zz_165_; - assign _zz_166_ = _zz_158_[11 : 10]; - assign _zz_81_ = _zz_166_; - assign _zz_80_ = _zz_382_[0]; - assign _zz_79_ = _zz_383_[0]; - assign _zz_167_ = _zz_158_[16 : 15]; - assign _zz_78_ = _zz_167_; - assign _zz_168_ = _zz_158_[18 : 17]; - assign _zz_77_ = _zz_168_; - assign _zz_76_ = _zz_384_[0]; - assign _zz_75_ = _zz_385_[0]; - assign _zz_74_ = _zz_386_[0]; - assign _zz_169_ = _zz_158_[23 : 22]; - assign _zz_73_ = _zz_169_; - assign _zz_72_ = _zz_387_[0]; - assign _zz_71_ = _zz_388_[0]; - assign _zz_170_ = _zz_158_[27 : 26]; - assign _zz_70_ = _zz_170_; - assign _zz_69_ = _zz_389_[0]; - assign _zz_68_ = _zz_390_[0]; - assign _zz_171_ = _zz_158_[31 : 30]; - assign _zz_67_ = _zz_171_; - assign _zz_66_ = _zz_391_[0]; - assign _zz_65_ = _zz_392_[0]; - assign _zz_64_ = _zz_393_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; + always @ (*) begin + _zz_97[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); + _zz_97[1] = (((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)); + end + + assign _zz_98 = _zz_97; + always @ (*) begin + _zz_99[0] = _zz_98[1]; + _zz_99[1] = _zz_98[0]; + end + + assign _zz_100 = (_zz_99 & (~ _zz_375)); + always @ (*) begin + _zz_101[0] = _zz_100[1]; + _zz_101[1] = _zz_100[0]; + end + + assign MmuPlugin_shared_refills = _zz_101; + assign _zz_102 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); + assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[0]); + assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[1]); + assign _zz_104 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_105 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_106 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); + assign _zz_107 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_108 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_109 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_103 = {(_zz_109 != 1'b0),{(_zz_109 != 1'b0),{((_zz_494 == _zz_495) != 1'b0),{(_zz_496 != 1'b0),{(_zz_497 != _zz_498),{_zz_499,{_zz_500,_zz_501}}}}}}}; + assign _zz_110 = _zz_103[2 : 1]; + assign _zz_49 = _zz_110; + assign _zz_111 = _zz_103[7 : 6]; + assign _zz_48 = _zz_111; + assign _zz_112 = _zz_103[9 : 8]; + assign _zz_47 = _zz_112; + assign _zz_113 = _zz_103[23 : 22]; + assign _zz_46 = _zz_113; + assign _zz_114 = _zz_103[25 : 24]; + assign _zz_45 = _zz_114; + assign _zz_115 = _zz_103[27 : 26]; + assign _zz_44 = _zz_115; + assign _zz_116 = _zz_103[30 : 29]; + assign _zz_43 = _zz_116; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_265_; - assign decode_RegFilePlugin_rs2Data = _zz_266_; - assign _zz_63_ = decode_RegFilePlugin_rs1Data; - assign _zz_62_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_235; + assign decode_RegFilePlugin_rs2Data = _zz_236; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_60_ && writeBack_arbitration_isFiring); - if(_zz_172_)begin + lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); + if(_zz_117)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_59_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_93_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; + if(_zz_117)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_50; + if(_zz_117)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -5570,361 +4642,354 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_173_ = execute_IntAluPlugin_bitwise; + _zz_118 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_173_ = {31'd0, _zz_394_}; + _zz_118 = {31'd0, _zz_376}; end default : begin - _zz_173_ = execute_SRC_ADD_SUB; + _zz_118 = execute_SRC_ADD_SUB; end endcase end - assign _zz_57_ = _zz_173_; - assign _zz_55_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_174_ = execute_RS1; + _zz_119 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_174_ = {29'd0, _zz_395_}; + _zz_119 = {29'd0, _zz_377}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_174_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_119 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_174_ = {27'd0, _zz_396_}; + _zz_119 = {27'd0, _zz_378}; end endcase end - assign _zz_54_ = _zz_174_; - assign _zz_175_ = _zz_397_[11]; - always @ (*) begin - _zz_176_[19] = _zz_175_; - _zz_176_[18] = _zz_175_; - _zz_176_[17] = _zz_175_; - _zz_176_[16] = _zz_175_; - _zz_176_[15] = _zz_175_; - _zz_176_[14] = _zz_175_; - _zz_176_[13] = _zz_175_; - _zz_176_[12] = _zz_175_; - _zz_176_[11] = _zz_175_; - _zz_176_[10] = _zz_175_; - _zz_176_[9] = _zz_175_; - _zz_176_[8] = _zz_175_; - _zz_176_[7] = _zz_175_; - _zz_176_[6] = _zz_175_; - _zz_176_[5] = _zz_175_; - _zz_176_[4] = _zz_175_; - _zz_176_[3] = _zz_175_; - _zz_176_[2] = _zz_175_; - _zz_176_[1] = _zz_175_; - _zz_176_[0] = _zz_175_; - end - - assign _zz_177_ = _zz_398_[11]; - always @ (*) begin - _zz_178_[19] = _zz_177_; - _zz_178_[18] = _zz_177_; - _zz_178_[17] = _zz_177_; - _zz_178_[16] = _zz_177_; - _zz_178_[15] = _zz_177_; - _zz_178_[14] = _zz_177_; - _zz_178_[13] = _zz_177_; - _zz_178_[12] = _zz_177_; - _zz_178_[11] = _zz_177_; - _zz_178_[10] = _zz_177_; - _zz_178_[9] = _zz_177_; - _zz_178_[8] = _zz_177_; - _zz_178_[7] = _zz_177_; - _zz_178_[6] = _zz_177_; - _zz_178_[5] = _zz_177_; - _zz_178_[4] = _zz_177_; - _zz_178_[3] = _zz_177_; - _zz_178_[2] = _zz_177_; - _zz_178_[1] = _zz_177_; - _zz_178_[0] = _zz_177_; + assign _zz_120 = _zz_379[11]; + always @ (*) begin + _zz_121[19] = _zz_120; + _zz_121[18] = _zz_120; + _zz_121[17] = _zz_120; + _zz_121[16] = _zz_120; + _zz_121[15] = _zz_120; + _zz_121[14] = _zz_120; + _zz_121[13] = _zz_120; + _zz_121[12] = _zz_120; + _zz_121[11] = _zz_120; + _zz_121[10] = _zz_120; + _zz_121[9] = _zz_120; + _zz_121[8] = _zz_120; + _zz_121[7] = _zz_120; + _zz_121[6] = _zz_120; + _zz_121[5] = _zz_120; + _zz_121[4] = _zz_120; + _zz_121[3] = _zz_120; + _zz_121[2] = _zz_120; + _zz_121[1] = _zz_120; + _zz_121[0] = _zz_120; + end + + assign _zz_122 = _zz_380[11]; + always @ (*) begin + _zz_123[19] = _zz_122; + _zz_123[18] = _zz_122; + _zz_123[17] = _zz_122; + _zz_123[16] = _zz_122; + _zz_123[15] = _zz_122; + _zz_123[14] = _zz_122; + _zz_123[13] = _zz_122; + _zz_123[12] = _zz_122; + _zz_123[11] = _zz_122; + _zz_123[10] = _zz_122; + _zz_123[9] = _zz_122; + _zz_123[8] = _zz_122; + _zz_123[7] = _zz_122; + _zz_123[6] = _zz_122; + _zz_123[5] = _zz_122; + _zz_123[4] = _zz_122; + _zz_123[3] = _zz_122; + _zz_123[2] = _zz_122; + _zz_123[1] = _zz_122; + _zz_123[0] = _zz_122; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_179_ = execute_RS2; + _zz_124 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_179_ = {_zz_176_,execute_INSTRUCTION[31 : 20]}; + _zz_124 = {_zz_121,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_179_ = {_zz_178_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_124 = {_zz_123,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_179_ = _zz_50_; + _zz_124 = _zz_35; end endcase end - assign _zz_52_ = _zz_179_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_399_; + execute_SrcPlugin_addSub = _zz_381; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_49_ = execute_SrcPlugin_addSub; - assign _zz_48_ = execute_SrcPlugin_addSub; - assign _zz_47_ = execute_SrcPlugin_less; assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_180_[0] = execute_SRC1[31]; - _zz_180_[1] = execute_SRC1[30]; - _zz_180_[2] = execute_SRC1[29]; - _zz_180_[3] = execute_SRC1[28]; - _zz_180_[4] = execute_SRC1[27]; - _zz_180_[5] = execute_SRC1[26]; - _zz_180_[6] = execute_SRC1[25]; - _zz_180_[7] = execute_SRC1[24]; - _zz_180_[8] = execute_SRC1[23]; - _zz_180_[9] = execute_SRC1[22]; - _zz_180_[10] = execute_SRC1[21]; - _zz_180_[11] = execute_SRC1[20]; - _zz_180_[12] = execute_SRC1[19]; - _zz_180_[13] = execute_SRC1[18]; - _zz_180_[14] = execute_SRC1[17]; - _zz_180_[15] = execute_SRC1[16]; - _zz_180_[16] = execute_SRC1[15]; - _zz_180_[17] = execute_SRC1[14]; - _zz_180_[18] = execute_SRC1[13]; - _zz_180_[19] = execute_SRC1[12]; - _zz_180_[20] = execute_SRC1[11]; - _zz_180_[21] = execute_SRC1[10]; - _zz_180_[22] = execute_SRC1[9]; - _zz_180_[23] = execute_SRC1[8]; - _zz_180_[24] = execute_SRC1[7]; - _zz_180_[25] = execute_SRC1[6]; - _zz_180_[26] = execute_SRC1[5]; - _zz_180_[27] = execute_SRC1[4]; - _zz_180_[28] = execute_SRC1[3]; - _zz_180_[29] = execute_SRC1[2]; - _zz_180_[30] = execute_SRC1[1]; - _zz_180_[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_180_ : execute_SRC1); - assign _zz_45_ = _zz_407_; - always @ (*) begin - _zz_181_[0] = memory_SHIFT_RIGHT[31]; - _zz_181_[1] = memory_SHIFT_RIGHT[30]; - _zz_181_[2] = memory_SHIFT_RIGHT[29]; - _zz_181_[3] = memory_SHIFT_RIGHT[28]; - _zz_181_[4] = memory_SHIFT_RIGHT[27]; - _zz_181_[5] = memory_SHIFT_RIGHT[26]; - _zz_181_[6] = memory_SHIFT_RIGHT[25]; - _zz_181_[7] = memory_SHIFT_RIGHT[24]; - _zz_181_[8] = memory_SHIFT_RIGHT[23]; - _zz_181_[9] = memory_SHIFT_RIGHT[22]; - _zz_181_[10] = memory_SHIFT_RIGHT[21]; - _zz_181_[11] = memory_SHIFT_RIGHT[20]; - _zz_181_[12] = memory_SHIFT_RIGHT[19]; - _zz_181_[13] = memory_SHIFT_RIGHT[18]; - _zz_181_[14] = memory_SHIFT_RIGHT[17]; - _zz_181_[15] = memory_SHIFT_RIGHT[16]; - _zz_181_[16] = memory_SHIFT_RIGHT[15]; - _zz_181_[17] = memory_SHIFT_RIGHT[14]; - _zz_181_[18] = memory_SHIFT_RIGHT[13]; - _zz_181_[19] = memory_SHIFT_RIGHT[12]; - _zz_181_[20] = memory_SHIFT_RIGHT[11]; - _zz_181_[21] = memory_SHIFT_RIGHT[10]; - _zz_181_[22] = memory_SHIFT_RIGHT[9]; - _zz_181_[23] = memory_SHIFT_RIGHT[8]; - _zz_181_[24] = memory_SHIFT_RIGHT[7]; - _zz_181_[25] = memory_SHIFT_RIGHT[6]; - _zz_181_[26] = memory_SHIFT_RIGHT[5]; - _zz_181_[27] = memory_SHIFT_RIGHT[4]; - _zz_181_[28] = memory_SHIFT_RIGHT[3]; - _zz_181_[29] = memory_SHIFT_RIGHT[2]; - _zz_181_[30] = memory_SHIFT_RIGHT[1]; - _zz_181_[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_182_ = 1'b0; - if(_zz_313_)begin - if(_zz_314_)begin - if(_zz_188_)begin - _zz_182_ = 1'b1; - end - end - end - if(_zz_315_)begin - if(_zz_316_)begin - if(_zz_190_)begin - _zz_182_ = 1'b1; - end - end - end - if(_zz_317_)begin - if(_zz_318_)begin - if(_zz_192_)begin - _zz_182_ = 1'b1; + _zz_125[0] = execute_SRC1[31]; + _zz_125[1] = execute_SRC1[30]; + _zz_125[2] = execute_SRC1[29]; + _zz_125[3] = execute_SRC1[28]; + _zz_125[4] = execute_SRC1[27]; + _zz_125[5] = execute_SRC1[26]; + _zz_125[6] = execute_SRC1[25]; + _zz_125[7] = execute_SRC1[24]; + _zz_125[8] = execute_SRC1[23]; + _zz_125[9] = execute_SRC1[22]; + _zz_125[10] = execute_SRC1[21]; + _zz_125[11] = execute_SRC1[20]; + _zz_125[12] = execute_SRC1[19]; + _zz_125[13] = execute_SRC1[18]; + _zz_125[14] = execute_SRC1[17]; + _zz_125[15] = execute_SRC1[16]; + _zz_125[16] = execute_SRC1[15]; + _zz_125[17] = execute_SRC1[14]; + _zz_125[18] = execute_SRC1[13]; + _zz_125[19] = execute_SRC1[12]; + _zz_125[20] = execute_SRC1[11]; + _zz_125[21] = execute_SRC1[10]; + _zz_125[22] = execute_SRC1[9]; + _zz_125[23] = execute_SRC1[8]; + _zz_125[24] = execute_SRC1[7]; + _zz_125[25] = execute_SRC1[6]; + _zz_125[26] = execute_SRC1[5]; + _zz_125[27] = execute_SRC1[4]; + _zz_125[28] = execute_SRC1[3]; + _zz_125[29] = execute_SRC1[2]; + _zz_125[30] = execute_SRC1[1]; + _zz_125[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_125 : execute_SRC1); + always @ (*) begin + _zz_126[0] = memory_SHIFT_RIGHT[31]; + _zz_126[1] = memory_SHIFT_RIGHT[30]; + _zz_126[2] = memory_SHIFT_RIGHT[29]; + _zz_126[3] = memory_SHIFT_RIGHT[28]; + _zz_126[4] = memory_SHIFT_RIGHT[27]; + _zz_126[5] = memory_SHIFT_RIGHT[26]; + _zz_126[6] = memory_SHIFT_RIGHT[25]; + _zz_126[7] = memory_SHIFT_RIGHT[24]; + _zz_126[8] = memory_SHIFT_RIGHT[23]; + _zz_126[9] = memory_SHIFT_RIGHT[22]; + _zz_126[10] = memory_SHIFT_RIGHT[21]; + _zz_126[11] = memory_SHIFT_RIGHT[20]; + _zz_126[12] = memory_SHIFT_RIGHT[19]; + _zz_126[13] = memory_SHIFT_RIGHT[18]; + _zz_126[14] = memory_SHIFT_RIGHT[17]; + _zz_126[15] = memory_SHIFT_RIGHT[16]; + _zz_126[16] = memory_SHIFT_RIGHT[15]; + _zz_126[17] = memory_SHIFT_RIGHT[14]; + _zz_126[18] = memory_SHIFT_RIGHT[13]; + _zz_126[19] = memory_SHIFT_RIGHT[12]; + _zz_126[20] = memory_SHIFT_RIGHT[11]; + _zz_126[21] = memory_SHIFT_RIGHT[10]; + _zz_126[22] = memory_SHIFT_RIGHT[9]; + _zz_126[23] = memory_SHIFT_RIGHT[8]; + _zz_126[24] = memory_SHIFT_RIGHT[7]; + _zz_126[25] = memory_SHIFT_RIGHT[6]; + _zz_126[26] = memory_SHIFT_RIGHT[5]; + _zz_126[27] = memory_SHIFT_RIGHT[4]; + _zz_126[28] = memory_SHIFT_RIGHT[3]; + _zz_126[29] = memory_SHIFT_RIGHT[2]; + _zz_126[30] = memory_SHIFT_RIGHT[1]; + _zz_126[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_281)begin + if(_zz_282)begin + if(_zz_127)begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(_zz_283)begin + if(_zz_284)begin + if(_zz_129)begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(_zz_285)begin + if(_zz_286)begin + if(_zz_131)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_182_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_183_ = 1'b0; - if(_zz_313_)begin - if(_zz_314_)begin - if(_zz_189_)begin - _zz_183_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_281)begin + if(_zz_282)begin + if(_zz_128)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_315_)begin - if(_zz_316_)begin - if(_zz_191_)begin - _zz_183_ = 1'b1; + if(_zz_283)begin + if(_zz_284)begin + if(_zz_130)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_317_)begin - if(_zz_318_)begin - if(_zz_193_)begin - _zz_183_ = 1'b1; + if(_zz_285)begin + if(_zz_286)begin + if(_zz_132)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_183_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_184_ = (_zz_60_ && writeBack_arbitration_isFiring); - assign _zz_188_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_189_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_190_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_191_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_192_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_193_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_41_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_127 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_128 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_129 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_130 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_131 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_132 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_194_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_194_ == (3'b000))) begin - _zz_195_ = execute_BranchPlugin_eq; - end else if((_zz_194_ == (3'b001))) begin - _zz_195_ = (! execute_BranchPlugin_eq); - end else if((((_zz_194_ & (3'b101)) == (3'b101)))) begin - _zz_195_ = (! execute_SRC_LESS); + assign _zz_133 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_133 == 3'b000)) begin + _zz_134 = execute_BranchPlugin_eq; + end else if((_zz_133 == 3'b001)) begin + _zz_134 = (! execute_BranchPlugin_eq); + end else if((((_zz_133 & 3'b101) == 3'b101))) begin + _zz_134 = (! execute_SRC_LESS); end else begin - _zz_195_ = execute_SRC_LESS; + _zz_134 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_196_ = 1'b0; + _zz_135 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_196_ = 1'b1; + _zz_135 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_196_ = 1'b1; + _zz_135 = 1'b1; end default : begin - _zz_196_ = _zz_195_; + _zz_135 = _zz_134; end endcase end - assign _zz_40_ = _zz_196_; - assign _zz_197_ = _zz_409_[11]; - always @ (*) begin - _zz_198_[19] = _zz_197_; - _zz_198_[18] = _zz_197_; - _zz_198_[17] = _zz_197_; - _zz_198_[16] = _zz_197_; - _zz_198_[15] = _zz_197_; - _zz_198_[14] = _zz_197_; - _zz_198_[13] = _zz_197_; - _zz_198_[12] = _zz_197_; - _zz_198_[11] = _zz_197_; - _zz_198_[10] = _zz_197_; - _zz_198_[9] = _zz_197_; - _zz_198_[8] = _zz_197_; - _zz_198_[7] = _zz_197_; - _zz_198_[6] = _zz_197_; - _zz_198_[5] = _zz_197_; - _zz_198_[4] = _zz_197_; - _zz_198_[3] = _zz_197_; - _zz_198_[2] = _zz_197_; - _zz_198_[1] = _zz_197_; - _zz_198_[0] = _zz_197_; - end - - assign _zz_199_ = _zz_410_[19]; - always @ (*) begin - _zz_200_[10] = _zz_199_; - _zz_200_[9] = _zz_199_; - _zz_200_[8] = _zz_199_; - _zz_200_[7] = _zz_199_; - _zz_200_[6] = _zz_199_; - _zz_200_[5] = _zz_199_; - _zz_200_[4] = _zz_199_; - _zz_200_[3] = _zz_199_; - _zz_200_[2] = _zz_199_; - _zz_200_[1] = _zz_199_; - _zz_200_[0] = _zz_199_; - end - - assign _zz_201_ = _zz_411_[11]; - always @ (*) begin - _zz_202_[18] = _zz_201_; - _zz_202_[17] = _zz_201_; - _zz_202_[16] = _zz_201_; - _zz_202_[15] = _zz_201_; - _zz_202_[14] = _zz_201_; - _zz_202_[13] = _zz_201_; - _zz_202_[12] = _zz_201_; - _zz_202_[11] = _zz_201_; - _zz_202_[10] = _zz_201_; - _zz_202_[9] = _zz_201_; - _zz_202_[8] = _zz_201_; - _zz_202_[7] = _zz_201_; - _zz_202_[6] = _zz_201_; - _zz_202_[5] = _zz_201_; - _zz_202_[4] = _zz_201_; - _zz_202_[3] = _zz_201_; - _zz_202_[2] = _zz_201_; - _zz_202_[1] = _zz_201_; - _zz_202_[0] = _zz_201_; + assign _zz_136 = _zz_388[11]; + always @ (*) begin + _zz_137[19] = _zz_136; + _zz_137[18] = _zz_136; + _zz_137[17] = _zz_136; + _zz_137[16] = _zz_136; + _zz_137[15] = _zz_136; + _zz_137[14] = _zz_136; + _zz_137[13] = _zz_136; + _zz_137[12] = _zz_136; + _zz_137[11] = _zz_136; + _zz_137[10] = _zz_136; + _zz_137[9] = _zz_136; + _zz_137[8] = _zz_136; + _zz_137[7] = _zz_136; + _zz_137[6] = _zz_136; + _zz_137[5] = _zz_136; + _zz_137[4] = _zz_136; + _zz_137[3] = _zz_136; + _zz_137[2] = _zz_136; + _zz_137[1] = _zz_136; + _zz_137[0] = _zz_136; + end + + assign _zz_138 = _zz_389[19]; + always @ (*) begin + _zz_139[10] = _zz_138; + _zz_139[9] = _zz_138; + _zz_139[8] = _zz_138; + _zz_139[7] = _zz_138; + _zz_139[6] = _zz_138; + _zz_139[5] = _zz_138; + _zz_139[4] = _zz_138; + _zz_139[3] = _zz_138; + _zz_139[2] = _zz_138; + _zz_139[1] = _zz_138; + _zz_139[0] = _zz_138; + end + + assign _zz_140 = _zz_390[11]; + always @ (*) begin + _zz_141[18] = _zz_140; + _zz_141[17] = _zz_140; + _zz_141[16] = _zz_140; + _zz_141[15] = _zz_140; + _zz_141[14] = _zz_140; + _zz_141[13] = _zz_140; + _zz_141[12] = _zz_140; + _zz_141[11] = _zz_140; + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_203_ = (_zz_412_[1] ^ execute_RS1[1]); + _zz_142 = (_zz_391[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_203_ = _zz_413_[1]; + _zz_142 = _zz_392[1]; end default : begin - _zz_203_ = _zz_414_[1]; + _zz_142 = _zz_393[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_203_); - assign _zz_38_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_142); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -5936,167 +5001,176 @@ module VexRiscv ( endcase end - assign _zz_204_ = _zz_415_[11]; + assign _zz_143 = _zz_394[11]; always @ (*) begin - _zz_205_[19] = _zz_204_; - _zz_205_[18] = _zz_204_; - _zz_205_[17] = _zz_204_; - _zz_205_[16] = _zz_204_; - _zz_205_[15] = _zz_204_; - _zz_205_[14] = _zz_204_; - _zz_205_[13] = _zz_204_; - _zz_205_[12] = _zz_204_; - _zz_205_[11] = _zz_204_; - _zz_205_[10] = _zz_204_; - _zz_205_[9] = _zz_204_; - _zz_205_[8] = _zz_204_; - _zz_205_[7] = _zz_204_; - _zz_205_[6] = _zz_204_; - _zz_205_[5] = _zz_204_; - _zz_205_[4] = _zz_204_; - _zz_205_[3] = _zz_204_; - _zz_205_[2] = _zz_204_; - _zz_205_[1] = _zz_204_; - _zz_205_[0] = _zz_204_; + _zz_144[19] = _zz_143; + _zz_144[18] = _zz_143; + _zz_144[17] = _zz_143; + _zz_144[16] = _zz_143; + _zz_144[15] = _zz_143; + _zz_144[14] = _zz_143; + _zz_144[13] = _zz_143; + _zz_144[12] = _zz_143; + _zz_144[11] = _zz_143; + _zz_144[10] = _zz_143; + _zz_144[9] = _zz_143; + _zz_144[8] = _zz_143; + _zz_144[7] = _zz_143; + _zz_144[6] = _zz_143; + _zz_144[5] = _zz_143; + _zz_144[4] = _zz_143; + _zz_144[3] = _zz_143; + _zz_144[2] = _zz_143; + _zz_144[1] = _zz_143; + _zz_144[0] = _zz_143; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_205_,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_144,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_207_,{{{_zz_715_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_209_,{{{_zz_716_,_zz_717_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_146,{{{_zz_693,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_148,{{{_zz_694,_zz_695},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_418_}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_397}; end end endcase end - assign _zz_206_ = _zz_416_[19]; - always @ (*) begin - _zz_207_[10] = _zz_206_; - _zz_207_[9] = _zz_206_; - _zz_207_[8] = _zz_206_; - _zz_207_[7] = _zz_206_; - _zz_207_[6] = _zz_206_; - _zz_207_[5] = _zz_206_; - _zz_207_[4] = _zz_206_; - _zz_207_[3] = _zz_206_; - _zz_207_[2] = _zz_206_; - _zz_207_[1] = _zz_206_; - _zz_207_[0] = _zz_206_; - end - - assign _zz_208_ = _zz_417_[11]; - always @ (*) begin - _zz_209_[18] = _zz_208_; - _zz_209_[17] = _zz_208_; - _zz_209_[16] = _zz_208_; - _zz_209_[15] = _zz_208_; - _zz_209_[14] = _zz_208_; - _zz_209_[13] = _zz_208_; - _zz_209_[12] = _zz_208_; - _zz_209_[11] = _zz_208_; - _zz_209_[10] = _zz_208_; - _zz_209_[9] = _zz_208_; - _zz_209_[8] = _zz_208_; - _zz_209_[7] = _zz_208_; - _zz_209_[6] = _zz_208_; - _zz_209_[5] = _zz_208_; - _zz_209_[4] = _zz_208_; - _zz_209_[3] = _zz_208_; - _zz_209_[2] = _zz_208_; - _zz_209_[1] = _zz_208_; - _zz_209_[0] = _zz_208_; + assign _zz_145 = _zz_395[19]; + always @ (*) begin + _zz_146[10] = _zz_145; + _zz_146[9] = _zz_145; + _zz_146[8] = _zz_145; + _zz_146[7] = _zz_145; + _zz_146[6] = _zz_145; + _zz_146[5] = _zz_145; + _zz_146[4] = _zz_145; + _zz_146[3] = _zz_145; + _zz_146[2] = _zz_145; + _zz_146[1] = _zz_145; + _zz_146[0] = _zz_145; + end + + assign _zz_147 = _zz_396[11]; + always @ (*) begin + _zz_148[18] = _zz_147; + _zz_148[17] = _zz_147; + _zz_148[16] = _zz_147; + _zz_148[15] = _zz_147; + _zz_148[14] = _zz_147; + _zz_148[13] = _zz_147; + _zz_148[12] = _zz_147; + _zz_148[11] = _zz_147; + _zz_148[10] = _zz_147; + _zz_148[9] = _zz_147; + _zz_148[8] = _zz_147; + _zz_148[7] = _zz_147; + _zz_148[6] = _zz_147; + _zz_148[5] = _zz_147; + _zz_148[4] = _zz_147; + _zz_148[3] = _zz_147; + _zz_148[2] = _zz_147; + _zz_148[1] = _zz_147; + _zz_148[0] = _zz_147; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_37_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = _zz_210_; + CsrPlugin_privilege = _zz_149; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign CsrPlugin_misa_base = (2'b01); - assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0; assign CsrPlugin_sip_SEIP_OR = (CsrPlugin_sip_SEIP_SOFT || CsrPlugin_sip_SEIP_INPUT); - assign _zz_211_ = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); - assign _zz_212_ = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); - assign _zz_213_ = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); - assign _zz_214_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_215_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_216_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + always @ (*) begin + CsrPlugin_redoInterface_valid = 1'b0; + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + CsrPlugin_redoInterface_valid = 1'b1; + end + end + end + + assign CsrPlugin_redoInterface_payload = decode_PC; + assign _zz_150 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_151 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_152 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_153 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_154 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_155 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) - 4'b1000 : begin - if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0000 : begin + if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0001 : begin + if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0010 : begin if(((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0101 : begin - if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0100 : begin + if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b1101 : begin - if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0101 : begin + if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0100 : begin - if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0110 : begin + if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0111 : begin if(((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0001 : begin - if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b1000 : begin + if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1001 : begin if(((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1100 : begin if(((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); - end - end - 4'b1111 : begin - if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0110 : begin - if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b1101 : begin + if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0000 : begin - if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b1111 : begin + if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end default : begin @@ -6105,11 +5179,11 @@ module VexRiscv ( end assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_217_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_218_ = _zz_419_[0]; + assign _zz_156 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_157 = _zz_398[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_300_)begin + if(_zz_270)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -6152,9 +5226,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -6178,7 +5253,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_mode = CsrPlugin_stvec_mode; @@ -6192,7 +5267,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_base = CsrPlugin_stvec_base; @@ -6206,131 +5281,118 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_35_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_34_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - always @ (*) begin - execute_CsrPlugin_inWfi = 1'b0; - if(_zz_301_)begin - execute_CsrPlugin_inWfi = 1'b1; - end - end - - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000011 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111100010001 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000010 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b111100010100 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b100111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b000100000000 : begin + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000010 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000001 : begin + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_256)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_384)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000110000000 : begin + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110011000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000001 : begin + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000100 : begin + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000100000101 : begin + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000000 : begin + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_770)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000011 : begin + end + if(execute_CsrPlugin_csr_771)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000000 : begin + end + if(execute_CsrPlugin_csr_324)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_260)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_261)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_321)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_320)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_322)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_323)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000100000100 : begin + end + if(execute_CsrPlugin_csr_2496)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3520)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_287)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -6349,29 +5411,29 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_319_)begin + if(_zz_288)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_320_)begin + if(_zz_289)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_319_)begin - CsrPlugin_selfException_payload_code = (4'b0010); + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_288)begin + CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_320_)begin + if(_zz_289)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end 2'b01 : begin - CsrPlugin_selfException_payload_code = (4'b1001); + CsrPlugin_selfException_payload_code = 4'b1001; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -6379,145 +5441,33 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_226_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[19 : 19] = MmuPlugin_status_mxr; - execute_CsrPlugin_readData[18 : 18] = MmuPlugin_status_sum; - execute_CsrPlugin_readData[17 : 17] = MmuPlugin_status_mprv; - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - execute_CsrPlugin_readData[8 : 8] = CsrPlugin_sstatus_SPP; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sstatus_SPIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sstatus_SIE; - end - 12'b001100000011 : begin - end - 12'b111100010001 : begin - execute_CsrPlugin_readData[0 : 0] = (1'b1); - end - 12'b000101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_scause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_scause_exceptionCode; - end - 12'b111100010100 : begin - end - 12'b100111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_228_; - end - 12'b000100000000 : begin - execute_CsrPlugin_readData[19 : 19] = MmuPlugin_status_mxr; - execute_CsrPlugin_readData[18 : 18] = MmuPlugin_status_sum; - execute_CsrPlugin_readData[17 : 17] = MmuPlugin_status_mprv; - execute_CsrPlugin_readData[8 : 8] = CsrPlugin_sstatus_SPP; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sstatus_SPIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sstatus_SIE; - end - 12'b001100000010 : begin - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sip_STIP; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sip_SSIP; - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sip_SEIP_OR; - end - 12'b001100000101 : begin - end - 12'b000110000000 : begin - execute_CsrPlugin_readData[31 : 31] = MmuPlugin_satp_mode; - execute_CsrPlugin_readData[19 : 0] = MmuPlugin_satp_ppn; - end - 12'b110011000000 : begin - execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); - execute_CsrPlugin_readData[25 : 20] = (6'b100000); - end - 12'b000101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_sepc; - end - 12'b111100010011 : begin - execute_CsrPlugin_readData[1 : 0] = (2'b11); - end - 12'b000101000100 : begin - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sip_STIP; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sip_SSIP; - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sip_SEIP_OR; - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b000100000101 : begin - execute_CsrPlugin_readData[31 : 2] = CsrPlugin_stvec_base; - execute_CsrPlugin_readData[1 : 0] = CsrPlugin_stvec_mode; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_227_; - end - 12'b001101000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sie_SEIE; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sie_STIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sie_SSIE; - end - 12'b111100010010 : begin - execute_CsrPlugin_readData[1 : 0] = (2'b10); - end - 12'b000101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_stval; - end - 12'b110111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_229_; - end - 12'b000101000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_sscratch; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - 12'b000100000100 : begin - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sie_SEIE; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sie_STIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sie_SSIE; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_287)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_287)begin + execute_CsrPlugin_readInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); always @ (*) begin execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - case(execute_CsrPlugin_csrAddress) - 12'b001101000100 : begin - execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; - end - 12'b000101000100 : begin - execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; - end - default : begin - end - endcase + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; + end + if(execute_CsrPlugin_csr_324)begin + execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; + end end always @ (*) begin - case(_zz_347_) + case(_zz_316) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -6528,10 +5478,10 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_MulPlugin_a = execute_SRC1; - assign execute_MulPlugin_b = execute_SRC2; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_321_) + case(_zz_290) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -6545,7 +5495,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_321_) + case(_zz_290) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -6564,16 +5514,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign _zz_31_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign _zz_30_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - assign _zz_28_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - assign _zz_27_ = ($signed(_zz_421_) + $signed(_zz_429_)); - assign writeBack_MulPlugin_result = ($signed(_zz_430_) + $signed(_zz_431_)); + assign writeBack_MulPlugin_result = ($signed(_zz_400) + $signed(_zz_401)); + assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_295_)begin - if(_zz_302_)begin + if(_zz_265)begin + if(_zz_291)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -6581,70 +5527,72 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_322_)begin + if(_zz_292)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end - assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); always @ (*) begin if(memory_DivPlugin_div_counter_willOverflow)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_435_); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_405); end if(memory_DivPlugin_div_counter_willClear)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); - end - end - - assign _zz_219_ = memory_DivPlugin_rs1[31 : 0]; - assign _zz_220_ = {memory_DivPlugin_accumulator[31 : 0],_zz_219_[31]}; - assign _zz_221_ = (_zz_220_ - _zz_436_); - assign _zz_222_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_223_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_224_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_225_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_225_[31 : 0] = execute_RS1; - end - - assign _zz_227_ = (_zz_226_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_227_ != (32'b00000000000000000000000000000000)); - assign _zz_229_ = (_zz_228_ & externalInterruptArray_regNext); - assign externalInterruptS = (_zz_229_ != (32'b00000000000000000000000000000000)); - assign _zz_26_ = decode_ENV_CTRL; - assign _zz_23_ = execute_ENV_CTRL; - assign _zz_21_ = memory_ENV_CTRL; - assign _zz_24_ = _zz_73_; - assign _zz_33_ = decode_to_execute_ENV_CTRL; - assign _zz_32_ = execute_to_memory_ENV_CTRL; - assign _zz_36_ = memory_to_writeBack_ENV_CTRL; - assign _zz_19_ = decode_SRC2_CTRL; - assign _zz_17_ = _zz_78_; - assign _zz_51_ = decode_to_execute_SRC2_CTRL; - assign _zz_16_ = decode_ALU_BITWISE_CTRL; - assign _zz_14_ = _zz_67_; - assign _zz_58_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_13_ = decode_SRC1_CTRL; - assign _zz_11_ = _zz_81_; - assign _zz_53_ = decode_to_execute_SRC1_CTRL; - assign _zz_10_ = decode_ALU_CTRL; - assign _zz_8_ = _zz_82_; - assign _zz_56_ = decode_to_execute_ALU_CTRL; - assign _zz_7_ = decode_SHIFT_CTRL; - assign _zz_4_ = execute_SHIFT_CTRL; - assign _zz_5_ = _zz_77_; - assign _zz_46_ = decode_to_execute_SHIFT_CTRL; - assign _zz_44_ = execute_to_memory_SHIFT_CTRL; - assign _zz_2_ = decode_BRANCH_CTRL; - assign _zz_99_ = _zz_70_; - assign _zz_39_ = decode_to_execute_BRANCH_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_158 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_158[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_406); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_407 : _zz_408); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_409[31:0]; + assign _zz_159 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_160 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_161 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_162[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_162[31 : 0] = execute_RS1; + end + + assign _zz_164 = (_zz_163 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_164 != 32'h0); + assign _zz_166 = (_zz_165 & externalInterruptArray_regNext); + assign externalInterruptS = (_zz_166 != 32'h0); + assign _zz_26 = decode_SRC1_CTRL; + assign _zz_24 = _zz_49; + assign _zz_37 = decode_to_execute_SRC1_CTRL; + assign _zz_23 = decode_ALU_CTRL; + assign _zz_21 = _zz_48; + assign _zz_38 = decode_to_execute_ALU_CTRL; + assign _zz_20 = decode_SRC2_CTRL; + assign _zz_18 = _zz_47; + assign _zz_36 = decode_to_execute_SRC2_CTRL; + assign _zz_17 = decode_ALU_BITWISE_CTRL; + assign _zz_15 = _zz_46; + assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_14 = decode_SHIFT_CTRL; + assign _zz_11 = execute_SHIFT_CTRL; + assign _zz_12 = _zz_45; + assign _zz_34 = decode_to_execute_SHIFT_CTRL; + assign _zz_33 = execute_to_memory_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_52 = _zz_44; + assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_43; + assign _zz_28 = decode_to_execute_ENV_CTRL; + assign _zz_27 = execute_to_memory_ENV_CTRL; + assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -6661,66 +5609,268 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign iBusWishbone_ADR = {_zz_494_,_zz_230_}; - assign iBusWishbone_CTI = ((_zz_230_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); - assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); always @ (*) begin - iBusWishbone_CYC = 1'b0; - if(_zz_323_)begin - iBusWishbone_CYC = 1'b1; + _zz_167 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_167[12 : 0] = 13'h1000; + _zz_167[25 : 20] = 6'h20; end end always @ (*) begin - iBusWishbone_STB = 1'b0; - if(_zz_323_)begin - iBusWishbone_STB = 1'b1; + _zz_168 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_168[19 : 19] = MmuPlugin_status_mxr; + _zz_168[18 : 18] = MmuPlugin_status_sum; + _zz_168[17 : 17] = MmuPlugin_status_mprv; + _zz_168[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_168[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_168[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_168[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_168[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_168[1 : 1] = CsrPlugin_sstatus_SIE; end end - assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_231_; - assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; - assign iBus_rsp_payload_error = 1'b0; - assign _zz_237_ = (dBus_cmd_payload_length != (3'b000)); - assign _zz_233_ = dBus_cmd_valid; - assign _zz_235_ = dBus_cmd_payload_wr; - assign _zz_236_ = (_zz_232_ == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_234_ && (_zz_235_ || _zz_236_)); - assign dBusWishbone_ADR = ((_zz_237_ ? {{dBus_cmd_payload_address[31 : 5],_zz_232_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); - assign dBusWishbone_CTI = (_zz_237_ ? (_zz_236_ ? (3'b111) : (3'b010)) : (3'b000)); - assign dBusWishbone_BTE = (2'b00); - assign dBusWishbone_SEL = (_zz_235_ ? dBus_cmd_payload_mask : (4'b1111)); - assign dBusWishbone_WE = _zz_235_; - assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_234_ = (_zz_233_ && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_233_; - assign dBusWishbone_STB = _zz_233_; - assign dBus_rsp_valid = _zz_238_; - assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; - assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin - if(reset) begin - IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; - IBusCachedPlugin_fetchPc_booted <= 1'b0; - IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_116_ <= 1'b0; - _zz_118_ <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + always @ (*) begin + _zz_169 = 32'h0; + if(execute_CsrPlugin_csr_256)begin + _zz_169[19 : 19] = MmuPlugin_status_mxr; + _zz_169[18 : 18] = MmuPlugin_status_sum; + _zz_169[17 : 17] = MmuPlugin_status_mprv; + _zz_169[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_169[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_169[1 : 1] = CsrPlugin_sstatus_SIE; + end + end + + always @ (*) begin + _zz_170 = 32'h0; + if(execute_CsrPlugin_csr_384)begin + _zz_170[31 : 31] = MmuPlugin_satp_mode; + _zz_170[30 : 22] = MmuPlugin_satp_asid; + _zz_170[19 : 0] = MmuPlugin_satp_ppn; + end + end + + always @ (*) begin + _zz_171 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_171[0 : 0] = 1'b1; + end + end + + always @ (*) begin + _zz_172 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_172[1 : 0] = 2'b10; + end + end + + always @ (*) begin + _zz_173 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_173[1 : 0] = 2'b11; + end + end + + always @ (*) begin + _zz_174 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_174[11 : 11] = CsrPlugin_mip_MEIP; + _zz_174[7 : 7] = CsrPlugin_mip_MTIP; + _zz_174[3 : 3] = CsrPlugin_mip_MSIP; + _zz_174[5 : 5] = CsrPlugin_sip_STIP; + _zz_174[1 : 1] = CsrPlugin_sip_SSIP; + _zz_174[9 : 9] = CsrPlugin_sip_SEIP_OR; + end + end + + always @ (*) begin + _zz_175 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_175[11 : 11] = CsrPlugin_mie_MEIE; + _zz_175[7 : 7] = CsrPlugin_mie_MTIE; + _zz_175[3 : 3] = CsrPlugin_mie_MSIE; + _zz_175[9 : 9] = CsrPlugin_sie_SEIE; + _zz_175[5 : 5] = CsrPlugin_sie_STIE; + _zz_175[1 : 1] = CsrPlugin_sie_SSIE; + end + end + + always @ (*) begin + _zz_176 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_176[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_177[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_178[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_178[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_179[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_324)begin + _zz_180[5 : 5] = CsrPlugin_sip_STIP; + _zz_180[1 : 1] = CsrPlugin_sip_SSIP; + _zz_180[9 : 9] = CsrPlugin_sip_SEIP_OR; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_260)begin + _zz_181[9 : 9] = CsrPlugin_sie_SEIE; + _zz_181[5 : 5] = CsrPlugin_sie_STIE; + _zz_181[1 : 1] = CsrPlugin_sie_SSIE; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_261)begin + _zz_182[31 : 2] = CsrPlugin_stvec_base; + _zz_182[1 : 0] = CsrPlugin_stvec_mode; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_321)begin + _zz_183[31 : 0] = CsrPlugin_sepc; + end + end + + always @ (*) begin + _zz_184 = 32'h0; + if(execute_CsrPlugin_csr_320)begin + _zz_184[31 : 0] = CsrPlugin_sscratch; + end + end + + always @ (*) begin + _zz_185 = 32'h0; + if(execute_CsrPlugin_csr_322)begin + _zz_185[31 : 31] = CsrPlugin_scause_interrupt; + _zz_185[3 : 0] = CsrPlugin_scause_exceptionCode; + end + end + + always @ (*) begin + _zz_186 = 32'h0; + if(execute_CsrPlugin_csr_323)begin + _zz_186[31 : 0] = CsrPlugin_stval; + end + end + + always @ (*) begin + _zz_187 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_187[31 : 0] = _zz_163; + end + end + + always @ (*) begin + _zz_188 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_188[31 : 0] = _zz_164; + end + end + + always @ (*) begin + _zz_189 = 32'h0; + if(execute_CsrPlugin_csr_2496)begin + _zz_189[31 : 0] = _zz_165; + end + end + + always @ (*) begin + _zz_190 = 32'h0; + if(execute_CsrPlugin_csr_3520)begin + _zz_190[31 : 0] = _zz_166; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_167 | _zz_168) | (_zz_169 | _zz_170)) | ((_zz_171 | _zz_172) | (_zz_173 | _zz_696))) | (((_zz_174 | _zz_175) | (_zz_176 | _zz_177)) | ((_zz_178 | _zz_179) | (_zz_180 | _zz_181)))) | ((((_zz_182 | _zz_183) | (_zz_184 | _zz_185)) | ((_zz_186 | _zz_187) | (_zz_188 | _zz_189))) | _zz_190)); + assign iBusWishbone_ADR = {_zz_464,_zz_191}; + assign iBusWishbone_CTI = ((_zz_191 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_293)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_293)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_192; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_198 = (dBus_cmd_payload_length != 3'b000); + assign _zz_194 = dBus_cmd_valid; + assign _zz_196 = dBus_cmd_payload_wr; + assign _zz_197 = (_zz_193 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_195 && (_zz_196 || _zz_197)); + assign dBusWishbone_ADR = ((_zz_198 ? {{dBus_cmd_payload_address[31 : 5],_zz_193},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_198 ? (_zz_197 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_196 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_196; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_195 = (_zz_194 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_194; + assign dBusWishbone_STB = _zz_194; + assign dBus_rsp_valid = _zz_199; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_67 <= 1'b0; + _zz_69 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_131_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_132_ <= 1'b0; - _zz_139_ <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_146_; - DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); + IBusCachedPlugin_rspCounter <= _zz_82; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_83; + DBusCachedPlugin_rspCounter <= 32'h0; MmuPlugin_status_sum <= 1'b0; MmuPlugin_status_mxr <= 1'b0; MmuPlugin_status_mprv <= 1'b0; @@ -6729,19 +5879,20 @@ module VexRiscv ( MmuPlugin_ports_0_cache_1_valid <= 1'b0; MmuPlugin_ports_0_cache_2_valid <= 1'b0; MmuPlugin_ports_0_cache_3_valid <= 1'b0; - MmuPlugin_ports_0_entryToReplace_value <= (2'b00); + MmuPlugin_ports_0_entryToReplace_value <= 2'b00; MmuPlugin_ports_1_cache_0_valid <= 1'b0; MmuPlugin_ports_1_cache_1_valid <= 1'b0; MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; - MmuPlugin_ports_1_entryToReplace_value <= (2'b00); - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE; - _zz_172_ <= 1'b1; - _zz_185_ <= 1'b0; - _zz_210_ <= (2'b11); + MmuPlugin_ports_1_entryToReplace_value <= 2'b00; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; + _zz_117 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_149 <= 2'b11; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -6762,7 +5913,7 @@ module VexRiscv ( CsrPlugin_mideleg_SS <= 1'b0; CsrPlugin_sstatus_SIE <= 1'b0; CsrPlugin_sstatus_SPIE <= 1'b0; - CsrPlugin_sstatus_SPP <= (1'b1); + CsrPlugin_sstatus_SPP <= 1'b1; CsrPlugin_sip_SEIP_SOFT <= 1'b0; CsrPlugin_sip_STIP <= 1'b0; CsrPlugin_sip_SSIP <= 1'b0; @@ -6775,25 +5926,32 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_DivPlugin_div_counter_value <= (6'b000000); - _zz_226_ <= (32'b00000000000000000000000000000000); - _zz_228_ <= (32'b00000000000000000000000000000000); + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_163 <= 32'h0; + _zz_165 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_IS_DBUS_SHARING <= 1'b0; memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_230_ <= (3'b000); - _zz_231_ <= 1'b0; - _zz_232_ <= (3'b000); - _zz_238_ <= 1'b0; + _zz_191 <= 3'b000; + _zz_192 <= 1'b0; + _zz_193 <= 3'b000; + _zz_199 <= 1'b0; end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin @@ -6802,83 +5960,77 @@ module VexRiscv ( if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_116_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_67 <= 1'b0; end - if(_zz_114_)begin - _zz_116_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if(_zz_65)begin + _zz_67 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_118_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_69 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_118_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_69 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_132_ <= 1'b0; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_324_)begin - _zz_132_ <= dataCache_1__io_mem_cmd_valid; + if(_zz_294)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_139_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end if(dBus_rsp_valid)begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; if(contextSwitching)begin @@ -6910,71 +6062,69 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_valid <= 1'b0; end end - case(MmuPlugin_shared_state_1_) + MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; + case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_325_)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; - end - if(_zz_326_)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + if(_zz_295)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; end end `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; end end `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin - if(MmuPlugin_dBusAccess_rsp_valid)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; end - if(MmuPlugin_dBusAccess_rsp_payload_redo)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; end end end `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; end end default : begin - if(MmuPlugin_dBusAccess_rsp_valid)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE; - if(MmuPlugin_dBusAccess_rsp_payload_redo)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; end end end endcase - if(_zz_310_)begin - if(_zz_311_)begin - if(_zz_327_)begin + if(_zz_278)begin + if(_zz_279)begin + if(_zz_296)begin MmuPlugin_ports_0_cache_0_valid <= 1'b1; end - if(_zz_328_)begin + if(_zz_297)begin MmuPlugin_ports_0_cache_1_valid <= 1'b1; end - if(_zz_329_)begin + if(_zz_298)begin MmuPlugin_ports_0_cache_2_valid <= 1'b1; end - if(_zz_330_)begin + if(_zz_299)begin MmuPlugin_ports_0_cache_3_valid <= 1'b1; end end - if(_zz_312_)begin - if(_zz_331_)begin + if(_zz_280)begin + if(_zz_300)begin MmuPlugin_ports_1_cache_0_valid <= 1'b1; end - if(_zz_332_)begin + if(_zz_301)begin MmuPlugin_ports_1_cache_1_valid <= 1'b1; end - if(_zz_333_)begin + if(_zz_302)begin MmuPlugin_ports_1_cache_2_valid <= 1'b1; end - if(_zz_334_)begin + if(_zz_303)begin MmuPlugin_ports_1_cache_3_valid <= 1'b1; end end @@ -6989,8 +6139,8 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - _zz_172_ <= 1'b0; - _zz_185_ <= _zz_184_; + _zz_117 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -7012,41 +6162,60 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_335_)begin - if(_zz_336_)begin + if(_zz_304)begin + if(_zz_305)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_337_)begin + if(_zz_306)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_338_)begin + if(_zz_307)begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(_zz_339_)begin - if(_zz_340_)begin + if(_zz_308)begin + if(_zz_309)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_341_)begin + if(_zz_310)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_342_)begin + if(_zz_311)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_343_)begin + if(_zz_312)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_344_)begin + if(_zz_313)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_345_)begin + if(_zz_314)begin CsrPlugin_interrupt_valid <= 1'b1; end end CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_303_)begin - _zz_210_ <= CsrPlugin_targetPrivilege; + if(_zz_272)begin + _zz_149 <= CsrPlugin_targetPrivilege; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_sstatus_SIE <= 1'b0; @@ -7062,32 +6231,26 @@ module VexRiscv ( end endcase end - if(_zz_304_)begin - case(_zz_305_) + if(_zz_273)begin + case(_zz_274) 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; - _zz_210_ <= CsrPlugin_mstatus_MPP; + _zz_149 <= CsrPlugin_mstatus_MPP; end 2'b01 : begin - CsrPlugin_sstatus_SPP <= (1'b0); + CsrPlugin_sstatus_SPP <= 1'b0; CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; CsrPlugin_sstatus_SPIE <= 1'b1; - _zz_210_ <= {(1'b0),CsrPlugin_sstatus_SPP}; + _zz_149 <= {1'b0,CsrPlugin_sstatus_SPP}; end default : begin end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_216_,{_zz_215_,{_zz_214_,{_zz_213_,{_zz_212_,_zz_211_}}}}} != (6'b000000)); + execute_CsrPlugin_wfiWake <= (({_zz_155,{_zz_154,{_zz_153,{_zz_152,{_zz_151,_zz_150}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_43_; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end if((! memory_arbitration_isStuck))begin execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; end @@ -7115,715 +6278,2004 @@ module VexRiscv ( if(MmuPlugin_dBusAccess_rsp_valid)begin memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_226_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_449_[0]; - MmuPlugin_status_sum <= _zz_450_[0]; - MmuPlugin_status_mprv <= _zz_451_[0]; - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_452_[0]; - CsrPlugin_mstatus_MIE <= _zz_453_[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_454_[0]; - CsrPlugin_sstatus_SIE <= _zz_455_[0]; - end - end - 12'b001100000011 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mideleg_SE <= _zz_456_[0]; - CsrPlugin_mideleg_ST <= _zz_457_[0]; - CsrPlugin_mideleg_SS <= _zz_458_[0]; - end - end - 12'b111100010001 : begin - end - 12'b000101000010 : begin - end - 12'b111100010100 : begin - end - 12'b100111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_228_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b000100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_460_[0]; - MmuPlugin_status_sum <= _zz_461_[0]; - MmuPlugin_status_mprv <= _zz_462_[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_463_[0]; - CsrPlugin_sstatus_SIE <= _zz_464_[0]; - end - end - 12'b001100000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_medeleg_EU <= _zz_465_[0]; - CsrPlugin_medeleg_II <= _zz_466_[0]; - CsrPlugin_medeleg_LAF <= _zz_467_[0]; - CsrPlugin_medeleg_LPF <= _zz_468_[0]; - CsrPlugin_medeleg_LAM <= _zz_469_[0]; - CsrPlugin_medeleg_SAF <= _zz_470_[0]; - CsrPlugin_medeleg_IAF <= _zz_471_[0]; - CsrPlugin_medeleg_ES <= _zz_472_[0]; - CsrPlugin_medeleg_IPF <= _zz_473_[0]; - CsrPlugin_medeleg_SPF <= _zz_474_[0]; - CsrPlugin_medeleg_SAM <= _zz_475_[0]; - CsrPlugin_medeleg_IAM <= _zz_476_[0]; - end - end - 12'b001101000001 : begin - end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_478_[0]; - CsrPlugin_sip_SSIP <= _zz_479_[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_480_[0]; - end - end - 12'b001100000101 : begin - end - 12'b000110000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_mode <= _zz_481_[0]; - end - end - 12'b110011000000 : begin - end - 12'b000101000001 : begin - end - 12'b111100010011 : begin - end - 12'b000101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_482_[0]; - CsrPlugin_sip_SSIP <= _zz_483_[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_484_[0]; - end - end - 12'b001101000011 : begin - end - 12'b000100000101 : begin - end - 12'b111111000000 : begin + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_status_mxr <= _zz_419[0]; + MmuPlugin_status_sum <= _zz_420[0]; + MmuPlugin_status_mprv <= _zz_421[0]; + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_422[0]; + CsrPlugin_mstatus_MIE <= _zz_423[0]; + CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; + CsrPlugin_sstatus_SPIE <= _zz_424[0]; + CsrPlugin_sstatus_SIE <= _zz_425[0]; + end + end + if(execute_CsrPlugin_csr_256)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_status_mxr <= _zz_426[0]; + MmuPlugin_status_sum <= _zz_427[0]; + MmuPlugin_status_mprv <= _zz_428[0]; + CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; + CsrPlugin_sstatus_SPIE <= _zz_429[0]; + CsrPlugin_sstatus_SIE <= _zz_430[0]; end - 12'b001101000000 : begin + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_485_[0]; - CsrPlugin_mie_MTIE <= _zz_486_[0]; - CsrPlugin_mie_MSIE <= _zz_487_[0]; - CsrPlugin_sie_SEIE <= _zz_488_[0]; - CsrPlugin_sie_STIE <= _zz_489_[0]; - CsrPlugin_sie_SSIE <= _zz_490_[0]; - end + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_mode <= _zz_431[0]; end - 12'b111100010010 : begin + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sip_STIP <= _zz_433[0]; + CsrPlugin_sip_SSIP <= _zz_434[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_435[0]; end - 12'b000101000011 : begin + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_436[0]; + CsrPlugin_mie_MTIE <= _zz_437[0]; + CsrPlugin_mie_MSIE <= _zz_438[0]; + CsrPlugin_sie_SEIE <= _zz_439[0]; + CsrPlugin_sie_STIE <= _zz_440[0]; + CsrPlugin_sie_SSIE <= _zz_441[0]; end - 12'b110111000000 : begin + end + if(execute_CsrPlugin_csr_770)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_medeleg_IAM <= _zz_442[0]; + CsrPlugin_medeleg_IAF <= _zz_443[0]; + CsrPlugin_medeleg_II <= _zz_444[0]; + CsrPlugin_medeleg_LAM <= _zz_445[0]; + CsrPlugin_medeleg_LAF <= _zz_446[0]; + CsrPlugin_medeleg_SAM <= _zz_447[0]; + CsrPlugin_medeleg_SAF <= _zz_448[0]; + CsrPlugin_medeleg_EU <= _zz_449[0]; + CsrPlugin_medeleg_ES <= _zz_450[0]; + CsrPlugin_medeleg_IPF <= _zz_451[0]; + CsrPlugin_medeleg_LPF <= _zz_452[0]; + CsrPlugin_medeleg_SPF <= _zz_453[0]; + end + end + if(execute_CsrPlugin_csr_771)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mideleg_SE <= _zz_454[0]; + CsrPlugin_mideleg_ST <= _zz_455[0]; + CsrPlugin_mideleg_SS <= _zz_456[0]; end - 12'b000101000000 : begin + end + if(execute_CsrPlugin_csr_324)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sip_STIP <= _zz_457[0]; + CsrPlugin_sip_SSIP <= _zz_458[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_459[0]; end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_260)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sie_SEIE <= _zz_460[0]; + CsrPlugin_sie_STIE <= _zz_461[0]; + CsrPlugin_sie_SSIE <= _zz_462[0]; end - 12'b000100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sie_SEIE <= _zz_491_[0]; - CsrPlugin_sie_STIE <= _zz_492_[0]; - CsrPlugin_sie_SSIE <= _zz_493_[0]; - end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; end - default : begin + end + if(execute_CsrPlugin_csr_2496)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; end - endcase - if(_zz_323_)begin + end + if(_zz_293)begin if(iBusWishbone_ACK)begin - _zz_230_ <= (_zz_230_ + (3'b001)); + _zz_191 <= (_zz_191 + 3'b001); end end - _zz_231_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_233_ && _zz_234_))begin - _zz_232_ <= (_zz_232_ + (3'b001)); - if(_zz_236_)begin - _zz_232_ <= (3'b000); + _zz_192 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_194 && _zz_195))begin + _zz_193 <= (_zz_193 + 3'b001); + if(_zz_197)begin + _zz_193 <= 3'b000; end end - _zz_238_ <= ((_zz_233_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_199 <= ((_zz_194 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_119_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_70 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin - IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_294)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; + MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; + MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; + if((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)))begin + MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; + MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G; + MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A; + MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D; + MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW; + MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; + end + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + if(_zz_295)begin + MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; + MmuPlugin_shared_vpn_1 <= _zz_102[31 : 22]; + MmuPlugin_shared_vpn_0 <= _zz_102[21 : 12]; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + end + default : begin + end + endcase + if(_zz_278)begin + if(_zz_279)begin + if(_zz_296)begin + MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_297)begin + MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_298)begin + MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_299)begin + MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + if(_zz_280)begin + if(_zz_300)begin + MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_301)begin + MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_302)begin + MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_303)begin + MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_sip_SEIP_INPUT <= externalInterruptS; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_270)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_157 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_157 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_304)begin + if(_zz_305)begin + CsrPlugin_interrupt_code <= 4'b0101; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + if(_zz_306)begin + CsrPlugin_interrupt_code <= 4'b0001; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + if(_zz_307)begin + CsrPlugin_interrupt_code <= 4'b1001; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + end + if(_zz_308)begin + if(_zz_309)begin + CsrPlugin_interrupt_code <= 4'b0101; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_310)begin + CsrPlugin_interrupt_code <= 4'b0001; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_311)begin + CsrPlugin_interrupt_code <= 4'b1001; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_312)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_313)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_314)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_272)begin + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_sepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_265)begin + if(_zz_291)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_410[31:0]; + end + end + end + if(_zz_292)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_161 ? (~ _zz_162) : _zz_162) + _zz_416); + memory_DivPlugin_rs2 <= ((_zz_160 ? (~ execute_RS2) : execute_RS2) + _zz_418); + memory_DivPlugin_div_needRevert <= ((_zz_161 ^ (_zz_160 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_35; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_55; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_53; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_54; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_770 <= (decode_INSTRUCTION[31 : 20] == 12'h302); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_771 <= (decode_INSTRUCTION[31 : 20] == 12'h303); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_324 <= (decode_INSTRUCTION[31 : 20] == 12'h144); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_260 <= (decode_INSTRUCTION[31 : 20] == 12'h104); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_261 <= (decode_INSTRUCTION[31 : 20] == 12'h105); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_321 <= (decode_INSTRUCTION[31 : 20] == 12'h141); end - if(_zz_324_)begin - _zz_133_ <= dataCache_1__io_mem_cmd_payload_wr; - _zz_134_ <= dataCache_1__io_mem_cmd_payload_address; - _zz_135_ <= dataCache_1__io_mem_cmd_payload_data; - _zz_136_ <= dataCache_1__io_mem_cmd_payload_mask; - _zz_137_ <= dataCache_1__io_mem_cmd_payload_length; - _zz_138_ <= dataCache_1__io_mem_cmd_payload_last; - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_140_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - _zz_141_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; - _zz_142_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; - _zz_143_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - _zz_144_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; - _zz_145_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; - end - if((MmuPlugin_dBusAccess_rsp_valid && (! MmuPlugin_dBusAccess_rsp_payload_redo)))begin - MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; - MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G; - MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A; - MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D; - MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW; - MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_320 <= (decode_INSTRUCTION[31 : 20] == 12'h140); end - case(MmuPlugin_shared_state_1_) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_325_)begin - MmuPlugin_shared_vpn_1 <= IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22]; - MmuPlugin_shared_vpn_0 <= IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]; - MmuPlugin_shared_portId <= (1'b0); - end - if(_zz_326_)begin - MmuPlugin_shared_vpn_1 <= DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22]; - MmuPlugin_shared_vpn_0 <= DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]; - MmuPlugin_shared_portId <= (1'b1); - end - end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin - end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin - end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin - end - default : begin - end - endcase - if(_zz_310_)begin - if(_zz_311_)begin - if(_zz_327_)begin - MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_328_)begin - MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_329_)begin - MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_0_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_0_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_330_)begin - MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_0_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_0_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - end - if(_zz_312_)begin - if(_zz_331_)begin - MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_332_)begin - MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_333_)begin - MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_1_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_1_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_334_)begin - MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_1_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_1_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_322 <= (decode_INSTRUCTION[31 : 20] == 12'h142); end - if(_zz_184_)begin - _zz_186_ <= _zz_59_[11 : 7]; - _zz_187_ <= _zz_93_; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_323 <= (decode_INSTRUCTION[31 : 20] == 12'h143); end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_sip_SEIP_INPUT <= externalInterruptS; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if(_zz_300_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_218_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_218_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2496 <= (decode_INSTRUCTION[31 : 20] == 12'h9c0); end - if(BranchPlugin_branchExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3520 <= (decode_INSTRUCTION[31 : 20] == 12'hdc0); end - if(DBusCachedPlugin_exceptionBus_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_asid <= execute_CsrPlugin_writeData[30 : 22]; + MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; + end end - if(_zz_335_)begin - if(_zz_336_)begin - CsrPlugin_interrupt_code <= (4'b0101); - CsrPlugin_interrupt_targetPrivilege <= (2'b01); + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_432[0]; end - if(_zz_337_)begin - CsrPlugin_interrupt_code <= (4'b0001); - CsrPlugin_interrupt_targetPrivilege <= (2'b01); + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - if(_zz_338_)begin - CsrPlugin_interrupt_code <= (4'b1001); - CsrPlugin_interrupt_targetPrivilege <= (2'b01); + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_339_)begin - if(_zz_340_)begin - CsrPlugin_interrupt_code <= (4'b0101); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; end - if(_zz_341_)begin - CsrPlugin_interrupt_code <= (4'b0001); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_261)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - if(_zz_342_)begin - CsrPlugin_interrupt_code <= (4'b1001); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_321)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0]; end - if(_zz_343_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_320)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0]; end - if(_zz_344_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_322)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_scause_interrupt <= _zz_463[0]; + CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end - if(_zz_345_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_323)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_303_)begin - case(CsrPlugin_targetPrivilege) - 2'b01 : begin - CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_sepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - default : begin - end - endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_isLrsc, + input io_cpu_execute_args_isAmo, + input io_cpu_execute_args_amoCtrl_swap, + input [2:0] io_cpu_execute_args_amoCtrl_alu, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_memory_mmuRsp_ways_0_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_0_physical, + input io_cpu_memory_mmuRsp_ways_1_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_1_physical, + input io_cpu_memory_mmuRsp_ways_2_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_2_physical, + input io_cpu_memory_mmuRsp_ways_3_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_3_physical, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire _zz_19; + wire _zz_20; + wire _zz_21; + wire _zz_22; + wire [2:0] _zz_23; + wire [0:0] _zz_24; + wire [0:0] _zz_25; + wire [9:0] _zz_26; + wire [9:0] _zz_27; + wire [31:0] _zz_28; + wire [31:0] _zz_29; + wire [31:0] _zz_30; + wire [31:0] _zz_31; + wire [1:0] _zz_32; + wire [31:0] _zz_33; + wire [1:0] _zz_34; + wire [1:0] _zz_35; + wire [0:0] _zz_36; + wire [0:0] _zz_37; + wire [0:0] _zz_38; + wire [2:0] _zz_39; + wire [1:0] _zz_40; + wire [21:0] _zz_41; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_isLrsc; + reg stageA_request_isAmo; + reg stageA_request_amoCtrl_swap; + reg [2:0] stageA_request_amoCtrl_alu; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_isLrsc; + reg stageB_request_isAmo; + reg stageB_request_amoCtrl_swap; + reg [2:0] stageB_request_amoCtrl_alu; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_mmuRsp_ways_0_sel; + reg [31:0] stageB_mmuRsp_ways_0_physical; + reg stageB_mmuRsp_ways_1_sel; + reg [31:0] stageB_mmuRsp_ways_1_physical; + reg stageB_mmuRsp_ways_2_sel; + reg [31:0] stageB_mmuRsp_ways_2_physical; + reg stageB_mmuRsp_ways_3_sel; + reg [31:0] stageB_mmuRsp_ways_3_physical; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + reg stageB_lrSc_reserved; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + reg [31:0] stageB_requestDataBypass; + wire stageB_amo_compare; + wire stageB_amo_unsigned; + wire [31:0] stageB_amo_addSub; + wire stageB_amo_less; + wire stageB_amo_selectRf; + reg [31:0] stageB_amo_result; + reg [31:0] stageB_amo_resultReg; + reg stageB_amo_internal_resultRegValid; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_42; + reg [7:0] _zz_43; + reg [7:0] _zz_44; + reg [7:0] _zz_45; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_15 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); + assign _zz_16 = (! stageB_amo_internal_resultRegValid); + assign _zz_17 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign _zz_18 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_19 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign _zz_20 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign _zz_21 = (! stageB_flusher_hold); + assign _zz_22 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_23 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); + assign _zz_24 = _zz_4[0 : 0]; + assign _zz_25 = _zz_4[1 : 1]; + assign _zz_26 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_27 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_28 = ($signed(_zz_29) + $signed(_zz_33)); + assign _zz_29 = ($signed(_zz_30) + $signed(_zz_31)); + assign _zz_30 = stageB_request_data; + assign _zz_31 = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux); + assign _zz_32 = (stageB_amo_compare ? _zz_34 : _zz_35); + assign _zz_33 = {{30{_zz_32[1]}}, _zz_32}; + assign _zz_34 = 2'b01; + assign _zz_35 = 2'b00; + assign _zz_36 = 1'b1; + assign _zz_37 = (! stageB_lrSc_reserved); + assign _zz_38 = loader_counter_willIncrement; + assign _zz_39 = {2'd0, _zz_38}; + assign _zz_40 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_41 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; end - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_done <= 1'b1; + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_41; end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + end + + always @ (*) begin + _zz_11 = {_zz_45, _zz_44, _zz_43, _zz_42}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_42 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_43 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_44 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_45 <= ways_0_data_symbol3[dataReadCmd_payload]; end - if(_zz_295_)begin - if(_zz_302_)begin - memory_DivPlugin_rs1[31 : 0] <= _zz_437_[31:0]; - memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_221_[32]) ? _zz_438_ : _zz_439_); - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_result <= _zz_440_[31:0]; - end - end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end - if(_zz_322_)begin - memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_DivPlugin_rs1 <= ((_zz_224_ ? (~ _zz_225_) : _zz_225_) + _zz_446_); - memory_DivPlugin_rs2 <= ((_zz_223_ ? (~ execute_RS2) : execute_RS2) + _zz_448_); - memory_DivPlugin_div_needRevert <= ((_zz_224_ ^ (_zz_223_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end - externalInterruptArray_regNext <= externalInterruptArray; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_42_; + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_25_; + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_22_; + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_24[0]; + assign ways_0_tagsReadRsp_error = _zz_25[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_20_; + end + + always @ (*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + + always @ (*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_18_; + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_15_; + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LL <= execute_MUL_LL; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + if(stageB_request_isAmo)begin + if(_zz_16)begin + dataWriteCmd_valid = 1'b0; + end + end + if(_zz_17)begin + dataWriteCmd_valid = 1'b0; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + if(_zz_18)begin + dataWriteCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; + if(_zz_18)begin + dataWriteCmd_payload_way = loader_waysAllocator; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HL <= execute_MUL_HL; + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + if(_zz_18)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_12_; + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + if(_zz_18)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_36[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HH <= execute_MUL_HH; + if(_zz_18)begin + dataWriteCmd_payload_mask = 4'b1111; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_26)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_27)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(! _zz_15) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + if(_zz_13)begin + stageB_loaderValid = 1'b0; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_14)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(_zz_19)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_15)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(stageB_request_isAmo)begin + if(_zz_16)begin + io_cpu_writeBack_haltIt = 1'b1; + end + end + if(_zz_17)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_9_; + end + + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + always @ (*) begin + stageB_requestDataBypass = stageB_request_data; + if(stageB_request_isAmo)begin + stageB_requestDataBypass = stageB_amo_resultReg; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_6_; + end + + assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; + assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == 2'b11); + assign stageB_amo_addSub = _zz_28; + assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31])); + assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); + always @ (*) begin + case(_zz_23) + 3'b000 : begin + stageB_amo_result = stageB_amo_addSub; + end + 3'b001 : begin + stageB_amo_result = (stageB_request_data ^ stageB_dataMux); + end + 3'b010 : begin + stageB_amo_result = (stageB_request_data | stageB_dataMux); + end + 3'b011 : begin + stageB_amo_result = (stageB_request_data & stageB_dataMux); + end + default : begin + stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux); + end + endcase + end + + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_3_; + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_request_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + if(_zz_20)begin + io_cpu_redo = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_50_; + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_14)begin + io_mem_cmd_valid = (! memCmdSent); + if(_zz_19)begin + io_mem_cmd_valid = 1'b0; + end + end else begin + if(_zz_15)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + if(stageB_request_isAmo)begin + if(_zz_16)begin + io_mem_cmd_valid = 1'b0; + end + end + if(_zz_20)begin + io_mem_cmd_valid = 1'b0; + end + if(_zz_17)begin + io_mem_cmd_valid = 1'b0; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LH <= execute_MUL_LH; + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(! _zz_15) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + if((stageB_request_isLrsc && stageB_request_wr))begin + io_cpu_writeBack_data = {31'd0, _zz_37}; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_18)begin + loader_counter_willIncrement = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_39); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_1_; + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; + stageA_request_isAmo <= io_cpu_execute_args_isAmo; + stageA_request_amoCtrl_swap <= io_cpu_execute_args_amoCtrl_swap; + stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_101_; + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_100_; + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_isLrsc <= stageA_request_isLrsc; + stageB_request_isAmo <= stageA_request_isAmo; + stageB_request_amoCtrl_swap <= stageA_request_amoCtrl_swap; + stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + stageB_mmuRsp_ways_0_sel <= io_cpu_memory_mmuRsp_ways_0_sel; + stageB_mmuRsp_ways_0_physical <= io_cpu_memory_mmuRsp_ways_0_physical; + stageB_mmuRsp_ways_1_sel <= io_cpu_memory_mmuRsp_ways_1_sel; + stageB_mmuRsp_ways_1_physical <= io_cpu_memory_mmuRsp_ways_1_physical; + stageB_mmuRsp_ways_2_sel <= io_cpu_memory_mmuRsp_ways_2_sel; + stageB_mmuRsp_ways_2_physical <= io_cpu_memory_mmuRsp_ways_2_physical; + stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; + stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_MUL <= decode_IS_MUL; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b001100000011 : begin - end - 12'b111100010001 : begin - end - 12'b000101000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_scause_interrupt <= _zz_459_[0]; - CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(stageB_flusher_valid)begin + if(_zz_21)begin + if(_zz_22)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); end end - 12'b111100010100 : begin - end - 12'b100111000000 : begin - end - 12'b000100000000 : begin - end - 12'b001100000010 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + stageB_amo_internal_resultRegValid <= io_cpu_writeBack_isStuck; + stageB_amo_resultReg <= stageB_amo_result; + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + stageB_lrSc_reserved <= 1'b0; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_477_[0]; - end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(stageB_flusher_valid)begin + if(_zz_21)begin + if(! _zz_22) begin + stageB_flusher_valid <= 1'b0; + end end end - 12'b000110000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; - end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; end - 12'b110011000000 : begin + if(((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc))begin + stageB_lrSc_reserved <= (! stageB_request_wr); end - 12'b000101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0]; - end + if(_zz_13)begin + stageB_lrSc_reserved <= stageB_lrSc_reserved; end - 12'b111100010011 : begin + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; end - 12'b000101000100 : begin + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; end - 12'b001101000011 : begin + if(_zz_18)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); end - 12'b000100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; end - 12'b111111000000 : begin + if((! loader_valid))begin + loader_waysAllocator <= _zz_40[0:0]; end - 12'b001101000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; - end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + input io_cpu_fetch_mmuRsp_ways_0_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_0_physical, + input io_cpu_fetch_mmuRsp_ways_1_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_1_physical, + input io_cpu_fetch_mmuRsp_ways_2_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_2_physical, + input io_cpu_fetch_mmuRsp_ways_3_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_3_physical, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_9; + reg [21:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [21:0] _zz_15; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_mmuRsp_ways_0_sel; + reg [31:0] decodeStage_mmuRsp_ways_0_physical; + reg decodeStage_mmuRsp_ways_1_sel; + reg [31:0] decodeStage_mmuRsp_ways_1_physical; + reg decodeStage_mmuRsp_ways_2_sel; + reg [31:0] decodeStage_mmuRsp_ways_2_physical; + reg decodeStage_mmuRsp_ways_3_sel; + reg [31:0] decodeStage_mmuRsp_ways_3_physical; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_11 = (! lineLoader_flushCounter[7]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; end - 12'b001100000100 : begin + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; end - 12'b111100010010 : begin + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; end - 12'b000101000011 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0]; - end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end - 12'b110111000000 : begin + if(io_flush)begin + lineLoader_flushPending <= 1'b1; end - 12'b000101000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0]; - end + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; end - 12'b001101000010 : begin + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; end - 12'b000100000100 : begin + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; end - default : begin + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end end - endcase - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end end -endmodule + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_12)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + decodeStage_mmuRsp_ways_0_sel <= io_cpu_fetch_mmuRsp_ways_0_sel; + decodeStage_mmuRsp_ways_0_physical <= io_cpu_fetch_mmuRsp_ways_0_physical; + decodeStage_mmuRsp_ways_1_sel <= io_cpu_fetch_mmuRsp_ways_1_sel; + decodeStage_mmuRsp_ways_1_physical <= io_cpu_fetch_mmuRsp_ways_1_physical; + decodeStage_mmuRsp_ways_2_sel <= io_cpu_fetch_mmuRsp_ways_2_sel; + decodeStage_mmuRsp_ways_2_physical <= io_cpu_fetch_mmuRsp_ways_2_physical; + decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; + decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v index f712883..b4f3b34 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v @@ -1,13 +1,19 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:07:34 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 `define ShiftCtrlEnum_defaultEncoding_type [1:0] `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 @@ -15,11 +21,6 @@ `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - `define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] `define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 @@ -31,17 +32,16 @@ `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 `define MmuPlugin_shared_State_defaultEncoding_type [2:0] `define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000 @@ -50,3815 +50,2804 @@ `define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011 `define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100 -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input [2:0] _zz_10_, - input [31:0] _zz_11_, - input clk, - input reset); - reg [21:0] _zz_12_; - reg [31:0] _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire [0:0] _zz_16_; - wire [0:0] _zz_17_; - wire [21:0] _zz_18_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [6:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_7_; - wire [9:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - reg [31:0] io_cpu_fetch_data_regNextWhen; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_hit_valid; - reg decodeStage_hit_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; - assign _zz_14_ = (! lineLoader_flushCounter[7]); - assign _zz_15_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_16_ = _zz_7_[0 : 0]; - assign _zz_17_ = _zz_7_[1 : 1]; - assign _zz_18_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_18_; - end - end - always @ (posedge clk) begin - if(_zz_6_) begin - _zz_12_ <= ways_0_tags[_zz_5_]; - end - end +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_203; + wire _zz_204; + wire _zz_205; + wire _zz_206; + wire _zz_207; + wire _zz_208; + wire _zz_209; + wire _zz_210; + reg _zz_211; + reg _zz_212; + reg [31:0] _zz_213; + reg _zz_214; + reg [31:0] _zz_215; + reg [1:0] _zz_216; + reg _zz_217; + reg _zz_218; + wire _zz_219; + wire [2:0] _zz_220; + reg _zz_221; + wire [31:0] _zz_222; + reg _zz_223; + reg _zz_224; + wire _zz_225; + wire [31:0] _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire [3:0] _zz_235; + wire _zz_236; + wire _zz_237; + reg [31:0] _zz_238; + reg [31:0] _zz_239; + reg [31:0] _zz_240; + reg _zz_241; + reg _zz_242; + reg _zz_243; + reg [9:0] _zz_244; + reg [9:0] _zz_245; + reg [9:0] _zz_246; + reg [9:0] _zz_247; + reg _zz_248; + reg _zz_249; + reg _zz_250; + reg _zz_251; + reg _zz_252; + reg _zz_253; + reg _zz_254; + reg [9:0] _zz_255; + reg [9:0] _zz_256; + reg [9:0] _zz_257; + reg [9:0] _zz_258; + reg _zz_259; + reg _zz_260; + reg _zz_261; + reg _zz_262; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire [1:0] _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire _zz_284; + wire _zz_285; + wire _zz_286; + wire _zz_287; + wire _zz_288; + wire _zz_289; + wire _zz_290; + wire _zz_291; + wire _zz_292; + wire _zz_293; + wire _zz_294; + wire _zz_295; + wire [1:0] _zz_296; + wire _zz_297; + wire _zz_298; + wire [5:0] _zz_299; + wire _zz_300; + wire _zz_301; + wire _zz_302; + wire _zz_303; + wire _zz_304; + wire _zz_305; + wire _zz_306; + wire _zz_307; + wire _zz_308; + wire _zz_309; + wire _zz_310; + wire _zz_311; + wire _zz_312; + wire _zz_313; + wire _zz_314; + wire _zz_315; + wire _zz_316; + wire _zz_317; + wire _zz_318; + wire _zz_319; + wire _zz_320; + wire _zz_321; + wire [1:0] _zz_322; + wire _zz_323; + wire [1:0] _zz_324; + wire [51:0] _zz_325; + wire [51:0] _zz_326; + wire [51:0] _zz_327; + wire [32:0] _zz_328; + wire [51:0] _zz_329; + wire [49:0] _zz_330; + wire [51:0] _zz_331; + wire [49:0] _zz_332; + wire [51:0] _zz_333; + wire [32:0] _zz_334; + wire [31:0] _zz_335; + wire [32:0] _zz_336; + wire [0:0] _zz_337; + wire [0:0] _zz_338; + wire [0:0] _zz_339; + wire [0:0] _zz_340; + wire [0:0] _zz_341; + wire [0:0] _zz_342; + wire [0:0] _zz_343; + wire [0:0] _zz_344; + wire [0:0] _zz_345; + wire [0:0] _zz_346; + wire [0:0] _zz_347; + wire [0:0] _zz_348; + wire [0:0] _zz_349; + wire [0:0] _zz_350; + wire [0:0] _zz_351; + wire [0:0] _zz_352; + wire [0:0] _zz_353; + wire [0:0] _zz_354; + wire [0:0] _zz_355; + wire [0:0] _zz_356; + wire [0:0] _zz_357; + wire [4:0] _zz_358; + wire [2:0] _zz_359; + wire [31:0] _zz_360; + wire [11:0] _zz_361; + wire [31:0] _zz_362; + wire [19:0] _zz_363; + wire [11:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire [19:0] _zz_367; + wire [11:0] _zz_368; + wire [2:0] _zz_369; + wire [2:0] _zz_370; + wire [0:0] _zz_371; + wire [1:0] _zz_372; + wire [0:0] _zz_373; + wire [1:0] _zz_374; + wire [0:0] _zz_375; + wire [0:0] _zz_376; + wire [0:0] _zz_377; + wire [0:0] _zz_378; + wire [0:0] _zz_379; + wire [0:0] _zz_380; + wire [0:0] _zz_381; + wire [0:0] _zz_382; + wire [1:0] _zz_383; + wire [0:0] _zz_384; + wire [2:0] _zz_385; + wire [4:0] _zz_386; + wire [11:0] _zz_387; + wire [11:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire [31:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire [11:0] _zz_396; + wire [19:0] _zz_397; + wire [11:0] _zz_398; + wire [31:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; + wire [11:0] _zz_402; + wire [19:0] _zz_403; + wire [11:0] _zz_404; + wire [2:0] _zz_405; + wire [1:0] _zz_406; + wire [1:0] _zz_407; + wire [65:0] _zz_408; + wire [65:0] _zz_409; + wire [31:0] _zz_410; + wire [31:0] _zz_411; + wire [0:0] _zz_412; + wire [5:0] _zz_413; + wire [32:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [32:0] _zz_417; + wire [32:0] _zz_418; + wire [32:0] _zz_419; + wire [32:0] _zz_420; + wire [0:0] _zz_421; + wire [32:0] _zz_422; + wire [0:0] _zz_423; + wire [32:0] _zz_424; + wire [0:0] _zz_425; + wire [31:0] _zz_426; + wire [0:0] _zz_427; + wire [0:0] _zz_428; + wire [0:0] _zz_429; + wire [0:0] _zz_430; + wire [0:0] _zz_431; + wire [0:0] _zz_432; + wire [0:0] _zz_433; + wire [0:0] _zz_434; + wire [0:0] _zz_435; + wire [0:0] _zz_436; + wire [0:0] _zz_437; + wire [0:0] _zz_438; + wire [0:0] _zz_439; + wire [0:0] _zz_440; + wire [0:0] _zz_441; + wire [0:0] _zz_442; + wire [0:0] _zz_443; + wire [0:0] _zz_444; + wire [0:0] _zz_445; + wire [0:0] _zz_446; + wire [0:0] _zz_447; + wire [0:0] _zz_448; + wire [0:0] _zz_449; + wire [0:0] _zz_450; + wire [0:0] _zz_451; + wire [0:0] _zz_452; + wire [0:0] _zz_453; + wire [0:0] _zz_454; + wire [0:0] _zz_455; + wire [0:0] _zz_456; + wire [0:0] _zz_457; + wire [0:0] _zz_458; + wire [0:0] _zz_459; + wire [0:0] _zz_460; + wire [0:0] _zz_461; + wire [0:0] _zz_462; + wire [0:0] _zz_463; + wire [0:0] _zz_464; + wire [0:0] _zz_465; + wire [0:0] _zz_466; + wire [0:0] _zz_467; + wire [0:0] _zz_468; + wire [0:0] _zz_469; + wire [0:0] _zz_470; + wire [0:0] _zz_471; + wire [26:0] _zz_472; + wire _zz_473; + wire _zz_474; + wire [2:0] _zz_475; + wire [31:0] _zz_476; + wire [31:0] _zz_477; + wire [31:0] _zz_478; + wire _zz_479; + wire [0:0] _zz_480; + wire [17:0] _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire _zz_485; + wire [0:0] _zz_486; + wire [11:0] _zz_487; + wire [31:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; + wire _zz_491; + wire [0:0] _zz_492; + wire [5:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire _zz_497; + wire _zz_498; + wire _zz_499; + wire _zz_500; + wire _zz_501; + wire [31:0] _zz_502; + wire [0:0] _zz_503; + wire [0:0] _zz_504; + wire _zz_505; + wire [0:0] _zz_506; + wire [29:0] _zz_507; + wire [31:0] _zz_508; + wire _zz_509; + wire _zz_510; + wire _zz_511; + wire [1:0] _zz_512; + wire [1:0] _zz_513; + wire _zz_514; + wire [0:0] _zz_515; + wire [25:0] _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire [31:0] _zz_520; + wire _zz_521; + wire _zz_522; + wire [1:0] _zz_523; + wire [1:0] _zz_524; + wire _zz_525; + wire [0:0] _zz_526; + wire [22:0] _zz_527; + wire [31:0] _zz_528; + wire [31:0] _zz_529; + wire [31:0] _zz_530; + wire [31:0] _zz_531; + wire _zz_532; + wire [0:0] _zz_533; + wire [0:0] _zz_534; + wire _zz_535; + wire [0:0] _zz_536; + wire [0:0] _zz_537; + wire _zz_538; + wire [0:0] _zz_539; + wire [19:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire [31:0] _zz_543; + wire _zz_544; + wire _zz_545; + wire _zz_546; + wire [0:0] _zz_547; + wire [0:0] _zz_548; + wire _zz_549; + wire [0:0] _zz_550; + wire [16:0] _zz_551; + wire [31:0] _zz_552; + wire [31:0] _zz_553; + wire [31:0] _zz_554; + wire [0:0] _zz_555; + wire [2:0] _zz_556; + wire [0:0] _zz_557; + wire [0:0] _zz_558; + wire _zz_559; + wire [0:0] _zz_560; + wire [13:0] _zz_561; + wire [31:0] _zz_562; + wire [31:0] _zz_563; + wire [31:0] _zz_564; + wire _zz_565; + wire _zz_566; + wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [0:0] _zz_570; + wire [4:0] _zz_571; + wire [2:0] _zz_572; + wire [2:0] _zz_573; + wire _zz_574; + wire [0:0] _zz_575; + wire [10:0] _zz_576; + wire [31:0] _zz_577; + wire [31:0] _zz_578; + wire [31:0] _zz_579; + wire [31:0] _zz_580; + wire _zz_581; + wire [0:0] _zz_582; + wire [2:0] _zz_583; + wire _zz_584; + wire [0:0] _zz_585; + wire [0:0] _zz_586; + wire [0:0] _zz_587; + wire [3:0] _zz_588; + wire [4:0] _zz_589; + wire [4:0] _zz_590; + wire _zz_591; + wire [0:0] _zz_592; + wire [8:0] _zz_593; + wire [31:0] _zz_594; + wire [31:0] _zz_595; + wire [31:0] _zz_596; + wire _zz_597; + wire [0:0] _zz_598; + wire [0:0] _zz_599; + wire [31:0] _zz_600; + wire [31:0] _zz_601; + wire [31:0] _zz_602; + wire [31:0] _zz_603; + wire [31:0] _zz_604; + wire [31:0] _zz_605; + wire [31:0] _zz_606; + wire _zz_607; + wire [0:0] _zz_608; + wire [1:0] _zz_609; + wire [0:0] _zz_610; + wire [2:0] _zz_611; + wire [0:0] _zz_612; + wire [5:0] _zz_613; + wire [1:0] _zz_614; + wire [1:0] _zz_615; + wire _zz_616; + wire [0:0] _zz_617; + wire [6:0] _zz_618; + wire [31:0] _zz_619; + wire [31:0] _zz_620; + wire [31:0] _zz_621; + wire [31:0] _zz_622; + wire [31:0] _zz_623; + wire [31:0] _zz_624; + wire [31:0] _zz_625; + wire [31:0] _zz_626; + wire _zz_627; + wire [31:0] _zz_628; + wire [31:0] _zz_629; + wire _zz_630; + wire [0:0] _zz_631; + wire [0:0] _zz_632; + wire _zz_633; + wire [0:0] _zz_634; + wire [3:0] _zz_635; + wire _zz_636; + wire [0:0] _zz_637; + wire [0:0] _zz_638; + wire [0:0] _zz_639; + wire [0:0] _zz_640; + wire _zz_641; + wire [0:0] _zz_642; + wire [4:0] _zz_643; + wire [31:0] _zz_644; + wire [31:0] _zz_645; + wire [31:0] _zz_646; + wire [31:0] _zz_647; + wire [31:0] _zz_648; + wire [31:0] _zz_649; + wire [31:0] _zz_650; + wire [31:0] _zz_651; + wire [31:0] _zz_652; + wire _zz_653; + wire [0:0] _zz_654; + wire [1:0] _zz_655; + wire [31:0] _zz_656; + wire [31:0] _zz_657; + wire [31:0] _zz_658; + wire [31:0] _zz_659; + wire [31:0] _zz_660; + wire _zz_661; + wire [4:0] _zz_662; + wire [4:0] _zz_663; + wire _zz_664; + wire [0:0] _zz_665; + wire [2:0] _zz_666; + wire [31:0] _zz_667; + wire [31:0] _zz_668; + wire [31:0] _zz_669; + wire _zz_670; + wire [31:0] _zz_671; + wire _zz_672; + wire [0:0] _zz_673; + wire [2:0] _zz_674; + wire [0:0] _zz_675; + wire [0:0] _zz_676; + wire [2:0] _zz_677; + wire [2:0] _zz_678; + wire _zz_679; + wire [0:0] _zz_680; + wire [0:0] _zz_681; + wire [31:0] _zz_682; + wire [31:0] _zz_683; + wire [31:0] _zz_684; + wire [31:0] _zz_685; + wire _zz_686; + wire [0:0] _zz_687; + wire [0:0] _zz_688; + wire [31:0] _zz_689; + wire [31:0] _zz_690; + wire _zz_691; + wire [0:0] _zz_692; + wire [0:0] _zz_693; + wire [0:0] _zz_694; + wire [1:0] _zz_695; + wire [1:0] _zz_696; + wire [1:0] _zz_697; + wire [0:0] _zz_698; + wire [0:0] _zz_699; + wire [31:0] _zz_700; + wire [31:0] _zz_701; + wire [31:0] _zz_702; + wire [31:0] _zz_703; + wire [31:0] _zz_704; + wire [31:0] _zz_705; + wire [31:0] _zz_706; + wire [31:0] _zz_707; + wire _zz_708; + wire _zz_709; + wire _zz_710; + wire [31:0] _zz_711; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire execute_IS_DBUS_SHARING; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire decode_SRC_LESS_UNSIGNED; + wire memory_IS_SFENCE_VMA; + wire execute_IS_SFENCE_VMA; + wire decode_IS_SFENCE_VMA; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_31; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_35; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_36; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; + wire [31:0] _zz_40; + wire _zz_41; + reg _zz_42; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_43; + wire `BranchCtrlEnum_defaultEncoding_type _zz_44; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; + wire `Src2CtrlEnum_defaultEncoding_type _zz_47; + wire `AluCtrlEnum_defaultEncoding_type _zz_48; + wire `Src1CtrlEnum_defaultEncoding_type _zz_49; + wire writeBack_IS_SFENCE_VMA; + wire writeBack_IS_DBUS_SHARING; + wire memory_IS_DBUS_SHARING; + reg [31:0] _zz_50; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_AMO; + wire execute_MEMORY_LRSC; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_AMO; + wire decode_MEMORY_LRSC; + reg _zz_51; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_52; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_53; + reg [31:0] _zz_54; + reg [31:0] _zz_55; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg IBusCachedPlugin_mmuBus_rsp_isPaging; + reg IBusCachedPlugin_mmuBus_rsp_allowRead; + reg IBusCachedPlugin_mmuBus_rsp_allowWrite; + reg IBusCachedPlugin_mmuBus_rsp_allowExecute; + reg IBusCachedPlugin_mmuBus_rsp_exception; + reg IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + reg DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg DBusCachedPlugin_mmuBus_rsp_isPaging; + reg DBusCachedPlugin_mmuBus_rsp_allowRead; + reg DBusCachedPlugin_mmuBus_rsp_allowWrite; + reg DBusCachedPlugin_mmuBus_rsp_allowExecute; + reg DBusCachedPlugin_mmuBus_rsp_exception; + reg DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_56; + reg MmuPlugin_dBusAccess_cmd_valid; + reg MmuPlugin_dBusAccess_cmd_ready; + reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; + wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; + wire MmuPlugin_dBusAccess_cmd_payload_write; + wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; + wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; + wire MmuPlugin_dBusAccess_rsp_valid; + wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; + wire MmuPlugin_dBusAccess_rsp_payload_error; + wire MmuPlugin_dBusAccess_rsp_payload_redo; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + reg CsrPlugin_redoInterface_valid; + wire [31:0] CsrPlugin_redoInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire externalInterruptS; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_57; + wire [4:0] _zz_58; + wire _zz_59; + wire _zz_60; + wire _zz_61; + wire _zz_62; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_63; + wire _zz_64; + wire _zz_65; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_66; + wire _zz_67; + reg _zz_68; + wire _zz_69; + reg _zz_70; + reg [31:0] _zz_71; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_72; + reg [18:0] _zz_73; + wire _zz_74; + reg [10:0] _zz_75; + wire _zz_76; + reg [18:0] _zz_77; + reg _zz_78; + wire _zz_79; + reg [10:0] _zz_80; + wire _zz_81; + reg [18:0] _zz_82; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_83; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_84; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_85; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_86; + reg [31:0] _zz_87; + wire _zz_88; + reg [31:0] _zz_89; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + reg DBusCachedPlugin_forceDatapath; + reg MmuPlugin_status_sum; + reg MmuPlugin_status_mxr; + reg MmuPlugin_status_mprv; + reg MmuPlugin_satp_mode; + reg [8:0] MmuPlugin_satp_asid; + reg [19:0] MmuPlugin_satp_ppn; + reg MmuPlugin_ports_0_cache_0_valid; + reg MmuPlugin_ports_0_cache_0_exception; + reg MmuPlugin_ports_0_cache_0_superPage; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; + reg MmuPlugin_ports_0_cache_0_allowRead; + reg MmuPlugin_ports_0_cache_0_allowWrite; + reg MmuPlugin_ports_0_cache_0_allowExecute; + reg MmuPlugin_ports_0_cache_0_allowUser; + reg MmuPlugin_ports_0_cache_1_valid; + reg MmuPlugin_ports_0_cache_1_exception; + reg MmuPlugin_ports_0_cache_1_superPage; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; + reg MmuPlugin_ports_0_cache_1_allowRead; + reg MmuPlugin_ports_0_cache_1_allowWrite; + reg MmuPlugin_ports_0_cache_1_allowExecute; + reg MmuPlugin_ports_0_cache_1_allowUser; + reg MmuPlugin_ports_0_cache_2_valid; + reg MmuPlugin_ports_0_cache_2_exception; + reg MmuPlugin_ports_0_cache_2_superPage; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; + reg MmuPlugin_ports_0_cache_2_allowRead; + reg MmuPlugin_ports_0_cache_2_allowWrite; + reg MmuPlugin_ports_0_cache_2_allowExecute; + reg MmuPlugin_ports_0_cache_2_allowUser; + reg MmuPlugin_ports_0_cache_3_valid; + reg MmuPlugin_ports_0_cache_3_exception; + reg MmuPlugin_ports_0_cache_3_superPage; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; + reg MmuPlugin_ports_0_cache_3_allowRead; + reg MmuPlugin_ports_0_cache_3_allowWrite; + reg MmuPlugin_ports_0_cache_3_allowExecute; + reg MmuPlugin_ports_0_cache_3_allowUser; + wire MmuPlugin_ports_0_dirty; + reg MmuPlugin_ports_0_requireMmuLockupCalc; + reg [3:0] MmuPlugin_ports_0_cacheHitsCalc; + wire MmuPlugin_ports_0_cacheHit; + wire _zz_90; + wire _zz_91; + wire _zz_92; + wire [1:0] _zz_93; + wire MmuPlugin_ports_0_cacheLine_valid; + wire MmuPlugin_ports_0_cacheLine_exception; + wire MmuPlugin_ports_0_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_0_cacheLine_allowRead; + wire MmuPlugin_ports_0_cacheLine_allowWrite; + wire MmuPlugin_ports_0_cacheLine_allowExecute; + wire MmuPlugin_ports_0_cacheLine_allowUser; + reg MmuPlugin_ports_0_entryToReplace_willIncrement; + wire MmuPlugin_ports_0_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_0_entryToReplace_value; + wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_0_entryToReplace_willOverflow; + reg MmuPlugin_ports_1_cache_0_valid; + reg MmuPlugin_ports_1_cache_0_exception; + reg MmuPlugin_ports_1_cache_0_superPage; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; + reg MmuPlugin_ports_1_cache_0_allowRead; + reg MmuPlugin_ports_1_cache_0_allowWrite; + reg MmuPlugin_ports_1_cache_0_allowExecute; + reg MmuPlugin_ports_1_cache_0_allowUser; + reg MmuPlugin_ports_1_cache_1_valid; + reg MmuPlugin_ports_1_cache_1_exception; + reg MmuPlugin_ports_1_cache_1_superPage; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; + reg MmuPlugin_ports_1_cache_1_allowRead; + reg MmuPlugin_ports_1_cache_1_allowWrite; + reg MmuPlugin_ports_1_cache_1_allowExecute; + reg MmuPlugin_ports_1_cache_1_allowUser; + reg MmuPlugin_ports_1_cache_2_valid; + reg MmuPlugin_ports_1_cache_2_exception; + reg MmuPlugin_ports_1_cache_2_superPage; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; + reg MmuPlugin_ports_1_cache_2_allowRead; + reg MmuPlugin_ports_1_cache_2_allowWrite; + reg MmuPlugin_ports_1_cache_2_allowExecute; + reg MmuPlugin_ports_1_cache_2_allowUser; + reg MmuPlugin_ports_1_cache_3_valid; + reg MmuPlugin_ports_1_cache_3_exception; + reg MmuPlugin_ports_1_cache_3_superPage; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; + reg MmuPlugin_ports_1_cache_3_allowRead; + reg MmuPlugin_ports_1_cache_3_allowWrite; + reg MmuPlugin_ports_1_cache_3_allowExecute; + reg MmuPlugin_ports_1_cache_3_allowUser; + wire MmuPlugin_ports_1_dirty; + reg MmuPlugin_ports_1_requireMmuLockupCalc; + reg [3:0] MmuPlugin_ports_1_cacheHitsCalc; + wire MmuPlugin_ports_1_cacheHit; + wire _zz_94; + wire _zz_95; + wire _zz_96; + wire [1:0] _zz_97; + wire MmuPlugin_ports_1_cacheLine_valid; + wire MmuPlugin_ports_1_cacheLine_exception; + wire MmuPlugin_ports_1_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_1_cacheLine_allowRead; + wire MmuPlugin_ports_1_cacheLine_allowWrite; + wire MmuPlugin_ports_1_cacheLine_allowExecute; + wire MmuPlugin_ports_1_cacheLine_allowUser; + reg MmuPlugin_ports_1_entryToReplace_willIncrement; + wire MmuPlugin_ports_1_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_1_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_1_entryToReplace_value; + wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_1_entryToReplace_willOverflow; + reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1; + reg [9:0] MmuPlugin_shared_vpn_0; + reg [9:0] MmuPlugin_shared_vpn_1; + reg [1:0] MmuPlugin_shared_portSortedOh; + reg MmuPlugin_shared_dBusRspStaged_valid; + reg [31:0] MmuPlugin_shared_dBusRspStaged_payload_data; + reg MmuPlugin_shared_dBusRspStaged_payload_error; + reg MmuPlugin_shared_dBusRspStaged_payload_redo; + wire MmuPlugin_shared_dBusRsp_pte_V; + wire MmuPlugin_shared_dBusRsp_pte_R; + wire MmuPlugin_shared_dBusRsp_pte_W; + wire MmuPlugin_shared_dBusRsp_pte_X; + wire MmuPlugin_shared_dBusRsp_pte_U; + wire MmuPlugin_shared_dBusRsp_pte_G; + wire MmuPlugin_shared_dBusRsp_pte_A; + wire MmuPlugin_shared_dBusRsp_pte_D; + wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; + wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; + wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; + wire MmuPlugin_shared_dBusRsp_exception; + wire MmuPlugin_shared_dBusRsp_leaf; + reg MmuPlugin_shared_pteBuffer_V; + reg MmuPlugin_shared_pteBuffer_R; + reg MmuPlugin_shared_pteBuffer_W; + reg MmuPlugin_shared_pteBuffer_X; + reg MmuPlugin_shared_pteBuffer_U; + reg MmuPlugin_shared_pteBuffer_G; + reg MmuPlugin_shared_pteBuffer_A; + reg MmuPlugin_shared_pteBuffer_D; + reg [1:0] MmuPlugin_shared_pteBuffer_RSW; + reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; + reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; + reg [1:0] _zz_98; + wire [1:0] _zz_99; + reg [1:0] _zz_100; + wire [1:0] MmuPlugin_shared_refills; + wire [1:0] _zz_101; + reg [1:0] _zz_102; + wire [31:0] _zz_103; + wire [35:0] _zz_104; + wire _zz_105; + wire _zz_106; + wire _zz_107; + wire _zz_108; + wire _zz_109; + wire _zz_110; + wire `Src1CtrlEnum_defaultEncoding_type _zz_111; + wire `AluCtrlEnum_defaultEncoding_type _zz_112; + wire `Src2CtrlEnum_defaultEncoding_type _zz_113; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_114; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_115; + wire `BranchCtrlEnum_defaultEncoding_type _zz_116; + wire `EnvCtrlEnum_defaultEncoding_type _zz_117; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_118; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_119; + reg [31:0] _zz_120; + wire _zz_121; + reg [19:0] _zz_122; + wire _zz_123; + reg [19:0] _zz_124; + reg [31:0] _zz_125; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_126; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_127; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_128; + wire _zz_129; + wire _zz_130; + wire _zz_131; + wire _zz_132; + wire _zz_133; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_134; + reg _zz_135; + reg _zz_136; + wire _zz_137; + reg [19:0] _zz_138; + wire _zz_139; + reg [10:0] _zz_140; + wire _zz_141; + reg [18:0] _zz_142; + reg _zz_143; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_144; + reg [19:0] _zz_145; + wire _zz_146; + reg [10:0] _zz_147; + wire _zz_148; + reg [18:0] _zz_149; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] _zz_150; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg CsrPlugin_medeleg_IAM; + reg CsrPlugin_medeleg_IAF; + reg CsrPlugin_medeleg_II; + reg CsrPlugin_medeleg_LAM; + reg CsrPlugin_medeleg_LAF; + reg CsrPlugin_medeleg_SAM; + reg CsrPlugin_medeleg_SAF; + reg CsrPlugin_medeleg_EU; + reg CsrPlugin_medeleg_ES; + reg CsrPlugin_medeleg_IPF; + reg CsrPlugin_medeleg_LPF; + reg CsrPlugin_medeleg_SPF; + reg CsrPlugin_mideleg_ST; + reg CsrPlugin_mideleg_SE; + reg CsrPlugin_mideleg_SS; + reg CsrPlugin_sstatus_SIE; + reg CsrPlugin_sstatus_SPIE; + reg [0:0] CsrPlugin_sstatus_SPP; + reg CsrPlugin_sip_SEIP_SOFT; + reg CsrPlugin_sip_SEIP_INPUT; + wire CsrPlugin_sip_SEIP_OR; + reg CsrPlugin_sip_STIP; + reg CsrPlugin_sip_SSIP; + reg CsrPlugin_sie_SEIE; + reg CsrPlugin_sie_STIE; + reg CsrPlugin_sie_SSIE; + reg [1:0] CsrPlugin_stvec_mode; + reg [29:0] CsrPlugin_stvec_base; + reg [31:0] CsrPlugin_sscratch; + reg CsrPlugin_scause_interrupt; + reg [3:0] CsrPlugin_scause_exceptionCode; + reg [31:0] CsrPlugin_stval; + reg [31:0] CsrPlugin_sepc; + reg [21:0] CsrPlugin_satp_PPN; + reg [8:0] CsrPlugin_satp_ASID; + reg [0:0] CsrPlugin_satp_MODE; + wire _zz_151; + wire _zz_152; + wire _zz_153; + wire _zz_154; + wire _zz_155; + wire _zz_156; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_157; + wire _zz_158; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + reg [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_159; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_160; + wire _zz_161; + wire _zz_162; + reg [32:0] _zz_163; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_164; + wire [31:0] _zz_165; + reg [31:0] _zz_166; + wire [31:0] _zz_167; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_168; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_LRSC; + reg decode_to_execute_MEMORY_AMO; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_IS_SFENCE_VMA; + reg execute_to_memory_IS_SFENCE_VMA; + reg memory_to_writeBack_IS_SFENCE_VMA; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_IS_DBUS_SHARING; + reg memory_to_writeBack_IS_DBUS_SHARING; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_169; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_256; + reg execute_CsrPlugin_csr_384; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_770; + reg execute_CsrPlugin_csr_771; + reg execute_CsrPlugin_csr_324; + reg execute_CsrPlugin_csr_260; + reg execute_CsrPlugin_csr_261; + reg execute_CsrPlugin_csr_321; + reg execute_CsrPlugin_csr_320; + reg execute_CsrPlugin_csr_322; + reg execute_CsrPlugin_csr_323; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg execute_CsrPlugin_csr_2496; + reg execute_CsrPlugin_csr_3520; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [2:0] _zz_194; + reg _zz_195; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + wire _zz_201; + reg _zz_202; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [23:0] _zz_20_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [63:0] _zz_23_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; + reg [95:0] _zz_26_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_27_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_29_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_30_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_33_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_34_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_36_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_37_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_38_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_39_string; + reg [39:0] _zz_43_string; + reg [31:0] _zz_44_string; + reg [71:0] _zz_45_string; + reg [39:0] _zz_46_string; + reg [23:0] _zz_47_string; + reg [63:0] _zz_48_string; + reg [95:0] _zz_49_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_52_string; + reg [47:0] MmuPlugin_shared_state_1_string; + reg [95:0] _zz_111_string; + reg [63:0] _zz_112_string; + reg [23:0] _zz_113_string; + reg [39:0] _zz_114_string; + reg [71:0] _zz_115_string; + reg [31:0] _zz_116_string; + reg [39:0] _zz_117_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif - always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_263 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_264 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_265 = 1'b1; + assign _zz_266 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_267 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_268 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_269 = ((_zz_208 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_270 = ((_zz_208 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_271 = ((_zz_208 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_272 = ((_zz_208 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_273 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_274 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_275 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_276 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_277 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_278 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_279 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_280 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_281 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign _zz_282 = (! dataCache_1_io_cpu_execute_refilling); + assign _zz_283 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_284 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign _zz_285 = MmuPlugin_shared_portSortedOh[0]; + assign _zz_286 = MmuPlugin_shared_portSortedOh[1]; + assign _zz_287 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_288 = (1'b0 || (! 1'b1)); + assign _zz_289 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_290 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_291 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_292 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_293 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_294 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_295 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_296 = execute_INSTRUCTION[13 : 12]; + assign _zz_297 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_298 = (! memory_arbitration_isStuck); + assign _zz_299 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_300 = (iBus_cmd_valid || (_zz_194 != 3'b000)); + assign _zz_301 = (_zz_237 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_302 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_303 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign _zz_304 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign _zz_305 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign _zz_306 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign _zz_307 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign _zz_308 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign _zz_309 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign _zz_310 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign _zz_311 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign _zz_312 = ((_zz_151 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign _zz_313 = ((_zz_152 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign _zz_314 = ((_zz_153 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign _zz_315 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_316 = ((_zz_151 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign _zz_317 = ((_zz_152 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign _zz_318 = ((_zz_153 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign _zz_319 = ((_zz_154 && 1'b1) && (! 1'b0)); + assign _zz_320 = ((_zz_155 && 1'b1) && (! 1'b0)); + assign _zz_321 = ((_zz_156 && 1'b1) && (! 1'b0)); + assign _zz_322 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_323 = execute_INSTRUCTION[13]; + assign _zz_324 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_325 = ($signed(_zz_326) + $signed(_zz_331)); + assign _zz_326 = ($signed(_zz_327) + $signed(_zz_329)); + assign _zz_327 = 52'h0; + assign _zz_328 = {1'b0,memory_MUL_LL}; + assign _zz_329 = {{19{_zz_328[32]}}, _zz_328}; + assign _zz_330 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_331 = {{2{_zz_330[49]}}, _zz_330}; + assign _zz_332 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_333 = {{2{_zz_332[49]}}, _zz_332}; + assign _zz_334 = ($signed(_zz_336) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_335 = _zz_334[31 : 0]; + assign _zz_336 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_337 = _zz_104[34 : 34]; + assign _zz_338 = _zz_104[33 : 33]; + assign _zz_339 = _zz_104[32 : 32]; + assign _zz_340 = _zz_104[31 : 31]; + assign _zz_341 = _zz_104[28 : 28]; + assign _zz_342 = _zz_104[21 : 21]; + assign _zz_343 = _zz_104[20 : 20]; + assign _zz_344 = _zz_104[19 : 19]; + assign _zz_345 = _zz_104[13 : 13]; + assign _zz_346 = _zz_104[12 : 12]; + assign _zz_347 = _zz_104[11 : 11]; + assign _zz_348 = _zz_104[35 : 35]; + assign _zz_349 = _zz_104[17 : 17]; + assign _zz_350 = _zz_104[5 : 5]; + assign _zz_351 = _zz_104[3 : 3]; + assign _zz_352 = _zz_104[18 : 18]; + assign _zz_353 = _zz_104[10 : 10]; + assign _zz_354 = _zz_104[16 : 16]; + assign _zz_355 = _zz_104[15 : 15]; + assign _zz_356 = _zz_104[4 : 4]; + assign _zz_357 = _zz_104[0 : 0]; + assign _zz_358 = (_zz_57 - 5'h01); + assign _zz_359 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_360 = {29'd0, _zz_359}; + assign _zz_361 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_362 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_363 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_364 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_365 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_366 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_367 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_368 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_369 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_370 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_371 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_372 = {1'd0, _zz_371}; + assign _zz_373 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_374 = {1'd0, _zz_373}; + assign _zz_375 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; + assign _zz_376 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; + assign _zz_377 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; + assign _zz_378 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; + assign _zz_379 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; + assign _zz_380 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; + assign _zz_381 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; + assign _zz_382 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; + assign _zz_383 = (_zz_100 - 2'b01); + assign _zz_384 = execute_SRC_LESS; + assign _zz_385 = 3'b100; + assign _zz_386 = execute_INSTRUCTION[19 : 15]; + assign _zz_387 = execute_INSTRUCTION[31 : 20]; + assign _zz_388 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_389 = ($signed(_zz_390) + $signed(_zz_393)); + assign _zz_390 = ($signed(_zz_391) + $signed(_zz_392)); + assign _zz_391 = execute_SRC1; + assign _zz_392 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_393 = (execute_SRC_USE_SUB_LESS ? _zz_394 : _zz_395); + assign _zz_394 = 32'h00000001; + assign _zz_395 = 32'h0; + assign _zz_396 = execute_INSTRUCTION[31 : 20]; + assign _zz_397 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_398 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_399 = {_zz_138,execute_INSTRUCTION[31 : 20]}; + assign _zz_400 = {{_zz_140,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_401 = {{_zz_142,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_402 = execute_INSTRUCTION[31 : 20]; + assign _zz_403 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_404 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_405 = 3'b100; + assign _zz_406 = (_zz_157 & (~ _zz_407)); + assign _zz_407 = (_zz_157 - 2'b01); + assign _zz_408 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_409 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_410 = writeBack_MUL_LOW[31 : 0]; + assign _zz_411 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_412 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_413 = {5'd0, _zz_412}; + assign _zz_414 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_415 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_416 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_417 = {_zz_159,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_418 = _zz_419; + assign _zz_419 = _zz_420; + assign _zz_420 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_160) : _zz_160)} + _zz_422); + assign _zz_421 = memory_DivPlugin_div_needRevert; + assign _zz_422 = {32'd0, _zz_421}; + assign _zz_423 = _zz_162; + assign _zz_424 = {32'd0, _zz_423}; + assign _zz_425 = _zz_161; + assign _zz_426 = {31'd0, _zz_425}; + assign _zz_427 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_428 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_429 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_430 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_431 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_432 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_433 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_434 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_435 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_436 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_437 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_438 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_439 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_440 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_441 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_442 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_443 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_444 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_445 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_446 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_447 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_448 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_449 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_450 = execute_CsrPlugin_writeData[0 : 0]; + assign _zz_451 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_452 = execute_CsrPlugin_writeData[2 : 2]; + assign _zz_453 = execute_CsrPlugin_writeData[4 : 4]; + assign _zz_454 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_455 = execute_CsrPlugin_writeData[6 : 6]; + assign _zz_456 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_457 = execute_CsrPlugin_writeData[8 : 8]; + assign _zz_458 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_459 = execute_CsrPlugin_writeData[12 : 12]; + assign _zz_460 = execute_CsrPlugin_writeData[13 : 13]; + assign _zz_461 = execute_CsrPlugin_writeData[15 : 15]; + assign _zz_462 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_463 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_464 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_465 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_466 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_467 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_468 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_469 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_470 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_471 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_472 = (iBus_cmd_payload_address >>> 5); + assign _zz_473 = 1'b1; + assign _zz_474 = 1'b1; + assign _zz_475 = {_zz_60,{_zz_62,_zz_61}}; + assign _zz_476 = 32'h0000107f; + assign _zz_477 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_478 = 32'h00002073; + assign _zz_479 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_480 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_481 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_482) == 32'h00000003),{(_zz_483 == _zz_484),{_zz_485,{_zz_486,_zz_487}}}}}}; + assign _zz_482 = 32'h0000505f; + assign _zz_483 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_484 = 32'h00000063; + assign _zz_485 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_486 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_487 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_488) == 32'h0000500f),{(_zz_489 == _zz_490),{_zz_491,{_zz_492,_zz_493}}}}}}; + assign _zz_488 = 32'h01f0707f; + assign _zz_489 = (decode_INSTRUCTION & 32'hbc00707f); + assign _zz_490 = 32'h00005013; + assign _zz_491 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); + assign _zz_492 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_493 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_494) == 32'h12000073),{(_zz_495 == _zz_496),{_zz_497,_zz_498}}}}}; + assign _zz_494 = 32'hfe007fff; + assign _zz_495 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_496 = 32'h10200073; + assign _zz_497 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_498 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_499 = decode_INSTRUCTION[31]; + assign _zz_500 = decode_INSTRUCTION[31]; + assign _zz_501 = decode_INSTRUCTION[7]; + assign _zz_502 = 32'h10103050; + assign _zz_503 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_504 = 1'b0; + assign _zz_505 = (((decode_INSTRUCTION & _zz_508) == 32'h02000030) != 1'b0); + assign _zz_506 = ({_zz_509,_zz_510} != 2'b00); + assign _zz_507 = {(_zz_511 != 1'b0),{(_zz_512 != _zz_513),{_zz_514,{_zz_515,_zz_516}}}}; + assign _zz_508 = 32'h02004074; + assign _zz_509 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz_510 = ((decode_INSTRUCTION & 32'h12203050) == 32'h10000050); + assign _zz_511 = ((decode_INSTRUCTION & 32'h02103050) == 32'h00000050); + assign _zz_512 = {(_zz_517 == _zz_518),(_zz_519 == _zz_520)}; + assign _zz_513 = 2'b00; + assign _zz_514 = ({_zz_106,_zz_521} != 2'b00); + assign _zz_515 = (_zz_522 != 1'b0); + assign _zz_516 = {(_zz_523 != _zz_524),{_zz_525,{_zz_526,_zz_527}}}; + assign _zz_517 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_518 = 32'h00001050; + assign _zz_519 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_520 = 32'h00002050; + assign _zz_521 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_522 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_523 = {(_zz_528 == _zz_529),(_zz_530 == _zz_531)}; + assign _zz_524 = 2'b00; + assign _zz_525 = ({_zz_532,{_zz_533,_zz_534}} != 3'b000); + assign _zz_526 = (_zz_535 != 1'b0); + assign _zz_527 = {(_zz_536 != _zz_537),{_zz_538,{_zz_539,_zz_540}}}; + assign _zz_528 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_529 = 32'h00005010; + assign _zz_530 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_531 = 32'h00005020; + assign _zz_532 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_533 = ((decode_INSTRUCTION & _zz_541) == 32'h00001010); + assign _zz_534 = ((decode_INSTRUCTION & _zz_542) == 32'h00001010); + assign _zz_535 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_536 = ((decode_INSTRUCTION & _zz_543) == 32'h00002000); + assign _zz_537 = 1'b0; + assign _zz_538 = ({_zz_544,_zz_545} != 2'b00); + assign _zz_539 = (_zz_546 != 1'b0); + assign _zz_540 = {(_zz_547 != _zz_548),{_zz_549,{_zz_550,_zz_551}}}; + assign _zz_541 = 32'h00007034; + assign _zz_542 = 32'h02007054; + assign _zz_543 = 32'h00003000; + assign _zz_544 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_545 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_546 = ((decode_INSTRUCTION & 32'h02003050) == 32'h02000050); + assign _zz_547 = ((decode_INSTRUCTION & _zz_552) == 32'h00004008); + assign _zz_548 = 1'b0; + assign _zz_549 = ((_zz_553 == _zz_554) != 1'b0); + assign _zz_550 = ({_zz_555,_zz_556} != 4'b0000); + assign _zz_551 = {(_zz_557 != _zz_558),{_zz_559,{_zz_560,_zz_561}}}; + assign _zz_552 = 32'h00004048; + assign _zz_553 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_554 = 32'h00000024; + assign _zz_555 = ((decode_INSTRUCTION & _zz_562) == 32'h00000020); + assign _zz_556 = {(_zz_563 == _zz_564),{_zz_565,_zz_566}}; + assign _zz_557 = ((decode_INSTRUCTION & _zz_567) == 32'h00000008); + assign _zz_558 = 1'b0; + assign _zz_559 = ((_zz_568 == _zz_569) != 1'b0); + assign _zz_560 = ({_zz_570,_zz_571} != 6'h0); + assign _zz_561 = {(_zz_572 != _zz_573),{_zz_574,{_zz_575,_zz_576}}}; + assign _zz_562 = 32'h00000034; + assign _zz_563 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_564 = 32'h00000020; + assign _zz_565 = ((decode_INSTRUCTION & _zz_577) == 32'h08000020); + assign _zz_566 = ((decode_INSTRUCTION & _zz_578) == 32'h00000020); + assign _zz_567 = 32'h10000008; + assign _zz_568 = (decode_INSTRUCTION & 32'h10000008); + assign _zz_569 = 32'h10000008; + assign _zz_570 = (_zz_579 == _zz_580); + assign _zz_571 = {_zz_581,{_zz_582,_zz_583}}; + assign _zz_572 = {_zz_584,{_zz_585,_zz_586}}; + assign _zz_573 = 3'b000; + assign _zz_574 = ({_zz_587,_zz_588} != 5'h0); + assign _zz_575 = (_zz_589 != _zz_590); + assign _zz_576 = {_zz_591,{_zz_592,_zz_593}}; + assign _zz_577 = 32'h08000070; + assign _zz_578 = 32'h10000070; + assign _zz_579 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_580 = 32'h00002040; + assign _zz_581 = ((decode_INSTRUCTION & _zz_594) == 32'h00001040); + assign _zz_582 = (_zz_595 == _zz_596); + assign _zz_583 = {_zz_597,{_zz_598,_zz_599}}; + assign _zz_584 = ((decode_INSTRUCTION & _zz_600) == 32'h08000020); + assign _zz_585 = (_zz_601 == _zz_602); + assign _zz_586 = (_zz_603 == _zz_604); + assign _zz_587 = (_zz_605 == _zz_606); + assign _zz_588 = {_zz_607,{_zz_608,_zz_609}}; + assign _zz_589 = {_zz_109,{_zz_610,_zz_611}}; + assign _zz_590 = 5'h0; + assign _zz_591 = ({_zz_612,_zz_613} != 7'h0); + assign _zz_592 = (_zz_614 != _zz_615); + assign _zz_593 = {_zz_616,{_zz_617,_zz_618}}; + assign _zz_594 = 32'h00001040; + assign _zz_595 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_596 = 32'h00000040; + assign _zz_597 = ((decode_INSTRUCTION & _zz_619) == 32'h00000040); + assign _zz_598 = (_zz_620 == _zz_621); + assign _zz_599 = (_zz_622 == _zz_623); + assign _zz_600 = 32'h08000020; + assign _zz_601 = (decode_INSTRUCTION & 32'h10000020); + assign _zz_602 = 32'h00000020; + assign _zz_603 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_604 = 32'h00000020; + assign _zz_605 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_606 = 32'h00000040; + assign _zz_607 = ((decode_INSTRUCTION & _zz_624) == 32'h00004020); + assign _zz_608 = (_zz_625 == _zz_626); + assign _zz_609 = {_zz_109,_zz_627}; + assign _zz_610 = (_zz_628 == _zz_629); + assign _zz_611 = {_zz_630,{_zz_631,_zz_632}}; + assign _zz_612 = _zz_106; + assign _zz_613 = {_zz_633,{_zz_634,_zz_635}}; + assign _zz_614 = {_zz_108,_zz_636}; + assign _zz_615 = 2'b00; + assign _zz_616 = ({_zz_637,_zz_638} != 2'b00); + assign _zz_617 = (_zz_639 != _zz_640); + assign _zz_618 = {_zz_641,{_zz_642,_zz_643}}; + assign _zz_619 = 32'h02100040; + assign _zz_620 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_621 = 32'h0; + assign _zz_622 = (decode_INSTRUCTION & 32'h18002008); + assign _zz_623 = 32'h10002008; + assign _zz_624 = 32'h00004020; + assign _zz_625 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_626 = 32'h00000010; + assign _zz_627 = ((decode_INSTRUCTION & _zz_644) == 32'h00000020); + assign _zz_628 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_629 = 32'h00002010; + assign _zz_630 = ((decode_INSTRUCTION & _zz_645) == 32'h00000010); + assign _zz_631 = (_zz_646 == _zz_647); + assign _zz_632 = (_zz_648 == _zz_649); + assign _zz_633 = ((decode_INSTRUCTION & _zz_650) == 32'h00001010); + assign _zz_634 = (_zz_651 == _zz_652); + assign _zz_635 = {_zz_653,{_zz_654,_zz_655}}; + assign _zz_636 = ((decode_INSTRUCTION & _zz_656) == 32'h00000020); + assign _zz_637 = _zz_108; + assign _zz_638 = (_zz_657 == _zz_658); + assign _zz_639 = (_zz_659 == _zz_660); + assign _zz_640 = 1'b0; + assign _zz_641 = (_zz_661 != 1'b0); + assign _zz_642 = (_zz_662 != _zz_663); + assign _zz_643 = {_zz_664,{_zz_665,_zz_666}}; + assign _zz_644 = 32'h02000028; + assign _zz_645 = 32'h00001030; + assign _zz_646 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_647 = 32'h00000020; + assign _zz_648 = (decode_INSTRUCTION & 32'h02002068); + assign _zz_649 = 32'h00002020; + assign _zz_650 = 32'h00001010; + assign _zz_651 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_652 = 32'h00002010; + assign _zz_653 = ((decode_INSTRUCTION & _zz_667) == 32'h00002008); + assign _zz_654 = (_zz_668 == _zz_669); + assign _zz_655 = {_zz_109,_zz_670}; + assign _zz_656 = 32'h00000070; + assign _zz_657 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_658 = 32'h0; + assign _zz_659 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_660 = 32'h00004010; + assign _zz_661 = ((decode_INSTRUCTION & _zz_671) == 32'h00002010); + assign _zz_662 = {_zz_672,{_zz_673,_zz_674}}; + assign _zz_663 = 5'h0; + assign _zz_664 = ({_zz_675,_zz_676} != 2'b00); + assign _zz_665 = (_zz_677 != _zz_678); + assign _zz_666 = {_zz_679,{_zz_680,_zz_681}}; + assign _zz_667 = 32'h00002008; + assign _zz_668 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_669 = 32'h00000010; + assign _zz_670 = ((decode_INSTRUCTION & _zz_682) == 32'h0); + assign _zz_671 = 32'h00006014; + assign _zz_672 = ((decode_INSTRUCTION & _zz_683) == 32'h0); + assign _zz_673 = (_zz_684 == _zz_685); + assign _zz_674 = {_zz_686,{_zz_687,_zz_688}}; + assign _zz_675 = _zz_107; + assign _zz_676 = (_zz_689 == _zz_690); + assign _zz_677 = {_zz_691,{_zz_692,_zz_693}}; + assign _zz_678 = 3'b000; + assign _zz_679 = ({_zz_694,_zz_695} != 3'b000); + assign _zz_680 = (_zz_696 != _zz_697); + assign _zz_681 = (_zz_698 != _zz_699); + assign _zz_682 = 32'h00000028; + assign _zz_683 = 32'h00000044; + assign _zz_684 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_685 = 32'h0; + assign _zz_686 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_687 = ((decode_INSTRUCTION & _zz_700) == 32'h00001000); + assign _zz_688 = _zz_107; + assign _zz_689 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_690 = 32'h0; + assign _zz_691 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_692 = ((decode_INSTRUCTION & _zz_701) == 32'h00002010); + assign _zz_693 = ((decode_INSTRUCTION & _zz_702) == 32'h40000030); + assign _zz_694 = _zz_106; + assign _zz_695 = {_zz_105,(_zz_703 == _zz_704)}; + assign _zz_696 = {_zz_105,(_zz_705 == _zz_706)}; + assign _zz_697 = 2'b00; + assign _zz_698 = ((decode_INSTRUCTION & _zz_707) == 32'h00001008); + assign _zz_699 = 1'b0; + assign _zz_700 = 32'h00005004; + assign _zz_701 = 32'h00002014; + assign _zz_702 = 32'h40000034; + assign _zz_703 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_704 = 32'h00000004; + assign _zz_705 = (decode_INSTRUCTION & 32'h0000004c); + assign _zz_706 = 32'h00000004; + assign _zz_707 = 32'h00005048; + assign _zz_708 = execute_INSTRUCTION[31]; + assign _zz_709 = execute_INSTRUCTION[31]; + assign _zz_710 = execute_INSTRUCTION[7]; + assign _zz_711 = 32'h0; always @ (posedge clk) begin - if(_zz_9_) begin - _zz_13_ <= ways_0_datas[_zz_8_]; + if(_zz_473) begin + _zz_238 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; + always @ (posedge clk) begin + if(_zz_474) begin + _zz_239 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; + always @ (posedge clk) begin + if(_zz_42) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_203 ), //i + .io_cpu_prefetch_isValid (_zz_204 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_205 ), //i + .io_cpu_fetch_isStuck (_zz_206 ), //i + .io_cpu_fetch_isRemoved (_zz_207 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_208 ), //i + .io_cpu_decode_isStuck (_zz_209 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_210 ), //i + .io_cpu_fill_valid (_zz_211 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_9 (_zz_169[2:0] ), //i + ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_212 ), //i + .io_cpu_execute_address (_zz_213[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (_zz_214 ), //i + .io_cpu_execute_args_data (_zz_215[31:0] ), //i + .io_cpu_execute_args_size (_zz_216[1:0] ), //i + .io_cpu_execute_args_isLrsc (_zz_217 ), //i + .io_cpu_execute_args_isAmo (_zz_218 ), //i + .io_cpu_execute_args_amoCtrl_swap (_zz_219 ), //i + .io_cpu_execute_args_amoCtrl_alu (_zz_220[2:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_221 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_222[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_223 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_writeBack_isValid (_zz_224 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_225 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_226[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_227 ), //i + .io_cpu_writeBack_fence_SR (_zz_228 ), //i + .io_cpu_writeBack_fence_SO (_zz_229 ), //i + .io_cpu_writeBack_fence_SI (_zz_230 ), //i + .io_cpu_writeBack_fence_PW (_zz_231 ), //i + .io_cpu_writeBack_fence_PR (_zz_232 ), //i + .io_cpu_writeBack_fence_PO (_zz_233 ), //i + .io_cpu_writeBack_fence_PI (_zz_234 ), //i + .io_cpu_writeBack_fence_FM (_zz_235[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_236 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_237 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_475) + 3'b000 : begin + _zz_240 = DBusCachedPlugin_redoBranch_payload; end - end - end - - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_14_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; - end + 3'b001 : begin + _zz_240 = CsrPlugin_jumpInterface_payload; + end + 3'b010 : begin + _zz_240 = BranchPlugin_jumpInterface_payload; + end + 3'b011 : begin + _zz_240 = CsrPlugin_redoInterface_payload; + end + default : begin + _zz_240 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase end - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_12_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_16_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_17_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_13_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; + always @(*) begin + case(_zz_93) + 2'b00 : begin + _zz_241 = MmuPlugin_ports_0_cache_0_valid; + _zz_242 = MmuPlugin_ports_0_cache_0_exception; + _zz_243 = MmuPlugin_ports_0_cache_0_superPage; + _zz_244 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_245 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_246 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_247 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_248 = MmuPlugin_ports_0_cache_0_allowRead; + _zz_249 = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_250 = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_251 = MmuPlugin_ports_0_cache_0_allowUser; end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; + 2'b01 : begin + _zz_241 = MmuPlugin_ports_0_cache_1_valid; + _zz_242 = MmuPlugin_ports_0_cache_1_exception; + _zz_243 = MmuPlugin_ports_0_cache_1_superPage; + _zz_244 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_245 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_246 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_247 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_248 = MmuPlugin_ports_0_cache_1_allowRead; + _zz_249 = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_250 = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_251 = MmuPlugin_ports_0_cache_1_allowUser; end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; + 2'b10 : begin + _zz_241 = MmuPlugin_ports_0_cache_2_valid; + _zz_242 = MmuPlugin_ports_0_cache_2_exception; + _zz_243 = MmuPlugin_ports_0_cache_2_superPage; + _zz_244 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_245 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_246 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_247 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_248 = MmuPlugin_ports_0_cache_2_allowRead; + _zz_249 = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_250 = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_251 = MmuPlugin_ports_0_cache_2_allowUser; end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; + default : begin + _zz_241 = MmuPlugin_ports_0_cache_3_valid; + _zz_242 = MmuPlugin_ports_0_cache_3_exception; + _zz_243 = MmuPlugin_ports_0_cache_3_superPage; + _zz_244 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_245 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_246 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_247 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_248 = MmuPlugin_ports_0_cache_3_allowRead; + _zz_249 = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_250 = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_251 = MmuPlugin_ports_0_cache_3_allowUser; end - if(_zz_15_)begin - lineLoader_flushPending <= 1'b0; + endcase + end + + always @(*) begin + case(_zz_97) + 2'b00 : begin + _zz_252 = MmuPlugin_ports_1_cache_0_valid; + _zz_253 = MmuPlugin_ports_1_cache_0_exception; + _zz_254 = MmuPlugin_ports_1_cache_0_superPage; + _zz_255 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_256 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_257 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_258 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_259 = MmuPlugin_ports_1_cache_0_allowRead; + _zz_260 = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_261 = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_262 = MmuPlugin_ports_1_cache_0_allowUser; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; + 2'b01 : begin + _zz_252 = MmuPlugin_ports_1_cache_1_valid; + _zz_253 = MmuPlugin_ports_1_cache_1_exception; + _zz_254 = MmuPlugin_ports_1_cache_1_superPage; + _zz_255 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_256 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_257 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_258 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_259 = MmuPlugin_ports_1_cache_1_allowRead; + _zz_260 = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_261 = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_262 = MmuPlugin_ports_1_cache_1_allowUser; end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; + 2'b10 : begin + _zz_252 = MmuPlugin_ports_1_cache_2_valid; + _zz_253 = MmuPlugin_ports_1_cache_2_exception; + _zz_254 = MmuPlugin_ports_1_cache_2_superPage; + _zz_255 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_256 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_257 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_258 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_259 = MmuPlugin_ports_1_cache_2_allowRead; + _zz_260 = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_261 = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_262 = MmuPlugin_ports_1_cache_2_allowUser; end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end + default : begin + _zz_252 = MmuPlugin_ports_1_cache_3_valid; + _zz_253 = MmuPlugin_ports_1_cache_3_exception; + _zz_254 = MmuPlugin_ports_1_cache_3_superPage; + _zz_255 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_256 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_257 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_258 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_259 = MmuPlugin_ports_1_cache_3_allowRead; + _zz_260 = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_261 = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_262 = MmuPlugin_ports_1_cache_3_allowUser; end - end + endcase end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_14_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); - end - _zz_3_ <= lineLoader_flushCounter[7]; - if(_zz_15_)begin - lineLoader_flushCounter <= (8'b00000000); - end - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_error <= fetchStage_hit_error; - end - if((_zz_10_ != (3'b000)))begin - io_cpu_fetch_data_regNextWhen <= _zz_11_; - end + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; + endcase end - -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, - input [1:0] io_cpu_execute_args_size, - input io_cpu_execute_args_isLrsc, - input io_cpu_execute_args_isAmo, - input io_cpu_execute_args_amoCtrl_swap, - input [2:0] io_cpu_execute_args_amoCtrl_alu, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - input io_cpu_memory_isRemoved, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - output io_cpu_memory_mmuBus_cmd_isValid, - output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, - output io_cpu_memory_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, - input io_cpu_memory_mmuBus_rsp_isIoAccess, - input io_cpu_memory_mmuBus_rsp_allowRead, - input io_cpu_memory_mmuBus_rsp_allowWrite, - input io_cpu_memory_mmuBus_rsp_allowExecute, - input io_cpu_memory_mmuBus_rsp_exception, - input io_cpu_memory_mmuBus_rsp_refilling, - output io_cpu_memory_mmuBus_end, - input io_cpu_memory_mmuBus_busy, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - input io_cpu_writeBack_clearLrsc, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output reg io_cpu_flush_ready, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, - output reg io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire _zz_16_; - wire _zz_17_; - wire _zz_18_; - wire _zz_19_; - wire _zz_20_; - wire _zz_21_; - wire [2:0] _zz_22_; - wire [0:0] _zz_23_; - wire [0:0] _zz_24_; - wire [31:0] _zz_25_; - wire [31:0] _zz_26_; - wire [31:0] _zz_27_; - wire [31:0] _zz_28_; - wire [1:0] _zz_29_; - wire [31:0] _zz_30_; - wire [1:0] _zz_31_; - wire [1:0] _zz_32_; - wire [0:0] _zz_33_; - wire [0:0] _zz_34_; - wire [2:0] _zz_35_; - wire [1:0] _zz_36_; - wire [21:0] _zz_37_; - reg _zz_1_; - reg _zz_2_; - wire haltCpu; - reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3_; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4_; - wire _zz_5_; - wire [31:0] ways_0_dataReadRsp; - reg [3:0] _zz_6_; - wire [3:0] stage0_mask; - wire [0:0] stage0_colisions; - reg stageA_request_wr; - reg [31:0] stageA_request_data; - reg [1:0] stageA_request_size; - reg stageA_request_isLrsc; - reg stageA_request_isAmo; - reg stageA_request_amoCtrl_swap; - reg [2:0] stageA_request_amoCtrl_alu; - reg [3:0] stageA_mask; - wire stageA_wayHits_0; - reg [0:0] stage0_colisions_regNextWhen; - wire [0:0] _zz_7_; - wire [0:0] stageA_colisions; - reg stageB_request_wr; - reg [31:0] stageB_request_data; - reg [1:0] stageB_request_size; - reg stageB_request_isLrsc; - reg stageB_isAmo; - reg stageB_request_amoCtrl_swap; - reg [2:0] stageB_request_amoCtrl_alu; - reg stageB_mmuRspFreeze; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg [31:0] stageB_dataReadRsp_0; - wire [0:0] _zz_8_; - reg [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - reg [3:0] stageB_mask; - reg [0:0] stageB_colisions; - reg stageB_loaderValid; - reg stageB_flusher_valid; - reg stageB_lrsc_reserved; - reg [31:0] stageB_requestDataBypass; - wire stageB_amo_compare; - wire stageB_amo_unsigned; - wire [31:0] stageB_amo_addSub; - wire stageB_amo_less; - wire stageB_amo_selectRf; - reg [31:0] stageB_amo_result; - reg stageB_amo_resultRegValid; - reg [31:0] stageB_amo_resultReg; - reg stageB_memCmdSent; - wire [0:0] _zz_9_; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [2:0] loader_counter_valueNext; - reg [2:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_38_; - reg [7:0] _zz_39_; - reg [7:0] _zz_40_; - reg [7:0] _zz_41_; - assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); - assign _zz_15_ = (! stageB_amo_resultRegValid); - assign _zz_16_ = (stageB_request_isLrsc && (! stageB_lrsc_reserved)); - assign _zz_17_ = (loader_valid && io_mem_rsp_valid); - assign _zz_18_ = (stageB_request_isLrsc && (! stageB_lrsc_reserved)); - assign _zz_19_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - assign _zz_20_ = (((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))); - assign _zz_21_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign _zz_22_ = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,(2'b00)}); - assign _zz_23_ = _zz_4_[0 : 0]; - assign _zz_24_ = _zz_4_[1 : 1]; - assign _zz_25_ = ($signed(_zz_26_) + $signed(_zz_30_)); - assign _zz_26_ = ($signed(_zz_27_) + $signed(_zz_28_)); - assign _zz_27_ = stageB_request_data; - assign _zz_28_ = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux); - assign _zz_29_ = (stageB_amo_compare ? _zz_31_ : _zz_32_); - assign _zz_30_ = {{30{_zz_29_[1]}}, _zz_29_}; - assign _zz_31_ = (2'b01); - assign _zz_32_ = (2'b00); - assign _zz_33_ = (! stageB_lrsc_reserved); - assign _zz_34_ = loader_counter_willIncrement; - assign _zz_35_ = {2'd0, _zz_34_}; - assign _zz_36_ = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_37_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_37_; - end + always @(*) begin + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_3_) begin - _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; - end + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase end - - always @ (*) begin - _zz_11_ = {_zz_41_, _zz_40_, _zz_39_, _zz_38_}; + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase end - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1_) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1_) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1_) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1_) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_5_) begin - _zz_38_ <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_39_ <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_40_ <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_41_ <= ways_0_data_symbol3[dataReadCmd_payload]; - end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase end - - always @ (*) begin - _zz_1_ = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_1_ = 1'b1; - end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase end - - always @ (*) begin - _zz_2_ = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_2_ = 1'b1; - end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase end - - assign haltCpu = 1'b0; - assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4_ = _zz_10_; - assign ways_0_tagsReadRsp_valid = _zz_23_[0]; - assign ways_0_tagsReadRsp_error = _zz_24_[0]; - assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; - assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRsp = _zz_11_; - always @ (*) begin - tagsReadCmd_valid = 1'b0; - if(_zz_12_)begin - tagsReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; + endcase end - - always @ (*) begin - tagsReadCmd_payload = (7'bxxxxxxx); - if(_zz_12_)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; - end + always @(*) begin + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_valid = 1'b0; - if(_zz_12_)begin - dataReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; + endcase end - - always @ (*) begin - dataReadCmd_payload = (10'bxxxxxxxxxx); - if(_zz_12_)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; - end - if(_zz_13_)begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_valid = 1'b1; - end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_way = (1'bx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = (1'b1); - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_address = (7'bxxxxxxx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_valid = 1'b1; - end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); - end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end + always @(*) begin + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((stageB_request_wr && stageB_waysHit))begin - dataWriteCmd_valid = 1'b1; - end - if(stageB_isAmo)begin - if(_zz_15_)begin - dataWriteCmd_valid = 1'b0; - end - end - if(_zz_16_)begin - dataWriteCmd_valid = 1'b0; - end - end - end - end - if(_zz_13_)begin - dataWriteCmd_valid = 1'b0; - end - if(_zz_17_)begin - dataWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_way = (1'bx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_way = stageB_waysHits; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_address = (10'bxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; - end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_data = stageB_requestDataBypass; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end + always @(*) begin + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_mask = (4'bxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_mask = stageB_mask; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_mask = (4'b1111); - end + always @(*) begin + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; + endcase end - - always @ (*) begin - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_6_ = (4'b0001); - end - 2'b01 : begin - _zz_6_ = (4'b0011); - end - default : begin - _zz_6_ = (4'b1111); - end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; endcase end - - assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); - assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; - assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; - assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); - always @ (*) begin - stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin - stageB_mmuRspFreeze = 1'b1; - end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase end - - assign _zz_8_[0] = stageA_wayHits_0; - assign stageB_waysHit = (stageB_waysHits != (1'b0)); - assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - if(io_mem_cmd_ready)begin - stageB_loaderValid = 1'b1; - end - end - end - end - if(_zz_13_)begin - stageB_loaderValid = 1'b0; - end + always @(*) begin + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin - io_cpu_writeBack_haltIt = 1'b0; - end - if(_zz_18_)begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(_zz_14_)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin - io_cpu_writeBack_haltIt = 1'b0; - end - if(stageB_isAmo)begin - if(_zz_15_)begin - io_cpu_writeBack_haltIt = 1'b1; - end - end - if(_zz_16_)begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - if(_zz_13_)begin - io_cpu_writeBack_haltIt = 1'b0; - end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(_zz_19_)begin - io_cpu_flush_ready = 1'b1; - end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase end - - always @ (*) begin - stageB_requestDataBypass = stageB_request_data; - if(stageB_isAmo)begin - stageB_requestDataBypass = stageB_amo_resultReg; - end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase end - - assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; - assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == (2'b11)); - assign stageB_amo_addSub = _zz_25_; - assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31])); - assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); - always @ (*) begin - case(_zz_22_) - 3'b000 : begin - stageB_amo_result = stageB_amo_addSub; - end - 3'b001 : begin - stageB_amo_result = (stageB_request_data ^ stageB_dataMux); - end - 3'b010 : begin - stageB_amo_result = (stageB_request_data | stageB_dataMux); - end - 3'b011 : begin - stageB_amo_result = (stageB_request_data & stageB_dataMux); - end - default : begin - stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux); - end + always @(*) begin + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; endcase end - - always @ (*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if(_zz_20_)begin - io_cpu_redo = 1'b1; - end - end - end - end - if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin - io_cpu_redo = 1'b1; - end - if(loader_valid)begin - io_cpu_redo = 1'b1; - end + always @(*) begin + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); - end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase end - - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_valid = (! stageB_memCmdSent); - if(_zz_18_)begin - io_mem_cmd_valid = 1'b0; - end - end else begin - if(_zz_14_)begin - if(stageB_request_wr)begin - io_mem_cmd_valid = 1'b1; - end - if(stageB_isAmo)begin - if(_zz_15_)begin - io_mem_cmd_valid = 1'b0; - end - end - if(_zz_20_)begin - io_mem_cmd_valid = 1'b0; - end - if(_zz_16_)begin - io_mem_cmd_valid = 1'b0; - end - end else begin - if((! stageB_memCmdSent))begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - io_mem_cmd_valid = 1'b0; - end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; - end - end - end + always @(*) begin + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_length = (3'bxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - io_mem_cmd_payload_length = (3'b111); - end - end - end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_last = 1'bx; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - io_mem_cmd_payload_last = 1'b1; - end - end - end + always @(*) begin + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; + endcase end - - always @ (*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - always @ (*) begin - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_data = io_mem_rsp_payload_data; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - if((stageB_request_isLrsc && stageB_request_wr))begin - io_cpu_writeBack_data = {31'd0, _zz_33_}; - end + always @(*) begin + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; + endcase end - - assign _zz_9_[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin - loader_counter_willIncrement = 1'b0; - if(_zz_17_)begin - loader_counter_willIncrement = 1'b1; - end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_35_); - if(loader_counter_willClear)begin - loader_counter_valueNext = (3'b000); - end + always @(*) begin + case(_zz_30) + `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; + default : _zz_30_string = "????"; + endcase end - - always @ (posedge clk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; - stageA_request_size <= io_cpu_execute_args_size; - stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; - stageA_request_isAmo <= io_cpu_execute_args_isAmo; - stageA_request_amoCtrl_swap <= io_cpu_execute_args_amoCtrl_swap; - stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; - end - if((! io_cpu_memory_isStuck))begin - stageA_mask <= stage0_mask; - end - if((! io_cpu_memory_isStuck))begin - stage0_colisions_regNextWhen <= stage0_colisions; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; - stageB_request_size <= stageA_request_size; - stageB_request_isLrsc <= stageA_request_isLrsc; - stageB_isAmo <= stageA_request_isAmo; - stageB_request_amoCtrl_swap <= stageA_request_amoCtrl_swap; - stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; - end - if(_zz_21_)begin - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_waysHits <= _zz_8_; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_mask <= stageA_mask; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_colisions <= stageA_colisions; - end - stageB_amo_resultRegValid <= 1'b1; - if((! io_cpu_writeBack_isStuck))begin - stageB_amo_resultRegValid <= 1'b0; - end - stageB_amo_resultReg <= stageB_amo_result; - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); - end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase end - - always @ (posedge clk) begin - if(reset) begin - stageB_flusher_valid <= 1'b1; - stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); - stageB_lrsc_reserved <= 1'b0; - stageB_memCmdSent <= 1'b0; - loader_valid <= 1'b0; - loader_counter_value <= (3'b000); - loader_waysAllocator <= (1'b1); - loader_error <= 1'b0; - end else begin - if(_zz_21_)begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; - end - if(stageB_flusher_valid)begin - if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); - end else begin - stageB_flusher_valid <= 1'b0; - end - end - if(_zz_19_)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); - stageB_flusher_valid <= 1'b1; - end - if(((((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && (! io_cpu_redo)) && stageB_request_isLrsc) && (! stageB_request_wr)))begin - stageB_lrsc_reserved <= 1'b1; - end - if(io_cpu_writeBack_clearLrsc)begin - stageB_lrsc_reserved <= 1'b0; - end - if(io_mem_cmd_ready)begin - stageB_memCmdSent <= 1'b1; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_memCmdSent <= 1'b0; - end - if(stageB_loaderValid)begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(_zz_17_)begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_counter_willOverflow)begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - end - if((! loader_valid))begin - loader_waysAllocator <= _zz_36_[0:0]; - end - end - end - -endmodule - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset, - input debugReset); - wire _zz_244_; - wire _zz_245_; - wire _zz_246_; - wire _zz_247_; - wire [31:0] _zz_248_; - wire _zz_249_; - wire _zz_250_; - wire _zz_251_; - reg _zz_252_; - reg _zz_253_; - reg [31:0] _zz_254_; - reg _zz_255_; - reg [31:0] _zz_256_; - reg [1:0] _zz_257_; - reg _zz_258_; - reg _zz_259_; - wire _zz_260_; - wire [2:0] _zz_261_; - reg _zz_262_; - wire [31:0] _zz_263_; - reg _zz_264_; - reg _zz_265_; - wire _zz_266_; - wire [31:0] _zz_267_; - wire _zz_268_; - wire _zz_269_; - reg [31:0] _zz_270_; - reg [31:0] _zz_271_; - reg [31:0] _zz_272_; - reg _zz_273_; - reg _zz_274_; - reg _zz_275_; - reg [9:0] _zz_276_; - reg [9:0] _zz_277_; - reg [9:0] _zz_278_; - reg [9:0] _zz_279_; - reg _zz_280_; - reg _zz_281_; - reg _zz_282_; - reg _zz_283_; - reg _zz_284_; - reg _zz_285_; - reg _zz_286_; - reg [9:0] _zz_287_; - reg [9:0] _zz_288_; - reg [9:0] _zz_289_; - reg [9:0] _zz_290_; - reg _zz_291_; - reg _zz_292_; - reg _zz_293_; - reg _zz_294_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1__io_cpu_memory_isWrite; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; - wire dataCache_1__io_cpu_memory_mmuBus_end; - wire dataCache_1__io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1__io_cpu_writeBack_data; - wire dataCache_1__io_cpu_writeBack_mmuException; - wire dataCache_1__io_cpu_writeBack_unalignedAccess; - wire dataCache_1__io_cpu_writeBack_accessError; - wire dataCache_1__io_cpu_writeBack_isWrite; - wire dataCache_1__io_cpu_flush_ready; - wire dataCache_1__io_cpu_redo; - wire dataCache_1__io_mem_cmd_valid; - wire dataCache_1__io_mem_cmd_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_payload_length; - wire dataCache_1__io_mem_cmd_payload_last; - wire _zz_295_; - wire _zz_296_; - wire _zz_297_; - wire _zz_298_; - wire _zz_299_; - wire _zz_300_; - wire _zz_301_; - wire _zz_302_; - wire _zz_303_; - wire _zz_304_; - wire _zz_305_; - wire _zz_306_; - wire _zz_307_; - wire _zz_308_; - wire _zz_309_; - wire _zz_310_; - wire _zz_311_; - wire _zz_312_; - wire [1:0] _zz_313_; - wire _zz_314_; - wire _zz_315_; - wire _zz_316_; - wire _zz_317_; - wire _zz_318_; - wire _zz_319_; - wire _zz_320_; - wire _zz_321_; - wire _zz_322_; - wire _zz_323_; - wire _zz_324_; - wire _zz_325_; - wire _zz_326_; - wire _zz_327_; - wire _zz_328_; - wire [1:0] _zz_329_; - wire _zz_330_; - wire [5:0] _zz_331_; - wire _zz_332_; - wire _zz_333_; - wire _zz_334_; - wire _zz_335_; - wire _zz_336_; - wire _zz_337_; - wire _zz_338_; - wire _zz_339_; - wire _zz_340_; - wire _zz_341_; - wire _zz_342_; - wire _zz_343_; - wire _zz_344_; - wire _zz_345_; - wire _zz_346_; - wire _zz_347_; - wire _zz_348_; - wire _zz_349_; - wire _zz_350_; - wire _zz_351_; - wire _zz_352_; - wire _zz_353_; - wire _zz_354_; - wire [1:0] _zz_355_; - wire _zz_356_; - wire [1:0] _zz_357_; - wire [4:0] _zz_358_; - wire [2:0] _zz_359_; - wire [31:0] _zz_360_; - wire [11:0] _zz_361_; - wire [31:0] _zz_362_; - wire [19:0] _zz_363_; - wire [11:0] _zz_364_; - wire [31:0] _zz_365_; - wire [31:0] _zz_366_; - wire [19:0] _zz_367_; - wire [11:0] _zz_368_; - wire [2:0] _zz_369_; - wire [2:0] _zz_370_; - wire [0:0] _zz_371_; - wire [1:0] _zz_372_; - wire [0:0] _zz_373_; - wire [1:0] _zz_374_; - wire [0:0] _zz_375_; - wire [0:0] _zz_376_; - wire [0:0] _zz_377_; - wire [0:0] _zz_378_; - wire [0:0] _zz_379_; - wire [0:0] _zz_380_; - wire [0:0] _zz_381_; - wire [0:0] _zz_382_; - wire [0:0] _zz_383_; - wire [0:0] _zz_384_; - wire [0:0] _zz_385_; - wire [0:0] _zz_386_; - wire [0:0] _zz_387_; - wire [0:0] _zz_388_; - wire [0:0] _zz_389_; - wire [0:0] _zz_390_; - wire [0:0] _zz_391_; - wire [0:0] _zz_392_; - wire [0:0] _zz_393_; - wire [0:0] _zz_394_; - wire [0:0] _zz_395_; - wire [0:0] _zz_396_; - wire [0:0] _zz_397_; - wire [0:0] _zz_398_; - wire [0:0] _zz_399_; - wire [0:0] _zz_400_; - wire [0:0] _zz_401_; - wire [0:0] _zz_402_; - wire [0:0] _zz_403_; - wire [0:0] _zz_404_; - wire [2:0] _zz_405_; - wire [4:0] _zz_406_; - wire [11:0] _zz_407_; - wire [11:0] _zz_408_; - wire [31:0] _zz_409_; - wire [31:0] _zz_410_; - wire [31:0] _zz_411_; - wire [31:0] _zz_412_; - wire [31:0] _zz_413_; - wire [31:0] _zz_414_; - wire [31:0] _zz_415_; - wire [32:0] _zz_416_; - wire [31:0] _zz_417_; - wire [32:0] _zz_418_; - wire [11:0] _zz_419_; - wire [19:0] _zz_420_; - wire [11:0] _zz_421_; - wire [31:0] _zz_422_; - wire [31:0] _zz_423_; - wire [31:0] _zz_424_; - wire [11:0] _zz_425_; - wire [19:0] _zz_426_; - wire [11:0] _zz_427_; - wire [2:0] _zz_428_; - wire [1:0] _zz_429_; - wire [1:0] _zz_430_; - wire [51:0] _zz_431_; - wire [51:0] _zz_432_; - wire [51:0] _zz_433_; - wire [32:0] _zz_434_; - wire [51:0] _zz_435_; - wire [49:0] _zz_436_; - wire [51:0] _zz_437_; - wire [49:0] _zz_438_; - wire [51:0] _zz_439_; - wire [65:0] _zz_440_; - wire [65:0] _zz_441_; - wire [31:0] _zz_442_; - wire [31:0] _zz_443_; - wire [0:0] _zz_444_; - wire [5:0] _zz_445_; - wire [32:0] _zz_446_; - wire [32:0] _zz_447_; - wire [31:0] _zz_448_; - wire [31:0] _zz_449_; - wire [32:0] _zz_450_; - wire [32:0] _zz_451_; - wire [32:0] _zz_452_; - wire [0:0] _zz_453_; - wire [32:0] _zz_454_; - wire [0:0] _zz_455_; - wire [32:0] _zz_456_; - wire [0:0] _zz_457_; - wire [31:0] _zz_458_; - wire [0:0] _zz_459_; - wire [0:0] _zz_460_; - wire [0:0] _zz_461_; - wire [0:0] _zz_462_; - wire [0:0] _zz_463_; - wire [0:0] _zz_464_; - wire [0:0] _zz_465_; - wire [0:0] _zz_466_; - wire [0:0] _zz_467_; - wire [0:0] _zz_468_; - wire [0:0] _zz_469_; - wire [0:0] _zz_470_; - wire [0:0] _zz_471_; - wire [0:0] _zz_472_; - wire [0:0] _zz_473_; - wire [0:0] _zz_474_; - wire [0:0] _zz_475_; - wire [0:0] _zz_476_; - wire [0:0] _zz_477_; - wire [0:0] _zz_478_; - wire [0:0] _zz_479_; - wire [0:0] _zz_480_; - wire [0:0] _zz_481_; - wire [0:0] _zz_482_; - wire [0:0] _zz_483_; - wire [0:0] _zz_484_; - wire [0:0] _zz_485_; - wire [0:0] _zz_486_; - wire [0:0] _zz_487_; - wire [0:0] _zz_488_; - wire [0:0] _zz_489_; - wire [0:0] _zz_490_; - wire [0:0] _zz_491_; - wire [0:0] _zz_492_; - wire [0:0] _zz_493_; - wire [0:0] _zz_494_; - wire [0:0] _zz_495_; - wire [0:0] _zz_496_; - wire [0:0] _zz_497_; - wire [0:0] _zz_498_; - wire [0:0] _zz_499_; - wire [0:0] _zz_500_; - wire [0:0] _zz_501_; - wire [0:0] _zz_502_; - wire [0:0] _zz_503_; - wire [26:0] _zz_504_; - wire _zz_505_; - wire _zz_506_; - wire [2:0] _zz_507_; - wire _zz_508_; - wire _zz_509_; - wire _zz_510_; - wire [31:0] _zz_511_; - wire [31:0] _zz_512_; - wire [31:0] _zz_513_; - wire _zz_514_; - wire [1:0] _zz_515_; - wire [1:0] _zz_516_; - wire _zz_517_; - wire [0:0] _zz_518_; - wire [29:0] _zz_519_; - wire [31:0] _zz_520_; - wire [31:0] _zz_521_; - wire [31:0] _zz_522_; - wire [31:0] _zz_523_; - wire [0:0] _zz_524_; - wire [4:0] _zz_525_; - wire _zz_526_; - wire [0:0] _zz_527_; - wire [0:0] _zz_528_; - wire _zz_529_; - wire [0:0] _zz_530_; - wire [26:0] _zz_531_; - wire [31:0] _zz_532_; - wire [31:0] _zz_533_; - wire [31:0] _zz_534_; - wire _zz_535_; - wire [0:0] _zz_536_; - wire [1:0] _zz_537_; - wire [31:0] _zz_538_; - wire [0:0] _zz_539_; - wire [1:0] _zz_540_; - wire [0:0] _zz_541_; - wire [0:0] _zz_542_; - wire _zz_543_; - wire [0:0] _zz_544_; - wire [23:0] _zz_545_; - wire [31:0] _zz_546_; - wire [31:0] _zz_547_; - wire [31:0] _zz_548_; - wire _zz_549_; - wire [31:0] _zz_550_; - wire [31:0] _zz_551_; - wire _zz_552_; - wire _zz_553_; - wire [31:0] _zz_554_; - wire [31:0] _zz_555_; - wire _zz_556_; - wire [3:0] _zz_557_; - wire [3:0] _zz_558_; - wire _zz_559_; - wire [0:0] _zz_560_; - wire [21:0] _zz_561_; - wire [31:0] _zz_562_; - wire [31:0] _zz_563_; - wire [31:0] _zz_564_; - wire [31:0] _zz_565_; - wire _zz_566_; - wire [0:0] _zz_567_; - wire [1:0] _zz_568_; - wire [0:0] _zz_569_; - wire [1:0] _zz_570_; - wire [1:0] _zz_571_; - wire [1:0] _zz_572_; - wire _zz_573_; - wire [0:0] _zz_574_; - wire [19:0] _zz_575_; - wire [31:0] _zz_576_; - wire [31:0] _zz_577_; - wire [31:0] _zz_578_; - wire [31:0] _zz_579_; - wire [31:0] _zz_580_; - wire [31:0] _zz_581_; - wire [31:0] _zz_582_; - wire [31:0] _zz_583_; - wire [31:0] _zz_584_; - wire [31:0] _zz_585_; - wire [31:0] _zz_586_; - wire [0:0] _zz_587_; - wire [1:0] _zz_588_; - wire [1:0] _zz_589_; - wire [1:0] _zz_590_; - wire _zz_591_; - wire [0:0] _zz_592_; - wire [16:0] _zz_593_; - wire [31:0] _zz_594_; - wire [31:0] _zz_595_; - wire [31:0] _zz_596_; - wire [31:0] _zz_597_; - wire [31:0] _zz_598_; - wire [31:0] _zz_599_; - wire [31:0] _zz_600_; - wire _zz_601_; - wire _zz_602_; - wire _zz_603_; - wire [0:0] _zz_604_; - wire [0:0] _zz_605_; - wire _zz_606_; - wire [0:0] _zz_607_; - wire [13:0] _zz_608_; - wire [31:0] _zz_609_; - wire _zz_610_; - wire _zz_611_; - wire [0:0] _zz_612_; - wire [1:0] _zz_613_; - wire [4:0] _zz_614_; - wire [4:0] _zz_615_; - wire _zz_616_; - wire [0:0] _zz_617_; - wire [10:0] _zz_618_; - wire [31:0] _zz_619_; - wire [31:0] _zz_620_; - wire [31:0] _zz_621_; - wire [31:0] _zz_622_; - wire [31:0] _zz_623_; - wire [31:0] _zz_624_; - wire [31:0] _zz_625_; - wire _zz_626_; - wire [0:0] _zz_627_; - wire [1:0] _zz_628_; - wire _zz_629_; - wire [0:0] _zz_630_; - wire [2:0] _zz_631_; - wire [0:0] _zz_632_; - wire [0:0] _zz_633_; - wire [0:0] _zz_634_; - wire [0:0] _zz_635_; - wire _zz_636_; - wire [0:0] _zz_637_; - wire [7:0] _zz_638_; - wire [31:0] _zz_639_; - wire [31:0] _zz_640_; - wire [31:0] _zz_641_; - wire _zz_642_; - wire [31:0] _zz_643_; - wire [31:0] _zz_644_; - wire [31:0] _zz_645_; - wire _zz_646_; - wire [0:0] _zz_647_; - wire [0:0] _zz_648_; - wire [31:0] _zz_649_; - wire [31:0] _zz_650_; - wire [31:0] _zz_651_; - wire [31:0] _zz_652_; - wire [0:0] _zz_653_; - wire [0:0] _zz_654_; - wire [0:0] _zz_655_; - wire [0:0] _zz_656_; - wire _zz_657_; - wire [0:0] _zz_658_; - wire [5:0] _zz_659_; - wire [31:0] _zz_660_; - wire [31:0] _zz_661_; - wire [31:0] _zz_662_; - wire [31:0] _zz_663_; - wire [31:0] _zz_664_; - wire [31:0] _zz_665_; - wire [31:0] _zz_666_; - wire [31:0] _zz_667_; - wire [31:0] _zz_668_; - wire [31:0] _zz_669_; - wire _zz_670_; - wire [0:0] _zz_671_; - wire [0:0] _zz_672_; - wire _zz_673_; - wire [0:0] _zz_674_; - wire [3:0] _zz_675_; - wire _zz_676_; - wire [0:0] _zz_677_; - wire [0:0] _zz_678_; - wire [0:0] _zz_679_; - wire [0:0] _zz_680_; - wire _zz_681_; - wire _zz_682_; - wire _zz_683_; - wire [0:0] _zz_684_; - wire [1:0] _zz_685_; - wire [31:0] _zz_686_; - wire [31:0] _zz_687_; - wire _zz_688_; - wire [0:0] _zz_689_; - wire [2:0] _zz_690_; - wire [31:0] _zz_691_; - wire [31:0] _zz_692_; - wire [31:0] _zz_693_; - wire [31:0] _zz_694_; - wire [31:0] _zz_695_; - wire [31:0] _zz_696_; - wire [31:0] _zz_697_; - wire [31:0] _zz_698_; - wire _zz_699_; - wire _zz_700_; - wire [31:0] _zz_701_; - wire [31:0] _zz_702_; - wire [31:0] _zz_703_; - wire _zz_704_; - wire [0:0] _zz_705_; - wire [17:0] _zz_706_; - wire [31:0] _zz_707_; - wire [31:0] _zz_708_; - wire [31:0] _zz_709_; - wire _zz_710_; - wire [0:0] _zz_711_; - wire [11:0] _zz_712_; - wire [31:0] _zz_713_; - wire [31:0] _zz_714_; - wire [31:0] _zz_715_; - wire _zz_716_; - wire [0:0] _zz_717_; - wire [5:0] _zz_718_; - wire [31:0] _zz_719_; - wire [31:0] _zz_720_; - wire [31:0] _zz_721_; - wire _zz_722_; - wire _zz_723_; - wire _zz_724_; - wire _zz_725_; - wire _zz_726_; - wire [31:0] memory_PC; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_1_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_2_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_3_; - wire [31:0] execute_SHIFT_RIGHT; - wire decode_DO_EBREAK; - wire decode_SRC_LESS_UNSIGNED; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_4_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_5_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_6_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_7_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_8_; - wire decode_IS_CSR; - wire decode_IS_RS2_SIGNED; - wire [31:0] execute_MUL_LL; - wire decode_CSR_READ_OPCODE; - wire decode_MEMORY_LRSC; - wire [51:0] memory_MUL_LOW; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_9_; - wire `AluCtrlEnum_defaultEncoding_type _zz_10_; - wire `AluCtrlEnum_defaultEncoding_type _zz_11_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_12_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_13_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14_; - wire [31:0] execute_BRANCH_CALC; - wire memory_IS_MUL; - wire execute_IS_MUL; - wire decode_IS_MUL; - wire decode_CSR_WRITE_OPCODE; - wire decode_MEMORY_MANAGMENT; - wire decode_SRC2_FORCE_ZERO; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_15_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_16_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_17_; - wire execute_IS_DBUS_SHARING; - wire memory_IS_SFENCE_VMA; - wire execute_IS_SFENCE_VMA; - wire decode_IS_SFENCE_VMA; - wire `BranchCtrlEnum_defaultEncoding_type _zz_18_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_19_; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire [33:0] execute_MUL_HL; - wire decode_MEMORY_AMO; - wire [33:0] memory_MUL_HH; - wire [33:0] execute_MUL_HH; - wire decode_IS_RS1_SIGNED; - wire `EnvCtrlEnum_defaultEncoding_type _zz_20_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_21_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_22_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_23_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_24_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_25_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire decode_IS_DIV; - wire [33:0] execute_MUL_LH; - wire decode_PREDICTION_HAD_BRANCHED2; - wire execute_BRANCH_DO; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; - wire _zz_27_; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire writeBack_IS_MUL; - wire [33:0] writeBack_MUL_HH; - wire [51:0] writeBack_MUL_LOW; - wire [33:0] memory_MUL_HL; - wire [33:0] memory_MUL_LH; - wire [31:0] memory_MUL_LL; - wire [51:0] _zz_28_; - wire [33:0] _zz_29_; - wire [33:0] _zz_30_; - wire [33:0] _zz_31_; - wire [31:0] _zz_32_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34_; - wire _zz_35_; - wire _zz_36_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_37_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_38_; - wire [31:0] execute_PC; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_39_; - wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_40_; - wire _zz_41_; - wire _zz_42_; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_43_; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_44_; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45_; - wire [31:0] _zz_46_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_47_; - wire _zz_48_; - wire [31:0] _zz_49_; - wire [31:0] _zz_50_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_51_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_52_; - wire [31:0] _zz_53_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_54_; - wire [31:0] _zz_55_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_56_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_57_; - wire [31:0] _zz_58_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_59_; - wire [31:0] _zz_60_; - wire _zz_61_; - reg _zz_62_; - wire [31:0] _zz_63_; - wire [31:0] _zz_64_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_65_; - wire _zz_66_; - wire _zz_67_; - wire _zz_68_; - wire _zz_69_; - wire _zz_70_; - wire _zz_71_; - wire _zz_72_; - wire _zz_73_; - wire _zz_74_; - wire _zz_75_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_76_; - wire _zz_77_; - wire _zz_78_; - wire _zz_79_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_80_; - wire _zz_81_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_82_; - wire _zz_83_; - wire _zz_84_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_85_; - wire _zz_86_; - wire `AluCtrlEnum_defaultEncoding_type _zz_87_; - wire _zz_88_; - wire _zz_89_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_90_; - wire _zz_91_; - wire _zz_92_; - wire _zz_93_; - wire writeBack_IS_SFENCE_VMA; - wire writeBack_IS_DBUS_SHARING; - wire memory_IS_DBUS_SHARING; - wire _zz_94_; - reg [31:0] _zz_95_; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_ENABLE; - wire [1:0] _zz_96_; - wire execute_MEMORY_AMO; - wire execute_MEMORY_LRSC; - wire execute_MEMORY_MANAGMENT; - wire [31:0] execute_RS2; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_97_; - reg _zz_98_; - reg _zz_99_; - wire [31:0] _zz_100_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_101_; - wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_102_; - reg [31:0] _zz_103_; - wire [31:0] decode_PC; - wire [31:0] _zz_104_; - wire [31:0] _zz_105_; - wire [31:0] _zz_106_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_predictionJumpInterface_valid; - (* syn_keep , keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; - reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; - wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - reg IBusCachedPlugin_mmuBus_rsp_allowRead; - reg IBusCachedPlugin_mmuBus_rsp_allowWrite; - reg IBusCachedPlugin_mmuBus_rsp_allowExecute; - reg IBusCachedPlugin_mmuBus_rsp_exception; - reg IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; - reg DBusCachedPlugin_mmuBus_cmd_bypassTranslation; - reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - reg DBusCachedPlugin_mmuBus_rsp_allowRead; - reg DBusCachedPlugin_mmuBus_rsp_allowWrite; - reg DBusCachedPlugin_mmuBus_rsp_allowExecute; - reg DBusCachedPlugin_mmuBus_rsp_exception; - reg DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_107_; - reg MmuPlugin_dBusAccess_cmd_valid; - reg MmuPlugin_dBusAccess_cmd_ready; - reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; - wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; - wire MmuPlugin_dBusAccess_cmd_payload_write; - wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; - wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; - wire MmuPlugin_dBusAccess_rsp_valid; - wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; - wire MmuPlugin_dBusAccess_rsp_payload_error; - wire MmuPlugin_dBusAccess_rsp_payload_redo; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire externalInterruptS; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; - reg IBusCachedPlugin_injectionPort_valid; - reg IBusCachedPlugin_injectionPort_ready; - wire [31:0] IBusCachedPlugin_injectionPort_payload; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_108_; - wire [4:0] _zz_109_; - wire _zz_110_; - wire _zz_111_; - wire _zz_112_; - wire _zz_113_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_114_; - wire _zz_115_; - wire _zz_116_; - wire _zz_117_; - wire _zz_118_; - reg _zz_119_; - wire _zz_120_; - reg _zz_121_; - reg [31:0] _zz_122_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_decodeInput_valid; - wire IBusCachedPlugin_iBusRsp_decodeInput_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - reg IBusCachedPlugin_injector_decodeRemoved; - wire _zz_123_; - reg [18:0] _zz_124_; - wire _zz_125_; - reg [10:0] _zz_126_; - wire _zz_127_; - reg [18:0] _zz_128_; - reg _zz_129_; - wire _zz_130_; - reg [10:0] _zz_131_; - wire _zz_132_; - reg [18:0] _zz_133_; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_134_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; - wire dBus_cmd_payload_last; - wire dBus_rsp_valid; - wire [31:0] dBus_rsp_payload_data; - wire dBus_rsp_payload_error; - wire dataCache_1__io_mem_cmd_s2mPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; - reg _zz_135_; - reg _zz_136_; - reg [31:0] _zz_137_; - reg [31:0] _zz_138_; - reg [3:0] _zz_139_; - reg [2:0] _zz_140_; - reg _zz_141_; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg _zz_142_; - reg _zz_143_; - reg [31:0] _zz_144_; - reg [31:0] _zz_145_; - reg [3:0] _zz_146_; - reg [2:0] _zz_147_; - reg _zz_148_; - wire [31:0] _zz_149_; - reg [31:0] DBusCachedPlugin_rspCounter; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_150_; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_151_; - reg [31:0] _zz_152_; - wire _zz_153_; - reg [31:0] _zz_154_; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - reg DBusCachedPlugin_forceDatapath; - reg MmuPlugin_status_sum; - reg MmuPlugin_status_mxr; - reg MmuPlugin_status_mprv; - reg MmuPlugin_satp_mode; - reg [19:0] MmuPlugin_satp_ppn; - reg MmuPlugin_ports_0_cache_0_valid; - reg MmuPlugin_ports_0_cache_0_exception; - reg MmuPlugin_ports_0_cache_0_superPage; - reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; - reg MmuPlugin_ports_0_cache_0_allowRead; - reg MmuPlugin_ports_0_cache_0_allowWrite; - reg MmuPlugin_ports_0_cache_0_allowExecute; - reg MmuPlugin_ports_0_cache_0_allowUser; - reg MmuPlugin_ports_0_cache_1_valid; - reg MmuPlugin_ports_0_cache_1_exception; - reg MmuPlugin_ports_0_cache_1_superPage; - reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; - reg MmuPlugin_ports_0_cache_1_allowRead; - reg MmuPlugin_ports_0_cache_1_allowWrite; - reg MmuPlugin_ports_0_cache_1_allowExecute; - reg MmuPlugin_ports_0_cache_1_allowUser; - reg MmuPlugin_ports_0_cache_2_valid; - reg MmuPlugin_ports_0_cache_2_exception; - reg MmuPlugin_ports_0_cache_2_superPage; - reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; - reg MmuPlugin_ports_0_cache_2_allowRead; - reg MmuPlugin_ports_0_cache_2_allowWrite; - reg MmuPlugin_ports_0_cache_2_allowExecute; - reg MmuPlugin_ports_0_cache_2_allowUser; - reg MmuPlugin_ports_0_cache_3_valid; - reg MmuPlugin_ports_0_cache_3_exception; - reg MmuPlugin_ports_0_cache_3_superPage; - reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; - reg MmuPlugin_ports_0_cache_3_allowRead; - reg MmuPlugin_ports_0_cache_3_allowWrite; - reg MmuPlugin_ports_0_cache_3_allowExecute; - reg MmuPlugin_ports_0_cache_3_allowUser; - wire MmuPlugin_ports_0_cacheHits_0; - wire MmuPlugin_ports_0_cacheHits_1; - wire MmuPlugin_ports_0_cacheHits_2; - wire MmuPlugin_ports_0_cacheHits_3; - wire MmuPlugin_ports_0_cacheHit; - wire _zz_155_; - wire _zz_156_; - wire [1:0] _zz_157_; - wire MmuPlugin_ports_0_cacheLine_valid; - wire MmuPlugin_ports_0_cacheLine_exception; - wire MmuPlugin_ports_0_cacheLine_superPage; - wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; - wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; - wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; - wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; - wire MmuPlugin_ports_0_cacheLine_allowRead; - wire MmuPlugin_ports_0_cacheLine_allowWrite; - wire MmuPlugin_ports_0_cacheLine_allowExecute; - wire MmuPlugin_ports_0_cacheLine_allowUser; - reg MmuPlugin_ports_0_entryToReplace_willIncrement; - wire MmuPlugin_ports_0_entryToReplace_willClear; - reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; - reg [1:0] MmuPlugin_ports_0_entryToReplace_value; - wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; - wire MmuPlugin_ports_0_entryToReplace_willOverflow; - reg MmuPlugin_ports_0_requireMmuLockup; - reg MmuPlugin_ports_1_cache_0_valid; - reg MmuPlugin_ports_1_cache_0_exception; - reg MmuPlugin_ports_1_cache_0_superPage; - reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; - reg MmuPlugin_ports_1_cache_0_allowRead; - reg MmuPlugin_ports_1_cache_0_allowWrite; - reg MmuPlugin_ports_1_cache_0_allowExecute; - reg MmuPlugin_ports_1_cache_0_allowUser; - reg MmuPlugin_ports_1_cache_1_valid; - reg MmuPlugin_ports_1_cache_1_exception; - reg MmuPlugin_ports_1_cache_1_superPage; - reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; - reg MmuPlugin_ports_1_cache_1_allowRead; - reg MmuPlugin_ports_1_cache_1_allowWrite; - reg MmuPlugin_ports_1_cache_1_allowExecute; - reg MmuPlugin_ports_1_cache_1_allowUser; - reg MmuPlugin_ports_1_cache_2_valid; - reg MmuPlugin_ports_1_cache_2_exception; - reg MmuPlugin_ports_1_cache_2_superPage; - reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; - reg MmuPlugin_ports_1_cache_2_allowRead; - reg MmuPlugin_ports_1_cache_2_allowWrite; - reg MmuPlugin_ports_1_cache_2_allowExecute; - reg MmuPlugin_ports_1_cache_2_allowUser; - reg MmuPlugin_ports_1_cache_3_valid; - reg MmuPlugin_ports_1_cache_3_exception; - reg MmuPlugin_ports_1_cache_3_superPage; - reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; - reg MmuPlugin_ports_1_cache_3_allowRead; - reg MmuPlugin_ports_1_cache_3_allowWrite; - reg MmuPlugin_ports_1_cache_3_allowExecute; - reg MmuPlugin_ports_1_cache_3_allowUser; - wire MmuPlugin_ports_1_cacheHits_0; - wire MmuPlugin_ports_1_cacheHits_1; - wire MmuPlugin_ports_1_cacheHits_2; - wire MmuPlugin_ports_1_cacheHits_3; - wire MmuPlugin_ports_1_cacheHit; - wire _zz_158_; - wire _zz_159_; - wire [1:0] _zz_160_; - wire MmuPlugin_ports_1_cacheLine_valid; - wire MmuPlugin_ports_1_cacheLine_exception; - wire MmuPlugin_ports_1_cacheLine_superPage; - wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; - wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; - wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; - wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; - wire MmuPlugin_ports_1_cacheLine_allowRead; - wire MmuPlugin_ports_1_cacheLine_allowWrite; - wire MmuPlugin_ports_1_cacheLine_allowExecute; - wire MmuPlugin_ports_1_cacheLine_allowUser; - reg MmuPlugin_ports_1_entryToReplace_willIncrement; - wire MmuPlugin_ports_1_entryToReplace_willClear; - reg [1:0] MmuPlugin_ports_1_entryToReplace_valueNext; - reg [1:0] MmuPlugin_ports_1_entryToReplace_value; - wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; - wire MmuPlugin_ports_1_entryToReplace_willOverflow; - reg MmuPlugin_ports_1_requireMmuLockup; - reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1_; - reg [9:0] MmuPlugin_shared_vpn_0; - reg [9:0] MmuPlugin_shared_vpn_1; - reg [0:0] MmuPlugin_shared_portId; - wire MmuPlugin_shared_dBusRsp_pte_V; - wire MmuPlugin_shared_dBusRsp_pte_R; - wire MmuPlugin_shared_dBusRsp_pte_W; - wire MmuPlugin_shared_dBusRsp_pte_X; - wire MmuPlugin_shared_dBusRsp_pte_U; - wire MmuPlugin_shared_dBusRsp_pte_G; - wire MmuPlugin_shared_dBusRsp_pte_A; - wire MmuPlugin_shared_dBusRsp_pte_D; - wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; - wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; - wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; - wire MmuPlugin_shared_dBusRsp_exception; - wire MmuPlugin_shared_dBusRsp_leaf; - reg MmuPlugin_shared_pteBuffer_V; - reg MmuPlugin_shared_pteBuffer_R; - reg MmuPlugin_shared_pteBuffer_W; - reg MmuPlugin_shared_pteBuffer_X; - reg MmuPlugin_shared_pteBuffer_U; - reg MmuPlugin_shared_pteBuffer_G; - reg MmuPlugin_shared_pteBuffer_A; - reg MmuPlugin_shared_pteBuffer_D; - reg [1:0] MmuPlugin_shared_pteBuffer_RSW; - reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; - reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; - wire [35:0] _zz_161_; - wire _zz_162_; - wire _zz_163_; - wire _zz_164_; - wire _zz_165_; - wire _zz_166_; - wire _zz_167_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_168_; - wire `AluCtrlEnum_defaultEncoding_type _zz_169_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_170_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_171_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_172_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_173_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_174_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_175_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_176_; - reg [31:0] _zz_177_; - wire _zz_178_; - reg [19:0] _zz_179_; - wire _zz_180_; - reg [19:0] _zz_181_; - reg [31:0] _zz_182_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_183_; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_184_; - reg _zz_185_; - reg _zz_186_; - wire _zz_187_; - reg _zz_188_; - reg [4:0] _zz_189_; - reg [31:0] _zz_190_; - wire _zz_191_; - wire _zz_192_; - wire _zz_193_; - wire _zz_194_; - wire _zz_195_; - wire _zz_196_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_197_; - reg _zz_198_; - reg _zz_199_; - wire _zz_200_; - reg [19:0] _zz_201_; - wire _zz_202_; - reg [10:0] _zz_203_; - wire _zz_204_; - reg [18:0] _zz_205_; - reg _zz_206_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_207_; - reg [19:0] _zz_208_; - wire _zz_209_; - reg [10:0] _zz_210_; - wire _zz_211_; - reg [18:0] _zz_212_; - wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] _zz_213_; - wire [1:0] CsrPlugin_misa_base; - wire [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg CsrPlugin_medeleg_IAM; - reg CsrPlugin_medeleg_IAF; - reg CsrPlugin_medeleg_II; - reg CsrPlugin_medeleg_LAM; - reg CsrPlugin_medeleg_LAF; - reg CsrPlugin_medeleg_SAM; - reg CsrPlugin_medeleg_SAF; - reg CsrPlugin_medeleg_EU; - reg CsrPlugin_medeleg_ES; - reg CsrPlugin_medeleg_IPF; - reg CsrPlugin_medeleg_LPF; - reg CsrPlugin_medeleg_SPF; - reg CsrPlugin_mideleg_ST; - reg CsrPlugin_mideleg_SE; - reg CsrPlugin_mideleg_SS; - reg CsrPlugin_sstatus_SIE; - reg CsrPlugin_sstatus_SPIE; - reg [0:0] CsrPlugin_sstatus_SPP; - reg CsrPlugin_sip_SEIP_SOFT; - reg CsrPlugin_sip_SEIP_INPUT; - wire CsrPlugin_sip_SEIP_OR; - reg CsrPlugin_sip_STIP; - reg CsrPlugin_sip_SSIP; - reg CsrPlugin_sie_SEIE; - reg CsrPlugin_sie_STIE; - reg CsrPlugin_sie_SSIE; - reg [1:0] CsrPlugin_stvec_mode; - reg [29:0] CsrPlugin_stvec_base; - reg [31:0] CsrPlugin_sscratch; - reg CsrPlugin_scause_interrupt; - reg [3:0] CsrPlugin_scause_exceptionCode; - reg [31:0] CsrPlugin_stval; - reg [31:0] CsrPlugin_sepc; - reg [21:0] CsrPlugin_satp_PPN; - reg [8:0] CsrPlugin_satp_ASID; - reg [0:0] CsrPlugin_satp_MODE; - wire _zz_214_; - wire _zz_215_; - wire _zz_216_; - wire _zz_217_; - wire _zz_218_; - wire _zz_219_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_220_; - wire _zz_221_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - reg CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - reg execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - reg [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg execute_MulPlugin_aSigned; - reg execute_MulPlugin_bSigned; - wire [31:0] execute_MulPlugin_a; - wire [31:0] execute_MulPlugin_b; - wire [15:0] execute_MulPlugin_aULow; - wire [15:0] execute_MulPlugin_bULow; - wire [16:0] execute_MulPlugin_aSLow; - wire [16:0] execute_MulPlugin_bSLow; - wire [16:0] execute_MulPlugin_aHigh; - wire [16:0] execute_MulPlugin_bHigh; - wire [65:0] writeBack_MulPlugin_result; - reg [32:0] memory_DivPlugin_rs1; - reg [31:0] memory_DivPlugin_rs2; - reg [64:0] memory_DivPlugin_accumulator; - reg memory_DivPlugin_div_needRevert; - reg memory_DivPlugin_div_counter_willIncrement; - reg memory_DivPlugin_div_counter_willClear; - reg [5:0] memory_DivPlugin_div_counter_valueNext; - reg [5:0] memory_DivPlugin_div_counter_value; - wire memory_DivPlugin_div_counter_willOverflowIfInc; - wire memory_DivPlugin_div_counter_willOverflow; - reg memory_DivPlugin_div_done; - reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_222_; - wire [32:0] _zz_223_; - wire [32:0] _zz_224_; - wire [31:0] _zz_225_; - wire _zz_226_; - wire _zz_227_; - reg [32:0] _zz_228_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_229_; - wire [31:0] _zz_230_; - reg [31:0] _zz_231_; - wire [31:0] _zz_232_; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_233_; - reg DebugPlugin_resetIt_regNext; - reg execute_to_memory_BRANCH_DO; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg [31:0] decode_to_execute_RS2; - reg [33:0] execute_to_memory_MUL_LH; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_IS_RS1_SIGNED; - reg [33:0] execute_to_memory_MUL_HH; - reg [33:0] memory_to_writeBack_MUL_HH; - reg decode_to_execute_MEMORY_AMO; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg [33:0] execute_to_memory_MUL_HL; - reg decode_to_execute_MEMORY_WR; - reg execute_to_memory_MEMORY_WR; - reg memory_to_writeBack_MEMORY_WR; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg decode_to_execute_IS_SFENCE_VMA; - reg execute_to_memory_IS_SFENCE_VMA; - reg memory_to_writeBack_IS_SFENCE_VMA; - reg execute_to_memory_IS_DBUS_SHARING; - reg memory_to_writeBack_IS_DBUS_SHARING; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg decode_to_execute_MEMORY_MANAGMENT; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg memory_to_writeBack_IS_MUL; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg [51:0] memory_to_writeBack_MUL_LOW; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg decode_to_execute_MEMORY_LRSC; - reg decode_to_execute_CSR_READ_OPCODE; - reg [31:0] execute_to_memory_MUL_LL; - reg decode_to_execute_IS_RS2_SIGNED; - reg decode_to_execute_IS_CSR; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg [31:0] decode_to_execute_RS1; - reg decode_to_execute_DO_EBREAK; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg [2:0] _zz_234_; - reg [2:0] _zz_235_; - reg _zz_236_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_237_; - wire _zz_238_; - wire _zz_239_; - wire _zz_240_; - wire _zz_241_; - wire _zz_242_; - reg _zz_243_; - reg [31:0] dBusWishbone_DAT_MISO_regNext; - `ifndef SYNTHESIS - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_1__string; - reg [95:0] _zz_2__string; - reg [95:0] _zz_3__string; - reg [71:0] _zz_4__string; - reg [71:0] _zz_5__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_6__string; - reg [71:0] _zz_7__string; - reg [71:0] _zz_8__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_9__string; - reg [63:0] _zz_10__string; - reg [63:0] _zz_11__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_12__string; - reg [39:0] _zz_13__string; - reg [39:0] _zz_14__string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_15__string; - reg [23:0] _zz_16__string; - reg [23:0] _zz_17__string; - reg [31:0] _zz_18__string; - reg [31:0] _zz_19__string; - reg [39:0] _zz_20__string; - reg [39:0] _zz_21__string; - reg [39:0] _zz_22__string; - reg [39:0] _zz_23__string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_24__string; - reg [39:0] _zz_25__string; - reg [39:0] _zz_26__string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33__string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34__string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_37__string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_40__string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_45__string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_47__string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_52__string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_54__string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_57__string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_59__string; - reg [39:0] _zz_65__string; - reg [95:0] _zz_76__string; - reg [39:0] _zz_80__string; - reg [71:0] _zz_82__string; - reg [31:0] _zz_85__string; - reg [63:0] _zz_87__string; - reg [23:0] _zz_90__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_101__string; - reg [47:0] MmuPlugin_shared_state_1__string; - reg [23:0] _zz_168__string; - reg [63:0] _zz_169__string; - reg [31:0] _zz_170__string; - reg [71:0] _zz_171__string; - reg [39:0] _zz_172__string; - reg [95:0] _zz_173__string; - reg [39:0] _zz_174__string; - reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - `endif - - (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_295_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_296_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_297_ = 1'b1; - assign _zz_298_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_299_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_300_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_301_ = ((_zz_249_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_97_)); - assign _zz_302_ = ((_zz_249_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_98_)); - assign _zz_303_ = ((_zz_249_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_99_)); - assign _zz_304_ = ((_zz_249_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); - assign _zz_305_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_306_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_307_ = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_308_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0); - assign _zz_309_ = (! memory_DivPlugin_div_done); - assign _zz_310_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_311_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_312_ = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_313_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_314_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_315_ = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != (3'b000))); - assign _zz_316_ = (! dataCache_1__io_cpu_redo); - assign _zz_317_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_318_ = ((MmuPlugin_dBusAccess_rsp_valid && (! MmuPlugin_dBusAccess_rsp_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); - assign _zz_319_ = (MmuPlugin_shared_portId == (1'b1)); - assign _zz_320_ = (MmuPlugin_shared_portId == (1'b0)); - assign _zz_321_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_322_ = (1'b0 || (! 1'b1)); - assign _zz_323_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_324_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_325_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_326_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_327_ = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_328_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_329_ = execute_INSTRUCTION[13 : 12]; - assign _zz_330_ = (! memory_arbitration_isStuck); - assign _zz_331_ = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_332_ = (iBus_cmd_valid || (_zz_235_ != (3'b000))); - assign _zz_333_ = (_zz_269_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); - assign _zz_334_ = (IBusCachedPlugin_mmuBus_cmd_isValid && IBusCachedPlugin_mmuBus_rsp_refilling); - assign _zz_335_ = (DBusCachedPlugin_mmuBus_cmd_isValid && DBusCachedPlugin_mmuBus_rsp_refilling); - assign _zz_336_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b00)); - assign _zz_337_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b01)); - assign _zz_338_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b10)); - assign _zz_339_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b11)); - assign _zz_340_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b00)); - assign _zz_341_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b01)); - assign _zz_342_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b10)); - assign _zz_343_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b11)); - assign _zz_344_ = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == (2'b01))) || (CsrPlugin_privilege < (2'b01))); - assign _zz_345_ = ((_zz_214_ && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); - assign _zz_346_ = ((_zz_215_ && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); - assign _zz_347_ = ((_zz_216_ && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); - assign _zz_348_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_349_ = ((_zz_214_ && 1'b1) && (! (CsrPlugin_mideleg_ST != (1'b0)))); - assign _zz_350_ = ((_zz_215_ && 1'b1) && (! (CsrPlugin_mideleg_SS != (1'b0)))); - assign _zz_351_ = ((_zz_216_ && 1'b1) && (! (CsrPlugin_mideleg_SE != (1'b0)))); - assign _zz_352_ = ((_zz_217_ && 1'b1) && (! 1'b0)); - assign _zz_353_ = ((_zz_218_ && 1'b1) && (! 1'b0)); - assign _zz_354_ = ((_zz_219_ && 1'b1) && (! 1'b0)); - assign _zz_355_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_356_ = execute_INSTRUCTION[13]; - assign _zz_357_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_358_ = (_zz_108_ - (5'b00001)); - assign _zz_359_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_360_ = {29'd0, _zz_359_}; - assign _zz_361_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_362_ = {{_zz_124_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_363_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_364_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_365_ = {{_zz_126_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_366_ = {{_zz_128_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_367_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_368_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_369_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); - assign _zz_370_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); - assign _zz_371_ = MmuPlugin_ports_0_entryToReplace_willIncrement; - assign _zz_372_ = {1'd0, _zz_371_}; - assign _zz_373_ = MmuPlugin_ports_1_entryToReplace_willIncrement; - assign _zz_374_ = {1'd0, _zz_373_}; - assign _zz_375_ = MmuPlugin_dBusAccess_rsp_payload_data[0 : 0]; - assign _zz_376_ = MmuPlugin_dBusAccess_rsp_payload_data[1 : 1]; - assign _zz_377_ = MmuPlugin_dBusAccess_rsp_payload_data[2 : 2]; - assign _zz_378_ = MmuPlugin_dBusAccess_rsp_payload_data[3 : 3]; - assign _zz_379_ = MmuPlugin_dBusAccess_rsp_payload_data[4 : 4]; - assign _zz_380_ = MmuPlugin_dBusAccess_rsp_payload_data[5 : 5]; - assign _zz_381_ = MmuPlugin_dBusAccess_rsp_payload_data[6 : 6]; - assign _zz_382_ = MmuPlugin_dBusAccess_rsp_payload_data[7 : 7]; - assign _zz_383_ = _zz_161_[1 : 1]; - assign _zz_384_ = _zz_161_[2 : 2]; - assign _zz_385_ = _zz_161_[5 : 5]; - assign _zz_386_ = _zz_161_[6 : 6]; - assign _zz_387_ = _zz_161_[9 : 9]; - assign _zz_388_ = _zz_161_[12 : 12]; - assign _zz_389_ = _zz_161_[13 : 13]; - assign _zz_390_ = _zz_161_[16 : 16]; - assign _zz_391_ = _zz_161_[19 : 19]; - assign _zz_392_ = _zz_161_[20 : 20]; - assign _zz_393_ = _zz_161_[21 : 21]; - assign _zz_394_ = _zz_161_[24 : 24]; - assign _zz_395_ = _zz_161_[25 : 25]; - assign _zz_396_ = _zz_161_[26 : 26]; - assign _zz_397_ = _zz_161_[27 : 27]; - assign _zz_398_ = _zz_161_[28 : 28]; - assign _zz_399_ = _zz_161_[29 : 29]; - assign _zz_400_ = _zz_161_[30 : 30]; - assign _zz_401_ = _zz_161_[31 : 31]; - assign _zz_402_ = _zz_161_[32 : 32]; - assign _zz_403_ = _zz_161_[33 : 33]; - assign _zz_404_ = execute_SRC_LESS; - assign _zz_405_ = (3'b100); - assign _zz_406_ = execute_INSTRUCTION[19 : 15]; - assign _zz_407_ = execute_INSTRUCTION[31 : 20]; - assign _zz_408_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_409_ = ($signed(_zz_410_) + $signed(_zz_413_)); - assign _zz_410_ = ($signed(_zz_411_) + $signed(_zz_412_)); - assign _zz_411_ = execute_SRC1; - assign _zz_412_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_413_ = (execute_SRC_USE_SUB_LESS ? _zz_414_ : _zz_415_); - assign _zz_414_ = (32'b00000000000000000000000000000001); - assign _zz_415_ = (32'b00000000000000000000000000000000); - assign _zz_416_ = ($signed(_zz_418_) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_417_ = _zz_416_[31 : 0]; - assign _zz_418_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_419_ = execute_INSTRUCTION[31 : 20]; - assign _zz_420_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_421_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_422_ = {_zz_201_,execute_INSTRUCTION[31 : 20]}; - assign _zz_423_ = {{_zz_203_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_424_ = {{_zz_205_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_425_ = execute_INSTRUCTION[31 : 20]; - assign _zz_426_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_427_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_428_ = (3'b100); - assign _zz_429_ = (_zz_220_ & (~ _zz_430_)); - assign _zz_430_ = (_zz_220_ - (2'b01)); - assign _zz_431_ = ($signed(_zz_432_) + $signed(_zz_437_)); - assign _zz_432_ = ($signed(_zz_433_) + $signed(_zz_435_)); - assign _zz_433_ = (52'b0000000000000000000000000000000000000000000000000000); - assign _zz_434_ = {1'b0,memory_MUL_LL}; - assign _zz_435_ = {{19{_zz_434_[32]}}, _zz_434_}; - assign _zz_436_ = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_437_ = {{2{_zz_436_[49]}}, _zz_436_}; - assign _zz_438_ = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_439_ = {{2{_zz_438_[49]}}, _zz_438_}; - assign _zz_440_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_441_ = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_442_ = writeBack_MUL_LOW[31 : 0]; - assign _zz_443_ = writeBack_MulPlugin_result[63 : 32]; - assign _zz_444_ = memory_DivPlugin_div_counter_willIncrement; - assign _zz_445_ = {5'd0, _zz_444_}; - assign _zz_446_ = {1'd0, memory_DivPlugin_rs2}; - assign _zz_447_ = {_zz_222_,(! _zz_224_[32])}; - assign _zz_448_ = _zz_224_[31:0]; - assign _zz_449_ = _zz_223_[31:0]; - assign _zz_450_ = _zz_451_; - assign _zz_451_ = _zz_452_; - assign _zz_452_ = ({1'b0,(memory_DivPlugin_div_needRevert ? (~ _zz_225_) : _zz_225_)} + _zz_454_); - assign _zz_453_ = memory_DivPlugin_div_needRevert; - assign _zz_454_ = {32'd0, _zz_453_}; - assign _zz_455_ = _zz_227_; - assign _zz_456_ = {32'd0, _zz_455_}; - assign _zz_457_ = _zz_226_; - assign _zz_458_ = {31'd0, _zz_457_}; - assign _zz_459_ = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_460_ = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_461_ = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_462_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_463_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_464_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_465_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_466_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_467_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_468_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_469_ = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_470_ = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_471_ = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_472_ = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_473_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_474_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_475_ = execute_CsrPlugin_writeData[8 : 8]; - assign _zz_476_ = execute_CsrPlugin_writeData[2 : 2]; - assign _zz_477_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_478_ = execute_CsrPlugin_writeData[13 : 13]; - assign _zz_479_ = execute_CsrPlugin_writeData[4 : 4]; - assign _zz_480_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_481_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_482_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_483_ = execute_CsrPlugin_writeData[12 : 12]; - assign _zz_484_ = execute_CsrPlugin_writeData[15 : 15]; - assign _zz_485_ = execute_CsrPlugin_writeData[6 : 6]; - assign _zz_486_ = execute_CsrPlugin_writeData[0 : 0]; - assign _zz_487_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_488_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_489_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_490_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_491_ = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_492_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_493_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_494_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_495_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_496_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_497_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_498_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_499_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_500_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_501_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_502_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_503_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_504_ = (iBus_cmd_payload_address >>> 5); - assign _zz_505_ = 1'b1; - assign _zz_506_ = 1'b1; - assign _zz_507_ = {_zz_111_,{_zz_113_,_zz_112_}}; - assign _zz_508_ = decode_INSTRUCTION[31]; - assign _zz_509_ = decode_INSTRUCTION[31]; - assign _zz_510_ = decode_INSTRUCTION[7]; - assign _zz_511_ = (32'b00000000000000000001000000000000); - assign _zz_512_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000)); - assign _zz_513_ = (32'b00000000000000000010000000000000); - assign _zz_514_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001001000)) == (32'b00000000000000000100000000001000)); - assign _zz_515_ = {(_zz_520_ == _zz_521_),(_zz_522_ == _zz_523_)}; - assign _zz_516_ = (2'b00); - assign _zz_517_ = ({_zz_165_,{_zz_524_,_zz_525_}} != (7'b0000000)); - assign _zz_518_ = (_zz_526_ != (1'b0)); - assign _zz_519_ = {(_zz_527_ != _zz_528_),{_zz_529_,{_zz_530_,_zz_531_}}}; - assign _zz_520_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_521_ = (32'b00000000000000000010000000000000); - assign _zz_522_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); - assign _zz_523_ = (32'b00000000000000000001000000000000); - assign _zz_524_ = ((decode_INSTRUCTION & _zz_532_) == (32'b00000000000000000001000000010000)); - assign _zz_525_ = {(_zz_533_ == _zz_534_),{_zz_535_,{_zz_536_,_zz_537_}}}; - assign _zz_526_ = ((decode_INSTRUCTION & (32'b00010000000000000000000000001000)) == (32'b00000000000000000000000000001000)); - assign _zz_527_ = ((decode_INSTRUCTION & _zz_538_) == (32'b00000000000000000001000000001000)); - assign _zz_528_ = (1'b0); - assign _zz_529_ = (_zz_164_ != (1'b0)); - assign _zz_530_ = ({_zz_539_,_zz_540_} != (3'b000)); - assign _zz_531_ = {(_zz_541_ != _zz_542_),{_zz_543_,{_zz_544_,_zz_545_}}}; - assign _zz_532_ = (32'b00000000000000000001000000010000); - assign _zz_533_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_534_ = (32'b00000000000000000010000000010000); - assign _zz_535_ = ((decode_INSTRUCTION & _zz_546_) == (32'b00000000000000000010000000001000)); - assign _zz_536_ = (_zz_547_ == _zz_548_); - assign _zz_537_ = {_zz_162_,_zz_549_}; - assign _zz_538_ = (32'b00000000000000000101000001001000); - assign _zz_539_ = (_zz_550_ == _zz_551_); - assign _zz_540_ = {_zz_552_,_zz_553_}; - assign _zz_541_ = (_zz_554_ == _zz_555_); - assign _zz_542_ = (1'b0); - assign _zz_543_ = (_zz_556_ != (1'b0)); - assign _zz_544_ = (_zz_557_ != _zz_558_); - assign _zz_545_ = {_zz_559_,{_zz_560_,_zz_561_}}; - assign _zz_546_ = (32'b00000000000000000010000000001000); - assign _zz_547_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000)); - assign _zz_548_ = (32'b00000000000000000000000000010000); - assign _zz_549_ = ((decode_INSTRUCTION & _zz_562_) == (32'b00000000000000000000000000000000)); - assign _zz_550_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_551_ = (32'b00000000000000000000000001000000); - assign _zz_552_ = ((decode_INSTRUCTION & _zz_563_) == (32'b00000000000000000010000000010000)); - assign _zz_553_ = ((decode_INSTRUCTION & _zz_564_) == (32'b01000000000000000000000000110000)); - assign _zz_554_ = (decode_INSTRUCTION & (32'b00010000000000000000000000001000)); - assign _zz_555_ = (32'b00010000000000000000000000001000); - assign _zz_556_ = ((decode_INSTRUCTION & _zz_565_) == (32'b00000010000000000000000001010000)); - assign _zz_557_ = {_zz_566_,{_zz_567_,_zz_568_}}; - assign _zz_558_ = (4'b0000); - assign _zz_559_ = ({_zz_569_,_zz_570_} != (3'b000)); - assign _zz_560_ = (_zz_571_ != _zz_572_); - assign _zz_561_ = {_zz_573_,{_zz_574_,_zz_575_}}; - assign _zz_562_ = (32'b00000000000000000000000000101000); - assign _zz_563_ = (32'b00000000000000000010000000010100); - assign _zz_564_ = (32'b01000000000000000000000000110100); - assign _zz_565_ = (32'b00000010000000000011000001010000); - assign _zz_566_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000)); - assign _zz_567_ = ((decode_INSTRUCTION & _zz_576_) == (32'b00000000000000000000000000100000)); - assign _zz_568_ = {(_zz_577_ == _zz_578_),(_zz_579_ == _zz_580_)}; - assign _zz_569_ = _zz_165_; - assign _zz_570_ = {_zz_167_,(_zz_581_ == _zz_582_)}; - assign _zz_571_ = {_zz_167_,(_zz_583_ == _zz_584_)}; - assign _zz_572_ = (2'b00); - assign _zz_573_ = ((_zz_585_ == _zz_586_) != (1'b0)); - assign _zz_574_ = ({_zz_587_,_zz_588_} != (3'b000)); - assign _zz_575_ = {(_zz_589_ != _zz_590_),{_zz_591_,{_zz_592_,_zz_593_}}}; - assign _zz_576_ = (32'b00000000000000000000000001100100); - assign _zz_577_ = (decode_INSTRUCTION & (32'b00001000000000000000000001110000)); - assign _zz_578_ = (32'b00001000000000000000000000100000); - assign _zz_579_ = (decode_INSTRUCTION & (32'b00010000000000000000000001110000)); - assign _zz_580_ = (32'b00000000000000000000000000100000); - assign _zz_581_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); - assign _zz_582_ = (32'b00000000000000000000000000000100); - assign _zz_583_ = (decode_INSTRUCTION & (32'b00000000000000000000000001001100)); - assign _zz_584_ = (32'b00000000000000000000000000000100); - assign _zz_585_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_586_ = (32'b00000000000000000000000000100100); - assign _zz_587_ = ((decode_INSTRUCTION & _zz_594_) == (32'b00001000000000000000000000100000)); - assign _zz_588_ = {(_zz_595_ == _zz_596_),(_zz_597_ == _zz_598_)}; - assign _zz_589_ = {_zz_166_,(_zz_599_ == _zz_600_)}; - assign _zz_590_ = (2'b00); - assign _zz_591_ = ({_zz_601_,_zz_602_} != (2'b00)); - assign _zz_592_ = (_zz_603_ != (1'b0)); - assign _zz_593_ = {(_zz_604_ != _zz_605_),{_zz_606_,{_zz_607_,_zz_608_}}}; - assign _zz_594_ = (32'b00001000000000000000000000100000); - assign _zz_595_ = (decode_INSTRUCTION & (32'b00010000000000000000000000100000)); - assign _zz_596_ = (32'b00000000000000000000000000100000); - assign _zz_597_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); - assign _zz_598_ = (32'b00000000000000000000000000100000); - assign _zz_599_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_600_ = (32'b00000000000000000000000000000000); - assign _zz_601_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000000000000000001010000)); - assign _zz_602_ = ((decode_INSTRUCTION & (32'b00010010001000000011000001010000)) == (32'b00010000000000000000000001010000)); - assign _zz_603_ = ((decode_INSTRUCTION & (32'b00000010000100000011000001010000)) == (32'b00000000000000000000000001010000)); - assign _zz_604_ = ((decode_INSTRUCTION & _zz_609_) == (32'b00000010000000000000000000110000)); - assign _zz_605_ = (1'b0); - assign _zz_606_ = ({_zz_610_,_zz_611_} != (2'b00)); - assign _zz_607_ = ({_zz_612_,_zz_613_} != (3'b000)); - assign _zz_608_ = {(_zz_614_ != _zz_615_),{_zz_616_,{_zz_617_,_zz_618_}}}; - assign _zz_609_ = (32'b00000010000000000100000001110100); - assign _zz_610_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000110100)) == (32'b00000000000000000101000000010000)); - assign _zz_611_ = ((decode_INSTRUCTION & (32'b00000010000000000111000001100100)) == (32'b00000000000000000101000000100000)); - assign _zz_612_ = ((decode_INSTRUCTION & _zz_619_) == (32'b01000000000000000001000000010000)); - assign _zz_613_ = {(_zz_620_ == _zz_621_),(_zz_622_ == _zz_623_)}; - assign _zz_614_ = {(_zz_624_ == _zz_625_),{_zz_626_,{_zz_627_,_zz_628_}}}; - assign _zz_615_ = (5'b00000); - assign _zz_616_ = ({_zz_629_,{_zz_630_,_zz_631_}} != (5'b00000)); - assign _zz_617_ = ({_zz_632_,_zz_633_} != (2'b00)); - assign _zz_618_ = {(_zz_634_ != _zz_635_),{_zz_636_,{_zz_637_,_zz_638_}}}; - assign _zz_619_ = (32'b01000000000000000011000001010100); - assign _zz_620_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_621_ = (32'b00000000000000000001000000010000); - assign _zz_622_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100)); - assign _zz_623_ = (32'b00000000000000000001000000010000); - assign _zz_624_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_625_ = (32'b00000000000000000000000000000000); - assign _zz_626_ = ((decode_INSTRUCTION & _zz_639_) == (32'b00000000000000000000000000000000)); - assign _zz_627_ = (_zz_640_ == _zz_641_); - assign _zz_628_ = {_zz_642_,_zz_166_}; - assign _zz_629_ = ((decode_INSTRUCTION & _zz_643_) == (32'b00000000000000000000000001000000)); - assign _zz_630_ = (_zz_644_ == _zz_645_); - assign _zz_631_ = {_zz_646_,{_zz_647_,_zz_648_}}; - assign _zz_632_ = _zz_165_; - assign _zz_633_ = (_zz_649_ == _zz_650_); - assign _zz_634_ = (_zz_651_ == _zz_652_); - assign _zz_635_ = (1'b0); - assign _zz_636_ = ({_zz_653_,_zz_654_} != (2'b00)); - assign _zz_637_ = (_zz_655_ != _zz_656_); - assign _zz_638_ = {_zz_657_,{_zz_658_,_zz_659_}}; - assign _zz_639_ = (32'b00000000000000000000000000011000); - assign _zz_640_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); - assign _zz_641_ = (32'b00000000000000000010000000000000); - assign _zz_642_ = ((decode_INSTRUCTION & _zz_660_) == (32'b00000000000000000001000000000000)); - assign _zz_643_ = (32'b00000000000000000000000001000000); - assign _zz_644_ = (decode_INSTRUCTION & (32'b00000000000000000100000000100000)); - assign _zz_645_ = (32'b00000000000000000100000000100000); - assign _zz_646_ = ((decode_INSTRUCTION & _zz_661_) == (32'b00000000000000000000000000010000)); - assign _zz_647_ = _zz_162_; - assign _zz_648_ = (_zz_662_ == _zz_663_); - assign _zz_649_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100)); - assign _zz_650_ = (32'b00000000000000000000000000000100); - assign _zz_651_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_652_ = (32'b00000000000000000000000001000000); - assign _zz_653_ = (_zz_664_ == _zz_665_); - assign _zz_654_ = (_zz_666_ == _zz_667_); - assign _zz_655_ = (_zz_668_ == _zz_669_); - assign _zz_656_ = (1'b0); - assign _zz_657_ = (_zz_670_ != (1'b0)); - assign _zz_658_ = (_zz_671_ != _zz_672_); - assign _zz_659_ = {_zz_673_,{_zz_674_,_zz_675_}}; - assign _zz_660_ = (32'b00000000000000000101000000000100); - assign _zz_661_ = (32'b00000000000000000000000000110000); - assign _zz_662_ = (decode_INSTRUCTION & (32'b00000010000000000000000000101000)); - assign _zz_663_ = (32'b00000000000000000000000000100000); - assign _zz_664_ = (decode_INSTRUCTION & (32'b00000000000000000001000001010000)); - assign _zz_665_ = (32'b00000000000000000001000001010000); - assign _zz_666_ = (decode_INSTRUCTION & (32'b00000000000000000010000001010000)); - assign _zz_667_ = (32'b00000000000000000010000001010000); - assign _zz_668_ = (decode_INSTRUCTION & (32'b00000000000000000100000000010100)); - assign _zz_669_ = (32'b00000000000000000100000000010000); - assign _zz_670_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)); - assign _zz_671_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001100100)) == (32'b00000010000000000100000000100000)); - assign _zz_672_ = (1'b0); - assign _zz_673_ = (_zz_164_ != (1'b0)); - assign _zz_674_ = ({_zz_163_,_zz_676_} != (2'b00)); - assign _zz_675_ = {({_zz_677_,_zz_678_} != (2'b00)),{(_zz_679_ != _zz_680_),{_zz_681_,_zz_682_}}}; - assign _zz_676_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); - assign _zz_677_ = _zz_163_; - assign _zz_678_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); - assign _zz_679_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); - assign _zz_680_ = (1'b0); - assign _zz_681_ = ({_zz_162_,{_zz_683_,{_zz_684_,_zz_685_}}} != (5'b00000)); - assign _zz_682_ = ({(_zz_686_ == _zz_687_),{_zz_688_,{_zz_689_,_zz_690_}}} != (6'b000000)); - assign _zz_683_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000110000)) == (32'b00000000000000000010000000010000)); - assign _zz_684_ = ((decode_INSTRUCTION & _zz_691_) == (32'b00000000000000000000000000010000)); - assign _zz_685_ = {(_zz_692_ == _zz_693_),(_zz_694_ == _zz_695_)}; - assign _zz_686_ = (decode_INSTRUCTION & (32'b00000000000000000010000001000000)); - assign _zz_687_ = (32'b00000000000000000010000001000000); - assign _zz_688_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001000000)) == (32'b00000000000000000001000001000000)); - assign _zz_689_ = ((decode_INSTRUCTION & _zz_696_) == (32'b00000000000000000000000001000000)); - assign _zz_690_ = {(_zz_697_ == _zz_698_),{_zz_699_,_zz_700_}}; - assign _zz_691_ = (32'b00000000000000000001000000110000); - assign _zz_692_ = (decode_INSTRUCTION & (32'b00000010000000000011000000100000)); - assign _zz_693_ = (32'b00000000000000000000000000100000); - assign _zz_694_ = (decode_INSTRUCTION & (32'b00000010000000000010000001101000)); - assign _zz_695_ = (32'b00000000000000000010000000100000); - assign _zz_696_ = (32'b00000000000000000000000001010000); - assign _zz_697_ = (decode_INSTRUCTION & (32'b00000010000100000000000001000000)); - assign _zz_698_ = (32'b00000000000000000000000001000000); - assign _zz_699_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000111000)) == (32'b00000000000000000000000000000000)); - assign _zz_700_ = ((decode_INSTRUCTION & (32'b00011000000000000010000000001000)) == (32'b00010000000000000010000000001000)); - assign _zz_701_ = (32'b00000000000000000001000001111111); - assign _zz_702_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_703_ = (32'b00000000000000000010000001110011); - assign _zz_704_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_705_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_706_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_707_) == (32'b00000000000000000000000000000011)),{(_zz_708_ == _zz_709_),{_zz_710_,{_zz_711_,_zz_712_}}}}}}; - assign _zz_707_ = (32'b00000000000000000101000001011111); - assign _zz_708_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_709_ = (32'b00000000000000000000000001100011); - assign _zz_710_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_711_ = ((decode_INSTRUCTION & (32'b00011000000000000111000001111111)) == (32'b00000000000000000010000000101111)); - assign _zz_712_ = {((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & (32'b11101000000000000111000001111111)) == (32'b00001000000000000010000000101111)),{((decode_INSTRUCTION & _zz_713_) == (32'b00000000000000000101000000001111)),{(_zz_714_ == _zz_715_),{_zz_716_,{_zz_717_,_zz_718_}}}}}}; - assign _zz_713_ = (32'b00000001111100000111000001111111); - assign _zz_714_ = (decode_INSTRUCTION & (32'b10111100000000000111000001111111)); - assign _zz_715_ = (32'b00000000000000000101000000010011); - assign _zz_716_ = ((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)); - assign _zz_717_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000101000000110011)); - assign _zz_718_ = {((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & (32'b11111001111100000111000001111111)) == (32'b00010000000000000010000000101111)),{((decode_INSTRUCTION & _zz_719_) == (32'b00010010000000000000000001110011)),{(_zz_720_ == _zz_721_),{_zz_722_,_zz_723_}}}}}; - assign _zz_719_ = (32'b11111110000000000111111111111111); - assign _zz_720_ = (decode_INSTRUCTION & (32'b11011111111111111111111111111111)); - assign _zz_721_ = (32'b00010000001000000000000001110011); - assign _zz_722_ = ((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)); - assign _zz_723_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); - assign _zz_724_ = execute_INSTRUCTION[31]; - assign _zz_725_ = execute_INSTRUCTION[31]; - assign _zz_726_ = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_62_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_505_) begin - _zz_270_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_506_) begin - _zz_271_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_244_), - .io_cpu_prefetch_isValid(_zz_245_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_246_), - .io_cpu_fetch_isStuck(_zz_247_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_248_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_249_), - .io_cpu_decode_isStuck(_zz_250_), - .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), - .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), - .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), - .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), - .io_cpu_decode_isUser(_zz_251_), - .io_cpu_fill_valid(_zz_252_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - ._zz_10_(_zz_234_), - ._zz_11_(IBusCachedPlugin_injectionPort_payload), - .clk(clk), - .reset(reset) - ); - DataCache dataCache_1_ ( - .io_cpu_execute_isValid(_zz_253_), - .io_cpu_execute_address(_zz_254_), - .io_cpu_execute_args_wr(_zz_255_), - .io_cpu_execute_args_data(_zz_256_), - .io_cpu_execute_args_size(_zz_257_), - .io_cpu_execute_args_isLrsc(_zz_258_), - .io_cpu_execute_args_isAmo(_zz_259_), - .io_cpu_execute_args_amoCtrl_swap(_zz_260_), - .io_cpu_execute_args_amoCtrl_alu(_zz_261_), - .io_cpu_memory_isValid(_zz_262_), - .io_cpu_memory_isStuck(memory_arbitration_isStuck), - .io_cpu_memory_isRemoved(memory_arbitration_removeIt), - .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), - .io_cpu_memory_address(_zz_263_), - .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), - .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), - .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), - .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_264_), - .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), - .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), - .io_cpu_writeBack_isValid(_zz_265_), - .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), - .io_cpu_writeBack_isUser(_zz_266_), - .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), - .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), - .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), - .io_cpu_writeBack_address(_zz_267_), - .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), - .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), - .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), - .io_cpu_writeBack_clearLrsc(contextSwitching), - .io_cpu_redo(dataCache_1__io_cpu_redo), - .io_cpu_flush_valid(_zz_268_), - .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), - .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), - .io_mem_cmd_ready(_zz_269_), - .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), - .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), - .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), - .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), - .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), - .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), - .io_mem_rsp_valid(dBus_rsp_valid), - .io_mem_rsp_payload_data(dBus_rsp_payload_data), - .io_mem_rsp_payload_error(dBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); - always @(*) begin - case(_zz_507_) - 3'b000 : begin - _zz_272_ = DBusCachedPlugin_redoBranch_payload; - end - 3'b001 : begin - _zz_272_ = CsrPlugin_jumpInterface_payload; - end - 3'b010 : begin - _zz_272_ = BranchPlugin_jumpInterface_payload; - end - 3'b011 : begin - _zz_272_ = IBusCachedPlugin_redoBranch_payload; - end - default : begin - _zz_272_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - endcase - end - - always @(*) begin - case(_zz_157_) - 2'b00 : begin - _zz_273_ = MmuPlugin_ports_0_cache_0_valid; - _zz_274_ = MmuPlugin_ports_0_cache_0_exception; - _zz_275_ = MmuPlugin_ports_0_cache_0_superPage; - _zz_276_ = MmuPlugin_ports_0_cache_0_virtualAddress_0; - _zz_277_ = MmuPlugin_ports_0_cache_0_virtualAddress_1; - _zz_278_ = MmuPlugin_ports_0_cache_0_physicalAddress_0; - _zz_279_ = MmuPlugin_ports_0_cache_0_physicalAddress_1; - _zz_280_ = MmuPlugin_ports_0_cache_0_allowRead; - _zz_281_ = MmuPlugin_ports_0_cache_0_allowWrite; - _zz_282_ = MmuPlugin_ports_0_cache_0_allowExecute; - _zz_283_ = MmuPlugin_ports_0_cache_0_allowUser; - end - 2'b01 : begin - _zz_273_ = MmuPlugin_ports_0_cache_1_valid; - _zz_274_ = MmuPlugin_ports_0_cache_1_exception; - _zz_275_ = MmuPlugin_ports_0_cache_1_superPage; - _zz_276_ = MmuPlugin_ports_0_cache_1_virtualAddress_0; - _zz_277_ = MmuPlugin_ports_0_cache_1_virtualAddress_1; - _zz_278_ = MmuPlugin_ports_0_cache_1_physicalAddress_0; - _zz_279_ = MmuPlugin_ports_0_cache_1_physicalAddress_1; - _zz_280_ = MmuPlugin_ports_0_cache_1_allowRead; - _zz_281_ = MmuPlugin_ports_0_cache_1_allowWrite; - _zz_282_ = MmuPlugin_ports_0_cache_1_allowExecute; - _zz_283_ = MmuPlugin_ports_0_cache_1_allowUser; - end - 2'b10 : begin - _zz_273_ = MmuPlugin_ports_0_cache_2_valid; - _zz_274_ = MmuPlugin_ports_0_cache_2_exception; - _zz_275_ = MmuPlugin_ports_0_cache_2_superPage; - _zz_276_ = MmuPlugin_ports_0_cache_2_virtualAddress_0; - _zz_277_ = MmuPlugin_ports_0_cache_2_virtualAddress_1; - _zz_278_ = MmuPlugin_ports_0_cache_2_physicalAddress_0; - _zz_279_ = MmuPlugin_ports_0_cache_2_physicalAddress_1; - _zz_280_ = MmuPlugin_ports_0_cache_2_allowRead; - _zz_281_ = MmuPlugin_ports_0_cache_2_allowWrite; - _zz_282_ = MmuPlugin_ports_0_cache_2_allowExecute; - _zz_283_ = MmuPlugin_ports_0_cache_2_allowUser; - end - default : begin - _zz_273_ = MmuPlugin_ports_0_cache_3_valid; - _zz_274_ = MmuPlugin_ports_0_cache_3_exception; - _zz_275_ = MmuPlugin_ports_0_cache_3_superPage; - _zz_276_ = MmuPlugin_ports_0_cache_3_virtualAddress_0; - _zz_277_ = MmuPlugin_ports_0_cache_3_virtualAddress_1; - _zz_278_ = MmuPlugin_ports_0_cache_3_physicalAddress_0; - _zz_279_ = MmuPlugin_ports_0_cache_3_physicalAddress_1; - _zz_280_ = MmuPlugin_ports_0_cache_3_allowRead; - _zz_281_ = MmuPlugin_ports_0_cache_3_allowWrite; - _zz_282_ = MmuPlugin_ports_0_cache_3_allowExecute; - _zz_283_ = MmuPlugin_ports_0_cache_3_allowUser; - end - endcase - end - - always @(*) begin - case(_zz_160_) - 2'b00 : begin - _zz_284_ = MmuPlugin_ports_1_cache_0_valid; - _zz_285_ = MmuPlugin_ports_1_cache_0_exception; - _zz_286_ = MmuPlugin_ports_1_cache_0_superPage; - _zz_287_ = MmuPlugin_ports_1_cache_0_virtualAddress_0; - _zz_288_ = MmuPlugin_ports_1_cache_0_virtualAddress_1; - _zz_289_ = MmuPlugin_ports_1_cache_0_physicalAddress_0; - _zz_290_ = MmuPlugin_ports_1_cache_0_physicalAddress_1; - _zz_291_ = MmuPlugin_ports_1_cache_0_allowRead; - _zz_292_ = MmuPlugin_ports_1_cache_0_allowWrite; - _zz_293_ = MmuPlugin_ports_1_cache_0_allowExecute; - _zz_294_ = MmuPlugin_ports_1_cache_0_allowUser; - end - 2'b01 : begin - _zz_284_ = MmuPlugin_ports_1_cache_1_valid; - _zz_285_ = MmuPlugin_ports_1_cache_1_exception; - _zz_286_ = MmuPlugin_ports_1_cache_1_superPage; - _zz_287_ = MmuPlugin_ports_1_cache_1_virtualAddress_0; - _zz_288_ = MmuPlugin_ports_1_cache_1_virtualAddress_1; - _zz_289_ = MmuPlugin_ports_1_cache_1_physicalAddress_0; - _zz_290_ = MmuPlugin_ports_1_cache_1_physicalAddress_1; - _zz_291_ = MmuPlugin_ports_1_cache_1_allowRead; - _zz_292_ = MmuPlugin_ports_1_cache_1_allowWrite; - _zz_293_ = MmuPlugin_ports_1_cache_1_allowExecute; - _zz_294_ = MmuPlugin_ports_1_cache_1_allowUser; - end - 2'b10 : begin - _zz_284_ = MmuPlugin_ports_1_cache_2_valid; - _zz_285_ = MmuPlugin_ports_1_cache_2_exception; - _zz_286_ = MmuPlugin_ports_1_cache_2_superPage; - _zz_287_ = MmuPlugin_ports_1_cache_2_virtualAddress_0; - _zz_288_ = MmuPlugin_ports_1_cache_2_virtualAddress_1; - _zz_289_ = MmuPlugin_ports_1_cache_2_physicalAddress_0; - _zz_290_ = MmuPlugin_ports_1_cache_2_physicalAddress_1; - _zz_291_ = MmuPlugin_ports_1_cache_2_allowRead; - _zz_292_ = MmuPlugin_ports_1_cache_2_allowWrite; - _zz_293_ = MmuPlugin_ports_1_cache_2_allowExecute; - _zz_294_ = MmuPlugin_ports_1_cache_2_allowUser; - end - default : begin - _zz_284_ = MmuPlugin_ports_1_cache_3_valid; - _zz_285_ = MmuPlugin_ports_1_cache_3_exception; - _zz_286_ = MmuPlugin_ports_1_cache_3_superPage; - _zz_287_ = MmuPlugin_ports_1_cache_3_virtualAddress_0; - _zz_288_ = MmuPlugin_ports_1_cache_3_virtualAddress_1; - _zz_289_ = MmuPlugin_ports_1_cache_3_physicalAddress_0; - _zz_290_ = MmuPlugin_ports_1_cache_3_physicalAddress_1; - _zz_291_ = MmuPlugin_ports_1_cache_3_allowRead; - _zz_292_ = MmuPlugin_ports_1_cache_3_allowWrite; - _zz_293_ = MmuPlugin_ports_1_cache_3_allowExecute; - _zz_294_ = MmuPlugin_ports_1_cache_3_allowUser; - end - endcase - end - - `ifndef SYNTHESIS - always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_1_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_1__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_1__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_1__string = "URS1 "; - default : _zz_1__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_2_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_2__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_2__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_2__string = "URS1 "; - default : _zz_2__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_3_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_3__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_3__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_3__string = "URS1 "; - default : _zz_3__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_4_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_4__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_4__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_4__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_4__string = "SRA_1 "; - default : _zz_4__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_5_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_5__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_5__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_5__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_5__string = "SRA_1 "; - default : _zz_5__string = "?????????"; - endcase - end - always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_6_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_6__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_6__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_6__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_6__string = "SRA_1 "; - default : _zz_6__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_7_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_7__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_7__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_7__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_7__string = "SRA_1 "; - default : _zz_7__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_8_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_8__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_8__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_8__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_8__string = "SRA_1 "; - default : _zz_8__string = "?????????"; - endcase - end - always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_9_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_9__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_9__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_9__string = "BITWISE "; - default : _zz_9__string = "????????"; - endcase - end - always @(*) begin - case(_zz_10_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10__string = "BITWISE "; - default : _zz_10__string = "????????"; - endcase - end - always @(*) begin - case(_zz_11_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_11__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_11__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_11__string = "BITWISE "; - default : _zz_11__string = "????????"; - endcase - end - always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_12_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_12__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_12__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_12__string = "AND_1"; - default : _zz_12__string = "?????"; - endcase - end - always @(*) begin - case(_zz_13_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_13__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_13__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_13__string = "AND_1"; - default : _zz_13__string = "?????"; - endcase - end - always @(*) begin - case(_zz_14_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14__string = "AND_1"; - default : _zz_14__string = "?????"; - endcase - end - always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_15_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_15__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_15__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_15__string = "PC "; - default : _zz_15__string = "???"; - endcase - end - always @(*) begin - case(_zz_16_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_16__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_16__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_16__string = "PC "; - default : _zz_16__string = "???"; - endcase - end - always @(*) begin - case(_zz_17_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_17__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_17__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_17__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_17__string = "PC "; - default : _zz_17__string = "???"; - endcase - end - always @(*) begin - case(_zz_18_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_18__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_18__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_18__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_18__string = "JALR"; - default : _zz_18__string = "????"; - endcase - end - always @(*) begin - case(_zz_19_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_19__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_19__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_19__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_19__string = "JALR"; - default : _zz_19__string = "????"; - endcase - end - always @(*) begin - case(_zz_20_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_20__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_20__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_20__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_20__string = "ECALL"; - default : _zz_20__string = "?????"; - endcase - end - always @(*) begin - case(_zz_21_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_21__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_21__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_21__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_21__string = "ECALL"; - default : _zz_21__string = "?????"; - endcase - end - always @(*) begin - case(_zz_22_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_22__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_22__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_22__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_22__string = "ECALL"; - default : _zz_22__string = "?????"; - endcase - end - always @(*) begin - case(_zz_23_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_23__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_23__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_23__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_23__string = "ECALL"; - default : _zz_23__string = "?????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_24_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_24__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_24__string = "ECALL"; - default : _zz_24__string = "?????"; - endcase - end - always @(*) begin - case(_zz_25_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_25__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25__string = "ECALL"; - default : _zz_25__string = "?????"; - endcase - end - always @(*) begin - case(_zz_26_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_26__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL"; - default : _zz_26__string = "?????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_33_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33__string = "ECALL"; - default : _zz_33__string = "?????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; - default : execute_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_34_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34__string = "ECALL"; - default : _zz_34__string = "?????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; - default : writeBack_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_37_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_37__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_37__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_37__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_37__string = "ECALL"; - default : _zz_37__string = "?????"; - endcase - end - always @(*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_40_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_40__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_40__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_40__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_40__string = "JALR"; - default : _zz_40__string = "????"; - endcase - end - always @(*) begin - case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; - default : memory_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_45_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45__string = "SRA_1 "; - default : _zz_45__string = "?????????"; - endcase + always @(*) begin + case(_zz_33) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; + default : _zz_33_string = "?????????"; + endcase end always @(*) begin case(execute_SHIFT_CTRL) @@ -3870,12 +2859,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_47_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_47__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_47__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_47__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_47__string = "SRA_1 "; - default : _zz_47__string = "?????????"; + case(_zz_34) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; + default : _zz_34_string = "?????????"; endcase end always @(*) begin @@ -3888,12 +2877,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_52_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_52__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_52__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_52__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_52__string = "PC "; - default : _zz_52__string = "???"; + case(_zz_36) + `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; + default : _zz_36_string = "???"; endcase end always @(*) begin @@ -3906,12 +2895,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_54_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_54__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_54__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54__string = "URS1 "; - default : _zz_54__string = "????????????"; + case(_zz_37) + `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; + default : _zz_37_string = "????????????"; endcase end always @(*) begin @@ -3923,11 +2912,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_57_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_57__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_57__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_57__string = "BITWISE "; - default : _zz_57__string = "????????"; + case(_zz_38) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; + default : _zz_38_string = "????????"; endcase end always @(*) begin @@ -3939,72 +2928,72 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_59_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_59__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_59__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_59__string = "AND_1"; - default : _zz_59__string = "?????"; + case(_zz_39) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; + default : _zz_39_string = "?????"; endcase end always @(*) begin - case(_zz_65_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_65__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_65__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_65__string = "AND_1"; - default : _zz_65__string = "?????"; + case(_zz_43) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_76_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_76__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_76__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_76__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_76__string = "URS1 "; - default : _zz_76__string = "????????????"; + case(_zz_44) + `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; + default : _zz_44_string = "????"; endcase end always @(*) begin - case(_zz_80_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_80__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_80__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_80__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_80__string = "ECALL"; - default : _zz_80__string = "?????"; + case(_zz_45) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; + default : _zz_45_string = "?????????"; endcase end always @(*) begin - case(_zz_82_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_82__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_82__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_82__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_82__string = "SRA_1 "; - default : _zz_82__string = "?????????"; + case(_zz_46) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; + default : _zz_46_string = "?????"; endcase end always @(*) begin - case(_zz_85_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_85__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_85__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_85__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_85__string = "JALR"; - default : _zz_85__string = "????"; + case(_zz_47) + `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; + default : _zz_47_string = "???"; endcase end always @(*) begin - case(_zz_87_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_87__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_87__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_87__string = "BITWISE "; - default : _zz_87__string = "????????"; + case(_zz_48) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; + default : _zz_48_string = "????????"; endcase end always @(*) begin - case(_zz_90_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_90__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_90__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_90__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_90__string = "PC "; - default : _zz_90__string = "???"; + case(_zz_49) + `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; + default : _zz_49_string = "????????????"; endcase end always @(*) begin @@ -4017,119 +3006,100 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_101_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_101__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_101__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_101__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_101__string = "JALR"; - default : _zz_101__string = "????"; + case(_zz_52) + `BranchCtrlEnum_defaultEncoding_INC : _zz_52_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_52_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_52_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_52_string = "JALR"; + default : _zz_52_string = "????"; endcase end always @(*) begin - case(MmuPlugin_shared_state_1_) - `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1__string = "IDLE "; - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1__string = "L1_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1__string = "L1_RSP"; - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1__string = "L0_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1__string = "L0_RSP"; - default : MmuPlugin_shared_state_1__string = "??????"; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; + default : MmuPlugin_shared_state_1_string = "??????"; endcase end always @(*) begin - case(_zz_168_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_168__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_168__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_168__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_168__string = "PC "; - default : _zz_168__string = "???"; + case(_zz_111) + `Src1CtrlEnum_defaultEncoding_RS : _zz_111_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_111_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_111_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_111_string = "URS1 "; + default : _zz_111_string = "????????????"; endcase end always @(*) begin - case(_zz_169_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_169__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_169__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_169__string = "BITWISE "; - default : _zz_169__string = "????????"; + case(_zz_112) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_112_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_112_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_112_string = "BITWISE "; + default : _zz_112_string = "????????"; endcase end always @(*) begin - case(_zz_170_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_170__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_170__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_170__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_170__string = "JALR"; - default : _zz_170__string = "????"; + case(_zz_113) + `Src2CtrlEnum_defaultEncoding_RS : _zz_113_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_113_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_113_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_113_string = "PC "; + default : _zz_113_string = "???"; endcase end always @(*) begin - case(_zz_171_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_171__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_171__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_171__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_171__string = "SRA_1 "; - default : _zz_171__string = "?????????"; + case(_zz_114) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_114_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_114_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_114_string = "AND_1"; + default : _zz_114_string = "?????"; endcase end always @(*) begin - case(_zz_172_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_172__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_172__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_172__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_172__string = "ECALL"; - default : _zz_172__string = "?????"; + case(_zz_115) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_115_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_115_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_115_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_115_string = "SRA_1 "; + default : _zz_115_string = "?????????"; endcase end always @(*) begin - case(_zz_173_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_173__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_173__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_173__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_173__string = "URS1 "; - default : _zz_173__string = "????????????"; + case(_zz_116) + `BranchCtrlEnum_defaultEncoding_INC : _zz_116_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_116_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_116_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_116_string = "JALR"; + default : _zz_116_string = "????"; endcase end always @(*) begin - case(_zz_174_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_174__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_174__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_174__string = "AND_1"; - default : _zz_174__string = "?????"; + case(_zz_117) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_117_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_117_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_117_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_117_string = "ECALL"; + default : _zz_117_string = "?????"; endcase end always @(*) begin - case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; - default : decode_to_execute_ENV_CTRL_string = "?????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; - default : execute_to_memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; - default : memory_to_writeBack_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin @@ -4149,14 +3119,6 @@ module VexRiscv ( default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end always @(*) begin case(decode_to_execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; @@ -4176,76 +3138,102 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_PC = execute_to_memory_PC; + assign memory_MUL_LOW = ($signed(_zz_325) + $signed(_zz_333)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_335; + assign execute_REGFILE_WRITE_DATA = _zz_119; + assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_96_; - assign execute_REGFILE_WRITE_DATA = _zz_58_; - assign decode_SRC1_CTRL = _zz_1_; - assign _zz_2_ = _zz_3_; - assign execute_SHIFT_RIGHT = _zz_46_; - assign decode_DO_EBREAK = _zz_27_; - assign decode_SRC_LESS_UNSIGNED = _zz_67_; - assign _zz_4_ = _zz_5_; - assign decode_SHIFT_CTRL = _zz_6_; - assign _zz_7_ = _zz_8_; - assign decode_IS_CSR = _zz_86_; - assign decode_IS_RS2_SIGNED = _zz_89_; - assign execute_MUL_LL = _zz_32_; - assign decode_CSR_READ_OPCODE = _zz_35_; - assign decode_MEMORY_LRSC = _zz_73_; - assign memory_MUL_LOW = _zz_28_; - assign decode_ALU_CTRL = _zz_9_; - assign _zz_10_ = _zz_11_; - assign decode_ALU_BITWISE_CTRL = _zz_12_; - assign _zz_13_ = _zz_14_; - assign execute_BRANCH_CALC = _zz_38_; + assign execute_MEMORY_ADDRESS_LOW = _zz_213[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_337[0]; + assign decode_IS_RS1_SIGNED = _zz_338[0]; + assign decode_IS_DIV = _zz_339[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_81_; - assign decode_CSR_WRITE_OPCODE = _zz_36_; - assign decode_MEMORY_MANAGMENT = _zz_66_; - assign decode_SRC2_FORCE_ZERO = _zz_56_; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_84_; - assign decode_SRC2_CTRL = _zz_15_; - assign _zz_16_ = _zz_17_; - assign execute_IS_DBUS_SHARING = _zz_94_; + assign decode_IS_MUL = _zz_340[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_341[0]; + assign _zz_8 = _zz_9; + assign _zz_10 = _zz_11; + assign decode_SHIFT_CTRL = _zz_12; + assign _zz_13 = _zz_14; + assign decode_ALU_BITWISE_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_SRC_LESS_UNSIGNED = _zz_342[0]; assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; - assign decode_IS_SFENCE_VMA = _zz_74_; - assign _zz_18_ = _zz_19_; + assign decode_IS_SFENCE_VMA = _zz_343[0]; + assign decode_MEMORY_MANAGMENT = _zz_344[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_78_; - assign execute_MUL_HL = _zz_30_; - assign decode_MEMORY_AMO = _zz_69_; - assign memory_MUL_HH = execute_to_memory_MUL_HH; - assign execute_MUL_HH = _zz_29_; - assign decode_IS_RS1_SIGNED = _zz_71_; - assign _zz_20_ = _zz_21_; - assign _zz_22_ = _zz_23_; - assign decode_ENV_CTRL = _zz_24_; - assign _zz_25_ = _zz_26_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_92_; + assign decode_MEMORY_WR = _zz_345[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_346[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_347[0]; + assign decode_SRC2_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_ALU_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_SRC1_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_51; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_104_; - assign decode_IS_DIV = _zz_88_; - assign execute_MUL_LH = _zz_31_; - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_42_; - assign execute_BRANCH_DO = _zz_39_; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_91_; + assign decode_IS_EBREAK = _zz_348[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -4259,25 +3247,25 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33_; - assign execute_ENV_CTRL = _zz_34_; - assign writeBack_ENV_CTRL = _zz_37_; + assign memory_ENV_CTRL = _zz_27; + assign execute_ENV_CTRL = _zz_28; + assign writeBack_ENV_CTRL = _zz_29; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_41_; - assign execute_BRANCH_CTRL = _zz_40_; - assign decode_RS2_USE = _zz_75_; - assign decode_RS1_USE = _zz_83_; + assign execute_BRANCH_COND_RESULT = _zz_136; + assign execute_BRANCH_CTRL = _zz_30; + assign decode_RS2_USE = _zz_349[0]; + assign decode_RS1_USE = _zz_350[0]; always @ (*) begin - _zz_43_ = execute_REGFILE_WRITE_DATA; - if(_zz_295_)begin - _zz_43_ = execute_CsrPlugin_readData; + _zz_31 = execute_REGFILE_WRITE_DATA; + if(_zz_263)begin + _zz_31 = execute_CsrPlugin_readData; end if(DBusCachedPlugin_forceDatapath)begin - _zz_43_ = MmuPlugin_dBusAccess_cmd_payload_address; + _zz_31 = MmuPlugin_dBusAccess_cmd_payload_address; end end @@ -4288,60 +3276,60 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - decode_RS2 = _zz_63_; - if(_zz_188_)begin - if((_zz_189_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_190_; + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_296_)begin - if(_zz_297_)begin - if(_zz_192_)begin - decode_RS2 = _zz_95_; + if(_zz_264)begin + if(_zz_265)begin + if(_zz_129)begin + decode_RS2 = _zz_50; end end end - if(_zz_298_)begin + if(_zz_266)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_194_)begin - decode_RS2 = _zz_44_; + if(_zz_131)begin + decode_RS2 = _zz_32; end end end - if(_zz_299_)begin + if(_zz_267)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_196_)begin - decode_RS2 = _zz_43_; + if(_zz_133)begin + decode_RS2 = _zz_31; end end end end always @ (*) begin - decode_RS1 = _zz_64_; - if(_zz_188_)begin - if((_zz_189_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_190_; + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_296_)begin - if(_zz_297_)begin - if(_zz_191_)begin - decode_RS1 = _zz_95_; + if(_zz_264)begin + if(_zz_265)begin + if(_zz_128)begin + decode_RS1 = _zz_50; end end end - if(_zz_298_)begin + if(_zz_266)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_193_)begin - decode_RS1 = _zz_44_; + if(_zz_130)begin + decode_RS1 = _zz_32; end end end - if(_zz_299_)begin + if(_zz_267)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_195_)begin - decode_RS1 = _zz_43_; + if(_zz_132)begin + decode_RS1 = _zz_31; end end end @@ -4349,74 +3337,73 @@ module VexRiscv ( assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_44_ = memory_REGFILE_WRITE_DATA; + _zz_32 = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_44_ = _zz_184_; + _zz_32 = _zz_127; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_44_ = memory_SHIFT_RIGHT; + _zz_32 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_300_)begin - _zz_44_ = memory_DivPlugin_div_result; + if(_zz_268)begin + _zz_32 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_45_; - assign execute_SHIFT_CTRL = _zz_47_; + assign memory_SHIFT_CTRL = _zz_33; + assign execute_SHIFT_CTRL = _zz_34; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_51_ = execute_PC; - assign execute_SRC2_CTRL = _zz_52_; - assign execute_SRC1_CTRL = _zz_54_; - assign decode_SRC_USE_SUB_LESS = _zz_72_; - assign decode_SRC_ADD_ZERO = _zz_77_; - assign execute_SRC_ADD_SUB = _zz_50_; - assign execute_SRC_LESS = _zz_48_; - assign execute_ALU_CTRL = _zz_57_; - assign execute_SRC2 = _zz_53_; - assign execute_SRC1 = _zz_55_; - assign execute_ALU_BITWISE_CTRL = _zz_59_; - assign _zz_60_ = writeBack_INSTRUCTION; - assign _zz_61_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_62_ = 1'b0; + assign _zz_35 = execute_PC; + assign execute_SRC2_CTRL = _zz_36; + assign execute_SRC1_CTRL = _zz_37; + assign decode_SRC_USE_SUB_LESS = _zz_351[0]; + assign decode_SRC_ADD_ZERO = _zz_352[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_38; + assign execute_SRC2 = _zz_125; + assign execute_SRC1 = _zz_120; + assign execute_ALU_BITWISE_CTRL = _zz_39; + assign _zz_40 = writeBack_INSTRUCTION; + assign _zz_41 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_42 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_62_ = 1'b1; + _zz_42 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_100_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_68_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_353[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_93_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_476) == 32'h00001073),{(_zz_477 == _zz_478),{_zz_479,{_zz_480,_zz_481}}}}}}} != 25'h0); assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; always @ (*) begin - _zz_95_ = writeBack_REGFILE_WRITE_DATA; + _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_95_ = writeBack_DBusCachedPlugin_rspFormated; + _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_357_) + case(_zz_324) 2'b00 : begin - _zz_95_ = _zz_442_; + _zz_50 = _zz_410; end default : begin - _zz_95_ = _zz_443_; + _zz_50 = _zz_411; end endcase end @@ -4430,62 +3417,69 @@ module VexRiscv ( assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; assign execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; assign execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = _zz_49_; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_79_; - assign decode_FLUSH_ALL = _zz_70_; + assign decode_MEMORY_AMO = _zz_354[0]; + assign decode_MEMORY_LRSC = _zz_355[0]; + assign decode_MEMORY_ENABLE = _zz_356[0]; + assign decode_FLUSH_ALL = _zz_357[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_269)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_97_; - if(_zz_301_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_270)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin - _zz_97_ = _zz_98_; - if(_zz_302_)begin - _zz_97_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_271)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_98_ = _zz_99_; - if(_zz_303_)begin - _zz_98_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_272)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end + assign decode_BRANCH_CTRL = _zz_52; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_99_ = 1'b0; - if(_zz_304_)begin - _zz_99_ = 1'b1; + _zz_53 = execute_FORMAL_PC_NEXT; + if(CsrPlugin_redoInterface_valid)begin + _zz_53 = CsrPlugin_redoInterface_payload; end end - assign decode_BRANCH_CTRL = _zz_101_; - assign decode_INSTRUCTION = _zz_105_; always @ (*) begin - _zz_102_ = memory_FORMAL_PC_NEXT; + _zz_54 = memory_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin - _zz_102_ = BranchPlugin_jumpInterface_payload; + _zz_54 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_103_ = decode_FORMAL_PC_NEXT; + _zz_55 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_103_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_103_ = IBusCachedPlugin_redoBranch_payload; + _zz_55 = IBusCachedPlugin_predictionJumpInterface_payload; end end - assign decode_PC = _zz_106_; + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -4493,18 +3487,10 @@ module VexRiscv ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_234_) - 3'b000 : begin - end - 3'b001 : begin - end + case(_zz_169) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end - 3'b011 : begin - end - 3'b100 : begin - end default : begin end endcase @@ -4515,20 +3501,20 @@ module VexRiscv ( if(MmuPlugin_dBusAccess_cmd_valid)begin decode_arbitration_haltByOther = 1'b1; end - if((decode_arbitration_isValid && (_zz_185_ || _zz_186_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_305_)begin + if(_zz_273)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4539,28 +3525,25 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_305_)begin + if(_zz_273)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if((_zz_268_ && (! dataCache_1__io_cpu_flush_ready)))begin - execute_arbitration_haltItself = 1'b1; - end - if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + if(((_zz_236 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_306_)begin + if(_zz_274)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_295_)begin + if(_zz_263)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -4569,7 +3552,10 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_307_)begin + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_275)begin execute_arbitration_haltByOther = 1'b1; end end @@ -4586,8 +3572,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_307_)begin - if(_zz_308_)begin + if(_zz_275)begin + if(_zz_276)begin execute_arbitration_flushIt = 1'b1; end end @@ -4598,8 +3584,13 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_307_)begin - if(_zz_308_)begin + if(_zz_275)begin + if(_zz_276)begin + execute_arbitration_flushNext = 1'b1; + end + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin execute_arbitration_flushNext = 1'b1; end end @@ -4607,8 +3598,8 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_300_)begin - if(_zz_309_)begin + if(_zz_268)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end end @@ -4638,7 +3629,7 @@ module VexRiscv ( always @ (*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1__io_cpu_writeBack_haltIt)begin + if(dataCache_1_io_cpu_writeBack_haltIt)begin writeBack_arbitration_haltItself = 1'b1; end end @@ -4669,10 +3660,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_310_)begin + if(_zz_277)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_311_)begin + if(_zz_278)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -4683,74 +3674,73 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_310_)begin + if(_zz_277)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_311_)begin + if(_zz_278)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_307_)begin - if(_zz_308_)begin + if(_zz_275)begin + if(_zz_276)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_312_)begin + if(_zz_279)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; end - if(_zz_307_)begin - if(_zz_308_)begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end + end + + always @ (*) begin + _zz_56 = 1'b0; + if(DebugPlugin_godmode)begin + _zz_56 = 1'b1; end end always @ (*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin - IBusCachedPlugin_incomingInstruction = 1'b1; + CsrPlugin_inWfi = 1'b0; + if(_zz_274)begin + CsrPlugin_inWfi = 1'b1; end end always @ (*) begin - _zz_107_ = 1'b0; - if(DebugPlugin_godmode)begin - _zz_107_ = 1'b1; + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_310_)begin + if(_zz_277)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_311_)begin + if(_zz_278)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_310_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_277)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_311_)begin - case(_zz_313_) + if(_zz_278)begin + case(_zz_280) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -4784,21 +3774,26 @@ module VexRiscv ( end end - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); - assign _zz_108_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_109_ = (_zz_108_ & (~ _zz_358_)); - assign _zz_110_ = _zz_109_[3]; - assign _zz_111_ = _zz_109_[4]; - assign _zz_112_ = (_zz_109_[1] || _zz_110_); - assign _zz_113_ = (_zz_109_[2] || _zz_110_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_272_; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != 5'h0); + assign _zz_57 = {IBusCachedPlugin_predictionJumpInterface_valid,{CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; + assign _zz_58 = (_zz_57 & (~ _zz_358)); + assign _zz_59 = _zz_58[3]; + assign _zz_60 = _zz_58[4]; + assign _zz_61 = (_zz_58[1] || _zz_59); + assign _zz_62 = (_zz_58[2] || _zz_59); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_240; always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin @@ -4807,7 +3802,10 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_360_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_360); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end @@ -4815,12 +3813,28 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin @@ -4828,41 +3842,44 @@ module VexRiscv ( end end - assign _zz_114_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_114_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_114_); + assign _zz_63 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_63); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_63); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + if(IBusCachedPlugin_mmuBus_busy)begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_115_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_115_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_115_); + assign _zz_64 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_64); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_64); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_116_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_116_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_116_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_117_; - assign _zz_117_ = ((1'b0 && (! _zz_118_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_118_ = _zz_119_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_118_; + assign _zz_65 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_66; + assign _zz_66 = ((1'b0 && (! _zz_67)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_67 = _zz_68; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_67; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_120_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_120_ = _zz_121_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_120_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_122_; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_69)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_69 = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_69; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_71; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -4874,149 +3891,140 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin - decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - case(_zz_234_) - 3'b000 : begin - end - 3'b001 : begin - end + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_169) 3'b010 : begin decode_arbitration_isValid = 1'b1; end 3'b011 : begin decode_arbitration_isValid = 1'b1; end - 3'b100 : begin - end default : begin end endcase end - assign _zz_106_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - assign _zz_105_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - assign _zz_104_ = (decode_PC + (32'b00000000000000000000000000000100)); - assign _zz_123_ = _zz_361_[11]; - always @ (*) begin - _zz_124_[18] = _zz_123_; - _zz_124_[17] = _zz_123_; - _zz_124_[16] = _zz_123_; - _zz_124_[15] = _zz_123_; - _zz_124_[14] = _zz_123_; - _zz_124_[13] = _zz_123_; - _zz_124_[12] = _zz_123_; - _zz_124_[11] = _zz_123_; - _zz_124_[10] = _zz_123_; - _zz_124_[9] = _zz_123_; - _zz_124_[8] = _zz_123_; - _zz_124_[7] = _zz_123_; - _zz_124_[6] = _zz_123_; - _zz_124_[5] = _zz_123_; - _zz_124_[4] = _zz_123_; - _zz_124_[3] = _zz_123_; - _zz_124_[2] = _zz_123_; - _zz_124_[1] = _zz_123_; - _zz_124_[0] = _zz_123_; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_362_[31])); - if(_zz_129_)begin + assign _zz_72 = _zz_361[11]; + always @ (*) begin + _zz_73[18] = _zz_72; + _zz_73[17] = _zz_72; + _zz_73[16] = _zz_72; + _zz_73[15] = _zz_72; + _zz_73[14] = _zz_72; + _zz_73[13] = _zz_72; + _zz_73[12] = _zz_72; + _zz_73[11] = _zz_72; + _zz_73[10] = _zz_72; + _zz_73[9] = _zz_72; + _zz_73[8] = _zz_72; + _zz_73[7] = _zz_72; + _zz_73[6] = _zz_72; + _zz_73[5] = _zz_72; + _zz_73[4] = _zz_72; + _zz_73[3] = _zz_72; + _zz_73[2] = _zz_72; + _zz_73[1] = _zz_72; + _zz_73[0] = _zz_72; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_362[31])); + if(_zz_78)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_125_ = _zz_363_[19]; + assign _zz_74 = _zz_363[19]; always @ (*) begin - _zz_126_[10] = _zz_125_; - _zz_126_[9] = _zz_125_; - _zz_126_[8] = _zz_125_; - _zz_126_[7] = _zz_125_; - _zz_126_[6] = _zz_125_; - _zz_126_[5] = _zz_125_; - _zz_126_[4] = _zz_125_; - _zz_126_[3] = _zz_125_; - _zz_126_[2] = _zz_125_; - _zz_126_[1] = _zz_125_; - _zz_126_[0] = _zz_125_; + _zz_75[10] = _zz_74; + _zz_75[9] = _zz_74; + _zz_75[8] = _zz_74; + _zz_75[7] = _zz_74; + _zz_75[6] = _zz_74; + _zz_75[5] = _zz_74; + _zz_75[4] = _zz_74; + _zz_75[3] = _zz_74; + _zz_75[2] = _zz_74; + _zz_75[1] = _zz_74; + _zz_75[0] = _zz_74; end - assign _zz_127_ = _zz_364_[11]; + assign _zz_76 = _zz_364[11]; always @ (*) begin - _zz_128_[18] = _zz_127_; - _zz_128_[17] = _zz_127_; - _zz_128_[16] = _zz_127_; - _zz_128_[15] = _zz_127_; - _zz_128_[14] = _zz_127_; - _zz_128_[13] = _zz_127_; - _zz_128_[12] = _zz_127_; - _zz_128_[11] = _zz_127_; - _zz_128_[10] = _zz_127_; - _zz_128_[9] = _zz_127_; - _zz_128_[8] = _zz_127_; - _zz_128_[7] = _zz_127_; - _zz_128_[6] = _zz_127_; - _zz_128_[5] = _zz_127_; - _zz_128_[4] = _zz_127_; - _zz_128_[3] = _zz_127_; - _zz_128_[2] = _zz_127_; - _zz_128_[1] = _zz_127_; - _zz_128_[0] = _zz_127_; + _zz_77[18] = _zz_76; + _zz_77[17] = _zz_76; + _zz_77[16] = _zz_76; + _zz_77[15] = _zz_76; + _zz_77[14] = _zz_76; + _zz_77[13] = _zz_76; + _zz_77[12] = _zz_76; + _zz_77[11] = _zz_76; + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7] = _zz_76; + _zz_77[6] = _zz_76; + _zz_77[5] = _zz_76; + _zz_77[4] = _zz_76; + _zz_77[3] = _zz_76; + _zz_77[2] = _zz_76; + _zz_77[1] = _zz_76; + _zz_77[0] = _zz_76; end always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_129_ = _zz_365_[1]; + _zz_78 = _zz_365[1]; end default : begin - _zz_129_ = _zz_366_[1]; + _zz_78 = _zz_366[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_130_ = _zz_367_[19]; - always @ (*) begin - _zz_131_[10] = _zz_130_; - _zz_131_[9] = _zz_130_; - _zz_131_[8] = _zz_130_; - _zz_131_[7] = _zz_130_; - _zz_131_[6] = _zz_130_; - _zz_131_[5] = _zz_130_; - _zz_131_[4] = _zz_130_; - _zz_131_[3] = _zz_130_; - _zz_131_[2] = _zz_130_; - _zz_131_[1] = _zz_130_; - _zz_131_[0] = _zz_130_; - end - - assign _zz_132_ = _zz_368_[11]; - always @ (*) begin - _zz_133_[18] = _zz_132_; - _zz_133_[17] = _zz_132_; - _zz_133_[16] = _zz_132_; - _zz_133_[15] = _zz_132_; - _zz_133_[14] = _zz_132_; - _zz_133_[13] = _zz_132_; - _zz_133_[12] = _zz_132_; - _zz_133_[11] = _zz_132_; - _zz_133_[10] = _zz_132_; - _zz_133_[9] = _zz_132_; - _zz_133_[8] = _zz_132_; - _zz_133_[7] = _zz_132_; - _zz_133_[6] = _zz_132_; - _zz_133_[5] = _zz_132_; - _zz_133_[4] = _zz_132_; - _zz_133_[3] = _zz_132_; - _zz_133_[2] = _zz_132_; - _zz_133_[1] = _zz_132_; - _zz_133_[0] = _zz_132_; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_131_,{{{_zz_508_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_133_,{{{_zz_509_,_zz_510_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_79 = _zz_367[19]; + always @ (*) begin + _zz_80[10] = _zz_79; + _zz_80[9] = _zz_79; + _zz_80[8] = _zz_79; + _zz_80[7] = _zz_79; + _zz_80[6] = _zz_79; + _zz_80[5] = _zz_79; + _zz_80[4] = _zz_79; + _zz_80[3] = _zz_79; + _zz_80[2] = _zz_79; + _zz_80[1] = _zz_79; + _zz_80[0] = _zz_79; + end + + assign _zz_81 = _zz_368[11]; + always @ (*) begin + _zz_82[18] = _zz_81; + _zz_82[17] = _zz_81; + _zz_82[16] = _zz_81; + _zz_82[15] = _zz_81; + _zz_82[14] = _zz_81; + _zz_82[13] = _zz_81; + _zz_82[12] = _zz_81; + _zz_82[11] = _zz_81; + _zz_82[10] = _zz_81; + _zz_82[9] = _zz_81; + _zz_82[8] = _zz_81; + _zz_82[7] = _zz_81; + _zz_82[6] = _zz_81; + _zz_82[5] = _zz_81; + _zz_82[4] = _zz_81; + _zz_82[3] = _zz_81; + _zz_82[2] = _zz_81; + _zz_82[1] = _zz_81; + _zz_82[0] = _zz_81; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_80,{{{_zz_499,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_82,{{{_zz_500,_zz_501},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -5025,120 +4033,127 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_245_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_248_ = (32'b00000000000000000000000000000000); - assign _zz_246_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_247_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_249_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_250_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_251_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_100_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign _zz_204 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_205 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_206 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_205; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_208 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_209 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_210 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_304_)begin + if(_zz_272)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_302_)begin + if(_zz_270)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_314_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - end end always @ (*) begin - _zz_252_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_302_)begin - _zz_252_ = 1'b1; - end - if(_zz_314_)begin - _zz_252_ = 1'b0; + _zz_211 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_270)begin + _zz_211 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_303_)begin + if(_zz_271)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_301_)begin + if(_zz_269)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_303_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); - end - if(_zz_301_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_244_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_135_); - assign _zz_269_ = (! _zz_135_); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_135_ ? _zz_136_ : dataCache_1__io_mem_cmd_payload_wr); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_135_ ? _zz_137_ : dataCache_1__io_mem_cmd_payload_address); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_135_ ? _zz_138_ : dataCache_1__io_mem_cmd_payload_data); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_135_ ? _zz_139_ : dataCache_1__io_mem_cmd_payload_mask); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_135_ ? _zz_140_ : dataCache_1__io_mem_cmd_payload_length); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_135_ ? _zz_141_ : dataCache_1__io_mem_cmd_payload_last); - assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_142_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_143_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_144_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_145_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_146_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_147_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_148_; - assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_271)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_269)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_203 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_237 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + always @ (*) begin + _zz_51 = 1'b0; + if(decode_INSTRUCTION[25])begin + if(decode_MEMORY_LRSC)begin + _zz_51 = 1'b1; + end + if(decode_MEMORY_AMO)begin + _zz_51 = 1'b1; + end + end + end + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin - _zz_253_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + _zz_212 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_315_)begin - if(_zz_316_)begin - _zz_253_ = 1'b1; + if(_zz_281)begin + if(_zz_282)begin + _zz_212 = 1'b1; end end end end always @ (*) begin - _zz_254_ = execute_SRC_ADD; + _zz_213 = execute_SRC_ADD; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_315_)begin - _zz_254_ = MmuPlugin_dBusAccess_cmd_payload_address; + if(_zz_281)begin + _zz_213 = MmuPlugin_dBusAccess_cmd_payload_address; end end end always @ (*) begin - _zz_255_ = execute_MEMORY_WR; + _zz_214 = execute_MEMORY_WR; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_315_)begin - _zz_255_ = MmuPlugin_dBusAccess_cmd_payload_write; + if(_zz_281)begin + _zz_214 = MmuPlugin_dBusAccess_cmd_payload_write; end end end @@ -5146,98 +4161,98 @@ module VexRiscv ( always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_150_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_85 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_150_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_85 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_150_ = execute_RS2[31 : 0]; + _zz_85 = execute_RS2[31 : 0]; end endcase end always @ (*) begin - _zz_256_ = _zz_150_; + _zz_215 = _zz_85; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_315_)begin - _zz_256_ = MmuPlugin_dBusAccess_cmd_payload_data; + if(_zz_281)begin + _zz_215 = MmuPlugin_dBusAccess_cmd_payload_data; end end end always @ (*) begin - _zz_257_ = execute_DBusCachedPlugin_size; + _zz_216 = execute_DBusCachedPlugin_size; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_315_)begin - _zz_257_ = MmuPlugin_dBusAccess_cmd_payload_size; + if(_zz_281)begin + _zz_216 = MmuPlugin_dBusAccess_cmd_payload_size; end end end - assign _zz_268_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_236 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); always @ (*) begin - _zz_258_ = 1'b0; + _zz_217 = 1'b0; if(execute_MEMORY_LRSC)begin - _zz_258_ = 1'b1; + _zz_217 = 1'b1; end if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_315_)begin - _zz_258_ = 1'b0; + if(_zz_281)begin + _zz_217 = 1'b0; end end end always @ (*) begin - _zz_259_ = execute_MEMORY_AMO; + _zz_218 = execute_MEMORY_AMO; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_315_)begin - _zz_259_ = 1'b0; + if(_zz_281)begin + _zz_218 = 1'b0; end end end - assign _zz_261_ = execute_INSTRUCTION[31 : 29]; - assign _zz_260_ = execute_INSTRUCTION[27]; - assign _zz_96_ = _zz_254_[1 : 0]; + assign _zz_220 = execute_INSTRUCTION[31 : 29]; + assign _zz_219 = execute_INSTRUCTION[27]; always @ (*) begin - _zz_262_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + _zz_221 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); if(memory_IS_DBUS_SHARING)begin - _zz_262_ = 1'b1; + _zz_221 = 1'b1; end end - assign _zz_263_ = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + assign _zz_222 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_221; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_222; always @ (*) begin - DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; if(memory_IS_DBUS_SHARING)begin - DBusCachedPlugin_mmuBus_cmd_bypassTranslation = 1'b1; + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; end end + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_264_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_107_ && (! dataCache_1__io_cpu_memory_isWrite)))begin - _zz_264_ = 1'b1; + _zz_223 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_56 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_223 = 1'b1; end end - assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; always @ (*) begin - _zz_265_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + _zz_224 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); if(writeBack_IS_DBUS_SHARING)begin - _zz_265_ = 1'b1; + _zz_224 = 1'b1; end end - assign _zz_266_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_267_ = writeBack_REGFILE_WRITE_DATA; + assign _zz_225 = (CsrPlugin_privilege == 2'b00); + assign _zz_226 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_317_)begin - if(dataCache_1__io_cpu_redo)begin + if(_zz_283)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end @@ -5246,17 +4261,17 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_317_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin + if(_zz_283)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_redo)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end @@ -5264,94 +4279,94 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); - if(_zz_317_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_369_}; + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_283)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_369}; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_370_}; + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1__io_cpu_writeBack_mmuException)begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_370}; end end end always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; end 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; end 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; end default : begin end endcase end - assign _zz_151_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_152_[31] = _zz_151_; - _zz_152_[30] = _zz_151_; - _zz_152_[29] = _zz_151_; - _zz_152_[28] = _zz_151_; - _zz_152_[27] = _zz_151_; - _zz_152_[26] = _zz_151_; - _zz_152_[25] = _zz_151_; - _zz_152_[24] = _zz_151_; - _zz_152_[23] = _zz_151_; - _zz_152_[22] = _zz_151_; - _zz_152_[21] = _zz_151_; - _zz_152_[20] = _zz_151_; - _zz_152_[19] = _zz_151_; - _zz_152_[18] = _zz_151_; - _zz_152_[17] = _zz_151_; - _zz_152_[16] = _zz_151_; - _zz_152_[15] = _zz_151_; - _zz_152_[14] = _zz_151_; - _zz_152_[13] = _zz_151_; - _zz_152_[12] = _zz_151_; - _zz_152_[11] = _zz_151_; - _zz_152_[10] = _zz_151_; - _zz_152_[9] = _zz_151_; - _zz_152_[8] = _zz_151_; - _zz_152_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_153_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_154_[31] = _zz_153_; - _zz_154_[30] = _zz_153_; - _zz_154_[29] = _zz_153_; - _zz_154_[28] = _zz_153_; - _zz_154_[27] = _zz_153_; - _zz_154_[26] = _zz_153_; - _zz_154_[25] = _zz_153_; - _zz_154_[24] = _zz_153_; - _zz_154_[23] = _zz_153_; - _zz_154_[22] = _zz_153_; - _zz_154_[21] = _zz_153_; - _zz_154_[20] = _zz_153_; - _zz_154_[19] = _zz_153_; - _zz_154_[18] = _zz_153_; - _zz_154_[17] = _zz_153_; - _zz_154_[16] = _zz_153_; - _zz_154_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_355_) + assign _zz_86 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_87[31] = _zz_86; + _zz_87[30] = _zz_86; + _zz_87[29] = _zz_86; + _zz_87[28] = _zz_86; + _zz_87[27] = _zz_86; + _zz_87[26] = _zz_86; + _zz_87[25] = _zz_86; + _zz_87[24] = _zz_86; + _zz_87[23] = _zz_86; + _zz_87[22] = _zz_86; + _zz_87[21] = _zz_86; + _zz_87[20] = _zz_86; + _zz_87[19] = _zz_86; + _zz_87[18] = _zz_86; + _zz_87[17] = _zz_86; + _zz_87[16] = _zz_86; + _zz_87[15] = _zz_86; + _zz_87[14] = _zz_86; + _zz_87[13] = _zz_86; + _zz_87[12] = _zz_86; + _zz_87[11] = _zz_86; + _zz_87[10] = _zz_86; + _zz_87[9] = _zz_86; + _zz_87[8] = _zz_86; + _zz_87[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_88 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_89[31] = _zz_88; + _zz_89[30] = _zz_88; + _zz_89[29] = _zz_88; + _zz_89[28] = _zz_88; + _zz_89[27] = _zz_88; + _zz_89[26] = _zz_88; + _zz_89[25] = _zz_88; + _zz_89[24] = _zz_88; + _zz_89[23] = _zz_88; + _zz_89[22] = _zz_88; + _zz_89[21] = _zz_88; + _zz_89[20] = _zz_88; + _zz_89[19] = _zz_88; + _zz_89[18] = _zz_88; + _zz_89[17] = _zz_88; + _zz_89[16] = _zz_88; + _zz_89[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_322) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_152_; + writeBack_DBusCachedPlugin_rspFormated = _zz_87; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_154_; + writeBack_DBusCachedPlugin_rspFormated = _zz_89; end default : begin writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; @@ -5362,8 +4377,8 @@ module VexRiscv ( always @ (*) begin MmuPlugin_dBusAccess_cmd_ready = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_315_)begin - if(_zz_316_)begin + if(_zz_281)begin + if(_zz_282)begin MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); end end @@ -5373,229 +4388,272 @@ module VexRiscv ( always @ (*) begin DBusCachedPlugin_forceDatapath = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_315_)begin + if(_zz_281)begin DBusCachedPlugin_forceDatapath = 1'b1; end end end - assign _zz_94_ = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); - assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1__io_cpu_writeBack_isWrite)) && (dataCache_1__io_cpu_redo || (! dataCache_1__io_cpu_writeBack_haltIt))); - assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1__io_cpu_writeBack_data; - assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1__io_cpu_writeBack_unalignedAccess || dataCache_1__io_cpu_writeBack_accessError); - assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1__io_cpu_redo; - assign MmuPlugin_ports_0_cacheHits_0 = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHits_1 = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHits_2 = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHits_3 = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHit = ({MmuPlugin_ports_0_cacheHits_3,{MmuPlugin_ports_0_cacheHits_2,{MmuPlugin_ports_0_cacheHits_1,MmuPlugin_ports_0_cacheHits_0}}} != (4'b0000)); - assign _zz_155_ = (MmuPlugin_ports_0_cacheHits_1 || MmuPlugin_ports_0_cacheHits_3); - assign _zz_156_ = (MmuPlugin_ports_0_cacheHits_2 || MmuPlugin_ports_0_cacheHits_3); - assign _zz_157_ = {_zz_156_,_zz_155_}; - assign MmuPlugin_ports_0_cacheLine_valid = _zz_273_; - assign MmuPlugin_ports_0_cacheLine_exception = _zz_274_; - assign MmuPlugin_ports_0_cacheLine_superPage = _zz_275_; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_276_; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_277_; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_278_; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_279_; - assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_280_; - assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_281_; - assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_282_; - assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_283_; + assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); + assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1_io_cpu_writeBack_data; + assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); + assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; + assign MmuPlugin_ports_0_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_0_requireMmuLockupCalc = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + end + + always @ (*) begin + MmuPlugin_ports_0_cacheHitsCalc[0] = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[1] = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[2] = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[3] = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + end + + assign MmuPlugin_ports_0_cacheHit = (MmuPlugin_ports_0_cacheHitsCalc != 4'b0000); + assign _zz_90 = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign _zz_91 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_90); + assign _zz_92 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_90); + assign _zz_93 = {_zz_92,_zz_91}; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_241; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_242; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_243; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_244; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_245; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_246; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_247; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_248; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_249; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_250; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_251; always @ (*) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; - if(_zz_318_)begin - if(_zz_319_)begin + if(_zz_284)begin + if(_zz_285)begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; end end end assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; - assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == (2'b11)); + assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_372_); + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_372); if(MmuPlugin_ports_0_entryToReplace_willClear)begin - MmuPlugin_ports_0_entryToReplace_valueNext = (2'b00); + MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; end end always @ (*) begin - MmuPlugin_ports_0_requireMmuLockup = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == (2'b11))))begin - MmuPlugin_ports_0_requireMmuLockup = 1'b0; - end - if((CsrPlugin_privilege == (2'b11)))begin - if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == (2'b11))))begin - MmuPlugin_ports_0_requireMmuLockup = 1'b0; - end + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_virtualAddress[11 : 0]}; + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); end else begin - DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; end else begin - DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; end else begin - DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin - DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_exception = (MmuPlugin_ports_0_cacheHit && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == (2'b01))) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == (2'b00))))); + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); end else begin - DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_refilling = (! MmuPlugin_ports_0_cacheHit); + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin - DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1011) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1110)) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111)); + assign IBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_0_requireMmuLockupCalc); + assign IBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_0_cacheHitsCalc[0]; + assign IBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_0_cache_0_physicalAddress_1,(MmuPlugin_ports_0_cache_0_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_0_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_0_cacheHitsCalc[1]; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_0_cache_1_physicalAddress_1,(MmuPlugin_ports_0_cache_1_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_1_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_0_cacheHitsCalc[2]; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_0_cache_2_physicalAddress_1,(MmuPlugin_ports_0_cache_2_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_2_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_ports_1_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_1_requireMmuLockupCalc = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; end + if((CsrPlugin_privilege == 2'b11))begin + if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + end + end + + always @ (*) begin + MmuPlugin_ports_1_cacheHitsCalc[0] = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[1] = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[2] = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[3] = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); end - assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1011)) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1110))) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111))); - assign MmuPlugin_ports_1_cacheHits_0 = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHits_1 = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHits_2 = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHits_3 = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHit = ({MmuPlugin_ports_1_cacheHits_3,{MmuPlugin_ports_1_cacheHits_2,{MmuPlugin_ports_1_cacheHits_1,MmuPlugin_ports_1_cacheHits_0}}} != (4'b0000)); - assign _zz_158_ = (MmuPlugin_ports_1_cacheHits_1 || MmuPlugin_ports_1_cacheHits_3); - assign _zz_159_ = (MmuPlugin_ports_1_cacheHits_2 || MmuPlugin_ports_1_cacheHits_3); - assign _zz_160_ = {_zz_159_,_zz_158_}; - assign MmuPlugin_ports_1_cacheLine_valid = _zz_284_; - assign MmuPlugin_ports_1_cacheLine_exception = _zz_285_; - assign MmuPlugin_ports_1_cacheLine_superPage = _zz_286_; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_287_; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_288_; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_289_; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_290_; - assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_291_; - assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_292_; - assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_293_; - assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_294_; + assign MmuPlugin_ports_1_cacheHit = (MmuPlugin_ports_1_cacheHitsCalc != 4'b0000); + assign _zz_94 = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign _zz_95 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_94); + assign _zz_96 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_94); + assign _zz_97 = {_zz_96,_zz_95}; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_252; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_253; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_254; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_255; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_256; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_257; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_258; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_259; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_260; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_261; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_262; always @ (*) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; - if(_zz_318_)begin - if(_zz_320_)begin + if(_zz_284)begin + if(_zz_286)begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; end end end assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; - assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == (2'b11)); + assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_374_); + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_374); if(MmuPlugin_ports_1_entryToReplace_willClear)begin - MmuPlugin_ports_1_entryToReplace_valueNext = (2'b00); + MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; end end always @ (*) begin - MmuPlugin_ports_1_requireMmuLockup = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == (2'b11))))begin - MmuPlugin_ports_1_requireMmuLockup = 1'b0; - end - if((CsrPlugin_privilege == (2'b11)))begin - MmuPlugin_ports_1_requireMmuLockup = 1'b0; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_virtualAddress[11 : 0]}; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); end else begin - IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; end else begin - IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; end else begin - IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin - IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_exception = (MmuPlugin_ports_1_cacheHit && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == (2'b01))) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == (2'b00))))); + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); end else begin - IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_refilling = (! MmuPlugin_ports_1_cacheHit); + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin - IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; - end - end - - assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1011)) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1110))) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111))); - assign MmuPlugin_shared_dBusRsp_pte_V = _zz_375_[0]; - assign MmuPlugin_shared_dBusRsp_pte_R = _zz_376_[0]; - assign MmuPlugin_shared_dBusRsp_pte_W = _zz_377_[0]; - assign MmuPlugin_shared_dBusRsp_pte_X = _zz_378_[0]; - assign MmuPlugin_shared_dBusRsp_pte_U = _zz_379_[0]; - assign MmuPlugin_shared_dBusRsp_pte_G = _zz_380_[0]; - assign MmuPlugin_shared_dBusRsp_pte_A = _zz_381_[0]; - assign MmuPlugin_shared_dBusRsp_pte_D = _zz_382_[0]; - assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_dBusAccess_rsp_payload_data[9 : 8]; - assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_dBusAccess_rsp_payload_data[19 : 10]; - assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_dBusAccess_rsp_payload_data[31 : 20]; - assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_dBusAccess_rsp_payload_error); + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1011) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1110)) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111)); + assign DBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_1_requireMmuLockupCalc); + assign DBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_1_cacheHitsCalc[0]; + assign DBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_1_cache_0_physicalAddress_1,(MmuPlugin_ports_1_cache_0_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_0_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_1_cacheHitsCalc[1]; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_1_cache_1_physicalAddress_1,(MmuPlugin_ports_1_cache_1_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_1_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_1_cacheHitsCalc[2]; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_shared_dBusRsp_pte_V = _zz_375[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = _zz_376[0]; + assign MmuPlugin_shared_dBusRsp_pte_W = _zz_377[0]; + assign MmuPlugin_shared_dBusRsp_pte_X = _zz_378[0]; + assign MmuPlugin_shared_dBusRsp_pte_U = _zz_379[0]; + assign MmuPlugin_shared_dBusRsp_pte_G = _zz_380[0]; + assign MmuPlugin_shared_dBusRsp_pte_A = _zz_381[0]; + assign MmuPlugin_shared_dBusRsp_pte_D = _zz_382[0]; + assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; + assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; + assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; + assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); always @ (*) begin MmuPlugin_dBusAccess_cmd_valid = 1'b0; - case(MmuPlugin_shared_state_1_) + case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin end `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin @@ -5612,90 +4670,97 @@ module VexRiscv ( end assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; - assign MmuPlugin_dBusAccess_cmd_payload_size = (2'b10); + assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; always @ (*) begin - MmuPlugin_dBusAccess_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - case(MmuPlugin_shared_state_1_) + MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin end `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin - MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},(2'b00)}; + MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; end `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin end `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin - MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},(2'b00)}; + MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; end default : begin end endcase end - assign MmuPlugin_dBusAccess_cmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - assign MmuPlugin_dBusAccess_cmd_payload_writeMask = (4'bxxxx); - assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1_ != `MmuPlugin_shared_State_defaultEncoding_IDLE) && (MmuPlugin_shared_portId == (1'b1))); - assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1_ != `MmuPlugin_shared_State_defaultEncoding_IDLE) && (MmuPlugin_shared_portId == (1'b0))); - assign _zz_162_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)); - assign _zz_163_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_164_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000000000000000000)); - assign _zz_165_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_166_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000000000000)); - assign _zz_167_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_161_ = {(((decode_INSTRUCTION & _zz_511_) == (32'b00000000000000000001000000000000)) != (1'b0)),{((_zz_512_ == _zz_513_) != (1'b0)),{(_zz_514_ != (1'b0)),{(_zz_515_ != _zz_516_),{_zz_517_,{_zz_518_,_zz_519_}}}}}}; - assign _zz_93_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_701_) == (32'b00000000000000000001000001110011)),{(_zz_702_ == _zz_703_),{_zz_704_,{_zz_705_,_zz_706_}}}}}}} != (25'b0000000000000000000000000)); - assign _zz_92_ = _zz_383_[0]; - assign _zz_91_ = _zz_384_[0]; - assign _zz_168_ = _zz_161_[4 : 3]; - assign _zz_90_ = _zz_168_; - assign _zz_89_ = _zz_385_[0]; - assign _zz_88_ = _zz_386_[0]; - assign _zz_169_ = _zz_161_[8 : 7]; - assign _zz_87_ = _zz_169_; - assign _zz_86_ = _zz_387_[0]; - assign _zz_170_ = _zz_161_[11 : 10]; - assign _zz_85_ = _zz_170_; - assign _zz_84_ = _zz_388_[0]; - assign _zz_83_ = _zz_389_[0]; - assign _zz_171_ = _zz_161_[15 : 14]; - assign _zz_82_ = _zz_171_; - assign _zz_81_ = _zz_390_[0]; - assign _zz_172_ = _zz_161_[18 : 17]; - assign _zz_80_ = _zz_172_; - assign _zz_79_ = _zz_391_[0]; - assign _zz_78_ = _zz_392_[0]; - assign _zz_77_ = _zz_393_[0]; - assign _zz_173_ = _zz_161_[23 : 22]; - assign _zz_76_ = _zz_173_; - assign _zz_75_ = _zz_394_[0]; - assign _zz_74_ = _zz_395_[0]; - assign _zz_73_ = _zz_396_[0]; - assign _zz_72_ = _zz_397_[0]; - assign _zz_71_ = _zz_398_[0]; - assign _zz_70_ = _zz_399_[0]; - assign _zz_69_ = _zz_400_[0]; - assign _zz_68_ = _zz_401_[0]; - assign _zz_67_ = _zz_402_[0]; - assign _zz_66_ = _zz_403_[0]; - assign _zz_174_ = _zz_161_[35 : 34]; - assign _zz_65_ = _zz_174_; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; + always @ (*) begin + _zz_98[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); + _zz_98[1] = (((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)); + end + + assign _zz_99 = _zz_98; + always @ (*) begin + _zz_100[0] = _zz_99[1]; + _zz_100[1] = _zz_99[0]; + end + + assign _zz_101 = (_zz_100 & (~ _zz_383)); + always @ (*) begin + _zz_102[0] = _zz_101[1]; + _zz_102[1] = _zz_101[0]; + end + + assign MmuPlugin_shared_refills = _zz_102; + assign _zz_103 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); + assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[0]); + assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[1]); + assign _zz_105 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_106 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_107 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); + assign _zz_108 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_109 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_110 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_104 = {(((decode_INSTRUCTION & _zz_502) == 32'h00100050) != 1'b0),{(_zz_110 != 1'b0),{(_zz_110 != 1'b0),{(_zz_503 != _zz_504),{_zz_505,{_zz_506,_zz_507}}}}}}; + assign _zz_111 = _zz_104[2 : 1]; + assign _zz_49 = _zz_111; + assign _zz_112 = _zz_104[7 : 6]; + assign _zz_48 = _zz_112; + assign _zz_113 = _zz_104[9 : 8]; + assign _zz_47 = _zz_113; + assign _zz_114 = _zz_104[23 : 22]; + assign _zz_46 = _zz_114; + assign _zz_115 = _zz_104[25 : 24]; + assign _zz_45 = _zz_115; + assign _zz_116 = _zz_104[27 : 26]; + assign _zz_44 = _zz_116; + assign _zz_117 = _zz_104[30 : 29]; + assign _zz_43 = _zz_117; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_270_; - assign decode_RegFilePlugin_rs2Data = _zz_271_; - assign _zz_64_ = decode_RegFilePlugin_rs1Data; - assign _zz_63_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_238; + assign decode_RegFilePlugin_rs2Data = _zz_239; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_61_ && writeBack_arbitration_isFiring); - if(_zz_175_)begin + lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); + if(_zz_118)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_60_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_95_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; + if(_zz_118)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_50; + if(_zz_118)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -5713,361 +4778,354 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_176_ = execute_IntAluPlugin_bitwise; + _zz_119 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_176_ = {31'd0, _zz_404_}; + _zz_119 = {31'd0, _zz_384}; end default : begin - _zz_176_ = execute_SRC_ADD_SUB; + _zz_119 = execute_SRC_ADD_SUB; end endcase end - assign _zz_58_ = _zz_176_; - assign _zz_56_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_177_ = execute_RS1; + _zz_120 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_177_ = {29'd0, _zz_405_}; + _zz_120 = {29'd0, _zz_385}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_177_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_120 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_177_ = {27'd0, _zz_406_}; + _zz_120 = {27'd0, _zz_386}; end endcase end - assign _zz_55_ = _zz_177_; - assign _zz_178_ = _zz_407_[11]; - always @ (*) begin - _zz_179_[19] = _zz_178_; - _zz_179_[18] = _zz_178_; - _zz_179_[17] = _zz_178_; - _zz_179_[16] = _zz_178_; - _zz_179_[15] = _zz_178_; - _zz_179_[14] = _zz_178_; - _zz_179_[13] = _zz_178_; - _zz_179_[12] = _zz_178_; - _zz_179_[11] = _zz_178_; - _zz_179_[10] = _zz_178_; - _zz_179_[9] = _zz_178_; - _zz_179_[8] = _zz_178_; - _zz_179_[7] = _zz_178_; - _zz_179_[6] = _zz_178_; - _zz_179_[5] = _zz_178_; - _zz_179_[4] = _zz_178_; - _zz_179_[3] = _zz_178_; - _zz_179_[2] = _zz_178_; - _zz_179_[1] = _zz_178_; - _zz_179_[0] = _zz_178_; - end - - assign _zz_180_ = _zz_408_[11]; - always @ (*) begin - _zz_181_[19] = _zz_180_; - _zz_181_[18] = _zz_180_; - _zz_181_[17] = _zz_180_; - _zz_181_[16] = _zz_180_; - _zz_181_[15] = _zz_180_; - _zz_181_[14] = _zz_180_; - _zz_181_[13] = _zz_180_; - _zz_181_[12] = _zz_180_; - _zz_181_[11] = _zz_180_; - _zz_181_[10] = _zz_180_; - _zz_181_[9] = _zz_180_; - _zz_181_[8] = _zz_180_; - _zz_181_[7] = _zz_180_; - _zz_181_[6] = _zz_180_; - _zz_181_[5] = _zz_180_; - _zz_181_[4] = _zz_180_; - _zz_181_[3] = _zz_180_; - _zz_181_[2] = _zz_180_; - _zz_181_[1] = _zz_180_; - _zz_181_[0] = _zz_180_; + assign _zz_121 = _zz_387[11]; + always @ (*) begin + _zz_122[19] = _zz_121; + _zz_122[18] = _zz_121; + _zz_122[17] = _zz_121; + _zz_122[16] = _zz_121; + _zz_122[15] = _zz_121; + _zz_122[14] = _zz_121; + _zz_122[13] = _zz_121; + _zz_122[12] = _zz_121; + _zz_122[11] = _zz_121; + _zz_122[10] = _zz_121; + _zz_122[9] = _zz_121; + _zz_122[8] = _zz_121; + _zz_122[7] = _zz_121; + _zz_122[6] = _zz_121; + _zz_122[5] = _zz_121; + _zz_122[4] = _zz_121; + _zz_122[3] = _zz_121; + _zz_122[2] = _zz_121; + _zz_122[1] = _zz_121; + _zz_122[0] = _zz_121; + end + + assign _zz_123 = _zz_388[11]; + always @ (*) begin + _zz_124[19] = _zz_123; + _zz_124[18] = _zz_123; + _zz_124[17] = _zz_123; + _zz_124[16] = _zz_123; + _zz_124[15] = _zz_123; + _zz_124[14] = _zz_123; + _zz_124[13] = _zz_123; + _zz_124[12] = _zz_123; + _zz_124[11] = _zz_123; + _zz_124[10] = _zz_123; + _zz_124[9] = _zz_123; + _zz_124[8] = _zz_123; + _zz_124[7] = _zz_123; + _zz_124[6] = _zz_123; + _zz_124[5] = _zz_123; + _zz_124[4] = _zz_123; + _zz_124[3] = _zz_123; + _zz_124[2] = _zz_123; + _zz_124[1] = _zz_123; + _zz_124[0] = _zz_123; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_182_ = execute_RS2; + _zz_125 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_182_ = {_zz_179_,execute_INSTRUCTION[31 : 20]}; + _zz_125 = {_zz_122,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_182_ = {_zz_181_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_125 = {_zz_124,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_182_ = _zz_51_; + _zz_125 = _zz_35; end endcase end - assign _zz_53_ = _zz_182_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_409_; + execute_SrcPlugin_addSub = _zz_389; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_50_ = execute_SrcPlugin_addSub; - assign _zz_49_ = execute_SrcPlugin_addSub; - assign _zz_48_ = execute_SrcPlugin_less; assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_183_[0] = execute_SRC1[31]; - _zz_183_[1] = execute_SRC1[30]; - _zz_183_[2] = execute_SRC1[29]; - _zz_183_[3] = execute_SRC1[28]; - _zz_183_[4] = execute_SRC1[27]; - _zz_183_[5] = execute_SRC1[26]; - _zz_183_[6] = execute_SRC1[25]; - _zz_183_[7] = execute_SRC1[24]; - _zz_183_[8] = execute_SRC1[23]; - _zz_183_[9] = execute_SRC1[22]; - _zz_183_[10] = execute_SRC1[21]; - _zz_183_[11] = execute_SRC1[20]; - _zz_183_[12] = execute_SRC1[19]; - _zz_183_[13] = execute_SRC1[18]; - _zz_183_[14] = execute_SRC1[17]; - _zz_183_[15] = execute_SRC1[16]; - _zz_183_[16] = execute_SRC1[15]; - _zz_183_[17] = execute_SRC1[14]; - _zz_183_[18] = execute_SRC1[13]; - _zz_183_[19] = execute_SRC1[12]; - _zz_183_[20] = execute_SRC1[11]; - _zz_183_[21] = execute_SRC1[10]; - _zz_183_[22] = execute_SRC1[9]; - _zz_183_[23] = execute_SRC1[8]; - _zz_183_[24] = execute_SRC1[7]; - _zz_183_[25] = execute_SRC1[6]; - _zz_183_[26] = execute_SRC1[5]; - _zz_183_[27] = execute_SRC1[4]; - _zz_183_[28] = execute_SRC1[3]; - _zz_183_[29] = execute_SRC1[2]; - _zz_183_[30] = execute_SRC1[1]; - _zz_183_[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_183_ : execute_SRC1); - assign _zz_46_ = _zz_417_; - always @ (*) begin - _zz_184_[0] = memory_SHIFT_RIGHT[31]; - _zz_184_[1] = memory_SHIFT_RIGHT[30]; - _zz_184_[2] = memory_SHIFT_RIGHT[29]; - _zz_184_[3] = memory_SHIFT_RIGHT[28]; - _zz_184_[4] = memory_SHIFT_RIGHT[27]; - _zz_184_[5] = memory_SHIFT_RIGHT[26]; - _zz_184_[6] = memory_SHIFT_RIGHT[25]; - _zz_184_[7] = memory_SHIFT_RIGHT[24]; - _zz_184_[8] = memory_SHIFT_RIGHT[23]; - _zz_184_[9] = memory_SHIFT_RIGHT[22]; - _zz_184_[10] = memory_SHIFT_RIGHT[21]; - _zz_184_[11] = memory_SHIFT_RIGHT[20]; - _zz_184_[12] = memory_SHIFT_RIGHT[19]; - _zz_184_[13] = memory_SHIFT_RIGHT[18]; - _zz_184_[14] = memory_SHIFT_RIGHT[17]; - _zz_184_[15] = memory_SHIFT_RIGHT[16]; - _zz_184_[16] = memory_SHIFT_RIGHT[15]; - _zz_184_[17] = memory_SHIFT_RIGHT[14]; - _zz_184_[18] = memory_SHIFT_RIGHT[13]; - _zz_184_[19] = memory_SHIFT_RIGHT[12]; - _zz_184_[20] = memory_SHIFT_RIGHT[11]; - _zz_184_[21] = memory_SHIFT_RIGHT[10]; - _zz_184_[22] = memory_SHIFT_RIGHT[9]; - _zz_184_[23] = memory_SHIFT_RIGHT[8]; - _zz_184_[24] = memory_SHIFT_RIGHT[7]; - _zz_184_[25] = memory_SHIFT_RIGHT[6]; - _zz_184_[26] = memory_SHIFT_RIGHT[5]; - _zz_184_[27] = memory_SHIFT_RIGHT[4]; - _zz_184_[28] = memory_SHIFT_RIGHT[3]; - _zz_184_[29] = memory_SHIFT_RIGHT[2]; - _zz_184_[30] = memory_SHIFT_RIGHT[1]; - _zz_184_[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_185_ = 1'b0; - if(_zz_321_)begin - if(_zz_322_)begin - if(_zz_191_)begin - _zz_185_ = 1'b1; - end - end - end - if(_zz_323_)begin - if(_zz_324_)begin - if(_zz_193_)begin - _zz_185_ = 1'b1; - end - end - end - if(_zz_325_)begin - if(_zz_326_)begin - if(_zz_195_)begin - _zz_185_ = 1'b1; + _zz_126[0] = execute_SRC1[31]; + _zz_126[1] = execute_SRC1[30]; + _zz_126[2] = execute_SRC1[29]; + _zz_126[3] = execute_SRC1[28]; + _zz_126[4] = execute_SRC1[27]; + _zz_126[5] = execute_SRC1[26]; + _zz_126[6] = execute_SRC1[25]; + _zz_126[7] = execute_SRC1[24]; + _zz_126[8] = execute_SRC1[23]; + _zz_126[9] = execute_SRC1[22]; + _zz_126[10] = execute_SRC1[21]; + _zz_126[11] = execute_SRC1[20]; + _zz_126[12] = execute_SRC1[19]; + _zz_126[13] = execute_SRC1[18]; + _zz_126[14] = execute_SRC1[17]; + _zz_126[15] = execute_SRC1[16]; + _zz_126[16] = execute_SRC1[15]; + _zz_126[17] = execute_SRC1[14]; + _zz_126[18] = execute_SRC1[13]; + _zz_126[19] = execute_SRC1[12]; + _zz_126[20] = execute_SRC1[11]; + _zz_126[21] = execute_SRC1[10]; + _zz_126[22] = execute_SRC1[9]; + _zz_126[23] = execute_SRC1[8]; + _zz_126[24] = execute_SRC1[7]; + _zz_126[25] = execute_SRC1[6]; + _zz_126[26] = execute_SRC1[5]; + _zz_126[27] = execute_SRC1[4]; + _zz_126[28] = execute_SRC1[3]; + _zz_126[29] = execute_SRC1[2]; + _zz_126[30] = execute_SRC1[1]; + _zz_126[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_126 : execute_SRC1); + always @ (*) begin + _zz_127[0] = memory_SHIFT_RIGHT[31]; + _zz_127[1] = memory_SHIFT_RIGHT[30]; + _zz_127[2] = memory_SHIFT_RIGHT[29]; + _zz_127[3] = memory_SHIFT_RIGHT[28]; + _zz_127[4] = memory_SHIFT_RIGHT[27]; + _zz_127[5] = memory_SHIFT_RIGHT[26]; + _zz_127[6] = memory_SHIFT_RIGHT[25]; + _zz_127[7] = memory_SHIFT_RIGHT[24]; + _zz_127[8] = memory_SHIFT_RIGHT[23]; + _zz_127[9] = memory_SHIFT_RIGHT[22]; + _zz_127[10] = memory_SHIFT_RIGHT[21]; + _zz_127[11] = memory_SHIFT_RIGHT[20]; + _zz_127[12] = memory_SHIFT_RIGHT[19]; + _zz_127[13] = memory_SHIFT_RIGHT[18]; + _zz_127[14] = memory_SHIFT_RIGHT[17]; + _zz_127[15] = memory_SHIFT_RIGHT[16]; + _zz_127[16] = memory_SHIFT_RIGHT[15]; + _zz_127[17] = memory_SHIFT_RIGHT[14]; + _zz_127[18] = memory_SHIFT_RIGHT[13]; + _zz_127[19] = memory_SHIFT_RIGHT[12]; + _zz_127[20] = memory_SHIFT_RIGHT[11]; + _zz_127[21] = memory_SHIFT_RIGHT[10]; + _zz_127[22] = memory_SHIFT_RIGHT[9]; + _zz_127[23] = memory_SHIFT_RIGHT[8]; + _zz_127[24] = memory_SHIFT_RIGHT[7]; + _zz_127[25] = memory_SHIFT_RIGHT[6]; + _zz_127[26] = memory_SHIFT_RIGHT[5]; + _zz_127[27] = memory_SHIFT_RIGHT[4]; + _zz_127[28] = memory_SHIFT_RIGHT[3]; + _zz_127[29] = memory_SHIFT_RIGHT[2]; + _zz_127[30] = memory_SHIFT_RIGHT[1]; + _zz_127[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_287)begin + if(_zz_288)begin + if(_zz_128)begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(_zz_289)begin + if(_zz_290)begin + if(_zz_130)begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(_zz_291)begin + if(_zz_292)begin + if(_zz_132)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_185_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_186_ = 1'b0; - if(_zz_321_)begin - if(_zz_322_)begin - if(_zz_192_)begin - _zz_186_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_287)begin + if(_zz_288)begin + if(_zz_129)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_323_)begin - if(_zz_324_)begin - if(_zz_194_)begin - _zz_186_ = 1'b1; + if(_zz_289)begin + if(_zz_290)begin + if(_zz_131)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_325_)begin - if(_zz_326_)begin - if(_zz_196_)begin - _zz_186_ = 1'b1; + if(_zz_291)begin + if(_zz_292)begin + if(_zz_133)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_186_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_187_ = (_zz_61_ && writeBack_arbitration_isFiring); - assign _zz_191_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_192_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_193_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_194_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_195_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_196_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_42_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_128 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_129 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_130 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_131 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_132 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_133 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_197_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_197_ == (3'b000))) begin - _zz_198_ = execute_BranchPlugin_eq; - end else if((_zz_197_ == (3'b001))) begin - _zz_198_ = (! execute_BranchPlugin_eq); - end else if((((_zz_197_ & (3'b101)) == (3'b101)))) begin - _zz_198_ = (! execute_SRC_LESS); + assign _zz_134 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_134 == 3'b000)) begin + _zz_135 = execute_BranchPlugin_eq; + end else if((_zz_134 == 3'b001)) begin + _zz_135 = (! execute_BranchPlugin_eq); + end else if((((_zz_134 & 3'b101) == 3'b101))) begin + _zz_135 = (! execute_SRC_LESS); end else begin - _zz_198_ = execute_SRC_LESS; + _zz_135 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_199_ = 1'b0; + _zz_136 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_199_ = 1'b1; + _zz_136 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_199_ = 1'b1; + _zz_136 = 1'b1; end default : begin - _zz_199_ = _zz_198_; + _zz_136 = _zz_135; end endcase end - assign _zz_41_ = _zz_199_; - assign _zz_200_ = _zz_419_[11]; - always @ (*) begin - _zz_201_[19] = _zz_200_; - _zz_201_[18] = _zz_200_; - _zz_201_[17] = _zz_200_; - _zz_201_[16] = _zz_200_; - _zz_201_[15] = _zz_200_; - _zz_201_[14] = _zz_200_; - _zz_201_[13] = _zz_200_; - _zz_201_[12] = _zz_200_; - _zz_201_[11] = _zz_200_; - _zz_201_[10] = _zz_200_; - _zz_201_[9] = _zz_200_; - _zz_201_[8] = _zz_200_; - _zz_201_[7] = _zz_200_; - _zz_201_[6] = _zz_200_; - _zz_201_[5] = _zz_200_; - _zz_201_[4] = _zz_200_; - _zz_201_[3] = _zz_200_; - _zz_201_[2] = _zz_200_; - _zz_201_[1] = _zz_200_; - _zz_201_[0] = _zz_200_; - end - - assign _zz_202_ = _zz_420_[19]; - always @ (*) begin - _zz_203_[10] = _zz_202_; - _zz_203_[9] = _zz_202_; - _zz_203_[8] = _zz_202_; - _zz_203_[7] = _zz_202_; - _zz_203_[6] = _zz_202_; - _zz_203_[5] = _zz_202_; - _zz_203_[4] = _zz_202_; - _zz_203_[3] = _zz_202_; - _zz_203_[2] = _zz_202_; - _zz_203_[1] = _zz_202_; - _zz_203_[0] = _zz_202_; - end - - assign _zz_204_ = _zz_421_[11]; - always @ (*) begin - _zz_205_[18] = _zz_204_; - _zz_205_[17] = _zz_204_; - _zz_205_[16] = _zz_204_; - _zz_205_[15] = _zz_204_; - _zz_205_[14] = _zz_204_; - _zz_205_[13] = _zz_204_; - _zz_205_[12] = _zz_204_; - _zz_205_[11] = _zz_204_; - _zz_205_[10] = _zz_204_; - _zz_205_[9] = _zz_204_; - _zz_205_[8] = _zz_204_; - _zz_205_[7] = _zz_204_; - _zz_205_[6] = _zz_204_; - _zz_205_[5] = _zz_204_; - _zz_205_[4] = _zz_204_; - _zz_205_[3] = _zz_204_; - _zz_205_[2] = _zz_204_; - _zz_205_[1] = _zz_204_; - _zz_205_[0] = _zz_204_; + assign _zz_137 = _zz_396[11]; + always @ (*) begin + _zz_138[19] = _zz_137; + _zz_138[18] = _zz_137; + _zz_138[17] = _zz_137; + _zz_138[16] = _zz_137; + _zz_138[15] = _zz_137; + _zz_138[14] = _zz_137; + _zz_138[13] = _zz_137; + _zz_138[12] = _zz_137; + _zz_138[11] = _zz_137; + _zz_138[10] = _zz_137; + _zz_138[9] = _zz_137; + _zz_138[8] = _zz_137; + _zz_138[7] = _zz_137; + _zz_138[6] = _zz_137; + _zz_138[5] = _zz_137; + _zz_138[4] = _zz_137; + _zz_138[3] = _zz_137; + _zz_138[2] = _zz_137; + _zz_138[1] = _zz_137; + _zz_138[0] = _zz_137; + end + + assign _zz_139 = _zz_397[19]; + always @ (*) begin + _zz_140[10] = _zz_139; + _zz_140[9] = _zz_139; + _zz_140[8] = _zz_139; + _zz_140[7] = _zz_139; + _zz_140[6] = _zz_139; + _zz_140[5] = _zz_139; + _zz_140[4] = _zz_139; + _zz_140[3] = _zz_139; + _zz_140[2] = _zz_139; + _zz_140[1] = _zz_139; + _zz_140[0] = _zz_139; + end + + assign _zz_141 = _zz_398[11]; + always @ (*) begin + _zz_142[18] = _zz_141; + _zz_142[17] = _zz_141; + _zz_142[16] = _zz_141; + _zz_142[15] = _zz_141; + _zz_142[14] = _zz_141; + _zz_142[13] = _zz_141; + _zz_142[12] = _zz_141; + _zz_142[11] = _zz_141; + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_206_ = (_zz_422_[1] ^ execute_RS1[1]); + _zz_143 = (_zz_399[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_206_ = _zz_423_[1]; + _zz_143 = _zz_400[1]; end default : begin - _zz_206_ = _zz_424_[1]; + _zz_143 = _zz_401[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_206_); - assign _zz_39_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_143); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -6079,167 +5137,176 @@ module VexRiscv ( endcase end - assign _zz_207_ = _zz_425_[11]; + assign _zz_144 = _zz_402[11]; always @ (*) begin - _zz_208_[19] = _zz_207_; - _zz_208_[18] = _zz_207_; - _zz_208_[17] = _zz_207_; - _zz_208_[16] = _zz_207_; - _zz_208_[15] = _zz_207_; - _zz_208_[14] = _zz_207_; - _zz_208_[13] = _zz_207_; - _zz_208_[12] = _zz_207_; - _zz_208_[11] = _zz_207_; - _zz_208_[10] = _zz_207_; - _zz_208_[9] = _zz_207_; - _zz_208_[8] = _zz_207_; - _zz_208_[7] = _zz_207_; - _zz_208_[6] = _zz_207_; - _zz_208_[5] = _zz_207_; - _zz_208_[4] = _zz_207_; - _zz_208_[3] = _zz_207_; - _zz_208_[2] = _zz_207_; - _zz_208_[1] = _zz_207_; - _zz_208_[0] = _zz_207_; + _zz_145[19] = _zz_144; + _zz_145[18] = _zz_144; + _zz_145[17] = _zz_144; + _zz_145[16] = _zz_144; + _zz_145[15] = _zz_144; + _zz_145[14] = _zz_144; + _zz_145[13] = _zz_144; + _zz_145[12] = _zz_144; + _zz_145[11] = _zz_144; + _zz_145[10] = _zz_144; + _zz_145[9] = _zz_144; + _zz_145[8] = _zz_144; + _zz_145[7] = _zz_144; + _zz_145[6] = _zz_144; + _zz_145[5] = _zz_144; + _zz_145[4] = _zz_144; + _zz_145[3] = _zz_144; + _zz_145[2] = _zz_144; + _zz_145[1] = _zz_144; + _zz_145[0] = _zz_144; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_208_,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_145,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_210_,{{{_zz_724_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_212_,{{{_zz_725_,_zz_726_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_147,{{{_zz_708,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_149,{{{_zz_709,_zz_710},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_428_}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_405}; end end endcase end - assign _zz_209_ = _zz_426_[19]; - always @ (*) begin - _zz_210_[10] = _zz_209_; - _zz_210_[9] = _zz_209_; - _zz_210_[8] = _zz_209_; - _zz_210_[7] = _zz_209_; - _zz_210_[6] = _zz_209_; - _zz_210_[5] = _zz_209_; - _zz_210_[4] = _zz_209_; - _zz_210_[3] = _zz_209_; - _zz_210_[2] = _zz_209_; - _zz_210_[1] = _zz_209_; - _zz_210_[0] = _zz_209_; - end - - assign _zz_211_ = _zz_427_[11]; - always @ (*) begin - _zz_212_[18] = _zz_211_; - _zz_212_[17] = _zz_211_; - _zz_212_[16] = _zz_211_; - _zz_212_[15] = _zz_211_; - _zz_212_[14] = _zz_211_; - _zz_212_[13] = _zz_211_; - _zz_212_[12] = _zz_211_; - _zz_212_[11] = _zz_211_; - _zz_212_[10] = _zz_211_; - _zz_212_[9] = _zz_211_; - _zz_212_[8] = _zz_211_; - _zz_212_[7] = _zz_211_; - _zz_212_[6] = _zz_211_; - _zz_212_[5] = _zz_211_; - _zz_212_[4] = _zz_211_; - _zz_212_[3] = _zz_211_; - _zz_212_[2] = _zz_211_; - _zz_212_[1] = _zz_211_; - _zz_212_[0] = _zz_211_; + assign _zz_146 = _zz_403[19]; + always @ (*) begin + _zz_147[10] = _zz_146; + _zz_147[9] = _zz_146; + _zz_147[8] = _zz_146; + _zz_147[7] = _zz_146; + _zz_147[6] = _zz_146; + _zz_147[5] = _zz_146; + _zz_147[4] = _zz_146; + _zz_147[3] = _zz_146; + _zz_147[2] = _zz_146; + _zz_147[1] = _zz_146; + _zz_147[0] = _zz_146; + end + + assign _zz_148 = _zz_404[11]; + always @ (*) begin + _zz_149[18] = _zz_148; + _zz_149[17] = _zz_148; + _zz_149[16] = _zz_148; + _zz_149[15] = _zz_148; + _zz_149[14] = _zz_148; + _zz_149[13] = _zz_148; + _zz_149[12] = _zz_148; + _zz_149[11] = _zz_148; + _zz_149[10] = _zz_148; + _zz_149[9] = _zz_148; + _zz_149[8] = _zz_148; + _zz_149[7] = _zz_148; + _zz_149[6] = _zz_148; + _zz_149[5] = _zz_148; + _zz_149[4] = _zz_148; + _zz_149[3] = _zz_148; + _zz_149[2] = _zz_148; + _zz_149[1] = _zz_148; + _zz_149[0] = _zz_148; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_38_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = _zz_213_; + CsrPlugin_privilege = _zz_150; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign CsrPlugin_misa_base = (2'b01); - assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0; assign CsrPlugin_sip_SEIP_OR = (CsrPlugin_sip_SEIP_SOFT || CsrPlugin_sip_SEIP_INPUT); - assign _zz_214_ = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); - assign _zz_215_ = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); - assign _zz_216_ = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); - assign _zz_217_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_218_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_219_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + always @ (*) begin + CsrPlugin_redoInterface_valid = 1'b0; + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + CsrPlugin_redoInterface_valid = 1'b1; + end + end + end + + assign CsrPlugin_redoInterface_payload = decode_PC; + assign _zz_151 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_152 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_153 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_154 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_155 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_156 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) - 4'b1000 : begin - if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0000 : begin + if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0001 : begin + if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0010 : begin if(((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0101 : begin - if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0100 : begin + if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b1101 : begin - if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0101 : begin + if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0100 : begin - if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0110 : begin + if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0111 : begin if(((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0001 : begin - if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b1000 : begin + if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1001 : begin if(((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1100 : begin if(((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b1111 : begin - if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); - end - end - 4'b0110 : begin - if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b1101 : begin + if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0000 : begin - if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b1111 : begin + if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end default : begin @@ -6248,11 +5315,11 @@ module VexRiscv ( end assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_220_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_221_ = _zz_429_[0]; + assign _zz_157 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_158 = _zz_406[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_305_)begin + if(_zz_273)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -6295,9 +5362,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -6321,7 +5389,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_mode = CsrPlugin_stvec_mode; @@ -6335,7 +5403,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_base = CsrPlugin_stvec_base; @@ -6349,131 +5417,118 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_36_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_35_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - always @ (*) begin - execute_CsrPlugin_inWfi = 1'b0; - if(_zz_306_)begin - execute_CsrPlugin_inWfi = 1'b1; - end - end - - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000000 : begin + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_256)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_384)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000011 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111100010001 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000010 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b111100010100 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b100111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b000100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000010 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000001 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000110000000 : begin + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110011000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000001 : begin + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000100 : begin + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000100000101 : begin + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000000 : begin + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_770)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000011 : begin + end + if(execute_CsrPlugin_csr_771)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000000 : begin + end + if(execute_CsrPlugin_csr_324)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_260)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_261)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_321)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_320)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_322)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_323)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000100000100 : begin + end + if(execute_CsrPlugin_csr_2496)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3520)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_293)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -6492,29 +5547,29 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_327_)begin + if(_zz_294)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_328_)begin + if(_zz_295)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_327_)begin - CsrPlugin_selfException_payload_code = (4'b0010); + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_294)begin + CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_328_)begin + if(_zz_295)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end 2'b01 : begin - CsrPlugin_selfException_payload_code = (4'b1001); + CsrPlugin_selfException_payload_code = 4'b1001; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -6522,145 +5577,33 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_229_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[19 : 19] = MmuPlugin_status_mxr; - execute_CsrPlugin_readData[18 : 18] = MmuPlugin_status_sum; - execute_CsrPlugin_readData[17 : 17] = MmuPlugin_status_mprv; - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - execute_CsrPlugin_readData[8 : 8] = CsrPlugin_sstatus_SPP; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sstatus_SPIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sstatus_SIE; - end - 12'b001100000011 : begin - end - 12'b111100010001 : begin - execute_CsrPlugin_readData[0 : 0] = (1'b1); - end - 12'b000101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_scause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_scause_exceptionCode; - end - 12'b111100010100 : begin - end - 12'b100111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_231_; - end - 12'b000100000000 : begin - execute_CsrPlugin_readData[19 : 19] = MmuPlugin_status_mxr; - execute_CsrPlugin_readData[18 : 18] = MmuPlugin_status_sum; - execute_CsrPlugin_readData[17 : 17] = MmuPlugin_status_mprv; - execute_CsrPlugin_readData[8 : 8] = CsrPlugin_sstatus_SPP; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sstatus_SPIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sstatus_SIE; - end - 12'b001100000010 : begin - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sip_STIP; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sip_SSIP; - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sip_SEIP_OR; - end - 12'b001100000101 : begin - end - 12'b000110000000 : begin - execute_CsrPlugin_readData[31 : 31] = MmuPlugin_satp_mode; - execute_CsrPlugin_readData[19 : 0] = MmuPlugin_satp_ppn; - end - 12'b110011000000 : begin - execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); - execute_CsrPlugin_readData[25 : 20] = (6'b100000); - end - 12'b000101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_sepc; - end - 12'b111100010011 : begin - execute_CsrPlugin_readData[1 : 0] = (2'b11); - end - 12'b000101000100 : begin - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sip_STIP; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sip_SSIP; - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sip_SEIP_OR; - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b000100000101 : begin - execute_CsrPlugin_readData[31 : 2] = CsrPlugin_stvec_base; - execute_CsrPlugin_readData[1 : 0] = CsrPlugin_stvec_mode; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_230_; - end - 12'b001101000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sie_SEIE; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sie_STIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sie_SSIE; - end - 12'b111100010010 : begin - execute_CsrPlugin_readData[1 : 0] = (2'b10); - end - 12'b000101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_stval; - end - 12'b110111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_232_; - end - 12'b000101000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_sscratch; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - 12'b000100000100 : begin - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sie_SEIE; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sie_STIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sie_SSIE; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_293)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_293)begin + execute_CsrPlugin_readInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); always @ (*) begin execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - case(execute_CsrPlugin_csrAddress) - 12'b001101000100 : begin - execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; - end - 12'b000101000100 : begin - execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; - end - default : begin - end - endcase + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; + end + if(execute_CsrPlugin_csr_324)begin + execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; + end end always @ (*) begin - case(_zz_356_) + case(_zz_323) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -6671,10 +5614,10 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_MulPlugin_a = execute_SRC1; - assign execute_MulPlugin_b = execute_SRC2; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_329_) + case(_zz_296) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -6688,7 +5631,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_329_) + case(_zz_296) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -6707,16 +5650,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign _zz_32_ = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign _zz_31_ = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); - assign _zz_30_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); - assign _zz_29_ = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); - assign _zz_28_ = ($signed(_zz_431_) + $signed(_zz_439_)); - assign writeBack_MulPlugin_result = ($signed(_zz_440_) + $signed(_zz_441_)); + assign writeBack_MulPlugin_result = ($signed(_zz_408) + $signed(_zz_409)); + assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_300_)begin - if(_zz_309_)begin + if(_zz_268)begin + if(_zz_297)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -6724,46 +5663,46 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_330_)begin + if(_zz_298)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end - assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == (6'b100001)); + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); always @ (*) begin if(memory_DivPlugin_div_counter_willOverflow)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_445_); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_413); end if(memory_DivPlugin_div_counter_willClear)begin - memory_DivPlugin_div_counter_valueNext = (6'b000000); + memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_222_ = memory_DivPlugin_rs1[31 : 0]; - assign _zz_223_ = {memory_DivPlugin_accumulator[31 : 0],_zz_222_[31]}; - assign _zz_224_ = (_zz_223_ - _zz_446_); - assign _zz_225_ = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_226_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_227_ = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_159 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_159[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_414); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_415 : _zz_416); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_417[31:0]; + assign _zz_160 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_161 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_162 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_228_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_228_[31 : 0] = execute_RS1; + _zz_163[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_163[31 : 0] = execute_RS1; end - assign _zz_230_ = (_zz_229_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_230_ != (32'b00000000000000000000000000000000)); - assign _zz_232_ = (_zz_231_ & externalInterruptArray_regNext); - assign externalInterruptS = (_zz_232_ != (32'b00000000000000000000000000000000)); + assign _zz_165 = (_zz_164 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_165 != 32'h0); + assign _zz_167 = (_zz_166 & externalInterruptArray_regNext); + assign externalInterruptS = (_zz_167 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_331_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_299) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end @@ -6776,7 +5715,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_233_))begin + if((! _zz_168))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -6788,10 +5727,8 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_331_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_299) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; end @@ -6803,39 +5740,39 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign _zz_27_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_26_ = decode_ENV_CTRL; - assign _zz_23_ = execute_ENV_CTRL; - assign _zz_21_ = memory_ENV_CTRL; - assign _zz_24_ = _zz_80_; - assign _zz_34_ = decode_to_execute_ENV_CTRL; - assign _zz_33_ = execute_to_memory_ENV_CTRL; - assign _zz_37_ = memory_to_writeBack_ENV_CTRL; - assign _zz_19_ = decode_BRANCH_CTRL; - assign _zz_101_ = _zz_85_; - assign _zz_40_ = decode_to_execute_BRANCH_CTRL; - assign _zz_17_ = decode_SRC2_CTRL; - assign _zz_15_ = _zz_90_; - assign _zz_52_ = decode_to_execute_SRC2_CTRL; - assign _zz_14_ = decode_ALU_BITWISE_CTRL; - assign _zz_12_ = _zz_65_; - assign _zz_59_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_11_ = decode_ALU_CTRL; - assign _zz_9_ = _zz_87_; - assign _zz_57_ = decode_to_execute_ALU_CTRL; - assign _zz_8_ = decode_SHIFT_CTRL; - assign _zz_5_ = execute_SHIFT_CTRL; - assign _zz_6_ = _zz_82_; - assign _zz_47_ = decode_to_execute_SHIFT_CTRL; - assign _zz_45_ = execute_to_memory_SHIFT_CTRL; - assign _zz_3_ = decode_SRC1_CTRL; - assign _zz_1_ = _zz_76_; - assign _zz_54_ = decode_to_execute_SRC1_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign _zz_26 = decode_SRC1_CTRL; + assign _zz_24 = _zz_49; + assign _zz_37 = decode_to_execute_SRC1_CTRL; + assign _zz_23 = decode_ALU_CTRL; + assign _zz_21 = _zz_48; + assign _zz_38 = decode_to_execute_ALU_CTRL; + assign _zz_20 = decode_SRC2_CTRL; + assign _zz_18 = _zz_47; + assign _zz_36 = decode_to_execute_SRC2_CTRL; + assign _zz_17 = decode_ALU_BITWISE_CTRL; + assign _zz_15 = _zz_46; + assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_14 = decode_SHIFT_CTRL; + assign _zz_11 = execute_SHIFT_CTRL; + assign _zz_12 = _zz_45; + assign _zz_34 = decode_to_execute_SHIFT_CTRL; + assign _zz_33 = execute_to_memory_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_52 = _zz_44; + assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_43; + assign _zz_28 = decode_to_execute_ENV_CTRL; + assign _zz_27 = execute_to_memory_ENV_CTRL; + assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -6854,15 +5791,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_234_) - 3'b000 : begin - end - 3'b001 : begin - end - 3'b010 : begin - end - 3'b011 : begin - end + case(_zz_169) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -6871,66 +5800,268 @@ module VexRiscv ( endcase end - assign iBusWishbone_ADR = {_zz_504_,_zz_235_}; - assign iBusWishbone_CTI = ((_zz_235_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); + always @ (*) begin + _zz_170 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_170[12 : 0] = 13'h1000; + _zz_170[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_171 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_171[19 : 19] = MmuPlugin_status_mxr; + _zz_171[18 : 18] = MmuPlugin_status_sum; + _zz_171[17 : 17] = MmuPlugin_status_mprv; + _zz_171[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_171[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_171[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_171[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_171[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_171[1 : 1] = CsrPlugin_sstatus_SIE; + end + end + + always @ (*) begin + _zz_172 = 32'h0; + if(execute_CsrPlugin_csr_256)begin + _zz_172[19 : 19] = MmuPlugin_status_mxr; + _zz_172[18 : 18] = MmuPlugin_status_sum; + _zz_172[17 : 17] = MmuPlugin_status_mprv; + _zz_172[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_172[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_172[1 : 1] = CsrPlugin_sstatus_SIE; + end + end + + always @ (*) begin + _zz_173 = 32'h0; + if(execute_CsrPlugin_csr_384)begin + _zz_173[31 : 31] = MmuPlugin_satp_mode; + _zz_173[30 : 22] = MmuPlugin_satp_asid; + _zz_173[19 : 0] = MmuPlugin_satp_ppn; + end + end + + always @ (*) begin + _zz_174 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_174[0 : 0] = 1'b1; + end + end + + always @ (*) begin + _zz_175 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_175[1 : 0] = 2'b10; + end + end + + always @ (*) begin + _zz_176 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_176[1 : 0] = 2'b11; + end + end + + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_177[11 : 11] = CsrPlugin_mip_MEIP; + _zz_177[7 : 7] = CsrPlugin_mip_MTIP; + _zz_177[3 : 3] = CsrPlugin_mip_MSIP; + _zz_177[5 : 5] = CsrPlugin_sip_STIP; + _zz_177[1 : 1] = CsrPlugin_sip_SSIP; + _zz_177[9 : 9] = CsrPlugin_sip_SEIP_OR; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_178[11 : 11] = CsrPlugin_mie_MEIE; + _zz_178[7 : 7] = CsrPlugin_mie_MTIE; + _zz_178[3 : 3] = CsrPlugin_mie_MSIE; + _zz_178[9 : 9] = CsrPlugin_sie_SEIE; + _zz_178[5 : 5] = CsrPlugin_sie_STIE; + _zz_178[1 : 1] = CsrPlugin_sie_SSIE; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_179[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_180[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_181[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_181[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_182[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_324)begin + _zz_183[5 : 5] = CsrPlugin_sip_STIP; + _zz_183[1 : 1] = CsrPlugin_sip_SSIP; + _zz_183[9 : 9] = CsrPlugin_sip_SEIP_OR; + end + end + + always @ (*) begin + _zz_184 = 32'h0; + if(execute_CsrPlugin_csr_260)begin + _zz_184[9 : 9] = CsrPlugin_sie_SEIE; + _zz_184[5 : 5] = CsrPlugin_sie_STIE; + _zz_184[1 : 1] = CsrPlugin_sie_SSIE; + end + end + + always @ (*) begin + _zz_185 = 32'h0; + if(execute_CsrPlugin_csr_261)begin + _zz_185[31 : 2] = CsrPlugin_stvec_base; + _zz_185[1 : 0] = CsrPlugin_stvec_mode; + end + end + + always @ (*) begin + _zz_186 = 32'h0; + if(execute_CsrPlugin_csr_321)begin + _zz_186[31 : 0] = CsrPlugin_sepc; + end + end + + always @ (*) begin + _zz_187 = 32'h0; + if(execute_CsrPlugin_csr_320)begin + _zz_187[31 : 0] = CsrPlugin_sscratch; + end + end + + always @ (*) begin + _zz_188 = 32'h0; + if(execute_CsrPlugin_csr_322)begin + _zz_188[31 : 31] = CsrPlugin_scause_interrupt; + _zz_188[3 : 0] = CsrPlugin_scause_exceptionCode; + end + end + + always @ (*) begin + _zz_189 = 32'h0; + if(execute_CsrPlugin_csr_323)begin + _zz_189[31 : 0] = CsrPlugin_stval; + end + end + + always @ (*) begin + _zz_190 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_190[31 : 0] = _zz_164; + end + end + + always @ (*) begin + _zz_191 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_191[31 : 0] = _zz_165; + end + end + + always @ (*) begin + _zz_192 = 32'h0; + if(execute_CsrPlugin_csr_2496)begin + _zz_192[31 : 0] = _zz_166; + end + end + + always @ (*) begin + _zz_193 = 32'h0; + if(execute_CsrPlugin_csr_3520)begin + _zz_193[31 : 0] = _zz_167; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_170 | _zz_171) | (_zz_172 | _zz_173)) | ((_zz_174 | _zz_175) | (_zz_176 | _zz_711))) | (((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_181 | _zz_182) | (_zz_183 | _zz_184)))) | ((((_zz_185 | _zz_186) | (_zz_187 | _zz_188)) | ((_zz_189 | _zz_190) | (_zz_191 | _zz_192))) | _zz_193)); + assign iBusWishbone_ADR = {_zz_472,_zz_194}; + assign iBusWishbone_CTI = ((_zz_194 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_332_)begin + if(_zz_300)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_332_)begin + if(_zz_300)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_236_; + assign iBus_rsp_valid = _zz_195; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_242_ = (dBus_cmd_payload_length != (3'b000)); - assign _zz_238_ = dBus_cmd_valid; - assign _zz_240_ = dBus_cmd_payload_wr; - assign _zz_241_ = (_zz_237_ == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_239_ && (_zz_240_ || _zz_241_)); - assign dBusWishbone_ADR = ((_zz_242_ ? {{dBus_cmd_payload_address[31 : 5],_zz_237_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); - assign dBusWishbone_CTI = (_zz_242_ ? (_zz_241_ ? (3'b111) : (3'b010)) : (3'b000)); - assign dBusWishbone_BTE = (2'b00); - assign dBusWishbone_SEL = (_zz_240_ ? dBus_cmd_payload_mask : (4'b1111)); - assign dBusWishbone_WE = _zz_240_; + assign _zz_201 = (dBus_cmd_payload_length != 3'b000); + assign _zz_197 = dBus_cmd_valid; + assign _zz_199 = dBus_cmd_payload_wr; + assign _zz_200 = (_zz_196 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_198 && (_zz_199 || _zz_200)); + assign dBusWishbone_ADR = ((_zz_201 ? {{dBus_cmd_payload_address[31 : 5],_zz_196},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_201 ? (_zz_200 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_199 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_199; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_239_ = (_zz_238_ && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_238_; - assign dBusWishbone_STB = _zz_238_; - assign dBus_rsp_valid = _zz_243_; + assign _zz_198 = (_zz_197 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_197; + assign dBusWishbone_STB = _zz_197; + assign dBus_rsp_valid = _zz_202; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_119_ <= 1'b0; - _zz_121_ <= 1'b0; + _zz_68 <= 1'b0; + _zz_70 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_134_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_135_ <= 1'b0; - _zz_142_ <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_149_; - DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); + IBusCachedPlugin_rspCounter <= _zz_83; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_84; + DBusCachedPlugin_rspCounter <= 32'h0; MmuPlugin_status_sum <= 1'b0; MmuPlugin_status_mxr <= 1'b0; MmuPlugin_status_mprv <= 1'b0; @@ -6939,19 +6070,20 @@ module VexRiscv ( MmuPlugin_ports_0_cache_1_valid <= 1'b0; MmuPlugin_ports_0_cache_2_valid <= 1'b0; MmuPlugin_ports_0_cache_3_valid <= 1'b0; - MmuPlugin_ports_0_entryToReplace_value <= (2'b00); + MmuPlugin_ports_0_entryToReplace_value <= 2'b00; MmuPlugin_ports_1_cache_0_valid <= 1'b0; MmuPlugin_ports_1_cache_1_valid <= 1'b0; MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; - MmuPlugin_ports_1_entryToReplace_value <= (2'b00); - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE; - _zz_175_ <= 1'b1; - _zz_188_ <= 1'b0; - _zz_213_ <= (2'b11); + MmuPlugin_ports_1_entryToReplace_value <= 2'b00; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; + _zz_118 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_150 <= 2'b11; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -6972,7 +6104,7 @@ module VexRiscv ( CsrPlugin_mideleg_SS <= 1'b0; CsrPlugin_sstatus_SIE <= 1'b0; CsrPlugin_sstatus_SPIE <= 1'b0; - CsrPlugin_sstatus_SPP <= (1'b1); + CsrPlugin_sstatus_SPP <= 1'b1; CsrPlugin_sip_SEIP_SOFT <= 1'b0; CsrPlugin_sip_STIP <= 1'b0; CsrPlugin_sip_SSIP <= 1'b0; @@ -6985,26 +6117,33 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_DivPlugin_div_counter_value <= (6'b000000); - _zz_229_ <= (32'b00000000000000000000000000000000); - _zz_231_ <= (32'b00000000000000000000000000000000); + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_164 <= 32'h0; + _zz_166 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_234_ <= (3'b000); + _zz_169 <= 3'b000; execute_to_memory_IS_DBUS_SHARING <= 1'b0; memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_235_ <= (3'b000); - _zz_236_ <= 1'b0; - _zz_237_ <= (3'b000); - _zz_243_ <= 1'b0; + _zz_194 <= 3'b000; + _zz_195 <= 1'b0; + _zz_196 <= 3'b000; + _zz_202 <= 1'b0; end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin @@ -7013,83 +6152,77 @@ module VexRiscv ( if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_119_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_68 <= 1'b0; end - if(_zz_117_)begin - _zz_119_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if(_zz_66)begin + _zz_68 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_121_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_70 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_121_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_70 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_135_ <= 1'b0; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_333_)begin - _zz_135_ <= dataCache_1__io_mem_cmd_valid; + if(_zz_301)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_142_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end if(dBus_rsp_valid)begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; if(contextSwitching)begin @@ -7121,71 +6254,69 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_valid <= 1'b0; end end - case(MmuPlugin_shared_state_1_) + MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; + case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_334_)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; - end - if(_zz_335_)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + if(_zz_302)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; end end `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; end end `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin - if(MmuPlugin_dBusAccess_rsp_valid)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; end - if(MmuPlugin_dBusAccess_rsp_payload_redo)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; end end end `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; end end default : begin - if(MmuPlugin_dBusAccess_rsp_valid)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE; - if(MmuPlugin_dBusAccess_rsp_payload_redo)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; end end end endcase - if(_zz_318_)begin - if(_zz_319_)begin - if(_zz_336_)begin + if(_zz_284)begin + if(_zz_285)begin + if(_zz_303)begin MmuPlugin_ports_0_cache_0_valid <= 1'b1; end - if(_zz_337_)begin + if(_zz_304)begin MmuPlugin_ports_0_cache_1_valid <= 1'b1; end - if(_zz_338_)begin + if(_zz_305)begin MmuPlugin_ports_0_cache_2_valid <= 1'b1; end - if(_zz_339_)begin + if(_zz_306)begin MmuPlugin_ports_0_cache_3_valid <= 1'b1; end end - if(_zz_320_)begin - if(_zz_340_)begin + if(_zz_286)begin + if(_zz_307)begin MmuPlugin_ports_1_cache_0_valid <= 1'b1; end - if(_zz_341_)begin + if(_zz_308)begin MmuPlugin_ports_1_cache_1_valid <= 1'b1; end - if(_zz_342_)begin + if(_zz_309)begin MmuPlugin_ports_1_cache_2_valid <= 1'b1; end - if(_zz_343_)begin + if(_zz_310)begin MmuPlugin_ports_1_cache_3_valid <= 1'b1; end end @@ -7200,8 +6331,8 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - _zz_175_ <= 1'b0; - _zz_188_ <= _zz_187_; + _zz_118 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -7223,41 +6354,60 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_344_)begin - if(_zz_345_)begin + if(_zz_311)begin + if(_zz_312)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_346_)begin + if(_zz_313)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_347_)begin + if(_zz_314)begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(_zz_348_)begin - if(_zz_349_)begin + if(_zz_315)begin + if(_zz_316)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_350_)begin + if(_zz_317)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_351_)begin + if(_zz_318)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_352_)begin + if(_zz_319)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_353_)begin + if(_zz_320)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_354_)begin + if(_zz_321)begin CsrPlugin_interrupt_valid <= 1'b1; end end CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_310_)begin - _zz_213_ <= CsrPlugin_targetPrivilege; + if(_zz_277)begin + _zz_150 <= CsrPlugin_targetPrivilege; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_sstatus_SIE <= 1'b0; @@ -7273,38 +6423,32 @@ module VexRiscv ( end endcase end - if(_zz_311_)begin - case(_zz_313_) + if(_zz_278)begin + case(_zz_280) 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; - _zz_213_ <= CsrPlugin_mstatus_MPP; + _zz_150 <= CsrPlugin_mstatus_MPP; end 2'b01 : begin - CsrPlugin_sstatus_SPP <= (1'b0); + CsrPlugin_sstatus_SPP <= 1'b0; CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; CsrPlugin_sstatus_SPIE <= 1'b1; - _zz_213_ <= {(1'b0),CsrPlugin_sstatus_SPP}; + _zz_150 <= {1'b0,CsrPlugin_sstatus_SPP}; end default : begin end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_219_,{_zz_218_,{_zz_217_,{_zz_216_,{_zz_215_,_zz_214_}}}}} != (6'b000000)); + execute_CsrPlugin_wfiWake <= (({_zz_156,{_zz_155,{_zz_154,{_zz_153,{_zz_152,_zz_151}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end if((! memory_arbitration_isStuck))begin execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_44_; - end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -7323,25 +6467,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_234_) + case(_zz_169) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_234_ <= (3'b001); + _zz_169 <= 3'b001; end end 3'b001 : begin - _zz_234_ <= (3'b010); + _zz_169 <= 3'b010; end 3'b010 : begin - _zz_234_ <= (3'b011); + _zz_169 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_234_ <= (3'b100); + _zz_169 <= 3'b100; end end 3'b100 : begin - _zz_234_ <= (3'b000); + _zz_169 <= 3'b000; end default : begin end @@ -7349,179 +6493,156 @@ module VexRiscv ( if(MmuPlugin_dBusAccess_rsp_valid)begin memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_229_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_459_[0]; - MmuPlugin_status_sum <= _zz_460_[0]; - MmuPlugin_status_mprv <= _zz_461_[0]; - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_462_[0]; - CsrPlugin_mstatus_MIE <= _zz_463_[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_464_[0]; - CsrPlugin_sstatus_SIE <= _zz_465_[0]; - end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_status_mxr <= _zz_427[0]; + MmuPlugin_status_sum <= _zz_428[0]; + MmuPlugin_status_mprv <= _zz_429[0]; + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_430[0]; + CsrPlugin_mstatus_MIE <= _zz_431[0]; + CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; + CsrPlugin_sstatus_SPIE <= _zz_432[0]; + CsrPlugin_sstatus_SIE <= _zz_433[0]; + end + end + if(execute_CsrPlugin_csr_256)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_status_mxr <= _zz_434[0]; + MmuPlugin_status_sum <= _zz_435[0]; + MmuPlugin_status_mprv <= _zz_436[0]; + CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; + CsrPlugin_sstatus_SPIE <= _zz_437[0]; + CsrPlugin_sstatus_SIE <= _zz_438[0]; end - 12'b001100000011 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mideleg_SE <= _zz_466_[0]; - CsrPlugin_mideleg_ST <= _zz_467_[0]; - CsrPlugin_mideleg_SS <= _zz_468_[0]; - end + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - 12'b111100010001 : begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_mode <= _zz_439[0]; end - 12'b000101000010 : begin + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sip_STIP <= _zz_441[0]; + CsrPlugin_sip_SSIP <= _zz_442[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_443[0]; end - 12'b111100010100 : begin - end - 12'b100111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_231_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b000100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_470_[0]; - MmuPlugin_status_sum <= _zz_471_[0]; - MmuPlugin_status_mprv <= _zz_472_[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_473_[0]; - CsrPlugin_sstatus_SIE <= _zz_474_[0]; - end - end - 12'b001100000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_medeleg_EU <= _zz_475_[0]; - CsrPlugin_medeleg_II <= _zz_476_[0]; - CsrPlugin_medeleg_LAF <= _zz_477_[0]; - CsrPlugin_medeleg_LPF <= _zz_478_[0]; - CsrPlugin_medeleg_LAM <= _zz_479_[0]; - CsrPlugin_medeleg_SAF <= _zz_480_[0]; - CsrPlugin_medeleg_IAF <= _zz_481_[0]; - CsrPlugin_medeleg_ES <= _zz_482_[0]; - CsrPlugin_medeleg_IPF <= _zz_483_[0]; - CsrPlugin_medeleg_SPF <= _zz_484_[0]; - CsrPlugin_medeleg_SAM <= _zz_485_[0]; - CsrPlugin_medeleg_IAM <= _zz_486_[0]; - end - end - 12'b001101000001 : begin - end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_488_[0]; - CsrPlugin_sip_SSIP <= _zz_489_[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_490_[0]; - end - end - 12'b001100000101 : begin - end - 12'b000110000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_mode <= _zz_491_[0]; - end - end - 12'b110011000000 : begin - end - 12'b000101000001 : begin - end - 12'b111100010011 : begin - end - 12'b000101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_492_[0]; - CsrPlugin_sip_SSIP <= _zz_493_[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_494_[0]; - end - end - 12'b001101000011 : begin - end - 12'b000100000101 : begin - end - 12'b111111000000 : begin - end - 12'b001101000000 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_495_[0]; - CsrPlugin_mie_MTIE <= _zz_496_[0]; - CsrPlugin_mie_MSIE <= _zz_497_[0]; - CsrPlugin_sie_SEIE <= _zz_498_[0]; - CsrPlugin_sie_STIE <= _zz_499_[0]; - CsrPlugin_sie_SSIE <= _zz_500_[0]; - end - end - 12'b111100010010 : begin - end - 12'b000101000011 : begin + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_444[0]; + CsrPlugin_mie_MTIE <= _zz_445[0]; + CsrPlugin_mie_MSIE <= _zz_446[0]; + CsrPlugin_sie_SEIE <= _zz_447[0]; + CsrPlugin_sie_STIE <= _zz_448[0]; + CsrPlugin_sie_SSIE <= _zz_449[0]; end - 12'b110111000000 : begin + end + if(execute_CsrPlugin_csr_770)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_medeleg_IAM <= _zz_450[0]; + CsrPlugin_medeleg_IAF <= _zz_451[0]; + CsrPlugin_medeleg_II <= _zz_452[0]; + CsrPlugin_medeleg_LAM <= _zz_453[0]; + CsrPlugin_medeleg_LAF <= _zz_454[0]; + CsrPlugin_medeleg_SAM <= _zz_455[0]; + CsrPlugin_medeleg_SAF <= _zz_456[0]; + CsrPlugin_medeleg_EU <= _zz_457[0]; + CsrPlugin_medeleg_ES <= _zz_458[0]; + CsrPlugin_medeleg_IPF <= _zz_459[0]; + CsrPlugin_medeleg_LPF <= _zz_460[0]; + CsrPlugin_medeleg_SPF <= _zz_461[0]; + end + end + if(execute_CsrPlugin_csr_771)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mideleg_SE <= _zz_462[0]; + CsrPlugin_mideleg_ST <= _zz_463[0]; + CsrPlugin_mideleg_SS <= _zz_464[0]; end - 12'b000101000000 : begin + end + if(execute_CsrPlugin_csr_324)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sip_STIP <= _zz_465[0]; + CsrPlugin_sip_SSIP <= _zz_466[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_467[0]; end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_260)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sie_SEIE <= _zz_468[0]; + CsrPlugin_sie_STIE <= _zz_469[0]; + CsrPlugin_sie_SSIE <= _zz_470[0]; end - 12'b000100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sie_SEIE <= _zz_501_[0]; - CsrPlugin_sie_STIE <= _zz_502_[0]; - CsrPlugin_sie_SSIE <= _zz_503_[0]; - end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; end - default : begin + end + if(execute_CsrPlugin_csr_2496)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; end - endcase - if(_zz_332_)begin + end + if(_zz_300)begin if(iBusWishbone_ACK)begin - _zz_235_ <= (_zz_235_ + (3'b001)); + _zz_194 <= (_zz_194 + 3'b001); end end - _zz_236_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_238_ && _zz_239_))begin - _zz_237_ <= (_zz_237_ + (3'b001)); - if(_zz_241_)begin - _zz_237_ <= (3'b000); + _zz_195 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_197 && _zz_198))begin + _zz_196 <= (_zz_196 + 3'b001); + if(_zz_200)begin + _zz_196 <= 3'b000; end end - _zz_243_ <= ((_zz_238_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_202 <= ((_zz_197 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_122_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_71 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_333_)begin - _zz_136_ <= dataCache_1__io_mem_cmd_payload_wr; - _zz_137_ <= dataCache_1__io_mem_cmd_payload_address; - _zz_138_ <= dataCache_1__io_mem_cmd_payload_data; - _zz_139_ <= dataCache_1__io_mem_cmd_payload_mask; - _zz_140_ <= dataCache_1__io_mem_cmd_payload_length; - _zz_141_ <= dataCache_1__io_mem_cmd_payload_last; - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_143_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - _zz_144_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; - _zz_145_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; - _zz_146_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - _zz_147_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; - _zz_148_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; - end - if((MmuPlugin_dBusAccess_rsp_valid && (! MmuPlugin_dBusAccess_rsp_payload_redo)))begin + if(_zz_301)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; + MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; + MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; + if((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)))begin MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; @@ -7534,17 +6655,12 @@ module VexRiscv ( MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; end - case(MmuPlugin_shared_state_1_) + case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_334_)begin - MmuPlugin_shared_vpn_1 <= IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22]; - MmuPlugin_shared_vpn_0 <= IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]; - MmuPlugin_shared_portId <= (1'b0); - end - if(_zz_335_)begin - MmuPlugin_shared_vpn_1 <= DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22]; - MmuPlugin_shared_vpn_0 <= DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]; - MmuPlugin_shared_portId <= (1'b1); + if(_zz_302)begin + MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; + MmuPlugin_shared_vpn_1 <= _zz_103[31 : 22]; + MmuPlugin_shared_vpn_0 <= _zz_103[21 : 12]; end end `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin @@ -7556,10 +6672,10 @@ module VexRiscv ( default : begin end endcase - if(_zz_318_)begin - if(_zz_319_)begin - if(_zz_336_)begin - MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); + if(_zz_284)begin + if(_zz_285)begin + if(_zz_303)begin + MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -7568,10 +6684,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_337_)begin - MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); + if(_zz_304)begin + MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -7580,10 +6696,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_338_)begin - MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); + if(_zz_305)begin + MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -7592,10 +6708,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_339_)begin - MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); + if(_zz_306)begin + MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -7604,12 +6720,12 @@ module VexRiscv ( MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end end - if(_zz_320_)begin - if(_zz_340_)begin - MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); + if(_zz_286)begin + if(_zz_307)begin + MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -7618,10 +6734,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_341_)begin - MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); + if(_zz_308)begin + MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -7630,10 +6746,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_342_)begin - MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); + if(_zz_309)begin + MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -7642,10 +6758,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_343_)begin - MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); + if(_zz_310)begin + MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -7654,486 +6770,1806 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end end end - if(_zz_187_)begin - _zz_189_ <= _zz_60_[11 : 7]; - _zz_190_ <= _zz_95_; - end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_sip_SEIP_INPUT <= externalInterruptS; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_273)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_158 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_158 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_311)begin + if(_zz_312)begin + CsrPlugin_interrupt_code <= 4'b0101; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + if(_zz_313)begin + CsrPlugin_interrupt_code <= 4'b0001; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + if(_zz_314)begin + CsrPlugin_interrupt_code <= 4'b1001; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + end + if(_zz_315)begin + if(_zz_316)begin + CsrPlugin_interrupt_code <= 4'b0101; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_317)begin + CsrPlugin_interrupt_code <= 4'b0001; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_318)begin + CsrPlugin_interrupt_code <= 4'b1001; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_319)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_320)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_321)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_277)begin + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_sepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_268)begin + if(_zz_297)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_418[31:0]; + end + end + end + if(_zz_298)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_162 ? (~ _zz_163) : _zz_163) + _zz_424); + memory_DivPlugin_rs2 <= ((_zz_161 ? (~ execute_RS2) : execute_RS2) + _zz_426); + memory_DivPlugin_div_needRevert <= ((_zz_162 ^ (_zz_161 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_35; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_55; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_53; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_54; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_13; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_10; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_770 <= (decode_INSTRUCTION[31 : 20] == 12'h302); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_771 <= (decode_INSTRUCTION[31 : 20] == 12'h303); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_324 <= (decode_INSTRUCTION[31 : 20] == 12'h144); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_260 <= (decode_INSTRUCTION[31 : 20] == 12'h104); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_261 <= (decode_INSTRUCTION[31 : 20] == 12'h105); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_321 <= (decode_INSTRUCTION[31 : 20] == 12'h141); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_320 <= (decode_INSTRUCTION[31 : 20] == 12'h140); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_322 <= (decode_INSTRUCTION[31 : 20] == 12'h142); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_323 <= (decode_INSTRUCTION[31 : 20] == 12'h143); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if(_zz_305_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_221_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_221_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2496 <= (decode_INSTRUCTION[31 : 20] == 12'h9c0); end - if(BranchPlugin_branchExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3520 <= (decode_INSTRUCTION[31 : 20] == 12'hdc0); end - if(DBusCachedPlugin_exceptionBus_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_asid <= execute_CsrPlugin_writeData[30 : 22]; + MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; + end end - if(_zz_344_)begin - if(_zz_345_)begin - CsrPlugin_interrupt_code <= (4'b0101); - CsrPlugin_interrupt_targetPrivilege <= (2'b01); + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_440[0]; end - if(_zz_346_)begin - CsrPlugin_interrupt_code <= (4'b0001); - CsrPlugin_interrupt_targetPrivilege <= (2'b01); + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - if(_zz_347_)begin - CsrPlugin_interrupt_code <= (4'b1001); - CsrPlugin_interrupt_targetPrivilege <= (2'b01); + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_348_)begin - if(_zz_349_)begin - CsrPlugin_interrupt_code <= (4'b0101); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; end - if(_zz_350_)begin - CsrPlugin_interrupt_code <= (4'b0001); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_261)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - if(_zz_351_)begin - CsrPlugin_interrupt_code <= (4'b1001); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_321)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0]; end - if(_zz_352_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_320)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0]; end - if(_zz_353_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_322)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_scause_interrupt <= _zz_471[0]; + CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end - if(_zz_354_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_323)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_310_)begin - case(CsrPlugin_targetPrivilege) - 2'b01 : begin - CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_sepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_50; + end + _zz_168 <= debug_bus_cmd_payload_address[2]; + if(_zz_275)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_299) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end end - end - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + default : begin end + endcase + end + if(_zz_275)begin + if(_zz_276)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; end - default : begin + end + if(_zz_279)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; end - endcase + end end - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_done <= 1'b1; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_isLrsc, + input io_cpu_execute_args_isAmo, + input io_cpu_execute_args_amoCtrl_swap, + input [2:0] io_cpu_execute_args_amoCtrl_alu, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_memory_mmuRsp_ways_0_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_0_physical, + input io_cpu_memory_mmuRsp_ways_1_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_1_physical, + input io_cpu_memory_mmuRsp_ways_2_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_2_physical, + input io_cpu_memory_mmuRsp_ways_3_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_3_physical, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire _zz_19; + wire _zz_20; + wire _zz_21; + wire _zz_22; + wire [2:0] _zz_23; + wire [0:0] _zz_24; + wire [0:0] _zz_25; + wire [9:0] _zz_26; + wire [9:0] _zz_27; + wire [31:0] _zz_28; + wire [31:0] _zz_29; + wire [31:0] _zz_30; + wire [31:0] _zz_31; + wire [1:0] _zz_32; + wire [31:0] _zz_33; + wire [1:0] _zz_34; + wire [1:0] _zz_35; + wire [0:0] _zz_36; + wire [0:0] _zz_37; + wire [0:0] _zz_38; + wire [2:0] _zz_39; + wire [1:0] _zz_40; + wire [21:0] _zz_41; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_isLrsc; + reg stageA_request_isAmo; + reg stageA_request_amoCtrl_swap; + reg [2:0] stageA_request_amoCtrl_alu; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_isLrsc; + reg stageB_request_isAmo; + reg stageB_request_amoCtrl_swap; + reg [2:0] stageB_request_amoCtrl_alu; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_mmuRsp_ways_0_sel; + reg [31:0] stageB_mmuRsp_ways_0_physical; + reg stageB_mmuRsp_ways_1_sel; + reg [31:0] stageB_mmuRsp_ways_1_physical; + reg stageB_mmuRsp_ways_2_sel; + reg [31:0] stageB_mmuRsp_ways_2_physical; + reg stageB_mmuRsp_ways_3_sel; + reg [31:0] stageB_mmuRsp_ways_3_physical; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + reg stageB_lrSc_reserved; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + reg [31:0] stageB_requestDataBypass; + wire stageB_amo_compare; + wire stageB_amo_unsigned; + wire [31:0] stageB_amo_addSub; + wire stageB_amo_less; + wire stageB_amo_selectRf; + reg [31:0] stageB_amo_result; + reg [31:0] stageB_amo_resultReg; + reg stageB_amo_internal_resultRegValid; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_42; + reg [7:0] _zz_43; + reg [7:0] _zz_44; + reg [7:0] _zz_45; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_15 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); + assign _zz_16 = (! stageB_amo_internal_resultRegValid); + assign _zz_17 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign _zz_18 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_19 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign _zz_20 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign _zz_21 = (! stageB_flusher_hold); + assign _zz_22 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_23 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); + assign _zz_24 = _zz_4[0 : 0]; + assign _zz_25 = _zz_4[1 : 1]; + assign _zz_26 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_27 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_28 = ($signed(_zz_29) + $signed(_zz_33)); + assign _zz_29 = ($signed(_zz_30) + $signed(_zz_31)); + assign _zz_30 = stageB_request_data; + assign _zz_31 = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux); + assign _zz_32 = (stageB_amo_compare ? _zz_34 : _zz_35); + assign _zz_33 = {{30{_zz_32[1]}}, _zz_32}; + assign _zz_34 = 2'b01; + assign _zz_35 = 2'b00; + assign _zz_36 = 1'b1; + assign _zz_37 = (! stageB_lrSc_reserved); + assign _zz_38 = loader_counter_willIncrement; + assign _zz_39 = {2'd0, _zz_38}; + assign _zz_40 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_41 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_41; end - if(_zz_300_)begin - if(_zz_309_)begin - memory_DivPlugin_rs1[31 : 0] <= _zz_447_[31:0]; - memory_DivPlugin_accumulator[31 : 0] <= ((! _zz_224_[32]) ? _zz_448_ : _zz_449_); - if((memory_DivPlugin_div_counter_value == (6'b100000)))begin - memory_DivPlugin_div_result <= _zz_450_[31:0]; - end - end + end + + always @ (*) begin + _zz_11 = {_zz_45, _zz_44, _zz_43, _zz_42}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_42 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_43 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_44 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_45 <= ways_0_data_symbol3[dataReadCmd_payload]; end - if(_zz_330_)begin - memory_DivPlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_DivPlugin_rs1 <= ((_zz_227_ ? (~ _zz_228_) : _zz_228_) + _zz_456_); - memory_DivPlugin_rs2 <= ((_zz_226_ ? (~ execute_RS2) : execute_RS2) + _zz_458_); - memory_DivPlugin_div_needRevert <= ((_zz_227_ ^ (_zz_226_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end - externalInterruptArray_regNext <= externalInterruptArray; - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LH <= execute_MUL_LH; + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_24[0]; + assign ways_0_tagsReadRsp_error = _zz_25[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_103_; + end + + always @ (*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_102_; + end + + always @ (*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_25_; + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_22_; + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_20_; + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HH <= execute_MUL_HH; + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + if(stageB_request_isAmo)begin + if(_zz_16)begin + dataWriteCmd_valid = 1'b0; + end + end + if(_zz_17)begin + dataWriteCmd_valid = 1'b0; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_HL <= execute_MUL_HL; + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + if(_zz_18)begin + dataWriteCmd_valid = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_18)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + if(_zz_18)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_18_; + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + if(_zz_18)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_36[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + if(_zz_18)begin + dataWriteCmd_payload_mask = 4'b1111; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_16_; + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_26)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_27)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(! _zz_15) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + if(_zz_13)begin + stageB_loaderValid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_14)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(_zz_19)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_15)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(stageB_request_isAmo)begin + if(_zz_16)begin + io_cpu_writeBack_haltIt = 1'b1; + end + end + if(_zz_17)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_MUL <= decode_IS_MUL; + end + + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + always @ (*) begin + stageB_requestDataBypass = stageB_request_data; + if(stageB_request_isAmo)begin + stageB_requestDataBypass = stageB_amo_resultReg; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; + end + + assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; + assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == 2'b11); + assign stageB_amo_addSub = _zz_28; + assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31])); + assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); + always @ (*) begin + case(_zz_23) + 3'b000 : begin + stageB_amo_result = stageB_amo_addSub; + end + 3'b001 : begin + stageB_amo_result = (stageB_request_data ^ stageB_dataMux); + end + 3'b010 : begin + stageB_amo_result = (stageB_request_data | stageB_dataMux); + end + 3'b011 : begin + stageB_amo_result = (stageB_request_data & stageB_dataMux); + end + default : begin + stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux); + end + endcase + end + + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_request_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + if(_zz_20)begin + io_cpu_redo = 1'b1; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_13_; + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_10_; + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_14)begin + io_mem_cmd_valid = (! memCmdSent); + if(_zz_19)begin + io_mem_cmd_valid = 1'b0; + end + end else begin + if(_zz_15)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + if(stageB_request_isAmo)begin + if(_zz_16)begin + io_mem_cmd_valid = 1'b0; + end + end + if(_zz_20)begin + io_mem_cmd_valid = 1'b0; + end + if(_zz_17)begin + io_mem_cmd_valid = 1'b0; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(! _zz_15) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MUL_LL <= execute_MUL_LL; + if((stageB_request_isLrsc && stageB_request_wr))begin + io_cpu_writeBack_data = {31'd0, _zz_37}; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_18)begin + loader_counter_willIncrement = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_39); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_7_; + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; + stageA_request_isAmo <= io_cpu_execute_args_isAmo; + stageA_request_amoCtrl_swap <= io_cpu_execute_args_amoCtrl_swap; + stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_4_; + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_isLrsc <= stageA_request_isLrsc; + stageB_request_isAmo <= stageA_request_isAmo; + stageB_request_amoCtrl_swap <= stageA_request_amoCtrl_swap; + stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + stageB_mmuRsp_ways_0_sel <= io_cpu_memory_mmuRsp_ways_0_sel; + stageB_mmuRsp_ways_0_physical <= io_cpu_memory_mmuRsp_ways_0_physical; + stageB_mmuRsp_ways_1_sel <= io_cpu_memory_mmuRsp_ways_1_sel; + stageB_mmuRsp_ways_1_physical <= io_cpu_memory_mmuRsp_ways_1_physical; + stageB_mmuRsp_ways_2_sel <= io_cpu_memory_mmuRsp_ways_2_sel; + stageB_mmuRsp_ways_2_physical <= io_cpu_memory_mmuRsp_ways_2_physical; + stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; + stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_2_; + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_43_; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_51_; + if(stageB_flusher_valid)begin + if(_zz_21)begin + if(_zz_22)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b001100000011 : begin + stageB_amo_internal_resultRegValid <= io_cpu_writeBack_isStuck; + stageB_amo_resultReg <= stageB_amo_result; + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + stageB_lrSc_reserved <= 1'b0; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; end - 12'b111100010001 : begin + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; end - 12'b000101000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_scause_interrupt <= _zz_469_[0]; - CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(stageB_flusher_valid)begin + if(_zz_21)begin + if(! _zz_22) begin + stageB_flusher_valid <= 1'b0; + end end end - 12'b111100010100 : begin - end - 12'b100111000000 : begin - end - 12'b000100000000 : begin - end - 12'b001100000010 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_487_[0]; - end + if(((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc))begin + stageB_lrSc_reserved <= (! stageB_request_wr); end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end + if(_zz_13)begin + stageB_lrSc_reserved <= stageB_lrSc_reserved; end - 12'b000110000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; - end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; end - 12'b110011000000 : begin + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; end - 12'b000101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0]; - end + if(_zz_18)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); end - 12'b111100010011 : begin + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; end - 12'b000101000100 : begin + if((! loader_valid))begin + loader_waysAllocator <= _zz_40[0:0]; end - 12'b001101000011 : begin + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + input io_cpu_fetch_mmuRsp_ways_0_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_0_physical, + input io_cpu_fetch_mmuRsp_ways_1_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_1_physical, + input io_cpu_fetch_mmuRsp_ways_2_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_2_physical, + input io_cpu_fetch_mmuRsp_ways_3_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_3_physical, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_9, + input [31:0] _zz_10, + input clk, + input reset +); + reg [31:0] _zz_11; + reg [21:0] _zz_12; + wire _zz_13; + wire _zz_14; + wire [0:0] _zz_15; + wire [0:0] _zz_16; + wire [21:0] _zz_17; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_mmuRsp_ways_0_sel; + reg [31:0] decodeStage_mmuRsp_ways_0_physical; + reg decodeStage_mmuRsp_ways_1_sel; + reg [31:0] decodeStage_mmuRsp_ways_1_physical; + reg decodeStage_mmuRsp_ways_2_sel; + reg [31:0] decodeStage_mmuRsp_ways_2_physical; + reg decodeStage_mmuRsp_ways_3_sel; + reg [31:0] decodeStage_mmuRsp_ways_3_physical; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_13 = (! lineLoader_flushCounter[7]); + assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_15 = _zz_8[0 : 0]; + assign _zz_16 = _zz_8[1 : 1]; + assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_11 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_12 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; end - 12'b000100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_13)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_12; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; end - 12'b111111000000 : begin + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; end - 12'b001101000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; - end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end - 12'b001100000100 : begin + if(io_flush)begin + lineLoader_flushPending <= 1'b1; end - 12'b111100010010 : begin + if(_zz_14)begin + lineLoader_flushPending <= 1'b0; end - 12'b000101000011 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0]; - end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; end - 12'b110111000000 : begin + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; end - 12'b000101000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; end end - 12'b001101000010 : begin - end - 12'b000100000100 : begin - end - default : begin - end - endcase - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end end always @ (posedge clk) begin - DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin - DebugPlugin_firstCycle <= 1'b1; + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; end - DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_95_; + if(_zz_13)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_233_ <= debug_bus_cmd_payload_address[2]; - if(_zz_307_)begin - DebugPlugin_busReadDataReg <= execute_PC; + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_14)begin + lineLoader_flushCounter <= 8'h0; end - DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; - end - - always @ (posedge clk) begin - if(debugReset) begin - DebugPlugin_resetIt <= 1'b0; - DebugPlugin_haltIt <= 1'b0; - DebugPlugin_stepIt <= 1'b0; - DebugPlugin_godmode <= 1'b0; - DebugPlugin_haltedByBreak <= 1'b0; - end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin - DebugPlugin_godmode <= 1'b1; - end - if(debug_bus_cmd_valid)begin - case(_zz_331_) - 6'b000000 : begin - if(debug_bus_cmd_payload_wr)begin - DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin - DebugPlugin_resetIt <= 1'b1; - end - if(debug_bus_cmd_payload_data[24])begin - DebugPlugin_resetIt <= 1'b0; - end - if(debug_bus_cmd_payload_data[17])begin - DebugPlugin_haltIt <= 1'b1; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_haltIt <= 1'b0; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_haltedByBreak <= 1'b0; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_godmode <= 1'b0; - end - end - end - 6'b000001 : begin - end - default : begin - end - endcase - end - if(_zz_307_)begin - if(_zz_308_)begin - DebugPlugin_haltIt <= 1'b1; - DebugPlugin_haltedByBreak <= 1'b1; - end - end - if(_zz_312_)begin - if(decode_arbitration_isValid)begin - DebugPlugin_haltIt <= 1'b1; - end - end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + decodeStage_mmuRsp_ways_0_sel <= io_cpu_fetch_mmuRsp_ways_0_sel; + decodeStage_mmuRsp_ways_0_physical <= io_cpu_fetch_mmuRsp_ways_0_physical; + decodeStage_mmuRsp_ways_1_sel <= io_cpu_fetch_mmuRsp_ways_1_sel; + decodeStage_mmuRsp_ways_1_physical <= io_cpu_fetch_mmuRsp_ways_1_physical; + decodeStage_mmuRsp_ways_2_sel <= io_cpu_fetch_mmuRsp_ways_2_sel; + decodeStage_mmuRsp_ways_2_physical <= io_cpu_fetch_mmuRsp_ways_2_physical; + decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; + decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + if((_zz_9 != 3'b000))begin + io_cpu_fetch_data_regNextWhen <= _zz_10; end end -endmodule +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v index 5be0dac..858cba5 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v @@ -1,13 +1,8 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:07:42 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - `define EnvCtrlEnum_defaultEncoding_type [1:0] `define EnvCtrlEnum_defaultEncoding_NONE 2'b00 `define EnvCtrlEnum_defaultEncoding_XRET 2'b01 @@ -20,29 +15,34 @@ `define BranchCtrlEnum_defaultEncoding_JAL 2'b10 `define BranchCtrlEnum_defaultEncoding_JALR 2'b11 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - `define ShiftCtrlEnum_defaultEncoding_type [1:0] `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 `define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + `define Src2CtrlEnum_defaultEncoding_type [1:0] `define Src2CtrlEnum_defaultEncoding_RS 2'b00 `define Src2CtrlEnum_defaultEncoding_IMI 2'b01 `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + `define MmuPlugin_shared_State_defaultEncoding_type [2:0] `define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000 `define MmuPlugin_shared_State_defaultEncoding_L1_CMD 3'b001 @@ -50,3549 +50,2565 @@ `define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011 `define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100 -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire [0:0] _zz_14_; - wire [0:0] _zz_15_; - wire [21:0] _zz_16_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [6:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_7_; - wire [9:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - reg [31:0] io_cpu_fetch_data_regNextWhen; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_hit_valid; - reg decodeStage_hit_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:1023]; - assign _zz_12_ = (! lineLoader_flushCounter[7]); - assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_14_ = _zz_7_[0 : 0]; - assign _zz_15_ = _zz_7_[1 : 1]; - assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; - end - end - always @ (posedge clk) begin - if(_zz_6_) begin - _zz_10_ <= ways_0_tags[_zz_5_]; - end - end +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + wire _zz_191; + wire _zz_192; + wire _zz_193; + wire _zz_194; + reg _zz_195; + reg _zz_196; + reg [31:0] _zz_197; + reg _zz_198; + reg [31:0] _zz_199; + reg [1:0] _zz_200; + reg _zz_201; + reg _zz_202; + wire _zz_203; + wire [2:0] _zz_204; + reg _zz_205; + wire [31:0] _zz_206; + reg _zz_207; + reg _zz_208; + wire _zz_209; + wire [31:0] _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + wire [3:0] _zz_219; + wire _zz_220; + wire _zz_221; + reg [31:0] _zz_222; + reg [31:0] _zz_223; + reg [31:0] _zz_224; + reg _zz_225; + reg _zz_226; + reg _zz_227; + reg [9:0] _zz_228; + reg [9:0] _zz_229; + reg [9:0] _zz_230; + reg [9:0] _zz_231; + reg _zz_232; + reg _zz_233; + reg _zz_234; + reg _zz_235; + reg _zz_236; + reg _zz_237; + reg _zz_238; + reg [9:0] _zz_239; + reg [9:0] _zz_240; + reg [9:0] _zz_241; + reg [9:0] _zz_242; + reg _zz_243; + reg _zz_244; + reg _zz_245; + reg _zz_246; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire _zz_255; + wire _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire [1:0] _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire _zz_284; + wire _zz_285; + wire _zz_286; + wire _zz_287; + wire _zz_288; + wire _zz_289; + wire _zz_290; + wire _zz_291; + wire _zz_292; + wire _zz_293; + wire _zz_294; + wire _zz_295; + wire _zz_296; + wire _zz_297; + wire _zz_298; + wire _zz_299; + wire _zz_300; + wire _zz_301; + wire _zz_302; + wire [1:0] _zz_303; + wire _zz_304; + wire [32:0] _zz_305; + wire [31:0] _zz_306; + wire [32:0] _zz_307; + wire [0:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire [0:0] _zz_321; + wire [0:0] _zz_322; + wire [0:0] _zz_323; + wire [0:0] _zz_324; + wire [0:0] _zz_325; + wire [0:0] _zz_326; + wire [0:0] _zz_327; + wire [3:0] _zz_328; + wire [2:0] _zz_329; + wire [31:0] _zz_330; + wire [2:0] _zz_331; + wire [2:0] _zz_332; + wire [0:0] _zz_333; + wire [1:0] _zz_334; + wire [0:0] _zz_335; + wire [1:0] _zz_336; + wire [0:0] _zz_337; + wire [0:0] _zz_338; + wire [0:0] _zz_339; + wire [0:0] _zz_340; + wire [0:0] _zz_341; + wire [0:0] _zz_342; + wire [0:0] _zz_343; + wire [0:0] _zz_344; + wire [1:0] _zz_345; + wire [0:0] _zz_346; + wire [2:0] _zz_347; + wire [4:0] _zz_348; + wire [11:0] _zz_349; + wire [11:0] _zz_350; + wire [31:0] _zz_351; + wire [31:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; + wire [31:0] _zz_355; + wire [31:0] _zz_356; + wire [31:0] _zz_357; + wire [19:0] _zz_358; + wire [11:0] _zz_359; + wire [11:0] _zz_360; + wire [1:0] _zz_361; + wire [1:0] _zz_362; + wire [0:0] _zz_363; + wire [5:0] _zz_364; + wire [33:0] _zz_365; + wire [32:0] _zz_366; + wire [33:0] _zz_367; + wire [32:0] _zz_368; + wire [33:0] _zz_369; + wire [32:0] _zz_370; + wire [0:0] _zz_371; + wire [5:0] _zz_372; + wire [32:0] _zz_373; + wire [31:0] _zz_374; + wire [31:0] _zz_375; + wire [32:0] _zz_376; + wire [32:0] _zz_377; + wire [32:0] _zz_378; + wire [32:0] _zz_379; + wire [0:0] _zz_380; + wire [32:0] _zz_381; + wire [0:0] _zz_382; + wire [32:0] _zz_383; + wire [0:0] _zz_384; + wire [31:0] _zz_385; + wire [0:0] _zz_386; + wire [0:0] _zz_387; + wire [0:0] _zz_388; + wire [0:0] _zz_389; + wire [0:0] _zz_390; + wire [0:0] _zz_391; + wire [0:0] _zz_392; + wire [0:0] _zz_393; + wire [0:0] _zz_394; + wire [0:0] _zz_395; + wire [0:0] _zz_396; + wire [0:0] _zz_397; + wire [0:0] _zz_398; + wire [0:0] _zz_399; + wire [0:0] _zz_400; + wire [0:0] _zz_401; + wire [0:0] _zz_402; + wire [0:0] _zz_403; + wire [0:0] _zz_404; + wire [0:0] _zz_405; + wire [0:0] _zz_406; + wire [0:0] _zz_407; + wire [0:0] _zz_408; + wire [0:0] _zz_409; + wire [0:0] _zz_410; + wire [0:0] _zz_411; + wire [0:0] _zz_412; + wire [0:0] _zz_413; + wire [0:0] _zz_414; + wire [0:0] _zz_415; + wire [0:0] _zz_416; + wire [0:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire [0:0] _zz_420; + wire [0:0] _zz_421; + wire [0:0] _zz_422; + wire [0:0] _zz_423; + wire [0:0] _zz_424; + wire [0:0] _zz_425; + wire [0:0] _zz_426; + wire [0:0] _zz_427; + wire [0:0] _zz_428; + wire [0:0] _zz_429; + wire [0:0] _zz_430; + wire [26:0] _zz_431; + wire _zz_432; + wire _zz_433; + wire [1:0] _zz_434; + wire [31:0] _zz_435; + wire [31:0] _zz_436; + wire [31:0] _zz_437; + wire _zz_438; + wire [0:0] _zz_439; + wire [17:0] _zz_440; + wire [31:0] _zz_441; + wire [31:0] _zz_442; + wire [31:0] _zz_443; + wire _zz_444; + wire [0:0] _zz_445; + wire [11:0] _zz_446; + wire [31:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire _zz_450; + wire [0:0] _zz_451; + wire [5:0] _zz_452; + wire [31:0] _zz_453; + wire [31:0] _zz_454; + wire [31:0] _zz_455; + wire _zz_456; + wire _zz_457; + wire [31:0] _zz_458; + wire [0:0] _zz_459; + wire [1:0] _zz_460; + wire [0:0] _zz_461; + wire [0:0] _zz_462; + wire _zz_463; + wire [0:0] _zz_464; + wire [28:0] _zz_465; + wire [31:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [0:0] _zz_469; + wire [0:0] _zz_470; + wire [1:0] _zz_471; + wire [1:0] _zz_472; + wire _zz_473; + wire [0:0] _zz_474; + wire [24:0] _zz_475; + wire [31:0] _zz_476; + wire [31:0] _zz_477; + wire [31:0] _zz_478; + wire [31:0] _zz_479; + wire [31:0] _zz_480; + wire [31:0] _zz_481; + wire [0:0] _zz_482; + wire [0:0] _zz_483; + wire [2:0] _zz_484; + wire [2:0] _zz_485; + wire _zz_486; + wire [0:0] _zz_487; + wire [21:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; + wire [31:0] _zz_491; + wire [31:0] _zz_492; + wire _zz_493; + wire _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire [1:0] _zz_497; + wire [1:0] _zz_498; + wire _zz_499; + wire [0:0] _zz_500; + wire [18:0] _zz_501; + wire [31:0] _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire [31:0] _zz_505; + wire [31:0] _zz_506; + wire [31:0] _zz_507; + wire _zz_508; + wire [0:0] _zz_509; + wire [0:0] _zz_510; + wire _zz_511; + wire [0:0] _zz_512; + wire [15:0] _zz_513; + wire [31:0] _zz_514; + wire [31:0] _zz_515; + wire _zz_516; + wire [0:0] _zz_517; + wire [0:0] _zz_518; + wire [31:0] _zz_519; + wire [31:0] _zz_520; + wire _zz_521; + wire [5:0] _zz_522; + wire [5:0] _zz_523; + wire _zz_524; + wire [0:0] _zz_525; + wire [11:0] _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; + wire [31:0] _zz_529; + wire [31:0] _zz_530; + wire _zz_531; + wire [0:0] _zz_532; + wire [2:0] _zz_533; + wire _zz_534; + wire [0:0] _zz_535; + wire [0:0] _zz_536; + wire _zz_537; + wire [4:0] _zz_538; + wire [4:0] _zz_539; + wire _zz_540; + wire [0:0] _zz_541; + wire [8:0] _zz_542; + wire [31:0] _zz_543; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire _zz_546; + wire [0:0] _zz_547; + wire [0:0] _zz_548; + wire [31:0] _zz_549; + wire [31:0] _zz_550; + wire [31:0] _zz_551; + wire [31:0] _zz_552; + wire [31:0] _zz_553; + wire [31:0] _zz_554; + wire [0:0] _zz_555; + wire [2:0] _zz_556; + wire [0:0] _zz_557; + wire [5:0] _zz_558; + wire [1:0] _zz_559; + wire [1:0] _zz_560; + wire _zz_561; + wire [0:0] _zz_562; + wire [6:0] _zz_563; + wire [31:0] _zz_564; + wire [31:0] _zz_565; + wire [31:0] _zz_566; + wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [31:0] _zz_570; + wire _zz_571; + wire [0:0] _zz_572; + wire [0:0] _zz_573; + wire _zz_574; + wire [0:0] _zz_575; + wire [3:0] _zz_576; + wire _zz_577; + wire [0:0] _zz_578; + wire [0:0] _zz_579; + wire [0:0] _zz_580; + wire [0:0] _zz_581; + wire _zz_582; + wire [0:0] _zz_583; + wire [4:0] _zz_584; + wire [31:0] _zz_585; + wire [31:0] _zz_586; + wire [31:0] _zz_587; + wire [31:0] _zz_588; + wire [31:0] _zz_589; + wire [31:0] _zz_590; + wire [31:0] _zz_591; + wire [31:0] _zz_592; + wire _zz_593; + wire [0:0] _zz_594; + wire [1:0] _zz_595; + wire [31:0] _zz_596; + wire [31:0] _zz_597; + wire [31:0] _zz_598; + wire [31:0] _zz_599; + wire [31:0] _zz_600; + wire _zz_601; + wire [4:0] _zz_602; + wire [4:0] _zz_603; + wire _zz_604; + wire [0:0] _zz_605; + wire [2:0] _zz_606; + wire [31:0] _zz_607; + wire [31:0] _zz_608; + wire [31:0] _zz_609; + wire _zz_610; + wire [31:0] _zz_611; + wire _zz_612; + wire [0:0] _zz_613; + wire [2:0] _zz_614; + wire [0:0] _zz_615; + wire [0:0] _zz_616; + wire [2:0] _zz_617; + wire [2:0] _zz_618; + wire _zz_619; + wire [0:0] _zz_620; + wire [0:0] _zz_621; + wire [31:0] _zz_622; + wire [31:0] _zz_623; + wire [31:0] _zz_624; + wire [31:0] _zz_625; + wire _zz_626; + wire [0:0] _zz_627; + wire [0:0] _zz_628; + wire [31:0] _zz_629; + wire [31:0] _zz_630; + wire _zz_631; + wire [0:0] _zz_632; + wire [0:0] _zz_633; + wire [0:0] _zz_634; + wire [1:0] _zz_635; + wire [1:0] _zz_636; + wire [1:0] _zz_637; + wire [0:0] _zz_638; + wire [0:0] _zz_639; + wire [31:0] _zz_640; + wire [31:0] _zz_641; + wire [31:0] _zz_642; + wire [31:0] _zz_643; + wire [31:0] _zz_644; + wire [31:0] _zz_645; + wire [31:0] _zz_646; + wire [31:0] _zz_647; + wire [31:0] _zz_648; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire execute_IS_DBUS_SHARING; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_DIV; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `BranchCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire decode_SRC_LESS_UNSIGNED; + wire memory_IS_SFENCE_VMA; + wire execute_IS_SFENCE_VMA; + wire decode_IS_SFENCE_VMA; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_MUL; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire memory_IS_MUL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_30; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_31; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_32; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_33; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_35; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_36; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_37; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_38; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_39; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_40; + wire [31:0] _zz_41; + wire _zz_42; + reg _zz_43; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_44; + wire `BranchCtrlEnum_defaultEncoding_type _zz_45; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_46; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47; + wire `Src2CtrlEnum_defaultEncoding_type _zz_48; + wire `AluCtrlEnum_defaultEncoding_type _zz_49; + wire `Src1CtrlEnum_defaultEncoding_type _zz_50; + wire writeBack_IS_SFENCE_VMA; + wire writeBack_IS_DBUS_SHARING; + wire memory_IS_DBUS_SHARING; + reg [31:0] _zz_51; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_AMO; + wire execute_MEMORY_LRSC; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + wire [31:0] execute_RS2; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_AMO; + wire decode_MEMORY_LRSC; + reg _zz_52; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_53; + reg [31:0] _zz_54; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg IBusCachedPlugin_mmuBus_rsp_isPaging; + reg IBusCachedPlugin_mmuBus_rsp_allowRead; + reg IBusCachedPlugin_mmuBus_rsp_allowWrite; + reg IBusCachedPlugin_mmuBus_rsp_allowExecute; + reg IBusCachedPlugin_mmuBus_rsp_exception; + reg IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire IBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + reg DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + reg DBusCachedPlugin_mmuBus_rsp_isPaging; + reg DBusCachedPlugin_mmuBus_rsp_allowRead; + reg DBusCachedPlugin_mmuBus_rsp_allowWrite; + reg DBusCachedPlugin_mmuBus_rsp_allowExecute; + reg DBusCachedPlugin_mmuBus_rsp_exception; + reg DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_rsp_ways_0_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_0_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_1_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_1_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_2_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_2_physical; + wire DBusCachedPlugin_mmuBus_rsp_ways_3_sel; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_ways_3_physical; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg MmuPlugin_dBusAccess_cmd_valid; + reg MmuPlugin_dBusAccess_cmd_ready; + reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; + wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; + wire MmuPlugin_dBusAccess_cmd_payload_write; + wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; + wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; + wire MmuPlugin_dBusAccess_rsp_valid; + wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; + wire MmuPlugin_dBusAccess_rsp_payload_error; + wire MmuPlugin_dBusAccess_rsp_payload_redo; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + reg CsrPlugin_redoInterface_valid; + wire [31:0] CsrPlugin_redoInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire externalInterruptS; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_55; + wire [3:0] _zz_56; + wire _zz_57; + wire _zz_58; + wire _zz_59; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire IBusCachedPlugin_iBusRsp_stages_3_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_3_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_3_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_3_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_3_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_3_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_3_halt; + wire _zz_60; + wire _zz_61; + wire _zz_62; + wire _zz_63; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_64; + wire _zz_65; + reg _zz_66; + wire _zz_67; + reg _zz_68; + reg [31:0] _zz_69; + wire _zz_70; + reg _zz_71; + reg [31:0] _zz_72; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + reg IBusCachedPlugin_injector_nextPcCalc_valids_5; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_73; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_74; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_75; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_76; + reg [31:0] _zz_77; + wire _zz_78; + reg [31:0] _zz_79; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + reg DBusCachedPlugin_forceDatapath; + reg MmuPlugin_status_sum; + reg MmuPlugin_status_mxr; + reg MmuPlugin_status_mprv; + reg MmuPlugin_satp_mode; + reg [8:0] MmuPlugin_satp_asid; + reg [19:0] MmuPlugin_satp_ppn; + reg MmuPlugin_ports_0_cache_0_valid; + reg MmuPlugin_ports_0_cache_0_exception; + reg MmuPlugin_ports_0_cache_0_superPage; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; + reg MmuPlugin_ports_0_cache_0_allowRead; + reg MmuPlugin_ports_0_cache_0_allowWrite; + reg MmuPlugin_ports_0_cache_0_allowExecute; + reg MmuPlugin_ports_0_cache_0_allowUser; + reg MmuPlugin_ports_0_cache_1_valid; + reg MmuPlugin_ports_0_cache_1_exception; + reg MmuPlugin_ports_0_cache_1_superPage; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; + reg MmuPlugin_ports_0_cache_1_allowRead; + reg MmuPlugin_ports_0_cache_1_allowWrite; + reg MmuPlugin_ports_0_cache_1_allowExecute; + reg MmuPlugin_ports_0_cache_1_allowUser; + reg MmuPlugin_ports_0_cache_2_valid; + reg MmuPlugin_ports_0_cache_2_exception; + reg MmuPlugin_ports_0_cache_2_superPage; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; + reg MmuPlugin_ports_0_cache_2_allowRead; + reg MmuPlugin_ports_0_cache_2_allowWrite; + reg MmuPlugin_ports_0_cache_2_allowExecute; + reg MmuPlugin_ports_0_cache_2_allowUser; + reg MmuPlugin_ports_0_cache_3_valid; + reg MmuPlugin_ports_0_cache_3_exception; + reg MmuPlugin_ports_0_cache_3_superPage; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; + reg MmuPlugin_ports_0_cache_3_allowRead; + reg MmuPlugin_ports_0_cache_3_allowWrite; + reg MmuPlugin_ports_0_cache_3_allowExecute; + reg MmuPlugin_ports_0_cache_3_allowUser; + wire MmuPlugin_ports_0_dirty; + reg MmuPlugin_ports_0_requireMmuLockupCalc; + reg [3:0] MmuPlugin_ports_0_cacheHitsCalc; + wire MmuPlugin_ports_0_cacheHit; + wire _zz_80; + wire _zz_81; + wire _zz_82; + wire [1:0] _zz_83; + wire MmuPlugin_ports_0_cacheLine_valid; + wire MmuPlugin_ports_0_cacheLine_exception; + wire MmuPlugin_ports_0_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_0_cacheLine_allowRead; + wire MmuPlugin_ports_0_cacheLine_allowWrite; + wire MmuPlugin_ports_0_cacheLine_allowExecute; + wire MmuPlugin_ports_0_cacheLine_allowUser; + reg MmuPlugin_ports_0_entryToReplace_willIncrement; + wire MmuPlugin_ports_0_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_0_entryToReplace_value; + wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_0_entryToReplace_willOverflow; + reg MmuPlugin_ports_1_cache_0_valid; + reg MmuPlugin_ports_1_cache_0_exception; + reg MmuPlugin_ports_1_cache_0_superPage; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; + reg MmuPlugin_ports_1_cache_0_allowRead; + reg MmuPlugin_ports_1_cache_0_allowWrite; + reg MmuPlugin_ports_1_cache_0_allowExecute; + reg MmuPlugin_ports_1_cache_0_allowUser; + reg MmuPlugin_ports_1_cache_1_valid; + reg MmuPlugin_ports_1_cache_1_exception; + reg MmuPlugin_ports_1_cache_1_superPage; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; + reg MmuPlugin_ports_1_cache_1_allowRead; + reg MmuPlugin_ports_1_cache_1_allowWrite; + reg MmuPlugin_ports_1_cache_1_allowExecute; + reg MmuPlugin_ports_1_cache_1_allowUser; + reg MmuPlugin_ports_1_cache_2_valid; + reg MmuPlugin_ports_1_cache_2_exception; + reg MmuPlugin_ports_1_cache_2_superPage; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; + reg MmuPlugin_ports_1_cache_2_allowRead; + reg MmuPlugin_ports_1_cache_2_allowWrite; + reg MmuPlugin_ports_1_cache_2_allowExecute; + reg MmuPlugin_ports_1_cache_2_allowUser; + reg MmuPlugin_ports_1_cache_3_valid; + reg MmuPlugin_ports_1_cache_3_exception; + reg MmuPlugin_ports_1_cache_3_superPage; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; + reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; + reg MmuPlugin_ports_1_cache_3_allowRead; + reg MmuPlugin_ports_1_cache_3_allowWrite; + reg MmuPlugin_ports_1_cache_3_allowExecute; + reg MmuPlugin_ports_1_cache_3_allowUser; + wire MmuPlugin_ports_1_dirty; + reg MmuPlugin_ports_1_requireMmuLockupCalc; + reg [3:0] MmuPlugin_ports_1_cacheHitsCalc; + wire MmuPlugin_ports_1_cacheHit; + wire _zz_84; + wire _zz_85; + wire _zz_86; + wire [1:0] _zz_87; + wire MmuPlugin_ports_1_cacheLine_valid; + wire MmuPlugin_ports_1_cacheLine_exception; + wire MmuPlugin_ports_1_cacheLine_superPage; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; + wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; + wire MmuPlugin_ports_1_cacheLine_allowRead; + wire MmuPlugin_ports_1_cacheLine_allowWrite; + wire MmuPlugin_ports_1_cacheLine_allowExecute; + wire MmuPlugin_ports_1_cacheLine_allowUser; + reg MmuPlugin_ports_1_entryToReplace_willIncrement; + wire MmuPlugin_ports_1_entryToReplace_willClear; + reg [1:0] MmuPlugin_ports_1_entryToReplace_valueNext; + reg [1:0] MmuPlugin_ports_1_entryToReplace_value; + wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; + wire MmuPlugin_ports_1_entryToReplace_willOverflow; + reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1; + reg [9:0] MmuPlugin_shared_vpn_0; + reg [9:0] MmuPlugin_shared_vpn_1; + reg [1:0] MmuPlugin_shared_portSortedOh; + reg MmuPlugin_shared_dBusRspStaged_valid; + reg [31:0] MmuPlugin_shared_dBusRspStaged_payload_data; + reg MmuPlugin_shared_dBusRspStaged_payload_error; + reg MmuPlugin_shared_dBusRspStaged_payload_redo; + wire MmuPlugin_shared_dBusRsp_pte_V; + wire MmuPlugin_shared_dBusRsp_pte_R; + wire MmuPlugin_shared_dBusRsp_pte_W; + wire MmuPlugin_shared_dBusRsp_pte_X; + wire MmuPlugin_shared_dBusRsp_pte_U; + wire MmuPlugin_shared_dBusRsp_pte_G; + wire MmuPlugin_shared_dBusRsp_pte_A; + wire MmuPlugin_shared_dBusRsp_pte_D; + wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; + wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; + wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; + wire MmuPlugin_shared_dBusRsp_exception; + wire MmuPlugin_shared_dBusRsp_leaf; + reg MmuPlugin_shared_pteBuffer_V; + reg MmuPlugin_shared_pteBuffer_R; + reg MmuPlugin_shared_pteBuffer_W; + reg MmuPlugin_shared_pteBuffer_X; + reg MmuPlugin_shared_pteBuffer_U; + reg MmuPlugin_shared_pteBuffer_G; + reg MmuPlugin_shared_pteBuffer_A; + reg MmuPlugin_shared_pteBuffer_D; + reg [1:0] MmuPlugin_shared_pteBuffer_RSW; + reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; + reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; + reg [1:0] _zz_88; + wire [1:0] _zz_89; + reg [1:0] _zz_90; + wire [1:0] MmuPlugin_shared_refills; + wire [1:0] _zz_91; + reg [1:0] _zz_92; + wire [31:0] _zz_93; + wire [34:0] _zz_94; + wire _zz_95; + wire _zz_96; + wire _zz_97; + wire _zz_98; + wire _zz_99; + wire _zz_100; + wire _zz_101; + wire _zz_102; + wire `Src1CtrlEnum_defaultEncoding_type _zz_103; + wire `AluCtrlEnum_defaultEncoding_type _zz_104; + wire `Src2CtrlEnum_defaultEncoding_type _zz_105; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_106; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_107; + wire `BranchCtrlEnum_defaultEncoding_type _zz_108; + wire `EnvCtrlEnum_defaultEncoding_type _zz_109; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_110; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_111; + reg [31:0] _zz_112; + wire _zz_113; + reg [19:0] _zz_114; + wire _zz_115; + reg [19:0] _zz_116; + reg [31:0] _zz_117; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_118; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_119; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_120; + wire _zz_121; + wire _zz_122; + wire _zz_123; + wire _zz_124; + wire _zz_125; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_126; + reg _zz_127; + reg _zz_128; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_129; + reg [10:0] _zz_130; + wire _zz_131; + reg [19:0] _zz_132; + wire _zz_133; + reg [18:0] _zz_134; + reg [31:0] _zz_135; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] _zz_136; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg CsrPlugin_medeleg_IAM; + reg CsrPlugin_medeleg_IAF; + reg CsrPlugin_medeleg_II; + reg CsrPlugin_medeleg_LAM; + reg CsrPlugin_medeleg_LAF; + reg CsrPlugin_medeleg_SAM; + reg CsrPlugin_medeleg_SAF; + reg CsrPlugin_medeleg_EU; + reg CsrPlugin_medeleg_ES; + reg CsrPlugin_medeleg_IPF; + reg CsrPlugin_medeleg_LPF; + reg CsrPlugin_medeleg_SPF; + reg CsrPlugin_mideleg_ST; + reg CsrPlugin_mideleg_SE; + reg CsrPlugin_mideleg_SS; + reg CsrPlugin_sstatus_SIE; + reg CsrPlugin_sstatus_SPIE; + reg [0:0] CsrPlugin_sstatus_SPP; + reg CsrPlugin_sip_SEIP_SOFT; + reg CsrPlugin_sip_SEIP_INPUT; + wire CsrPlugin_sip_SEIP_OR; + reg CsrPlugin_sip_STIP; + reg CsrPlugin_sip_SSIP; + reg CsrPlugin_sie_SEIE; + reg CsrPlugin_sie_STIE; + reg CsrPlugin_sie_SSIE; + reg [1:0] CsrPlugin_stvec_mode; + reg [29:0] CsrPlugin_stvec_base; + reg [31:0] CsrPlugin_sscratch; + reg CsrPlugin_scause_interrupt; + reg [3:0] CsrPlugin_scause_exceptionCode; + reg [31:0] CsrPlugin_stval; + reg [31:0] CsrPlugin_sepc; + reg [21:0] CsrPlugin_satp_PPN; + reg [8:0] CsrPlugin_satp_ASID; + reg [0:0] CsrPlugin_satp_MODE; + wire _zz_137; + wire _zz_138; + wire _zz_139; + wire _zz_140; + wire _zz_141; + wire _zz_142; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_143; + wire _zz_144; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + reg [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_mul_counter_willIncrement; + reg memory_MulDivIterativePlugin_mul_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; + wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire [31:0] _zz_145; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [31:0] _zz_146; + wire _zz_147; + wire _zz_148; + reg [32:0] _zz_149; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_150; + wire [31:0] _zz_151; + reg [31:0] _zz_152; + wire [31:0] _zz_153; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_LRSC; + reg decode_to_execute_MEMORY_AMO; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_IS_SFENCE_VMA; + reg execute_to_memory_IS_SFENCE_VMA; + reg memory_to_writeBack_IS_SFENCE_VMA; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_IS_DBUS_SHARING; + reg memory_to_writeBack_IS_DBUS_SHARING; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_256; + reg execute_CsrPlugin_csr_384; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_770; + reg execute_CsrPlugin_csr_771; + reg execute_CsrPlugin_csr_324; + reg execute_CsrPlugin_csr_260; + reg execute_CsrPlugin_csr_261; + reg execute_CsrPlugin_csr_321; + reg execute_CsrPlugin_csr_320; + reg execute_CsrPlugin_csr_322; + reg execute_CsrPlugin_csr_323; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg execute_CsrPlugin_csr_2496; + reg execute_CsrPlugin_csr_3520; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [2:0] _zz_178; + reg _zz_179; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_180; + wire _zz_181; + wire _zz_182; + wire _zz_183; + wire _zz_184; + wire _zz_185; + reg _zz_186; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [31:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] _zz_12_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [71:0] _zz_15_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [39:0] _zz_18_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_19_string; + reg [23:0] _zz_20_string; + reg [23:0] _zz_21_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_22_string; + reg [63:0] _zz_23_string; + reg [63:0] _zz_24_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_25_string; + reg [95:0] _zz_26_string; + reg [95:0] _zz_27_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_29_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_30_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_31_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_34_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_35_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_37_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_38_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_39_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_40_string; + reg [39:0] _zz_44_string; + reg [31:0] _zz_45_string; + reg [71:0] _zz_46_string; + reg [39:0] _zz_47_string; + reg [23:0] _zz_48_string; + reg [63:0] _zz_49_string; + reg [95:0] _zz_50_string; + reg [47:0] MmuPlugin_shared_state_1_string; + reg [95:0] _zz_103_string; + reg [63:0] _zz_104_string; + reg [23:0] _zz_105_string; + reg [39:0] _zz_106_string; + reg [71:0] _zz_107_string; + reg [31:0] _zz_108_string; + reg [39:0] _zz_109_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif - always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_247 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_248 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_249 = 1'b1; + assign _zz_250 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_251 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_252 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_254 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_255 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_256 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_257 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_260 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_264 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign _zz_265 = (! dataCache_1_io_cpu_execute_refilling); + assign _zz_266 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_267 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign _zz_268 = MmuPlugin_shared_portSortedOh[0]; + assign _zz_269 = MmuPlugin_shared_portSortedOh[1]; + assign _zz_270 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_271 = (1'b0 || (! 1'b1)); + assign _zz_272 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_273 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_274 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_275 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_276 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_277 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_278 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_279 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_280 = (! memory_arbitration_isStuck); + assign _zz_281 = (iBus_cmd_valid || (_zz_178 != 3'b000)); + assign _zz_282 = (_zz_221 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_283 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_284 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign _zz_285 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign _zz_286 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign _zz_287 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign _zz_288 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign _zz_289 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign _zz_290 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign _zz_291 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign _zz_292 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign _zz_293 = ((_zz_137 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign _zz_294 = ((_zz_138 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign _zz_295 = ((_zz_139 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign _zz_296 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_297 = ((_zz_137 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign _zz_298 = ((_zz_138 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign _zz_299 = ((_zz_139 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign _zz_300 = ((_zz_140 && 1'b1) && (! 1'b0)); + assign _zz_301 = ((_zz_141 && 1'b1) && (! 1'b0)); + assign _zz_302 = ((_zz_142 && 1'b1) && (! 1'b0)); + assign _zz_303 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_304 = execute_INSTRUCTION[13]; + assign _zz_305 = ($signed(_zz_307) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_306 = _zz_305[31 : 0]; + assign _zz_307 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_308 = _zz_94[34 : 34]; + assign _zz_309 = _zz_94[33 : 33]; + assign _zz_310 = _zz_94[32 : 32]; + assign _zz_311 = _zz_94[31 : 31]; + assign _zz_312 = _zz_94[28 : 28]; + assign _zz_313 = _zz_94[21 : 21]; + assign _zz_314 = _zz_94[20 : 20]; + assign _zz_315 = _zz_94[19 : 19]; + assign _zz_316 = _zz_94[13 : 13]; + assign _zz_317 = _zz_94[12 : 12]; + assign _zz_318 = _zz_94[11 : 11]; + assign _zz_319 = _zz_94[17 : 17]; + assign _zz_320 = _zz_94[5 : 5]; + assign _zz_321 = _zz_94[3 : 3]; + assign _zz_322 = _zz_94[18 : 18]; + assign _zz_323 = _zz_94[10 : 10]; + assign _zz_324 = _zz_94[16 : 16]; + assign _zz_325 = _zz_94[15 : 15]; + assign _zz_326 = _zz_94[4 : 4]; + assign _zz_327 = _zz_94[0 : 0]; + assign _zz_328 = (_zz_55 - 4'b0001); + assign _zz_329 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_330 = {29'd0, _zz_329}; + assign _zz_331 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_332 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_333 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_334 = {1'd0, _zz_333}; + assign _zz_335 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_336 = {1'd0, _zz_335}; + assign _zz_337 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; + assign _zz_338 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; + assign _zz_339 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; + assign _zz_340 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; + assign _zz_341 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; + assign _zz_342 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; + assign _zz_343 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; + assign _zz_344 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; + assign _zz_345 = (_zz_90 - 2'b01); + assign _zz_346 = execute_SRC_LESS; + assign _zz_347 = 3'b100; + assign _zz_348 = execute_INSTRUCTION[19 : 15]; + assign _zz_349 = execute_INSTRUCTION[31 : 20]; + assign _zz_350 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_351 = ($signed(_zz_352) + $signed(_zz_355)); + assign _zz_352 = ($signed(_zz_353) + $signed(_zz_354)); + assign _zz_353 = execute_SRC1; + assign _zz_354 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_355 = (execute_SRC_USE_SUB_LESS ? _zz_356 : _zz_357); + assign _zz_356 = 32'h00000001; + assign _zz_357 = 32'h0; + assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_359 = execute_INSTRUCTION[31 : 20]; + assign _zz_360 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_361 = (_zz_143 & (~ _zz_362)); + assign _zz_362 = (_zz_143 - 2'b01); + assign _zz_363 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_364 = {5'd0, _zz_363}; + assign _zz_365 = (_zz_367 + _zz_369); + assign _zz_366 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_367 = {{1{_zz_366[32]}}, _zz_366}; + assign _zz_368 = _zz_370; + assign _zz_369 = {{1{_zz_368[32]}}, _zz_368}; + assign _zz_370 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_371 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_372 = {5'd0, _zz_371}; + assign _zz_373 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_374 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_375 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_376 = {_zz_145,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_377 = _zz_378; + assign _zz_378 = _zz_379; + assign _zz_379 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_146) : _zz_146)} + _zz_381); + assign _zz_380 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_381 = {32'd0, _zz_380}; + assign _zz_382 = _zz_148; + assign _zz_383 = {32'd0, _zz_382}; + assign _zz_384 = _zz_147; + assign _zz_385 = {31'd0, _zz_384}; + assign _zz_386 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_387 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_388 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_391 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_392 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_393 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_394 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_395 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_396 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_397 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_398 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_399 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_400 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_401 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_402 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_403 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_404 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_405 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_406 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_407 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_408 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_409 = execute_CsrPlugin_writeData[0 : 0]; + assign _zz_410 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_411 = execute_CsrPlugin_writeData[2 : 2]; + assign _zz_412 = execute_CsrPlugin_writeData[4 : 4]; + assign _zz_413 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_414 = execute_CsrPlugin_writeData[6 : 6]; + assign _zz_415 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_416 = execute_CsrPlugin_writeData[8 : 8]; + assign _zz_417 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_418 = execute_CsrPlugin_writeData[12 : 12]; + assign _zz_419 = execute_CsrPlugin_writeData[13 : 13]; + assign _zz_420 = execute_CsrPlugin_writeData[15 : 15]; + assign _zz_421 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_422 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_423 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_424 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_425 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_426 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_427 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_428 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_429 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_430 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_431 = (iBus_cmd_payload_address >>> 5); + assign _zz_432 = 1'b1; + assign _zz_433 = 1'b1; + assign _zz_434 = {_zz_59,_zz_58}; + assign _zz_435 = 32'h0000107f; + assign _zz_436 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_437 = 32'h00002073; + assign _zz_438 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_439 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_440 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_441) == 32'h00000003),{(_zz_442 == _zz_443),{_zz_444,{_zz_445,_zz_446}}}}}}; + assign _zz_441 = 32'h0000505f; + assign _zz_442 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_443 = 32'h00000063; + assign _zz_444 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_445 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_446 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_447) == 32'h00001013),{(_zz_448 == _zz_449),{_zz_450,{_zz_451,_zz_452}}}}}}; + assign _zz_447 = 32'hfc00305f; + assign _zz_448 = (decode_INSTRUCTION & 32'h01f0707f); + assign _zz_449 = 32'h0000500f; + assign _zz_450 = ((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013); + assign _zz_451 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_452 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_453) == 32'h12000073),{(_zz_454 == _zz_455),{_zz_456,_zz_457}}}}}; + assign _zz_453 = 32'hfe007fff; + assign _zz_454 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_455 = 32'h10200073; + assign _zz_456 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_457 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_458 = 32'h02004064; + assign _zz_459 = _zz_102; + assign _zz_460 = {_zz_100,_zz_101}; + assign _zz_461 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_462 = 1'b0; + assign _zz_463 = (((decode_INSTRUCTION & _zz_466) == 32'h00000050) != 1'b0); + assign _zz_464 = ((_zz_467 == _zz_468) != 1'b0); + assign _zz_465 = {({_zz_469,_zz_470} != 2'b00),{(_zz_471 != _zz_472),{_zz_473,{_zz_474,_zz_475}}}}; + assign _zz_466 = 32'h02203050; + assign _zz_467 = (decode_INSTRUCTION & 32'h02403050); + assign _zz_468 = 32'h00000050; + assign _zz_469 = ((decode_INSTRUCTION & _zz_476) == 32'h00001050); + assign _zz_470 = ((decode_INSTRUCTION & _zz_477) == 32'h00002050); + assign _zz_471 = {_zz_96,(_zz_478 == _zz_479)}; + assign _zz_472 = 2'b00; + assign _zz_473 = ((_zz_480 == _zz_481) != 1'b0); + assign _zz_474 = ({_zz_482,_zz_483} != 2'b00); + assign _zz_475 = {(_zz_484 != _zz_485),{_zz_486,{_zz_487,_zz_488}}}; + assign _zz_476 = 32'h00001050; + assign _zz_477 = 32'h00002050; + assign _zz_478 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_479 = 32'h00000004; + assign _zz_480 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_481 = 32'h00000040; + assign _zz_482 = ((decode_INSTRUCTION & _zz_489) == 32'h00005010); + assign _zz_483 = ((decode_INSTRUCTION & _zz_490) == 32'h00005020); + assign _zz_484 = {(_zz_491 == _zz_492),{_zz_493,_zz_494}}; + assign _zz_485 = 3'b000; + assign _zz_486 = ((_zz_495 == _zz_496) != 1'b0); + assign _zz_487 = (_zz_100 != 1'b0); + assign _zz_488 = {(_zz_497 != _zz_498),{_zz_499,{_zz_500,_zz_501}}}; + assign _zz_489 = 32'h00007034; + assign _zz_490 = 32'h02007064; + assign _zz_491 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_492 = 32'h40001010; + assign _zz_493 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_494 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_495 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_496 = 32'h00001000; + assign _zz_497 = {(_zz_502 == _zz_503),(_zz_504 == _zz_505)}; + assign _zz_498 = 2'b00; + assign _zz_499 = ((_zz_506 == _zz_507) != 1'b0); + assign _zz_500 = (_zz_508 != 1'b0); + assign _zz_501 = {(_zz_509 != _zz_510),{_zz_511,{_zz_512,_zz_513}}}; + assign _zz_502 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_503 = 32'h00002000; + assign _zz_504 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_505 = 32'h00001000; + assign _zz_506 = (decode_INSTRUCTION & 32'h02003050); + assign _zz_507 = 32'h02000050; + assign _zz_508 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz_509 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_510 = 1'b0; + assign _zz_511 = ({(_zz_514 == _zz_515),{_zz_516,{_zz_517,_zz_518}}} != 4'b0000); + assign _zz_512 = ((_zz_519 == _zz_520) != 1'b0); + assign _zz_513 = {(_zz_521 != 1'b0),{(_zz_522 != _zz_523),{_zz_524,{_zz_525,_zz_526}}}}; + assign _zz_514 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_515 = 32'h00000020; + assign _zz_516 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_517 = ((decode_INSTRUCTION & _zz_527) == 32'h08000020); + assign _zz_518 = ((decode_INSTRUCTION & _zz_528) == 32'h00000020); + assign _zz_519 = (decode_INSTRUCTION & 32'h10000008); + assign _zz_520 = 32'h00000008; + assign _zz_521 = ((decode_INSTRUCTION & 32'h10000008) == 32'h10000008); + assign _zz_522 = {(_zz_529 == _zz_530),{_zz_531,{_zz_532,_zz_533}}}; + assign _zz_523 = 6'h0; + assign _zz_524 = ({_zz_534,{_zz_535,_zz_536}} != 3'b000); + assign _zz_525 = (_zz_537 != 1'b0); + assign _zz_526 = {(_zz_538 != _zz_539),{_zz_540,{_zz_541,_zz_542}}}; + assign _zz_527 = 32'h08000070; + assign _zz_528 = 32'h10000070; + assign _zz_529 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_530 = 32'h00002040; + assign _zz_531 = ((decode_INSTRUCTION & _zz_543) == 32'h00001040); + assign _zz_532 = (_zz_544 == _zz_545); + assign _zz_533 = {_zz_546,{_zz_547,_zz_548}}; + assign _zz_534 = ((decode_INSTRUCTION & _zz_549) == 32'h08000020); + assign _zz_535 = (_zz_550 == _zz_551); + assign _zz_536 = (_zz_552 == _zz_553); + assign _zz_537 = ((decode_INSTRUCTION & _zz_554) == 32'h00000010); + assign _zz_538 = {_zz_99,{_zz_555,_zz_556}}; + assign _zz_539 = 5'h0; + assign _zz_540 = ({_zz_557,_zz_558} != 7'h0); + assign _zz_541 = (_zz_559 != _zz_560); + assign _zz_542 = {_zz_561,{_zz_562,_zz_563}}; + assign _zz_543 = 32'h00001040; + assign _zz_544 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_545 = 32'h00000040; + assign _zz_546 = ((decode_INSTRUCTION & _zz_564) == 32'h00000040); + assign _zz_547 = (_zz_565 == _zz_566); + assign _zz_548 = (_zz_567 == _zz_568); + assign _zz_549 = 32'h08000020; + assign _zz_550 = (decode_INSTRUCTION & 32'h10000020); + assign _zz_551 = 32'h00000020; + assign _zz_552 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_553 = 32'h00000020; + assign _zz_554 = 32'h00000010; + assign _zz_555 = (_zz_569 == _zz_570); + assign _zz_556 = {_zz_571,{_zz_572,_zz_573}}; + assign _zz_557 = _zz_96; + assign _zz_558 = {_zz_574,{_zz_575,_zz_576}}; + assign _zz_559 = {_zz_98,_zz_577}; + assign _zz_560 = 2'b00; + assign _zz_561 = ({_zz_578,_zz_579} != 2'b00); + assign _zz_562 = (_zz_580 != _zz_581); + assign _zz_563 = {_zz_582,{_zz_583,_zz_584}}; + assign _zz_564 = 32'h02400040; + assign _zz_565 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_566 = 32'h0; + assign _zz_567 = (decode_INSTRUCTION & 32'h18002008); + assign _zz_568 = 32'h10002008; + assign _zz_569 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_570 = 32'h00002010; + assign _zz_571 = ((decode_INSTRUCTION & _zz_585) == 32'h00000010); + assign _zz_572 = (_zz_586 == _zz_587); + assign _zz_573 = (_zz_588 == _zz_589); + assign _zz_574 = ((decode_INSTRUCTION & _zz_590) == 32'h00001010); + assign _zz_575 = (_zz_591 == _zz_592); + assign _zz_576 = {_zz_593,{_zz_594,_zz_595}}; + assign _zz_577 = ((decode_INSTRUCTION & _zz_596) == 32'h00000020); + assign _zz_578 = _zz_98; + assign _zz_579 = (_zz_597 == _zz_598); + assign _zz_580 = (_zz_599 == _zz_600); + assign _zz_581 = 1'b0; + assign _zz_582 = (_zz_601 != 1'b0); + assign _zz_583 = (_zz_602 != _zz_603); + assign _zz_584 = {_zz_604,{_zz_605,_zz_606}}; + assign _zz_585 = 32'h00001030; + assign _zz_586 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_587 = 32'h00000020; + assign _zz_588 = (decode_INSTRUCTION & 32'h02002068); + assign _zz_589 = 32'h00002020; + assign _zz_590 = 32'h00001010; + assign _zz_591 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_592 = 32'h00002010; + assign _zz_593 = ((decode_INSTRUCTION & _zz_607) == 32'h00002008); + assign _zz_594 = (_zz_608 == _zz_609); + assign _zz_595 = {_zz_99,_zz_610}; + assign _zz_596 = 32'h00000070; + assign _zz_597 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_598 = 32'h0; + assign _zz_599 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_600 = 32'h00004010; + assign _zz_601 = ((decode_INSTRUCTION & _zz_611) == 32'h00002010); + assign _zz_602 = {_zz_612,{_zz_613,_zz_614}}; + assign _zz_603 = 5'h0; + assign _zz_604 = ({_zz_615,_zz_616} != 2'b00); + assign _zz_605 = (_zz_617 != _zz_618); + assign _zz_606 = {_zz_619,{_zz_620,_zz_621}}; + assign _zz_607 = 32'h00002008; + assign _zz_608 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_609 = 32'h00000010; + assign _zz_610 = ((decode_INSTRUCTION & _zz_622) == 32'h0); + assign _zz_611 = 32'h00006014; + assign _zz_612 = ((decode_INSTRUCTION & _zz_623) == 32'h0); + assign _zz_613 = (_zz_624 == _zz_625); + assign _zz_614 = {_zz_626,{_zz_627,_zz_628}}; + assign _zz_615 = _zz_97; + assign _zz_616 = (_zz_629 == _zz_630); + assign _zz_617 = {_zz_631,{_zz_632,_zz_633}}; + assign _zz_618 = 3'b000; + assign _zz_619 = ({_zz_634,_zz_635} != 3'b000); + assign _zz_620 = (_zz_636 != _zz_637); + assign _zz_621 = (_zz_638 != _zz_639); + assign _zz_622 = 32'h00000028; + assign _zz_623 = 32'h00000044; + assign _zz_624 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_625 = 32'h0; + assign _zz_626 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_627 = ((decode_INSTRUCTION & _zz_640) == 32'h00001000); + assign _zz_628 = _zz_97; + assign _zz_629 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_630 = 32'h0; + assign _zz_631 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_632 = ((decode_INSTRUCTION & _zz_641) == 32'h00002010); + assign _zz_633 = ((decode_INSTRUCTION & _zz_642) == 32'h40000030); + assign _zz_634 = _zz_96; + assign _zz_635 = {_zz_95,(_zz_643 == _zz_644)}; + assign _zz_636 = {_zz_95,(_zz_645 == _zz_646)}; + assign _zz_637 = 2'b00; + assign _zz_638 = ((decode_INSTRUCTION & _zz_647) == 32'h00001008); + assign _zz_639 = 1'b0; + assign _zz_640 = 32'h00005004; + assign _zz_641 = 32'h00002014; + assign _zz_642 = 32'h40000034; + assign _zz_643 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_644 = 32'h00000004; + assign _zz_645 = (decode_INSTRUCTION & 32'h0000004c); + assign _zz_646 = 32'h00000004; + assign _zz_647 = 32'h00005048; + assign _zz_648 = 32'h0; always @ (posedge clk) begin - if(_zz_9_) begin - _zz_11_ <= ways_0_datas[_zz_8_]; + if(_zz_432) begin + _zz_222 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; + always @ (posedge clk) begin + if(_zz_433) begin + _zz_223 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; + always @ (posedge clk) begin + if(_zz_43) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_187 ), //i + .io_cpu_prefetch_isValid (_zz_188 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_189 ), //i + .io_cpu_fetch_isStuck (_zz_190 ), //i + .io_cpu_fetch_isRemoved (_zz_191 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_192 ), //i + .io_cpu_decode_isStuck (_zz_193 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_3_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_194 ), //i + .io_cpu_fill_valid (_zz_195 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_196 ), //i + .io_cpu_execute_address (_zz_197[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (_zz_198 ), //i + .io_cpu_execute_args_data (_zz_199[31:0] ), //i + .io_cpu_execute_args_size (_zz_200[1:0] ), //i + .io_cpu_execute_args_isLrsc (_zz_201 ), //i + .io_cpu_execute_args_isAmo (_zz_202 ), //i + .io_cpu_execute_args_amoCtrl_swap (_zz_203 ), //i + .io_cpu_execute_args_amoCtrl_alu (_zz_204[2:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_205 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_206[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_207 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i + .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i + .io_cpu_writeBack_isValid (_zz_208 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_209 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_210[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_211 ), //i + .io_cpu_writeBack_fence_SR (_zz_212 ), //i + .io_cpu_writeBack_fence_SO (_zz_213 ), //i + .io_cpu_writeBack_fence_SI (_zz_214 ), //i + .io_cpu_writeBack_fence_PW (_zz_215 ), //i + .io_cpu_writeBack_fence_PR (_zz_216 ), //i + .io_cpu_writeBack_fence_PO (_zz_217 ), //i + .io_cpu_writeBack_fence_PI (_zz_218 ), //i + .io_cpu_writeBack_fence_FM (_zz_219[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_220 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_221 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_434) + 2'b00 : begin + _zz_224 = DBusCachedPlugin_redoBranch_payload; end - end - end - - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_12_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; - end - end - - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; - end + 2'b01 : begin + _zz_224 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_224 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_224 = CsrPlugin_redoInterface_payload; + end + endcase end - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_10_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_11_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; + always @(*) begin + case(_zz_83) + 2'b00 : begin + _zz_225 = MmuPlugin_ports_0_cache_0_valid; + _zz_226 = MmuPlugin_ports_0_cache_0_exception; + _zz_227 = MmuPlugin_ports_0_cache_0_superPage; + _zz_228 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_229 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_230 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_231 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_232 = MmuPlugin_ports_0_cache_0_allowRead; + _zz_233 = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_234 = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_235 = MmuPlugin_ports_0_cache_0_allowUser; end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; + 2'b01 : begin + _zz_225 = MmuPlugin_ports_0_cache_1_valid; + _zz_226 = MmuPlugin_ports_0_cache_1_exception; + _zz_227 = MmuPlugin_ports_0_cache_1_superPage; + _zz_228 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_229 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_230 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_231 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_232 = MmuPlugin_ports_0_cache_1_allowRead; + _zz_233 = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_234 = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_235 = MmuPlugin_ports_0_cache_1_allowUser; end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; + 2'b10 : begin + _zz_225 = MmuPlugin_ports_0_cache_2_valid; + _zz_226 = MmuPlugin_ports_0_cache_2_exception; + _zz_227 = MmuPlugin_ports_0_cache_2_superPage; + _zz_228 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_229 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_230 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_231 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_232 = MmuPlugin_ports_0_cache_2_allowRead; + _zz_233 = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_234 = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_235 = MmuPlugin_ports_0_cache_2_allowUser; end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; + default : begin + _zz_225 = MmuPlugin_ports_0_cache_3_valid; + _zz_226 = MmuPlugin_ports_0_cache_3_exception; + _zz_227 = MmuPlugin_ports_0_cache_3_superPage; + _zz_228 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_229 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_230 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_231 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_232 = MmuPlugin_ports_0_cache_3_allowRead; + _zz_233 = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_234 = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_235 = MmuPlugin_ports_0_cache_3_allowUser; end - if(_zz_13_)begin - lineLoader_flushPending <= 1'b0; + endcase + end + + always @(*) begin + case(_zz_87) + 2'b00 : begin + _zz_236 = MmuPlugin_ports_1_cache_0_valid; + _zz_237 = MmuPlugin_ports_1_cache_0_exception; + _zz_238 = MmuPlugin_ports_1_cache_0_superPage; + _zz_239 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_240 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_241 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_242 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_243 = MmuPlugin_ports_1_cache_0_allowRead; + _zz_244 = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_245 = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_246 = MmuPlugin_ports_1_cache_0_allowUser; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; + 2'b01 : begin + _zz_236 = MmuPlugin_ports_1_cache_1_valid; + _zz_237 = MmuPlugin_ports_1_cache_1_exception; + _zz_238 = MmuPlugin_ports_1_cache_1_superPage; + _zz_239 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_240 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_241 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_242 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_243 = MmuPlugin_ports_1_cache_1_allowRead; + _zz_244 = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_245 = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_246 = MmuPlugin_ports_1_cache_1_allowUser; end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; + 2'b10 : begin + _zz_236 = MmuPlugin_ports_1_cache_2_valid; + _zz_237 = MmuPlugin_ports_1_cache_2_exception; + _zz_238 = MmuPlugin_ports_1_cache_2_superPage; + _zz_239 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_240 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_241 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_242 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_243 = MmuPlugin_ports_1_cache_2_allowRead; + _zz_244 = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_245 = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_246 = MmuPlugin_ports_1_cache_2_allowUser; end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end + default : begin + _zz_236 = MmuPlugin_ports_1_cache_3_valid; + _zz_237 = MmuPlugin_ports_1_cache_3_exception; + _zz_238 = MmuPlugin_ports_1_cache_3_superPage; + _zz_239 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_240 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_241 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_242 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_243 = MmuPlugin_ports_1_cache_3_allowRead; + _zz_244 = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_245 = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_246 = MmuPlugin_ports_1_cache_3_allowUser; end - end - end - - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_12_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (8'b00000001)); - end - _zz_3_ <= lineLoader_flushCounter[7]; - if(_zz_13_)begin - lineLoader_flushCounter <= (8'b00000000); - end - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_error <= fetchStage_hit_error; - end + endcase end -endmodule - -module DataCache ( - input io_cpu_execute_isValid, - input [31:0] io_cpu_execute_address, - input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, - input [1:0] io_cpu_execute_args_size, - input io_cpu_execute_args_isLrsc, - input io_cpu_execute_args_isAmo, - input io_cpu_execute_args_amoCtrl_swap, - input [2:0] io_cpu_execute_args_amoCtrl_alu, - input io_cpu_memory_isValid, - input io_cpu_memory_isStuck, - input io_cpu_memory_isRemoved, - output io_cpu_memory_isWrite, - input [31:0] io_cpu_memory_address, - output io_cpu_memory_mmuBus_cmd_isValid, - output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, - output io_cpu_memory_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, - input io_cpu_memory_mmuBus_rsp_isIoAccess, - input io_cpu_memory_mmuBus_rsp_allowRead, - input io_cpu_memory_mmuBus_rsp_allowWrite, - input io_cpu_memory_mmuBus_rsp_allowExecute, - input io_cpu_memory_mmuBus_rsp_exception, - input io_cpu_memory_mmuBus_rsp_refilling, - output io_cpu_memory_mmuBus_end, - input io_cpu_memory_mmuBus_busy, - input io_cpu_writeBack_isValid, - input io_cpu_writeBack_isStuck, - input io_cpu_writeBack_isUser, - output reg io_cpu_writeBack_haltIt, - output io_cpu_writeBack_isWrite, - output reg [31:0] io_cpu_writeBack_data, - input [31:0] io_cpu_writeBack_address, - output io_cpu_writeBack_mmuException, - output io_cpu_writeBack_unalignedAccess, - output reg io_cpu_writeBack_accessError, - input io_cpu_writeBack_clearLrsc, - output reg io_cpu_redo, - input io_cpu_flush_valid, - output reg io_cpu_flush_ready, - output reg io_mem_cmd_valid, - input io_mem_cmd_ready, - output reg io_mem_cmd_payload_wr, - output reg [31:0] io_mem_cmd_payload_address, - output [31:0] io_mem_cmd_payload_data, - output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, - output reg io_mem_cmd_payload_last, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [21:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire _zz_16_; - wire _zz_17_; - wire _zz_18_; - wire _zz_19_; - wire _zz_20_; - wire _zz_21_; - wire [2:0] _zz_22_; - wire [0:0] _zz_23_; - wire [0:0] _zz_24_; - wire [31:0] _zz_25_; - wire [31:0] _zz_26_; - wire [31:0] _zz_27_; - wire [31:0] _zz_28_; - wire [1:0] _zz_29_; - wire [31:0] _zz_30_; - wire [1:0] _zz_31_; - wire [1:0] _zz_32_; - wire [0:0] _zz_33_; - wire [0:0] _zz_34_; - wire [2:0] _zz_35_; - wire [1:0] _zz_36_; - wire [21:0] _zz_37_; - reg _zz_1_; - reg _zz_2_; - wire haltCpu; - reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; - reg tagsWriteCmd_valid; - reg [0:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; - reg tagsWriteCmd_payload_data_valid; - reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; - reg tagsWriteLastCmd_valid; - reg [0:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; - reg tagsWriteLastCmd_payload_data_valid; - reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; - reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; - reg dataWriteCmd_valid; - reg [0:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; - reg [31:0] dataWriteCmd_payload_data; - reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3_; - wire ways_0_tagsReadRsp_valid; - wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4_; - wire _zz_5_; - wire [31:0] ways_0_dataReadRsp; - reg [3:0] _zz_6_; - wire [3:0] stage0_mask; - wire [0:0] stage0_colisions; - reg stageA_request_wr; - reg [31:0] stageA_request_data; - reg [1:0] stageA_request_size; - reg stageA_request_isLrsc; - reg stageA_request_isAmo; - reg stageA_request_amoCtrl_swap; - reg [2:0] stageA_request_amoCtrl_alu; - reg [3:0] stageA_mask; - wire stageA_wayHits_0; - reg [0:0] stage0_colisions_regNextWhen; - wire [0:0] _zz_7_; - wire [0:0] stageA_colisions; - reg stageB_request_wr; - reg [31:0] stageB_request_data; - reg [1:0] stageB_request_size; - reg stageB_request_isLrsc; - reg stageB_isAmo; - reg stageB_request_amoCtrl_swap; - reg [2:0] stageB_request_amoCtrl_alu; - reg stageB_mmuRspFreeze; - reg [31:0] stageB_mmuRsp_physicalAddress; - reg stageB_mmuRsp_isIoAccess; - reg stageB_mmuRsp_allowRead; - reg stageB_mmuRsp_allowWrite; - reg stageB_mmuRsp_allowExecute; - reg stageB_mmuRsp_exception; - reg stageB_mmuRsp_refilling; - reg stageB_tagsReadRsp_0_valid; - reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg [31:0] stageB_dataReadRsp_0; - wire [0:0] _zz_8_; - reg [0:0] stageB_waysHits; - wire stageB_waysHit; - wire [31:0] stageB_dataMux; - reg [3:0] stageB_mask; - reg [0:0] stageB_colisions; - reg stageB_loaderValid; - reg stageB_flusher_valid; - reg stageB_lrsc_reserved; - reg [31:0] stageB_requestDataBypass; - wire stageB_amo_compare; - wire stageB_amo_unsigned; - wire [31:0] stageB_amo_addSub; - wire stageB_amo_less; - wire stageB_amo_selectRf; - reg [31:0] stageB_amo_result; - reg stageB_amo_resultRegValid; - reg [31:0] stageB_amo_resultReg; - reg stageB_memCmdSent; - wire [0:0] _zz_9_; - reg loader_valid; - reg loader_counter_willIncrement; - wire loader_counter_willClear; - reg [2:0] loader_counter_valueNext; - reg [2:0] loader_counter_value; - wire loader_counter_willOverflowIfInc; - wire loader_counter_willOverflow; - reg [0:0] loader_waysAllocator; - reg loader_error; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_38_; - reg [7:0] _zz_39_; - reg [7:0] _zz_40_; - reg [7:0] _zz_41_; - assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13_ = (((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); - assign _zz_15_ = (! stageB_amo_resultRegValid); - assign _zz_16_ = (stageB_request_isLrsc && (! stageB_lrsc_reserved)); - assign _zz_17_ = (loader_valid && io_mem_rsp_valid); - assign _zz_18_ = (stageB_request_isLrsc && (! stageB_lrsc_reserved)); - assign _zz_19_ = ((((io_cpu_flush_valid && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - assign _zz_20_ = (((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))); - assign _zz_21_ = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); - assign _zz_22_ = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,(2'b00)}); - assign _zz_23_ = _zz_4_[0 : 0]; - assign _zz_24_ = _zz_4_[1 : 1]; - assign _zz_25_ = ($signed(_zz_26_) + $signed(_zz_30_)); - assign _zz_26_ = ($signed(_zz_27_) + $signed(_zz_28_)); - assign _zz_27_ = stageB_request_data; - assign _zz_28_ = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux); - assign _zz_29_ = (stageB_amo_compare ? _zz_31_ : _zz_32_); - assign _zz_30_ = {{30{_zz_29_[1]}}, _zz_29_}; - assign _zz_31_ = (2'b01); - assign _zz_32_ = (2'b00); - assign _zz_33_ = (! stageB_lrsc_reserved); - assign _zz_34_ = loader_counter_willIncrement; - assign _zz_35_ = {2'd0, _zz_34_}; - assign _zz_36_ = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_37_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_37_; - end + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_3_) begin - _zz_10_ <= ways_0_tags[tagsReadCmd_payload]; - end + always @(*) begin + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; + endcase end - - always @ (*) begin - _zz_11_ = {_zz_41_, _zz_40_, _zz_39_, _zz_38_}; + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase end - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_1_) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_1_) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_1_) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_1_) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase end - - always @ (posedge clk) begin - if(_zz_5_) begin - _zz_38_ <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_39_ <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_40_ <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_41_ <= ways_0_data_symbol3[dataReadCmd_payload]; - end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase end - - always @ (*) begin - _zz_1_ = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_1_ = 1'b1; - end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase end - - always @ (*) begin - _zz_2_ = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_2_ = 1'b1; - end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase end - - assign haltCpu = 1'b0; - assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4_ = _zz_10_; - assign ways_0_tagsReadRsp_valid = _zz_23_[0]; - assign ways_0_tagsReadRsp_error = _zz_24_[0]; - assign ways_0_tagsReadRsp_address = _zz_4_[21 : 2]; - assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRsp = _zz_11_; - always @ (*) begin - tagsReadCmd_valid = 1'b0; - if(_zz_12_)begin - tagsReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase end - - always @ (*) begin - tagsReadCmd_payload = (7'bxxxxxxx); - if(_zz_12_)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; - end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_valid = 1'b0; - if(_zz_12_)begin - dataReadCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; + endcase end - - always @ (*) begin - dataReadCmd_payload = (10'bxxxxxxxxxx); - if(_zz_12_)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; - end + always @(*) begin + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; + endcase end - - always @ (*) begin - tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; - end - if(_zz_13_)begin - tagsWriteCmd_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_10) + `BranchCtrlEnum_defaultEncoding_INC : _zz_10_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_10_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_10_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_10_string = "JALR"; + default : _zz_10_string = "????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_way = (1'bx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = (1'b1); - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_address = (7'bxxxxxxx); - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; - end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_data_valid = 1'b0; - end - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_valid = 1'b1; - end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_error = 1'bx; - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); - end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase end - - always @ (*) begin - tagsWriteCmd_payload_data_address = (20'bxxxxxxxxxxxxxxxxxxxx); - if(loader_counter_willOverflow)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; - end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase end - - always @ (*) begin - dataWriteCmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if((stageB_request_wr && stageB_waysHit))begin - dataWriteCmd_valid = 1'b1; - end - if(stageB_isAmo)begin - if(_zz_15_)begin - dataWriteCmd_valid = 1'b0; - end - end - if(_zz_16_)begin - dataWriteCmd_valid = 1'b0; - end - end - end - end - if(_zz_13_)begin - dataWriteCmd_valid = 1'b0; - end - if(_zz_17_)begin - dataWriteCmd_valid = 1'b1; - end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_way = (1'bx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_way = stageB_waysHits; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_way = loader_waysAllocator; - end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_address = (10'bxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; - end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_data = stageB_requestDataBypass; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_data = io_mem_rsp_payload_data; - end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase end - - always @ (*) begin - dataWriteCmd_payload_mask = (4'bxxxx); - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - dataWriteCmd_payload_mask = stageB_mask; - end - end - end - if(_zz_17_)begin - dataWriteCmd_payload_mask = (4'b1111); - end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase end - - always @ (*) begin - case(io_cpu_execute_args_size) - 2'b00 : begin - _zz_6_ = (4'b0001); - end - 2'b01 : begin - _zz_6_ = (4'b0011); - end - default : begin - _zz_6_ = (4'b1111); - end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; endcase end - - assign stage0_mask = (_zz_6_ <<< io_cpu_execute_address[1 : 0]); - assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; - assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; - assign io_cpu_memory_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); - assign io_cpu_memory_isWrite = stageA_request_wr; - assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); - assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); - always @ (*) begin - stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin - stageB_mmuRspFreeze = 1'b1; - end + always @(*) begin + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; + endcase end - - assign _zz_8_[0] = stageA_wayHits_0; - assign stageB_waysHit = (stageB_waysHits != (1'b0)); - assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin - stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - if(io_mem_cmd_ready)begin - stageB_loaderValid = 1'b1; - end - end - end - end - if(_zz_13_)begin - stageB_loaderValid = 1'b0; - end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; + endcase end - - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin - io_cpu_writeBack_haltIt = 1'b0; - end - if(_zz_18_)begin - io_cpu_writeBack_haltIt = 1'b0; - end - end else begin - if(_zz_14_)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin - io_cpu_writeBack_haltIt = 1'b0; - end - if(stageB_isAmo)begin - if(_zz_15_)begin - io_cpu_writeBack_haltIt = 1'b1; - end - end - if(_zz_16_)begin - io_cpu_writeBack_haltIt = 1'b0; - end - end - end - end - if(_zz_13_)begin - io_cpu_writeBack_haltIt = 1'b0; - end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase end - - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(_zz_19_)begin - io_cpu_flush_ready = 1'b1; - end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase end - - always @ (*) begin - stageB_requestDataBypass = stageB_request_data; - if(stageB_isAmo)begin - stageB_requestDataBypass = stageB_amo_resultReg; - end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase end - - assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; - assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == (2'b11)); - assign stageB_amo_addSub = _zz_25_; - assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31])); - assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); - always @ (*) begin - case(_zz_22_) - 3'b000 : begin - stageB_amo_result = stageB_amo_addSub; - end - 3'b001 : begin - stageB_amo_result = (stageB_request_data ^ stageB_dataMux); - end - 3'b010 : begin - stageB_amo_result = (stageB_request_data | stageB_dataMux); - end - 3'b011 : begin - stageB_amo_result = (stageB_request_data & stageB_dataMux); - end - default : begin - stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux); - end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; endcase end - - always @ (*) begin - io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(_zz_14_)begin - if(_zz_20_)begin - io_cpu_redo = 1'b1; - end - end - end - end - if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin - io_cpu_redo = 1'b1; - end - if(loader_valid)begin - io_cpu_redo = 1'b1; - end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase end - - always @ (*) begin - io_cpu_writeBack_accessError = 1'b0; - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); - end else begin - io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); - end - end - - assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && ((stageB_mmuRsp_exception || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo)))); - assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); - assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin - io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_valid = (! stageB_memCmdSent); - if(_zz_18_)begin - io_mem_cmd_valid = 1'b0; - end - end else begin - if(_zz_14_)begin - if(stageB_request_wr)begin - io_mem_cmd_valid = 1'b1; - end - if(stageB_isAmo)begin - if(_zz_15_)begin - io_mem_cmd_valid = 1'b0; - end - end - if(_zz_20_)begin - io_mem_cmd_valid = 1'b0; - end - if(_zz_16_)begin - io_mem_cmd_valid = 1'b0; - end - end else begin - if((! stageB_memCmdSent))begin - io_mem_cmd_valid = 1'b1; - end - end - end - end - if(_zz_13_)begin - io_mem_cmd_valid = 1'b0; - end - end - - always @ (*) begin - io_mem_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],(5'b00000)}; - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = (3'bxxx); - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_length = (3'b000); - end else begin - io_mem_cmd_payload_length = (3'b111); - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_last = 1'bx; - if(io_cpu_writeBack_isValid)begin - if(stageB_mmuRsp_isIoAccess)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - if(_zz_14_)begin - io_mem_cmd_payload_last = 1'b1; - end else begin - io_mem_cmd_payload_last = 1'b1; - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_mmuRsp_isIoAccess) begin - if(! _zz_14_) begin - io_mem_cmd_payload_wr = 1'b0; - end - end - end - end - - assign io_mem_cmd_payload_mask = stageB_mask; - assign io_mem_cmd_payload_data = stageB_requestDataBypass; - always @ (*) begin - if(stageB_mmuRsp_isIoAccess)begin - io_cpu_writeBack_data = io_mem_rsp_payload_data; - end else begin - io_cpu_writeBack_data = stageB_dataMux; - end - if((stageB_request_isLrsc && stageB_request_wr))begin - io_cpu_writeBack_data = {31'd0, _zz_33_}; - end - end - - assign _zz_9_[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin - loader_counter_willIncrement = 1'b0; - if(_zz_17_)begin - loader_counter_willIncrement = 1'b1; - end - end - - assign loader_counter_willClear = 1'b0; - assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); - assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_35_); - if(loader_counter_willClear)begin - loader_counter_valueNext = (3'b000); - end - end - - always @ (posedge clk) begin - tagsWriteLastCmd_valid <= tagsWriteCmd_valid; - tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; - tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; - tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; - tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; - tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin - stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; - stageA_request_size <= io_cpu_execute_args_size; - stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; - stageA_request_isAmo <= io_cpu_execute_args_isAmo; - stageA_request_amoCtrl_swap <= io_cpu_execute_args_amoCtrl_swap; - stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; - end - if((! io_cpu_memory_isStuck))begin - stageA_mask <= stage0_mask; - end - if((! io_cpu_memory_isStuck))begin - stage0_colisions_regNextWhen <= stage0_colisions; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; - stageB_request_size <= stageA_request_size; - stageB_request_isLrsc <= stageA_request_isLrsc; - stageB_isAmo <= stageA_request_isAmo; - stageB_request_amoCtrl_swap <= stageA_request_amoCtrl_swap; - stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; - end - if(_zz_21_)begin - stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; - stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; - stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; - stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; - stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; - stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; - stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; - stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_0 <= ways_0_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_waysHits <= _zz_8_; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_mask <= stageA_mask; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_colisions <= stageA_colisions; - end - stageB_amo_resultRegValid <= 1'b1; - if((! io_cpu_writeBack_isStuck))begin - stageB_amo_resultRegValid <= 1'b0; - end - stageB_amo_resultReg <= stageB_amo_result; - if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("ERROR writeBack stuck by another plugin is not allowed"); - end - end - - always @ (posedge clk) begin - if(reset) begin - stageB_flusher_valid <= 1'b1; - stageB_mmuRsp_physicalAddress <= (32'b00000000000000000000000000000000); - stageB_lrsc_reserved <= 1'b0; - stageB_memCmdSent <= 1'b0; - loader_valid <= 1'b0; - loader_counter_value <= (3'b000); - loader_waysAllocator <= (1'b1); - loader_error <= 1'b0; - end else begin - if(_zz_21_)begin - stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; - end - if(stageB_flusher_valid)begin - if((stageB_mmuRsp_physicalAddress[11 : 5] != (7'b1111111)))begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + (7'b0000001)); - end else begin - stageB_flusher_valid <= 1'b0; - end - end - if(_zz_19_)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (7'b0000000); - stageB_flusher_valid <= 1'b1; - end - if(((((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && (! io_cpu_redo)) && stageB_request_isLrsc) && (! stageB_request_wr)))begin - stageB_lrsc_reserved <= 1'b1; - end - if(io_cpu_writeBack_clearLrsc)begin - stageB_lrsc_reserved <= 1'b0; - end - if(io_mem_cmd_ready)begin - stageB_memCmdSent <= 1'b1; - end - if((! io_cpu_writeBack_isStuck))begin - stageB_memCmdSent <= 1'b0; - end - if(stageB_loaderValid)begin - loader_valid <= 1'b1; - end - loader_counter_value <= loader_counter_valueNext; - if(_zz_17_)begin - loader_error <= (loader_error || io_mem_rsp_payload_error); - end - if(loader_counter_willOverflow)begin - loader_valid <= 1'b0; - loader_error <= 1'b0; - end - if((! loader_valid))begin - loader_waysAllocator <= _zz_36_[0:0]; - end - end - end - -endmodule - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset); - wire _zz_220_; - wire _zz_221_; - wire _zz_222_; - wire _zz_223_; - wire [31:0] _zz_224_; - wire _zz_225_; - wire _zz_226_; - wire _zz_227_; - reg _zz_228_; - reg _zz_229_; - reg [31:0] _zz_230_; - reg _zz_231_; - reg [31:0] _zz_232_; - reg [1:0] _zz_233_; - reg _zz_234_; - reg _zz_235_; - wire _zz_236_; - wire [2:0] _zz_237_; - reg _zz_238_; - wire [31:0] _zz_239_; - reg _zz_240_; - reg _zz_241_; - wire _zz_242_; - wire [31:0] _zz_243_; - wire _zz_244_; - wire _zz_245_; - reg [31:0] _zz_246_; - reg [31:0] _zz_247_; - reg [31:0] _zz_248_; - reg _zz_249_; - reg _zz_250_; - reg _zz_251_; - reg [9:0] _zz_252_; - reg [9:0] _zz_253_; - reg [9:0] _zz_254_; - reg [9:0] _zz_255_; - reg _zz_256_; - reg _zz_257_; - reg _zz_258_; - reg _zz_259_; - reg _zz_260_; - reg _zz_261_; - reg _zz_262_; - reg [9:0] _zz_263_; - reg [9:0] _zz_264_; - reg [9:0] _zz_265_; - reg [9:0] _zz_266_; - reg _zz_267_; - reg _zz_268_; - reg _zz_269_; - reg _zz_270_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire dataCache_1__io_cpu_memory_isWrite; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; - wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; - wire dataCache_1__io_cpu_memory_mmuBus_end; - wire dataCache_1__io_cpu_writeBack_haltIt; - wire [31:0] dataCache_1__io_cpu_writeBack_data; - wire dataCache_1__io_cpu_writeBack_mmuException; - wire dataCache_1__io_cpu_writeBack_unalignedAccess; - wire dataCache_1__io_cpu_writeBack_accessError; - wire dataCache_1__io_cpu_writeBack_isWrite; - wire dataCache_1__io_cpu_flush_ready; - wire dataCache_1__io_cpu_redo; - wire dataCache_1__io_mem_cmd_valid; - wire dataCache_1__io_mem_cmd_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_payload_length; - wire dataCache_1__io_mem_cmd_payload_last; - wire _zz_271_; - wire _zz_272_; - wire _zz_273_; - wire _zz_274_; - wire _zz_275_; - wire _zz_276_; - wire _zz_277_; - wire _zz_278_; - wire _zz_279_; - wire _zz_280_; - wire _zz_281_; - wire _zz_282_; - wire _zz_283_; - wire _zz_284_; - wire _zz_285_; - wire _zz_286_; - wire _zz_287_; - wire [1:0] _zz_288_; - wire _zz_289_; - wire _zz_290_; - wire _zz_291_; - wire _zz_292_; - wire _zz_293_; - wire _zz_294_; - wire _zz_295_; - wire _zz_296_; - wire _zz_297_; - wire _zz_298_; - wire _zz_299_; - wire _zz_300_; - wire _zz_301_; - wire _zz_302_; - wire _zz_303_; - wire _zz_304_; - wire _zz_305_; - wire _zz_306_; - wire _zz_307_; - wire _zz_308_; - wire _zz_309_; - wire _zz_310_; - wire _zz_311_; - wire _zz_312_; - wire _zz_313_; - wire _zz_314_; - wire _zz_315_; - wire _zz_316_; - wire _zz_317_; - wire _zz_318_; - wire _zz_319_; - wire _zz_320_; - wire _zz_321_; - wire _zz_322_; - wire _zz_323_; - wire _zz_324_; - wire _zz_325_; - wire _zz_326_; - wire _zz_327_; - wire [1:0] _zz_328_; - wire _zz_329_; - wire [3:0] _zz_330_; - wire [2:0] _zz_331_; - wire [31:0] _zz_332_; - wire [2:0] _zz_333_; - wire [2:0] _zz_334_; - wire [0:0] _zz_335_; - wire [1:0] _zz_336_; - wire [0:0] _zz_337_; - wire [1:0] _zz_338_; - wire [0:0] _zz_339_; - wire [0:0] _zz_340_; - wire [0:0] _zz_341_; - wire [0:0] _zz_342_; - wire [0:0] _zz_343_; - wire [0:0] _zz_344_; - wire [0:0] _zz_345_; - wire [0:0] _zz_346_; - wire [0:0] _zz_347_; - wire [0:0] _zz_348_; - wire [0:0] _zz_349_; - wire [0:0] _zz_350_; - wire [0:0] _zz_351_; - wire [0:0] _zz_352_; - wire [0:0] _zz_353_; - wire [0:0] _zz_354_; - wire [0:0] _zz_355_; - wire [0:0] _zz_356_; - wire [0:0] _zz_357_; - wire [0:0] _zz_358_; - wire [0:0] _zz_359_; - wire [0:0] _zz_360_; - wire [0:0] _zz_361_; - wire [0:0] _zz_362_; - wire [0:0] _zz_363_; - wire [0:0] _zz_364_; - wire [0:0] _zz_365_; - wire [0:0] _zz_366_; - wire [0:0] _zz_367_; - wire [2:0] _zz_368_; - wire [4:0] _zz_369_; - wire [11:0] _zz_370_; - wire [11:0] _zz_371_; - wire [31:0] _zz_372_; - wire [31:0] _zz_373_; - wire [31:0] _zz_374_; - wire [31:0] _zz_375_; - wire [31:0] _zz_376_; - wire [31:0] _zz_377_; - wire [31:0] _zz_378_; - wire [32:0] _zz_379_; - wire [31:0] _zz_380_; - wire [32:0] _zz_381_; - wire [19:0] _zz_382_; - wire [11:0] _zz_383_; - wire [11:0] _zz_384_; - wire [1:0] _zz_385_; - wire [1:0] _zz_386_; - wire [0:0] _zz_387_; - wire [5:0] _zz_388_; - wire [33:0] _zz_389_; - wire [32:0] _zz_390_; - wire [33:0] _zz_391_; - wire [32:0] _zz_392_; - wire [33:0] _zz_393_; - wire [32:0] _zz_394_; - wire [0:0] _zz_395_; - wire [5:0] _zz_396_; - wire [32:0] _zz_397_; - wire [32:0] _zz_398_; - wire [31:0] _zz_399_; - wire [31:0] _zz_400_; - wire [32:0] _zz_401_; - wire [32:0] _zz_402_; - wire [32:0] _zz_403_; - wire [0:0] _zz_404_; - wire [32:0] _zz_405_; - wire [0:0] _zz_406_; - wire [32:0] _zz_407_; - wire [0:0] _zz_408_; - wire [31:0] _zz_409_; - wire [0:0] _zz_410_; - wire [0:0] _zz_411_; - wire [0:0] _zz_412_; - wire [0:0] _zz_413_; - wire [0:0] _zz_414_; - wire [0:0] _zz_415_; - wire [0:0] _zz_416_; - wire [0:0] _zz_417_; - wire [0:0] _zz_418_; - wire [0:0] _zz_419_; - wire [0:0] _zz_420_; - wire [0:0] _zz_421_; - wire [0:0] _zz_422_; - wire [0:0] _zz_423_; - wire [0:0] _zz_424_; - wire [0:0] _zz_425_; - wire [0:0] _zz_426_; - wire [0:0] _zz_427_; - wire [0:0] _zz_428_; - wire [0:0] _zz_429_; - wire [0:0] _zz_430_; - wire [0:0] _zz_431_; - wire [0:0] _zz_432_; - wire [0:0] _zz_433_; - wire [0:0] _zz_434_; - wire [0:0] _zz_435_; - wire [0:0] _zz_436_; - wire [0:0] _zz_437_; - wire [0:0] _zz_438_; - wire [0:0] _zz_439_; - wire [0:0] _zz_440_; - wire [0:0] _zz_441_; - wire [0:0] _zz_442_; - wire [0:0] _zz_443_; - wire [0:0] _zz_444_; - wire [0:0] _zz_445_; - wire [0:0] _zz_446_; - wire [0:0] _zz_447_; - wire [0:0] _zz_448_; - wire [0:0] _zz_449_; - wire [0:0] _zz_450_; - wire [0:0] _zz_451_; - wire [0:0] _zz_452_; - wire [0:0] _zz_453_; - wire [0:0] _zz_454_; - wire [26:0] _zz_455_; - wire _zz_456_; - wire _zz_457_; - wire [1:0] _zz_458_; - wire [31:0] _zz_459_; - wire _zz_460_; - wire _zz_461_; - wire _zz_462_; - wire [2:0] _zz_463_; - wire [2:0] _zz_464_; - wire _zz_465_; - wire [0:0] _zz_466_; - wire [28:0] _zz_467_; - wire _zz_468_; - wire _zz_469_; - wire _zz_470_; - wire [1:0] _zz_471_; - wire [1:0] _zz_472_; - wire _zz_473_; - wire [0:0] _zz_474_; - wire [25:0] _zz_475_; - wire [31:0] _zz_476_; - wire [31:0] _zz_477_; - wire [31:0] _zz_478_; - wire [31:0] _zz_479_; - wire _zz_480_; - wire [0:0] _zz_481_; - wire [0:0] _zz_482_; - wire _zz_483_; - wire [0:0] _zz_484_; - wire [0:0] _zz_485_; - wire _zz_486_; - wire [0:0] _zz_487_; - wire [22:0] _zz_488_; - wire [31:0] _zz_489_; - wire [31:0] _zz_490_; - wire [31:0] _zz_491_; - wire [0:0] _zz_492_; - wire [0:0] _zz_493_; - wire [0:0] _zz_494_; - wire [1:0] _zz_495_; - wire [0:0] _zz_496_; - wire [0:0] _zz_497_; - wire _zz_498_; - wire [0:0] _zz_499_; - wire [19:0] _zz_500_; - wire [31:0] _zz_501_; - wire [31:0] _zz_502_; - wire [31:0] _zz_503_; - wire [31:0] _zz_504_; - wire [31:0] _zz_505_; - wire [31:0] _zz_506_; - wire [31:0] _zz_507_; - wire [31:0] _zz_508_; - wire [0:0] _zz_509_; - wire [5:0] _zz_510_; - wire [1:0] _zz_511_; - wire [1:0] _zz_512_; - wire _zz_513_; - wire [0:0] _zz_514_; - wire [16:0] _zz_515_; - wire [31:0] _zz_516_; - wire [31:0] _zz_517_; - wire _zz_518_; - wire [0:0] _zz_519_; - wire [2:0] _zz_520_; - wire [31:0] _zz_521_; - wire [31:0] _zz_522_; - wire [31:0] _zz_523_; - wire [31:0] _zz_524_; - wire [31:0] _zz_525_; - wire [31:0] _zz_526_; - wire [0:0] _zz_527_; - wire [0:0] _zz_528_; - wire _zz_529_; - wire [0:0] _zz_530_; - wire [13:0] _zz_531_; - wire [31:0] _zz_532_; - wire [31:0] _zz_533_; - wire [31:0] _zz_534_; - wire _zz_535_; - wire [31:0] _zz_536_; - wire _zz_537_; - wire [0:0] _zz_538_; - wire [0:0] _zz_539_; - wire [1:0] _zz_540_; - wire [1:0] _zz_541_; - wire _zz_542_; - wire [0:0] _zz_543_; - wire [10:0] _zz_544_; - wire [31:0] _zz_545_; - wire [31:0] _zz_546_; - wire [31:0] _zz_547_; - wire [31:0] _zz_548_; - wire [31:0] _zz_549_; - wire [0:0] _zz_550_; - wire [4:0] _zz_551_; - wire [4:0] _zz_552_; - wire [4:0] _zz_553_; - wire _zz_554_; - wire [0:0] _zz_555_; - wire [7:0] _zz_556_; - wire [31:0] _zz_557_; - wire [31:0] _zz_558_; - wire [31:0] _zz_559_; - wire _zz_560_; - wire [0:0] _zz_561_; - wire [1:0] _zz_562_; - wire _zz_563_; - wire [0:0] _zz_564_; - wire [1:0] _zz_565_; - wire [31:0] _zz_566_; - wire [31:0] _zz_567_; - wire _zz_568_; - wire [1:0] _zz_569_; - wire [1:0] _zz_570_; - wire _zz_571_; - wire [0:0] _zz_572_; - wire [4:0] _zz_573_; - wire [31:0] _zz_574_; - wire [31:0] _zz_575_; - wire [31:0] _zz_576_; - wire _zz_577_; - wire _zz_578_; - wire [31:0] _zz_579_; - wire [31:0] _zz_580_; - wire [31:0] _zz_581_; - wire _zz_582_; - wire _zz_583_; - wire [31:0] _zz_584_; - wire [0:0] _zz_585_; - wire [1:0] _zz_586_; - wire [1:0] _zz_587_; - wire [1:0] _zz_588_; - wire _zz_589_; - wire [0:0] _zz_590_; - wire [2:0] _zz_591_; - wire [31:0] _zz_592_; - wire [31:0] _zz_593_; - wire [31:0] _zz_594_; - wire [31:0] _zz_595_; - wire [31:0] _zz_596_; - wire [31:0] _zz_597_; - wire _zz_598_; - wire _zz_599_; - wire _zz_600_; - wire _zz_601_; - wire [4:0] _zz_602_; - wire [4:0] _zz_603_; - wire _zz_604_; - wire [0:0] _zz_605_; - wire [0:0] _zz_606_; - wire [31:0] _zz_607_; - wire [31:0] _zz_608_; - wire _zz_609_; - wire [0:0] _zz_610_; - wire [1:0] _zz_611_; - wire _zz_612_; - wire [0:0] _zz_613_; - wire [1:0] _zz_614_; - wire _zz_615_; - wire _zz_616_; - wire [31:0] _zz_617_; - wire [31:0] _zz_618_; - wire [31:0] _zz_619_; - wire [31:0] _zz_620_; - wire [31:0] _zz_621_; - wire [31:0] _zz_622_; - wire [31:0] _zz_623_; - wire [31:0] _zz_624_; - wire [31:0] _zz_625_; - wire [31:0] _zz_626_; - wire [31:0] _zz_627_; - wire _zz_628_; - wire [0:0] _zz_629_; - wire [17:0] _zz_630_; - wire [31:0] _zz_631_; - wire [31:0] _zz_632_; - wire [31:0] _zz_633_; - wire _zz_634_; - wire [0:0] _zz_635_; - wire [11:0] _zz_636_; - wire [31:0] _zz_637_; - wire [31:0] _zz_638_; - wire [31:0] _zz_639_; - wire _zz_640_; - wire [0:0] _zz_641_; - wire [5:0] _zz_642_; - wire [31:0] _zz_643_; - wire [31:0] _zz_644_; - wire [31:0] _zz_645_; - wire _zz_646_; - wire _zz_647_; - wire decode_IS_RS1_SIGNED; - wire decode_CSR_READ_OPCODE; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire decode_CSR_WRITE_OPCODE; - wire decode_IS_CSR; - wire [31:0] memory_PC; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_1_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_2_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_3_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; - wire decode_IS_MUL; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_13_; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_SRC2_FORCE_ZERO; - wire decode_MEMORY_LRSC; - wire decode_IS_RS2_SIGNED; - wire [31:0] execute_SHIFT_RIGHT; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_14_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_15_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_16_; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire decode_IS_DIV; - wire [31:0] execute_BRANCH_CALC; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire decode_MEMORY_MANAGMENT; - wire execute_IS_DBUS_SHARING; - wire execute_BRANCH_DO; - wire decode_MEMORY_AMO; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_17_; - wire `AluCtrlEnum_defaultEncoding_type _zz_18_; - wire `AluCtrlEnum_defaultEncoding_type _zz_19_; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_24_; - wire memory_MEMORY_WR; - wire decode_MEMORY_WR; - wire memory_IS_SFENCE_VMA; - wire execute_IS_SFENCE_VMA; - wire decode_IS_SFENCE_VMA; - wire decode_SRC_LESS_UNSIGNED; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_25_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_26_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_27_; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_MUL; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire memory_IS_MUL; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29_; - wire _zz_30_; - wire _zz_31_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_32_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_33_; - wire [31:0] execute_PC; - wire [31:0] execute_RS1; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_34_; - wire _zz_35_; - wire decode_RS2_USE; - wire decode_RS1_USE; - reg [31:0] _zz_36_; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_37_; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_38_; - wire [31:0] _zz_39_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_40_; - wire _zz_41_; - wire [31:0] _zz_42_; - wire [31:0] _zz_43_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_44_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_45_; - wire [31:0] _zz_46_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_47_; - wire [31:0] _zz_48_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_49_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_50_; - wire [31:0] _zz_51_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_52_; - wire [31:0] _zz_53_; - wire _zz_54_; - reg _zz_55_; - wire [31:0] _zz_56_; - wire [31:0] _zz_57_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_58_; - wire _zz_59_; - wire _zz_60_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_61_; - wire _zz_62_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_63_; - wire `AluCtrlEnum_defaultEncoding_type _zz_64_; - wire _zz_65_; - wire _zz_66_; - wire _zz_67_; - wire _zz_68_; - wire _zz_69_; - wire _zz_70_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_71_; - wire _zz_72_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_73_; - wire _zz_74_; - wire _zz_75_; - wire _zz_76_; - wire _zz_77_; - wire _zz_78_; - wire _zz_79_; - wire _zz_80_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_81_; - wire _zz_82_; - wire _zz_83_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_84_; - wire _zz_85_; - wire writeBack_IS_SFENCE_VMA; - wire writeBack_IS_DBUS_SHARING; - wire memory_IS_DBUS_SHARING; - wire _zz_86_; - reg [31:0] _zz_87_; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire writeBack_MEMORY_WR; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire writeBack_MEMORY_ENABLE; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_ENABLE; - wire [1:0] _zz_88_; - wire execute_MEMORY_AMO; - wire execute_MEMORY_LRSC; - wire execute_MEMORY_MANAGMENT; - wire [31:0] execute_RS2; - wire execute_MEMORY_WR; - wire [31:0] execute_SRC_ADD; - wire execute_MEMORY_ENABLE; - wire [31:0] execute_INSTRUCTION; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_89_; - reg _zz_90_; - reg _zz_91_; - wire [31:0] decode_INSTRUCTION; - wire [31:0] _zz_92_; - reg [31:0] _zz_93_; - reg [31:0] _zz_94_; - wire [31:0] decode_PC; - wire [31:0] _zz_95_; - wire [31:0] _zz_96_; - wire [31:0] _zz_97_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - wire decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - wire execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - wire execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - reg writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - reg writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - reg [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - reg IBusCachedPlugin_mmuBus_rsp_allowRead; - reg IBusCachedPlugin_mmuBus_rsp_allowWrite; - reg IBusCachedPlugin_mmuBus_rsp_allowExecute; - reg IBusCachedPlugin_mmuBus_rsp_exception; - reg IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - wire DBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; - reg DBusCachedPlugin_mmuBus_cmd_bypassTranslation; - reg [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; - reg DBusCachedPlugin_mmuBus_rsp_allowRead; - reg DBusCachedPlugin_mmuBus_rsp_allowWrite; - reg DBusCachedPlugin_mmuBus_rsp_allowExecute; - reg DBusCachedPlugin_mmuBus_rsp_exception; - reg DBusCachedPlugin_mmuBus_rsp_refilling; - wire DBusCachedPlugin_mmuBus_end; - wire DBusCachedPlugin_mmuBus_busy; - reg DBusCachedPlugin_redoBranch_valid; - wire [31:0] DBusCachedPlugin_redoBranch_payload; - reg DBusCachedPlugin_exceptionBus_valid; - reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; - wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg MmuPlugin_dBusAccess_cmd_valid; - reg MmuPlugin_dBusAccess_cmd_ready; - reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; - wire [1:0] MmuPlugin_dBusAccess_cmd_payload_size; - wire MmuPlugin_dBusAccess_cmd_payload_write; - wire [31:0] MmuPlugin_dBusAccess_cmd_payload_data; - wire [3:0] MmuPlugin_dBusAccess_cmd_payload_writeMask; - wire MmuPlugin_dBusAccess_rsp_valid; - wire [31:0] MmuPlugin_dBusAccess_rsp_payload_data; - wire MmuPlugin_dBusAccess_rsp_payload_error; - wire MmuPlugin_dBusAccess_rsp_payload_redo; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire externalInterruptS; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - wire CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - wire CsrPlugin_allowInterrupts; - wire CsrPlugin_allowException; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_98_; - wire [3:0] _zz_99_; - wire _zz_100_; - wire _zz_101_; - wire _zz_102_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire IBusCachedPlugin_iBusRsp_stages_2_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_103_; - wire _zz_104_; - wire _zz_105_; - wire _zz_106_; - wire _zz_107_; - wire _zz_108_; - reg _zz_109_; - wire _zz_110_; - reg _zz_111_; - reg [31:0] _zz_112_; - wire _zz_113_; - reg _zz_114_; - reg [31:0] _zz_115_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_decodeInput_valid; - wire IBusCachedPlugin_iBusRsp_decodeInput_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - reg IBusCachedPlugin_injector_nextPcCalc_valids_5; - reg IBusCachedPlugin_injector_decodeRemoved; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_116_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; - wire dBus_cmd_payload_last; - wire dBus_rsp_valid; - wire [31:0] dBus_rsp_payload_data; - wire dBus_rsp_payload_error; - wire dataCache_1__io_mem_cmd_s2mPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_payload_last; - reg _zz_117_; - reg _zz_118_; - reg [31:0] _zz_119_; - reg [31:0] _zz_120_; - reg [3:0] _zz_121_; - reg [2:0] _zz_122_; - reg _zz_123_; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - wire [31:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - wire [3:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - wire dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg _zz_124_; - reg _zz_125_; - reg [31:0] _zz_126_; - reg [31:0] _zz_127_; - reg [3:0] _zz_128_; - reg [2:0] _zz_129_; - reg _zz_130_; - wire [31:0] _zz_131_; - reg [31:0] DBusCachedPlugin_rspCounter; - wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_132_; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_133_; - reg [31:0] _zz_134_; - wire _zz_135_; - reg [31:0] _zz_136_; - reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - reg DBusCachedPlugin_forceDatapath; - reg MmuPlugin_status_sum; - reg MmuPlugin_status_mxr; - reg MmuPlugin_status_mprv; - reg MmuPlugin_satp_mode; - reg [19:0] MmuPlugin_satp_ppn; - reg MmuPlugin_ports_0_cache_0_valid; - reg MmuPlugin_ports_0_cache_0_exception; - reg MmuPlugin_ports_0_cache_0_superPage; - reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_0_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_0_physicalAddress_1; - reg MmuPlugin_ports_0_cache_0_allowRead; - reg MmuPlugin_ports_0_cache_0_allowWrite; - reg MmuPlugin_ports_0_cache_0_allowExecute; - reg MmuPlugin_ports_0_cache_0_allowUser; - reg MmuPlugin_ports_0_cache_1_valid; - reg MmuPlugin_ports_0_cache_1_exception; - reg MmuPlugin_ports_0_cache_1_superPage; - reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_1_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_1_physicalAddress_1; - reg MmuPlugin_ports_0_cache_1_allowRead; - reg MmuPlugin_ports_0_cache_1_allowWrite; - reg MmuPlugin_ports_0_cache_1_allowExecute; - reg MmuPlugin_ports_0_cache_1_allowUser; - reg MmuPlugin_ports_0_cache_2_valid; - reg MmuPlugin_ports_0_cache_2_exception; - reg MmuPlugin_ports_0_cache_2_superPage; - reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_2_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_2_physicalAddress_1; - reg MmuPlugin_ports_0_cache_2_allowRead; - reg MmuPlugin_ports_0_cache_2_allowWrite; - reg MmuPlugin_ports_0_cache_2_allowExecute; - reg MmuPlugin_ports_0_cache_2_allowUser; - reg MmuPlugin_ports_0_cache_3_valid; - reg MmuPlugin_ports_0_cache_3_exception; - reg MmuPlugin_ports_0_cache_3_superPage; - reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_3_virtualAddress_1; - reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_0; - reg [9:0] MmuPlugin_ports_0_cache_3_physicalAddress_1; - reg MmuPlugin_ports_0_cache_3_allowRead; - reg MmuPlugin_ports_0_cache_3_allowWrite; - reg MmuPlugin_ports_0_cache_3_allowExecute; - reg MmuPlugin_ports_0_cache_3_allowUser; - wire MmuPlugin_ports_0_cacheHits_0; - wire MmuPlugin_ports_0_cacheHits_1; - wire MmuPlugin_ports_0_cacheHits_2; - wire MmuPlugin_ports_0_cacheHits_3; - wire MmuPlugin_ports_0_cacheHit; - wire _zz_137_; - wire _zz_138_; - wire [1:0] _zz_139_; - wire MmuPlugin_ports_0_cacheLine_valid; - wire MmuPlugin_ports_0_cacheLine_exception; - wire MmuPlugin_ports_0_cacheLine_superPage; - wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_0; - wire [9:0] MmuPlugin_ports_0_cacheLine_virtualAddress_1; - wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_0; - wire [9:0] MmuPlugin_ports_0_cacheLine_physicalAddress_1; - wire MmuPlugin_ports_0_cacheLine_allowRead; - wire MmuPlugin_ports_0_cacheLine_allowWrite; - wire MmuPlugin_ports_0_cacheLine_allowExecute; - wire MmuPlugin_ports_0_cacheLine_allowUser; - reg MmuPlugin_ports_0_entryToReplace_willIncrement; - wire MmuPlugin_ports_0_entryToReplace_willClear; - reg [1:0] MmuPlugin_ports_0_entryToReplace_valueNext; - reg [1:0] MmuPlugin_ports_0_entryToReplace_value; - wire MmuPlugin_ports_0_entryToReplace_willOverflowIfInc; - wire MmuPlugin_ports_0_entryToReplace_willOverflow; - reg MmuPlugin_ports_0_requireMmuLockup; - reg MmuPlugin_ports_1_cache_0_valid; - reg MmuPlugin_ports_1_cache_0_exception; - reg MmuPlugin_ports_1_cache_0_superPage; - reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_0_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_0_physicalAddress_1; - reg MmuPlugin_ports_1_cache_0_allowRead; - reg MmuPlugin_ports_1_cache_0_allowWrite; - reg MmuPlugin_ports_1_cache_0_allowExecute; - reg MmuPlugin_ports_1_cache_0_allowUser; - reg MmuPlugin_ports_1_cache_1_valid; - reg MmuPlugin_ports_1_cache_1_exception; - reg MmuPlugin_ports_1_cache_1_superPage; - reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_1_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_1_physicalAddress_1; - reg MmuPlugin_ports_1_cache_1_allowRead; - reg MmuPlugin_ports_1_cache_1_allowWrite; - reg MmuPlugin_ports_1_cache_1_allowExecute; - reg MmuPlugin_ports_1_cache_1_allowUser; - reg MmuPlugin_ports_1_cache_2_valid; - reg MmuPlugin_ports_1_cache_2_exception; - reg MmuPlugin_ports_1_cache_2_superPage; - reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_2_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_2_physicalAddress_1; - reg MmuPlugin_ports_1_cache_2_allowRead; - reg MmuPlugin_ports_1_cache_2_allowWrite; - reg MmuPlugin_ports_1_cache_2_allowExecute; - reg MmuPlugin_ports_1_cache_2_allowUser; - reg MmuPlugin_ports_1_cache_3_valid; - reg MmuPlugin_ports_1_cache_3_exception; - reg MmuPlugin_ports_1_cache_3_superPage; - reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_3_virtualAddress_1; - reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_0; - reg [9:0] MmuPlugin_ports_1_cache_3_physicalAddress_1; - reg MmuPlugin_ports_1_cache_3_allowRead; - reg MmuPlugin_ports_1_cache_3_allowWrite; - reg MmuPlugin_ports_1_cache_3_allowExecute; - reg MmuPlugin_ports_1_cache_3_allowUser; - wire MmuPlugin_ports_1_cacheHits_0; - wire MmuPlugin_ports_1_cacheHits_1; - wire MmuPlugin_ports_1_cacheHits_2; - wire MmuPlugin_ports_1_cacheHits_3; - wire MmuPlugin_ports_1_cacheHit; - wire _zz_140_; - wire _zz_141_; - wire [1:0] _zz_142_; - wire MmuPlugin_ports_1_cacheLine_valid; - wire MmuPlugin_ports_1_cacheLine_exception; - wire MmuPlugin_ports_1_cacheLine_superPage; - wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_0; - wire [9:0] MmuPlugin_ports_1_cacheLine_virtualAddress_1; - wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_0; - wire [9:0] MmuPlugin_ports_1_cacheLine_physicalAddress_1; - wire MmuPlugin_ports_1_cacheLine_allowRead; - wire MmuPlugin_ports_1_cacheLine_allowWrite; - wire MmuPlugin_ports_1_cacheLine_allowExecute; - wire MmuPlugin_ports_1_cacheLine_allowUser; - reg MmuPlugin_ports_1_entryToReplace_willIncrement; - wire MmuPlugin_ports_1_entryToReplace_willClear; - reg [1:0] MmuPlugin_ports_1_entryToReplace_valueNext; - reg [1:0] MmuPlugin_ports_1_entryToReplace_value; - wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; - wire MmuPlugin_ports_1_entryToReplace_willOverflow; - reg MmuPlugin_ports_1_requireMmuLockup; - reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1_; - reg [9:0] MmuPlugin_shared_vpn_0; - reg [9:0] MmuPlugin_shared_vpn_1; - reg [0:0] MmuPlugin_shared_portId; - wire MmuPlugin_shared_dBusRsp_pte_V; - wire MmuPlugin_shared_dBusRsp_pte_R; - wire MmuPlugin_shared_dBusRsp_pte_W; - wire MmuPlugin_shared_dBusRsp_pte_X; - wire MmuPlugin_shared_dBusRsp_pte_U; - wire MmuPlugin_shared_dBusRsp_pte_G; - wire MmuPlugin_shared_dBusRsp_pte_A; - wire MmuPlugin_shared_dBusRsp_pte_D; - wire [1:0] MmuPlugin_shared_dBusRsp_pte_RSW; - wire [9:0] MmuPlugin_shared_dBusRsp_pte_PPN0; - wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; - wire MmuPlugin_shared_dBusRsp_exception; - wire MmuPlugin_shared_dBusRsp_leaf; - reg MmuPlugin_shared_pteBuffer_V; - reg MmuPlugin_shared_pteBuffer_R; - reg MmuPlugin_shared_pteBuffer_W; - reg MmuPlugin_shared_pteBuffer_X; - reg MmuPlugin_shared_pteBuffer_U; - reg MmuPlugin_shared_pteBuffer_G; - reg MmuPlugin_shared_pteBuffer_A; - reg MmuPlugin_shared_pteBuffer_D; - reg [1:0] MmuPlugin_shared_pteBuffer_RSW; - reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; - reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; - wire [34:0] _zz_143_; - wire _zz_144_; - wire _zz_145_; - wire _zz_146_; - wire _zz_147_; - wire _zz_148_; - wire _zz_149_; - wire _zz_150_; - wire _zz_151_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_152_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_153_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_154_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_155_; - wire `AluCtrlEnum_defaultEncoding_type _zz_156_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_157_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_158_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_159_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_160_; - reg [31:0] _zz_161_; - wire _zz_162_; - reg [19:0] _zz_163_; - wire _zz_164_; - reg [19:0] _zz_165_; - reg [31:0] _zz_166_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_167_; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_168_; - reg _zz_169_; - reg _zz_170_; - wire _zz_171_; - reg _zz_172_; - reg [4:0] _zz_173_; - reg [31:0] _zz_174_; - wire _zz_175_; - wire _zz_176_; - wire _zz_177_; - wire _zz_178_; - wire _zz_179_; - wire _zz_180_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_181_; - reg _zz_182_; - reg _zz_183_; - wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_184_; - reg [10:0] _zz_185_; - wire _zz_186_; - reg [19:0] _zz_187_; - wire _zz_188_; - reg [18:0] _zz_189_; - reg [31:0] _zz_190_; - wire [31:0] execute_BranchPlugin_branch_src2; - wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] _zz_191_; - wire [1:0] CsrPlugin_misa_base; - wire [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg [31:0] CsrPlugin_mscratch; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg CsrPlugin_medeleg_IAM; - reg CsrPlugin_medeleg_IAF; - reg CsrPlugin_medeleg_II; - reg CsrPlugin_medeleg_LAM; - reg CsrPlugin_medeleg_LAF; - reg CsrPlugin_medeleg_SAM; - reg CsrPlugin_medeleg_SAF; - reg CsrPlugin_medeleg_EU; - reg CsrPlugin_medeleg_ES; - reg CsrPlugin_medeleg_IPF; - reg CsrPlugin_medeleg_LPF; - reg CsrPlugin_medeleg_SPF; - reg CsrPlugin_mideleg_ST; - reg CsrPlugin_mideleg_SE; - reg CsrPlugin_mideleg_SS; - reg CsrPlugin_sstatus_SIE; - reg CsrPlugin_sstatus_SPIE; - reg [0:0] CsrPlugin_sstatus_SPP; - reg CsrPlugin_sip_SEIP_SOFT; - reg CsrPlugin_sip_SEIP_INPUT; - wire CsrPlugin_sip_SEIP_OR; - reg CsrPlugin_sip_STIP; - reg CsrPlugin_sip_SSIP; - reg CsrPlugin_sie_SEIE; - reg CsrPlugin_sie_STIE; - reg CsrPlugin_sie_SSIE; - reg [1:0] CsrPlugin_stvec_mode; - reg [29:0] CsrPlugin_stvec_base; - reg [31:0] CsrPlugin_sscratch; - reg CsrPlugin_scause_interrupt; - reg [3:0] CsrPlugin_scause_exceptionCode; - reg [31:0] CsrPlugin_stval; - reg [31:0] CsrPlugin_sepc; - reg [21:0] CsrPlugin_satp_PPN; - reg [8:0] CsrPlugin_satp_ASID; - reg [0:0] CsrPlugin_satp_MODE; - wire _zz_192_; - wire _zz_193_; - wire _zz_194_; - wire _zz_195_; - wire _zz_196_; - wire _zz_197_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_198_; - wire _zz_199_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - reg CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - reg execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - reg [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - reg memory_MulDivIterativePlugin_mul_counter_willIncrement; - reg memory_MulDivIterativePlugin_mul_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; - wire memory_MulDivIterativePlugin_mul_willOverflowIfInc; - wire memory_MulDivIterativePlugin_mul_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_needRevert; - reg memory_MulDivIterativePlugin_div_counter_willIncrement; - reg memory_MulDivIterativePlugin_div_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_div_counter_value; - wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_div_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_done; - reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_200_; - wire [32:0] _zz_201_; - wire [32:0] _zz_202_; - wire [31:0] _zz_203_; - wire _zz_204_; - wire _zz_205_; - reg [32:0] _zz_206_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_207_; - wire [31:0] _zz_208_; - reg [31:0] _zz_209_; - wire [31:0] _zz_210_; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg decode_to_execute_IS_SFENCE_VMA; - reg execute_to_memory_IS_SFENCE_VMA; - reg memory_to_writeBack_IS_SFENCE_VMA; - reg decode_to_execute_MEMORY_WR; - reg execute_to_memory_MEMORY_WR; - reg memory_to_writeBack_MEMORY_WR; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg [31:0] decode_to_execute_RS2; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg decode_to_execute_MEMORY_AMO; - reg execute_to_memory_BRANCH_DO; - reg [31:0] decode_to_execute_RS1; - reg execute_to_memory_IS_DBUS_SHARING; - reg memory_to_writeBack_IS_DBUS_SHARING; - reg decode_to_execute_MEMORY_MANAGMENT; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg decode_to_execute_IS_RS2_SIGNED; - reg decode_to_execute_MEMORY_LRSC; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg decode_to_execute_IS_CSR; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg decode_to_execute_CSR_READ_OPCODE; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg decode_to_execute_IS_RS1_SIGNED; - reg [2:0] _zz_211_; - reg _zz_212_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_213_; - wire _zz_214_; - wire _zz_215_; - wire _zz_216_; - wire _zz_217_; - wire _zz_218_; - reg _zz_219_; - reg [31:0] dBusWishbone_DAT_MISO_regNext; - `ifndef SYNTHESIS - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_1__string; - reg [39:0] _zz_2__string; - reg [39:0] _zz_3__string; - reg [39:0] _zz_4__string; - reg [39:0] _zz_5__string; - reg [39:0] _zz_6__string; - reg [39:0] _zz_7__string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8__string; - reg [39:0] _zz_9__string; - reg [39:0] _zz_10__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_11__string; - reg [31:0] _zz_12__string; - reg [31:0] _zz_13__string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_14__string; - reg [95:0] _zz_15__string; - reg [95:0] _zz_16__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_17__string; - reg [63:0] _zz_18__string; - reg [63:0] _zz_19__string; - reg [71:0] _zz_20__string; - reg [71:0] _zz_21__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_22__string; - reg [71:0] _zz_23__string; - reg [71:0] _zz_24__string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_25__string; - reg [23:0] _zz_26__string; - reg [23:0] _zz_27__string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_28__string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_29__string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_32__string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_34__string; - reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_38__string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_40__string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_45__string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_47__string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_50__string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_52__string; - reg [95:0] _zz_61__string; - reg [71:0] _zz_63__string; - reg [63:0] _zz_64__string; - reg [39:0] _zz_71__string; - reg [23:0] _zz_73__string; - reg [31:0] _zz_81__string; - reg [39:0] _zz_84__string; - reg [47:0] MmuPlugin_shared_state_1__string; - reg [39:0] _zz_152__string; - reg [31:0] _zz_153__string; - reg [23:0] _zz_154__string; - reg [39:0] _zz_155__string; - reg [63:0] _zz_156__string; - reg [71:0] _zz_157__string; - reg [95:0] _zz_158__string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [71:0] execute_to_memory_SHIFT_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - `endif - - (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_271_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_272_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_273_ = 1'b1; - assign _zz_274_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_275_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_276_ = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_277_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_278_ = ((_zz_225_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_89_)); - assign _zz_279_ = ((_zz_225_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_90_)); - assign _zz_280_ = ((_zz_225_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_91_)); - assign _zz_281_ = ((_zz_225_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); - assign _zz_282_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_283_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_284_ = (! memory_MulDivIterativePlugin_mul_willOverflowIfInc); - assign _zz_285_ = (! memory_MulDivIterativePlugin_div_done); - assign _zz_286_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_287_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_288_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_289_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_290_ = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != (3'b000))); - assign _zz_291_ = (! dataCache_1__io_cpu_redo); - assign _zz_292_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_293_ = ((MmuPlugin_dBusAccess_rsp_valid && (! MmuPlugin_dBusAccess_rsp_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); - assign _zz_294_ = (MmuPlugin_shared_portId == (1'b1)); - assign _zz_295_ = (MmuPlugin_shared_portId == (1'b0)); - assign _zz_296_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_297_ = (1'b0 || (! 1'b1)); - assign _zz_298_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_299_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_300_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_301_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_302_ = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_303_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_304_ = (! memory_arbitration_isStuck); - assign _zz_305_ = (iBus_cmd_valid || (_zz_211_ != (3'b000))); - assign _zz_306_ = (_zz_245_ && (! dataCache_1__io_mem_cmd_s2mPipe_ready)); - assign _zz_307_ = (IBusCachedPlugin_mmuBus_cmd_isValid && IBusCachedPlugin_mmuBus_rsp_refilling); - assign _zz_308_ = (DBusCachedPlugin_mmuBus_cmd_isValid && DBusCachedPlugin_mmuBus_rsp_refilling); - assign _zz_309_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b00)); - assign _zz_310_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b01)); - assign _zz_311_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b10)); - assign _zz_312_ = (MmuPlugin_ports_0_entryToReplace_value == (2'b11)); - assign _zz_313_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b00)); - assign _zz_314_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b01)); - assign _zz_315_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b10)); - assign _zz_316_ = (MmuPlugin_ports_1_entryToReplace_value == (2'b11)); - assign _zz_317_ = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == (2'b01))) || (CsrPlugin_privilege < (2'b01))); - assign _zz_318_ = ((_zz_192_ && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); - assign _zz_319_ = ((_zz_193_ && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); - assign _zz_320_ = ((_zz_194_ && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); - assign _zz_321_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_322_ = ((_zz_192_ && 1'b1) && (! (CsrPlugin_mideleg_ST != (1'b0)))); - assign _zz_323_ = ((_zz_193_ && 1'b1) && (! (CsrPlugin_mideleg_SS != (1'b0)))); - assign _zz_324_ = ((_zz_194_ && 1'b1) && (! (CsrPlugin_mideleg_SE != (1'b0)))); - assign _zz_325_ = ((_zz_195_ && 1'b1) && (! 1'b0)); - assign _zz_326_ = ((_zz_196_ && 1'b1) && (! 1'b0)); - assign _zz_327_ = ((_zz_197_ && 1'b1) && (! 1'b0)); - assign _zz_328_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_329_ = execute_INSTRUCTION[13]; - assign _zz_330_ = (_zz_98_ - (4'b0001)); - assign _zz_331_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_332_ = {29'd0, _zz_331_}; - assign _zz_333_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); - assign _zz_334_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); - assign _zz_335_ = MmuPlugin_ports_0_entryToReplace_willIncrement; - assign _zz_336_ = {1'd0, _zz_335_}; - assign _zz_337_ = MmuPlugin_ports_1_entryToReplace_willIncrement; - assign _zz_338_ = {1'd0, _zz_337_}; - assign _zz_339_ = MmuPlugin_dBusAccess_rsp_payload_data[0 : 0]; - assign _zz_340_ = MmuPlugin_dBusAccess_rsp_payload_data[1 : 1]; - assign _zz_341_ = MmuPlugin_dBusAccess_rsp_payload_data[2 : 2]; - assign _zz_342_ = MmuPlugin_dBusAccess_rsp_payload_data[3 : 3]; - assign _zz_343_ = MmuPlugin_dBusAccess_rsp_payload_data[4 : 4]; - assign _zz_344_ = MmuPlugin_dBusAccess_rsp_payload_data[5 : 5]; - assign _zz_345_ = MmuPlugin_dBusAccess_rsp_payload_data[6 : 6]; - assign _zz_346_ = MmuPlugin_dBusAccess_rsp_payload_data[7 : 7]; - assign _zz_347_ = _zz_143_[2 : 2]; - assign _zz_348_ = _zz_143_[3 : 3]; - assign _zz_349_ = _zz_143_[6 : 6]; - assign _zz_350_ = _zz_143_[7 : 7]; - assign _zz_351_ = _zz_143_[8 : 8]; - assign _zz_352_ = _zz_143_[9 : 9]; - assign _zz_353_ = _zz_143_[10 : 10]; - assign _zz_354_ = _zz_143_[12 : 12]; - assign _zz_355_ = _zz_143_[13 : 13]; - assign _zz_356_ = _zz_143_[16 : 16]; - assign _zz_357_ = _zz_143_[19 : 19]; - assign _zz_358_ = _zz_143_[20 : 20]; - assign _zz_359_ = _zz_143_[21 : 21]; - assign _zz_360_ = _zz_143_[22 : 22]; - assign _zz_361_ = _zz_143_[23 : 23]; - assign _zz_362_ = _zz_143_[24 : 24]; - assign _zz_363_ = _zz_143_[29 : 29]; - assign _zz_364_ = _zz_143_[32 : 32]; - assign _zz_365_ = _zz_143_[33 : 33]; - assign _zz_366_ = _zz_143_[34 : 34]; - assign _zz_367_ = execute_SRC_LESS; - assign _zz_368_ = (3'b100); - assign _zz_369_ = execute_INSTRUCTION[19 : 15]; - assign _zz_370_ = execute_INSTRUCTION[31 : 20]; - assign _zz_371_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_372_ = ($signed(_zz_373_) + $signed(_zz_376_)); - assign _zz_373_ = ($signed(_zz_374_) + $signed(_zz_375_)); - assign _zz_374_ = execute_SRC1; - assign _zz_375_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_376_ = (execute_SRC_USE_SUB_LESS ? _zz_377_ : _zz_378_); - assign _zz_377_ = (32'b00000000000000000000000000000001); - assign _zz_378_ = (32'b00000000000000000000000000000000); - assign _zz_379_ = ($signed(_zz_381_) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_380_ = _zz_379_[31 : 0]; - assign _zz_381_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_382_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_383_ = execute_INSTRUCTION[31 : 20]; - assign _zz_384_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_385_ = (_zz_198_ & (~ _zz_386_)); - assign _zz_386_ = (_zz_198_ - (2'b01)); - assign _zz_387_ = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_388_ = {5'd0, _zz_387_}; - assign _zz_389_ = (_zz_391_ + _zz_393_); - assign _zz_390_ = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : (33'b000000000000000000000000000000000)); - assign _zz_391_ = {{1{_zz_390_[32]}}, _zz_390_}; - assign _zz_392_ = _zz_394_; - assign _zz_393_ = {{1{_zz_392_[32]}}, _zz_392_}; - assign _zz_394_ = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_395_ = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_396_ = {5'd0, _zz_395_}; - assign _zz_397_ = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_398_ = {_zz_200_,(! _zz_202_[32])}; - assign _zz_399_ = _zz_202_[31:0]; - assign _zz_400_ = _zz_201_[31:0]; - assign _zz_401_ = _zz_402_; - assign _zz_402_ = _zz_403_; - assign _zz_403_ = ({1'b0,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_203_) : _zz_203_)} + _zz_405_); - assign _zz_404_ = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_405_ = {32'd0, _zz_404_}; - assign _zz_406_ = _zz_205_; - assign _zz_407_ = {32'd0, _zz_406_}; - assign _zz_408_ = _zz_204_; - assign _zz_409_ = {31'd0, _zz_408_}; - assign _zz_410_ = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_411_ = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_412_ = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_413_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_414_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_415_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_416_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_417_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_418_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_419_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_420_ = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_421_ = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_422_ = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_423_ = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_424_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_425_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_426_ = execute_CsrPlugin_writeData[8 : 8]; - assign _zz_427_ = execute_CsrPlugin_writeData[2 : 2]; - assign _zz_428_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_429_ = execute_CsrPlugin_writeData[13 : 13]; - assign _zz_430_ = execute_CsrPlugin_writeData[4 : 4]; - assign _zz_431_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_432_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_433_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_434_ = execute_CsrPlugin_writeData[12 : 12]; - assign _zz_435_ = execute_CsrPlugin_writeData[15 : 15]; - assign _zz_436_ = execute_CsrPlugin_writeData[6 : 6]; - assign _zz_437_ = execute_CsrPlugin_writeData[0 : 0]; - assign _zz_438_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_439_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_440_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_441_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_442_ = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_443_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_444_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_445_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_446_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_447_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_448_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_449_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_450_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_451_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_452_ = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_453_ = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_454_ = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_455_ = (iBus_cmd_payload_address >>> 5); - assign _zz_456_ = 1'b1; - assign _zz_457_ = 1'b1; - assign _zz_458_ = {_zz_102_,_zz_101_}; - assign _zz_459_ = (32'b00010000000000000000000000001000); - assign _zz_460_ = ((decode_INSTRUCTION & (32'b00000000000000000001000001010000)) == (32'b00000000000000000001000001010000)); - assign _zz_461_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000001010000)); - assign _zz_462_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001100100)) == (32'b00000010000000000100000000100000)); - assign _zz_463_ = {_zz_145_,{_zz_151_,_zz_468_}}; - assign _zz_464_ = (3'b000); - assign _zz_465_ = ({_zz_151_,_zz_469_} != (2'b00)); - assign _zz_466_ = (_zz_470_ != (1'b0)); - assign _zz_467_ = {(_zz_471_ != _zz_472_),{_zz_473_,{_zz_474_,_zz_475_}}}; - assign _zz_468_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010100)) == (32'b00000000000000000000000000000100)); - assign _zz_469_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001100)) == (32'b00000000000000000000000000000100)); - assign _zz_470_ = ((decode_INSTRUCTION & (32'b00000010000000000011000001010000)) == (32'b00000010000000000000000001010000)); - assign _zz_471_ = {(_zz_476_ == _zz_477_),(_zz_478_ == _zz_479_)}; - assign _zz_472_ = (2'b00); - assign _zz_473_ = ({_zz_480_,{_zz_481_,_zz_482_}} != (3'b000)); - assign _zz_474_ = (_zz_483_ != (1'b0)); - assign _zz_475_ = {(_zz_484_ != _zz_485_),{_zz_486_,{_zz_487_,_zz_488_}}}; - assign _zz_476_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_477_ = (32'b00000000000000000101000000010000); - assign _zz_478_ = (decode_INSTRUCTION & (32'b00000010000000000111000001100100)); - assign _zz_479_ = (32'b00000000000000000101000000100000); - assign _zz_480_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); - assign _zz_481_ = ((decode_INSTRUCTION & _zz_489_) == (32'b00000000000000000001000000010000)); - assign _zz_482_ = ((decode_INSTRUCTION & _zz_490_) == (32'b00000000000000000001000000010000)); - assign _zz_483_ = ((decode_INSTRUCTION & (32'b00000000000000000100000000010100)) == (32'b00000000000000000100000000010000)); - assign _zz_484_ = ((decode_INSTRUCTION & _zz_491_) == (32'b00000000000000000010000000010000)); - assign _zz_485_ = (1'b0); - assign _zz_486_ = ({_zz_147_,{_zz_492_,_zz_493_}} != (3'b000)); - assign _zz_487_ = ({_zz_494_,_zz_495_} != (3'b000)); - assign _zz_488_ = {(_zz_496_ != _zz_497_),{_zz_498_,{_zz_499_,_zz_500_}}}; - assign _zz_489_ = (32'b00000000000000000111000000110100); - assign _zz_490_ = (32'b00000010000000000111000001010100); - assign _zz_491_ = (32'b00000000000000000110000000010100); - assign _zz_492_ = _zz_150_; - assign _zz_493_ = _zz_146_; - assign _zz_494_ = ((decode_INSTRUCTION & _zz_501_) == (32'b00000000000000000000000001000000)); - assign _zz_495_ = {(_zz_502_ == _zz_503_),(_zz_504_ == _zz_505_)}; - assign _zz_496_ = ((decode_INSTRUCTION & _zz_506_) == (32'b00000000000000000000000000100100)); - assign _zz_497_ = (1'b0); - assign _zz_498_ = ((_zz_507_ == _zz_508_) != (1'b0)); - assign _zz_499_ = ({_zz_509_,_zz_510_} != (7'b0000000)); - assign _zz_500_ = {(_zz_511_ != _zz_512_),{_zz_513_,{_zz_514_,_zz_515_}}}; - assign _zz_501_ = (32'b00000000000000000000000001000100); - assign _zz_502_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); - assign _zz_503_ = (32'b00000000000000000010000000010000); - assign _zz_504_ = (decode_INSTRUCTION & (32'b01000000000000000000000000110100)); - assign _zz_505_ = (32'b01000000000000000000000000110000); - assign _zz_506_ = (32'b00000000000000000000000001100100); - assign _zz_507_ = (decode_INSTRUCTION & (32'b00000000000000000101000001001000)); - assign _zz_508_ = (32'b00000000000000000001000000001000); - assign _zz_509_ = _zz_145_; - assign _zz_510_ = {(_zz_516_ == _zz_517_),{_zz_518_,{_zz_519_,_zz_520_}}}; - assign _zz_511_ = {(_zz_521_ == _zz_522_),(_zz_523_ == _zz_524_)}; - assign _zz_512_ = (2'b00); - assign _zz_513_ = ((_zz_525_ == _zz_526_) != (1'b0)); - assign _zz_514_ = (_zz_150_ != (1'b0)); - assign _zz_515_ = {(_zz_527_ != _zz_528_),{_zz_529_,{_zz_530_,_zz_531_}}}; - assign _zz_516_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); - assign _zz_517_ = (32'b00000000000000000001000000010000); - assign _zz_518_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); - assign _zz_519_ = ((decode_INSTRUCTION & _zz_532_) == (32'b00000000000000000010000000001000)); - assign _zz_520_ = {(_zz_533_ == _zz_534_),{_zz_148_,_zz_535_}}; - assign _zz_521_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_522_ = (32'b00000000000000000010000000000000); - assign _zz_523_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); - assign _zz_524_ = (32'b00000000000000000001000000000000); - assign _zz_525_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); - assign _zz_526_ = (32'b00000000000000000001000000000000); - assign _zz_527_ = ((decode_INSTRUCTION & _zz_536_) == (32'b00000000000000000100000000001000)); - assign _zz_528_ = (1'b0); - assign _zz_529_ = ({_zz_149_,_zz_537_} != (2'b00)); - assign _zz_530_ = ({_zz_538_,_zz_539_} != (2'b00)); - assign _zz_531_ = {(_zz_540_ != _zz_541_),{_zz_542_,{_zz_543_,_zz_544_}}}; - assign _zz_532_ = (32'b00000000000000000010000000001000); - assign _zz_533_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000)); - assign _zz_534_ = (32'b00000000000000000000000000010000); - assign _zz_535_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000)); - assign _zz_536_ = (32'b00000000000000000100000001001000); - assign _zz_537_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); - assign _zz_538_ = _zz_149_; - assign _zz_539_ = ((decode_INSTRUCTION & _zz_545_) == (32'b00000000000000000000000000000000)); - assign _zz_540_ = {_zz_144_,(_zz_546_ == _zz_547_)}; - assign _zz_541_ = (2'b00); - assign _zz_542_ = ((_zz_548_ == _zz_549_) != (1'b0)); - assign _zz_543_ = ({_zz_550_,_zz_551_} != (6'b000000)); - assign _zz_544_ = {(_zz_552_ != _zz_553_),{_zz_554_,{_zz_555_,_zz_556_}}}; - assign _zz_545_ = (32'b00000000000000000000000000100000); - assign _zz_546_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_547_ = (32'b00000000000000000000000000000000); - assign _zz_548_ = (decode_INSTRUCTION & (32'b00000010000000000100000001110100)); - assign _zz_549_ = (32'b00000010000000000000000000110000); - assign _zz_550_ = ((decode_INSTRUCTION & _zz_557_) == (32'b00000000000000000010000001000000)); - assign _zz_551_ = {(_zz_558_ == _zz_559_),{_zz_560_,{_zz_561_,_zz_562_}}}; - assign _zz_552_ = {_zz_148_,{_zz_563_,{_zz_564_,_zz_565_}}}; - assign _zz_553_ = (5'b00000); - assign _zz_554_ = ((_zz_566_ == _zz_567_) != (1'b0)); - assign _zz_555_ = (_zz_568_ != (1'b0)); - assign _zz_556_ = {(_zz_569_ != _zz_570_),{_zz_571_,{_zz_572_,_zz_573_}}}; - assign _zz_557_ = (32'b00000000000000000010000001000000); - assign _zz_558_ = (decode_INSTRUCTION & (32'b00000000000000000001000001000000)); - assign _zz_559_ = (32'b00000000000000000001000001000000); - assign _zz_560_ = ((decode_INSTRUCTION & _zz_574_) == (32'b00000000000000000000000001000000)); - assign _zz_561_ = (_zz_575_ == _zz_576_); - assign _zz_562_ = {_zz_577_,_zz_578_}; - assign _zz_563_ = ((decode_INSTRUCTION & _zz_579_) == (32'b00000000000000000010000000010000)); - assign _zz_564_ = (_zz_580_ == _zz_581_); - assign _zz_565_ = {_zz_582_,_zz_583_}; - assign _zz_566_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010000)); - assign _zz_567_ = (32'b00000000000000000000000000010000); - assign _zz_568_ = ((decode_INSTRUCTION & _zz_584_) == (32'b00000000000000000000000000001000)); - assign _zz_569_ = {_zz_147_,_zz_146_}; - assign _zz_570_ = (2'b00); - assign _zz_571_ = ({_zz_585_,_zz_586_} != (3'b000)); - assign _zz_572_ = (_zz_587_ != _zz_588_); - assign _zz_573_ = {_zz_589_,{_zz_590_,_zz_591_}}; - assign _zz_574_ = (32'b00000000000000000000000001010000); - assign _zz_575_ = (decode_INSTRUCTION & (32'b00000010010000000000000001000000)); - assign _zz_576_ = (32'b00000000000000000000000001000000); - assign _zz_577_ = ((decode_INSTRUCTION & _zz_592_) == (32'b00000000000000000000000000000000)); - assign _zz_578_ = ((decode_INSTRUCTION & _zz_593_) == (32'b00010000000000000010000000001000)); - assign _zz_579_ = (32'b00000000000000000010000000110000); - assign _zz_580_ = (decode_INSTRUCTION & (32'b00000000000000000001000000110000)); - assign _zz_581_ = (32'b00000000000000000000000000010000); - assign _zz_582_ = ((decode_INSTRUCTION & _zz_594_) == (32'b00000000000000000000000000100000)); - assign _zz_583_ = ((decode_INSTRUCTION & _zz_595_) == (32'b00000000000000000010000000100000)); - assign _zz_584_ = (32'b00010000000000000000000000001000); - assign _zz_585_ = (_zz_596_ == _zz_597_); - assign _zz_586_ = {_zz_598_,_zz_599_}; - assign _zz_587_ = {_zz_145_,_zz_600_}; - assign _zz_588_ = (2'b00); - assign _zz_589_ = (_zz_601_ != (1'b0)); - assign _zz_590_ = (_zz_602_ != _zz_603_); - assign _zz_591_ = {_zz_604_,{_zz_605_,_zz_606_}}; - assign _zz_592_ = (32'b00000000000000000000000000111000); - assign _zz_593_ = (32'b00011000000000000010000000001000); - assign _zz_594_ = (32'b00000010000000000011000000100000); - assign _zz_595_ = (32'b00000010000000000010000001101000); - assign _zz_596_ = (decode_INSTRUCTION & (32'b00001000000000000000000000100000)); - assign _zz_597_ = (32'b00001000000000000000000000100000); - assign _zz_598_ = ((decode_INSTRUCTION & (32'b00010000000000000000000000100000)) == (32'b00000000000000000000000000100000)); - assign _zz_599_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000100000)); - assign _zz_600_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); - assign _zz_601_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); - assign _zz_602_ = {(_zz_607_ == _zz_608_),{_zz_609_,{_zz_610_,_zz_611_}}}; - assign _zz_603_ = (5'b00000); - assign _zz_604_ = ({_zz_612_,{_zz_613_,_zz_614_}} != (4'b0000)); - assign _zz_605_ = (_zz_615_ != (1'b0)); - assign _zz_606_ = (_zz_616_ != (1'b0)); - assign _zz_607_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_608_ = (32'b00000000000000000000000000000000); - assign _zz_609_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011000)) == (32'b00000000000000000000000000000000)); - assign _zz_610_ = ((decode_INSTRUCTION & _zz_617_) == (32'b00000000000000000010000000000000)); - assign _zz_611_ = {(_zz_618_ == _zz_619_),_zz_144_}; - assign _zz_612_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000)); - assign _zz_613_ = ((decode_INSTRUCTION & _zz_620_) == (32'b00000000000000000000000000100000)); - assign _zz_614_ = {(_zz_621_ == _zz_622_),(_zz_623_ == _zz_624_)}; - assign _zz_615_ = ((decode_INSTRUCTION & (32'b00000010001000000011000001010000)) == (32'b00000000000000000000000001010000)); - assign _zz_616_ = ((decode_INSTRUCTION & (32'b00000010010000000011000001010000)) == (32'b00000000000000000000000001010000)); - assign _zz_617_ = (32'b00000000000000000110000000000100); - assign _zz_618_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); - assign _zz_619_ = (32'b00000000000000000001000000000000); - assign _zz_620_ = (32'b00000000000000000000000001100100); - assign _zz_621_ = (decode_INSTRUCTION & (32'b00001000000000000000000001110000)); - assign _zz_622_ = (32'b00001000000000000000000000100000); - assign _zz_623_ = (decode_INSTRUCTION & (32'b00010000000000000000000001110000)); - assign _zz_624_ = (32'b00000000000000000000000000100000); - assign _zz_625_ = (32'b00000000000000000001000001111111); - assign _zz_626_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_627_ = (32'b00000000000000000010000001110011); - assign _zz_628_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_629_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_630_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_631_) == (32'b00000000000000000000000000000011)),{(_zz_632_ == _zz_633_),{_zz_634_,{_zz_635_,_zz_636_}}}}}}; - assign _zz_631_ = (32'b00000000000000000101000001011111); - assign _zz_632_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_633_ = (32'b00000000000000000000000001100011); - assign _zz_634_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_635_ = ((decode_INSTRUCTION & (32'b00011000000000000111000001111111)) == (32'b00000000000000000010000000101111)); - assign _zz_636_ = {((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & (32'b11101000000000000111000001111111)) == (32'b00001000000000000010000000101111)),{((decode_INSTRUCTION & _zz_637_) == (32'b00000000000000000001000000010011)),{(_zz_638_ == _zz_639_),{_zz_640_,{_zz_641_,_zz_642_}}}}}}; - assign _zz_637_ = (32'b11111100000000000011000001011111); - assign _zz_638_ = (decode_INSTRUCTION & (32'b00000001111100000111000001111111)); - assign _zz_639_ = (32'b00000000000000000101000000001111); - assign _zz_640_ = ((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)); - assign _zz_641_ = ((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000101000000110011)); - assign _zz_642_ = {((decode_INSTRUCTION & (32'b10111110000000000111000001111111)) == (32'b00000000000000000000000000110011)),{((decode_INSTRUCTION & (32'b11111001111100000111000001111111)) == (32'b00010000000000000010000000101111)),{((decode_INSTRUCTION & _zz_643_) == (32'b00010010000000000000000001110011)),{(_zz_644_ == _zz_645_),{_zz_646_,_zz_647_}}}}}; - assign _zz_643_ = (32'b11111110000000000111111111111111); - assign _zz_644_ = (decode_INSTRUCTION & (32'b11011111111111111111111111111111)); - assign _zz_645_ = (32'b00010000001000000000000001110011); - assign _zz_646_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); - assign _zz_647_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011)); - always @ (posedge clk) begin - if(_zz_55_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_456_) begin - _zz_246_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_457_) begin - _zz_247_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_220_), - .io_cpu_prefetch_isValid(_zz_221_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), - .io_cpu_fetch_isValid(_zz_222_), - .io_cpu_fetch_isStuck(_zz_223_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_2_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_224_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_225_), - .io_cpu_decode_isStuck(_zz_226_), - .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), - .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), - .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), - .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), - .io_cpu_decode_isUser(_zz_227_), - .io_cpu_fill_valid(_zz_228_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); - DataCache dataCache_1_ ( - .io_cpu_execute_isValid(_zz_229_), - .io_cpu_execute_address(_zz_230_), - .io_cpu_execute_args_wr(_zz_231_), - .io_cpu_execute_args_data(_zz_232_), - .io_cpu_execute_args_size(_zz_233_), - .io_cpu_execute_args_isLrsc(_zz_234_), - .io_cpu_execute_args_isAmo(_zz_235_), - .io_cpu_execute_args_amoCtrl_swap(_zz_236_), - .io_cpu_execute_args_amoCtrl_alu(_zz_237_), - .io_cpu_memory_isValid(_zz_238_), - .io_cpu_memory_isStuck(memory_arbitration_isStuck), - .io_cpu_memory_isRemoved(memory_arbitration_removeIt), - .io_cpu_memory_isWrite(dataCache_1__io_cpu_memory_isWrite), - .io_cpu_memory_address(_zz_239_), - .io_cpu_memory_mmuBus_cmd_isValid(dataCache_1__io_cpu_memory_mmuBus_cmd_isValid), - .io_cpu_memory_mmuBus_cmd_virtualAddress(dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress), - .io_cpu_memory_mmuBus_cmd_bypassTranslation(dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation), - .io_cpu_memory_mmuBus_rsp_physicalAddress(DBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_memory_mmuBus_rsp_isIoAccess(_zz_240_), - .io_cpu_memory_mmuBus_rsp_allowRead(DBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_memory_mmuBus_rsp_allowWrite(DBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_memory_mmuBus_rsp_allowExecute(DBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_memory_mmuBus_rsp_exception(DBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_memory_mmuBus_rsp_refilling(DBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_memory_mmuBus_end(dataCache_1__io_cpu_memory_mmuBus_end), - .io_cpu_memory_mmuBus_busy(DBusCachedPlugin_mmuBus_busy), - .io_cpu_writeBack_isValid(_zz_241_), - .io_cpu_writeBack_isStuck(writeBack_arbitration_isStuck), - .io_cpu_writeBack_isUser(_zz_242_), - .io_cpu_writeBack_haltIt(dataCache_1__io_cpu_writeBack_haltIt), - .io_cpu_writeBack_isWrite(dataCache_1__io_cpu_writeBack_isWrite), - .io_cpu_writeBack_data(dataCache_1__io_cpu_writeBack_data), - .io_cpu_writeBack_address(_zz_243_), - .io_cpu_writeBack_mmuException(dataCache_1__io_cpu_writeBack_mmuException), - .io_cpu_writeBack_unalignedAccess(dataCache_1__io_cpu_writeBack_unalignedAccess), - .io_cpu_writeBack_accessError(dataCache_1__io_cpu_writeBack_accessError), - .io_cpu_writeBack_clearLrsc(contextSwitching), - .io_cpu_redo(dataCache_1__io_cpu_redo), - .io_cpu_flush_valid(_zz_244_), - .io_cpu_flush_ready(dataCache_1__io_cpu_flush_ready), - .io_mem_cmd_valid(dataCache_1__io_mem_cmd_valid), - .io_mem_cmd_ready(_zz_245_), - .io_mem_cmd_payload_wr(dataCache_1__io_mem_cmd_payload_wr), - .io_mem_cmd_payload_address(dataCache_1__io_mem_cmd_payload_address), - .io_mem_cmd_payload_data(dataCache_1__io_mem_cmd_payload_data), - .io_mem_cmd_payload_mask(dataCache_1__io_mem_cmd_payload_mask), - .io_mem_cmd_payload_length(dataCache_1__io_mem_cmd_payload_length), - .io_mem_cmd_payload_last(dataCache_1__io_mem_cmd_payload_last), - .io_mem_rsp_valid(dBus_rsp_valid), - .io_mem_rsp_payload_data(dBus_rsp_payload_data), - .io_mem_rsp_payload_error(dBus_rsp_payload_error), - .clk(clk), - .reset(reset) - ); always @(*) begin - case(_zz_458_) - 2'b00 : begin - _zz_248_ = DBusCachedPlugin_redoBranch_payload; - end - 2'b01 : begin - _zz_248_ = CsrPlugin_jumpInterface_payload; - end - 2'b10 : begin - _zz_248_ = BranchPlugin_jumpInterface_payload; - end - default : begin - _zz_248_ = IBusCachedPlugin_redoBranch_payload; - end + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; endcase end - always @(*) begin - case(_zz_139_) - 2'b00 : begin - _zz_249_ = MmuPlugin_ports_0_cache_0_valid; - _zz_250_ = MmuPlugin_ports_0_cache_0_exception; - _zz_251_ = MmuPlugin_ports_0_cache_0_superPage; - _zz_252_ = MmuPlugin_ports_0_cache_0_virtualAddress_0; - _zz_253_ = MmuPlugin_ports_0_cache_0_virtualAddress_1; - _zz_254_ = MmuPlugin_ports_0_cache_0_physicalAddress_0; - _zz_255_ = MmuPlugin_ports_0_cache_0_physicalAddress_1; - _zz_256_ = MmuPlugin_ports_0_cache_0_allowRead; - _zz_257_ = MmuPlugin_ports_0_cache_0_allowWrite; - _zz_258_ = MmuPlugin_ports_0_cache_0_allowExecute; - _zz_259_ = MmuPlugin_ports_0_cache_0_allowUser; - end - 2'b01 : begin - _zz_249_ = MmuPlugin_ports_0_cache_1_valid; - _zz_250_ = MmuPlugin_ports_0_cache_1_exception; - _zz_251_ = MmuPlugin_ports_0_cache_1_superPage; - _zz_252_ = MmuPlugin_ports_0_cache_1_virtualAddress_0; - _zz_253_ = MmuPlugin_ports_0_cache_1_virtualAddress_1; - _zz_254_ = MmuPlugin_ports_0_cache_1_physicalAddress_0; - _zz_255_ = MmuPlugin_ports_0_cache_1_physicalAddress_1; - _zz_256_ = MmuPlugin_ports_0_cache_1_allowRead; - _zz_257_ = MmuPlugin_ports_0_cache_1_allowWrite; - _zz_258_ = MmuPlugin_ports_0_cache_1_allowExecute; - _zz_259_ = MmuPlugin_ports_0_cache_1_allowUser; - end - 2'b10 : begin - _zz_249_ = MmuPlugin_ports_0_cache_2_valid; - _zz_250_ = MmuPlugin_ports_0_cache_2_exception; - _zz_251_ = MmuPlugin_ports_0_cache_2_superPage; - _zz_252_ = MmuPlugin_ports_0_cache_2_virtualAddress_0; - _zz_253_ = MmuPlugin_ports_0_cache_2_virtualAddress_1; - _zz_254_ = MmuPlugin_ports_0_cache_2_physicalAddress_0; - _zz_255_ = MmuPlugin_ports_0_cache_2_physicalAddress_1; - _zz_256_ = MmuPlugin_ports_0_cache_2_allowRead; - _zz_257_ = MmuPlugin_ports_0_cache_2_allowWrite; - _zz_258_ = MmuPlugin_ports_0_cache_2_allowExecute; - _zz_259_ = MmuPlugin_ports_0_cache_2_allowUser; - end - default : begin - _zz_249_ = MmuPlugin_ports_0_cache_3_valid; - _zz_250_ = MmuPlugin_ports_0_cache_3_exception; - _zz_251_ = MmuPlugin_ports_0_cache_3_superPage; - _zz_252_ = MmuPlugin_ports_0_cache_3_virtualAddress_0; - _zz_253_ = MmuPlugin_ports_0_cache_3_virtualAddress_1; - _zz_254_ = MmuPlugin_ports_0_cache_3_physicalAddress_0; - _zz_255_ = MmuPlugin_ports_0_cache_3_physicalAddress_1; - _zz_256_ = MmuPlugin_ports_0_cache_3_allowRead; - _zz_257_ = MmuPlugin_ports_0_cache_3_allowWrite; - _zz_258_ = MmuPlugin_ports_0_cache_3_allowExecute; - _zz_259_ = MmuPlugin_ports_0_cache_3_allowUser; - end + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; endcase end - always @(*) begin - case(_zz_142_) - 2'b00 : begin - _zz_260_ = MmuPlugin_ports_1_cache_0_valid; - _zz_261_ = MmuPlugin_ports_1_cache_0_exception; - _zz_262_ = MmuPlugin_ports_1_cache_0_superPage; - _zz_263_ = MmuPlugin_ports_1_cache_0_virtualAddress_0; - _zz_264_ = MmuPlugin_ports_1_cache_0_virtualAddress_1; - _zz_265_ = MmuPlugin_ports_1_cache_0_physicalAddress_0; - _zz_266_ = MmuPlugin_ports_1_cache_0_physicalAddress_1; - _zz_267_ = MmuPlugin_ports_1_cache_0_allowRead; - _zz_268_ = MmuPlugin_ports_1_cache_0_allowWrite; - _zz_269_ = MmuPlugin_ports_1_cache_0_allowExecute; - _zz_270_ = MmuPlugin_ports_1_cache_0_allowUser; - end - 2'b01 : begin - _zz_260_ = MmuPlugin_ports_1_cache_1_valid; - _zz_261_ = MmuPlugin_ports_1_cache_1_exception; - _zz_262_ = MmuPlugin_ports_1_cache_1_superPage; - _zz_263_ = MmuPlugin_ports_1_cache_1_virtualAddress_0; - _zz_264_ = MmuPlugin_ports_1_cache_1_virtualAddress_1; - _zz_265_ = MmuPlugin_ports_1_cache_1_physicalAddress_0; - _zz_266_ = MmuPlugin_ports_1_cache_1_physicalAddress_1; - _zz_267_ = MmuPlugin_ports_1_cache_1_allowRead; - _zz_268_ = MmuPlugin_ports_1_cache_1_allowWrite; - _zz_269_ = MmuPlugin_ports_1_cache_1_allowExecute; - _zz_270_ = MmuPlugin_ports_1_cache_1_allowUser; - end - 2'b10 : begin - _zz_260_ = MmuPlugin_ports_1_cache_2_valid; - _zz_261_ = MmuPlugin_ports_1_cache_2_exception; - _zz_262_ = MmuPlugin_ports_1_cache_2_superPage; - _zz_263_ = MmuPlugin_ports_1_cache_2_virtualAddress_0; - _zz_264_ = MmuPlugin_ports_1_cache_2_virtualAddress_1; - _zz_265_ = MmuPlugin_ports_1_cache_2_physicalAddress_0; - _zz_266_ = MmuPlugin_ports_1_cache_2_physicalAddress_1; - _zz_267_ = MmuPlugin_ports_1_cache_2_allowRead; - _zz_268_ = MmuPlugin_ports_1_cache_2_allowWrite; - _zz_269_ = MmuPlugin_ports_1_cache_2_allowExecute; - _zz_270_ = MmuPlugin_ports_1_cache_2_allowUser; - end - default : begin - _zz_260_ = MmuPlugin_ports_1_cache_3_valid; - _zz_261_ = MmuPlugin_ports_1_cache_3_exception; - _zz_262_ = MmuPlugin_ports_1_cache_3_superPage; - _zz_263_ = MmuPlugin_ports_1_cache_3_virtualAddress_0; - _zz_264_ = MmuPlugin_ports_1_cache_3_virtualAddress_1; - _zz_265_ = MmuPlugin_ports_1_cache_3_physicalAddress_0; - _zz_266_ = MmuPlugin_ports_1_cache_3_physicalAddress_1; - _zz_267_ = MmuPlugin_ports_1_cache_3_allowRead; - _zz_268_ = MmuPlugin_ports_1_cache_3_allowWrite; - _zz_269_ = MmuPlugin_ports_1_cache_3_allowExecute; - _zz_270_ = MmuPlugin_ports_1_cache_3_allowUser; - end + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; endcase end - - `ifndef SYNTHESIS always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_1_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_1__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_1__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_1__string = "AND_1"; - default : _zz_1__string = "?????"; - endcase - end - always @(*) begin - case(_zz_2_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_2__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_2__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_2__string = "AND_1"; - default : _zz_2__string = "?????"; - endcase - end - always @(*) begin - case(_zz_3_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_3__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_3__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_3__string = "AND_1"; - default : _zz_3__string = "?????"; - endcase - end - always @(*) begin - case(_zz_4_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL"; - default : _zz_4__string = "?????"; - endcase - end - always @(*) begin - case(_zz_5_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL"; - default : _zz_5__string = "?????"; - endcase - end - always @(*) begin - case(_zz_6_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL"; - default : _zz_6__string = "?????"; - endcase - end - always @(*) begin - case(_zz_7_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL"; - default : _zz_7__string = "?????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_8_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_8__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8__string = "ECALL"; - default : _zz_8__string = "?????"; - endcase - end - always @(*) begin - case(_zz_9_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_9__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9__string = "ECALL"; - default : _zz_9__string = "?????"; - endcase - end - always @(*) begin - case(_zz_10_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_10__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL"; - default : _zz_10__string = "?????"; - endcase - end - always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; - endcase - end - always @(*) begin - case(_zz_11_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11__string = "JALR"; - default : _zz_11__string = "????"; - endcase - end - always @(*) begin - case(_zz_12_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12__string = "JALR"; - default : _zz_12__string = "????"; - endcase - end - always @(*) begin - case(_zz_13_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_13__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_13__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_13__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_13__string = "JALR"; - default : _zz_13__string = "????"; - endcase - end - always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_14_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_14__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_14__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_14__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_14__string = "URS1 "; - default : _zz_14__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_15_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_15__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_15__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_15__string = "URS1 "; - default : _zz_15__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_16_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_16__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_16__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_16__string = "URS1 "; - default : _zz_16__string = "????????????"; - endcase - end - always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_17_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17__string = "BITWISE "; - default : _zz_17__string = "????????"; - endcase - end - always @(*) begin - case(_zz_18_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE "; - default : _zz_18__string = "????????"; - endcase - end - always @(*) begin - case(_zz_19_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE "; - default : _zz_19__string = "????????"; - endcase - end - always @(*) begin - case(_zz_20_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 "; - default : _zz_20__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_21_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 "; - default : _zz_21__string = "?????????"; - endcase - end - always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_22_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; - default : _zz_22__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_23_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 "; - default : _zz_23__string = "?????????"; - endcase - end - always @(*) begin - case(_zz_24_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1 "; - default : _zz_24__string = "?????????"; - endcase - end - always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_25_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_25__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_25__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_25__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_25__string = "PC "; - default : _zz_25__string = "???"; - endcase - end - always @(*) begin - case(_zz_26_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_26__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_26__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_26__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_26__string = "PC "; - default : _zz_26__string = "???"; - endcase - end - always @(*) begin - case(_zz_27_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_27__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_27__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_27__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_27__string = "PC "; - default : _zz_27__string = "???"; + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; endcase end always @(*) begin @@ -3605,12 +2621,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_28_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_28__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28__string = "ECALL"; - default : _zz_28__string = "?????"; + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; endcase end always @(*) begin @@ -3623,12 +2639,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_29_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_29__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29__string = "ECALL"; - default : _zz_29__string = "?????"; + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; endcase end always @(*) begin @@ -3641,12 +2657,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_32_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_32__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_32__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_32__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32__string = "ECALL"; - default : _zz_32__string = "?????"; + case(_zz_30) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_30_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_30_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_30_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30_string = "ECALL"; + default : _zz_30_string = "?????"; endcase end always @(*) begin @@ -3659,12 +2675,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_34_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_34__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_34__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_34__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_34__string = "JALR"; - default : _zz_34__string = "????"; + case(_zz_31) + `BranchCtrlEnum_defaultEncoding_INC : _zz_31_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_31_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_31_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_31_string = "JALR"; + default : _zz_31_string = "????"; endcase end always @(*) begin @@ -3677,12 +2693,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_38_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38__string = "SRA_1 "; - default : _zz_38__string = "?????????"; + case(_zz_34) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; + default : _zz_34_string = "?????????"; endcase end always @(*) begin @@ -3695,12 +2711,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_40_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40__string = "SRA_1 "; - default : _zz_40__string = "?????????"; + case(_zz_35) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35_string = "SRA_1 "; + default : _zz_35_string = "?????????"; endcase end always @(*) begin @@ -3713,12 +2729,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_45_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_45__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_45__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_45__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_45__string = "PC "; - default : _zz_45__string = "???"; + case(_zz_37) + `Src2CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_37_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_37_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_37_string = "PC "; + default : _zz_37_string = "???"; endcase end always @(*) begin @@ -3731,12 +2747,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_47_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_47__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_47__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_47__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_47__string = "URS1 "; - default : _zz_47__string = "????????????"; + case(_zz_38) + `Src1CtrlEnum_defaultEncoding_RS : _zz_38_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_38_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_38_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_38_string = "URS1 "; + default : _zz_38_string = "????????????"; endcase end always @(*) begin @@ -3748,11 +2764,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_50_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_50__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_50__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_50__string = "BITWISE "; - default : _zz_50__string = "????????"; + case(_zz_39) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_39_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_39_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_39_string = "BITWISE "; + default : _zz_39_string = "????????"; endcase end always @(*) begin @@ -3764,143 +2780,160 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_52_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_52__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_52__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_52__string = "AND_1"; - default : _zz_52__string = "?????"; + case(_zz_40) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_40_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_40_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_40_string = "AND_1"; + default : _zz_40_string = "?????"; + endcase + end + always @(*) begin + case(_zz_44) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_44_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_44_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_44_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_44_string = "ECALL"; + default : _zz_44_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `BranchCtrlEnum_defaultEncoding_INC : _zz_45_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_45_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_45_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_45_string = "JALR"; + default : _zz_45_string = "????"; endcase end always @(*) begin - case(_zz_61_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_61__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_61__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_61__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_61__string = "URS1 "; - default : _zz_61__string = "????????????"; + case(_zz_46) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46_string = "SRA_1 "; + default : _zz_46_string = "?????????"; endcase end always @(*) begin - case(_zz_63_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_63__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_63__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_63__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_63__string = "SRA_1 "; - default : _zz_63__string = "?????????"; + case(_zz_47) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47_string = "AND_1"; + default : _zz_47_string = "?????"; endcase end always @(*) begin - case(_zz_64_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_64__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_64__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_64__string = "BITWISE "; - default : _zz_64__string = "????????"; + case(_zz_48) + `Src2CtrlEnum_defaultEncoding_RS : _zz_48_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_48_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_48_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_48_string = "PC "; + default : _zz_48_string = "???"; endcase end always @(*) begin - case(_zz_71_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_71__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_71__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_71__string = "AND_1"; - default : _zz_71__string = "?????"; + case(_zz_49) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_49_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_49_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_49_string = "BITWISE "; + default : _zz_49_string = "????????"; endcase end always @(*) begin - case(_zz_73_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_73__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_73__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_73__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_73__string = "PC "; - default : _zz_73__string = "???"; + case(_zz_50) + `Src1CtrlEnum_defaultEncoding_RS : _zz_50_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_50_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_50_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_50_string = "URS1 "; + default : _zz_50_string = "????????????"; endcase end always @(*) begin - case(_zz_81_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_81__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_81__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_81__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_81__string = "JALR"; - default : _zz_81__string = "????"; + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; + `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; + default : MmuPlugin_shared_state_1_string = "??????"; endcase end always @(*) begin - case(_zz_84_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_84__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_84__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_84__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_84__string = "ECALL"; - default : _zz_84__string = "?????"; + case(_zz_103) + `Src1CtrlEnum_defaultEncoding_RS : _zz_103_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_103_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_103_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_103_string = "URS1 "; + default : _zz_103_string = "????????????"; endcase end always @(*) begin - case(MmuPlugin_shared_state_1_) - `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1__string = "IDLE "; - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1__string = "L1_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1__string = "L1_RSP"; - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1__string = "L0_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1__string = "L0_RSP"; - default : MmuPlugin_shared_state_1__string = "??????"; + case(_zz_104) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_104_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_104_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_104_string = "BITWISE "; + default : _zz_104_string = "????????"; endcase end always @(*) begin - case(_zz_152_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_152__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_152__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_152__string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_152__string = "ECALL"; - default : _zz_152__string = "?????"; + case(_zz_105) + `Src2CtrlEnum_defaultEncoding_RS : _zz_105_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_105_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_105_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_105_string = "PC "; + default : _zz_105_string = "???"; endcase end always @(*) begin - case(_zz_153_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_153__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_153__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_153__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_153__string = "JALR"; - default : _zz_153__string = "????"; + case(_zz_106) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_106_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_106_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_106_string = "AND_1"; + default : _zz_106_string = "?????"; endcase end always @(*) begin - case(_zz_154_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_154__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_154__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_154__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_154__string = "PC "; - default : _zz_154__string = "???"; + case(_zz_107) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_107_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_107_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_107_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_107_string = "SRA_1 "; + default : _zz_107_string = "?????????"; endcase end always @(*) begin - case(_zz_155_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_155__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_155__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_155__string = "AND_1"; - default : _zz_155__string = "?????"; + case(_zz_108) + `BranchCtrlEnum_defaultEncoding_INC : _zz_108_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_108_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_108_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_108_string = "JALR"; + default : _zz_108_string = "????"; endcase end always @(*) begin - case(_zz_156_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_156__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_156__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_156__string = "BITWISE "; - default : _zz_156__string = "????????"; + case(_zz_109) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_109_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_109_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_109_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_109_string = "ECALL"; + default : _zz_109_string = "?????"; endcase end always @(*) begin - case(_zz_157_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_157__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_157__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_157__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_157__string = "SRA_1 "; - default : _zz_157__string = "?????????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_158_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_158__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_158__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_158__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_158__string = "URS1 "; - default : _zz_158__string = "????????????"; + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin @@ -3912,6 +2945,14 @@ module VexRiscv ( default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end always @(*) begin case(decode_to_execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; @@ -3930,23 +2971,6 @@ module VexRiscv ( default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end always @(*) begin case(decode_to_execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; @@ -3983,65 +3007,56 @@ module VexRiscv ( default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end `endif - assign decode_IS_RS1_SIGNED = _zz_65_; - assign decode_CSR_READ_OPCODE = _zz_30_; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_128; + assign execute_SHIFT_RIGHT = _zz_306; + assign execute_REGFILE_WRITE_DATA = _zz_111; + assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_88_; - assign decode_CSR_WRITE_OPCODE = _zz_31_; - assign decode_IS_CSR = _zz_59_; - assign memory_PC = execute_to_memory_PC; - assign decode_ALU_BITWISE_CTRL = _zz_1_; - assign _zz_2_ = _zz_3_; - assign _zz_4_ = _zz_5_; - assign _zz_6_ = _zz_7_; - assign decode_ENV_CTRL = _zz_8_; - assign _zz_9_ = _zz_10_; - assign decode_IS_MUL = _zz_75_; - assign decode_BRANCH_CTRL = _zz_11_; - assign _zz_12_ = _zz_13_; + assign execute_MEMORY_ADDRESS_LOW = _zz_197[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_DIV = _zz_308[0]; + assign decode_IS_RS2_SIGNED = _zz_309[0]; + assign decode_IS_RS1_SIGNED = _zz_310[0]; + assign decode_IS_MUL = _zz_311[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_312[0]; + assign decode_BRANCH_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign _zz_11 = _zz_12; + assign decode_SHIFT_CTRL = _zz_13; + assign _zz_14 = _zz_15; + assign decode_ALU_BITWISE_CTRL = _zz_16; + assign _zz_17 = _zz_18; + assign decode_SRC_LESS_UNSIGNED = _zz_313[0]; + assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; + assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; + assign decode_IS_SFENCE_VMA = _zz_314[0]; + assign decode_MEMORY_MANAGMENT = _zz_315[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_316[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_77_; - assign decode_SRC2_FORCE_ZERO = _zz_49_; - assign decode_MEMORY_LRSC = _zz_58_; - assign decode_IS_RS2_SIGNED = _zz_79_; - assign execute_SHIFT_RIGHT = _zz_39_; - assign decode_SRC1_CTRL = _zz_14_; - assign _zz_15_ = _zz_16_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_76_; - assign decode_IS_DIV = _zz_60_; - assign execute_BRANCH_CALC = _zz_33_; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_317[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_318[0]; + assign decode_SRC2_CTRL = _zz_19; + assign _zz_20 = _zz_21; + assign decode_ALU_CTRL = _zz_22; + assign _zz_23 = _zz_24; + assign decode_SRC1_CTRL = _zz_25; + assign _zz_26 = _zz_27; + assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_52; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_95_; - assign decode_MEMORY_MANAGMENT = _zz_72_; - assign execute_IS_DBUS_SHARING = _zz_86_; - assign execute_BRANCH_DO = _zz_35_; - assign decode_MEMORY_AMO = _zz_78_; - assign decode_ALU_CTRL = _zz_17_; - assign _zz_18_ = _zz_19_; - assign execute_REGFILE_WRITE_DATA = _zz_51_; - assign _zz_20_ = _zz_21_; - assign decode_SHIFT_CTRL = _zz_22_; - assign _zz_23_ = _zz_24_; - assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_80_; - assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; - assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; - assign decode_IS_SFENCE_VMA = _zz_62_; - assign decode_SRC_LESS_UNSIGNED = _zz_70_; - assign decode_SRC2_CTRL = _zz_25_; - assign _zz_26_ = _zz_27_; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_MUL = decode_to_execute_IS_MUL; @@ -4051,23 +3066,23 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_28_; - assign execute_ENV_CTRL = _zz_29_; - assign writeBack_ENV_CTRL = _zz_32_; + assign memory_ENV_CTRL = _zz_28; + assign execute_ENV_CTRL = _zz_29; + assign writeBack_ENV_CTRL = _zz_30; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_34_; - assign decode_RS2_USE = _zz_83_; - assign decode_RS1_USE = _zz_82_; + assign execute_BRANCH_CTRL = _zz_31; + assign decode_RS2_USE = _zz_319[0]; + assign decode_RS1_USE = _zz_320[0]; always @ (*) begin - _zz_36_ = execute_REGFILE_WRITE_DATA; - if(_zz_271_)begin - _zz_36_ = execute_CsrPlugin_readData; + _zz_32 = execute_REGFILE_WRITE_DATA; + if(_zz_247)begin + _zz_32 = execute_CsrPlugin_readData; end if(DBusCachedPlugin_forceDatapath)begin - _zz_36_ = MmuPlugin_dBusAccess_cmd_payload_address; + _zz_32 = MmuPlugin_dBusAccess_cmd_payload_address; end end @@ -4078,60 +3093,60 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - decode_RS2 = _zz_56_; - if(_zz_172_)begin - if((_zz_173_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_174_; + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_272_)begin - if(_zz_273_)begin - if(_zz_176_)begin - decode_RS2 = _zz_87_; + if(_zz_248)begin + if(_zz_249)begin + if(_zz_121)begin + decode_RS2 = _zz_51; end end end - if(_zz_274_)begin + if(_zz_250)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_178_)begin - decode_RS2 = _zz_37_; + if(_zz_123)begin + decode_RS2 = _zz_33; end end end - if(_zz_275_)begin + if(_zz_251)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_180_)begin - decode_RS2 = _zz_36_; + if(_zz_125)begin + decode_RS2 = _zz_32; end end end end always @ (*) begin - decode_RS1 = _zz_57_; - if(_zz_172_)begin - if((_zz_173_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_174_; + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_272_)begin - if(_zz_273_)begin - if(_zz_175_)begin - decode_RS1 = _zz_87_; + if(_zz_248)begin + if(_zz_249)begin + if(_zz_120)begin + decode_RS1 = _zz_51; end end end - if(_zz_274_)begin + if(_zz_250)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_177_)begin - decode_RS1 = _zz_37_; + if(_zz_122)begin + decode_RS1 = _zz_33; end end end - if(_zz_275_)begin + if(_zz_251)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_179_)begin - decode_RS1 = _zz_36_; + if(_zz_124)begin + decode_RS1 = _zz_32; end end end @@ -4139,69 +3154,68 @@ module VexRiscv ( assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_37_ = memory_REGFILE_WRITE_DATA; + _zz_33 = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_37_ = _zz_168_; + _zz_33 = _zz_119; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_37_ = memory_SHIFT_RIGHT; + _zz_33 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_276_)begin - _zz_37_ = ((memory_INSTRUCTION[13 : 12] == (2'b00)) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + if(_zz_252)begin + _zz_33 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_277_)begin - _zz_37_ = memory_MulDivIterativePlugin_div_result; + if(_zz_253)begin + _zz_33 = memory_MulDivIterativePlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_38_; - assign execute_SHIFT_CTRL = _zz_40_; + assign memory_SHIFT_CTRL = _zz_34; + assign execute_SHIFT_CTRL = _zz_35; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_44_ = execute_PC; - assign execute_SRC2_CTRL = _zz_45_; - assign execute_SRC1_CTRL = _zz_47_; - assign decode_SRC_USE_SUB_LESS = _zz_66_; - assign decode_SRC_ADD_ZERO = _zz_67_; - assign execute_SRC_ADD_SUB = _zz_43_; - assign execute_SRC_LESS = _zz_41_; - assign execute_ALU_CTRL = _zz_50_; - assign execute_SRC2 = _zz_46_; - assign execute_SRC1 = _zz_48_; - assign execute_ALU_BITWISE_CTRL = _zz_52_; - assign _zz_53_ = writeBack_INSTRUCTION; - assign _zz_54_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_55_ = 1'b0; + assign _zz_36 = execute_PC; + assign execute_SRC2_CTRL = _zz_37; + assign execute_SRC1_CTRL = _zz_38; + assign decode_SRC_USE_SUB_LESS = _zz_321[0]; + assign decode_SRC_ADD_ZERO = _zz_322[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_39; + assign execute_SRC2 = _zz_117; + assign execute_SRC1 = _zz_112; + assign execute_ALU_BITWISE_CTRL = _zz_40; + assign _zz_41 = writeBack_INSTRUCTION; + assign _zz_42 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_43 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_55_ = 1'b1; + _zz_43 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_92_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_69_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_323[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_85_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_435) == 32'h00001073),{(_zz_436 == _zz_437),{_zz_438,{_zz_439,_zz_440}}}}}}} != 25'h0); assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; always @ (*) begin - _zz_87_ = writeBack_REGFILE_WRITE_DATA; + _zz_51 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_87_ = writeBack_DBusCachedPlugin_rspFormated; + _zz_51 = writeBack_DBusCachedPlugin_rspFormated; end end @@ -4213,58 +3227,61 @@ module VexRiscv ( assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; assign execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; assign execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; - assign execute_SRC_ADD = _zz_42_; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_74_; - assign decode_FLUSH_ALL = _zz_68_; + assign decode_MEMORY_AMO = _zz_324[0]; + assign decode_MEMORY_LRSC = _zz_325[0]; + assign decode_MEMORY_ENABLE = _zz_326[0]; + assign decode_FLUSH_ALL = _zz_327[0]; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_89_; - if(_zz_278_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_254)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin - _zz_89_ = _zz_90_; - if(_zz_279_)begin - _zz_89_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_255)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin - _zz_90_ = _zz_91_; - if(_zz_280_)begin - _zz_90_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_256)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_91_ = 1'b0; - if(_zz_281_)begin - _zz_91_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_257)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_INSTRUCTION = _zz_96_; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_93_ = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_93_ = BranchPlugin_jumpInterface_payload; + _zz_53 = execute_FORMAL_PC_NEXT; + if(CsrPlugin_redoInterface_valid)begin + _zz_53 = CsrPlugin_redoInterface_payload; end end always @ (*) begin - _zz_94_ = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_94_ = IBusCachedPlugin_redoBranch_payload; + _zz_54 = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_54 = BranchPlugin_jumpInterface_payload; end end - assign decode_PC = _zz_97_; + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -4279,20 +3296,20 @@ module VexRiscv ( if(MmuPlugin_dBusAccess_cmd_valid)begin decode_arbitration_haltByOther = 1'b1; end - if((decode_arbitration_isValid && (_zz_169_ || _zz_170_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_282_)begin + if(_zz_258)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4303,35 +3320,35 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin - decode_arbitration_flushNext = 1'b1; - end - if(_zz_282_)begin + if(_zz_258)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if((_zz_244_ && (! dataCache_1__io_cpu_flush_ready)))begin - execute_arbitration_haltItself = 1'b1; - end - if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + if(((_zz_220 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_283_)begin + if(_zz_259)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_271_)begin + if(_zz_247)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end end end - assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + end + always @ (*) begin execute_arbitration_removeIt = 1'b0; if(CsrPlugin_selfException_valid)begin @@ -4348,17 +3365,25 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + execute_arbitration_flushNext = 1'b1; + end + end end always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_276_)begin - if(_zz_284_)begin + if(_zz_252)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_260)begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_277_)begin - if(_zz_285_)begin + if(_zz_253)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end end @@ -4388,7 +3413,7 @@ module VexRiscv ( always @ (*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1__io_cpu_writeBack_haltIt)begin + if(dataCache_1_io_cpu_writeBack_haltIt)begin writeBack_arbitration_haltItself = 1'b1; end end @@ -4419,10 +3444,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_286_)begin + if(_zz_261)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_287_)begin + if(_zz_262)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -4433,48 +3458,49 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_286_)begin + if(_zz_261)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_287_)begin + if(_zz_262)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; + IBusCachedPlugin_incomingInstruction = 1'b0; + if(((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid) || IBusCachedPlugin_iBusRsp_stages_3_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; end end always @ (*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if(((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin - IBusCachedPlugin_incomingInstruction = 1'b1; + CsrPlugin_inWfi = 1'b0; + if(_zz_259)begin + CsrPlugin_inWfi = 1'b1; end end + assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_286_)begin + if(_zz_261)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_287_)begin + if(_zz_262)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_286_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_261)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_287_)begin - case(_zz_288_) + if(_zz_262)begin + case(_zz_263) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -4490,20 +3516,25 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_redoBranch_valid}}} != (4'b0000)); - assign _zz_98_ = {IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_99_ = (_zz_98_ & (~ _zz_330_)); - assign _zz_100_ = _zz_99_[3]; - assign _zz_101_ = (_zz_99_[1] || _zz_100_); - assign _zz_102_ = (_zz_99_[2] || _zz_100_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_248_; - always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}} != 4'b0000); + assign _zz_55 = {CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_56 = (_zz_55 & (~ _zz_328)); + assign _zz_57 = _zz_56[3]; + assign _zz_58 = (_zz_56[1] || _zz_57); + assign _zz_59 = (_zz_56[2] || _zz_57); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_224; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin @@ -4512,7 +3543,10 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_332_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_330); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end @@ -4520,16 +3554,32 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; assign IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - assign _zz_103_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_103_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_103_); + assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_60); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_60); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; @@ -4538,45 +3588,48 @@ module VexRiscv ( end end - assign _zz_104_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_104_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_104_); + assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_61); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_61); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + if(IBusCachedPlugin_mmuBus_busy)begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_105_ = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_105_); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_105_); + assign _zz_62 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_62); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_62); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + IBusCachedPlugin_iBusRsp_stages_3_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_3_halt = 1'b1; end end - assign _zz_106_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_106_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_106_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_107_; - assign _zz_107_ = ((1'b0 && (! _zz_108_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_108_ = _zz_109_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_108_; + assign _zz_63 = (! IBusCachedPlugin_iBusRsp_stages_3_halt); + assign IBusCachedPlugin_iBusRsp_stages_3_input_ready = (IBusCachedPlugin_iBusRsp_stages_3_output_ready && _zz_63); + assign IBusCachedPlugin_iBusRsp_stages_3_output_valid = (IBusCachedPlugin_iBusRsp_stages_3_input_valid && _zz_63); + assign IBusCachedPlugin_iBusRsp_stages_3_output_payload = IBusCachedPlugin_iBusRsp_stages_3_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_3_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_64; + assign _zz_64 = ((1'b0 && (! _zz_65)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_65 = _zz_66; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_65; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_110_)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_110_ = _zz_111_; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_110_; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_112_; - assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_113_ = _zz_114_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_113_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_115_; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_67)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_67 = _zz_68; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_67; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_69; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_3_input_ready); + assign _zz_70 = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_3_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_3_input_payload = _zz_72; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -4588,11 +3641,8 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_5; - assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); - assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - assign _zz_97_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - assign _zz_96_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - assign _zz_95_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -4601,120 +3651,127 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_221_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_224_ = (32'b00000000000000000000000000000000); - assign _zz_222_ = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_223_ = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_225_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_226_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_227_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_92_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign _zz_188 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_189 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_190 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_189; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_2_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_192 = (IBusCachedPlugin_iBusRsp_stages_3_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_193 = (! IBusCachedPlugin_iBusRsp_stages_3_input_ready); + assign _zz_194 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_281_)begin + if(_zz_257)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_279_)begin + if(_zz_255)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_289_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - end end always @ (*) begin - _zz_228_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_279_)begin - _zz_228_ = 1'b1; - end - if(_zz_289_)begin - _zz_228_ = 1'b0; + _zz_195 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_255)begin + _zz_195 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_280_)begin + if(_zz_256)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_278_)begin + if(_zz_254)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_280_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); - end - if(_zz_278_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_220_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1__io_mem_cmd_s2mPipe_valid = (dataCache_1__io_mem_cmd_valid || _zz_117_); - assign _zz_245_ = (! _zz_117_); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_wr = (_zz_117_ ? _zz_118_ : dataCache_1__io_mem_cmd_payload_wr); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_address = (_zz_117_ ? _zz_119_ : dataCache_1__io_mem_cmd_payload_address); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_data = (_zz_117_ ? _zz_120_ : dataCache_1__io_mem_cmd_payload_data); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_mask = (_zz_117_ ? _zz_121_ : dataCache_1__io_mem_cmd_payload_mask); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_length = (_zz_117_ ? _zz_122_ : dataCache_1__io_mem_cmd_payload_length); - assign dataCache_1__io_mem_cmd_s2mPipe_payload_last = (_zz_117_ ? _zz_123_ : dataCache_1__io_mem_cmd_payload_last); - assign dataCache_1__io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid = _zz_124_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr = _zz_125_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address = _zz_126_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data = _zz_127_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask = _zz_128_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length = _zz_129_; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last = _zz_130_; - assign dBus_cmd_valid = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_valid; - assign dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; - assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_wr; - assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_address; - assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_data; - assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_length; - assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_s2mPipe_m2sPipe_payload_last; + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_256)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_254)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_3_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_3_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_3_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_3_output_payload; + assign _zz_187 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_221 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + always @ (*) begin + _zz_52 = 1'b0; + if(decode_INSTRUCTION[25])begin + if(decode_MEMORY_LRSC)begin + _zz_52 = 1'b1; + end + if(decode_MEMORY_AMO)begin + _zz_52 = 1'b1; + end + end + end + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin - _zz_229_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + _zz_196 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_290_)begin - if(_zz_291_)begin - _zz_229_ = 1'b1; + if(_zz_264)begin + if(_zz_265)begin + _zz_196 = 1'b1; end end end end always @ (*) begin - _zz_230_ = execute_SRC_ADD; + _zz_197 = execute_SRC_ADD; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_290_)begin - _zz_230_ = MmuPlugin_dBusAccess_cmd_payload_address; + if(_zz_264)begin + _zz_197 = MmuPlugin_dBusAccess_cmd_payload_address; end end end always @ (*) begin - _zz_231_ = execute_MEMORY_WR; + _zz_198 = execute_MEMORY_WR; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_290_)begin - _zz_231_ = MmuPlugin_dBusAccess_cmd_payload_write; + if(_zz_264)begin + _zz_198 = MmuPlugin_dBusAccess_cmd_payload_write; end end end @@ -4722,98 +3779,98 @@ module VexRiscv ( always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_132_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_75 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_132_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_75 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_132_ = execute_RS2[31 : 0]; + _zz_75 = execute_RS2[31 : 0]; end endcase end always @ (*) begin - _zz_232_ = _zz_132_; + _zz_199 = _zz_75; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_290_)begin - _zz_232_ = MmuPlugin_dBusAccess_cmd_payload_data; + if(_zz_264)begin + _zz_199 = MmuPlugin_dBusAccess_cmd_payload_data; end end end always @ (*) begin - _zz_233_ = execute_DBusCachedPlugin_size; + _zz_200 = execute_DBusCachedPlugin_size; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_290_)begin - _zz_233_ = MmuPlugin_dBusAccess_cmd_payload_size; + if(_zz_264)begin + _zz_200 = MmuPlugin_dBusAccess_cmd_payload_size; end end end - assign _zz_244_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_220 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); always @ (*) begin - _zz_234_ = 1'b0; + _zz_201 = 1'b0; if(execute_MEMORY_LRSC)begin - _zz_234_ = 1'b1; + _zz_201 = 1'b1; end if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_290_)begin - _zz_234_ = 1'b0; + if(_zz_264)begin + _zz_201 = 1'b0; end end end always @ (*) begin - _zz_235_ = execute_MEMORY_AMO; + _zz_202 = execute_MEMORY_AMO; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_290_)begin - _zz_235_ = 1'b0; + if(_zz_264)begin + _zz_202 = 1'b0; end end end - assign _zz_237_ = execute_INSTRUCTION[31 : 29]; - assign _zz_236_ = execute_INSTRUCTION[27]; - assign _zz_88_ = _zz_230_[1 : 0]; + assign _zz_204 = execute_INSTRUCTION[31 : 29]; + assign _zz_203 = execute_INSTRUCTION[27]; always @ (*) begin - _zz_238_ = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + _zz_205 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); if(memory_IS_DBUS_SHARING)begin - _zz_238_ = 1'b1; + _zz_205 = 1'b1; end end - assign _zz_239_ = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; - assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + assign _zz_206 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_205; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_206; always @ (*) begin - DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; if(memory_IS_DBUS_SHARING)begin - DBusCachedPlugin_mmuBus_cmd_bypassTranslation = 1'b1; + DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; end end + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_240_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin - _zz_240_ = 1'b1; + _zz_207 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_207 = 1'b1; end end - assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; always @ (*) begin - _zz_241_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + _zz_208 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); if(writeBack_IS_DBUS_SHARING)begin - _zz_241_ = 1'b1; + _zz_208 = 1'b1; end end - assign _zz_242_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_243_ = writeBack_REGFILE_WRITE_DATA; + assign _zz_209 = (CsrPlugin_privilege == 2'b00); + assign _zz_210 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_292_)begin - if(dataCache_1__io_cpu_redo)begin + if(_zz_266)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end @@ -4822,17 +3879,17 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_292_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin + if(_zz_266)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1__io_cpu_redo)begin + if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end @@ -4840,94 +3897,94 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); - if(_zz_292_)begin - if(dataCache_1__io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_333_}; + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_266)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_331}; end - if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_334_}; + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1__io_cpu_writeBack_mmuException)begin - DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_332}; end end end always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; end 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; end 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; end default : begin end endcase end - assign _zz_133_ = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_134_[31] = _zz_133_; - _zz_134_[30] = _zz_133_; - _zz_134_[29] = _zz_133_; - _zz_134_[28] = _zz_133_; - _zz_134_[27] = _zz_133_; - _zz_134_[26] = _zz_133_; - _zz_134_[25] = _zz_133_; - _zz_134_[24] = _zz_133_; - _zz_134_[23] = _zz_133_; - _zz_134_[22] = _zz_133_; - _zz_134_[21] = _zz_133_; - _zz_134_[20] = _zz_133_; - _zz_134_[19] = _zz_133_; - _zz_134_[18] = _zz_133_; - _zz_134_[17] = _zz_133_; - _zz_134_[16] = _zz_133_; - _zz_134_[15] = _zz_133_; - _zz_134_[14] = _zz_133_; - _zz_134_[13] = _zz_133_; - _zz_134_[12] = _zz_133_; - _zz_134_[11] = _zz_133_; - _zz_134_[10] = _zz_133_; - _zz_134_[9] = _zz_133_; - _zz_134_[8] = _zz_133_; - _zz_134_[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_135_ = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_136_[31] = _zz_135_; - _zz_136_[30] = _zz_135_; - _zz_136_[29] = _zz_135_; - _zz_136_[28] = _zz_135_; - _zz_136_[27] = _zz_135_; - _zz_136_[26] = _zz_135_; - _zz_136_[25] = _zz_135_; - _zz_136_[24] = _zz_135_; - _zz_136_[23] = _zz_135_; - _zz_136_[22] = _zz_135_; - _zz_136_[21] = _zz_135_; - _zz_136_[20] = _zz_135_; - _zz_136_[19] = _zz_135_; - _zz_136_[18] = _zz_135_; - _zz_136_[17] = _zz_135_; - _zz_136_[16] = _zz_135_; - _zz_136_[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_328_) + assign _zz_76 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_77[31] = _zz_76; + _zz_77[30] = _zz_76; + _zz_77[29] = _zz_76; + _zz_77[28] = _zz_76; + _zz_77[27] = _zz_76; + _zz_77[26] = _zz_76; + _zz_77[25] = _zz_76; + _zz_77[24] = _zz_76; + _zz_77[23] = _zz_76; + _zz_77[22] = _zz_76; + _zz_77[21] = _zz_76; + _zz_77[20] = _zz_76; + _zz_77[19] = _zz_76; + _zz_77[18] = _zz_76; + _zz_77[17] = _zz_76; + _zz_77[16] = _zz_76; + _zz_77[15] = _zz_76; + _zz_77[14] = _zz_76; + _zz_77[13] = _zz_76; + _zz_77[12] = _zz_76; + _zz_77[11] = _zz_76; + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_78 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_79[31] = _zz_78; + _zz_79[30] = _zz_78; + _zz_79[29] = _zz_78; + _zz_79[28] = _zz_78; + _zz_79[27] = _zz_78; + _zz_79[26] = _zz_78; + _zz_79[25] = _zz_78; + _zz_79[24] = _zz_78; + _zz_79[23] = _zz_78; + _zz_79[22] = _zz_78; + _zz_79[21] = _zz_78; + _zz_79[20] = _zz_78; + _zz_79[19] = _zz_78; + _zz_79[18] = _zz_78; + _zz_79[17] = _zz_78; + _zz_79[16] = _zz_78; + _zz_79[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_303) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_134_; + writeBack_DBusCachedPlugin_rspFormated = _zz_77; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_136_; + writeBack_DBusCachedPlugin_rspFormated = _zz_79; end default : begin writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; @@ -4938,8 +3995,8 @@ module VexRiscv ( always @ (*) begin MmuPlugin_dBusAccess_cmd_ready = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_290_)begin - if(_zz_291_)begin + if(_zz_264)begin + if(_zz_265)begin MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); end end @@ -4949,229 +4006,272 @@ module VexRiscv ( always @ (*) begin DBusCachedPlugin_forceDatapath = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_290_)begin + if(_zz_264)begin DBusCachedPlugin_forceDatapath = 1'b1; end end end - assign _zz_86_ = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); - assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1__io_cpu_writeBack_isWrite)) && (dataCache_1__io_cpu_redo || (! dataCache_1__io_cpu_writeBack_haltIt))); - assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1__io_cpu_writeBack_data; - assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1__io_cpu_writeBack_unalignedAccess || dataCache_1__io_cpu_writeBack_accessError); - assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1__io_cpu_redo; - assign MmuPlugin_ports_0_cacheHits_0 = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHits_1 = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHits_2 = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHits_3 = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_0_cacheHit = ({MmuPlugin_ports_0_cacheHits_3,{MmuPlugin_ports_0_cacheHits_2,{MmuPlugin_ports_0_cacheHits_1,MmuPlugin_ports_0_cacheHits_0}}} != (4'b0000)); - assign _zz_137_ = (MmuPlugin_ports_0_cacheHits_1 || MmuPlugin_ports_0_cacheHits_3); - assign _zz_138_ = (MmuPlugin_ports_0_cacheHits_2 || MmuPlugin_ports_0_cacheHits_3); - assign _zz_139_ = {_zz_138_,_zz_137_}; - assign MmuPlugin_ports_0_cacheLine_valid = _zz_249_; - assign MmuPlugin_ports_0_cacheLine_exception = _zz_250_; - assign MmuPlugin_ports_0_cacheLine_superPage = _zz_251_; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_252_; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_253_; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_254_; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_255_; - assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_256_; - assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_257_; - assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_258_; - assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_259_; + assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); + assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1_io_cpu_writeBack_data; + assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); + assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; + assign MmuPlugin_ports_0_dirty = 1'b0; + always @ (*) begin + MmuPlugin_ports_0_requireMmuLockupCalc = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; + end + end + + always @ (*) begin + MmuPlugin_ports_0_cacheHitsCalc[0] = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[1] = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[2] = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_0_cacheHitsCalc[3] = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + end + + assign MmuPlugin_ports_0_cacheHit = (MmuPlugin_ports_0_cacheHitsCalc != 4'b0000); + assign _zz_80 = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign _zz_81 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_80); + assign _zz_82 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_80); + assign _zz_83 = {_zz_82,_zz_81}; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_225; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_226; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_227; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_228; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_229; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_230; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_231; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_232; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_233; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_234; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_235; always @ (*) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; - if(_zz_293_)begin - if(_zz_294_)begin + if(_zz_267)begin + if(_zz_268)begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; end end end assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; - assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == (2'b11)); + assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_336_); + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_334); if(MmuPlugin_ports_0_entryToReplace_willClear)begin - MmuPlugin_ports_0_entryToReplace_valueNext = (2'b00); + MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; end end always @ (*) begin - MmuPlugin_ports_0_requireMmuLockup = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == (2'b11))))begin - MmuPlugin_ports_0_requireMmuLockup = 1'b0; - end - if((CsrPlugin_privilege == (2'b11)))begin - if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == (2'b11))))begin - MmuPlugin_ports_0_requireMmuLockup = 1'b0; - end + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + end else begin + IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_virtualAddress[11 : 0]}; + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); end else begin - DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; end else begin - DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; end else begin - DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin - DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_exception = (MmuPlugin_ports_0_cacheHit && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == (2'b01))) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == (2'b00))))); + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); end else begin - DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockup)begin - DBusCachedPlugin_mmuBus_rsp_refilling = (! MmuPlugin_ports_0_cacheHit); + if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin - DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; end end - assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1011)) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1110))) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111))); - assign MmuPlugin_ports_1_cacheHits_0 = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHits_1 = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHits_2 = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHits_3 = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]))); - assign MmuPlugin_ports_1_cacheHit = ({MmuPlugin_ports_1_cacheHits_3,{MmuPlugin_ports_1_cacheHits_2,{MmuPlugin_ports_1_cacheHits_1,MmuPlugin_ports_1_cacheHits_0}}} != (4'b0000)); - assign _zz_140_ = (MmuPlugin_ports_1_cacheHits_1 || MmuPlugin_ports_1_cacheHits_3); - assign _zz_141_ = (MmuPlugin_ports_1_cacheHits_2 || MmuPlugin_ports_1_cacheHits_3); - assign _zz_142_ = {_zz_141_,_zz_140_}; - assign MmuPlugin_ports_1_cacheLine_valid = _zz_260_; - assign MmuPlugin_ports_1_cacheLine_exception = _zz_261_; - assign MmuPlugin_ports_1_cacheLine_superPage = _zz_262_; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_263_; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_264_; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_265_; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_266_; - assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_267_; - assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_268_; - assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_269_; - assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_270_; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1011) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1110)) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111)); + assign IBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_0_requireMmuLockupCalc); + assign IBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_0_cacheHitsCalc[0]; + assign IBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_0_cache_0_physicalAddress_1,(MmuPlugin_ports_0_cache_0_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_0_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_0_cacheHitsCalc[1]; + assign IBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_0_cache_1_physicalAddress_1,(MmuPlugin_ports_0_cache_1_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_1_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_0_cacheHitsCalc[2]; + assign IBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_0_cache_2_physicalAddress_1,(MmuPlugin_ports_0_cache_2_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_2_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_ports_1_dirty = 1'b0; always @ (*) begin - MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; - if(_zz_293_)begin - if(_zz_295_)begin - MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; + MmuPlugin_ports_1_requireMmuLockupCalc = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); + if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; + end + if((CsrPlugin_privilege == 2'b11))begin + if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)))begin + MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; end end end - assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; - assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == (2'b11)); - assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_338_); - if(MmuPlugin_ports_1_entryToReplace_willClear)begin - MmuPlugin_ports_1_entryToReplace_valueNext = (2'b00); - end + MmuPlugin_ports_1_cacheHitsCalc[0] = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[1] = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[2] = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); + MmuPlugin_ports_1_cacheHitsCalc[3] = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); end + assign MmuPlugin_ports_1_cacheHit = (MmuPlugin_ports_1_cacheHitsCalc != 4'b0000); + assign _zz_84 = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign _zz_85 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_84); + assign _zz_86 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_84); + assign _zz_87 = {_zz_86,_zz_85}; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_236; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_237; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_238; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_239; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_240; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_241; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_242; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_243; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_244; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_245; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_246; always @ (*) begin - MmuPlugin_ports_1_requireMmuLockup = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == (2'b11))))begin - MmuPlugin_ports_1_requireMmuLockup = 1'b0; + MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; + if(_zz_267)begin + if(_zz_269)begin + MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; + end end - if((CsrPlugin_privilege == (2'b11)))begin - MmuPlugin_ports_1_requireMmuLockup = 1'b0; + end + + assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; + assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); + always @ (*) begin + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_336); + if(MmuPlugin_ports_1_entryToReplace_willClear)begin + MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_virtualAddress[11 : 0]}; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; end else begin - IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); end else begin - IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; end else begin - IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; end else begin - IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_exception = (MmuPlugin_ports_1_cacheHit && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == (2'b01))) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == (2'b00))))); + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin - IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockup)begin - IBusCachedPlugin_mmuBus_rsp_refilling = (! MmuPlugin_ports_1_cacheHit); + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); end else begin - IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end - assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (((IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1011)) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1110))) || (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111))); - assign MmuPlugin_shared_dBusRsp_pte_V = _zz_339_[0]; - assign MmuPlugin_shared_dBusRsp_pte_R = _zz_340_[0]; - assign MmuPlugin_shared_dBusRsp_pte_W = _zz_341_[0]; - assign MmuPlugin_shared_dBusRsp_pte_X = _zz_342_[0]; - assign MmuPlugin_shared_dBusRsp_pte_U = _zz_343_[0]; - assign MmuPlugin_shared_dBusRsp_pte_G = _zz_344_[0]; - assign MmuPlugin_shared_dBusRsp_pte_A = _zz_345_[0]; - assign MmuPlugin_shared_dBusRsp_pte_D = _zz_346_[0]; - assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_dBusAccess_rsp_payload_data[9 : 8]; - assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_dBusAccess_rsp_payload_data[19 : 10]; - assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_dBusAccess_rsp_payload_data[31 : 20]; - assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_dBusAccess_rsp_payload_error); + always @ (*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; + end else begin + DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + end + end + + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (((DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1011) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1110)) || (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == 4'b1111)); + assign DBusCachedPlugin_mmuBus_rsp_bypassTranslation = (! MmuPlugin_ports_1_requireMmuLockupCalc); + assign DBusCachedPlugin_mmuBus_rsp_ways_0_sel = MmuPlugin_ports_1_cacheHitsCalc[0]; + assign DBusCachedPlugin_mmuBus_rsp_ways_0_physical = {{MmuPlugin_ports_1_cache_0_physicalAddress_1,(MmuPlugin_ports_1_cache_0_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_0_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_sel = MmuPlugin_ports_1_cacheHitsCalc[1]; + assign DBusCachedPlugin_mmuBus_rsp_ways_1_physical = {{MmuPlugin_ports_1_cache_1_physicalAddress_1,(MmuPlugin_ports_1_cache_1_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_1_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_sel = MmuPlugin_ports_1_cacheHitsCalc[2]; + assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; + assign MmuPlugin_shared_dBusRsp_pte_V = _zz_337[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = _zz_338[0]; + assign MmuPlugin_shared_dBusRsp_pte_W = _zz_339[0]; + assign MmuPlugin_shared_dBusRsp_pte_X = _zz_340[0]; + assign MmuPlugin_shared_dBusRsp_pte_U = _zz_341[0]; + assign MmuPlugin_shared_dBusRsp_pte_G = _zz_342[0]; + assign MmuPlugin_shared_dBusRsp_pte_A = _zz_343[0]; + assign MmuPlugin_shared_dBusRsp_pte_D = _zz_344[0]; + assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; + assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; + assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; + assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); always @ (*) begin MmuPlugin_dBusAccess_cmd_valid = 1'b0; - case(MmuPlugin_shared_state_1_) + case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin end `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin @@ -5188,91 +4288,99 @@ module VexRiscv ( end assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; - assign MmuPlugin_dBusAccess_cmd_payload_size = (2'b10); + assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; always @ (*) begin - MmuPlugin_dBusAccess_cmd_payload_address = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - case(MmuPlugin_shared_state_1_) + MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin end `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin - MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},(2'b00)}; + MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; end `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin end `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin - MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},(2'b00)}; + MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; end default : begin end endcase end - assign MmuPlugin_dBusAccess_cmd_payload_data = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - assign MmuPlugin_dBusAccess_cmd_payload_writeMask = (4'bxxxx); - assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1_ != `MmuPlugin_shared_State_defaultEncoding_IDLE) && (MmuPlugin_shared_portId == (1'b1))); - assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1_ != `MmuPlugin_shared_State_defaultEncoding_IDLE) && (MmuPlugin_shared_portId == (1'b0))); - assign _zz_144_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000000000000)); - assign _zz_145_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_146_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_147_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000100000000000000)); - assign _zz_148_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)); - assign _zz_149_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_150_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); - assign _zz_151_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_143_ = {(((decode_INSTRUCTION & _zz_459_) == (32'b00010000000000000000000000001000)) != (1'b0)),{({_zz_460_,_zz_461_} != (2'b00)),{(_zz_462_ != (1'b0)),{(_zz_463_ != _zz_464_),{_zz_465_,{_zz_466_,_zz_467_}}}}}}; - assign _zz_85_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_625_) == (32'b00000000000000000001000001110011)),{(_zz_626_ == _zz_627_),{_zz_628_,{_zz_629_,_zz_630_}}}}}}} != (25'b0000000000000000000000000)); - assign _zz_152_ = _zz_143_[1 : 0]; - assign _zz_84_ = _zz_152_; - assign _zz_83_ = _zz_347_[0]; - assign _zz_82_ = _zz_348_[0]; - assign _zz_153_ = _zz_143_[5 : 4]; - assign _zz_81_ = _zz_153_; - assign _zz_80_ = _zz_349_[0]; - assign _zz_79_ = _zz_350_[0]; - assign _zz_78_ = _zz_351_[0]; - assign _zz_77_ = _zz_352_[0]; - assign _zz_76_ = _zz_353_[0]; - assign _zz_75_ = _zz_354_[0]; - assign _zz_74_ = _zz_355_[0]; - assign _zz_154_ = _zz_143_[15 : 14]; - assign _zz_73_ = _zz_154_; - assign _zz_72_ = _zz_356_[0]; - assign _zz_155_ = _zz_143_[18 : 17]; - assign _zz_71_ = _zz_155_; - assign _zz_70_ = _zz_357_[0]; - assign _zz_69_ = _zz_358_[0]; - assign _zz_68_ = _zz_359_[0]; - assign _zz_67_ = _zz_360_[0]; - assign _zz_66_ = _zz_361_[0]; - assign _zz_65_ = _zz_362_[0]; - assign _zz_156_ = _zz_143_[26 : 25]; - assign _zz_64_ = _zz_156_; - assign _zz_157_ = _zz_143_[28 : 27]; - assign _zz_63_ = _zz_157_; - assign _zz_62_ = _zz_363_[0]; - assign _zz_158_ = _zz_143_[31 : 30]; - assign _zz_61_ = _zz_158_; - assign _zz_60_ = _zz_364_[0]; - assign _zz_59_ = _zz_365_[0]; - assign _zz_58_ = _zz_366_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; + always @ (*) begin + _zz_88[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); + _zz_88[1] = (((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)); + end + + assign _zz_89 = _zz_88; + always @ (*) begin + _zz_90[0] = _zz_89[1]; + _zz_90[1] = _zz_89[0]; + end + + assign _zz_91 = (_zz_90 & (~ _zz_345)); + always @ (*) begin + _zz_92[0] = _zz_91[1]; + _zz_92[1] = _zz_91[0]; + end + + assign MmuPlugin_shared_refills = _zz_92; + assign _zz_93 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); + assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[0]); + assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[1]); + assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_97 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); + assign _zz_98 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_99 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_100 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_101 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); + assign _zz_102 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); + assign _zz_94 = {(((decode_INSTRUCTION & _zz_458) == 32'h02004020) != 1'b0),{({_zz_102,_zz_101} != 2'b00),{({_zz_459,_zz_460} != 3'b000),{(_zz_461 != _zz_462),{_zz_463,{_zz_464,_zz_465}}}}}}; + assign _zz_103 = _zz_94[2 : 1]; + assign _zz_50 = _zz_103; + assign _zz_104 = _zz_94[7 : 6]; + assign _zz_49 = _zz_104; + assign _zz_105 = _zz_94[9 : 8]; + assign _zz_48 = _zz_105; + assign _zz_106 = _zz_94[23 : 22]; + assign _zz_47 = _zz_106; + assign _zz_107 = _zz_94[25 : 24]; + assign _zz_46 = _zz_107; + assign _zz_108 = _zz_94[27 : 26]; + assign _zz_45 = _zz_108; + assign _zz_109 = _zz_94[30 : 29]; + assign _zz_44 = _zz_109; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_246_; - assign decode_RegFilePlugin_rs2Data = _zz_247_; - assign _zz_57_ = decode_RegFilePlugin_rs1Data; - assign _zz_56_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_222; + assign decode_RegFilePlugin_rs2Data = _zz_223; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_54_ && writeBack_arbitration_isFiring); - if(_zz_159_)begin + lastStageRegFileWrite_valid = (_zz_42 && writeBack_arbitration_isFiring); + if(_zz_110)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_53_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_87_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_41[11 : 7]; + if(_zz_110)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_51; + if(_zz_110)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -5290,444 +4398,448 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_160_ = execute_IntAluPlugin_bitwise; + _zz_111 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_160_ = {31'd0, _zz_367_}; + _zz_111 = {31'd0, _zz_346}; end default : begin - _zz_160_ = execute_SRC_ADD_SUB; + _zz_111 = execute_SRC_ADD_SUB; end endcase end - assign _zz_51_ = _zz_160_; - assign _zz_49_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_161_ = execute_RS1; + _zz_112 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_161_ = {29'd0, _zz_368_}; + _zz_112 = {29'd0, _zz_347}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_161_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_112 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_161_ = {27'd0, _zz_369_}; + _zz_112 = {27'd0, _zz_348}; end endcase end - assign _zz_48_ = _zz_161_; - assign _zz_162_ = _zz_370_[11]; - always @ (*) begin - _zz_163_[19] = _zz_162_; - _zz_163_[18] = _zz_162_; - _zz_163_[17] = _zz_162_; - _zz_163_[16] = _zz_162_; - _zz_163_[15] = _zz_162_; - _zz_163_[14] = _zz_162_; - _zz_163_[13] = _zz_162_; - _zz_163_[12] = _zz_162_; - _zz_163_[11] = _zz_162_; - _zz_163_[10] = _zz_162_; - _zz_163_[9] = _zz_162_; - _zz_163_[8] = _zz_162_; - _zz_163_[7] = _zz_162_; - _zz_163_[6] = _zz_162_; - _zz_163_[5] = _zz_162_; - _zz_163_[4] = _zz_162_; - _zz_163_[3] = _zz_162_; - _zz_163_[2] = _zz_162_; - _zz_163_[1] = _zz_162_; - _zz_163_[0] = _zz_162_; - end - - assign _zz_164_ = _zz_371_[11]; - always @ (*) begin - _zz_165_[19] = _zz_164_; - _zz_165_[18] = _zz_164_; - _zz_165_[17] = _zz_164_; - _zz_165_[16] = _zz_164_; - _zz_165_[15] = _zz_164_; - _zz_165_[14] = _zz_164_; - _zz_165_[13] = _zz_164_; - _zz_165_[12] = _zz_164_; - _zz_165_[11] = _zz_164_; - _zz_165_[10] = _zz_164_; - _zz_165_[9] = _zz_164_; - _zz_165_[8] = _zz_164_; - _zz_165_[7] = _zz_164_; - _zz_165_[6] = _zz_164_; - _zz_165_[5] = _zz_164_; - _zz_165_[4] = _zz_164_; - _zz_165_[3] = _zz_164_; - _zz_165_[2] = _zz_164_; - _zz_165_[1] = _zz_164_; - _zz_165_[0] = _zz_164_; + assign _zz_113 = _zz_349[11]; + always @ (*) begin + _zz_114[19] = _zz_113; + _zz_114[18] = _zz_113; + _zz_114[17] = _zz_113; + _zz_114[16] = _zz_113; + _zz_114[15] = _zz_113; + _zz_114[14] = _zz_113; + _zz_114[13] = _zz_113; + _zz_114[12] = _zz_113; + _zz_114[11] = _zz_113; + _zz_114[10] = _zz_113; + _zz_114[9] = _zz_113; + _zz_114[8] = _zz_113; + _zz_114[7] = _zz_113; + _zz_114[6] = _zz_113; + _zz_114[5] = _zz_113; + _zz_114[4] = _zz_113; + _zz_114[3] = _zz_113; + _zz_114[2] = _zz_113; + _zz_114[1] = _zz_113; + _zz_114[0] = _zz_113; + end + + assign _zz_115 = _zz_350[11]; + always @ (*) begin + _zz_116[19] = _zz_115; + _zz_116[18] = _zz_115; + _zz_116[17] = _zz_115; + _zz_116[16] = _zz_115; + _zz_116[15] = _zz_115; + _zz_116[14] = _zz_115; + _zz_116[13] = _zz_115; + _zz_116[12] = _zz_115; + _zz_116[11] = _zz_115; + _zz_116[10] = _zz_115; + _zz_116[9] = _zz_115; + _zz_116[8] = _zz_115; + _zz_116[7] = _zz_115; + _zz_116[6] = _zz_115; + _zz_116[5] = _zz_115; + _zz_116[4] = _zz_115; + _zz_116[3] = _zz_115; + _zz_116[2] = _zz_115; + _zz_116[1] = _zz_115; + _zz_116[0] = _zz_115; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_166_ = execute_RS2; + _zz_117 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_166_ = {_zz_163_,execute_INSTRUCTION[31 : 20]}; + _zz_117 = {_zz_114,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_166_ = {_zz_165_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_117 = {_zz_116,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_166_ = _zz_44_; + _zz_117 = _zz_36; end endcase end - assign _zz_46_ = _zz_166_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_372_; + execute_SrcPlugin_addSub = _zz_351; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_43_ = execute_SrcPlugin_addSub; - assign _zz_42_ = execute_SrcPlugin_addSub; - assign _zz_41_ = execute_SrcPlugin_less; assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_167_[0] = execute_SRC1[31]; - _zz_167_[1] = execute_SRC1[30]; - _zz_167_[2] = execute_SRC1[29]; - _zz_167_[3] = execute_SRC1[28]; - _zz_167_[4] = execute_SRC1[27]; - _zz_167_[5] = execute_SRC1[26]; - _zz_167_[6] = execute_SRC1[25]; - _zz_167_[7] = execute_SRC1[24]; - _zz_167_[8] = execute_SRC1[23]; - _zz_167_[9] = execute_SRC1[22]; - _zz_167_[10] = execute_SRC1[21]; - _zz_167_[11] = execute_SRC1[20]; - _zz_167_[12] = execute_SRC1[19]; - _zz_167_[13] = execute_SRC1[18]; - _zz_167_[14] = execute_SRC1[17]; - _zz_167_[15] = execute_SRC1[16]; - _zz_167_[16] = execute_SRC1[15]; - _zz_167_[17] = execute_SRC1[14]; - _zz_167_[18] = execute_SRC1[13]; - _zz_167_[19] = execute_SRC1[12]; - _zz_167_[20] = execute_SRC1[11]; - _zz_167_[21] = execute_SRC1[10]; - _zz_167_[22] = execute_SRC1[9]; - _zz_167_[23] = execute_SRC1[8]; - _zz_167_[24] = execute_SRC1[7]; - _zz_167_[25] = execute_SRC1[6]; - _zz_167_[26] = execute_SRC1[5]; - _zz_167_[27] = execute_SRC1[4]; - _zz_167_[28] = execute_SRC1[3]; - _zz_167_[29] = execute_SRC1[2]; - _zz_167_[30] = execute_SRC1[1]; - _zz_167_[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_167_ : execute_SRC1); - assign _zz_39_ = _zz_380_; - always @ (*) begin - _zz_168_[0] = memory_SHIFT_RIGHT[31]; - _zz_168_[1] = memory_SHIFT_RIGHT[30]; - _zz_168_[2] = memory_SHIFT_RIGHT[29]; - _zz_168_[3] = memory_SHIFT_RIGHT[28]; - _zz_168_[4] = memory_SHIFT_RIGHT[27]; - _zz_168_[5] = memory_SHIFT_RIGHT[26]; - _zz_168_[6] = memory_SHIFT_RIGHT[25]; - _zz_168_[7] = memory_SHIFT_RIGHT[24]; - _zz_168_[8] = memory_SHIFT_RIGHT[23]; - _zz_168_[9] = memory_SHIFT_RIGHT[22]; - _zz_168_[10] = memory_SHIFT_RIGHT[21]; - _zz_168_[11] = memory_SHIFT_RIGHT[20]; - _zz_168_[12] = memory_SHIFT_RIGHT[19]; - _zz_168_[13] = memory_SHIFT_RIGHT[18]; - _zz_168_[14] = memory_SHIFT_RIGHT[17]; - _zz_168_[15] = memory_SHIFT_RIGHT[16]; - _zz_168_[16] = memory_SHIFT_RIGHT[15]; - _zz_168_[17] = memory_SHIFT_RIGHT[14]; - _zz_168_[18] = memory_SHIFT_RIGHT[13]; - _zz_168_[19] = memory_SHIFT_RIGHT[12]; - _zz_168_[20] = memory_SHIFT_RIGHT[11]; - _zz_168_[21] = memory_SHIFT_RIGHT[10]; - _zz_168_[22] = memory_SHIFT_RIGHT[9]; - _zz_168_[23] = memory_SHIFT_RIGHT[8]; - _zz_168_[24] = memory_SHIFT_RIGHT[7]; - _zz_168_[25] = memory_SHIFT_RIGHT[6]; - _zz_168_[26] = memory_SHIFT_RIGHT[5]; - _zz_168_[27] = memory_SHIFT_RIGHT[4]; - _zz_168_[28] = memory_SHIFT_RIGHT[3]; - _zz_168_[29] = memory_SHIFT_RIGHT[2]; - _zz_168_[30] = memory_SHIFT_RIGHT[1]; - _zz_168_[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_169_ = 1'b0; - if(_zz_296_)begin - if(_zz_297_)begin - if(_zz_175_)begin - _zz_169_ = 1'b1; - end - end - end - if(_zz_298_)begin - if(_zz_299_)begin - if(_zz_177_)begin - _zz_169_ = 1'b1; - end - end - end - if(_zz_300_)begin - if(_zz_301_)begin - if(_zz_179_)begin - _zz_169_ = 1'b1; + _zz_118[0] = execute_SRC1[31]; + _zz_118[1] = execute_SRC1[30]; + _zz_118[2] = execute_SRC1[29]; + _zz_118[3] = execute_SRC1[28]; + _zz_118[4] = execute_SRC1[27]; + _zz_118[5] = execute_SRC1[26]; + _zz_118[6] = execute_SRC1[25]; + _zz_118[7] = execute_SRC1[24]; + _zz_118[8] = execute_SRC1[23]; + _zz_118[9] = execute_SRC1[22]; + _zz_118[10] = execute_SRC1[21]; + _zz_118[11] = execute_SRC1[20]; + _zz_118[12] = execute_SRC1[19]; + _zz_118[13] = execute_SRC1[18]; + _zz_118[14] = execute_SRC1[17]; + _zz_118[15] = execute_SRC1[16]; + _zz_118[16] = execute_SRC1[15]; + _zz_118[17] = execute_SRC1[14]; + _zz_118[18] = execute_SRC1[13]; + _zz_118[19] = execute_SRC1[12]; + _zz_118[20] = execute_SRC1[11]; + _zz_118[21] = execute_SRC1[10]; + _zz_118[22] = execute_SRC1[9]; + _zz_118[23] = execute_SRC1[8]; + _zz_118[24] = execute_SRC1[7]; + _zz_118[25] = execute_SRC1[6]; + _zz_118[26] = execute_SRC1[5]; + _zz_118[27] = execute_SRC1[4]; + _zz_118[28] = execute_SRC1[3]; + _zz_118[29] = execute_SRC1[2]; + _zz_118[30] = execute_SRC1[1]; + _zz_118[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_118 : execute_SRC1); + always @ (*) begin + _zz_119[0] = memory_SHIFT_RIGHT[31]; + _zz_119[1] = memory_SHIFT_RIGHT[30]; + _zz_119[2] = memory_SHIFT_RIGHT[29]; + _zz_119[3] = memory_SHIFT_RIGHT[28]; + _zz_119[4] = memory_SHIFT_RIGHT[27]; + _zz_119[5] = memory_SHIFT_RIGHT[26]; + _zz_119[6] = memory_SHIFT_RIGHT[25]; + _zz_119[7] = memory_SHIFT_RIGHT[24]; + _zz_119[8] = memory_SHIFT_RIGHT[23]; + _zz_119[9] = memory_SHIFT_RIGHT[22]; + _zz_119[10] = memory_SHIFT_RIGHT[21]; + _zz_119[11] = memory_SHIFT_RIGHT[20]; + _zz_119[12] = memory_SHIFT_RIGHT[19]; + _zz_119[13] = memory_SHIFT_RIGHT[18]; + _zz_119[14] = memory_SHIFT_RIGHT[17]; + _zz_119[15] = memory_SHIFT_RIGHT[16]; + _zz_119[16] = memory_SHIFT_RIGHT[15]; + _zz_119[17] = memory_SHIFT_RIGHT[14]; + _zz_119[18] = memory_SHIFT_RIGHT[13]; + _zz_119[19] = memory_SHIFT_RIGHT[12]; + _zz_119[20] = memory_SHIFT_RIGHT[11]; + _zz_119[21] = memory_SHIFT_RIGHT[10]; + _zz_119[22] = memory_SHIFT_RIGHT[9]; + _zz_119[23] = memory_SHIFT_RIGHT[8]; + _zz_119[24] = memory_SHIFT_RIGHT[7]; + _zz_119[25] = memory_SHIFT_RIGHT[6]; + _zz_119[26] = memory_SHIFT_RIGHT[5]; + _zz_119[27] = memory_SHIFT_RIGHT[4]; + _zz_119[28] = memory_SHIFT_RIGHT[3]; + _zz_119[29] = memory_SHIFT_RIGHT[2]; + _zz_119[30] = memory_SHIFT_RIGHT[1]; + _zz_119[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_270)begin + if(_zz_271)begin + if(_zz_120)begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(_zz_272)begin + if(_zz_273)begin + if(_zz_122)begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(_zz_274)begin + if(_zz_275)begin + if(_zz_124)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_169_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_170_ = 1'b0; - if(_zz_296_)begin - if(_zz_297_)begin - if(_zz_176_)begin - _zz_170_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_270)begin + if(_zz_271)begin + if(_zz_121)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_298_)begin - if(_zz_299_)begin - if(_zz_178_)begin - _zz_170_ = 1'b1; + if(_zz_272)begin + if(_zz_273)begin + if(_zz_123)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_300_)begin - if(_zz_301_)begin - if(_zz_180_)begin - _zz_170_ = 1'b1; + if(_zz_274)begin + if(_zz_275)begin + if(_zz_125)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_170_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_171_ = (_zz_54_ && writeBack_arbitration_isFiring); - assign _zz_175_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_176_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_177_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_178_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_179_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_180_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_42 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_41[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_51; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_120 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_121 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_122 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_123 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_124 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_125 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_181_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_181_ == (3'b000))) begin - _zz_182_ = execute_BranchPlugin_eq; - end else if((_zz_181_ == (3'b001))) begin - _zz_182_ = (! execute_BranchPlugin_eq); - end else if((((_zz_181_ & (3'b101)) == (3'b101)))) begin - _zz_182_ = (! execute_SRC_LESS); + assign _zz_126 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_126 == 3'b000)) begin + _zz_127 = execute_BranchPlugin_eq; + end else if((_zz_126 == 3'b001)) begin + _zz_127 = (! execute_BranchPlugin_eq); + end else if((((_zz_126 & 3'b101) == 3'b101))) begin + _zz_127 = (! execute_SRC_LESS); end else begin - _zz_182_ = execute_SRC_LESS; + _zz_127 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_183_ = 1'b0; + _zz_128 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_183_ = 1'b1; + _zz_128 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_183_ = 1'b1; + _zz_128 = 1'b1; end default : begin - _zz_183_ = _zz_182_; + _zz_128 = _zz_127; end endcase end - assign _zz_35_ = _zz_183_; assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_184_ = _zz_382_[19]; - always @ (*) begin - _zz_185_[10] = _zz_184_; - _zz_185_[9] = _zz_184_; - _zz_185_[8] = _zz_184_; - _zz_185_[7] = _zz_184_; - _zz_185_[6] = _zz_184_; - _zz_185_[5] = _zz_184_; - _zz_185_[4] = _zz_184_; - _zz_185_[3] = _zz_184_; - _zz_185_[2] = _zz_184_; - _zz_185_[1] = _zz_184_; - _zz_185_[0] = _zz_184_; - end - - assign _zz_186_ = _zz_383_[11]; - always @ (*) begin - _zz_187_[19] = _zz_186_; - _zz_187_[18] = _zz_186_; - _zz_187_[17] = _zz_186_; - _zz_187_[16] = _zz_186_; - _zz_187_[15] = _zz_186_; - _zz_187_[14] = _zz_186_; - _zz_187_[13] = _zz_186_; - _zz_187_[12] = _zz_186_; - _zz_187_[11] = _zz_186_; - _zz_187_[10] = _zz_186_; - _zz_187_[9] = _zz_186_; - _zz_187_[8] = _zz_186_; - _zz_187_[7] = _zz_186_; - _zz_187_[6] = _zz_186_; - _zz_187_[5] = _zz_186_; - _zz_187_[4] = _zz_186_; - _zz_187_[3] = _zz_186_; - _zz_187_[2] = _zz_186_; - _zz_187_[1] = _zz_186_; - _zz_187_[0] = _zz_186_; - end - - assign _zz_188_ = _zz_384_[11]; - always @ (*) begin - _zz_189_[18] = _zz_188_; - _zz_189_[17] = _zz_188_; - _zz_189_[16] = _zz_188_; - _zz_189_[15] = _zz_188_; - _zz_189_[14] = _zz_188_; - _zz_189_[13] = _zz_188_; - _zz_189_[12] = _zz_188_; - _zz_189_[11] = _zz_188_; - _zz_189_[10] = _zz_188_; - _zz_189_[9] = _zz_188_; - _zz_189_[8] = _zz_188_; - _zz_189_[7] = _zz_188_; - _zz_189_[6] = _zz_188_; - _zz_189_[5] = _zz_188_; - _zz_189_[4] = _zz_188_; - _zz_189_[3] = _zz_188_; - _zz_189_[2] = _zz_188_; - _zz_189_[1] = _zz_188_; - _zz_189_[0] = _zz_188_; + assign _zz_129 = _zz_358[19]; + always @ (*) begin + _zz_130[10] = _zz_129; + _zz_130[9] = _zz_129; + _zz_130[8] = _zz_129; + _zz_130[7] = _zz_129; + _zz_130[6] = _zz_129; + _zz_130[5] = _zz_129; + _zz_130[4] = _zz_129; + _zz_130[3] = _zz_129; + _zz_130[2] = _zz_129; + _zz_130[1] = _zz_129; + _zz_130[0] = _zz_129; + end + + assign _zz_131 = _zz_359[11]; + always @ (*) begin + _zz_132[19] = _zz_131; + _zz_132[18] = _zz_131; + _zz_132[17] = _zz_131; + _zz_132[16] = _zz_131; + _zz_132[15] = _zz_131; + _zz_132[14] = _zz_131; + _zz_132[13] = _zz_131; + _zz_132[12] = _zz_131; + _zz_132[11] = _zz_131; + _zz_132[10] = _zz_131; + _zz_132[9] = _zz_131; + _zz_132[8] = _zz_131; + _zz_132[7] = _zz_131; + _zz_132[6] = _zz_131; + _zz_132[5] = _zz_131; + _zz_132[4] = _zz_131; + _zz_132[3] = _zz_131; + _zz_132[2] = _zz_131; + _zz_132[1] = _zz_131; + _zz_132[0] = _zz_131; + end + + assign _zz_133 = _zz_360[11]; + always @ (*) begin + _zz_134[18] = _zz_133; + _zz_134[17] = _zz_133; + _zz_134[16] = _zz_133; + _zz_134[15] = _zz_133; + _zz_134[14] = _zz_133; + _zz_134[13] = _zz_133; + _zz_134[12] = _zz_133; + _zz_134[11] = _zz_133; + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_190_ = {{_zz_185_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_135 = {{_zz_130,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_190_ = {_zz_187_,execute_INSTRUCTION[31 : 20]}; + _zz_135 = {_zz_132,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_190_ = {{_zz_189_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_135 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_190_; + assign execute_BranchPlugin_branch_src2 = _zz_135; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_33_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; always @ (*) begin - CsrPlugin_privilege = _zz_191_; + CsrPlugin_privilege = _zz_136; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign CsrPlugin_misa_base = (2'b01); - assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0; assign CsrPlugin_sip_SEIP_OR = (CsrPlugin_sip_SEIP_SOFT || CsrPlugin_sip_SEIP_INPUT); - assign _zz_192_ = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); - assign _zz_193_ = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); - assign _zz_194_ = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); - assign _zz_195_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_196_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_197_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + always @ (*) begin + CsrPlugin_redoInterface_valid = 1'b0; + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + CsrPlugin_redoInterface_valid = 1'b1; + end + end + end + + assign CsrPlugin_redoInterface_payload = decode_PC; + assign _zz_137 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_138 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_139 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_140 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_141 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_142 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) - 4'b1000 : begin - if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0000 : begin + if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; + end + end + 4'b0001 : begin + if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0010 : begin if(((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0101 : begin - if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0100 : begin + if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b1101 : begin - if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0101 : begin + if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0100 : begin - if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b0110 : begin + if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0111 : begin if(((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0001 : begin - if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b1000 : begin + if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1001 : begin if(((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1100 : begin if(((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); - end - end - 4'b1111 : begin - if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0110 : begin - if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b1101 : begin + if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end - 4'b0000 : begin - if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin - CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b01); + 4'b1111 : begin + if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin + CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end default : begin @@ -5736,11 +4848,11 @@ module VexRiscv ( end assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_198_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_199_ = _zz_385_[0]; + assign _zz_143 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_144 = _zz_361[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_282_)begin + if(_zz_258)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -5783,9 +4895,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -5809,7 +4922,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_mode = CsrPlugin_stvec_mode; @@ -5823,7 +4936,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_base = CsrPlugin_stvec_base; @@ -5837,131 +4950,118 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_31_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_30_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - always @ (*) begin - execute_CsrPlugin_inWfi = 1'b0; - if(_zz_283_)begin - execute_CsrPlugin_inWfi = 1'b1; - end - end - - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000011 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111100010001 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000010 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b111100010100 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b100111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b000100000000 : begin + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000010 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000001 : begin + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_256)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_384)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000110000000 : begin + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110011000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000001 : begin + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000100 : begin + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000100000101 : begin + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000000 : begin + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_770)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b111100010010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000011 : begin + end + if(execute_CsrPlugin_csr_771)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b110111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000101000000 : begin + end + if(execute_CsrPlugin_csr_324)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_260)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_261)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_321)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_320)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_322)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_323)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b000100000100 : begin + end + if(execute_CsrPlugin_csr_2496)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3520)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_276)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -5980,29 +5080,29 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_302_)begin + if(_zz_277)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_303_)begin + if(_zz_278)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_302_)begin - CsrPlugin_selfException_payload_code = (4'b0010); + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_277)begin + CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_303_)begin + if(_zz_278)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end 2'b01 : begin - CsrPlugin_selfException_payload_code = (4'b1001); + CsrPlugin_selfException_payload_code = 4'b1001; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -6010,145 +5110,33 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_207_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[19 : 19] = MmuPlugin_status_mxr; - execute_CsrPlugin_readData[18 : 18] = MmuPlugin_status_sum; - execute_CsrPlugin_readData[17 : 17] = MmuPlugin_status_mprv; - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - execute_CsrPlugin_readData[8 : 8] = CsrPlugin_sstatus_SPP; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sstatus_SPIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sstatus_SIE; - end - 12'b001100000011 : begin - end - 12'b111100010001 : begin - execute_CsrPlugin_readData[0 : 0] = (1'b1); - end - 12'b000101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_scause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_scause_exceptionCode; - end - 12'b111100010100 : begin - end - 12'b100111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_209_; - end - 12'b000100000000 : begin - execute_CsrPlugin_readData[19 : 19] = MmuPlugin_status_mxr; - execute_CsrPlugin_readData[18 : 18] = MmuPlugin_status_sum; - execute_CsrPlugin_readData[17 : 17] = MmuPlugin_status_mprv; - execute_CsrPlugin_readData[8 : 8] = CsrPlugin_sstatus_SPP; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sstatus_SPIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sstatus_SIE; - end - 12'b001100000010 : begin - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sip_STIP; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sip_SSIP; - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sip_SEIP_OR; - end - 12'b001100000101 : begin - end - 12'b000110000000 : begin - execute_CsrPlugin_readData[31 : 31] = MmuPlugin_satp_mode; - execute_CsrPlugin_readData[19 : 0] = MmuPlugin_satp_ppn; - end - 12'b110011000000 : begin - execute_CsrPlugin_readData[12 : 0] = (13'b1000000000000); - execute_CsrPlugin_readData[25 : 20] = (6'b100000); - end - 12'b000101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_sepc; - end - 12'b111100010011 : begin - execute_CsrPlugin_readData[1 : 0] = (2'b11); - end - 12'b000101000100 : begin - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sip_STIP; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sip_SSIP; - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sip_SEIP_OR; - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b000100000101 : begin - execute_CsrPlugin_readData[31 : 2] = CsrPlugin_stvec_base; - execute_CsrPlugin_readData[1 : 0] = CsrPlugin_stvec_mode; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_208_; - end - 12'b001101000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sie_SEIE; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sie_STIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sie_SSIE; - end - 12'b111100010010 : begin - execute_CsrPlugin_readData[1 : 0] = (2'b10); - end - 12'b000101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_stval; - end - 12'b110111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_210_; - end - 12'b000101000000 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_sscratch; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - 12'b000100000100 : begin - execute_CsrPlugin_readData[9 : 9] = CsrPlugin_sie_SEIE; - execute_CsrPlugin_readData[5 : 5] = CsrPlugin_sie_STIE; - execute_CsrPlugin_readData[1 : 1] = CsrPlugin_sie_SSIE; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_276)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_276)begin + execute_CsrPlugin_readInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); always @ (*) begin execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - case(execute_CsrPlugin_csrAddress) - 12'b001101000100 : begin - execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; - end - 12'b000101000100 : begin - execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; - end - default : begin - end - endcase + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; + end + if(execute_CsrPlugin_csr_324)begin + execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; + end end always @ (*) begin - case(_zz_329_) + case(_zz_304) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -6159,10 +5147,11 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; always @ (*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_276_)begin - if(_zz_284_)begin + if(_zz_252)begin + if(_zz_260)begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end @@ -6175,23 +5164,23 @@ module VexRiscv ( end end - assign memory_MulDivIterativePlugin_mul_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == (6'b100000)); - assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); + assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); + assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); always @ (*) begin if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_388_); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_364); end if(memory_MulDivIterativePlugin_mul_counter_willClear)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end end always @ (*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_277_)begin - if(_zz_285_)begin + if(_zz_253)begin + if(_zz_279)begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end @@ -6199,70 +5188,72 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_304_)begin + if(_zz_280)begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end - assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == (6'b100001)); + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); always @ (*) begin if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin - memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_396_); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_372); end if(memory_MulDivIterativePlugin_div_counter_willClear)begin - memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000); - end - end - - assign _zz_200_ = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign _zz_201_ = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_200_[31]}; - assign _zz_202_ = (_zz_201_ - _zz_397_); - assign _zz_203_ = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_204_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_205_ = ((execute_IS_MUL && _zz_204_) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_206_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_206_[31 : 0] = execute_RS1; - end - - assign _zz_208_ = (_zz_207_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_208_ != (32'b00000000000000000000000000000000)); - assign _zz_210_ = (_zz_209_ & externalInterruptArray_regNext); - assign externalInterruptS = (_zz_210_ != (32'b00000000000000000000000000000000)); - assign _zz_27_ = decode_SRC2_CTRL; - assign _zz_25_ = _zz_73_; - assign _zz_45_ = decode_to_execute_SRC2_CTRL; - assign _zz_24_ = decode_SHIFT_CTRL; - assign _zz_21_ = execute_SHIFT_CTRL; - assign _zz_22_ = _zz_63_; - assign _zz_40_ = decode_to_execute_SHIFT_CTRL; - assign _zz_38_ = execute_to_memory_SHIFT_CTRL; - assign _zz_19_ = decode_ALU_CTRL; - assign _zz_17_ = _zz_64_; - assign _zz_50_ = decode_to_execute_ALU_CTRL; - assign _zz_16_ = decode_SRC1_CTRL; - assign _zz_14_ = _zz_61_; - assign _zz_47_ = decode_to_execute_SRC1_CTRL; - assign _zz_13_ = decode_BRANCH_CTRL; - assign _zz_11_ = _zz_81_; - assign _zz_34_ = decode_to_execute_BRANCH_CTRL; - assign _zz_10_ = decode_ENV_CTRL; - assign _zz_7_ = execute_ENV_CTRL; - assign _zz_5_ = memory_ENV_CTRL; - assign _zz_8_ = _zz_84_; - assign _zz_29_ = decode_to_execute_ENV_CTRL; - assign _zz_28_ = execute_to_memory_ENV_CTRL; - assign _zz_32_ = memory_to_writeBack_ENV_CTRL; - assign _zz_3_ = decode_ALU_BITWISE_CTRL; - assign _zz_1_ = _zz_71_; - assign _zz_52_ = decode_to_execute_ALU_BITWISE_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_145 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_145[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_373); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_374 : _zz_375); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_376[31:0]; + assign _zz_146 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_147 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_148 = ((execute_IS_MUL && _zz_147) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_149[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_149[31 : 0] = execute_RS1; + end + + assign _zz_151 = (_zz_150 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_151 != 32'h0); + assign _zz_153 = (_zz_152 & externalInterruptArray_regNext); + assign externalInterruptS = (_zz_153 != 32'h0); + assign _zz_27 = decode_SRC1_CTRL; + assign _zz_25 = _zz_50; + assign _zz_38 = decode_to_execute_SRC1_CTRL; + assign _zz_24 = decode_ALU_CTRL; + assign _zz_22 = _zz_49; + assign _zz_39 = decode_to_execute_ALU_CTRL; + assign _zz_21 = decode_SRC2_CTRL; + assign _zz_19 = _zz_48; + assign _zz_37 = decode_to_execute_SRC2_CTRL; + assign _zz_18 = decode_ALU_BITWISE_CTRL; + assign _zz_16 = _zz_47; + assign _zz_40 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_15 = decode_SHIFT_CTRL; + assign _zz_12 = execute_SHIFT_CTRL; + assign _zz_13 = _zz_46; + assign _zz_35 = decode_to_execute_SHIFT_CTRL; + assign _zz_34 = execute_to_memory_SHIFT_CTRL; + assign _zz_10 = decode_BRANCH_CTRL; + assign _zz_8 = _zz_45; + assign _zz_31 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_44; + assign _zz_29 = decode_to_execute_ENV_CTRL; + assign _zz_28 = execute_to_memory_ENV_CTRL; + assign _zz_30 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -6279,101 +5270,304 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign iBusWishbone_ADR = {_zz_455_,_zz_211_}; - assign iBusWishbone_CTI = ((_zz_211_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); - assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); always @ (*) begin - iBusWishbone_CYC = 1'b0; - if(_zz_305_)begin - iBusWishbone_CYC = 1'b1; + _zz_154 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_154[12 : 0] = 13'h1000; + _zz_154[25 : 20] = 6'h20; end end always @ (*) begin - iBusWishbone_STB = 1'b0; - if(_zz_305_)begin - iBusWishbone_STB = 1'b1; + _zz_155 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_155[19 : 19] = MmuPlugin_status_mxr; + _zz_155[18 : 18] = MmuPlugin_status_sum; + _zz_155[17 : 17] = MmuPlugin_status_mprv; + _zz_155[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_155[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_155[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_155[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_155[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_155[1 : 1] = CsrPlugin_sstatus_SIE; end end - assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_212_; - assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; - assign iBus_rsp_payload_error = 1'b0; - assign _zz_218_ = (dBus_cmd_payload_length != (3'b000)); - assign _zz_214_ = dBus_cmd_valid; - assign _zz_216_ = dBus_cmd_payload_wr; - assign _zz_217_ = (_zz_213_ == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_215_ && (_zz_216_ || _zz_217_)); - assign dBusWishbone_ADR = ((_zz_218_ ? {{dBus_cmd_payload_address[31 : 5],_zz_213_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); - assign dBusWishbone_CTI = (_zz_218_ ? (_zz_217_ ? (3'b111) : (3'b010)) : (3'b000)); - assign dBusWishbone_BTE = (2'b00); - assign dBusWishbone_SEL = (_zz_216_ ? dBus_cmd_payload_mask : (4'b1111)); - assign dBusWishbone_WE = _zz_216_; - assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_215_ = (_zz_214_ && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_214_; - assign dBusWishbone_STB = _zz_214_; - assign dBus_rsp_valid = _zz_219_; - assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; - assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin - if(reset) begin - IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; - IBusCachedPlugin_fetchPc_booted <= 1'b0; - IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_109_ <= 1'b0; - _zz_111_ <= 1'b0; - _zz_114_ <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_116_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_117_ <= 1'b0; - _zz_124_ <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_131_; - DBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - MmuPlugin_status_sum <= 1'b0; - MmuPlugin_status_mxr <= 1'b0; - MmuPlugin_status_mprv <= 1'b0; - MmuPlugin_satp_mode <= 1'b0; - MmuPlugin_ports_0_cache_0_valid <= 1'b0; - MmuPlugin_ports_0_cache_1_valid <= 1'b0; - MmuPlugin_ports_0_cache_2_valid <= 1'b0; - MmuPlugin_ports_0_cache_3_valid <= 1'b0; - MmuPlugin_ports_0_entryToReplace_value <= (2'b00); - MmuPlugin_ports_1_cache_0_valid <= 1'b0; - MmuPlugin_ports_1_cache_1_valid <= 1'b0; - MmuPlugin_ports_1_cache_2_valid <= 1'b0; - MmuPlugin_ports_1_cache_3_valid <= 1'b0; - MmuPlugin_ports_1_entryToReplace_value <= (2'b00); - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE; - _zz_159_ <= 1'b1; - _zz_172_ <= 1'b0; - _zz_191_ <= (2'b11); - CsrPlugin_mstatus_MIE <= 1'b0; - CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); - CsrPlugin_mie_MEIE <= 1'b0; - CsrPlugin_mie_MTIE <= 1'b0; - CsrPlugin_mie_MSIE <= 1'b0; - CsrPlugin_medeleg_IAM <= 1'b0; - CsrPlugin_medeleg_IAF <= 1'b0; - CsrPlugin_medeleg_II <= 1'b0; - CsrPlugin_medeleg_LAM <= 1'b0; - CsrPlugin_medeleg_LAF <= 1'b0; - CsrPlugin_medeleg_SAM <= 1'b0; - CsrPlugin_medeleg_SAF <= 1'b0; - CsrPlugin_medeleg_EU <= 1'b0; - CsrPlugin_medeleg_ES <= 1'b0; + always @ (*) begin + _zz_156 = 32'h0; + if(execute_CsrPlugin_csr_256)begin + _zz_156[19 : 19] = MmuPlugin_status_mxr; + _zz_156[18 : 18] = MmuPlugin_status_sum; + _zz_156[17 : 17] = MmuPlugin_status_mprv; + _zz_156[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_156[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_156[1 : 1] = CsrPlugin_sstatus_SIE; + end + end + + always @ (*) begin + _zz_157 = 32'h0; + if(execute_CsrPlugin_csr_384)begin + _zz_157[31 : 31] = MmuPlugin_satp_mode; + _zz_157[30 : 22] = MmuPlugin_satp_asid; + _zz_157[19 : 0] = MmuPlugin_satp_ppn; + end + end + + always @ (*) begin + _zz_158 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_158[0 : 0] = 1'b1; + end + end + + always @ (*) begin + _zz_159 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_159[1 : 0] = 2'b10; + end + end + + always @ (*) begin + _zz_160 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_160[1 : 0] = 2'b11; + end + end + + always @ (*) begin + _zz_161 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_161[11 : 11] = CsrPlugin_mip_MEIP; + _zz_161[7 : 7] = CsrPlugin_mip_MTIP; + _zz_161[3 : 3] = CsrPlugin_mip_MSIP; + _zz_161[5 : 5] = CsrPlugin_sip_STIP; + _zz_161[1 : 1] = CsrPlugin_sip_SSIP; + _zz_161[9 : 9] = CsrPlugin_sip_SEIP_OR; + end + end + + always @ (*) begin + _zz_162 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_162[11 : 11] = CsrPlugin_mie_MEIE; + _zz_162[7 : 7] = CsrPlugin_mie_MTIE; + _zz_162[3 : 3] = CsrPlugin_mie_MSIE; + _zz_162[9 : 9] = CsrPlugin_sie_SEIE; + _zz_162[5 : 5] = CsrPlugin_sie_STIE; + _zz_162[1 : 1] = CsrPlugin_sie_SSIE; + end + end + + always @ (*) begin + _zz_163 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_163[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_164 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_164[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_165 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_165[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_165[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_166 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_166[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_167 = 32'h0; + if(execute_CsrPlugin_csr_324)begin + _zz_167[5 : 5] = CsrPlugin_sip_STIP; + _zz_167[1 : 1] = CsrPlugin_sip_SSIP; + _zz_167[9 : 9] = CsrPlugin_sip_SEIP_OR; + end + end + + always @ (*) begin + _zz_168 = 32'h0; + if(execute_CsrPlugin_csr_260)begin + _zz_168[9 : 9] = CsrPlugin_sie_SEIE; + _zz_168[5 : 5] = CsrPlugin_sie_STIE; + _zz_168[1 : 1] = CsrPlugin_sie_SSIE; + end + end + + always @ (*) begin + _zz_169 = 32'h0; + if(execute_CsrPlugin_csr_261)begin + _zz_169[31 : 2] = CsrPlugin_stvec_base; + _zz_169[1 : 0] = CsrPlugin_stvec_mode; + end + end + + always @ (*) begin + _zz_170 = 32'h0; + if(execute_CsrPlugin_csr_321)begin + _zz_170[31 : 0] = CsrPlugin_sepc; + end + end + + always @ (*) begin + _zz_171 = 32'h0; + if(execute_CsrPlugin_csr_320)begin + _zz_171[31 : 0] = CsrPlugin_sscratch; + end + end + + always @ (*) begin + _zz_172 = 32'h0; + if(execute_CsrPlugin_csr_322)begin + _zz_172[31 : 31] = CsrPlugin_scause_interrupt; + _zz_172[3 : 0] = CsrPlugin_scause_exceptionCode; + end + end + + always @ (*) begin + _zz_173 = 32'h0; + if(execute_CsrPlugin_csr_323)begin + _zz_173[31 : 0] = CsrPlugin_stval; + end + end + + always @ (*) begin + _zz_174 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_174[31 : 0] = _zz_150; + end + end + + always @ (*) begin + _zz_175 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_175[31 : 0] = _zz_151; + end + end + + always @ (*) begin + _zz_176 = 32'h0; + if(execute_CsrPlugin_csr_2496)begin + _zz_176[31 : 0] = _zz_152; + end + end + + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_3520)begin + _zz_177[31 : 0] = _zz_153; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_154 | _zz_155) | (_zz_156 | _zz_157)) | ((_zz_158 | _zz_159) | (_zz_160 | _zz_648))) | (((_zz_161 | _zz_162) | (_zz_163 | _zz_164)) | ((_zz_165 | _zz_166) | (_zz_167 | _zz_168)))) | ((((_zz_169 | _zz_170) | (_zz_171 | _zz_172)) | ((_zz_173 | _zz_174) | (_zz_175 | _zz_176))) | _zz_177)); + assign iBusWishbone_ADR = {_zz_431,_zz_178}; + assign iBusWishbone_CTI = ((_zz_178 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_281)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_281)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_179; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_185 = (dBus_cmd_payload_length != 3'b000); + assign _zz_181 = dBus_cmd_valid; + assign _zz_183 = dBus_cmd_payload_wr; + assign _zz_184 = (_zz_180 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_182 && (_zz_183 || _zz_184)); + assign dBusWishbone_ADR = ((_zz_185 ? {{dBus_cmd_payload_address[31 : 5],_zz_180},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_185 ? (_zz_184 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_183 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_183; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_182 = (_zz_181 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_181; + assign dBusWishbone_STB = _zz_181; + assign dBus_rsp_valid = _zz_186; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_66 <= 1'b0; + _zz_68 <= 1'b0; + _zz_71 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_73; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_74; + DBusCachedPlugin_rspCounter <= 32'h0; + MmuPlugin_status_sum <= 1'b0; + MmuPlugin_status_mxr <= 1'b0; + MmuPlugin_status_mprv <= 1'b0; + MmuPlugin_satp_mode <= 1'b0; + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_0_entryToReplace_value <= 2'b00; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_entryToReplace_value <= 2'b00; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; + _zz_110 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_136 <= 2'b11; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_medeleg_IAM <= 1'b0; + CsrPlugin_medeleg_IAF <= 1'b0; + CsrPlugin_medeleg_II <= 1'b0; + CsrPlugin_medeleg_LAM <= 1'b0; + CsrPlugin_medeleg_LAF <= 1'b0; + CsrPlugin_medeleg_SAM <= 1'b0; + CsrPlugin_medeleg_SAF <= 1'b0; + CsrPlugin_medeleg_EU <= 1'b0; + CsrPlugin_medeleg_ES <= 1'b0; CsrPlugin_medeleg_IPF <= 1'b0; CsrPlugin_medeleg_LPF <= 1'b0; CsrPlugin_medeleg_SPF <= 1'b0; @@ -6382,7 +5576,7 @@ module VexRiscv ( CsrPlugin_mideleg_SS <= 1'b0; CsrPlugin_sstatus_SIE <= 1'b0; CsrPlugin_sstatus_SPIE <= 1'b0; - CsrPlugin_sstatus_SPP <= (1'b1); + CsrPlugin_sstatus_SPP <= 1'b1; CsrPlugin_sip_SEIP_SOFT <= 1'b0; CsrPlugin_sip_STIP <= 1'b0; CsrPlugin_sip_SSIP <= 1'b0; @@ -6395,26 +5589,33 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_MulDivIterativePlugin_mul_counter_value <= (6'b000000); - memory_MulDivIterativePlugin_div_counter_value <= (6'b000000); - _zz_207_ <= (32'b00000000000000000000000000000000); - _zz_209_ <= (32'b00000000000000000000000000000000); + memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + _zz_150 <= 32'h0; + _zz_152 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_IS_DBUS_SHARING <= 1'b0; memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_211_ <= (3'b000); - _zz_212_ <= 1'b0; - _zz_213_ <= (3'b000); - _zz_219_ <= 1'b0; + _zz_178 <= 3'b000; + _zz_179 <= 1'b0; + _zz_180 <= 3'b000; + _zz_186 <= 1'b0; end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin @@ -6423,98 +5624,92 @@ module VexRiscv ( if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_109_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_66 <= 1'b0; + end + if(_zz_64)begin + _zz_66 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(_zz_107_)begin - _zz_109_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_68 <= 1'b0; end if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_111_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + _zz_68 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_111_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_71 <= 1'b0; end if(IBusCachedPlugin_iBusRsp_stages_2_output_ready)begin - _zz_114_ <= IBusCachedPlugin_iBusRsp_stages_2_output_valid; + _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_2_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_114_ <= 1'b0; - end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + if((! (! IBusCachedPlugin_iBusRsp_stages_3_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_117_ <= 1'b0; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_306_)begin - _zz_117_ <= dataCache_1__io_mem_cmd_valid; + if(_zz_282)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_124_ <= dataCache_1__io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end if(dBus_rsp_valid)begin - DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; if(contextSwitching)begin @@ -6546,71 +5741,69 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_valid <= 1'b0; end end - case(MmuPlugin_shared_state_1_) + MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; + case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_307_)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; - end - if(_zz_308_)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + if(_zz_283)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; end end `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; end end `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin - if(MmuPlugin_dBusAccess_rsp_valid)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; end - if(MmuPlugin_dBusAccess_rsp_payload_redo)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; end end end `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; end end default : begin - if(MmuPlugin_dBusAccess_rsp_valid)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_IDLE; - if(MmuPlugin_dBusAccess_rsp_payload_redo)begin - MmuPlugin_shared_state_1_ <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if(MmuPlugin_shared_dBusRspStaged_valid)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; end end end endcase - if(_zz_293_)begin - if(_zz_294_)begin - if(_zz_309_)begin + if(_zz_267)begin + if(_zz_268)begin + if(_zz_284)begin MmuPlugin_ports_0_cache_0_valid <= 1'b1; end - if(_zz_310_)begin + if(_zz_285)begin MmuPlugin_ports_0_cache_1_valid <= 1'b1; end - if(_zz_311_)begin + if(_zz_286)begin MmuPlugin_ports_0_cache_2_valid <= 1'b1; end - if(_zz_312_)begin + if(_zz_287)begin MmuPlugin_ports_0_cache_3_valid <= 1'b1; end end - if(_zz_295_)begin - if(_zz_313_)begin + if(_zz_269)begin + if(_zz_288)begin MmuPlugin_ports_1_cache_0_valid <= 1'b1; end - if(_zz_314_)begin + if(_zz_289)begin MmuPlugin_ports_1_cache_1_valid <= 1'b1; end - if(_zz_315_)begin + if(_zz_290)begin MmuPlugin_ports_1_cache_2_valid <= 1'b1; end - if(_zz_316_)begin + if(_zz_291)begin MmuPlugin_ports_1_cache_3_valid <= 1'b1; end end @@ -6625,8 +5818,8 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - _zz_159_ <= 1'b0; - _zz_172_ <= _zz_171_; + _zz_110 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -6648,41 +5841,60 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_317_)begin - if(_zz_318_)begin + if(_zz_292)begin + if(_zz_293)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_319_)begin + if(_zz_294)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_320_)begin + if(_zz_295)begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(_zz_321_)begin - if(_zz_322_)begin + if(_zz_296)begin + if(_zz_297)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_323_)begin + if(_zz_298)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_324_)begin + if(_zz_299)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_325_)begin + if(_zz_300)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_326_)begin + if(_zz_301)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_327_)begin + if(_zz_302)begin CsrPlugin_interrupt_valid <= 1'b1; end end CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_286_)begin - _zz_191_ <= CsrPlugin_targetPrivilege; + if(_zz_261)begin + _zz_136 <= CsrPlugin_targetPrivilege; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_sstatus_SIE <= 1'b0; @@ -6698,39 +5910,33 @@ module VexRiscv ( end endcase end - if(_zz_287_)begin - case(_zz_288_) + if(_zz_262)begin + case(_zz_263) 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; - _zz_191_ <= CsrPlugin_mstatus_MPP; + _zz_136 <= CsrPlugin_mstatus_MPP; end 2'b01 : begin - CsrPlugin_sstatus_SPP <= (1'b0); + CsrPlugin_sstatus_SPP <= 1'b0; CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; CsrPlugin_sstatus_SPIE <= 1'b1; - _zz_191_ <= {(1'b0),CsrPlugin_sstatus_SPP}; + _zz_136 <= {1'b0,CsrPlugin_sstatus_SPP}; end default : begin end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_197_,{_zz_196_,{_zz_195_,{_zz_194_,{_zz_193_,_zz_192_}}}}} != (6'b000000)); + execute_CsrPlugin_wfiWake <= (({_zz_142,{_zz_141,{_zz_140,{_zz_139,{_zz_138,_zz_137}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_37_; - end if((! memory_arbitration_isStuck))begin execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -6752,700 +5958,1989 @@ module VexRiscv ( if(MmuPlugin_dBusAccess_rsp_valid)begin memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_207_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_410_[0]; - MmuPlugin_status_sum <= _zz_411_[0]; - MmuPlugin_status_mprv <= _zz_412_[0]; - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_413_[0]; - CsrPlugin_mstatus_MIE <= _zz_414_[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_415_[0]; - CsrPlugin_sstatus_SIE <= _zz_416_[0]; - end - end - 12'b001100000011 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mideleg_SE <= _zz_417_[0]; - CsrPlugin_mideleg_ST <= _zz_418_[0]; - CsrPlugin_mideleg_SS <= _zz_419_[0]; - end - end - 12'b111100010001 : begin - end - 12'b000101000010 : begin - end - 12'b111100010100 : begin - end - 12'b100111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_209_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b000100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_421_[0]; - MmuPlugin_status_sum <= _zz_422_[0]; - MmuPlugin_status_mprv <= _zz_423_[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_424_[0]; - CsrPlugin_sstatus_SIE <= _zz_425_[0]; - end - end - 12'b001100000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_medeleg_EU <= _zz_426_[0]; - CsrPlugin_medeleg_II <= _zz_427_[0]; - CsrPlugin_medeleg_LAF <= _zz_428_[0]; - CsrPlugin_medeleg_LPF <= _zz_429_[0]; - CsrPlugin_medeleg_LAM <= _zz_430_[0]; - CsrPlugin_medeleg_SAF <= _zz_431_[0]; - CsrPlugin_medeleg_IAF <= _zz_432_[0]; - CsrPlugin_medeleg_ES <= _zz_433_[0]; - CsrPlugin_medeleg_IPF <= _zz_434_[0]; - CsrPlugin_medeleg_SPF <= _zz_435_[0]; - CsrPlugin_medeleg_SAM <= _zz_436_[0]; - CsrPlugin_medeleg_IAM <= _zz_437_[0]; - end - end - 12'b001101000001 : begin - end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_439_[0]; - CsrPlugin_sip_SSIP <= _zz_440_[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_441_[0]; - end - end - 12'b001100000101 : begin - end - 12'b000110000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_mode <= _zz_442_[0]; - end - end - 12'b110011000000 : begin - end - 12'b000101000001 : begin - end - 12'b111100010011 : begin - end - 12'b000101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_443_[0]; - CsrPlugin_sip_SSIP <= _zz_444_[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_445_[0]; - end - end - 12'b001101000011 : begin - end - 12'b000100000101 : begin - end - 12'b111111000000 : begin + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_status_mxr <= _zz_386[0]; + MmuPlugin_status_sum <= _zz_387[0]; + MmuPlugin_status_mprv <= _zz_388[0]; + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_389[0]; + CsrPlugin_mstatus_MIE <= _zz_390[0]; + CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; + CsrPlugin_sstatus_SPIE <= _zz_391[0]; + CsrPlugin_sstatus_SIE <= _zz_392[0]; + end + end + if(execute_CsrPlugin_csr_256)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_status_mxr <= _zz_393[0]; + MmuPlugin_status_sum <= _zz_394[0]; + MmuPlugin_status_mprv <= _zz_395[0]; + CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; + CsrPlugin_sstatus_SPIE <= _zz_396[0]; + CsrPlugin_sstatus_SIE <= _zz_397[0]; end - 12'b001101000000 : begin + end + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeInstruction)begin + MmuPlugin_ports_0_cache_0_valid <= 1'b0; + MmuPlugin_ports_0_cache_1_valid <= 1'b0; + MmuPlugin_ports_0_cache_2_valid <= 1'b0; + MmuPlugin_ports_0_cache_3_valid <= 1'b0; + MmuPlugin_ports_1_cache_0_valid <= 1'b0; + MmuPlugin_ports_1_cache_1_valid <= 1'b0; + MmuPlugin_ports_1_cache_2_valid <= 1'b0; + MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_446_[0]; - CsrPlugin_mie_MTIE <= _zz_447_[0]; - CsrPlugin_mie_MSIE <= _zz_448_[0]; - CsrPlugin_sie_SEIE <= _zz_449_[0]; - CsrPlugin_sie_STIE <= _zz_450_[0]; - CsrPlugin_sie_SSIE <= _zz_451_[0]; - end + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_mode <= _zz_398[0]; end - 12'b111100010010 : begin + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sip_STIP <= _zz_400[0]; + CsrPlugin_sip_SSIP <= _zz_401[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_402[0]; end - 12'b000101000011 : begin + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_403[0]; + CsrPlugin_mie_MTIE <= _zz_404[0]; + CsrPlugin_mie_MSIE <= _zz_405[0]; + CsrPlugin_sie_SEIE <= _zz_406[0]; + CsrPlugin_sie_STIE <= _zz_407[0]; + CsrPlugin_sie_SSIE <= _zz_408[0]; end - 12'b110111000000 : begin + end + if(execute_CsrPlugin_csr_770)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_medeleg_IAM <= _zz_409[0]; + CsrPlugin_medeleg_IAF <= _zz_410[0]; + CsrPlugin_medeleg_II <= _zz_411[0]; + CsrPlugin_medeleg_LAM <= _zz_412[0]; + CsrPlugin_medeleg_LAF <= _zz_413[0]; + CsrPlugin_medeleg_SAM <= _zz_414[0]; + CsrPlugin_medeleg_SAF <= _zz_415[0]; + CsrPlugin_medeleg_EU <= _zz_416[0]; + CsrPlugin_medeleg_ES <= _zz_417[0]; + CsrPlugin_medeleg_IPF <= _zz_418[0]; + CsrPlugin_medeleg_LPF <= _zz_419[0]; + CsrPlugin_medeleg_SPF <= _zz_420[0]; + end + end + if(execute_CsrPlugin_csr_771)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mideleg_SE <= _zz_421[0]; + CsrPlugin_mideleg_ST <= _zz_422[0]; + CsrPlugin_mideleg_SS <= _zz_423[0]; end - 12'b000101000000 : begin + end + if(execute_CsrPlugin_csr_324)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sip_STIP <= _zz_424[0]; + CsrPlugin_sip_SSIP <= _zz_425[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_426[0]; end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_260)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sie_SEIE <= _zz_427[0]; + CsrPlugin_sie_STIE <= _zz_428[0]; + CsrPlugin_sie_SSIE <= _zz_429[0]; end - 12'b000100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sie_SEIE <= _zz_452_[0]; - CsrPlugin_sie_STIE <= _zz_453_[0]; - CsrPlugin_sie_SSIE <= _zz_454_[0]; - end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_150 <= execute_CsrPlugin_writeData[31 : 0]; end - default : begin + end + if(execute_CsrPlugin_csr_2496)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; end - endcase - if(_zz_305_)begin + end + if(_zz_281)begin if(iBusWishbone_ACK)begin - _zz_211_ <= (_zz_211_ + (3'b001)); + _zz_178 <= (_zz_178 + 3'b001); end end - _zz_212_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_214_ && _zz_215_))begin - _zz_213_ <= (_zz_213_ + (3'b001)); - if(_zz_217_)begin - _zz_213_ <= (3'b000); + _zz_179 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_181 && _zz_182))begin + _zz_180 <= (_zz_180 + 3'b001); + if(_zz_184)begin + _zz_180 <= 3'b000; end end - _zz_219_ <= ((_zz_214_ && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_186 <= ((_zz_181 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_112_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_69 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_2_output_ready)begin + _zz_72 <= IBusCachedPlugin_iBusRsp_stages_2_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_3_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_282)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; + MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; + MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; + if((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)))begin + MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; + MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G; + MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A; + MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D; + MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW; + MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; + end + case(MmuPlugin_shared_state_1) + `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + if(_zz_283)begin + MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; + MmuPlugin_shared_vpn_1 <= _zz_93[31 : 22]; + MmuPlugin_shared_vpn_0 <= _zz_93[21 : 12]; + end + end + `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + end + `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + end + `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + end + default : begin + end + endcase + if(_zz_267)begin + if(_zz_268)begin + if(_zz_284)begin + MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_285)begin + MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_286)begin + MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_287)begin + MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_0_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_0_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + if(_zz_269)begin + if(_zz_288)begin + MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_289)begin + MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_290)begin + MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + if(_zz_291)begin + MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; + MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; + MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; + MmuPlugin_ports_1_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; + MmuPlugin_ports_1_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; + MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; + MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; + MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; + MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + end + end + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_sip_SEIP_INPUT <= externalInterruptS; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_258)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_144 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_144 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_292)begin + if(_zz_293)begin + CsrPlugin_interrupt_code <= 4'b0101; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + if(_zz_294)begin + CsrPlugin_interrupt_code <= 4'b0001; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + if(_zz_295)begin + CsrPlugin_interrupt_code <= 4'b1001; + CsrPlugin_interrupt_targetPrivilege <= 2'b01; + end + end + if(_zz_296)begin + if(_zz_297)begin + CsrPlugin_interrupt_code <= 4'b0101; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_298)begin + CsrPlugin_interrupt_code <= 4'b0001; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_299)begin + CsrPlugin_interrupt_code <= 4'b1001; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_300)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_301)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_302)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_261)begin + case(CsrPlugin_targetPrivilege) + 2'b01 : begin + CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_sepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(_zz_252)begin + if(_zz_260)begin + memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_365,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + end + end + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(_zz_253)begin + if(_zz_279)begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_result <= _zz_377[31:0]; + end + end + end + if(_zz_280)begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_148 ? (~ _zz_149) : _zz_149) + _zz_383); + memory_MulDivIterativePlugin_rs2 <= ((_zz_147 ? (~ execute_RS2) : execute_RS2) + _zz_385); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_148 ^ (_zz_147 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_36; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_53; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_54; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_26; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_23; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_20; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_17; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_14; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_9; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_32; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_33; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_770 <= (decode_INSTRUCTION[31 : 20] == 12'h302); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_771 <= (decode_INSTRUCTION[31 : 20] == 12'h303); end - if(IBusCachedPlugin_iBusRsp_stages_2_output_ready)begin - _zz_115_ <= IBusCachedPlugin_iBusRsp_stages_2_output_payload; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_324 <= (decode_INSTRUCTION[31 : 20] == 12'h144); end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin - IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_260 <= (decode_INSTRUCTION[31 : 20] == 12'h104); end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin - IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_261 <= (decode_INSTRUCTION[31 : 20] == 12'h105); end - if(_zz_306_)begin - _zz_118_ <= dataCache_1__io_mem_cmd_payload_wr; - _zz_119_ <= dataCache_1__io_mem_cmd_payload_address; - _zz_120_ <= dataCache_1__io_mem_cmd_payload_data; - _zz_121_ <= dataCache_1__io_mem_cmd_payload_mask; - _zz_122_ <= dataCache_1__io_mem_cmd_payload_length; - _zz_123_ <= dataCache_1__io_mem_cmd_payload_last; - end - if(dataCache_1__io_mem_cmd_s2mPipe_ready)begin - _zz_125_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_wr; - _zz_126_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_address; - _zz_127_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_data; - _zz_128_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_mask; - _zz_129_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_length; - _zz_130_ <= dataCache_1__io_mem_cmd_s2mPipe_payload_last; - end - if((MmuPlugin_dBusAccess_rsp_valid && (! MmuPlugin_dBusAccess_rsp_payload_redo)))begin - MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; - MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_shared_pteBuffer_X <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_shared_pteBuffer_U <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_shared_pteBuffer_G <= MmuPlugin_shared_dBusRsp_pte_G; - MmuPlugin_shared_pteBuffer_A <= MmuPlugin_shared_dBusRsp_pte_A; - MmuPlugin_shared_pteBuffer_D <= MmuPlugin_shared_dBusRsp_pte_D; - MmuPlugin_shared_pteBuffer_RSW <= MmuPlugin_shared_dBusRsp_pte_RSW; - MmuPlugin_shared_pteBuffer_PPN0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_321 <= (decode_INSTRUCTION[31 : 20] == 12'h141); end - case(MmuPlugin_shared_state_1_) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_307_)begin - MmuPlugin_shared_vpn_1 <= IBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22]; - MmuPlugin_shared_vpn_0 <= IBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]; - MmuPlugin_shared_portId <= (1'b0); - end - if(_zz_308_)begin - MmuPlugin_shared_vpn_1 <= DBusCachedPlugin_mmuBus_cmd_virtualAddress[31 : 22]; - MmuPlugin_shared_vpn_0 <= DBusCachedPlugin_mmuBus_cmd_virtualAddress[21 : 12]; - MmuPlugin_shared_portId <= (1'b1); - end - end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin - end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin - end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin - end - default : begin - end - endcase - if(_zz_293_)begin - if(_zz_294_)begin - if(_zz_309_)begin - MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_0_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_0_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_310_)begin - MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_0_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_0_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_311_)begin - MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_0_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_0_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_312_)begin - MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_0_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_0_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - end - if(_zz_295_)begin - if(_zz_313_)begin - MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_1_cache_0_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_1_cache_0_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_314_)begin - MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_1_cache_1_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_1_cache_1_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_315_)begin - MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_1_cache_2_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_1_cache_2_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - if(_zz_316_)begin - MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != (10'b0000000000)))); - MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; - MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; - MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; - MmuPlugin_ports_1_cache_3_physicalAddress_1 <= MmuPlugin_shared_dBusRsp_pte_PPN1[9 : 0]; - MmuPlugin_ports_1_cache_3_allowRead <= MmuPlugin_shared_dBusRsp_pte_R; - MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; - MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; - MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1_ == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); - end - end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_320 <= (decode_INSTRUCTION[31 : 20] == 12'h140); end - if(_zz_171_)begin - _zz_173_ <= _zz_53_[11 : 7]; - _zz_174_ <= _zz_87_; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_322 <= (decode_INSTRUCTION[31 : 20] == 12'h142); end - CsrPlugin_mip_MEIP <= externalInterrupt; - CsrPlugin_mip_MTIP <= timerInterrupt; - CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_sip_SEIP_INPUT <= externalInterruptS; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); - if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_323 <= (decode_INSTRUCTION[31 : 20] == 12'h143); end - if(_zz_282_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_199_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_199_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(BranchPlugin_branchExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2496 <= (decode_INSTRUCTION[31 : 20] == 12'h9c0); end - if(DBusCachedPlugin_exceptionBus_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3520 <= (decode_INSTRUCTION[31 : 20] == 12'hdc0); end - if(_zz_317_)begin - if(_zz_318_)begin - CsrPlugin_interrupt_code <= (4'b0101); - CsrPlugin_interrupt_targetPrivilege <= (2'b01); + if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_writeEnable)begin + MmuPlugin_satp_asid <= execute_CsrPlugin_writeData[30 : 22]; + MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; end - if(_zz_319_)begin - CsrPlugin_interrupt_code <= (4'b0001); - CsrPlugin_interrupt_targetPrivilege <= (2'b01); - end - if(_zz_320_)begin - CsrPlugin_interrupt_code <= (4'b1001); - CsrPlugin_interrupt_targetPrivilege <= (2'b01); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_399[0]; end end - if(_zz_321_)begin - if(_zz_322_)begin - CsrPlugin_interrupt_code <= (4'b0101); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - if(_zz_323_)begin - CsrPlugin_interrupt_code <= (4'b0001); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end - if(_zz_324_)begin - CsrPlugin_interrupt_code <= (4'b1001); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; end - if(_zz_325_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_261)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - if(_zz_326_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_321)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0]; end - if(_zz_327_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + end + if(execute_CsrPlugin_csr_320)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_286_)begin - case(CsrPlugin_targetPrivilege) - 2'b01 : begin - CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_sepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - 2'b11 : begin - CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); - CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin - CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - end - end - default : begin - end - endcase + if(execute_CsrPlugin_csr_322)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_scause_interrupt <= _zz_430[0]; + CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end end - if(_zz_276_)begin - if(_zz_284_)begin - memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_389_,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + if(execute_CsrPlugin_csr_323)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0]; end end - if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin - memory_MulDivIterativePlugin_div_done <= 1'b1; + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_isLrsc, + input io_cpu_execute_args_isAmo, + input io_cpu_execute_args_amoCtrl_swap, + input [2:0] io_cpu_execute_args_amoCtrl_alu, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_memory_mmuRsp_ways_0_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_0_physical, + input io_cpu_memory_mmuRsp_ways_1_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_1_physical, + input io_cpu_memory_mmuRsp_ways_2_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_2_physical, + input io_cpu_memory_mmuRsp_ways_3_sel, + input [31:0] io_cpu_memory_mmuRsp_ways_3_physical, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire _zz_19; + wire _zz_20; + wire _zz_21; + wire _zz_22; + wire [2:0] _zz_23; + wire [0:0] _zz_24; + wire [0:0] _zz_25; + wire [9:0] _zz_26; + wire [9:0] _zz_27; + wire [31:0] _zz_28; + wire [31:0] _zz_29; + wire [31:0] _zz_30; + wire [31:0] _zz_31; + wire [1:0] _zz_32; + wire [31:0] _zz_33; + wire [1:0] _zz_34; + wire [1:0] _zz_35; + wire [0:0] _zz_36; + wire [0:0] _zz_37; + wire [0:0] _zz_38; + wire [2:0] _zz_39; + wire [1:0] _zz_40; + wire [21:0] _zz_41; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_isLrsc; + reg stageA_request_isAmo; + reg stageA_request_amoCtrl_swap; + reg [2:0] stageA_request_amoCtrl_alu; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_isLrsc; + reg stageB_request_isAmo; + reg stageB_request_amoCtrl_swap; + reg [2:0] stageB_request_amoCtrl_alu; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_mmuRsp_ways_0_sel; + reg [31:0] stageB_mmuRsp_ways_0_physical; + reg stageB_mmuRsp_ways_1_sel; + reg [31:0] stageB_mmuRsp_ways_1_physical; + reg stageB_mmuRsp_ways_2_sel; + reg [31:0] stageB_mmuRsp_ways_2_physical; + reg stageB_mmuRsp_ways_3_sel; + reg [31:0] stageB_mmuRsp_ways_3_physical; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + reg stageB_lrSc_reserved; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + reg [31:0] stageB_requestDataBypass; + wire stageB_amo_compare; + wire stageB_amo_unsigned; + wire [31:0] stageB_amo_addSub; + wire stageB_amo_less; + wire stageB_amo_selectRf; + reg [31:0] stageB_amo_result; + reg [31:0] stageB_amo_resultReg; + reg stageB_amo_internal_resultRegValid; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_42; + reg [7:0] _zz_43; + reg [7:0] _zz_44; + reg [7:0] _zz_45; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_15 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); + assign _zz_16 = (! stageB_amo_internal_resultRegValid); + assign _zz_17 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign _zz_18 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_19 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign _zz_20 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign _zz_21 = (! stageB_flusher_hold); + assign _zz_22 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_23 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); + assign _zz_24 = _zz_4[0 : 0]; + assign _zz_25 = _zz_4[1 : 1]; + assign _zz_26 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_27 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_28 = ($signed(_zz_29) + $signed(_zz_33)); + assign _zz_29 = ($signed(_zz_30) + $signed(_zz_31)); + assign _zz_30 = stageB_request_data; + assign _zz_31 = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux); + assign _zz_32 = (stageB_amo_compare ? _zz_34 : _zz_35); + assign _zz_33 = {{30{_zz_32[1]}}, _zz_32}; + assign _zz_34 = 2'b01; + assign _zz_35 = 2'b00; + assign _zz_36 = 1'b1; + assign _zz_37 = (! stageB_lrSc_reserved); + assign _zz_38 = loader_counter_willIncrement; + assign _zz_39 = {2'd0, _zz_38}; + assign _zz_40 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_41 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; end - if((! memory_arbitration_isStuck))begin - memory_MulDivIterativePlugin_div_done <= 1'b0; + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_41; end - if(_zz_277_)begin - if(_zz_285_)begin - memory_MulDivIterativePlugin_rs1[31 : 0] <= _zz_398_[31:0]; - memory_MulDivIterativePlugin_accumulator[31 : 0] <= ((! _zz_202_[32]) ? _zz_399_ : _zz_400_); - if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin - memory_MulDivIterativePlugin_div_result <= _zz_401_[31:0]; - end - end + end + + always @ (*) begin + _zz_11 = {_zz_45, _zz_44, _zz_43, _zz_42}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_42 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_43 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_44 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_45 <= ways_0_data_symbol3[dataReadCmd_payload]; end - if(_zz_304_)begin - memory_MulDivIterativePlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_MulDivIterativePlugin_rs1 <= ((_zz_205_ ? (~ _zz_206_) : _zz_206_) + _zz_407_); - memory_MulDivIterativePlugin_rs2 <= ((_zz_204_ ? (~ execute_RS2) : execute_RS2) + _zz_409_); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_205_ ^ (_zz_204_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_26_; + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_24[0]; + assign ways_0_tagsReadRsp_error = _zz_25[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_23_; + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_20_; + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_36_; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + if(stageB_request_isAmo)begin + if(_zz_16)begin + dataWriteCmd_valid = 1'b0; + end + end + if(_zz_17)begin + dataWriteCmd_valid = 1'b0; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_18_; + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + if(_zz_18)begin + dataWriteCmd_valid = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + if(_zz_18)begin + dataWriteCmd_payload_way = loader_waysAllocator; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; + if(_zz_18)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + if(_zz_18)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_36[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_94_; + if(_zz_18)begin + dataWriteCmd_payload_mask = 4'b1111; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_26)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_27)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_93_; + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(! _zz_15) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + if(_zz_13)begin + stageB_loaderValid = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_14)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(_zz_19)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_15)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(stageB_request_isAmo)begin + if(_zz_16)begin + io_cpu_writeBack_haltIt = 1'b1; + end + end + if(_zz_17)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_15_; + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + always @ (*) begin + stageB_requestDataBypass = stageB_request_data; + if(stageB_request_isAmo)begin + stageB_requestDataBypass = stageB_amo_resultReg; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + + assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; + assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == 2'b11); + assign stageB_amo_addSub = _zz_28; + assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31])); + assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); + always @ (*) begin + case(_zz_23) + 3'b000 : begin + stageB_amo_result = stageB_amo_addSub; + end + 3'b001 : begin + stageB_amo_result = (stageB_request_data ^ stageB_dataMux); + end + 3'b010 : begin + stageB_amo_result = (stageB_request_data | stageB_dataMux); + end + 3'b011 : begin + stageB_amo_result = (stageB_request_data & stageB_dataMux); + end + default : begin + stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux); + end + endcase + end + + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_request_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + if(_zz_20)begin + io_cpu_redo = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_12_; + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_14)begin + io_mem_cmd_valid = (! memCmdSent); + if(_zz_19)begin + io_mem_cmd_valid = 1'b0; + end + end else begin + if(_zz_15)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + if(stageB_request_isAmo)begin + if(_zz_16)begin + io_mem_cmd_valid = 1'b0; + end + end + if(_zz_20)begin + io_mem_cmd_valid = 1'b0; + end + if(_zz_17)begin + io_mem_cmd_valid = 1'b0; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_MUL <= decode_IS_MUL; + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9_; + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(_zz_15)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6_; + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_14) begin + if(! _zz_15) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4_; + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_2_; + if((stageB_request_isLrsc && stageB_request_wr))begin + io_cpu_writeBack_data = {31'd0, _zz_37}; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_18)begin + loader_counter_willIncrement = 1'b1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_44_; + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_39); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; + stageA_request_isAmo <= io_cpu_execute_args_isAmo; + stageA_request_amoCtrl_swap <= io_cpu_execute_args_amoCtrl_swap; + stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_isLrsc <= stageA_request_isLrsc; + stageB_request_isAmo <= stageA_request_isAmo; + stageB_request_amoCtrl_swap <= stageA_request_amoCtrl_swap; + stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + stageB_mmuRsp_ways_0_sel <= io_cpu_memory_mmuRsp_ways_0_sel; + stageB_mmuRsp_ways_0_physical <= io_cpu_memory_mmuRsp_ways_0_physical; + stageB_mmuRsp_ways_1_sel <= io_cpu_memory_mmuRsp_ways_1_sel; + stageB_mmuRsp_ways_1_physical <= io_cpu_memory_mmuRsp_ways_1_physical; + stageB_mmuRsp_ways_2_sel <= io_cpu_memory_mmuRsp_ways_2_sel; + stageB_mmuRsp_ways_2_physical <= io_cpu_memory_mmuRsp_ways_2_physical; + stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; + stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b001100000011 : begin - end - 12'b111100010001 : begin - end - 12'b000101000010 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_scause_interrupt <= _zz_420_[0]; - CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(stageB_flusher_valid)begin + if(_zz_21)begin + if(_zz_22)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); end end - 12'b111100010100 : begin - end - 12'b100111000000 : begin - end - 12'b000100000000 : begin - end - 12'b001100000010 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + stageB_amo_internal_resultRegValid <= io_cpu_writeBack_isStuck; + stageB_amo_resultReg <= stageB_amo_result; + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + stageB_lrSc_reserved <= 1'b0; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_438_[0]; - end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(stageB_flusher_valid)begin + if(_zz_21)begin + if(! _zz_22) begin + stageB_flusher_valid <= 1'b0; + end end end - 12'b000110000000 : begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; - end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; end - 12'b110011000000 : begin + if(((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc))begin + stageB_lrSc_reserved <= (! stageB_request_wr); end - 12'b000101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0]; - end + if(_zz_13)begin + stageB_lrSc_reserved <= stageB_lrSc_reserved; end - 12'b111100010011 : begin + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; end - 12'b000101000100 : begin + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; end - 12'b001101000011 : begin + if(_zz_18)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); end - 12'b000100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; end - 12'b111111000000 : begin + if((! loader_valid))begin + loader_waysAllocator <= _zz_40[0:0]; end - 12'b001101000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; - end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + input io_cpu_fetch_mmuRsp_ways_0_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_0_physical, + input io_cpu_fetch_mmuRsp_ways_1_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_1_physical, + input io_cpu_fetch_mmuRsp_ways_2_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_2_physical, + input io_cpu_fetch_mmuRsp_ways_3_sel, + input [31:0] io_cpu_fetch_mmuRsp_ways_3_physical, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_9; + reg [21:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [21:0] _zz_15; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [9:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [6:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_mmuRsp_ways_0_sel; + reg [31:0] decodeStage_mmuRsp_ways_0_physical; + reg decodeStage_mmuRsp_ways_1_sel; + reg [31:0] decodeStage_mmuRsp_ways_1_physical; + reg decodeStage_mmuRsp_ways_2_sel; + reg [31:0] decodeStage_mmuRsp_ways_2_physical; + reg decodeStage_mmuRsp_ways_3_sel; + reg [31:0] decodeStage_mmuRsp_ways_3_physical; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + + assign _zz_11 = (! lineLoader_flushCounter[7]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; end - 12'b001100000100 : begin + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; end - 12'b111100010010 : begin + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; end - 12'b000101000011 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0]; - end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end - 12'b110111000000 : begin + if(io_flush)begin + lineLoader_flushPending <= 1'b1; end - 12'b000101000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0]; - end + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; end - 12'b001101000010 : begin + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; end - 12'b000100000100 : begin + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; end - default : begin + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end end - endcase - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end end -endmodule + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3 <= lineLoader_flushCounter[7]; + if(_zz_12)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + decodeStage_mmuRsp_ways_0_sel <= io_cpu_fetch_mmuRsp_ways_0_sel; + decodeStage_mmuRsp_ways_0_physical <= io_cpu_fetch_mmuRsp_ways_0_physical; + decodeStage_mmuRsp_ways_1_sel <= io_cpu_fetch_mmuRsp_ways_1_sel; + decodeStage_mmuRsp_ways_1_physical <= io_cpu_fetch_mmuRsp_ways_1_physical; + decodeStage_mmuRsp_ways_2_sel <= io_cpu_fetch_mmuRsp_ways_2_sel; + decodeStage_mmuRsp_ways_2_physical <= io_cpu_fetch_mmuRsp_ways_2_physical; + decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; + decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.yaml new file mode 100644 index 0000000..cf27a68 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.yaml @@ -0,0 +1,4 @@ +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 4096} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v index 74b2d35..60138a0 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v @@ -1,2007 +1,1723 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:06:37 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - `define EnvCtrlEnum_defaultEncoding_type [1:0] `define EnvCtrlEnum_defaultEncoding_NONE 2'b00 `define EnvCtrlEnum_defaultEncoding_XRET 2'b01 `define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - `define BranchCtrlEnum_defaultEncoding_type [1:0] `define BranchCtrlEnum_defaultEncoding_INC 2'b00 `define BranchCtrlEnum_defaultEncoding_B 2'b01 `define BranchCtrlEnum_defaultEncoding_JAL 2'b10 `define BranchCtrlEnum_defaultEncoding_JALR 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - `define ShiftCtrlEnum_defaultEncoding_type [1:0] `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 `define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input clk, - input reset); - reg [22:0] _zz_10_; - reg [31:0] _zz_11_; - wire _zz_12_; - wire _zz_13_; - wire [0:0] _zz_14_; - wire [0:0] _zz_15_; - wire [22:0] _zz_16_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [6:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [5:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [20:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [8:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [5:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_7_; - wire [8:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - reg [31:0] io_cpu_fetch_data_regNextWhen; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_hit_valid; - reg decodeStage_hit_error; - (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:511]; - assign _zz_12_ = (! lineLoader_flushCounter[6]); - assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_14_ = _zz_7_[0 : 0]; - assign _zz_15_ = _zz_7_[1 : 1]; - assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; - end - end - - always @ (posedge clk) begin - if(_zz_6_) begin - _zz_10_ <= ways_0_tags[_zz_5_]; - end - end - - always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_9_) begin - _zz_11_ <= ways_0_datas[_zz_8_]; - end - end - - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; - end - end - - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; - end - end - - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; - end - end - end - - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_12_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; - end - end +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; - end - end +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[10 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_10_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[10 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_11_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; - end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; - end - if(_zz_13_)begin - lineLoader_flushPending <= 1'b0; - end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; - end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; - end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end - end - end - end +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_12_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001)); - end - _zz_3_ <= lineLoader_flushCounter[6]; - if(_zz_13_)begin - lineLoader_flushCounter <= (7'b0000000); - end - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_error <= fetchStage_hit_error; - end - end +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -endmodule module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output reg [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset); - wire _zz_205_; - wire _zz_206_; - wire _zz_207_; - wire _zz_208_; - wire [31:0] _zz_209_; - wire _zz_210_; - wire _zz_211_; - wire _zz_212_; - reg _zz_213_; - reg [31:0] _zz_214_; - reg [31:0] _zz_215_; - reg [31:0] _zz_216_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_217_; - wire _zz_218_; - wire _zz_219_; - wire _zz_220_; - wire _zz_221_; - wire _zz_222_; - wire _zz_223_; - wire _zz_224_; - wire _zz_225_; - wire _zz_226_; - wire _zz_227_; - wire _zz_228_; - wire _zz_229_; - wire _zz_230_; - wire _zz_231_; - wire _zz_232_; - wire _zz_233_; - wire _zz_234_; - wire _zz_235_; - wire [1:0] _zz_236_; - wire _zz_237_; - wire _zz_238_; - wire _zz_239_; - wire _zz_240_; - wire _zz_241_; - wire _zz_242_; - wire _zz_243_; - wire _zz_244_; - wire _zz_245_; - wire _zz_246_; - wire _zz_247_; - wire _zz_248_; - wire _zz_249_; - wire _zz_250_; - wire _zz_251_; - wire _zz_252_; - wire _zz_253_; - wire [1:0] _zz_254_; - wire _zz_255_; - wire [4:0] _zz_256_; - wire [2:0] _zz_257_; - wire [31:0] _zz_258_; - wire [11:0] _zz_259_; - wire [31:0] _zz_260_; - wire [19:0] _zz_261_; - wire [11:0] _zz_262_; - wire [31:0] _zz_263_; - wire [31:0] _zz_264_; - wire [19:0] _zz_265_; - wire [11:0] _zz_266_; - wire [2:0] _zz_267_; - wire [0:0] _zz_268_; - wire [0:0] _zz_269_; - wire [0:0] _zz_270_; - wire [0:0] _zz_271_; - wire [0:0] _zz_272_; - wire [0:0] _zz_273_; - wire [0:0] _zz_274_; - wire [0:0] _zz_275_; - wire [0:0] _zz_276_; - wire [0:0] _zz_277_; - wire [0:0] _zz_278_; - wire [0:0] _zz_279_; - wire [0:0] _zz_280_; - wire [0:0] _zz_281_; - wire [0:0] _zz_282_; - wire [0:0] _zz_283_; - wire [0:0] _zz_284_; - wire [2:0] _zz_285_; - wire [4:0] _zz_286_; - wire [11:0] _zz_287_; - wire [11:0] _zz_288_; - wire [31:0] _zz_289_; - wire [31:0] _zz_290_; - wire [31:0] _zz_291_; - wire [31:0] _zz_292_; - wire [31:0] _zz_293_; - wire [31:0] _zz_294_; - wire [31:0] _zz_295_; - wire [31:0] _zz_296_; - wire [32:0] _zz_297_; - wire [11:0] _zz_298_; - wire [19:0] _zz_299_; - wire [11:0] _zz_300_; - wire [31:0] _zz_301_; - wire [31:0] _zz_302_; - wire [31:0] _zz_303_; - wire [11:0] _zz_304_; - wire [19:0] _zz_305_; - wire [11:0] _zz_306_; - wire [2:0] _zz_307_; - wire [1:0] _zz_308_; - wire [1:0] _zz_309_; - wire [1:0] _zz_310_; - wire [1:0] _zz_311_; - wire [0:0] _zz_312_; - wire [5:0] _zz_313_; - wire [33:0] _zz_314_; - wire [32:0] _zz_315_; - wire [33:0] _zz_316_; - wire [32:0] _zz_317_; - wire [33:0] _zz_318_; - wire [32:0] _zz_319_; - wire [0:0] _zz_320_; - wire [5:0] _zz_321_; - wire [32:0] _zz_322_; - wire [32:0] _zz_323_; - wire [31:0] _zz_324_; - wire [31:0] _zz_325_; - wire [32:0] _zz_326_; - wire [32:0] _zz_327_; - wire [32:0] _zz_328_; - wire [0:0] _zz_329_; - wire [32:0] _zz_330_; - wire [0:0] _zz_331_; - wire [32:0] _zz_332_; - wire [0:0] _zz_333_; - wire [31:0] _zz_334_; - wire [0:0] _zz_335_; - wire [0:0] _zz_336_; - wire [0:0] _zz_337_; - wire [0:0] _zz_338_; - wire [0:0] _zz_339_; - wire [0:0] _zz_340_; - wire [26:0] _zz_341_; - wire [6:0] _zz_342_; - wire _zz_343_; - wire _zz_344_; - wire [2:0] _zz_345_; - wire _zz_346_; - wire _zz_347_; - wire _zz_348_; - wire [31:0] _zz_349_; - wire _zz_350_; - wire _zz_351_; - wire _zz_352_; - wire [0:0] _zz_353_; - wire [0:0] _zz_354_; - wire _zz_355_; - wire [0:0] _zz_356_; - wire [24:0] _zz_357_; - wire [31:0] _zz_358_; - wire [31:0] _zz_359_; - wire _zz_360_; - wire [2:0] _zz_361_; - wire [2:0] _zz_362_; - wire _zz_363_; - wire [0:0] _zz_364_; - wire [20:0] _zz_365_; - wire [31:0] _zz_366_; - wire [31:0] _zz_367_; - wire _zz_368_; - wire _zz_369_; - wire [31:0] _zz_370_; - wire [31:0] _zz_371_; - wire [0:0] _zz_372_; - wire [0:0] _zz_373_; - wire [0:0] _zz_374_; - wire [0:0] _zz_375_; - wire _zz_376_; - wire [0:0] _zz_377_; - wire [17:0] _zz_378_; - wire [31:0] _zz_379_; - wire [31:0] _zz_380_; - wire [0:0] _zz_381_; - wire [0:0] _zz_382_; - wire _zz_383_; - wire [3:0] _zz_384_; - wire [3:0] _zz_385_; - wire _zz_386_; - wire [0:0] _zz_387_; - wire [14:0] _zz_388_; - wire [31:0] _zz_389_; - wire [31:0] _zz_390_; - wire [31:0] _zz_391_; - wire [31:0] _zz_392_; - wire _zz_393_; - wire [0:0] _zz_394_; - wire [0:0] _zz_395_; - wire _zz_396_; - wire _zz_397_; - wire [0:0] _zz_398_; - wire [0:0] _zz_399_; - wire [1:0] _zz_400_; - wire [1:0] _zz_401_; - wire _zz_402_; - wire [0:0] _zz_403_; - wire [11:0] _zz_404_; - wire [31:0] _zz_405_; - wire [31:0] _zz_406_; - wire [31:0] _zz_407_; - wire [31:0] _zz_408_; - wire [31:0] _zz_409_; - wire [31:0] _zz_410_; - wire [31:0] _zz_411_; - wire [31:0] _zz_412_; - wire [31:0] _zz_413_; - wire _zz_414_; - wire _zz_415_; - wire [1:0] _zz_416_; - wire [1:0] _zz_417_; - wire _zz_418_; - wire [0:0] _zz_419_; - wire [9:0] _zz_420_; - wire [31:0] _zz_421_; - wire [31:0] _zz_422_; - wire [31:0] _zz_423_; - wire [31:0] _zz_424_; - wire _zz_425_; - wire [0:0] _zz_426_; - wire [0:0] _zz_427_; - wire _zz_428_; - wire [2:0] _zz_429_; - wire [2:0] _zz_430_; - wire _zz_431_; - wire [0:0] _zz_432_; - wire [6:0] _zz_433_; - wire [31:0] _zz_434_; - wire [31:0] _zz_435_; - wire [31:0] _zz_436_; - wire [31:0] _zz_437_; - wire _zz_438_; - wire _zz_439_; - wire [31:0] _zz_440_; - wire [31:0] _zz_441_; - wire [0:0] _zz_442_; - wire [4:0] _zz_443_; - wire [1:0] _zz_444_; - wire [1:0] _zz_445_; - wire _zz_446_; - wire [0:0] _zz_447_; - wire [3:0] _zz_448_; - wire [31:0] _zz_449_; - wire [31:0] _zz_450_; - wire _zz_451_; - wire [0:0] _zz_452_; - wire [1:0] _zz_453_; - wire [31:0] _zz_454_; - wire [31:0] _zz_455_; - wire [31:0] _zz_456_; - wire [31:0] _zz_457_; - wire [0:0] _zz_458_; - wire [0:0] _zz_459_; - wire [2:0] _zz_460_; - wire [2:0] _zz_461_; - wire _zz_462_; - wire [0:0] _zz_463_; - wire [0:0] _zz_464_; - wire [31:0] _zz_465_; - wire [31:0] _zz_466_; - wire [31:0] _zz_467_; - wire _zz_468_; - wire _zz_469_; - wire [31:0] _zz_470_; - wire [31:0] _zz_471_; - wire [31:0] _zz_472_; - wire [31:0] _zz_473_; - wire _zz_474_; - wire [0:0] _zz_475_; - wire [0:0] _zz_476_; - wire [0:0] _zz_477_; - wire [0:0] _zz_478_; - wire [1:0] _zz_479_; - wire [1:0] _zz_480_; - wire [2:0] _zz_481_; - wire [2:0] _zz_482_; - wire [31:0] _zz_483_; - wire [31:0] _zz_484_; - wire [31:0] _zz_485_; - wire [31:0] _zz_486_; - wire [31:0] _zz_487_; - wire [31:0] _zz_488_; - wire [31:0] _zz_489_; - wire [31:0] _zz_490_; - wire _zz_491_; - wire [0:0] _zz_492_; - wire [12:0] _zz_493_; - wire [31:0] _zz_494_; - wire [31:0] _zz_495_; - wire [31:0] _zz_496_; - wire _zz_497_; - wire [0:0] _zz_498_; - wire [6:0] _zz_499_; - wire [31:0] _zz_500_; - wire [31:0] _zz_501_; - wire [31:0] _zz_502_; - wire _zz_503_; - wire [0:0] _zz_504_; - wire [0:0] _zz_505_; - wire _zz_506_; - wire _zz_507_; - wire _zz_508_; - wire decode_PREDICTION_HAD_BRANCHED2; - wire decode_CSR_WRITE_OPCODE; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire decode_SRC_LESS_UNSIGNED; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_1_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_2_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_3_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_4_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_5_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_6_; - wire decode_IS_RS1_SIGNED; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire decode_IS_MUL; - wire execute_BRANCH_DO; - wire decode_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_11_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_12_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_13_; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_IS_DIV; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_14_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_15_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_16_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_17_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_18_; - wire decode_SRC2_FORCE_ZERO; - wire [31:0] execute_BRANCH_CALC; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire [31:0] memory_MEMORY_READ_DATA; - wire decode_IS_RS2_SIGNED; - wire decode_MEMORY_STORE; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_19_; - wire `AluCtrlEnum_defaultEncoding_type _zz_20_; - wire `AluCtrlEnum_defaultEncoding_type _zz_21_; - wire decode_CSR_READ_OPCODE; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_23_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_24_; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_MUL; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire memory_IS_MUL; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_25_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; - wire _zz_27_; - wire _zz_28_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_30_; - wire [31:0] execute_PC; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_31_; - wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_32_; - wire _zz_33_; - wire _zz_34_; - wire decode_RS2_USE; - wire decode_RS1_USE; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - reg [31:0] _zz_35_; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - reg [31:0] _zz_36_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_37_; - wire _zz_38_; - wire [31:0] _zz_39_; - wire [31:0] _zz_40_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_41_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_42_; - wire [31:0] _zz_43_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_44_; - wire [31:0] _zz_45_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_46_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_47_; - wire [31:0] _zz_48_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_49_; - wire [31:0] _zz_50_; - wire _zz_51_; - reg _zz_52_; - wire [31:0] _zz_53_; - wire [31:0] _zz_54_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_55_; - wire `AluCtrlEnum_defaultEncoding_type _zz_56_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_57_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_58_; - wire _zz_59_; - wire _zz_60_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_61_; - wire _zz_62_; - wire _zz_63_; - wire _zz_64_; - wire _zz_65_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_66_; - wire _zz_67_; - wire _zz_68_; - wire _zz_69_; - wire _zz_70_; - wire _zz_71_; - wire _zz_72_; - wire _zz_73_; - wire _zz_74_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_75_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_76_; - wire _zz_77_; - wire _zz_78_; - wire writeBack_MEMORY_STORE; - reg [31:0] _zz_79_; - wire writeBack_MEMORY_ENABLE; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP_physicalAddress; - wire memory_MMU_RSP_isIoAccess; - wire memory_MMU_RSP_allowRead; - wire memory_MMU_RSP_allowWrite; - wire memory_MMU_RSP_allowExecute; - wire memory_MMU_RSP_exception; - wire memory_MMU_RSP_refilling; - wire [31:0] memory_PC; - wire memory_ALIGNEMENT_FAULT; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_STORE; - wire memory_MEMORY_ENABLE; - wire [31:0] _zz_80_; - wire [31:0] _zz_81_; - wire _zz_82_; - wire _zz_83_; - wire _zz_84_; - wire _zz_85_; - wire _zz_86_; - wire _zz_87_; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP_physicalAddress; - wire execute_MMU_RSP_isIoAccess; - wire execute_MMU_RSP_allowRead; - wire execute_MMU_RSP_allowWrite; - wire execute_MMU_RSP_allowExecute; - wire execute_MMU_RSP_exception; - wire execute_MMU_RSP_refilling; - wire _zz_88_; - wire [31:0] execute_SRC_ADD; - wire [1:0] _zz_89_; - wire [31:0] execute_RS2; - wire [31:0] execute_INSTRUCTION; - wire execute_MEMORY_STORE; - wire execute_MEMORY_ENABLE; - wire execute_ALIGNEMENT_FAULT; - wire _zz_90_; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_91_; - reg _zz_92_; - reg _zz_93_; - wire [31:0] _zz_94_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_95_; - wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_96_; - reg [31:0] _zz_97_; - wire [31:0] decode_PC; - wire [31:0] _zz_98_; - wire [31:0] _zz_99_; - wire [31:0] _zz_100_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - wire decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - wire execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - wire execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - wire writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - wire writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_predictionJumpInterface_valid; - (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; - reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; - wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - reg DBusSimplePlugin_memoryExceptionPort_valid; - reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; - wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_isValid; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - wire CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - wire CsrPlugin_allowInterrupts; - wire CsrPlugin_allowException; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_101_; - wire [4:0] _zz_102_; - wire _zz_103_; - wire _zz_104_; - wire _zz_105_; - wire _zz_106_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_107_; - wire _zz_108_; - wire _zz_109_; - wire _zz_110_; - wire _zz_111_; - reg _zz_112_; - wire _zz_113_; - reg _zz_114_; - reg [31:0] _zz_115_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_decodeInput_valid; - wire IBusCachedPlugin_iBusRsp_decodeInput_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - reg IBusCachedPlugin_injector_decodeRemoved; - wire _zz_116_; - reg [18:0] _zz_117_; - wire _zz_118_; - reg [10:0] _zz_119_; - wire _zz_120_; - reg [18:0] _zz_121_; - reg _zz_122_; - wire _zz_123_; - reg [10:0] _zz_124_; - wire _zz_125_; - reg [18:0] _zz_126_; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_127_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [1:0] dBus_cmd_payload_size; - wire dBus_rsp_ready; - wire dBus_rsp_error; - wire [31:0] dBus_rsp_data; - wire _zz_128_; - reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_129_; - reg [3:0] _zz_130_; - wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_131_; - reg [31:0] _zz_132_; - wire _zz_133_; - reg [31:0] _zz_134_; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [30:0] _zz_135_; - wire _zz_136_; - wire _zz_137_; - wire _zz_138_; - wire _zz_139_; - wire _zz_140_; - wire _zz_141_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_142_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_143_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_144_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_145_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_146_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_147_; - wire `AluCtrlEnum_defaultEncoding_type _zz_148_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_149_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_150_; - reg [31:0] _zz_151_; - wire _zz_152_; - reg [19:0] _zz_153_; - wire _zz_154_; - reg [19:0] _zz_155_; - reg [31:0] _zz_156_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - reg execute_LightShifterPlugin_isActive; - wire execute_LightShifterPlugin_isShift; - reg [4:0] execute_LightShifterPlugin_amplitudeReg; - wire [4:0] execute_LightShifterPlugin_amplitude; - wire [31:0] execute_LightShifterPlugin_shiftInput; - wire execute_LightShifterPlugin_done; - reg [31:0] _zz_157_; - reg _zz_158_; - reg _zz_159_; - wire _zz_160_; - reg _zz_161_; - reg [4:0] _zz_162_; - reg [31:0] _zz_163_; - wire _zz_164_; - wire _zz_165_; - wire _zz_166_; - wire _zz_167_; - wire _zz_168_; - wire _zz_169_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_170_; - reg _zz_171_; - reg _zz_172_; - wire _zz_173_; - reg [19:0] _zz_174_; - wire _zz_175_; - reg [10:0] _zz_176_; - wire _zz_177_; - reg [18:0] _zz_178_; - reg _zz_179_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_180_; - reg [19:0] _zz_181_; - wire _zz_182_; - reg [10:0] _zz_183_; - wire _zz_184_; - reg [18:0] _zz_185_; - wire [31:0] execute_BranchPlugin_branchAdder; - wire [1:0] CsrPlugin_misa_base; - wire [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_186_; - wire _zz_187_; - wire _zz_188_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_189_; - wire _zz_190_; - wire [1:0] _zz_191_; - wire _zz_192_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - reg memory_MulDivIterativePlugin_mul_counter_willIncrement; - reg memory_MulDivIterativePlugin_mul_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; - wire memory_MulDivIterativePlugin_mul_willOverflowIfInc; - wire memory_MulDivIterativePlugin_mul_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_needRevert; - reg memory_MulDivIterativePlugin_div_counter_willIncrement; - reg memory_MulDivIterativePlugin_div_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_div_counter_value; - wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_div_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_done; - reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_193_; - wire [32:0] _zz_194_; - wire [32:0] _zz_195_; - wire [31:0] _zz_196_; - wire _zz_197_; - wire _zz_198_; - reg [32:0] _zz_199_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_200_; - wire [31:0] _zz_201_; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg decode_to_execute_CSR_READ_OPCODE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg decode_to_execute_MEMORY_STORE; - reg execute_to_memory_MEMORY_STORE; - reg memory_to_writeBack_MEMORY_STORE; - reg decode_to_execute_IS_RS2_SIGNED; - reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg [31:0] decode_to_execute_RS1; - reg execute_to_memory_ALIGNEMENT_FAULT; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_IS_CSR; - reg [31:0] execute_to_memory_MMU_RSP_physicalAddress; - reg execute_to_memory_MMU_RSP_isIoAccess; - reg execute_to_memory_MMU_RSP_allowRead; - reg execute_to_memory_MMU_RSP_allowWrite; - reg execute_to_memory_MMU_RSP_allowExecute; - reg execute_to_memory_MMU_RSP_exception; - reg execute_to_memory_MMU_RSP_refilling; - reg execute_to_memory_BRANCH_DO; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg decode_to_execute_IS_RS1_SIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg [31:0] decode_to_execute_RS2; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg execute_to_memory_MMU_FAULT; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg [2:0] _zz_202_; - reg _zz_203_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - wire dBus_cmd_halfPipe_valid; - wire dBus_cmd_halfPipe_ready; - wire dBus_cmd_halfPipe_payload_wr; - wire [31:0] dBus_cmd_halfPipe_payload_address; - wire [31:0] dBus_cmd_halfPipe_payload_data; - wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_204_; + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_154; + wire _zz_155; + wire _zz_156; + wire _zz_157; + wire _zz_158; + wire _zz_159; + wire _zz_160; + wire _zz_161; + reg _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_166; + wire _zz_167; + wire _zz_168; + wire _zz_169; + wire _zz_170; + wire _zz_171; + wire _zz_172; + wire _zz_173; + wire _zz_174; + wire _zz_175; + wire _zz_176; + wire _zz_177; + wire _zz_178; + wire _zz_179; + wire _zz_180; + wire _zz_181; + wire _zz_182; + wire [1:0] _zz_183; + wire _zz_184; + wire _zz_185; + wire _zz_186; + wire _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + wire _zz_191; + wire _zz_192; + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + wire _zz_201; + wire _zz_202; + wire [1:0] _zz_203; + wire _zz_204; + wire [0:0] _zz_205; + wire [0:0] _zz_206; + wire [0:0] _zz_207; + wire [0:0] _zz_208; + wire [0:0] _zz_209; + wire [0:0] _zz_210; + wire [0:0] _zz_211; + wire [0:0] _zz_212; + wire [0:0] _zz_213; + wire [0:0] _zz_214; + wire [0:0] _zz_215; + wire [0:0] _zz_216; + wire [0:0] _zz_217; + wire [0:0] _zz_218; + wire [0:0] _zz_219; + wire [0:0] _zz_220; + wire [3:0] _zz_221; + wire [2:0] _zz_222; + wire [31:0] _zz_223; + wire [11:0] _zz_224; + wire [31:0] _zz_225; + wire [19:0] _zz_226; + wire [11:0] _zz_227; + wire [31:0] _zz_228; + wire [31:0] _zz_229; + wire [19:0] _zz_230; + wire [11:0] _zz_231; + wire [2:0] _zz_232; + wire [0:0] _zz_233; + wire [2:0] _zz_234; + wire [4:0] _zz_235; + wire [11:0] _zz_236; + wire [11:0] _zz_237; + wire [31:0] _zz_238; + wire [31:0] _zz_239; + wire [31:0] _zz_240; + wire [31:0] _zz_241; + wire [31:0] _zz_242; + wire [31:0] _zz_243; + wire [31:0] _zz_244; + wire [31:0] _zz_245; + wire [32:0] _zz_246; + wire [11:0] _zz_247; + wire [19:0] _zz_248; + wire [11:0] _zz_249; + wire [31:0] _zz_250; + wire [31:0] _zz_251; + wire [31:0] _zz_252; + wire [11:0] _zz_253; + wire [19:0] _zz_254; + wire [11:0] _zz_255; + wire [2:0] _zz_256; + wire [1:0] _zz_257; + wire [1:0] _zz_258; + wire [1:0] _zz_259; + wire [1:0] _zz_260; + wire [0:0] _zz_261; + wire [5:0] _zz_262; + wire [33:0] _zz_263; + wire [32:0] _zz_264; + wire [33:0] _zz_265; + wire [32:0] _zz_266; + wire [33:0] _zz_267; + wire [32:0] _zz_268; + wire [0:0] _zz_269; + wire [5:0] _zz_270; + wire [32:0] _zz_271; + wire [31:0] _zz_272; + wire [31:0] _zz_273; + wire [32:0] _zz_274; + wire [32:0] _zz_275; + wire [32:0] _zz_276; + wire [32:0] _zz_277; + wire [0:0] _zz_278; + wire [32:0] _zz_279; + wire [0:0] _zz_280; + wire [32:0] _zz_281; + wire [0:0] _zz_282; + wire [31:0] _zz_283; + wire [0:0] _zz_284; + wire [0:0] _zz_285; + wire [0:0] _zz_286; + wire [0:0] _zz_287; + wire [0:0] _zz_288; + wire [0:0] _zz_289; + wire [26:0] _zz_290; + wire _zz_291; + wire _zz_292; + wire [1:0] _zz_293; + wire [31:0] _zz_294; + wire [31:0] _zz_295; + wire [31:0] _zz_296; + wire _zz_297; + wire [0:0] _zz_298; + wire [12:0] _zz_299; + wire [31:0] _zz_300; + wire [31:0] _zz_301; + wire [31:0] _zz_302; + wire _zz_303; + wire [0:0] _zz_304; + wire [6:0] _zz_305; + wire [31:0] _zz_306; + wire [31:0] _zz_307; + wire [31:0] _zz_308; + wire _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire _zz_312; + wire _zz_313; + wire _zz_314; + wire [31:0] _zz_315; + wire [0:0] _zz_316; + wire [1:0] _zz_317; + wire [0:0] _zz_318; + wire [0:0] _zz_319; + wire _zz_320; + wire [0:0] _zz_321; + wire [24:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [0:0] _zz_326; + wire [0:0] _zz_327; + wire [1:0] _zz_328; + wire [1:0] _zz_329; + wire _zz_330; + wire [0:0] _zz_331; + wire [20:0] _zz_332; + wire [31:0] _zz_333; + wire [31:0] _zz_334; + wire [31:0] _zz_335; + wire [31:0] _zz_336; + wire [31:0] _zz_337; + wire [31:0] _zz_338; + wire [0:0] _zz_339; + wire [0:0] _zz_340; + wire [2:0] _zz_341; + wire [2:0] _zz_342; + wire _zz_343; + wire [0:0] _zz_344; + wire [17:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; + wire [31:0] _zz_349; + wire _zz_350; + wire _zz_351; + wire _zz_352; + wire [0:0] _zz_353; + wire [0:0] _zz_354; + wire _zz_355; + wire [0:0] _zz_356; + wire [0:0] _zz_357; + wire _zz_358; + wire [0:0] _zz_359; + wire [14:0] _zz_360; + wire [31:0] _zz_361; + wire [31:0] _zz_362; + wire [31:0] _zz_363; + wire [31:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire [31:0] _zz_367; + wire [31:0] _zz_368; + wire [0:0] _zz_369; + wire [0:0] _zz_370; + wire [1:0] _zz_371; + wire [1:0] _zz_372; + wire _zz_373; + wire [0:0] _zz_374; + wire [12:0] _zz_375; + wire [31:0] _zz_376; + wire [31:0] _zz_377; + wire [31:0] _zz_378; + wire [31:0] _zz_379; + wire [31:0] _zz_380; + wire [31:0] _zz_381; + wire _zz_382; + wire [0:0] _zz_383; + wire [0:0] _zz_384; + wire _zz_385; + wire [0:0] _zz_386; + wire [0:0] _zz_387; + wire _zz_388; + wire [0:0] _zz_389; + wire [9:0] _zz_390; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire [31:0] _zz_393; + wire [0:0] _zz_394; + wire [0:0] _zz_395; + wire [0:0] _zz_396; + wire [4:0] _zz_397; + wire [1:0] _zz_398; + wire [1:0] _zz_399; + wire _zz_400; + wire [0:0] _zz_401; + wire [6:0] _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire [31:0] _zz_405; + wire [31:0] _zz_406; + wire _zz_407; + wire [0:0] _zz_408; + wire [1:0] _zz_409; + wire [31:0] _zz_410; + wire [31:0] _zz_411; + wire _zz_412; + wire [0:0] _zz_413; + wire [0:0] _zz_414; + wire [0:0] _zz_415; + wire [0:0] _zz_416; + wire _zz_417; + wire [0:0] _zz_418; + wire [3:0] _zz_419; + wire [31:0] _zz_420; + wire [31:0] _zz_421; + wire [31:0] _zz_422; + wire _zz_423; + wire _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire [31:0] _zz_427; + wire [31:0] _zz_428; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire [31:0] _zz_431; + wire [0:0] _zz_432; + wire [2:0] _zz_433; + wire [0:0] _zz_434; + wire [0:0] _zz_435; + wire _zz_436; + wire [0:0] _zz_437; + wire [1:0] _zz_438; + wire [31:0] _zz_439; + wire [31:0] _zz_440; + wire [31:0] _zz_441; + wire [31:0] _zz_442; + wire _zz_443; + wire [0:0] _zz_444; + wire [0:0] _zz_445; + wire [31:0] _zz_446; + wire [31:0] _zz_447; + wire [0:0] _zz_448; + wire [1:0] _zz_449; + wire [1:0] _zz_450; + wire [1:0] _zz_451; + wire _zz_452; + wire _zz_453; + wire [31:0] _zz_454; + wire [31:0] _zz_455; + wire [31:0] _zz_456; + wire [31:0] _zz_457; + wire [31:0] _zz_458; + wire [31:0] _zz_459; + wire [31:0] _zz_460; + wire [31:0] _zz_461; + wire [31:0] _zz_462; + wire _zz_463; + wire [31:0] _zz_464; + wire [31:0] _zz_465; + wire _zz_466; + wire _zz_467; + wire _zz_468; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_DIV; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_13; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_16; + wire `Src2CtrlEnum_defaultEncoding_type _zz_17; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_19; + wire `AluCtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_22; + wire `Src1CtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_MUL; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire memory_IS_MUL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_25; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_26; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + wire [31:0] execute_RS1; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_28; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + reg [31:0] _zz_29; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + reg [31:0] _zz_30; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_31; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_32; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_33; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_34; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_36; + wire [31:0] _zz_37; + wire _zz_38; + reg _zz_39; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_40; + wire `BranchCtrlEnum_defaultEncoding_type _zz_41; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_42; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; + wire `Src2CtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_defaultEncoding_type _zz_45; + wire `Src1CtrlEnum_defaultEncoding_type _zz_46; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_47; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP2_physicalAddress; + wire memory_MMU_RSP2_isIoAccess; + wire memory_MMU_RSP2_isPaging; + wire memory_MMU_RSP2_allowRead; + wire memory_MMU_RSP2_allowWrite; + wire memory_MMU_RSP2_allowExecute; + wire memory_MMU_RSP2_exception; + wire memory_MMU_RSP2_refilling; + wire memory_MMU_RSP2_bypassTranslation; + wire [31:0] memory_PC; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire execute_MMU_FAULT; + wire [31:0] execute_MMU_RSP2_physicalAddress; + wire execute_MMU_RSP2_isIoAccess; + wire execute_MMU_RSP2_isPaging; + wire execute_MMU_RSP2_allowRead; + wire execute_MMU_RSP2_allowWrite; + wire execute_MMU_RSP2_allowExecute; + wire execute_MMU_RSP2_exception; + wire execute_MMU_RSP2_refilling; + wire execute_MMU_RSP2_bypassTranslation; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_48; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_49; + reg [31:0] _zz_50; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire DBusSimplePlugin_mmuBus_cmd_0_isValid; + wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire DBusSimplePlugin_mmuBus_rsp_isPaging; + wire DBusSimplePlugin_mmuBus_rsp_allowRead; + wire DBusSimplePlugin_mmuBus_rsp_allowWrite; + wire DBusSimplePlugin_mmuBus_rsp_allowExecute; + wire DBusSimplePlugin_mmuBus_rsp_exception; + wire DBusSimplePlugin_mmuBus_rsp_refilling; + wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire DBusSimplePlugin_mmuBus_end; + wire DBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_redoBranch_valid; + wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_51; + wire [3:0] _zz_52; + wire _zz_53; + wire _zz_54; + wire _zz_55; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_56; + wire _zz_57; + wire _zz_58; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_59; + wire _zz_60; + reg _zz_61; + wire _zz_62; + reg _zz_63; + reg [31:0] _zz_64; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_65; + reg [18:0] _zz_66; + wire _zz_67; + reg [10:0] _zz_68; + wire _zz_69; + reg [18:0] _zz_70; + reg _zz_71; + wire _zz_72; + reg [10:0] _zz_73; + wire _zz_74; + reg [18:0] _zz_75; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_76; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire _zz_77; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_78; + reg [3:0] _zz_79; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_80; + reg [31:0] _zz_81; + wire _zz_82; + reg [31:0] _zz_83; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [30:0] _zz_84; + wire _zz_85; + wire _zz_86; + wire _zz_87; + wire _zz_88; + wire _zz_89; + wire _zz_90; + wire `Src1CtrlEnum_defaultEncoding_type _zz_91; + wire `AluCtrlEnum_defaultEncoding_type _zz_92; + wire `Src2CtrlEnum_defaultEncoding_type _zz_93; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_94; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_95; + wire `BranchCtrlEnum_defaultEncoding_type _zz_96; + wire `EnvCtrlEnum_defaultEncoding_type _zz_97; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_98; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_99; + reg [31:0] _zz_100; + wire _zz_101; + reg [19:0] _zz_102; + wire _zz_103; + reg [19:0] _zz_104; + reg [31:0] _zz_105; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_106; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_107; + wire _zz_108; + wire _zz_109; + wire _zz_110; + wire _zz_111; + wire _zz_112; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_113; + reg _zz_114; + reg _zz_115; + wire _zz_116; + reg [19:0] _zz_117; + wire _zz_118; + reg [10:0] _zz_119; + wire _zz_120; + reg [18:0] _zz_121; + reg _zz_122; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_123; + reg [19:0] _zz_124; + wire _zz_125; + reg [10:0] _zz_126; + wire _zz_127; + reg [18:0] _zz_128; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_129; + wire _zz_130; + wire _zz_131; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_132; + wire _zz_133; + wire [1:0] _zz_134; + wire _zz_135; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_mul_counter_willIncrement; + reg memory_MulDivIterativePlugin_mul_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; + wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire [31:0] _zz_136; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [31:0] _zz_137; + wire _zz_138; + wire _zz_139; + reg [32:0] _zz_140; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_141; + wire [31:0] _zz_142; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; + reg execute_to_memory_MMU_RSP2_isIoAccess; + reg execute_to_memory_MMU_RSP2_isPaging; + reg execute_to_memory_MMU_RSP2_allowRead; + reg execute_to_memory_MMU_RSP2_allowWrite; + reg execute_to_memory_MMU_RSP2_allowExecute; + reg execute_to_memory_MMU_RSP2_exception; + reg execute_to_memory_MMU_RSP2_refilling; + reg execute_to_memory_MMU_RSP2_bypassTranslation; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_143; + reg [31:0] _zz_144; + reg [31:0] _zz_145; + reg [31:0] _zz_146; + reg [31:0] _zz_147; + reg [31:0] _zz_148; + reg [31:0] _zz_149; + reg [31:0] _zz_150; + reg [2:0] _zz_151; + reg _zz_152; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_153; `ifndef SYNTHESIS - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_1__string; - reg [95:0] _zz_2__string; - reg [95:0] _zz_3__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_4__string; - reg [39:0] _zz_5__string; - reg [39:0] _zz_6__string; - reg [39:0] _zz_7__string; - reg [39:0] _zz_8__string; - reg [39:0] _zz_9__string; - reg [39:0] _zz_10__string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_11__string; - reg [39:0] _zz_12__string; - reg [39:0] _zz_13__string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] _zz_12_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_13_string; + reg [39:0] _zz_14_string; + reg [39:0] _zz_15_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_14__string; - reg [23:0] _zz_15__string; - reg [23:0] _zz_16__string; - reg [31:0] _zz_17__string; - reg [31:0] _zz_18__string; + reg [23:0] _zz_16_string; + reg [23:0] _zz_17_string; + reg [23:0] _zz_18_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_19__string; - reg [63:0] _zz_20__string; - reg [63:0] _zz_21__string; - reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_22__string; - reg [71:0] _zz_23__string; - reg [71:0] _zz_24__string; + reg [63:0] _zz_19_string; + reg [63:0] _zz_20_string; + reg [63:0] _zz_21_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_22_string; + reg [95:0] _zz_23_string; + reg [95:0] _zz_24_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_25__string; + reg [39:0] _zz_25_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_26__string; + reg [39:0] _zz_26_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_29__string; + reg [39:0] _zz_27_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_32__string; + reg [31:0] _zz_28_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_37__string; + reg [71:0] _zz_31_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_42__string; + reg [23:0] _zz_33_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_44__string; + reg [95:0] _zz_34_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_47__string; + reg [63:0] _zz_35_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_49__string; - reg [63:0] _zz_56__string; - reg [39:0] _zz_57__string; - reg [39:0] _zz_58__string; - reg [31:0] _zz_61__string; - reg [95:0] _zz_66__string; - reg [71:0] _zz_75__string; - reg [23:0] _zz_76__string; + reg [39:0] _zz_36_string; + reg [39:0] _zz_40_string; + reg [31:0] _zz_41_string; + reg [71:0] _zz_42_string; + reg [39:0] _zz_43_string; + reg [23:0] _zz_44_string; + reg [63:0] _zz_45_string; + reg [95:0] _zz_46_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_95__string; - reg [23:0] _zz_142__string; - reg [71:0] _zz_143__string; - reg [95:0] _zz_144__string; - reg [31:0] _zz_145__string; - reg [39:0] _zz_146__string; - reg [39:0] _zz_147__string; - reg [63:0] _zz_148__string; - reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] _zz_48_string; + reg [95:0] _zz_91_string; + reg [63:0] _zz_92_string; + reg [23:0] _zz_93_string; + reg [39:0] _zz_94_string; + reg [71:0] _zz_95_string; + reg [31:0] _zz_96_string; + reg [39:0] _zz_97_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [39:0] decode_to_execute_ENV_CTRL_string; reg [39:0] execute_to_memory_ENV_CTRL_string; reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; `endif (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_217_ = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_218_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_219_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_220_ = 1'b1; - assign _zz_221_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_222_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_223_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); - assign _zz_224_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_225_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_91_)); - assign _zz_226_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_92_)); - assign _zz_227_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_93_)); - assign _zz_228_ = ((_zz_210_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); - assign _zz_229_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_230_ = (! execute_arbitration_isStuckByOthers); - assign _zz_231_ = (! memory_MulDivIterativePlugin_mul_willOverflowIfInc); - assign _zz_232_ = (! memory_MulDivIterativePlugin_div_done); - assign _zz_233_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00)); - assign _zz_234_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_235_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_236_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_237_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_238_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_239_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_240_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_241_ = (1'b0 || (! 1'b1)); - assign _zz_242_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_243_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_244_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_245_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_246_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_247_ = (! memory_arbitration_isStuck); - assign _zz_248_ = (iBus_cmd_valid || (_zz_202_ != (3'b000))); - assign _zz_249_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_250_ = ((_zz_186_ && 1'b1) && (! 1'b0)); - assign _zz_251_ = ((_zz_187_ && 1'b1) && (! 1'b0)); - assign _zz_252_ = ((_zz_188_ && 1'b1) && (! 1'b0)); - assign _zz_253_ = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_254_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_255_ = execute_INSTRUCTION[13]; - assign _zz_256_ = (_zz_101_ - (5'b00001)); - assign _zz_257_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_258_ = {29'd0, _zz_257_}; - assign _zz_259_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_260_ = {{_zz_117_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_261_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_262_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_263_ = {{_zz_119_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_264_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_265_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_266_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_267_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100)); - assign _zz_268_ = _zz_135_[0 : 0]; - assign _zz_269_ = _zz_135_[5 : 5]; - assign _zz_270_ = _zz_135_[6 : 6]; - assign _zz_271_ = _zz_135_[7 : 7]; - assign _zz_272_ = _zz_135_[8 : 8]; - assign _zz_273_ = _zz_135_[10 : 10]; - assign _zz_274_ = _zz_135_[11 : 11]; - assign _zz_275_ = _zz_135_[12 : 12]; - assign _zz_276_ = _zz_135_[13 : 13]; - assign _zz_277_ = _zz_135_[16 : 16]; - assign _zz_278_ = _zz_135_[17 : 17]; - assign _zz_279_ = _zz_135_[18 : 18]; - assign _zz_280_ = _zz_135_[19 : 19]; - assign _zz_281_ = _zz_135_[22 : 22]; - assign _zz_282_ = _zz_135_[23 : 23]; - assign _zz_283_ = _zz_135_[30 : 30]; - assign _zz_284_ = execute_SRC_LESS; - assign _zz_285_ = (3'b100); - assign _zz_286_ = execute_INSTRUCTION[19 : 15]; - assign _zz_287_ = execute_INSTRUCTION[31 : 20]; - assign _zz_288_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_289_ = ($signed(_zz_290_) + $signed(_zz_293_)); - assign _zz_290_ = ($signed(_zz_291_) + $signed(_zz_292_)); - assign _zz_291_ = execute_SRC1; - assign _zz_292_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_293_ = (execute_SRC_USE_SUB_LESS ? _zz_294_ : _zz_295_); - assign _zz_294_ = (32'b00000000000000000000000000000001); - assign _zz_295_ = (32'b00000000000000000000000000000000); - assign _zz_296_ = (_zz_297_ >>> 1); - assign _zz_297_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_298_ = execute_INSTRUCTION[31 : 20]; - assign _zz_299_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_300_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_301_ = {_zz_174_,execute_INSTRUCTION[31 : 20]}; - assign _zz_302_ = {{_zz_176_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_303_ = {{_zz_178_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_304_ = execute_INSTRUCTION[31 : 20]; - assign _zz_305_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_306_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_307_ = (3'b100); - assign _zz_308_ = (_zz_189_ & (~ _zz_309_)); - assign _zz_309_ = (_zz_189_ - (2'b01)); - assign _zz_310_ = (_zz_191_ & (~ _zz_311_)); - assign _zz_311_ = (_zz_191_ - (2'b01)); - assign _zz_312_ = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_313_ = {5'd0, _zz_312_}; - assign _zz_314_ = (_zz_316_ + _zz_318_); - assign _zz_315_ = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : (33'b000000000000000000000000000000000)); - assign _zz_316_ = {{1{_zz_315_[32]}}, _zz_315_}; - assign _zz_317_ = _zz_319_; - assign _zz_318_ = {{1{_zz_317_[32]}}, _zz_317_}; - assign _zz_319_ = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_320_ = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_321_ = {5'd0, _zz_320_}; - assign _zz_322_ = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_323_ = {_zz_193_,(! _zz_195_[32])}; - assign _zz_324_ = _zz_195_[31:0]; - assign _zz_325_ = _zz_194_[31:0]; - assign _zz_326_ = _zz_327_; - assign _zz_327_ = _zz_328_; - assign _zz_328_ = ({1'b0,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_196_) : _zz_196_)} + _zz_330_); - assign _zz_329_ = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_330_ = {32'd0, _zz_329_}; - assign _zz_331_ = _zz_198_; - assign _zz_332_ = {32'd0, _zz_331_}; - assign _zz_333_ = _zz_197_; - assign _zz_334_ = {31'd0, _zz_333_}; - assign _zz_335_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_336_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_337_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_338_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_339_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_340_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_341_ = (iBus_cmd_payload_address >>> 5); - assign _zz_342_ = ({3'd0,_zz_204_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - assign _zz_343_ = 1'b1; - assign _zz_344_ = 1'b1; - assign _zz_345_ = {_zz_104_,{_zz_106_,_zz_105_}}; - assign _zz_346_ = decode_INSTRUCTION[31]; - assign _zz_347_ = decode_INSTRUCTION[31]; - assign _zz_348_ = decode_INSTRUCTION[7]; - assign _zz_349_ = (32'b00000000000000000001000001001000); - assign _zz_350_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000110000000010000)); - assign _zz_351_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000010100)) == (32'b00000000000000000100000000010000)); - assign _zz_352_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)); - assign _zz_353_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_354_ = (1'b0); - assign _zz_355_ = (_zz_137_ != (1'b0)); - assign _zz_356_ = ((_zz_358_ == _zz_359_) != (1'b0)); - assign _zz_357_ = {(_zz_360_ != (1'b0)),{(_zz_361_ != _zz_362_),{_zz_363_,{_zz_364_,_zz_365_}}}}; - assign _zz_358_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000)); - assign _zz_359_ = (32'b00000000000000000000000001010000); - assign _zz_360_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); - assign _zz_361_ = {(_zz_366_ == _zz_367_),{_zz_368_,_zz_369_}}; - assign _zz_362_ = (3'b000); - assign _zz_363_ = ((_zz_370_ == _zz_371_) != (1'b0)); - assign _zz_364_ = ({_zz_372_,_zz_373_} != (2'b00)); - assign _zz_365_ = {(_zz_374_ != _zz_375_),{_zz_376_,{_zz_377_,_zz_378_}}}; - assign _zz_366_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_367_ = (32'b00000000000000000000000000100100); - assign _zz_368_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000110100)) == (32'b00000000000000000001000000010000)); - assign _zz_369_ = ((decode_INSTRUCTION & (32'b00000010000000000011000001010100)) == (32'b00000000000000000001000000010000)); - assign _zz_370_ = (decode_INSTRUCTION & (32'b00000010000000000100000001110100)); - assign _zz_371_ = (32'b00000010000000000000000000110000); - assign _zz_372_ = _zz_140_; - assign _zz_373_ = ((decode_INSTRUCTION & _zz_379_) == (32'b00000000000000000000000000000100)); - assign _zz_374_ = ((decode_INSTRUCTION & _zz_380_) == (32'b00000000000000000000000001000000)); - assign _zz_375_ = (1'b0); - assign _zz_376_ = ({_zz_139_,{_zz_381_,_zz_382_}} != (3'b000)); - assign _zz_377_ = (_zz_383_ != (1'b0)); - assign _zz_378_ = {(_zz_384_ != _zz_385_),{_zz_386_,{_zz_387_,_zz_388_}}}; - assign _zz_379_ = (32'b00000000000000000000000000011100); - assign _zz_380_ = (32'b00000000000000000000000001011000); - assign _zz_381_ = ((decode_INSTRUCTION & _zz_389_) == (32'b00000000000000000000000000010000)); - assign _zz_382_ = ((decode_INSTRUCTION & _zz_390_) == (32'b00000000000000000000000000100000)); - assign _zz_383_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001100100)) == (32'b00000010000000000100000000100000)); - assign _zz_384_ = {(_zz_391_ == _zz_392_),{_zz_393_,{_zz_394_,_zz_395_}}}; - assign _zz_385_ = (4'b0000); - assign _zz_386_ = ({_zz_396_,_zz_397_} != (2'b00)); - assign _zz_387_ = ({_zz_398_,_zz_399_} != (2'b00)); - assign _zz_388_ = {(_zz_400_ != _zz_401_),{_zz_402_,{_zz_403_,_zz_404_}}}; - assign _zz_389_ = (32'b00000000000000000000000000110000); - assign _zz_390_ = (32'b00000010000000000000000001100000); - assign _zz_391_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_392_ = (32'b00000000000000000000000000000000); - assign _zz_393_ = ((decode_INSTRUCTION & _zz_405_) == (32'b00000000000000000000000000000000)); - assign _zz_394_ = (_zz_406_ == _zz_407_); - assign _zz_395_ = (_zz_408_ == _zz_409_); - assign _zz_396_ = ((decode_INSTRUCTION & _zz_410_) == (32'b00000000000000000001000001010000)); - assign _zz_397_ = ((decode_INSTRUCTION & _zz_411_) == (32'b00000000000000000010000001010000)); - assign _zz_398_ = (_zz_412_ == _zz_413_); - assign _zz_399_ = _zz_141_; - assign _zz_400_ = {_zz_414_,_zz_141_}; - assign _zz_401_ = (2'b00); - assign _zz_402_ = (_zz_415_ != (1'b0)); - assign _zz_403_ = (_zz_416_ != _zz_417_); - assign _zz_404_ = {_zz_418_,{_zz_419_,_zz_420_}}; - assign _zz_405_ = (32'b00000000000000000000000000011000); - assign _zz_406_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); - assign _zz_407_ = (32'b00000000000000000010000000000000); - assign _zz_408_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); - assign _zz_409_ = (32'b00000000000000000001000000000000); - assign _zz_410_ = (32'b00000000000000000001000001010000); - assign _zz_411_ = (32'b00000000000000000010000001010000); - assign _zz_412_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100)); - assign _zz_413_ = (32'b00000000000000000000000000000100); - assign _zz_414_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); - assign _zz_415_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); - assign _zz_416_ = {(_zz_421_ == _zz_422_),(_zz_423_ == _zz_424_)}; - assign _zz_417_ = (2'b00); - assign _zz_418_ = ({_zz_425_,{_zz_426_,_zz_427_}} != (3'b000)); - assign _zz_419_ = (_zz_428_ != (1'b0)); - assign _zz_420_ = {(_zz_429_ != _zz_430_),{_zz_431_,{_zz_432_,_zz_433_}}}; - assign _zz_421_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); - assign _zz_422_ = (32'b00000000000000000000000000100000); - assign _zz_423_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_424_ = (32'b00000000000000000000000000100000); - assign _zz_425_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); - assign _zz_426_ = ((decode_INSTRUCTION & _zz_434_) == (32'b00000000000000000010000000010000)); - assign _zz_427_ = ((decode_INSTRUCTION & _zz_435_) == (32'b01000000000000000000000000110000)); - assign _zz_428_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000)); - assign _zz_429_ = {(_zz_436_ == _zz_437_),{_zz_438_,_zz_439_}}; - assign _zz_430_ = (3'b000); - assign _zz_431_ = ((_zz_440_ == _zz_441_) != (1'b0)); - assign _zz_432_ = ({_zz_442_,_zz_443_} != (6'b000000)); - assign _zz_433_ = {(_zz_444_ != _zz_445_),{_zz_446_,{_zz_447_,_zz_448_}}}; - assign _zz_434_ = (32'b00000000000000000010000000010100); - assign _zz_435_ = (32'b01000000000000000100000000110100); - assign _zz_436_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000)); - assign _zz_437_ = (32'b00000000000000000000000001000000); - assign _zz_438_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000111000)) == (32'b00000000000000000000000000000000)); - assign _zz_439_ = ((decode_INSTRUCTION & (32'b00000000010000000011000001000000)) == (32'b00000000000000000000000001000000)); - assign _zz_440_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_441_ = (32'b00000000000000000000000000000000); - assign _zz_442_ = _zz_140_; - assign _zz_443_ = {(_zz_449_ == _zz_450_),{_zz_451_,{_zz_452_,_zz_453_}}}; - assign _zz_444_ = {(_zz_454_ == _zz_455_),(_zz_456_ == _zz_457_)}; - assign _zz_445_ = (2'b00); - assign _zz_446_ = ({_zz_138_,_zz_136_} != (2'b00)); - assign _zz_447_ = ({_zz_458_,_zz_459_} != (2'b00)); - assign _zz_448_ = {(_zz_460_ != _zz_461_),{_zz_462_,{_zz_463_,_zz_464_}}}; - assign _zz_449_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); - assign _zz_450_ = (32'b00000000000000000001000000010000); - assign _zz_451_ = ((decode_INSTRUCTION & _zz_465_) == (32'b00000000000000000010000000010000)); - assign _zz_452_ = (_zz_466_ == _zz_467_); - assign _zz_453_ = {_zz_468_,_zz_469_}; - assign _zz_454_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_455_ = (32'b00000000000000000010000000000000); - assign _zz_456_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); - assign _zz_457_ = (32'b00000000000000000001000000000000); - assign _zz_458_ = (_zz_470_ == _zz_471_); - assign _zz_459_ = (_zz_472_ == _zz_473_); - assign _zz_460_ = {_zz_474_,{_zz_475_,_zz_476_}}; - assign _zz_461_ = (3'b000); - assign _zz_462_ = ({_zz_477_,_zz_478_} != (2'b00)); - assign _zz_463_ = (_zz_479_ != _zz_480_); - assign _zz_464_ = (_zz_481_ != _zz_482_); - assign _zz_465_ = (32'b00000000000000000010000000010000); - assign _zz_466_ = (decode_INSTRUCTION & (32'b00000000000000000000000001010000)); - assign _zz_467_ = (32'b00000000000000000000000000010000); - assign _zz_468_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)); - assign _zz_469_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000)); - assign _zz_470_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_471_ = (32'b00000000000000000101000000010000); - assign _zz_472_ = (decode_INSTRUCTION & (32'b00000010000000000111000001100100)); - assign _zz_473_ = (32'b00000000000000000101000000100000); - assign _zz_474_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); - assign _zz_475_ = ((decode_INSTRUCTION & _zz_483_) == (32'b00000000000000000001000000010000)); - assign _zz_476_ = ((decode_INSTRUCTION & _zz_484_) == (32'b00000000000000000001000000010000)); - assign _zz_477_ = _zz_139_; - assign _zz_478_ = ((decode_INSTRUCTION & _zz_485_) == (32'b00000000000000000000000000100000)); - assign _zz_479_ = {_zz_139_,(_zz_486_ == _zz_487_)}; - assign _zz_480_ = (2'b00); - assign _zz_481_ = {_zz_138_,{_zz_137_,_zz_136_}}; - assign _zz_482_ = (3'b000); - assign _zz_483_ = (32'b00000000000000000111000000110100); - assign _zz_484_ = (32'b00000010000000000111000001010100); - assign _zz_485_ = (32'b00000000000000000000000001110000); - assign _zz_486_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_487_ = (32'b00000000000000000000000000000000); - assign _zz_488_ = (32'b00000000000000000001000001111111); - assign _zz_489_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_490_ = (32'b00000000000000000010000001110011); - assign _zz_491_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_492_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_493_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_494_) == (32'b00000000000000000000000000000011)),{(_zz_495_ == _zz_496_),{_zz_497_,{_zz_498_,_zz_499_}}}}}}; - assign _zz_494_ = (32'b00000000000000000101000001011111); - assign _zz_495_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_496_ = (32'b00000000000000000000000001100011); - assign _zz_497_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_498_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_499_ = {((decode_INSTRUCTION & (32'b11111100000000000011000001011111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_500_) == (32'b00000000000000000101000000110011)),{(_zz_501_ == _zz_502_),{_zz_503_,{_zz_504_,_zz_505_}}}}}}; - assign _zz_500_ = (32'b10111110000000000111000001111111); - assign _zz_501_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_502_ = (32'b00000000000000000000000000110011); - assign _zz_503_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_504_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); - assign _zz_505_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011)); - assign _zz_506_ = execute_INSTRUCTION[31]; - assign _zz_507_ = execute_INSTRUCTION[31]; - assign _zz_508_ = execute_INSTRUCTION[7]; + + assign _zz_166 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_167 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_168 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_169 = 1'b1; + assign _zz_170 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_171 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_172 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_173 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_174 = ((_zz_159 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_175 = ((_zz_159 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_176 = ((_zz_159 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_177 = ((_zz_159 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_178 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_179 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_180 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_181 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_182 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_183 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_184 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_185 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_186 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_187 = (1'b0 || (! 1'b1)); + assign _zz_188 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_189 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_190 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_191 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_192 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_193 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_194 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_195 = (! memory_arbitration_isStuck); + assign _zz_196 = (iBus_cmd_valid || (_zz_151 != 3'b000)); + assign _zz_197 = (! execute_arbitration_isStuckByOthers); + assign _zz_198 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_199 = ((_zz_129 && 1'b1) && (! 1'b0)); + assign _zz_200 = ((_zz_130 && 1'b1) && (! 1'b0)); + assign _zz_201 = ((_zz_131 && 1'b1) && (! 1'b0)); + assign _zz_202 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_203 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_204 = execute_INSTRUCTION[13]; + assign _zz_205 = _zz_84[30 : 30]; + assign _zz_206 = _zz_84[29 : 29]; + assign _zz_207 = _zz_84[28 : 28]; + assign _zz_208 = _zz_84[27 : 27]; + assign _zz_209 = _zz_84[24 : 24]; + assign _zz_210 = _zz_84[16 : 16]; + assign _zz_211 = _zz_84[13 : 13]; + assign _zz_212 = _zz_84[12 : 12]; + assign _zz_213 = _zz_84[11 : 11]; + assign _zz_214 = _zz_84[15 : 15]; + assign _zz_215 = _zz_84[5 : 5]; + assign _zz_216 = _zz_84[3 : 3]; + assign _zz_217 = _zz_84[19 : 19]; + assign _zz_218 = _zz_84[10 : 10]; + assign _zz_219 = _zz_84[4 : 4]; + assign _zz_220 = _zz_84[0 : 0]; + assign _zz_221 = (_zz_51 - 4'b0001); + assign _zz_222 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_223 = {29'd0, _zz_222}; + assign _zz_224 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_225 = {{_zz_66,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_226 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_227 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_228 = {{_zz_68,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_229 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_230 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_231 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_232 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_233 = execute_SRC_LESS; + assign _zz_234 = 3'b100; + assign _zz_235 = execute_INSTRUCTION[19 : 15]; + assign _zz_236 = execute_INSTRUCTION[31 : 20]; + assign _zz_237 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_238 = ($signed(_zz_239) + $signed(_zz_242)); + assign _zz_239 = ($signed(_zz_240) + $signed(_zz_241)); + assign _zz_240 = execute_SRC1; + assign _zz_241 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_242 = (execute_SRC_USE_SUB_LESS ? _zz_243 : _zz_244); + assign _zz_243 = 32'h00000001; + assign _zz_244 = 32'h0; + assign _zz_245 = (_zz_246 >>> 1); + assign _zz_246 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_247 = execute_INSTRUCTION[31 : 20]; + assign _zz_248 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_249 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_250 = {_zz_117,execute_INSTRUCTION[31 : 20]}; + assign _zz_251 = {{_zz_119,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_252 = {{_zz_121,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_253 = execute_INSTRUCTION[31 : 20]; + assign _zz_254 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_255 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_256 = 3'b100; + assign _zz_257 = (_zz_132 & (~ _zz_258)); + assign _zz_258 = (_zz_132 - 2'b01); + assign _zz_259 = (_zz_134 & (~ _zz_260)); + assign _zz_260 = (_zz_134 - 2'b01); + assign _zz_261 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_262 = {5'd0, _zz_261}; + assign _zz_263 = (_zz_265 + _zz_267); + assign _zz_264 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_265 = {{1{_zz_264[32]}}, _zz_264}; + assign _zz_266 = _zz_268; + assign _zz_267 = {{1{_zz_266[32]}}, _zz_266}; + assign _zz_268 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_269 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_270 = {5'd0, _zz_269}; + assign _zz_271 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_272 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_273 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_274 = {_zz_136,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_275 = _zz_276; + assign _zz_276 = _zz_277; + assign _zz_277 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_137) : _zz_137)} + _zz_279); + assign _zz_278 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_279 = {32'd0, _zz_278}; + assign _zz_280 = _zz_139; + assign _zz_281 = {32'd0, _zz_280}; + assign _zz_282 = _zz_138; + assign _zz_283 = {31'd0, _zz_282}; + assign _zz_284 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_285 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_286 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_287 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_288 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_289 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_290 = (iBus_cmd_payload_address >>> 5); + assign _zz_291 = 1'b1; + assign _zz_292 = 1'b1; + assign _zz_293 = {_zz_55,_zz_54}; + assign _zz_294 = 32'h0000107f; + assign _zz_295 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_296 = 32'h00002073; + assign _zz_297 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_298 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_299 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_300) == 32'h00000003),{(_zz_301 == _zz_302),{_zz_303,{_zz_304,_zz_305}}}}}}; + assign _zz_300 = 32'h0000505f; + assign _zz_301 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_302 = 32'h00000063; + assign _zz_303 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_304 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_305 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_306) == 32'h00005033),{(_zz_307 == _zz_308),{_zz_309,{_zz_310,_zz_311}}}}}}; + assign _zz_306 = 32'hbe00707f; + assign _zz_307 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_308 = 32'h00000033; + assign _zz_309 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_310 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_311 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_312 = decode_INSTRUCTION[31]; + assign _zz_313 = decode_INSTRUCTION[31]; + assign _zz_314 = decode_INSTRUCTION[7]; + assign _zz_315 = 32'h02004064; + assign _zz_316 = _zz_90; + assign _zz_317 = {_zz_88,_zz_89}; + assign _zz_318 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_319 = 1'b0; + assign _zz_320 = (((decode_INSTRUCTION & _zz_323) == 32'h00000050) != 1'b0); + assign _zz_321 = ((_zz_324 == _zz_325) != 1'b0); + assign _zz_322 = {({_zz_326,_zz_327} != 2'b00),{(_zz_328 != _zz_329),{_zz_330,{_zz_331,_zz_332}}}}; + assign _zz_323 = 32'h10003050; + assign _zz_324 = (decode_INSTRUCTION & 32'h10403050); + assign _zz_325 = 32'h10000050; + assign _zz_326 = ((decode_INSTRUCTION & _zz_333) == 32'h00001050); + assign _zz_327 = ((decode_INSTRUCTION & _zz_334) == 32'h00002050); + assign _zz_328 = {_zz_87,(_zz_335 == _zz_336)}; + assign _zz_329 = 2'b00; + assign _zz_330 = ((_zz_337 == _zz_338) != 1'b0); + assign _zz_331 = ({_zz_339,_zz_340} != 2'b00); + assign _zz_332 = {(_zz_341 != _zz_342),{_zz_343,{_zz_344,_zz_345}}}; + assign _zz_333 = 32'h00001050; + assign _zz_334 = 32'h00002050; + assign _zz_335 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_336 = 32'h00000004; + assign _zz_337 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_338 = 32'h00000040; + assign _zz_339 = ((decode_INSTRUCTION & _zz_346) == 32'h00005010); + assign _zz_340 = ((decode_INSTRUCTION & _zz_347) == 32'h00005020); + assign _zz_341 = {(_zz_348 == _zz_349),{_zz_350,_zz_351}}; + assign _zz_342 = 3'b000; + assign _zz_343 = ({_zz_352,{_zz_353,_zz_354}} != 3'b000); + assign _zz_344 = (_zz_355 != 1'b0); + assign _zz_345 = {(_zz_356 != _zz_357),{_zz_358,{_zz_359,_zz_360}}}; + assign _zz_346 = 32'h00007034; + assign _zz_347 = 32'h02007064; + assign _zz_348 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_349 = 32'h40001010; + assign _zz_350 = ((decode_INSTRUCTION & _zz_361) == 32'h00001010); + assign _zz_351 = ((decode_INSTRUCTION & _zz_362) == 32'h00001010); + assign _zz_352 = ((decode_INSTRUCTION & _zz_363) == 32'h00000024); + assign _zz_353 = (_zz_364 == _zz_365); + assign _zz_354 = (_zz_366 == _zz_367); + assign _zz_355 = ((decode_INSTRUCTION & _zz_368) == 32'h00001000); + assign _zz_356 = _zz_88; + assign _zz_357 = 1'b0; + assign _zz_358 = ({_zz_369,_zz_370} != 2'b00); + assign _zz_359 = (_zz_371 != _zz_372); + assign _zz_360 = {_zz_373,{_zz_374,_zz_375}}; + assign _zz_361 = 32'h00007034; + assign _zz_362 = 32'h02007054; + assign _zz_363 = 32'h00000064; + assign _zz_364 = (decode_INSTRUCTION & 32'h00003034); + assign _zz_365 = 32'h00001010; + assign _zz_366 = (decode_INSTRUCTION & 32'h02003054); + assign _zz_367 = 32'h00001010; + assign _zz_368 = 32'h00001000; + assign _zz_369 = ((decode_INSTRUCTION & _zz_376) == 32'h00002000); + assign _zz_370 = ((decode_INSTRUCTION & _zz_377) == 32'h00001000); + assign _zz_371 = {(_zz_378 == _zz_379),(_zz_380 == _zz_381)}; + assign _zz_372 = 2'b00; + assign _zz_373 = ({_zz_382,{_zz_383,_zz_384}} != 3'b000); + assign _zz_374 = (_zz_385 != 1'b0); + assign _zz_375 = {(_zz_386 != _zz_387),{_zz_388,{_zz_389,_zz_390}}}; + assign _zz_376 = 32'h00002010; + assign _zz_377 = 32'h00005000; + assign _zz_378 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_379 = 32'h00000020; + assign _zz_380 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_381 = 32'h00000020; + assign _zz_382 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_383 = ((decode_INSTRUCTION & _zz_391) == 32'h0); + assign _zz_384 = ((decode_INSTRUCTION & _zz_392) == 32'h00000040); + assign _zz_385 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_386 = ((decode_INSTRUCTION & _zz_393) == 32'h00000010); + assign _zz_387 = 1'b0; + assign _zz_388 = ({_zz_86,{_zz_394,_zz_395}} != 3'b000); + assign _zz_389 = ({_zz_396,_zz_397} != 6'h0); + assign _zz_390 = {(_zz_398 != _zz_399),{_zz_400,{_zz_401,_zz_402}}}; + assign _zz_391 = 32'h00000038; + assign _zz_392 = 32'h00403040; + assign _zz_393 = 32'h00000010; + assign _zz_394 = ((decode_INSTRUCTION & _zz_403) == 32'h00000010); + assign _zz_395 = ((decode_INSTRUCTION & _zz_404) == 32'h00000020); + assign _zz_396 = _zz_87; + assign _zz_397 = {(_zz_405 == _zz_406),{_zz_407,{_zz_408,_zz_409}}}; + assign _zz_398 = {_zz_86,(_zz_410 == _zz_411)}; + assign _zz_399 = 2'b00; + assign _zz_400 = ({_zz_86,_zz_412} != 2'b00); + assign _zz_401 = ({_zz_413,_zz_414} != 2'b00); + assign _zz_402 = {(_zz_415 != _zz_416),{_zz_417,{_zz_418,_zz_419}}}; + assign _zz_403 = 32'h00000030; + assign _zz_404 = 32'h02000060; + assign _zz_405 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_406 = 32'h00001010; + assign _zz_407 = ((decode_INSTRUCTION & _zz_420) == 32'h00002010); + assign _zz_408 = (_zz_421 == _zz_422); + assign _zz_409 = {_zz_423,_zz_424}; + assign _zz_410 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_411 = 32'h00000020; + assign _zz_412 = ((decode_INSTRUCTION & _zz_425) == 32'h0); + assign _zz_413 = (_zz_426 == _zz_427); + assign _zz_414 = (_zz_428 == _zz_429); + assign _zz_415 = (_zz_430 == _zz_431); + assign _zz_416 = 1'b0; + assign _zz_417 = ({_zz_432,_zz_433} != 4'b0000); + assign _zz_418 = (_zz_434 != _zz_435); + assign _zz_419 = {_zz_436,{_zz_437,_zz_438}}; + assign _zz_420 = 32'h00002010; + assign _zz_421 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_422 = 32'h00000010; + assign _zz_423 = ((decode_INSTRUCTION & _zz_439) == 32'h00000004); + assign _zz_424 = ((decode_INSTRUCTION & _zz_440) == 32'h0); + assign _zz_425 = 32'h00000020; + assign _zz_426 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_427 = 32'h00006010; + assign _zz_428 = (decode_INSTRUCTION & 32'h00005014); + assign _zz_429 = 32'h00004010; + assign _zz_430 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_431 = 32'h00002010; + assign _zz_432 = (_zz_441 == _zz_442); + assign _zz_433 = {_zz_443,{_zz_444,_zz_445}}; + assign _zz_434 = (_zz_446 == _zz_447); + assign _zz_435 = 1'b0; + assign _zz_436 = ({_zz_448,_zz_449} != 3'b000); + assign _zz_437 = (_zz_450 != _zz_451); + assign _zz_438 = {_zz_452,_zz_453}; + assign _zz_439 = 32'h0000000c; + assign _zz_440 = 32'h00000028; + assign _zz_441 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_442 = 32'h0; + assign _zz_443 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz_444 = ((decode_INSTRUCTION & _zz_454) == 32'h00002000); + assign _zz_445 = ((decode_INSTRUCTION & _zz_455) == 32'h00001000); + assign _zz_446 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_447 = 32'h0; + assign _zz_448 = ((decode_INSTRUCTION & _zz_456) == 32'h00000040); + assign _zz_449 = {(_zz_457 == _zz_458),(_zz_459 == _zz_460)}; + assign _zz_450 = {(_zz_461 == _zz_462),_zz_85}; + assign _zz_451 = 2'b00; + assign _zz_452 = ({_zz_463,_zz_85} != 2'b00); + assign _zz_453 = ((_zz_464 == _zz_465) != 1'b0); + assign _zz_454 = 32'h00006004; + assign _zz_455 = 32'h00005004; + assign _zz_456 = 32'h00000044; + assign _zz_457 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_458 = 32'h00002010; + assign _zz_459 = (decode_INSTRUCTION & 32'h40004034); + assign _zz_460 = 32'h40000030; + assign _zz_461 = (decode_INSTRUCTION & 32'h00000014); + assign _zz_462 = 32'h00000004; + assign _zz_463 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_464 = (decode_INSTRUCTION & 32'h00001048); + assign _zz_465 = 32'h00001008; + assign _zz_466 = execute_INSTRUCTION[31]; + assign _zz_467 = execute_INSTRUCTION[31]; + assign _zz_468 = execute_INSTRUCTION[7]; always @ (posedge clk) begin - if(_zz_52_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + if(_zz_291) begin + _zz_163 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_343_) begin - _zz_214_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_292) begin + _zz_164 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_344_) begin - _zz_215_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_205_), - .io_cpu_prefetch_isValid(_zz_206_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_207_), - .io_cpu_fetch_isStuck(_zz_208_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_209_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_210_), - .io_cpu_decode_isStuck(_zz_211_), - .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), - .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), - .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), - .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), - .io_cpu_decode_isUser(_zz_212_), - .io_cpu_fill_valid(_zz_213_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - .clk(clk), - .reset(reset) + if(_zz_39) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_154 ), //i + .io_cpu_prefetch_isValid (_zz_155 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_156 ), //i + .io_cpu_fetch_isStuck (_zz_157 ), //i + .io_cpu_fetch_isRemoved (_zz_158 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_159 ), //i + .io_cpu_decode_isStuck (_zz_160 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_161 ), //i + .io_cpu_fill_valid (_zz_162 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_345_) - 3'b000 : begin - _zz_216_ = CsrPlugin_jumpInterface_payload; - end - 3'b001 : begin - _zz_216_ = DBusSimplePlugin_redoBranch_payload; + case(_zz_293) + 2'b00 : begin + _zz_165 = CsrPlugin_jumpInterface_payload; end - 3'b010 : begin - _zz_216_ = BranchPlugin_jumpInterface_payload; + 2'b01 : begin + _zz_165 = DBusSimplePlugin_redoBranch_payload; end - 3'b011 : begin - _zz_216_ = IBusCachedPlugin_redoBranch_payload; + 2'b10 : begin + _zz_165 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_216_ = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_165 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end `ifndef SYNTHESIS always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; endcase end always @(*) begin - case(_zz_1_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_1__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_1__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_1__string = "URS1 "; - default : _zz_1__string = "????????????"; + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; endcase end always @(*) begin - case(_zz_2_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_2__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_2__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_2__string = "URS1 "; - default : _zz_2__string = "????????????"; + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; endcase end always @(*) begin - case(_zz_3_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_3__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_3__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_3__string = "URS1 "; - default : _zz_3__string = "????????????"; + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_4__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_4__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_4__string = "AND_1"; - default : _zz_4__string = "?????"; + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; endcase end always @(*) begin - case(_zz_5_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_5__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_5__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_5__string = "AND_1"; - default : _zz_5__string = "?????"; + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; endcase end always @(*) begin - case(_zz_6_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_6__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_6__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_6__string = "AND_1"; - default : _zz_6__string = "?????"; + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; endcase end always @(*) begin - case(_zz_7_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL"; - default : _zz_7__string = "?????"; + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; endcase end always @(*) begin - case(_zz_8_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8__string = "ECALL"; - default : _zz_8__string = "?????"; + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; endcase end always @(*) begin - case(_zz_9_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9__string = "ECALL"; - default : _zz_9__string = "?????"; + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_10_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL"; - default : _zz_10__string = "?????"; + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; endcase end always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; endcase end always @(*) begin - case(_zz_11_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_11__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_11__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_11__string = "ECALL"; - default : _zz_11__string = "?????"; + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; endcase end always @(*) begin - case(_zz_12_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_12__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_12__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_12__string = "ECALL"; - default : _zz_12__string = "?????"; + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_13_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_13__string = "ECALL"; - default : _zz_13__string = "?????"; + case(_zz_13) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_13_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_13_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_13_string = "AND_1"; + default : _zz_13_string = "?????"; endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(_zz_14) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; + default : _zz_14_string = "?????"; endcase end always @(*) begin - case(_zz_14_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_14__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_14__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_14__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_14__string = "PC "; - default : _zz_14__string = "???"; + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; endcase end always @(*) begin - case(_zz_15_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_15__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_15__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_15__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_15__string = "PC "; - default : _zz_15__string = "???"; + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_16_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_16__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_16__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_16__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_16__string = "PC "; - default : _zz_16__string = "???"; + case(_zz_16) + `Src2CtrlEnum_defaultEncoding_RS : _zz_16_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_16_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_16_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_16_string = "PC "; + default : _zz_16_string = "???"; endcase end always @(*) begin - case(_zz_17_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_17__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_17__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_17__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_17__string = "JALR"; - default : _zz_17__string = "????"; + case(_zz_17) + `Src2CtrlEnum_defaultEncoding_RS : _zz_17_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_17_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_17_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_17_string = "PC "; + default : _zz_17_string = "???"; endcase end always @(*) begin - case(_zz_18_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_18__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_18__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_18__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_18__string = "JALR"; - default : _zz_18__string = "????"; + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; endcase end always @(*) begin @@ -2013,63 +1729,63 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_19_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE "; - default : _zz_19__string = "????????"; + case(_zz_19) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19_string = "BITWISE "; + default : _zz_19_string = "????????"; endcase end always @(*) begin - case(_zz_20_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20__string = "BITWISE "; - default : _zz_20__string = "????????"; + case(_zz_20) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; + default : _zz_20_string = "????????"; endcase end always @(*) begin - case(_zz_21_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21__string = "BITWISE "; - default : _zz_21__string = "????????"; + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_22_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; - default : _zz_22__string = "?????????"; + case(_zz_22) + `Src1CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_22_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_22_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_22_string = "URS1 "; + default : _zz_22_string = "????????????"; endcase end always @(*) begin - case(_zz_23_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_23__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_23__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_23__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_23__string = "SRA_1 "; - default : _zz_23__string = "?????????"; + case(_zz_23) + `Src1CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_23_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_23_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_23_string = "URS1 "; + default : _zz_23_string = "????????????"; endcase end always @(*) begin - case(_zz_24_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_24__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_24__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_24__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_24__string = "SRA_1 "; - default : _zz_24__string = "?????????"; + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; endcase end always @(*) begin @@ -2081,11 +1797,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_25_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_25__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_25__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25__string = "ECALL"; - default : _zz_25__string = "?????"; + case(_zz_25) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_25_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_25_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25_string = "ECALL"; + default : _zz_25_string = "?????"; endcase end always @(*) begin @@ -2097,11 +1813,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_26_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL"; - default : _zz_26__string = "?????"; + case(_zz_26) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_26_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_26_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26_string = "ECALL"; + default : _zz_26_string = "?????"; endcase end always @(*) begin @@ -2113,11 +1829,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_29_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29__string = "ECALL"; - default : _zz_29__string = "?????"; + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; endcase end always @(*) begin @@ -2130,12 +1846,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_32_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR"; - default : _zz_32__string = "????"; + case(_zz_28) + `BranchCtrlEnum_defaultEncoding_INC : _zz_28_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_28_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_28_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_28_string = "JALR"; + default : _zz_28_string = "????"; endcase end always @(*) begin @@ -2148,12 +1864,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_37_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_37__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_37__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_37__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_37__string = "SRA_1 "; - default : _zz_37__string = "?????????"; + case(_zz_31) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_31_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_31_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_31_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_31_string = "SRA_1 "; + default : _zz_31_string = "?????????"; endcase end always @(*) begin @@ -2166,12 +1882,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_42_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_42__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_42__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_42__string = "PC "; - default : _zz_42__string = "???"; + case(_zz_33) + `Src2CtrlEnum_defaultEncoding_RS : _zz_33_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_33_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_33_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_33_string = "PC "; + default : _zz_33_string = "???"; endcase end always @(*) begin @@ -2184,12 +1900,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_44_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_44__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_44__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_44__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_44__string = "URS1 "; - default : _zz_44__string = "????????????"; + case(_zz_34) + `Src1CtrlEnum_defaultEncoding_RS : _zz_34_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_34_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34_string = "URS1 "; + default : _zz_34_string = "????????????"; endcase end always @(*) begin @@ -2201,11 +1917,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_47_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_47__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_47__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_47__string = "BITWISE "; - default : _zz_47__string = "????????"; + case(_zz_35) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_35_string = "BITWISE "; + default : _zz_35_string = "????????"; endcase end always @(*) begin @@ -2217,71 +1933,71 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_49_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_49__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_49__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_49__string = "AND_1"; - default : _zz_49__string = "?????"; + case(_zz_36) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_36_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_36_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_36_string = "AND_1"; + default : _zz_36_string = "?????"; endcase end always @(*) begin - case(_zz_56_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_56__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_56__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_56__string = "BITWISE "; - default : _zz_56__string = "????????"; + case(_zz_40) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_40_string = "ECALL"; + default : _zz_40_string = "?????"; endcase end always @(*) begin - case(_zz_57_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_57__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_57__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_57__string = "AND_1"; - default : _zz_57__string = "?????"; + case(_zz_41) + `BranchCtrlEnum_defaultEncoding_INC : _zz_41_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_41_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_41_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_41_string = "JALR"; + default : _zz_41_string = "????"; endcase end always @(*) begin - case(_zz_58_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_58__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_58__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_58__string = "ECALL"; - default : _zz_58__string = "?????"; + case(_zz_42) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_42_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_42_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_42_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_42_string = "SRA_1 "; + default : _zz_42_string = "?????????"; endcase end always @(*) begin - case(_zz_61_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_61__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_61__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_61__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_61__string = "JALR"; - default : _zz_61__string = "????"; + case(_zz_43) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_66_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_66__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_66__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_66__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_66__string = "URS1 "; - default : _zz_66__string = "????????????"; + case(_zz_44) + `Src2CtrlEnum_defaultEncoding_RS : _zz_44_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_44_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_44_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_44_string = "PC "; + default : _zz_44_string = "???"; endcase end always @(*) begin - case(_zz_75_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_75__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_75__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_75__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_75__string = "SRA_1 "; - default : _zz_75__string = "?????????"; + case(_zz_45) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; + default : _zz_45_string = "????????"; endcase end always @(*) begin - case(_zz_76_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_76__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_76__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_76__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_76__string = "PC "; - default : _zz_76__string = "???"; + case(_zz_46) + `Src1CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_46_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_46_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_46_string = "URS1 "; + default : _zz_46_string = "????????????"; endcase end always @(*) begin @@ -2294,81 +2010,81 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_95_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_95__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_95__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_95__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_95__string = "JALR"; - default : _zz_95__string = "????"; + case(_zz_48) + `BranchCtrlEnum_defaultEncoding_INC : _zz_48_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_48_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_48_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_48_string = "JALR"; + default : _zz_48_string = "????"; endcase end always @(*) begin - case(_zz_142_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_142__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_142__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_142__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_142__string = "PC "; - default : _zz_142__string = "???"; + case(_zz_91) + `Src1CtrlEnum_defaultEncoding_RS : _zz_91_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_91_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_91_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_91_string = "URS1 "; + default : _zz_91_string = "????????????"; endcase end always @(*) begin - case(_zz_143_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_143__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_143__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_143__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_143__string = "SRA_1 "; - default : _zz_143__string = "?????????"; + case(_zz_92) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_92_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_92_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_92_string = "BITWISE "; + default : _zz_92_string = "????????"; endcase end always @(*) begin - case(_zz_144_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_144__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_144__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_144__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_144__string = "URS1 "; - default : _zz_144__string = "????????????"; + case(_zz_93) + `Src2CtrlEnum_defaultEncoding_RS : _zz_93_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_93_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_93_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_93_string = "PC "; + default : _zz_93_string = "???"; endcase end always @(*) begin - case(_zz_145_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_145__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_145__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_145__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_145__string = "JALR"; - default : _zz_145__string = "????"; + case(_zz_94) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_94_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_94_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_94_string = "AND_1"; + default : _zz_94_string = "?????"; endcase end always @(*) begin - case(_zz_146_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_146__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_146__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_146__string = "ECALL"; - default : _zz_146__string = "?????"; + case(_zz_95) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_95_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_95_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_95_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_95_string = "SRA_1 "; + default : _zz_95_string = "?????????"; endcase end always @(*) begin - case(_zz_147_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_147__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_147__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_147__string = "AND_1"; - default : _zz_147__string = "?????"; + case(_zz_96) + `BranchCtrlEnum_defaultEncoding_INC : _zz_96_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_96_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_96_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_96_string = "JALR"; + default : _zz_96_string = "????"; endcase end always @(*) begin - case(_zz_148_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_148__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_148__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_148__string = "BITWISE "; - default : _zz_148__string = "????????"; + case(_zz_97) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_97_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_97_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_97_string = "ECALL"; + default : _zz_97_string = "?????"; endcase end always @(*) begin - case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; - default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin @@ -2379,15 +2095,6 @@ module VexRiscv ( default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end - always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; - endcase - end always @(*) begin case(decode_to_execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; @@ -2397,6 +2104,32 @@ module VexRiscv ( default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end always @(*) begin case(decode_to_execute_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; @@ -2421,65 +2154,48 @@ module VexRiscv ( default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end `endif - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_34_; - assign decode_CSR_WRITE_OPCODE = _zz_28_; + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_99; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_89_; - assign decode_SRC_LESS_UNSIGNED = _zz_73_; - assign decode_SRC1_CTRL = _zz_1_; - assign _zz_2_ = _zz_3_; - assign decode_ALU_BITWISE_CTRL = _zz_4_; - assign _zz_5_ = _zz_6_; - assign decode_IS_RS1_SIGNED = _zz_77_; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_DIV = _zz_205[0]; + assign decode_IS_RS2_SIGNED = _zz_206[0]; + assign decode_IS_RS1_SIGNED = _zz_207[0]; + assign decode_IS_MUL = _zz_208[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_209[0]; + assign _zz_8 = _zz_9; + assign decode_SHIFT_CTRL = _zz_10; + assign _zz_11 = _zz_12; + assign decode_ALU_BITWISE_CTRL = _zz_13; + assign _zz_14 = _zz_15; + assign decode_SRC_LESS_UNSIGNED = _zz_210[0]; + assign decode_MEMORY_STORE = _zz_211[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_212[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_213[0]; + assign decode_SRC2_CTRL = _zz_16; + assign _zz_17 = _zz_18; + assign decode_ALU_CTRL = _zz_19; + assign _zz_20 = _zz_21; + assign decode_SRC1_CTRL = _zz_22; + assign _zz_23 = _zz_24; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_98_; - assign decode_IS_MUL = _zz_60_; - assign execute_BRANCH_DO = _zz_31_; - assign decode_IS_CSR = _zz_65_; - assign _zz_7_ = _zz_8_; - assign _zz_9_ = _zz_10_; - assign decode_ENV_CTRL = _zz_11_; - assign _zz_12_ = _zz_13_; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_67_; - assign decode_IS_DIV = _zz_63_; - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_48_; - assign decode_SRC2_CTRL = _zz_14_; - assign _zz_15_ = _zz_16_; - assign _zz_17_ = _zz_18_; - assign decode_SRC2_FORCE_ZERO = _zz_46_; - assign execute_BRANCH_CALC = _zz_30_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_62_; - assign memory_MEMORY_READ_DATA = _zz_80_; - assign decode_IS_RS2_SIGNED = _zz_74_; - assign decode_MEMORY_STORE = _zz_70_; - assign decode_ALU_CTRL = _zz_19_; - assign _zz_20_ = _zz_21_; - assign decode_CSR_READ_OPCODE = _zz_27_; - assign decode_SHIFT_CTRL = _zz_22_; - assign _zz_23_ = _zz_24_; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_MUL = decode_to_execute_IS_MUL; @@ -2489,27 +2205,27 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_25_; - assign execute_ENV_CTRL = _zz_26_; - assign writeBack_ENV_CTRL = _zz_29_; + assign memory_ENV_CTRL = _zz_25; + assign execute_ENV_CTRL = _zz_26; + assign writeBack_ENV_CTRL = _zz_27; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_33_; - assign execute_BRANCH_CTRL = _zz_32_; - assign decode_RS2_USE = _zz_68_; - assign decode_RS1_USE = _zz_64_; + assign execute_BRANCH_COND_RESULT = _zz_115; + assign execute_BRANCH_CTRL = _zz_28; + assign decode_RS2_USE = _zz_214[0]; + assign decode_RS1_USE = _zz_215[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; always @ (*) begin - _zz_35_ = memory_REGFILE_WRITE_DATA; - if(_zz_217_)begin - _zz_35_ = ((memory_INSTRUCTION[13 : 12] == (2'b00)) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + _zz_29 = memory_REGFILE_WRITE_DATA; + if(_zz_166)begin + _zz_29 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_218_)begin - _zz_35_ = memory_MulDivIterativePlugin_div_result; + if(_zz_167)begin + _zz_29 = memory_MulDivIterativePlugin_div_result; end end @@ -2518,114 +2234,113 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - decode_RS2 = _zz_53_; - if(_zz_161_)begin - if((_zz_162_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_163_; + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_219_)begin - if(_zz_220_)begin - if(_zz_165_)begin - decode_RS2 = _zz_79_; + if(_zz_168)begin + if(_zz_169)begin + if(_zz_108)begin + decode_RS2 = _zz_47; end end end - if(_zz_221_)begin + if(_zz_170)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_167_)begin - decode_RS2 = _zz_35_; + if(_zz_110)begin + decode_RS2 = _zz_29; end end end - if(_zz_222_)begin + if(_zz_171)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_169_)begin - decode_RS2 = _zz_36_; + if(_zz_112)begin + decode_RS2 = _zz_30; end end end end always @ (*) begin - decode_RS1 = _zz_54_; - if(_zz_161_)begin - if((_zz_162_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_163_; + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_219_)begin - if(_zz_220_)begin - if(_zz_164_)begin - decode_RS1 = _zz_79_; + if(_zz_168)begin + if(_zz_169)begin + if(_zz_107)begin + decode_RS1 = _zz_47; end end end - if(_zz_221_)begin + if(_zz_170)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_166_)begin - decode_RS1 = _zz_35_; + if(_zz_109)begin + decode_RS1 = _zz_29; end end end - if(_zz_222_)begin + if(_zz_171)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_168_)begin - decode_RS1 = _zz_36_; + if(_zz_111)begin + decode_RS1 = _zz_30; end end end end always @ (*) begin - _zz_36_ = execute_REGFILE_WRITE_DATA; - if(_zz_223_)begin - _zz_36_ = _zz_157_; + _zz_30 = execute_REGFILE_WRITE_DATA; + if(_zz_172)begin + _zz_30 = _zz_106; end - if(_zz_224_)begin - _zz_36_ = execute_CsrPlugin_readData; + if(_zz_173)begin + _zz_30 = execute_CsrPlugin_readData; end end - assign execute_SHIFT_CTRL = _zz_37_; + assign execute_SHIFT_CTRL = _zz_31; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_41_ = execute_PC; - assign execute_SRC2_CTRL = _zz_42_; - assign execute_SRC1_CTRL = _zz_44_; - assign decode_SRC_USE_SUB_LESS = _zz_69_; - assign decode_SRC_ADD_ZERO = _zz_59_; - assign execute_SRC_ADD_SUB = _zz_40_; - assign execute_SRC_LESS = _zz_38_; - assign execute_ALU_CTRL = _zz_47_; - assign execute_SRC2 = _zz_43_; - assign execute_SRC1 = _zz_45_; - assign execute_ALU_BITWISE_CTRL = _zz_49_; - assign _zz_50_ = writeBack_INSTRUCTION; - assign _zz_51_ = writeBack_REGFILE_WRITE_VALID; + assign _zz_32 = execute_PC; + assign execute_SRC2_CTRL = _zz_33; + assign execute_SRC1_CTRL = _zz_34; + assign decode_SRC_USE_SUB_LESS = _zz_216[0]; + assign decode_SRC_ADD_ZERO = _zz_217[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_35; + assign execute_SRC2 = _zz_105; + assign execute_SRC1 = _zz_100; + assign execute_ALU_BITWISE_CTRL = _zz_36; + assign _zz_37 = writeBack_INSTRUCTION; + assign _zz_38 = writeBack_REGFILE_WRITE_VALID; always @ (*) begin - _zz_52_ = 1'b0; + _zz_39 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_52_ = 1'b1; + _zz_39 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_94_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_72_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_218[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_78_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_294) == 32'h00001073),{(_zz_295 == _zz_296),{_zz_297,{_zz_298,_zz_299}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin - _zz_79_ = writeBack_REGFILE_WRITE_DATA; + _zz_47 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_79_ = writeBack_DBusSimplePlugin_rspFormated; + _zz_47 = writeBack_DBusSimplePlugin_rspFormated; end end @@ -2633,85 +2348,86 @@ module VexRiscv ( assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress; - assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess; - assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead; - assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite; - assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute; - assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception; - assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling; + assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; + assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; + assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; + assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; + assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; + assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; + assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; + assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; + assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; assign memory_PC = execute_to_memory_PC; assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = _zz_88_; - assign execute_MMU_RSP_physicalAddress = _zz_81_; - assign execute_MMU_RSP_isIoAccess = _zz_82_; - assign execute_MMU_RSP_allowRead = _zz_83_; - assign execute_MMU_RSP_allowWrite = _zz_84_; - assign execute_MMU_RSP_allowExecute = _zz_85_; - assign execute_MMU_RSP_exception = _zz_86_; - assign execute_MMU_RSP_refilling = _zz_87_; - assign execute_SRC_ADD = _zz_39_; + assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); + assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; + assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; + assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; + assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; + assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; + assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; + assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; + assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_ALIGNEMENT_FAULT = _zz_90_; - assign decode_MEMORY_ENABLE = _zz_71_; - assign decode_FLUSH_ALL = _zz_55_; + assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); + assign decode_MEMORY_ENABLE = _zz_219[0]; + assign decode_FLUSH_ALL = _zz_220[0]; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_91_; - if(_zz_225_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_174)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin - _zz_91_ = _zz_92_; - if(_zz_226_)begin - _zz_91_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_175)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin - _zz_92_ = _zz_93_; - if(_zz_227_)begin - _zz_92_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_176)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_93_ = 1'b0; - if(_zz_228_)begin - _zz_93_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_177)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_95_; - assign decode_INSTRUCTION = _zz_99_; + assign decode_BRANCH_CTRL = _zz_48; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_96_ = memory_FORMAL_PC_NEXT; + _zz_49 = memory_FORMAL_PC_NEXT; if(DBusSimplePlugin_redoBranch_valid)begin - _zz_96_ = DBusSimplePlugin_redoBranch_payload; + _zz_49 = DBusSimplePlugin_redoBranch_payload; end if(BranchPlugin_jumpInterface_valid)begin - _zz_96_ = BranchPlugin_jumpInterface_payload; + _zz_49 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_97_ = decode_FORMAL_PC_NEXT; + _zz_50 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_97_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_97_ = IBusCachedPlugin_redoBranch_payload; + _zz_50 = IBusCachedPlugin_predictionJumpInterface_payload; end end - assign decode_PC = _zz_100_; + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -2723,20 +2439,20 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_158_ || _zz_159_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_229_)begin + if(_zz_178)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2747,27 +2463,25 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_229_)begin + if(_zz_178)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_128_)))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_77)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_223_)begin - if(_zz_230_)begin - if(! execute_LightShifterPlugin_done) begin - execute_arbitration_haltItself = 1'b1; - end + if(_zz_172)begin + if((! execute_LightShifterPlugin_done))begin + execute_arbitration_haltItself = 1'b1; end end - if(_zz_224_)begin + if(_zz_173)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2798,13 +2512,16 @@ module VexRiscv ( if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_217_)begin - if(_zz_231_)begin + if(_zz_166)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_179)begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_218_)begin - if(_zz_232_)begin + if(_zz_167)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end end @@ -2813,7 +2530,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_233_)begin + if(_zz_180)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2836,7 +2553,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_233_)begin + if(_zz_180)begin memory_arbitration_flushNext = 1'b1; end end @@ -2853,10 +2570,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_234_)begin + if(_zz_181)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_235_)begin + if(_zz_182)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2867,51 +2584,43 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_234_)begin + if(_zz_181)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_235_)begin + if(_zz_182)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - end - always @ (*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin IBusCachedPlugin_incomingInstruction = 1'b1; end end + assign CsrPlugin_inWfi = 1'b0; + assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_234_)begin + if(_zz_181)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_235_)begin + if(_zz_182)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_234_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_181)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_235_)begin - case(_zz_236_) + if(_zz_182)begin + case(_zz_183) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2924,21 +2633,25 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); - assign _zz_101_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}}; - assign _zz_102_ = (_zz_101_ & (~ _zz_256_)); - assign _zz_103_ = _zz_102_[3]; - assign _zz_104_ = _zz_102_[4]; - assign _zz_105_ = (_zz_102_[1] || _zz_103_); - assign _zz_106_ = (_zz_102_[2] || _zz_103_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_216_; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_51 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; + assign _zz_52 = (_zz_51 & (~ _zz_221)); + assign _zz_53 = _zz_52[3]; + assign _zz_54 = (_zz_52[1] || _zz_53); + assign _zz_55 = (_zz_52[2] || _zz_53); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_165; always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin @@ -2947,7 +2660,10 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_258_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_223); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end @@ -2955,12 +2671,28 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin @@ -2968,41 +2700,44 @@ module VexRiscv ( end end - assign _zz_107_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_107_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_107_); + assign _zz_56 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_56); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_56); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + if(IBusCachedPlugin_mmuBus_busy)begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_108_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_108_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_108_); + assign _zz_57 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_57); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_57); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; - end - end - - assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_109_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_109_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_110_; - assign _zz_110_ = ((1'b0 && (! _zz_111_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_111_ = _zz_112_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_111_; + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_58 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_58); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_58); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_59; + assign _zz_59 = ((1'b0 && (! _zz_60)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_60 = _zz_61; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_60; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_113_ = _zz_114_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_113_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_115_; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_62)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_62 = _zz_63; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_62; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_64; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -3014,130 +2749,127 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); - assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - assign _zz_100_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - assign _zz_99_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - assign _zz_98_ = (decode_PC + (32'b00000000000000000000000000000100)); - assign _zz_116_ = _zz_259_[11]; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign _zz_65 = _zz_224[11]; always @ (*) begin - _zz_117_[18] = _zz_116_; - _zz_117_[17] = _zz_116_; - _zz_117_[16] = _zz_116_; - _zz_117_[15] = _zz_116_; - _zz_117_[14] = _zz_116_; - _zz_117_[13] = _zz_116_; - _zz_117_[12] = _zz_116_; - _zz_117_[11] = _zz_116_; - _zz_117_[10] = _zz_116_; - _zz_117_[9] = _zz_116_; - _zz_117_[8] = _zz_116_; - _zz_117_[7] = _zz_116_; - _zz_117_[6] = _zz_116_; - _zz_117_[5] = _zz_116_; - _zz_117_[4] = _zz_116_; - _zz_117_[3] = _zz_116_; - _zz_117_[2] = _zz_116_; - _zz_117_[1] = _zz_116_; - _zz_117_[0] = _zz_116_; + _zz_66[18] = _zz_65; + _zz_66[17] = _zz_65; + _zz_66[16] = _zz_65; + _zz_66[15] = _zz_65; + _zz_66[14] = _zz_65; + _zz_66[13] = _zz_65; + _zz_66[12] = _zz_65; + _zz_66[11] = _zz_65; + _zz_66[10] = _zz_65; + _zz_66[9] = _zz_65; + _zz_66[8] = _zz_65; + _zz_66[7] = _zz_65; + _zz_66[6] = _zz_65; + _zz_66[5] = _zz_65; + _zz_66[4] = _zz_65; + _zz_66[3] = _zz_65; + _zz_66[2] = _zz_65; + _zz_66[1] = _zz_65; + _zz_66[0] = _zz_65; end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_260_[31])); - if(_zz_122_)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_225[31])); + if(_zz_71)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_118_ = _zz_261_[19]; + assign _zz_67 = _zz_226[19]; always @ (*) begin - _zz_119_[10] = _zz_118_; - _zz_119_[9] = _zz_118_; - _zz_119_[8] = _zz_118_; - _zz_119_[7] = _zz_118_; - _zz_119_[6] = _zz_118_; - _zz_119_[5] = _zz_118_; - _zz_119_[4] = _zz_118_; - _zz_119_[3] = _zz_118_; - _zz_119_[2] = _zz_118_; - _zz_119_[1] = _zz_118_; - _zz_119_[0] = _zz_118_; - end - - assign _zz_120_ = _zz_262_[11]; + _zz_68[10] = _zz_67; + _zz_68[9] = _zz_67; + _zz_68[8] = _zz_67; + _zz_68[7] = _zz_67; + _zz_68[6] = _zz_67; + _zz_68[5] = _zz_67; + _zz_68[4] = _zz_67; + _zz_68[3] = _zz_67; + _zz_68[2] = _zz_67; + _zz_68[1] = _zz_67; + _zz_68[0] = _zz_67; + end + + assign _zz_69 = _zz_227[11]; always @ (*) begin - _zz_121_[18] = _zz_120_; - _zz_121_[17] = _zz_120_; - _zz_121_[16] = _zz_120_; - _zz_121_[15] = _zz_120_; - _zz_121_[14] = _zz_120_; - _zz_121_[13] = _zz_120_; - _zz_121_[12] = _zz_120_; - _zz_121_[11] = _zz_120_; - _zz_121_[10] = _zz_120_; - _zz_121_[9] = _zz_120_; - _zz_121_[8] = _zz_120_; - _zz_121_[7] = _zz_120_; - _zz_121_[6] = _zz_120_; - _zz_121_[5] = _zz_120_; - _zz_121_[4] = _zz_120_; - _zz_121_[3] = _zz_120_; - _zz_121_[2] = _zz_120_; - _zz_121_[1] = _zz_120_; - _zz_121_[0] = _zz_120_; + _zz_70[18] = _zz_69; + _zz_70[17] = _zz_69; + _zz_70[16] = _zz_69; + _zz_70[15] = _zz_69; + _zz_70[14] = _zz_69; + _zz_70[13] = _zz_69; + _zz_70[12] = _zz_69; + _zz_70[11] = _zz_69; + _zz_70[10] = _zz_69; + _zz_70[9] = _zz_69; + _zz_70[8] = _zz_69; + _zz_70[7] = _zz_69; + _zz_70[6] = _zz_69; + _zz_70[5] = _zz_69; + _zz_70[4] = _zz_69; + _zz_70[3] = _zz_69; + _zz_70[2] = _zz_69; + _zz_70[1] = _zz_69; + _zz_70[0] = _zz_69; end always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_122_ = _zz_263_[1]; + _zz_71 = _zz_228[1]; end default : begin - _zz_122_ = _zz_264_[1]; + _zz_71 = _zz_229[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_123_ = _zz_265_[19]; + assign _zz_72 = _zz_230[19]; always @ (*) begin - _zz_124_[10] = _zz_123_; - _zz_124_[9] = _zz_123_; - _zz_124_[8] = _zz_123_; - _zz_124_[7] = _zz_123_; - _zz_124_[6] = _zz_123_; - _zz_124_[5] = _zz_123_; - _zz_124_[4] = _zz_123_; - _zz_124_[3] = _zz_123_; - _zz_124_[2] = _zz_123_; - _zz_124_[1] = _zz_123_; - _zz_124_[0] = _zz_123_; - end - - assign _zz_125_ = _zz_266_[11]; + _zz_73[10] = _zz_72; + _zz_73[9] = _zz_72; + _zz_73[8] = _zz_72; + _zz_73[7] = _zz_72; + _zz_73[6] = _zz_72; + _zz_73[5] = _zz_72; + _zz_73[4] = _zz_72; + _zz_73[3] = _zz_72; + _zz_73[2] = _zz_72; + _zz_73[1] = _zz_72; + _zz_73[0] = _zz_72; + end + + assign _zz_74 = _zz_231[11]; always @ (*) begin - _zz_126_[18] = _zz_125_; - _zz_126_[17] = _zz_125_; - _zz_126_[16] = _zz_125_; - _zz_126_[15] = _zz_125_; - _zz_126_[14] = _zz_125_; - _zz_126_[13] = _zz_125_; - _zz_126_[12] = _zz_125_; - _zz_126_[11] = _zz_125_; - _zz_126_[10] = _zz_125_; - _zz_126_[9] = _zz_125_; - _zz_126_[8] = _zz_125_; - _zz_126_[7] = _zz_125_; - _zz_126_[6] = _zz_125_; - _zz_126_[5] = _zz_125_; - _zz_126_[4] = _zz_125_; - _zz_126_[3] = _zz_125_; - _zz_126_[2] = _zz_125_; - _zz_126_[1] = _zz_125_; - _zz_126_[0] = _zz_125_; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_124_,{{{_zz_346_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_126_,{{{_zz_347_,_zz_348_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + _zz_75[18] = _zz_74; + _zz_75[17] = _zz_74; + _zz_75[16] = _zz_74; + _zz_75[15] = _zz_74; + _zz_75[14] = _zz_74; + _zz_75[13] = _zz_74; + _zz_75[12] = _zz_74; + _zz_75[11] = _zz_74; + _zz_75[10] = _zz_74; + _zz_75[9] = _zz_74; + _zz_75[8] = _zz_74; + _zz_75[7] = _zz_74; + _zz_75[6] = _zz_74; + _zz_75[5] = _zz_74; + _zz_75[4] = _zz_74; + _zz_75[3] = _zz_74; + _zz_75[2] = _zz_74; + _zz_75[1] = _zz_74; + _zz_75[0] = _zz_74; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_73,{{{_zz_312,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_75,{{{_zz_313,_zz_314},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3146,161 +2878,143 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_206_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_209_ = (32'b00000000000000000000000000000000); - assign _zz_207_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_208_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_210_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_211_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_212_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_94_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign _zz_155 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_156 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_157 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_156; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_159 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_160 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_161 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_228_)begin + if(_zz_177)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_226_)begin + if(_zz_175)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_237_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - end end always @ (*) begin - _zz_213_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_226_)begin - _zz_213_ = 1'b1; - end - if(_zz_237_)begin - _zz_213_ = 1'b0; + _zz_162 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_175)begin + _zz_162 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_227_)begin + if(_zz_176)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_225_)begin + if(_zz_174)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_227_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); - end - if(_zz_225_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); - end - end - - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_205_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign _zz_128_ = 1'b0; - assign _zz_90_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_176)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_174)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_154 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_77 = 1'b0; always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin execute_DBusSimplePlugin_skipCmd = 1'b1; end - if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin + if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_128_)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_77)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_129_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_78 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_129_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_78 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_129_ = execute_RS2[31 : 0]; + _zz_78 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_129_; - assign _zz_89_ = dBus_cmd_payload_address[1 : 0]; + assign dBus_cmd_payload_data = _zz_78; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_130_ = (4'b0001); + _zz_79 = 4'b0001; end 2'b01 : begin - _zz_130_ = (4'b0011); + _zz_79 = 4'b0011; end default : begin - _zz_130_ = (4'b1111); + _zz_79 = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_130_ <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; + assign execute_DBusSimplePlugin_formalMask = (_zz_79 <<< dBus_cmd_payload_address[1 : 0]); + assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; + assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; + assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign _zz_88_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE))); - assign _zz_81_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign _zz_82_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign _zz_83_ = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign _zz_84_ = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign _zz_85_ = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign _zz_86_ = DBusSimplePlugin_mmuBus_rsp_exception; - assign _zz_87_ = DBusSimplePlugin_mmuBus_rsp_refilling; - assign _zz_80_ = dBus_rsp_data; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_238_)begin + if(_zz_184)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end if(memory_ALIGNEMENT_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_MMU_RSP_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end else begin if(memory_MMU_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_239_)begin + if(_zz_185)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); - if(_zz_238_)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101); + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; + if(_zz_184)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_267_}; + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_232}; end - if(! memory_MMU_RSP_refilling) begin + if(! memory_MMU_RSP2_refilling) begin if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101)); + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); end end end @@ -3308,10 +3022,10 @@ module VexRiscv ( assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; always @ (*) begin DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_239_)begin + if(_zz_185)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -3334,63 +3048,63 @@ module VexRiscv ( endcase end - assign _zz_131_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + assign _zz_80 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); always @ (*) begin - _zz_132_[31] = _zz_131_; - _zz_132_[30] = _zz_131_; - _zz_132_[29] = _zz_131_; - _zz_132_[28] = _zz_131_; - _zz_132_[27] = _zz_131_; - _zz_132_[26] = _zz_131_; - _zz_132_[25] = _zz_131_; - _zz_132_[24] = _zz_131_; - _zz_132_[23] = _zz_131_; - _zz_132_[22] = _zz_131_; - _zz_132_[21] = _zz_131_; - _zz_132_[20] = _zz_131_; - _zz_132_[19] = _zz_131_; - _zz_132_[18] = _zz_131_; - _zz_132_[17] = _zz_131_; - _zz_132_[16] = _zz_131_; - _zz_132_[15] = _zz_131_; - _zz_132_[14] = _zz_131_; - _zz_132_[13] = _zz_131_; - _zz_132_[12] = _zz_131_; - _zz_132_[11] = _zz_131_; - _zz_132_[10] = _zz_131_; - _zz_132_[9] = _zz_131_; - _zz_132_[8] = _zz_131_; - _zz_132_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_133_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + _zz_81[31] = _zz_80; + _zz_81[30] = _zz_80; + _zz_81[29] = _zz_80; + _zz_81[28] = _zz_80; + _zz_81[27] = _zz_80; + _zz_81[26] = _zz_80; + _zz_81[25] = _zz_80; + _zz_81[24] = _zz_80; + _zz_81[23] = _zz_80; + _zz_81[22] = _zz_80; + _zz_81[21] = _zz_80; + _zz_81[20] = _zz_80; + _zz_81[19] = _zz_80; + _zz_81[18] = _zz_80; + _zz_81[17] = _zz_80; + _zz_81[16] = _zz_80; + _zz_81[15] = _zz_80; + _zz_81[14] = _zz_80; + _zz_81[13] = _zz_80; + _zz_81[12] = _zz_80; + _zz_81[11] = _zz_80; + _zz_81[10] = _zz_80; + _zz_81[9] = _zz_80; + _zz_81[8] = _zz_80; + _zz_81[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_82 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); always @ (*) begin - _zz_134_[31] = _zz_133_; - _zz_134_[30] = _zz_133_; - _zz_134_[29] = _zz_133_; - _zz_134_[28] = _zz_133_; - _zz_134_[27] = _zz_133_; - _zz_134_[26] = _zz_133_; - _zz_134_[25] = _zz_133_; - _zz_134_[24] = _zz_133_; - _zz_134_[23] = _zz_133_; - _zz_134_[22] = _zz_133_; - _zz_134_[21] = _zz_133_; - _zz_134_[20] = _zz_133_; - _zz_134_[19] = _zz_133_; - _zz_134_[18] = _zz_133_; - _zz_134_[17] = _zz_133_; - _zz_134_[16] = _zz_133_; - _zz_134_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + _zz_83[31] = _zz_82; + _zz_83[30] = _zz_82; + _zz_83[29] = _zz_82; + _zz_83[28] = _zz_82; + _zz_83[27] = _zz_82; + _zz_83[26] = _zz_82; + _zz_83[25] = _zz_82; + _zz_83[24] = _zz_82; + _zz_83[23] = _zz_82; + _zz_83[22] = _zz_82; + _zz_83[21] = _zz_82; + _zz_83[20] = _zz_82; + _zz_83[19] = _zz_82; + _zz_83[18] = _zz_82; + _zz_83[17] = _zz_82; + _zz_83[16] = _zz_82; + _zz_83[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; end always @ (*) begin - case(_zz_254_) + case(_zz_203) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_132_; + writeBack_DBusSimplePlugin_rspFormated = _zz_81; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_134_; + writeBack_DBusSimplePlugin_rspFormated = _zz_83; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -3398,78 +3112,73 @@ module VexRiscv ( endcase end - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress; + assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_136_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_137_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); - assign _zz_138_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000100000000000000)); - assign _zz_139_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_140_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_141_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_135_ = {(((decode_INSTRUCTION & _zz_349_) == (32'b00000000000000000001000000001000)) != (1'b0)),{({_zz_350_,_zz_351_} != (2'b00)),{(_zz_352_ != (1'b0)),{(_zz_353_ != _zz_354_),{_zz_355_,{_zz_356_,_zz_357_}}}}}}; - assign _zz_78_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_488_) == (32'b00000000000000000001000001110011)),{(_zz_489_ == _zz_490_),{_zz_491_,{_zz_492_,_zz_493_}}}}}}} != (20'b00000000000000000000)); - assign _zz_77_ = _zz_268_[0]; - assign _zz_142_ = _zz_135_[2 : 1]; - assign _zz_76_ = _zz_142_; - assign _zz_143_ = _zz_135_[4 : 3]; - assign _zz_75_ = _zz_143_; - assign _zz_74_ = _zz_269_[0]; - assign _zz_73_ = _zz_270_[0]; - assign _zz_72_ = _zz_271_[0]; - assign _zz_71_ = _zz_272_[0]; - assign _zz_70_ = _zz_273_[0]; - assign _zz_69_ = _zz_274_[0]; - assign _zz_68_ = _zz_275_[0]; - assign _zz_67_ = _zz_276_[0]; - assign _zz_144_ = _zz_135_[15 : 14]; - assign _zz_66_ = _zz_144_; - assign _zz_65_ = _zz_277_[0]; - assign _zz_64_ = _zz_278_[0]; - assign _zz_63_ = _zz_279_[0]; - assign _zz_62_ = _zz_280_[0]; - assign _zz_145_ = _zz_135_[21 : 20]; - assign _zz_61_ = _zz_145_; - assign _zz_60_ = _zz_281_[0]; - assign _zz_59_ = _zz_282_[0]; - assign _zz_146_ = _zz_135_[25 : 24]; - assign _zz_58_ = _zz_146_; - assign _zz_147_ = _zz_135_[27 : 26]; - assign _zz_57_ = _zz_147_; - assign _zz_148_ = _zz_135_[29 : 28]; - assign _zz_56_ = _zz_148_; - assign _zz_55_ = _zz_283_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign _zz_85 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_86 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_87 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_88 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_89 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); + assign _zz_90 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); + assign _zz_84 = {(((decode_INSTRUCTION & _zz_315) == 32'h02004020) != 1'b0),{({_zz_90,_zz_89} != 2'b00),{({_zz_316,_zz_317} != 3'b000),{(_zz_318 != _zz_319),{_zz_320,{_zz_321,_zz_322}}}}}}; + assign _zz_91 = _zz_84[2 : 1]; + assign _zz_46 = _zz_91; + assign _zz_92 = _zz_84[7 : 6]; + assign _zz_45 = _zz_92; + assign _zz_93 = _zz_84[9 : 8]; + assign _zz_44 = _zz_93; + assign _zz_94 = _zz_84[18 : 17]; + assign _zz_43 = _zz_94; + assign _zz_95 = _zz_84[21 : 20]; + assign _zz_42 = _zz_95; + assign _zz_96 = _zz_84[23 : 22]; + assign _zz_41 = _zz_96; + assign _zz_97 = _zz_84[26 : 25]; + assign _zz_40 = _zz_97; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_214_; - assign decode_RegFilePlugin_rs2Data = _zz_215_; - assign _zz_54_ = decode_RegFilePlugin_rs1Data; - assign _zz_53_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_163; + assign decode_RegFilePlugin_rs2Data = _zz_164; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_51_ && writeBack_arbitration_isFiring); - if(_zz_149_)begin + lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); + if(_zz_98)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_50_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_79_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_37[11 : 7]; + if(_zz_98)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_47; + if(_zz_98)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -3487,303 +3196,297 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_150_ = execute_IntAluPlugin_bitwise; + _zz_99 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_150_ = {31'd0, _zz_284_}; + _zz_99 = {31'd0, _zz_233}; end default : begin - _zz_150_ = execute_SRC_ADD_SUB; + _zz_99 = execute_SRC_ADD_SUB; end endcase end - assign _zz_48_ = _zz_150_; - assign _zz_46_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_151_ = execute_RS1; + _zz_100 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_151_ = {29'd0, _zz_285_}; + _zz_100 = {29'd0, _zz_234}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_151_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_151_ = {27'd0, _zz_286_}; + _zz_100 = {27'd0, _zz_235}; end endcase end - assign _zz_45_ = _zz_151_; - assign _zz_152_ = _zz_287_[11]; + assign _zz_101 = _zz_236[11]; always @ (*) begin - _zz_153_[19] = _zz_152_; - _zz_153_[18] = _zz_152_; - _zz_153_[17] = _zz_152_; - _zz_153_[16] = _zz_152_; - _zz_153_[15] = _zz_152_; - _zz_153_[14] = _zz_152_; - _zz_153_[13] = _zz_152_; - _zz_153_[12] = _zz_152_; - _zz_153_[11] = _zz_152_; - _zz_153_[10] = _zz_152_; - _zz_153_[9] = _zz_152_; - _zz_153_[8] = _zz_152_; - _zz_153_[7] = _zz_152_; - _zz_153_[6] = _zz_152_; - _zz_153_[5] = _zz_152_; - _zz_153_[4] = _zz_152_; - _zz_153_[3] = _zz_152_; - _zz_153_[2] = _zz_152_; - _zz_153_[1] = _zz_152_; - _zz_153_[0] = _zz_152_; - end - - assign _zz_154_ = _zz_288_[11]; + _zz_102[19] = _zz_101; + _zz_102[18] = _zz_101; + _zz_102[17] = _zz_101; + _zz_102[16] = _zz_101; + _zz_102[15] = _zz_101; + _zz_102[14] = _zz_101; + _zz_102[13] = _zz_101; + _zz_102[12] = _zz_101; + _zz_102[11] = _zz_101; + _zz_102[10] = _zz_101; + _zz_102[9] = _zz_101; + _zz_102[8] = _zz_101; + _zz_102[7] = _zz_101; + _zz_102[6] = _zz_101; + _zz_102[5] = _zz_101; + _zz_102[4] = _zz_101; + _zz_102[3] = _zz_101; + _zz_102[2] = _zz_101; + _zz_102[1] = _zz_101; + _zz_102[0] = _zz_101; + end + + assign _zz_103 = _zz_237[11]; always @ (*) begin - _zz_155_[19] = _zz_154_; - _zz_155_[18] = _zz_154_; - _zz_155_[17] = _zz_154_; - _zz_155_[16] = _zz_154_; - _zz_155_[15] = _zz_154_; - _zz_155_[14] = _zz_154_; - _zz_155_[13] = _zz_154_; - _zz_155_[12] = _zz_154_; - _zz_155_[11] = _zz_154_; - _zz_155_[10] = _zz_154_; - _zz_155_[9] = _zz_154_; - _zz_155_[8] = _zz_154_; - _zz_155_[7] = _zz_154_; - _zz_155_[6] = _zz_154_; - _zz_155_[5] = _zz_154_; - _zz_155_[4] = _zz_154_; - _zz_155_[3] = _zz_154_; - _zz_155_[2] = _zz_154_; - _zz_155_[1] = _zz_154_; - _zz_155_[0] = _zz_154_; + _zz_104[19] = _zz_103; + _zz_104[18] = _zz_103; + _zz_104[17] = _zz_103; + _zz_104[16] = _zz_103; + _zz_104[15] = _zz_103; + _zz_104[14] = _zz_103; + _zz_104[13] = _zz_103; + _zz_104[12] = _zz_103; + _zz_104[11] = _zz_103; + _zz_104[10] = _zz_103; + _zz_104[9] = _zz_103; + _zz_104[8] = _zz_103; + _zz_104[7] = _zz_103; + _zz_104[6] = _zz_103; + _zz_104[5] = _zz_103; + _zz_104[4] = _zz_103; + _zz_104[3] = _zz_103; + _zz_104[2] = _zz_103; + _zz_104[1] = _zz_103; + _zz_104[0] = _zz_103; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_156_ = execute_RS2; + _zz_105 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_156_ = {_zz_153_,execute_INSTRUCTION[31 : 20]}; + _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_156_ = {_zz_155_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_105 = {_zz_104,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_156_ = _zz_41_; + _zz_105 = _zz_32; end endcase end - assign _zz_43_ = _zz_156_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_289_; + execute_SrcPlugin_addSub = _zz_238; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_40_ = execute_SrcPlugin_addSub; - assign _zz_39_ = execute_SrcPlugin_addSub; - assign _zz_38_ = execute_SrcPlugin_less; assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); - assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_157_ = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_106 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_157_ = _zz_296_; + _zz_106 = _zz_245; end endcase end always @ (*) begin - _zz_158_ = 1'b0; - if(_zz_240_)begin - if(_zz_241_)begin - if(_zz_164_)begin - _zz_158_ = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_186)begin + if(_zz_187)begin + if(_zz_107)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_242_)begin - if(_zz_243_)begin - if(_zz_166_)begin - _zz_158_ = 1'b1; + if(_zz_188)begin + if(_zz_189)begin + if(_zz_109)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_244_)begin - if(_zz_245_)begin - if(_zz_168_)begin - _zz_158_ = 1'b1; + if(_zz_190)begin + if(_zz_191)begin + if(_zz_111)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_158_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_159_ = 1'b0; - if(_zz_240_)begin - if(_zz_241_)begin - if(_zz_165_)begin - _zz_159_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_186)begin + if(_zz_187)begin + if(_zz_108)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_242_)begin - if(_zz_243_)begin - if(_zz_167_)begin - _zz_159_ = 1'b1; + if(_zz_188)begin + if(_zz_189)begin + if(_zz_110)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_244_)begin - if(_zz_245_)begin - if(_zz_169_)begin - _zz_159_ = 1'b1; + if(_zz_190)begin + if(_zz_191)begin + if(_zz_112)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_159_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_160_ = (_zz_51_ && writeBack_arbitration_isFiring); - assign _zz_164_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_165_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_166_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_167_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_168_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_169_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_34_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_38 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_37[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_47; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_107 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_108 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_109 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_110 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_111 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_112 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_170_ = execute_INSTRUCTION[14 : 12]; + assign _zz_113 = execute_INSTRUCTION[14 : 12]; always @ (*) begin - if((_zz_170_ == (3'b000))) begin - _zz_171_ = execute_BranchPlugin_eq; - end else if((_zz_170_ == (3'b001))) begin - _zz_171_ = (! execute_BranchPlugin_eq); - end else if((((_zz_170_ & (3'b101)) == (3'b101)))) begin - _zz_171_ = (! execute_SRC_LESS); + if((_zz_113 == 3'b000)) begin + _zz_114 = execute_BranchPlugin_eq; + end else if((_zz_113 == 3'b001)) begin + _zz_114 = (! execute_BranchPlugin_eq); + end else if((((_zz_113 & 3'b101) == 3'b101))) begin + _zz_114 = (! execute_SRC_LESS); end else begin - _zz_171_ = execute_SRC_LESS; + _zz_114 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_172_ = 1'b0; + _zz_115 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_172_ = 1'b1; + _zz_115 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_172_ = 1'b1; + _zz_115 = 1'b1; end default : begin - _zz_172_ = _zz_171_; + _zz_115 = _zz_114; end endcase end - assign _zz_33_ = _zz_172_; - assign _zz_173_ = _zz_298_[11]; + assign _zz_116 = _zz_247[11]; always @ (*) begin - _zz_174_[19] = _zz_173_; - _zz_174_[18] = _zz_173_; - _zz_174_[17] = _zz_173_; - _zz_174_[16] = _zz_173_; - _zz_174_[15] = _zz_173_; - _zz_174_[14] = _zz_173_; - _zz_174_[13] = _zz_173_; - _zz_174_[12] = _zz_173_; - _zz_174_[11] = _zz_173_; - _zz_174_[10] = _zz_173_; - _zz_174_[9] = _zz_173_; - _zz_174_[8] = _zz_173_; - _zz_174_[7] = _zz_173_; - _zz_174_[6] = _zz_173_; - _zz_174_[5] = _zz_173_; - _zz_174_[4] = _zz_173_; - _zz_174_[3] = _zz_173_; - _zz_174_[2] = _zz_173_; - _zz_174_[1] = _zz_173_; - _zz_174_[0] = _zz_173_; - end - - assign _zz_175_ = _zz_299_[19]; + _zz_117[19] = _zz_116; + _zz_117[18] = _zz_116; + _zz_117[17] = _zz_116; + _zz_117[16] = _zz_116; + _zz_117[15] = _zz_116; + _zz_117[14] = _zz_116; + _zz_117[13] = _zz_116; + _zz_117[12] = _zz_116; + _zz_117[11] = _zz_116; + _zz_117[10] = _zz_116; + _zz_117[9] = _zz_116; + _zz_117[8] = _zz_116; + _zz_117[7] = _zz_116; + _zz_117[6] = _zz_116; + _zz_117[5] = _zz_116; + _zz_117[4] = _zz_116; + _zz_117[3] = _zz_116; + _zz_117[2] = _zz_116; + _zz_117[1] = _zz_116; + _zz_117[0] = _zz_116; + end + + assign _zz_118 = _zz_248[19]; always @ (*) begin - _zz_176_[10] = _zz_175_; - _zz_176_[9] = _zz_175_; - _zz_176_[8] = _zz_175_; - _zz_176_[7] = _zz_175_; - _zz_176_[6] = _zz_175_; - _zz_176_[5] = _zz_175_; - _zz_176_[4] = _zz_175_; - _zz_176_[3] = _zz_175_; - _zz_176_[2] = _zz_175_; - _zz_176_[1] = _zz_175_; - _zz_176_[0] = _zz_175_; - end - - assign _zz_177_ = _zz_300_[11]; + _zz_119[10] = _zz_118; + _zz_119[9] = _zz_118; + _zz_119[8] = _zz_118; + _zz_119[7] = _zz_118; + _zz_119[6] = _zz_118; + _zz_119[5] = _zz_118; + _zz_119[4] = _zz_118; + _zz_119[3] = _zz_118; + _zz_119[2] = _zz_118; + _zz_119[1] = _zz_118; + _zz_119[0] = _zz_118; + end + + assign _zz_120 = _zz_249[11]; always @ (*) begin - _zz_178_[18] = _zz_177_; - _zz_178_[17] = _zz_177_; - _zz_178_[16] = _zz_177_; - _zz_178_[15] = _zz_177_; - _zz_178_[14] = _zz_177_; - _zz_178_[13] = _zz_177_; - _zz_178_[12] = _zz_177_; - _zz_178_[11] = _zz_177_; - _zz_178_[10] = _zz_177_; - _zz_178_[9] = _zz_177_; - _zz_178_[8] = _zz_177_; - _zz_178_[7] = _zz_177_; - _zz_178_[6] = _zz_177_; - _zz_178_[5] = _zz_177_; - _zz_178_[4] = _zz_177_; - _zz_178_[3] = _zz_177_; - _zz_178_[2] = _zz_177_; - _zz_178_[1] = _zz_177_; - _zz_178_[0] = _zz_177_; + _zz_121[18] = _zz_120; + _zz_121[17] = _zz_120; + _zz_121[16] = _zz_120; + _zz_121[15] = _zz_120; + _zz_121[14] = _zz_120; + _zz_121[13] = _zz_120; + _zz_121[12] = _zz_120; + _zz_121[11] = _zz_120; + _zz_121[10] = _zz_120; + _zz_121[9] = _zz_120; + _zz_121[8] = _zz_120; + _zz_121[7] = _zz_120; + _zz_121[6] = _zz_120; + _zz_121[5] = _zz_120; + _zz_121[4] = _zz_120; + _zz_121[3] = _zz_120; + _zz_121[2] = _zz_120; + _zz_121[1] = _zz_120; + _zz_121[0] = _zz_120; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_179_ = (_zz_301_[1] ^ execute_RS1[1]); + _zz_122 = (_zz_250[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_179_ = _zz_302_[1]; + _zz_122 = _zz_251[1]; end default : begin - _zz_179_ = _zz_303_[1]; + _zz_122 = _zz_252[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_179_); - assign _zz_31_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_122); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -3795,111 +3498,110 @@ module VexRiscv ( endcase end - assign _zz_180_ = _zz_304_[11]; + assign _zz_123 = _zz_253[11]; always @ (*) begin - _zz_181_[19] = _zz_180_; - _zz_181_[18] = _zz_180_; - _zz_181_[17] = _zz_180_; - _zz_181_[16] = _zz_180_; - _zz_181_[15] = _zz_180_; - _zz_181_[14] = _zz_180_; - _zz_181_[13] = _zz_180_; - _zz_181_[12] = _zz_180_; - _zz_181_[11] = _zz_180_; - _zz_181_[10] = _zz_180_; - _zz_181_[9] = _zz_180_; - _zz_181_[8] = _zz_180_; - _zz_181_[7] = _zz_180_; - _zz_181_[6] = _zz_180_; - _zz_181_[5] = _zz_180_; - _zz_181_[4] = _zz_180_; - _zz_181_[3] = _zz_180_; - _zz_181_[2] = _zz_180_; - _zz_181_[1] = _zz_180_; - _zz_181_[0] = _zz_180_; + _zz_124[19] = _zz_123; + _zz_124[18] = _zz_123; + _zz_124[17] = _zz_123; + _zz_124[16] = _zz_123; + _zz_124[15] = _zz_123; + _zz_124[14] = _zz_123; + _zz_124[13] = _zz_123; + _zz_124[12] = _zz_123; + _zz_124[11] = _zz_123; + _zz_124[10] = _zz_123; + _zz_124[9] = _zz_123; + _zz_124[8] = _zz_123; + _zz_124[7] = _zz_123; + _zz_124[6] = _zz_123; + _zz_124[5] = _zz_123; + _zz_124[4] = _zz_123; + _zz_124[3] = _zz_123; + _zz_124[2] = _zz_123; + _zz_124[1] = _zz_123; + _zz_124[0] = _zz_123; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_181_,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_124,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_183_,{{{_zz_506_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_185_,{{{_zz_507_,_zz_508_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_126,{{{_zz_466,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_128,{{{_zz_467,_zz_468},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_307_}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_256}; end end endcase end - assign _zz_182_ = _zz_305_[19]; + assign _zz_125 = _zz_254[19]; always @ (*) begin - _zz_183_[10] = _zz_182_; - _zz_183_[9] = _zz_182_; - _zz_183_[8] = _zz_182_; - _zz_183_[7] = _zz_182_; - _zz_183_[6] = _zz_182_; - _zz_183_[5] = _zz_182_; - _zz_183_[4] = _zz_182_; - _zz_183_[3] = _zz_182_; - _zz_183_[2] = _zz_182_; - _zz_183_[1] = _zz_182_; - _zz_183_[0] = _zz_182_; - end - - assign _zz_184_ = _zz_306_[11]; + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; + end + + assign _zz_127 = _zz_255[11]; always @ (*) begin - _zz_185_[18] = _zz_184_; - _zz_185_[17] = _zz_184_; - _zz_185_[16] = _zz_184_; - _zz_185_[15] = _zz_184_; - _zz_185_[14] = _zz_184_; - _zz_185_[13] = _zz_184_; - _zz_185_[12] = _zz_184_; - _zz_185_[11] = _zz_184_; - _zz_185_[10] = _zz_184_; - _zz_185_[9] = _zz_184_; - _zz_185_[8] = _zz_184_; - _zz_185_[7] = _zz_184_; - _zz_185_[6] = _zz_184_; - _zz_185_[5] = _zz_184_; - _zz_185_[4] = _zz_184_; - _zz_185_[3] = _zz_184_; - _zz_185_[2] = _zz_184_; - _zz_185_[1] = _zz_184_; - _zz_185_[0] = _zz_184_; + _zz_128[18] = _zz_127; + _zz_128[17] = _zz_127; + _zz_128[16] = _zz_127; + _zz_128[15] = _zz_127; + _zz_128[14] = _zz_127; + _zz_128[13] = _zz_127; + _zz_128[12] = _zz_127; + _zz_128[11] = _zz_127; + _zz_128[10] = _zz_127; + _zz_128[9] = _zz_127; + _zz_128[8] = _zz_127; + _zz_128[7] = _zz_127; + _zz_128[6] = _zz_127; + _zz_128[5] = _zz_127; + _zz_128[4] = _zz_127; + _zz_128[3] = _zz_127; + _zz_128[2] = _zz_127; + _zz_128[1] = _zz_127; + _zz_128[0] = _zz_127; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_30_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign CsrPlugin_misa_base = (2'b01); - assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); - assign _zz_186_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_187_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_188_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign _zz_129 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_130 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_131 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_189_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_190_ = _zz_308_[0]; - assign _zz_191_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_192_ = _zz_310_[0]; + assign _zz_132 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_133 = _zz_257[0]; + assign _zz_134 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_135 = _zz_259[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_229_)begin + if(_zz_178)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3919,7 +3621,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_233_)begin + if(_zz_180)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3940,9 +3642,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -3966,7 +3669,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; @@ -3977,7 +3680,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3988,52 +3691,45 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_28_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_27_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - assign execute_CsrPlugin_inWfi = 1'b0; - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000001 : begin + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_192)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4052,20 +3748,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_246_)begin + if(_zz_193)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_246_)begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_193)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -4073,53 +3769,24 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_200_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_201_; - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_192)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_192)begin + execute_CsrPlugin_readInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_255_) + case(_zz_204) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4130,10 +3797,11 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; always @ (*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_217_)begin - if(_zz_231_)begin + if(_zz_166)begin + if(_zz_179)begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end @@ -4146,23 +3814,23 @@ module VexRiscv ( end end - assign memory_MulDivIterativePlugin_mul_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == (6'b100000)); - assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); + assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); + assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); always @ (*) begin if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_313_); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_262); end if(memory_MulDivIterativePlugin_mul_counter_willClear)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end end always @ (*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_218_)begin - if(_zz_232_)begin + if(_zz_167)begin + if(_zz_194)begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end @@ -4170,66 +3838,68 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_247_)begin + if(_zz_195)begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end - assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == (6'b100001)); + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); always @ (*) begin if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin - memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_321_); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_270); end if(memory_MulDivIterativePlugin_div_counter_willClear)begin - memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end end - assign _zz_193_ = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign _zz_194_ = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_193_[31]}; - assign _zz_195_ = (_zz_194_ - _zz_322_); - assign _zz_196_ = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_197_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_198_ = ((execute_IS_MUL && _zz_197_) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_136 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_136[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_271); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_272 : _zz_273); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_274[31:0]; + assign _zz_137 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_138 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_139 = ((execute_IS_MUL && _zz_138) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_199_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_199_[31 : 0] = execute_RS1; - end - - assign _zz_201_ = (_zz_200_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_201_ != (32'b00000000000000000000000000000000)); - assign _zz_24_ = decode_SHIFT_CTRL; - assign _zz_22_ = _zz_75_; - assign _zz_37_ = decode_to_execute_SHIFT_CTRL; - assign _zz_21_ = decode_ALU_CTRL; - assign _zz_19_ = _zz_56_; - assign _zz_47_ = decode_to_execute_ALU_CTRL; - assign _zz_18_ = decode_BRANCH_CTRL; - assign _zz_95_ = _zz_61_; - assign _zz_32_ = decode_to_execute_BRANCH_CTRL; - assign _zz_16_ = decode_SRC2_CTRL; - assign _zz_14_ = _zz_76_; - assign _zz_42_ = decode_to_execute_SRC2_CTRL; - assign _zz_13_ = decode_ENV_CTRL; - assign _zz_10_ = execute_ENV_CTRL; - assign _zz_8_ = memory_ENV_CTRL; - assign _zz_11_ = _zz_58_; - assign _zz_26_ = decode_to_execute_ENV_CTRL; - assign _zz_25_ = execute_to_memory_ENV_CTRL; - assign _zz_29_ = memory_to_writeBack_ENV_CTRL; - assign _zz_6_ = decode_ALU_BITWISE_CTRL; - assign _zz_4_ = _zz_57_; - assign _zz_49_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_3_ = decode_SRC1_CTRL; - assign _zz_1_ = _zz_66_; - assign _zz_44_ = decode_to_execute_SRC1_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + _zz_140[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_140[31 : 0] = execute_RS1; + end + + assign _zz_142 = (_zz_141 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_142 != 32'h0); + assign _zz_24 = decode_SRC1_CTRL; + assign _zz_22 = _zz_46; + assign _zz_34 = decode_to_execute_SRC1_CTRL; + assign _zz_21 = decode_ALU_CTRL; + assign _zz_19 = _zz_45; + assign _zz_35 = decode_to_execute_ALU_CTRL; + assign _zz_18 = decode_SRC2_CTRL; + assign _zz_16 = _zz_44; + assign _zz_33 = decode_to_execute_SRC2_CTRL; + assign _zz_15 = decode_ALU_BITWISE_CTRL; + assign _zz_13 = _zz_43; + assign _zz_36 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_12 = decode_SHIFT_CTRL; + assign _zz_10 = _zz_42; + assign _zz_31 = decode_to_execute_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_48 = _zz_41; + assign _zz_28 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_40; + assign _zz_26 = decode_to_execute_ENV_CTRL; + assign _zz_25 = execute_to_memory_ENV_CTRL; + assign _zz_27 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -4246,28 +3916,92 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - assign iBusWishbone_ADR = {_zz_341_,_zz_202_}; - assign iBusWishbone_CTI = ((_zz_202_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); + always @ (*) begin + _zz_143 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_143[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_143[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_143[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_144 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_144[11 : 11] = CsrPlugin_mip_MEIP; + _zz_144[7 : 7] = CsrPlugin_mip_MTIP; + _zz_144[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_145 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_145[11 : 11] = CsrPlugin_mie_MEIE; + _zz_145[7 : 7] = CsrPlugin_mie_MTIE; + _zz_145[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_146 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_146[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_147 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_147[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_147[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_148 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_148[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_149 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_149[31 : 0] = _zz_141; + end + end + + always @ (*) begin + _zz_150 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_150[31 : 0] = _zz_142; + end + end + + assign execute_CsrPlugin_readData = (((_zz_143 | _zz_144) | (_zz_145 | _zz_146)) | ((_zz_147 | _zz_148) | (_zz_149 | _zz_150))); + assign iBusWishbone_ADR = {_zz_290,_zz_151}; + assign iBusWishbone_CTI = ((_zz_151 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_248_)begin + if(_zz_196)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_248_)begin + if(_zz_196)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_203_; + assign iBus_rsp_valid = _zz_152; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; @@ -4277,26 +4011,26 @@ module VexRiscv ( assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); - assign dBusWishbone_CTI = (3'b000); - assign dBusWishbone_BTE = (2'b00); + assign dBusWishbone_CTI = 3'b000; + assign dBusWishbone_BTE = 2'b00; always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_204_ = (4'b0001); + _zz_153 = 4'b0001; end 2'b01 : begin - _zz_204_ = (4'b0011); + _zz_153 = 4'b0011; end default : begin - _zz_204_ = (4'b1111); + _zz_153 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = _zz_342_[3:0]; + dBusWishbone_SEL = (_zz_153 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin - dBusWishbone_SEL = (4'b1111); + dBusWishbone_SEL = 4'b1111; end end @@ -4311,24 +4045,24 @@ module VexRiscv ( always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_112_ <= 1'b0; - _zz_114_ <= 1'b0; + _zz_61 <= 1'b0; + _zz_63 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_127_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_149_ <= 1'b1; + IBusCachedPlugin_rspCounter <= _zz_76; + IBusCachedPlugin_rspCounter <= 32'h0; + _zz_98 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_161_ <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -4337,23 +4071,30 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_MulDivIterativePlugin_mul_counter_value <= (6'b000000); - memory_MulDivIterativePlugin_div_counter_value <= (6'b000000); - _zz_200_ <= (32'b00000000000000000000000000000000); + memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + _zz_141 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_202_ <= (3'b000); - _zz_203_ <= 1'b0; + _zz_151 <= 3'b000; + _zz_152 <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin @@ -4362,75 +4103,89 @@ module VexRiscv ( if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_112_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_61 <= 1'b0; end - if(_zz_110_)begin - _zz_112_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if(_zz_59)begin + _zz_61 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_114_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_63 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_114_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_63 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); - end - _zz_149_ <= 1'b0; - if(_zz_223_)begin - if(_zz_230_)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + _zz_98 <= 1'b0; + if(_zz_172)begin + if(_zz_197)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -4440,7 +4195,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_161_ <= _zz_160_; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4462,19 +4217,38 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_249_)begin - if(_zz_250_)begin + if(_zz_198)begin + if(_zz_199)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_251_)begin + if(_zz_200)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_252_)begin + if(_zz_201)begin CsrPlugin_interrupt_valid <= 1'b1; end end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_234_)begin + if(_zz_181)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4485,10 +4259,10 @@ module VexRiscv ( end endcase end - if(_zz_235_)begin - case(_zz_236_) + if(_zz_182)begin + case(_zz_183) 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; end @@ -4496,15 +4270,9 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_188_,{_zz_187_,_zz_186_}} != (3'b000)); + execute_CsrPlugin_wfiWake <= (({_zz_131,{_zz_130,_zz_129}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_35_; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -4523,48 +4291,32 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_200_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_335_[0]; - CsrPlugin_mstatus_MIE <= _zz_336_[0]; - end - end - 12'b001101000001 : begin - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_338_[0]; - CsrPlugin_mie_MTIE <= _zz_339_[0]; - CsrPlugin_mie_MSIE <= _zz_340_[0]; - end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_284[0]; + CsrPlugin_mstatus_MIE <= _zz_285[0]; end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_287[0]; + CsrPlugin_mie_MTIE <= _zz_288[0]; + CsrPlugin_mie_MSIE <= _zz_289[0]; end - default : begin + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_141 <= execute_CsrPlugin_writeData[31 : 0]; end - endcase - if(_zz_248_)begin + end + if(_zz_196)begin if(iBusWishbone_ACK)begin - _zz_202_ <= (_zz_202_ + (3'b001)); + _zz_151 <= (_zz_151 + 3'b001); end end - _zz_203_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_253_)begin + _zz_152 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_202)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -4576,63 +4328,55 @@ module VexRiscv ( always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_115_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_64 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin - $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); - end - if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin - $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); - end - if(_zz_223_)begin - if(_zz_230_)begin - execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + if(_zz_172)begin + if(_zz_197)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - if(_zz_160_)begin - _zz_162_ <= _zz_50_[11 : 7]; - _zz_163_ <= _zz_79_; - end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_229_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_190_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_190_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_178)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_133 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_133 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_233_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_192_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_192_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_180)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_135 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_135 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_249_)begin - if(_zz_250_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_198)begin + if(_zz_199)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_251_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_200)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_252_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_201)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_234_)begin + if(_zz_181)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4646,96 +4390,93 @@ module VexRiscv ( end endcase end - if(_zz_217_)begin - if(_zz_231_)begin + if(_zz_166)begin + if(_zz_179)begin memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_314_,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_263,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end - if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin memory_MulDivIterativePlugin_div_done <= 1'b1; end if((! memory_arbitration_isStuck))begin memory_MulDivIterativePlugin_div_done <= 1'b0; end - if(_zz_218_)begin - if(_zz_232_)begin - memory_MulDivIterativePlugin_rs1[31 : 0] <= _zz_323_[31:0]; - memory_MulDivIterativePlugin_accumulator[31 : 0] <= ((! _zz_195_[32]) ? _zz_324_ : _zz_325_); - if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin - memory_MulDivIterativePlugin_div_result <= _zz_326_[31:0]; + if(_zz_167)begin + if(_zz_194)begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_result <= _zz_275[31:0]; end end end - if(_zz_247_)begin - memory_MulDivIterativePlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_MulDivIterativePlugin_rs1 <= ((_zz_198_ ? (~ _zz_199_) : _zz_199_) + _zz_332_); - memory_MulDivIterativePlugin_rs2 <= ((_zz_197_ ? (~ execute_RS2) : execute_RS2) + _zz_334_); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_198_ ^ (_zz_197_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(_zz_195)begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_139 ? (~ _zz_140) : _zz_140) + _zz_281); + memory_MulDivIterativePlugin_rs2 <= ((_zz_138 ? (~ execute_RS2) : execute_RS2) + _zz_283); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_139 ^ (_zz_138 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_23_; + decode_to_execute_PC <= decode_PC; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_32; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_20_; + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; end if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + decode_to_execute_FORMAL_PC_NEXT <= _zz_50; end if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_49; end if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + decode_to_execute_SRC1_CTRL <= _zz_23; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + decode_to_execute_ALU_CTRL <= _zz_20; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_17_; + decode_to_execute_SRC2_CTRL <= _zz_17; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_15_; + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_36_; + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end if((! execute_arbitration_isStuck))begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; @@ -4744,28 +4485,37 @@ module VexRiscv ( execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_12_; + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_9_; + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_7_; + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_14; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress; - execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess; - execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead; - execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite; - execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute; - execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception; - execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling; + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; end if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_MUL <= decode_IS_MUL; @@ -4774,43 +4524,37 @@ module VexRiscv ( execute_to_memory_IS_MUL <= execute_IS_MUL; end if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_41_; + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_97_; + decode_to_execute_IS_DIV <= decode_IS_DIV; end if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_96_; + execute_to_memory_IS_DIV <= execute_IS_DIV; end if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + decode_to_execute_RS1 <= decode_RS1; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_5_; + decode_to_execute_RS2 <= decode_RS2; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_2_; + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; end if((! memory_arbitration_isStuck))begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; @@ -4818,67 +4562,371 @@ module VexRiscv ( if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; + execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; + execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; + execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; + execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; + execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; + execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; + execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; + execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + end + if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_30; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_29; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_286[0]; end - 12'b001100000000 : begin + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_202)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_9; + reg [22:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [22:0] _zz_15; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [8:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [8:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; + + assign _zz_11 = (! lineLoader_flushCounter[6]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_337_[0]; - end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; end - 12'b001101000011 : begin + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; end - 12'b111111000000 : begin + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end - 12'b001100000100 : begin + if(io_flush)begin + lineLoader_flushPending <= 1'b1; end - 12'b001101000010 : begin + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; end - default : begin + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end end - endcase - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_253_)begin - dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; - dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; - dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; - dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; end end -endmodule + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_3 <= lineLoader_flushCounter[6]; + if(_zz_12)begin + lineLoader_flushCounter <= 7'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v index 2ff4cd6..87a6a9f 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v @@ -1,2155 +1,1829 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:06:45 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - `define EnvCtrlEnum_defaultEncoding_type [1:0] `define EnvCtrlEnum_defaultEncoding_NONE 2'b00 `define EnvCtrlEnum_defaultEncoding_XRET 2'b01 `define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - `define BranchCtrlEnum_defaultEncoding_type [1:0] `define BranchCtrlEnum_defaultEncoding_INC 2'b00 `define BranchCtrlEnum_defaultEncoding_B 2'b01 `define BranchCtrlEnum_defaultEncoding_JAL 2'b10 `define BranchCtrlEnum_defaultEncoding_JALR 2'b11 -module InstructionCache ( - input io_flush, - input io_cpu_prefetch_isValid, - output reg io_cpu_prefetch_haltIt, - input [31:0] io_cpu_prefetch_pc, - input io_cpu_fetch_isValid, - input io_cpu_fetch_isStuck, - input io_cpu_fetch_isRemoved, - input [31:0] io_cpu_fetch_pc, - output [31:0] io_cpu_fetch_data, - input io_cpu_fetch_dataBypassValid, - input [31:0] io_cpu_fetch_dataBypass, - output io_cpu_fetch_mmuBus_cmd_isValid, - output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, - output io_cpu_fetch_mmuBus_cmd_bypassTranslation, - input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, - input io_cpu_fetch_mmuBus_rsp_isIoAccess, - input io_cpu_fetch_mmuBus_rsp_allowRead, - input io_cpu_fetch_mmuBus_rsp_allowWrite, - input io_cpu_fetch_mmuBus_rsp_allowExecute, - input io_cpu_fetch_mmuBus_rsp_exception, - input io_cpu_fetch_mmuBus_rsp_refilling, - output io_cpu_fetch_mmuBus_end, - input io_cpu_fetch_mmuBus_busy, - output [31:0] io_cpu_fetch_physicalAddress, - output io_cpu_fetch_haltIt, - input io_cpu_decode_isValid, - input io_cpu_decode_isStuck, - input [31:0] io_cpu_decode_pc, - output [31:0] io_cpu_decode_physicalAddress, - output [31:0] io_cpu_decode_data, - output io_cpu_decode_cacheMiss, - output io_cpu_decode_error, - output io_cpu_decode_mmuRefilling, - output io_cpu_decode_mmuException, - input io_cpu_decode_isUser, - input io_cpu_fill_valid, - input [31:0] io_cpu_fill_payload, - output io_mem_cmd_valid, - input io_mem_cmd_ready, - output [31:0] io_mem_cmd_payload_address, - output [2:0] io_mem_cmd_payload_size, - input io_mem_rsp_valid, - input [31:0] io_mem_rsp_payload_data, - input io_mem_rsp_payload_error, - input [2:0] _zz_10_, - input [31:0] _zz_11_, - input clk, - input reset); - reg [22:0] _zz_12_; - reg [31:0] _zz_13_; - wire _zz_14_; - wire _zz_15_; - wire [0:0] _zz_16_; - wire [0:0] _zz_17_; - wire [22:0] _zz_18_; - reg _zz_1_; - reg _zz_2_; - reg lineLoader_fire; - reg lineLoader_valid; - reg [31:0] lineLoader_address; - reg lineLoader_hadError; - reg lineLoader_flushPending; - reg [6:0] lineLoader_flushCounter; - reg _zz_3_; - reg lineLoader_cmdSent; - reg lineLoader_wayToAllocate_willIncrement; - wire lineLoader_wayToAllocate_willClear; - wire lineLoader_wayToAllocate_willOverflowIfInc; - wire lineLoader_wayToAllocate_willOverflow; - reg [2:0] lineLoader_wordIndex; - wire lineLoader_write_tag_0_valid; - wire [5:0] lineLoader_write_tag_0_payload_address; - wire lineLoader_write_tag_0_payload_data_valid; - wire lineLoader_write_tag_0_payload_data_error; - wire [20:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_data_0_valid; - wire [8:0] lineLoader_write_data_0_payload_address; - wire [31:0] lineLoader_write_data_0_payload_data; - wire _zz_4_; - wire [5:0] _zz_5_; - wire _zz_6_; - wire fetchStage_read_waysValues_0_tag_valid; - wire fetchStage_read_waysValues_0_tag_error; - wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_7_; - wire [8:0] _zz_8_; - wire _zz_9_; - wire [31:0] fetchStage_read_waysValues_0_data; - wire fetchStage_hit_hits_0; - wire fetchStage_hit_valid; - wire fetchStage_hit_error; - wire [31:0] fetchStage_hit_data; - wire [31:0] fetchStage_hit_word; - reg [31:0] io_cpu_fetch_data_regNextWhen; - reg [31:0] decodeStage_mmuRsp_physicalAddress; - reg decodeStage_mmuRsp_isIoAccess; - reg decodeStage_mmuRsp_allowRead; - reg decodeStage_mmuRsp_allowWrite; - reg decodeStage_mmuRsp_allowExecute; - reg decodeStage_mmuRsp_exception; - reg decodeStage_mmuRsp_refilling; - reg decodeStage_hit_valid; - reg decodeStage_hit_error; - (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - (* ram_style = "block" *) reg [31:0] ways_0_datas [0:511]; - assign _zz_14_ = (! lineLoader_flushCounter[6]); - assign _zz_15_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_16_ = _zz_7_[0 : 0]; - assign _zz_17_ = _zz_7_[1 : 1]; - assign _zz_18_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2_) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_18_; - end - end - - always @ (posedge clk) begin - if(_zz_6_) begin - _zz_12_ <= ways_0_tags[_zz_5_]; - end - end - - always @ (posedge clk) begin - if(_zz_1_) begin - ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_9_) begin - _zz_13_ <= ways_0_datas[_zz_8_]; - end - end - - always @ (*) begin - _zz_1_ = 1'b0; - if(lineLoader_write_data_0_valid)begin - _zz_1_ = 1'b1; - end - end - - always @ (*) begin - _zz_2_ = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_2_ = 1'b1; - end - end - - assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; - always @ (*) begin - lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == (3'b111)))begin - lineLoader_fire = 1'b1; - end - end - end +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - always @ (*) begin - io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_14_)begin - io_cpu_prefetch_haltIt = 1'b1; - end - if((! _zz_3_))begin - io_cpu_prefetch_haltIt = 1'b1; - end - if(io_flush)begin - io_cpu_prefetch_haltIt = 1'b1; - end - end +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); - assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; - assign io_mem_cmd_payload_size = (3'b101); - always @ (*) begin - lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin - lineLoader_wayToAllocate_willIncrement = 1'b1; - end - end +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; - assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign _zz_4_ = 1'b1; - assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[6])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; - assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_5_ = io_cpu_prefetch_pc[10 : 5]; - assign _zz_6_ = (! io_cpu_fetch_isStuck); - assign _zz_7_ = _zz_12_; - assign fetchStage_read_waysValues_0_tag_valid = _zz_16_[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_17_[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_7_[22 : 2]; - assign _zz_8_ = io_cpu_prefetch_pc[10 : 2]; - assign _zz_9_ = (! io_cpu_fetch_isStuck); - assign fetchStage_read_waysValues_0_data = _zz_13_; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 11])); - assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); - assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; - assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; - assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; - assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); - assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; - assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; - assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; - assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; - assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); - assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; - assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); - assign io_cpu_decode_error = decodeStage_hit_error; - assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; - assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); - assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin - if(reset) begin - lineLoader_valid <= 1'b0; - lineLoader_hadError <= 1'b0; - lineLoader_flushPending <= 1'b1; - lineLoader_cmdSent <= 1'b0; - lineLoader_wordIndex <= (3'b000); - end else begin - if(lineLoader_fire)begin - lineLoader_valid <= 1'b0; - end - if(lineLoader_fire)begin - lineLoader_hadError <= 1'b0; - end - if(io_cpu_fill_valid)begin - lineLoader_valid <= 1'b1; - end - if(io_flush)begin - lineLoader_flushPending <= 1'b1; - end - if(_zz_15_)begin - lineLoader_flushPending <= 1'b0; - end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin - lineLoader_cmdSent <= 1'b1; - end - if(lineLoader_fire)begin - lineLoader_cmdSent <= 1'b0; - end - if(io_mem_rsp_valid)begin - lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); - if(io_mem_rsp_payload_error)begin - lineLoader_hadError <= 1'b1; - end - end - end - end +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin - lineLoader_address <= io_cpu_fill_payload; - end - if(_zz_14_)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + (7'b0000001)); - end - _zz_3_ <= lineLoader_flushCounter[6]; - if(_zz_15_)begin - lineLoader_flushCounter <= (7'b0000000); - end - if((! io_cpu_decode_isStuck))begin - io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; - decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; - decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; - decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; - decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; - decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; - decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_valid <= fetchStage_hit_valid; - end - if((! io_cpu_decode_isStuck))begin - decodeStage_hit_error <= fetchStage_hit_error; - end - if((_zz_10_ != (3'b000)))begin - io_cpu_fetch_data_regNextWhen <= _zz_11_; - end - end +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -endmodule module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output reg iBusWishbone_CYC, - output reg iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output reg [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset, - input debugReset); - wire _zz_209_; - wire _zz_210_; - wire _zz_211_; - wire _zz_212_; - wire [31:0] _zz_213_; - wire _zz_214_; - wire _zz_215_; - wire _zz_216_; - reg _zz_217_; - reg [31:0] _zz_218_; - reg [31:0] _zz_219_; - reg [31:0] _zz_220_; - wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - wire IBusCachedPlugin_cache_io_cpu_decode_error; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; - wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; - wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; - wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; - wire IBusCachedPlugin_cache_io_mem_cmd_valid; - wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; - wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_221_; - wire _zz_222_; - wire _zz_223_; - wire _zz_224_; - wire _zz_225_; - wire _zz_226_; - wire _zz_227_; - wire _zz_228_; - wire _zz_229_; - wire _zz_230_; - wire _zz_231_; - wire _zz_232_; - wire _zz_233_; - wire _zz_234_; - wire _zz_235_; - wire _zz_236_; - wire _zz_237_; - wire _zz_238_; - wire _zz_239_; - wire _zz_240_; - wire _zz_241_; - wire _zz_242_; - wire [1:0] _zz_243_; - wire _zz_244_; - wire _zz_245_; - wire _zz_246_; - wire _zz_247_; - wire _zz_248_; - wire _zz_249_; - wire _zz_250_; - wire _zz_251_; - wire _zz_252_; - wire _zz_253_; - wire _zz_254_; - wire [5:0] _zz_255_; - wire _zz_256_; - wire _zz_257_; - wire _zz_258_; - wire _zz_259_; - wire _zz_260_; - wire _zz_261_; - wire [1:0] _zz_262_; - wire _zz_263_; - wire [4:0] _zz_264_; - wire [2:0] _zz_265_; - wire [31:0] _zz_266_; - wire [11:0] _zz_267_; - wire [31:0] _zz_268_; - wire [19:0] _zz_269_; - wire [11:0] _zz_270_; - wire [31:0] _zz_271_; - wire [31:0] _zz_272_; - wire [19:0] _zz_273_; - wire [11:0] _zz_274_; - wire [2:0] _zz_275_; - wire [0:0] _zz_276_; - wire [0:0] _zz_277_; - wire [0:0] _zz_278_; - wire [0:0] _zz_279_; - wire [0:0] _zz_280_; - wire [0:0] _zz_281_; - wire [0:0] _zz_282_; - wire [0:0] _zz_283_; - wire [0:0] _zz_284_; - wire [0:0] _zz_285_; - wire [0:0] _zz_286_; - wire [0:0] _zz_287_; - wire [0:0] _zz_288_; - wire [0:0] _zz_289_; - wire [0:0] _zz_290_; - wire [0:0] _zz_291_; - wire [0:0] _zz_292_; - wire [0:0] _zz_293_; - wire [2:0] _zz_294_; - wire [4:0] _zz_295_; - wire [11:0] _zz_296_; - wire [11:0] _zz_297_; - wire [31:0] _zz_298_; - wire [31:0] _zz_299_; - wire [31:0] _zz_300_; - wire [31:0] _zz_301_; - wire [31:0] _zz_302_; - wire [31:0] _zz_303_; - wire [31:0] _zz_304_; - wire [31:0] _zz_305_; - wire [32:0] _zz_306_; - wire [11:0] _zz_307_; - wire [19:0] _zz_308_; - wire [11:0] _zz_309_; - wire [31:0] _zz_310_; - wire [31:0] _zz_311_; - wire [31:0] _zz_312_; - wire [11:0] _zz_313_; - wire [19:0] _zz_314_; - wire [11:0] _zz_315_; - wire [2:0] _zz_316_; - wire [1:0] _zz_317_; - wire [1:0] _zz_318_; - wire [1:0] _zz_319_; - wire [1:0] _zz_320_; - wire [0:0] _zz_321_; - wire [5:0] _zz_322_; - wire [33:0] _zz_323_; - wire [32:0] _zz_324_; - wire [33:0] _zz_325_; - wire [32:0] _zz_326_; - wire [33:0] _zz_327_; - wire [32:0] _zz_328_; - wire [0:0] _zz_329_; - wire [5:0] _zz_330_; - wire [32:0] _zz_331_; - wire [32:0] _zz_332_; - wire [31:0] _zz_333_; - wire [31:0] _zz_334_; - wire [32:0] _zz_335_; - wire [32:0] _zz_336_; - wire [32:0] _zz_337_; - wire [0:0] _zz_338_; - wire [32:0] _zz_339_; - wire [0:0] _zz_340_; - wire [32:0] _zz_341_; - wire [0:0] _zz_342_; - wire [31:0] _zz_343_; - wire [0:0] _zz_344_; - wire [0:0] _zz_345_; - wire [0:0] _zz_346_; - wire [0:0] _zz_347_; - wire [0:0] _zz_348_; - wire [0:0] _zz_349_; - wire [26:0] _zz_350_; - wire [6:0] _zz_351_; - wire _zz_352_; - wire _zz_353_; - wire [2:0] _zz_354_; - wire _zz_355_; - wire _zz_356_; - wire _zz_357_; - wire [31:0] _zz_358_; - wire [31:0] _zz_359_; - wire [31:0] _zz_360_; - wire _zz_361_; - wire [3:0] _zz_362_; - wire [3:0] _zz_363_; - wire _zz_364_; - wire [0:0] _zz_365_; - wire [25:0] _zz_366_; - wire [31:0] _zz_367_; - wire [31:0] _zz_368_; - wire _zz_369_; - wire [0:0] _zz_370_; - wire [0:0] _zz_371_; - wire _zz_372_; - wire _zz_373_; - wire [0:0] _zz_374_; - wire [0:0] _zz_375_; - wire [2:0] _zz_376_; - wire [2:0] _zz_377_; - wire _zz_378_; - wire [0:0] _zz_379_; - wire [22:0] _zz_380_; - wire [31:0] _zz_381_; - wire [31:0] _zz_382_; - wire [31:0] _zz_383_; - wire [31:0] _zz_384_; - wire [31:0] _zz_385_; - wire [31:0] _zz_386_; - wire [31:0] _zz_387_; - wire [31:0] _zz_388_; - wire [31:0] _zz_389_; - wire [31:0] _zz_390_; - wire [31:0] _zz_391_; - wire _zz_392_; - wire [0:0] _zz_393_; - wire [0:0] _zz_394_; - wire [0:0] _zz_395_; - wire [4:0] _zz_396_; - wire [0:0] _zz_397_; - wire [0:0] _zz_398_; - wire _zz_399_; - wire [0:0] _zz_400_; - wire [20:0] _zz_401_; - wire [31:0] _zz_402_; - wire [31:0] _zz_403_; - wire [31:0] _zz_404_; - wire [31:0] _zz_405_; - wire [31:0] _zz_406_; - wire _zz_407_; - wire [0:0] _zz_408_; - wire [2:0] _zz_409_; - wire [31:0] _zz_410_; - wire [31:0] _zz_411_; - wire _zz_412_; - wire [2:0] _zz_413_; - wire [2:0] _zz_414_; - wire _zz_415_; - wire [0:0] _zz_416_; - wire [18:0] _zz_417_; - wire [31:0] _zz_418_; - wire [31:0] _zz_419_; - wire [31:0] _zz_420_; - wire _zz_421_; - wire [0:0] _zz_422_; - wire [0:0] _zz_423_; - wire [31:0] _zz_424_; - wire _zz_425_; - wire [0:0] _zz_426_; - wire [0:0] _zz_427_; - wire [0:0] _zz_428_; - wire [1:0] _zz_429_; - wire [0:0] _zz_430_; - wire [0:0] _zz_431_; - wire _zz_432_; - wire [0:0] _zz_433_; - wire [16:0] _zz_434_; - wire [31:0] _zz_435_; - wire [31:0] _zz_436_; - wire [31:0] _zz_437_; - wire [31:0] _zz_438_; - wire [31:0] _zz_439_; - wire [31:0] _zz_440_; - wire [31:0] _zz_441_; - wire [31:0] _zz_442_; - wire [31:0] _zz_443_; - wire [31:0] _zz_444_; - wire _zz_445_; - wire _zz_446_; - wire [31:0] _zz_447_; - wire [31:0] _zz_448_; - wire [0:0] _zz_449_; - wire [0:0] _zz_450_; - wire _zz_451_; - wire [0:0] _zz_452_; - wire [14:0] _zz_453_; - wire [31:0] _zz_454_; - wire [0:0] _zz_455_; - wire [0:0] _zz_456_; - wire [0:0] _zz_457_; - wire [1:0] _zz_458_; - wire [1:0] _zz_459_; - wire [1:0] _zz_460_; - wire _zz_461_; - wire [0:0] _zz_462_; - wire [11:0] _zz_463_; - wire [31:0] _zz_464_; - wire [31:0] _zz_465_; - wire [31:0] _zz_466_; - wire [31:0] _zz_467_; - wire [31:0] _zz_468_; - wire [31:0] _zz_469_; - wire [31:0] _zz_470_; - wire [31:0] _zz_471_; - wire [31:0] _zz_472_; - wire [31:0] _zz_473_; - wire [31:0] _zz_474_; - wire [0:0] _zz_475_; - wire [0:0] _zz_476_; - wire [1:0] _zz_477_; - wire [1:0] _zz_478_; - wire _zz_479_; - wire [0:0] _zz_480_; - wire [8:0] _zz_481_; - wire [31:0] _zz_482_; - wire [31:0] _zz_483_; - wire [31:0] _zz_484_; - wire _zz_485_; - wire [0:0] _zz_486_; - wire [0:0] _zz_487_; - wire _zz_488_; - wire [0:0] _zz_489_; - wire [0:0] _zz_490_; - wire _zz_491_; - wire [0:0] _zz_492_; - wire [5:0] _zz_493_; - wire [31:0] _zz_494_; - wire [31:0] _zz_495_; - wire [31:0] _zz_496_; - wire _zz_497_; - wire _zz_498_; - wire _zz_499_; - wire [1:0] _zz_500_; - wire [1:0] _zz_501_; - wire _zz_502_; - wire [0:0] _zz_503_; - wire [2:0] _zz_504_; - wire [31:0] _zz_505_; - wire [31:0] _zz_506_; - wire _zz_507_; - wire [0:0] _zz_508_; - wire [0:0] _zz_509_; - wire [1:0] _zz_510_; - wire [1:0] _zz_511_; - wire _zz_512_; - wire _zz_513_; - wire [31:0] _zz_514_; - wire [31:0] _zz_515_; - wire [31:0] _zz_516_; - wire _zz_517_; - wire [0:0] _zz_518_; - wire [12:0] _zz_519_; - wire [31:0] _zz_520_; - wire [31:0] _zz_521_; - wire [31:0] _zz_522_; - wire _zz_523_; - wire [0:0] _zz_524_; - wire [6:0] _zz_525_; - wire [31:0] _zz_526_; - wire [31:0] _zz_527_; - wire [31:0] _zz_528_; - wire _zz_529_; - wire [0:0] _zz_530_; - wire [0:0] _zz_531_; - wire _zz_532_; - wire _zz_533_; - wire _zz_534_; - wire decode_CSR_WRITE_OPCODE; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire decode_IS_CSR; - wire decode_DO_EBREAK; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_1_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_2_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_3_; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_4_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_5_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_6_; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_SRC_LESS_UNSIGNED; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_7_; - wire `AluCtrlEnum_defaultEncoding_type _zz_8_; - wire `AluCtrlEnum_defaultEncoding_type _zz_9_; - wire decode_IS_DIV; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_10_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_11_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_12_; - wire decode_SRC2_FORCE_ZERO; - wire [31:0] execute_BRANCH_CALC; - wire decode_MEMORY_STORE; - wire [31:0] memory_MEMORY_READ_DATA; - wire `EnvCtrlEnum_defaultEncoding_type _zz_13_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_14_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_15_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_16_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_17_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_18_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_19_; - wire decode_CSR_READ_OPCODE; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; - wire decode_IS_RS2_SIGNED; - wire execute_BRANCH_DO; - wire decode_IS_MUL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_23_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_24_; - wire decode_IS_RS1_SIGNED; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire decode_PREDICTION_HAD_BRANCHED2; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; - wire _zz_25_; - wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_MUL; - wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire memory_IS_MUL; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27_; - wire _zz_28_; - wire _zz_29_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_30_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_31_; - wire [31:0] execute_PC; - wire execute_PREDICTION_HAD_BRANCHED2; - wire _zz_32_; - wire [31:0] execute_RS1; - wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_33_; - wire _zz_34_; - wire _zz_35_; - wire decode_RS2_USE; - wire decode_RS1_USE; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - reg [31:0] _zz_36_; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] decode_RS2; - reg [31:0] decode_RS1; - reg [31:0] _zz_37_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_38_; - wire _zz_39_; - wire [31:0] _zz_40_; - wire [31:0] _zz_41_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_42_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_43_; - wire [31:0] _zz_44_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_45_; - wire [31:0] _zz_46_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_47_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_48_; - wire [31:0] _zz_49_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_50_; - wire [31:0] _zz_51_; - wire _zz_52_; - reg _zz_53_; - wire [31:0] _zz_54_; - wire [31:0] _zz_55_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_56_; - wire _zz_57_; - wire _zz_58_; - wire _zz_59_; - wire _zz_60_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_61_; - wire _zz_62_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_63_; - wire _zz_64_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_65_; - wire _zz_66_; - wire _zz_67_; - wire _zz_68_; - wire `AluCtrlEnum_defaultEncoding_type _zz_69_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_70_; - wire _zz_71_; - wire _zz_72_; - wire _zz_73_; - wire _zz_74_; - wire _zz_75_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_76_; - wire _zz_77_; - wire _zz_78_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_79_; - wire _zz_80_; - wire writeBack_MEMORY_STORE; - reg [31:0] _zz_81_; - wire writeBack_MEMORY_ENABLE; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP_physicalAddress; - wire memory_MMU_RSP_isIoAccess; - wire memory_MMU_RSP_allowRead; - wire memory_MMU_RSP_allowWrite; - wire memory_MMU_RSP_allowExecute; - wire memory_MMU_RSP_exception; - wire memory_MMU_RSP_refilling; - wire [31:0] memory_PC; - wire memory_ALIGNEMENT_FAULT; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_STORE; - wire memory_MEMORY_ENABLE; - wire [31:0] _zz_82_; - wire [31:0] _zz_83_; - wire _zz_84_; - wire _zz_85_; - wire _zz_86_; - wire _zz_87_; - wire _zz_88_; - wire _zz_89_; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP_physicalAddress; - wire execute_MMU_RSP_isIoAccess; - wire execute_MMU_RSP_allowRead; - wire execute_MMU_RSP_allowWrite; - wire execute_MMU_RSP_allowExecute; - wire execute_MMU_RSP_exception; - wire execute_MMU_RSP_refilling; - wire _zz_90_; - wire [31:0] execute_SRC_ADD; - wire [1:0] _zz_91_; - wire [31:0] execute_RS2; - wire [31:0] execute_INSTRUCTION; - wire execute_MEMORY_STORE; - wire execute_MEMORY_ENABLE; - wire execute_ALIGNEMENT_FAULT; - wire _zz_92_; - wire decode_MEMORY_ENABLE; - wire decode_FLUSH_ALL; - reg IBusCachedPlugin_rsp_issueDetected; - reg _zz_93_; - reg _zz_94_; - reg _zz_95_; - wire [31:0] _zz_96_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_97_; - wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_98_; - reg [31:0] _zz_99_; - wire [31:0] decode_PC; - wire [31:0] _zz_100_; - wire [31:0] _zz_101_; - wire [31:0] _zz_102_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - wire decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - wire writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - wire writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusCachedPlugin_fetcherHalt; - reg IBusCachedPlugin_fetcherflushIt; - reg IBusCachedPlugin_incomingInstruction; - wire IBusCachedPlugin_predictionJumpInterface_valid; - (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; - reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; - wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; - wire IBusCachedPlugin_pcValids_0; - wire IBusCachedPlugin_pcValids_1; - wire IBusCachedPlugin_pcValids_2; - wire IBusCachedPlugin_pcValids_3; - wire IBusCachedPlugin_redoBranch_valid; - wire [31:0] IBusCachedPlugin_redoBranch_payload; - reg IBusCachedPlugin_decodeExceptionPort_valid; - reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; - wire IBusCachedPlugin_mmuBus_cmd_isValid; - wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; - wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; - wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; - wire IBusCachedPlugin_mmuBus_rsp_allowRead; - wire IBusCachedPlugin_mmuBus_rsp_allowWrite; - wire IBusCachedPlugin_mmuBus_rsp_allowExecute; - wire IBusCachedPlugin_mmuBus_rsp_exception; - wire IBusCachedPlugin_mmuBus_rsp_refilling; - wire IBusCachedPlugin_mmuBus_end; - wire IBusCachedPlugin_mmuBus_busy; - reg DBusSimplePlugin_memoryExceptionPort_valid; - reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; - wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_isValid; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; - reg IBusCachedPlugin_injectionPort_valid; - reg IBusCachedPlugin_injectionPort_ready; - wire [31:0] IBusCachedPlugin_injectionPort_payload; - wire IBusCachedPlugin_jump_pcLoad_valid; - wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_103_; - wire [4:0] _zz_104_; - wire _zz_105_; - wire _zz_106_; - wire _zz_107_; - wire _zz_108_; - wire IBusCachedPlugin_fetchPc_output_valid; - wire IBusCachedPlugin_fetchPc_output_ready; - wire [31:0] IBusCachedPlugin_fetchPc_output_payload; - reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusCachedPlugin_fetchPc_corrected; - reg IBusCachedPlugin_fetchPc_pcRegPropagate; - reg IBusCachedPlugin_fetchPc_booted; - reg IBusCachedPlugin_fetchPc_inc; - reg [31:0] IBusCachedPlugin_fetchPc_pc; - wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_0_halt; - wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; - wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; - wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; - wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; - reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire IBusCachedPlugin_iBusRsp_stages_1_inputSample; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; - wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; - wire _zz_109_; - wire _zz_110_; - wire _zz_111_; - wire _zz_112_; - wire _zz_113_; - reg _zz_114_; - wire _zz_115_; - reg _zz_116_; - reg [31:0] _zz_117_; - reg IBusCachedPlugin_iBusRsp_readyForError; - wire IBusCachedPlugin_iBusRsp_decodeInput_valid; - wire IBusCachedPlugin_iBusRsp_decodeInput_ready; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; - wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; - reg IBusCachedPlugin_injector_nextPcCalc_valids_0; - reg IBusCachedPlugin_injector_nextPcCalc_valids_1; - reg IBusCachedPlugin_injector_nextPcCalc_valids_2; - reg IBusCachedPlugin_injector_nextPcCalc_valids_3; - reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - reg IBusCachedPlugin_injector_decodeRemoved; - wire _zz_118_; - reg [18:0] _zz_119_; - wire _zz_120_; - reg [10:0] _zz_121_; - wire _zz_122_; - reg [18:0] _zz_123_; - reg _zz_124_; - wire _zz_125_; - reg [10:0] _zz_126_; - wire _zz_127_; - reg [18:0] _zz_128_; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - reg [31:0] iBus_cmd_payload_address; - wire [2:0] iBus_cmd_payload_size; - wire iBus_rsp_valid; - wire [31:0] iBus_rsp_payload_data; - wire iBus_rsp_payload_error; - wire [31:0] _zz_129_; - reg [31:0] IBusCachedPlugin_rspCounter; - wire IBusCachedPlugin_s0_tightlyCoupledHit; - reg IBusCachedPlugin_s1_tightlyCoupledHit; - reg IBusCachedPlugin_s2_tightlyCoupledHit; - wire IBusCachedPlugin_rsp_iBusRspOutputHalt; - reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [1:0] dBus_cmd_payload_size; - wire dBus_rsp_ready; - wire dBus_rsp_error; - wire [31:0] dBus_rsp_data; - wire _zz_130_; - reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_131_; - reg [3:0] _zz_132_; - wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_133_; - reg [31:0] _zz_134_; - wire _zz_135_; - reg [31:0] _zz_136_; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [31:0] _zz_137_; - wire _zz_138_; - wire _zz_139_; - wire _zz_140_; - wire _zz_141_; - wire _zz_142_; - wire _zz_143_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_144_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_145_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_146_; - wire `AluCtrlEnum_defaultEncoding_type _zz_147_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_148_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_149_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_150_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_151_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_152_; - reg [31:0] _zz_153_; - wire _zz_154_; - reg [19:0] _zz_155_; - wire _zz_156_; - reg [19:0] _zz_157_; - reg [31:0] _zz_158_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - reg execute_LightShifterPlugin_isActive; - wire execute_LightShifterPlugin_isShift; - reg [4:0] execute_LightShifterPlugin_amplitudeReg; - wire [4:0] execute_LightShifterPlugin_amplitude; - wire [31:0] execute_LightShifterPlugin_shiftInput; - wire execute_LightShifterPlugin_done; - reg [31:0] _zz_159_; - reg _zz_160_; - reg _zz_161_; - wire _zz_162_; - reg _zz_163_; - reg [4:0] _zz_164_; - reg [31:0] _zz_165_; - wire _zz_166_; - wire _zz_167_; - wire _zz_168_; - wire _zz_169_; - wire _zz_170_; - wire _zz_171_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_172_; - reg _zz_173_; - reg _zz_174_; - wire _zz_175_; - reg [19:0] _zz_176_; - wire _zz_177_; - reg [10:0] _zz_178_; - wire _zz_179_; - reg [18:0] _zz_180_; - reg _zz_181_; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_182_; - reg [19:0] _zz_183_; - wire _zz_184_; - reg [10:0] _zz_185_; - wire _zz_186_; - reg [18:0] _zz_187_; - wire [31:0] execute_BranchPlugin_branchAdder; - wire [1:0] CsrPlugin_misa_base; - wire [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_188_; - wire _zz_189_; - wire _zz_190_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_191_; - wire _zz_192_; - wire [1:0] _zz_193_; - wire _zz_194_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - reg memory_MulDivIterativePlugin_mul_counter_willIncrement; - reg memory_MulDivIterativePlugin_mul_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; - wire memory_MulDivIterativePlugin_mul_willOverflowIfInc; - wire memory_MulDivIterativePlugin_mul_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_needRevert; - reg memory_MulDivIterativePlugin_div_counter_willIncrement; - reg memory_MulDivIterativePlugin_div_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_div_counter_value; - wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_div_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_done; - reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_195_; - wire [32:0] _zz_196_; - wire [32:0] _zz_197_; - wire [31:0] _zz_198_; - wire _zz_199_; - wire _zz_200_; - reg [32:0] _zz_201_; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_202_; - wire [31:0] _zz_203_; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_204_; - reg DebugPlugin_resetIt_regNext; - reg decode_to_execute_PREDICTION_HAD_BRANCHED2; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg decode_to_execute_IS_RS1_SIGNED; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; - reg [31:0] execute_to_memory_MMU_RSP_physicalAddress; - reg execute_to_memory_MMU_RSP_isIoAccess; - reg execute_to_memory_MMU_RSP_allowRead; - reg execute_to_memory_MMU_RSP_allowWrite; - reg execute_to_memory_MMU_RSP_allowExecute; - reg execute_to_memory_MMU_RSP_exception; - reg execute_to_memory_MMU_RSP_refilling; - reg execute_to_memory_BRANCH_DO; - reg decode_to_execute_IS_RS2_SIGNED; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg decode_to_execute_CSR_READ_OPCODE; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg [31:0] decode_to_execute_RS2; - reg decode_to_execute_MEMORY_STORE; - reg execute_to_memory_MEMORY_STORE; - reg memory_to_writeBack_MEMORY_STORE; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg execute_to_memory_MMU_FAULT; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_ALIGNEMENT_FAULT; - reg [31:0] decode_to_execute_RS1; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg decode_to_execute_DO_EBREAK; - reg decode_to_execute_IS_CSR; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg [2:0] _zz_205_; - reg [2:0] _zz_206_; - reg _zz_207_; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - wire dBus_cmd_halfPipe_valid; - wire dBus_cmd_halfPipe_ready; - wire dBus_cmd_halfPipe_payload_wr; - wire [31:0] dBus_cmd_halfPipe_payload_address; - wire [31:0] dBus_cmd_halfPipe_payload_data; - wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_208_; + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_156; + wire _zz_157; + wire _zz_158; + wire _zz_159; + wire _zz_160; + wire _zz_161; + wire _zz_162; + wire _zz_163; + reg _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_168; + wire _zz_169; + wire _zz_170; + wire _zz_171; + wire _zz_172; + wire _zz_173; + wire _zz_174; + wire _zz_175; + wire _zz_176; + wire _zz_177; + wire _zz_178; + wire _zz_179; + wire _zz_180; + wire _zz_181; + wire _zz_182; + wire _zz_183; + wire _zz_184; + wire _zz_185; + wire _zz_186; + wire _zz_187; + wire [1:0] _zz_188; + wire _zz_189; + wire _zz_190; + wire _zz_191; + wire _zz_192; + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + wire [5:0] _zz_201; + wire _zz_202; + wire _zz_203; + wire _zz_204; + wire _zz_205; + wire _zz_206; + wire _zz_207; + wire _zz_208; + wire [1:0] _zz_209; + wire _zz_210; + wire [0:0] _zz_211; + wire [0:0] _zz_212; + wire [0:0] _zz_213; + wire [0:0] _zz_214; + wire [0:0] _zz_215; + wire [0:0] _zz_216; + wire [0:0] _zz_217; + wire [0:0] _zz_218; + wire [0:0] _zz_219; + wire [0:0] _zz_220; + wire [0:0] _zz_221; + wire [0:0] _zz_222; + wire [0:0] _zz_223; + wire [0:0] _zz_224; + wire [0:0] _zz_225; + wire [0:0] _zz_226; + wire [0:0] _zz_227; + wire [3:0] _zz_228; + wire [2:0] _zz_229; + wire [31:0] _zz_230; + wire [11:0] _zz_231; + wire [31:0] _zz_232; + wire [19:0] _zz_233; + wire [11:0] _zz_234; + wire [31:0] _zz_235; + wire [31:0] _zz_236; + wire [19:0] _zz_237; + wire [11:0] _zz_238; + wire [2:0] _zz_239; + wire [0:0] _zz_240; + wire [2:0] _zz_241; + wire [4:0] _zz_242; + wire [11:0] _zz_243; + wire [11:0] _zz_244; + wire [31:0] _zz_245; + wire [31:0] _zz_246; + wire [31:0] _zz_247; + wire [31:0] _zz_248; + wire [31:0] _zz_249; + wire [31:0] _zz_250; + wire [31:0] _zz_251; + wire [31:0] _zz_252; + wire [32:0] _zz_253; + wire [11:0] _zz_254; + wire [19:0] _zz_255; + wire [11:0] _zz_256; + wire [31:0] _zz_257; + wire [31:0] _zz_258; + wire [31:0] _zz_259; + wire [11:0] _zz_260; + wire [19:0] _zz_261; + wire [11:0] _zz_262; + wire [2:0] _zz_263; + wire [1:0] _zz_264; + wire [1:0] _zz_265; + wire [1:0] _zz_266; + wire [1:0] _zz_267; + wire [0:0] _zz_268; + wire [5:0] _zz_269; + wire [33:0] _zz_270; + wire [32:0] _zz_271; + wire [33:0] _zz_272; + wire [32:0] _zz_273; + wire [33:0] _zz_274; + wire [32:0] _zz_275; + wire [0:0] _zz_276; + wire [5:0] _zz_277; + wire [32:0] _zz_278; + wire [31:0] _zz_279; + wire [31:0] _zz_280; + wire [32:0] _zz_281; + wire [32:0] _zz_282; + wire [32:0] _zz_283; + wire [32:0] _zz_284; + wire [0:0] _zz_285; + wire [32:0] _zz_286; + wire [0:0] _zz_287; + wire [32:0] _zz_288; + wire [0:0] _zz_289; + wire [31:0] _zz_290; + wire [0:0] _zz_291; + wire [0:0] _zz_292; + wire [0:0] _zz_293; + wire [0:0] _zz_294; + wire [0:0] _zz_295; + wire [0:0] _zz_296; + wire [26:0] _zz_297; + wire _zz_298; + wire _zz_299; + wire [1:0] _zz_300; + wire [31:0] _zz_301; + wire [31:0] _zz_302; + wire [31:0] _zz_303; + wire _zz_304; + wire [0:0] _zz_305; + wire [12:0] _zz_306; + wire [31:0] _zz_307; + wire [31:0] _zz_308; + wire [31:0] _zz_309; + wire _zz_310; + wire [0:0] _zz_311; + wire [6:0] _zz_312; + wire [31:0] _zz_313; + wire [31:0] _zz_314; + wire [31:0] _zz_315; + wire _zz_316; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire _zz_319; + wire _zz_320; + wire _zz_321; + wire [31:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [0:0] _zz_325; + wire [0:0] _zz_326; + wire [2:0] _zz_327; + wire [2:0] _zz_328; + wire _zz_329; + wire [0:0] _zz_330; + wire [25:0] _zz_331; + wire [31:0] _zz_332; + wire [31:0] _zz_333; + wire [31:0] _zz_334; + wire _zz_335; + wire [1:0] _zz_336; + wire [1:0] _zz_337; + wire _zz_338; + wire [0:0] _zz_339; + wire [21:0] _zz_340; + wire [31:0] _zz_341; + wire [31:0] _zz_342; + wire [31:0] _zz_343; + wire [31:0] _zz_344; + wire _zz_345; + wire _zz_346; + wire [1:0] _zz_347; + wire [1:0] _zz_348; + wire _zz_349; + wire [0:0] _zz_350; + wire [18:0] _zz_351; + wire [31:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; + wire [31:0] _zz_355; + wire _zz_356; + wire [0:0] _zz_357; + wire [0:0] _zz_358; + wire [0:0] _zz_359; + wire [1:0] _zz_360; + wire [0:0] _zz_361; + wire [0:0] _zz_362; + wire _zz_363; + wire [0:0] _zz_364; + wire [15:0] _zz_365; + wire [31:0] _zz_366; + wire [31:0] _zz_367; + wire [31:0] _zz_368; + wire [31:0] _zz_369; + wire [31:0] _zz_370; + wire [31:0] _zz_371; + wire [31:0] _zz_372; + wire _zz_373; + wire _zz_374; + wire [31:0] _zz_375; + wire [31:0] _zz_376; + wire [1:0] _zz_377; + wire [1:0] _zz_378; + wire _zz_379; + wire [0:0] _zz_380; + wire [13:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire [31:0] _zz_384; + wire [31:0] _zz_385; + wire _zz_386; + wire _zz_387; + wire [0:0] _zz_388; + wire [1:0] _zz_389; + wire [0:0] _zz_390; + wire [0:0] _zz_391; + wire _zz_392; + wire [0:0] _zz_393; + wire [10:0] _zz_394; + wire [31:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire [31:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; + wire [31:0] _zz_402; + wire [0:0] _zz_403; + wire [1:0] _zz_404; + wire [5:0] _zz_405; + wire [5:0] _zz_406; + wire _zz_407; + wire [0:0] _zz_408; + wire [7:0] _zz_409; + wire [31:0] _zz_410; + wire [31:0] _zz_411; + wire [31:0] _zz_412; + wire [31:0] _zz_413; + wire _zz_414; + wire [0:0] _zz_415; + wire [2:0] _zz_416; + wire _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire [1:0] _zz_420; + wire [1:0] _zz_421; + wire _zz_422; + wire [0:0] _zz_423; + wire [4:0] _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire [31:0] _zz_427; + wire _zz_428; + wire [0:0] _zz_429; + wire [0:0] _zz_430; + wire [31:0] _zz_431; + wire [31:0] _zz_432; + wire [31:0] _zz_433; + wire _zz_434; + wire _zz_435; + wire _zz_436; + wire [3:0] _zz_437; + wire [3:0] _zz_438; + wire _zz_439; + wire [0:0] _zz_440; + wire [2:0] _zz_441; + wire [31:0] _zz_442; + wire [31:0] _zz_443; + wire [31:0] _zz_444; + wire [31:0] _zz_445; + wire [31:0] _zz_446; + wire [31:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire _zz_450; + wire [0:0] _zz_451; + wire [1:0] _zz_452; + wire _zz_453; + wire [2:0] _zz_454; + wire [2:0] _zz_455; + wire _zz_456; + wire [0:0] _zz_457; + wire [0:0] _zz_458; + wire [31:0] _zz_459; + wire [31:0] _zz_460; + wire [31:0] _zz_461; + wire [31:0] _zz_462; + wire [31:0] _zz_463; + wire [31:0] _zz_464; + wire [31:0] _zz_465; + wire _zz_466; + wire _zz_467; + wire _zz_468; + wire [0:0] _zz_469; + wire [0:0] _zz_470; + wire _zz_471; + wire _zz_472; + wire _zz_473; + wire _zz_474; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_DIV; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_13; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_16; + wire `Src2CtrlEnum_defaultEncoding_type _zz_17; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_19; + wire `AluCtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_22; + wire `Src1CtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_MUL; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire memory_IS_MUL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_25; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_26; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + wire [31:0] execute_RS1; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_28; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + reg [31:0] _zz_29; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + reg [31:0] _zz_30; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_31; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_32; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_33; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_34; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_36; + wire [31:0] _zz_37; + wire _zz_38; + reg _zz_39; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_40; + wire `BranchCtrlEnum_defaultEncoding_type _zz_41; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_42; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; + wire `Src2CtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_defaultEncoding_type _zz_45; + wire `Src1CtrlEnum_defaultEncoding_type _zz_46; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_47; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP2_physicalAddress; + wire memory_MMU_RSP2_isIoAccess; + wire memory_MMU_RSP2_isPaging; + wire memory_MMU_RSP2_allowRead; + wire memory_MMU_RSP2_allowWrite; + wire memory_MMU_RSP2_allowExecute; + wire memory_MMU_RSP2_exception; + wire memory_MMU_RSP2_refilling; + wire memory_MMU_RSP2_bypassTranslation; + wire [31:0] memory_PC; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire execute_MMU_FAULT; + wire [31:0] execute_MMU_RSP2_physicalAddress; + wire execute_MMU_RSP2_isIoAccess; + wire execute_MMU_RSP2_isPaging; + wire execute_MMU_RSP2_allowRead; + wire execute_MMU_RSP2_allowWrite; + wire execute_MMU_RSP2_allowExecute; + wire execute_MMU_RSP2_exception; + wire execute_MMU_RSP2_refilling; + wire execute_MMU_RSP2_bypassTranslation; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_48; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_49; + reg [31:0] _zz_50; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire DBusSimplePlugin_mmuBus_cmd_0_isValid; + wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire DBusSimplePlugin_mmuBus_rsp_isPaging; + wire DBusSimplePlugin_mmuBus_rsp_allowRead; + wire DBusSimplePlugin_mmuBus_rsp_allowWrite; + wire DBusSimplePlugin_mmuBus_rsp_allowExecute; + wire DBusSimplePlugin_mmuBus_rsp_exception; + wire DBusSimplePlugin_mmuBus_rsp_refilling; + wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire DBusSimplePlugin_mmuBus_end; + wire DBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_redoBranch_valid; + wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_51; + wire [3:0] _zz_52; + wire _zz_53; + wire _zz_54; + wire _zz_55; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_56; + wire _zz_57; + wire _zz_58; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_59; + wire _zz_60; + reg _zz_61; + wire _zz_62; + reg _zz_63; + reg [31:0] _zz_64; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_65; + reg [18:0] _zz_66; + wire _zz_67; + reg [10:0] _zz_68; + wire _zz_69; + reg [18:0] _zz_70; + reg _zz_71; + wire _zz_72; + reg [10:0] _zz_73; + wire _zz_74; + reg [18:0] _zz_75; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_76; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire _zz_77; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_78; + reg [3:0] _zz_79; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_80; + reg [31:0] _zz_81; + wire _zz_82; + reg [31:0] _zz_83; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [31:0] _zz_84; + wire _zz_85; + wire _zz_86; + wire _zz_87; + wire _zz_88; + wire _zz_89; + wire _zz_90; + wire `Src1CtrlEnum_defaultEncoding_type _zz_91; + wire `AluCtrlEnum_defaultEncoding_type _zz_92; + wire `Src2CtrlEnum_defaultEncoding_type _zz_93; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_94; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_95; + wire `BranchCtrlEnum_defaultEncoding_type _zz_96; + wire `EnvCtrlEnum_defaultEncoding_type _zz_97; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_98; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_99; + reg [31:0] _zz_100; + wire _zz_101; + reg [19:0] _zz_102; + wire _zz_103; + reg [19:0] _zz_104; + reg [31:0] _zz_105; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_106; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire _zz_107; + wire _zz_108; + wire _zz_109; + wire _zz_110; + wire _zz_111; + wire _zz_112; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_113; + reg _zz_114; + reg _zz_115; + wire _zz_116; + reg [19:0] _zz_117; + wire _zz_118; + reg [10:0] _zz_119; + wire _zz_120; + reg [18:0] _zz_121; + reg _zz_122; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_123; + reg [19:0] _zz_124; + wire _zz_125; + reg [10:0] _zz_126; + wire _zz_127; + reg [18:0] _zz_128; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_129; + wire _zz_130; + wire _zz_131; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_132; + wire _zz_133; + wire [1:0] _zz_134; + wire _zz_135; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_mul_counter_willIncrement; + reg memory_MulDivIterativePlugin_mul_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; + wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire [31:0] _zz_136; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [31:0] _zz_137; + wire _zz_138; + wire _zz_139; + reg [32:0] _zz_140; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_141; + wire [31:0] _zz_142; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_143; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; + reg execute_to_memory_MMU_RSP2_isIoAccess; + reg execute_to_memory_MMU_RSP2_isPaging; + reg execute_to_memory_MMU_RSP2_allowRead; + reg execute_to_memory_MMU_RSP2_allowWrite; + reg execute_to_memory_MMU_RSP2_allowExecute; + reg execute_to_memory_MMU_RSP2_exception; + reg execute_to_memory_MMU_RSP2_refilling; + reg execute_to_memory_MMU_RSP2_bypassTranslation; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg [2:0] _zz_144; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_145; + reg [31:0] _zz_146; + reg [31:0] _zz_147; + reg [31:0] _zz_148; + reg [31:0] _zz_149; + reg [31:0] _zz_150; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [2:0] _zz_153; + reg _zz_154; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_155; `ifndef SYNTHESIS - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_1__string; - reg [95:0] _zz_2__string; - reg [95:0] _zz_3__string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_4__string; - reg [23:0] _zz_5__string; - reg [23:0] _zz_6__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_7__string; - reg [63:0] _zz_8__string; - reg [63:0] _zz_9__string; - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_10__string; - reg [39:0] _zz_11__string; - reg [39:0] _zz_12__string; - reg [39:0] _zz_13__string; - reg [39:0] _zz_14__string; - reg [39:0] _zz_15__string; - reg [39:0] _zz_16__string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_17__string; - reg [39:0] _zz_18__string; - reg [39:0] _zz_19__string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_20__string; - reg [71:0] _zz_21__string; - reg [71:0] _zz_22__string; - reg [31:0] _zz_23__string; - reg [31:0] _zz_24__string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] _zz_12_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_13_string; + reg [39:0] _zz_14_string; + reg [39:0] _zz_15_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_16_string; + reg [23:0] _zz_17_string; + reg [23:0] _zz_18_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_19_string; + reg [63:0] _zz_20_string; + reg [63:0] _zz_21_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_22_string; + reg [95:0] _zz_23_string; + reg [95:0] _zz_24_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_26__string; + reg [39:0] _zz_25_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_27__string; + reg [39:0] _zz_26_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_30__string; + reg [39:0] _zz_27_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_33__string; + reg [31:0] _zz_28_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_38__string; + reg [71:0] _zz_31_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_43__string; + reg [23:0] _zz_33_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_45__string; + reg [95:0] _zz_34_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_48__string; + reg [63:0] _zz_35_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_50__string; - reg [71:0] _zz_61__string; - reg [39:0] _zz_63__string; - reg [39:0] _zz_65__string; - reg [63:0] _zz_69__string; - reg [23:0] _zz_70__string; - reg [95:0] _zz_76__string; - reg [31:0] _zz_79__string; + reg [39:0] _zz_36_string; + reg [39:0] _zz_40_string; + reg [31:0] _zz_41_string; + reg [71:0] _zz_42_string; + reg [39:0] _zz_43_string; + reg [23:0] _zz_44_string; + reg [63:0] _zz_45_string; + reg [95:0] _zz_46_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_97__string; - reg [31:0] _zz_144__string; - reg [95:0] _zz_145__string; - reg [23:0] _zz_146__string; - reg [63:0] _zz_147__string; - reg [39:0] _zz_148__string; - reg [39:0] _zz_149__string; - reg [71:0] _zz_150__string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_48_string; + reg [95:0] _zz_91_string; + reg [63:0] _zz_92_string; + reg [23:0] _zz_93_string; + reg [39:0] _zz_94_string; + reg [71:0] _zz_95_string; + reg [31:0] _zz_96_string; + reg [39:0] _zz_97_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [39:0] decode_to_execute_ENV_CTRL_string; reg [39:0] execute_to_memory_ENV_CTRL_string; reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; `endif (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_221_ = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_222_ = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_223_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_224_ = 1'b1; - assign _zz_225_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_226_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_227_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); - assign _zz_228_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_229_ = ((_zz_214_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_93_)); - assign _zz_230_ = ((_zz_214_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_94_)); - assign _zz_231_ = ((_zz_214_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_95_)); - assign _zz_232_ = ((_zz_214_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! 1'b0)); - assign _zz_233_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_234_ = (! execute_arbitration_isStuckByOthers); - assign _zz_235_ = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_236_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0); - assign _zz_237_ = (! memory_MulDivIterativePlugin_mul_willOverflowIfInc); - assign _zz_238_ = (! memory_MulDivIterativePlugin_div_done); - assign _zz_239_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00)); - assign _zz_240_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_241_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_242_ = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_243_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_244_ = (! IBusCachedPlugin_iBusRsp_readyForError); - assign _zz_245_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_246_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_247_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_248_ = (1'b0 || (! 1'b1)); - assign _zz_249_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_250_ = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_251_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_252_ = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_253_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_254_ = (! memory_arbitration_isStuck); - assign _zz_255_ = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_256_ = (iBus_cmd_valid || (_zz_206_ != (3'b000))); - assign _zz_257_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_258_ = ((_zz_188_ && 1'b1) && (! 1'b0)); - assign _zz_259_ = ((_zz_189_ && 1'b1) && (! 1'b0)); - assign _zz_260_ = ((_zz_190_ && 1'b1) && (! 1'b0)); - assign _zz_261_ = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_262_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_263_ = execute_INSTRUCTION[13]; - assign _zz_264_ = (_zz_103_ - (5'b00001)); - assign _zz_265_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; - assign _zz_266_ = {29'd0, _zz_265_}; - assign _zz_267_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_268_ = {{_zz_119_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_269_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_270_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_271_ = {{_zz_121_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_272_ = {{_zz_123_,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_273_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_274_ = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_275_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100)); - assign _zz_276_ = _zz_137_[2 : 2]; - assign _zz_277_ = _zz_137_[3 : 3]; - assign _zz_278_ = _zz_137_[6 : 6]; - assign _zz_279_ = _zz_137_[7 : 7]; - assign _zz_280_ = _zz_137_[8 : 8]; - assign _zz_281_ = _zz_137_[9 : 9]; - assign _zz_282_ = _zz_137_[10 : 10]; - assign _zz_283_ = _zz_137_[15 : 15]; - assign _zz_284_ = _zz_137_[16 : 16]; - assign _zz_285_ = _zz_137_[17 : 17]; - assign _zz_286_ = _zz_137_[20 : 20]; - assign _zz_287_ = _zz_137_[24 : 24]; - assign _zz_288_ = _zz_137_[27 : 27]; - assign _zz_289_ = _zz_137_[28 : 28]; - assign _zz_290_ = _zz_137_[29 : 29]; - assign _zz_291_ = _zz_137_[30 : 30]; - assign _zz_292_ = _zz_137_[31 : 31]; - assign _zz_293_ = execute_SRC_LESS; - assign _zz_294_ = (3'b100); - assign _zz_295_ = execute_INSTRUCTION[19 : 15]; - assign _zz_296_ = execute_INSTRUCTION[31 : 20]; - assign _zz_297_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_298_ = ($signed(_zz_299_) + $signed(_zz_302_)); - assign _zz_299_ = ($signed(_zz_300_) + $signed(_zz_301_)); - assign _zz_300_ = execute_SRC1; - assign _zz_301_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_302_ = (execute_SRC_USE_SUB_LESS ? _zz_303_ : _zz_304_); - assign _zz_303_ = (32'b00000000000000000000000000000001); - assign _zz_304_ = (32'b00000000000000000000000000000000); - assign _zz_305_ = (_zz_306_ >>> 1); - assign _zz_306_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_307_ = execute_INSTRUCTION[31 : 20]; - assign _zz_308_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_309_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_310_ = {_zz_176_,execute_INSTRUCTION[31 : 20]}; - assign _zz_311_ = {{_zz_178_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_312_ = {{_zz_180_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_313_ = execute_INSTRUCTION[31 : 20]; - assign _zz_314_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_315_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_316_ = (3'b100); - assign _zz_317_ = (_zz_191_ & (~ _zz_318_)); - assign _zz_318_ = (_zz_191_ - (2'b01)); - assign _zz_319_ = (_zz_193_ & (~ _zz_320_)); - assign _zz_320_ = (_zz_193_ - (2'b01)); - assign _zz_321_ = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_322_ = {5'd0, _zz_321_}; - assign _zz_323_ = (_zz_325_ + _zz_327_); - assign _zz_324_ = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : (33'b000000000000000000000000000000000)); - assign _zz_325_ = {{1{_zz_324_[32]}}, _zz_324_}; - assign _zz_326_ = _zz_328_; - assign _zz_327_ = {{1{_zz_326_[32]}}, _zz_326_}; - assign _zz_328_ = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_329_ = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_330_ = {5'd0, _zz_329_}; - assign _zz_331_ = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_332_ = {_zz_195_,(! _zz_197_[32])}; - assign _zz_333_ = _zz_197_[31:0]; - assign _zz_334_ = _zz_196_[31:0]; - assign _zz_335_ = _zz_336_; - assign _zz_336_ = _zz_337_; - assign _zz_337_ = ({1'b0,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_198_) : _zz_198_)} + _zz_339_); - assign _zz_338_ = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_339_ = {32'd0, _zz_338_}; - assign _zz_340_ = _zz_200_; - assign _zz_341_ = {32'd0, _zz_340_}; - assign _zz_342_ = _zz_199_; - assign _zz_343_ = {31'd0, _zz_342_}; - assign _zz_344_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_345_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_346_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_347_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_348_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_349_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_350_ = (iBus_cmd_payload_address >>> 5); - assign _zz_351_ = ({3'd0,_zz_208_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - assign _zz_352_ = 1'b1; - assign _zz_353_ = 1'b1; - assign _zz_354_ = {_zz_106_,{_zz_108_,_zz_107_}}; - assign _zz_355_ = decode_INSTRUCTION[31]; - assign _zz_356_ = decode_INSTRUCTION[31]; - assign _zz_357_ = decode_INSTRUCTION[7]; - assign _zz_358_ = (32'b00000010000000000100000001110100); - assign _zz_359_ = (decode_INSTRUCTION & (32'b00000000000000000001000001001000)); - assign _zz_360_ = (32'b00000000000000000001000000001000); - assign _zz_361_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); - assign _zz_362_ = {(_zz_367_ == _zz_368_),{_zz_369_,{_zz_370_,_zz_371_}}}; - assign _zz_363_ = (4'b0000); - assign _zz_364_ = ({_zz_372_,_zz_373_} != (2'b00)); - assign _zz_365_ = ({_zz_374_,_zz_375_} != (2'b00)); - assign _zz_366_ = {(_zz_376_ != _zz_377_),{_zz_378_,{_zz_379_,_zz_380_}}}; - assign _zz_367_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_368_ = (32'b00000000000000000000000000000000); - assign _zz_369_ = ((decode_INSTRUCTION & _zz_381_) == (32'b00000000000000000000000000000000)); - assign _zz_370_ = (_zz_382_ == _zz_383_); - assign _zz_371_ = (_zz_384_ == _zz_385_); - assign _zz_372_ = ((decode_INSTRUCTION & _zz_386_) == (32'b00000000000000000001000001010000)); - assign _zz_373_ = ((decode_INSTRUCTION & _zz_387_) == (32'b00000000000000000010000001010000)); - assign _zz_374_ = (_zz_388_ == _zz_389_); - assign _zz_375_ = (_zz_390_ == _zz_391_); - assign _zz_376_ = {_zz_392_,{_zz_393_,_zz_394_}}; - assign _zz_377_ = (3'b000); - assign _zz_378_ = ({_zz_395_,_zz_396_} != (6'b000000)); - assign _zz_379_ = (_zz_397_ != _zz_398_); - assign _zz_380_ = {_zz_399_,{_zz_400_,_zz_401_}}; - assign _zz_381_ = (32'b00000000000000000000000000011000); - assign _zz_382_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); - assign _zz_383_ = (32'b00000000000000000010000000000000); - assign _zz_384_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); - assign _zz_385_ = (32'b00000000000000000001000000000000); - assign _zz_386_ = (32'b00000000000000000001000001010000); - assign _zz_387_ = (32'b00000000000000000010000001010000); - assign _zz_388_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_389_ = (32'b00000000000000000101000000010000); - assign _zz_390_ = (decode_INSTRUCTION & (32'b00000010000000000111000001100100)); - assign _zz_391_ = (32'b00000000000000000101000000100000); - assign _zz_392_ = ((decode_INSTRUCTION & _zz_402_) == (32'b01000000000000000001000000010000)); - assign _zz_393_ = (_zz_403_ == _zz_404_); - assign _zz_394_ = (_zz_405_ == _zz_406_); - assign _zz_395_ = _zz_138_; - assign _zz_396_ = {_zz_407_,{_zz_408_,_zz_409_}}; - assign _zz_397_ = (_zz_410_ == _zz_411_); - assign _zz_398_ = (1'b0); - assign _zz_399_ = (_zz_412_ != (1'b0)); - assign _zz_400_ = (_zz_413_ != _zz_414_); - assign _zz_401_ = {_zz_415_,{_zz_416_,_zz_417_}}; - assign _zz_402_ = (32'b01000000000000000011000001010100); - assign _zz_403_ = (decode_INSTRUCTION & (32'b00000000000000000111000000110100)); - assign _zz_404_ = (32'b00000000000000000001000000010000); - assign _zz_405_ = (decode_INSTRUCTION & (32'b00000010000000000111000001010100)); - assign _zz_406_ = (32'b00000000000000000001000000010000); - assign _zz_407_ = ((decode_INSTRUCTION & _zz_418_) == (32'b00000000000000000001000000010000)); - assign _zz_408_ = (_zz_419_ == _zz_420_); - assign _zz_409_ = {_zz_421_,{_zz_422_,_zz_423_}}; - assign _zz_410_ = (decode_INSTRUCTION & (32'b00010000000100000011000001010000)); - assign _zz_411_ = (32'b00000000000000000000000001010000); - assign _zz_412_ = ((decode_INSTRUCTION & _zz_424_) == (32'b00010000000000000000000001010000)); - assign _zz_413_ = {_zz_425_,{_zz_426_,_zz_427_}}; - assign _zz_414_ = (3'b000); - assign _zz_415_ = ({_zz_428_,_zz_429_} != (3'b000)); - assign _zz_416_ = (_zz_430_ != _zz_431_); - assign _zz_417_ = {_zz_432_,{_zz_433_,_zz_434_}}; - assign _zz_418_ = (32'b00000000000000000001000000010000); - assign _zz_419_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_420_ = (32'b00000000000000000010000000010000); - assign _zz_421_ = ((decode_INSTRUCTION & _zz_435_) == (32'b00000000000000000000000000010000)); - assign _zz_422_ = (_zz_436_ == _zz_437_); - assign _zz_423_ = (_zz_438_ == _zz_439_); - assign _zz_424_ = (32'b00010000010000000011000001010000); - assign _zz_425_ = ((decode_INSTRUCTION & _zz_440_) == (32'b00000000000000000000000001000000)); - assign _zz_426_ = (_zz_441_ == _zz_442_); - assign _zz_427_ = (_zz_443_ == _zz_444_); - assign _zz_428_ = _zz_142_; - assign _zz_429_ = {_zz_445_,_zz_446_}; - assign _zz_430_ = (_zz_447_ == _zz_448_); - assign _zz_431_ = (1'b0); - assign _zz_432_ = (_zz_143_ != (1'b0)); - assign _zz_433_ = (_zz_449_ != _zz_450_); - assign _zz_434_ = {_zz_451_,{_zz_452_,_zz_453_}}; - assign _zz_435_ = (32'b00000000000000000000000001010000); - assign _zz_436_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); - assign _zz_437_ = (32'b00000000000000000000000000000100); - assign _zz_438_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); - assign _zz_439_ = (32'b00000000000000000000000000000000); - assign _zz_440_ = (32'b00000000000000000000000001010000); - assign _zz_441_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000)); - assign _zz_442_ = (32'b00000000000000000000000000000000); - assign _zz_443_ = (decode_INSTRUCTION & (32'b00000000000100000011000001000000)); - assign _zz_444_ = (32'b00000000000000000000000001000000); - assign _zz_445_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110000)) == (32'b00000000000000000000000000010000)); - assign _zz_446_ = ((decode_INSTRUCTION & (32'b00000010000000000000000001100000)) == (32'b00000000000000000000000000100000)); - assign _zz_447_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); - assign _zz_448_ = (32'b00000000000000000001000000000000); - assign _zz_449_ = ((decode_INSTRUCTION & _zz_454_) == (32'b00000000000000000000000000000000)); - assign _zz_450_ = (1'b0); - assign _zz_451_ = ({_zz_140_,{_zz_455_,_zz_456_}} != (3'b000)); - assign _zz_452_ = ({_zz_457_,_zz_458_} != (3'b000)); - assign _zz_453_ = {(_zz_459_ != _zz_460_),{_zz_461_,{_zz_462_,_zz_463_}}}; - assign _zz_454_ = (32'b00000000000000000000000001011000); - assign _zz_455_ = _zz_143_; - assign _zz_456_ = _zz_139_; - assign _zz_457_ = ((decode_INSTRUCTION & _zz_464_) == (32'b00000000000000000000000001000000)); - assign _zz_458_ = {(_zz_465_ == _zz_466_),(_zz_467_ == _zz_468_)}; - assign _zz_459_ = {(_zz_469_ == _zz_470_),(_zz_471_ == _zz_472_)}; - assign _zz_460_ = (2'b00); - assign _zz_461_ = ((_zz_473_ == _zz_474_) != (1'b0)); - assign _zz_462_ = ({_zz_475_,_zz_476_} != (2'b00)); - assign _zz_463_ = {(_zz_477_ != _zz_478_),{_zz_479_,{_zz_480_,_zz_481_}}}; - assign _zz_464_ = (32'b00000000000000000000000001000100); - assign _zz_465_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); - assign _zz_466_ = (32'b00000000000000000010000000010000); - assign _zz_467_ = (decode_INSTRUCTION & (32'b01000000000000000100000000110100)); - assign _zz_468_ = (32'b01000000000000000000000000110000); - assign _zz_469_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); - assign _zz_470_ = (32'b00000000000000000110000000010000); - assign _zz_471_ = (decode_INSTRUCTION & (32'b00000000000000000101000000010100)); - assign _zz_472_ = (32'b00000000000000000100000000010000); - assign _zz_473_ = (decode_INSTRUCTION & (32'b00000000000000000110000000010100)); - assign _zz_474_ = (32'b00000000000000000010000000010000); - assign _zz_475_ = _zz_142_; - assign _zz_476_ = ((decode_INSTRUCTION & _zz_482_) == (32'b00000000000000000000000000100000)); - assign _zz_477_ = {_zz_142_,(_zz_483_ == _zz_484_)}; - assign _zz_478_ = (2'b00); - assign _zz_479_ = ({_zz_485_,{_zz_486_,_zz_487_}} != (3'b000)); - assign _zz_480_ = (_zz_488_ != (1'b0)); - assign _zz_481_ = {(_zz_489_ != _zz_490_),{_zz_491_,{_zz_492_,_zz_493_}}}; - assign _zz_482_ = (32'b00000000000000000000000001110000); - assign _zz_483_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_484_ = (32'b00000000000000000000000000000000); - assign _zz_485_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); - assign _zz_486_ = ((decode_INSTRUCTION & _zz_494_) == (32'b00000000000000000001000000010000)); - assign _zz_487_ = ((decode_INSTRUCTION & _zz_495_) == (32'b00000000000000000001000000010000)); - assign _zz_488_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); - assign _zz_489_ = ((decode_INSTRUCTION & _zz_496_) == (32'b00000000000000000000000000100000)); - assign _zz_490_ = (1'b0); - assign _zz_491_ = ({_zz_497_,_zz_498_} != (2'b00)); - assign _zz_492_ = (_zz_499_ != (1'b0)); - assign _zz_493_ = {(_zz_500_ != _zz_501_),{_zz_502_,{_zz_503_,_zz_504_}}}; - assign _zz_494_ = (32'b00000000000000000011000000110100); - assign _zz_495_ = (32'b00000010000000000011000001010100); - assign _zz_496_ = (32'b00000000000000000000000000100000); - assign _zz_497_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)); - assign _zz_498_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_499_ = ((decode_INSTRUCTION & (32'b00000010000000000100000001100100)) == (32'b00000010000000000100000000100000)); - assign _zz_500_ = {(_zz_505_ == _zz_506_),_zz_141_}; - assign _zz_501_ = (2'b00); - assign _zz_502_ = ({_zz_507_,_zz_141_} != (2'b00)); - assign _zz_503_ = ({_zz_508_,_zz_509_} != (2'b00)); - assign _zz_504_ = {(_zz_510_ != _zz_511_),{_zz_512_,_zz_513_}}; - assign _zz_505_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100)); - assign _zz_506_ = (32'b00000000000000000000000000000100); - assign _zz_507_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); - assign _zz_508_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000)); - assign _zz_509_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100000)); - assign _zz_510_ = {_zz_140_,_zz_139_}; - assign _zz_511_ = (2'b00); - assign _zz_512_ = ({_zz_138_,((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100))} != (2'b00)); - assign _zz_513_ = (((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)) != (1'b0)); - assign _zz_514_ = (32'b00000000000000000001000001111111); - assign _zz_515_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_516_ = (32'b00000000000000000010000001110011); - assign _zz_517_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_518_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_519_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_520_) == (32'b00000000000000000000000000000011)),{(_zz_521_ == _zz_522_),{_zz_523_,{_zz_524_,_zz_525_}}}}}}; - assign _zz_520_ = (32'b00000000000000000101000001011111); - assign _zz_521_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_522_ = (32'b00000000000000000000000001100011); - assign _zz_523_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_524_ = ((decode_INSTRUCTION & (32'b11111100000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_525_ = {((decode_INSTRUCTION & (32'b11111100000000000011000001011111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & _zz_526_) == (32'b00000000000000000101000000110011)),{(_zz_527_ == _zz_528_),{_zz_529_,{_zz_530_,_zz_531_}}}}}}; - assign _zz_526_ = (32'b10111110000000000111000001111111); - assign _zz_527_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_528_ = (32'b00000000000000000000000000110011); - assign _zz_529_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_530_ = ((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)); - assign _zz_531_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); - assign _zz_532_ = execute_INSTRUCTION[31]; - assign _zz_533_ = execute_INSTRUCTION[31]; - assign _zz_534_ = execute_INSTRUCTION[7]; + + assign _zz_168 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_169 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_170 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_171 = 1'b1; + assign _zz_172 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_173 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_174 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_175 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_176 = ((_zz_161 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_177 = ((_zz_161 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_178 = ((_zz_161 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_179 = ((_zz_161 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_180 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_181 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_182 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_183 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_184 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_185 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_186 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_187 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_188 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_189 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_190 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_191 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_192 = (1'b0 || (! 1'b1)); + assign _zz_193 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_194 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_195 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_196 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_197 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_198 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_199 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_200 = (! memory_arbitration_isStuck); + assign _zz_201 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_202 = (iBus_cmd_valid || (_zz_153 != 3'b000)); + assign _zz_203 = (! execute_arbitration_isStuckByOthers); + assign _zz_204 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_205 = ((_zz_129 && 1'b1) && (! 1'b0)); + assign _zz_206 = ((_zz_130 && 1'b1) && (! 1'b0)); + assign _zz_207 = ((_zz_131 && 1'b1) && (! 1'b0)); + assign _zz_208 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_209 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_210 = execute_INSTRUCTION[13]; + assign _zz_211 = _zz_84[30 : 30]; + assign _zz_212 = _zz_84[29 : 29]; + assign _zz_213 = _zz_84[28 : 28]; + assign _zz_214 = _zz_84[27 : 27]; + assign _zz_215 = _zz_84[24 : 24]; + assign _zz_216 = _zz_84[16 : 16]; + assign _zz_217 = _zz_84[13 : 13]; + assign _zz_218 = _zz_84[12 : 12]; + assign _zz_219 = _zz_84[11 : 11]; + assign _zz_220 = _zz_84[31 : 31]; + assign _zz_221 = _zz_84[15 : 15]; + assign _zz_222 = _zz_84[5 : 5]; + assign _zz_223 = _zz_84[3 : 3]; + assign _zz_224 = _zz_84[19 : 19]; + assign _zz_225 = _zz_84[10 : 10]; + assign _zz_226 = _zz_84[4 : 4]; + assign _zz_227 = _zz_84[0 : 0]; + assign _zz_228 = (_zz_51 - 4'b0001); + assign _zz_229 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_230 = {29'd0, _zz_229}; + assign _zz_231 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_232 = {{_zz_66,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_233 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_234 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_235 = {{_zz_68,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_236 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_237 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_238 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_239 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_240 = execute_SRC_LESS; + assign _zz_241 = 3'b100; + assign _zz_242 = execute_INSTRUCTION[19 : 15]; + assign _zz_243 = execute_INSTRUCTION[31 : 20]; + assign _zz_244 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_245 = ($signed(_zz_246) + $signed(_zz_249)); + assign _zz_246 = ($signed(_zz_247) + $signed(_zz_248)); + assign _zz_247 = execute_SRC1; + assign _zz_248 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_249 = (execute_SRC_USE_SUB_LESS ? _zz_250 : _zz_251); + assign _zz_250 = 32'h00000001; + assign _zz_251 = 32'h0; + assign _zz_252 = (_zz_253 >>> 1); + assign _zz_253 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_254 = execute_INSTRUCTION[31 : 20]; + assign _zz_255 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_256 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_257 = {_zz_117,execute_INSTRUCTION[31 : 20]}; + assign _zz_258 = {{_zz_119,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_259 = {{_zz_121,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_260 = execute_INSTRUCTION[31 : 20]; + assign _zz_261 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_262 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_263 = 3'b100; + assign _zz_264 = (_zz_132 & (~ _zz_265)); + assign _zz_265 = (_zz_132 - 2'b01); + assign _zz_266 = (_zz_134 & (~ _zz_267)); + assign _zz_267 = (_zz_134 - 2'b01); + assign _zz_268 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_269 = {5'd0, _zz_268}; + assign _zz_270 = (_zz_272 + _zz_274); + assign _zz_271 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_272 = {{1{_zz_271[32]}}, _zz_271}; + assign _zz_273 = _zz_275; + assign _zz_274 = {{1{_zz_273[32]}}, _zz_273}; + assign _zz_275 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_276 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_277 = {5'd0, _zz_276}; + assign _zz_278 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_279 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_280 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_281 = {_zz_136,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_282 = _zz_283; + assign _zz_283 = _zz_284; + assign _zz_284 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_137) : _zz_137)} + _zz_286); + assign _zz_285 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_286 = {32'd0, _zz_285}; + assign _zz_287 = _zz_139; + assign _zz_288 = {32'd0, _zz_287}; + assign _zz_289 = _zz_138; + assign _zz_290 = {31'd0, _zz_289}; + assign _zz_291 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_292 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_293 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_294 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_295 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_296 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_297 = (iBus_cmd_payload_address >>> 5); + assign _zz_298 = 1'b1; + assign _zz_299 = 1'b1; + assign _zz_300 = {_zz_55,_zz_54}; + assign _zz_301 = 32'h0000107f; + assign _zz_302 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_303 = 32'h00002073; + assign _zz_304 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_305 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_306 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_307) == 32'h00000003),{(_zz_308 == _zz_309),{_zz_310,{_zz_311,_zz_312}}}}}}; + assign _zz_307 = 32'h0000505f; + assign _zz_308 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_309 = 32'h00000063; + assign _zz_310 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_311 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_312 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_313) == 32'h00005033),{(_zz_314 == _zz_315),{_zz_316,{_zz_317,_zz_318}}}}}}; + assign _zz_313 = 32'hbe00707f; + assign _zz_314 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_315 = 32'h00000033; + assign _zz_316 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_317 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_318 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_319 = decode_INSTRUCTION[31]; + assign _zz_320 = decode_INSTRUCTION[31]; + assign _zz_321 = decode_INSTRUCTION[7]; + assign _zz_322 = 32'h10103050; + assign _zz_323 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_324 = 32'h02004020; + assign _zz_325 = _zz_90; + assign _zz_326 = _zz_89; + assign _zz_327 = {_zz_90,{_zz_88,_zz_89}}; + assign _zz_328 = 3'b000; + assign _zz_329 = (((decode_INSTRUCTION & _zz_332) == 32'h02000030) != 1'b0); + assign _zz_330 = ((_zz_333 == _zz_334) != 1'b0); + assign _zz_331 = {(_zz_335 != 1'b0),{(_zz_336 != _zz_337),{_zz_338,{_zz_339,_zz_340}}}}; + assign _zz_332 = 32'h02004074; + assign _zz_333 = (decode_INSTRUCTION & 32'h10103050); + assign _zz_334 = 32'h00000050; + assign _zz_335 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz_336 = {(_zz_341 == _zz_342),(_zz_343 == _zz_344)}; + assign _zz_337 = 2'b00; + assign _zz_338 = ({_zz_87,_zz_345} != 2'b00); + assign _zz_339 = (_zz_346 != 1'b0); + assign _zz_340 = {(_zz_347 != _zz_348),{_zz_349,{_zz_350,_zz_351}}}; + assign _zz_341 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_342 = 32'h00001050; + assign _zz_343 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_344 = 32'h00002050; + assign _zz_345 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_346 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_347 = {(_zz_352 == _zz_353),(_zz_354 == _zz_355)}; + assign _zz_348 = 2'b00; + assign _zz_349 = ({_zz_356,{_zz_357,_zz_358}} != 3'b000); + assign _zz_350 = ({_zz_359,_zz_360} != 3'b000); + assign _zz_351 = {(_zz_361 != _zz_362),{_zz_363,{_zz_364,_zz_365}}}; + assign _zz_352 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_353 = 32'h00005010; + assign _zz_354 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_355 = 32'h00005020; + assign _zz_356 = ((decode_INSTRUCTION & _zz_366) == 32'h40001010); + assign _zz_357 = (_zz_367 == _zz_368); + assign _zz_358 = (_zz_369 == _zz_370); + assign _zz_359 = (_zz_371 == _zz_372); + assign _zz_360 = {_zz_373,_zz_374}; + assign _zz_361 = (_zz_375 == _zz_376); + assign _zz_362 = 1'b0; + assign _zz_363 = (_zz_88 != 1'b0); + assign _zz_364 = (_zz_377 != _zz_378); + assign _zz_365 = {_zz_379,{_zz_380,_zz_381}}; + assign _zz_366 = 32'h40003054; + assign _zz_367 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_368 = 32'h00001010; + assign _zz_369 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_370 = 32'h00001010; + assign _zz_371 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_372 = 32'h00000024; + assign _zz_373 = ((decode_INSTRUCTION & 32'h00003034) == 32'h00001010); + assign _zz_374 = ((decode_INSTRUCTION & 32'h02003054) == 32'h00001010); + assign _zz_375 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_376 = 32'h00001000; + assign _zz_377 = {(_zz_382 == _zz_383),(_zz_384 == _zz_385)}; + assign _zz_378 = 2'b00; + assign _zz_379 = ({_zz_386,_zz_387} != 2'b00); + assign _zz_380 = ({_zz_388,_zz_389} != 3'b000); + assign _zz_381 = {(_zz_390 != _zz_391),{_zz_392,{_zz_393,_zz_394}}}; + assign _zz_382 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_383 = 32'h00002000; + assign _zz_384 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_385 = 32'h00001000; + assign _zz_386 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_387 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_388 = ((decode_INSTRUCTION & _zz_395) == 32'h00000040); + assign _zz_389 = {(_zz_396 == _zz_397),(_zz_398 == _zz_399)}; + assign _zz_390 = ((decode_INSTRUCTION & _zz_400) == 32'h00000020); + assign _zz_391 = 1'b0; + assign _zz_392 = ((_zz_401 == _zz_402) != 1'b0); + assign _zz_393 = ({_zz_403,_zz_404} != 3'b000); + assign _zz_394 = {(_zz_405 != _zz_406),{_zz_407,{_zz_408,_zz_409}}}; + assign _zz_395 = 32'h00000050; + assign _zz_396 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_397 = 32'h0; + assign _zz_398 = (decode_INSTRUCTION & 32'h00103040); + assign _zz_399 = 32'h00000040; + assign _zz_400 = 32'h00000020; + assign _zz_401 = (decode_INSTRUCTION & 32'h00000010); + assign _zz_402 = 32'h00000010; + assign _zz_403 = _zz_86; + assign _zz_404 = {(_zz_410 == _zz_411),(_zz_412 == _zz_413)}; + assign _zz_405 = {_zz_87,{_zz_414,{_zz_415,_zz_416}}}; + assign _zz_406 = 6'h0; + assign _zz_407 = ({_zz_86,_zz_417} != 2'b00); + assign _zz_408 = ({_zz_418,_zz_419} != 2'b00); + assign _zz_409 = {(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}; + assign _zz_410 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_411 = 32'h00000010; + assign _zz_412 = (decode_INSTRUCTION & 32'h02000060); + assign _zz_413 = 32'h00000020; + assign _zz_414 = ((decode_INSTRUCTION & _zz_425) == 32'h00001010); + assign _zz_415 = (_zz_426 == _zz_427); + assign _zz_416 = {_zz_428,{_zz_429,_zz_430}}; + assign _zz_417 = ((decode_INSTRUCTION & _zz_431) == 32'h00000020); + assign _zz_418 = _zz_86; + assign _zz_419 = (_zz_432 == _zz_433); + assign _zz_420 = {_zz_434,_zz_435}; + assign _zz_421 = 2'b00; + assign _zz_422 = (_zz_436 != 1'b0); + assign _zz_423 = (_zz_437 != _zz_438); + assign _zz_424 = {_zz_439,{_zz_440,_zz_441}}; + assign _zz_425 = 32'h00001010; + assign _zz_426 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_427 = 32'h00002010; + assign _zz_428 = ((decode_INSTRUCTION & _zz_442) == 32'h00000010); + assign _zz_429 = (_zz_443 == _zz_444); + assign _zz_430 = (_zz_445 == _zz_446); + assign _zz_431 = 32'h00000070; + assign _zz_432 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_433 = 32'h0; + assign _zz_434 = ((decode_INSTRUCTION & _zz_447) == 32'h00006010); + assign _zz_435 = ((decode_INSTRUCTION & _zz_448) == 32'h00004010); + assign _zz_436 = ((decode_INSTRUCTION & _zz_449) == 32'h00002010); + assign _zz_437 = {_zz_450,{_zz_451,_zz_452}}; + assign _zz_438 = 4'b0000; + assign _zz_439 = (_zz_453 != 1'b0); + assign _zz_440 = (_zz_454 != _zz_455); + assign _zz_441 = {_zz_456,{_zz_457,_zz_458}}; + assign _zz_442 = 32'h00000050; + assign _zz_443 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_444 = 32'h00000004; + assign _zz_445 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_446 = 32'h0; + assign _zz_447 = 32'h00006014; + assign _zz_448 = 32'h00005014; + assign _zz_449 = 32'h00006014; + assign _zz_450 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_451 = ((decode_INSTRUCTION & _zz_459) == 32'h0); + assign _zz_452 = {(_zz_460 == _zz_461),(_zz_462 == _zz_463)}; + assign _zz_453 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_454 = {(_zz_464 == _zz_465),{_zz_466,_zz_467}}; + assign _zz_455 = 3'b000; + assign _zz_456 = ({_zz_468,_zz_85} != 2'b00); + assign _zz_457 = ({_zz_469,_zz_470} != 2'b00); + assign _zz_458 = (_zz_471 != 1'b0); + assign _zz_459 = 32'h00000018; + assign _zz_460 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_461 = 32'h00002000; + assign _zz_462 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_463 = 32'h00001000; + assign _zz_464 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_465 = 32'h00000040; + assign _zz_466 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_467 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz_468 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_469 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_470 = _zz_85; + assign _zz_471 = ((decode_INSTRUCTION & 32'h00001048) == 32'h00001008); + assign _zz_472 = execute_INSTRUCTION[31]; + assign _zz_473 = execute_INSTRUCTION[31]; + assign _zz_474 = execute_INSTRUCTION[7]; always @ (posedge clk) begin - if(_zz_53_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + if(_zz_298) begin + _zz_165 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_352_) begin - _zz_218_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_299) begin + _zz_166 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_353_) begin - _zz_219_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - InstructionCache IBusCachedPlugin_cache ( - .io_flush(_zz_209_), - .io_cpu_prefetch_isValid(_zz_210_), - .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), - .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), - .io_cpu_fetch_isValid(_zz_211_), - .io_cpu_fetch_isStuck(_zz_212_), - .io_cpu_fetch_isRemoved(IBusCachedPlugin_fetcherflushIt), - .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_stages_1_input_payload), - .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), - .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), - .io_cpu_fetch_dataBypass(_zz_213_), - .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), - .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), - .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), - .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_mmuBus_rsp_physicalAddress), - .io_cpu_fetch_mmuBus_rsp_isIoAccess(IBusCachedPlugin_mmuBus_rsp_isIoAccess), - .io_cpu_fetch_mmuBus_rsp_allowRead(IBusCachedPlugin_mmuBus_rsp_allowRead), - .io_cpu_fetch_mmuBus_rsp_allowWrite(IBusCachedPlugin_mmuBus_rsp_allowWrite), - .io_cpu_fetch_mmuBus_rsp_allowExecute(IBusCachedPlugin_mmuBus_rsp_allowExecute), - .io_cpu_fetch_mmuBus_rsp_exception(IBusCachedPlugin_mmuBus_rsp_exception), - .io_cpu_fetch_mmuBus_rsp_refilling(IBusCachedPlugin_mmuBus_rsp_refilling), - .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), - .io_cpu_fetch_mmuBus_busy(IBusCachedPlugin_mmuBus_busy), - .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), - .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), - .io_cpu_decode_isValid(_zz_214_), - .io_cpu_decode_isStuck(_zz_215_), - .io_cpu_decode_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), - .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), - .io_cpu_decode_cacheMiss(IBusCachedPlugin_cache_io_cpu_decode_cacheMiss), - .io_cpu_decode_error(IBusCachedPlugin_cache_io_cpu_decode_error), - .io_cpu_decode_mmuRefilling(IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling), - .io_cpu_decode_mmuException(IBusCachedPlugin_cache_io_cpu_decode_mmuException), - .io_cpu_decode_isUser(_zz_216_), - .io_cpu_fill_valid(_zz_217_), - .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), - .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), - .io_mem_cmd_ready(iBus_cmd_ready), - .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), - .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), - .io_mem_rsp_valid(iBus_rsp_valid), - .io_mem_rsp_payload_data(iBus_rsp_payload_data), - .io_mem_rsp_payload_error(iBus_rsp_payload_error), - ._zz_10_(_zz_205_), - ._zz_11_(IBusCachedPlugin_injectionPort_payload), - .clk(clk), - .reset(reset) + if(_zz_39) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_156 ), //i + .io_cpu_prefetch_isValid (_zz_157 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_158 ), //i + .io_cpu_fetch_isStuck (_zz_159 ), //i + .io_cpu_fetch_isRemoved (_zz_160 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_161 ), //i + .io_cpu_decode_isStuck (_zz_162 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_163 ), //i + .io_cpu_fill_valid (_zz_164 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_9 (_zz_144[2:0] ), //i + ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_354_) - 3'b000 : begin - _zz_220_ = CsrPlugin_jumpInterface_payload; - end - 3'b001 : begin - _zz_220_ = DBusSimplePlugin_redoBranch_payload; + case(_zz_300) + 2'b00 : begin + _zz_167 = CsrPlugin_jumpInterface_payload; end - 3'b010 : begin - _zz_220_ = BranchPlugin_jumpInterface_payload; + 2'b01 : begin + _zz_167 = DBusSimplePlugin_redoBranch_payload; end - 3'b011 : begin - _zz_220_ = IBusCachedPlugin_redoBranch_payload; + 2'b10 : begin + _zz_167 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_220_ = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_167 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end `ifndef SYNTHESIS always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; endcase end always @(*) begin - case(_zz_1_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_1__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_1__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_1__string = "URS1 "; - default : _zz_1__string = "????????????"; + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; endcase end always @(*) begin - case(_zz_2_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_2__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_2__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_2__string = "URS1 "; - default : _zz_2__string = "????????????"; + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; endcase end always @(*) begin - case(_zz_3_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_3__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_3__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_3__string = "URS1 "; - default : _zz_3__string = "????????????"; + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_4__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_4__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_4__string = "PC "; - default : _zz_4__string = "???"; + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; endcase end always @(*) begin - case(_zz_5_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_5__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_5__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_5__string = "PC "; - default : _zz_5__string = "???"; + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; endcase end always @(*) begin - case(_zz_6_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_6__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_6__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_6__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_6__string = "PC "; - default : _zz_6__string = "???"; + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; endcase end always @(*) begin - case(_zz_7_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_7__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_7__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_7__string = "BITWISE "; - default : _zz_7__string = "????????"; + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; endcase end always @(*) begin - case(_zz_8_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_8__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_8__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_8__string = "BITWISE "; - default : _zz_8__string = "????????"; + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_9_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_9__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_9__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_9__string = "BITWISE "; - default : _zz_9__string = "????????"; + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; endcase end always @(*) begin - case(_zz_10_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_10__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_10__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_10__string = "AND_1"; - default : _zz_10__string = "?????"; + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; endcase end always @(*) begin - case(_zz_11_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_11__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_11__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_11__string = "AND_1"; - default : _zz_11__string = "?????"; + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_12_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_12__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_12__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_12__string = "AND_1"; - default : _zz_12__string = "?????"; + case(_zz_13) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_13_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_13_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_13_string = "AND_1"; + default : _zz_13_string = "?????"; endcase end always @(*) begin - case(_zz_13_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_13__string = "ECALL"; - default : _zz_13__string = "?????"; + case(_zz_14) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; + default : _zz_14_string = "?????"; endcase end always @(*) begin - case(_zz_14_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_14__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_14__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_14__string = "ECALL"; - default : _zz_14__string = "?????"; + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; endcase end always @(*) begin - case(_zz_15_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_15__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_15__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_15__string = "ECALL"; - default : _zz_15__string = "?????"; + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_16_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_16__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_16__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_16__string = "ECALL"; - default : _zz_16__string = "?????"; + case(_zz_16) + `Src2CtrlEnum_defaultEncoding_RS : _zz_16_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_16_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_16_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_16_string = "PC "; + default : _zz_16_string = "???"; endcase end always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; + case(_zz_17) + `Src2CtrlEnum_defaultEncoding_RS : _zz_17_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_17_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_17_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_17_string = "PC "; + default : _zz_17_string = "???"; endcase end always @(*) begin - case(_zz_17_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_17__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_17__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_17__string = "ECALL"; - default : _zz_17__string = "?????"; + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; endcase end always @(*) begin - case(_zz_18_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_18__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_18__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_18__string = "ECALL"; - default : _zz_18__string = "?????"; + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_19_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_19__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_19__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_19__string = "ECALL"; - default : _zz_19__string = "?????"; + case(_zz_19) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19_string = "BITWISE "; + default : _zz_19_string = "????????"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(_zz_20) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; + default : _zz_20_string = "????????"; endcase end always @(*) begin - case(_zz_20_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 "; - default : _zz_20__string = "?????????"; + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; endcase end always @(*) begin - case(_zz_21_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 "; - default : _zz_21__string = "?????????"; + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_22_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; - default : _zz_22__string = "?????????"; + case(_zz_22) + `Src1CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_22_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_22_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_22_string = "URS1 "; + default : _zz_22_string = "????????????"; endcase end always @(*) begin - case(_zz_23_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_23__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_23__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_23__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_23__string = "JALR"; - default : _zz_23__string = "????"; + case(_zz_23) + `Src1CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_23_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_23_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_23_string = "URS1 "; + default : _zz_23_string = "????????????"; endcase end always @(*) begin - case(_zz_24_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_24__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_24__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_24__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_24__string = "JALR"; - default : _zz_24__string = "????"; + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; endcase end always @(*) begin @@ -2161,11 +1835,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_26_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL"; - default : _zz_26__string = "?????"; + case(_zz_25) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_25_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_25_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25_string = "ECALL"; + default : _zz_25_string = "?????"; endcase end always @(*) begin @@ -2177,11 +1851,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_27_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL"; - default : _zz_27__string = "?????"; + case(_zz_26) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_26_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_26_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26_string = "ECALL"; + default : _zz_26_string = "?????"; endcase end always @(*) begin @@ -2193,11 +1867,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_30_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30__string = "ECALL"; - default : _zz_30__string = "?????"; + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; endcase end always @(*) begin @@ -2210,12 +1884,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_33_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_33__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_33__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_33__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_33__string = "JALR"; - default : _zz_33__string = "????"; + case(_zz_28) + `BranchCtrlEnum_defaultEncoding_INC : _zz_28_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_28_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_28_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_28_string = "JALR"; + default : _zz_28_string = "????"; endcase end always @(*) begin @@ -2228,12 +1902,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_38_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38__string = "SRA_1 "; - default : _zz_38__string = "?????????"; + case(_zz_31) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_31_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_31_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_31_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_31_string = "SRA_1 "; + default : _zz_31_string = "?????????"; endcase end always @(*) begin @@ -2246,12 +1920,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_43_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_43__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_43__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_43__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_43__string = "PC "; - default : _zz_43__string = "???"; + case(_zz_33) + `Src2CtrlEnum_defaultEncoding_RS : _zz_33_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_33_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_33_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_33_string = "PC "; + default : _zz_33_string = "???"; endcase end always @(*) begin @@ -2264,12 +1938,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_45_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_45__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_45__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_45__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_45__string = "URS1 "; - default : _zz_45__string = "????????????"; + case(_zz_34) + `Src1CtrlEnum_defaultEncoding_RS : _zz_34_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_34_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34_string = "URS1 "; + default : _zz_34_string = "????????????"; endcase end always @(*) begin @@ -2281,11 +1955,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_48_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48__string = "BITWISE "; - default : _zz_48__string = "????????"; + case(_zz_35) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_35_string = "BITWISE "; + default : _zz_35_string = "????????"; endcase end always @(*) begin @@ -2297,71 +1971,71 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_50_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_50__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_50__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_50__string = "AND_1"; - default : _zz_50__string = "?????"; + case(_zz_36) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_36_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_36_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_36_string = "AND_1"; + default : _zz_36_string = "?????"; endcase end always @(*) begin - case(_zz_61_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_61__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_61__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_61__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_61__string = "SRA_1 "; - default : _zz_61__string = "?????????"; + case(_zz_40) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_40_string = "ECALL"; + default : _zz_40_string = "?????"; endcase end always @(*) begin - case(_zz_63_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_63__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_63__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_63__string = "ECALL"; - default : _zz_63__string = "?????"; + case(_zz_41) + `BranchCtrlEnum_defaultEncoding_INC : _zz_41_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_41_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_41_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_41_string = "JALR"; + default : _zz_41_string = "????"; endcase end always @(*) begin - case(_zz_65_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_65__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_65__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_65__string = "AND_1"; - default : _zz_65__string = "?????"; + case(_zz_42) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_42_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_42_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_42_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_42_string = "SRA_1 "; + default : _zz_42_string = "?????????"; endcase end always @(*) begin - case(_zz_69_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_69__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_69__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_69__string = "BITWISE "; - default : _zz_69__string = "????????"; + case(_zz_43) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_70_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_70__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_70__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_70__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_70__string = "PC "; - default : _zz_70__string = "???"; + case(_zz_44) + `Src2CtrlEnum_defaultEncoding_RS : _zz_44_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_44_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_44_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_44_string = "PC "; + default : _zz_44_string = "???"; endcase end always @(*) begin - case(_zz_76_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_76__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_76__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_76__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_76__string = "URS1 "; - default : _zz_76__string = "????????????"; + case(_zz_45) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; + default : _zz_45_string = "????????"; endcase end always @(*) begin - case(_zz_79_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_79__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_79__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_79__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_79__string = "JALR"; - default : _zz_79__string = "????"; + case(_zz_46) + `Src1CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_46_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_46_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_46_string = "URS1 "; + default : _zz_46_string = "????????????"; endcase end always @(*) begin @@ -2374,81 +2048,106 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_97_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_97__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_97__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_97__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_97__string = "JALR"; - default : _zz_97__string = "????"; + case(_zz_48) + `BranchCtrlEnum_defaultEncoding_INC : _zz_48_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_48_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_48_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_48_string = "JALR"; + default : _zz_48_string = "????"; endcase end always @(*) begin - case(_zz_144_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_144__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_144__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_144__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_144__string = "JALR"; - default : _zz_144__string = "????"; + case(_zz_91) + `Src1CtrlEnum_defaultEncoding_RS : _zz_91_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_91_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_91_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_91_string = "URS1 "; + default : _zz_91_string = "????????????"; endcase end always @(*) begin - case(_zz_145_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_145__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_145__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_145__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_145__string = "URS1 "; - default : _zz_145__string = "????????????"; + case(_zz_92) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_92_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_92_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_92_string = "BITWISE "; + default : _zz_92_string = "????????"; endcase end always @(*) begin - case(_zz_146_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_146__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_146__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_146__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_146__string = "PC "; - default : _zz_146__string = "???"; + case(_zz_93) + `Src2CtrlEnum_defaultEncoding_RS : _zz_93_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_93_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_93_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_93_string = "PC "; + default : _zz_93_string = "???"; endcase end always @(*) begin - case(_zz_147_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_147__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_147__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_147__string = "BITWISE "; - default : _zz_147__string = "????????"; + case(_zz_94) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_94_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_94_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_94_string = "AND_1"; + default : _zz_94_string = "?????"; endcase end always @(*) begin - case(_zz_148_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_148__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_148__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_148__string = "AND_1"; - default : _zz_148__string = "?????"; + case(_zz_95) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_95_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_95_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_95_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_95_string = "SRA_1 "; + default : _zz_95_string = "?????????"; endcase end always @(*) begin - case(_zz_149_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_149__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_149__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_149__string = "ECALL"; - default : _zz_149__string = "?????"; + case(_zz_96) + `BranchCtrlEnum_defaultEncoding_INC : _zz_96_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_96_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_96_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_96_string = "JALR"; + default : _zz_96_string = "????"; endcase end always @(*) begin - case(_zz_150_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_150__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_150__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_150__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_150__string = "SRA_1 "; - default : _zz_150__string = "?????????"; + case(_zz_97) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_97_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_97_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_97_string = "ECALL"; + default : _zz_97_string = "?????"; endcase end always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin @@ -2460,6 +2159,15 @@ module VexRiscv ( default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end always @(*) begin case(decode_to_execute_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; @@ -2484,85 +2192,51 @@ module VexRiscv ( default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; - default : decode_to_execute_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end `endif - assign decode_CSR_WRITE_OPCODE = _zz_29_; - assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; - assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; - assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_100_; - assign decode_IS_CSR = _zz_60_; - assign decode_DO_EBREAK = _zz_25_; - assign decode_SRC1_CTRL = _zz_1_; - assign _zz_2_ = _zz_3_; + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_49_; + assign execute_REGFILE_WRITE_DATA = _zz_99; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_91_; - assign decode_SRC2_CTRL = _zz_4_; - assign _zz_5_ = _zz_6_; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_DIV = _zz_211[0]; + assign decode_IS_RS2_SIGNED = _zz_212[0]; + assign decode_IS_RS1_SIGNED = _zz_213[0]; + assign decode_IS_MUL = _zz_214[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_215[0]; + assign _zz_8 = _zz_9; + assign decode_SHIFT_CTRL = _zz_10; + assign _zz_11 = _zz_12; + assign decode_ALU_BITWISE_CTRL = _zz_13; + assign _zz_14 = _zz_15; + assign decode_SRC_LESS_UNSIGNED = _zz_216[0]; + assign decode_MEMORY_STORE = _zz_217[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_58_; - assign decode_SRC_LESS_UNSIGNED = _zz_74_; - assign decode_ALU_CTRL = _zz_7_; - assign _zz_8_ = _zz_9_; - assign decode_IS_DIV = _zz_75_; - assign decode_ALU_BITWISE_CTRL = _zz_10_; - assign _zz_11_ = _zz_12_; - assign decode_SRC2_FORCE_ZERO = _zz_47_; - assign execute_BRANCH_CALC = _zz_31_; - assign decode_MEMORY_STORE = _zz_73_; - assign memory_MEMORY_READ_DATA = _zz_82_; - assign _zz_13_ = _zz_14_; - assign _zz_15_ = _zz_16_; - assign decode_ENV_CTRL = _zz_17_; - assign _zz_18_ = _zz_19_; - assign decode_CSR_READ_OPCODE = _zz_28_; - assign decode_SHIFT_CTRL = _zz_20_; - assign _zz_21_ = _zz_22_; - assign decode_IS_RS2_SIGNED = _zz_78_; - assign execute_BRANCH_DO = _zz_32_; - assign decode_IS_MUL = _zz_56_; - assign _zz_23_ = _zz_24_; - assign decode_IS_RS1_SIGNED = _zz_67_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_64_; - assign decode_PREDICTION_HAD_BRANCHED2 = _zz_35_; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_218[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_219[0]; + assign decode_SRC2_CTRL = _zz_16; + assign _zz_17 = _zz_18; + assign decode_ALU_CTRL = _zz_19; + assign _zz_20 = _zz_21; + assign decode_SRC1_CTRL = _zz_22; + assign _zz_23 = _zz_24; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_72_; + assign decode_IS_EBREAK = _zz_220[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_MUL = decode_to_execute_IS_MUL; @@ -2572,27 +2246,27 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_26_; - assign execute_ENV_CTRL = _zz_27_; - assign writeBack_ENV_CTRL = _zz_30_; + assign memory_ENV_CTRL = _zz_25; + assign execute_ENV_CTRL = _zz_26; + assign writeBack_ENV_CTRL = _zz_27; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_34_; - assign execute_BRANCH_CTRL = _zz_33_; - assign decode_RS2_USE = _zz_77_; - assign decode_RS1_USE = _zz_59_; + assign execute_BRANCH_COND_RESULT = _zz_115; + assign execute_BRANCH_CTRL = _zz_28; + assign decode_RS2_USE = _zz_221[0]; + assign decode_RS1_USE = _zz_222[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; always @ (*) begin - _zz_36_ = memory_REGFILE_WRITE_DATA; - if(_zz_221_)begin - _zz_36_ = ((memory_INSTRUCTION[13 : 12] == (2'b00)) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + _zz_29 = memory_REGFILE_WRITE_DATA; + if(_zz_168)begin + _zz_29 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_222_)begin - _zz_36_ = memory_MulDivIterativePlugin_div_result; + if(_zz_169)begin + _zz_29 = memory_MulDivIterativePlugin_div_result; end end @@ -2601,114 +2275,113 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - decode_RS2 = _zz_54_; - if(_zz_163_)begin - if((_zz_164_ == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_165_; + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_223_)begin - if(_zz_224_)begin - if(_zz_167_)begin - decode_RS2 = _zz_81_; + if(_zz_170)begin + if(_zz_171)begin + if(_zz_108)begin + decode_RS2 = _zz_47; end end end - if(_zz_225_)begin + if(_zz_172)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_169_)begin - decode_RS2 = _zz_36_; + if(_zz_110)begin + decode_RS2 = _zz_29; end end end - if(_zz_226_)begin + if(_zz_173)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_171_)begin - decode_RS2 = _zz_37_; + if(_zz_112)begin + decode_RS2 = _zz_30; end end end end always @ (*) begin - decode_RS1 = _zz_55_; - if(_zz_163_)begin - if((_zz_164_ == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_165_; + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_223_)begin - if(_zz_224_)begin - if(_zz_166_)begin - decode_RS1 = _zz_81_; + if(_zz_170)begin + if(_zz_171)begin + if(_zz_107)begin + decode_RS1 = _zz_47; end end end - if(_zz_225_)begin + if(_zz_172)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_168_)begin - decode_RS1 = _zz_36_; + if(_zz_109)begin + decode_RS1 = _zz_29; end end end - if(_zz_226_)begin + if(_zz_173)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_170_)begin - decode_RS1 = _zz_37_; + if(_zz_111)begin + decode_RS1 = _zz_30; end end end end always @ (*) begin - _zz_37_ = execute_REGFILE_WRITE_DATA; - if(_zz_227_)begin - _zz_37_ = _zz_159_; + _zz_30 = execute_REGFILE_WRITE_DATA; + if(_zz_174)begin + _zz_30 = _zz_106; end - if(_zz_228_)begin - _zz_37_ = execute_CsrPlugin_readData; + if(_zz_175)begin + _zz_30 = execute_CsrPlugin_readData; end end - assign execute_SHIFT_CTRL = _zz_38_; + assign execute_SHIFT_CTRL = _zz_31; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_42_ = execute_PC; - assign execute_SRC2_CTRL = _zz_43_; - assign execute_SRC1_CTRL = _zz_45_; - assign decode_SRC_USE_SUB_LESS = _zz_68_; - assign decode_SRC_ADD_ZERO = _zz_71_; - assign execute_SRC_ADD_SUB = _zz_41_; - assign execute_SRC_LESS = _zz_39_; - assign execute_ALU_CTRL = _zz_48_; - assign execute_SRC2 = _zz_44_; - assign execute_SRC1 = _zz_46_; - assign execute_ALU_BITWISE_CTRL = _zz_50_; - assign _zz_51_ = writeBack_INSTRUCTION; - assign _zz_52_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_53_ = 1'b0; + assign _zz_32 = execute_PC; + assign execute_SRC2_CTRL = _zz_33; + assign execute_SRC1_CTRL = _zz_34; + assign decode_SRC_USE_SUB_LESS = _zz_223[0]; + assign decode_SRC_ADD_ZERO = _zz_224[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_35; + assign execute_SRC2 = _zz_105; + assign execute_SRC1 = _zz_100; + assign execute_ALU_BITWISE_CTRL = _zz_36; + assign _zz_37 = writeBack_INSTRUCTION; + assign _zz_38 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_39 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_53_ = 1'b1; + _zz_39 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_96_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_62_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_225[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_80_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_301) == 32'h00001073),{(_zz_302 == _zz_303),{_zz_304,{_zz_305,_zz_306}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin - _zz_81_ = writeBack_REGFILE_WRITE_DATA; + _zz_47 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_81_ = writeBack_DBusSimplePlugin_rspFormated; + _zz_47 = writeBack_DBusSimplePlugin_rspFormated; end end @@ -2716,85 +2389,86 @@ module VexRiscv ( assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress; - assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess; - assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead; - assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite; - assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute; - assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception; - assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling; + assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; + assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; + assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; + assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; + assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; + assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; + assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; + assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; + assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; assign memory_PC = execute_to_memory_PC; assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = _zz_90_; - assign execute_MMU_RSP_physicalAddress = _zz_83_; - assign execute_MMU_RSP_isIoAccess = _zz_84_; - assign execute_MMU_RSP_allowRead = _zz_85_; - assign execute_MMU_RSP_allowWrite = _zz_86_; - assign execute_MMU_RSP_allowExecute = _zz_87_; - assign execute_MMU_RSP_exception = _zz_88_; - assign execute_MMU_RSP_refilling = _zz_89_; - assign execute_SRC_ADD = _zz_40_; + assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); + assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; + assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; + assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; + assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; + assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; + assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; + assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; + assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_ALIGNEMENT_FAULT = _zz_92_; - assign decode_MEMORY_ENABLE = _zz_66_; - assign decode_FLUSH_ALL = _zz_57_; + assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); + assign decode_MEMORY_ENABLE = _zz_226[0]; + assign decode_FLUSH_ALL = _zz_227[0]; always @ (*) begin - IBusCachedPlugin_rsp_issueDetected = _zz_93_; - if(_zz_229_)begin - IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_176)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin - _zz_93_ = _zz_94_; - if(_zz_230_)begin - _zz_93_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_177)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin - _zz_94_ = _zz_95_; - if(_zz_231_)begin - _zz_94_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_178)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_95_ = 1'b0; - if(_zz_232_)begin - _zz_95_ = 1'b1; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_179)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_97_; - assign decode_INSTRUCTION = _zz_101_; + assign decode_BRANCH_CTRL = _zz_48; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_98_ = memory_FORMAL_PC_NEXT; + _zz_49 = memory_FORMAL_PC_NEXT; if(DBusSimplePlugin_redoBranch_valid)begin - _zz_98_ = DBusSimplePlugin_redoBranch_payload; + _zz_49 = DBusSimplePlugin_redoBranch_payload; end if(BranchPlugin_jumpInterface_valid)begin - _zz_98_ = BranchPlugin_jumpInterface_payload; + _zz_49 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_99_ = decode_FORMAL_PC_NEXT; + _zz_50 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_99_ = IBusCachedPlugin_predictionJumpInterface_payload; - end - if(IBusCachedPlugin_redoBranch_valid)begin - _zz_99_ = IBusCachedPlugin_redoBranch_payload; + _zz_50 = IBusCachedPlugin_predictionJumpInterface_payload; end end - assign decode_PC = _zz_102_; + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -2802,18 +2476,10 @@ module VexRiscv ( if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_205_) - 3'b000 : begin - end - 3'b001 : begin - end + case(_zz_144) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end - 3'b011 : begin - end - 3'b100 : begin - end default : begin end endcase @@ -2821,20 +2487,20 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_160_ || _zz_161_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_233_)begin + if(_zz_180)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2845,27 +2511,25 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_redoBranch_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_233_)begin + if(_zz_180)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_130_)))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_77)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_227_)begin - if(_zz_234_)begin - if(! execute_LightShifterPlugin_done) begin - execute_arbitration_haltItself = 1'b1; - end + if(_zz_174)begin + if((! execute_LightShifterPlugin_done))begin + execute_arbitration_haltItself = 1'b1; end end - if(_zz_228_)begin + if(_zz_175)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2874,7 +2538,7 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_235_)begin + if(_zz_181)begin execute_arbitration_haltByOther = 1'b1; end end @@ -2891,8 +2555,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_235_)begin - if(_zz_236_)begin + if(_zz_181)begin + if(_zz_182)begin execute_arbitration_flushIt = 1'b1; end end @@ -2903,8 +2567,8 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_235_)begin - if(_zz_236_)begin + if(_zz_181)begin + if(_zz_182)begin execute_arbitration_flushNext = 1'b1; end end @@ -2915,13 +2579,16 @@ module VexRiscv ( if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_221_)begin - if(_zz_237_)begin + if(_zz_168)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_183)begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_222_)begin - if(_zz_238_)begin + if(_zz_169)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end end @@ -2930,7 +2597,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_239_)begin + if(_zz_184)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2953,7 +2620,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_239_)begin + if(_zz_184)begin memory_arbitration_flushNext = 1'b1; end end @@ -2970,10 +2637,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_240_)begin + if(_zz_185)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_241_)begin + if(_zz_186)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2984,67 +2651,60 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_240_)begin + if(_zz_185)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_241_)begin + if(_zz_186)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_235_)begin - if(_zz_236_)begin + if(_zz_181)begin + if(_zz_182)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_242_)begin + if(_zz_187)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end always @ (*) begin - IBusCachedPlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if((IBusCachedPlugin_predictionJumpInterface_valid && decode_arbitration_isFiring))begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end - if(_zz_235_)begin - if(_zz_236_)begin - IBusCachedPlugin_fetcherflushIt = 1'b1; - end + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; end end + assign CsrPlugin_inWfi = 1'b0; always @ (*) begin - IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid))begin - IBusCachedPlugin_incomingInstruction = 1'b1; + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_240_)begin + if(_zz_185)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_241_)begin + if(_zz_186)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_240_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_185)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_241_)begin - case(_zz_243_) + if(_zz_186)begin + case(_zz_188) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3075,21 +2735,25 @@ module VexRiscv ( end end - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,{IBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != (5'b00000)); - assign _zz_103_ = {IBusCachedPlugin_predictionJumpInterface_valid,{IBusCachedPlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}}; - assign _zz_104_ = (_zz_103_ & (~ _zz_264_)); - assign _zz_105_ = _zz_104_[3]; - assign _zz_106_ = _zz_104_[4]; - assign _zz_107_ = (_zz_104_[1] || _zz_105_); - assign _zz_108_ = (_zz_104_[2] || _zz_105_); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_220_; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_51 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; + assign _zz_52 = (_zz_51 & (~ _zz_228)); + assign _zz_53 = _zz_52[3]; + assign _zz_54 = (_zz_52[1] || _zz_53); + assign _zz_55 = (_zz_52[2] || _zz_53); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_167; always @ (*) begin - IBusCachedPlugin_fetchPc_corrected = 1'b0; + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin - IBusCachedPlugin_fetchPc_corrected = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin @@ -3098,7 +2762,10 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_266_); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_230); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end if(IBusCachedPlugin_jump_pcLoad_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end @@ -3106,12 +2773,28 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin @@ -3119,41 +2802,44 @@ module VexRiscv ( end end - assign _zz_109_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_109_); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_109_); + assign _zz_56 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_56); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_56); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + if(IBusCachedPlugin_mmuBus_busy)begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_110_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_110_); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_110_); + assign _zz_57 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_57); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_57); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin - IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; - end - end - - assign _zz_111_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_111_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_111_); - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_112_; - assign _zz_112_ = ((1'b0 && (! _zz_113_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_113_ = _zz_114_; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_113_; + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_58 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_58); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_58); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_59; + assign _zz_59 = ((1'b0 && (! _zz_60)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_60 = _zz_61; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_60; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_115_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_115_ = _zz_116_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_115_; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = _zz_117_; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_62)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_62 = _zz_63; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_62; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_64; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -3165,149 +2851,140 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; - assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin - decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); - case(_zz_205_) - 3'b000 : begin - end - 3'b001 : begin - end + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_144) 3'b010 : begin decode_arbitration_isValid = 1'b1; end 3'b011 : begin decode_arbitration_isValid = 1'b1; end - 3'b100 : begin - end default : begin end endcase end - assign _zz_102_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; - assign _zz_101_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; - assign _zz_100_ = (decode_PC + (32'b00000000000000000000000000000100)); - assign _zz_118_ = _zz_267_[11]; - always @ (*) begin - _zz_119_[18] = _zz_118_; - _zz_119_[17] = _zz_118_; - _zz_119_[16] = _zz_118_; - _zz_119_[15] = _zz_118_; - _zz_119_[14] = _zz_118_; - _zz_119_[13] = _zz_118_; - _zz_119_[12] = _zz_118_; - _zz_119_[11] = _zz_118_; - _zz_119_[10] = _zz_118_; - _zz_119_[9] = _zz_118_; - _zz_119_[8] = _zz_118_; - _zz_119_[7] = _zz_118_; - _zz_119_[6] = _zz_118_; - _zz_119_[5] = _zz_118_; - _zz_119_[4] = _zz_118_; - _zz_119_[3] = _zz_118_; - _zz_119_[2] = _zz_118_; - _zz_119_[1] = _zz_118_; - _zz_119_[0] = _zz_118_; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_268_[31])); - if(_zz_124_)begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; - end + assign _zz_65 = _zz_231[11]; + always @ (*) begin + _zz_66[18] = _zz_65; + _zz_66[17] = _zz_65; + _zz_66[16] = _zz_65; + _zz_66[15] = _zz_65; + _zz_66[14] = _zz_65; + _zz_66[13] = _zz_65; + _zz_66[12] = _zz_65; + _zz_66[11] = _zz_65; + _zz_66[10] = _zz_65; + _zz_66[9] = _zz_65; + _zz_66[8] = _zz_65; + _zz_66[7] = _zz_65; + _zz_66[6] = _zz_65; + _zz_66[5] = _zz_65; + _zz_66[4] = _zz_65; + _zz_66[3] = _zz_65; + _zz_66[2] = _zz_65; + _zz_66[1] = _zz_65; + _zz_66[0] = _zz_65; end - assign _zz_120_ = _zz_269_[19]; always @ (*) begin - _zz_121_[10] = _zz_120_; - _zz_121_[9] = _zz_120_; - _zz_121_[8] = _zz_120_; - _zz_121_[7] = _zz_120_; - _zz_121_[6] = _zz_120_; - _zz_121_[5] = _zz_120_; - _zz_121_[4] = _zz_120_; - _zz_121_[3] = _zz_120_; - _zz_121_[2] = _zz_120_; - _zz_121_[1] = _zz_120_; - _zz_121_[0] = _zz_120_; + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_232[31])); + if(_zz_71)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end end - assign _zz_122_ = _zz_270_[11]; + assign _zz_67 = _zz_233[19]; always @ (*) begin - _zz_123_[18] = _zz_122_; - _zz_123_[17] = _zz_122_; - _zz_123_[16] = _zz_122_; - _zz_123_[15] = _zz_122_; - _zz_123_[14] = _zz_122_; - _zz_123_[13] = _zz_122_; - _zz_123_[12] = _zz_122_; - _zz_123_[11] = _zz_122_; - _zz_123_[10] = _zz_122_; - _zz_123_[9] = _zz_122_; - _zz_123_[8] = _zz_122_; - _zz_123_[7] = _zz_122_; - _zz_123_[6] = _zz_122_; - _zz_123_[5] = _zz_122_; - _zz_123_[4] = _zz_122_; - _zz_123_[3] = _zz_122_; - _zz_123_[2] = _zz_122_; - _zz_123_[1] = _zz_122_; - _zz_123_[0] = _zz_122_; + _zz_68[10] = _zz_67; + _zz_68[9] = _zz_67; + _zz_68[8] = _zz_67; + _zz_68[7] = _zz_67; + _zz_68[6] = _zz_67; + _zz_68[5] = _zz_67; + _zz_68[4] = _zz_67; + _zz_68[3] = _zz_67; + _zz_68[2] = _zz_67; + _zz_68[1] = _zz_67; + _zz_68[0] = _zz_67; + end + + assign _zz_69 = _zz_234[11]; + always @ (*) begin + _zz_70[18] = _zz_69; + _zz_70[17] = _zz_69; + _zz_70[16] = _zz_69; + _zz_70[15] = _zz_69; + _zz_70[14] = _zz_69; + _zz_70[13] = _zz_69; + _zz_70[12] = _zz_69; + _zz_70[11] = _zz_69; + _zz_70[10] = _zz_69; + _zz_70[9] = _zz_69; + _zz_70[8] = _zz_69; + _zz_70[7] = _zz_69; + _zz_70[6] = _zz_69; + _zz_70[5] = _zz_69; + _zz_70[4] = _zz_69; + _zz_70[3] = _zz_69; + _zz_70[2] = _zz_69; + _zz_70[1] = _zz_69; + _zz_70[0] = _zz_69; end always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_124_ = _zz_271_[1]; + _zz_71 = _zz_235[1]; end default : begin - _zz_124_ = _zz_272_[1]; + _zz_71 = _zz_236[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_125_ = _zz_273_[19]; - always @ (*) begin - _zz_126_[10] = _zz_125_; - _zz_126_[9] = _zz_125_; - _zz_126_[8] = _zz_125_; - _zz_126_[7] = _zz_125_; - _zz_126_[6] = _zz_125_; - _zz_126_[5] = _zz_125_; - _zz_126_[4] = _zz_125_; - _zz_126_[3] = _zz_125_; - _zz_126_[2] = _zz_125_; - _zz_126_[1] = _zz_125_; - _zz_126_[0] = _zz_125_; - end - - assign _zz_127_ = _zz_274_[11]; - always @ (*) begin - _zz_128_[18] = _zz_127_; - _zz_128_[17] = _zz_127_; - _zz_128_[16] = _zz_127_; - _zz_128_[15] = _zz_127_; - _zz_128_[14] = _zz_127_; - _zz_128_[13] = _zz_127_; - _zz_128_[12] = _zz_127_; - _zz_128_[11] = _zz_127_; - _zz_128_[10] = _zz_127_; - _zz_128_[9] = _zz_127_; - _zz_128_[8] = _zz_127_; - _zz_128_[7] = _zz_127_; - _zz_128_[6] = _zz_127_; - _zz_128_[5] = _zz_127_; - _zz_128_[4] = _zz_127_; - _zz_128_[3] = _zz_127_; - _zz_128_[2] = _zz_127_; - _zz_128_[1] = _zz_127_; - _zz_128_[0] = _zz_127_; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_126_,{{{_zz_355_,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_128_,{{{_zz_356_,_zz_357_},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_72 = _zz_237[19]; + always @ (*) begin + _zz_73[10] = _zz_72; + _zz_73[9] = _zz_72; + _zz_73[8] = _zz_72; + _zz_73[7] = _zz_72; + _zz_73[6] = _zz_72; + _zz_73[5] = _zz_72; + _zz_73[4] = _zz_72; + _zz_73[3] = _zz_72; + _zz_73[2] = _zz_72; + _zz_73[1] = _zz_72; + _zz_73[0] = _zz_72; + end + + assign _zz_74 = _zz_238[11]; + always @ (*) begin + _zz_75[18] = _zz_74; + _zz_75[17] = _zz_74; + _zz_75[16] = _zz_74; + _zz_75[15] = _zz_74; + _zz_75[14] = _zz_74; + _zz_75[13] = _zz_74; + _zz_75[12] = _zz_74; + _zz_75[11] = _zz_74; + _zz_75[10] = _zz_74; + _zz_75[9] = _zz_74; + _zz_75[8] = _zz_74; + _zz_75[7] = _zz_74; + _zz_75[6] = _zz_74; + _zz_75[5] = _zz_74; + _zz_75[4] = _zz_74; + _zz_75[3] = _zz_74; + _zz_75[2] = _zz_74; + _zz_75[1] = _zz_74; + _zz_75[0] = _zz_74; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_73,{{{_zz_319,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_75,{{{_zz_320,_zz_321},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3316,161 +2993,143 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_210_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_213_ = (32'b00000000000000000000000000000000); - assign _zz_211_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_212_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_214_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_215_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); - assign _zz_216_ = (CsrPlugin_privilege == (2'b00)); - assign _zz_96_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + assign _zz_157 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_158 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_159 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_158; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_161 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_162 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_163 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_232_)begin + if(_zz_179)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_230_)begin + if(_zz_177)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_244_)begin - IBusCachedPlugin_rsp_redoFetch = 1'b0; - end end always @ (*) begin - _zz_217_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_230_)begin - _zz_217_ = 1'b1; - end - if(_zz_244_)begin - _zz_217_ = 1'b0; + _zz_164 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_177)begin + _zz_164 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_231_)begin + if(_zz_178)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_229_)begin + if(_zz_176)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_231_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_178)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_229_)begin - IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + if(_zz_176)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end - assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; - assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; - assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; - assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; - assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; - assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; - assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; - assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; - assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; - assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; - assign _zz_209_ = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign _zz_130_ = 1'b0; - assign _zz_92_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_156 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_77 = 1'b0; always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin execute_DBusSimplePlugin_skipCmd = 1'b1; end - if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin + if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_130_)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_77)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_131_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_78 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_131_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_78 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_131_ = execute_RS2[31 : 0]; + _zz_78 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_131_; - assign _zz_91_ = dBus_cmd_payload_address[1 : 0]; + assign dBus_cmd_payload_data = _zz_78; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_132_ = (4'b0001); + _zz_79 = 4'b0001; end 2'b01 : begin - _zz_132_ = (4'b0011); + _zz_79 = 4'b0011; end default : begin - _zz_132_ = (4'b1111); + _zz_79 = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_132_ <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; + assign execute_DBusSimplePlugin_formalMask = (_zz_79 <<< dBus_cmd_payload_address[1 : 0]); + assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; + assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; + assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign _zz_90_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE))); - assign _zz_83_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign _zz_84_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign _zz_85_ = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign _zz_86_ = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign _zz_87_ = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign _zz_88_ = DBusSimplePlugin_mmuBus_rsp_exception; - assign _zz_89_ = DBusSimplePlugin_mmuBus_rsp_refilling; - assign _zz_82_ = dBus_rsp_data; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_245_)begin + if(_zz_189)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end if(memory_ALIGNEMENT_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_MMU_RSP_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end else begin if(memory_MMU_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_246_)begin + if(_zz_190)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); - if(_zz_245_)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101); + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; + if(_zz_189)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_275_}; + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_239}; end - if(! memory_MMU_RSP_refilling) begin + if(! memory_MMU_RSP2_refilling) begin if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101)); + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); end end end @@ -3478,10 +3137,10 @@ module VexRiscv ( assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; always @ (*) begin DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_246_)begin + if(_zz_190)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -3504,63 +3163,63 @@ module VexRiscv ( endcase end - assign _zz_133_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_134_[31] = _zz_133_; - _zz_134_[30] = _zz_133_; - _zz_134_[29] = _zz_133_; - _zz_134_[28] = _zz_133_; - _zz_134_[27] = _zz_133_; - _zz_134_[26] = _zz_133_; - _zz_134_[25] = _zz_133_; - _zz_134_[24] = _zz_133_; - _zz_134_[23] = _zz_133_; - _zz_134_[22] = _zz_133_; - _zz_134_[21] = _zz_133_; - _zz_134_[20] = _zz_133_; - _zz_134_[19] = _zz_133_; - _zz_134_[18] = _zz_133_; - _zz_134_[17] = _zz_133_; - _zz_134_[16] = _zz_133_; - _zz_134_[15] = _zz_133_; - _zz_134_[14] = _zz_133_; - _zz_134_[13] = _zz_133_; - _zz_134_[12] = _zz_133_; - _zz_134_[11] = _zz_133_; - _zz_134_[10] = _zz_133_; - _zz_134_[9] = _zz_133_; - _zz_134_[8] = _zz_133_; - _zz_134_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_135_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_136_[31] = _zz_135_; - _zz_136_[30] = _zz_135_; - _zz_136_[29] = _zz_135_; - _zz_136_[28] = _zz_135_; - _zz_136_[27] = _zz_135_; - _zz_136_[26] = _zz_135_; - _zz_136_[25] = _zz_135_; - _zz_136_[24] = _zz_135_; - _zz_136_[23] = _zz_135_; - _zz_136_[22] = _zz_135_; - _zz_136_[21] = _zz_135_; - _zz_136_[20] = _zz_135_; - _zz_136_[19] = _zz_135_; - _zz_136_[18] = _zz_135_; - _zz_136_[17] = _zz_135_; - _zz_136_[16] = _zz_135_; - _zz_136_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_262_) + assign _zz_80 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_81[31] = _zz_80; + _zz_81[30] = _zz_80; + _zz_81[29] = _zz_80; + _zz_81[28] = _zz_80; + _zz_81[27] = _zz_80; + _zz_81[26] = _zz_80; + _zz_81[25] = _zz_80; + _zz_81[24] = _zz_80; + _zz_81[23] = _zz_80; + _zz_81[22] = _zz_80; + _zz_81[21] = _zz_80; + _zz_81[20] = _zz_80; + _zz_81[19] = _zz_80; + _zz_81[18] = _zz_80; + _zz_81[17] = _zz_80; + _zz_81[16] = _zz_80; + _zz_81[15] = _zz_80; + _zz_81[14] = _zz_80; + _zz_81[13] = _zz_80; + _zz_81[12] = _zz_80; + _zz_81[11] = _zz_80; + _zz_81[10] = _zz_80; + _zz_81[9] = _zz_80; + _zz_81[8] = _zz_80; + _zz_81[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_82 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_83[31] = _zz_82; + _zz_83[30] = _zz_82; + _zz_83[29] = _zz_82; + _zz_83[28] = _zz_82; + _zz_83[27] = _zz_82; + _zz_83[26] = _zz_82; + _zz_83[25] = _zz_82; + _zz_83[24] = _zz_82; + _zz_83[23] = _zz_82; + _zz_83[22] = _zz_82; + _zz_83[21] = _zz_82; + _zz_83[20] = _zz_82; + _zz_83[19] = _zz_82; + _zz_83[18] = _zz_82; + _zz_83[17] = _zz_82; + _zz_83[16] = _zz_82; + _zz_83[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_209) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_134_; + writeBack_DBusSimplePlugin_rspFormated = _zz_81; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_136_; + writeBack_DBusSimplePlugin_rspFormated = _zz_83; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -3568,79 +3227,73 @@ module VexRiscv ( endcase end - assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress; + assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_138_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_139_ = ((decode_INSTRUCTION & (32'b00000000000000000111000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_140_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000100000000000000)); - assign _zz_141_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_142_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_143_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); - assign _zz_137_ = {(((decode_INSTRUCTION & _zz_358_) == (32'b00000010000000000000000000110000)) != (1'b0)),{((_zz_359_ == _zz_360_) != (1'b0)),{(_zz_361_ != (1'b0)),{(_zz_362_ != _zz_363_),{_zz_364_,{_zz_365_,_zz_366_}}}}}}; - assign _zz_80_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_514_) == (32'b00000000000000000001000001110011)),{(_zz_515_ == _zz_516_),{_zz_517_,{_zz_518_,_zz_519_}}}}}}} != (20'b00000000000000000000)); - assign _zz_144_ = _zz_137_[1 : 0]; - assign _zz_79_ = _zz_144_; - assign _zz_78_ = _zz_276_[0]; - assign _zz_77_ = _zz_277_[0]; - assign _zz_145_ = _zz_137_[5 : 4]; - assign _zz_76_ = _zz_145_; - assign _zz_75_ = _zz_278_[0]; - assign _zz_74_ = _zz_279_[0]; - assign _zz_73_ = _zz_280_[0]; - assign _zz_72_ = _zz_281_[0]; - assign _zz_71_ = _zz_282_[0]; - assign _zz_146_ = _zz_137_[12 : 11]; - assign _zz_70_ = _zz_146_; - assign _zz_147_ = _zz_137_[14 : 13]; - assign _zz_69_ = _zz_147_; - assign _zz_68_ = _zz_283_[0]; - assign _zz_67_ = _zz_284_[0]; - assign _zz_66_ = _zz_285_[0]; - assign _zz_148_ = _zz_137_[19 : 18]; - assign _zz_65_ = _zz_148_; - assign _zz_64_ = _zz_286_[0]; - assign _zz_149_ = _zz_137_[23 : 22]; - assign _zz_63_ = _zz_149_; - assign _zz_62_ = _zz_287_[0]; - assign _zz_150_ = _zz_137_[26 : 25]; - assign _zz_61_ = _zz_150_; - assign _zz_60_ = _zz_288_[0]; - assign _zz_59_ = _zz_289_[0]; - assign _zz_58_ = _zz_290_[0]; - assign _zz_57_ = _zz_291_[0]; - assign _zz_56_ = _zz_292_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign _zz_85 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_86 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_87 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_88 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_89 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); + assign _zz_90 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); + assign _zz_84 = {(((decode_INSTRUCTION & _zz_322) == 32'h00100050) != 1'b0),{((_zz_323 == _zz_324) != 1'b0),{({_zz_325,_zz_326} != 2'b00),{(_zz_327 != _zz_328),{_zz_329,{_zz_330,_zz_331}}}}}}; + assign _zz_91 = _zz_84[2 : 1]; + assign _zz_46 = _zz_91; + assign _zz_92 = _zz_84[7 : 6]; + assign _zz_45 = _zz_92; + assign _zz_93 = _zz_84[9 : 8]; + assign _zz_44 = _zz_93; + assign _zz_94 = _zz_84[18 : 17]; + assign _zz_43 = _zz_94; + assign _zz_95 = _zz_84[21 : 20]; + assign _zz_42 = _zz_95; + assign _zz_96 = _zz_84[23 : 22]; + assign _zz_41 = _zz_96; + assign _zz_97 = _zz_84[26 : 25]; + assign _zz_40 = _zz_97; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_218_; - assign decode_RegFilePlugin_rs2Data = _zz_219_; - assign _zz_55_ = decode_RegFilePlugin_rs1Data; - assign _zz_54_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_165; + assign decode_RegFilePlugin_rs2Data = _zz_166; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_52_ && writeBack_arbitration_isFiring); - if(_zz_151_)begin + lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); + if(_zz_98)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_51_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_81_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_37[11 : 7]; + if(_zz_98)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_47; + if(_zz_98)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -3658,303 +3311,297 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_152_ = execute_IntAluPlugin_bitwise; + _zz_99 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_152_ = {31'd0, _zz_293_}; + _zz_99 = {31'd0, _zz_240}; end default : begin - _zz_152_ = execute_SRC_ADD_SUB; + _zz_99 = execute_SRC_ADD_SUB; end endcase end - assign _zz_49_ = _zz_152_; - assign _zz_47_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_153_ = execute_RS1; + _zz_100 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_153_ = {29'd0, _zz_294_}; + _zz_100 = {29'd0, _zz_241}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_153_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_153_ = {27'd0, _zz_295_}; + _zz_100 = {27'd0, _zz_242}; end endcase end - assign _zz_46_ = _zz_153_; - assign _zz_154_ = _zz_296_[11]; - always @ (*) begin - _zz_155_[19] = _zz_154_; - _zz_155_[18] = _zz_154_; - _zz_155_[17] = _zz_154_; - _zz_155_[16] = _zz_154_; - _zz_155_[15] = _zz_154_; - _zz_155_[14] = _zz_154_; - _zz_155_[13] = _zz_154_; - _zz_155_[12] = _zz_154_; - _zz_155_[11] = _zz_154_; - _zz_155_[10] = _zz_154_; - _zz_155_[9] = _zz_154_; - _zz_155_[8] = _zz_154_; - _zz_155_[7] = _zz_154_; - _zz_155_[6] = _zz_154_; - _zz_155_[5] = _zz_154_; - _zz_155_[4] = _zz_154_; - _zz_155_[3] = _zz_154_; - _zz_155_[2] = _zz_154_; - _zz_155_[1] = _zz_154_; - _zz_155_[0] = _zz_154_; - end - - assign _zz_156_ = _zz_297_[11]; - always @ (*) begin - _zz_157_[19] = _zz_156_; - _zz_157_[18] = _zz_156_; - _zz_157_[17] = _zz_156_; - _zz_157_[16] = _zz_156_; - _zz_157_[15] = _zz_156_; - _zz_157_[14] = _zz_156_; - _zz_157_[13] = _zz_156_; - _zz_157_[12] = _zz_156_; - _zz_157_[11] = _zz_156_; - _zz_157_[10] = _zz_156_; - _zz_157_[9] = _zz_156_; - _zz_157_[8] = _zz_156_; - _zz_157_[7] = _zz_156_; - _zz_157_[6] = _zz_156_; - _zz_157_[5] = _zz_156_; - _zz_157_[4] = _zz_156_; - _zz_157_[3] = _zz_156_; - _zz_157_[2] = _zz_156_; - _zz_157_[1] = _zz_156_; - _zz_157_[0] = _zz_156_; + assign _zz_101 = _zz_243[11]; + always @ (*) begin + _zz_102[19] = _zz_101; + _zz_102[18] = _zz_101; + _zz_102[17] = _zz_101; + _zz_102[16] = _zz_101; + _zz_102[15] = _zz_101; + _zz_102[14] = _zz_101; + _zz_102[13] = _zz_101; + _zz_102[12] = _zz_101; + _zz_102[11] = _zz_101; + _zz_102[10] = _zz_101; + _zz_102[9] = _zz_101; + _zz_102[8] = _zz_101; + _zz_102[7] = _zz_101; + _zz_102[6] = _zz_101; + _zz_102[5] = _zz_101; + _zz_102[4] = _zz_101; + _zz_102[3] = _zz_101; + _zz_102[2] = _zz_101; + _zz_102[1] = _zz_101; + _zz_102[0] = _zz_101; + end + + assign _zz_103 = _zz_244[11]; + always @ (*) begin + _zz_104[19] = _zz_103; + _zz_104[18] = _zz_103; + _zz_104[17] = _zz_103; + _zz_104[16] = _zz_103; + _zz_104[15] = _zz_103; + _zz_104[14] = _zz_103; + _zz_104[13] = _zz_103; + _zz_104[12] = _zz_103; + _zz_104[11] = _zz_103; + _zz_104[10] = _zz_103; + _zz_104[9] = _zz_103; + _zz_104[8] = _zz_103; + _zz_104[7] = _zz_103; + _zz_104[6] = _zz_103; + _zz_104[5] = _zz_103; + _zz_104[4] = _zz_103; + _zz_104[3] = _zz_103; + _zz_104[2] = _zz_103; + _zz_104[1] = _zz_103; + _zz_104[0] = _zz_103; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_158_ = execute_RS2; + _zz_105 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_158_ = {_zz_155_,execute_INSTRUCTION[31 : 20]}; + _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_158_ = {_zz_157_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_105 = {_zz_104,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_158_ = _zz_42_; + _zz_105 = _zz_32; end endcase end - assign _zz_44_ = _zz_158_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_298_; + execute_SrcPlugin_addSub = _zz_245; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_41_ = execute_SrcPlugin_addSub; - assign _zz_40_ = execute_SrcPlugin_addSub; - assign _zz_39_ = execute_SrcPlugin_less; assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); - assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_159_ = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_106 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_159_ = _zz_305_; + _zz_106 = _zz_252; end endcase end always @ (*) begin - _zz_160_ = 1'b0; - if(_zz_247_)begin - if(_zz_248_)begin - if(_zz_166_)begin - _zz_160_ = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b0; + if(_zz_191)begin + if(_zz_192)begin + if(_zz_107)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_249_)begin - if(_zz_250_)begin - if(_zz_168_)begin - _zz_160_ = 1'b1; + if(_zz_193)begin + if(_zz_194)begin + if(_zz_109)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_251_)begin - if(_zz_252_)begin - if(_zz_170_)begin - _zz_160_ = 1'b1; + if(_zz_195)begin + if(_zz_196)begin + if(_zz_111)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_160_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_161_ = 1'b0; - if(_zz_247_)begin - if(_zz_248_)begin - if(_zz_167_)begin - _zz_161_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(_zz_191)begin + if(_zz_192)begin + if(_zz_108)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_249_)begin - if(_zz_250_)begin - if(_zz_169_)begin - _zz_161_ = 1'b1; + if(_zz_193)begin + if(_zz_194)begin + if(_zz_110)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_251_)begin - if(_zz_252_)begin - if(_zz_171_)begin - _zz_161_ = 1'b1; + if(_zz_195)begin + if(_zz_196)begin + if(_zz_112)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_161_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_162_ = (_zz_52_ && writeBack_arbitration_isFiring); - assign _zz_166_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_167_ = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_168_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_169_ = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_170_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_171_ = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_35_ = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_38 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_37[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_47; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign _zz_107 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_108 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_109 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_110 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_111 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_112 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_172_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_172_ == (3'b000))) begin - _zz_173_ = execute_BranchPlugin_eq; - end else if((_zz_172_ == (3'b001))) begin - _zz_173_ = (! execute_BranchPlugin_eq); - end else if((((_zz_172_ & (3'b101)) == (3'b101)))) begin - _zz_173_ = (! execute_SRC_LESS); + assign _zz_113 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_113 == 3'b000)) begin + _zz_114 = execute_BranchPlugin_eq; + end else if((_zz_113 == 3'b001)) begin + _zz_114 = (! execute_BranchPlugin_eq); + end else if((((_zz_113 & 3'b101) == 3'b101))) begin + _zz_114 = (! execute_SRC_LESS); end else begin - _zz_173_ = execute_SRC_LESS; + _zz_114 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_174_ = 1'b0; + _zz_115 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_174_ = 1'b1; + _zz_115 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_174_ = 1'b1; + _zz_115 = 1'b1; end default : begin - _zz_174_ = _zz_173_; + _zz_115 = _zz_114; end endcase end - assign _zz_34_ = _zz_174_; - assign _zz_175_ = _zz_307_[11]; - always @ (*) begin - _zz_176_[19] = _zz_175_; - _zz_176_[18] = _zz_175_; - _zz_176_[17] = _zz_175_; - _zz_176_[16] = _zz_175_; - _zz_176_[15] = _zz_175_; - _zz_176_[14] = _zz_175_; - _zz_176_[13] = _zz_175_; - _zz_176_[12] = _zz_175_; - _zz_176_[11] = _zz_175_; - _zz_176_[10] = _zz_175_; - _zz_176_[9] = _zz_175_; - _zz_176_[8] = _zz_175_; - _zz_176_[7] = _zz_175_; - _zz_176_[6] = _zz_175_; - _zz_176_[5] = _zz_175_; - _zz_176_[4] = _zz_175_; - _zz_176_[3] = _zz_175_; - _zz_176_[2] = _zz_175_; - _zz_176_[1] = _zz_175_; - _zz_176_[0] = _zz_175_; - end - - assign _zz_177_ = _zz_308_[19]; - always @ (*) begin - _zz_178_[10] = _zz_177_; - _zz_178_[9] = _zz_177_; - _zz_178_[8] = _zz_177_; - _zz_178_[7] = _zz_177_; - _zz_178_[6] = _zz_177_; - _zz_178_[5] = _zz_177_; - _zz_178_[4] = _zz_177_; - _zz_178_[3] = _zz_177_; - _zz_178_[2] = _zz_177_; - _zz_178_[1] = _zz_177_; - _zz_178_[0] = _zz_177_; - end - - assign _zz_179_ = _zz_309_[11]; - always @ (*) begin - _zz_180_[18] = _zz_179_; - _zz_180_[17] = _zz_179_; - _zz_180_[16] = _zz_179_; - _zz_180_[15] = _zz_179_; - _zz_180_[14] = _zz_179_; - _zz_180_[13] = _zz_179_; - _zz_180_[12] = _zz_179_; - _zz_180_[11] = _zz_179_; - _zz_180_[10] = _zz_179_; - _zz_180_[9] = _zz_179_; - _zz_180_[8] = _zz_179_; - _zz_180_[7] = _zz_179_; - _zz_180_[6] = _zz_179_; - _zz_180_[5] = _zz_179_; - _zz_180_[4] = _zz_179_; - _zz_180_[3] = _zz_179_; - _zz_180_[2] = _zz_179_; - _zz_180_[1] = _zz_179_; - _zz_180_[0] = _zz_179_; + assign _zz_116 = _zz_254[11]; + always @ (*) begin + _zz_117[19] = _zz_116; + _zz_117[18] = _zz_116; + _zz_117[17] = _zz_116; + _zz_117[16] = _zz_116; + _zz_117[15] = _zz_116; + _zz_117[14] = _zz_116; + _zz_117[13] = _zz_116; + _zz_117[12] = _zz_116; + _zz_117[11] = _zz_116; + _zz_117[10] = _zz_116; + _zz_117[9] = _zz_116; + _zz_117[8] = _zz_116; + _zz_117[7] = _zz_116; + _zz_117[6] = _zz_116; + _zz_117[5] = _zz_116; + _zz_117[4] = _zz_116; + _zz_117[3] = _zz_116; + _zz_117[2] = _zz_116; + _zz_117[1] = _zz_116; + _zz_117[0] = _zz_116; + end + + assign _zz_118 = _zz_255[19]; + always @ (*) begin + _zz_119[10] = _zz_118; + _zz_119[9] = _zz_118; + _zz_119[8] = _zz_118; + _zz_119[7] = _zz_118; + _zz_119[6] = _zz_118; + _zz_119[5] = _zz_118; + _zz_119[4] = _zz_118; + _zz_119[3] = _zz_118; + _zz_119[2] = _zz_118; + _zz_119[1] = _zz_118; + _zz_119[0] = _zz_118; + end + + assign _zz_120 = _zz_256[11]; + always @ (*) begin + _zz_121[18] = _zz_120; + _zz_121[17] = _zz_120; + _zz_121[16] = _zz_120; + _zz_121[15] = _zz_120; + _zz_121[14] = _zz_120; + _zz_121[13] = _zz_120; + _zz_121[12] = _zz_120; + _zz_121[11] = _zz_120; + _zz_121[10] = _zz_120; + _zz_121[9] = _zz_120; + _zz_121[8] = _zz_120; + _zz_121[7] = _zz_120; + _zz_121[6] = _zz_120; + _zz_121[5] = _zz_120; + _zz_121[4] = _zz_120; + _zz_121[3] = _zz_120; + _zz_121[2] = _zz_120; + _zz_121[1] = _zz_120; + _zz_121[0] = _zz_120; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_181_ = (_zz_310_[1] ^ execute_RS1[1]); + _zz_122 = (_zz_257[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_181_ = _zz_311_[1]; + _zz_122 = _zz_258[1]; end default : begin - _zz_181_ = _zz_312_[1]; + _zz_122 = _zz_259[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_181_); - assign _zz_32_ = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_122); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -3966,111 +3613,110 @@ module VexRiscv ( endcase end - assign _zz_182_ = _zz_313_[11]; + assign _zz_123 = _zz_260[11]; always @ (*) begin - _zz_183_[19] = _zz_182_; - _zz_183_[18] = _zz_182_; - _zz_183_[17] = _zz_182_; - _zz_183_[16] = _zz_182_; - _zz_183_[15] = _zz_182_; - _zz_183_[14] = _zz_182_; - _zz_183_[13] = _zz_182_; - _zz_183_[12] = _zz_182_; - _zz_183_[11] = _zz_182_; - _zz_183_[10] = _zz_182_; - _zz_183_[9] = _zz_182_; - _zz_183_[8] = _zz_182_; - _zz_183_[7] = _zz_182_; - _zz_183_[6] = _zz_182_; - _zz_183_[5] = _zz_182_; - _zz_183_[4] = _zz_182_; - _zz_183_[3] = _zz_182_; - _zz_183_[2] = _zz_182_; - _zz_183_[1] = _zz_182_; - _zz_183_[0] = _zz_182_; + _zz_124[19] = _zz_123; + _zz_124[18] = _zz_123; + _zz_124[17] = _zz_123; + _zz_124[16] = _zz_123; + _zz_124[15] = _zz_123; + _zz_124[14] = _zz_123; + _zz_124[13] = _zz_123; + _zz_124[12] = _zz_123; + _zz_124[11] = _zz_123; + _zz_124[10] = _zz_123; + _zz_124[9] = _zz_123; + _zz_124[8] = _zz_123; + _zz_124[7] = _zz_123; + _zz_124[6] = _zz_123; + _zz_124[5] = _zz_123; + _zz_124[4] = _zz_123; + _zz_124[3] = _zz_123; + _zz_124[2] = _zz_123; + _zz_124[1] = _zz_123; + _zz_124[0] = _zz_123; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_183_,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_124,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_185_,{{{_zz_532_,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_187_,{{{_zz_533_,_zz_534_},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_126,{{{_zz_472,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_128,{{{_zz_473,_zz_474},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_316_}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_263}; end end endcase end - assign _zz_184_ = _zz_314_[19]; - always @ (*) begin - _zz_185_[10] = _zz_184_; - _zz_185_[9] = _zz_184_; - _zz_185_[8] = _zz_184_; - _zz_185_[7] = _zz_184_; - _zz_185_[6] = _zz_184_; - _zz_185_[5] = _zz_184_; - _zz_185_[4] = _zz_184_; - _zz_185_[3] = _zz_184_; - _zz_185_[2] = _zz_184_; - _zz_185_[1] = _zz_184_; - _zz_185_[0] = _zz_184_; - end - - assign _zz_186_ = _zz_315_[11]; - always @ (*) begin - _zz_187_[18] = _zz_186_; - _zz_187_[17] = _zz_186_; - _zz_187_[16] = _zz_186_; - _zz_187_[15] = _zz_186_; - _zz_187_[14] = _zz_186_; - _zz_187_[13] = _zz_186_; - _zz_187_[12] = _zz_186_; - _zz_187_[11] = _zz_186_; - _zz_187_[10] = _zz_186_; - _zz_187_[9] = _zz_186_; - _zz_187_[8] = _zz_186_; - _zz_187_[7] = _zz_186_; - _zz_187_[6] = _zz_186_; - _zz_187_[5] = _zz_186_; - _zz_187_[4] = _zz_186_; - _zz_187_[3] = _zz_186_; - _zz_187_[2] = _zz_186_; - _zz_187_[1] = _zz_186_; - _zz_187_[0] = _zz_186_; + assign _zz_125 = _zz_261[19]; + always @ (*) begin + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; + end + + assign _zz_127 = _zz_262[11]; + always @ (*) begin + _zz_128[18] = _zz_127; + _zz_128[17] = _zz_127; + _zz_128[16] = _zz_127; + _zz_128[15] = _zz_127; + _zz_128[14] = _zz_127; + _zz_128[13] = _zz_127; + _zz_128[12] = _zz_127; + _zz_128[11] = _zz_127; + _zz_128[10] = _zz_127; + _zz_128[9] = _zz_127; + _zz_128[8] = _zz_127; + _zz_128[7] = _zz_127; + _zz_128[6] = _zz_127; + _zz_128[5] = _zz_127; + _zz_128[4] = _zz_127; + _zz_128[3] = _zz_127; + _zz_128[2] = _zz_127; + _zz_128[1] = _zz_127; + _zz_128[0] = _zz_127; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_31_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign CsrPlugin_misa_base = (2'b01); - assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); - assign _zz_188_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_189_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_190_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign _zz_129 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_130 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_131 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_191_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_192_ = _zz_317_[0]; - assign _zz_193_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_194_ = _zz_319_[0]; + assign _zz_132 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_133 = _zz_264[0]; + assign _zz_134 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_135 = _zz_266[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_233_)begin + if(_zz_180)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4090,7 +3736,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_239_)begin + if(_zz_184)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4111,9 +3757,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusCachedPlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -4137,7 +3784,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; @@ -4148,7 +3795,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4159,52 +3806,45 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - assign execute_CsrPlugin_inWfi = 1'b0; - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000001 : begin + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_197)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4223,20 +3863,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_253_)begin + if(_zz_198)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_253_)begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_198)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -4244,53 +3884,24 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_202_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_203_; - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_197)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_197)begin + execute_CsrPlugin_readInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_263_) + case(_zz_210) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4301,10 +3912,11 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; always @ (*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_221_)begin - if(_zz_237_)begin + if(_zz_168)begin + if(_zz_183)begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end @@ -4317,23 +3929,23 @@ module VexRiscv ( end end - assign memory_MulDivIterativePlugin_mul_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == (6'b100000)); - assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); + assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); + assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); always @ (*) begin if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_322_); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_269); end if(memory_MulDivIterativePlugin_mul_counter_willClear)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end end always @ (*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_222_)begin - if(_zz_238_)begin + if(_zz_169)begin + if(_zz_199)begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end @@ -4341,44 +3953,44 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_254_)begin + if(_zz_200)begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end - assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == (6'b100001)); + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); always @ (*) begin if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin - memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_330_); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_277); end if(memory_MulDivIterativePlugin_div_counter_willClear)begin - memory_MulDivIterativePlugin_div_counter_valueNext = (6'b000000); + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end end - assign _zz_195_ = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign _zz_196_ = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_195_[31]}; - assign _zz_197_ = (_zz_196_ - _zz_331_); - assign _zz_198_ = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_199_ = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_200_ = ((execute_IS_MUL && _zz_199_) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_136 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_136[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_278); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_279 : _zz_280); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_281[31:0]; + assign _zz_137 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_138 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_139 = ((execute_IS_MUL && _zz_138) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_201_[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_201_[31 : 0] = execute_RS1; + _zz_140[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_140[31 : 0] = execute_RS1; end - assign _zz_203_ = (_zz_202_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_203_ != (32'b00000000000000000000000000000000)); + assign _zz_142 = (_zz_141 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_142 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_255_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_201) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end @@ -4391,7 +4003,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_204_))begin + if((! _zz_143))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4403,10 +4015,8 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_255_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_201) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; end @@ -4418,37 +4028,37 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign _zz_25_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_24_ = decode_BRANCH_CTRL; - assign _zz_97_ = _zz_79_; - assign _zz_33_ = decode_to_execute_BRANCH_CTRL; - assign _zz_22_ = decode_SHIFT_CTRL; - assign _zz_20_ = _zz_61_; - assign _zz_38_ = decode_to_execute_SHIFT_CTRL; - assign _zz_19_ = decode_ENV_CTRL; - assign _zz_16_ = execute_ENV_CTRL; - assign _zz_14_ = memory_ENV_CTRL; - assign _zz_17_ = _zz_63_; - assign _zz_27_ = decode_to_execute_ENV_CTRL; - assign _zz_26_ = execute_to_memory_ENV_CTRL; - assign _zz_30_ = memory_to_writeBack_ENV_CTRL; - assign _zz_12_ = decode_ALU_BITWISE_CTRL; - assign _zz_10_ = _zz_65_; - assign _zz_50_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_9_ = decode_ALU_CTRL; - assign _zz_7_ = _zz_69_; - assign _zz_48_ = decode_to_execute_ALU_CTRL; - assign _zz_6_ = decode_SRC2_CTRL; - assign _zz_4_ = _zz_70_; - assign _zz_43_ = decode_to_execute_SRC2_CTRL; - assign _zz_3_ = decode_SRC1_CTRL; - assign _zz_1_ = _zz_76_; - assign _zz_45_ = decode_to_execute_SRC1_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign _zz_24 = decode_SRC1_CTRL; + assign _zz_22 = _zz_46; + assign _zz_34 = decode_to_execute_SRC1_CTRL; + assign _zz_21 = decode_ALU_CTRL; + assign _zz_19 = _zz_45; + assign _zz_35 = decode_to_execute_ALU_CTRL; + assign _zz_18 = decode_SRC2_CTRL; + assign _zz_16 = _zz_44; + assign _zz_33 = decode_to_execute_SRC2_CTRL; + assign _zz_15 = decode_ALU_BITWISE_CTRL; + assign _zz_13 = _zz_43; + assign _zz_36 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_12 = decode_SHIFT_CTRL; + assign _zz_10 = _zz_42; + assign _zz_31 = decode_to_execute_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_48 = _zz_41; + assign _zz_28 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_40; + assign _zz_26 = decode_to_execute_ENV_CTRL; + assign _zz_25 = execute_to_memory_ENV_CTRL; + assign _zz_27 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -4467,15 +4077,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_205_) - 3'b000 : begin - end - 3'b001 : begin - end - 3'b010 : begin - end - 3'b011 : begin - end + case(_zz_144) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4484,28 +4086,92 @@ module VexRiscv ( endcase end - assign iBusWishbone_ADR = {_zz_350_,_zz_206_}; - assign iBusWishbone_CTI = ((_zz_206_ == (3'b111)) ? (3'b111) : (3'b010)); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); + always @ (*) begin + _zz_145 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_145[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_145[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_145[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_146 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_146[11 : 11] = CsrPlugin_mip_MEIP; + _zz_146[7 : 7] = CsrPlugin_mip_MTIP; + _zz_146[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_147 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_147[11 : 11] = CsrPlugin_mie_MEIE; + _zz_147[7 : 7] = CsrPlugin_mie_MTIE; + _zz_147[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_148 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_148[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_149 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_149[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_149[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_150 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_150[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_151 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_151[31 : 0] = _zz_141; + end + end + + always @ (*) begin + _zz_152 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_152[31 : 0] = _zz_142; + end + end + + assign execute_CsrPlugin_readData = (((_zz_145 | _zz_146) | (_zz_147 | _zz_148)) | ((_zz_149 | _zz_150) | (_zz_151 | _zz_152))); + assign iBusWishbone_ADR = {_zz_297,_zz_153}; + assign iBusWishbone_CTI = ((_zz_153 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_256_)begin + if(_zz_202)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_256_)begin + if(_zz_202)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_207_; + assign iBus_rsp_valid = _zz_154; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; @@ -4515,26 +4181,26 @@ module VexRiscv ( assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); - assign dBusWishbone_CTI = (3'b000); - assign dBusWishbone_BTE = (2'b00); + assign dBusWishbone_CTI = 3'b000; + assign dBusWishbone_BTE = 2'b00; always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_208_ = (4'b0001); + _zz_155 = 4'b0001; end 2'b01 : begin - _zz_208_ = (4'b0011); + _zz_155 = 4'b0011; end default : begin - _zz_208_ = (4'b1111); + _zz_155 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = _zz_351_[3:0]; + dBusWishbone_SEL = (_zz_155 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin - dBusWishbone_SEL = (4'b1111); + dBusWishbone_SEL = 4'b1111; end end @@ -4549,24 +4215,24 @@ module VexRiscv ( always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_114_ <= 1'b0; - _zz_116_ <= 1'b0; + _zz_61 <= 1'b0; + _zz_63 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_129_; - IBusCachedPlugin_rspCounter <= (32'b00000000000000000000000000000000); - _zz_151_ <= 1'b1; + IBusCachedPlugin_rspCounter <= _zz_76; + IBusCachedPlugin_rspCounter <= 32'h0; + _zz_98 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_163_ <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -4575,24 +4241,31 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_MulDivIterativePlugin_mul_counter_value <= (6'b000000); - memory_MulDivIterativePlugin_div_counter_value <= (6'b000000); - _zz_202_ <= (32'b00000000000000000000000000000000); + memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + _zz_141 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_205_ <= (3'b000); - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_206_ <= (3'b000); - _zz_207_ <= 1'b0; + _zz_144 <= 3'b000; + _zz_153 <= 3'b000; + _zz_154 <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_corrected || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin @@ -4601,75 +4274,89 @@ module VexRiscv ( if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetcherflushIt) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_114_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_61 <= 1'b0; end - if(_zz_112_)begin - _zz_114_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + if(_zz_59)begin + _zz_61 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_116_ <= IBusCachedPlugin_iBusRsp_stages_1_output_valid; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_63 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin - _zz_116_ <= 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_63 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetcherflushIt)begin + if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusCachedPlugin_fetcherflushIt)begin - IBusCachedPlugin_injector_decodeRemoved <= 1'b0; - end if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + (32'b00000000000000000000000000000001)); - end - _zz_151_ <= 1'b0; - if(_zz_227_)begin - if(_zz_234_)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + _zz_98 <= 1'b0; + if(_zz_174)begin + if(_zz_203)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -4679,7 +4366,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_163_ <= _zz_162_; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4701,19 +4388,38 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_257_)begin - if(_zz_258_)begin + if(_zz_204)begin + if(_zz_205)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_259_)begin + if(_zz_206)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_260_)begin + if(_zz_207)begin CsrPlugin_interrupt_valid <= 1'b1; end end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_240_)begin + if(_zz_185)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4724,10 +4430,10 @@ module VexRiscv ( end endcase end - if(_zz_241_)begin - case(_zz_243_) + if(_zz_186)begin + case(_zz_188) 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; end @@ -4735,15 +4441,9 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_190_,{_zz_189_,_zz_188_}} != (3'b000)); + execute_CsrPlugin_wfiWake <= (({_zz_131,{_zz_130,_zz_129}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_36_; - end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -4762,71 +4462,55 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_205_) + case(_zz_144) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_205_ <= (3'b001); + _zz_144 <= 3'b001; end end 3'b001 : begin - _zz_205_ <= (3'b010); + _zz_144 <= 3'b010; end 3'b010 : begin - _zz_205_ <= (3'b011); + _zz_144 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_205_ <= (3'b100); + _zz_144 <= 3'b100; end end 3'b100 : begin - _zz_205_ <= (3'b000); + _zz_144 <= 3'b000; end default : begin end endcase - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_202_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_344_[0]; - CsrPlugin_mstatus_MIE <= _zz_345_[0]; - end - end - 12'b001101000001 : begin - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_347_[0]; - CsrPlugin_mie_MTIE <= _zz_348_[0]; - CsrPlugin_mie_MSIE <= _zz_349_[0]; - end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_291[0]; + CsrPlugin_mstatus_MIE <= _zz_292[0]; end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_294[0]; + CsrPlugin_mie_MTIE <= _zz_295[0]; + CsrPlugin_mie_MSIE <= _zz_296[0]; end - default : begin + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_141 <= execute_CsrPlugin_writeData[31 : 0]; end - endcase - if(_zz_256_)begin + end + if(_zz_202)begin if(iBusWishbone_ACK)begin - _zz_206_ <= (_zz_206_ + (3'b001)); + _zz_153 <= (_zz_153 + 3'b001); end end - _zz_207_ <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_261_)begin + _zz_154 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_208)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -4838,63 +4522,55 @@ module VexRiscv ( always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_117_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_64 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin - $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); - end - if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin - $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); - end - if(_zz_227_)begin - if(_zz_234_)begin - execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + if(_zz_174)begin + if(_zz_203)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - if(_zz_162_)begin - _zz_164_ <= _zz_51_[11 : 7]; - _zz_165_ <= _zz_81_; - end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_233_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_192_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_192_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_180)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_133 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_133 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_239_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_194_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_194_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_184)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_135 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_135 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_257_)begin - if(_zz_258_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_204)begin + if(_zz_205)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_259_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_206)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_260_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_207)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_240_)begin + if(_zz_185)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4908,66 +4584,81 @@ module VexRiscv ( end endcase end - if(_zz_221_)begin - if(_zz_237_)begin + if(_zz_168)begin + if(_zz_183)begin memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_323_,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_270,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end - if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin memory_MulDivIterativePlugin_div_done <= 1'b1; end if((! memory_arbitration_isStuck))begin memory_MulDivIterativePlugin_div_done <= 1'b0; end - if(_zz_222_)begin - if(_zz_238_)begin - memory_MulDivIterativePlugin_rs1[31 : 0] <= _zz_332_[31:0]; - memory_MulDivIterativePlugin_accumulator[31 : 0] <= ((! _zz_197_[32]) ? _zz_333_ : _zz_334_); - if((memory_MulDivIterativePlugin_div_counter_value == (6'b100000)))begin - memory_MulDivIterativePlugin_div_result <= _zz_335_[31:0]; + if(_zz_169)begin + if(_zz_199)begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_result <= _zz_282[31:0]; end end end - if(_zz_254_)begin - memory_MulDivIterativePlugin_accumulator <= (65'b00000000000000000000000000000000000000000000000000000000000000000); - memory_MulDivIterativePlugin_rs1 <= ((_zz_200_ ? (~ _zz_201_) : _zz_201_) + _zz_341_); - memory_MulDivIterativePlugin_rs2 <= ((_zz_199_ ? (~ execute_RS2) : execute_RS2) + _zz_343_); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_200_ ^ (_zz_199_ && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == (32'b00000000000000000000000000000000)) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(_zz_200)begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_139 ? (~ _zz_140) : _zz_140) + _zz_288); + memory_MulDivIterativePlugin_rs2 <= ((_zz_138 ? (~ execute_RS2) : execute_RS2) + _zz_290); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_139 ^ (_zz_138 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_32; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin - decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + decode_to_execute_FORMAL_PC_NEXT <= _zz_50; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_49; end if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + decode_to_execute_SRC1_CTRL <= _zz_23; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_23_; + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_MUL <= decode_IS_MUL; + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress; - execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess; - execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead; - execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite; - execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute; - execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception; - execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_20; end if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + decode_to_execute_SRC2_CTRL <= _zz_17; end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; @@ -4979,67 +4670,58 @@ module VexRiscv ( memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_21_; + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_42_; - end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_18_; + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_15_; + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_13_; + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + decode_to_execute_ALU_BITWISE_CTRL <= _zz_14; end if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + decode_to_execute_SHIFT_CTRL <= _zz_11; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_8; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; end if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + decode_to_execute_ENV_CTRL <= _zz_6; end if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + execute_to_memory_ENV_CTRL <= _zz_3; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + memory_to_writeBack_ENV_CTRL <= _zz_1; end if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + decode_to_execute_IS_MUL <= decode_IS_MUL; end if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + execute_to_memory_IS_MUL <= execute_IS_MUL; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_11_; + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_DIV <= decode_IS_DIV; @@ -5048,22 +4730,28 @@ module VexRiscv ( execute_to_memory_IS_DIV <= execute_IS_DIV; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_8_; + decode_to_execute_RS1 <= decode_RS1; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + decode_to_execute_RS2 <= decode_RS2; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_5_; + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; end if((! memory_arbitration_isStuck))begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; @@ -5072,72 +4760,79 @@ module VexRiscv ( memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end if((! memory_arbitration_isStuck))begin - execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; + execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; + execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; + execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; + execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; + execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; + execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; + execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; + execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; end if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37_; + execute_to_memory_REGFILE_WRITE_DATA <= _zz_30; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_29; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_2_; + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end if((! execute_arbitration_isStuck))begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_99_; + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_98_; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end - end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_346_[0]; - end - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b001100000100 : begin + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_293[0]; end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - default : begin + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end - endcase + end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_261_)begin + if(_zz_208)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; @@ -5151,12 +4846,12 @@ module VexRiscv ( DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)) || IBusCachedPlugin_incomingInstruction); + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_81_; + DebugPlugin_busReadDataReg <= _zz_47; end - _zz_204_ <= debug_bus_cmd_payload_address[2]; - if(_zz_235_)begin + _zz_143 <= debug_bus_cmd_payload_address[2]; + if(_zz_181)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -5174,8 +4869,8 @@ module VexRiscv ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_255_) - 6'b000000 : begin + case(_zz_201) + 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; if(debug_bus_cmd_payload_data[16])begin @@ -5198,19 +4893,17 @@ module VexRiscv ( end end end - 6'b000001 : begin - end default : begin end endcase end - if(_zz_235_)begin - if(_zz_236_)begin + if(_zz_181)begin + if(_zz_182)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_242_)begin + if(_zz_187)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end @@ -5218,5 +4911,295 @@ module VexRiscv ( end end + endmodule +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_9, + input [31:0] _zz_10, + input clk, + input reset +); + reg [31:0] _zz_11; + reg [22:0] _zz_12; + wire _zz_13; + wire _zz_14; + wire [0:0] _zz_15; + wire [0:0] _zz_16; + wire [22:0] _zz_17; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [8:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [8:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; + + assign _zz_13 = (! lineLoader_flushCounter[6]); + assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_15 = _zz_8[0 : 0]; + assign _zz_16 = _zz_8[1 : 1]; + assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_11 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_12 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_13)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_12; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_14)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_13)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_3 <= lineLoader_flushCounter[6]; + if(_zz_14)begin + lineLoader_flushCounter <= 7'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + if((_zz_9 != 3'b000))begin + io_cpu_fetch_data_regNextWhen <= _zz_10; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v index 0fda9d8..93bdea0 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v @@ -1,36 +1,19 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:06:53 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - `define EnvCtrlEnum_defaultEncoding_type [1:0] `define EnvCtrlEnum_defaultEncoding_NONE 2'b00 `define EnvCtrlEnum_defaultEncoding_XRET 2'b01 `define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - `define BranchCtrlEnum_defaultEncoding_type [1:0] `define BranchCtrlEnum_defaultEncoding_INC 2'b00 `define BranchCtrlEnum_defaultEncoding_B 2'b01 `define BranchCtrlEnum_defaultEncoding_JAL 2'b10 `define BranchCtrlEnum_defaultEncoding_JALR 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - `define ShiftCtrlEnum_defaultEncoding_type [1:0] `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 `define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 @@ -42,1584 +25,1491 @@ `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 `define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 -module StreamFifoLowLatency ( - input io_push_valid, - output io_push_ready, - input io_push_payload_error, - input [31:0] io_push_payload_inst, - output reg io_pop_valid, - input io_pop_ready, - output reg io_pop_payload_error, - output reg [31:0] io_pop_payload_inst, - input io_flush, - output [0:0] io_occupancy, - input clk, - input reset); - wire _zz_5_; - wire [0:0] _zz_6_; - reg _zz_1_; - reg pushPtr_willIncrement; - reg pushPtr_willClear; - wire pushPtr_willOverflowIfInc; - wire pushPtr_willOverflow; - reg popPtr_willIncrement; - reg popPtr_willClear; - wire popPtr_willOverflowIfInc; - wire popPtr_willOverflow; - wire ptrMatch; - reg risingOccupancy; - wire empty; - wire full; - wire pushing; - wire popping; - wire [32:0] _zz_2_; - wire [32:0] _zz_3_; - reg [32:0] _zz_4_; - assign _zz_5_ = (! empty); - assign _zz_6_ = _zz_2_[0 : 0]; - always @ (*) begin - _zz_1_ = 1'b0; - if(pushing)begin - _zz_1_ = 1'b1; - end - end - - always @ (*) begin - pushPtr_willIncrement = 1'b0; - if(pushing)begin - pushPtr_willIncrement = 1'b1; - end - end - - always @ (*) begin - pushPtr_willClear = 1'b0; - if(io_flush)begin - pushPtr_willClear = 1'b1; - end - end - - assign pushPtr_willOverflowIfInc = 1'b1; - assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); - always @ (*) begin - popPtr_willIncrement = 1'b0; - if(popping)begin - popPtr_willIncrement = 1'b1; - end - end - - always @ (*) begin - popPtr_willClear = 1'b0; - if(io_flush)begin - popPtr_willClear = 1'b1; - end - end - - assign popPtr_willOverflowIfInc = 1'b1; - assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); - assign ptrMatch = 1'b1; - assign empty = (ptrMatch && (! risingOccupancy)); - assign full = (ptrMatch && risingOccupancy); - assign pushing = (io_push_valid && io_push_ready); - assign popping = (io_pop_valid && io_pop_ready); - assign io_push_ready = (! full); - always @ (*) begin - if(_zz_5_)begin - io_pop_valid = 1'b1; - end else begin - io_pop_valid = io_push_valid; - end - end - - assign _zz_2_ = _zz_3_; - always @ (*) begin - if(_zz_5_)begin - io_pop_payload_error = _zz_6_[0]; - end else begin - io_pop_payload_error = io_push_payload_error; - end - end - - always @ (*) begin - if(_zz_5_)begin - io_pop_payload_inst = _zz_2_[32 : 1]; - end else begin - io_pop_payload_inst = io_push_payload_inst; - end - end +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - assign io_occupancy = (risingOccupancy && ptrMatch); - assign _zz_3_ = _zz_4_; - always @ (posedge clk) begin - if(reset) begin - risingOccupancy <= 1'b0; - end else begin - if((pushing != popping))begin - risingOccupancy <= pushing; - end - if(io_flush)begin - risingOccupancy <= 1'b0; - end - end - end +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - always @ (posedge clk) begin - if(_zz_1_)begin - _zz_4_ <= {io_push_payload_inst,io_push_payload_error}; - end - end +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -endmodule module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - output iBusWishbone_CYC, - output iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output reg [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset); - reg [31:0] _zz_161_; - reg [31:0] _zz_162_; - reg [31:0] _zz_163_; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; - wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; - wire _zz_164_; - wire _zz_165_; - wire _zz_166_; - wire _zz_167_; - wire _zz_168_; - wire _zz_169_; - wire _zz_170_; - wire [1:0] _zz_171_; - wire _zz_172_; - wire _zz_173_; - wire _zz_174_; - wire _zz_175_; - wire _zz_176_; - wire _zz_177_; - wire _zz_178_; - wire _zz_179_; - wire _zz_180_; - wire _zz_181_; - wire _zz_182_; - wire _zz_183_; - wire _zz_184_; - wire _zz_185_; - wire _zz_186_; - wire _zz_187_; - wire [1:0] _zz_188_; - wire _zz_189_; - wire [3:0] _zz_190_; - wire [2:0] _zz_191_; - wire [31:0] _zz_192_; - wire [2:0] _zz_193_; - wire [0:0] _zz_194_; - wire [2:0] _zz_195_; - wire [0:0] _zz_196_; - wire [2:0] _zz_197_; - wire [0:0] _zz_198_; - wire [2:0] _zz_199_; - wire [0:0] _zz_200_; - wire [2:0] _zz_201_; - wire [2:0] _zz_202_; - wire [0:0] _zz_203_; - wire [0:0] _zz_204_; - wire [0:0] _zz_205_; - wire [0:0] _zz_206_; - wire [0:0] _zz_207_; - wire [0:0] _zz_208_; - wire [0:0] _zz_209_; - wire [0:0] _zz_210_; - wire [0:0] _zz_211_; - wire [0:0] _zz_212_; - wire [0:0] _zz_213_; - wire [0:0] _zz_214_; - wire [2:0] _zz_215_; - wire [4:0] _zz_216_; - wire [11:0] _zz_217_; - wire [11:0] _zz_218_; - wire [31:0] _zz_219_; - wire [31:0] _zz_220_; - wire [31:0] _zz_221_; - wire [31:0] _zz_222_; - wire [31:0] _zz_223_; - wire [31:0] _zz_224_; - wire [31:0] _zz_225_; - wire [31:0] _zz_226_; - wire [32:0] _zz_227_; - wire [19:0] _zz_228_; - wire [11:0] _zz_229_; - wire [11:0] _zz_230_; - wire [1:0] _zz_231_; - wire [1:0] _zz_232_; - wire [1:0] _zz_233_; - wire [1:0] _zz_234_; - wire [0:0] _zz_235_; - wire [0:0] _zz_236_; - wire [0:0] _zz_237_; - wire [0:0] _zz_238_; - wire [0:0] _zz_239_; - wire [0:0] _zz_240_; - wire [6:0] _zz_241_; - wire _zz_242_; - wire _zz_243_; - wire [1:0] _zz_244_; - wire [31:0] _zz_245_; - wire [31:0] _zz_246_; - wire [31:0] _zz_247_; - wire _zz_248_; - wire [0:0] _zz_249_; - wire [0:0] _zz_250_; - wire _zz_251_; - wire [0:0] _zz_252_; - wire [18:0] _zz_253_; - wire [31:0] _zz_254_; - wire [31:0] _zz_255_; - wire [31:0] _zz_256_; - wire [31:0] _zz_257_; - wire [31:0] _zz_258_; - wire [31:0] _zz_259_; - wire _zz_260_; - wire [1:0] _zz_261_; - wire [1:0] _zz_262_; - wire _zz_263_; - wire [0:0] _zz_264_; - wire [14:0] _zz_265_; - wire [31:0] _zz_266_; - wire [31:0] _zz_267_; - wire [31:0] _zz_268_; - wire [31:0] _zz_269_; - wire [0:0] _zz_270_; - wire [0:0] _zz_271_; - wire [0:0] _zz_272_; - wire [0:0] _zz_273_; - wire _zz_274_; - wire [0:0] _zz_275_; - wire [11:0] _zz_276_; - wire [31:0] _zz_277_; - wire [31:0] _zz_278_; - wire [31:0] _zz_279_; - wire _zz_280_; - wire [0:0] _zz_281_; - wire [1:0] _zz_282_; - wire [0:0] _zz_283_; - wire [0:0] _zz_284_; - wire [1:0] _zz_285_; - wire [1:0] _zz_286_; - wire _zz_287_; - wire [0:0] _zz_288_; - wire [8:0] _zz_289_; - wire [31:0] _zz_290_; - wire [31:0] _zz_291_; - wire [31:0] _zz_292_; - wire [31:0] _zz_293_; - wire [31:0] _zz_294_; - wire [31:0] _zz_295_; - wire [31:0] _zz_296_; - wire [31:0] _zz_297_; - wire _zz_298_; - wire _zz_299_; - wire [0:0] _zz_300_; - wire [0:0] _zz_301_; - wire [1:0] _zz_302_; - wire [1:0] _zz_303_; - wire _zz_304_; - wire [0:0] _zz_305_; - wire [5:0] _zz_306_; - wire [31:0] _zz_307_; - wire [31:0] _zz_308_; - wire [31:0] _zz_309_; - wire [31:0] _zz_310_; - wire _zz_311_; - wire _zz_312_; - wire [1:0] _zz_313_; - wire [1:0] _zz_314_; - wire _zz_315_; - wire [0:0] _zz_316_; - wire [2:0] _zz_317_; - wire [31:0] _zz_318_; - wire [31:0] _zz_319_; - wire [31:0] _zz_320_; - wire [31:0] _zz_321_; - wire _zz_322_; - wire [0:0] _zz_323_; - wire [0:0] _zz_324_; - wire [0:0] _zz_325_; - wire [1:0] _zz_326_; - wire [5:0] _zz_327_; - wire [5:0] _zz_328_; - wire _zz_329_; - wire _zz_330_; - wire [31:0] _zz_331_; - wire [31:0] _zz_332_; - wire [31:0] _zz_333_; - wire [31:0] _zz_334_; - wire [31:0] _zz_335_; - wire [31:0] _zz_336_; - wire [31:0] _zz_337_; - wire _zz_338_; - wire [0:0] _zz_339_; - wire [2:0] _zz_340_; - wire [31:0] _zz_341_; - wire [31:0] _zz_342_; - wire _zz_343_; - wire _zz_344_; - wire [31:0] _zz_345_; - wire [31:0] _zz_346_; - wire [31:0] _zz_347_; - wire _zz_348_; - wire [0:0] _zz_349_; - wire [12:0] _zz_350_; - wire [31:0] _zz_351_; - wire [31:0] _zz_352_; - wire [31:0] _zz_353_; - wire _zz_354_; - wire [0:0] _zz_355_; - wire [6:0] _zz_356_; - wire [31:0] _zz_357_; - wire [31:0] _zz_358_; - wire [31:0] _zz_359_; - wire _zz_360_; - wire [0:0] _zz_361_; - wire [0:0] _zz_362_; - wire [31:0] decode_RS1; - wire execute_BRANCH_DO; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_SRC2_FORCE_ZERO; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_1_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_2_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_3_; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire decode_CSR_WRITE_OPCODE; - wire [31:0] execute_BRANCH_CALC; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire decode_SRC_LESS_UNSIGNED; - wire decode_MEMORY_STORE; - wire [31:0] memory_MEMORY_READ_DATA; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire decode_IS_CSR; - wire [31:0] decode_RS2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_11_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_12_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_13_; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_14_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_15_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_16_; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_17_; - wire `AluCtrlEnum_defaultEncoding_type _zz_18_; - wire `AluCtrlEnum_defaultEncoding_type _zz_19_; - wire decode_CSR_READ_OPCODE; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_20_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_21_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_22_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_23_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_24_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27_; - wire _zz_28_; - wire _zz_29_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_30_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_31_; - wire [31:0] execute_PC; - wire [31:0] execute_RS1; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_32_; - wire _zz_33_; - wire decode_RS2_USE; - wire decode_RS1_USE; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] _zz_34_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_35_; - wire _zz_36_; - wire [31:0] _zz_37_; - wire [31:0] _zz_38_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_39_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_40_; - wire [31:0] _zz_41_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_42_; - wire [31:0] _zz_43_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_44_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_45_; - wire [31:0] _zz_46_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47_; - wire [31:0] _zz_48_; - wire _zz_49_; - reg _zz_50_; - wire [31:0] _zz_51_; - wire [31:0] _zz_52_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_53_; - wire _zz_54_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_55_; - wire _zz_56_; - wire _zz_57_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_59_; - wire `AluCtrlEnum_defaultEncoding_type _zz_60_; - wire _zz_61_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_62_; - wire _zz_63_; - wire _zz_64_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_65_; - wire _zz_66_; - wire _zz_67_; - wire _zz_68_; - wire _zz_69_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_70_; - wire _zz_71_; - wire writeBack_MEMORY_STORE; - reg [31:0] _zz_72_; - wire writeBack_MEMORY_ENABLE; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP_physicalAddress; - wire memory_MMU_RSP_isIoAccess; - wire memory_MMU_RSP_allowRead; - wire memory_MMU_RSP_allowWrite; - wire memory_MMU_RSP_allowExecute; - wire memory_MMU_RSP_exception; - wire memory_MMU_RSP_refilling; - wire [31:0] memory_PC; - wire memory_ALIGNEMENT_FAULT; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_STORE; - wire memory_MEMORY_ENABLE; - wire [31:0] _zz_73_; - wire [31:0] _zz_74_; - wire _zz_75_; - wire _zz_76_; - wire _zz_77_; - wire _zz_78_; - wire _zz_79_; - wire _zz_80_; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP_physicalAddress; - wire execute_MMU_RSP_isIoAccess; - wire execute_MMU_RSP_allowRead; - wire execute_MMU_RSP_allowWrite; - wire execute_MMU_RSP_allowExecute; - wire execute_MMU_RSP_exception; - wire execute_MMU_RSP_refilling; - wire _zz_81_; - wire [31:0] execute_SRC_ADD; - wire [1:0] _zz_82_; - wire [31:0] execute_RS2; - wire [31:0] execute_INSTRUCTION; - wire execute_MEMORY_STORE; - wire execute_MEMORY_ENABLE; - wire execute_ALIGNEMENT_FAULT; - wire _zz_83_; - wire decode_MEMORY_ENABLE; - reg [31:0] _zz_84_; - reg [31:0] _zz_85_; - wire [31:0] decode_PC; - wire [31:0] _zz_86_; - wire [31:0] _zz_87_; - wire [31:0] _zz_88_; - wire [31:0] decode_INSTRUCTION; - wire [31:0] _zz_89_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - reg decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - wire decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - wire execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - wire execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - wire writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - wire writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusSimplePlugin_fetcherHalt; - reg IBusSimplePlugin_fetcherflushIt; - reg IBusSimplePlugin_incomingInstruction; - wire IBusSimplePlugin_pcValids_0; - wire IBusSimplePlugin_pcValids_1; - wire IBusSimplePlugin_pcValids_2; - wire IBusSimplePlugin_pcValids_3; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - wire [31:0] iBus_cmd_payload_pc; - wire iBus_rsp_valid; - wire iBus_rsp_payload_error; - wire [31:0] iBus_rsp_payload_inst; - wire IBusSimplePlugin_decodeExceptionPort_valid; - reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; - wire IBusSimplePlugin_mmuBus_cmd_isValid; - wire [31:0] IBusSimplePlugin_mmuBus_cmd_virtualAddress; - wire IBusSimplePlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire IBusSimplePlugin_mmuBus_rsp_allowRead; - wire IBusSimplePlugin_mmuBus_rsp_allowWrite; - wire IBusSimplePlugin_mmuBus_rsp_allowExecute; - wire IBusSimplePlugin_mmuBus_rsp_exception; - wire IBusSimplePlugin_mmuBus_rsp_refilling; - wire IBusSimplePlugin_mmuBus_end; - wire IBusSimplePlugin_mmuBus_busy; - wire IBusSimplePlugin_redoBranch_valid; - wire [31:0] IBusSimplePlugin_redoBranch_payload; - reg DBusSimplePlugin_memoryExceptionPort_valid; - reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; - wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_isValid; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - wire CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - wire CsrPlugin_allowInterrupts; - wire CsrPlugin_allowException; - wire IBusSimplePlugin_jump_pcLoad_valid; - wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; - wire [3:0] _zz_90_; - wire [3:0] _zz_91_; - wire _zz_92_; - wire _zz_93_; - wire _zz_94_; - wire IBusSimplePlugin_fetchPc_output_valid; - wire IBusSimplePlugin_fetchPc_output_ready; - wire [31:0] IBusSimplePlugin_fetchPc_output_payload; - reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusSimplePlugin_fetchPc_corrected; - reg IBusSimplePlugin_fetchPc_pcRegPropagate; - reg IBusSimplePlugin_fetchPc_booted; - reg IBusSimplePlugin_fetchPc_inc; - reg [31:0] IBusSimplePlugin_fetchPc_pc; - reg IBusSimplePlugin_iBusRsp_stages_0_input_valid; - reg IBusSimplePlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; - wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; - wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; - reg IBusSimplePlugin_iBusRsp_stages_0_halt; - wire IBusSimplePlugin_iBusRsp_stages_0_inputSample; - wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; - wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; - wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; - wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; - wire IBusSimplePlugin_iBusRsp_stages_1_halt; - wire IBusSimplePlugin_iBusRsp_stages_1_inputSample; - wire _zz_95_; - wire _zz_96_; - wire _zz_97_; - wire _zz_98_; - reg _zz_99_; - reg IBusSimplePlugin_iBusRsp_readyForError; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; - wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; - wire IBusSimplePlugin_injector_decodeInput_valid; - wire IBusSimplePlugin_injector_decodeInput_ready; - wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; - wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; - wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; - reg _zz_100_; - reg [31:0] _zz_101_; - reg _zz_102_; - reg [31:0] _zz_103_; - reg _zz_104_; - reg IBusSimplePlugin_injector_nextPcCalc_valids_0; - reg IBusSimplePlugin_injector_nextPcCalc_valids_1; - reg IBusSimplePlugin_injector_nextPcCalc_valids_2; - reg IBusSimplePlugin_injector_nextPcCalc_valids_3; - reg IBusSimplePlugin_injector_nextPcCalc_valids_4; - reg IBusSimplePlugin_injector_decodeRemoved; - reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; - reg IBusSimplePlugin_cmd_valid; - wire IBusSimplePlugin_cmd_ready; - wire [31:0] IBusSimplePlugin_cmd_payload_pc; - reg [2:0] IBusSimplePlugin_pendingCmd; - wire [2:0] IBusSimplePlugin_pendingCmdNext; - reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; - reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; - reg IBusSimplePlugin_mmu_joinCtx_allowRead; - reg IBusSimplePlugin_mmu_joinCtx_allowWrite; - reg IBusSimplePlugin_mmu_joinCtx_allowExecute; - reg IBusSimplePlugin_mmu_joinCtx_exception; - reg IBusSimplePlugin_mmu_joinCtx_refilling; - reg [2:0] IBusSimplePlugin_rspJoin_discardCounter; - wire IBusSimplePlugin_rspJoin_rspBufferOutput_valid; - wire IBusSimplePlugin_rspJoin_rspBufferOutput_ready; - wire IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; - wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; - wire iBus_rsp_takeWhen_valid; - wire iBus_rsp_takeWhen_payload_error; - wire [31:0] iBus_rsp_takeWhen_payload_inst; - wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; - reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; - wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; - wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; - wire IBusSimplePlugin_rspJoin_join_valid; - wire IBusSimplePlugin_rspJoin_join_ready; - wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; - wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; - wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; - wire IBusSimplePlugin_rspJoin_join_payload_isRvc; - reg IBusSimplePlugin_rspJoin_exceptionDetected; - reg IBusSimplePlugin_rspJoin_redoRequired; - wire _zz_105_; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [1:0] dBus_cmd_payload_size; - wire dBus_rsp_ready; - wire dBus_rsp_error; - wire [31:0] dBus_rsp_data; - wire _zz_106_; - reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_107_; - reg [3:0] _zz_108_; - wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_109_; - reg [31:0] _zz_110_; - wire _zz_111_; - reg [31:0] _zz_112_; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [25:0] _zz_113_; - wire _zz_114_; - wire _zz_115_; - wire _zz_116_; - wire _zz_117_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_118_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_119_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_120_; - wire `AluCtrlEnum_defaultEncoding_type _zz_121_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_122_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_123_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_124_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_125_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_126_; - reg [31:0] _zz_127_; - wire _zz_128_; - reg [19:0] _zz_129_; - wire _zz_130_; - reg [19:0] _zz_131_; - reg [31:0] _zz_132_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - reg execute_LightShifterPlugin_isActive; - wire execute_LightShifterPlugin_isShift; - reg [4:0] execute_LightShifterPlugin_amplitudeReg; - wire [4:0] execute_LightShifterPlugin_amplitude; - wire [31:0] execute_LightShifterPlugin_shiftInput; - wire execute_LightShifterPlugin_done; - reg [31:0] _zz_133_; - reg _zz_134_; - reg _zz_135_; - wire _zz_136_; - reg _zz_137_; - reg [4:0] _zz_138_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_139_; - reg _zz_140_; - reg _zz_141_; - wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_142_; - reg [10:0] _zz_143_; - wire _zz_144_; - reg [19:0] _zz_145_; - wire _zz_146_; - reg [18:0] _zz_147_; - reg [31:0] _zz_148_; - wire [31:0] execute_BranchPlugin_branch_src2; - wire [31:0] execute_BranchPlugin_branchAdder; - wire [1:0] CsrPlugin_misa_base; - wire [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_149_; - wire _zz_150_; - wire _zz_151_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_152_; - wire _zz_153_; - wire [1:0] _zz_154_; - wire _zz_155_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_156_; - wire [31:0] _zz_157_; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg execute_to_memory_MMU_FAULT; - reg decode_to_execute_CSR_READ_OPCODE; - reg [31:0] execute_to_memory_MMU_RSP_physicalAddress; - reg execute_to_memory_MMU_RSP_isIoAccess; - reg execute_to_memory_MMU_RSP_allowRead; - reg execute_to_memory_MMU_RSP_allowWrite; - reg execute_to_memory_MMU_RSP_allowExecute; - reg execute_to_memory_MMU_RSP_exception; - reg execute_to_memory_MMU_RSP_refilling; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg execute_to_memory_ALIGNEMENT_FAULT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg [31:0] decode_to_execute_RS2; - reg decode_to_execute_IS_CSR; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg decode_to_execute_MEMORY_STORE; - reg execute_to_memory_MEMORY_STORE; - reg memory_to_writeBack_MEMORY_STORE; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BRANCH_DO; - reg [31:0] decode_to_execute_RS1; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - wire iBus_cmd_m2sPipe_valid; - wire iBus_cmd_m2sPipe_ready; - wire [31:0] iBus_cmd_m2sPipe_payload_pc; - reg _zz_158_; - reg [31:0] _zz_159_; - wire dBus_cmd_halfPipe_valid; - wire dBus_cmd_halfPipe_ready; - wire dBus_cmd_halfPipe_payload_wr; - wire [31:0] dBus_cmd_halfPipe_payload_address; - wire [31:0] dBus_cmd_halfPipe_payload_data; - wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_160_; + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output iBusWishbone_CYC, + output iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_120; + wire _zz_121; + reg [31:0] _zz_122; + reg [31:0] _zz_123; + reg [31:0] _zz_124; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_125; + wire _zz_126; + wire _zz_127; + wire _zz_128; + wire _zz_129; + wire _zz_130; + wire [1:0] _zz_131; + wire _zz_132; + wire _zz_133; + wire _zz_134; + wire _zz_135; + wire _zz_136; + wire _zz_137; + wire _zz_138; + wire _zz_139; + wire _zz_140; + wire _zz_141; + wire _zz_142; + wire _zz_143; + wire _zz_144; + wire _zz_145; + wire _zz_146; + wire _zz_147; + wire _zz_148; + wire [1:0] _zz_149; + wire _zz_150; + wire [0:0] _zz_151; + wire [0:0] _zz_152; + wire [0:0] _zz_153; + wire [0:0] _zz_154; + wire [0:0] _zz_155; + wire [0:0] _zz_156; + wire [0:0] _zz_157; + wire [0:0] _zz_158; + wire [0:0] _zz_159; + wire [0:0] _zz_160; + wire [0:0] _zz_161; + wire [2:0] _zz_162; + wire [2:0] _zz_163; + wire [31:0] _zz_164; + wire [2:0] _zz_165; + wire [0:0] _zz_166; + wire [2:0] _zz_167; + wire [0:0] _zz_168; + wire [2:0] _zz_169; + wire [0:0] _zz_170; + wire [2:0] _zz_171; + wire [0:0] _zz_172; + wire [2:0] _zz_173; + wire [2:0] _zz_174; + wire [0:0] _zz_175; + wire [2:0] _zz_176; + wire [4:0] _zz_177; + wire [11:0] _zz_178; + wire [11:0] _zz_179; + wire [31:0] _zz_180; + wire [31:0] _zz_181; + wire [31:0] _zz_182; + wire [31:0] _zz_183; + wire [31:0] _zz_184; + wire [31:0] _zz_185; + wire [31:0] _zz_186; + wire [31:0] _zz_187; + wire [32:0] _zz_188; + wire [19:0] _zz_189; + wire [11:0] _zz_190; + wire [11:0] _zz_191; + wire [1:0] _zz_192; + wire [1:0] _zz_193; + wire [1:0] _zz_194; + wire [1:0] _zz_195; + wire [0:0] _zz_196; + wire [0:0] _zz_197; + wire [0:0] _zz_198; + wire [0:0] _zz_199; + wire [0:0] _zz_200; + wire [0:0] _zz_201; + wire _zz_202; + wire _zz_203; + wire [1:0] _zz_204; + wire [31:0] _zz_205; + wire [31:0] _zz_206; + wire [31:0] _zz_207; + wire _zz_208; + wire [0:0] _zz_209; + wire [12:0] _zz_210; + wire [31:0] _zz_211; + wire [31:0] _zz_212; + wire [31:0] _zz_213; + wire _zz_214; + wire [0:0] _zz_215; + wire [6:0] _zz_216; + wire [31:0] _zz_217; + wire [31:0] _zz_218; + wire [31:0] _zz_219; + wire _zz_220; + wire [0:0] _zz_221; + wire [0:0] _zz_222; + wire [31:0] _zz_223; + wire [31:0] _zz_224; + wire [31:0] _zz_225; + wire [0:0] _zz_226; + wire [0:0] _zz_227; + wire [1:0] _zz_228; + wire [1:0] _zz_229; + wire _zz_230; + wire [0:0] _zz_231; + wire [19:0] _zz_232; + wire [31:0] _zz_233; + wire [31:0] _zz_234; + wire [31:0] _zz_235; + wire [31:0] _zz_236; + wire [31:0] _zz_237; + wire [31:0] _zz_238; + wire _zz_239; + wire [1:0] _zz_240; + wire [1:0] _zz_241; + wire _zz_242; + wire [0:0] _zz_243; + wire [16:0] _zz_244; + wire [31:0] _zz_245; + wire [31:0] _zz_246; + wire [31:0] _zz_247; + wire [31:0] _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire [0:0] _zz_252; + wire [0:0] _zz_253; + wire _zz_254; + wire [0:0] _zz_255; + wire [13:0] _zz_256; + wire [31:0] _zz_257; + wire _zz_258; + wire _zz_259; + wire [0:0] _zz_260; + wire [0:0] _zz_261; + wire [2:0] _zz_262; + wire [2:0] _zz_263; + wire _zz_264; + wire [0:0] _zz_265; + wire [10:0] _zz_266; + wire [31:0] _zz_267; + wire [31:0] _zz_268; + wire [31:0] _zz_269; + wire [31:0] _zz_270; + wire _zz_271; + wire _zz_272; + wire [31:0] _zz_273; + wire [31:0] _zz_274; + wire _zz_275; + wire [0:0] _zz_276; + wire [0:0] _zz_277; + wire _zz_278; + wire [0:0] _zz_279; + wire [7:0] _zz_280; + wire [0:0] _zz_281; + wire [3:0] _zz_282; + wire [0:0] _zz_283; + wire [0:0] _zz_284; + wire [1:0] _zz_285; + wire [1:0] _zz_286; + wire _zz_287; + wire [0:0] _zz_288; + wire [4:0] _zz_289; + wire [31:0] _zz_290; + wire [31:0] _zz_291; + wire [31:0] _zz_292; + wire [0:0] _zz_293; + wire [0:0] _zz_294; + wire [31:0] _zz_295; + wire [31:0] _zz_296; + wire [31:0] _zz_297; + wire _zz_298; + wire _zz_299; + wire _zz_300; + wire [3:0] _zz_301; + wire [3:0] _zz_302; + wire _zz_303; + wire [0:0] _zz_304; + wire [1:0] _zz_305; + wire [31:0] _zz_306; + wire [31:0] _zz_307; + wire [31:0] _zz_308; + wire [31:0] _zz_309; + wire [31:0] _zz_310; + wire [31:0] _zz_311; + wire [31:0] _zz_312; + wire _zz_313; + wire [0:0] _zz_314; + wire [1:0] _zz_315; + wire _zz_316; + wire [2:0] _zz_317; + wire [2:0] _zz_318; + wire _zz_319; + wire _zz_320; + wire [31:0] _zz_321; + wire [31:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [31:0] _zz_326; + wire [31:0] _zz_327; + wire _zz_328; + wire _zz_329; + wire _zz_330; + wire _zz_331; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire [31:0] decode_RS2; + wire [31:0] decode_RS1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `BranchCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_17; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_26; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_29; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] _zz_30; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_31; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_32; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_33; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_34; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_36; + wire [31:0] _zz_37; + wire _zz_38; + reg _zz_39; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_40; + wire `BranchCtrlEnum_defaultEncoding_type _zz_41; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_42; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; + wire `Src2CtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_defaultEncoding_type _zz_45; + wire `Src1CtrlEnum_defaultEncoding_type _zz_46; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_47; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP2_physicalAddress; + wire memory_MMU_RSP2_isIoAccess; + wire memory_MMU_RSP2_isPaging; + wire memory_MMU_RSP2_allowRead; + wire memory_MMU_RSP2_allowWrite; + wire memory_MMU_RSP2_allowExecute; + wire memory_MMU_RSP2_exception; + wire memory_MMU_RSP2_refilling; + wire memory_MMU_RSP2_bypassTranslation; + wire [31:0] memory_PC; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire execute_MMU_FAULT; + wire [31:0] execute_MMU_RSP2_physicalAddress; + wire execute_MMU_RSP2_isIoAccess; + wire execute_MMU_RSP2_isPaging; + wire execute_MMU_RSP2_allowRead; + wire execute_MMU_RSP2_allowWrite; + wire execute_MMU_RSP2_allowExecute; + wire execute_MMU_RSP2_exception; + wire execute_MMU_RSP2_refilling; + wire execute_MMU_RSP2_bypassTranslation; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire decode_MEMORY_ENABLE; + reg [31:0] _zz_48; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusSimplePlugin_fetcherHalt; + reg IBusSimplePlugin_incomingInstruction; + wire IBusSimplePlugin_pcValids_0; + wire IBusSimplePlugin_pcValids_1; + wire IBusSimplePlugin_pcValids_2; + wire IBusSimplePlugin_pcValids_3; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + wire [31:0] iBus_cmd_payload_pc; + wire iBus_rsp_valid; + wire iBus_rsp_payload_error; + wire [31:0] iBus_rsp_payload_inst; + wire IBusSimplePlugin_decodeExceptionPort_valid; + reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; + wire IBusSimplePlugin_mmuBus_cmd_0_isValid; + wire IBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire IBusSimplePlugin_mmuBus_rsp_isPaging; + wire IBusSimplePlugin_mmuBus_rsp_allowRead; + wire IBusSimplePlugin_mmuBus_rsp_allowWrite; + wire IBusSimplePlugin_mmuBus_rsp_allowExecute; + wire IBusSimplePlugin_mmuBus_rsp_exception; + wire IBusSimplePlugin_mmuBus_rsp_refilling; + wire IBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire IBusSimplePlugin_mmuBus_end; + wire IBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire DBusSimplePlugin_mmuBus_cmd_0_isValid; + wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire DBusSimplePlugin_mmuBus_rsp_isPaging; + wire DBusSimplePlugin_mmuBus_rsp_allowRead; + wire DBusSimplePlugin_mmuBus_rsp_allowWrite; + wire DBusSimplePlugin_mmuBus_rsp_allowExecute; + wire DBusSimplePlugin_mmuBus_rsp_exception; + wire DBusSimplePlugin_mmuBus_rsp_refilling; + wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire DBusSimplePlugin_mmuBus_end; + wire DBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_redoBranch_valid; + wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusSimplePlugin_externalFlush; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire [2:0] _zz_49; + wire [2:0] _zz_50; + wire _zz_51; + wire _zz_52; + wire IBusSimplePlugin_fetchPc_output_valid; + wire IBusSimplePlugin_fetchPc_output_ready; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusSimplePlugin_fetchPc_correction; + reg IBusSimplePlugin_fetchPc_correctionReg; + wire IBusSimplePlugin_fetchPc_corrected; + reg IBusSimplePlugin_fetchPc_pcRegPropagate; + reg IBusSimplePlugin_fetchPc_booted; + reg IBusSimplePlugin_fetchPc_inc; + reg [31:0] IBusSimplePlugin_fetchPc_pc; + wire IBusSimplePlugin_fetchPc_redo_valid; + wire [31:0] IBusSimplePlugin_fetchPc_redo_payload; + reg IBusSimplePlugin_fetchPc_flushed; + reg IBusSimplePlugin_iBusRsp_redoFetch; + wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + reg IBusSimplePlugin_iBusRsp_stages_0_halt; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_halt; + wire _zz_53; + wire _zz_54; + wire IBusSimplePlugin_iBusRsp_flush; + wire _zz_55; + wire _zz_56; + reg _zz_57; + reg IBusSimplePlugin_iBusRsp_readyForError; + wire IBusSimplePlugin_iBusRsp_output_valid; + wire IBusSimplePlugin_iBusRsp_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; + wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; + wire IBusSimplePlugin_injector_decodeInput_valid; + wire IBusSimplePlugin_injector_decodeInput_ready; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; + wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; + reg _zz_58; + reg [31:0] _zz_59; + reg _zz_60; + reg [31:0] _zz_61; + reg _zz_62; + reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; + reg IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_ready; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + wire IBusSimplePlugin_pending_inc; + wire IBusSimplePlugin_pending_dec; + reg [2:0] IBusSimplePlugin_pending_value; + wire [2:0] IBusSimplePlugin_pending_next; + wire IBusSimplePlugin_cmdFork_canEmit; + reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; + reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; + reg IBusSimplePlugin_mmu_joinCtx_isPaging; + reg IBusSimplePlugin_mmu_joinCtx_allowRead; + reg IBusSimplePlugin_mmu_joinCtx_allowWrite; + reg IBusSimplePlugin_mmu_joinCtx_allowExecute; + reg IBusSimplePlugin_mmu_joinCtx_exception; + reg IBusSimplePlugin_mmu_joinCtx_refilling; + reg IBusSimplePlugin_mmu_joinCtx_bypassTranslation; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_join_ready; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_payload_isRvc; + reg IBusSimplePlugin_rspJoin_exceptionDetected; + wire _zz_63; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire _zz_64; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_65; + reg [3:0] _zz_66; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_67; + reg [31:0] _zz_68; + wire _zz_69; + reg [31:0] _zz_70; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [25:0] _zz_71; + wire _zz_72; + wire _zz_73; + wire _zz_74; + wire _zz_75; + wire `Src1CtrlEnum_defaultEncoding_type _zz_76; + wire `AluCtrlEnum_defaultEncoding_type _zz_77; + wire `Src2CtrlEnum_defaultEncoding_type _zz_78; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_79; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_80; + wire `BranchCtrlEnum_defaultEncoding_type _zz_81; + wire `EnvCtrlEnum_defaultEncoding_type _zz_82; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_83; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_84; + reg [31:0] _zz_85; + wire _zz_86; + reg [19:0] _zz_87; + wire _zz_88; + reg [19:0] _zz_89; + reg [31:0] _zz_90; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_91; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_92; + reg _zz_93; + reg _zz_94; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_95; + reg [10:0] _zz_96; + wire _zz_97; + reg [19:0] _zz_98; + wire _zz_99; + reg [18:0] _zz_100; + reg [31:0] _zz_101; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_102; + wire _zz_103; + wire _zz_104; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_105; + wire _zz_106; + wire [1:0] _zz_107; + wire _zz_108; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_109; + wire [31:0] _zz_110; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; + reg execute_to_memory_MMU_RSP2_isIoAccess; + reg execute_to_memory_MMU_RSP2_isPaging; + reg execute_to_memory_MMU_RSP2_allowRead; + reg execute_to_memory_MMU_RSP2_allowWrite; + reg execute_to_memory_MMU_RSP2_allowExecute; + reg execute_to_memory_MMU_RSP2_exception; + reg execute_to_memory_MMU_RSP2_refilling; + reg execute_to_memory_MMU_RSP2_bypassTranslation; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_111; + reg [31:0] _zz_112; + reg [31:0] _zz_113; + reg [31:0] _zz_114; + reg [31:0] _zz_115; + reg [31:0] _zz_116; + reg [31:0] _zz_117; + reg [31:0] _zz_118; + wire iBus_cmd_m2sPipe_valid; + wire iBus_cmd_m2sPipe_ready; + wire [31:0] iBus_cmd_m2sPipe_payload_pc; + reg iBus_cmd_m2sPipe_rValid; + reg [31:0] iBus_cmd_m2sPipe_rData_pc; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_119; `ifndef SYNTHESIS - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_1__string; - reg [23:0] _zz_2__string; - reg [23:0] _zz_3__string; - reg [39:0] _zz_4__string; - reg [39:0] _zz_5__string; - reg [39:0] _zz_6__string; - reg [39:0] _zz_7__string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8__string; - reg [39:0] _zz_9__string; - reg [39:0] _zz_10__string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_11__string; - reg [95:0] _zz_12__string; - reg [95:0] _zz_13__string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_14__string; - reg [31:0] _zz_15__string; - reg [31:0] _zz_16__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_17__string; - reg [63:0] _zz_18__string; - reg [63:0] _zz_19__string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [31:0] _zz_10_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_20__string; - reg [71:0] _zz_21__string; - reg [71:0] _zz_22__string; + reg [71:0] _zz_11_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_23__string; - reg [39:0] _zz_24__string; - reg [39:0] _zz_25__string; + reg [39:0] _zz_14_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_17_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_20_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_23_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_26__string; + reg [39:0] _zz_26_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_27__string; + reg [39:0] _zz_27_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_30__string; + reg [39:0] _zz_28_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_32__string; + reg [31:0] _zz_29_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_35__string; + reg [71:0] _zz_31_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_40__string; + reg [23:0] _zz_33_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_42__string; + reg [95:0] _zz_34_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_45__string; + reg [63:0] _zz_35_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_47__string; - reg [39:0] _zz_55__string; - reg [39:0] _zz_58__string; - reg [31:0] _zz_59__string; - reg [63:0] _zz_60__string; - reg [23:0] _zz_62__string; - reg [95:0] _zz_65__string; - reg [71:0] _zz_70__string; - reg [71:0] _zz_118__string; - reg [95:0] _zz_119__string; - reg [23:0] _zz_120__string; - reg [63:0] _zz_121__string; - reg [31:0] _zz_122__string; - reg [39:0] _zz_123__string; - reg [39:0] _zz_124__string; + reg [39:0] _zz_36_string; + reg [39:0] _zz_40_string; + reg [31:0] _zz_41_string; + reg [71:0] _zz_42_string; + reg [39:0] _zz_43_string; + reg [23:0] _zz_44_string; + reg [63:0] _zz_45_string; + reg [95:0] _zz_46_string; + reg [95:0] _zz_76_string; + reg [63:0] _zz_77_string; + reg [23:0] _zz_78_string; + reg [39:0] _zz_79_string; + reg [71:0] _zz_80_string; + reg [31:0] _zz_81_string; + reg [39:0] _zz_82_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [39:0] decode_to_execute_ENV_CTRL_string; reg [39:0] execute_to_memory_ENV_CTRL_string; reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; `endif (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_164_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); - assign _zz_165_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_166_ = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_167_ = (! execute_arbitration_isStuckByOthers); - assign _zz_168_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00)); - assign _zz_169_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_170_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_171_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_172_ = (IBusSimplePlugin_mmuBus_rsp_exception || IBusSimplePlugin_mmuBus_rsp_refilling); - assign _zz_173_ = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_174_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_175_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_176_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_177_ = (1'b1 || (! 1'b1)); - assign _zz_178_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_179_ = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_180_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_181_ = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_182_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_183_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_184_ = ((_zz_149_ && 1'b1) && (! 1'b0)); - assign _zz_185_ = ((_zz_150_ && 1'b1) && (! 1'b0)); - assign _zz_186_ = ((_zz_151_ && 1'b1) && (! 1'b0)); - assign _zz_187_ = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_188_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_189_ = execute_INSTRUCTION[13]; - assign _zz_190_ = (_zz_90_ - (4'b0001)); - assign _zz_191_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)}; - assign _zz_192_ = {29'd0, _zz_191_}; - assign _zz_193_ = (IBusSimplePlugin_pendingCmd + _zz_195_); - assign _zz_194_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); - assign _zz_195_ = {2'd0, _zz_194_}; - assign _zz_196_ = iBus_rsp_valid; - assign _zz_197_ = {2'd0, _zz_196_}; - assign _zz_198_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (3'b000))); - assign _zz_199_ = {2'd0, _zz_198_}; - assign _zz_200_ = iBus_rsp_valid; - assign _zz_201_ = {2'd0, _zz_200_}; - assign _zz_202_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100)); - assign _zz_203_ = _zz_113_[2 : 2]; - assign _zz_204_ = _zz_113_[4 : 4]; - assign _zz_205_ = _zz_113_[5 : 5]; - assign _zz_206_ = _zz_113_[6 : 6]; - assign _zz_207_ = _zz_113_[9 : 9]; - assign _zz_208_ = _zz_113_[10 : 10]; - assign _zz_209_ = _zz_113_[13 : 13]; - assign _zz_210_ = _zz_113_[20 : 20]; - assign _zz_211_ = _zz_113_[21 : 21]; - assign _zz_212_ = _zz_113_[24 : 24]; - assign _zz_213_ = _zz_113_[25 : 25]; - assign _zz_214_ = execute_SRC_LESS; - assign _zz_215_ = (3'b100); - assign _zz_216_ = execute_INSTRUCTION[19 : 15]; - assign _zz_217_ = execute_INSTRUCTION[31 : 20]; - assign _zz_218_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_219_ = ($signed(_zz_220_) + $signed(_zz_223_)); - assign _zz_220_ = ($signed(_zz_221_) + $signed(_zz_222_)); - assign _zz_221_ = execute_SRC1; - assign _zz_222_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_223_ = (execute_SRC_USE_SUB_LESS ? _zz_224_ : _zz_225_); - assign _zz_224_ = (32'b00000000000000000000000000000001); - assign _zz_225_ = (32'b00000000000000000000000000000000); - assign _zz_226_ = (_zz_227_ >>> 1); - assign _zz_227_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_228_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_229_ = execute_INSTRUCTION[31 : 20]; - assign _zz_230_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_231_ = (_zz_152_ & (~ _zz_232_)); - assign _zz_232_ = (_zz_152_ - (2'b01)); - assign _zz_233_ = (_zz_154_ & (~ _zz_234_)); - assign _zz_234_ = (_zz_154_ - (2'b01)); - assign _zz_235_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_236_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_237_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_238_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_239_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_240_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_241_ = ({3'd0,_zz_160_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - assign _zz_242_ = 1'b1; - assign _zz_243_ = 1'b1; - assign _zz_244_ = {_zz_94_,_zz_93_}; - assign _zz_245_ = (32'b00000000000000000000000000010000); - assign _zz_246_ = (decode_INSTRUCTION & (32'b00010000000000000011000001010000)); - assign _zz_247_ = (32'b00000000000000000000000001010000); - assign _zz_248_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); - assign _zz_249_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000100000)); - assign _zz_250_ = (1'b0); - assign _zz_251_ = ({(_zz_254_ == _zz_255_),(_zz_256_ == _zz_257_)} != (2'b00)); - assign _zz_252_ = ((_zz_258_ == _zz_259_) != (1'b0)); - assign _zz_253_ = {(_zz_260_ != (1'b0)),{(_zz_261_ != _zz_262_),{_zz_263_,{_zz_264_,_zz_265_}}}}; - assign _zz_254_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_255_ = (32'b00000000000000000000000000100100); - assign _zz_256_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010100)); - assign _zz_257_ = (32'b00000000000000000001000000010000); - assign _zz_258_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); - assign _zz_259_ = (32'b00000000000000000001000000000000); - assign _zz_260_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); - assign _zz_261_ = {_zz_115_,(_zz_266_ == _zz_267_)}; - assign _zz_262_ = (2'b00); - assign _zz_263_ = ((_zz_268_ == _zz_269_) != (1'b0)); - assign _zz_264_ = ({_zz_270_,_zz_271_} != (2'b00)); - assign _zz_265_ = {(_zz_272_ != _zz_273_),{_zz_274_,{_zz_275_,_zz_276_}}}; - assign _zz_266_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011100)); - assign _zz_267_ = (32'b00000000000000000000000000000100); - assign _zz_268_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); - assign _zz_269_ = (32'b00000000000000000000000001000000); - assign _zz_270_ = ((decode_INSTRUCTION & _zz_277_) == (32'b00000000000000000110000000010000)); - assign _zz_271_ = ((decode_INSTRUCTION & _zz_278_) == (32'b00000000000000000100000000010000)); - assign _zz_272_ = ((decode_INSTRUCTION & _zz_279_) == (32'b00000000000000000010000000010000)); - assign _zz_273_ = (1'b0); - assign _zz_274_ = ({_zz_280_,{_zz_281_,_zz_282_}} != (4'b0000)); - assign _zz_275_ = ({_zz_283_,_zz_284_} != (2'b00)); - assign _zz_276_ = {(_zz_285_ != _zz_286_),{_zz_287_,{_zz_288_,_zz_289_}}}; - assign _zz_277_ = (32'b00000000000000000110000000010100); - assign _zz_278_ = (32'b00000000000000000101000000010100); - assign _zz_279_ = (32'b00000000000000000110000000010100); - assign _zz_280_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000000)); - assign _zz_281_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000000000000)); - assign _zz_282_ = {(_zz_291_ == _zz_292_),(_zz_293_ == _zz_294_)}; - assign _zz_283_ = _zz_117_; - assign _zz_284_ = ((decode_INSTRUCTION & _zz_295_) == (32'b00000000000000000000000000100000)); - assign _zz_285_ = {_zz_117_,(_zz_296_ == _zz_297_)}; - assign _zz_286_ = (2'b00); - assign _zz_287_ = ({_zz_298_,_zz_299_} != (2'b00)); - assign _zz_288_ = ({_zz_300_,_zz_301_} != (2'b00)); - assign _zz_289_ = {(_zz_302_ != _zz_303_),{_zz_304_,{_zz_305_,_zz_306_}}}; - assign _zz_290_ = (32'b00000000000000000000000000011000); - assign _zz_291_ = (decode_INSTRUCTION & (32'b00000000000000000110000000000100)); - assign _zz_292_ = (32'b00000000000000000010000000000000); - assign _zz_293_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000100)); - assign _zz_294_ = (32'b00000000000000000001000000000000); - assign _zz_295_ = (32'b00000000000000000000000001110000); - assign _zz_296_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_297_ = (32'b00000000000000000000000000000000); - assign _zz_298_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000000000)); - assign _zz_299_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000000)) == (32'b00000000000000000001000000000000)); - assign _zz_300_ = ((decode_INSTRUCTION & _zz_307_) == (32'b00000000000000000001000001010000)); - assign _zz_301_ = ((decode_INSTRUCTION & _zz_308_) == (32'b00000000000000000010000001010000)); - assign _zz_302_ = {(_zz_309_ == _zz_310_),_zz_116_}; - assign _zz_303_ = (2'b00); - assign _zz_304_ = ({_zz_311_,_zz_116_} != (2'b00)); - assign _zz_305_ = (_zz_312_ != (1'b0)); - assign _zz_306_ = {(_zz_313_ != _zz_314_),{_zz_315_,{_zz_316_,_zz_317_}}}; - assign _zz_307_ = (32'b00000000000000000001000001010000); - assign _zz_308_ = (32'b00000000000000000010000001010000); - assign _zz_309_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100)); - assign _zz_310_ = (32'b00000000000000000000000000000100); - assign _zz_311_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); - assign _zz_312_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000)); - assign _zz_313_ = {(_zz_318_ == _zz_319_),(_zz_320_ == _zz_321_)}; - assign _zz_314_ = (2'b00); - assign _zz_315_ = ({_zz_322_,{_zz_323_,_zz_324_}} != (3'b000)); - assign _zz_316_ = ({_zz_325_,_zz_326_} != (3'b000)); - assign _zz_317_ = {(_zz_327_ != _zz_328_),{_zz_329_,_zz_330_}}; - assign _zz_318_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); - assign _zz_319_ = (32'b00000000000000000000000000100000); - assign _zz_320_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_321_ = (32'b00000000000000000000000000100000); - assign _zz_322_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000001000000)); - assign _zz_323_ = ((decode_INSTRUCTION & _zz_331_) == (32'b00000000000000000010000000010000)); - assign _zz_324_ = ((decode_INSTRUCTION & _zz_332_) == (32'b01000000000000000000000000110000)); - assign _zz_325_ = ((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000000000001000000)); - assign _zz_326_ = {(_zz_334_ == _zz_335_),(_zz_336_ == _zz_337_)}; - assign _zz_327_ = {_zz_115_,{_zz_338_,{_zz_339_,_zz_340_}}}; - assign _zz_328_ = (6'b000000); - assign _zz_329_ = ((_zz_341_ == _zz_342_) != (1'b0)); - assign _zz_330_ = ({_zz_343_,_zz_344_} != (2'b00)); - assign _zz_331_ = (32'b00000000000000000010000000010100); - assign _zz_332_ = (32'b01000000000000000100000000110100); - assign _zz_333_ = (32'b00000000000000000000000001010000); - assign _zz_334_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000)); - assign _zz_335_ = (32'b00000000000000000000000000000000); - assign _zz_336_ = (decode_INSTRUCTION & (32'b00000000010000000011000001000000)); - assign _zz_337_ = (32'b00000000000000000000000001000000); - assign _zz_338_ = ((decode_INSTRUCTION & (32'b00000000000000000001000000010000)) == (32'b00000000000000000001000000010000)); - assign _zz_339_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); - assign _zz_340_ = {_zz_114_,{((decode_INSTRUCTION & (32'b00000000000000000000000000001100)) == (32'b00000000000000000000000000000100)),((decode_INSTRUCTION & (32'b00000000000000000000000000101000)) == (32'b00000000000000000000000000000000))}}; - assign _zz_341_ = (decode_INSTRUCTION & (32'b00000000000000000111000001010100)); - assign _zz_342_ = (32'b00000000000000000101000000010000); - assign _zz_343_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); - assign _zz_344_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); - assign _zz_345_ = (32'b00000000000000000001000001111111); - assign _zz_346_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_347_ = (32'b00000000000000000010000001110011); - assign _zz_348_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_349_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_350_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_351_) == (32'b00000000000000000000000000000011)),{(_zz_352_ == _zz_353_),{_zz_354_,{_zz_355_,_zz_356_}}}}}}; - assign _zz_351_ = (32'b00000000000000000101000001011111); - assign _zz_352_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_353_ = (32'b00000000000000000000000001100011); - assign _zz_354_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_355_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_356_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_357_) == (32'b00000000000000000101000000110011)),{(_zz_358_ == _zz_359_),{_zz_360_,{_zz_361_,_zz_362_}}}}}}; - assign _zz_357_ = (32'b10111110000000000111000001111111); - assign _zz_358_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_359_ = (32'b00000000000000000000000000110011); - assign _zz_360_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_361_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); - assign _zz_362_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00000000000000000000000001110011)); + + assign _zz_125 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_126 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_127 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_128 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_129 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_130 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_131 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_132 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); + assign _zz_133 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_134 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_135 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_136 = (1'b1 || (! 1'b1)); + assign _zz_137 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_138 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_139 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_140 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_141 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_142 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_143 = (! execute_arbitration_isStuckByOthers); + assign _zz_144 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_145 = ((_zz_102 && 1'b1) && (! 1'b0)); + assign _zz_146 = ((_zz_103 && 1'b1) && (! 1'b0)); + assign _zz_147 = ((_zz_104 && 1'b1) && (! 1'b0)); + assign _zz_148 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_149 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_150 = execute_INSTRUCTION[13]; + assign _zz_151 = _zz_71[23 : 23]; + assign _zz_152 = _zz_71[15 : 15]; + assign _zz_153 = _zz_71[12 : 12]; + assign _zz_154 = _zz_71[11 : 11]; + assign _zz_155 = _zz_71[10 : 10]; + assign _zz_156 = _zz_71[14 : 14]; + assign _zz_157 = _zz_71[4 : 4]; + assign _zz_158 = _zz_71[2 : 2]; + assign _zz_159 = _zz_71[18 : 18]; + assign _zz_160 = _zz_71[9 : 9]; + assign _zz_161 = _zz_71[3 : 3]; + assign _zz_162 = (_zz_49 - 3'b001); + assign _zz_163 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_164 = {29'd0, _zz_163}; + assign _zz_165 = (IBusSimplePlugin_pending_value + _zz_167); + assign _zz_166 = IBusSimplePlugin_pending_inc; + assign _zz_167 = {2'd0, _zz_166}; + assign _zz_168 = IBusSimplePlugin_pending_dec; + assign _zz_169 = {2'd0, _zz_168}; + assign _zz_170 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_171 = {2'd0, _zz_170}; + assign _zz_172 = IBusSimplePlugin_pending_dec; + assign _zz_173 = {2'd0, _zz_172}; + assign _zz_174 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_175 = execute_SRC_LESS; + assign _zz_176 = 3'b100; + assign _zz_177 = execute_INSTRUCTION[19 : 15]; + assign _zz_178 = execute_INSTRUCTION[31 : 20]; + assign _zz_179 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_180 = ($signed(_zz_181) + $signed(_zz_184)); + assign _zz_181 = ($signed(_zz_182) + $signed(_zz_183)); + assign _zz_182 = execute_SRC1; + assign _zz_183 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_184 = (execute_SRC_USE_SUB_LESS ? _zz_185 : _zz_186); + assign _zz_185 = 32'h00000001; + assign _zz_186 = 32'h0; + assign _zz_187 = (_zz_188 >>> 1); + assign _zz_188 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_189 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_190 = execute_INSTRUCTION[31 : 20]; + assign _zz_191 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_192 = (_zz_105 & (~ _zz_193)); + assign _zz_193 = (_zz_105 - 2'b01); + assign _zz_194 = (_zz_107 & (~ _zz_195)); + assign _zz_195 = (_zz_107 - 2'b01); + assign _zz_196 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_197 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_198 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_199 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_200 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_201 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_202 = 1'b1; + assign _zz_203 = 1'b1; + assign _zz_204 = {_zz_52,_zz_51}; + assign _zz_205 = 32'h0000107f; + assign _zz_206 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_207 = 32'h00002073; + assign _zz_208 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_209 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_210 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_211) == 32'h00000003),{(_zz_212 == _zz_213),{_zz_214,{_zz_215,_zz_216}}}}}}; + assign _zz_211 = 32'h0000505f; + assign _zz_212 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_213 = 32'h00000063; + assign _zz_214 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_215 = ((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033); + assign _zz_216 = {((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013),{((decode_INSTRUCTION & _zz_217) == 32'h00005033),{(_zz_218 == _zz_219),{_zz_220,{_zz_221,_zz_222}}}}}}; + assign _zz_217 = 32'hbe00707f; + assign _zz_218 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_219 = 32'h00000033; + assign _zz_220 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_221 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_222 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_223 = 32'h10003050; + assign _zz_224 = (decode_INSTRUCTION & 32'h10403050); + assign _zz_225 = 32'h10000050; + assign _zz_226 = ((decode_INSTRUCTION & _zz_233) == 32'h00001050); + assign _zz_227 = ((decode_INSTRUCTION & _zz_234) == 32'h00002050); + assign _zz_228 = {_zz_75,(_zz_235 == _zz_236)}; + assign _zz_229 = 2'b00; + assign _zz_230 = ((_zz_237 == _zz_238) != 1'b0); + assign _zz_231 = (_zz_239 != 1'b0); + assign _zz_232 = {(_zz_240 != _zz_241),{_zz_242,{_zz_243,_zz_244}}}; + assign _zz_233 = 32'h00001050; + assign _zz_234 = 32'h00002050; + assign _zz_235 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_236 = 32'h00000004; + assign _zz_237 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_238 = 32'h00000040; + assign _zz_239 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); + assign _zz_240 = {(_zz_245 == _zz_246),(_zz_247 == _zz_248)}; + assign _zz_241 = 2'b00; + assign _zz_242 = ({_zz_249,_zz_250} != 2'b00); + assign _zz_243 = (_zz_251 != 1'b0); + assign _zz_244 = {(_zz_252 != _zz_253),{_zz_254,{_zz_255,_zz_256}}}; + assign _zz_245 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_246 = 32'h40001010; + assign _zz_247 = (decode_INSTRUCTION & 32'h00007054); + assign _zz_248 = 32'h00001010; + assign _zz_249 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_250 = ((decode_INSTRUCTION & 32'h00003054) == 32'h00001010); + assign _zz_251 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_252 = ((decode_INSTRUCTION & _zz_257) == 32'h00002000); + assign _zz_253 = 1'b0; + assign _zz_254 = ({_zz_258,_zz_259} != 2'b00); + assign _zz_255 = ({_zz_260,_zz_261} != 2'b00); + assign _zz_256 = {(_zz_262 != _zz_263),{_zz_264,{_zz_265,_zz_266}}}; + assign _zz_257 = 32'h00003000; + assign _zz_258 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_259 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_260 = ((decode_INSTRUCTION & _zz_267) == 32'h00000020); + assign _zz_261 = ((decode_INSTRUCTION & _zz_268) == 32'h00000020); + assign _zz_262 = {(_zz_269 == _zz_270),{_zz_271,_zz_272}}; + assign _zz_263 = 3'b000; + assign _zz_264 = ((_zz_273 == _zz_274) != 1'b0); + assign _zz_265 = (_zz_275 != 1'b0); + assign _zz_266 = {(_zz_276 != _zz_277),{_zz_278,{_zz_279,_zz_280}}}; + assign _zz_267 = 32'h00000034; + assign _zz_268 = 32'h00000064; + assign _zz_269 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_270 = 32'h00000040; + assign _zz_271 = ((decode_INSTRUCTION & 32'h00000038) == 32'h0); + assign _zz_272 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); + assign _zz_273 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_274 = 32'h00000020; + assign _zz_275 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); + assign _zz_276 = _zz_74; + assign _zz_277 = 1'b0; + assign _zz_278 = ({_zz_75,{_zz_281,_zz_282}} != 6'h0); + assign _zz_279 = ({_zz_283,_zz_284} != 2'b00); + assign _zz_280 = {(_zz_285 != _zz_286),{_zz_287,{_zz_288,_zz_289}}}; + assign _zz_281 = ((decode_INSTRUCTION & _zz_290) == 32'h00001010); + assign _zz_282 = {(_zz_291 == _zz_292),{_zz_74,{_zz_293,_zz_294}}}; + assign _zz_283 = _zz_73; + assign _zz_284 = ((decode_INSTRUCTION & _zz_295) == 32'h00000020); + assign _zz_285 = {_zz_73,(_zz_296 == _zz_297)}; + assign _zz_286 = 2'b00; + assign _zz_287 = ({_zz_298,_zz_299} != 2'b00); + assign _zz_288 = (_zz_300 != 1'b0); + assign _zz_289 = {(_zz_301 != _zz_302),{_zz_303,{_zz_304,_zz_305}}}; + assign _zz_290 = 32'h00001010; + assign _zz_291 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_292 = 32'h00002010; + assign _zz_293 = (_zz_306 == _zz_307); + assign _zz_294 = (_zz_308 == _zz_309); + assign _zz_295 = 32'h00000070; + assign _zz_296 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_297 = 32'h0; + assign _zz_298 = ((decode_INSTRUCTION & _zz_310) == 32'h00006010); + assign _zz_299 = ((decode_INSTRUCTION & _zz_311) == 32'h00004010); + assign _zz_300 = ((decode_INSTRUCTION & _zz_312) == 32'h00002010); + assign _zz_301 = {_zz_313,{_zz_314,_zz_315}}; + assign _zz_302 = 4'b0000; + assign _zz_303 = (_zz_316 != 1'b0); + assign _zz_304 = (_zz_317 != _zz_318); + assign _zz_305 = {_zz_319,_zz_320}; + assign _zz_306 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_307 = 32'h00000004; + assign _zz_308 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_309 = 32'h0; + assign _zz_310 = 32'h00006014; + assign _zz_311 = 32'h00005014; + assign _zz_312 = 32'h00006014; + assign _zz_313 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_314 = ((decode_INSTRUCTION & _zz_321) == 32'h0); + assign _zz_315 = {(_zz_322 == _zz_323),(_zz_324 == _zz_325)}; + assign _zz_316 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_317 = {(_zz_326 == _zz_327),{_zz_328,_zz_329}}; + assign _zz_318 = 3'b000; + assign _zz_319 = ({_zz_330,_zz_72} != 2'b00); + assign _zz_320 = ({_zz_331,_zz_72} != 2'b00); + assign _zz_321 = 32'h00000018; + assign _zz_322 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_323 = 32'h00002000; + assign _zz_324 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_325 = 32'h00001000; + assign _zz_326 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_327 = 32'h00000040; + assign _zz_328 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_329 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz_330 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_331 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); always @ (posedge clk) begin - if(_zz_50_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + if(_zz_202) begin + _zz_122 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_242_) begin - _zz_161_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_203) begin + _zz_123 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_243_) begin - _zz_162_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( - .io_push_valid(iBus_rsp_takeWhen_valid), - .io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready), - .io_push_payload_error(iBus_rsp_takeWhen_payload_error), - .io_push_payload_inst(iBus_rsp_takeWhen_payload_inst), - .io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid), - .io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready), - .io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error), - .io_pop_payload_inst(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst), - .io_flush(IBusSimplePlugin_fetcherflushIt), - .io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy), - .clk(clk), - .reset(reset) + if(_zz_39) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid (iBus_rsp_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_payload_error ), //i + .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (_zz_120 ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o + .io_flush (_zz_121 ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_244_) + case(_zz_204) 2'b00 : begin - _zz_163_ = CsrPlugin_jumpInterface_payload; + _zz_124 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_163_ = DBusSimplePlugin_redoBranch_payload; - end - 2'b10 : begin - _zz_163_ = BranchPlugin_jumpInterface_payload; + _zz_124 = DBusSimplePlugin_redoBranch_payload; end default : begin - _zz_163_ = IBusSimplePlugin_redoBranch_payload; + _zz_124 = BranchPlugin_jumpInterface_payload; end endcase end `ifndef SYNTHESIS always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; endcase end always @(*) begin - case(_zz_1_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_1__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_1__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_1__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_1__string = "PC "; - default : _zz_1__string = "???"; + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; endcase end always @(*) begin - case(_zz_2_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_2__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_2__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_2__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_2__string = "PC "; - default : _zz_2__string = "???"; + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; endcase end always @(*) begin - case(_zz_3_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_3__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_3__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_3__string = "PC "; - default : _zz_3__string = "???"; + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; endcase end always @(*) begin - case(_zz_4_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4__string = "ECALL"; - default : _zz_4__string = "?????"; + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5__string = "ECALL"; - default : _zz_5__string = "?????"; + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; endcase end always @(*) begin - case(_zz_6_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6__string = "ECALL"; - default : _zz_6__string = "?????"; + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; endcase end always @(*) begin - case(_zz_7_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL"; - default : _zz_7__string = "?????"; + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; endcase end always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_8_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8__string = "ECALL"; - default : _zz_8__string = "?????"; + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; endcase end always @(*) begin - case(_zz_9_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9__string = "ECALL"; - default : _zz_9__string = "?????"; + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; endcase end always @(*) begin - case(_zz_10_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL"; - default : _zz_10__string = "?????"; + case(_zz_10) + `BranchCtrlEnum_defaultEncoding_INC : _zz_10_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_10_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_10_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_10_string = "JALR"; + default : _zz_10_string = "????"; endcase end always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_11__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_11__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_11__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_11__string = "URS1 "; - default : _zz_11__string = "????????????"; + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; endcase end always @(*) begin - case(_zz_12_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_12__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_12__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_12__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_12__string = "URS1 "; - default : _zz_12__string = "????????????"; + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; endcase end always @(*) begin - case(_zz_13_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_13__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_13__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_13__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_13__string = "URS1 "; - default : _zz_13__string = "????????????"; + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; endcase end always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_14_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR"; - default : _zz_14__string = "????"; + case(_zz_14) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; + default : _zz_14_string = "?????"; endcase end always @(*) begin - case(_zz_15_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR"; - default : _zz_15__string = "????"; + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; endcase end always @(*) begin - case(_zz_16_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_16__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_16__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_16__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_16__string = "JALR"; - default : _zz_16__string = "????"; + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_17_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17__string = "BITWISE "; - default : _zz_17__string = "????????"; + case(_zz_17) + `Src2CtrlEnum_defaultEncoding_RS : _zz_17_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_17_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_17_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_17_string = "PC "; + default : _zz_17_string = "???"; endcase end always @(*) begin - case(_zz_18_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE "; - default : _zz_18__string = "????????"; + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; endcase end always @(*) begin - case(_zz_19_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE "; - default : _zz_19__string = "????????"; + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_20_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_20__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_20__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_20__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_20__string = "SRA_1 "; - default : _zz_20__string = "?????????"; + case(_zz_20) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; + default : _zz_20_string = "????????"; endcase end always @(*) begin - case(_zz_21_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_21__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_21__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_21__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_21__string = "SRA_1 "; - default : _zz_21__string = "?????????"; + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; endcase end always @(*) begin - case(_zz_22_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22__string = "SRA_1 "; - default : _zz_22__string = "?????????"; + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_23_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_23__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_23__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_23__string = "AND_1"; - default : _zz_23__string = "?????"; + case(_zz_23) + `Src1CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_23_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_23_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_23_string = "URS1 "; + default : _zz_23_string = "????????????"; endcase end always @(*) begin - case(_zz_24_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_24__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_24__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_24__string = "AND_1"; - default : _zz_24__string = "?????"; + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; endcase end always @(*) begin - case(_zz_25_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25__string = "AND_1"; - default : _zz_25__string = "?????"; + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; endcase end always @(*) begin @@ -1631,11 +1521,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_26_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26__string = "ECALL"; - default : _zz_26__string = "?????"; + case(_zz_26) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_26_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_26_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26_string = "ECALL"; + default : _zz_26_string = "?????"; endcase end always @(*) begin @@ -1647,11 +1537,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_27_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL"; - default : _zz_27__string = "?????"; + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; endcase end always @(*) begin @@ -1663,11 +1553,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_30_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_30__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_30__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30__string = "ECALL"; - default : _zz_30__string = "?????"; + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; endcase end always @(*) begin @@ -1680,12 +1570,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_32_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_32__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_32__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_32__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_32__string = "JALR"; - default : _zz_32__string = "????"; + case(_zz_29) + `BranchCtrlEnum_defaultEncoding_INC : _zz_29_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_29_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_29_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_29_string = "JALR"; + default : _zz_29_string = "????"; endcase end always @(*) begin @@ -1698,12 +1588,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_35_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35__string = "SRA_1 "; - default : _zz_35__string = "?????????"; + case(_zz_31) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_31_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_31_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_31_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_31_string = "SRA_1 "; + default : _zz_31_string = "?????????"; endcase end always @(*) begin @@ -1716,12 +1606,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_40_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_40__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_40__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_40__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_40__string = "PC "; - default : _zz_40__string = "???"; + case(_zz_33) + `Src2CtrlEnum_defaultEncoding_RS : _zz_33_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_33_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_33_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_33_string = "PC "; + default : _zz_33_string = "???"; endcase end always @(*) begin @@ -1734,12 +1624,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_42_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_42__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_42__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_42__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_42__string = "URS1 "; - default : _zz_42__string = "????????????"; + case(_zz_34) + `Src1CtrlEnum_defaultEncoding_RS : _zz_34_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_34_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34_string = "URS1 "; + default : _zz_34_string = "????????????"; endcase end always @(*) begin @@ -1751,11 +1641,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_45_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45__string = "BITWISE "; - default : _zz_45__string = "????????"; + case(_zz_35) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_35_string = "BITWISE "; + default : _zz_35_string = "????????"; endcase end always @(*) begin @@ -1767,131 +1657,157 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_47_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47__string = "AND_1"; - default : _zz_47__string = "?????"; + case(_zz_36) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_36_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_36_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_36_string = "AND_1"; + default : _zz_36_string = "?????"; + endcase + end + always @(*) begin + case(_zz_40) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_40_string = "ECALL"; + default : _zz_40_string = "?????"; + endcase + end + always @(*) begin + case(_zz_41) + `BranchCtrlEnum_defaultEncoding_INC : _zz_41_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_41_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_41_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_41_string = "JALR"; + default : _zz_41_string = "????"; + endcase + end + always @(*) begin + case(_zz_42) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_42_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_42_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_42_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_42_string = "SRA_1 "; + default : _zz_42_string = "?????????"; endcase end always @(*) begin - case(_zz_55_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_55__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_55__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_55__string = "ECALL"; - default : _zz_55__string = "?????"; + case(_zz_43) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_58_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; - default : _zz_58__string = "?????"; + case(_zz_44) + `Src2CtrlEnum_defaultEncoding_RS : _zz_44_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_44_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_44_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_44_string = "PC "; + default : _zz_44_string = "???"; endcase end always @(*) begin - case(_zz_59_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_59__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_59__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_59__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_59__string = "JALR"; - default : _zz_59__string = "????"; + case(_zz_45) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; + default : _zz_45_string = "????????"; endcase end always @(*) begin - case(_zz_60_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_60__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_60__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_60__string = "BITWISE "; - default : _zz_60__string = "????????"; + case(_zz_46) + `Src1CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_46_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_46_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_46_string = "URS1 "; + default : _zz_46_string = "????????????"; endcase end always @(*) begin - case(_zz_62_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_62__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_62__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_62__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_62__string = "PC "; - default : _zz_62__string = "???"; + case(_zz_76) + `Src1CtrlEnum_defaultEncoding_RS : _zz_76_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_76_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_76_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_76_string = "URS1 "; + default : _zz_76_string = "????????????"; endcase end always @(*) begin - case(_zz_65_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_65__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_65__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_65__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_65__string = "URS1 "; - default : _zz_65__string = "????????????"; + case(_zz_77) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_77_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_77_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_77_string = "BITWISE "; + default : _zz_77_string = "????????"; endcase end always @(*) begin - case(_zz_70_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_70__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_70__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_70__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_70__string = "SRA_1 "; - default : _zz_70__string = "?????????"; + case(_zz_78) + `Src2CtrlEnum_defaultEncoding_RS : _zz_78_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_78_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_78_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_78_string = "PC "; + default : _zz_78_string = "???"; endcase end always @(*) begin - case(_zz_118_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_118__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_118__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_118__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_118__string = "SRA_1 "; - default : _zz_118__string = "?????????"; + case(_zz_79) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_79_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_79_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_79_string = "AND_1"; + default : _zz_79_string = "?????"; endcase end always @(*) begin - case(_zz_119_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_119__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_119__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_119__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_119__string = "URS1 "; - default : _zz_119__string = "????????????"; + case(_zz_80) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_80_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_80_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_80_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_80_string = "SRA_1 "; + default : _zz_80_string = "?????????"; endcase end always @(*) begin - case(_zz_120_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_120__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_120__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_120__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_120__string = "PC "; - default : _zz_120__string = "???"; + case(_zz_81) + `BranchCtrlEnum_defaultEncoding_INC : _zz_81_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_81_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_81_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_81_string = "JALR"; + default : _zz_81_string = "????"; endcase end always @(*) begin - case(_zz_121_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_121__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_121__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_121__string = "BITWISE "; - default : _zz_121__string = "????????"; + case(_zz_82) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_82_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_82_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_82_string = "ECALL"; + default : _zz_82_string = "?????"; endcase end always @(*) begin - case(_zz_122_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_122__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_122__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_122__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_122__string = "JALR"; - default : _zz_122__string = "????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_123_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_123__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_123__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_123__string = "AND_1"; - default : _zz_123__string = "?????"; + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_124_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_124__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_124__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_124__string = "ECALL"; - default : _zz_124__string = "?????"; + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin @@ -1911,14 +1827,6 @@ module VexRiscv ( default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end always @(*) begin case(decode_to_execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; @@ -1928,15 +1836,6 @@ module VexRiscv ( default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end always @(*) begin case(decode_to_execute_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; @@ -1961,68 +1860,59 @@ module VexRiscv ( default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; - default : decode_to_execute_SRC2_CTRL_string = "???"; - endcase - end `endif - assign decode_RS1 = _zz_52_; - assign execute_BRANCH_DO = _zz_33_; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_54_; - assign decode_SRC2_FORCE_ZERO = _zz_44_; - assign decode_SRC2_CTRL = _zz_1_; - assign _zz_2_ = _zz_3_; + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_94; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_46_; - assign decode_CSR_WRITE_OPCODE = _zz_29_; - assign execute_BRANCH_CALC = _zz_31_; + assign execute_REGFILE_WRITE_DATA = _zz_84; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_RS2 = decode_RegFilePlugin_rs2Data; + assign decode_RS1 = decode_RegFilePlugin_rs1Data; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_151[0]; + assign decode_BRANCH_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_SHIFT_CTRL = _zz_11; + assign _zz_12 = _zz_13; + assign decode_ALU_BITWISE_CTRL = _zz_14; + assign _zz_15 = _zz_16; + assign decode_SRC_LESS_UNSIGNED = _zz_152[0]; + assign decode_MEMORY_STORE = _zz_153[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_154[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_155[0]; + assign decode_SRC2_CTRL = _zz_17; + assign _zz_18 = _zz_19; + assign decode_ALU_CTRL = _zz_20; + assign _zz_21 = _zz_22; + assign decode_SRC1_CTRL = _zz_23; + assign _zz_24 = _zz_25; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_86_; - assign decode_SRC_LESS_UNSIGNED = _zz_63_; - assign decode_MEMORY_STORE = _zz_56_; - assign memory_MEMORY_READ_DATA = _zz_73_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_53_; - assign decode_IS_CSR = _zz_64_; - assign decode_RS2 = _zz_51_; - assign _zz_4_ = _zz_5_; - assign _zz_6_ = _zz_7_; - assign decode_ENV_CTRL = _zz_8_; - assign _zz_9_ = _zz_10_; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_82_; - assign decode_SRC1_CTRL = _zz_11_; - assign _zz_12_ = _zz_13_; - assign decode_BRANCH_CTRL = _zz_14_; - assign _zz_15_ = _zz_16_; - assign decode_ALU_CTRL = _zz_17_; - assign _zz_18_ = _zz_19_; - assign decode_CSR_READ_OPCODE = _zz_28_; - assign decode_SHIFT_CTRL = _zz_20_; - assign _zz_21_ = _zz_22_; - assign decode_ALU_BITWISE_CTRL = _zz_23_; - assign _zz_24_ = _zz_25_; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_26_; - assign execute_ENV_CTRL = _zz_27_; - assign writeBack_ENV_CTRL = _zz_30_; + assign memory_ENV_CTRL = _zz_26; + assign execute_ENV_CTRL = _zz_27; + assign writeBack_ENV_CTRL = _zz_28; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_32_; - assign decode_RS2_USE = _zz_67_; - assign decode_RS1_USE = _zz_61_; + assign execute_BRANCH_CTRL = _zz_29; + assign decode_RS2_USE = _zz_156[0]; + assign decode_RS1_USE = _zz_157[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; @@ -2030,54 +1920,53 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - _zz_34_ = execute_REGFILE_WRITE_DATA; - if(_zz_164_)begin - _zz_34_ = _zz_133_; + _zz_30 = execute_REGFILE_WRITE_DATA; + if(_zz_125)begin + _zz_30 = _zz_91; end - if(_zz_165_)begin - _zz_34_ = execute_CsrPlugin_readData; + if(_zz_126)begin + _zz_30 = execute_CsrPlugin_readData; end end - assign execute_SHIFT_CTRL = _zz_35_; + assign execute_SHIFT_CTRL = _zz_31; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_39_ = execute_PC; - assign execute_SRC2_CTRL = _zz_40_; - assign execute_SRC1_CTRL = _zz_42_; - assign decode_SRC_USE_SUB_LESS = _zz_68_; - assign decode_SRC_ADD_ZERO = _zz_57_; - assign execute_SRC_ADD_SUB = _zz_38_; - assign execute_SRC_LESS = _zz_36_; - assign execute_ALU_CTRL = _zz_45_; - assign execute_SRC2 = _zz_41_; - assign execute_SRC1 = _zz_43_; - assign execute_ALU_BITWISE_CTRL = _zz_47_; - assign _zz_48_ = writeBack_INSTRUCTION; - assign _zz_49_ = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_50_ = 1'b0; + assign _zz_32 = execute_PC; + assign execute_SRC2_CTRL = _zz_33; + assign execute_SRC1_CTRL = _zz_34; + assign decode_SRC_USE_SUB_LESS = _zz_158[0]; + assign decode_SRC_ADD_ZERO = _zz_159[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_35; + assign execute_SRC2 = _zz_90; + assign execute_SRC1 = _zz_85; + assign execute_ALU_BITWISE_CTRL = _zz_36; + assign _zz_37 = writeBack_INSTRUCTION; + assign _zz_38 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_39 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_50_ = 1'b1; + _zz_39 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_89_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_69_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_160[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_71_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_205) == 32'h00001073),{(_zz_206 == _zz_207),{_zz_208,{_zz_209,_zz_210}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin - _zz_72_ = writeBack_REGFILE_WRITE_DATA; + _zz_47 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_72_ = writeBack_DBusSimplePlugin_rspFormated; + _zz_47 = writeBack_DBusSimplePlugin_rspFormated; end end @@ -2085,52 +1974,49 @@ module VexRiscv ( assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress; - assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess; - assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead; - assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite; - assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute; - assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception; - assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling; + assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; + assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; + assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; + assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; + assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; + assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; + assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; + assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; + assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; assign memory_PC = execute_to_memory_PC; assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = _zz_81_; - assign execute_MMU_RSP_physicalAddress = _zz_74_; - assign execute_MMU_RSP_isIoAccess = _zz_75_; - assign execute_MMU_RSP_allowRead = _zz_76_; - assign execute_MMU_RSP_allowWrite = _zz_77_; - assign execute_MMU_RSP_allowExecute = _zz_78_; - assign execute_MMU_RSP_exception = _zz_79_; - assign execute_MMU_RSP_refilling = _zz_80_; - assign execute_SRC_ADD = _zz_37_; + assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); + assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; + assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; + assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; + assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; + assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; + assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; + assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; + assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_ALIGNEMENT_FAULT = _zz_83_; - assign decode_MEMORY_ENABLE = _zz_66_; + assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); + assign decode_MEMORY_ENABLE = _zz_161[0]; always @ (*) begin - _zz_84_ = memory_FORMAL_PC_NEXT; + _zz_48 = memory_FORMAL_PC_NEXT; if(DBusSimplePlugin_redoBranch_valid)begin - _zz_84_ = DBusSimplePlugin_redoBranch_payload; + _zz_48 = DBusSimplePlugin_redoBranch_payload; end if(BranchPlugin_jumpInterface_valid)begin - _zz_84_ = BranchPlugin_jumpInterface_payload; - end - end - - always @ (*) begin - _zz_85_ = decode_FORMAL_PC_NEXT; - if(IBusSimplePlugin_redoBranch_valid)begin - _zz_85_ = IBusSimplePlugin_redoBranch_payload; + _zz_48 = BranchPlugin_jumpInterface_payload; end end - assign decode_PC = _zz_88_; - assign decode_INSTRUCTION = _zz_87_; + assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -2142,20 +2028,20 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_134_ || _zz_135_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_166_)begin + if(_zz_127)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2163,36 +2049,25 @@ module VexRiscv ( end end - always @ (*) begin - decode_arbitration_flushIt = 1'b0; - if(IBusSimplePlugin_redoBranch_valid)begin - decode_arbitration_flushIt = 1'b1; - end - end - + assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusSimplePlugin_redoBranch_valid)begin - decode_arbitration_flushNext = 1'b1; - end - if(_zz_166_)begin + if(_zz_127)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_)))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_164_)begin - if(_zz_167_)begin - if(! execute_LightShifterPlugin_done) begin - execute_arbitration_haltItself = 1'b1; - end + if(_zz_125)begin + if((! execute_LightShifterPlugin_done))begin + execute_arbitration_haltItself = 1'b1; end end - if(_zz_165_)begin + if(_zz_126)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2228,7 +2103,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_168_)begin + if(_zz_128)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2251,7 +2126,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_168_)begin + if(_zz_128)begin memory_arbitration_flushNext = 1'b1; end end @@ -2268,10 +2143,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_169_)begin + if(_zz_129)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_170_)begin + if(_zz_130)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2282,24 +2157,17 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusSimplePlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_169_)begin + if(_zz_129)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_170_)begin + if(_zz_130)begin IBusSimplePlugin_fetcherHalt = 1'b1; end end - always @ (*) begin - IBusSimplePlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusSimplePlugin_fetcherflushIt = 1'b1; - end - end - always @ (*) begin IBusSimplePlugin_incomingInstruction = 1'b0; if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin @@ -2310,23 +2178,25 @@ module VexRiscv ( end end + assign CsrPlugin_inWfi = 1'b0; + assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_169_)begin + if(_zz_129)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_170_)begin + if(_zz_130)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_169_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_129)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_170_)begin - case(_zz_171_) + if(_zz_130)begin + case(_zz_131) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2339,20 +2209,24 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; - assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusSimplePlugin_redoBranch_valid}}} != (4'b0000)); - assign _zz_90_ = {IBusSimplePlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; - assign _zz_91_ = (_zz_90_ & (~ _zz_190_)); - assign _zz_92_ = _zz_91_[3]; - assign _zz_93_ = (_zz_91_[1] || _zz_92_); - assign _zz_94_ = (_zz_91_[2] || _zz_92_); - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_163_; - always @ (*) begin - IBusSimplePlugin_fetchPc_corrected = 1'b0; + assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); + assign _zz_49 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; + assign _zz_50 = (_zz_49 & (~ _zz_162)); + assign _zz_51 = _zz_50[1]; + assign _zz_52 = _zz_50[2]; + assign IBusSimplePlugin_jump_pcLoad_payload = _zz_124; + always @ (*) begin + IBusSimplePlugin_fetchPc_correction = 1'b0; + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end if(IBusSimplePlugin_jump_pcLoad_valid)begin - IBusSimplePlugin_fetchPc_corrected = 1'b1; + IBusSimplePlugin_fetchPc_correction = 1'b1; end end + assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); always @ (*) begin IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin @@ -2361,7 +2235,10 @@ module VexRiscv ( end always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_192_); + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_164); + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; + end if(IBusSimplePlugin_jump_pcLoad_valid)begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; end @@ -2369,47 +2246,59 @@ module VexRiscv ( IBusSimplePlugin_fetchPc_pc[1] = 1'b0; end + always @ (*) begin + IBusSimplePlugin_fetchPc_flushed = 1'b0; + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; always @ (*) begin - IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; - if(IBusSimplePlugin_mmuBus_busy)begin - IBusSimplePlugin_iBusRsp_stages_0_input_valid = 1'b0; + IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin + IBusSimplePlugin_iBusRsp_redoFetch = 1'b1; end end + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; - assign IBusSimplePlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmd_valid) || (! IBusSimplePlugin_cmd_ready))))begin + if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; end - if(_zz_172_)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - end - end - - assign _zz_95_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt); - always @ (*) begin - IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_95_); - if(IBusSimplePlugin_mmuBus_busy)begin - IBusSimplePlugin_iBusRsp_stages_0_input_ready = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin + if(IBusSimplePlugin_mmuBus_rsp_refilling)begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; + end + if(IBusSimplePlugin_mmuBus_rsp_exception)begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + end end end - assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_95_); + assign _zz_53 = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_53); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_53); assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; - assign _zz_96_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt); - assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_96_); - assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_96_); + assign _zz_54 = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_54); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_54); assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; - assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_97_; - assign _zz_97_ = ((1'b0 && (! _zz_98_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); - assign _zz_98_ = _zz_99_; - assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_98_; + assign IBusSimplePlugin_fetchPc_redo_valid = IBusSimplePlugin_iBusRsp_redoFetch; + assign IBusSimplePlugin_fetchPc_redo_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_55; + assign _zz_55 = ((1'b0 && (! _zz_56)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_56 = _zz_57; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_56; assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; always @ (*) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b1; @@ -2421,183 +2310,167 @@ module VexRiscv ( end end - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); - assign IBusSimplePlugin_injector_decodeInput_valid = _zz_100_; - assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_101_; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_102_; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_103_; - assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_104_; - assign _zz_89_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst); + assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_58; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_59; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_60; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_61; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_62; assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - assign decode_arbitration_isValid = (IBusSimplePlugin_injector_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved)); - assign _zz_88_ = IBusSimplePlugin_injector_decodeInput_payload_pc; - assign _zz_87_ = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; - assign _zz_86_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pendingCmdNext = (_zz_193_ - _zz_197_); + assign IBusSimplePlugin_pending_next = (_zz_165 - _zz_169); + assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); always @ (*) begin - IBusSimplePlugin_cmd_valid = ((IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) && (IBusSimplePlugin_pendingCmd != (3'b111))); - if(_zz_172_)begin - IBusSimplePlugin_cmd_valid = 1'b0; + IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); + if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin + if(IBusSimplePlugin_mmuBus_rsp_refilling)begin + IBusSimplePlugin_cmd_valid = 1'b0; + end + if(IBusSimplePlugin_mmuBus_rsp_exception)begin + IBusSimplePlugin_cmd_valid = 1'b0; + end end end - assign IBusSimplePlugin_mmuBus_cmd_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; - assign IBusSimplePlugin_mmuBus_cmd_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; - assign IBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; - assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_fetcherflushIt); - assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],(2'b00)}; - assign iBus_rsp_takeWhen_valid = (iBus_rsp_valid && (! (IBusSimplePlugin_rspJoin_discardCounter != (3'b000)))); - assign iBus_rsp_takeWhen_payload_error = iBus_rsp_payload_error; - assign iBus_rsp_takeWhen_payload_inst = iBus_rsp_payload_inst; - assign IBusSimplePlugin_rspJoin_rspBufferOutput_valid = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; - assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; - assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_mmuBus_cmd_0_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; + assign IBusSimplePlugin_mmuBus_cmd_0_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_externalFlush); + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],2'b00}; + assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign _zz_120 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_120); assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; always @ (*) begin - IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; - if((! IBusSimplePlugin_rspJoin_rspBufferOutput_valid))begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; end end - assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; always @ (*) begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_173_)begin + if(_zz_132)begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; end end - always @ (*) begin - IBusSimplePlugin_rspJoin_redoRequired = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin - IBusSimplePlugin_rspJoin_redoRequired = 1'b1; - end - end - - assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBufferOutput_valid); + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); - assign IBusSimplePlugin_rspJoin_rspBufferOutput_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); - assign _zz_105_ = (! (IBusSimplePlugin_rspJoin_exceptionDetected || IBusSimplePlugin_rspJoin_redoRequired)); - assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_inputBeforeStage_ready && _zz_105_); - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_105_); - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; - assign IBusSimplePlugin_redoBranch_valid = (IBusSimplePlugin_rspJoin_redoRequired && IBusSimplePlugin_iBusRsp_readyForError); - assign IBusSimplePlugin_redoBranch_payload = decode_PC; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign _zz_63 = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_63); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_63); + assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; always @ (*) begin - IBusSimplePlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_173_)begin - IBusSimplePlugin_decodeExceptionPort_payload_code = (4'b1100); + IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_132)begin + IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; end end - assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],(2'b00)}; + assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],2'b00}; assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError); - assign _zz_106_ = 1'b0; - assign _zz_83_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + assign _zz_64 = 1'b0; always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin execute_DBusSimplePlugin_skipCmd = 1'b1; end - if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin + if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_106_)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_107_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_65 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_107_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_65 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_107_ = execute_RS2[31 : 0]; + _zz_65 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_107_; - assign _zz_82_ = dBus_cmd_payload_address[1 : 0]; + assign dBus_cmd_payload_data = _zz_65; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_108_ = (4'b0001); + _zz_66 = 4'b0001; end 2'b01 : begin - _zz_108_ = (4'b0011); + _zz_66 = 4'b0011; end default : begin - _zz_108_ = (4'b1111); + _zz_66 = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_108_ <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; + assign execute_DBusSimplePlugin_formalMask = (_zz_66 <<< dBus_cmd_payload_address[1 : 0]); + assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; + assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; + assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign _zz_81_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE))); - assign _zz_74_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign _zz_75_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign _zz_76_ = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign _zz_77_ = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign _zz_78_ = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign _zz_79_ = DBusSimplePlugin_mmuBus_rsp_exception; - assign _zz_80_ = DBusSimplePlugin_mmuBus_rsp_refilling; - assign _zz_73_ = dBus_rsp_data; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_174_)begin + if(_zz_133)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end if(memory_ALIGNEMENT_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_MMU_RSP_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end else begin if(memory_MMU_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_175_)begin + if(_zz_134)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); - if(_zz_174_)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101); + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; + if(_zz_133)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_202_}; + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_174}; end - if(! memory_MMU_RSP_refilling) begin + if(! memory_MMU_RSP2_refilling) begin if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101)); + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); end end end @@ -2605,10 +2478,10 @@ module VexRiscv ( assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; always @ (*) begin DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_175_)begin + if(_zz_134)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -2631,63 +2504,63 @@ module VexRiscv ( endcase end - assign _zz_109_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_110_[31] = _zz_109_; - _zz_110_[30] = _zz_109_; - _zz_110_[29] = _zz_109_; - _zz_110_[28] = _zz_109_; - _zz_110_[27] = _zz_109_; - _zz_110_[26] = _zz_109_; - _zz_110_[25] = _zz_109_; - _zz_110_[24] = _zz_109_; - _zz_110_[23] = _zz_109_; - _zz_110_[22] = _zz_109_; - _zz_110_[21] = _zz_109_; - _zz_110_[20] = _zz_109_; - _zz_110_[19] = _zz_109_; - _zz_110_[18] = _zz_109_; - _zz_110_[17] = _zz_109_; - _zz_110_[16] = _zz_109_; - _zz_110_[15] = _zz_109_; - _zz_110_[14] = _zz_109_; - _zz_110_[13] = _zz_109_; - _zz_110_[12] = _zz_109_; - _zz_110_[11] = _zz_109_; - _zz_110_[10] = _zz_109_; - _zz_110_[9] = _zz_109_; - _zz_110_[8] = _zz_109_; - _zz_110_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_111_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_112_[31] = _zz_111_; - _zz_112_[30] = _zz_111_; - _zz_112_[29] = _zz_111_; - _zz_112_[28] = _zz_111_; - _zz_112_[27] = _zz_111_; - _zz_112_[26] = _zz_111_; - _zz_112_[25] = _zz_111_; - _zz_112_[24] = _zz_111_; - _zz_112_[23] = _zz_111_; - _zz_112_[22] = _zz_111_; - _zz_112_[21] = _zz_111_; - _zz_112_[20] = _zz_111_; - _zz_112_[19] = _zz_111_; - _zz_112_[18] = _zz_111_; - _zz_112_[17] = _zz_111_; - _zz_112_[16] = _zz_111_; - _zz_112_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_188_) + assign _zz_67 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_68[31] = _zz_67; + _zz_68[30] = _zz_67; + _zz_68[29] = _zz_67; + _zz_68[28] = _zz_67; + _zz_68[27] = _zz_67; + _zz_68[26] = _zz_67; + _zz_68[25] = _zz_67; + _zz_68[24] = _zz_67; + _zz_68[23] = _zz_67; + _zz_68[22] = _zz_67; + _zz_68[21] = _zz_67; + _zz_68[20] = _zz_67; + _zz_68[19] = _zz_67; + _zz_68[18] = _zz_67; + _zz_68[17] = _zz_67; + _zz_68[16] = _zz_67; + _zz_68[15] = _zz_67; + _zz_68[14] = _zz_67; + _zz_68[13] = _zz_67; + _zz_68[12] = _zz_67; + _zz_68[11] = _zz_67; + _zz_68[10] = _zz_67; + _zz_68[9] = _zz_67; + _zz_68[8] = _zz_67; + _zz_68[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_69 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_70[31] = _zz_69; + _zz_70[30] = _zz_69; + _zz_70[29] = _zz_69; + _zz_70[28] = _zz_69; + _zz_70[27] = _zz_69; + _zz_70[26] = _zz_69; + _zz_70[25] = _zz_69; + _zz_70[24] = _zz_69; + _zz_70[23] = _zz_69; + _zz_70[22] = _zz_69; + _zz_70[21] = _zz_69; + _zz_70[20] = _zz_69; + _zz_70[19] = _zz_69; + _zz_70[18] = _zz_69; + _zz_70[17] = _zz_69; + _zz_70[16] = _zz_69; + _zz_70[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_149) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_110_; + writeBack_DBusSimplePlugin_rspFormated = _zz_68; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_112_; + writeBack_DBusSimplePlugin_rspFormated = _zz_70; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -2695,71 +2568,71 @@ module VexRiscv ( endcase end - assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_virtualAddress; + assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign IBusSimplePlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress; + assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_114_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); - assign _zz_115_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_116_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_117_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_113_ = {(_zz_114_ != (1'b0)),{(((decode_INSTRUCTION & _zz_245_) == (32'b00000000000000000000000000010000)) != (1'b0)),{((_zz_246_ == _zz_247_) != (1'b0)),{(_zz_248_ != (1'b0)),{(_zz_249_ != _zz_250_),{_zz_251_,{_zz_252_,_zz_253_}}}}}}}; - assign _zz_71_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_345_) == (32'b00000000000000000001000001110011)),{(_zz_346_ == _zz_347_),{_zz_348_,{_zz_349_,_zz_350_}}}}}}} != (20'b00000000000000000000)); - assign _zz_118_ = _zz_113_[1 : 0]; - assign _zz_70_ = _zz_118_; - assign _zz_69_ = _zz_203_[0]; - assign _zz_68_ = _zz_204_[0]; - assign _zz_67_ = _zz_205_[0]; - assign _zz_66_ = _zz_206_[0]; - assign _zz_119_ = _zz_113_[8 : 7]; - assign _zz_65_ = _zz_119_; - assign _zz_64_ = _zz_207_[0]; - assign _zz_63_ = _zz_208_[0]; - assign _zz_120_ = _zz_113_[12 : 11]; - assign _zz_62_ = _zz_120_; - assign _zz_61_ = _zz_209_[0]; - assign _zz_121_ = _zz_113_[15 : 14]; - assign _zz_60_ = _zz_121_; - assign _zz_122_ = _zz_113_[17 : 16]; - assign _zz_59_ = _zz_122_; - assign _zz_123_ = _zz_113_[19 : 18]; - assign _zz_58_ = _zz_123_; - assign _zz_57_ = _zz_210_[0]; - assign _zz_56_ = _zz_211_[0]; - assign _zz_124_ = _zz_113_[23 : 22]; - assign _zz_55_ = _zz_124_; - assign _zz_54_ = _zz_212_[0]; - assign _zz_53_ = _zz_213_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign _zz_72 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_73 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_74 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz_75 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_71 = {(((decode_INSTRUCTION & _zz_223) == 32'h00000050) != 1'b0),{((_zz_224 == _zz_225) != 1'b0),{({_zz_226,_zz_227} != 2'b00),{(_zz_228 != _zz_229),{_zz_230,{_zz_231,_zz_232}}}}}}; + assign _zz_76 = _zz_71[1 : 0]; + assign _zz_46 = _zz_76; + assign _zz_77 = _zz_71[6 : 5]; + assign _zz_45 = _zz_77; + assign _zz_78 = _zz_71[8 : 7]; + assign _zz_44 = _zz_78; + assign _zz_79 = _zz_71[17 : 16]; + assign _zz_43 = _zz_79; + assign _zz_80 = _zz_71[20 : 19]; + assign _zz_42 = _zz_80; + assign _zz_81 = _zz_71[22 : 21]; + assign _zz_41 = _zz_81; + assign _zz_82 = _zz_71[25 : 24]; + assign _zz_40 = _zz_82; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_161_; - assign decode_RegFilePlugin_rs2Data = _zz_162_; - assign _zz_52_ = decode_RegFilePlugin_rs1Data; - assign _zz_51_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_122; + assign decode_RegFilePlugin_rs2Data = _zz_123; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_49_ && writeBack_arbitration_isFiring); - if(_zz_125_)begin + lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); + if(_zz_83)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_48_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_72_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_37[11 : 7]; + if(_zz_83)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_47; + if(_zz_83)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -2777,334 +2650,329 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_126_ = execute_IntAluPlugin_bitwise; + _zz_84 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_126_ = {31'd0, _zz_214_}; + _zz_84 = {31'd0, _zz_175}; end default : begin - _zz_126_ = execute_SRC_ADD_SUB; + _zz_84 = execute_SRC_ADD_SUB; end endcase end - assign _zz_46_ = _zz_126_; - assign _zz_44_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_127_ = execute_RS1; + _zz_85 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_127_ = {29'd0, _zz_215_}; + _zz_85 = {29'd0, _zz_176}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_127_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_85 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_127_ = {27'd0, _zz_216_}; - end - endcase - end - - assign _zz_43_ = _zz_127_; - assign _zz_128_ = _zz_217_[11]; - always @ (*) begin - _zz_129_[19] = _zz_128_; - _zz_129_[18] = _zz_128_; - _zz_129_[17] = _zz_128_; - _zz_129_[16] = _zz_128_; - _zz_129_[15] = _zz_128_; - _zz_129_[14] = _zz_128_; - _zz_129_[13] = _zz_128_; - _zz_129_[12] = _zz_128_; - _zz_129_[11] = _zz_128_; - _zz_129_[10] = _zz_128_; - _zz_129_[9] = _zz_128_; - _zz_129_[8] = _zz_128_; - _zz_129_[7] = _zz_128_; - _zz_129_[6] = _zz_128_; - _zz_129_[5] = _zz_128_; - _zz_129_[4] = _zz_128_; - _zz_129_[3] = _zz_128_; - _zz_129_[2] = _zz_128_; - _zz_129_[1] = _zz_128_; - _zz_129_[0] = _zz_128_; - end - - assign _zz_130_ = _zz_218_[11]; - always @ (*) begin - _zz_131_[19] = _zz_130_; - _zz_131_[18] = _zz_130_; - _zz_131_[17] = _zz_130_; - _zz_131_[16] = _zz_130_; - _zz_131_[15] = _zz_130_; - _zz_131_[14] = _zz_130_; - _zz_131_[13] = _zz_130_; - _zz_131_[12] = _zz_130_; - _zz_131_[11] = _zz_130_; - _zz_131_[10] = _zz_130_; - _zz_131_[9] = _zz_130_; - _zz_131_[8] = _zz_130_; - _zz_131_[7] = _zz_130_; - _zz_131_[6] = _zz_130_; - _zz_131_[5] = _zz_130_; - _zz_131_[4] = _zz_130_; - _zz_131_[3] = _zz_130_; - _zz_131_[2] = _zz_130_; - _zz_131_[1] = _zz_130_; - _zz_131_[0] = _zz_130_; + _zz_85 = {27'd0, _zz_177}; + end + endcase + end + + assign _zz_86 = _zz_178[11]; + always @ (*) begin + _zz_87[19] = _zz_86; + _zz_87[18] = _zz_86; + _zz_87[17] = _zz_86; + _zz_87[16] = _zz_86; + _zz_87[15] = _zz_86; + _zz_87[14] = _zz_86; + _zz_87[13] = _zz_86; + _zz_87[12] = _zz_86; + _zz_87[11] = _zz_86; + _zz_87[10] = _zz_86; + _zz_87[9] = _zz_86; + _zz_87[8] = _zz_86; + _zz_87[7] = _zz_86; + _zz_87[6] = _zz_86; + _zz_87[5] = _zz_86; + _zz_87[4] = _zz_86; + _zz_87[3] = _zz_86; + _zz_87[2] = _zz_86; + _zz_87[1] = _zz_86; + _zz_87[0] = _zz_86; + end + + assign _zz_88 = _zz_179[11]; + always @ (*) begin + _zz_89[19] = _zz_88; + _zz_89[18] = _zz_88; + _zz_89[17] = _zz_88; + _zz_89[16] = _zz_88; + _zz_89[15] = _zz_88; + _zz_89[14] = _zz_88; + _zz_89[13] = _zz_88; + _zz_89[12] = _zz_88; + _zz_89[11] = _zz_88; + _zz_89[10] = _zz_88; + _zz_89[9] = _zz_88; + _zz_89[8] = _zz_88; + _zz_89[7] = _zz_88; + _zz_89[6] = _zz_88; + _zz_89[5] = _zz_88; + _zz_89[4] = _zz_88; + _zz_89[3] = _zz_88; + _zz_89[2] = _zz_88; + _zz_89[1] = _zz_88; + _zz_89[0] = _zz_88; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_132_ = execute_RS2; + _zz_90 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_132_ = {_zz_129_,execute_INSTRUCTION[31 : 20]}; + _zz_90 = {_zz_87,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_132_ = {_zz_131_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_90 = {_zz_89,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_132_ = _zz_39_; + _zz_90 = _zz_32; end endcase end - assign _zz_41_ = _zz_132_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_219_; + execute_SrcPlugin_addSub = _zz_180; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_38_ = execute_SrcPlugin_addSub; - assign _zz_37_ = execute_SrcPlugin_addSub; - assign _zz_36_ = execute_SrcPlugin_less; assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); - assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_133_ = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_91 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_133_ = _zz_226_; + _zz_91 = _zz_187; end endcase end always @ (*) begin - _zz_134_ = 1'b0; - if(_zz_137_)begin - if((_zz_138_ == decode_INSTRUCTION[19 : 15]))begin - _zz_134_ = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end - if(_zz_176_)begin - if(_zz_177_)begin + if(_zz_135)begin + if(_zz_136)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_134_ = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_178_)begin - if(_zz_179_)begin + if(_zz_137)begin + if(_zz_138)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_134_ = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_180_)begin - if(_zz_181_)begin + if(_zz_139)begin + if(_zz_140)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_134_ = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_134_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_135_ = 1'b0; - if(_zz_137_)begin - if((_zz_138_ == decode_INSTRUCTION[24 : 20]))begin - _zz_135_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end - if(_zz_176_)begin - if(_zz_177_)begin + if(_zz_135)begin + if(_zz_136)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_135_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_178_)begin - if(_zz_179_)begin + if(_zz_137)begin + if(_zz_138)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_135_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_180_)begin - if(_zz_181_)begin + if(_zz_139)begin + if(_zz_140)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_135_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_135_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_136_ = (_zz_49_ && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_38 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_37[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_47; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_139_ = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_139_ == (3'b000))) begin - _zz_140_ = execute_BranchPlugin_eq; - end else if((_zz_139_ == (3'b001))) begin - _zz_140_ = (! execute_BranchPlugin_eq); - end else if((((_zz_139_ & (3'b101)) == (3'b101)))) begin - _zz_140_ = (! execute_SRC_LESS); + assign _zz_92 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_92 == 3'b000)) begin + _zz_93 = execute_BranchPlugin_eq; + end else if((_zz_92 == 3'b001)) begin + _zz_93 = (! execute_BranchPlugin_eq); + end else if((((_zz_92 & 3'b101) == 3'b101))) begin + _zz_93 = (! execute_SRC_LESS); end else begin - _zz_140_ = execute_SRC_LESS; + _zz_93 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_141_ = 1'b0; + _zz_94 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_141_ = 1'b1; + _zz_94 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_141_ = 1'b1; + _zz_94 = 1'b1; end default : begin - _zz_141_ = _zz_140_; + _zz_94 = _zz_93; end endcase end - assign _zz_33_ = _zz_141_; assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_142_ = _zz_228_[19]; - always @ (*) begin - _zz_143_[10] = _zz_142_; - _zz_143_[9] = _zz_142_; - _zz_143_[8] = _zz_142_; - _zz_143_[7] = _zz_142_; - _zz_143_[6] = _zz_142_; - _zz_143_[5] = _zz_142_; - _zz_143_[4] = _zz_142_; - _zz_143_[3] = _zz_142_; - _zz_143_[2] = _zz_142_; - _zz_143_[1] = _zz_142_; - _zz_143_[0] = _zz_142_; - end - - assign _zz_144_ = _zz_229_[11]; - always @ (*) begin - _zz_145_[19] = _zz_144_; - _zz_145_[18] = _zz_144_; - _zz_145_[17] = _zz_144_; - _zz_145_[16] = _zz_144_; - _zz_145_[15] = _zz_144_; - _zz_145_[14] = _zz_144_; - _zz_145_[13] = _zz_144_; - _zz_145_[12] = _zz_144_; - _zz_145_[11] = _zz_144_; - _zz_145_[10] = _zz_144_; - _zz_145_[9] = _zz_144_; - _zz_145_[8] = _zz_144_; - _zz_145_[7] = _zz_144_; - _zz_145_[6] = _zz_144_; - _zz_145_[5] = _zz_144_; - _zz_145_[4] = _zz_144_; - _zz_145_[3] = _zz_144_; - _zz_145_[2] = _zz_144_; - _zz_145_[1] = _zz_144_; - _zz_145_[0] = _zz_144_; - end - - assign _zz_146_ = _zz_230_[11]; - always @ (*) begin - _zz_147_[18] = _zz_146_; - _zz_147_[17] = _zz_146_; - _zz_147_[16] = _zz_146_; - _zz_147_[15] = _zz_146_; - _zz_147_[14] = _zz_146_; - _zz_147_[13] = _zz_146_; - _zz_147_[12] = _zz_146_; - _zz_147_[11] = _zz_146_; - _zz_147_[10] = _zz_146_; - _zz_147_[9] = _zz_146_; - _zz_147_[8] = _zz_146_; - _zz_147_[7] = _zz_146_; - _zz_147_[6] = _zz_146_; - _zz_147_[5] = _zz_146_; - _zz_147_[4] = _zz_146_; - _zz_147_[3] = _zz_146_; - _zz_147_[2] = _zz_146_; - _zz_147_[1] = _zz_146_; - _zz_147_[0] = _zz_146_; + assign _zz_95 = _zz_189[19]; + always @ (*) begin + _zz_96[10] = _zz_95; + _zz_96[9] = _zz_95; + _zz_96[8] = _zz_95; + _zz_96[7] = _zz_95; + _zz_96[6] = _zz_95; + _zz_96[5] = _zz_95; + _zz_96[4] = _zz_95; + _zz_96[3] = _zz_95; + _zz_96[2] = _zz_95; + _zz_96[1] = _zz_95; + _zz_96[0] = _zz_95; + end + + assign _zz_97 = _zz_190[11]; + always @ (*) begin + _zz_98[19] = _zz_97; + _zz_98[18] = _zz_97; + _zz_98[17] = _zz_97; + _zz_98[16] = _zz_97; + _zz_98[15] = _zz_97; + _zz_98[14] = _zz_97; + _zz_98[13] = _zz_97; + _zz_98[12] = _zz_97; + _zz_98[11] = _zz_97; + _zz_98[10] = _zz_97; + _zz_98[9] = _zz_97; + _zz_98[8] = _zz_97; + _zz_98[7] = _zz_97; + _zz_98[6] = _zz_97; + _zz_98[5] = _zz_97; + _zz_98[4] = _zz_97; + _zz_98[3] = _zz_97; + _zz_98[2] = _zz_97; + _zz_98[1] = _zz_97; + _zz_98[0] = _zz_97; + end + + assign _zz_99 = _zz_191[11]; + always @ (*) begin + _zz_100[18] = _zz_99; + _zz_100[17] = _zz_99; + _zz_100[16] = _zz_99; + _zz_100[15] = _zz_99; + _zz_100[14] = _zz_99; + _zz_100[13] = _zz_99; + _zz_100[12] = _zz_99; + _zz_100[11] = _zz_99; + _zz_100[10] = _zz_99; + _zz_100[9] = _zz_99; + _zz_100[8] = _zz_99; + _zz_100[7] = _zz_99; + _zz_100[6] = _zz_99; + _zz_100[5] = _zz_99; + _zz_100[4] = _zz_99; + _zz_100[3] = _zz_99; + _zz_100[2] = _zz_99; + _zz_100[1] = _zz_99; + _zz_100[0] = _zz_99; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_148_ = {{_zz_143_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_101 = {{_zz_96,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_148_ = {_zz_145_,execute_INSTRUCTION[31 : 20]}; + _zz_101 = {_zz_98,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_148_ = {{_zz_147_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_101 = {{_zz_100,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_148_; + assign execute_BranchPlugin_branch_src2 = _zz_101; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_31_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; always @ (*) begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign CsrPlugin_misa_base = (2'b01); - assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); - assign _zz_149_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_150_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_151_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign _zz_102 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_103 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_104 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_152_ = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; - assign _zz_153_ = _zz_231_[0]; - assign _zz_154_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_155_ = _zz_233_[0]; + assign _zz_105 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; + assign _zz_106 = _zz_192[0]; + assign _zz_107 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_108 = _zz_194[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_166_)begin + if(_zz_127)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3124,7 +2992,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_168_)begin + if(_zz_128)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3145,9 +3013,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusSimplePlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -3171,7 +3040,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; @@ -3182,7 +3051,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3193,52 +3062,45 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_29_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_28_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - assign execute_CsrPlugin_inWfi = 1'b0; - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000001 : begin + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_141)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3257,20 +3119,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_182_)begin + if(_zz_142)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_182_)begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_142)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -3278,53 +3140,24 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_156_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_157_; - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_141)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_141)begin + execute_CsrPlugin_readInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_189_) + case(_zz_150) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3335,37 +3168,37 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign _zz_157_ = (_zz_156_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_157_ != (32'b00000000000000000000000000000000)); - assign _zz_25_ = decode_ALU_BITWISE_CTRL; - assign _zz_23_ = _zz_58_; - assign _zz_47_ = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_22_ = decode_SHIFT_CTRL; - assign _zz_20_ = _zz_70_; - assign _zz_35_ = decode_to_execute_SHIFT_CTRL; - assign _zz_19_ = decode_ALU_CTRL; - assign _zz_17_ = _zz_60_; - assign _zz_45_ = decode_to_execute_ALU_CTRL; - assign _zz_16_ = decode_BRANCH_CTRL; - assign _zz_14_ = _zz_59_; - assign _zz_32_ = decode_to_execute_BRANCH_CTRL; - assign _zz_13_ = decode_SRC1_CTRL; - assign _zz_11_ = _zz_65_; - assign _zz_42_ = decode_to_execute_SRC1_CTRL; - assign _zz_10_ = decode_ENV_CTRL; - assign _zz_7_ = execute_ENV_CTRL; - assign _zz_5_ = memory_ENV_CTRL; - assign _zz_8_ = _zz_55_; - assign _zz_27_ = decode_to_execute_ENV_CTRL; - assign _zz_26_ = execute_to_memory_ENV_CTRL; - assign _zz_30_ = memory_to_writeBack_ENV_CTRL; - assign _zz_3_ = decode_SRC2_CTRL; - assign _zz_1_ = _zz_62_; - assign _zz_40_ = decode_to_execute_SRC2_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign _zz_110 = (_zz_109 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_110 != 32'h0); + assign _zz_25 = decode_SRC1_CTRL; + assign _zz_23 = _zz_46; + assign _zz_34 = decode_to_execute_SRC1_CTRL; + assign _zz_22 = decode_ALU_CTRL; + assign _zz_20 = _zz_45; + assign _zz_35 = decode_to_execute_ALU_CTRL; + assign _zz_19 = decode_SRC2_CTRL; + assign _zz_17 = _zz_44; + assign _zz_33 = decode_to_execute_SRC2_CTRL; + assign _zz_16 = decode_ALU_BITWISE_CTRL; + assign _zz_14 = _zz_43; + assign _zz_36 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_13 = decode_SHIFT_CTRL; + assign _zz_11 = _zz_42; + assign _zz_31 = decode_to_execute_SHIFT_CTRL; + assign _zz_10 = decode_BRANCH_CTRL; + assign _zz_8 = _zz_41; + assign _zz_29 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_40; + assign _zz_27 = decode_to_execute_ENV_CTRL; + assign _zz_26 = execute_to_memory_ENV_CTRL; + assign _zz_28 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -3382,15 +3215,79 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_111 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_111[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_111[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_111[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_112 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_112[11 : 11] = CsrPlugin_mip_MEIP; + _zz_112[7 : 7] = CsrPlugin_mip_MTIP; + _zz_112[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_113 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_113[11 : 11] = CsrPlugin_mie_MEIE; + _zz_113[7 : 7] = CsrPlugin_mie_MTIE; + _zz_113[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_114 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_114[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_115 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_115[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_115[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_116 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_116[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_117 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_117[31 : 0] = _zz_109; + end + end + + always @ (*) begin + _zz_118 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_118[31 : 0] = _zz_110; + end + end + + assign execute_CsrPlugin_readData = (((_zz_111 | _zz_112) | (_zz_113 | _zz_114)) | ((_zz_115 | _zz_116) | (_zz_117 | _zz_118))); assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); - assign iBus_cmd_m2sPipe_valid = _zz_158_; - assign iBus_cmd_m2sPipe_payload_pc = _zz_159_; + assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; + assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); - assign iBusWishbone_CTI = (3'b000); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_CTI = 3'b000; + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); @@ -3404,26 +3301,26 @@ module VexRiscv ( assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); - assign dBusWishbone_CTI = (3'b000); - assign dBusWishbone_BTE = (2'b00); + assign dBusWishbone_CTI = 3'b000; + assign dBusWishbone_BTE = 2'b00; always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_160_ = (4'b0001); + _zz_119 = 4'b0001; end 2'b01 : begin - _zz_160_ = (4'b0011); + _zz_119 = 4'b0011; end default : begin - _zz_160_ = (4'b1111); + _zz_119 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = _zz_241_[3:0]; + dBusWishbone_SEL = (_zz_119 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin - dBusWishbone_SEL = (4'b1111); + dBusWishbone_SEL = 4'b1111; end end @@ -3435,27 +3332,28 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; + assign _zz_121 = 1'b0; always @ (posedge clk) begin if(reset) begin IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; IBusSimplePlugin_fetchPc_booted <= 1'b0; IBusSimplePlugin_fetchPc_inc <= 1'b0; - _zz_99_ <= 1'b0; - _zz_100_ <= 1'b0; + _zz_57 <= 1'b0; + _zz_58 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusSimplePlugin_injector_decodeRemoved <= 1'b0; - IBusSimplePlugin_pendingCmd <= (3'b000); - IBusSimplePlugin_rspJoin_discardCounter <= (3'b000); - _zz_125_ <= 1'b1; + IBusSimplePlugin_pending_value <= 3'b000; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; + _zz_83 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_137_ <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -3464,20 +3362,27 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - _zz_156_ <= (32'b00000000000000000000000000000000); + _zz_109 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_158_ <= 1'b0; + iBus_cmd_m2sPipe_rValid <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin + if(IBusSimplePlugin_fetchPc_correction)begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + end IBusSimplePlugin_fetchPc_booted <= 1'b1; - if((IBusSimplePlugin_fetchPc_corrected || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin @@ -3486,77 +3391,91 @@ module VexRiscv ( if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end - if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetcherflushIt) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; end - if(IBusSimplePlugin_fetcherflushIt)begin - _zz_99_ <= 1'b0; + if(IBusSimplePlugin_iBusRsp_flush)begin + _zz_57 <= 1'b0; end - if(_zz_97_)begin - _zz_99_ <= IBusSimplePlugin_iBusRsp_stages_0_output_valid; + if(_zz_55)begin + _zz_57 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin - _zz_100_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; + if(decode_arbitration_removeIt)begin + _zz_58 <= 1'b0; end - if(IBusSimplePlugin_fetcherflushIt)begin - _zz_100_ <= 1'b0; + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_58 <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; end if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusSimplePlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_decodeRemoved <= 1'b0; - end - IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext; - IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_rspJoin_discardCounter - _zz_199_); - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_pendingCmd - _zz_201_); - end - _zz_125_ <= 1'b0; - if(_zz_164_)begin - if(_zz_167_)begin + IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_171); + if(IBusSimplePlugin_iBusRsp_flush)begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_173); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + _zz_83 <= 1'b0; + if(_zz_125)begin + if(_zz_143)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -3566,7 +3485,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_137_ <= _zz_136_; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -3588,19 +3507,38 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_183_)begin - if(_zz_184_)begin + if(_zz_144)begin + if(_zz_145)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_185_)begin + if(_zz_146)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_186_)begin + if(_zz_147)begin CsrPlugin_interrupt_valid <= 1'b1; end end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_169_)begin + if(_zz_129)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3611,10 +3549,10 @@ module VexRiscv ( end endcase end - if(_zz_170_)begin - case(_zz_171_) + if(_zz_130)begin + case(_zz_131) 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; end @@ -3622,13 +3560,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_151_,{_zz_150_,_zz_149_}} != (3'b000)); - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end + execute_CsrPlugin_wfiWake <= (({_zz_104,{_zz_103,_zz_102}} != 3'b000) || CsrPlugin_thirdPartyWake); if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -3647,45 +3579,29 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_235_[0]; - CsrPlugin_mstatus_MIE <= _zz_236_[0]; - end - end - 12'b001101000001 : begin - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_238_[0]; - CsrPlugin_mie_MTIE <= _zz_239_[0]; - CsrPlugin_mie_MSIE <= _zz_240_[0]; - end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_196[0]; + CsrPlugin_mstatus_MIE <= _zz_197[0]; end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_199[0]; + CsrPlugin_mie_MTIE <= _zz_200[0]; + CsrPlugin_mie_MSIE <= _zz_201[0]; end - default : begin + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_109 <= execute_CsrPlugin_writeData[31 : 0]; end - endcase + end if(iBus_cmd_ready)begin - _zz_158_ <= iBus_cmd_valid; + iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; end - if(_zz_187_)begin + if(_zz_148)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -3696,72 +3612,67 @@ module VexRiscv ( end always @ (posedge clk) begin - if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin - _zz_101_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; - _zz_102_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; - _zz_103_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; - _zz_104_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_59 <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_60 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_61 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_62 <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; end if(IBusSimplePlugin_injector_decodeInput_ready)begin - IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; end if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; + IBusSimplePlugin_mmu_joinCtx_isPaging <= IBusSimplePlugin_mmuBus_rsp_isPaging; IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; + IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; end - if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin - $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); - end - if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin - $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); - end - if(_zz_164_)begin - if(_zz_167_)begin - execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + if(_zz_125)begin + if(_zz_143)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - if(_zz_136_)begin - _zz_138_ <= _zz_48_[11 : 7]; - end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_166_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_153_ ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_127)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_106 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_106 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_168_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_155_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_128)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_108 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_108 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_183_)begin - if(_zz_184_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_144)begin + if(_zz_145)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_185_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_146)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_186_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_147)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_169_)begin + if(_zz_129)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -3777,67 +3688,70 @@ module VexRiscv ( end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_24_; + decode_to_execute_PC <= decode_PC; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_21_; + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_32; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress; - execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess; - execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead; - execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite; - execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute; - execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception; - execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling; + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_18_; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_48; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_15_; + decode_to_execute_SRC1_CTRL <= _zz_24; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_12_; + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_21; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9_; + decode_to_execute_SRC2_CTRL <= _zz_18; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6_; + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4_; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; @@ -3852,110 +3766,126 @@ module VexRiscv ( decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_85_; + decode_to_execute_ALU_BITWISE_CTRL <= _zz_15; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_12; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_84_; + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_9; end if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; end if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + execute_to_memory_ENV_CTRL <= _zz_3; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + memory_to_writeBack_ENV_CTRL <= _zz_1; end if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; end if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_39_; + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; + execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; + execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; + execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; + execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; + execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; + execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; + execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; + execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; end if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_34_; + execute_to_memory_REGFILE_WRITE_DATA <= _zz_30; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_2_; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end if((! execute_arbitration_isStuck))begin - decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end - end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_237_[0]; - end - end - 12'b001101000011 : begin + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_198[0]; end - 12'b111111000000 : begin - end - 12'b001100000100 : begin - end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - default : begin + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end - endcase + end if(iBus_cmd_ready)begin - _zz_159_ <= iBus_cmd_payload_pc; + iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; end - if(_zz_187_)begin + if(_zz_148)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; @@ -3963,5 +3893,134 @@ module VexRiscv ( end end + endmodule +module StreamFifoLowLatency ( + input io_push_valid, + output io_push_ready, + input io_push_payload_error, + input [31:0] io_push_payload_inst, + output reg io_pop_valid, + input io_pop_ready, + output reg io_pop_payload_error, + output reg [31:0] io_pop_payload_inst, + input io_flush, + output [0:0] io_occupancy, + input clk, + input reset +); + wire _zz_4; + wire [0:0] _zz_5; + reg _zz_1; + reg pushPtr_willIncrement; + reg pushPtr_willClear; + wire pushPtr_willOverflowIfInc; + wire pushPtr_willOverflow; + reg popPtr_willIncrement; + reg popPtr_willClear; + wire popPtr_willOverflowIfInc; + wire popPtr_willOverflow; + wire ptrMatch; + reg risingOccupancy; + wire empty; + wire full; + wire pushing; + wire popping; + wire [32:0] _zz_2; + reg [32:0] _zz_3; + + assign _zz_4 = (! empty); + assign _zz_5 = _zz_2[0 : 0]; + always @ (*) begin + _zz_1 = 1'b0; + if(pushing)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + pushPtr_willIncrement = 1'b0; + if(pushing)begin + pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + pushPtr_willClear = 1'b0; + if(io_flush)begin + pushPtr_willClear = 1'b1; + end + end + + assign pushPtr_willOverflowIfInc = 1'b1; + assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); + always @ (*) begin + popPtr_willIncrement = 1'b0; + if(popping)begin + popPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + popPtr_willClear = 1'b0; + if(io_flush)begin + popPtr_willClear = 1'b1; + end + end + + assign popPtr_willOverflowIfInc = 1'b1; + assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); + assign ptrMatch = 1'b1; + assign empty = (ptrMatch && (! risingOccupancy)); + assign full = (ptrMatch && risingOccupancy); + assign pushing = (io_push_valid && io_push_ready); + assign popping = (io_pop_valid && io_pop_ready); + assign io_push_ready = (! full); + always @ (*) begin + if(_zz_4)begin + io_pop_valid = 1'b1; + end else begin + io_pop_valid = io_push_valid; + end + end + + assign _zz_2 = _zz_3; + always @ (*) begin + if(_zz_4)begin + io_pop_payload_error = _zz_5[0]; + end else begin + io_pop_payload_error = io_push_payload_error; + end + end + + always @ (*) begin + if(_zz_4)begin + io_pop_payload_inst = _zz_2[32 : 1]; + end else begin + io_pop_payload_inst = io_push_payload_inst; + end + end + + assign io_occupancy = (risingOccupancy && ptrMatch); + always @ (posedge clk) begin + if(reset) begin + risingOccupancy <= 1'b0; + end else begin + if((pushing != popping))begin + risingOccupancy <= pushing; + end + if(io_flush)begin + risingOccupancy <= 1'b0; + end + end + end + + always @ (posedge clk) begin + if(_zz_1)begin + _zz_3 <= {io_push_payload_inst,io_push_payload_error}; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v index 727bac6..30baf5c 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v @@ -1,34 +1,29 @@ -// Generator : SpinalHDL v1.3.6 git head : 9bf01e7f360e003fac1dd5ca8b8f4bffec0e52b8 -// Date : 23/03/2020, 17:07:01 +// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 // Component : VexRiscv +// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - `define EnvCtrlEnum_defaultEncoding_type [1:0] `define EnvCtrlEnum_defaultEncoding_NONE 2'b00 `define EnvCtrlEnum_defaultEncoding_XRET 2'b01 `define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + `define ShiftCtrlEnum_defaultEncoding_type [1:0] `define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 `define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 `define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 `define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 `define Src2CtrlEnum_defaultEncoding_type [1:0] `define Src2CtrlEnum_defaultEncoding_RS 2'b00 @@ -36,1503 +31,1357 @@ `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -module StreamFifoLowLatency ( - input io_push_valid, - output io_push_ready, - input io_push_payload_error, - input [31:0] io_push_payload_inst, - output reg io_pop_valid, - input io_pop_ready, - output reg io_pop_payload_error, - output reg [31:0] io_pop_payload_inst, - input io_flush, - output [0:0] io_occupancy, - input clk, - input reset); - wire _zz_5_; - wire [0:0] _zz_6_; - reg _zz_1_; - reg pushPtr_willIncrement; - reg pushPtr_willClear; - wire pushPtr_willOverflowIfInc; - wire pushPtr_willOverflow; - reg popPtr_willIncrement; - reg popPtr_willClear; - wire popPtr_willOverflowIfInc; - wire popPtr_willOverflow; - wire ptrMatch; - reg risingOccupancy; - wire empty; - wire full; - wire pushing; - wire popping; - wire [32:0] _zz_2_; - wire [32:0] _zz_3_; - reg [32:0] _zz_4_; - assign _zz_5_ = (! empty); - assign _zz_6_ = _zz_2_[0 : 0]; - always @ (*) begin - _zz_1_ = 1'b0; - if(pushing)begin - _zz_1_ = 1'b1; - end - end - - always @ (*) begin - pushPtr_willIncrement = 1'b0; - if(pushing)begin - pushPtr_willIncrement = 1'b1; - end - end - - always @ (*) begin - pushPtr_willClear = 1'b0; - if(io_flush)begin - pushPtr_willClear = 1'b1; - end - end - - assign pushPtr_willOverflowIfInc = 1'b1; - assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); - always @ (*) begin - popPtr_willIncrement = 1'b0; - if(popping)begin - popPtr_willIncrement = 1'b1; - end - end - - always @ (*) begin - popPtr_willClear = 1'b0; - if(io_flush)begin - popPtr_willClear = 1'b1; - end - end - - assign popPtr_willOverflowIfInc = 1'b1; - assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); - assign ptrMatch = 1'b1; - assign empty = (ptrMatch && (! risingOccupancy)); - assign full = (ptrMatch && risingOccupancy); - assign pushing = (io_push_valid && io_push_ready); - assign popping = (io_pop_valid && io_pop_ready); - assign io_push_ready = (! full); - always @ (*) begin - if(_zz_5_)begin - io_pop_valid = 1'b1; - end else begin - io_pop_valid = io_push_valid; - end - end - - assign _zz_2_ = _zz_3_; - always @ (*) begin - if(_zz_5_)begin - io_pop_payload_error = _zz_6_[0]; - end else begin - io_pop_payload_error = io_push_payload_error; - end - end - - always @ (*) begin - if(_zz_5_)begin - io_pop_payload_inst = _zz_2_[32 : 1]; - end else begin - io_pop_payload_inst = io_push_payload_inst; - end - end - - assign io_occupancy = (risingOccupancy && ptrMatch); - assign _zz_3_ = _zz_4_; - always @ (posedge clk) begin - if(reset) begin - risingOccupancy <= 1'b0; - end else begin - if((pushing != popping))begin - risingOccupancy <= pushing; - end - if(io_flush)begin - risingOccupancy <= 1'b0; - end - end - end +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - always @ (posedge clk) begin - if(_zz_1_)begin - _zz_4_ <= {io_push_payload_inst,io_push_payload_error}; - end - end +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -endmodule module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output iBusWishbone_CYC, - output iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [1:0] iBusWishbone_BTE, - output [2:0] iBusWishbone_CTI, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output reg [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [1:0] dBusWishbone_BTE, - output [2:0] dBusWishbone_CTI, - input clk, - input reset, - input debugReset); - reg [31:0] _zz_165_; - reg [31:0] _zz_166_; - reg [31:0] _zz_167_; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; - wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; - wire _zz_168_; - wire _zz_169_; - wire _zz_170_; - wire _zz_171_; - wire _zz_172_; - wire _zz_173_; - wire _zz_174_; - wire _zz_175_; - wire _zz_176_; - wire _zz_177_; - wire [1:0] _zz_178_; - wire _zz_179_; - wire _zz_180_; - wire _zz_181_; - wire _zz_182_; - wire _zz_183_; - wire _zz_184_; - wire _zz_185_; - wire _zz_186_; - wire _zz_187_; - wire _zz_188_; - wire _zz_189_; - wire [5:0] _zz_190_; - wire _zz_191_; - wire _zz_192_; - wire _zz_193_; - wire _zz_194_; - wire _zz_195_; - wire [1:0] _zz_196_; - wire _zz_197_; - wire [3:0] _zz_198_; - wire [2:0] _zz_199_; - wire [31:0] _zz_200_; - wire [2:0] _zz_201_; - wire [0:0] _zz_202_; - wire [2:0] _zz_203_; - wire [0:0] _zz_204_; - wire [2:0] _zz_205_; - wire [0:0] _zz_206_; - wire [2:0] _zz_207_; - wire [0:0] _zz_208_; - wire [2:0] _zz_209_; - wire [2:0] _zz_210_; - wire [0:0] _zz_211_; - wire [0:0] _zz_212_; - wire [0:0] _zz_213_; - wire [0:0] _zz_214_; - wire [0:0] _zz_215_; - wire [0:0] _zz_216_; - wire [0:0] _zz_217_; - wire [0:0] _zz_218_; - wire [0:0] _zz_219_; - wire [0:0] _zz_220_; - wire [0:0] _zz_221_; - wire [0:0] _zz_222_; - wire [0:0] _zz_223_; - wire [2:0] _zz_224_; - wire [4:0] _zz_225_; - wire [11:0] _zz_226_; - wire [11:0] _zz_227_; - wire [31:0] _zz_228_; - wire [31:0] _zz_229_; - wire [31:0] _zz_230_; - wire [31:0] _zz_231_; - wire [31:0] _zz_232_; - wire [31:0] _zz_233_; - wire [31:0] _zz_234_; - wire [31:0] _zz_235_; - wire [32:0] _zz_236_; - wire [19:0] _zz_237_; - wire [11:0] _zz_238_; - wire [11:0] _zz_239_; - wire [1:0] _zz_240_; - wire [1:0] _zz_241_; - wire [1:0] _zz_242_; - wire [1:0] _zz_243_; - wire [0:0] _zz_244_; - wire [0:0] _zz_245_; - wire [0:0] _zz_246_; - wire [0:0] _zz_247_; - wire [0:0] _zz_248_; - wire [0:0] _zz_249_; - wire [6:0] _zz_250_; - wire _zz_251_; - wire _zz_252_; - wire [1:0] _zz_253_; - wire [31:0] _zz_254_; - wire [31:0] _zz_255_; - wire _zz_256_; - wire [0:0] _zz_257_; - wire [0:0] _zz_258_; - wire [31:0] _zz_259_; - wire [31:0] _zz_260_; - wire [0:0] _zz_261_; - wire [1:0] _zz_262_; - wire [0:0] _zz_263_; - wire [0:0] _zz_264_; - wire _zz_265_; - wire [0:0] _zz_266_; - wire [20:0] _zz_267_; - wire [31:0] _zz_268_; - wire [31:0] _zz_269_; - wire [31:0] _zz_270_; - wire [31:0] _zz_271_; - wire [31:0] _zz_272_; - wire [31:0] _zz_273_; - wire [31:0] _zz_274_; - wire [31:0] _zz_275_; - wire [31:0] _zz_276_; - wire _zz_277_; - wire [1:0] _zz_278_; - wire [1:0] _zz_279_; - wire _zz_280_; - wire [0:0] _zz_281_; - wire [17:0] _zz_282_; - wire [31:0] _zz_283_; - wire [31:0] _zz_284_; - wire _zz_285_; - wire [0:0] _zz_286_; - wire [0:0] _zz_287_; - wire [0:0] _zz_288_; - wire [0:0] _zz_289_; - wire _zz_290_; - wire [0:0] _zz_291_; - wire [14:0] _zz_292_; - wire [31:0] _zz_293_; - wire [31:0] _zz_294_; - wire [31:0] _zz_295_; - wire _zz_296_; - wire _zz_297_; - wire [0:0] _zz_298_; - wire [4:0] _zz_299_; - wire [0:0] _zz_300_; - wire [0:0] _zz_301_; - wire _zz_302_; - wire [0:0] _zz_303_; - wire [11:0] _zz_304_; - wire [31:0] _zz_305_; - wire [31:0] _zz_306_; - wire _zz_307_; - wire [0:0] _zz_308_; - wire [1:0] _zz_309_; - wire [31:0] _zz_310_; - wire [31:0] _zz_311_; - wire [31:0] _zz_312_; - wire _zz_313_; - wire [1:0] _zz_314_; - wire [1:0] _zz_315_; - wire _zz_316_; - wire [0:0] _zz_317_; - wire [8:0] _zz_318_; - wire [31:0] _zz_319_; - wire [31:0] _zz_320_; - wire [31:0] _zz_321_; - wire [31:0] _zz_322_; - wire [31:0] _zz_323_; - wire [31:0] _zz_324_; - wire _zz_325_; - wire [0:0] _zz_326_; - wire [1:0] _zz_327_; - wire [1:0] _zz_328_; - wire [1:0] _zz_329_; - wire _zz_330_; - wire [0:0] _zz_331_; - wire [5:0] _zz_332_; - wire [31:0] _zz_333_; - wire [31:0] _zz_334_; - wire [31:0] _zz_335_; - wire [31:0] _zz_336_; - wire [31:0] _zz_337_; - wire [31:0] _zz_338_; - wire [31:0] _zz_339_; - wire [31:0] _zz_340_; - wire [31:0] _zz_341_; - wire _zz_342_; - wire _zz_343_; - wire _zz_344_; - wire [1:0] _zz_345_; - wire [1:0] _zz_346_; - wire _zz_347_; - wire [0:0] _zz_348_; - wire [2:0] _zz_349_; - wire [31:0] _zz_350_; - wire [31:0] _zz_351_; - wire [31:0] _zz_352_; - wire [31:0] _zz_353_; - wire [31:0] _zz_354_; - wire [31:0] _zz_355_; - wire _zz_356_; - wire [1:0] _zz_357_; - wire [1:0] _zz_358_; - wire _zz_359_; - wire _zz_360_; - wire [31:0] _zz_361_; - wire [31:0] _zz_362_; - wire [31:0] _zz_363_; - wire _zz_364_; - wire [0:0] _zz_365_; - wire [12:0] _zz_366_; - wire [31:0] _zz_367_; - wire [31:0] _zz_368_; - wire [31:0] _zz_369_; - wire _zz_370_; - wire [0:0] _zz_371_; - wire [6:0] _zz_372_; - wire [31:0] _zz_373_; - wire [31:0] _zz_374_; - wire [31:0] _zz_375_; - wire _zz_376_; - wire [0:0] _zz_377_; - wire [0:0] _zz_378_; - wire decode_DO_EBREAK; - wire decode_IS_CSR; - wire [31:0] decode_RS1; - wire execute_BRANCH_DO; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire decode_CSR_READ_OPCODE; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_1_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_2_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_3_; - wire decode_MEMORY_STORE; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_4_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_5_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_6_; - wire [31:0] execute_BRANCH_CALC; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_CSR_WRITE_OPCODE; - wire decode_SRC2_FORCE_ZERO; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10_; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_11_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_12_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_13_; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16_; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_17_; - wire `AluCtrlEnum_defaultEncoding_type _zz_18_; - wire `AluCtrlEnum_defaultEncoding_type _zz_19_; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22_; - wire [31:0] memory_MEMORY_READ_DATA; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; - wire [31:0] execute_FORMAL_PC_NEXT; - wire [31:0] decode_FORMAL_PC_NEXT; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_23_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_24_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_25_; - wire [31:0] decode_RS2; - wire decode_SRC_LESS_UNSIGNED; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; - wire _zz_26_; - wire execute_CSR_READ_OPCODE; - wire execute_CSR_WRITE_OPCODE; - wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27_; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28_; - wire _zz_29_; - wire _zz_30_; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_31_; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] _zz_32_; - wire [31:0] execute_PC; - wire [31:0] execute_RS1; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_33_; - wire _zz_34_; - wire decode_RS2_USE; - wire decode_RS1_USE; - wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] _zz_35_; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_36_; - wire _zz_37_; - wire [31:0] _zz_38_; - wire [31:0] _zz_39_; - wire execute_SRC_LESS_UNSIGNED; - wire execute_SRC2_FORCE_ZERO; - wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_40_; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_41_; - wire [31:0] _zz_42_; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_43_; - wire [31:0] _zz_44_; - wire decode_SRC_USE_SUB_LESS; - wire decode_SRC_ADD_ZERO; - wire _zz_45_; - wire [31:0] execute_SRC_ADD_SUB; - wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_46_; - wire [31:0] _zz_47_; - wire [31:0] execute_SRC2; - wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_48_; - wire [31:0] _zz_49_; - wire _zz_50_; - reg _zz_51_; - wire [31:0] _zz_52_; - wire [31:0] _zz_53_; - wire [31:0] decode_INSTRUCTION_ANTICIPATED; - reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; - wire decode_INSTRUCTION_READY; - wire _zz_54_; - wire _zz_55_; - wire _zz_56_; - wire _zz_57_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_58_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_59_; - wire _zz_60_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_61_; - wire _zz_62_; - wire _zz_63_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_64_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_65_; - wire _zz_66_; - wire `AluCtrlEnum_defaultEncoding_type _zz_67_; - wire _zz_68_; - wire _zz_69_; - wire _zz_70_; - wire _zz_71_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_72_; - wire _zz_73_; - wire writeBack_MEMORY_STORE; - reg [31:0] _zz_74_; - wire writeBack_MEMORY_ENABLE; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP_physicalAddress; - wire memory_MMU_RSP_isIoAccess; - wire memory_MMU_RSP_allowRead; - wire memory_MMU_RSP_allowWrite; - wire memory_MMU_RSP_allowExecute; - wire memory_MMU_RSP_exception; - wire memory_MMU_RSP_refilling; - wire [31:0] memory_PC; - wire memory_ALIGNEMENT_FAULT; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_STORE; - wire memory_MEMORY_ENABLE; - wire [31:0] _zz_75_; - wire [31:0] _zz_76_; - wire _zz_77_; - wire _zz_78_; - wire _zz_79_; - wire _zz_80_; - wire _zz_81_; - wire _zz_82_; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP_physicalAddress; - wire execute_MMU_RSP_isIoAccess; - wire execute_MMU_RSP_allowRead; - wire execute_MMU_RSP_allowWrite; - wire execute_MMU_RSP_allowExecute; - wire execute_MMU_RSP_exception; - wire execute_MMU_RSP_refilling; - wire _zz_83_; - wire [31:0] execute_SRC_ADD; - wire [1:0] _zz_84_; - wire [31:0] execute_RS2; - wire [31:0] execute_INSTRUCTION; - wire execute_MEMORY_STORE; - wire execute_MEMORY_ENABLE; - wire execute_ALIGNEMENT_FAULT; - wire _zz_85_; - wire decode_MEMORY_ENABLE; - reg [31:0] _zz_86_; - reg [31:0] _zz_87_; - wire [31:0] decode_PC; - wire [31:0] _zz_88_; - wire [31:0] _zz_89_; - wire [31:0] _zz_90_; - wire [31:0] decode_INSTRUCTION; - wire [31:0] _zz_91_; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; - reg decode_arbitration_haltByOther; - reg decode_arbitration_removeIt; - reg decode_arbitration_flushIt; - reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; - wire decode_arbitration_isStuck; - wire decode_arbitration_isStuckByOthers; - wire decode_arbitration_isFlushed; - wire decode_arbitration_isMoving; - wire decode_arbitration_isFiring; - reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; - reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; - reg execute_arbitration_flushNext; - reg execute_arbitration_isValid; - wire execute_arbitration_isStuck; - wire execute_arbitration_isStuckByOthers; - wire execute_arbitration_isFlushed; - wire execute_arbitration_isMoving; - wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - wire writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - wire writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; - wire [31:0] lastStageInstruction /* verilator public */ ; - wire [31:0] lastStagePc /* verilator public */ ; - wire lastStageIsValid /* verilator public */ ; - wire lastStageIsFiring /* verilator public */ ; - reg IBusSimplePlugin_fetcherHalt; - reg IBusSimplePlugin_fetcherflushIt; - reg IBusSimplePlugin_incomingInstruction; - wire IBusSimplePlugin_pcValids_0; - wire IBusSimplePlugin_pcValids_1; - wire IBusSimplePlugin_pcValids_2; - wire IBusSimplePlugin_pcValids_3; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - wire [31:0] iBus_cmd_payload_pc; - wire iBus_rsp_valid; - wire iBus_rsp_payload_error; - wire [31:0] iBus_rsp_payload_inst; - wire IBusSimplePlugin_decodeExceptionPort_valid; - reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; - wire IBusSimplePlugin_mmuBus_cmd_isValid; - wire [31:0] IBusSimplePlugin_mmuBus_cmd_virtualAddress; - wire IBusSimplePlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire IBusSimplePlugin_mmuBus_rsp_allowRead; - wire IBusSimplePlugin_mmuBus_rsp_allowWrite; - wire IBusSimplePlugin_mmuBus_rsp_allowExecute; - wire IBusSimplePlugin_mmuBus_rsp_exception; - wire IBusSimplePlugin_mmuBus_rsp_refilling; - wire IBusSimplePlugin_mmuBus_end; - wire IBusSimplePlugin_mmuBus_busy; - wire IBusSimplePlugin_redoBranch_valid; - wire [31:0] IBusSimplePlugin_redoBranch_payload; - reg DBusSimplePlugin_memoryExceptionPort_valid; - reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; - wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_isValid; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; - wire BranchPlugin_jumpInterface_valid; - wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; - reg CsrPlugin_jumpInterface_valid; - reg [31:0] CsrPlugin_jumpInterface_payload; - wire CsrPlugin_exceptionPendings_0; - wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; - wire externalInterrupt; - wire contextSwitching; - reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; - reg CsrPlugin_selfException_valid; - reg [3:0] CsrPlugin_selfException_payload_code; - wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; - reg IBusSimplePlugin_injectionPort_valid; - reg IBusSimplePlugin_injectionPort_ready; - wire [31:0] IBusSimplePlugin_injectionPort_payload; - wire IBusSimplePlugin_jump_pcLoad_valid; - wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; - wire [3:0] _zz_92_; - wire [3:0] _zz_93_; - wire _zz_94_; - wire _zz_95_; - wire _zz_96_; - wire IBusSimplePlugin_fetchPc_output_valid; - wire IBusSimplePlugin_fetchPc_output_ready; - wire [31:0] IBusSimplePlugin_fetchPc_output_payload; - reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusSimplePlugin_fetchPc_corrected; - reg IBusSimplePlugin_fetchPc_pcRegPropagate; - reg IBusSimplePlugin_fetchPc_booted; - reg IBusSimplePlugin_fetchPc_inc; - reg [31:0] IBusSimplePlugin_fetchPc_pc; - reg IBusSimplePlugin_iBusRsp_stages_0_input_valid; - reg IBusSimplePlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; - wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; - wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; - reg IBusSimplePlugin_iBusRsp_stages_0_halt; - wire IBusSimplePlugin_iBusRsp_stages_0_inputSample; - wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; - wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; - wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; - wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; - wire IBusSimplePlugin_iBusRsp_stages_1_halt; - wire IBusSimplePlugin_iBusRsp_stages_1_inputSample; - wire _zz_97_; - wire _zz_98_; - wire _zz_99_; - wire _zz_100_; - reg _zz_101_; - reg IBusSimplePlugin_iBusRsp_readyForError; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; - wire [31:0] IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; - wire IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; - wire IBusSimplePlugin_injector_decodeInput_valid; - wire IBusSimplePlugin_injector_decodeInput_ready; - wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; - wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; - wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; - reg _zz_102_; - reg [31:0] _zz_103_; - reg _zz_104_; - reg [31:0] _zz_105_; - reg _zz_106_; - reg IBusSimplePlugin_injector_nextPcCalc_valids_0; - reg IBusSimplePlugin_injector_nextPcCalc_valids_1; - reg IBusSimplePlugin_injector_nextPcCalc_valids_2; - reg IBusSimplePlugin_injector_nextPcCalc_valids_3; - reg IBusSimplePlugin_injector_nextPcCalc_valids_4; - reg IBusSimplePlugin_injector_decodeRemoved; - reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; - reg IBusSimplePlugin_cmd_valid; - wire IBusSimplePlugin_cmd_ready; - wire [31:0] IBusSimplePlugin_cmd_payload_pc; - reg [2:0] IBusSimplePlugin_pendingCmd; - wire [2:0] IBusSimplePlugin_pendingCmdNext; - reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; - reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; - reg IBusSimplePlugin_mmu_joinCtx_allowRead; - reg IBusSimplePlugin_mmu_joinCtx_allowWrite; - reg IBusSimplePlugin_mmu_joinCtx_allowExecute; - reg IBusSimplePlugin_mmu_joinCtx_exception; - reg IBusSimplePlugin_mmu_joinCtx_refilling; - reg [2:0] IBusSimplePlugin_rspJoin_discardCounter; - wire IBusSimplePlugin_rspJoin_rspBufferOutput_valid; - wire IBusSimplePlugin_rspJoin_rspBufferOutput_ready; - wire IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; - wire [31:0] IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; - wire iBus_rsp_takeWhen_valid; - wire iBus_rsp_takeWhen_payload_error; - wire [31:0] iBus_rsp_takeWhen_payload_inst; - wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; - reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; - wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; - wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; - wire IBusSimplePlugin_rspJoin_join_valid; - wire IBusSimplePlugin_rspJoin_join_ready; - wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; - wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; - wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; - wire IBusSimplePlugin_rspJoin_join_payload_isRvc; - reg IBusSimplePlugin_rspJoin_exceptionDetected; - reg IBusSimplePlugin_rspJoin_redoRequired; - wire _zz_107_; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [1:0] dBus_cmd_payload_size; - wire dBus_rsp_ready; - wire dBus_rsp_error; - wire [31:0] dBus_rsp_data; - wire _zz_108_; - reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_109_; - reg [3:0] _zz_110_; - wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_111_; - reg [31:0] _zz_112_; - wire _zz_113_; - reg [31:0] _zz_114_; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [26:0] _zz_115_; - wire _zz_116_; - wire _zz_117_; - wire _zz_118_; - wire _zz_119_; - wire `BranchCtrlEnum_defaultEncoding_type _zz_120_; - wire `AluCtrlEnum_defaultEncoding_type _zz_121_; - wire `Src1CtrlEnum_defaultEncoding_type _zz_122_; - wire `EnvCtrlEnum_defaultEncoding_type _zz_123_; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_124_; - wire `Src2CtrlEnum_defaultEncoding_type _zz_125_; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_126_; - wire [4:0] decode_RegFilePlugin_regFileReadAddress1; - wire [4:0] decode_RegFilePlugin_regFileReadAddress2; - wire [31:0] decode_RegFilePlugin_rs1Data; - wire [31:0] decode_RegFilePlugin_rs2Data; - reg lastStageRegFileWrite_valid /* verilator public */ ; - wire [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; - wire [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_127_; - reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_128_; - reg [31:0] _zz_129_; - wire _zz_130_; - reg [19:0] _zz_131_; - wire _zz_132_; - reg [19:0] _zz_133_; - reg [31:0] _zz_134_; - reg [31:0] execute_SrcPlugin_addSub; - wire execute_SrcPlugin_less; - reg execute_LightShifterPlugin_isActive; - wire execute_LightShifterPlugin_isShift; - reg [4:0] execute_LightShifterPlugin_amplitudeReg; - wire [4:0] execute_LightShifterPlugin_amplitude; - wire [31:0] execute_LightShifterPlugin_shiftInput; - wire execute_LightShifterPlugin_done; - reg [31:0] _zz_135_; - reg _zz_136_; - reg _zz_137_; - wire _zz_138_; - reg _zz_139_; - reg [4:0] _zz_140_; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_141_; - reg _zz_142_; - reg _zz_143_; - wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_144_; - reg [10:0] _zz_145_; - wire _zz_146_; - reg [19:0] _zz_147_; - wire _zz_148_; - reg [18:0] _zz_149_; - reg [31:0] _zz_150_; - wire [31:0] execute_BranchPlugin_branch_src2; - wire [31:0] execute_BranchPlugin_branchAdder; - wire [1:0] CsrPlugin_misa_base; - wire [25:0] CsrPlugin_misa_extensions; - reg [1:0] CsrPlugin_mtvec_mode; - reg [29:0] CsrPlugin_mtvec_base; - reg [31:0] CsrPlugin_mepc; - reg CsrPlugin_mstatus_MIE; - reg CsrPlugin_mstatus_MPIE; - reg [1:0] CsrPlugin_mstatus_MPP; - reg CsrPlugin_mip_MEIP; - reg CsrPlugin_mip_MTIP; - reg CsrPlugin_mip_MSIP; - reg CsrPlugin_mie_MEIE; - reg CsrPlugin_mie_MTIE; - reg CsrPlugin_mie_MSIE; - reg CsrPlugin_mcause_interrupt; - reg [3:0] CsrPlugin_mcause_exceptionCode; - reg [31:0] CsrPlugin_mtval; - reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; - reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_151_; - wire _zz_152_; - wire _zz_153_; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; - reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; - wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_154_; - wire _zz_155_; - wire [1:0] _zz_156_; - wire _zz_157_; - reg CsrPlugin_interrupt_valid; - reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; - reg [1:0] CsrPlugin_interrupt_targetPrivilege; - wire CsrPlugin_exception; - wire CsrPlugin_lastStageWasWfi; - reg CsrPlugin_pipelineLiberator_done; - wire CsrPlugin_interruptJump /* verilator public */ ; - reg CsrPlugin_hadException; - reg [1:0] CsrPlugin_targetPrivilege; - reg [3:0] CsrPlugin_trapCause; - reg [1:0] CsrPlugin_xtvec_mode; - reg [29:0] CsrPlugin_xtvec_base; - wire execute_CsrPlugin_inWfi /* verilator public */ ; - reg execute_CsrPlugin_wfiWake; - wire execute_CsrPlugin_blockedBySideEffects; - reg execute_CsrPlugin_illegalAccess; - reg execute_CsrPlugin_illegalInstruction; - reg [31:0] execute_CsrPlugin_readData; - wire execute_CsrPlugin_writeInstruction; - wire execute_CsrPlugin_readInstruction; - wire execute_CsrPlugin_writeEnable; - wire execute_CsrPlugin_readEnable; - wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; - wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_158_; - wire [31:0] _zz_159_; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_160_; - reg DebugPlugin_resetIt_regNext; - reg decode_to_execute_SRC_LESS_UNSIGNED; - reg [31:0] decode_to_execute_RS2; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; - reg decode_to_execute_SRC_USE_SUB_LESS; - reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; - reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_SRC2_FORCE_ZERO; - reg decode_to_execute_CSR_WRITE_OPCODE; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_MMU_FAULT; - reg execute_to_memory_ALIGNEMENT_FAULT; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; - reg decode_to_execute_MEMORY_STORE; - reg execute_to_memory_MEMORY_STORE; - reg memory_to_writeBack_MEMORY_STORE; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg decode_to_execute_CSR_READ_OPCODE; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg execute_to_memory_BRANCH_DO; - reg [31:0] decode_to_execute_RS1; - reg [31:0] execute_to_memory_MMU_RSP_physicalAddress; - reg execute_to_memory_MMU_RSP_isIoAccess; - reg execute_to_memory_MMU_RSP_allowRead; - reg execute_to_memory_MMU_RSP_allowWrite; - reg execute_to_memory_MMU_RSP_allowExecute; - reg execute_to_memory_MMU_RSP_exception; - reg execute_to_memory_MMU_RSP_refilling; - reg decode_to_execute_IS_CSR; - reg decode_to_execute_DO_EBREAK; - reg [2:0] _zz_161_; - wire iBus_cmd_m2sPipe_valid; - wire iBus_cmd_m2sPipe_ready; - wire [31:0] iBus_cmd_m2sPipe_payload_pc; - reg _zz_162_; - reg [31:0] _zz_163_; - wire dBus_cmd_halfPipe_valid; - wire dBus_cmd_halfPipe_ready; - wire dBus_cmd_halfPipe_payload_wr; - wire [31:0] dBus_cmd_halfPipe_payload_address; - wire [31:0] dBus_cmd_halfPipe_payload_data; - wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_164_; + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBusWishbone_CYC, + output iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_122; + wire _zz_123; + reg [31:0] _zz_124; + reg [31:0] _zz_125; + reg [31:0] _zz_126; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_127; + wire _zz_128; + wire _zz_129; + wire _zz_130; + wire _zz_131; + wire _zz_132; + wire _zz_133; + wire _zz_134; + wire _zz_135; + wire [1:0] _zz_136; + wire _zz_137; + wire _zz_138; + wire _zz_139; + wire _zz_140; + wire _zz_141; + wire _zz_142; + wire _zz_143; + wire _zz_144; + wire _zz_145; + wire _zz_146; + wire _zz_147; + wire [5:0] _zz_148; + wire _zz_149; + wire _zz_150; + wire _zz_151; + wire _zz_152; + wire _zz_153; + wire _zz_154; + wire [1:0] _zz_155; + wire _zz_156; + wire [0:0] _zz_157; + wire [0:0] _zz_158; + wire [0:0] _zz_159; + wire [0:0] _zz_160; + wire [0:0] _zz_161; + wire [0:0] _zz_162; + wire [0:0] _zz_163; + wire [0:0] _zz_164; + wire [0:0] _zz_165; + wire [0:0] _zz_166; + wire [0:0] _zz_167; + wire [0:0] _zz_168; + wire [2:0] _zz_169; + wire [2:0] _zz_170; + wire [31:0] _zz_171; + wire [2:0] _zz_172; + wire [0:0] _zz_173; + wire [2:0] _zz_174; + wire [0:0] _zz_175; + wire [2:0] _zz_176; + wire [0:0] _zz_177; + wire [2:0] _zz_178; + wire [0:0] _zz_179; + wire [2:0] _zz_180; + wire [2:0] _zz_181; + wire [0:0] _zz_182; + wire [2:0] _zz_183; + wire [4:0] _zz_184; + wire [11:0] _zz_185; + wire [11:0] _zz_186; + wire [31:0] _zz_187; + wire [31:0] _zz_188; + wire [31:0] _zz_189; + wire [31:0] _zz_190; + wire [31:0] _zz_191; + wire [31:0] _zz_192; + wire [31:0] _zz_193; + wire [31:0] _zz_194; + wire [32:0] _zz_195; + wire [19:0] _zz_196; + wire [11:0] _zz_197; + wire [11:0] _zz_198; + wire [1:0] _zz_199; + wire [1:0] _zz_200; + wire [1:0] _zz_201; + wire [1:0] _zz_202; + wire [0:0] _zz_203; + wire [0:0] _zz_204; + wire [0:0] _zz_205; + wire [0:0] _zz_206; + wire [0:0] _zz_207; + wire [0:0] _zz_208; + wire _zz_209; + wire _zz_210; + wire [1:0] _zz_211; + wire [31:0] _zz_212; + wire [31:0] _zz_213; + wire [31:0] _zz_214; + wire _zz_215; + wire [0:0] _zz_216; + wire [12:0] _zz_217; + wire [31:0] _zz_218; + wire [31:0] _zz_219; + wire [31:0] _zz_220; + wire _zz_221; + wire [0:0] _zz_222; + wire [6:0] _zz_223; + wire [31:0] _zz_224; + wire [31:0] _zz_225; + wire [31:0] _zz_226; + wire _zz_227; + wire [0:0] _zz_228; + wire [0:0] _zz_229; + wire [31:0] _zz_230; + wire [31:0] _zz_231; + wire [31:0] _zz_232; + wire _zz_233; + wire [1:0] _zz_234; + wire [1:0] _zz_235; + wire _zz_236; + wire [0:0] _zz_237; + wire [20:0] _zz_238; + wire [31:0] _zz_239; + wire [31:0] _zz_240; + wire [31:0] _zz_241; + wire [31:0] _zz_242; + wire _zz_243; + wire _zz_244; + wire [0:0] _zz_245; + wire [0:0] _zz_246; + wire _zz_247; + wire [0:0] _zz_248; + wire [17:0] _zz_249; + wire [31:0] _zz_250; + wire _zz_251; + wire _zz_252; + wire [0:0] _zz_253; + wire [0:0] _zz_254; + wire [0:0] _zz_255; + wire [0:0] _zz_256; + wire _zz_257; + wire [0:0] _zz_258; + wire [14:0] _zz_259; + wire [31:0] _zz_260; + wire [31:0] _zz_261; + wire [31:0] _zz_262; + wire [31:0] _zz_263; + wire [31:0] _zz_264; + wire [0:0] _zz_265; + wire [0:0] _zz_266; + wire [1:0] _zz_267; + wire [1:0] _zz_268; + wire _zz_269; + wire [0:0] _zz_270; + wire [11:0] _zz_271; + wire [31:0] _zz_272; + wire [31:0] _zz_273; + wire [31:0] _zz_274; + wire [31:0] _zz_275; + wire [31:0] _zz_276; + wire [31:0] _zz_277; + wire _zz_278; + wire [0:0] _zz_279; + wire [0:0] _zz_280; + wire _zz_281; + wire [0:0] _zz_282; + wire [0:0] _zz_283; + wire _zz_284; + wire [0:0] _zz_285; + wire [8:0] _zz_286; + wire [31:0] _zz_287; + wire [31:0] _zz_288; + wire [31:0] _zz_289; + wire [0:0] _zz_290; + wire [4:0] _zz_291; + wire [1:0] _zz_292; + wire [1:0] _zz_293; + wire _zz_294; + wire [0:0] _zz_295; + wire [5:0] _zz_296; + wire [31:0] _zz_297; + wire [31:0] _zz_298; + wire _zz_299; + wire [0:0] _zz_300; + wire [1:0] _zz_301; + wire [31:0] _zz_302; + wire [31:0] _zz_303; + wire _zz_304; + wire [0:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire _zz_309; + wire [0:0] _zz_310; + wire [2:0] _zz_311; + wire [31:0] _zz_312; + wire _zz_313; + wire _zz_314; + wire [31:0] _zz_315; + wire [31:0] _zz_316; + wire [31:0] _zz_317; + wire [31:0] _zz_318; + wire [31:0] _zz_319; + wire [31:0] _zz_320; + wire [31:0] _zz_321; + wire [0:0] _zz_322; + wire [2:0] _zz_323; + wire [0:0] _zz_324; + wire [0:0] _zz_325; + wire _zz_326; + wire [0:0] _zz_327; + wire [0:0] _zz_328; + wire [31:0] _zz_329; + wire [31:0] _zz_330; + wire [31:0] _zz_331; + wire _zz_332; + wire _zz_333; + wire [31:0] _zz_334; + wire _zz_335; + wire [0:0] _zz_336; + wire [0:0] _zz_337; + wire [0:0] _zz_338; + wire [0:0] _zz_339; + wire [0:0] _zz_340; + wire [0:0] _zz_341; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire [31:0] decode_RS2; + wire [31:0] decode_RS1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `BranchCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_17; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_26; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_29; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] _zz_30; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_31; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_32; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_33; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_34; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_36; + wire [31:0] _zz_37; + wire _zz_38; + reg _zz_39; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_40; + wire `BranchCtrlEnum_defaultEncoding_type _zz_41; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_42; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; + wire `Src2CtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_defaultEncoding_type _zz_45; + wire `Src1CtrlEnum_defaultEncoding_type _zz_46; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_47; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP2_physicalAddress; + wire memory_MMU_RSP2_isIoAccess; + wire memory_MMU_RSP2_isPaging; + wire memory_MMU_RSP2_allowRead; + wire memory_MMU_RSP2_allowWrite; + wire memory_MMU_RSP2_allowExecute; + wire memory_MMU_RSP2_exception; + wire memory_MMU_RSP2_refilling; + wire memory_MMU_RSP2_bypassTranslation; + wire [31:0] memory_PC; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire execute_MMU_FAULT; + wire [31:0] execute_MMU_RSP2_physicalAddress; + wire execute_MMU_RSP2_isIoAccess; + wire execute_MMU_RSP2_isPaging; + wire execute_MMU_RSP2_allowRead; + wire execute_MMU_RSP2_allowWrite; + wire execute_MMU_RSP2_allowExecute; + wire execute_MMU_RSP2_exception; + wire execute_MMU_RSP2_refilling; + wire execute_MMU_RSP2_bypassTranslation; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire decode_MEMORY_ENABLE; + reg [31:0] _zz_48; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusSimplePlugin_fetcherHalt; + reg IBusSimplePlugin_incomingInstruction; + wire IBusSimplePlugin_pcValids_0; + wire IBusSimplePlugin_pcValids_1; + wire IBusSimplePlugin_pcValids_2; + wire IBusSimplePlugin_pcValids_3; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + wire [31:0] iBus_cmd_payload_pc; + wire iBus_rsp_valid; + wire iBus_rsp_payload_error; + wire [31:0] iBus_rsp_payload_inst; + wire IBusSimplePlugin_decodeExceptionPort_valid; + reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; + wire IBusSimplePlugin_mmuBus_cmd_0_isValid; + wire IBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire IBusSimplePlugin_mmuBus_rsp_isPaging; + wire IBusSimplePlugin_mmuBus_rsp_allowRead; + wire IBusSimplePlugin_mmuBus_rsp_allowWrite; + wire IBusSimplePlugin_mmuBus_rsp_allowExecute; + wire IBusSimplePlugin_mmuBus_rsp_exception; + wire IBusSimplePlugin_mmuBus_rsp_refilling; + wire IBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire IBusSimplePlugin_mmuBus_end; + wire IBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire DBusSimplePlugin_mmuBus_cmd_0_isValid; + wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire DBusSimplePlugin_mmuBus_rsp_isPaging; + wire DBusSimplePlugin_mmuBus_rsp_allowRead; + wire DBusSimplePlugin_mmuBus_rsp_allowWrite; + wire DBusSimplePlugin_mmuBus_rsp_allowExecute; + wire DBusSimplePlugin_mmuBus_rsp_exception; + wire DBusSimplePlugin_mmuBus_rsp_refilling; + wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire DBusSimplePlugin_mmuBus_end; + wire DBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_redoBranch_valid; + wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg IBusSimplePlugin_injectionPort_valid; + reg IBusSimplePlugin_injectionPort_ready; + wire [31:0] IBusSimplePlugin_injectionPort_payload; + wire IBusSimplePlugin_externalFlush; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire [2:0] _zz_49; + wire [2:0] _zz_50; + wire _zz_51; + wire _zz_52; + wire IBusSimplePlugin_fetchPc_output_valid; + wire IBusSimplePlugin_fetchPc_output_ready; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusSimplePlugin_fetchPc_correction; + reg IBusSimplePlugin_fetchPc_correctionReg; + wire IBusSimplePlugin_fetchPc_corrected; + reg IBusSimplePlugin_fetchPc_pcRegPropagate; + reg IBusSimplePlugin_fetchPc_booted; + reg IBusSimplePlugin_fetchPc_inc; + reg [31:0] IBusSimplePlugin_fetchPc_pc; + wire IBusSimplePlugin_fetchPc_redo_valid; + wire [31:0] IBusSimplePlugin_fetchPc_redo_payload; + reg IBusSimplePlugin_fetchPc_flushed; + reg IBusSimplePlugin_iBusRsp_redoFetch; + wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + reg IBusSimplePlugin_iBusRsp_stages_0_halt; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_halt; + wire _zz_53; + wire _zz_54; + wire IBusSimplePlugin_iBusRsp_flush; + wire _zz_55; + wire _zz_56; + reg _zz_57; + reg IBusSimplePlugin_iBusRsp_readyForError; + wire IBusSimplePlugin_iBusRsp_output_valid; + wire IBusSimplePlugin_iBusRsp_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; + wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; + wire IBusSimplePlugin_injector_decodeInput_valid; + wire IBusSimplePlugin_injector_decodeInput_ready; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; + wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; + reg _zz_58; + reg [31:0] _zz_59; + reg _zz_60; + reg [31:0] _zz_61; + reg _zz_62; + reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; + reg IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_ready; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + wire IBusSimplePlugin_pending_inc; + wire IBusSimplePlugin_pending_dec; + reg [2:0] IBusSimplePlugin_pending_value; + wire [2:0] IBusSimplePlugin_pending_next; + wire IBusSimplePlugin_cmdFork_canEmit; + reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; + reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; + reg IBusSimplePlugin_mmu_joinCtx_isPaging; + reg IBusSimplePlugin_mmu_joinCtx_allowRead; + reg IBusSimplePlugin_mmu_joinCtx_allowWrite; + reg IBusSimplePlugin_mmu_joinCtx_allowExecute; + reg IBusSimplePlugin_mmu_joinCtx_exception; + reg IBusSimplePlugin_mmu_joinCtx_refilling; + reg IBusSimplePlugin_mmu_joinCtx_bypassTranslation; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_join_ready; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_payload_isRvc; + reg IBusSimplePlugin_rspJoin_exceptionDetected; + wire _zz_63; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire _zz_64; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_65; + reg [3:0] _zz_66; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_67; + reg [31:0] _zz_68; + wire _zz_69; + reg [31:0] _zz_70; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [26:0] _zz_71; + wire _zz_72; + wire _zz_73; + wire _zz_74; + wire _zz_75; + wire `Src1CtrlEnum_defaultEncoding_type _zz_76; + wire `AluCtrlEnum_defaultEncoding_type _zz_77; + wire `Src2CtrlEnum_defaultEncoding_type _zz_78; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_79; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_80; + wire `BranchCtrlEnum_defaultEncoding_type _zz_81; + wire `EnvCtrlEnum_defaultEncoding_type _zz_82; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_83; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_84; + reg [31:0] _zz_85; + wire _zz_86; + reg [19:0] _zz_87; + wire _zz_88; + reg [19:0] _zz_89; + reg [31:0] _zz_90; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_91; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_92; + reg _zz_93; + reg _zz_94; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_95; + reg [10:0] _zz_96; + wire _zz_97; + reg [19:0] _zz_98; + wire _zz_99; + reg [18:0] _zz_100; + reg [31:0] _zz_101; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_102; + wire _zz_103; + wire _zz_104; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_105; + wire _zz_106; + wire [1:0] _zz_107; + wire _zz_108; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_109; + wire [31:0] _zz_110; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_111; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; + reg execute_to_memory_MMU_RSP2_isIoAccess; + reg execute_to_memory_MMU_RSP2_isPaging; + reg execute_to_memory_MMU_RSP2_allowRead; + reg execute_to_memory_MMU_RSP2_allowWrite; + reg execute_to_memory_MMU_RSP2_allowExecute; + reg execute_to_memory_MMU_RSP2_exception; + reg execute_to_memory_MMU_RSP2_refilling; + reg execute_to_memory_MMU_RSP2_bypassTranslation; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg [2:0] _zz_112; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_113; + reg [31:0] _zz_114; + reg [31:0] _zz_115; + reg [31:0] _zz_116; + reg [31:0] _zz_117; + reg [31:0] _zz_118; + reg [31:0] _zz_119; + reg [31:0] _zz_120; + wire iBus_cmd_m2sPipe_valid; + wire iBus_cmd_m2sPipe_ready; + wire [31:0] iBus_cmd_m2sPipe_payload_pc; + reg iBus_cmd_m2sPipe_rValid; + reg [31:0] iBus_cmd_m2sPipe_rData_pc; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_121; `ifndef SYNTHESIS - reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_1__string; - reg [39:0] _zz_2__string; - reg [39:0] _zz_3__string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_4__string; - reg [95:0] _zz_5__string; - reg [95:0] _zz_6__string; - reg [39:0] _zz_7__string; - reg [39:0] _zz_8__string; - reg [39:0] _zz_9__string; - reg [39:0] _zz_10__string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_11__string; - reg [39:0] _zz_12__string; - reg [39:0] _zz_13__string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [31:0] _zz_10_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_14__string; - reg [71:0] _zz_15__string; - reg [71:0] _zz_16__string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_17__string; - reg [63:0] _zz_18__string; - reg [63:0] _zz_19__string; + reg [71:0] _zz_11_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_14_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_20__string; - reg [23:0] _zz_21__string; - reg [23:0] _zz_22__string; - reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_23__string; - reg [31:0] _zz_24__string; - reg [31:0] _zz_25__string; + reg [23:0] _zz_17_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_20_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_23_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27__string; + reg [39:0] _zz_26_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28__string; + reg [39:0] _zz_27_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_31__string; + reg [39:0] _zz_28_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_33__string; + reg [31:0] _zz_29_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_36__string; + reg [71:0] _zz_31_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_41__string; + reg [23:0] _zz_33_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_43__string; + reg [95:0] _zz_34_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_46__string; + reg [63:0] _zz_35_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_48__string; - reg [39:0] _zz_58__string; - reg [23:0] _zz_59__string; - reg [71:0] _zz_61__string; - reg [39:0] _zz_64__string; - reg [95:0] _zz_65__string; - reg [63:0] _zz_67__string; - reg [31:0] _zz_72__string; - reg [31:0] _zz_120__string; - reg [63:0] _zz_121__string; - reg [95:0] _zz_122__string; - reg [39:0] _zz_123__string; - reg [71:0] _zz_124__string; - reg [23:0] _zz_125__string; - reg [39:0] _zz_126__string; - reg [31:0] decode_to_execute_BRANCH_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] _zz_36_string; + reg [39:0] _zz_40_string; + reg [31:0] _zz_41_string; + reg [71:0] _zz_42_string; + reg [39:0] _zz_43_string; + reg [23:0] _zz_44_string; + reg [63:0] _zz_45_string; + reg [95:0] _zz_46_string; + reg [95:0] _zz_76_string; + reg [63:0] _zz_77_string; + reg [23:0] _zz_78_string; + reg [39:0] _zz_79_string; + reg [71:0] _zz_80_string; + reg [31:0] _zz_81_string; + reg [39:0] _zz_82_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [39:0] decode_to_execute_ENV_CTRL_string; reg [39:0] execute_to_memory_ENV_CTRL_string; reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; `endif (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_168_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); - assign _zz_169_ = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_170_ = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != (2'b00)); - assign _zz_171_ = (! execute_arbitration_isStuckByOthers); - assign _zz_172_ = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_173_ = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)) == 1'b0); - assign _zz_174_ = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != (2'b00)); - assign _zz_175_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_176_ = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_177_ = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); - assign _zz_178_ = writeBack_INSTRUCTION[29 : 28]; - assign _zz_179_ = (IBusSimplePlugin_mmuBus_rsp_exception || IBusSimplePlugin_mmuBus_rsp_refilling); - assign _zz_180_ = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_181_ = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_182_ = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_183_ = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_184_ = (1'b1 || (! 1'b1)); - assign _zz_185_ = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_186_ = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_187_ = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_188_ = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_189_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_190_ = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_191_ = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))); - assign _zz_192_ = ((_zz_151_ && 1'b1) && (! 1'b0)); - assign _zz_193_ = ((_zz_152_ && 1'b1) && (! 1'b0)); - assign _zz_194_ = ((_zz_153_ && 1'b1) && (! 1'b0)); - assign _zz_195_ = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_196_ = writeBack_INSTRUCTION[13 : 12]; - assign _zz_197_ = execute_INSTRUCTION[13]; - assign _zz_198_ = (_zz_92_ - (4'b0001)); - assign _zz_199_ = {IBusSimplePlugin_fetchPc_inc,(2'b00)}; - assign _zz_200_ = {29'd0, _zz_199_}; - assign _zz_201_ = (IBusSimplePlugin_pendingCmd + _zz_203_); - assign _zz_202_ = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); - assign _zz_203_ = {2'd0, _zz_202_}; - assign _zz_204_ = iBus_rsp_valid; - assign _zz_205_ = {2'd0, _zz_204_}; - assign _zz_206_ = (iBus_rsp_valid && (IBusSimplePlugin_rspJoin_discardCounter != (3'b000))); - assign _zz_207_ = {2'd0, _zz_206_}; - assign _zz_208_ = iBus_rsp_valid; - assign _zz_209_ = {2'd0, _zz_208_}; - assign _zz_210_ = (memory_MEMORY_STORE ? (3'b110) : (3'b100)); - assign _zz_211_ = _zz_115_[2 : 2]; - assign _zz_212_ = _zz_115_[3 : 3]; - assign _zz_213_ = _zz_115_[4 : 4]; - assign _zz_214_ = _zz_115_[5 : 5]; - assign _zz_215_ = _zz_115_[8 : 8]; - assign _zz_216_ = _zz_115_[14 : 14]; - assign _zz_217_ = _zz_115_[15 : 15]; - assign _zz_218_ = _zz_115_[18 : 18]; - assign _zz_219_ = _zz_115_[23 : 23]; - assign _zz_220_ = _zz_115_[24 : 24]; - assign _zz_221_ = _zz_115_[25 : 25]; - assign _zz_222_ = _zz_115_[26 : 26]; - assign _zz_223_ = execute_SRC_LESS; - assign _zz_224_ = (3'b100); - assign _zz_225_ = execute_INSTRUCTION[19 : 15]; - assign _zz_226_ = execute_INSTRUCTION[31 : 20]; - assign _zz_227_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_228_ = ($signed(_zz_229_) + $signed(_zz_232_)); - assign _zz_229_ = ($signed(_zz_230_) + $signed(_zz_231_)); - assign _zz_230_ = execute_SRC1; - assign _zz_231_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_232_ = (execute_SRC_USE_SUB_LESS ? _zz_233_ : _zz_234_); - assign _zz_233_ = (32'b00000000000000000000000000000001); - assign _zz_234_ = (32'b00000000000000000000000000000000); - assign _zz_235_ = (_zz_236_ >>> 1); - assign _zz_236_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_237_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_238_ = execute_INSTRUCTION[31 : 20]; - assign _zz_239_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_240_ = (_zz_154_ & (~ _zz_241_)); - assign _zz_241_ = (_zz_154_ - (2'b01)); - assign _zz_242_ = (_zz_156_ & (~ _zz_243_)); - assign _zz_243_ = (_zz_156_ - (2'b01)); - assign _zz_244_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_245_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_246_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_247_ = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_248_ = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_249_ = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_250_ = ({3'd0,_zz_164_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - assign _zz_251_ = 1'b1; - assign _zz_252_ = 1'b1; - assign _zz_253_ = {_zz_96_,_zz_95_}; - assign _zz_254_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); - assign _zz_255_ = (32'b00000000000000000000000000000000); - assign _zz_256_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011000)) == (32'b00000000000000000000000000000000)); - assign _zz_257_ = ((decode_INSTRUCTION & _zz_268_) == (32'b00000000000000000010000000000000)); - assign _zz_258_ = ((decode_INSTRUCTION & _zz_269_) == (32'b00000000000000000001000000000000)); - assign _zz_259_ = (decode_INSTRUCTION & (32'b00000000000000000000000000100000)); - assign _zz_260_ = (32'b00000000000000000000000000100000); - assign _zz_261_ = ((decode_INSTRUCTION & _zz_270_) == (32'b00000000000000000000000001000000)); - assign _zz_262_ = {(_zz_271_ == _zz_272_),(_zz_273_ == _zz_274_)}; - assign _zz_263_ = _zz_118_; - assign _zz_264_ = (1'b0); - assign _zz_265_ = ((_zz_275_ == _zz_276_) != (1'b0)); - assign _zz_266_ = (_zz_277_ != (1'b0)); - assign _zz_267_ = {(_zz_278_ != _zz_279_),{_zz_280_,{_zz_281_,_zz_282_}}}; - assign _zz_268_ = (32'b00000000000000000110000000000100); - assign _zz_269_ = (32'b00000000000000000101000000000100); - assign _zz_270_ = (32'b00000000000000000000000001000100); - assign _zz_271_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010100)); - assign _zz_272_ = (32'b00000000000000000010000000010000); - assign _zz_273_ = (decode_INSTRUCTION & (32'b01000000000000000100000000110100)); - assign _zz_274_ = (32'b01000000000000000000000000110000); - assign _zz_275_ = (decode_INSTRUCTION & (32'b00000000000000000001000000000000)); - assign _zz_276_ = (32'b00000000000000000001000000000000); - assign _zz_277_ = ((decode_INSTRUCTION & (32'b00000000000000000011000000000000)) == (32'b00000000000000000010000000000000)); - assign _zz_278_ = {_zz_119_,(_zz_283_ == _zz_284_)}; - assign _zz_279_ = (2'b00); - assign _zz_280_ = ({_zz_119_,_zz_285_} != (2'b00)); - assign _zz_281_ = ({_zz_286_,_zz_287_} != (2'b00)); - assign _zz_282_ = {(_zz_288_ != _zz_289_),{_zz_290_,{_zz_291_,_zz_292_}}}; - assign _zz_283_ = (decode_INSTRUCTION & (32'b00000000000000000000000001110000)); - assign _zz_284_ = (32'b00000000000000000000000000100000); - assign _zz_285_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000100000)) == (32'b00000000000000000000000000000000)); - assign _zz_286_ = ((decode_INSTRUCTION & _zz_293_) == (32'b00000000000000000001000001010000)); - assign _zz_287_ = ((decode_INSTRUCTION & _zz_294_) == (32'b00000000000000000010000001010000)); - assign _zz_288_ = ((decode_INSTRUCTION & _zz_295_) == (32'b00000000000000000101000000010000)); - assign _zz_289_ = (1'b0); - assign _zz_290_ = ({_zz_296_,_zz_297_} != (2'b00)); - assign _zz_291_ = ({_zz_298_,_zz_299_} != (6'b000000)); - assign _zz_292_ = {(_zz_300_ != _zz_301_),{_zz_302_,{_zz_303_,_zz_304_}}}; - assign _zz_293_ = (32'b00000000000000000001000001010000); - assign _zz_294_ = (32'b00000000000000000010000001010000); - assign _zz_295_ = (32'b00000000000000000111000001010100); - assign _zz_296_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); - assign _zz_297_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); - assign _zz_298_ = _zz_116_; - assign _zz_299_ = {(_zz_305_ == _zz_306_),{_zz_307_,{_zz_308_,_zz_309_}}}; - assign _zz_300_ = ((decode_INSTRUCTION & _zz_310_) == (32'b00000000000100000000000001010000)); - assign _zz_301_ = (1'b0); - assign _zz_302_ = ((_zz_311_ == _zz_312_) != (1'b0)); - assign _zz_303_ = (_zz_313_ != (1'b0)); - assign _zz_304_ = {(_zz_314_ != _zz_315_),{_zz_316_,{_zz_317_,_zz_318_}}}; - assign _zz_305_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); - assign _zz_306_ = (32'b00000000000000000001000000010000); - assign _zz_307_ = ((decode_INSTRUCTION & (32'b00000000000000000010000000010000)) == (32'b00000000000000000010000000010000)); - assign _zz_308_ = _zz_118_; - assign _zz_309_ = {(_zz_319_ == _zz_320_),(_zz_321_ == _zz_322_)}; - assign _zz_310_ = (32'b00010000000100000011000001010000); - assign _zz_311_ = (decode_INSTRUCTION & (32'b00010000000100000011000001010000)); - assign _zz_312_ = (32'b00000000000000000000000001010000); - assign _zz_313_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); - assign _zz_314_ = {(_zz_323_ == _zz_324_),_zz_117_}; - assign _zz_315_ = (2'b00); - assign _zz_316_ = ({_zz_325_,_zz_117_} != (2'b00)); - assign _zz_317_ = ({_zz_326_,_zz_327_} != (3'b000)); - assign _zz_318_ = {(_zz_328_ != _zz_329_),{_zz_330_,{_zz_331_,_zz_332_}}}; - assign _zz_319_ = (decode_INSTRUCTION & (32'b00000000000000000000000000001100)); - assign _zz_320_ = (32'b00000000000000000000000000000100); - assign _zz_321_ = (decode_INSTRUCTION & (32'b00000000000000000000000000101000)); - assign _zz_322_ = (32'b00000000000000000000000000000000); - assign _zz_323_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010100)); - assign _zz_324_ = (32'b00000000000000000000000000000100); - assign _zz_325_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001000100)) == (32'b00000000000000000000000000000100)); - assign _zz_326_ = ((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000000000001000000)); - assign _zz_327_ = {(_zz_334_ == _zz_335_),(_zz_336_ == _zz_337_)}; - assign _zz_328_ = {(_zz_338_ == _zz_339_),(_zz_340_ == _zz_341_)}; - assign _zz_329_ = (2'b00); - assign _zz_330_ = ({_zz_342_,_zz_343_} != (2'b00)); - assign _zz_331_ = (_zz_344_ != (1'b0)); - assign _zz_332_ = {(_zz_345_ != _zz_346_),{_zz_347_,{_zz_348_,_zz_349_}}}; - assign _zz_333_ = (32'b00000000000000000000000001010000); - assign _zz_334_ = (decode_INSTRUCTION & (32'b00000000000000000000000000111000)); - assign _zz_335_ = (32'b00000000000000000000000000000000); - assign _zz_336_ = (decode_INSTRUCTION & (32'b00000000000100000011000001000000)); - assign _zz_337_ = (32'b00000000000000000000000001000000); - assign _zz_338_ = (decode_INSTRUCTION & (32'b00000000000000000010000000010000)); - assign _zz_339_ = (32'b00000000000000000010000000000000); - assign _zz_340_ = (decode_INSTRUCTION & (32'b00000000000000000101000000000000)); - assign _zz_341_ = (32'b00000000000000000001000000000000); - assign _zz_342_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000110000000010000)); - assign _zz_343_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000010100)) == (32'b00000000000000000100000000010000)); - assign _zz_344_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000010100)) == (32'b00000000000000000010000000010000)); - assign _zz_345_ = {(_zz_350_ == _zz_351_),(_zz_352_ == _zz_353_)}; - assign _zz_346_ = (2'b00); - assign _zz_347_ = ((_zz_354_ == _zz_355_) != (1'b0)); - assign _zz_348_ = (_zz_356_ != (1'b0)); - assign _zz_349_ = {(_zz_357_ != _zz_358_),{_zz_359_,_zz_360_}}; - assign _zz_350_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); - assign _zz_351_ = (32'b00000000000000000000000000100100); - assign _zz_352_ = (decode_INSTRUCTION & (32'b00000000000000000011000001010100)); - assign _zz_353_ = (32'b00000000000000000001000000010000); - assign _zz_354_ = (decode_INSTRUCTION & (32'b00000000000000000000000000010000)); - assign _zz_355_ = (32'b00000000000000000000000000010000); - assign _zz_356_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000000000000)); - assign _zz_357_ = {((decode_INSTRUCTION & (32'b00000000000000000000000000110100)) == (32'b00000000000000000000000000100000)),((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100000))}; - assign _zz_358_ = (2'b00); - assign _zz_359_ = ({_zz_116_,((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100))} != (2'b00)); - assign _zz_360_ = (((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)) != (1'b0)); - assign _zz_361_ = (32'b00000000000000000001000001111111); - assign _zz_362_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); - assign _zz_363_ = (32'b00000000000000000010000001110011); - assign _zz_364_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); - assign _zz_365_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); - assign _zz_366_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_367_) == (32'b00000000000000000000000000000011)),{(_zz_368_ == _zz_369_),{_zz_370_,{_zz_371_,_zz_372_}}}}}}; - assign _zz_367_ = (32'b00000000000000000101000001011111); - assign _zz_368_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); - assign _zz_369_ = (32'b00000000000000000000000001100011); - assign _zz_370_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); - assign _zz_371_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); - assign _zz_372_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_373_) == (32'b00000000000000000101000000110011)),{(_zz_374_ == _zz_375_),{_zz_376_,{_zz_377_,_zz_378_}}}}}}; - assign _zz_373_ = (32'b10111110000000000111000001111111); - assign _zz_374_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); - assign _zz_375_ = (32'b00000000000000000000000000110011); - assign _zz_376_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); - assign _zz_377_ = ((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)); - assign _zz_378_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); + + assign _zz_127 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_128 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_129 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_130 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_131 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_132 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_133 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_134 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_135 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); + assign _zz_136 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_137 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); + assign _zz_138 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_139 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_140 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_141 = (1'b1 || (! 1'b1)); + assign _zz_142 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_143 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_144 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_145 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_146 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_147 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_148 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_149 = (! execute_arbitration_isStuckByOthers); + assign _zz_150 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_151 = ((_zz_102 && 1'b1) && (! 1'b0)); + assign _zz_152 = ((_zz_103 && 1'b1) && (! 1'b0)); + assign _zz_153 = ((_zz_104 && 1'b1) && (! 1'b0)); + assign _zz_154 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_155 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_156 = execute_INSTRUCTION[13]; + assign _zz_157 = _zz_71[23 : 23]; + assign _zz_158 = _zz_71[15 : 15]; + assign _zz_159 = _zz_71[12 : 12]; + assign _zz_160 = _zz_71[11 : 11]; + assign _zz_161 = _zz_71[10 : 10]; + assign _zz_162 = _zz_71[26 : 26]; + assign _zz_163 = _zz_71[14 : 14]; + assign _zz_164 = _zz_71[4 : 4]; + assign _zz_165 = _zz_71[2 : 2]; + assign _zz_166 = _zz_71[18 : 18]; + assign _zz_167 = _zz_71[9 : 9]; + assign _zz_168 = _zz_71[3 : 3]; + assign _zz_169 = (_zz_49 - 3'b001); + assign _zz_170 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_171 = {29'd0, _zz_170}; + assign _zz_172 = (IBusSimplePlugin_pending_value + _zz_174); + assign _zz_173 = IBusSimplePlugin_pending_inc; + assign _zz_174 = {2'd0, _zz_173}; + assign _zz_175 = IBusSimplePlugin_pending_dec; + assign _zz_176 = {2'd0, _zz_175}; + assign _zz_177 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_178 = {2'd0, _zz_177}; + assign _zz_179 = IBusSimplePlugin_pending_dec; + assign _zz_180 = {2'd0, _zz_179}; + assign _zz_181 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_182 = execute_SRC_LESS; + assign _zz_183 = 3'b100; + assign _zz_184 = execute_INSTRUCTION[19 : 15]; + assign _zz_185 = execute_INSTRUCTION[31 : 20]; + assign _zz_186 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_187 = ($signed(_zz_188) + $signed(_zz_191)); + assign _zz_188 = ($signed(_zz_189) + $signed(_zz_190)); + assign _zz_189 = execute_SRC1; + assign _zz_190 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_191 = (execute_SRC_USE_SUB_LESS ? _zz_192 : _zz_193); + assign _zz_192 = 32'h00000001; + assign _zz_193 = 32'h0; + assign _zz_194 = (_zz_195 >>> 1); + assign _zz_195 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_196 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_197 = execute_INSTRUCTION[31 : 20]; + assign _zz_198 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_199 = (_zz_105 & (~ _zz_200)); + assign _zz_200 = (_zz_105 - 2'b01); + assign _zz_201 = (_zz_107 & (~ _zz_202)); + assign _zz_202 = (_zz_107 - 2'b01); + assign _zz_203 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_204 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_205 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_206 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_207 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_208 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_209 = 1'b1; + assign _zz_210 = 1'b1; + assign _zz_211 = {_zz_52,_zz_51}; + assign _zz_212 = 32'h0000107f; + assign _zz_213 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_214 = 32'h00002073; + assign _zz_215 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_216 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_217 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_218) == 32'h00000003),{(_zz_219 == _zz_220),{_zz_221,{_zz_222,_zz_223}}}}}}; + assign _zz_218 = 32'h0000505f; + assign _zz_219 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_220 = 32'h00000063; + assign _zz_221 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_222 = ((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033); + assign _zz_223 = {((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013),{((decode_INSTRUCTION & _zz_224) == 32'h00005033),{(_zz_225 == _zz_226),{_zz_227,{_zz_228,_zz_229}}}}}}; + assign _zz_224 = 32'hbe00707f; + assign _zz_225 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_226 = 32'h00000033; + assign _zz_227 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_228 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_229 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_230 = 32'h10103050; + assign _zz_231 = (decode_INSTRUCTION & 32'h10103050); + assign _zz_232 = 32'h00000050; + assign _zz_233 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz_234 = {(_zz_239 == _zz_240),(_zz_241 == _zz_242)}; + assign _zz_235 = 2'b00; + assign _zz_236 = ({_zz_75,_zz_243} != 2'b00); + assign _zz_237 = (_zz_244 != 1'b0); + assign _zz_238 = {(_zz_245 != _zz_246),{_zz_247,{_zz_248,_zz_249}}}; + assign _zz_239 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_240 = 32'h00001050; + assign _zz_241 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_242 = 32'h00002050; + assign _zz_243 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_244 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_245 = ((decode_INSTRUCTION & _zz_250) == 32'h00005010); + assign _zz_246 = 1'b0; + assign _zz_247 = ({_zz_251,_zz_252} != 2'b00); + assign _zz_248 = ({_zz_253,_zz_254} != 2'b00); + assign _zz_249 = {(_zz_255 != _zz_256),{_zz_257,{_zz_258,_zz_259}}}; + assign _zz_250 = 32'h00007054; + assign _zz_251 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_252 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00001010); + assign _zz_253 = ((decode_INSTRUCTION & _zz_260) == 32'h00000024); + assign _zz_254 = ((decode_INSTRUCTION & _zz_261) == 32'h00001010); + assign _zz_255 = ((decode_INSTRUCTION & _zz_262) == 32'h00001000); + assign _zz_256 = 1'b0; + assign _zz_257 = ((_zz_263 == _zz_264) != 1'b0); + assign _zz_258 = ({_zz_265,_zz_266} != 2'b00); + assign _zz_259 = {(_zz_267 != _zz_268),{_zz_269,{_zz_270,_zz_271}}}; + assign _zz_260 = 32'h00000064; + assign _zz_261 = 32'h00003054; + assign _zz_262 = 32'h00001000; + assign _zz_263 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_264 = 32'h00002000; + assign _zz_265 = ((decode_INSTRUCTION & _zz_272) == 32'h00002000); + assign _zz_266 = ((decode_INSTRUCTION & _zz_273) == 32'h00001000); + assign _zz_267 = {(_zz_274 == _zz_275),(_zz_276 == _zz_277)}; + assign _zz_268 = 2'b00; + assign _zz_269 = ({_zz_278,{_zz_279,_zz_280}} != 3'b000); + assign _zz_270 = (_zz_281 != 1'b0); + assign _zz_271 = {(_zz_282 != _zz_283),{_zz_284,{_zz_285,_zz_286}}}; + assign _zz_272 = 32'h00002010; + assign _zz_273 = 32'h00005000; + assign _zz_274 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_275 = 32'h00000020; + assign _zz_276 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_277 = 32'h00000020; + assign _zz_278 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_279 = ((decode_INSTRUCTION & _zz_287) == 32'h0); + assign _zz_280 = ((decode_INSTRUCTION & _zz_288) == 32'h00000040); + assign _zz_281 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_282 = ((decode_INSTRUCTION & _zz_289) == 32'h00000010); + assign _zz_283 = 1'b0; + assign _zz_284 = (_zz_74 != 1'b0); + assign _zz_285 = ({_zz_290,_zz_291} != 6'h0); + assign _zz_286 = {(_zz_292 != _zz_293),{_zz_294,{_zz_295,_zz_296}}}; + assign _zz_287 = 32'h00000038; + assign _zz_288 = 32'h00103040; + assign _zz_289 = 32'h00000010; + assign _zz_290 = _zz_75; + assign _zz_291 = {(_zz_297 == _zz_298),{_zz_299,{_zz_300,_zz_301}}}; + assign _zz_292 = {_zz_73,(_zz_302 == _zz_303)}; + assign _zz_293 = 2'b00; + assign _zz_294 = ({_zz_73,_zz_304} != 2'b00); + assign _zz_295 = ({_zz_305,_zz_306} != 2'b00); + assign _zz_296 = {(_zz_307 != _zz_308),{_zz_309,{_zz_310,_zz_311}}}; + assign _zz_297 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_298 = 32'h00001010; + assign _zz_299 = ((decode_INSTRUCTION & _zz_312) == 32'h00002010); + assign _zz_300 = _zz_74; + assign _zz_301 = {_zz_313,_zz_314}; + assign _zz_302 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_303 = 32'h00000020; + assign _zz_304 = ((decode_INSTRUCTION & _zz_315) == 32'h0); + assign _zz_305 = (_zz_316 == _zz_317); + assign _zz_306 = (_zz_318 == _zz_319); + assign _zz_307 = (_zz_320 == _zz_321); + assign _zz_308 = 1'b0; + assign _zz_309 = ({_zz_322,_zz_323} != 4'b0000); + assign _zz_310 = (_zz_324 != _zz_325); + assign _zz_311 = {_zz_326,{_zz_327,_zz_328}}; + assign _zz_312 = 32'h00002010; + assign _zz_313 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_314 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_315 = 32'h00000020; + assign _zz_316 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_317 = 32'h00006010; + assign _zz_318 = (decode_INSTRUCTION & 32'h00005014); + assign _zz_319 = 32'h00004010; + assign _zz_320 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_321 = 32'h00002010; + assign _zz_322 = ((decode_INSTRUCTION & _zz_329) == 32'h0); + assign _zz_323 = {(_zz_330 == _zz_331),{_zz_332,_zz_333}}; + assign _zz_324 = ((decode_INSTRUCTION & _zz_334) == 32'h0); + assign _zz_325 = 1'b0; + assign _zz_326 = ({_zz_335,{_zz_336,_zz_337}} != 3'b000); + assign _zz_327 = ({_zz_338,_zz_339} != 2'b00); + assign _zz_328 = ({_zz_340,_zz_341} != 2'b00); + assign _zz_329 = 32'h00000044; + assign _zz_330 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_331 = 32'h0; + assign _zz_332 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_333 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_334 = 32'h00000058; + assign _zz_335 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_336 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_337 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz_338 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_339 = _zz_72; + assign _zz_340 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_341 = _zz_72; always @ (posedge clk) begin - if(_zz_51_) begin - RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + if(_zz_209) begin + _zz_124 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_251_) begin - _zz_165_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_210) begin + _zz_125 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_252_) begin - _zz_166_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( - .io_push_valid(iBus_rsp_takeWhen_valid), - .io_push_ready(IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready), - .io_push_payload_error(iBus_rsp_takeWhen_payload_error), - .io_push_payload_inst(iBus_rsp_takeWhen_payload_inst), - .io_pop_valid(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid), - .io_pop_ready(IBusSimplePlugin_rspJoin_rspBufferOutput_ready), - .io_pop_payload_error(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error), - .io_pop_payload_inst(IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst), - .io_flush(IBusSimplePlugin_fetcherflushIt), - .io_occupancy(IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy), - .clk(clk), - .reset(reset) + if(_zz_39) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid (iBus_rsp_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_payload_error ), //i + .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (_zz_122 ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o + .io_flush (_zz_123 ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_253_) + case(_zz_211) 2'b00 : begin - _zz_167_ = CsrPlugin_jumpInterface_payload; + _zz_126 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_167_ = DBusSimplePlugin_redoBranch_payload; - end - 2'b10 : begin - _zz_167_ = BranchPlugin_jumpInterface_payload; + _zz_126 = DBusSimplePlugin_redoBranch_payload; end default : begin - _zz_167_ = IBusSimplePlugin_redoBranch_payload; + _zz_126 = BranchPlugin_jumpInterface_payload; end endcase end `ifndef SYNTHESIS always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; endcase end always @(*) begin - case(_zz_1_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_1__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_1__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_1__string = "AND_1"; - default : _zz_1__string = "?????"; - endcase - end - always @(*) begin - case(_zz_2_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_2__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_2__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_2__string = "AND_1"; - default : _zz_2__string = "?????"; - endcase - end - always @(*) begin - case(_zz_3_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_3__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_3__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_3__string = "AND_1"; - default : _zz_3__string = "?????"; - endcase - end - always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; endcase end always @(*) begin - case(_zz_4_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_4__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_4__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_4__string = "URS1 "; - default : _zz_4__string = "????????????"; + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; endcase end always @(*) begin - case(_zz_5_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_5__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_5__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_5__string = "URS1 "; - default : _zz_5__string = "????????????"; + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; endcase end always @(*) begin - case(_zz_6_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_6__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_6__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_6__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_6__string = "URS1 "; - default : _zz_6__string = "????????????"; - endcase - end - always @(*) begin - case(_zz_7_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7__string = "ECALL"; - default : _zz_7__string = "?????"; + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_8_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8__string = "ECALL"; - default : _zz_8__string = "?????"; + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; endcase end always @(*) begin - case(_zz_9_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9__string = "ECALL"; - default : _zz_9__string = "?????"; + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; endcase end always @(*) begin - case(_zz_10_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10__string = "ECALL"; - default : _zz_10__string = "?????"; + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; endcase end always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_11_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_11__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_11__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_11__string = "ECALL"; - default : _zz_11__string = "?????"; + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; endcase end always @(*) begin - case(_zz_12_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_12__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_12__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_12__string = "ECALL"; - default : _zz_12__string = "?????"; + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; endcase end always @(*) begin - case(_zz_13_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_13__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_13__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_13__string = "ECALL"; - default : _zz_13__string = "?????"; + case(_zz_10) + `BranchCtrlEnum_defaultEncoding_INC : _zz_10_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_10_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_10_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_10_string = "JALR"; + default : _zz_10_string = "????"; endcase end always @(*) begin @@ -1545,62 +1394,62 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_14_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14__string = "SRA_1 "; - default : _zz_14__string = "?????????"; + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; endcase end always @(*) begin - case(_zz_15_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15__string = "SRA_1 "; - default : _zz_15__string = "?????????"; + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; endcase end always @(*) begin - case(_zz_16_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16__string = "SRA_1 "; - default : _zz_16__string = "?????????"; + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17__string = "BITWISE "; - default : _zz_17__string = "????????"; + case(_zz_14) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; + default : _zz_14_string = "?????"; endcase end always @(*) begin - case(_zz_18_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18__string = "BITWISE "; - default : _zz_18__string = "????????"; + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; endcase end always @(*) begin - case(_zz_19_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19__string = "BITWISE "; - default : _zz_19__string = "????????"; + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; endcase end always @(*) begin @@ -1613,66 +1462,98 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_20_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20__string = "PC "; - default : _zz_20__string = "???"; + case(_zz_17) + `Src2CtrlEnum_defaultEncoding_RS : _zz_17_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_17_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_17_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_17_string = "PC "; + default : _zz_17_string = "???"; endcase end always @(*) begin - case(_zz_21_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21__string = "PC "; - default : _zz_21__string = "???"; + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; endcase end always @(*) begin - case(_zz_22_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22__string = "PC "; - default : _zz_22__string = "???"; + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; endcase end always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; + default : _zz_20_string = "????????"; + endcase + end + always @(*) begin + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; + endcase + end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_23_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_23__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_23__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_23__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_23__string = "JALR"; - default : _zz_23__string = "????"; + case(_zz_23) + `Src1CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_23_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_23_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_23_string = "URS1 "; + default : _zz_23_string = "????????????"; endcase end always @(*) begin - case(_zz_24_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_24__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_24__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_24__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_24__string = "JALR"; - default : _zz_24__string = "????"; + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; endcase end always @(*) begin - case(_zz_25_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_25__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_25__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_25__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_25__string = "JALR"; - default : _zz_25__string = "????"; + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; endcase end always @(*) begin @@ -1684,11 +1565,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_27_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27__string = "ECALL"; - default : _zz_27__string = "?????"; + case(_zz_26) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_26_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_26_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26_string = "ECALL"; + default : _zz_26_string = "?????"; endcase end always @(*) begin @@ -1700,11 +1581,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_28_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28__string = "ECALL"; - default : _zz_28__string = "?????"; + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; endcase end always @(*) begin @@ -1716,11 +1597,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_31_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_31__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_31__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_31__string = "ECALL"; - default : _zz_31__string = "?????"; + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; endcase end always @(*) begin @@ -1733,12 +1614,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_33_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_33__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_33__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_33__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_33__string = "JALR"; - default : _zz_33__string = "????"; + case(_zz_29) + `BranchCtrlEnum_defaultEncoding_INC : _zz_29_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_29_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_29_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_29_string = "JALR"; + default : _zz_29_string = "????"; endcase end always @(*) begin @@ -1751,12 +1632,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_36_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_36__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_36__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_36__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_36__string = "SRA_1 "; - default : _zz_36__string = "?????????"; + case(_zz_31) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_31_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_31_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_31_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_31_string = "SRA_1 "; + default : _zz_31_string = "?????????"; endcase end always @(*) begin @@ -1769,12 +1650,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_41_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_41__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_41__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_41__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_41__string = "PC "; - default : _zz_41__string = "???"; + case(_zz_33) + `Src2CtrlEnum_defaultEncoding_RS : _zz_33_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_33_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_33_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_33_string = "PC "; + default : _zz_33_string = "???"; endcase end always @(*) begin @@ -1787,12 +1668,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_43_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_43__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_43__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43__string = "URS1 "; - default : _zz_43__string = "????????????"; + case(_zz_34) + `Src1CtrlEnum_defaultEncoding_RS : _zz_34_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_34_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34_string = "URS1 "; + default : _zz_34_string = "????????????"; endcase end always @(*) begin @@ -1804,11 +1685,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_46_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_46__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_46__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_46__string = "BITWISE "; - default : _zz_46__string = "????????"; + case(_zz_35) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_35_string = "BITWISE "; + default : _zz_35_string = "????????"; endcase end always @(*) begin @@ -1820,140 +1701,148 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_48_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_48__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_48__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_48__string = "AND_1"; - default : _zz_48__string = "?????"; + case(_zz_36) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_36_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_36_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_36_string = "AND_1"; + default : _zz_36_string = "?????"; endcase end always @(*) begin - case(_zz_58_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_58__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_58__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_58__string = "AND_1"; - default : _zz_58__string = "?????"; + case(_zz_40) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_40_string = "ECALL"; + default : _zz_40_string = "?????"; endcase end always @(*) begin - case(_zz_59_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_59__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_59__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_59__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_59__string = "PC "; - default : _zz_59__string = "???"; + case(_zz_41) + `BranchCtrlEnum_defaultEncoding_INC : _zz_41_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_41_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_41_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_41_string = "JALR"; + default : _zz_41_string = "????"; endcase end always @(*) begin - case(_zz_61_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_61__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_61__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_61__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_61__string = "SRA_1 "; - default : _zz_61__string = "?????????"; + case(_zz_42) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_42_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_42_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_42_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_42_string = "SRA_1 "; + default : _zz_42_string = "?????????"; endcase end always @(*) begin - case(_zz_64_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_64__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_64__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_64__string = "ECALL"; - default : _zz_64__string = "?????"; + case(_zz_43) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_65_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_65__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_65__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_65__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_65__string = "URS1 "; - default : _zz_65__string = "????????????"; + case(_zz_44) + `Src2CtrlEnum_defaultEncoding_RS : _zz_44_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_44_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_44_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_44_string = "PC "; + default : _zz_44_string = "???"; endcase end always @(*) begin - case(_zz_67_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_67__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_67__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_67__string = "BITWISE "; - default : _zz_67__string = "????????"; + case(_zz_45) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; + default : _zz_45_string = "????????"; endcase end always @(*) begin - case(_zz_72_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_72__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_72__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_72__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_72__string = "JALR"; - default : _zz_72__string = "????"; + case(_zz_46) + `Src1CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_46_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_46_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_46_string = "URS1 "; + default : _zz_46_string = "????????????"; endcase end always @(*) begin - case(_zz_120_) - `BranchCtrlEnum_defaultEncoding_INC : _zz_120__string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_120__string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_120__string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_120__string = "JALR"; - default : _zz_120__string = "????"; + case(_zz_76) + `Src1CtrlEnum_defaultEncoding_RS : _zz_76_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_76_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_76_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_76_string = "URS1 "; + default : _zz_76_string = "????????????"; endcase end always @(*) begin - case(_zz_121_) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_121__string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_121__string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_121__string = "BITWISE "; - default : _zz_121__string = "????????"; + case(_zz_77) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_77_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_77_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_77_string = "BITWISE "; + default : _zz_77_string = "????????"; endcase end always @(*) begin - case(_zz_122_) - `Src1CtrlEnum_defaultEncoding_RS : _zz_122__string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_122__string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_122__string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_122__string = "URS1 "; - default : _zz_122__string = "????????????"; + case(_zz_78) + `Src2CtrlEnum_defaultEncoding_RS : _zz_78_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_78_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_78_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_78_string = "PC "; + default : _zz_78_string = "???"; endcase end always @(*) begin - case(_zz_123_) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_123__string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_123__string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_123__string = "ECALL"; - default : _zz_123__string = "?????"; + case(_zz_79) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_79_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_79_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_79_string = "AND_1"; + default : _zz_79_string = "?????"; endcase end always @(*) begin - case(_zz_124_) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_124__string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_124__string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_124__string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_124__string = "SRA_1 "; - default : _zz_124__string = "?????????"; + case(_zz_80) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_80_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_80_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_80_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_80_string = "SRA_1 "; + default : _zz_80_string = "?????????"; endcase end always @(*) begin - case(_zz_125_) - `Src2CtrlEnum_defaultEncoding_RS : _zz_125__string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_125__string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_125__string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_125__string = "PC "; - default : _zz_125__string = "???"; + case(_zz_81) + `BranchCtrlEnum_defaultEncoding_INC : _zz_81_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_81_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_81_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_81_string = "JALR"; + default : _zz_81_string = "????"; endcase end always @(*) begin - case(_zz_126_) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_126__string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_126__string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_126__string = "AND_1"; - default : _zz_126__string = "?????"; + case(_zz_82) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_82_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_82_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_82_string = "ECALL"; + default : _zz_82_string = "?????"; endcase end always @(*) begin - case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; - default : decode_to_execute_BRANCH_CTRL_string = "????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin @@ -1966,11 +1855,11 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin @@ -1982,6 +1871,15 @@ module VexRiscv ( default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end always @(*) begin case(decode_to_execute_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; @@ -2006,79 +1904,62 @@ module VexRiscv ( default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end `endif - assign decode_DO_EBREAK = _zz_26_; - assign decode_IS_CSR = _zz_60_; - assign decode_RS1 = _zz_53_; - assign execute_BRANCH_DO = _zz_34_; + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_94; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_47_; - assign decode_CSR_READ_OPCODE = _zz_29_; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_57_; + assign execute_REGFILE_WRITE_DATA = _zz_84; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_84_; - assign decode_ALU_BITWISE_CTRL = _zz_1_; - assign _zz_2_ = _zz_3_; - assign decode_MEMORY_STORE = _zz_55_; - assign decode_SRC1_CTRL = _zz_4_; - assign _zz_5_ = _zz_6_; - assign execute_BRANCH_CALC = _zz_32_; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_RS2 = decode_RegFilePlugin_rs2Data; + assign decode_RS1 = decode_RegFilePlugin_rs1Data; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_157[0]; + assign decode_BRANCH_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_SHIFT_CTRL = _zz_11; + assign _zz_12 = _zz_13; + assign decode_ALU_BITWISE_CTRL = _zz_14; + assign _zz_15 = _zz_16; + assign decode_SRC_LESS_UNSIGNED = _zz_158[0]; + assign decode_MEMORY_STORE = _zz_159[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_69_; - assign decode_CSR_WRITE_OPCODE = _zz_30_; - assign decode_SRC2_FORCE_ZERO = _zz_45_; - assign _zz_7_ = _zz_8_; - assign _zz_9_ = _zz_10_; - assign decode_ENV_CTRL = _zz_11_; - assign _zz_12_ = _zz_13_; - assign decode_SHIFT_CTRL = _zz_14_; - assign _zz_15_ = _zz_16_; - assign decode_ALU_CTRL = _zz_17_; - assign _zz_18_ = _zz_19_; - assign decode_SRC2_CTRL = _zz_20_; - assign _zz_21_ = _zz_22_; - assign memory_MEMORY_READ_DATA = _zz_75_; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_160[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_161[0]; + assign decode_SRC2_CTRL = _zz_17; + assign _zz_18 = _zz_19; + assign decode_ALU_CTRL = _zz_20; + assign _zz_21 = _zz_22; + assign decode_SRC1_CTRL = _zz_23; + assign _zz_24 = _zz_25; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = _zz_88_; - assign decode_BRANCH_CTRL = _zz_23_; - assign _zz_24_ = _zz_25_; - assign decode_RS2 = _zz_52_; - assign decode_SRC_LESS_UNSIGNED = _zz_66_; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_63_; + assign decode_IS_EBREAK = _zz_162[0]; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27_; - assign execute_ENV_CTRL = _zz_28_; - assign writeBack_ENV_CTRL = _zz_31_; + assign memory_ENV_CTRL = _zz_26; + assign execute_ENV_CTRL = _zz_27; + assign writeBack_ENV_CTRL = _zz_28; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_33_; - assign decode_RS2_USE = _zz_71_; - assign decode_RS1_USE = _zz_54_; + assign execute_BRANCH_CTRL = _zz_29; + assign decode_RS2_USE = _zz_163[0]; + assign decode_RS1_USE = _zz_164[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; @@ -2086,54 +1967,53 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin - _zz_35_ = execute_REGFILE_WRITE_DATA; - if(_zz_168_)begin - _zz_35_ = _zz_135_; + _zz_30 = execute_REGFILE_WRITE_DATA; + if(_zz_127)begin + _zz_30 = _zz_91; end - if(_zz_169_)begin - _zz_35_ = execute_CsrPlugin_readData; + if(_zz_128)begin + _zz_30 = execute_CsrPlugin_readData; end end - assign execute_SHIFT_CTRL = _zz_36_; + assign execute_SHIFT_CTRL = _zz_31; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_40_ = execute_PC; - assign execute_SRC2_CTRL = _zz_41_; - assign execute_SRC1_CTRL = _zz_43_; - assign decode_SRC_USE_SUB_LESS = _zz_56_; - assign decode_SRC_ADD_ZERO = _zz_68_; - assign execute_SRC_ADD_SUB = _zz_39_; - assign execute_SRC_LESS = _zz_37_; - assign execute_ALU_CTRL = _zz_46_; - assign execute_SRC2 = _zz_42_; - assign execute_SRC1 = _zz_44_; - assign execute_ALU_BITWISE_CTRL = _zz_48_; - assign _zz_49_ = writeBack_INSTRUCTION; - assign _zz_50_ = writeBack_REGFILE_WRITE_VALID; + assign _zz_32 = execute_PC; + assign execute_SRC2_CTRL = _zz_33; + assign execute_SRC1_CTRL = _zz_34; + assign decode_SRC_USE_SUB_LESS = _zz_165[0]; + assign decode_SRC_ADD_ZERO = _zz_166[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_35; + assign execute_SRC2 = _zz_90; + assign execute_SRC1 = _zz_85; + assign execute_ALU_BITWISE_CTRL = _zz_36; + assign _zz_37 = writeBack_INSTRUCTION; + assign _zz_38 = writeBack_REGFILE_WRITE_VALID; always @ (*) begin - _zz_51_ = 1'b0; + _zz_39 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_51_ = 1'b1; + _zz_39 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = _zz_91_; + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_62_; - if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = _zz_167[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = _zz_73_; - assign decode_INSTRUCTION_READY = 1'b1; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_212) == 32'h00001073),{(_zz_213 == _zz_214),{_zz_215,{_zz_216,_zz_217}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin - _zz_74_ = writeBack_REGFILE_WRITE_DATA; + _zz_47 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_74_ = writeBack_DBusSimplePlugin_rspFormated; + _zz_47 = writeBack_DBusSimplePlugin_rspFormated; end end @@ -2141,52 +2021,49 @@ module VexRiscv ( assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP_physicalAddress = execute_to_memory_MMU_RSP_physicalAddress; - assign memory_MMU_RSP_isIoAccess = execute_to_memory_MMU_RSP_isIoAccess; - assign memory_MMU_RSP_allowRead = execute_to_memory_MMU_RSP_allowRead; - assign memory_MMU_RSP_allowWrite = execute_to_memory_MMU_RSP_allowWrite; - assign memory_MMU_RSP_allowExecute = execute_to_memory_MMU_RSP_allowExecute; - assign memory_MMU_RSP_exception = execute_to_memory_MMU_RSP_exception; - assign memory_MMU_RSP_refilling = execute_to_memory_MMU_RSP_refilling; + assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; + assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; + assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; + assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; + assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; + assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; + assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; + assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; + assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; assign memory_PC = execute_to_memory_PC; assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = _zz_83_; - assign execute_MMU_RSP_physicalAddress = _zz_76_; - assign execute_MMU_RSP_isIoAccess = _zz_77_; - assign execute_MMU_RSP_allowRead = _zz_78_; - assign execute_MMU_RSP_allowWrite = _zz_79_; - assign execute_MMU_RSP_allowExecute = _zz_80_; - assign execute_MMU_RSP_exception = _zz_81_; - assign execute_MMU_RSP_refilling = _zz_82_; - assign execute_SRC_ADD = _zz_38_; + assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); + assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; + assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; + assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; + assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; + assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; + assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; + assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; + assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_ALIGNEMENT_FAULT = _zz_85_; - assign decode_MEMORY_ENABLE = _zz_70_; + assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); + assign decode_MEMORY_ENABLE = _zz_168[0]; always @ (*) begin - _zz_86_ = memory_FORMAL_PC_NEXT; + _zz_48 = memory_FORMAL_PC_NEXT; if(DBusSimplePlugin_redoBranch_valid)begin - _zz_86_ = DBusSimplePlugin_redoBranch_payload; + _zz_48 = DBusSimplePlugin_redoBranch_payload; end if(BranchPlugin_jumpInterface_valid)begin - _zz_86_ = BranchPlugin_jumpInterface_payload; - end - end - - always @ (*) begin - _zz_87_ = decode_FORMAL_PC_NEXT; - if(IBusSimplePlugin_redoBranch_valid)begin - _zz_87_ = IBusSimplePlugin_redoBranch_payload; + _zz_48 = BranchPlugin_jumpInterface_payload; end end - assign decode_PC = _zz_90_; - assign decode_INSTRUCTION = _zz_89_; + assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin @@ -2194,18 +2071,10 @@ module VexRiscv ( if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_161_) - 3'b000 : begin - end - 3'b001 : begin - end + case(_zz_112) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end - 3'b011 : begin - end - 3'b100 : begin - end default : begin end endcase @@ -2213,20 +2082,20 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_136_ || _zz_137_)))begin + if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin decode_arbitration_haltByOther = 1'b1; end - if((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts))begin - decode_arbitration_haltByOther = decode_arbitration_isValid; + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != (3'b000)))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_170_)begin + if(_zz_129)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2234,36 +2103,25 @@ module VexRiscv ( end end - always @ (*) begin - decode_arbitration_flushIt = 1'b0; - if(IBusSimplePlugin_redoBranch_valid)begin - decode_arbitration_flushIt = 1'b1; - end - end - + assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusSimplePlugin_redoBranch_valid)begin - decode_arbitration_flushNext = 1'b1; - end - if(_zz_170_)begin + if(_zz_129)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_108_)))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_168_)begin - if(_zz_171_)begin - if(! execute_LightShifterPlugin_done) begin - execute_arbitration_haltItself = 1'b1; - end + if(_zz_127)begin + if((! execute_LightShifterPlugin_done))begin + execute_arbitration_haltItself = 1'b1; end end - if(_zz_169_)begin + if(_zz_128)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2272,7 +2130,7 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_172_)begin + if(_zz_130)begin execute_arbitration_haltByOther = 1'b1; end end @@ -2289,8 +2147,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_172_)begin - if(_zz_173_)begin + if(_zz_130)begin + if(_zz_131)begin execute_arbitration_flushIt = 1'b1; end end @@ -2301,8 +2159,8 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_172_)begin - if(_zz_173_)begin + if(_zz_130)begin + if(_zz_131)begin execute_arbitration_flushNext = 1'b1; end end @@ -2318,7 +2176,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_174_)begin + if(_zz_132)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2341,7 +2199,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_174_)begin + if(_zz_132)begin memory_arbitration_flushNext = 1'b1; end end @@ -2358,10 +2216,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_175_)begin + if(_zz_133)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_176_)begin + if(_zz_134)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2372,40 +2230,28 @@ module VexRiscv ( assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusSimplePlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_175_)begin + if(_zz_133)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_176_)begin + if(_zz_134)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_172_)begin - if(_zz_173_)begin + if(_zz_130)begin + if(_zz_131)begin IBusSimplePlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_177_)begin + if(_zz_135)begin IBusSimplePlugin_fetcherHalt = 1'b1; end end - always @ (*) begin - IBusSimplePlugin_fetcherflushIt = 1'b0; - if(({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)))begin - IBusSimplePlugin_fetcherflushIt = 1'b1; - end - if(_zz_172_)begin - if(_zz_173_)begin - IBusSimplePlugin_fetcherflushIt = 1'b1; - end - end - end - always @ (*) begin IBusSimplePlugin_incomingInstruction = 1'b0; if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin @@ -2416,23 +2262,31 @@ module VexRiscv ( end end + assign CsrPlugin_inWfi = 1'b0; + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_175_)begin + if(_zz_133)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_176_)begin + if(_zz_134)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); - if(_zz_175_)begin - CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(_zz_133)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_176_)begin - case(_zz_178_) + if(_zz_134)begin + case(_zz_136) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2463,20 +2317,24 @@ module VexRiscv ( end end - assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusSimplePlugin_redoBranch_valid}}} != (4'b0000)); - assign _zz_92_ = {IBusSimplePlugin_redoBranch_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; - assign _zz_93_ = (_zz_92_ & (~ _zz_198_)); - assign _zz_94_ = _zz_93_[3]; - assign _zz_95_ = (_zz_93_[1] || _zz_94_); - assign _zz_96_ = (_zz_93_[2] || _zz_94_); - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_167_; + assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); + assign _zz_49 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; + assign _zz_50 = (_zz_49 & (~ _zz_169)); + assign _zz_51 = _zz_50[1]; + assign _zz_52 = _zz_50[2]; + assign IBusSimplePlugin_jump_pcLoad_payload = _zz_126; always @ (*) begin - IBusSimplePlugin_fetchPc_corrected = 1'b0; + IBusSimplePlugin_fetchPc_correction = 1'b0; + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end if(IBusSimplePlugin_jump_pcLoad_valid)begin - IBusSimplePlugin_fetchPc_corrected = 1'b1; + IBusSimplePlugin_fetchPc_correction = 1'b1; end end + assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); always @ (*) begin IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin @@ -2485,7 +2343,10 @@ module VexRiscv ( end always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_200_); + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_171); + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; + end if(IBusSimplePlugin_jump_pcLoad_valid)begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; end @@ -2493,47 +2354,59 @@ module VexRiscv ( IBusSimplePlugin_fetchPc_pc[1] = 1'b0; end + always @ (*) begin + IBusSimplePlugin_fetchPc_flushed = 1'b0; + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + end + assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; always @ (*) begin - IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; - if(IBusSimplePlugin_mmuBus_busy)begin - IBusSimplePlugin_iBusRsp_stages_0_input_valid = 1'b0; + IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin + IBusSimplePlugin_iBusRsp_redoFetch = 1'b1; end end + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; - assign IBusSimplePlugin_iBusRsp_stages_0_inputSample = 1'b1; always @ (*) begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmd_valid) || (! IBusSimplePlugin_cmd_ready))))begin + if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; end - if(_zz_179_)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - end - end - - assign _zz_97_ = (! IBusSimplePlugin_iBusRsp_stages_0_halt); - always @ (*) begin - IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_97_); - if(IBusSimplePlugin_mmuBus_busy)begin - IBusSimplePlugin_iBusRsp_stages_0_input_ready = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin + if(IBusSimplePlugin_mmuBus_rsp_refilling)begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; + end + if(IBusSimplePlugin_mmuBus_rsp_exception)begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + end end end - assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_97_); + assign _zz_53 = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_53); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_53); assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; - assign _zz_98_ = (! IBusSimplePlugin_iBusRsp_stages_1_halt); - assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_98_); - assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_98_); + assign _zz_54 = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_54); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_54); assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; - assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_99_; - assign _zz_99_ = ((1'b0 && (! _zz_100_)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); - assign _zz_100_ = _zz_101_; - assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_100_; + assign IBusSimplePlugin_fetchPc_redo_valid = IBusSimplePlugin_iBusRsp_redoFetch; + assign IBusSimplePlugin_fetchPc_redo_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_55; + assign _zz_55 = ((1'b0 && (! _zz_56)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_56 = _zz_57; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_56; assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; always @ (*) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b1; @@ -2545,202 +2418,180 @@ module VexRiscv ( end end - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); - assign IBusSimplePlugin_injector_decodeInput_valid = _zz_102_; - assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_103_; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_104_; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_105_; - assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_106_; - assign _zz_91_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst); + assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_58; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_59; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_60; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_61; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_62; assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); always @ (*) begin - decode_arbitration_isValid = (IBusSimplePlugin_injector_decodeInput_valid && (! IBusSimplePlugin_injector_decodeRemoved)); - case(_zz_161_) - 3'b000 : begin - end - 3'b001 : begin - end + decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; + case(_zz_112) 3'b010 : begin decode_arbitration_isValid = 1'b1; end 3'b011 : begin decode_arbitration_isValid = 1'b1; end - 3'b100 : begin - end default : begin end endcase end - assign _zz_90_ = IBusSimplePlugin_injector_decodeInput_payload_pc; - assign _zz_89_ = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; - assign _zz_88_ = (decode_PC + (32'b00000000000000000000000000000100)); assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pendingCmdNext = (_zz_201_ - _zz_205_); + assign IBusSimplePlugin_pending_next = (_zz_172 - _zz_176); + assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); always @ (*) begin - IBusSimplePlugin_cmd_valid = ((IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) && (IBusSimplePlugin_pendingCmd != (3'b111))); - if(_zz_179_)begin - IBusSimplePlugin_cmd_valid = 1'b0; - end - end - - assign IBusSimplePlugin_mmuBus_cmd_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; - assign IBusSimplePlugin_mmuBus_cmd_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; - assign IBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; - assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_fetcherflushIt); - assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],(2'b00)}; - assign iBus_rsp_takeWhen_valid = (iBus_rsp_valid && (! (IBusSimplePlugin_rspJoin_discardCounter != (3'b000)))); - assign iBus_rsp_takeWhen_payload_error = iBus_rsp_payload_error; - assign iBus_rsp_takeWhen_payload_inst = iBus_rsp_payload_inst; - assign IBusSimplePlugin_rspJoin_rspBufferOutput_valid = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; - assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; - assign IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); + if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin + if(IBusSimplePlugin_mmuBus_rsp_refilling)begin + IBusSimplePlugin_cmd_valid = 1'b0; + end + if(IBusSimplePlugin_mmuBus_rsp_exception)begin + IBusSimplePlugin_cmd_valid = 1'b0; + end + end + end + + assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_mmuBus_cmd_0_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; + assign IBusSimplePlugin_mmuBus_cmd_0_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_externalFlush); + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],2'b00}; + assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign _zz_122 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_122); assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; always @ (*) begin - IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_error; - if((! IBusSimplePlugin_rspJoin_rspBufferOutput_valid))begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; end end - assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBufferOutput_payload_inst; + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; always @ (*) begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_180_)begin + if(_zz_137)begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; end end - always @ (*) begin - IBusSimplePlugin_rspJoin_redoRequired = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin - IBusSimplePlugin_rspJoin_redoRequired = 1'b1; - end - end - - assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBufferOutput_valid); + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); - assign IBusSimplePlugin_rspJoin_rspBufferOutput_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); - assign _zz_107_ = (! (IBusSimplePlugin_rspJoin_exceptionDetected || IBusSimplePlugin_rspJoin_redoRequired)); - assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_inputBeforeStage_ready && _zz_107_); - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_107_); - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; - assign IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; - assign IBusSimplePlugin_redoBranch_valid = (IBusSimplePlugin_rspJoin_redoRequired && IBusSimplePlugin_iBusRsp_readyForError); - assign IBusSimplePlugin_redoBranch_payload = decode_PC; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign _zz_63 = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_63); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_63); + assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; always @ (*) begin - IBusSimplePlugin_decodeExceptionPort_payload_code = (4'bxxxx); - if(_zz_180_)begin - IBusSimplePlugin_decodeExceptionPort_payload_code = (4'b1100); + IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_137)begin + IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; end end - assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],(2'b00)}; + assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],2'b00}; assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError); - assign _zz_108_ = 1'b0; - assign _zz_85_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + assign _zz_64 = 1'b0; always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin execute_DBusSimplePlugin_skipCmd = 1'b1; end - if((execute_MMU_FAULT || execute_MMU_RSP_refilling))begin + if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_108_)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_109_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_65 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_109_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_65 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_109_ = execute_RS2[31 : 0]; + _zz_65 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_109_; - assign _zz_84_ = dBus_cmd_payload_address[1 : 0]; + assign dBus_cmd_payload_data = _zz_65; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_110_ = (4'b0001); + _zz_66 = 4'b0001; end 2'b01 : begin - _zz_110_ = (4'b0011); + _zz_66 = 4'b0011; end default : begin - _zz_110_ = (4'b1111); + _zz_66 = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_110_ <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_bypassTranslation = 1'b0; + assign execute_DBusSimplePlugin_formalMask = (_zz_66 <<< dBus_cmd_payload_address[1 : 0]); + assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; + assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; + assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign _zz_83_ = ((execute_MMU_RSP_exception || ((! execute_MMU_RSP_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP_allowRead) && (! execute_MEMORY_STORE))); - assign _zz_76_ = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign _zz_77_ = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign _zz_78_ = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign _zz_79_ = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign _zz_80_ = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign _zz_81_ = DBusSimplePlugin_mmuBus_rsp_exception; - assign _zz_82_ = DBusSimplePlugin_mmuBus_rsp_refilling; - assign _zz_75_ = dBus_rsp_data; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_181_)begin + if(_zz_138)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end if(memory_ALIGNEMENT_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_MMU_RSP_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end else begin if(memory_MMU_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_182_)begin + if(_zz_139)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); - if(_zz_181_)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (4'b0101); + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; + if(_zz_138)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_210_}; + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_181}; end - if(! memory_MMU_RSP_refilling) begin + if(! memory_MMU_RSP2_refilling) begin if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? (4'b1111) : (4'b1101)); + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); end end end @@ -2748,10 +2599,10 @@ module VexRiscv ( assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; always @ (*) begin DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_182_)begin + if(_zz_139)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -2774,63 +2625,63 @@ module VexRiscv ( endcase end - assign _zz_111_ = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + assign _zz_67 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); always @ (*) begin - _zz_112_[31] = _zz_111_; - _zz_112_[30] = _zz_111_; - _zz_112_[29] = _zz_111_; - _zz_112_[28] = _zz_111_; - _zz_112_[27] = _zz_111_; - _zz_112_[26] = _zz_111_; - _zz_112_[25] = _zz_111_; - _zz_112_[24] = _zz_111_; - _zz_112_[23] = _zz_111_; - _zz_112_[22] = _zz_111_; - _zz_112_[21] = _zz_111_; - _zz_112_[20] = _zz_111_; - _zz_112_[19] = _zz_111_; - _zz_112_[18] = _zz_111_; - _zz_112_[17] = _zz_111_; - _zz_112_[16] = _zz_111_; - _zz_112_[15] = _zz_111_; - _zz_112_[14] = _zz_111_; - _zz_112_[13] = _zz_111_; - _zz_112_[12] = _zz_111_; - _zz_112_[11] = _zz_111_; - _zz_112_[10] = _zz_111_; - _zz_112_[9] = _zz_111_; - _zz_112_[8] = _zz_111_; - _zz_112_[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_113_ = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + _zz_68[31] = _zz_67; + _zz_68[30] = _zz_67; + _zz_68[29] = _zz_67; + _zz_68[28] = _zz_67; + _zz_68[27] = _zz_67; + _zz_68[26] = _zz_67; + _zz_68[25] = _zz_67; + _zz_68[24] = _zz_67; + _zz_68[23] = _zz_67; + _zz_68[22] = _zz_67; + _zz_68[21] = _zz_67; + _zz_68[20] = _zz_67; + _zz_68[19] = _zz_67; + _zz_68[18] = _zz_67; + _zz_68[17] = _zz_67; + _zz_68[16] = _zz_67; + _zz_68[15] = _zz_67; + _zz_68[14] = _zz_67; + _zz_68[13] = _zz_67; + _zz_68[12] = _zz_67; + _zz_68[11] = _zz_67; + _zz_68[10] = _zz_67; + _zz_68[9] = _zz_67; + _zz_68[8] = _zz_67; + _zz_68[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_69 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); always @ (*) begin - _zz_114_[31] = _zz_113_; - _zz_114_[30] = _zz_113_; - _zz_114_[29] = _zz_113_; - _zz_114_[28] = _zz_113_; - _zz_114_[27] = _zz_113_; - _zz_114_[26] = _zz_113_; - _zz_114_[25] = _zz_113_; - _zz_114_[24] = _zz_113_; - _zz_114_[23] = _zz_113_; - _zz_114_[22] = _zz_113_; - _zz_114_[21] = _zz_113_; - _zz_114_[20] = _zz_113_; - _zz_114_[19] = _zz_113_; - _zz_114_[18] = _zz_113_; - _zz_114_[17] = _zz_113_; - _zz_114_[16] = _zz_113_; - _zz_114_[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + _zz_70[31] = _zz_69; + _zz_70[30] = _zz_69; + _zz_70[29] = _zz_69; + _zz_70[28] = _zz_69; + _zz_70[27] = _zz_69; + _zz_70[26] = _zz_69; + _zz_70[25] = _zz_69; + _zz_70[24] = _zz_69; + _zz_70[23] = _zz_69; + _zz_70[22] = _zz_69; + _zz_70[21] = _zz_69; + _zz_70[20] = _zz_69; + _zz_70[19] = _zz_69; + _zz_70[18] = _zz_69; + _zz_70[17] = _zz_69; + _zz_70[16] = _zz_69; + _zz_70[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; end always @ (*) begin - case(_zz_196_) + case(_zz_155) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_112_; + writeBack_DBusSimplePlugin_rspFormated = _zz_68; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_114_; + writeBack_DBusSimplePlugin_rspFormated = _zz_70; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -2838,72 +2689,71 @@ module VexRiscv ( endcase end - assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_virtualAddress; + assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign IBusSimplePlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_virtualAddress; + assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_116_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); - assign _zz_117_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); - assign _zz_118_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); - assign _zz_119_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); - assign _zz_115_ = {({(_zz_254_ == _zz_255_),{_zz_256_,{_zz_257_,_zz_258_}}} != (4'b0000)),{((_zz_259_ == _zz_260_) != (1'b0)),{({_zz_261_,_zz_262_} != (3'b000)),{(_zz_263_ != _zz_264_),{_zz_265_,{_zz_266_,_zz_267_}}}}}}; - assign _zz_73_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_361_) == (32'b00000000000000000001000001110011)),{(_zz_362_ == _zz_363_),{_zz_364_,{_zz_365_,_zz_366_}}}}}}} != (20'b00000000000000000000)); - assign _zz_120_ = _zz_115_[1 : 0]; - assign _zz_72_ = _zz_120_; - assign _zz_71_ = _zz_211_[0]; - assign _zz_70_ = _zz_212_[0]; - assign _zz_69_ = _zz_213_[0]; - assign _zz_68_ = _zz_214_[0]; - assign _zz_121_ = _zz_115_[7 : 6]; - assign _zz_67_ = _zz_121_; - assign _zz_66_ = _zz_215_[0]; - assign _zz_122_ = _zz_115_[11 : 10]; - assign _zz_65_ = _zz_122_; - assign _zz_123_ = _zz_115_[13 : 12]; - assign _zz_64_ = _zz_123_; - assign _zz_63_ = _zz_216_[0]; - assign _zz_62_ = _zz_217_[0]; - assign _zz_124_ = _zz_115_[17 : 16]; - assign _zz_61_ = _zz_124_; - assign _zz_60_ = _zz_218_[0]; - assign _zz_125_ = _zz_115_[20 : 19]; - assign _zz_59_ = _zz_125_; - assign _zz_126_ = _zz_115_[22 : 21]; - assign _zz_58_ = _zz_126_; - assign _zz_57_ = _zz_219_[0]; - assign _zz_56_ = _zz_220_[0]; - assign _zz_55_ = _zz_221_[0]; - assign _zz_54_ = _zz_222_[0]; - assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = (4'b0010); + assign _zz_72 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_73 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_74 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz_75 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_71 = {(((decode_INSTRUCTION & _zz_230) == 32'h00100050) != 1'b0),{((_zz_231 == _zz_232) != 1'b0),{(_zz_233 != 1'b0),{(_zz_234 != _zz_235),{_zz_236,{_zz_237,_zz_238}}}}}}; + assign _zz_76 = _zz_71[1 : 0]; + assign _zz_46 = _zz_76; + assign _zz_77 = _zz_71[6 : 5]; + assign _zz_45 = _zz_77; + assign _zz_78 = _zz_71[8 : 7]; + assign _zz_44 = _zz_78; + assign _zz_79 = _zz_71[17 : 16]; + assign _zz_43 = _zz_79; + assign _zz_80 = _zz_71[20 : 19]; + assign _zz_42 = _zz_80; + assign _zz_81 = _zz_71[22 : 21]; + assign _zz_41 = _zz_81; + assign _zz_82 = _zz_71[25 : 24]; + assign _zz_40 = _zz_82; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_165_; - assign decode_RegFilePlugin_rs2Data = _zz_166_; - assign _zz_53_ = decode_RegFilePlugin_rs1Data; - assign _zz_52_ = decode_RegFilePlugin_rs2Data; + assign decode_RegFilePlugin_rs1Data = _zz_124; + assign decode_RegFilePlugin_rs2Data = _zz_125; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_50_ && writeBack_arbitration_isFiring); - if(_zz_127_)begin + lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); + if(_zz_83)begin lastStageRegFileWrite_valid = 1'b1; end end - assign lastStageRegFileWrite_payload_address = _zz_49_[11 : 7]; - assign lastStageRegFileWrite_payload_data = _zz_74_; + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_37[11 : 7]; + if(_zz_83)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_47; + if(_zz_83)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + always @ (*) begin case(execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin @@ -2921,334 +2771,329 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_128_ = execute_IntAluPlugin_bitwise; + _zz_84 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_128_ = {31'd0, _zz_223_}; + _zz_84 = {31'd0, _zz_182}; end default : begin - _zz_128_ = execute_SRC_ADD_SUB; + _zz_84 = execute_SRC_ADD_SUB; end endcase end - assign _zz_47_ = _zz_128_; - assign _zz_45_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_129_ = execute_RS1; + _zz_85 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_129_ = {29'd0, _zz_224_}; + _zz_85 = {29'd0, _zz_183}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_129_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + _zz_85 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_129_ = {27'd0, _zz_225_}; + _zz_85 = {27'd0, _zz_184}; end endcase end - assign _zz_44_ = _zz_129_; - assign _zz_130_ = _zz_226_[11]; + assign _zz_86 = _zz_185[11]; always @ (*) begin - _zz_131_[19] = _zz_130_; - _zz_131_[18] = _zz_130_; - _zz_131_[17] = _zz_130_; - _zz_131_[16] = _zz_130_; - _zz_131_[15] = _zz_130_; - _zz_131_[14] = _zz_130_; - _zz_131_[13] = _zz_130_; - _zz_131_[12] = _zz_130_; - _zz_131_[11] = _zz_130_; - _zz_131_[10] = _zz_130_; - _zz_131_[9] = _zz_130_; - _zz_131_[8] = _zz_130_; - _zz_131_[7] = _zz_130_; - _zz_131_[6] = _zz_130_; - _zz_131_[5] = _zz_130_; - _zz_131_[4] = _zz_130_; - _zz_131_[3] = _zz_130_; - _zz_131_[2] = _zz_130_; - _zz_131_[1] = _zz_130_; - _zz_131_[0] = _zz_130_; - end - - assign _zz_132_ = _zz_227_[11]; + _zz_87[19] = _zz_86; + _zz_87[18] = _zz_86; + _zz_87[17] = _zz_86; + _zz_87[16] = _zz_86; + _zz_87[15] = _zz_86; + _zz_87[14] = _zz_86; + _zz_87[13] = _zz_86; + _zz_87[12] = _zz_86; + _zz_87[11] = _zz_86; + _zz_87[10] = _zz_86; + _zz_87[9] = _zz_86; + _zz_87[8] = _zz_86; + _zz_87[7] = _zz_86; + _zz_87[6] = _zz_86; + _zz_87[5] = _zz_86; + _zz_87[4] = _zz_86; + _zz_87[3] = _zz_86; + _zz_87[2] = _zz_86; + _zz_87[1] = _zz_86; + _zz_87[0] = _zz_86; + end + + assign _zz_88 = _zz_186[11]; always @ (*) begin - _zz_133_[19] = _zz_132_; - _zz_133_[18] = _zz_132_; - _zz_133_[17] = _zz_132_; - _zz_133_[16] = _zz_132_; - _zz_133_[15] = _zz_132_; - _zz_133_[14] = _zz_132_; - _zz_133_[13] = _zz_132_; - _zz_133_[12] = _zz_132_; - _zz_133_[11] = _zz_132_; - _zz_133_[10] = _zz_132_; - _zz_133_[9] = _zz_132_; - _zz_133_[8] = _zz_132_; - _zz_133_[7] = _zz_132_; - _zz_133_[6] = _zz_132_; - _zz_133_[5] = _zz_132_; - _zz_133_[4] = _zz_132_; - _zz_133_[3] = _zz_132_; - _zz_133_[2] = _zz_132_; - _zz_133_[1] = _zz_132_; - _zz_133_[0] = _zz_132_; + _zz_89[19] = _zz_88; + _zz_89[18] = _zz_88; + _zz_89[17] = _zz_88; + _zz_89[16] = _zz_88; + _zz_89[15] = _zz_88; + _zz_89[14] = _zz_88; + _zz_89[13] = _zz_88; + _zz_89[12] = _zz_88; + _zz_89[11] = _zz_88; + _zz_89[10] = _zz_88; + _zz_89[9] = _zz_88; + _zz_89[8] = _zz_88; + _zz_89[7] = _zz_88; + _zz_89[6] = _zz_88; + _zz_89[5] = _zz_88; + _zz_89[4] = _zz_88; + _zz_89[3] = _zz_88; + _zz_89[2] = _zz_88; + _zz_89[1] = _zz_88; + _zz_89[0] = _zz_88; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_134_ = execute_RS2; + _zz_90 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_134_ = {_zz_131_,execute_INSTRUCTION[31 : 20]}; + _zz_90 = {_zz_87,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_134_ = {_zz_133_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_90 = {_zz_89,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_134_ = _zz_40_; + _zz_90 = _zz_32; end endcase end - assign _zz_42_ = _zz_134_; always @ (*) begin - execute_SrcPlugin_addSub = _zz_228_; + execute_SrcPlugin_addSub = _zz_187; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign _zz_39_ = execute_SrcPlugin_addSub; - assign _zz_38_ = execute_SrcPlugin_addSub; - assign _zz_37_ = execute_SrcPlugin_less; assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); - assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_135_ = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_91 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_135_ = _zz_235_; + _zz_91 = _zz_194; end endcase end always @ (*) begin - _zz_136_ = 1'b0; - if(_zz_139_)begin - if((_zz_140_ == decode_INSTRUCTION[19 : 15]))begin - _zz_136_ = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr0Match)begin + HazardSimplePlugin_src0Hazard = 1'b1; end end - if(_zz_183_)begin - if(_zz_184_)begin + if(_zz_140)begin + if(_zz_141)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_136_ = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_185_)begin - if(_zz_186_)begin + if(_zz_142)begin + if(_zz_143)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_136_ = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_187_)begin - if(_zz_188_)begin + if(_zz_144)begin + if(_zz_145)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_136_ = 1'b1; + HazardSimplePlugin_src0Hazard = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_136_ = 1'b0; + HazardSimplePlugin_src0Hazard = 1'b0; end end always @ (*) begin - _zz_137_ = 1'b0; - if(_zz_139_)begin - if((_zz_140_ == decode_INSTRUCTION[24 : 20]))begin - _zz_137_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid)begin + if(HazardSimplePlugin_addr1Match)begin + HazardSimplePlugin_src1Hazard = 1'b1; end end - if(_zz_183_)begin - if(_zz_184_)begin + if(_zz_140)begin + if(_zz_141)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_137_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_185_)begin - if(_zz_186_)begin + if(_zz_142)begin + if(_zz_143)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_137_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_187_)begin - if(_zz_188_)begin + if(_zz_144)begin + if(_zz_145)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_137_ = 1'b1; + HazardSimplePlugin_src1Hazard = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_137_ = 1'b0; + HazardSimplePlugin_src1Hazard = 1'b0; end end - assign _zz_138_ = (_zz_50_ && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_38 && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_37[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_47; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_141_ = execute_INSTRUCTION[14 : 12]; + assign _zz_92 = execute_INSTRUCTION[14 : 12]; always @ (*) begin - if((_zz_141_ == (3'b000))) begin - _zz_142_ = execute_BranchPlugin_eq; - end else if((_zz_141_ == (3'b001))) begin - _zz_142_ = (! execute_BranchPlugin_eq); - end else if((((_zz_141_ & (3'b101)) == (3'b101)))) begin - _zz_142_ = (! execute_SRC_LESS); + if((_zz_92 == 3'b000)) begin + _zz_93 = execute_BranchPlugin_eq; + end else if((_zz_92 == 3'b001)) begin + _zz_93 = (! execute_BranchPlugin_eq); + end else if((((_zz_92 & 3'b101) == 3'b101))) begin + _zz_93 = (! execute_SRC_LESS); end else begin - _zz_142_ = execute_SRC_LESS; + _zz_93 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_143_ = 1'b0; + _zz_94 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_143_ = 1'b1; + _zz_94 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_143_ = 1'b1; + _zz_94 = 1'b1; end default : begin - _zz_143_ = _zz_142_; + _zz_94 = _zz_93; end endcase end - assign _zz_34_ = _zz_143_; assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_144_ = _zz_237_[19]; + assign _zz_95 = _zz_196[19]; always @ (*) begin - _zz_145_[10] = _zz_144_; - _zz_145_[9] = _zz_144_; - _zz_145_[8] = _zz_144_; - _zz_145_[7] = _zz_144_; - _zz_145_[6] = _zz_144_; - _zz_145_[5] = _zz_144_; - _zz_145_[4] = _zz_144_; - _zz_145_[3] = _zz_144_; - _zz_145_[2] = _zz_144_; - _zz_145_[1] = _zz_144_; - _zz_145_[0] = _zz_144_; - end - - assign _zz_146_ = _zz_238_[11]; + _zz_96[10] = _zz_95; + _zz_96[9] = _zz_95; + _zz_96[8] = _zz_95; + _zz_96[7] = _zz_95; + _zz_96[6] = _zz_95; + _zz_96[5] = _zz_95; + _zz_96[4] = _zz_95; + _zz_96[3] = _zz_95; + _zz_96[2] = _zz_95; + _zz_96[1] = _zz_95; + _zz_96[0] = _zz_95; + end + + assign _zz_97 = _zz_197[11]; always @ (*) begin - _zz_147_[19] = _zz_146_; - _zz_147_[18] = _zz_146_; - _zz_147_[17] = _zz_146_; - _zz_147_[16] = _zz_146_; - _zz_147_[15] = _zz_146_; - _zz_147_[14] = _zz_146_; - _zz_147_[13] = _zz_146_; - _zz_147_[12] = _zz_146_; - _zz_147_[11] = _zz_146_; - _zz_147_[10] = _zz_146_; - _zz_147_[9] = _zz_146_; - _zz_147_[8] = _zz_146_; - _zz_147_[7] = _zz_146_; - _zz_147_[6] = _zz_146_; - _zz_147_[5] = _zz_146_; - _zz_147_[4] = _zz_146_; - _zz_147_[3] = _zz_146_; - _zz_147_[2] = _zz_146_; - _zz_147_[1] = _zz_146_; - _zz_147_[0] = _zz_146_; - end - - assign _zz_148_ = _zz_239_[11]; + _zz_98[19] = _zz_97; + _zz_98[18] = _zz_97; + _zz_98[17] = _zz_97; + _zz_98[16] = _zz_97; + _zz_98[15] = _zz_97; + _zz_98[14] = _zz_97; + _zz_98[13] = _zz_97; + _zz_98[12] = _zz_97; + _zz_98[11] = _zz_97; + _zz_98[10] = _zz_97; + _zz_98[9] = _zz_97; + _zz_98[8] = _zz_97; + _zz_98[7] = _zz_97; + _zz_98[6] = _zz_97; + _zz_98[5] = _zz_97; + _zz_98[4] = _zz_97; + _zz_98[3] = _zz_97; + _zz_98[2] = _zz_97; + _zz_98[1] = _zz_97; + _zz_98[0] = _zz_97; + end + + assign _zz_99 = _zz_198[11]; always @ (*) begin - _zz_149_[18] = _zz_148_; - _zz_149_[17] = _zz_148_; - _zz_149_[16] = _zz_148_; - _zz_149_[15] = _zz_148_; - _zz_149_[14] = _zz_148_; - _zz_149_[13] = _zz_148_; - _zz_149_[12] = _zz_148_; - _zz_149_[11] = _zz_148_; - _zz_149_[10] = _zz_148_; - _zz_149_[9] = _zz_148_; - _zz_149_[8] = _zz_148_; - _zz_149_[7] = _zz_148_; - _zz_149_[6] = _zz_148_; - _zz_149_[5] = _zz_148_; - _zz_149_[4] = _zz_148_; - _zz_149_[3] = _zz_148_; - _zz_149_[2] = _zz_148_; - _zz_149_[1] = _zz_148_; - _zz_149_[0] = _zz_148_; + _zz_100[18] = _zz_99; + _zz_100[17] = _zz_99; + _zz_100[16] = _zz_99; + _zz_100[15] = _zz_99; + _zz_100[14] = _zz_99; + _zz_100[13] = _zz_99; + _zz_100[12] = _zz_99; + _zz_100[11] = _zz_99; + _zz_100[10] = _zz_99; + _zz_100[9] = _zz_99; + _zz_100[8] = _zz_99; + _zz_100[7] = _zz_99; + _zz_100[6] = _zz_99; + _zz_100[5] = _zz_99; + _zz_100[4] = _zz_99; + _zz_100[3] = _zz_99; + _zz_100[2] = _zz_99; + _zz_100[1] = _zz_99; + _zz_100[0] = _zz_99; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_150_ = {{_zz_145_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_101 = {{_zz_96,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_150_ = {_zz_147_,execute_INSTRUCTION[31 : 20]}; + _zz_101 = {_zz_98,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_150_ = {{_zz_149_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_101 = {{_zz_100,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_150_; + assign execute_BranchPlugin_branch_src2 = _zz_101; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign _zz_32_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); - assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; always @ (*) begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin - CsrPlugin_privilege = (2'b11); + CsrPlugin_privilege = 2'b11; end end - assign CsrPlugin_misa_base = (2'b01); - assign CsrPlugin_misa_extensions = (26'b00000000000000000001000010); - assign _zz_151_ = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_152_ = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_153_ = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign _zz_102 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_103 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_104 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_154_ = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; - assign _zz_155_ = _zz_240_[0]; - assign _zz_156_ = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_157_ = _zz_242_[0]; + assign _zz_105 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; + assign _zz_106 = _zz_199[0]; + assign _zz_107 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_108 = _zz_201[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_170_)begin + if(_zz_129)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3268,7 +3113,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_174_)begin + if(_zz_132)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3289,9 +3134,10 @@ module VexRiscv ( assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = ((! ({writeBack_arbitration_isValid,{memory_arbitration_isValid,execute_arbitration_isValid}} != (3'b000))) && IBusSimplePlugin_pcValids_3); - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -3315,7 +3161,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; @@ -3326,7 +3172,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3337,52 +3183,45 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign _zz_30_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); - assign _zz_29_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); - assign execute_CsrPlugin_inWfi = 1'b0; - assign execute_CsrPlugin_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - 12'b001100000000 : begin + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000001 : begin + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001100000101 : begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001101000100 : begin + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000011 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b111111000000 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - 12'b001100000100 : begin + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end - 12'b001101000010 : begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - default : begin - end - endcase - if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + end + if(_zz_146)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3401,20 +3240,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_189_)begin + if(_zz_147)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin - CsrPlugin_selfException_payload_code = (4'bxxxx); - if(_zz_189_)begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_147)begin case(CsrPlugin_privilege) 2'b00 : begin - CsrPlugin_selfException_payload_code = (4'b1000); + CsrPlugin_selfException_payload_code = 4'b1000; end default : begin - CsrPlugin_selfException_payload_code = (4'b1011); + CsrPlugin_selfException_payload_code = 4'b1011; end endcase end @@ -3422,53 +3261,24 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin - execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_158_; - end - 12'b001100000000 : begin - execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; - end - 12'b001101000001 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; - end - 12'b001101000011 : begin - execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; - end - 12'b111111000000 : begin - execute_CsrPlugin_readData[31 : 0] = _zz_159_; - end - 12'b001100000100 : begin - execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; - execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; - execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; - end - 12'b001101000010 : begin - execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; - execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; - end - default : begin - end - endcase + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_146)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end end - assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); - assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_146)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_197_) + case(_zz_156) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3479,15 +3289,13 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign _zz_159_ = (_zz_158_ & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_159_ != (32'b00000000000000000000000000000000)); + assign _zz_110 = (_zz_109 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_110 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_190_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_148) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusSimplePlugin_injectionPort_ready; end @@ -3500,7 +3308,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_160_))begin + if((! _zz_111))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -3512,10 +3320,8 @@ module VexRiscv ( always @ (*) begin IBusSimplePlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_190_) - 6'b000000 : begin - end - 6'b000001 : begin + case(_zz_148) + 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusSimplePlugin_injectionPort_valid = 1'b1; end @@ -3527,37 +3333,37 @@ module VexRiscv ( end assign IBusSimplePlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign _zz_26_ = ((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)); + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_25_ = decode_BRANCH_CTRL; - assign _zz_23_ = _zz_72_; - assign _zz_33_ = decode_to_execute_BRANCH_CTRL; - assign _zz_22_ = decode_SRC2_CTRL; - assign _zz_20_ = _zz_59_; - assign _zz_41_ = decode_to_execute_SRC2_CTRL; - assign _zz_19_ = decode_ALU_CTRL; - assign _zz_17_ = _zz_67_; - assign _zz_46_ = decode_to_execute_ALU_CTRL; - assign _zz_16_ = decode_SHIFT_CTRL; - assign _zz_14_ = _zz_61_; - assign _zz_36_ = decode_to_execute_SHIFT_CTRL; - assign _zz_13_ = decode_ENV_CTRL; - assign _zz_10_ = execute_ENV_CTRL; - assign _zz_8_ = memory_ENV_CTRL; - assign _zz_11_ = _zz_64_; - assign _zz_28_ = decode_to_execute_ENV_CTRL; - assign _zz_27_ = execute_to_memory_ENV_CTRL; - assign _zz_31_ = memory_to_writeBack_ENV_CTRL; - assign _zz_6_ = decode_SRC1_CTRL; - assign _zz_4_ = _zz_65_; - assign _zz_43_ = decode_to_execute_SRC1_CTRL; - assign _zz_3_ = decode_ALU_BITWISE_CTRL; - assign _zz_1_ = _zz_58_; - assign _zz_48_ = decode_to_execute_ALU_BITWISE_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign _zz_25 = decode_SRC1_CTRL; + assign _zz_23 = _zz_46; + assign _zz_34 = decode_to_execute_SRC1_CTRL; + assign _zz_22 = decode_ALU_CTRL; + assign _zz_20 = _zz_45; + assign _zz_35 = decode_to_execute_ALU_CTRL; + assign _zz_19 = decode_SRC2_CTRL; + assign _zz_17 = _zz_44; + assign _zz_33 = decode_to_execute_SRC2_CTRL; + assign _zz_16 = decode_ALU_BITWISE_CTRL; + assign _zz_14 = _zz_43; + assign _zz_36 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_13 = decode_SHIFT_CTRL; + assign _zz_11 = _zz_42; + assign _zz_31 = decode_to_execute_SHIFT_CTRL; + assign _zz_10 = decode_BRANCH_CTRL; + assign _zz_8 = _zz_41; + assign _zz_29 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_40; + assign _zz_27 = decode_to_execute_ENV_CTRL; + assign _zz_26 = execute_to_memory_ENV_CTRL; + assign _zz_28 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); @@ -3576,15 +3382,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusSimplePlugin_injectionPort_ready = 1'b0; - case(_zz_161_) - 3'b000 : begin - end - 3'b001 : begin - end - 3'b010 : begin - end - 3'b011 : begin - end + case(_zz_112) 3'b100 : begin IBusSimplePlugin_injectionPort_ready = 1'b1; end @@ -3593,15 +3391,79 @@ module VexRiscv ( endcase end + always @ (*) begin + _zz_113 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_113[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_113[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_113[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_114 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_114[11 : 11] = CsrPlugin_mip_MEIP; + _zz_114[7 : 7] = CsrPlugin_mip_MTIP; + _zz_114[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_115 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_115[11 : 11] = CsrPlugin_mie_MEIE; + _zz_115[7 : 7] = CsrPlugin_mie_MTIE; + _zz_115[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_116 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_116[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_117 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_117[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_117[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_118 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_118[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_119 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_119[31 : 0] = _zz_109; + end + end + + always @ (*) begin + _zz_120 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_120[31 : 0] = _zz_110; + end + end + + assign execute_CsrPlugin_readData = (((_zz_113 | _zz_114) | (_zz_115 | _zz_116)) | ((_zz_117 | _zz_118) | (_zz_119 | _zz_120))); assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); - assign iBus_cmd_m2sPipe_valid = _zz_162_; - assign iBus_cmd_m2sPipe_payload_pc = _zz_163_; + assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; + assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); - assign iBusWishbone_CTI = (3'b000); - assign iBusWishbone_BTE = (2'b00); - assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_CTI = 3'b000; + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); @@ -3615,26 +3477,26 @@ module VexRiscv ( assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); - assign dBusWishbone_CTI = (3'b000); - assign dBusWishbone_BTE = (2'b00); + assign dBusWishbone_CTI = 3'b000; + assign dBusWishbone_BTE = 2'b00; always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_164_ = (4'b0001); + _zz_121 = 4'b0001; end 2'b01 : begin - _zz_164_ = (4'b0011); + _zz_121 = 4'b0011; end default : begin - _zz_164_ = (4'b1111); + _zz_121 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = _zz_250_[3:0]; + dBusWishbone_SEL = (_zz_121 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin - dBusWishbone_SEL = (4'b1111); + dBusWishbone_SEL = 4'b1111; end end @@ -3646,27 +3508,28 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; + assign _zz_123 = 1'b0; always @ (posedge clk) begin if(reset) begin IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; IBusSimplePlugin_fetchPc_booted <= 1'b0; IBusSimplePlugin_fetchPc_inc <= 1'b0; - _zz_101_ <= 1'b0; - _zz_102_ <= 1'b0; + _zz_57 <= 1'b0; + _zz_58 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusSimplePlugin_injector_decodeRemoved <= 1'b0; - IBusSimplePlugin_pendingCmd <= (3'b000); - IBusSimplePlugin_rspJoin_discardCounter <= (3'b000); - _zz_127_ <= 1'b1; + IBusSimplePlugin_pending_value <= 3'b000; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; + _zz_83 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_139_ <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; - CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mstatus_MPP <= 2'b11; CsrPlugin_mie_MEIE <= 1'b0; CsrPlugin_mie_MTIE <= 1'b0; CsrPlugin_mie_MSIE <= 1'b0; @@ -3675,21 +3538,28 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - _zz_158_ <= (32'b00000000000000000000000000000000); + _zz_109 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_161_ <= (3'b000); - memory_to_writeBack_REGFILE_WRITE_DATA <= (32'b00000000000000000000000000000000); - memory_to_writeBack_INSTRUCTION <= (32'b00000000000000000000000000000000); - _zz_162_ <= 1'b0; + _zz_112 <= 3'b000; + iBus_cmd_m2sPipe_rValid <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin + if(IBusSimplePlugin_fetchPc_correction)begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + end IBusSimplePlugin_fetchPc_booted <= 1'b1; - if((IBusSimplePlugin_fetchPc_corrected || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin @@ -3698,77 +3568,91 @@ module VexRiscv ( if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end - if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetcherflushIt) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; end - if(IBusSimplePlugin_fetcherflushIt)begin - _zz_101_ <= 1'b0; + if(IBusSimplePlugin_iBusRsp_flush)begin + _zz_57 <= 1'b0; end - if(_zz_99_)begin - _zz_101_ <= IBusSimplePlugin_iBusRsp_stages_0_output_valid; + if(_zz_55)begin + _zz_57 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin - _zz_102_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_valid; + if(decode_arbitration_removeIt)begin + _zz_58 <= 1'b0; end - if(IBusSimplePlugin_fetcherflushIt)begin - _zz_102_ <= 1'b0; + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_58 <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; end if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; end if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; end if((! memory_arbitration_isStuck))begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end if((! writeBack_arbitration_isStuck))begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; end - if(IBusSimplePlugin_fetcherflushIt)begin + if(IBusSimplePlugin_fetchPc_flushed)begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(decode_arbitration_removeIt)begin - IBusSimplePlugin_injector_decodeRemoved <= 1'b1; - end - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_injector_decodeRemoved <= 1'b0; - end - IBusSimplePlugin_pendingCmd <= IBusSimplePlugin_pendingCmdNext; - IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_rspJoin_discardCounter - _zz_207_); - if(IBusSimplePlugin_fetcherflushIt)begin - IBusSimplePlugin_rspJoin_discardCounter <= (IBusSimplePlugin_pendingCmd - _zz_209_); - end - _zz_127_ <= 1'b0; - if(_zz_168_)begin - if(_zz_171_)begin + IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_178); + if(IBusSimplePlugin_iBusRsp_flush)begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_180); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + _zz_83 <= 1'b0; + if(_zz_127)begin + if(_zz_149)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -3778,7 +3662,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_139_ <= _zz_138_; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -3800,19 +3684,38 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_191_)begin - if(_zz_192_)begin + if(_zz_150)begin + if(_zz_151)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_193_)begin + if(_zz_152)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_194_)begin + if(_zz_153)begin CsrPlugin_interrupt_valid <= 1'b1; end end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_175_)begin + if(_zz_133)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3823,10 +3726,10 @@ module VexRiscv ( end endcase end - if(_zz_176_)begin - case(_zz_178_) + if(_zz_134)begin + case(_zz_136) 2'b11 : begin - CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; end @@ -3834,13 +3737,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= ({_zz_153_,{_zz_152_,_zz_151_}} != (3'b000)); - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; - end + execute_CsrPlugin_wfiWake <= (({_zz_104,{_zz_103,_zz_102}} != 3'b000) || CsrPlugin_thirdPartyWake); if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -3859,68 +3756,52 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_161_) + case(_zz_112) 3'b000 : begin if(IBusSimplePlugin_injectionPort_valid)begin - _zz_161_ <= (3'b001); + _zz_112 <= 3'b001; end end 3'b001 : begin - _zz_161_ <= (3'b010); + _zz_112 <= 3'b010; end 3'b010 : begin - _zz_161_ <= (3'b011); + _zz_112 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_161_ <= (3'b100); + _zz_112 <= 3'b100; end end 3'b100 : begin - _zz_161_ <= (3'b000); + _zz_112 <= 3'b000; end default : begin end endcase - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158_ <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000000 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_244_[0]; - CsrPlugin_mstatus_MIE <= _zz_245_[0]; - end - end - 12'b001101000001 : begin - end - 12'b001100000101 : begin - end - 12'b001101000100 : begin - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin - end - 12'b001100000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_247_[0]; - CsrPlugin_mie_MTIE <= _zz_248_[0]; - CsrPlugin_mie_MSIE <= _zz_249_[0]; - end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_203[0]; + CsrPlugin_mstatus_MIE <= _zz_204[0]; end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_206[0]; + CsrPlugin_mie_MTIE <= _zz_207[0]; + CsrPlugin_mie_MSIE <= _zz_208[0]; end - default : begin + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_109 <= execute_CsrPlugin_writeData[31 : 0]; end - endcase + end if(iBus_cmd_ready)begin - _zz_162_ <= iBus_cmd_valid; + iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; end - if(_zz_195_)begin + if(_zz_154)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -3931,72 +3812,67 @@ module VexRiscv ( end always @ (posedge clk) begin - if(IBusSimplePlugin_iBusRsp_inputBeforeStage_ready)begin - _zz_103_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_pc; - _zz_104_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_error; - _zz_105_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; - _zz_106_ <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_isRvc; + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_59 <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_60 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_61 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_62 <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; end if(IBusSimplePlugin_injector_decodeInput_ready)begin - IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_inputBeforeStage_payload_rsp_inst; + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; end if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; + IBusSimplePlugin_mmu_joinCtx_isPaging <= IBusSimplePlugin_mmuBus_rsp_isPaging; IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; + IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; end - if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin - $display("ERROR DBusSimplePlugin doesn't allow memory stage stall when read happend"); - end - if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin - $display("ERROR DBusSimplePlugin doesn't allow writeback stage stall when read happend"); - end - if(_zz_168_)begin - if(_zz_171_)begin - execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + if(_zz_127)begin + if(_zz_149)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - if(_zz_138_)begin - _zz_140_ <= _zz_49_[11 : 7]; - end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; - CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); if(writeBack_arbitration_isFiring)begin - CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_170_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_155_ ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_155_ ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_129)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_106 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_106 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_174_)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_157_ ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_157_ ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_132)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_108 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_108 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_191_)begin - if(_zz_192_)begin - CsrPlugin_interrupt_code <= (4'b0111); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_150)begin + if(_zz_151)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_193_)begin - CsrPlugin_interrupt_code <= (4'b0011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_152)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_194_)begin - CsrPlugin_interrupt_code <= (4'b1011); - CsrPlugin_interrupt_targetPrivilege <= (2'b11); + if(_zz_153)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_175_)begin + if(_zz_133)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4012,16 +3888,13 @@ module VexRiscv ( end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + decode_to_execute_PC <= decode_PC; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_24_; + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_32; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; end if((! execute_arbitration_isStuck))begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; @@ -4029,89 +3902,110 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_87_; + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end if((! memory_arbitration_isStuck))begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_86_; + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_48; end if((! execute_arbitration_isStuck))begin - decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + decode_to_execute_SRC1_CTRL <= _zz_24; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_21; end if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; + decode_to_execute_SRC2_CTRL <= _zz_18; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_40_; + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_21_; + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_18_; + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_15_; + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_12_; + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_9_; + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_7_; + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + decode_to_execute_ALU_BITWISE_CTRL <= _zz_15; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + decode_to_execute_SHIFT_CTRL <= _zz_12; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_9; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; end if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_5_; + decode_to_execute_RS1 <= decode_RS1; end if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + decode_to_execute_RS2 <= decode_RS2; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_2_; + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; end if((! memory_arbitration_isStuck))begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; @@ -4119,84 +4013,85 @@ module VexRiscv ( if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; end if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; + execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; + execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; + execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; + execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; + execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; + execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; + execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; + execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + end + if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_30; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((_zz_112 != 3'b000))begin + _zz_61 <= IBusSimplePlugin_injectionPort_payload; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end if((! execute_arbitration_isStuck))begin - decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_35_; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP_physicalAddress <= execute_MMU_RSP_physicalAddress; - execute_to_memory_MMU_RSP_isIoAccess <= execute_MMU_RSP_isIoAccess; - execute_to_memory_MMU_RSP_allowRead <= execute_MMU_RSP_allowRead; - execute_to_memory_MMU_RSP_allowWrite <= execute_MMU_RSP_allowWrite; - execute_to_memory_MMU_RSP_allowExecute <= execute_MMU_RSP_allowExecute; - execute_to_memory_MMU_RSP_exception <= execute_MMU_RSP_exception; - execute_to_memory_MMU_RSP_refilling <= execute_MMU_RSP_refilling; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_CSR <= decode_IS_CSR; + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end if((! execute_arbitration_isStuck))begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((_zz_161_ != (3'b000)))begin - _zz_105_ <= IBusSimplePlugin_injectionPort_payload; + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - case(execute_CsrPlugin_csrAddress) - 12'b101111000000 : begin - end - 12'b001100000000 : begin - end - 12'b001101000001 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; - end - end - 12'b001100000101 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; - end - end - 12'b001101000100 : begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_246_[0]; - end - end - 12'b001101000011 : begin - end - 12'b111111000000 : begin + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_205[0]; end - 12'b001100000100 : begin - end - 12'b001101000010 : begin + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; end - default : begin + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end - endcase + end if(iBus_cmd_ready)begin - _zz_163_ <= iBus_cmd_payload_pc; + iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; end - if(_zz_195_)begin + if(_zz_154)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; @@ -4210,12 +4105,12 @@ module VexRiscv ( DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != (4'b0000)) || IBusSimplePlugin_incomingInstruction); + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusSimplePlugin_incomingInstruction); if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_74_; + DebugPlugin_busReadDataReg <= _zz_47; end - _zz_160_ <= debug_bus_cmd_payload_address[2]; - if(_zz_172_)begin + _zz_111 <= debug_bus_cmd_payload_address[2]; + if(_zz_130)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -4233,8 +4128,8 @@ module VexRiscv ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_190_) - 6'b000000 : begin + case(_zz_148) + 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; if(debug_bus_cmd_payload_data[16])begin @@ -4257,19 +4152,17 @@ module VexRiscv ( end end end - 6'b000001 : begin - end default : begin end endcase end - if(_zz_172_)begin - if(_zz_173_)begin + if(_zz_130)begin + if(_zz_131)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_177_)begin + if(_zz_135)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end @@ -4277,5 +4170,134 @@ module VexRiscv ( end end + endmodule +module StreamFifoLowLatency ( + input io_push_valid, + output io_push_ready, + input io_push_payload_error, + input [31:0] io_push_payload_inst, + output reg io_pop_valid, + input io_pop_ready, + output reg io_pop_payload_error, + output reg [31:0] io_pop_payload_inst, + input io_flush, + output [0:0] io_occupancy, + input clk, + input reset +); + wire _zz_4; + wire [0:0] _zz_5; + reg _zz_1; + reg pushPtr_willIncrement; + reg pushPtr_willClear; + wire pushPtr_willOverflowIfInc; + wire pushPtr_willOverflow; + reg popPtr_willIncrement; + reg popPtr_willClear; + wire popPtr_willOverflowIfInc; + wire popPtr_willOverflow; + wire ptrMatch; + reg risingOccupancy; + wire empty; + wire full; + wire pushing; + wire popping; + wire [32:0] _zz_2; + reg [32:0] _zz_3; + + assign _zz_4 = (! empty); + assign _zz_5 = _zz_2[0 : 0]; + always @ (*) begin + _zz_1 = 1'b0; + if(pushing)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + pushPtr_willIncrement = 1'b0; + if(pushing)begin + pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + pushPtr_willClear = 1'b0; + if(io_flush)begin + pushPtr_willClear = 1'b1; + end + end + + assign pushPtr_willOverflowIfInc = 1'b1; + assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); + always @ (*) begin + popPtr_willIncrement = 1'b0; + if(popping)begin + popPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + popPtr_willClear = 1'b0; + if(io_flush)begin + popPtr_willClear = 1'b1; + end + end + + assign popPtr_willOverflowIfInc = 1'b1; + assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); + assign ptrMatch = 1'b1; + assign empty = (ptrMatch && (! risingOccupancy)); + assign full = (ptrMatch && risingOccupancy); + assign pushing = (io_push_valid && io_push_ready); + assign popping = (io_pop_valid && io_pop_ready); + assign io_push_ready = (! full); + always @ (*) begin + if(_zz_4)begin + io_pop_valid = 1'b1; + end else begin + io_pop_valid = io_push_valid; + end + end + + assign _zz_2 = _zz_3; + always @ (*) begin + if(_zz_4)begin + io_pop_payload_error = _zz_5[0]; + end else begin + io_pop_payload_error = io_push_payload_error; + end + end + + always @ (*) begin + if(_zz_4)begin + io_pop_payload_inst = _zz_2[32 : 1]; + end else begin + io_pop_payload_inst = io_push_payload_inst; + end + end + + assign io_occupancy = (risingOccupancy && ptrMatch); + always @ (posedge clk) begin + if(reset) begin + risingOccupancy <= 1'b0; + end else begin + if((pushing != popping))begin + risingOccupancy <= pushing; + end + if(io_flush)begin + risingOccupancy <= 1'b0; + end + end + end + + always @ (posedge clk) begin + if(_zz_1)begin + _zz_3 <= {io_push_payload_inst,io_push_payload_error}; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/ext/SpinalHDL b/pythondata_cpu_vexriscv/verilog/ext/SpinalHDL index f7a9fa2..441dfe1 160000 --- a/pythondata_cpu_vexriscv/verilog/ext/SpinalHDL +++ b/pythondata_cpu_vexriscv/verilog/ext/SpinalHDL @@ -1 +1 @@ -Subproject commit f7a9fa258904b963b2b96a3f91c6bdf75083d096 +Subproject commit 441dfe186ba8e331d21395f9cf55c49053ab2965 diff --git a/pythondata_cpu_vexriscv/verilog/ext/VexRiscv b/pythondata_cpu_vexriscv/verilog/ext/VexRiscv index 8bd1785..06b7a91 160000 --- a/pythondata_cpu_vexriscv/verilog/ext/VexRiscv +++ b/pythondata_cpu_vexriscv/verilog/ext/VexRiscv @@ -1 +1 @@ -Subproject commit 8bd1785233dfeb18ce264b2752a0730c1061c62e +Subproject commit 06b7a91de4b288345d9be82324975c19a6ea1136 diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index 6b56a53..f83d70d 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -210,16 +210,17 @@ object GenCoreDefault{ encodings = List( CfuPluginEncoding ( instruction = M"-------------------------0001011", - functionId = List(14 downto 12), + functionId = List(31 downto 12), input2Kind = CfuPlugin.Input2Kind.RS ) ), busParameter = CfuBusParameter( CFU_VERSION = 0, CFU_INTERFACE_ID_W = 0, - CFU_FUNCTION_ID_W = 3, + CFU_FUNCTION_ID_W = 20, CFU_REORDER_ID_W = 0, CFU_REQ_RESP_ID_W = 0, + CFU_STATE_INDEX_NUM = 0, CFU_INPUTS = 2, CFU_INPUT_DATA_W = 32, CFU_OUTPUTS = 1, diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v index d9dcf76..75ccab0 100644 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v @@ -36,7 +36,7 @@ module VexRiscv ( wire CfuPlugin_bus_cmd_valid; wire CfuPlugin_bus_cmd_ready; - wire [2:0] CfuPlugin_bus_cmd_payload_function_id; + wire [19:0] CfuPlugin_bus_cmd_payload_function_id; wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; wire CfuPlugin_bus_rsp_valid; diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v index 3e71b34..069b86c 100644 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v @@ -44,7 +44,7 @@ module VexRiscv ( wire CfuPlugin_bus_cmd_valid; wire CfuPlugin_bus_cmd_ready; - wire [2:0] CfuPlugin_bus_cmd_payload_function_id; + wire [19:0] CfuPlugin_bus_cmd_payload_function_id; wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; wire CfuPlugin_bus_rsp_valid; From 9f870869a08c2f08812676be9bb2baffad2dbfe2 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Fri, 5 Mar 2021 15:54:50 -0800 Subject: [PATCH 08/30] Delete SpinalHDL submodule. Signed-off-by: Tim Callahan --- .gitmodules | 6 +----- pythondata_cpu_vexriscv/verilog/ext/SpinalHDL | 1 - 2 files changed, 1 insertion(+), 6 deletions(-) delete mode 160000 pythondata_cpu_vexriscv/verilog/ext/SpinalHDL diff --git a/.gitmodules b/.gitmodules index 77ab592..bcae734 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,8 +1,4 @@ [submodule "pythondata_cpu_vexriscv/verilog/ext/VexRiscv"] path = pythondata_cpu_vexriscv/verilog/ext/VexRiscv url = https://github.com/SpinalHDL/VexRiscv.git - branch = dev -[submodule "pythondata_cpu_vexriscv/verilog/ext/SpinalHDL"] - path = pythondata_cpu_vexriscv/verilog/ext/SpinalHDL - url = https://github.com/SpinalHDL/SpinalHDL.git - branch = dev + branch = master diff --git a/pythondata_cpu_vexriscv/verilog/ext/SpinalHDL b/pythondata_cpu_vexriscv/verilog/ext/SpinalHDL deleted file mode 160000 index 441dfe1..0000000 --- a/pythondata_cpu_vexriscv/verilog/ext/SpinalHDL +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 441dfe186ba8e331d21395f9cf55c49053ab2965 From b6724a20373cfbda9b04bf70ffd945adfb7e4180 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Fri, 5 Mar 2021 18:32:14 -0800 Subject: [PATCH 09/30] Rebuild: VexRiscv master w/ cfu fix, Spinal 1.4.3, wide func_id. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/VexRiscv.v | 2144 +++++----- .../verilog/VexRiscv_Debug.v | 2236 +++++----- .../verilog/VexRiscv_Full.v | 2244 +++++----- .../verilog/VexRiscv_FullCfu.v | 3666 ++++++++-------- .../verilog/VexRiscv_FullCfuDebug.v | 3766 +++++++++-------- .../verilog/VexRiscv_FullDebug.v | 2332 +++++----- .../verilog/VexRiscv_IMAC.v | 2160 +++++----- .../verilog/VexRiscv_IMACDebug.v | 2262 +++++----- .../verilog/VexRiscv_Linux.v | 3154 +++++++------- .../verilog/VexRiscv_LinuxDebug.v | 3270 +++++++------- .../verilog/VexRiscv_LinuxNoDspFmax.v | 2888 +++++++------ .../verilog/VexRiscv_Lite.v | 1970 +++++---- .../verilog/VexRiscv_LiteDebug.v | 2078 +++++---- .../verilog/VexRiscv_Min.v | 1260 +++--- .../verilog/VexRiscv_MinDebug.v | 1350 +++--- pythondata_cpu_vexriscv/verilog/build.sbt | 10 +- pythondata_cpu_vexriscv/verilog/ext/VexRiscv | 2 +- 17 files changed, 18342 insertions(+), 18450 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv.v b/pythondata_cpu_vexriscv/verilog/VexRiscv.v index 13d0734..8a23a18 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -73,37 +73,37 @@ module VexRiscv ( input clk, input reset ); - wire _zz_160; - wire _zz_161; - wire _zz_162; - wire _zz_163; - wire _zz_164; wire _zz_165; wire _zz_166; wire _zz_167; - reg _zz_168; + wire _zz_168; wire _zz_169; - wire [31:0] _zz_170; + wire _zz_170; wire _zz_171; - wire [31:0] _zz_172; + wire _zz_172; reg _zz_173; wire _zz_174; - wire _zz_175; - wire [31:0] _zz_176; - wire _zz_177; - wire _zz_178; + wire [31:0] _zz_175; + wire _zz_176; + wire [31:0] _zz_177; + reg _zz_178; wire _zz_179; wire _zz_180; - wire _zz_181; + wire [31:0] _zz_181; wire _zz_182; wire _zz_183; wire _zz_184; - wire [3:0] _zz_185; + wire _zz_185; wire _zz_186; wire _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; + wire _zz_188; + wire _zz_189; + wire [3:0] _zz_190; + wire _zz_191; + wire _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -136,11 +136,6 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_191; - wire _zz_192; - wire _zz_193; - wire _zz_194; - wire _zz_195; wire _zz_196; wire _zz_197; wire _zz_198; @@ -149,45 +144,45 @@ module VexRiscv ( wire _zz_201; wire _zz_202; wire _zz_203; - wire [1:0] _zz_204; + wire _zz_204; wire _zz_205; wire _zz_206; wire _zz_207; wire _zz_208; - wire _zz_209; + wire [1:0] _zz_209; wire _zz_210; wire _zz_211; wire _zz_212; wire _zz_213; - wire [1:0] _zz_214; + wire _zz_214; wire _zz_215; wire _zz_216; wire _zz_217; wire _zz_218; - wire _zz_219; + wire [1:0] _zz_219; wire _zz_220; wire _zz_221; wire _zz_222; - wire [1:0] _zz_223; + wire _zz_223; wire _zz_224; - wire [1:0] _zz_225; - wire [51:0] _zz_226; - wire [51:0] _zz_227; - wire [51:0] _zz_228; - wire [32:0] _zz_229; - wire [51:0] _zz_230; - wire [49:0] _zz_231; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire [1:0] _zz_228; + wire _zz_229; + wire [1:0] _zz_230; + wire [51:0] _zz_231; wire [51:0] _zz_232; - wire [49:0] _zz_233; - wire [51:0] _zz_234; - wire [32:0] _zz_235; - wire [31:0] _zz_236; - wire [32:0] _zz_237; - wire [0:0] _zz_238; - wire [0:0] _zz_239; - wire [0:0] _zz_240; - wire [0:0] _zz_241; - wire [0:0] _zz_242; + wire [51:0] _zz_233; + wire [32:0] _zz_234; + wire [51:0] _zz_235; + wire [49:0] _zz_236; + wire [51:0] _zz_237; + wire [49:0] _zz_238; + wire [51:0] _zz_239; + wire [32:0] _zz_240; + wire [31:0] _zz_241; + wire [32:0] _zz_242; wire [0:0] _zz_243; wire [0:0] _zz_244; wire [0:0] _zz_245; @@ -200,254 +195,259 @@ module VexRiscv ( wire [0:0] _zz_252; wire [0:0] _zz_253; wire [0:0] _zz_254; - wire [3:0] _zz_255; - wire [2:0] _zz_256; - wire [31:0] _zz_257; - wire [11:0] _zz_258; - wire [31:0] _zz_259; - wire [19:0] _zz_260; - wire [11:0] _zz_261; + wire [0:0] _zz_255; + wire [0:0] _zz_256; + wire [0:0] _zz_257; + wire [0:0] _zz_258; + wire [0:0] _zz_259; + wire [3:0] _zz_260; + wire [2:0] _zz_261; wire [31:0] _zz_262; - wire [31:0] _zz_263; - wire [19:0] _zz_264; - wire [11:0] _zz_265; - wire [2:0] _zz_266; - wire [2:0] _zz_267; - wire [0:0] _zz_268; - wire [2:0] _zz_269; - wire [4:0] _zz_270; - wire [11:0] _zz_271; - wire [11:0] _zz_272; - wire [31:0] _zz_273; - wire [31:0] _zz_274; - wire [31:0] _zz_275; - wire [31:0] _zz_276; - wire [31:0] _zz_277; + wire [11:0] _zz_263; + wire [31:0] _zz_264; + wire [19:0] _zz_265; + wire [11:0] _zz_266; + wire [31:0] _zz_267; + wire [31:0] _zz_268; + wire [19:0] _zz_269; + wire [11:0] _zz_270; + wire [2:0] _zz_271; + wire [2:0] _zz_272; + wire [0:0] _zz_273; + wire [2:0] _zz_274; + wire [4:0] _zz_275; + wire [11:0] _zz_276; + wire [11:0] _zz_277; wire [31:0] _zz_278; wire [31:0] _zz_279; - wire [11:0] _zz_280; - wire [19:0] _zz_281; - wire [11:0] _zz_282; + wire [31:0] _zz_280; + wire [31:0] _zz_281; + wire [31:0] _zz_282; wire [31:0] _zz_283; wire [31:0] _zz_284; - wire [31:0] _zz_285; - wire [11:0] _zz_286; - wire [19:0] _zz_287; - wire [11:0] _zz_288; - wire [2:0] _zz_289; - wire [1:0] _zz_290; - wire [1:0] _zz_291; - wire [65:0] _zz_292; - wire [65:0] _zz_293; - wire [31:0] _zz_294; - wire [31:0] _zz_295; - wire [0:0] _zz_296; - wire [5:0] _zz_297; - wire [32:0] _zz_298; + wire [11:0] _zz_285; + wire [19:0] _zz_286; + wire [11:0] _zz_287; + wire [31:0] _zz_288; + wire [31:0] _zz_289; + wire [31:0] _zz_290; + wire [11:0] _zz_291; + wire [19:0] _zz_292; + wire [11:0] _zz_293; + wire [2:0] _zz_294; + wire [1:0] _zz_295; + wire [1:0] _zz_296; + wire [65:0] _zz_297; + wire [65:0] _zz_298; wire [31:0] _zz_299; wire [31:0] _zz_300; - wire [32:0] _zz_301; - wire [32:0] _zz_302; + wire [0:0] _zz_301; + wire [5:0] _zz_302; wire [32:0] _zz_303; - wire [32:0] _zz_304; - wire [0:0] _zz_305; + wire [31:0] _zz_304; + wire [31:0] _zz_305; wire [32:0] _zz_306; - wire [0:0] _zz_307; + wire [32:0] _zz_307; wire [32:0] _zz_308; - wire [0:0] _zz_309; - wire [31:0] _zz_310; - wire [0:0] _zz_311; + wire [32:0] _zz_309; + wire [0:0] _zz_310; + wire [32:0] _zz_311; wire [0:0] _zz_312; - wire [0:0] _zz_313; + wire [32:0] _zz_313; wire [0:0] _zz_314; - wire [0:0] _zz_315; + wire [31:0] _zz_315; wire [0:0] _zz_316; - wire [26:0] _zz_317; - wire _zz_318; - wire _zz_319; - wire [1:0] _zz_320; - wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire [0:0] _zz_321; + wire [26:0] _zz_322; + wire _zz_323; wire _zz_324; - wire [0:0] _zz_325; - wire [13:0] _zz_326; + wire [1:0] _zz_325; + wire [31:0] _zz_326; wire [31:0] _zz_327; wire [31:0] _zz_328; - wire [31:0] _zz_329; - wire _zz_330; - wire [0:0] _zz_331; - wire [7:0] _zz_332; + wire _zz_329; + wire [0:0] _zz_330; + wire [13:0] _zz_331; + wire [31:0] _zz_332; wire [31:0] _zz_333; wire [31:0] _zz_334; - wire [31:0] _zz_335; - wire _zz_336; - wire [0:0] _zz_337; - wire [1:0] _zz_338; - wire _zz_339; - wire _zz_340; + wire _zz_335; + wire [0:0] _zz_336; + wire [7:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [31:0] _zz_340; wire _zz_341; - wire [31:0] _zz_342; - wire [31:0] _zz_343; + wire [0:0] _zz_342; + wire [1:0] _zz_343; wire _zz_344; - wire [0:0] _zz_345; - wire [0:0] _zz_346; - wire _zz_347; - wire [0:0] _zz_348; - wire [24:0] _zz_349; - wire [31:0] _zz_350; - wire _zz_351; + wire _zz_345; + wire _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; + wire _zz_349; + wire [0:0] _zz_350; + wire [0:0] _zz_351; wire _zz_352; wire [0:0] _zz_353; - wire [0:0] _zz_354; - wire [0:0] _zz_355; - wire [0:0] _zz_356; + wire [24:0] _zz_354; + wire [31:0] _zz_355; + wire _zz_356; wire _zz_357; wire [0:0] _zz_358; - wire [20:0] _zz_359; - wire [31:0] _zz_360; - wire [31:0] _zz_361; + wire [0:0] _zz_359; + wire [0:0] _zz_360; + wire [0:0] _zz_361; wire _zz_362; - wire _zz_363; - wire [0:0] _zz_364; - wire [1:0] _zz_365; - wire [0:0] _zz_366; - wire [0:0] _zz_367; + wire [0:0] _zz_363; + wire [20:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire _zz_367; wire _zz_368; wire [0:0] _zz_369; - wire [17:0] _zz_370; - wire [31:0] _zz_371; - wire [31:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire [31:0] _zz_375; + wire [1:0] _zz_370; + wire [0:0] _zz_371; + wire [0:0] _zz_372; + wire _zz_373; + wire [0:0] _zz_374; + wire [17:0] _zz_375; wire [31:0] _zz_376; wire [31:0] _zz_377; wire [31:0] _zz_378; - wire _zz_379; - wire [1:0] _zz_380; - wire [1:0] _zz_381; - wire _zz_382; - wire [0:0] _zz_383; - wire [14:0] _zz_384; - wire [31:0] _zz_385; - wire [31:0] _zz_386; - wire [31:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; + wire [31:0] _zz_379; + wire [31:0] _zz_380; + wire [31:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire _zz_384; + wire [1:0] _zz_385; + wire [1:0] _zz_386; + wire _zz_387; + wire [0:0] _zz_388; + wire [14:0] _zz_389; wire [31:0] _zz_390; - wire [0:0] _zz_391; - wire [0:0] _zz_392; - wire [2:0] _zz_393; - wire [2:0] _zz_394; - wire _zz_395; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire [31:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; wire [0:0] _zz_396; - wire [11:0] _zz_397; - wire [31:0] _zz_398; - wire [31:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire _zz_402; - wire _zz_403; + wire [0:0] _zz_397; + wire [2:0] _zz_398; + wire [2:0] _zz_399; + wire _zz_400; + wire [0:0] _zz_401; + wire [11:0] _zz_402; + wire [31:0] _zz_403; wire [31:0] _zz_404; wire [31:0] _zz_405; - wire [0:0] _zz_406; - wire [3:0] _zz_407; - wire [4:0] _zz_408; - wire [4:0] _zz_409; - wire _zz_410; + wire [31:0] _zz_406; + wire _zz_407; + wire _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; wire [0:0] _zz_411; - wire [8:0] _zz_412; - wire [31:0] _zz_413; - wire [31:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [0:0] _zz_417; - wire [1:0] _zz_418; - wire [0:0] _zz_419; - wire [2:0] _zz_420; - wire [0:0] _zz_421; - wire [4:0] _zz_422; + wire [3:0] _zz_412; + wire [4:0] _zz_413; + wire [4:0] _zz_414; + wire _zz_415; + wire [0:0] _zz_416; + wire [8:0] _zz_417; + wire [31:0] _zz_418; + wire [31:0] _zz_419; + wire [31:0] _zz_420; + wire [31:0] _zz_421; + wire [0:0] _zz_422; wire [1:0] _zz_423; - wire [1:0] _zz_424; - wire _zz_425; + wire [0:0] _zz_424; + wire [2:0] _zz_425; wire [0:0] _zz_426; - wire [6:0] _zz_427; - wire [31:0] _zz_428; - wire [31:0] _zz_429; + wire [4:0] _zz_427; + wire [1:0] _zz_428; + wire [1:0] _zz_429; wire _zz_430; - wire _zz_431; - wire [31:0] _zz_432; + wire [0:0] _zz_431; + wire [6:0] _zz_432; wire [31:0] _zz_433; - wire _zz_434; - wire [0:0] _zz_435; - wire [0:0] _zz_436; - wire _zz_437; - wire [0:0] _zz_438; - wire [2:0] _zz_439; - wire _zz_440; + wire [31:0] _zz_434; + wire _zz_435; + wire _zz_436; + wire [31:0] _zz_437; + wire [31:0] _zz_438; + wire _zz_439; + wire [0:0] _zz_440; wire [0:0] _zz_441; - wire [0:0] _zz_442; + wire _zz_442; wire [0:0] _zz_443; - wire [0:0] _zz_444; + wire [2:0] _zz_444; wire _zz_445; wire [0:0] _zz_446; - wire [4:0] _zz_447; - wire [31:0] _zz_448; - wire [31:0] _zz_449; - wire [31:0] _zz_450; - wire [31:0] _zz_451; - wire [31:0] _zz_452; + wire [0:0] _zz_447; + wire [0:0] _zz_448; + wire [0:0] _zz_449; + wire _zz_450; + wire [0:0] _zz_451; + wire [4:0] _zz_452; wire [31:0] _zz_453; wire [31:0] _zz_454; wire [31:0] _zz_455; wire [31:0] _zz_456; wire [31:0] _zz_457; - wire _zz_458; - wire [0:0] _zz_459; - wire [0:0] _zz_460; + wire [31:0] _zz_458; + wire [31:0] _zz_459; + wire [31:0] _zz_460; wire [31:0] _zz_461; wire [31:0] _zz_462; - wire [31:0] _zz_463; - wire [31:0] _zz_464; - wire [31:0] _zz_465; - wire _zz_466; - wire [3:0] _zz_467; - wire [3:0] _zz_468; - wire _zz_469; - wire [0:0] _zz_470; - wire [2:0] _zz_471; - wire [31:0] _zz_472; - wire [31:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; + wire _zz_463; + wire [0:0] _zz_464; + wire [0:0] _zz_465; + wire [31:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire _zz_471; + wire [3:0] _zz_472; + wire [3:0] _zz_473; + wire _zz_474; + wire [0:0] _zz_475; + wire [2:0] _zz_476; wire [31:0] _zz_477; - wire _zz_478; - wire [0:0] _zz_479; - wire [1:0] _zz_480; - wire _zz_481; - wire [2:0] _zz_482; - wire [2:0] _zz_483; - wire _zz_484; - wire [0:0] _zz_485; - wire [0:0] _zz_486; - wire [31:0] _zz_487; - wire [31:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; - wire [31:0] _zz_491; + wire [31:0] _zz_478; + wire [31:0] _zz_479; + wire [31:0] _zz_480; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire _zz_483; + wire [0:0] _zz_484; + wire [1:0] _zz_485; + wire _zz_486; + wire [2:0] _zz_487; + wire [2:0] _zz_488; + wire _zz_489; + wire [0:0] _zz_490; + wire [0:0] _zz_491; wire [31:0] _zz_492; wire [31:0] _zz_493; - wire _zz_494; - wire _zz_495; - wire _zz_496; - wire [0:0] _zz_497; - wire [0:0] _zz_498; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire [31:0] _zz_497; + wire [31:0] _zz_498; wire _zz_499; wire _zz_500; wire _zz_501; - wire _zz_502; + wire [0:0] _zz_502; + wire [0:0] _zz_503; + wire _zz_504; + wire _zz_505; + wire _zz_506; + wire _zz_507; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -923,42 +923,37 @@ module VexRiscv ( reg [31:0] _zz_106; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_107; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_108; - wire _zz_109; - wire _zz_110; - wire _zz_111; - wire _zz_112; + reg _zz_108; + reg _zz_109; + reg _zz_110; + reg [4:0] _zz_111; + reg [31:0] _zz_112; wire _zz_113; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_114; - reg _zz_115; - reg _zz_116; + wire _zz_114; + wire _zz_115; + wire _zz_116; wire _zz_117; - reg [19:0] _zz_118; - wire _zz_119; - reg [10:0] _zz_120; - wire _zz_121; - reg [18:0] _zz_122; - reg _zz_123; + wire _zz_118; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_119; + reg _zz_120; + reg _zz_121; + wire _zz_122; + reg [19:0] _zz_123; + wire _zz_124; + reg [10:0] _zz_125; + wire _zz_126; + reg [18:0] _zz_127; + reg _zz_128; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_124; - reg [19:0] _zz_125; - wire _zz_126; - reg [10:0] _zz_127; - wire _zz_128; - reg [18:0] _zz_129; + wire _zz_129; + reg [19:0] _zz_130; + wire _zz_131; + reg [10:0] _zz_132; + wire _zz_133; + reg [18:0] _zz_134; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; @@ -979,9 +974,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_130; - wire _zz_131; - wire _zz_132; + wire _zz_135; + wire _zz_136; + wire _zz_137; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -994,8 +989,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_133; - wire _zz_134; + wire [1:0] _zz_138; + wire _zz_139; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1048,18 +1043,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_135; + wire [31:0] _zz_140; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_136; - wire _zz_137; - wire _zz_138; - reg [32:0] _zz_139; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_140; wire [31:0] _zz_141; + wire _zz_142; + wire _zz_143; + reg [32:0] _zz_144; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_145; + wire [31:0] _zz_146; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1132,25 +1127,25 @@ module VexRiscv ( reg execute_CsrPlugin_csr_835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_142; - reg [31:0] _zz_143; - reg [31:0] _zz_144; - reg [31:0] _zz_145; - reg [31:0] _zz_146; reg [31:0] _zz_147; reg [31:0] _zz_148; reg [31:0] _zz_149; reg [31:0] _zz_150; - reg [2:0] _zz_151; - reg _zz_152; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [2:0] _zz_156; + reg _zz_157; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_153; - wire _zz_154; - wire _zz_155; - wire _zz_156; - wire _zz_157; - wire _zz_158; - reg _zz_159; + reg [2:0] _zz_158; + wire _zz_159; + wire _zz_160; + wire _zz_161; + wire _zz_162; + wire _zz_163; + reg _zz_164; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] _zz_1_string; @@ -1235,327 +1230,327 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_191 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_192 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_193 = 1'b1; - assign _zz_194 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_195 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_196 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_197 = ((_zz_165 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_198 = ((_zz_165 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_199 = ((_zz_165 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_200 = ((_zz_165 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_201 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_202 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_203 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_204 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_205 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_206 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_207 = (1'b0 || (! 1'b1)); - assign _zz_208 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_209 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_210 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_211 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_212 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_213 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_214 = execute_INSTRUCTION[13 : 12]; - assign _zz_215 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_216 = (! memory_arbitration_isStuck); - assign _zz_217 = (iBus_cmd_valid || (_zz_151 != 3'b000)); - assign _zz_218 = (_zz_187 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_219 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_220 = ((_zz_130 && 1'b1) && (! 1'b0)); - assign _zz_221 = ((_zz_131 && 1'b1) && (! 1'b0)); - assign _zz_222 = ((_zz_132 && 1'b1) && (! 1'b0)); - assign _zz_223 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_224 = execute_INSTRUCTION[13]; - assign _zz_225 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_226 = ($signed(_zz_227) + $signed(_zz_232)); - assign _zz_227 = ($signed(_zz_228) + $signed(_zz_230)); - assign _zz_228 = 52'h0; - assign _zz_229 = {1'b0,memory_MUL_LL}; - assign _zz_230 = {{19{_zz_229[32]}}, _zz_229}; - assign _zz_231 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_232 = {{2{_zz_231[49]}}, _zz_231}; - assign _zz_233 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_234 = {{2{_zz_233[49]}}, _zz_233}; - assign _zz_235 = ($signed(_zz_237) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_236 = _zz_235[31 : 0]; - assign _zz_237 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_238 = _zz_86[31 : 31]; - assign _zz_239 = _zz_86[30 : 30]; - assign _zz_240 = _zz_86[29 : 29]; - assign _zz_241 = _zz_86[28 : 28]; - assign _zz_242 = _zz_86[25 : 25]; - assign _zz_243 = _zz_86[17 : 17]; - assign _zz_244 = _zz_86[16 : 16]; - assign _zz_245 = _zz_86[13 : 13]; - assign _zz_246 = _zz_86[12 : 12]; - assign _zz_247 = _zz_86[11 : 11]; - assign _zz_248 = _zz_86[15 : 15]; - assign _zz_249 = _zz_86[5 : 5]; - assign _zz_250 = _zz_86[3 : 3]; - assign _zz_251 = _zz_86[20 : 20]; - assign _zz_252 = _zz_86[10 : 10]; - assign _zz_253 = _zz_86[4 : 4]; - assign _zz_254 = _zz_86[0 : 0]; - assign _zz_255 = (_zz_54 - 4'b0001); - assign _zz_256 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_257 = {29'd0, _zz_256}; - assign _zz_258 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_259 = {{_zz_69,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_260 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_261 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_262 = {{_zz_71,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_263 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_264 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_265 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_266 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_267 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_268 = execute_SRC_LESS; - assign _zz_269 = 3'b100; - assign _zz_270 = execute_INSTRUCTION[19 : 15]; - assign _zz_271 = execute_INSTRUCTION[31 : 20]; - assign _zz_272 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_273 = ($signed(_zz_274) + $signed(_zz_277)); - assign _zz_274 = ($signed(_zz_275) + $signed(_zz_276)); - assign _zz_275 = execute_SRC1; - assign _zz_276 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_277 = (execute_SRC_USE_SUB_LESS ? _zz_278 : _zz_279); - assign _zz_278 = 32'h00000001; - assign _zz_279 = 32'h0; - assign _zz_280 = execute_INSTRUCTION[31 : 20]; - assign _zz_281 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_282 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_283 = {_zz_118,execute_INSTRUCTION[31 : 20]}; - assign _zz_284 = {{_zz_120,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_285 = {{_zz_122,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_286 = execute_INSTRUCTION[31 : 20]; - assign _zz_287 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_288 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_289 = 3'b100; - assign _zz_290 = (_zz_133 & (~ _zz_291)); - assign _zz_291 = (_zz_133 - 2'b01); - assign _zz_292 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_293 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_294 = writeBack_MUL_LOW[31 : 0]; - assign _zz_295 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_296 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_297 = {5'd0, _zz_296}; - assign _zz_298 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_299 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_300 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_301 = {_zz_135,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_302 = _zz_303; - assign _zz_303 = _zz_304; - assign _zz_304 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_136) : _zz_136)} + _zz_306); - assign _zz_305 = memory_DivPlugin_div_needRevert; - assign _zz_306 = {32'd0, _zz_305}; - assign _zz_307 = _zz_138; - assign _zz_308 = {32'd0, _zz_307}; - assign _zz_309 = _zz_137; - assign _zz_310 = {31'd0, _zz_309}; - assign _zz_311 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_312 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_313 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_314 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_315 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_316 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_317 = (iBus_cmd_payload_address >>> 5); - assign _zz_318 = 1'b1; - assign _zz_319 = 1'b1; - assign _zz_320 = {_zz_58,_zz_57}; - assign _zz_321 = 32'h0000107f; - assign _zz_322 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_323 = 32'h00002073; - assign _zz_324 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_325 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_326 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_327) == 32'h00000003),{(_zz_328 == _zz_329),{_zz_330,{_zz_331,_zz_332}}}}}}; - assign _zz_327 = 32'h0000505f; - assign _zz_328 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_329 = 32'h00000063; - assign _zz_330 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_331 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_332 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_333) == 32'h00001013),{(_zz_334 == _zz_335),{_zz_336,{_zz_337,_zz_338}}}}}}; - assign _zz_333 = 32'hfc00307f; - assign _zz_334 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_335 = 32'h00005033; - assign _zz_336 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_337 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_338 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; - assign _zz_339 = decode_INSTRUCTION[31]; - assign _zz_340 = decode_INSTRUCTION[31]; - assign _zz_341 = decode_INSTRUCTION[7]; - assign _zz_342 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_343 = 32'h02004020; - assign _zz_344 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_345 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); - assign _zz_346 = 1'b0; - assign _zz_347 = (((decode_INSTRUCTION & _zz_350) == 32'h10000050) != 1'b0); - assign _zz_348 = ({_zz_351,_zz_352} != 2'b00); - assign _zz_349 = {({_zz_353,_zz_354} != 2'b00),{(_zz_355 != _zz_356),{_zz_357,{_zz_358,_zz_359}}}}; - assign _zz_350 = 32'h10403050; - assign _zz_351 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_352 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_353 = _zz_89; - assign _zz_354 = ((decode_INSTRUCTION & _zz_360) == 32'h00000004); - assign _zz_355 = ((decode_INSTRUCTION & _zz_361) == 32'h00000040); - assign _zz_356 = 1'b0; - assign _zz_357 = ({_zz_362,_zz_363} != 2'b00); - assign _zz_358 = ({_zz_364,_zz_365} != 3'b000); - assign _zz_359 = {(_zz_366 != _zz_367),{_zz_368,{_zz_369,_zz_370}}}; - assign _zz_360 = 32'h0000001c; - assign _zz_361 = 32'h00000058; - assign _zz_362 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_363 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_364 = ((decode_INSTRUCTION & _zz_371) == 32'h40001010); - assign _zz_365 = {(_zz_372 == _zz_373),(_zz_374 == _zz_375)}; - assign _zz_366 = ((decode_INSTRUCTION & _zz_376) == 32'h00000024); - assign _zz_367 = 1'b0; - assign _zz_368 = ((_zz_377 == _zz_378) != 1'b0); - assign _zz_369 = (_zz_379 != 1'b0); - assign _zz_370 = {(_zz_380 != _zz_381),{_zz_382,{_zz_383,_zz_384}}}; - assign _zz_371 = 32'h40003054; - assign _zz_372 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_373 = 32'h00001010; - assign _zz_374 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_375 = 32'h00001010; - assign _zz_376 = 32'h00000064; - assign _zz_377 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_378 = 32'h00001000; - assign _zz_379 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_380 = {(_zz_385 == _zz_386),(_zz_387 == _zz_388)}; - assign _zz_381 = 2'b00; - assign _zz_382 = ((_zz_389 == _zz_390) != 1'b0); - assign _zz_383 = ({_zz_391,_zz_392} != 2'b00); - assign _zz_384 = {(_zz_393 != _zz_394),{_zz_395,{_zz_396,_zz_397}}}; - assign _zz_385 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_386 = 32'h00002000; - assign _zz_387 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_388 = 32'h00001000; - assign _zz_389 = (decode_INSTRUCTION & 32'h00004048); - assign _zz_390 = 32'h00004008; - assign _zz_391 = ((decode_INSTRUCTION & _zz_398) == 32'h00000020); - assign _zz_392 = ((decode_INSTRUCTION & _zz_399) == 32'h00000020); - assign _zz_393 = {(_zz_400 == _zz_401),{_zz_402,_zz_403}}; - assign _zz_394 = 3'b000; - assign _zz_395 = ((_zz_404 == _zz_405) != 1'b0); - assign _zz_396 = ({_zz_406,_zz_407} != 5'h0); - assign _zz_397 = {(_zz_408 != _zz_409),{_zz_410,{_zz_411,_zz_412}}}; - assign _zz_398 = 32'h00000034; - assign _zz_399 = 32'h00000064; - assign _zz_400 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_401 = 32'h00000040; - assign _zz_402 = ((decode_INSTRUCTION & _zz_413) == 32'h0); - assign _zz_403 = ((decode_INSTRUCTION & _zz_414) == 32'h00000040); - assign _zz_404 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_405 = 32'h00000020; - assign _zz_406 = (_zz_415 == _zz_416); - assign _zz_407 = {_zz_88,{_zz_417,_zz_418}}; - assign _zz_408 = {_zz_88,{_zz_419,_zz_420}}; - assign _zz_409 = 5'h0; - assign _zz_410 = ({_zz_421,_zz_422} != 6'h0); - assign _zz_411 = (_zz_423 != _zz_424); - assign _zz_412 = {_zz_425,{_zz_426,_zz_427}}; - assign _zz_413 = 32'h00000038; - assign _zz_414 = 32'h00403040; - assign _zz_415 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_416 = 32'h00000040; - assign _zz_417 = (_zz_428 == _zz_429); - assign _zz_418 = {_zz_430,_zz_431}; - assign _zz_419 = (_zz_432 == _zz_433); - assign _zz_420 = {_zz_434,{_zz_435,_zz_436}}; - assign _zz_421 = _zz_89; - assign _zz_422 = {_zz_437,{_zz_438,_zz_439}}; - assign _zz_423 = {_zz_88,_zz_440}; - assign _zz_424 = 2'b00; - assign _zz_425 = ({_zz_441,_zz_442} != 2'b00); - assign _zz_426 = (_zz_443 != _zz_444); - assign _zz_427 = {_zz_445,{_zz_446,_zz_447}}; - assign _zz_428 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_429 = 32'h00004020; - assign _zz_430 = ((decode_INSTRUCTION & _zz_448) == 32'h00000010); - assign _zz_431 = ((decode_INSTRUCTION & _zz_449) == 32'h00000020); - assign _zz_432 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_433 = 32'h00002010; - assign _zz_434 = ((decode_INSTRUCTION & _zz_450) == 32'h00000010); - assign _zz_435 = (_zz_451 == _zz_452); - assign _zz_436 = (_zz_453 == _zz_454); - assign _zz_437 = ((decode_INSTRUCTION & _zz_455) == 32'h00001010); - assign _zz_438 = (_zz_456 == _zz_457); - assign _zz_439 = {_zz_458,{_zz_459,_zz_460}}; - assign _zz_440 = ((decode_INSTRUCTION & _zz_461) == 32'h00000020); - assign _zz_441 = _zz_88; - assign _zz_442 = (_zz_462 == _zz_463); - assign _zz_443 = (_zz_464 == _zz_465); - assign _zz_444 = 1'b0; - assign _zz_445 = (_zz_466 != 1'b0); - assign _zz_446 = (_zz_467 != _zz_468); - assign _zz_447 = {_zz_469,{_zz_470,_zz_471}}; - assign _zz_448 = 32'h00000030; - assign _zz_449 = 32'h02000020; - assign _zz_450 = 32'h00001030; - assign _zz_451 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_452 = 32'h00002020; - assign _zz_453 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_454 = 32'h00000020; - assign _zz_455 = 32'h00001010; - assign _zz_456 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_457 = 32'h00002010; - assign _zz_458 = ((decode_INSTRUCTION & _zz_472) == 32'h00000010); - assign _zz_459 = (_zz_473 == _zz_474); - assign _zz_460 = (_zz_475 == _zz_476); - assign _zz_461 = 32'h00000070; - assign _zz_462 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_463 = 32'h0; - assign _zz_464 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_465 = 32'h00004010; - assign _zz_466 = ((decode_INSTRUCTION & _zz_477) == 32'h00002010); - assign _zz_467 = {_zz_478,{_zz_479,_zz_480}}; - assign _zz_468 = 4'b0000; - assign _zz_469 = (_zz_481 != 1'b0); - assign _zz_470 = (_zz_482 != _zz_483); - assign _zz_471 = {_zz_484,{_zz_485,_zz_486}}; - assign _zz_472 = 32'h00000050; - assign _zz_473 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_474 = 32'h00000004; - assign _zz_475 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_476 = 32'h0; - assign _zz_477 = 32'h00006014; - assign _zz_478 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_479 = ((decode_INSTRUCTION & _zz_487) == 32'h0); - assign _zz_480 = {(_zz_488 == _zz_489),(_zz_490 == _zz_491)}; - assign _zz_481 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_482 = {(_zz_492 == _zz_493),{_zz_494,_zz_495}}; - assign _zz_483 = 3'b000; - assign _zz_484 = ({_zz_496,_zz_87} != 2'b00); - assign _zz_485 = ({_zz_497,_zz_498} != 2'b00); - assign _zz_486 = (_zz_499 != 1'b0); - assign _zz_487 = 32'h00000018; - assign _zz_488 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_489 = 32'h00002000; - assign _zz_490 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_491 = 32'h00001000; - assign _zz_492 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_493 = 32'h00000040; - assign _zz_494 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_495 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_496 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_497 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_498 = _zz_87; - assign _zz_499 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); - assign _zz_500 = execute_INSTRUCTION[31]; - assign _zz_501 = execute_INSTRUCTION[31]; - assign _zz_502 = execute_INSTRUCTION[7]; + assign _zz_196 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_197 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_198 = 1'b1; + assign _zz_199 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_200 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_201 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_202 = ((_zz_170 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_203 = ((_zz_170 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_204 = ((_zz_170 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_205 = ((_zz_170 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_206 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_207 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_208 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_209 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_210 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_211 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_212 = (1'b0 || (! 1'b1)); + assign _zz_213 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_214 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_215 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_216 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_217 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_218 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_219 = execute_INSTRUCTION[13 : 12]; + assign _zz_220 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_221 = (! memory_arbitration_isStuck); + assign _zz_222 = (iBus_cmd_valid || (_zz_156 != 3'b000)); + assign _zz_223 = (_zz_192 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_224 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_225 = ((_zz_135 && 1'b1) && (! 1'b0)); + assign _zz_226 = ((_zz_136 && 1'b1) && (! 1'b0)); + assign _zz_227 = ((_zz_137 && 1'b1) && (! 1'b0)); + assign _zz_228 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_229 = execute_INSTRUCTION[13]; + assign _zz_230 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_231 = ($signed(_zz_232) + $signed(_zz_237)); + assign _zz_232 = ($signed(_zz_233) + $signed(_zz_235)); + assign _zz_233 = 52'h0; + assign _zz_234 = {1'b0,memory_MUL_LL}; + assign _zz_235 = {{19{_zz_234[32]}}, _zz_234}; + assign _zz_236 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_237 = {{2{_zz_236[49]}}, _zz_236}; + assign _zz_238 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_239 = {{2{_zz_238[49]}}, _zz_238}; + assign _zz_240 = ($signed(_zz_242) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_241 = _zz_240[31 : 0]; + assign _zz_242 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_243 = _zz_86[31 : 31]; + assign _zz_244 = _zz_86[30 : 30]; + assign _zz_245 = _zz_86[29 : 29]; + assign _zz_246 = _zz_86[28 : 28]; + assign _zz_247 = _zz_86[25 : 25]; + assign _zz_248 = _zz_86[17 : 17]; + assign _zz_249 = _zz_86[16 : 16]; + assign _zz_250 = _zz_86[13 : 13]; + assign _zz_251 = _zz_86[12 : 12]; + assign _zz_252 = _zz_86[11 : 11]; + assign _zz_253 = _zz_86[15 : 15]; + assign _zz_254 = _zz_86[5 : 5]; + assign _zz_255 = _zz_86[3 : 3]; + assign _zz_256 = _zz_86[20 : 20]; + assign _zz_257 = _zz_86[10 : 10]; + assign _zz_258 = _zz_86[4 : 4]; + assign _zz_259 = _zz_86[0 : 0]; + assign _zz_260 = (_zz_54 - 4'b0001); + assign _zz_261 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_262 = {29'd0, _zz_261}; + assign _zz_263 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_264 = {{_zz_69,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_265 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_266 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_267 = {{_zz_71,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_268 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_269 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_270 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_271 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_272 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_273 = execute_SRC_LESS; + assign _zz_274 = 3'b100; + assign _zz_275 = execute_INSTRUCTION[19 : 15]; + assign _zz_276 = execute_INSTRUCTION[31 : 20]; + assign _zz_277 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_278 = ($signed(_zz_279) + $signed(_zz_282)); + assign _zz_279 = ($signed(_zz_280) + $signed(_zz_281)); + assign _zz_280 = execute_SRC1; + assign _zz_281 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_282 = (execute_SRC_USE_SUB_LESS ? _zz_283 : _zz_284); + assign _zz_283 = 32'h00000001; + assign _zz_284 = 32'h0; + assign _zz_285 = execute_INSTRUCTION[31 : 20]; + assign _zz_286 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_287 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_288 = {_zz_123,execute_INSTRUCTION[31 : 20]}; + assign _zz_289 = {{_zz_125,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_290 = {{_zz_127,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_291 = execute_INSTRUCTION[31 : 20]; + assign _zz_292 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_293 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_294 = 3'b100; + assign _zz_295 = (_zz_138 & (~ _zz_296)); + assign _zz_296 = (_zz_138 - 2'b01); + assign _zz_297 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_298 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_299 = writeBack_MUL_LOW[31 : 0]; + assign _zz_300 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_301 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_302 = {5'd0, _zz_301}; + assign _zz_303 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_304 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_305 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_306 = {_zz_140,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_307 = _zz_308; + assign _zz_308 = _zz_309; + assign _zz_309 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_141) : _zz_141)} + _zz_311); + assign _zz_310 = memory_DivPlugin_div_needRevert; + assign _zz_311 = {32'd0, _zz_310}; + assign _zz_312 = _zz_143; + assign _zz_313 = {32'd0, _zz_312}; + assign _zz_314 = _zz_142; + assign _zz_315 = {31'd0, _zz_314}; + assign _zz_316 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_317 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_318 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_319 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_320 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_321 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_322 = (iBus_cmd_payload_address >>> 5); + assign _zz_323 = 1'b1; + assign _zz_324 = 1'b1; + assign _zz_325 = {_zz_58,_zz_57}; + assign _zz_326 = 32'h0000107f; + assign _zz_327 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_328 = 32'h00002073; + assign _zz_329 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_330 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_331 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_332) == 32'h00000003),{(_zz_333 == _zz_334),{_zz_335,{_zz_336,_zz_337}}}}}}; + assign _zz_332 = 32'h0000505f; + assign _zz_333 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_334 = 32'h00000063; + assign _zz_335 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_336 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_337 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_338) == 32'h00001013),{(_zz_339 == _zz_340),{_zz_341,{_zz_342,_zz_343}}}}}}; + assign _zz_338 = 32'hfc00307f; + assign _zz_339 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_340 = 32'h00005033; + assign _zz_341 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_342 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_343 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_344 = decode_INSTRUCTION[31]; + assign _zz_345 = decode_INSTRUCTION[31]; + assign _zz_346 = decode_INSTRUCTION[7]; + assign _zz_347 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_348 = 32'h02004020; + assign _zz_349 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_350 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz_351 = 1'b0; + assign _zz_352 = (((decode_INSTRUCTION & _zz_355) == 32'h10000050) != 1'b0); + assign _zz_353 = ({_zz_356,_zz_357} != 2'b00); + assign _zz_354 = {({_zz_358,_zz_359} != 2'b00),{(_zz_360 != _zz_361),{_zz_362,{_zz_363,_zz_364}}}}; + assign _zz_355 = 32'h10403050; + assign _zz_356 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_357 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_358 = _zz_89; + assign _zz_359 = ((decode_INSTRUCTION & _zz_365) == 32'h00000004); + assign _zz_360 = ((decode_INSTRUCTION & _zz_366) == 32'h00000040); + assign _zz_361 = 1'b0; + assign _zz_362 = ({_zz_367,_zz_368} != 2'b00); + assign _zz_363 = ({_zz_369,_zz_370} != 3'b000); + assign _zz_364 = {(_zz_371 != _zz_372),{_zz_373,{_zz_374,_zz_375}}}; + assign _zz_365 = 32'h0000001c; + assign _zz_366 = 32'h00000058; + assign _zz_367 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_368 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_369 = ((decode_INSTRUCTION & _zz_376) == 32'h40001010); + assign _zz_370 = {(_zz_377 == _zz_378),(_zz_379 == _zz_380)}; + assign _zz_371 = ((decode_INSTRUCTION & _zz_381) == 32'h00000024); + assign _zz_372 = 1'b0; + assign _zz_373 = ((_zz_382 == _zz_383) != 1'b0); + assign _zz_374 = (_zz_384 != 1'b0); + assign _zz_375 = {(_zz_385 != _zz_386),{_zz_387,{_zz_388,_zz_389}}}; + assign _zz_376 = 32'h40003054; + assign _zz_377 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_378 = 32'h00001010; + assign _zz_379 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_380 = 32'h00001010; + assign _zz_381 = 32'h00000064; + assign _zz_382 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_383 = 32'h00001000; + assign _zz_384 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_385 = {(_zz_390 == _zz_391),(_zz_392 == _zz_393)}; + assign _zz_386 = 2'b00; + assign _zz_387 = ((_zz_394 == _zz_395) != 1'b0); + assign _zz_388 = ({_zz_396,_zz_397} != 2'b00); + assign _zz_389 = {(_zz_398 != _zz_399),{_zz_400,{_zz_401,_zz_402}}}; + assign _zz_390 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_391 = 32'h00002000; + assign _zz_392 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_393 = 32'h00001000; + assign _zz_394 = (decode_INSTRUCTION & 32'h00004048); + assign _zz_395 = 32'h00004008; + assign _zz_396 = ((decode_INSTRUCTION & _zz_403) == 32'h00000020); + assign _zz_397 = ((decode_INSTRUCTION & _zz_404) == 32'h00000020); + assign _zz_398 = {(_zz_405 == _zz_406),{_zz_407,_zz_408}}; + assign _zz_399 = 3'b000; + assign _zz_400 = ((_zz_409 == _zz_410) != 1'b0); + assign _zz_401 = ({_zz_411,_zz_412} != 5'h0); + assign _zz_402 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; + assign _zz_403 = 32'h00000034; + assign _zz_404 = 32'h00000064; + assign _zz_405 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_406 = 32'h00000040; + assign _zz_407 = ((decode_INSTRUCTION & _zz_418) == 32'h0); + assign _zz_408 = ((decode_INSTRUCTION & _zz_419) == 32'h00000040); + assign _zz_409 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_410 = 32'h00000020; + assign _zz_411 = (_zz_420 == _zz_421); + assign _zz_412 = {_zz_88,{_zz_422,_zz_423}}; + assign _zz_413 = {_zz_88,{_zz_424,_zz_425}}; + assign _zz_414 = 5'h0; + assign _zz_415 = ({_zz_426,_zz_427} != 6'h0); + assign _zz_416 = (_zz_428 != _zz_429); + assign _zz_417 = {_zz_430,{_zz_431,_zz_432}}; + assign _zz_418 = 32'h00000038; + assign _zz_419 = 32'h00403040; + assign _zz_420 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_421 = 32'h00000040; + assign _zz_422 = (_zz_433 == _zz_434); + assign _zz_423 = {_zz_435,_zz_436}; + assign _zz_424 = (_zz_437 == _zz_438); + assign _zz_425 = {_zz_439,{_zz_440,_zz_441}}; + assign _zz_426 = _zz_89; + assign _zz_427 = {_zz_442,{_zz_443,_zz_444}}; + assign _zz_428 = {_zz_88,_zz_445}; + assign _zz_429 = 2'b00; + assign _zz_430 = ({_zz_446,_zz_447} != 2'b00); + assign _zz_431 = (_zz_448 != _zz_449); + assign _zz_432 = {_zz_450,{_zz_451,_zz_452}}; + assign _zz_433 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_434 = 32'h00004020; + assign _zz_435 = ((decode_INSTRUCTION & _zz_453) == 32'h00000010); + assign _zz_436 = ((decode_INSTRUCTION & _zz_454) == 32'h00000020); + assign _zz_437 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_438 = 32'h00002010; + assign _zz_439 = ((decode_INSTRUCTION & _zz_455) == 32'h00000010); + assign _zz_440 = (_zz_456 == _zz_457); + assign _zz_441 = (_zz_458 == _zz_459); + assign _zz_442 = ((decode_INSTRUCTION & _zz_460) == 32'h00001010); + assign _zz_443 = (_zz_461 == _zz_462); + assign _zz_444 = {_zz_463,{_zz_464,_zz_465}}; + assign _zz_445 = ((decode_INSTRUCTION & _zz_466) == 32'h00000020); + assign _zz_446 = _zz_88; + assign _zz_447 = (_zz_467 == _zz_468); + assign _zz_448 = (_zz_469 == _zz_470); + assign _zz_449 = 1'b0; + assign _zz_450 = (_zz_471 != 1'b0); + assign _zz_451 = (_zz_472 != _zz_473); + assign _zz_452 = {_zz_474,{_zz_475,_zz_476}}; + assign _zz_453 = 32'h00000030; + assign _zz_454 = 32'h02000020; + assign _zz_455 = 32'h00001030; + assign _zz_456 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_457 = 32'h00002020; + assign _zz_458 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_459 = 32'h00000020; + assign _zz_460 = 32'h00001010; + assign _zz_461 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_462 = 32'h00002010; + assign _zz_463 = ((decode_INSTRUCTION & _zz_477) == 32'h00000010); + assign _zz_464 = (_zz_478 == _zz_479); + assign _zz_465 = (_zz_480 == _zz_481); + assign _zz_466 = 32'h00000070; + assign _zz_467 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_468 = 32'h0; + assign _zz_469 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_470 = 32'h00004010; + assign _zz_471 = ((decode_INSTRUCTION & _zz_482) == 32'h00002010); + assign _zz_472 = {_zz_483,{_zz_484,_zz_485}}; + assign _zz_473 = 4'b0000; + assign _zz_474 = (_zz_486 != 1'b0); + assign _zz_475 = (_zz_487 != _zz_488); + assign _zz_476 = {_zz_489,{_zz_490,_zz_491}}; + assign _zz_477 = 32'h00000050; + assign _zz_478 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_479 = 32'h00000004; + assign _zz_480 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_481 = 32'h0; + assign _zz_482 = 32'h00006014; + assign _zz_483 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_484 = ((decode_INSTRUCTION & _zz_492) == 32'h0); + assign _zz_485 = {(_zz_493 == _zz_494),(_zz_495 == _zz_496)}; + assign _zz_486 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_487 = {(_zz_497 == _zz_498),{_zz_499,_zz_500}}; + assign _zz_488 = 3'b000; + assign _zz_489 = ({_zz_501,_zz_87} != 2'b00); + assign _zz_490 = ({_zz_502,_zz_503} != 2'b00); + assign _zz_491 = (_zz_504 != 1'b0); + assign _zz_492 = 32'h00000018; + assign _zz_493 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_494 = 32'h00002000; + assign _zz_495 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_496 = 32'h00001000; + assign _zz_497 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_498 = 32'h00000040; + assign _zz_499 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_500 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_501 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_502 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_503 = _zz_87; + assign _zz_504 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_505 = execute_INSTRUCTION[31]; + assign _zz_506 = execute_INSTRUCTION[31]; + assign _zz_507 = execute_INSTRUCTION[7]; always @ (posedge clk) begin - if(_zz_318) begin - _zz_188 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_323) begin + _zz_193 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_319) begin - _zz_189 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_324) begin + _zz_194 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1566,13 +1561,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_160 ), //i - .io_cpu_prefetch_isValid (_zz_161 ), //i + .io_flush (_zz_165 ), //i + .io_cpu_prefetch_isValid (_zz_166 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_162 ), //i - .io_cpu_fetch_isStuck (_zz_163 ), //i - .io_cpu_fetch_isRemoved (_zz_164 ), //i + .io_cpu_fetch_isValid (_zz_167 ), //i + .io_cpu_fetch_isStuck (_zz_168 ), //i + .io_cpu_fetch_isRemoved (_zz_169 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1585,8 +1580,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_165 ), //i - .io_cpu_decode_isStuck (_zz_166 ), //i + .io_cpu_decode_isValid (_zz_170 ), //i + .io_cpu_decode_isStuck (_zz_171 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1594,8 +1589,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_167 ), //i - .io_cpu_fill_valid (_zz_168 ), //i + .io_cpu_decode_isUser (_zz_172 ), //i + .io_cpu_fill_valid (_zz_173 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1608,20 +1603,20 @@ module VexRiscv ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_169 ), //i - .io_cpu_execute_address (_zz_170[31:0] ), //i + .io_cpu_execute_isValid (_zz_174 ), //i + .io_cpu_execute_address (_zz_175[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_81[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_171 ), //i + .io_cpu_memory_isValid (_zz_176 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_172[31:0] ), //i + .io_cpu_memory_address (_zz_177[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_173 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_178 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1629,31 +1624,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_174 ), //i + .io_cpu_writeBack_isValid (_zz_179 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_175 ), //i + .io_cpu_writeBack_isUser (_zz_180 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_176[31:0] ), //i + .io_cpu_writeBack_address (_zz_181[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_177 ), //i - .io_cpu_writeBack_fence_SR (_zz_178 ), //i - .io_cpu_writeBack_fence_SO (_zz_179 ), //i - .io_cpu_writeBack_fence_SI (_zz_180 ), //i - .io_cpu_writeBack_fence_PW (_zz_181 ), //i - .io_cpu_writeBack_fence_PR (_zz_182 ), //i - .io_cpu_writeBack_fence_PO (_zz_183 ), //i - .io_cpu_writeBack_fence_PI (_zz_184 ), //i - .io_cpu_writeBack_fence_FM (_zz_185[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_182 ), //i + .io_cpu_writeBack_fence_SR (_zz_183 ), //i + .io_cpu_writeBack_fence_SO (_zz_184 ), //i + .io_cpu_writeBack_fence_SI (_zz_185 ), //i + .io_cpu_writeBack_fence_PW (_zz_186 ), //i + .io_cpu_writeBack_fence_PR (_zz_187 ), //i + .io_cpu_writeBack_fence_PO (_zz_188 ), //i + .io_cpu_writeBack_fence_PI (_zz_189 ), //i + .io_cpu_writeBack_fence_FM (_zz_190[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_186 ), //i + .io_cpu_flush_valid (_zz_191 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_187 ), //i + .io_mem_cmd_ready (_zz_192 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1669,18 +1664,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_320) + case(_zz_325) 2'b00 : begin - _zz_190 = DBusCachedPlugin_redoBranch_payload; + _zz_195 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_190 = CsrPlugin_jumpInterface_payload; + _zz_195 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_190 = BranchPlugin_jumpInterface_payload; + _zz_195 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_190 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_195 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2353,7 +2348,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_226) + $signed(_zz_234)); + assign memory_MUL_LOW = ($signed(_zz_231) + $signed(_zz_239)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2361,38 +2356,38 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_236; + assign execute_SHIFT_RIGHT = _zz_241; assign execute_REGFILE_WRITE_DATA = _zz_99; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_170[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_175[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_238[0]; - assign decode_IS_RS1_SIGNED = _zz_239[0]; - assign decode_IS_DIV = _zz_240[0]; + assign decode_IS_RS2_SIGNED = _zz_243[0]; + assign decode_IS_RS1_SIGNED = _zz_244[0]; + assign decode_IS_DIV = _zz_245[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_241[0]; + assign decode_IS_MUL = _zz_246[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_242[0]; + assign decode_IS_CSR = _zz_247[0]; assign _zz_8 = _zz_9; assign _zz_10 = _zz_11; assign decode_SHIFT_CTRL = _zz_12; assign _zz_13 = _zz_14; assign decode_ALU_BITWISE_CTRL = _zz_15; assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_243[0]; - assign decode_MEMORY_MANAGMENT = _zz_244[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_248[0]; + assign decode_MEMORY_MANAGMENT = _zz_249[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_245[0]; + assign decode_MEMORY_WR = _zz_250[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_246[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_247[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_251[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_252[0]; assign decode_SRC2_CTRL = _zz_18; assign _zz_19 = _zz_20; assign decode_ALU_CTRL = _zz_21; @@ -2426,13 +2421,13 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_116; + assign execute_BRANCH_COND_RESULT = _zz_121; assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_248[0]; - assign decode_RS1_USE = _zz_249[0]; + assign decode_RS2_USE = _zz_253[0]; + assign decode_RS1_USE = _zz_254[0]; always @ (*) begin _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_191)begin + if(_zz_196)begin _zz_31 = execute_CsrPlugin_readData; end end @@ -2445,28 +2440,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_110)begin + if((_zz_111 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_112; end end - if(_zz_192)begin - if(_zz_193)begin - if(_zz_109)begin + if(_zz_197)begin + if(_zz_198)begin + if(_zz_114)begin decode_RS2 = _zz_50; end end end - if(_zz_194)begin + if(_zz_199)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_111)begin + if(_zz_116)begin decode_RS2 = _zz_32; end end end - if(_zz_195)begin + if(_zz_200)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_113)begin + if(_zz_118)begin decode_RS2 = _zz_31; end end @@ -2475,28 +2470,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_110)begin + if((_zz_111 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_112; end end - if(_zz_192)begin - if(_zz_193)begin - if(_zz_108)begin + if(_zz_197)begin + if(_zz_198)begin + if(_zz_113)begin decode_RS1 = _zz_50; end end end - if(_zz_194)begin + if(_zz_199)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_110)begin + if(_zz_115)begin decode_RS1 = _zz_32; end end end - if(_zz_195)begin + if(_zz_200)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_112)begin + if(_zz_117)begin decode_RS1 = _zz_31; end end @@ -2518,7 +2513,7 @@ module VexRiscv ( end endcase end - if(_zz_196)begin + if(_zz_201)begin _zz_32 = memory_DivPlugin_div_result; end end @@ -2531,8 +2526,8 @@ module VexRiscv ( assign _zz_35 = execute_PC; assign execute_SRC2_CTRL = _zz_36; assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_250[0]; - assign decode_SRC_ADD_ZERO = _zz_251[0]; + assign decode_SRC_USE_SUB_LESS = _zz_255[0]; + assign decode_SRC_ADD_ZERO = _zz_256[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_38; @@ -2550,25 +2545,25 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_252[0]; + decode_REGFILE_WRITE_VALID = _zz_257[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_321) == 32'h00001073),{(_zz_322 == _zz_323),{_zz_324,{_zz_325,_zz_326}}}}}}} != 21'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_326) == 32'h00001073),{(_zz_327 == _zz_328),{_zz_329,{_zz_330,_zz_331}}}}}}} != 21'h0); always @ (*) begin _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_225) + case(_zz_230) 2'b00 : begin - _zz_50 = _zz_294; + _zz_50 = _zz_299; end default : begin - _zz_50 = _zz_295; + _zz_50 = _zz_300; end endcase end @@ -2587,32 +2582,32 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_253[0]; - assign decode_FLUSH_ALL = _zz_254[0]; + assign decode_MEMORY_ENABLE = _zz_258[0]; + assign decode_FLUSH_ALL = _zz_259[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_197)begin + if(_zz_202)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_198)begin + if(_zz_203)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_199)begin + if(_zz_204)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_200)begin + if(_zz_205)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2645,7 +2640,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_108 || _zz_109)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2658,7 +2653,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_201)begin + if(_zz_206)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2672,17 +2667,17 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_201)begin + if(_zz_206)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_186 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_191 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_191)begin + if(_zz_196)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2716,7 +2711,7 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_196)begin + if(_zz_201)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2778,10 +2773,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_202)begin + if(_zz_207)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_203)begin + if(_zz_208)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2795,10 +2790,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_202)begin + if(_zz_207)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_203)begin + if(_zz_208)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -2814,21 +2809,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_202)begin + if(_zz_207)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_203)begin + if(_zz_208)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_202)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_207)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_203)begin - case(_zz_204) + if(_zz_208)begin + case(_zz_209) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2844,11 +2839,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_54 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_55 = (_zz_54 & (~ _zz_255)); + assign _zz_55 = (_zz_54 & (~ _zz_260)); assign _zz_56 = _zz_55[3]; assign _zz_57 = (_zz_55[1] || _zz_56); assign _zz_58 = (_zz_55[2] || _zz_56); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_190; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_195; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -2868,7 +2863,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_257); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_262); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -2959,7 +2954,7 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_68 = _zz_258[11]; + assign _zz_68 = _zz_263[11]; always @ (*) begin _zz_69[18] = _zz_68; _zz_69[17] = _zz_68; @@ -2983,13 +2978,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_259[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_264[31])); if(_zz_74)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_70 = _zz_260[19]; + assign _zz_70 = _zz_265[19]; always @ (*) begin _zz_71[10] = _zz_70; _zz_71[9] = _zz_70; @@ -3004,7 +2999,7 @@ module VexRiscv ( _zz_71[0] = _zz_70; end - assign _zz_72 = _zz_261[11]; + assign _zz_72 = _zz_266[11]; always @ (*) begin _zz_73[18] = _zz_72; _zz_73[17] = _zz_72; @@ -3030,16 +3025,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_74 = _zz_262[1]; + _zz_74 = _zz_267[1]; end default : begin - _zz_74 = _zz_263[1]; + _zz_74 = _zz_268[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_75 = _zz_264[19]; + assign _zz_75 = _zz_269[19]; always @ (*) begin _zz_76[10] = _zz_75; _zz_76[9] = _zz_75; @@ -3054,7 +3049,7 @@ module VexRiscv ( _zz_76[0] = _zz_75; end - assign _zz_77 = _zz_265[11]; + assign _zz_77 = _zz_270[11]; always @ (*) begin _zz_78[18] = _zz_77; _zz_78[17] = _zz_77; @@ -3077,7 +3072,7 @@ module VexRiscv ( _zz_78[0] = _zz_77; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_76,{{{_zz_339,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_78,{{{_zz_340,_zz_341},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_76,{{{_zz_344,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_78,{{{_zz_345,_zz_346},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3086,52 +3081,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_161 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_162 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_163 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_162; + assign _zz_166 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_167 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_168 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_167; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_165 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_166 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_167 = (CsrPlugin_privilege == 2'b00); + assign _zz_170 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_171 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_172 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_200)begin + if(_zz_205)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_198)begin + if(_zz_203)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_168 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_198)begin - _zz_168 = 1'b1; + _zz_173 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_203)begin + _zz_173 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_199)begin + if(_zz_204)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_197)begin + if(_zz_202)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_199)begin + if(_zz_204)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_197)begin + if(_zz_202)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3141,9 +3136,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_160 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_165 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_187 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_192 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3170,8 +3165,8 @@ module VexRiscv ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_169 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_170 = execute_SRC_ADD; + assign _zz_174 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_175 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3186,27 +3181,27 @@ module VexRiscv ( endcase end - assign _zz_186 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_171 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_172 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_171; + assign _zz_191 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_176 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_177 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_176; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_172; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_177; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_173 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_178 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_173 = 1'b1; + _zz_178 = 1'b1; end end - assign _zz_174 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_175 = (CsrPlugin_privilege == 2'b00); - assign _zz_176 = writeBack_REGFILE_WRITE_DATA; + assign _zz_179 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_180 = (CsrPlugin_privilege == 2'b00); + assign _zz_181 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_205)begin + if(_zz_210)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3216,7 +3211,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_205)begin + if(_zz_210)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3235,15 +3230,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_205)begin + if(_zz_210)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_266}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_271}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_267}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_272}; end end end @@ -3316,7 +3311,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_223) + case(_zz_228) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_83; end @@ -3351,7 +3346,7 @@ module VexRiscv ( assign _zz_88 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_89 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_90 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_86 = {(_zz_90 != 1'b0),{(_zz_90 != 1'b0),{((_zz_342 == _zz_343) != 1'b0),{(_zz_344 != 1'b0),{(_zz_345 != _zz_346),{_zz_347,{_zz_348,_zz_349}}}}}}}; + assign _zz_86 = {(_zz_90 != 1'b0),{(_zz_90 != 1'b0),{((_zz_347 == _zz_348) != 1'b0),{(_zz_349 != 1'b0),{(_zz_350 != _zz_351),{_zz_352,{_zz_353,_zz_354}}}}}}}; assign _zz_91 = _zz_86[2 : 1]; assign _zz_49 = _zz_91; assign _zz_92 = _zz_86[7 : 6]; @@ -3371,8 +3366,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_188; - assign decode_RegFilePlugin_rs2Data = _zz_189; + assign decode_RegFilePlugin_rs1Data = _zz_193; + assign decode_RegFilePlugin_rs2Data = _zz_194; always @ (*) begin lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); if(_zz_98)begin @@ -3414,7 +3409,7 @@ module VexRiscv ( _zz_99 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_99 = {31'd0, _zz_268}; + _zz_99 = {31'd0, _zz_273}; end default : begin _zz_99 = execute_SRC_ADD_SUB; @@ -3428,18 +3423,18 @@ module VexRiscv ( _zz_100 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_100 = {29'd0, _zz_269}; + _zz_100 = {29'd0, _zz_274}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_100 = {27'd0, _zz_270}; + _zz_100 = {27'd0, _zz_275}; end endcase end - assign _zz_101 = _zz_271[11]; + assign _zz_101 = _zz_276[11]; always @ (*) begin _zz_102[19] = _zz_101; _zz_102[18] = _zz_101; @@ -3463,7 +3458,7 @@ module VexRiscv ( _zz_102[0] = _zz_101; end - assign _zz_103 = _zz_272[11]; + assign _zz_103 = _zz_277[11]; always @ (*) begin _zz_104[19] = _zz_103; _zz_104[18] = _zz_103; @@ -3505,7 +3500,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_273; + execute_SrcPlugin_addSub = _zz_278; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3585,180 +3580,175 @@ module VexRiscv ( end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_206)begin - if(_zz_207)begin - if(_zz_108)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_108 = 1'b0; + if(_zz_211)begin + if(_zz_212)begin + if(_zz_113)begin + _zz_108 = 1'b1; end end end - if(_zz_208)begin - if(_zz_209)begin - if(_zz_110)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_213)begin + if(_zz_214)begin + if(_zz_115)begin + _zz_108 = 1'b1; end end end - if(_zz_210)begin - if(_zz_211)begin - if(_zz_112)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_215)begin + if(_zz_216)begin + if(_zz_117)begin + _zz_108 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_108 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_206)begin - if(_zz_207)begin - if(_zz_109)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_109 = 1'b0; + if(_zz_211)begin + if(_zz_212)begin + if(_zz_114)begin + _zz_109 = 1'b1; end end end - if(_zz_208)begin - if(_zz_209)begin - if(_zz_111)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_213)begin + if(_zz_214)begin + if(_zz_116)begin + _zz_109 = 1'b1; end end end - if(_zz_210)begin - if(_zz_211)begin - if(_zz_113)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_215)begin + if(_zz_216)begin + if(_zz_118)begin + _zz_109 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_109 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_108 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_109 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_110 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_111 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_112 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_113 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_113 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_114 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_115 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_116 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_117 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_118 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_114 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_114 == 3'b000)) begin - _zz_115 = execute_BranchPlugin_eq; - end else if((_zz_114 == 3'b001)) begin - _zz_115 = (! execute_BranchPlugin_eq); - end else if((((_zz_114 & 3'b101) == 3'b101))) begin - _zz_115 = (! execute_SRC_LESS); + assign _zz_119 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_119 == 3'b000)) begin + _zz_120 = execute_BranchPlugin_eq; + end else if((_zz_119 == 3'b001)) begin + _zz_120 = (! execute_BranchPlugin_eq); + end else if((((_zz_119 & 3'b101) == 3'b101))) begin + _zz_120 = (! execute_SRC_LESS); end else begin - _zz_115 = execute_SRC_LESS; + _zz_120 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_116 = 1'b0; + _zz_121 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_116 = 1'b1; + _zz_121 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_116 = 1'b1; + _zz_121 = 1'b1; end default : begin - _zz_116 = _zz_115; + _zz_121 = _zz_120; end endcase end - assign _zz_117 = _zz_280[11]; - always @ (*) begin - _zz_118[19] = _zz_117; - _zz_118[18] = _zz_117; - _zz_118[17] = _zz_117; - _zz_118[16] = _zz_117; - _zz_118[15] = _zz_117; - _zz_118[14] = _zz_117; - _zz_118[13] = _zz_117; - _zz_118[12] = _zz_117; - _zz_118[11] = _zz_117; - _zz_118[10] = _zz_117; - _zz_118[9] = _zz_117; - _zz_118[8] = _zz_117; - _zz_118[7] = _zz_117; - _zz_118[6] = _zz_117; - _zz_118[5] = _zz_117; - _zz_118[4] = _zz_117; - _zz_118[3] = _zz_117; - _zz_118[2] = _zz_117; - _zz_118[1] = _zz_117; - _zz_118[0] = _zz_117; - end - - assign _zz_119 = _zz_281[19]; - always @ (*) begin - _zz_120[10] = _zz_119; - _zz_120[9] = _zz_119; - _zz_120[8] = _zz_119; - _zz_120[7] = _zz_119; - _zz_120[6] = _zz_119; - _zz_120[5] = _zz_119; - _zz_120[4] = _zz_119; - _zz_120[3] = _zz_119; - _zz_120[2] = _zz_119; - _zz_120[1] = _zz_119; - _zz_120[0] = _zz_119; - end - - assign _zz_121 = _zz_282[11]; - always @ (*) begin - _zz_122[18] = _zz_121; - _zz_122[17] = _zz_121; - _zz_122[16] = _zz_121; - _zz_122[15] = _zz_121; - _zz_122[14] = _zz_121; - _zz_122[13] = _zz_121; - _zz_122[12] = _zz_121; - _zz_122[11] = _zz_121; - _zz_122[10] = _zz_121; - _zz_122[9] = _zz_121; - _zz_122[8] = _zz_121; - _zz_122[7] = _zz_121; - _zz_122[6] = _zz_121; - _zz_122[5] = _zz_121; - _zz_122[4] = _zz_121; - _zz_122[3] = _zz_121; - _zz_122[2] = _zz_121; - _zz_122[1] = _zz_121; - _zz_122[0] = _zz_121; + assign _zz_122 = _zz_285[11]; + always @ (*) begin + _zz_123[19] = _zz_122; + _zz_123[18] = _zz_122; + _zz_123[17] = _zz_122; + _zz_123[16] = _zz_122; + _zz_123[15] = _zz_122; + _zz_123[14] = _zz_122; + _zz_123[13] = _zz_122; + _zz_123[12] = _zz_122; + _zz_123[11] = _zz_122; + _zz_123[10] = _zz_122; + _zz_123[9] = _zz_122; + _zz_123[8] = _zz_122; + _zz_123[7] = _zz_122; + _zz_123[6] = _zz_122; + _zz_123[5] = _zz_122; + _zz_123[4] = _zz_122; + _zz_123[3] = _zz_122; + _zz_123[2] = _zz_122; + _zz_123[1] = _zz_122; + _zz_123[0] = _zz_122; + end + + assign _zz_124 = _zz_286[19]; + always @ (*) begin + _zz_125[10] = _zz_124; + _zz_125[9] = _zz_124; + _zz_125[8] = _zz_124; + _zz_125[7] = _zz_124; + _zz_125[6] = _zz_124; + _zz_125[5] = _zz_124; + _zz_125[4] = _zz_124; + _zz_125[3] = _zz_124; + _zz_125[2] = _zz_124; + _zz_125[1] = _zz_124; + _zz_125[0] = _zz_124; + end + + assign _zz_126 = _zz_287[11]; + always @ (*) begin + _zz_127[18] = _zz_126; + _zz_127[17] = _zz_126; + _zz_127[16] = _zz_126; + _zz_127[15] = _zz_126; + _zz_127[14] = _zz_126; + _zz_127[13] = _zz_126; + _zz_127[12] = _zz_126; + _zz_127[11] = _zz_126; + _zz_127[10] = _zz_126; + _zz_127[9] = _zz_126; + _zz_127[8] = _zz_126; + _zz_127[7] = _zz_126; + _zz_127[6] = _zz_126; + _zz_127[5] = _zz_126; + _zz_127[4] = _zz_126; + _zz_127[3] = _zz_126; + _zz_127[2] = _zz_126; + _zz_127[1] = _zz_126; + _zz_127[0] = _zz_126; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_123 = (_zz_283[1] ^ execute_RS1[1]); + _zz_128 = (_zz_288[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_123 = _zz_284[1]; + _zz_128 = _zz_289[1]; end default : begin - _zz_123 = _zz_285[1]; + _zz_128 = _zz_290[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_123); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_128); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -3770,80 +3760,80 @@ module VexRiscv ( endcase end - assign _zz_124 = _zz_286[11]; + assign _zz_129 = _zz_291[11]; always @ (*) begin - _zz_125[19] = _zz_124; - _zz_125[18] = _zz_124; - _zz_125[17] = _zz_124; - _zz_125[16] = _zz_124; - _zz_125[15] = _zz_124; - _zz_125[14] = _zz_124; - _zz_125[13] = _zz_124; - _zz_125[12] = _zz_124; - _zz_125[11] = _zz_124; - _zz_125[10] = _zz_124; - _zz_125[9] = _zz_124; - _zz_125[8] = _zz_124; - _zz_125[7] = _zz_124; - _zz_125[6] = _zz_124; - _zz_125[5] = _zz_124; - _zz_125[4] = _zz_124; - _zz_125[3] = _zz_124; - _zz_125[2] = _zz_124; - _zz_125[1] = _zz_124; - _zz_125[0] = _zz_124; + _zz_130[19] = _zz_129; + _zz_130[18] = _zz_129; + _zz_130[17] = _zz_129; + _zz_130[16] = _zz_129; + _zz_130[15] = _zz_129; + _zz_130[14] = _zz_129; + _zz_130[13] = _zz_129; + _zz_130[12] = _zz_129; + _zz_130[11] = _zz_129; + _zz_130[10] = _zz_129; + _zz_130[9] = _zz_129; + _zz_130[8] = _zz_129; + _zz_130[7] = _zz_129; + _zz_130[6] = _zz_129; + _zz_130[5] = _zz_129; + _zz_130[4] = _zz_129; + _zz_130[3] = _zz_129; + _zz_130[2] = _zz_129; + _zz_130[1] = _zz_129; + _zz_130[0] = _zz_129; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_125,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_130,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_127,{{{_zz_500,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_129,{{{_zz_501,_zz_502},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_132,{{{_zz_505,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_134,{{{_zz_506,_zz_507},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_289}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_294}; end end endcase end - assign _zz_126 = _zz_287[19]; - always @ (*) begin - _zz_127[10] = _zz_126; - _zz_127[9] = _zz_126; - _zz_127[8] = _zz_126; - _zz_127[7] = _zz_126; - _zz_127[6] = _zz_126; - _zz_127[5] = _zz_126; - _zz_127[4] = _zz_126; - _zz_127[3] = _zz_126; - _zz_127[2] = _zz_126; - _zz_127[1] = _zz_126; - _zz_127[0] = _zz_126; - end - - assign _zz_128 = _zz_288[11]; - always @ (*) begin - _zz_129[18] = _zz_128; - _zz_129[17] = _zz_128; - _zz_129[16] = _zz_128; - _zz_129[15] = _zz_128; - _zz_129[14] = _zz_128; - _zz_129[13] = _zz_128; - _zz_129[12] = _zz_128; - _zz_129[11] = _zz_128; - _zz_129[10] = _zz_128; - _zz_129[9] = _zz_128; - _zz_129[8] = _zz_128; - _zz_129[7] = _zz_128; - _zz_129[6] = _zz_128; - _zz_129[5] = _zz_128; - _zz_129[4] = _zz_128; - _zz_129[3] = _zz_128; - _zz_129[2] = _zz_128; - _zz_129[1] = _zz_128; - _zz_129[0] = _zz_128; + assign _zz_131 = _zz_292[19]; + always @ (*) begin + _zz_132[10] = _zz_131; + _zz_132[9] = _zz_131; + _zz_132[8] = _zz_131; + _zz_132[7] = _zz_131; + _zz_132[6] = _zz_131; + _zz_132[5] = _zz_131; + _zz_132[4] = _zz_131; + _zz_132[3] = _zz_131; + _zz_132[2] = _zz_131; + _zz_132[1] = _zz_131; + _zz_132[0] = _zz_131; + end + + assign _zz_133 = _zz_293[11]; + always @ (*) begin + _zz_134[18] = _zz_133; + _zz_134[17] = _zz_133; + _zz_134[16] = _zz_133; + _zz_134[15] = _zz_133; + _zz_134[14] = _zz_133; + _zz_134[13] = _zz_133; + _zz_134[12] = _zz_133; + _zz_134[11] = _zz_133; + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -3862,16 +3852,16 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_130 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_131 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_132 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_135 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_136 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_137 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_133 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_134 = _zz_290[0]; + assign _zz_138 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_139 = _zz_295[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_201)begin + if(_zz_206)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3953,7 +3943,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4007,7 +3997,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_212)begin + if(_zz_217)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4026,14 +4016,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_213)begin + if(_zz_218)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_213)begin + if(_zz_218)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4048,14 +4038,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_212)begin + if(_zz_217)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_212)begin + if(_zz_217)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4064,7 +4054,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_224) + case(_zz_229) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4078,7 +4068,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_214) + case(_zz_219) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4092,7 +4082,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_214) + case(_zz_219) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4111,12 +4101,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_292) + $signed(_zz_293)); + assign writeBack_MulPlugin_result = ($signed(_zz_297) + $signed(_zz_298)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_196)begin - if(_zz_215)begin + if(_zz_201)begin + if(_zz_220)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4124,7 +4114,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_216)begin + if(_zz_221)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4135,28 +4125,28 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_297); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_302); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_135 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_135[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_298); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_299 : _zz_300); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_301[31:0]; - assign _zz_136 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_137 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_138 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_140 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_140[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_303); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_304 : _zz_305); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_306[31:0]; + assign _zz_141 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_142 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_143 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_139[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_139[31 : 0] = execute_RS1; + _zz_144[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_144[31 : 0] = execute_RS1; end - assign _zz_141 = (_zz_140 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_141 != 32'h0); + assign _zz_146 = (_zz_145 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_146 != 32'h0); assign _zz_26 = decode_SRC1_CTRL; assign _zz_24 = _zz_49; assign _zz_37 = decode_to_execute_SRC1_CTRL; @@ -4205,116 +4195,116 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_142 = 32'h0; + _zz_147 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_142[12 : 0] = 13'h1000; - _zz_142[25 : 20] = 6'h20; + _zz_147[12 : 0] = 13'h1000; + _zz_147[25 : 20] = 6'h20; end end always @ (*) begin - _zz_143 = 32'h0; + _zz_148 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_143[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_143[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_143[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_148[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_148[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_148[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_144 = 32'h0; + _zz_149 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_144[11 : 11] = CsrPlugin_mip_MEIP; - _zz_144[7 : 7] = CsrPlugin_mip_MTIP; - _zz_144[3 : 3] = CsrPlugin_mip_MSIP; + _zz_149[11 : 11] = CsrPlugin_mip_MEIP; + _zz_149[7 : 7] = CsrPlugin_mip_MTIP; + _zz_149[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_145 = 32'h0; + _zz_150 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_145[11 : 11] = CsrPlugin_mie_MEIE; - _zz_145[7 : 7] = CsrPlugin_mie_MTIE; - _zz_145[3 : 3] = CsrPlugin_mie_MSIE; + _zz_150[11 : 11] = CsrPlugin_mie_MEIE; + _zz_150[7 : 7] = CsrPlugin_mie_MTIE; + _zz_150[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_146 = 32'h0; + _zz_151 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_146[31 : 0] = CsrPlugin_mepc; + _zz_151[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_147 = 32'h0; + _zz_152 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_147[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_147[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_152[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_152[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_148 = 32'h0; + _zz_153 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_148[31 : 0] = CsrPlugin_mtval; + _zz_153[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_149 = 32'h0; + _zz_154 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_149[31 : 0] = _zz_140; + _zz_154[31 : 0] = _zz_145; end end always @ (*) begin - _zz_150 = 32'h0; + _zz_155 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_150[31 : 0] = _zz_141; + _zz_155[31 : 0] = _zz_146; end end - assign execute_CsrPlugin_readData = ((((_zz_142 | _zz_143) | (_zz_144 | _zz_145)) | ((_zz_146 | _zz_147) | (_zz_148 | _zz_149))) | _zz_150); - assign iBusWishbone_ADR = {_zz_317,_zz_151}; - assign iBusWishbone_CTI = ((_zz_151 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = ((((_zz_147 | _zz_148) | (_zz_149 | _zz_150)) | ((_zz_151 | _zz_152) | (_zz_153 | _zz_154))) | _zz_155); + assign iBusWishbone_ADR = {_zz_322,_zz_156}; + assign iBusWishbone_CTI = ((_zz_156 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_217)begin + if(_zz_222)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_217)begin + if(_zz_222)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_152; + assign iBus_rsp_valid = _zz_157; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_158 = (dBus_cmd_payload_length != 3'b000); - assign _zz_154 = dBus_cmd_valid; - assign _zz_156 = dBus_cmd_payload_wr; - assign _zz_157 = (_zz_153 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_155 && (_zz_156 || _zz_157)); - assign dBusWishbone_ADR = ((_zz_158 ? {{dBus_cmd_payload_address[31 : 5],_zz_153},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_158 ? (_zz_157 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_163 = (dBus_cmd_payload_length != 3'b000); + assign _zz_159 = dBus_cmd_valid; + assign _zz_161 = dBus_cmd_payload_wr; + assign _zz_162 = (_zz_158 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_160 && (_zz_161 || _zz_162)); + assign dBusWishbone_ADR = ((_zz_163 ? {{dBus_cmd_payload_address[31 : 5],_zz_158},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_163 ? (_zz_162 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_156 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_156; + assign dBusWishbone_SEL = (_zz_161 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_161; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_155 = (_zz_154 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_154; - assign dBusWishbone_STB = _zz_154; - assign dBus_rsp_valid = _zz_159; + assign _zz_160 = (_zz_159 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_159; + assign dBusWishbone_STB = _zz_159; + assign dBus_rsp_valid = _zz_164; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4337,7 +4327,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= _zz_80; DBusCachedPlugin_rspCounter <= 32'h0; _zz_98 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_110 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -4355,14 +4345,14 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_140 <= 32'h0; + _zz_145 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_151 <= 3'b000; - _zz_152 <= 1'b0; - _zz_153 <= 3'b000; - _zz_159 <= 1'b0; + _zz_156 <= 3'b000; + _zz_157 <= 1'b0; + _zz_158 <= 3'b000; + _zz_164 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -4443,7 +4433,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_218)begin + if(_zz_223)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -4453,7 +4443,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end _zz_98 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_110 <= (_zz_41 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4475,14 +4465,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_219)begin - if(_zz_220)begin + if(_zz_224)begin + if(_zz_225)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_221)begin + if(_zz_226)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_222)begin + if(_zz_227)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4506,7 +4496,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_202)begin + if(_zz_207)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4517,8 +4507,8 @@ module VexRiscv ( end endcase end - if(_zz_203)begin - case(_zz_204) + if(_zz_208)begin + case(_zz_209) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4528,7 +4518,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_132,{_zz_131,_zz_130}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_137,{_zz_136,_zz_135}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; @@ -4551,35 +4541,35 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_311[0]; - CsrPlugin_mstatus_MIE <= _zz_312[0]; + CsrPlugin_mstatus_MPIE <= _zz_316[0]; + CsrPlugin_mstatus_MIE <= _zz_317[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_314[0]; - CsrPlugin_mie_MTIE <= _zz_315[0]; - CsrPlugin_mie_MSIE <= _zz_316[0]; + CsrPlugin_mie_MEIE <= _zz_319[0]; + CsrPlugin_mie_MTIE <= _zz_320[0]; + CsrPlugin_mie_MSIE <= _zz_321[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_140 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_145 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_217)begin + if(_zz_222)begin if(iBusWishbone_ACK)begin - _zz_151 <= (_zz_151 + 3'b001); + _zz_156 <= (_zz_156 + 3'b001); end end - _zz_152 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_154 && _zz_155))begin - _zz_153 <= (_zz_153 + 3'b001); - if(_zz_157)begin - _zz_153 <= 3'b000; + _zz_157 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_159 && _zz_160))begin + _zz_158 <= (_zz_158 + 3'b001); + if(_zz_162)begin + _zz_158 <= 3'b000; end end - _zz_159 <= ((_zz_154 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_164 <= ((_zz_159 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -4593,7 +4583,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_218)begin + if(_zz_223)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -4611,8 +4601,8 @@ module VexRiscv ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_111 <= _zz_40[11 : 7]; + _zz_112 <= _zz_50; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -4620,9 +4610,9 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_201)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_134 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_134 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_206)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_139 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_139 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -4636,21 +4626,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_219)begin - if(_zz_220)begin + if(_zz_224)begin + if(_zz_225)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_221)begin + if(_zz_226)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_222)begin + if(_zz_227)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_202)begin + if(_zz_207)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4670,20 +4660,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_196)begin - if(_zz_215)begin + if(_zz_201)begin + if(_zz_220)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_302[31:0]; + memory_DivPlugin_div_result <= _zz_307[31:0]; end end end - if(_zz_216)begin + if(_zz_221)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_138 ? (~ _zz_139) : _zz_139) + _zz_308); - memory_DivPlugin_rs2 <= ((_zz_137 ? (~ execute_RS2) : execute_RS2) + _zz_310); - memory_DivPlugin_div_needRevert <= ((_zz_138 ^ (_zz_137 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_143 ? (~ _zz_144) : _zz_144) + _zz_313); + memory_DivPlugin_rs2 <= ((_zz_142 ? (~ execute_RS2) : execute_RS2) + _zz_315); + memory_DivPlugin_div_needRevert <= ((_zz_143 ^ (_zz_142 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -4904,7 +4894,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_313[0]; + CsrPlugin_mip_MSIP <= _zz_318[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5208,7 +5198,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_12)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -5222,7 +5212,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_12)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -5252,7 +5242,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -5279,7 +5269,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -5311,7 +5301,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -5321,7 +5311,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v index 54d517d..d5319fc 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -81,37 +81,37 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_163; - wire _zz_164; - wire _zz_165; - wire _zz_166; - wire _zz_167; wire _zz_168; wire _zz_169; wire _zz_170; - reg _zz_171; + wire _zz_171; wire _zz_172; - wire [31:0] _zz_173; + wire _zz_173; wire _zz_174; - wire [31:0] _zz_175; + wire _zz_175; reg _zz_176; wire _zz_177; - wire _zz_178; - wire [31:0] _zz_179; - wire _zz_180; - wire _zz_181; + wire [31:0] _zz_178; + wire _zz_179; + wire [31:0] _zz_180; + reg _zz_181; wire _zz_182; wire _zz_183; - wire _zz_184; + wire [31:0] _zz_184; wire _zz_185; wire _zz_186; wire _zz_187; - wire [3:0] _zz_188; + wire _zz_188; wire _zz_189; wire _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; + wire _zz_191; + wire _zz_192; + wire [3:0] _zz_193; + wire _zz_194; + wire _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -144,11 +144,6 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_194; - wire _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; wire _zz_199; wire _zz_200; wire _zz_201; @@ -160,46 +155,46 @@ module VexRiscv ( wire _zz_207; wire _zz_208; wire _zz_209; - wire [1:0] _zz_210; + wire _zz_210; wire _zz_211; wire _zz_212; wire _zz_213; wire _zz_214; - wire _zz_215; + wire [1:0] _zz_215; wire _zz_216; wire _zz_217; wire _zz_218; wire _zz_219; - wire [1:0] _zz_220; + wire _zz_220; wire _zz_221; wire _zz_222; - wire [5:0] _zz_223; + wire _zz_223; wire _zz_224; - wire _zz_225; + wire [1:0] _zz_225; wire _zz_226; wire _zz_227; - wire _zz_228; + wire [5:0] _zz_228; wire _zz_229; - wire [1:0] _zz_230; + wire _zz_230; wire _zz_231; - wire [1:0] _zz_232; - wire [51:0] _zz_233; - wire [51:0] _zz_234; - wire [51:0] _zz_235; - wire [32:0] _zz_236; - wire [51:0] _zz_237; - wire [49:0] _zz_238; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire [1:0] _zz_235; + wire _zz_236; + wire [1:0] _zz_237; + wire [51:0] _zz_238; wire [51:0] _zz_239; - wire [49:0] _zz_240; - wire [51:0] _zz_241; - wire [32:0] _zz_242; - wire [31:0] _zz_243; - wire [32:0] _zz_244; - wire [0:0] _zz_245; - wire [0:0] _zz_246; - wire [0:0] _zz_247; - wire [0:0] _zz_248; - wire [0:0] _zz_249; + wire [51:0] _zz_240; + wire [32:0] _zz_241; + wire [51:0] _zz_242; + wire [49:0] _zz_243; + wire [51:0] _zz_244; + wire [49:0] _zz_245; + wire [51:0] _zz_246; + wire [32:0] _zz_247; + wire [31:0] _zz_248; + wire [32:0] _zz_249; wire [0:0] _zz_250; wire [0:0] _zz_251; wire [0:0] _zz_252; @@ -213,254 +208,259 @@ module VexRiscv ( wire [0:0] _zz_260; wire [0:0] _zz_261; wire [0:0] _zz_262; - wire [3:0] _zz_263; - wire [2:0] _zz_264; - wire [31:0] _zz_265; - wire [11:0] _zz_266; - wire [31:0] _zz_267; - wire [19:0] _zz_268; - wire [11:0] _zz_269; + wire [0:0] _zz_263; + wire [0:0] _zz_264; + wire [0:0] _zz_265; + wire [0:0] _zz_266; + wire [0:0] _zz_267; + wire [3:0] _zz_268; + wire [2:0] _zz_269; wire [31:0] _zz_270; - wire [31:0] _zz_271; - wire [19:0] _zz_272; - wire [11:0] _zz_273; - wire [2:0] _zz_274; - wire [2:0] _zz_275; - wire [0:0] _zz_276; - wire [2:0] _zz_277; - wire [4:0] _zz_278; - wire [11:0] _zz_279; - wire [11:0] _zz_280; - wire [31:0] _zz_281; - wire [31:0] _zz_282; - wire [31:0] _zz_283; - wire [31:0] _zz_284; - wire [31:0] _zz_285; + wire [11:0] _zz_271; + wire [31:0] _zz_272; + wire [19:0] _zz_273; + wire [11:0] _zz_274; + wire [31:0] _zz_275; + wire [31:0] _zz_276; + wire [19:0] _zz_277; + wire [11:0] _zz_278; + wire [2:0] _zz_279; + wire [2:0] _zz_280; + wire [0:0] _zz_281; + wire [2:0] _zz_282; + wire [4:0] _zz_283; + wire [11:0] _zz_284; + wire [11:0] _zz_285; wire [31:0] _zz_286; wire [31:0] _zz_287; - wire [11:0] _zz_288; - wire [19:0] _zz_289; - wire [11:0] _zz_290; + wire [31:0] _zz_288; + wire [31:0] _zz_289; + wire [31:0] _zz_290; wire [31:0] _zz_291; wire [31:0] _zz_292; - wire [31:0] _zz_293; - wire [11:0] _zz_294; - wire [19:0] _zz_295; - wire [11:0] _zz_296; - wire [2:0] _zz_297; - wire [1:0] _zz_298; - wire [1:0] _zz_299; - wire [65:0] _zz_300; - wire [65:0] _zz_301; - wire [31:0] _zz_302; - wire [31:0] _zz_303; - wire [0:0] _zz_304; - wire [5:0] _zz_305; - wire [32:0] _zz_306; + wire [11:0] _zz_293; + wire [19:0] _zz_294; + wire [11:0] _zz_295; + wire [31:0] _zz_296; + wire [31:0] _zz_297; + wire [31:0] _zz_298; + wire [11:0] _zz_299; + wire [19:0] _zz_300; + wire [11:0] _zz_301; + wire [2:0] _zz_302; + wire [1:0] _zz_303; + wire [1:0] _zz_304; + wire [65:0] _zz_305; + wire [65:0] _zz_306; wire [31:0] _zz_307; wire [31:0] _zz_308; - wire [32:0] _zz_309; - wire [32:0] _zz_310; + wire [0:0] _zz_309; + wire [5:0] _zz_310; wire [32:0] _zz_311; - wire [32:0] _zz_312; - wire [0:0] _zz_313; + wire [31:0] _zz_312; + wire [31:0] _zz_313; wire [32:0] _zz_314; - wire [0:0] _zz_315; + wire [32:0] _zz_315; wire [32:0] _zz_316; - wire [0:0] _zz_317; - wire [31:0] _zz_318; - wire [0:0] _zz_319; + wire [32:0] _zz_317; + wire [0:0] _zz_318; + wire [32:0] _zz_319; wire [0:0] _zz_320; - wire [0:0] _zz_321; + wire [32:0] _zz_321; wire [0:0] _zz_322; - wire [0:0] _zz_323; + wire [31:0] _zz_323; wire [0:0] _zz_324; - wire [26:0] _zz_325; - wire _zz_326; - wire _zz_327; - wire [1:0] _zz_328; - wire [31:0] _zz_329; - wire [31:0] _zz_330; - wire [31:0] _zz_331; + wire [0:0] _zz_325; + wire [0:0] _zz_326; + wire [0:0] _zz_327; + wire [0:0] _zz_328; + wire [0:0] _zz_329; + wire [26:0] _zz_330; + wire _zz_331; wire _zz_332; - wire [0:0] _zz_333; - wire [13:0] _zz_334; + wire [1:0] _zz_333; + wire [31:0] _zz_334; wire [31:0] _zz_335; wire [31:0] _zz_336; - wire [31:0] _zz_337; - wire _zz_338; - wire [0:0] _zz_339; - wire [7:0] _zz_340; + wire _zz_337; + wire [0:0] _zz_338; + wire [13:0] _zz_339; + wire [31:0] _zz_340; wire [31:0] _zz_341; wire [31:0] _zz_342; - wire [31:0] _zz_343; - wire _zz_344; - wire [0:0] _zz_345; - wire [1:0] _zz_346; - wire _zz_347; - wire _zz_348; + wire _zz_343; + wire [0:0] _zz_344; + wire [7:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; wire _zz_349; - wire [31:0] _zz_350; - wire [0:0] _zz_351; - wire [0:0] _zz_352; + wire [0:0] _zz_350; + wire [1:0] _zz_351; + wire _zz_352; wire _zz_353; - wire [0:0] _zz_354; - wire [26:0] _zz_355; - wire [31:0] _zz_356; - wire [31:0] _zz_357; - wire [31:0] _zz_358; - wire _zz_359; - wire [1:0] _zz_360; - wire [1:0] _zz_361; - wire _zz_362; - wire [0:0] _zz_363; - wire [22:0] _zz_364; - wire [31:0] _zz_365; - wire [31:0] _zz_366; - wire [31:0] _zz_367; - wire [31:0] _zz_368; - wire _zz_369; - wire _zz_370; - wire [1:0] _zz_371; - wire [1:0] _zz_372; - wire _zz_373; - wire [0:0] _zz_374; - wire [19:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire [31:0] _zz_378; - wire [31:0] _zz_379; - wire _zz_380; - wire [0:0] _zz_381; - wire [0:0] _zz_382; - wire _zz_383; - wire [0:0] _zz_384; - wire [0:0] _zz_385; - wire _zz_386; + wire _zz_354; + wire [31:0] _zz_355; + wire [0:0] _zz_356; + wire [0:0] _zz_357; + wire _zz_358; + wire [0:0] _zz_359; + wire [26:0] _zz_360; + wire [31:0] _zz_361; + wire [31:0] _zz_362; + wire [31:0] _zz_363; + wire _zz_364; + wire [1:0] _zz_365; + wire [1:0] _zz_366; + wire _zz_367; + wire [0:0] _zz_368; + wire [22:0] _zz_369; + wire [31:0] _zz_370; + wire [31:0] _zz_371; + wire [31:0] _zz_372; + wire [31:0] _zz_373; + wire _zz_374; + wire _zz_375; + wire [1:0] _zz_376; + wire [1:0] _zz_377; + wire _zz_378; + wire [0:0] _zz_379; + wire [19:0] _zz_380; + wire [31:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire [31:0] _zz_384; + wire _zz_385; + wire [0:0] _zz_386; wire [0:0] _zz_387; - wire [16:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire [31:0] _zz_391; - wire [31:0] _zz_392; - wire [31:0] _zz_393; - wire [0:0] _zz_394; - wire [0:0] _zz_395; - wire [0:0] _zz_396; - wire [0:0] _zz_397; - wire _zz_398; + wire _zz_388; + wire [0:0] _zz_389; + wire [0:0] _zz_390; + wire _zz_391; + wire [0:0] _zz_392; + wire [16:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; wire [0:0] _zz_399; - wire [13:0] _zz_400; - wire [31:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [1:0] _zz_407; - wire [0:0] _zz_408; - wire [0:0] _zz_409; + wire [0:0] _zz_400; + wire [0:0] _zz_401; + wire [0:0] _zz_402; + wire _zz_403; + wire [0:0] _zz_404; + wire [13:0] _zz_405; + wire [31:0] _zz_406; + wire [31:0] _zz_407; + wire [31:0] _zz_408; + wire _zz_409; wire _zz_410; wire [0:0] _zz_411; - wire [10:0] _zz_412; - wire [31:0] _zz_413; - wire [31:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; + wire [1:0] _zz_412; + wire [0:0] _zz_413; + wire [0:0] _zz_414; + wire _zz_415; + wire [0:0] _zz_416; + wire [10:0] _zz_417; wire [31:0] _zz_418; - wire _zz_419; - wire [0:0] _zz_420; - wire [2:0] _zz_421; - wire [0:0] _zz_422; - wire [3:0] _zz_423; - wire [5:0] _zz_424; - wire [5:0] _zz_425; - wire _zz_426; + wire [31:0] _zz_419; + wire [31:0] _zz_420; + wire [31:0] _zz_421; + wire [31:0] _zz_422; + wire [31:0] _zz_423; + wire _zz_424; + wire [0:0] _zz_425; + wire [2:0] _zz_426; wire [0:0] _zz_427; - wire [7:0] _zz_428; - wire [31:0] _zz_429; - wire _zz_430; - wire [0:0] _zz_431; + wire [3:0] _zz_428; + wire [5:0] _zz_429; + wire [5:0] _zz_430; + wire _zz_431; wire [0:0] _zz_432; - wire _zz_433; - wire [0:0] _zz_434; - wire [1:0] _zz_435; + wire [7:0] _zz_433; + wire [31:0] _zz_434; + wire _zz_435; wire [0:0] _zz_436; - wire [3:0] _zz_437; - wire [0:0] _zz_438; + wire [0:0] _zz_437; + wire _zz_438; wire [0:0] _zz_439; wire [1:0] _zz_440; - wire [1:0] _zz_441; - wire _zz_442; + wire [0:0] _zz_441; + wire [3:0] _zz_442; wire [0:0] _zz_443; - wire [5:0] _zz_444; - wire [31:0] _zz_445; - wire [31:0] _zz_446; - wire [31:0] _zz_447; - wire [31:0] _zz_448; - wire [31:0] _zz_449; + wire [0:0] _zz_444; + wire [1:0] _zz_445; + wire [1:0] _zz_446; + wire _zz_447; + wire [0:0] _zz_448; + wire [5:0] _zz_449; wire [31:0] _zz_450; wire [31:0] _zz_451; wire [31:0] _zz_452; - wire _zz_453; - wire _zz_454; + wire [31:0] _zz_453; + wire [31:0] _zz_454; wire [31:0] _zz_455; wire [31:0] _zz_456; - wire _zz_457; - wire [0:0] _zz_458; - wire [1:0] _zz_459; + wire [31:0] _zz_457; + wire _zz_458; + wire _zz_459; wire [31:0] _zz_460; wire [31:0] _zz_461; wire _zz_462; - wire _zz_463; - wire [0:0] _zz_464; - wire [0:0] _zz_465; - wire _zz_466; - wire [0:0] _zz_467; - wire [3:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire [31:0] _zz_471; - wire [31:0] _zz_472; - wire [31:0] _zz_473; - wire _zz_474; - wire _zz_475; + wire [0:0] _zz_463; + wire [1:0] _zz_464; + wire [31:0] _zz_465; + wire [31:0] _zz_466; + wire _zz_467; + wire _zz_468; + wire [0:0] _zz_469; + wire [0:0] _zz_470; + wire _zz_471; + wire [0:0] _zz_472; + wire [3:0] _zz_473; + wire [31:0] _zz_474; + wire [31:0] _zz_475; wire [31:0] _zz_476; wire [31:0] _zz_477; wire [31:0] _zz_478; - wire [31:0] _zz_479; - wire [0:0] _zz_480; - wire [2:0] _zz_481; - wire [0:0] _zz_482; - wire [0:0] _zz_483; - wire _zz_484; + wire _zz_479; + wire _zz_480; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; wire [0:0] _zz_485; - wire [1:0] _zz_486; - wire [31:0] _zz_487; - wire [31:0] _zz_488; - wire [31:0] _zz_489; - wire _zz_490; - wire _zz_491; + wire [2:0] _zz_486; + wire [0:0] _zz_487; + wire [0:0] _zz_488; + wire _zz_489; + wire [0:0] _zz_490; + wire [1:0] _zz_491; wire [31:0] _zz_492; - wire _zz_493; - wire [0:0] _zz_494; - wire [0:0] _zz_495; - wire [0:0] _zz_496; - wire [0:0] _zz_497; - wire [1:0] _zz_498; - wire [1:0] _zz_499; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire _zz_495; + wire _zz_496; + wire [31:0] _zz_497; + wire _zz_498; + wire [0:0] _zz_499; wire [0:0] _zz_500; wire [0:0] _zz_501; - wire [31:0] _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire [31:0] _zz_505; - wire [31:0] _zz_506; + wire [0:0] _zz_502; + wire [1:0] _zz_503; + wire [1:0] _zz_504; + wire [0:0] _zz_505; + wire [0:0] _zz_506; wire [31:0] _zz_507; - wire _zz_508; - wire _zz_509; - wire _zz_510; + wire [31:0] _zz_508; + wire [31:0] _zz_509; + wire [31:0] _zz_510; + wire [31:0] _zz_511; + wire [31:0] _zz_512; + wire _zz_513; + wire _zz_514; + wire _zz_515; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -943,42 +943,37 @@ module VexRiscv ( reg [31:0] _zz_107; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_108; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_109; - wire _zz_110; - wire _zz_111; - wire _zz_112; - wire _zz_113; + reg _zz_109; + reg _zz_110; + reg _zz_111; + reg [4:0] _zz_112; + reg [31:0] _zz_113; wire _zz_114; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_115; - reg _zz_116; - reg _zz_117; + wire _zz_115; + wire _zz_116; + wire _zz_117; wire _zz_118; - reg [19:0] _zz_119; - wire _zz_120; - reg [10:0] _zz_121; - wire _zz_122; - reg [18:0] _zz_123; - reg _zz_124; + wire _zz_119; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_120; + reg _zz_121; + reg _zz_122; + wire _zz_123; + reg [19:0] _zz_124; + wire _zz_125; + reg [10:0] _zz_126; + wire _zz_127; + reg [18:0] _zz_128; + reg _zz_129; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_125; - reg [19:0] _zz_126; - wire _zz_127; - reg [10:0] _zz_128; - wire _zz_129; - reg [18:0] _zz_130; + wire _zz_130; + reg [19:0] _zz_131; + wire _zz_132; + reg [10:0] _zz_133; + wire _zz_134; + reg [18:0] _zz_135; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; @@ -999,9 +994,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_131; - wire _zz_132; - wire _zz_133; + wire _zz_136; + wire _zz_137; + wire _zz_138; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1014,8 +1009,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_134; - wire _zz_135; + wire [1:0] _zz_139; + wire _zz_140; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1068,18 +1063,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_136; + wire [31:0] _zz_141; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_137; - wire _zz_138; - wire _zz_139; - reg [32:0] _zz_140; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_141; wire [31:0] _zz_142; + wire _zz_143; + wire _zz_144; + reg [32:0] _zz_145; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_146; + wire [31:0] _zz_147; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1089,7 +1084,7 @@ module VexRiscv ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_143; + reg _zz_148; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1155,7 +1150,7 @@ module VexRiscv ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_144; + reg [2:0] _zz_149; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_836; @@ -1166,25 +1161,25 @@ module VexRiscv ( reg execute_CsrPlugin_csr_835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_145; - reg [31:0] _zz_146; - reg [31:0] _zz_147; - reg [31:0] _zz_148; - reg [31:0] _zz_149; reg [31:0] _zz_150; reg [31:0] _zz_151; reg [31:0] _zz_152; reg [31:0] _zz_153; - reg [2:0] _zz_154; - reg _zz_155; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [2:0] _zz_159; + reg _zz_160; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_156; - wire _zz_157; - wire _zz_158; - wire _zz_159; - wire _zz_160; - wire _zz_161; - reg _zz_162; + reg [2:0] _zz_161; + wire _zz_162; + wire _zz_163; + wire _zz_164; + wire _zz_165; + wire _zz_166; + reg _zz_167; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] _zz_1_string; @@ -1269,332 +1264,332 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_194 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_195 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_196 = 1'b1; - assign _zz_197 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_198 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_199 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_200 = ((_zz_168 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_201 = ((_zz_168 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_202 = ((_zz_168 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_203 = ((_zz_168 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_204 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_205 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_206 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_207 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_208 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_209 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_210 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_211 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_212 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_213 = (1'b0 || (! 1'b1)); - assign _zz_214 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_215 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_216 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_217 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_218 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_219 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_220 = execute_INSTRUCTION[13 : 12]; - assign _zz_221 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_222 = (! memory_arbitration_isStuck); - assign _zz_223 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_224 = (iBus_cmd_valid || (_zz_154 != 3'b000)); - assign _zz_225 = (_zz_190 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_226 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_227 = ((_zz_131 && 1'b1) && (! 1'b0)); - assign _zz_228 = ((_zz_132 && 1'b1) && (! 1'b0)); - assign _zz_229 = ((_zz_133 && 1'b1) && (! 1'b0)); - assign _zz_230 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_231 = execute_INSTRUCTION[13]; - assign _zz_232 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_233 = ($signed(_zz_234) + $signed(_zz_239)); - assign _zz_234 = ($signed(_zz_235) + $signed(_zz_237)); - assign _zz_235 = 52'h0; - assign _zz_236 = {1'b0,memory_MUL_LL}; - assign _zz_237 = {{19{_zz_236[32]}}, _zz_236}; - assign _zz_238 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_239 = {{2{_zz_238[49]}}, _zz_238}; - assign _zz_240 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_241 = {{2{_zz_240[49]}}, _zz_240}; - assign _zz_242 = ($signed(_zz_244) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_243 = _zz_242[31 : 0]; - assign _zz_244 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_245 = _zz_87[31 : 31]; - assign _zz_246 = _zz_87[30 : 30]; - assign _zz_247 = _zz_87[29 : 29]; - assign _zz_248 = _zz_87[28 : 28]; - assign _zz_249 = _zz_87[25 : 25]; - assign _zz_250 = _zz_87[17 : 17]; - assign _zz_251 = _zz_87[16 : 16]; - assign _zz_252 = _zz_87[13 : 13]; - assign _zz_253 = _zz_87[12 : 12]; - assign _zz_254 = _zz_87[11 : 11]; - assign _zz_255 = _zz_87[32 : 32]; - assign _zz_256 = _zz_87[15 : 15]; - assign _zz_257 = _zz_87[5 : 5]; - assign _zz_258 = _zz_87[3 : 3]; - assign _zz_259 = _zz_87[20 : 20]; - assign _zz_260 = _zz_87[10 : 10]; - assign _zz_261 = _zz_87[4 : 4]; - assign _zz_262 = _zz_87[0 : 0]; - assign _zz_263 = (_zz_55 - 4'b0001); - assign _zz_264 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_265 = {29'd0, _zz_264}; - assign _zz_266 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_267 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_268 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_269 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_270 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_271 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_272 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_273 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_274 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_275 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_276 = execute_SRC_LESS; - assign _zz_277 = 3'b100; - assign _zz_278 = execute_INSTRUCTION[19 : 15]; - assign _zz_279 = execute_INSTRUCTION[31 : 20]; - assign _zz_280 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_281 = ($signed(_zz_282) + $signed(_zz_285)); - assign _zz_282 = ($signed(_zz_283) + $signed(_zz_284)); - assign _zz_283 = execute_SRC1; - assign _zz_284 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_285 = (execute_SRC_USE_SUB_LESS ? _zz_286 : _zz_287); - assign _zz_286 = 32'h00000001; - assign _zz_287 = 32'h0; - assign _zz_288 = execute_INSTRUCTION[31 : 20]; - assign _zz_289 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_290 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_291 = {_zz_119,execute_INSTRUCTION[31 : 20]}; - assign _zz_292 = {{_zz_121,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_293 = {{_zz_123,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_294 = execute_INSTRUCTION[31 : 20]; - assign _zz_295 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_296 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_297 = 3'b100; - assign _zz_298 = (_zz_134 & (~ _zz_299)); - assign _zz_299 = (_zz_134 - 2'b01); - assign _zz_300 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_301 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_302 = writeBack_MUL_LOW[31 : 0]; - assign _zz_303 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_304 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_305 = {5'd0, _zz_304}; - assign _zz_306 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_307 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_308 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_309 = {_zz_136,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_310 = _zz_311; - assign _zz_311 = _zz_312; - assign _zz_312 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_137) : _zz_137)} + _zz_314); - assign _zz_313 = memory_DivPlugin_div_needRevert; - assign _zz_314 = {32'd0, _zz_313}; - assign _zz_315 = _zz_139; - assign _zz_316 = {32'd0, _zz_315}; - assign _zz_317 = _zz_138; - assign _zz_318 = {31'd0, _zz_317}; - assign _zz_319 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_320 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_321 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_322 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_323 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_324 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_325 = (iBus_cmd_payload_address >>> 5); - assign _zz_326 = 1'b1; - assign _zz_327 = 1'b1; - assign _zz_328 = {_zz_59,_zz_58}; - assign _zz_329 = 32'h0000107f; - assign _zz_330 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_331 = 32'h00002073; - assign _zz_332 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_333 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_334 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_335) == 32'h00000003),{(_zz_336 == _zz_337),{_zz_338,{_zz_339,_zz_340}}}}}}; - assign _zz_335 = 32'h0000505f; - assign _zz_336 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_337 = 32'h00000063; - assign _zz_338 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_339 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_340 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_341) == 32'h00001013),{(_zz_342 == _zz_343),{_zz_344,{_zz_345,_zz_346}}}}}}; - assign _zz_341 = 32'hfc00307f; - assign _zz_342 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_343 = 32'h00005033; - assign _zz_344 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_345 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_346 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz_347 = decode_INSTRUCTION[31]; - assign _zz_348 = decode_INSTRUCTION[31]; - assign _zz_349 = decode_INSTRUCTION[7]; - assign _zz_350 = 32'h10103050; - assign _zz_351 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_352 = 1'b0; - assign _zz_353 = (((decode_INSTRUCTION & _zz_356) == 32'h02000030) != 1'b0); - assign _zz_354 = ((_zz_357 == _zz_358) != 1'b0); - assign _zz_355 = {(_zz_359 != 1'b0),{(_zz_360 != _zz_361),{_zz_362,{_zz_363,_zz_364}}}}; - assign _zz_356 = 32'h02004074; - assign _zz_357 = (decode_INSTRUCTION & 32'h10103050); - assign _zz_358 = 32'h00000050; - assign _zz_359 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); - assign _zz_360 = {(_zz_365 == _zz_366),(_zz_367 == _zz_368)}; - assign _zz_361 = 2'b00; - assign _zz_362 = ({_zz_90,_zz_369} != 2'b00); - assign _zz_363 = (_zz_370 != 1'b0); - assign _zz_364 = {(_zz_371 != _zz_372),{_zz_373,{_zz_374,_zz_375}}}; - assign _zz_365 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_366 = 32'h00001050; - assign _zz_367 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_368 = 32'h00002050; - assign _zz_369 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_370 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_371 = {(_zz_376 == _zz_377),(_zz_378 == _zz_379)}; - assign _zz_372 = 2'b00; - assign _zz_373 = ({_zz_380,{_zz_381,_zz_382}} != 3'b000); - assign _zz_374 = (_zz_383 != 1'b0); - assign _zz_375 = {(_zz_384 != _zz_385),{_zz_386,{_zz_387,_zz_388}}}; - assign _zz_376 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_377 = 32'h00005010; - assign _zz_378 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_379 = 32'h00005020; - assign _zz_380 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_381 = ((decode_INSTRUCTION & _zz_389) == 32'h00001010); - assign _zz_382 = ((decode_INSTRUCTION & _zz_390) == 32'h00001010); - assign _zz_383 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_384 = ((decode_INSTRUCTION & _zz_391) == 32'h00001000); - assign _zz_385 = 1'b0; - assign _zz_386 = ((_zz_392 == _zz_393) != 1'b0); - assign _zz_387 = ({_zz_394,_zz_395} != 2'b00); - assign _zz_388 = {(_zz_396 != _zz_397),{_zz_398,{_zz_399,_zz_400}}}; - assign _zz_389 = 32'h00007034; - assign _zz_390 = 32'h02007054; - assign _zz_391 = 32'h00001000; - assign _zz_392 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_393 = 32'h00002000; - assign _zz_394 = ((decode_INSTRUCTION & _zz_401) == 32'h00002000); - assign _zz_395 = ((decode_INSTRUCTION & _zz_402) == 32'h00001000); - assign _zz_396 = ((decode_INSTRUCTION & _zz_403) == 32'h00004008); - assign _zz_397 = 1'b0; - assign _zz_398 = ({_zz_404,_zz_405} != 2'b00); - assign _zz_399 = ({_zz_406,_zz_407} != 3'b000); - assign _zz_400 = {(_zz_408 != _zz_409),{_zz_410,{_zz_411,_zz_412}}}; - assign _zz_401 = 32'h00002010; - assign _zz_402 = 32'h00005000; - assign _zz_403 = 32'h00004048; - assign _zz_404 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); - assign _zz_405 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_406 = ((decode_INSTRUCTION & _zz_413) == 32'h00000040); - assign _zz_407 = {(_zz_414 == _zz_415),(_zz_416 == _zz_417)}; - assign _zz_408 = ((decode_INSTRUCTION & _zz_418) == 32'h00000020); - assign _zz_409 = 1'b0; - assign _zz_410 = ({_zz_419,{_zz_420,_zz_421}} != 5'h0); - assign _zz_411 = ({_zz_422,_zz_423} != 5'h0); - assign _zz_412 = {(_zz_424 != _zz_425),{_zz_426,{_zz_427,_zz_428}}}; - assign _zz_413 = 32'h00000050; - assign _zz_414 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_415 = 32'h0; - assign _zz_416 = (decode_INSTRUCTION & 32'h00103040); - assign _zz_417 = 32'h00000040; - assign _zz_418 = 32'h00000020; - assign _zz_419 = ((decode_INSTRUCTION & _zz_429) == 32'h00000040); - assign _zz_420 = _zz_89; - assign _zz_421 = {_zz_430,{_zz_431,_zz_432}}; - assign _zz_422 = _zz_89; - assign _zz_423 = {_zz_433,{_zz_434,_zz_435}}; - assign _zz_424 = {_zz_90,{_zz_436,_zz_437}}; - assign _zz_425 = 6'h0; - assign _zz_426 = ({_zz_438,_zz_439} != 2'b00); - assign _zz_427 = (_zz_440 != _zz_441); - assign _zz_428 = {_zz_442,{_zz_443,_zz_444}}; - assign _zz_429 = 32'h00000040; - assign _zz_430 = ((decode_INSTRUCTION & _zz_445) == 32'h00004020); - assign _zz_431 = (_zz_446 == _zz_447); - assign _zz_432 = (_zz_448 == _zz_449); - assign _zz_433 = ((decode_INSTRUCTION & _zz_450) == 32'h00002010); - assign _zz_434 = (_zz_451 == _zz_452); - assign _zz_435 = {_zz_453,_zz_454}; - assign _zz_436 = (_zz_455 == _zz_456); - assign _zz_437 = {_zz_457,{_zz_458,_zz_459}}; - assign _zz_438 = _zz_89; - assign _zz_439 = (_zz_460 == _zz_461); - assign _zz_440 = {_zz_89,_zz_462}; - assign _zz_441 = 2'b00; - assign _zz_442 = (_zz_463 != 1'b0); - assign _zz_443 = (_zz_464 != _zz_465); - assign _zz_444 = {_zz_466,{_zz_467,_zz_468}}; - assign _zz_445 = 32'h00004020; - assign _zz_446 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_447 = 32'h00000010; - assign _zz_448 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_449 = 32'h00000020; - assign _zz_450 = 32'h00002030; - assign _zz_451 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_199 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_200 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_201 = 1'b1; + assign _zz_202 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_203 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_204 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_205 = ((_zz_173 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_206 = ((_zz_173 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_207 = ((_zz_173 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_208 = ((_zz_173 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_209 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_210 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_211 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_212 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_213 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_214 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_215 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_216 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_217 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_218 = (1'b0 || (! 1'b1)); + assign _zz_219 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_220 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_221 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_222 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_223 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_224 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_225 = execute_INSTRUCTION[13 : 12]; + assign _zz_226 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_227 = (! memory_arbitration_isStuck); + assign _zz_228 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_229 = (iBus_cmd_valid || (_zz_159 != 3'b000)); + assign _zz_230 = (_zz_195 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_231 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_232 = ((_zz_136 && 1'b1) && (! 1'b0)); + assign _zz_233 = ((_zz_137 && 1'b1) && (! 1'b0)); + assign _zz_234 = ((_zz_138 && 1'b1) && (! 1'b0)); + assign _zz_235 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_236 = execute_INSTRUCTION[13]; + assign _zz_237 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_238 = ($signed(_zz_239) + $signed(_zz_244)); + assign _zz_239 = ($signed(_zz_240) + $signed(_zz_242)); + assign _zz_240 = 52'h0; + assign _zz_241 = {1'b0,memory_MUL_LL}; + assign _zz_242 = {{19{_zz_241[32]}}, _zz_241}; + assign _zz_243 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_244 = {{2{_zz_243[49]}}, _zz_243}; + assign _zz_245 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_246 = {{2{_zz_245[49]}}, _zz_245}; + assign _zz_247 = ($signed(_zz_249) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_248 = _zz_247[31 : 0]; + assign _zz_249 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_250 = _zz_87[31 : 31]; + assign _zz_251 = _zz_87[30 : 30]; + assign _zz_252 = _zz_87[29 : 29]; + assign _zz_253 = _zz_87[28 : 28]; + assign _zz_254 = _zz_87[25 : 25]; + assign _zz_255 = _zz_87[17 : 17]; + assign _zz_256 = _zz_87[16 : 16]; + assign _zz_257 = _zz_87[13 : 13]; + assign _zz_258 = _zz_87[12 : 12]; + assign _zz_259 = _zz_87[11 : 11]; + assign _zz_260 = _zz_87[32 : 32]; + assign _zz_261 = _zz_87[15 : 15]; + assign _zz_262 = _zz_87[5 : 5]; + assign _zz_263 = _zz_87[3 : 3]; + assign _zz_264 = _zz_87[20 : 20]; + assign _zz_265 = _zz_87[10 : 10]; + assign _zz_266 = _zz_87[4 : 4]; + assign _zz_267 = _zz_87[0 : 0]; + assign _zz_268 = (_zz_55 - 4'b0001); + assign _zz_269 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_270 = {29'd0, _zz_269}; + assign _zz_271 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_272 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_273 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_274 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_275 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_276 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_277 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_278 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_279 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_280 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_281 = execute_SRC_LESS; + assign _zz_282 = 3'b100; + assign _zz_283 = execute_INSTRUCTION[19 : 15]; + assign _zz_284 = execute_INSTRUCTION[31 : 20]; + assign _zz_285 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_286 = ($signed(_zz_287) + $signed(_zz_290)); + assign _zz_287 = ($signed(_zz_288) + $signed(_zz_289)); + assign _zz_288 = execute_SRC1; + assign _zz_289 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_290 = (execute_SRC_USE_SUB_LESS ? _zz_291 : _zz_292); + assign _zz_291 = 32'h00000001; + assign _zz_292 = 32'h0; + assign _zz_293 = execute_INSTRUCTION[31 : 20]; + assign _zz_294 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_295 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_296 = {_zz_124,execute_INSTRUCTION[31 : 20]}; + assign _zz_297 = {{_zz_126,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_298 = {{_zz_128,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_299 = execute_INSTRUCTION[31 : 20]; + assign _zz_300 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_301 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_302 = 3'b100; + assign _zz_303 = (_zz_139 & (~ _zz_304)); + assign _zz_304 = (_zz_139 - 2'b01); + assign _zz_305 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_306 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_307 = writeBack_MUL_LOW[31 : 0]; + assign _zz_308 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_309 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_310 = {5'd0, _zz_309}; + assign _zz_311 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_312 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_313 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_314 = {_zz_141,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_315 = _zz_316; + assign _zz_316 = _zz_317; + assign _zz_317 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_142) : _zz_142)} + _zz_319); + assign _zz_318 = memory_DivPlugin_div_needRevert; + assign _zz_319 = {32'd0, _zz_318}; + assign _zz_320 = _zz_144; + assign _zz_321 = {32'd0, _zz_320}; + assign _zz_322 = _zz_143; + assign _zz_323 = {31'd0, _zz_322}; + assign _zz_324 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_325 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_326 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_327 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_328 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_329 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_330 = (iBus_cmd_payload_address >>> 5); + assign _zz_331 = 1'b1; + assign _zz_332 = 1'b1; + assign _zz_333 = {_zz_59,_zz_58}; + assign _zz_334 = 32'h0000107f; + assign _zz_335 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_336 = 32'h00002073; + assign _zz_337 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_338 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_339 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_340) == 32'h00000003),{(_zz_341 == _zz_342),{_zz_343,{_zz_344,_zz_345}}}}}}; + assign _zz_340 = 32'h0000505f; + assign _zz_341 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_342 = 32'h00000063; + assign _zz_343 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_344 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_345 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_346) == 32'h00001013),{(_zz_347 == _zz_348),{_zz_349,{_zz_350,_zz_351}}}}}}; + assign _zz_346 = 32'hfc00307f; + assign _zz_347 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_348 = 32'h00005033; + assign _zz_349 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_350 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_351 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz_352 = decode_INSTRUCTION[31]; + assign _zz_353 = decode_INSTRUCTION[31]; + assign _zz_354 = decode_INSTRUCTION[7]; + assign _zz_355 = 32'h10103050; + assign _zz_356 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_357 = 1'b0; + assign _zz_358 = (((decode_INSTRUCTION & _zz_361) == 32'h02000030) != 1'b0); + assign _zz_359 = ((_zz_362 == _zz_363) != 1'b0); + assign _zz_360 = {(_zz_364 != 1'b0),{(_zz_365 != _zz_366),{_zz_367,{_zz_368,_zz_369}}}}; + assign _zz_361 = 32'h02004074; + assign _zz_362 = (decode_INSTRUCTION & 32'h10103050); + assign _zz_363 = 32'h00000050; + assign _zz_364 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz_365 = {(_zz_370 == _zz_371),(_zz_372 == _zz_373)}; + assign _zz_366 = 2'b00; + assign _zz_367 = ({_zz_90,_zz_374} != 2'b00); + assign _zz_368 = (_zz_375 != 1'b0); + assign _zz_369 = {(_zz_376 != _zz_377),{_zz_378,{_zz_379,_zz_380}}}; + assign _zz_370 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_371 = 32'h00001050; + assign _zz_372 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_373 = 32'h00002050; + assign _zz_374 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_375 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_376 = {(_zz_381 == _zz_382),(_zz_383 == _zz_384)}; + assign _zz_377 = 2'b00; + assign _zz_378 = ({_zz_385,{_zz_386,_zz_387}} != 3'b000); + assign _zz_379 = (_zz_388 != 1'b0); + assign _zz_380 = {(_zz_389 != _zz_390),{_zz_391,{_zz_392,_zz_393}}}; + assign _zz_381 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_382 = 32'h00005010; + assign _zz_383 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_384 = 32'h00005020; + assign _zz_385 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_386 = ((decode_INSTRUCTION & _zz_394) == 32'h00001010); + assign _zz_387 = ((decode_INSTRUCTION & _zz_395) == 32'h00001010); + assign _zz_388 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_389 = ((decode_INSTRUCTION & _zz_396) == 32'h00001000); + assign _zz_390 = 1'b0; + assign _zz_391 = ((_zz_397 == _zz_398) != 1'b0); + assign _zz_392 = ({_zz_399,_zz_400} != 2'b00); + assign _zz_393 = {(_zz_401 != _zz_402),{_zz_403,{_zz_404,_zz_405}}}; + assign _zz_394 = 32'h00007034; + assign _zz_395 = 32'h02007054; + assign _zz_396 = 32'h00001000; + assign _zz_397 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_398 = 32'h00002000; + assign _zz_399 = ((decode_INSTRUCTION & _zz_406) == 32'h00002000); + assign _zz_400 = ((decode_INSTRUCTION & _zz_407) == 32'h00001000); + assign _zz_401 = ((decode_INSTRUCTION & _zz_408) == 32'h00004008); + assign _zz_402 = 1'b0; + assign _zz_403 = ({_zz_409,_zz_410} != 2'b00); + assign _zz_404 = ({_zz_411,_zz_412} != 3'b000); + assign _zz_405 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; + assign _zz_406 = 32'h00002010; + assign _zz_407 = 32'h00005000; + assign _zz_408 = 32'h00004048; + assign _zz_409 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_410 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_411 = ((decode_INSTRUCTION & _zz_418) == 32'h00000040); + assign _zz_412 = {(_zz_419 == _zz_420),(_zz_421 == _zz_422)}; + assign _zz_413 = ((decode_INSTRUCTION & _zz_423) == 32'h00000020); + assign _zz_414 = 1'b0; + assign _zz_415 = ({_zz_424,{_zz_425,_zz_426}} != 5'h0); + assign _zz_416 = ({_zz_427,_zz_428} != 5'h0); + assign _zz_417 = {(_zz_429 != _zz_430),{_zz_431,{_zz_432,_zz_433}}}; + assign _zz_418 = 32'h00000050; + assign _zz_419 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_420 = 32'h0; + assign _zz_421 = (decode_INSTRUCTION & 32'h00103040); + assign _zz_422 = 32'h00000040; + assign _zz_423 = 32'h00000020; + assign _zz_424 = ((decode_INSTRUCTION & _zz_434) == 32'h00000040); + assign _zz_425 = _zz_89; + assign _zz_426 = {_zz_435,{_zz_436,_zz_437}}; + assign _zz_427 = _zz_89; + assign _zz_428 = {_zz_438,{_zz_439,_zz_440}}; + assign _zz_429 = {_zz_90,{_zz_441,_zz_442}}; + assign _zz_430 = 6'h0; + assign _zz_431 = ({_zz_443,_zz_444} != 2'b00); + assign _zz_432 = (_zz_445 != _zz_446); + assign _zz_433 = {_zz_447,{_zz_448,_zz_449}}; + assign _zz_434 = 32'h00000040; + assign _zz_435 = ((decode_INSTRUCTION & _zz_450) == 32'h00004020); + assign _zz_436 = (_zz_451 == _zz_452); + assign _zz_437 = (_zz_453 == _zz_454); + assign _zz_438 = ((decode_INSTRUCTION & _zz_455) == 32'h00002010); + assign _zz_439 = (_zz_456 == _zz_457); + assign _zz_440 = {_zz_458,_zz_459}; + assign _zz_441 = (_zz_460 == _zz_461); + assign _zz_442 = {_zz_462,{_zz_463,_zz_464}}; + assign _zz_443 = _zz_89; + assign _zz_444 = (_zz_465 == _zz_466); + assign _zz_445 = {_zz_89,_zz_467}; + assign _zz_446 = 2'b00; + assign _zz_447 = (_zz_468 != 1'b0); + assign _zz_448 = (_zz_469 != _zz_470); + assign _zz_449 = {_zz_471,{_zz_472,_zz_473}}; + assign _zz_450 = 32'h00004020; + assign _zz_451 = (decode_INSTRUCTION & 32'h00000030); assign _zz_452 = 32'h00000010; - assign _zz_453 = ((decode_INSTRUCTION & _zz_469) == 32'h00002020); - assign _zz_454 = ((decode_INSTRUCTION & _zz_470) == 32'h00000020); - assign _zz_455 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_456 = 32'h00001010; - assign _zz_457 = ((decode_INSTRUCTION & _zz_471) == 32'h00002010); - assign _zz_458 = (_zz_472 == _zz_473); - assign _zz_459 = {_zz_474,_zz_475}; - assign _zz_460 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_461 = 32'h00000020; - assign _zz_462 = ((decode_INSTRUCTION & _zz_476) == 32'h0); - assign _zz_463 = ((decode_INSTRUCTION & _zz_477) == 32'h00004010); - assign _zz_464 = (_zz_478 == _zz_479); - assign _zz_465 = 1'b0; - assign _zz_466 = ({_zz_480,_zz_481} != 4'b0000); - assign _zz_467 = (_zz_482 != _zz_483); - assign _zz_468 = {_zz_484,{_zz_485,_zz_486}}; - assign _zz_469 = 32'h02002060; - assign _zz_470 = 32'h02003020; - assign _zz_471 = 32'h00002010; - assign _zz_472 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_473 = 32'h00000010; - assign _zz_474 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_475 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); - assign _zz_476 = 32'h00000020; - assign _zz_477 = 32'h00004014; - assign _zz_478 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_479 = 32'h00002010; - assign _zz_480 = ((decode_INSTRUCTION & _zz_487) == 32'h0); - assign _zz_481 = {(_zz_488 == _zz_489),{_zz_490,_zz_491}}; - assign _zz_482 = ((decode_INSTRUCTION & _zz_492) == 32'h0); - assign _zz_483 = 1'b0; - assign _zz_484 = ({_zz_493,{_zz_494,_zz_495}} != 3'b000); - assign _zz_485 = ({_zz_496,_zz_497} != 2'b00); - assign _zz_486 = {(_zz_498 != _zz_499),(_zz_500 != _zz_501)}; - assign _zz_487 = 32'h00000044; - assign _zz_488 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_489 = 32'h0; - assign _zz_490 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_491 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_492 = 32'h00000058; - assign _zz_493 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_494 = ((decode_INSTRUCTION & _zz_502) == 32'h00002010); - assign _zz_495 = ((decode_INSTRUCTION & _zz_503) == 32'h40000030); - assign _zz_496 = ((decode_INSTRUCTION & _zz_504) == 32'h00000004); - assign _zz_497 = _zz_88; - assign _zz_498 = {(_zz_505 == _zz_506),_zz_88}; - assign _zz_499 = 2'b00; - assign _zz_500 = ((decode_INSTRUCTION & _zz_507) == 32'h00001008); - assign _zz_501 = 1'b0; - assign _zz_502 = 32'h00002014; - assign _zz_503 = 32'h40000034; - assign _zz_504 = 32'h00000014; - assign _zz_505 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_506 = 32'h00000004; - assign _zz_507 = 32'h00005048; - assign _zz_508 = execute_INSTRUCTION[31]; - assign _zz_509 = execute_INSTRUCTION[31]; - assign _zz_510 = execute_INSTRUCTION[7]; + assign _zz_453 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_454 = 32'h00000020; + assign _zz_455 = 32'h00002030; + assign _zz_456 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_457 = 32'h00000010; + assign _zz_458 = ((decode_INSTRUCTION & _zz_474) == 32'h00002020); + assign _zz_459 = ((decode_INSTRUCTION & _zz_475) == 32'h00000020); + assign _zz_460 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_461 = 32'h00001010; + assign _zz_462 = ((decode_INSTRUCTION & _zz_476) == 32'h00002010); + assign _zz_463 = (_zz_477 == _zz_478); + assign _zz_464 = {_zz_479,_zz_480}; + assign _zz_465 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_466 = 32'h00000020; + assign _zz_467 = ((decode_INSTRUCTION & _zz_481) == 32'h0); + assign _zz_468 = ((decode_INSTRUCTION & _zz_482) == 32'h00004010); + assign _zz_469 = (_zz_483 == _zz_484); + assign _zz_470 = 1'b0; + assign _zz_471 = ({_zz_485,_zz_486} != 4'b0000); + assign _zz_472 = (_zz_487 != _zz_488); + assign _zz_473 = {_zz_489,{_zz_490,_zz_491}}; + assign _zz_474 = 32'h02002060; + assign _zz_475 = 32'h02003020; + assign _zz_476 = 32'h00002010; + assign _zz_477 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_478 = 32'h00000010; + assign _zz_479 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_480 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_481 = 32'h00000020; + assign _zz_482 = 32'h00004014; + assign _zz_483 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_484 = 32'h00002010; + assign _zz_485 = ((decode_INSTRUCTION & _zz_492) == 32'h0); + assign _zz_486 = {(_zz_493 == _zz_494),{_zz_495,_zz_496}}; + assign _zz_487 = ((decode_INSTRUCTION & _zz_497) == 32'h0); + assign _zz_488 = 1'b0; + assign _zz_489 = ({_zz_498,{_zz_499,_zz_500}} != 3'b000); + assign _zz_490 = ({_zz_501,_zz_502} != 2'b00); + assign _zz_491 = {(_zz_503 != _zz_504),(_zz_505 != _zz_506)}; + assign _zz_492 = 32'h00000044; + assign _zz_493 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_494 = 32'h0; + assign _zz_495 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_496 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_497 = 32'h00000058; + assign _zz_498 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_499 = ((decode_INSTRUCTION & _zz_507) == 32'h00002010); + assign _zz_500 = ((decode_INSTRUCTION & _zz_508) == 32'h40000030); + assign _zz_501 = ((decode_INSTRUCTION & _zz_509) == 32'h00000004); + assign _zz_502 = _zz_88; + assign _zz_503 = {(_zz_510 == _zz_511),_zz_88}; + assign _zz_504 = 2'b00; + assign _zz_505 = ((decode_INSTRUCTION & _zz_512) == 32'h00001008); + assign _zz_506 = 1'b0; + assign _zz_507 = 32'h00002014; + assign _zz_508 = 32'h40000034; + assign _zz_509 = 32'h00000014; + assign _zz_510 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_511 = 32'h00000004; + assign _zz_512 = 32'h00005048; + assign _zz_513 = execute_INSTRUCTION[31]; + assign _zz_514 = execute_INSTRUCTION[31]; + assign _zz_515 = execute_INSTRUCTION[7]; always @ (posedge clk) begin - if(_zz_326) begin - _zz_191 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_331) begin + _zz_196 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_327) begin - _zz_192 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_332) begin + _zz_197 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1605,13 +1600,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_163 ), //i - .io_cpu_prefetch_isValid (_zz_164 ), //i + .io_flush (_zz_168 ), //i + .io_cpu_prefetch_isValid (_zz_169 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_165 ), //i - .io_cpu_fetch_isStuck (_zz_166 ), //i - .io_cpu_fetch_isRemoved (_zz_167 ), //i + .io_cpu_fetch_isValid (_zz_170 ), //i + .io_cpu_fetch_isStuck (_zz_171 ), //i + .io_cpu_fetch_isRemoved (_zz_172 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1624,8 +1619,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_168 ), //i - .io_cpu_decode_isStuck (_zz_169 ), //i + .io_cpu_decode_isValid (_zz_173 ), //i + .io_cpu_decode_isStuck (_zz_174 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1633,8 +1628,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_170 ), //i - .io_cpu_fill_valid (_zz_171 ), //i + .io_cpu_decode_isUser (_zz_175 ), //i + .io_cpu_fill_valid (_zz_176 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1643,26 +1638,26 @@ module VexRiscv ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_144[2:0] ), //i + ._zz_9 (_zz_149[2:0] ), //i ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_172 ), //i - .io_cpu_execute_address (_zz_173[31:0] ), //i + .io_cpu_execute_isValid (_zz_177 ), //i + .io_cpu_execute_address (_zz_178[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_82[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_174 ), //i + .io_cpu_memory_isValid (_zz_179 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_175[31:0] ), //i + .io_cpu_memory_address (_zz_180[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_176 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_181 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1670,31 +1665,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_177 ), //i + .io_cpu_writeBack_isValid (_zz_182 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_178 ), //i + .io_cpu_writeBack_isUser (_zz_183 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_179[31:0] ), //i + .io_cpu_writeBack_address (_zz_184[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_180 ), //i - .io_cpu_writeBack_fence_SR (_zz_181 ), //i - .io_cpu_writeBack_fence_SO (_zz_182 ), //i - .io_cpu_writeBack_fence_SI (_zz_183 ), //i - .io_cpu_writeBack_fence_PW (_zz_184 ), //i - .io_cpu_writeBack_fence_PR (_zz_185 ), //i - .io_cpu_writeBack_fence_PO (_zz_186 ), //i - .io_cpu_writeBack_fence_PI (_zz_187 ), //i - .io_cpu_writeBack_fence_FM (_zz_188[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_185 ), //i + .io_cpu_writeBack_fence_SR (_zz_186 ), //i + .io_cpu_writeBack_fence_SO (_zz_187 ), //i + .io_cpu_writeBack_fence_SI (_zz_188 ), //i + .io_cpu_writeBack_fence_PW (_zz_189 ), //i + .io_cpu_writeBack_fence_PR (_zz_190 ), //i + .io_cpu_writeBack_fence_PO (_zz_191 ), //i + .io_cpu_writeBack_fence_PI (_zz_192 ), //i + .io_cpu_writeBack_fence_FM (_zz_193[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_189 ), //i + .io_cpu_flush_valid (_zz_194 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_190 ), //i + .io_mem_cmd_ready (_zz_195 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1710,18 +1705,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_328) + case(_zz_333) 2'b00 : begin - _zz_193 = DBusCachedPlugin_redoBranch_payload; + _zz_198 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_193 = CsrPlugin_jumpInterface_payload; + _zz_198 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_193 = BranchPlugin_jumpInterface_payload; + _zz_198 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_193 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_198 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2394,7 +2389,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_233) + $signed(_zz_241)); + assign memory_MUL_LOW = ($signed(_zz_238) + $signed(_zz_246)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2402,39 +2397,39 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_243; + assign execute_SHIFT_RIGHT = _zz_248; assign execute_REGFILE_WRITE_DATA = _zz_100; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_173[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_178[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_245[0]; - assign decode_IS_RS1_SIGNED = _zz_246[0]; - assign decode_IS_DIV = _zz_247[0]; + assign decode_IS_RS2_SIGNED = _zz_250[0]; + assign decode_IS_RS1_SIGNED = _zz_251[0]; + assign decode_IS_DIV = _zz_252[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_248[0]; + assign decode_IS_MUL = _zz_253[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_249[0]; + assign decode_IS_CSR = _zz_254[0]; assign _zz_8 = _zz_9; assign _zz_10 = _zz_11; assign decode_SHIFT_CTRL = _zz_12; assign _zz_13 = _zz_14; assign decode_ALU_BITWISE_CTRL = _zz_15; assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_250[0]; - assign decode_MEMORY_MANAGMENT = _zz_251[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_255[0]; + assign decode_MEMORY_MANAGMENT = _zz_256[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_252[0]; + assign decode_MEMORY_WR = _zz_257[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_253[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_254[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_258[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_259[0]; assign decode_SRC2_CTRL = _zz_18; assign _zz_19 = _zz_20; assign decode_ALU_CTRL = _zz_21; @@ -2448,7 +2443,7 @@ module VexRiscv ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_255[0]; + assign decode_IS_EBREAK = _zz_260[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2470,13 +2465,13 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_117; + assign execute_BRANCH_COND_RESULT = _zz_122; assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_256[0]; - assign decode_RS1_USE = _zz_257[0]; + assign decode_RS2_USE = _zz_261[0]; + assign decode_RS1_USE = _zz_262[0]; always @ (*) begin _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_194)begin + if(_zz_199)begin _zz_31 = execute_CsrPlugin_readData; end end @@ -2489,28 +2484,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_111)begin + if((_zz_112 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_113; end end - if(_zz_195)begin - if(_zz_196)begin - if(_zz_110)begin + if(_zz_200)begin + if(_zz_201)begin + if(_zz_115)begin decode_RS2 = _zz_50; end end end - if(_zz_197)begin + if(_zz_202)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_112)begin + if(_zz_117)begin decode_RS2 = _zz_32; end end end - if(_zz_198)begin + if(_zz_203)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_114)begin + if(_zz_119)begin decode_RS2 = _zz_31; end end @@ -2519,28 +2514,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_111)begin + if((_zz_112 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_113; end end - if(_zz_195)begin - if(_zz_196)begin - if(_zz_109)begin + if(_zz_200)begin + if(_zz_201)begin + if(_zz_114)begin decode_RS1 = _zz_50; end end end - if(_zz_197)begin + if(_zz_202)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_111)begin + if(_zz_116)begin decode_RS1 = _zz_32; end end end - if(_zz_198)begin + if(_zz_203)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_113)begin + if(_zz_118)begin decode_RS1 = _zz_31; end end @@ -2562,7 +2557,7 @@ module VexRiscv ( end endcase end - if(_zz_199)begin + if(_zz_204)begin _zz_32 = memory_DivPlugin_div_result; end end @@ -2575,8 +2570,8 @@ module VexRiscv ( assign _zz_35 = execute_PC; assign execute_SRC2_CTRL = _zz_36; assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_258[0]; - assign decode_SRC_ADD_ZERO = _zz_259[0]; + assign decode_SRC_USE_SUB_LESS = _zz_263[0]; + assign decode_SRC_ADD_ZERO = _zz_264[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_38; @@ -2594,25 +2589,25 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_260[0]; + decode_REGFILE_WRITE_VALID = _zz_265[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_329) == 32'h00001073),{(_zz_330 == _zz_331),{_zz_332,{_zz_333,_zz_334}}}}}}} != 21'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_334) == 32'h00001073),{(_zz_335 == _zz_336),{_zz_337,{_zz_338,_zz_339}}}}}}} != 21'h0); always @ (*) begin _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_232) + case(_zz_237) 2'b00 : begin - _zz_50 = _zz_302; + _zz_50 = _zz_307; end default : begin - _zz_50 = _zz_303; + _zz_50 = _zz_308; end endcase end @@ -2631,32 +2626,32 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_261[0]; - assign decode_FLUSH_ALL = _zz_262[0]; + assign decode_MEMORY_ENABLE = _zz_266[0]; + assign decode_FLUSH_ALL = _zz_267[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_200)begin + if(_zz_205)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_201)begin + if(_zz_206)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_202)begin + if(_zz_207)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_203)begin + if(_zz_208)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2685,7 +2680,7 @@ module VexRiscv ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_144) + case(_zz_149) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2696,7 +2691,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_109 || _zz_110)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2709,7 +2704,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_204)begin + if(_zz_209)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2723,17 +2718,17 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_204)begin + if(_zz_209)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_189 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_194 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_194)begin + if(_zz_199)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2745,7 +2740,7 @@ module VexRiscv ( if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_205)begin + if(_zz_210)begin execute_arbitration_haltByOther = 1'b1; end end @@ -2762,8 +2757,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_205)begin - if(_zz_206)begin + if(_zz_210)begin + if(_zz_211)begin execute_arbitration_flushIt = 1'b1; end end @@ -2774,8 +2769,8 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_205)begin - if(_zz_206)begin + if(_zz_210)begin + if(_zz_211)begin execute_arbitration_flushNext = 1'b1; end end @@ -2783,7 +2778,7 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_199)begin + if(_zz_204)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2845,10 +2840,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_207)begin + if(_zz_212)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_208)begin + if(_zz_213)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2862,21 +2857,21 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_207)begin + if(_zz_212)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_208)begin + if(_zz_213)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_205)begin - if(_zz_206)begin + if(_zz_210)begin + if(_zz_211)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_209)begin + if(_zz_214)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -2905,21 +2900,21 @@ module VexRiscv ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_207)begin + if(_zz_212)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_208)begin + if(_zz_213)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_207)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_212)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_208)begin - case(_zz_210) + if(_zz_213)begin + case(_zz_215) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2953,11 +2948,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_55 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_56 = (_zz_55 & (~ _zz_263)); + assign _zz_56 = (_zz_55 & (~ _zz_268)); assign _zz_57 = _zz_56[3]; assign _zz_58 = (_zz_56[1] || _zz_57); assign _zz_59 = (_zz_56[2] || _zz_57); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_193; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_198; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -2977,7 +2972,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_265); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_270); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3069,7 +3064,7 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_144) + case(_zz_149) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3081,7 +3076,7 @@ module VexRiscv ( endcase end - assign _zz_69 = _zz_266[11]; + assign _zz_69 = _zz_271[11]; always @ (*) begin _zz_70[18] = _zz_69; _zz_70[17] = _zz_69; @@ -3105,13 +3100,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_267[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_272[31])); if(_zz_75)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_71 = _zz_268[19]; + assign _zz_71 = _zz_273[19]; always @ (*) begin _zz_72[10] = _zz_71; _zz_72[9] = _zz_71; @@ -3126,7 +3121,7 @@ module VexRiscv ( _zz_72[0] = _zz_71; end - assign _zz_73 = _zz_269[11]; + assign _zz_73 = _zz_274[11]; always @ (*) begin _zz_74[18] = _zz_73; _zz_74[17] = _zz_73; @@ -3152,16 +3147,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_75 = _zz_270[1]; + _zz_75 = _zz_275[1]; end default : begin - _zz_75 = _zz_271[1]; + _zz_75 = _zz_276[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_76 = _zz_272[19]; + assign _zz_76 = _zz_277[19]; always @ (*) begin _zz_77[10] = _zz_76; _zz_77[9] = _zz_76; @@ -3176,7 +3171,7 @@ module VexRiscv ( _zz_77[0] = _zz_76; end - assign _zz_78 = _zz_273[11]; + assign _zz_78 = _zz_278[11]; always @ (*) begin _zz_79[18] = _zz_78; _zz_79[17] = _zz_78; @@ -3199,7 +3194,7 @@ module VexRiscv ( _zz_79[0] = _zz_78; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_77,{{{_zz_347,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_79,{{{_zz_348,_zz_349},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_77,{{{_zz_352,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_79,{{{_zz_353,_zz_354},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3208,52 +3203,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_164 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_165 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_166 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_165; + assign _zz_169 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_170 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_171 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_170; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_168 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_169 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_170 = (CsrPlugin_privilege == 2'b00); + assign _zz_173 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_174 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_175 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_203)begin + if(_zz_208)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_201)begin + if(_zz_206)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_171 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_201)begin - _zz_171 = 1'b1; + _zz_176 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_206)begin + _zz_176 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_202)begin + if(_zz_207)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_200)begin + if(_zz_205)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_202)begin + if(_zz_207)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_200)begin + if(_zz_205)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3263,9 +3258,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_163 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_168 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_190 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_195 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3292,8 +3287,8 @@ module VexRiscv ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_172 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_173 = execute_SRC_ADD; + assign _zz_177 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_178 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3308,27 +3303,27 @@ module VexRiscv ( endcase end - assign _zz_189 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_174 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_175 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_174; + assign _zz_194 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_179 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_180 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_179; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_175; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_180; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_176 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_181 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_54 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_176 = 1'b1; + _zz_181 = 1'b1; end end - assign _zz_177 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_178 = (CsrPlugin_privilege == 2'b00); - assign _zz_179 = writeBack_REGFILE_WRITE_DATA; + assign _zz_182 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_183 = (CsrPlugin_privilege == 2'b00); + assign _zz_184 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_211)begin + if(_zz_216)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3338,7 +3333,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_211)begin + if(_zz_216)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3357,15 +3352,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_211)begin + if(_zz_216)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_274}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_279}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_275}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_280}; end end end @@ -3438,7 +3433,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_230) + case(_zz_235) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_84; end @@ -3473,7 +3468,7 @@ module VexRiscv ( assign _zz_89 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_90 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_91 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_87 = {(((decode_INSTRUCTION & _zz_350) == 32'h00100050) != 1'b0),{(_zz_91 != 1'b0),{(_zz_91 != 1'b0),{(_zz_351 != _zz_352),{_zz_353,{_zz_354,_zz_355}}}}}}; + assign _zz_87 = {(((decode_INSTRUCTION & _zz_355) == 32'h00100050) != 1'b0),{(_zz_91 != 1'b0),{(_zz_91 != 1'b0),{(_zz_356 != _zz_357),{_zz_358,{_zz_359,_zz_360}}}}}}; assign _zz_92 = _zz_87[2 : 1]; assign _zz_49 = _zz_92; assign _zz_93 = _zz_87[7 : 6]; @@ -3493,8 +3488,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_191; - assign decode_RegFilePlugin_rs2Data = _zz_192; + assign decode_RegFilePlugin_rs1Data = _zz_196; + assign decode_RegFilePlugin_rs2Data = _zz_197; always @ (*) begin lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); if(_zz_99)begin @@ -3536,7 +3531,7 @@ module VexRiscv ( _zz_100 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_100 = {31'd0, _zz_276}; + _zz_100 = {31'd0, _zz_281}; end default : begin _zz_100 = execute_SRC_ADD_SUB; @@ -3550,18 +3545,18 @@ module VexRiscv ( _zz_101 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_101 = {29'd0, _zz_277}; + _zz_101 = {29'd0, _zz_282}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_101 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_101 = {27'd0, _zz_278}; + _zz_101 = {27'd0, _zz_283}; end endcase end - assign _zz_102 = _zz_279[11]; + assign _zz_102 = _zz_284[11]; always @ (*) begin _zz_103[19] = _zz_102; _zz_103[18] = _zz_102; @@ -3585,7 +3580,7 @@ module VexRiscv ( _zz_103[0] = _zz_102; end - assign _zz_104 = _zz_280[11]; + assign _zz_104 = _zz_285[11]; always @ (*) begin _zz_105[19] = _zz_104; _zz_105[18] = _zz_104; @@ -3627,7 +3622,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_281; + execute_SrcPlugin_addSub = _zz_286; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3707,180 +3702,175 @@ module VexRiscv ( end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_212)begin - if(_zz_213)begin - if(_zz_109)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_109 = 1'b0; + if(_zz_217)begin + if(_zz_218)begin + if(_zz_114)begin + _zz_109 = 1'b1; end end end - if(_zz_214)begin - if(_zz_215)begin - if(_zz_111)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_219)begin + if(_zz_220)begin + if(_zz_116)begin + _zz_109 = 1'b1; end end end - if(_zz_216)begin - if(_zz_217)begin - if(_zz_113)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_221)begin + if(_zz_222)begin + if(_zz_118)begin + _zz_109 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_109 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_212)begin - if(_zz_213)begin - if(_zz_110)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_110 = 1'b0; + if(_zz_217)begin + if(_zz_218)begin + if(_zz_115)begin + _zz_110 = 1'b1; end end end - if(_zz_214)begin - if(_zz_215)begin - if(_zz_112)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_219)begin + if(_zz_220)begin + if(_zz_117)begin + _zz_110 = 1'b1; end end end - if(_zz_216)begin - if(_zz_217)begin - if(_zz_114)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_221)begin + if(_zz_222)begin + if(_zz_119)begin + _zz_110 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_110 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_109 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_110 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_111 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_112 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_113 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_114 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_114 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_115 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_116 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_117 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_118 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_119 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_115 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_115 == 3'b000)) begin - _zz_116 = execute_BranchPlugin_eq; - end else if((_zz_115 == 3'b001)) begin - _zz_116 = (! execute_BranchPlugin_eq); - end else if((((_zz_115 & 3'b101) == 3'b101))) begin - _zz_116 = (! execute_SRC_LESS); + assign _zz_120 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_120 == 3'b000)) begin + _zz_121 = execute_BranchPlugin_eq; + end else if((_zz_120 == 3'b001)) begin + _zz_121 = (! execute_BranchPlugin_eq); + end else if((((_zz_120 & 3'b101) == 3'b101))) begin + _zz_121 = (! execute_SRC_LESS); end else begin - _zz_116 = execute_SRC_LESS; + _zz_121 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_117 = 1'b0; + _zz_122 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_117 = 1'b1; + _zz_122 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_117 = 1'b1; + _zz_122 = 1'b1; end default : begin - _zz_117 = _zz_116; + _zz_122 = _zz_121; end endcase end - assign _zz_118 = _zz_288[11]; - always @ (*) begin - _zz_119[19] = _zz_118; - _zz_119[18] = _zz_118; - _zz_119[17] = _zz_118; - _zz_119[16] = _zz_118; - _zz_119[15] = _zz_118; - _zz_119[14] = _zz_118; - _zz_119[13] = _zz_118; - _zz_119[12] = _zz_118; - _zz_119[11] = _zz_118; - _zz_119[10] = _zz_118; - _zz_119[9] = _zz_118; - _zz_119[8] = _zz_118; - _zz_119[7] = _zz_118; - _zz_119[6] = _zz_118; - _zz_119[5] = _zz_118; - _zz_119[4] = _zz_118; - _zz_119[3] = _zz_118; - _zz_119[2] = _zz_118; - _zz_119[1] = _zz_118; - _zz_119[0] = _zz_118; - end - - assign _zz_120 = _zz_289[19]; - always @ (*) begin - _zz_121[10] = _zz_120; - _zz_121[9] = _zz_120; - _zz_121[8] = _zz_120; - _zz_121[7] = _zz_120; - _zz_121[6] = _zz_120; - _zz_121[5] = _zz_120; - _zz_121[4] = _zz_120; - _zz_121[3] = _zz_120; - _zz_121[2] = _zz_120; - _zz_121[1] = _zz_120; - _zz_121[0] = _zz_120; - end - - assign _zz_122 = _zz_290[11]; - always @ (*) begin - _zz_123[18] = _zz_122; - _zz_123[17] = _zz_122; - _zz_123[16] = _zz_122; - _zz_123[15] = _zz_122; - _zz_123[14] = _zz_122; - _zz_123[13] = _zz_122; - _zz_123[12] = _zz_122; - _zz_123[11] = _zz_122; - _zz_123[10] = _zz_122; - _zz_123[9] = _zz_122; - _zz_123[8] = _zz_122; - _zz_123[7] = _zz_122; - _zz_123[6] = _zz_122; - _zz_123[5] = _zz_122; - _zz_123[4] = _zz_122; - _zz_123[3] = _zz_122; - _zz_123[2] = _zz_122; - _zz_123[1] = _zz_122; - _zz_123[0] = _zz_122; + assign _zz_123 = _zz_293[11]; + always @ (*) begin + _zz_124[19] = _zz_123; + _zz_124[18] = _zz_123; + _zz_124[17] = _zz_123; + _zz_124[16] = _zz_123; + _zz_124[15] = _zz_123; + _zz_124[14] = _zz_123; + _zz_124[13] = _zz_123; + _zz_124[12] = _zz_123; + _zz_124[11] = _zz_123; + _zz_124[10] = _zz_123; + _zz_124[9] = _zz_123; + _zz_124[8] = _zz_123; + _zz_124[7] = _zz_123; + _zz_124[6] = _zz_123; + _zz_124[5] = _zz_123; + _zz_124[4] = _zz_123; + _zz_124[3] = _zz_123; + _zz_124[2] = _zz_123; + _zz_124[1] = _zz_123; + _zz_124[0] = _zz_123; + end + + assign _zz_125 = _zz_294[19]; + always @ (*) begin + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; + end + + assign _zz_127 = _zz_295[11]; + always @ (*) begin + _zz_128[18] = _zz_127; + _zz_128[17] = _zz_127; + _zz_128[16] = _zz_127; + _zz_128[15] = _zz_127; + _zz_128[14] = _zz_127; + _zz_128[13] = _zz_127; + _zz_128[12] = _zz_127; + _zz_128[11] = _zz_127; + _zz_128[10] = _zz_127; + _zz_128[9] = _zz_127; + _zz_128[8] = _zz_127; + _zz_128[7] = _zz_127; + _zz_128[6] = _zz_127; + _zz_128[5] = _zz_127; + _zz_128[4] = _zz_127; + _zz_128[3] = _zz_127; + _zz_128[2] = _zz_127; + _zz_128[1] = _zz_127; + _zz_128[0] = _zz_127; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_124 = (_zz_291[1] ^ execute_RS1[1]); + _zz_129 = (_zz_296[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_124 = _zz_292[1]; + _zz_129 = _zz_297[1]; end default : begin - _zz_124 = _zz_293[1]; + _zz_129 = _zz_298[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_124); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_129); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -3892,80 +3882,80 @@ module VexRiscv ( endcase end - assign _zz_125 = _zz_294[11]; + assign _zz_130 = _zz_299[11]; always @ (*) begin - _zz_126[19] = _zz_125; - _zz_126[18] = _zz_125; - _zz_126[17] = _zz_125; - _zz_126[16] = _zz_125; - _zz_126[15] = _zz_125; - _zz_126[14] = _zz_125; - _zz_126[13] = _zz_125; - _zz_126[12] = _zz_125; - _zz_126[11] = _zz_125; - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; + _zz_131[19] = _zz_130; + _zz_131[18] = _zz_130; + _zz_131[17] = _zz_130; + _zz_131[16] = _zz_130; + _zz_131[15] = _zz_130; + _zz_131[14] = _zz_130; + _zz_131[13] = _zz_130; + _zz_131[12] = _zz_130; + _zz_131[11] = _zz_130; + _zz_131[10] = _zz_130; + _zz_131[9] = _zz_130; + _zz_131[8] = _zz_130; + _zz_131[7] = _zz_130; + _zz_131[6] = _zz_130; + _zz_131[5] = _zz_130; + _zz_131[4] = _zz_130; + _zz_131[3] = _zz_130; + _zz_131[2] = _zz_130; + _zz_131[1] = _zz_130; + _zz_131[0] = _zz_130; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_126,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_131,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_128,{{{_zz_508,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_130,{{{_zz_509,_zz_510},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_133,{{{_zz_513,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_135,{{{_zz_514,_zz_515},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_297}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_302}; end end endcase end - assign _zz_127 = _zz_295[19]; - always @ (*) begin - _zz_128[10] = _zz_127; - _zz_128[9] = _zz_127; - _zz_128[8] = _zz_127; - _zz_128[7] = _zz_127; - _zz_128[6] = _zz_127; - _zz_128[5] = _zz_127; - _zz_128[4] = _zz_127; - _zz_128[3] = _zz_127; - _zz_128[2] = _zz_127; - _zz_128[1] = _zz_127; - _zz_128[0] = _zz_127; - end - - assign _zz_129 = _zz_296[11]; - always @ (*) begin - _zz_130[18] = _zz_129; - _zz_130[17] = _zz_129; - _zz_130[16] = _zz_129; - _zz_130[15] = _zz_129; - _zz_130[14] = _zz_129; - _zz_130[13] = _zz_129; - _zz_130[12] = _zz_129; - _zz_130[11] = _zz_129; - _zz_130[10] = _zz_129; - _zz_130[9] = _zz_129; - _zz_130[8] = _zz_129; - _zz_130[7] = _zz_129; - _zz_130[6] = _zz_129; - _zz_130[5] = _zz_129; - _zz_130[4] = _zz_129; - _zz_130[3] = _zz_129; - _zz_130[2] = _zz_129; - _zz_130[1] = _zz_129; - _zz_130[0] = _zz_129; + assign _zz_132 = _zz_300[19]; + always @ (*) begin + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; + end + + assign _zz_134 = _zz_301[11]; + always @ (*) begin + _zz_135[18] = _zz_134; + _zz_135[17] = _zz_134; + _zz_135[16] = _zz_134; + _zz_135[15] = _zz_134; + _zz_135[14] = _zz_134; + _zz_135[13] = _zz_134; + _zz_135[12] = _zz_134; + _zz_135[11] = _zz_134; + _zz_135[10] = _zz_134; + _zz_135[9] = _zz_134; + _zz_135[8] = _zz_134; + _zz_135[7] = _zz_134; + _zz_135[6] = _zz_134; + _zz_135[5] = _zz_134; + _zz_135[4] = _zz_134; + _zz_135[3] = _zz_134; + _zz_135[2] = _zz_134; + _zz_135[1] = _zz_134; + _zz_135[0] = _zz_134; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -3984,16 +3974,16 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_131 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_132 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_133 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_136 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_137 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_138 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_134 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_135 = _zz_298[0]; + assign _zz_139 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_140 = _zz_303[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_204)begin + if(_zz_209)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4075,7 +4065,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4129,7 +4119,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_218)begin + if(_zz_223)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4148,14 +4138,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_219)begin + if(_zz_224)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_219)begin + if(_zz_224)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4170,14 +4160,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_218)begin + if(_zz_223)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_218)begin + if(_zz_223)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4186,7 +4176,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_231) + case(_zz_236) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4200,7 +4190,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_220) + case(_zz_225) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4214,7 +4204,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_220) + case(_zz_225) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4233,12 +4223,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_300) + $signed(_zz_301)); + assign writeBack_MulPlugin_result = ($signed(_zz_305) + $signed(_zz_306)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_199)begin - if(_zz_221)begin + if(_zz_204)begin + if(_zz_226)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4246,7 +4236,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_222)begin + if(_zz_227)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4257,32 +4247,32 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_305); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_310); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_136 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_136[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_306); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_307 : _zz_308); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_309[31:0]; - assign _zz_137 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_138 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_139 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_141 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_141[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_311); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_312 : _zz_313); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_314[31:0]; + assign _zz_142 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_143 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_144 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_140[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_140[31 : 0] = execute_RS1; + _zz_145[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_145[31 : 0] = execute_RS1; end - assign _zz_142 = (_zz_141 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_142 != 32'h0); + assign _zz_147 = (_zz_146 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_147 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_223) + case(_zz_228) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4296,7 +4286,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_143))begin + if((! _zz_148))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4308,7 +4298,7 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_223) + case(_zz_228) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4372,7 +4362,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_144) + case(_zz_149) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4382,116 +4372,116 @@ module VexRiscv ( end always @ (*) begin - _zz_145 = 32'h0; + _zz_150 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_145[12 : 0] = 13'h1000; - _zz_145[25 : 20] = 6'h20; + _zz_150[12 : 0] = 13'h1000; + _zz_150[25 : 20] = 6'h20; end end always @ (*) begin - _zz_146 = 32'h0; + _zz_151 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_146[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_146[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_146[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_151[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_151[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_151[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_147 = 32'h0; + _zz_152 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_147[11 : 11] = CsrPlugin_mip_MEIP; - _zz_147[7 : 7] = CsrPlugin_mip_MTIP; - _zz_147[3 : 3] = CsrPlugin_mip_MSIP; + _zz_152[11 : 11] = CsrPlugin_mip_MEIP; + _zz_152[7 : 7] = CsrPlugin_mip_MTIP; + _zz_152[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_148 = 32'h0; + _zz_153 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_148[11 : 11] = CsrPlugin_mie_MEIE; - _zz_148[7 : 7] = CsrPlugin_mie_MTIE; - _zz_148[3 : 3] = CsrPlugin_mie_MSIE; + _zz_153[11 : 11] = CsrPlugin_mie_MEIE; + _zz_153[7 : 7] = CsrPlugin_mie_MTIE; + _zz_153[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_149 = 32'h0; + _zz_154 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_149[31 : 0] = CsrPlugin_mepc; + _zz_154[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_150 = 32'h0; + _zz_155 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_150[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_150[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_155[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_155[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_151 = 32'h0; + _zz_156 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_151[31 : 0] = CsrPlugin_mtval; + _zz_156[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_152 = 32'h0; + _zz_157 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_152[31 : 0] = _zz_141; + _zz_157[31 : 0] = _zz_146; end end always @ (*) begin - _zz_153 = 32'h0; + _zz_158 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_153[31 : 0] = _zz_142; + _zz_158[31 : 0] = _zz_147; end end - assign execute_CsrPlugin_readData = ((((_zz_145 | _zz_146) | (_zz_147 | _zz_148)) | ((_zz_149 | _zz_150) | (_zz_151 | _zz_152))) | _zz_153); - assign iBusWishbone_ADR = {_zz_325,_zz_154}; - assign iBusWishbone_CTI = ((_zz_154 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = ((((_zz_150 | _zz_151) | (_zz_152 | _zz_153)) | ((_zz_154 | _zz_155) | (_zz_156 | _zz_157))) | _zz_158); + assign iBusWishbone_ADR = {_zz_330,_zz_159}; + assign iBusWishbone_CTI = ((_zz_159 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_224)begin + if(_zz_229)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_224)begin + if(_zz_229)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_155; + assign iBus_rsp_valid = _zz_160; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_161 = (dBus_cmd_payload_length != 3'b000); - assign _zz_157 = dBus_cmd_valid; - assign _zz_159 = dBus_cmd_payload_wr; - assign _zz_160 = (_zz_156 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_158 && (_zz_159 || _zz_160)); - assign dBusWishbone_ADR = ((_zz_161 ? {{dBus_cmd_payload_address[31 : 5],_zz_156},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_161 ? (_zz_160 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_166 = (dBus_cmd_payload_length != 3'b000); + assign _zz_162 = dBus_cmd_valid; + assign _zz_164 = dBus_cmd_payload_wr; + assign _zz_165 = (_zz_161 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_163 && (_zz_164 || _zz_165)); + assign dBusWishbone_ADR = ((_zz_166 ? {{dBus_cmd_payload_address[31 : 5],_zz_161},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_166 ? (_zz_165 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_159 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_159; + assign dBusWishbone_SEL = (_zz_164 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_164; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_158 = (_zz_157 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_157; - assign dBusWishbone_STB = _zz_157; - assign dBus_rsp_valid = _zz_162; + assign _zz_163 = (_zz_162 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_162; + assign dBusWishbone_STB = _zz_162; + assign dBus_rsp_valid = _zz_167; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4514,7 +4504,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= _zz_81; DBusCachedPlugin_rspCounter <= 32'h0; _zz_99 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_111 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -4532,15 +4522,15 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_141 <= 32'h0; + _zz_146 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_144 <= 3'b000; - _zz_154 <= 3'b000; - _zz_155 <= 1'b0; - _zz_156 <= 3'b000; - _zz_162 <= 1'b0; + _zz_149 <= 3'b000; + _zz_159 <= 3'b000; + _zz_160 <= 1'b0; + _zz_161 <= 3'b000; + _zz_167 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -4621,7 +4611,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_225)begin + if(_zz_230)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -4631,7 +4621,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end _zz_99 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_111 <= (_zz_41 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4653,14 +4643,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_226)begin - if(_zz_227)begin + if(_zz_231)begin + if(_zz_232)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_228)begin + if(_zz_233)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_229)begin + if(_zz_234)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4684,7 +4674,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_207)begin + if(_zz_212)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4695,8 +4685,8 @@ module VexRiscv ( end endcase end - if(_zz_208)begin - case(_zz_210) + if(_zz_213)begin + case(_zz_215) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4706,7 +4696,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_133,{_zz_132,_zz_131}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_138,{_zz_137,_zz_136}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; @@ -4726,25 +4716,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_144) + case(_zz_149) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_144 <= 3'b001; + _zz_149 <= 3'b001; end end 3'b001 : begin - _zz_144 <= 3'b010; + _zz_149 <= 3'b010; end 3'b010 : begin - _zz_144 <= 3'b011; + _zz_149 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_144 <= 3'b100; + _zz_149 <= 3'b100; end end 3'b100 : begin - _zz_144 <= 3'b000; + _zz_149 <= 3'b000; end default : begin end @@ -4752,35 +4742,35 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_319[0]; - CsrPlugin_mstatus_MIE <= _zz_320[0]; + CsrPlugin_mstatus_MPIE <= _zz_324[0]; + CsrPlugin_mstatus_MIE <= _zz_325[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_322[0]; - CsrPlugin_mie_MTIE <= _zz_323[0]; - CsrPlugin_mie_MSIE <= _zz_324[0]; + CsrPlugin_mie_MEIE <= _zz_327[0]; + CsrPlugin_mie_MTIE <= _zz_328[0]; + CsrPlugin_mie_MSIE <= _zz_329[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_141 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_224)begin + if(_zz_229)begin if(iBusWishbone_ACK)begin - _zz_154 <= (_zz_154 + 3'b001); + _zz_159 <= (_zz_159 + 3'b001); end end - _zz_155 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_157 && _zz_158))begin - _zz_156 <= (_zz_156 + 3'b001); - if(_zz_160)begin - _zz_156 <= 3'b000; + _zz_160 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_162 && _zz_163))begin + _zz_161 <= (_zz_161 + 3'b001); + if(_zz_165)begin + _zz_161 <= 3'b000; end end - _zz_162 <= ((_zz_157 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_167 <= ((_zz_162 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -4794,7 +4784,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_225)begin + if(_zz_230)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -4812,8 +4802,8 @@ module VexRiscv ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_112 <= _zz_40[11 : 7]; + _zz_113 <= _zz_50; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -4821,9 +4811,9 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_204)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_135 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_135 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_209)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_140 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_140 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -4837,21 +4827,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_226)begin - if(_zz_227)begin + if(_zz_231)begin + if(_zz_232)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_228)begin + if(_zz_233)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_229)begin + if(_zz_234)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_207)begin + if(_zz_212)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4871,20 +4861,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_199)begin - if(_zz_221)begin + if(_zz_204)begin + if(_zz_226)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_310[31:0]; + memory_DivPlugin_div_result <= _zz_315[31:0]; end end end - if(_zz_222)begin + if(_zz_227)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_139 ? (~ _zz_140) : _zz_140) + _zz_316); - memory_DivPlugin_rs2 <= ((_zz_138 ? (~ execute_RS2) : execute_RS2) + _zz_318); - memory_DivPlugin_div_needRevert <= ((_zz_139 ^ (_zz_138 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_144 ? (~ _zz_145) : _zz_145) + _zz_321); + memory_DivPlugin_rs2 <= ((_zz_143 ? (~ execute_RS2) : execute_RS2) + _zz_323); + memory_DivPlugin_div_needRevert <= ((_zz_144 ^ (_zz_143 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5108,7 +5098,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_321[0]; + CsrPlugin_mip_MSIP <= _zz_326[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5136,8 +5126,8 @@ module VexRiscv ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_50; end - _zz_143 <= debug_bus_cmd_payload_address[2]; - if(_zz_205)begin + _zz_148 <= debug_bus_cmd_payload_address[2]; + if(_zz_210)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -5155,7 +5145,7 @@ module VexRiscv ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_223) + case(_zz_228) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -5183,13 +5173,13 @@ module VexRiscv ( end endcase end - if(_zz_205)begin - if(_zz_206)begin + if(_zz_210)begin + if(_zz_211)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_209)begin + if(_zz_214)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end @@ -5483,7 +5473,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_12)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -5497,7 +5487,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_12)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -5527,7 +5517,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -5554,7 +5544,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -5586,7 +5576,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -5596,7 +5586,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v index 95dce32..ace5e1a 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -74,37 +74,37 @@ module VexRiscv ( input clk, input reset ); - wire _zz_174; - wire _zz_175; - wire _zz_176; - wire _zz_177; - wire _zz_178; wire _zz_179; wire _zz_180; wire _zz_181; - reg _zz_182; + wire _zz_182; wire _zz_183; - wire [31:0] _zz_184; + wire _zz_184; wire _zz_185; - wire [31:0] _zz_186; + wire _zz_186; reg _zz_187; wire _zz_188; - wire _zz_189; - wire [31:0] _zz_190; - wire _zz_191; - wire _zz_192; + wire [31:0] _zz_189; + wire _zz_190; + wire [31:0] _zz_191; + reg _zz_192; wire _zz_193; wire _zz_194; - wire _zz_195; + wire [31:0] _zz_195; wire _zz_196; wire _zz_197; wire _zz_198; - wire [3:0] _zz_199; + wire _zz_199; wire _zz_200; wire _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; + wire _zz_202; + wire _zz_203; + wire [3:0] _zz_204; + wire _zz_205; + wire _zz_206; + reg [31:0] _zz_207; + reg [31:0] _zz_208; + reg [31:0] _zz_209; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -137,11 +137,6 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_205; - wire _zz_206; - wire _zz_207; - wire _zz_208; - wire _zz_209; wire _zz_210; wire _zz_211; wire _zz_212; @@ -151,46 +146,46 @@ module VexRiscv ( wire _zz_216; wire _zz_217; wire _zz_218; - wire [1:0] _zz_219; + wire _zz_219; wire _zz_220; wire _zz_221; wire _zz_222; wire _zz_223; - wire _zz_224; + wire [1:0] _zz_224; wire _zz_225; wire _zz_226; wire _zz_227; wire _zz_228; wire _zz_229; - wire [1:0] _zz_230; + wire _zz_230; wire _zz_231; wire _zz_232; wire _zz_233; wire _zz_234; - wire _zz_235; + wire [1:0] _zz_235; wire _zz_236; wire _zz_237; wire _zz_238; - wire [1:0] _zz_239; + wire _zz_239; wire _zz_240; - wire [1:0] _zz_241; - wire [51:0] _zz_242; - wire [51:0] _zz_243; - wire [51:0] _zz_244; - wire [32:0] _zz_245; - wire [51:0] _zz_246; - wire [49:0] _zz_247; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire [1:0] _zz_244; + wire _zz_245; + wire [1:0] _zz_246; + wire [51:0] _zz_247; wire [51:0] _zz_248; - wire [49:0] _zz_249; - wire [51:0] _zz_250; - wire [32:0] _zz_251; - wire [31:0] _zz_252; - wire [32:0] _zz_253; - wire [0:0] _zz_254; - wire [0:0] _zz_255; - wire [0:0] _zz_256; - wire [0:0] _zz_257; - wire [0:0] _zz_258; + wire [51:0] _zz_249; + wire [32:0] _zz_250; + wire [51:0] _zz_251; + wire [49:0] _zz_252; + wire [51:0] _zz_253; + wire [49:0] _zz_254; + wire [51:0] _zz_255; + wire [32:0] _zz_256; + wire [31:0] _zz_257; + wire [32:0] _zz_258; wire [0:0] _zz_259; wire [0:0] _zz_260; wire [0:0] _zz_261; @@ -203,262 +198,267 @@ module VexRiscv ( wire [0:0] _zz_268; wire [0:0] _zz_269; wire [0:0] _zz_270; - wire [3:0] _zz_271; - wire [2:0] _zz_272; - wire [31:0] _zz_273; - wire [11:0] _zz_274; - wire [31:0] _zz_275; - wire [19:0] _zz_276; - wire [11:0] _zz_277; + wire [0:0] _zz_271; + wire [0:0] _zz_272; + wire [0:0] _zz_273; + wire [0:0] _zz_274; + wire [0:0] _zz_275; + wire [3:0] _zz_276; + wire [2:0] _zz_277; wire [31:0] _zz_278; - wire [31:0] _zz_279; - wire [19:0] _zz_280; - wire [11:0] _zz_281; - wire [2:0] _zz_282; - wire [2:0] _zz_283; - wire [0:0] _zz_284; - wire [2:0] _zz_285; - wire [4:0] _zz_286; - wire [11:0] _zz_287; - wire [11:0] _zz_288; - wire [31:0] _zz_289; - wire [31:0] _zz_290; - wire [31:0] _zz_291; - wire [31:0] _zz_292; - wire [31:0] _zz_293; + wire [11:0] _zz_279; + wire [31:0] _zz_280; + wire [19:0] _zz_281; + wire [11:0] _zz_282; + wire [31:0] _zz_283; + wire [31:0] _zz_284; + wire [19:0] _zz_285; + wire [11:0] _zz_286; + wire [2:0] _zz_287; + wire [2:0] _zz_288; + wire [0:0] _zz_289; + wire [2:0] _zz_290; + wire [4:0] _zz_291; + wire [11:0] _zz_292; + wire [11:0] _zz_293; wire [31:0] _zz_294; wire [31:0] _zz_295; - wire [11:0] _zz_296; - wire [19:0] _zz_297; - wire [11:0] _zz_298; + wire [31:0] _zz_296; + wire [31:0] _zz_297; + wire [31:0] _zz_298; wire [31:0] _zz_299; wire [31:0] _zz_300; - wire [31:0] _zz_301; - wire [11:0] _zz_302; - wire [19:0] _zz_303; - wire [11:0] _zz_304; - wire [2:0] _zz_305; - wire [1:0] _zz_306; - wire [1:0] _zz_307; - wire [65:0] _zz_308; - wire [65:0] _zz_309; - wire [31:0] _zz_310; - wire [31:0] _zz_311; - wire [0:0] _zz_312; - wire [5:0] _zz_313; - wire [32:0] _zz_314; + wire [11:0] _zz_301; + wire [19:0] _zz_302; + wire [11:0] _zz_303; + wire [31:0] _zz_304; + wire [31:0] _zz_305; + wire [31:0] _zz_306; + wire [11:0] _zz_307; + wire [19:0] _zz_308; + wire [11:0] _zz_309; + wire [2:0] _zz_310; + wire [1:0] _zz_311; + wire [1:0] _zz_312; + wire [65:0] _zz_313; + wire [65:0] _zz_314; wire [31:0] _zz_315; wire [31:0] _zz_316; - wire [32:0] _zz_317; - wire [32:0] _zz_318; + wire [0:0] _zz_317; + wire [5:0] _zz_318; wire [32:0] _zz_319; - wire [32:0] _zz_320; - wire [0:0] _zz_321; + wire [31:0] _zz_320; + wire [31:0] _zz_321; wire [32:0] _zz_322; - wire [0:0] _zz_323; + wire [32:0] _zz_323; wire [32:0] _zz_324; - wire [0:0] _zz_325; - wire [31:0] _zz_326; - wire [0:0] _zz_327; + wire [32:0] _zz_325; + wire [0:0] _zz_326; + wire [32:0] _zz_327; wire [0:0] _zz_328; - wire [0:0] _zz_329; + wire [32:0] _zz_329; wire [0:0] _zz_330; - wire [0:0] _zz_331; + wire [31:0] _zz_331; wire [0:0] _zz_332; wire [0:0] _zz_333; - wire [26:0] _zz_334; - wire _zz_335; - wire _zz_336; - wire [1:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire [31:0] _zz_340; + wire [0:0] _zz_334; + wire [0:0] _zz_335; + wire [0:0] _zz_336; + wire [0:0] _zz_337; + wire [0:0] _zz_338; + wire [26:0] _zz_339; + wire _zz_340; wire _zz_341; - wire [0:0] _zz_342; - wire [13:0] _zz_343; + wire [1:0] _zz_342; + wire [31:0] _zz_343; wire [31:0] _zz_344; wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire _zz_347; - wire [0:0] _zz_348; - wire [7:0] _zz_349; + wire _zz_346; + wire [0:0] _zz_347; + wire [13:0] _zz_348; + wire [31:0] _zz_349; wire [31:0] _zz_350; wire [31:0] _zz_351; - wire [31:0] _zz_352; - wire _zz_353; - wire [0:0] _zz_354; - wire [1:0] _zz_355; - wire _zz_356; - wire _zz_357; + wire _zz_352; + wire [0:0] _zz_353; + wire [7:0] _zz_354; + wire [31:0] _zz_355; + wire [31:0] _zz_356; + wire [31:0] _zz_357; wire _zz_358; - wire [31:0] _zz_359; - wire [31:0] _zz_360; + wire [0:0] _zz_359; + wire [1:0] _zz_360; wire _zz_361; - wire [0:0] _zz_362; - wire [0:0] _zz_363; - wire _zz_364; - wire [0:0] _zz_365; - wire [24:0] _zz_366; - wire [31:0] _zz_367; - wire _zz_368; + wire _zz_362; + wire _zz_363; + wire [31:0] _zz_364; + wire [31:0] _zz_365; + wire _zz_366; + wire [0:0] _zz_367; + wire [0:0] _zz_368; wire _zz_369; wire [0:0] _zz_370; - wire [0:0] _zz_371; - wire [0:0] _zz_372; - wire [0:0] _zz_373; + wire [24:0] _zz_371; + wire [31:0] _zz_372; + wire _zz_373; wire _zz_374; wire [0:0] _zz_375; - wire [20:0] _zz_376; - wire [31:0] _zz_377; - wire [31:0] _zz_378; + wire [0:0] _zz_376; + wire [0:0] _zz_377; + wire [0:0] _zz_378; wire _zz_379; - wire _zz_380; - wire [0:0] _zz_381; - wire [1:0] _zz_382; - wire [0:0] _zz_383; - wire [0:0] _zz_384; + wire [0:0] _zz_380; + wire [20:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire _zz_384; wire _zz_385; wire [0:0] _zz_386; - wire [17:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire [31:0] _zz_391; - wire [31:0] _zz_392; + wire [1:0] _zz_387; + wire [0:0] _zz_388; + wire [0:0] _zz_389; + wire _zz_390; + wire [0:0] _zz_391; + wire [17:0] _zz_392; wire [31:0] _zz_393; wire [31:0] _zz_394; wire [31:0] _zz_395; - wire _zz_396; - wire [1:0] _zz_397; - wire [1:0] _zz_398; - wire _zz_399; - wire [0:0] _zz_400; - wire [14:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire [31:0] _zz_405; - wire [31:0] _zz_406; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire [31:0] _zz_399; + wire [31:0] _zz_400; + wire _zz_401; + wire [1:0] _zz_402; + wire [1:0] _zz_403; + wire _zz_404; + wire [0:0] _zz_405; + wire [14:0] _zz_406; wire [31:0] _zz_407; - wire [0:0] _zz_408; - wire [0:0] _zz_409; - wire [4:0] _zz_410; - wire [4:0] _zz_411; - wire _zz_412; + wire [31:0] _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire [31:0] _zz_411; + wire [31:0] _zz_412; wire [0:0] _zz_413; - wire [11:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; - wire [31:0] _zz_418; - wire _zz_419; - wire [0:0] _zz_420; - wire [1:0] _zz_421; + wire [0:0] _zz_414; + wire [4:0] _zz_415; + wire [4:0] _zz_416; + wire _zz_417; + wire [0:0] _zz_418; + wire [11:0] _zz_419; + wire [31:0] _zz_420; + wire [31:0] _zz_421; wire [31:0] _zz_422; wire [31:0] _zz_423; - wire [0:0] _zz_424; - wire [3:0] _zz_425; - wire [4:0] _zz_426; - wire [4:0] _zz_427; - wire _zz_428; + wire _zz_424; + wire [0:0] _zz_425; + wire [1:0] _zz_426; + wire [31:0] _zz_427; + wire [31:0] _zz_428; wire [0:0] _zz_429; - wire [8:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire [31:0] _zz_433; - wire _zz_434; - wire _zz_435; + wire [3:0] _zz_430; + wire [4:0] _zz_431; + wire [4:0] _zz_432; + wire _zz_433; + wire [0:0] _zz_434; + wire [8:0] _zz_435; wire [31:0] _zz_436; wire [31:0] _zz_437; - wire [0:0] _zz_438; - wire [1:0] _zz_439; - wire [0:0] _zz_440; - wire [2:0] _zz_441; - wire [0:0] _zz_442; - wire [4:0] _zz_443; + wire [31:0] _zz_438; + wire _zz_439; + wire _zz_440; + wire [31:0] _zz_441; + wire [31:0] _zz_442; + wire [0:0] _zz_443; wire [1:0] _zz_444; - wire [1:0] _zz_445; - wire _zz_446; + wire [0:0] _zz_445; + wire [2:0] _zz_446; wire [0:0] _zz_447; - wire [6:0] _zz_448; - wire [31:0] _zz_449; - wire [31:0] _zz_450; - wire [31:0] _zz_451; - wire [31:0] _zz_452; - wire _zz_453; - wire _zz_454; + wire [4:0] _zz_448; + wire [1:0] _zz_449; + wire [1:0] _zz_450; + wire _zz_451; + wire [0:0] _zz_452; + wire [6:0] _zz_453; + wire [31:0] _zz_454; wire [31:0] _zz_455; wire [31:0] _zz_456; - wire _zz_457; - wire [0:0] _zz_458; - wire [0:0] _zz_459; - wire _zz_460; - wire [0:0] _zz_461; - wire [2:0] _zz_462; - wire _zz_463; + wire [31:0] _zz_457; + wire _zz_458; + wire _zz_459; + wire [31:0] _zz_460; + wire [31:0] _zz_461; + wire _zz_462; + wire [0:0] _zz_463; wire [0:0] _zz_464; - wire [0:0] _zz_465; + wire _zz_465; wire [0:0] _zz_466; - wire [0:0] _zz_467; + wire [2:0] _zz_467; wire _zz_468; wire [0:0] _zz_469; - wire [4:0] _zz_470; - wire [31:0] _zz_471; - wire [31:0] _zz_472; - wire [31:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; + wire [0:0] _zz_470; + wire [0:0] _zz_471; + wire [0:0] _zz_472; + wire _zz_473; + wire [0:0] _zz_474; + wire [4:0] _zz_475; wire [31:0] _zz_476; wire [31:0] _zz_477; wire [31:0] _zz_478; wire [31:0] _zz_479; wire [31:0] _zz_480; - wire _zz_481; - wire [0:0] _zz_482; - wire [0:0] _zz_483; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; wire [31:0] _zz_484; wire [31:0] _zz_485; - wire [31:0] _zz_486; - wire [31:0] _zz_487; - wire [31:0] _zz_488; - wire _zz_489; - wire [3:0] _zz_490; - wire [3:0] _zz_491; - wire _zz_492; - wire [0:0] _zz_493; - wire [2:0] _zz_494; - wire [31:0] _zz_495; - wire [31:0] _zz_496; - wire [31:0] _zz_497; - wire [31:0] _zz_498; - wire [31:0] _zz_499; + wire _zz_486; + wire [0:0] _zz_487; + wire [0:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; + wire [31:0] _zz_491; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire _zz_494; + wire [3:0] _zz_495; + wire [3:0] _zz_496; + wire _zz_497; + wire [0:0] _zz_498; + wire [2:0] _zz_499; wire [31:0] _zz_500; - wire _zz_501; - wire [0:0] _zz_502; - wire [1:0] _zz_503; - wire _zz_504; - wire [2:0] _zz_505; - wire [2:0] _zz_506; - wire _zz_507; - wire [0:0] _zz_508; - wire [0:0] _zz_509; - wire [31:0] _zz_510; - wire [31:0] _zz_511; - wire [31:0] _zz_512; - wire [31:0] _zz_513; - wire [31:0] _zz_514; + wire [31:0] _zz_501; + wire [31:0] _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire [31:0] _zz_505; + wire _zz_506; + wire [0:0] _zz_507; + wire [1:0] _zz_508; + wire _zz_509; + wire [2:0] _zz_510; + wire [2:0] _zz_511; + wire _zz_512; + wire [0:0] _zz_513; + wire [0:0] _zz_514; wire [31:0] _zz_515; wire [31:0] _zz_516; - wire _zz_517; - wire _zz_518; - wire _zz_519; - wire [0:0] _zz_520; - wire [0:0] _zz_521; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire [31:0] _zz_520; + wire [31:0] _zz_521; wire _zz_522; wire _zz_523; wire _zz_524; - wire _zz_525; - wire [31:0] _zz_526; + wire [0:0] _zz_525; + wire [0:0] _zz_526; + wire _zz_527; + wire _zz_528; + wire _zz_529; + wire _zz_530; + wire [31:0] _zz_531; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -934,42 +934,37 @@ module VexRiscv ( reg [31:0] _zz_106; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_107; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_108; - wire _zz_109; - wire _zz_110; - wire _zz_111; - wire _zz_112; + reg _zz_108; + reg _zz_109; + reg _zz_110; + reg [4:0] _zz_111; + reg [31:0] _zz_112; wire _zz_113; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_114; - reg _zz_115; - reg _zz_116; + wire _zz_114; + wire _zz_115; + wire _zz_116; wire _zz_117; - reg [19:0] _zz_118; - wire _zz_119; - reg [10:0] _zz_120; - wire _zz_121; - reg [18:0] _zz_122; - reg _zz_123; + wire _zz_118; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_119; + reg _zz_120; + reg _zz_121; + wire _zz_122; + reg [19:0] _zz_123; + wire _zz_124; + reg [10:0] _zz_125; + wire _zz_126; + reg [18:0] _zz_127; + reg _zz_128; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_124; - reg [19:0] _zz_125; - wire _zz_126; - reg [10:0] _zz_127; - wire _zz_128; - reg [18:0] _zz_129; + wire _zz_129; + reg [19:0] _zz_130; + wire _zz_131; + reg [10:0] _zz_132; + wire _zz_133; + reg [18:0] _zz_134; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -991,9 +986,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_130; - wire _zz_131; - wire _zz_132; + wire _zz_135; + wire _zz_136; + wire _zz_137; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1006,8 +1001,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_133; - wire _zz_134; + wire [1:0] _zz_138; + wire _zz_139; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1060,18 +1055,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_135; + wire [31:0] _zz_140; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_136; - wire _zz_137; - wire _zz_138; - reg [32:0] _zz_139; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_140; wire [31:0] _zz_141; + wire _zz_142; + wire _zz_143; + reg [32:0] _zz_144; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_145; + wire [31:0] _zz_146; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1158,11 +1153,6 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3202; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_142; - reg [31:0] _zz_143; - reg [31:0] _zz_144; - reg [31:0] _zz_145; - reg [31:0] _zz_146; reg [31:0] _zz_147; reg [31:0] _zz_148; reg [31:0] _zz_149; @@ -1181,16 +1171,21 @@ module VexRiscv ( reg [31:0] _zz_162; reg [31:0] _zz_163; reg [31:0] _zz_164; - reg [2:0] _zz_165; - reg _zz_166; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [2:0] _zz_170; + reg _zz_171; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_167; - wire _zz_168; - wire _zz_169; - wire _zz_170; - wire _zz_171; - wire _zz_172; - reg _zz_173; + reg [2:0] _zz_172; + wire _zz_173; + wire _zz_174; + wire _zz_175; + wire _zz_176; + wire _zz_177; + reg _zz_178; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] _zz_1_string; @@ -1275,337 +1270,337 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_205 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_206 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_207 = 1'b1; - assign _zz_208 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_209 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_210 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_211 = ((_zz_179 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_212 = ((_zz_179 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_213 = ((_zz_179 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_214 = ((_zz_179 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_215 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_216 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_217 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_218 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_219 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_220 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_221 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_222 = (1'b0 || (! 1'b1)); - assign _zz_223 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_224 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_225 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_226 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_227 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_228 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_229 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_230 = execute_INSTRUCTION[13 : 12]; - assign _zz_231 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_232 = (! memory_arbitration_isStuck); - assign _zz_233 = (iBus_cmd_valid || (_zz_165 != 3'b000)); - assign _zz_234 = (_zz_201 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_235 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_236 = ((_zz_130 && 1'b1) && (! 1'b0)); - assign _zz_237 = ((_zz_131 && 1'b1) && (! 1'b0)); - assign _zz_238 = ((_zz_132 && 1'b1) && (! 1'b0)); - assign _zz_239 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_240 = execute_INSTRUCTION[13]; - assign _zz_241 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_242 = ($signed(_zz_243) + $signed(_zz_248)); - assign _zz_243 = ($signed(_zz_244) + $signed(_zz_246)); - assign _zz_244 = 52'h0; - assign _zz_245 = {1'b0,memory_MUL_LL}; - assign _zz_246 = {{19{_zz_245[32]}}, _zz_245}; - assign _zz_247 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_248 = {{2{_zz_247[49]}}, _zz_247}; - assign _zz_249 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_250 = {{2{_zz_249[49]}}, _zz_249}; - assign _zz_251 = ($signed(_zz_253) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_252 = _zz_251[31 : 0]; - assign _zz_253 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_254 = _zz_86[31 : 31]; - assign _zz_255 = _zz_86[30 : 30]; - assign _zz_256 = _zz_86[29 : 29]; - assign _zz_257 = _zz_86[28 : 28]; - assign _zz_258 = _zz_86[25 : 25]; - assign _zz_259 = _zz_86[17 : 17]; - assign _zz_260 = _zz_86[16 : 16]; - assign _zz_261 = _zz_86[13 : 13]; - assign _zz_262 = _zz_86[12 : 12]; - assign _zz_263 = _zz_86[11 : 11]; - assign _zz_264 = _zz_86[15 : 15]; - assign _zz_265 = _zz_86[5 : 5]; - assign _zz_266 = _zz_86[3 : 3]; - assign _zz_267 = _zz_86[20 : 20]; - assign _zz_268 = _zz_86[10 : 10]; - assign _zz_269 = _zz_86[4 : 4]; - assign _zz_270 = _zz_86[0 : 0]; - assign _zz_271 = (_zz_54 - 4'b0001); - assign _zz_272 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_273 = {29'd0, _zz_272}; - assign _zz_274 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_275 = {{_zz_69,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_276 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_277 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_278 = {{_zz_71,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_279 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_280 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_281 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_282 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_283 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_284 = execute_SRC_LESS; - assign _zz_285 = 3'b100; - assign _zz_286 = execute_INSTRUCTION[19 : 15]; - assign _zz_287 = execute_INSTRUCTION[31 : 20]; - assign _zz_288 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_289 = ($signed(_zz_290) + $signed(_zz_293)); - assign _zz_290 = ($signed(_zz_291) + $signed(_zz_292)); - assign _zz_291 = execute_SRC1; - assign _zz_292 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_293 = (execute_SRC_USE_SUB_LESS ? _zz_294 : _zz_295); - assign _zz_294 = 32'h00000001; - assign _zz_295 = 32'h0; - assign _zz_296 = execute_INSTRUCTION[31 : 20]; - assign _zz_297 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_298 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_299 = {_zz_118,execute_INSTRUCTION[31 : 20]}; - assign _zz_300 = {{_zz_120,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_301 = {{_zz_122,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_302 = execute_INSTRUCTION[31 : 20]; - assign _zz_303 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_304 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_305 = 3'b100; - assign _zz_306 = (_zz_133 & (~ _zz_307)); - assign _zz_307 = (_zz_133 - 2'b01); - assign _zz_308 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_309 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_310 = writeBack_MUL_LOW[31 : 0]; - assign _zz_311 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_312 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_313 = {5'd0, _zz_312}; - assign _zz_314 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_315 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_316 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_317 = {_zz_135,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_318 = _zz_319; - assign _zz_319 = _zz_320; - assign _zz_320 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_136) : _zz_136)} + _zz_322); - assign _zz_321 = memory_DivPlugin_div_needRevert; - assign _zz_322 = {32'd0, _zz_321}; - assign _zz_323 = _zz_138; - assign _zz_324 = {32'd0, _zz_323}; - assign _zz_325 = _zz_137; - assign _zz_326 = {31'd0, _zz_325}; - assign _zz_327 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_328 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_329 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_330 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_331 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_332 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_333 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_334 = (iBus_cmd_payload_address >>> 5); - assign _zz_335 = 1'b1; - assign _zz_336 = 1'b1; - assign _zz_337 = {_zz_58,_zz_57}; - assign _zz_338 = 32'h0000107f; - assign _zz_339 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_340 = 32'h00002073; - assign _zz_341 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_342 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_343 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_344) == 32'h00000003),{(_zz_345 == _zz_346),{_zz_347,{_zz_348,_zz_349}}}}}}; - assign _zz_344 = 32'h0000505f; - assign _zz_345 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_346 = 32'h00000063; - assign _zz_347 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_348 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_349 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_350) == 32'h00001013),{(_zz_351 == _zz_352),{_zz_353,{_zz_354,_zz_355}}}}}}; - assign _zz_350 = 32'hfc00307f; - assign _zz_351 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_352 = 32'h00005033; - assign _zz_353 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_354 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_355 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; - assign _zz_356 = decode_INSTRUCTION[31]; - assign _zz_357 = decode_INSTRUCTION[31]; - assign _zz_358 = decode_INSTRUCTION[7]; - assign _zz_359 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_360 = 32'h02004020; - assign _zz_361 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_362 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); - assign _zz_363 = 1'b0; - assign _zz_364 = (((decode_INSTRUCTION & _zz_367) == 32'h00000050) != 1'b0); - assign _zz_365 = ({_zz_368,_zz_369} != 2'b00); - assign _zz_366 = {({_zz_370,_zz_371} != 2'b00),{(_zz_372 != _zz_373),{_zz_374,{_zz_375,_zz_376}}}}; - assign _zz_367 = 32'h00403050; - assign _zz_368 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_369 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_370 = _zz_89; - assign _zz_371 = ((decode_INSTRUCTION & _zz_377) == 32'h00000004); - assign _zz_372 = ((decode_INSTRUCTION & _zz_378) == 32'h00000040); - assign _zz_373 = 1'b0; - assign _zz_374 = ({_zz_379,_zz_380} != 2'b00); - assign _zz_375 = ({_zz_381,_zz_382} != 3'b000); - assign _zz_376 = {(_zz_383 != _zz_384),{_zz_385,{_zz_386,_zz_387}}}; - assign _zz_377 = 32'h0000001c; - assign _zz_378 = 32'h00000058; - assign _zz_379 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_380 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_381 = ((decode_INSTRUCTION & _zz_388) == 32'h40001010); - assign _zz_382 = {(_zz_389 == _zz_390),(_zz_391 == _zz_392)}; - assign _zz_383 = ((decode_INSTRUCTION & _zz_393) == 32'h00000024); - assign _zz_384 = 1'b0; - assign _zz_385 = ((_zz_394 == _zz_395) != 1'b0); - assign _zz_386 = (_zz_396 != 1'b0); - assign _zz_387 = {(_zz_397 != _zz_398),{_zz_399,{_zz_400,_zz_401}}}; - assign _zz_388 = 32'h40003054; - assign _zz_389 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_390 = 32'h00001010; - assign _zz_391 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_392 = 32'h00001010; - assign _zz_393 = 32'h00000064; - assign _zz_394 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_395 = 32'h00001000; - assign _zz_396 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_397 = {(_zz_402 == _zz_403),(_zz_404 == _zz_405)}; - assign _zz_398 = 2'b00; - assign _zz_399 = ((_zz_406 == _zz_407) != 1'b0); - assign _zz_400 = ({_zz_408,_zz_409} != 2'b00); - assign _zz_401 = {(_zz_410 != _zz_411),{_zz_412,{_zz_413,_zz_414}}}; - assign _zz_402 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_403 = 32'h00002000; - assign _zz_404 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_405 = 32'h00001000; - assign _zz_406 = (decode_INSTRUCTION & 32'h00004048); - assign _zz_407 = 32'h00004008; - assign _zz_408 = ((decode_INSTRUCTION & _zz_415) == 32'h00000020); - assign _zz_409 = ((decode_INSTRUCTION & _zz_416) == 32'h00000020); - assign _zz_410 = {(_zz_417 == _zz_418),{_zz_419,{_zz_420,_zz_421}}}; - assign _zz_411 = 5'h0; - assign _zz_412 = ((_zz_422 == _zz_423) != 1'b0); - assign _zz_413 = ({_zz_424,_zz_425} != 5'h0); - assign _zz_414 = {(_zz_426 != _zz_427),{_zz_428,{_zz_429,_zz_430}}}; - assign _zz_415 = 32'h00000034; - assign _zz_416 = 32'h00000064; - assign _zz_417 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_418 = 32'h00002040; - assign _zz_419 = ((decode_INSTRUCTION & _zz_431) == 32'h00001040); - assign _zz_420 = (_zz_432 == _zz_433); - assign _zz_421 = {_zz_434,_zz_435}; - assign _zz_422 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_423 = 32'h00000020; - assign _zz_424 = (_zz_436 == _zz_437); - assign _zz_425 = {_zz_88,{_zz_438,_zz_439}}; - assign _zz_426 = {_zz_88,{_zz_440,_zz_441}}; - assign _zz_427 = 5'h0; - assign _zz_428 = ({_zz_442,_zz_443} != 6'h0); - assign _zz_429 = (_zz_444 != _zz_445); - assign _zz_430 = {_zz_446,{_zz_447,_zz_448}}; - assign _zz_431 = 32'h00001040; - assign _zz_432 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_433 = 32'h00000040; - assign _zz_434 = ((decode_INSTRUCTION & _zz_449) == 32'h00000040); - assign _zz_435 = ((decode_INSTRUCTION & _zz_450) == 32'h0); - assign _zz_436 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_437 = 32'h00000040; - assign _zz_438 = (_zz_451 == _zz_452); - assign _zz_439 = {_zz_453,_zz_454}; - assign _zz_440 = (_zz_455 == _zz_456); - assign _zz_441 = {_zz_457,{_zz_458,_zz_459}}; - assign _zz_442 = _zz_89; - assign _zz_443 = {_zz_460,{_zz_461,_zz_462}}; - assign _zz_444 = {_zz_88,_zz_463}; - assign _zz_445 = 2'b00; - assign _zz_446 = ({_zz_464,_zz_465} != 2'b00); - assign _zz_447 = (_zz_466 != _zz_467); - assign _zz_448 = {_zz_468,{_zz_469,_zz_470}}; - assign _zz_449 = 32'h00400040; - assign _zz_450 = 32'h00000038; - assign _zz_451 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_452 = 32'h00004020; - assign _zz_453 = ((decode_INSTRUCTION & _zz_471) == 32'h00000010); - assign _zz_454 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); - assign _zz_455 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_456 = 32'h00002010; - assign _zz_457 = ((decode_INSTRUCTION & _zz_473) == 32'h00000010); - assign _zz_458 = (_zz_474 == _zz_475); - assign _zz_459 = (_zz_476 == _zz_477); - assign _zz_460 = ((decode_INSTRUCTION & _zz_478) == 32'h00001010); - assign _zz_461 = (_zz_479 == _zz_480); - assign _zz_462 = {_zz_481,{_zz_482,_zz_483}}; - assign _zz_463 = ((decode_INSTRUCTION & _zz_484) == 32'h00000020); - assign _zz_464 = _zz_88; - assign _zz_465 = (_zz_485 == _zz_486); - assign _zz_466 = (_zz_487 == _zz_488); - assign _zz_467 = 1'b0; - assign _zz_468 = (_zz_489 != 1'b0); - assign _zz_469 = (_zz_490 != _zz_491); - assign _zz_470 = {_zz_492,{_zz_493,_zz_494}}; - assign _zz_471 = 32'h00000030; - assign _zz_472 = 32'h02000020; - assign _zz_473 = 32'h00001030; - assign _zz_474 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_475 = 32'h00002020; - assign _zz_476 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_477 = 32'h00000020; - assign _zz_478 = 32'h00001010; - assign _zz_479 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_480 = 32'h00002010; - assign _zz_481 = ((decode_INSTRUCTION & _zz_495) == 32'h00000010); - assign _zz_482 = (_zz_496 == _zz_497); - assign _zz_483 = (_zz_498 == _zz_499); - assign _zz_484 = 32'h00000070; - assign _zz_485 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_486 = 32'h0; - assign _zz_487 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_488 = 32'h00004010; - assign _zz_489 = ((decode_INSTRUCTION & _zz_500) == 32'h00002010); - assign _zz_490 = {_zz_501,{_zz_502,_zz_503}}; - assign _zz_491 = 4'b0000; - assign _zz_492 = (_zz_504 != 1'b0); - assign _zz_493 = (_zz_505 != _zz_506); - assign _zz_494 = {_zz_507,{_zz_508,_zz_509}}; - assign _zz_495 = 32'h00000050; - assign _zz_496 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_497 = 32'h00000004; - assign _zz_498 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_499 = 32'h0; - assign _zz_500 = 32'h00006014; - assign _zz_501 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_502 = ((decode_INSTRUCTION & _zz_510) == 32'h0); - assign _zz_503 = {(_zz_511 == _zz_512),(_zz_513 == _zz_514)}; - assign _zz_504 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_505 = {(_zz_515 == _zz_516),{_zz_517,_zz_518}}; - assign _zz_506 = 3'b000; - assign _zz_507 = ({_zz_519,_zz_87} != 2'b00); - assign _zz_508 = ({_zz_520,_zz_521} != 2'b00); - assign _zz_509 = (_zz_522 != 1'b0); - assign _zz_510 = 32'h00000018; - assign _zz_511 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_512 = 32'h00002000; - assign _zz_513 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_514 = 32'h00001000; - assign _zz_515 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_516 = 32'h00000040; - assign _zz_517 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_518 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_519 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_520 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_521 = _zz_87; - assign _zz_522 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); - assign _zz_523 = execute_INSTRUCTION[31]; - assign _zz_524 = execute_INSTRUCTION[31]; - assign _zz_525 = execute_INSTRUCTION[7]; - assign _zz_526 = 32'h0; + assign _zz_210 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_211 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_212 = 1'b1; + assign _zz_213 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_214 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_215 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_216 = ((_zz_184 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_217 = ((_zz_184 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_218 = ((_zz_184 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_219 = ((_zz_184 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_220 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_221 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_222 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_223 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_224 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_225 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_226 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_227 = (1'b0 || (! 1'b1)); + assign _zz_228 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_229 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_230 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_231 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_232 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_233 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_234 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_235 = execute_INSTRUCTION[13 : 12]; + assign _zz_236 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_237 = (! memory_arbitration_isStuck); + assign _zz_238 = (iBus_cmd_valid || (_zz_170 != 3'b000)); + assign _zz_239 = (_zz_206 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_240 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_241 = ((_zz_135 && 1'b1) && (! 1'b0)); + assign _zz_242 = ((_zz_136 && 1'b1) && (! 1'b0)); + assign _zz_243 = ((_zz_137 && 1'b1) && (! 1'b0)); + assign _zz_244 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_245 = execute_INSTRUCTION[13]; + assign _zz_246 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_247 = ($signed(_zz_248) + $signed(_zz_253)); + assign _zz_248 = ($signed(_zz_249) + $signed(_zz_251)); + assign _zz_249 = 52'h0; + assign _zz_250 = {1'b0,memory_MUL_LL}; + assign _zz_251 = {{19{_zz_250[32]}}, _zz_250}; + assign _zz_252 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_253 = {{2{_zz_252[49]}}, _zz_252}; + assign _zz_254 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_255 = {{2{_zz_254[49]}}, _zz_254}; + assign _zz_256 = ($signed(_zz_258) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_257 = _zz_256[31 : 0]; + assign _zz_258 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_259 = _zz_86[31 : 31]; + assign _zz_260 = _zz_86[30 : 30]; + assign _zz_261 = _zz_86[29 : 29]; + assign _zz_262 = _zz_86[28 : 28]; + assign _zz_263 = _zz_86[25 : 25]; + assign _zz_264 = _zz_86[17 : 17]; + assign _zz_265 = _zz_86[16 : 16]; + assign _zz_266 = _zz_86[13 : 13]; + assign _zz_267 = _zz_86[12 : 12]; + assign _zz_268 = _zz_86[11 : 11]; + assign _zz_269 = _zz_86[15 : 15]; + assign _zz_270 = _zz_86[5 : 5]; + assign _zz_271 = _zz_86[3 : 3]; + assign _zz_272 = _zz_86[20 : 20]; + assign _zz_273 = _zz_86[10 : 10]; + assign _zz_274 = _zz_86[4 : 4]; + assign _zz_275 = _zz_86[0 : 0]; + assign _zz_276 = (_zz_54 - 4'b0001); + assign _zz_277 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_278 = {29'd0, _zz_277}; + assign _zz_279 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_280 = {{_zz_69,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_281 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_282 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_283 = {{_zz_71,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_284 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_285 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_286 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_287 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_288 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_289 = execute_SRC_LESS; + assign _zz_290 = 3'b100; + assign _zz_291 = execute_INSTRUCTION[19 : 15]; + assign _zz_292 = execute_INSTRUCTION[31 : 20]; + assign _zz_293 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_294 = ($signed(_zz_295) + $signed(_zz_298)); + assign _zz_295 = ($signed(_zz_296) + $signed(_zz_297)); + assign _zz_296 = execute_SRC1; + assign _zz_297 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_298 = (execute_SRC_USE_SUB_LESS ? _zz_299 : _zz_300); + assign _zz_299 = 32'h00000001; + assign _zz_300 = 32'h0; + assign _zz_301 = execute_INSTRUCTION[31 : 20]; + assign _zz_302 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_303 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_304 = {_zz_123,execute_INSTRUCTION[31 : 20]}; + assign _zz_305 = {{_zz_125,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_306 = {{_zz_127,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_307 = execute_INSTRUCTION[31 : 20]; + assign _zz_308 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_309 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_310 = 3'b100; + assign _zz_311 = (_zz_138 & (~ _zz_312)); + assign _zz_312 = (_zz_138 - 2'b01); + assign _zz_313 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_314 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_315 = writeBack_MUL_LOW[31 : 0]; + assign _zz_316 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_317 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_318 = {5'd0, _zz_317}; + assign _zz_319 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_320 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_321 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_322 = {_zz_140,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_323 = _zz_324; + assign _zz_324 = _zz_325; + assign _zz_325 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_141) : _zz_141)} + _zz_327); + assign _zz_326 = memory_DivPlugin_div_needRevert; + assign _zz_327 = {32'd0, _zz_326}; + assign _zz_328 = _zz_143; + assign _zz_329 = {32'd0, _zz_328}; + assign _zz_330 = _zz_142; + assign _zz_331 = {31'd0, _zz_330}; + assign _zz_332 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_333 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_334 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_335 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_336 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_337 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_338 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_339 = (iBus_cmd_payload_address >>> 5); + assign _zz_340 = 1'b1; + assign _zz_341 = 1'b1; + assign _zz_342 = {_zz_58,_zz_57}; + assign _zz_343 = 32'h0000107f; + assign _zz_344 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_345 = 32'h00002073; + assign _zz_346 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_347 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_348 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_349) == 32'h00000003),{(_zz_350 == _zz_351),{_zz_352,{_zz_353,_zz_354}}}}}}; + assign _zz_349 = 32'h0000505f; + assign _zz_350 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_351 = 32'h00000063; + assign _zz_352 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_353 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_354 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_355) == 32'h00001013),{(_zz_356 == _zz_357),{_zz_358,{_zz_359,_zz_360}}}}}}; + assign _zz_355 = 32'hfc00307f; + assign _zz_356 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_357 = 32'h00005033; + assign _zz_358 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_359 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_360 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_361 = decode_INSTRUCTION[31]; + assign _zz_362 = decode_INSTRUCTION[31]; + assign _zz_363 = decode_INSTRUCTION[7]; + assign _zz_364 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_365 = 32'h02004020; + assign _zz_366 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_367 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); + assign _zz_368 = 1'b0; + assign _zz_369 = (((decode_INSTRUCTION & _zz_372) == 32'h00000050) != 1'b0); + assign _zz_370 = ({_zz_373,_zz_374} != 2'b00); + assign _zz_371 = {({_zz_375,_zz_376} != 2'b00),{(_zz_377 != _zz_378),{_zz_379,{_zz_380,_zz_381}}}}; + assign _zz_372 = 32'h00403050; + assign _zz_373 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_374 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_375 = _zz_89; + assign _zz_376 = ((decode_INSTRUCTION & _zz_382) == 32'h00000004); + assign _zz_377 = ((decode_INSTRUCTION & _zz_383) == 32'h00000040); + assign _zz_378 = 1'b0; + assign _zz_379 = ({_zz_384,_zz_385} != 2'b00); + assign _zz_380 = ({_zz_386,_zz_387} != 3'b000); + assign _zz_381 = {(_zz_388 != _zz_389),{_zz_390,{_zz_391,_zz_392}}}; + assign _zz_382 = 32'h0000001c; + assign _zz_383 = 32'h00000058; + assign _zz_384 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_385 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_386 = ((decode_INSTRUCTION & _zz_393) == 32'h40001010); + assign _zz_387 = {(_zz_394 == _zz_395),(_zz_396 == _zz_397)}; + assign _zz_388 = ((decode_INSTRUCTION & _zz_398) == 32'h00000024); + assign _zz_389 = 1'b0; + assign _zz_390 = ((_zz_399 == _zz_400) != 1'b0); + assign _zz_391 = (_zz_401 != 1'b0); + assign _zz_392 = {(_zz_402 != _zz_403),{_zz_404,{_zz_405,_zz_406}}}; + assign _zz_393 = 32'h40003054; + assign _zz_394 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_395 = 32'h00001010; + assign _zz_396 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_397 = 32'h00001010; + assign _zz_398 = 32'h00000064; + assign _zz_399 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_400 = 32'h00001000; + assign _zz_401 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_402 = {(_zz_407 == _zz_408),(_zz_409 == _zz_410)}; + assign _zz_403 = 2'b00; + assign _zz_404 = ((_zz_411 == _zz_412) != 1'b0); + assign _zz_405 = ({_zz_413,_zz_414} != 2'b00); + assign _zz_406 = {(_zz_415 != _zz_416),{_zz_417,{_zz_418,_zz_419}}}; + assign _zz_407 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_408 = 32'h00002000; + assign _zz_409 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_410 = 32'h00001000; + assign _zz_411 = (decode_INSTRUCTION & 32'h00004048); + assign _zz_412 = 32'h00004008; + assign _zz_413 = ((decode_INSTRUCTION & _zz_420) == 32'h00000020); + assign _zz_414 = ((decode_INSTRUCTION & _zz_421) == 32'h00000020); + assign _zz_415 = {(_zz_422 == _zz_423),{_zz_424,{_zz_425,_zz_426}}}; + assign _zz_416 = 5'h0; + assign _zz_417 = ((_zz_427 == _zz_428) != 1'b0); + assign _zz_418 = ({_zz_429,_zz_430} != 5'h0); + assign _zz_419 = {(_zz_431 != _zz_432),{_zz_433,{_zz_434,_zz_435}}}; + assign _zz_420 = 32'h00000034; + assign _zz_421 = 32'h00000064; + assign _zz_422 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_423 = 32'h00002040; + assign _zz_424 = ((decode_INSTRUCTION & _zz_436) == 32'h00001040); + assign _zz_425 = (_zz_437 == _zz_438); + assign _zz_426 = {_zz_439,_zz_440}; + assign _zz_427 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_428 = 32'h00000020; + assign _zz_429 = (_zz_441 == _zz_442); + assign _zz_430 = {_zz_88,{_zz_443,_zz_444}}; + assign _zz_431 = {_zz_88,{_zz_445,_zz_446}}; + assign _zz_432 = 5'h0; + assign _zz_433 = ({_zz_447,_zz_448} != 6'h0); + assign _zz_434 = (_zz_449 != _zz_450); + assign _zz_435 = {_zz_451,{_zz_452,_zz_453}}; + assign _zz_436 = 32'h00001040; + assign _zz_437 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_438 = 32'h00000040; + assign _zz_439 = ((decode_INSTRUCTION & _zz_454) == 32'h00000040); + assign _zz_440 = ((decode_INSTRUCTION & _zz_455) == 32'h0); + assign _zz_441 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_442 = 32'h00000040; + assign _zz_443 = (_zz_456 == _zz_457); + assign _zz_444 = {_zz_458,_zz_459}; + assign _zz_445 = (_zz_460 == _zz_461); + assign _zz_446 = {_zz_462,{_zz_463,_zz_464}}; + assign _zz_447 = _zz_89; + assign _zz_448 = {_zz_465,{_zz_466,_zz_467}}; + assign _zz_449 = {_zz_88,_zz_468}; + assign _zz_450 = 2'b00; + assign _zz_451 = ({_zz_469,_zz_470} != 2'b00); + assign _zz_452 = (_zz_471 != _zz_472); + assign _zz_453 = {_zz_473,{_zz_474,_zz_475}}; + assign _zz_454 = 32'h00400040; + assign _zz_455 = 32'h00000038; + assign _zz_456 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_457 = 32'h00004020; + assign _zz_458 = ((decode_INSTRUCTION & _zz_476) == 32'h00000010); + assign _zz_459 = ((decode_INSTRUCTION & _zz_477) == 32'h00000020); + assign _zz_460 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_461 = 32'h00002010; + assign _zz_462 = ((decode_INSTRUCTION & _zz_478) == 32'h00000010); + assign _zz_463 = (_zz_479 == _zz_480); + assign _zz_464 = (_zz_481 == _zz_482); + assign _zz_465 = ((decode_INSTRUCTION & _zz_483) == 32'h00001010); + assign _zz_466 = (_zz_484 == _zz_485); + assign _zz_467 = {_zz_486,{_zz_487,_zz_488}}; + assign _zz_468 = ((decode_INSTRUCTION & _zz_489) == 32'h00000020); + assign _zz_469 = _zz_88; + assign _zz_470 = (_zz_490 == _zz_491); + assign _zz_471 = (_zz_492 == _zz_493); + assign _zz_472 = 1'b0; + assign _zz_473 = (_zz_494 != 1'b0); + assign _zz_474 = (_zz_495 != _zz_496); + assign _zz_475 = {_zz_497,{_zz_498,_zz_499}}; + assign _zz_476 = 32'h00000030; + assign _zz_477 = 32'h02000020; + assign _zz_478 = 32'h00001030; + assign _zz_479 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_480 = 32'h00002020; + assign _zz_481 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_482 = 32'h00000020; + assign _zz_483 = 32'h00001010; + assign _zz_484 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_485 = 32'h00002010; + assign _zz_486 = ((decode_INSTRUCTION & _zz_500) == 32'h00000010); + assign _zz_487 = (_zz_501 == _zz_502); + assign _zz_488 = (_zz_503 == _zz_504); + assign _zz_489 = 32'h00000070; + assign _zz_490 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_491 = 32'h0; + assign _zz_492 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_493 = 32'h00004010; + assign _zz_494 = ((decode_INSTRUCTION & _zz_505) == 32'h00002010); + assign _zz_495 = {_zz_506,{_zz_507,_zz_508}}; + assign _zz_496 = 4'b0000; + assign _zz_497 = (_zz_509 != 1'b0); + assign _zz_498 = (_zz_510 != _zz_511); + assign _zz_499 = {_zz_512,{_zz_513,_zz_514}}; + assign _zz_500 = 32'h00000050; + assign _zz_501 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_502 = 32'h00000004; + assign _zz_503 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_504 = 32'h0; + assign _zz_505 = 32'h00006014; + assign _zz_506 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_507 = ((decode_INSTRUCTION & _zz_515) == 32'h0); + assign _zz_508 = {(_zz_516 == _zz_517),(_zz_518 == _zz_519)}; + assign _zz_509 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_510 = {(_zz_520 == _zz_521),{_zz_522,_zz_523}}; + assign _zz_511 = 3'b000; + assign _zz_512 = ({_zz_524,_zz_87} != 2'b00); + assign _zz_513 = ({_zz_525,_zz_526} != 2'b00); + assign _zz_514 = (_zz_527 != 1'b0); + assign _zz_515 = 32'h00000018; + assign _zz_516 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_517 = 32'h00002000; + assign _zz_518 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_519 = 32'h00001000; + assign _zz_520 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_521 = 32'h00000040; + assign _zz_522 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_523 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_524 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_525 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_526 = _zz_87; + assign _zz_527 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_528 = execute_INSTRUCTION[31]; + assign _zz_529 = execute_INSTRUCTION[31]; + assign _zz_530 = execute_INSTRUCTION[7]; + assign _zz_531 = 32'h0; always @ (posedge clk) begin - if(_zz_335) begin - _zz_202 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_340) begin + _zz_207 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_336) begin - _zz_203 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_341) begin + _zz_208 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1616,13 +1611,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_174 ), //i - .io_cpu_prefetch_isValid (_zz_175 ), //i + .io_flush (_zz_179 ), //i + .io_cpu_prefetch_isValid (_zz_180 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_176 ), //i - .io_cpu_fetch_isStuck (_zz_177 ), //i - .io_cpu_fetch_isRemoved (_zz_178 ), //i + .io_cpu_fetch_isValid (_zz_181 ), //i + .io_cpu_fetch_isStuck (_zz_182 ), //i + .io_cpu_fetch_isRemoved (_zz_183 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1635,8 +1630,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_179 ), //i - .io_cpu_decode_isStuck (_zz_180 ), //i + .io_cpu_decode_isValid (_zz_184 ), //i + .io_cpu_decode_isStuck (_zz_185 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1644,8 +1639,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_181 ), //i - .io_cpu_fill_valid (_zz_182 ), //i + .io_cpu_decode_isUser (_zz_186 ), //i + .io_cpu_fill_valid (_zz_187 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1658,20 +1653,20 @@ module VexRiscv ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_183 ), //i - .io_cpu_execute_address (_zz_184[31:0] ), //i + .io_cpu_execute_isValid (_zz_188 ), //i + .io_cpu_execute_address (_zz_189[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_81[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_185 ), //i + .io_cpu_memory_isValid (_zz_190 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_186[31:0] ), //i + .io_cpu_memory_address (_zz_191[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_187 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_192 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1679,31 +1674,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_188 ), //i + .io_cpu_writeBack_isValid (_zz_193 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_189 ), //i + .io_cpu_writeBack_isUser (_zz_194 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_190[31:0] ), //i + .io_cpu_writeBack_address (_zz_195[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_191 ), //i - .io_cpu_writeBack_fence_SR (_zz_192 ), //i - .io_cpu_writeBack_fence_SO (_zz_193 ), //i - .io_cpu_writeBack_fence_SI (_zz_194 ), //i - .io_cpu_writeBack_fence_PW (_zz_195 ), //i - .io_cpu_writeBack_fence_PR (_zz_196 ), //i - .io_cpu_writeBack_fence_PO (_zz_197 ), //i - .io_cpu_writeBack_fence_PI (_zz_198 ), //i - .io_cpu_writeBack_fence_FM (_zz_199[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_196 ), //i + .io_cpu_writeBack_fence_SR (_zz_197 ), //i + .io_cpu_writeBack_fence_SO (_zz_198 ), //i + .io_cpu_writeBack_fence_SI (_zz_199 ), //i + .io_cpu_writeBack_fence_PW (_zz_200 ), //i + .io_cpu_writeBack_fence_PR (_zz_201 ), //i + .io_cpu_writeBack_fence_PO (_zz_202 ), //i + .io_cpu_writeBack_fence_PI (_zz_203 ), //i + .io_cpu_writeBack_fence_FM (_zz_204[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_200 ), //i + .io_cpu_flush_valid (_zz_205 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_201 ), //i + .io_mem_cmd_ready (_zz_206 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1719,18 +1714,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_337) + case(_zz_342) 2'b00 : begin - _zz_204 = DBusCachedPlugin_redoBranch_payload; + _zz_209 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_204 = CsrPlugin_jumpInterface_payload; + _zz_209 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_204 = BranchPlugin_jumpInterface_payload; + _zz_209 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_204 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_209 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2422,7 +2417,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_242) + $signed(_zz_250)); + assign memory_MUL_LOW = ($signed(_zz_247) + $signed(_zz_255)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2430,38 +2425,38 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_252; + assign execute_SHIFT_RIGHT = _zz_257; assign execute_REGFILE_WRITE_DATA = _zz_99; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_184[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_189[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_254[0]; - assign decode_IS_RS1_SIGNED = _zz_255[0]; - assign decode_IS_DIV = _zz_256[0]; + assign decode_IS_RS2_SIGNED = _zz_259[0]; + assign decode_IS_RS1_SIGNED = _zz_260[0]; + assign decode_IS_DIV = _zz_261[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_257[0]; + assign decode_IS_MUL = _zz_262[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_258[0]; + assign decode_IS_CSR = _zz_263[0]; assign _zz_8 = _zz_9; assign _zz_10 = _zz_11; assign decode_SHIFT_CTRL = _zz_12; assign _zz_13 = _zz_14; assign decode_ALU_BITWISE_CTRL = _zz_15; assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_259[0]; - assign decode_MEMORY_MANAGMENT = _zz_260[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_264[0]; + assign decode_MEMORY_MANAGMENT = _zz_265[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_261[0]; + assign decode_MEMORY_WR = _zz_266[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_262[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_263[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_267[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_268[0]; assign decode_SRC2_CTRL = _zz_18; assign _zz_19 = _zz_20; assign decode_ALU_CTRL = _zz_21; @@ -2495,13 +2490,13 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_116; + assign execute_BRANCH_COND_RESULT = _zz_121; assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_264[0]; - assign decode_RS1_USE = _zz_265[0]; + assign decode_RS2_USE = _zz_269[0]; + assign decode_RS1_USE = _zz_270[0]; always @ (*) begin _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_205)begin + if(_zz_210)begin _zz_31 = execute_CsrPlugin_readData; end end @@ -2514,28 +2509,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_110)begin + if((_zz_111 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_112; end end - if(_zz_206)begin - if(_zz_207)begin - if(_zz_109)begin + if(_zz_211)begin + if(_zz_212)begin + if(_zz_114)begin decode_RS2 = _zz_50; end end end - if(_zz_208)begin + if(_zz_213)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_111)begin + if(_zz_116)begin decode_RS2 = _zz_32; end end end - if(_zz_209)begin + if(_zz_214)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_113)begin + if(_zz_118)begin decode_RS2 = _zz_31; end end @@ -2544,28 +2539,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_110)begin + if((_zz_111 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_112; end end - if(_zz_206)begin - if(_zz_207)begin - if(_zz_108)begin + if(_zz_211)begin + if(_zz_212)begin + if(_zz_113)begin decode_RS1 = _zz_50; end end end - if(_zz_208)begin + if(_zz_213)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_110)begin + if(_zz_115)begin decode_RS1 = _zz_32; end end end - if(_zz_209)begin + if(_zz_214)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_112)begin + if(_zz_117)begin decode_RS1 = _zz_31; end end @@ -2587,7 +2582,7 @@ module VexRiscv ( end endcase end - if(_zz_210)begin + if(_zz_215)begin _zz_32 = memory_DivPlugin_div_result; end end @@ -2600,8 +2595,8 @@ module VexRiscv ( assign _zz_35 = execute_PC; assign execute_SRC2_CTRL = _zz_36; assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_266[0]; - assign decode_SRC_ADD_ZERO = _zz_267[0]; + assign decode_SRC_USE_SUB_LESS = _zz_271[0]; + assign decode_SRC_ADD_ZERO = _zz_272[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_38; @@ -2619,25 +2614,25 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_268[0]; + decode_REGFILE_WRITE_VALID = _zz_273[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_338) == 32'h00001073),{(_zz_339 == _zz_340),{_zz_341,{_zz_342,_zz_343}}}}}}} != 21'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_343) == 32'h00001073),{(_zz_344 == _zz_345),{_zz_346,{_zz_347,_zz_348}}}}}}} != 21'h0); always @ (*) begin _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_241) + case(_zz_246) 2'b00 : begin - _zz_50 = _zz_310; + _zz_50 = _zz_315; end default : begin - _zz_50 = _zz_311; + _zz_50 = _zz_316; end endcase end @@ -2656,32 +2651,32 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_269[0]; - assign decode_FLUSH_ALL = _zz_270[0]; + assign decode_MEMORY_ENABLE = _zz_274[0]; + assign decode_FLUSH_ALL = _zz_275[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_211)begin + if(_zz_216)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_212)begin + if(_zz_217)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_213)begin + if(_zz_218)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_214)begin + if(_zz_219)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2714,7 +2709,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_108 || _zz_109)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2727,7 +2722,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_215)begin + if(_zz_220)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2741,22 +2736,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_215)begin + if(_zz_220)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_200 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_205 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_216)begin + if(_zz_221)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_205)begin + if(_zz_210)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2790,7 +2785,7 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_210)begin + if(_zz_215)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2852,10 +2847,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_217)begin + if(_zz_222)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_218)begin + if(_zz_223)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2869,10 +2864,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_217)begin + if(_zz_222)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_218)begin + if(_zz_223)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -2886,7 +2881,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_216)begin + if(_zz_221)begin CsrPlugin_inWfi = 1'b1; end end @@ -2894,21 +2889,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_217)begin + if(_zz_222)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_218)begin + if(_zz_223)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_217)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_222)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_218)begin - case(_zz_219) + if(_zz_223)begin + case(_zz_224) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2924,11 +2919,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_54 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_55 = (_zz_54 & (~ _zz_271)); + assign _zz_55 = (_zz_54 & (~ _zz_276)); assign _zz_56 = _zz_55[3]; assign _zz_57 = (_zz_55[1] || _zz_56); assign _zz_58 = (_zz_55[2] || _zz_56); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_204; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_209; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -2948,7 +2943,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_273); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_278); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3039,7 +3034,7 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_68 = _zz_274[11]; + assign _zz_68 = _zz_279[11]; always @ (*) begin _zz_69[18] = _zz_68; _zz_69[17] = _zz_68; @@ -3063,13 +3058,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_275[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_280[31])); if(_zz_74)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_70 = _zz_276[19]; + assign _zz_70 = _zz_281[19]; always @ (*) begin _zz_71[10] = _zz_70; _zz_71[9] = _zz_70; @@ -3084,7 +3079,7 @@ module VexRiscv ( _zz_71[0] = _zz_70; end - assign _zz_72 = _zz_277[11]; + assign _zz_72 = _zz_282[11]; always @ (*) begin _zz_73[18] = _zz_72; _zz_73[17] = _zz_72; @@ -3110,16 +3105,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_74 = _zz_278[1]; + _zz_74 = _zz_283[1]; end default : begin - _zz_74 = _zz_279[1]; + _zz_74 = _zz_284[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_75 = _zz_280[19]; + assign _zz_75 = _zz_285[19]; always @ (*) begin _zz_76[10] = _zz_75; _zz_76[9] = _zz_75; @@ -3134,7 +3129,7 @@ module VexRiscv ( _zz_76[0] = _zz_75; end - assign _zz_77 = _zz_281[11]; + assign _zz_77 = _zz_286[11]; always @ (*) begin _zz_78[18] = _zz_77; _zz_78[17] = _zz_77; @@ -3157,7 +3152,7 @@ module VexRiscv ( _zz_78[0] = _zz_77; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_76,{{{_zz_356,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_78,{{{_zz_357,_zz_358},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_76,{{{_zz_361,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_78,{{{_zz_362,_zz_363},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3166,52 +3161,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_175 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_176 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_177 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_176; + assign _zz_180 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_181 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_182 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_181; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_179 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_180 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_181 = (CsrPlugin_privilege == 2'b00); + assign _zz_184 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_185 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_186 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_214)begin + if(_zz_219)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_212)begin + if(_zz_217)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_182 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_212)begin - _zz_182 = 1'b1; + _zz_187 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_217)begin + _zz_187 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_213)begin + if(_zz_218)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_211)begin + if(_zz_216)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_213)begin + if(_zz_218)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_211)begin + if(_zz_216)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3221,9 +3216,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_174 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_179 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_201 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_206 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3250,8 +3245,8 @@ module VexRiscv ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_183 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_184 = execute_SRC_ADD; + assign _zz_188 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_189 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3266,27 +3261,27 @@ module VexRiscv ( endcase end - assign _zz_200 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_185 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_186 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_185; + assign _zz_205 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_190 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_191 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_190; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_186; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_191; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_187 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_192 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_187 = 1'b1; + _zz_192 = 1'b1; end end - assign _zz_188 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_189 = (CsrPlugin_privilege == 2'b00); - assign _zz_190 = writeBack_REGFILE_WRITE_DATA; + assign _zz_193 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_194 = (CsrPlugin_privilege == 2'b00); + assign _zz_195 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_220)begin + if(_zz_225)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3296,7 +3291,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_220)begin + if(_zz_225)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3315,15 +3310,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_220)begin + if(_zz_225)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_282}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_287}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_283}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_288}; end end end @@ -3396,7 +3391,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_239) + case(_zz_244) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_83; end @@ -3431,7 +3426,7 @@ module VexRiscv ( assign _zz_88 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_89 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_90 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_86 = {(_zz_90 != 1'b0),{(_zz_90 != 1'b0),{((_zz_359 == _zz_360) != 1'b0),{(_zz_361 != 1'b0),{(_zz_362 != _zz_363),{_zz_364,{_zz_365,_zz_366}}}}}}}; + assign _zz_86 = {(_zz_90 != 1'b0),{(_zz_90 != 1'b0),{((_zz_364 == _zz_365) != 1'b0),{(_zz_366 != 1'b0),{(_zz_367 != _zz_368),{_zz_369,{_zz_370,_zz_371}}}}}}}; assign _zz_91 = _zz_86[2 : 1]; assign _zz_49 = _zz_91; assign _zz_92 = _zz_86[7 : 6]; @@ -3451,8 +3446,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_202; - assign decode_RegFilePlugin_rs2Data = _zz_203; + assign decode_RegFilePlugin_rs1Data = _zz_207; + assign decode_RegFilePlugin_rs2Data = _zz_208; always @ (*) begin lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); if(_zz_98)begin @@ -3494,7 +3489,7 @@ module VexRiscv ( _zz_99 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_99 = {31'd0, _zz_284}; + _zz_99 = {31'd0, _zz_289}; end default : begin _zz_99 = execute_SRC_ADD_SUB; @@ -3508,18 +3503,18 @@ module VexRiscv ( _zz_100 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_100 = {29'd0, _zz_285}; + _zz_100 = {29'd0, _zz_290}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_100 = {27'd0, _zz_286}; + _zz_100 = {27'd0, _zz_291}; end endcase end - assign _zz_101 = _zz_287[11]; + assign _zz_101 = _zz_292[11]; always @ (*) begin _zz_102[19] = _zz_101; _zz_102[18] = _zz_101; @@ -3543,7 +3538,7 @@ module VexRiscv ( _zz_102[0] = _zz_101; end - assign _zz_103 = _zz_288[11]; + assign _zz_103 = _zz_293[11]; always @ (*) begin _zz_104[19] = _zz_103; _zz_104[18] = _zz_103; @@ -3585,7 +3580,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_289; + execute_SrcPlugin_addSub = _zz_294; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3665,180 +3660,175 @@ module VexRiscv ( end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_221)begin - if(_zz_222)begin - if(_zz_108)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_108 = 1'b0; + if(_zz_226)begin + if(_zz_227)begin + if(_zz_113)begin + _zz_108 = 1'b1; end end end - if(_zz_223)begin - if(_zz_224)begin - if(_zz_110)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_228)begin + if(_zz_229)begin + if(_zz_115)begin + _zz_108 = 1'b1; end end end - if(_zz_225)begin - if(_zz_226)begin - if(_zz_112)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_230)begin + if(_zz_231)begin + if(_zz_117)begin + _zz_108 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_108 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_221)begin - if(_zz_222)begin - if(_zz_109)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_109 = 1'b0; + if(_zz_226)begin + if(_zz_227)begin + if(_zz_114)begin + _zz_109 = 1'b1; end end end - if(_zz_223)begin - if(_zz_224)begin - if(_zz_111)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_228)begin + if(_zz_229)begin + if(_zz_116)begin + _zz_109 = 1'b1; end end end - if(_zz_225)begin - if(_zz_226)begin - if(_zz_113)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_230)begin + if(_zz_231)begin + if(_zz_118)begin + _zz_109 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_109 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_108 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_109 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_110 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_111 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_112 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_113 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_113 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_114 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_115 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_116 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_117 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_118 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_114 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_114 == 3'b000)) begin - _zz_115 = execute_BranchPlugin_eq; - end else if((_zz_114 == 3'b001)) begin - _zz_115 = (! execute_BranchPlugin_eq); - end else if((((_zz_114 & 3'b101) == 3'b101))) begin - _zz_115 = (! execute_SRC_LESS); + assign _zz_119 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_119 == 3'b000)) begin + _zz_120 = execute_BranchPlugin_eq; + end else if((_zz_119 == 3'b001)) begin + _zz_120 = (! execute_BranchPlugin_eq); + end else if((((_zz_119 & 3'b101) == 3'b101))) begin + _zz_120 = (! execute_SRC_LESS); end else begin - _zz_115 = execute_SRC_LESS; + _zz_120 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_116 = 1'b0; + _zz_121 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_116 = 1'b1; + _zz_121 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_116 = 1'b1; + _zz_121 = 1'b1; end default : begin - _zz_116 = _zz_115; + _zz_121 = _zz_120; end endcase end - assign _zz_117 = _zz_296[11]; - always @ (*) begin - _zz_118[19] = _zz_117; - _zz_118[18] = _zz_117; - _zz_118[17] = _zz_117; - _zz_118[16] = _zz_117; - _zz_118[15] = _zz_117; - _zz_118[14] = _zz_117; - _zz_118[13] = _zz_117; - _zz_118[12] = _zz_117; - _zz_118[11] = _zz_117; - _zz_118[10] = _zz_117; - _zz_118[9] = _zz_117; - _zz_118[8] = _zz_117; - _zz_118[7] = _zz_117; - _zz_118[6] = _zz_117; - _zz_118[5] = _zz_117; - _zz_118[4] = _zz_117; - _zz_118[3] = _zz_117; - _zz_118[2] = _zz_117; - _zz_118[1] = _zz_117; - _zz_118[0] = _zz_117; - end - - assign _zz_119 = _zz_297[19]; - always @ (*) begin - _zz_120[10] = _zz_119; - _zz_120[9] = _zz_119; - _zz_120[8] = _zz_119; - _zz_120[7] = _zz_119; - _zz_120[6] = _zz_119; - _zz_120[5] = _zz_119; - _zz_120[4] = _zz_119; - _zz_120[3] = _zz_119; - _zz_120[2] = _zz_119; - _zz_120[1] = _zz_119; - _zz_120[0] = _zz_119; - end - - assign _zz_121 = _zz_298[11]; - always @ (*) begin - _zz_122[18] = _zz_121; - _zz_122[17] = _zz_121; - _zz_122[16] = _zz_121; - _zz_122[15] = _zz_121; - _zz_122[14] = _zz_121; - _zz_122[13] = _zz_121; - _zz_122[12] = _zz_121; - _zz_122[11] = _zz_121; - _zz_122[10] = _zz_121; - _zz_122[9] = _zz_121; - _zz_122[8] = _zz_121; - _zz_122[7] = _zz_121; - _zz_122[6] = _zz_121; - _zz_122[5] = _zz_121; - _zz_122[4] = _zz_121; - _zz_122[3] = _zz_121; - _zz_122[2] = _zz_121; - _zz_122[1] = _zz_121; - _zz_122[0] = _zz_121; + assign _zz_122 = _zz_301[11]; + always @ (*) begin + _zz_123[19] = _zz_122; + _zz_123[18] = _zz_122; + _zz_123[17] = _zz_122; + _zz_123[16] = _zz_122; + _zz_123[15] = _zz_122; + _zz_123[14] = _zz_122; + _zz_123[13] = _zz_122; + _zz_123[12] = _zz_122; + _zz_123[11] = _zz_122; + _zz_123[10] = _zz_122; + _zz_123[9] = _zz_122; + _zz_123[8] = _zz_122; + _zz_123[7] = _zz_122; + _zz_123[6] = _zz_122; + _zz_123[5] = _zz_122; + _zz_123[4] = _zz_122; + _zz_123[3] = _zz_122; + _zz_123[2] = _zz_122; + _zz_123[1] = _zz_122; + _zz_123[0] = _zz_122; + end + + assign _zz_124 = _zz_302[19]; + always @ (*) begin + _zz_125[10] = _zz_124; + _zz_125[9] = _zz_124; + _zz_125[8] = _zz_124; + _zz_125[7] = _zz_124; + _zz_125[6] = _zz_124; + _zz_125[5] = _zz_124; + _zz_125[4] = _zz_124; + _zz_125[3] = _zz_124; + _zz_125[2] = _zz_124; + _zz_125[1] = _zz_124; + _zz_125[0] = _zz_124; + end + + assign _zz_126 = _zz_303[11]; + always @ (*) begin + _zz_127[18] = _zz_126; + _zz_127[17] = _zz_126; + _zz_127[16] = _zz_126; + _zz_127[15] = _zz_126; + _zz_127[14] = _zz_126; + _zz_127[13] = _zz_126; + _zz_127[12] = _zz_126; + _zz_127[11] = _zz_126; + _zz_127[10] = _zz_126; + _zz_127[9] = _zz_126; + _zz_127[8] = _zz_126; + _zz_127[7] = _zz_126; + _zz_127[6] = _zz_126; + _zz_127[5] = _zz_126; + _zz_127[4] = _zz_126; + _zz_127[3] = _zz_126; + _zz_127[2] = _zz_126; + _zz_127[1] = _zz_126; + _zz_127[0] = _zz_126; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_123 = (_zz_299[1] ^ execute_RS1[1]); + _zz_128 = (_zz_304[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_123 = _zz_300[1]; + _zz_128 = _zz_305[1]; end default : begin - _zz_123 = _zz_301[1]; + _zz_128 = _zz_306[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_123); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_128); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -3850,80 +3840,80 @@ module VexRiscv ( endcase end - assign _zz_124 = _zz_302[11]; + assign _zz_129 = _zz_307[11]; always @ (*) begin - _zz_125[19] = _zz_124; - _zz_125[18] = _zz_124; - _zz_125[17] = _zz_124; - _zz_125[16] = _zz_124; - _zz_125[15] = _zz_124; - _zz_125[14] = _zz_124; - _zz_125[13] = _zz_124; - _zz_125[12] = _zz_124; - _zz_125[11] = _zz_124; - _zz_125[10] = _zz_124; - _zz_125[9] = _zz_124; - _zz_125[8] = _zz_124; - _zz_125[7] = _zz_124; - _zz_125[6] = _zz_124; - _zz_125[5] = _zz_124; - _zz_125[4] = _zz_124; - _zz_125[3] = _zz_124; - _zz_125[2] = _zz_124; - _zz_125[1] = _zz_124; - _zz_125[0] = _zz_124; + _zz_130[19] = _zz_129; + _zz_130[18] = _zz_129; + _zz_130[17] = _zz_129; + _zz_130[16] = _zz_129; + _zz_130[15] = _zz_129; + _zz_130[14] = _zz_129; + _zz_130[13] = _zz_129; + _zz_130[12] = _zz_129; + _zz_130[11] = _zz_129; + _zz_130[10] = _zz_129; + _zz_130[9] = _zz_129; + _zz_130[8] = _zz_129; + _zz_130[7] = _zz_129; + _zz_130[6] = _zz_129; + _zz_130[5] = _zz_129; + _zz_130[4] = _zz_129; + _zz_130[3] = _zz_129; + _zz_130[2] = _zz_129; + _zz_130[1] = _zz_129; + _zz_130[0] = _zz_129; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_125,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_130,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_127,{{{_zz_523,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_129,{{{_zz_524,_zz_525},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_132,{{{_zz_528,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_134,{{{_zz_529,_zz_530},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_305}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_310}; end end endcase end - assign _zz_126 = _zz_303[19]; - always @ (*) begin - _zz_127[10] = _zz_126; - _zz_127[9] = _zz_126; - _zz_127[8] = _zz_126; - _zz_127[7] = _zz_126; - _zz_127[6] = _zz_126; - _zz_127[5] = _zz_126; - _zz_127[4] = _zz_126; - _zz_127[3] = _zz_126; - _zz_127[2] = _zz_126; - _zz_127[1] = _zz_126; - _zz_127[0] = _zz_126; - end - - assign _zz_128 = _zz_304[11]; - always @ (*) begin - _zz_129[18] = _zz_128; - _zz_129[17] = _zz_128; - _zz_129[16] = _zz_128; - _zz_129[15] = _zz_128; - _zz_129[14] = _zz_128; - _zz_129[13] = _zz_128; - _zz_129[12] = _zz_128; - _zz_129[11] = _zz_128; - _zz_129[10] = _zz_128; - _zz_129[9] = _zz_128; - _zz_129[8] = _zz_128; - _zz_129[7] = _zz_128; - _zz_129[6] = _zz_128; - _zz_129[5] = _zz_128; - _zz_129[4] = _zz_128; - _zz_129[3] = _zz_128; - _zz_129[2] = _zz_128; - _zz_129[1] = _zz_128; - _zz_129[0] = _zz_128; + assign _zz_131 = _zz_308[19]; + always @ (*) begin + _zz_132[10] = _zz_131; + _zz_132[9] = _zz_131; + _zz_132[8] = _zz_131; + _zz_132[7] = _zz_131; + _zz_132[6] = _zz_131; + _zz_132[5] = _zz_131; + _zz_132[4] = _zz_131; + _zz_132[3] = _zz_131; + _zz_132[2] = _zz_131; + _zz_132[1] = _zz_131; + _zz_132[0] = _zz_131; + end + + assign _zz_133 = _zz_309[11]; + always @ (*) begin + _zz_134[18] = _zz_133; + _zz_134[17] = _zz_133; + _zz_134[16] = _zz_133; + _zz_134[15] = _zz_133; + _zz_134[14] = _zz_133; + _zz_134[13] = _zz_133; + _zz_134[12] = _zz_133; + _zz_134[11] = _zz_133; + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -3940,16 +3930,16 @@ module VexRiscv ( end end - assign _zz_130 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_131 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_132 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_135 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_136 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_137 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_133 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_134 = _zz_306[0]; + assign _zz_138 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_139 = _zz_311[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_215)begin + if(_zz_220)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4030,7 +4020,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4136,7 +4126,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_227)begin + if(_zz_232)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4155,20 +4145,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_228)begin + if(_zz_233)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_229)begin + if(_zz_234)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_228)begin + if(_zz_233)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_229)begin + if(_zz_234)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4183,14 +4173,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_227)begin + if(_zz_232)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_227)begin + if(_zz_232)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4199,7 +4189,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_240) + case(_zz_245) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4213,7 +4203,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_230) + case(_zz_235) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4227,7 +4217,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_230) + case(_zz_235) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4246,12 +4236,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_308) + $signed(_zz_309)); + assign writeBack_MulPlugin_result = ($signed(_zz_313) + $signed(_zz_314)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_210)begin - if(_zz_231)begin + if(_zz_215)begin + if(_zz_236)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4259,7 +4249,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_232)begin + if(_zz_237)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4270,28 +4260,28 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_313); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_318); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_135 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_135[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_314); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_315 : _zz_316); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_317[31:0]; - assign _zz_136 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_137 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_138 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_140 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_140[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_319); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_320 : _zz_321); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_322[31:0]; + assign _zz_141 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_142 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_143 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_139[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_139[31 : 0] = execute_RS1; + _zz_144[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_144[31 : 0] = execute_RS1; end - assign _zz_141 = (_zz_140 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_141 != 32'h0); + assign _zz_146 = (_zz_145 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_146 != 32'h0); assign _zz_26 = decode_SRC1_CTRL; assign _zz_24 = _zz_49; assign _zz_37 = decode_to_execute_SRC1_CTRL; @@ -4340,216 +4330,216 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_142 = 32'h0; + _zz_147 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_142[12 : 0] = 13'h1000; - _zz_142[25 : 20] = 6'h20; + _zz_147[12 : 0] = 13'h1000; + _zz_147[25 : 20] = 6'h20; end end always @ (*) begin - _zz_143 = 32'h0; + _zz_148 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_143[3 : 0] = 4'b1011; + _zz_148[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_144 = 32'h0; + _zz_149 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_144[4 : 0] = 5'h16; + _zz_149[4 : 0] = 5'h16; end end always @ (*) begin - _zz_145 = 32'h0; + _zz_150 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_145[5 : 0] = 6'h21; + _zz_150[5 : 0] = 6'h21; end end always @ (*) begin - _zz_146 = 32'h0; + _zz_151 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_146[31 : 30] = CsrPlugin_misa_base; - _zz_146[25 : 0] = CsrPlugin_misa_extensions; + _zz_151[31 : 30] = CsrPlugin_misa_base; + _zz_151[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_147 = 32'h0; + _zz_152 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_147[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_147[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_147[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_152[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_152[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_152[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_148 = 32'h0; + _zz_153 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_148[11 : 11] = CsrPlugin_mip_MEIP; - _zz_148[7 : 7] = CsrPlugin_mip_MTIP; - _zz_148[3 : 3] = CsrPlugin_mip_MSIP; + _zz_153[11 : 11] = CsrPlugin_mip_MEIP; + _zz_153[7 : 7] = CsrPlugin_mip_MTIP; + _zz_153[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_149 = 32'h0; + _zz_154 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_149[11 : 11] = CsrPlugin_mie_MEIE; - _zz_149[7 : 7] = CsrPlugin_mie_MTIE; - _zz_149[3 : 3] = CsrPlugin_mie_MSIE; + _zz_154[11 : 11] = CsrPlugin_mie_MEIE; + _zz_154[7 : 7] = CsrPlugin_mie_MTIE; + _zz_154[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_150 = 32'h0; + _zz_155 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_150[31 : 2] = CsrPlugin_mtvec_base; - _zz_150[1 : 0] = CsrPlugin_mtvec_mode; + _zz_155[31 : 2] = CsrPlugin_mtvec_base; + _zz_155[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_151 = 32'h0; + _zz_156 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_151[31 : 0] = CsrPlugin_mepc; + _zz_156[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_152 = 32'h0; + _zz_157 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_152[31 : 0] = CsrPlugin_mscratch; + _zz_157[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_153 = 32'h0; + _zz_158 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_153[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_153[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_158[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_158[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_154 = 32'h0; + _zz_159 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_154[31 : 0] = CsrPlugin_mtval; + _zz_159[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_155 = 32'h0; + _zz_160 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_155[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_160[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_156 = 32'h0; + _zz_161 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_156[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_161[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_157 = 32'h0; + _zz_162 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_157[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_162[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_158 = 32'h0; + _zz_163 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_158[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_163[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_159 = 32'h0; + _zz_164 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_159[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_164[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_160 = 32'h0; + _zz_165 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_160[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_165[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_161 = 32'h0; + _zz_166 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_161[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_166[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_162 = 32'h0; + _zz_167 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_162[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_167[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_163 = 32'h0; + _zz_168 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_163[31 : 0] = _zz_140; + _zz_168[31 : 0] = _zz_145; end end always @ (*) begin - _zz_164 = 32'h0; + _zz_169 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_164[31 : 0] = _zz_141; + _zz_169[31 : 0] = _zz_146; end end - assign execute_CsrPlugin_readData = (((((_zz_142 | _zz_143) | (_zz_144 | _zz_145)) | ((_zz_526 | _zz_146) | (_zz_147 | _zz_148))) | (((_zz_149 | _zz_150) | (_zz_151 | _zz_152)) | ((_zz_153 | _zz_154) | (_zz_155 | _zz_156)))) | (((_zz_157 | _zz_158) | (_zz_159 | _zz_160)) | ((_zz_161 | _zz_162) | (_zz_163 | _zz_164)))); - assign iBusWishbone_ADR = {_zz_334,_zz_165}; - assign iBusWishbone_CTI = ((_zz_165 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_147 | _zz_148) | (_zz_149 | _zz_150)) | ((_zz_531 | _zz_151) | (_zz_152 | _zz_153))) | (((_zz_154 | _zz_155) | (_zz_156 | _zz_157)) | ((_zz_158 | _zz_159) | (_zz_160 | _zz_161)))) | (((_zz_162 | _zz_163) | (_zz_164 | _zz_165)) | ((_zz_166 | _zz_167) | (_zz_168 | _zz_169)))); + assign iBusWishbone_ADR = {_zz_339,_zz_170}; + assign iBusWishbone_CTI = ((_zz_170 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_233)begin + if(_zz_238)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_233)begin + if(_zz_238)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_166; + assign iBus_rsp_valid = _zz_171; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_172 = (dBus_cmd_payload_length != 3'b000); - assign _zz_168 = dBus_cmd_valid; - assign _zz_170 = dBus_cmd_payload_wr; - assign _zz_171 = (_zz_167 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_169 && (_zz_170 || _zz_171)); - assign dBusWishbone_ADR = ((_zz_172 ? {{dBus_cmd_payload_address[31 : 5],_zz_167},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_172 ? (_zz_171 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_177 = (dBus_cmd_payload_length != 3'b000); + assign _zz_173 = dBus_cmd_valid; + assign _zz_175 = dBus_cmd_payload_wr; + assign _zz_176 = (_zz_172 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_174 && (_zz_175 || _zz_176)); + assign dBusWishbone_ADR = ((_zz_177 ? {{dBus_cmd_payload_address[31 : 5],_zz_172},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_177 ? (_zz_176 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_170 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_170; + assign dBusWishbone_SEL = (_zz_175 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_175; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_169 = (_zz_168 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_168; - assign dBusWishbone_STB = _zz_168; - assign dBus_rsp_valid = _zz_173; + assign _zz_174 = (_zz_173 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_173; + assign dBusWishbone_STB = _zz_173; + assign dBus_rsp_valid = _zz_178; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4572,7 +4562,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= _zz_80; DBusCachedPlugin_rspCounter <= 32'h0; _zz_98 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_110 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4593,14 +4583,14 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_140 <= 32'h0; + _zz_145 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_165 <= 3'b000; - _zz_166 <= 1'b0; - _zz_167 <= 3'b000; - _zz_173 <= 1'b0; + _zz_170 <= 3'b000; + _zz_171 <= 1'b0; + _zz_172 <= 3'b000; + _zz_178 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -4681,7 +4671,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_234)begin + if(_zz_239)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -4691,7 +4681,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end _zz_98 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_110 <= (_zz_41 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4713,14 +4703,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_235)begin - if(_zz_236)begin + if(_zz_240)begin + if(_zz_241)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_237)begin + if(_zz_242)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_238)begin + if(_zz_243)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4745,7 +4735,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_217)begin + if(_zz_222)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4756,8 +4746,8 @@ module VexRiscv ( end endcase end - if(_zz_218)begin - case(_zz_219) + if(_zz_223)begin + case(_zz_224) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4767,7 +4757,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_132,{_zz_131,_zz_130}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_137,{_zz_136,_zz_135}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; @@ -4796,35 +4786,35 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_327[0]; - CsrPlugin_mstatus_MIE <= _zz_328[0]; + CsrPlugin_mstatus_MPIE <= _zz_332[0]; + CsrPlugin_mstatus_MIE <= _zz_333[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_330[0]; - CsrPlugin_mie_MTIE <= _zz_331[0]; - CsrPlugin_mie_MSIE <= _zz_332[0]; + CsrPlugin_mie_MEIE <= _zz_335[0]; + CsrPlugin_mie_MTIE <= _zz_336[0]; + CsrPlugin_mie_MSIE <= _zz_337[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_140 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_145 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_233)begin + if(_zz_238)begin if(iBusWishbone_ACK)begin - _zz_165 <= (_zz_165 + 3'b001); + _zz_170 <= (_zz_170 + 3'b001); end end - _zz_166 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_168 && _zz_169))begin - _zz_167 <= (_zz_167 + 3'b001); - if(_zz_171)begin - _zz_167 <= 3'b000; + _zz_171 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_173 && _zz_174))begin + _zz_172 <= (_zz_172 + 3'b001); + if(_zz_176)begin + _zz_172 <= 3'b000; end end - _zz_173 <= ((_zz_168 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_178 <= ((_zz_173 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -4838,7 +4828,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_234)begin + if(_zz_239)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -4856,8 +4846,8 @@ module VexRiscv ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_111 <= _zz_40[11 : 7]; + _zz_112 <= _zz_50; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -4865,9 +4855,9 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_215)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_134 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_134 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_220)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_139 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_139 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -4881,21 +4871,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_235)begin - if(_zz_236)begin + if(_zz_240)begin + if(_zz_241)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_237)begin + if(_zz_242)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_238)begin + if(_zz_243)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_217)begin + if(_zz_222)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4915,20 +4905,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_210)begin - if(_zz_231)begin + if(_zz_215)begin + if(_zz_236)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_318[31:0]; + memory_DivPlugin_div_result <= _zz_323[31:0]; end end end - if(_zz_232)begin + if(_zz_237)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_138 ? (~ _zz_139) : _zz_139) + _zz_324); - memory_DivPlugin_rs2 <= ((_zz_137 ? (~ execute_RS2) : execute_RS2) + _zz_326); - memory_DivPlugin_div_needRevert <= ((_zz_138 ^ (_zz_137 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_143 ? (~ _zz_144) : _zz_144) + _zz_329); + memory_DivPlugin_rs2 <= ((_zz_142 ? (~ execute_RS2) : execute_RS2) + _zz_331); + memory_DivPlugin_div_needRevert <= ((_zz_143 ^ (_zz_142 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5191,7 +5181,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_329[0]; + CsrPlugin_mip_MSIP <= _zz_334[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5212,7 +5202,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_333[0]; + CsrPlugin_mcause_interrupt <= _zz_338[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5531,7 +5521,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_12)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -5545,7 +5535,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_12)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -5575,7 +5565,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -5602,7 +5592,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -5634,7 +5624,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -5644,7 +5634,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index f2b8055..29f4f6f 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define Input2Kind_defaultEncoding_type [0:0] @@ -87,37 +87,37 @@ module VexRiscv_inner ( input clk, input reset ); - wire _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; wire _zz_217; - reg _zz_218; + wire _zz_218; wire _zz_219; - wire [31:0] _zz_220; + wire _zz_220; wire _zz_221; - wire [31:0] _zz_222; - reg _zz_223; + wire _zz_222; + wire _zz_223; wire _zz_224; - wire _zz_225; - wire [31:0] _zz_226; - wire _zz_227; + reg _zz_225; + wire _zz_226; + wire [31:0] _zz_227; wire _zz_228; - wire _zz_229; - wire _zz_230; + wire [31:0] _zz_229; + reg _zz_230; wire _zz_231; wire _zz_232; - wire _zz_233; + wire [31:0] _zz_233; wire _zz_234; - wire [3:0] _zz_235; + wire _zz_235; wire _zz_236; wire _zz_237; - reg [31:0] _zz_238; - reg [31:0] _zz_239; - reg [31:0] _zz_240; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire [3:0] _zz_242; + wire _zz_243; + wire _zz_244; + reg [31:0] _zz_245; + reg [31:0] _zz_246; + reg [31:0] _zz_247; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -150,13 +150,6 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire _zz_245; - wire _zz_246; - wire _zz_247; wire _zz_248; wire _zz_249; wire _zz_250; @@ -165,49 +158,49 @@ module VexRiscv_inner ( wire _zz_253; wire _zz_254; wire _zz_255; - wire [1:0] _zz_256; + wire _zz_256; wire _zz_257; wire _zz_258; wire _zz_259; wire _zz_260; wire _zz_261; wire _zz_262; - wire _zz_263; + wire [1:0] _zz_263; wire _zz_264; wire _zz_265; wire _zz_266; - wire [1:0] _zz_267; + wire _zz_267; wire _zz_268; wire _zz_269; wire _zz_270; wire _zz_271; wire _zz_272; wire _zz_273; - wire _zz_274; + wire [1:0] _zz_274; wire _zz_275; wire _zz_276; - wire [1:0] _zz_277; + wire _zz_277; wire _zz_278; - wire [1:0] _zz_279; - wire [51:0] _zz_280; - wire [51:0] _zz_281; - wire [51:0] _zz_282; - wire [32:0] _zz_283; - wire [51:0] _zz_284; - wire [49:0] _zz_285; - wire [51:0] _zz_286; - wire [49:0] _zz_287; + wire _zz_279; + wire _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire [1:0] _zz_284; + wire _zz_285; + wire [1:0] _zz_286; + wire [51:0] _zz_287; wire [51:0] _zz_288; - wire [32:0] _zz_289; - wire [31:0] _zz_290; - wire [32:0] _zz_291; - wire [0:0] _zz_292; - wire [0:0] _zz_293; - wire [0:0] _zz_294; - wire [0:0] _zz_295; - wire [0:0] _zz_296; - wire [0:0] _zz_297; - wire [0:0] _zz_298; + wire [51:0] _zz_289; + wire [32:0] _zz_290; + wire [51:0] _zz_291; + wire [49:0] _zz_292; + wire [51:0] _zz_293; + wire [49:0] _zz_294; + wire [51:0] _zz_295; + wire [32:0] _zz_296; + wire [31:0] _zz_297; + wire [32:0] _zz_298; wire [0:0] _zz_299; wire [0:0] _zz_300; wire [0:0] _zz_301; @@ -219,276 +212,284 @@ module VexRiscv_inner ( wire [0:0] _zz_307; wire [0:0] _zz_308; wire [0:0] _zz_309; - wire [3:0] _zz_310; - wire [2:0] _zz_311; - wire [31:0] _zz_312; - wire [11:0] _zz_313; - wire [31:0] _zz_314; - wire [19:0] _zz_315; - wire [11:0] _zz_316; - wire [31:0] _zz_317; - wire [31:0] _zz_318; - wire [19:0] _zz_319; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [3:0] _zz_317; + wire [2:0] _zz_318; + wire [31:0] _zz_319; wire [11:0] _zz_320; - wire [2:0] _zz_321; - wire [2:0] _zz_322; - wire [0:0] _zz_323; - wire [2:0] _zz_324; - wire [4:0] _zz_325; - wire [11:0] _zz_326; + wire [31:0] _zz_321; + wire [19:0] _zz_322; + wire [11:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [19:0] _zz_326; wire [11:0] _zz_327; - wire [31:0] _zz_328; - wire [31:0] _zz_329; - wire [31:0] _zz_330; - wire [31:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [31:0] _zz_334; - wire [11:0] _zz_335; - wire [19:0] _zz_336; - wire [11:0] _zz_337; + wire [2:0] _zz_328; + wire [2:0] _zz_329; + wire [0:0] _zz_330; + wire [2:0] _zz_331; + wire [4:0] _zz_332; + wire [11:0] _zz_333; + wire [11:0] _zz_334; + wire [31:0] _zz_335; + wire [31:0] _zz_336; + wire [31:0] _zz_337; wire [31:0] _zz_338; wire [31:0] _zz_339; wire [31:0] _zz_340; - wire [11:0] _zz_341; - wire [19:0] _zz_342; - wire [11:0] _zz_343; - wire [2:0] _zz_344; - wire [1:0] _zz_345; - wire [1:0] _zz_346; - wire [1:0] _zz_347; - wire [1:0] _zz_348; + wire [31:0] _zz_341; + wire [11:0] _zz_342; + wire [19:0] _zz_343; + wire [11:0] _zz_344; + wire [31:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [11:0] _zz_348; wire [19:0] _zz_349; wire [11:0] _zz_350; - wire [65:0] _zz_351; - wire [65:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire [0:0] _zz_355; - wire [5:0] _zz_356; - wire [32:0] _zz_357; - wire [31:0] _zz_358; - wire [31:0] _zz_359; - wire [32:0] _zz_360; - wire [32:0] _zz_361; - wire [32:0] _zz_362; - wire [32:0] _zz_363; - wire [0:0] _zz_364; - wire [32:0] _zz_365; - wire [0:0] _zz_366; + wire [2:0] _zz_351; + wire [1:0] _zz_352; + wire [1:0] _zz_353; + wire [1:0] _zz_354; + wire [1:0] _zz_355; + wire [19:0] _zz_356; + wire [11:0] _zz_357; + wire [65:0] _zz_358; + wire [65:0] _zz_359; + wire [31:0] _zz_360; + wire [31:0] _zz_361; + wire [0:0] _zz_362; + wire [5:0] _zz_363; + wire [32:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; wire [32:0] _zz_367; - wire [0:0] _zz_368; - wire [31:0] _zz_369; - wire [0:0] _zz_370; + wire [32:0] _zz_368; + wire [32:0] _zz_369; + wire [32:0] _zz_370; wire [0:0] _zz_371; - wire [0:0] _zz_372; + wire [32:0] _zz_372; wire [0:0] _zz_373; - wire [0:0] _zz_374; + wire [32:0] _zz_374; wire [0:0] _zz_375; - wire [0:0] _zz_376; - wire [26:0] _zz_377; - wire _zz_378; - wire _zz_379; - wire [1:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire _zz_384; - wire [0:0] _zz_385; - wire [14:0] _zz_386; - wire [31:0] _zz_387; + wire [31:0] _zz_376; + wire [0:0] _zz_377; + wire [0:0] _zz_378; + wire [0:0] _zz_379; + wire [0:0] _zz_380; + wire [0:0] _zz_381; + wire [0:0] _zz_382; + wire [0:0] _zz_383; + wire [26:0] _zz_384; + wire _zz_385; + wire _zz_386; + wire [1:0] _zz_387; wire [31:0] _zz_388; wire [31:0] _zz_389; - wire _zz_390; - wire [0:0] _zz_391; - wire [8:0] _zz_392; - wire [31:0] _zz_393; + wire [31:0] _zz_390; + wire _zz_391; + wire [0:0] _zz_392; + wire [14:0] _zz_393; wire [31:0] _zz_394; wire [31:0] _zz_395; - wire _zz_396; - wire [0:0] _zz_397; - wire [2:0] _zz_398; - wire _zz_399; - wire _zz_400; - wire _zz_401; + wire [31:0] _zz_396; + wire _zz_397; + wire [0:0] _zz_398; + wire [8:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [26:0] _zz_407; - wire [31:0] _zz_408; + wire _zz_403; + wire [0:0] _zz_404; + wire [2:0] _zz_405; + wire _zz_406; + wire _zz_407; + wire _zz_408; wire [31:0] _zz_409; wire [31:0] _zz_410; - wire [0:0] _zz_411; - wire [0:0] _zz_412; - wire [1:0] _zz_413; - wire [1:0] _zz_414; - wire _zz_415; - wire [0:0] _zz_416; - wire [21:0] _zz_417; - wire [31:0] _zz_418; - wire [31:0] _zz_419; - wire [31:0] _zz_420; - wire [31:0] _zz_421; - wire [31:0] _zz_422; - wire [31:0] _zz_423; - wire [0:0] _zz_424; - wire [0:0] _zz_425; - wire [2:0] _zz_426; - wire [2:0] _zz_427; - wire _zz_428; - wire [0:0] _zz_429; - wire [18:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire [31:0] _zz_433; - wire [31:0] _zz_434; + wire _zz_411; + wire _zz_412; + wire [0:0] _zz_413; + wire [26:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire [1:0] _zz_420; + wire [1:0] _zz_421; + wire _zz_422; + wire [0:0] _zz_423; + wire [21:0] _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire [31:0] _zz_427; + wire [31:0] _zz_428; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire [0:0] _zz_431; + wire [0:0] _zz_432; + wire [2:0] _zz_433; + wire [2:0] _zz_434; wire _zz_435; - wire _zz_436; - wire [31:0] _zz_437; + wire [0:0] _zz_436; + wire [18:0] _zz_437; wire [31:0] _zz_438; - wire _zz_439; - wire [0:0] _zz_440; - wire [0:0] _zz_441; + wire [31:0] _zz_439; + wire [31:0] _zz_440; + wire [31:0] _zz_441; wire _zz_442; - wire [0:0] _zz_443; - wire [15:0] _zz_444; + wire _zz_443; + wire [31:0] _zz_444; wire [31:0] _zz_445; wire _zz_446; - wire _zz_447; - wire _zz_448; - wire [2:0] _zz_449; - wire [2:0] _zz_450; - wire _zz_451; - wire [0:0] _zz_452; - wire [12:0] _zz_453; + wire [0:0] _zz_447; + wire [0:0] _zz_448; + wire _zz_449; + wire [0:0] _zz_450; + wire [15:0] _zz_451; + wire [31:0] _zz_452; + wire _zz_453; wire _zz_454; wire _zz_455; - wire _zz_456; - wire [0:0] _zz_457; - wire [2:0] _zz_458; - wire _zz_459; - wire [5:0] _zz_460; - wire [5:0] _zz_461; + wire [2:0] _zz_456; + wire [2:0] _zz_457; + wire _zz_458; + wire [0:0] _zz_459; + wire [12:0] _zz_460; + wire _zz_461; wire _zz_462; - wire [0:0] _zz_463; - wire [9:0] _zz_464; - wire [31:0] _zz_465; - wire [31:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire _zz_470; - wire [0:0] _zz_471; - wire [0:0] _zz_472; + wire _zz_463; + wire [0:0] _zz_464; + wire [2:0] _zz_465; + wire _zz_466; + wire [5:0] _zz_467; + wire [5:0] _zz_468; + wire _zz_469; + wire [0:0] _zz_470; + wire [9:0] _zz_471; + wire [31:0] _zz_472; wire [31:0] _zz_473; - wire _zz_474; - wire [0:0] _zz_475; - wire [3:0] _zz_476; - wire [0:0] _zz_477; - wire [3:0] _zz_478; - wire [5:0] _zz_479; - wire [5:0] _zz_480; + wire [31:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; + wire _zz_477; + wire [0:0] _zz_478; + wire [0:0] _zz_479; + wire [31:0] _zz_480; wire _zz_481; wire [0:0] _zz_482; - wire [7:0] _zz_483; - wire [31:0] _zz_484; - wire [31:0] _zz_485; - wire [31:0] _zz_486; - wire [31:0] _zz_487; - wire [31:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; + wire [3:0] _zz_483; + wire [0:0] _zz_484; + wire [3:0] _zz_485; + wire [5:0] _zz_486; + wire [5:0] _zz_487; + wire _zz_488; + wire [0:0] _zz_489; + wire [7:0] _zz_490; wire [31:0] _zz_491; - wire [0:0] _zz_492; - wire [1:0] _zz_493; - wire _zz_494; - wire [0:0] _zz_495; - wire [1:0] _zz_496; - wire [0:0] _zz_497; - wire [3:0] _zz_498; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire [31:0] _zz_497; + wire [31:0] _zz_498; wire [0:0] _zz_499; - wire [0:0] _zz_500; - wire [1:0] _zz_501; - wire [1:0] _zz_502; - wire _zz_503; + wire [1:0] _zz_500; + wire _zz_501; + wire [0:0] _zz_502; + wire [1:0] _zz_503; wire [0:0] _zz_504; - wire [5:0] _zz_505; - wire [31:0] _zz_506; - wire [31:0] _zz_507; - wire _zz_508; - wire _zz_509; - wire [31:0] _zz_510; - wire [31:0] _zz_511; - wire [31:0] _zz_512; - wire _zz_513; - wire _zz_514; - wire [31:0] _zz_515; - wire [31:0] _zz_516; - wire _zz_517; - wire [0:0] _zz_518; - wire [1:0] _zz_519; - wire [31:0] _zz_520; - wire [31:0] _zz_521; - wire _zz_522; - wire _zz_523; - wire [0:0] _zz_524; + wire [3:0] _zz_505; + wire [0:0] _zz_506; + wire [0:0] _zz_507; + wire [1:0] _zz_508; + wire [1:0] _zz_509; + wire _zz_510; + wire [0:0] _zz_511; + wire [5:0] _zz_512; + wire [31:0] _zz_513; + wire [31:0] _zz_514; + wire _zz_515; + wire _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire _zz_520; + wire _zz_521; + wire [31:0] _zz_522; + wire [31:0] _zz_523; + wire _zz_524; wire [0:0] _zz_525; - wire _zz_526; - wire [0:0] _zz_527; - wire [3:0] _zz_528; - wire [31:0] _zz_529; - wire [31:0] _zz_530; - wire [31:0] _zz_531; - wire [31:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire [31:0] _zz_535; - wire _zz_536; - wire _zz_537; + wire [1:0] _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; + wire _zz_529; + wire _zz_530; + wire [0:0] _zz_531; + wire [0:0] _zz_532; + wire _zz_533; + wire [0:0] _zz_534; + wire [3:0] _zz_535; + wire [31:0] _zz_536; + wire [31:0] _zz_537; wire [31:0] _zz_538; wire [31:0] _zz_539; wire [31:0] _zz_540; wire [31:0] _zz_541; - wire [0:0] _zz_542; - wire [2:0] _zz_543; - wire [0:0] _zz_544; - wire [0:0] _zz_545; - wire _zz_546; - wire [0:0] _zz_547; - wire [1:0] _zz_548; - wire [31:0] _zz_549; - wire [31:0] _zz_550; - wire [31:0] _zz_551; - wire _zz_552; + wire [31:0] _zz_542; + wire _zz_543; + wire _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; + wire [0:0] _zz_549; + wire [2:0] _zz_550; + wire [0:0] _zz_551; + wire [0:0] _zz_552; wire _zz_553; - wire [31:0] _zz_554; - wire _zz_555; - wire [0:0] _zz_556; - wire [0:0] _zz_557; - wire [0:0] _zz_558; - wire [0:0] _zz_559; - wire [1:0] _zz_560; - wire [1:0] _zz_561; - wire [0:0] _zz_562; + wire [0:0] _zz_554; + wire [1:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire _zz_559; + wire _zz_560; + wire [31:0] _zz_561; + wire _zz_562; wire [0:0] _zz_563; - wire [31:0] _zz_564; - wire [31:0] _zz_565; - wire [31:0] _zz_566; - wire [31:0] _zz_567; - wire [31:0] _zz_568; - wire [31:0] _zz_569; - wire _zz_570; - wire _zz_571; - wire _zz_572; + wire [0:0] _zz_564; + wire [0:0] _zz_565; + wire [0:0] _zz_566; + wire [1:0] _zz_567; + wire [1:0] _zz_568; + wire [0:0] _zz_569; + wire [0:0] _zz_570; + wire [31:0] _zz_571; + wire [31:0] _zz_572; wire [31:0] _zz_573; + wire [31:0] _zz_574; + wire [31:0] _zz_575; + wire [31:0] _zz_576; + wire _zz_577; + wire _zz_578; + wire _zz_579; + wire [31:0] _zz_580; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -567,19 +568,21 @@ module VexRiscv_inner ( wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; + reg _zz_30; + reg _zz_31; wire memory_CfuPlugin_CFU_IN_FLIGHT; wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_ENCODING; - wire `Input2Kind_defaultEncoding_type _zz_30; + wire `Input2Kind_defaultEncoding_type _zz_32; wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_31; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_32; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; @@ -587,10 +590,10 @@ module VexRiscv_inner ( (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_34; + wire `BranchCtrlEnum_defaultEncoding_type _zz_36; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_35; + reg [31:0] _zz_37; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -600,44 +603,44 @@ module VexRiscv_inner ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_36; + reg [31:0] _zz_38; wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_37; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_38; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_39; + wire [31:0] _zz_41; wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_40; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42; wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_41; + wire `Src1CtrlEnum_defaultEncoding_type _zz_43; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_42; + wire `AluCtrlEnum_defaultEncoding_type _zz_44; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; - wire [31:0] _zz_44; - wire _zz_45; - reg _zz_46; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; + wire [31:0] _zz_46; + wire _zz_47; + reg _zz_48; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_47; - wire `EnvCtrlEnum_defaultEncoding_type _zz_48; - wire `BranchCtrlEnum_defaultEncoding_type _zz_49; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_50; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_51; - wire `Src2CtrlEnum_defaultEncoding_type _zz_52; - wire `AluCtrlEnum_defaultEncoding_type _zz_53; - wire `Src1CtrlEnum_defaultEncoding_type _zz_54; - reg [31:0] _zz_55; + wire `Input2Kind_defaultEncoding_type _zz_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; + wire `Src2CtrlEnum_defaultEncoding_type _zz_54; + wire `AluCtrlEnum_defaultEncoding_type _zz_55; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56; + reg [31:0] _zz_57; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire writeBack_MEMORY_WR; wire [31:0] writeBack_REGFILE_WRITE_DATA; @@ -658,10 +661,10 @@ module VexRiscv_inner ( reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_56; + wire `BranchCtrlEnum_defaultEncoding_type _zz_58; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_57; - reg [31:0] _zz_58; + reg [31:0] _zz_59; + reg [31:0] _zz_60; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -805,11 +808,11 @@ module VexRiscv_inner ( wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_59; - wire [3:0] _zz_60; - wire _zz_61; - wire _zz_62; + wire [3:0] _zz_61; + wire [3:0] _zz_62; wire _zz_63; + wire _zz_64; + wire _zz_65; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; @@ -846,16 +849,16 @@ module VexRiscv_inner ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_64; - wire _zz_65; wire _zz_66; - wire IBusCachedPlugin_iBusRsp_flush; wire _zz_67; wire _zz_68; - reg _zz_69; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_69; wire _zz_70; reg _zz_71; - reg [31:0] _zz_72; + wire _zz_72; + reg _zz_73; + reg [31:0] _zz_74; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -868,17 +871,17 @@ module VexRiscv_inner ( reg IBusCachedPlugin_injector_nextPcCalc_valids_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_73; - reg [18:0] _zz_74; wire _zz_75; - reg [10:0] _zz_76; + reg [18:0] _zz_76; wire _zz_77; - reg [18:0] _zz_78; - reg _zz_79; - wire _zz_80; - reg [10:0] _zz_81; + reg [10:0] _zz_78; + wire _zz_79; + reg [18:0] _zz_80; + reg _zz_81; wire _zz_82; - reg [18:0] _zz_83; + reg [10:0] _zz_83; + wire _zz_84; + reg [18:0] _zz_85; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -886,7 +889,7 @@ module VexRiscv_inner ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_84; + wire [31:0] _zz_86; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -928,30 +931,30 @@ module VexRiscv_inner ( reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_85; + wire [31:0] _zz_87; reg [31:0] DBusCachedPlugin_rspCounter; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_86; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_87; reg [31:0] _zz_88; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; wire _zz_89; reg [31:0] _zz_90; + wire _zz_91; + reg [31:0] _zz_92; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [33:0] _zz_91; - wire _zz_92; - wire _zz_93; + wire [33:0] _zz_93; wire _zz_94; wire _zz_95; wire _zz_96; - wire `Src1CtrlEnum_defaultEncoding_type _zz_97; - wire `AluCtrlEnum_defaultEncoding_type _zz_98; - wire `Src2CtrlEnum_defaultEncoding_type _zz_99; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_100; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_101; - wire `BranchCtrlEnum_defaultEncoding_type _zz_102; - wire `EnvCtrlEnum_defaultEncoding_type _zz_103; - wire `Input2Kind_defaultEncoding_type _zz_104; + wire _zz_97; + wire _zz_98; + wire `Src1CtrlEnum_defaultEncoding_type _zz_99; + wire `AluCtrlEnum_defaultEncoding_type _zz_100; + wire `Src2CtrlEnum_defaultEncoding_type _zz_101; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_102; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_103; + wire `BranchCtrlEnum_defaultEncoding_type _zz_104; + wire `EnvCtrlEnum_defaultEncoding_type _zz_105; + wire `Input2Kind_defaultEncoding_type _zz_106; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -959,57 +962,52 @@ module VexRiscv_inner ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_105; + reg _zz_107; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_106; - reg [31:0] _zz_107; - wire _zz_108; - reg [19:0] _zz_109; + reg [31:0] _zz_108; + reg [31:0] _zz_109; wire _zz_110; reg [19:0] _zz_111; - reg [31:0] _zz_112; + wire _zz_112; + reg [19:0] _zz_113; + reg [31:0] _zz_114; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_113; + reg [31:0] _zz_115; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_114; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_115; - wire _zz_116; - wire _zz_117; - wire _zz_118; - wire _zz_119; - wire _zz_120; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_121; - reg _zz_122; - reg _zz_123; + reg [31:0] _zz_116; + reg _zz_117; + reg _zz_118; + reg _zz_119; + reg [4:0] _zz_120; + reg [31:0] _zz_121; + wire _zz_122; + wire _zz_123; wire _zz_124; - reg [19:0] _zz_125; + wire _zz_125; wire _zz_126; - reg [10:0] _zz_127; - wire _zz_128; - reg [18:0] _zz_129; + wire _zz_127; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_128; + reg _zz_129; reg _zz_130; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; wire _zz_131; reg [19:0] _zz_132; wire _zz_133; reg [10:0] _zz_134; wire _zz_135; reg [18:0] _zz_136; + reg _zz_137; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_138; + reg [19:0] _zz_139; + wire _zz_140; + reg [10:0] _zz_141; + wire _zz_142; + reg [18:0] _zz_143; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1031,9 +1029,9 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_137; - wire _zz_138; - wire _zz_139; + wire _zz_144; + wire _zz_145; + wire _zz_146; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1046,10 +1044,10 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_140; - wire _zz_141; - wire [1:0] _zz_142; - wire _zz_143; + wire [1:0] _zz_147; + wire _zz_148; + wire [1:0] _zz_149; + wire _zz_150; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1078,13 +1076,6 @@ module VexRiscv_inner ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_144; - reg [31:0] _zz_145; - reg [31:0] _zz_146; - reg [31:0] _zz_147; - reg [31:0] _zz_148; - reg [31:0] _zz_149; - reg [31:0] _zz_150; reg [31:0] _zz_151; reg [31:0] _zz_152; reg [31:0] _zz_153; @@ -1094,13 +1085,20 @@ module VexRiscv_inner ( reg [31:0] _zz_157; reg [31:0] _zz_158; reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [19:0] execute_CfuPlugin_functionsIds_0; - wire _zz_160; - reg [19:0] _zz_161; - reg [31:0] _zz_162; + wire _zz_167; + reg [19:0] _zz_168; + reg [31:0] _zz_169; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1132,18 +1130,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_163; + wire [31:0] _zz_170; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_164; - wire _zz_165; - wire _zz_166; - reg [32:0] _zz_167; + wire [31:0] _zz_171; + wire _zz_172; + wire _zz_173; + reg [32:0] _zz_174; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_168; - wire [31:0] _zz_169; + reg [31:0] _zz_175; + wire [31:0] _zz_176; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1203,6 +1201,7 @@ module VexRiscv_inner ( reg execute_to_memory_BRANCH_DO; reg [31:0] execute_to_memory_BRANCH_CALC; reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; reg [31:0] execute_to_memory_MUL_LL; reg [33:0] execute_to_memory_MUL_LH; reg [33:0] execute_to_memory_MUL_HL; @@ -1249,13 +1248,6 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; reg [31:0] _zz_177; reg [31:0] _zz_178; reg [31:0] _zz_179; @@ -1280,16 +1272,23 @@ module VexRiscv_inner ( reg [31:0] _zz_198; reg [31:0] _zz_199; reg [31:0] _zz_200; - reg [2:0] _zz_201; - reg _zz_202; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_203; - wire _zz_204; - wire _zz_205; - wire _zz_206; - wire _zz_207; - wire _zz_208; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + reg [2:0] _zz_208; reg _zz_209; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + reg _zz_216; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; @@ -1329,45 +1328,45 @@ module VexRiscv_inner ( reg [95:0] _zz_28_string; reg [95:0] _zz_29_string; reg [39:0] execute_CfuPlugin_CFU_ENCODING_string; - reg [39:0] _zz_30_string; + reg [39:0] _zz_32_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_31_string; + reg [39:0] _zz_33_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_32_string; + reg [39:0] _zz_34_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_35_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_34_string; + reg [31:0] _zz_36_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_37_string; + reg [71:0] _zz_39_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_38_string; + reg [71:0] _zz_40_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_40_string; + reg [23:0] _zz_42_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_41_string; + reg [95:0] _zz_43_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_42_string; + reg [63:0] _zz_44_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_43_string; - reg [39:0] _zz_47_string; - reg [39:0] _zz_48_string; - reg [31:0] _zz_49_string; - reg [71:0] _zz_50_string; - reg [39:0] _zz_51_string; - reg [23:0] _zz_52_string; - reg [63:0] _zz_53_string; - reg [95:0] _zz_54_string; + reg [39:0] _zz_45_string; + reg [39:0] _zz_49_string; + reg [39:0] _zz_50_string; + reg [31:0] _zz_51_string; + reg [71:0] _zz_52_string; + reg [39:0] _zz_53_string; + reg [23:0] _zz_54_string; + reg [63:0] _zz_55_string; + reg [95:0] _zz_56_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_56_string; - reg [95:0] _zz_97_string; - reg [63:0] _zz_98_string; - reg [23:0] _zz_99_string; - reg [39:0] _zz_100_string; - reg [71:0] _zz_101_string; - reg [31:0] _zz_102_string; - reg [39:0] _zz_103_string; - reg [39:0] _zz_104_string; + reg [31:0] _zz_58_string; + reg [95:0] _zz_99_string; + reg [63:0] _zz_100_string; + reg [23:0] _zz_101_string; + reg [39:0] _zz_102_string; + reg [71:0] _zz_103_string; + reg [31:0] _zz_104_string; + reg [39:0] _zz_105_string; + reg [39:0] _zz_106_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1383,365 +1382,365 @@ module VexRiscv_inner ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_241 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_242 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_243 = 1'b1; - assign _zz_244 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_245 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_246 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_247 = ((_zz_215 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_248 = ((_zz_215 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_249 = ((_zz_215 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_250 = ((_zz_215 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_251 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_252 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_253 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_254 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_255 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_256 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_257 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_258 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_259 = (1'b0 || (! 1'b1)); - assign _zz_260 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_261 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_262 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_263 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_264 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_265 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_266 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_267 = execute_INSTRUCTION[13 : 12]; - assign _zz_268 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_269 = (! memory_arbitration_isStuck); - assign _zz_270 = (iBus_cmd_valid || (_zz_201 != 3'b000)); - assign _zz_271 = (_zz_237 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_272 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_273 = ((_zz_137 && 1'b1) && (! 1'b0)); - assign _zz_274 = ((_zz_138 && 1'b1) && (! 1'b0)); - assign _zz_275 = ((_zz_139 && 1'b1) && (! 1'b0)); - assign _zz_276 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_277 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_278 = execute_INSTRUCTION[13]; - assign _zz_279 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_280 = ($signed(_zz_281) + $signed(_zz_286)); - assign _zz_281 = ($signed(_zz_282) + $signed(_zz_284)); - assign _zz_282 = 52'h0; - assign _zz_283 = {1'b0,memory_MUL_LL}; - assign _zz_284 = {{19{_zz_283[32]}}, _zz_283}; - assign _zz_285 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_286 = {{2{_zz_285[49]}}, _zz_285}; - assign _zz_287 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_288 = {{2{_zz_287[49]}}, _zz_287}; - assign _zz_289 = ($signed(_zz_291) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_290 = _zz_289[31 : 0]; - assign _zz_291 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_292 = _zz_91[33 : 33]; - assign _zz_293 = _zz_91[32 : 32]; - assign _zz_294 = _zz_91[31 : 31]; - assign _zz_295 = _zz_91[30 : 30]; - assign _zz_296 = _zz_91[28 : 28]; - assign _zz_297 = _zz_91[25 : 25]; - assign _zz_298 = _zz_91[17 : 17]; - assign _zz_299 = _zz_91[16 : 16]; - assign _zz_300 = _zz_91[13 : 13]; - assign _zz_301 = _zz_91[12 : 12]; - assign _zz_302 = _zz_91[11 : 11]; - assign _zz_303 = _zz_91[15 : 15]; - assign _zz_304 = _zz_91[5 : 5]; - assign _zz_305 = _zz_91[3 : 3]; - assign _zz_306 = _zz_91[20 : 20]; - assign _zz_307 = _zz_91[10 : 10]; - assign _zz_308 = _zz_91[4 : 4]; - assign _zz_309 = _zz_91[0 : 0]; - assign _zz_310 = (_zz_59 - 4'b0001); - assign _zz_311 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_312 = {29'd0, _zz_311}; - assign _zz_313 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_314 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_315 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_316 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_317 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_318 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_319 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_248 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_249 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_250 = 1'b1; + assign _zz_251 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_252 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_254 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_255 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_256 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_257 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_260 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_264 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_265 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_266 = (1'b0 || (! 1'b1)); + assign _zz_267 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_268 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_270 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_271 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_272 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_273 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_274 = execute_INSTRUCTION[13 : 12]; + assign _zz_275 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_276 = (! memory_arbitration_isStuck); + assign _zz_277 = (iBus_cmd_valid || (_zz_208 != 3'b000)); + assign _zz_278 = (_zz_244 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_280 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_281 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_282 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_285 = execute_INSTRUCTION[13]; + assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); + assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); + assign _zz_289 = 52'h0; + assign _zz_290 = {1'b0,memory_MUL_LL}; + assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; + assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; + assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; + assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_297 = _zz_296[31 : 0]; + assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_299 = _zz_93[33 : 33]; + assign _zz_300 = _zz_93[32 : 32]; + assign _zz_301 = _zz_93[31 : 31]; + assign _zz_302 = _zz_93[30 : 30]; + assign _zz_303 = _zz_93[28 : 28]; + assign _zz_304 = _zz_93[25 : 25]; + assign _zz_305 = _zz_93[17 : 17]; + assign _zz_306 = _zz_93[16 : 16]; + assign _zz_307 = _zz_93[13 : 13]; + assign _zz_308 = _zz_93[12 : 12]; + assign _zz_309 = _zz_93[11 : 11]; + assign _zz_310 = _zz_93[15 : 15]; + assign _zz_311 = _zz_93[5 : 5]; + assign _zz_312 = _zz_93[3 : 3]; + assign _zz_313 = _zz_93[20 : 20]; + assign _zz_314 = _zz_93[10 : 10]; + assign _zz_315 = _zz_93[4 : 4]; + assign _zz_316 = _zz_93[0 : 0]; + assign _zz_317 = (_zz_61 - 4'b0001); + assign _zz_318 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_319 = {29'd0, _zz_318}; assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_321 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_322 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_323 = execute_SRC_LESS; - assign _zz_324 = 3'b100; - assign _zz_325 = execute_INSTRUCTION[19 : 15]; - assign _zz_326 = execute_INSTRUCTION[31 : 20]; - assign _zz_327 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_328 = ($signed(_zz_329) + $signed(_zz_332)); - assign _zz_329 = ($signed(_zz_330) + $signed(_zz_331)); - assign _zz_330 = execute_SRC1; - assign _zz_331 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_332 = (execute_SRC_USE_SUB_LESS ? _zz_333 : _zz_334); - assign _zz_333 = 32'h00000001; - assign _zz_334 = 32'h0; - assign _zz_335 = execute_INSTRUCTION[31 : 20]; - assign _zz_336 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_337 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_338 = {_zz_125,execute_INSTRUCTION[31 : 20]}; - assign _zz_339 = {{_zz_127,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_340 = {{_zz_129,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_341 = execute_INSTRUCTION[31 : 20]; - assign _zz_342 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_344 = 3'b100; - assign _zz_345 = (_zz_140 & (~ _zz_346)); - assign _zz_346 = (_zz_140 - 2'b01); - assign _zz_347 = (_zz_142 & (~ _zz_348)); - assign _zz_348 = (_zz_142 - 2'b01); - assign _zz_349 = execute_INSTRUCTION[31 : 12]; - assign _zz_350 = execute_INSTRUCTION[31 : 20]; - assign _zz_351 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_352 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_353 = writeBack_MUL_LOW[31 : 0]; - assign _zz_354 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_355 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_356 = {5'd0, _zz_355}; - assign _zz_357 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_358 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_359 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_360 = {_zz_163,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_361 = _zz_362; - assign _zz_362 = _zz_363; - assign _zz_363 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_164) : _zz_164)} + _zz_365); - assign _zz_364 = memory_DivPlugin_div_needRevert; - assign _zz_365 = {32'd0, _zz_364}; - assign _zz_366 = _zz_166; - assign _zz_367 = {32'd0, _zz_366}; - assign _zz_368 = _zz_165; - assign _zz_369 = {31'd0, _zz_368}; - assign _zz_370 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_371 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_372 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_373 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_374 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_375 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_376 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_377 = (iBus_cmd_payload_address >>> 5); - assign _zz_378 = 1'b1; - assign _zz_379 = 1'b1; - assign _zz_380 = {_zz_63,_zz_62}; - assign _zz_381 = 32'h0000106f; - assign _zz_382 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_383 = 32'h00001073; - assign _zz_384 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_385 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_386 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_387) == 32'h00000003),{(_zz_388 == _zz_389),{_zz_390,{_zz_391,_zz_392}}}}}}; - assign _zz_387 = 32'h0000207f; - assign _zz_388 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_389 = 32'h00000003; - assign _zz_390 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_391 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_392 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_393) == 32'h00005013),{(_zz_394 == _zz_395),{_zz_396,{_zz_397,_zz_398}}}}}}; - assign _zz_393 = 32'hbc00707f; - assign _zz_394 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_395 = 32'h00001013; - assign _zz_396 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_397 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_398 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_399 = decode_INSTRUCTION[31]; - assign _zz_400 = decode_INSTRUCTION[31]; - assign _zz_401 = decode_INSTRUCTION[7]; - assign _zz_402 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_403 = 32'h02004020; - assign _zz_404 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_405 = (_zz_95 != 1'b0); - assign _zz_406 = (((decode_INSTRUCTION & _zz_408) == 32'h00000050) != 1'b0); - assign _zz_407 = {((_zz_409 == _zz_410) != 1'b0),{({_zz_411,_zz_412} != 2'b00),{(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}}}; - assign _zz_408 = 32'h00203050; - assign _zz_409 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_410 = 32'h00000050; - assign _zz_411 = ((decode_INSTRUCTION & _zz_418) == 32'h00001050); - assign _zz_412 = ((decode_INSTRUCTION & _zz_419) == 32'h00002050); - assign _zz_413 = {_zz_94,(_zz_420 == _zz_421)}; - assign _zz_414 = 2'b00; - assign _zz_415 = ((_zz_422 == _zz_423) != 1'b0); - assign _zz_416 = ({_zz_424,_zz_425} != 2'b00); - assign _zz_417 = {(_zz_426 != _zz_427),{_zz_428,{_zz_429,_zz_430}}}; - assign _zz_418 = 32'h00001050; - assign _zz_419 = 32'h00002050; - assign _zz_420 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_421 = 32'h00000004; - assign _zz_422 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_423 = 32'h00000040; - assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00005010); - assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00005020); - assign _zz_426 = {(_zz_433 == _zz_434),{_zz_435,_zz_436}}; - assign _zz_427 = 3'b000; - assign _zz_428 = ((_zz_437 == _zz_438) != 1'b0); - assign _zz_429 = (_zz_439 != 1'b0); - assign _zz_430 = {(_zz_440 != _zz_441),{_zz_442,{_zz_443,_zz_444}}}; - assign _zz_431 = 32'h00007034; - assign _zz_432 = 32'h02007064; - assign _zz_433 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_434 = 32'h40001010; - assign _zz_435 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_436 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_437 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_438 = 32'h00000024; - assign _zz_439 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_440 = ((decode_INSTRUCTION & _zz_445) == 32'h00002000); - assign _zz_441 = 1'b0; - assign _zz_442 = ({_zz_446,_zz_447} != 2'b00); - assign _zz_443 = (_zz_448 != 1'b0); - assign _zz_444 = {(_zz_449 != _zz_450),{_zz_451,{_zz_452,_zz_453}}}; - assign _zz_445 = 32'h00003000; - assign _zz_446 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_447 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_448 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_449 = {_zz_95,{_zz_454,_zz_455}}; - assign _zz_450 = 3'b000; - assign _zz_451 = ({_zz_456,{_zz_457,_zz_458}} != 5'h0); - assign _zz_452 = (_zz_459 != 1'b0); - assign _zz_453 = {(_zz_460 != _zz_461),{_zz_462,{_zz_463,_zz_464}}}; - assign _zz_454 = ((decode_INSTRUCTION & _zz_465) == 32'h00000020); - assign _zz_455 = ((decode_INSTRUCTION & _zz_466) == 32'h00000020); - assign _zz_456 = ((decode_INSTRUCTION & _zz_467) == 32'h00002040); - assign _zz_457 = (_zz_468 == _zz_469); - assign _zz_458 = {_zz_470,{_zz_471,_zz_472}}; - assign _zz_459 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); - assign _zz_460 = {_zz_474,{_zz_475,_zz_476}}; - assign _zz_461 = 6'h0; - assign _zz_462 = ({_zz_477,_zz_478} != 5'h0); - assign _zz_463 = (_zz_479 != _zz_480); - assign _zz_464 = {_zz_481,{_zz_482,_zz_483}}; - assign _zz_465 = 32'h00000034; - assign _zz_466 = 32'h00000064; - assign _zz_467 = 32'h00002040; - assign _zz_468 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_469 = 32'h00001040; - assign _zz_470 = ((decode_INSTRUCTION & _zz_484) == 32'h00000040); - assign _zz_471 = (_zz_485 == _zz_486); - assign _zz_472 = (_zz_487 == _zz_488); - assign _zz_473 = 32'h00000020; - assign _zz_474 = ((decode_INSTRUCTION & _zz_489) == 32'h00000008); - assign _zz_475 = (_zz_490 == _zz_491); - assign _zz_476 = {_zz_93,{_zz_492,_zz_493}}; - assign _zz_477 = _zz_93; - assign _zz_478 = {_zz_494,{_zz_495,_zz_496}}; - assign _zz_479 = {_zz_94,{_zz_497,_zz_498}}; - assign _zz_480 = 6'h0; - assign _zz_481 = ({_zz_499,_zz_500} != 2'b00); - assign _zz_482 = (_zz_501 != _zz_502); - assign _zz_483 = {_zz_503,{_zz_504,_zz_505}}; - assign _zz_484 = 32'h00000050; - assign _zz_485 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_486 = 32'h00000040; - assign _zz_487 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_488 = 32'h0; - assign _zz_489 = 32'h00000008; - assign _zz_490 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_491 = 32'h00000040; - assign _zz_492 = (_zz_506 == _zz_507); - assign _zz_493 = {_zz_508,_zz_509}; - assign _zz_494 = ((decode_INSTRUCTION & _zz_510) == 32'h00002010); - assign _zz_495 = (_zz_511 == _zz_512); - assign _zz_496 = {_zz_513,_zz_514}; - assign _zz_497 = (_zz_515 == _zz_516); - assign _zz_498 = {_zz_517,{_zz_518,_zz_519}}; - assign _zz_499 = _zz_93; - assign _zz_500 = (_zz_520 == _zz_521); - assign _zz_501 = {_zz_93,_zz_522}; - assign _zz_502 = 2'b00; - assign _zz_503 = (_zz_523 != 1'b0); - assign _zz_504 = (_zz_524 != _zz_525); - assign _zz_505 = {_zz_526,{_zz_527,_zz_528}}; - assign _zz_506 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_507 = 32'h00004020; - assign _zz_508 = ((decode_INSTRUCTION & _zz_529) == 32'h00000010); - assign _zz_509 = ((decode_INSTRUCTION & _zz_530) == 32'h00000020); - assign _zz_510 = 32'h00002030; - assign _zz_511 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_512 = 32'h00000010; - assign _zz_513 = ((decode_INSTRUCTION & _zz_531) == 32'h00002020); - assign _zz_514 = ((decode_INSTRUCTION & _zz_532) == 32'h00000020); - assign _zz_515 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_516 = 32'h00001010; - assign _zz_517 = ((decode_INSTRUCTION & _zz_533) == 32'h00002010); - assign _zz_518 = (_zz_534 == _zz_535); - assign _zz_519 = {_zz_536,_zz_537}; - assign _zz_520 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_521 = 32'h00000020; - assign _zz_522 = ((decode_INSTRUCTION & _zz_538) == 32'h0); - assign _zz_523 = ((decode_INSTRUCTION & _zz_539) == 32'h00004010); - assign _zz_524 = (_zz_540 == _zz_541); - assign _zz_525 = 1'b0; - assign _zz_526 = ({_zz_542,_zz_543} != 4'b0000); - assign _zz_527 = (_zz_544 != _zz_545); - assign _zz_528 = {_zz_546,{_zz_547,_zz_548}}; - assign _zz_529 = 32'h00000030; - assign _zz_530 = 32'h02000020; - assign _zz_531 = 32'h02002060; - assign _zz_532 = 32'h02003020; - assign _zz_533 = 32'h00002010; - assign _zz_534 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_535 = 32'h00000010; - assign _zz_536 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_537 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_538 = 32'h00000020; - assign _zz_539 = 32'h00004014; - assign _zz_540 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_541 = 32'h00002010; - assign _zz_542 = ((decode_INSTRUCTION & _zz_549) == 32'h0); - assign _zz_543 = {(_zz_550 == _zz_551),{_zz_552,_zz_553}}; - assign _zz_544 = ((decode_INSTRUCTION & _zz_554) == 32'h0); - assign _zz_545 = 1'b0; - assign _zz_546 = ({_zz_555,{_zz_556,_zz_557}} != 3'b000); - assign _zz_547 = ({_zz_558,_zz_559} != 2'b00); - assign _zz_548 = {(_zz_560 != _zz_561),(_zz_562 != _zz_563)}; - assign _zz_549 = 32'h00000044; - assign _zz_550 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_551 = 32'h0; - assign _zz_552 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_553 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_554 = 32'h00000058; - assign _zz_555 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_556 = ((decode_INSTRUCTION & _zz_564) == 32'h00002010); - assign _zz_557 = ((decode_INSTRUCTION & _zz_565) == 32'h40000030); - assign _zz_558 = ((decode_INSTRUCTION & _zz_566) == 32'h00000004); - assign _zz_559 = _zz_92; - assign _zz_560 = {(_zz_567 == _zz_568),_zz_92}; - assign _zz_561 = 2'b00; - assign _zz_562 = ((decode_INSTRUCTION & _zz_569) == 32'h00001004); - assign _zz_563 = 1'b0; - assign _zz_564 = 32'h00002014; - assign _zz_565 = 32'h40000034; - assign _zz_566 = 32'h00000014; - assign _zz_567 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_568 = 32'h00000004; - assign _zz_569 = 32'h00005054; - assign _zz_570 = execute_INSTRUCTION[31]; - assign _zz_571 = execute_INSTRUCTION[31]; - assign _zz_572 = execute_INSTRUCTION[7]; - assign _zz_573 = 32'h0; + assign _zz_321 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_324 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_325 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_326 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_328 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_329 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_330 = execute_SRC_LESS; + assign _zz_331 = 3'b100; + assign _zz_332 = execute_INSTRUCTION[19 : 15]; + assign _zz_333 = execute_INSTRUCTION[31 : 20]; + assign _zz_334 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_335 = ($signed(_zz_336) + $signed(_zz_339)); + assign _zz_336 = ($signed(_zz_337) + $signed(_zz_338)); + assign _zz_337 = execute_SRC1; + assign _zz_338 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_339 = (execute_SRC_USE_SUB_LESS ? _zz_340 : _zz_341); + assign _zz_340 = 32'h00000001; + assign _zz_341 = 32'h0; + assign _zz_342 = execute_INSTRUCTION[31 : 20]; + assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_345 = {_zz_132,execute_INSTRUCTION[31 : 20]}; + assign _zz_346 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_347 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_348 = execute_INSTRUCTION[31 : 20]; + assign _zz_349 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_351 = 3'b100; + assign _zz_352 = (_zz_147 & (~ _zz_353)); + assign _zz_353 = (_zz_147 - 2'b01); + assign _zz_354 = (_zz_149 & (~ _zz_355)); + assign _zz_355 = (_zz_149 - 2'b01); + assign _zz_356 = execute_INSTRUCTION[31 : 12]; + assign _zz_357 = execute_INSTRUCTION[31 : 20]; + assign _zz_358 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_359 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_360 = writeBack_MUL_LOW[31 : 0]; + assign _zz_361 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_362 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_363 = {5'd0, _zz_362}; + assign _zz_364 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_365 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_366 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_367 = {_zz_170,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_368 = _zz_369; + assign _zz_369 = _zz_370; + assign _zz_370 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_171) : _zz_171)} + _zz_372); + assign _zz_371 = memory_DivPlugin_div_needRevert; + assign _zz_372 = {32'd0, _zz_371}; + assign _zz_373 = _zz_173; + assign _zz_374 = {32'd0, _zz_373}; + assign _zz_375 = _zz_172; + assign _zz_376 = {31'd0, _zz_375}; + assign _zz_377 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_378 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_380 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_381 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_382 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_383 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_384 = (iBus_cmd_payload_address >>> 5); + assign _zz_385 = 1'b1; + assign _zz_386 = 1'b1; + assign _zz_387 = {_zz_65,_zz_64}; + assign _zz_388 = 32'h0000106f; + assign _zz_389 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_390 = 32'h00001073; + assign _zz_391 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_392 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_393 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_394) == 32'h00000003),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; + assign _zz_394 = 32'h0000207f; + assign _zz_395 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_396 = 32'h00000003; + assign _zz_397 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_398 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_399 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_400) == 32'h00005013),{(_zz_401 == _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; + assign _zz_400 = 32'hbc00707f; + assign _zz_401 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_402 = 32'h00001013; + assign _zz_403 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_405 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_406 = decode_INSTRUCTION[31]; + assign _zz_407 = decode_INSTRUCTION[31]; + assign _zz_408 = decode_INSTRUCTION[7]; + assign _zz_409 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_410 = 32'h02004020; + assign _zz_411 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_412 = (_zz_97 != 1'b0); + assign _zz_413 = (((decode_INSTRUCTION & _zz_415) == 32'h00000050) != 1'b0); + assign _zz_414 = {((_zz_416 == _zz_417) != 1'b0),{({_zz_418,_zz_419} != 2'b00),{(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}}}; + assign _zz_415 = 32'h00203050; + assign _zz_416 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_417 = 32'h00000050; + assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00001050); + assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00002050); + assign _zz_420 = {_zz_96,(_zz_427 == _zz_428)}; + assign _zz_421 = 2'b00; + assign _zz_422 = ((_zz_429 == _zz_430) != 1'b0); + assign _zz_423 = ({_zz_431,_zz_432} != 2'b00); + assign _zz_424 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; + assign _zz_425 = 32'h00001050; + assign _zz_426 = 32'h00002050; + assign _zz_427 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_428 = 32'h00000004; + assign _zz_429 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_430 = 32'h00000040; + assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h00005010); + assign _zz_432 = ((decode_INSTRUCTION & _zz_439) == 32'h00005020); + assign _zz_433 = {(_zz_440 == _zz_441),{_zz_442,_zz_443}}; + assign _zz_434 = 3'b000; + assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); + assign _zz_436 = (_zz_446 != 1'b0); + assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; + assign _zz_438 = 32'h00007034; + assign _zz_439 = 32'h02007064; + assign _zz_440 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_441 = 32'h40001010; + assign _zz_442 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_443 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_445 = 32'h00000024; + assign _zz_446 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_447 = ((decode_INSTRUCTION & _zz_452) == 32'h00002000); + assign _zz_448 = 1'b0; + assign _zz_449 = ({_zz_453,_zz_454} != 2'b00); + assign _zz_450 = (_zz_455 != 1'b0); + assign _zz_451 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; + assign _zz_452 = 32'h00003000; + assign _zz_453 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_454 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_455 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_456 = {_zz_97,{_zz_461,_zz_462}}; + assign _zz_457 = 3'b000; + assign _zz_458 = ({_zz_463,{_zz_464,_zz_465}} != 5'h0); + assign _zz_459 = (_zz_466 != 1'b0); + assign _zz_460 = {(_zz_467 != _zz_468),{_zz_469,{_zz_470,_zz_471}}}; + assign _zz_461 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); + assign _zz_462 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); + assign _zz_463 = ((decode_INSTRUCTION & _zz_474) == 32'h00002040); + assign _zz_464 = (_zz_475 == _zz_476); + assign _zz_465 = {_zz_477,{_zz_478,_zz_479}}; + assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000020); + assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; + assign _zz_468 = 6'h0; + assign _zz_469 = ({_zz_484,_zz_485} != 5'h0); + assign _zz_470 = (_zz_486 != _zz_487); + assign _zz_471 = {_zz_488,{_zz_489,_zz_490}}; + assign _zz_472 = 32'h00000034; + assign _zz_473 = 32'h00000064; + assign _zz_474 = 32'h00002040; + assign _zz_475 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_476 = 32'h00001040; + assign _zz_477 = ((decode_INSTRUCTION & _zz_491) == 32'h00000040); + assign _zz_478 = (_zz_492 == _zz_493); + assign _zz_479 = (_zz_494 == _zz_495); + assign _zz_480 = 32'h00000020; + assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00000008); + assign _zz_482 = (_zz_497 == _zz_498); + assign _zz_483 = {_zz_95,{_zz_499,_zz_500}}; + assign _zz_484 = _zz_95; + assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; + assign _zz_486 = {_zz_96,{_zz_504,_zz_505}}; + assign _zz_487 = 6'h0; + assign _zz_488 = ({_zz_506,_zz_507} != 2'b00); + assign _zz_489 = (_zz_508 != _zz_509); + assign _zz_490 = {_zz_510,{_zz_511,_zz_512}}; + assign _zz_491 = 32'h00000050; + assign _zz_492 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_493 = 32'h00000040; + assign _zz_494 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_495 = 32'h0; + assign _zz_496 = 32'h00000008; + assign _zz_497 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_498 = 32'h00000040; + assign _zz_499 = (_zz_513 == _zz_514); + assign _zz_500 = {_zz_515,_zz_516}; + assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00002010); + assign _zz_502 = (_zz_518 == _zz_519); + assign _zz_503 = {_zz_520,_zz_521}; + assign _zz_504 = (_zz_522 == _zz_523); + assign _zz_505 = {_zz_524,{_zz_525,_zz_526}}; + assign _zz_506 = _zz_95; + assign _zz_507 = (_zz_527 == _zz_528); + assign _zz_508 = {_zz_95,_zz_529}; + assign _zz_509 = 2'b00; + assign _zz_510 = (_zz_530 != 1'b0); + assign _zz_511 = (_zz_531 != _zz_532); + assign _zz_512 = {_zz_533,{_zz_534,_zz_535}}; + assign _zz_513 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_514 = 32'h00004020; + assign _zz_515 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); + assign _zz_516 = ((decode_INSTRUCTION & _zz_537) == 32'h00000020); + assign _zz_517 = 32'h00002030; + assign _zz_518 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_519 = 32'h00000010; + assign _zz_520 = ((decode_INSTRUCTION & _zz_538) == 32'h00002020); + assign _zz_521 = ((decode_INSTRUCTION & _zz_539) == 32'h00000020); + assign _zz_522 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_523 = 32'h00001010; + assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00002010); + assign _zz_525 = (_zz_541 == _zz_542); + assign _zz_526 = {_zz_543,_zz_544}; + assign _zz_527 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_528 = 32'h00000020; + assign _zz_529 = ((decode_INSTRUCTION & _zz_545) == 32'h0); + assign _zz_530 = ((decode_INSTRUCTION & _zz_546) == 32'h00004010); + assign _zz_531 = (_zz_547 == _zz_548); + assign _zz_532 = 1'b0; + assign _zz_533 = ({_zz_549,_zz_550} != 4'b0000); + assign _zz_534 = (_zz_551 != _zz_552); + assign _zz_535 = {_zz_553,{_zz_554,_zz_555}}; + assign _zz_536 = 32'h00000030; + assign _zz_537 = 32'h02000020; + assign _zz_538 = 32'h02002060; + assign _zz_539 = 32'h02003020; + assign _zz_540 = 32'h00002010; + assign _zz_541 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_542 = 32'h00000010; + assign _zz_543 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_544 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_545 = 32'h00000020; + assign _zz_546 = 32'h00004014; + assign _zz_547 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_548 = 32'h00002010; + assign _zz_549 = ((decode_INSTRUCTION & _zz_556) == 32'h0); + assign _zz_550 = {(_zz_557 == _zz_558),{_zz_559,_zz_560}}; + assign _zz_551 = ((decode_INSTRUCTION & _zz_561) == 32'h0); + assign _zz_552 = 1'b0; + assign _zz_553 = ({_zz_562,{_zz_563,_zz_564}} != 3'b000); + assign _zz_554 = ({_zz_565,_zz_566} != 2'b00); + assign _zz_555 = {(_zz_567 != _zz_568),(_zz_569 != _zz_570)}; + assign _zz_556 = 32'h00000044; + assign _zz_557 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_558 = 32'h0; + assign _zz_559 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_560 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_561 = 32'h00000058; + assign _zz_562 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_563 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); + assign _zz_564 = ((decode_INSTRUCTION & _zz_572) == 32'h40000030); + assign _zz_565 = ((decode_INSTRUCTION & _zz_573) == 32'h00000004); + assign _zz_566 = _zz_94; + assign _zz_567 = {(_zz_574 == _zz_575),_zz_94}; + assign _zz_568 = 2'b00; + assign _zz_569 = ((decode_INSTRUCTION & _zz_576) == 32'h00001004); + assign _zz_570 = 1'b0; + assign _zz_571 = 32'h00002014; + assign _zz_572 = 32'h40000034; + assign _zz_573 = 32'h00000014; + assign _zz_574 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_575 = 32'h00000004; + assign _zz_576 = 32'h00005054; + assign _zz_577 = execute_INSTRUCTION[31]; + assign _zz_578 = execute_INSTRUCTION[31]; + assign _zz_579 = execute_INSTRUCTION[7]; + assign _zz_580 = 32'h0; always @ (posedge clk) begin - if(_zz_378) begin - _zz_238 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_385) begin + _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_379) begin - _zz_239 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_386) begin + _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_46) begin + if(_zz_48) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_210 ), //i - .io_cpu_prefetch_isValid (_zz_211 ), //i + .io_flush (_zz_217 ), //i + .io_cpu_prefetch_isValid (_zz_218 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_212 ), //i - .io_cpu_fetch_isStuck (_zz_213 ), //i - .io_cpu_fetch_isRemoved (_zz_214 ), //i + .io_cpu_fetch_isValid (_zz_219 ), //i + .io_cpu_fetch_isStuck (_zz_220 ), //i + .io_cpu_fetch_isRemoved (_zz_221 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1754,8 +1753,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_215 ), //i - .io_cpu_decode_isStuck (_zz_216 ), //i + .io_cpu_decode_isValid (_zz_222 ), //i + .io_cpu_decode_isStuck (_zz_223 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1763,8 +1762,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_217 ), //i - .io_cpu_fill_valid (_zz_218 ), //i + .io_cpu_decode_isUser (_zz_224 ), //i + .io_cpu_fill_valid (_zz_225 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1777,20 +1776,20 @@ module VexRiscv_inner ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_219 ), //i - .io_cpu_execute_address (_zz_220[31:0] ), //i + .io_cpu_execute_isValid (_zz_226 ), //i + .io_cpu_execute_address (_zz_227[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_86[31:0] ), //i + .io_cpu_execute_args_data (_zz_88[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_221 ), //i + .io_cpu_memory_isValid (_zz_228 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_222[31:0] ), //i + .io_cpu_memory_address (_zz_229[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_223 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_230 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1798,31 +1797,31 @@ module VexRiscv_inner ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_224 ), //i + .io_cpu_writeBack_isValid (_zz_231 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_225 ), //i + .io_cpu_writeBack_isUser (_zz_232 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_226[31:0] ), //i + .io_cpu_writeBack_address (_zz_233[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_227 ), //i - .io_cpu_writeBack_fence_SR (_zz_228 ), //i - .io_cpu_writeBack_fence_SO (_zz_229 ), //i - .io_cpu_writeBack_fence_SI (_zz_230 ), //i - .io_cpu_writeBack_fence_PW (_zz_231 ), //i - .io_cpu_writeBack_fence_PR (_zz_232 ), //i - .io_cpu_writeBack_fence_PO (_zz_233 ), //i - .io_cpu_writeBack_fence_PI (_zz_234 ), //i - .io_cpu_writeBack_fence_FM (_zz_235[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_234 ), //i + .io_cpu_writeBack_fence_SR (_zz_235 ), //i + .io_cpu_writeBack_fence_SO (_zz_236 ), //i + .io_cpu_writeBack_fence_SI (_zz_237 ), //i + .io_cpu_writeBack_fence_PW (_zz_238 ), //i + .io_cpu_writeBack_fence_PR (_zz_239 ), //i + .io_cpu_writeBack_fence_PO (_zz_240 ), //i + .io_cpu_writeBack_fence_PI (_zz_241 ), //i + .io_cpu_writeBack_fence_FM (_zz_242[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_236 ), //i + .io_cpu_flush_valid (_zz_243 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_237 ), //i + .io_mem_cmd_ready (_zz_244 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1838,18 +1837,18 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_380) + case(_zz_387) 2'b00 : begin - _zz_240 = DBusCachedPlugin_redoBranch_payload; + _zz_247 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_240 = CsrPlugin_jumpInterface_payload; + _zz_247 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_240 = BranchPlugin_jumpInterface_payload; + _zz_247 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_240 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_247 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2171,10 +2170,10 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_30) - `Input2Kind_defaultEncoding_RS : _zz_30_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_30_string = "IMM_I"; - default : _zz_30_string = "?????"; + case(_zz_32) + `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; + default : _zz_32_string = "?????"; endcase end always @(*) begin @@ -2187,12 +2186,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_31) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_31_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_31_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_31_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_31_string = "ECALL"; - default : _zz_31_string = "?????"; + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; endcase end always @(*) begin @@ -2205,12 +2204,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_32) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_32_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_32_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_32_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32_string = "ECALL"; - default : _zz_32_string = "?????"; + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; endcase end always @(*) begin @@ -2223,12 +2222,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; endcase end always @(*) begin @@ -2241,12 +2240,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_34) - `BranchCtrlEnum_defaultEncoding_INC : _zz_34_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_34_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_34_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_34_string = "JALR"; - default : _zz_34_string = "????"; + case(_zz_36) + `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; + default : _zz_36_string = "????"; endcase end always @(*) begin @@ -2259,12 +2258,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_37) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_37_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_37_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_37_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_37_string = "SRA_1 "; - default : _zz_37_string = "?????????"; + case(_zz_39) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; + default : _zz_39_string = "?????????"; endcase end always @(*) begin @@ -2277,12 +2276,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_38) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38_string = "SRA_1 "; - default : _zz_38_string = "?????????"; + case(_zz_40) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; + default : _zz_40_string = "?????????"; endcase end always @(*) begin @@ -2295,12 +2294,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_40) - `Src2CtrlEnum_defaultEncoding_RS : _zz_40_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_40_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_40_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_40_string = "PC "; - default : _zz_40_string = "???"; + case(_zz_42) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; + default : _zz_42_string = "???"; endcase end always @(*) begin @@ -2313,12 +2312,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_41) - `Src1CtrlEnum_defaultEncoding_RS : _zz_41_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_41_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_41_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_41_string = "URS1 "; - default : _zz_41_string = "????????????"; + case(_zz_43) + `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; + default : _zz_43_string = "????????????"; endcase end always @(*) begin @@ -2330,11 +2329,11 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_42) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_42_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_42_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_42_string = "BITWISE "; - default : _zz_42_string = "????????"; + case(_zz_44) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; + default : _zz_44_string = "????????"; endcase end always @(*) begin @@ -2346,165 +2345,165 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_43) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; - default : _zz_43_string = "?????"; - endcase - end - always @(*) begin - case(_zz_47) - `Input2Kind_defaultEncoding_RS : _zz_47_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_47_string = "IMM_I"; - default : _zz_47_string = "?????"; - endcase - end - always @(*) begin - case(_zz_48) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_48_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_48_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_48_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_48_string = "ECALL"; - default : _zz_48_string = "?????"; + case(_zz_45) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; + default : _zz_45_string = "?????"; endcase end always @(*) begin case(_zz_49) - `BranchCtrlEnum_defaultEncoding_INC : _zz_49_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_49_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_49_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_49_string = "JALR"; - default : _zz_49_string = "????"; + `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; + default : _zz_49_string = "?????"; endcase end always @(*) begin case(_zz_50) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_50_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_50_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_50_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_50_string = "SRA_1 "; - default : _zz_50_string = "?????????"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; + default : _zz_50_string = "?????"; endcase end always @(*) begin case(_zz_51) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_51_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_51_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_51_string = "AND_1"; - default : _zz_51_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; endcase end always @(*) begin case(_zz_52) - `Src2CtrlEnum_defaultEncoding_RS : _zz_52_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_52_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_52_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_52_string = "PC "; - default : _zz_52_string = "???"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; + default : _zz_52_string = "?????????"; endcase end always @(*) begin case(_zz_53) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_53_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_53_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_53_string = "BITWISE "; - default : _zz_53_string = "????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; + default : _zz_53_string = "?????"; endcase end always @(*) begin case(_zz_54) - `Src1CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_54_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54_string = "URS1 "; - default : _zz_54_string = "????????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; + default : _zz_54_string = "???"; endcase end always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; + case(_zz_55) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; + default : _zz_55_string = "????????"; endcase end always @(*) begin case(_zz_56) - `BranchCtrlEnum_defaultEncoding_INC : _zz_56_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_56_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_56_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_56_string = "JALR"; - default : _zz_56_string = "????"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; + default : _zz_56_string = "????????????"; endcase end always @(*) begin - case(_zz_97) - `Src1CtrlEnum_defaultEncoding_RS : _zz_97_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_97_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_97_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_97_string = "URS1 "; - default : _zz_97_string = "????????????"; + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_98) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_98_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_98_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_98_string = "BITWISE "; - default : _zz_98_string = "????????"; + case(_zz_58) + `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; + default : _zz_58_string = "????"; endcase end always @(*) begin case(_zz_99) - `Src2CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_99_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_99_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_99_string = "PC "; - default : _zz_99_string = "???"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_99_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99_string = "URS1 "; + default : _zz_99_string = "????????????"; endcase end always @(*) begin case(_zz_100) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_100_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_100_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_100_string = "AND_1"; - default : _zz_100_string = "?????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_100_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_100_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_100_string = "BITWISE "; + default : _zz_100_string = "????????"; endcase end always @(*) begin case(_zz_101) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_101_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_101_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_101_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_101_string = "SRA_1 "; - default : _zz_101_string = "?????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_101_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_101_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_101_string = "PC "; + default : _zz_101_string = "???"; endcase end always @(*) begin case(_zz_102) - `BranchCtrlEnum_defaultEncoding_INC : _zz_102_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_102_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_102_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_102_string = "JALR"; - default : _zz_102_string = "????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_102_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_102_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_102_string = "AND_1"; + default : _zz_102_string = "?????"; endcase end always @(*) begin case(_zz_103) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_103_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_103_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_103_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_103_string = "ECALL"; - default : _zz_103_string = "?????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_103_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_103_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_103_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_103_string = "SRA_1 "; + default : _zz_103_string = "?????????"; endcase end always @(*) begin case(_zz_104) - `Input2Kind_defaultEncoding_RS : _zz_104_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_104_string = "IMM_I"; - default : _zz_104_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_104_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_104_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_104_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_104_string = "JALR"; + default : _zz_104_string = "????"; + endcase + end + always @(*) begin + case(_zz_105) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_105_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_105_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_105_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_105_string = "ECALL"; + default : _zz_105_string = "?????"; + endcase + end + always @(*) begin + case(_zz_106) + `Input2Kind_defaultEncoding_RS : _zz_106_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_106_string = "IMM_I"; + default : _zz_106_string = "?????"; endcase end always @(*) begin @@ -2604,50 +2603,51 @@ module VexRiscv_inner ( end `endif - assign memory_MUL_LOW = ($signed(_zz_280) + $signed(_zz_288)); + assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_290; - assign execute_REGFILE_WRITE_DATA = _zz_106; + assign execute_SHIFT_RIGHT = _zz_297; + assign execute_REGFILE_WRITE_DATA = _zz_108; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_220[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_227[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_292[0]; - assign decode_IS_RS1_SIGNED = _zz_293[0]; - assign decode_IS_DIV = _zz_294[0]; + assign decode_IS_RS2_SIGNED = _zz_299[0]; + assign decode_IS_RS1_SIGNED = _zz_300[0]; + assign decode_IS_DIV = _zz_301[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_295[0]; + assign decode_IS_MUL = _zz_302[0]; assign decode_CfuPlugin_CFU_ENCODING = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_296[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_297[0]; + assign decode_IS_CSR = _zz_304[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_298[0]; - assign decode_MEMORY_MANAGMENT = _zz_299[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; + assign decode_MEMORY_MANAGMENT = _zz_306[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_300[0]; + assign decode_MEMORY_WR = _zz_307[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_301[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_302[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2670,28 +2670,42 @@ module VexRiscv_inner ( assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; + always @ (*) begin + _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck)begin + _zz_30 = 1'b0; + end + end + + always @ (*) begin + _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck)begin + _zz_31 = 1'b0; + end + end + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_ENCODING = _zz_30; + assign execute_CfuPlugin_CFU_ENCODING = _zz_32; assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_31; - assign execute_ENV_CTRL = _zz_32; - assign writeBack_ENV_CTRL = _zz_33; + assign memory_ENV_CTRL = _zz_33; + assign execute_ENV_CTRL = _zz_34; + assign writeBack_ENV_CTRL = _zz_35; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_123; - assign execute_BRANCH_CTRL = _zz_34; - assign decode_RS2_USE = _zz_303[0]; - assign decode_RS1_USE = _zz_304[0]; + assign execute_BRANCH_COND_RESULT = _zz_130; + assign execute_BRANCH_CTRL = _zz_36; + assign decode_RS2_USE = _zz_310[0]; + assign decode_RS1_USE = _zz_311[0]; always @ (*) begin - _zz_35 = execute_REGFILE_WRITE_DATA; - if(_zz_241)begin - _zz_35 = execute_CsrPlugin_readData; + _zz_37 = execute_REGFILE_WRITE_DATA; + if(_zz_248)begin + _zz_37 = execute_CsrPlugin_readData; end end @@ -2703,29 +2717,29 @@ module VexRiscv_inner ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_119)begin + if((_zz_120 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_121; end end - if(_zz_242)begin - if(_zz_243)begin - if(_zz_116)begin - decode_RS2 = _zz_55; + if(_zz_249)begin + if(_zz_250)begin + if(_zz_123)begin + decode_RS2 = _zz_57; end end end - if(_zz_244)begin + if(_zz_251)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_118)begin - decode_RS2 = _zz_36; + if(_zz_125)begin + decode_RS2 = _zz_38; end end end - if(_zz_245)begin + if(_zz_252)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_120)begin - decode_RS2 = _zz_35; + if(_zz_127)begin + decode_RS2 = _zz_37; end end end @@ -2733,29 +2747,29 @@ module VexRiscv_inner ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_119)begin + if((_zz_120 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_121; end end - if(_zz_242)begin - if(_zz_243)begin - if(_zz_115)begin - decode_RS1 = _zz_55; + if(_zz_249)begin + if(_zz_250)begin + if(_zz_122)begin + decode_RS1 = _zz_57; end end end - if(_zz_244)begin + if(_zz_251)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_117)begin - decode_RS1 = _zz_36; + if(_zz_124)begin + decode_RS1 = _zz_38; end end end - if(_zz_245)begin + if(_zz_252)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_119)begin - decode_RS1 = _zz_35; + if(_zz_126)begin + decode_RS1 = _zz_37; end end end @@ -2763,73 +2777,73 @@ module VexRiscv_inner ( assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_36 = memory_REGFILE_WRITE_DATA; + _zz_38 = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_36 = _zz_114; + _zz_38 = _zz_116; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_36 = memory_SHIFT_RIGHT; + _zz_38 = memory_SHIFT_RIGHT; end default : begin end endcase end if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_36 = memory_CfuPlugin_rsp_payload_outputs_0; + _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_246)begin - _zz_36 = memory_DivPlugin_div_result; + if(_zz_253)begin + _zz_38 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_37; - assign execute_SHIFT_CTRL = _zz_38; + assign memory_SHIFT_CTRL = _zz_39; + assign execute_SHIFT_CTRL = _zz_40; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_39 = execute_PC; - assign execute_SRC2_CTRL = _zz_40; - assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_305[0]; - assign decode_SRC_ADD_ZERO = _zz_306[0]; + assign _zz_41 = execute_PC; + assign execute_SRC2_CTRL = _zz_42; + assign execute_SRC1_CTRL = _zz_43; + assign decode_SRC_USE_SUB_LESS = _zz_312[0]; + assign decode_SRC_ADD_ZERO = _zz_313[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_42; - assign execute_SRC2 = _zz_112; - assign execute_SRC1 = _zz_107; - assign execute_ALU_BITWISE_CTRL = _zz_43; - assign _zz_44 = writeBack_INSTRUCTION; - assign _zz_45 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_46 = 1'b0; + assign execute_ALU_CTRL = _zz_44; + assign execute_SRC2 = _zz_114; + assign execute_SRC1 = _zz_109; + assign execute_ALU_BITWISE_CTRL = _zz_45; + assign _zz_46 = writeBack_INSTRUCTION; + assign _zz_47 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_48 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_46 = 1'b1; + _zz_48 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_307[0]; + decode_REGFILE_WRITE_VALID = _zz_314[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_381) == 32'h00000003),{(_zz_382 == _zz_383),{_zz_384,{_zz_385,_zz_386}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}} != 22'h0); always @ (*) begin - _zz_55 = writeBack_REGFILE_WRITE_DATA; + _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_55 = writeBack_DBusCachedPlugin_rspFormated; + _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_279) + case(_zz_286) 2'b00 : begin - _zz_55 = _zz_353; + _zz_57 = _zz_360; end default : begin - _zz_55 = _zz_354; + _zz_57 = _zz_361; end endcase end @@ -2848,49 +2862,49 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_308[0]; - assign decode_FLUSH_ALL = _zz_309[0]; + assign decode_MEMORY_ENABLE = _zz_315[0]; + assign decode_FLUSH_ALL = _zz_316[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_247)begin + if(_zz_254)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_248)begin + if(_zz_255)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_249)begin + if(_zz_256)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_250)begin + if(_zz_257)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_56; + assign decode_BRANCH_CTRL = _zz_58; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_57 = memory_FORMAL_PC_NEXT; + _zz_59 = memory_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin - _zz_57 = BranchPlugin_jumpInterface_payload; + _zz_59 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_58 = decode_FORMAL_PC_NEXT; + _zz_60 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_58 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; end end @@ -2906,7 +2920,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_117 || _zz_118)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2919,7 +2933,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_251)begin + if(_zz_258)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2933,22 +2947,22 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_251)begin + if(_zz_258)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_236 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_243 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_252)begin + if(_zz_259)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_241)begin + if(_zz_248)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2990,7 +3004,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_246)begin + if(_zz_253)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3000,7 +3014,7 @@ module VexRiscv_inner ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_253)begin + if(_zz_260)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3014,7 +3028,7 @@ module VexRiscv_inner ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_253)begin + if(_zz_260)begin memory_arbitration_flushNext = 1'b1; end end @@ -3052,10 +3066,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_254)begin + if(_zz_261)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_255)begin + if(_zz_262)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3069,10 +3083,10 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_254)begin + if(_zz_261)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_255)begin + if(_zz_262)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3086,7 +3100,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_252)begin + if(_zz_259)begin CsrPlugin_inWfi = 1'b1; end end @@ -3094,21 +3108,21 @@ module VexRiscv_inner ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_254)begin + if(_zz_261)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_255)begin + if(_zz_262)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_254)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_261)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_255)begin - case(_zz_256) + if(_zz_262)begin + case(_zz_263) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3123,12 +3137,12 @@ module VexRiscv_inner ( assign CsrPlugin_allowException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_59 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_60 = (_zz_59 & (~ _zz_310)); - assign _zz_61 = _zz_60[3]; - assign _zz_62 = (_zz_60[1] || _zz_61); - assign _zz_63 = (_zz_60[2] || _zz_61); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_240; + assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_62 = (_zz_61 & (~ _zz_317)); + assign _zz_63 = _zz_62[3]; + assign _zz_64 = (_zz_62[1] || _zz_63); + assign _zz_65 = (_zz_62[2] || _zz_63); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3148,7 +3162,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_312); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_319); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3188,9 +3202,9 @@ module VexRiscv_inner ( end end - assign _zz_64 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_64); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_64); + assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_66); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; @@ -3199,9 +3213,9 @@ module VexRiscv_inner ( end end - assign _zz_65 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_65); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_65); + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_67); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; @@ -3210,22 +3224,22 @@ module VexRiscv_inner ( end end - assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_66); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_66); + assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_68); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_67; - assign _zz_67 = ((1'b0 && (! _zz_68)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_68 = _zz_69; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_68; - assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_69; + assign _zz_69 = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign _zz_70 = _zz_71; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_70; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_72)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_72 = _zz_73; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_74; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -3239,38 +3253,16 @@ module VexRiscv_inner ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_73 = _zz_313[11]; - always @ (*) begin - _zz_74[18] = _zz_73; - _zz_74[17] = _zz_73; - _zz_74[16] = _zz_73; - _zz_74[15] = _zz_73; - _zz_74[14] = _zz_73; - _zz_74[13] = _zz_73; - _zz_74[12] = _zz_73; - _zz_74[11] = _zz_73; - _zz_74[10] = _zz_73; - _zz_74[9] = _zz_73; - _zz_74[8] = _zz_73; - _zz_74[7] = _zz_73; - _zz_74[6] = _zz_73; - _zz_74[5] = _zz_73; - _zz_74[4] = _zz_73; - _zz_74[3] = _zz_73; - _zz_74[2] = _zz_73; - _zz_74[1] = _zz_73; - _zz_74[0] = _zz_73; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_314[31])); - if(_zz_79)begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; - end - end - - assign _zz_75 = _zz_315[19]; - always @ (*) begin + assign _zz_75 = _zz_320[11]; + always @ (*) begin + _zz_76[18] = _zz_75; + _zz_76[17] = _zz_75; + _zz_76[16] = _zz_75; + _zz_76[15] = _zz_75; + _zz_76[14] = _zz_75; + _zz_76[13] = _zz_75; + _zz_76[12] = _zz_75; + _zz_76[11] = _zz_75; _zz_76[10] = _zz_75; _zz_76[9] = _zz_75; _zz_76[8] = _zz_75; @@ -3284,16 +3276,15 @@ module VexRiscv_inner ( _zz_76[0] = _zz_75; end - assign _zz_77 = _zz_316[11]; always @ (*) begin - _zz_78[18] = _zz_77; - _zz_78[17] = _zz_77; - _zz_78[16] = _zz_77; - _zz_78[15] = _zz_77; - _zz_78[14] = _zz_77; - _zz_78[13] = _zz_77; - _zz_78[12] = _zz_77; - _zz_78[11] = _zz_77; + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_321[31])); + if(_zz_81)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_77 = _zz_322[19]; + always @ (*) begin _zz_78[10] = _zz_77; _zz_78[9] = _zz_77; _zz_78[8] = _zz_77; @@ -3307,43 +3298,43 @@ module VexRiscv_inner ( _zz_78[0] = _zz_77; end + assign _zz_79 = _zz_323[11]; + always @ (*) begin + _zz_80[18] = _zz_79; + _zz_80[17] = _zz_79; + _zz_80[16] = _zz_79; + _zz_80[15] = _zz_79; + _zz_80[14] = _zz_79; + _zz_80[13] = _zz_79; + _zz_80[12] = _zz_79; + _zz_80[11] = _zz_79; + _zz_80[10] = _zz_79; + _zz_80[9] = _zz_79; + _zz_80[8] = _zz_79; + _zz_80[7] = _zz_79; + _zz_80[6] = _zz_79; + _zz_80[5] = _zz_79; + _zz_80[4] = _zz_79; + _zz_80[3] = _zz_79; + _zz_80[2] = _zz_79; + _zz_80[1] = _zz_79; + _zz_80[0] = _zz_79; + end + always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_79 = _zz_317[1]; + _zz_81 = _zz_324[1]; end default : begin - _zz_79 = _zz_318[1]; + _zz_81 = _zz_325[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_80 = _zz_319[19]; - always @ (*) begin - _zz_81[10] = _zz_80; - _zz_81[9] = _zz_80; - _zz_81[8] = _zz_80; - _zz_81[7] = _zz_80; - _zz_81[6] = _zz_80; - _zz_81[5] = _zz_80; - _zz_81[4] = _zz_80; - _zz_81[3] = _zz_80; - _zz_81[2] = _zz_80; - _zz_81[1] = _zz_80; - _zz_81[0] = _zz_80; - end - - assign _zz_82 = _zz_320[11]; - always @ (*) begin - _zz_83[18] = _zz_82; - _zz_83[17] = _zz_82; - _zz_83[16] = _zz_82; - _zz_83[15] = _zz_82; - _zz_83[14] = _zz_82; - _zz_83[13] = _zz_82; - _zz_83[12] = _zz_82; - _zz_83[11] = _zz_82; + assign _zz_82 = _zz_326[19]; + always @ (*) begin _zz_83[10] = _zz_82; _zz_83[9] = _zz_82; _zz_83[8] = _zz_82; @@ -3357,7 +3348,30 @@ module VexRiscv_inner ( _zz_83[0] = _zz_82; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_81,{{{_zz_399,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_83,{{{_zz_400,_zz_401},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_84 = _zz_327[11]; + always @ (*) begin + _zz_85[18] = _zz_84; + _zz_85[17] = _zz_84; + _zz_85[16] = _zz_84; + _zz_85[15] = _zz_84; + _zz_85[14] = _zz_84; + _zz_85[13] = _zz_84; + _zz_85[12] = _zz_84; + _zz_85[11] = _zz_84; + _zz_85[10] = _zz_84; + _zz_85[9] = _zz_84; + _zz_85[8] = _zz_84; + _zz_85[7] = _zz_84; + _zz_85[6] = _zz_84; + _zz_85[5] = _zz_84; + _zz_85[4] = _zz_84; + _zz_85[3] = _zz_84; + _zz_85[2] = _zz_84; + _zz_85[1] = _zz_84; + _zz_85[0] = _zz_84; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_406,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_407,_zz_408},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3366,52 +3380,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_211 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_212 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_213 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_212; + assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_219; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_215 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_216 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_217 = (CsrPlugin_privilege == 2'b00); + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_224 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_250)begin + if(_zz_257)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_248)begin + if(_zz_255)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_218 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_248)begin - _zz_218 = 1'b1; + _zz_225 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_255)begin + _zz_225 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_249)begin + if(_zz_256)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_247)begin + if(_zz_254)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_249)begin + if(_zz_256)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_247)begin + if(_zz_254)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3421,9 +3435,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_210 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_217 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_237 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_244 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3450,43 +3464,43 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_219 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_220 = execute_SRC_ADD; + assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_227 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_86 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_88 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_86 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_88 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_86 = execute_RS2[31 : 0]; + _zz_88 = execute_RS2[31 : 0]; end endcase end - assign _zz_236 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_221 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_222 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_221; + assign _zz_243 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_228 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_229 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_228; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_222; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_229; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_223 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_230 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_223 = 1'b1; + _zz_230 = 1'b1; end end - assign _zz_224 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_225 = (CsrPlugin_privilege == 2'b00); - assign _zz_226 = writeBack_REGFILE_WRITE_DATA; + assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_232 = (CsrPlugin_privilege == 2'b00); + assign _zz_233 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_257)begin + if(_zz_264)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3496,7 +3510,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_257)begin + if(_zz_264)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3515,15 +3529,15 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_257)begin + if(_zz_264)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_321}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_322}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; end end end @@ -3545,36 +3559,7 @@ module VexRiscv_inner ( endcase end - assign _zz_87 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_88[31] = _zz_87; - _zz_88[30] = _zz_87; - _zz_88[29] = _zz_87; - _zz_88[28] = _zz_87; - _zz_88[27] = _zz_87; - _zz_88[26] = _zz_87; - _zz_88[25] = _zz_87; - _zz_88[24] = _zz_87; - _zz_88[23] = _zz_87; - _zz_88[22] = _zz_87; - _zz_88[21] = _zz_87; - _zz_88[20] = _zz_87; - _zz_88[19] = _zz_87; - _zz_88[18] = _zz_87; - _zz_88[17] = _zz_87; - _zz_88[16] = _zz_87; - _zz_88[15] = _zz_87; - _zz_88[14] = _zz_87; - _zz_88[13] = _zz_87; - _zz_88[12] = _zz_87; - _zz_88[11] = _zz_87; - _zz_88[10] = _zz_87; - _zz_88[9] = _zz_87; - _zz_88[8] = _zz_87; - _zz_88[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_89 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + assign _zz_89 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); always @ (*) begin _zz_90[31] = _zz_89; _zz_90[30] = _zz_89; @@ -3592,16 +3577,45 @@ module VexRiscv_inner ( _zz_90[18] = _zz_89; _zz_90[17] = _zz_89; _zz_90[16] = _zz_89; - _zz_90[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_277) + _zz_90[15] = _zz_89; + _zz_90[14] = _zz_89; + _zz_90[13] = _zz_89; + _zz_90[12] = _zz_89; + _zz_90[11] = _zz_89; + _zz_90[10] = _zz_89; + _zz_90[9] = _zz_89; + _zz_90[8] = _zz_89; + _zz_90[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_91 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_92[31] = _zz_91; + _zz_92[30] = _zz_91; + _zz_92[29] = _zz_91; + _zz_92[28] = _zz_91; + _zz_92[27] = _zz_91; + _zz_92[26] = _zz_91; + _zz_92[25] = _zz_91; + _zz_92[24] = _zz_91; + _zz_92[23] = _zz_91; + _zz_92[22] = _zz_91; + _zz_92[21] = _zz_91; + _zz_92[20] = _zz_91; + _zz_92[19] = _zz_91; + _zz_92[18] = _zz_91; + _zz_92[17] = _zz_91; + _zz_92[16] = _zz_91; + _zz_92[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_284) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_88; + writeBack_DBusCachedPlugin_rspFormated = _zz_90; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_90; + writeBack_DBusCachedPlugin_rspFormated = _zz_92; end default : begin writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; @@ -3627,52 +3641,52 @@ module VexRiscv_inner ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_92 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_93 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_94 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_95 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_91 = {(_zz_96 != 1'b0),{(_zz_96 != 1'b0),{((_zz_402 == _zz_403) != 1'b0),{(_zz_404 != 1'b0),{1'b0,{_zz_405,{_zz_406,_zz_407}}}}}}}; - assign _zz_97 = _zz_91[2 : 1]; - assign _zz_54 = _zz_97; - assign _zz_98 = _zz_91[7 : 6]; - assign _zz_53 = _zz_98; - assign _zz_99 = _zz_91[9 : 8]; - assign _zz_52 = _zz_99; - assign _zz_100 = _zz_91[19 : 18]; - assign _zz_51 = _zz_100; - assign _zz_101 = _zz_91[22 : 21]; - assign _zz_50 = _zz_101; - assign _zz_102 = _zz_91[24 : 23]; - assign _zz_49 = _zz_102; - assign _zz_103 = _zz_91[27 : 26]; - assign _zz_48 = _zz_103; - assign _zz_104 = _zz_91[29 : 29]; - assign _zz_47 = _zz_104; + assign _zz_94 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_95 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_409 == _zz_410) != 1'b0),{(_zz_411 != 1'b0),{1'b0,{_zz_412,{_zz_413,_zz_414}}}}}}}; + assign _zz_99 = _zz_93[2 : 1]; + assign _zz_56 = _zz_99; + assign _zz_100 = _zz_93[7 : 6]; + assign _zz_55 = _zz_100; + assign _zz_101 = _zz_93[9 : 8]; + assign _zz_54 = _zz_101; + assign _zz_102 = _zz_93[19 : 18]; + assign _zz_53 = _zz_102; + assign _zz_103 = _zz_93[22 : 21]; + assign _zz_52 = _zz_103; + assign _zz_104 = _zz_93[24 : 23]; + assign _zz_51 = _zz_104; + assign _zz_105 = _zz_93[27 : 26]; + assign _zz_50 = _zz_105; + assign _zz_106 = _zz_93[29 : 29]; + assign _zz_49 = _zz_106; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_238; - assign decode_RegFilePlugin_rs2Data = _zz_239; + assign decode_RegFilePlugin_rs1Data = _zz_245; + assign decode_RegFilePlugin_rs2Data = _zz_246; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); - if(_zz_105)begin + lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); + if(_zz_107)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; - if(_zz_105)begin + lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; + if(_zz_107)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_55; - if(_zz_105)begin + lastStageRegFileWrite_payload_data = _zz_57; + if(_zz_107)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -3694,13 +3708,13 @@ module VexRiscv_inner ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_106 = execute_IntAluPlugin_bitwise; + _zz_108 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_106 = {31'd0, _zz_323}; + _zz_108 = {31'd0, _zz_330}; end default : begin - _zz_106 = execute_SRC_ADD_SUB; + _zz_108 = execute_SRC_ADD_SUB; end endcase end @@ -3708,45 +3722,21 @@ module VexRiscv_inner ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_107 = execute_RS1; + _zz_109 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_107 = {29'd0, _zz_324}; + _zz_109 = {29'd0, _zz_331}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_107 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_107 = {27'd0, _zz_325}; + _zz_109 = {27'd0, _zz_332}; end endcase end - assign _zz_108 = _zz_326[11]; - always @ (*) begin - _zz_109[19] = _zz_108; - _zz_109[18] = _zz_108; - _zz_109[17] = _zz_108; - _zz_109[16] = _zz_108; - _zz_109[15] = _zz_108; - _zz_109[14] = _zz_108; - _zz_109[13] = _zz_108; - _zz_109[12] = _zz_108; - _zz_109[11] = _zz_108; - _zz_109[10] = _zz_108; - _zz_109[9] = _zz_108; - _zz_109[8] = _zz_108; - _zz_109[7] = _zz_108; - _zz_109[6] = _zz_108; - _zz_109[5] = _zz_108; - _zz_109[4] = _zz_108; - _zz_109[3] = _zz_108; - _zz_109[2] = _zz_108; - _zz_109[1] = _zz_108; - _zz_109[0] = _zz_108; - end - - assign _zz_110 = _zz_327[11]; + assign _zz_110 = _zz_333[11]; always @ (*) begin _zz_111[19] = _zz_110; _zz_111[18] = _zz_110; @@ -3770,25 +3760,49 @@ module VexRiscv_inner ( _zz_111[0] = _zz_110; end + assign _zz_112 = _zz_334[11]; + always @ (*) begin + _zz_113[19] = _zz_112; + _zz_113[18] = _zz_112; + _zz_113[17] = _zz_112; + _zz_113[16] = _zz_112; + _zz_113[15] = _zz_112; + _zz_113[14] = _zz_112; + _zz_113[13] = _zz_112; + _zz_113[12] = _zz_112; + _zz_113[11] = _zz_112; + _zz_113[10] = _zz_112; + _zz_113[9] = _zz_112; + _zz_113[8] = _zz_112; + _zz_113[7] = _zz_112; + _zz_113[6] = _zz_112; + _zz_113[5] = _zz_112; + _zz_113[4] = _zz_112; + _zz_113[3] = _zz_112; + _zz_113[2] = _zz_112; + _zz_113[1] = _zz_112; + _zz_113[0] = _zz_112; + end + always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_112 = execute_RS2; + _zz_114 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_112 = {_zz_109,execute_INSTRUCTION[31 : 20]}; + _zz_114 = {_zz_111,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_112 = {_zz_111,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_114 = {_zz_113,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_112 = _zz_39; + _zz_114 = _zz_41; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_328; + execute_SrcPlugin_addSub = _zz_335; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3797,263 +3811,170 @@ module VexRiscv_inner ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_113[0] = execute_SRC1[31]; - _zz_113[1] = execute_SRC1[30]; - _zz_113[2] = execute_SRC1[29]; - _zz_113[3] = execute_SRC1[28]; - _zz_113[4] = execute_SRC1[27]; - _zz_113[5] = execute_SRC1[26]; - _zz_113[6] = execute_SRC1[25]; - _zz_113[7] = execute_SRC1[24]; - _zz_113[8] = execute_SRC1[23]; - _zz_113[9] = execute_SRC1[22]; - _zz_113[10] = execute_SRC1[21]; - _zz_113[11] = execute_SRC1[20]; - _zz_113[12] = execute_SRC1[19]; - _zz_113[13] = execute_SRC1[18]; - _zz_113[14] = execute_SRC1[17]; - _zz_113[15] = execute_SRC1[16]; - _zz_113[16] = execute_SRC1[15]; - _zz_113[17] = execute_SRC1[14]; - _zz_113[18] = execute_SRC1[13]; - _zz_113[19] = execute_SRC1[12]; - _zz_113[20] = execute_SRC1[11]; - _zz_113[21] = execute_SRC1[10]; - _zz_113[22] = execute_SRC1[9]; - _zz_113[23] = execute_SRC1[8]; - _zz_113[24] = execute_SRC1[7]; - _zz_113[25] = execute_SRC1[6]; - _zz_113[26] = execute_SRC1[5]; - _zz_113[27] = execute_SRC1[4]; - _zz_113[28] = execute_SRC1[3]; - _zz_113[29] = execute_SRC1[2]; - _zz_113[30] = execute_SRC1[1]; - _zz_113[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_113 : execute_SRC1); - always @ (*) begin - _zz_114[0] = memory_SHIFT_RIGHT[31]; - _zz_114[1] = memory_SHIFT_RIGHT[30]; - _zz_114[2] = memory_SHIFT_RIGHT[29]; - _zz_114[3] = memory_SHIFT_RIGHT[28]; - _zz_114[4] = memory_SHIFT_RIGHT[27]; - _zz_114[5] = memory_SHIFT_RIGHT[26]; - _zz_114[6] = memory_SHIFT_RIGHT[25]; - _zz_114[7] = memory_SHIFT_RIGHT[24]; - _zz_114[8] = memory_SHIFT_RIGHT[23]; - _zz_114[9] = memory_SHIFT_RIGHT[22]; - _zz_114[10] = memory_SHIFT_RIGHT[21]; - _zz_114[11] = memory_SHIFT_RIGHT[20]; - _zz_114[12] = memory_SHIFT_RIGHT[19]; - _zz_114[13] = memory_SHIFT_RIGHT[18]; - _zz_114[14] = memory_SHIFT_RIGHT[17]; - _zz_114[15] = memory_SHIFT_RIGHT[16]; - _zz_114[16] = memory_SHIFT_RIGHT[15]; - _zz_114[17] = memory_SHIFT_RIGHT[14]; - _zz_114[18] = memory_SHIFT_RIGHT[13]; - _zz_114[19] = memory_SHIFT_RIGHT[12]; - _zz_114[20] = memory_SHIFT_RIGHT[11]; - _zz_114[21] = memory_SHIFT_RIGHT[10]; - _zz_114[22] = memory_SHIFT_RIGHT[9]; - _zz_114[23] = memory_SHIFT_RIGHT[8]; - _zz_114[24] = memory_SHIFT_RIGHT[7]; - _zz_114[25] = memory_SHIFT_RIGHT[6]; - _zz_114[26] = memory_SHIFT_RIGHT[5]; - _zz_114[27] = memory_SHIFT_RIGHT[4]; - _zz_114[28] = memory_SHIFT_RIGHT[3]; - _zz_114[29] = memory_SHIFT_RIGHT[2]; - _zz_114[30] = memory_SHIFT_RIGHT[1]; - _zz_114[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_258)begin - if(_zz_259)begin - if(_zz_115)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_115[0] = execute_SRC1[31]; + _zz_115[1] = execute_SRC1[30]; + _zz_115[2] = execute_SRC1[29]; + _zz_115[3] = execute_SRC1[28]; + _zz_115[4] = execute_SRC1[27]; + _zz_115[5] = execute_SRC1[26]; + _zz_115[6] = execute_SRC1[25]; + _zz_115[7] = execute_SRC1[24]; + _zz_115[8] = execute_SRC1[23]; + _zz_115[9] = execute_SRC1[22]; + _zz_115[10] = execute_SRC1[21]; + _zz_115[11] = execute_SRC1[20]; + _zz_115[12] = execute_SRC1[19]; + _zz_115[13] = execute_SRC1[18]; + _zz_115[14] = execute_SRC1[17]; + _zz_115[15] = execute_SRC1[16]; + _zz_115[16] = execute_SRC1[15]; + _zz_115[17] = execute_SRC1[14]; + _zz_115[18] = execute_SRC1[13]; + _zz_115[19] = execute_SRC1[12]; + _zz_115[20] = execute_SRC1[11]; + _zz_115[21] = execute_SRC1[10]; + _zz_115[22] = execute_SRC1[9]; + _zz_115[23] = execute_SRC1[8]; + _zz_115[24] = execute_SRC1[7]; + _zz_115[25] = execute_SRC1[6]; + _zz_115[26] = execute_SRC1[5]; + _zz_115[27] = execute_SRC1[4]; + _zz_115[28] = execute_SRC1[3]; + _zz_115[29] = execute_SRC1[2]; + _zz_115[30] = execute_SRC1[1]; + _zz_115[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_115 : execute_SRC1); + always @ (*) begin + _zz_116[0] = memory_SHIFT_RIGHT[31]; + _zz_116[1] = memory_SHIFT_RIGHT[30]; + _zz_116[2] = memory_SHIFT_RIGHT[29]; + _zz_116[3] = memory_SHIFT_RIGHT[28]; + _zz_116[4] = memory_SHIFT_RIGHT[27]; + _zz_116[5] = memory_SHIFT_RIGHT[26]; + _zz_116[6] = memory_SHIFT_RIGHT[25]; + _zz_116[7] = memory_SHIFT_RIGHT[24]; + _zz_116[8] = memory_SHIFT_RIGHT[23]; + _zz_116[9] = memory_SHIFT_RIGHT[22]; + _zz_116[10] = memory_SHIFT_RIGHT[21]; + _zz_116[11] = memory_SHIFT_RIGHT[20]; + _zz_116[12] = memory_SHIFT_RIGHT[19]; + _zz_116[13] = memory_SHIFT_RIGHT[18]; + _zz_116[14] = memory_SHIFT_RIGHT[17]; + _zz_116[15] = memory_SHIFT_RIGHT[16]; + _zz_116[16] = memory_SHIFT_RIGHT[15]; + _zz_116[17] = memory_SHIFT_RIGHT[14]; + _zz_116[18] = memory_SHIFT_RIGHT[13]; + _zz_116[19] = memory_SHIFT_RIGHT[12]; + _zz_116[20] = memory_SHIFT_RIGHT[11]; + _zz_116[21] = memory_SHIFT_RIGHT[10]; + _zz_116[22] = memory_SHIFT_RIGHT[9]; + _zz_116[23] = memory_SHIFT_RIGHT[8]; + _zz_116[24] = memory_SHIFT_RIGHT[7]; + _zz_116[25] = memory_SHIFT_RIGHT[6]; + _zz_116[26] = memory_SHIFT_RIGHT[5]; + _zz_116[27] = memory_SHIFT_RIGHT[4]; + _zz_116[28] = memory_SHIFT_RIGHT[3]; + _zz_116[29] = memory_SHIFT_RIGHT[2]; + _zz_116[30] = memory_SHIFT_RIGHT[1]; + _zz_116[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_117 = 1'b0; + if(_zz_265)begin + if(_zz_266)begin + if(_zz_122)begin + _zz_117 = 1'b1; end end end - if(_zz_260)begin - if(_zz_261)begin - if(_zz_117)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_267)begin + if(_zz_268)begin + if(_zz_124)begin + _zz_117 = 1'b1; end end end - if(_zz_262)begin - if(_zz_263)begin - if(_zz_119)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_269)begin + if(_zz_270)begin + if(_zz_126)begin + _zz_117 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_117 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_258)begin - if(_zz_259)begin - if(_zz_116)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_118 = 1'b0; + if(_zz_265)begin + if(_zz_266)begin + if(_zz_123)begin + _zz_118 = 1'b1; end end end - if(_zz_260)begin - if(_zz_261)begin - if(_zz_118)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_267)begin + if(_zz_268)begin + if(_zz_125)begin + _zz_118 = 1'b1; end end end - if(_zz_262)begin - if(_zz_263)begin - if(_zz_120)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_269)begin + if(_zz_270)begin + if(_zz_127)begin + _zz_118 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_118 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_45 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_44[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_55; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_115 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_116 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_117 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_118 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_119 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_120 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_121 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_121 == 3'b000)) begin - _zz_122 = execute_BranchPlugin_eq; - end else if((_zz_121 == 3'b001)) begin - _zz_122 = (! execute_BranchPlugin_eq); - end else if((((_zz_121 & 3'b101) == 3'b101))) begin - _zz_122 = (! execute_SRC_LESS); + assign _zz_128 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_128 == 3'b000)) begin + _zz_129 = execute_BranchPlugin_eq; + end else if((_zz_128 == 3'b001)) begin + _zz_129 = (! execute_BranchPlugin_eq); + end else if((((_zz_128 & 3'b101) == 3'b101))) begin + _zz_129 = (! execute_SRC_LESS); end else begin - _zz_122 = execute_SRC_LESS; + _zz_129 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_123 = 1'b0; + _zz_130 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_123 = 1'b1; - end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_123 = 1'b1; + _zz_130 = 1'b1; end - default : begin - _zz_123 = _zz_122; - end - endcase - end - - assign _zz_124 = _zz_335[11]; - always @ (*) begin - _zz_125[19] = _zz_124; - _zz_125[18] = _zz_124; - _zz_125[17] = _zz_124; - _zz_125[16] = _zz_124; - _zz_125[15] = _zz_124; - _zz_125[14] = _zz_124; - _zz_125[13] = _zz_124; - _zz_125[12] = _zz_124; - _zz_125[11] = _zz_124; - _zz_125[10] = _zz_124; - _zz_125[9] = _zz_124; - _zz_125[8] = _zz_124; - _zz_125[7] = _zz_124; - _zz_125[6] = _zz_124; - _zz_125[5] = _zz_124; - _zz_125[4] = _zz_124; - _zz_125[3] = _zz_124; - _zz_125[2] = _zz_124; - _zz_125[1] = _zz_124; - _zz_125[0] = _zz_124; - end - - assign _zz_126 = _zz_336[19]; - always @ (*) begin - _zz_127[10] = _zz_126; - _zz_127[9] = _zz_126; - _zz_127[8] = _zz_126; - _zz_127[7] = _zz_126; - _zz_127[6] = _zz_126; - _zz_127[5] = _zz_126; - _zz_127[4] = _zz_126; - _zz_127[3] = _zz_126; - _zz_127[2] = _zz_126; - _zz_127[1] = _zz_126; - _zz_127[0] = _zz_126; - end - - assign _zz_128 = _zz_337[11]; - always @ (*) begin - _zz_129[18] = _zz_128; - _zz_129[17] = _zz_128; - _zz_129[16] = _zz_128; - _zz_129[15] = _zz_128; - _zz_129[14] = _zz_128; - _zz_129[13] = _zz_128; - _zz_129[12] = _zz_128; - _zz_129[11] = _zz_128; - _zz_129[10] = _zz_128; - _zz_129[9] = _zz_128; - _zz_129[8] = _zz_128; - _zz_129[7] = _zz_128; - _zz_129[6] = _zz_128; - _zz_129[5] = _zz_128; - _zz_129[4] = _zz_128; - _zz_129[3] = _zz_128; - _zz_129[2] = _zz_128; - _zz_129[1] = _zz_128; - _zz_129[0] = _zz_128; - end - - always @ (*) begin - case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_130 = (_zz_338[1] ^ execute_RS1[1]); - end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_130 = _zz_339[1]; + _zz_130 = 1'b1; end default : begin - _zz_130 = _zz_340[1]; + _zz_130 = _zz_129; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_130); - always @ (*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src1 = execute_RS1; - end - default : begin - execute_BranchPlugin_branch_src1 = execute_PC; - end - endcase - end - - assign _zz_131 = _zz_341[11]; + assign _zz_131 = _zz_342[11]; always @ (*) begin _zz_132[19] = _zz_131; _zz_132[18] = _zz_131; @@ -4077,21 +3998,7 @@ module VexRiscv_inner ( _zz_132[0] = _zz_131; end - always @ (*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_132,execute_INSTRUCTION[31 : 20]}; - end - default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_134,{{{_zz_570,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_136,{{{_zz_571,_zz_572},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_344}; - end - end - endcase - end - - assign _zz_133 = _zz_342[19]; + assign _zz_133 = _zz_343[19]; always @ (*) begin _zz_134[10] = _zz_133; _zz_134[9] = _zz_133; @@ -4106,7 +4013,7 @@ module VexRiscv_inner ( _zz_134[0] = _zz_133; end - assign _zz_135 = _zz_343[11]; + assign _zz_135 = _zz_344[11]; always @ (*) begin _zz_136[18] = _zz_135; _zz_136[17] = _zz_135; @@ -4129,6 +4036,108 @@ module VexRiscv_inner ( _zz_136[0] = _zz_135; end + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_137 = (_zz_345[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_137 = _zz_346[1]; + end + default : begin + _zz_137 = _zz_347[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_137); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_138 = _zz_348[11]; + always @ (*) begin + _zz_139[19] = _zz_138; + _zz_139[18] = _zz_138; + _zz_139[17] = _zz_138; + _zz_139[16] = _zz_138; + _zz_139[15] = _zz_138; + _zz_139[14] = _zz_138; + _zz_139[13] = _zz_138; + _zz_139[12] = _zz_138; + _zz_139[11] = _zz_138; + _zz_139[10] = _zz_138; + _zz_139[9] = _zz_138; + _zz_139[8] = _zz_138; + _zz_139[7] = _zz_138; + _zz_139[6] = _zz_138; + _zz_139[5] = _zz_138; + _zz_139[4] = _zz_138; + _zz_139[3] = _zz_138; + _zz_139[2] = _zz_138; + _zz_139[1] = _zz_138; + _zz_139[0] = _zz_138; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_577,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_578,_zz_579},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_351}; + end + end + endcase + end + + assign _zz_140 = _zz_349[19]; + always @ (*) begin + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; + end + + assign _zz_142 = _zz_350[11]; + always @ (*) begin + _zz_143[18] = _zz_142; + _zz_143[17] = _zz_142; + _zz_143[16] = _zz_142; + _zz_143[15] = _zz_142; + _zz_143[14] = _zz_142; + _zz_143[13] = _zz_142; + _zz_143[12] = _zz_142; + _zz_143[11] = _zz_142; + _zz_143[10] = _zz_142; + _zz_143[9] = _zz_142; + _zz_143[8] = _zz_142; + _zz_143[7] = _zz_142; + _zz_143[6] = _zz_142; + _zz_143[5] = _zz_142; + _zz_143[4] = _zz_142; + _zz_143[3] = _zz_142; + _zz_143[2] = _zz_142; + _zz_143[1] = _zz_142; + _zz_143[0] = _zz_142; + end + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; @@ -4143,18 +4152,18 @@ module VexRiscv_inner ( end end - assign _zz_137 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_138 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_139 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_144 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_145 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_146 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_140 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_141 = _zz_345[0]; - assign _zz_142 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_143 = _zz_347[0]; + assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_148 = _zz_352[0]; + assign _zz_149 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_150 = _zz_354[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_251)begin + if(_zz_258)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4174,7 +4183,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_253)begin + if(_zz_260)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4235,7 +4244,7 @@ module VexRiscv_inner ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4405,7 +4414,7 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_264)begin + if(_zz_271)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4424,20 +4433,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_265)begin + if(_zz_272)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_266)begin + if(_zz_273)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_265)begin + if(_zz_272)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_266)begin + if(_zz_273)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4452,14 +4461,14 @@ module VexRiscv_inner ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_264)begin + if(_zz_271)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_264)begin + if(_zz_271)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4468,7 +4477,7 @@ module VexRiscv_inner ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_278) + case(_zz_285) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4481,45 +4490,45 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_349; + assign execute_CfuPlugin_functionsIds_0 = _zz_356; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_160 = _zz_350[11]; - always @ (*) begin - _zz_161[19] = _zz_160; - _zz_161[18] = _zz_160; - _zz_161[17] = _zz_160; - _zz_161[16] = _zz_160; - _zz_161[15] = _zz_160; - _zz_161[14] = _zz_160; - _zz_161[13] = _zz_160; - _zz_161[12] = _zz_160; - _zz_161[11] = _zz_160; - _zz_161[10] = _zz_160; - _zz_161[9] = _zz_160; - _zz_161[8] = _zz_160; - _zz_161[7] = _zz_160; - _zz_161[6] = _zz_160; - _zz_161[5] = _zz_160; - _zz_161[4] = _zz_160; - _zz_161[3] = _zz_160; - _zz_161[2] = _zz_160; - _zz_161[1] = _zz_160; - _zz_161[0] = _zz_160; + assign _zz_167 = _zz_357[11]; + always @ (*) begin + _zz_168[19] = _zz_167; + _zz_168[18] = _zz_167; + _zz_168[17] = _zz_167; + _zz_168[16] = _zz_167; + _zz_168[15] = _zz_167; + _zz_168[14] = _zz_167; + _zz_168[13] = _zz_167; + _zz_168[12] = _zz_167; + _zz_168[11] = _zz_167; + _zz_168[10] = _zz_167; + _zz_168[9] = _zz_167; + _zz_168[8] = _zz_167; + _zz_168[7] = _zz_167; + _zz_168[6] = _zz_167; + _zz_168[5] = _zz_167; + _zz_168[4] = _zz_167; + _zz_168[3] = _zz_167; + _zz_168[2] = _zz_167; + _zz_168[1] = _zz_167; + _zz_168[0] = _zz_167; end always @ (*) begin case(execute_CfuPlugin_CFU_ENCODING) `Input2Kind_defaultEncoding_RS : begin - _zz_162 = execute_RS2; + _zz_169 = execute_RS2; end default : begin - _zz_162 = {_zz_161,execute_INSTRUCTION[31 : 20]}; + _zz_169 = {_zz_168,execute_INSTRUCTION[31 : 20]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_162; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_169; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4545,7 +4554,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_267) + case(_zz_274) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4559,7 +4568,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_267) + case(_zz_274) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4578,12 +4587,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_351) + $signed(_zz_352)); + assign writeBack_MulPlugin_result = ($signed(_zz_358) + $signed(_zz_359)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_246)begin - if(_zz_268)begin + if(_zz_253)begin + if(_zz_275)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4591,7 +4600,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_269)begin + if(_zz_276)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4602,58 +4611,58 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_356); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_363); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_163 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_163[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_357); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_358 : _zz_359); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_360[31:0]; - assign _zz_164 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_165 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_166 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_170 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_170[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_364); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_365 : _zz_366); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_367[31:0]; + assign _zz_171 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_172 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_173 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_167[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_167[31 : 0] = execute_RS1; + _zz_174[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_174[31 : 0] = execute_RS1; end - assign _zz_169 = (_zz_168 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_169 != 32'h0); + assign _zz_176 = (_zz_175 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_176 != 32'h0); assign _zz_29 = decode_SRC1_CTRL; - assign _zz_27 = _zz_54; - assign _zz_41 = decode_to_execute_SRC1_CTRL; + assign _zz_27 = _zz_56; + assign _zz_43 = decode_to_execute_SRC1_CTRL; assign _zz_26 = decode_ALU_CTRL; - assign _zz_24 = _zz_53; - assign _zz_42 = decode_to_execute_ALU_CTRL; + assign _zz_24 = _zz_55; + assign _zz_44 = decode_to_execute_ALU_CTRL; assign _zz_23 = decode_SRC2_CTRL; - assign _zz_21 = _zz_52; - assign _zz_40 = decode_to_execute_SRC2_CTRL; + assign _zz_21 = _zz_54; + assign _zz_42 = decode_to_execute_SRC2_CTRL; assign _zz_20 = decode_ALU_BITWISE_CTRL; - assign _zz_18 = _zz_51; - assign _zz_43 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_18 = _zz_53; + assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; assign _zz_17 = decode_SHIFT_CTRL; assign _zz_14 = execute_SHIFT_CTRL; - assign _zz_15 = _zz_50; - assign _zz_38 = decode_to_execute_SHIFT_CTRL; - assign _zz_37 = execute_to_memory_SHIFT_CTRL; + assign _zz_15 = _zz_52; + assign _zz_40 = decode_to_execute_SHIFT_CTRL; + assign _zz_39 = execute_to_memory_SHIFT_CTRL; assign _zz_12 = decode_BRANCH_CTRL; - assign _zz_56 = _zz_49; - assign _zz_34 = decode_to_execute_BRANCH_CTRL; + assign _zz_58 = _zz_51; + assign _zz_36 = decode_to_execute_BRANCH_CTRL; assign _zz_10 = decode_ENV_CTRL; assign _zz_7 = execute_ENV_CTRL; assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_48; - assign _zz_32 = decode_to_execute_ENV_CTRL; - assign _zz_31 = execute_to_memory_ENV_CTRL; - assign _zz_33 = memory_to_writeBack_ENV_CTRL; + assign _zz_8 = _zz_50; + assign _zz_34 = decode_to_execute_ENV_CTRL; + assign _zz_33 = execute_to_memory_ENV_CTRL; + assign _zz_35 = memory_to_writeBack_ENV_CTRL; assign _zz_3 = decode_CfuPlugin_CFU_ENCODING; - assign _zz_1 = _zz_47; - assign _zz_30 = decode_to_execute_CfuPlugin_CFU_ENCODING; + assign _zz_1 = _zz_49; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_ENCODING; assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4675,272 +4684,272 @@ module VexRiscv_inner ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_170 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_170[12 : 0] = 13'h1000; - _zz_170[25 : 20] = 6'h20; + _zz_177[12 : 0] = 13'h1000; + _zz_177[25 : 20] = 6'h20; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_171[3 : 0] = 4'b1011; + _zz_178[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_172[4 : 0] = 5'h16; + _zz_179[4 : 0] = 5'h16; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_173[5 : 0] = 6'h21; + _zz_180[5 : 0] = 6'h21; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_174[31 : 30] = CsrPlugin_misa_base; - _zz_174[25 : 0] = CsrPlugin_misa_extensions; + _zz_181[31 : 30] = CsrPlugin_misa_base; + _zz_181[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_175[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_175[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_175[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_182[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_182[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_182[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_176[11 : 11] = CsrPlugin_mip_MEIP; - _zz_176[7 : 7] = CsrPlugin_mip_MTIP; - _zz_176[3 : 3] = CsrPlugin_mip_MSIP; + _zz_183[11 : 11] = CsrPlugin_mip_MEIP; + _zz_183[7 : 7] = CsrPlugin_mip_MTIP; + _zz_183[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_177[11 : 11] = CsrPlugin_mie_MEIE; - _zz_177[7 : 7] = CsrPlugin_mie_MTIE; - _zz_177[3 : 3] = CsrPlugin_mie_MSIE; + _zz_184[11 : 11] = CsrPlugin_mie_MEIE; + _zz_184[7 : 7] = CsrPlugin_mie_MTIE; + _zz_184[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_178[31 : 2] = CsrPlugin_mtvec_base; - _zz_178[1 : 0] = CsrPlugin_mtvec_mode; + _zz_185[31 : 2] = CsrPlugin_mtvec_base; + _zz_185[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_179[31 : 0] = CsrPlugin_mepc; + _zz_186[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_180[31 : 0] = CsrPlugin_mscratch; + _zz_187[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_181[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_181[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_188[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_188[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_182[31 : 0] = CsrPlugin_mtval; + _zz_189[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_183[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_184[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_185[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_186[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_187[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_188[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_189[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_190[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_2820)begin - _zz_191[31 : 0] = _zz_144; + _zz_198[31 : 0] = _zz_151; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_199 = 32'h0; if(execute_CsrPlugin_csr_2822)begin - _zz_192[31 : 0] = _zz_146; + _zz_199[31 : 0] = _zz_153; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_200 = 32'h0; if(execute_CsrPlugin_csr_2824)begin - _zz_193[31 : 0] = _zz_148; + _zz_200[31 : 0] = _zz_155; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_201 = 32'h0; if(execute_CsrPlugin_csr_2826)begin - _zz_194[31 : 0] = _zz_150; + _zz_201[31 : 0] = _zz_157; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_202 = 32'h0; if(execute_CsrPlugin_csr_2828)begin - _zz_195[31 : 0] = _zz_152; + _zz_202[31 : 0] = _zz_159; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_203 = 32'h0; if(execute_CsrPlugin_csr_2830)begin - _zz_196[31 : 0] = _zz_154; + _zz_203[31 : 0] = _zz_161; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_204 = 32'h0; if(execute_CsrPlugin_csr_2832)begin - _zz_197[31 : 0] = _zz_156; + _zz_204[31 : 0] = _zz_163; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_205 = 32'h0; if(execute_CsrPlugin_csr_2834)begin - _zz_198[31 : 0] = _zz_158; + _zz_205[31 : 0] = _zz_165; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_206 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_199[31 : 0] = _zz_168; + _zz_206[31 : 0] = _zz_175; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_207 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_200[31 : 0] = _zz_169; + _zz_207[31 : 0] = _zz_176; end end - assign execute_CsrPlugin_readData = (((((_zz_170 | _zz_171) | (_zz_172 | _zz_173)) | ((_zz_573 | _zz_174) | (_zz_175 | _zz_176))) | (((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_181 | _zz_182) | (_zz_183 | _zz_184)))) | ((((_zz_185 | _zz_186) | (_zz_187 | _zz_188)) | ((_zz_189 | _zz_190) | (_zz_191 | _zz_192))) | (((_zz_193 | _zz_194) | (_zz_195 | _zz_196)) | ((_zz_197 | _zz_198) | (_zz_199 | _zz_200))))); - assign iBusWishbone_ADR = {_zz_377,_zz_201}; - assign iBusWishbone_CTI = ((_zz_201 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_580 | _zz_181) | (_zz_182 | _zz_183))) | (((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191)))) | ((((_zz_192 | _zz_193) | (_zz_194 | _zz_195)) | ((_zz_196 | _zz_197) | (_zz_198 | _zz_199))) | (((_zz_200 | _zz_201) | (_zz_202 | _zz_203)) | ((_zz_204 | _zz_205) | (_zz_206 | _zz_207))))); + assign iBusWishbone_ADR = {_zz_384,_zz_208}; + assign iBusWishbone_CTI = ((_zz_208 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_270)begin + if(_zz_277)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_270)begin + if(_zz_277)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_202; + assign iBus_rsp_valid = _zz_209; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_208 = (dBus_cmd_payload_length != 3'b000); - assign _zz_204 = dBus_cmd_valid; - assign _zz_206 = dBus_cmd_payload_wr; - assign _zz_207 = (_zz_203 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_205 && (_zz_206 || _zz_207)); - assign dBusWishbone_ADR = ((_zz_208 ? {{dBus_cmd_payload_address[31 : 5],_zz_203},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_208 ? (_zz_207 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_215 = (dBus_cmd_payload_length != 3'b000); + assign _zz_211 = dBus_cmd_valid; + assign _zz_213 = dBus_cmd_payload_wr; + assign _zz_214 = (_zz_210 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_212 && (_zz_213 || _zz_214)); + assign dBusWishbone_ADR = ((_zz_215 ? {{dBus_cmd_payload_address[31 : 5],_zz_210},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_215 ? (_zz_214 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_206 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_206; + assign dBusWishbone_SEL = (_zz_213 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_213; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_205 = (_zz_204 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_204; - assign dBusWishbone_STB = _zz_204; - assign dBus_rsp_valid = _zz_209; + assign _zz_212 = (_zz_211 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_211; + assign dBusWishbone_STB = _zz_211; + assign dBus_rsp_valid = _zz_216; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4949,21 +4958,21 @@ module VexRiscv_inner ( IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_69 <= 1'b0; _zz_71 <= 1'b0; + _zz_73 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_84; + IBusCachedPlugin_rspCounter <= _zz_86; IBusCachedPlugin_rspCounter <= 32'h0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_85; + DBusCachedPlugin_rspCounter <= _zz_87; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_105 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_107 <= 1'b1; + _zz_119 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4987,15 +4996,15 @@ module VexRiscv_inner ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_168 <= 32'h0; + _zz_175 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_201 <= 3'b000; - _zz_202 <= 1'b0; - _zz_203 <= 3'b000; + _zz_208 <= 3'b000; _zz_209 <= 1'b0; + _zz_210 <= 3'b000; + _zz_216 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5017,16 +5026,16 @@ module VexRiscv_inner ( IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_69 <= 1'b0; + _zz_71 <= 1'b0; end - if(_zz_67)begin - _zz_69 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_69)begin + _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_71 <= 1'b0; + _zz_73 <= 1'b0; end if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + _zz_73 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; @@ -5076,7 +5085,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_271)begin + if(_zz_278)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5085,8 +5094,8 @@ module VexRiscv_inner ( if(dBus_rsp_valid)begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_105 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_107 <= 1'b0; + _zz_119 <= (_zz_47 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5108,14 +5117,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_272)begin - if(_zz_273)begin + if(_zz_279)begin + if(_zz_280)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_274)begin + if(_zz_281)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_275)begin + if(_zz_282)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5140,7 +5149,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_254)begin + if(_zz_261)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5151,8 +5160,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_255)begin - case(_zz_256) + if(_zz_262)begin + case(_zz_263) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5162,7 +5171,7 @@ module VexRiscv_inner ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_139,{_zz_138,_zz_137}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_146,{_zz_145,_zz_144}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -5178,12 +5187,12 @@ module VexRiscv_inner ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_276)begin + if(_zz_283)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= execute_CfuPlugin_CFU_IN_FLIGHT; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; @@ -5212,41 +5221,41 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_370[0]; - CsrPlugin_mstatus_MIE <= _zz_371[0]; + CsrPlugin_mstatus_MPIE <= _zz_377[0]; + CsrPlugin_mstatus_MIE <= _zz_378[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_373[0]; - CsrPlugin_mie_MTIE <= _zz_374[0]; - CsrPlugin_mie_MSIE <= _zz_375[0]; + CsrPlugin_mie_MEIE <= _zz_380[0]; + CsrPlugin_mie_MTIE <= _zz_381[0]; + CsrPlugin_mie_MSIE <= _zz_382[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_175 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_270)begin + if(_zz_277)begin if(iBusWishbone_ACK)begin - _zz_201 <= (_zz_201 + 3'b001); + _zz_208 <= (_zz_208 + 3'b001); end end - _zz_202 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_204 && _zz_205))begin - _zz_203 <= (_zz_203 + 3'b001); - if(_zz_207)begin - _zz_203 <= 3'b000; + _zz_209 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_211 && _zz_212))begin + _zz_210 <= (_zz_210 + 3'b001); + if(_zz_214)begin + _zz_210 <= 3'b000; end end - _zz_209 <= ((_zz_204 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_216 <= ((_zz_211 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_72 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_74 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; @@ -5254,7 +5263,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_271)begin + if(_zz_278)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5272,8 +5281,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_120 <= _zz_46[11 : 7]; + _zz_121 <= _zz_57; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5281,37 +5290,37 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_251)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_141 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_141 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_258)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_253)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_143 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_143 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(_zz_260)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); end if(DBusCachedPlugin_exceptionBus_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_272)begin - if(_zz_273)begin + if(_zz_279)begin + if(_zz_280)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_274)begin + if(_zz_281)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_275)begin + if(_zz_282)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_254)begin + if(_zz_261)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5325,31 +5334,31 @@ module VexRiscv_inner ( end endcase end - if(_zz_145[0])begin - _zz_144 <= (_zz_144 + 32'h00000001); + if(_zz_152[0])begin + _zz_151 <= (_zz_151 + 32'h00000001); end - if(_zz_147[0])begin - _zz_146 <= (_zz_146 + 32'h00000001); + if(_zz_154[0])begin + _zz_153 <= (_zz_153 + 32'h00000001); end - if(_zz_149[0])begin - _zz_148 <= (_zz_148 + 32'h00000001); + if(_zz_156[0])begin + _zz_155 <= (_zz_155 + 32'h00000001); end - if(_zz_151[0])begin - _zz_150 <= (_zz_150 + 32'h00000001); + if(_zz_158[0])begin + _zz_157 <= (_zz_157 + 32'h00000001); end - if(_zz_153[0])begin - _zz_152 <= (_zz_152 + 32'h00000001); + if(_zz_160[0])begin + _zz_159 <= (_zz_159 + 32'h00000001); end - if(_zz_155[0])begin - _zz_154 <= (_zz_154 + 32'h00000001); + if(_zz_162[0])begin + _zz_161 <= (_zz_161 + 32'h00000001); end - if(_zz_157[0])begin - _zz_156 <= (_zz_156 + 32'h00000001); + if(_zz_164[0])begin + _zz_163 <= (_zz_163 + 32'h00000001); end - if(_zz_159[0])begin - _zz_158 <= (_zz_158 + 32'h00000001); + if(_zz_166[0])begin + _zz_165 <= (_zz_165 + 32'h00000001); end - if(_zz_276)begin + if(_zz_283)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5359,27 +5368,27 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_246)begin - if(_zz_268)begin + if(_zz_253)begin + if(_zz_275)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_361[31:0]; + memory_DivPlugin_div_result <= _zz_368[31:0]; end end end - if(_zz_269)begin + if(_zz_276)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_166 ? (~ _zz_167) : _zz_167) + _zz_367); - memory_DivPlugin_rs2 <= ((_zz_165 ? (~ execute_RS2) : execute_RS2) + _zz_369); - memory_DivPlugin_div_needRevert <= ((_zz_166 ^ (_zz_165 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_173 ? (~ _zz_174) : _zz_174) + _zz_374); + memory_DivPlugin_rs2 <= ((_zz_172 ? (~ execute_RS2) : execute_RS2) + _zz_376); + memory_DivPlugin_div_needRevert <= ((_zz_173 ^ (_zz_172 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin decode_to_execute_PC <= decode_PC; end if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_39; + execute_to_memory_PC <= _zz_41; end if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin memory_to_writeBack_PC <= memory_PC; @@ -5394,13 +5403,13 @@ module VexRiscv_inner ( memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_58; + decode_to_execute_FORMAL_PC_NEXT <= _zz_60; end if((! memory_arbitration_isStuck))begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_57; + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_59; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; @@ -5535,10 +5544,10 @@ module VexRiscv_inner ( memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_35; + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_36; + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; end if((! memory_arbitration_isStuck))begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; @@ -5549,6 +5558,9 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + end if((! memory_arbitration_isStuck))begin execute_to_memory_MUL_LL <= execute_MUL_LL; end @@ -5689,7 +5701,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_372[0]; + CsrPlugin_mip_MSIP <= _zz_379[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5710,7 +5722,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_376[0]; + CsrPlugin_mcause_interrupt <= _zz_383[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5741,82 +5753,82 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_2820)begin if(execute_CsrPlugin_writeEnable)begin - _zz_144 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2821)begin if(execute_CsrPlugin_writeEnable)begin - _zz_145 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2822)begin if(execute_CsrPlugin_writeEnable)begin - _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2823)begin if(execute_CsrPlugin_writeEnable)begin - _zz_147 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2824)begin if(execute_CsrPlugin_writeEnable)begin - _zz_148 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2825)begin if(execute_CsrPlugin_writeEnable)begin - _zz_149 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2826)begin if(execute_CsrPlugin_writeEnable)begin - _zz_150 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2827)begin if(execute_CsrPlugin_writeEnable)begin - _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2828)begin if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2829)begin if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2830)begin if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2831)begin if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2832)begin if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2833)begin if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2834)begin if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2835)begin if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -6201,7 +6213,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_23)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -6215,7 +6227,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_23)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -6245,7 +6257,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -6272,7 +6284,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -6304,7 +6316,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -6314,7 +6326,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index 46a5db4..65743dd 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define Input2Kind_defaultEncoding_type [0:0] @@ -95,37 +95,37 @@ module VexRiscv_inner ( input reset, input debugReset ); - wire _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - wire _zz_219; wire _zz_220; - reg _zz_221; + wire _zz_221; wire _zz_222; - wire [31:0] _zz_223; + wire _zz_223; wire _zz_224; - wire [31:0] _zz_225; - reg _zz_226; + wire _zz_225; + wire _zz_226; wire _zz_227; - wire _zz_228; - wire [31:0] _zz_229; - wire _zz_230; + reg _zz_228; + wire _zz_229; + wire [31:0] _zz_230; wire _zz_231; - wire _zz_232; - wire _zz_233; + wire [31:0] _zz_232; + reg _zz_233; wire _zz_234; wire _zz_235; - wire _zz_236; + wire [31:0] _zz_236; wire _zz_237; - wire [3:0] _zz_238; + wire _zz_238; wire _zz_239; wire _zz_240; - reg [31:0] _zz_241; - reg [31:0] _zz_242; - reg [31:0] _zz_243; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire [3:0] _zz_245; + wire _zz_246; + wire _zz_247; + reg [31:0] _zz_248; + reg [31:0] _zz_249; + reg [31:0] _zz_250; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -158,13 +158,6 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_244; - wire _zz_245; - wire _zz_246; - wire _zz_247; - wire _zz_248; - wire _zz_249; - wire _zz_250; wire _zz_251; wire _zz_252; wire _zz_253; @@ -176,50 +169,50 @@ module VexRiscv_inner ( wire _zz_259; wire _zz_260; wire _zz_261; - wire [1:0] _zz_262; + wire _zz_262; wire _zz_263; wire _zz_264; wire _zz_265; wire _zz_266; wire _zz_267; wire _zz_268; - wire _zz_269; + wire [1:0] _zz_269; wire _zz_270; wire _zz_271; wire _zz_272; - wire [1:0] _zz_273; + wire _zz_273; wire _zz_274; wire _zz_275; - wire [5:0] _zz_276; + wire _zz_276; wire _zz_277; wire _zz_278; wire _zz_279; - wire _zz_280; + wire [1:0] _zz_280; wire _zz_281; wire _zz_282; - wire _zz_283; - wire [1:0] _zz_284; + wire [5:0] _zz_283; + wire _zz_284; wire _zz_285; - wire [1:0] _zz_286; - wire [51:0] _zz_287; - wire [51:0] _zz_288; - wire [51:0] _zz_289; - wire [32:0] _zz_290; - wire [51:0] _zz_291; - wire [49:0] _zz_292; - wire [51:0] _zz_293; - wire [49:0] _zz_294; + wire _zz_286; + wire _zz_287; + wire _zz_288; + wire _zz_289; + wire _zz_290; + wire [1:0] _zz_291; + wire _zz_292; + wire [1:0] _zz_293; + wire [51:0] _zz_294; wire [51:0] _zz_295; - wire [32:0] _zz_296; - wire [31:0] _zz_297; - wire [32:0] _zz_298; - wire [0:0] _zz_299; - wire [0:0] _zz_300; - wire [0:0] _zz_301; - wire [0:0] _zz_302; - wire [0:0] _zz_303; - wire [0:0] _zz_304; - wire [0:0] _zz_305; + wire [51:0] _zz_296; + wire [32:0] _zz_297; + wire [51:0] _zz_298; + wire [49:0] _zz_299; + wire [51:0] _zz_300; + wire [49:0] _zz_301; + wire [51:0] _zz_302; + wire [32:0] _zz_303; + wire [31:0] _zz_304; + wire [32:0] _zz_305; wire [0:0] _zz_306; wire [0:0] _zz_307; wire [0:0] _zz_308; @@ -232,285 +225,293 @@ module VexRiscv_inner ( wire [0:0] _zz_315; wire [0:0] _zz_316; wire [0:0] _zz_317; - wire [3:0] _zz_318; - wire [2:0] _zz_319; - wire [31:0] _zz_320; - wire [11:0] _zz_321; - wire [31:0] _zz_322; - wire [19:0] _zz_323; - wire [11:0] _zz_324; - wire [31:0] _zz_325; - wire [31:0] _zz_326; - wire [19:0] _zz_327; + wire [0:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire [0:0] _zz_321; + wire [0:0] _zz_322; + wire [0:0] _zz_323; + wire [0:0] _zz_324; + wire [3:0] _zz_325; + wire [2:0] _zz_326; + wire [31:0] _zz_327; wire [11:0] _zz_328; - wire [2:0] _zz_329; - wire [2:0] _zz_330; - wire [0:0] _zz_331; - wire [2:0] _zz_332; - wire [4:0] _zz_333; - wire [11:0] _zz_334; + wire [31:0] _zz_329; + wire [19:0] _zz_330; + wire [11:0] _zz_331; + wire [31:0] _zz_332; + wire [31:0] _zz_333; + wire [19:0] _zz_334; wire [11:0] _zz_335; - wire [31:0] _zz_336; - wire [31:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire [31:0] _zz_340; - wire [31:0] _zz_341; - wire [31:0] _zz_342; - wire [11:0] _zz_343; - wire [19:0] _zz_344; - wire [11:0] _zz_345; + wire [2:0] _zz_336; + wire [2:0] _zz_337; + wire [0:0] _zz_338; + wire [2:0] _zz_339; + wire [4:0] _zz_340; + wire [11:0] _zz_341; + wire [11:0] _zz_342; + wire [31:0] _zz_343; + wire [31:0] _zz_344; + wire [31:0] _zz_345; wire [31:0] _zz_346; wire [31:0] _zz_347; wire [31:0] _zz_348; - wire [11:0] _zz_349; - wire [19:0] _zz_350; - wire [11:0] _zz_351; - wire [2:0] _zz_352; - wire [1:0] _zz_353; - wire [1:0] _zz_354; - wire [1:0] _zz_355; - wire [1:0] _zz_356; + wire [31:0] _zz_349; + wire [11:0] _zz_350; + wire [19:0] _zz_351; + wire [11:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; + wire [31:0] _zz_355; + wire [11:0] _zz_356; wire [19:0] _zz_357; wire [11:0] _zz_358; - wire [65:0] _zz_359; - wire [65:0] _zz_360; - wire [31:0] _zz_361; - wire [31:0] _zz_362; - wire [0:0] _zz_363; - wire [5:0] _zz_364; - wire [32:0] _zz_365; - wire [31:0] _zz_366; - wire [31:0] _zz_367; - wire [32:0] _zz_368; - wire [32:0] _zz_369; - wire [32:0] _zz_370; - wire [32:0] _zz_371; - wire [0:0] _zz_372; - wire [32:0] _zz_373; - wire [0:0] _zz_374; + wire [2:0] _zz_359; + wire [1:0] _zz_360; + wire [1:0] _zz_361; + wire [1:0] _zz_362; + wire [1:0] _zz_363; + wire [19:0] _zz_364; + wire [11:0] _zz_365; + wire [65:0] _zz_366; + wire [65:0] _zz_367; + wire [31:0] _zz_368; + wire [31:0] _zz_369; + wire [0:0] _zz_370; + wire [5:0] _zz_371; + wire [32:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; wire [32:0] _zz_375; - wire [0:0] _zz_376; - wire [31:0] _zz_377; - wire [0:0] _zz_378; + wire [32:0] _zz_376; + wire [32:0] _zz_377; + wire [32:0] _zz_378; wire [0:0] _zz_379; - wire [0:0] _zz_380; + wire [32:0] _zz_380; wire [0:0] _zz_381; - wire [0:0] _zz_382; + wire [32:0] _zz_382; wire [0:0] _zz_383; - wire [0:0] _zz_384; - wire [26:0] _zz_385; - wire _zz_386; - wire _zz_387; - wire [1:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire [31:0] _zz_391; - wire _zz_392; - wire [0:0] _zz_393; - wire [14:0] _zz_394; - wire [31:0] _zz_395; + wire [31:0] _zz_384; + wire [0:0] _zz_385; + wire [0:0] _zz_386; + wire [0:0] _zz_387; + wire [0:0] _zz_388; + wire [0:0] _zz_389; + wire [0:0] _zz_390; + wire [0:0] _zz_391; + wire [26:0] _zz_392; + wire _zz_393; + wire _zz_394; + wire [1:0] _zz_395; wire [31:0] _zz_396; wire [31:0] _zz_397; - wire _zz_398; - wire [0:0] _zz_399; - wire [8:0] _zz_400; - wire [31:0] _zz_401; + wire [31:0] _zz_398; + wire _zz_399; + wire [0:0] _zz_400; + wire [14:0] _zz_401; wire [31:0] _zz_402; wire [31:0] _zz_403; - wire _zz_404; - wire [0:0] _zz_405; - wire [2:0] _zz_406; - wire _zz_407; - wire _zz_408; - wire _zz_409; + wire [31:0] _zz_404; + wire _zz_405; + wire [0:0] _zz_406; + wire [8:0] _zz_407; + wire [31:0] _zz_408; + wire [31:0] _zz_409; wire [31:0] _zz_410; - wire [0:0] _zz_411; + wire _zz_411; wire [0:0] _zz_412; - wire _zz_413; - wire [0:0] _zz_414; - wire [28:0] _zz_415; - wire [0:0] _zz_416; - wire [0:0] _zz_417; + wire [2:0] _zz_413; + wire _zz_414; + wire _zz_415; + wire _zz_416; + wire [31:0] _zz_417; wire [0:0] _zz_418; wire [0:0] _zz_419; wire _zz_420; wire [0:0] _zz_421; - wire [23:0] _zz_422; - wire [31:0] _zz_423; - wire [31:0] _zz_424; - wire [31:0] _zz_425; - wire _zz_426; + wire [28:0] _zz_422; + wire [0:0] _zz_423; + wire [0:0] _zz_424; + wire [0:0] _zz_425; + wire [0:0] _zz_426; wire _zz_427; wire [0:0] _zz_428; - wire [0:0] _zz_429; - wire [0:0] _zz_430; - wire [0:0] _zz_431; - wire _zz_432; - wire [0:0] _zz_433; - wire [20:0] _zz_434; - wire [31:0] _zz_435; - wire [31:0] _zz_436; - wire _zz_437; - wire _zz_438; - wire [0:0] _zz_439; - wire [1:0] _zz_440; - wire [0:0] _zz_441; - wire [0:0] _zz_442; - wire _zz_443; - wire [0:0] _zz_444; - wire [17:0] _zz_445; - wire [31:0] _zz_446; - wire [31:0] _zz_447; - wire [31:0] _zz_448; - wire [31:0] _zz_449; - wire [31:0] _zz_450; - wire [31:0] _zz_451; - wire [31:0] _zz_452; + wire [23:0] _zz_429; + wire [31:0] _zz_430; + wire [31:0] _zz_431; + wire [31:0] _zz_432; + wire _zz_433; + wire _zz_434; + wire [0:0] _zz_435; + wire [0:0] _zz_436; + wire [0:0] _zz_437; + wire [0:0] _zz_438; + wire _zz_439; + wire [0:0] _zz_440; + wire [20:0] _zz_441; + wire [31:0] _zz_442; + wire [31:0] _zz_443; + wire _zz_444; + wire _zz_445; + wire [0:0] _zz_446; + wire [1:0] _zz_447; + wire [0:0] _zz_448; + wire [0:0] _zz_449; + wire _zz_450; + wire [0:0] _zz_451; + wire [17:0] _zz_452; wire [31:0] _zz_453; - wire _zz_454; - wire [1:0] _zz_455; - wire [1:0] _zz_456; - wire _zz_457; - wire [0:0] _zz_458; - wire [14:0] _zz_459; + wire [31:0] _zz_454; + wire [31:0] _zz_455; + wire [31:0] _zz_456; + wire [31:0] _zz_457; + wire [31:0] _zz_458; + wire [31:0] _zz_459; wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire [31:0] _zz_462; - wire [31:0] _zz_463; - wire [31:0] _zz_464; - wire [31:0] _zz_465; - wire [0:0] _zz_466; - wire [1:0] _zz_467; - wire [4:0] _zz_468; - wire [4:0] _zz_469; - wire _zz_470; - wire [0:0] _zz_471; - wire [11:0] _zz_472; - wire [31:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; - wire _zz_479; - wire [0:0] _zz_480; - wire [1:0] _zz_481; + wire _zz_461; + wire [1:0] _zz_462; + wire [1:0] _zz_463; + wire _zz_464; + wire [0:0] _zz_465; + wire [14:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [0:0] _zz_473; + wire [1:0] _zz_474; + wire [4:0] _zz_475; + wire [4:0] _zz_476; + wire _zz_477; + wire [0:0] _zz_478; + wire [11:0] _zz_479; + wire [31:0] _zz_480; + wire [31:0] _zz_481; wire [31:0] _zz_482; wire [31:0] _zz_483; - wire [0:0] _zz_484; - wire [4:0] _zz_485; - wire [4:0] _zz_486; - wire [4:0] _zz_487; - wire _zz_488; - wire [0:0] _zz_489; - wire [8:0] _zz_490; - wire [31:0] _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire _zz_494; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire _zz_486; + wire [0:0] _zz_487; + wire [1:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; + wire [0:0] _zz_491; + wire [4:0] _zz_492; + wire [4:0] _zz_493; + wire [4:0] _zz_494; wire _zz_495; - wire [31:0] _zz_496; - wire [31:0] _zz_497; - wire _zz_498; - wire [0:0] _zz_499; - wire [2:0] _zz_500; - wire [0:0] _zz_501; - wire [2:0] _zz_502; - wire [0:0] _zz_503; - wire [4:0] _zz_504; - wire [1:0] _zz_505; - wire [1:0] _zz_506; - wire _zz_507; + wire [0:0] _zz_496; + wire [8:0] _zz_497; + wire [31:0] _zz_498; + wire [31:0] _zz_499; + wire [31:0] _zz_500; + wire _zz_501; + wire _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire _zz_505; + wire [0:0] _zz_506; + wire [2:0] _zz_507; wire [0:0] _zz_508; - wire [6:0] _zz_509; - wire [31:0] _zz_510; - wire [31:0] _zz_511; - wire [31:0] _zz_512; - wire _zz_513; - wire [0:0] _zz_514; + wire [2:0] _zz_509; + wire [0:0] _zz_510; + wire [4:0] _zz_511; + wire [1:0] _zz_512; + wire [1:0] _zz_513; + wire _zz_514; wire [0:0] _zz_515; - wire [31:0] _zz_516; + wire [6:0] _zz_516; wire [31:0] _zz_517; - wire _zz_518; - wire [0:0] _zz_519; - wire [0:0] _zz_520; - wire _zz_521; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire _zz_520; + wire [0:0] _zz_521; wire [0:0] _zz_522; - wire [2:0] _zz_523; - wire _zz_524; - wire [0:0] _zz_525; + wire [31:0] _zz_523; + wire [31:0] _zz_524; + wire _zz_525; wire [0:0] _zz_526; wire [0:0] _zz_527; - wire [0:0] _zz_528; - wire _zz_529; - wire [0:0] _zz_530; - wire [4:0] _zz_531; - wire [31:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire [31:0] _zz_535; - wire [31:0] _zz_536; - wire [31:0] _zz_537; - wire [31:0] _zz_538; + wire _zz_528; + wire [0:0] _zz_529; + wire [2:0] _zz_530; + wire _zz_531; + wire [0:0] _zz_532; + wire [0:0] _zz_533; + wire [0:0] _zz_534; + wire [0:0] _zz_535; + wire _zz_536; + wire [0:0] _zz_537; + wire [4:0] _zz_538; wire [31:0] _zz_539; wire [31:0] _zz_540; wire [31:0] _zz_541; wire [31:0] _zz_542; wire [31:0] _zz_543; wire [31:0] _zz_544; - wire _zz_545; - wire [0:0] _zz_546; - wire [0:0] _zz_547; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; wire [31:0] _zz_548; wire [31:0] _zz_549; wire [31:0] _zz_550; wire [31:0] _zz_551; - wire [31:0] _zz_552; - wire _zz_553; - wire [3:0] _zz_554; - wire [3:0] _zz_555; - wire _zz_556; - wire [0:0] _zz_557; - wire [2:0] _zz_558; + wire _zz_552; + wire [0:0] _zz_553; + wire [0:0] _zz_554; + wire [31:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; wire [31:0] _zz_559; - wire [31:0] _zz_560; - wire [31:0] _zz_561; - wire [31:0] _zz_562; - wire [31:0] _zz_563; - wire [31:0] _zz_564; - wire _zz_565; - wire [0:0] _zz_566; - wire [1:0] _zz_567; - wire _zz_568; - wire [2:0] _zz_569; - wire [2:0] _zz_570; - wire _zz_571; - wire [0:0] _zz_572; + wire _zz_560; + wire [3:0] _zz_561; + wire [3:0] _zz_562; + wire _zz_563; + wire [0:0] _zz_564; + wire [2:0] _zz_565; + wire [31:0] _zz_566; + wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [31:0] _zz_570; + wire [31:0] _zz_571; + wire _zz_572; wire [0:0] _zz_573; - wire [31:0] _zz_574; - wire [31:0] _zz_575; - wire [31:0] _zz_576; - wire [31:0] _zz_577; - wire [31:0] _zz_578; - wire [31:0] _zz_579; - wire [31:0] _zz_580; - wire _zz_581; - wire _zz_582; - wire _zz_583; - wire [0:0] _zz_584; - wire [0:0] _zz_585; - wire _zz_586; - wire _zz_587; + wire [1:0] _zz_574; + wire _zz_575; + wire [2:0] _zz_576; + wire [2:0] _zz_577; + wire _zz_578; + wire [0:0] _zz_579; + wire [0:0] _zz_580; + wire [31:0] _zz_581; + wire [31:0] _zz_582; + wire [31:0] _zz_583; + wire [31:0] _zz_584; + wire [31:0] _zz_585; + wire [31:0] _zz_586; + wire [31:0] _zz_587; wire _zz_588; wire _zz_589; - wire [31:0] _zz_590; + wire _zz_590; + wire [0:0] _zz_591; + wire [0:0] _zz_592; + wire _zz_593; + wire _zz_594; + wire _zz_595; + wire _zz_596; + wire [31:0] _zz_597; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -592,19 +593,21 @@ module VexRiscv_inner ( wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; + reg _zz_30; + reg _zz_31; wire memory_CfuPlugin_CFU_IN_FLIGHT; wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_ENCODING; - wire `Input2Kind_defaultEncoding_type _zz_30; + wire `Input2Kind_defaultEncoding_type _zz_32; wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_31; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_32; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; @@ -612,10 +615,10 @@ module VexRiscv_inner ( (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_34; + wire `BranchCtrlEnum_defaultEncoding_type _zz_36; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_35; + reg [31:0] _zz_37; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -625,44 +628,44 @@ module VexRiscv_inner ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_36; + reg [31:0] _zz_38; wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_37; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_38; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_39; + wire [31:0] _zz_41; wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_40; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42; wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_41; + wire `Src1CtrlEnum_defaultEncoding_type _zz_43; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_42; + wire `AluCtrlEnum_defaultEncoding_type _zz_44; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; - wire [31:0] _zz_44; - wire _zz_45; - reg _zz_46; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; + wire [31:0] _zz_46; + wire _zz_47; + reg _zz_48; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_47; - wire `EnvCtrlEnum_defaultEncoding_type _zz_48; - wire `BranchCtrlEnum_defaultEncoding_type _zz_49; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_50; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_51; - wire `Src2CtrlEnum_defaultEncoding_type _zz_52; - wire `AluCtrlEnum_defaultEncoding_type _zz_53; - wire `Src1CtrlEnum_defaultEncoding_type _zz_54; - reg [31:0] _zz_55; + wire `Input2Kind_defaultEncoding_type _zz_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; + wire `Src2CtrlEnum_defaultEncoding_type _zz_54; + wire `AluCtrlEnum_defaultEncoding_type _zz_55; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56; + reg [31:0] _zz_57; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire writeBack_MEMORY_WR; wire [31:0] writeBack_REGFILE_WRITE_DATA; @@ -683,10 +686,10 @@ module VexRiscv_inner ( reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_56; + wire `BranchCtrlEnum_defaultEncoding_type _zz_58; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_57; - reg [31:0] _zz_58; + reg [31:0] _zz_59; + reg [31:0] _zz_60; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -799,7 +802,7 @@ module VexRiscv_inner ( reg DBusCachedPlugin_exceptionBus_valid; reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_59; + reg _zz_61; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -834,11 +837,11 @@ module VexRiscv_inner ( wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_60; - wire [3:0] _zz_61; - wire _zz_62; - wire _zz_63; + wire [3:0] _zz_62; + wire [3:0] _zz_63; wire _zz_64; + wire _zz_65; + wire _zz_66; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; @@ -875,16 +878,16 @@ module VexRiscv_inner ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_65; - wire _zz_66; wire _zz_67; - wire IBusCachedPlugin_iBusRsp_flush; wire _zz_68; wire _zz_69; - reg _zz_70; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_70; wire _zz_71; reg _zz_72; - reg [31:0] _zz_73; + wire _zz_73; + reg _zz_74; + reg [31:0] _zz_75; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -897,17 +900,17 @@ module VexRiscv_inner ( reg IBusCachedPlugin_injector_nextPcCalc_valids_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_74; - reg [18:0] _zz_75; wire _zz_76; - reg [10:0] _zz_77; + reg [18:0] _zz_77; wire _zz_78; - reg [18:0] _zz_79; - reg _zz_80; - wire _zz_81; - reg [10:0] _zz_82; + reg [10:0] _zz_79; + wire _zz_80; + reg [18:0] _zz_81; + reg _zz_82; wire _zz_83; - reg [18:0] _zz_84; + reg [10:0] _zz_84; + wire _zz_85; + reg [18:0] _zz_86; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -915,7 +918,7 @@ module VexRiscv_inner ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_85; + wire [31:0] _zz_87; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -957,30 +960,30 @@ module VexRiscv_inner ( reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_86; + wire [31:0] _zz_88; reg [31:0] DBusCachedPlugin_rspCounter; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_87; - reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_88; reg [31:0] _zz_89; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; wire _zz_90; reg [31:0] _zz_91; + wire _zz_92; + reg [31:0] _zz_93; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [34:0] _zz_92; - wire _zz_93; - wire _zz_94; + wire [34:0] _zz_94; wire _zz_95; wire _zz_96; wire _zz_97; - wire `Src1CtrlEnum_defaultEncoding_type _zz_98; - wire `AluCtrlEnum_defaultEncoding_type _zz_99; - wire `Src2CtrlEnum_defaultEncoding_type _zz_100; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_101; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_102; - wire `BranchCtrlEnum_defaultEncoding_type _zz_103; - wire `EnvCtrlEnum_defaultEncoding_type _zz_104; - wire `Input2Kind_defaultEncoding_type _zz_105; + wire _zz_98; + wire _zz_99; + wire `Src1CtrlEnum_defaultEncoding_type _zz_100; + wire `AluCtrlEnum_defaultEncoding_type _zz_101; + wire `Src2CtrlEnum_defaultEncoding_type _zz_102; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; + wire `BranchCtrlEnum_defaultEncoding_type _zz_105; + wire `EnvCtrlEnum_defaultEncoding_type _zz_106; + wire `Input2Kind_defaultEncoding_type _zz_107; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -988,57 +991,52 @@ module VexRiscv_inner ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_106; + reg _zz_108; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_107; - reg [31:0] _zz_108; - wire _zz_109; - reg [19:0] _zz_110; + reg [31:0] _zz_109; + reg [31:0] _zz_110; wire _zz_111; reg [19:0] _zz_112; - reg [31:0] _zz_113; + wire _zz_113; + reg [19:0] _zz_114; + reg [31:0] _zz_115; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_114; + reg [31:0] _zz_116; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_115; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_116; - wire _zz_117; - wire _zz_118; - wire _zz_119; - wire _zz_120; - wire _zz_121; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_122; - reg _zz_123; - reg _zz_124; + reg [31:0] _zz_117; + reg _zz_118; + reg _zz_119; + reg _zz_120; + reg [4:0] _zz_121; + reg [31:0] _zz_122; + wire _zz_123; + wire _zz_124; wire _zz_125; - reg [19:0] _zz_126; + wire _zz_126; wire _zz_127; - reg [10:0] _zz_128; - wire _zz_129; - reg [18:0] _zz_130; + wire _zz_128; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_129; + reg _zz_130; reg _zz_131; - wire execute_BranchPlugin_missAlignedTarget; - reg [31:0] execute_BranchPlugin_branch_src1; - reg [31:0] execute_BranchPlugin_branch_src2; wire _zz_132; reg [19:0] _zz_133; wire _zz_134; reg [10:0] _zz_135; wire _zz_136; reg [18:0] _zz_137; + reg _zz_138; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_139; + reg [19:0] _zz_140; + wire _zz_141; + reg [10:0] _zz_142; + wire _zz_143; + reg [18:0] _zz_144; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1060,9 +1058,9 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_138; - wire _zz_139; - wire _zz_140; + wire _zz_145; + wire _zz_146; + wire _zz_147; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1075,10 +1073,10 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_141; - wire _zz_142; - wire [1:0] _zz_143; - wire _zz_144; + wire [1:0] _zz_148; + wire _zz_149; + wire [1:0] _zz_150; + wire _zz_151; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1107,13 +1105,6 @@ module VexRiscv_inner ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_145; - reg [31:0] _zz_146; - reg [31:0] _zz_147; - reg [31:0] _zz_148; - reg [31:0] _zz_149; - reg [31:0] _zz_150; - reg [31:0] _zz_151; reg [31:0] _zz_152; reg [31:0] _zz_153; reg [31:0] _zz_154; @@ -1123,13 +1114,20 @@ module VexRiscv_inner ( reg [31:0] _zz_158; reg [31:0] _zz_159; reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [19:0] execute_CfuPlugin_functionsIds_0; - wire _zz_161; - reg [19:0] _zz_162; - reg [31:0] _zz_163; + wire _zz_168; + reg [19:0] _zz_169; + reg [31:0] _zz_170; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1161,18 +1159,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_164; + wire [31:0] _zz_171; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_165; - wire _zz_166; - wire _zz_167; - reg [32:0] _zz_168; + wire [31:0] _zz_172; + wire _zz_173; + wire _zz_174; + reg [32:0] _zz_175; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_169; - wire [31:0] _zz_170; + reg [31:0] _zz_176; + wire [31:0] _zz_177; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1182,7 +1180,7 @@ module VexRiscv_inner ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_171; + reg _zz_178; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1245,13 +1243,14 @@ module VexRiscv_inner ( reg execute_to_memory_BRANCH_DO; reg [31:0] execute_to_memory_BRANCH_CALC; reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; reg [31:0] execute_to_memory_MUL_LL; reg [33:0] execute_to_memory_MUL_LH; reg [33:0] execute_to_memory_MUL_HL; reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_172; + reg [2:0] _zz_179; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; @@ -1292,13 +1291,6 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; reg [31:0] _zz_180; reg [31:0] _zz_181; reg [31:0] _zz_182; @@ -1323,16 +1315,23 @@ module VexRiscv_inner ( reg [31:0] _zz_201; reg [31:0] _zz_202; reg [31:0] _zz_203; - reg [2:0] _zz_204; - reg _zz_205; - reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_206; - wire _zz_207; - wire _zz_208; - wire _zz_209; - wire _zz_210; - wire _zz_211; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + reg [31:0] _zz_208; + reg [31:0] _zz_209; + reg [31:0] _zz_210; + reg [2:0] _zz_211; reg _zz_212; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + reg _zz_219; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; @@ -1372,45 +1371,45 @@ module VexRiscv_inner ( reg [95:0] _zz_28_string; reg [95:0] _zz_29_string; reg [39:0] execute_CfuPlugin_CFU_ENCODING_string; - reg [39:0] _zz_30_string; + reg [39:0] _zz_32_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_31_string; + reg [39:0] _zz_33_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_32_string; + reg [39:0] _zz_34_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_35_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_34_string; + reg [31:0] _zz_36_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_37_string; + reg [71:0] _zz_39_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_38_string; + reg [71:0] _zz_40_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_40_string; + reg [23:0] _zz_42_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_41_string; + reg [95:0] _zz_43_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_42_string; + reg [63:0] _zz_44_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_43_string; - reg [39:0] _zz_47_string; - reg [39:0] _zz_48_string; - reg [31:0] _zz_49_string; - reg [71:0] _zz_50_string; - reg [39:0] _zz_51_string; - reg [23:0] _zz_52_string; - reg [63:0] _zz_53_string; - reg [95:0] _zz_54_string; + reg [39:0] _zz_45_string; + reg [39:0] _zz_49_string; + reg [39:0] _zz_50_string; + reg [31:0] _zz_51_string; + reg [71:0] _zz_52_string; + reg [39:0] _zz_53_string; + reg [23:0] _zz_54_string; + reg [63:0] _zz_55_string; + reg [95:0] _zz_56_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_56_string; - reg [95:0] _zz_98_string; - reg [63:0] _zz_99_string; - reg [23:0] _zz_100_string; - reg [39:0] _zz_101_string; - reg [71:0] _zz_102_string; - reg [31:0] _zz_103_string; - reg [39:0] _zz_104_string; - reg [39:0] _zz_105_string; + reg [31:0] _zz_58_string; + reg [95:0] _zz_100_string; + reg [63:0] _zz_101_string; + reg [23:0] _zz_102_string; + reg [39:0] _zz_103_string; + reg [71:0] _zz_104_string; + reg [31:0] _zz_105_string; + reg [39:0] _zz_106_string; + reg [39:0] _zz_107_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1426,379 +1425,379 @@ module VexRiscv_inner ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_244 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_245 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_246 = 1'b1; - assign _zz_247 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_248 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_249 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_250 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_251 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_252 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_253 = ((_zz_218 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_254 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_255 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_256 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_257 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_258 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_259 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_260 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_261 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_262 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_263 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_264 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_265 = (1'b0 || (! 1'b1)); - assign _zz_266 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_267 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_268 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_269 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_270 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_271 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_272 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_273 = execute_INSTRUCTION[13 : 12]; - assign _zz_274 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_275 = (! memory_arbitration_isStuck); - assign _zz_276 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_277 = (iBus_cmd_valid || (_zz_204 != 3'b000)); - assign _zz_278 = (_zz_240 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_280 = ((_zz_138 && 1'b1) && (! 1'b0)); - assign _zz_281 = ((_zz_139 && 1'b1) && (! 1'b0)); - assign _zz_282 = ((_zz_140 && 1'b1) && (! 1'b0)); - assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_285 = execute_INSTRUCTION[13]; - assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); - assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); - assign _zz_289 = 52'h0; - assign _zz_290 = {1'b0,memory_MUL_LL}; - assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; - assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; - assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; - assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_297 = _zz_296[31 : 0]; - assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_299 = _zz_92[33 : 33]; - assign _zz_300 = _zz_92[32 : 32]; - assign _zz_301 = _zz_92[31 : 31]; - assign _zz_302 = _zz_92[30 : 30]; - assign _zz_303 = _zz_92[28 : 28]; - assign _zz_304 = _zz_92[25 : 25]; - assign _zz_305 = _zz_92[17 : 17]; - assign _zz_306 = _zz_92[16 : 16]; - assign _zz_307 = _zz_92[13 : 13]; - assign _zz_308 = _zz_92[12 : 12]; - assign _zz_309 = _zz_92[11 : 11]; - assign _zz_310 = _zz_92[34 : 34]; - assign _zz_311 = _zz_92[15 : 15]; - assign _zz_312 = _zz_92[5 : 5]; - assign _zz_313 = _zz_92[3 : 3]; - assign _zz_314 = _zz_92[20 : 20]; - assign _zz_315 = _zz_92[10 : 10]; - assign _zz_316 = _zz_92[4 : 4]; - assign _zz_317 = _zz_92[0 : 0]; - assign _zz_318 = (_zz_60 - 4'b0001); - assign _zz_319 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_320 = {29'd0, _zz_319}; - assign _zz_321 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_322 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_324 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_325 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_326 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_251 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_253 = 1'b1; + assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_256 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_257 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_258 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_259 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_260 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_261 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_262 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_263 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_264 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_265 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_268 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_269 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_270 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_271 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_272 = (1'b0 || (! 1'b1)); + assign _zz_273 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_274 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_275 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_276 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_277 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_278 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_280 = execute_INSTRUCTION[13 : 12]; + assign _zz_281 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_282 = (! memory_arbitration_isStuck); + assign _zz_283 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_284 = (iBus_cmd_valid || (_zz_211 != 3'b000)); + assign _zz_285 = (_zz_247 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_286 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_287 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_288 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_289 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_290 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_291 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_292 = execute_INSTRUCTION[13]; + assign _zz_293 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_294 = ($signed(_zz_295) + $signed(_zz_300)); + assign _zz_295 = ($signed(_zz_296) + $signed(_zz_298)); + assign _zz_296 = 52'h0; + assign _zz_297 = {1'b0,memory_MUL_LL}; + assign _zz_298 = {{19{_zz_297[32]}}, _zz_297}; + assign _zz_299 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; + assign _zz_301 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_302 = {{2{_zz_301[49]}}, _zz_301}; + assign _zz_303 = ($signed(_zz_305) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_304 = _zz_303[31 : 0]; + assign _zz_305 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_306 = _zz_94[33 : 33]; + assign _zz_307 = _zz_94[32 : 32]; + assign _zz_308 = _zz_94[31 : 31]; + assign _zz_309 = _zz_94[30 : 30]; + assign _zz_310 = _zz_94[28 : 28]; + assign _zz_311 = _zz_94[25 : 25]; + assign _zz_312 = _zz_94[17 : 17]; + assign _zz_313 = _zz_94[16 : 16]; + assign _zz_314 = _zz_94[13 : 13]; + assign _zz_315 = _zz_94[12 : 12]; + assign _zz_316 = _zz_94[11 : 11]; + assign _zz_317 = _zz_94[34 : 34]; + assign _zz_318 = _zz_94[15 : 15]; + assign _zz_319 = _zz_94[5 : 5]; + assign _zz_320 = _zz_94[3 : 3]; + assign _zz_321 = _zz_94[20 : 20]; + assign _zz_322 = _zz_94[10 : 10]; + assign _zz_323 = _zz_94[4 : 4]; + assign _zz_324 = _zz_94[0 : 0]; + assign _zz_325 = (_zz_62 - 4'b0001); + assign _zz_326 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_327 = {29'd0, _zz_326}; assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_329 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_330 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_331 = execute_SRC_LESS; - assign _zz_332 = 3'b100; - assign _zz_333 = execute_INSTRUCTION[19 : 15]; - assign _zz_334 = execute_INSTRUCTION[31 : 20]; - assign _zz_335 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_336 = ($signed(_zz_337) + $signed(_zz_340)); - assign _zz_337 = ($signed(_zz_338) + $signed(_zz_339)); - assign _zz_338 = execute_SRC1; - assign _zz_339 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_340 = (execute_SRC_USE_SUB_LESS ? _zz_341 : _zz_342); - assign _zz_341 = 32'h00000001; - assign _zz_342 = 32'h0; - assign _zz_343 = execute_INSTRUCTION[31 : 20]; - assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_345 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_346 = {_zz_126,execute_INSTRUCTION[31 : 20]}; - assign _zz_347 = {{_zz_128,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_348 = {{_zz_130,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_349 = execute_INSTRUCTION[31 : 20]; - assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_352 = 3'b100; - assign _zz_353 = (_zz_141 & (~ _zz_354)); - assign _zz_354 = (_zz_141 - 2'b01); - assign _zz_355 = (_zz_143 & (~ _zz_356)); - assign _zz_356 = (_zz_143 - 2'b01); - assign _zz_357 = execute_INSTRUCTION[31 : 12]; - assign _zz_358 = execute_INSTRUCTION[31 : 20]; - assign _zz_359 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_360 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_361 = writeBack_MUL_LOW[31 : 0]; - assign _zz_362 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_363 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_364 = {5'd0, _zz_363}; - assign _zz_365 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_366 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_367 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_368 = {_zz_164,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_369 = _zz_370; - assign _zz_370 = _zz_371; - assign _zz_371 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_165) : _zz_165)} + _zz_373); - assign _zz_372 = memory_DivPlugin_div_needRevert; - assign _zz_373 = {32'd0, _zz_372}; - assign _zz_374 = _zz_167; - assign _zz_375 = {32'd0, _zz_374}; - assign _zz_376 = _zz_166; - assign _zz_377 = {31'd0, _zz_376}; - assign _zz_378 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_380 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_381 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_382 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_383 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_384 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_385 = (iBus_cmd_payload_address >>> 5); - assign _zz_386 = 1'b1; - assign _zz_387 = 1'b1; - assign _zz_388 = {_zz_64,_zz_63}; - assign _zz_389 = 32'h0000106f; - assign _zz_390 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_391 = 32'h00001073; - assign _zz_392 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_393 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_394 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_395) == 32'h00000003),{(_zz_396 == _zz_397),{_zz_398,{_zz_399,_zz_400}}}}}}; - assign _zz_395 = 32'h0000207f; - assign _zz_396 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_397 = 32'h00000003; - assign _zz_398 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_399 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_400 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_401) == 32'h00005013),{(_zz_402 == _zz_403),{_zz_404,{_zz_405,_zz_406}}}}}}; - assign _zz_401 = 32'hbc00707f; - assign _zz_402 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_403 = 32'h00001013; - assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_405 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_406 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; - assign _zz_407 = decode_INSTRUCTION[31]; - assign _zz_408 = decode_INSTRUCTION[31]; - assign _zz_409 = decode_INSTRUCTION[7]; - assign _zz_410 = 32'h10103050; - assign _zz_411 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_412 = 1'b0; - assign _zz_413 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_414 = 1'b0; - assign _zz_415 = {(_zz_96 != 1'b0),{({_zz_416,_zz_417} != 2'b00),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}; - assign _zz_416 = ((decode_INSTRUCTION & _zz_423) == 32'h10000050); - assign _zz_417 = ((decode_INSTRUCTION & _zz_424) == 32'h00000050); - assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00000050); + assign _zz_329 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_331 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_332 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_333 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_334 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_335 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_338 = execute_SRC_LESS; + assign _zz_339 = 3'b100; + assign _zz_340 = execute_INSTRUCTION[19 : 15]; + assign _zz_341 = execute_INSTRUCTION[31 : 20]; + assign _zz_342 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_343 = ($signed(_zz_344) + $signed(_zz_347)); + assign _zz_344 = ($signed(_zz_345) + $signed(_zz_346)); + assign _zz_345 = execute_SRC1; + assign _zz_346 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_347 = (execute_SRC_USE_SUB_LESS ? _zz_348 : _zz_349); + assign _zz_348 = 32'h00000001; + assign _zz_349 = 32'h0; + assign _zz_350 = execute_INSTRUCTION[31 : 20]; + assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_353 = {_zz_133,execute_INSTRUCTION[31 : 20]}; + assign _zz_354 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_355 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_356 = execute_INSTRUCTION[31 : 20]; + assign _zz_357 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_359 = 3'b100; + assign _zz_360 = (_zz_148 & (~ _zz_361)); + assign _zz_361 = (_zz_148 - 2'b01); + assign _zz_362 = (_zz_150 & (~ _zz_363)); + assign _zz_363 = (_zz_150 - 2'b01); + assign _zz_364 = execute_INSTRUCTION[31 : 12]; + assign _zz_365 = execute_INSTRUCTION[31 : 20]; + assign _zz_366 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_367 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_368 = writeBack_MUL_LOW[31 : 0]; + assign _zz_369 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_370 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_371 = {5'd0, _zz_370}; + assign _zz_372 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_373 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_374 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_375 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_376 = _zz_377; + assign _zz_377 = _zz_378; + assign _zz_378 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_380); + assign _zz_379 = memory_DivPlugin_div_needRevert; + assign _zz_380 = {32'd0, _zz_379}; + assign _zz_381 = _zz_174; + assign _zz_382 = {32'd0, _zz_381}; + assign _zz_383 = _zz_173; + assign _zz_384 = {31'd0, _zz_383}; + assign _zz_385 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_386 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_387 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_388 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_391 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_392 = (iBus_cmd_payload_address >>> 5); + assign _zz_393 = 1'b1; + assign _zz_394 = 1'b1; + assign _zz_395 = {_zz_66,_zz_65}; + assign _zz_396 = 32'h0000106f; + assign _zz_397 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_398 = 32'h00001073; + assign _zz_399 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_400 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_401 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_402) == 32'h00000003),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; + assign _zz_402 = 32'h0000207f; + assign _zz_403 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_404 = 32'h00000003; + assign _zz_405 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_406 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_407 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_408) == 32'h00005013),{(_zz_409 == _zz_410),{_zz_411,{_zz_412,_zz_413}}}}}}; + assign _zz_408 = 32'hbc00707f; + assign _zz_409 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_410 = 32'h00001013; + assign _zz_411 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_412 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_413 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_414 = decode_INSTRUCTION[31]; + assign _zz_415 = decode_INSTRUCTION[31]; + assign _zz_416 = decode_INSTRUCTION[7]; + assign _zz_417 = 32'h10103050; + assign _zz_418 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); assign _zz_419 = 1'b0; - assign _zz_420 = ({_zz_426,_zz_427} != 2'b00); - assign _zz_421 = ({_zz_428,_zz_429} != 2'b00); - assign _zz_422 = {(_zz_430 != _zz_431),{_zz_432,{_zz_433,_zz_434}}}; - assign _zz_423 = 32'h10203050; - assign _zz_424 = 32'h10103050; - assign _zz_425 = 32'h00103050; - assign _zz_426 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_427 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_428 = _zz_95; - assign _zz_429 = ((decode_INSTRUCTION & _zz_435) == 32'h00000004); - assign _zz_430 = ((decode_INSTRUCTION & _zz_436) == 32'h00000040); - assign _zz_431 = 1'b0; - assign _zz_432 = ({_zz_437,_zz_438} != 2'b00); - assign _zz_433 = ({_zz_439,_zz_440} != 3'b000); - assign _zz_434 = {(_zz_441 != _zz_442),{_zz_443,{_zz_444,_zz_445}}}; - assign _zz_435 = 32'h0000001c; - assign _zz_436 = 32'h00000058; - assign _zz_437 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_438 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_439 = ((decode_INSTRUCTION & _zz_446) == 32'h40001010); - assign _zz_440 = {(_zz_447 == _zz_448),(_zz_449 == _zz_450)}; - assign _zz_441 = ((decode_INSTRUCTION & _zz_451) == 32'h00000024); - assign _zz_442 = 1'b0; - assign _zz_443 = ((_zz_452 == _zz_453) != 1'b0); - assign _zz_444 = (_zz_454 != 1'b0); - assign _zz_445 = {(_zz_455 != _zz_456),{_zz_457,{_zz_458,_zz_459}}}; - assign _zz_446 = 32'h40003054; - assign _zz_447 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_448 = 32'h00001010; - assign _zz_449 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_450 = 32'h00001010; - assign _zz_451 = 32'h00000064; - assign _zz_452 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_453 = 32'h00001000; - assign _zz_454 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_455 = {(_zz_460 == _zz_461),(_zz_462 == _zz_463)}; - assign _zz_456 = 2'b00; - assign _zz_457 = ((_zz_464 == _zz_465) != 1'b0); - assign _zz_458 = ({_zz_466,_zz_467} != 3'b000); - assign _zz_459 = {(_zz_468 != _zz_469),{_zz_470,{_zz_471,_zz_472}}}; - assign _zz_460 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_461 = 32'h00002000; - assign _zz_462 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_463 = 32'h00001000; - assign _zz_464 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_465 = 32'h00004004; - assign _zz_466 = _zz_96; - assign _zz_467 = {(_zz_473 == _zz_474),(_zz_475 == _zz_476)}; - assign _zz_468 = {(_zz_477 == _zz_478),{_zz_479,{_zz_480,_zz_481}}}; - assign _zz_469 = 5'h0; - assign _zz_470 = ((_zz_482 == _zz_483) != 1'b0); - assign _zz_471 = ({_zz_484,_zz_485} != 6'h0); - assign _zz_472 = {(_zz_486 != _zz_487),{_zz_488,{_zz_489,_zz_490}}}; - assign _zz_473 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_474 = 32'h00000020; - assign _zz_475 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_476 = 32'h00000020; - assign _zz_477 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_478 = 32'h00002040; - assign _zz_479 = ((decode_INSTRUCTION & _zz_491) == 32'h00001040); - assign _zz_480 = (_zz_492 == _zz_493); - assign _zz_481 = {_zz_494,_zz_495}; - assign _zz_482 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_420 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_421 = 1'b0; + assign _zz_422 = {(_zz_98 != 1'b0),{({_zz_423,_zz_424} != 2'b00),{(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}}}; + assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h10000050); + assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00000050); + assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00000050); + assign _zz_426 = 1'b0; + assign _zz_427 = ({_zz_433,_zz_434} != 2'b00); + assign _zz_428 = ({_zz_435,_zz_436} != 2'b00); + assign _zz_429 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; + assign _zz_430 = 32'h10203050; + assign _zz_431 = 32'h10103050; + assign _zz_432 = 32'h00103050; + assign _zz_433 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_434 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_435 = _zz_97; + assign _zz_436 = ((decode_INSTRUCTION & _zz_442) == 32'h00000004); + assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000040); + assign _zz_438 = 1'b0; + assign _zz_439 = ({_zz_444,_zz_445} != 2'b00); + assign _zz_440 = ({_zz_446,_zz_447} != 3'b000); + assign _zz_441 = {(_zz_448 != _zz_449),{_zz_450,{_zz_451,_zz_452}}}; + assign _zz_442 = 32'h0000001c; + assign _zz_443 = 32'h00000058; + assign _zz_444 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_445 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h40001010); + assign _zz_447 = {(_zz_454 == _zz_455),(_zz_456 == _zz_457)}; + assign _zz_448 = ((decode_INSTRUCTION & _zz_458) == 32'h00000024); + assign _zz_449 = 1'b0; + assign _zz_450 = ((_zz_459 == _zz_460) != 1'b0); + assign _zz_451 = (_zz_461 != 1'b0); + assign _zz_452 = {(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}; + assign _zz_453 = 32'h40003054; + assign _zz_454 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_455 = 32'h00001010; + assign _zz_456 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_457 = 32'h00001010; + assign _zz_458 = 32'h00000064; + assign _zz_459 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_460 = 32'h00001000; + assign _zz_461 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_462 = {(_zz_467 == _zz_468),(_zz_469 == _zz_470)}; + assign _zz_463 = 2'b00; + assign _zz_464 = ((_zz_471 == _zz_472) != 1'b0); + assign _zz_465 = ({_zz_473,_zz_474} != 3'b000); + assign _zz_466 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; + assign _zz_467 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_468 = 32'h00002000; + assign _zz_469 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_470 = 32'h00001000; + assign _zz_471 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_472 = 32'h00004004; + assign _zz_473 = _zz_98; + assign _zz_474 = {(_zz_480 == _zz_481),(_zz_482 == _zz_483)}; + assign _zz_475 = {(_zz_484 == _zz_485),{_zz_486,{_zz_487,_zz_488}}}; + assign _zz_476 = 5'h0; + assign _zz_477 = ((_zz_489 == _zz_490) != 1'b0); + assign _zz_478 = ({_zz_491,_zz_492} != 6'h0); + assign _zz_479 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; + assign _zz_480 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_481 = 32'h00000020; + assign _zz_482 = (decode_INSTRUCTION & 32'h00000064); assign _zz_483 = 32'h00000020; - assign _zz_484 = (_zz_496 == _zz_497); - assign _zz_485 = {_zz_498,{_zz_499,_zz_500}}; - assign _zz_486 = {_zz_94,{_zz_501,_zz_502}}; - assign _zz_487 = 5'h0; - assign _zz_488 = ({_zz_503,_zz_504} != 6'h0); - assign _zz_489 = (_zz_505 != _zz_506); - assign _zz_490 = {_zz_507,{_zz_508,_zz_509}}; - assign _zz_491 = 32'h00001040; - assign _zz_492 = (decode_INSTRUCTION & 32'h00100040); - assign _zz_493 = 32'h00000040; - assign _zz_494 = ((decode_INSTRUCTION & _zz_510) == 32'h00000040); - assign _zz_495 = ((decode_INSTRUCTION & _zz_511) == 32'h0); - assign _zz_496 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_497 = 32'h00000008; - assign _zz_498 = ((decode_INSTRUCTION & _zz_512) == 32'h00000040); - assign _zz_499 = _zz_94; - assign _zz_500 = {_zz_513,{_zz_514,_zz_515}}; - assign _zz_501 = (_zz_516 == _zz_517); - assign _zz_502 = {_zz_518,{_zz_519,_zz_520}}; - assign _zz_503 = _zz_95; - assign _zz_504 = {_zz_521,{_zz_522,_zz_523}}; - assign _zz_505 = {_zz_94,_zz_524}; - assign _zz_506 = 2'b00; - assign _zz_507 = ({_zz_525,_zz_526} != 2'b00); - assign _zz_508 = (_zz_527 != _zz_528); - assign _zz_509 = {_zz_529,{_zz_530,_zz_531}}; - assign _zz_510 = 32'h00000050; - assign _zz_511 = 32'h00000038; - assign _zz_512 = 32'h00000040; - assign _zz_513 = ((decode_INSTRUCTION & _zz_532) == 32'h00004020); - assign _zz_514 = (_zz_533 == _zz_534); - assign _zz_515 = (_zz_535 == _zz_536); - assign _zz_516 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_517 = 32'h00002010; - assign _zz_518 = ((decode_INSTRUCTION & _zz_537) == 32'h00000010); - assign _zz_519 = (_zz_538 == _zz_539); - assign _zz_520 = (_zz_540 == _zz_541); - assign _zz_521 = ((decode_INSTRUCTION & _zz_542) == 32'h00001010); - assign _zz_522 = (_zz_543 == _zz_544); - assign _zz_523 = {_zz_545,{_zz_546,_zz_547}}; - assign _zz_524 = ((decode_INSTRUCTION & _zz_548) == 32'h00000020); - assign _zz_525 = _zz_94; - assign _zz_526 = (_zz_549 == _zz_550); - assign _zz_527 = (_zz_551 == _zz_552); - assign _zz_528 = 1'b0; - assign _zz_529 = (_zz_553 != 1'b0); - assign _zz_530 = (_zz_554 != _zz_555); - assign _zz_531 = {_zz_556,{_zz_557,_zz_558}}; - assign _zz_532 = 32'h00004020; - assign _zz_533 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_534 = 32'h00000010; - assign _zz_535 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_536 = 32'h00000020; - assign _zz_537 = 32'h00001030; - assign _zz_538 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_539 = 32'h00002020; - assign _zz_540 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_541 = 32'h00000020; - assign _zz_542 = 32'h00001010; - assign _zz_543 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_544 = 32'h00002010; - assign _zz_545 = ((decode_INSTRUCTION & _zz_559) == 32'h00000010); - assign _zz_546 = (_zz_560 == _zz_561); - assign _zz_547 = (_zz_562 == _zz_563); - assign _zz_548 = 32'h00000070; - assign _zz_549 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_550 = 32'h0; - assign _zz_551 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_552 = 32'h00004010; - assign _zz_553 = ((decode_INSTRUCTION & _zz_564) == 32'h00002010); - assign _zz_554 = {_zz_565,{_zz_566,_zz_567}}; - assign _zz_555 = 4'b0000; - assign _zz_556 = (_zz_568 != 1'b0); - assign _zz_557 = (_zz_569 != _zz_570); - assign _zz_558 = {_zz_571,{_zz_572,_zz_573}}; - assign _zz_559 = 32'h00000050; - assign _zz_560 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_561 = 32'h00000004; - assign _zz_562 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_563 = 32'h0; - assign _zz_564 = 32'h00006014; - assign _zz_565 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_566 = ((decode_INSTRUCTION & _zz_574) == 32'h0); - assign _zz_567 = {(_zz_575 == _zz_576),(_zz_577 == _zz_578)}; - assign _zz_568 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_569 = {(_zz_579 == _zz_580),{_zz_581,_zz_582}}; - assign _zz_570 = 3'b000; - assign _zz_571 = ({_zz_583,_zz_93} != 2'b00); - assign _zz_572 = ({_zz_584,_zz_585} != 2'b00); - assign _zz_573 = (_zz_586 != 1'b0); - assign _zz_574 = 32'h00000018; - assign _zz_575 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_576 = 32'h00002000; - assign _zz_577 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_578 = 32'h00001000; - assign _zz_579 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_580 = 32'h00000040; - assign _zz_581 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_582 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_583 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_584 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_585 = _zz_93; - assign _zz_586 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); - assign _zz_587 = execute_INSTRUCTION[31]; - assign _zz_588 = execute_INSTRUCTION[31]; - assign _zz_589 = execute_INSTRUCTION[7]; - assign _zz_590 = 32'h0; + assign _zz_484 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_485 = 32'h00002040; + assign _zz_486 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); + assign _zz_487 = (_zz_499 == _zz_500); + assign _zz_488 = {_zz_501,_zz_502}; + assign _zz_489 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_490 = 32'h00000020; + assign _zz_491 = (_zz_503 == _zz_504); + assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; + assign _zz_493 = {_zz_96,{_zz_508,_zz_509}}; + assign _zz_494 = 5'h0; + assign _zz_495 = ({_zz_510,_zz_511} != 6'h0); + assign _zz_496 = (_zz_512 != _zz_513); + assign _zz_497 = {_zz_514,{_zz_515,_zz_516}}; + assign _zz_498 = 32'h00001040; + assign _zz_499 = (decode_INSTRUCTION & 32'h00100040); + assign _zz_500 = 32'h00000040; + assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00000040); + assign _zz_502 = ((decode_INSTRUCTION & _zz_518) == 32'h0); + assign _zz_503 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_504 = 32'h00000008; + assign _zz_505 = ((decode_INSTRUCTION & _zz_519) == 32'h00000040); + assign _zz_506 = _zz_96; + assign _zz_507 = {_zz_520,{_zz_521,_zz_522}}; + assign _zz_508 = (_zz_523 == _zz_524); + assign _zz_509 = {_zz_525,{_zz_526,_zz_527}}; + assign _zz_510 = _zz_97; + assign _zz_511 = {_zz_528,{_zz_529,_zz_530}}; + assign _zz_512 = {_zz_96,_zz_531}; + assign _zz_513 = 2'b00; + assign _zz_514 = ({_zz_532,_zz_533} != 2'b00); + assign _zz_515 = (_zz_534 != _zz_535); + assign _zz_516 = {_zz_536,{_zz_537,_zz_538}}; + assign _zz_517 = 32'h00000050; + assign _zz_518 = 32'h00000038; + assign _zz_519 = 32'h00000040; + assign _zz_520 = ((decode_INSTRUCTION & _zz_539) == 32'h00004020); + assign _zz_521 = (_zz_540 == _zz_541); + assign _zz_522 = (_zz_542 == _zz_543); + assign _zz_523 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_524 = 32'h00002010; + assign _zz_525 = ((decode_INSTRUCTION & _zz_544) == 32'h00000010); + assign _zz_526 = (_zz_545 == _zz_546); + assign _zz_527 = (_zz_547 == _zz_548); + assign _zz_528 = ((decode_INSTRUCTION & _zz_549) == 32'h00001010); + assign _zz_529 = (_zz_550 == _zz_551); + assign _zz_530 = {_zz_552,{_zz_553,_zz_554}}; + assign _zz_531 = ((decode_INSTRUCTION & _zz_555) == 32'h00000020); + assign _zz_532 = _zz_96; + assign _zz_533 = (_zz_556 == _zz_557); + assign _zz_534 = (_zz_558 == _zz_559); + assign _zz_535 = 1'b0; + assign _zz_536 = (_zz_560 != 1'b0); + assign _zz_537 = (_zz_561 != _zz_562); + assign _zz_538 = {_zz_563,{_zz_564,_zz_565}}; + assign _zz_539 = 32'h00004020; + assign _zz_540 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_541 = 32'h00000010; + assign _zz_542 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_543 = 32'h00000020; + assign _zz_544 = 32'h00001030; + assign _zz_545 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_546 = 32'h00002020; + assign _zz_547 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_548 = 32'h00000020; + assign _zz_549 = 32'h00001010; + assign _zz_550 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_551 = 32'h00002010; + assign _zz_552 = ((decode_INSTRUCTION & _zz_566) == 32'h00000010); + assign _zz_553 = (_zz_567 == _zz_568); + assign _zz_554 = (_zz_569 == _zz_570); + assign _zz_555 = 32'h00000070; + assign _zz_556 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_557 = 32'h0; + assign _zz_558 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_559 = 32'h00004010; + assign _zz_560 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); + assign _zz_561 = {_zz_572,{_zz_573,_zz_574}}; + assign _zz_562 = 4'b0000; + assign _zz_563 = (_zz_575 != 1'b0); + assign _zz_564 = (_zz_576 != _zz_577); + assign _zz_565 = {_zz_578,{_zz_579,_zz_580}}; + assign _zz_566 = 32'h00000050; + assign _zz_567 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_568 = 32'h00000004; + assign _zz_569 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_570 = 32'h0; + assign _zz_571 = 32'h00006014; + assign _zz_572 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_573 = ((decode_INSTRUCTION & _zz_581) == 32'h0); + assign _zz_574 = {(_zz_582 == _zz_583),(_zz_584 == _zz_585)}; + assign _zz_575 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_576 = {(_zz_586 == _zz_587),{_zz_588,_zz_589}}; + assign _zz_577 = 3'b000; + assign _zz_578 = ({_zz_590,_zz_95} != 2'b00); + assign _zz_579 = ({_zz_591,_zz_592} != 2'b00); + assign _zz_580 = (_zz_593 != 1'b0); + assign _zz_581 = 32'h00000018; + assign _zz_582 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_583 = 32'h00002000; + assign _zz_584 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_585 = 32'h00001000; + assign _zz_586 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_587 = 32'h00000040; + assign _zz_588 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_589 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_590 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_591 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_592 = _zz_95; + assign _zz_593 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_594 = execute_INSTRUCTION[31]; + assign _zz_595 = execute_INSTRUCTION[31]; + assign _zz_596 = execute_INSTRUCTION[7]; + assign _zz_597 = 32'h0; always @ (posedge clk) begin - if(_zz_386) begin - _zz_241 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_393) begin + _zz_248 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_387) begin - _zz_242 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_394) begin + _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_46) begin + if(_zz_48) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_213 ), //i - .io_cpu_prefetch_isValid (_zz_214 ), //i + .io_flush (_zz_220 ), //i + .io_cpu_prefetch_isValid (_zz_221 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_215 ), //i - .io_cpu_fetch_isStuck (_zz_216 ), //i - .io_cpu_fetch_isRemoved (_zz_217 ), //i + .io_cpu_fetch_isValid (_zz_222 ), //i + .io_cpu_fetch_isStuck (_zz_223 ), //i + .io_cpu_fetch_isRemoved (_zz_224 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1811,8 +1810,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_218 ), //i - .io_cpu_decode_isStuck (_zz_219 ), //i + .io_cpu_decode_isValid (_zz_225 ), //i + .io_cpu_decode_isStuck (_zz_226 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1820,8 +1819,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_220 ), //i - .io_cpu_fill_valid (_zz_221 ), //i + .io_cpu_decode_isUser (_zz_227 ), //i + .io_cpu_fill_valid (_zz_228 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1830,26 +1829,26 @@ module VexRiscv_inner ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_16 (_zz_172[2:0] ), //i + ._zz_16 (_zz_179[2:0] ), //i ._zz_17 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_222 ), //i - .io_cpu_execute_address (_zz_223[31:0] ), //i + .io_cpu_execute_isValid (_zz_229 ), //i + .io_cpu_execute_address (_zz_230[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_87[31:0] ), //i + .io_cpu_execute_args_data (_zz_89[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_224 ), //i + .io_cpu_memory_isValid (_zz_231 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_225[31:0] ), //i + .io_cpu_memory_address (_zz_232[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_226 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_233 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1857,31 +1856,31 @@ module VexRiscv_inner ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_227 ), //i + .io_cpu_writeBack_isValid (_zz_234 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_228 ), //i + .io_cpu_writeBack_isUser (_zz_235 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_229[31:0] ), //i + .io_cpu_writeBack_address (_zz_236[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_230 ), //i - .io_cpu_writeBack_fence_SR (_zz_231 ), //i - .io_cpu_writeBack_fence_SO (_zz_232 ), //i - .io_cpu_writeBack_fence_SI (_zz_233 ), //i - .io_cpu_writeBack_fence_PW (_zz_234 ), //i - .io_cpu_writeBack_fence_PR (_zz_235 ), //i - .io_cpu_writeBack_fence_PO (_zz_236 ), //i - .io_cpu_writeBack_fence_PI (_zz_237 ), //i - .io_cpu_writeBack_fence_FM (_zz_238[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_237 ), //i + .io_cpu_writeBack_fence_SR (_zz_238 ), //i + .io_cpu_writeBack_fence_SO (_zz_239 ), //i + .io_cpu_writeBack_fence_SI (_zz_240 ), //i + .io_cpu_writeBack_fence_PW (_zz_241 ), //i + .io_cpu_writeBack_fence_PR (_zz_242 ), //i + .io_cpu_writeBack_fence_PO (_zz_243 ), //i + .io_cpu_writeBack_fence_PI (_zz_244 ), //i + .io_cpu_writeBack_fence_FM (_zz_245[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_239 ), //i + .io_cpu_flush_valid (_zz_246 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_240 ), //i + .io_mem_cmd_ready (_zz_247 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1897,18 +1896,18 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_388) + case(_zz_395) 2'b00 : begin - _zz_243 = DBusCachedPlugin_redoBranch_payload; + _zz_250 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_243 = CsrPlugin_jumpInterface_payload; + _zz_250 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_243 = BranchPlugin_jumpInterface_payload; + _zz_250 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_243 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_250 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2230,10 +2229,10 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_30) - `Input2Kind_defaultEncoding_RS : _zz_30_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_30_string = "IMM_I"; - default : _zz_30_string = "?????"; + case(_zz_32) + `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; + default : _zz_32_string = "?????"; endcase end always @(*) begin @@ -2246,12 +2245,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_31) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_31_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_31_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_31_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_31_string = "ECALL"; - default : _zz_31_string = "?????"; + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; endcase end always @(*) begin @@ -2264,12 +2263,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_32) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_32_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_32_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_32_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_32_string = "ECALL"; - default : _zz_32_string = "?????"; + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; endcase end always @(*) begin @@ -2282,12 +2281,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; endcase end always @(*) begin @@ -2300,12 +2299,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_34) - `BranchCtrlEnum_defaultEncoding_INC : _zz_34_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_34_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_34_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_34_string = "JALR"; - default : _zz_34_string = "????"; + case(_zz_36) + `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; + default : _zz_36_string = "????"; endcase end always @(*) begin @@ -2318,12 +2317,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_37) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_37_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_37_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_37_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_37_string = "SRA_1 "; - default : _zz_37_string = "?????????"; + case(_zz_39) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; + default : _zz_39_string = "?????????"; endcase end always @(*) begin @@ -2336,12 +2335,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_38) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38_string = "SRA_1 "; - default : _zz_38_string = "?????????"; + case(_zz_40) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; + default : _zz_40_string = "?????????"; endcase end always @(*) begin @@ -2354,12 +2353,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_40) - `Src2CtrlEnum_defaultEncoding_RS : _zz_40_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_40_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_40_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_40_string = "PC "; - default : _zz_40_string = "???"; + case(_zz_42) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; + default : _zz_42_string = "???"; endcase end always @(*) begin @@ -2372,12 +2371,12 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_41) - `Src1CtrlEnum_defaultEncoding_RS : _zz_41_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_41_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_41_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_41_string = "URS1 "; - default : _zz_41_string = "????????????"; + case(_zz_43) + `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; + default : _zz_43_string = "????????????"; endcase end always @(*) begin @@ -2389,11 +2388,11 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_42) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_42_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_42_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_42_string = "BITWISE "; - default : _zz_42_string = "????????"; + case(_zz_44) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; + default : _zz_44_string = "????????"; endcase end always @(*) begin @@ -2405,165 +2404,165 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(_zz_43) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; - default : _zz_43_string = "?????"; - endcase - end - always @(*) begin - case(_zz_47) - `Input2Kind_defaultEncoding_RS : _zz_47_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_47_string = "IMM_I"; - default : _zz_47_string = "?????"; - endcase - end - always @(*) begin - case(_zz_48) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_48_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_48_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_48_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_48_string = "ECALL"; - default : _zz_48_string = "?????"; + case(_zz_45) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; + default : _zz_45_string = "?????"; endcase end always @(*) begin case(_zz_49) - `BranchCtrlEnum_defaultEncoding_INC : _zz_49_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_49_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_49_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_49_string = "JALR"; - default : _zz_49_string = "????"; + `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; + default : _zz_49_string = "?????"; endcase end always @(*) begin case(_zz_50) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_50_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_50_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_50_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_50_string = "SRA_1 "; - default : _zz_50_string = "?????????"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; + default : _zz_50_string = "?????"; endcase end always @(*) begin case(_zz_51) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_51_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_51_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_51_string = "AND_1"; - default : _zz_51_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; endcase end always @(*) begin case(_zz_52) - `Src2CtrlEnum_defaultEncoding_RS : _zz_52_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_52_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_52_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_52_string = "PC "; - default : _zz_52_string = "???"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; + default : _zz_52_string = "?????????"; endcase end always @(*) begin case(_zz_53) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_53_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_53_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_53_string = "BITWISE "; - default : _zz_53_string = "????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; + default : _zz_53_string = "?????"; endcase end always @(*) begin case(_zz_54) - `Src1CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_54_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54_string = "URS1 "; - default : _zz_54_string = "????????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; + default : _zz_54_string = "???"; endcase end always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; + case(_zz_55) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; + default : _zz_55_string = "????????"; endcase end always @(*) begin case(_zz_56) - `BranchCtrlEnum_defaultEncoding_INC : _zz_56_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_56_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_56_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_56_string = "JALR"; - default : _zz_56_string = "????"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; + default : _zz_56_string = "????????????"; endcase end always @(*) begin - case(_zz_98) - `Src1CtrlEnum_defaultEncoding_RS : _zz_98_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_98_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_98_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_98_string = "URS1 "; - default : _zz_98_string = "????????????"; + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_99) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_99_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_99_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_99_string = "BITWISE "; - default : _zz_99_string = "????????"; + case(_zz_58) + `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; + default : _zz_58_string = "????"; endcase end always @(*) begin case(_zz_100) - `Src2CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_100_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_100_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_100_string = "PC "; - default : _zz_100_string = "???"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; + default : _zz_100_string = "????????????"; endcase end always @(*) begin case(_zz_101) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_101_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_101_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_101_string = "AND_1"; - default : _zz_101_string = "?????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; + default : _zz_101_string = "????????"; endcase end always @(*) begin case(_zz_102) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_102_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_102_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_102_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_102_string = "SRA_1 "; - default : _zz_102_string = "?????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; + default : _zz_102_string = "???"; endcase end always @(*) begin case(_zz_103) - `BranchCtrlEnum_defaultEncoding_INC : _zz_103_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_103_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_103_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_103_string = "JALR"; - default : _zz_103_string = "????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; + default : _zz_103_string = "?????"; endcase end always @(*) begin case(_zz_104) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_104_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_104_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_104_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_104_string = "ECALL"; - default : _zz_104_string = "?????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; + default : _zz_104_string = "?????????"; endcase end always @(*) begin case(_zz_105) - `Input2Kind_defaultEncoding_RS : _zz_105_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_105_string = "IMM_I"; - default : _zz_105_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; + default : _zz_105_string = "????"; + endcase + end + always @(*) begin + case(_zz_106) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; + default : _zz_106_string = "?????"; + endcase + end + always @(*) begin + case(_zz_107) + `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; + default : _zz_107_string = "?????"; endcase end always @(*) begin @@ -2663,51 +2662,52 @@ module VexRiscv_inner ( end `endif - assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); + assign memory_MUL_LOW = ($signed(_zz_294) + $signed(_zz_302)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_297; - assign execute_REGFILE_WRITE_DATA = _zz_107; + assign execute_SHIFT_RIGHT = _zz_304; + assign execute_REGFILE_WRITE_DATA = _zz_109; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_223[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_230[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_299[0]; - assign decode_IS_RS1_SIGNED = _zz_300[0]; - assign decode_IS_DIV = _zz_301[0]; + assign decode_IS_RS2_SIGNED = _zz_306[0]; + assign decode_IS_RS1_SIGNED = _zz_307[0]; + assign decode_IS_DIV = _zz_308[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_302[0]; + assign decode_IS_MUL = _zz_309[0]; assign decode_CfuPlugin_CFU_ENCODING = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_310[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_304[0]; + assign decode_IS_CSR = _zz_311[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; - assign decode_MEMORY_MANAGMENT = _zz_306[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_312[0]; + assign decode_MEMORY_MANAGMENT = _zz_313[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_307[0]; + assign decode_MEMORY_WR = _zz_314[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_315[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_316[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2721,7 +2721,7 @@ module VexRiscv_inner ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_310[0]; + assign decode_IS_EBREAK = _zz_317[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2732,28 +2732,42 @@ module VexRiscv_inner ( assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; + always @ (*) begin + _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck)begin + _zz_30 = 1'b0; + end + end + + always @ (*) begin + _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck)begin + _zz_31 = 1'b0; + end + end + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_ENCODING = _zz_30; + assign execute_CfuPlugin_CFU_ENCODING = _zz_32; assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_31; - assign execute_ENV_CTRL = _zz_32; - assign writeBack_ENV_CTRL = _zz_33; + assign memory_ENV_CTRL = _zz_33; + assign execute_ENV_CTRL = _zz_34; + assign writeBack_ENV_CTRL = _zz_35; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_124; - assign execute_BRANCH_CTRL = _zz_34; - assign decode_RS2_USE = _zz_311[0]; - assign decode_RS1_USE = _zz_312[0]; + assign execute_BRANCH_COND_RESULT = _zz_131; + assign execute_BRANCH_CTRL = _zz_36; + assign decode_RS2_USE = _zz_318[0]; + assign decode_RS1_USE = _zz_319[0]; always @ (*) begin - _zz_35 = execute_REGFILE_WRITE_DATA; - if(_zz_244)begin - _zz_35 = execute_CsrPlugin_readData; + _zz_37 = execute_REGFILE_WRITE_DATA; + if(_zz_251)begin + _zz_37 = execute_CsrPlugin_readData; end end @@ -2765,29 +2779,29 @@ module VexRiscv_inner ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_122; end end - if(_zz_245)begin - if(_zz_246)begin - if(_zz_117)begin - decode_RS2 = _zz_55; + if(_zz_252)begin + if(_zz_253)begin + if(_zz_124)begin + decode_RS2 = _zz_57; end end end - if(_zz_247)begin + if(_zz_254)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_119)begin - decode_RS2 = _zz_36; + if(_zz_126)begin + decode_RS2 = _zz_38; end end end - if(_zz_248)begin + if(_zz_255)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_121)begin - decode_RS2 = _zz_35; + if(_zz_128)begin + decode_RS2 = _zz_37; end end end @@ -2795,29 +2809,29 @@ module VexRiscv_inner ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_122; end end - if(_zz_245)begin - if(_zz_246)begin - if(_zz_116)begin - decode_RS1 = _zz_55; + if(_zz_252)begin + if(_zz_253)begin + if(_zz_123)begin + decode_RS1 = _zz_57; end end end - if(_zz_247)begin + if(_zz_254)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_118)begin - decode_RS1 = _zz_36; + if(_zz_125)begin + decode_RS1 = _zz_38; end end end - if(_zz_248)begin + if(_zz_255)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_120)begin - decode_RS1 = _zz_35; + if(_zz_127)begin + decode_RS1 = _zz_37; end end end @@ -2825,73 +2839,73 @@ module VexRiscv_inner ( assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_36 = memory_REGFILE_WRITE_DATA; + _zz_38 = memory_REGFILE_WRITE_DATA; if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_36 = _zz_115; + _zz_38 = _zz_117; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_36 = memory_SHIFT_RIGHT; + _zz_38 = memory_SHIFT_RIGHT; end default : begin end endcase end if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_36 = memory_CfuPlugin_rsp_payload_outputs_0; + _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_249)begin - _zz_36 = memory_DivPlugin_div_result; + if(_zz_256)begin + _zz_38 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_37; - assign execute_SHIFT_CTRL = _zz_38; + assign memory_SHIFT_CTRL = _zz_39; + assign execute_SHIFT_CTRL = _zz_40; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_39 = execute_PC; - assign execute_SRC2_CTRL = _zz_40; - assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_313[0]; - assign decode_SRC_ADD_ZERO = _zz_314[0]; + assign _zz_41 = execute_PC; + assign execute_SRC2_CTRL = _zz_42; + assign execute_SRC1_CTRL = _zz_43; + assign decode_SRC_USE_SUB_LESS = _zz_320[0]; + assign decode_SRC_ADD_ZERO = _zz_321[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_42; - assign execute_SRC2 = _zz_113; - assign execute_SRC1 = _zz_108; - assign execute_ALU_BITWISE_CTRL = _zz_43; - assign _zz_44 = writeBack_INSTRUCTION; - assign _zz_45 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_46 = 1'b0; + assign execute_ALU_CTRL = _zz_44; + assign execute_SRC2 = _zz_115; + assign execute_SRC1 = _zz_110; + assign execute_ALU_BITWISE_CTRL = _zz_45; + assign _zz_46 = writeBack_INSTRUCTION; + assign _zz_47 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_48 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_46 = 1'b1; + _zz_48 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_315[0]; + decode_REGFILE_WRITE_VALID = _zz_322[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_389) == 32'h00000003),{(_zz_390 == _zz_391),{_zz_392,{_zz_393,_zz_394}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}} != 22'h0); always @ (*) begin - _zz_55 = writeBack_REGFILE_WRITE_DATA; + _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_55 = writeBack_DBusCachedPlugin_rspFormated; + _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_286) + case(_zz_293) 2'b00 : begin - _zz_55 = _zz_361; + _zz_57 = _zz_368; end default : begin - _zz_55 = _zz_362; + _zz_57 = _zz_369; end endcase end @@ -2910,49 +2924,49 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_316[0]; - assign decode_FLUSH_ALL = _zz_317[0]; + assign decode_MEMORY_ENABLE = _zz_323[0]; + assign decode_FLUSH_ALL = _zz_324[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_250)begin + if(_zz_257)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_251)begin + if(_zz_258)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_252)begin + if(_zz_259)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_253)begin + if(_zz_260)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_56; + assign decode_BRANCH_CTRL = _zz_58; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_57 = memory_FORMAL_PC_NEXT; + _zz_59 = memory_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin - _zz_57 = BranchPlugin_jumpInterface_payload; + _zz_59 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_58 = decode_FORMAL_PC_NEXT; + _zz_60 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_58 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; end end @@ -2964,7 +2978,7 @@ module VexRiscv_inner ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_172) + case(_zz_179) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2975,7 +2989,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2988,7 +3002,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_254)begin + if(_zz_261)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3002,22 +3016,22 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_254)begin + if(_zz_261)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_239 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_246 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_255)begin + if(_zz_262)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_244)begin + if(_zz_251)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3032,7 +3046,7 @@ module VexRiscv_inner ( if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_256)begin + if(_zz_263)begin execute_arbitration_haltByOther = 1'b1; end end @@ -3049,8 +3063,8 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_256)begin - if(_zz_257)begin + if(_zz_263)begin + if(_zz_264)begin execute_arbitration_flushIt = 1'b1; end end @@ -3061,8 +3075,8 @@ module VexRiscv_inner ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_256)begin - if(_zz_257)begin + if(_zz_263)begin + if(_zz_264)begin execute_arbitration_flushNext = 1'b1; end end @@ -3075,7 +3089,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_249)begin + if(_zz_256)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3085,7 +3099,7 @@ module VexRiscv_inner ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_258)begin + if(_zz_265)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3099,7 +3113,7 @@ module VexRiscv_inner ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_258)begin + if(_zz_265)begin memory_arbitration_flushNext = 1'b1; end end @@ -3137,10 +3151,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_259)begin + if(_zz_266)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_260)begin + if(_zz_267)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3154,21 +3168,21 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_259)begin + if(_zz_266)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_260)begin + if(_zz_267)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_256)begin - if(_zz_257)begin + if(_zz_263)begin + if(_zz_264)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_261)begin + if(_zz_268)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3181,15 +3195,15 @@ module VexRiscv_inner ( end always @ (*) begin - _zz_59 = 1'b0; + _zz_61 = 1'b0; if(DebugPlugin_godmode)begin - _zz_59 = 1'b1; + _zz_61 = 1'b1; end end always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_255)begin + if(_zz_262)begin CsrPlugin_inWfi = 1'b1; end end @@ -3203,21 +3217,21 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_259)begin + if(_zz_266)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_260)begin + if(_zz_267)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_259)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_266)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_260)begin - case(_zz_262) + if(_zz_267)begin + case(_zz_269) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3250,12 +3264,12 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_60 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_61 = (_zz_60 & (~ _zz_318)); - assign _zz_62 = _zz_61[3]; - assign _zz_63 = (_zz_61[1] || _zz_62); - assign _zz_64 = (_zz_61[2] || _zz_62); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_243; + assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_63 = (_zz_62 & (~ _zz_325)); + assign _zz_64 = _zz_63[3]; + assign _zz_65 = (_zz_63[1] || _zz_64); + assign _zz_66 = (_zz_63[2] || _zz_64); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_250; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3275,7 +3289,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_320); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_327); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3315,9 +3329,9 @@ module VexRiscv_inner ( end end - assign _zz_65 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_65); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_65); + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_67); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; @@ -3326,9 +3340,9 @@ module VexRiscv_inner ( end end - assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_66); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_66); + assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_68); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; @@ -3337,22 +3351,22 @@ module VexRiscv_inner ( end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_67); + assign _zz_69 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_69); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_69); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_68; - assign _zz_68 = ((1'b0 && (! _zz_69)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_69 = _zz_70; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_69; - assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_70; + assign _zz_70 = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign _zz_71 = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_71; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_73; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_73)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_73 = _zz_74; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_73; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_75; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -3367,7 +3381,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_172) + case(_zz_179) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3379,38 +3393,16 @@ module VexRiscv_inner ( endcase end - assign _zz_74 = _zz_321[11]; - always @ (*) begin - _zz_75[18] = _zz_74; - _zz_75[17] = _zz_74; - _zz_75[16] = _zz_74; - _zz_75[15] = _zz_74; - _zz_75[14] = _zz_74; - _zz_75[13] = _zz_74; - _zz_75[12] = _zz_74; - _zz_75[11] = _zz_74; - _zz_75[10] = _zz_74; - _zz_75[9] = _zz_74; - _zz_75[8] = _zz_74; - _zz_75[7] = _zz_74; - _zz_75[6] = _zz_74; - _zz_75[5] = _zz_74; - _zz_75[4] = _zz_74; - _zz_75[3] = _zz_74; - _zz_75[2] = _zz_74; - _zz_75[1] = _zz_74; - _zz_75[0] = _zz_74; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_322[31])); - if(_zz_80)begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; - end - end - - assign _zz_76 = _zz_323[19]; + assign _zz_76 = _zz_328[11]; always @ (*) begin + _zz_77[18] = _zz_76; + _zz_77[17] = _zz_76; + _zz_77[16] = _zz_76; + _zz_77[15] = _zz_76; + _zz_77[14] = _zz_76; + _zz_77[13] = _zz_76; + _zz_77[12] = _zz_76; + _zz_77[11] = _zz_76; _zz_77[10] = _zz_76; _zz_77[9] = _zz_76; _zz_77[8] = _zz_76; @@ -3424,16 +3416,15 @@ module VexRiscv_inner ( _zz_77[0] = _zz_76; end - assign _zz_78 = _zz_324[11]; always @ (*) begin - _zz_79[18] = _zz_78; - _zz_79[17] = _zz_78; - _zz_79[16] = _zz_78; - _zz_79[15] = _zz_78; - _zz_79[14] = _zz_78; - _zz_79[13] = _zz_78; - _zz_79[12] = _zz_78; - _zz_79[11] = _zz_78; + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_329[31])); + if(_zz_82)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_78 = _zz_330[19]; + always @ (*) begin _zz_79[10] = _zz_78; _zz_79[9] = _zz_78; _zz_79[8] = _zz_78; @@ -3447,43 +3438,43 @@ module VexRiscv_inner ( _zz_79[0] = _zz_78; end + assign _zz_80 = _zz_331[11]; + always @ (*) begin + _zz_81[18] = _zz_80; + _zz_81[17] = _zz_80; + _zz_81[16] = _zz_80; + _zz_81[15] = _zz_80; + _zz_81[14] = _zz_80; + _zz_81[13] = _zz_80; + _zz_81[12] = _zz_80; + _zz_81[11] = _zz_80; + _zz_81[10] = _zz_80; + _zz_81[9] = _zz_80; + _zz_81[8] = _zz_80; + _zz_81[7] = _zz_80; + _zz_81[6] = _zz_80; + _zz_81[5] = _zz_80; + _zz_81[4] = _zz_80; + _zz_81[3] = _zz_80; + _zz_81[2] = _zz_80; + _zz_81[1] = _zz_80; + _zz_81[0] = _zz_80; + end + always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_80 = _zz_325[1]; + _zz_82 = _zz_332[1]; end default : begin - _zz_80 = _zz_326[1]; + _zz_82 = _zz_333[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_81 = _zz_327[19]; - always @ (*) begin - _zz_82[10] = _zz_81; - _zz_82[9] = _zz_81; - _zz_82[8] = _zz_81; - _zz_82[7] = _zz_81; - _zz_82[6] = _zz_81; - _zz_82[5] = _zz_81; - _zz_82[4] = _zz_81; - _zz_82[3] = _zz_81; - _zz_82[2] = _zz_81; - _zz_82[1] = _zz_81; - _zz_82[0] = _zz_81; - end - - assign _zz_83 = _zz_328[11]; - always @ (*) begin - _zz_84[18] = _zz_83; - _zz_84[17] = _zz_83; - _zz_84[16] = _zz_83; - _zz_84[15] = _zz_83; - _zz_84[14] = _zz_83; - _zz_84[13] = _zz_83; - _zz_84[12] = _zz_83; - _zz_84[11] = _zz_83; + assign _zz_83 = _zz_334[19]; + always @ (*) begin _zz_84[10] = _zz_83; _zz_84[9] = _zz_83; _zz_84[8] = _zz_83; @@ -3497,7 +3488,30 @@ module VexRiscv_inner ( _zz_84[0] = _zz_83; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_82,{{{_zz_407,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_84,{{{_zz_408,_zz_409},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_85 = _zz_335[11]; + always @ (*) begin + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7] = _zz_85; + _zz_86[6] = _zz_85; + _zz_86[5] = _zz_85; + _zz_86[4] = _zz_85; + _zz_86[3] = _zz_85; + _zz_86[2] = _zz_85; + _zz_86[1] = _zz_85; + _zz_86[0] = _zz_85; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_414,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_415,_zz_416},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3506,52 +3520,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_214 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_215 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_216 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_215; + assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_222; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_219 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_220 = (CsrPlugin_privilege == 2'b00); + assign _zz_225 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_226 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_227 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_253)begin + if(_zz_260)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_251)begin + if(_zz_258)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_221 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_251)begin - _zz_221 = 1'b1; + _zz_228 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_258)begin + _zz_228 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_252)begin + if(_zz_259)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_250)begin + if(_zz_257)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_252)begin + if(_zz_259)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_250)begin + if(_zz_257)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3561,9 +3575,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_213 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_220 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_240 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_247 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3590,43 +3604,43 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_222 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_223 = execute_SRC_ADD; + assign _zz_229 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_230 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_87 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_87 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_89 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_87 = execute_RS2[31 : 0]; + _zz_89 = execute_RS2[31 : 0]; end endcase end - assign _zz_239 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_224 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_225 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_224; + assign _zz_246 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_231 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_232 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_231; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_225; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_232; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_226 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_59 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_226 = 1'b1; + _zz_233 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_233 = 1'b1; end end - assign _zz_227 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_228 = (CsrPlugin_privilege == 2'b00); - assign _zz_229 = writeBack_REGFILE_WRITE_DATA; + assign _zz_234 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_235 = (CsrPlugin_privilege == 2'b00); + assign _zz_236 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_263)begin + if(_zz_270)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3636,7 +3650,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_263)begin + if(_zz_270)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3655,15 +3669,15 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_263)begin + if(_zz_270)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_330}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; end end end @@ -3685,36 +3699,7 @@ module VexRiscv_inner ( endcase end - assign _zz_88 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_89[31] = _zz_88; - _zz_89[30] = _zz_88; - _zz_89[29] = _zz_88; - _zz_89[28] = _zz_88; - _zz_89[27] = _zz_88; - _zz_89[26] = _zz_88; - _zz_89[25] = _zz_88; - _zz_89[24] = _zz_88; - _zz_89[23] = _zz_88; - _zz_89[22] = _zz_88; - _zz_89[21] = _zz_88; - _zz_89[20] = _zz_88; - _zz_89[19] = _zz_88; - _zz_89[18] = _zz_88; - _zz_89[17] = _zz_88; - _zz_89[16] = _zz_88; - _zz_89[15] = _zz_88; - _zz_89[14] = _zz_88; - _zz_89[13] = _zz_88; - _zz_89[12] = _zz_88; - _zz_89[11] = _zz_88; - _zz_89[10] = _zz_88; - _zz_89[9] = _zz_88; - _zz_89[8] = _zz_88; - _zz_89[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_90 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + assign _zz_90 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); always @ (*) begin _zz_91[31] = _zz_90; _zz_91[30] = _zz_90; @@ -3732,16 +3717,45 @@ module VexRiscv_inner ( _zz_91[18] = _zz_90; _zz_91[17] = _zz_90; _zz_91[16] = _zz_90; - _zz_91[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_284) + _zz_91[15] = _zz_90; + _zz_91[14] = _zz_90; + _zz_91[13] = _zz_90; + _zz_91[12] = _zz_90; + _zz_91[11] = _zz_90; + _zz_91[10] = _zz_90; + _zz_91[9] = _zz_90; + _zz_91[8] = _zz_90; + _zz_91[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_92 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_93[31] = _zz_92; + _zz_93[30] = _zz_92; + _zz_93[29] = _zz_92; + _zz_93[28] = _zz_92; + _zz_93[27] = _zz_92; + _zz_93[26] = _zz_92; + _zz_93[25] = _zz_92; + _zz_93[24] = _zz_92; + _zz_93[23] = _zz_92; + _zz_93[22] = _zz_92; + _zz_93[21] = _zz_92; + _zz_93[20] = _zz_92; + _zz_93[19] = _zz_92; + _zz_93[18] = _zz_92; + _zz_93[17] = _zz_92; + _zz_93[16] = _zz_92; + _zz_93[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_291) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_89; + writeBack_DBusCachedPlugin_rspFormated = _zz_91; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_91; + writeBack_DBusCachedPlugin_rspFormated = _zz_93; end default : begin writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; @@ -3767,52 +3781,52 @@ module VexRiscv_inner ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_93 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_94 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_95 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_96 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_97 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_92 = {(((decode_INSTRUCTION & _zz_410) == 32'h00100050) != 1'b0),{(_zz_97 != 1'b0),{(_zz_97 != 1'b0),{(_zz_411 != _zz_412),{_zz_413,{_zz_414,_zz_415}}}}}}; - assign _zz_98 = _zz_92[2 : 1]; - assign _zz_54 = _zz_98; - assign _zz_99 = _zz_92[7 : 6]; - assign _zz_53 = _zz_99; - assign _zz_100 = _zz_92[9 : 8]; - assign _zz_52 = _zz_100; - assign _zz_101 = _zz_92[19 : 18]; - assign _zz_51 = _zz_101; - assign _zz_102 = _zz_92[22 : 21]; - assign _zz_50 = _zz_102; - assign _zz_103 = _zz_92[24 : 23]; - assign _zz_49 = _zz_103; - assign _zz_104 = _zz_92[27 : 26]; - assign _zz_48 = _zz_104; - assign _zz_105 = _zz_92[29 : 29]; - assign _zz_47 = _zz_105; + assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_96 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_94 = {(((decode_INSTRUCTION & _zz_417) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}; + assign _zz_100 = _zz_94[2 : 1]; + assign _zz_56 = _zz_100; + assign _zz_101 = _zz_94[7 : 6]; + assign _zz_55 = _zz_101; + assign _zz_102 = _zz_94[9 : 8]; + assign _zz_54 = _zz_102; + assign _zz_103 = _zz_94[19 : 18]; + assign _zz_53 = _zz_103; + assign _zz_104 = _zz_94[22 : 21]; + assign _zz_52 = _zz_104; + assign _zz_105 = _zz_94[24 : 23]; + assign _zz_51 = _zz_105; + assign _zz_106 = _zz_94[27 : 26]; + assign _zz_50 = _zz_106; + assign _zz_107 = _zz_94[29 : 29]; + assign _zz_49 = _zz_107; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_241; - assign decode_RegFilePlugin_rs2Data = _zz_242; + assign decode_RegFilePlugin_rs1Data = _zz_248; + assign decode_RegFilePlugin_rs2Data = _zz_249; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); - if(_zz_106)begin + lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); + if(_zz_108)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; - if(_zz_106)begin + lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; + if(_zz_108)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_55; - if(_zz_106)begin + lastStageRegFileWrite_payload_data = _zz_57; + if(_zz_108)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -3834,13 +3848,13 @@ module VexRiscv_inner ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_107 = execute_IntAluPlugin_bitwise; + _zz_109 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_107 = {31'd0, _zz_331}; + _zz_109 = {31'd0, _zz_338}; end default : begin - _zz_107 = execute_SRC_ADD_SUB; + _zz_109 = execute_SRC_ADD_SUB; end endcase end @@ -3848,45 +3862,21 @@ module VexRiscv_inner ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_108 = execute_RS1; + _zz_110 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_108 = {29'd0, _zz_332}; + _zz_110 = {29'd0, _zz_339}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_108 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_108 = {27'd0, _zz_333}; + _zz_110 = {27'd0, _zz_340}; end endcase end - assign _zz_109 = _zz_334[11]; - always @ (*) begin - _zz_110[19] = _zz_109; - _zz_110[18] = _zz_109; - _zz_110[17] = _zz_109; - _zz_110[16] = _zz_109; - _zz_110[15] = _zz_109; - _zz_110[14] = _zz_109; - _zz_110[13] = _zz_109; - _zz_110[12] = _zz_109; - _zz_110[11] = _zz_109; - _zz_110[10] = _zz_109; - _zz_110[9] = _zz_109; - _zz_110[8] = _zz_109; - _zz_110[7] = _zz_109; - _zz_110[6] = _zz_109; - _zz_110[5] = _zz_109; - _zz_110[4] = _zz_109; - _zz_110[3] = _zz_109; - _zz_110[2] = _zz_109; - _zz_110[1] = _zz_109; - _zz_110[0] = _zz_109; - end - - assign _zz_111 = _zz_335[11]; + assign _zz_111 = _zz_341[11]; always @ (*) begin _zz_112[19] = _zz_111; _zz_112[18] = _zz_111; @@ -3910,25 +3900,49 @@ module VexRiscv_inner ( _zz_112[0] = _zz_111; end + assign _zz_113 = _zz_342[11]; + always @ (*) begin + _zz_114[19] = _zz_113; + _zz_114[18] = _zz_113; + _zz_114[17] = _zz_113; + _zz_114[16] = _zz_113; + _zz_114[15] = _zz_113; + _zz_114[14] = _zz_113; + _zz_114[13] = _zz_113; + _zz_114[12] = _zz_113; + _zz_114[11] = _zz_113; + _zz_114[10] = _zz_113; + _zz_114[9] = _zz_113; + _zz_114[8] = _zz_113; + _zz_114[7] = _zz_113; + _zz_114[6] = _zz_113; + _zz_114[5] = _zz_113; + _zz_114[4] = _zz_113; + _zz_114[3] = _zz_113; + _zz_114[2] = _zz_113; + _zz_114[1] = _zz_113; + _zz_114[0] = _zz_113; + end + always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_113 = execute_RS2; + _zz_115 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_113 = {_zz_110,execute_INSTRUCTION[31 : 20]}; + _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_113 = {_zz_112,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_113 = _zz_39; + _zz_115 = _zz_41; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_336; + execute_SrcPlugin_addSub = _zz_343; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3937,263 +3951,170 @@ module VexRiscv_inner ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_114[0] = execute_SRC1[31]; - _zz_114[1] = execute_SRC1[30]; - _zz_114[2] = execute_SRC1[29]; - _zz_114[3] = execute_SRC1[28]; - _zz_114[4] = execute_SRC1[27]; - _zz_114[5] = execute_SRC1[26]; - _zz_114[6] = execute_SRC1[25]; - _zz_114[7] = execute_SRC1[24]; - _zz_114[8] = execute_SRC1[23]; - _zz_114[9] = execute_SRC1[22]; - _zz_114[10] = execute_SRC1[21]; - _zz_114[11] = execute_SRC1[20]; - _zz_114[12] = execute_SRC1[19]; - _zz_114[13] = execute_SRC1[18]; - _zz_114[14] = execute_SRC1[17]; - _zz_114[15] = execute_SRC1[16]; - _zz_114[16] = execute_SRC1[15]; - _zz_114[17] = execute_SRC1[14]; - _zz_114[18] = execute_SRC1[13]; - _zz_114[19] = execute_SRC1[12]; - _zz_114[20] = execute_SRC1[11]; - _zz_114[21] = execute_SRC1[10]; - _zz_114[22] = execute_SRC1[9]; - _zz_114[23] = execute_SRC1[8]; - _zz_114[24] = execute_SRC1[7]; - _zz_114[25] = execute_SRC1[6]; - _zz_114[26] = execute_SRC1[5]; - _zz_114[27] = execute_SRC1[4]; - _zz_114[28] = execute_SRC1[3]; - _zz_114[29] = execute_SRC1[2]; - _zz_114[30] = execute_SRC1[1]; - _zz_114[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_114 : execute_SRC1); - always @ (*) begin - _zz_115[0] = memory_SHIFT_RIGHT[31]; - _zz_115[1] = memory_SHIFT_RIGHT[30]; - _zz_115[2] = memory_SHIFT_RIGHT[29]; - _zz_115[3] = memory_SHIFT_RIGHT[28]; - _zz_115[4] = memory_SHIFT_RIGHT[27]; - _zz_115[5] = memory_SHIFT_RIGHT[26]; - _zz_115[6] = memory_SHIFT_RIGHT[25]; - _zz_115[7] = memory_SHIFT_RIGHT[24]; - _zz_115[8] = memory_SHIFT_RIGHT[23]; - _zz_115[9] = memory_SHIFT_RIGHT[22]; - _zz_115[10] = memory_SHIFT_RIGHT[21]; - _zz_115[11] = memory_SHIFT_RIGHT[20]; - _zz_115[12] = memory_SHIFT_RIGHT[19]; - _zz_115[13] = memory_SHIFT_RIGHT[18]; - _zz_115[14] = memory_SHIFT_RIGHT[17]; - _zz_115[15] = memory_SHIFT_RIGHT[16]; - _zz_115[16] = memory_SHIFT_RIGHT[15]; - _zz_115[17] = memory_SHIFT_RIGHT[14]; - _zz_115[18] = memory_SHIFT_RIGHT[13]; - _zz_115[19] = memory_SHIFT_RIGHT[12]; - _zz_115[20] = memory_SHIFT_RIGHT[11]; - _zz_115[21] = memory_SHIFT_RIGHT[10]; - _zz_115[22] = memory_SHIFT_RIGHT[9]; - _zz_115[23] = memory_SHIFT_RIGHT[8]; - _zz_115[24] = memory_SHIFT_RIGHT[7]; - _zz_115[25] = memory_SHIFT_RIGHT[6]; - _zz_115[26] = memory_SHIFT_RIGHT[5]; - _zz_115[27] = memory_SHIFT_RIGHT[4]; - _zz_115[28] = memory_SHIFT_RIGHT[3]; - _zz_115[29] = memory_SHIFT_RIGHT[2]; - _zz_115[30] = memory_SHIFT_RIGHT[1]; - _zz_115[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_264)begin - if(_zz_265)begin - if(_zz_116)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_116[0] = execute_SRC1[31]; + _zz_116[1] = execute_SRC1[30]; + _zz_116[2] = execute_SRC1[29]; + _zz_116[3] = execute_SRC1[28]; + _zz_116[4] = execute_SRC1[27]; + _zz_116[5] = execute_SRC1[26]; + _zz_116[6] = execute_SRC1[25]; + _zz_116[7] = execute_SRC1[24]; + _zz_116[8] = execute_SRC1[23]; + _zz_116[9] = execute_SRC1[22]; + _zz_116[10] = execute_SRC1[21]; + _zz_116[11] = execute_SRC1[20]; + _zz_116[12] = execute_SRC1[19]; + _zz_116[13] = execute_SRC1[18]; + _zz_116[14] = execute_SRC1[17]; + _zz_116[15] = execute_SRC1[16]; + _zz_116[16] = execute_SRC1[15]; + _zz_116[17] = execute_SRC1[14]; + _zz_116[18] = execute_SRC1[13]; + _zz_116[19] = execute_SRC1[12]; + _zz_116[20] = execute_SRC1[11]; + _zz_116[21] = execute_SRC1[10]; + _zz_116[22] = execute_SRC1[9]; + _zz_116[23] = execute_SRC1[8]; + _zz_116[24] = execute_SRC1[7]; + _zz_116[25] = execute_SRC1[6]; + _zz_116[26] = execute_SRC1[5]; + _zz_116[27] = execute_SRC1[4]; + _zz_116[28] = execute_SRC1[3]; + _zz_116[29] = execute_SRC1[2]; + _zz_116[30] = execute_SRC1[1]; + _zz_116[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); + always @ (*) begin + _zz_117[0] = memory_SHIFT_RIGHT[31]; + _zz_117[1] = memory_SHIFT_RIGHT[30]; + _zz_117[2] = memory_SHIFT_RIGHT[29]; + _zz_117[3] = memory_SHIFT_RIGHT[28]; + _zz_117[4] = memory_SHIFT_RIGHT[27]; + _zz_117[5] = memory_SHIFT_RIGHT[26]; + _zz_117[6] = memory_SHIFT_RIGHT[25]; + _zz_117[7] = memory_SHIFT_RIGHT[24]; + _zz_117[8] = memory_SHIFT_RIGHT[23]; + _zz_117[9] = memory_SHIFT_RIGHT[22]; + _zz_117[10] = memory_SHIFT_RIGHT[21]; + _zz_117[11] = memory_SHIFT_RIGHT[20]; + _zz_117[12] = memory_SHIFT_RIGHT[19]; + _zz_117[13] = memory_SHIFT_RIGHT[18]; + _zz_117[14] = memory_SHIFT_RIGHT[17]; + _zz_117[15] = memory_SHIFT_RIGHT[16]; + _zz_117[16] = memory_SHIFT_RIGHT[15]; + _zz_117[17] = memory_SHIFT_RIGHT[14]; + _zz_117[18] = memory_SHIFT_RIGHT[13]; + _zz_117[19] = memory_SHIFT_RIGHT[12]; + _zz_117[20] = memory_SHIFT_RIGHT[11]; + _zz_117[21] = memory_SHIFT_RIGHT[10]; + _zz_117[22] = memory_SHIFT_RIGHT[9]; + _zz_117[23] = memory_SHIFT_RIGHT[8]; + _zz_117[24] = memory_SHIFT_RIGHT[7]; + _zz_117[25] = memory_SHIFT_RIGHT[6]; + _zz_117[26] = memory_SHIFT_RIGHT[5]; + _zz_117[27] = memory_SHIFT_RIGHT[4]; + _zz_117[28] = memory_SHIFT_RIGHT[3]; + _zz_117[29] = memory_SHIFT_RIGHT[2]; + _zz_117[30] = memory_SHIFT_RIGHT[1]; + _zz_117[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_118 = 1'b0; + if(_zz_271)begin + if(_zz_272)begin + if(_zz_123)begin + _zz_118 = 1'b1; end end end - if(_zz_266)begin - if(_zz_267)begin - if(_zz_118)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_273)begin + if(_zz_274)begin + if(_zz_125)begin + _zz_118 = 1'b1; end end end - if(_zz_268)begin - if(_zz_269)begin - if(_zz_120)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_275)begin + if(_zz_276)begin + if(_zz_127)begin + _zz_118 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_118 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_264)begin - if(_zz_265)begin - if(_zz_117)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_119 = 1'b0; + if(_zz_271)begin + if(_zz_272)begin + if(_zz_124)begin + _zz_119 = 1'b1; end end end - if(_zz_266)begin - if(_zz_267)begin - if(_zz_119)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_273)begin + if(_zz_274)begin + if(_zz_126)begin + _zz_119 = 1'b1; end end end - if(_zz_268)begin - if(_zz_269)begin - if(_zz_121)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_275)begin + if(_zz_276)begin + if(_zz_128)begin + _zz_119 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_119 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_45 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_44[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_55; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_116 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_117 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_118 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_119 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_120 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_121 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_122 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_122 == 3'b000)) begin - _zz_123 = execute_BranchPlugin_eq; - end else if((_zz_122 == 3'b001)) begin - _zz_123 = (! execute_BranchPlugin_eq); - end else if((((_zz_122 & 3'b101) == 3'b101))) begin - _zz_123 = (! execute_SRC_LESS); + assign _zz_129 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_129 == 3'b000)) begin + _zz_130 = execute_BranchPlugin_eq; + end else if((_zz_129 == 3'b001)) begin + _zz_130 = (! execute_BranchPlugin_eq); + end else if((((_zz_129 & 3'b101) == 3'b101))) begin + _zz_130 = (! execute_SRC_LESS); end else begin - _zz_123 = execute_SRC_LESS; + _zz_130 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_124 = 1'b0; - end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_124 = 1'b1; - end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_124 = 1'b1; - end - default : begin - _zz_124 = _zz_123; - end - endcase - end - - assign _zz_125 = _zz_343[11]; - always @ (*) begin - _zz_126[19] = _zz_125; - _zz_126[18] = _zz_125; - _zz_126[17] = _zz_125; - _zz_126[16] = _zz_125; - _zz_126[15] = _zz_125; - _zz_126[14] = _zz_125; - _zz_126[13] = _zz_125; - _zz_126[12] = _zz_125; - _zz_126[11] = _zz_125; - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; - end - - assign _zz_127 = _zz_344[19]; - always @ (*) begin - _zz_128[10] = _zz_127; - _zz_128[9] = _zz_127; - _zz_128[8] = _zz_127; - _zz_128[7] = _zz_127; - _zz_128[6] = _zz_127; - _zz_128[5] = _zz_127; - _zz_128[4] = _zz_127; - _zz_128[3] = _zz_127; - _zz_128[2] = _zz_127; - _zz_128[1] = _zz_127; - _zz_128[0] = _zz_127; - end - - assign _zz_129 = _zz_345[11]; - always @ (*) begin - _zz_130[18] = _zz_129; - _zz_130[17] = _zz_129; - _zz_130[16] = _zz_129; - _zz_130[15] = _zz_129; - _zz_130[14] = _zz_129; - _zz_130[13] = _zz_129; - _zz_130[12] = _zz_129; - _zz_130[11] = _zz_129; - _zz_130[10] = _zz_129; - _zz_130[9] = _zz_129; - _zz_130[8] = _zz_129; - _zz_130[7] = _zz_129; - _zz_130[6] = _zz_129; - _zz_130[5] = _zz_129; - _zz_130[4] = _zz_129; - _zz_130[3] = _zz_129; - _zz_130[2] = _zz_129; - _zz_130[1] = _zz_129; - _zz_130[0] = _zz_129; - end - - always @ (*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_131 = (_zz_346[1] ^ execute_RS1[1]); + _zz_131 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_131 = _zz_347[1]; - end - default : begin - _zz_131 = _zz_348[1]; + _zz_131 = 1'b1; end - endcase - end - - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_131); - always @ (*) begin - case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src1 = execute_RS1; + _zz_131 = 1'b1; end default : begin - execute_BranchPlugin_branch_src1 = execute_PC; + _zz_131 = _zz_130; end endcase end - assign _zz_132 = _zz_349[11]; + assign _zz_132 = _zz_350[11]; always @ (*) begin _zz_133[19] = _zz_132; _zz_133[18] = _zz_132; @@ -4217,21 +4138,7 @@ module VexRiscv_inner ( _zz_133[0] = _zz_132; end - always @ (*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_133,execute_INSTRUCTION[31 : 20]}; - end - default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_135,{{{_zz_587,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_137,{{{_zz_588,_zz_589},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_352}; - end - end - endcase - end - - assign _zz_134 = _zz_350[19]; + assign _zz_134 = _zz_351[19]; always @ (*) begin _zz_135[10] = _zz_134; _zz_135[9] = _zz_134; @@ -4246,7 +4153,7 @@ module VexRiscv_inner ( _zz_135[0] = _zz_134; end - assign _zz_136 = _zz_351[11]; + assign _zz_136 = _zz_352[11]; always @ (*) begin _zz_137[18] = _zz_136; _zz_137[17] = _zz_136; @@ -4269,6 +4176,108 @@ module VexRiscv_inner ( _zz_137[0] = _zz_136; end + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_138 = (_zz_353[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_138 = _zz_354[1]; + end + default : begin + _zz_138 = _zz_355[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_139 = _zz_356[11]; + always @ (*) begin + _zz_140[19] = _zz_139; + _zz_140[18] = _zz_139; + _zz_140[17] = _zz_139; + _zz_140[16] = _zz_139; + _zz_140[15] = _zz_139; + _zz_140[14] = _zz_139; + _zz_140[13] = _zz_139; + _zz_140[12] = _zz_139; + _zz_140[11] = _zz_139; + _zz_140[10] = _zz_139; + _zz_140[9] = _zz_139; + _zz_140[8] = _zz_139; + _zz_140[7] = _zz_139; + _zz_140[6] = _zz_139; + _zz_140[5] = _zz_139; + _zz_140[4] = _zz_139; + _zz_140[3] = _zz_139; + _zz_140[2] = _zz_139; + _zz_140[1] = _zz_139; + _zz_140[0] = _zz_139; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_594,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_595,_zz_596},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_359}; + end + end + endcase + end + + assign _zz_141 = _zz_357[19]; + always @ (*) begin + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; + end + + assign _zz_143 = _zz_358[11]; + always @ (*) begin + _zz_144[18] = _zz_143; + _zz_144[17] = _zz_143; + _zz_144[16] = _zz_143; + _zz_144[15] = _zz_143; + _zz_144[14] = _zz_143; + _zz_144[13] = _zz_143; + _zz_144[12] = _zz_143; + _zz_144[11] = _zz_143; + _zz_144[10] = _zz_143; + _zz_144[9] = _zz_143; + _zz_144[8] = _zz_143; + _zz_144[7] = _zz_143; + _zz_144[6] = _zz_143; + _zz_144[5] = _zz_143; + _zz_144[4] = _zz_143; + _zz_144[3] = _zz_143; + _zz_144[2] = _zz_143; + _zz_144[1] = _zz_143; + _zz_144[0] = _zz_143; + end + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; @@ -4283,18 +4292,18 @@ module VexRiscv_inner ( end end - assign _zz_138 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_139 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_140 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_141 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_142 = _zz_353[0]; - assign _zz_143 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_144 = _zz_355[0]; + assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_149 = _zz_360[0]; + assign _zz_150 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_151 = _zz_362[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_254)begin + if(_zz_261)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4314,7 +4323,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_258)begin + if(_zz_265)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4375,7 +4384,7 @@ module VexRiscv_inner ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4545,7 +4554,7 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_270)begin + if(_zz_277)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4564,20 +4573,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_271)begin + if(_zz_278)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_272)begin + if(_zz_279)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_271)begin + if(_zz_278)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_272)begin + if(_zz_279)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4592,14 +4601,14 @@ module VexRiscv_inner ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_270)begin + if(_zz_277)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_270)begin + if(_zz_277)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4608,7 +4617,7 @@ module VexRiscv_inner ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_285) + case(_zz_292) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4621,45 +4630,45 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_357; + assign execute_CfuPlugin_functionsIds_0 = _zz_364; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_161 = _zz_358[11]; - always @ (*) begin - _zz_162[19] = _zz_161; - _zz_162[18] = _zz_161; - _zz_162[17] = _zz_161; - _zz_162[16] = _zz_161; - _zz_162[15] = _zz_161; - _zz_162[14] = _zz_161; - _zz_162[13] = _zz_161; - _zz_162[12] = _zz_161; - _zz_162[11] = _zz_161; - _zz_162[10] = _zz_161; - _zz_162[9] = _zz_161; - _zz_162[8] = _zz_161; - _zz_162[7] = _zz_161; - _zz_162[6] = _zz_161; - _zz_162[5] = _zz_161; - _zz_162[4] = _zz_161; - _zz_162[3] = _zz_161; - _zz_162[2] = _zz_161; - _zz_162[1] = _zz_161; - _zz_162[0] = _zz_161; + assign _zz_168 = _zz_365[11]; + always @ (*) begin + _zz_169[19] = _zz_168; + _zz_169[18] = _zz_168; + _zz_169[17] = _zz_168; + _zz_169[16] = _zz_168; + _zz_169[15] = _zz_168; + _zz_169[14] = _zz_168; + _zz_169[13] = _zz_168; + _zz_169[12] = _zz_168; + _zz_169[11] = _zz_168; + _zz_169[10] = _zz_168; + _zz_169[9] = _zz_168; + _zz_169[8] = _zz_168; + _zz_169[7] = _zz_168; + _zz_169[6] = _zz_168; + _zz_169[5] = _zz_168; + _zz_169[4] = _zz_168; + _zz_169[3] = _zz_168; + _zz_169[2] = _zz_168; + _zz_169[1] = _zz_168; + _zz_169[0] = _zz_168; end always @ (*) begin case(execute_CfuPlugin_CFU_ENCODING) `Input2Kind_defaultEncoding_RS : begin - _zz_163 = execute_RS2; + _zz_170 = execute_RS2; end default : begin - _zz_163 = {_zz_162,execute_INSTRUCTION[31 : 20]}; + _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 20]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_163; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4685,7 +4694,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_273) + case(_zz_280) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4699,7 +4708,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_273) + case(_zz_280) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4718,12 +4727,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_359) + $signed(_zz_360)); + assign writeBack_MulPlugin_result = ($signed(_zz_366) + $signed(_zz_367)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_249)begin - if(_zz_274)begin + if(_zz_256)begin + if(_zz_281)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4731,7 +4740,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_275)begin + if(_zz_282)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4742,32 +4751,32 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_364); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_164 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_164[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_365); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_366 : _zz_367); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_368[31:0]; - assign _zz_165 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_166 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_167 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_372); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_373 : _zz_374); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_375[31:0]; + assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_168[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_168[31 : 0] = execute_RS1; + _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_175[31 : 0] = execute_RS1; end - assign _zz_170 = (_zz_169 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_170 != 32'h0); + assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_177 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_276) + case(_zz_283) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4781,7 +4790,7 @@ module VexRiscv_inner ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_171))begin + if((! _zz_178))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4793,7 +4802,7 @@ module VexRiscv_inner ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_276) + case(_zz_283) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4809,35 +4818,35 @@ module VexRiscv_inner ( assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); assign debug_resetOut = DebugPlugin_resetIt_regNext; assign _zz_29 = decode_SRC1_CTRL; - assign _zz_27 = _zz_54; - assign _zz_41 = decode_to_execute_SRC1_CTRL; + assign _zz_27 = _zz_56; + assign _zz_43 = decode_to_execute_SRC1_CTRL; assign _zz_26 = decode_ALU_CTRL; - assign _zz_24 = _zz_53; - assign _zz_42 = decode_to_execute_ALU_CTRL; + assign _zz_24 = _zz_55; + assign _zz_44 = decode_to_execute_ALU_CTRL; assign _zz_23 = decode_SRC2_CTRL; - assign _zz_21 = _zz_52; - assign _zz_40 = decode_to_execute_SRC2_CTRL; + assign _zz_21 = _zz_54; + assign _zz_42 = decode_to_execute_SRC2_CTRL; assign _zz_20 = decode_ALU_BITWISE_CTRL; - assign _zz_18 = _zz_51; - assign _zz_43 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_18 = _zz_53; + assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; assign _zz_17 = decode_SHIFT_CTRL; assign _zz_14 = execute_SHIFT_CTRL; - assign _zz_15 = _zz_50; - assign _zz_38 = decode_to_execute_SHIFT_CTRL; - assign _zz_37 = execute_to_memory_SHIFT_CTRL; + assign _zz_15 = _zz_52; + assign _zz_40 = decode_to_execute_SHIFT_CTRL; + assign _zz_39 = execute_to_memory_SHIFT_CTRL; assign _zz_12 = decode_BRANCH_CTRL; - assign _zz_56 = _zz_49; - assign _zz_34 = decode_to_execute_BRANCH_CTRL; + assign _zz_58 = _zz_51; + assign _zz_36 = decode_to_execute_BRANCH_CTRL; assign _zz_10 = decode_ENV_CTRL; assign _zz_7 = execute_ENV_CTRL; assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_48; - assign _zz_32 = decode_to_execute_ENV_CTRL; - assign _zz_31 = execute_to_memory_ENV_CTRL; - assign _zz_33 = memory_to_writeBack_ENV_CTRL; + assign _zz_8 = _zz_50; + assign _zz_34 = decode_to_execute_ENV_CTRL; + assign _zz_33 = execute_to_memory_ENV_CTRL; + assign _zz_35 = memory_to_writeBack_ENV_CTRL; assign _zz_3 = decode_CfuPlugin_CFU_ENCODING; - assign _zz_1 = _zz_47; - assign _zz_30 = decode_to_execute_CfuPlugin_CFU_ENCODING; + assign _zz_1 = _zz_49; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_ENCODING; assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4860,7 +4869,7 @@ module VexRiscv_inner ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_172) + case(_zz_179) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4870,272 +4879,272 @@ module VexRiscv_inner ( end always @ (*) begin - _zz_173 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_173[12 : 0] = 13'h1000; - _zz_173[25 : 20] = 6'h20; + _zz_180[12 : 0] = 13'h1000; + _zz_180[25 : 20] = 6'h20; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_174[3 : 0] = 4'b1011; + _zz_181[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_175[4 : 0] = 5'h16; + _zz_182[4 : 0] = 5'h16; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_176[5 : 0] = 6'h21; + _zz_183[5 : 0] = 6'h21; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_177[31 : 30] = CsrPlugin_misa_base; - _zz_177[25 : 0] = CsrPlugin_misa_extensions; + _zz_184[31 : 30] = CsrPlugin_misa_base; + _zz_184[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_178[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_178[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_178[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_179[11 : 11] = CsrPlugin_mip_MEIP; - _zz_179[7 : 7] = CsrPlugin_mip_MTIP; - _zz_179[3 : 3] = CsrPlugin_mip_MSIP; + _zz_186[11 : 11] = CsrPlugin_mip_MEIP; + _zz_186[7 : 7] = CsrPlugin_mip_MTIP; + _zz_186[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_180[11 : 11] = CsrPlugin_mie_MEIE; - _zz_180[7 : 7] = CsrPlugin_mie_MTIE; - _zz_180[3 : 3] = CsrPlugin_mie_MSIE; + _zz_187[11 : 11] = CsrPlugin_mie_MEIE; + _zz_187[7 : 7] = CsrPlugin_mie_MTIE; + _zz_187[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_181[31 : 2] = CsrPlugin_mtvec_base; - _zz_181[1 : 0] = CsrPlugin_mtvec_mode; + _zz_188[31 : 2] = CsrPlugin_mtvec_base; + _zz_188[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_182[31 : 0] = CsrPlugin_mepc; + _zz_189[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_183[31 : 0] = CsrPlugin_mscratch; + _zz_190[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_184[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_184[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_185[31 : 0] = CsrPlugin_mtval; + _zz_192[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_186[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_187[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_188[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_189[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_199 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_200 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_201 = 32'h0; if(execute_CsrPlugin_csr_2820)begin - _zz_194[31 : 0] = _zz_145; + _zz_201[31 : 0] = _zz_152; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_202 = 32'h0; if(execute_CsrPlugin_csr_2822)begin - _zz_195[31 : 0] = _zz_147; + _zz_202[31 : 0] = _zz_154; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_203 = 32'h0; if(execute_CsrPlugin_csr_2824)begin - _zz_196[31 : 0] = _zz_149; + _zz_203[31 : 0] = _zz_156; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_204 = 32'h0; if(execute_CsrPlugin_csr_2826)begin - _zz_197[31 : 0] = _zz_151; + _zz_204[31 : 0] = _zz_158; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_205 = 32'h0; if(execute_CsrPlugin_csr_2828)begin - _zz_198[31 : 0] = _zz_153; + _zz_205[31 : 0] = _zz_160; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_206 = 32'h0; if(execute_CsrPlugin_csr_2830)begin - _zz_199[31 : 0] = _zz_155; + _zz_206[31 : 0] = _zz_162; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_207 = 32'h0; if(execute_CsrPlugin_csr_2832)begin - _zz_200[31 : 0] = _zz_157; + _zz_207[31 : 0] = _zz_164; end end always @ (*) begin - _zz_201 = 32'h0; + _zz_208 = 32'h0; if(execute_CsrPlugin_csr_2834)begin - _zz_201[31 : 0] = _zz_159; + _zz_208[31 : 0] = _zz_166; end end always @ (*) begin - _zz_202 = 32'h0; + _zz_209 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_202[31 : 0] = _zz_169; + _zz_209[31 : 0] = _zz_176; end end always @ (*) begin - _zz_203 = 32'h0; + _zz_210 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_203[31 : 0] = _zz_170; + _zz_210[31 : 0] = _zz_177; end end - assign execute_CsrPlugin_readData = (((((_zz_173 | _zz_174) | (_zz_175 | _zz_176)) | ((_zz_590 | _zz_177) | (_zz_178 | _zz_179))) | (((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_184 | _zz_185) | (_zz_186 | _zz_187)))) | ((((_zz_188 | _zz_189) | (_zz_190 | _zz_191)) | ((_zz_192 | _zz_193) | (_zz_194 | _zz_195))) | (((_zz_196 | _zz_197) | (_zz_198 | _zz_199)) | ((_zz_200 | _zz_201) | (_zz_202 | _zz_203))))); - assign iBusWishbone_ADR = {_zz_385,_zz_204}; - assign iBusWishbone_CTI = ((_zz_204 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_597 | _zz_184) | (_zz_185 | _zz_186))) | (((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194)))) | ((((_zz_195 | _zz_196) | (_zz_197 | _zz_198)) | ((_zz_199 | _zz_200) | (_zz_201 | _zz_202))) | (((_zz_203 | _zz_204) | (_zz_205 | _zz_206)) | ((_zz_207 | _zz_208) | (_zz_209 | _zz_210))))); + assign iBusWishbone_ADR = {_zz_392,_zz_211}; + assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_277)begin + if(_zz_284)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_277)begin + if(_zz_284)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_205; + assign iBus_rsp_valid = _zz_212; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_211 = (dBus_cmd_payload_length != 3'b000); - assign _zz_207 = dBus_cmd_valid; - assign _zz_209 = dBus_cmd_payload_wr; - assign _zz_210 = (_zz_206 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_208 && (_zz_209 || _zz_210)); - assign dBusWishbone_ADR = ((_zz_211 ? {{dBus_cmd_payload_address[31 : 5],_zz_206},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_211 ? (_zz_210 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_218 = (dBus_cmd_payload_length != 3'b000); + assign _zz_214 = dBus_cmd_valid; + assign _zz_216 = dBus_cmd_payload_wr; + assign _zz_217 = (_zz_213 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_215 && (_zz_216 || _zz_217)); + assign dBusWishbone_ADR = ((_zz_218 ? {{dBus_cmd_payload_address[31 : 5],_zz_213},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_218 ? (_zz_217 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_209 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_209; + assign dBusWishbone_SEL = (_zz_216 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_216; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_208 = (_zz_207 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_207; - assign dBusWishbone_STB = _zz_207; - assign dBus_rsp_valid = _zz_212; + assign _zz_215 = (_zz_214 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_214; + assign dBusWishbone_STB = _zz_214; + assign dBus_rsp_valid = _zz_219; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5144,21 +5153,21 @@ module VexRiscv_inner ( IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_70 <= 1'b0; _zz_72 <= 1'b0; + _zz_74 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_85; + IBusCachedPlugin_rspCounter <= _zz_87; IBusCachedPlugin_rspCounter <= 32'h0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_86; + DBusCachedPlugin_rspCounter <= _zz_88; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_106 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_108 <= 1'b1; + _zz_120 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -5182,16 +5191,16 @@ module VexRiscv_inner ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_169 <= 32'h0; + _zz_176 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_172 <= 3'b000; + _zz_179 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_204 <= 3'b000; - _zz_205 <= 1'b0; - _zz_206 <= 3'b000; + _zz_211 <= 3'b000; _zz_212 <= 1'b0; + _zz_213 <= 3'b000; + _zz_219 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5213,16 +5222,16 @@ module VexRiscv_inner ( IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_70 <= 1'b0; + _zz_72 <= 1'b0; end - if(_zz_68)begin - _zz_70 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_70)begin + _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_72 <= 1'b0; + _zz_74 <= 1'b0; end if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + _zz_74 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; @@ -5272,7 +5281,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_278)begin + if(_zz_285)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5281,8 +5290,8 @@ module VexRiscv_inner ( if(dBus_rsp_valid)begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_106 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_108 <= 1'b0; + _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5304,14 +5313,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_279)begin - if(_zz_280)begin + if(_zz_286)begin + if(_zz_287)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_281)begin + if(_zz_288)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_282)begin + if(_zz_289)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5336,7 +5345,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_259)begin + if(_zz_266)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5347,8 +5356,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_260)begin - case(_zz_262) + if(_zz_267)begin + case(_zz_269) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5358,7 +5367,7 @@ module VexRiscv_inner ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_140,{_zz_139,_zz_138}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -5374,12 +5383,12 @@ module VexRiscv_inner ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_283)begin + if(_zz_290)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= execute_CfuPlugin_CFU_IN_FLIGHT; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; @@ -5399,25 +5408,25 @@ module VexRiscv_inner ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_172) + case(_zz_179) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_172 <= 3'b001; + _zz_179 <= 3'b001; end end 3'b001 : begin - _zz_172 <= 3'b010; + _zz_179 <= 3'b010; end 3'b010 : begin - _zz_172 <= 3'b011; + _zz_179 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_172 <= 3'b100; + _zz_179 <= 3'b100; end end 3'b100 : begin - _zz_172 <= 3'b000; + _zz_179 <= 3'b000; end default : begin end @@ -5431,41 +5440,41 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_378[0]; - CsrPlugin_mstatus_MIE <= _zz_379[0]; + CsrPlugin_mstatus_MPIE <= _zz_385[0]; + CsrPlugin_mstatus_MIE <= _zz_386[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_381[0]; - CsrPlugin_mie_MTIE <= _zz_382[0]; - CsrPlugin_mie_MSIE <= _zz_383[0]; + CsrPlugin_mie_MEIE <= _zz_388[0]; + CsrPlugin_mie_MTIE <= _zz_389[0]; + CsrPlugin_mie_MSIE <= _zz_390[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_169 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_277)begin + if(_zz_284)begin if(iBusWishbone_ACK)begin - _zz_204 <= (_zz_204 + 3'b001); + _zz_211 <= (_zz_211 + 3'b001); end end - _zz_205 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_207 && _zz_208))begin - _zz_206 <= (_zz_206 + 3'b001); - if(_zz_210)begin - _zz_206 <= 3'b000; + _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_214 && _zz_215))begin + _zz_213 <= (_zz_213 + 3'b001); + if(_zz_217)begin + _zz_213 <= 3'b000; end end - _zz_212 <= ((_zz_207 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_219 <= ((_zz_214 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_73 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_75 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; @@ -5473,7 +5482,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_278)begin + if(_zz_285)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5491,8 +5500,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_121 <= _zz_46[11 : 7]; + _zz_122 <= _zz_57; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5500,37 +5509,37 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_254)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_142 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_142 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_261)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_258)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_144 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_144 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(_zz_265)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); end if(DBusCachedPlugin_exceptionBus_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_279)begin - if(_zz_280)begin + if(_zz_286)begin + if(_zz_287)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_281)begin + if(_zz_288)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_282)begin + if(_zz_289)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_259)begin + if(_zz_266)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5544,31 +5553,31 @@ module VexRiscv_inner ( end endcase end - if(_zz_146[0])begin - _zz_145 <= (_zz_145 + 32'h00000001); + if(_zz_153[0])begin + _zz_152 <= (_zz_152 + 32'h00000001); end - if(_zz_148[0])begin - _zz_147 <= (_zz_147 + 32'h00000001); + if(_zz_155[0])begin + _zz_154 <= (_zz_154 + 32'h00000001); end - if(_zz_150[0])begin - _zz_149 <= (_zz_149 + 32'h00000001); + if(_zz_157[0])begin + _zz_156 <= (_zz_156 + 32'h00000001); end - if(_zz_152[0])begin - _zz_151 <= (_zz_151 + 32'h00000001); + if(_zz_159[0])begin + _zz_158 <= (_zz_158 + 32'h00000001); end - if(_zz_154[0])begin - _zz_153 <= (_zz_153 + 32'h00000001); + if(_zz_161[0])begin + _zz_160 <= (_zz_160 + 32'h00000001); end - if(_zz_156[0])begin - _zz_155 <= (_zz_155 + 32'h00000001); + if(_zz_163[0])begin + _zz_162 <= (_zz_162 + 32'h00000001); end - if(_zz_158[0])begin - _zz_157 <= (_zz_157 + 32'h00000001); + if(_zz_165[0])begin + _zz_164 <= (_zz_164 + 32'h00000001); end - if(_zz_160[0])begin - _zz_159 <= (_zz_159 + 32'h00000001); + if(_zz_167[0])begin + _zz_166 <= (_zz_166 + 32'h00000001); end - if(_zz_283)begin + if(_zz_290)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5578,27 +5587,27 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_249)begin - if(_zz_274)begin + if(_zz_256)begin + if(_zz_281)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_369[31:0]; + memory_DivPlugin_div_result <= _zz_376[31:0]; end end end - if(_zz_275)begin + if(_zz_282)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_167 ? (~ _zz_168) : _zz_168) + _zz_375); - memory_DivPlugin_rs2 <= ((_zz_166 ? (~ execute_RS2) : execute_RS2) + _zz_377); - memory_DivPlugin_div_needRevert <= ((_zz_167 ^ (_zz_166 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_382); + memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_384); + memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin decode_to_execute_PC <= decode_PC; end if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_39; + execute_to_memory_PC <= _zz_41; end if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin memory_to_writeBack_PC <= memory_PC; @@ -5613,13 +5622,13 @@ module VexRiscv_inner ( memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_58; + decode_to_execute_FORMAL_PC_NEXT <= _zz_60; end if((! memory_arbitration_isStuck))begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_57; + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_59; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; @@ -5757,10 +5766,10 @@ module VexRiscv_inner ( memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_35; + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_36; + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; end if((! memory_arbitration_isStuck))begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; @@ -5771,6 +5780,9 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + end if((! memory_arbitration_isStuck))begin execute_to_memory_MUL_LL <= execute_MUL_LL; end @@ -5911,7 +5923,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_380[0]; + CsrPlugin_mip_MSIP <= _zz_387[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5932,7 +5944,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_384[0]; + CsrPlugin_mcause_interrupt <= _zz_391[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5963,82 +5975,82 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_2820)begin if(execute_CsrPlugin_writeEnable)begin - _zz_145 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2821)begin if(execute_CsrPlugin_writeEnable)begin - _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2822)begin if(execute_CsrPlugin_writeEnable)begin - _zz_147 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2823)begin if(execute_CsrPlugin_writeEnable)begin - _zz_148 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2824)begin if(execute_CsrPlugin_writeEnable)begin - _zz_149 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2825)begin if(execute_CsrPlugin_writeEnable)begin - _zz_150 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2826)begin if(execute_CsrPlugin_writeEnable)begin - _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2827)begin if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2828)begin if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2829)begin if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2830)begin if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2831)begin if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2832)begin if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2833)begin if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2834)begin if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2835)begin if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -6053,10 +6065,10 @@ module VexRiscv_inner ( DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_55; + DebugPlugin_busReadDataReg <= _zz_57; end - _zz_171 <= debug_bus_cmd_payload_address[2]; - if(_zz_256)begin + _zz_178 <= debug_bus_cmd_payload_address[2]; + if(_zz_263)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -6074,7 +6086,7 @@ module VexRiscv_inner ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_276) + case(_zz_283) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -6102,13 +6114,13 @@ module VexRiscv_inner ( end endcase end - if(_zz_256)begin - if(_zz_257)begin + if(_zz_263)begin + if(_zz_264)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_261)begin + if(_zz_268)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end @@ -6494,7 +6506,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_23)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -6508,7 +6520,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_23)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -6538,7 +6550,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -6565,7 +6577,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -6597,7 +6609,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -6607,7 +6619,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v index 5058753..c944f80 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -82,37 +82,37 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_177; - wire _zz_178; - wire _zz_179; - wire _zz_180; - wire _zz_181; wire _zz_182; wire _zz_183; wire _zz_184; - reg _zz_185; + wire _zz_185; wire _zz_186; - wire [31:0] _zz_187; + wire _zz_187; wire _zz_188; - wire [31:0] _zz_189; + wire _zz_189; reg _zz_190; wire _zz_191; - wire _zz_192; - wire [31:0] _zz_193; - wire _zz_194; - wire _zz_195; + wire [31:0] _zz_192; + wire _zz_193; + wire [31:0] _zz_194; + reg _zz_195; wire _zz_196; wire _zz_197; - wire _zz_198; + wire [31:0] _zz_198; wire _zz_199; wire _zz_200; wire _zz_201; - wire [3:0] _zz_202; + wire _zz_202; wire _zz_203; wire _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; + wire _zz_205; + wire _zz_206; + wire [3:0] _zz_207; + wire _zz_208; + wire _zz_209; + reg [31:0] _zz_210; + reg [31:0] _zz_211; + reg [31:0] _zz_212; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -145,11 +145,6 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_208; - wire _zz_209; - wire _zz_210; - wire _zz_211; - wire _zz_212; wire _zz_213; wire _zz_214; wire _zz_215; @@ -162,47 +157,47 @@ module VexRiscv ( wire _zz_222; wire _zz_223; wire _zz_224; - wire [1:0] _zz_225; + wire _zz_225; wire _zz_226; wire _zz_227; wire _zz_228; wire _zz_229; - wire _zz_230; + wire [1:0] _zz_230; wire _zz_231; wire _zz_232; wire _zz_233; wire _zz_234; wire _zz_235; - wire [1:0] _zz_236; + wire _zz_236; wire _zz_237; wire _zz_238; - wire [5:0] _zz_239; + wire _zz_239; wire _zz_240; - wire _zz_241; + wire [1:0] _zz_241; wire _zz_242; wire _zz_243; - wire _zz_244; + wire [5:0] _zz_244; wire _zz_245; - wire [1:0] _zz_246; + wire _zz_246; wire _zz_247; - wire [1:0] _zz_248; - wire [51:0] _zz_249; - wire [51:0] _zz_250; - wire [51:0] _zz_251; - wire [32:0] _zz_252; - wire [51:0] _zz_253; - wire [49:0] _zz_254; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire [1:0] _zz_251; + wire _zz_252; + wire [1:0] _zz_253; + wire [51:0] _zz_254; wire [51:0] _zz_255; - wire [49:0] _zz_256; - wire [51:0] _zz_257; - wire [32:0] _zz_258; - wire [31:0] _zz_259; - wire [32:0] _zz_260; - wire [0:0] _zz_261; - wire [0:0] _zz_262; - wire [0:0] _zz_263; - wire [0:0] _zz_264; - wire [0:0] _zz_265; + wire [51:0] _zz_256; + wire [32:0] _zz_257; + wire [51:0] _zz_258; + wire [49:0] _zz_259; + wire [51:0] _zz_260; + wire [49:0] _zz_261; + wire [51:0] _zz_262; + wire [32:0] _zz_263; + wire [31:0] _zz_264; + wire [32:0] _zz_265; wire [0:0] _zz_266; wire [0:0] _zz_267; wire [0:0] _zz_268; @@ -216,262 +211,267 @@ module VexRiscv ( wire [0:0] _zz_276; wire [0:0] _zz_277; wire [0:0] _zz_278; - wire [3:0] _zz_279; - wire [2:0] _zz_280; - wire [31:0] _zz_281; - wire [11:0] _zz_282; - wire [31:0] _zz_283; - wire [19:0] _zz_284; - wire [11:0] _zz_285; + wire [0:0] _zz_279; + wire [0:0] _zz_280; + wire [0:0] _zz_281; + wire [0:0] _zz_282; + wire [0:0] _zz_283; + wire [3:0] _zz_284; + wire [2:0] _zz_285; wire [31:0] _zz_286; - wire [31:0] _zz_287; - wire [19:0] _zz_288; - wire [11:0] _zz_289; - wire [2:0] _zz_290; - wire [2:0] _zz_291; - wire [0:0] _zz_292; - wire [2:0] _zz_293; - wire [4:0] _zz_294; - wire [11:0] _zz_295; - wire [11:0] _zz_296; - wire [31:0] _zz_297; - wire [31:0] _zz_298; - wire [31:0] _zz_299; - wire [31:0] _zz_300; - wire [31:0] _zz_301; + wire [11:0] _zz_287; + wire [31:0] _zz_288; + wire [19:0] _zz_289; + wire [11:0] _zz_290; + wire [31:0] _zz_291; + wire [31:0] _zz_292; + wire [19:0] _zz_293; + wire [11:0] _zz_294; + wire [2:0] _zz_295; + wire [2:0] _zz_296; + wire [0:0] _zz_297; + wire [2:0] _zz_298; + wire [4:0] _zz_299; + wire [11:0] _zz_300; + wire [11:0] _zz_301; wire [31:0] _zz_302; wire [31:0] _zz_303; - wire [11:0] _zz_304; - wire [19:0] _zz_305; - wire [11:0] _zz_306; + wire [31:0] _zz_304; + wire [31:0] _zz_305; + wire [31:0] _zz_306; wire [31:0] _zz_307; wire [31:0] _zz_308; - wire [31:0] _zz_309; - wire [11:0] _zz_310; - wire [19:0] _zz_311; - wire [11:0] _zz_312; - wire [2:0] _zz_313; - wire [1:0] _zz_314; - wire [1:0] _zz_315; - wire [65:0] _zz_316; - wire [65:0] _zz_317; - wire [31:0] _zz_318; - wire [31:0] _zz_319; - wire [0:0] _zz_320; - wire [5:0] _zz_321; - wire [32:0] _zz_322; + wire [11:0] _zz_309; + wire [19:0] _zz_310; + wire [11:0] _zz_311; + wire [31:0] _zz_312; + wire [31:0] _zz_313; + wire [31:0] _zz_314; + wire [11:0] _zz_315; + wire [19:0] _zz_316; + wire [11:0] _zz_317; + wire [2:0] _zz_318; + wire [1:0] _zz_319; + wire [1:0] _zz_320; + wire [65:0] _zz_321; + wire [65:0] _zz_322; wire [31:0] _zz_323; wire [31:0] _zz_324; - wire [32:0] _zz_325; - wire [32:0] _zz_326; + wire [0:0] _zz_325; + wire [5:0] _zz_326; wire [32:0] _zz_327; - wire [32:0] _zz_328; - wire [0:0] _zz_329; + wire [31:0] _zz_328; + wire [31:0] _zz_329; wire [32:0] _zz_330; - wire [0:0] _zz_331; + wire [32:0] _zz_331; wire [32:0] _zz_332; - wire [0:0] _zz_333; - wire [31:0] _zz_334; - wire [0:0] _zz_335; + wire [32:0] _zz_333; + wire [0:0] _zz_334; + wire [32:0] _zz_335; wire [0:0] _zz_336; - wire [0:0] _zz_337; + wire [32:0] _zz_337; wire [0:0] _zz_338; - wire [0:0] _zz_339; + wire [31:0] _zz_339; wire [0:0] _zz_340; wire [0:0] _zz_341; - wire [26:0] _zz_342; - wire _zz_343; - wire _zz_344; - wire [1:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; + wire [0:0] _zz_342; + wire [0:0] _zz_343; + wire [0:0] _zz_344; + wire [0:0] _zz_345; + wire [0:0] _zz_346; + wire [26:0] _zz_347; + wire _zz_348; wire _zz_349; - wire [0:0] _zz_350; - wire [13:0] _zz_351; + wire [1:0] _zz_350; + wire [31:0] _zz_351; wire [31:0] _zz_352; wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire _zz_355; - wire [0:0] _zz_356; - wire [7:0] _zz_357; + wire _zz_354; + wire [0:0] _zz_355; + wire [13:0] _zz_356; + wire [31:0] _zz_357; wire [31:0] _zz_358; wire [31:0] _zz_359; - wire [31:0] _zz_360; - wire _zz_361; - wire [0:0] _zz_362; - wire [1:0] _zz_363; - wire _zz_364; - wire _zz_365; + wire _zz_360; + wire [0:0] _zz_361; + wire [7:0] _zz_362; + wire [31:0] _zz_363; + wire [31:0] _zz_364; + wire [31:0] _zz_365; wire _zz_366; - wire [31:0] _zz_367; - wire [0:0] _zz_368; - wire [0:0] _zz_369; + wire [0:0] _zz_367; + wire [1:0] _zz_368; + wire _zz_369; wire _zz_370; - wire [0:0] _zz_371; - wire [26:0] _zz_372; - wire [31:0] _zz_373; - wire _zz_374; + wire _zz_371; + wire [31:0] _zz_372; + wire [0:0] _zz_373; + wire [0:0] _zz_374; wire _zz_375; - wire _zz_376; - wire [1:0] _zz_377; - wire [1:0] _zz_378; + wire [0:0] _zz_376; + wire [26:0] _zz_377; + wire [31:0] _zz_378; wire _zz_379; - wire [0:0] _zz_380; - wire [22:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire [31:0] _zz_384; - wire [31:0] _zz_385; - wire _zz_386; - wire _zz_387; - wire [1:0] _zz_388; - wire [1:0] _zz_389; - wire _zz_390; - wire [0:0] _zz_391; - wire [19:0] _zz_392; - wire [31:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire _zz_397; - wire [0:0] _zz_398; - wire [0:0] _zz_399; - wire _zz_400; - wire [0:0] _zz_401; - wire [0:0] _zz_402; - wire _zz_403; + wire _zz_380; + wire _zz_381; + wire [1:0] _zz_382; + wire [1:0] _zz_383; + wire _zz_384; + wire [0:0] _zz_385; + wire [22:0] _zz_386; + wire [31:0] _zz_387; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire _zz_391; + wire _zz_392; + wire [1:0] _zz_393; + wire [1:0] _zz_394; + wire _zz_395; + wire [0:0] _zz_396; + wire [19:0] _zz_397; + wire [31:0] _zz_398; + wire [31:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; + wire _zz_402; + wire [0:0] _zz_403; wire [0:0] _zz_404; - wire [16:0] _zz_405; - wire [31:0] _zz_406; - wire [31:0] _zz_407; - wire [31:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire [0:0] _zz_411; - wire [0:0] _zz_412; - wire [0:0] _zz_413; - wire [0:0] _zz_414; - wire _zz_415; + wire _zz_405; + wire [0:0] _zz_406; + wire [0:0] _zz_407; + wire _zz_408; + wire [0:0] _zz_409; + wire [16:0] _zz_410; + wire [31:0] _zz_411; + wire [31:0] _zz_412; + wire [31:0] _zz_413; + wire [31:0] _zz_414; + wire [31:0] _zz_415; wire [0:0] _zz_416; - wire [13:0] _zz_417; - wire [31:0] _zz_418; - wire [31:0] _zz_419; - wire [31:0] _zz_420; - wire _zz_421; - wire _zz_422; - wire [0:0] _zz_423; - wire [3:0] _zz_424; - wire [0:0] _zz_425; - wire [0:0] _zz_426; + wire [0:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire _zz_420; + wire [0:0] _zz_421; + wire [13:0] _zz_422; + wire [31:0] _zz_423; + wire [31:0] _zz_424; + wire [31:0] _zz_425; + wire _zz_426; wire _zz_427; wire [0:0] _zz_428; - wire [10:0] _zz_429; - wire [31:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire _zz_433; - wire [0:0] _zz_434; - wire [0:0] _zz_435; + wire [3:0] _zz_429; + wire [0:0] _zz_430; + wire [0:0] _zz_431; + wire _zz_432; + wire [0:0] _zz_433; + wire [10:0] _zz_434; + wire [31:0] _zz_435; wire [31:0] _zz_436; - wire _zz_437; - wire [0:0] _zz_438; - wire [2:0] _zz_439; + wire [31:0] _zz_437; + wire _zz_438; + wire [0:0] _zz_439; wire [0:0] _zz_440; - wire [3:0] _zz_441; - wire [5:0] _zz_442; - wire [5:0] _zz_443; - wire _zz_444; + wire [31:0] _zz_441; + wire _zz_442; + wire [0:0] _zz_443; + wire [2:0] _zz_444; wire [0:0] _zz_445; - wire [7:0] _zz_446; - wire [31:0] _zz_447; - wire [31:0] _zz_448; - wire [31:0] _zz_449; - wire [31:0] _zz_450; - wire [31:0] _zz_451; + wire [3:0] _zz_446; + wire [5:0] _zz_447; + wire [5:0] _zz_448; + wire _zz_449; + wire [0:0] _zz_450; + wire [7:0] _zz_451; wire [31:0] _zz_452; - wire _zz_453; - wire [0:0] _zz_454; - wire [0:0] _zz_455; - wire _zz_456; - wire [0:0] _zz_457; - wire [1:0] _zz_458; + wire [31:0] _zz_453; + wire [31:0] _zz_454; + wire [31:0] _zz_455; + wire [31:0] _zz_456; + wire [31:0] _zz_457; + wire _zz_458; wire [0:0] _zz_459; - wire [3:0] _zz_460; - wire [0:0] _zz_461; + wire [0:0] _zz_460; + wire _zz_461; wire [0:0] _zz_462; wire [1:0] _zz_463; - wire [1:0] _zz_464; - wire _zz_465; + wire [0:0] _zz_464; + wire [3:0] _zz_465; wire [0:0] _zz_466; - wire [5:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire [31:0] _zz_471; - wire [31:0] _zz_472; + wire [0:0] _zz_467; + wire [1:0] _zz_468; + wire [1:0] _zz_469; + wire _zz_470; + wire [0:0] _zz_471; + wire [5:0] _zz_472; wire [31:0] _zz_473; wire [31:0] _zz_474; wire [31:0] _zz_475; - wire _zz_476; - wire _zz_477; + wire [31:0] _zz_476; + wire [31:0] _zz_477; wire [31:0] _zz_478; wire [31:0] _zz_479; - wire _zz_480; - wire [0:0] _zz_481; - wire [1:0] _zz_482; + wire [31:0] _zz_480; + wire _zz_481; + wire _zz_482; wire [31:0] _zz_483; wire [31:0] _zz_484; wire _zz_485; - wire _zz_486; - wire [0:0] _zz_487; - wire [0:0] _zz_488; - wire _zz_489; - wire [0:0] _zz_490; - wire [3:0] _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; - wire [31:0] _zz_496; - wire _zz_497; - wire _zz_498; + wire [0:0] _zz_486; + wire [1:0] _zz_487; + wire [31:0] _zz_488; + wire [31:0] _zz_489; + wire _zz_490; + wire _zz_491; + wire [0:0] _zz_492; + wire [0:0] _zz_493; + wire _zz_494; + wire [0:0] _zz_495; + wire [3:0] _zz_496; + wire [31:0] _zz_497; + wire [31:0] _zz_498; wire [31:0] _zz_499; wire [31:0] _zz_500; wire [31:0] _zz_501; - wire [31:0] _zz_502; - wire [0:0] _zz_503; - wire [2:0] _zz_504; - wire [0:0] _zz_505; - wire [0:0] _zz_506; - wire _zz_507; + wire _zz_502; + wire _zz_503; + wire [31:0] _zz_504; + wire [31:0] _zz_505; + wire [31:0] _zz_506; + wire [31:0] _zz_507; wire [0:0] _zz_508; - wire [1:0] _zz_509; - wire [31:0] _zz_510; - wire [31:0] _zz_511; - wire [31:0] _zz_512; - wire _zz_513; - wire _zz_514; + wire [2:0] _zz_509; + wire [0:0] _zz_510; + wire [0:0] _zz_511; + wire _zz_512; + wire [0:0] _zz_513; + wire [1:0] _zz_514; wire [31:0] _zz_515; - wire _zz_516; - wire [0:0] _zz_517; - wire [0:0] _zz_518; - wire [0:0] _zz_519; - wire [0:0] _zz_520; - wire [1:0] _zz_521; - wire [1:0] _zz_522; + wire [31:0] _zz_516; + wire [31:0] _zz_517; + wire _zz_518; + wire _zz_519; + wire [31:0] _zz_520; + wire _zz_521; + wire [0:0] _zz_522; wire [0:0] _zz_523; wire [0:0] _zz_524; - wire [31:0] _zz_525; - wire [31:0] _zz_526; - wire [31:0] _zz_527; - wire [31:0] _zz_528; - wire [31:0] _zz_529; + wire [0:0] _zz_525; + wire [1:0] _zz_526; + wire [1:0] _zz_527; + wire [0:0] _zz_528; + wire [0:0] _zz_529; wire [31:0] _zz_530; - wire _zz_531; - wire _zz_532; - wire _zz_533; + wire [31:0] _zz_531; + wire [31:0] _zz_532; + wire [31:0] _zz_533; wire [31:0] _zz_534; + wire [31:0] _zz_535; + wire _zz_536; + wire _zz_537; + wire _zz_538; + wire [31:0] _zz_539; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -954,42 +954,37 @@ module VexRiscv ( reg [31:0] _zz_107; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_108; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_109; - wire _zz_110; - wire _zz_111; - wire _zz_112; - wire _zz_113; + reg _zz_109; + reg _zz_110; + reg _zz_111; + reg [4:0] _zz_112; + reg [31:0] _zz_113; wire _zz_114; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_115; - reg _zz_116; - reg _zz_117; + wire _zz_115; + wire _zz_116; + wire _zz_117; wire _zz_118; - reg [19:0] _zz_119; - wire _zz_120; - reg [10:0] _zz_121; - wire _zz_122; - reg [18:0] _zz_123; - reg _zz_124; + wire _zz_119; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_120; + reg _zz_121; + reg _zz_122; + wire _zz_123; + reg [19:0] _zz_124; + wire _zz_125; + reg [10:0] _zz_126; + wire _zz_127; + reg [18:0] _zz_128; + reg _zz_129; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_125; - reg [19:0] _zz_126; - wire _zz_127; - reg [10:0] _zz_128; - wire _zz_129; - reg [18:0] _zz_130; + wire _zz_130; + reg [19:0] _zz_131; + wire _zz_132; + reg [10:0] _zz_133; + wire _zz_134; + reg [18:0] _zz_135; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1011,9 +1006,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_131; - wire _zz_132; - wire _zz_133; + wire _zz_136; + wire _zz_137; + wire _zz_138; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1026,8 +1021,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_134; - wire _zz_135; + wire [1:0] _zz_139; + wire _zz_140; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1080,18 +1075,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_136; + wire [31:0] _zz_141; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_137; - wire _zz_138; - wire _zz_139; - reg [32:0] _zz_140; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_141; wire [31:0] _zz_142; + wire _zz_143; + wire _zz_144; + reg [32:0] _zz_145; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_146; + wire [31:0] _zz_147; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1101,7 +1096,7 @@ module VexRiscv ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_143; + reg _zz_148; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1167,7 +1162,7 @@ module VexRiscv ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_144; + reg [2:0] _zz_149; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; @@ -1192,11 +1187,6 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3202; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_145; - reg [31:0] _zz_146; - reg [31:0] _zz_147; - reg [31:0] _zz_148; - reg [31:0] _zz_149; reg [31:0] _zz_150; reg [31:0] _zz_151; reg [31:0] _zz_152; @@ -1215,16 +1205,21 @@ module VexRiscv ( reg [31:0] _zz_165; reg [31:0] _zz_166; reg [31:0] _zz_167; - reg [2:0] _zz_168; - reg _zz_169; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [2:0] _zz_173; + reg _zz_174; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_170; - wire _zz_171; - wire _zz_172; - wire _zz_173; - wire _zz_174; - wire _zz_175; - reg _zz_176; + reg [2:0] _zz_175; + wire _zz_176; + wire _zz_177; + wire _zz_178; + wire _zz_179; + wire _zz_180; + reg _zz_181; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] _zz_1_string; @@ -1309,342 +1304,342 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_208 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_209 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_210 = 1'b1; - assign _zz_211 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_212 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_213 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_214 = ((_zz_182 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_215 = ((_zz_182 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_216 = ((_zz_182 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_217 = ((_zz_182 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_218 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_219 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_220 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_221 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_222 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_223 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_224 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_225 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_226 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_227 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_228 = (1'b0 || (! 1'b1)); - assign _zz_229 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_230 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_231 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_232 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_233 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_234 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_235 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_236 = execute_INSTRUCTION[13 : 12]; - assign _zz_237 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_238 = (! memory_arbitration_isStuck); - assign _zz_239 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_240 = (iBus_cmd_valid || (_zz_168 != 3'b000)); - assign _zz_241 = (_zz_204 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_242 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_243 = ((_zz_131 && 1'b1) && (! 1'b0)); - assign _zz_244 = ((_zz_132 && 1'b1) && (! 1'b0)); - assign _zz_245 = ((_zz_133 && 1'b1) && (! 1'b0)); - assign _zz_246 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_247 = execute_INSTRUCTION[13]; - assign _zz_248 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_249 = ($signed(_zz_250) + $signed(_zz_255)); - assign _zz_250 = ($signed(_zz_251) + $signed(_zz_253)); - assign _zz_251 = 52'h0; - assign _zz_252 = {1'b0,memory_MUL_LL}; - assign _zz_253 = {{19{_zz_252[32]}}, _zz_252}; - assign _zz_254 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_255 = {{2{_zz_254[49]}}, _zz_254}; - assign _zz_256 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_257 = {{2{_zz_256[49]}}, _zz_256}; - assign _zz_258 = ($signed(_zz_260) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_259 = _zz_258[31 : 0]; - assign _zz_260 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_261 = _zz_87[31 : 31]; - assign _zz_262 = _zz_87[30 : 30]; - assign _zz_263 = _zz_87[29 : 29]; - assign _zz_264 = _zz_87[28 : 28]; - assign _zz_265 = _zz_87[25 : 25]; - assign _zz_266 = _zz_87[17 : 17]; - assign _zz_267 = _zz_87[16 : 16]; - assign _zz_268 = _zz_87[13 : 13]; - assign _zz_269 = _zz_87[12 : 12]; - assign _zz_270 = _zz_87[11 : 11]; - assign _zz_271 = _zz_87[32 : 32]; - assign _zz_272 = _zz_87[15 : 15]; - assign _zz_273 = _zz_87[5 : 5]; - assign _zz_274 = _zz_87[3 : 3]; - assign _zz_275 = _zz_87[20 : 20]; - assign _zz_276 = _zz_87[10 : 10]; - assign _zz_277 = _zz_87[4 : 4]; - assign _zz_278 = _zz_87[0 : 0]; - assign _zz_279 = (_zz_55 - 4'b0001); - assign _zz_280 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_281 = {29'd0, _zz_280}; - assign _zz_282 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_283 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_284 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_285 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_286 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_287 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_288 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_289 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_290 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_291 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_292 = execute_SRC_LESS; - assign _zz_293 = 3'b100; - assign _zz_294 = execute_INSTRUCTION[19 : 15]; - assign _zz_295 = execute_INSTRUCTION[31 : 20]; - assign _zz_296 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_297 = ($signed(_zz_298) + $signed(_zz_301)); - assign _zz_298 = ($signed(_zz_299) + $signed(_zz_300)); - assign _zz_299 = execute_SRC1; - assign _zz_300 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_301 = (execute_SRC_USE_SUB_LESS ? _zz_302 : _zz_303); - assign _zz_302 = 32'h00000001; - assign _zz_303 = 32'h0; - assign _zz_304 = execute_INSTRUCTION[31 : 20]; - assign _zz_305 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_306 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_307 = {_zz_119,execute_INSTRUCTION[31 : 20]}; - assign _zz_308 = {{_zz_121,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_309 = {{_zz_123,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_310 = execute_INSTRUCTION[31 : 20]; - assign _zz_311 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_312 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_313 = 3'b100; - assign _zz_314 = (_zz_134 & (~ _zz_315)); - assign _zz_315 = (_zz_134 - 2'b01); - assign _zz_316 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_317 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_318 = writeBack_MUL_LOW[31 : 0]; - assign _zz_319 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_320 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_321 = {5'd0, _zz_320}; - assign _zz_322 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_323 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_324 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_325 = {_zz_136,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_326 = _zz_327; - assign _zz_327 = _zz_328; - assign _zz_328 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_137) : _zz_137)} + _zz_330); - assign _zz_329 = memory_DivPlugin_div_needRevert; - assign _zz_330 = {32'd0, _zz_329}; - assign _zz_331 = _zz_139; - assign _zz_332 = {32'd0, _zz_331}; - assign _zz_333 = _zz_138; - assign _zz_334 = {31'd0, _zz_333}; - assign _zz_335 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_336 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_337 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_338 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_339 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_340 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_341 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_342 = (iBus_cmd_payload_address >>> 5); - assign _zz_343 = 1'b1; - assign _zz_344 = 1'b1; - assign _zz_345 = {_zz_59,_zz_58}; - assign _zz_346 = 32'h0000107f; - assign _zz_347 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_348 = 32'h00002073; - assign _zz_349 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_350 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_351 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_352) == 32'h00000003),{(_zz_353 == _zz_354),{_zz_355,{_zz_356,_zz_357}}}}}}; - assign _zz_352 = 32'h0000505f; - assign _zz_353 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_354 = 32'h00000063; - assign _zz_355 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_356 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_357 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_358) == 32'h00001013),{(_zz_359 == _zz_360),{_zz_361,{_zz_362,_zz_363}}}}}}; - assign _zz_358 = 32'hfc00307f; - assign _zz_359 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_360 = 32'h00005033; - assign _zz_361 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_362 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_363 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz_364 = decode_INSTRUCTION[31]; - assign _zz_365 = decode_INSTRUCTION[31]; - assign _zz_366 = decode_INSTRUCTION[7]; - assign _zz_367 = 32'h10103050; - assign _zz_368 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_369 = 1'b0; - assign _zz_370 = (((decode_INSTRUCTION & _zz_373) == 32'h02000030) != 1'b0); - assign _zz_371 = ({_zz_374,_zz_375} != 2'b00); - assign _zz_372 = {(_zz_376 != 1'b0),{(_zz_377 != _zz_378),{_zz_379,{_zz_380,_zz_381}}}}; - assign _zz_373 = 32'h02004074; - assign _zz_374 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); - assign _zz_375 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); - assign _zz_376 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); - assign _zz_377 = {(_zz_382 == _zz_383),(_zz_384 == _zz_385)}; - assign _zz_378 = 2'b00; - assign _zz_379 = ({_zz_90,_zz_386} != 2'b00); - assign _zz_380 = (_zz_387 != 1'b0); - assign _zz_381 = {(_zz_388 != _zz_389),{_zz_390,{_zz_391,_zz_392}}}; - assign _zz_382 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_383 = 32'h00001050; - assign _zz_384 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_385 = 32'h00002050; - assign _zz_386 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_387 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_388 = {(_zz_393 == _zz_394),(_zz_395 == _zz_396)}; - assign _zz_389 = 2'b00; - assign _zz_390 = ({_zz_397,{_zz_398,_zz_399}} != 3'b000); - assign _zz_391 = (_zz_400 != 1'b0); - assign _zz_392 = {(_zz_401 != _zz_402),{_zz_403,{_zz_404,_zz_405}}}; - assign _zz_393 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_394 = 32'h00005010; - assign _zz_395 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_396 = 32'h00005020; - assign _zz_397 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_398 = ((decode_INSTRUCTION & _zz_406) == 32'h00001010); - assign _zz_399 = ((decode_INSTRUCTION & _zz_407) == 32'h00001010); - assign _zz_400 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_401 = ((decode_INSTRUCTION & _zz_408) == 32'h00001000); - assign _zz_402 = 1'b0; - assign _zz_403 = ((_zz_409 == _zz_410) != 1'b0); - assign _zz_404 = ({_zz_411,_zz_412} != 2'b00); - assign _zz_405 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; - assign _zz_406 = 32'h00007034; - assign _zz_407 = 32'h02007054; - assign _zz_408 = 32'h00001000; - assign _zz_409 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_410 = 32'h00002000; - assign _zz_411 = ((decode_INSTRUCTION & _zz_418) == 32'h00002000); - assign _zz_412 = ((decode_INSTRUCTION & _zz_419) == 32'h00001000); - assign _zz_413 = ((decode_INSTRUCTION & _zz_420) == 32'h00004008); - assign _zz_414 = 1'b0; - assign _zz_415 = ({_zz_421,_zz_422} != 2'b00); - assign _zz_416 = ({_zz_423,_zz_424} != 5'h0); - assign _zz_417 = {(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}; - assign _zz_418 = 32'h00002010; - assign _zz_419 = 32'h00005000; - assign _zz_420 = 32'h00004048; - assign _zz_421 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); - assign _zz_422 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h00002040); - assign _zz_424 = {(_zz_431 == _zz_432),{_zz_433,{_zz_434,_zz_435}}}; - assign _zz_425 = ((decode_INSTRUCTION & _zz_436) == 32'h00000020); - assign _zz_426 = 1'b0; - assign _zz_427 = ({_zz_437,{_zz_438,_zz_439}} != 5'h0); - assign _zz_428 = ({_zz_440,_zz_441} != 5'h0); - assign _zz_429 = {(_zz_442 != _zz_443),{_zz_444,{_zz_445,_zz_446}}}; - assign _zz_430 = 32'h00002040; - assign _zz_431 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_432 = 32'h00001040; - assign _zz_433 = ((decode_INSTRUCTION & _zz_447) == 32'h00000040); - assign _zz_434 = (_zz_448 == _zz_449); - assign _zz_435 = (_zz_450 == _zz_451); - assign _zz_436 = 32'h00000020; - assign _zz_437 = ((decode_INSTRUCTION & _zz_452) == 32'h00000040); - assign _zz_438 = _zz_89; - assign _zz_439 = {_zz_453,{_zz_454,_zz_455}}; - assign _zz_440 = _zz_89; - assign _zz_441 = {_zz_456,{_zz_457,_zz_458}}; - assign _zz_442 = {_zz_90,{_zz_459,_zz_460}}; - assign _zz_443 = 6'h0; - assign _zz_444 = ({_zz_461,_zz_462} != 2'b00); - assign _zz_445 = (_zz_463 != _zz_464); - assign _zz_446 = {_zz_465,{_zz_466,_zz_467}}; - assign _zz_447 = 32'h00100040; - assign _zz_448 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_449 = 32'h00000040; - assign _zz_450 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_451 = 32'h0; - assign _zz_452 = 32'h00000040; - assign _zz_453 = ((decode_INSTRUCTION & _zz_468) == 32'h00004020); - assign _zz_454 = (_zz_469 == _zz_470); - assign _zz_455 = (_zz_471 == _zz_472); - assign _zz_456 = ((decode_INSTRUCTION & _zz_473) == 32'h00002010); - assign _zz_457 = (_zz_474 == _zz_475); - assign _zz_458 = {_zz_476,_zz_477}; - assign _zz_459 = (_zz_478 == _zz_479); - assign _zz_460 = {_zz_480,{_zz_481,_zz_482}}; - assign _zz_461 = _zz_89; - assign _zz_462 = (_zz_483 == _zz_484); - assign _zz_463 = {_zz_89,_zz_485}; - assign _zz_464 = 2'b00; - assign _zz_465 = (_zz_486 != 1'b0); - assign _zz_466 = (_zz_487 != _zz_488); - assign _zz_467 = {_zz_489,{_zz_490,_zz_491}}; - assign _zz_468 = 32'h00004020; - assign _zz_469 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_470 = 32'h00000010; - assign _zz_471 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_472 = 32'h00000020; - assign _zz_473 = 32'h00002030; - assign _zz_474 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_213 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_214 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_215 = 1'b1; + assign _zz_216 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_217 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_218 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_219 = ((_zz_187 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_220 = ((_zz_187 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_221 = ((_zz_187 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_222 = ((_zz_187 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_223 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_224 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_225 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_226 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_227 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_228 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_229 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_230 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_232 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_233 = (1'b0 || (! 1'b1)); + assign _zz_234 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_235 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_236 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_237 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_238 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_239 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_240 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_241 = execute_INSTRUCTION[13 : 12]; + assign _zz_242 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_243 = (! memory_arbitration_isStuck); + assign _zz_244 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_245 = (iBus_cmd_valid || (_zz_173 != 3'b000)); + assign _zz_246 = (_zz_209 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_247 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_248 = ((_zz_136 && 1'b1) && (! 1'b0)); + assign _zz_249 = ((_zz_137 && 1'b1) && (! 1'b0)); + assign _zz_250 = ((_zz_138 && 1'b1) && (! 1'b0)); + assign _zz_251 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_252 = execute_INSTRUCTION[13]; + assign _zz_253 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_254 = ($signed(_zz_255) + $signed(_zz_260)); + assign _zz_255 = ($signed(_zz_256) + $signed(_zz_258)); + assign _zz_256 = 52'h0; + assign _zz_257 = {1'b0,memory_MUL_LL}; + assign _zz_258 = {{19{_zz_257[32]}}, _zz_257}; + assign _zz_259 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_260 = {{2{_zz_259[49]}}, _zz_259}; + assign _zz_261 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_262 = {{2{_zz_261[49]}}, _zz_261}; + assign _zz_263 = ($signed(_zz_265) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_264 = _zz_263[31 : 0]; + assign _zz_265 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_266 = _zz_87[31 : 31]; + assign _zz_267 = _zz_87[30 : 30]; + assign _zz_268 = _zz_87[29 : 29]; + assign _zz_269 = _zz_87[28 : 28]; + assign _zz_270 = _zz_87[25 : 25]; + assign _zz_271 = _zz_87[17 : 17]; + assign _zz_272 = _zz_87[16 : 16]; + assign _zz_273 = _zz_87[13 : 13]; + assign _zz_274 = _zz_87[12 : 12]; + assign _zz_275 = _zz_87[11 : 11]; + assign _zz_276 = _zz_87[32 : 32]; + assign _zz_277 = _zz_87[15 : 15]; + assign _zz_278 = _zz_87[5 : 5]; + assign _zz_279 = _zz_87[3 : 3]; + assign _zz_280 = _zz_87[20 : 20]; + assign _zz_281 = _zz_87[10 : 10]; + assign _zz_282 = _zz_87[4 : 4]; + assign _zz_283 = _zz_87[0 : 0]; + assign _zz_284 = (_zz_55 - 4'b0001); + assign _zz_285 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_286 = {29'd0, _zz_285}; + assign _zz_287 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_288 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_289 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_290 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_291 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_292 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_293 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_294 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_295 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_296 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_297 = execute_SRC_LESS; + assign _zz_298 = 3'b100; + assign _zz_299 = execute_INSTRUCTION[19 : 15]; + assign _zz_300 = execute_INSTRUCTION[31 : 20]; + assign _zz_301 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_302 = ($signed(_zz_303) + $signed(_zz_306)); + assign _zz_303 = ($signed(_zz_304) + $signed(_zz_305)); + assign _zz_304 = execute_SRC1; + assign _zz_305 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_306 = (execute_SRC_USE_SUB_LESS ? _zz_307 : _zz_308); + assign _zz_307 = 32'h00000001; + assign _zz_308 = 32'h0; + assign _zz_309 = execute_INSTRUCTION[31 : 20]; + assign _zz_310 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_311 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_312 = {_zz_124,execute_INSTRUCTION[31 : 20]}; + assign _zz_313 = {{_zz_126,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_314 = {{_zz_128,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_315 = execute_INSTRUCTION[31 : 20]; + assign _zz_316 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_317 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_318 = 3'b100; + assign _zz_319 = (_zz_139 & (~ _zz_320)); + assign _zz_320 = (_zz_139 - 2'b01); + assign _zz_321 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_322 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_323 = writeBack_MUL_LOW[31 : 0]; + assign _zz_324 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_325 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_326 = {5'd0, _zz_325}; + assign _zz_327 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_328 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_329 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_330 = {_zz_141,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_331 = _zz_332; + assign _zz_332 = _zz_333; + assign _zz_333 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_142) : _zz_142)} + _zz_335); + assign _zz_334 = memory_DivPlugin_div_needRevert; + assign _zz_335 = {32'd0, _zz_334}; + assign _zz_336 = _zz_144; + assign _zz_337 = {32'd0, _zz_336}; + assign _zz_338 = _zz_143; + assign _zz_339 = {31'd0, _zz_338}; + assign _zz_340 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_341 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_342 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_343 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_344 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_345 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_346 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_347 = (iBus_cmd_payload_address >>> 5); + assign _zz_348 = 1'b1; + assign _zz_349 = 1'b1; + assign _zz_350 = {_zz_59,_zz_58}; + assign _zz_351 = 32'h0000107f; + assign _zz_352 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_353 = 32'h00002073; + assign _zz_354 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_355 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_356 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_357) == 32'h00000003),{(_zz_358 == _zz_359),{_zz_360,{_zz_361,_zz_362}}}}}}; + assign _zz_357 = 32'h0000505f; + assign _zz_358 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_359 = 32'h00000063; + assign _zz_360 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_361 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_362 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_363) == 32'h00001013),{(_zz_364 == _zz_365),{_zz_366,{_zz_367,_zz_368}}}}}}; + assign _zz_363 = 32'hfc00307f; + assign _zz_364 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_365 = 32'h00005033; + assign _zz_366 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_367 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_368 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz_369 = decode_INSTRUCTION[31]; + assign _zz_370 = decode_INSTRUCTION[31]; + assign _zz_371 = decode_INSTRUCTION[7]; + assign _zz_372 = 32'h10103050; + assign _zz_373 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_374 = 1'b0; + assign _zz_375 = (((decode_INSTRUCTION & _zz_378) == 32'h02000030) != 1'b0); + assign _zz_376 = ({_zz_379,_zz_380} != 2'b00); + assign _zz_377 = {(_zz_381 != 1'b0),{(_zz_382 != _zz_383),{_zz_384,{_zz_385,_zz_386}}}}; + assign _zz_378 = 32'h02004074; + assign _zz_379 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); + assign _zz_380 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz_381 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz_382 = {(_zz_387 == _zz_388),(_zz_389 == _zz_390)}; + assign _zz_383 = 2'b00; + assign _zz_384 = ({_zz_90,_zz_391} != 2'b00); + assign _zz_385 = (_zz_392 != 1'b0); + assign _zz_386 = {(_zz_393 != _zz_394),{_zz_395,{_zz_396,_zz_397}}}; + assign _zz_387 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_388 = 32'h00001050; + assign _zz_389 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_390 = 32'h00002050; + assign _zz_391 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_392 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_393 = {(_zz_398 == _zz_399),(_zz_400 == _zz_401)}; + assign _zz_394 = 2'b00; + assign _zz_395 = ({_zz_402,{_zz_403,_zz_404}} != 3'b000); + assign _zz_396 = (_zz_405 != 1'b0); + assign _zz_397 = {(_zz_406 != _zz_407),{_zz_408,{_zz_409,_zz_410}}}; + assign _zz_398 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_399 = 32'h00005010; + assign _zz_400 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_401 = 32'h00005020; + assign _zz_402 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_403 = ((decode_INSTRUCTION & _zz_411) == 32'h00001010); + assign _zz_404 = ((decode_INSTRUCTION & _zz_412) == 32'h00001010); + assign _zz_405 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_406 = ((decode_INSTRUCTION & _zz_413) == 32'h00001000); + assign _zz_407 = 1'b0; + assign _zz_408 = ((_zz_414 == _zz_415) != 1'b0); + assign _zz_409 = ({_zz_416,_zz_417} != 2'b00); + assign _zz_410 = {(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}; + assign _zz_411 = 32'h00007034; + assign _zz_412 = 32'h02007054; + assign _zz_413 = 32'h00001000; + assign _zz_414 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_415 = 32'h00002000; + assign _zz_416 = ((decode_INSTRUCTION & _zz_423) == 32'h00002000); + assign _zz_417 = ((decode_INSTRUCTION & _zz_424) == 32'h00001000); + assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00004008); + assign _zz_419 = 1'b0; + assign _zz_420 = ({_zz_426,_zz_427} != 2'b00); + assign _zz_421 = ({_zz_428,_zz_429} != 5'h0); + assign _zz_422 = {(_zz_430 != _zz_431),{_zz_432,{_zz_433,_zz_434}}}; + assign _zz_423 = 32'h00002010; + assign _zz_424 = 32'h00005000; + assign _zz_425 = 32'h00004048; + assign _zz_426 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_427 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_428 = ((decode_INSTRUCTION & _zz_435) == 32'h00002040); + assign _zz_429 = {(_zz_436 == _zz_437),{_zz_438,{_zz_439,_zz_440}}}; + assign _zz_430 = ((decode_INSTRUCTION & _zz_441) == 32'h00000020); + assign _zz_431 = 1'b0; + assign _zz_432 = ({_zz_442,{_zz_443,_zz_444}} != 5'h0); + assign _zz_433 = ({_zz_445,_zz_446} != 5'h0); + assign _zz_434 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; + assign _zz_435 = 32'h00002040; + assign _zz_436 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_437 = 32'h00001040; + assign _zz_438 = ((decode_INSTRUCTION & _zz_452) == 32'h00000040); + assign _zz_439 = (_zz_453 == _zz_454); + assign _zz_440 = (_zz_455 == _zz_456); + assign _zz_441 = 32'h00000020; + assign _zz_442 = ((decode_INSTRUCTION & _zz_457) == 32'h00000040); + assign _zz_443 = _zz_89; + assign _zz_444 = {_zz_458,{_zz_459,_zz_460}}; + assign _zz_445 = _zz_89; + assign _zz_446 = {_zz_461,{_zz_462,_zz_463}}; + assign _zz_447 = {_zz_90,{_zz_464,_zz_465}}; + assign _zz_448 = 6'h0; + assign _zz_449 = ({_zz_466,_zz_467} != 2'b00); + assign _zz_450 = (_zz_468 != _zz_469); + assign _zz_451 = {_zz_470,{_zz_471,_zz_472}}; + assign _zz_452 = 32'h00100040; + assign _zz_453 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_454 = 32'h00000040; + assign _zz_455 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_456 = 32'h0; + assign _zz_457 = 32'h00000040; + assign _zz_458 = ((decode_INSTRUCTION & _zz_473) == 32'h00004020); + assign _zz_459 = (_zz_474 == _zz_475); + assign _zz_460 = (_zz_476 == _zz_477); + assign _zz_461 = ((decode_INSTRUCTION & _zz_478) == 32'h00002010); + assign _zz_462 = (_zz_479 == _zz_480); + assign _zz_463 = {_zz_481,_zz_482}; + assign _zz_464 = (_zz_483 == _zz_484); + assign _zz_465 = {_zz_485,{_zz_486,_zz_487}}; + assign _zz_466 = _zz_89; + assign _zz_467 = (_zz_488 == _zz_489); + assign _zz_468 = {_zz_89,_zz_490}; + assign _zz_469 = 2'b00; + assign _zz_470 = (_zz_491 != 1'b0); + assign _zz_471 = (_zz_492 != _zz_493); + assign _zz_472 = {_zz_494,{_zz_495,_zz_496}}; + assign _zz_473 = 32'h00004020; + assign _zz_474 = (decode_INSTRUCTION & 32'h00000030); assign _zz_475 = 32'h00000010; - assign _zz_476 = ((decode_INSTRUCTION & _zz_492) == 32'h00002020); - assign _zz_477 = ((decode_INSTRUCTION & _zz_493) == 32'h00000020); - assign _zz_478 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_479 = 32'h00001010; - assign _zz_480 = ((decode_INSTRUCTION & _zz_494) == 32'h00002010); - assign _zz_481 = (_zz_495 == _zz_496); - assign _zz_482 = {_zz_497,_zz_498}; - assign _zz_483 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_484 = 32'h00000020; - assign _zz_485 = ((decode_INSTRUCTION & _zz_499) == 32'h0); - assign _zz_486 = ((decode_INSTRUCTION & _zz_500) == 32'h00004010); - assign _zz_487 = (_zz_501 == _zz_502); - assign _zz_488 = 1'b0; - assign _zz_489 = ({_zz_503,_zz_504} != 4'b0000); - assign _zz_490 = (_zz_505 != _zz_506); - assign _zz_491 = {_zz_507,{_zz_508,_zz_509}}; - assign _zz_492 = 32'h02002060; - assign _zz_493 = 32'h02003020; - assign _zz_494 = 32'h00002010; - assign _zz_495 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_496 = 32'h00000010; - assign _zz_497 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_498 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); - assign _zz_499 = 32'h00000020; - assign _zz_500 = 32'h00004014; - assign _zz_501 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_502 = 32'h00002010; - assign _zz_503 = ((decode_INSTRUCTION & _zz_510) == 32'h0); - assign _zz_504 = {(_zz_511 == _zz_512),{_zz_513,_zz_514}}; - assign _zz_505 = ((decode_INSTRUCTION & _zz_515) == 32'h0); - assign _zz_506 = 1'b0; - assign _zz_507 = ({_zz_516,{_zz_517,_zz_518}} != 3'b000); - assign _zz_508 = ({_zz_519,_zz_520} != 2'b00); - assign _zz_509 = {(_zz_521 != _zz_522),(_zz_523 != _zz_524)}; - assign _zz_510 = 32'h00000044; - assign _zz_511 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_512 = 32'h0; - assign _zz_513 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_514 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_515 = 32'h00000058; - assign _zz_516 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_517 = ((decode_INSTRUCTION & _zz_525) == 32'h00002010); - assign _zz_518 = ((decode_INSTRUCTION & _zz_526) == 32'h40000030); - assign _zz_519 = ((decode_INSTRUCTION & _zz_527) == 32'h00000004); - assign _zz_520 = _zz_88; - assign _zz_521 = {(_zz_528 == _zz_529),_zz_88}; - assign _zz_522 = 2'b00; - assign _zz_523 = ((decode_INSTRUCTION & _zz_530) == 32'h00001008); - assign _zz_524 = 1'b0; - assign _zz_525 = 32'h00002014; - assign _zz_526 = 32'h40000034; - assign _zz_527 = 32'h00000014; - assign _zz_528 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_529 = 32'h00000004; - assign _zz_530 = 32'h00005048; - assign _zz_531 = execute_INSTRUCTION[31]; - assign _zz_532 = execute_INSTRUCTION[31]; - assign _zz_533 = execute_INSTRUCTION[7]; - assign _zz_534 = 32'h0; + assign _zz_476 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_477 = 32'h00000020; + assign _zz_478 = 32'h00002030; + assign _zz_479 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_480 = 32'h00000010; + assign _zz_481 = ((decode_INSTRUCTION & _zz_497) == 32'h00002020); + assign _zz_482 = ((decode_INSTRUCTION & _zz_498) == 32'h00000020); + assign _zz_483 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_484 = 32'h00001010; + assign _zz_485 = ((decode_INSTRUCTION & _zz_499) == 32'h00002010); + assign _zz_486 = (_zz_500 == _zz_501); + assign _zz_487 = {_zz_502,_zz_503}; + assign _zz_488 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_489 = 32'h00000020; + assign _zz_490 = ((decode_INSTRUCTION & _zz_504) == 32'h0); + assign _zz_491 = ((decode_INSTRUCTION & _zz_505) == 32'h00004010); + assign _zz_492 = (_zz_506 == _zz_507); + assign _zz_493 = 1'b0; + assign _zz_494 = ({_zz_508,_zz_509} != 4'b0000); + assign _zz_495 = (_zz_510 != _zz_511); + assign _zz_496 = {_zz_512,{_zz_513,_zz_514}}; + assign _zz_497 = 32'h02002060; + assign _zz_498 = 32'h02003020; + assign _zz_499 = 32'h00002010; + assign _zz_500 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_501 = 32'h00000010; + assign _zz_502 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_503 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_504 = 32'h00000020; + assign _zz_505 = 32'h00004014; + assign _zz_506 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_507 = 32'h00002010; + assign _zz_508 = ((decode_INSTRUCTION & _zz_515) == 32'h0); + assign _zz_509 = {(_zz_516 == _zz_517),{_zz_518,_zz_519}}; + assign _zz_510 = ((decode_INSTRUCTION & _zz_520) == 32'h0); + assign _zz_511 = 1'b0; + assign _zz_512 = ({_zz_521,{_zz_522,_zz_523}} != 3'b000); + assign _zz_513 = ({_zz_524,_zz_525} != 2'b00); + assign _zz_514 = {(_zz_526 != _zz_527),(_zz_528 != _zz_529)}; + assign _zz_515 = 32'h00000044; + assign _zz_516 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_517 = 32'h0; + assign _zz_518 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_519 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_520 = 32'h00000058; + assign _zz_521 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_522 = ((decode_INSTRUCTION & _zz_530) == 32'h00002010); + assign _zz_523 = ((decode_INSTRUCTION & _zz_531) == 32'h40000030); + assign _zz_524 = ((decode_INSTRUCTION & _zz_532) == 32'h00000004); + assign _zz_525 = _zz_88; + assign _zz_526 = {(_zz_533 == _zz_534),_zz_88}; + assign _zz_527 = 2'b00; + assign _zz_528 = ((decode_INSTRUCTION & _zz_535) == 32'h00001008); + assign _zz_529 = 1'b0; + assign _zz_530 = 32'h00002014; + assign _zz_531 = 32'h40000034; + assign _zz_532 = 32'h00000014; + assign _zz_533 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_534 = 32'h00000004; + assign _zz_535 = 32'h00005048; + assign _zz_536 = execute_INSTRUCTION[31]; + assign _zz_537 = execute_INSTRUCTION[31]; + assign _zz_538 = execute_INSTRUCTION[7]; + assign _zz_539 = 32'h0; always @ (posedge clk) begin - if(_zz_343) begin - _zz_205 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_348) begin + _zz_210 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_344) begin - _zz_206 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_349) begin + _zz_211 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1655,13 +1650,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_177 ), //i - .io_cpu_prefetch_isValid (_zz_178 ), //i + .io_flush (_zz_182 ), //i + .io_cpu_prefetch_isValid (_zz_183 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_179 ), //i - .io_cpu_fetch_isStuck (_zz_180 ), //i - .io_cpu_fetch_isRemoved (_zz_181 ), //i + .io_cpu_fetch_isValid (_zz_184 ), //i + .io_cpu_fetch_isStuck (_zz_185 ), //i + .io_cpu_fetch_isRemoved (_zz_186 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1674,8 +1669,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_182 ), //i - .io_cpu_decode_isStuck (_zz_183 ), //i + .io_cpu_decode_isValid (_zz_187 ), //i + .io_cpu_decode_isStuck (_zz_188 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1683,8 +1678,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_184 ), //i - .io_cpu_fill_valid (_zz_185 ), //i + .io_cpu_decode_isUser (_zz_189 ), //i + .io_cpu_fill_valid (_zz_190 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1693,26 +1688,26 @@ module VexRiscv ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_144[2:0] ), //i + ._zz_9 (_zz_149[2:0] ), //i ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_186 ), //i - .io_cpu_execute_address (_zz_187[31:0] ), //i + .io_cpu_execute_isValid (_zz_191 ), //i + .io_cpu_execute_address (_zz_192[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_82[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_188 ), //i + .io_cpu_memory_isValid (_zz_193 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_189[31:0] ), //i + .io_cpu_memory_address (_zz_194[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_190 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_195 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1720,31 +1715,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_191 ), //i + .io_cpu_writeBack_isValid (_zz_196 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_192 ), //i + .io_cpu_writeBack_isUser (_zz_197 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_193[31:0] ), //i + .io_cpu_writeBack_address (_zz_198[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_194 ), //i - .io_cpu_writeBack_fence_SR (_zz_195 ), //i - .io_cpu_writeBack_fence_SO (_zz_196 ), //i - .io_cpu_writeBack_fence_SI (_zz_197 ), //i - .io_cpu_writeBack_fence_PW (_zz_198 ), //i - .io_cpu_writeBack_fence_PR (_zz_199 ), //i - .io_cpu_writeBack_fence_PO (_zz_200 ), //i - .io_cpu_writeBack_fence_PI (_zz_201 ), //i - .io_cpu_writeBack_fence_FM (_zz_202[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_199 ), //i + .io_cpu_writeBack_fence_SR (_zz_200 ), //i + .io_cpu_writeBack_fence_SO (_zz_201 ), //i + .io_cpu_writeBack_fence_SI (_zz_202 ), //i + .io_cpu_writeBack_fence_PW (_zz_203 ), //i + .io_cpu_writeBack_fence_PR (_zz_204 ), //i + .io_cpu_writeBack_fence_PO (_zz_205 ), //i + .io_cpu_writeBack_fence_PI (_zz_206 ), //i + .io_cpu_writeBack_fence_FM (_zz_207[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_203 ), //i + .io_cpu_flush_valid (_zz_208 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_204 ), //i + .io_mem_cmd_ready (_zz_209 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1760,18 +1755,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_345) + case(_zz_350) 2'b00 : begin - _zz_207 = DBusCachedPlugin_redoBranch_payload; + _zz_212 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_207 = CsrPlugin_jumpInterface_payload; + _zz_212 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_207 = BranchPlugin_jumpInterface_payload; + _zz_212 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_207 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_212 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2463,7 +2458,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_249) + $signed(_zz_257)); + assign memory_MUL_LOW = ($signed(_zz_254) + $signed(_zz_262)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2471,39 +2466,39 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_259; + assign execute_SHIFT_RIGHT = _zz_264; assign execute_REGFILE_WRITE_DATA = _zz_100; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_187[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_192[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_261[0]; - assign decode_IS_RS1_SIGNED = _zz_262[0]; - assign decode_IS_DIV = _zz_263[0]; + assign decode_IS_RS2_SIGNED = _zz_266[0]; + assign decode_IS_RS1_SIGNED = _zz_267[0]; + assign decode_IS_DIV = _zz_268[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_264[0]; + assign decode_IS_MUL = _zz_269[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_265[0]; + assign decode_IS_CSR = _zz_270[0]; assign _zz_8 = _zz_9; assign _zz_10 = _zz_11; assign decode_SHIFT_CTRL = _zz_12; assign _zz_13 = _zz_14; assign decode_ALU_BITWISE_CTRL = _zz_15; assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_266[0]; - assign decode_MEMORY_MANAGMENT = _zz_267[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_271[0]; + assign decode_MEMORY_MANAGMENT = _zz_272[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_268[0]; + assign decode_MEMORY_WR = _zz_273[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_269[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_270[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_274[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_275[0]; assign decode_SRC2_CTRL = _zz_18; assign _zz_19 = _zz_20; assign decode_ALU_CTRL = _zz_21; @@ -2517,7 +2512,7 @@ module VexRiscv ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_271[0]; + assign decode_IS_EBREAK = _zz_276[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2539,13 +2534,13 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_117; + assign execute_BRANCH_COND_RESULT = _zz_122; assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_272[0]; - assign decode_RS1_USE = _zz_273[0]; + assign decode_RS2_USE = _zz_277[0]; + assign decode_RS1_USE = _zz_278[0]; always @ (*) begin _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_208)begin + if(_zz_213)begin _zz_31 = execute_CsrPlugin_readData; end end @@ -2558,28 +2553,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_111)begin + if((_zz_112 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_113; end end - if(_zz_209)begin - if(_zz_210)begin - if(_zz_110)begin + if(_zz_214)begin + if(_zz_215)begin + if(_zz_115)begin decode_RS2 = _zz_50; end end end - if(_zz_211)begin + if(_zz_216)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_112)begin + if(_zz_117)begin decode_RS2 = _zz_32; end end end - if(_zz_212)begin + if(_zz_217)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_114)begin + if(_zz_119)begin decode_RS2 = _zz_31; end end @@ -2588,28 +2583,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_111)begin + if((_zz_112 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_113; end end - if(_zz_209)begin - if(_zz_210)begin - if(_zz_109)begin + if(_zz_214)begin + if(_zz_215)begin + if(_zz_114)begin decode_RS1 = _zz_50; end end end - if(_zz_211)begin + if(_zz_216)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_111)begin + if(_zz_116)begin decode_RS1 = _zz_32; end end end - if(_zz_212)begin + if(_zz_217)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_113)begin + if(_zz_118)begin decode_RS1 = _zz_31; end end @@ -2631,7 +2626,7 @@ module VexRiscv ( end endcase end - if(_zz_213)begin + if(_zz_218)begin _zz_32 = memory_DivPlugin_div_result; end end @@ -2644,8 +2639,8 @@ module VexRiscv ( assign _zz_35 = execute_PC; assign execute_SRC2_CTRL = _zz_36; assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_274[0]; - assign decode_SRC_ADD_ZERO = _zz_275[0]; + assign decode_SRC_USE_SUB_LESS = _zz_279[0]; + assign decode_SRC_ADD_ZERO = _zz_280[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_38; @@ -2663,25 +2658,25 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_276[0]; + decode_REGFILE_WRITE_VALID = _zz_281[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_346) == 32'h00001073),{(_zz_347 == _zz_348),{_zz_349,{_zz_350,_zz_351}}}}}}} != 21'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_351) == 32'h00001073),{(_zz_352 == _zz_353),{_zz_354,{_zz_355,_zz_356}}}}}}} != 21'h0); always @ (*) begin _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_248) + case(_zz_253) 2'b00 : begin - _zz_50 = _zz_318; + _zz_50 = _zz_323; end default : begin - _zz_50 = _zz_319; + _zz_50 = _zz_324; end endcase end @@ -2700,32 +2695,32 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_277[0]; - assign decode_FLUSH_ALL = _zz_278[0]; + assign decode_MEMORY_ENABLE = _zz_282[0]; + assign decode_FLUSH_ALL = _zz_283[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_214)begin + if(_zz_219)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_215)begin + if(_zz_220)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_216)begin + if(_zz_221)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_217)begin + if(_zz_222)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2754,7 +2749,7 @@ module VexRiscv ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_144) + case(_zz_149) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2765,7 +2760,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_109 || _zz_110)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2778,7 +2773,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_218)begin + if(_zz_223)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2792,22 +2787,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_218)begin + if(_zz_223)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_203 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_208 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_219)begin + if(_zz_224)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_208)begin + if(_zz_213)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2819,7 +2814,7 @@ module VexRiscv ( if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_220)begin + if(_zz_225)begin execute_arbitration_haltByOther = 1'b1; end end @@ -2836,8 +2831,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_220)begin - if(_zz_221)begin + if(_zz_225)begin + if(_zz_226)begin execute_arbitration_flushIt = 1'b1; end end @@ -2848,8 +2843,8 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_220)begin - if(_zz_221)begin + if(_zz_225)begin + if(_zz_226)begin execute_arbitration_flushNext = 1'b1; end end @@ -2857,7 +2852,7 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_213)begin + if(_zz_218)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2919,10 +2914,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_222)begin + if(_zz_227)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_223)begin + if(_zz_228)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2936,21 +2931,21 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_222)begin + if(_zz_227)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_223)begin + if(_zz_228)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_220)begin - if(_zz_221)begin + if(_zz_225)begin + if(_zz_226)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_224)begin + if(_zz_229)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -2971,7 +2966,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_219)begin + if(_zz_224)begin CsrPlugin_inWfi = 1'b1; end end @@ -2985,21 +2980,21 @@ module VexRiscv ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_222)begin + if(_zz_227)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_223)begin + if(_zz_228)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_222)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_227)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_223)begin - case(_zz_225) + if(_zz_228)begin + case(_zz_230) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3033,11 +3028,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_55 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_56 = (_zz_55 & (~ _zz_279)); + assign _zz_56 = (_zz_55 & (~ _zz_284)); assign _zz_57 = _zz_56[3]; assign _zz_58 = (_zz_56[1] || _zz_57); assign _zz_59 = (_zz_56[2] || _zz_57); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_207; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_212; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3057,7 +3052,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_281); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_286); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3149,7 +3144,7 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_144) + case(_zz_149) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3161,7 +3156,7 @@ module VexRiscv ( endcase end - assign _zz_69 = _zz_282[11]; + assign _zz_69 = _zz_287[11]; always @ (*) begin _zz_70[18] = _zz_69; _zz_70[17] = _zz_69; @@ -3185,13 +3180,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_283[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_288[31])); if(_zz_75)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_71 = _zz_284[19]; + assign _zz_71 = _zz_289[19]; always @ (*) begin _zz_72[10] = _zz_71; _zz_72[9] = _zz_71; @@ -3206,7 +3201,7 @@ module VexRiscv ( _zz_72[0] = _zz_71; end - assign _zz_73 = _zz_285[11]; + assign _zz_73 = _zz_290[11]; always @ (*) begin _zz_74[18] = _zz_73; _zz_74[17] = _zz_73; @@ -3232,16 +3227,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_75 = _zz_286[1]; + _zz_75 = _zz_291[1]; end default : begin - _zz_75 = _zz_287[1]; + _zz_75 = _zz_292[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_76 = _zz_288[19]; + assign _zz_76 = _zz_293[19]; always @ (*) begin _zz_77[10] = _zz_76; _zz_77[9] = _zz_76; @@ -3256,7 +3251,7 @@ module VexRiscv ( _zz_77[0] = _zz_76; end - assign _zz_78 = _zz_289[11]; + assign _zz_78 = _zz_294[11]; always @ (*) begin _zz_79[18] = _zz_78; _zz_79[17] = _zz_78; @@ -3279,7 +3274,7 @@ module VexRiscv ( _zz_79[0] = _zz_78; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_77,{{{_zz_364,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_79,{{{_zz_365,_zz_366},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_77,{{{_zz_369,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_79,{{{_zz_370,_zz_371},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3288,52 +3283,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_178 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_179 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_180 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_179; + assign _zz_183 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_184 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_185 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_184; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_182 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_183 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_184 = (CsrPlugin_privilege == 2'b00); + assign _zz_187 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_188 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_189 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_217)begin + if(_zz_222)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_215)begin + if(_zz_220)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_185 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_215)begin - _zz_185 = 1'b1; + _zz_190 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_220)begin + _zz_190 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_216)begin + if(_zz_221)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_214)begin + if(_zz_219)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_216)begin + if(_zz_221)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_214)begin + if(_zz_219)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3343,9 +3338,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_177 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_182 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_204 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_209 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3372,8 +3367,8 @@ module VexRiscv ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_186 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_187 = execute_SRC_ADD; + assign _zz_191 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_192 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3388,27 +3383,27 @@ module VexRiscv ( endcase end - assign _zz_203 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_188 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_189 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_188; + assign _zz_208 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_193 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_194 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_193; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_189; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_194; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_190 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_195 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_54 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_190 = 1'b1; + _zz_195 = 1'b1; end end - assign _zz_191 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_192 = (CsrPlugin_privilege == 2'b00); - assign _zz_193 = writeBack_REGFILE_WRITE_DATA; + assign _zz_196 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_197 = (CsrPlugin_privilege == 2'b00); + assign _zz_198 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_226)begin + if(_zz_231)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3418,7 +3413,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_226)begin + if(_zz_231)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3437,15 +3432,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_226)begin + if(_zz_231)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_290}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_295}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_291}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_296}; end end end @@ -3518,7 +3513,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_246) + case(_zz_251) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_84; end @@ -3553,7 +3548,7 @@ module VexRiscv ( assign _zz_89 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_90 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_91 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_87 = {(((decode_INSTRUCTION & _zz_367) == 32'h00100050) != 1'b0),{(_zz_91 != 1'b0),{(_zz_91 != 1'b0),{(_zz_368 != _zz_369),{_zz_370,{_zz_371,_zz_372}}}}}}; + assign _zz_87 = {(((decode_INSTRUCTION & _zz_372) == 32'h00100050) != 1'b0),{(_zz_91 != 1'b0),{(_zz_91 != 1'b0),{(_zz_373 != _zz_374),{_zz_375,{_zz_376,_zz_377}}}}}}; assign _zz_92 = _zz_87[2 : 1]; assign _zz_49 = _zz_92; assign _zz_93 = _zz_87[7 : 6]; @@ -3573,8 +3568,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_205; - assign decode_RegFilePlugin_rs2Data = _zz_206; + assign decode_RegFilePlugin_rs1Data = _zz_210; + assign decode_RegFilePlugin_rs2Data = _zz_211; always @ (*) begin lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); if(_zz_99)begin @@ -3616,7 +3611,7 @@ module VexRiscv ( _zz_100 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_100 = {31'd0, _zz_292}; + _zz_100 = {31'd0, _zz_297}; end default : begin _zz_100 = execute_SRC_ADD_SUB; @@ -3630,18 +3625,18 @@ module VexRiscv ( _zz_101 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_101 = {29'd0, _zz_293}; + _zz_101 = {29'd0, _zz_298}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_101 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_101 = {27'd0, _zz_294}; + _zz_101 = {27'd0, _zz_299}; end endcase end - assign _zz_102 = _zz_295[11]; + assign _zz_102 = _zz_300[11]; always @ (*) begin _zz_103[19] = _zz_102; _zz_103[18] = _zz_102; @@ -3665,7 +3660,7 @@ module VexRiscv ( _zz_103[0] = _zz_102; end - assign _zz_104 = _zz_296[11]; + assign _zz_104 = _zz_301[11]; always @ (*) begin _zz_105[19] = _zz_104; _zz_105[18] = _zz_104; @@ -3707,7 +3702,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_297; + execute_SrcPlugin_addSub = _zz_302; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3787,180 +3782,175 @@ module VexRiscv ( end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_227)begin - if(_zz_228)begin - if(_zz_109)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_109 = 1'b0; + if(_zz_232)begin + if(_zz_233)begin + if(_zz_114)begin + _zz_109 = 1'b1; end end end - if(_zz_229)begin - if(_zz_230)begin - if(_zz_111)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_234)begin + if(_zz_235)begin + if(_zz_116)begin + _zz_109 = 1'b1; end end end - if(_zz_231)begin - if(_zz_232)begin - if(_zz_113)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_236)begin + if(_zz_237)begin + if(_zz_118)begin + _zz_109 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_109 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_227)begin - if(_zz_228)begin - if(_zz_110)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_110 = 1'b0; + if(_zz_232)begin + if(_zz_233)begin + if(_zz_115)begin + _zz_110 = 1'b1; end end end - if(_zz_229)begin - if(_zz_230)begin - if(_zz_112)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_234)begin + if(_zz_235)begin + if(_zz_117)begin + _zz_110 = 1'b1; end end end - if(_zz_231)begin - if(_zz_232)begin - if(_zz_114)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_236)begin + if(_zz_237)begin + if(_zz_119)begin + _zz_110 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_110 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_109 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_110 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_111 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_112 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_113 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_114 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_114 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_115 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_116 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_117 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_118 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_119 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_115 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_115 == 3'b000)) begin - _zz_116 = execute_BranchPlugin_eq; - end else if((_zz_115 == 3'b001)) begin - _zz_116 = (! execute_BranchPlugin_eq); - end else if((((_zz_115 & 3'b101) == 3'b101))) begin - _zz_116 = (! execute_SRC_LESS); + assign _zz_120 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_120 == 3'b000)) begin + _zz_121 = execute_BranchPlugin_eq; + end else if((_zz_120 == 3'b001)) begin + _zz_121 = (! execute_BranchPlugin_eq); + end else if((((_zz_120 & 3'b101) == 3'b101))) begin + _zz_121 = (! execute_SRC_LESS); end else begin - _zz_116 = execute_SRC_LESS; + _zz_121 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_117 = 1'b0; + _zz_122 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_117 = 1'b1; + _zz_122 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_117 = 1'b1; + _zz_122 = 1'b1; end default : begin - _zz_117 = _zz_116; + _zz_122 = _zz_121; end endcase end - assign _zz_118 = _zz_304[11]; - always @ (*) begin - _zz_119[19] = _zz_118; - _zz_119[18] = _zz_118; - _zz_119[17] = _zz_118; - _zz_119[16] = _zz_118; - _zz_119[15] = _zz_118; - _zz_119[14] = _zz_118; - _zz_119[13] = _zz_118; - _zz_119[12] = _zz_118; - _zz_119[11] = _zz_118; - _zz_119[10] = _zz_118; - _zz_119[9] = _zz_118; - _zz_119[8] = _zz_118; - _zz_119[7] = _zz_118; - _zz_119[6] = _zz_118; - _zz_119[5] = _zz_118; - _zz_119[4] = _zz_118; - _zz_119[3] = _zz_118; - _zz_119[2] = _zz_118; - _zz_119[1] = _zz_118; - _zz_119[0] = _zz_118; - end - - assign _zz_120 = _zz_305[19]; - always @ (*) begin - _zz_121[10] = _zz_120; - _zz_121[9] = _zz_120; - _zz_121[8] = _zz_120; - _zz_121[7] = _zz_120; - _zz_121[6] = _zz_120; - _zz_121[5] = _zz_120; - _zz_121[4] = _zz_120; - _zz_121[3] = _zz_120; - _zz_121[2] = _zz_120; - _zz_121[1] = _zz_120; - _zz_121[0] = _zz_120; - end - - assign _zz_122 = _zz_306[11]; - always @ (*) begin - _zz_123[18] = _zz_122; - _zz_123[17] = _zz_122; - _zz_123[16] = _zz_122; - _zz_123[15] = _zz_122; - _zz_123[14] = _zz_122; - _zz_123[13] = _zz_122; - _zz_123[12] = _zz_122; - _zz_123[11] = _zz_122; - _zz_123[10] = _zz_122; - _zz_123[9] = _zz_122; - _zz_123[8] = _zz_122; - _zz_123[7] = _zz_122; - _zz_123[6] = _zz_122; - _zz_123[5] = _zz_122; - _zz_123[4] = _zz_122; - _zz_123[3] = _zz_122; - _zz_123[2] = _zz_122; - _zz_123[1] = _zz_122; - _zz_123[0] = _zz_122; + assign _zz_123 = _zz_309[11]; + always @ (*) begin + _zz_124[19] = _zz_123; + _zz_124[18] = _zz_123; + _zz_124[17] = _zz_123; + _zz_124[16] = _zz_123; + _zz_124[15] = _zz_123; + _zz_124[14] = _zz_123; + _zz_124[13] = _zz_123; + _zz_124[12] = _zz_123; + _zz_124[11] = _zz_123; + _zz_124[10] = _zz_123; + _zz_124[9] = _zz_123; + _zz_124[8] = _zz_123; + _zz_124[7] = _zz_123; + _zz_124[6] = _zz_123; + _zz_124[5] = _zz_123; + _zz_124[4] = _zz_123; + _zz_124[3] = _zz_123; + _zz_124[2] = _zz_123; + _zz_124[1] = _zz_123; + _zz_124[0] = _zz_123; + end + + assign _zz_125 = _zz_310[19]; + always @ (*) begin + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; + end + + assign _zz_127 = _zz_311[11]; + always @ (*) begin + _zz_128[18] = _zz_127; + _zz_128[17] = _zz_127; + _zz_128[16] = _zz_127; + _zz_128[15] = _zz_127; + _zz_128[14] = _zz_127; + _zz_128[13] = _zz_127; + _zz_128[12] = _zz_127; + _zz_128[11] = _zz_127; + _zz_128[10] = _zz_127; + _zz_128[9] = _zz_127; + _zz_128[8] = _zz_127; + _zz_128[7] = _zz_127; + _zz_128[6] = _zz_127; + _zz_128[5] = _zz_127; + _zz_128[4] = _zz_127; + _zz_128[3] = _zz_127; + _zz_128[2] = _zz_127; + _zz_128[1] = _zz_127; + _zz_128[0] = _zz_127; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_124 = (_zz_307[1] ^ execute_RS1[1]); + _zz_129 = (_zz_312[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_124 = _zz_308[1]; + _zz_129 = _zz_313[1]; end default : begin - _zz_124 = _zz_309[1]; + _zz_129 = _zz_314[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_124); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_129); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -3972,80 +3962,80 @@ module VexRiscv ( endcase end - assign _zz_125 = _zz_310[11]; + assign _zz_130 = _zz_315[11]; always @ (*) begin - _zz_126[19] = _zz_125; - _zz_126[18] = _zz_125; - _zz_126[17] = _zz_125; - _zz_126[16] = _zz_125; - _zz_126[15] = _zz_125; - _zz_126[14] = _zz_125; - _zz_126[13] = _zz_125; - _zz_126[12] = _zz_125; - _zz_126[11] = _zz_125; - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; + _zz_131[19] = _zz_130; + _zz_131[18] = _zz_130; + _zz_131[17] = _zz_130; + _zz_131[16] = _zz_130; + _zz_131[15] = _zz_130; + _zz_131[14] = _zz_130; + _zz_131[13] = _zz_130; + _zz_131[12] = _zz_130; + _zz_131[11] = _zz_130; + _zz_131[10] = _zz_130; + _zz_131[9] = _zz_130; + _zz_131[8] = _zz_130; + _zz_131[7] = _zz_130; + _zz_131[6] = _zz_130; + _zz_131[5] = _zz_130; + _zz_131[4] = _zz_130; + _zz_131[3] = _zz_130; + _zz_131[2] = _zz_130; + _zz_131[1] = _zz_130; + _zz_131[0] = _zz_130; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_126,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_131,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_128,{{{_zz_531,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_130,{{{_zz_532,_zz_533},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_133,{{{_zz_536,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_135,{{{_zz_537,_zz_538},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_313}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_318}; end end endcase end - assign _zz_127 = _zz_311[19]; - always @ (*) begin - _zz_128[10] = _zz_127; - _zz_128[9] = _zz_127; - _zz_128[8] = _zz_127; - _zz_128[7] = _zz_127; - _zz_128[6] = _zz_127; - _zz_128[5] = _zz_127; - _zz_128[4] = _zz_127; - _zz_128[3] = _zz_127; - _zz_128[2] = _zz_127; - _zz_128[1] = _zz_127; - _zz_128[0] = _zz_127; - end - - assign _zz_129 = _zz_312[11]; - always @ (*) begin - _zz_130[18] = _zz_129; - _zz_130[17] = _zz_129; - _zz_130[16] = _zz_129; - _zz_130[15] = _zz_129; - _zz_130[14] = _zz_129; - _zz_130[13] = _zz_129; - _zz_130[12] = _zz_129; - _zz_130[11] = _zz_129; - _zz_130[10] = _zz_129; - _zz_130[9] = _zz_129; - _zz_130[8] = _zz_129; - _zz_130[7] = _zz_129; - _zz_130[6] = _zz_129; - _zz_130[5] = _zz_129; - _zz_130[4] = _zz_129; - _zz_130[3] = _zz_129; - _zz_130[2] = _zz_129; - _zz_130[1] = _zz_129; - _zz_130[0] = _zz_129; + assign _zz_132 = _zz_316[19]; + always @ (*) begin + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; + end + + assign _zz_134 = _zz_317[11]; + always @ (*) begin + _zz_135[18] = _zz_134; + _zz_135[17] = _zz_134; + _zz_135[16] = _zz_134; + _zz_135[15] = _zz_134; + _zz_135[14] = _zz_134; + _zz_135[13] = _zz_134; + _zz_135[12] = _zz_134; + _zz_135[11] = _zz_134; + _zz_135[10] = _zz_134; + _zz_135[9] = _zz_134; + _zz_135[8] = _zz_134; + _zz_135[7] = _zz_134; + _zz_135[6] = _zz_134; + _zz_135[5] = _zz_134; + _zz_135[4] = _zz_134; + _zz_135[3] = _zz_134; + _zz_135[2] = _zz_134; + _zz_135[1] = _zz_134; + _zz_135[0] = _zz_134; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -4062,16 +4052,16 @@ module VexRiscv ( end end - assign _zz_131 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_132 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_133 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_136 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_137 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_138 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_134 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_135 = _zz_314[0]; + assign _zz_139 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_140 = _zz_319[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_218)begin + if(_zz_223)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4152,7 +4142,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4258,7 +4248,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_233)begin + if(_zz_238)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4277,20 +4267,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_234)begin + if(_zz_239)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_235)begin + if(_zz_240)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_234)begin + if(_zz_239)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_235)begin + if(_zz_240)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4305,14 +4295,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_233)begin + if(_zz_238)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_233)begin + if(_zz_238)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4321,7 +4311,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_247) + case(_zz_252) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4335,7 +4325,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_236) + case(_zz_241) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4349,7 +4339,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_236) + case(_zz_241) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4368,12 +4358,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_316) + $signed(_zz_317)); + assign writeBack_MulPlugin_result = ($signed(_zz_321) + $signed(_zz_322)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_213)begin - if(_zz_237)begin + if(_zz_218)begin + if(_zz_242)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4381,7 +4371,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_238)begin + if(_zz_243)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4392,32 +4382,32 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_321); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_326); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_136 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_136[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_322); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_323 : _zz_324); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_325[31:0]; - assign _zz_137 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_138 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_139 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_141 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_141[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_327); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_328 : _zz_329); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_330[31:0]; + assign _zz_142 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_143 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_144 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_140[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_140[31 : 0] = execute_RS1; + _zz_145[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_145[31 : 0] = execute_RS1; end - assign _zz_142 = (_zz_141 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_142 != 32'h0); + assign _zz_147 = (_zz_146 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_147 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_239) + case(_zz_244) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4431,7 +4421,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_143))begin + if((! _zz_148))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4443,7 +4433,7 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_239) + case(_zz_244) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4507,7 +4497,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_144) + case(_zz_149) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4517,216 +4507,216 @@ module VexRiscv ( end always @ (*) begin - _zz_145 = 32'h0; + _zz_150 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_145[12 : 0] = 13'h1000; - _zz_145[25 : 20] = 6'h20; + _zz_150[12 : 0] = 13'h1000; + _zz_150[25 : 20] = 6'h20; end end always @ (*) begin - _zz_146 = 32'h0; + _zz_151 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_146[3 : 0] = 4'b1011; + _zz_151[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_147 = 32'h0; + _zz_152 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_147[4 : 0] = 5'h16; + _zz_152[4 : 0] = 5'h16; end end always @ (*) begin - _zz_148 = 32'h0; + _zz_153 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_148[5 : 0] = 6'h21; + _zz_153[5 : 0] = 6'h21; end end always @ (*) begin - _zz_149 = 32'h0; + _zz_154 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_149[31 : 30] = CsrPlugin_misa_base; - _zz_149[25 : 0] = CsrPlugin_misa_extensions; + _zz_154[31 : 30] = CsrPlugin_misa_base; + _zz_154[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_150 = 32'h0; + _zz_155 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_150[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_150[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_150[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_155[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_155[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_155[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_151 = 32'h0; + _zz_156 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_151[11 : 11] = CsrPlugin_mip_MEIP; - _zz_151[7 : 7] = CsrPlugin_mip_MTIP; - _zz_151[3 : 3] = CsrPlugin_mip_MSIP; + _zz_156[11 : 11] = CsrPlugin_mip_MEIP; + _zz_156[7 : 7] = CsrPlugin_mip_MTIP; + _zz_156[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_152 = 32'h0; + _zz_157 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_152[11 : 11] = CsrPlugin_mie_MEIE; - _zz_152[7 : 7] = CsrPlugin_mie_MTIE; - _zz_152[3 : 3] = CsrPlugin_mie_MSIE; + _zz_157[11 : 11] = CsrPlugin_mie_MEIE; + _zz_157[7 : 7] = CsrPlugin_mie_MTIE; + _zz_157[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_153 = 32'h0; + _zz_158 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_153[31 : 2] = CsrPlugin_mtvec_base; - _zz_153[1 : 0] = CsrPlugin_mtvec_mode; + _zz_158[31 : 2] = CsrPlugin_mtvec_base; + _zz_158[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_154 = 32'h0; + _zz_159 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_154[31 : 0] = CsrPlugin_mepc; + _zz_159[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_155 = 32'h0; + _zz_160 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_155[31 : 0] = CsrPlugin_mscratch; + _zz_160[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_156 = 32'h0; + _zz_161 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_156[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_156[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_161[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_161[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_157 = 32'h0; + _zz_162 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_157[31 : 0] = CsrPlugin_mtval; + _zz_162[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_158 = 32'h0; + _zz_163 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_158[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_163[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_159 = 32'h0; + _zz_164 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_159[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_164[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_160 = 32'h0; + _zz_165 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_160[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_165[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_161 = 32'h0; + _zz_166 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_161[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_166[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_162 = 32'h0; + _zz_167 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_162[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_167[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_163 = 32'h0; + _zz_168 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_163[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_168[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_164 = 32'h0; + _zz_169 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_164[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_169[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_165 = 32'h0; + _zz_170 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_165[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_170[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_166 = 32'h0; + _zz_171 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_166[31 : 0] = _zz_141; + _zz_171[31 : 0] = _zz_146; end end always @ (*) begin - _zz_167 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_167[31 : 0] = _zz_142; + _zz_172[31 : 0] = _zz_147; end end - assign execute_CsrPlugin_readData = (((((_zz_145 | _zz_146) | (_zz_147 | _zz_148)) | ((_zz_534 | _zz_149) | (_zz_150 | _zz_151))) | (((_zz_152 | _zz_153) | (_zz_154 | _zz_155)) | ((_zz_156 | _zz_157) | (_zz_158 | _zz_159)))) | (((_zz_160 | _zz_161) | (_zz_162 | _zz_163)) | ((_zz_164 | _zz_165) | (_zz_166 | _zz_167)))); - assign iBusWishbone_ADR = {_zz_342,_zz_168}; - assign iBusWishbone_CTI = ((_zz_168 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_150 | _zz_151) | (_zz_152 | _zz_153)) | ((_zz_539 | _zz_154) | (_zz_155 | _zz_156))) | (((_zz_157 | _zz_158) | (_zz_159 | _zz_160)) | ((_zz_161 | _zz_162) | (_zz_163 | _zz_164)))) | (((_zz_165 | _zz_166) | (_zz_167 | _zz_168)) | ((_zz_169 | _zz_170) | (_zz_171 | _zz_172)))); + assign iBusWishbone_ADR = {_zz_347,_zz_173}; + assign iBusWishbone_CTI = ((_zz_173 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_240)begin + if(_zz_245)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_240)begin + if(_zz_245)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_169; + assign iBus_rsp_valid = _zz_174; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_175 = (dBus_cmd_payload_length != 3'b000); - assign _zz_171 = dBus_cmd_valid; - assign _zz_173 = dBus_cmd_payload_wr; - assign _zz_174 = (_zz_170 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_172 && (_zz_173 || _zz_174)); - assign dBusWishbone_ADR = ((_zz_175 ? {{dBus_cmd_payload_address[31 : 5],_zz_170},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_175 ? (_zz_174 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_180 = (dBus_cmd_payload_length != 3'b000); + assign _zz_176 = dBus_cmd_valid; + assign _zz_178 = dBus_cmd_payload_wr; + assign _zz_179 = (_zz_175 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_177 && (_zz_178 || _zz_179)); + assign dBusWishbone_ADR = ((_zz_180 ? {{dBus_cmd_payload_address[31 : 5],_zz_175},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_180 ? (_zz_179 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_173 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_173; + assign dBusWishbone_SEL = (_zz_178 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_178; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_172 = (_zz_171 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_171; - assign dBusWishbone_STB = _zz_171; - assign dBus_rsp_valid = _zz_176; + assign _zz_177 = (_zz_176 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_176; + assign dBusWishbone_STB = _zz_176; + assign dBus_rsp_valid = _zz_181; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4749,7 +4739,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= _zz_81; DBusCachedPlugin_rspCounter <= 32'h0; _zz_99 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_111 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4770,15 +4760,15 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_141 <= 32'h0; + _zz_146 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_144 <= 3'b000; - _zz_168 <= 3'b000; - _zz_169 <= 1'b0; - _zz_170 <= 3'b000; - _zz_176 <= 1'b0; + _zz_149 <= 3'b000; + _zz_173 <= 3'b000; + _zz_174 <= 1'b0; + _zz_175 <= 3'b000; + _zz_181 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -4859,7 +4849,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_241)begin + if(_zz_246)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -4869,7 +4859,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end _zz_99 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_111 <= (_zz_41 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4891,14 +4881,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_242)begin - if(_zz_243)begin + if(_zz_247)begin + if(_zz_248)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_244)begin + if(_zz_249)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_245)begin + if(_zz_250)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4923,7 +4913,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_222)begin + if(_zz_227)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4934,8 +4924,8 @@ module VexRiscv ( end endcase end - if(_zz_223)begin - case(_zz_225) + if(_zz_228)begin + case(_zz_230) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4945,7 +4935,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_133,{_zz_132,_zz_131}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_138,{_zz_137,_zz_136}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; @@ -4965,25 +4955,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_144) + case(_zz_149) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_144 <= 3'b001; + _zz_149 <= 3'b001; end end 3'b001 : begin - _zz_144 <= 3'b010; + _zz_149 <= 3'b010; end 3'b010 : begin - _zz_144 <= 3'b011; + _zz_149 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_144 <= 3'b100; + _zz_149 <= 3'b100; end end 3'b100 : begin - _zz_144 <= 3'b000; + _zz_149 <= 3'b000; end default : begin end @@ -4997,35 +4987,35 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_335[0]; - CsrPlugin_mstatus_MIE <= _zz_336[0]; + CsrPlugin_mstatus_MPIE <= _zz_340[0]; + CsrPlugin_mstatus_MIE <= _zz_341[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_338[0]; - CsrPlugin_mie_MTIE <= _zz_339[0]; - CsrPlugin_mie_MSIE <= _zz_340[0]; + CsrPlugin_mie_MEIE <= _zz_343[0]; + CsrPlugin_mie_MTIE <= _zz_344[0]; + CsrPlugin_mie_MSIE <= _zz_345[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_141 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_240)begin + if(_zz_245)begin if(iBusWishbone_ACK)begin - _zz_168 <= (_zz_168 + 3'b001); + _zz_173 <= (_zz_173 + 3'b001); end end - _zz_169 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_171 && _zz_172))begin - _zz_170 <= (_zz_170 + 3'b001); - if(_zz_174)begin - _zz_170 <= 3'b000; + _zz_174 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_176 && _zz_177))begin + _zz_175 <= (_zz_175 + 3'b001); + if(_zz_179)begin + _zz_175 <= 3'b000; end end - _zz_176 <= ((_zz_171 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_181 <= ((_zz_176 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5039,7 +5029,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_241)begin + if(_zz_246)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5057,8 +5047,8 @@ module VexRiscv ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_112 <= _zz_40[11 : 7]; + _zz_113 <= _zz_50; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5066,9 +5056,9 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_218)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_135 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_135 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_223)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_140 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_140 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -5082,21 +5072,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_242)begin - if(_zz_243)begin + if(_zz_247)begin + if(_zz_248)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_244)begin + if(_zz_249)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_245)begin + if(_zz_250)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_222)begin + if(_zz_227)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5116,20 +5106,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_213)begin - if(_zz_237)begin + if(_zz_218)begin + if(_zz_242)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_326[31:0]; + memory_DivPlugin_div_result <= _zz_331[31:0]; end end end - if(_zz_238)begin + if(_zz_243)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_139 ? (~ _zz_140) : _zz_140) + _zz_332); - memory_DivPlugin_rs2 <= ((_zz_138 ? (~ execute_RS2) : execute_RS2) + _zz_334); - memory_DivPlugin_div_needRevert <= ((_zz_139 ^ (_zz_138 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_144 ? (~ _zz_145) : _zz_145) + _zz_337); + memory_DivPlugin_rs2 <= ((_zz_143 ? (~ execute_RS2) : execute_RS2) + _zz_339); + memory_DivPlugin_div_needRevert <= ((_zz_144 ^ (_zz_143 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5395,7 +5385,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_337[0]; + CsrPlugin_mip_MSIP <= _zz_342[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5416,7 +5406,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_341[0]; + CsrPlugin_mcause_interrupt <= _zz_346[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5459,8 +5449,8 @@ module VexRiscv ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_50; end - _zz_143 <= debug_bus_cmd_payload_address[2]; - if(_zz_220)begin + _zz_148 <= debug_bus_cmd_payload_address[2]; + if(_zz_225)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -5478,7 +5468,7 @@ module VexRiscv ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_239) + case(_zz_244) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -5506,13 +5496,13 @@ module VexRiscv ( end endcase end - if(_zz_220)begin - if(_zz_221)begin + if(_zz_225)begin + if(_zz_226)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_224)begin + if(_zz_229)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end @@ -5806,7 +5796,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_12)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -5820,7 +5810,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_12)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -5850,7 +5840,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -5877,7 +5867,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -5909,7 +5899,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -5919,7 +5909,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v index 592ac6e..6d1a3b4 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -74,38 +74,38 @@ module VexRiscv ( input clk, input reset ); - wire _zz_190; - wire _zz_191; - wire _zz_192; - wire _zz_193; - wire _zz_194; wire _zz_195; wire _zz_196; wire _zz_197; - wire [31:0] _zz_198; - reg _zz_199; + wire _zz_198; + wire _zz_199; wire _zz_200; - wire [31:0] _zz_201; + wire _zz_201; wire _zz_202; wire [31:0] _zz_203; reg _zz_204; wire _zz_205; - wire _zz_206; - wire [31:0] _zz_207; - wire _zz_208; - wire _zz_209; + wire [31:0] _zz_206; + wire _zz_207; + wire [31:0] _zz_208; + reg _zz_209; wire _zz_210; wire _zz_211; - wire _zz_212; + wire [31:0] _zz_212; wire _zz_213; wire _zz_214; wire _zz_215; - wire [3:0] _zz_216; + wire _zz_216; wire _zz_217; wire _zz_218; - reg [31:0] _zz_219; - reg [31:0] _zz_220; - reg [31:0] _zz_221; + wire _zz_219; + wire _zz_220; + wire [3:0] _zz_221; + wire _zz_222; + wire _zz_223; + reg [31:0] _zz_224; + reg [31:0] _zz_225; + reg [31:0] _zz_226; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire IBusCachedPlugin_cache_io_cpu_fetch_error; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; @@ -138,11 +138,6 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_222; - wire _zz_223; - wire _zz_224; - wire _zz_225; - wire _zz_226; wire _zz_227; wire _zz_228; wire _zz_229; @@ -152,324 +147,329 @@ module VexRiscv ( wire _zz_233; wire _zz_234; wire _zz_235; - wire [1:0] _zz_236; + wire _zz_236; wire _zz_237; wire _zz_238; wire _zz_239; wire _zz_240; - wire _zz_241; + wire [1:0] _zz_241; wire _zz_242; wire _zz_243; wire _zz_244; wire _zz_245; wire _zz_246; wire _zz_247; - wire [1:0] _zz_248; + wire _zz_248; wire _zz_249; wire _zz_250; wire _zz_251; wire _zz_252; - wire _zz_253; + wire [1:0] _zz_253; wire _zz_254; wire _zz_255; wire _zz_256; wire _zz_257; - wire [4:0] _zz_258; - wire [1:0] _zz_259; - wire [1:0] _zz_260; - wire [1:0] _zz_261; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; wire _zz_262; - wire [1:0] _zz_263; - wire [51:0] _zz_264; - wire [51:0] _zz_265; - wire [51:0] _zz_266; - wire [32:0] _zz_267; - wire [51:0] _zz_268; - wire [49:0] _zz_269; + wire [4:0] _zz_263; + wire [1:0] _zz_264; + wire [1:0] _zz_265; + wire [1:0] _zz_266; + wire _zz_267; + wire [1:0] _zz_268; + wire [51:0] _zz_269; wire [51:0] _zz_270; - wire [49:0] _zz_271; - wire [51:0] _zz_272; - wire [32:0] _zz_273; - wire [31:0] _zz_274; - wire [32:0] _zz_275; - wire [0:0] _zz_276; - wire [0:0] _zz_277; - wire [0:0] _zz_278; - wire [0:0] _zz_279; - wire [0:0] _zz_280; + wire [51:0] _zz_271; + wire [32:0] _zz_272; + wire [51:0] _zz_273; + wire [49:0] _zz_274; + wire [51:0] _zz_275; + wire [49:0] _zz_276; + wire [51:0] _zz_277; + wire [32:0] _zz_278; + wire [31:0] _zz_279; + wire [32:0] _zz_280; wire [0:0] _zz_281; wire [0:0] _zz_282; wire [0:0] _zz_283; wire [0:0] _zz_284; wire [0:0] _zz_285; - wire [2:0] _zz_286; - wire [31:0] _zz_287; + wire [0:0] _zz_286; + wire [0:0] _zz_287; wire [0:0] _zz_288; wire [0:0] _zz_289; wire [0:0] _zz_290; - wire [0:0] _zz_291; - wire [0:0] _zz_292; + wire [2:0] _zz_291; + wire [31:0] _zz_292; wire [0:0] _zz_293; wire [0:0] _zz_294; - wire [3:0] _zz_295; - wire [2:0] _zz_296; - wire [31:0] _zz_297; - wire [2:0] _zz_298; - wire [31:0] _zz_299; - wire [31:0] _zz_300; - wire [11:0] _zz_301; - wire [11:0] _zz_302; - wire [11:0] _zz_303; + wire [0:0] _zz_295; + wire [0:0] _zz_296; + wire [0:0] _zz_297; + wire [0:0] _zz_298; + wire [0:0] _zz_299; + wire [3:0] _zz_300; + wire [2:0] _zz_301; + wire [31:0] _zz_302; + wire [2:0] _zz_303; wire [31:0] _zz_304; - wire [19:0] _zz_305; + wire [31:0] _zz_305; wire [11:0] _zz_306; - wire [2:0] _zz_307; - wire [2:0] _zz_308; - wire [0:0] _zz_309; - wire [2:0] _zz_310; - wire [4:0] _zz_311; - wire [11:0] _zz_312; - wire [11:0] _zz_313; - wire [31:0] _zz_314; - wire [31:0] _zz_315; - wire [31:0] _zz_316; - wire [31:0] _zz_317; - wire [31:0] _zz_318; + wire [11:0] _zz_307; + wire [11:0] _zz_308; + wire [31:0] _zz_309; + wire [19:0] _zz_310; + wire [11:0] _zz_311; + wire [2:0] _zz_312; + wire [2:0] _zz_313; + wire [0:0] _zz_314; + wire [2:0] _zz_315; + wire [4:0] _zz_316; + wire [11:0] _zz_317; + wire [11:0] _zz_318; wire [31:0] _zz_319; wire [31:0] _zz_320; - wire [11:0] _zz_321; - wire [19:0] _zz_322; - wire [11:0] _zz_323; - wire [2:0] _zz_324; - wire [1:0] _zz_325; - wire [1:0] _zz_326; - wire [65:0] _zz_327; - wire [65:0] _zz_328; - wire [31:0] _zz_329; - wire [31:0] _zz_330; - wire [0:0] _zz_331; - wire [5:0] _zz_332; - wire [32:0] _zz_333; + wire [31:0] _zz_321; + wire [31:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [11:0] _zz_326; + wire [19:0] _zz_327; + wire [11:0] _zz_328; + wire [2:0] _zz_329; + wire [1:0] _zz_330; + wire [1:0] _zz_331; + wire [65:0] _zz_332; + wire [65:0] _zz_333; wire [31:0] _zz_334; wire [31:0] _zz_335; - wire [32:0] _zz_336; - wire [32:0] _zz_337; + wire [0:0] _zz_336; + wire [5:0] _zz_337; wire [32:0] _zz_338; - wire [32:0] _zz_339; - wire [0:0] _zz_340; + wire [31:0] _zz_339; + wire [31:0] _zz_340; wire [32:0] _zz_341; - wire [0:0] _zz_342; + wire [32:0] _zz_342; wire [32:0] _zz_343; - wire [0:0] _zz_344; - wire [31:0] _zz_345; - wire [0:0] _zz_346; + wire [32:0] _zz_344; + wire [0:0] _zz_345; + wire [32:0] _zz_346; wire [0:0] _zz_347; - wire [0:0] _zz_348; + wire [32:0] _zz_348; wire [0:0] _zz_349; - wire [0:0] _zz_350; + wire [31:0] _zz_350; wire [0:0] _zz_351; wire [0:0] _zz_352; - wire [26:0] _zz_353; - wire _zz_354; - wire _zz_355; - wire [1:0] _zz_356; - wire [31:0] _zz_357; - wire [31:0] _zz_358; - wire [31:0] _zz_359; + wire [0:0] _zz_353; + wire [0:0] _zz_354; + wire [0:0] _zz_355; + wire [0:0] _zz_356; + wire [0:0] _zz_357; + wire [26:0] _zz_358; + wire _zz_359; wire _zz_360; - wire [0:0] _zz_361; - wire [13:0] _zz_362; + wire [1:0] _zz_361; + wire [31:0] _zz_362; wire [31:0] _zz_363; wire [31:0] _zz_364; - wire [31:0] _zz_365; - wire _zz_366; - wire [0:0] _zz_367; - wire [7:0] _zz_368; + wire _zz_365; + wire [0:0] _zz_366; + wire [13:0] _zz_367; + wire [31:0] _zz_368; wire [31:0] _zz_369; wire [31:0] _zz_370; - wire [31:0] _zz_371; - wire _zz_372; - wire [0:0] _zz_373; - wire [1:0] _zz_374; - wire _zz_375; - wire _zz_376; - wire [6:0] _zz_377; - wire [4:0] _zz_378; - wire _zz_379; - wire [4:0] _zz_380; - wire [0:0] _zz_381; - wire [7:0] _zz_382; - wire _zz_383; - wire [0:0] _zz_384; - wire [0:0] _zz_385; - wire [31:0] _zz_386; - wire [31:0] _zz_387; + wire _zz_371; + wire [0:0] _zz_372; + wire [7:0] _zz_373; + wire [31:0] _zz_374; + wire [31:0] _zz_375; + wire [31:0] _zz_376; + wire _zz_377; + wire [0:0] _zz_378; + wire [1:0] _zz_379; + wire _zz_380; + wire _zz_381; + wire [6:0] _zz_382; + wire [4:0] _zz_383; + wire _zz_384; + wire [4:0] _zz_385; + wire [0:0] _zz_386; + wire [7:0] _zz_387; wire _zz_388; wire [0:0] _zz_389; wire [0:0] _zz_390; - wire _zz_391; - wire [0:0] _zz_392; - wire [24:0] _zz_393; - wire [31:0] _zz_394; - wire _zz_395; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire _zz_393; + wire [0:0] _zz_394; + wire [0:0] _zz_395; wire _zz_396; wire [0:0] _zz_397; - wire [0:0] _zz_398; - wire [0:0] _zz_399; - wire [0:0] _zz_400; + wire [24:0] _zz_398; + wire [31:0] _zz_399; + wire _zz_400; wire _zz_401; wire [0:0] _zz_402; - wire [20:0] _zz_403; - wire [31:0] _zz_404; - wire [31:0] _zz_405; + wire [0:0] _zz_403; + wire [0:0] _zz_404; + wire [0:0] _zz_405; wire _zz_406; - wire _zz_407; - wire [0:0] _zz_408; - wire [1:0] _zz_409; - wire [0:0] _zz_410; - wire [0:0] _zz_411; + wire [0:0] _zz_407; + wire [20:0] _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire _zz_411; wire _zz_412; wire [0:0] _zz_413; - wire [17:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; - wire [31:0] _zz_418; - wire [31:0] _zz_419; + wire [1:0] _zz_414; + wire [0:0] _zz_415; + wire [0:0] _zz_416; + wire _zz_417; + wire [0:0] _zz_418; + wire [17:0] _zz_419; wire [31:0] _zz_420; wire [31:0] _zz_421; wire [31:0] _zz_422; - wire _zz_423; - wire [1:0] _zz_424; - wire [1:0] _zz_425; - wire _zz_426; - wire [0:0] _zz_427; - wire [14:0] _zz_428; - wire [31:0] _zz_429; - wire [31:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire [31:0] _zz_433; + wire [31:0] _zz_423; + wire [31:0] _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire [31:0] _zz_427; + wire _zz_428; + wire [1:0] _zz_429; + wire [1:0] _zz_430; + wire _zz_431; + wire [0:0] _zz_432; + wire [14:0] _zz_433; wire [31:0] _zz_434; - wire [0:0] _zz_435; - wire [0:0] _zz_436; - wire [4:0] _zz_437; - wire [4:0] _zz_438; - wire _zz_439; + wire [31:0] _zz_435; + wire [31:0] _zz_436; + wire [31:0] _zz_437; + wire [31:0] _zz_438; + wire [31:0] _zz_439; wire [0:0] _zz_440; - wire [11:0] _zz_441; - wire [31:0] _zz_442; - wire [31:0] _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire _zz_446; - wire [0:0] _zz_447; - wire [1:0] _zz_448; + wire [0:0] _zz_441; + wire [4:0] _zz_442; + wire [4:0] _zz_443; + wire _zz_444; + wire [0:0] _zz_445; + wire [11:0] _zz_446; + wire [31:0] _zz_447; + wire [31:0] _zz_448; wire [31:0] _zz_449; wire [31:0] _zz_450; - wire [0:0] _zz_451; - wire [3:0] _zz_452; - wire [4:0] _zz_453; - wire [4:0] _zz_454; - wire _zz_455; + wire _zz_451; + wire [0:0] _zz_452; + wire [1:0] _zz_453; + wire [31:0] _zz_454; + wire [31:0] _zz_455; wire [0:0] _zz_456; - wire [8:0] _zz_457; - wire [31:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire _zz_461; - wire _zz_462; + wire [3:0] _zz_457; + wire [4:0] _zz_458; + wire [4:0] _zz_459; + wire _zz_460; + wire [0:0] _zz_461; + wire [8:0] _zz_462; wire [31:0] _zz_463; wire [31:0] _zz_464; - wire [0:0] _zz_465; - wire [1:0] _zz_466; - wire [0:0] _zz_467; - wire [2:0] _zz_468; - wire [0:0] _zz_469; - wire [4:0] _zz_470; + wire [31:0] _zz_465; + wire _zz_466; + wire _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [0:0] _zz_470; wire [1:0] _zz_471; - wire [1:0] _zz_472; - wire _zz_473; + wire [0:0] _zz_472; + wire [2:0] _zz_473; wire [0:0] _zz_474; - wire [6:0] _zz_475; - wire [31:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; - wire [31:0] _zz_479; - wire _zz_480; - wire _zz_481; + wire [4:0] _zz_475; + wire [1:0] _zz_476; + wire [1:0] _zz_477; + wire _zz_478; + wire [0:0] _zz_479; + wire [6:0] _zz_480; + wire [31:0] _zz_481; wire [31:0] _zz_482; wire [31:0] _zz_483; - wire _zz_484; - wire [0:0] _zz_485; - wire [0:0] _zz_486; - wire _zz_487; - wire [0:0] _zz_488; - wire [2:0] _zz_489; - wire _zz_490; + wire [31:0] _zz_484; + wire _zz_485; + wire _zz_486; + wire [31:0] _zz_487; + wire [31:0] _zz_488; + wire _zz_489; + wire [0:0] _zz_490; wire [0:0] _zz_491; - wire [0:0] _zz_492; + wire _zz_492; wire [0:0] _zz_493; - wire [0:0] _zz_494; + wire [2:0] _zz_494; wire _zz_495; wire [0:0] _zz_496; - wire [4:0] _zz_497; - wire [31:0] _zz_498; - wire [31:0] _zz_499; - wire [31:0] _zz_500; - wire [31:0] _zz_501; - wire [31:0] _zz_502; + wire [0:0] _zz_497; + wire [0:0] _zz_498; + wire [0:0] _zz_499; + wire _zz_500; + wire [0:0] _zz_501; + wire [4:0] _zz_502; wire [31:0] _zz_503; wire [31:0] _zz_504; wire [31:0] _zz_505; wire [31:0] _zz_506; wire [31:0] _zz_507; - wire _zz_508; - wire [0:0] _zz_509; - wire [0:0] _zz_510; + wire [31:0] _zz_508; + wire [31:0] _zz_509; + wire [31:0] _zz_510; wire [31:0] _zz_511; wire [31:0] _zz_512; - wire [31:0] _zz_513; - wire [31:0] _zz_514; - wire [31:0] _zz_515; - wire _zz_516; - wire [3:0] _zz_517; - wire [3:0] _zz_518; - wire _zz_519; - wire [0:0] _zz_520; - wire [2:0] _zz_521; - wire [31:0] _zz_522; - wire [31:0] _zz_523; - wire [31:0] _zz_524; - wire [31:0] _zz_525; - wire [31:0] _zz_526; + wire _zz_513; + wire [0:0] _zz_514; + wire [0:0] _zz_515; + wire [31:0] _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire [31:0] _zz_520; + wire _zz_521; + wire [3:0] _zz_522; + wire [3:0] _zz_523; + wire _zz_524; + wire [0:0] _zz_525; + wire [2:0] _zz_526; wire [31:0] _zz_527; - wire _zz_528; - wire [0:0] _zz_529; - wire [1:0] _zz_530; - wire _zz_531; - wire [2:0] _zz_532; - wire [2:0] _zz_533; - wire _zz_534; - wire [0:0] _zz_535; - wire [0:0] _zz_536; - wire [31:0] _zz_537; - wire [31:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire [31:0] _zz_541; + wire [31:0] _zz_528; + wire [31:0] _zz_529; + wire [31:0] _zz_530; + wire [31:0] _zz_531; + wire [31:0] _zz_532; + wire _zz_533; + wire [0:0] _zz_534; + wire [1:0] _zz_535; + wire _zz_536; + wire [2:0] _zz_537; + wire [2:0] _zz_538; + wire _zz_539; + wire [0:0] _zz_540; + wire [0:0] _zz_541; wire [31:0] _zz_542; wire [31:0] _zz_543; - wire _zz_544; - wire _zz_545; - wire _zz_546; - wire [0:0] _zz_547; - wire [0:0] _zz_548; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; wire _zz_549; wire _zz_550; wire _zz_551; - wire _zz_552; - wire [31:0] _zz_553; + wire [0:0] _zz_552; + wire [0:0] _zz_553; + wire _zz_554; + wire _zz_555; + wire _zz_556; + wire _zz_557; + wire [31:0] _zz_558; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -994,35 +994,30 @@ module VexRiscv ( reg [31:0] _zz_129; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_130; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_131; - wire _zz_132; - wire _zz_133; - wire _zz_134; - wire _zz_135; + reg _zz_131; + reg _zz_132; + reg _zz_133; + reg [4:0] _zz_134; + reg [31:0] _zz_135; wire _zz_136; + wire _zz_137; + wire _zz_138; + wire _zz_139; + wire _zz_140; + wire _zz_141; wire execute_BranchPlugin_eq; - wire [2:0] _zz_137; - reg _zz_138; - reg _zz_139; + wire [2:0] _zz_142; + reg _zz_143; + reg _zz_144; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_140; - reg [19:0] _zz_141; - wire _zz_142; - reg [10:0] _zz_143; - wire _zz_144; - reg [18:0] _zz_145; + wire _zz_145; + reg [19:0] _zz_146; + wire _zz_147; + reg [10:0] _zz_148; + wire _zz_149; + reg [18:0] _zz_150; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1044,9 +1039,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_146; - wire _zz_147; - wire _zz_148; + wire _zz_151; + wire _zz_152; + wire _zz_153; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1059,8 +1054,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_149; - wire _zz_150; + wire [1:0] _zz_154; + wire _zz_155; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1113,18 +1108,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_151; + wire [31:0] _zz_156; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_152; - wire _zz_153; - wire _zz_154; - reg [32:0] _zz_155; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_156; wire [31:0] _zz_157; + wire _zz_158; + wire _zz_159; + reg [32:0] _zz_160; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_161; + wire [31:0] _zz_162; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1212,11 +1207,6 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3202; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; reg [31:0] _zz_163; reg [31:0] _zz_164; reg [31:0] _zz_165; @@ -1235,16 +1225,21 @@ module VexRiscv ( reg [31:0] _zz_178; reg [31:0] _zz_179; reg [31:0] _zz_180; - reg [2:0] _zz_181; - reg _zz_182; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [2:0] _zz_186; + reg _zz_187; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_183; - wire _zz_184; - wire _zz_185; - wire _zz_186; - wire _zz_187; - wire _zz_188; - reg _zz_189; + reg [2:0] _zz_188; + wire _zz_189; + wire _zz_190; + wire _zz_191; + wire _zz_192; + wire _zz_193; + reg _zz_194; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] _zz_1_string; @@ -1329,347 +1324,347 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_222 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_223 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_224 = 1'b1; - assign _zz_225 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_226 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_227 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_228 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_229 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_230 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_231 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_232 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_233 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_234 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_235 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_236 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_237 = (IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); - assign _zz_238 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_239 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_240 = (1'b0 || (! 1'b1)); - assign _zz_241 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_242 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_243 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_244 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_245 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_246 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_247 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_248 = execute_INSTRUCTION[13 : 12]; - assign _zz_249 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_250 = (! memory_arbitration_isStuck); - assign _zz_251 = (iBus_cmd_valid || (_zz_181 != 3'b000)); - assign _zz_252 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); - assign _zz_253 = (_zz_218 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_254 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_255 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_256 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_257 = ((_zz_148 && 1'b1) && (! 1'b0)); - assign _zz_258 = {_zz_64[1 : 0],_zz_64[15 : 13]}; - assign _zz_259 = _zz_64[6 : 5]; - assign _zz_260 = _zz_64[11 : 10]; - assign _zz_261 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_262 = execute_INSTRUCTION[13]; - assign _zz_263 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_264 = ($signed(_zz_265) + $signed(_zz_270)); - assign _zz_265 = ($signed(_zz_266) + $signed(_zz_268)); - assign _zz_266 = 52'h0; - assign _zz_267 = {1'b0,memory_MUL_LL}; - assign _zz_268 = {{19{_zz_267[32]}}, _zz_267}; - assign _zz_269 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_270 = {{2{_zz_269[49]}}, _zz_269}; - assign _zz_271 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_272 = {{2{_zz_271[49]}}, _zz_271}; - assign _zz_273 = ($signed(_zz_275) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_274 = _zz_273[31 : 0]; - assign _zz_275 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_276 = _zz_109[31 : 31]; - assign _zz_277 = _zz_109[30 : 30]; - assign _zz_278 = _zz_109[29 : 29]; - assign _zz_279 = _zz_109[28 : 28]; - assign _zz_280 = _zz_109[25 : 25]; - assign _zz_281 = _zz_109[17 : 17]; - assign _zz_282 = _zz_109[16 : 16]; - assign _zz_283 = _zz_109[13 : 13]; - assign _zz_284 = _zz_109[12 : 12]; - assign _zz_285 = _zz_109[11 : 11]; - assign _zz_286 = (decode_IS_RVC ? 3'b010 : 3'b100); - assign _zz_287 = {29'd0, _zz_286}; - assign _zz_288 = _zz_109[15 : 15]; - assign _zz_289 = _zz_109[5 : 5]; - assign _zz_290 = _zz_109[3 : 3]; - assign _zz_291 = _zz_109[20 : 20]; - assign _zz_292 = _zz_109[10 : 10]; - assign _zz_293 = _zz_109[4 : 4]; - assign _zz_294 = _zz_109[0 : 0]; - assign _zz_295 = (_zz_54 - 4'b0001); - assign _zz_296 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_297 = {29'd0, _zz_296}; - assign _zz_298 = (decode_IS_RVC ? 3'b010 : 3'b100); - assign _zz_299 = {29'd0, _zz_298}; - assign _zz_300 = {{_zz_74,_zz_64[6 : 2]},12'h0}; - assign _zz_301 = {{{4'b0000,_zz_64[8 : 7]},_zz_64[12 : 9]},2'b00}; - assign _zz_302 = {{{4'b0000,_zz_64[8 : 7]},_zz_64[12 : 9]},2'b00}; - assign _zz_303 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_304 = {{_zz_97,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_305 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_306 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_307 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_308 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_309 = execute_SRC_LESS; - assign _zz_310 = (execute_IS_RVC ? 3'b010 : 3'b100); - assign _zz_311 = execute_INSTRUCTION[19 : 15]; - assign _zz_312 = execute_INSTRUCTION[31 : 20]; - assign _zz_313 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_314 = ($signed(_zz_315) + $signed(_zz_318)); - assign _zz_315 = ($signed(_zz_316) + $signed(_zz_317)); - assign _zz_316 = execute_SRC1; - assign _zz_317 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_318 = (execute_SRC_USE_SUB_LESS ? _zz_319 : _zz_320); - assign _zz_319 = 32'h00000001; - assign _zz_320 = 32'h0; - assign _zz_321 = execute_INSTRUCTION[31 : 20]; - assign _zz_322 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_323 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_324 = (execute_IS_RVC ? 3'b010 : 3'b100); - assign _zz_325 = (_zz_149 & (~ _zz_326)); - assign _zz_326 = (_zz_149 - 2'b01); - assign _zz_327 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_328 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_329 = writeBack_MUL_LOW[31 : 0]; - assign _zz_330 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_331 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_332 = {5'd0, _zz_331}; - assign _zz_333 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_334 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_335 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_336 = {_zz_151,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_337 = _zz_338; - assign _zz_338 = _zz_339; - assign _zz_339 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_152) : _zz_152)} + _zz_341); - assign _zz_340 = memory_DivPlugin_div_needRevert; - assign _zz_341 = {32'd0, _zz_340}; - assign _zz_342 = _zz_154; - assign _zz_343 = {32'd0, _zz_342}; - assign _zz_344 = _zz_153; - assign _zz_345 = {31'd0, _zz_344}; - assign _zz_346 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_347 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_348 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_349 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_350 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_351 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_352 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_353 = (iBus_cmd_payload_address >>> 5); - assign _zz_354 = 1'b1; - assign _zz_355 = 1'b1; - assign _zz_356 = {_zz_58,_zz_57}; - assign _zz_357 = 32'h0000107f; - assign _zz_358 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_359 = 32'h00002073; - assign _zz_360 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_361 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_362 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_363) == 32'h00000003),{(_zz_364 == _zz_365),{_zz_366,{_zz_367,_zz_368}}}}}}; - assign _zz_363 = 32'h0000505f; - assign _zz_364 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_365 = 32'h00000063; - assign _zz_366 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_367 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_368 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_369) == 32'h00001013),{(_zz_370 == _zz_371),{_zz_372,{_zz_373,_zz_374}}}}}}; - assign _zz_369 = 32'hfc00307f; - assign _zz_370 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_371 = 32'h00005033; - assign _zz_372 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_373 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_374 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; - assign _zz_375 = (_zz_64[11 : 10] == 2'b01); - assign _zz_376 = ((_zz_64[11 : 10] == 2'b11) && (_zz_64[6 : 5] == 2'b00)); - assign _zz_377 = 7'h0; - assign _zz_378 = _zz_64[6 : 2]; - assign _zz_379 = _zz_64[12]; - assign _zz_380 = _zz_64[11 : 7]; - assign _zz_381 = decode_INSTRUCTION[31]; - assign _zz_382 = decode_INSTRUCTION[19 : 12]; - assign _zz_383 = decode_INSTRUCTION[20]; - assign _zz_384 = decode_INSTRUCTION[31]; - assign _zz_385 = decode_INSTRUCTION[7]; - assign _zz_386 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_387 = 32'h02004020; - assign _zz_388 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_389 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); - assign _zz_390 = 1'b0; - assign _zz_391 = (((decode_INSTRUCTION & _zz_394) == 32'h00000050) != 1'b0); - assign _zz_392 = ({_zz_395,_zz_396} != 2'b00); - assign _zz_393 = {({_zz_397,_zz_398} != 2'b00),{(_zz_399 != _zz_400),{_zz_401,{_zz_402,_zz_403}}}}; - assign _zz_394 = 32'h00403050; - assign _zz_395 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_396 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_397 = _zz_112; - assign _zz_398 = ((decode_INSTRUCTION & _zz_404) == 32'h00000004); - assign _zz_399 = ((decode_INSTRUCTION & _zz_405) == 32'h00000040); - assign _zz_400 = 1'b0; - assign _zz_401 = ({_zz_406,_zz_407} != 2'b00); - assign _zz_402 = ({_zz_408,_zz_409} != 3'b000); - assign _zz_403 = {(_zz_410 != _zz_411),{_zz_412,{_zz_413,_zz_414}}}; - assign _zz_404 = 32'h0000001c; - assign _zz_405 = 32'h00000058; - assign _zz_406 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_407 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_408 = ((decode_INSTRUCTION & _zz_415) == 32'h40001010); - assign _zz_409 = {(_zz_416 == _zz_417),(_zz_418 == _zz_419)}; - assign _zz_410 = ((decode_INSTRUCTION & _zz_420) == 32'h00000024); - assign _zz_411 = 1'b0; - assign _zz_412 = ((_zz_421 == _zz_422) != 1'b0); - assign _zz_413 = (_zz_423 != 1'b0); - assign _zz_414 = {(_zz_424 != _zz_425),{_zz_426,{_zz_427,_zz_428}}}; - assign _zz_415 = 32'h40003054; - assign _zz_416 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_417 = 32'h00001010; - assign _zz_418 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_419 = 32'h00001010; - assign _zz_420 = 32'h00000064; - assign _zz_421 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_422 = 32'h00001000; - assign _zz_423 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_424 = {(_zz_429 == _zz_430),(_zz_431 == _zz_432)}; - assign _zz_425 = 2'b00; - assign _zz_426 = ((_zz_433 == _zz_434) != 1'b0); - assign _zz_427 = ({_zz_435,_zz_436} != 2'b00); - assign _zz_428 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; - assign _zz_429 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_430 = 32'h00002000; - assign _zz_431 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_432 = 32'h00001000; - assign _zz_433 = (decode_INSTRUCTION & 32'h00004048); - assign _zz_434 = 32'h00004008; - assign _zz_435 = ((decode_INSTRUCTION & _zz_442) == 32'h00000020); - assign _zz_436 = ((decode_INSTRUCTION & _zz_443) == 32'h00000020); - assign _zz_437 = {(_zz_444 == _zz_445),{_zz_446,{_zz_447,_zz_448}}}; - assign _zz_438 = 5'h0; - assign _zz_439 = ((_zz_449 == _zz_450) != 1'b0); - assign _zz_440 = ({_zz_451,_zz_452} != 5'h0); - assign _zz_441 = {(_zz_453 != _zz_454),{_zz_455,{_zz_456,_zz_457}}}; - assign _zz_442 = 32'h00000034; - assign _zz_443 = 32'h00000064; - assign _zz_444 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_445 = 32'h00002040; - assign _zz_446 = ((decode_INSTRUCTION & _zz_458) == 32'h00001040); - assign _zz_447 = (_zz_459 == _zz_460); - assign _zz_448 = {_zz_461,_zz_462}; - assign _zz_449 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_450 = 32'h00000020; - assign _zz_451 = (_zz_463 == _zz_464); - assign _zz_452 = {_zz_111,{_zz_465,_zz_466}}; - assign _zz_453 = {_zz_111,{_zz_467,_zz_468}}; - assign _zz_454 = 5'h0; - assign _zz_455 = ({_zz_469,_zz_470} != 6'h0); - assign _zz_456 = (_zz_471 != _zz_472); - assign _zz_457 = {_zz_473,{_zz_474,_zz_475}}; - assign _zz_458 = 32'h00001040; - assign _zz_459 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_460 = 32'h00000040; - assign _zz_461 = ((decode_INSTRUCTION & _zz_476) == 32'h00000040); - assign _zz_462 = ((decode_INSTRUCTION & _zz_477) == 32'h0); - assign _zz_463 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_464 = 32'h00000040; - assign _zz_465 = (_zz_478 == _zz_479); - assign _zz_466 = {_zz_480,_zz_481}; - assign _zz_467 = (_zz_482 == _zz_483); - assign _zz_468 = {_zz_484,{_zz_485,_zz_486}}; - assign _zz_469 = _zz_112; - assign _zz_470 = {_zz_487,{_zz_488,_zz_489}}; - assign _zz_471 = {_zz_111,_zz_490}; - assign _zz_472 = 2'b00; - assign _zz_473 = ({_zz_491,_zz_492} != 2'b00); - assign _zz_474 = (_zz_493 != _zz_494); - assign _zz_475 = {_zz_495,{_zz_496,_zz_497}}; - assign _zz_476 = 32'h00400040; - assign _zz_477 = 32'h00000038; - assign _zz_478 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_479 = 32'h00004020; - assign _zz_480 = ((decode_INSTRUCTION & _zz_498) == 32'h00000010); - assign _zz_481 = ((decode_INSTRUCTION & _zz_499) == 32'h00000020); - assign _zz_482 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_483 = 32'h00002010; - assign _zz_484 = ((decode_INSTRUCTION & _zz_500) == 32'h00000010); - assign _zz_485 = (_zz_501 == _zz_502); - assign _zz_486 = (_zz_503 == _zz_504); - assign _zz_487 = ((decode_INSTRUCTION & _zz_505) == 32'h00001010); - assign _zz_488 = (_zz_506 == _zz_507); - assign _zz_489 = {_zz_508,{_zz_509,_zz_510}}; - assign _zz_490 = ((decode_INSTRUCTION & _zz_511) == 32'h00000020); - assign _zz_491 = _zz_111; - assign _zz_492 = (_zz_512 == _zz_513); - assign _zz_493 = (_zz_514 == _zz_515); - assign _zz_494 = 1'b0; - assign _zz_495 = (_zz_516 != 1'b0); - assign _zz_496 = (_zz_517 != _zz_518); - assign _zz_497 = {_zz_519,{_zz_520,_zz_521}}; - assign _zz_498 = 32'h00000030; - assign _zz_499 = 32'h02000020; - assign _zz_500 = 32'h00001030; - assign _zz_501 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_502 = 32'h00002020; - assign _zz_503 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_504 = 32'h00000020; - assign _zz_505 = 32'h00001010; - assign _zz_506 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_507 = 32'h00002010; - assign _zz_508 = ((decode_INSTRUCTION & _zz_522) == 32'h00000010); - assign _zz_509 = (_zz_523 == _zz_524); - assign _zz_510 = (_zz_525 == _zz_526); - assign _zz_511 = 32'h00000070; - assign _zz_512 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_513 = 32'h0; - assign _zz_514 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_515 = 32'h00004010; - assign _zz_516 = ((decode_INSTRUCTION & _zz_527) == 32'h00002010); - assign _zz_517 = {_zz_528,{_zz_529,_zz_530}}; - assign _zz_518 = 4'b0000; - assign _zz_519 = (_zz_531 != 1'b0); - assign _zz_520 = (_zz_532 != _zz_533); - assign _zz_521 = {_zz_534,{_zz_535,_zz_536}}; - assign _zz_522 = 32'h00000050; - assign _zz_523 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_524 = 32'h00000004; - assign _zz_525 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_526 = 32'h0; - assign _zz_527 = 32'h00006014; - assign _zz_528 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_529 = ((decode_INSTRUCTION & _zz_537) == 32'h0); - assign _zz_530 = {(_zz_538 == _zz_539),(_zz_540 == _zz_541)}; - assign _zz_531 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_532 = {(_zz_542 == _zz_543),{_zz_544,_zz_545}}; - assign _zz_533 = 3'b000; - assign _zz_534 = ({_zz_546,_zz_110} != 2'b00); - assign _zz_535 = ({_zz_547,_zz_548} != 2'b00); - assign _zz_536 = (_zz_549 != 1'b0); - assign _zz_537 = 32'h00000018; - assign _zz_538 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_539 = 32'h00002000; - assign _zz_540 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_541 = 32'h00001000; - assign _zz_542 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_543 = 32'h00000040; - assign _zz_544 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_545 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_546 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_547 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_548 = _zz_110; - assign _zz_549 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); - assign _zz_550 = execute_INSTRUCTION[31]; - assign _zz_551 = execute_INSTRUCTION[31]; - assign _zz_552 = execute_INSTRUCTION[7]; - assign _zz_553 = 32'h0; + assign _zz_227 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_228 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_229 = 1'b1; + assign _zz_230 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_231 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_232 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_233 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_234 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_235 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_236 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_237 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_238 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_239 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_240 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_241 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_242 = (IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); + assign _zz_243 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_244 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_245 = (1'b0 || (! 1'b1)); + assign _zz_246 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_247 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_248 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_249 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_250 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_251 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_252 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_253 = execute_INSTRUCTION[13 : 12]; + assign _zz_254 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_255 = (! memory_arbitration_isStuck); + assign _zz_256 = (iBus_cmd_valid || (_zz_186 != 3'b000)); + assign _zz_257 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); + assign _zz_258 = (_zz_223 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_259 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_260 = ((_zz_151 && 1'b1) && (! 1'b0)); + assign _zz_261 = ((_zz_152 && 1'b1) && (! 1'b0)); + assign _zz_262 = ((_zz_153 && 1'b1) && (! 1'b0)); + assign _zz_263 = {_zz_64[1 : 0],_zz_64[15 : 13]}; + assign _zz_264 = _zz_64[6 : 5]; + assign _zz_265 = _zz_64[11 : 10]; + assign _zz_266 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_267 = execute_INSTRUCTION[13]; + assign _zz_268 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_269 = ($signed(_zz_270) + $signed(_zz_275)); + assign _zz_270 = ($signed(_zz_271) + $signed(_zz_273)); + assign _zz_271 = 52'h0; + assign _zz_272 = {1'b0,memory_MUL_LL}; + assign _zz_273 = {{19{_zz_272[32]}}, _zz_272}; + assign _zz_274 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_275 = {{2{_zz_274[49]}}, _zz_274}; + assign _zz_276 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_277 = {{2{_zz_276[49]}}, _zz_276}; + assign _zz_278 = ($signed(_zz_280) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_279 = _zz_278[31 : 0]; + assign _zz_280 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_281 = _zz_109[31 : 31]; + assign _zz_282 = _zz_109[30 : 30]; + assign _zz_283 = _zz_109[29 : 29]; + assign _zz_284 = _zz_109[28 : 28]; + assign _zz_285 = _zz_109[25 : 25]; + assign _zz_286 = _zz_109[17 : 17]; + assign _zz_287 = _zz_109[16 : 16]; + assign _zz_288 = _zz_109[13 : 13]; + assign _zz_289 = _zz_109[12 : 12]; + assign _zz_290 = _zz_109[11 : 11]; + assign _zz_291 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_292 = {29'd0, _zz_291}; + assign _zz_293 = _zz_109[15 : 15]; + assign _zz_294 = _zz_109[5 : 5]; + assign _zz_295 = _zz_109[3 : 3]; + assign _zz_296 = _zz_109[20 : 20]; + assign _zz_297 = _zz_109[10 : 10]; + assign _zz_298 = _zz_109[4 : 4]; + assign _zz_299 = _zz_109[0 : 0]; + assign _zz_300 = (_zz_54 - 4'b0001); + assign _zz_301 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_302 = {29'd0, _zz_301}; + assign _zz_303 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_304 = {29'd0, _zz_303}; + assign _zz_305 = {{_zz_74,_zz_64[6 : 2]},12'h0}; + assign _zz_306 = {{{4'b0000,_zz_64[8 : 7]},_zz_64[12 : 9]},2'b00}; + assign _zz_307 = {{{4'b0000,_zz_64[8 : 7]},_zz_64[12 : 9]},2'b00}; + assign _zz_308 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_309 = {{_zz_97,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_310 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_311 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_312 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_313 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_314 = execute_SRC_LESS; + assign _zz_315 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz_316 = execute_INSTRUCTION[19 : 15]; + assign _zz_317 = execute_INSTRUCTION[31 : 20]; + assign _zz_318 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_319 = ($signed(_zz_320) + $signed(_zz_323)); + assign _zz_320 = ($signed(_zz_321) + $signed(_zz_322)); + assign _zz_321 = execute_SRC1; + assign _zz_322 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_323 = (execute_SRC_USE_SUB_LESS ? _zz_324 : _zz_325); + assign _zz_324 = 32'h00000001; + assign _zz_325 = 32'h0; + assign _zz_326 = execute_INSTRUCTION[31 : 20]; + assign _zz_327 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_329 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz_330 = (_zz_154 & (~ _zz_331)); + assign _zz_331 = (_zz_154 - 2'b01); + assign _zz_332 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_333 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_334 = writeBack_MUL_LOW[31 : 0]; + assign _zz_335 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_336 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_337 = {5'd0, _zz_336}; + assign _zz_338 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_339 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_340 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_341 = {_zz_156,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_342 = _zz_343; + assign _zz_343 = _zz_344; + assign _zz_344 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_157) : _zz_157)} + _zz_346); + assign _zz_345 = memory_DivPlugin_div_needRevert; + assign _zz_346 = {32'd0, _zz_345}; + assign _zz_347 = _zz_159; + assign _zz_348 = {32'd0, _zz_347}; + assign _zz_349 = _zz_158; + assign _zz_350 = {31'd0, _zz_349}; + assign _zz_351 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_352 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_353 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_354 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_355 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_356 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_357 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_358 = (iBus_cmd_payload_address >>> 5); + assign _zz_359 = 1'b1; + assign _zz_360 = 1'b1; + assign _zz_361 = {_zz_58,_zz_57}; + assign _zz_362 = 32'h0000107f; + assign _zz_363 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_364 = 32'h00002073; + assign _zz_365 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_366 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_367 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_368) == 32'h00000003),{(_zz_369 == _zz_370),{_zz_371,{_zz_372,_zz_373}}}}}}; + assign _zz_368 = 32'h0000505f; + assign _zz_369 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_370 = 32'h00000063; + assign _zz_371 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_372 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_373 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_374) == 32'h00001013),{(_zz_375 == _zz_376),{_zz_377,{_zz_378,_zz_379}}}}}}; + assign _zz_374 = 32'hfc00307f; + assign _zz_375 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_376 = 32'h00005033; + assign _zz_377 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_378 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_379 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_380 = (_zz_64[11 : 10] == 2'b01); + assign _zz_381 = ((_zz_64[11 : 10] == 2'b11) && (_zz_64[6 : 5] == 2'b00)); + assign _zz_382 = 7'h0; + assign _zz_383 = _zz_64[6 : 2]; + assign _zz_384 = _zz_64[12]; + assign _zz_385 = _zz_64[11 : 7]; + assign _zz_386 = decode_INSTRUCTION[31]; + assign _zz_387 = decode_INSTRUCTION[19 : 12]; + assign _zz_388 = decode_INSTRUCTION[20]; + assign _zz_389 = decode_INSTRUCTION[31]; + assign _zz_390 = decode_INSTRUCTION[7]; + assign _zz_391 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_392 = 32'h02004020; + assign _zz_393 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_394 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); + assign _zz_395 = 1'b0; + assign _zz_396 = (((decode_INSTRUCTION & _zz_399) == 32'h00000050) != 1'b0); + assign _zz_397 = ({_zz_400,_zz_401} != 2'b00); + assign _zz_398 = {({_zz_402,_zz_403} != 2'b00),{(_zz_404 != _zz_405),{_zz_406,{_zz_407,_zz_408}}}}; + assign _zz_399 = 32'h00403050; + assign _zz_400 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_401 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_402 = _zz_112; + assign _zz_403 = ((decode_INSTRUCTION & _zz_409) == 32'h00000004); + assign _zz_404 = ((decode_INSTRUCTION & _zz_410) == 32'h00000040); + assign _zz_405 = 1'b0; + assign _zz_406 = ({_zz_411,_zz_412} != 2'b00); + assign _zz_407 = ({_zz_413,_zz_414} != 3'b000); + assign _zz_408 = {(_zz_415 != _zz_416),{_zz_417,{_zz_418,_zz_419}}}; + assign _zz_409 = 32'h0000001c; + assign _zz_410 = 32'h00000058; + assign _zz_411 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_412 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_413 = ((decode_INSTRUCTION & _zz_420) == 32'h40001010); + assign _zz_414 = {(_zz_421 == _zz_422),(_zz_423 == _zz_424)}; + assign _zz_415 = ((decode_INSTRUCTION & _zz_425) == 32'h00000024); + assign _zz_416 = 1'b0; + assign _zz_417 = ((_zz_426 == _zz_427) != 1'b0); + assign _zz_418 = (_zz_428 != 1'b0); + assign _zz_419 = {(_zz_429 != _zz_430),{_zz_431,{_zz_432,_zz_433}}}; + assign _zz_420 = 32'h40003054; + assign _zz_421 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_422 = 32'h00001010; + assign _zz_423 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_424 = 32'h00001010; + assign _zz_425 = 32'h00000064; + assign _zz_426 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_427 = 32'h00001000; + assign _zz_428 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_429 = {(_zz_434 == _zz_435),(_zz_436 == _zz_437)}; + assign _zz_430 = 2'b00; + assign _zz_431 = ((_zz_438 == _zz_439) != 1'b0); + assign _zz_432 = ({_zz_440,_zz_441} != 2'b00); + assign _zz_433 = {(_zz_442 != _zz_443),{_zz_444,{_zz_445,_zz_446}}}; + assign _zz_434 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_435 = 32'h00002000; + assign _zz_436 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_437 = 32'h00001000; + assign _zz_438 = (decode_INSTRUCTION & 32'h00004048); + assign _zz_439 = 32'h00004008; + assign _zz_440 = ((decode_INSTRUCTION & _zz_447) == 32'h00000020); + assign _zz_441 = ((decode_INSTRUCTION & _zz_448) == 32'h00000020); + assign _zz_442 = {(_zz_449 == _zz_450),{_zz_451,{_zz_452,_zz_453}}}; + assign _zz_443 = 5'h0; + assign _zz_444 = ((_zz_454 == _zz_455) != 1'b0); + assign _zz_445 = ({_zz_456,_zz_457} != 5'h0); + assign _zz_446 = {(_zz_458 != _zz_459),{_zz_460,{_zz_461,_zz_462}}}; + assign _zz_447 = 32'h00000034; + assign _zz_448 = 32'h00000064; + assign _zz_449 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_450 = 32'h00002040; + assign _zz_451 = ((decode_INSTRUCTION & _zz_463) == 32'h00001040); + assign _zz_452 = (_zz_464 == _zz_465); + assign _zz_453 = {_zz_466,_zz_467}; + assign _zz_454 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_455 = 32'h00000020; + assign _zz_456 = (_zz_468 == _zz_469); + assign _zz_457 = {_zz_111,{_zz_470,_zz_471}}; + assign _zz_458 = {_zz_111,{_zz_472,_zz_473}}; + assign _zz_459 = 5'h0; + assign _zz_460 = ({_zz_474,_zz_475} != 6'h0); + assign _zz_461 = (_zz_476 != _zz_477); + assign _zz_462 = {_zz_478,{_zz_479,_zz_480}}; + assign _zz_463 = 32'h00001040; + assign _zz_464 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_465 = 32'h00000040; + assign _zz_466 = ((decode_INSTRUCTION & _zz_481) == 32'h00000040); + assign _zz_467 = ((decode_INSTRUCTION & _zz_482) == 32'h0); + assign _zz_468 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_469 = 32'h00000040; + assign _zz_470 = (_zz_483 == _zz_484); + assign _zz_471 = {_zz_485,_zz_486}; + assign _zz_472 = (_zz_487 == _zz_488); + assign _zz_473 = {_zz_489,{_zz_490,_zz_491}}; + assign _zz_474 = _zz_112; + assign _zz_475 = {_zz_492,{_zz_493,_zz_494}}; + assign _zz_476 = {_zz_111,_zz_495}; + assign _zz_477 = 2'b00; + assign _zz_478 = ({_zz_496,_zz_497} != 2'b00); + assign _zz_479 = (_zz_498 != _zz_499); + assign _zz_480 = {_zz_500,{_zz_501,_zz_502}}; + assign _zz_481 = 32'h00400040; + assign _zz_482 = 32'h00000038; + assign _zz_483 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_484 = 32'h00004020; + assign _zz_485 = ((decode_INSTRUCTION & _zz_503) == 32'h00000010); + assign _zz_486 = ((decode_INSTRUCTION & _zz_504) == 32'h00000020); + assign _zz_487 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_488 = 32'h00002010; + assign _zz_489 = ((decode_INSTRUCTION & _zz_505) == 32'h00000010); + assign _zz_490 = (_zz_506 == _zz_507); + assign _zz_491 = (_zz_508 == _zz_509); + assign _zz_492 = ((decode_INSTRUCTION & _zz_510) == 32'h00001010); + assign _zz_493 = (_zz_511 == _zz_512); + assign _zz_494 = {_zz_513,{_zz_514,_zz_515}}; + assign _zz_495 = ((decode_INSTRUCTION & _zz_516) == 32'h00000020); + assign _zz_496 = _zz_111; + assign _zz_497 = (_zz_517 == _zz_518); + assign _zz_498 = (_zz_519 == _zz_520); + assign _zz_499 = 1'b0; + assign _zz_500 = (_zz_521 != 1'b0); + assign _zz_501 = (_zz_522 != _zz_523); + assign _zz_502 = {_zz_524,{_zz_525,_zz_526}}; + assign _zz_503 = 32'h00000030; + assign _zz_504 = 32'h02000020; + assign _zz_505 = 32'h00001030; + assign _zz_506 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_507 = 32'h00002020; + assign _zz_508 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_509 = 32'h00000020; + assign _zz_510 = 32'h00001010; + assign _zz_511 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_512 = 32'h00002010; + assign _zz_513 = ((decode_INSTRUCTION & _zz_527) == 32'h00000010); + assign _zz_514 = (_zz_528 == _zz_529); + assign _zz_515 = (_zz_530 == _zz_531); + assign _zz_516 = 32'h00000070; + assign _zz_517 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_518 = 32'h0; + assign _zz_519 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_520 = 32'h00004010; + assign _zz_521 = ((decode_INSTRUCTION & _zz_532) == 32'h00002010); + assign _zz_522 = {_zz_533,{_zz_534,_zz_535}}; + assign _zz_523 = 4'b0000; + assign _zz_524 = (_zz_536 != 1'b0); + assign _zz_525 = (_zz_537 != _zz_538); + assign _zz_526 = {_zz_539,{_zz_540,_zz_541}}; + assign _zz_527 = 32'h00000050; + assign _zz_528 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_529 = 32'h00000004; + assign _zz_530 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_531 = 32'h0; + assign _zz_532 = 32'h00006014; + assign _zz_533 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_534 = ((decode_INSTRUCTION & _zz_542) == 32'h0); + assign _zz_535 = {(_zz_543 == _zz_544),(_zz_545 == _zz_546)}; + assign _zz_536 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_537 = {(_zz_547 == _zz_548),{_zz_549,_zz_550}}; + assign _zz_538 = 3'b000; + assign _zz_539 = ({_zz_551,_zz_110} != 2'b00); + assign _zz_540 = ({_zz_552,_zz_553} != 2'b00); + assign _zz_541 = (_zz_554 != 1'b0); + assign _zz_542 = 32'h00000018; + assign _zz_543 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_544 = 32'h00002000; + assign _zz_545 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_546 = 32'h00001000; + assign _zz_547 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_548 = 32'h00000040; + assign _zz_549 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_550 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_551 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_552 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_553 = _zz_110; + assign _zz_554 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_555 = execute_INSTRUCTION[31]; + assign _zz_556 = execute_INSTRUCTION[31]; + assign _zz_557 = execute_INSTRUCTION[7]; + assign _zz_558 = 32'h0; always @ (posedge clk) begin - if(_zz_354) begin - _zz_219 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_359) begin + _zz_224 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_355) begin - _zz_220 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_360) begin + _zz_225 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1680,13 +1675,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_190 ), //i - .io_cpu_prefetch_isValid (_zz_191 ), //i + .io_flush (_zz_195 ), //i + .io_cpu_prefetch_isValid (_zz_196 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_192 ), //i - .io_cpu_fetch_isStuck (_zz_193 ), //i - .io_cpu_fetch_isRemoved (_zz_194 ), //i + .io_cpu_fetch_isValid (_zz_197 ), //i + .io_cpu_fetch_isStuck (_zz_198 ), //i + .io_cpu_fetch_isRemoved (_zz_199 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1703,13 +1698,13 @@ module VexRiscv ( .io_cpu_fetch_error (IBusCachedPlugin_cache_io_cpu_fetch_error ), //o .io_cpu_fetch_mmuRefilling (IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling ), //o .io_cpu_fetch_mmuException (IBusCachedPlugin_cache_io_cpu_fetch_mmuException ), //o - .io_cpu_fetch_isUser (_zz_195 ), //i - .io_cpu_decode_isValid (_zz_196 ), //i - .io_cpu_decode_isStuck (_zz_197 ), //i - .io_cpu_decode_pc (_zz_198[31:0] ), //i + .io_cpu_fetch_isUser (_zz_200 ), //i + .io_cpu_decode_isValid (_zz_201 ), //i + .io_cpu_decode_isStuck (_zz_202 ), //i + .io_cpu_decode_pc (_zz_203[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_fill_valid (_zz_199 ), //i + .io_cpu_fill_valid (_zz_204 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1722,20 +1717,20 @@ module VexRiscv ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_200 ), //i - .io_cpu_execute_address (_zz_201[31:0] ), //i + .io_cpu_execute_isValid (_zz_205 ), //i + .io_cpu_execute_address (_zz_206[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_104[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_202 ), //i + .io_cpu_memory_isValid (_zz_207 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_203[31:0] ), //i + .io_cpu_memory_address (_zz_208[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_204 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_209 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1743,31 +1738,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_205 ), //i + .io_cpu_writeBack_isValid (_zz_210 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_206 ), //i + .io_cpu_writeBack_isUser (_zz_211 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_207[31:0] ), //i + .io_cpu_writeBack_address (_zz_212[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_208 ), //i - .io_cpu_writeBack_fence_SR (_zz_209 ), //i - .io_cpu_writeBack_fence_SO (_zz_210 ), //i - .io_cpu_writeBack_fence_SI (_zz_211 ), //i - .io_cpu_writeBack_fence_PW (_zz_212 ), //i - .io_cpu_writeBack_fence_PR (_zz_213 ), //i - .io_cpu_writeBack_fence_PO (_zz_214 ), //i - .io_cpu_writeBack_fence_PI (_zz_215 ), //i - .io_cpu_writeBack_fence_FM (_zz_216[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_213 ), //i + .io_cpu_writeBack_fence_SR (_zz_214 ), //i + .io_cpu_writeBack_fence_SO (_zz_215 ), //i + .io_cpu_writeBack_fence_SI (_zz_216 ), //i + .io_cpu_writeBack_fence_PW (_zz_217 ), //i + .io_cpu_writeBack_fence_PR (_zz_218 ), //i + .io_cpu_writeBack_fence_PO (_zz_219 ), //i + .io_cpu_writeBack_fence_PI (_zz_220 ), //i + .io_cpu_writeBack_fence_FM (_zz_221[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_217 ), //i + .io_cpu_flush_valid (_zz_222 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_218 ), //i + .io_mem_cmd_ready (_zz_223 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1783,18 +1778,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_356) + case(_zz_361) 2'b00 : begin - _zz_221 = DBusCachedPlugin_redoBranch_payload; + _zz_226 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_221 = CsrPlugin_jumpInterface_payload; + _zz_226 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_221 = BranchPlugin_jumpInterface_payload; + _zz_226 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_221 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_226 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2486,7 +2481,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_264) + $signed(_zz_272)); + assign memory_MUL_LOW = ($signed(_zz_269) + $signed(_zz_277)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2494,38 +2489,38 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_274; + assign execute_SHIFT_RIGHT = _zz_279; assign execute_REGFILE_WRITE_DATA = _zz_122; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_201[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_206[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_276[0]; - assign decode_IS_RS1_SIGNED = _zz_277[0]; - assign decode_IS_DIV = _zz_278[0]; + assign decode_IS_RS2_SIGNED = _zz_281[0]; + assign decode_IS_RS1_SIGNED = _zz_282[0]; + assign decode_IS_DIV = _zz_283[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_279[0]; + assign decode_IS_MUL = _zz_284[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_280[0]; + assign decode_IS_CSR = _zz_285[0]; assign _zz_8 = _zz_9; assign _zz_10 = _zz_11; assign decode_SHIFT_CTRL = _zz_12; assign _zz_13 = _zz_14; assign decode_ALU_BITWISE_CTRL = _zz_15; assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_281[0]; - assign decode_MEMORY_MANAGMENT = _zz_282[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_286[0]; + assign decode_MEMORY_MANAGMENT = _zz_287[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_283[0]; + assign decode_MEMORY_WR = _zz_288[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_284[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_285[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_289[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_290[0]; assign decode_SRC2_CTRL = _zz_18; assign _zz_19 = _zz_20; assign decode_ALU_CTRL = _zz_21; @@ -2536,7 +2531,7 @@ module VexRiscv ( assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_287); + assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_292); assign memory_PC = execute_to_memory_PC; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; @@ -2558,14 +2553,14 @@ module VexRiscv ( assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_139; + assign execute_BRANCH_COND_RESULT = _zz_144; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_288[0]; - assign decode_RS1_USE = _zz_289[0]; + assign decode_RS2_USE = _zz_293[0]; + assign decode_RS1_USE = _zz_294[0]; always @ (*) begin _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_222)begin + if(_zz_227)begin _zz_31 = execute_CsrPlugin_readData; end end @@ -2578,28 +2573,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_133)begin + if((_zz_134 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_135; end end - if(_zz_223)begin - if(_zz_224)begin - if(_zz_132)begin + if(_zz_228)begin + if(_zz_229)begin + if(_zz_137)begin decode_RS2 = _zz_50; end end end - if(_zz_225)begin + if(_zz_230)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_134)begin + if(_zz_139)begin decode_RS2 = _zz_32; end end end - if(_zz_226)begin + if(_zz_231)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_136)begin + if(_zz_141)begin decode_RS2 = _zz_31; end end @@ -2608,28 +2603,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_133)begin + if((_zz_134 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_135; end end - if(_zz_223)begin - if(_zz_224)begin - if(_zz_131)begin + if(_zz_228)begin + if(_zz_229)begin + if(_zz_136)begin decode_RS1 = _zz_50; end end end - if(_zz_225)begin + if(_zz_230)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_133)begin + if(_zz_138)begin decode_RS1 = _zz_32; end end end - if(_zz_226)begin + if(_zz_231)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_135)begin + if(_zz_140)begin decode_RS1 = _zz_31; end end @@ -2651,7 +2646,7 @@ module VexRiscv ( end endcase end - if(_zz_227)begin + if(_zz_232)begin _zz_32 = memory_DivPlugin_div_result; end end @@ -2665,8 +2660,8 @@ module VexRiscv ( assign execute_SRC2_CTRL = _zz_36; assign execute_IS_RVC = decode_to_execute_IS_RVC; assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_290[0]; - assign decode_SRC_ADD_ZERO = _zz_291[0]; + assign decode_SRC_USE_SUB_LESS = _zz_295[0]; + assign decode_SRC_ADD_ZERO = _zz_296[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_38; @@ -2684,25 +2679,25 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_decompressor_output_payload_rsp_inst); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_292[0]; + decode_REGFILE_WRITE_VALID = _zz_297[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_357) == 32'h00001073),{(_zz_358 == _zz_359),{_zz_360,{_zz_361,_zz_362}}}}}}} != 21'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_362) == 32'h00001073),{(_zz_363 == _zz_364),{_zz_365,{_zz_366,_zz_367}}}}}}} != 21'h0); always @ (*) begin _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_263) + case(_zz_268) 2'b00 : begin - _zz_50 = _zz_329; + _zz_50 = _zz_334; end default : begin - _zz_50 = _zz_330; + _zz_50 = _zz_335; end endcase end @@ -2721,32 +2716,32 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_293[0]; - assign decode_FLUSH_ALL = _zz_294[0]; + assign decode_MEMORY_ENABLE = _zz_298[0]; + assign decode_FLUSH_ALL = _zz_299[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_228)begin + if(_zz_233)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_229)begin + if(_zz_234)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_230)begin + if(_zz_235)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_231)begin + if(_zz_236)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2780,7 +2775,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_131 || _zz_132)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2793,7 +2788,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_232)begin + if(_zz_237)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2807,22 +2802,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_232)begin + if(_zz_237)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_217 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_222 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_233)begin + if(_zz_238)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_222)begin + if(_zz_227)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2856,7 +2851,7 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_227)begin + if(_zz_232)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2912,10 +2907,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_234)begin + if(_zz_239)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_235)begin + if(_zz_240)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2929,10 +2924,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_234)begin + if(_zz_239)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_235)begin + if(_zz_240)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -2949,7 +2944,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_233)begin + if(_zz_238)begin CsrPlugin_inWfi = 1'b1; end end @@ -2957,21 +2952,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_234)begin + if(_zz_239)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_235)begin + if(_zz_240)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_234)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_239)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_235)begin - case(_zz_236) + if(_zz_240)begin + case(_zz_241) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2987,11 +2982,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_54 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_55 = (_zz_54 & (~ _zz_295)); + assign _zz_55 = (_zz_54 & (~ _zz_300)); assign _zz_56 = _zz_55[3]; assign _zz_57 = (_zz_55[1] || _zz_56); assign _zz_58 = (_zz_55[2] || _zz_56); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_221; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_226; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3011,7 +3006,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_297); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_302); if(IBusCachedPlugin_fetchPc_inc)begin IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end @@ -3038,12 +3033,12 @@ module VexRiscv ( assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; always @ (*) begin IBusCachedPlugin_decodePc_flushed = 1'b0; - if(_zz_237)begin + if(_zz_242)begin IBusCachedPlugin_decodePc_flushed = 1'b1; end end - assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_299); + assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_304); assign IBusCachedPlugin_decodePc_injectedDecode = 1'b0; always @ (*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; @@ -3117,8 +3112,8 @@ module VexRiscv ( assign IBusCachedPlugin_decompressor_isRvc = (IBusCachedPlugin_decompressor_raw[1 : 0] != 2'b11); assign _zz_64 = IBusCachedPlugin_decompressor_raw[15 : 0]; always @ (*) begin - IBusCachedPlugin_decompressor_decompressed = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - case(_zz_258) + IBusCachedPlugin_decompressor_decompressed = 32'h0; + case(_zz_263) 5'h0 : begin IBusCachedPlugin_decompressor_decompressed = {{{{{{{{{2'b00,_zz_64[10 : 7]},_zz_64[12 : 11]},_zz_64[5]},_zz_64[6]},2'b00},5'h02},3'b000},_zz_66},7'h13}; end @@ -3138,10 +3133,10 @@ module VexRiscv ( IBusCachedPlugin_decompressor_decompressed = {{{{_zz_69,5'h0},3'b000},_zz_64[11 : 7]},7'h13}; end 5'h0b : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_64[11 : 7] == 5'h02) ? {{{{{{{{{_zz_76,_zz_64[4 : 3]},_zz_64[5]},_zz_64[2]},_zz_64[6]},4'b0000},_zz_64[11 : 7]},3'b000},_zz_64[11 : 7]},7'h13} : {{_zz_300[31 : 12],_zz_64[11 : 7]},7'h37}); + IBusCachedPlugin_decompressor_decompressed = ((_zz_64[11 : 7] == 5'h02) ? {{{{{{{{{_zz_76,_zz_64[4 : 3]},_zz_64[5]},_zz_64[2]},_zz_64[6]},4'b0000},_zz_64[11 : 7]},3'b000},_zz_64[11 : 7]},7'h13} : {{_zz_305[31 : 12],_zz_64[11 : 7]},7'h37}); end 5'h0c : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_64[11 : 10] == 2'b10) ? _zz_90 : {{1'b0,(_zz_375 || _zz_376)},5'h0}),(((! _zz_64[11]) || _zz_86) ? _zz_64[6 : 2] : _zz_66)},_zz_65},_zz_88},_zz_65},(_zz_86 ? 7'h13 : 7'h33)}; + IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_64[11 : 10] == 2'b10) ? _zz_90 : {{1'b0,(_zz_380 || _zz_381)},5'h0}),(((! _zz_64[11]) || _zz_86) ? _zz_64[6 : 2] : _zz_66)},_zz_65},_zz_88},_zz_65},(_zz_86 ? 7'h13 : 7'h33)}; end 5'h0d : begin IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_79[20],_zz_79[10 : 1]},_zz_79[11]},_zz_79[19 : 12]},_zz_83},7'h6f}; @@ -3159,10 +3154,10 @@ module VexRiscv ( IBusCachedPlugin_decompressor_decompressed = {{{{{{{{4'b0000,_zz_64[3 : 2]},_zz_64[12]},_zz_64[6 : 4]},2'b00},_zz_85},3'b010},_zz_64[11 : 7]},7'h03}; end 5'h14 : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_64[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_64[6 : 2] == 5'h0) ? {{{{12'h0,_zz_64[11 : 7]},3'b000},(_zz_64[12] ? _zz_84 : _zz_83)},7'h67} : {{{{{_zz_377,_zz_378},(_zz_379 ? _zz_380 : _zz_83)},3'b000},_zz_64[11 : 7]},7'h33})); + IBusCachedPlugin_decompressor_decompressed = ((_zz_64[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_64[6 : 2] == 5'h0) ? {{{{12'h0,_zz_64[11 : 7]},3'b000},(_zz_64[12] ? _zz_84 : _zz_83)},7'h67} : {{{{{_zz_382,_zz_383},(_zz_384 ? _zz_385 : _zz_83)},3'b000},_zz_64[11 : 7]},7'h33})); end 5'h16 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_301[11 : 5],_zz_64[6 : 2]},_zz_85},3'b010},_zz_302[4 : 0]},7'h23}; + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_306[11 : 5],_zz_64[6 : 2]},_zz_85},3'b010},_zz_307[4 : 0]},7'h23}; end default : begin end @@ -3255,7 +3250,7 @@ module VexRiscv ( assign _zz_85 = 5'h02; assign _zz_86 = (_zz_64[11 : 10] != 2'b11); always @ (*) begin - case(_zz_259) + case(_zz_264) 2'b00 : begin _zz_87 = 3'b000; end @@ -3272,7 +3267,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_260) + case(_zz_265) 2'b00 : begin _zz_88 = 3'b101; end @@ -3317,7 +3312,7 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; - assign _zz_96 = _zz_303[11]; + assign _zz_96 = _zz_308[11]; always @ (*) begin _zz_97[18] = _zz_96; _zz_97[17] = _zz_96; @@ -3340,9 +3335,9 @@ module VexRiscv ( _zz_97[0] = _zz_96; end - assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_304[31])); + assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_309[31])); assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_98 = _zz_305[19]; + assign _zz_98 = _zz_310[19]; always @ (*) begin _zz_99[10] = _zz_98; _zz_99[9] = _zz_98; @@ -3357,7 +3352,7 @@ module VexRiscv ( _zz_99[0] = _zz_98; end - assign _zz_100 = _zz_306[11]; + assign _zz_100 = _zz_311[11]; always @ (*) begin _zz_101[18] = _zz_100; _zz_101[17] = _zz_100; @@ -3380,7 +3375,7 @@ module VexRiscv ( _zz_101[0] = _zz_100; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_99,{{{_zz_381,_zz_382},_zz_383},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_101,{{{_zz_384,_zz_385},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_99,{{{_zz_386,_zz_387},_zz_388},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_101,{{{_zz_389,_zz_390},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3389,50 +3384,50 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_191 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_192 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_193 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_192; + assign _zz_196 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_197 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_198 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_197; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_195 = (CsrPlugin_privilege == 2'b00); + assign _zz_200 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_231)begin + if(_zz_236)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_229)begin + if(_zz_234)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_199 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); - if(_zz_229)begin - _zz_199 = 1'b1; + _zz_204 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(_zz_234)begin + _zz_204 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_230)begin + if(_zz_235)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_228)begin + if(_zz_233)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_230)begin + if(_zz_235)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_228)begin + if(_zz_233)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3442,9 +3437,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_1_output_payload; - assign _zz_190 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_195 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_218 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_223 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3471,8 +3466,8 @@ module VexRiscv ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_200 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_201 = execute_SRC_ADD; + assign _zz_205 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_206 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3487,27 +3482,27 @@ module VexRiscv ( endcase end - assign _zz_217 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_202 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_203 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_202; + assign _zz_222 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_207 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_208 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_207; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_203; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_208; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_204 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_209 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_204 = 1'b1; + _zz_209 = 1'b1; end end - assign _zz_205 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_206 = (CsrPlugin_privilege == 2'b00); - assign _zz_207 = writeBack_REGFILE_WRITE_DATA; + assign _zz_210 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_211 = (CsrPlugin_privilege == 2'b00); + assign _zz_212 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_238)begin + if(_zz_243)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3517,7 +3512,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_238)begin + if(_zz_243)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3536,15 +3531,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_238)begin + if(_zz_243)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_307}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_312}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_308}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_313}; end end end @@ -3617,7 +3612,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_261) + case(_zz_266) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_106; end @@ -3652,7 +3647,7 @@ module VexRiscv ( assign _zz_111 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_112 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_113 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_109 = {(_zz_113 != 1'b0),{(_zz_113 != 1'b0),{((_zz_386 == _zz_387) != 1'b0),{(_zz_388 != 1'b0),{(_zz_389 != _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}}; + assign _zz_109 = {(_zz_113 != 1'b0),{(_zz_113 != 1'b0),{((_zz_391 == _zz_392) != 1'b0),{(_zz_393 != 1'b0),{(_zz_394 != _zz_395),{_zz_396,{_zz_397,_zz_398}}}}}}}; assign _zz_114 = _zz_109[2 : 1]; assign _zz_49 = _zz_114; assign _zz_115 = _zz_109[7 : 6]; @@ -3672,8 +3667,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_219; - assign decode_RegFilePlugin_rs2Data = _zz_220; + assign decode_RegFilePlugin_rs1Data = _zz_224; + assign decode_RegFilePlugin_rs2Data = _zz_225; always @ (*) begin lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); if(_zz_121)begin @@ -3715,7 +3710,7 @@ module VexRiscv ( _zz_122 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_122 = {31'd0, _zz_309}; + _zz_122 = {31'd0, _zz_314}; end default : begin _zz_122 = execute_SRC_ADD_SUB; @@ -3729,18 +3724,18 @@ module VexRiscv ( _zz_123 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_123 = {29'd0, _zz_310}; + _zz_123 = {29'd0, _zz_315}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_123 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_123 = {27'd0, _zz_311}; + _zz_123 = {27'd0, _zz_316}; end endcase end - assign _zz_124 = _zz_312[11]; + assign _zz_124 = _zz_317[11]; always @ (*) begin _zz_125[19] = _zz_124; _zz_125[18] = _zz_124; @@ -3764,7 +3759,7 @@ module VexRiscv ( _zz_125[0] = _zz_124; end - assign _zz_126 = _zz_313[11]; + assign _zz_126 = _zz_318[11]; always @ (*) begin _zz_127[19] = _zz_126; _zz_127[18] = _zz_126; @@ -3806,7 +3801,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_314; + execute_SrcPlugin_addSub = _zz_319; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3886,99 +3881,94 @@ module VexRiscv ( end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_239)begin - if(_zz_240)begin - if(_zz_131)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_131 = 1'b0; + if(_zz_244)begin + if(_zz_245)begin + if(_zz_136)begin + _zz_131 = 1'b1; end end end - if(_zz_241)begin - if(_zz_242)begin - if(_zz_133)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_246)begin + if(_zz_247)begin + if(_zz_138)begin + _zz_131 = 1'b1; end end end - if(_zz_243)begin - if(_zz_244)begin - if(_zz_135)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_248)begin + if(_zz_249)begin + if(_zz_140)begin + _zz_131 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_131 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_239)begin - if(_zz_240)begin - if(_zz_132)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_132 = 1'b0; + if(_zz_244)begin + if(_zz_245)begin + if(_zz_137)begin + _zz_132 = 1'b1; end end end - if(_zz_241)begin - if(_zz_242)begin - if(_zz_134)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_246)begin + if(_zz_247)begin + if(_zz_139)begin + _zz_132 = 1'b1; end end end - if(_zz_243)begin - if(_zz_244)begin - if(_zz_136)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_248)begin + if(_zz_249)begin + if(_zz_141)begin + _zz_132 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_132 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_131 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_132 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_133 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_134 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_135 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_136 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_136 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_137 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_138 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_139 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_140 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_141 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_137 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_137 == 3'b000)) begin - _zz_138 = execute_BranchPlugin_eq; - end else if((_zz_137 == 3'b001)) begin - _zz_138 = (! execute_BranchPlugin_eq); - end else if((((_zz_137 & 3'b101) == 3'b101))) begin - _zz_138 = (! execute_SRC_LESS); + assign _zz_142 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_142 == 3'b000)) begin + _zz_143 = execute_BranchPlugin_eq; + end else if((_zz_142 == 3'b001)) begin + _zz_143 = (! execute_BranchPlugin_eq); + end else if((((_zz_142 & 3'b101) == 3'b101))) begin + _zz_143 = (! execute_SRC_LESS); end else begin - _zz_138 = execute_SRC_LESS; + _zz_143 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_139 = 1'b0; + _zz_144 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_139 = 1'b1; + _zz_144 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_139 = 1'b1; + _zz_144 = 1'b1; end default : begin - _zz_139 = _zz_138; + _zz_144 = _zz_143; end endcase end @@ -3995,80 +3985,80 @@ module VexRiscv ( endcase end - assign _zz_140 = _zz_321[11]; + assign _zz_145 = _zz_326[11]; always @ (*) begin - _zz_141[19] = _zz_140; - _zz_141[18] = _zz_140; - _zz_141[17] = _zz_140; - _zz_141[16] = _zz_140; - _zz_141[15] = _zz_140; - _zz_141[14] = _zz_140; - _zz_141[13] = _zz_140; - _zz_141[12] = _zz_140; - _zz_141[11] = _zz_140; - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; + _zz_146[19] = _zz_145; + _zz_146[18] = _zz_145; + _zz_146[17] = _zz_145; + _zz_146[16] = _zz_145; + _zz_146[15] = _zz_145; + _zz_146[14] = _zz_145; + _zz_146[13] = _zz_145; + _zz_146[12] = _zz_145; + _zz_146[11] = _zz_145; + _zz_146[10] = _zz_145; + _zz_146[9] = _zz_145; + _zz_146[8] = _zz_145; + _zz_146[7] = _zz_145; + _zz_146[6] = _zz_145; + _zz_146[5] = _zz_145; + _zz_146[4] = _zz_145; + _zz_146[3] = _zz_145; + _zz_146[2] = _zz_145; + _zz_146[1] = _zz_145; + _zz_146[0] = _zz_145; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_141,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_146,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_143,{{{_zz_550,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_145,{{{_zz_551,_zz_552},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_148,{{{_zz_555,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_150,{{{_zz_556,_zz_557},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_324}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_329}; end end endcase end - assign _zz_142 = _zz_322[19]; - always @ (*) begin - _zz_143[10] = _zz_142; - _zz_143[9] = _zz_142; - _zz_143[8] = _zz_142; - _zz_143[7] = _zz_142; - _zz_143[6] = _zz_142; - _zz_143[5] = _zz_142; - _zz_143[4] = _zz_142; - _zz_143[3] = _zz_142; - _zz_143[2] = _zz_142; - _zz_143[1] = _zz_142; - _zz_143[0] = _zz_142; - end - - assign _zz_144 = _zz_323[11]; - always @ (*) begin - _zz_145[18] = _zz_144; - _zz_145[17] = _zz_144; - _zz_145[16] = _zz_144; - _zz_145[15] = _zz_144; - _zz_145[14] = _zz_144; - _zz_145[13] = _zz_144; - _zz_145[12] = _zz_144; - _zz_145[11] = _zz_144; - _zz_145[10] = _zz_144; - _zz_145[9] = _zz_144; - _zz_145[8] = _zz_144; - _zz_145[7] = _zz_144; - _zz_145[6] = _zz_144; - _zz_145[5] = _zz_144; - _zz_145[4] = _zz_144; - _zz_145[3] = _zz_144; - _zz_145[2] = _zz_144; - _zz_145[1] = _zz_144; - _zz_145[0] = _zz_144; + assign _zz_147 = _zz_327[19]; + always @ (*) begin + _zz_148[10] = _zz_147; + _zz_148[9] = _zz_147; + _zz_148[8] = _zz_147; + _zz_148[7] = _zz_147; + _zz_148[6] = _zz_147; + _zz_148[5] = _zz_147; + _zz_148[4] = _zz_147; + _zz_148[3] = _zz_147; + _zz_148[2] = _zz_147; + _zz_148[1] = _zz_147; + _zz_148[0] = _zz_147; + end + + assign _zz_149 = _zz_328[11]; + always @ (*) begin + _zz_150[18] = _zz_149; + _zz_150[17] = _zz_149; + _zz_150[16] = _zz_149; + _zz_150[15] = _zz_149; + _zz_150[14] = _zz_149; + _zz_150[13] = _zz_149; + _zz_150[12] = _zz_149; + _zz_150[11] = _zz_149; + _zz_150[10] = _zz_149; + _zz_150[9] = _zz_149; + _zz_150[8] = _zz_149; + _zz_150[7] = _zz_149; + _zz_150[6] = _zz_149; + _zz_150[5] = _zz_149; + _zz_150[4] = _zz_149; + _zz_150[3] = _zz_149; + _zz_150[2] = _zz_149; + _zz_150[1] = _zz_149; + _zz_150[0] = _zz_149; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -4082,16 +4072,16 @@ module VexRiscv ( end end - assign _zz_146 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_147 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_148 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_151 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_152 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_153 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_149 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_150 = _zz_325[0]; + assign _zz_154 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_155 = _zz_330[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_232)begin + if(_zz_237)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4169,7 +4159,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4275,7 +4265,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_245)begin + if(_zz_250)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4294,20 +4284,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_246)begin + if(_zz_251)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_247)begin + if(_zz_252)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_246)begin + if(_zz_251)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_247)begin + if(_zz_252)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4322,14 +4312,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_245)begin + if(_zz_250)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_245)begin + if(_zz_250)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4338,7 +4328,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_262) + case(_zz_267) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4352,7 +4342,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_248) + case(_zz_253) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4366,7 +4356,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_248) + case(_zz_253) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4385,12 +4375,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_327) + $signed(_zz_328)); + assign writeBack_MulPlugin_result = ($signed(_zz_332) + $signed(_zz_333)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_227)begin - if(_zz_249)begin + if(_zz_232)begin + if(_zz_254)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4398,7 +4388,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_250)begin + if(_zz_255)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4409,28 +4399,28 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_332); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_337); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_151 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_151[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_333); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_334 : _zz_335); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_336[31:0]; - assign _zz_152 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_153 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_154 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_156 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_156[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_338); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_339 : _zz_340); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_341[31:0]; + assign _zz_157 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_158 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_159 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_155[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_155[31 : 0] = execute_RS1; + _zz_160[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_160[31 : 0] = execute_RS1; end - assign _zz_157 = (_zz_156 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_157 != 32'h0); + assign _zz_162 = (_zz_161 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_162 != 32'h0); assign _zz_26 = decode_SRC1_CTRL; assign _zz_24 = _zz_49; assign _zz_37 = decode_to_execute_SRC1_CTRL; @@ -4479,216 +4469,216 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_158 = 32'h0; + _zz_163 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_158[12 : 0] = 13'h1000; - _zz_158[25 : 20] = 6'h20; + _zz_163[12 : 0] = 13'h1000; + _zz_163[25 : 20] = 6'h20; end end always @ (*) begin - _zz_159 = 32'h0; + _zz_164 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_159[3 : 0] = 4'b1011; + _zz_164[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_160 = 32'h0; + _zz_165 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_160[4 : 0] = 5'h16; + _zz_165[4 : 0] = 5'h16; end end always @ (*) begin - _zz_161 = 32'h0; + _zz_166 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_161[5 : 0] = 6'h21; + _zz_166[5 : 0] = 6'h21; end end always @ (*) begin - _zz_162 = 32'h0; + _zz_167 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_162[31 : 30] = CsrPlugin_misa_base; - _zz_162[25 : 0] = CsrPlugin_misa_extensions; + _zz_167[31 : 30] = CsrPlugin_misa_base; + _zz_167[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_163 = 32'h0; + _zz_168 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_163[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_163[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_163[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_168[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_168[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_168[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_164 = 32'h0; + _zz_169 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_164[11 : 11] = CsrPlugin_mip_MEIP; - _zz_164[7 : 7] = CsrPlugin_mip_MTIP; - _zz_164[3 : 3] = CsrPlugin_mip_MSIP; + _zz_169[11 : 11] = CsrPlugin_mip_MEIP; + _zz_169[7 : 7] = CsrPlugin_mip_MTIP; + _zz_169[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_165 = 32'h0; + _zz_170 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_165[11 : 11] = CsrPlugin_mie_MEIE; - _zz_165[7 : 7] = CsrPlugin_mie_MTIE; - _zz_165[3 : 3] = CsrPlugin_mie_MSIE; + _zz_170[11 : 11] = CsrPlugin_mie_MEIE; + _zz_170[7 : 7] = CsrPlugin_mie_MTIE; + _zz_170[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_166 = 32'h0; + _zz_171 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_166[31 : 2] = CsrPlugin_mtvec_base; - _zz_166[1 : 0] = CsrPlugin_mtvec_mode; + _zz_171[31 : 2] = CsrPlugin_mtvec_base; + _zz_171[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_167 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_167[31 : 0] = CsrPlugin_mepc; + _zz_172[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_168 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_168[31 : 0] = CsrPlugin_mscratch; + _zz_173[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_169 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_169[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_169[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_174[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_174[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_170 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_170[31 : 0] = CsrPlugin_mtval; + _zz_175[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_171[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_176[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_172[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_177[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_173[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_178[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_174[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_179[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_175[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_180[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_176[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_181[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_177[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_182[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_178[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_183[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_179[31 : 0] = _zz_156; + _zz_184[31 : 0] = _zz_161; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_180[31 : 0] = _zz_157; + _zz_185[31 : 0] = _zz_162; end end - assign execute_CsrPlugin_readData = (((((_zz_158 | _zz_159) | (_zz_160 | _zz_161)) | ((_zz_553 | _zz_162) | (_zz_163 | _zz_164))) | (((_zz_165 | _zz_166) | (_zz_167 | _zz_168)) | ((_zz_169 | _zz_170) | (_zz_171 | _zz_172)))) | (((_zz_173 | _zz_174) | (_zz_175 | _zz_176)) | ((_zz_177 | _zz_178) | (_zz_179 | _zz_180)))); - assign iBusWishbone_ADR = {_zz_353,_zz_181}; - assign iBusWishbone_CTI = ((_zz_181 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_163 | _zz_164) | (_zz_165 | _zz_166)) | ((_zz_558 | _zz_167) | (_zz_168 | _zz_169))) | (((_zz_170 | _zz_171) | (_zz_172 | _zz_173)) | ((_zz_174 | _zz_175) | (_zz_176 | _zz_177)))) | (((_zz_178 | _zz_179) | (_zz_180 | _zz_181)) | ((_zz_182 | _zz_183) | (_zz_184 | _zz_185)))); + assign iBusWishbone_ADR = {_zz_358,_zz_186}; + assign iBusWishbone_CTI = ((_zz_186 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_251)begin + if(_zz_256)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_251)begin + if(_zz_256)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_182; + assign iBus_rsp_valid = _zz_187; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_188 = (dBus_cmd_payload_length != 3'b000); - assign _zz_184 = dBus_cmd_valid; - assign _zz_186 = dBus_cmd_payload_wr; - assign _zz_187 = (_zz_183 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_185 && (_zz_186 || _zz_187)); - assign dBusWishbone_ADR = ((_zz_188 ? {{dBus_cmd_payload_address[31 : 5],_zz_183},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_188 ? (_zz_187 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_193 = (dBus_cmd_payload_length != 3'b000); + assign _zz_189 = dBus_cmd_valid; + assign _zz_191 = dBus_cmd_payload_wr; + assign _zz_192 = (_zz_188 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_190 && (_zz_191 || _zz_192)); + assign dBusWishbone_ADR = ((_zz_193 ? {{dBus_cmd_payload_address[31 : 5],_zz_188},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_193 ? (_zz_192 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_186 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_186; + assign dBusWishbone_SEL = (_zz_191 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_191; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_185 = (_zz_184 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_184; - assign dBusWishbone_STB = _zz_184; - assign dBus_rsp_valid = _zz_189; + assign _zz_190 = (_zz_189 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_189; + assign dBusWishbone_STB = _zz_189; + assign dBus_rsp_valid = _zz_194; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4713,7 +4703,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= _zz_103; DBusCachedPlugin_rspCounter <= 32'h0; _zz_121 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_133 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4734,14 +4724,14 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_156 <= 32'h0; + _zz_161 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_181 <= 3'b000; - _zz_182 <= 1'b0; - _zz_183 <= 3'b000; - _zz_189 <= 1'b0; + _zz_186 <= 3'b000; + _zz_187 <= 1'b0; + _zz_188 <= 3'b000; + _zz_194 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -4765,7 +4755,7 @@ module VexRiscv ( if((decode_arbitration_isFiring && (! IBusCachedPlugin_decodePc_injectedDecode)))begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_decodePc_pcPlus; end - if(_zz_237)begin + if(_zz_242)begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_jump_pcLoad_payload; end if(IBusCachedPlugin_iBusRsp_flush)begin @@ -4780,7 +4770,7 @@ module VexRiscv ( if((IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid))begin IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end - if(_zz_252)begin + if(_zz_257)begin if(IBusCachedPlugin_decompressor_bufferFill)begin IBusCachedPlugin_decompressor_bufferValid <= 1'b1; end @@ -4825,7 +4815,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_253)begin + if(_zz_258)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -4835,7 +4825,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end _zz_121 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_133 <= (_zz_41 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4857,14 +4847,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_254)begin - if(_zz_255)begin + if(_zz_259)begin + if(_zz_260)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_256)begin + if(_zz_261)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_257)begin + if(_zz_262)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4889,7 +4879,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_234)begin + if(_zz_239)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4900,8 +4890,8 @@ module VexRiscv ( end endcase end - if(_zz_235)begin - case(_zz_236) + if(_zz_240)begin + case(_zz_241) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4911,7 +4901,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_148,{_zz_147,_zz_146}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_153,{_zz_152,_zz_151}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; @@ -4940,40 +4930,40 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_346[0]; - CsrPlugin_mstatus_MIE <= _zz_347[0]; + CsrPlugin_mstatus_MPIE <= _zz_351[0]; + CsrPlugin_mstatus_MIE <= _zz_352[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_349[0]; - CsrPlugin_mie_MTIE <= _zz_350[0]; - CsrPlugin_mie_MSIE <= _zz_351[0]; + CsrPlugin_mie_MEIE <= _zz_354[0]; + CsrPlugin_mie_MTIE <= _zz_355[0]; + CsrPlugin_mie_MSIE <= _zz_356[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_251)begin + if(_zz_256)begin if(iBusWishbone_ACK)begin - _zz_181 <= (_zz_181 + 3'b001); + _zz_186 <= (_zz_186 + 3'b001); end end - _zz_182 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_184 && _zz_185))begin - _zz_183 <= (_zz_183 + 3'b001); - if(_zz_187)begin - _zz_183 <= 3'b000; + _zz_187 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_189 && _zz_190))begin + _zz_188 <= (_zz_188 + 3'b001); + if(_zz_192)begin + _zz_188 <= 3'b000; end end - _zz_189 <= ((_zz_184 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_194 <= ((_zz_189 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end always @ (posedge clk) begin - if(_zz_252)begin + if(_zz_257)begin IBusCachedPlugin_decompressor_bufferData <= IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16]; end if(IBusCachedPlugin_decompressor_output_ready)begin @@ -4988,7 +4978,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(_zz_253)begin + if(_zz_258)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5006,8 +4996,8 @@ module VexRiscv ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_134 <= _zz_40[11 : 7]; + _zz_135 <= _zz_50; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5015,9 +5005,9 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_232)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_237)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_155 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_155 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -5027,21 +5017,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_254)begin - if(_zz_255)begin + if(_zz_259)begin + if(_zz_260)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_256)begin + if(_zz_261)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_257)begin + if(_zz_262)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_234)begin + if(_zz_239)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5061,20 +5051,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_227)begin - if(_zz_249)begin + if(_zz_232)begin + if(_zz_254)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_337[31:0]; + memory_DivPlugin_div_result <= _zz_342[31:0]; end end end - if(_zz_250)begin + if(_zz_255)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_154 ? (~ _zz_155) : _zz_155) + _zz_343); - memory_DivPlugin_rs2 <= ((_zz_153 ? (~ execute_RS2) : execute_RS2) + _zz_345); - memory_DivPlugin_div_needRevert <= ((_zz_154 ^ (_zz_153 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_159 ? (~ _zz_160) : _zz_160) + _zz_348); + memory_DivPlugin_rs2 <= ((_zz_158 ? (~ execute_RS2) : execute_RS2) + _zz_350); + memory_DivPlugin_div_needRevert <= ((_zz_159 ^ (_zz_158 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5340,7 +5330,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_348[0]; + CsrPlugin_mip_MSIP <= _zz_353[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5361,7 +5351,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_352[0]; + CsrPlugin_mcause_interrupt <= _zz_357[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5680,7 +5670,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_12)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -5694,7 +5684,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_12)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -5724,7 +5714,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -5751,7 +5741,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -5783,7 +5773,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -5793,7 +5783,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v index 2dc6158..9d11f1a 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -82,38 +82,38 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_194; - wire _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; wire _zz_199; wire _zz_200; wire _zz_201; - wire [31:0] _zz_202; - reg _zz_203; + wire _zz_202; + wire _zz_203; wire _zz_204; - wire [31:0] _zz_205; + wire _zz_205; wire _zz_206; wire [31:0] _zz_207; reg _zz_208; wire _zz_209; - wire _zz_210; - wire [31:0] _zz_211; - wire _zz_212; - wire _zz_213; + wire [31:0] _zz_210; + wire _zz_211; + wire [31:0] _zz_212; + reg _zz_213; wire _zz_214; wire _zz_215; - wire _zz_216; + wire [31:0] _zz_216; wire _zz_217; wire _zz_218; wire _zz_219; - wire [3:0] _zz_220; + wire _zz_220; wire _zz_221; wire _zz_222; - reg [31:0] _zz_223; - reg [31:0] _zz_224; - reg [31:0] _zz_225; + wire _zz_223; + wire _zz_224; + wire [3:0] _zz_225; + wire _zz_226; + wire _zz_227; + reg [31:0] _zz_228; + reg [31:0] _zz_229; + reg [31:0] _zz_230; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire IBusCachedPlugin_cache_io_cpu_fetch_error; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; @@ -146,11 +146,6 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_226; - wire _zz_227; - wire _zz_228; - wire _zz_229; - wire _zz_230; wire _zz_231; wire _zz_232; wire _zz_233; @@ -163,326 +158,331 @@ module VexRiscv ( wire _zz_240; wire _zz_241; wire _zz_242; - wire [1:0] _zz_243; + wire _zz_243; wire _zz_244; wire _zz_245; wire _zz_246; wire _zz_247; - wire _zz_248; + wire [1:0] _zz_248; wire _zz_249; wire _zz_250; wire _zz_251; wire _zz_252; wire _zz_253; wire _zz_254; - wire [1:0] _zz_255; + wire _zz_255; wire _zz_256; wire _zz_257; - wire [5:0] _zz_258; + wire _zz_258; wire _zz_259; - wire _zz_260; + wire [1:0] _zz_260; wire _zz_261; wire _zz_262; - wire _zz_263; + wire [5:0] _zz_263; wire _zz_264; wire _zz_265; - wire [4:0] _zz_266; - wire [1:0] _zz_267; - wire [1:0] _zz_268; - wire [1:0] _zz_269; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire _zz_269; wire _zz_270; - wire [1:0] _zz_271; - wire [51:0] _zz_272; - wire [51:0] _zz_273; - wire [51:0] _zz_274; - wire [32:0] _zz_275; - wire [51:0] _zz_276; - wire [49:0] _zz_277; + wire [4:0] _zz_271; + wire [1:0] _zz_272; + wire [1:0] _zz_273; + wire [1:0] _zz_274; + wire _zz_275; + wire [1:0] _zz_276; + wire [51:0] _zz_277; wire [51:0] _zz_278; - wire [49:0] _zz_279; - wire [51:0] _zz_280; - wire [32:0] _zz_281; - wire [31:0] _zz_282; - wire [32:0] _zz_283; - wire [0:0] _zz_284; - wire [0:0] _zz_285; - wire [0:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; + wire [51:0] _zz_279; + wire [32:0] _zz_280; + wire [51:0] _zz_281; + wire [49:0] _zz_282; + wire [51:0] _zz_283; + wire [49:0] _zz_284; + wire [51:0] _zz_285; + wire [32:0] _zz_286; + wire [31:0] _zz_287; + wire [32:0] _zz_288; wire [0:0] _zz_289; wire [0:0] _zz_290; wire [0:0] _zz_291; wire [0:0] _zz_292; wire [0:0] _zz_293; - wire [2:0] _zz_294; - wire [31:0] _zz_295; + wire [0:0] _zz_294; + wire [0:0] _zz_295; wire [0:0] _zz_296; wire [0:0] _zz_297; wire [0:0] _zz_298; - wire [0:0] _zz_299; - wire [0:0] _zz_300; + wire [2:0] _zz_299; + wire [31:0] _zz_300; wire [0:0] _zz_301; wire [0:0] _zz_302; wire [0:0] _zz_303; - wire [3:0] _zz_304; - wire [2:0] _zz_305; - wire [31:0] _zz_306; - wire [2:0] _zz_307; - wire [31:0] _zz_308; - wire [31:0] _zz_309; - wire [11:0] _zz_310; - wire [11:0] _zz_311; - wire [11:0] _zz_312; + wire [0:0] _zz_304; + wire [0:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire [3:0] _zz_309; + wire [2:0] _zz_310; + wire [31:0] _zz_311; + wire [2:0] _zz_312; wire [31:0] _zz_313; - wire [19:0] _zz_314; + wire [31:0] _zz_314; wire [11:0] _zz_315; - wire [2:0] _zz_316; - wire [2:0] _zz_317; - wire [0:0] _zz_318; - wire [2:0] _zz_319; - wire [4:0] _zz_320; - wire [11:0] _zz_321; - wire [11:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [31:0] _zz_326; - wire [31:0] _zz_327; + wire [11:0] _zz_316; + wire [11:0] _zz_317; + wire [31:0] _zz_318; + wire [19:0] _zz_319; + wire [11:0] _zz_320; + wire [2:0] _zz_321; + wire [2:0] _zz_322; + wire [0:0] _zz_323; + wire [2:0] _zz_324; + wire [4:0] _zz_325; + wire [11:0] _zz_326; + wire [11:0] _zz_327; wire [31:0] _zz_328; wire [31:0] _zz_329; - wire [11:0] _zz_330; - wire [19:0] _zz_331; - wire [11:0] _zz_332; - wire [2:0] _zz_333; - wire [1:0] _zz_334; - wire [1:0] _zz_335; - wire [65:0] _zz_336; - wire [65:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire [0:0] _zz_340; - wire [5:0] _zz_341; - wire [32:0] _zz_342; + wire [31:0] _zz_330; + wire [31:0] _zz_331; + wire [31:0] _zz_332; + wire [31:0] _zz_333; + wire [31:0] _zz_334; + wire [11:0] _zz_335; + wire [19:0] _zz_336; + wire [11:0] _zz_337; + wire [2:0] _zz_338; + wire [1:0] _zz_339; + wire [1:0] _zz_340; + wire [65:0] _zz_341; + wire [65:0] _zz_342; wire [31:0] _zz_343; wire [31:0] _zz_344; - wire [32:0] _zz_345; - wire [32:0] _zz_346; + wire [0:0] _zz_345; + wire [5:0] _zz_346; wire [32:0] _zz_347; - wire [32:0] _zz_348; - wire [0:0] _zz_349; + wire [31:0] _zz_348; + wire [31:0] _zz_349; wire [32:0] _zz_350; - wire [0:0] _zz_351; + wire [32:0] _zz_351; wire [32:0] _zz_352; - wire [0:0] _zz_353; - wire [31:0] _zz_354; - wire [0:0] _zz_355; + wire [32:0] _zz_353; + wire [0:0] _zz_354; + wire [32:0] _zz_355; wire [0:0] _zz_356; - wire [0:0] _zz_357; + wire [32:0] _zz_357; wire [0:0] _zz_358; - wire [0:0] _zz_359; + wire [31:0] _zz_359; wire [0:0] _zz_360; wire [0:0] _zz_361; - wire [26:0] _zz_362; - wire _zz_363; - wire _zz_364; - wire [1:0] _zz_365; - wire [31:0] _zz_366; - wire [31:0] _zz_367; - wire [31:0] _zz_368; + wire [0:0] _zz_362; + wire [0:0] _zz_363; + wire [0:0] _zz_364; + wire [0:0] _zz_365; + wire [0:0] _zz_366; + wire [26:0] _zz_367; + wire _zz_368; wire _zz_369; - wire [0:0] _zz_370; - wire [13:0] _zz_371; + wire [1:0] _zz_370; + wire [31:0] _zz_371; wire [31:0] _zz_372; wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire _zz_375; - wire [0:0] _zz_376; - wire [7:0] _zz_377; + wire _zz_374; + wire [0:0] _zz_375; + wire [13:0] _zz_376; + wire [31:0] _zz_377; wire [31:0] _zz_378; wire [31:0] _zz_379; - wire [31:0] _zz_380; - wire _zz_381; - wire [0:0] _zz_382; - wire [1:0] _zz_383; - wire _zz_384; - wire _zz_385; - wire [6:0] _zz_386; - wire [4:0] _zz_387; - wire _zz_388; - wire [4:0] _zz_389; - wire [0:0] _zz_390; - wire [7:0] _zz_391; - wire _zz_392; - wire [0:0] _zz_393; - wire [0:0] _zz_394; - wire [31:0] _zz_395; - wire [0:0] _zz_396; - wire [0:0] _zz_397; - wire _zz_398; + wire _zz_380; + wire [0:0] _zz_381; + wire [7:0] _zz_382; + wire [31:0] _zz_383; + wire [31:0] _zz_384; + wire [31:0] _zz_385; + wire _zz_386; + wire [0:0] _zz_387; + wire [1:0] _zz_388; + wire _zz_389; + wire _zz_390; + wire [6:0] _zz_391; + wire [4:0] _zz_392; + wire _zz_393; + wire [4:0] _zz_394; + wire [0:0] _zz_395; + wire [7:0] _zz_396; + wire _zz_397; + wire [0:0] _zz_398; wire [0:0] _zz_399; - wire [26:0] _zz_400; - wire [31:0] _zz_401; - wire _zz_402; + wire [31:0] _zz_400; + wire [0:0] _zz_401; + wire [0:0] _zz_402; wire _zz_403; - wire _zz_404; - wire [1:0] _zz_405; - wire [1:0] _zz_406; + wire [0:0] _zz_404; + wire [26:0] _zz_405; + wire [31:0] _zz_406; wire _zz_407; - wire [0:0] _zz_408; - wire [22:0] _zz_409; - wire [31:0] _zz_410; - wire [31:0] _zz_411; - wire [31:0] _zz_412; - wire [31:0] _zz_413; - wire _zz_414; - wire _zz_415; - wire [1:0] _zz_416; - wire [1:0] _zz_417; - wire _zz_418; - wire [0:0] _zz_419; - wire [19:0] _zz_420; - wire [31:0] _zz_421; - wire [31:0] _zz_422; - wire [31:0] _zz_423; - wire [31:0] _zz_424; - wire _zz_425; - wire [0:0] _zz_426; - wire [0:0] _zz_427; - wire _zz_428; - wire [0:0] _zz_429; - wire [0:0] _zz_430; - wire _zz_431; + wire _zz_408; + wire _zz_409; + wire [1:0] _zz_410; + wire [1:0] _zz_411; + wire _zz_412; + wire [0:0] _zz_413; + wire [22:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire [31:0] _zz_418; + wire _zz_419; + wire _zz_420; + wire [1:0] _zz_421; + wire [1:0] _zz_422; + wire _zz_423; + wire [0:0] _zz_424; + wire [19:0] _zz_425; + wire [31:0] _zz_426; + wire [31:0] _zz_427; + wire [31:0] _zz_428; + wire [31:0] _zz_429; + wire _zz_430; + wire [0:0] _zz_431; wire [0:0] _zz_432; - wire [16:0] _zz_433; - wire [31:0] _zz_434; - wire [31:0] _zz_435; - wire [31:0] _zz_436; - wire [31:0] _zz_437; - wire [31:0] _zz_438; - wire [0:0] _zz_439; - wire [0:0] _zz_440; - wire [0:0] _zz_441; - wire [0:0] _zz_442; - wire _zz_443; + wire _zz_433; + wire [0:0] _zz_434; + wire [0:0] _zz_435; + wire _zz_436; + wire [0:0] _zz_437; + wire [16:0] _zz_438; + wire [31:0] _zz_439; + wire [31:0] _zz_440; + wire [31:0] _zz_441; + wire [31:0] _zz_442; + wire [31:0] _zz_443; wire [0:0] _zz_444; - wire [13:0] _zz_445; - wire [31:0] _zz_446; - wire [31:0] _zz_447; - wire [31:0] _zz_448; - wire _zz_449; - wire _zz_450; - wire [0:0] _zz_451; - wire [3:0] _zz_452; - wire [0:0] _zz_453; - wire [0:0] _zz_454; + wire [0:0] _zz_445; + wire [0:0] _zz_446; + wire [0:0] _zz_447; + wire _zz_448; + wire [0:0] _zz_449; + wire [13:0] _zz_450; + wire [31:0] _zz_451; + wire [31:0] _zz_452; + wire [31:0] _zz_453; + wire _zz_454; wire _zz_455; wire [0:0] _zz_456; - wire [10:0] _zz_457; - wire [31:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire _zz_461; - wire [0:0] _zz_462; - wire [0:0] _zz_463; + wire [3:0] _zz_457; + wire [0:0] _zz_458; + wire [0:0] _zz_459; + wire _zz_460; + wire [0:0] _zz_461; + wire [10:0] _zz_462; + wire [31:0] _zz_463; wire [31:0] _zz_464; - wire _zz_465; - wire [0:0] _zz_466; - wire [2:0] _zz_467; + wire [31:0] _zz_465; + wire _zz_466; + wire [0:0] _zz_467; wire [0:0] _zz_468; - wire [3:0] _zz_469; - wire [5:0] _zz_470; - wire [5:0] _zz_471; - wire _zz_472; + wire [31:0] _zz_469; + wire _zz_470; + wire [0:0] _zz_471; + wire [2:0] _zz_472; wire [0:0] _zz_473; - wire [7:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; - wire [31:0] _zz_479; + wire [3:0] _zz_474; + wire [5:0] _zz_475; + wire [5:0] _zz_476; + wire _zz_477; + wire [0:0] _zz_478; + wire [7:0] _zz_479; wire [31:0] _zz_480; - wire _zz_481; - wire [0:0] _zz_482; - wire [0:0] _zz_483; - wire _zz_484; - wire [0:0] _zz_485; - wire [1:0] _zz_486; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire _zz_486; wire [0:0] _zz_487; - wire [3:0] _zz_488; - wire [0:0] _zz_489; + wire [0:0] _zz_488; + wire _zz_489; wire [0:0] _zz_490; wire [1:0] _zz_491; - wire [1:0] _zz_492; - wire _zz_493; + wire [0:0] _zz_492; + wire [3:0] _zz_493; wire [0:0] _zz_494; - wire [5:0] _zz_495; - wire [31:0] _zz_496; - wire [31:0] _zz_497; - wire [31:0] _zz_498; - wire [31:0] _zz_499; - wire [31:0] _zz_500; + wire [0:0] _zz_495; + wire [1:0] _zz_496; + wire [1:0] _zz_497; + wire _zz_498; + wire [0:0] _zz_499; + wire [5:0] _zz_500; wire [31:0] _zz_501; wire [31:0] _zz_502; wire [31:0] _zz_503; - wire _zz_504; - wire _zz_505; + wire [31:0] _zz_504; + wire [31:0] _zz_505; wire [31:0] _zz_506; wire [31:0] _zz_507; - wire _zz_508; - wire [0:0] _zz_509; - wire [1:0] _zz_510; + wire [31:0] _zz_508; + wire _zz_509; + wire _zz_510; wire [31:0] _zz_511; wire [31:0] _zz_512; wire _zz_513; - wire _zz_514; - wire [0:0] _zz_515; - wire [0:0] _zz_516; - wire _zz_517; - wire [0:0] _zz_518; - wire [3:0] _zz_519; - wire [31:0] _zz_520; - wire [31:0] _zz_521; - wire [31:0] _zz_522; - wire [31:0] _zz_523; - wire [31:0] _zz_524; - wire _zz_525; - wire _zz_526; + wire [0:0] _zz_514; + wire [1:0] _zz_515; + wire [31:0] _zz_516; + wire [31:0] _zz_517; + wire _zz_518; + wire _zz_519; + wire [0:0] _zz_520; + wire [0:0] _zz_521; + wire _zz_522; + wire [0:0] _zz_523; + wire [3:0] _zz_524; + wire [31:0] _zz_525; + wire [31:0] _zz_526; wire [31:0] _zz_527; wire [31:0] _zz_528; wire [31:0] _zz_529; - wire [31:0] _zz_530; - wire [0:0] _zz_531; - wire [2:0] _zz_532; - wire [0:0] _zz_533; - wire [0:0] _zz_534; - wire _zz_535; + wire _zz_530; + wire _zz_531; + wire [31:0] _zz_532; + wire [31:0] _zz_533; + wire [31:0] _zz_534; + wire [31:0] _zz_535; wire [0:0] _zz_536; - wire [1:0] _zz_537; - wire [31:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire _zz_541; - wire _zz_542; + wire [2:0] _zz_537; + wire [0:0] _zz_538; + wire [0:0] _zz_539; + wire _zz_540; + wire [0:0] _zz_541; + wire [1:0] _zz_542; wire [31:0] _zz_543; - wire _zz_544; - wire [0:0] _zz_545; - wire [0:0] _zz_546; - wire [0:0] _zz_547; - wire [0:0] _zz_548; - wire [1:0] _zz_549; - wire [1:0] _zz_550; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire _zz_546; + wire _zz_547; + wire [31:0] _zz_548; + wire _zz_549; + wire [0:0] _zz_550; wire [0:0] _zz_551; wire [0:0] _zz_552; - wire [31:0] _zz_553; - wire [31:0] _zz_554; - wire [31:0] _zz_555; - wire [31:0] _zz_556; - wire [31:0] _zz_557; + wire [0:0] _zz_553; + wire [1:0] _zz_554; + wire [1:0] _zz_555; + wire [0:0] _zz_556; + wire [0:0] _zz_557; wire [31:0] _zz_558; - wire _zz_559; - wire _zz_560; - wire _zz_561; + wire [31:0] _zz_559; + wire [31:0] _zz_560; + wire [31:0] _zz_561; wire [31:0] _zz_562; + wire [31:0] _zz_563; + wire _zz_564; + wire _zz_565; + wire _zz_566; + wire [31:0] _zz_567; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1014,35 +1014,30 @@ module VexRiscv ( reg [31:0] _zz_130; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_131; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_132; - wire _zz_133; - wire _zz_134; - wire _zz_135; - wire _zz_136; + reg _zz_132; + reg _zz_133; + reg _zz_134; + reg [4:0] _zz_135; + reg [31:0] _zz_136; wire _zz_137; + wire _zz_138; + wire _zz_139; + wire _zz_140; + wire _zz_141; + wire _zz_142; wire execute_BranchPlugin_eq; - wire [2:0] _zz_138; - reg _zz_139; - reg _zz_140; + wire [2:0] _zz_143; + reg _zz_144; + reg _zz_145; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_141; - reg [19:0] _zz_142; - wire _zz_143; - reg [10:0] _zz_144; - wire _zz_145; - reg [18:0] _zz_146; + wire _zz_146; + reg [19:0] _zz_147; + wire _zz_148; + reg [10:0] _zz_149; + wire _zz_150; + reg [18:0] _zz_151; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1064,9 +1059,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_147; - wire _zz_148; - wire _zz_149; + wire _zz_152; + wire _zz_153; + wire _zz_154; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1079,8 +1074,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_150; - wire _zz_151; + wire [1:0] _zz_155; + wire _zz_156; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1133,18 +1128,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_152; + wire [31:0] _zz_157; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_153; - wire _zz_154; - wire _zz_155; - reg [32:0] _zz_156; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_157; wire [31:0] _zz_158; + wire _zz_159; + wire _zz_160; + reg [32:0] _zz_161; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_162; + wire [31:0] _zz_163; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1154,9 +1149,9 @@ module VexRiscv ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_159; + reg _zz_164; wire DebugPlugin_allowEBreak; - reg _zz_160; + reg _zz_165; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; @@ -1222,7 +1217,7 @@ module VexRiscv ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_161; + reg [2:0] _zz_166; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; @@ -1247,11 +1242,6 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3202; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; reg [31:0] _zz_167; reg [31:0] _zz_168; reg [31:0] _zz_169; @@ -1270,16 +1260,21 @@ module VexRiscv ( reg [31:0] _zz_182; reg [31:0] _zz_183; reg [31:0] _zz_184; - reg [2:0] _zz_185; - reg _zz_186; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [2:0] _zz_190; + reg _zz_191; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_187; - wire _zz_188; - wire _zz_189; - wire _zz_190; - wire _zz_191; - wire _zz_192; - reg _zz_193; + reg [2:0] _zz_192; + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + reg _zz_198; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] _zz_1_string; @@ -1364,352 +1359,352 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_226 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_227 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_228 = 1'b1; - assign _zz_229 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_230 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_231 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_232 = ((_zz_196 && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_233 = ((_zz_196 && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_234 = ((_zz_196 && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_235 = ((_zz_196 && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_236 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_237 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_238 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_239 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_240 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_241 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_242 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_243 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_244 = (IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); - assign _zz_245 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_246 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_247 = (1'b0 || (! 1'b1)); - assign _zz_248 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_249 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_250 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_251 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_252 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_253 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_254 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_255 = execute_INSTRUCTION[13 : 12]; - assign _zz_256 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_257 = (! memory_arbitration_isStuck); - assign _zz_258 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_259 = (iBus_cmd_valid || (_zz_185 != 3'b000)); - assign _zz_260 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); - assign _zz_261 = (_zz_222 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_262 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_263 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_264 = ((_zz_148 && 1'b1) && (! 1'b0)); - assign _zz_265 = ((_zz_149 && 1'b1) && (! 1'b0)); - assign _zz_266 = {_zz_65[1 : 0],_zz_65[15 : 13]}; - assign _zz_267 = _zz_65[6 : 5]; - assign _zz_268 = _zz_65[11 : 10]; - assign _zz_269 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_270 = execute_INSTRUCTION[13]; - assign _zz_271 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_272 = ($signed(_zz_273) + $signed(_zz_278)); - assign _zz_273 = ($signed(_zz_274) + $signed(_zz_276)); - assign _zz_274 = 52'h0; - assign _zz_275 = {1'b0,memory_MUL_LL}; - assign _zz_276 = {{19{_zz_275[32]}}, _zz_275}; - assign _zz_277 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_278 = {{2{_zz_277[49]}}, _zz_277}; - assign _zz_279 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_280 = {{2{_zz_279[49]}}, _zz_279}; - assign _zz_281 = ($signed(_zz_283) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_282 = _zz_281[31 : 0]; - assign _zz_283 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_284 = _zz_110[31 : 31]; - assign _zz_285 = _zz_110[30 : 30]; - assign _zz_286 = _zz_110[29 : 29]; - assign _zz_287 = _zz_110[28 : 28]; - assign _zz_288 = _zz_110[25 : 25]; - assign _zz_289 = _zz_110[17 : 17]; - assign _zz_290 = _zz_110[16 : 16]; - assign _zz_291 = _zz_110[13 : 13]; - assign _zz_292 = _zz_110[12 : 12]; - assign _zz_293 = _zz_110[11 : 11]; - assign _zz_294 = (decode_IS_RVC ? 3'b010 : 3'b100); - assign _zz_295 = {29'd0, _zz_294}; - assign _zz_296 = _zz_110[32 : 32]; - assign _zz_297 = _zz_110[15 : 15]; - assign _zz_298 = _zz_110[5 : 5]; - assign _zz_299 = _zz_110[3 : 3]; - assign _zz_300 = _zz_110[20 : 20]; - assign _zz_301 = _zz_110[10 : 10]; - assign _zz_302 = _zz_110[4 : 4]; - assign _zz_303 = _zz_110[0 : 0]; - assign _zz_304 = (_zz_55 - 4'b0001); - assign _zz_305 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_306 = {29'd0, _zz_305}; - assign _zz_307 = (decode_IS_RVC ? 3'b010 : 3'b100); - assign _zz_308 = {29'd0, _zz_307}; - assign _zz_309 = {{_zz_75,_zz_65[6 : 2]},12'h0}; - assign _zz_310 = {{{4'b0000,_zz_65[8 : 7]},_zz_65[12 : 9]},2'b00}; - assign _zz_311 = {{{4'b0000,_zz_65[8 : 7]},_zz_65[12 : 9]},2'b00}; - assign _zz_312 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_313 = {{_zz_98,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_314 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_315 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_316 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_317 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_318 = execute_SRC_LESS; - assign _zz_319 = (execute_IS_RVC ? 3'b010 : 3'b100); - assign _zz_320 = execute_INSTRUCTION[19 : 15]; - assign _zz_321 = execute_INSTRUCTION[31 : 20]; - assign _zz_322 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_323 = ($signed(_zz_324) + $signed(_zz_327)); - assign _zz_324 = ($signed(_zz_325) + $signed(_zz_326)); - assign _zz_325 = execute_SRC1; - assign _zz_326 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_327 = (execute_SRC_USE_SUB_LESS ? _zz_328 : _zz_329); - assign _zz_328 = 32'h00000001; - assign _zz_329 = 32'h0; - assign _zz_330 = execute_INSTRUCTION[31 : 20]; - assign _zz_331 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_332 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_333 = (execute_IS_RVC ? 3'b010 : 3'b100); - assign _zz_334 = (_zz_150 & (~ _zz_335)); - assign _zz_335 = (_zz_150 - 2'b01); - assign _zz_336 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_337 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_338 = writeBack_MUL_LOW[31 : 0]; - assign _zz_339 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_340 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_341 = {5'd0, _zz_340}; - assign _zz_342 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_343 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_344 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_345 = {_zz_152,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_346 = _zz_347; - assign _zz_347 = _zz_348; - assign _zz_348 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_153) : _zz_153)} + _zz_350); - assign _zz_349 = memory_DivPlugin_div_needRevert; - assign _zz_350 = {32'd0, _zz_349}; - assign _zz_351 = _zz_155; - assign _zz_352 = {32'd0, _zz_351}; - assign _zz_353 = _zz_154; - assign _zz_354 = {31'd0, _zz_353}; - assign _zz_355 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_356 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_357 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_358 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_359 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_360 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_361 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_362 = (iBus_cmd_payload_address >>> 5); - assign _zz_363 = 1'b1; - assign _zz_364 = 1'b1; - assign _zz_365 = {_zz_59,_zz_58}; - assign _zz_366 = 32'h0000107f; - assign _zz_367 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_368 = 32'h00002073; - assign _zz_369 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_370 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_371 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_372) == 32'h00000003),{(_zz_373 == _zz_374),{_zz_375,{_zz_376,_zz_377}}}}}}; - assign _zz_372 = 32'h0000505f; - assign _zz_373 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_374 = 32'h00000063; - assign _zz_375 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_376 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_377 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_378) == 32'h00001013),{(_zz_379 == _zz_380),{_zz_381,{_zz_382,_zz_383}}}}}}; - assign _zz_378 = 32'hfc00307f; - assign _zz_379 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_380 = 32'h00005033; - assign _zz_381 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_382 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_383 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz_384 = (_zz_65[11 : 10] == 2'b01); - assign _zz_385 = ((_zz_65[11 : 10] == 2'b11) && (_zz_65[6 : 5] == 2'b00)); - assign _zz_386 = 7'h0; - assign _zz_387 = _zz_65[6 : 2]; - assign _zz_388 = _zz_65[12]; - assign _zz_389 = _zz_65[11 : 7]; - assign _zz_390 = decode_INSTRUCTION[31]; - assign _zz_391 = decode_INSTRUCTION[19 : 12]; - assign _zz_392 = decode_INSTRUCTION[20]; - assign _zz_393 = decode_INSTRUCTION[31]; - assign _zz_394 = decode_INSTRUCTION[7]; - assign _zz_395 = 32'h10103050; - assign _zz_396 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_397 = 1'b0; - assign _zz_398 = (((decode_INSTRUCTION & _zz_401) == 32'h02000030) != 1'b0); - assign _zz_399 = ({_zz_402,_zz_403} != 2'b00); - assign _zz_400 = {(_zz_404 != 1'b0),{(_zz_405 != _zz_406),{_zz_407,{_zz_408,_zz_409}}}}; - assign _zz_401 = 32'h02004074; - assign _zz_402 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); - assign _zz_403 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); - assign _zz_404 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); - assign _zz_405 = {(_zz_410 == _zz_411),(_zz_412 == _zz_413)}; - assign _zz_406 = 2'b00; - assign _zz_407 = ({_zz_113,_zz_414} != 2'b00); - assign _zz_408 = (_zz_415 != 1'b0); - assign _zz_409 = {(_zz_416 != _zz_417),{_zz_418,{_zz_419,_zz_420}}}; - assign _zz_410 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_411 = 32'h00001050; - assign _zz_412 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_413 = 32'h00002050; - assign _zz_414 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_415 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_416 = {(_zz_421 == _zz_422),(_zz_423 == _zz_424)}; - assign _zz_417 = 2'b00; - assign _zz_418 = ({_zz_425,{_zz_426,_zz_427}} != 3'b000); - assign _zz_419 = (_zz_428 != 1'b0); - assign _zz_420 = {(_zz_429 != _zz_430),{_zz_431,{_zz_432,_zz_433}}}; - assign _zz_421 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_422 = 32'h00005010; - assign _zz_423 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_424 = 32'h00005020; - assign _zz_425 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_426 = ((decode_INSTRUCTION & _zz_434) == 32'h00001010); - assign _zz_427 = ((decode_INSTRUCTION & _zz_435) == 32'h00001010); - assign _zz_428 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_429 = ((decode_INSTRUCTION & _zz_436) == 32'h00001000); - assign _zz_430 = 1'b0; - assign _zz_431 = ((_zz_437 == _zz_438) != 1'b0); - assign _zz_432 = ({_zz_439,_zz_440} != 2'b00); - assign _zz_433 = {(_zz_441 != _zz_442),{_zz_443,{_zz_444,_zz_445}}}; - assign _zz_434 = 32'h00007034; - assign _zz_435 = 32'h02007054; - assign _zz_436 = 32'h00001000; - assign _zz_437 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_438 = 32'h00002000; - assign _zz_439 = ((decode_INSTRUCTION & _zz_446) == 32'h00002000); - assign _zz_440 = ((decode_INSTRUCTION & _zz_447) == 32'h00001000); - assign _zz_441 = ((decode_INSTRUCTION & _zz_448) == 32'h00004008); - assign _zz_442 = 1'b0; - assign _zz_443 = ({_zz_449,_zz_450} != 2'b00); - assign _zz_444 = ({_zz_451,_zz_452} != 5'h0); - assign _zz_445 = {(_zz_453 != _zz_454),{_zz_455,{_zz_456,_zz_457}}}; - assign _zz_446 = 32'h00002010; - assign _zz_447 = 32'h00005000; - assign _zz_448 = 32'h00004048; - assign _zz_449 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); - assign _zz_450 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_451 = ((decode_INSTRUCTION & _zz_458) == 32'h00002040); - assign _zz_452 = {(_zz_459 == _zz_460),{_zz_461,{_zz_462,_zz_463}}}; - assign _zz_453 = ((decode_INSTRUCTION & _zz_464) == 32'h00000020); - assign _zz_454 = 1'b0; - assign _zz_455 = ({_zz_465,{_zz_466,_zz_467}} != 5'h0); - assign _zz_456 = ({_zz_468,_zz_469} != 5'h0); - assign _zz_457 = {(_zz_470 != _zz_471),{_zz_472,{_zz_473,_zz_474}}}; - assign _zz_458 = 32'h00002040; - assign _zz_459 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_460 = 32'h00001040; - assign _zz_461 = ((decode_INSTRUCTION & _zz_475) == 32'h00000040); - assign _zz_462 = (_zz_476 == _zz_477); - assign _zz_463 = (_zz_478 == _zz_479); - assign _zz_464 = 32'h00000020; - assign _zz_465 = ((decode_INSTRUCTION & _zz_480) == 32'h00000040); - assign _zz_466 = _zz_112; - assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; - assign _zz_468 = _zz_112; - assign _zz_469 = {_zz_484,{_zz_485,_zz_486}}; - assign _zz_470 = {_zz_113,{_zz_487,_zz_488}}; - assign _zz_471 = 6'h0; - assign _zz_472 = ({_zz_489,_zz_490} != 2'b00); - assign _zz_473 = (_zz_491 != _zz_492); - assign _zz_474 = {_zz_493,{_zz_494,_zz_495}}; - assign _zz_475 = 32'h00100040; - assign _zz_476 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_477 = 32'h00000040; - assign _zz_478 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_479 = 32'h0; - assign _zz_480 = 32'h00000040; - assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00004020); - assign _zz_482 = (_zz_497 == _zz_498); - assign _zz_483 = (_zz_499 == _zz_500); - assign _zz_484 = ((decode_INSTRUCTION & _zz_501) == 32'h00002010); - assign _zz_485 = (_zz_502 == _zz_503); - assign _zz_486 = {_zz_504,_zz_505}; - assign _zz_487 = (_zz_506 == _zz_507); - assign _zz_488 = {_zz_508,{_zz_509,_zz_510}}; - assign _zz_489 = _zz_112; - assign _zz_490 = (_zz_511 == _zz_512); - assign _zz_491 = {_zz_112,_zz_513}; - assign _zz_492 = 2'b00; - assign _zz_493 = (_zz_514 != 1'b0); - assign _zz_494 = (_zz_515 != _zz_516); - assign _zz_495 = {_zz_517,{_zz_518,_zz_519}}; - assign _zz_496 = 32'h00004020; - assign _zz_497 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_498 = 32'h00000010; - assign _zz_499 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_500 = 32'h00000020; - assign _zz_501 = 32'h00002030; - assign _zz_502 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_231 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_232 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_233 = 1'b1; + assign _zz_234 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_235 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_236 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_237 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_238 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_239 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_240 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_241 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_242 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_243 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_244 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_245 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_246 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_247 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_248 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_249 = (IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); + assign _zz_250 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_251 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_252 = (1'b0 || (! 1'b1)); + assign _zz_253 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_254 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_256 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_257 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_258 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_260 = execute_INSTRUCTION[13 : 12]; + assign _zz_261 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_262 = (! memory_arbitration_isStuck); + assign _zz_263 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_264 = (iBus_cmd_valid || (_zz_190 != 3'b000)); + assign _zz_265 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); + assign _zz_266 = (_zz_227 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_267 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_268 = ((_zz_152 && 1'b1) && (! 1'b0)); + assign _zz_269 = ((_zz_153 && 1'b1) && (! 1'b0)); + assign _zz_270 = ((_zz_154 && 1'b1) && (! 1'b0)); + assign _zz_271 = {_zz_65[1 : 0],_zz_65[15 : 13]}; + assign _zz_272 = _zz_65[6 : 5]; + assign _zz_273 = _zz_65[11 : 10]; + assign _zz_274 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_275 = execute_INSTRUCTION[13]; + assign _zz_276 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_277 = ($signed(_zz_278) + $signed(_zz_283)); + assign _zz_278 = ($signed(_zz_279) + $signed(_zz_281)); + assign _zz_279 = 52'h0; + assign _zz_280 = {1'b0,memory_MUL_LL}; + assign _zz_281 = {{19{_zz_280[32]}}, _zz_280}; + assign _zz_282 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_283 = {{2{_zz_282[49]}}, _zz_282}; + assign _zz_284 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_285 = {{2{_zz_284[49]}}, _zz_284}; + assign _zz_286 = ($signed(_zz_288) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_287 = _zz_286[31 : 0]; + assign _zz_288 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_289 = _zz_110[31 : 31]; + assign _zz_290 = _zz_110[30 : 30]; + assign _zz_291 = _zz_110[29 : 29]; + assign _zz_292 = _zz_110[28 : 28]; + assign _zz_293 = _zz_110[25 : 25]; + assign _zz_294 = _zz_110[17 : 17]; + assign _zz_295 = _zz_110[16 : 16]; + assign _zz_296 = _zz_110[13 : 13]; + assign _zz_297 = _zz_110[12 : 12]; + assign _zz_298 = _zz_110[11 : 11]; + assign _zz_299 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_300 = {29'd0, _zz_299}; + assign _zz_301 = _zz_110[32 : 32]; + assign _zz_302 = _zz_110[15 : 15]; + assign _zz_303 = _zz_110[5 : 5]; + assign _zz_304 = _zz_110[3 : 3]; + assign _zz_305 = _zz_110[20 : 20]; + assign _zz_306 = _zz_110[10 : 10]; + assign _zz_307 = _zz_110[4 : 4]; + assign _zz_308 = _zz_110[0 : 0]; + assign _zz_309 = (_zz_55 - 4'b0001); + assign _zz_310 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_311 = {29'd0, _zz_310}; + assign _zz_312 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_313 = {29'd0, _zz_312}; + assign _zz_314 = {{_zz_75,_zz_65[6 : 2]},12'h0}; + assign _zz_315 = {{{4'b0000,_zz_65[8 : 7]},_zz_65[12 : 9]},2'b00}; + assign _zz_316 = {{{4'b0000,_zz_65[8 : 7]},_zz_65[12 : 9]},2'b00}; + assign _zz_317 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_318 = {{_zz_98,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_319 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_321 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_322 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_323 = execute_SRC_LESS; + assign _zz_324 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz_325 = execute_INSTRUCTION[19 : 15]; + assign _zz_326 = execute_INSTRUCTION[31 : 20]; + assign _zz_327 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_328 = ($signed(_zz_329) + $signed(_zz_332)); + assign _zz_329 = ($signed(_zz_330) + $signed(_zz_331)); + assign _zz_330 = execute_SRC1; + assign _zz_331 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_332 = (execute_SRC_USE_SUB_LESS ? _zz_333 : _zz_334); + assign _zz_333 = 32'h00000001; + assign _zz_334 = 32'h0; + assign _zz_335 = execute_INSTRUCTION[31 : 20]; + assign _zz_336 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_337 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_338 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz_339 = (_zz_155 & (~ _zz_340)); + assign _zz_340 = (_zz_155 - 2'b01); + assign _zz_341 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_342 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_343 = writeBack_MUL_LOW[31 : 0]; + assign _zz_344 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_345 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_346 = {5'd0, _zz_345}; + assign _zz_347 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_348 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_349 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_350 = {_zz_157,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_351 = _zz_352; + assign _zz_352 = _zz_353; + assign _zz_353 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_158) : _zz_158)} + _zz_355); + assign _zz_354 = memory_DivPlugin_div_needRevert; + assign _zz_355 = {32'd0, _zz_354}; + assign _zz_356 = _zz_160; + assign _zz_357 = {32'd0, _zz_356}; + assign _zz_358 = _zz_159; + assign _zz_359 = {31'd0, _zz_358}; + assign _zz_360 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_361 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_362 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_363 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_364 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_365 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_366 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_367 = (iBus_cmd_payload_address >>> 5); + assign _zz_368 = 1'b1; + assign _zz_369 = 1'b1; + assign _zz_370 = {_zz_59,_zz_58}; + assign _zz_371 = 32'h0000107f; + assign _zz_372 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_373 = 32'h00002073; + assign _zz_374 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_375 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_376 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_377) == 32'h00000003),{(_zz_378 == _zz_379),{_zz_380,{_zz_381,_zz_382}}}}}}; + assign _zz_377 = 32'h0000505f; + assign _zz_378 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_379 = 32'h00000063; + assign _zz_380 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_381 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_382 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_383) == 32'h00001013),{(_zz_384 == _zz_385),{_zz_386,{_zz_387,_zz_388}}}}}}; + assign _zz_383 = 32'hfc00307f; + assign _zz_384 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_385 = 32'h00005033; + assign _zz_386 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_387 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_388 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz_389 = (_zz_65[11 : 10] == 2'b01); + assign _zz_390 = ((_zz_65[11 : 10] == 2'b11) && (_zz_65[6 : 5] == 2'b00)); + assign _zz_391 = 7'h0; + assign _zz_392 = _zz_65[6 : 2]; + assign _zz_393 = _zz_65[12]; + assign _zz_394 = _zz_65[11 : 7]; + assign _zz_395 = decode_INSTRUCTION[31]; + assign _zz_396 = decode_INSTRUCTION[19 : 12]; + assign _zz_397 = decode_INSTRUCTION[20]; + assign _zz_398 = decode_INSTRUCTION[31]; + assign _zz_399 = decode_INSTRUCTION[7]; + assign _zz_400 = 32'h10103050; + assign _zz_401 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_402 = 1'b0; + assign _zz_403 = (((decode_INSTRUCTION & _zz_406) == 32'h02000030) != 1'b0); + assign _zz_404 = ({_zz_407,_zz_408} != 2'b00); + assign _zz_405 = {(_zz_409 != 1'b0),{(_zz_410 != _zz_411),{_zz_412,{_zz_413,_zz_414}}}}; + assign _zz_406 = 32'h02004074; + assign _zz_407 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); + assign _zz_408 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz_409 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz_410 = {(_zz_415 == _zz_416),(_zz_417 == _zz_418)}; + assign _zz_411 = 2'b00; + assign _zz_412 = ({_zz_113,_zz_419} != 2'b00); + assign _zz_413 = (_zz_420 != 1'b0); + assign _zz_414 = {(_zz_421 != _zz_422),{_zz_423,{_zz_424,_zz_425}}}; + assign _zz_415 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_416 = 32'h00001050; + assign _zz_417 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_418 = 32'h00002050; + assign _zz_419 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_420 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_421 = {(_zz_426 == _zz_427),(_zz_428 == _zz_429)}; + assign _zz_422 = 2'b00; + assign _zz_423 = ({_zz_430,{_zz_431,_zz_432}} != 3'b000); + assign _zz_424 = (_zz_433 != 1'b0); + assign _zz_425 = {(_zz_434 != _zz_435),{_zz_436,{_zz_437,_zz_438}}}; + assign _zz_426 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_427 = 32'h00005010; + assign _zz_428 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_429 = 32'h00005020; + assign _zz_430 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_431 = ((decode_INSTRUCTION & _zz_439) == 32'h00001010); + assign _zz_432 = ((decode_INSTRUCTION & _zz_440) == 32'h00001010); + assign _zz_433 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_434 = ((decode_INSTRUCTION & _zz_441) == 32'h00001000); + assign _zz_435 = 1'b0; + assign _zz_436 = ((_zz_442 == _zz_443) != 1'b0); + assign _zz_437 = ({_zz_444,_zz_445} != 2'b00); + assign _zz_438 = {(_zz_446 != _zz_447),{_zz_448,{_zz_449,_zz_450}}}; + assign _zz_439 = 32'h00007034; + assign _zz_440 = 32'h02007054; + assign _zz_441 = 32'h00001000; + assign _zz_442 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_443 = 32'h00002000; + assign _zz_444 = ((decode_INSTRUCTION & _zz_451) == 32'h00002000); + assign _zz_445 = ((decode_INSTRUCTION & _zz_452) == 32'h00001000); + assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h00004008); + assign _zz_447 = 1'b0; + assign _zz_448 = ({_zz_454,_zz_455} != 2'b00); + assign _zz_449 = ({_zz_456,_zz_457} != 5'h0); + assign _zz_450 = {(_zz_458 != _zz_459),{_zz_460,{_zz_461,_zz_462}}}; + assign _zz_451 = 32'h00002010; + assign _zz_452 = 32'h00005000; + assign _zz_453 = 32'h00004048; + assign _zz_454 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_455 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_456 = ((decode_INSTRUCTION & _zz_463) == 32'h00002040); + assign _zz_457 = {(_zz_464 == _zz_465),{_zz_466,{_zz_467,_zz_468}}}; + assign _zz_458 = ((decode_INSTRUCTION & _zz_469) == 32'h00000020); + assign _zz_459 = 1'b0; + assign _zz_460 = ({_zz_470,{_zz_471,_zz_472}} != 5'h0); + assign _zz_461 = ({_zz_473,_zz_474} != 5'h0); + assign _zz_462 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; + assign _zz_463 = 32'h00002040; + assign _zz_464 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_465 = 32'h00001040; + assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000040); + assign _zz_467 = (_zz_481 == _zz_482); + assign _zz_468 = (_zz_483 == _zz_484); + assign _zz_469 = 32'h00000020; + assign _zz_470 = ((decode_INSTRUCTION & _zz_485) == 32'h00000040); + assign _zz_471 = _zz_112; + assign _zz_472 = {_zz_486,{_zz_487,_zz_488}}; + assign _zz_473 = _zz_112; + assign _zz_474 = {_zz_489,{_zz_490,_zz_491}}; + assign _zz_475 = {_zz_113,{_zz_492,_zz_493}}; + assign _zz_476 = 6'h0; + assign _zz_477 = ({_zz_494,_zz_495} != 2'b00); + assign _zz_478 = (_zz_496 != _zz_497); + assign _zz_479 = {_zz_498,{_zz_499,_zz_500}}; + assign _zz_480 = 32'h00100040; + assign _zz_481 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_482 = 32'h00000040; + assign _zz_483 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_484 = 32'h0; + assign _zz_485 = 32'h00000040; + assign _zz_486 = ((decode_INSTRUCTION & _zz_501) == 32'h00004020); + assign _zz_487 = (_zz_502 == _zz_503); + assign _zz_488 = (_zz_504 == _zz_505); + assign _zz_489 = ((decode_INSTRUCTION & _zz_506) == 32'h00002010); + assign _zz_490 = (_zz_507 == _zz_508); + assign _zz_491 = {_zz_509,_zz_510}; + assign _zz_492 = (_zz_511 == _zz_512); + assign _zz_493 = {_zz_513,{_zz_514,_zz_515}}; + assign _zz_494 = _zz_112; + assign _zz_495 = (_zz_516 == _zz_517); + assign _zz_496 = {_zz_112,_zz_518}; + assign _zz_497 = 2'b00; + assign _zz_498 = (_zz_519 != 1'b0); + assign _zz_499 = (_zz_520 != _zz_521); + assign _zz_500 = {_zz_522,{_zz_523,_zz_524}}; + assign _zz_501 = 32'h00004020; + assign _zz_502 = (decode_INSTRUCTION & 32'h00000030); assign _zz_503 = 32'h00000010; - assign _zz_504 = ((decode_INSTRUCTION & _zz_520) == 32'h00002020); - assign _zz_505 = ((decode_INSTRUCTION & _zz_521) == 32'h00000020); - assign _zz_506 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_507 = 32'h00001010; - assign _zz_508 = ((decode_INSTRUCTION & _zz_522) == 32'h00002010); - assign _zz_509 = (_zz_523 == _zz_524); - assign _zz_510 = {_zz_525,_zz_526}; - assign _zz_511 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_512 = 32'h00000020; - assign _zz_513 = ((decode_INSTRUCTION & _zz_527) == 32'h0); - assign _zz_514 = ((decode_INSTRUCTION & _zz_528) == 32'h00004010); - assign _zz_515 = (_zz_529 == _zz_530); - assign _zz_516 = 1'b0; - assign _zz_517 = ({_zz_531,_zz_532} != 4'b0000); - assign _zz_518 = (_zz_533 != _zz_534); - assign _zz_519 = {_zz_535,{_zz_536,_zz_537}}; - assign _zz_520 = 32'h02002060; - assign _zz_521 = 32'h02003020; - assign _zz_522 = 32'h00002010; - assign _zz_523 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_524 = 32'h00000010; - assign _zz_525 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_526 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); - assign _zz_527 = 32'h00000020; - assign _zz_528 = 32'h00004014; - assign _zz_529 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_530 = 32'h00002010; - assign _zz_531 = ((decode_INSTRUCTION & _zz_538) == 32'h0); - assign _zz_532 = {(_zz_539 == _zz_540),{_zz_541,_zz_542}}; - assign _zz_533 = ((decode_INSTRUCTION & _zz_543) == 32'h0); - assign _zz_534 = 1'b0; - assign _zz_535 = ({_zz_544,{_zz_545,_zz_546}} != 3'b000); - assign _zz_536 = ({_zz_547,_zz_548} != 2'b00); - assign _zz_537 = {(_zz_549 != _zz_550),(_zz_551 != _zz_552)}; - assign _zz_538 = 32'h00000044; - assign _zz_539 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_540 = 32'h0; - assign _zz_541 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_542 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_543 = 32'h00000058; - assign _zz_544 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_545 = ((decode_INSTRUCTION & _zz_553) == 32'h00002010); - assign _zz_546 = ((decode_INSTRUCTION & _zz_554) == 32'h40000030); - assign _zz_547 = ((decode_INSTRUCTION & _zz_555) == 32'h00000004); - assign _zz_548 = _zz_111; - assign _zz_549 = {(_zz_556 == _zz_557),_zz_111}; - assign _zz_550 = 2'b00; - assign _zz_551 = ((decode_INSTRUCTION & _zz_558) == 32'h00001008); - assign _zz_552 = 1'b0; - assign _zz_553 = 32'h00002014; - assign _zz_554 = 32'h40000034; - assign _zz_555 = 32'h00000014; - assign _zz_556 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_557 = 32'h00000004; - assign _zz_558 = 32'h00005048; - assign _zz_559 = execute_INSTRUCTION[31]; - assign _zz_560 = execute_INSTRUCTION[31]; - assign _zz_561 = execute_INSTRUCTION[7]; - assign _zz_562 = 32'h0; + assign _zz_504 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_505 = 32'h00000020; + assign _zz_506 = 32'h00002030; + assign _zz_507 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_508 = 32'h00000010; + assign _zz_509 = ((decode_INSTRUCTION & _zz_525) == 32'h00002020); + assign _zz_510 = ((decode_INSTRUCTION & _zz_526) == 32'h00000020); + assign _zz_511 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_512 = 32'h00001010; + assign _zz_513 = ((decode_INSTRUCTION & _zz_527) == 32'h00002010); + assign _zz_514 = (_zz_528 == _zz_529); + assign _zz_515 = {_zz_530,_zz_531}; + assign _zz_516 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_517 = 32'h00000020; + assign _zz_518 = ((decode_INSTRUCTION & _zz_532) == 32'h0); + assign _zz_519 = ((decode_INSTRUCTION & _zz_533) == 32'h00004010); + assign _zz_520 = (_zz_534 == _zz_535); + assign _zz_521 = 1'b0; + assign _zz_522 = ({_zz_536,_zz_537} != 4'b0000); + assign _zz_523 = (_zz_538 != _zz_539); + assign _zz_524 = {_zz_540,{_zz_541,_zz_542}}; + assign _zz_525 = 32'h02002060; + assign _zz_526 = 32'h02003020; + assign _zz_527 = 32'h00002010; + assign _zz_528 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_529 = 32'h00000010; + assign _zz_530 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_531 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_532 = 32'h00000020; + assign _zz_533 = 32'h00004014; + assign _zz_534 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_535 = 32'h00002010; + assign _zz_536 = ((decode_INSTRUCTION & _zz_543) == 32'h0); + assign _zz_537 = {(_zz_544 == _zz_545),{_zz_546,_zz_547}}; + assign _zz_538 = ((decode_INSTRUCTION & _zz_548) == 32'h0); + assign _zz_539 = 1'b0; + assign _zz_540 = ({_zz_549,{_zz_550,_zz_551}} != 3'b000); + assign _zz_541 = ({_zz_552,_zz_553} != 2'b00); + assign _zz_542 = {(_zz_554 != _zz_555),(_zz_556 != _zz_557)}; + assign _zz_543 = 32'h00000044; + assign _zz_544 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_545 = 32'h0; + assign _zz_546 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_547 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_548 = 32'h00000058; + assign _zz_549 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_550 = ((decode_INSTRUCTION & _zz_558) == 32'h00002010); + assign _zz_551 = ((decode_INSTRUCTION & _zz_559) == 32'h40000030); + assign _zz_552 = ((decode_INSTRUCTION & _zz_560) == 32'h00000004); + assign _zz_553 = _zz_111; + assign _zz_554 = {(_zz_561 == _zz_562),_zz_111}; + assign _zz_555 = 2'b00; + assign _zz_556 = ((decode_INSTRUCTION & _zz_563) == 32'h00001008); + assign _zz_557 = 1'b0; + assign _zz_558 = 32'h00002014; + assign _zz_559 = 32'h40000034; + assign _zz_560 = 32'h00000014; + assign _zz_561 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_562 = 32'h00000004; + assign _zz_563 = 32'h00005048; + assign _zz_564 = execute_INSTRUCTION[31]; + assign _zz_565 = execute_INSTRUCTION[31]; + assign _zz_566 = execute_INSTRUCTION[7]; + assign _zz_567 = 32'h0; always @ (posedge clk) begin - if(_zz_363) begin - _zz_223 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_368) begin + _zz_228 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_364) begin - _zz_224 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_369) begin + _zz_229 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1720,13 +1715,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_194 ), //i - .io_cpu_prefetch_isValid (_zz_195 ), //i + .io_flush (_zz_199 ), //i + .io_cpu_prefetch_isValid (_zz_200 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_196 ), //i - .io_cpu_fetch_isStuck (_zz_197 ), //i - .io_cpu_fetch_isRemoved (_zz_198 ), //i + .io_cpu_fetch_isValid (_zz_201 ), //i + .io_cpu_fetch_isStuck (_zz_202 ), //i + .io_cpu_fetch_isRemoved (_zz_203 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1743,13 +1738,13 @@ module VexRiscv ( .io_cpu_fetch_error (IBusCachedPlugin_cache_io_cpu_fetch_error ), //o .io_cpu_fetch_mmuRefilling (IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling ), //o .io_cpu_fetch_mmuException (IBusCachedPlugin_cache_io_cpu_fetch_mmuException ), //o - .io_cpu_fetch_isUser (_zz_199 ), //i - .io_cpu_decode_isValid (_zz_200 ), //i - .io_cpu_decode_isStuck (_zz_201 ), //i - .io_cpu_decode_pc (_zz_202[31:0] ), //i + .io_cpu_fetch_isUser (_zz_204 ), //i + .io_cpu_decode_isValid (_zz_205 ), //i + .io_cpu_decode_isStuck (_zz_206 ), //i + .io_cpu_decode_pc (_zz_207[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_fill_valid (_zz_203 ), //i + .io_cpu_fill_valid (_zz_208 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1762,20 +1757,20 @@ module VexRiscv ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_204 ), //i - .io_cpu_execute_address (_zz_205[31:0] ), //i + .io_cpu_execute_isValid (_zz_209 ), //i + .io_cpu_execute_address (_zz_210[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_105[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_206 ), //i + .io_cpu_memory_isValid (_zz_211 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_207[31:0] ), //i + .io_cpu_memory_address (_zz_212[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_208 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_213 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1783,31 +1778,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_209 ), //i + .io_cpu_writeBack_isValid (_zz_214 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_210 ), //i + .io_cpu_writeBack_isUser (_zz_215 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_211[31:0] ), //i + .io_cpu_writeBack_address (_zz_216[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_212 ), //i - .io_cpu_writeBack_fence_SR (_zz_213 ), //i - .io_cpu_writeBack_fence_SO (_zz_214 ), //i - .io_cpu_writeBack_fence_SI (_zz_215 ), //i - .io_cpu_writeBack_fence_PW (_zz_216 ), //i - .io_cpu_writeBack_fence_PR (_zz_217 ), //i - .io_cpu_writeBack_fence_PO (_zz_218 ), //i - .io_cpu_writeBack_fence_PI (_zz_219 ), //i - .io_cpu_writeBack_fence_FM (_zz_220[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_217 ), //i + .io_cpu_writeBack_fence_SR (_zz_218 ), //i + .io_cpu_writeBack_fence_SO (_zz_219 ), //i + .io_cpu_writeBack_fence_SI (_zz_220 ), //i + .io_cpu_writeBack_fence_PW (_zz_221 ), //i + .io_cpu_writeBack_fence_PR (_zz_222 ), //i + .io_cpu_writeBack_fence_PO (_zz_223 ), //i + .io_cpu_writeBack_fence_PI (_zz_224 ), //i + .io_cpu_writeBack_fence_FM (_zz_225[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_221 ), //i + .io_cpu_flush_valid (_zz_226 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_222 ), //i + .io_mem_cmd_ready (_zz_227 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1823,18 +1818,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_365) + case(_zz_370) 2'b00 : begin - _zz_225 = DBusCachedPlugin_redoBranch_payload; + _zz_230 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_225 = CsrPlugin_jumpInterface_payload; + _zz_230 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_225 = BranchPlugin_jumpInterface_payload; + _zz_230 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_225 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_230 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2526,7 +2521,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_272) + $signed(_zz_280)); + assign memory_MUL_LOW = ($signed(_zz_277) + $signed(_zz_285)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2534,39 +2529,39 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_282; + assign execute_SHIFT_RIGHT = _zz_287; assign execute_REGFILE_WRITE_DATA = _zz_123; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_205[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_210[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_284[0]; - assign decode_IS_RS1_SIGNED = _zz_285[0]; - assign decode_IS_DIV = _zz_286[0]; + assign decode_IS_RS2_SIGNED = _zz_289[0]; + assign decode_IS_RS1_SIGNED = _zz_290[0]; + assign decode_IS_DIV = _zz_291[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_287[0]; + assign decode_IS_MUL = _zz_292[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_288[0]; + assign decode_IS_CSR = _zz_293[0]; assign _zz_8 = _zz_9; assign _zz_10 = _zz_11; assign decode_SHIFT_CTRL = _zz_12; assign _zz_13 = _zz_14; assign decode_ALU_BITWISE_CTRL = _zz_15; assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_289[0]; - assign decode_MEMORY_MANAGMENT = _zz_290[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_294[0]; + assign decode_MEMORY_MANAGMENT = _zz_295[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_291[0]; + assign decode_MEMORY_WR = _zz_296[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_292[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_293[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_297[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_298[0]; assign decode_SRC2_CTRL = _zz_18; assign _zz_19 = _zz_20; assign decode_ALU_CTRL = _zz_21; @@ -2577,10 +2572,10 @@ module VexRiscv ( assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_295); + assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_300); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_296[0]; + assign decode_IS_EBREAK = _zz_301[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2601,14 +2596,14 @@ module VexRiscv ( assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_140; + assign execute_BRANCH_COND_RESULT = _zz_145; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_297[0]; - assign decode_RS1_USE = _zz_298[0]; + assign decode_RS2_USE = _zz_302[0]; + assign decode_RS1_USE = _zz_303[0]; always @ (*) begin _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_226)begin + if(_zz_231)begin _zz_31 = execute_CsrPlugin_readData; end end @@ -2621,28 +2616,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_134)begin + if((_zz_135 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_136; end end - if(_zz_227)begin - if(_zz_228)begin - if(_zz_133)begin + if(_zz_232)begin + if(_zz_233)begin + if(_zz_138)begin decode_RS2 = _zz_50; end end end - if(_zz_229)begin + if(_zz_234)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_135)begin + if(_zz_140)begin decode_RS2 = _zz_32; end end end - if(_zz_230)begin + if(_zz_235)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_137)begin + if(_zz_142)begin decode_RS2 = _zz_31; end end @@ -2651,28 +2646,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_134)begin + if((_zz_135 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_136; end end - if(_zz_227)begin - if(_zz_228)begin - if(_zz_132)begin + if(_zz_232)begin + if(_zz_233)begin + if(_zz_137)begin decode_RS1 = _zz_50; end end end - if(_zz_229)begin + if(_zz_234)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_134)begin + if(_zz_139)begin decode_RS1 = _zz_32; end end end - if(_zz_230)begin + if(_zz_235)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_136)begin + if(_zz_141)begin decode_RS1 = _zz_31; end end @@ -2694,7 +2689,7 @@ module VexRiscv ( end endcase end - if(_zz_231)begin + if(_zz_236)begin _zz_32 = memory_DivPlugin_div_result; end end @@ -2708,8 +2703,8 @@ module VexRiscv ( assign execute_SRC2_CTRL = _zz_36; assign execute_IS_RVC = decode_to_execute_IS_RVC; assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_299[0]; - assign decode_SRC_ADD_ZERO = _zz_300[0]; + assign decode_SRC_USE_SUB_LESS = _zz_304[0]; + assign decode_SRC_ADD_ZERO = _zz_305[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_38; @@ -2727,25 +2722,25 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_decompressor_output_payload_rsp_inst); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_301[0]; + decode_REGFILE_WRITE_VALID = _zz_306[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_366) == 32'h00001073),{(_zz_367 == _zz_368),{_zz_369,{_zz_370,_zz_371}}}}}}} != 21'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_371) == 32'h00001073),{(_zz_372 == _zz_373),{_zz_374,{_zz_375,_zz_376}}}}}}} != 21'h0); always @ (*) begin _zz_50 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_271) + case(_zz_276) 2'b00 : begin - _zz_50 = _zz_338; + _zz_50 = _zz_343; end default : begin - _zz_50 = _zz_339; + _zz_50 = _zz_344; end endcase end @@ -2764,32 +2759,32 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_302[0]; - assign decode_FLUSH_ALL = _zz_303[0]; + assign decode_MEMORY_ENABLE = _zz_307[0]; + assign decode_FLUSH_ALL = _zz_308[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_232)begin + if(_zz_237)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_233)begin + if(_zz_238)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_234)begin + if(_zz_239)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_235)begin + if(_zz_240)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2819,7 +2814,7 @@ module VexRiscv ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_161) + case(_zz_166) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2830,7 +2825,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_132 || _zz_133)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2843,7 +2838,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_236)begin + if(_zz_241)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2857,22 +2852,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_236)begin + if(_zz_241)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_221 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_226 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_237)begin + if(_zz_242)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_226)begin + if(_zz_231)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2884,7 +2879,7 @@ module VexRiscv ( if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_238)begin + if(_zz_243)begin execute_arbitration_haltByOther = 1'b1; end end @@ -2901,8 +2896,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_238)begin - if(_zz_239)begin + if(_zz_243)begin + if(_zz_244)begin execute_arbitration_flushIt = 1'b1; end end @@ -2913,19 +2908,19 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_238)begin - if(_zz_239)begin + if(_zz_243)begin + if(_zz_244)begin execute_arbitration_flushNext = 1'b1; end end - if(_zz_160)begin + if(_zz_165)begin execute_arbitration_flushNext = 1'b1; end end always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_231)begin + if(_zz_236)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2981,10 +2976,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_240)begin + if(_zz_245)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_241)begin + if(_zz_246)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2998,21 +2993,21 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_240)begin + if(_zz_245)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_241)begin + if(_zz_246)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_238)begin - if(_zz_239)begin + if(_zz_243)begin + if(_zz_244)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_242)begin + if(_zz_247)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3036,7 +3031,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_237)begin + if(_zz_242)begin CsrPlugin_inWfi = 1'b1; end end @@ -3050,21 +3045,21 @@ module VexRiscv ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_240)begin + if(_zz_245)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_241)begin + if(_zz_246)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_240)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_245)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_241)begin - case(_zz_243) + if(_zz_246)begin + case(_zz_248) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3098,11 +3093,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_55 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_56 = (_zz_55 & (~ _zz_304)); + assign _zz_56 = (_zz_55 & (~ _zz_309)); assign _zz_57 = _zz_56[3]; assign _zz_58 = (_zz_56[1] || _zz_57); assign _zz_59 = (_zz_56[2] || _zz_57); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_225; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_230; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3122,7 +3117,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_306); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_311); if(IBusCachedPlugin_fetchPc_inc)begin IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end @@ -3149,15 +3144,15 @@ module VexRiscv ( assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; always @ (*) begin IBusCachedPlugin_decodePc_flushed = 1'b0; - if(_zz_244)begin + if(_zz_249)begin IBusCachedPlugin_decodePc_flushed = 1'b1; end end - assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_308); + assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_313); always @ (*) begin IBusCachedPlugin_decodePc_injectedDecode = 1'b0; - if((_zz_161 != 3'b000))begin + if((_zz_166 != 3'b000))begin IBusCachedPlugin_decodePc_injectedDecode = 1'b1; end end @@ -3234,8 +3229,8 @@ module VexRiscv ( assign IBusCachedPlugin_decompressor_isRvc = (IBusCachedPlugin_decompressor_raw[1 : 0] != 2'b11); assign _zz_65 = IBusCachedPlugin_decompressor_raw[15 : 0]; always @ (*) begin - IBusCachedPlugin_decompressor_decompressed = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - case(_zz_266) + IBusCachedPlugin_decompressor_decompressed = 32'h0; + case(_zz_271) 5'h0 : begin IBusCachedPlugin_decompressor_decompressed = {{{{{{{{{2'b00,_zz_65[10 : 7]},_zz_65[12 : 11]},_zz_65[5]},_zz_65[6]},2'b00},5'h02},3'b000},_zz_67},7'h13}; end @@ -3255,10 +3250,10 @@ module VexRiscv ( IBusCachedPlugin_decompressor_decompressed = {{{{_zz_70,5'h0},3'b000},_zz_65[11 : 7]},7'h13}; end 5'h0b : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_65[11 : 7] == 5'h02) ? {{{{{{{{{_zz_77,_zz_65[4 : 3]},_zz_65[5]},_zz_65[2]},_zz_65[6]},4'b0000},_zz_65[11 : 7]},3'b000},_zz_65[11 : 7]},7'h13} : {{_zz_309[31 : 12],_zz_65[11 : 7]},7'h37}); + IBusCachedPlugin_decompressor_decompressed = ((_zz_65[11 : 7] == 5'h02) ? {{{{{{{{{_zz_77,_zz_65[4 : 3]},_zz_65[5]},_zz_65[2]},_zz_65[6]},4'b0000},_zz_65[11 : 7]},3'b000},_zz_65[11 : 7]},7'h13} : {{_zz_314[31 : 12],_zz_65[11 : 7]},7'h37}); end 5'h0c : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_65[11 : 10] == 2'b10) ? _zz_91 : {{1'b0,(_zz_384 || _zz_385)},5'h0}),(((! _zz_65[11]) || _zz_87) ? _zz_65[6 : 2] : _zz_67)},_zz_66},_zz_89},_zz_66},(_zz_87 ? 7'h13 : 7'h33)}; + IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_65[11 : 10] == 2'b10) ? _zz_91 : {{1'b0,(_zz_389 || _zz_390)},5'h0}),(((! _zz_65[11]) || _zz_87) ? _zz_65[6 : 2] : _zz_67)},_zz_66},_zz_89},_zz_66},(_zz_87 ? 7'h13 : 7'h33)}; end 5'h0d : begin IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_80[20],_zz_80[10 : 1]},_zz_80[11]},_zz_80[19 : 12]},_zz_84},7'h6f}; @@ -3276,10 +3271,10 @@ module VexRiscv ( IBusCachedPlugin_decompressor_decompressed = {{{{{{{{4'b0000,_zz_65[3 : 2]},_zz_65[12]},_zz_65[6 : 4]},2'b00},_zz_86},3'b010},_zz_65[11 : 7]},7'h03}; end 5'h14 : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_65[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_65[6 : 2] == 5'h0) ? {{{{12'h0,_zz_65[11 : 7]},3'b000},(_zz_65[12] ? _zz_85 : _zz_84)},7'h67} : {{{{{_zz_386,_zz_387},(_zz_388 ? _zz_389 : _zz_84)},3'b000},_zz_65[11 : 7]},7'h33})); + IBusCachedPlugin_decompressor_decompressed = ((_zz_65[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_65[6 : 2] == 5'h0) ? {{{{12'h0,_zz_65[11 : 7]},3'b000},(_zz_65[12] ? _zz_85 : _zz_84)},7'h67} : {{{{{_zz_391,_zz_392},(_zz_393 ? _zz_394 : _zz_84)},3'b000},_zz_65[11 : 7]},7'h33})); end 5'h16 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_310[11 : 5],_zz_65[6 : 2]},_zz_86},3'b010},_zz_311[4 : 0]},7'h23}; + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_315[11 : 5],_zz_65[6 : 2]},_zz_86},3'b010},_zz_316[4 : 0]},7'h23}; end default : begin end @@ -3372,7 +3367,7 @@ module VexRiscv ( assign _zz_86 = 5'h02; assign _zz_87 = (_zz_65[11 : 10] != 2'b11); always @ (*) begin - case(_zz_267) + case(_zz_272) 2'b00 : begin _zz_88 = 3'b000; end @@ -3389,7 +3384,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_268) + case(_zz_273) 2'b00 : begin _zz_89 = 3'b101; end @@ -3435,7 +3430,7 @@ module VexRiscv ( assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; - case(_zz_161) + case(_zz_166) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3447,7 +3442,7 @@ module VexRiscv ( endcase end - assign _zz_97 = _zz_312[11]; + assign _zz_97 = _zz_317[11]; always @ (*) begin _zz_98[18] = _zz_97; _zz_98[17] = _zz_97; @@ -3470,9 +3465,9 @@ module VexRiscv ( _zz_98[0] = _zz_97; end - assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_313[31])); + assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_318[31])); assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_99 = _zz_314[19]; + assign _zz_99 = _zz_319[19]; always @ (*) begin _zz_100[10] = _zz_99; _zz_100[9] = _zz_99; @@ -3487,7 +3482,7 @@ module VexRiscv ( _zz_100[0] = _zz_99; end - assign _zz_101 = _zz_315[11]; + assign _zz_101 = _zz_320[11]; always @ (*) begin _zz_102[18] = _zz_101; _zz_102[17] = _zz_101; @@ -3510,7 +3505,7 @@ module VexRiscv ( _zz_102[0] = _zz_101; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_100,{{{_zz_390,_zz_391},_zz_392},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_102,{{{_zz_393,_zz_394},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_100,{{{_zz_395,_zz_396},_zz_397},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_102,{{{_zz_398,_zz_399},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3519,50 +3514,50 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_195 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_196 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_197 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_196; + assign _zz_200 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_201 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_202 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_201; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_199 = (CsrPlugin_privilege == 2'b00); + assign _zz_204 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_235)begin + if(_zz_240)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_233)begin + if(_zz_238)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_203 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); - if(_zz_233)begin - _zz_203 = 1'b1; + _zz_208 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(_zz_238)begin + _zz_208 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_234)begin + if(_zz_239)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_232)begin + if(_zz_237)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_234)begin + if(_zz_239)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_232)begin + if(_zz_237)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3572,9 +3567,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_1_output_payload; - assign _zz_194 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_199 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_222 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_227 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3601,8 +3596,8 @@ module VexRiscv ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_204 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_205 = execute_SRC_ADD; + assign _zz_209 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_210 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3617,27 +3612,27 @@ module VexRiscv ( endcase end - assign _zz_221 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_206 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_207 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_206; + assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_211 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_212 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_211; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_207; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_212; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_208 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_213 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_54 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_208 = 1'b1; + _zz_213 = 1'b1; end end - assign _zz_209 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_210 = (CsrPlugin_privilege == 2'b00); - assign _zz_211 = writeBack_REGFILE_WRITE_DATA; + assign _zz_214 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_215 = (CsrPlugin_privilege == 2'b00); + assign _zz_216 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_245)begin + if(_zz_250)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3647,7 +3642,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_245)begin + if(_zz_250)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3666,15 +3661,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_245)begin + if(_zz_250)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_316}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_321}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_317}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_322}; end end end @@ -3747,7 +3742,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_269) + case(_zz_274) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_107; end @@ -3782,7 +3777,7 @@ module VexRiscv ( assign _zz_112 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_113 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_114 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_110 = {(((decode_INSTRUCTION & _zz_395) == 32'h00100050) != 1'b0),{(_zz_114 != 1'b0),{(_zz_114 != 1'b0),{(_zz_396 != _zz_397),{_zz_398,{_zz_399,_zz_400}}}}}}; + assign _zz_110 = {(((decode_INSTRUCTION & _zz_400) == 32'h00100050) != 1'b0),{(_zz_114 != 1'b0),{(_zz_114 != 1'b0),{(_zz_401 != _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; assign _zz_115 = _zz_110[2 : 1]; assign _zz_49 = _zz_115; assign _zz_116 = _zz_110[7 : 6]; @@ -3802,8 +3797,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_223; - assign decode_RegFilePlugin_rs2Data = _zz_224; + assign decode_RegFilePlugin_rs1Data = _zz_228; + assign decode_RegFilePlugin_rs2Data = _zz_229; always @ (*) begin lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); if(_zz_122)begin @@ -3845,7 +3840,7 @@ module VexRiscv ( _zz_123 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_123 = {31'd0, _zz_318}; + _zz_123 = {31'd0, _zz_323}; end default : begin _zz_123 = execute_SRC_ADD_SUB; @@ -3859,18 +3854,18 @@ module VexRiscv ( _zz_124 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_124 = {29'd0, _zz_319}; + _zz_124 = {29'd0, _zz_324}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_124 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_124 = {27'd0, _zz_320}; + _zz_124 = {27'd0, _zz_325}; end endcase end - assign _zz_125 = _zz_321[11]; + assign _zz_125 = _zz_326[11]; always @ (*) begin _zz_126[19] = _zz_125; _zz_126[18] = _zz_125; @@ -3894,7 +3889,7 @@ module VexRiscv ( _zz_126[0] = _zz_125; end - assign _zz_127 = _zz_322[11]; + assign _zz_127 = _zz_327[11]; always @ (*) begin _zz_128[19] = _zz_127; _zz_128[18] = _zz_127; @@ -3936,7 +3931,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_323; + execute_SrcPlugin_addSub = _zz_328; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -4016,99 +4011,94 @@ module VexRiscv ( end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_246)begin - if(_zz_247)begin - if(_zz_132)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_132 = 1'b0; + if(_zz_251)begin + if(_zz_252)begin + if(_zz_137)begin + _zz_132 = 1'b1; end end end - if(_zz_248)begin - if(_zz_249)begin - if(_zz_134)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_253)begin + if(_zz_254)begin + if(_zz_139)begin + _zz_132 = 1'b1; end end end - if(_zz_250)begin - if(_zz_251)begin - if(_zz_136)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_255)begin + if(_zz_256)begin + if(_zz_141)begin + _zz_132 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_132 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_246)begin - if(_zz_247)begin - if(_zz_133)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_133 = 1'b0; + if(_zz_251)begin + if(_zz_252)begin + if(_zz_138)begin + _zz_133 = 1'b1; end end end - if(_zz_248)begin - if(_zz_249)begin - if(_zz_135)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_253)begin + if(_zz_254)begin + if(_zz_140)begin + _zz_133 = 1'b1; end end end - if(_zz_250)begin - if(_zz_251)begin - if(_zz_137)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_255)begin + if(_zz_256)begin + if(_zz_142)begin + _zz_133 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_133 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_132 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_133 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_134 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_135 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_136 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_137 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_137 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_138 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_139 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_140 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_141 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_142 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_138 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_138 == 3'b000)) begin - _zz_139 = execute_BranchPlugin_eq; - end else if((_zz_138 == 3'b001)) begin - _zz_139 = (! execute_BranchPlugin_eq); - end else if((((_zz_138 & 3'b101) == 3'b101))) begin - _zz_139 = (! execute_SRC_LESS); + assign _zz_143 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_143 == 3'b000)) begin + _zz_144 = execute_BranchPlugin_eq; + end else if((_zz_143 == 3'b001)) begin + _zz_144 = (! execute_BranchPlugin_eq); + end else if((((_zz_143 & 3'b101) == 3'b101))) begin + _zz_144 = (! execute_SRC_LESS); end else begin - _zz_139 = execute_SRC_LESS; + _zz_144 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_140 = 1'b0; + _zz_145 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_140 = 1'b1; + _zz_145 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_140 = 1'b1; + _zz_145 = 1'b1; end default : begin - _zz_140 = _zz_139; + _zz_145 = _zz_144; end endcase end @@ -4125,80 +4115,80 @@ module VexRiscv ( endcase end - assign _zz_141 = _zz_330[11]; + assign _zz_146 = _zz_335[11]; always @ (*) begin - _zz_142[19] = _zz_141; - _zz_142[18] = _zz_141; - _zz_142[17] = _zz_141; - _zz_142[16] = _zz_141; - _zz_142[15] = _zz_141; - _zz_142[14] = _zz_141; - _zz_142[13] = _zz_141; - _zz_142[12] = _zz_141; - _zz_142[11] = _zz_141; - _zz_142[10] = _zz_141; - _zz_142[9] = _zz_141; - _zz_142[8] = _zz_141; - _zz_142[7] = _zz_141; - _zz_142[6] = _zz_141; - _zz_142[5] = _zz_141; - _zz_142[4] = _zz_141; - _zz_142[3] = _zz_141; - _zz_142[2] = _zz_141; - _zz_142[1] = _zz_141; - _zz_142[0] = _zz_141; + _zz_147[19] = _zz_146; + _zz_147[18] = _zz_146; + _zz_147[17] = _zz_146; + _zz_147[16] = _zz_146; + _zz_147[15] = _zz_146; + _zz_147[14] = _zz_146; + _zz_147[13] = _zz_146; + _zz_147[12] = _zz_146; + _zz_147[11] = _zz_146; + _zz_147[10] = _zz_146; + _zz_147[9] = _zz_146; + _zz_147[8] = _zz_146; + _zz_147[7] = _zz_146; + _zz_147[6] = _zz_146; + _zz_147[5] = _zz_146; + _zz_147[4] = _zz_146; + _zz_147[3] = _zz_146; + _zz_147[2] = _zz_146; + _zz_147[1] = _zz_146; + _zz_147[0] = _zz_146; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_142,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_147,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_144,{{{_zz_559,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_146,{{{_zz_560,_zz_561},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_149,{{{_zz_564,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_151,{{{_zz_565,_zz_566},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_333}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_338}; end end endcase end - assign _zz_143 = _zz_331[19]; - always @ (*) begin - _zz_144[10] = _zz_143; - _zz_144[9] = _zz_143; - _zz_144[8] = _zz_143; - _zz_144[7] = _zz_143; - _zz_144[6] = _zz_143; - _zz_144[5] = _zz_143; - _zz_144[4] = _zz_143; - _zz_144[3] = _zz_143; - _zz_144[2] = _zz_143; - _zz_144[1] = _zz_143; - _zz_144[0] = _zz_143; - end - - assign _zz_145 = _zz_332[11]; - always @ (*) begin - _zz_146[18] = _zz_145; - _zz_146[17] = _zz_145; - _zz_146[16] = _zz_145; - _zz_146[15] = _zz_145; - _zz_146[14] = _zz_145; - _zz_146[13] = _zz_145; - _zz_146[12] = _zz_145; - _zz_146[11] = _zz_145; - _zz_146[10] = _zz_145; - _zz_146[9] = _zz_145; - _zz_146[8] = _zz_145; - _zz_146[7] = _zz_145; - _zz_146[6] = _zz_145; - _zz_146[5] = _zz_145; - _zz_146[4] = _zz_145; - _zz_146[3] = _zz_145; - _zz_146[2] = _zz_145; - _zz_146[1] = _zz_145; - _zz_146[0] = _zz_145; + assign _zz_148 = _zz_336[19]; + always @ (*) begin + _zz_149[10] = _zz_148; + _zz_149[9] = _zz_148; + _zz_149[8] = _zz_148; + _zz_149[7] = _zz_148; + _zz_149[6] = _zz_148; + _zz_149[5] = _zz_148; + _zz_149[4] = _zz_148; + _zz_149[3] = _zz_148; + _zz_149[2] = _zz_148; + _zz_149[1] = _zz_148; + _zz_149[0] = _zz_148; + end + + assign _zz_150 = _zz_337[11]; + always @ (*) begin + _zz_151[18] = _zz_150; + _zz_151[17] = _zz_150; + _zz_151[16] = _zz_150; + _zz_151[15] = _zz_150; + _zz_151[14] = _zz_150; + _zz_151[13] = _zz_150; + _zz_151[12] = _zz_150; + _zz_151[11] = _zz_150; + _zz_151[10] = _zz_150; + _zz_151[9] = _zz_150; + _zz_151[8] = _zz_150; + _zz_151[7] = _zz_150; + _zz_151[6] = _zz_150; + _zz_151[5] = _zz_150; + _zz_151[4] = _zz_150; + _zz_151[3] = _zz_150; + _zz_151[2] = _zz_150; + _zz_151[1] = _zz_150; + _zz_151[0] = _zz_150; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -4212,16 +4202,16 @@ module VexRiscv ( end end - assign _zz_147 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_148 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_149 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_152 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_153 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_154 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_150 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_151 = _zz_334[0]; + assign _zz_155 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_156 = _zz_339[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_236)begin + if(_zz_241)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4299,7 +4289,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4405,7 +4395,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_252)begin + if(_zz_257)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4424,20 +4414,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_253)begin + if(_zz_258)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_254)begin + if(_zz_259)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_253)begin + if(_zz_258)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_254)begin + if(_zz_259)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4452,14 +4442,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_252)begin + if(_zz_257)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_252)begin + if(_zz_257)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4468,7 +4458,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_270) + case(_zz_275) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4482,7 +4472,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_255) + case(_zz_260) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4496,7 +4486,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_255) + case(_zz_260) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4515,12 +4505,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_336) + $signed(_zz_337)); + assign writeBack_MulPlugin_result = ($signed(_zz_341) + $signed(_zz_342)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_231)begin - if(_zz_256)begin + if(_zz_236)begin + if(_zz_261)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4528,7 +4518,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_257)begin + if(_zz_262)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4539,32 +4529,32 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_341); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_346); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_152 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_152[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_342); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_343 : _zz_344); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_345[31:0]; - assign _zz_153 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_154 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_155 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_157 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_157[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_347); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_348 : _zz_349); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_350[31:0]; + assign _zz_158 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_159 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_160 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_156[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_156[31 : 0] = execute_RS1; + _zz_161[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_161[31 : 0] = execute_RS1; end - assign _zz_158 = (_zz_157 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_158 != 32'h0); + assign _zz_163 = (_zz_162 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_163 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_258) + case(_zz_263) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4578,7 +4568,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_159))begin + if((! _zz_164))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4590,7 +4580,7 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_258) + case(_zz_263) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4654,7 +4644,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_161) + case(_zz_166) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4664,216 +4654,216 @@ module VexRiscv ( end always @ (*) begin - _zz_162 = 32'h0; + _zz_167 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_162[12 : 0] = 13'h1000; - _zz_162[25 : 20] = 6'h20; + _zz_167[12 : 0] = 13'h1000; + _zz_167[25 : 20] = 6'h20; end end always @ (*) begin - _zz_163 = 32'h0; + _zz_168 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_163[3 : 0] = 4'b1011; + _zz_168[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_164 = 32'h0; + _zz_169 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_164[4 : 0] = 5'h16; + _zz_169[4 : 0] = 5'h16; end end always @ (*) begin - _zz_165 = 32'h0; + _zz_170 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_165[5 : 0] = 6'h21; + _zz_170[5 : 0] = 6'h21; end end always @ (*) begin - _zz_166 = 32'h0; + _zz_171 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_166[31 : 30] = CsrPlugin_misa_base; - _zz_166[25 : 0] = CsrPlugin_misa_extensions; + _zz_171[31 : 30] = CsrPlugin_misa_base; + _zz_171[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_167 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_167[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_167[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_167[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_172[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_172[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_172[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_168 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_168[11 : 11] = CsrPlugin_mip_MEIP; - _zz_168[7 : 7] = CsrPlugin_mip_MTIP; - _zz_168[3 : 3] = CsrPlugin_mip_MSIP; + _zz_173[11 : 11] = CsrPlugin_mip_MEIP; + _zz_173[7 : 7] = CsrPlugin_mip_MTIP; + _zz_173[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_169 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_169[11 : 11] = CsrPlugin_mie_MEIE; - _zz_169[7 : 7] = CsrPlugin_mie_MTIE; - _zz_169[3 : 3] = CsrPlugin_mie_MSIE; + _zz_174[11 : 11] = CsrPlugin_mie_MEIE; + _zz_174[7 : 7] = CsrPlugin_mie_MTIE; + _zz_174[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_170 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_170[31 : 2] = CsrPlugin_mtvec_base; - _zz_170[1 : 0] = CsrPlugin_mtvec_mode; + _zz_175[31 : 2] = CsrPlugin_mtvec_base; + _zz_175[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_171[31 : 0] = CsrPlugin_mepc; + _zz_176[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_172[31 : 0] = CsrPlugin_mscratch; + _zz_177[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_173[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_173[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_178[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_178[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_174[31 : 0] = CsrPlugin_mtval; + _zz_179[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_175[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_180[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_176[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_181[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_177[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_182[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_178[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_183[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_179[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_184[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_180[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_185[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_181[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_186[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_182[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_187[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_183[31 : 0] = _zz_157; + _zz_188[31 : 0] = _zz_162; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_184[31 : 0] = _zz_158; + _zz_189[31 : 0] = _zz_163; end end - assign execute_CsrPlugin_readData = (((((_zz_162 | _zz_163) | (_zz_164 | _zz_165)) | ((_zz_562 | _zz_166) | (_zz_167 | _zz_168))) | (((_zz_169 | _zz_170) | (_zz_171 | _zz_172)) | ((_zz_173 | _zz_174) | (_zz_175 | _zz_176)))) | (((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_181 | _zz_182) | (_zz_183 | _zz_184)))); - assign iBusWishbone_ADR = {_zz_362,_zz_185}; - assign iBusWishbone_CTI = ((_zz_185 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_167 | _zz_168) | (_zz_169 | _zz_170)) | ((_zz_567 | _zz_171) | (_zz_172 | _zz_173))) | (((_zz_174 | _zz_175) | (_zz_176 | _zz_177)) | ((_zz_178 | _zz_179) | (_zz_180 | _zz_181)))) | (((_zz_182 | _zz_183) | (_zz_184 | _zz_185)) | ((_zz_186 | _zz_187) | (_zz_188 | _zz_189)))); + assign iBusWishbone_ADR = {_zz_367,_zz_190}; + assign iBusWishbone_CTI = ((_zz_190 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_259)begin + if(_zz_264)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_259)begin + if(_zz_264)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_186; + assign iBus_rsp_valid = _zz_191; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_192 = (dBus_cmd_payload_length != 3'b000); - assign _zz_188 = dBus_cmd_valid; - assign _zz_190 = dBus_cmd_payload_wr; - assign _zz_191 = (_zz_187 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_189 && (_zz_190 || _zz_191)); - assign dBusWishbone_ADR = ((_zz_192 ? {{dBus_cmd_payload_address[31 : 5],_zz_187},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_192 ? (_zz_191 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_197 = (dBus_cmd_payload_length != 3'b000); + assign _zz_193 = dBus_cmd_valid; + assign _zz_195 = dBus_cmd_payload_wr; + assign _zz_196 = (_zz_192 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_194 && (_zz_195 || _zz_196)); + assign dBusWishbone_ADR = ((_zz_197 ? {{dBus_cmd_payload_address[31 : 5],_zz_192},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_197 ? (_zz_196 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_190 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_190; + assign dBusWishbone_SEL = (_zz_195 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_195; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_189 = (_zz_188 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_188; - assign dBusWishbone_STB = _zz_188; - assign dBus_rsp_valid = _zz_193; + assign _zz_194 = (_zz_193 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_193; + assign dBusWishbone_STB = _zz_193; + assign dBus_rsp_valid = _zz_198; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4898,7 +4888,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= _zz_104; DBusCachedPlugin_rspCounter <= 32'h0; _zz_122 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_134 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4919,15 +4909,15 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_157 <= 32'h0; + _zz_162 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_161 <= 3'b000; - _zz_185 <= 3'b000; - _zz_186 <= 1'b0; - _zz_187 <= 3'b000; - _zz_193 <= 1'b0; + _zz_166 <= 3'b000; + _zz_190 <= 3'b000; + _zz_191 <= 1'b0; + _zz_192 <= 3'b000; + _zz_198 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -4951,7 +4941,7 @@ module VexRiscv ( if((decode_arbitration_isFiring && (! IBusCachedPlugin_decodePc_injectedDecode)))begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_decodePc_pcPlus; end - if(_zz_244)begin + if(_zz_249)begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_jump_pcLoad_payload; end if(IBusCachedPlugin_iBusRsp_flush)begin @@ -4966,7 +4956,7 @@ module VexRiscv ( if((IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid))begin IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end - if(_zz_260)begin + if(_zz_265)begin if(IBusCachedPlugin_decompressor_bufferFill)begin IBusCachedPlugin_decompressor_bufferValid <= 1'b1; end @@ -5011,7 +5001,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_261)begin + if(_zz_266)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5021,7 +5011,7 @@ module VexRiscv ( DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end _zz_122 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_134 <= (_zz_41 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5043,14 +5033,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_262)begin - if(_zz_263)begin + if(_zz_267)begin + if(_zz_268)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_264)begin + if(_zz_269)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_265)begin + if(_zz_270)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5075,7 +5065,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_240)begin + if(_zz_245)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5086,8 +5076,8 @@ module VexRiscv ( end endcase end - if(_zz_241)begin - case(_zz_243) + if(_zz_246)begin + case(_zz_248) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5097,7 +5087,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_149,{_zz_148,_zz_147}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_154,{_zz_153,_zz_152}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; @@ -5117,25 +5107,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_161) + case(_zz_166) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_161 <= 3'b001; + _zz_166 <= 3'b001; end end 3'b001 : begin - _zz_161 <= 3'b010; + _zz_166 <= 3'b010; end 3'b010 : begin - _zz_161 <= 3'b011; + _zz_166 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_161 <= 3'b100; + _zz_166 <= 3'b100; end end 3'b100 : begin - _zz_161 <= 3'b000; + _zz_166 <= 3'b000; end default : begin end @@ -5149,40 +5139,40 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_355[0]; - CsrPlugin_mstatus_MIE <= _zz_356[0]; + CsrPlugin_mstatus_MPIE <= _zz_360[0]; + CsrPlugin_mstatus_MIE <= _zz_361[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_358[0]; - CsrPlugin_mie_MTIE <= _zz_359[0]; - CsrPlugin_mie_MSIE <= _zz_360[0]; + CsrPlugin_mie_MEIE <= _zz_363[0]; + CsrPlugin_mie_MTIE <= _zz_364[0]; + CsrPlugin_mie_MSIE <= _zz_365[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_259)begin + if(_zz_264)begin if(iBusWishbone_ACK)begin - _zz_185 <= (_zz_185 + 3'b001); + _zz_190 <= (_zz_190 + 3'b001); end end - _zz_186 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_188 && _zz_189))begin - _zz_187 <= (_zz_187 + 3'b001); - if(_zz_191)begin - _zz_187 <= 3'b000; + _zz_191 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_193 && _zz_194))begin + _zz_192 <= (_zz_192 + 3'b001); + if(_zz_196)begin + _zz_192 <= 3'b000; end end - _zz_193 <= ((_zz_188 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_198 <= ((_zz_193 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end always @ (posedge clk) begin - if(_zz_260)begin + if(_zz_265)begin IBusCachedPlugin_decompressor_bufferData <= IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16]; end if(IBusCachedPlugin_decompressor_output_ready)begin @@ -5197,7 +5187,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(_zz_261)begin + if(_zz_266)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5215,8 +5205,8 @@ module VexRiscv ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_135 <= _zz_40[11 : 7]; + _zz_136 <= _zz_50; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5224,9 +5214,9 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_236)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_241)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_156 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_156 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -5236,21 +5226,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_262)begin - if(_zz_263)begin + if(_zz_267)begin + if(_zz_268)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_264)begin + if(_zz_269)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_265)begin + if(_zz_270)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_240)begin + if(_zz_245)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5270,20 +5260,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_231)begin - if(_zz_256)begin + if(_zz_236)begin + if(_zz_261)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_346[31:0]; + memory_DivPlugin_div_result <= _zz_351[31:0]; end end end - if(_zz_257)begin + if(_zz_262)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_155 ? (~ _zz_156) : _zz_156) + _zz_352); - memory_DivPlugin_rs2 <= ((_zz_154 ? (~ execute_RS2) : execute_RS2) + _zz_354); - memory_DivPlugin_div_needRevert <= ((_zz_155 ^ (_zz_154 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_160 ? (~ _zz_161) : _zz_161) + _zz_357); + memory_DivPlugin_rs2 <= ((_zz_159 ? (~ execute_RS2) : execute_RS2) + _zz_359); + memory_DivPlugin_div_needRevert <= ((_zz_160 ^ (_zz_159 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5478,7 +5468,7 @@ module VexRiscv ( if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((_zz_161 != 3'b000))begin + if((_zz_166 != 3'b000))begin _zz_95 <= IBusCachedPlugin_injectionPort_payload; end if((! execute_arbitration_isStuck))begin @@ -5555,7 +5545,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_357[0]; + CsrPlugin_mip_MSIP <= _zz_362[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5576,7 +5566,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_361[0]; + CsrPlugin_mcause_interrupt <= _zz_366[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5619,8 +5609,8 @@ module VexRiscv ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_50; end - _zz_159 <= debug_bus_cmd_payload_address[2]; - if(_zz_238)begin + _zz_164 <= debug_bus_cmd_payload_address[2]; + if(_zz_243)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -5633,13 +5623,13 @@ module VexRiscv ( DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; - _zz_160 <= 1'b0; + _zz_165 <= 1'b0; end else begin if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_258) + case(_zz_263) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -5667,18 +5657,18 @@ module VexRiscv ( end endcase end - if(_zz_238)begin - if(_zz_239)begin + if(_zz_243)begin + if(_zz_244)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_242)begin + if(_zz_247)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end end - _zz_160 <= (DebugPlugin_stepIt && decode_arbitration_isFiring); + _zz_165 <= (DebugPlugin_stepIt && decode_arbitration_isFiring); end end @@ -5968,7 +5958,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_12)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -5982,7 +5972,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_12)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -6012,7 +6002,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -6039,7 +6029,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -6071,7 +6061,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -6081,7 +6071,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v index b39bc51..d014909 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -81,66 +81,66 @@ module VexRiscv ( input clk, input reset ); - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - wire _zz_204; wire _zz_205; wire _zz_206; wire _zz_207; - reg _zz_208; - reg _zz_209; - reg [31:0] _zz_210; - reg _zz_211; - reg [31:0] _zz_212; - reg [1:0] _zz_213; + wire _zz_208; + wire _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + reg _zz_213; reg _zz_214; - reg _zz_215; - wire _zz_216; - wire [2:0] _zz_217; - reg _zz_218; - wire [31:0] _zz_219; + reg [31:0] _zz_215; + reg _zz_216; + reg [31:0] _zz_217; + reg [1:0] _zz_218; + reg _zz_219; reg _zz_220; - reg _zz_221; - wire _zz_222; - wire [31:0] _zz_223; - wire _zz_224; - wire _zz_225; - wire _zz_226; + wire _zz_221; + wire [2:0] _zz_222; + reg _zz_223; + wire [31:0] _zz_224; + reg _zz_225; + reg _zz_226; wire _zz_227; - wire _zz_228; + wire [31:0] _zz_228; wire _zz_229; wire _zz_230; wire _zz_231; - wire [3:0] _zz_232; + wire _zz_232; wire _zz_233; wire _zz_234; - reg [31:0] _zz_235; - reg [31:0] _zz_236; - reg [31:0] _zz_237; - reg _zz_238; - reg _zz_239; - reg _zz_240; - reg [9:0] _zz_241; - reg [9:0] _zz_242; - reg [9:0] _zz_243; - reg [9:0] _zz_244; + wire _zz_235; + wire _zz_236; + wire [3:0] _zz_237; + wire _zz_238; + wire _zz_239; + reg [31:0] _zz_240; + reg [31:0] _zz_241; + reg [31:0] _zz_242; + reg _zz_243; + reg _zz_244; reg _zz_245; - reg _zz_246; - reg _zz_247; - reg _zz_248; - reg _zz_249; + reg [9:0] _zz_246; + reg [9:0] _zz_247; + reg [9:0] _zz_248; + reg [9:0] _zz_249; reg _zz_250; reg _zz_251; - reg [9:0] _zz_252; - reg [9:0] _zz_253; - reg [9:0] _zz_254; - reg [9:0] _zz_255; + reg _zz_252; + reg _zz_253; + reg _zz_254; + reg _zz_255; reg _zz_256; - reg _zz_257; - reg _zz_258; - reg _zz_259; + reg [9:0] _zz_257; + reg [9:0] _zz_258; + reg [9:0] _zz_259; + reg [9:0] _zz_260; + reg _zz_261; + reg _zz_262; + reg _zz_263; + reg _zz_264; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -173,11 +173,6 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_260; - wire _zz_261; - wire _zz_262; - wire _zz_263; - wire _zz_264; wire _zz_265; wire _zz_266; wire _zz_267; @@ -187,12 +182,12 @@ module VexRiscv ( wire _zz_271; wire _zz_272; wire _zz_273; - wire [1:0] _zz_274; + wire _zz_274; wire _zz_275; wire _zz_276; wire _zz_277; wire _zz_278; - wire _zz_279; + wire [1:0] _zz_279; wire _zz_280; wire _zz_281; wire _zz_282; @@ -203,12 +198,12 @@ module VexRiscv ( wire _zz_287; wire _zz_288; wire _zz_289; - wire [1:0] _zz_290; + wire _zz_290; wire _zz_291; wire _zz_292; wire _zz_293; wire _zz_294; - wire _zz_295; + wire [1:0] _zz_295; wire _zz_296; wire _zz_297; wire _zz_298; @@ -228,26 +223,26 @@ module VexRiscv ( wire _zz_312; wire _zz_313; wire _zz_314; - wire [1:0] _zz_315; + wire _zz_315; wire _zz_316; - wire [1:0] _zz_317; - wire [51:0] _zz_318; - wire [51:0] _zz_319; - wire [51:0] _zz_320; - wire [32:0] _zz_321; - wire [51:0] _zz_322; - wire [49:0] _zz_323; + wire _zz_317; + wire _zz_318; + wire _zz_319; + wire [1:0] _zz_320; + wire _zz_321; + wire [1:0] _zz_322; + wire [51:0] _zz_323; wire [51:0] _zz_324; - wire [49:0] _zz_325; - wire [51:0] _zz_326; - wire [32:0] _zz_327; - wire [31:0] _zz_328; - wire [32:0] _zz_329; - wire [0:0] _zz_330; - wire [0:0] _zz_331; - wire [0:0] _zz_332; - wire [0:0] _zz_333; - wire [0:0] _zz_334; + wire [51:0] _zz_325; + wire [32:0] _zz_326; + wire [51:0] _zz_327; + wire [49:0] _zz_328; + wire [51:0] _zz_329; + wire [49:0] _zz_330; + wire [51:0] _zz_331; + wire [32:0] _zz_332; + wire [31:0] _zz_333; + wire [32:0] _zz_334; wire [0:0] _zz_335; wire [0:0] _zz_336; wire [0:0] _zz_337; @@ -263,80 +258,80 @@ module VexRiscv ( wire [0:0] _zz_347; wire [0:0] _zz_348; wire [0:0] _zz_349; - wire [4:0] _zz_350; - wire [2:0] _zz_351; - wire [31:0] _zz_352; - wire [11:0] _zz_353; - wire [31:0] _zz_354; - wire [19:0] _zz_355; - wire [11:0] _zz_356; + wire [0:0] _zz_350; + wire [0:0] _zz_351; + wire [0:0] _zz_352; + wire [0:0] _zz_353; + wire [0:0] _zz_354; + wire [4:0] _zz_355; + wire [2:0] _zz_356; wire [31:0] _zz_357; - wire [31:0] _zz_358; - wire [19:0] _zz_359; - wire [11:0] _zz_360; - wire [2:0] _zz_361; - wire [2:0] _zz_362; - wire [0:0] _zz_363; - wire [1:0] _zz_364; - wire [0:0] _zz_365; - wire [1:0] _zz_366; - wire [0:0] _zz_367; + wire [11:0] _zz_358; + wire [31:0] _zz_359; + wire [19:0] _zz_360; + wire [11:0] _zz_361; + wire [31:0] _zz_362; + wire [31:0] _zz_363; + wire [19:0] _zz_364; + wire [11:0] _zz_365; + wire [2:0] _zz_366; + wire [2:0] _zz_367; wire [0:0] _zz_368; - wire [0:0] _zz_369; + wire [1:0] _zz_369; wire [0:0] _zz_370; - wire [0:0] _zz_371; + wire [1:0] _zz_371; wire [0:0] _zz_372; wire [0:0] _zz_373; wire [0:0] _zz_374; - wire [1:0] _zz_375; + wire [0:0] _zz_375; wire [0:0] _zz_376; - wire [2:0] _zz_377; - wire [4:0] _zz_378; - wire [11:0] _zz_379; - wire [11:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire [31:0] _zz_384; - wire [31:0] _zz_385; + wire [0:0] _zz_377; + wire [0:0] _zz_378; + wire [0:0] _zz_379; + wire [1:0] _zz_380; + wire [0:0] _zz_381; + wire [2:0] _zz_382; + wire [4:0] _zz_383; + wire [11:0] _zz_384; + wire [11:0] _zz_385; wire [31:0] _zz_386; wire [31:0] _zz_387; - wire [11:0] _zz_388; - wire [19:0] _zz_389; - wire [11:0] _zz_390; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; wire [31:0] _zz_391; wire [31:0] _zz_392; - wire [31:0] _zz_393; - wire [11:0] _zz_394; - wire [19:0] _zz_395; - wire [11:0] _zz_396; - wire [2:0] _zz_397; - wire [1:0] _zz_398; - wire [1:0] _zz_399; - wire [65:0] _zz_400; - wire [65:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [0:0] _zz_404; - wire [5:0] _zz_405; - wire [32:0] _zz_406; + wire [11:0] _zz_393; + wire [19:0] _zz_394; + wire [11:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire [11:0] _zz_399; + wire [19:0] _zz_400; + wire [11:0] _zz_401; + wire [2:0] _zz_402; + wire [1:0] _zz_403; + wire [1:0] _zz_404; + wire [65:0] _zz_405; + wire [65:0] _zz_406; wire [31:0] _zz_407; wire [31:0] _zz_408; - wire [32:0] _zz_409; - wire [32:0] _zz_410; + wire [0:0] _zz_409; + wire [5:0] _zz_410; wire [32:0] _zz_411; - wire [32:0] _zz_412; - wire [0:0] _zz_413; + wire [31:0] _zz_412; + wire [31:0] _zz_413; wire [32:0] _zz_414; - wire [0:0] _zz_415; + wire [32:0] _zz_415; wire [32:0] _zz_416; - wire [0:0] _zz_417; - wire [31:0] _zz_418; - wire [0:0] _zz_419; + wire [32:0] _zz_417; + wire [0:0] _zz_418; + wire [32:0] _zz_419; wire [0:0] _zz_420; - wire [0:0] _zz_421; + wire [32:0] _zz_421; wire [0:0] _zz_422; - wire [0:0] _zz_423; + wire [31:0] _zz_423; wire [0:0] _zz_424; wire [0:0] _zz_425; wire [0:0] _zz_426; @@ -377,239 +372,244 @@ module VexRiscv ( wire [0:0] _zz_461; wire [0:0] _zz_462; wire [0:0] _zz_463; - wire [26:0] _zz_464; - wire _zz_465; - wire _zz_466; - wire [2:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; + wire [0:0] _zz_464; + wire [0:0] _zz_465; + wire [0:0] _zz_466; + wire [0:0] _zz_467; + wire [0:0] _zz_468; + wire [26:0] _zz_469; + wire _zz_470; wire _zz_471; - wire [0:0] _zz_472; - wire [17:0] _zz_473; + wire [2:0] _zz_472; + wire [31:0] _zz_473; wire [31:0] _zz_474; wire [31:0] _zz_475; - wire [31:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [11:0] _zz_479; + wire _zz_476; + wire [0:0] _zz_477; + wire [17:0] _zz_478; + wire [31:0] _zz_479; wire [31:0] _zz_480; wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire _zz_483; - wire [0:0] _zz_484; - wire [5:0] _zz_485; + wire _zz_482; + wire [0:0] _zz_483; + wire [11:0] _zz_484; + wire [31:0] _zz_485; wire [31:0] _zz_486; wire [31:0] _zz_487; - wire [31:0] _zz_488; - wire _zz_489; - wire _zz_490; - wire _zz_491; - wire _zz_492; - wire _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; + wire _zz_488; + wire [0:0] _zz_489; + wire [5:0] _zz_490; + wire [31:0] _zz_491; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire _zz_494; + wire _zz_495; wire _zz_496; - wire [0:0] _zz_497; - wire [0:0] _zz_498; - wire _zz_499; - wire [0:0] _zz_500; - wire [27:0] _zz_501; - wire [31:0] _zz_502; - wire _zz_503; + wire _zz_497; + wire _zz_498; + wire [31:0] _zz_499; + wire [31:0] _zz_500; + wire _zz_501; + wire [0:0] _zz_502; + wire [0:0] _zz_503; wire _zz_504; wire [0:0] _zz_505; - wire [0:0] _zz_506; - wire [0:0] _zz_507; - wire [0:0] _zz_508; + wire [27:0] _zz_506; + wire [31:0] _zz_507; + wire _zz_508; wire _zz_509; wire [0:0] _zz_510; - wire [23:0] _zz_511; - wire [31:0] _zz_512; - wire [31:0] _zz_513; + wire [0:0] _zz_511; + wire [0:0] _zz_512; + wire [0:0] _zz_513; wire _zz_514; - wire _zz_515; - wire [0:0] _zz_516; - wire [1:0] _zz_517; - wire [0:0] _zz_518; - wire [0:0] _zz_519; + wire [0:0] _zz_515; + wire [23:0] _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire _zz_519; wire _zz_520; wire [0:0] _zz_521; - wire [20:0] _zz_522; - wire [31:0] _zz_523; - wire [31:0] _zz_524; - wire [31:0] _zz_525; - wire [31:0] _zz_526; - wire [31:0] _zz_527; + wire [1:0] _zz_522; + wire [0:0] _zz_523; + wire [0:0] _zz_524; + wire _zz_525; + wire [0:0] _zz_526; + wire [20:0] _zz_527; wire [31:0] _zz_528; wire [31:0] _zz_529; wire [31:0] _zz_530; - wire [0:0] _zz_531; - wire [0:0] _zz_532; - wire [0:0] _zz_533; - wire [0:0] _zz_534; - wire _zz_535; + wire [31:0] _zz_531; + wire [31:0] _zz_532; + wire [31:0] _zz_533; + wire [31:0] _zz_534; + wire [31:0] _zz_535; wire [0:0] _zz_536; - wire [17:0] _zz_537; - wire [31:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire [31:0] _zz_541; - wire [31:0] _zz_542; - wire _zz_543; - wire [3:0] _zz_544; - wire [3:0] _zz_545; - wire _zz_546; - wire [0:0] _zz_547; - wire [14:0] _zz_548; - wire [31:0] _zz_549; - wire [31:0] _zz_550; + wire [0:0] _zz_537; + wire [0:0] _zz_538; + wire [0:0] _zz_539; + wire _zz_540; + wire [0:0] _zz_541; + wire [17:0] _zz_542; + wire [31:0] _zz_543; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire _zz_548; + wire [3:0] _zz_549; + wire [3:0] _zz_550; wire _zz_551; wire [0:0] _zz_552; - wire [0:0] _zz_553; + wire [14:0] _zz_553; wire [31:0] _zz_554; wire [31:0] _zz_555; wire _zz_556; - wire [5:0] _zz_557; - wire [5:0] _zz_558; - wire _zz_559; - wire [0:0] _zz_560; - wire [11:0] _zz_561; - wire [31:0] _zz_562; - wire [31:0] _zz_563; - wire [31:0] _zz_564; - wire [31:0] _zz_565; - wire _zz_566; - wire [0:0] _zz_567; - wire [2:0] _zz_568; - wire _zz_569; - wire [0:0] _zz_570; - wire [0:0] _zz_571; + wire [0:0] _zz_557; + wire [0:0] _zz_558; + wire [31:0] _zz_559; + wire [31:0] _zz_560; + wire _zz_561; + wire [5:0] _zz_562; + wire [5:0] _zz_563; + wire _zz_564; + wire [0:0] _zz_565; + wire [11:0] _zz_566; + wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [31:0] _zz_570; + wire _zz_571; wire [0:0] _zz_572; - wire [3:0] _zz_573; - wire [4:0] _zz_574; - wire [4:0] _zz_575; - wire _zz_576; + wire [2:0] _zz_573; + wire _zz_574; + wire [0:0] _zz_575; + wire [0:0] _zz_576; wire [0:0] _zz_577; - wire [8:0] _zz_578; - wire [31:0] _zz_579; - wire [31:0] _zz_580; - wire [31:0] _zz_581; - wire _zz_582; - wire [0:0] _zz_583; - wire [0:0] _zz_584; + wire [3:0] _zz_578; + wire [4:0] _zz_579; + wire [4:0] _zz_580; + wire _zz_581; + wire [0:0] _zz_582; + wire [8:0] _zz_583; + wire [31:0] _zz_584; wire [31:0] _zz_585; wire [31:0] _zz_586; - wire [31:0] _zz_587; - wire [31:0] _zz_588; - wire [31:0] _zz_589; + wire _zz_587; + wire [0:0] _zz_588; + wire [0:0] _zz_589; wire [31:0] _zz_590; wire [31:0] _zz_591; - wire _zz_592; - wire [0:0] _zz_593; - wire [1:0] _zz_594; - wire [0:0] _zz_595; - wire [2:0] _zz_596; - wire [0:0] _zz_597; - wire [5:0] _zz_598; + wire [31:0] _zz_592; + wire [31:0] _zz_593; + wire [31:0] _zz_594; + wire [31:0] _zz_595; + wire [31:0] _zz_596; + wire _zz_597; + wire [0:0] _zz_598; wire [1:0] _zz_599; - wire [1:0] _zz_600; - wire _zz_601; + wire [0:0] _zz_600; + wire [2:0] _zz_601; wire [0:0] _zz_602; - wire [6:0] _zz_603; - wire [31:0] _zz_604; - wire [31:0] _zz_605; - wire [31:0] _zz_606; - wire [31:0] _zz_607; - wire [31:0] _zz_608; + wire [5:0] _zz_603; + wire [1:0] _zz_604; + wire [1:0] _zz_605; + wire _zz_606; + wire [0:0] _zz_607; + wire [6:0] _zz_608; wire [31:0] _zz_609; wire [31:0] _zz_610; wire [31:0] _zz_611; - wire _zz_612; + wire [31:0] _zz_612; wire [31:0] _zz_613; wire [31:0] _zz_614; - wire _zz_615; - wire [0:0] _zz_616; - wire [0:0] _zz_617; - wire _zz_618; - wire [0:0] _zz_619; - wire [3:0] _zz_620; - wire _zz_621; + wire [31:0] _zz_615; + wire [31:0] _zz_616; + wire _zz_617; + wire [31:0] _zz_618; + wire [31:0] _zz_619; + wire _zz_620; + wire [0:0] _zz_621; wire [0:0] _zz_622; - wire [0:0] _zz_623; + wire _zz_623; wire [0:0] _zz_624; - wire [0:0] _zz_625; + wire [3:0] _zz_625; wire _zz_626; wire [0:0] _zz_627; - wire [4:0] _zz_628; - wire [31:0] _zz_629; - wire [31:0] _zz_630; - wire [31:0] _zz_631; - wire [31:0] _zz_632; - wire [31:0] _zz_633; + wire [0:0] _zz_628; + wire [0:0] _zz_629; + wire [0:0] _zz_630; + wire _zz_631; + wire [0:0] _zz_632; + wire [4:0] _zz_633; wire [31:0] _zz_634; wire [31:0] _zz_635; wire [31:0] _zz_636; wire [31:0] _zz_637; - wire _zz_638; - wire [0:0] _zz_639; - wire [1:0] _zz_640; + wire [31:0] _zz_638; + wire [31:0] _zz_639; + wire [31:0] _zz_640; wire [31:0] _zz_641; wire [31:0] _zz_642; - wire [31:0] _zz_643; - wire [31:0] _zz_644; - wire [31:0] _zz_645; - wire _zz_646; - wire [4:0] _zz_647; - wire [4:0] _zz_648; - wire _zz_649; - wire [0:0] _zz_650; - wire [2:0] _zz_651; - wire [31:0] _zz_652; - wire [31:0] _zz_653; - wire [31:0] _zz_654; - wire _zz_655; - wire [31:0] _zz_656; - wire _zz_657; - wire [0:0] _zz_658; - wire [2:0] _zz_659; - wire [0:0] _zz_660; - wire [0:0] _zz_661; - wire [2:0] _zz_662; - wire [2:0] _zz_663; - wire _zz_664; + wire _zz_643; + wire [0:0] _zz_644; + wire [1:0] _zz_645; + wire [31:0] _zz_646; + wire [31:0] _zz_647; + wire [31:0] _zz_648; + wire [31:0] _zz_649; + wire [31:0] _zz_650; + wire _zz_651; + wire [4:0] _zz_652; + wire [4:0] _zz_653; + wire _zz_654; + wire [0:0] _zz_655; + wire [2:0] _zz_656; + wire [31:0] _zz_657; + wire [31:0] _zz_658; + wire [31:0] _zz_659; + wire _zz_660; + wire [31:0] _zz_661; + wire _zz_662; + wire [0:0] _zz_663; + wire [2:0] _zz_664; wire [0:0] _zz_665; wire [0:0] _zz_666; - wire [31:0] _zz_667; - wire [31:0] _zz_668; - wire [31:0] _zz_669; - wire [31:0] _zz_670; - wire _zz_671; - wire [0:0] _zz_672; - wire [0:0] _zz_673; + wire [2:0] _zz_667; + wire [2:0] _zz_668; + wire _zz_669; + wire [0:0] _zz_670; + wire [0:0] _zz_671; + wire [31:0] _zz_672; + wire [31:0] _zz_673; wire [31:0] _zz_674; wire [31:0] _zz_675; wire _zz_676; wire [0:0] _zz_677; wire [0:0] _zz_678; - wire [0:0] _zz_679; - wire [1:0] _zz_680; - wire [1:0] _zz_681; - wire [1:0] _zz_682; + wire [31:0] _zz_679; + wire [31:0] _zz_680; + wire _zz_681; + wire [0:0] _zz_682; wire [0:0] _zz_683; wire [0:0] _zz_684; - wire [31:0] _zz_685; - wire [31:0] _zz_686; - wire [31:0] _zz_687; - wire [31:0] _zz_688; - wire [31:0] _zz_689; + wire [1:0] _zz_685; + wire [1:0] _zz_686; + wire [1:0] _zz_687; + wire [0:0] _zz_688; + wire [0:0] _zz_689; wire [31:0] _zz_690; wire [31:0] _zz_691; wire [31:0] _zz_692; - wire _zz_693; - wire _zz_694; - wire _zz_695; + wire [31:0] _zz_693; + wire [31:0] _zz_694; + wire [31:0] _zz_695; wire [31:0] _zz_696; + wire [31:0] _zz_697; + wire _zz_698; + wire _zz_699; + wire _zz_700; + wire [31:0] _zz_701; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1315,44 +1315,39 @@ module VexRiscv ( reg [31:0] _zz_125; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_126; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_127; - wire _zz_128; - wire _zz_129; - wire _zz_130; - wire _zz_131; + reg _zz_127; + reg _zz_128; + reg _zz_129; + reg [4:0] _zz_130; + reg [31:0] _zz_131; wire _zz_132; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_133; - reg _zz_134; - reg _zz_135; + wire _zz_133; + wire _zz_134; + wire _zz_135; wire _zz_136; - reg [19:0] _zz_137; - wire _zz_138; - reg [10:0] _zz_139; - wire _zz_140; - reg [18:0] _zz_141; - reg _zz_142; + wire _zz_137; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_138; + reg _zz_139; + reg _zz_140; + wire _zz_141; + reg [19:0] _zz_142; + wire _zz_143; + reg [10:0] _zz_144; + wire _zz_145; + reg [18:0] _zz_146; + reg _zz_147; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_143; - reg [19:0] _zz_144; - wire _zz_145; - reg [10:0] _zz_146; - wire _zz_147; - reg [18:0] _zz_148; + wire _zz_148; + reg [19:0] _zz_149; + wire _zz_150; + reg [10:0] _zz_151; + wire _zz_152; + reg [18:0] _zz_153; wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] _zz_149; + reg [1:0] _zz_154; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1409,12 +1404,12 @@ module VexRiscv ( reg [21:0] CsrPlugin_satp_PPN; reg [8:0] CsrPlugin_satp_ASID; reg [0:0] CsrPlugin_satp_MODE; - wire _zz_150; - wire _zz_151; - wire _zz_152; - wire _zz_153; - wire _zz_154; wire _zz_155; + wire _zz_156; + wire _zz_157; + wire _zz_158; + wire _zz_159; + wire _zz_160; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1427,8 +1422,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_156; - wire _zz_157; + wire [1:0] _zz_161; + wire _zz_162; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1481,20 +1476,20 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_158; + wire [31:0] _zz_163; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_159; - wire _zz_160; - wire _zz_161; - reg [32:0] _zz_162; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_163; wire [31:0] _zz_164; - reg [31:0] _zz_165; - wire [31:0] _zz_166; + wire _zz_165; + wire _zz_166; + reg [32:0] _zz_167; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_168; + wire [31:0] _zz_169; + reg [31:0] _zz_170; + wire [31:0] _zz_171; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1592,11 +1587,6 @@ module VexRiscv ( reg execute_CsrPlugin_csr_4032; reg execute_CsrPlugin_csr_2496; reg execute_CsrPlugin_csr_3520; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; reg [31:0] _zz_172; reg [31:0] _zz_173; reg [31:0] _zz_174; @@ -1616,16 +1606,21 @@ module VexRiscv ( reg [31:0] _zz_188; reg [31:0] _zz_189; reg [31:0] _zz_190; - reg [2:0] _zz_191; - reg _zz_192; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [2:0] _zz_196; + reg _zz_197; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_193; - wire _zz_194; - wire _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; - reg _zz_199; + reg [2:0] _zz_198; + wire _zz_199; + wire _zz_200; + wire _zz_201; + wire _zz_202; + wire _zz_203; + reg _zz_204; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] _zz_1_string; @@ -1711,452 +1706,452 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_260 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_261 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_262 = 1'b1; - assign _zz_263 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_264 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_265 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_266 = ((_zz_205 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_267 = ((_zz_205 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_268 = ((_zz_205 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_269 = ((_zz_205 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_270 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_271 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_272 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_273 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_274 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_275 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); - assign _zz_276 = (! dataCache_1_io_cpu_execute_refilling); - assign _zz_277 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_278 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); - assign _zz_279 = MmuPlugin_shared_portSortedOh[0]; - assign _zz_280 = MmuPlugin_shared_portSortedOh[1]; - assign _zz_281 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_282 = (1'b0 || (! 1'b1)); - assign _zz_283 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_284 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_285 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_286 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_287 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_288 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_289 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_290 = execute_INSTRUCTION[13 : 12]; - assign _zz_291 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_292 = (! memory_arbitration_isStuck); - assign _zz_293 = (iBus_cmd_valid || (_zz_191 != 3'b000)); - assign _zz_294 = (_zz_234 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_295 = (MmuPlugin_shared_refills != 2'b00); - assign _zz_296 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); - assign _zz_297 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); - assign _zz_298 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); - assign _zz_299 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); - assign _zz_300 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); - assign _zz_301 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); - assign _zz_302 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); - assign _zz_303 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); - assign _zz_304 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); - assign _zz_305 = ((_zz_150 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); - assign _zz_306 = ((_zz_151 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); - assign _zz_307 = ((_zz_152 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); - assign _zz_308 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_309 = ((_zz_150 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); - assign _zz_310 = ((_zz_151 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); - assign _zz_311 = ((_zz_152 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); - assign _zz_312 = ((_zz_153 && 1'b1) && (! 1'b0)); - assign _zz_313 = ((_zz_154 && 1'b1) && (! 1'b0)); - assign _zz_314 = ((_zz_155 && 1'b1) && (! 1'b0)); - assign _zz_315 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_316 = execute_INSTRUCTION[13]; - assign _zz_317 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_318 = ($signed(_zz_319) + $signed(_zz_324)); - assign _zz_319 = ($signed(_zz_320) + $signed(_zz_322)); - assign _zz_320 = 52'h0; - assign _zz_321 = {1'b0,memory_MUL_LL}; - assign _zz_322 = {{19{_zz_321[32]}}, _zz_321}; - assign _zz_323 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_324 = {{2{_zz_323[49]}}, _zz_323}; - assign _zz_325 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_326 = {{2{_zz_325[49]}}, _zz_325}; - assign _zz_327 = ($signed(_zz_329) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_328 = _zz_327[31 : 0]; - assign _zz_329 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_330 = _zz_103[34 : 34]; - assign _zz_331 = _zz_103[33 : 33]; - assign _zz_332 = _zz_103[32 : 32]; - assign _zz_333 = _zz_103[31 : 31]; - assign _zz_334 = _zz_103[28 : 28]; - assign _zz_335 = _zz_103[21 : 21]; - assign _zz_336 = _zz_103[20 : 20]; - assign _zz_337 = _zz_103[19 : 19]; - assign _zz_338 = _zz_103[13 : 13]; - assign _zz_339 = _zz_103[12 : 12]; - assign _zz_340 = _zz_103[11 : 11]; - assign _zz_341 = _zz_103[17 : 17]; - assign _zz_342 = _zz_103[5 : 5]; - assign _zz_343 = _zz_103[3 : 3]; - assign _zz_344 = _zz_103[18 : 18]; - assign _zz_345 = _zz_103[10 : 10]; - assign _zz_346 = _zz_103[16 : 16]; - assign _zz_347 = _zz_103[15 : 15]; - assign _zz_348 = _zz_103[4 : 4]; - assign _zz_349 = _zz_103[0 : 0]; - assign _zz_350 = (_zz_56 - 5'h01); - assign _zz_351 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_352 = {29'd0, _zz_351}; - assign _zz_353 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_354 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_355 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_356 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_357 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_358 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_359 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_360 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_361 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_362 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_363 = MmuPlugin_ports_0_entryToReplace_willIncrement; - assign _zz_364 = {1'd0, _zz_363}; - assign _zz_365 = MmuPlugin_ports_1_entryToReplace_willIncrement; - assign _zz_366 = {1'd0, _zz_365}; - assign _zz_367 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; - assign _zz_368 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; - assign _zz_369 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; - assign _zz_370 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; - assign _zz_371 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; - assign _zz_372 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; - assign _zz_373 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; - assign _zz_374 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; - assign _zz_375 = (_zz_99 - 2'b01); - assign _zz_376 = execute_SRC_LESS; - assign _zz_377 = 3'b100; - assign _zz_378 = execute_INSTRUCTION[19 : 15]; - assign _zz_379 = execute_INSTRUCTION[31 : 20]; - assign _zz_380 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_381 = ($signed(_zz_382) + $signed(_zz_385)); - assign _zz_382 = ($signed(_zz_383) + $signed(_zz_384)); - assign _zz_383 = execute_SRC1; - assign _zz_384 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_385 = (execute_SRC_USE_SUB_LESS ? _zz_386 : _zz_387); - assign _zz_386 = 32'h00000001; - assign _zz_387 = 32'h0; - assign _zz_388 = execute_INSTRUCTION[31 : 20]; - assign _zz_389 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_390 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_391 = {_zz_137,execute_INSTRUCTION[31 : 20]}; - assign _zz_392 = {{_zz_139,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_393 = {{_zz_141,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_394 = execute_INSTRUCTION[31 : 20]; - assign _zz_395 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_396 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_397 = 3'b100; - assign _zz_398 = (_zz_156 & (~ _zz_399)); - assign _zz_399 = (_zz_156 - 2'b01); - assign _zz_400 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_401 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_402 = writeBack_MUL_LOW[31 : 0]; - assign _zz_403 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_404 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_405 = {5'd0, _zz_404}; - assign _zz_406 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_407 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_408 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_409 = {_zz_158,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_410 = _zz_411; - assign _zz_411 = _zz_412; - assign _zz_412 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_159) : _zz_159)} + _zz_414); - assign _zz_413 = memory_DivPlugin_div_needRevert; - assign _zz_414 = {32'd0, _zz_413}; - assign _zz_415 = _zz_161; - assign _zz_416 = {32'd0, _zz_415}; - assign _zz_417 = _zz_160; - assign _zz_418 = {31'd0, _zz_417}; - assign _zz_419 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_420 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_421 = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_422 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_423 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_424 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_425 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_426 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_427 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_428 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_265 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_266 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_267 = 1'b1; + assign _zz_268 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_270 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_271 = ((_zz_210 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_272 = ((_zz_210 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_273 = ((_zz_210 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_274 = ((_zz_210 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_275 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_276 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_277 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_278 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_279 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_280 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign _zz_281 = (! dataCache_1_io_cpu_execute_refilling); + assign _zz_282 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_283 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign _zz_284 = MmuPlugin_shared_portSortedOh[0]; + assign _zz_285 = MmuPlugin_shared_portSortedOh[1]; + assign _zz_286 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_287 = (1'b0 || (! 1'b1)); + assign _zz_288 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_289 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_290 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_291 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_292 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_293 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_294 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_295 = execute_INSTRUCTION[13 : 12]; + assign _zz_296 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_297 = (! memory_arbitration_isStuck); + assign _zz_298 = (iBus_cmd_valid || (_zz_196 != 3'b000)); + assign _zz_299 = (_zz_239 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_300 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_301 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign _zz_302 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign _zz_303 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign _zz_304 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign _zz_305 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign _zz_306 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign _zz_307 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign _zz_308 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign _zz_309 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign _zz_310 = ((_zz_155 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign _zz_311 = ((_zz_156 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign _zz_312 = ((_zz_157 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign _zz_313 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_314 = ((_zz_155 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign _zz_315 = ((_zz_156 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign _zz_316 = ((_zz_157 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign _zz_317 = ((_zz_158 && 1'b1) && (! 1'b0)); + assign _zz_318 = ((_zz_159 && 1'b1) && (! 1'b0)); + assign _zz_319 = ((_zz_160 && 1'b1) && (! 1'b0)); + assign _zz_320 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_321 = execute_INSTRUCTION[13]; + assign _zz_322 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_323 = ($signed(_zz_324) + $signed(_zz_329)); + assign _zz_324 = ($signed(_zz_325) + $signed(_zz_327)); + assign _zz_325 = 52'h0; + assign _zz_326 = {1'b0,memory_MUL_LL}; + assign _zz_327 = {{19{_zz_326[32]}}, _zz_326}; + assign _zz_328 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_329 = {{2{_zz_328[49]}}, _zz_328}; + assign _zz_330 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_331 = {{2{_zz_330[49]}}, _zz_330}; + assign _zz_332 = ($signed(_zz_334) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_333 = _zz_332[31 : 0]; + assign _zz_334 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_335 = _zz_103[34 : 34]; + assign _zz_336 = _zz_103[33 : 33]; + assign _zz_337 = _zz_103[32 : 32]; + assign _zz_338 = _zz_103[31 : 31]; + assign _zz_339 = _zz_103[28 : 28]; + assign _zz_340 = _zz_103[21 : 21]; + assign _zz_341 = _zz_103[20 : 20]; + assign _zz_342 = _zz_103[19 : 19]; + assign _zz_343 = _zz_103[13 : 13]; + assign _zz_344 = _zz_103[12 : 12]; + assign _zz_345 = _zz_103[11 : 11]; + assign _zz_346 = _zz_103[17 : 17]; + assign _zz_347 = _zz_103[5 : 5]; + assign _zz_348 = _zz_103[3 : 3]; + assign _zz_349 = _zz_103[18 : 18]; + assign _zz_350 = _zz_103[10 : 10]; + assign _zz_351 = _zz_103[16 : 16]; + assign _zz_352 = _zz_103[15 : 15]; + assign _zz_353 = _zz_103[4 : 4]; + assign _zz_354 = _zz_103[0 : 0]; + assign _zz_355 = (_zz_56 - 5'h01); + assign _zz_356 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_357 = {29'd0, _zz_356}; + assign _zz_358 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_359 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_360 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_361 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_362 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_363 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_364 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_365 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_366 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_367 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_368 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_369 = {1'd0, _zz_368}; + assign _zz_370 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_371 = {1'd0, _zz_370}; + assign _zz_372 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; + assign _zz_373 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; + assign _zz_374 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; + assign _zz_375 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; + assign _zz_376 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; + assign _zz_377 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; + assign _zz_378 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; + assign _zz_379 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; + assign _zz_380 = (_zz_99 - 2'b01); + assign _zz_381 = execute_SRC_LESS; + assign _zz_382 = 3'b100; + assign _zz_383 = execute_INSTRUCTION[19 : 15]; + assign _zz_384 = execute_INSTRUCTION[31 : 20]; + assign _zz_385 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_386 = ($signed(_zz_387) + $signed(_zz_390)); + assign _zz_387 = ($signed(_zz_388) + $signed(_zz_389)); + assign _zz_388 = execute_SRC1; + assign _zz_389 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_390 = (execute_SRC_USE_SUB_LESS ? _zz_391 : _zz_392); + assign _zz_391 = 32'h00000001; + assign _zz_392 = 32'h0; + assign _zz_393 = execute_INSTRUCTION[31 : 20]; + assign _zz_394 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_395 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_396 = {_zz_142,execute_INSTRUCTION[31 : 20]}; + assign _zz_397 = {{_zz_144,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_398 = {{_zz_146,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_399 = execute_INSTRUCTION[31 : 20]; + assign _zz_400 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_401 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_402 = 3'b100; + assign _zz_403 = (_zz_161 & (~ _zz_404)); + assign _zz_404 = (_zz_161 - 2'b01); + assign _zz_405 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_406 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_407 = writeBack_MUL_LOW[31 : 0]; + assign _zz_408 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_409 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_410 = {5'd0, _zz_409}; + assign _zz_411 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_412 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_413 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_414 = {_zz_163,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_415 = _zz_416; + assign _zz_416 = _zz_417; + assign _zz_417 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_164) : _zz_164)} + _zz_419); + assign _zz_418 = memory_DivPlugin_div_needRevert; + assign _zz_419 = {32'd0, _zz_418}; + assign _zz_420 = _zz_166; + assign _zz_421 = {32'd0, _zz_420}; + assign _zz_422 = _zz_165; + assign _zz_423 = {31'd0, _zz_422}; + assign _zz_424 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_425 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_426 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_427 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_428 = execute_CsrPlugin_writeData[3 : 3]; assign _zz_429 = execute_CsrPlugin_writeData[5 : 5]; assign _zz_430 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_431 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_432 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_433 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_434 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_435 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_436 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_437 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_438 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_439 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_440 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_441 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_442 = execute_CsrPlugin_writeData[0 : 0]; - assign _zz_443 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_444 = execute_CsrPlugin_writeData[2 : 2]; - assign _zz_445 = execute_CsrPlugin_writeData[4 : 4]; - assign _zz_446 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_447 = execute_CsrPlugin_writeData[6 : 6]; - assign _zz_448 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_449 = execute_CsrPlugin_writeData[8 : 8]; - assign _zz_450 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_451 = execute_CsrPlugin_writeData[12 : 12]; - assign _zz_452 = execute_CsrPlugin_writeData[13 : 13]; - assign _zz_453 = execute_CsrPlugin_writeData[15 : 15]; - assign _zz_454 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_455 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_456 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_457 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_458 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_431 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_432 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_433 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_434 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_435 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_436 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_437 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_438 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_439 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_440 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_441 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_442 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_443 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_444 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_445 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_446 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_447 = execute_CsrPlugin_writeData[0 : 0]; + assign _zz_448 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_449 = execute_CsrPlugin_writeData[2 : 2]; + assign _zz_450 = execute_CsrPlugin_writeData[4 : 4]; + assign _zz_451 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_452 = execute_CsrPlugin_writeData[6 : 6]; + assign _zz_453 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_454 = execute_CsrPlugin_writeData[8 : 8]; + assign _zz_455 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_456 = execute_CsrPlugin_writeData[12 : 12]; + assign _zz_457 = execute_CsrPlugin_writeData[13 : 13]; + assign _zz_458 = execute_CsrPlugin_writeData[15 : 15]; assign _zz_459 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_460 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_461 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_462 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_463 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_464 = (iBus_cmd_payload_address >>> 5); - assign _zz_465 = 1'b1; - assign _zz_466 = 1'b1; - assign _zz_467 = {_zz_59,{_zz_61,_zz_60}}; - assign _zz_468 = 32'h0000107f; - assign _zz_469 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_470 = 32'h00002073; - assign _zz_471 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_472 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_473 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_474) == 32'h00000003),{(_zz_475 == _zz_476),{_zz_477,{_zz_478,_zz_479}}}}}}; - assign _zz_474 = 32'h0000505f; - assign _zz_475 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_476 = 32'h00000063; - assign _zz_477 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_478 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); - assign _zz_479 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_480) == 32'h0000500f),{(_zz_481 == _zz_482),{_zz_483,{_zz_484,_zz_485}}}}}}; - assign _zz_480 = 32'h01f0707f; - assign _zz_481 = (decode_INSTRUCTION & 32'hbc00707f); - assign _zz_482 = 32'h00005013; - assign _zz_483 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); - assign _zz_484 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_485 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_486) == 32'h12000073),{(_zz_487 == _zz_488),{_zz_489,_zz_490}}}}}; - assign _zz_486 = 32'hfe007fff; - assign _zz_487 = (decode_INSTRUCTION & 32'hdfffffff); - assign _zz_488 = 32'h10200073; - assign _zz_489 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_490 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); - assign _zz_491 = decode_INSTRUCTION[31]; - assign _zz_492 = decode_INSTRUCTION[31]; - assign _zz_493 = decode_INSTRUCTION[7]; - assign _zz_494 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_495 = 32'h02004020; - assign _zz_496 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_497 = ((decode_INSTRUCTION & 32'h02203050) == 32'h00000050); - assign _zz_498 = 1'b0; - assign _zz_499 = (((decode_INSTRUCTION & _zz_502) == 32'h00000050) != 1'b0); - assign _zz_500 = ({_zz_503,_zz_504} != 2'b00); - assign _zz_501 = {({_zz_505,_zz_506} != 2'b00),{(_zz_507 != _zz_508),{_zz_509,{_zz_510,_zz_511}}}}; - assign _zz_502 = 32'h02403050; - assign _zz_503 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_504 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_505 = _zz_105; - assign _zz_506 = ((decode_INSTRUCTION & _zz_512) == 32'h00000004); - assign _zz_507 = ((decode_INSTRUCTION & _zz_513) == 32'h00000040); - assign _zz_508 = 1'b0; - assign _zz_509 = ({_zz_514,_zz_515} != 2'b00); - assign _zz_510 = ({_zz_516,_zz_517} != 3'b000); - assign _zz_511 = {(_zz_518 != _zz_519),{_zz_520,{_zz_521,_zz_522}}}; - assign _zz_512 = 32'h0000001c; - assign _zz_513 = 32'h00000058; - assign _zz_514 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_515 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_516 = ((decode_INSTRUCTION & _zz_523) == 32'h40001010); - assign _zz_517 = {(_zz_524 == _zz_525),(_zz_526 == _zz_527)}; - assign _zz_518 = ((decode_INSTRUCTION & _zz_528) == 32'h00001000); - assign _zz_519 = 1'b0; - assign _zz_520 = ((_zz_529 == _zz_530) != 1'b0); - assign _zz_521 = ({_zz_531,_zz_532} != 2'b00); - assign _zz_522 = {(_zz_533 != _zz_534),{_zz_535,{_zz_536,_zz_537}}}; - assign _zz_523 = 32'h40003054; - assign _zz_524 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_525 = 32'h00001010; - assign _zz_526 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_527 = 32'h00001010; - assign _zz_528 = 32'h00001000; - assign _zz_529 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_530 = 32'h00002000; - assign _zz_531 = ((decode_INSTRUCTION & _zz_538) == 32'h00002000); - assign _zz_532 = ((decode_INSTRUCTION & _zz_539) == 32'h00001000); - assign _zz_533 = ((decode_INSTRUCTION & _zz_540) == 32'h02000050); - assign _zz_534 = 1'b0; - assign _zz_535 = ((_zz_541 == _zz_542) != 1'b0); - assign _zz_536 = (_zz_543 != 1'b0); - assign _zz_537 = {(_zz_544 != _zz_545),{_zz_546,{_zz_547,_zz_548}}}; - assign _zz_538 = 32'h00002010; - assign _zz_539 = 32'h00005000; - assign _zz_540 = 32'h02003050; - assign _zz_541 = (decode_INSTRUCTION & 32'h00004048); - assign _zz_542 = 32'h00004008; - assign _zz_543 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_544 = {(_zz_549 == _zz_550),{_zz_551,{_zz_552,_zz_553}}}; - assign _zz_545 = 4'b0000; - assign _zz_546 = ((_zz_554 == _zz_555) != 1'b0); - assign _zz_547 = (_zz_556 != 1'b0); - assign _zz_548 = {(_zz_557 != _zz_558),{_zz_559,{_zz_560,_zz_561}}}; - assign _zz_549 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_550 = 32'h00000020; - assign _zz_551 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_552 = ((decode_INSTRUCTION & _zz_562) == 32'h08000020); - assign _zz_553 = ((decode_INSTRUCTION & _zz_563) == 32'h00000020); - assign _zz_554 = (decode_INSTRUCTION & 32'h10000008); - assign _zz_555 = 32'h00000008; - assign _zz_556 = ((decode_INSTRUCTION & 32'h10000008) == 32'h10000008); - assign _zz_557 = {(_zz_564 == _zz_565),{_zz_566,{_zz_567,_zz_568}}}; - assign _zz_558 = 6'h0; - assign _zz_559 = ({_zz_569,{_zz_570,_zz_571}} != 3'b000); - assign _zz_560 = ({_zz_572,_zz_573} != 5'h0); - assign _zz_561 = {(_zz_574 != _zz_575),{_zz_576,{_zz_577,_zz_578}}}; - assign _zz_562 = 32'h08000070; - assign _zz_563 = 32'h10000070; - assign _zz_564 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_565 = 32'h00002040; - assign _zz_566 = ((decode_INSTRUCTION & _zz_579) == 32'h00001040); - assign _zz_567 = (_zz_580 == _zz_581); - assign _zz_568 = {_zz_582,{_zz_583,_zz_584}}; - assign _zz_569 = ((decode_INSTRUCTION & _zz_585) == 32'h08000020); - assign _zz_570 = (_zz_586 == _zz_587); - assign _zz_571 = (_zz_588 == _zz_589); - assign _zz_572 = (_zz_590 == _zz_591); - assign _zz_573 = {_zz_592,{_zz_593,_zz_594}}; - assign _zz_574 = {_zz_108,{_zz_595,_zz_596}}; - assign _zz_575 = 5'h0; - assign _zz_576 = ({_zz_597,_zz_598} != 7'h0); - assign _zz_577 = (_zz_599 != _zz_600); - assign _zz_578 = {_zz_601,{_zz_602,_zz_603}}; - assign _zz_579 = 32'h00001040; - assign _zz_580 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_581 = 32'h00000040; - assign _zz_582 = ((decode_INSTRUCTION & _zz_604) == 32'h00000040); - assign _zz_583 = (_zz_605 == _zz_606); - assign _zz_584 = (_zz_607 == _zz_608); - assign _zz_585 = 32'h08000020; - assign _zz_586 = (decode_INSTRUCTION & 32'h10000020); - assign _zz_587 = 32'h00000020; - assign _zz_588 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_589 = 32'h00000020; - assign _zz_590 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_591 = 32'h00000040; - assign _zz_592 = ((decode_INSTRUCTION & _zz_609) == 32'h00004020); - assign _zz_593 = (_zz_610 == _zz_611); - assign _zz_594 = {_zz_108,_zz_612}; - assign _zz_595 = (_zz_613 == _zz_614); - assign _zz_596 = {_zz_615,{_zz_616,_zz_617}}; - assign _zz_597 = _zz_105; - assign _zz_598 = {_zz_618,{_zz_619,_zz_620}}; - assign _zz_599 = {_zz_107,_zz_621}; - assign _zz_600 = 2'b00; - assign _zz_601 = ({_zz_622,_zz_623} != 2'b00); - assign _zz_602 = (_zz_624 != _zz_625); - assign _zz_603 = {_zz_626,{_zz_627,_zz_628}}; - assign _zz_604 = 32'h02400040; - assign _zz_605 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_606 = 32'h0; - assign _zz_607 = (decode_INSTRUCTION & 32'h18002008); - assign _zz_608 = 32'h10002008; - assign _zz_609 = 32'h00004020; - assign _zz_610 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_611 = 32'h00000010; - assign _zz_612 = ((decode_INSTRUCTION & _zz_629) == 32'h00000020); - assign _zz_613 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_614 = 32'h00002010; - assign _zz_615 = ((decode_INSTRUCTION & _zz_630) == 32'h00000010); - assign _zz_616 = (_zz_631 == _zz_632); - assign _zz_617 = (_zz_633 == _zz_634); - assign _zz_618 = ((decode_INSTRUCTION & _zz_635) == 32'h00001010); - assign _zz_619 = (_zz_636 == _zz_637); - assign _zz_620 = {_zz_638,{_zz_639,_zz_640}}; - assign _zz_621 = ((decode_INSTRUCTION & _zz_641) == 32'h00000020); - assign _zz_622 = _zz_107; - assign _zz_623 = (_zz_642 == _zz_643); - assign _zz_624 = (_zz_644 == _zz_645); - assign _zz_625 = 1'b0; - assign _zz_626 = (_zz_646 != 1'b0); - assign _zz_627 = (_zz_647 != _zz_648); - assign _zz_628 = {_zz_649,{_zz_650,_zz_651}}; - assign _zz_629 = 32'h02000028; - assign _zz_630 = 32'h00001030; - assign _zz_631 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_632 = 32'h00000020; - assign _zz_633 = (decode_INSTRUCTION & 32'h02002068); - assign _zz_634 = 32'h00002020; - assign _zz_635 = 32'h00001010; - assign _zz_636 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_637 = 32'h00002010; - assign _zz_638 = ((decode_INSTRUCTION & _zz_652) == 32'h00002008); - assign _zz_639 = (_zz_653 == _zz_654); - assign _zz_640 = {_zz_108,_zz_655}; - assign _zz_641 = 32'h00000070; - assign _zz_642 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_643 = 32'h0; - assign _zz_644 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_645 = 32'h00004010; - assign _zz_646 = ((decode_INSTRUCTION & _zz_656) == 32'h00002010); - assign _zz_647 = {_zz_657,{_zz_658,_zz_659}}; - assign _zz_648 = 5'h0; - assign _zz_649 = ({_zz_660,_zz_661} != 2'b00); - assign _zz_650 = (_zz_662 != _zz_663); - assign _zz_651 = {_zz_664,{_zz_665,_zz_666}}; - assign _zz_652 = 32'h00002008; - assign _zz_653 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_654 = 32'h00000010; - assign _zz_655 = ((decode_INSTRUCTION & _zz_667) == 32'h0); - assign _zz_656 = 32'h00006014; - assign _zz_657 = ((decode_INSTRUCTION & _zz_668) == 32'h0); - assign _zz_658 = (_zz_669 == _zz_670); - assign _zz_659 = {_zz_671,{_zz_672,_zz_673}}; - assign _zz_660 = _zz_106; - assign _zz_661 = (_zz_674 == _zz_675); - assign _zz_662 = {_zz_676,{_zz_677,_zz_678}}; - assign _zz_663 = 3'b000; - assign _zz_664 = ({_zz_679,_zz_680} != 3'b000); - assign _zz_665 = (_zz_681 != _zz_682); - assign _zz_666 = (_zz_683 != _zz_684); - assign _zz_667 = 32'h00000028; - assign _zz_668 = 32'h00000044; - assign _zz_669 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_670 = 32'h0; - assign _zz_671 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_672 = ((decode_INSTRUCTION & _zz_685) == 32'h00001000); - assign _zz_673 = _zz_106; - assign _zz_674 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_460 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_461 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_462 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_463 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_464 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_465 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_466 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_467 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_468 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_469 = (iBus_cmd_payload_address >>> 5); + assign _zz_470 = 1'b1; + assign _zz_471 = 1'b1; + assign _zz_472 = {_zz_59,{_zz_61,_zz_60}}; + assign _zz_473 = 32'h0000107f; + assign _zz_474 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_475 = 32'h00002073; + assign _zz_476 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_477 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_478 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_479) == 32'h00000003),{(_zz_480 == _zz_481),{_zz_482,{_zz_483,_zz_484}}}}}}; + assign _zz_479 = 32'h0000505f; + assign _zz_480 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_481 = 32'h00000063; + assign _zz_482 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_483 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_484 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_485) == 32'h0000500f),{(_zz_486 == _zz_487),{_zz_488,{_zz_489,_zz_490}}}}}}; + assign _zz_485 = 32'h01f0707f; + assign _zz_486 = (decode_INSTRUCTION & 32'hbc00707f); + assign _zz_487 = 32'h00005013; + assign _zz_488 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); + assign _zz_489 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_490 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_491) == 32'h12000073),{(_zz_492 == _zz_493),{_zz_494,_zz_495}}}}}; + assign _zz_491 = 32'hfe007fff; + assign _zz_492 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_493 = 32'h10200073; + assign _zz_494 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_495 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_496 = decode_INSTRUCTION[31]; + assign _zz_497 = decode_INSTRUCTION[31]; + assign _zz_498 = decode_INSTRUCTION[7]; + assign _zz_499 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_500 = 32'h02004020; + assign _zz_501 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_502 = ((decode_INSTRUCTION & 32'h02203050) == 32'h00000050); + assign _zz_503 = 1'b0; + assign _zz_504 = (((decode_INSTRUCTION & _zz_507) == 32'h00000050) != 1'b0); + assign _zz_505 = ({_zz_508,_zz_509} != 2'b00); + assign _zz_506 = {({_zz_510,_zz_511} != 2'b00),{(_zz_512 != _zz_513),{_zz_514,{_zz_515,_zz_516}}}}; + assign _zz_507 = 32'h02403050; + assign _zz_508 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_509 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_510 = _zz_105; + assign _zz_511 = ((decode_INSTRUCTION & _zz_517) == 32'h00000004); + assign _zz_512 = ((decode_INSTRUCTION & _zz_518) == 32'h00000040); + assign _zz_513 = 1'b0; + assign _zz_514 = ({_zz_519,_zz_520} != 2'b00); + assign _zz_515 = ({_zz_521,_zz_522} != 3'b000); + assign _zz_516 = {(_zz_523 != _zz_524),{_zz_525,{_zz_526,_zz_527}}}; + assign _zz_517 = 32'h0000001c; + assign _zz_518 = 32'h00000058; + assign _zz_519 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_520 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_521 = ((decode_INSTRUCTION & _zz_528) == 32'h40001010); + assign _zz_522 = {(_zz_529 == _zz_530),(_zz_531 == _zz_532)}; + assign _zz_523 = ((decode_INSTRUCTION & _zz_533) == 32'h00001000); + assign _zz_524 = 1'b0; + assign _zz_525 = ((_zz_534 == _zz_535) != 1'b0); + assign _zz_526 = ({_zz_536,_zz_537} != 2'b00); + assign _zz_527 = {(_zz_538 != _zz_539),{_zz_540,{_zz_541,_zz_542}}}; + assign _zz_528 = 32'h40003054; + assign _zz_529 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_530 = 32'h00001010; + assign _zz_531 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_532 = 32'h00001010; + assign _zz_533 = 32'h00001000; + assign _zz_534 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_535 = 32'h00002000; + assign _zz_536 = ((decode_INSTRUCTION & _zz_543) == 32'h00002000); + assign _zz_537 = ((decode_INSTRUCTION & _zz_544) == 32'h00001000); + assign _zz_538 = ((decode_INSTRUCTION & _zz_545) == 32'h02000050); + assign _zz_539 = 1'b0; + assign _zz_540 = ((_zz_546 == _zz_547) != 1'b0); + assign _zz_541 = (_zz_548 != 1'b0); + assign _zz_542 = {(_zz_549 != _zz_550),{_zz_551,{_zz_552,_zz_553}}}; + assign _zz_543 = 32'h00002010; + assign _zz_544 = 32'h00005000; + assign _zz_545 = 32'h02003050; + assign _zz_546 = (decode_INSTRUCTION & 32'h00004048); + assign _zz_547 = 32'h00004008; + assign _zz_548 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_549 = {(_zz_554 == _zz_555),{_zz_556,{_zz_557,_zz_558}}}; + assign _zz_550 = 4'b0000; + assign _zz_551 = ((_zz_559 == _zz_560) != 1'b0); + assign _zz_552 = (_zz_561 != 1'b0); + assign _zz_553 = {(_zz_562 != _zz_563),{_zz_564,{_zz_565,_zz_566}}}; + assign _zz_554 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_555 = 32'h00000020; + assign _zz_556 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_557 = ((decode_INSTRUCTION & _zz_567) == 32'h08000020); + assign _zz_558 = ((decode_INSTRUCTION & _zz_568) == 32'h00000020); + assign _zz_559 = (decode_INSTRUCTION & 32'h10000008); + assign _zz_560 = 32'h00000008; + assign _zz_561 = ((decode_INSTRUCTION & 32'h10000008) == 32'h10000008); + assign _zz_562 = {(_zz_569 == _zz_570),{_zz_571,{_zz_572,_zz_573}}}; + assign _zz_563 = 6'h0; + assign _zz_564 = ({_zz_574,{_zz_575,_zz_576}} != 3'b000); + assign _zz_565 = ({_zz_577,_zz_578} != 5'h0); + assign _zz_566 = {(_zz_579 != _zz_580),{_zz_581,{_zz_582,_zz_583}}}; + assign _zz_567 = 32'h08000070; + assign _zz_568 = 32'h10000070; + assign _zz_569 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_570 = 32'h00002040; + assign _zz_571 = ((decode_INSTRUCTION & _zz_584) == 32'h00001040); + assign _zz_572 = (_zz_585 == _zz_586); + assign _zz_573 = {_zz_587,{_zz_588,_zz_589}}; + assign _zz_574 = ((decode_INSTRUCTION & _zz_590) == 32'h08000020); + assign _zz_575 = (_zz_591 == _zz_592); + assign _zz_576 = (_zz_593 == _zz_594); + assign _zz_577 = (_zz_595 == _zz_596); + assign _zz_578 = {_zz_597,{_zz_598,_zz_599}}; + assign _zz_579 = {_zz_108,{_zz_600,_zz_601}}; + assign _zz_580 = 5'h0; + assign _zz_581 = ({_zz_602,_zz_603} != 7'h0); + assign _zz_582 = (_zz_604 != _zz_605); + assign _zz_583 = {_zz_606,{_zz_607,_zz_608}}; + assign _zz_584 = 32'h00001040; + assign _zz_585 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_586 = 32'h00000040; + assign _zz_587 = ((decode_INSTRUCTION & _zz_609) == 32'h00000040); + assign _zz_588 = (_zz_610 == _zz_611); + assign _zz_589 = (_zz_612 == _zz_613); + assign _zz_590 = 32'h08000020; + assign _zz_591 = (decode_INSTRUCTION & 32'h10000020); + assign _zz_592 = 32'h00000020; + assign _zz_593 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_594 = 32'h00000020; + assign _zz_595 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_596 = 32'h00000040; + assign _zz_597 = ((decode_INSTRUCTION & _zz_614) == 32'h00004020); + assign _zz_598 = (_zz_615 == _zz_616); + assign _zz_599 = {_zz_108,_zz_617}; + assign _zz_600 = (_zz_618 == _zz_619); + assign _zz_601 = {_zz_620,{_zz_621,_zz_622}}; + assign _zz_602 = _zz_105; + assign _zz_603 = {_zz_623,{_zz_624,_zz_625}}; + assign _zz_604 = {_zz_107,_zz_626}; + assign _zz_605 = 2'b00; + assign _zz_606 = ({_zz_627,_zz_628} != 2'b00); + assign _zz_607 = (_zz_629 != _zz_630); + assign _zz_608 = {_zz_631,{_zz_632,_zz_633}}; + assign _zz_609 = 32'h02400040; + assign _zz_610 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_611 = 32'h0; + assign _zz_612 = (decode_INSTRUCTION & 32'h18002008); + assign _zz_613 = 32'h10002008; + assign _zz_614 = 32'h00004020; + assign _zz_615 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_616 = 32'h00000010; + assign _zz_617 = ((decode_INSTRUCTION & _zz_634) == 32'h00000020); + assign _zz_618 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_619 = 32'h00002010; + assign _zz_620 = ((decode_INSTRUCTION & _zz_635) == 32'h00000010); + assign _zz_621 = (_zz_636 == _zz_637); + assign _zz_622 = (_zz_638 == _zz_639); + assign _zz_623 = ((decode_INSTRUCTION & _zz_640) == 32'h00001010); + assign _zz_624 = (_zz_641 == _zz_642); + assign _zz_625 = {_zz_643,{_zz_644,_zz_645}}; + assign _zz_626 = ((decode_INSTRUCTION & _zz_646) == 32'h00000020); + assign _zz_627 = _zz_107; + assign _zz_628 = (_zz_647 == _zz_648); + assign _zz_629 = (_zz_649 == _zz_650); + assign _zz_630 = 1'b0; + assign _zz_631 = (_zz_651 != 1'b0); + assign _zz_632 = (_zz_652 != _zz_653); + assign _zz_633 = {_zz_654,{_zz_655,_zz_656}}; + assign _zz_634 = 32'h02000028; + assign _zz_635 = 32'h00001030; + assign _zz_636 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_637 = 32'h00000020; + assign _zz_638 = (decode_INSTRUCTION & 32'h02002068); + assign _zz_639 = 32'h00002020; + assign _zz_640 = 32'h00001010; + assign _zz_641 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_642 = 32'h00002010; + assign _zz_643 = ((decode_INSTRUCTION & _zz_657) == 32'h00002008); + assign _zz_644 = (_zz_658 == _zz_659); + assign _zz_645 = {_zz_108,_zz_660}; + assign _zz_646 = 32'h00000070; + assign _zz_647 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_648 = 32'h0; + assign _zz_649 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_650 = 32'h00004010; + assign _zz_651 = ((decode_INSTRUCTION & _zz_661) == 32'h00002010); + assign _zz_652 = {_zz_662,{_zz_663,_zz_664}}; + assign _zz_653 = 5'h0; + assign _zz_654 = ({_zz_665,_zz_666} != 2'b00); + assign _zz_655 = (_zz_667 != _zz_668); + assign _zz_656 = {_zz_669,{_zz_670,_zz_671}}; + assign _zz_657 = 32'h00002008; + assign _zz_658 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_659 = 32'h00000010; + assign _zz_660 = ((decode_INSTRUCTION & _zz_672) == 32'h0); + assign _zz_661 = 32'h00006014; + assign _zz_662 = ((decode_INSTRUCTION & _zz_673) == 32'h0); + assign _zz_663 = (_zz_674 == _zz_675); + assign _zz_664 = {_zz_676,{_zz_677,_zz_678}}; + assign _zz_665 = _zz_106; + assign _zz_666 = (_zz_679 == _zz_680); + assign _zz_667 = {_zz_681,{_zz_682,_zz_683}}; + assign _zz_668 = 3'b000; + assign _zz_669 = ({_zz_684,_zz_685} != 3'b000); + assign _zz_670 = (_zz_686 != _zz_687); + assign _zz_671 = (_zz_688 != _zz_689); + assign _zz_672 = 32'h00000028; + assign _zz_673 = 32'h00000044; + assign _zz_674 = (decode_INSTRUCTION & 32'h00000018); assign _zz_675 = 32'h0; - assign _zz_676 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_677 = ((decode_INSTRUCTION & _zz_686) == 32'h00002010); - assign _zz_678 = ((decode_INSTRUCTION & _zz_687) == 32'h40000030); - assign _zz_679 = _zz_105; - assign _zz_680 = {_zz_104,(_zz_688 == _zz_689)}; - assign _zz_681 = {_zz_104,(_zz_690 == _zz_691)}; - assign _zz_682 = 2'b00; - assign _zz_683 = ((decode_INSTRUCTION & _zz_692) == 32'h00001008); - assign _zz_684 = 1'b0; - assign _zz_685 = 32'h00005004; - assign _zz_686 = 32'h00002014; - assign _zz_687 = 32'h40000034; - assign _zz_688 = (decode_INSTRUCTION & 32'h00002014); - assign _zz_689 = 32'h00000004; - assign _zz_690 = (decode_INSTRUCTION & 32'h0000004c); - assign _zz_691 = 32'h00000004; - assign _zz_692 = 32'h00005048; - assign _zz_693 = execute_INSTRUCTION[31]; - assign _zz_694 = execute_INSTRUCTION[31]; - assign _zz_695 = execute_INSTRUCTION[7]; - assign _zz_696 = 32'h0; + assign _zz_676 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_677 = ((decode_INSTRUCTION & _zz_690) == 32'h00001000); + assign _zz_678 = _zz_106; + assign _zz_679 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_680 = 32'h0; + assign _zz_681 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_682 = ((decode_INSTRUCTION & _zz_691) == 32'h00002010); + assign _zz_683 = ((decode_INSTRUCTION & _zz_692) == 32'h40000030); + assign _zz_684 = _zz_105; + assign _zz_685 = {_zz_104,(_zz_693 == _zz_694)}; + assign _zz_686 = {_zz_104,(_zz_695 == _zz_696)}; + assign _zz_687 = 2'b00; + assign _zz_688 = ((decode_INSTRUCTION & _zz_697) == 32'h00001008); + assign _zz_689 = 1'b0; + assign _zz_690 = 32'h00005004; + assign _zz_691 = 32'h00002014; + assign _zz_692 = 32'h40000034; + assign _zz_693 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_694 = 32'h00000004; + assign _zz_695 = (decode_INSTRUCTION & 32'h0000004c); + assign _zz_696 = 32'h00000004; + assign _zz_697 = 32'h00005048; + assign _zz_698 = execute_INSTRUCTION[31]; + assign _zz_699 = execute_INSTRUCTION[31]; + assign _zz_700 = execute_INSTRUCTION[7]; + assign _zz_701 = 32'h0; always @ (posedge clk) begin - if(_zz_465) begin - _zz_235 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_470) begin + _zz_240 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_466) begin - _zz_236 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_471) begin + _zz_241 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -2167,13 +2162,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_200 ), //i - .io_cpu_prefetch_isValid (_zz_201 ), //i + .io_flush (_zz_205 ), //i + .io_cpu_prefetch_isValid (_zz_206 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_202 ), //i - .io_cpu_fetch_isStuck (_zz_203 ), //i - .io_cpu_fetch_isRemoved (_zz_204 ), //i + .io_cpu_fetch_isValid (_zz_207 ), //i + .io_cpu_fetch_isStuck (_zz_208 ), //i + .io_cpu_fetch_isRemoved (_zz_209 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -2194,8 +2189,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_205 ), //i - .io_cpu_decode_isStuck (_zz_206 ), //i + .io_cpu_decode_isValid (_zz_210 ), //i + .io_cpu_decode_isStuck (_zz_211 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -2203,8 +2198,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_207 ), //i - .io_cpu_fill_valid (_zz_208 ), //i + .io_cpu_decode_isUser (_zz_212 ), //i + .io_cpu_fill_valid (_zz_213 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -2217,24 +2212,24 @@ module VexRiscv ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_209 ), //i - .io_cpu_execute_address (_zz_210[31:0] ), //i + .io_cpu_execute_isValid (_zz_214 ), //i + .io_cpu_execute_address (_zz_215[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (_zz_211 ), //i - .io_cpu_execute_args_data (_zz_212[31:0] ), //i - .io_cpu_execute_args_size (_zz_213[1:0] ), //i - .io_cpu_execute_args_isLrsc (_zz_214 ), //i - .io_cpu_execute_args_isAmo (_zz_215 ), //i - .io_cpu_execute_args_amoCtrl_swap (_zz_216 ), //i - .io_cpu_execute_args_amoCtrl_alu (_zz_217[2:0] ), //i + .io_cpu_execute_args_wr (_zz_216 ), //i + .io_cpu_execute_args_data (_zz_217[31:0] ), //i + .io_cpu_execute_args_size (_zz_218[1:0] ), //i + .io_cpu_execute_args_isLrsc (_zz_219 ), //i + .io_cpu_execute_args_isAmo (_zz_220 ), //i + .io_cpu_execute_args_amoCtrl_swap (_zz_221 ), //i + .io_cpu_execute_args_amoCtrl_alu (_zz_222[2:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_218 ), //i + .io_cpu_memory_isValid (_zz_223 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_219[31:0] ), //i + .io_cpu_memory_address (_zz_224[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_220 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_225 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -2250,31 +2245,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i - .io_cpu_writeBack_isValid (_zz_221 ), //i + .io_cpu_writeBack_isValid (_zz_226 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_222 ), //i + .io_cpu_writeBack_isUser (_zz_227 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_223[31:0] ), //i + .io_cpu_writeBack_address (_zz_228[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_224 ), //i - .io_cpu_writeBack_fence_SR (_zz_225 ), //i - .io_cpu_writeBack_fence_SO (_zz_226 ), //i - .io_cpu_writeBack_fence_SI (_zz_227 ), //i - .io_cpu_writeBack_fence_PW (_zz_228 ), //i - .io_cpu_writeBack_fence_PR (_zz_229 ), //i - .io_cpu_writeBack_fence_PO (_zz_230 ), //i - .io_cpu_writeBack_fence_PI (_zz_231 ), //i - .io_cpu_writeBack_fence_FM (_zz_232[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_229 ), //i + .io_cpu_writeBack_fence_SR (_zz_230 ), //i + .io_cpu_writeBack_fence_SO (_zz_231 ), //i + .io_cpu_writeBack_fence_SI (_zz_232 ), //i + .io_cpu_writeBack_fence_PW (_zz_233 ), //i + .io_cpu_writeBack_fence_PR (_zz_234 ), //i + .io_cpu_writeBack_fence_PO (_zz_235 ), //i + .io_cpu_writeBack_fence_PI (_zz_236 ), //i + .io_cpu_writeBack_fence_FM (_zz_237[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_233 ), //i + .io_cpu_flush_valid (_zz_238 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_234 ), //i + .io_mem_cmd_ready (_zz_239 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -2290,21 +2285,21 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_467) + case(_zz_472) 3'b000 : begin - _zz_237 = DBusCachedPlugin_redoBranch_payload; + _zz_242 = DBusCachedPlugin_redoBranch_payload; end 3'b001 : begin - _zz_237 = CsrPlugin_jumpInterface_payload; + _zz_242 = CsrPlugin_jumpInterface_payload; end 3'b010 : begin - _zz_237 = BranchPlugin_jumpInterface_payload; + _zz_242 = BranchPlugin_jumpInterface_payload; end 3'b011 : begin - _zz_237 = CsrPlugin_redoInterface_payload; + _zz_242 = CsrPlugin_redoInterface_payload; end default : begin - _zz_237 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_242 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2312,56 +2307,56 @@ module VexRiscv ( always @(*) begin case(_zz_92) 2'b00 : begin - _zz_238 = MmuPlugin_ports_0_cache_0_valid; - _zz_239 = MmuPlugin_ports_0_cache_0_exception; - _zz_240 = MmuPlugin_ports_0_cache_0_superPage; - _zz_241 = MmuPlugin_ports_0_cache_0_virtualAddress_0; - _zz_242 = MmuPlugin_ports_0_cache_0_virtualAddress_1; - _zz_243 = MmuPlugin_ports_0_cache_0_physicalAddress_0; - _zz_244 = MmuPlugin_ports_0_cache_0_physicalAddress_1; - _zz_245 = MmuPlugin_ports_0_cache_0_allowRead; - _zz_246 = MmuPlugin_ports_0_cache_0_allowWrite; - _zz_247 = MmuPlugin_ports_0_cache_0_allowExecute; - _zz_248 = MmuPlugin_ports_0_cache_0_allowUser; + _zz_243 = MmuPlugin_ports_0_cache_0_valid; + _zz_244 = MmuPlugin_ports_0_cache_0_exception; + _zz_245 = MmuPlugin_ports_0_cache_0_superPage; + _zz_246 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_247 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_248 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_249 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_250 = MmuPlugin_ports_0_cache_0_allowRead; + _zz_251 = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_252 = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_253 = MmuPlugin_ports_0_cache_0_allowUser; end 2'b01 : begin - _zz_238 = MmuPlugin_ports_0_cache_1_valid; - _zz_239 = MmuPlugin_ports_0_cache_1_exception; - _zz_240 = MmuPlugin_ports_0_cache_1_superPage; - _zz_241 = MmuPlugin_ports_0_cache_1_virtualAddress_0; - _zz_242 = MmuPlugin_ports_0_cache_1_virtualAddress_1; - _zz_243 = MmuPlugin_ports_0_cache_1_physicalAddress_0; - _zz_244 = MmuPlugin_ports_0_cache_1_physicalAddress_1; - _zz_245 = MmuPlugin_ports_0_cache_1_allowRead; - _zz_246 = MmuPlugin_ports_0_cache_1_allowWrite; - _zz_247 = MmuPlugin_ports_0_cache_1_allowExecute; - _zz_248 = MmuPlugin_ports_0_cache_1_allowUser; + _zz_243 = MmuPlugin_ports_0_cache_1_valid; + _zz_244 = MmuPlugin_ports_0_cache_1_exception; + _zz_245 = MmuPlugin_ports_0_cache_1_superPage; + _zz_246 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_247 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_248 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_249 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_250 = MmuPlugin_ports_0_cache_1_allowRead; + _zz_251 = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_252 = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_253 = MmuPlugin_ports_0_cache_1_allowUser; end 2'b10 : begin - _zz_238 = MmuPlugin_ports_0_cache_2_valid; - _zz_239 = MmuPlugin_ports_0_cache_2_exception; - _zz_240 = MmuPlugin_ports_0_cache_2_superPage; - _zz_241 = MmuPlugin_ports_0_cache_2_virtualAddress_0; - _zz_242 = MmuPlugin_ports_0_cache_2_virtualAddress_1; - _zz_243 = MmuPlugin_ports_0_cache_2_physicalAddress_0; - _zz_244 = MmuPlugin_ports_0_cache_2_physicalAddress_1; - _zz_245 = MmuPlugin_ports_0_cache_2_allowRead; - _zz_246 = MmuPlugin_ports_0_cache_2_allowWrite; - _zz_247 = MmuPlugin_ports_0_cache_2_allowExecute; - _zz_248 = MmuPlugin_ports_0_cache_2_allowUser; + _zz_243 = MmuPlugin_ports_0_cache_2_valid; + _zz_244 = MmuPlugin_ports_0_cache_2_exception; + _zz_245 = MmuPlugin_ports_0_cache_2_superPage; + _zz_246 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_247 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_248 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_249 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_250 = MmuPlugin_ports_0_cache_2_allowRead; + _zz_251 = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_252 = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_253 = MmuPlugin_ports_0_cache_2_allowUser; end default : begin - _zz_238 = MmuPlugin_ports_0_cache_3_valid; - _zz_239 = MmuPlugin_ports_0_cache_3_exception; - _zz_240 = MmuPlugin_ports_0_cache_3_superPage; - _zz_241 = MmuPlugin_ports_0_cache_3_virtualAddress_0; - _zz_242 = MmuPlugin_ports_0_cache_3_virtualAddress_1; - _zz_243 = MmuPlugin_ports_0_cache_3_physicalAddress_0; - _zz_244 = MmuPlugin_ports_0_cache_3_physicalAddress_1; - _zz_245 = MmuPlugin_ports_0_cache_3_allowRead; - _zz_246 = MmuPlugin_ports_0_cache_3_allowWrite; - _zz_247 = MmuPlugin_ports_0_cache_3_allowExecute; - _zz_248 = MmuPlugin_ports_0_cache_3_allowUser; + _zz_243 = MmuPlugin_ports_0_cache_3_valid; + _zz_244 = MmuPlugin_ports_0_cache_3_exception; + _zz_245 = MmuPlugin_ports_0_cache_3_superPage; + _zz_246 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_247 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_248 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_249 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_250 = MmuPlugin_ports_0_cache_3_allowRead; + _zz_251 = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_252 = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_253 = MmuPlugin_ports_0_cache_3_allowUser; end endcase end @@ -2369,56 +2364,56 @@ module VexRiscv ( always @(*) begin case(_zz_96) 2'b00 : begin - _zz_249 = MmuPlugin_ports_1_cache_0_valid; - _zz_250 = MmuPlugin_ports_1_cache_0_exception; - _zz_251 = MmuPlugin_ports_1_cache_0_superPage; - _zz_252 = MmuPlugin_ports_1_cache_0_virtualAddress_0; - _zz_253 = MmuPlugin_ports_1_cache_0_virtualAddress_1; - _zz_254 = MmuPlugin_ports_1_cache_0_physicalAddress_0; - _zz_255 = MmuPlugin_ports_1_cache_0_physicalAddress_1; - _zz_256 = MmuPlugin_ports_1_cache_0_allowRead; - _zz_257 = MmuPlugin_ports_1_cache_0_allowWrite; - _zz_258 = MmuPlugin_ports_1_cache_0_allowExecute; - _zz_259 = MmuPlugin_ports_1_cache_0_allowUser; + _zz_254 = MmuPlugin_ports_1_cache_0_valid; + _zz_255 = MmuPlugin_ports_1_cache_0_exception; + _zz_256 = MmuPlugin_ports_1_cache_0_superPage; + _zz_257 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_258 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_259 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_260 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_261 = MmuPlugin_ports_1_cache_0_allowRead; + _zz_262 = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_263 = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_264 = MmuPlugin_ports_1_cache_0_allowUser; end 2'b01 : begin - _zz_249 = MmuPlugin_ports_1_cache_1_valid; - _zz_250 = MmuPlugin_ports_1_cache_1_exception; - _zz_251 = MmuPlugin_ports_1_cache_1_superPage; - _zz_252 = MmuPlugin_ports_1_cache_1_virtualAddress_0; - _zz_253 = MmuPlugin_ports_1_cache_1_virtualAddress_1; - _zz_254 = MmuPlugin_ports_1_cache_1_physicalAddress_0; - _zz_255 = MmuPlugin_ports_1_cache_1_physicalAddress_1; - _zz_256 = MmuPlugin_ports_1_cache_1_allowRead; - _zz_257 = MmuPlugin_ports_1_cache_1_allowWrite; - _zz_258 = MmuPlugin_ports_1_cache_1_allowExecute; - _zz_259 = MmuPlugin_ports_1_cache_1_allowUser; + _zz_254 = MmuPlugin_ports_1_cache_1_valid; + _zz_255 = MmuPlugin_ports_1_cache_1_exception; + _zz_256 = MmuPlugin_ports_1_cache_1_superPage; + _zz_257 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_258 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_259 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_260 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_261 = MmuPlugin_ports_1_cache_1_allowRead; + _zz_262 = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_263 = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_264 = MmuPlugin_ports_1_cache_1_allowUser; end 2'b10 : begin - _zz_249 = MmuPlugin_ports_1_cache_2_valid; - _zz_250 = MmuPlugin_ports_1_cache_2_exception; - _zz_251 = MmuPlugin_ports_1_cache_2_superPage; - _zz_252 = MmuPlugin_ports_1_cache_2_virtualAddress_0; - _zz_253 = MmuPlugin_ports_1_cache_2_virtualAddress_1; - _zz_254 = MmuPlugin_ports_1_cache_2_physicalAddress_0; - _zz_255 = MmuPlugin_ports_1_cache_2_physicalAddress_1; - _zz_256 = MmuPlugin_ports_1_cache_2_allowRead; - _zz_257 = MmuPlugin_ports_1_cache_2_allowWrite; - _zz_258 = MmuPlugin_ports_1_cache_2_allowExecute; - _zz_259 = MmuPlugin_ports_1_cache_2_allowUser; + _zz_254 = MmuPlugin_ports_1_cache_2_valid; + _zz_255 = MmuPlugin_ports_1_cache_2_exception; + _zz_256 = MmuPlugin_ports_1_cache_2_superPage; + _zz_257 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_258 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_259 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_260 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_261 = MmuPlugin_ports_1_cache_2_allowRead; + _zz_262 = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_263 = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_264 = MmuPlugin_ports_1_cache_2_allowUser; end default : begin - _zz_249 = MmuPlugin_ports_1_cache_3_valid; - _zz_250 = MmuPlugin_ports_1_cache_3_exception; - _zz_251 = MmuPlugin_ports_1_cache_3_superPage; - _zz_252 = MmuPlugin_ports_1_cache_3_virtualAddress_0; - _zz_253 = MmuPlugin_ports_1_cache_3_virtualAddress_1; - _zz_254 = MmuPlugin_ports_1_cache_3_physicalAddress_0; - _zz_255 = MmuPlugin_ports_1_cache_3_physicalAddress_1; - _zz_256 = MmuPlugin_ports_1_cache_3_allowRead; - _zz_257 = MmuPlugin_ports_1_cache_3_allowWrite; - _zz_258 = MmuPlugin_ports_1_cache_3_allowExecute; - _zz_259 = MmuPlugin_ports_1_cache_3_allowUser; + _zz_254 = MmuPlugin_ports_1_cache_3_valid; + _zz_255 = MmuPlugin_ports_1_cache_3_exception; + _zz_256 = MmuPlugin_ports_1_cache_3_superPage; + _zz_257 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_258 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_259 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_260 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_261 = MmuPlugin_ports_1_cache_3_allowRead; + _zz_262 = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_263 = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_264 = MmuPlugin_ports_1_cache_3_allowUser; end endcase end @@ -3120,7 +3115,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_318) + $signed(_zz_326)); + assign memory_MUL_LOW = ($signed(_zz_323) + $signed(_zz_331)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -3128,42 +3123,42 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_328; + assign execute_SHIFT_RIGHT = _zz_333; assign execute_REGFILE_WRITE_DATA = _zz_118; assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_210[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_215[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_330[0]; - assign decode_IS_RS1_SIGNED = _zz_331[0]; - assign decode_IS_DIV = _zz_332[0]; + assign decode_IS_RS2_SIGNED = _zz_335[0]; + assign decode_IS_RS1_SIGNED = _zz_336[0]; + assign decode_IS_DIV = _zz_337[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_333[0]; + assign decode_IS_MUL = _zz_338[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_334[0]; + assign decode_IS_CSR = _zz_339[0]; assign _zz_8 = _zz_9; assign _zz_10 = _zz_11; assign decode_SHIFT_CTRL = _zz_12; assign _zz_13 = _zz_14; assign decode_ALU_BITWISE_CTRL = _zz_15; assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_335[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_340[0]; assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; - assign decode_IS_SFENCE_VMA = _zz_336[0]; - assign decode_MEMORY_MANAGMENT = _zz_337[0]; + assign decode_IS_SFENCE_VMA = _zz_341[0]; + assign decode_MEMORY_MANAGMENT = _zz_342[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_338[0]; + assign decode_MEMORY_WR = _zz_343[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_339[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_340[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_344[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_345[0]; assign decode_SRC2_CTRL = _zz_18; assign _zz_19 = _zz_20; assign decode_ALU_CTRL = _zz_21; @@ -3197,13 +3192,13 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_135; + assign execute_BRANCH_COND_RESULT = _zz_140; assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_341[0]; - assign decode_RS1_USE = _zz_342[0]; + assign decode_RS2_USE = _zz_346[0]; + assign decode_RS1_USE = _zz_347[0]; always @ (*) begin _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_260)begin + if(_zz_265)begin _zz_31 = execute_CsrPlugin_readData; end if(DBusCachedPlugin_forceDatapath)begin @@ -3219,28 +3214,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_129)begin + if((_zz_130 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_131; end end - if(_zz_261)begin - if(_zz_262)begin - if(_zz_128)begin + if(_zz_266)begin + if(_zz_267)begin + if(_zz_133)begin decode_RS2 = _zz_50; end end end - if(_zz_263)begin + if(_zz_268)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_130)begin + if(_zz_135)begin decode_RS2 = _zz_32; end end end - if(_zz_264)begin + if(_zz_269)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_132)begin + if(_zz_137)begin decode_RS2 = _zz_31; end end @@ -3249,28 +3244,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_129)begin + if((_zz_130 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_131; end end - if(_zz_261)begin - if(_zz_262)begin - if(_zz_127)begin + if(_zz_266)begin + if(_zz_267)begin + if(_zz_132)begin decode_RS1 = _zz_50; end end end - if(_zz_263)begin + if(_zz_268)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_129)begin + if(_zz_134)begin decode_RS1 = _zz_32; end end end - if(_zz_264)begin + if(_zz_269)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_131)begin + if(_zz_136)begin decode_RS1 = _zz_31; end end @@ -3292,7 +3287,7 @@ module VexRiscv ( end endcase end - if(_zz_265)begin + if(_zz_270)begin _zz_32 = memory_DivPlugin_div_result; end end @@ -3305,8 +3300,8 @@ module VexRiscv ( assign _zz_35 = execute_PC; assign execute_SRC2_CTRL = _zz_36; assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_343[0]; - assign decode_SRC_ADD_ZERO = _zz_344[0]; + assign decode_SRC_USE_SUB_LESS = _zz_348[0]; + assign decode_SRC_ADD_ZERO = _zz_349[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_38; @@ -3324,13 +3319,13 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_345[0]; + decode_REGFILE_WRITE_VALID = _zz_350[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_468) == 32'h00001073),{(_zz_469 == _zz_470),{_zz_471,{_zz_472,_zz_473}}}}}}} != 25'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_473) == 32'h00001073),{(_zz_474 == _zz_475),{_zz_476,{_zz_477,_zz_478}}}}}}} != 25'h0); assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; @@ -3340,12 +3335,12 @@ module VexRiscv ( _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_317) + case(_zz_322) 2'b00 : begin - _zz_50 = _zz_402; + _zz_50 = _zz_407; end default : begin - _zz_50 = _zz_403; + _zz_50 = _zz_408; end endcase end @@ -3366,34 +3361,34 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_AMO = _zz_346[0]; - assign decode_MEMORY_LRSC = _zz_347[0]; - assign decode_MEMORY_ENABLE = _zz_348[0]; - assign decode_FLUSH_ALL = _zz_349[0]; + assign decode_MEMORY_AMO = _zz_351[0]; + assign decode_MEMORY_LRSC = _zz_352[0]; + assign decode_MEMORY_ENABLE = _zz_353[0]; + assign decode_FLUSH_ALL = _zz_354[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_266)begin + if(_zz_271)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_267)begin + if(_zz_272)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_268)begin + if(_zz_273)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_269)begin + if(_zz_274)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -3436,7 +3431,7 @@ module VexRiscv ( if(MmuPlugin_dBusAccess_cmd_valid)begin decode_arbitration_haltByOther = 1'b1; end - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_127 || _zz_128)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -3449,7 +3444,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_270)begin + if(_zz_275)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3463,22 +3458,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_270)begin + if(_zz_275)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_233 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_238 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_271)begin + if(_zz_276)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_260)begin + if(_zz_265)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3517,7 +3512,7 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_265)begin + if(_zz_270)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3579,10 +3574,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_272)begin + if(_zz_277)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_273)begin + if(_zz_278)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3596,10 +3591,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_272)begin + if(_zz_277)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_273)begin + if(_zz_278)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3613,7 +3608,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_271)begin + if(_zz_276)begin CsrPlugin_inWfi = 1'b1; end end @@ -3621,21 +3616,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_272)begin + if(_zz_277)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_273)begin + if(_zz_278)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_272)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_277)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_273)begin - case(_zz_274) + if(_zz_278)begin + case(_zz_279) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3654,12 +3649,12 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != 5'h0); assign _zz_56 = {IBusCachedPlugin_predictionJumpInterface_valid,{CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_57 = (_zz_56 & (~ _zz_350)); + assign _zz_57 = (_zz_56 & (~ _zz_355)); assign _zz_58 = _zz_57[3]; assign _zz_59 = _zz_57[4]; assign _zz_60 = (_zz_57[1] || _zz_58); assign _zz_61 = (_zz_57[2] || _zz_58); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_237; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_242; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3679,7 +3674,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_352); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_357); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3770,7 +3765,7 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_71 = _zz_353[11]; + assign _zz_71 = _zz_358[11]; always @ (*) begin _zz_72[18] = _zz_71; _zz_72[17] = _zz_71; @@ -3794,13 +3789,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_354[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_359[31])); if(_zz_77)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_73 = _zz_355[19]; + assign _zz_73 = _zz_360[19]; always @ (*) begin _zz_74[10] = _zz_73; _zz_74[9] = _zz_73; @@ -3815,7 +3810,7 @@ module VexRiscv ( _zz_74[0] = _zz_73; end - assign _zz_75 = _zz_356[11]; + assign _zz_75 = _zz_361[11]; always @ (*) begin _zz_76[18] = _zz_75; _zz_76[17] = _zz_75; @@ -3841,16 +3836,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_77 = _zz_357[1]; + _zz_77 = _zz_362[1]; end default : begin - _zz_77 = _zz_358[1]; + _zz_77 = _zz_363[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_78 = _zz_359[19]; + assign _zz_78 = _zz_364[19]; always @ (*) begin _zz_79[10] = _zz_78; _zz_79[9] = _zz_78; @@ -3865,7 +3860,7 @@ module VexRiscv ( _zz_79[0] = _zz_78; end - assign _zz_80 = _zz_360[11]; + assign _zz_80 = _zz_365[11]; always @ (*) begin _zz_81[18] = _zz_80; _zz_81[17] = _zz_80; @@ -3888,7 +3883,7 @@ module VexRiscv ( _zz_81[0] = _zz_80; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_79,{{{_zz_491,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_81,{{{_zz_492,_zz_493},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_79,{{{_zz_496,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_81,{{{_zz_497,_zz_498},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3897,52 +3892,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_201 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_202 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_203 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_202; + assign _zz_206 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_207 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_208 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_207; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_205 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_206 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_207 = (CsrPlugin_privilege == 2'b00); + assign _zz_210 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_211 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_212 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_269)begin + if(_zz_274)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_267)begin + if(_zz_272)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_208 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_267)begin - _zz_208 = 1'b1; + _zz_213 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_272)begin + _zz_213 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_268)begin + if(_zz_273)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_266)begin + if(_zz_271)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_268)begin + if(_zz_273)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_266)begin + if(_zz_271)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3952,9 +3947,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_200 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_205 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_234 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_239 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3994,30 +3989,30 @@ module VexRiscv ( assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin - _zz_209 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + _zz_214 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_275)begin - if(_zz_276)begin - _zz_209 = 1'b1; + if(_zz_280)begin + if(_zz_281)begin + _zz_214 = 1'b1; end end end end always @ (*) begin - _zz_210 = execute_SRC_ADD; + _zz_215 = execute_SRC_ADD; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_275)begin - _zz_210 = MmuPlugin_dBusAccess_cmd_payload_address; + if(_zz_280)begin + _zz_215 = MmuPlugin_dBusAccess_cmd_payload_address; end end end always @ (*) begin - _zz_211 = execute_MEMORY_WR; + _zz_216 = execute_MEMORY_WR; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_275)begin - _zz_211 = MmuPlugin_dBusAccess_cmd_payload_write; + if(_zz_280)begin + _zz_216 = MmuPlugin_dBusAccess_cmd_payload_write; end end end @@ -4037,58 +4032,58 @@ module VexRiscv ( end always @ (*) begin - _zz_212 = _zz_84; + _zz_217 = _zz_84; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_275)begin - _zz_212 = MmuPlugin_dBusAccess_cmd_payload_data; + if(_zz_280)begin + _zz_217 = MmuPlugin_dBusAccess_cmd_payload_data; end end end always @ (*) begin - _zz_213 = execute_DBusCachedPlugin_size; + _zz_218 = execute_DBusCachedPlugin_size; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_275)begin - _zz_213 = MmuPlugin_dBusAccess_cmd_payload_size; + if(_zz_280)begin + _zz_218 = MmuPlugin_dBusAccess_cmd_payload_size; end end end - assign _zz_233 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_238 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); always @ (*) begin - _zz_214 = 1'b0; + _zz_219 = 1'b0; if(execute_MEMORY_LRSC)begin - _zz_214 = 1'b1; + _zz_219 = 1'b1; end if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_275)begin - _zz_214 = 1'b0; + if(_zz_280)begin + _zz_219 = 1'b0; end end end always @ (*) begin - _zz_215 = execute_MEMORY_AMO; + _zz_220 = execute_MEMORY_AMO; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_275)begin - _zz_215 = 1'b0; + if(_zz_280)begin + _zz_220 = 1'b0; end end end - assign _zz_217 = execute_INSTRUCTION[31 : 29]; - assign _zz_216 = execute_INSTRUCTION[27]; + assign _zz_222 = execute_INSTRUCTION[31 : 29]; + assign _zz_221 = execute_INSTRUCTION[27]; always @ (*) begin - _zz_218 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + _zz_223 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); if(memory_IS_DBUS_SHARING)begin - _zz_218 = 1'b1; + _zz_223 = 1'b1; end end - assign _zz_219 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_218; + assign _zz_224 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_223; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_219; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_224; always @ (*) begin DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; if(memory_IS_DBUS_SHARING)begin @@ -4098,24 +4093,24 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_220 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_225 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_220 = 1'b1; + _zz_225 = 1'b1; end end always @ (*) begin - _zz_221 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + _zz_226 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); if(writeBack_IS_DBUS_SHARING)begin - _zz_221 = 1'b1; + _zz_226 = 1'b1; end end - assign _zz_222 = (CsrPlugin_privilege == 2'b00); - assign _zz_223 = writeBack_REGFILE_WRITE_DATA; + assign _zz_227 = (CsrPlugin_privilege == 2'b00); + assign _zz_228 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_277)begin + if(_zz_282)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -4125,7 +4120,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_277)begin + if(_zz_282)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -4144,15 +4139,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_277)begin + if(_zz_282)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_361}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_366}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_362}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_367}; end end end @@ -4225,7 +4220,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_315) + case(_zz_320) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_86; end @@ -4241,8 +4236,8 @@ module VexRiscv ( always @ (*) begin MmuPlugin_dBusAccess_cmd_ready = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_275)begin - if(_zz_276)begin + if(_zz_280)begin + if(_zz_281)begin MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); end end @@ -4252,7 +4247,7 @@ module VexRiscv ( always @ (*) begin DBusCachedPlugin_forceDatapath = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_275)begin + if(_zz_280)begin DBusCachedPlugin_forceDatapath = 1'b1; end end @@ -4285,21 +4280,21 @@ module VexRiscv ( assign _zz_90 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_89); assign _zz_91 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_89); assign _zz_92 = {_zz_91,_zz_90}; - assign MmuPlugin_ports_0_cacheLine_valid = _zz_238; - assign MmuPlugin_ports_0_cacheLine_exception = _zz_239; - assign MmuPlugin_ports_0_cacheLine_superPage = _zz_240; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_241; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_242; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_243; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_244; - assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_245; - assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_246; - assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_247; - assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_248; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_243; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_244; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_245; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_246; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_247; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_248; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_249; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_250; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_251; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_252; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_253; always @ (*) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; - if(_zz_278)begin - if(_zz_279)begin + if(_zz_283)begin + if(_zz_284)begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; end end @@ -4309,7 +4304,7 @@ module VexRiscv ( assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_364); + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_369); if(MmuPlugin_ports_0_entryToReplace_willClear)begin MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; end @@ -4406,21 +4401,21 @@ module VexRiscv ( assign _zz_94 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_93); assign _zz_95 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_93); assign _zz_96 = {_zz_95,_zz_94}; - assign MmuPlugin_ports_1_cacheLine_valid = _zz_249; - assign MmuPlugin_ports_1_cacheLine_exception = _zz_250; - assign MmuPlugin_ports_1_cacheLine_superPage = _zz_251; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_252; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_253; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_254; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_255; - assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_256; - assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_257; - assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_258; - assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_259; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_254; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_255; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_256; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_257; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_258; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_259; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_260; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_261; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_262; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_263; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_264; always @ (*) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; - if(_zz_278)begin - if(_zz_280)begin + if(_zz_283)begin + if(_zz_285)begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; end end @@ -4430,7 +4425,7 @@ module VexRiscv ( assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_366); + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_371); if(MmuPlugin_ports_1_entryToReplace_willClear)begin MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; end @@ -4502,14 +4497,14 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; - assign MmuPlugin_shared_dBusRsp_pte_V = _zz_367[0]; - assign MmuPlugin_shared_dBusRsp_pte_R = _zz_368[0]; - assign MmuPlugin_shared_dBusRsp_pte_W = _zz_369[0]; - assign MmuPlugin_shared_dBusRsp_pte_X = _zz_370[0]; - assign MmuPlugin_shared_dBusRsp_pte_U = _zz_371[0]; - assign MmuPlugin_shared_dBusRsp_pte_G = _zz_372[0]; - assign MmuPlugin_shared_dBusRsp_pte_A = _zz_373[0]; - assign MmuPlugin_shared_dBusRsp_pte_D = _zz_374[0]; + assign MmuPlugin_shared_dBusRsp_pte_V = _zz_372[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = _zz_373[0]; + assign MmuPlugin_shared_dBusRsp_pte_W = _zz_374[0]; + assign MmuPlugin_shared_dBusRsp_pte_X = _zz_375[0]; + assign MmuPlugin_shared_dBusRsp_pte_U = _zz_376[0]; + assign MmuPlugin_shared_dBusRsp_pte_G = _zz_377[0]; + assign MmuPlugin_shared_dBusRsp_pte_A = _zz_378[0]; + assign MmuPlugin_shared_dBusRsp_pte_D = _zz_379[0]; assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; @@ -4536,7 +4531,7 @@ module VexRiscv ( assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; always @ (*) begin - MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + MmuPlugin_dBusAccess_cmd_payload_address = 32'h0; case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin end @@ -4553,7 +4548,7 @@ module VexRiscv ( endcase end - assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'h0; assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; always @ (*) begin _zz_97[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); @@ -4566,7 +4561,7 @@ module VexRiscv ( _zz_99[1] = _zz_98[0]; end - assign _zz_100 = (_zz_99 & (~ _zz_375)); + assign _zz_100 = (_zz_99 & (~ _zz_380)); always @ (*) begin _zz_101[0] = _zz_100[1]; _zz_101[1] = _zz_100[0]; @@ -4582,7 +4577,7 @@ module VexRiscv ( assign _zz_107 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_108 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); assign _zz_109 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_103 = {(_zz_109 != 1'b0),{(_zz_109 != 1'b0),{((_zz_494 == _zz_495) != 1'b0),{(_zz_496 != 1'b0),{(_zz_497 != _zz_498),{_zz_499,{_zz_500,_zz_501}}}}}}}; + assign _zz_103 = {(_zz_109 != 1'b0),{(_zz_109 != 1'b0),{((_zz_499 == _zz_500) != 1'b0),{(_zz_501 != 1'b0),{(_zz_502 != _zz_503),{_zz_504,{_zz_505,_zz_506}}}}}}}; assign _zz_110 = _zz_103[2 : 1]; assign _zz_49 = _zz_110; assign _zz_111 = _zz_103[7 : 6]; @@ -4602,8 +4597,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_235; - assign decode_RegFilePlugin_rs2Data = _zz_236; + assign decode_RegFilePlugin_rs1Data = _zz_240; + assign decode_RegFilePlugin_rs2Data = _zz_241; always @ (*) begin lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); if(_zz_117)begin @@ -4645,7 +4640,7 @@ module VexRiscv ( _zz_118 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_118 = {31'd0, _zz_376}; + _zz_118 = {31'd0, _zz_381}; end default : begin _zz_118 = execute_SRC_ADD_SUB; @@ -4659,18 +4654,18 @@ module VexRiscv ( _zz_119 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_119 = {29'd0, _zz_377}; + _zz_119 = {29'd0, _zz_382}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_119 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_119 = {27'd0, _zz_378}; + _zz_119 = {27'd0, _zz_383}; end endcase end - assign _zz_120 = _zz_379[11]; + assign _zz_120 = _zz_384[11]; always @ (*) begin _zz_121[19] = _zz_120; _zz_121[18] = _zz_120; @@ -4694,7 +4689,7 @@ module VexRiscv ( _zz_121[0] = _zz_120; end - assign _zz_122 = _zz_380[11]; + assign _zz_122 = _zz_385[11]; always @ (*) begin _zz_123[19] = _zz_122; _zz_123[18] = _zz_122; @@ -4736,7 +4731,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_381; + execute_SrcPlugin_addSub = _zz_386; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -4816,180 +4811,175 @@ module VexRiscv ( end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_281)begin - if(_zz_282)begin - if(_zz_127)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_127 = 1'b0; + if(_zz_286)begin + if(_zz_287)begin + if(_zz_132)begin + _zz_127 = 1'b1; end end end - if(_zz_283)begin - if(_zz_284)begin - if(_zz_129)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_288)begin + if(_zz_289)begin + if(_zz_134)begin + _zz_127 = 1'b1; end end end - if(_zz_285)begin - if(_zz_286)begin - if(_zz_131)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_290)begin + if(_zz_291)begin + if(_zz_136)begin + _zz_127 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_127 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_281)begin - if(_zz_282)begin - if(_zz_128)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_128 = 1'b0; + if(_zz_286)begin + if(_zz_287)begin + if(_zz_133)begin + _zz_128 = 1'b1; end end end - if(_zz_283)begin - if(_zz_284)begin - if(_zz_130)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_288)begin + if(_zz_289)begin + if(_zz_135)begin + _zz_128 = 1'b1; end end end - if(_zz_285)begin - if(_zz_286)begin - if(_zz_132)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_290)begin + if(_zz_291)begin + if(_zz_137)begin + _zz_128 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_128 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_127 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_128 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_129 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_130 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_131 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_132 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_132 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_133 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_134 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_135 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_136 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_137 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_133 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_133 == 3'b000)) begin - _zz_134 = execute_BranchPlugin_eq; - end else if((_zz_133 == 3'b001)) begin - _zz_134 = (! execute_BranchPlugin_eq); - end else if((((_zz_133 & 3'b101) == 3'b101))) begin - _zz_134 = (! execute_SRC_LESS); + assign _zz_138 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_138 == 3'b000)) begin + _zz_139 = execute_BranchPlugin_eq; + end else if((_zz_138 == 3'b001)) begin + _zz_139 = (! execute_BranchPlugin_eq); + end else if((((_zz_138 & 3'b101) == 3'b101))) begin + _zz_139 = (! execute_SRC_LESS); end else begin - _zz_134 = execute_SRC_LESS; + _zz_139 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_135 = 1'b0; + _zz_140 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_135 = 1'b1; + _zz_140 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_135 = 1'b1; + _zz_140 = 1'b1; end default : begin - _zz_135 = _zz_134; + _zz_140 = _zz_139; end endcase end - assign _zz_136 = _zz_388[11]; - always @ (*) begin - _zz_137[19] = _zz_136; - _zz_137[18] = _zz_136; - _zz_137[17] = _zz_136; - _zz_137[16] = _zz_136; - _zz_137[15] = _zz_136; - _zz_137[14] = _zz_136; - _zz_137[13] = _zz_136; - _zz_137[12] = _zz_136; - _zz_137[11] = _zz_136; - _zz_137[10] = _zz_136; - _zz_137[9] = _zz_136; - _zz_137[8] = _zz_136; - _zz_137[7] = _zz_136; - _zz_137[6] = _zz_136; - _zz_137[5] = _zz_136; - _zz_137[4] = _zz_136; - _zz_137[3] = _zz_136; - _zz_137[2] = _zz_136; - _zz_137[1] = _zz_136; - _zz_137[0] = _zz_136; - end - - assign _zz_138 = _zz_389[19]; - always @ (*) begin - _zz_139[10] = _zz_138; - _zz_139[9] = _zz_138; - _zz_139[8] = _zz_138; - _zz_139[7] = _zz_138; - _zz_139[6] = _zz_138; - _zz_139[5] = _zz_138; - _zz_139[4] = _zz_138; - _zz_139[3] = _zz_138; - _zz_139[2] = _zz_138; - _zz_139[1] = _zz_138; - _zz_139[0] = _zz_138; - end - - assign _zz_140 = _zz_390[11]; - always @ (*) begin - _zz_141[18] = _zz_140; - _zz_141[17] = _zz_140; - _zz_141[16] = _zz_140; - _zz_141[15] = _zz_140; - _zz_141[14] = _zz_140; - _zz_141[13] = _zz_140; - _zz_141[12] = _zz_140; - _zz_141[11] = _zz_140; - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; + assign _zz_141 = _zz_393[11]; + always @ (*) begin + _zz_142[19] = _zz_141; + _zz_142[18] = _zz_141; + _zz_142[17] = _zz_141; + _zz_142[16] = _zz_141; + _zz_142[15] = _zz_141; + _zz_142[14] = _zz_141; + _zz_142[13] = _zz_141; + _zz_142[12] = _zz_141; + _zz_142[11] = _zz_141; + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; + end + + assign _zz_143 = _zz_394[19]; + always @ (*) begin + _zz_144[10] = _zz_143; + _zz_144[9] = _zz_143; + _zz_144[8] = _zz_143; + _zz_144[7] = _zz_143; + _zz_144[6] = _zz_143; + _zz_144[5] = _zz_143; + _zz_144[4] = _zz_143; + _zz_144[3] = _zz_143; + _zz_144[2] = _zz_143; + _zz_144[1] = _zz_143; + _zz_144[0] = _zz_143; + end + + assign _zz_145 = _zz_395[11]; + always @ (*) begin + _zz_146[18] = _zz_145; + _zz_146[17] = _zz_145; + _zz_146[16] = _zz_145; + _zz_146[15] = _zz_145; + _zz_146[14] = _zz_145; + _zz_146[13] = _zz_145; + _zz_146[12] = _zz_145; + _zz_146[11] = _zz_145; + _zz_146[10] = _zz_145; + _zz_146[9] = _zz_145; + _zz_146[8] = _zz_145; + _zz_146[7] = _zz_145; + _zz_146[6] = _zz_145; + _zz_146[5] = _zz_145; + _zz_146[4] = _zz_145; + _zz_146[3] = _zz_145; + _zz_146[2] = _zz_145; + _zz_146[1] = _zz_145; + _zz_146[0] = _zz_145; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_142 = (_zz_391[1] ^ execute_RS1[1]); + _zz_147 = (_zz_396[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_142 = _zz_392[1]; + _zz_147 = _zz_397[1]; end default : begin - _zz_142 = _zz_393[1]; + _zz_147 = _zz_398[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_142); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_147); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -5001,80 +4991,80 @@ module VexRiscv ( endcase end - assign _zz_143 = _zz_394[11]; + assign _zz_148 = _zz_399[11]; always @ (*) begin - _zz_144[19] = _zz_143; - _zz_144[18] = _zz_143; - _zz_144[17] = _zz_143; - _zz_144[16] = _zz_143; - _zz_144[15] = _zz_143; - _zz_144[14] = _zz_143; - _zz_144[13] = _zz_143; - _zz_144[12] = _zz_143; - _zz_144[11] = _zz_143; - _zz_144[10] = _zz_143; - _zz_144[9] = _zz_143; - _zz_144[8] = _zz_143; - _zz_144[7] = _zz_143; - _zz_144[6] = _zz_143; - _zz_144[5] = _zz_143; - _zz_144[4] = _zz_143; - _zz_144[3] = _zz_143; - _zz_144[2] = _zz_143; - _zz_144[1] = _zz_143; - _zz_144[0] = _zz_143; + _zz_149[19] = _zz_148; + _zz_149[18] = _zz_148; + _zz_149[17] = _zz_148; + _zz_149[16] = _zz_148; + _zz_149[15] = _zz_148; + _zz_149[14] = _zz_148; + _zz_149[13] = _zz_148; + _zz_149[12] = _zz_148; + _zz_149[11] = _zz_148; + _zz_149[10] = _zz_148; + _zz_149[9] = _zz_148; + _zz_149[8] = _zz_148; + _zz_149[7] = _zz_148; + _zz_149[6] = _zz_148; + _zz_149[5] = _zz_148; + _zz_149[4] = _zz_148; + _zz_149[3] = _zz_148; + _zz_149[2] = _zz_148; + _zz_149[1] = _zz_148; + _zz_149[0] = _zz_148; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_144,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_149,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_146,{{{_zz_693,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_148,{{{_zz_694,_zz_695},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_151,{{{_zz_698,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_153,{{{_zz_699,_zz_700},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_397}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_402}; end end endcase end - assign _zz_145 = _zz_395[19]; - always @ (*) begin - _zz_146[10] = _zz_145; - _zz_146[9] = _zz_145; - _zz_146[8] = _zz_145; - _zz_146[7] = _zz_145; - _zz_146[6] = _zz_145; - _zz_146[5] = _zz_145; - _zz_146[4] = _zz_145; - _zz_146[3] = _zz_145; - _zz_146[2] = _zz_145; - _zz_146[1] = _zz_145; - _zz_146[0] = _zz_145; - end - - assign _zz_147 = _zz_396[11]; - always @ (*) begin - _zz_148[18] = _zz_147; - _zz_148[17] = _zz_147; - _zz_148[16] = _zz_147; - _zz_148[15] = _zz_147; - _zz_148[14] = _zz_147; - _zz_148[13] = _zz_147; - _zz_148[12] = _zz_147; - _zz_148[11] = _zz_147; - _zz_148[10] = _zz_147; - _zz_148[9] = _zz_147; - _zz_148[8] = _zz_147; - _zz_148[7] = _zz_147; - _zz_148[6] = _zz_147; - _zz_148[5] = _zz_147; - _zz_148[4] = _zz_147; - _zz_148[3] = _zz_147; - _zz_148[2] = _zz_147; - _zz_148[1] = _zz_147; - _zz_148[0] = _zz_147; + assign _zz_150 = _zz_400[19]; + always @ (*) begin + _zz_151[10] = _zz_150; + _zz_151[9] = _zz_150; + _zz_151[8] = _zz_150; + _zz_151[7] = _zz_150; + _zz_151[6] = _zz_150; + _zz_151[5] = _zz_150; + _zz_151[4] = _zz_150; + _zz_151[3] = _zz_150; + _zz_151[2] = _zz_150; + _zz_151[1] = _zz_150; + _zz_151[0] = _zz_150; + end + + assign _zz_152 = _zz_401[11]; + always @ (*) begin + _zz_153[18] = _zz_152; + _zz_153[17] = _zz_152; + _zz_153[16] = _zz_152; + _zz_153[15] = _zz_152; + _zz_153[14] = _zz_152; + _zz_153[13] = _zz_152; + _zz_153[12] = _zz_152; + _zz_153[11] = _zz_152; + _zz_153[10] = _zz_152; + _zz_153[9] = _zz_152; + _zz_153[8] = _zz_152; + _zz_153[7] = _zz_152; + _zz_153[6] = _zz_152; + _zz_153[5] = _zz_152; + _zz_153[4] = _zz_152; + _zz_153[3] = _zz_152; + _zz_153[2] = _zz_152; + _zz_153[1] = _zz_152; + _zz_153[0] = _zz_152; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -5085,7 +5075,7 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = _zz_149; + CsrPlugin_privilege = _zz_154; if(CsrPlugin_forceMachineWire)begin CsrPlugin_privilege = 2'b11; end @@ -5104,12 +5094,12 @@ module VexRiscv ( end assign CsrPlugin_redoInterface_payload = decode_PC; - assign _zz_150 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); - assign _zz_151 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); - assign _zz_152 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); - assign _zz_153 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_154 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_155 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_155 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_156 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_157 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_158 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_159 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_160 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) @@ -5179,11 +5169,11 @@ module VexRiscv ( end assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_156 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_157 = _zz_398[0]; + assign _zz_161 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_162 = _zz_403[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_270)begin + if(_zz_275)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -5267,7 +5257,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_base = CsrPlugin_stvec_base; @@ -5392,7 +5382,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_287)begin + if(_zz_292)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -5411,20 +5401,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_288)begin + if(_zz_293)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_289)begin + if(_zz_294)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_288)begin + if(_zz_293)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_289)begin + if(_zz_294)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -5442,14 +5432,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_287)begin + if(_zz_292)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_287)begin + if(_zz_292)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -5467,7 +5457,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_316) + case(_zz_321) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -5481,7 +5471,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_290) + case(_zz_295) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -5495,7 +5485,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_290) + case(_zz_295) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -5514,12 +5504,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_400) + $signed(_zz_401)); + assign writeBack_MulPlugin_result = ($signed(_zz_405) + $signed(_zz_406)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_265)begin - if(_zz_291)begin + if(_zz_270)begin + if(_zz_296)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -5527,7 +5517,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_292)begin + if(_zz_297)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -5538,30 +5528,30 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_405); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_410); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_158 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_158[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_406); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_407 : _zz_408); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_409[31:0]; - assign _zz_159 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_160 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_161 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_163 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_163[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_411); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_412 : _zz_413); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_414[31:0]; + assign _zz_164 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_165 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_166 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_162[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_162[31 : 0] = execute_RS1; + _zz_167[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_167[31 : 0] = execute_RS1; end - assign _zz_164 = (_zz_163 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_164 != 32'h0); - assign _zz_166 = (_zz_165 & externalInterruptArray_regNext); - assign externalInterruptS = (_zz_166 != 32'h0); + assign _zz_169 = (_zz_168 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_169 != 32'h0); + assign _zz_171 = (_zz_170 & externalInterruptArray_regNext); + assign externalInterruptS = (_zz_171 != 32'h0); assign _zz_26 = decode_SRC1_CTRL; assign _zz_24 = _zz_49; assign _zz_37 = decode_to_execute_SRC1_CTRL; @@ -5610,246 +5600,246 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_167 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_167[12 : 0] = 13'h1000; - _zz_167[25 : 20] = 6'h20; + _zz_172[12 : 0] = 13'h1000; + _zz_172[25 : 20] = 6'h20; end end always @ (*) begin - _zz_168 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_168[19 : 19] = MmuPlugin_status_mxr; - _zz_168[18 : 18] = MmuPlugin_status_sum; - _zz_168[17 : 17] = MmuPlugin_status_mprv; - _zz_168[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_168[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_168[3 : 3] = CsrPlugin_mstatus_MIE; - _zz_168[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_168[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_168[1 : 1] = CsrPlugin_sstatus_SIE; + _zz_173[19 : 19] = MmuPlugin_status_mxr; + _zz_173[18 : 18] = MmuPlugin_status_sum; + _zz_173[17 : 17] = MmuPlugin_status_mprv; + _zz_173[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_173[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_173[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_173[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_173[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_173[1 : 1] = CsrPlugin_sstatus_SIE; end end always @ (*) begin - _zz_169 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_256)begin - _zz_169[19 : 19] = MmuPlugin_status_mxr; - _zz_169[18 : 18] = MmuPlugin_status_sum; - _zz_169[17 : 17] = MmuPlugin_status_mprv; - _zz_169[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_169[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_169[1 : 1] = CsrPlugin_sstatus_SIE; + _zz_174[19 : 19] = MmuPlugin_status_mxr; + _zz_174[18 : 18] = MmuPlugin_status_sum; + _zz_174[17 : 17] = MmuPlugin_status_mprv; + _zz_174[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_174[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_174[1 : 1] = CsrPlugin_sstatus_SIE; end end always @ (*) begin - _zz_170 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_384)begin - _zz_170[31 : 31] = MmuPlugin_satp_mode; - _zz_170[30 : 22] = MmuPlugin_satp_asid; - _zz_170[19 : 0] = MmuPlugin_satp_ppn; + _zz_175[31 : 31] = MmuPlugin_satp_mode; + _zz_175[30 : 22] = MmuPlugin_satp_asid; + _zz_175[19 : 0] = MmuPlugin_satp_ppn; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_171[0 : 0] = 1'b1; + _zz_176[0 : 0] = 1'b1; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_172[1 : 0] = 2'b10; + _zz_177[1 : 0] = 2'b10; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_173[1 : 0] = 2'b11; + _zz_178[1 : 0] = 2'b11; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_174[11 : 11] = CsrPlugin_mip_MEIP; - _zz_174[7 : 7] = CsrPlugin_mip_MTIP; - _zz_174[3 : 3] = CsrPlugin_mip_MSIP; - _zz_174[5 : 5] = CsrPlugin_sip_STIP; - _zz_174[1 : 1] = CsrPlugin_sip_SSIP; - _zz_174[9 : 9] = CsrPlugin_sip_SEIP_OR; + _zz_179[11 : 11] = CsrPlugin_mip_MEIP; + _zz_179[7 : 7] = CsrPlugin_mip_MTIP; + _zz_179[3 : 3] = CsrPlugin_mip_MSIP; + _zz_179[5 : 5] = CsrPlugin_sip_STIP; + _zz_179[1 : 1] = CsrPlugin_sip_SSIP; + _zz_179[9 : 9] = CsrPlugin_sip_SEIP_OR; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_175[11 : 11] = CsrPlugin_mie_MEIE; - _zz_175[7 : 7] = CsrPlugin_mie_MTIE; - _zz_175[3 : 3] = CsrPlugin_mie_MSIE; - _zz_175[9 : 9] = CsrPlugin_sie_SEIE; - _zz_175[5 : 5] = CsrPlugin_sie_STIE; - _zz_175[1 : 1] = CsrPlugin_sie_SSIE; + _zz_180[11 : 11] = CsrPlugin_mie_MEIE; + _zz_180[7 : 7] = CsrPlugin_mie_MTIE; + _zz_180[3 : 3] = CsrPlugin_mie_MSIE; + _zz_180[9 : 9] = CsrPlugin_sie_SEIE; + _zz_180[5 : 5] = CsrPlugin_sie_STIE; + _zz_180[1 : 1] = CsrPlugin_sie_SSIE; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_176[31 : 0] = CsrPlugin_mepc; + _zz_181[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_177[31 : 0] = CsrPlugin_mscratch; + _zz_182[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_178[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_178[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_183[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_183[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_179[31 : 0] = CsrPlugin_mtval; + _zz_184[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_324)begin - _zz_180[5 : 5] = CsrPlugin_sip_STIP; - _zz_180[1 : 1] = CsrPlugin_sip_SSIP; - _zz_180[9 : 9] = CsrPlugin_sip_SEIP_OR; + _zz_185[5 : 5] = CsrPlugin_sip_STIP; + _zz_185[1 : 1] = CsrPlugin_sip_SSIP; + _zz_185[9 : 9] = CsrPlugin_sip_SEIP_OR; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_260)begin - _zz_181[9 : 9] = CsrPlugin_sie_SEIE; - _zz_181[5 : 5] = CsrPlugin_sie_STIE; - _zz_181[1 : 1] = CsrPlugin_sie_SSIE; + _zz_186[9 : 9] = CsrPlugin_sie_SEIE; + _zz_186[5 : 5] = CsrPlugin_sie_STIE; + _zz_186[1 : 1] = CsrPlugin_sie_SSIE; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_261)begin - _zz_182[31 : 2] = CsrPlugin_stvec_base; - _zz_182[1 : 0] = CsrPlugin_stvec_mode; + _zz_187[31 : 2] = CsrPlugin_stvec_base; + _zz_187[1 : 0] = CsrPlugin_stvec_mode; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_321)begin - _zz_183[31 : 0] = CsrPlugin_sepc; + _zz_188[31 : 0] = CsrPlugin_sepc; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_320)begin - _zz_184[31 : 0] = CsrPlugin_sscratch; + _zz_189[31 : 0] = CsrPlugin_sscratch; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_322)begin - _zz_185[31 : 31] = CsrPlugin_scause_interrupt; - _zz_185[3 : 0] = CsrPlugin_scause_exceptionCode; + _zz_190[31 : 31] = CsrPlugin_scause_interrupt; + _zz_190[3 : 0] = CsrPlugin_scause_exceptionCode; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_323)begin - _zz_186[31 : 0] = CsrPlugin_stval; + _zz_191[31 : 0] = CsrPlugin_stval; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_187[31 : 0] = _zz_163; + _zz_192[31 : 0] = _zz_168; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_188[31 : 0] = _zz_164; + _zz_193[31 : 0] = _zz_169; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_2496)begin - _zz_189[31 : 0] = _zz_165; + _zz_194[31 : 0] = _zz_170; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_3520)begin - _zz_190[31 : 0] = _zz_166; + _zz_195[31 : 0] = _zz_171; end end - assign execute_CsrPlugin_readData = (((((_zz_167 | _zz_168) | (_zz_169 | _zz_170)) | ((_zz_171 | _zz_172) | (_zz_173 | _zz_696))) | (((_zz_174 | _zz_175) | (_zz_176 | _zz_177)) | ((_zz_178 | _zz_179) | (_zz_180 | _zz_181)))) | ((((_zz_182 | _zz_183) | (_zz_184 | _zz_185)) | ((_zz_186 | _zz_187) | (_zz_188 | _zz_189))) | _zz_190)); - assign iBusWishbone_ADR = {_zz_464,_zz_191}; - assign iBusWishbone_CTI = ((_zz_191 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_172 | _zz_173) | (_zz_174 | _zz_175)) | ((_zz_176 | _zz_177) | (_zz_178 | _zz_701))) | (((_zz_179 | _zz_180) | (_zz_181 | _zz_182)) | ((_zz_183 | _zz_184) | (_zz_185 | _zz_186)))) | ((((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194))) | _zz_195)); + assign iBusWishbone_ADR = {_zz_469,_zz_196}; + assign iBusWishbone_CTI = ((_zz_196 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_293)begin + if(_zz_298)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_293)begin + if(_zz_298)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_192; + assign iBus_rsp_valid = _zz_197; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_198 = (dBus_cmd_payload_length != 3'b000); - assign _zz_194 = dBus_cmd_valid; - assign _zz_196 = dBus_cmd_payload_wr; - assign _zz_197 = (_zz_193 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_195 && (_zz_196 || _zz_197)); - assign dBusWishbone_ADR = ((_zz_198 ? {{dBus_cmd_payload_address[31 : 5],_zz_193},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_198 ? (_zz_197 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_203 = (dBus_cmd_payload_length != 3'b000); + assign _zz_199 = dBus_cmd_valid; + assign _zz_201 = dBus_cmd_payload_wr; + assign _zz_202 = (_zz_198 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_200 && (_zz_201 || _zz_202)); + assign dBusWishbone_ADR = ((_zz_203 ? {{dBus_cmd_payload_address[31 : 5],_zz_198},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_203 ? (_zz_202 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_196 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_196; + assign dBusWishbone_SEL = (_zz_201 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_201; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_195 = (_zz_194 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_194; - assign dBusWishbone_STB = _zz_194; - assign dBus_rsp_valid = _zz_199; + assign _zz_200 = (_zz_199 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_199; + assign dBusWishbone_STB = _zz_199; + assign dBus_rsp_valid = _zz_204; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5888,8 +5878,8 @@ module VexRiscv ( MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; _zz_117 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; - _zz_149 <= 2'b11; + _zz_129 <= 1'b0; + _zz_154 <= 2'b11; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -5932,17 +5922,17 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_163 <= 32'h0; - _zz_165 <= 32'h0; + _zz_168 <= 32'h0; + _zz_170 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_IS_DBUS_SHARING <= 1'b0; memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; - _zz_191 <= 3'b000; - _zz_192 <= 1'b0; - _zz_193 <= 3'b000; - _zz_199 <= 1'b0; + _zz_196 <= 3'b000; + _zz_197 <= 1'b0; + _zz_198 <= 3'b000; + _zz_204 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -6023,7 +6013,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_294)begin + if(_zz_299)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -6065,7 +6055,7 @@ module VexRiscv ( MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_295)begin + if(_zz_300)begin MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; end end @@ -6099,32 +6089,32 @@ module VexRiscv ( end end endcase - if(_zz_278)begin - if(_zz_279)begin - if(_zz_296)begin + if(_zz_283)begin + if(_zz_284)begin + if(_zz_301)begin MmuPlugin_ports_0_cache_0_valid <= 1'b1; end - if(_zz_297)begin + if(_zz_302)begin MmuPlugin_ports_0_cache_1_valid <= 1'b1; end - if(_zz_298)begin + if(_zz_303)begin MmuPlugin_ports_0_cache_2_valid <= 1'b1; end - if(_zz_299)begin + if(_zz_304)begin MmuPlugin_ports_0_cache_3_valid <= 1'b1; end end - if(_zz_280)begin - if(_zz_300)begin + if(_zz_285)begin + if(_zz_305)begin MmuPlugin_ports_1_cache_0_valid <= 1'b1; end - if(_zz_301)begin + if(_zz_306)begin MmuPlugin_ports_1_cache_1_valid <= 1'b1; end - if(_zz_302)begin + if(_zz_307)begin MmuPlugin_ports_1_cache_2_valid <= 1'b1; end - if(_zz_303)begin + if(_zz_308)begin MmuPlugin_ports_1_cache_3_valid <= 1'b1; end end @@ -6140,7 +6130,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_valid <= 1'b0; end _zz_117 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_129 <= (_zz_41 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -6162,34 +6152,34 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_304)begin - if(_zz_305)begin + if(_zz_309)begin + if(_zz_310)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_306)begin + if(_zz_311)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_307)begin + if(_zz_312)begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(_zz_308)begin - if(_zz_309)begin + if(_zz_313)begin + if(_zz_314)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_310)begin + if(_zz_315)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_311)begin + if(_zz_316)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_312)begin + if(_zz_317)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_313)begin + if(_zz_318)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_314)begin + if(_zz_319)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -6214,8 +6204,8 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_272)begin - _zz_149 <= CsrPlugin_targetPrivilege; + if(_zz_277)begin + _zz_154 <= CsrPlugin_targetPrivilege; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_sstatus_SIE <= 1'b0; @@ -6231,25 +6221,25 @@ module VexRiscv ( end endcase end - if(_zz_273)begin - case(_zz_274) + if(_zz_278)begin + case(_zz_279) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; - _zz_149 <= CsrPlugin_mstatus_MPP; + _zz_154 <= CsrPlugin_mstatus_MPP; end 2'b01 : begin CsrPlugin_sstatus_SPP <= 1'b0; CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; CsrPlugin_sstatus_SPIE <= 1'b1; - _zz_149 <= {1'b0,CsrPlugin_sstatus_SPP}; + _zz_154 <= {1'b0,CsrPlugin_sstatus_SPP}; end default : begin end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_155,{_zz_154,{_zz_153,{_zz_152,{_zz_151,_zz_150}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_160,{_zz_159,{_zz_158,{_zz_157,{_zz_156,_zz_155}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if((! memory_arbitration_isStuck))begin execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; @@ -6280,25 +6270,25 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_419[0]; - MmuPlugin_status_sum <= _zz_420[0]; - MmuPlugin_status_mprv <= _zz_421[0]; + MmuPlugin_status_mxr <= _zz_424[0]; + MmuPlugin_status_sum <= _zz_425[0]; + MmuPlugin_status_mprv <= _zz_426[0]; CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_422[0]; - CsrPlugin_mstatus_MIE <= _zz_423[0]; + CsrPlugin_mstatus_MPIE <= _zz_427[0]; + CsrPlugin_mstatus_MIE <= _zz_428[0]; CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_424[0]; - CsrPlugin_sstatus_SIE <= _zz_425[0]; + CsrPlugin_sstatus_SPIE <= _zz_429[0]; + CsrPlugin_sstatus_SIE <= _zz_430[0]; end end if(execute_CsrPlugin_csr_256)begin if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_426[0]; - MmuPlugin_status_sum <= _zz_427[0]; - MmuPlugin_status_mprv <= _zz_428[0]; + MmuPlugin_status_mxr <= _zz_431[0]; + MmuPlugin_status_sum <= _zz_432[0]; + MmuPlugin_status_mprv <= _zz_433[0]; CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_429[0]; - CsrPlugin_sstatus_SIE <= _zz_430[0]; + CsrPlugin_sstatus_SPIE <= _zz_434[0]; + CsrPlugin_sstatus_SIE <= _zz_435[0]; end end if(execute_CsrPlugin_csr_384)begin @@ -6313,86 +6303,86 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_valid <= 1'b0; end if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_mode <= _zz_431[0]; + MmuPlugin_satp_mode <= _zz_436[0]; end end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_433[0]; - CsrPlugin_sip_SSIP <= _zz_434[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_435[0]; + CsrPlugin_sip_STIP <= _zz_438[0]; + CsrPlugin_sip_SSIP <= _zz_439[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_440[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_436[0]; - CsrPlugin_mie_MTIE <= _zz_437[0]; - CsrPlugin_mie_MSIE <= _zz_438[0]; - CsrPlugin_sie_SEIE <= _zz_439[0]; - CsrPlugin_sie_STIE <= _zz_440[0]; - CsrPlugin_sie_SSIE <= _zz_441[0]; + CsrPlugin_mie_MEIE <= _zz_441[0]; + CsrPlugin_mie_MTIE <= _zz_442[0]; + CsrPlugin_mie_MSIE <= _zz_443[0]; + CsrPlugin_sie_SEIE <= _zz_444[0]; + CsrPlugin_sie_STIE <= _zz_445[0]; + CsrPlugin_sie_SSIE <= _zz_446[0]; end end if(execute_CsrPlugin_csr_770)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_medeleg_IAM <= _zz_442[0]; - CsrPlugin_medeleg_IAF <= _zz_443[0]; - CsrPlugin_medeleg_II <= _zz_444[0]; - CsrPlugin_medeleg_LAM <= _zz_445[0]; - CsrPlugin_medeleg_LAF <= _zz_446[0]; - CsrPlugin_medeleg_SAM <= _zz_447[0]; - CsrPlugin_medeleg_SAF <= _zz_448[0]; - CsrPlugin_medeleg_EU <= _zz_449[0]; - CsrPlugin_medeleg_ES <= _zz_450[0]; - CsrPlugin_medeleg_IPF <= _zz_451[0]; - CsrPlugin_medeleg_LPF <= _zz_452[0]; - CsrPlugin_medeleg_SPF <= _zz_453[0]; + CsrPlugin_medeleg_IAM <= _zz_447[0]; + CsrPlugin_medeleg_IAF <= _zz_448[0]; + CsrPlugin_medeleg_II <= _zz_449[0]; + CsrPlugin_medeleg_LAM <= _zz_450[0]; + CsrPlugin_medeleg_LAF <= _zz_451[0]; + CsrPlugin_medeleg_SAM <= _zz_452[0]; + CsrPlugin_medeleg_SAF <= _zz_453[0]; + CsrPlugin_medeleg_EU <= _zz_454[0]; + CsrPlugin_medeleg_ES <= _zz_455[0]; + CsrPlugin_medeleg_IPF <= _zz_456[0]; + CsrPlugin_medeleg_LPF <= _zz_457[0]; + CsrPlugin_medeleg_SPF <= _zz_458[0]; end end if(execute_CsrPlugin_csr_771)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mideleg_SE <= _zz_454[0]; - CsrPlugin_mideleg_ST <= _zz_455[0]; - CsrPlugin_mideleg_SS <= _zz_456[0]; + CsrPlugin_mideleg_SE <= _zz_459[0]; + CsrPlugin_mideleg_ST <= _zz_460[0]; + CsrPlugin_mideleg_SS <= _zz_461[0]; end end if(execute_CsrPlugin_csr_324)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_457[0]; - CsrPlugin_sip_SSIP <= _zz_458[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_459[0]; + CsrPlugin_sip_STIP <= _zz_462[0]; + CsrPlugin_sip_SSIP <= _zz_463[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_464[0]; end end if(execute_CsrPlugin_csr_260)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sie_SEIE <= _zz_460[0]; - CsrPlugin_sie_STIE <= _zz_461[0]; - CsrPlugin_sie_SSIE <= _zz_462[0]; + CsrPlugin_sie_SEIE <= _zz_465[0]; + CsrPlugin_sie_STIE <= _zz_466[0]; + CsrPlugin_sie_SSIE <= _zz_467[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2496)begin if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_170 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_293)begin + if(_zz_298)begin if(iBusWishbone_ACK)begin - _zz_191 <= (_zz_191 + 3'b001); + _zz_196 <= (_zz_196 + 3'b001); end end - _zz_192 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_194 && _zz_195))begin - _zz_193 <= (_zz_193 + 3'b001); - if(_zz_197)begin - _zz_193 <= 3'b000; + _zz_197 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_199 && _zz_200))begin + _zz_198 <= (_zz_198 + 3'b001); + if(_zz_202)begin + _zz_198 <= 3'b000; end end - _zz_199 <= ((_zz_194 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_204 <= ((_zz_199 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -6406,7 +6396,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_294)begin + if(_zz_299)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -6442,7 +6432,7 @@ module VexRiscv ( end case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_295)begin + if(_zz_300)begin MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; MmuPlugin_shared_vpn_1 <= _zz_102[31 : 22]; MmuPlugin_shared_vpn_0 <= _zz_102[21 : 12]; @@ -6457,9 +6447,9 @@ module VexRiscv ( default : begin end endcase - if(_zz_278)begin - if(_zz_279)begin - if(_zz_296)begin + if(_zz_283)begin + if(_zz_284)begin + if(_zz_301)begin MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6471,7 +6461,7 @@ module VexRiscv ( MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_297)begin + if(_zz_302)begin MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6483,7 +6473,7 @@ module VexRiscv ( MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_298)begin + if(_zz_303)begin MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6495,7 +6485,7 @@ module VexRiscv ( MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_299)begin + if(_zz_304)begin MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6508,8 +6498,8 @@ module VexRiscv ( MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end end - if(_zz_280)begin - if(_zz_300)begin + if(_zz_285)begin + if(_zz_305)begin MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6521,7 +6511,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_301)begin + if(_zz_306)begin MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6533,7 +6523,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_302)begin + if(_zz_307)begin MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6545,7 +6535,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_303)begin + if(_zz_308)begin MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6559,8 +6549,8 @@ module VexRiscv ( end end end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_130 <= _zz_40[11 : 7]; + _zz_131 <= _zz_50; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -6569,9 +6559,9 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_270)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_157 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_157 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_275)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_162 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_162 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -6585,47 +6575,47 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_304)begin - if(_zz_305)begin + if(_zz_309)begin + if(_zz_310)begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_306)begin + if(_zz_311)begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_307)begin + if(_zz_312)begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end end - if(_zz_308)begin - if(_zz_309)begin + if(_zz_313)begin + if(_zz_314)begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_310)begin + if(_zz_315)begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_311)begin + if(_zz_316)begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_312)begin + if(_zz_317)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_313)begin + if(_zz_318)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_314)begin + if(_zz_319)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_272)begin + if(_zz_277)begin case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); @@ -6653,20 +6643,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_265)begin - if(_zz_291)begin + if(_zz_270)begin + if(_zz_296)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_410[31:0]; + memory_DivPlugin_div_result <= _zz_415[31:0]; end end end - if(_zz_292)begin + if(_zz_297)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_161 ? (~ _zz_162) : _zz_162) + _zz_416); - memory_DivPlugin_rs2 <= ((_zz_160 ? (~ execute_RS2) : execute_RS2) + _zz_418); - memory_DivPlugin_div_needRevert <= ((_zz_161 ^ (_zz_160 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_166 ? (~ _zz_167) : _zz_167) + _zz_421); + memory_DivPlugin_rs2 <= ((_zz_165 ? (~ execute_RS2) : execute_RS2) + _zz_423); + memory_DivPlugin_div_needRevert <= ((_zz_166 ^ (_zz_165 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -6962,7 +6952,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_432[0]; + CsrPlugin_mip_MSIP <= _zz_437[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -6999,7 +6989,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_322)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_scause_interrupt <= _zz_463[0]; + CsrPlugin_scause_interrupt <= _zz_468[0]; CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -7358,7 +7348,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_12)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -7372,7 +7362,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_12)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -7402,7 +7392,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -7429,7 +7419,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -7477,7 +7467,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -7487,7 +7477,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v index b4f3b34..3ce89ef 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -89,66 +89,66 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_203; - wire _zz_204; - wire _zz_205; - wire _zz_206; - wire _zz_207; wire _zz_208; wire _zz_209; wire _zz_210; - reg _zz_211; - reg _zz_212; - reg [31:0] _zz_213; - reg _zz_214; - reg [31:0] _zz_215; - reg [1:0] _zz_216; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + reg _zz_216; reg _zz_217; - reg _zz_218; - wire _zz_219; - wire [2:0] _zz_220; - reg _zz_221; - wire [31:0] _zz_222; + reg [31:0] _zz_218; + reg _zz_219; + reg [31:0] _zz_220; + reg [1:0] _zz_221; + reg _zz_222; reg _zz_223; - reg _zz_224; - wire _zz_225; - wire [31:0] _zz_226; - wire _zz_227; - wire _zz_228; - wire _zz_229; + wire _zz_224; + wire [2:0] _zz_225; + reg _zz_226; + wire [31:0] _zz_227; + reg _zz_228; + reg _zz_229; wire _zz_230; - wire _zz_231; + wire [31:0] _zz_231; wire _zz_232; wire _zz_233; wire _zz_234; - wire [3:0] _zz_235; + wire _zz_235; wire _zz_236; wire _zz_237; - reg [31:0] _zz_238; - reg [31:0] _zz_239; - reg [31:0] _zz_240; - reg _zz_241; - reg _zz_242; - reg _zz_243; - reg [9:0] _zz_244; - reg [9:0] _zz_245; - reg [9:0] _zz_246; - reg [9:0] _zz_247; + wire _zz_238; + wire _zz_239; + wire [3:0] _zz_240; + wire _zz_241; + wire _zz_242; + reg [31:0] _zz_243; + reg [31:0] _zz_244; + reg [31:0] _zz_245; + reg _zz_246; + reg _zz_247; reg _zz_248; - reg _zz_249; - reg _zz_250; - reg _zz_251; - reg _zz_252; + reg [9:0] _zz_249; + reg [9:0] _zz_250; + reg [9:0] _zz_251; + reg [9:0] _zz_252; reg _zz_253; reg _zz_254; - reg [9:0] _zz_255; - reg [9:0] _zz_256; - reg [9:0] _zz_257; - reg [9:0] _zz_258; + reg _zz_255; + reg _zz_256; + reg _zz_257; + reg _zz_258; reg _zz_259; - reg _zz_260; - reg _zz_261; - reg _zz_262; + reg [9:0] _zz_260; + reg [9:0] _zz_261; + reg [9:0] _zz_262; + reg [9:0] _zz_263; + reg _zz_264; + reg _zz_265; + reg _zz_266; + reg _zz_267; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -181,11 +181,6 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire _zz_267; wire _zz_268; wire _zz_269; wire _zz_270; @@ -198,12 +193,12 @@ module VexRiscv ( wire _zz_277; wire _zz_278; wire _zz_279; - wire [1:0] _zz_280; + wire _zz_280; wire _zz_281; wire _zz_282; wire _zz_283; wire _zz_284; - wire _zz_285; + wire [1:0] _zz_285; wire _zz_286; wire _zz_287; wire _zz_288; @@ -214,15 +209,15 @@ module VexRiscv ( wire _zz_293; wire _zz_294; wire _zz_295; - wire [1:0] _zz_296; + wire _zz_296; wire _zz_297; wire _zz_298; - wire [5:0] _zz_299; + wire _zz_299; wire _zz_300; - wire _zz_301; + wire [1:0] _zz_301; wire _zz_302; wire _zz_303; - wire _zz_304; + wire [5:0] _zz_304; wire _zz_305; wire _zz_306; wire _zz_307; @@ -240,26 +235,26 @@ module VexRiscv ( wire _zz_319; wire _zz_320; wire _zz_321; - wire [1:0] _zz_322; + wire _zz_322; wire _zz_323; - wire [1:0] _zz_324; - wire [51:0] _zz_325; - wire [51:0] _zz_326; - wire [51:0] _zz_327; - wire [32:0] _zz_328; - wire [51:0] _zz_329; - wire [49:0] _zz_330; + wire _zz_324; + wire _zz_325; + wire _zz_326; + wire [1:0] _zz_327; + wire _zz_328; + wire [1:0] _zz_329; + wire [51:0] _zz_330; wire [51:0] _zz_331; - wire [49:0] _zz_332; - wire [51:0] _zz_333; - wire [32:0] _zz_334; - wire [31:0] _zz_335; - wire [32:0] _zz_336; - wire [0:0] _zz_337; - wire [0:0] _zz_338; - wire [0:0] _zz_339; - wire [0:0] _zz_340; - wire [0:0] _zz_341; + wire [51:0] _zz_332; + wire [32:0] _zz_333; + wire [51:0] _zz_334; + wire [49:0] _zz_335; + wire [51:0] _zz_336; + wire [49:0] _zz_337; + wire [51:0] _zz_338; + wire [32:0] _zz_339; + wire [31:0] _zz_340; + wire [32:0] _zz_341; wire [0:0] _zz_342; wire [0:0] _zz_343; wire [0:0] _zz_344; @@ -276,80 +271,80 @@ module VexRiscv ( wire [0:0] _zz_355; wire [0:0] _zz_356; wire [0:0] _zz_357; - wire [4:0] _zz_358; - wire [2:0] _zz_359; - wire [31:0] _zz_360; - wire [11:0] _zz_361; - wire [31:0] _zz_362; - wire [19:0] _zz_363; - wire [11:0] _zz_364; + wire [0:0] _zz_358; + wire [0:0] _zz_359; + wire [0:0] _zz_360; + wire [0:0] _zz_361; + wire [0:0] _zz_362; + wire [4:0] _zz_363; + wire [2:0] _zz_364; wire [31:0] _zz_365; - wire [31:0] _zz_366; - wire [19:0] _zz_367; - wire [11:0] _zz_368; - wire [2:0] _zz_369; - wire [2:0] _zz_370; - wire [0:0] _zz_371; - wire [1:0] _zz_372; - wire [0:0] _zz_373; - wire [1:0] _zz_374; - wire [0:0] _zz_375; + wire [11:0] _zz_366; + wire [31:0] _zz_367; + wire [19:0] _zz_368; + wire [11:0] _zz_369; + wire [31:0] _zz_370; + wire [31:0] _zz_371; + wire [19:0] _zz_372; + wire [11:0] _zz_373; + wire [2:0] _zz_374; + wire [2:0] _zz_375; wire [0:0] _zz_376; - wire [0:0] _zz_377; + wire [1:0] _zz_377; wire [0:0] _zz_378; - wire [0:0] _zz_379; + wire [1:0] _zz_379; wire [0:0] _zz_380; wire [0:0] _zz_381; wire [0:0] _zz_382; - wire [1:0] _zz_383; + wire [0:0] _zz_383; wire [0:0] _zz_384; - wire [2:0] _zz_385; - wire [4:0] _zz_386; - wire [11:0] _zz_387; - wire [11:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire [31:0] _zz_391; - wire [31:0] _zz_392; - wire [31:0] _zz_393; + wire [0:0] _zz_385; + wire [0:0] _zz_386; + wire [0:0] _zz_387; + wire [1:0] _zz_388; + wire [0:0] _zz_389; + wire [2:0] _zz_390; + wire [4:0] _zz_391; + wire [11:0] _zz_392; + wire [11:0] _zz_393; wire [31:0] _zz_394; wire [31:0] _zz_395; - wire [11:0] _zz_396; - wire [19:0] _zz_397; - wire [11:0] _zz_398; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; wire [31:0] _zz_399; wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire [11:0] _zz_402; - wire [19:0] _zz_403; - wire [11:0] _zz_404; - wire [2:0] _zz_405; - wire [1:0] _zz_406; - wire [1:0] _zz_407; - wire [65:0] _zz_408; - wire [65:0] _zz_409; - wire [31:0] _zz_410; - wire [31:0] _zz_411; - wire [0:0] _zz_412; - wire [5:0] _zz_413; - wire [32:0] _zz_414; + wire [11:0] _zz_401; + wire [19:0] _zz_402; + wire [11:0] _zz_403; + wire [31:0] _zz_404; + wire [31:0] _zz_405; + wire [31:0] _zz_406; + wire [11:0] _zz_407; + wire [19:0] _zz_408; + wire [11:0] _zz_409; + wire [2:0] _zz_410; + wire [1:0] _zz_411; + wire [1:0] _zz_412; + wire [65:0] _zz_413; + wire [65:0] _zz_414; wire [31:0] _zz_415; wire [31:0] _zz_416; - wire [32:0] _zz_417; - wire [32:0] _zz_418; + wire [0:0] _zz_417; + wire [5:0] _zz_418; wire [32:0] _zz_419; - wire [32:0] _zz_420; - wire [0:0] _zz_421; + wire [31:0] _zz_420; + wire [31:0] _zz_421; wire [32:0] _zz_422; - wire [0:0] _zz_423; + wire [32:0] _zz_423; wire [32:0] _zz_424; - wire [0:0] _zz_425; - wire [31:0] _zz_426; - wire [0:0] _zz_427; + wire [32:0] _zz_425; + wire [0:0] _zz_426; + wire [32:0] _zz_427; wire [0:0] _zz_428; - wire [0:0] _zz_429; + wire [32:0] _zz_429; wire [0:0] _zz_430; - wire [0:0] _zz_431; + wire [31:0] _zz_431; wire [0:0] _zz_432; wire [0:0] _zz_433; wire [0:0] _zz_434; @@ -390,246 +385,251 @@ module VexRiscv ( wire [0:0] _zz_469; wire [0:0] _zz_470; wire [0:0] _zz_471; - wire [26:0] _zz_472; - wire _zz_473; - wire _zz_474; - wire [2:0] _zz_475; - wire [31:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; + wire [0:0] _zz_472; + wire [0:0] _zz_473; + wire [0:0] _zz_474; + wire [0:0] _zz_475; + wire [0:0] _zz_476; + wire [26:0] _zz_477; + wire _zz_478; wire _zz_479; - wire [0:0] _zz_480; - wire [17:0] _zz_481; + wire [2:0] _zz_480; + wire [31:0] _zz_481; wire [31:0] _zz_482; wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire _zz_485; - wire [0:0] _zz_486; - wire [11:0] _zz_487; + wire _zz_484; + wire [0:0] _zz_485; + wire [17:0] _zz_486; + wire [31:0] _zz_487; wire [31:0] _zz_488; wire [31:0] _zz_489; - wire [31:0] _zz_490; - wire _zz_491; - wire [0:0] _zz_492; - wire [5:0] _zz_493; + wire _zz_490; + wire [0:0] _zz_491; + wire [11:0] _zz_492; + wire [31:0] _zz_493; wire [31:0] _zz_494; wire [31:0] _zz_495; - wire [31:0] _zz_496; - wire _zz_497; - wire _zz_498; - wire _zz_499; - wire _zz_500; - wire _zz_501; - wire [31:0] _zz_502; - wire [0:0] _zz_503; - wire [0:0] _zz_504; + wire _zz_496; + wire [0:0] _zz_497; + wire [5:0] _zz_498; + wire [31:0] _zz_499; + wire [31:0] _zz_500; + wire [31:0] _zz_501; + wire _zz_502; + wire _zz_503; + wire _zz_504; wire _zz_505; - wire [0:0] _zz_506; - wire [29:0] _zz_507; - wire [31:0] _zz_508; - wire _zz_509; + wire _zz_506; + wire [31:0] _zz_507; + wire [0:0] _zz_508; + wire [0:0] _zz_509; wire _zz_510; - wire _zz_511; - wire [1:0] _zz_512; - wire [1:0] _zz_513; + wire [0:0] _zz_511; + wire [29:0] _zz_512; + wire [31:0] _zz_513; wire _zz_514; - wire [0:0] _zz_515; - wire [25:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire [31:0] _zz_520; - wire _zz_521; - wire _zz_522; - wire [1:0] _zz_523; - wire [1:0] _zz_524; - wire _zz_525; - wire [0:0] _zz_526; - wire [22:0] _zz_527; - wire [31:0] _zz_528; - wire [31:0] _zz_529; - wire [31:0] _zz_530; - wire [31:0] _zz_531; - wire _zz_532; - wire [0:0] _zz_533; - wire [0:0] _zz_534; - wire _zz_535; - wire [0:0] _zz_536; - wire [0:0] _zz_537; - wire _zz_538; + wire _zz_515; + wire _zz_516; + wire [1:0] _zz_517; + wire [1:0] _zz_518; + wire _zz_519; + wire [0:0] _zz_520; + wire [25:0] _zz_521; + wire [31:0] _zz_522; + wire [31:0] _zz_523; + wire [31:0] _zz_524; + wire [31:0] _zz_525; + wire _zz_526; + wire _zz_527; + wire [1:0] _zz_528; + wire [1:0] _zz_529; + wire _zz_530; + wire [0:0] _zz_531; + wire [22:0] _zz_532; + wire [31:0] _zz_533; + wire [31:0] _zz_534; + wire [31:0] _zz_535; + wire [31:0] _zz_536; + wire _zz_537; + wire [0:0] _zz_538; wire [0:0] _zz_539; - wire [19:0] _zz_540; - wire [31:0] _zz_541; - wire [31:0] _zz_542; - wire [31:0] _zz_543; - wire _zz_544; - wire _zz_545; - wire _zz_546; - wire [0:0] _zz_547; - wire [0:0] _zz_548; + wire _zz_540; + wire [0:0] _zz_541; + wire [0:0] _zz_542; + wire _zz_543; + wire [0:0] _zz_544; + wire [19:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; wire _zz_549; - wire [0:0] _zz_550; - wire [16:0] _zz_551; - wire [31:0] _zz_552; - wire [31:0] _zz_553; - wire [31:0] _zz_554; + wire _zz_550; + wire _zz_551; + wire [0:0] _zz_552; + wire [0:0] _zz_553; + wire _zz_554; wire [0:0] _zz_555; - wire [2:0] _zz_556; - wire [0:0] _zz_557; - wire [0:0] _zz_558; - wire _zz_559; + wire [16:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire [31:0] _zz_559; wire [0:0] _zz_560; - wire [13:0] _zz_561; - wire [31:0] _zz_562; - wire [31:0] _zz_563; - wire [31:0] _zz_564; - wire _zz_565; - wire _zz_566; + wire [2:0] _zz_561; + wire [0:0] _zz_562; + wire [0:0] _zz_563; + wire _zz_564; + wire [0:0] _zz_565; + wire [13:0] _zz_566; wire [31:0] _zz_567; wire [31:0] _zz_568; wire [31:0] _zz_569; - wire [0:0] _zz_570; - wire [4:0] _zz_571; - wire [2:0] _zz_572; - wire [2:0] _zz_573; - wire _zz_574; + wire _zz_570; + wire _zz_571; + wire [31:0] _zz_572; + wire [31:0] _zz_573; + wire [31:0] _zz_574; wire [0:0] _zz_575; - wire [10:0] _zz_576; - wire [31:0] _zz_577; - wire [31:0] _zz_578; - wire [31:0] _zz_579; - wire [31:0] _zz_580; - wire _zz_581; - wire [0:0] _zz_582; - wire [2:0] _zz_583; - wire _zz_584; - wire [0:0] _zz_585; - wire [0:0] _zz_586; + wire [4:0] _zz_576; + wire [2:0] _zz_577; + wire [2:0] _zz_578; + wire _zz_579; + wire [0:0] _zz_580; + wire [10:0] _zz_581; + wire [31:0] _zz_582; + wire [31:0] _zz_583; + wire [31:0] _zz_584; + wire [31:0] _zz_585; + wire _zz_586; wire [0:0] _zz_587; - wire [3:0] _zz_588; - wire [4:0] _zz_589; - wire [4:0] _zz_590; - wire _zz_591; + wire [2:0] _zz_588; + wire _zz_589; + wire [0:0] _zz_590; + wire [0:0] _zz_591; wire [0:0] _zz_592; - wire [8:0] _zz_593; - wire [31:0] _zz_594; - wire [31:0] _zz_595; - wire [31:0] _zz_596; - wire _zz_597; - wire [0:0] _zz_598; - wire [0:0] _zz_599; + wire [3:0] _zz_593; + wire [4:0] _zz_594; + wire [4:0] _zz_595; + wire _zz_596; + wire [0:0] _zz_597; + wire [8:0] _zz_598; + wire [31:0] _zz_599; wire [31:0] _zz_600; wire [31:0] _zz_601; - wire [31:0] _zz_602; - wire [31:0] _zz_603; - wire [31:0] _zz_604; + wire _zz_602; + wire [0:0] _zz_603; + wire [0:0] _zz_604; wire [31:0] _zz_605; wire [31:0] _zz_606; - wire _zz_607; - wire [0:0] _zz_608; - wire [1:0] _zz_609; - wire [0:0] _zz_610; - wire [2:0] _zz_611; - wire [0:0] _zz_612; - wire [5:0] _zz_613; + wire [31:0] _zz_607; + wire [31:0] _zz_608; + wire [31:0] _zz_609; + wire [31:0] _zz_610; + wire [31:0] _zz_611; + wire _zz_612; + wire [0:0] _zz_613; wire [1:0] _zz_614; - wire [1:0] _zz_615; - wire _zz_616; + wire [0:0] _zz_615; + wire [2:0] _zz_616; wire [0:0] _zz_617; - wire [6:0] _zz_618; - wire [31:0] _zz_619; - wire [31:0] _zz_620; - wire [31:0] _zz_621; - wire [31:0] _zz_622; - wire [31:0] _zz_623; + wire [5:0] _zz_618; + wire [1:0] _zz_619; + wire [1:0] _zz_620; + wire _zz_621; + wire [0:0] _zz_622; + wire [6:0] _zz_623; wire [31:0] _zz_624; wire [31:0] _zz_625; wire [31:0] _zz_626; - wire _zz_627; + wire [31:0] _zz_627; wire [31:0] _zz_628; wire [31:0] _zz_629; - wire _zz_630; - wire [0:0] _zz_631; - wire [0:0] _zz_632; - wire _zz_633; - wire [0:0] _zz_634; - wire [3:0] _zz_635; - wire _zz_636; + wire [31:0] _zz_630; + wire [31:0] _zz_631; + wire _zz_632; + wire [31:0] _zz_633; + wire [31:0] _zz_634; + wire _zz_635; + wire [0:0] _zz_636; wire [0:0] _zz_637; - wire [0:0] _zz_638; + wire _zz_638; wire [0:0] _zz_639; - wire [0:0] _zz_640; + wire [3:0] _zz_640; wire _zz_641; wire [0:0] _zz_642; - wire [4:0] _zz_643; - wire [31:0] _zz_644; - wire [31:0] _zz_645; - wire [31:0] _zz_646; - wire [31:0] _zz_647; - wire [31:0] _zz_648; + wire [0:0] _zz_643; + wire [0:0] _zz_644; + wire [0:0] _zz_645; + wire _zz_646; + wire [0:0] _zz_647; + wire [4:0] _zz_648; wire [31:0] _zz_649; wire [31:0] _zz_650; wire [31:0] _zz_651; wire [31:0] _zz_652; - wire _zz_653; - wire [0:0] _zz_654; - wire [1:0] _zz_655; + wire [31:0] _zz_653; + wire [31:0] _zz_654; + wire [31:0] _zz_655; wire [31:0] _zz_656; wire [31:0] _zz_657; - wire [31:0] _zz_658; - wire [31:0] _zz_659; - wire [31:0] _zz_660; - wire _zz_661; - wire [4:0] _zz_662; - wire [4:0] _zz_663; - wire _zz_664; - wire [0:0] _zz_665; - wire [2:0] _zz_666; - wire [31:0] _zz_667; - wire [31:0] _zz_668; - wire [31:0] _zz_669; - wire _zz_670; - wire [31:0] _zz_671; - wire _zz_672; - wire [0:0] _zz_673; - wire [2:0] _zz_674; - wire [0:0] _zz_675; - wire [0:0] _zz_676; - wire [2:0] _zz_677; - wire [2:0] _zz_678; - wire _zz_679; + wire _zz_658; + wire [0:0] _zz_659; + wire [1:0] _zz_660; + wire [31:0] _zz_661; + wire [31:0] _zz_662; + wire [31:0] _zz_663; + wire [31:0] _zz_664; + wire [31:0] _zz_665; + wire _zz_666; + wire [4:0] _zz_667; + wire [4:0] _zz_668; + wire _zz_669; + wire [0:0] _zz_670; + wire [2:0] _zz_671; + wire [31:0] _zz_672; + wire [31:0] _zz_673; + wire [31:0] _zz_674; + wire _zz_675; + wire [31:0] _zz_676; + wire _zz_677; + wire [0:0] _zz_678; + wire [2:0] _zz_679; wire [0:0] _zz_680; wire [0:0] _zz_681; - wire [31:0] _zz_682; - wire [31:0] _zz_683; - wire [31:0] _zz_684; - wire [31:0] _zz_685; - wire _zz_686; - wire [0:0] _zz_687; - wire [0:0] _zz_688; + wire [2:0] _zz_682; + wire [2:0] _zz_683; + wire _zz_684; + wire [0:0] _zz_685; + wire [0:0] _zz_686; + wire [31:0] _zz_687; + wire [31:0] _zz_688; wire [31:0] _zz_689; wire [31:0] _zz_690; wire _zz_691; wire [0:0] _zz_692; wire [0:0] _zz_693; - wire [0:0] _zz_694; - wire [1:0] _zz_695; - wire [1:0] _zz_696; - wire [1:0] _zz_697; + wire [31:0] _zz_694; + wire [31:0] _zz_695; + wire _zz_696; + wire [0:0] _zz_697; wire [0:0] _zz_698; wire [0:0] _zz_699; - wire [31:0] _zz_700; - wire [31:0] _zz_701; - wire [31:0] _zz_702; - wire [31:0] _zz_703; - wire [31:0] _zz_704; + wire [1:0] _zz_700; + wire [1:0] _zz_701; + wire [1:0] _zz_702; + wire [0:0] _zz_703; + wire [0:0] _zz_704; wire [31:0] _zz_705; wire [31:0] _zz_706; wire [31:0] _zz_707; - wire _zz_708; - wire _zz_709; - wire _zz_710; + wire [31:0] _zz_708; + wire [31:0] _zz_709; + wire [31:0] _zz_710; wire [31:0] _zz_711; + wire [31:0] _zz_712; + wire _zz_713; + wire _zz_714; + wire _zz_715; + wire [31:0] _zz_716; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1342,44 +1342,39 @@ module VexRiscv ( reg [31:0] _zz_126; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_127; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_128; - wire _zz_129; - wire _zz_130; - wire _zz_131; - wire _zz_132; + reg _zz_128; + reg _zz_129; + reg _zz_130; + reg [4:0] _zz_131; + reg [31:0] _zz_132; wire _zz_133; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_134; - reg _zz_135; - reg _zz_136; + wire _zz_134; + wire _zz_135; + wire _zz_136; wire _zz_137; - reg [19:0] _zz_138; - wire _zz_139; - reg [10:0] _zz_140; - wire _zz_141; - reg [18:0] _zz_142; - reg _zz_143; + wire _zz_138; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_139; + reg _zz_140; + reg _zz_141; + wire _zz_142; + reg [19:0] _zz_143; + wire _zz_144; + reg [10:0] _zz_145; + wire _zz_146; + reg [18:0] _zz_147; + reg _zz_148; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_144; - reg [19:0] _zz_145; - wire _zz_146; - reg [10:0] _zz_147; - wire _zz_148; - reg [18:0] _zz_149; + wire _zz_149; + reg [19:0] _zz_150; + wire _zz_151; + reg [10:0] _zz_152; + wire _zz_153; + reg [18:0] _zz_154; wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] _zz_150; + reg [1:0] _zz_155; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1436,12 +1431,12 @@ module VexRiscv ( reg [21:0] CsrPlugin_satp_PPN; reg [8:0] CsrPlugin_satp_ASID; reg [0:0] CsrPlugin_satp_MODE; - wire _zz_151; - wire _zz_152; - wire _zz_153; - wire _zz_154; - wire _zz_155; wire _zz_156; + wire _zz_157; + wire _zz_158; + wire _zz_159; + wire _zz_160; + wire _zz_161; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1454,8 +1449,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_157; - wire _zz_158; + wire [1:0] _zz_162; + wire _zz_163; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1508,20 +1503,20 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_159; + wire [31:0] _zz_164; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_160; - wire _zz_161; - wire _zz_162; - reg [32:0] _zz_163; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_164; wire [31:0] _zz_165; - reg [31:0] _zz_166; - wire [31:0] _zz_167; + wire _zz_166; + wire _zz_167; + reg [32:0] _zz_168; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_169; + wire [31:0] _zz_170; + reg [31:0] _zz_171; + wire [31:0] _zz_172; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1531,7 +1526,7 @@ module VexRiscv ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_168; + reg _zz_173; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1604,7 +1599,7 @@ module VexRiscv ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_169; + reg [2:0] _zz_174; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_256; @@ -1633,11 +1628,6 @@ module VexRiscv ( reg execute_CsrPlugin_csr_4032; reg execute_CsrPlugin_csr_2496; reg execute_CsrPlugin_csr_3520; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; reg [31:0] _zz_175; reg [31:0] _zz_176; reg [31:0] _zz_177; @@ -1657,16 +1647,21 @@ module VexRiscv ( reg [31:0] _zz_191; reg [31:0] _zz_192; reg [31:0] _zz_193; - reg [2:0] _zz_194; - reg _zz_195; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; + reg [2:0] _zz_199; + reg _zz_200; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - reg _zz_202; + reg [2:0] _zz_201; + wire _zz_202; + wire _zz_203; + wire _zz_204; + wire _zz_205; + wire _zz_206; + reg _zz_207; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] _zz_1_string; @@ -1752,464 +1747,464 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_263 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_264 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_265 = 1'b1; - assign _zz_266 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_267 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_268 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_269 = ((_zz_208 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_270 = ((_zz_208 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_271 = ((_zz_208 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_272 = ((_zz_208 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_273 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_274 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_275 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_276 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_277 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_278 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_279 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_280 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_281 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); - assign _zz_282 = (! dataCache_1_io_cpu_execute_refilling); - assign _zz_283 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_284 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); - assign _zz_285 = MmuPlugin_shared_portSortedOh[0]; - assign _zz_286 = MmuPlugin_shared_portSortedOh[1]; - assign _zz_287 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_288 = (1'b0 || (! 1'b1)); - assign _zz_289 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_290 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_291 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_292 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_293 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_294 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_295 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_296 = execute_INSTRUCTION[13 : 12]; - assign _zz_297 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_298 = (! memory_arbitration_isStuck); - assign _zz_299 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_300 = (iBus_cmd_valid || (_zz_194 != 3'b000)); - assign _zz_301 = (_zz_237 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_302 = (MmuPlugin_shared_refills != 2'b00); - assign _zz_303 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); - assign _zz_304 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); - assign _zz_305 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); - assign _zz_306 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); - assign _zz_307 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); - assign _zz_308 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); - assign _zz_309 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); - assign _zz_310 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); - assign _zz_311 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); - assign _zz_312 = ((_zz_151 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); - assign _zz_313 = ((_zz_152 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); - assign _zz_314 = ((_zz_153 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); - assign _zz_315 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_316 = ((_zz_151 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); - assign _zz_317 = ((_zz_152 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); - assign _zz_318 = ((_zz_153 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); - assign _zz_319 = ((_zz_154 && 1'b1) && (! 1'b0)); - assign _zz_320 = ((_zz_155 && 1'b1) && (! 1'b0)); - assign _zz_321 = ((_zz_156 && 1'b1) && (! 1'b0)); - assign _zz_322 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_323 = execute_INSTRUCTION[13]; - assign _zz_324 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_325 = ($signed(_zz_326) + $signed(_zz_331)); - assign _zz_326 = ($signed(_zz_327) + $signed(_zz_329)); - assign _zz_327 = 52'h0; - assign _zz_328 = {1'b0,memory_MUL_LL}; - assign _zz_329 = {{19{_zz_328[32]}}, _zz_328}; - assign _zz_330 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_331 = {{2{_zz_330[49]}}, _zz_330}; - assign _zz_332 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_333 = {{2{_zz_332[49]}}, _zz_332}; - assign _zz_334 = ($signed(_zz_336) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_335 = _zz_334[31 : 0]; - assign _zz_336 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_337 = _zz_104[34 : 34]; - assign _zz_338 = _zz_104[33 : 33]; - assign _zz_339 = _zz_104[32 : 32]; - assign _zz_340 = _zz_104[31 : 31]; - assign _zz_341 = _zz_104[28 : 28]; - assign _zz_342 = _zz_104[21 : 21]; - assign _zz_343 = _zz_104[20 : 20]; - assign _zz_344 = _zz_104[19 : 19]; - assign _zz_345 = _zz_104[13 : 13]; - assign _zz_346 = _zz_104[12 : 12]; - assign _zz_347 = _zz_104[11 : 11]; - assign _zz_348 = _zz_104[35 : 35]; - assign _zz_349 = _zz_104[17 : 17]; - assign _zz_350 = _zz_104[5 : 5]; - assign _zz_351 = _zz_104[3 : 3]; - assign _zz_352 = _zz_104[18 : 18]; - assign _zz_353 = _zz_104[10 : 10]; - assign _zz_354 = _zz_104[16 : 16]; - assign _zz_355 = _zz_104[15 : 15]; - assign _zz_356 = _zz_104[4 : 4]; - assign _zz_357 = _zz_104[0 : 0]; - assign _zz_358 = (_zz_57 - 5'h01); - assign _zz_359 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_360 = {29'd0, _zz_359}; - assign _zz_361 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_362 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_363 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_364 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_365 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_366 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_367 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_368 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_369 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_370 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_371 = MmuPlugin_ports_0_entryToReplace_willIncrement; - assign _zz_372 = {1'd0, _zz_371}; - assign _zz_373 = MmuPlugin_ports_1_entryToReplace_willIncrement; - assign _zz_374 = {1'd0, _zz_373}; - assign _zz_375 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; - assign _zz_376 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; - assign _zz_377 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; - assign _zz_378 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; - assign _zz_379 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; - assign _zz_380 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; - assign _zz_381 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; - assign _zz_382 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; - assign _zz_383 = (_zz_100 - 2'b01); - assign _zz_384 = execute_SRC_LESS; - assign _zz_385 = 3'b100; - assign _zz_386 = execute_INSTRUCTION[19 : 15]; - assign _zz_387 = execute_INSTRUCTION[31 : 20]; - assign _zz_388 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_389 = ($signed(_zz_390) + $signed(_zz_393)); - assign _zz_390 = ($signed(_zz_391) + $signed(_zz_392)); - assign _zz_391 = execute_SRC1; - assign _zz_392 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_393 = (execute_SRC_USE_SUB_LESS ? _zz_394 : _zz_395); - assign _zz_394 = 32'h00000001; - assign _zz_395 = 32'h0; - assign _zz_396 = execute_INSTRUCTION[31 : 20]; - assign _zz_397 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_398 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_399 = {_zz_138,execute_INSTRUCTION[31 : 20]}; - assign _zz_400 = {{_zz_140,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_401 = {{_zz_142,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_402 = execute_INSTRUCTION[31 : 20]; - assign _zz_403 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_404 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_405 = 3'b100; - assign _zz_406 = (_zz_157 & (~ _zz_407)); - assign _zz_407 = (_zz_157 - 2'b01); - assign _zz_408 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_409 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_410 = writeBack_MUL_LOW[31 : 0]; - assign _zz_411 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_412 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_413 = {5'd0, _zz_412}; - assign _zz_414 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_415 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_416 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_417 = {_zz_159,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_418 = _zz_419; - assign _zz_419 = _zz_420; - assign _zz_420 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_160) : _zz_160)} + _zz_422); - assign _zz_421 = memory_DivPlugin_div_needRevert; - assign _zz_422 = {32'd0, _zz_421}; - assign _zz_423 = _zz_162; - assign _zz_424 = {32'd0, _zz_423}; - assign _zz_425 = _zz_161; - assign _zz_426 = {31'd0, _zz_425}; - assign _zz_427 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_428 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_429 = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_430 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_431 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_432 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_433 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_434 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_435 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_436 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_268 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_269 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_270 = 1'b1; + assign _zz_271 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_272 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_273 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_274 = ((_zz_213 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_275 = ((_zz_213 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_276 = ((_zz_213 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_277 = ((_zz_213 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_278 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_280 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_281 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_282 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_283 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_284 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_285 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_286 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign _zz_287 = (! dataCache_1_io_cpu_execute_refilling); + assign _zz_288 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_289 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign _zz_290 = MmuPlugin_shared_portSortedOh[0]; + assign _zz_291 = MmuPlugin_shared_portSortedOh[1]; + assign _zz_292 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_293 = (1'b0 || (! 1'b1)); + assign _zz_294 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_295 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_296 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_297 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_298 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_299 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_300 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_301 = execute_INSTRUCTION[13 : 12]; + assign _zz_302 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_303 = (! memory_arbitration_isStuck); + assign _zz_304 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_305 = (iBus_cmd_valid || (_zz_199 != 3'b000)); + assign _zz_306 = (_zz_242 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_307 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_308 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign _zz_309 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign _zz_310 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign _zz_311 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign _zz_312 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign _zz_313 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign _zz_314 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign _zz_315 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign _zz_316 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign _zz_317 = ((_zz_156 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign _zz_318 = ((_zz_157 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign _zz_319 = ((_zz_158 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign _zz_320 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_321 = ((_zz_156 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign _zz_322 = ((_zz_157 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign _zz_323 = ((_zz_158 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign _zz_324 = ((_zz_159 && 1'b1) && (! 1'b0)); + assign _zz_325 = ((_zz_160 && 1'b1) && (! 1'b0)); + assign _zz_326 = ((_zz_161 && 1'b1) && (! 1'b0)); + assign _zz_327 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_328 = execute_INSTRUCTION[13]; + assign _zz_329 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_330 = ($signed(_zz_331) + $signed(_zz_336)); + assign _zz_331 = ($signed(_zz_332) + $signed(_zz_334)); + assign _zz_332 = 52'h0; + assign _zz_333 = {1'b0,memory_MUL_LL}; + assign _zz_334 = {{19{_zz_333[32]}}, _zz_333}; + assign _zz_335 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_336 = {{2{_zz_335[49]}}, _zz_335}; + assign _zz_337 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_338 = {{2{_zz_337[49]}}, _zz_337}; + assign _zz_339 = ($signed(_zz_341) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_340 = _zz_339[31 : 0]; + assign _zz_341 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_342 = _zz_104[34 : 34]; + assign _zz_343 = _zz_104[33 : 33]; + assign _zz_344 = _zz_104[32 : 32]; + assign _zz_345 = _zz_104[31 : 31]; + assign _zz_346 = _zz_104[28 : 28]; + assign _zz_347 = _zz_104[21 : 21]; + assign _zz_348 = _zz_104[20 : 20]; + assign _zz_349 = _zz_104[19 : 19]; + assign _zz_350 = _zz_104[13 : 13]; + assign _zz_351 = _zz_104[12 : 12]; + assign _zz_352 = _zz_104[11 : 11]; + assign _zz_353 = _zz_104[35 : 35]; + assign _zz_354 = _zz_104[17 : 17]; + assign _zz_355 = _zz_104[5 : 5]; + assign _zz_356 = _zz_104[3 : 3]; + assign _zz_357 = _zz_104[18 : 18]; + assign _zz_358 = _zz_104[10 : 10]; + assign _zz_359 = _zz_104[16 : 16]; + assign _zz_360 = _zz_104[15 : 15]; + assign _zz_361 = _zz_104[4 : 4]; + assign _zz_362 = _zz_104[0 : 0]; + assign _zz_363 = (_zz_57 - 5'h01); + assign _zz_364 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_365 = {29'd0, _zz_364}; + assign _zz_366 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_367 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_368 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_369 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_370 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_371 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_372 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_373 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_374 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_375 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_376 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_377 = {1'd0, _zz_376}; + assign _zz_378 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_379 = {1'd0, _zz_378}; + assign _zz_380 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; + assign _zz_381 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; + assign _zz_382 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; + assign _zz_383 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; + assign _zz_384 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; + assign _zz_385 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; + assign _zz_386 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; + assign _zz_387 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; + assign _zz_388 = (_zz_100 - 2'b01); + assign _zz_389 = execute_SRC_LESS; + assign _zz_390 = 3'b100; + assign _zz_391 = execute_INSTRUCTION[19 : 15]; + assign _zz_392 = execute_INSTRUCTION[31 : 20]; + assign _zz_393 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_394 = ($signed(_zz_395) + $signed(_zz_398)); + assign _zz_395 = ($signed(_zz_396) + $signed(_zz_397)); + assign _zz_396 = execute_SRC1; + assign _zz_397 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_398 = (execute_SRC_USE_SUB_LESS ? _zz_399 : _zz_400); + assign _zz_399 = 32'h00000001; + assign _zz_400 = 32'h0; + assign _zz_401 = execute_INSTRUCTION[31 : 20]; + assign _zz_402 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_403 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_404 = {_zz_143,execute_INSTRUCTION[31 : 20]}; + assign _zz_405 = {{_zz_145,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_406 = {{_zz_147,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_407 = execute_INSTRUCTION[31 : 20]; + assign _zz_408 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_409 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_410 = 3'b100; + assign _zz_411 = (_zz_162 & (~ _zz_412)); + assign _zz_412 = (_zz_162 - 2'b01); + assign _zz_413 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_414 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_415 = writeBack_MUL_LOW[31 : 0]; + assign _zz_416 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_417 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_418 = {5'd0, _zz_417}; + assign _zz_419 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_420 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_421 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_422 = {_zz_164,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_423 = _zz_424; + assign _zz_424 = _zz_425; + assign _zz_425 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_165) : _zz_165)} + _zz_427); + assign _zz_426 = memory_DivPlugin_div_needRevert; + assign _zz_427 = {32'd0, _zz_426}; + assign _zz_428 = _zz_167; + assign _zz_429 = {32'd0, _zz_428}; + assign _zz_430 = _zz_166; + assign _zz_431 = {31'd0, _zz_430}; + assign _zz_432 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_433 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_434 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_435 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_436 = execute_CsrPlugin_writeData[3 : 3]; assign _zz_437 = execute_CsrPlugin_writeData[5 : 5]; assign _zz_438 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_439 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_440 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_441 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_442 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_443 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_444 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_445 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_446 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_447 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_448 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_449 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_450 = execute_CsrPlugin_writeData[0 : 0]; - assign _zz_451 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_452 = execute_CsrPlugin_writeData[2 : 2]; - assign _zz_453 = execute_CsrPlugin_writeData[4 : 4]; - assign _zz_454 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_455 = execute_CsrPlugin_writeData[6 : 6]; - assign _zz_456 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_457 = execute_CsrPlugin_writeData[8 : 8]; - assign _zz_458 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_459 = execute_CsrPlugin_writeData[12 : 12]; - assign _zz_460 = execute_CsrPlugin_writeData[13 : 13]; - assign _zz_461 = execute_CsrPlugin_writeData[15 : 15]; - assign _zz_462 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_463 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_464 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_465 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_466 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_439 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_440 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_441 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_442 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_443 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_444 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_445 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_446 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_447 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_448 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_449 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_450 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_451 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_452 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_453 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_454 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_455 = execute_CsrPlugin_writeData[0 : 0]; + assign _zz_456 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_457 = execute_CsrPlugin_writeData[2 : 2]; + assign _zz_458 = execute_CsrPlugin_writeData[4 : 4]; + assign _zz_459 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_460 = execute_CsrPlugin_writeData[6 : 6]; + assign _zz_461 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_462 = execute_CsrPlugin_writeData[8 : 8]; + assign _zz_463 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_464 = execute_CsrPlugin_writeData[12 : 12]; + assign _zz_465 = execute_CsrPlugin_writeData[13 : 13]; + assign _zz_466 = execute_CsrPlugin_writeData[15 : 15]; assign _zz_467 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_468 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_469 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_470 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_471 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_472 = (iBus_cmd_payload_address >>> 5); - assign _zz_473 = 1'b1; - assign _zz_474 = 1'b1; - assign _zz_475 = {_zz_60,{_zz_62,_zz_61}}; - assign _zz_476 = 32'h0000107f; - assign _zz_477 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_478 = 32'h00002073; - assign _zz_479 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_480 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_481 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_482) == 32'h00000003),{(_zz_483 == _zz_484),{_zz_485,{_zz_486,_zz_487}}}}}}; - assign _zz_482 = 32'h0000505f; - assign _zz_483 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_484 = 32'h00000063; - assign _zz_485 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_486 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); - assign _zz_487 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_488) == 32'h0000500f),{(_zz_489 == _zz_490),{_zz_491,{_zz_492,_zz_493}}}}}}; - assign _zz_488 = 32'h01f0707f; - assign _zz_489 = (decode_INSTRUCTION & 32'hbc00707f); - assign _zz_490 = 32'h00005013; - assign _zz_491 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); - assign _zz_492 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_493 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_494) == 32'h12000073),{(_zz_495 == _zz_496),{_zz_497,_zz_498}}}}}; - assign _zz_494 = 32'hfe007fff; - assign _zz_495 = (decode_INSTRUCTION & 32'hdfffffff); - assign _zz_496 = 32'h10200073; - assign _zz_497 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); - assign _zz_498 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_499 = decode_INSTRUCTION[31]; - assign _zz_500 = decode_INSTRUCTION[31]; - assign _zz_501 = decode_INSTRUCTION[7]; - assign _zz_502 = 32'h10103050; - assign _zz_503 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_504 = 1'b0; - assign _zz_505 = (((decode_INSTRUCTION & _zz_508) == 32'h02000030) != 1'b0); - assign _zz_506 = ({_zz_509,_zz_510} != 2'b00); - assign _zz_507 = {(_zz_511 != 1'b0),{(_zz_512 != _zz_513),{_zz_514,{_zz_515,_zz_516}}}}; - assign _zz_508 = 32'h02004074; - assign _zz_509 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); - assign _zz_510 = ((decode_INSTRUCTION & 32'h12203050) == 32'h10000050); - assign _zz_511 = ((decode_INSTRUCTION & 32'h02103050) == 32'h00000050); - assign _zz_512 = {(_zz_517 == _zz_518),(_zz_519 == _zz_520)}; - assign _zz_513 = 2'b00; - assign _zz_514 = ({_zz_106,_zz_521} != 2'b00); - assign _zz_515 = (_zz_522 != 1'b0); - assign _zz_516 = {(_zz_523 != _zz_524),{_zz_525,{_zz_526,_zz_527}}}; - assign _zz_517 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_518 = 32'h00001050; - assign _zz_519 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_520 = 32'h00002050; - assign _zz_521 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_522 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_523 = {(_zz_528 == _zz_529),(_zz_530 == _zz_531)}; - assign _zz_524 = 2'b00; - assign _zz_525 = ({_zz_532,{_zz_533,_zz_534}} != 3'b000); - assign _zz_526 = (_zz_535 != 1'b0); - assign _zz_527 = {(_zz_536 != _zz_537),{_zz_538,{_zz_539,_zz_540}}}; - assign _zz_528 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_529 = 32'h00005010; - assign _zz_530 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_531 = 32'h00005020; - assign _zz_532 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_533 = ((decode_INSTRUCTION & _zz_541) == 32'h00001010); - assign _zz_534 = ((decode_INSTRUCTION & _zz_542) == 32'h00001010); - assign _zz_535 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_536 = ((decode_INSTRUCTION & _zz_543) == 32'h00002000); - assign _zz_537 = 1'b0; - assign _zz_538 = ({_zz_544,_zz_545} != 2'b00); - assign _zz_539 = (_zz_546 != 1'b0); - assign _zz_540 = {(_zz_547 != _zz_548),{_zz_549,{_zz_550,_zz_551}}}; - assign _zz_541 = 32'h00007034; - assign _zz_542 = 32'h02007054; - assign _zz_543 = 32'h00003000; - assign _zz_544 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_545 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_546 = ((decode_INSTRUCTION & 32'h02003050) == 32'h02000050); - assign _zz_547 = ((decode_INSTRUCTION & _zz_552) == 32'h00004008); - assign _zz_548 = 1'b0; - assign _zz_549 = ((_zz_553 == _zz_554) != 1'b0); - assign _zz_550 = ({_zz_555,_zz_556} != 4'b0000); - assign _zz_551 = {(_zz_557 != _zz_558),{_zz_559,{_zz_560,_zz_561}}}; - assign _zz_552 = 32'h00004048; - assign _zz_553 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_554 = 32'h00000024; - assign _zz_555 = ((decode_INSTRUCTION & _zz_562) == 32'h00000020); - assign _zz_556 = {(_zz_563 == _zz_564),{_zz_565,_zz_566}}; - assign _zz_557 = ((decode_INSTRUCTION & _zz_567) == 32'h00000008); - assign _zz_558 = 1'b0; - assign _zz_559 = ((_zz_568 == _zz_569) != 1'b0); - assign _zz_560 = ({_zz_570,_zz_571} != 6'h0); - assign _zz_561 = {(_zz_572 != _zz_573),{_zz_574,{_zz_575,_zz_576}}}; - assign _zz_562 = 32'h00000034; - assign _zz_563 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_564 = 32'h00000020; - assign _zz_565 = ((decode_INSTRUCTION & _zz_577) == 32'h08000020); - assign _zz_566 = ((decode_INSTRUCTION & _zz_578) == 32'h00000020); - assign _zz_567 = 32'h10000008; - assign _zz_568 = (decode_INSTRUCTION & 32'h10000008); - assign _zz_569 = 32'h10000008; - assign _zz_570 = (_zz_579 == _zz_580); - assign _zz_571 = {_zz_581,{_zz_582,_zz_583}}; - assign _zz_572 = {_zz_584,{_zz_585,_zz_586}}; - assign _zz_573 = 3'b000; - assign _zz_574 = ({_zz_587,_zz_588} != 5'h0); - assign _zz_575 = (_zz_589 != _zz_590); - assign _zz_576 = {_zz_591,{_zz_592,_zz_593}}; - assign _zz_577 = 32'h08000070; - assign _zz_578 = 32'h10000070; - assign _zz_579 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_580 = 32'h00002040; - assign _zz_581 = ((decode_INSTRUCTION & _zz_594) == 32'h00001040); - assign _zz_582 = (_zz_595 == _zz_596); - assign _zz_583 = {_zz_597,{_zz_598,_zz_599}}; - assign _zz_584 = ((decode_INSTRUCTION & _zz_600) == 32'h08000020); - assign _zz_585 = (_zz_601 == _zz_602); - assign _zz_586 = (_zz_603 == _zz_604); - assign _zz_587 = (_zz_605 == _zz_606); - assign _zz_588 = {_zz_607,{_zz_608,_zz_609}}; - assign _zz_589 = {_zz_109,{_zz_610,_zz_611}}; - assign _zz_590 = 5'h0; - assign _zz_591 = ({_zz_612,_zz_613} != 7'h0); - assign _zz_592 = (_zz_614 != _zz_615); - assign _zz_593 = {_zz_616,{_zz_617,_zz_618}}; - assign _zz_594 = 32'h00001040; - assign _zz_595 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_596 = 32'h00000040; - assign _zz_597 = ((decode_INSTRUCTION & _zz_619) == 32'h00000040); - assign _zz_598 = (_zz_620 == _zz_621); - assign _zz_599 = (_zz_622 == _zz_623); - assign _zz_600 = 32'h08000020; - assign _zz_601 = (decode_INSTRUCTION & 32'h10000020); - assign _zz_602 = 32'h00000020; - assign _zz_603 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_604 = 32'h00000020; - assign _zz_605 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_606 = 32'h00000040; - assign _zz_607 = ((decode_INSTRUCTION & _zz_624) == 32'h00004020); - assign _zz_608 = (_zz_625 == _zz_626); - assign _zz_609 = {_zz_109,_zz_627}; - assign _zz_610 = (_zz_628 == _zz_629); - assign _zz_611 = {_zz_630,{_zz_631,_zz_632}}; - assign _zz_612 = _zz_106; - assign _zz_613 = {_zz_633,{_zz_634,_zz_635}}; - assign _zz_614 = {_zz_108,_zz_636}; - assign _zz_615 = 2'b00; - assign _zz_616 = ({_zz_637,_zz_638} != 2'b00); - assign _zz_617 = (_zz_639 != _zz_640); - assign _zz_618 = {_zz_641,{_zz_642,_zz_643}}; - assign _zz_619 = 32'h02100040; - assign _zz_620 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_621 = 32'h0; - assign _zz_622 = (decode_INSTRUCTION & 32'h18002008); - assign _zz_623 = 32'h10002008; - assign _zz_624 = 32'h00004020; - assign _zz_625 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_626 = 32'h00000010; - assign _zz_627 = ((decode_INSTRUCTION & _zz_644) == 32'h00000020); - assign _zz_628 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_629 = 32'h00002010; - assign _zz_630 = ((decode_INSTRUCTION & _zz_645) == 32'h00000010); - assign _zz_631 = (_zz_646 == _zz_647); - assign _zz_632 = (_zz_648 == _zz_649); - assign _zz_633 = ((decode_INSTRUCTION & _zz_650) == 32'h00001010); - assign _zz_634 = (_zz_651 == _zz_652); - assign _zz_635 = {_zz_653,{_zz_654,_zz_655}}; - assign _zz_636 = ((decode_INSTRUCTION & _zz_656) == 32'h00000020); - assign _zz_637 = _zz_108; - assign _zz_638 = (_zz_657 == _zz_658); - assign _zz_639 = (_zz_659 == _zz_660); - assign _zz_640 = 1'b0; - assign _zz_641 = (_zz_661 != 1'b0); - assign _zz_642 = (_zz_662 != _zz_663); - assign _zz_643 = {_zz_664,{_zz_665,_zz_666}}; - assign _zz_644 = 32'h02000028; - assign _zz_645 = 32'h00001030; - assign _zz_646 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_647 = 32'h00000020; - assign _zz_648 = (decode_INSTRUCTION & 32'h02002068); - assign _zz_649 = 32'h00002020; - assign _zz_650 = 32'h00001010; - assign _zz_651 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_652 = 32'h00002010; - assign _zz_653 = ((decode_INSTRUCTION & _zz_667) == 32'h00002008); - assign _zz_654 = (_zz_668 == _zz_669); - assign _zz_655 = {_zz_109,_zz_670}; - assign _zz_656 = 32'h00000070; - assign _zz_657 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_658 = 32'h0; - assign _zz_659 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_660 = 32'h00004010; - assign _zz_661 = ((decode_INSTRUCTION & _zz_671) == 32'h00002010); - assign _zz_662 = {_zz_672,{_zz_673,_zz_674}}; - assign _zz_663 = 5'h0; - assign _zz_664 = ({_zz_675,_zz_676} != 2'b00); - assign _zz_665 = (_zz_677 != _zz_678); - assign _zz_666 = {_zz_679,{_zz_680,_zz_681}}; - assign _zz_667 = 32'h00002008; - assign _zz_668 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_669 = 32'h00000010; - assign _zz_670 = ((decode_INSTRUCTION & _zz_682) == 32'h0); - assign _zz_671 = 32'h00006014; - assign _zz_672 = ((decode_INSTRUCTION & _zz_683) == 32'h0); - assign _zz_673 = (_zz_684 == _zz_685); - assign _zz_674 = {_zz_686,{_zz_687,_zz_688}}; - assign _zz_675 = _zz_107; - assign _zz_676 = (_zz_689 == _zz_690); - assign _zz_677 = {_zz_691,{_zz_692,_zz_693}}; - assign _zz_678 = 3'b000; - assign _zz_679 = ({_zz_694,_zz_695} != 3'b000); - assign _zz_680 = (_zz_696 != _zz_697); - assign _zz_681 = (_zz_698 != _zz_699); - assign _zz_682 = 32'h00000028; - assign _zz_683 = 32'h00000044; - assign _zz_684 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_685 = 32'h0; - assign _zz_686 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_687 = ((decode_INSTRUCTION & _zz_700) == 32'h00001000); - assign _zz_688 = _zz_107; - assign _zz_689 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_468 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_469 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_470 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_471 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_472 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_473 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_474 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_475 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_476 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_477 = (iBus_cmd_payload_address >>> 5); + assign _zz_478 = 1'b1; + assign _zz_479 = 1'b1; + assign _zz_480 = {_zz_60,{_zz_62,_zz_61}}; + assign _zz_481 = 32'h0000107f; + assign _zz_482 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_483 = 32'h00002073; + assign _zz_484 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_485 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_486 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_487) == 32'h00000003),{(_zz_488 == _zz_489),{_zz_490,{_zz_491,_zz_492}}}}}}; + assign _zz_487 = 32'h0000505f; + assign _zz_488 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_489 = 32'h00000063; + assign _zz_490 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_491 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_492 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_493) == 32'h0000500f),{(_zz_494 == _zz_495),{_zz_496,{_zz_497,_zz_498}}}}}}; + assign _zz_493 = 32'h01f0707f; + assign _zz_494 = (decode_INSTRUCTION & 32'hbc00707f); + assign _zz_495 = 32'h00005013; + assign _zz_496 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); + assign _zz_497 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_498 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_499) == 32'h12000073),{(_zz_500 == _zz_501),{_zz_502,_zz_503}}}}}; + assign _zz_499 = 32'hfe007fff; + assign _zz_500 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_501 = 32'h10200073; + assign _zz_502 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_503 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_504 = decode_INSTRUCTION[31]; + assign _zz_505 = decode_INSTRUCTION[31]; + assign _zz_506 = decode_INSTRUCTION[7]; + assign _zz_507 = 32'h10103050; + assign _zz_508 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_509 = 1'b0; + assign _zz_510 = (((decode_INSTRUCTION & _zz_513) == 32'h02000030) != 1'b0); + assign _zz_511 = ({_zz_514,_zz_515} != 2'b00); + assign _zz_512 = {(_zz_516 != 1'b0),{(_zz_517 != _zz_518),{_zz_519,{_zz_520,_zz_521}}}}; + assign _zz_513 = 32'h02004074; + assign _zz_514 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz_515 = ((decode_INSTRUCTION & 32'h12203050) == 32'h10000050); + assign _zz_516 = ((decode_INSTRUCTION & 32'h02103050) == 32'h00000050); + assign _zz_517 = {(_zz_522 == _zz_523),(_zz_524 == _zz_525)}; + assign _zz_518 = 2'b00; + assign _zz_519 = ({_zz_106,_zz_526} != 2'b00); + assign _zz_520 = (_zz_527 != 1'b0); + assign _zz_521 = {(_zz_528 != _zz_529),{_zz_530,{_zz_531,_zz_532}}}; + assign _zz_522 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_523 = 32'h00001050; + assign _zz_524 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_525 = 32'h00002050; + assign _zz_526 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_527 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_528 = {(_zz_533 == _zz_534),(_zz_535 == _zz_536)}; + assign _zz_529 = 2'b00; + assign _zz_530 = ({_zz_537,{_zz_538,_zz_539}} != 3'b000); + assign _zz_531 = (_zz_540 != 1'b0); + assign _zz_532 = {(_zz_541 != _zz_542),{_zz_543,{_zz_544,_zz_545}}}; + assign _zz_533 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_534 = 32'h00005010; + assign _zz_535 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_536 = 32'h00005020; + assign _zz_537 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_538 = ((decode_INSTRUCTION & _zz_546) == 32'h00001010); + assign _zz_539 = ((decode_INSTRUCTION & _zz_547) == 32'h00001010); + assign _zz_540 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_541 = ((decode_INSTRUCTION & _zz_548) == 32'h00002000); + assign _zz_542 = 1'b0; + assign _zz_543 = ({_zz_549,_zz_550} != 2'b00); + assign _zz_544 = (_zz_551 != 1'b0); + assign _zz_545 = {(_zz_552 != _zz_553),{_zz_554,{_zz_555,_zz_556}}}; + assign _zz_546 = 32'h00007034; + assign _zz_547 = 32'h02007054; + assign _zz_548 = 32'h00003000; + assign _zz_549 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_550 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_551 = ((decode_INSTRUCTION & 32'h02003050) == 32'h02000050); + assign _zz_552 = ((decode_INSTRUCTION & _zz_557) == 32'h00004008); + assign _zz_553 = 1'b0; + assign _zz_554 = ((_zz_558 == _zz_559) != 1'b0); + assign _zz_555 = ({_zz_560,_zz_561} != 4'b0000); + assign _zz_556 = {(_zz_562 != _zz_563),{_zz_564,{_zz_565,_zz_566}}}; + assign _zz_557 = 32'h00004048; + assign _zz_558 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_559 = 32'h00000024; + assign _zz_560 = ((decode_INSTRUCTION & _zz_567) == 32'h00000020); + assign _zz_561 = {(_zz_568 == _zz_569),{_zz_570,_zz_571}}; + assign _zz_562 = ((decode_INSTRUCTION & _zz_572) == 32'h00000008); + assign _zz_563 = 1'b0; + assign _zz_564 = ((_zz_573 == _zz_574) != 1'b0); + assign _zz_565 = ({_zz_575,_zz_576} != 6'h0); + assign _zz_566 = {(_zz_577 != _zz_578),{_zz_579,{_zz_580,_zz_581}}}; + assign _zz_567 = 32'h00000034; + assign _zz_568 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_569 = 32'h00000020; + assign _zz_570 = ((decode_INSTRUCTION & _zz_582) == 32'h08000020); + assign _zz_571 = ((decode_INSTRUCTION & _zz_583) == 32'h00000020); + assign _zz_572 = 32'h10000008; + assign _zz_573 = (decode_INSTRUCTION & 32'h10000008); + assign _zz_574 = 32'h10000008; + assign _zz_575 = (_zz_584 == _zz_585); + assign _zz_576 = {_zz_586,{_zz_587,_zz_588}}; + assign _zz_577 = {_zz_589,{_zz_590,_zz_591}}; + assign _zz_578 = 3'b000; + assign _zz_579 = ({_zz_592,_zz_593} != 5'h0); + assign _zz_580 = (_zz_594 != _zz_595); + assign _zz_581 = {_zz_596,{_zz_597,_zz_598}}; + assign _zz_582 = 32'h08000070; + assign _zz_583 = 32'h10000070; + assign _zz_584 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_585 = 32'h00002040; + assign _zz_586 = ((decode_INSTRUCTION & _zz_599) == 32'h00001040); + assign _zz_587 = (_zz_600 == _zz_601); + assign _zz_588 = {_zz_602,{_zz_603,_zz_604}}; + assign _zz_589 = ((decode_INSTRUCTION & _zz_605) == 32'h08000020); + assign _zz_590 = (_zz_606 == _zz_607); + assign _zz_591 = (_zz_608 == _zz_609); + assign _zz_592 = (_zz_610 == _zz_611); + assign _zz_593 = {_zz_612,{_zz_613,_zz_614}}; + assign _zz_594 = {_zz_109,{_zz_615,_zz_616}}; + assign _zz_595 = 5'h0; + assign _zz_596 = ({_zz_617,_zz_618} != 7'h0); + assign _zz_597 = (_zz_619 != _zz_620); + assign _zz_598 = {_zz_621,{_zz_622,_zz_623}}; + assign _zz_599 = 32'h00001040; + assign _zz_600 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_601 = 32'h00000040; + assign _zz_602 = ((decode_INSTRUCTION & _zz_624) == 32'h00000040); + assign _zz_603 = (_zz_625 == _zz_626); + assign _zz_604 = (_zz_627 == _zz_628); + assign _zz_605 = 32'h08000020; + assign _zz_606 = (decode_INSTRUCTION & 32'h10000020); + assign _zz_607 = 32'h00000020; + assign _zz_608 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_609 = 32'h00000020; + assign _zz_610 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_611 = 32'h00000040; + assign _zz_612 = ((decode_INSTRUCTION & _zz_629) == 32'h00004020); + assign _zz_613 = (_zz_630 == _zz_631); + assign _zz_614 = {_zz_109,_zz_632}; + assign _zz_615 = (_zz_633 == _zz_634); + assign _zz_616 = {_zz_635,{_zz_636,_zz_637}}; + assign _zz_617 = _zz_106; + assign _zz_618 = {_zz_638,{_zz_639,_zz_640}}; + assign _zz_619 = {_zz_108,_zz_641}; + assign _zz_620 = 2'b00; + assign _zz_621 = ({_zz_642,_zz_643} != 2'b00); + assign _zz_622 = (_zz_644 != _zz_645); + assign _zz_623 = {_zz_646,{_zz_647,_zz_648}}; + assign _zz_624 = 32'h02100040; + assign _zz_625 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_626 = 32'h0; + assign _zz_627 = (decode_INSTRUCTION & 32'h18002008); + assign _zz_628 = 32'h10002008; + assign _zz_629 = 32'h00004020; + assign _zz_630 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_631 = 32'h00000010; + assign _zz_632 = ((decode_INSTRUCTION & _zz_649) == 32'h00000020); + assign _zz_633 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_634 = 32'h00002010; + assign _zz_635 = ((decode_INSTRUCTION & _zz_650) == 32'h00000010); + assign _zz_636 = (_zz_651 == _zz_652); + assign _zz_637 = (_zz_653 == _zz_654); + assign _zz_638 = ((decode_INSTRUCTION & _zz_655) == 32'h00001010); + assign _zz_639 = (_zz_656 == _zz_657); + assign _zz_640 = {_zz_658,{_zz_659,_zz_660}}; + assign _zz_641 = ((decode_INSTRUCTION & _zz_661) == 32'h00000020); + assign _zz_642 = _zz_108; + assign _zz_643 = (_zz_662 == _zz_663); + assign _zz_644 = (_zz_664 == _zz_665); + assign _zz_645 = 1'b0; + assign _zz_646 = (_zz_666 != 1'b0); + assign _zz_647 = (_zz_667 != _zz_668); + assign _zz_648 = {_zz_669,{_zz_670,_zz_671}}; + assign _zz_649 = 32'h02000028; + assign _zz_650 = 32'h00001030; + assign _zz_651 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_652 = 32'h00000020; + assign _zz_653 = (decode_INSTRUCTION & 32'h02002068); + assign _zz_654 = 32'h00002020; + assign _zz_655 = 32'h00001010; + assign _zz_656 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_657 = 32'h00002010; + assign _zz_658 = ((decode_INSTRUCTION & _zz_672) == 32'h00002008); + assign _zz_659 = (_zz_673 == _zz_674); + assign _zz_660 = {_zz_109,_zz_675}; + assign _zz_661 = 32'h00000070; + assign _zz_662 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_663 = 32'h0; + assign _zz_664 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_665 = 32'h00004010; + assign _zz_666 = ((decode_INSTRUCTION & _zz_676) == 32'h00002010); + assign _zz_667 = {_zz_677,{_zz_678,_zz_679}}; + assign _zz_668 = 5'h0; + assign _zz_669 = ({_zz_680,_zz_681} != 2'b00); + assign _zz_670 = (_zz_682 != _zz_683); + assign _zz_671 = {_zz_684,{_zz_685,_zz_686}}; + assign _zz_672 = 32'h00002008; + assign _zz_673 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_674 = 32'h00000010; + assign _zz_675 = ((decode_INSTRUCTION & _zz_687) == 32'h0); + assign _zz_676 = 32'h00006014; + assign _zz_677 = ((decode_INSTRUCTION & _zz_688) == 32'h0); + assign _zz_678 = (_zz_689 == _zz_690); + assign _zz_679 = {_zz_691,{_zz_692,_zz_693}}; + assign _zz_680 = _zz_107; + assign _zz_681 = (_zz_694 == _zz_695); + assign _zz_682 = {_zz_696,{_zz_697,_zz_698}}; + assign _zz_683 = 3'b000; + assign _zz_684 = ({_zz_699,_zz_700} != 3'b000); + assign _zz_685 = (_zz_701 != _zz_702); + assign _zz_686 = (_zz_703 != _zz_704); + assign _zz_687 = 32'h00000028; + assign _zz_688 = 32'h00000044; + assign _zz_689 = (decode_INSTRUCTION & 32'h00000018); assign _zz_690 = 32'h0; - assign _zz_691 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_692 = ((decode_INSTRUCTION & _zz_701) == 32'h00002010); - assign _zz_693 = ((decode_INSTRUCTION & _zz_702) == 32'h40000030); - assign _zz_694 = _zz_106; - assign _zz_695 = {_zz_105,(_zz_703 == _zz_704)}; - assign _zz_696 = {_zz_105,(_zz_705 == _zz_706)}; - assign _zz_697 = 2'b00; - assign _zz_698 = ((decode_INSTRUCTION & _zz_707) == 32'h00001008); - assign _zz_699 = 1'b0; - assign _zz_700 = 32'h00005004; - assign _zz_701 = 32'h00002014; - assign _zz_702 = 32'h40000034; - assign _zz_703 = (decode_INSTRUCTION & 32'h00002014); - assign _zz_704 = 32'h00000004; - assign _zz_705 = (decode_INSTRUCTION & 32'h0000004c); - assign _zz_706 = 32'h00000004; - assign _zz_707 = 32'h00005048; - assign _zz_708 = execute_INSTRUCTION[31]; - assign _zz_709 = execute_INSTRUCTION[31]; - assign _zz_710 = execute_INSTRUCTION[7]; - assign _zz_711 = 32'h0; + assign _zz_691 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_692 = ((decode_INSTRUCTION & _zz_705) == 32'h00001000); + assign _zz_693 = _zz_107; + assign _zz_694 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_695 = 32'h0; + assign _zz_696 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_697 = ((decode_INSTRUCTION & _zz_706) == 32'h00002010); + assign _zz_698 = ((decode_INSTRUCTION & _zz_707) == 32'h40000030); + assign _zz_699 = _zz_106; + assign _zz_700 = {_zz_105,(_zz_708 == _zz_709)}; + assign _zz_701 = {_zz_105,(_zz_710 == _zz_711)}; + assign _zz_702 = 2'b00; + assign _zz_703 = ((decode_INSTRUCTION & _zz_712) == 32'h00001008); + assign _zz_704 = 1'b0; + assign _zz_705 = 32'h00005004; + assign _zz_706 = 32'h00002014; + assign _zz_707 = 32'h40000034; + assign _zz_708 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_709 = 32'h00000004; + assign _zz_710 = (decode_INSTRUCTION & 32'h0000004c); + assign _zz_711 = 32'h00000004; + assign _zz_712 = 32'h00005048; + assign _zz_713 = execute_INSTRUCTION[31]; + assign _zz_714 = execute_INSTRUCTION[31]; + assign _zz_715 = execute_INSTRUCTION[7]; + assign _zz_716 = 32'h0; always @ (posedge clk) begin - if(_zz_473) begin - _zz_238 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_478) begin + _zz_243 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_474) begin - _zz_239 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_479) begin + _zz_244 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -2220,13 +2215,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_203 ), //i - .io_cpu_prefetch_isValid (_zz_204 ), //i + .io_flush (_zz_208 ), //i + .io_cpu_prefetch_isValid (_zz_209 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_205 ), //i - .io_cpu_fetch_isStuck (_zz_206 ), //i - .io_cpu_fetch_isRemoved (_zz_207 ), //i + .io_cpu_fetch_isValid (_zz_210 ), //i + .io_cpu_fetch_isStuck (_zz_211 ), //i + .io_cpu_fetch_isRemoved (_zz_212 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -2247,8 +2242,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_208 ), //i - .io_cpu_decode_isStuck (_zz_209 ), //i + .io_cpu_decode_isValid (_zz_213 ), //i + .io_cpu_decode_isStuck (_zz_214 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -2256,8 +2251,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_210 ), //i - .io_cpu_fill_valid (_zz_211 ), //i + .io_cpu_decode_isUser (_zz_215 ), //i + .io_cpu_fill_valid (_zz_216 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -2266,30 +2261,30 @@ module VexRiscv ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_169[2:0] ), //i + ._zz_9 (_zz_174[2:0] ), //i ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_212 ), //i - .io_cpu_execute_address (_zz_213[31:0] ), //i + .io_cpu_execute_isValid (_zz_217 ), //i + .io_cpu_execute_address (_zz_218[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (_zz_214 ), //i - .io_cpu_execute_args_data (_zz_215[31:0] ), //i - .io_cpu_execute_args_size (_zz_216[1:0] ), //i - .io_cpu_execute_args_isLrsc (_zz_217 ), //i - .io_cpu_execute_args_isAmo (_zz_218 ), //i - .io_cpu_execute_args_amoCtrl_swap (_zz_219 ), //i - .io_cpu_execute_args_amoCtrl_alu (_zz_220[2:0] ), //i + .io_cpu_execute_args_wr (_zz_219 ), //i + .io_cpu_execute_args_data (_zz_220[31:0] ), //i + .io_cpu_execute_args_size (_zz_221[1:0] ), //i + .io_cpu_execute_args_isLrsc (_zz_222 ), //i + .io_cpu_execute_args_isAmo (_zz_223 ), //i + .io_cpu_execute_args_amoCtrl_swap (_zz_224 ), //i + .io_cpu_execute_args_amoCtrl_alu (_zz_225[2:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_221 ), //i + .io_cpu_memory_isValid (_zz_226 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_222[31:0] ), //i + .io_cpu_memory_address (_zz_227[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_223 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_228 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -2305,31 +2300,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i - .io_cpu_writeBack_isValid (_zz_224 ), //i + .io_cpu_writeBack_isValid (_zz_229 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_225 ), //i + .io_cpu_writeBack_isUser (_zz_230 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_226[31:0] ), //i + .io_cpu_writeBack_address (_zz_231[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_227 ), //i - .io_cpu_writeBack_fence_SR (_zz_228 ), //i - .io_cpu_writeBack_fence_SO (_zz_229 ), //i - .io_cpu_writeBack_fence_SI (_zz_230 ), //i - .io_cpu_writeBack_fence_PW (_zz_231 ), //i - .io_cpu_writeBack_fence_PR (_zz_232 ), //i - .io_cpu_writeBack_fence_PO (_zz_233 ), //i - .io_cpu_writeBack_fence_PI (_zz_234 ), //i - .io_cpu_writeBack_fence_FM (_zz_235[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_232 ), //i + .io_cpu_writeBack_fence_SR (_zz_233 ), //i + .io_cpu_writeBack_fence_SO (_zz_234 ), //i + .io_cpu_writeBack_fence_SI (_zz_235 ), //i + .io_cpu_writeBack_fence_PW (_zz_236 ), //i + .io_cpu_writeBack_fence_PR (_zz_237 ), //i + .io_cpu_writeBack_fence_PO (_zz_238 ), //i + .io_cpu_writeBack_fence_PI (_zz_239 ), //i + .io_cpu_writeBack_fence_FM (_zz_240[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_236 ), //i + .io_cpu_flush_valid (_zz_241 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_237 ), //i + .io_mem_cmd_ready (_zz_242 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -2345,21 +2340,21 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_475) + case(_zz_480) 3'b000 : begin - _zz_240 = DBusCachedPlugin_redoBranch_payload; + _zz_245 = DBusCachedPlugin_redoBranch_payload; end 3'b001 : begin - _zz_240 = CsrPlugin_jumpInterface_payload; + _zz_245 = CsrPlugin_jumpInterface_payload; end 3'b010 : begin - _zz_240 = BranchPlugin_jumpInterface_payload; + _zz_245 = BranchPlugin_jumpInterface_payload; end 3'b011 : begin - _zz_240 = CsrPlugin_redoInterface_payload; + _zz_245 = CsrPlugin_redoInterface_payload; end default : begin - _zz_240 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_245 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2367,56 +2362,56 @@ module VexRiscv ( always @(*) begin case(_zz_93) 2'b00 : begin - _zz_241 = MmuPlugin_ports_0_cache_0_valid; - _zz_242 = MmuPlugin_ports_0_cache_0_exception; - _zz_243 = MmuPlugin_ports_0_cache_0_superPage; - _zz_244 = MmuPlugin_ports_0_cache_0_virtualAddress_0; - _zz_245 = MmuPlugin_ports_0_cache_0_virtualAddress_1; - _zz_246 = MmuPlugin_ports_0_cache_0_physicalAddress_0; - _zz_247 = MmuPlugin_ports_0_cache_0_physicalAddress_1; - _zz_248 = MmuPlugin_ports_0_cache_0_allowRead; - _zz_249 = MmuPlugin_ports_0_cache_0_allowWrite; - _zz_250 = MmuPlugin_ports_0_cache_0_allowExecute; - _zz_251 = MmuPlugin_ports_0_cache_0_allowUser; + _zz_246 = MmuPlugin_ports_0_cache_0_valid; + _zz_247 = MmuPlugin_ports_0_cache_0_exception; + _zz_248 = MmuPlugin_ports_0_cache_0_superPage; + _zz_249 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_250 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_251 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_252 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_253 = MmuPlugin_ports_0_cache_0_allowRead; + _zz_254 = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_255 = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_256 = MmuPlugin_ports_0_cache_0_allowUser; end 2'b01 : begin - _zz_241 = MmuPlugin_ports_0_cache_1_valid; - _zz_242 = MmuPlugin_ports_0_cache_1_exception; - _zz_243 = MmuPlugin_ports_0_cache_1_superPage; - _zz_244 = MmuPlugin_ports_0_cache_1_virtualAddress_0; - _zz_245 = MmuPlugin_ports_0_cache_1_virtualAddress_1; - _zz_246 = MmuPlugin_ports_0_cache_1_physicalAddress_0; - _zz_247 = MmuPlugin_ports_0_cache_1_physicalAddress_1; - _zz_248 = MmuPlugin_ports_0_cache_1_allowRead; - _zz_249 = MmuPlugin_ports_0_cache_1_allowWrite; - _zz_250 = MmuPlugin_ports_0_cache_1_allowExecute; - _zz_251 = MmuPlugin_ports_0_cache_1_allowUser; + _zz_246 = MmuPlugin_ports_0_cache_1_valid; + _zz_247 = MmuPlugin_ports_0_cache_1_exception; + _zz_248 = MmuPlugin_ports_0_cache_1_superPage; + _zz_249 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_250 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_251 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_252 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_253 = MmuPlugin_ports_0_cache_1_allowRead; + _zz_254 = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_255 = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_256 = MmuPlugin_ports_0_cache_1_allowUser; end 2'b10 : begin - _zz_241 = MmuPlugin_ports_0_cache_2_valid; - _zz_242 = MmuPlugin_ports_0_cache_2_exception; - _zz_243 = MmuPlugin_ports_0_cache_2_superPage; - _zz_244 = MmuPlugin_ports_0_cache_2_virtualAddress_0; - _zz_245 = MmuPlugin_ports_0_cache_2_virtualAddress_1; - _zz_246 = MmuPlugin_ports_0_cache_2_physicalAddress_0; - _zz_247 = MmuPlugin_ports_0_cache_2_physicalAddress_1; - _zz_248 = MmuPlugin_ports_0_cache_2_allowRead; - _zz_249 = MmuPlugin_ports_0_cache_2_allowWrite; - _zz_250 = MmuPlugin_ports_0_cache_2_allowExecute; - _zz_251 = MmuPlugin_ports_0_cache_2_allowUser; + _zz_246 = MmuPlugin_ports_0_cache_2_valid; + _zz_247 = MmuPlugin_ports_0_cache_2_exception; + _zz_248 = MmuPlugin_ports_0_cache_2_superPage; + _zz_249 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_250 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_251 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_252 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_253 = MmuPlugin_ports_0_cache_2_allowRead; + _zz_254 = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_255 = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_256 = MmuPlugin_ports_0_cache_2_allowUser; end default : begin - _zz_241 = MmuPlugin_ports_0_cache_3_valid; - _zz_242 = MmuPlugin_ports_0_cache_3_exception; - _zz_243 = MmuPlugin_ports_0_cache_3_superPage; - _zz_244 = MmuPlugin_ports_0_cache_3_virtualAddress_0; - _zz_245 = MmuPlugin_ports_0_cache_3_virtualAddress_1; - _zz_246 = MmuPlugin_ports_0_cache_3_physicalAddress_0; - _zz_247 = MmuPlugin_ports_0_cache_3_physicalAddress_1; - _zz_248 = MmuPlugin_ports_0_cache_3_allowRead; - _zz_249 = MmuPlugin_ports_0_cache_3_allowWrite; - _zz_250 = MmuPlugin_ports_0_cache_3_allowExecute; - _zz_251 = MmuPlugin_ports_0_cache_3_allowUser; + _zz_246 = MmuPlugin_ports_0_cache_3_valid; + _zz_247 = MmuPlugin_ports_0_cache_3_exception; + _zz_248 = MmuPlugin_ports_0_cache_3_superPage; + _zz_249 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_250 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_251 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_252 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_253 = MmuPlugin_ports_0_cache_3_allowRead; + _zz_254 = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_255 = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_256 = MmuPlugin_ports_0_cache_3_allowUser; end endcase end @@ -2424,56 +2419,56 @@ module VexRiscv ( always @(*) begin case(_zz_97) 2'b00 : begin - _zz_252 = MmuPlugin_ports_1_cache_0_valid; - _zz_253 = MmuPlugin_ports_1_cache_0_exception; - _zz_254 = MmuPlugin_ports_1_cache_0_superPage; - _zz_255 = MmuPlugin_ports_1_cache_0_virtualAddress_0; - _zz_256 = MmuPlugin_ports_1_cache_0_virtualAddress_1; - _zz_257 = MmuPlugin_ports_1_cache_0_physicalAddress_0; - _zz_258 = MmuPlugin_ports_1_cache_0_physicalAddress_1; - _zz_259 = MmuPlugin_ports_1_cache_0_allowRead; - _zz_260 = MmuPlugin_ports_1_cache_0_allowWrite; - _zz_261 = MmuPlugin_ports_1_cache_0_allowExecute; - _zz_262 = MmuPlugin_ports_1_cache_0_allowUser; + _zz_257 = MmuPlugin_ports_1_cache_0_valid; + _zz_258 = MmuPlugin_ports_1_cache_0_exception; + _zz_259 = MmuPlugin_ports_1_cache_0_superPage; + _zz_260 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_261 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_262 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_263 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_264 = MmuPlugin_ports_1_cache_0_allowRead; + _zz_265 = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_266 = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_267 = MmuPlugin_ports_1_cache_0_allowUser; end 2'b01 : begin - _zz_252 = MmuPlugin_ports_1_cache_1_valid; - _zz_253 = MmuPlugin_ports_1_cache_1_exception; - _zz_254 = MmuPlugin_ports_1_cache_1_superPage; - _zz_255 = MmuPlugin_ports_1_cache_1_virtualAddress_0; - _zz_256 = MmuPlugin_ports_1_cache_1_virtualAddress_1; - _zz_257 = MmuPlugin_ports_1_cache_1_physicalAddress_0; - _zz_258 = MmuPlugin_ports_1_cache_1_physicalAddress_1; - _zz_259 = MmuPlugin_ports_1_cache_1_allowRead; - _zz_260 = MmuPlugin_ports_1_cache_1_allowWrite; - _zz_261 = MmuPlugin_ports_1_cache_1_allowExecute; - _zz_262 = MmuPlugin_ports_1_cache_1_allowUser; + _zz_257 = MmuPlugin_ports_1_cache_1_valid; + _zz_258 = MmuPlugin_ports_1_cache_1_exception; + _zz_259 = MmuPlugin_ports_1_cache_1_superPage; + _zz_260 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_261 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_262 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_263 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_264 = MmuPlugin_ports_1_cache_1_allowRead; + _zz_265 = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_266 = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_267 = MmuPlugin_ports_1_cache_1_allowUser; end 2'b10 : begin - _zz_252 = MmuPlugin_ports_1_cache_2_valid; - _zz_253 = MmuPlugin_ports_1_cache_2_exception; - _zz_254 = MmuPlugin_ports_1_cache_2_superPage; - _zz_255 = MmuPlugin_ports_1_cache_2_virtualAddress_0; - _zz_256 = MmuPlugin_ports_1_cache_2_virtualAddress_1; - _zz_257 = MmuPlugin_ports_1_cache_2_physicalAddress_0; - _zz_258 = MmuPlugin_ports_1_cache_2_physicalAddress_1; - _zz_259 = MmuPlugin_ports_1_cache_2_allowRead; - _zz_260 = MmuPlugin_ports_1_cache_2_allowWrite; - _zz_261 = MmuPlugin_ports_1_cache_2_allowExecute; - _zz_262 = MmuPlugin_ports_1_cache_2_allowUser; + _zz_257 = MmuPlugin_ports_1_cache_2_valid; + _zz_258 = MmuPlugin_ports_1_cache_2_exception; + _zz_259 = MmuPlugin_ports_1_cache_2_superPage; + _zz_260 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_261 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_262 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_263 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_264 = MmuPlugin_ports_1_cache_2_allowRead; + _zz_265 = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_266 = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_267 = MmuPlugin_ports_1_cache_2_allowUser; end default : begin - _zz_252 = MmuPlugin_ports_1_cache_3_valid; - _zz_253 = MmuPlugin_ports_1_cache_3_exception; - _zz_254 = MmuPlugin_ports_1_cache_3_superPage; - _zz_255 = MmuPlugin_ports_1_cache_3_virtualAddress_0; - _zz_256 = MmuPlugin_ports_1_cache_3_virtualAddress_1; - _zz_257 = MmuPlugin_ports_1_cache_3_physicalAddress_0; - _zz_258 = MmuPlugin_ports_1_cache_3_physicalAddress_1; - _zz_259 = MmuPlugin_ports_1_cache_3_allowRead; - _zz_260 = MmuPlugin_ports_1_cache_3_allowWrite; - _zz_261 = MmuPlugin_ports_1_cache_3_allowExecute; - _zz_262 = MmuPlugin_ports_1_cache_3_allowUser; + _zz_257 = MmuPlugin_ports_1_cache_3_valid; + _zz_258 = MmuPlugin_ports_1_cache_3_exception; + _zz_259 = MmuPlugin_ports_1_cache_3_superPage; + _zz_260 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_261 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_262 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_263 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_264 = MmuPlugin_ports_1_cache_3_allowRead; + _zz_265 = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_266 = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_267 = MmuPlugin_ports_1_cache_3_allowUser; end endcase end @@ -3175,7 +3170,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_325) + $signed(_zz_333)); + assign memory_MUL_LOW = ($signed(_zz_330) + $signed(_zz_338)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -3183,43 +3178,43 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_335; + assign execute_SHIFT_RIGHT = _zz_340; assign execute_REGFILE_WRITE_DATA = _zz_119; assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_213[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_218[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_337[0]; - assign decode_IS_RS1_SIGNED = _zz_338[0]; - assign decode_IS_DIV = _zz_339[0]; + assign decode_IS_RS2_SIGNED = _zz_342[0]; + assign decode_IS_RS1_SIGNED = _zz_343[0]; + assign decode_IS_DIV = _zz_344[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_340[0]; + assign decode_IS_MUL = _zz_345[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_341[0]; + assign decode_IS_CSR = _zz_346[0]; assign _zz_8 = _zz_9; assign _zz_10 = _zz_11; assign decode_SHIFT_CTRL = _zz_12; assign _zz_13 = _zz_14; assign decode_ALU_BITWISE_CTRL = _zz_15; assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_342[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_347[0]; assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; - assign decode_IS_SFENCE_VMA = _zz_343[0]; - assign decode_MEMORY_MANAGMENT = _zz_344[0]; + assign decode_IS_SFENCE_VMA = _zz_348[0]; + assign decode_MEMORY_MANAGMENT = _zz_349[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_345[0]; + assign decode_MEMORY_WR = _zz_350[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_346[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_347[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_351[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_352[0]; assign decode_SRC2_CTRL = _zz_18; assign _zz_19 = _zz_20; assign decode_ALU_CTRL = _zz_21; @@ -3233,7 +3228,7 @@ module VexRiscv ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_348[0]; + assign decode_IS_EBREAK = _zz_353[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -3255,13 +3250,13 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_136; + assign execute_BRANCH_COND_RESULT = _zz_141; assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_349[0]; - assign decode_RS1_USE = _zz_350[0]; + assign decode_RS2_USE = _zz_354[0]; + assign decode_RS1_USE = _zz_355[0]; always @ (*) begin _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_263)begin + if(_zz_268)begin _zz_31 = execute_CsrPlugin_readData; end if(DBusCachedPlugin_forceDatapath)begin @@ -3277,28 +3272,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_130)begin + if((_zz_131 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_132; end end - if(_zz_264)begin - if(_zz_265)begin - if(_zz_129)begin + if(_zz_269)begin + if(_zz_270)begin + if(_zz_134)begin decode_RS2 = _zz_50; end end end - if(_zz_266)begin + if(_zz_271)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_131)begin + if(_zz_136)begin decode_RS2 = _zz_32; end end end - if(_zz_267)begin + if(_zz_272)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_133)begin + if(_zz_138)begin decode_RS2 = _zz_31; end end @@ -3307,28 +3302,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_130)begin + if((_zz_131 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_132; end end - if(_zz_264)begin - if(_zz_265)begin - if(_zz_128)begin + if(_zz_269)begin + if(_zz_270)begin + if(_zz_133)begin decode_RS1 = _zz_50; end end end - if(_zz_266)begin + if(_zz_271)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_130)begin + if(_zz_135)begin decode_RS1 = _zz_32; end end end - if(_zz_267)begin + if(_zz_272)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_132)begin + if(_zz_137)begin decode_RS1 = _zz_31; end end @@ -3350,7 +3345,7 @@ module VexRiscv ( end endcase end - if(_zz_268)begin + if(_zz_273)begin _zz_32 = memory_DivPlugin_div_result; end end @@ -3363,8 +3358,8 @@ module VexRiscv ( assign _zz_35 = execute_PC; assign execute_SRC2_CTRL = _zz_36; assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_351[0]; - assign decode_SRC_ADD_ZERO = _zz_352[0]; + assign decode_SRC_USE_SUB_LESS = _zz_356[0]; + assign decode_SRC_ADD_ZERO = _zz_357[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_38; @@ -3382,13 +3377,13 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_353[0]; + decode_REGFILE_WRITE_VALID = _zz_358[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_476) == 32'h00001073),{(_zz_477 == _zz_478),{_zz_479,{_zz_480,_zz_481}}}}}}} != 25'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_481) == 32'h00001073),{(_zz_482 == _zz_483),{_zz_484,{_zz_485,_zz_486}}}}}}} != 25'h0); assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; @@ -3398,12 +3393,12 @@ module VexRiscv ( _zz_50 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_324) + case(_zz_329) 2'b00 : begin - _zz_50 = _zz_410; + _zz_50 = _zz_415; end default : begin - _zz_50 = _zz_411; + _zz_50 = _zz_416; end endcase end @@ -3424,34 +3419,34 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_AMO = _zz_354[0]; - assign decode_MEMORY_LRSC = _zz_355[0]; - assign decode_MEMORY_ENABLE = _zz_356[0]; - assign decode_FLUSH_ALL = _zz_357[0]; + assign decode_MEMORY_AMO = _zz_359[0]; + assign decode_MEMORY_LRSC = _zz_360[0]; + assign decode_MEMORY_ENABLE = _zz_361[0]; + assign decode_FLUSH_ALL = _zz_362[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_269)begin + if(_zz_274)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_270)begin + if(_zz_275)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_271)begin + if(_zz_276)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_272)begin + if(_zz_277)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -3487,7 +3482,7 @@ module VexRiscv ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_169) + case(_zz_174) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -3501,7 +3496,7 @@ module VexRiscv ( if(MmuPlugin_dBusAccess_cmd_valid)begin decode_arbitration_haltByOther = 1'b1; end - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_128 || _zz_129)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -3514,7 +3509,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_273)begin + if(_zz_278)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3528,22 +3523,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_273)begin + if(_zz_278)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_236 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_241 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_274)begin + if(_zz_279)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_263)begin + if(_zz_268)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3555,7 +3550,7 @@ module VexRiscv ( if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_275)begin + if(_zz_280)begin execute_arbitration_haltByOther = 1'b1; end end @@ -3572,8 +3567,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_275)begin - if(_zz_276)begin + if(_zz_280)begin + if(_zz_281)begin execute_arbitration_flushIt = 1'b1; end end @@ -3584,8 +3579,8 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_275)begin - if(_zz_276)begin + if(_zz_280)begin + if(_zz_281)begin execute_arbitration_flushNext = 1'b1; end end @@ -3598,7 +3593,7 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_268)begin + if(_zz_273)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3660,10 +3655,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_277)begin + if(_zz_282)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_278)begin + if(_zz_283)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3677,21 +3672,21 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_277)begin + if(_zz_282)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_278)begin + if(_zz_283)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_275)begin - if(_zz_276)begin + if(_zz_280)begin + if(_zz_281)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_279)begin + if(_zz_284)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3712,7 +3707,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_274)begin + if(_zz_279)begin CsrPlugin_inWfi = 1'b1; end end @@ -3726,21 +3721,21 @@ module VexRiscv ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_277)begin + if(_zz_282)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_278)begin + if(_zz_283)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_277)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_282)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_278)begin - case(_zz_280) + if(_zz_283)begin + case(_zz_285) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3777,12 +3772,12 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != 5'h0); assign _zz_57 = {IBusCachedPlugin_predictionJumpInterface_valid,{CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_58 = (_zz_57 & (~ _zz_358)); + assign _zz_58 = (_zz_57 & (~ _zz_363)); assign _zz_59 = _zz_58[3]; assign _zz_60 = _zz_58[4]; assign _zz_61 = (_zz_58[1] || _zz_59); assign _zz_62 = (_zz_58[2] || _zz_59); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_240; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_245; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3802,7 +3797,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_360); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_365); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3894,7 +3889,7 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_169) + case(_zz_174) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3906,7 +3901,7 @@ module VexRiscv ( endcase end - assign _zz_72 = _zz_361[11]; + assign _zz_72 = _zz_366[11]; always @ (*) begin _zz_73[18] = _zz_72; _zz_73[17] = _zz_72; @@ -3930,13 +3925,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_362[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_367[31])); if(_zz_78)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_74 = _zz_363[19]; + assign _zz_74 = _zz_368[19]; always @ (*) begin _zz_75[10] = _zz_74; _zz_75[9] = _zz_74; @@ -3951,7 +3946,7 @@ module VexRiscv ( _zz_75[0] = _zz_74; end - assign _zz_76 = _zz_364[11]; + assign _zz_76 = _zz_369[11]; always @ (*) begin _zz_77[18] = _zz_76; _zz_77[17] = _zz_76; @@ -3977,16 +3972,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_78 = _zz_365[1]; + _zz_78 = _zz_370[1]; end default : begin - _zz_78 = _zz_366[1]; + _zz_78 = _zz_371[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_79 = _zz_367[19]; + assign _zz_79 = _zz_372[19]; always @ (*) begin _zz_80[10] = _zz_79; _zz_80[9] = _zz_79; @@ -4001,7 +3996,7 @@ module VexRiscv ( _zz_80[0] = _zz_79; end - assign _zz_81 = _zz_368[11]; + assign _zz_81 = _zz_373[11]; always @ (*) begin _zz_82[18] = _zz_81; _zz_82[17] = _zz_81; @@ -4024,7 +4019,7 @@ module VexRiscv ( _zz_82[0] = _zz_81; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_80,{{{_zz_499,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_82,{{{_zz_500,_zz_501},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_80,{{{_zz_504,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_82,{{{_zz_505,_zz_506},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -4033,52 +4028,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_204 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_205 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_206 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_205; + assign _zz_209 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_210 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_211 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_210; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_208 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_209 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_210 = (CsrPlugin_privilege == 2'b00); + assign _zz_213 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_214 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_215 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_272)begin + if(_zz_277)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_270)begin + if(_zz_275)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_211 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_270)begin - _zz_211 = 1'b1; + _zz_216 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_275)begin + _zz_216 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_271)begin + if(_zz_276)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_269)begin + if(_zz_274)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_271)begin + if(_zz_276)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_269)begin + if(_zz_274)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -4088,9 +4083,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_203 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_208 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_237 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_242 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -4130,30 +4125,30 @@ module VexRiscv ( assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin - _zz_212 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + _zz_217 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_281)begin - if(_zz_282)begin - _zz_212 = 1'b1; + if(_zz_286)begin + if(_zz_287)begin + _zz_217 = 1'b1; end end end end always @ (*) begin - _zz_213 = execute_SRC_ADD; + _zz_218 = execute_SRC_ADD; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_281)begin - _zz_213 = MmuPlugin_dBusAccess_cmd_payload_address; + if(_zz_286)begin + _zz_218 = MmuPlugin_dBusAccess_cmd_payload_address; end end end always @ (*) begin - _zz_214 = execute_MEMORY_WR; + _zz_219 = execute_MEMORY_WR; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_281)begin - _zz_214 = MmuPlugin_dBusAccess_cmd_payload_write; + if(_zz_286)begin + _zz_219 = MmuPlugin_dBusAccess_cmd_payload_write; end end end @@ -4173,58 +4168,58 @@ module VexRiscv ( end always @ (*) begin - _zz_215 = _zz_85; + _zz_220 = _zz_85; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_281)begin - _zz_215 = MmuPlugin_dBusAccess_cmd_payload_data; + if(_zz_286)begin + _zz_220 = MmuPlugin_dBusAccess_cmd_payload_data; end end end always @ (*) begin - _zz_216 = execute_DBusCachedPlugin_size; + _zz_221 = execute_DBusCachedPlugin_size; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_281)begin - _zz_216 = MmuPlugin_dBusAccess_cmd_payload_size; + if(_zz_286)begin + _zz_221 = MmuPlugin_dBusAccess_cmd_payload_size; end end end - assign _zz_236 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_241 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); always @ (*) begin - _zz_217 = 1'b0; + _zz_222 = 1'b0; if(execute_MEMORY_LRSC)begin - _zz_217 = 1'b1; + _zz_222 = 1'b1; end if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_281)begin - _zz_217 = 1'b0; + if(_zz_286)begin + _zz_222 = 1'b0; end end end always @ (*) begin - _zz_218 = execute_MEMORY_AMO; + _zz_223 = execute_MEMORY_AMO; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_281)begin - _zz_218 = 1'b0; + if(_zz_286)begin + _zz_223 = 1'b0; end end end - assign _zz_220 = execute_INSTRUCTION[31 : 29]; - assign _zz_219 = execute_INSTRUCTION[27]; + assign _zz_225 = execute_INSTRUCTION[31 : 29]; + assign _zz_224 = execute_INSTRUCTION[27]; always @ (*) begin - _zz_221 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + _zz_226 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); if(memory_IS_DBUS_SHARING)begin - _zz_221 = 1'b1; + _zz_226 = 1'b1; end end - assign _zz_222 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_221; + assign _zz_227 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_226; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_222; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_227; always @ (*) begin DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; if(memory_IS_DBUS_SHARING)begin @@ -4234,24 +4229,24 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_223 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_228 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_56 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_223 = 1'b1; + _zz_228 = 1'b1; end end always @ (*) begin - _zz_224 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + _zz_229 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); if(writeBack_IS_DBUS_SHARING)begin - _zz_224 = 1'b1; + _zz_229 = 1'b1; end end - assign _zz_225 = (CsrPlugin_privilege == 2'b00); - assign _zz_226 = writeBack_REGFILE_WRITE_DATA; + assign _zz_230 = (CsrPlugin_privilege == 2'b00); + assign _zz_231 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_283)begin + if(_zz_288)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -4261,7 +4256,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_283)begin + if(_zz_288)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -4280,15 +4275,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_283)begin + if(_zz_288)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_369}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_374}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_370}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_375}; end end end @@ -4361,7 +4356,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_322) + case(_zz_327) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_87; end @@ -4377,8 +4372,8 @@ module VexRiscv ( always @ (*) begin MmuPlugin_dBusAccess_cmd_ready = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_281)begin - if(_zz_282)begin + if(_zz_286)begin + if(_zz_287)begin MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); end end @@ -4388,7 +4383,7 @@ module VexRiscv ( always @ (*) begin DBusCachedPlugin_forceDatapath = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_281)begin + if(_zz_286)begin DBusCachedPlugin_forceDatapath = 1'b1; end end @@ -4421,21 +4416,21 @@ module VexRiscv ( assign _zz_91 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_90); assign _zz_92 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_90); assign _zz_93 = {_zz_92,_zz_91}; - assign MmuPlugin_ports_0_cacheLine_valid = _zz_241; - assign MmuPlugin_ports_0_cacheLine_exception = _zz_242; - assign MmuPlugin_ports_0_cacheLine_superPage = _zz_243; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_244; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_245; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_246; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_247; - assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_248; - assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_249; - assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_250; - assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_251; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_246; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_247; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_248; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_249; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_250; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_251; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_252; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_253; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_254; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_255; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_256; always @ (*) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; - if(_zz_284)begin - if(_zz_285)begin + if(_zz_289)begin + if(_zz_290)begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; end end @@ -4445,7 +4440,7 @@ module VexRiscv ( assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_372); + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_377); if(MmuPlugin_ports_0_entryToReplace_willClear)begin MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; end @@ -4542,21 +4537,21 @@ module VexRiscv ( assign _zz_95 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_94); assign _zz_96 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_94); assign _zz_97 = {_zz_96,_zz_95}; - assign MmuPlugin_ports_1_cacheLine_valid = _zz_252; - assign MmuPlugin_ports_1_cacheLine_exception = _zz_253; - assign MmuPlugin_ports_1_cacheLine_superPage = _zz_254; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_255; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_256; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_257; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_258; - assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_259; - assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_260; - assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_261; - assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_262; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_257; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_258; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_259; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_260; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_261; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_262; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_263; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_264; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_265; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_266; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_267; always @ (*) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; - if(_zz_284)begin - if(_zz_286)begin + if(_zz_289)begin + if(_zz_291)begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; end end @@ -4566,7 +4561,7 @@ module VexRiscv ( assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_374); + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_379); if(MmuPlugin_ports_1_entryToReplace_willClear)begin MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; end @@ -4638,14 +4633,14 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; - assign MmuPlugin_shared_dBusRsp_pte_V = _zz_375[0]; - assign MmuPlugin_shared_dBusRsp_pte_R = _zz_376[0]; - assign MmuPlugin_shared_dBusRsp_pte_W = _zz_377[0]; - assign MmuPlugin_shared_dBusRsp_pte_X = _zz_378[0]; - assign MmuPlugin_shared_dBusRsp_pte_U = _zz_379[0]; - assign MmuPlugin_shared_dBusRsp_pte_G = _zz_380[0]; - assign MmuPlugin_shared_dBusRsp_pte_A = _zz_381[0]; - assign MmuPlugin_shared_dBusRsp_pte_D = _zz_382[0]; + assign MmuPlugin_shared_dBusRsp_pte_V = _zz_380[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = _zz_381[0]; + assign MmuPlugin_shared_dBusRsp_pte_W = _zz_382[0]; + assign MmuPlugin_shared_dBusRsp_pte_X = _zz_383[0]; + assign MmuPlugin_shared_dBusRsp_pte_U = _zz_384[0]; + assign MmuPlugin_shared_dBusRsp_pte_G = _zz_385[0]; + assign MmuPlugin_shared_dBusRsp_pte_A = _zz_386[0]; + assign MmuPlugin_shared_dBusRsp_pte_D = _zz_387[0]; assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; @@ -4672,7 +4667,7 @@ module VexRiscv ( assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; always @ (*) begin - MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + MmuPlugin_dBusAccess_cmd_payload_address = 32'h0; case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin end @@ -4689,7 +4684,7 @@ module VexRiscv ( endcase end - assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'h0; assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; always @ (*) begin _zz_98[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); @@ -4702,7 +4697,7 @@ module VexRiscv ( _zz_100[1] = _zz_99[0]; end - assign _zz_101 = (_zz_100 & (~ _zz_383)); + assign _zz_101 = (_zz_100 & (~ _zz_388)); always @ (*) begin _zz_102[0] = _zz_101[1]; _zz_102[1] = _zz_101[0]; @@ -4718,7 +4713,7 @@ module VexRiscv ( assign _zz_108 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_109 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); assign _zz_110 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_104 = {(((decode_INSTRUCTION & _zz_502) == 32'h00100050) != 1'b0),{(_zz_110 != 1'b0),{(_zz_110 != 1'b0),{(_zz_503 != _zz_504),{_zz_505,{_zz_506,_zz_507}}}}}}; + assign _zz_104 = {(((decode_INSTRUCTION & _zz_507) == 32'h00100050) != 1'b0),{(_zz_110 != 1'b0),{(_zz_110 != 1'b0),{(_zz_508 != _zz_509),{_zz_510,{_zz_511,_zz_512}}}}}}; assign _zz_111 = _zz_104[2 : 1]; assign _zz_49 = _zz_111; assign _zz_112 = _zz_104[7 : 6]; @@ -4738,8 +4733,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_238; - assign decode_RegFilePlugin_rs2Data = _zz_239; + assign decode_RegFilePlugin_rs1Data = _zz_243; + assign decode_RegFilePlugin_rs2Data = _zz_244; always @ (*) begin lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); if(_zz_118)begin @@ -4781,7 +4776,7 @@ module VexRiscv ( _zz_119 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_119 = {31'd0, _zz_384}; + _zz_119 = {31'd0, _zz_389}; end default : begin _zz_119 = execute_SRC_ADD_SUB; @@ -4795,18 +4790,18 @@ module VexRiscv ( _zz_120 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_120 = {29'd0, _zz_385}; + _zz_120 = {29'd0, _zz_390}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_120 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_120 = {27'd0, _zz_386}; + _zz_120 = {27'd0, _zz_391}; end endcase end - assign _zz_121 = _zz_387[11]; + assign _zz_121 = _zz_392[11]; always @ (*) begin _zz_122[19] = _zz_121; _zz_122[18] = _zz_121; @@ -4830,7 +4825,7 @@ module VexRiscv ( _zz_122[0] = _zz_121; end - assign _zz_123 = _zz_388[11]; + assign _zz_123 = _zz_393[11]; always @ (*) begin _zz_124[19] = _zz_123; _zz_124[18] = _zz_123; @@ -4872,7 +4867,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_389; + execute_SrcPlugin_addSub = _zz_394; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -4952,180 +4947,175 @@ module VexRiscv ( end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_287)begin - if(_zz_288)begin - if(_zz_128)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_128 = 1'b0; + if(_zz_292)begin + if(_zz_293)begin + if(_zz_133)begin + _zz_128 = 1'b1; end end end - if(_zz_289)begin - if(_zz_290)begin - if(_zz_130)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_294)begin + if(_zz_295)begin + if(_zz_135)begin + _zz_128 = 1'b1; end end end - if(_zz_291)begin - if(_zz_292)begin - if(_zz_132)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_296)begin + if(_zz_297)begin + if(_zz_137)begin + _zz_128 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_128 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_287)begin - if(_zz_288)begin - if(_zz_129)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_129 = 1'b0; + if(_zz_292)begin + if(_zz_293)begin + if(_zz_134)begin + _zz_129 = 1'b1; end end end - if(_zz_289)begin - if(_zz_290)begin - if(_zz_131)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_294)begin + if(_zz_295)begin + if(_zz_136)begin + _zz_129 = 1'b1; end end end - if(_zz_291)begin - if(_zz_292)begin - if(_zz_133)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_296)begin + if(_zz_297)begin + if(_zz_138)begin + _zz_129 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_129 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_41 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_40[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_50; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_128 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_129 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_130 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_131 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_132 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_133 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_133 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_134 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_135 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_136 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_137 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_138 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_134 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_134 == 3'b000)) begin - _zz_135 = execute_BranchPlugin_eq; - end else if((_zz_134 == 3'b001)) begin - _zz_135 = (! execute_BranchPlugin_eq); - end else if((((_zz_134 & 3'b101) == 3'b101))) begin - _zz_135 = (! execute_SRC_LESS); + assign _zz_139 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_139 == 3'b000)) begin + _zz_140 = execute_BranchPlugin_eq; + end else if((_zz_139 == 3'b001)) begin + _zz_140 = (! execute_BranchPlugin_eq); + end else if((((_zz_139 & 3'b101) == 3'b101))) begin + _zz_140 = (! execute_SRC_LESS); end else begin - _zz_135 = execute_SRC_LESS; + _zz_140 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_136 = 1'b0; + _zz_141 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_136 = 1'b1; + _zz_141 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_136 = 1'b1; + _zz_141 = 1'b1; end default : begin - _zz_136 = _zz_135; + _zz_141 = _zz_140; end endcase end - assign _zz_137 = _zz_396[11]; - always @ (*) begin - _zz_138[19] = _zz_137; - _zz_138[18] = _zz_137; - _zz_138[17] = _zz_137; - _zz_138[16] = _zz_137; - _zz_138[15] = _zz_137; - _zz_138[14] = _zz_137; - _zz_138[13] = _zz_137; - _zz_138[12] = _zz_137; - _zz_138[11] = _zz_137; - _zz_138[10] = _zz_137; - _zz_138[9] = _zz_137; - _zz_138[8] = _zz_137; - _zz_138[7] = _zz_137; - _zz_138[6] = _zz_137; - _zz_138[5] = _zz_137; - _zz_138[4] = _zz_137; - _zz_138[3] = _zz_137; - _zz_138[2] = _zz_137; - _zz_138[1] = _zz_137; - _zz_138[0] = _zz_137; - end - - assign _zz_139 = _zz_397[19]; - always @ (*) begin - _zz_140[10] = _zz_139; - _zz_140[9] = _zz_139; - _zz_140[8] = _zz_139; - _zz_140[7] = _zz_139; - _zz_140[6] = _zz_139; - _zz_140[5] = _zz_139; - _zz_140[4] = _zz_139; - _zz_140[3] = _zz_139; - _zz_140[2] = _zz_139; - _zz_140[1] = _zz_139; - _zz_140[0] = _zz_139; - end - - assign _zz_141 = _zz_398[11]; - always @ (*) begin - _zz_142[18] = _zz_141; - _zz_142[17] = _zz_141; - _zz_142[16] = _zz_141; - _zz_142[15] = _zz_141; - _zz_142[14] = _zz_141; - _zz_142[13] = _zz_141; - _zz_142[12] = _zz_141; - _zz_142[11] = _zz_141; - _zz_142[10] = _zz_141; - _zz_142[9] = _zz_141; - _zz_142[8] = _zz_141; - _zz_142[7] = _zz_141; - _zz_142[6] = _zz_141; - _zz_142[5] = _zz_141; - _zz_142[4] = _zz_141; - _zz_142[3] = _zz_141; - _zz_142[2] = _zz_141; - _zz_142[1] = _zz_141; - _zz_142[0] = _zz_141; + assign _zz_142 = _zz_401[11]; + always @ (*) begin + _zz_143[19] = _zz_142; + _zz_143[18] = _zz_142; + _zz_143[17] = _zz_142; + _zz_143[16] = _zz_142; + _zz_143[15] = _zz_142; + _zz_143[14] = _zz_142; + _zz_143[13] = _zz_142; + _zz_143[12] = _zz_142; + _zz_143[11] = _zz_142; + _zz_143[10] = _zz_142; + _zz_143[9] = _zz_142; + _zz_143[8] = _zz_142; + _zz_143[7] = _zz_142; + _zz_143[6] = _zz_142; + _zz_143[5] = _zz_142; + _zz_143[4] = _zz_142; + _zz_143[3] = _zz_142; + _zz_143[2] = _zz_142; + _zz_143[1] = _zz_142; + _zz_143[0] = _zz_142; + end + + assign _zz_144 = _zz_402[19]; + always @ (*) begin + _zz_145[10] = _zz_144; + _zz_145[9] = _zz_144; + _zz_145[8] = _zz_144; + _zz_145[7] = _zz_144; + _zz_145[6] = _zz_144; + _zz_145[5] = _zz_144; + _zz_145[4] = _zz_144; + _zz_145[3] = _zz_144; + _zz_145[2] = _zz_144; + _zz_145[1] = _zz_144; + _zz_145[0] = _zz_144; + end + + assign _zz_146 = _zz_403[11]; + always @ (*) begin + _zz_147[18] = _zz_146; + _zz_147[17] = _zz_146; + _zz_147[16] = _zz_146; + _zz_147[15] = _zz_146; + _zz_147[14] = _zz_146; + _zz_147[13] = _zz_146; + _zz_147[12] = _zz_146; + _zz_147[11] = _zz_146; + _zz_147[10] = _zz_146; + _zz_147[9] = _zz_146; + _zz_147[8] = _zz_146; + _zz_147[7] = _zz_146; + _zz_147[6] = _zz_146; + _zz_147[5] = _zz_146; + _zz_147[4] = _zz_146; + _zz_147[3] = _zz_146; + _zz_147[2] = _zz_146; + _zz_147[1] = _zz_146; + _zz_147[0] = _zz_146; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_143 = (_zz_399[1] ^ execute_RS1[1]); + _zz_148 = (_zz_404[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_143 = _zz_400[1]; + _zz_148 = _zz_405[1]; end default : begin - _zz_143 = _zz_401[1]; + _zz_148 = _zz_406[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_143); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_148); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -5137,80 +5127,80 @@ module VexRiscv ( endcase end - assign _zz_144 = _zz_402[11]; + assign _zz_149 = _zz_407[11]; always @ (*) begin - _zz_145[19] = _zz_144; - _zz_145[18] = _zz_144; - _zz_145[17] = _zz_144; - _zz_145[16] = _zz_144; - _zz_145[15] = _zz_144; - _zz_145[14] = _zz_144; - _zz_145[13] = _zz_144; - _zz_145[12] = _zz_144; - _zz_145[11] = _zz_144; - _zz_145[10] = _zz_144; - _zz_145[9] = _zz_144; - _zz_145[8] = _zz_144; - _zz_145[7] = _zz_144; - _zz_145[6] = _zz_144; - _zz_145[5] = _zz_144; - _zz_145[4] = _zz_144; - _zz_145[3] = _zz_144; - _zz_145[2] = _zz_144; - _zz_145[1] = _zz_144; - _zz_145[0] = _zz_144; + _zz_150[19] = _zz_149; + _zz_150[18] = _zz_149; + _zz_150[17] = _zz_149; + _zz_150[16] = _zz_149; + _zz_150[15] = _zz_149; + _zz_150[14] = _zz_149; + _zz_150[13] = _zz_149; + _zz_150[12] = _zz_149; + _zz_150[11] = _zz_149; + _zz_150[10] = _zz_149; + _zz_150[9] = _zz_149; + _zz_150[8] = _zz_149; + _zz_150[7] = _zz_149; + _zz_150[6] = _zz_149; + _zz_150[5] = _zz_149; + _zz_150[4] = _zz_149; + _zz_150[3] = _zz_149; + _zz_150[2] = _zz_149; + _zz_150[1] = _zz_149; + _zz_150[0] = _zz_149; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_145,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_150,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_147,{{{_zz_708,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_149,{{{_zz_709,_zz_710},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_152,{{{_zz_713,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_154,{{{_zz_714,_zz_715},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_405}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_410}; end end endcase end - assign _zz_146 = _zz_403[19]; - always @ (*) begin - _zz_147[10] = _zz_146; - _zz_147[9] = _zz_146; - _zz_147[8] = _zz_146; - _zz_147[7] = _zz_146; - _zz_147[6] = _zz_146; - _zz_147[5] = _zz_146; - _zz_147[4] = _zz_146; - _zz_147[3] = _zz_146; - _zz_147[2] = _zz_146; - _zz_147[1] = _zz_146; - _zz_147[0] = _zz_146; - end - - assign _zz_148 = _zz_404[11]; - always @ (*) begin - _zz_149[18] = _zz_148; - _zz_149[17] = _zz_148; - _zz_149[16] = _zz_148; - _zz_149[15] = _zz_148; - _zz_149[14] = _zz_148; - _zz_149[13] = _zz_148; - _zz_149[12] = _zz_148; - _zz_149[11] = _zz_148; - _zz_149[10] = _zz_148; - _zz_149[9] = _zz_148; - _zz_149[8] = _zz_148; - _zz_149[7] = _zz_148; - _zz_149[6] = _zz_148; - _zz_149[5] = _zz_148; - _zz_149[4] = _zz_148; - _zz_149[3] = _zz_148; - _zz_149[2] = _zz_148; - _zz_149[1] = _zz_148; - _zz_149[0] = _zz_148; + assign _zz_151 = _zz_408[19]; + always @ (*) begin + _zz_152[10] = _zz_151; + _zz_152[9] = _zz_151; + _zz_152[8] = _zz_151; + _zz_152[7] = _zz_151; + _zz_152[6] = _zz_151; + _zz_152[5] = _zz_151; + _zz_152[4] = _zz_151; + _zz_152[3] = _zz_151; + _zz_152[2] = _zz_151; + _zz_152[1] = _zz_151; + _zz_152[0] = _zz_151; + end + + assign _zz_153 = _zz_409[11]; + always @ (*) begin + _zz_154[18] = _zz_153; + _zz_154[17] = _zz_153; + _zz_154[16] = _zz_153; + _zz_154[15] = _zz_153; + _zz_154[14] = _zz_153; + _zz_154[13] = _zz_153; + _zz_154[12] = _zz_153; + _zz_154[11] = _zz_153; + _zz_154[10] = _zz_153; + _zz_154[9] = _zz_153; + _zz_154[8] = _zz_153; + _zz_154[7] = _zz_153; + _zz_154[6] = _zz_153; + _zz_154[5] = _zz_153; + _zz_154[4] = _zz_153; + _zz_154[3] = _zz_153; + _zz_154[2] = _zz_153; + _zz_154[1] = _zz_153; + _zz_154[0] = _zz_153; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -5221,7 +5211,7 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin - CsrPlugin_privilege = _zz_150; + CsrPlugin_privilege = _zz_155; if(CsrPlugin_forceMachineWire)begin CsrPlugin_privilege = 2'b11; end @@ -5240,12 +5230,12 @@ module VexRiscv ( end assign CsrPlugin_redoInterface_payload = decode_PC; - assign _zz_151 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); - assign _zz_152 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); - assign _zz_153 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); - assign _zz_154 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_155 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_156 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_156 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_157 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_158 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_159 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_160 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_161 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) @@ -5315,11 +5305,11 @@ module VexRiscv ( end assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_157 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_158 = _zz_406[0]; + assign _zz_162 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_163 = _zz_411[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_273)begin + if(_zz_278)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -5403,7 +5393,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_base = CsrPlugin_stvec_base; @@ -5528,7 +5518,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_293)begin + if(_zz_298)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -5547,20 +5537,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_294)begin + if(_zz_299)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_295)begin + if(_zz_300)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_294)begin + if(_zz_299)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_295)begin + if(_zz_300)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -5578,14 +5568,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_293)begin + if(_zz_298)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_293)begin + if(_zz_298)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -5603,7 +5593,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_323) + case(_zz_328) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -5617,7 +5607,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_296) + case(_zz_301) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -5631,7 +5621,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_296) + case(_zz_301) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -5650,12 +5640,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_408) + $signed(_zz_409)); + assign writeBack_MulPlugin_result = ($signed(_zz_413) + $signed(_zz_414)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_268)begin - if(_zz_297)begin + if(_zz_273)begin + if(_zz_302)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -5663,7 +5653,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_298)begin + if(_zz_303)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -5674,34 +5664,34 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_413); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_418); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_159 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_159[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_414); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_415 : _zz_416); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_417[31:0]; - assign _zz_160 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_161 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_162 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_164 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_164[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_419); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_420 : _zz_421); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_422[31:0]; + assign _zz_165 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_166 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_167 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_163[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_163[31 : 0] = execute_RS1; + _zz_168[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_168[31 : 0] = execute_RS1; end - assign _zz_165 = (_zz_164 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_165 != 32'h0); - assign _zz_167 = (_zz_166 & externalInterruptArray_regNext); - assign externalInterruptS = (_zz_167 != 32'h0); + assign _zz_170 = (_zz_169 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_170 != 32'h0); + assign _zz_172 = (_zz_171 & externalInterruptArray_regNext); + assign externalInterruptS = (_zz_172 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_299) + case(_zz_304) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -5715,7 +5705,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_168))begin + if((! _zz_173))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -5727,7 +5717,7 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_299) + case(_zz_304) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -5791,7 +5781,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_169) + case(_zz_174) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -5801,246 +5791,246 @@ module VexRiscv ( end always @ (*) begin - _zz_170 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_170[12 : 0] = 13'h1000; - _zz_170[25 : 20] = 6'h20; + _zz_175[12 : 0] = 13'h1000; + _zz_175[25 : 20] = 6'h20; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_171[19 : 19] = MmuPlugin_status_mxr; - _zz_171[18 : 18] = MmuPlugin_status_sum; - _zz_171[17 : 17] = MmuPlugin_status_mprv; - _zz_171[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_171[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_171[3 : 3] = CsrPlugin_mstatus_MIE; - _zz_171[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_171[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_171[1 : 1] = CsrPlugin_sstatus_SIE; + _zz_176[19 : 19] = MmuPlugin_status_mxr; + _zz_176[18 : 18] = MmuPlugin_status_sum; + _zz_176[17 : 17] = MmuPlugin_status_mprv; + _zz_176[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_176[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_176[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_176[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_176[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_176[1 : 1] = CsrPlugin_sstatus_SIE; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_256)begin - _zz_172[19 : 19] = MmuPlugin_status_mxr; - _zz_172[18 : 18] = MmuPlugin_status_sum; - _zz_172[17 : 17] = MmuPlugin_status_mprv; - _zz_172[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_172[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_172[1 : 1] = CsrPlugin_sstatus_SIE; + _zz_177[19 : 19] = MmuPlugin_status_mxr; + _zz_177[18 : 18] = MmuPlugin_status_sum; + _zz_177[17 : 17] = MmuPlugin_status_mprv; + _zz_177[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_177[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_177[1 : 1] = CsrPlugin_sstatus_SIE; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_384)begin - _zz_173[31 : 31] = MmuPlugin_satp_mode; - _zz_173[30 : 22] = MmuPlugin_satp_asid; - _zz_173[19 : 0] = MmuPlugin_satp_ppn; + _zz_178[31 : 31] = MmuPlugin_satp_mode; + _zz_178[30 : 22] = MmuPlugin_satp_asid; + _zz_178[19 : 0] = MmuPlugin_satp_ppn; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_174[0 : 0] = 1'b1; + _zz_179[0 : 0] = 1'b1; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_175[1 : 0] = 2'b10; + _zz_180[1 : 0] = 2'b10; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_176[1 : 0] = 2'b11; + _zz_181[1 : 0] = 2'b11; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_177[11 : 11] = CsrPlugin_mip_MEIP; - _zz_177[7 : 7] = CsrPlugin_mip_MTIP; - _zz_177[3 : 3] = CsrPlugin_mip_MSIP; - _zz_177[5 : 5] = CsrPlugin_sip_STIP; - _zz_177[1 : 1] = CsrPlugin_sip_SSIP; - _zz_177[9 : 9] = CsrPlugin_sip_SEIP_OR; + _zz_182[11 : 11] = CsrPlugin_mip_MEIP; + _zz_182[7 : 7] = CsrPlugin_mip_MTIP; + _zz_182[3 : 3] = CsrPlugin_mip_MSIP; + _zz_182[5 : 5] = CsrPlugin_sip_STIP; + _zz_182[1 : 1] = CsrPlugin_sip_SSIP; + _zz_182[9 : 9] = CsrPlugin_sip_SEIP_OR; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_178[11 : 11] = CsrPlugin_mie_MEIE; - _zz_178[7 : 7] = CsrPlugin_mie_MTIE; - _zz_178[3 : 3] = CsrPlugin_mie_MSIE; - _zz_178[9 : 9] = CsrPlugin_sie_SEIE; - _zz_178[5 : 5] = CsrPlugin_sie_STIE; - _zz_178[1 : 1] = CsrPlugin_sie_SSIE; + _zz_183[11 : 11] = CsrPlugin_mie_MEIE; + _zz_183[7 : 7] = CsrPlugin_mie_MTIE; + _zz_183[3 : 3] = CsrPlugin_mie_MSIE; + _zz_183[9 : 9] = CsrPlugin_sie_SEIE; + _zz_183[5 : 5] = CsrPlugin_sie_STIE; + _zz_183[1 : 1] = CsrPlugin_sie_SSIE; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_179[31 : 0] = CsrPlugin_mepc; + _zz_184[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_180[31 : 0] = CsrPlugin_mscratch; + _zz_185[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_181[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_181[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_186[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_186[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_182[31 : 0] = CsrPlugin_mtval; + _zz_187[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_324)begin - _zz_183[5 : 5] = CsrPlugin_sip_STIP; - _zz_183[1 : 1] = CsrPlugin_sip_SSIP; - _zz_183[9 : 9] = CsrPlugin_sip_SEIP_OR; + _zz_188[5 : 5] = CsrPlugin_sip_STIP; + _zz_188[1 : 1] = CsrPlugin_sip_SSIP; + _zz_188[9 : 9] = CsrPlugin_sip_SEIP_OR; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_260)begin - _zz_184[9 : 9] = CsrPlugin_sie_SEIE; - _zz_184[5 : 5] = CsrPlugin_sie_STIE; - _zz_184[1 : 1] = CsrPlugin_sie_SSIE; + _zz_189[9 : 9] = CsrPlugin_sie_SEIE; + _zz_189[5 : 5] = CsrPlugin_sie_STIE; + _zz_189[1 : 1] = CsrPlugin_sie_SSIE; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_261)begin - _zz_185[31 : 2] = CsrPlugin_stvec_base; - _zz_185[1 : 0] = CsrPlugin_stvec_mode; + _zz_190[31 : 2] = CsrPlugin_stvec_base; + _zz_190[1 : 0] = CsrPlugin_stvec_mode; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_321)begin - _zz_186[31 : 0] = CsrPlugin_sepc; + _zz_191[31 : 0] = CsrPlugin_sepc; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_320)begin - _zz_187[31 : 0] = CsrPlugin_sscratch; + _zz_192[31 : 0] = CsrPlugin_sscratch; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_322)begin - _zz_188[31 : 31] = CsrPlugin_scause_interrupt; - _zz_188[3 : 0] = CsrPlugin_scause_exceptionCode; + _zz_193[31 : 31] = CsrPlugin_scause_interrupt; + _zz_193[3 : 0] = CsrPlugin_scause_exceptionCode; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_323)begin - _zz_189[31 : 0] = CsrPlugin_stval; + _zz_194[31 : 0] = CsrPlugin_stval; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_190[31 : 0] = _zz_164; + _zz_195[31 : 0] = _zz_169; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_191[31 : 0] = _zz_165; + _zz_196[31 : 0] = _zz_170; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_2496)begin - _zz_192[31 : 0] = _zz_166; + _zz_197[31 : 0] = _zz_171; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_3520)begin - _zz_193[31 : 0] = _zz_167; + _zz_198[31 : 0] = _zz_172; end end - assign execute_CsrPlugin_readData = (((((_zz_170 | _zz_171) | (_zz_172 | _zz_173)) | ((_zz_174 | _zz_175) | (_zz_176 | _zz_711))) | (((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_181 | _zz_182) | (_zz_183 | _zz_184)))) | ((((_zz_185 | _zz_186) | (_zz_187 | _zz_188)) | ((_zz_189 | _zz_190) | (_zz_191 | _zz_192))) | _zz_193)); - assign iBusWishbone_ADR = {_zz_472,_zz_194}; - assign iBusWishbone_CTI = ((_zz_194 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_175 | _zz_176) | (_zz_177 | _zz_178)) | ((_zz_179 | _zz_180) | (_zz_181 | _zz_716))) | (((_zz_182 | _zz_183) | (_zz_184 | _zz_185)) | ((_zz_186 | _zz_187) | (_zz_188 | _zz_189)))) | ((((_zz_190 | _zz_191) | (_zz_192 | _zz_193)) | ((_zz_194 | _zz_195) | (_zz_196 | _zz_197))) | _zz_198)); + assign iBusWishbone_ADR = {_zz_477,_zz_199}; + assign iBusWishbone_CTI = ((_zz_199 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_300)begin + if(_zz_305)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_300)begin + if(_zz_305)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_195; + assign iBus_rsp_valid = _zz_200; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_201 = (dBus_cmd_payload_length != 3'b000); - assign _zz_197 = dBus_cmd_valid; - assign _zz_199 = dBus_cmd_payload_wr; - assign _zz_200 = (_zz_196 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_198 && (_zz_199 || _zz_200)); - assign dBusWishbone_ADR = ((_zz_201 ? {{dBus_cmd_payload_address[31 : 5],_zz_196},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_201 ? (_zz_200 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_206 = (dBus_cmd_payload_length != 3'b000); + assign _zz_202 = dBus_cmd_valid; + assign _zz_204 = dBus_cmd_payload_wr; + assign _zz_205 = (_zz_201 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_203 && (_zz_204 || _zz_205)); + assign dBusWishbone_ADR = ((_zz_206 ? {{dBus_cmd_payload_address[31 : 5],_zz_201},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_206 ? (_zz_205 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_199 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_199; + assign dBusWishbone_SEL = (_zz_204 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_204; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_198 = (_zz_197 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_197; - assign dBusWishbone_STB = _zz_197; - assign dBus_rsp_valid = _zz_202; + assign _zz_203 = (_zz_202 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_202; + assign dBusWishbone_STB = _zz_202; + assign dBus_rsp_valid = _zz_207; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -6079,8 +6069,8 @@ module VexRiscv ( MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; _zz_118 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; - _zz_150 <= 2'b11; + _zz_130 <= 1'b0; + _zz_155 <= 2'b11; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -6123,18 +6113,18 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_164 <= 32'h0; - _zz_166 <= 32'h0; + _zz_169 <= 32'h0; + _zz_171 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_169 <= 3'b000; + _zz_174 <= 3'b000; execute_to_memory_IS_DBUS_SHARING <= 1'b0; memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; - _zz_194 <= 3'b000; - _zz_195 <= 1'b0; - _zz_196 <= 3'b000; - _zz_202 <= 1'b0; + _zz_199 <= 3'b000; + _zz_200 <= 1'b0; + _zz_201 <= 3'b000; + _zz_207 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -6215,7 +6205,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_301)begin + if(_zz_306)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -6257,7 +6247,7 @@ module VexRiscv ( MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_302)begin + if(_zz_307)begin MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; end end @@ -6291,32 +6281,32 @@ module VexRiscv ( end end endcase - if(_zz_284)begin - if(_zz_285)begin - if(_zz_303)begin + if(_zz_289)begin + if(_zz_290)begin + if(_zz_308)begin MmuPlugin_ports_0_cache_0_valid <= 1'b1; end - if(_zz_304)begin + if(_zz_309)begin MmuPlugin_ports_0_cache_1_valid <= 1'b1; end - if(_zz_305)begin + if(_zz_310)begin MmuPlugin_ports_0_cache_2_valid <= 1'b1; end - if(_zz_306)begin + if(_zz_311)begin MmuPlugin_ports_0_cache_3_valid <= 1'b1; end end - if(_zz_286)begin - if(_zz_307)begin + if(_zz_291)begin + if(_zz_312)begin MmuPlugin_ports_1_cache_0_valid <= 1'b1; end - if(_zz_308)begin + if(_zz_313)begin MmuPlugin_ports_1_cache_1_valid <= 1'b1; end - if(_zz_309)begin + if(_zz_314)begin MmuPlugin_ports_1_cache_2_valid <= 1'b1; end - if(_zz_310)begin + if(_zz_315)begin MmuPlugin_ports_1_cache_3_valid <= 1'b1; end end @@ -6332,7 +6322,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_valid <= 1'b0; end _zz_118 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_130 <= (_zz_41 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -6354,34 +6344,34 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_311)begin - if(_zz_312)begin + if(_zz_316)begin + if(_zz_317)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_313)begin + if(_zz_318)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_314)begin + if(_zz_319)begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(_zz_315)begin - if(_zz_316)begin + if(_zz_320)begin + if(_zz_321)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_317)begin + if(_zz_322)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_318)begin + if(_zz_323)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_319)begin + if(_zz_324)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_320)begin + if(_zz_325)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_321)begin + if(_zz_326)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -6406,8 +6396,8 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_277)begin - _zz_150 <= CsrPlugin_targetPrivilege; + if(_zz_282)begin + _zz_155 <= CsrPlugin_targetPrivilege; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_sstatus_SIE <= 1'b0; @@ -6423,25 +6413,25 @@ module VexRiscv ( end endcase end - if(_zz_278)begin - case(_zz_280) + if(_zz_283)begin + case(_zz_285) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; - _zz_150 <= CsrPlugin_mstatus_MPP; + _zz_155 <= CsrPlugin_mstatus_MPP; end 2'b01 : begin CsrPlugin_sstatus_SPP <= 1'b0; CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; CsrPlugin_sstatus_SPIE <= 1'b1; - _zz_150 <= {1'b0,CsrPlugin_sstatus_SPP}; + _zz_155 <= {1'b0,CsrPlugin_sstatus_SPP}; end default : begin end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_156,{_zz_155,{_zz_154,{_zz_153,{_zz_152,_zz_151}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_161,{_zz_160,{_zz_159,{_zz_158,{_zz_157,_zz_156}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; if((! memory_arbitration_isStuck))begin execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; @@ -6467,25 +6457,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_169) + case(_zz_174) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_169 <= 3'b001; + _zz_174 <= 3'b001; end end 3'b001 : begin - _zz_169 <= 3'b010; + _zz_174 <= 3'b010; end 3'b010 : begin - _zz_169 <= 3'b011; + _zz_174 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_169 <= 3'b100; + _zz_174 <= 3'b100; end end 3'b100 : begin - _zz_169 <= 3'b000; + _zz_174 <= 3'b000; end default : begin end @@ -6495,25 +6485,25 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_427[0]; - MmuPlugin_status_sum <= _zz_428[0]; - MmuPlugin_status_mprv <= _zz_429[0]; + MmuPlugin_status_mxr <= _zz_432[0]; + MmuPlugin_status_sum <= _zz_433[0]; + MmuPlugin_status_mprv <= _zz_434[0]; CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_430[0]; - CsrPlugin_mstatus_MIE <= _zz_431[0]; + CsrPlugin_mstatus_MPIE <= _zz_435[0]; + CsrPlugin_mstatus_MIE <= _zz_436[0]; CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_432[0]; - CsrPlugin_sstatus_SIE <= _zz_433[0]; + CsrPlugin_sstatus_SPIE <= _zz_437[0]; + CsrPlugin_sstatus_SIE <= _zz_438[0]; end end if(execute_CsrPlugin_csr_256)begin if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_434[0]; - MmuPlugin_status_sum <= _zz_435[0]; - MmuPlugin_status_mprv <= _zz_436[0]; + MmuPlugin_status_mxr <= _zz_439[0]; + MmuPlugin_status_sum <= _zz_440[0]; + MmuPlugin_status_mprv <= _zz_441[0]; CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_437[0]; - CsrPlugin_sstatus_SIE <= _zz_438[0]; + CsrPlugin_sstatus_SPIE <= _zz_442[0]; + CsrPlugin_sstatus_SIE <= _zz_443[0]; end end if(execute_CsrPlugin_csr_384)begin @@ -6528,86 +6518,86 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_valid <= 1'b0; end if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_mode <= _zz_439[0]; + MmuPlugin_satp_mode <= _zz_444[0]; end end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_441[0]; - CsrPlugin_sip_SSIP <= _zz_442[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_443[0]; + CsrPlugin_sip_STIP <= _zz_446[0]; + CsrPlugin_sip_SSIP <= _zz_447[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_448[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_444[0]; - CsrPlugin_mie_MTIE <= _zz_445[0]; - CsrPlugin_mie_MSIE <= _zz_446[0]; - CsrPlugin_sie_SEIE <= _zz_447[0]; - CsrPlugin_sie_STIE <= _zz_448[0]; - CsrPlugin_sie_SSIE <= _zz_449[0]; + CsrPlugin_mie_MEIE <= _zz_449[0]; + CsrPlugin_mie_MTIE <= _zz_450[0]; + CsrPlugin_mie_MSIE <= _zz_451[0]; + CsrPlugin_sie_SEIE <= _zz_452[0]; + CsrPlugin_sie_STIE <= _zz_453[0]; + CsrPlugin_sie_SSIE <= _zz_454[0]; end end if(execute_CsrPlugin_csr_770)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_medeleg_IAM <= _zz_450[0]; - CsrPlugin_medeleg_IAF <= _zz_451[0]; - CsrPlugin_medeleg_II <= _zz_452[0]; - CsrPlugin_medeleg_LAM <= _zz_453[0]; - CsrPlugin_medeleg_LAF <= _zz_454[0]; - CsrPlugin_medeleg_SAM <= _zz_455[0]; - CsrPlugin_medeleg_SAF <= _zz_456[0]; - CsrPlugin_medeleg_EU <= _zz_457[0]; - CsrPlugin_medeleg_ES <= _zz_458[0]; - CsrPlugin_medeleg_IPF <= _zz_459[0]; - CsrPlugin_medeleg_LPF <= _zz_460[0]; - CsrPlugin_medeleg_SPF <= _zz_461[0]; + CsrPlugin_medeleg_IAM <= _zz_455[0]; + CsrPlugin_medeleg_IAF <= _zz_456[0]; + CsrPlugin_medeleg_II <= _zz_457[0]; + CsrPlugin_medeleg_LAM <= _zz_458[0]; + CsrPlugin_medeleg_LAF <= _zz_459[0]; + CsrPlugin_medeleg_SAM <= _zz_460[0]; + CsrPlugin_medeleg_SAF <= _zz_461[0]; + CsrPlugin_medeleg_EU <= _zz_462[0]; + CsrPlugin_medeleg_ES <= _zz_463[0]; + CsrPlugin_medeleg_IPF <= _zz_464[0]; + CsrPlugin_medeleg_LPF <= _zz_465[0]; + CsrPlugin_medeleg_SPF <= _zz_466[0]; end end if(execute_CsrPlugin_csr_771)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mideleg_SE <= _zz_462[0]; - CsrPlugin_mideleg_ST <= _zz_463[0]; - CsrPlugin_mideleg_SS <= _zz_464[0]; + CsrPlugin_mideleg_SE <= _zz_467[0]; + CsrPlugin_mideleg_ST <= _zz_468[0]; + CsrPlugin_mideleg_SS <= _zz_469[0]; end end if(execute_CsrPlugin_csr_324)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_465[0]; - CsrPlugin_sip_SSIP <= _zz_466[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_467[0]; + CsrPlugin_sip_STIP <= _zz_470[0]; + CsrPlugin_sip_SSIP <= _zz_471[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_472[0]; end end if(execute_CsrPlugin_csr_260)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sie_SEIE <= _zz_468[0]; - CsrPlugin_sie_STIE <= _zz_469[0]; - CsrPlugin_sie_SSIE <= _zz_470[0]; + CsrPlugin_sie_SEIE <= _zz_473[0]; + CsrPlugin_sie_STIE <= _zz_474[0]; + CsrPlugin_sie_SSIE <= _zz_475[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_169 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2496)begin if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_171 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_300)begin + if(_zz_305)begin if(iBusWishbone_ACK)begin - _zz_194 <= (_zz_194 + 3'b001); + _zz_199 <= (_zz_199 + 3'b001); end end - _zz_195 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_197 && _zz_198))begin - _zz_196 <= (_zz_196 + 3'b001); - if(_zz_200)begin - _zz_196 <= 3'b000; + _zz_200 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_202 && _zz_203))begin + _zz_201 <= (_zz_201 + 3'b001); + if(_zz_205)begin + _zz_201 <= 3'b000; end end - _zz_202 <= ((_zz_197 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_207 <= ((_zz_202 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -6621,7 +6611,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_301)begin + if(_zz_306)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -6657,7 +6647,7 @@ module VexRiscv ( end case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_302)begin + if(_zz_307)begin MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; MmuPlugin_shared_vpn_1 <= _zz_103[31 : 22]; MmuPlugin_shared_vpn_0 <= _zz_103[21 : 12]; @@ -6672,9 +6662,9 @@ module VexRiscv ( default : begin end endcase - if(_zz_284)begin - if(_zz_285)begin - if(_zz_303)begin + if(_zz_289)begin + if(_zz_290)begin + if(_zz_308)begin MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6686,7 +6676,7 @@ module VexRiscv ( MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_304)begin + if(_zz_309)begin MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6698,7 +6688,7 @@ module VexRiscv ( MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_305)begin + if(_zz_310)begin MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6710,7 +6700,7 @@ module VexRiscv ( MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_306)begin + if(_zz_311)begin MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6723,8 +6713,8 @@ module VexRiscv ( MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end end - if(_zz_286)begin - if(_zz_307)begin + if(_zz_291)begin + if(_zz_312)begin MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6736,7 +6726,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_308)begin + if(_zz_313)begin MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6748,7 +6738,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_309)begin + if(_zz_314)begin MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6760,7 +6750,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_310)begin + if(_zz_315)begin MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6774,8 +6764,8 @@ module VexRiscv ( end end end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_131 <= _zz_40[11 : 7]; + _zz_132 <= _zz_50; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -6784,9 +6774,9 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_273)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_158 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_158 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_278)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_163 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_163 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -6800,47 +6790,47 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_311)begin - if(_zz_312)begin + if(_zz_316)begin + if(_zz_317)begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_313)begin + if(_zz_318)begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_314)begin + if(_zz_319)begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end end - if(_zz_315)begin - if(_zz_316)begin + if(_zz_320)begin + if(_zz_321)begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_317)begin + if(_zz_322)begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_318)begin + if(_zz_323)begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_319)begin + if(_zz_324)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_320)begin + if(_zz_325)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_321)begin + if(_zz_326)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_277)begin + if(_zz_282)begin case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); @@ -6868,20 +6858,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_268)begin - if(_zz_297)begin + if(_zz_273)begin + if(_zz_302)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_418[31:0]; + memory_DivPlugin_div_result <= _zz_423[31:0]; end end end - if(_zz_298)begin + if(_zz_303)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_162 ? (~ _zz_163) : _zz_163) + _zz_424); - memory_DivPlugin_rs2 <= ((_zz_161 ? (~ execute_RS2) : execute_RS2) + _zz_426); - memory_DivPlugin_div_needRevert <= ((_zz_162 ^ (_zz_161 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_167 ? (~ _zz_168) : _zz_168) + _zz_429); + memory_DivPlugin_rs2 <= ((_zz_166 ? (~ execute_RS2) : execute_RS2) + _zz_431); + memory_DivPlugin_div_needRevert <= ((_zz_167 ^ (_zz_166 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -7180,7 +7170,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_440[0]; + CsrPlugin_mip_MSIP <= _zz_445[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -7217,7 +7207,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_322)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_scause_interrupt <= _zz_471[0]; + CsrPlugin_scause_interrupt <= _zz_476[0]; CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -7240,8 +7230,8 @@ module VexRiscv ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_50; end - _zz_168 <= debug_bus_cmd_payload_address[2]; - if(_zz_275)begin + _zz_173 <= debug_bus_cmd_payload_address[2]; + if(_zz_280)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -7259,7 +7249,7 @@ module VexRiscv ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_299) + case(_zz_304) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -7287,13 +7277,13 @@ module VexRiscv ( end endcase end - if(_zz_275)begin - if(_zz_276)begin + if(_zz_280)begin + if(_zz_281)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_279)begin + if(_zz_284)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end @@ -7647,7 +7637,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_12)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -7661,7 +7651,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_12)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -7691,7 +7681,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -7718,7 +7708,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -7766,7 +7756,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -7776,7 +7766,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v index 858cba5..389fed5 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -81,66 +81,66 @@ module VexRiscv ( input clk, input reset ); - wire _zz_187; - wire _zz_188; - wire _zz_189; - wire _zz_190; - wire _zz_191; wire _zz_192; wire _zz_193; wire _zz_194; - reg _zz_195; - reg _zz_196; - reg [31:0] _zz_197; - reg _zz_198; - reg [31:0] _zz_199; - reg [1:0] _zz_200; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + reg _zz_200; reg _zz_201; - reg _zz_202; - wire _zz_203; - wire [2:0] _zz_204; - reg _zz_205; - wire [31:0] _zz_206; + reg [31:0] _zz_202; + reg _zz_203; + reg [31:0] _zz_204; + reg [1:0] _zz_205; + reg _zz_206; reg _zz_207; - reg _zz_208; - wire _zz_209; - wire [31:0] _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; + wire _zz_208; + wire [2:0] _zz_209; + reg _zz_210; + wire [31:0] _zz_211; + reg _zz_212; + reg _zz_213; wire _zz_214; - wire _zz_215; + wire [31:0] _zz_215; wire _zz_216; wire _zz_217; wire _zz_218; - wire [3:0] _zz_219; + wire _zz_219; wire _zz_220; wire _zz_221; - reg [31:0] _zz_222; - reg [31:0] _zz_223; - reg [31:0] _zz_224; - reg _zz_225; - reg _zz_226; - reg _zz_227; - reg [9:0] _zz_228; - reg [9:0] _zz_229; - reg [9:0] _zz_230; - reg [9:0] _zz_231; + wire _zz_222; + wire _zz_223; + wire [3:0] _zz_224; + wire _zz_225; + wire _zz_226; + reg [31:0] _zz_227; + reg [31:0] _zz_228; + reg [31:0] _zz_229; + reg _zz_230; + reg _zz_231; reg _zz_232; - reg _zz_233; - reg _zz_234; - reg _zz_235; - reg _zz_236; + reg [9:0] _zz_233; + reg [9:0] _zz_234; + reg [9:0] _zz_235; + reg [9:0] _zz_236; reg _zz_237; reg _zz_238; - reg [9:0] _zz_239; - reg [9:0] _zz_240; - reg [9:0] _zz_241; - reg [9:0] _zz_242; + reg _zz_239; + reg _zz_240; + reg _zz_241; + reg _zz_242; reg _zz_243; - reg _zz_244; - reg _zz_245; - reg _zz_246; + reg [9:0] _zz_244; + reg [9:0] _zz_245; + reg [9:0] _zz_246; + reg [9:0] _zz_247; + reg _zz_248; + reg _zz_249; + reg _zz_250; + reg _zz_251; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -173,11 +173,6 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_247; - wire _zz_248; - wire _zz_249; - wire _zz_250; - wire _zz_251; wire _zz_252; wire _zz_253; wire _zz_254; @@ -189,12 +184,12 @@ module VexRiscv ( wire _zz_260; wire _zz_261; wire _zz_262; - wire [1:0] _zz_263; + wire _zz_263; wire _zz_264; wire _zz_265; wire _zz_266; wire _zz_267; - wire _zz_268; + wire [1:0] _zz_268; wire _zz_269; wire _zz_270; wire _zz_271; @@ -229,16 +224,16 @@ module VexRiscv ( wire _zz_300; wire _zz_301; wire _zz_302; - wire [1:0] _zz_303; + wire _zz_303; wire _zz_304; - wire [32:0] _zz_305; - wire [31:0] _zz_306; - wire [32:0] _zz_307; - wire [0:0] _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire [0:0] _zz_312; + wire _zz_305; + wire _zz_306; + wire _zz_307; + wire [1:0] _zz_308; + wire _zz_309; + wire [32:0] _zz_310; + wire [31:0] _zz_311; + wire [32:0] _zz_312; wire [0:0] _zz_313; wire [0:0] _zz_314; wire [0:0] _zz_315; @@ -254,69 +249,69 @@ module VexRiscv ( wire [0:0] _zz_325; wire [0:0] _zz_326; wire [0:0] _zz_327; - wire [3:0] _zz_328; - wire [2:0] _zz_329; - wire [31:0] _zz_330; - wire [2:0] _zz_331; - wire [2:0] _zz_332; - wire [0:0] _zz_333; - wire [1:0] _zz_334; - wire [0:0] _zz_335; - wire [1:0] _zz_336; - wire [0:0] _zz_337; + wire [0:0] _zz_328; + wire [0:0] _zz_329; + wire [0:0] _zz_330; + wire [0:0] _zz_331; + wire [0:0] _zz_332; + wire [3:0] _zz_333; + wire [2:0] _zz_334; + wire [31:0] _zz_335; + wire [2:0] _zz_336; + wire [2:0] _zz_337; wire [0:0] _zz_338; - wire [0:0] _zz_339; + wire [1:0] _zz_339; wire [0:0] _zz_340; - wire [0:0] _zz_341; + wire [1:0] _zz_341; wire [0:0] _zz_342; wire [0:0] _zz_343; wire [0:0] _zz_344; - wire [1:0] _zz_345; + wire [0:0] _zz_345; wire [0:0] _zz_346; - wire [2:0] _zz_347; - wire [4:0] _zz_348; - wire [11:0] _zz_349; - wire [11:0] _zz_350; - wire [31:0] _zz_351; - wire [31:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire [31:0] _zz_355; + wire [0:0] _zz_347; + wire [0:0] _zz_348; + wire [0:0] _zz_349; + wire [1:0] _zz_350; + wire [0:0] _zz_351; + wire [2:0] _zz_352; + wire [4:0] _zz_353; + wire [11:0] _zz_354; + wire [11:0] _zz_355; wire [31:0] _zz_356; wire [31:0] _zz_357; - wire [19:0] _zz_358; - wire [11:0] _zz_359; - wire [11:0] _zz_360; - wire [1:0] _zz_361; - wire [1:0] _zz_362; - wire [0:0] _zz_363; - wire [5:0] _zz_364; - wire [33:0] _zz_365; - wire [32:0] _zz_366; - wire [33:0] _zz_367; - wire [32:0] _zz_368; - wire [33:0] _zz_369; - wire [32:0] _zz_370; - wire [0:0] _zz_371; - wire [5:0] _zz_372; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire [31:0] _zz_360; + wire [31:0] _zz_361; + wire [31:0] _zz_362; + wire [19:0] _zz_363; + wire [11:0] _zz_364; + wire [11:0] _zz_365; + wire [1:0] _zz_366; + wire [1:0] _zz_367; + wire [0:0] _zz_368; + wire [5:0] _zz_369; + wire [33:0] _zz_370; + wire [32:0] _zz_371; + wire [33:0] _zz_372; wire [32:0] _zz_373; - wire [31:0] _zz_374; - wire [31:0] _zz_375; - wire [32:0] _zz_376; - wire [32:0] _zz_377; + wire [33:0] _zz_374; + wire [32:0] _zz_375; + wire [0:0] _zz_376; + wire [5:0] _zz_377; wire [32:0] _zz_378; - wire [32:0] _zz_379; - wire [0:0] _zz_380; + wire [31:0] _zz_379; + wire [31:0] _zz_380; wire [32:0] _zz_381; - wire [0:0] _zz_382; + wire [32:0] _zz_382; wire [32:0] _zz_383; - wire [0:0] _zz_384; - wire [31:0] _zz_385; - wire [0:0] _zz_386; + wire [32:0] _zz_384; + wire [0:0] _zz_385; + wire [32:0] _zz_386; wire [0:0] _zz_387; - wire [0:0] _zz_388; + wire [32:0] _zz_388; wire [0:0] _zz_389; - wire [0:0] _zz_390; + wire [31:0] _zz_390; wire [0:0] _zz_391; wire [0:0] _zz_392; wire [0:0] _zz_393; @@ -357,224 +352,229 @@ module VexRiscv ( wire [0:0] _zz_428; wire [0:0] _zz_429; wire [0:0] _zz_430; - wire [26:0] _zz_431; - wire _zz_432; - wire _zz_433; - wire [1:0] _zz_434; - wire [31:0] _zz_435; - wire [31:0] _zz_436; - wire [31:0] _zz_437; + wire [0:0] _zz_431; + wire [0:0] _zz_432; + wire [0:0] _zz_433; + wire [0:0] _zz_434; + wire [0:0] _zz_435; + wire [26:0] _zz_436; + wire _zz_437; wire _zz_438; - wire [0:0] _zz_439; - wire [17:0] _zz_440; + wire [1:0] _zz_439; + wire [31:0] _zz_440; wire [31:0] _zz_441; wire [31:0] _zz_442; - wire [31:0] _zz_443; - wire _zz_444; - wire [0:0] _zz_445; - wire [11:0] _zz_446; + wire _zz_443; + wire [0:0] _zz_444; + wire [17:0] _zz_445; + wire [31:0] _zz_446; wire [31:0] _zz_447; wire [31:0] _zz_448; - wire [31:0] _zz_449; - wire _zz_450; - wire [0:0] _zz_451; - wire [5:0] _zz_452; + wire _zz_449; + wire [0:0] _zz_450; + wire [11:0] _zz_451; + wire [31:0] _zz_452; wire [31:0] _zz_453; wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire _zz_456; - wire _zz_457; + wire _zz_455; + wire [0:0] _zz_456; + wire [5:0] _zz_457; wire [31:0] _zz_458; - wire [0:0] _zz_459; - wire [1:0] _zz_460; - wire [0:0] _zz_461; - wire [0:0] _zz_462; - wire _zz_463; + wire [31:0] _zz_459; + wire [31:0] _zz_460; + wire _zz_461; + wire _zz_462; + wire [31:0] _zz_463; wire [0:0] _zz_464; - wire [28:0] _zz_465; - wire [31:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; + wire [1:0] _zz_465; + wire [0:0] _zz_466; + wire [0:0] _zz_467; + wire _zz_468; wire [0:0] _zz_469; - wire [0:0] _zz_470; - wire [1:0] _zz_471; - wire [1:0] _zz_472; - wire _zz_473; + wire [28:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; wire [0:0] _zz_474; - wire [24:0] _zz_475; - wire [31:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; - wire [31:0] _zz_479; - wire [31:0] _zz_480; + wire [0:0] _zz_475; + wire [1:0] _zz_476; + wire [1:0] _zz_477; + wire _zz_478; + wire [0:0] _zz_479; + wire [24:0] _zz_480; wire [31:0] _zz_481; - wire [0:0] _zz_482; - wire [0:0] _zz_483; - wire [2:0] _zz_484; - wire [2:0] _zz_485; - wire _zz_486; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire [31:0] _zz_486; wire [0:0] _zz_487; - wire [21:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; - wire [31:0] _zz_491; - wire [31:0] _zz_492; - wire _zz_493; - wire _zz_494; + wire [0:0] _zz_488; + wire [2:0] _zz_489; + wire [2:0] _zz_490; + wire _zz_491; + wire [0:0] _zz_492; + wire [21:0] _zz_493; + wire [31:0] _zz_494; wire [31:0] _zz_495; wire [31:0] _zz_496; - wire [1:0] _zz_497; - wire [1:0] _zz_498; + wire [31:0] _zz_497; + wire _zz_498; wire _zz_499; - wire [0:0] _zz_500; - wire [18:0] _zz_501; - wire [31:0] _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire [31:0] _zz_505; - wire [31:0] _zz_506; + wire [31:0] _zz_500; + wire [31:0] _zz_501; + wire [1:0] _zz_502; + wire [1:0] _zz_503; + wire _zz_504; + wire [0:0] _zz_505; + wire [18:0] _zz_506; wire [31:0] _zz_507; - wire _zz_508; - wire [0:0] _zz_509; - wire [0:0] _zz_510; - wire _zz_511; - wire [0:0] _zz_512; - wire [15:0] _zz_513; - wire [31:0] _zz_514; - wire [31:0] _zz_515; + wire [31:0] _zz_508; + wire [31:0] _zz_509; + wire [31:0] _zz_510; + wire [31:0] _zz_511; + wire [31:0] _zz_512; + wire _zz_513; + wire [0:0] _zz_514; + wire [0:0] _zz_515; wire _zz_516; wire [0:0] _zz_517; - wire [0:0] _zz_518; + wire [15:0] _zz_518; wire [31:0] _zz_519; wire [31:0] _zz_520; wire _zz_521; - wire [5:0] _zz_522; - wire [5:0] _zz_523; - wire _zz_524; - wire [0:0] _zz_525; - wire [11:0] _zz_526; - wire [31:0] _zz_527; - wire [31:0] _zz_528; - wire [31:0] _zz_529; - wire [31:0] _zz_530; - wire _zz_531; - wire [0:0] _zz_532; - wire [2:0] _zz_533; - wire _zz_534; - wire [0:0] _zz_535; - wire [0:0] _zz_536; - wire _zz_537; - wire [4:0] _zz_538; - wire [4:0] _zz_539; - wire _zz_540; + wire [0:0] _zz_522; + wire [0:0] _zz_523; + wire [31:0] _zz_524; + wire [31:0] _zz_525; + wire _zz_526; + wire [5:0] _zz_527; + wire [5:0] _zz_528; + wire _zz_529; + wire [0:0] _zz_530; + wire [11:0] _zz_531; + wire [31:0] _zz_532; + wire [31:0] _zz_533; + wire [31:0] _zz_534; + wire [31:0] _zz_535; + wire _zz_536; + wire [0:0] _zz_537; + wire [2:0] _zz_538; + wire _zz_539; + wire [0:0] _zz_540; wire [0:0] _zz_541; - wire [8:0] _zz_542; - wire [31:0] _zz_543; - wire [31:0] _zz_544; - wire [31:0] _zz_545; - wire _zz_546; - wire [0:0] _zz_547; - wire [0:0] _zz_548; + wire _zz_542; + wire [4:0] _zz_543; + wire [4:0] _zz_544; + wire _zz_545; + wire [0:0] _zz_546; + wire [8:0] _zz_547; + wire [31:0] _zz_548; wire [31:0] _zz_549; wire [31:0] _zz_550; - wire [31:0] _zz_551; - wire [31:0] _zz_552; - wire [31:0] _zz_553; + wire _zz_551; + wire [0:0] _zz_552; + wire [0:0] _zz_553; wire [31:0] _zz_554; - wire [0:0] _zz_555; - wire [2:0] _zz_556; - wire [0:0] _zz_557; - wire [5:0] _zz_558; - wire [1:0] _zz_559; - wire [1:0] _zz_560; - wire _zz_561; + wire [31:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire [31:0] _zz_559; + wire [0:0] _zz_560; + wire [2:0] _zz_561; wire [0:0] _zz_562; - wire [6:0] _zz_563; - wire [31:0] _zz_564; - wire [31:0] _zz_565; - wire [31:0] _zz_566; - wire [31:0] _zz_567; - wire [31:0] _zz_568; + wire [5:0] _zz_563; + wire [1:0] _zz_564; + wire [1:0] _zz_565; + wire _zz_566; + wire [0:0] _zz_567; + wire [6:0] _zz_568; wire [31:0] _zz_569; wire [31:0] _zz_570; - wire _zz_571; - wire [0:0] _zz_572; - wire [0:0] _zz_573; - wire _zz_574; - wire [0:0] _zz_575; - wire [3:0] _zz_576; - wire _zz_577; + wire [31:0] _zz_571; + wire [31:0] _zz_572; + wire [31:0] _zz_573; + wire [31:0] _zz_574; + wire [31:0] _zz_575; + wire _zz_576; + wire [0:0] _zz_577; wire [0:0] _zz_578; - wire [0:0] _zz_579; + wire _zz_579; wire [0:0] _zz_580; - wire [0:0] _zz_581; + wire [3:0] _zz_581; wire _zz_582; wire [0:0] _zz_583; - wire [4:0] _zz_584; - wire [31:0] _zz_585; - wire [31:0] _zz_586; - wire [31:0] _zz_587; - wire [31:0] _zz_588; - wire [31:0] _zz_589; + wire [0:0] _zz_584; + wire [0:0] _zz_585; + wire [0:0] _zz_586; + wire _zz_587; + wire [0:0] _zz_588; + wire [4:0] _zz_589; wire [31:0] _zz_590; wire [31:0] _zz_591; wire [31:0] _zz_592; - wire _zz_593; - wire [0:0] _zz_594; - wire [1:0] _zz_595; + wire [31:0] _zz_593; + wire [31:0] _zz_594; + wire [31:0] _zz_595; wire [31:0] _zz_596; wire [31:0] _zz_597; - wire [31:0] _zz_598; - wire [31:0] _zz_599; - wire [31:0] _zz_600; - wire _zz_601; - wire [4:0] _zz_602; - wire [4:0] _zz_603; - wire _zz_604; - wire [0:0] _zz_605; - wire [2:0] _zz_606; - wire [31:0] _zz_607; - wire [31:0] _zz_608; - wire [31:0] _zz_609; - wire _zz_610; - wire [31:0] _zz_611; - wire _zz_612; - wire [0:0] _zz_613; - wire [2:0] _zz_614; - wire [0:0] _zz_615; - wire [0:0] _zz_616; - wire [2:0] _zz_617; - wire [2:0] _zz_618; - wire _zz_619; + wire _zz_598; + wire [0:0] _zz_599; + wire [1:0] _zz_600; + wire [31:0] _zz_601; + wire [31:0] _zz_602; + wire [31:0] _zz_603; + wire [31:0] _zz_604; + wire [31:0] _zz_605; + wire _zz_606; + wire [4:0] _zz_607; + wire [4:0] _zz_608; + wire _zz_609; + wire [0:0] _zz_610; + wire [2:0] _zz_611; + wire [31:0] _zz_612; + wire [31:0] _zz_613; + wire [31:0] _zz_614; + wire _zz_615; + wire [31:0] _zz_616; + wire _zz_617; + wire [0:0] _zz_618; + wire [2:0] _zz_619; wire [0:0] _zz_620; wire [0:0] _zz_621; - wire [31:0] _zz_622; - wire [31:0] _zz_623; - wire [31:0] _zz_624; - wire [31:0] _zz_625; - wire _zz_626; - wire [0:0] _zz_627; - wire [0:0] _zz_628; + wire [2:0] _zz_622; + wire [2:0] _zz_623; + wire _zz_624; + wire [0:0] _zz_625; + wire [0:0] _zz_626; + wire [31:0] _zz_627; + wire [31:0] _zz_628; wire [31:0] _zz_629; wire [31:0] _zz_630; wire _zz_631; wire [0:0] _zz_632; wire [0:0] _zz_633; - wire [0:0] _zz_634; - wire [1:0] _zz_635; - wire [1:0] _zz_636; - wire [1:0] _zz_637; + wire [31:0] _zz_634; + wire [31:0] _zz_635; + wire _zz_636; + wire [0:0] _zz_637; wire [0:0] _zz_638; wire [0:0] _zz_639; - wire [31:0] _zz_640; - wire [31:0] _zz_641; - wire [31:0] _zz_642; - wire [31:0] _zz_643; - wire [31:0] _zz_644; + wire [1:0] _zz_640; + wire [1:0] _zz_641; + wire [1:0] _zz_642; + wire [0:0] _zz_643; + wire [0:0] _zz_644; wire [31:0] _zz_645; wire [31:0] _zz_646; wire [31:0] _zz_647; wire [31:0] _zz_648; + wire [31:0] _zz_649; + wire [31:0] _zz_650; + wire [31:0] _zz_651; + wire [31:0] _zz_652; + wire [31:0] _zz_653; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; @@ -1262,37 +1262,32 @@ module VexRiscv ( reg [31:0] _zz_118; wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_119; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_120; - wire _zz_121; - wire _zz_122; - wire _zz_123; - wire _zz_124; + reg _zz_120; + reg _zz_121; + reg _zz_122; + reg [4:0] _zz_123; + reg [31:0] _zz_124; wire _zz_125; + wire _zz_126; + wire _zz_127; + wire _zz_128; + wire _zz_129; + wire _zz_130; wire execute_BranchPlugin_eq; - wire [2:0] _zz_126; - reg _zz_127; - reg _zz_128; + wire [2:0] _zz_131; + reg _zz_132; + reg _zz_133; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_129; - reg [10:0] _zz_130; - wire _zz_131; - reg [19:0] _zz_132; - wire _zz_133; - reg [18:0] _zz_134; - reg [31:0] _zz_135; + wire _zz_134; + reg [10:0] _zz_135; + wire _zz_136; + reg [19:0] _zz_137; + wire _zz_138; + reg [18:0] _zz_139; + reg [31:0] _zz_140; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] _zz_136; + reg [1:0] _zz_141; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1349,12 +1344,12 @@ module VexRiscv ( reg [21:0] CsrPlugin_satp_PPN; reg [8:0] CsrPlugin_satp_ASID; reg [0:0] CsrPlugin_satp_MODE; - wire _zz_137; - wire _zz_138; - wire _zz_139; - wire _zz_140; - wire _zz_141; wire _zz_142; + wire _zz_143; + wire _zz_144; + wire _zz_145; + wire _zz_146; + wire _zz_147; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1367,8 +1362,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_143; - wire _zz_144; + wire [1:0] _zz_148; + wire _zz_149; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1416,20 +1411,20 @@ module VexRiscv ( wire memory_MulDivIterativePlugin_div_counter_willOverflow; reg memory_MulDivIterativePlugin_div_done; reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_145; + wire [31:0] _zz_150; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [31:0] _zz_146; - wire _zz_147; - wire _zz_148; - reg [32:0] _zz_149; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_150; wire [31:0] _zz_151; - reg [31:0] _zz_152; - wire [31:0] _zz_153; + wire _zz_152; + wire _zz_153; + reg [32:0] _zz_154; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_155; + wire [31:0] _zz_156; + reg [31:0] _zz_157; + wire [31:0] _zz_158; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1519,11 +1514,6 @@ module VexRiscv ( reg execute_CsrPlugin_csr_4032; reg execute_CsrPlugin_csr_2496; reg execute_CsrPlugin_csr_3520; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; reg [31:0] _zz_159; reg [31:0] _zz_160; reg [31:0] _zz_161; @@ -1543,16 +1533,21 @@ module VexRiscv ( reg [31:0] _zz_175; reg [31:0] _zz_176; reg [31:0] _zz_177; - reg [2:0] _zz_178; - reg _zz_179; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [2:0] _zz_183; + reg _zz_184; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_180; - wire _zz_181; - wire _zz_182; - wire _zz_183; - wire _zz_184; - wire _zz_185; - reg _zz_186; + reg [2:0] _zz_185; + wire _zz_186; + wire _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + reg _zz_191; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] _zz_1_string; @@ -1638,417 +1633,417 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_247 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_248 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_249 = 1'b1; - assign _zz_250 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_251 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_252 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_254 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_255 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_256 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_257 = ((_zz_192 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_260 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_264 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); - assign _zz_265 = (! dataCache_1_io_cpu_execute_refilling); - assign _zz_266 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_267 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); - assign _zz_268 = MmuPlugin_shared_portSortedOh[0]; - assign _zz_269 = MmuPlugin_shared_portSortedOh[1]; - assign _zz_270 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_271 = (1'b0 || (! 1'b1)); - assign _zz_272 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_273 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_274 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_275 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_276 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_277 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_278 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_279 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_280 = (! memory_arbitration_isStuck); - assign _zz_281 = (iBus_cmd_valid || (_zz_178 != 3'b000)); - assign _zz_282 = (_zz_221 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_283 = (MmuPlugin_shared_refills != 2'b00); - assign _zz_284 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); - assign _zz_285 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); - assign _zz_286 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); - assign _zz_287 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); - assign _zz_288 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); - assign _zz_289 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); - assign _zz_290 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); - assign _zz_291 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); - assign _zz_292 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); - assign _zz_293 = ((_zz_137 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); - assign _zz_294 = ((_zz_138 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); - assign _zz_295 = ((_zz_139 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); - assign _zz_296 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_297 = ((_zz_137 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); - assign _zz_298 = ((_zz_138 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); - assign _zz_299 = ((_zz_139 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); - assign _zz_300 = ((_zz_140 && 1'b1) && (! 1'b0)); - assign _zz_301 = ((_zz_141 && 1'b1) && (! 1'b0)); - assign _zz_302 = ((_zz_142 && 1'b1) && (! 1'b0)); - assign _zz_303 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_304 = execute_INSTRUCTION[13]; - assign _zz_305 = ($signed(_zz_307) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_306 = _zz_305[31 : 0]; - assign _zz_307 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_308 = _zz_94[34 : 34]; - assign _zz_309 = _zz_94[33 : 33]; - assign _zz_310 = _zz_94[32 : 32]; - assign _zz_311 = _zz_94[31 : 31]; - assign _zz_312 = _zz_94[28 : 28]; - assign _zz_313 = _zz_94[21 : 21]; - assign _zz_314 = _zz_94[20 : 20]; - assign _zz_315 = _zz_94[19 : 19]; - assign _zz_316 = _zz_94[13 : 13]; - assign _zz_317 = _zz_94[12 : 12]; - assign _zz_318 = _zz_94[11 : 11]; - assign _zz_319 = _zz_94[17 : 17]; - assign _zz_320 = _zz_94[5 : 5]; - assign _zz_321 = _zz_94[3 : 3]; - assign _zz_322 = _zz_94[18 : 18]; - assign _zz_323 = _zz_94[10 : 10]; - assign _zz_324 = _zz_94[16 : 16]; - assign _zz_325 = _zz_94[15 : 15]; - assign _zz_326 = _zz_94[4 : 4]; - assign _zz_327 = _zz_94[0 : 0]; - assign _zz_328 = (_zz_55 - 4'b0001); - assign _zz_329 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_330 = {29'd0, _zz_329}; - assign _zz_331 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_332 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_333 = MmuPlugin_ports_0_entryToReplace_willIncrement; - assign _zz_334 = {1'd0, _zz_333}; - assign _zz_335 = MmuPlugin_ports_1_entryToReplace_willIncrement; - assign _zz_336 = {1'd0, _zz_335}; - assign _zz_337 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; - assign _zz_338 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; - assign _zz_339 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; - assign _zz_340 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; - assign _zz_341 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; - assign _zz_342 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; - assign _zz_343 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; - assign _zz_344 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; - assign _zz_345 = (_zz_90 - 2'b01); - assign _zz_346 = execute_SRC_LESS; - assign _zz_347 = 3'b100; - assign _zz_348 = execute_INSTRUCTION[19 : 15]; - assign _zz_349 = execute_INSTRUCTION[31 : 20]; - assign _zz_350 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_351 = ($signed(_zz_352) + $signed(_zz_355)); - assign _zz_352 = ($signed(_zz_353) + $signed(_zz_354)); - assign _zz_353 = execute_SRC1; - assign _zz_354 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_355 = (execute_SRC_USE_SUB_LESS ? _zz_356 : _zz_357); - assign _zz_356 = 32'h00000001; - assign _zz_357 = 32'h0; - assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_359 = execute_INSTRUCTION[31 : 20]; - assign _zz_360 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_361 = (_zz_143 & (~ _zz_362)); - assign _zz_362 = (_zz_143 - 2'b01); - assign _zz_363 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_364 = {5'd0, _zz_363}; - assign _zz_365 = (_zz_367 + _zz_369); - assign _zz_366 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_367 = {{1{_zz_366[32]}}, _zz_366}; - assign _zz_368 = _zz_370; - assign _zz_369 = {{1{_zz_368[32]}}, _zz_368}; - assign _zz_370 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_371 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_372 = {5'd0, _zz_371}; - assign _zz_373 = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_374 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_375 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_376 = {_zz_145,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_377 = _zz_378; - assign _zz_378 = _zz_379; - assign _zz_379 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_146) : _zz_146)} + _zz_381); - assign _zz_380 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_381 = {32'd0, _zz_380}; - assign _zz_382 = _zz_148; - assign _zz_383 = {32'd0, _zz_382}; - assign _zz_384 = _zz_147; - assign _zz_385 = {31'd0, _zz_384}; - assign _zz_386 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_387 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_388 = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_391 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_392 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_393 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_394 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_395 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_252 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_253 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_254 = 1'b1; + assign _zz_255 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_256 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_257 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_258 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_259 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_260 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_261 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_262 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_263 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_264 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_265 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_268 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_269 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign _zz_270 = (! dataCache_1_io_cpu_execute_refilling); + assign _zz_271 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_272 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign _zz_273 = MmuPlugin_shared_portSortedOh[0]; + assign _zz_274 = MmuPlugin_shared_portSortedOh[1]; + assign _zz_275 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_276 = (1'b0 || (! 1'b1)); + assign _zz_277 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_278 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_279 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_280 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_281 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_282 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_283 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_284 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_285 = (! memory_arbitration_isStuck); + assign _zz_286 = (iBus_cmd_valid || (_zz_183 != 3'b000)); + assign _zz_287 = (_zz_226 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_288 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_289 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign _zz_290 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign _zz_291 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign _zz_292 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign _zz_293 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign _zz_294 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign _zz_295 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign _zz_296 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign _zz_297 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign _zz_298 = ((_zz_142 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign _zz_299 = ((_zz_143 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign _zz_300 = ((_zz_144 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign _zz_301 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_302 = ((_zz_142 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign _zz_303 = ((_zz_143 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign _zz_304 = ((_zz_144 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign _zz_305 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_306 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_307 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_308 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_309 = execute_INSTRUCTION[13]; + assign _zz_310 = ($signed(_zz_312) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_311 = _zz_310[31 : 0]; + assign _zz_312 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_313 = _zz_94[34 : 34]; + assign _zz_314 = _zz_94[33 : 33]; + assign _zz_315 = _zz_94[32 : 32]; + assign _zz_316 = _zz_94[31 : 31]; + assign _zz_317 = _zz_94[28 : 28]; + assign _zz_318 = _zz_94[21 : 21]; + assign _zz_319 = _zz_94[20 : 20]; + assign _zz_320 = _zz_94[19 : 19]; + assign _zz_321 = _zz_94[13 : 13]; + assign _zz_322 = _zz_94[12 : 12]; + assign _zz_323 = _zz_94[11 : 11]; + assign _zz_324 = _zz_94[17 : 17]; + assign _zz_325 = _zz_94[5 : 5]; + assign _zz_326 = _zz_94[3 : 3]; + assign _zz_327 = _zz_94[18 : 18]; + assign _zz_328 = _zz_94[10 : 10]; + assign _zz_329 = _zz_94[16 : 16]; + assign _zz_330 = _zz_94[15 : 15]; + assign _zz_331 = _zz_94[4 : 4]; + assign _zz_332 = _zz_94[0 : 0]; + assign _zz_333 = (_zz_55 - 4'b0001); + assign _zz_334 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_335 = {29'd0, _zz_334}; + assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_338 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_339 = {1'd0, _zz_338}; + assign _zz_340 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_341 = {1'd0, _zz_340}; + assign _zz_342 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; + assign _zz_343 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; + assign _zz_344 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; + assign _zz_345 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; + assign _zz_346 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; + assign _zz_347 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; + assign _zz_348 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; + assign _zz_349 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; + assign _zz_350 = (_zz_90 - 2'b01); + assign _zz_351 = execute_SRC_LESS; + assign _zz_352 = 3'b100; + assign _zz_353 = execute_INSTRUCTION[19 : 15]; + assign _zz_354 = execute_INSTRUCTION[31 : 20]; + assign _zz_355 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_356 = ($signed(_zz_357) + $signed(_zz_360)); + assign _zz_357 = ($signed(_zz_358) + $signed(_zz_359)); + assign _zz_358 = execute_SRC1; + assign _zz_359 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_360 = (execute_SRC_USE_SUB_LESS ? _zz_361 : _zz_362); + assign _zz_361 = 32'h00000001; + assign _zz_362 = 32'h0; + assign _zz_363 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_364 = execute_INSTRUCTION[31 : 20]; + assign _zz_365 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_366 = (_zz_148 & (~ _zz_367)); + assign _zz_367 = (_zz_148 - 2'b01); + assign _zz_368 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_369 = {5'd0, _zz_368}; + assign _zz_370 = (_zz_372 + _zz_374); + assign _zz_371 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_372 = {{1{_zz_371[32]}}, _zz_371}; + assign _zz_373 = _zz_375; + assign _zz_374 = {{1{_zz_373[32]}}, _zz_373}; + assign _zz_375 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_376 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_377 = {5'd0, _zz_376}; + assign _zz_378 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_379 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_380 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_381 = {_zz_150,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_382 = _zz_383; + assign _zz_383 = _zz_384; + assign _zz_384 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_151) : _zz_151)} + _zz_386); + assign _zz_385 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_386 = {32'd0, _zz_385}; + assign _zz_387 = _zz_153; + assign _zz_388 = {32'd0, _zz_387}; + assign _zz_389 = _zz_152; + assign _zz_390 = {31'd0, _zz_389}; + assign _zz_391 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_392 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_393 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_394 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_395 = execute_CsrPlugin_writeData[3 : 3]; assign _zz_396 = execute_CsrPlugin_writeData[5 : 5]; assign _zz_397 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_398 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_399 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_400 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_401 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_402 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_403 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_404 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_405 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_406 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_407 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_408 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_409 = execute_CsrPlugin_writeData[0 : 0]; - assign _zz_410 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_411 = execute_CsrPlugin_writeData[2 : 2]; - assign _zz_412 = execute_CsrPlugin_writeData[4 : 4]; - assign _zz_413 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_414 = execute_CsrPlugin_writeData[6 : 6]; - assign _zz_415 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_416 = execute_CsrPlugin_writeData[8 : 8]; - assign _zz_417 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_418 = execute_CsrPlugin_writeData[12 : 12]; - assign _zz_419 = execute_CsrPlugin_writeData[13 : 13]; - assign _zz_420 = execute_CsrPlugin_writeData[15 : 15]; - assign _zz_421 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_422 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_423 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_424 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_425 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_398 = execute_CsrPlugin_writeData[19 : 19]; + assign _zz_399 = execute_CsrPlugin_writeData[18 : 18]; + assign _zz_400 = execute_CsrPlugin_writeData[17 : 17]; + assign _zz_401 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_402 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_403 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_404 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_405 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_406 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_407 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_408 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_409 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_410 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_411 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_412 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_413 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_414 = execute_CsrPlugin_writeData[0 : 0]; + assign _zz_415 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_416 = execute_CsrPlugin_writeData[2 : 2]; + assign _zz_417 = execute_CsrPlugin_writeData[4 : 4]; + assign _zz_418 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_419 = execute_CsrPlugin_writeData[6 : 6]; + assign _zz_420 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_421 = execute_CsrPlugin_writeData[8 : 8]; + assign _zz_422 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_423 = execute_CsrPlugin_writeData[12 : 12]; + assign _zz_424 = execute_CsrPlugin_writeData[13 : 13]; + assign _zz_425 = execute_CsrPlugin_writeData[15 : 15]; assign _zz_426 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_427 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_428 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_429 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_430 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_431 = (iBus_cmd_payload_address >>> 5); - assign _zz_432 = 1'b1; - assign _zz_433 = 1'b1; - assign _zz_434 = {_zz_59,_zz_58}; - assign _zz_435 = 32'h0000107f; - assign _zz_436 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_437 = 32'h00002073; - assign _zz_438 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_439 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_440 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_441) == 32'h00000003),{(_zz_442 == _zz_443),{_zz_444,{_zz_445,_zz_446}}}}}}; - assign _zz_441 = 32'h0000505f; - assign _zz_442 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_443 = 32'h00000063; - assign _zz_444 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_445 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); - assign _zz_446 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_447) == 32'h00001013),{(_zz_448 == _zz_449),{_zz_450,{_zz_451,_zz_452}}}}}}; - assign _zz_447 = 32'hfc00305f; - assign _zz_448 = (decode_INSTRUCTION & 32'h01f0707f); - assign _zz_449 = 32'h0000500f; - assign _zz_450 = ((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013); - assign _zz_451 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_452 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_453) == 32'h12000073),{(_zz_454 == _zz_455),{_zz_456,_zz_457}}}}}; - assign _zz_453 = 32'hfe007fff; - assign _zz_454 = (decode_INSTRUCTION & 32'hdfffffff); - assign _zz_455 = 32'h10200073; - assign _zz_456 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_457 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); - assign _zz_458 = 32'h02004064; - assign _zz_459 = _zz_102; - assign _zz_460 = {_zz_100,_zz_101}; - assign _zz_461 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_462 = 1'b0; - assign _zz_463 = (((decode_INSTRUCTION & _zz_466) == 32'h00000050) != 1'b0); - assign _zz_464 = ((_zz_467 == _zz_468) != 1'b0); - assign _zz_465 = {({_zz_469,_zz_470} != 2'b00),{(_zz_471 != _zz_472),{_zz_473,{_zz_474,_zz_475}}}}; - assign _zz_466 = 32'h02203050; - assign _zz_467 = (decode_INSTRUCTION & 32'h02403050); - assign _zz_468 = 32'h00000050; - assign _zz_469 = ((decode_INSTRUCTION & _zz_476) == 32'h00001050); - assign _zz_470 = ((decode_INSTRUCTION & _zz_477) == 32'h00002050); - assign _zz_471 = {_zz_96,(_zz_478 == _zz_479)}; - assign _zz_472 = 2'b00; - assign _zz_473 = ((_zz_480 == _zz_481) != 1'b0); - assign _zz_474 = ({_zz_482,_zz_483} != 2'b00); - assign _zz_475 = {(_zz_484 != _zz_485),{_zz_486,{_zz_487,_zz_488}}}; - assign _zz_476 = 32'h00001050; - assign _zz_477 = 32'h00002050; - assign _zz_478 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_479 = 32'h00000004; - assign _zz_480 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_481 = 32'h00000040; - assign _zz_482 = ((decode_INSTRUCTION & _zz_489) == 32'h00005010); - assign _zz_483 = ((decode_INSTRUCTION & _zz_490) == 32'h00005020); - assign _zz_484 = {(_zz_491 == _zz_492),{_zz_493,_zz_494}}; - assign _zz_485 = 3'b000; - assign _zz_486 = ((_zz_495 == _zz_496) != 1'b0); - assign _zz_487 = (_zz_100 != 1'b0); - assign _zz_488 = {(_zz_497 != _zz_498),{_zz_499,{_zz_500,_zz_501}}}; - assign _zz_489 = 32'h00007034; - assign _zz_490 = 32'h02007064; - assign _zz_491 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_492 = 32'h40001010; - assign _zz_493 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_494 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_495 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_496 = 32'h00001000; - assign _zz_497 = {(_zz_502 == _zz_503),(_zz_504 == _zz_505)}; - assign _zz_498 = 2'b00; - assign _zz_499 = ((_zz_506 == _zz_507) != 1'b0); - assign _zz_500 = (_zz_508 != 1'b0); - assign _zz_501 = {(_zz_509 != _zz_510),{_zz_511,{_zz_512,_zz_513}}}; - assign _zz_502 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_503 = 32'h00002000; - assign _zz_504 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_505 = 32'h00001000; - assign _zz_506 = (decode_INSTRUCTION & 32'h02003050); - assign _zz_507 = 32'h02000050; - assign _zz_508 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); - assign _zz_509 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_510 = 1'b0; - assign _zz_511 = ({(_zz_514 == _zz_515),{_zz_516,{_zz_517,_zz_518}}} != 4'b0000); - assign _zz_512 = ((_zz_519 == _zz_520) != 1'b0); - assign _zz_513 = {(_zz_521 != 1'b0),{(_zz_522 != _zz_523),{_zz_524,{_zz_525,_zz_526}}}}; - assign _zz_514 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_515 = 32'h00000020; - assign _zz_516 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_517 = ((decode_INSTRUCTION & _zz_527) == 32'h08000020); - assign _zz_518 = ((decode_INSTRUCTION & _zz_528) == 32'h00000020); - assign _zz_519 = (decode_INSTRUCTION & 32'h10000008); - assign _zz_520 = 32'h00000008; - assign _zz_521 = ((decode_INSTRUCTION & 32'h10000008) == 32'h10000008); - assign _zz_522 = {(_zz_529 == _zz_530),{_zz_531,{_zz_532,_zz_533}}}; - assign _zz_523 = 6'h0; - assign _zz_524 = ({_zz_534,{_zz_535,_zz_536}} != 3'b000); - assign _zz_525 = (_zz_537 != 1'b0); - assign _zz_526 = {(_zz_538 != _zz_539),{_zz_540,{_zz_541,_zz_542}}}; - assign _zz_527 = 32'h08000070; - assign _zz_528 = 32'h10000070; - assign _zz_529 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_530 = 32'h00002040; - assign _zz_531 = ((decode_INSTRUCTION & _zz_543) == 32'h00001040); - assign _zz_532 = (_zz_544 == _zz_545); - assign _zz_533 = {_zz_546,{_zz_547,_zz_548}}; - assign _zz_534 = ((decode_INSTRUCTION & _zz_549) == 32'h08000020); - assign _zz_535 = (_zz_550 == _zz_551); - assign _zz_536 = (_zz_552 == _zz_553); - assign _zz_537 = ((decode_INSTRUCTION & _zz_554) == 32'h00000010); - assign _zz_538 = {_zz_99,{_zz_555,_zz_556}}; - assign _zz_539 = 5'h0; - assign _zz_540 = ({_zz_557,_zz_558} != 7'h0); - assign _zz_541 = (_zz_559 != _zz_560); - assign _zz_542 = {_zz_561,{_zz_562,_zz_563}}; - assign _zz_543 = 32'h00001040; - assign _zz_544 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_545 = 32'h00000040; - assign _zz_546 = ((decode_INSTRUCTION & _zz_564) == 32'h00000040); - assign _zz_547 = (_zz_565 == _zz_566); - assign _zz_548 = (_zz_567 == _zz_568); - assign _zz_549 = 32'h08000020; - assign _zz_550 = (decode_INSTRUCTION & 32'h10000020); - assign _zz_551 = 32'h00000020; - assign _zz_552 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_553 = 32'h00000020; - assign _zz_554 = 32'h00000010; - assign _zz_555 = (_zz_569 == _zz_570); - assign _zz_556 = {_zz_571,{_zz_572,_zz_573}}; - assign _zz_557 = _zz_96; - assign _zz_558 = {_zz_574,{_zz_575,_zz_576}}; - assign _zz_559 = {_zz_98,_zz_577}; - assign _zz_560 = 2'b00; - assign _zz_561 = ({_zz_578,_zz_579} != 2'b00); - assign _zz_562 = (_zz_580 != _zz_581); - assign _zz_563 = {_zz_582,{_zz_583,_zz_584}}; - assign _zz_564 = 32'h02400040; - assign _zz_565 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_566 = 32'h0; - assign _zz_567 = (decode_INSTRUCTION & 32'h18002008); - assign _zz_568 = 32'h10002008; - assign _zz_569 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_570 = 32'h00002010; - assign _zz_571 = ((decode_INSTRUCTION & _zz_585) == 32'h00000010); - assign _zz_572 = (_zz_586 == _zz_587); - assign _zz_573 = (_zz_588 == _zz_589); - assign _zz_574 = ((decode_INSTRUCTION & _zz_590) == 32'h00001010); - assign _zz_575 = (_zz_591 == _zz_592); - assign _zz_576 = {_zz_593,{_zz_594,_zz_595}}; - assign _zz_577 = ((decode_INSTRUCTION & _zz_596) == 32'h00000020); - assign _zz_578 = _zz_98; - assign _zz_579 = (_zz_597 == _zz_598); - assign _zz_580 = (_zz_599 == _zz_600); - assign _zz_581 = 1'b0; - assign _zz_582 = (_zz_601 != 1'b0); - assign _zz_583 = (_zz_602 != _zz_603); - assign _zz_584 = {_zz_604,{_zz_605,_zz_606}}; - assign _zz_585 = 32'h00001030; - assign _zz_586 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_587 = 32'h00000020; - assign _zz_588 = (decode_INSTRUCTION & 32'h02002068); - assign _zz_589 = 32'h00002020; - assign _zz_590 = 32'h00001010; - assign _zz_591 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_592 = 32'h00002010; - assign _zz_593 = ((decode_INSTRUCTION & _zz_607) == 32'h00002008); - assign _zz_594 = (_zz_608 == _zz_609); - assign _zz_595 = {_zz_99,_zz_610}; - assign _zz_596 = 32'h00000070; - assign _zz_597 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_598 = 32'h0; - assign _zz_599 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_600 = 32'h00004010; - assign _zz_601 = ((decode_INSTRUCTION & _zz_611) == 32'h00002010); - assign _zz_602 = {_zz_612,{_zz_613,_zz_614}}; - assign _zz_603 = 5'h0; - assign _zz_604 = ({_zz_615,_zz_616} != 2'b00); - assign _zz_605 = (_zz_617 != _zz_618); - assign _zz_606 = {_zz_619,{_zz_620,_zz_621}}; - assign _zz_607 = 32'h00002008; - assign _zz_608 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_609 = 32'h00000010; - assign _zz_610 = ((decode_INSTRUCTION & _zz_622) == 32'h0); - assign _zz_611 = 32'h00006014; - assign _zz_612 = ((decode_INSTRUCTION & _zz_623) == 32'h0); - assign _zz_613 = (_zz_624 == _zz_625); - assign _zz_614 = {_zz_626,{_zz_627,_zz_628}}; - assign _zz_615 = _zz_97; - assign _zz_616 = (_zz_629 == _zz_630); - assign _zz_617 = {_zz_631,{_zz_632,_zz_633}}; - assign _zz_618 = 3'b000; - assign _zz_619 = ({_zz_634,_zz_635} != 3'b000); - assign _zz_620 = (_zz_636 != _zz_637); - assign _zz_621 = (_zz_638 != _zz_639); - assign _zz_622 = 32'h00000028; - assign _zz_623 = 32'h00000044; - assign _zz_624 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_625 = 32'h0; - assign _zz_626 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_627 = ((decode_INSTRUCTION & _zz_640) == 32'h00001000); - assign _zz_628 = _zz_97; - assign _zz_629 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_427 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_428 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_429 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_430 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_431 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_432 = execute_CsrPlugin_writeData[9 : 9]; + assign _zz_433 = execute_CsrPlugin_writeData[5 : 5]; + assign _zz_434 = execute_CsrPlugin_writeData[1 : 1]; + assign _zz_435 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_436 = (iBus_cmd_payload_address >>> 5); + assign _zz_437 = 1'b1; + assign _zz_438 = 1'b1; + assign _zz_439 = {_zz_59,_zz_58}; + assign _zz_440 = 32'h0000107f; + assign _zz_441 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_442 = 32'h00002073; + assign _zz_443 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_444 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_445 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_446) == 32'h00000003),{(_zz_447 == _zz_448),{_zz_449,{_zz_450,_zz_451}}}}}}; + assign _zz_446 = 32'h0000505f; + assign _zz_447 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_448 = 32'h00000063; + assign _zz_449 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_450 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_451 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_452) == 32'h00001013),{(_zz_453 == _zz_454),{_zz_455,{_zz_456,_zz_457}}}}}}; + assign _zz_452 = 32'hfc00305f; + assign _zz_453 = (decode_INSTRUCTION & 32'h01f0707f); + assign _zz_454 = 32'h0000500f; + assign _zz_455 = ((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013); + assign _zz_456 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_457 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_458) == 32'h12000073),{(_zz_459 == _zz_460),{_zz_461,_zz_462}}}}}; + assign _zz_458 = 32'hfe007fff; + assign _zz_459 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_460 = 32'h10200073; + assign _zz_461 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_462 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_463 = 32'h02004064; + assign _zz_464 = _zz_102; + assign _zz_465 = {_zz_100,_zz_101}; + assign _zz_466 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_467 = 1'b0; + assign _zz_468 = (((decode_INSTRUCTION & _zz_471) == 32'h00000050) != 1'b0); + assign _zz_469 = ((_zz_472 == _zz_473) != 1'b0); + assign _zz_470 = {({_zz_474,_zz_475} != 2'b00),{(_zz_476 != _zz_477),{_zz_478,{_zz_479,_zz_480}}}}; + assign _zz_471 = 32'h02203050; + assign _zz_472 = (decode_INSTRUCTION & 32'h02403050); + assign _zz_473 = 32'h00000050; + assign _zz_474 = ((decode_INSTRUCTION & _zz_481) == 32'h00001050); + assign _zz_475 = ((decode_INSTRUCTION & _zz_482) == 32'h00002050); + assign _zz_476 = {_zz_96,(_zz_483 == _zz_484)}; + assign _zz_477 = 2'b00; + assign _zz_478 = ((_zz_485 == _zz_486) != 1'b0); + assign _zz_479 = ({_zz_487,_zz_488} != 2'b00); + assign _zz_480 = {(_zz_489 != _zz_490),{_zz_491,{_zz_492,_zz_493}}}; + assign _zz_481 = 32'h00001050; + assign _zz_482 = 32'h00002050; + assign _zz_483 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_484 = 32'h00000004; + assign _zz_485 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_486 = 32'h00000040; + assign _zz_487 = ((decode_INSTRUCTION & _zz_494) == 32'h00005010); + assign _zz_488 = ((decode_INSTRUCTION & _zz_495) == 32'h00005020); + assign _zz_489 = {(_zz_496 == _zz_497),{_zz_498,_zz_499}}; + assign _zz_490 = 3'b000; + assign _zz_491 = ((_zz_500 == _zz_501) != 1'b0); + assign _zz_492 = (_zz_100 != 1'b0); + assign _zz_493 = {(_zz_502 != _zz_503),{_zz_504,{_zz_505,_zz_506}}}; + assign _zz_494 = 32'h00007034; + assign _zz_495 = 32'h02007064; + assign _zz_496 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_497 = 32'h40001010; + assign _zz_498 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_499 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_500 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_501 = 32'h00001000; + assign _zz_502 = {(_zz_507 == _zz_508),(_zz_509 == _zz_510)}; + assign _zz_503 = 2'b00; + assign _zz_504 = ((_zz_511 == _zz_512) != 1'b0); + assign _zz_505 = (_zz_513 != 1'b0); + assign _zz_506 = {(_zz_514 != _zz_515),{_zz_516,{_zz_517,_zz_518}}}; + assign _zz_507 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_508 = 32'h00002000; + assign _zz_509 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_510 = 32'h00001000; + assign _zz_511 = (decode_INSTRUCTION & 32'h02003050); + assign _zz_512 = 32'h02000050; + assign _zz_513 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz_514 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_515 = 1'b0; + assign _zz_516 = ({(_zz_519 == _zz_520),{_zz_521,{_zz_522,_zz_523}}} != 4'b0000); + assign _zz_517 = ((_zz_524 == _zz_525) != 1'b0); + assign _zz_518 = {(_zz_526 != 1'b0),{(_zz_527 != _zz_528),{_zz_529,{_zz_530,_zz_531}}}}; + assign _zz_519 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_520 = 32'h00000020; + assign _zz_521 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_522 = ((decode_INSTRUCTION & _zz_532) == 32'h08000020); + assign _zz_523 = ((decode_INSTRUCTION & _zz_533) == 32'h00000020); + assign _zz_524 = (decode_INSTRUCTION & 32'h10000008); + assign _zz_525 = 32'h00000008; + assign _zz_526 = ((decode_INSTRUCTION & 32'h10000008) == 32'h10000008); + assign _zz_527 = {(_zz_534 == _zz_535),{_zz_536,{_zz_537,_zz_538}}}; + assign _zz_528 = 6'h0; + assign _zz_529 = ({_zz_539,{_zz_540,_zz_541}} != 3'b000); + assign _zz_530 = (_zz_542 != 1'b0); + assign _zz_531 = {(_zz_543 != _zz_544),{_zz_545,{_zz_546,_zz_547}}}; + assign _zz_532 = 32'h08000070; + assign _zz_533 = 32'h10000070; + assign _zz_534 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_535 = 32'h00002040; + assign _zz_536 = ((decode_INSTRUCTION & _zz_548) == 32'h00001040); + assign _zz_537 = (_zz_549 == _zz_550); + assign _zz_538 = {_zz_551,{_zz_552,_zz_553}}; + assign _zz_539 = ((decode_INSTRUCTION & _zz_554) == 32'h08000020); + assign _zz_540 = (_zz_555 == _zz_556); + assign _zz_541 = (_zz_557 == _zz_558); + assign _zz_542 = ((decode_INSTRUCTION & _zz_559) == 32'h00000010); + assign _zz_543 = {_zz_99,{_zz_560,_zz_561}}; + assign _zz_544 = 5'h0; + assign _zz_545 = ({_zz_562,_zz_563} != 7'h0); + assign _zz_546 = (_zz_564 != _zz_565); + assign _zz_547 = {_zz_566,{_zz_567,_zz_568}}; + assign _zz_548 = 32'h00001040; + assign _zz_549 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_550 = 32'h00000040; + assign _zz_551 = ((decode_INSTRUCTION & _zz_569) == 32'h00000040); + assign _zz_552 = (_zz_570 == _zz_571); + assign _zz_553 = (_zz_572 == _zz_573); + assign _zz_554 = 32'h08000020; + assign _zz_555 = (decode_INSTRUCTION & 32'h10000020); + assign _zz_556 = 32'h00000020; + assign _zz_557 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_558 = 32'h00000020; + assign _zz_559 = 32'h00000010; + assign _zz_560 = (_zz_574 == _zz_575); + assign _zz_561 = {_zz_576,{_zz_577,_zz_578}}; + assign _zz_562 = _zz_96; + assign _zz_563 = {_zz_579,{_zz_580,_zz_581}}; + assign _zz_564 = {_zz_98,_zz_582}; + assign _zz_565 = 2'b00; + assign _zz_566 = ({_zz_583,_zz_584} != 2'b00); + assign _zz_567 = (_zz_585 != _zz_586); + assign _zz_568 = {_zz_587,{_zz_588,_zz_589}}; + assign _zz_569 = 32'h02400040; + assign _zz_570 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_571 = 32'h0; + assign _zz_572 = (decode_INSTRUCTION & 32'h18002008); + assign _zz_573 = 32'h10002008; + assign _zz_574 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_575 = 32'h00002010; + assign _zz_576 = ((decode_INSTRUCTION & _zz_590) == 32'h00000010); + assign _zz_577 = (_zz_591 == _zz_592); + assign _zz_578 = (_zz_593 == _zz_594); + assign _zz_579 = ((decode_INSTRUCTION & _zz_595) == 32'h00001010); + assign _zz_580 = (_zz_596 == _zz_597); + assign _zz_581 = {_zz_598,{_zz_599,_zz_600}}; + assign _zz_582 = ((decode_INSTRUCTION & _zz_601) == 32'h00000020); + assign _zz_583 = _zz_98; + assign _zz_584 = (_zz_602 == _zz_603); + assign _zz_585 = (_zz_604 == _zz_605); + assign _zz_586 = 1'b0; + assign _zz_587 = (_zz_606 != 1'b0); + assign _zz_588 = (_zz_607 != _zz_608); + assign _zz_589 = {_zz_609,{_zz_610,_zz_611}}; + assign _zz_590 = 32'h00001030; + assign _zz_591 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_592 = 32'h00000020; + assign _zz_593 = (decode_INSTRUCTION & 32'h02002068); + assign _zz_594 = 32'h00002020; + assign _zz_595 = 32'h00001010; + assign _zz_596 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_597 = 32'h00002010; + assign _zz_598 = ((decode_INSTRUCTION & _zz_612) == 32'h00002008); + assign _zz_599 = (_zz_613 == _zz_614); + assign _zz_600 = {_zz_99,_zz_615}; + assign _zz_601 = 32'h00000070; + assign _zz_602 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_603 = 32'h0; + assign _zz_604 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_605 = 32'h00004010; + assign _zz_606 = ((decode_INSTRUCTION & _zz_616) == 32'h00002010); + assign _zz_607 = {_zz_617,{_zz_618,_zz_619}}; + assign _zz_608 = 5'h0; + assign _zz_609 = ({_zz_620,_zz_621} != 2'b00); + assign _zz_610 = (_zz_622 != _zz_623); + assign _zz_611 = {_zz_624,{_zz_625,_zz_626}}; + assign _zz_612 = 32'h00002008; + assign _zz_613 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_614 = 32'h00000010; + assign _zz_615 = ((decode_INSTRUCTION & _zz_627) == 32'h0); + assign _zz_616 = 32'h00006014; + assign _zz_617 = ((decode_INSTRUCTION & _zz_628) == 32'h0); + assign _zz_618 = (_zz_629 == _zz_630); + assign _zz_619 = {_zz_631,{_zz_632,_zz_633}}; + assign _zz_620 = _zz_97; + assign _zz_621 = (_zz_634 == _zz_635); + assign _zz_622 = {_zz_636,{_zz_637,_zz_638}}; + assign _zz_623 = 3'b000; + assign _zz_624 = ({_zz_639,_zz_640} != 3'b000); + assign _zz_625 = (_zz_641 != _zz_642); + assign _zz_626 = (_zz_643 != _zz_644); + assign _zz_627 = 32'h00000028; + assign _zz_628 = 32'h00000044; + assign _zz_629 = (decode_INSTRUCTION & 32'h00000018); assign _zz_630 = 32'h0; - assign _zz_631 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_632 = ((decode_INSTRUCTION & _zz_641) == 32'h00002010); - assign _zz_633 = ((decode_INSTRUCTION & _zz_642) == 32'h40000030); - assign _zz_634 = _zz_96; - assign _zz_635 = {_zz_95,(_zz_643 == _zz_644)}; - assign _zz_636 = {_zz_95,(_zz_645 == _zz_646)}; - assign _zz_637 = 2'b00; - assign _zz_638 = ((decode_INSTRUCTION & _zz_647) == 32'h00001008); - assign _zz_639 = 1'b0; - assign _zz_640 = 32'h00005004; - assign _zz_641 = 32'h00002014; - assign _zz_642 = 32'h40000034; - assign _zz_643 = (decode_INSTRUCTION & 32'h00002014); - assign _zz_644 = 32'h00000004; - assign _zz_645 = (decode_INSTRUCTION & 32'h0000004c); - assign _zz_646 = 32'h00000004; - assign _zz_647 = 32'h00005048; - assign _zz_648 = 32'h0; + assign _zz_631 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_632 = ((decode_INSTRUCTION & _zz_645) == 32'h00001000); + assign _zz_633 = _zz_97; + assign _zz_634 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_635 = 32'h0; + assign _zz_636 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_637 = ((decode_INSTRUCTION & _zz_646) == 32'h00002010); + assign _zz_638 = ((decode_INSTRUCTION & _zz_647) == 32'h40000030); + assign _zz_639 = _zz_96; + assign _zz_640 = {_zz_95,(_zz_648 == _zz_649)}; + assign _zz_641 = {_zz_95,(_zz_650 == _zz_651)}; + assign _zz_642 = 2'b00; + assign _zz_643 = ((decode_INSTRUCTION & _zz_652) == 32'h00001008); + assign _zz_644 = 1'b0; + assign _zz_645 = 32'h00005004; + assign _zz_646 = 32'h00002014; + assign _zz_647 = 32'h40000034; + assign _zz_648 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_649 = 32'h00000004; + assign _zz_650 = (decode_INSTRUCTION & 32'h0000004c); + assign _zz_651 = 32'h00000004; + assign _zz_652 = 32'h00005048; + assign _zz_653 = 32'h0; always @ (posedge clk) begin - if(_zz_432) begin - _zz_222 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_437) begin + _zz_227 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_433) begin - _zz_223 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_438) begin + _zz_228 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -2059,13 +2054,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_187 ), //i - .io_cpu_prefetch_isValid (_zz_188 ), //i + .io_flush (_zz_192 ), //i + .io_cpu_prefetch_isValid (_zz_193 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_189 ), //i - .io_cpu_fetch_isStuck (_zz_190 ), //i - .io_cpu_fetch_isRemoved (_zz_191 ), //i + .io_cpu_fetch_isValid (_zz_194 ), //i + .io_cpu_fetch_isStuck (_zz_195 ), //i + .io_cpu_fetch_isRemoved (_zz_196 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -2086,8 +2081,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_192 ), //i - .io_cpu_decode_isStuck (_zz_193 ), //i + .io_cpu_decode_isValid (_zz_197 ), //i + .io_cpu_decode_isStuck (_zz_198 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_3_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -2095,8 +2090,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_194 ), //i - .io_cpu_fill_valid (_zz_195 ), //i + .io_cpu_decode_isUser (_zz_199 ), //i + .io_cpu_fill_valid (_zz_200 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -2109,24 +2104,24 @@ module VexRiscv ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_196 ), //i - .io_cpu_execute_address (_zz_197[31:0] ), //i + .io_cpu_execute_isValid (_zz_201 ), //i + .io_cpu_execute_address (_zz_202[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (_zz_198 ), //i - .io_cpu_execute_args_data (_zz_199[31:0] ), //i - .io_cpu_execute_args_size (_zz_200[1:0] ), //i - .io_cpu_execute_args_isLrsc (_zz_201 ), //i - .io_cpu_execute_args_isAmo (_zz_202 ), //i - .io_cpu_execute_args_amoCtrl_swap (_zz_203 ), //i - .io_cpu_execute_args_amoCtrl_alu (_zz_204[2:0] ), //i + .io_cpu_execute_args_wr (_zz_203 ), //i + .io_cpu_execute_args_data (_zz_204[31:0] ), //i + .io_cpu_execute_args_size (_zz_205[1:0] ), //i + .io_cpu_execute_args_isLrsc (_zz_206 ), //i + .io_cpu_execute_args_isAmo (_zz_207 ), //i + .io_cpu_execute_args_amoCtrl_swap (_zz_208 ), //i + .io_cpu_execute_args_amoCtrl_alu (_zz_209[2:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_205 ), //i + .io_cpu_memory_isValid (_zz_210 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_206[31:0] ), //i + .io_cpu_memory_address (_zz_211[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_207 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_212 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -2142,31 +2137,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i - .io_cpu_writeBack_isValid (_zz_208 ), //i + .io_cpu_writeBack_isValid (_zz_213 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_209 ), //i + .io_cpu_writeBack_isUser (_zz_214 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_210[31:0] ), //i + .io_cpu_writeBack_address (_zz_215[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_211 ), //i - .io_cpu_writeBack_fence_SR (_zz_212 ), //i - .io_cpu_writeBack_fence_SO (_zz_213 ), //i - .io_cpu_writeBack_fence_SI (_zz_214 ), //i - .io_cpu_writeBack_fence_PW (_zz_215 ), //i - .io_cpu_writeBack_fence_PR (_zz_216 ), //i - .io_cpu_writeBack_fence_PO (_zz_217 ), //i - .io_cpu_writeBack_fence_PI (_zz_218 ), //i - .io_cpu_writeBack_fence_FM (_zz_219[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_216 ), //i + .io_cpu_writeBack_fence_SR (_zz_217 ), //i + .io_cpu_writeBack_fence_SO (_zz_218 ), //i + .io_cpu_writeBack_fence_SI (_zz_219 ), //i + .io_cpu_writeBack_fence_PW (_zz_220 ), //i + .io_cpu_writeBack_fence_PR (_zz_221 ), //i + .io_cpu_writeBack_fence_PO (_zz_222 ), //i + .io_cpu_writeBack_fence_PI (_zz_223 ), //i + .io_cpu_writeBack_fence_FM (_zz_224[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_220 ), //i + .io_cpu_flush_valid (_zz_225 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_221 ), //i + .io_mem_cmd_ready (_zz_226 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -2182,18 +2177,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_434) + case(_zz_439) 2'b00 : begin - _zz_224 = DBusCachedPlugin_redoBranch_payload; + _zz_229 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_224 = CsrPlugin_jumpInterface_payload; + _zz_229 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_224 = BranchPlugin_jumpInterface_payload; + _zz_229 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_224 = CsrPlugin_redoInterface_payload; + _zz_229 = CsrPlugin_redoInterface_payload; end endcase end @@ -2201,56 +2196,56 @@ module VexRiscv ( always @(*) begin case(_zz_83) 2'b00 : begin - _zz_225 = MmuPlugin_ports_0_cache_0_valid; - _zz_226 = MmuPlugin_ports_0_cache_0_exception; - _zz_227 = MmuPlugin_ports_0_cache_0_superPage; - _zz_228 = MmuPlugin_ports_0_cache_0_virtualAddress_0; - _zz_229 = MmuPlugin_ports_0_cache_0_virtualAddress_1; - _zz_230 = MmuPlugin_ports_0_cache_0_physicalAddress_0; - _zz_231 = MmuPlugin_ports_0_cache_0_physicalAddress_1; - _zz_232 = MmuPlugin_ports_0_cache_0_allowRead; - _zz_233 = MmuPlugin_ports_0_cache_0_allowWrite; - _zz_234 = MmuPlugin_ports_0_cache_0_allowExecute; - _zz_235 = MmuPlugin_ports_0_cache_0_allowUser; + _zz_230 = MmuPlugin_ports_0_cache_0_valid; + _zz_231 = MmuPlugin_ports_0_cache_0_exception; + _zz_232 = MmuPlugin_ports_0_cache_0_superPage; + _zz_233 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_234 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_235 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_236 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_237 = MmuPlugin_ports_0_cache_0_allowRead; + _zz_238 = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_239 = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_240 = MmuPlugin_ports_0_cache_0_allowUser; end 2'b01 : begin - _zz_225 = MmuPlugin_ports_0_cache_1_valid; - _zz_226 = MmuPlugin_ports_0_cache_1_exception; - _zz_227 = MmuPlugin_ports_0_cache_1_superPage; - _zz_228 = MmuPlugin_ports_0_cache_1_virtualAddress_0; - _zz_229 = MmuPlugin_ports_0_cache_1_virtualAddress_1; - _zz_230 = MmuPlugin_ports_0_cache_1_physicalAddress_0; - _zz_231 = MmuPlugin_ports_0_cache_1_physicalAddress_1; - _zz_232 = MmuPlugin_ports_0_cache_1_allowRead; - _zz_233 = MmuPlugin_ports_0_cache_1_allowWrite; - _zz_234 = MmuPlugin_ports_0_cache_1_allowExecute; - _zz_235 = MmuPlugin_ports_0_cache_1_allowUser; + _zz_230 = MmuPlugin_ports_0_cache_1_valid; + _zz_231 = MmuPlugin_ports_0_cache_1_exception; + _zz_232 = MmuPlugin_ports_0_cache_1_superPage; + _zz_233 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_234 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_235 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_236 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_237 = MmuPlugin_ports_0_cache_1_allowRead; + _zz_238 = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_239 = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_240 = MmuPlugin_ports_0_cache_1_allowUser; end 2'b10 : begin - _zz_225 = MmuPlugin_ports_0_cache_2_valid; - _zz_226 = MmuPlugin_ports_0_cache_2_exception; - _zz_227 = MmuPlugin_ports_0_cache_2_superPage; - _zz_228 = MmuPlugin_ports_0_cache_2_virtualAddress_0; - _zz_229 = MmuPlugin_ports_0_cache_2_virtualAddress_1; - _zz_230 = MmuPlugin_ports_0_cache_2_physicalAddress_0; - _zz_231 = MmuPlugin_ports_0_cache_2_physicalAddress_1; - _zz_232 = MmuPlugin_ports_0_cache_2_allowRead; - _zz_233 = MmuPlugin_ports_0_cache_2_allowWrite; - _zz_234 = MmuPlugin_ports_0_cache_2_allowExecute; - _zz_235 = MmuPlugin_ports_0_cache_2_allowUser; + _zz_230 = MmuPlugin_ports_0_cache_2_valid; + _zz_231 = MmuPlugin_ports_0_cache_2_exception; + _zz_232 = MmuPlugin_ports_0_cache_2_superPage; + _zz_233 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_234 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_235 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_236 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_237 = MmuPlugin_ports_0_cache_2_allowRead; + _zz_238 = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_239 = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_240 = MmuPlugin_ports_0_cache_2_allowUser; end default : begin - _zz_225 = MmuPlugin_ports_0_cache_3_valid; - _zz_226 = MmuPlugin_ports_0_cache_3_exception; - _zz_227 = MmuPlugin_ports_0_cache_3_superPage; - _zz_228 = MmuPlugin_ports_0_cache_3_virtualAddress_0; - _zz_229 = MmuPlugin_ports_0_cache_3_virtualAddress_1; - _zz_230 = MmuPlugin_ports_0_cache_3_physicalAddress_0; - _zz_231 = MmuPlugin_ports_0_cache_3_physicalAddress_1; - _zz_232 = MmuPlugin_ports_0_cache_3_allowRead; - _zz_233 = MmuPlugin_ports_0_cache_3_allowWrite; - _zz_234 = MmuPlugin_ports_0_cache_3_allowExecute; - _zz_235 = MmuPlugin_ports_0_cache_3_allowUser; + _zz_230 = MmuPlugin_ports_0_cache_3_valid; + _zz_231 = MmuPlugin_ports_0_cache_3_exception; + _zz_232 = MmuPlugin_ports_0_cache_3_superPage; + _zz_233 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_234 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_235 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_236 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_237 = MmuPlugin_ports_0_cache_3_allowRead; + _zz_238 = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_239 = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_240 = MmuPlugin_ports_0_cache_3_allowUser; end endcase end @@ -2258,56 +2253,56 @@ module VexRiscv ( always @(*) begin case(_zz_87) 2'b00 : begin - _zz_236 = MmuPlugin_ports_1_cache_0_valid; - _zz_237 = MmuPlugin_ports_1_cache_0_exception; - _zz_238 = MmuPlugin_ports_1_cache_0_superPage; - _zz_239 = MmuPlugin_ports_1_cache_0_virtualAddress_0; - _zz_240 = MmuPlugin_ports_1_cache_0_virtualAddress_1; - _zz_241 = MmuPlugin_ports_1_cache_0_physicalAddress_0; - _zz_242 = MmuPlugin_ports_1_cache_0_physicalAddress_1; - _zz_243 = MmuPlugin_ports_1_cache_0_allowRead; - _zz_244 = MmuPlugin_ports_1_cache_0_allowWrite; - _zz_245 = MmuPlugin_ports_1_cache_0_allowExecute; - _zz_246 = MmuPlugin_ports_1_cache_0_allowUser; + _zz_241 = MmuPlugin_ports_1_cache_0_valid; + _zz_242 = MmuPlugin_ports_1_cache_0_exception; + _zz_243 = MmuPlugin_ports_1_cache_0_superPage; + _zz_244 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_245 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_246 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_247 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_248 = MmuPlugin_ports_1_cache_0_allowRead; + _zz_249 = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_250 = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_251 = MmuPlugin_ports_1_cache_0_allowUser; end 2'b01 : begin - _zz_236 = MmuPlugin_ports_1_cache_1_valid; - _zz_237 = MmuPlugin_ports_1_cache_1_exception; - _zz_238 = MmuPlugin_ports_1_cache_1_superPage; - _zz_239 = MmuPlugin_ports_1_cache_1_virtualAddress_0; - _zz_240 = MmuPlugin_ports_1_cache_1_virtualAddress_1; - _zz_241 = MmuPlugin_ports_1_cache_1_physicalAddress_0; - _zz_242 = MmuPlugin_ports_1_cache_1_physicalAddress_1; - _zz_243 = MmuPlugin_ports_1_cache_1_allowRead; - _zz_244 = MmuPlugin_ports_1_cache_1_allowWrite; - _zz_245 = MmuPlugin_ports_1_cache_1_allowExecute; - _zz_246 = MmuPlugin_ports_1_cache_1_allowUser; + _zz_241 = MmuPlugin_ports_1_cache_1_valid; + _zz_242 = MmuPlugin_ports_1_cache_1_exception; + _zz_243 = MmuPlugin_ports_1_cache_1_superPage; + _zz_244 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_245 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_246 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_247 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_248 = MmuPlugin_ports_1_cache_1_allowRead; + _zz_249 = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_250 = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_251 = MmuPlugin_ports_1_cache_1_allowUser; end 2'b10 : begin - _zz_236 = MmuPlugin_ports_1_cache_2_valid; - _zz_237 = MmuPlugin_ports_1_cache_2_exception; - _zz_238 = MmuPlugin_ports_1_cache_2_superPage; - _zz_239 = MmuPlugin_ports_1_cache_2_virtualAddress_0; - _zz_240 = MmuPlugin_ports_1_cache_2_virtualAddress_1; - _zz_241 = MmuPlugin_ports_1_cache_2_physicalAddress_0; - _zz_242 = MmuPlugin_ports_1_cache_2_physicalAddress_1; - _zz_243 = MmuPlugin_ports_1_cache_2_allowRead; - _zz_244 = MmuPlugin_ports_1_cache_2_allowWrite; - _zz_245 = MmuPlugin_ports_1_cache_2_allowExecute; - _zz_246 = MmuPlugin_ports_1_cache_2_allowUser; + _zz_241 = MmuPlugin_ports_1_cache_2_valid; + _zz_242 = MmuPlugin_ports_1_cache_2_exception; + _zz_243 = MmuPlugin_ports_1_cache_2_superPage; + _zz_244 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_245 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_246 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_247 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_248 = MmuPlugin_ports_1_cache_2_allowRead; + _zz_249 = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_250 = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_251 = MmuPlugin_ports_1_cache_2_allowUser; end default : begin - _zz_236 = MmuPlugin_ports_1_cache_3_valid; - _zz_237 = MmuPlugin_ports_1_cache_3_exception; - _zz_238 = MmuPlugin_ports_1_cache_3_superPage; - _zz_239 = MmuPlugin_ports_1_cache_3_virtualAddress_0; - _zz_240 = MmuPlugin_ports_1_cache_3_virtualAddress_1; - _zz_241 = MmuPlugin_ports_1_cache_3_physicalAddress_0; - _zz_242 = MmuPlugin_ports_1_cache_3_physicalAddress_1; - _zz_243 = MmuPlugin_ports_1_cache_3_allowRead; - _zz_244 = MmuPlugin_ports_1_cache_3_allowWrite; - _zz_245 = MmuPlugin_ports_1_cache_3_allowExecute; - _zz_246 = MmuPlugin_ports_1_cache_3_allowUser; + _zz_241 = MmuPlugin_ports_1_cache_3_valid; + _zz_242 = MmuPlugin_ports_1_cache_3_exception; + _zz_243 = MmuPlugin_ports_1_cache_3_superPage; + _zz_244 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_245 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_246 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_247 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_248 = MmuPlugin_ports_1_cache_3_allowRead; + _zz_249 = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_250 = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_251 = MmuPlugin_ports_1_cache_3_allowUser; end endcase end @@ -3010,24 +3005,24 @@ module VexRiscv ( `endif assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_128; - assign execute_SHIFT_RIGHT = _zz_306; + assign execute_BRANCH_DO = _zz_133; + assign execute_SHIFT_RIGHT = _zz_311; assign execute_REGFILE_WRITE_DATA = _zz_111; assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_197[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_202[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_DIV = _zz_308[0]; - assign decode_IS_RS2_SIGNED = _zz_309[0]; - assign decode_IS_RS1_SIGNED = _zz_310[0]; - assign decode_IS_MUL = _zz_311[0]; + assign decode_IS_DIV = _zz_313[0]; + assign decode_IS_RS2_SIGNED = _zz_314[0]; + assign decode_IS_RS1_SIGNED = _zz_315[0]; + assign decode_IS_MUL = _zz_316[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_312[0]; + assign decode_IS_CSR = _zz_317[0]; assign decode_BRANCH_CTRL = _zz_8; assign _zz_9 = _zz_10; assign _zz_11 = _zz_12; @@ -3035,16 +3030,16 @@ module VexRiscv ( assign _zz_14 = _zz_15; assign decode_ALU_BITWISE_CTRL = _zz_16; assign _zz_17 = _zz_18; - assign decode_SRC_LESS_UNSIGNED = _zz_313[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_318[0]; assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; - assign decode_IS_SFENCE_VMA = _zz_314[0]; - assign decode_MEMORY_MANAGMENT = _zz_315[0]; + assign decode_IS_SFENCE_VMA = _zz_319[0]; + assign decode_MEMORY_MANAGMENT = _zz_320[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_316[0]; + assign decode_MEMORY_WR = _zz_321[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_317[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_318[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_322[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_323[0]; assign decode_SRC2_CTRL = _zz_19; assign _zz_20 = _zz_21; assign decode_ALU_CTRL = _zz_22; @@ -3074,11 +3069,11 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_CTRL = _zz_31; - assign decode_RS2_USE = _zz_319[0]; - assign decode_RS1_USE = _zz_320[0]; + assign decode_RS2_USE = _zz_324[0]; + assign decode_RS1_USE = _zz_325[0]; always @ (*) begin _zz_32 = execute_REGFILE_WRITE_DATA; - if(_zz_247)begin + if(_zz_252)begin _zz_32 = execute_CsrPlugin_readData; end if(DBusCachedPlugin_forceDatapath)begin @@ -3094,28 +3089,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_122)begin + if((_zz_123 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_124; end end - if(_zz_248)begin - if(_zz_249)begin - if(_zz_121)begin + if(_zz_253)begin + if(_zz_254)begin + if(_zz_126)begin decode_RS2 = _zz_51; end end end - if(_zz_250)begin + if(_zz_255)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_123)begin + if(_zz_128)begin decode_RS2 = _zz_33; end end end - if(_zz_251)begin + if(_zz_256)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_125)begin + if(_zz_130)begin decode_RS2 = _zz_32; end end @@ -3124,28 +3119,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_122)begin + if((_zz_123 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_124; end end - if(_zz_248)begin - if(_zz_249)begin - if(_zz_120)begin + if(_zz_253)begin + if(_zz_254)begin + if(_zz_125)begin decode_RS1 = _zz_51; end end end - if(_zz_250)begin + if(_zz_255)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_122)begin + if(_zz_127)begin decode_RS1 = _zz_33; end end end - if(_zz_251)begin + if(_zz_256)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_124)begin + if(_zz_129)begin decode_RS1 = _zz_32; end end @@ -3167,10 +3162,10 @@ module VexRiscv ( end endcase end - if(_zz_252)begin + if(_zz_257)begin _zz_33 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_253)begin + if(_zz_258)begin _zz_33 = memory_MulDivIterativePlugin_div_result; end end @@ -3183,8 +3178,8 @@ module VexRiscv ( assign _zz_36 = execute_PC; assign execute_SRC2_CTRL = _zz_37; assign execute_SRC1_CTRL = _zz_38; - assign decode_SRC_USE_SUB_LESS = _zz_321[0]; - assign decode_SRC_ADD_ZERO = _zz_322[0]; + assign decode_SRC_USE_SUB_LESS = _zz_326[0]; + assign decode_SRC_ADD_ZERO = _zz_327[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_39; @@ -3202,13 +3197,13 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_323[0]; + decode_REGFILE_WRITE_VALID = _zz_328[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_435) == 32'h00001073),{(_zz_436 == _zz_437),{_zz_438,{_zz_439,_zz_440}}}}}}} != 25'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_440) == 32'h00001073),{(_zz_441 == _zz_442),{_zz_443,{_zz_444,_zz_445}}}}}}} != 25'h0); assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; @@ -3234,34 +3229,34 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_AMO = _zz_324[0]; - assign decode_MEMORY_LRSC = _zz_325[0]; - assign decode_MEMORY_ENABLE = _zz_326[0]; - assign decode_FLUSH_ALL = _zz_327[0]; + assign decode_MEMORY_AMO = _zz_329[0]; + assign decode_MEMORY_LRSC = _zz_330[0]; + assign decode_MEMORY_ENABLE = _zz_331[0]; + assign decode_FLUSH_ALL = _zz_332[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_254)begin + if(_zz_259)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_255)begin + if(_zz_260)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_256)begin + if(_zz_261)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_257)begin + if(_zz_262)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -3296,7 +3291,7 @@ module VexRiscv ( if(MmuPlugin_dBusAccess_cmd_valid)begin decode_arbitration_haltByOther = 1'b1; end - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_120 || _zz_121)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -3309,7 +3304,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_258)begin + if(_zz_263)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3320,22 +3315,22 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(_zz_258)begin + if(_zz_263)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_220 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_225 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_259)begin + if(_zz_264)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_247)begin + if(_zz_252)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3374,15 +3369,15 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_252)begin + if(_zz_257)begin if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_260)begin + if(_zz_265)begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_253)begin + if(_zz_258)begin if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3444,10 +3439,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(_zz_266)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_262)begin + if(_zz_267)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3461,10 +3456,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_261)begin + if(_zz_266)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_262)begin + if(_zz_267)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3478,7 +3473,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_259)begin + if(_zz_264)begin CsrPlugin_inWfi = 1'b1; end end @@ -3486,21 +3481,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_261)begin + if(_zz_266)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_262)begin + if(_zz_267)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_261)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_266)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_262)begin - case(_zz_263) + if(_zz_267)begin + case(_zz_268) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3519,11 +3514,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}} != 4'b0000); assign _zz_55 = {CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_56 = (_zz_55 & (~ _zz_328)); + assign _zz_56 = (_zz_55 & (~ _zz_333)); assign _zz_57 = _zz_56[3]; assign _zz_58 = (_zz_56[1] || _zz_57); assign _zz_59 = (_zz_56[2] || _zz_57); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_224; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_229; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3543,7 +3538,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_330); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_335); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3651,52 +3646,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_188 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_189 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_190 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_189; + assign _zz_193 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_194 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_195 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_194; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_2_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_192 = (IBusCachedPlugin_iBusRsp_stages_3_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_193 = (! IBusCachedPlugin_iBusRsp_stages_3_input_ready); - assign _zz_194 = (CsrPlugin_privilege == 2'b00); + assign _zz_197 = (IBusCachedPlugin_iBusRsp_stages_3_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_198 = (! IBusCachedPlugin_iBusRsp_stages_3_input_ready); + assign _zz_199 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_257)begin + if(_zz_262)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_255)begin + if(_zz_260)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_195 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_255)begin - _zz_195 = 1'b1; + _zz_200 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_260)begin + _zz_200 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_256)begin + if(_zz_261)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_254)begin + if(_zz_259)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_256)begin + if(_zz_261)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_254)begin + if(_zz_259)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3706,9 +3701,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_3_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_3_output_payload; - assign _zz_187 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_192 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_221 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_226 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3748,30 +3743,30 @@ module VexRiscv ( assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin - _zz_196 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + _zz_201 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_264)begin - if(_zz_265)begin - _zz_196 = 1'b1; + if(_zz_269)begin + if(_zz_270)begin + _zz_201 = 1'b1; end end end end always @ (*) begin - _zz_197 = execute_SRC_ADD; + _zz_202 = execute_SRC_ADD; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_264)begin - _zz_197 = MmuPlugin_dBusAccess_cmd_payload_address; + if(_zz_269)begin + _zz_202 = MmuPlugin_dBusAccess_cmd_payload_address; end end end always @ (*) begin - _zz_198 = execute_MEMORY_WR; + _zz_203 = execute_MEMORY_WR; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_264)begin - _zz_198 = MmuPlugin_dBusAccess_cmd_payload_write; + if(_zz_269)begin + _zz_203 = MmuPlugin_dBusAccess_cmd_payload_write; end end end @@ -3791,58 +3786,58 @@ module VexRiscv ( end always @ (*) begin - _zz_199 = _zz_75; + _zz_204 = _zz_75; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_264)begin - _zz_199 = MmuPlugin_dBusAccess_cmd_payload_data; + if(_zz_269)begin + _zz_204 = MmuPlugin_dBusAccess_cmd_payload_data; end end end always @ (*) begin - _zz_200 = execute_DBusCachedPlugin_size; + _zz_205 = execute_DBusCachedPlugin_size; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_264)begin - _zz_200 = MmuPlugin_dBusAccess_cmd_payload_size; + if(_zz_269)begin + _zz_205 = MmuPlugin_dBusAccess_cmd_payload_size; end end end - assign _zz_220 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_225 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); always @ (*) begin - _zz_201 = 1'b0; + _zz_206 = 1'b0; if(execute_MEMORY_LRSC)begin - _zz_201 = 1'b1; + _zz_206 = 1'b1; end if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_264)begin - _zz_201 = 1'b0; + if(_zz_269)begin + _zz_206 = 1'b0; end end end always @ (*) begin - _zz_202 = execute_MEMORY_AMO; + _zz_207 = execute_MEMORY_AMO; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_264)begin - _zz_202 = 1'b0; + if(_zz_269)begin + _zz_207 = 1'b0; end end end - assign _zz_204 = execute_INSTRUCTION[31 : 29]; - assign _zz_203 = execute_INSTRUCTION[27]; + assign _zz_209 = execute_INSTRUCTION[31 : 29]; + assign _zz_208 = execute_INSTRUCTION[27]; always @ (*) begin - _zz_205 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + _zz_210 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); if(memory_IS_DBUS_SHARING)begin - _zz_205 = 1'b1; + _zz_210 = 1'b1; end end - assign _zz_206 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_205; + assign _zz_211 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_210; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_206; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_211; always @ (*) begin DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; if(memory_IS_DBUS_SHARING)begin @@ -3852,24 +3847,24 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_207 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_212 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_207 = 1'b1; + _zz_212 = 1'b1; end end always @ (*) begin - _zz_208 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + _zz_213 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); if(writeBack_IS_DBUS_SHARING)begin - _zz_208 = 1'b1; + _zz_213 = 1'b1; end end - assign _zz_209 = (CsrPlugin_privilege == 2'b00); - assign _zz_210 = writeBack_REGFILE_WRITE_DATA; + assign _zz_214 = (CsrPlugin_privilege == 2'b00); + assign _zz_215 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_266)begin + if(_zz_271)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3879,7 +3874,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_266)begin + if(_zz_271)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3898,15 +3893,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_266)begin + if(_zz_271)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_331}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_332}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; end end end @@ -3979,7 +3974,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_303) + case(_zz_308) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_77; end @@ -3995,8 +3990,8 @@ module VexRiscv ( always @ (*) begin MmuPlugin_dBusAccess_cmd_ready = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_264)begin - if(_zz_265)begin + if(_zz_269)begin + if(_zz_270)begin MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); end end @@ -4006,7 +4001,7 @@ module VexRiscv ( always @ (*) begin DBusCachedPlugin_forceDatapath = 1'b0; if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_264)begin + if(_zz_269)begin DBusCachedPlugin_forceDatapath = 1'b1; end end @@ -4039,21 +4034,21 @@ module VexRiscv ( assign _zz_81 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_80); assign _zz_82 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_80); assign _zz_83 = {_zz_82,_zz_81}; - assign MmuPlugin_ports_0_cacheLine_valid = _zz_225; - assign MmuPlugin_ports_0_cacheLine_exception = _zz_226; - assign MmuPlugin_ports_0_cacheLine_superPage = _zz_227; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_228; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_229; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_230; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_231; - assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_232; - assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_233; - assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_234; - assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_235; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_230; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_231; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_232; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_233; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_234; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_235; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_236; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_237; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_238; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_239; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_240; always @ (*) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; - if(_zz_267)begin - if(_zz_268)begin + if(_zz_272)begin + if(_zz_273)begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; end end @@ -4063,7 +4058,7 @@ module VexRiscv ( assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_334); + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_339); if(MmuPlugin_ports_0_entryToReplace_willClear)begin MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; end @@ -4160,21 +4155,21 @@ module VexRiscv ( assign _zz_85 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_84); assign _zz_86 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_84); assign _zz_87 = {_zz_86,_zz_85}; - assign MmuPlugin_ports_1_cacheLine_valid = _zz_236; - assign MmuPlugin_ports_1_cacheLine_exception = _zz_237; - assign MmuPlugin_ports_1_cacheLine_superPage = _zz_238; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_239; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_240; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_241; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_242; - assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_243; - assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_244; - assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_245; - assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_246; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_241; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_242; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_243; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_244; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_245; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_246; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_247; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_248; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_249; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_250; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_251; always @ (*) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; - if(_zz_267)begin - if(_zz_269)begin + if(_zz_272)begin + if(_zz_274)begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; end end @@ -4184,7 +4179,7 @@ module VexRiscv ( assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); always @ (*) begin - MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_336); + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_341); if(MmuPlugin_ports_1_entryToReplace_willClear)begin MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; end @@ -4256,14 +4251,14 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; - assign MmuPlugin_shared_dBusRsp_pte_V = _zz_337[0]; - assign MmuPlugin_shared_dBusRsp_pte_R = _zz_338[0]; - assign MmuPlugin_shared_dBusRsp_pte_W = _zz_339[0]; - assign MmuPlugin_shared_dBusRsp_pte_X = _zz_340[0]; - assign MmuPlugin_shared_dBusRsp_pte_U = _zz_341[0]; - assign MmuPlugin_shared_dBusRsp_pte_G = _zz_342[0]; - assign MmuPlugin_shared_dBusRsp_pte_A = _zz_343[0]; - assign MmuPlugin_shared_dBusRsp_pte_D = _zz_344[0]; + assign MmuPlugin_shared_dBusRsp_pte_V = _zz_342[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = _zz_343[0]; + assign MmuPlugin_shared_dBusRsp_pte_W = _zz_344[0]; + assign MmuPlugin_shared_dBusRsp_pte_X = _zz_345[0]; + assign MmuPlugin_shared_dBusRsp_pte_U = _zz_346[0]; + assign MmuPlugin_shared_dBusRsp_pte_G = _zz_347[0]; + assign MmuPlugin_shared_dBusRsp_pte_A = _zz_348[0]; + assign MmuPlugin_shared_dBusRsp_pte_D = _zz_349[0]; assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; @@ -4290,7 +4285,7 @@ module VexRiscv ( assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; always @ (*) begin - MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + MmuPlugin_dBusAccess_cmd_payload_address = 32'h0; case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin end @@ -4307,7 +4302,7 @@ module VexRiscv ( endcase end - assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'h0; assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; always @ (*) begin _zz_88[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); @@ -4320,7 +4315,7 @@ module VexRiscv ( _zz_90[1] = _zz_89[0]; end - assign _zz_91 = (_zz_90 & (~ _zz_345)); + assign _zz_91 = (_zz_90 & (~ _zz_350)); always @ (*) begin _zz_92[0] = _zz_91[1]; _zz_92[1] = _zz_91[0]; @@ -4338,7 +4333,7 @@ module VexRiscv ( assign _zz_100 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); assign _zz_101 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); assign _zz_102 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); - assign _zz_94 = {(((decode_INSTRUCTION & _zz_458) == 32'h02004020) != 1'b0),{({_zz_102,_zz_101} != 2'b00),{({_zz_459,_zz_460} != 3'b000),{(_zz_461 != _zz_462),{_zz_463,{_zz_464,_zz_465}}}}}}; + assign _zz_94 = {(((decode_INSTRUCTION & _zz_463) == 32'h02004020) != 1'b0),{({_zz_102,_zz_101} != 2'b00),{({_zz_464,_zz_465} != 3'b000),{(_zz_466 != _zz_467),{_zz_468,{_zz_469,_zz_470}}}}}}; assign _zz_103 = _zz_94[2 : 1]; assign _zz_50 = _zz_103; assign _zz_104 = _zz_94[7 : 6]; @@ -4358,8 +4353,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_222; - assign decode_RegFilePlugin_rs2Data = _zz_223; + assign decode_RegFilePlugin_rs1Data = _zz_227; + assign decode_RegFilePlugin_rs2Data = _zz_228; always @ (*) begin lastStageRegFileWrite_valid = (_zz_42 && writeBack_arbitration_isFiring); if(_zz_110)begin @@ -4401,7 +4396,7 @@ module VexRiscv ( _zz_111 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_111 = {31'd0, _zz_346}; + _zz_111 = {31'd0, _zz_351}; end default : begin _zz_111 = execute_SRC_ADD_SUB; @@ -4415,18 +4410,18 @@ module VexRiscv ( _zz_112 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_112 = {29'd0, _zz_347}; + _zz_112 = {29'd0, _zz_352}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_112 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_112 = {27'd0, _zz_348}; + _zz_112 = {27'd0, _zz_353}; end endcase end - assign _zz_113 = _zz_349[11]; + assign _zz_113 = _zz_354[11]; always @ (*) begin _zz_114[19] = _zz_113; _zz_114[18] = _zz_113; @@ -4450,7 +4445,7 @@ module VexRiscv ( _zz_114[0] = _zz_113; end - assign _zz_115 = _zz_350[11]; + assign _zz_115 = _zz_355[11]; always @ (*) begin _zz_116[19] = _zz_115; _zz_116[18] = _zz_115; @@ -4492,7 +4487,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_351; + execute_SrcPlugin_addSub = _zz_356; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -4572,181 +4567,176 @@ module VexRiscv ( end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_270)begin - if(_zz_271)begin - if(_zz_120)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_120 = 1'b0; + if(_zz_275)begin + if(_zz_276)begin + if(_zz_125)begin + _zz_120 = 1'b1; end end end - if(_zz_272)begin - if(_zz_273)begin - if(_zz_122)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_277)begin + if(_zz_278)begin + if(_zz_127)begin + _zz_120 = 1'b1; end end end - if(_zz_274)begin - if(_zz_275)begin - if(_zz_124)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_279)begin + if(_zz_280)begin + if(_zz_129)begin + _zz_120 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_120 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_270)begin - if(_zz_271)begin - if(_zz_121)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_121 = 1'b0; + if(_zz_275)begin + if(_zz_276)begin + if(_zz_126)begin + _zz_121 = 1'b1; end end end - if(_zz_272)begin - if(_zz_273)begin - if(_zz_123)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_277)begin + if(_zz_278)begin + if(_zz_128)begin + _zz_121 = 1'b1; end end end - if(_zz_274)begin - if(_zz_275)begin - if(_zz_125)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_279)begin + if(_zz_280)begin + if(_zz_130)begin + _zz_121 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_121 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_42 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_41[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_51; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_120 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_121 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_122 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_123 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_124 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_125 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_125 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_126 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_127 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_128 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_129 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_130 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_126 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_126 == 3'b000)) begin - _zz_127 = execute_BranchPlugin_eq; - end else if((_zz_126 == 3'b001)) begin - _zz_127 = (! execute_BranchPlugin_eq); - end else if((((_zz_126 & 3'b101) == 3'b101))) begin - _zz_127 = (! execute_SRC_LESS); + assign _zz_131 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_131 == 3'b000)) begin + _zz_132 = execute_BranchPlugin_eq; + end else if((_zz_131 == 3'b001)) begin + _zz_132 = (! execute_BranchPlugin_eq); + end else if((((_zz_131 & 3'b101) == 3'b101))) begin + _zz_132 = (! execute_SRC_LESS); end else begin - _zz_127 = execute_SRC_LESS; + _zz_132 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_128 = 1'b0; + _zz_133 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_128 = 1'b1; + _zz_133 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_128 = 1'b1; + _zz_133 = 1'b1; end default : begin - _zz_128 = _zz_127; + _zz_133 = _zz_132; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_129 = _zz_358[19]; - always @ (*) begin - _zz_130[10] = _zz_129; - _zz_130[9] = _zz_129; - _zz_130[8] = _zz_129; - _zz_130[7] = _zz_129; - _zz_130[6] = _zz_129; - _zz_130[5] = _zz_129; - _zz_130[4] = _zz_129; - _zz_130[3] = _zz_129; - _zz_130[2] = _zz_129; - _zz_130[1] = _zz_129; - _zz_130[0] = _zz_129; - end - - assign _zz_131 = _zz_359[11]; - always @ (*) begin - _zz_132[19] = _zz_131; - _zz_132[18] = _zz_131; - _zz_132[17] = _zz_131; - _zz_132[16] = _zz_131; - _zz_132[15] = _zz_131; - _zz_132[14] = _zz_131; - _zz_132[13] = _zz_131; - _zz_132[12] = _zz_131; - _zz_132[11] = _zz_131; - _zz_132[10] = _zz_131; - _zz_132[9] = _zz_131; - _zz_132[8] = _zz_131; - _zz_132[7] = _zz_131; - _zz_132[6] = _zz_131; - _zz_132[5] = _zz_131; - _zz_132[4] = _zz_131; - _zz_132[3] = _zz_131; - _zz_132[2] = _zz_131; - _zz_132[1] = _zz_131; - _zz_132[0] = _zz_131; - end - - assign _zz_133 = _zz_360[11]; - always @ (*) begin - _zz_134[18] = _zz_133; - _zz_134[17] = _zz_133; - _zz_134[16] = _zz_133; - _zz_134[15] = _zz_133; - _zz_134[14] = _zz_133; - _zz_134[13] = _zz_133; - _zz_134[12] = _zz_133; - _zz_134[11] = _zz_133; - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; + assign _zz_134 = _zz_363[19]; + always @ (*) begin + _zz_135[10] = _zz_134; + _zz_135[9] = _zz_134; + _zz_135[8] = _zz_134; + _zz_135[7] = _zz_134; + _zz_135[6] = _zz_134; + _zz_135[5] = _zz_134; + _zz_135[4] = _zz_134; + _zz_135[3] = _zz_134; + _zz_135[2] = _zz_134; + _zz_135[1] = _zz_134; + _zz_135[0] = _zz_134; + end + + assign _zz_136 = _zz_364[11]; + always @ (*) begin + _zz_137[19] = _zz_136; + _zz_137[18] = _zz_136; + _zz_137[17] = _zz_136; + _zz_137[16] = _zz_136; + _zz_137[15] = _zz_136; + _zz_137[14] = _zz_136; + _zz_137[13] = _zz_136; + _zz_137[12] = _zz_136; + _zz_137[11] = _zz_136; + _zz_137[10] = _zz_136; + _zz_137[9] = _zz_136; + _zz_137[8] = _zz_136; + _zz_137[7] = _zz_136; + _zz_137[6] = _zz_136; + _zz_137[5] = _zz_136; + _zz_137[4] = _zz_136; + _zz_137[3] = _zz_136; + _zz_137[2] = _zz_136; + _zz_137[1] = _zz_136; + _zz_137[0] = _zz_136; + end + + assign _zz_138 = _zz_365[11]; + always @ (*) begin + _zz_139[18] = _zz_138; + _zz_139[17] = _zz_138; + _zz_139[16] = _zz_138; + _zz_139[15] = _zz_138; + _zz_139[14] = _zz_138; + _zz_139[13] = _zz_138; + _zz_139[12] = _zz_138; + _zz_139[11] = _zz_138; + _zz_139[10] = _zz_138; + _zz_139[9] = _zz_138; + _zz_139[8] = _zz_138; + _zz_139[7] = _zz_138; + _zz_139[6] = _zz_138; + _zz_139[5] = _zz_138; + _zz_139[4] = _zz_138; + _zz_139[3] = _zz_138; + _zz_139[2] = _zz_138; + _zz_139[1] = _zz_138; + _zz_139[0] = _zz_138; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_135 = {{_zz_130,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_140 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_135 = {_zz_132,execute_INSTRUCTION[31 : 20]}; + _zz_140 = {_zz_137,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_135 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_140 = {{_zz_139,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_135; + assign execute_BranchPlugin_branch_src2 = _zz_140; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; @@ -4754,7 +4744,7 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; always @ (*) begin - CsrPlugin_privilege = _zz_136; + CsrPlugin_privilege = _zz_141; if(CsrPlugin_forceMachineWire)begin CsrPlugin_privilege = 2'b11; end @@ -4773,12 +4763,12 @@ module VexRiscv ( end assign CsrPlugin_redoInterface_payload = decode_PC; - assign _zz_137 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); - assign _zz_138 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); - assign _zz_139 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); - assign _zz_140 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_141 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_142 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_142 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_143 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_144 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) @@ -4848,11 +4838,11 @@ module VexRiscv ( end assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_143 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_144 = _zz_361[0]; + assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_149 = _zz_366[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_258)begin + if(_zz_263)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4936,7 +4926,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_base = CsrPlugin_stvec_base; @@ -5061,7 +5051,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_276)begin + if(_zz_281)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -5080,20 +5070,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_277)begin + if(_zz_282)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_278)begin + if(_zz_283)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_277)begin + if(_zz_282)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_278)begin + if(_zz_283)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -5111,14 +5101,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_276)begin + if(_zz_281)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_276)begin + if(_zz_281)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -5136,7 +5126,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_304) + case(_zz_309) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -5150,8 +5140,8 @@ module VexRiscv ( assign memory_MulDivIterativePlugin_frontendOk = 1'b1; always @ (*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_252)begin - if(_zz_260)begin + if(_zz_257)begin + if(_zz_265)begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end @@ -5170,7 +5160,7 @@ module VexRiscv ( if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_364); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_369); end if(memory_MulDivIterativePlugin_mul_counter_willClear)begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; @@ -5179,8 +5169,8 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_253)begin - if(_zz_279)begin + if(_zz_258)begin + if(_zz_284)begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end @@ -5188,7 +5178,7 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_280)begin + if(_zz_285)begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end @@ -5199,30 +5189,30 @@ module VexRiscv ( if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_372); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_377); end if(memory_MulDivIterativePlugin_div_counter_willClear)begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end end - assign _zz_145 = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_145[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_373); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_374 : _zz_375); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_376[31:0]; - assign _zz_146 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_147 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_148 = ((execute_IS_MUL && _zz_147) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_150 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_150[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_378); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_379 : _zz_380); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_381[31:0]; + assign _zz_151 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_152 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_153 = ((execute_IS_MUL && _zz_152) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_149[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_149[31 : 0] = execute_RS1; + _zz_154[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_154[31 : 0] = execute_RS1; end - assign _zz_151 = (_zz_150 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_151 != 32'h0); - assign _zz_153 = (_zz_152 & externalInterruptArray_regNext); - assign externalInterruptS = (_zz_153 != 32'h0); + assign _zz_156 = (_zz_155 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_156 != 32'h0); + assign _zz_158 = (_zz_157 & externalInterruptArray_regNext); + assign externalInterruptS = (_zz_158 != 32'h0); assign _zz_27 = decode_SRC1_CTRL; assign _zz_25 = _zz_50; assign _zz_38 = decode_to_execute_SRC1_CTRL; @@ -5271,246 +5261,246 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_154 = 32'h0; + _zz_159 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_154[12 : 0] = 13'h1000; - _zz_154[25 : 20] = 6'h20; + _zz_159[12 : 0] = 13'h1000; + _zz_159[25 : 20] = 6'h20; end end always @ (*) begin - _zz_155 = 32'h0; + _zz_160 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_155[19 : 19] = MmuPlugin_status_mxr; - _zz_155[18 : 18] = MmuPlugin_status_sum; - _zz_155[17 : 17] = MmuPlugin_status_mprv; - _zz_155[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_155[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_155[3 : 3] = CsrPlugin_mstatus_MIE; - _zz_155[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_155[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_155[1 : 1] = CsrPlugin_sstatus_SIE; + _zz_160[19 : 19] = MmuPlugin_status_mxr; + _zz_160[18 : 18] = MmuPlugin_status_sum; + _zz_160[17 : 17] = MmuPlugin_status_mprv; + _zz_160[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_160[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_160[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_160[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_160[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_160[1 : 1] = CsrPlugin_sstatus_SIE; end end always @ (*) begin - _zz_156 = 32'h0; + _zz_161 = 32'h0; if(execute_CsrPlugin_csr_256)begin - _zz_156[19 : 19] = MmuPlugin_status_mxr; - _zz_156[18 : 18] = MmuPlugin_status_sum; - _zz_156[17 : 17] = MmuPlugin_status_mprv; - _zz_156[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_156[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_156[1 : 1] = CsrPlugin_sstatus_SIE; + _zz_161[19 : 19] = MmuPlugin_status_mxr; + _zz_161[18 : 18] = MmuPlugin_status_sum; + _zz_161[17 : 17] = MmuPlugin_status_mprv; + _zz_161[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_161[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_161[1 : 1] = CsrPlugin_sstatus_SIE; end end always @ (*) begin - _zz_157 = 32'h0; + _zz_162 = 32'h0; if(execute_CsrPlugin_csr_384)begin - _zz_157[31 : 31] = MmuPlugin_satp_mode; - _zz_157[30 : 22] = MmuPlugin_satp_asid; - _zz_157[19 : 0] = MmuPlugin_satp_ppn; + _zz_162[31 : 31] = MmuPlugin_satp_mode; + _zz_162[30 : 22] = MmuPlugin_satp_asid; + _zz_162[19 : 0] = MmuPlugin_satp_ppn; end end always @ (*) begin - _zz_158 = 32'h0; + _zz_163 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_158[0 : 0] = 1'b1; + _zz_163[0 : 0] = 1'b1; end end always @ (*) begin - _zz_159 = 32'h0; + _zz_164 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_159[1 : 0] = 2'b10; + _zz_164[1 : 0] = 2'b10; end end always @ (*) begin - _zz_160 = 32'h0; + _zz_165 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_160[1 : 0] = 2'b11; + _zz_165[1 : 0] = 2'b11; end end always @ (*) begin - _zz_161 = 32'h0; + _zz_166 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_161[11 : 11] = CsrPlugin_mip_MEIP; - _zz_161[7 : 7] = CsrPlugin_mip_MTIP; - _zz_161[3 : 3] = CsrPlugin_mip_MSIP; - _zz_161[5 : 5] = CsrPlugin_sip_STIP; - _zz_161[1 : 1] = CsrPlugin_sip_SSIP; - _zz_161[9 : 9] = CsrPlugin_sip_SEIP_OR; + _zz_166[11 : 11] = CsrPlugin_mip_MEIP; + _zz_166[7 : 7] = CsrPlugin_mip_MTIP; + _zz_166[3 : 3] = CsrPlugin_mip_MSIP; + _zz_166[5 : 5] = CsrPlugin_sip_STIP; + _zz_166[1 : 1] = CsrPlugin_sip_SSIP; + _zz_166[9 : 9] = CsrPlugin_sip_SEIP_OR; end end always @ (*) begin - _zz_162 = 32'h0; + _zz_167 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_162[11 : 11] = CsrPlugin_mie_MEIE; - _zz_162[7 : 7] = CsrPlugin_mie_MTIE; - _zz_162[3 : 3] = CsrPlugin_mie_MSIE; - _zz_162[9 : 9] = CsrPlugin_sie_SEIE; - _zz_162[5 : 5] = CsrPlugin_sie_STIE; - _zz_162[1 : 1] = CsrPlugin_sie_SSIE; + _zz_167[11 : 11] = CsrPlugin_mie_MEIE; + _zz_167[7 : 7] = CsrPlugin_mie_MTIE; + _zz_167[3 : 3] = CsrPlugin_mie_MSIE; + _zz_167[9 : 9] = CsrPlugin_sie_SEIE; + _zz_167[5 : 5] = CsrPlugin_sie_STIE; + _zz_167[1 : 1] = CsrPlugin_sie_SSIE; end end always @ (*) begin - _zz_163 = 32'h0; + _zz_168 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_163[31 : 0] = CsrPlugin_mepc; + _zz_168[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_164 = 32'h0; + _zz_169 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_164[31 : 0] = CsrPlugin_mscratch; + _zz_169[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_165 = 32'h0; + _zz_170 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_165[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_165[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_170[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_170[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_166 = 32'h0; + _zz_171 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_166[31 : 0] = CsrPlugin_mtval; + _zz_171[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_167 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_324)begin - _zz_167[5 : 5] = CsrPlugin_sip_STIP; - _zz_167[1 : 1] = CsrPlugin_sip_SSIP; - _zz_167[9 : 9] = CsrPlugin_sip_SEIP_OR; + _zz_172[5 : 5] = CsrPlugin_sip_STIP; + _zz_172[1 : 1] = CsrPlugin_sip_SSIP; + _zz_172[9 : 9] = CsrPlugin_sip_SEIP_OR; end end always @ (*) begin - _zz_168 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_260)begin - _zz_168[9 : 9] = CsrPlugin_sie_SEIE; - _zz_168[5 : 5] = CsrPlugin_sie_STIE; - _zz_168[1 : 1] = CsrPlugin_sie_SSIE; + _zz_173[9 : 9] = CsrPlugin_sie_SEIE; + _zz_173[5 : 5] = CsrPlugin_sie_STIE; + _zz_173[1 : 1] = CsrPlugin_sie_SSIE; end end always @ (*) begin - _zz_169 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_261)begin - _zz_169[31 : 2] = CsrPlugin_stvec_base; - _zz_169[1 : 0] = CsrPlugin_stvec_mode; + _zz_174[31 : 2] = CsrPlugin_stvec_base; + _zz_174[1 : 0] = CsrPlugin_stvec_mode; end end always @ (*) begin - _zz_170 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_321)begin - _zz_170[31 : 0] = CsrPlugin_sepc; + _zz_175[31 : 0] = CsrPlugin_sepc; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_320)begin - _zz_171[31 : 0] = CsrPlugin_sscratch; + _zz_176[31 : 0] = CsrPlugin_sscratch; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_322)begin - _zz_172[31 : 31] = CsrPlugin_scause_interrupt; - _zz_172[3 : 0] = CsrPlugin_scause_exceptionCode; + _zz_177[31 : 31] = CsrPlugin_scause_interrupt; + _zz_177[3 : 0] = CsrPlugin_scause_exceptionCode; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_323)begin - _zz_173[31 : 0] = CsrPlugin_stval; + _zz_178[31 : 0] = CsrPlugin_stval; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_174[31 : 0] = _zz_150; + _zz_179[31 : 0] = _zz_155; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_175[31 : 0] = _zz_151; + _zz_180[31 : 0] = _zz_156; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_2496)begin - _zz_176[31 : 0] = _zz_152; + _zz_181[31 : 0] = _zz_157; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_3520)begin - _zz_177[31 : 0] = _zz_153; + _zz_182[31 : 0] = _zz_158; end end - assign execute_CsrPlugin_readData = (((((_zz_154 | _zz_155) | (_zz_156 | _zz_157)) | ((_zz_158 | _zz_159) | (_zz_160 | _zz_648))) | (((_zz_161 | _zz_162) | (_zz_163 | _zz_164)) | ((_zz_165 | _zz_166) | (_zz_167 | _zz_168)))) | ((((_zz_169 | _zz_170) | (_zz_171 | _zz_172)) | ((_zz_173 | _zz_174) | (_zz_175 | _zz_176))) | _zz_177)); - assign iBusWishbone_ADR = {_zz_431,_zz_178}; - assign iBusWishbone_CTI = ((_zz_178 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_159 | _zz_160) | (_zz_161 | _zz_162)) | ((_zz_163 | _zz_164) | (_zz_165 | _zz_653))) | (((_zz_166 | _zz_167) | (_zz_168 | _zz_169)) | ((_zz_170 | _zz_171) | (_zz_172 | _zz_173)))) | ((((_zz_174 | _zz_175) | (_zz_176 | _zz_177)) | ((_zz_178 | _zz_179) | (_zz_180 | _zz_181))) | _zz_182)); + assign iBusWishbone_ADR = {_zz_436,_zz_183}; + assign iBusWishbone_CTI = ((_zz_183 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_281)begin + if(_zz_286)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_281)begin + if(_zz_286)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_179; + assign iBus_rsp_valid = _zz_184; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_185 = (dBus_cmd_payload_length != 3'b000); - assign _zz_181 = dBus_cmd_valid; - assign _zz_183 = dBus_cmd_payload_wr; - assign _zz_184 = (_zz_180 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_182 && (_zz_183 || _zz_184)); - assign dBusWishbone_ADR = ((_zz_185 ? {{dBus_cmd_payload_address[31 : 5],_zz_180},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_185 ? (_zz_184 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_190 = (dBus_cmd_payload_length != 3'b000); + assign _zz_186 = dBus_cmd_valid; + assign _zz_188 = dBus_cmd_payload_wr; + assign _zz_189 = (_zz_185 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_187 && (_zz_188 || _zz_189)); + assign dBusWishbone_ADR = ((_zz_190 ? {{dBus_cmd_payload_address[31 : 5],_zz_185},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_190 ? (_zz_189 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_183 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_183; + assign dBusWishbone_SEL = (_zz_188 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_188; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_182 = (_zz_181 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_181; - assign dBusWishbone_STB = _zz_181; - assign dBus_rsp_valid = _zz_186; + assign _zz_187 = (_zz_186 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_186; + assign dBusWishbone_STB = _zz_186; + assign dBus_rsp_valid = _zz_191; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5551,8 +5541,8 @@ module VexRiscv ( MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; _zz_110 <= 1'b1; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; - _zz_136 <= 2'b11; + _zz_122 <= 1'b0; + _zz_141 <= 2'b11; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -5596,17 +5586,17 @@ module VexRiscv ( execute_CsrPlugin_wfiWake <= 1'b0; memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - _zz_150 <= 32'h0; - _zz_152 <= 32'h0; + _zz_155 <= 32'h0; + _zz_157 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_IS_DBUS_SHARING <= 1'b0; memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; - _zz_178 <= 3'b000; - _zz_179 <= 1'b0; - _zz_180 <= 3'b000; - _zz_186 <= 1'b0; + _zz_183 <= 3'b000; + _zz_184 <= 1'b0; + _zz_185 <= 3'b000; + _zz_191 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5702,7 +5692,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_282)begin + if(_zz_287)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5744,7 +5734,7 @@ module VexRiscv ( MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_283)begin + if(_zz_288)begin MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; end end @@ -5778,32 +5768,32 @@ module VexRiscv ( end end endcase - if(_zz_267)begin - if(_zz_268)begin - if(_zz_284)begin + if(_zz_272)begin + if(_zz_273)begin + if(_zz_289)begin MmuPlugin_ports_0_cache_0_valid <= 1'b1; end - if(_zz_285)begin + if(_zz_290)begin MmuPlugin_ports_0_cache_1_valid <= 1'b1; end - if(_zz_286)begin + if(_zz_291)begin MmuPlugin_ports_0_cache_2_valid <= 1'b1; end - if(_zz_287)begin + if(_zz_292)begin MmuPlugin_ports_0_cache_3_valid <= 1'b1; end end - if(_zz_269)begin - if(_zz_288)begin + if(_zz_274)begin + if(_zz_293)begin MmuPlugin_ports_1_cache_0_valid <= 1'b1; end - if(_zz_289)begin + if(_zz_294)begin MmuPlugin_ports_1_cache_1_valid <= 1'b1; end - if(_zz_290)begin + if(_zz_295)begin MmuPlugin_ports_1_cache_2_valid <= 1'b1; end - if(_zz_291)begin + if(_zz_296)begin MmuPlugin_ports_1_cache_3_valid <= 1'b1; end end @@ -5819,7 +5809,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_valid <= 1'b0; end _zz_110 <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_122 <= (_zz_42 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5841,34 +5831,34 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_292)begin - if(_zz_293)begin + if(_zz_297)begin + if(_zz_298)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_294)begin + if(_zz_299)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_295)begin + if(_zz_300)begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(_zz_296)begin - if(_zz_297)begin + if(_zz_301)begin + if(_zz_302)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_298)begin + if(_zz_303)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_299)begin + if(_zz_304)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_300)begin + if(_zz_305)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_301)begin + if(_zz_306)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_302)begin + if(_zz_307)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5893,8 +5883,8 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_261)begin - _zz_136 <= CsrPlugin_targetPrivilege; + if(_zz_266)begin + _zz_141 <= CsrPlugin_targetPrivilege; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_sstatus_SIE <= 1'b0; @@ -5910,25 +5900,25 @@ module VexRiscv ( end endcase end - if(_zz_262)begin - case(_zz_263) + if(_zz_267)begin + case(_zz_268) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; - _zz_136 <= CsrPlugin_mstatus_MPP; + _zz_141 <= CsrPlugin_mstatus_MPP; end 2'b01 : begin CsrPlugin_sstatus_SPP <= 1'b0; CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; CsrPlugin_sstatus_SPIE <= 1'b1; - _zz_136 <= {1'b0,CsrPlugin_sstatus_SPP}; + _zz_141 <= {1'b0,CsrPlugin_sstatus_SPP}; end default : begin end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_142,{_zz_141,{_zz_140,{_zz_139,{_zz_138,_zz_137}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,{_zz_145,{_zz_144,{_zz_143,_zz_142}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; if((! memory_arbitration_isStuck))begin @@ -5960,25 +5950,25 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_386[0]; - MmuPlugin_status_sum <= _zz_387[0]; - MmuPlugin_status_mprv <= _zz_388[0]; + MmuPlugin_status_mxr <= _zz_391[0]; + MmuPlugin_status_sum <= _zz_392[0]; + MmuPlugin_status_mprv <= _zz_393[0]; CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_389[0]; - CsrPlugin_mstatus_MIE <= _zz_390[0]; + CsrPlugin_mstatus_MPIE <= _zz_394[0]; + CsrPlugin_mstatus_MIE <= _zz_395[0]; CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_391[0]; - CsrPlugin_sstatus_SIE <= _zz_392[0]; + CsrPlugin_sstatus_SPIE <= _zz_396[0]; + CsrPlugin_sstatus_SIE <= _zz_397[0]; end end if(execute_CsrPlugin_csr_256)begin if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_393[0]; - MmuPlugin_status_sum <= _zz_394[0]; - MmuPlugin_status_mprv <= _zz_395[0]; + MmuPlugin_status_mxr <= _zz_398[0]; + MmuPlugin_status_sum <= _zz_399[0]; + MmuPlugin_status_mprv <= _zz_400[0]; CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_396[0]; - CsrPlugin_sstatus_SIE <= _zz_397[0]; + CsrPlugin_sstatus_SPIE <= _zz_401[0]; + CsrPlugin_sstatus_SIE <= _zz_402[0]; end end if(execute_CsrPlugin_csr_384)begin @@ -5993,86 +5983,86 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_valid <= 1'b0; end if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_mode <= _zz_398[0]; + MmuPlugin_satp_mode <= _zz_403[0]; end end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_400[0]; - CsrPlugin_sip_SSIP <= _zz_401[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_402[0]; + CsrPlugin_sip_STIP <= _zz_405[0]; + CsrPlugin_sip_SSIP <= _zz_406[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_407[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_403[0]; - CsrPlugin_mie_MTIE <= _zz_404[0]; - CsrPlugin_mie_MSIE <= _zz_405[0]; - CsrPlugin_sie_SEIE <= _zz_406[0]; - CsrPlugin_sie_STIE <= _zz_407[0]; - CsrPlugin_sie_SSIE <= _zz_408[0]; + CsrPlugin_mie_MEIE <= _zz_408[0]; + CsrPlugin_mie_MTIE <= _zz_409[0]; + CsrPlugin_mie_MSIE <= _zz_410[0]; + CsrPlugin_sie_SEIE <= _zz_411[0]; + CsrPlugin_sie_STIE <= _zz_412[0]; + CsrPlugin_sie_SSIE <= _zz_413[0]; end end if(execute_CsrPlugin_csr_770)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_medeleg_IAM <= _zz_409[0]; - CsrPlugin_medeleg_IAF <= _zz_410[0]; - CsrPlugin_medeleg_II <= _zz_411[0]; - CsrPlugin_medeleg_LAM <= _zz_412[0]; - CsrPlugin_medeleg_LAF <= _zz_413[0]; - CsrPlugin_medeleg_SAM <= _zz_414[0]; - CsrPlugin_medeleg_SAF <= _zz_415[0]; - CsrPlugin_medeleg_EU <= _zz_416[0]; - CsrPlugin_medeleg_ES <= _zz_417[0]; - CsrPlugin_medeleg_IPF <= _zz_418[0]; - CsrPlugin_medeleg_LPF <= _zz_419[0]; - CsrPlugin_medeleg_SPF <= _zz_420[0]; + CsrPlugin_medeleg_IAM <= _zz_414[0]; + CsrPlugin_medeleg_IAF <= _zz_415[0]; + CsrPlugin_medeleg_II <= _zz_416[0]; + CsrPlugin_medeleg_LAM <= _zz_417[0]; + CsrPlugin_medeleg_LAF <= _zz_418[0]; + CsrPlugin_medeleg_SAM <= _zz_419[0]; + CsrPlugin_medeleg_SAF <= _zz_420[0]; + CsrPlugin_medeleg_EU <= _zz_421[0]; + CsrPlugin_medeleg_ES <= _zz_422[0]; + CsrPlugin_medeleg_IPF <= _zz_423[0]; + CsrPlugin_medeleg_LPF <= _zz_424[0]; + CsrPlugin_medeleg_SPF <= _zz_425[0]; end end if(execute_CsrPlugin_csr_771)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mideleg_SE <= _zz_421[0]; - CsrPlugin_mideleg_ST <= _zz_422[0]; - CsrPlugin_mideleg_SS <= _zz_423[0]; + CsrPlugin_mideleg_SE <= _zz_426[0]; + CsrPlugin_mideleg_ST <= _zz_427[0]; + CsrPlugin_mideleg_SS <= _zz_428[0]; end end if(execute_CsrPlugin_csr_324)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_424[0]; - CsrPlugin_sip_SSIP <= _zz_425[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_426[0]; + CsrPlugin_sip_STIP <= _zz_429[0]; + CsrPlugin_sip_SSIP <= _zz_430[0]; + CsrPlugin_sip_SEIP_SOFT <= _zz_431[0]; end end if(execute_CsrPlugin_csr_260)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sie_SEIE <= _zz_427[0]; - CsrPlugin_sie_STIE <= _zz_428[0]; - CsrPlugin_sie_SSIE <= _zz_429[0]; + CsrPlugin_sie_SEIE <= _zz_432[0]; + CsrPlugin_sie_STIE <= _zz_433[0]; + CsrPlugin_sie_SSIE <= _zz_434[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_150 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2496)begin if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_281)begin + if(_zz_286)begin if(iBusWishbone_ACK)begin - _zz_178 <= (_zz_178 + 3'b001); + _zz_183 <= (_zz_183 + 3'b001); end end - _zz_179 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_181 && _zz_182))begin - _zz_180 <= (_zz_180 + 3'b001); - if(_zz_184)begin - _zz_180 <= 3'b000; + _zz_184 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_186 && _zz_187))begin + _zz_185 <= (_zz_185 + 3'b001); + if(_zz_189)begin + _zz_185 <= 3'b000; end end - _zz_186 <= ((_zz_181 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_191 <= ((_zz_186 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -6089,7 +6079,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_3_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_282)begin + if(_zz_287)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -6125,7 +6115,7 @@ module VexRiscv ( end case(MmuPlugin_shared_state_1) `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_283)begin + if(_zz_288)begin MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; MmuPlugin_shared_vpn_1 <= _zz_93[31 : 22]; MmuPlugin_shared_vpn_0 <= _zz_93[21 : 12]; @@ -6140,9 +6130,9 @@ module VexRiscv ( default : begin end endcase - if(_zz_267)begin - if(_zz_268)begin - if(_zz_284)begin + if(_zz_272)begin + if(_zz_273)begin + if(_zz_289)begin MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6154,7 +6144,7 @@ module VexRiscv ( MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_285)begin + if(_zz_290)begin MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6166,7 +6156,7 @@ module VexRiscv ( MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_286)begin + if(_zz_291)begin MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6178,7 +6168,7 @@ module VexRiscv ( MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_287)begin + if(_zz_292)begin MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6191,8 +6181,8 @@ module VexRiscv ( MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end end - if(_zz_269)begin - if(_zz_288)begin + if(_zz_274)begin + if(_zz_293)begin MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6204,7 +6194,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_289)begin + if(_zz_294)begin MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6216,7 +6206,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_290)begin + if(_zz_295)begin MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6228,7 +6218,7 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); end - if(_zz_291)begin + if(_zz_296)begin MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; @@ -6242,8 +6232,8 @@ module VexRiscv ( end end end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_123 <= _zz_41[11 : 7]; + _zz_124 <= _zz_51; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -6252,9 +6242,9 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_258)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_144 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_144 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_263)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; @@ -6268,47 +6258,47 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_292)begin - if(_zz_293)begin + if(_zz_297)begin + if(_zz_298)begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_294)begin + if(_zz_299)begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_295)begin + if(_zz_300)begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end end - if(_zz_296)begin - if(_zz_297)begin + if(_zz_301)begin + if(_zz_302)begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_298)begin + if(_zz_303)begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_299)begin + if(_zz_304)begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_300)begin + if(_zz_305)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_301)begin + if(_zz_306)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_302)begin + if(_zz_307)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_261)begin + if(_zz_266)begin case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); @@ -6330,10 +6320,10 @@ module VexRiscv ( end endcase end - if(_zz_252)begin - if(_zz_260)begin + if(_zz_257)begin + if(_zz_265)begin memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_365,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_370,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin @@ -6342,20 +6332,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_MulDivIterativePlugin_div_done <= 1'b0; end - if(_zz_253)begin - if(_zz_279)begin + if(_zz_258)begin + if(_zz_284)begin memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_result <= _zz_377[31:0]; + memory_MulDivIterativePlugin_div_result <= _zz_382[31:0]; end end end - if(_zz_280)begin + if(_zz_285)begin memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_148 ? (~ _zz_149) : _zz_149) + _zz_383); - memory_MulDivIterativePlugin_rs2 <= ((_zz_147 ? (~ execute_RS2) : execute_RS2) + _zz_385); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_148 ^ (_zz_147 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_MulDivIterativePlugin_rs1 <= ((_zz_153 ? (~ _zz_154) : _zz_154) + _zz_388); + memory_MulDivIterativePlugin_rs2 <= ((_zz_152 ? (~ execute_RS2) : execute_RS2) + _zz_390); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_153 ^ (_zz_152 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -6627,7 +6617,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_399[0]; + CsrPlugin_mip_MSIP <= _zz_404[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -6664,7 +6654,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_322)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_scause_interrupt <= _zz_430[0]; + CsrPlugin_scause_interrupt <= _zz_435[0]; CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -7023,7 +7013,7 @@ module DataCache ( end always @ (*) begin - tagsReadCmd_payload = 7'bxxxxxxx; + tagsReadCmd_payload = 7'h0; if(_zz_12)begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end @@ -7037,7 +7027,7 @@ module DataCache ( end always @ (*) begin - dataReadCmd_payload = 10'bxxxxxxxxxx; + dataReadCmd_payload = 10'h0; if(_zz_12)begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end @@ -7067,7 +7057,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_address = 7'bxxxxxxx; + tagsWriteCmd_payload_address = 7'h0; if(stageB_flusher_valid)begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end @@ -7094,7 +7084,7 @@ module DataCache ( end always @ (*) begin - tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + tagsWriteCmd_payload_data_address = 20'h0; if(loader_done)begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end @@ -7142,7 +7132,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + dataWriteCmd_payload_address = 10'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end @@ -7152,7 +7142,7 @@ module DataCache ( end always @ (*) begin - dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + dataWriteCmd_payload_data = 32'h0; if(stageB_cpuWriteToCache)begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v index 60138a0..115224b 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -73,18 +73,18 @@ module VexRiscv ( input clk, input reset ); - wire _zz_154; - wire _zz_155; - wire _zz_156; - wire _zz_157; - wire _zz_158; wire _zz_159; wire _zz_160; wire _zz_161; - reg _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; + wire _zz_162; + wire _zz_163; + wire _zz_164; + wire _zz_165; + wire _zz_166; + reg _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -97,11 +97,6 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_166; - wire _zz_167; - wire _zz_168; - wire _zz_169; - wire _zz_170; wire _zz_171; wire _zz_172; wire _zz_173; @@ -114,12 +109,12 @@ module VexRiscv ( wire _zz_180; wire _zz_181; wire _zz_182; - wire [1:0] _zz_183; + wire _zz_183; wire _zz_184; wire _zz_185; wire _zz_186; wire _zz_187; - wire _zz_188; + wire [1:0] _zz_188; wire _zz_189; wire _zz_190; wire _zz_191; @@ -134,13 +129,13 @@ module VexRiscv ( wire _zz_200; wire _zz_201; wire _zz_202; - wire [1:0] _zz_203; + wire _zz_203; wire _zz_204; - wire [0:0] _zz_205; - wire [0:0] _zz_206; - wire [0:0] _zz_207; - wire [0:0] _zz_208; - wire [0:0] _zz_209; + wire _zz_205; + wire _zz_206; + wire _zz_207; + wire [1:0] _zz_208; + wire _zz_209; wire [0:0] _zz_210; wire [0:0] _zz_211; wire [0:0] _zz_212; @@ -152,254 +147,259 @@ module VexRiscv ( wire [0:0] _zz_218; wire [0:0] _zz_219; wire [0:0] _zz_220; - wire [3:0] _zz_221; - wire [2:0] _zz_222; - wire [31:0] _zz_223; - wire [11:0] _zz_224; - wire [31:0] _zz_225; - wire [19:0] _zz_226; - wire [11:0] _zz_227; + wire [0:0] _zz_221; + wire [0:0] _zz_222; + wire [0:0] _zz_223; + wire [0:0] _zz_224; + wire [0:0] _zz_225; + wire [3:0] _zz_226; + wire [2:0] _zz_227; wire [31:0] _zz_228; - wire [31:0] _zz_229; - wire [19:0] _zz_230; - wire [11:0] _zz_231; - wire [2:0] _zz_232; - wire [0:0] _zz_233; - wire [2:0] _zz_234; - wire [4:0] _zz_235; + wire [11:0] _zz_229; + wire [31:0] _zz_230; + wire [19:0] _zz_231; + wire [11:0] _zz_232; + wire [31:0] _zz_233; + wire [31:0] _zz_234; + wire [19:0] _zz_235; wire [11:0] _zz_236; - wire [11:0] _zz_237; - wire [31:0] _zz_238; - wire [31:0] _zz_239; - wire [31:0] _zz_240; - wire [31:0] _zz_241; - wire [31:0] _zz_242; + wire [2:0] _zz_237; + wire [0:0] _zz_238; + wire [2:0] _zz_239; + wire [4:0] _zz_240; + wire [11:0] _zz_241; + wire [11:0] _zz_242; wire [31:0] _zz_243; wire [31:0] _zz_244; wire [31:0] _zz_245; - wire [32:0] _zz_246; - wire [11:0] _zz_247; - wire [19:0] _zz_248; - wire [11:0] _zz_249; + wire [31:0] _zz_246; + wire [31:0] _zz_247; + wire [31:0] _zz_248; + wire [31:0] _zz_249; wire [31:0] _zz_250; - wire [31:0] _zz_251; - wire [31:0] _zz_252; - wire [11:0] _zz_253; - wire [19:0] _zz_254; - wire [11:0] _zz_255; - wire [2:0] _zz_256; - wire [1:0] _zz_257; - wire [1:0] _zz_258; - wire [1:0] _zz_259; - wire [1:0] _zz_260; - wire [0:0] _zz_261; - wire [5:0] _zz_262; - wire [33:0] _zz_263; - wire [32:0] _zz_264; - wire [33:0] _zz_265; - wire [32:0] _zz_266; - wire [33:0] _zz_267; - wire [32:0] _zz_268; - wire [0:0] _zz_269; - wire [5:0] _zz_270; + wire [32:0] _zz_251; + wire [11:0] _zz_252; + wire [19:0] _zz_253; + wire [11:0] _zz_254; + wire [31:0] _zz_255; + wire [31:0] _zz_256; + wire [31:0] _zz_257; + wire [11:0] _zz_258; + wire [19:0] _zz_259; + wire [11:0] _zz_260; + wire [2:0] _zz_261; + wire [1:0] _zz_262; + wire [1:0] _zz_263; + wire [1:0] _zz_264; + wire [1:0] _zz_265; + wire [0:0] _zz_266; + wire [5:0] _zz_267; + wire [33:0] _zz_268; + wire [32:0] _zz_269; + wire [33:0] _zz_270; wire [32:0] _zz_271; - wire [31:0] _zz_272; - wire [31:0] _zz_273; - wire [32:0] _zz_274; - wire [32:0] _zz_275; + wire [33:0] _zz_272; + wire [32:0] _zz_273; + wire [0:0] _zz_274; + wire [5:0] _zz_275; wire [32:0] _zz_276; - wire [32:0] _zz_277; - wire [0:0] _zz_278; + wire [31:0] _zz_277; + wire [31:0] _zz_278; wire [32:0] _zz_279; - wire [0:0] _zz_280; + wire [32:0] _zz_280; wire [32:0] _zz_281; - wire [0:0] _zz_282; - wire [31:0] _zz_283; - wire [0:0] _zz_284; + wire [32:0] _zz_282; + wire [0:0] _zz_283; + wire [32:0] _zz_284; wire [0:0] _zz_285; - wire [0:0] _zz_286; + wire [32:0] _zz_286; wire [0:0] _zz_287; - wire [0:0] _zz_288; + wire [31:0] _zz_288; wire [0:0] _zz_289; - wire [26:0] _zz_290; - wire _zz_291; - wire _zz_292; - wire [1:0] _zz_293; - wire [31:0] _zz_294; - wire [31:0] _zz_295; - wire [31:0] _zz_296; + wire [0:0] _zz_290; + wire [0:0] _zz_291; + wire [0:0] _zz_292; + wire [0:0] _zz_293; + wire [0:0] _zz_294; + wire [26:0] _zz_295; + wire _zz_296; wire _zz_297; - wire [0:0] _zz_298; - wire [12:0] _zz_299; + wire [1:0] _zz_298; + wire [31:0] _zz_299; wire [31:0] _zz_300; wire [31:0] _zz_301; - wire [31:0] _zz_302; - wire _zz_303; - wire [0:0] _zz_304; - wire [6:0] _zz_305; + wire _zz_302; + wire [0:0] _zz_303; + wire [12:0] _zz_304; + wire [31:0] _zz_305; wire [31:0] _zz_306; wire [31:0] _zz_307; - wire [31:0] _zz_308; - wire _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire _zz_312; - wire _zz_313; + wire _zz_308; + wire [0:0] _zz_309; + wire [6:0] _zz_310; + wire [31:0] _zz_311; + wire [31:0] _zz_312; + wire [31:0] _zz_313; wire _zz_314; - wire [31:0] _zz_315; + wire [0:0] _zz_315; wire [0:0] _zz_316; - wire [1:0] _zz_317; - wire [0:0] _zz_318; - wire [0:0] _zz_319; - wire _zz_320; + wire _zz_317; + wire _zz_318; + wire _zz_319; + wire [31:0] _zz_320; wire [0:0] _zz_321; - wire [24:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; + wire [1:0] _zz_322; + wire [0:0] _zz_323; + wire [0:0] _zz_324; + wire _zz_325; wire [0:0] _zz_326; - wire [0:0] _zz_327; - wire [1:0] _zz_328; - wire [1:0] _zz_329; - wire _zz_330; + wire [24:0] _zz_327; + wire [31:0] _zz_328; + wire [31:0] _zz_329; + wire [31:0] _zz_330; wire [0:0] _zz_331; - wire [20:0] _zz_332; - wire [31:0] _zz_333; - wire [31:0] _zz_334; - wire [31:0] _zz_335; - wire [31:0] _zz_336; - wire [31:0] _zz_337; + wire [0:0] _zz_332; + wire [1:0] _zz_333; + wire [1:0] _zz_334; + wire _zz_335; + wire [0:0] _zz_336; + wire [20:0] _zz_337; wire [31:0] _zz_338; - wire [0:0] _zz_339; - wire [0:0] _zz_340; - wire [2:0] _zz_341; - wire [2:0] _zz_342; - wire _zz_343; + wire [31:0] _zz_339; + wire [31:0] _zz_340; + wire [31:0] _zz_341; + wire [31:0] _zz_342; + wire [31:0] _zz_343; wire [0:0] _zz_344; - wire [17:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; - wire [31:0] _zz_349; - wire _zz_350; - wire _zz_351; - wire _zz_352; - wire [0:0] _zz_353; - wire [0:0] _zz_354; + wire [0:0] _zz_345; + wire [2:0] _zz_346; + wire [2:0] _zz_347; + wire _zz_348; + wire [0:0] _zz_349; + wire [17:0] _zz_350; + wire [31:0] _zz_351; + wire [31:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; wire _zz_355; - wire [0:0] _zz_356; - wire [0:0] _zz_357; - wire _zz_358; + wire _zz_356; + wire _zz_357; + wire [0:0] _zz_358; wire [0:0] _zz_359; - wire [14:0] _zz_360; - wire [31:0] _zz_361; - wire [31:0] _zz_362; - wire [31:0] _zz_363; - wire [31:0] _zz_364; - wire [31:0] _zz_365; + wire _zz_360; + wire [0:0] _zz_361; + wire [0:0] _zz_362; + wire _zz_363; + wire [0:0] _zz_364; + wire [14:0] _zz_365; wire [31:0] _zz_366; wire [31:0] _zz_367; wire [31:0] _zz_368; - wire [0:0] _zz_369; - wire [0:0] _zz_370; - wire [1:0] _zz_371; - wire [1:0] _zz_372; - wire _zz_373; + wire [31:0] _zz_369; + wire [31:0] _zz_370; + wire [31:0] _zz_371; + wire [31:0] _zz_372; + wire [31:0] _zz_373; wire [0:0] _zz_374; - wire [12:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire [31:0] _zz_378; - wire [31:0] _zz_379; - wire [31:0] _zz_380; + wire [0:0] _zz_375; + wire [1:0] _zz_376; + wire [1:0] _zz_377; + wire _zz_378; + wire [0:0] _zz_379; + wire [12:0] _zz_380; wire [31:0] _zz_381; - wire _zz_382; - wire [0:0] _zz_383; - wire [0:0] _zz_384; - wire _zz_385; - wire [0:0] _zz_386; - wire [0:0] _zz_387; - wire _zz_388; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire [31:0] _zz_384; + wire [31:0] _zz_385; + wire [31:0] _zz_386; + wire _zz_387; + wire [0:0] _zz_388; wire [0:0] _zz_389; - wire [9:0] _zz_390; - wire [31:0] _zz_391; - wire [31:0] _zz_392; - wire [31:0] _zz_393; + wire _zz_390; + wire [0:0] _zz_391; + wire [0:0] _zz_392; + wire _zz_393; wire [0:0] _zz_394; - wire [0:0] _zz_395; - wire [0:0] _zz_396; - wire [4:0] _zz_397; - wire [1:0] _zz_398; - wire [1:0] _zz_399; - wire _zz_400; + wire [9:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire [0:0] _zz_399; + wire [0:0] _zz_400; wire [0:0] _zz_401; - wire [6:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire [31:0] _zz_405; - wire [31:0] _zz_406; - wire _zz_407; - wire [0:0] _zz_408; - wire [1:0] _zz_409; + wire [4:0] _zz_402; + wire [1:0] _zz_403; + wire [1:0] _zz_404; + wire _zz_405; + wire [0:0] _zz_406; + wire [6:0] _zz_407; + wire [31:0] _zz_408; + wire [31:0] _zz_409; wire [31:0] _zz_410; wire [31:0] _zz_411; wire _zz_412; wire [0:0] _zz_413; - wire [0:0] _zz_414; - wire [0:0] _zz_415; - wire [0:0] _zz_416; + wire [1:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; wire _zz_417; wire [0:0] _zz_418; - wire [3:0] _zz_419; - wire [31:0] _zz_420; - wire [31:0] _zz_421; - wire [31:0] _zz_422; - wire _zz_423; - wire _zz_424; + wire [0:0] _zz_419; + wire [0:0] _zz_420; + wire [0:0] _zz_421; + wire _zz_422; + wire [0:0] _zz_423; + wire [3:0] _zz_424; wire [31:0] _zz_425; wire [31:0] _zz_426; wire [31:0] _zz_427; - wire [31:0] _zz_428; - wire [31:0] _zz_429; + wire _zz_428; + wire _zz_429; wire [31:0] _zz_430; wire [31:0] _zz_431; - wire [0:0] _zz_432; - wire [2:0] _zz_433; - wire [0:0] _zz_434; - wire [0:0] _zz_435; - wire _zz_436; + wire [31:0] _zz_432; + wire [31:0] _zz_433; + wire [31:0] _zz_434; + wire [31:0] _zz_435; + wire [31:0] _zz_436; wire [0:0] _zz_437; - wire [1:0] _zz_438; - wire [31:0] _zz_439; - wire [31:0] _zz_440; - wire [31:0] _zz_441; - wire [31:0] _zz_442; - wire _zz_443; - wire [0:0] _zz_444; - wire [0:0] _zz_445; + wire [2:0] _zz_438; + wire [0:0] _zz_439; + wire [0:0] _zz_440; + wire _zz_441; + wire [0:0] _zz_442; + wire [1:0] _zz_443; + wire [31:0] _zz_444; + wire [31:0] _zz_445; wire [31:0] _zz_446; wire [31:0] _zz_447; - wire [0:0] _zz_448; - wire [1:0] _zz_449; - wire [1:0] _zz_450; - wire [1:0] _zz_451; - wire _zz_452; - wire _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [31:0] _zz_456; - wire [31:0] _zz_457; - wire [31:0] _zz_458; + wire _zz_448; + wire [0:0] _zz_449; + wire [0:0] _zz_450; + wire [31:0] _zz_451; + wire [31:0] _zz_452; + wire [0:0] _zz_453; + wire [1:0] _zz_454; + wire [1:0] _zz_455; + wire [1:0] _zz_456; + wire _zz_457; + wire _zz_458; wire [31:0] _zz_459; wire [31:0] _zz_460; wire [31:0] _zz_461; wire [31:0] _zz_462; - wire _zz_463; + wire [31:0] _zz_463; wire [31:0] _zz_464; wire [31:0] _zz_465; - wire _zz_466; - wire _zz_467; + wire [31:0] _zz_466; + wire [31:0] _zz_467; wire _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire _zz_471; + wire _zz_472; + wire _zz_473; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -845,42 +845,37 @@ module VexRiscv ( wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; reg [31:0] _zz_106; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_107; - wire _zz_108; - wire _zz_109; - wire _zz_110; - wire _zz_111; + reg _zz_107; + reg _zz_108; + reg _zz_109; + reg [4:0] _zz_110; + reg [31:0] _zz_111; wire _zz_112; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_113; - reg _zz_114; - reg _zz_115; + wire _zz_113; + wire _zz_114; + wire _zz_115; wire _zz_116; - reg [19:0] _zz_117; - wire _zz_118; - reg [10:0] _zz_119; - wire _zz_120; - reg [18:0] _zz_121; - reg _zz_122; + wire _zz_117; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_118; + reg _zz_119; + reg _zz_120; + wire _zz_121; + reg [19:0] _zz_122; + wire _zz_123; + reg [10:0] _zz_124; + wire _zz_125; + reg [18:0] _zz_126; + reg _zz_127; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_123; - reg [19:0] _zz_124; - wire _zz_125; - reg [10:0] _zz_126; - wire _zz_127; - reg [18:0] _zz_128; + wire _zz_128; + reg [19:0] _zz_129; + wire _zz_130; + reg [10:0] _zz_131; + wire _zz_132; + reg [18:0] _zz_133; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; @@ -901,9 +896,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_129; - wire _zz_130; - wire _zz_131; + wire _zz_134; + wire _zz_135; + wire _zz_136; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -916,10 +911,10 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_132; - wire _zz_133; - wire [1:0] _zz_134; - wire _zz_135; + wire [1:0] _zz_137; + wire _zz_138; + wire [1:0] _zz_139; + wire _zz_140; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -967,18 +962,18 @@ module VexRiscv ( wire memory_MulDivIterativePlugin_div_counter_willOverflow; reg memory_MulDivIterativePlugin_div_done; reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_136; + wire [31:0] _zz_141; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [31:0] _zz_137; - wire _zz_138; - wire _zz_139; - reg [32:0] _zz_140; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_141; wire [31:0] _zz_142; + wire _zz_143; + wire _zz_144; + reg [32:0] _zz_145; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_146; + wire [31:0] _zz_147; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1051,16 +1046,16 @@ module VexRiscv ( reg execute_CsrPlugin_csr_835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_143; - reg [31:0] _zz_144; - reg [31:0] _zz_145; - reg [31:0] _zz_146; - reg [31:0] _zz_147; reg [31:0] _zz_148; reg [31:0] _zz_149; reg [31:0] _zz_150; - reg [2:0] _zz_151; - reg _zz_152; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [2:0] _zz_156; + reg _zz_157; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -1074,7 +1069,7 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_153; + reg [3:0] _zz_158; `ifndef SYNTHESIS reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; @@ -1153,318 +1148,318 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_166 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_167 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_168 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_169 = 1'b1; - assign _zz_170 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_171 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_172 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_173 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_174 = ((_zz_159 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_175 = ((_zz_159 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_176 = ((_zz_159 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_177 = ((_zz_159 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_178 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_179 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_180 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_181 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_182 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_183 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_184 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_185 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_186 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_187 = (1'b0 || (! 1'b1)); - assign _zz_188 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_189 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_190 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_191 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_192 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_193 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_194 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_195 = (! memory_arbitration_isStuck); - assign _zz_196 = (iBus_cmd_valid || (_zz_151 != 3'b000)); - assign _zz_197 = (! execute_arbitration_isStuckByOthers); - assign _zz_198 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_199 = ((_zz_129 && 1'b1) && (! 1'b0)); - assign _zz_200 = ((_zz_130 && 1'b1) && (! 1'b0)); - assign _zz_201 = ((_zz_131 && 1'b1) && (! 1'b0)); - assign _zz_202 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_203 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_204 = execute_INSTRUCTION[13]; - assign _zz_205 = _zz_84[30 : 30]; - assign _zz_206 = _zz_84[29 : 29]; - assign _zz_207 = _zz_84[28 : 28]; - assign _zz_208 = _zz_84[27 : 27]; - assign _zz_209 = _zz_84[24 : 24]; - assign _zz_210 = _zz_84[16 : 16]; - assign _zz_211 = _zz_84[13 : 13]; - assign _zz_212 = _zz_84[12 : 12]; - assign _zz_213 = _zz_84[11 : 11]; - assign _zz_214 = _zz_84[15 : 15]; - assign _zz_215 = _zz_84[5 : 5]; - assign _zz_216 = _zz_84[3 : 3]; - assign _zz_217 = _zz_84[19 : 19]; - assign _zz_218 = _zz_84[10 : 10]; - assign _zz_219 = _zz_84[4 : 4]; - assign _zz_220 = _zz_84[0 : 0]; - assign _zz_221 = (_zz_51 - 4'b0001); - assign _zz_222 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_223 = {29'd0, _zz_222}; - assign _zz_224 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_225 = {{_zz_66,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_226 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_227 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_228 = {{_zz_68,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_229 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_230 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_231 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_232 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_233 = execute_SRC_LESS; - assign _zz_234 = 3'b100; - assign _zz_235 = execute_INSTRUCTION[19 : 15]; - assign _zz_236 = execute_INSTRUCTION[31 : 20]; - assign _zz_237 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_238 = ($signed(_zz_239) + $signed(_zz_242)); - assign _zz_239 = ($signed(_zz_240) + $signed(_zz_241)); - assign _zz_240 = execute_SRC1; - assign _zz_241 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_242 = (execute_SRC_USE_SUB_LESS ? _zz_243 : _zz_244); - assign _zz_243 = 32'h00000001; - assign _zz_244 = 32'h0; - assign _zz_245 = (_zz_246 >>> 1); - assign _zz_246 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_247 = execute_INSTRUCTION[31 : 20]; - assign _zz_248 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_249 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_250 = {_zz_117,execute_INSTRUCTION[31 : 20]}; - assign _zz_251 = {{_zz_119,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_252 = {{_zz_121,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_253 = execute_INSTRUCTION[31 : 20]; - assign _zz_254 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_255 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_256 = 3'b100; - assign _zz_257 = (_zz_132 & (~ _zz_258)); - assign _zz_258 = (_zz_132 - 2'b01); - assign _zz_259 = (_zz_134 & (~ _zz_260)); - assign _zz_260 = (_zz_134 - 2'b01); - assign _zz_261 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_262 = {5'd0, _zz_261}; - assign _zz_263 = (_zz_265 + _zz_267); - assign _zz_264 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_265 = {{1{_zz_264[32]}}, _zz_264}; - assign _zz_266 = _zz_268; - assign _zz_267 = {{1{_zz_266[32]}}, _zz_266}; - assign _zz_268 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_269 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_270 = {5'd0, _zz_269}; - assign _zz_271 = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_272 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_273 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_274 = {_zz_136,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_275 = _zz_276; - assign _zz_276 = _zz_277; - assign _zz_277 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_137) : _zz_137)} + _zz_279); - assign _zz_278 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_279 = {32'd0, _zz_278}; - assign _zz_280 = _zz_139; - assign _zz_281 = {32'd0, _zz_280}; - assign _zz_282 = _zz_138; - assign _zz_283 = {31'd0, _zz_282}; - assign _zz_284 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_285 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_286 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_287 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_288 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_289 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_290 = (iBus_cmd_payload_address >>> 5); - assign _zz_291 = 1'b1; - assign _zz_292 = 1'b1; - assign _zz_293 = {_zz_55,_zz_54}; - assign _zz_294 = 32'h0000107f; - assign _zz_295 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_296 = 32'h00002073; - assign _zz_297 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_298 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_299 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_300) == 32'h00000003),{(_zz_301 == _zz_302),{_zz_303,{_zz_304,_zz_305}}}}}}; - assign _zz_300 = 32'h0000505f; - assign _zz_301 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_302 = 32'h00000063; - assign _zz_303 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_304 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_305 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_306) == 32'h00005033),{(_zz_307 == _zz_308),{_zz_309,{_zz_310,_zz_311}}}}}}; - assign _zz_306 = 32'hbe00707f; - assign _zz_307 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_308 = 32'h00000033; - assign _zz_309 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_310 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_311 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); - assign _zz_312 = decode_INSTRUCTION[31]; - assign _zz_313 = decode_INSTRUCTION[31]; - assign _zz_314 = decode_INSTRUCTION[7]; - assign _zz_315 = 32'h02004064; - assign _zz_316 = _zz_90; - assign _zz_317 = {_zz_88,_zz_89}; - assign _zz_318 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_319 = 1'b0; - assign _zz_320 = (((decode_INSTRUCTION & _zz_323) == 32'h00000050) != 1'b0); - assign _zz_321 = ((_zz_324 == _zz_325) != 1'b0); - assign _zz_322 = {({_zz_326,_zz_327} != 2'b00),{(_zz_328 != _zz_329),{_zz_330,{_zz_331,_zz_332}}}}; - assign _zz_323 = 32'h10003050; - assign _zz_324 = (decode_INSTRUCTION & 32'h10403050); - assign _zz_325 = 32'h10000050; - assign _zz_326 = ((decode_INSTRUCTION & _zz_333) == 32'h00001050); - assign _zz_327 = ((decode_INSTRUCTION & _zz_334) == 32'h00002050); - assign _zz_328 = {_zz_87,(_zz_335 == _zz_336)}; - assign _zz_329 = 2'b00; - assign _zz_330 = ((_zz_337 == _zz_338) != 1'b0); - assign _zz_331 = ({_zz_339,_zz_340} != 2'b00); - assign _zz_332 = {(_zz_341 != _zz_342),{_zz_343,{_zz_344,_zz_345}}}; - assign _zz_333 = 32'h00001050; - assign _zz_334 = 32'h00002050; - assign _zz_335 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_336 = 32'h00000004; - assign _zz_337 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_338 = 32'h00000040; - assign _zz_339 = ((decode_INSTRUCTION & _zz_346) == 32'h00005010); - assign _zz_340 = ((decode_INSTRUCTION & _zz_347) == 32'h00005020); - assign _zz_341 = {(_zz_348 == _zz_349),{_zz_350,_zz_351}}; - assign _zz_342 = 3'b000; - assign _zz_343 = ({_zz_352,{_zz_353,_zz_354}} != 3'b000); - assign _zz_344 = (_zz_355 != 1'b0); - assign _zz_345 = {(_zz_356 != _zz_357),{_zz_358,{_zz_359,_zz_360}}}; - assign _zz_346 = 32'h00007034; - assign _zz_347 = 32'h02007064; - assign _zz_348 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_349 = 32'h40001010; - assign _zz_350 = ((decode_INSTRUCTION & _zz_361) == 32'h00001010); - assign _zz_351 = ((decode_INSTRUCTION & _zz_362) == 32'h00001010); - assign _zz_352 = ((decode_INSTRUCTION & _zz_363) == 32'h00000024); - assign _zz_353 = (_zz_364 == _zz_365); - assign _zz_354 = (_zz_366 == _zz_367); - assign _zz_355 = ((decode_INSTRUCTION & _zz_368) == 32'h00001000); - assign _zz_356 = _zz_88; - assign _zz_357 = 1'b0; - assign _zz_358 = ({_zz_369,_zz_370} != 2'b00); - assign _zz_359 = (_zz_371 != _zz_372); - assign _zz_360 = {_zz_373,{_zz_374,_zz_375}}; - assign _zz_361 = 32'h00007034; - assign _zz_362 = 32'h02007054; - assign _zz_363 = 32'h00000064; - assign _zz_364 = (decode_INSTRUCTION & 32'h00003034); - assign _zz_365 = 32'h00001010; - assign _zz_366 = (decode_INSTRUCTION & 32'h02003054); - assign _zz_367 = 32'h00001010; - assign _zz_368 = 32'h00001000; - assign _zz_369 = ((decode_INSTRUCTION & _zz_376) == 32'h00002000); - assign _zz_370 = ((decode_INSTRUCTION & _zz_377) == 32'h00001000); - assign _zz_371 = {(_zz_378 == _zz_379),(_zz_380 == _zz_381)}; - assign _zz_372 = 2'b00; - assign _zz_373 = ({_zz_382,{_zz_383,_zz_384}} != 3'b000); - assign _zz_374 = (_zz_385 != 1'b0); - assign _zz_375 = {(_zz_386 != _zz_387),{_zz_388,{_zz_389,_zz_390}}}; - assign _zz_376 = 32'h00002010; - assign _zz_377 = 32'h00005000; - assign _zz_378 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_379 = 32'h00000020; - assign _zz_380 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_381 = 32'h00000020; - assign _zz_382 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); - assign _zz_383 = ((decode_INSTRUCTION & _zz_391) == 32'h0); - assign _zz_384 = ((decode_INSTRUCTION & _zz_392) == 32'h00000040); - assign _zz_385 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz_386 = ((decode_INSTRUCTION & _zz_393) == 32'h00000010); - assign _zz_387 = 1'b0; - assign _zz_388 = ({_zz_86,{_zz_394,_zz_395}} != 3'b000); - assign _zz_389 = ({_zz_396,_zz_397} != 6'h0); - assign _zz_390 = {(_zz_398 != _zz_399),{_zz_400,{_zz_401,_zz_402}}}; - assign _zz_391 = 32'h00000038; - assign _zz_392 = 32'h00403040; - assign _zz_393 = 32'h00000010; - assign _zz_394 = ((decode_INSTRUCTION & _zz_403) == 32'h00000010); - assign _zz_395 = ((decode_INSTRUCTION & _zz_404) == 32'h00000020); - assign _zz_396 = _zz_87; - assign _zz_397 = {(_zz_405 == _zz_406),{_zz_407,{_zz_408,_zz_409}}}; - assign _zz_398 = {_zz_86,(_zz_410 == _zz_411)}; - assign _zz_399 = 2'b00; - assign _zz_400 = ({_zz_86,_zz_412} != 2'b00); - assign _zz_401 = ({_zz_413,_zz_414} != 2'b00); - assign _zz_402 = {(_zz_415 != _zz_416),{_zz_417,{_zz_418,_zz_419}}}; - assign _zz_403 = 32'h00000030; - assign _zz_404 = 32'h02000060; - assign _zz_405 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_406 = 32'h00001010; - assign _zz_407 = ((decode_INSTRUCTION & _zz_420) == 32'h00002010); - assign _zz_408 = (_zz_421 == _zz_422); - assign _zz_409 = {_zz_423,_zz_424}; - assign _zz_410 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_411 = 32'h00000020; - assign _zz_412 = ((decode_INSTRUCTION & _zz_425) == 32'h0); + assign _zz_171 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_172 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_173 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_174 = 1'b1; + assign _zz_175 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_176 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_177 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_178 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_179 = ((_zz_164 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_180 = ((_zz_164 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_181 = ((_zz_164 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_182 = ((_zz_164 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_183 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_184 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_185 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_186 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_187 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_188 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_189 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_190 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_191 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_192 = (1'b0 || (! 1'b1)); + assign _zz_193 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_194 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_195 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_196 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_197 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_198 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_199 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_200 = (! memory_arbitration_isStuck); + assign _zz_201 = (iBus_cmd_valid || (_zz_156 != 3'b000)); + assign _zz_202 = (! execute_arbitration_isStuckByOthers); + assign _zz_203 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_204 = ((_zz_134 && 1'b1) && (! 1'b0)); + assign _zz_205 = ((_zz_135 && 1'b1) && (! 1'b0)); + assign _zz_206 = ((_zz_136 && 1'b1) && (! 1'b0)); + assign _zz_207 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_208 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_209 = execute_INSTRUCTION[13]; + assign _zz_210 = _zz_84[30 : 30]; + assign _zz_211 = _zz_84[29 : 29]; + assign _zz_212 = _zz_84[28 : 28]; + assign _zz_213 = _zz_84[27 : 27]; + assign _zz_214 = _zz_84[24 : 24]; + assign _zz_215 = _zz_84[16 : 16]; + assign _zz_216 = _zz_84[13 : 13]; + assign _zz_217 = _zz_84[12 : 12]; + assign _zz_218 = _zz_84[11 : 11]; + assign _zz_219 = _zz_84[15 : 15]; + assign _zz_220 = _zz_84[5 : 5]; + assign _zz_221 = _zz_84[3 : 3]; + assign _zz_222 = _zz_84[19 : 19]; + assign _zz_223 = _zz_84[10 : 10]; + assign _zz_224 = _zz_84[4 : 4]; + assign _zz_225 = _zz_84[0 : 0]; + assign _zz_226 = (_zz_51 - 4'b0001); + assign _zz_227 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_228 = {29'd0, _zz_227}; + assign _zz_229 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_230 = {{_zz_66,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_231 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_232 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_233 = {{_zz_68,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_234 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_235 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_236 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_237 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_238 = execute_SRC_LESS; + assign _zz_239 = 3'b100; + assign _zz_240 = execute_INSTRUCTION[19 : 15]; + assign _zz_241 = execute_INSTRUCTION[31 : 20]; + assign _zz_242 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_243 = ($signed(_zz_244) + $signed(_zz_247)); + assign _zz_244 = ($signed(_zz_245) + $signed(_zz_246)); + assign _zz_245 = execute_SRC1; + assign _zz_246 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_247 = (execute_SRC_USE_SUB_LESS ? _zz_248 : _zz_249); + assign _zz_248 = 32'h00000001; + assign _zz_249 = 32'h0; + assign _zz_250 = (_zz_251 >>> 1); + assign _zz_251 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_252 = execute_INSTRUCTION[31 : 20]; + assign _zz_253 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_254 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_255 = {_zz_122,execute_INSTRUCTION[31 : 20]}; + assign _zz_256 = {{_zz_124,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_257 = {{_zz_126,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_258 = execute_INSTRUCTION[31 : 20]; + assign _zz_259 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_260 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_261 = 3'b100; + assign _zz_262 = (_zz_137 & (~ _zz_263)); + assign _zz_263 = (_zz_137 - 2'b01); + assign _zz_264 = (_zz_139 & (~ _zz_265)); + assign _zz_265 = (_zz_139 - 2'b01); + assign _zz_266 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_267 = {5'd0, _zz_266}; + assign _zz_268 = (_zz_270 + _zz_272); + assign _zz_269 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_270 = {{1{_zz_269[32]}}, _zz_269}; + assign _zz_271 = _zz_273; + assign _zz_272 = {{1{_zz_271[32]}}, _zz_271}; + assign _zz_273 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_274 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_275 = {5'd0, _zz_274}; + assign _zz_276 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_277 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_278 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_279 = {_zz_141,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_280 = _zz_281; + assign _zz_281 = _zz_282; + assign _zz_282 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_142) : _zz_142)} + _zz_284); + assign _zz_283 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_284 = {32'd0, _zz_283}; + assign _zz_285 = _zz_144; + assign _zz_286 = {32'd0, _zz_285}; + assign _zz_287 = _zz_143; + assign _zz_288 = {31'd0, _zz_287}; + assign _zz_289 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_290 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_291 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_292 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_293 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_294 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_295 = (iBus_cmd_payload_address >>> 5); + assign _zz_296 = 1'b1; + assign _zz_297 = 1'b1; + assign _zz_298 = {_zz_55,_zz_54}; + assign _zz_299 = 32'h0000107f; + assign _zz_300 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_301 = 32'h00002073; + assign _zz_302 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_303 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_304 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_305) == 32'h00000003),{(_zz_306 == _zz_307),{_zz_308,{_zz_309,_zz_310}}}}}}; + assign _zz_305 = 32'h0000505f; + assign _zz_306 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_307 = 32'h00000063; + assign _zz_308 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_309 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_310 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_311) == 32'h00005033),{(_zz_312 == _zz_313),{_zz_314,{_zz_315,_zz_316}}}}}}; + assign _zz_311 = 32'hbe00707f; + assign _zz_312 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_313 = 32'h00000033; + assign _zz_314 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_315 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_316 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_317 = decode_INSTRUCTION[31]; + assign _zz_318 = decode_INSTRUCTION[31]; + assign _zz_319 = decode_INSTRUCTION[7]; + assign _zz_320 = 32'h02004064; + assign _zz_321 = _zz_90; + assign _zz_322 = {_zz_88,_zz_89}; + assign _zz_323 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_324 = 1'b0; + assign _zz_325 = (((decode_INSTRUCTION & _zz_328) == 32'h00000050) != 1'b0); + assign _zz_326 = ((_zz_329 == _zz_330) != 1'b0); + assign _zz_327 = {({_zz_331,_zz_332} != 2'b00),{(_zz_333 != _zz_334),{_zz_335,{_zz_336,_zz_337}}}}; + assign _zz_328 = 32'h10003050; + assign _zz_329 = (decode_INSTRUCTION & 32'h10403050); + assign _zz_330 = 32'h10000050; + assign _zz_331 = ((decode_INSTRUCTION & _zz_338) == 32'h00001050); + assign _zz_332 = ((decode_INSTRUCTION & _zz_339) == 32'h00002050); + assign _zz_333 = {_zz_87,(_zz_340 == _zz_341)}; + assign _zz_334 = 2'b00; + assign _zz_335 = ((_zz_342 == _zz_343) != 1'b0); + assign _zz_336 = ({_zz_344,_zz_345} != 2'b00); + assign _zz_337 = {(_zz_346 != _zz_347),{_zz_348,{_zz_349,_zz_350}}}; + assign _zz_338 = 32'h00001050; + assign _zz_339 = 32'h00002050; + assign _zz_340 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_341 = 32'h00000004; + assign _zz_342 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_343 = 32'h00000040; + assign _zz_344 = ((decode_INSTRUCTION & _zz_351) == 32'h00005010); + assign _zz_345 = ((decode_INSTRUCTION & _zz_352) == 32'h00005020); + assign _zz_346 = {(_zz_353 == _zz_354),{_zz_355,_zz_356}}; + assign _zz_347 = 3'b000; + assign _zz_348 = ({_zz_357,{_zz_358,_zz_359}} != 3'b000); + assign _zz_349 = (_zz_360 != 1'b0); + assign _zz_350 = {(_zz_361 != _zz_362),{_zz_363,{_zz_364,_zz_365}}}; + assign _zz_351 = 32'h00007034; + assign _zz_352 = 32'h02007064; + assign _zz_353 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_354 = 32'h40001010; + assign _zz_355 = ((decode_INSTRUCTION & _zz_366) == 32'h00001010); + assign _zz_356 = ((decode_INSTRUCTION & _zz_367) == 32'h00001010); + assign _zz_357 = ((decode_INSTRUCTION & _zz_368) == 32'h00000024); + assign _zz_358 = (_zz_369 == _zz_370); + assign _zz_359 = (_zz_371 == _zz_372); + assign _zz_360 = ((decode_INSTRUCTION & _zz_373) == 32'h00001000); + assign _zz_361 = _zz_88; + assign _zz_362 = 1'b0; + assign _zz_363 = ({_zz_374,_zz_375} != 2'b00); + assign _zz_364 = (_zz_376 != _zz_377); + assign _zz_365 = {_zz_378,{_zz_379,_zz_380}}; + assign _zz_366 = 32'h00007034; + assign _zz_367 = 32'h02007054; + assign _zz_368 = 32'h00000064; + assign _zz_369 = (decode_INSTRUCTION & 32'h00003034); + assign _zz_370 = 32'h00001010; + assign _zz_371 = (decode_INSTRUCTION & 32'h02003054); + assign _zz_372 = 32'h00001010; + assign _zz_373 = 32'h00001000; + assign _zz_374 = ((decode_INSTRUCTION & _zz_381) == 32'h00002000); + assign _zz_375 = ((decode_INSTRUCTION & _zz_382) == 32'h00001000); + assign _zz_376 = {(_zz_383 == _zz_384),(_zz_385 == _zz_386)}; + assign _zz_377 = 2'b00; + assign _zz_378 = ({_zz_387,{_zz_388,_zz_389}} != 3'b000); + assign _zz_379 = (_zz_390 != 1'b0); + assign _zz_380 = {(_zz_391 != _zz_392),{_zz_393,{_zz_394,_zz_395}}}; + assign _zz_381 = 32'h00002010; + assign _zz_382 = 32'h00005000; + assign _zz_383 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_384 = 32'h00000020; + assign _zz_385 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_386 = 32'h00000020; + assign _zz_387 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_388 = ((decode_INSTRUCTION & _zz_396) == 32'h0); + assign _zz_389 = ((decode_INSTRUCTION & _zz_397) == 32'h00000040); + assign _zz_390 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_391 = ((decode_INSTRUCTION & _zz_398) == 32'h00000010); + assign _zz_392 = 1'b0; + assign _zz_393 = ({_zz_86,{_zz_399,_zz_400}} != 3'b000); + assign _zz_394 = ({_zz_401,_zz_402} != 6'h0); + assign _zz_395 = {(_zz_403 != _zz_404),{_zz_405,{_zz_406,_zz_407}}}; + assign _zz_396 = 32'h00000038; + assign _zz_397 = 32'h00403040; + assign _zz_398 = 32'h00000010; + assign _zz_399 = ((decode_INSTRUCTION & _zz_408) == 32'h00000010); + assign _zz_400 = ((decode_INSTRUCTION & _zz_409) == 32'h00000020); + assign _zz_401 = _zz_87; + assign _zz_402 = {(_zz_410 == _zz_411),{_zz_412,{_zz_413,_zz_414}}}; + assign _zz_403 = {_zz_86,(_zz_415 == _zz_416)}; + assign _zz_404 = 2'b00; + assign _zz_405 = ({_zz_86,_zz_417} != 2'b00); + assign _zz_406 = ({_zz_418,_zz_419} != 2'b00); + assign _zz_407 = {(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}; + assign _zz_408 = 32'h00000030; + assign _zz_409 = 32'h02000060; + assign _zz_410 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_411 = 32'h00001010; + assign _zz_412 = ((decode_INSTRUCTION & _zz_425) == 32'h00002010); assign _zz_413 = (_zz_426 == _zz_427); - assign _zz_414 = (_zz_428 == _zz_429); - assign _zz_415 = (_zz_430 == _zz_431); - assign _zz_416 = 1'b0; - assign _zz_417 = ({_zz_432,_zz_433} != 4'b0000); - assign _zz_418 = (_zz_434 != _zz_435); - assign _zz_419 = {_zz_436,{_zz_437,_zz_438}}; - assign _zz_420 = 32'h00002010; - assign _zz_421 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_422 = 32'h00000010; - assign _zz_423 = ((decode_INSTRUCTION & _zz_439) == 32'h00000004); - assign _zz_424 = ((decode_INSTRUCTION & _zz_440) == 32'h0); - assign _zz_425 = 32'h00000020; - assign _zz_426 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_427 = 32'h00006010; - assign _zz_428 = (decode_INSTRUCTION & 32'h00005014); - assign _zz_429 = 32'h00004010; - assign _zz_430 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_431 = 32'h00002010; - assign _zz_432 = (_zz_441 == _zz_442); - assign _zz_433 = {_zz_443,{_zz_444,_zz_445}}; - assign _zz_434 = (_zz_446 == _zz_447); - assign _zz_435 = 1'b0; - assign _zz_436 = ({_zz_448,_zz_449} != 3'b000); - assign _zz_437 = (_zz_450 != _zz_451); - assign _zz_438 = {_zz_452,_zz_453}; - assign _zz_439 = 32'h0000000c; - assign _zz_440 = 32'h00000028; - assign _zz_441 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_442 = 32'h0; - assign _zz_443 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); - assign _zz_444 = ((decode_INSTRUCTION & _zz_454) == 32'h00002000); - assign _zz_445 = ((decode_INSTRUCTION & _zz_455) == 32'h00001000); - assign _zz_446 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_414 = {_zz_428,_zz_429}; + assign _zz_415 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_416 = 32'h00000020; + assign _zz_417 = ((decode_INSTRUCTION & _zz_430) == 32'h0); + assign _zz_418 = (_zz_431 == _zz_432); + assign _zz_419 = (_zz_433 == _zz_434); + assign _zz_420 = (_zz_435 == _zz_436); + assign _zz_421 = 1'b0; + assign _zz_422 = ({_zz_437,_zz_438} != 4'b0000); + assign _zz_423 = (_zz_439 != _zz_440); + assign _zz_424 = {_zz_441,{_zz_442,_zz_443}}; + assign _zz_425 = 32'h00002010; + assign _zz_426 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_427 = 32'h00000010; + assign _zz_428 = ((decode_INSTRUCTION & _zz_444) == 32'h00000004); + assign _zz_429 = ((decode_INSTRUCTION & _zz_445) == 32'h0); + assign _zz_430 = 32'h00000020; + assign _zz_431 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_432 = 32'h00006010; + assign _zz_433 = (decode_INSTRUCTION & 32'h00005014); + assign _zz_434 = 32'h00004010; + assign _zz_435 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_436 = 32'h00002010; + assign _zz_437 = (_zz_446 == _zz_447); + assign _zz_438 = {_zz_448,{_zz_449,_zz_450}}; + assign _zz_439 = (_zz_451 == _zz_452); + assign _zz_440 = 1'b0; + assign _zz_441 = ({_zz_453,_zz_454} != 3'b000); + assign _zz_442 = (_zz_455 != _zz_456); + assign _zz_443 = {_zz_457,_zz_458}; + assign _zz_444 = 32'h0000000c; + assign _zz_445 = 32'h00000028; + assign _zz_446 = (decode_INSTRUCTION & 32'h00000044); assign _zz_447 = 32'h0; - assign _zz_448 = ((decode_INSTRUCTION & _zz_456) == 32'h00000040); - assign _zz_449 = {(_zz_457 == _zz_458),(_zz_459 == _zz_460)}; - assign _zz_450 = {(_zz_461 == _zz_462),_zz_85}; - assign _zz_451 = 2'b00; - assign _zz_452 = ({_zz_463,_zz_85} != 2'b00); - assign _zz_453 = ((_zz_464 == _zz_465) != 1'b0); - assign _zz_454 = 32'h00006004; - assign _zz_455 = 32'h00005004; - assign _zz_456 = 32'h00000044; - assign _zz_457 = (decode_INSTRUCTION & 32'h00002014); - assign _zz_458 = 32'h00002010; - assign _zz_459 = (decode_INSTRUCTION & 32'h40004034); - assign _zz_460 = 32'h40000030; - assign _zz_461 = (decode_INSTRUCTION & 32'h00000014); - assign _zz_462 = 32'h00000004; - assign _zz_463 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_464 = (decode_INSTRUCTION & 32'h00001048); - assign _zz_465 = 32'h00001008; - assign _zz_466 = execute_INSTRUCTION[31]; - assign _zz_467 = execute_INSTRUCTION[31]; - assign _zz_468 = execute_INSTRUCTION[7]; + assign _zz_448 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz_449 = ((decode_INSTRUCTION & _zz_459) == 32'h00002000); + assign _zz_450 = ((decode_INSTRUCTION & _zz_460) == 32'h00001000); + assign _zz_451 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_452 = 32'h0; + assign _zz_453 = ((decode_INSTRUCTION & _zz_461) == 32'h00000040); + assign _zz_454 = {(_zz_462 == _zz_463),(_zz_464 == _zz_465)}; + assign _zz_455 = {(_zz_466 == _zz_467),_zz_85}; + assign _zz_456 = 2'b00; + assign _zz_457 = ({_zz_468,_zz_85} != 2'b00); + assign _zz_458 = ((_zz_469 == _zz_470) != 1'b0); + assign _zz_459 = 32'h00006004; + assign _zz_460 = 32'h00005004; + assign _zz_461 = 32'h00000044; + assign _zz_462 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_463 = 32'h00002010; + assign _zz_464 = (decode_INSTRUCTION & 32'h40004034); + assign _zz_465 = 32'h40000030; + assign _zz_466 = (decode_INSTRUCTION & 32'h00000014); + assign _zz_467 = 32'h00000004; + assign _zz_468 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_469 = (decode_INSTRUCTION & 32'h00001048); + assign _zz_470 = 32'h00001008; + assign _zz_471 = execute_INSTRUCTION[31]; + assign _zz_472 = execute_INSTRUCTION[31]; + assign _zz_473 = execute_INSTRUCTION[7]; always @ (posedge clk) begin - if(_zz_291) begin - _zz_163 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_296) begin + _zz_168 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_292) begin - _zz_164 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_297) begin + _zz_169 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1475,13 +1470,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_154 ), //i - .io_cpu_prefetch_isValid (_zz_155 ), //i + .io_flush (_zz_159 ), //i + .io_cpu_prefetch_isValid (_zz_160 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_156 ), //i - .io_cpu_fetch_isStuck (_zz_157 ), //i - .io_cpu_fetch_isRemoved (_zz_158 ), //i + .io_cpu_fetch_isValid (_zz_161 ), //i + .io_cpu_fetch_isStuck (_zz_162 ), //i + .io_cpu_fetch_isRemoved (_zz_163 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1494,8 +1489,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_159 ), //i - .io_cpu_decode_isStuck (_zz_160 ), //i + .io_cpu_decode_isValid (_zz_164 ), //i + .io_cpu_decode_isStuck (_zz_165 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1503,8 +1498,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_161 ), //i - .io_cpu_fill_valid (_zz_162 ), //i + .io_cpu_decode_isUser (_zz_166 ), //i + .io_cpu_fill_valid (_zz_167 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1517,18 +1512,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_293) + case(_zz_298) 2'b00 : begin - _zz_165 = CsrPlugin_jumpInterface_payload; + _zz_170 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_165 = DBusSimplePlugin_redoBranch_payload; + _zz_170 = DBusSimplePlugin_redoBranch_payload; end 2'b10 : begin - _zz_165 = BranchPlugin_jumpInterface_payload; + _zz_170 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_165 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_170 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2167,25 +2162,25 @@ module VexRiscv ( assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_DIV = _zz_205[0]; - assign decode_IS_RS2_SIGNED = _zz_206[0]; - assign decode_IS_RS1_SIGNED = _zz_207[0]; - assign decode_IS_MUL = _zz_208[0]; + assign decode_IS_DIV = _zz_210[0]; + assign decode_IS_RS2_SIGNED = _zz_211[0]; + assign decode_IS_RS1_SIGNED = _zz_212[0]; + assign decode_IS_MUL = _zz_213[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_209[0]; + assign decode_IS_CSR = _zz_214[0]; assign _zz_8 = _zz_9; assign decode_SHIFT_CTRL = _zz_10; assign _zz_11 = _zz_12; assign decode_ALU_BITWISE_CTRL = _zz_13; assign _zz_14 = _zz_15; - assign decode_SRC_LESS_UNSIGNED = _zz_210[0]; - assign decode_MEMORY_STORE = _zz_211[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_215[0]; + assign decode_MEMORY_STORE = _zz_216[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_212[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_213[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_217[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_218[0]; assign decode_SRC2_CTRL = _zz_16; assign _zz_17 = _zz_18; assign decode_ALU_CTRL = _zz_19; @@ -2213,18 +2208,18 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_115; + assign execute_BRANCH_COND_RESULT = _zz_120; assign execute_BRANCH_CTRL = _zz_28; - assign decode_RS2_USE = _zz_214[0]; - assign decode_RS1_USE = _zz_215[0]; + assign decode_RS2_USE = _zz_219[0]; + assign decode_RS1_USE = _zz_220[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; always @ (*) begin _zz_29 = memory_REGFILE_WRITE_DATA; - if(_zz_166)begin + if(_zz_171)begin _zz_29 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_167)begin + if(_zz_172)begin _zz_29 = memory_MulDivIterativePlugin_div_result; end end @@ -2235,28 +2230,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_109)begin + if((_zz_110 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_111; end end - if(_zz_168)begin - if(_zz_169)begin - if(_zz_108)begin + if(_zz_173)begin + if(_zz_174)begin + if(_zz_113)begin decode_RS2 = _zz_47; end end end - if(_zz_170)begin + if(_zz_175)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_110)begin + if(_zz_115)begin decode_RS2 = _zz_29; end end end - if(_zz_171)begin + if(_zz_176)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_112)begin + if(_zz_117)begin decode_RS2 = _zz_30; end end @@ -2265,28 +2260,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_109)begin + if((_zz_110 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_111; end end - if(_zz_168)begin - if(_zz_169)begin - if(_zz_107)begin + if(_zz_173)begin + if(_zz_174)begin + if(_zz_112)begin decode_RS1 = _zz_47; end end end - if(_zz_170)begin + if(_zz_175)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_109)begin + if(_zz_114)begin decode_RS1 = _zz_29; end end end - if(_zz_171)begin + if(_zz_176)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_111)begin + if(_zz_116)begin decode_RS1 = _zz_30; end end @@ -2295,10 +2290,10 @@ module VexRiscv ( always @ (*) begin _zz_30 = execute_REGFILE_WRITE_DATA; - if(_zz_172)begin + if(_zz_177)begin _zz_30 = _zz_106; end - if(_zz_173)begin + if(_zz_178)begin _zz_30 = execute_CsrPlugin_readData; end end @@ -2310,8 +2305,8 @@ module VexRiscv ( assign _zz_32 = execute_PC; assign execute_SRC2_CTRL = _zz_33; assign execute_SRC1_CTRL = _zz_34; - assign decode_SRC_USE_SUB_LESS = _zz_216[0]; - assign decode_SRC_ADD_ZERO = _zz_217[0]; + assign decode_SRC_USE_SUB_LESS = _zz_221[0]; + assign decode_SRC_ADD_ZERO = _zz_222[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_35; @@ -2329,13 +2324,13 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_218[0]; + decode_REGFILE_WRITE_VALID = _zz_223[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_294) == 32'h00001073),{(_zz_295 == _zz_296),{_zz_297,{_zz_298,_zz_299}}}}}}} != 20'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_299) == 32'h00001073),{(_zz_300 == _zz_301),{_zz_302,{_zz_303,_zz_304}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin _zz_47 = writeBack_REGFILE_WRITE_DATA; @@ -2378,32 +2373,32 @@ module VexRiscv ( assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_219[0]; - assign decode_FLUSH_ALL = _zz_220[0]; + assign decode_MEMORY_ENABLE = _zz_224[0]; + assign decode_FLUSH_ALL = _zz_225[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_174)begin + if(_zz_179)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_175)begin + if(_zz_180)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_176)begin + if(_zz_181)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_177)begin + if(_zz_182)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2439,7 +2434,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_107 || _zz_108)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2452,7 +2447,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_178)begin + if(_zz_183)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2466,7 +2461,7 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_178)begin + if(_zz_183)begin decode_arbitration_flushNext = 1'b1; end end @@ -2476,12 +2471,12 @@ module VexRiscv ( if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_77)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_172)begin + if(_zz_177)begin if((! execute_LightShifterPlugin_done))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_173)begin + if(_zz_178)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2512,15 +2507,15 @@ module VexRiscv ( if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_166)begin + if(_zz_171)begin if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_179)begin + if(_zz_184)begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_167)begin + if(_zz_172)begin if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2530,7 +2525,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_180)begin + if(_zz_185)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2553,7 +2548,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_180)begin + if(_zz_185)begin memory_arbitration_flushNext = 1'b1; end end @@ -2570,10 +2565,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_181)begin + if(_zz_186)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_182)begin + if(_zz_187)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2587,10 +2582,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_181)begin + if(_zz_186)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_182)begin + if(_zz_187)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -2606,21 +2601,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_181)begin + if(_zz_186)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_182)begin + if(_zz_187)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_181)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_186)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_182)begin - case(_zz_183) + if(_zz_187)begin + case(_zz_188) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2636,11 +2631,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_51 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; - assign _zz_52 = (_zz_51 & (~ _zz_221)); + assign _zz_52 = (_zz_51 & (~ _zz_226)); assign _zz_53 = _zz_52[3]; assign _zz_54 = (_zz_52[1] || _zz_53); assign _zz_55 = (_zz_52[2] || _zz_53); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_165; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_170; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -2660,7 +2655,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_223); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_228); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -2751,7 +2746,7 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_65 = _zz_224[11]; + assign _zz_65 = _zz_229[11]; always @ (*) begin _zz_66[18] = _zz_65; _zz_66[17] = _zz_65; @@ -2775,13 +2770,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_225[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_230[31])); if(_zz_71)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_67 = _zz_226[19]; + assign _zz_67 = _zz_231[19]; always @ (*) begin _zz_68[10] = _zz_67; _zz_68[9] = _zz_67; @@ -2796,7 +2791,7 @@ module VexRiscv ( _zz_68[0] = _zz_67; end - assign _zz_69 = _zz_227[11]; + assign _zz_69 = _zz_232[11]; always @ (*) begin _zz_70[18] = _zz_69; _zz_70[17] = _zz_69; @@ -2822,16 +2817,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_71 = _zz_228[1]; + _zz_71 = _zz_233[1]; end default : begin - _zz_71 = _zz_229[1]; + _zz_71 = _zz_234[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_72 = _zz_230[19]; + assign _zz_72 = _zz_235[19]; always @ (*) begin _zz_73[10] = _zz_72; _zz_73[9] = _zz_72; @@ -2846,7 +2841,7 @@ module VexRiscv ( _zz_73[0] = _zz_72; end - assign _zz_74 = _zz_231[11]; + assign _zz_74 = _zz_236[11]; always @ (*) begin _zz_75[18] = _zz_74; _zz_75[17] = _zz_74; @@ -2869,7 +2864,7 @@ module VexRiscv ( _zz_75[0] = _zz_74; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_73,{{{_zz_312,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_75,{{{_zz_313,_zz_314},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_73,{{{_zz_317,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_75,{{{_zz_318,_zz_319},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -2878,52 +2873,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_155 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_156 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_157 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_156; + assign _zz_160 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_161 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_162 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_161; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_159 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_160 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_161 = (CsrPlugin_privilege == 2'b00); + assign _zz_164 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_165 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_166 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_177)begin + if(_zz_182)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_175)begin + if(_zz_180)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_162 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_175)begin - _zz_162 = 1'b1; + _zz_167 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_180)begin + _zz_167 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_176)begin + if(_zz_181)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_174)begin + if(_zz_179)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_176)begin + if(_zz_181)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_174)begin + if(_zz_179)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -2933,7 +2928,7 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_154 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_159 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign _zz_77 = 1'b0; always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; @@ -2986,7 +2981,7 @@ module VexRiscv ( assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_184)begin + if(_zz_189)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end if(memory_ALIGNEMENT_FAULT)begin @@ -2999,18 +2994,18 @@ module VexRiscv ( DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_185)begin + if(_zz_190)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_184)begin + if(_zz_189)begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_232}; + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_237}; end if(! memory_MMU_RSP2_refilling) begin if(memory_MMU_FAULT)begin @@ -3025,7 +3020,7 @@ module VexRiscv ( if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_185)begin + if(_zz_190)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -3099,7 +3094,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_203) + case(_zz_208) 2'b00 : begin writeBack_DBusSimplePlugin_rspFormated = _zz_81; end @@ -3136,7 +3131,7 @@ module VexRiscv ( assign _zz_88 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); assign _zz_89 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); assign _zz_90 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); - assign _zz_84 = {(((decode_INSTRUCTION & _zz_315) == 32'h02004020) != 1'b0),{({_zz_90,_zz_89} != 2'b00),{({_zz_316,_zz_317} != 3'b000),{(_zz_318 != _zz_319),{_zz_320,{_zz_321,_zz_322}}}}}}; + assign _zz_84 = {(((decode_INSTRUCTION & _zz_320) == 32'h02004020) != 1'b0),{({_zz_90,_zz_89} != 2'b00),{({_zz_321,_zz_322} != 3'b000),{(_zz_323 != _zz_324),{_zz_325,{_zz_326,_zz_327}}}}}}; assign _zz_91 = _zz_84[2 : 1]; assign _zz_46 = _zz_91; assign _zz_92 = _zz_84[7 : 6]; @@ -3156,8 +3151,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_163; - assign decode_RegFilePlugin_rs2Data = _zz_164; + assign decode_RegFilePlugin_rs1Data = _zz_168; + assign decode_RegFilePlugin_rs2Data = _zz_169; always @ (*) begin lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); if(_zz_98)begin @@ -3199,7 +3194,7 @@ module VexRiscv ( _zz_99 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_99 = {31'd0, _zz_233}; + _zz_99 = {31'd0, _zz_238}; end default : begin _zz_99 = execute_SRC_ADD_SUB; @@ -3213,18 +3208,18 @@ module VexRiscv ( _zz_100 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_100 = {29'd0, _zz_234}; + _zz_100 = {29'd0, _zz_239}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_100 = {27'd0, _zz_235}; + _zz_100 = {27'd0, _zz_240}; end endcase end - assign _zz_101 = _zz_236[11]; + assign _zz_101 = _zz_241[11]; always @ (*) begin _zz_102[19] = _zz_101; _zz_102[18] = _zz_101; @@ -3248,7 +3243,7 @@ module VexRiscv ( _zz_102[0] = _zz_101; end - assign _zz_103 = _zz_237[11]; + assign _zz_103 = _zz_242[11]; always @ (*) begin _zz_104[19] = _zz_103; _zz_104[18] = _zz_103; @@ -3290,7 +3285,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_238; + execute_SrcPlugin_addSub = _zz_243; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3307,186 +3302,181 @@ module VexRiscv ( _zz_106 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_106 = _zz_245; + _zz_106 = _zz_250; end endcase end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_186)begin - if(_zz_187)begin - if(_zz_107)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_107 = 1'b0; + if(_zz_191)begin + if(_zz_192)begin + if(_zz_112)begin + _zz_107 = 1'b1; end end end - if(_zz_188)begin - if(_zz_189)begin - if(_zz_109)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_193)begin + if(_zz_194)begin + if(_zz_114)begin + _zz_107 = 1'b1; end end end - if(_zz_190)begin - if(_zz_191)begin - if(_zz_111)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_195)begin + if(_zz_196)begin + if(_zz_116)begin + _zz_107 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_107 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_186)begin - if(_zz_187)begin - if(_zz_108)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_108 = 1'b0; + if(_zz_191)begin + if(_zz_192)begin + if(_zz_113)begin + _zz_108 = 1'b1; end end end - if(_zz_188)begin - if(_zz_189)begin - if(_zz_110)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_193)begin + if(_zz_194)begin + if(_zz_115)begin + _zz_108 = 1'b1; end end end - if(_zz_190)begin - if(_zz_191)begin - if(_zz_112)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_195)begin + if(_zz_196)begin + if(_zz_117)begin + _zz_108 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_108 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_38 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_37[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_47; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_107 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_108 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_109 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_110 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_111 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_112 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_112 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_113 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_114 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_115 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_116 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_117 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_113 = execute_INSTRUCTION[14 : 12]; + assign _zz_118 = execute_INSTRUCTION[14 : 12]; always @ (*) begin - if((_zz_113 == 3'b000)) begin - _zz_114 = execute_BranchPlugin_eq; - end else if((_zz_113 == 3'b001)) begin - _zz_114 = (! execute_BranchPlugin_eq); - end else if((((_zz_113 & 3'b101) == 3'b101))) begin - _zz_114 = (! execute_SRC_LESS); + if((_zz_118 == 3'b000)) begin + _zz_119 = execute_BranchPlugin_eq; + end else if((_zz_118 == 3'b001)) begin + _zz_119 = (! execute_BranchPlugin_eq); + end else if((((_zz_118 & 3'b101) == 3'b101))) begin + _zz_119 = (! execute_SRC_LESS); end else begin - _zz_114 = execute_SRC_LESS; + _zz_119 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_115 = 1'b0; + _zz_120 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_115 = 1'b1; + _zz_120 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_115 = 1'b1; + _zz_120 = 1'b1; end default : begin - _zz_115 = _zz_114; + _zz_120 = _zz_119; end endcase end - assign _zz_116 = _zz_247[11]; + assign _zz_121 = _zz_252[11]; always @ (*) begin - _zz_117[19] = _zz_116; - _zz_117[18] = _zz_116; - _zz_117[17] = _zz_116; - _zz_117[16] = _zz_116; - _zz_117[15] = _zz_116; - _zz_117[14] = _zz_116; - _zz_117[13] = _zz_116; - _zz_117[12] = _zz_116; - _zz_117[11] = _zz_116; - _zz_117[10] = _zz_116; - _zz_117[9] = _zz_116; - _zz_117[8] = _zz_116; - _zz_117[7] = _zz_116; - _zz_117[6] = _zz_116; - _zz_117[5] = _zz_116; - _zz_117[4] = _zz_116; - _zz_117[3] = _zz_116; - _zz_117[2] = _zz_116; - _zz_117[1] = _zz_116; - _zz_117[0] = _zz_116; - end - - assign _zz_118 = _zz_248[19]; + _zz_122[19] = _zz_121; + _zz_122[18] = _zz_121; + _zz_122[17] = _zz_121; + _zz_122[16] = _zz_121; + _zz_122[15] = _zz_121; + _zz_122[14] = _zz_121; + _zz_122[13] = _zz_121; + _zz_122[12] = _zz_121; + _zz_122[11] = _zz_121; + _zz_122[10] = _zz_121; + _zz_122[9] = _zz_121; + _zz_122[8] = _zz_121; + _zz_122[7] = _zz_121; + _zz_122[6] = _zz_121; + _zz_122[5] = _zz_121; + _zz_122[4] = _zz_121; + _zz_122[3] = _zz_121; + _zz_122[2] = _zz_121; + _zz_122[1] = _zz_121; + _zz_122[0] = _zz_121; + end + + assign _zz_123 = _zz_253[19]; always @ (*) begin - _zz_119[10] = _zz_118; - _zz_119[9] = _zz_118; - _zz_119[8] = _zz_118; - _zz_119[7] = _zz_118; - _zz_119[6] = _zz_118; - _zz_119[5] = _zz_118; - _zz_119[4] = _zz_118; - _zz_119[3] = _zz_118; - _zz_119[2] = _zz_118; - _zz_119[1] = _zz_118; - _zz_119[0] = _zz_118; - end - - assign _zz_120 = _zz_249[11]; + _zz_124[10] = _zz_123; + _zz_124[9] = _zz_123; + _zz_124[8] = _zz_123; + _zz_124[7] = _zz_123; + _zz_124[6] = _zz_123; + _zz_124[5] = _zz_123; + _zz_124[4] = _zz_123; + _zz_124[3] = _zz_123; + _zz_124[2] = _zz_123; + _zz_124[1] = _zz_123; + _zz_124[0] = _zz_123; + end + + assign _zz_125 = _zz_254[11]; always @ (*) begin - _zz_121[18] = _zz_120; - _zz_121[17] = _zz_120; - _zz_121[16] = _zz_120; - _zz_121[15] = _zz_120; - _zz_121[14] = _zz_120; - _zz_121[13] = _zz_120; - _zz_121[12] = _zz_120; - _zz_121[11] = _zz_120; - _zz_121[10] = _zz_120; - _zz_121[9] = _zz_120; - _zz_121[8] = _zz_120; - _zz_121[7] = _zz_120; - _zz_121[6] = _zz_120; - _zz_121[5] = _zz_120; - _zz_121[4] = _zz_120; - _zz_121[3] = _zz_120; - _zz_121[2] = _zz_120; - _zz_121[1] = _zz_120; - _zz_121[0] = _zz_120; + _zz_126[18] = _zz_125; + _zz_126[17] = _zz_125; + _zz_126[16] = _zz_125; + _zz_126[15] = _zz_125; + _zz_126[14] = _zz_125; + _zz_126[13] = _zz_125; + _zz_126[12] = _zz_125; + _zz_126[11] = _zz_125; + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_122 = (_zz_250[1] ^ execute_RS1[1]); + _zz_127 = (_zz_255[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_122 = _zz_251[1]; + _zz_127 = _zz_256[1]; end default : begin - _zz_122 = _zz_252[1]; + _zz_127 = _zz_257[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_122); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_127); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -3498,80 +3488,80 @@ module VexRiscv ( endcase end - assign _zz_123 = _zz_253[11]; + assign _zz_128 = _zz_258[11]; always @ (*) begin - _zz_124[19] = _zz_123; - _zz_124[18] = _zz_123; - _zz_124[17] = _zz_123; - _zz_124[16] = _zz_123; - _zz_124[15] = _zz_123; - _zz_124[14] = _zz_123; - _zz_124[13] = _zz_123; - _zz_124[12] = _zz_123; - _zz_124[11] = _zz_123; - _zz_124[10] = _zz_123; - _zz_124[9] = _zz_123; - _zz_124[8] = _zz_123; - _zz_124[7] = _zz_123; - _zz_124[6] = _zz_123; - _zz_124[5] = _zz_123; - _zz_124[4] = _zz_123; - _zz_124[3] = _zz_123; - _zz_124[2] = _zz_123; - _zz_124[1] = _zz_123; - _zz_124[0] = _zz_123; + _zz_129[19] = _zz_128; + _zz_129[18] = _zz_128; + _zz_129[17] = _zz_128; + _zz_129[16] = _zz_128; + _zz_129[15] = _zz_128; + _zz_129[14] = _zz_128; + _zz_129[13] = _zz_128; + _zz_129[12] = _zz_128; + _zz_129[11] = _zz_128; + _zz_129[10] = _zz_128; + _zz_129[9] = _zz_128; + _zz_129[8] = _zz_128; + _zz_129[7] = _zz_128; + _zz_129[6] = _zz_128; + _zz_129[5] = _zz_128; + _zz_129[4] = _zz_128; + _zz_129[3] = _zz_128; + _zz_129[2] = _zz_128; + _zz_129[1] = _zz_128; + _zz_129[0] = _zz_128; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_124,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_129,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_126,{{{_zz_466,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_128,{{{_zz_467,_zz_468},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_131,{{{_zz_471,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_133,{{{_zz_472,_zz_473},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_256}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_261}; end end endcase end - assign _zz_125 = _zz_254[19]; + assign _zz_130 = _zz_259[19]; always @ (*) begin - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; - end - - assign _zz_127 = _zz_255[11]; + _zz_131[10] = _zz_130; + _zz_131[9] = _zz_130; + _zz_131[8] = _zz_130; + _zz_131[7] = _zz_130; + _zz_131[6] = _zz_130; + _zz_131[5] = _zz_130; + _zz_131[4] = _zz_130; + _zz_131[3] = _zz_130; + _zz_131[2] = _zz_130; + _zz_131[1] = _zz_130; + _zz_131[0] = _zz_130; + end + + assign _zz_132 = _zz_260[11]; always @ (*) begin - _zz_128[18] = _zz_127; - _zz_128[17] = _zz_127; - _zz_128[16] = _zz_127; - _zz_128[15] = _zz_127; - _zz_128[14] = _zz_127; - _zz_128[13] = _zz_127; - _zz_128[12] = _zz_127; - _zz_128[11] = _zz_127; - _zz_128[10] = _zz_127; - _zz_128[9] = _zz_127; - _zz_128[8] = _zz_127; - _zz_128[7] = _zz_127; - _zz_128[6] = _zz_127; - _zz_128[5] = _zz_127; - _zz_128[4] = _zz_127; - _zz_128[3] = _zz_127; - _zz_128[2] = _zz_127; - _zz_128[1] = _zz_127; - _zz_128[0] = _zz_127; + _zz_133[18] = _zz_132; + _zz_133[17] = _zz_132; + _zz_133[16] = _zz_132; + _zz_133[15] = _zz_132; + _zz_133[14] = _zz_132; + _zz_133[13] = _zz_132; + _zz_133[12] = _zz_132; + _zz_133[11] = _zz_132; + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -3590,18 +3580,18 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_129 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_130 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_131 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_134 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_135 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_136 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_132 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_133 = _zz_257[0]; - assign _zz_134 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_135 = _zz_259[0]; + assign _zz_137 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_138 = _zz_262[0]; + assign _zz_139 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_140 = _zz_264[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_178)begin + if(_zz_183)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3621,7 +3611,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_180)begin + if(_zz_185)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3680,7 +3670,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3729,7 +3719,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_192)begin + if(_zz_197)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3748,14 +3738,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_193)begin + if(_zz_198)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_193)begin + if(_zz_198)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3770,14 +3760,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_192)begin + if(_zz_197)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_192)begin + if(_zz_197)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -3786,7 +3776,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_204) + case(_zz_209) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3800,8 +3790,8 @@ module VexRiscv ( assign memory_MulDivIterativePlugin_frontendOk = 1'b1; always @ (*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_166)begin - if(_zz_179)begin + if(_zz_171)begin + if(_zz_184)begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end @@ -3820,7 +3810,7 @@ module VexRiscv ( if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_262); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_267); end if(memory_MulDivIterativePlugin_mul_counter_willClear)begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; @@ -3829,8 +3819,8 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_167)begin - if(_zz_194)begin + if(_zz_172)begin + if(_zz_199)begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end @@ -3838,7 +3828,7 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_195)begin + if(_zz_200)begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end @@ -3849,28 +3839,28 @@ module VexRiscv ( if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_270); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_275); end if(memory_MulDivIterativePlugin_div_counter_willClear)begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end end - assign _zz_136 = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_136[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_271); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_272 : _zz_273); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_274[31:0]; - assign _zz_137 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_138 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_139 = ((execute_IS_MUL && _zz_138) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_141 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_141[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_276); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_277 : _zz_278); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_279[31:0]; + assign _zz_142 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_143 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_144 = ((execute_IS_MUL && _zz_143) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_140[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_140[31 : 0] = execute_RS1; + _zz_145[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_145[31 : 0] = execute_RS1; end - assign _zz_142 = (_zz_141 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_142 != 32'h0); + assign _zz_147 = (_zz_146 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_147 != 32'h0); assign _zz_24 = decode_SRC1_CTRL; assign _zz_22 = _zz_46; assign _zz_34 = decode_to_execute_SRC1_CTRL; @@ -3917,91 +3907,91 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_143 = 32'h0; + _zz_148 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_143[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_143[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_143[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_148[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_148[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_148[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_144 = 32'h0; + _zz_149 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_144[11 : 11] = CsrPlugin_mip_MEIP; - _zz_144[7 : 7] = CsrPlugin_mip_MTIP; - _zz_144[3 : 3] = CsrPlugin_mip_MSIP; + _zz_149[11 : 11] = CsrPlugin_mip_MEIP; + _zz_149[7 : 7] = CsrPlugin_mip_MTIP; + _zz_149[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_145 = 32'h0; + _zz_150 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_145[11 : 11] = CsrPlugin_mie_MEIE; - _zz_145[7 : 7] = CsrPlugin_mie_MTIE; - _zz_145[3 : 3] = CsrPlugin_mie_MSIE; + _zz_150[11 : 11] = CsrPlugin_mie_MEIE; + _zz_150[7 : 7] = CsrPlugin_mie_MTIE; + _zz_150[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_146 = 32'h0; + _zz_151 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_146[31 : 0] = CsrPlugin_mepc; + _zz_151[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_147 = 32'h0; + _zz_152 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_147[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_147[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_152[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_152[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_148 = 32'h0; + _zz_153 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_148[31 : 0] = CsrPlugin_mtval; + _zz_153[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_149 = 32'h0; + _zz_154 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_149[31 : 0] = _zz_141; + _zz_154[31 : 0] = _zz_146; end end always @ (*) begin - _zz_150 = 32'h0; + _zz_155 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_150[31 : 0] = _zz_142; + _zz_155[31 : 0] = _zz_147; end end - assign execute_CsrPlugin_readData = (((_zz_143 | _zz_144) | (_zz_145 | _zz_146)) | ((_zz_147 | _zz_148) | (_zz_149 | _zz_150))); - assign iBusWishbone_ADR = {_zz_290,_zz_151}; - assign iBusWishbone_CTI = ((_zz_151 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((_zz_148 | _zz_149) | (_zz_150 | _zz_151)) | ((_zz_152 | _zz_153) | (_zz_154 | _zz_155))); + assign iBusWishbone_ADR = {_zz_295,_zz_156}; + assign iBusWishbone_CTI = ((_zz_156 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_196)begin + if(_zz_201)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_196)begin + if(_zz_201)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_152; + assign iBus_rsp_valid = _zz_157; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; @@ -4016,19 +4006,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_153 = 4'b0001; + _zz_158 = 4'b0001; end 2'b01 : begin - _zz_153 = 4'b0011; + _zz_158 = 4'b0011; end default : begin - _zz_153 = 4'b1111; + _zz_158 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_153 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_158 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -4059,7 +4049,7 @@ module VexRiscv ( IBusCachedPlugin_rspCounter <= 32'h0; _zz_98 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_109 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -4078,12 +4068,12 @@ module VexRiscv ( execute_CsrPlugin_wfiWake <= 1'b0; memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - _zz_141 <= 32'h0; + _zz_146 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_151 <= 3'b000; - _zz_152 <= 1'b0; + _zz_156 <= 3'b000; + _zz_157 <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin @@ -4184,8 +4174,8 @@ module VexRiscv ( `endif `endif _zz_98 <= 1'b0; - if(_zz_172)begin - if(_zz_197)begin + if(_zz_177)begin + if(_zz_202)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -4195,7 +4185,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_109 <= (_zz_38 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4217,14 +4207,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_198)begin - if(_zz_199)begin + if(_zz_203)begin + if(_zz_204)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_200)begin + if(_zz_205)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_201)begin + if(_zz_206)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4248,7 +4238,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_181)begin + if(_zz_186)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4259,8 +4249,8 @@ module VexRiscv ( end endcase end - if(_zz_182)begin - case(_zz_183) + if(_zz_187)begin + case(_zz_188) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4270,7 +4260,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_131,{_zz_130,_zz_129}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_136,{_zz_135,_zz_134}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin @@ -4294,29 +4284,29 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_284[0]; - CsrPlugin_mstatus_MIE <= _zz_285[0]; + CsrPlugin_mstatus_MPIE <= _zz_289[0]; + CsrPlugin_mstatus_MIE <= _zz_290[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_287[0]; - CsrPlugin_mie_MTIE <= _zz_288[0]; - CsrPlugin_mie_MSIE <= _zz_289[0]; + CsrPlugin_mie_MEIE <= _zz_292[0]; + CsrPlugin_mie_MTIE <= _zz_293[0]; + CsrPlugin_mie_MSIE <= _zz_294[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_141 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_196)begin + if(_zz_201)begin if(iBusWishbone_ACK)begin - _zz_151 <= (_zz_151 + 3'b001); + _zz_156 <= (_zz_156 + 3'b001); end end - _zz_152 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_202)begin + _zz_157 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_207)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -4336,13 +4326,13 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_172)begin - if(_zz_197)begin + if(_zz_177)begin + if(_zz_202)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_110 <= _zz_37[11 : 7]; + _zz_111 <= _zz_47; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -4350,33 +4340,33 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_178)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_133 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_133 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_183)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_138 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_138 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_180)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_135 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_135 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_185)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_140 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_140 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_198)begin - if(_zz_199)begin + if(_zz_203)begin + if(_zz_204)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_200)begin + if(_zz_205)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_201)begin + if(_zz_206)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_181)begin + if(_zz_186)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4390,10 +4380,10 @@ module VexRiscv ( end endcase end - if(_zz_166)begin - if(_zz_179)begin + if(_zz_171)begin + if(_zz_184)begin memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_263,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_268,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin @@ -4402,20 +4392,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_MulDivIterativePlugin_div_done <= 1'b0; end - if(_zz_167)begin - if(_zz_194)begin + if(_zz_172)begin + if(_zz_199)begin memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_result <= _zz_275[31:0]; + memory_MulDivIterativePlugin_div_result <= _zz_280[31:0]; end end end - if(_zz_195)begin + if(_zz_200)begin memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_139 ? (~ _zz_140) : _zz_140) + _zz_281); - memory_MulDivIterativePlugin_rs2 <= ((_zz_138 ? (~ execute_RS2) : execute_RS2) + _zz_283); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_139 ^ (_zz_138 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_MulDivIterativePlugin_rs1 <= ((_zz_144 ? (~ _zz_145) : _zz_145) + _zz_286); + memory_MulDivIterativePlugin_rs2 <= ((_zz_143 ? (~ execute_RS2) : execute_RS2) + _zz_288); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_144 ^ (_zz_143 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -4620,7 +4610,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_286[0]; + CsrPlugin_mip_MSIP <= _zz_291[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -4635,7 +4625,7 @@ module VexRiscv ( end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_202)begin + if(_zz_207)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v index 87a6a9f..2ec5a6a 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -81,18 +81,18 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_156; - wire _zz_157; - wire _zz_158; - wire _zz_159; - wire _zz_160; wire _zz_161; wire _zz_162; wire _zz_163; - reg _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; + wire _zz_164; + wire _zz_165; + wire _zz_166; + wire _zz_167; + wire _zz_168; + reg _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -105,11 +105,6 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_168; - wire _zz_169; - wire _zz_170; - wire _zz_171; - wire _zz_172; wire _zz_173; wire _zz_174; wire _zz_175; @@ -125,12 +120,12 @@ module VexRiscv ( wire _zz_185; wire _zz_186; wire _zz_187; - wire [1:0] _zz_188; + wire _zz_188; wire _zz_189; wire _zz_190; wire _zz_191; wire _zz_192; - wire _zz_193; + wire [1:0] _zz_193; wire _zz_194; wire _zz_195; wire _zz_196; @@ -138,21 +133,21 @@ module VexRiscv ( wire _zz_198; wire _zz_199; wire _zz_200; - wire [5:0] _zz_201; + wire _zz_201; wire _zz_202; wire _zz_203; wire _zz_204; wire _zz_205; - wire _zz_206; + wire [5:0] _zz_206; wire _zz_207; wire _zz_208; - wire [1:0] _zz_209; + wire _zz_209; wire _zz_210; - wire [0:0] _zz_211; - wire [0:0] _zz_212; - wire [0:0] _zz_213; - wire [0:0] _zz_214; - wire [0:0] _zz_215; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire [1:0] _zz_214; + wire _zz_215; wire [0:0] _zz_216; wire [0:0] _zz_217; wire [0:0] _zz_218; @@ -165,253 +160,258 @@ module VexRiscv ( wire [0:0] _zz_225; wire [0:0] _zz_226; wire [0:0] _zz_227; - wire [3:0] _zz_228; - wire [2:0] _zz_229; - wire [31:0] _zz_230; - wire [11:0] _zz_231; - wire [31:0] _zz_232; - wire [19:0] _zz_233; - wire [11:0] _zz_234; + wire [0:0] _zz_228; + wire [0:0] _zz_229; + wire [0:0] _zz_230; + wire [0:0] _zz_231; + wire [0:0] _zz_232; + wire [3:0] _zz_233; + wire [2:0] _zz_234; wire [31:0] _zz_235; - wire [31:0] _zz_236; - wire [19:0] _zz_237; - wire [11:0] _zz_238; - wire [2:0] _zz_239; - wire [0:0] _zz_240; - wire [2:0] _zz_241; - wire [4:0] _zz_242; + wire [11:0] _zz_236; + wire [31:0] _zz_237; + wire [19:0] _zz_238; + wire [11:0] _zz_239; + wire [31:0] _zz_240; + wire [31:0] _zz_241; + wire [19:0] _zz_242; wire [11:0] _zz_243; - wire [11:0] _zz_244; - wire [31:0] _zz_245; - wire [31:0] _zz_246; - wire [31:0] _zz_247; - wire [31:0] _zz_248; - wire [31:0] _zz_249; + wire [2:0] _zz_244; + wire [0:0] _zz_245; + wire [2:0] _zz_246; + wire [4:0] _zz_247; + wire [11:0] _zz_248; + wire [11:0] _zz_249; wire [31:0] _zz_250; wire [31:0] _zz_251; wire [31:0] _zz_252; - wire [32:0] _zz_253; - wire [11:0] _zz_254; - wire [19:0] _zz_255; - wire [11:0] _zz_256; + wire [31:0] _zz_253; + wire [31:0] _zz_254; + wire [31:0] _zz_255; + wire [31:0] _zz_256; wire [31:0] _zz_257; - wire [31:0] _zz_258; - wire [31:0] _zz_259; - wire [11:0] _zz_260; - wire [19:0] _zz_261; - wire [11:0] _zz_262; - wire [2:0] _zz_263; - wire [1:0] _zz_264; - wire [1:0] _zz_265; - wire [1:0] _zz_266; - wire [1:0] _zz_267; - wire [0:0] _zz_268; - wire [5:0] _zz_269; - wire [33:0] _zz_270; - wire [32:0] _zz_271; - wire [33:0] _zz_272; - wire [32:0] _zz_273; - wire [33:0] _zz_274; - wire [32:0] _zz_275; - wire [0:0] _zz_276; - wire [5:0] _zz_277; + wire [32:0] _zz_258; + wire [11:0] _zz_259; + wire [19:0] _zz_260; + wire [11:0] _zz_261; + wire [31:0] _zz_262; + wire [31:0] _zz_263; + wire [31:0] _zz_264; + wire [11:0] _zz_265; + wire [19:0] _zz_266; + wire [11:0] _zz_267; + wire [2:0] _zz_268; + wire [1:0] _zz_269; + wire [1:0] _zz_270; + wire [1:0] _zz_271; + wire [1:0] _zz_272; + wire [0:0] _zz_273; + wire [5:0] _zz_274; + wire [33:0] _zz_275; + wire [32:0] _zz_276; + wire [33:0] _zz_277; wire [32:0] _zz_278; - wire [31:0] _zz_279; - wire [31:0] _zz_280; - wire [32:0] _zz_281; - wire [32:0] _zz_282; + wire [33:0] _zz_279; + wire [32:0] _zz_280; + wire [0:0] _zz_281; + wire [5:0] _zz_282; wire [32:0] _zz_283; - wire [32:0] _zz_284; - wire [0:0] _zz_285; + wire [31:0] _zz_284; + wire [31:0] _zz_285; wire [32:0] _zz_286; - wire [0:0] _zz_287; + wire [32:0] _zz_287; wire [32:0] _zz_288; - wire [0:0] _zz_289; - wire [31:0] _zz_290; - wire [0:0] _zz_291; + wire [32:0] _zz_289; + wire [0:0] _zz_290; + wire [32:0] _zz_291; wire [0:0] _zz_292; - wire [0:0] _zz_293; + wire [32:0] _zz_293; wire [0:0] _zz_294; - wire [0:0] _zz_295; + wire [31:0] _zz_295; wire [0:0] _zz_296; - wire [26:0] _zz_297; - wire _zz_298; - wire _zz_299; - wire [1:0] _zz_300; - wire [31:0] _zz_301; - wire [31:0] _zz_302; - wire [31:0] _zz_303; + wire [0:0] _zz_297; + wire [0:0] _zz_298; + wire [0:0] _zz_299; + wire [0:0] _zz_300; + wire [0:0] _zz_301; + wire [26:0] _zz_302; + wire _zz_303; wire _zz_304; - wire [0:0] _zz_305; - wire [12:0] _zz_306; + wire [1:0] _zz_305; + wire [31:0] _zz_306; wire [31:0] _zz_307; wire [31:0] _zz_308; - wire [31:0] _zz_309; - wire _zz_310; - wire [0:0] _zz_311; - wire [6:0] _zz_312; + wire _zz_309; + wire [0:0] _zz_310; + wire [12:0] _zz_311; + wire [31:0] _zz_312; wire [31:0] _zz_313; wire [31:0] _zz_314; - wire [31:0] _zz_315; - wire _zz_316; - wire [0:0] _zz_317; - wire [0:0] _zz_318; - wire _zz_319; - wire _zz_320; + wire _zz_315; + wire [0:0] _zz_316; + wire [6:0] _zz_317; + wire [31:0] _zz_318; + wire [31:0] _zz_319; + wire [31:0] _zz_320; wire _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [0:0] _zz_325; - wire [0:0] _zz_326; - wire [2:0] _zz_327; - wire [2:0] _zz_328; - wire _zz_329; + wire [0:0] _zz_322; + wire [0:0] _zz_323; + wire _zz_324; + wire _zz_325; + wire _zz_326; + wire [31:0] _zz_327; + wire [31:0] _zz_328; + wire [31:0] _zz_329; wire [0:0] _zz_330; - wire [25:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [31:0] _zz_334; - wire _zz_335; - wire [1:0] _zz_336; - wire [1:0] _zz_337; - wire _zz_338; - wire [0:0] _zz_339; - wire [21:0] _zz_340; - wire [31:0] _zz_341; - wire [31:0] _zz_342; - wire [31:0] _zz_343; - wire [31:0] _zz_344; - wire _zz_345; - wire _zz_346; - wire [1:0] _zz_347; - wire [1:0] _zz_348; - wire _zz_349; - wire [0:0] _zz_350; - wire [18:0] _zz_351; - wire [31:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire [31:0] _zz_355; - wire _zz_356; - wire [0:0] _zz_357; - wire [0:0] _zz_358; - wire [0:0] _zz_359; - wire [1:0] _zz_360; - wire [0:0] _zz_361; + wire [0:0] _zz_331; + wire [2:0] _zz_332; + wire [2:0] _zz_333; + wire _zz_334; + wire [0:0] _zz_335; + wire [25:0] _zz_336; + wire [31:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire _zz_340; + wire [1:0] _zz_341; + wire [1:0] _zz_342; + wire _zz_343; + wire [0:0] _zz_344; + wire [21:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; + wire [31:0] _zz_349; + wire _zz_350; + wire _zz_351; + wire [1:0] _zz_352; + wire [1:0] _zz_353; + wire _zz_354; + wire [0:0] _zz_355; + wire [18:0] _zz_356; + wire [31:0] _zz_357; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire [31:0] _zz_360; + wire _zz_361; wire [0:0] _zz_362; - wire _zz_363; + wire [0:0] _zz_363; wire [0:0] _zz_364; - wire [15:0] _zz_365; - wire [31:0] _zz_366; - wire [31:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; - wire [31:0] _zz_370; + wire [1:0] _zz_365; + wire [0:0] _zz_366; + wire [0:0] _zz_367; + wire _zz_368; + wire [0:0] _zz_369; + wire [15:0] _zz_370; wire [31:0] _zz_371; wire [31:0] _zz_372; - wire _zz_373; - wire _zz_374; + wire [31:0] _zz_373; + wire [31:0] _zz_374; wire [31:0] _zz_375; wire [31:0] _zz_376; - wire [1:0] _zz_377; - wire [1:0] _zz_378; + wire [31:0] _zz_377; + wire _zz_378; wire _zz_379; - wire [0:0] _zz_380; - wire [13:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire [31:0] _zz_384; - wire [31:0] _zz_385; - wire _zz_386; - wire _zz_387; - wire [0:0] _zz_388; - wire [1:0] _zz_389; - wire [0:0] _zz_390; - wire [0:0] _zz_391; + wire [31:0] _zz_380; + wire [31:0] _zz_381; + wire [1:0] _zz_382; + wire [1:0] _zz_383; + wire _zz_384; + wire [0:0] _zz_385; + wire [13:0] _zz_386; + wire [31:0] _zz_387; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire _zz_391; wire _zz_392; wire [0:0] _zz_393; - wire [10:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire [31:0] _zz_399; + wire [1:0] _zz_394; + wire [0:0] _zz_395; + wire [0:0] _zz_396; + wire _zz_397; + wire [0:0] _zz_398; + wire [10:0] _zz_399; wire [31:0] _zz_400; wire [31:0] _zz_401; wire [31:0] _zz_402; - wire [0:0] _zz_403; - wire [1:0] _zz_404; - wire [5:0] _zz_405; - wire [5:0] _zz_406; - wire _zz_407; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire [31:0] _zz_405; + wire [31:0] _zz_406; + wire [31:0] _zz_407; wire [0:0] _zz_408; - wire [7:0] _zz_409; - wire [31:0] _zz_410; - wire [31:0] _zz_411; - wire [31:0] _zz_412; - wire [31:0] _zz_413; - wire _zz_414; - wire [0:0] _zz_415; - wire [2:0] _zz_416; - wire _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire [1:0] _zz_420; - wire [1:0] _zz_421; + wire [1:0] _zz_409; + wire [5:0] _zz_410; + wire [5:0] _zz_411; + wire _zz_412; + wire [0:0] _zz_413; + wire [7:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire [31:0] _zz_418; + wire _zz_419; + wire [0:0] _zz_420; + wire [2:0] _zz_421; wire _zz_422; wire [0:0] _zz_423; - wire [4:0] _zz_424; - wire [31:0] _zz_425; - wire [31:0] _zz_426; - wire [31:0] _zz_427; - wire _zz_428; - wire [0:0] _zz_429; - wire [0:0] _zz_430; + wire [0:0] _zz_424; + wire [1:0] _zz_425; + wire [1:0] _zz_426; + wire _zz_427; + wire [0:0] _zz_428; + wire [4:0] _zz_429; + wire [31:0] _zz_430; wire [31:0] _zz_431; wire [31:0] _zz_432; - wire [31:0] _zz_433; - wire _zz_434; - wire _zz_435; - wire _zz_436; - wire [3:0] _zz_437; - wire [3:0] _zz_438; + wire _zz_433; + wire [0:0] _zz_434; + wire [0:0] _zz_435; + wire [31:0] _zz_436; + wire [31:0] _zz_437; + wire [31:0] _zz_438; wire _zz_439; - wire [0:0] _zz_440; - wire [2:0] _zz_441; - wire [31:0] _zz_442; - wire [31:0] _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire [31:0] _zz_446; + wire _zz_440; + wire _zz_441; + wire [3:0] _zz_442; + wire [3:0] _zz_443; + wire _zz_444; + wire [0:0] _zz_445; + wire [2:0] _zz_446; wire [31:0] _zz_447; wire [31:0] _zz_448; wire [31:0] _zz_449; - wire _zz_450; - wire [0:0] _zz_451; - wire [1:0] _zz_452; - wire _zz_453; - wire [2:0] _zz_454; - wire [2:0] _zz_455; - wire _zz_456; - wire [0:0] _zz_457; - wire [0:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire [31:0] _zz_462; - wire [31:0] _zz_463; + wire [31:0] _zz_450; + wire [31:0] _zz_451; + wire [31:0] _zz_452; + wire [31:0] _zz_453; + wire [31:0] _zz_454; + wire _zz_455; + wire [0:0] _zz_456; + wire [1:0] _zz_457; + wire _zz_458; + wire [2:0] _zz_459; + wire [2:0] _zz_460; + wire _zz_461; + wire [0:0] _zz_462; + wire [0:0] _zz_463; wire [31:0] _zz_464; wire [31:0] _zz_465; - wire _zz_466; - wire _zz_467; - wire _zz_468; - wire [0:0] _zz_469; - wire [0:0] _zz_470; + wire [31:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; wire _zz_471; wire _zz_472; wire _zz_473; - wire _zz_474; + wire [0:0] _zz_474; + wire [0:0] _zz_475; + wire _zz_476; + wire _zz_477; + wire _zz_478; + wire _zz_479; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -863,42 +863,37 @@ module VexRiscv ( wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; reg [31:0] _zz_106; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire _zz_107; - wire _zz_108; - wire _zz_109; - wire _zz_110; - wire _zz_111; + reg _zz_107; + reg _zz_108; + reg _zz_109; + reg [4:0] _zz_110; + reg [31:0] _zz_111; wire _zz_112; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_113; - reg _zz_114; - reg _zz_115; + wire _zz_113; + wire _zz_114; + wire _zz_115; wire _zz_116; - reg [19:0] _zz_117; - wire _zz_118; - reg [10:0] _zz_119; - wire _zz_120; - reg [18:0] _zz_121; - reg _zz_122; + wire _zz_117; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_118; + reg _zz_119; + reg _zz_120; + wire _zz_121; + reg [19:0] _zz_122; + wire _zz_123; + reg [10:0] _zz_124; + wire _zz_125; + reg [18:0] _zz_126; + reg _zz_127; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_123; - reg [19:0] _zz_124; - wire _zz_125; - reg [10:0] _zz_126; - wire _zz_127; - reg [18:0] _zz_128; + wire _zz_128; + reg [19:0] _zz_129; + wire _zz_130; + reg [10:0] _zz_131; + wire _zz_132; + reg [18:0] _zz_133; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; @@ -919,9 +914,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_129; - wire _zz_130; - wire _zz_131; + wire _zz_134; + wire _zz_135; + wire _zz_136; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -934,10 +929,10 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_132; - wire _zz_133; - wire [1:0] _zz_134; - wire _zz_135; + wire [1:0] _zz_137; + wire _zz_138; + wire [1:0] _zz_139; + wire _zz_140; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -985,18 +980,18 @@ module VexRiscv ( wire memory_MulDivIterativePlugin_div_counter_willOverflow; reg memory_MulDivIterativePlugin_div_done; reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_136; + wire [31:0] _zz_141; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [31:0] _zz_137; - wire _zz_138; - wire _zz_139; - reg [32:0] _zz_140; - reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_141; wire [31:0] _zz_142; + wire _zz_143; + wire _zz_144; + reg [32:0] _zz_145; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_146; + wire [31:0] _zz_147; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1006,7 +1001,7 @@ module VexRiscv ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_143; + reg _zz_148; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1073,7 +1068,7 @@ module VexRiscv ( reg execute_to_memory_BRANCH_DO; reg [31:0] execute_to_memory_BRANCH_CALC; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg [2:0] _zz_144; + reg [2:0] _zz_149; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_836; reg execute_CsrPlugin_csr_772; @@ -1083,16 +1078,16 @@ module VexRiscv ( reg execute_CsrPlugin_csr_835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_145; - reg [31:0] _zz_146; - reg [31:0] _zz_147; - reg [31:0] _zz_148; - reg [31:0] _zz_149; reg [31:0] _zz_150; reg [31:0] _zz_151; reg [31:0] _zz_152; - reg [2:0] _zz_153; - reg _zz_154; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [2:0] _zz_158; + reg _zz_159; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -1106,7 +1101,7 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_155; + reg [3:0] _zz_160; `ifndef SYNTHESIS reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; @@ -1185,322 +1180,322 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_168 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_169 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_170 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_171 = 1'b1; - assign _zz_172 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_173 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_174 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_175 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_176 = ((_zz_161 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_177 = ((_zz_161 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_178 = ((_zz_161 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_179 = ((_zz_161 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_180 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_181 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_182 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_183 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_184 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_185 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_186 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_187 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_188 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_189 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_190 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_191 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_192 = (1'b0 || (! 1'b1)); - assign _zz_193 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_194 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_195 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_196 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_197 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_198 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_199 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_200 = (! memory_arbitration_isStuck); - assign _zz_201 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_202 = (iBus_cmd_valid || (_zz_153 != 3'b000)); - assign _zz_203 = (! execute_arbitration_isStuckByOthers); - assign _zz_204 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_205 = ((_zz_129 && 1'b1) && (! 1'b0)); - assign _zz_206 = ((_zz_130 && 1'b1) && (! 1'b0)); - assign _zz_207 = ((_zz_131 && 1'b1) && (! 1'b0)); - assign _zz_208 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_209 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_210 = execute_INSTRUCTION[13]; - assign _zz_211 = _zz_84[30 : 30]; - assign _zz_212 = _zz_84[29 : 29]; - assign _zz_213 = _zz_84[28 : 28]; - assign _zz_214 = _zz_84[27 : 27]; - assign _zz_215 = _zz_84[24 : 24]; - assign _zz_216 = _zz_84[16 : 16]; - assign _zz_217 = _zz_84[13 : 13]; - assign _zz_218 = _zz_84[12 : 12]; - assign _zz_219 = _zz_84[11 : 11]; - assign _zz_220 = _zz_84[31 : 31]; - assign _zz_221 = _zz_84[15 : 15]; - assign _zz_222 = _zz_84[5 : 5]; - assign _zz_223 = _zz_84[3 : 3]; - assign _zz_224 = _zz_84[19 : 19]; - assign _zz_225 = _zz_84[10 : 10]; - assign _zz_226 = _zz_84[4 : 4]; - assign _zz_227 = _zz_84[0 : 0]; - assign _zz_228 = (_zz_51 - 4'b0001); - assign _zz_229 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_230 = {29'd0, _zz_229}; - assign _zz_231 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_232 = {{_zz_66,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_233 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_234 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_235 = {{_zz_68,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_236 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_237 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_238 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_239 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_240 = execute_SRC_LESS; - assign _zz_241 = 3'b100; - assign _zz_242 = execute_INSTRUCTION[19 : 15]; - assign _zz_243 = execute_INSTRUCTION[31 : 20]; - assign _zz_244 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_245 = ($signed(_zz_246) + $signed(_zz_249)); - assign _zz_246 = ($signed(_zz_247) + $signed(_zz_248)); - assign _zz_247 = execute_SRC1; - assign _zz_248 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_249 = (execute_SRC_USE_SUB_LESS ? _zz_250 : _zz_251); - assign _zz_250 = 32'h00000001; - assign _zz_251 = 32'h0; - assign _zz_252 = (_zz_253 >>> 1); - assign _zz_253 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_254 = execute_INSTRUCTION[31 : 20]; - assign _zz_255 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_256 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_257 = {_zz_117,execute_INSTRUCTION[31 : 20]}; - assign _zz_258 = {{_zz_119,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_259 = {{_zz_121,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_260 = execute_INSTRUCTION[31 : 20]; - assign _zz_261 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_262 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_263 = 3'b100; - assign _zz_264 = (_zz_132 & (~ _zz_265)); - assign _zz_265 = (_zz_132 - 2'b01); - assign _zz_266 = (_zz_134 & (~ _zz_267)); - assign _zz_267 = (_zz_134 - 2'b01); - assign _zz_268 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_269 = {5'd0, _zz_268}; - assign _zz_270 = (_zz_272 + _zz_274); - assign _zz_271 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_272 = {{1{_zz_271[32]}}, _zz_271}; - assign _zz_273 = _zz_275; - assign _zz_274 = {{1{_zz_273[32]}}, _zz_273}; - assign _zz_275 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_276 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_277 = {5'd0, _zz_276}; - assign _zz_278 = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_279 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_280 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_281 = {_zz_136,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_282 = _zz_283; - assign _zz_283 = _zz_284; - assign _zz_284 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_137) : _zz_137)} + _zz_286); - assign _zz_285 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_286 = {32'd0, _zz_285}; - assign _zz_287 = _zz_139; - assign _zz_288 = {32'd0, _zz_287}; - assign _zz_289 = _zz_138; - assign _zz_290 = {31'd0, _zz_289}; - assign _zz_291 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_292 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_293 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_294 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_295 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_296 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_297 = (iBus_cmd_payload_address >>> 5); - assign _zz_298 = 1'b1; - assign _zz_299 = 1'b1; - assign _zz_300 = {_zz_55,_zz_54}; - assign _zz_301 = 32'h0000107f; - assign _zz_302 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_303 = 32'h00002073; - assign _zz_304 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_305 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_306 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_307) == 32'h00000003),{(_zz_308 == _zz_309),{_zz_310,{_zz_311,_zz_312}}}}}}; - assign _zz_307 = 32'h0000505f; - assign _zz_308 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_309 = 32'h00000063; - assign _zz_310 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_311 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_312 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_313) == 32'h00005033),{(_zz_314 == _zz_315),{_zz_316,{_zz_317,_zz_318}}}}}}; - assign _zz_313 = 32'hbe00707f; - assign _zz_314 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_315 = 32'h00000033; - assign _zz_316 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_317 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); - assign _zz_318 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_319 = decode_INSTRUCTION[31]; - assign _zz_320 = decode_INSTRUCTION[31]; - assign _zz_321 = decode_INSTRUCTION[7]; - assign _zz_322 = 32'h10103050; - assign _zz_323 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_324 = 32'h02004020; - assign _zz_325 = _zz_90; - assign _zz_326 = _zz_89; - assign _zz_327 = {_zz_90,{_zz_88,_zz_89}}; - assign _zz_328 = 3'b000; - assign _zz_329 = (((decode_INSTRUCTION & _zz_332) == 32'h02000030) != 1'b0); - assign _zz_330 = ((_zz_333 == _zz_334) != 1'b0); - assign _zz_331 = {(_zz_335 != 1'b0),{(_zz_336 != _zz_337),{_zz_338,{_zz_339,_zz_340}}}}; - assign _zz_332 = 32'h02004074; - assign _zz_333 = (decode_INSTRUCTION & 32'h10103050); - assign _zz_334 = 32'h00000050; - assign _zz_335 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); - assign _zz_336 = {(_zz_341 == _zz_342),(_zz_343 == _zz_344)}; - assign _zz_337 = 2'b00; - assign _zz_338 = ({_zz_87,_zz_345} != 2'b00); - assign _zz_339 = (_zz_346 != 1'b0); - assign _zz_340 = {(_zz_347 != _zz_348),{_zz_349,{_zz_350,_zz_351}}}; - assign _zz_341 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_342 = 32'h00001050; - assign _zz_343 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_344 = 32'h00002050; - assign _zz_345 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_346 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_347 = {(_zz_352 == _zz_353),(_zz_354 == _zz_355)}; - assign _zz_348 = 2'b00; - assign _zz_349 = ({_zz_356,{_zz_357,_zz_358}} != 3'b000); - assign _zz_350 = ({_zz_359,_zz_360} != 3'b000); - assign _zz_351 = {(_zz_361 != _zz_362),{_zz_363,{_zz_364,_zz_365}}}; - assign _zz_352 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_353 = 32'h00005010; - assign _zz_354 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_355 = 32'h00005020; - assign _zz_356 = ((decode_INSTRUCTION & _zz_366) == 32'h40001010); - assign _zz_357 = (_zz_367 == _zz_368); - assign _zz_358 = (_zz_369 == _zz_370); - assign _zz_359 = (_zz_371 == _zz_372); - assign _zz_360 = {_zz_373,_zz_374}; - assign _zz_361 = (_zz_375 == _zz_376); - assign _zz_362 = 1'b0; - assign _zz_363 = (_zz_88 != 1'b0); - assign _zz_364 = (_zz_377 != _zz_378); - assign _zz_365 = {_zz_379,{_zz_380,_zz_381}}; - assign _zz_366 = 32'h40003054; - assign _zz_367 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_368 = 32'h00001010; - assign _zz_369 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_370 = 32'h00001010; - assign _zz_371 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_372 = 32'h00000024; - assign _zz_373 = ((decode_INSTRUCTION & 32'h00003034) == 32'h00001010); - assign _zz_374 = ((decode_INSTRUCTION & 32'h02003054) == 32'h00001010); - assign _zz_375 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_376 = 32'h00001000; - assign _zz_377 = {(_zz_382 == _zz_383),(_zz_384 == _zz_385)}; - assign _zz_378 = 2'b00; - assign _zz_379 = ({_zz_386,_zz_387} != 2'b00); - assign _zz_380 = ({_zz_388,_zz_389} != 3'b000); - assign _zz_381 = {(_zz_390 != _zz_391),{_zz_392,{_zz_393,_zz_394}}}; - assign _zz_382 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_383 = 32'h00002000; - assign _zz_384 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_385 = 32'h00001000; - assign _zz_386 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); - assign _zz_387 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_388 = ((decode_INSTRUCTION & _zz_395) == 32'h00000040); - assign _zz_389 = {(_zz_396 == _zz_397),(_zz_398 == _zz_399)}; - assign _zz_390 = ((decode_INSTRUCTION & _zz_400) == 32'h00000020); - assign _zz_391 = 1'b0; - assign _zz_392 = ((_zz_401 == _zz_402) != 1'b0); - assign _zz_393 = ({_zz_403,_zz_404} != 3'b000); - assign _zz_394 = {(_zz_405 != _zz_406),{_zz_407,{_zz_408,_zz_409}}}; - assign _zz_395 = 32'h00000050; - assign _zz_396 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_397 = 32'h0; - assign _zz_398 = (decode_INSTRUCTION & 32'h00103040); - assign _zz_399 = 32'h00000040; - assign _zz_400 = 32'h00000020; - assign _zz_401 = (decode_INSTRUCTION & 32'h00000010); - assign _zz_402 = 32'h00000010; - assign _zz_403 = _zz_86; - assign _zz_404 = {(_zz_410 == _zz_411),(_zz_412 == _zz_413)}; - assign _zz_405 = {_zz_87,{_zz_414,{_zz_415,_zz_416}}}; - assign _zz_406 = 6'h0; - assign _zz_407 = ({_zz_86,_zz_417} != 2'b00); - assign _zz_408 = ({_zz_418,_zz_419} != 2'b00); - assign _zz_409 = {(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}; - assign _zz_410 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_411 = 32'h00000010; - assign _zz_412 = (decode_INSTRUCTION & 32'h02000060); - assign _zz_413 = 32'h00000020; - assign _zz_414 = ((decode_INSTRUCTION & _zz_425) == 32'h00001010); - assign _zz_415 = (_zz_426 == _zz_427); - assign _zz_416 = {_zz_428,{_zz_429,_zz_430}}; - assign _zz_417 = ((decode_INSTRUCTION & _zz_431) == 32'h00000020); - assign _zz_418 = _zz_86; - assign _zz_419 = (_zz_432 == _zz_433); - assign _zz_420 = {_zz_434,_zz_435}; - assign _zz_421 = 2'b00; - assign _zz_422 = (_zz_436 != 1'b0); - assign _zz_423 = (_zz_437 != _zz_438); - assign _zz_424 = {_zz_439,{_zz_440,_zz_441}}; - assign _zz_425 = 32'h00001010; - assign _zz_426 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_427 = 32'h00002010; - assign _zz_428 = ((decode_INSTRUCTION & _zz_442) == 32'h00000010); - assign _zz_429 = (_zz_443 == _zz_444); - assign _zz_430 = (_zz_445 == _zz_446); - assign _zz_431 = 32'h00000070; - assign _zz_432 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_433 = 32'h0; - assign _zz_434 = ((decode_INSTRUCTION & _zz_447) == 32'h00006010); - assign _zz_435 = ((decode_INSTRUCTION & _zz_448) == 32'h00004010); - assign _zz_436 = ((decode_INSTRUCTION & _zz_449) == 32'h00002010); - assign _zz_437 = {_zz_450,{_zz_451,_zz_452}}; - assign _zz_438 = 4'b0000; - assign _zz_439 = (_zz_453 != 1'b0); - assign _zz_440 = (_zz_454 != _zz_455); - assign _zz_441 = {_zz_456,{_zz_457,_zz_458}}; - assign _zz_442 = 32'h00000050; - assign _zz_443 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_444 = 32'h00000004; - assign _zz_445 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_446 = 32'h0; - assign _zz_447 = 32'h00006014; - assign _zz_448 = 32'h00005014; - assign _zz_449 = 32'h00006014; - assign _zz_450 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_451 = ((decode_INSTRUCTION & _zz_459) == 32'h0); - assign _zz_452 = {(_zz_460 == _zz_461),(_zz_462 == _zz_463)}; - assign _zz_453 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_454 = {(_zz_464 == _zz_465),{_zz_466,_zz_467}}; - assign _zz_455 = 3'b000; - assign _zz_456 = ({_zz_468,_zz_85} != 2'b00); - assign _zz_457 = ({_zz_469,_zz_470} != 2'b00); - assign _zz_458 = (_zz_471 != 1'b0); - assign _zz_459 = 32'h00000018; - assign _zz_460 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_461 = 32'h00002000; - assign _zz_462 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_463 = 32'h00001000; - assign _zz_464 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_465 = 32'h00000040; - assign _zz_466 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_467 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz_468 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_469 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_470 = _zz_85; - assign _zz_471 = ((decode_INSTRUCTION & 32'h00001048) == 32'h00001008); - assign _zz_472 = execute_INSTRUCTION[31]; - assign _zz_473 = execute_INSTRUCTION[31]; - assign _zz_474 = execute_INSTRUCTION[7]; + assign _zz_173 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_174 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_175 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_176 = 1'b1; + assign _zz_177 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_178 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_179 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_180 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_181 = ((_zz_166 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_182 = ((_zz_166 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_183 = ((_zz_166 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_184 = ((_zz_166 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_185 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_186 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_187 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_188 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_189 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_190 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_191 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_192 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_193 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_194 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_195 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_196 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_197 = (1'b0 || (! 1'b1)); + assign _zz_198 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_199 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_200 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_201 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_202 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_203 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_204 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_205 = (! memory_arbitration_isStuck); + assign _zz_206 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_207 = (iBus_cmd_valid || (_zz_158 != 3'b000)); + assign _zz_208 = (! execute_arbitration_isStuckByOthers); + assign _zz_209 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_210 = ((_zz_134 && 1'b1) && (! 1'b0)); + assign _zz_211 = ((_zz_135 && 1'b1) && (! 1'b0)); + assign _zz_212 = ((_zz_136 && 1'b1) && (! 1'b0)); + assign _zz_213 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_214 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_215 = execute_INSTRUCTION[13]; + assign _zz_216 = _zz_84[30 : 30]; + assign _zz_217 = _zz_84[29 : 29]; + assign _zz_218 = _zz_84[28 : 28]; + assign _zz_219 = _zz_84[27 : 27]; + assign _zz_220 = _zz_84[24 : 24]; + assign _zz_221 = _zz_84[16 : 16]; + assign _zz_222 = _zz_84[13 : 13]; + assign _zz_223 = _zz_84[12 : 12]; + assign _zz_224 = _zz_84[11 : 11]; + assign _zz_225 = _zz_84[31 : 31]; + assign _zz_226 = _zz_84[15 : 15]; + assign _zz_227 = _zz_84[5 : 5]; + assign _zz_228 = _zz_84[3 : 3]; + assign _zz_229 = _zz_84[19 : 19]; + assign _zz_230 = _zz_84[10 : 10]; + assign _zz_231 = _zz_84[4 : 4]; + assign _zz_232 = _zz_84[0 : 0]; + assign _zz_233 = (_zz_51 - 4'b0001); + assign _zz_234 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_235 = {29'd0, _zz_234}; + assign _zz_236 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_237 = {{_zz_66,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_238 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_239 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_240 = {{_zz_68,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_241 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_242 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_243 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_244 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_245 = execute_SRC_LESS; + assign _zz_246 = 3'b100; + assign _zz_247 = execute_INSTRUCTION[19 : 15]; + assign _zz_248 = execute_INSTRUCTION[31 : 20]; + assign _zz_249 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_250 = ($signed(_zz_251) + $signed(_zz_254)); + assign _zz_251 = ($signed(_zz_252) + $signed(_zz_253)); + assign _zz_252 = execute_SRC1; + assign _zz_253 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_254 = (execute_SRC_USE_SUB_LESS ? _zz_255 : _zz_256); + assign _zz_255 = 32'h00000001; + assign _zz_256 = 32'h0; + assign _zz_257 = (_zz_258 >>> 1); + assign _zz_258 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_259 = execute_INSTRUCTION[31 : 20]; + assign _zz_260 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_261 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_262 = {_zz_122,execute_INSTRUCTION[31 : 20]}; + assign _zz_263 = {{_zz_124,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_264 = {{_zz_126,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_265 = execute_INSTRUCTION[31 : 20]; + assign _zz_266 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_267 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_268 = 3'b100; + assign _zz_269 = (_zz_137 & (~ _zz_270)); + assign _zz_270 = (_zz_137 - 2'b01); + assign _zz_271 = (_zz_139 & (~ _zz_272)); + assign _zz_272 = (_zz_139 - 2'b01); + assign _zz_273 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_274 = {5'd0, _zz_273}; + assign _zz_275 = (_zz_277 + _zz_279); + assign _zz_276 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_277 = {{1{_zz_276[32]}}, _zz_276}; + assign _zz_278 = _zz_280; + assign _zz_279 = {{1{_zz_278[32]}}, _zz_278}; + assign _zz_280 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_281 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_282 = {5'd0, _zz_281}; + assign _zz_283 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_284 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_285 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_286 = {_zz_141,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_287 = _zz_288; + assign _zz_288 = _zz_289; + assign _zz_289 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_142) : _zz_142)} + _zz_291); + assign _zz_290 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_291 = {32'd0, _zz_290}; + assign _zz_292 = _zz_144; + assign _zz_293 = {32'd0, _zz_292}; + assign _zz_294 = _zz_143; + assign _zz_295 = {31'd0, _zz_294}; + assign _zz_296 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_297 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_298 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_299 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_300 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_301 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_302 = (iBus_cmd_payload_address >>> 5); + assign _zz_303 = 1'b1; + assign _zz_304 = 1'b1; + assign _zz_305 = {_zz_55,_zz_54}; + assign _zz_306 = 32'h0000107f; + assign _zz_307 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_308 = 32'h00002073; + assign _zz_309 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_310 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_311 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_312) == 32'h00000003),{(_zz_313 == _zz_314),{_zz_315,{_zz_316,_zz_317}}}}}}; + assign _zz_312 = 32'h0000505f; + assign _zz_313 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_314 = 32'h00000063; + assign _zz_315 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_316 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_317 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_318) == 32'h00005033),{(_zz_319 == _zz_320),{_zz_321,{_zz_322,_zz_323}}}}}}; + assign _zz_318 = 32'hbe00707f; + assign _zz_319 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_320 = 32'h00000033; + assign _zz_321 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_322 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_323 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_324 = decode_INSTRUCTION[31]; + assign _zz_325 = decode_INSTRUCTION[31]; + assign _zz_326 = decode_INSTRUCTION[7]; + assign _zz_327 = 32'h10103050; + assign _zz_328 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_329 = 32'h02004020; + assign _zz_330 = _zz_90; + assign _zz_331 = _zz_89; + assign _zz_332 = {_zz_90,{_zz_88,_zz_89}}; + assign _zz_333 = 3'b000; + assign _zz_334 = (((decode_INSTRUCTION & _zz_337) == 32'h02000030) != 1'b0); + assign _zz_335 = ((_zz_338 == _zz_339) != 1'b0); + assign _zz_336 = {(_zz_340 != 1'b0),{(_zz_341 != _zz_342),{_zz_343,{_zz_344,_zz_345}}}}; + assign _zz_337 = 32'h02004074; + assign _zz_338 = (decode_INSTRUCTION & 32'h10103050); + assign _zz_339 = 32'h00000050; + assign _zz_340 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz_341 = {(_zz_346 == _zz_347),(_zz_348 == _zz_349)}; + assign _zz_342 = 2'b00; + assign _zz_343 = ({_zz_87,_zz_350} != 2'b00); + assign _zz_344 = (_zz_351 != 1'b0); + assign _zz_345 = {(_zz_352 != _zz_353),{_zz_354,{_zz_355,_zz_356}}}; + assign _zz_346 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_347 = 32'h00001050; + assign _zz_348 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_349 = 32'h00002050; + assign _zz_350 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_351 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_352 = {(_zz_357 == _zz_358),(_zz_359 == _zz_360)}; + assign _zz_353 = 2'b00; + assign _zz_354 = ({_zz_361,{_zz_362,_zz_363}} != 3'b000); + assign _zz_355 = ({_zz_364,_zz_365} != 3'b000); + assign _zz_356 = {(_zz_366 != _zz_367),{_zz_368,{_zz_369,_zz_370}}}; + assign _zz_357 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_358 = 32'h00005010; + assign _zz_359 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_360 = 32'h00005020; + assign _zz_361 = ((decode_INSTRUCTION & _zz_371) == 32'h40001010); + assign _zz_362 = (_zz_372 == _zz_373); + assign _zz_363 = (_zz_374 == _zz_375); + assign _zz_364 = (_zz_376 == _zz_377); + assign _zz_365 = {_zz_378,_zz_379}; + assign _zz_366 = (_zz_380 == _zz_381); + assign _zz_367 = 1'b0; + assign _zz_368 = (_zz_88 != 1'b0); + assign _zz_369 = (_zz_382 != _zz_383); + assign _zz_370 = {_zz_384,{_zz_385,_zz_386}}; + assign _zz_371 = 32'h40003054; + assign _zz_372 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_373 = 32'h00001010; + assign _zz_374 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_375 = 32'h00001010; + assign _zz_376 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_377 = 32'h00000024; + assign _zz_378 = ((decode_INSTRUCTION & 32'h00003034) == 32'h00001010); + assign _zz_379 = ((decode_INSTRUCTION & 32'h02003054) == 32'h00001010); + assign _zz_380 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_381 = 32'h00001000; + assign _zz_382 = {(_zz_387 == _zz_388),(_zz_389 == _zz_390)}; + assign _zz_383 = 2'b00; + assign _zz_384 = ({_zz_391,_zz_392} != 2'b00); + assign _zz_385 = ({_zz_393,_zz_394} != 3'b000); + assign _zz_386 = {(_zz_395 != _zz_396),{_zz_397,{_zz_398,_zz_399}}}; + assign _zz_387 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_388 = 32'h00002000; + assign _zz_389 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_390 = 32'h00001000; + assign _zz_391 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_392 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_393 = ((decode_INSTRUCTION & _zz_400) == 32'h00000040); + assign _zz_394 = {(_zz_401 == _zz_402),(_zz_403 == _zz_404)}; + assign _zz_395 = ((decode_INSTRUCTION & _zz_405) == 32'h00000020); + assign _zz_396 = 1'b0; + assign _zz_397 = ((_zz_406 == _zz_407) != 1'b0); + assign _zz_398 = ({_zz_408,_zz_409} != 3'b000); + assign _zz_399 = {(_zz_410 != _zz_411),{_zz_412,{_zz_413,_zz_414}}}; + assign _zz_400 = 32'h00000050; + assign _zz_401 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_402 = 32'h0; + assign _zz_403 = (decode_INSTRUCTION & 32'h00103040); + assign _zz_404 = 32'h00000040; + assign _zz_405 = 32'h00000020; + assign _zz_406 = (decode_INSTRUCTION & 32'h00000010); + assign _zz_407 = 32'h00000010; + assign _zz_408 = _zz_86; + assign _zz_409 = {(_zz_415 == _zz_416),(_zz_417 == _zz_418)}; + assign _zz_410 = {_zz_87,{_zz_419,{_zz_420,_zz_421}}}; + assign _zz_411 = 6'h0; + assign _zz_412 = ({_zz_86,_zz_422} != 2'b00); + assign _zz_413 = ({_zz_423,_zz_424} != 2'b00); + assign _zz_414 = {(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}; + assign _zz_415 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_416 = 32'h00000010; + assign _zz_417 = (decode_INSTRUCTION & 32'h02000060); + assign _zz_418 = 32'h00000020; + assign _zz_419 = ((decode_INSTRUCTION & _zz_430) == 32'h00001010); + assign _zz_420 = (_zz_431 == _zz_432); + assign _zz_421 = {_zz_433,{_zz_434,_zz_435}}; + assign _zz_422 = ((decode_INSTRUCTION & _zz_436) == 32'h00000020); + assign _zz_423 = _zz_86; + assign _zz_424 = (_zz_437 == _zz_438); + assign _zz_425 = {_zz_439,_zz_440}; + assign _zz_426 = 2'b00; + assign _zz_427 = (_zz_441 != 1'b0); + assign _zz_428 = (_zz_442 != _zz_443); + assign _zz_429 = {_zz_444,{_zz_445,_zz_446}}; + assign _zz_430 = 32'h00001010; + assign _zz_431 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_432 = 32'h00002010; + assign _zz_433 = ((decode_INSTRUCTION & _zz_447) == 32'h00000010); + assign _zz_434 = (_zz_448 == _zz_449); + assign _zz_435 = (_zz_450 == _zz_451); + assign _zz_436 = 32'h00000070; + assign _zz_437 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_438 = 32'h0; + assign _zz_439 = ((decode_INSTRUCTION & _zz_452) == 32'h00006010); + assign _zz_440 = ((decode_INSTRUCTION & _zz_453) == 32'h00004010); + assign _zz_441 = ((decode_INSTRUCTION & _zz_454) == 32'h00002010); + assign _zz_442 = {_zz_455,{_zz_456,_zz_457}}; + assign _zz_443 = 4'b0000; + assign _zz_444 = (_zz_458 != 1'b0); + assign _zz_445 = (_zz_459 != _zz_460); + assign _zz_446 = {_zz_461,{_zz_462,_zz_463}}; + assign _zz_447 = 32'h00000050; + assign _zz_448 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_449 = 32'h00000004; + assign _zz_450 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_451 = 32'h0; + assign _zz_452 = 32'h00006014; + assign _zz_453 = 32'h00005014; + assign _zz_454 = 32'h00006014; + assign _zz_455 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_456 = ((decode_INSTRUCTION & _zz_464) == 32'h0); + assign _zz_457 = {(_zz_465 == _zz_466),(_zz_467 == _zz_468)}; + assign _zz_458 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_459 = {(_zz_469 == _zz_470),{_zz_471,_zz_472}}; + assign _zz_460 = 3'b000; + assign _zz_461 = ({_zz_473,_zz_85} != 2'b00); + assign _zz_462 = ({_zz_474,_zz_475} != 2'b00); + assign _zz_463 = (_zz_476 != 1'b0); + assign _zz_464 = 32'h00000018; + assign _zz_465 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_466 = 32'h00002000; + assign _zz_467 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_468 = 32'h00001000; + assign _zz_469 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_470 = 32'h00000040; + assign _zz_471 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_472 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz_473 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_474 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_475 = _zz_85; + assign _zz_476 = ((decode_INSTRUCTION & 32'h00001048) == 32'h00001008); + assign _zz_477 = execute_INSTRUCTION[31]; + assign _zz_478 = execute_INSTRUCTION[31]; + assign _zz_479 = execute_INSTRUCTION[7]; always @ (posedge clk) begin - if(_zz_298) begin - _zz_165 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_303) begin + _zz_170 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_299) begin - _zz_166 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_304) begin + _zz_171 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1511,13 +1506,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_156 ), //i - .io_cpu_prefetch_isValid (_zz_157 ), //i + .io_flush (_zz_161 ), //i + .io_cpu_prefetch_isValid (_zz_162 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_158 ), //i - .io_cpu_fetch_isStuck (_zz_159 ), //i - .io_cpu_fetch_isRemoved (_zz_160 ), //i + .io_cpu_fetch_isValid (_zz_163 ), //i + .io_cpu_fetch_isStuck (_zz_164 ), //i + .io_cpu_fetch_isRemoved (_zz_165 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1530,8 +1525,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_161 ), //i - .io_cpu_decode_isStuck (_zz_162 ), //i + .io_cpu_decode_isValid (_zz_166 ), //i + .io_cpu_decode_isStuck (_zz_167 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1539,8 +1534,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_163 ), //i - .io_cpu_fill_valid (_zz_164 ), //i + .io_cpu_decode_isUser (_zz_168 ), //i + .io_cpu_fill_valid (_zz_169 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1549,24 +1544,24 @@ module VexRiscv ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_144[2:0] ), //i + ._zz_9 (_zz_149[2:0] ), //i ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); always @(*) begin - case(_zz_300) + case(_zz_305) 2'b00 : begin - _zz_167 = CsrPlugin_jumpInterface_payload; + _zz_172 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_167 = DBusSimplePlugin_redoBranch_payload; + _zz_172 = DBusSimplePlugin_redoBranch_payload; end 2'b10 : begin - _zz_167 = BranchPlugin_jumpInterface_payload; + _zz_172 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_167 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_172 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2206,25 +2201,25 @@ module VexRiscv ( assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_DIV = _zz_211[0]; - assign decode_IS_RS2_SIGNED = _zz_212[0]; - assign decode_IS_RS1_SIGNED = _zz_213[0]; - assign decode_IS_MUL = _zz_214[0]; + assign decode_IS_DIV = _zz_216[0]; + assign decode_IS_RS2_SIGNED = _zz_217[0]; + assign decode_IS_RS1_SIGNED = _zz_218[0]; + assign decode_IS_MUL = _zz_219[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_215[0]; + assign decode_IS_CSR = _zz_220[0]; assign _zz_8 = _zz_9; assign decode_SHIFT_CTRL = _zz_10; assign _zz_11 = _zz_12; assign decode_ALU_BITWISE_CTRL = _zz_13; assign _zz_14 = _zz_15; - assign decode_SRC_LESS_UNSIGNED = _zz_216[0]; - assign decode_MEMORY_STORE = _zz_217[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_221[0]; + assign decode_MEMORY_STORE = _zz_222[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_218[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_219[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_223[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_224[0]; assign decode_SRC2_CTRL = _zz_16; assign _zz_17 = _zz_18; assign decode_ALU_CTRL = _zz_19; @@ -2236,7 +2231,7 @@ module VexRiscv ( assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_220[0]; + assign decode_IS_EBREAK = _zz_225[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_MUL = decode_to_execute_IS_MUL; @@ -2254,18 +2249,18 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_115; + assign execute_BRANCH_COND_RESULT = _zz_120; assign execute_BRANCH_CTRL = _zz_28; - assign decode_RS2_USE = _zz_221[0]; - assign decode_RS1_USE = _zz_222[0]; + assign decode_RS2_USE = _zz_226[0]; + assign decode_RS1_USE = _zz_227[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; always @ (*) begin _zz_29 = memory_REGFILE_WRITE_DATA; - if(_zz_168)begin + if(_zz_173)begin _zz_29 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_169)begin + if(_zz_174)begin _zz_29 = memory_MulDivIterativePlugin_div_result; end end @@ -2276,28 +2271,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_109)begin + if((_zz_110 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_111; end end - if(_zz_170)begin - if(_zz_171)begin - if(_zz_108)begin + if(_zz_175)begin + if(_zz_176)begin + if(_zz_113)begin decode_RS2 = _zz_47; end end end - if(_zz_172)begin + if(_zz_177)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_110)begin + if(_zz_115)begin decode_RS2 = _zz_29; end end end - if(_zz_173)begin + if(_zz_178)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_112)begin + if(_zz_117)begin decode_RS2 = _zz_30; end end @@ -2306,28 +2301,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + if(_zz_109)begin + if((_zz_110 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_111; end end - if(_zz_170)begin - if(_zz_171)begin - if(_zz_107)begin + if(_zz_175)begin + if(_zz_176)begin + if(_zz_112)begin decode_RS1 = _zz_47; end end end - if(_zz_172)begin + if(_zz_177)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_109)begin + if(_zz_114)begin decode_RS1 = _zz_29; end end end - if(_zz_173)begin + if(_zz_178)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_111)begin + if(_zz_116)begin decode_RS1 = _zz_30; end end @@ -2336,10 +2331,10 @@ module VexRiscv ( always @ (*) begin _zz_30 = execute_REGFILE_WRITE_DATA; - if(_zz_174)begin + if(_zz_179)begin _zz_30 = _zz_106; end - if(_zz_175)begin + if(_zz_180)begin _zz_30 = execute_CsrPlugin_readData; end end @@ -2351,8 +2346,8 @@ module VexRiscv ( assign _zz_32 = execute_PC; assign execute_SRC2_CTRL = _zz_33; assign execute_SRC1_CTRL = _zz_34; - assign decode_SRC_USE_SUB_LESS = _zz_223[0]; - assign decode_SRC_ADD_ZERO = _zz_224[0]; + assign decode_SRC_USE_SUB_LESS = _zz_228[0]; + assign decode_SRC_ADD_ZERO = _zz_229[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_35; @@ -2370,13 +2365,13 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_225[0]; + decode_REGFILE_WRITE_VALID = _zz_230[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_301) == 32'h00001073),{(_zz_302 == _zz_303),{_zz_304,{_zz_305,_zz_306}}}}}}} != 20'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_306) == 32'h00001073),{(_zz_307 == _zz_308),{_zz_309,{_zz_310,_zz_311}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin _zz_47 = writeBack_REGFILE_WRITE_DATA; @@ -2419,32 +2414,32 @@ module VexRiscv ( assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_226[0]; - assign decode_FLUSH_ALL = _zz_227[0]; + assign decode_MEMORY_ENABLE = _zz_231[0]; + assign decode_FLUSH_ALL = _zz_232[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_176)begin + if(_zz_181)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_177)begin + if(_zz_182)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_178)begin + if(_zz_183)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_179)begin + if(_zz_184)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2476,7 +2471,7 @@ module VexRiscv ( if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_144) + case(_zz_149) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2487,7 +2482,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_107 || _zz_108)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2500,7 +2495,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_180)begin + if(_zz_185)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2514,7 +2509,7 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_180)begin + if(_zz_185)begin decode_arbitration_flushNext = 1'b1; end end @@ -2524,12 +2519,12 @@ module VexRiscv ( if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_77)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_174)begin + if(_zz_179)begin if((! execute_LightShifterPlugin_done))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_175)begin + if(_zz_180)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2538,7 +2533,7 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_181)begin + if(_zz_186)begin execute_arbitration_haltByOther = 1'b1; end end @@ -2555,8 +2550,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_181)begin - if(_zz_182)begin + if(_zz_186)begin + if(_zz_187)begin execute_arbitration_flushIt = 1'b1; end end @@ -2567,8 +2562,8 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_181)begin - if(_zz_182)begin + if(_zz_186)begin + if(_zz_187)begin execute_arbitration_flushNext = 1'b1; end end @@ -2579,15 +2574,15 @@ module VexRiscv ( if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_168)begin + if(_zz_173)begin if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_183)begin + if(_zz_188)begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_169)begin + if(_zz_174)begin if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2597,7 +2592,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_184)begin + if(_zz_189)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2620,7 +2615,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_184)begin + if(_zz_189)begin memory_arbitration_flushNext = 1'b1; end end @@ -2637,10 +2632,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_185)begin + if(_zz_190)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_186)begin + if(_zz_191)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2654,21 +2649,21 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_185)begin + if(_zz_190)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_186)begin + if(_zz_191)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_181)begin - if(_zz_182)begin + if(_zz_186)begin + if(_zz_187)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_187)begin + if(_zz_192)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -2690,21 +2685,21 @@ module VexRiscv ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_185)begin + if(_zz_190)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_186)begin + if(_zz_191)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_185)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_190)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_186)begin - case(_zz_188) + if(_zz_191)begin + case(_zz_193) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2738,11 +2733,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_51 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; - assign _zz_52 = (_zz_51 & (~ _zz_228)); + assign _zz_52 = (_zz_51 & (~ _zz_233)); assign _zz_53 = _zz_52[3]; assign _zz_54 = (_zz_52[1] || _zz_53); assign _zz_55 = (_zz_52[2] || _zz_53); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_167; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_172; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -2762,7 +2757,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_230); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_235); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -2854,7 +2849,7 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_144) + case(_zz_149) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -2866,7 +2861,7 @@ module VexRiscv ( endcase end - assign _zz_65 = _zz_231[11]; + assign _zz_65 = _zz_236[11]; always @ (*) begin _zz_66[18] = _zz_65; _zz_66[17] = _zz_65; @@ -2890,13 +2885,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_232[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_237[31])); if(_zz_71)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_67 = _zz_233[19]; + assign _zz_67 = _zz_238[19]; always @ (*) begin _zz_68[10] = _zz_67; _zz_68[9] = _zz_67; @@ -2911,7 +2906,7 @@ module VexRiscv ( _zz_68[0] = _zz_67; end - assign _zz_69 = _zz_234[11]; + assign _zz_69 = _zz_239[11]; always @ (*) begin _zz_70[18] = _zz_69; _zz_70[17] = _zz_69; @@ -2937,16 +2932,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_71 = _zz_235[1]; + _zz_71 = _zz_240[1]; end default : begin - _zz_71 = _zz_236[1]; + _zz_71 = _zz_241[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_72 = _zz_237[19]; + assign _zz_72 = _zz_242[19]; always @ (*) begin _zz_73[10] = _zz_72; _zz_73[9] = _zz_72; @@ -2961,7 +2956,7 @@ module VexRiscv ( _zz_73[0] = _zz_72; end - assign _zz_74 = _zz_238[11]; + assign _zz_74 = _zz_243[11]; always @ (*) begin _zz_75[18] = _zz_74; _zz_75[17] = _zz_74; @@ -2984,7 +2979,7 @@ module VexRiscv ( _zz_75[0] = _zz_74; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_73,{{{_zz_319,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_75,{{{_zz_320,_zz_321},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_73,{{{_zz_324,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_75,{{{_zz_325,_zz_326},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -2993,52 +2988,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_157 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_158 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_159 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_158; + assign _zz_162 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_163 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_164 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_163; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_161 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_162 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_163 = (CsrPlugin_privilege == 2'b00); + assign _zz_166 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_167 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_168 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_179)begin + if(_zz_184)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_177)begin + if(_zz_182)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_164 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_177)begin - _zz_164 = 1'b1; + _zz_169 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_182)begin + _zz_169 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_178)begin + if(_zz_183)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_176)begin + if(_zz_181)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_178)begin + if(_zz_183)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_176)begin + if(_zz_181)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3048,7 +3043,7 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_156 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_161 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign _zz_77 = 1'b0; always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; @@ -3101,7 +3096,7 @@ module VexRiscv ( assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_189)begin + if(_zz_194)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end if(memory_ALIGNEMENT_FAULT)begin @@ -3114,18 +3109,18 @@ module VexRiscv ( DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_190)begin + if(_zz_195)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_189)begin + if(_zz_194)begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_239}; + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_244}; end if(! memory_MMU_RSP2_refilling) begin if(memory_MMU_FAULT)begin @@ -3140,7 +3135,7 @@ module VexRiscv ( if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_190)begin + if(_zz_195)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -3214,7 +3209,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_209) + case(_zz_214) 2'b00 : begin writeBack_DBusSimplePlugin_rspFormated = _zz_81; end @@ -3251,7 +3246,7 @@ module VexRiscv ( assign _zz_88 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); assign _zz_89 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); assign _zz_90 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); - assign _zz_84 = {(((decode_INSTRUCTION & _zz_322) == 32'h00100050) != 1'b0),{((_zz_323 == _zz_324) != 1'b0),{({_zz_325,_zz_326} != 2'b00),{(_zz_327 != _zz_328),{_zz_329,{_zz_330,_zz_331}}}}}}; + assign _zz_84 = {(((decode_INSTRUCTION & _zz_327) == 32'h00100050) != 1'b0),{((_zz_328 == _zz_329) != 1'b0),{({_zz_330,_zz_331} != 2'b00),{(_zz_332 != _zz_333),{_zz_334,{_zz_335,_zz_336}}}}}}; assign _zz_91 = _zz_84[2 : 1]; assign _zz_46 = _zz_91; assign _zz_92 = _zz_84[7 : 6]; @@ -3271,8 +3266,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_165; - assign decode_RegFilePlugin_rs2Data = _zz_166; + assign decode_RegFilePlugin_rs1Data = _zz_170; + assign decode_RegFilePlugin_rs2Data = _zz_171; always @ (*) begin lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); if(_zz_98)begin @@ -3314,7 +3309,7 @@ module VexRiscv ( _zz_99 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_99 = {31'd0, _zz_240}; + _zz_99 = {31'd0, _zz_245}; end default : begin _zz_99 = execute_SRC_ADD_SUB; @@ -3328,18 +3323,18 @@ module VexRiscv ( _zz_100 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_100 = {29'd0, _zz_241}; + _zz_100 = {29'd0, _zz_246}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_100 = {27'd0, _zz_242}; + _zz_100 = {27'd0, _zz_247}; end endcase end - assign _zz_101 = _zz_243[11]; + assign _zz_101 = _zz_248[11]; always @ (*) begin _zz_102[19] = _zz_101; _zz_102[18] = _zz_101; @@ -3363,7 +3358,7 @@ module VexRiscv ( _zz_102[0] = _zz_101; end - assign _zz_103 = _zz_244[11]; + assign _zz_103 = _zz_249[11]; always @ (*) begin _zz_104[19] = _zz_103; _zz_104[18] = _zz_103; @@ -3405,7 +3400,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_245; + execute_SrcPlugin_addSub = _zz_250; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3422,186 +3417,181 @@ module VexRiscv ( _zz_106 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_106 = _zz_252; + _zz_106 = _zz_257; end endcase end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(_zz_191)begin - if(_zz_192)begin - if(_zz_107)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_107 = 1'b0; + if(_zz_196)begin + if(_zz_197)begin + if(_zz_112)begin + _zz_107 = 1'b1; end end end - if(_zz_193)begin - if(_zz_194)begin - if(_zz_109)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_198)begin + if(_zz_199)begin + if(_zz_114)begin + _zz_107 = 1'b1; end end end - if(_zz_195)begin - if(_zz_196)begin - if(_zz_111)begin - HazardSimplePlugin_src0Hazard = 1'b1; + if(_zz_200)begin + if(_zz_201)begin + if(_zz_116)begin + _zz_107 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_107 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(_zz_191)begin - if(_zz_192)begin - if(_zz_108)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_108 = 1'b0; + if(_zz_196)begin + if(_zz_197)begin + if(_zz_113)begin + _zz_108 = 1'b1; end end end - if(_zz_193)begin - if(_zz_194)begin - if(_zz_110)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_198)begin + if(_zz_199)begin + if(_zz_115)begin + _zz_108 = 1'b1; end end end - if(_zz_195)begin - if(_zz_196)begin - if(_zz_112)begin - HazardSimplePlugin_src1Hazard = 1'b1; + if(_zz_200)begin + if(_zz_201)begin + if(_zz_117)begin + _zz_108 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_108 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_38 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_37[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_47; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); - assign _zz_107 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_108 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_109 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_110 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_111 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_112 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_112 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_113 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_114 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_115 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_116 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_117 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_113 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_113 == 3'b000)) begin - _zz_114 = execute_BranchPlugin_eq; - end else if((_zz_113 == 3'b001)) begin - _zz_114 = (! execute_BranchPlugin_eq); - end else if((((_zz_113 & 3'b101) == 3'b101))) begin - _zz_114 = (! execute_SRC_LESS); + assign _zz_118 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_118 == 3'b000)) begin + _zz_119 = execute_BranchPlugin_eq; + end else if((_zz_118 == 3'b001)) begin + _zz_119 = (! execute_BranchPlugin_eq); + end else if((((_zz_118 & 3'b101) == 3'b101))) begin + _zz_119 = (! execute_SRC_LESS); end else begin - _zz_114 = execute_SRC_LESS; + _zz_119 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_115 = 1'b0; + _zz_120 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_115 = 1'b1; + _zz_120 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_115 = 1'b1; + _zz_120 = 1'b1; end default : begin - _zz_115 = _zz_114; + _zz_120 = _zz_119; end endcase end - assign _zz_116 = _zz_254[11]; - always @ (*) begin - _zz_117[19] = _zz_116; - _zz_117[18] = _zz_116; - _zz_117[17] = _zz_116; - _zz_117[16] = _zz_116; - _zz_117[15] = _zz_116; - _zz_117[14] = _zz_116; - _zz_117[13] = _zz_116; - _zz_117[12] = _zz_116; - _zz_117[11] = _zz_116; - _zz_117[10] = _zz_116; - _zz_117[9] = _zz_116; - _zz_117[8] = _zz_116; - _zz_117[7] = _zz_116; - _zz_117[6] = _zz_116; - _zz_117[5] = _zz_116; - _zz_117[4] = _zz_116; - _zz_117[3] = _zz_116; - _zz_117[2] = _zz_116; - _zz_117[1] = _zz_116; - _zz_117[0] = _zz_116; - end - - assign _zz_118 = _zz_255[19]; - always @ (*) begin - _zz_119[10] = _zz_118; - _zz_119[9] = _zz_118; - _zz_119[8] = _zz_118; - _zz_119[7] = _zz_118; - _zz_119[6] = _zz_118; - _zz_119[5] = _zz_118; - _zz_119[4] = _zz_118; - _zz_119[3] = _zz_118; - _zz_119[2] = _zz_118; - _zz_119[1] = _zz_118; - _zz_119[0] = _zz_118; - end - - assign _zz_120 = _zz_256[11]; - always @ (*) begin - _zz_121[18] = _zz_120; - _zz_121[17] = _zz_120; - _zz_121[16] = _zz_120; - _zz_121[15] = _zz_120; - _zz_121[14] = _zz_120; - _zz_121[13] = _zz_120; - _zz_121[12] = _zz_120; - _zz_121[11] = _zz_120; - _zz_121[10] = _zz_120; - _zz_121[9] = _zz_120; - _zz_121[8] = _zz_120; - _zz_121[7] = _zz_120; - _zz_121[6] = _zz_120; - _zz_121[5] = _zz_120; - _zz_121[4] = _zz_120; - _zz_121[3] = _zz_120; - _zz_121[2] = _zz_120; - _zz_121[1] = _zz_120; - _zz_121[0] = _zz_120; + assign _zz_121 = _zz_259[11]; + always @ (*) begin + _zz_122[19] = _zz_121; + _zz_122[18] = _zz_121; + _zz_122[17] = _zz_121; + _zz_122[16] = _zz_121; + _zz_122[15] = _zz_121; + _zz_122[14] = _zz_121; + _zz_122[13] = _zz_121; + _zz_122[12] = _zz_121; + _zz_122[11] = _zz_121; + _zz_122[10] = _zz_121; + _zz_122[9] = _zz_121; + _zz_122[8] = _zz_121; + _zz_122[7] = _zz_121; + _zz_122[6] = _zz_121; + _zz_122[5] = _zz_121; + _zz_122[4] = _zz_121; + _zz_122[3] = _zz_121; + _zz_122[2] = _zz_121; + _zz_122[1] = _zz_121; + _zz_122[0] = _zz_121; + end + + assign _zz_123 = _zz_260[19]; + always @ (*) begin + _zz_124[10] = _zz_123; + _zz_124[9] = _zz_123; + _zz_124[8] = _zz_123; + _zz_124[7] = _zz_123; + _zz_124[6] = _zz_123; + _zz_124[5] = _zz_123; + _zz_124[4] = _zz_123; + _zz_124[3] = _zz_123; + _zz_124[2] = _zz_123; + _zz_124[1] = _zz_123; + _zz_124[0] = _zz_123; + end + + assign _zz_125 = _zz_261[11]; + always @ (*) begin + _zz_126[18] = _zz_125; + _zz_126[17] = _zz_125; + _zz_126[16] = _zz_125; + _zz_126[15] = _zz_125; + _zz_126[14] = _zz_125; + _zz_126[13] = _zz_125; + _zz_126[12] = _zz_125; + _zz_126[11] = _zz_125; + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_122 = (_zz_257[1] ^ execute_RS1[1]); + _zz_127 = (_zz_262[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_122 = _zz_258[1]; + _zz_127 = _zz_263[1]; end default : begin - _zz_122 = _zz_259[1]; + _zz_127 = _zz_264[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_122); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_127); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -3613,80 +3603,80 @@ module VexRiscv ( endcase end - assign _zz_123 = _zz_260[11]; + assign _zz_128 = _zz_265[11]; always @ (*) begin - _zz_124[19] = _zz_123; - _zz_124[18] = _zz_123; - _zz_124[17] = _zz_123; - _zz_124[16] = _zz_123; - _zz_124[15] = _zz_123; - _zz_124[14] = _zz_123; - _zz_124[13] = _zz_123; - _zz_124[12] = _zz_123; - _zz_124[11] = _zz_123; - _zz_124[10] = _zz_123; - _zz_124[9] = _zz_123; - _zz_124[8] = _zz_123; - _zz_124[7] = _zz_123; - _zz_124[6] = _zz_123; - _zz_124[5] = _zz_123; - _zz_124[4] = _zz_123; - _zz_124[3] = _zz_123; - _zz_124[2] = _zz_123; - _zz_124[1] = _zz_123; - _zz_124[0] = _zz_123; + _zz_129[19] = _zz_128; + _zz_129[18] = _zz_128; + _zz_129[17] = _zz_128; + _zz_129[16] = _zz_128; + _zz_129[15] = _zz_128; + _zz_129[14] = _zz_128; + _zz_129[13] = _zz_128; + _zz_129[12] = _zz_128; + _zz_129[11] = _zz_128; + _zz_129[10] = _zz_128; + _zz_129[9] = _zz_128; + _zz_129[8] = _zz_128; + _zz_129[7] = _zz_128; + _zz_129[6] = _zz_128; + _zz_129[5] = _zz_128; + _zz_129[4] = _zz_128; + _zz_129[3] = _zz_128; + _zz_129[2] = _zz_128; + _zz_129[1] = _zz_128; + _zz_129[0] = _zz_128; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_124,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_129,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_126,{{{_zz_472,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_128,{{{_zz_473,_zz_474},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_131,{{{_zz_477,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_133,{{{_zz_478,_zz_479},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_263}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_268}; end end endcase end - assign _zz_125 = _zz_261[19]; - always @ (*) begin - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; - end - - assign _zz_127 = _zz_262[11]; - always @ (*) begin - _zz_128[18] = _zz_127; - _zz_128[17] = _zz_127; - _zz_128[16] = _zz_127; - _zz_128[15] = _zz_127; - _zz_128[14] = _zz_127; - _zz_128[13] = _zz_127; - _zz_128[12] = _zz_127; - _zz_128[11] = _zz_127; - _zz_128[10] = _zz_127; - _zz_128[9] = _zz_127; - _zz_128[8] = _zz_127; - _zz_128[7] = _zz_127; - _zz_128[6] = _zz_127; - _zz_128[5] = _zz_127; - _zz_128[4] = _zz_127; - _zz_128[3] = _zz_127; - _zz_128[2] = _zz_127; - _zz_128[1] = _zz_127; - _zz_128[0] = _zz_127; + assign _zz_130 = _zz_266[19]; + always @ (*) begin + _zz_131[10] = _zz_130; + _zz_131[9] = _zz_130; + _zz_131[8] = _zz_130; + _zz_131[7] = _zz_130; + _zz_131[6] = _zz_130; + _zz_131[5] = _zz_130; + _zz_131[4] = _zz_130; + _zz_131[3] = _zz_130; + _zz_131[2] = _zz_130; + _zz_131[1] = _zz_130; + _zz_131[0] = _zz_130; + end + + assign _zz_132 = _zz_267[11]; + always @ (*) begin + _zz_133[18] = _zz_132; + _zz_133[17] = _zz_132; + _zz_133[16] = _zz_132; + _zz_133[15] = _zz_132; + _zz_133[14] = _zz_132; + _zz_133[13] = _zz_132; + _zz_133[12] = _zz_132; + _zz_133[11] = _zz_132; + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -3705,18 +3695,18 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_129 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_130 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_131 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_134 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_135 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_136 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_132 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_133 = _zz_264[0]; - assign _zz_134 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_135 = _zz_266[0]; + assign _zz_137 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_138 = _zz_269[0]; + assign _zz_139 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_140 = _zz_271[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_180)begin + if(_zz_185)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3736,7 +3726,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_184)begin + if(_zz_189)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3795,7 +3785,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3844,7 +3834,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_197)begin + if(_zz_202)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3863,14 +3853,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_198)begin + if(_zz_203)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_198)begin + if(_zz_203)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3885,14 +3875,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_197)begin + if(_zz_202)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_197)begin + if(_zz_202)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -3901,7 +3891,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_210) + case(_zz_215) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3915,8 +3905,8 @@ module VexRiscv ( assign memory_MulDivIterativePlugin_frontendOk = 1'b1; always @ (*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_168)begin - if(_zz_183)begin + if(_zz_173)begin + if(_zz_188)begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end @@ -3935,7 +3925,7 @@ module VexRiscv ( if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_269); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_274); end if(memory_MulDivIterativePlugin_mul_counter_willClear)begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; @@ -3944,8 +3934,8 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_169)begin - if(_zz_199)begin + if(_zz_174)begin + if(_zz_204)begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end @@ -3953,7 +3943,7 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_200)begin + if(_zz_205)begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end @@ -3964,32 +3954,32 @@ module VexRiscv ( if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_277); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_282); end if(memory_MulDivIterativePlugin_div_counter_willClear)begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end end - assign _zz_136 = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_136[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_278); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_279 : _zz_280); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_281[31:0]; - assign _zz_137 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_138 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_139 = ((execute_IS_MUL && _zz_138) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_141 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_141[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_283); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_284 : _zz_285); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_286[31:0]; + assign _zz_142 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_143 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_144 = ((execute_IS_MUL && _zz_143) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_140[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_140[31 : 0] = execute_RS1; + _zz_145[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_145[31 : 0] = execute_RS1; end - assign _zz_142 = (_zz_141 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_142 != 32'h0); + assign _zz_147 = (_zz_146 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_147 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_201) + case(_zz_206) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4003,7 +3993,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_143))begin + if((! _zz_148))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4015,7 +4005,7 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_201) + case(_zz_206) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4077,7 +4067,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_144) + case(_zz_149) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4087,91 +4077,91 @@ module VexRiscv ( end always @ (*) begin - _zz_145 = 32'h0; + _zz_150 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_145[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_145[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_145[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_150[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_150[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_150[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_146 = 32'h0; + _zz_151 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_146[11 : 11] = CsrPlugin_mip_MEIP; - _zz_146[7 : 7] = CsrPlugin_mip_MTIP; - _zz_146[3 : 3] = CsrPlugin_mip_MSIP; + _zz_151[11 : 11] = CsrPlugin_mip_MEIP; + _zz_151[7 : 7] = CsrPlugin_mip_MTIP; + _zz_151[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_147 = 32'h0; + _zz_152 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_147[11 : 11] = CsrPlugin_mie_MEIE; - _zz_147[7 : 7] = CsrPlugin_mie_MTIE; - _zz_147[3 : 3] = CsrPlugin_mie_MSIE; + _zz_152[11 : 11] = CsrPlugin_mie_MEIE; + _zz_152[7 : 7] = CsrPlugin_mie_MTIE; + _zz_152[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_148 = 32'h0; + _zz_153 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_148[31 : 0] = CsrPlugin_mepc; + _zz_153[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_149 = 32'h0; + _zz_154 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_149[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_149[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_154[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_154[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_150 = 32'h0; + _zz_155 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_150[31 : 0] = CsrPlugin_mtval; + _zz_155[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_151 = 32'h0; + _zz_156 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_151[31 : 0] = _zz_141; + _zz_156[31 : 0] = _zz_146; end end always @ (*) begin - _zz_152 = 32'h0; + _zz_157 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_152[31 : 0] = _zz_142; + _zz_157[31 : 0] = _zz_147; end end - assign execute_CsrPlugin_readData = (((_zz_145 | _zz_146) | (_zz_147 | _zz_148)) | ((_zz_149 | _zz_150) | (_zz_151 | _zz_152))); - assign iBusWishbone_ADR = {_zz_297,_zz_153}; - assign iBusWishbone_CTI = ((_zz_153 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((_zz_150 | _zz_151) | (_zz_152 | _zz_153)) | ((_zz_154 | _zz_155) | (_zz_156 | _zz_157))); + assign iBusWishbone_ADR = {_zz_302,_zz_158}; + assign iBusWishbone_CTI = ((_zz_158 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_202)begin + if(_zz_207)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_202)begin + if(_zz_207)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_154; + assign iBus_rsp_valid = _zz_159; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; @@ -4186,19 +4176,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_155 = 4'b0001; + _zz_160 = 4'b0001; end 2'b01 : begin - _zz_155 = 4'b0011; + _zz_160 = 4'b0011; end default : begin - _zz_155 = 4'b1111; + _zz_160 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_155 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_160 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -4229,7 +4219,7 @@ module VexRiscv ( IBusCachedPlugin_rspCounter <= 32'h0; _zz_98 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_109 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -4248,13 +4238,13 @@ module VexRiscv ( execute_CsrPlugin_wfiWake <= 1'b0; memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - _zz_141 <= 32'h0; + _zz_146 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_144 <= 3'b000; - _zz_153 <= 3'b000; - _zz_154 <= 1'b0; + _zz_149 <= 3'b000; + _zz_158 <= 3'b000; + _zz_159 <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin @@ -4355,8 +4345,8 @@ module VexRiscv ( `endif `endif _zz_98 <= 1'b0; - if(_zz_174)begin - if(_zz_203)begin + if(_zz_179)begin + if(_zz_208)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -4366,7 +4356,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_109 <= (_zz_38 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4388,14 +4378,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_204)begin - if(_zz_205)begin + if(_zz_209)begin + if(_zz_210)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_206)begin + if(_zz_211)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_207)begin + if(_zz_212)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4419,7 +4409,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_185)begin + if(_zz_190)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4430,8 +4420,8 @@ module VexRiscv ( end endcase end - if(_zz_186)begin - case(_zz_188) + if(_zz_191)begin + case(_zz_193) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4441,7 +4431,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_131,{_zz_130,_zz_129}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_136,{_zz_135,_zz_134}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin @@ -4462,25 +4452,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_144) + case(_zz_149) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_144 <= 3'b001; + _zz_149 <= 3'b001; end end 3'b001 : begin - _zz_144 <= 3'b010; + _zz_149 <= 3'b010; end 3'b010 : begin - _zz_144 <= 3'b011; + _zz_149 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_144 <= 3'b100; + _zz_149 <= 3'b100; end end 3'b100 : begin - _zz_144 <= 3'b000; + _zz_149 <= 3'b000; end default : begin end @@ -4488,29 +4478,29 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_291[0]; - CsrPlugin_mstatus_MIE <= _zz_292[0]; + CsrPlugin_mstatus_MPIE <= _zz_296[0]; + CsrPlugin_mstatus_MIE <= _zz_297[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_294[0]; - CsrPlugin_mie_MTIE <= _zz_295[0]; - CsrPlugin_mie_MSIE <= _zz_296[0]; + CsrPlugin_mie_MEIE <= _zz_299[0]; + CsrPlugin_mie_MTIE <= _zz_300[0]; + CsrPlugin_mie_MSIE <= _zz_301[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_141 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_202)begin + if(_zz_207)begin if(iBusWishbone_ACK)begin - _zz_153 <= (_zz_153 + 3'b001); + _zz_158 <= (_zz_158 + 3'b001); end end - _zz_154 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_208)begin + _zz_159 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_213)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -4530,13 +4520,13 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_174)begin - if(_zz_203)begin + if(_zz_179)begin + if(_zz_208)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_110 <= _zz_37[11 : 7]; + _zz_111 <= _zz_47; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -4544,33 +4534,33 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_180)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_133 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_133 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_185)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_138 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_138 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_184)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_135 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_135 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_189)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_140 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_140 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_204)begin - if(_zz_205)begin + if(_zz_209)begin + if(_zz_210)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_206)begin + if(_zz_211)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_207)begin + if(_zz_212)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_185)begin + if(_zz_190)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4584,10 +4574,10 @@ module VexRiscv ( end endcase end - if(_zz_168)begin - if(_zz_183)begin + if(_zz_173)begin + if(_zz_188)begin memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_270,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_275,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin @@ -4596,20 +4586,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_MulDivIterativePlugin_div_done <= 1'b0; end - if(_zz_169)begin - if(_zz_199)begin + if(_zz_174)begin + if(_zz_204)begin memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_result <= _zz_282[31:0]; + memory_MulDivIterativePlugin_div_result <= _zz_287[31:0]; end end end - if(_zz_200)begin + if(_zz_205)begin memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_139 ? (~ _zz_140) : _zz_140) + _zz_288); - memory_MulDivIterativePlugin_rs2 <= ((_zz_138 ? (~ execute_RS2) : execute_RS2) + _zz_290); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_139 ^ (_zz_138 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_MulDivIterativePlugin_rs1 <= ((_zz_144 ? (~ _zz_145) : _zz_145) + _zz_293); + memory_MulDivIterativePlugin_rs2 <= ((_zz_143 ? (~ execute_RS2) : execute_RS2) + _zz_295); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_144 ^ (_zz_143 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -4817,7 +4807,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_293[0]; + CsrPlugin_mip_MSIP <= _zz_298[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -4832,7 +4822,7 @@ module VexRiscv ( end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_208)begin + if(_zz_213)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; @@ -4850,8 +4840,8 @@ module VexRiscv ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_47; end - _zz_143 <= debug_bus_cmd_payload_address[2]; - if(_zz_181)begin + _zz_148 <= debug_bus_cmd_payload_address[2]; + if(_zz_186)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -4869,7 +4859,7 @@ module VexRiscv ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_201) + case(_zz_206) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -4897,13 +4887,13 @@ module VexRiscv ( end endcase end - if(_zz_181)begin - if(_zz_182)begin + if(_zz_186)begin + if(_zz_187)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_187)begin + if(_zz_192)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v index 93bdea0..490f8bc 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -73,27 +73,23 @@ module VexRiscv ( input clk, input reset ); - wire _zz_120; - wire _zz_121; - reg [31:0] _zz_122; - reg [31:0] _zz_123; - reg [31:0] _zz_124; + wire _zz_124; + wire _zz_125; + reg [31:0] _zz_126; + reg [31:0] _zz_127; + reg [31:0] _zz_128; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; - wire _zz_125; - wire _zz_126; - wire _zz_127; - wire _zz_128; wire _zz_129; wire _zz_130; - wire [1:0] _zz_131; + wire _zz_131; wire _zz_132; wire _zz_133; wire _zz_134; - wire _zz_135; + wire [1:0] _zz_135; wire _zz_136; wire _zz_137; wire _zz_138; @@ -107,12 +103,12 @@ module VexRiscv ( wire _zz_146; wire _zz_147; wire _zz_148; - wire [1:0] _zz_149; + wire _zz_149; wire _zz_150; - wire [0:0] _zz_151; - wire [0:0] _zz_152; - wire [0:0] _zz_153; - wire [0:0] _zz_154; + wire _zz_151; + wire _zz_152; + wire [1:0] _zz_153; + wire _zz_154; wire [0:0] _zz_155; wire [0:0] _zz_156; wire [0:0] _zz_157; @@ -120,176 +116,180 @@ module VexRiscv ( wire [0:0] _zz_159; wire [0:0] _zz_160; wire [0:0] _zz_161; - wire [2:0] _zz_162; - wire [2:0] _zz_163; - wire [31:0] _zz_164; - wire [2:0] _zz_165; - wire [0:0] _zz_166; + wire [0:0] _zz_162; + wire [0:0] _zz_163; + wire [0:0] _zz_164; + wire [0:0] _zz_165; + wire [2:0] _zz_166; wire [2:0] _zz_167; - wire [0:0] _zz_168; + wire [31:0] _zz_168; wire [2:0] _zz_169; wire [0:0] _zz_170; wire [2:0] _zz_171; wire [0:0] _zz_172; wire [2:0] _zz_173; - wire [2:0] _zz_174; - wire [0:0] _zz_175; - wire [2:0] _zz_176; - wire [4:0] _zz_177; - wire [11:0] _zz_178; - wire [11:0] _zz_179; - wire [31:0] _zz_180; - wire [31:0] _zz_181; - wire [31:0] _zz_182; - wire [31:0] _zz_183; + wire [0:0] _zz_174; + wire [2:0] _zz_175; + wire [0:0] _zz_176; + wire [2:0] _zz_177; + wire [2:0] _zz_178; + wire [0:0] _zz_179; + wire [2:0] _zz_180; + wire [4:0] _zz_181; + wire [11:0] _zz_182; + wire [11:0] _zz_183; wire [31:0] _zz_184; wire [31:0] _zz_185; wire [31:0] _zz_186; wire [31:0] _zz_187; - wire [32:0] _zz_188; - wire [19:0] _zz_189; - wire [11:0] _zz_190; - wire [11:0] _zz_191; - wire [1:0] _zz_192; - wire [1:0] _zz_193; - wire [1:0] _zz_194; - wire [1:0] _zz_195; - wire [0:0] _zz_196; - wire [0:0] _zz_197; - wire [0:0] _zz_198; - wire [0:0] _zz_199; + wire [31:0] _zz_188; + wire [31:0] _zz_189; + wire [31:0] _zz_190; + wire [31:0] _zz_191; + wire [32:0] _zz_192; + wire [19:0] _zz_193; + wire [11:0] _zz_194; + wire [11:0] _zz_195; + wire [1:0] _zz_196; + wire [1:0] _zz_197; + wire [1:0] _zz_198; + wire [1:0] _zz_199; wire [0:0] _zz_200; wire [0:0] _zz_201; - wire _zz_202; - wire _zz_203; - wire [1:0] _zz_204; - wire [31:0] _zz_205; - wire [31:0] _zz_206; - wire [31:0] _zz_207; - wire _zz_208; - wire [0:0] _zz_209; - wire [12:0] _zz_210; + wire [0:0] _zz_202; + wire [0:0] _zz_203; + wire [0:0] _zz_204; + wire [0:0] _zz_205; + wire _zz_206; + wire _zz_207; + wire [1:0] _zz_208; + wire [31:0] _zz_209; + wire [31:0] _zz_210; wire [31:0] _zz_211; - wire [31:0] _zz_212; - wire [31:0] _zz_213; - wire _zz_214; - wire [0:0] _zz_215; - wire [6:0] _zz_216; + wire _zz_212; + wire [0:0] _zz_213; + wire [12:0] _zz_214; + wire [31:0] _zz_215; + wire [31:0] _zz_216; wire [31:0] _zz_217; - wire [31:0] _zz_218; - wire [31:0] _zz_219; - wire _zz_220; - wire [0:0] _zz_221; - wire [0:0] _zz_222; + wire _zz_218; + wire [0:0] _zz_219; + wire [6:0] _zz_220; + wire [31:0] _zz_221; + wire [31:0] _zz_222; wire [31:0] _zz_223; - wire [31:0] _zz_224; - wire [31:0] _zz_225; + wire _zz_224; + wire [0:0] _zz_225; wire [0:0] _zz_226; - wire [0:0] _zz_227; - wire [1:0] _zz_228; - wire [1:0] _zz_229; - wire _zz_230; + wire [31:0] _zz_227; + wire [31:0] _zz_228; + wire [31:0] _zz_229; + wire [0:0] _zz_230; wire [0:0] _zz_231; - wire [19:0] _zz_232; - wire [31:0] _zz_233; - wire [31:0] _zz_234; - wire [31:0] _zz_235; - wire [31:0] _zz_236; + wire [1:0] _zz_232; + wire [1:0] _zz_233; + wire _zz_234; + wire [0:0] _zz_235; + wire [19:0] _zz_236; wire [31:0] _zz_237; wire [31:0] _zz_238; - wire _zz_239; - wire [1:0] _zz_240; - wire [1:0] _zz_241; - wire _zz_242; - wire [0:0] _zz_243; - wire [16:0] _zz_244; - wire [31:0] _zz_245; - wire [31:0] _zz_246; - wire [31:0] _zz_247; - wire [31:0] _zz_248; - wire _zz_249; - wire _zz_250; - wire _zz_251; - wire [0:0] _zz_252; - wire [0:0] _zz_253; + wire [31:0] _zz_239; + wire [31:0] _zz_240; + wire [31:0] _zz_241; + wire [31:0] _zz_242; + wire _zz_243; + wire [1:0] _zz_244; + wire [1:0] _zz_245; + wire _zz_246; + wire [0:0] _zz_247; + wire [16:0] _zz_248; + wire [31:0] _zz_249; + wire [31:0] _zz_250; + wire [31:0] _zz_251; + wire [31:0] _zz_252; + wire _zz_253; wire _zz_254; - wire [0:0] _zz_255; - wire [13:0] _zz_256; - wire [31:0] _zz_257; + wire _zz_255; + wire [0:0] _zz_256; + wire [0:0] _zz_257; wire _zz_258; - wire _zz_259; - wire [0:0] _zz_260; - wire [0:0] _zz_261; - wire [2:0] _zz_262; - wire [2:0] _zz_263; - wire _zz_264; + wire [0:0] _zz_259; + wire [13:0] _zz_260; + wire [31:0] _zz_261; + wire _zz_262; + wire _zz_263; + wire [0:0] _zz_264; wire [0:0] _zz_265; - wire [10:0] _zz_266; - wire [31:0] _zz_267; - wire [31:0] _zz_268; - wire [31:0] _zz_269; - wire [31:0] _zz_270; - wire _zz_271; - wire _zz_272; + wire [2:0] _zz_266; + wire [2:0] _zz_267; + wire _zz_268; + wire [0:0] _zz_269; + wire [10:0] _zz_270; + wire [31:0] _zz_271; + wire [31:0] _zz_272; wire [31:0] _zz_273; wire [31:0] _zz_274; wire _zz_275; - wire [0:0] _zz_276; - wire [0:0] _zz_277; - wire _zz_278; - wire [0:0] _zz_279; - wire [7:0] _zz_280; + wire _zz_276; + wire [31:0] _zz_277; + wire [31:0] _zz_278; + wire _zz_279; + wire [0:0] _zz_280; wire [0:0] _zz_281; - wire [3:0] _zz_282; + wire _zz_282; wire [0:0] _zz_283; - wire [0:0] _zz_284; - wire [1:0] _zz_285; - wire [1:0] _zz_286; - wire _zz_287; + wire [7:0] _zz_284; + wire [0:0] _zz_285; + wire [3:0] _zz_286; + wire [0:0] _zz_287; wire [0:0] _zz_288; - wire [4:0] _zz_289; - wire [31:0] _zz_290; - wire [31:0] _zz_291; - wire [31:0] _zz_292; - wire [0:0] _zz_293; - wire [0:0] _zz_294; + wire [1:0] _zz_289; + wire [1:0] _zz_290; + wire _zz_291; + wire [0:0] _zz_292; + wire [4:0] _zz_293; + wire [31:0] _zz_294; wire [31:0] _zz_295; wire [31:0] _zz_296; - wire [31:0] _zz_297; - wire _zz_298; - wire _zz_299; - wire _zz_300; - wire [3:0] _zz_301; - wire [3:0] _zz_302; + wire [0:0] _zz_297; + wire [0:0] _zz_298; + wire [31:0] _zz_299; + wire [31:0] _zz_300; + wire [31:0] _zz_301; + wire _zz_302; wire _zz_303; - wire [0:0] _zz_304; - wire [1:0] _zz_305; - wire [31:0] _zz_306; - wire [31:0] _zz_307; - wire [31:0] _zz_308; - wire [31:0] _zz_309; + wire _zz_304; + wire [3:0] _zz_305; + wire [3:0] _zz_306; + wire _zz_307; + wire [0:0] _zz_308; + wire [1:0] _zz_309; wire [31:0] _zz_310; wire [31:0] _zz_311; wire [31:0] _zz_312; - wire _zz_313; - wire [0:0] _zz_314; - wire [1:0] _zz_315; - wire _zz_316; - wire [2:0] _zz_317; - wire [2:0] _zz_318; - wire _zz_319; + wire [31:0] _zz_313; + wire [31:0] _zz_314; + wire [31:0] _zz_315; + wire [31:0] _zz_316; + wire _zz_317; + wire [0:0] _zz_318; + wire [1:0] _zz_319; wire _zz_320; - wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; + wire [2:0] _zz_321; + wire [2:0] _zz_322; + wire _zz_323; + wire _zz_324; wire [31:0] _zz_325; wire [31:0] _zz_326; wire [31:0] _zz_327; - wire _zz_328; - wire _zz_329; - wire _zz_330; - wire _zz_331; + wire [31:0] _zz_328; + wire [31:0] _zz_329; + wire [31:0] _zz_330; + wire [31:0] _zz_331; + wire _zz_332; + wire _zz_333; + wire _zz_334; + wire _zz_335; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -724,28 +724,22 @@ module VexRiscv ( wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; reg [31:0] _zz_91; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_92; + reg _zz_92; reg _zz_93; reg _zz_94; + reg [4:0] _zz_95; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_96; + reg _zz_97; + reg _zz_98; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_95; - reg [10:0] _zz_96; - wire _zz_97; - reg [19:0] _zz_98; wire _zz_99; - reg [18:0] _zz_100; - reg [31:0] _zz_101; + reg [10:0] _zz_100; + wire _zz_101; + reg [19:0] _zz_102; + wire _zz_103; + reg [18:0] _zz_104; + reg [31:0] _zz_105; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -767,9 +761,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_102; - wire _zz_103; - wire _zz_104; + wire _zz_106; + wire _zz_107; + wire _zz_108; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -782,10 +776,10 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_105; - wire _zz_106; - wire [1:0] _zz_107; - wire _zz_108; + wire [1:0] _zz_109; + wire _zz_110; + wire [1:0] _zz_111; + wire _zz_112; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -815,8 +809,8 @@ module VexRiscv ( reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_109; - wire [31:0] _zz_110; + reg [31:0] _zz_113; + wire [31:0] _zz_114; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -882,14 +876,14 @@ module VexRiscv ( reg execute_CsrPlugin_csr_835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_111; - reg [31:0] _zz_112; - reg [31:0] _zz_113; - reg [31:0] _zz_114; reg [31:0] _zz_115; reg [31:0] _zz_116; reg [31:0] _zz_117; reg [31:0] _zz_118; + reg [31:0] _zz_119; + reg [31:0] _zz_120; + reg [31:0] _zz_121; + reg [31:0] _zz_122; wire iBus_cmd_m2sPipe_valid; wire iBus_cmd_m2sPipe_ready; wire [31:0] iBus_cmd_m2sPipe_payload_pc; @@ -907,7 +901,7 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_119; + reg [3:0] _zz_123; `ifndef SYNTHESIS reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; @@ -986,222 +980,222 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_125 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_126 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_127 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_128 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_129 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_130 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_131 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_132 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_133 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_134 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_135 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_136 = (1'b1 || (! 1'b1)); - assign _zz_137 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_138 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_139 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_140 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_141 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_142 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_143 = (! execute_arbitration_isStuckByOthers); - assign _zz_144 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_145 = ((_zz_102 && 1'b1) && (! 1'b0)); - assign _zz_146 = ((_zz_103 && 1'b1) && (! 1'b0)); - assign _zz_147 = ((_zz_104 && 1'b1) && (! 1'b0)); - assign _zz_148 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_149 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_150 = execute_INSTRUCTION[13]; - assign _zz_151 = _zz_71[23 : 23]; - assign _zz_152 = _zz_71[15 : 15]; - assign _zz_153 = _zz_71[12 : 12]; - assign _zz_154 = _zz_71[11 : 11]; - assign _zz_155 = _zz_71[10 : 10]; - assign _zz_156 = _zz_71[14 : 14]; - assign _zz_157 = _zz_71[4 : 4]; - assign _zz_158 = _zz_71[2 : 2]; - assign _zz_159 = _zz_71[18 : 18]; - assign _zz_160 = _zz_71[9 : 9]; - assign _zz_161 = _zz_71[3 : 3]; - assign _zz_162 = (_zz_49 - 3'b001); - assign _zz_163 = {IBusSimplePlugin_fetchPc_inc,2'b00}; - assign _zz_164 = {29'd0, _zz_163}; - assign _zz_165 = (IBusSimplePlugin_pending_value + _zz_167); - assign _zz_166 = IBusSimplePlugin_pending_inc; - assign _zz_167 = {2'd0, _zz_166}; - assign _zz_168 = IBusSimplePlugin_pending_dec; - assign _zz_169 = {2'd0, _zz_168}; - assign _zz_170 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_129 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_130 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_131 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_132 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_133 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_134 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_135 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_136 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); + assign _zz_137 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_138 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_139 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_140 = (1'b1 || (! 1'b1)); + assign _zz_141 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_142 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_143 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_144 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_145 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_146 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_147 = (! execute_arbitration_isStuckByOthers); + assign _zz_148 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_149 = ((_zz_106 && 1'b1) && (! 1'b0)); + assign _zz_150 = ((_zz_107 && 1'b1) && (! 1'b0)); + assign _zz_151 = ((_zz_108 && 1'b1) && (! 1'b0)); + assign _zz_152 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_153 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_154 = execute_INSTRUCTION[13]; + assign _zz_155 = _zz_71[23 : 23]; + assign _zz_156 = _zz_71[15 : 15]; + assign _zz_157 = _zz_71[12 : 12]; + assign _zz_158 = _zz_71[11 : 11]; + assign _zz_159 = _zz_71[10 : 10]; + assign _zz_160 = _zz_71[14 : 14]; + assign _zz_161 = _zz_71[4 : 4]; + assign _zz_162 = _zz_71[2 : 2]; + assign _zz_163 = _zz_71[18 : 18]; + assign _zz_164 = _zz_71[9 : 9]; + assign _zz_165 = _zz_71[3 : 3]; + assign _zz_166 = (_zz_49 - 3'b001); + assign _zz_167 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_168 = {29'd0, _zz_167}; + assign _zz_169 = (IBusSimplePlugin_pending_value + _zz_171); + assign _zz_170 = IBusSimplePlugin_pending_inc; assign _zz_171 = {2'd0, _zz_170}; assign _zz_172 = IBusSimplePlugin_pending_dec; assign _zz_173 = {2'd0, _zz_172}; - assign _zz_174 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_175 = execute_SRC_LESS; - assign _zz_176 = 3'b100; - assign _zz_177 = execute_INSTRUCTION[19 : 15]; - assign _zz_178 = execute_INSTRUCTION[31 : 20]; - assign _zz_179 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_180 = ($signed(_zz_181) + $signed(_zz_184)); - assign _zz_181 = ($signed(_zz_182) + $signed(_zz_183)); - assign _zz_182 = execute_SRC1; - assign _zz_183 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_184 = (execute_SRC_USE_SUB_LESS ? _zz_185 : _zz_186); - assign _zz_185 = 32'h00000001; - assign _zz_186 = 32'h0; - assign _zz_187 = (_zz_188 >>> 1); - assign _zz_188 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_189 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_190 = execute_INSTRUCTION[31 : 20]; - assign _zz_191 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_192 = (_zz_105 & (~ _zz_193)); - assign _zz_193 = (_zz_105 - 2'b01); - assign _zz_194 = (_zz_107 & (~ _zz_195)); - assign _zz_195 = (_zz_107 - 2'b01); - assign _zz_196 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_197 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_198 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_199 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_174 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_175 = {2'd0, _zz_174}; + assign _zz_176 = IBusSimplePlugin_pending_dec; + assign _zz_177 = {2'd0, _zz_176}; + assign _zz_178 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_179 = execute_SRC_LESS; + assign _zz_180 = 3'b100; + assign _zz_181 = execute_INSTRUCTION[19 : 15]; + assign _zz_182 = execute_INSTRUCTION[31 : 20]; + assign _zz_183 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_184 = ($signed(_zz_185) + $signed(_zz_188)); + assign _zz_185 = ($signed(_zz_186) + $signed(_zz_187)); + assign _zz_186 = execute_SRC1; + assign _zz_187 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_188 = (execute_SRC_USE_SUB_LESS ? _zz_189 : _zz_190); + assign _zz_189 = 32'h00000001; + assign _zz_190 = 32'h0; + assign _zz_191 = (_zz_192 >>> 1); + assign _zz_192 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_193 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_194 = execute_INSTRUCTION[31 : 20]; + assign _zz_195 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_196 = (_zz_109 & (~ _zz_197)); + assign _zz_197 = (_zz_109 - 2'b01); + assign _zz_198 = (_zz_111 & (~ _zz_199)); + assign _zz_199 = (_zz_111 - 2'b01); assign _zz_200 = execute_CsrPlugin_writeData[7 : 7]; assign _zz_201 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_202 = 1'b1; - assign _zz_203 = 1'b1; - assign _zz_204 = {_zz_52,_zz_51}; - assign _zz_205 = 32'h0000107f; - assign _zz_206 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_207 = 32'h00002073; - assign _zz_208 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_209 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_210 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_211) == 32'h00000003),{(_zz_212 == _zz_213),{_zz_214,{_zz_215,_zz_216}}}}}}; - assign _zz_211 = 32'h0000505f; - assign _zz_212 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_213 = 32'h00000063; - assign _zz_214 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_215 = ((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033); - assign _zz_216 = {((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013),{((decode_INSTRUCTION & _zz_217) == 32'h00005033),{(_zz_218 == _zz_219),{_zz_220,{_zz_221,_zz_222}}}}}}; - assign _zz_217 = 32'hbe00707f; - assign _zz_218 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_219 = 32'h00000033; - assign _zz_220 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_221 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_222 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); - assign _zz_223 = 32'h10003050; - assign _zz_224 = (decode_INSTRUCTION & 32'h10403050); - assign _zz_225 = 32'h10000050; - assign _zz_226 = ((decode_INSTRUCTION & _zz_233) == 32'h00001050); - assign _zz_227 = ((decode_INSTRUCTION & _zz_234) == 32'h00002050); - assign _zz_228 = {_zz_75,(_zz_235 == _zz_236)}; - assign _zz_229 = 2'b00; - assign _zz_230 = ((_zz_237 == _zz_238) != 1'b0); - assign _zz_231 = (_zz_239 != 1'b0); - assign _zz_232 = {(_zz_240 != _zz_241),{_zz_242,{_zz_243,_zz_244}}}; - assign _zz_233 = 32'h00001050; - assign _zz_234 = 32'h00002050; - assign _zz_235 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_236 = 32'h00000004; - assign _zz_237 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_238 = 32'h00000040; - assign _zz_239 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); - assign _zz_240 = {(_zz_245 == _zz_246),(_zz_247 == _zz_248)}; - assign _zz_241 = 2'b00; - assign _zz_242 = ({_zz_249,_zz_250} != 2'b00); - assign _zz_243 = (_zz_251 != 1'b0); - assign _zz_244 = {(_zz_252 != _zz_253),{_zz_254,{_zz_255,_zz_256}}}; - assign _zz_245 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_246 = 32'h40001010; - assign _zz_247 = (decode_INSTRUCTION & 32'h00007054); - assign _zz_248 = 32'h00001010; - assign _zz_249 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_250 = ((decode_INSTRUCTION & 32'h00003054) == 32'h00001010); - assign _zz_251 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_252 = ((decode_INSTRUCTION & _zz_257) == 32'h00002000); - assign _zz_253 = 1'b0; - assign _zz_254 = ({_zz_258,_zz_259} != 2'b00); - assign _zz_255 = ({_zz_260,_zz_261} != 2'b00); - assign _zz_256 = {(_zz_262 != _zz_263),{_zz_264,{_zz_265,_zz_266}}}; - assign _zz_257 = 32'h00003000; - assign _zz_258 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_259 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_260 = ((decode_INSTRUCTION & _zz_267) == 32'h00000020); - assign _zz_261 = ((decode_INSTRUCTION & _zz_268) == 32'h00000020); - assign _zz_262 = {(_zz_269 == _zz_270),{_zz_271,_zz_272}}; - assign _zz_263 = 3'b000; - assign _zz_264 = ((_zz_273 == _zz_274) != 1'b0); - assign _zz_265 = (_zz_275 != 1'b0); - assign _zz_266 = {(_zz_276 != _zz_277),{_zz_278,{_zz_279,_zz_280}}}; - assign _zz_267 = 32'h00000034; - assign _zz_268 = 32'h00000064; - assign _zz_269 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_270 = 32'h00000040; - assign _zz_271 = ((decode_INSTRUCTION & 32'h00000038) == 32'h0); - assign _zz_272 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); - assign _zz_273 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_274 = 32'h00000020; - assign _zz_275 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); - assign _zz_276 = _zz_74; - assign _zz_277 = 1'b0; - assign _zz_278 = ({_zz_75,{_zz_281,_zz_282}} != 6'h0); - assign _zz_279 = ({_zz_283,_zz_284} != 2'b00); - assign _zz_280 = {(_zz_285 != _zz_286),{_zz_287,{_zz_288,_zz_289}}}; - assign _zz_281 = ((decode_INSTRUCTION & _zz_290) == 32'h00001010); - assign _zz_282 = {(_zz_291 == _zz_292),{_zz_74,{_zz_293,_zz_294}}}; - assign _zz_283 = _zz_73; - assign _zz_284 = ((decode_INSTRUCTION & _zz_295) == 32'h00000020); - assign _zz_285 = {_zz_73,(_zz_296 == _zz_297)}; - assign _zz_286 = 2'b00; - assign _zz_287 = ({_zz_298,_zz_299} != 2'b00); - assign _zz_288 = (_zz_300 != 1'b0); - assign _zz_289 = {(_zz_301 != _zz_302),{_zz_303,{_zz_304,_zz_305}}}; - assign _zz_290 = 32'h00001010; - assign _zz_291 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_292 = 32'h00002010; - assign _zz_293 = (_zz_306 == _zz_307); - assign _zz_294 = (_zz_308 == _zz_309); - assign _zz_295 = 32'h00000070; - assign _zz_296 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_297 = 32'h0; - assign _zz_298 = ((decode_INSTRUCTION & _zz_310) == 32'h00006010); - assign _zz_299 = ((decode_INSTRUCTION & _zz_311) == 32'h00004010); - assign _zz_300 = ((decode_INSTRUCTION & _zz_312) == 32'h00002010); - assign _zz_301 = {_zz_313,{_zz_314,_zz_315}}; - assign _zz_302 = 4'b0000; - assign _zz_303 = (_zz_316 != 1'b0); - assign _zz_304 = (_zz_317 != _zz_318); - assign _zz_305 = {_zz_319,_zz_320}; - assign _zz_306 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_307 = 32'h00000004; - assign _zz_308 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_309 = 32'h0; - assign _zz_310 = 32'h00006014; - assign _zz_311 = 32'h00005014; - assign _zz_312 = 32'h00006014; - assign _zz_313 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_314 = ((decode_INSTRUCTION & _zz_321) == 32'h0); - assign _zz_315 = {(_zz_322 == _zz_323),(_zz_324 == _zz_325)}; - assign _zz_316 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_317 = {(_zz_326 == _zz_327),{_zz_328,_zz_329}}; - assign _zz_318 = 3'b000; - assign _zz_319 = ({_zz_330,_zz_72} != 2'b00); - assign _zz_320 = ({_zz_331,_zz_72} != 2'b00); - assign _zz_321 = 32'h00000018; - assign _zz_322 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_323 = 32'h00002000; - assign _zz_324 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_325 = 32'h00001000; - assign _zz_326 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_327 = 32'h00000040; - assign _zz_328 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_329 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz_330 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_331 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_202 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_203 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_204 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_205 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_206 = 1'b1; + assign _zz_207 = 1'b1; + assign _zz_208 = {_zz_52,_zz_51}; + assign _zz_209 = 32'h0000107f; + assign _zz_210 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_211 = 32'h00002073; + assign _zz_212 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_213 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_214 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_215) == 32'h00000003),{(_zz_216 == _zz_217),{_zz_218,{_zz_219,_zz_220}}}}}}; + assign _zz_215 = 32'h0000505f; + assign _zz_216 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_217 = 32'h00000063; + assign _zz_218 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_219 = ((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033); + assign _zz_220 = {((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013),{((decode_INSTRUCTION & _zz_221) == 32'h00005033),{(_zz_222 == _zz_223),{_zz_224,{_zz_225,_zz_226}}}}}}; + assign _zz_221 = 32'hbe00707f; + assign _zz_222 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_223 = 32'h00000033; + assign _zz_224 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_225 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_226 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_227 = 32'h10003050; + assign _zz_228 = (decode_INSTRUCTION & 32'h10403050); + assign _zz_229 = 32'h10000050; + assign _zz_230 = ((decode_INSTRUCTION & _zz_237) == 32'h00001050); + assign _zz_231 = ((decode_INSTRUCTION & _zz_238) == 32'h00002050); + assign _zz_232 = {_zz_75,(_zz_239 == _zz_240)}; + assign _zz_233 = 2'b00; + assign _zz_234 = ((_zz_241 == _zz_242) != 1'b0); + assign _zz_235 = (_zz_243 != 1'b0); + assign _zz_236 = {(_zz_244 != _zz_245),{_zz_246,{_zz_247,_zz_248}}}; + assign _zz_237 = 32'h00001050; + assign _zz_238 = 32'h00002050; + assign _zz_239 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_240 = 32'h00000004; + assign _zz_241 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_242 = 32'h00000040; + assign _zz_243 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); + assign _zz_244 = {(_zz_249 == _zz_250),(_zz_251 == _zz_252)}; + assign _zz_245 = 2'b00; + assign _zz_246 = ({_zz_253,_zz_254} != 2'b00); + assign _zz_247 = (_zz_255 != 1'b0); + assign _zz_248 = {(_zz_256 != _zz_257),{_zz_258,{_zz_259,_zz_260}}}; + assign _zz_249 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_250 = 32'h40001010; + assign _zz_251 = (decode_INSTRUCTION & 32'h00007054); + assign _zz_252 = 32'h00001010; + assign _zz_253 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_254 = ((decode_INSTRUCTION & 32'h00003054) == 32'h00001010); + assign _zz_255 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_256 = ((decode_INSTRUCTION & _zz_261) == 32'h00002000); + assign _zz_257 = 1'b0; + assign _zz_258 = ({_zz_262,_zz_263} != 2'b00); + assign _zz_259 = ({_zz_264,_zz_265} != 2'b00); + assign _zz_260 = {(_zz_266 != _zz_267),{_zz_268,{_zz_269,_zz_270}}}; + assign _zz_261 = 32'h00003000; + assign _zz_262 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_263 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_264 = ((decode_INSTRUCTION & _zz_271) == 32'h00000020); + assign _zz_265 = ((decode_INSTRUCTION & _zz_272) == 32'h00000020); + assign _zz_266 = {(_zz_273 == _zz_274),{_zz_275,_zz_276}}; + assign _zz_267 = 3'b000; + assign _zz_268 = ((_zz_277 == _zz_278) != 1'b0); + assign _zz_269 = (_zz_279 != 1'b0); + assign _zz_270 = {(_zz_280 != _zz_281),{_zz_282,{_zz_283,_zz_284}}}; + assign _zz_271 = 32'h00000034; + assign _zz_272 = 32'h00000064; + assign _zz_273 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_274 = 32'h00000040; + assign _zz_275 = ((decode_INSTRUCTION & 32'h00000038) == 32'h0); + assign _zz_276 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); + assign _zz_277 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_278 = 32'h00000020; + assign _zz_279 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); + assign _zz_280 = _zz_74; + assign _zz_281 = 1'b0; + assign _zz_282 = ({_zz_75,{_zz_285,_zz_286}} != 6'h0); + assign _zz_283 = ({_zz_287,_zz_288} != 2'b00); + assign _zz_284 = {(_zz_289 != _zz_290),{_zz_291,{_zz_292,_zz_293}}}; + assign _zz_285 = ((decode_INSTRUCTION & _zz_294) == 32'h00001010); + assign _zz_286 = {(_zz_295 == _zz_296),{_zz_74,{_zz_297,_zz_298}}}; + assign _zz_287 = _zz_73; + assign _zz_288 = ((decode_INSTRUCTION & _zz_299) == 32'h00000020); + assign _zz_289 = {_zz_73,(_zz_300 == _zz_301)}; + assign _zz_290 = 2'b00; + assign _zz_291 = ({_zz_302,_zz_303} != 2'b00); + assign _zz_292 = (_zz_304 != 1'b0); + assign _zz_293 = {(_zz_305 != _zz_306),{_zz_307,{_zz_308,_zz_309}}}; + assign _zz_294 = 32'h00001010; + assign _zz_295 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_296 = 32'h00002010; + assign _zz_297 = (_zz_310 == _zz_311); + assign _zz_298 = (_zz_312 == _zz_313); + assign _zz_299 = 32'h00000070; + assign _zz_300 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_301 = 32'h0; + assign _zz_302 = ((decode_INSTRUCTION & _zz_314) == 32'h00006010); + assign _zz_303 = ((decode_INSTRUCTION & _zz_315) == 32'h00004010); + assign _zz_304 = ((decode_INSTRUCTION & _zz_316) == 32'h00002010); + assign _zz_305 = {_zz_317,{_zz_318,_zz_319}}; + assign _zz_306 = 4'b0000; + assign _zz_307 = (_zz_320 != 1'b0); + assign _zz_308 = (_zz_321 != _zz_322); + assign _zz_309 = {_zz_323,_zz_324}; + assign _zz_310 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_311 = 32'h00000004; + assign _zz_312 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_313 = 32'h0; + assign _zz_314 = 32'h00006014; + assign _zz_315 = 32'h00005014; + assign _zz_316 = 32'h00006014; + assign _zz_317 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_318 = ((decode_INSTRUCTION & _zz_325) == 32'h0); + assign _zz_319 = {(_zz_326 == _zz_327),(_zz_328 == _zz_329)}; + assign _zz_320 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_321 = {(_zz_330 == _zz_331),{_zz_332,_zz_333}}; + assign _zz_322 = 3'b000; + assign _zz_323 = ({_zz_334,_zz_72} != 2'b00); + assign _zz_324 = ({_zz_335,_zz_72} != 2'b00); + assign _zz_325 = 32'h00000018; + assign _zz_326 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_327 = 32'h00002000; + assign _zz_328 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_329 = 32'h00001000; + assign _zz_330 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_331 = 32'h00000040; + assign _zz_332 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_333 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz_334 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_335 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); always @ (posedge clk) begin - if(_zz_202) begin - _zz_122 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_206) begin + _zz_126 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_203) begin - _zz_123 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_207) begin + _zz_127 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1217,24 +1211,24 @@ module VexRiscv ( .io_push_payload_error (iBus_rsp_payload_error ), //i .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o - .io_pop_ready (_zz_120 ), //i + .io_pop_ready (_zz_124 ), //i .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o - .io_flush (_zz_121 ), //i + .io_flush (_zz_125 ), //i .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o .clk (clk ), //i .reset (reset ) //i ); always @(*) begin - case(_zz_204) + case(_zz_208) 2'b00 : begin - _zz_124 = CsrPlugin_jumpInterface_payload; + _zz_128 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_124 = DBusSimplePlugin_redoBranch_payload; + _zz_128 = DBusSimplePlugin_redoBranch_payload; end default : begin - _zz_124 = BranchPlugin_jumpInterface_payload; + _zz_128 = BranchPlugin_jumpInterface_payload; end endcase end @@ -1864,7 +1858,7 @@ module VexRiscv ( assign memory_MEMORY_READ_DATA = dBus_rsp_data; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_94; + assign execute_BRANCH_DO = _zz_98; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign execute_REGFILE_WRITE_DATA = _zz_84; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; @@ -1878,18 +1872,18 @@ module VexRiscv ( assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_151[0]; + assign decode_IS_CSR = _zz_155[0]; assign decode_BRANCH_CTRL = _zz_8; assign _zz_9 = _zz_10; assign decode_SHIFT_CTRL = _zz_11; assign _zz_12 = _zz_13; assign decode_ALU_BITWISE_CTRL = _zz_14; assign _zz_15 = _zz_16; - assign decode_SRC_LESS_UNSIGNED = _zz_152[0]; - assign decode_MEMORY_STORE = _zz_153[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_156[0]; + assign decode_MEMORY_STORE = _zz_157[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_154[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_155[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_158[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_159[0]; assign decode_SRC2_CTRL = _zz_17; assign _zz_18 = _zz_19; assign decode_ALU_CTRL = _zz_20; @@ -1911,8 +1905,8 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_CTRL = _zz_29; - assign decode_RS2_USE = _zz_156[0]; - assign decode_RS1_USE = _zz_157[0]; + assign decode_RS2_USE = _zz_160[0]; + assign decode_RS1_USE = _zz_161[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; @@ -1921,10 +1915,10 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin _zz_30 = execute_REGFILE_WRITE_DATA; - if(_zz_125)begin + if(_zz_129)begin _zz_30 = _zz_91; end - if(_zz_126)begin + if(_zz_130)begin _zz_30 = execute_CsrPlugin_readData; end end @@ -1936,8 +1930,8 @@ module VexRiscv ( assign _zz_32 = execute_PC; assign execute_SRC2_CTRL = _zz_33; assign execute_SRC1_CTRL = _zz_34; - assign decode_SRC_USE_SUB_LESS = _zz_158[0]; - assign decode_SRC_ADD_ZERO = _zz_159[0]; + assign decode_SRC_USE_SUB_LESS = _zz_162[0]; + assign decode_SRC_ADD_ZERO = _zz_163[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_35; @@ -1955,13 +1949,13 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_160[0]; + decode_REGFILE_WRITE_VALID = _zz_164[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_205) == 32'h00001073),{(_zz_206 == _zz_207),{_zz_208,{_zz_209,_zz_210}}}}}}} != 20'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_209) == 32'h00001073),{(_zz_210 == _zz_211),{_zz_212,{_zz_213,_zz_214}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin _zz_47 = writeBack_REGFILE_WRITE_DATA; @@ -2004,7 +1998,7 @@ module VexRiscv ( assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_161[0]; + assign decode_MEMORY_ENABLE = _zz_165[0]; always @ (*) begin _zz_48 = memory_FORMAL_PC_NEXT; if(DBusSimplePlugin_redoBranch_valid)begin @@ -2028,7 +2022,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_92 || _zz_93)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2041,7 +2035,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_127)begin + if(_zz_131)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2052,7 +2046,7 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(_zz_127)begin + if(_zz_131)begin decode_arbitration_flushNext = 1'b1; end end @@ -2062,12 +2056,12 @@ module VexRiscv ( if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_125)begin + if(_zz_129)begin if((! execute_LightShifterPlugin_done))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_126)begin + if(_zz_130)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2103,7 +2097,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_128)begin + if(_zz_132)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2126,7 +2120,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_128)begin + if(_zz_132)begin memory_arbitration_flushNext = 1'b1; end end @@ -2143,10 +2137,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_129)begin + if(_zz_133)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_130)begin + if(_zz_134)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2160,10 +2154,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_129)begin + if(_zz_133)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_130)begin + if(_zz_134)begin IBusSimplePlugin_fetcherHalt = 1'b1; end end @@ -2182,21 +2176,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_129)begin + if(_zz_133)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_130)begin + if(_zz_134)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_129)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_133)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_130)begin - case(_zz_131) + if(_zz_134)begin + case(_zz_135) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2212,10 +2206,10 @@ module VexRiscv ( assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); assign _zz_49 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_50 = (_zz_49 & (~ _zz_162)); + assign _zz_50 = (_zz_49 & (~ _zz_166)); assign _zz_51 = _zz_50[1]; assign _zz_52 = _zz_50[2]; - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_124; + assign IBusSimplePlugin_jump_pcLoad_payload = _zz_128; always @ (*) begin IBusSimplePlugin_fetchPc_correction = 1'b0; if(IBusSimplePlugin_fetchPc_redo_valid)begin @@ -2235,7 +2229,7 @@ module VexRiscv ( end always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_164); + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_168); if(IBusSimplePlugin_fetchPc_redo_valid)begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; end @@ -2325,7 +2319,7 @@ module VexRiscv ( assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pending_next = (_zz_165 - _zz_169); + assign IBusSimplePlugin_pending_next = (_zz_169 - _zz_173); assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); always @ (*) begin IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); @@ -2349,8 +2343,8 @@ module VexRiscv ( assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - assign _zz_120 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); - assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_120); + assign _zz_124 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_124); assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; always @ (*) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; @@ -2362,7 +2356,7 @@ module VexRiscv ( assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; always @ (*) begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_132)begin + if(_zz_136)begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; end end @@ -2383,7 +2377,7 @@ module VexRiscv ( assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; always @ (*) begin IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_132)begin + if(_zz_136)begin IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; end end @@ -2442,7 +2436,7 @@ module VexRiscv ( assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_133)begin + if(_zz_137)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end if(memory_ALIGNEMENT_FAULT)begin @@ -2455,18 +2449,18 @@ module VexRiscv ( DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_134)begin + if(_zz_138)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_133)begin + if(_zz_137)begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_174}; + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_178}; end if(! memory_MMU_RSP2_refilling) begin if(memory_MMU_FAULT)begin @@ -2481,7 +2475,7 @@ module VexRiscv ( if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_134)begin + if(_zz_138)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -2555,7 +2549,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_149) + case(_zz_153) 2'b00 : begin writeBack_DBusSimplePlugin_rspFormated = _zz_68; end @@ -2590,7 +2584,7 @@ module VexRiscv ( assign _zz_73 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_74 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); assign _zz_75 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_71 = {(((decode_INSTRUCTION & _zz_223) == 32'h00000050) != 1'b0),{((_zz_224 == _zz_225) != 1'b0),{({_zz_226,_zz_227} != 2'b00),{(_zz_228 != _zz_229),{_zz_230,{_zz_231,_zz_232}}}}}}; + assign _zz_71 = {(((decode_INSTRUCTION & _zz_227) == 32'h00000050) != 1'b0),{((_zz_228 == _zz_229) != 1'b0),{({_zz_230,_zz_231} != 2'b00),{(_zz_232 != _zz_233),{_zz_234,{_zz_235,_zz_236}}}}}}; assign _zz_76 = _zz_71[1 : 0]; assign _zz_46 = _zz_76; assign _zz_77 = _zz_71[6 : 5]; @@ -2610,8 +2604,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_122; - assign decode_RegFilePlugin_rs2Data = _zz_123; + assign decode_RegFilePlugin_rs1Data = _zz_126; + assign decode_RegFilePlugin_rs2Data = _zz_127; always @ (*) begin lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); if(_zz_83)begin @@ -2653,7 +2647,7 @@ module VexRiscv ( _zz_84 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_84 = {31'd0, _zz_175}; + _zz_84 = {31'd0, _zz_179}; end default : begin _zz_84 = execute_SRC_ADD_SUB; @@ -2667,18 +2661,18 @@ module VexRiscv ( _zz_85 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_85 = {29'd0, _zz_176}; + _zz_85 = {29'd0, _zz_180}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_85 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_85 = {27'd0, _zz_177}; + _zz_85 = {27'd0, _zz_181}; end endcase end - assign _zz_86 = _zz_178[11]; + assign _zz_86 = _zz_182[11]; always @ (*) begin _zz_87[19] = _zz_86; _zz_87[18] = _zz_86; @@ -2702,7 +2696,7 @@ module VexRiscv ( _zz_87[0] = _zz_86; end - assign _zz_88 = _zz_179[11]; + assign _zz_88 = _zz_183[11]; always @ (*) begin _zz_89[19] = _zz_88; _zz_89[18] = _zz_88; @@ -2744,7 +2738,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_180; + execute_SrcPlugin_addSub = _zz_184; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -2761,163 +2755,111 @@ module VexRiscv ( _zz_91 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_91 = _zz_187; + _zz_91 = _zz_191; end endcase end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_92 = 1'b0; + if(_zz_94)begin + if((_zz_95 == decode_INSTRUCTION[19 : 15]))begin + _zz_92 = 1'b1; end end - if(_zz_135)begin - if(_zz_136)begin + if(_zz_139)begin + if(_zz_140)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_92 = 1'b1; end end end - if(_zz_137)begin - if(_zz_138)begin + if(_zz_141)begin + if(_zz_142)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_92 = 1'b1; end end end - if(_zz_139)begin - if(_zz_140)begin + if(_zz_143)begin + if(_zz_144)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_92 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_92 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_93 = 1'b0; + if(_zz_94)begin + if((_zz_95 == decode_INSTRUCTION[24 : 20]))begin + _zz_93 = 1'b1; end end - if(_zz_135)begin - if(_zz_136)begin + if(_zz_139)begin + if(_zz_140)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_93 = 1'b1; end end end - if(_zz_137)begin - if(_zz_138)begin + if(_zz_141)begin + if(_zz_142)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_93 = 1'b1; end end end - if(_zz_139)begin - if(_zz_140)begin + if(_zz_143)begin + if(_zz_144)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_93 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_93 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_38 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_37[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_47; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_92 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_92 == 3'b000)) begin - _zz_93 = execute_BranchPlugin_eq; - end else if((_zz_92 == 3'b001)) begin - _zz_93 = (! execute_BranchPlugin_eq); - end else if((((_zz_92 & 3'b101) == 3'b101))) begin - _zz_93 = (! execute_SRC_LESS); + assign _zz_96 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_96 == 3'b000)) begin + _zz_97 = execute_BranchPlugin_eq; + end else if((_zz_96 == 3'b001)) begin + _zz_97 = (! execute_BranchPlugin_eq); + end else if((((_zz_96 & 3'b101) == 3'b101))) begin + _zz_97 = (! execute_SRC_LESS); end else begin - _zz_93 = execute_SRC_LESS; + _zz_97 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_94 = 1'b0; + _zz_98 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_94 = 1'b1; + _zz_98 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_94 = 1'b1; + _zz_98 = 1'b1; end default : begin - _zz_94 = _zz_93; + _zz_98 = _zz_97; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_95 = _zz_189[19]; - always @ (*) begin - _zz_96[10] = _zz_95; - _zz_96[9] = _zz_95; - _zz_96[8] = _zz_95; - _zz_96[7] = _zz_95; - _zz_96[6] = _zz_95; - _zz_96[5] = _zz_95; - _zz_96[4] = _zz_95; - _zz_96[3] = _zz_95; - _zz_96[2] = _zz_95; - _zz_96[1] = _zz_95; - _zz_96[0] = _zz_95; - end - - assign _zz_97 = _zz_190[11]; - always @ (*) begin - _zz_98[19] = _zz_97; - _zz_98[18] = _zz_97; - _zz_98[17] = _zz_97; - _zz_98[16] = _zz_97; - _zz_98[15] = _zz_97; - _zz_98[14] = _zz_97; - _zz_98[13] = _zz_97; - _zz_98[12] = _zz_97; - _zz_98[11] = _zz_97; - _zz_98[10] = _zz_97; - _zz_98[9] = _zz_97; - _zz_98[8] = _zz_97; - _zz_98[7] = _zz_97; - _zz_98[6] = _zz_97; - _zz_98[5] = _zz_97; - _zz_98[4] = _zz_97; - _zz_98[3] = _zz_97; - _zz_98[2] = _zz_97; - _zz_98[1] = _zz_97; - _zz_98[0] = _zz_97; - end - - assign _zz_99 = _zz_191[11]; - always @ (*) begin - _zz_100[18] = _zz_99; - _zz_100[17] = _zz_99; - _zz_100[16] = _zz_99; - _zz_100[15] = _zz_99; - _zz_100[14] = _zz_99; - _zz_100[13] = _zz_99; - _zz_100[12] = _zz_99; - _zz_100[11] = _zz_99; + assign _zz_99 = _zz_193[19]; + always @ (*) begin _zz_100[10] = _zz_99; _zz_100[9] = _zz_99; _zz_100[8] = _zz_99; @@ -2931,21 +2873,68 @@ module VexRiscv ( _zz_100[0] = _zz_99; end + assign _zz_101 = _zz_194[11]; + always @ (*) begin + _zz_102[19] = _zz_101; + _zz_102[18] = _zz_101; + _zz_102[17] = _zz_101; + _zz_102[16] = _zz_101; + _zz_102[15] = _zz_101; + _zz_102[14] = _zz_101; + _zz_102[13] = _zz_101; + _zz_102[12] = _zz_101; + _zz_102[11] = _zz_101; + _zz_102[10] = _zz_101; + _zz_102[9] = _zz_101; + _zz_102[8] = _zz_101; + _zz_102[7] = _zz_101; + _zz_102[6] = _zz_101; + _zz_102[5] = _zz_101; + _zz_102[4] = _zz_101; + _zz_102[3] = _zz_101; + _zz_102[2] = _zz_101; + _zz_102[1] = _zz_101; + _zz_102[0] = _zz_101; + end + + assign _zz_103 = _zz_195[11]; + always @ (*) begin + _zz_104[18] = _zz_103; + _zz_104[17] = _zz_103; + _zz_104[16] = _zz_103; + _zz_104[15] = _zz_103; + _zz_104[14] = _zz_103; + _zz_104[13] = _zz_103; + _zz_104[12] = _zz_103; + _zz_104[11] = _zz_103; + _zz_104[10] = _zz_103; + _zz_104[9] = _zz_103; + _zz_104[8] = _zz_103; + _zz_104[7] = _zz_103; + _zz_104[6] = _zz_103; + _zz_104[5] = _zz_103; + _zz_104[4] = _zz_103; + _zz_104[3] = _zz_103; + _zz_104[2] = _zz_103; + _zz_104[1] = _zz_103; + _zz_104[0] = _zz_103; + end + always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_101 = {{_zz_96,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_105 = {{_zz_100,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_101 = {_zz_98,execute_INSTRUCTION[31 : 20]}; + _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_101 = {{_zz_100,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_105 = {{_zz_104,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_101; + assign execute_BranchPlugin_branch_src2 = _zz_105; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; @@ -2961,18 +2950,18 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_102 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_103 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_104 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_106 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_107 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_108 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_105 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; - assign _zz_106 = _zz_192[0]; - assign _zz_107 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_108 = _zz_194[0]; + assign _zz_109 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; + assign _zz_110 = _zz_196[0]; + assign _zz_111 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_112 = _zz_198[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_127)begin + if(_zz_131)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2992,7 +2981,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_128)begin + if(_zz_132)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3051,7 +3040,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3100,7 +3089,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_141)begin + if(_zz_145)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3119,14 +3108,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_142)begin + if(_zz_146)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_142)begin + if(_zz_146)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3141,14 +3130,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_141)begin + if(_zz_145)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_141)begin + if(_zz_145)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -3157,7 +3146,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_150) + case(_zz_154) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3168,8 +3157,8 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign _zz_110 = (_zz_109 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_110 != 32'h0); + assign _zz_114 = (_zz_113 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_114 != 32'h0); assign _zz_25 = decode_SRC1_CTRL; assign _zz_23 = _zz_46; assign _zz_34 = decode_to_execute_SRC1_CTRL; @@ -3216,69 +3205,69 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_111 = 32'h0; + _zz_115 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_111[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_111[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_111[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_115[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_115[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_115[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_112 = 32'h0; + _zz_116 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_112[11 : 11] = CsrPlugin_mip_MEIP; - _zz_112[7 : 7] = CsrPlugin_mip_MTIP; - _zz_112[3 : 3] = CsrPlugin_mip_MSIP; + _zz_116[11 : 11] = CsrPlugin_mip_MEIP; + _zz_116[7 : 7] = CsrPlugin_mip_MTIP; + _zz_116[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_113 = 32'h0; + _zz_117 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_113[11 : 11] = CsrPlugin_mie_MEIE; - _zz_113[7 : 7] = CsrPlugin_mie_MTIE; - _zz_113[3 : 3] = CsrPlugin_mie_MSIE; + _zz_117[11 : 11] = CsrPlugin_mie_MEIE; + _zz_117[7 : 7] = CsrPlugin_mie_MTIE; + _zz_117[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_114 = 32'h0; + _zz_118 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_114[31 : 0] = CsrPlugin_mepc; + _zz_118[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_115 = 32'h0; + _zz_119 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_115[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_115[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_119[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_119[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_116 = 32'h0; + _zz_120 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_116[31 : 0] = CsrPlugin_mtval; + _zz_120[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_117 = 32'h0; + _zz_121 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_117[31 : 0] = _zz_109; + _zz_121[31 : 0] = _zz_113; end end always @ (*) begin - _zz_118 = 32'h0; + _zz_122 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_118[31 : 0] = _zz_110; + _zz_122[31 : 0] = _zz_114; end end - assign execute_CsrPlugin_readData = (((_zz_111 | _zz_112) | (_zz_113 | _zz_114)) | ((_zz_115 | _zz_116) | (_zz_117 | _zz_118))); + assign execute_CsrPlugin_readData = (((_zz_115 | _zz_116) | (_zz_117 | _zz_118)) | ((_zz_119 | _zz_120) | (_zz_121 | _zz_122))); assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; @@ -3287,7 +3276,7 @@ module VexRiscv ( assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); @@ -3306,19 +3295,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_119 = 4'b0001; + _zz_123 = 4'b0001; end 2'b01 : begin - _zz_119 = 4'b0011; + _zz_123 = 4'b0011; end default : begin - _zz_119 = 4'b1111; + _zz_123 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_119 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_123 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -3332,7 +3321,7 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - assign _zz_121 = 1'b0; + assign _zz_125 = 1'b0; always @ (posedge clk) begin if(reset) begin IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; @@ -3350,7 +3339,7 @@ module VexRiscv ( IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; _zz_83 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_94 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3367,7 +3356,7 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - _zz_109 <= 32'h0; + _zz_113 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; @@ -3449,9 +3438,9 @@ module VexRiscv ( IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_171); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_175); if(IBusSimplePlugin_iBusRsp_flush)begin - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_173); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_177); end `ifndef SYNTHESIS `ifdef FORMAL @@ -3474,8 +3463,8 @@ module VexRiscv ( `endif `endif _zz_83 <= 1'b0; - if(_zz_125)begin - if(_zz_143)begin + if(_zz_129)begin + if(_zz_147)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -3485,7 +3474,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_94 <= (_zz_38 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -3507,14 +3496,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_144)begin - if(_zz_145)begin + if(_zz_148)begin + if(_zz_149)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_146)begin + if(_zz_150)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_147)begin + if(_zz_151)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -3538,7 +3527,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_129)begin + if(_zz_133)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3549,8 +3538,8 @@ module VexRiscv ( end endcase end - if(_zz_130)begin - case(_zz_131) + if(_zz_134)begin + case(_zz_135) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3560,7 +3549,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_104,{_zz_103,_zz_102}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_108,{_zz_107,_zz_106}} != 3'b000) || CsrPlugin_thirdPartyWake); if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -3582,26 +3571,26 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_196[0]; - CsrPlugin_mstatus_MIE <= _zz_197[0]; + CsrPlugin_mstatus_MPIE <= _zz_200[0]; + CsrPlugin_mstatus_MIE <= _zz_201[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_199[0]; - CsrPlugin_mie_MTIE <= _zz_200[0]; - CsrPlugin_mie_MSIE <= _zz_201[0]; + CsrPlugin_mie_MEIE <= _zz_203[0]; + CsrPlugin_mie_MTIE <= _zz_204[0]; + CsrPlugin_mie_MSIE <= _zz_205[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_109 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_113 <= execute_CsrPlugin_writeData[31 : 0]; end end if(iBus_cmd_ready)begin iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; end - if(_zz_148)begin + if(_zz_152)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -3632,13 +3621,12 @@ module VexRiscv ( IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; end - if(_zz_125)begin - if(_zz_143)begin + if(_zz_129)begin + if(_zz_147)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_95 <= _zz_37[11 : 7]; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -3646,33 +3634,33 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_127)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_106 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_106 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_131)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_110 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_110 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_128)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_108 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_108 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_132)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_112 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_112 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_144)begin - if(_zz_145)begin + if(_zz_148)begin + if(_zz_149)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_146)begin + if(_zz_150)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_147)begin + if(_zz_151)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_129)begin + if(_zz_133)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -3868,7 +3856,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_198[0]; + CsrPlugin_mip_MSIP <= _zz_202[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -3885,7 +3873,7 @@ module VexRiscv ( if(iBus_cmd_ready)begin iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; end - if(_zz_148)begin + if(_zz_152)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v index 30baf5c..f1b3c6a 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v @@ -1,6 +1,6 @@ -// Generator : SpinalHDL v1.4.4 git head : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 59f011da0a5ef9d5ed94ef2308e3df290d596e66 +// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -81,30 +81,26 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_122; - wire _zz_123; - reg [31:0] _zz_124; - reg [31:0] _zz_125; - reg [31:0] _zz_126; + wire _zz_126; + wire _zz_127; + reg [31:0] _zz_128; + reg [31:0] _zz_129; + reg [31:0] _zz_130; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; - wire _zz_127; - wire _zz_128; - wire _zz_129; - wire _zz_130; wire _zz_131; wire _zz_132; wire _zz_133; wire _zz_134; wire _zz_135; - wire [1:0] _zz_136; + wire _zz_136; wire _zz_137; wire _zz_138; wire _zz_139; - wire _zz_140; + wire [1:0] _zz_140; wire _zz_141; wire _zz_142; wire _zz_143; @@ -112,19 +108,19 @@ module VexRiscv ( wire _zz_145; wire _zz_146; wire _zz_147; - wire [5:0] _zz_148; + wire _zz_148; wire _zz_149; wire _zz_150; wire _zz_151; - wire _zz_152; + wire [5:0] _zz_152; wire _zz_153; wire _zz_154; - wire [1:0] _zz_155; + wire _zz_155; wire _zz_156; - wire [0:0] _zz_157; - wire [0:0] _zz_158; - wire [0:0] _zz_159; - wire [0:0] _zz_160; + wire _zz_157; + wire _zz_158; + wire [1:0] _zz_159; + wire _zz_160; wire [0:0] _zz_161; wire [0:0] _zz_162; wire [0:0] _zz_163; @@ -133,179 +129,183 @@ module VexRiscv ( wire [0:0] _zz_166; wire [0:0] _zz_167; wire [0:0] _zz_168; - wire [2:0] _zz_169; - wire [2:0] _zz_170; - wire [31:0] _zz_171; - wire [2:0] _zz_172; - wire [0:0] _zz_173; + wire [0:0] _zz_169; + wire [0:0] _zz_170; + wire [0:0] _zz_171; + wire [0:0] _zz_172; + wire [2:0] _zz_173; wire [2:0] _zz_174; - wire [0:0] _zz_175; + wire [31:0] _zz_175; wire [2:0] _zz_176; wire [0:0] _zz_177; wire [2:0] _zz_178; wire [0:0] _zz_179; wire [2:0] _zz_180; - wire [2:0] _zz_181; - wire [0:0] _zz_182; - wire [2:0] _zz_183; - wire [4:0] _zz_184; - wire [11:0] _zz_185; - wire [11:0] _zz_186; - wire [31:0] _zz_187; - wire [31:0] _zz_188; - wire [31:0] _zz_189; - wire [31:0] _zz_190; + wire [0:0] _zz_181; + wire [2:0] _zz_182; + wire [0:0] _zz_183; + wire [2:0] _zz_184; + wire [2:0] _zz_185; + wire [0:0] _zz_186; + wire [2:0] _zz_187; + wire [4:0] _zz_188; + wire [11:0] _zz_189; + wire [11:0] _zz_190; wire [31:0] _zz_191; wire [31:0] _zz_192; wire [31:0] _zz_193; wire [31:0] _zz_194; - wire [32:0] _zz_195; - wire [19:0] _zz_196; - wire [11:0] _zz_197; - wire [11:0] _zz_198; - wire [1:0] _zz_199; - wire [1:0] _zz_200; - wire [1:0] _zz_201; - wire [1:0] _zz_202; - wire [0:0] _zz_203; - wire [0:0] _zz_204; - wire [0:0] _zz_205; - wire [0:0] _zz_206; + wire [31:0] _zz_195; + wire [31:0] _zz_196; + wire [31:0] _zz_197; + wire [31:0] _zz_198; + wire [32:0] _zz_199; + wire [19:0] _zz_200; + wire [11:0] _zz_201; + wire [11:0] _zz_202; + wire [1:0] _zz_203; + wire [1:0] _zz_204; + wire [1:0] _zz_205; + wire [1:0] _zz_206; wire [0:0] _zz_207; wire [0:0] _zz_208; - wire _zz_209; - wire _zz_210; - wire [1:0] _zz_211; - wire [31:0] _zz_212; - wire [31:0] _zz_213; - wire [31:0] _zz_214; - wire _zz_215; - wire [0:0] _zz_216; - wire [12:0] _zz_217; + wire [0:0] _zz_209; + wire [0:0] _zz_210; + wire [0:0] _zz_211; + wire [0:0] _zz_212; + wire _zz_213; + wire _zz_214; + wire [1:0] _zz_215; + wire [31:0] _zz_216; + wire [31:0] _zz_217; wire [31:0] _zz_218; - wire [31:0] _zz_219; - wire [31:0] _zz_220; - wire _zz_221; - wire [0:0] _zz_222; - wire [6:0] _zz_223; + wire _zz_219; + wire [0:0] _zz_220; + wire [12:0] _zz_221; + wire [31:0] _zz_222; + wire [31:0] _zz_223; wire [31:0] _zz_224; - wire [31:0] _zz_225; - wire [31:0] _zz_226; - wire _zz_227; - wire [0:0] _zz_228; - wire [0:0] _zz_229; + wire _zz_225; + wire [0:0] _zz_226; + wire [6:0] _zz_227; + wire [31:0] _zz_228; + wire [31:0] _zz_229; wire [31:0] _zz_230; - wire [31:0] _zz_231; - wire [31:0] _zz_232; - wire _zz_233; - wire [1:0] _zz_234; - wire [1:0] _zz_235; - wire _zz_236; - wire [0:0] _zz_237; - wire [20:0] _zz_238; - wire [31:0] _zz_239; - wire [31:0] _zz_240; - wire [31:0] _zz_241; - wire [31:0] _zz_242; - wire _zz_243; - wire _zz_244; - wire [0:0] _zz_245; - wire [0:0] _zz_246; + wire _zz_231; + wire [0:0] _zz_232; + wire [0:0] _zz_233; + wire [31:0] _zz_234; + wire [31:0] _zz_235; + wire [31:0] _zz_236; + wire _zz_237; + wire [1:0] _zz_238; + wire [1:0] _zz_239; + wire _zz_240; + wire [0:0] _zz_241; + wire [20:0] _zz_242; + wire [31:0] _zz_243; + wire [31:0] _zz_244; + wire [31:0] _zz_245; + wire [31:0] _zz_246; wire _zz_247; - wire [0:0] _zz_248; - wire [17:0] _zz_249; - wire [31:0] _zz_250; + wire _zz_248; + wire [0:0] _zz_249; + wire [0:0] _zz_250; wire _zz_251; - wire _zz_252; - wire [0:0] _zz_253; - wire [0:0] _zz_254; - wire [0:0] _zz_255; - wire [0:0] _zz_256; - wire _zz_257; + wire [0:0] _zz_252; + wire [17:0] _zz_253; + wire [31:0] _zz_254; + wire _zz_255; + wire _zz_256; + wire [0:0] _zz_257; wire [0:0] _zz_258; - wire [14:0] _zz_259; - wire [31:0] _zz_260; - wire [31:0] _zz_261; - wire [31:0] _zz_262; - wire [31:0] _zz_263; + wire [0:0] _zz_259; + wire [0:0] _zz_260; + wire _zz_261; + wire [0:0] _zz_262; + wire [14:0] _zz_263; wire [31:0] _zz_264; - wire [0:0] _zz_265; - wire [0:0] _zz_266; - wire [1:0] _zz_267; - wire [1:0] _zz_268; - wire _zz_269; + wire [31:0] _zz_265; + wire [31:0] _zz_266; + wire [31:0] _zz_267; + wire [31:0] _zz_268; + wire [0:0] _zz_269; wire [0:0] _zz_270; - wire [11:0] _zz_271; - wire [31:0] _zz_272; - wire [31:0] _zz_273; - wire [31:0] _zz_274; - wire [31:0] _zz_275; + wire [1:0] _zz_271; + wire [1:0] _zz_272; + wire _zz_273; + wire [0:0] _zz_274; + wire [11:0] _zz_275; wire [31:0] _zz_276; wire [31:0] _zz_277; - wire _zz_278; - wire [0:0] _zz_279; - wire [0:0] _zz_280; - wire _zz_281; - wire [0:0] _zz_282; + wire [31:0] _zz_278; + wire [31:0] _zz_279; + wire [31:0] _zz_280; + wire [31:0] _zz_281; + wire _zz_282; wire [0:0] _zz_283; - wire _zz_284; - wire [0:0] _zz_285; - wire [8:0] _zz_286; - wire [31:0] _zz_287; - wire [31:0] _zz_288; - wire [31:0] _zz_289; - wire [0:0] _zz_290; - wire [4:0] _zz_291; - wire [1:0] _zz_292; - wire [1:0] _zz_293; - wire _zz_294; - wire [0:0] _zz_295; - wire [5:0] _zz_296; - wire [31:0] _zz_297; - wire [31:0] _zz_298; - wire _zz_299; - wire [0:0] _zz_300; - wire [1:0] _zz_301; + wire [0:0] _zz_284; + wire _zz_285; + wire [0:0] _zz_286; + wire [0:0] _zz_287; + wire _zz_288; + wire [0:0] _zz_289; + wire [8:0] _zz_290; + wire [31:0] _zz_291; + wire [31:0] _zz_292; + wire [31:0] _zz_293; + wire [0:0] _zz_294; + wire [4:0] _zz_295; + wire [1:0] _zz_296; + wire [1:0] _zz_297; + wire _zz_298; + wire [0:0] _zz_299; + wire [5:0] _zz_300; + wire [31:0] _zz_301; wire [31:0] _zz_302; - wire [31:0] _zz_303; - wire _zz_304; - wire [0:0] _zz_305; - wire [0:0] _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire _zz_309; + wire _zz_303; + wire [0:0] _zz_304; + wire [1:0] _zz_305; + wire [31:0] _zz_306; + wire [31:0] _zz_307; + wire _zz_308; + wire [0:0] _zz_309; wire [0:0] _zz_310; - wire [2:0] _zz_311; - wire [31:0] _zz_312; + wire [0:0] _zz_311; + wire [0:0] _zz_312; wire _zz_313; - wire _zz_314; - wire [31:0] _zz_315; + wire [0:0] _zz_314; + wire [2:0] _zz_315; wire [31:0] _zz_316; - wire [31:0] _zz_317; - wire [31:0] _zz_318; + wire _zz_317; + wire _zz_318; wire [31:0] _zz_319; wire [31:0] _zz_320; wire [31:0] _zz_321; - wire [0:0] _zz_322; - wire [2:0] _zz_323; - wire [0:0] _zz_324; - wire [0:0] _zz_325; - wire _zz_326; - wire [0:0] _zz_327; + wire [31:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [0:0] _zz_326; + wire [2:0] _zz_327; wire [0:0] _zz_328; - wire [31:0] _zz_329; - wire [31:0] _zz_330; - wire [31:0] _zz_331; - wire _zz_332; - wire _zz_333; + wire [0:0] _zz_329; + wire _zz_330; + wire [0:0] _zz_331; + wire [0:0] _zz_332; + wire [31:0] _zz_333; wire [31:0] _zz_334; - wire _zz_335; - wire [0:0] _zz_336; - wire [0:0] _zz_337; - wire [0:0] _zz_338; - wire [0:0] _zz_339; + wire [31:0] _zz_335; + wire _zz_336; + wire _zz_337; + wire [31:0] _zz_338; + wire _zz_339; wire [0:0] _zz_340; wire [0:0] _zz_341; + wire [0:0] _zz_342; + wire [0:0] _zz_343; + wire [0:0] _zz_344; + wire [0:0] _zz_345; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -746,28 +746,22 @@ module VexRiscv ( wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; reg [31:0] _zz_91; - reg HazardSimplePlugin_src0Hazard; - reg HazardSimplePlugin_src1Hazard; - wire HazardSimplePlugin_writeBackWrites_valid; - wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; - wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; - reg HazardSimplePlugin_writeBackBuffer_valid; - reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; - reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; - wire HazardSimplePlugin_addr0Match; - wire HazardSimplePlugin_addr1Match; - wire execute_BranchPlugin_eq; - wire [2:0] _zz_92; + reg _zz_92; reg _zz_93; reg _zz_94; + reg [4:0] _zz_95; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_96; + reg _zz_97; + reg _zz_98; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_95; - reg [10:0] _zz_96; - wire _zz_97; - reg [19:0] _zz_98; wire _zz_99; - reg [18:0] _zz_100; - reg [31:0] _zz_101; + reg [10:0] _zz_100; + wire _zz_101; + reg [19:0] _zz_102; + wire _zz_103; + reg [18:0] _zz_104; + reg [31:0] _zz_105; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -789,9 +783,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_102; - wire _zz_103; - wire _zz_104; + wire _zz_106; + wire _zz_107; + wire _zz_108; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -804,10 +798,10 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_105; - wire _zz_106; - wire [1:0] _zz_107; - wire _zz_108; + wire [1:0] _zz_109; + wire _zz_110; + wire [1:0] _zz_111; + wire _zz_112; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -837,8 +831,8 @@ module VexRiscv ( reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_109; - wire [31:0] _zz_110; + reg [31:0] _zz_113; + wire [31:0] _zz_114; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -848,7 +842,7 @@ module VexRiscv ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_111; + reg _zz_115; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -908,7 +902,7 @@ module VexRiscv ( reg execute_to_memory_BRANCH_DO; reg [31:0] execute_to_memory_BRANCH_CALC; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg [2:0] _zz_112; + reg [2:0] _zz_116; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_836; reg execute_CsrPlugin_csr_772; @@ -918,14 +912,14 @@ module VexRiscv ( reg execute_CsrPlugin_csr_835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_113; - reg [31:0] _zz_114; - reg [31:0] _zz_115; - reg [31:0] _zz_116; reg [31:0] _zz_117; reg [31:0] _zz_118; reg [31:0] _zz_119; reg [31:0] _zz_120; + reg [31:0] _zz_121; + reg [31:0] _zz_122; + reg [31:0] _zz_123; + reg [31:0] _zz_124; wire iBus_cmd_m2sPipe_valid; wire iBus_cmd_m2sPipe_ready; wire [31:0] iBus_cmd_m2sPipe_payload_pc; @@ -943,7 +937,7 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_121; + reg [3:0] _zz_125; `ifndef SYNTHESIS reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; @@ -1022,230 +1016,230 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_127 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_128 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_129 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_130 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_131 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_132 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_133 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_134 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_135 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); - assign _zz_136 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_137 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_138 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_139 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_140 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_141 = (1'b1 || (! 1'b1)); - assign _zz_142 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_143 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_144 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_145 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_146 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_147 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_148 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_149 = (! execute_arbitration_isStuckByOthers); - assign _zz_150 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_151 = ((_zz_102 && 1'b1) && (! 1'b0)); - assign _zz_152 = ((_zz_103 && 1'b1) && (! 1'b0)); - assign _zz_153 = ((_zz_104 && 1'b1) && (! 1'b0)); - assign _zz_154 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_155 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_156 = execute_INSTRUCTION[13]; - assign _zz_157 = _zz_71[23 : 23]; - assign _zz_158 = _zz_71[15 : 15]; - assign _zz_159 = _zz_71[12 : 12]; - assign _zz_160 = _zz_71[11 : 11]; - assign _zz_161 = _zz_71[10 : 10]; - assign _zz_162 = _zz_71[26 : 26]; - assign _zz_163 = _zz_71[14 : 14]; - assign _zz_164 = _zz_71[4 : 4]; - assign _zz_165 = _zz_71[2 : 2]; - assign _zz_166 = _zz_71[18 : 18]; - assign _zz_167 = _zz_71[9 : 9]; - assign _zz_168 = _zz_71[3 : 3]; - assign _zz_169 = (_zz_49 - 3'b001); - assign _zz_170 = {IBusSimplePlugin_fetchPc_inc,2'b00}; - assign _zz_171 = {29'd0, _zz_170}; - assign _zz_172 = (IBusSimplePlugin_pending_value + _zz_174); - assign _zz_173 = IBusSimplePlugin_pending_inc; - assign _zz_174 = {2'd0, _zz_173}; - assign _zz_175 = IBusSimplePlugin_pending_dec; - assign _zz_176 = {2'd0, _zz_175}; - assign _zz_177 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_131 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_132 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_133 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_134 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_135 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_136 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_137 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_138 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_139 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); + assign _zz_140 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_141 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); + assign _zz_142 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_143 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_144 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_145 = (1'b1 || (! 1'b1)); + assign _zz_146 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_147 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_148 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_149 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_150 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_151 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_152 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_153 = (! execute_arbitration_isStuckByOthers); + assign _zz_154 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_155 = ((_zz_106 && 1'b1) && (! 1'b0)); + assign _zz_156 = ((_zz_107 && 1'b1) && (! 1'b0)); + assign _zz_157 = ((_zz_108 && 1'b1) && (! 1'b0)); + assign _zz_158 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_159 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_160 = execute_INSTRUCTION[13]; + assign _zz_161 = _zz_71[23 : 23]; + assign _zz_162 = _zz_71[15 : 15]; + assign _zz_163 = _zz_71[12 : 12]; + assign _zz_164 = _zz_71[11 : 11]; + assign _zz_165 = _zz_71[10 : 10]; + assign _zz_166 = _zz_71[26 : 26]; + assign _zz_167 = _zz_71[14 : 14]; + assign _zz_168 = _zz_71[4 : 4]; + assign _zz_169 = _zz_71[2 : 2]; + assign _zz_170 = _zz_71[18 : 18]; + assign _zz_171 = _zz_71[9 : 9]; + assign _zz_172 = _zz_71[3 : 3]; + assign _zz_173 = (_zz_49 - 3'b001); + assign _zz_174 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_175 = {29'd0, _zz_174}; + assign _zz_176 = (IBusSimplePlugin_pending_value + _zz_178); + assign _zz_177 = IBusSimplePlugin_pending_inc; assign _zz_178 = {2'd0, _zz_177}; assign _zz_179 = IBusSimplePlugin_pending_dec; assign _zz_180 = {2'd0, _zz_179}; - assign _zz_181 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_182 = execute_SRC_LESS; - assign _zz_183 = 3'b100; - assign _zz_184 = execute_INSTRUCTION[19 : 15]; - assign _zz_185 = execute_INSTRUCTION[31 : 20]; - assign _zz_186 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_187 = ($signed(_zz_188) + $signed(_zz_191)); - assign _zz_188 = ($signed(_zz_189) + $signed(_zz_190)); - assign _zz_189 = execute_SRC1; - assign _zz_190 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_191 = (execute_SRC_USE_SUB_LESS ? _zz_192 : _zz_193); - assign _zz_192 = 32'h00000001; - assign _zz_193 = 32'h0; - assign _zz_194 = (_zz_195 >>> 1); - assign _zz_195 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_196 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_197 = execute_INSTRUCTION[31 : 20]; - assign _zz_198 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_199 = (_zz_105 & (~ _zz_200)); - assign _zz_200 = (_zz_105 - 2'b01); - assign _zz_201 = (_zz_107 & (~ _zz_202)); - assign _zz_202 = (_zz_107 - 2'b01); - assign _zz_203 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_204 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_205 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_206 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_181 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_182 = {2'd0, _zz_181}; + assign _zz_183 = IBusSimplePlugin_pending_dec; + assign _zz_184 = {2'd0, _zz_183}; + assign _zz_185 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_186 = execute_SRC_LESS; + assign _zz_187 = 3'b100; + assign _zz_188 = execute_INSTRUCTION[19 : 15]; + assign _zz_189 = execute_INSTRUCTION[31 : 20]; + assign _zz_190 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_191 = ($signed(_zz_192) + $signed(_zz_195)); + assign _zz_192 = ($signed(_zz_193) + $signed(_zz_194)); + assign _zz_193 = execute_SRC1; + assign _zz_194 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_195 = (execute_SRC_USE_SUB_LESS ? _zz_196 : _zz_197); + assign _zz_196 = 32'h00000001; + assign _zz_197 = 32'h0; + assign _zz_198 = (_zz_199 >>> 1); + assign _zz_199 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_200 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_201 = execute_INSTRUCTION[31 : 20]; + assign _zz_202 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_203 = (_zz_109 & (~ _zz_204)); + assign _zz_204 = (_zz_109 - 2'b01); + assign _zz_205 = (_zz_111 & (~ _zz_206)); + assign _zz_206 = (_zz_111 - 2'b01); assign _zz_207 = execute_CsrPlugin_writeData[7 : 7]; assign _zz_208 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_209 = 1'b1; - assign _zz_210 = 1'b1; - assign _zz_211 = {_zz_52,_zz_51}; - assign _zz_212 = 32'h0000107f; - assign _zz_213 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_214 = 32'h00002073; - assign _zz_215 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_216 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_217 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_218) == 32'h00000003),{(_zz_219 == _zz_220),{_zz_221,{_zz_222,_zz_223}}}}}}; - assign _zz_218 = 32'h0000505f; - assign _zz_219 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_220 = 32'h00000063; - assign _zz_221 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_222 = ((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033); - assign _zz_223 = {((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013),{((decode_INSTRUCTION & _zz_224) == 32'h00005033),{(_zz_225 == _zz_226),{_zz_227,{_zz_228,_zz_229}}}}}}; - assign _zz_224 = 32'hbe00707f; - assign _zz_225 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_226 = 32'h00000033; - assign _zz_227 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_228 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); - assign _zz_229 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_230 = 32'h10103050; - assign _zz_231 = (decode_INSTRUCTION & 32'h10103050); - assign _zz_232 = 32'h00000050; - assign _zz_233 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); - assign _zz_234 = {(_zz_239 == _zz_240),(_zz_241 == _zz_242)}; - assign _zz_235 = 2'b00; - assign _zz_236 = ({_zz_75,_zz_243} != 2'b00); - assign _zz_237 = (_zz_244 != 1'b0); - assign _zz_238 = {(_zz_245 != _zz_246),{_zz_247,{_zz_248,_zz_249}}}; - assign _zz_239 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_240 = 32'h00001050; - assign _zz_241 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_242 = 32'h00002050; - assign _zz_243 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_244 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_245 = ((decode_INSTRUCTION & _zz_250) == 32'h00005010); - assign _zz_246 = 1'b0; - assign _zz_247 = ({_zz_251,_zz_252} != 2'b00); - assign _zz_248 = ({_zz_253,_zz_254} != 2'b00); - assign _zz_249 = {(_zz_255 != _zz_256),{_zz_257,{_zz_258,_zz_259}}}; - assign _zz_250 = 32'h00007054; - assign _zz_251 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_252 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00001010); - assign _zz_253 = ((decode_INSTRUCTION & _zz_260) == 32'h00000024); - assign _zz_254 = ((decode_INSTRUCTION & _zz_261) == 32'h00001010); - assign _zz_255 = ((decode_INSTRUCTION & _zz_262) == 32'h00001000); - assign _zz_256 = 1'b0; - assign _zz_257 = ((_zz_263 == _zz_264) != 1'b0); - assign _zz_258 = ({_zz_265,_zz_266} != 2'b00); - assign _zz_259 = {(_zz_267 != _zz_268),{_zz_269,{_zz_270,_zz_271}}}; - assign _zz_260 = 32'h00000064; - assign _zz_261 = 32'h00003054; - assign _zz_262 = 32'h00001000; - assign _zz_263 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_264 = 32'h00002000; - assign _zz_265 = ((decode_INSTRUCTION & _zz_272) == 32'h00002000); - assign _zz_266 = ((decode_INSTRUCTION & _zz_273) == 32'h00001000); - assign _zz_267 = {(_zz_274 == _zz_275),(_zz_276 == _zz_277)}; - assign _zz_268 = 2'b00; - assign _zz_269 = ({_zz_278,{_zz_279,_zz_280}} != 3'b000); - assign _zz_270 = (_zz_281 != 1'b0); - assign _zz_271 = {(_zz_282 != _zz_283),{_zz_284,{_zz_285,_zz_286}}}; - assign _zz_272 = 32'h00002010; - assign _zz_273 = 32'h00005000; - assign _zz_274 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_275 = 32'h00000020; - assign _zz_276 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_277 = 32'h00000020; - assign _zz_278 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); - assign _zz_279 = ((decode_INSTRUCTION & _zz_287) == 32'h0); - assign _zz_280 = ((decode_INSTRUCTION & _zz_288) == 32'h00000040); - assign _zz_281 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz_282 = ((decode_INSTRUCTION & _zz_289) == 32'h00000010); - assign _zz_283 = 1'b0; - assign _zz_284 = (_zz_74 != 1'b0); - assign _zz_285 = ({_zz_290,_zz_291} != 6'h0); - assign _zz_286 = {(_zz_292 != _zz_293),{_zz_294,{_zz_295,_zz_296}}}; - assign _zz_287 = 32'h00000038; - assign _zz_288 = 32'h00103040; - assign _zz_289 = 32'h00000010; - assign _zz_290 = _zz_75; - assign _zz_291 = {(_zz_297 == _zz_298),{_zz_299,{_zz_300,_zz_301}}}; - assign _zz_292 = {_zz_73,(_zz_302 == _zz_303)}; - assign _zz_293 = 2'b00; - assign _zz_294 = ({_zz_73,_zz_304} != 2'b00); - assign _zz_295 = ({_zz_305,_zz_306} != 2'b00); - assign _zz_296 = {(_zz_307 != _zz_308),{_zz_309,{_zz_310,_zz_311}}}; - assign _zz_297 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_298 = 32'h00001010; - assign _zz_299 = ((decode_INSTRUCTION & _zz_312) == 32'h00002010); - assign _zz_300 = _zz_74; - assign _zz_301 = {_zz_313,_zz_314}; - assign _zz_302 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_303 = 32'h00000020; - assign _zz_304 = ((decode_INSTRUCTION & _zz_315) == 32'h0); - assign _zz_305 = (_zz_316 == _zz_317); - assign _zz_306 = (_zz_318 == _zz_319); - assign _zz_307 = (_zz_320 == _zz_321); - assign _zz_308 = 1'b0; - assign _zz_309 = ({_zz_322,_zz_323} != 4'b0000); - assign _zz_310 = (_zz_324 != _zz_325); - assign _zz_311 = {_zz_326,{_zz_327,_zz_328}}; - assign _zz_312 = 32'h00002010; - assign _zz_313 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_314 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); - assign _zz_315 = 32'h00000020; - assign _zz_316 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_317 = 32'h00006010; - assign _zz_318 = (decode_INSTRUCTION & 32'h00005014); - assign _zz_319 = 32'h00004010; + assign _zz_209 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_210 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_211 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_212 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_213 = 1'b1; + assign _zz_214 = 1'b1; + assign _zz_215 = {_zz_52,_zz_51}; + assign _zz_216 = 32'h0000107f; + assign _zz_217 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_218 = 32'h00002073; + assign _zz_219 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_220 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_221 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_222) == 32'h00000003),{(_zz_223 == _zz_224),{_zz_225,{_zz_226,_zz_227}}}}}}; + assign _zz_222 = 32'h0000505f; + assign _zz_223 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_224 = 32'h00000063; + assign _zz_225 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_226 = ((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033); + assign _zz_227 = {((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013),{((decode_INSTRUCTION & _zz_228) == 32'h00005033),{(_zz_229 == _zz_230),{_zz_231,{_zz_232,_zz_233}}}}}}; + assign _zz_228 = 32'hbe00707f; + assign _zz_229 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_230 = 32'h00000033; + assign _zz_231 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_232 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_233 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_234 = 32'h10103050; + assign _zz_235 = (decode_INSTRUCTION & 32'h10103050); + assign _zz_236 = 32'h00000050; + assign _zz_237 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz_238 = {(_zz_243 == _zz_244),(_zz_245 == _zz_246)}; + assign _zz_239 = 2'b00; + assign _zz_240 = ({_zz_75,_zz_247} != 2'b00); + assign _zz_241 = (_zz_248 != 1'b0); + assign _zz_242 = {(_zz_249 != _zz_250),{_zz_251,{_zz_252,_zz_253}}}; + assign _zz_243 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_244 = 32'h00001050; + assign _zz_245 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_246 = 32'h00002050; + assign _zz_247 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_248 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_249 = ((decode_INSTRUCTION & _zz_254) == 32'h00005010); + assign _zz_250 = 1'b0; + assign _zz_251 = ({_zz_255,_zz_256} != 2'b00); + assign _zz_252 = ({_zz_257,_zz_258} != 2'b00); + assign _zz_253 = {(_zz_259 != _zz_260),{_zz_261,{_zz_262,_zz_263}}}; + assign _zz_254 = 32'h00007054; + assign _zz_255 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_256 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00001010); + assign _zz_257 = ((decode_INSTRUCTION & _zz_264) == 32'h00000024); + assign _zz_258 = ((decode_INSTRUCTION & _zz_265) == 32'h00001010); + assign _zz_259 = ((decode_INSTRUCTION & _zz_266) == 32'h00001000); + assign _zz_260 = 1'b0; + assign _zz_261 = ((_zz_267 == _zz_268) != 1'b0); + assign _zz_262 = ({_zz_269,_zz_270} != 2'b00); + assign _zz_263 = {(_zz_271 != _zz_272),{_zz_273,{_zz_274,_zz_275}}}; + assign _zz_264 = 32'h00000064; + assign _zz_265 = 32'h00003054; + assign _zz_266 = 32'h00001000; + assign _zz_267 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_268 = 32'h00002000; + assign _zz_269 = ((decode_INSTRUCTION & _zz_276) == 32'h00002000); + assign _zz_270 = ((decode_INSTRUCTION & _zz_277) == 32'h00001000); + assign _zz_271 = {(_zz_278 == _zz_279),(_zz_280 == _zz_281)}; + assign _zz_272 = 2'b00; + assign _zz_273 = ({_zz_282,{_zz_283,_zz_284}} != 3'b000); + assign _zz_274 = (_zz_285 != 1'b0); + assign _zz_275 = {(_zz_286 != _zz_287),{_zz_288,{_zz_289,_zz_290}}}; + assign _zz_276 = 32'h00002010; + assign _zz_277 = 32'h00005000; + assign _zz_278 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_279 = 32'h00000020; + assign _zz_280 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_281 = 32'h00000020; + assign _zz_282 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_283 = ((decode_INSTRUCTION & _zz_291) == 32'h0); + assign _zz_284 = ((decode_INSTRUCTION & _zz_292) == 32'h00000040); + assign _zz_285 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_286 = ((decode_INSTRUCTION & _zz_293) == 32'h00000010); + assign _zz_287 = 1'b0; + assign _zz_288 = (_zz_74 != 1'b0); + assign _zz_289 = ({_zz_294,_zz_295} != 6'h0); + assign _zz_290 = {(_zz_296 != _zz_297),{_zz_298,{_zz_299,_zz_300}}}; + assign _zz_291 = 32'h00000038; + assign _zz_292 = 32'h00103040; + assign _zz_293 = 32'h00000010; + assign _zz_294 = _zz_75; + assign _zz_295 = {(_zz_301 == _zz_302),{_zz_303,{_zz_304,_zz_305}}}; + assign _zz_296 = {_zz_73,(_zz_306 == _zz_307)}; + assign _zz_297 = 2'b00; + assign _zz_298 = ({_zz_73,_zz_308} != 2'b00); + assign _zz_299 = ({_zz_309,_zz_310} != 2'b00); + assign _zz_300 = {(_zz_311 != _zz_312),{_zz_313,{_zz_314,_zz_315}}}; + assign _zz_301 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_302 = 32'h00001010; + assign _zz_303 = ((decode_INSTRUCTION & _zz_316) == 32'h00002010); + assign _zz_304 = _zz_74; + assign _zz_305 = {_zz_317,_zz_318}; + assign _zz_306 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_307 = 32'h00000020; + assign _zz_308 = ((decode_INSTRUCTION & _zz_319) == 32'h0); + assign _zz_309 = (_zz_320 == _zz_321); + assign _zz_310 = (_zz_322 == _zz_323); + assign _zz_311 = (_zz_324 == _zz_325); + assign _zz_312 = 1'b0; + assign _zz_313 = ({_zz_326,_zz_327} != 4'b0000); + assign _zz_314 = (_zz_328 != _zz_329); + assign _zz_315 = {_zz_330,{_zz_331,_zz_332}}; + assign _zz_316 = 32'h00002010; + assign _zz_317 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_318 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_319 = 32'h00000020; assign _zz_320 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_321 = 32'h00002010; - assign _zz_322 = ((decode_INSTRUCTION & _zz_329) == 32'h0); - assign _zz_323 = {(_zz_330 == _zz_331),{_zz_332,_zz_333}}; - assign _zz_324 = ((decode_INSTRUCTION & _zz_334) == 32'h0); - assign _zz_325 = 1'b0; - assign _zz_326 = ({_zz_335,{_zz_336,_zz_337}} != 3'b000); - assign _zz_327 = ({_zz_338,_zz_339} != 2'b00); - assign _zz_328 = ({_zz_340,_zz_341} != 2'b00); - assign _zz_329 = 32'h00000044; - assign _zz_330 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_331 = 32'h0; - assign _zz_332 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_333 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_334 = 32'h00000058; - assign _zz_335 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_336 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_337 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz_338 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_339 = _zz_72; - assign _zz_340 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_341 = _zz_72; + assign _zz_321 = 32'h00006010; + assign _zz_322 = (decode_INSTRUCTION & 32'h00005014); + assign _zz_323 = 32'h00004010; + assign _zz_324 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_325 = 32'h00002010; + assign _zz_326 = ((decode_INSTRUCTION & _zz_333) == 32'h0); + assign _zz_327 = {(_zz_334 == _zz_335),{_zz_336,_zz_337}}; + assign _zz_328 = ((decode_INSTRUCTION & _zz_338) == 32'h0); + assign _zz_329 = 1'b0; + assign _zz_330 = ({_zz_339,{_zz_340,_zz_341}} != 3'b000); + assign _zz_331 = ({_zz_342,_zz_343} != 2'b00); + assign _zz_332 = ({_zz_344,_zz_345} != 2'b00); + assign _zz_333 = 32'h00000044; + assign _zz_334 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_335 = 32'h0; + assign _zz_336 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_337 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_338 = 32'h00000058; + assign _zz_339 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_340 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_341 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz_342 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_343 = _zz_72; + assign _zz_344 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_345 = _zz_72; always @ (posedge clk) begin - if(_zz_209) begin - _zz_124 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_213) begin + _zz_128 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_210) begin - _zz_125 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_214) begin + _zz_129 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1261,24 +1255,24 @@ module VexRiscv ( .io_push_payload_error (iBus_rsp_payload_error ), //i .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o - .io_pop_ready (_zz_122 ), //i + .io_pop_ready (_zz_126 ), //i .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o - .io_flush (_zz_123 ), //i + .io_flush (_zz_127 ), //i .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o .clk (clk ), //i .reset (reset ) //i ); always @(*) begin - case(_zz_211) + case(_zz_215) 2'b00 : begin - _zz_126 = CsrPlugin_jumpInterface_payload; + _zz_130 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_126 = DBusSimplePlugin_redoBranch_payload; + _zz_130 = DBusSimplePlugin_redoBranch_payload; end default : begin - _zz_126 = BranchPlugin_jumpInterface_payload; + _zz_130 = BranchPlugin_jumpInterface_payload; end endcase end @@ -1908,7 +1902,7 @@ module VexRiscv ( assign memory_MEMORY_READ_DATA = dBus_rsp_data; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_94; + assign execute_BRANCH_DO = _zz_98; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign execute_REGFILE_WRITE_DATA = _zz_84; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; @@ -1923,18 +1917,18 @@ module VexRiscv ( assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_157[0]; + assign decode_IS_CSR = _zz_161[0]; assign decode_BRANCH_CTRL = _zz_8; assign _zz_9 = _zz_10; assign decode_SHIFT_CTRL = _zz_11; assign _zz_12 = _zz_13; assign decode_ALU_BITWISE_CTRL = _zz_14; assign _zz_15 = _zz_16; - assign decode_SRC_LESS_UNSIGNED = _zz_158[0]; - assign decode_MEMORY_STORE = _zz_159[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_162[0]; + assign decode_MEMORY_STORE = _zz_163[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_160[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_161[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_164[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_165[0]; assign decode_SRC2_CTRL = _zz_17; assign _zz_18 = _zz_19; assign decode_ALU_CTRL = _zz_20; @@ -1946,7 +1940,7 @@ module VexRiscv ( assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_162[0]; + assign decode_IS_EBREAK = _zz_166[0]; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; @@ -1958,8 +1952,8 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_CTRL = _zz_29; - assign decode_RS2_USE = _zz_163[0]; - assign decode_RS1_USE = _zz_164[0]; + assign decode_RS2_USE = _zz_167[0]; + assign decode_RS1_USE = _zz_168[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; @@ -1968,10 +1962,10 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin _zz_30 = execute_REGFILE_WRITE_DATA; - if(_zz_127)begin + if(_zz_131)begin _zz_30 = _zz_91; end - if(_zz_128)begin + if(_zz_132)begin _zz_30 = execute_CsrPlugin_readData; end end @@ -1983,8 +1977,8 @@ module VexRiscv ( assign _zz_32 = execute_PC; assign execute_SRC2_CTRL = _zz_33; assign execute_SRC1_CTRL = _zz_34; - assign decode_SRC_USE_SUB_LESS = _zz_165[0]; - assign decode_SRC_ADD_ZERO = _zz_166[0]; + assign decode_SRC_USE_SUB_LESS = _zz_169[0]; + assign decode_SRC_ADD_ZERO = _zz_170[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_35; @@ -2002,13 +1996,13 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_167[0]; + decode_REGFILE_WRITE_VALID = _zz_171[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_212) == 32'h00001073),{(_zz_213 == _zz_214),{_zz_215,{_zz_216,_zz_217}}}}}}} != 20'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_216) == 32'h00001073),{(_zz_217 == _zz_218),{_zz_219,{_zz_220,_zz_221}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin _zz_47 = writeBack_REGFILE_WRITE_DATA; @@ -2051,7 +2045,7 @@ module VexRiscv ( assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_168[0]; + assign decode_MEMORY_ENABLE = _zz_172[0]; always @ (*) begin _zz_48 = memory_FORMAL_PC_NEXT; if(DBusSimplePlugin_redoBranch_valid)begin @@ -2071,7 +2065,7 @@ module VexRiscv ( if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_112) + case(_zz_116) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2082,7 +2076,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)))begin + if((decode_arbitration_isValid && (_zz_92 || _zz_93)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2095,7 +2089,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_129)begin + if(_zz_133)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2106,7 +2100,7 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(_zz_129)begin + if(_zz_133)begin decode_arbitration_flushNext = 1'b1; end end @@ -2116,12 +2110,12 @@ module VexRiscv ( if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_127)begin + if(_zz_131)begin if((! execute_LightShifterPlugin_done))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_128)begin + if(_zz_132)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2130,7 +2124,7 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_130)begin + if(_zz_134)begin execute_arbitration_haltByOther = 1'b1; end end @@ -2147,8 +2141,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_130)begin - if(_zz_131)begin + if(_zz_134)begin + if(_zz_135)begin execute_arbitration_flushIt = 1'b1; end end @@ -2159,8 +2153,8 @@ module VexRiscv ( if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_130)begin - if(_zz_131)begin + if(_zz_134)begin + if(_zz_135)begin execute_arbitration_flushNext = 1'b1; end end @@ -2176,7 +2170,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_132)begin + if(_zz_136)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2199,7 +2193,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_132)begin + if(_zz_136)begin memory_arbitration_flushNext = 1'b1; end end @@ -2216,10 +2210,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_133)begin + if(_zz_137)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_134)begin + if(_zz_138)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2233,21 +2227,21 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_133)begin + if(_zz_137)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_134)begin + if(_zz_138)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_130)begin - if(_zz_131)begin + if(_zz_134)begin + if(_zz_135)begin IBusSimplePlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_135)begin + if(_zz_139)begin IBusSimplePlugin_fetcherHalt = 1'b1; end end @@ -2272,21 +2266,21 @@ module VexRiscv ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_133)begin + if(_zz_137)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_134)begin + if(_zz_138)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; - if(_zz_133)begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_137)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_134)begin - case(_zz_136) + if(_zz_138)begin + case(_zz_140) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2320,10 +2314,10 @@ module VexRiscv ( assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); assign _zz_49 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_50 = (_zz_49 & (~ _zz_169)); + assign _zz_50 = (_zz_49 & (~ _zz_173)); assign _zz_51 = _zz_50[1]; assign _zz_52 = _zz_50[2]; - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_126; + assign IBusSimplePlugin_jump_pcLoad_payload = _zz_130; always @ (*) begin IBusSimplePlugin_fetchPc_correction = 1'b0; if(IBusSimplePlugin_fetchPc_redo_valid)begin @@ -2343,7 +2337,7 @@ module VexRiscv ( end always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_171); + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_175); if(IBusSimplePlugin_fetchPc_redo_valid)begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; end @@ -2431,7 +2425,7 @@ module VexRiscv ( assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; - case(_zz_112) + case(_zz_116) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -2446,7 +2440,7 @@ module VexRiscv ( assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pending_next = (_zz_172 - _zz_176); + assign IBusSimplePlugin_pending_next = (_zz_176 - _zz_180); assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); always @ (*) begin IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); @@ -2470,8 +2464,8 @@ module VexRiscv ( assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - assign _zz_122 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); - assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_122); + assign _zz_126 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_126); assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; always @ (*) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; @@ -2483,7 +2477,7 @@ module VexRiscv ( assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; always @ (*) begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_137)begin + if(_zz_141)begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; end end @@ -2504,7 +2498,7 @@ module VexRiscv ( assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; always @ (*) begin IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_137)begin + if(_zz_141)begin IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; end end @@ -2563,7 +2557,7 @@ module VexRiscv ( assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_138)begin + if(_zz_142)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end if(memory_ALIGNEMENT_FAULT)begin @@ -2576,18 +2570,18 @@ module VexRiscv ( DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_139)begin + if(_zz_143)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_138)begin + if(_zz_142)begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_181}; + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_185}; end if(! memory_MMU_RSP2_refilling) begin if(memory_MMU_FAULT)begin @@ -2602,7 +2596,7 @@ module VexRiscv ( if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_139)begin + if(_zz_143)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -2676,7 +2670,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_155) + case(_zz_159) 2'b00 : begin writeBack_DBusSimplePlugin_rspFormated = _zz_68; end @@ -2711,7 +2705,7 @@ module VexRiscv ( assign _zz_73 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); assign _zz_74 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); assign _zz_75 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_71 = {(((decode_INSTRUCTION & _zz_230) == 32'h00100050) != 1'b0),{((_zz_231 == _zz_232) != 1'b0),{(_zz_233 != 1'b0),{(_zz_234 != _zz_235),{_zz_236,{_zz_237,_zz_238}}}}}}; + assign _zz_71 = {(((decode_INSTRUCTION & _zz_234) == 32'h00100050) != 1'b0),{((_zz_235 == _zz_236) != 1'b0),{(_zz_237 != 1'b0),{(_zz_238 != _zz_239),{_zz_240,{_zz_241,_zz_242}}}}}}; assign _zz_76 = _zz_71[1 : 0]; assign _zz_46 = _zz_76; assign _zz_77 = _zz_71[6 : 5]; @@ -2731,8 +2725,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_124; - assign decode_RegFilePlugin_rs2Data = _zz_125; + assign decode_RegFilePlugin_rs1Data = _zz_128; + assign decode_RegFilePlugin_rs2Data = _zz_129; always @ (*) begin lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); if(_zz_83)begin @@ -2774,7 +2768,7 @@ module VexRiscv ( _zz_84 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_84 = {31'd0, _zz_182}; + _zz_84 = {31'd0, _zz_186}; end default : begin _zz_84 = execute_SRC_ADD_SUB; @@ -2788,18 +2782,18 @@ module VexRiscv ( _zz_85 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_85 = {29'd0, _zz_183}; + _zz_85 = {29'd0, _zz_187}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_85 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_85 = {27'd0, _zz_184}; + _zz_85 = {27'd0, _zz_188}; end endcase end - assign _zz_86 = _zz_185[11]; + assign _zz_86 = _zz_189[11]; always @ (*) begin _zz_87[19] = _zz_86; _zz_87[18] = _zz_86; @@ -2823,7 +2817,7 @@ module VexRiscv ( _zz_87[0] = _zz_86; end - assign _zz_88 = _zz_186[11]; + assign _zz_88 = _zz_190[11]; always @ (*) begin _zz_89[19] = _zz_88; _zz_89[18] = _zz_88; @@ -2865,7 +2859,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_187; + execute_SrcPlugin_addSub = _zz_191; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -2882,163 +2876,111 @@ module VexRiscv ( _zz_91 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_91 = _zz_194; + _zz_91 = _zz_198; end endcase end always @ (*) begin - HazardSimplePlugin_src0Hazard = 1'b0; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr0Match)begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_92 = 1'b0; + if(_zz_94)begin + if((_zz_95 == decode_INSTRUCTION[19 : 15]))begin + _zz_92 = 1'b1; end end - if(_zz_140)begin - if(_zz_141)begin + if(_zz_144)begin + if(_zz_145)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_92 = 1'b1; end end end - if(_zz_142)begin - if(_zz_143)begin + if(_zz_146)begin + if(_zz_147)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_92 = 1'b1; end end end - if(_zz_144)begin - if(_zz_145)begin + if(_zz_148)begin + if(_zz_149)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - HazardSimplePlugin_src0Hazard = 1'b1; + _zz_92 = 1'b1; end end end if((! decode_RS1_USE))begin - HazardSimplePlugin_src0Hazard = 1'b0; + _zz_92 = 1'b0; end end always @ (*) begin - HazardSimplePlugin_src1Hazard = 1'b0; - if(HazardSimplePlugin_writeBackBuffer_valid)begin - if(HazardSimplePlugin_addr1Match)begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_93 = 1'b0; + if(_zz_94)begin + if((_zz_95 == decode_INSTRUCTION[24 : 20]))begin + _zz_93 = 1'b1; end end - if(_zz_140)begin - if(_zz_141)begin + if(_zz_144)begin + if(_zz_145)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_93 = 1'b1; end end end - if(_zz_142)begin - if(_zz_143)begin + if(_zz_146)begin + if(_zz_147)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_93 = 1'b1; end end end - if(_zz_144)begin - if(_zz_145)begin + if(_zz_148)begin + if(_zz_149)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - HazardSimplePlugin_src1Hazard = 1'b1; + _zz_93 = 1'b1; end end end if((! decode_RS2_USE))begin - HazardSimplePlugin_src1Hazard = 1'b0; + _zz_93 = 1'b0; end end - assign HazardSimplePlugin_writeBackWrites_valid = (_zz_38 && writeBack_arbitration_isFiring); - assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_37[11 : 7]; - assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_47; - assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); - assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_92 = execute_INSTRUCTION[14 : 12]; + assign _zz_96 = execute_INSTRUCTION[14 : 12]; always @ (*) begin - if((_zz_92 == 3'b000)) begin - _zz_93 = execute_BranchPlugin_eq; - end else if((_zz_92 == 3'b001)) begin - _zz_93 = (! execute_BranchPlugin_eq); - end else if((((_zz_92 & 3'b101) == 3'b101))) begin - _zz_93 = (! execute_SRC_LESS); + if((_zz_96 == 3'b000)) begin + _zz_97 = execute_BranchPlugin_eq; + end else if((_zz_96 == 3'b001)) begin + _zz_97 = (! execute_BranchPlugin_eq); + end else if((((_zz_96 & 3'b101) == 3'b101))) begin + _zz_97 = (! execute_SRC_LESS); end else begin - _zz_93 = execute_SRC_LESS; + _zz_97 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_94 = 1'b0; + _zz_98 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_94 = 1'b1; + _zz_98 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_94 = 1'b1; + _zz_98 = 1'b1; end default : begin - _zz_94 = _zz_93; + _zz_98 = _zz_97; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_95 = _zz_196[19]; + assign _zz_99 = _zz_200[19]; always @ (*) begin - _zz_96[10] = _zz_95; - _zz_96[9] = _zz_95; - _zz_96[8] = _zz_95; - _zz_96[7] = _zz_95; - _zz_96[6] = _zz_95; - _zz_96[5] = _zz_95; - _zz_96[4] = _zz_95; - _zz_96[3] = _zz_95; - _zz_96[2] = _zz_95; - _zz_96[1] = _zz_95; - _zz_96[0] = _zz_95; - end - - assign _zz_97 = _zz_197[11]; - always @ (*) begin - _zz_98[19] = _zz_97; - _zz_98[18] = _zz_97; - _zz_98[17] = _zz_97; - _zz_98[16] = _zz_97; - _zz_98[15] = _zz_97; - _zz_98[14] = _zz_97; - _zz_98[13] = _zz_97; - _zz_98[12] = _zz_97; - _zz_98[11] = _zz_97; - _zz_98[10] = _zz_97; - _zz_98[9] = _zz_97; - _zz_98[8] = _zz_97; - _zz_98[7] = _zz_97; - _zz_98[6] = _zz_97; - _zz_98[5] = _zz_97; - _zz_98[4] = _zz_97; - _zz_98[3] = _zz_97; - _zz_98[2] = _zz_97; - _zz_98[1] = _zz_97; - _zz_98[0] = _zz_97; - end - - assign _zz_99 = _zz_198[11]; - always @ (*) begin - _zz_100[18] = _zz_99; - _zz_100[17] = _zz_99; - _zz_100[16] = _zz_99; - _zz_100[15] = _zz_99; - _zz_100[14] = _zz_99; - _zz_100[13] = _zz_99; - _zz_100[12] = _zz_99; - _zz_100[11] = _zz_99; _zz_100[10] = _zz_99; _zz_100[9] = _zz_99; _zz_100[8] = _zz_99; @@ -3052,21 +2994,68 @@ module VexRiscv ( _zz_100[0] = _zz_99; end + assign _zz_101 = _zz_201[11]; + always @ (*) begin + _zz_102[19] = _zz_101; + _zz_102[18] = _zz_101; + _zz_102[17] = _zz_101; + _zz_102[16] = _zz_101; + _zz_102[15] = _zz_101; + _zz_102[14] = _zz_101; + _zz_102[13] = _zz_101; + _zz_102[12] = _zz_101; + _zz_102[11] = _zz_101; + _zz_102[10] = _zz_101; + _zz_102[9] = _zz_101; + _zz_102[8] = _zz_101; + _zz_102[7] = _zz_101; + _zz_102[6] = _zz_101; + _zz_102[5] = _zz_101; + _zz_102[4] = _zz_101; + _zz_102[3] = _zz_101; + _zz_102[2] = _zz_101; + _zz_102[1] = _zz_101; + _zz_102[0] = _zz_101; + end + + assign _zz_103 = _zz_202[11]; + always @ (*) begin + _zz_104[18] = _zz_103; + _zz_104[17] = _zz_103; + _zz_104[16] = _zz_103; + _zz_104[15] = _zz_103; + _zz_104[14] = _zz_103; + _zz_104[13] = _zz_103; + _zz_104[12] = _zz_103; + _zz_104[11] = _zz_103; + _zz_104[10] = _zz_103; + _zz_104[9] = _zz_103; + _zz_104[8] = _zz_103; + _zz_104[7] = _zz_103; + _zz_104[6] = _zz_103; + _zz_104[5] = _zz_103; + _zz_104[4] = _zz_103; + _zz_104[3] = _zz_103; + _zz_104[2] = _zz_103; + _zz_104[1] = _zz_103; + _zz_104[0] = _zz_103; + end + always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_101 = {{_zz_96,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_105 = {{_zz_100,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_101 = {_zz_98,execute_INSTRUCTION[31 : 20]}; + _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_101 = {{_zz_100,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_105 = {{_zz_104,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_101; + assign execute_BranchPlugin_branch_src2 = _zz_105; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; @@ -3082,18 +3071,18 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_102 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_103 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_104 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_106 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_107 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_108 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_105 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; - assign _zz_106 = _zz_199[0]; - assign _zz_107 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_108 = _zz_201[0]; + assign _zz_109 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; + assign _zz_110 = _zz_203[0]; + assign _zz_111 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_112 = _zz_205[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_129)begin + if(_zz_133)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3113,7 +3102,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_132)begin + if(_zz_136)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3172,7 +3161,7 @@ module VexRiscv ( end always @ (*) begin - CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + CsrPlugin_xtvec_base = 30'h0; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3221,7 +3210,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_146)begin + if(_zz_150)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3240,14 +3229,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_147)begin + if(_zz_151)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_147)begin + if(_zz_151)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3262,14 +3251,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_146)begin + if(_zz_150)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_146)begin + if(_zz_150)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -3278,7 +3267,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_156) + case(_zz_160) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3289,12 +3278,12 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign _zz_110 = (_zz_109 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_110 != 32'h0); + assign _zz_114 = (_zz_113 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_114 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_148) + case(_zz_152) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusSimplePlugin_injectionPort_ready; @@ -3308,7 +3297,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_111))begin + if((! _zz_115))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -3320,7 +3309,7 @@ module VexRiscv ( always @ (*) begin IBusSimplePlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_148) + case(_zz_152) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusSimplePlugin_injectionPort_valid = 1'b1; @@ -3382,7 +3371,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusSimplePlugin_injectionPort_ready = 1'b0; - case(_zz_112) + case(_zz_116) 3'b100 : begin IBusSimplePlugin_injectionPort_ready = 1'b1; end @@ -3392,69 +3381,69 @@ module VexRiscv ( end always @ (*) begin - _zz_113 = 32'h0; + _zz_117 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_113[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_113[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_113[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_117[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_117[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_117[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_114 = 32'h0; + _zz_118 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_114[11 : 11] = CsrPlugin_mip_MEIP; - _zz_114[7 : 7] = CsrPlugin_mip_MTIP; - _zz_114[3 : 3] = CsrPlugin_mip_MSIP; + _zz_118[11 : 11] = CsrPlugin_mip_MEIP; + _zz_118[7 : 7] = CsrPlugin_mip_MTIP; + _zz_118[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_115 = 32'h0; + _zz_119 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_115[11 : 11] = CsrPlugin_mie_MEIE; - _zz_115[7 : 7] = CsrPlugin_mie_MTIE; - _zz_115[3 : 3] = CsrPlugin_mie_MSIE; + _zz_119[11 : 11] = CsrPlugin_mie_MEIE; + _zz_119[7 : 7] = CsrPlugin_mie_MTIE; + _zz_119[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_116 = 32'h0; + _zz_120 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_116[31 : 0] = CsrPlugin_mepc; + _zz_120[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_117 = 32'h0; + _zz_121 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_117[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_117[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_121[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_121[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_118 = 32'h0; + _zz_122 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_118[31 : 0] = CsrPlugin_mtval; + _zz_122[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_119 = 32'h0; + _zz_123 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_119[31 : 0] = _zz_109; + _zz_123[31 : 0] = _zz_113; end end always @ (*) begin - _zz_120 = 32'h0; + _zz_124 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_120[31 : 0] = _zz_110; + _zz_124[31 : 0] = _zz_114; end end - assign execute_CsrPlugin_readData = (((_zz_113 | _zz_114) | (_zz_115 | _zz_116)) | ((_zz_117 | _zz_118) | (_zz_119 | _zz_120))); + assign execute_CsrPlugin_readData = (((_zz_117 | _zz_118) | (_zz_119 | _zz_120)) | ((_zz_121 | _zz_122) | (_zz_123 | _zz_124))); assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; @@ -3463,7 +3452,7 @@ module VexRiscv ( assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + assign iBusWishbone_DAT_MOSI = 32'h0; assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); @@ -3482,19 +3471,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_121 = 4'b0001; + _zz_125 = 4'b0001; end 2'b01 : begin - _zz_121 = 4'b0011; + _zz_125 = 4'b0011; end default : begin - _zz_121 = 4'b1111; + _zz_125 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_121 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_125 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -3508,7 +3497,7 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - assign _zz_123 = 1'b0; + assign _zz_127 = 1'b0; always @ (posedge clk) begin if(reset) begin IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; @@ -3526,7 +3515,7 @@ module VexRiscv ( IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; _zz_83 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_94 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3543,11 +3532,11 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - _zz_109 <= 32'h0; + _zz_113 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_112 <= 3'b000; + _zz_116 <= 3'b000; iBus_cmd_m2sPipe_rValid <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; @@ -3626,9 +3615,9 @@ module VexRiscv ( IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_178); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_182); if(IBusSimplePlugin_iBusRsp_flush)begin - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_180); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_184); end `ifndef SYNTHESIS `ifdef FORMAL @@ -3651,8 +3640,8 @@ module VexRiscv ( `endif `endif _zz_83 <= 1'b0; - if(_zz_127)begin - if(_zz_149)begin + if(_zz_131)begin + if(_zz_153)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -3662,7 +3651,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + _zz_94 <= (_zz_38 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -3684,14 +3673,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_150)begin - if(_zz_151)begin + if(_zz_154)begin + if(_zz_155)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_152)begin + if(_zz_156)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_153)begin + if(_zz_157)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -3715,7 +3704,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_133)begin + if(_zz_137)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3726,8 +3715,8 @@ module VexRiscv ( end endcase end - if(_zz_134)begin - case(_zz_136) + if(_zz_138)begin + case(_zz_140) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3737,7 +3726,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_104,{_zz_103,_zz_102}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_108,{_zz_107,_zz_106}} != 3'b000) || CsrPlugin_thirdPartyWake); if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -3756,25 +3745,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_112) + case(_zz_116) 3'b000 : begin if(IBusSimplePlugin_injectionPort_valid)begin - _zz_112 <= 3'b001; + _zz_116 <= 3'b001; end end 3'b001 : begin - _zz_112 <= 3'b010; + _zz_116 <= 3'b010; end 3'b010 : begin - _zz_112 <= 3'b011; + _zz_116 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_112 <= 3'b100; + _zz_116 <= 3'b100; end end 3'b100 : begin - _zz_112 <= 3'b000; + _zz_116 <= 3'b000; end default : begin end @@ -3782,26 +3771,26 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_203[0]; - CsrPlugin_mstatus_MIE <= _zz_204[0]; + CsrPlugin_mstatus_MPIE <= _zz_207[0]; + CsrPlugin_mstatus_MIE <= _zz_208[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_206[0]; - CsrPlugin_mie_MTIE <= _zz_207[0]; - CsrPlugin_mie_MSIE <= _zz_208[0]; + CsrPlugin_mie_MEIE <= _zz_210[0]; + CsrPlugin_mie_MTIE <= _zz_211[0]; + CsrPlugin_mie_MSIE <= _zz_212[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_109 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_113 <= execute_CsrPlugin_writeData[31 : 0]; end end if(iBus_cmd_ready)begin iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; end - if(_zz_154)begin + if(_zz_158)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -3832,13 +3821,12 @@ module VexRiscv ( IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; end - if(_zz_127)begin - if(_zz_149)begin + if(_zz_131)begin + if(_zz_153)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; - HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + _zz_95 <= _zz_37[11 : 7]; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -3846,33 +3834,33 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_129)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_106 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_106 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_133)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_110 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_110 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_132)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_108 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_108 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_136)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_112 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_112 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_150)begin - if(_zz_151)begin + if(_zz_154)begin + if(_zz_155)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_152)begin + if(_zz_156)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_153)begin + if(_zz_157)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_133)begin + if(_zz_137)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4042,7 +4030,7 @@ module VexRiscv ( if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end - if((_zz_112 != 3'b000))begin + if((_zz_116 != 3'b000))begin _zz_61 <= IBusSimplePlugin_injectionPort_payload; end if((! execute_arbitration_isStuck))begin @@ -4074,7 +4062,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_205[0]; + CsrPlugin_mip_MSIP <= _zz_209[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -4091,7 +4079,7 @@ module VexRiscv ( if(iBus_cmd_ready)begin iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; end - if(_zz_154)begin + if(_zz_158)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; @@ -4109,8 +4097,8 @@ module VexRiscv ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_47; end - _zz_111 <= debug_bus_cmd_payload_address[2]; - if(_zz_130)begin + _zz_115 <= debug_bus_cmd_payload_address[2]; + if(_zz_134)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -4128,7 +4116,7 @@ module VexRiscv ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_148) + case(_zz_152) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -4156,13 +4144,13 @@ module VexRiscv ( end endcase end - if(_zz_130)begin - if(_zz_131)begin + if(_zz_134)begin + if(_zz_135)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_135)begin + if(_zz_139)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end diff --git a/pythondata_cpu_vexriscv/verilog/build.sbt b/pythondata_cpu_vexriscv/verilog/build.sbt index 5e90117..6664b26 100644 --- a/pythondata_cpu_vexriscv/verilog/build.sbt +++ b/pythondata_cpu_vexriscv/verilog/build.sbt @@ -1,4 +1,4 @@ -val spinalVersion = "1.4.2" +val spinalVersion = "1.4.3" lazy val root = (project in file(".")). settings( @@ -8,10 +8,12 @@ lazy val root = (project in file(".")). version := "0.1.0-SNAPSHOT" )), name := "VexRiscvOnWishbone", - scalacOptions += s"-Xplugin:${new File(baseDirectory.value + s"/ext/SpinalHDL/idslplugin/target/scala-2.11/spinalhdl-idsl-plugin_2.11-$spinalVersion.jar")}", - scalacOptions += s"-Xplugin-require:idsl-plugin", + libraryDependencies ++= Seq( + compilerPlugin("com.github.spinalhdl" % "spinalhdl-idsl-plugin_2.11" % spinalVersion) + ), + scalacOptions += s"-Xplugin-require:idsl-plugin" ).dependsOn(vexRiscv) -lazy val vexRiscv = RootProject(file("./ext/VexRiscv")) +lazy val vexRiscv = RootProject(file("ext/VexRiscv")) fork := true diff --git a/pythondata_cpu_vexriscv/verilog/ext/VexRiscv b/pythondata_cpu_vexriscv/verilog/ext/VexRiscv index 06b7a91..ec50730 160000 --- a/pythondata_cpu_vexriscv/verilog/ext/VexRiscv +++ b/pythondata_cpu_vexriscv/verilog/ext/VexRiscv @@ -1 +1 @@ -Subproject commit 06b7a91de4b288345d9be82324975c19a6ea1136 +Subproject commit ec507308e7e5fc8ab6265590c98b8c40127296af From 767476cae91f564ec9eab25516eb1664b04c1224 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Tue, 6 Apr 2021 17:04:05 -0700 Subject: [PATCH 10/30] Update CFU instr. encoding to match spec (update vex submodule too). Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/ext/VexRiscv | 2 +- .../src/main/scala/vexriscv/GenCoreDefault.scala | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/ext/VexRiscv b/pythondata_cpu_vexriscv/verilog/ext/VexRiscv index ec50730..21d24eb 160000 --- a/pythondata_cpu_vexriscv/verilog/ext/VexRiscv +++ b/pythondata_cpu_vexriscv/verilog/ext/VexRiscv @@ -1 +1 @@ -Subproject commit ec507308e7e5fc8ab6265590c98b8c40127296af +Subproject commit 21d24eb07fad16fd671b3d4668d302cbaa4549a7 diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index f83d70d..1e12d0b 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -208,16 +208,23 @@ object GenCoreDefault{ stageCount = 1, allowZeroLatency = true, encodings = List( + // CFU R-type CfuPluginEncoding ( instruction = M"-------------------------0001011", - functionId = List(31 downto 12), + functionId = List(31 downto 25, 14 downto 12), input2Kind = CfuPlugin.Input2Kind.RS + ), + // CFU I-type + CfuPluginEncoding ( + instruction = M"-----------------000-----0101011", + functionId = List(23 downto 20), + input2Kind = CfuPlugin.Input2Kind.IMM_I ) ), busParameter = CfuBusParameter( CFU_VERSION = 0, CFU_INTERFACE_ID_W = 0, - CFU_FUNCTION_ID_W = 20, + CFU_FUNCTION_ID_W = 10, CFU_REORDER_ID_W = 0, CFU_REQ_RESP_ID_W = 0, CFU_STATE_INDEX_NUM = 0, From eafff82697ae47892bb4654e4bb7d282a4b9807c Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Tue, 6 Apr 2021 21:31:38 -0700 Subject: [PATCH 11/30] Match CFU spec; function_id now 10b {funct7,funct3}. Rebuilt just the CFU-enabled Vex Verilogs. Signed-off-by: Tim Callahan --- .../verilog/VexRiscv_FullCfu.v | 2928 +++++++++-------- .../verilog/VexRiscv_FullCfuDebug.v | 2782 ++++++++-------- .../main/scala/vexriscv/GenCoreDefault.scala | 5 +- .../verilog/wrapVexRiscv_FullCfu.v | 2 +- .../verilog/wrapVexRiscv_FullCfuDebug.v | 2 +- 5 files changed, 2892 insertions(+), 2827 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index 29f4f6f..094c87d 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : 767476cae91f564ec9eab25516eb1664b04c1224 `define Input2Kind_defaultEncoding_type [0:0] @@ -54,7 +54,7 @@ module VexRiscv_inner ( input softwareInterrupt, output CfuPlugin_bus_cmd_valid, input CfuPlugin_bus_cmd_ready, - output [19:0] CfuPlugin_bus_cmd_payload_function_id, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, input CfuPlugin_bus_rsp_valid, @@ -87,7 +87,6 @@ module VexRiscv_inner ( input clk, input reset ); - wire _zz_217; wire _zz_218; wire _zz_219; wire _zz_220; @@ -95,16 +94,16 @@ module VexRiscv_inner ( wire _zz_222; wire _zz_223; wire _zz_224; - reg _zz_225; - wire _zz_226; - wire [31:0] _zz_227; - wire _zz_228; - wire [31:0] _zz_229; - reg _zz_230; - wire _zz_231; + wire _zz_225; + reg _zz_226; + wire _zz_227; + wire [31:0] _zz_228; + wire _zz_229; + wire [31:0] _zz_230; + reg _zz_231; wire _zz_232; - wire [31:0] _zz_233; - wire _zz_234; + wire _zz_233; + wire [31:0] _zz_234; wire _zz_235; wire _zz_236; wire _zz_237; @@ -112,12 +111,14 @@ module VexRiscv_inner ( wire _zz_239; wire _zz_240; wire _zz_241; - wire [3:0] _zz_242; - wire _zz_243; + wire _zz_242; + wire [3:0] _zz_243; wire _zz_244; - reg [31:0] _zz_245; + wire _zz_245; reg [31:0] _zz_246; reg [31:0] _zz_247; + reg [31:0] _zz_248; + reg [9:0] _zz_249; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -150,8 +151,6 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_248; - wire _zz_249; wire _zz_250; wire _zz_251; wire _zz_252; @@ -165,9 +164,9 @@ module VexRiscv_inner ( wire _zz_260; wire _zz_261; wire _zz_262; - wire [1:0] _zz_263; + wire _zz_263; wire _zz_264; - wire _zz_265; + wire [1:0] _zz_265; wire _zz_266; wire _zz_267; wire _zz_268; @@ -176,9 +175,9 @@ module VexRiscv_inner ( wire _zz_271; wire _zz_272; wire _zz_273; - wire [1:0] _zz_274; + wire _zz_274; wire _zz_275; - wire _zz_276; + wire [1:0] _zz_276; wire _zz_277; wire _zz_278; wire _zz_279; @@ -186,23 +185,23 @@ module VexRiscv_inner ( wire _zz_281; wire _zz_282; wire _zz_283; - wire [1:0] _zz_284; + wire _zz_284; wire _zz_285; wire [1:0] _zz_286; - wire [51:0] _zz_287; - wire [51:0] _zz_288; + wire _zz_287; + wire [1:0] _zz_288; wire [51:0] _zz_289; - wire [32:0] _zz_290; + wire [51:0] _zz_290; wire [51:0] _zz_291; - wire [49:0] _zz_292; + wire [32:0] _zz_292; wire [51:0] _zz_293; wire [49:0] _zz_294; wire [51:0] _zz_295; - wire [32:0] _zz_296; - wire [31:0] _zz_297; + wire [49:0] _zz_296; + wire [51:0] _zz_297; wire [32:0] _zz_298; - wire [0:0] _zz_299; - wire [0:0] _zz_300; + wire [31:0] _zz_299; + wire [32:0] _zz_300; wire [0:0] _zz_301; wire [0:0] _zz_302; wire [0:0] _zz_303; @@ -219,270 +218,276 @@ module VexRiscv_inner ( wire [0:0] _zz_314; wire [0:0] _zz_315; wire [0:0] _zz_316; - wire [3:0] _zz_317; - wire [2:0] _zz_318; - wire [31:0] _zz_319; - wire [11:0] _zz_320; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire [3:0] _zz_319; + wire [2:0] _zz_320; wire [31:0] _zz_321; - wire [19:0] _zz_322; - wire [11:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [19:0] _zz_326; - wire [11:0] _zz_327; - wire [2:0] _zz_328; - wire [2:0] _zz_329; - wire [0:0] _zz_330; + wire [11:0] _zz_322; + wire [31:0] _zz_323; + wire [19:0] _zz_324; + wire [11:0] _zz_325; + wire [31:0] _zz_326; + wire [31:0] _zz_327; + wire [19:0] _zz_328; + wire [11:0] _zz_329; + wire [2:0] _zz_330; wire [2:0] _zz_331; - wire [4:0] _zz_332; - wire [11:0] _zz_333; - wire [11:0] _zz_334; - wire [31:0] _zz_335; - wire [31:0] _zz_336; + wire [0:0] _zz_332; + wire [2:0] _zz_333; + wire [4:0] _zz_334; + wire [11:0] _zz_335; + wire [11:0] _zz_336; wire [31:0] _zz_337; wire [31:0] _zz_338; wire [31:0] _zz_339; wire [31:0] _zz_340; wire [31:0] _zz_341; - wire [11:0] _zz_342; - wire [19:0] _zz_343; + wire [31:0] _zz_342; + wire [31:0] _zz_343; wire [11:0] _zz_344; - wire [31:0] _zz_345; - wire [31:0] _zz_346; + wire [19:0] _zz_345; + wire [11:0] _zz_346; wire [31:0] _zz_347; - wire [11:0] _zz_348; - wire [19:0] _zz_349; + wire [31:0] _zz_348; + wire [31:0] _zz_349; wire [11:0] _zz_350; - wire [2:0] _zz_351; - wire [1:0] _zz_352; - wire [1:0] _zz_353; + wire [19:0] _zz_351; + wire [11:0] _zz_352; + wire [2:0] _zz_353; wire [1:0] _zz_354; wire [1:0] _zz_355; - wire [19:0] _zz_356; - wire [11:0] _zz_357; - wire [65:0] _zz_358; - wire [65:0] _zz_359; - wire [31:0] _zz_360; - wire [31:0] _zz_361; - wire [0:0] _zz_362; - wire [5:0] _zz_363; - wire [32:0] _zz_364; - wire [31:0] _zz_365; - wire [31:0] _zz_366; + wire [1:0] _zz_356; + wire [1:0] _zz_357; + wire [9:0] _zz_358; + wire [3:0] _zz_359; + wire [7:0] _zz_360; + wire [65:0] _zz_361; + wire [65:0] _zz_362; + wire [31:0] _zz_363; + wire [31:0] _zz_364; + wire [0:0] _zz_365; + wire [5:0] _zz_366; wire [32:0] _zz_367; - wire [32:0] _zz_368; - wire [32:0] _zz_369; + wire [31:0] _zz_368; + wire [31:0] _zz_369; wire [32:0] _zz_370; - wire [0:0] _zz_371; + wire [32:0] _zz_371; wire [32:0] _zz_372; - wire [0:0] _zz_373; - wire [32:0] _zz_374; - wire [0:0] _zz_375; - wire [31:0] _zz_376; - wire [0:0] _zz_377; + wire [32:0] _zz_373; + wire [0:0] _zz_374; + wire [32:0] _zz_375; + wire [0:0] _zz_376; + wire [32:0] _zz_377; wire [0:0] _zz_378; - wire [0:0] _zz_379; + wire [31:0] _zz_379; wire [0:0] _zz_380; wire [0:0] _zz_381; wire [0:0] _zz_382; wire [0:0] _zz_383; - wire [26:0] _zz_384; - wire _zz_385; - wire _zz_386; - wire [1:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire _zz_391; - wire [0:0] _zz_392; - wire [14:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire _zz_397; - wire [0:0] _zz_398; - wire [8:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire [31:0] _zz_402; - wire _zz_403; - wire [0:0] _zz_404; - wire [2:0] _zz_405; + wire [0:0] _zz_384; + wire [0:0] _zz_385; + wire [0:0] _zz_386; + wire [26:0] _zz_387; + wire _zz_388; + wire _zz_389; + wire [1:0] _zz_390; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire [31:0] _zz_393; + wire _zz_394; + wire [0:0] _zz_395; + wire [15:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire [31:0] _zz_399; + wire _zz_400; + wire [0:0] _zz_401; + wire [9:0] _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire [31:0] _zz_405; wire _zz_406; - wire _zz_407; - wire _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; + wire [0:0] _zz_407; + wire [3:0] _zz_408; + wire _zz_409; + wire _zz_410; wire _zz_411; - wire _zz_412; - wire [0:0] _zz_413; - wire [26:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; + wire [31:0] _zz_412; + wire [31:0] _zz_413; + wire _zz_414; + wire [0:0] _zz_415; + wire [0:0] _zz_416; + wire _zz_417; wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire [1:0] _zz_420; - wire [1:0] _zz_421; + wire [27:0] _zz_419; + wire [31:0] _zz_420; + wire [31:0] _zz_421; wire _zz_422; - wire [0:0] _zz_423; - wire [21:0] _zz_424; - wire [31:0] _zz_425; - wire [31:0] _zz_426; - wire [31:0] _zz_427; + wire [1:0] _zz_423; + wire [1:0] _zz_424; + wire _zz_425; + wire [0:0] _zz_426; + wire [22:0] _zz_427; wire [31:0] _zz_428; wire [31:0] _zz_429; wire [31:0] _zz_430; - wire [0:0] _zz_431; - wire [0:0] _zz_432; - wire [2:0] _zz_433; - wire [2:0] _zz_434; - wire _zz_435; - wire [0:0] _zz_436; - wire [18:0] _zz_437; - wire [31:0] _zz_438; + wire [31:0] _zz_431; + wire _zz_432; + wire _zz_433; + wire [1:0] _zz_434; + wire [1:0] _zz_435; + wire _zz_436; + wire [0:0] _zz_437; + wire [19:0] _zz_438; wire [31:0] _zz_439; wire [31:0] _zz_440; wire [31:0] _zz_441; - wire _zz_442; + wire [31:0] _zz_442; wire _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; + wire [0:0] _zz_444; + wire [0:0] _zz_445; wire _zz_446; wire [0:0] _zz_447; wire [0:0] _zz_448; wire _zz_449; wire [0:0] _zz_450; - wire [15:0] _zz_451; + wire [16:0] _zz_451; wire [31:0] _zz_452; - wire _zz_453; - wire _zz_454; - wire _zz_455; - wire [2:0] _zz_456; - wire [2:0] _zz_457; - wire _zz_458; + wire [31:0] _zz_453; + wire [31:0] _zz_454; + wire [31:0] _zz_455; + wire [31:0] _zz_456; + wire [0:0] _zz_457; + wire [0:0] _zz_458; wire [0:0] _zz_459; - wire [12:0] _zz_460; + wire [0:0] _zz_460; wire _zz_461; - wire _zz_462; - wire _zz_463; - wire [0:0] _zz_464; - wire [2:0] _zz_465; - wire _zz_466; - wire [5:0] _zz_467; - wire [5:0] _zz_468; - wire _zz_469; + wire [0:0] _zz_462; + wire [13:0] _zz_463; + wire [31:0] _zz_464; + wire [31:0] _zz_465; + wire [31:0] _zz_466; + wire _zz_467; + wire [0:0] _zz_468; + wire [0:0] _zz_469; wire [0:0] _zz_470; - wire [9:0] _zz_471; - wire [31:0] _zz_472; - wire [31:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [0:0] _zz_479; + wire [3:0] _zz_471; + wire [0:0] _zz_472; + wire [0:0] _zz_473; + wire _zz_474; + wire [0:0] _zz_475; + wire [10:0] _zz_476; + wire [31:0] _zz_477; + wire [31:0] _zz_478; + wire [31:0] _zz_479; wire [31:0] _zz_480; - wire _zz_481; - wire [0:0] _zz_482; - wire [3:0] _zz_483; + wire [31:0] _zz_481; + wire _zz_482; + wire [0:0] _zz_483; wire [0:0] _zz_484; - wire [3:0] _zz_485; - wire [5:0] _zz_486; - wire [5:0] _zz_487; - wire _zz_488; - wire [0:0] _zz_489; - wire [7:0] _zz_490; - wire [31:0] _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; + wire _zz_485; + wire [0:0] _zz_486; + wire [3:0] _zz_487; + wire [0:0] _zz_488; + wire [3:0] _zz_489; + wire [6:0] _zz_490; + wire [6:0] _zz_491; + wire _zz_492; + wire [0:0] _zz_493; + wire [7:0] _zz_494; wire [31:0] _zz_495; wire [31:0] _zz_496; wire [31:0] _zz_497; wire [31:0] _zz_498; - wire [0:0] _zz_499; - wire [1:0] _zz_500; - wire _zz_501; - wire [0:0] _zz_502; - wire [1:0] _zz_503; - wire [0:0] _zz_504; - wire [3:0] _zz_505; + wire [31:0] _zz_499; + wire [31:0] _zz_500; + wire [31:0] _zz_501; + wire [31:0] _zz_502; + wire [0:0] _zz_503; + wire [1:0] _zz_504; + wire _zz_505; wire [0:0] _zz_506; - wire [0:0] _zz_507; - wire [1:0] _zz_508; - wire [1:0] _zz_509; - wire _zz_510; + wire [1:0] _zz_507; + wire [0:0] _zz_508; + wire [4:0] _zz_509; + wire [0:0] _zz_510; wire [0:0] _zz_511; - wire [5:0] _zz_512; - wire [31:0] _zz_513; - wire [31:0] _zz_514; - wire _zz_515; - wire _zz_516; + wire [1:0] _zz_512; + wire [1:0] _zz_513; + wire _zz_514; + wire [0:0] _zz_515; + wire [5:0] _zz_516; wire [31:0] _zz_517; wire [31:0] _zz_518; - wire [31:0] _zz_519; + wire _zz_519; wire _zz_520; - wire _zz_521; + wire [31:0] _zz_521; wire [31:0] _zz_522; wire [31:0] _zz_523; wire _zz_524; - wire [0:0] _zz_525; - wire [1:0] _zz_526; + wire _zz_525; + wire [31:0] _zz_526; wire [31:0] _zz_527; - wire [31:0] _zz_528; - wire _zz_529; - wire _zz_530; - wire [0:0] _zz_531; - wire [0:0] _zz_532; + wire _zz_528; + wire [0:0] _zz_529; + wire [2:0] _zz_530; + wire [31:0] _zz_531; + wire [31:0] _zz_532; wire _zz_533; - wire [0:0] _zz_534; - wire [3:0] _zz_535; - wire [31:0] _zz_536; - wire [31:0] _zz_537; - wire [31:0] _zz_538; - wire [31:0] _zz_539; + wire _zz_534; + wire [0:0] _zz_535; + wire [0:0] _zz_536; + wire _zz_537; + wire [0:0] _zz_538; + wire [3:0] _zz_539; wire [31:0] _zz_540; wire [31:0] _zz_541; wire [31:0] _zz_542; - wire _zz_543; - wire _zz_544; + wire [31:0] _zz_543; + wire [31:0] _zz_544; wire [31:0] _zz_545; wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire [0:0] _zz_549; - wire [2:0] _zz_550; - wire [0:0] _zz_551; - wire [0:0] _zz_552; - wire _zz_553; - wire [0:0] _zz_554; - wire [1:0] _zz_555; - wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire _zz_559; - wire _zz_560; + wire [0:0] _zz_547; + wire [0:0] _zz_548; + wire [31:0] _zz_549; + wire [31:0] _zz_550; + wire [31:0] _zz_551; + wire [31:0] _zz_552; + wire [0:0] _zz_553; + wire [2:0] _zz_554; + wire [0:0] _zz_555; + wire [0:0] _zz_556; + wire _zz_557; + wire [0:0] _zz_558; + wire [1:0] _zz_559; + wire [31:0] _zz_560; wire [31:0] _zz_561; - wire _zz_562; - wire [0:0] _zz_563; - wire [0:0] _zz_564; - wire [0:0] _zz_565; - wire [0:0] _zz_566; - wire [1:0] _zz_567; - wire [1:0] _zz_568; + wire [31:0] _zz_562; + wire [31:0] _zz_563; + wire [31:0] _zz_564; + wire _zz_565; + wire _zz_566; + wire [31:0] _zz_567; + wire _zz_568; wire [0:0] _zz_569; wire [0:0] _zz_570; - wire [31:0] _zz_571; - wire [31:0] _zz_572; - wire [31:0] _zz_573; - wire [31:0] _zz_574; - wire [31:0] _zz_575; - wire [31:0] _zz_576; - wire _zz_577; - wire _zz_578; - wire _zz_579; + wire [0:0] _zz_571; + wire [0:0] _zz_572; + wire [1:0] _zz_573; + wire [1:0] _zz_574; + wire [0:0] _zz_575; + wire [0:0] _zz_576; + wire [31:0] _zz_577; + wire [31:0] _zz_578; + wire [31:0] _zz_579; wire [31:0] _zz_580; + wire [31:0] _zz_581; + wire [31:0] _zz_582; + wire _zz_583; + wire _zz_584; + wire _zz_585; + wire [31:0] _zz_586; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -491,8 +496,6 @@ module VexRiscv_inner ( wire [31:0] execute_MUL_LL; wire writeBack_CfuPlugin_CFU_IN_FLIGHT; wire execute_CfuPlugin_CFU_IN_FLIGHT; - wire [31:0] execute_BRANCH_CALC; - wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; wire [1:0] memory_MEMORY_ADDRESS_LOW; @@ -507,10 +510,11 @@ module VexRiscv_inner ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_ENCODING; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; wire `Input2Kind_defaultEncoding_type _zz_1; wire `Input2Kind_defaultEncoding_type _zz_2; wire `Input2Kind_defaultEncoding_type _zz_3; + wire [0:0] decode_CfuPlugin_CFU_ENCODING; wire decode_CfuPlugin_CFU_ENABLE; wire `EnvCtrlEnum_defaultEncoding_type _zz_4; wire `EnvCtrlEnum_defaultEncoding_type _zz_5; @@ -571,8 +575,9 @@ module VexRiscv_inner ( reg _zz_30; reg _zz_31; wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_ENCODING; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; wire `Input2Kind_defaultEncoding_type _zz_32; + wire [0:0] execute_CfuPlugin_CFU_ENCODING; wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; @@ -583,8 +588,8 @@ module VexRiscv_inner ( wire `EnvCtrlEnum_defaultEncoding_type _zz_34; wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_35; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; @@ -782,7 +787,7 @@ module VexRiscv_inner ( wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; + reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; reg CsrPlugin_inWfi /* verilator public */ ; @@ -941,20 +946,21 @@ module VexRiscv_inner ( wire _zz_91; reg [31:0] _zz_92; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [33:0] _zz_93; + wire [34:0] _zz_93; wire _zz_94; wire _zz_95; wire _zz_96; wire _zz_97; wire _zz_98; - wire `Src1CtrlEnum_defaultEncoding_type _zz_99; - wire `AluCtrlEnum_defaultEncoding_type _zz_100; - wire `Src2CtrlEnum_defaultEncoding_type _zz_101; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_102; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_103; - wire `BranchCtrlEnum_defaultEncoding_type _zz_104; - wire `EnvCtrlEnum_defaultEncoding_type _zz_105; - wire `Input2Kind_defaultEncoding_type _zz_106; + wire _zz_99; + wire `Src1CtrlEnum_defaultEncoding_type _zz_100; + wire `AluCtrlEnum_defaultEncoding_type _zz_101; + wire `Src2CtrlEnum_defaultEncoding_type _zz_102; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; + wire `BranchCtrlEnum_defaultEncoding_type _zz_105; + wire `EnvCtrlEnum_defaultEncoding_type _zz_106; + wire `Input2Kind_defaultEncoding_type _zz_107; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -962,52 +968,52 @@ module VexRiscv_inner ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_107; + reg _zz_108; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_108; reg [31:0] _zz_109; - wire _zz_110; - reg [19:0] _zz_111; - wire _zz_112; - reg [19:0] _zz_113; - reg [31:0] _zz_114; + reg [31:0] _zz_110; + wire _zz_111; + reg [19:0] _zz_112; + wire _zz_113; + reg [19:0] _zz_114; + reg [31:0] _zz_115; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_115; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_116; - reg _zz_117; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_117; reg _zz_118; reg _zz_119; - reg [4:0] _zz_120; - reg [31:0] _zz_121; - wire _zz_122; + reg _zz_120; + reg [4:0] _zz_121; + reg [31:0] _zz_122; wire _zz_123; wire _zz_124; wire _zz_125; wire _zz_126; wire _zz_127; + wire _zz_128; wire execute_BranchPlugin_eq; - wire [2:0] _zz_128; - reg _zz_129; + wire [2:0] _zz_129; reg _zz_130; - wire _zz_131; - reg [19:0] _zz_132; - wire _zz_133; - reg [10:0] _zz_134; - wire _zz_135; - reg [18:0] _zz_136; - reg _zz_137; + reg _zz_131; + wire _zz_132; + reg [19:0] _zz_133; + wire _zz_134; + reg [10:0] _zz_135; + wire _zz_136; + reg [18:0] _zz_137; + reg _zz_138; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_138; - reg [19:0] _zz_139; - wire _zz_140; - reg [10:0] _zz_141; - wire _zz_142; - reg [18:0] _zz_143; + wire _zz_139; + reg [19:0] _zz_140; + wire _zz_141; + reg [10:0] _zz_142; + wire _zz_143; + reg [18:0] _zz_144; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1029,9 +1035,9 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_144; wire _zz_145; wire _zz_146; + wire _zz_147; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1044,10 +1050,10 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_147; - wire _zz_148; - wire [1:0] _zz_149; - wire _zz_150; + wire [1:0] _zz_148; + wire _zz_149; + wire [1:0] _zz_150; + wire _zz_151; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1076,7 +1082,6 @@ module VexRiscv_inner ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_151; reg [31:0] _zz_152; reg [31:0] _zz_153; reg [31:0] _zz_154; @@ -1092,13 +1097,15 @@ module VexRiscv_inner ( reg [31:0] _zz_164; reg [31:0] _zz_165; reg [31:0] _zz_166; + reg [31:0] _zz_167; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; - wire [19:0] execute_CfuPlugin_functionsIds_0; - wire _zz_167; - reg [19:0] _zz_168; - reg [31:0] _zz_169; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire [9:0] execute_CfuPlugin_functionsIds_1; + wire _zz_168; + reg [23:0] _zz_169; + reg [31:0] _zz_170; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1130,18 +1137,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_170; + wire [31:0] _zz_171; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_171; - wire _zz_172; + wire [31:0] _zz_172; wire _zz_173; - reg [32:0] _zz_174; + wire _zz_174; + reg [32:0] _zz_175; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_175; - wire [31:0] _zz_176; + reg [31:0] _zz_176; + wire [31:0] _zz_177; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1179,7 +1186,8 @@ module VexRiscv_inner ( reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_ENCODING; + reg [0:0] decode_to_execute_CfuPlugin_CFU_ENCODING; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; reg decode_to_execute_IS_MUL; reg execute_to_memory_IS_MUL; reg memory_to_writeBack_IS_MUL; @@ -1198,8 +1206,6 @@ module VexRiscv_inner ( reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_BRANCH_DO; - reg [31:0] execute_to_memory_BRANCH_CALC; reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; reg [31:0] execute_to_memory_MUL_LL; @@ -1248,7 +1254,6 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_177; reg [31:0] _zz_178; reg [31:0] _zz_179; reg [31:0] _zz_180; @@ -1279,19 +1284,20 @@ module VexRiscv_inner ( reg [31:0] _zz_205; reg [31:0] _zz_206; reg [31:0] _zz_207; - reg [2:0] _zz_208; - reg _zz_209; + reg [31:0] _zz_208; + reg [2:0] _zz_209; + reg _zz_210; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_210; - wire _zz_211; + reg [2:0] _zz_211; wire _zz_212; wire _zz_213; wire _zz_214; wire _zz_215; - reg _zz_216; + wire _zz_216; + reg _zz_217; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; + reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; reg [39:0] _zz_3_string; @@ -1327,7 +1333,7 @@ module VexRiscv_inner ( reg [95:0] _zz_27_string; reg [95:0] _zz_28_string; reg [95:0] _zz_29_string; - reg [39:0] execute_CfuPlugin_CFU_ENCODING_string; + reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] _zz_32_string; reg [39:0] memory_ENV_CTRL_string; reg [39:0] _zz_33_string; @@ -1359,14 +1365,14 @@ module VexRiscv_inner ( reg [95:0] _zz_56_string; reg [31:0] decode_BRANCH_CTRL_string; reg [31:0] _zz_58_string; - reg [95:0] _zz_99_string; - reg [63:0] _zz_100_string; - reg [23:0] _zz_101_string; - reg [39:0] _zz_102_string; - reg [71:0] _zz_103_string; - reg [31:0] _zz_104_string; - reg [39:0] _zz_105_string; + reg [95:0] _zz_100_string; + reg [63:0] _zz_101_string; + reg [23:0] _zz_102_string; + reg [39:0] _zz_103_string; + reg [71:0] _zz_104_string; + reg [31:0] _zz_105_string; reg [39:0] _zz_106_string; + reg [39:0] _zz_107_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1377,353 +1383,357 @@ module VexRiscv_inner ( reg [39:0] decode_to_execute_ENV_CTRL_string; reg [39:0] execute_to_memory_ENV_CTRL_string; reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [39:0] decode_to_execute_CfuPlugin_CFU_ENCODING_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; `endif (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_248 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_249 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_250 = 1'b1; - assign _zz_251 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_252 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_254 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_255 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_256 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_257 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_260 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_264 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_265 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_266 = (1'b0 || (! 1'b1)); - assign _zz_267 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_268 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_270 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_271 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_272 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_273 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_274 = execute_INSTRUCTION[13 : 12]; - assign _zz_275 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_276 = (! memory_arbitration_isStuck); - assign _zz_277 = (iBus_cmd_valid || (_zz_208 != 3'b000)); - assign _zz_278 = (_zz_244 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_280 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_281 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_282 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_285 = execute_INSTRUCTION[13]; + assign _zz_250 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_251 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_252 = 1'b1; + assign _zz_253 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_254 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_255 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_256 = ((_zz_223 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_257 = ((_zz_223 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_258 = ((_zz_223 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_259 = ((_zz_223 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_260 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_261 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_262 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_263 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_264 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_265 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_266 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_267 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_268 = (1'b0 || (! 1'b1)); + assign _zz_269 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_270 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_271 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_272 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_273 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_274 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_275 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_276 = execute_INSTRUCTION[13 : 12]; + assign _zz_277 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_278 = (! memory_arbitration_isStuck); + assign _zz_279 = (iBus_cmd_valid || (_zz_209 != 3'b000)); + assign _zz_280 = (_zz_245 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_281 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_282 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_283 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_284 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_285 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); - assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); - assign _zz_289 = 52'h0; - assign _zz_290 = {1'b0,memory_MUL_LL}; - assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; - assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; - assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_287 = execute_INSTRUCTION[13]; + assign _zz_288 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_289 = ($signed(_zz_290) + $signed(_zz_295)); + assign _zz_290 = ($signed(_zz_291) + $signed(_zz_293)); + assign _zz_291 = 52'h0; + assign _zz_292 = {1'b0,memory_MUL_LL}; + assign _zz_293 = {{19{_zz_292[32]}}, _zz_292}; + assign _zz_294 = ({16'd0,memory_MUL_LH} <<< 16); assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; - assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_297 = _zz_296[31 : 0]; - assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_299 = _zz_93[33 : 33]; - assign _zz_300 = _zz_93[32 : 32]; - assign _zz_301 = _zz_93[31 : 31]; - assign _zz_302 = _zz_93[30 : 30]; - assign _zz_303 = _zz_93[28 : 28]; - assign _zz_304 = _zz_93[25 : 25]; - assign _zz_305 = _zz_93[17 : 17]; - assign _zz_306 = _zz_93[16 : 16]; - assign _zz_307 = _zz_93[13 : 13]; - assign _zz_308 = _zz_93[12 : 12]; - assign _zz_309 = _zz_93[11 : 11]; - assign _zz_310 = _zz_93[15 : 15]; - assign _zz_311 = _zz_93[5 : 5]; - assign _zz_312 = _zz_93[3 : 3]; - assign _zz_313 = _zz_93[20 : 20]; - assign _zz_314 = _zz_93[10 : 10]; - assign _zz_315 = _zz_93[4 : 4]; - assign _zz_316 = _zz_93[0 : 0]; - assign _zz_317 = (_zz_61 - 4'b0001); - assign _zz_318 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_319 = {29'd0, _zz_318}; - assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_321 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_324 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_325 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_326 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_328 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_329 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_330 = execute_SRC_LESS; - assign _zz_331 = 3'b100; - assign _zz_332 = execute_INSTRUCTION[19 : 15]; - assign _zz_333 = execute_INSTRUCTION[31 : 20]; - assign _zz_334 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_335 = ($signed(_zz_336) + $signed(_zz_339)); - assign _zz_336 = ($signed(_zz_337) + $signed(_zz_338)); - assign _zz_337 = execute_SRC1; - assign _zz_338 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_339 = (execute_SRC_USE_SUB_LESS ? _zz_340 : _zz_341); - assign _zz_340 = 32'h00000001; - assign _zz_341 = 32'h0; - assign _zz_342 = execute_INSTRUCTION[31 : 20]; - assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_345 = {_zz_132,execute_INSTRUCTION[31 : 20]}; - assign _zz_346 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_347 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_348 = execute_INSTRUCTION[31 : 20]; - assign _zz_349 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_351 = 3'b100; - assign _zz_352 = (_zz_147 & (~ _zz_353)); - assign _zz_353 = (_zz_147 - 2'b01); - assign _zz_354 = (_zz_149 & (~ _zz_355)); - assign _zz_355 = (_zz_149 - 2'b01); - assign _zz_356 = execute_INSTRUCTION[31 : 12]; - assign _zz_357 = execute_INSTRUCTION[31 : 20]; - assign _zz_358 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_359 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_360 = writeBack_MUL_LOW[31 : 0]; - assign _zz_361 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_362 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_363 = {5'd0, _zz_362}; - assign _zz_364 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_365 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_366 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_367 = {_zz_170,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_368 = _zz_369; - assign _zz_369 = _zz_370; - assign _zz_370 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_171) : _zz_171)} + _zz_372); - assign _zz_371 = memory_DivPlugin_div_needRevert; - assign _zz_372 = {32'd0, _zz_371}; - assign _zz_373 = _zz_173; - assign _zz_374 = {32'd0, _zz_373}; - assign _zz_375 = _zz_172; - assign _zz_376 = {31'd0, _zz_375}; - assign _zz_377 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_378 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_380 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_381 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_296 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_297 = {{2{_zz_296[49]}}, _zz_296}; + assign _zz_298 = ($signed(_zz_300) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_299 = _zz_298[31 : 0]; + assign _zz_300 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_301 = _zz_93[34 : 34]; + assign _zz_302 = _zz_93[33 : 33]; + assign _zz_303 = _zz_93[32 : 32]; + assign _zz_304 = _zz_93[31 : 31]; + assign _zz_305 = _zz_93[28 : 28]; + assign _zz_306 = _zz_93[25 : 25]; + assign _zz_307 = _zz_93[17 : 17]; + assign _zz_308 = _zz_93[16 : 16]; + assign _zz_309 = _zz_93[13 : 13]; + assign _zz_310 = _zz_93[12 : 12]; + assign _zz_311 = _zz_93[11 : 11]; + assign _zz_312 = _zz_93[15 : 15]; + assign _zz_313 = _zz_93[5 : 5]; + assign _zz_314 = _zz_93[3 : 3]; + assign _zz_315 = _zz_93[20 : 20]; + assign _zz_316 = _zz_93[10 : 10]; + assign _zz_317 = _zz_93[4 : 4]; + assign _zz_318 = _zz_93[0 : 0]; + assign _zz_319 = (_zz_61 - 4'b0001); + assign _zz_320 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_321 = {29'd0, _zz_320}; + assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_323 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_324 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_325 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_326 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_327 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_329 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_330 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_331 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_332 = execute_SRC_LESS; + assign _zz_333 = 3'b100; + assign _zz_334 = execute_INSTRUCTION[19 : 15]; + assign _zz_335 = execute_INSTRUCTION[31 : 20]; + assign _zz_336 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_337 = ($signed(_zz_338) + $signed(_zz_341)); + assign _zz_338 = ($signed(_zz_339) + $signed(_zz_340)); + assign _zz_339 = execute_SRC1; + assign _zz_340 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_341 = (execute_SRC_USE_SUB_LESS ? _zz_342 : _zz_343); + assign _zz_342 = 32'h00000001; + assign _zz_343 = 32'h0; + assign _zz_344 = execute_INSTRUCTION[31 : 20]; + assign _zz_345 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_346 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_347 = {_zz_133,execute_INSTRUCTION[31 : 20]}; + assign _zz_348 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_349 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_350 = execute_INSTRUCTION[31 : 20]; + assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_353 = 3'b100; + assign _zz_354 = (_zz_148 & (~ _zz_355)); + assign _zz_355 = (_zz_148 - 2'b01); + assign _zz_356 = (_zz_150 & (~ _zz_357)); + assign _zz_357 = (_zz_150 - 2'b01); + assign _zz_358 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_359 = execute_INSTRUCTION[23 : 20]; + assign _zz_360 = execute_INSTRUCTION[31 : 24]; + assign _zz_361 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_362 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_363 = writeBack_MUL_LOW[31 : 0]; + assign _zz_364 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_365 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_366 = {5'd0, _zz_365}; + assign _zz_367 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_368 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_369 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_370 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_371 = _zz_372; + assign _zz_372 = _zz_373; + assign _zz_373 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_375); + assign _zz_374 = memory_DivPlugin_div_needRevert; + assign _zz_375 = {32'd0, _zz_374}; + assign _zz_376 = _zz_174; + assign _zz_377 = {32'd0, _zz_376}; + assign _zz_378 = _zz_173; + assign _zz_379 = {31'd0, _zz_378}; + assign _zz_380 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_381 = execute_CsrPlugin_writeData[3 : 3]; assign _zz_382 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_383 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_384 = (iBus_cmd_payload_address >>> 5); - assign _zz_385 = 1'b1; - assign _zz_386 = 1'b1; - assign _zz_387 = {_zz_65,_zz_64}; - assign _zz_388 = 32'h0000106f; - assign _zz_389 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_390 = 32'h00001073; - assign _zz_391 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_392 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_393 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_394) == 32'h00000003),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; - assign _zz_394 = 32'h0000207f; - assign _zz_395 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_396 = 32'h00000003; - assign _zz_397 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_398 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_399 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_400) == 32'h00005013),{(_zz_401 == _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; - assign _zz_400 = 32'hbc00707f; - assign _zz_401 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_402 = 32'h00001013; - assign _zz_403 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_405 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_406 = decode_INSTRUCTION[31]; - assign _zz_407 = decode_INSTRUCTION[31]; - assign _zz_408 = decode_INSTRUCTION[7]; - assign _zz_409 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_410 = 32'h02004020; - assign _zz_411 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_412 = (_zz_97 != 1'b0); - assign _zz_413 = (((decode_INSTRUCTION & _zz_415) == 32'h00000050) != 1'b0); - assign _zz_414 = {((_zz_416 == _zz_417) != 1'b0),{({_zz_418,_zz_419} != 2'b00),{(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}}}; - assign _zz_415 = 32'h00203050; - assign _zz_416 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_417 = 32'h00000050; - assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00001050); - assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00002050); - assign _zz_420 = {_zz_96,(_zz_427 == _zz_428)}; - assign _zz_421 = 2'b00; - assign _zz_422 = ((_zz_429 == _zz_430) != 1'b0); - assign _zz_423 = ({_zz_431,_zz_432} != 2'b00); - assign _zz_424 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; - assign _zz_425 = 32'h00001050; - assign _zz_426 = 32'h00002050; - assign _zz_427 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_428 = 32'h00000004; - assign _zz_429 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_430 = 32'h00000040; - assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h00005010); - assign _zz_432 = ((decode_INSTRUCTION & _zz_439) == 32'h00005020); - assign _zz_433 = {(_zz_440 == _zz_441),{_zz_442,_zz_443}}; - assign _zz_434 = 3'b000; - assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); - assign _zz_436 = (_zz_446 != 1'b0); - assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; - assign _zz_438 = 32'h00007034; - assign _zz_439 = 32'h02007064; - assign _zz_440 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_441 = 32'h40001010; - assign _zz_442 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_443 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_445 = 32'h00000024; - assign _zz_446 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_447 = ((decode_INSTRUCTION & _zz_452) == 32'h00002000); + assign _zz_383 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_384 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_385 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_386 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_387 = (iBus_cmd_payload_address >>> 5); + assign _zz_388 = 1'b1; + assign _zz_389 = 1'b1; + assign _zz_390 = {_zz_65,_zz_64}; + assign _zz_391 = 32'h0000106f; + assign _zz_392 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_393 = 32'h00001073; + assign _zz_394 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_395 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_396 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_397) == 32'h00000003),{(_zz_398 == _zz_399),{_zz_400,{_zz_401,_zz_402}}}}}}; + assign _zz_397 = 32'h0000207f; + assign _zz_398 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_399 = 32'h00000003; + assign _zz_400 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_401 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_402 = {((decode_INSTRUCTION & 32'h00007077) == 32'h00000023),{((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_403) == 32'h0000500f),{(_zz_404 == _zz_405),{_zz_406,{_zz_407,_zz_408}}}}}}; + assign _zz_403 = 32'h01f0707f; + assign _zz_404 = (decode_INSTRUCTION & 32'hbc00707f); + assign _zz_405 = 32'h00005013; + assign _zz_406 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); + assign _zz_407 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_408 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}}; + assign _zz_409 = decode_INSTRUCTION[31]; + assign _zz_410 = decode_INSTRUCTION[31]; + assign _zz_411 = decode_INSTRUCTION[7]; + assign _zz_412 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_413 = 32'h02004020; + assign _zz_414 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_415 = _zz_98; + assign _zz_416 = 1'b0; + assign _zz_417 = (_zz_98 != 1'b0); + assign _zz_418 = (_zz_96 != 1'b0); + assign _zz_419 = {((_zz_420 == _zz_421) != 1'b0),{(_zz_422 != 1'b0),{(_zz_423 != _zz_424),{_zz_425,{_zz_426,_zz_427}}}}}; + assign _zz_420 = (decode_INSTRUCTION & 32'h00203050); + assign _zz_421 = 32'h00000050; + assign _zz_422 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050); + assign _zz_423 = {(_zz_428 == _zz_429),(_zz_430 == _zz_431)}; + assign _zz_424 = 2'b00; + assign _zz_425 = ({_zz_97,_zz_432} != 2'b00); + assign _zz_426 = (_zz_433 != 1'b0); + assign _zz_427 = {(_zz_434 != _zz_435),{_zz_436,{_zz_437,_zz_438}}}; + assign _zz_428 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_429 = 32'h00001050; + assign _zz_430 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_431 = 32'h00002050; + assign _zz_432 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_433 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_434 = {(_zz_439 == _zz_440),(_zz_441 == _zz_442)}; + assign _zz_435 = 2'b00; + assign _zz_436 = ({_zz_443,{_zz_444,_zz_445}} != 3'b000); + assign _zz_437 = (_zz_446 != 1'b0); + assign _zz_438 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; + assign _zz_439 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_440 = 32'h00005010; + assign _zz_441 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_442 = 32'h00005020; + assign _zz_443 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz_444 = ((decode_INSTRUCTION & _zz_452) == 32'h00001010); + assign _zz_445 = ((decode_INSTRUCTION & _zz_453) == 32'h00001010); + assign _zz_446 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_447 = ((decode_INSTRUCTION & _zz_454) == 32'h00001000); assign _zz_448 = 1'b0; - assign _zz_449 = ({_zz_453,_zz_454} != 2'b00); - assign _zz_450 = (_zz_455 != 1'b0); - assign _zz_451 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; - assign _zz_452 = 32'h00003000; - assign _zz_453 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_454 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_455 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_456 = {_zz_97,{_zz_461,_zz_462}}; - assign _zz_457 = 3'b000; - assign _zz_458 = ({_zz_463,{_zz_464,_zz_465}} != 5'h0); - assign _zz_459 = (_zz_466 != 1'b0); - assign _zz_460 = {(_zz_467 != _zz_468),{_zz_469,{_zz_470,_zz_471}}}; - assign _zz_461 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); - assign _zz_462 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); - assign _zz_463 = ((decode_INSTRUCTION & _zz_474) == 32'h00002040); - assign _zz_464 = (_zz_475 == _zz_476); - assign _zz_465 = {_zz_477,{_zz_478,_zz_479}}; - assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000020); - assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; - assign _zz_468 = 6'h0; - assign _zz_469 = ({_zz_484,_zz_485} != 5'h0); - assign _zz_470 = (_zz_486 != _zz_487); - assign _zz_471 = {_zz_488,{_zz_489,_zz_490}}; - assign _zz_472 = 32'h00000034; - assign _zz_473 = 32'h00000064; - assign _zz_474 = 32'h00002040; - assign _zz_475 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_476 = 32'h00001040; - assign _zz_477 = ((decode_INSTRUCTION & _zz_491) == 32'h00000040); - assign _zz_478 = (_zz_492 == _zz_493); - assign _zz_479 = (_zz_494 == _zz_495); - assign _zz_480 = 32'h00000020; - assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00000008); - assign _zz_482 = (_zz_497 == _zz_498); - assign _zz_483 = {_zz_95,{_zz_499,_zz_500}}; - assign _zz_484 = _zz_95; - assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; - assign _zz_486 = {_zz_96,{_zz_504,_zz_505}}; - assign _zz_487 = 6'h0; - assign _zz_488 = ({_zz_506,_zz_507} != 2'b00); - assign _zz_489 = (_zz_508 != _zz_509); - assign _zz_490 = {_zz_510,{_zz_511,_zz_512}}; - assign _zz_491 = 32'h00000050; - assign _zz_492 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_493 = 32'h00000040; - assign _zz_494 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_495 = 32'h0; - assign _zz_496 = 32'h00000008; - assign _zz_497 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_498 = 32'h00000040; - assign _zz_499 = (_zz_513 == _zz_514); - assign _zz_500 = {_zz_515,_zz_516}; - assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00002010); - assign _zz_502 = (_zz_518 == _zz_519); - assign _zz_503 = {_zz_520,_zz_521}; - assign _zz_504 = (_zz_522 == _zz_523); - assign _zz_505 = {_zz_524,{_zz_525,_zz_526}}; - assign _zz_506 = _zz_95; - assign _zz_507 = (_zz_527 == _zz_528); - assign _zz_508 = {_zz_95,_zz_529}; - assign _zz_509 = 2'b00; - assign _zz_510 = (_zz_530 != 1'b0); - assign _zz_511 = (_zz_531 != _zz_532); - assign _zz_512 = {_zz_533,{_zz_534,_zz_535}}; - assign _zz_513 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_514 = 32'h00004020; - assign _zz_515 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); - assign _zz_516 = ((decode_INSTRUCTION & _zz_537) == 32'h00000020); - assign _zz_517 = 32'h00002030; - assign _zz_518 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_519 = 32'h00000010; - assign _zz_520 = ((decode_INSTRUCTION & _zz_538) == 32'h00002020); - assign _zz_521 = ((decode_INSTRUCTION & _zz_539) == 32'h00000020); - assign _zz_522 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_523 = 32'h00001010; - assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00002010); - assign _zz_525 = (_zz_541 == _zz_542); - assign _zz_526 = {_zz_543,_zz_544}; - assign _zz_527 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_528 = 32'h00000020; - assign _zz_529 = ((decode_INSTRUCTION & _zz_545) == 32'h0); - assign _zz_530 = ((decode_INSTRUCTION & _zz_546) == 32'h00004010); - assign _zz_531 = (_zz_547 == _zz_548); - assign _zz_532 = 1'b0; - assign _zz_533 = ({_zz_549,_zz_550} != 4'b0000); - assign _zz_534 = (_zz_551 != _zz_552); - assign _zz_535 = {_zz_553,{_zz_554,_zz_555}}; - assign _zz_536 = 32'h00000030; - assign _zz_537 = 32'h02000020; - assign _zz_538 = 32'h02002060; - assign _zz_539 = 32'h02003020; - assign _zz_540 = 32'h00002010; - assign _zz_541 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_542 = 32'h00000010; - assign _zz_543 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_544 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_545 = 32'h00000020; - assign _zz_546 = 32'h00004014; - assign _zz_547 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_548 = 32'h00002010; - assign _zz_549 = ((decode_INSTRUCTION & _zz_556) == 32'h0); - assign _zz_550 = {(_zz_557 == _zz_558),{_zz_559,_zz_560}}; - assign _zz_551 = ((decode_INSTRUCTION & _zz_561) == 32'h0); - assign _zz_552 = 1'b0; - assign _zz_553 = ({_zz_562,{_zz_563,_zz_564}} != 3'b000); - assign _zz_554 = ({_zz_565,_zz_566} != 2'b00); - assign _zz_555 = {(_zz_567 != _zz_568),(_zz_569 != _zz_570)}; - assign _zz_556 = 32'h00000044; - assign _zz_557 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_558 = 32'h0; - assign _zz_559 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_560 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_561 = 32'h00000058; - assign _zz_562 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_563 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); - assign _zz_564 = ((decode_INSTRUCTION & _zz_572) == 32'h40000030); - assign _zz_565 = ((decode_INSTRUCTION & _zz_573) == 32'h00000004); - assign _zz_566 = _zz_94; - assign _zz_567 = {(_zz_574 == _zz_575),_zz_94}; - assign _zz_568 = 2'b00; - assign _zz_569 = ((decode_INSTRUCTION & _zz_576) == 32'h00001004); - assign _zz_570 = 1'b0; - assign _zz_571 = 32'h00002014; - assign _zz_572 = 32'h40000034; - assign _zz_573 = 32'h00000014; - assign _zz_574 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_575 = 32'h00000004; - assign _zz_576 = 32'h00005054; - assign _zz_577 = execute_INSTRUCTION[31]; - assign _zz_578 = execute_INSTRUCTION[31]; - assign _zz_579 = execute_INSTRUCTION[7]; - assign _zz_580 = 32'h0; + assign _zz_449 = ((_zz_455 == _zz_456) != 1'b0); + assign _zz_450 = ({_zz_457,_zz_458} != 2'b00); + assign _zz_451 = {(_zz_459 != _zz_460),{_zz_461,{_zz_462,_zz_463}}}; + assign _zz_452 = 32'h00007034; + assign _zz_453 = 32'h02007054; + assign _zz_454 = 32'h00001000; + assign _zz_455 = (decode_INSTRUCTION & 32'h00003000); + assign _zz_456 = 32'h00002000; + assign _zz_457 = ((decode_INSTRUCTION & _zz_464) == 32'h00002000); + assign _zz_458 = ((decode_INSTRUCTION & _zz_465) == 32'h00001000); + assign _zz_459 = ((decode_INSTRUCTION & _zz_466) == 32'h00004004); + assign _zz_460 = 1'b0; + assign _zz_461 = ({_zz_467,{_zz_468,_zz_469}} != 3'b000); + assign _zz_462 = ({_zz_470,_zz_471} != 5'h0); + assign _zz_463 = {(_zz_472 != _zz_473),{_zz_474,{_zz_475,_zz_476}}}; + assign _zz_464 = 32'h00002010; + assign _zz_465 = 32'h00005000; + assign _zz_466 = 32'h00004054; + assign _zz_467 = ((decode_INSTRUCTION & 32'h0000002c) == 32'h00000008); + assign _zz_468 = ((decode_INSTRUCTION & _zz_477) == 32'h00000040); + assign _zz_469 = ((decode_INSTRUCTION & _zz_478) == 32'h00000020); + assign _zz_470 = ((decode_INSTRUCTION & _zz_479) == 32'h00002040); + assign _zz_471 = {(_zz_480 == _zz_481),{_zz_482,{_zz_483,_zz_484}}}; + assign _zz_472 = _zz_98; + assign _zz_473 = 1'b0; + assign _zz_474 = ({_zz_485,{_zz_486,_zz_487}} != 6'h0); + assign _zz_475 = ({_zz_488,_zz_489} != 5'h0); + assign _zz_476 = {(_zz_490 != _zz_491),{_zz_492,{_zz_493,_zz_494}}}; + assign _zz_477 = 32'h00000054; + assign _zz_478 = 32'h0000006c; + assign _zz_479 = 32'h00002040; + assign _zz_480 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_481 = 32'h00001040; + assign _zz_482 = ((decode_INSTRUCTION & _zz_495) == 32'h00000040); + assign _zz_483 = (_zz_496 == _zz_497); + assign _zz_484 = (_zz_498 == _zz_499); + assign _zz_485 = ((decode_INSTRUCTION & _zz_500) == 32'h00000008); + assign _zz_486 = (_zz_501 == _zz_502); + assign _zz_487 = {_zz_95,{_zz_503,_zz_504}}; + assign _zz_488 = _zz_95; + assign _zz_489 = {_zz_505,{_zz_506,_zz_507}}; + assign _zz_490 = {_zz_97,{_zz_508,_zz_509}}; + assign _zz_491 = 7'h0; + assign _zz_492 = ({_zz_510,_zz_511} != 2'b00); + assign _zz_493 = (_zz_512 != _zz_513); + assign _zz_494 = {_zz_514,{_zz_515,_zz_516}}; + assign _zz_495 = 32'h00000050; + assign _zz_496 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_497 = 32'h00000040; + assign _zz_498 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_499 = 32'h0; + assign _zz_500 = 32'h00000008; + assign _zz_501 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_502 = 32'h00000040; + assign _zz_503 = (_zz_517 == _zz_518); + assign _zz_504 = {_zz_519,_zz_520}; + assign _zz_505 = ((decode_INSTRUCTION & _zz_521) == 32'h00002010); + assign _zz_506 = (_zz_522 == _zz_523); + assign _zz_507 = {_zz_524,_zz_525}; + assign _zz_508 = (_zz_526 == _zz_527); + assign _zz_509 = {_zz_528,{_zz_529,_zz_530}}; + assign _zz_510 = _zz_95; + assign _zz_511 = (_zz_531 == _zz_532); + assign _zz_512 = {_zz_95,_zz_533}; + assign _zz_513 = 2'b00; + assign _zz_514 = (_zz_534 != 1'b0); + assign _zz_515 = (_zz_535 != _zz_536); + assign _zz_516 = {_zz_537,{_zz_538,_zz_539}}; + assign _zz_517 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_518 = 32'h00004020; + assign _zz_519 = ((decode_INSTRUCTION & _zz_540) == 32'h00000010); + assign _zz_520 = ((decode_INSTRUCTION & _zz_541) == 32'h00000020); + assign _zz_521 = 32'h00002030; + assign _zz_522 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_523 = 32'h00000010; + assign _zz_524 = ((decode_INSTRUCTION & _zz_542) == 32'h00002020); + assign _zz_525 = ((decode_INSTRUCTION & _zz_543) == 32'h00000020); + assign _zz_526 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_527 = 32'h00001010; + assign _zz_528 = ((decode_INSTRUCTION & _zz_544) == 32'h00002010); + assign _zz_529 = (_zz_545 == _zz_546); + assign _zz_530 = {_zz_96,{_zz_547,_zz_548}}; + assign _zz_531 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_532 = 32'h00000020; + assign _zz_533 = ((decode_INSTRUCTION & _zz_549) == 32'h0); + assign _zz_534 = ((decode_INSTRUCTION & _zz_550) == 32'h00004010); + assign _zz_535 = (_zz_551 == _zz_552); + assign _zz_536 = 1'b0; + assign _zz_537 = ({_zz_553,_zz_554} != 4'b0000); + assign _zz_538 = (_zz_555 != _zz_556); + assign _zz_539 = {_zz_557,{_zz_558,_zz_559}}; + assign _zz_540 = 32'h00000030; + assign _zz_541 = 32'h02000020; + assign _zz_542 = 32'h02002060; + assign _zz_543 = 32'h02003028; + assign _zz_544 = 32'h00002010; + assign _zz_545 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_546 = 32'h00000010; + assign _zz_547 = ((decode_INSTRUCTION & _zz_560) == 32'h00000004); + assign _zz_548 = ((decode_INSTRUCTION & _zz_561) == 32'h0); + assign _zz_549 = 32'h00000020; + assign _zz_550 = 32'h00004014; + assign _zz_551 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_552 = 32'h00002010; + assign _zz_553 = ((decode_INSTRUCTION & _zz_562) == 32'h0); + assign _zz_554 = {(_zz_563 == _zz_564),{_zz_565,_zz_566}}; + assign _zz_555 = ((decode_INSTRUCTION & _zz_567) == 32'h0); + assign _zz_556 = 1'b0; + assign _zz_557 = ({_zz_568,{_zz_569,_zz_570}} != 3'b000); + assign _zz_558 = ({_zz_571,_zz_572} != 2'b00); + assign _zz_559 = {(_zz_573 != _zz_574),(_zz_575 != _zz_576)}; + assign _zz_560 = 32'h0000000c; + assign _zz_561 = 32'h00000028; + assign _zz_562 = 32'h00000044; + assign _zz_563 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_564 = 32'h0; + assign _zz_565 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_566 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_567 = 32'h00000058; + assign _zz_568 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_569 = ((decode_INSTRUCTION & _zz_577) == 32'h00002010); + assign _zz_570 = ((decode_INSTRUCTION & _zz_578) == 32'h40000030); + assign _zz_571 = ((decode_INSTRUCTION & _zz_579) == 32'h00000004); + assign _zz_572 = _zz_94; + assign _zz_573 = {(_zz_580 == _zz_581),_zz_94}; + assign _zz_574 = 2'b00; + assign _zz_575 = ((decode_INSTRUCTION & _zz_582) == 32'h00001004); + assign _zz_576 = 1'b0; + assign _zz_577 = 32'h00002014; + assign _zz_578 = 32'h40000034; + assign _zz_579 = 32'h00000014; + assign _zz_580 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_581 = 32'h00000004; + assign _zz_582 = 32'h00005054; + assign _zz_583 = execute_INSTRUCTION[31]; + assign _zz_584 = execute_INSTRUCTION[31]; + assign _zz_585 = execute_INSTRUCTION[7]; + assign _zz_586 = 32'h0; always @ (posedge clk) begin - if(_zz_385) begin - _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_388) begin + _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_386) begin - _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_389) begin + _zz_247 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1734,13 +1744,13 @@ module VexRiscv_inner ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_217 ), //i - .io_cpu_prefetch_isValid (_zz_218 ), //i + .io_flush (_zz_218 ), //i + .io_cpu_prefetch_isValid (_zz_219 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_219 ), //i - .io_cpu_fetch_isStuck (_zz_220 ), //i - .io_cpu_fetch_isRemoved (_zz_221 ), //i + .io_cpu_fetch_isValid (_zz_220 ), //i + .io_cpu_fetch_isStuck (_zz_221 ), //i + .io_cpu_fetch_isRemoved (_zz_222 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1753,8 +1763,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_222 ), //i - .io_cpu_decode_isStuck (_zz_223 ), //i + .io_cpu_decode_isValid (_zz_223 ), //i + .io_cpu_decode_isStuck (_zz_224 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1762,8 +1772,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_224 ), //i - .io_cpu_fill_valid (_zz_225 ), //i + .io_cpu_decode_isUser (_zz_225 ), //i + .io_cpu_fill_valid (_zz_226 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1776,20 +1786,20 @@ module VexRiscv_inner ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_226 ), //i - .io_cpu_execute_address (_zz_227[31:0] ), //i + .io_cpu_execute_isValid (_zz_227 ), //i + .io_cpu_execute_address (_zz_228[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_88[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_228 ), //i + .io_cpu_memory_isValid (_zz_229 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_229[31:0] ), //i + .io_cpu_memory_address (_zz_230[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_230 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_231 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1797,31 +1807,31 @@ module VexRiscv_inner ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_231 ), //i + .io_cpu_writeBack_isValid (_zz_232 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_232 ), //i + .io_cpu_writeBack_isUser (_zz_233 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_233[31:0] ), //i + .io_cpu_writeBack_address (_zz_234[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_234 ), //i - .io_cpu_writeBack_fence_SR (_zz_235 ), //i - .io_cpu_writeBack_fence_SO (_zz_236 ), //i - .io_cpu_writeBack_fence_SI (_zz_237 ), //i - .io_cpu_writeBack_fence_PW (_zz_238 ), //i - .io_cpu_writeBack_fence_PR (_zz_239 ), //i - .io_cpu_writeBack_fence_PO (_zz_240 ), //i - .io_cpu_writeBack_fence_PI (_zz_241 ), //i - .io_cpu_writeBack_fence_FM (_zz_242[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_235 ), //i + .io_cpu_writeBack_fence_SR (_zz_236 ), //i + .io_cpu_writeBack_fence_SO (_zz_237 ), //i + .io_cpu_writeBack_fence_SI (_zz_238 ), //i + .io_cpu_writeBack_fence_PW (_zz_239 ), //i + .io_cpu_writeBack_fence_PR (_zz_240 ), //i + .io_cpu_writeBack_fence_PO (_zz_241 ), //i + .io_cpu_writeBack_fence_PI (_zz_242 ), //i + .io_cpu_writeBack_fence_FM (_zz_243[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_243 ), //i + .io_cpu_flush_valid (_zz_244 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_244 ), //i + .io_mem_cmd_ready (_zz_245 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1837,28 +1847,39 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_387) + case(_zz_390) 2'b00 : begin - _zz_247 = DBusCachedPlugin_redoBranch_payload; + _zz_248 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_247 = CsrPlugin_jumpInterface_payload; + _zz_248 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_247 = BranchPlugin_jumpInterface_payload; + _zz_248 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_248 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(execute_CfuPlugin_CFU_ENCODING) + 1'b0 : begin + _zz_249 = execute_CfuPlugin_functionsIds_0; end default : begin - _zz_247 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_249 = execute_CfuPlugin_functionsIds_1; end endcase end `ifndef SYNTHESIS always @(*) begin - case(decode_CfuPlugin_CFU_ENCODING) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_ENCODING_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_ENCODING_string = "IMM_I"; - default : decode_CfuPlugin_CFU_ENCODING_string = "?????"; + case(decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin @@ -2163,10 +2184,10 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(execute_CfuPlugin_CFU_ENCODING) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_ENCODING_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_ENCODING_string = "IMM_I"; - default : execute_CfuPlugin_CFU_ENCODING_string = "?????"; + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin @@ -2438,74 +2459,74 @@ module VexRiscv_inner ( default : _zz_58_string = "????"; endcase end - always @(*) begin - case(_zz_99) - `Src1CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_99_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99_string = "URS1 "; - default : _zz_99_string = "????????????"; - endcase - end always @(*) begin case(_zz_100) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_100_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_100_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_100_string = "BITWISE "; - default : _zz_100_string = "????????"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; + default : _zz_100_string = "????????????"; endcase end always @(*) begin case(_zz_101) - `Src2CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_101_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_101_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_101_string = "PC "; - default : _zz_101_string = "???"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; + default : _zz_101_string = "????????"; endcase end always @(*) begin case(_zz_102) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_102_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_102_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_102_string = "AND_1"; - default : _zz_102_string = "?????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; + default : _zz_102_string = "???"; endcase end always @(*) begin case(_zz_103) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_103_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_103_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_103_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_103_string = "SRA_1 "; - default : _zz_103_string = "?????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; + default : _zz_103_string = "?????"; endcase end always @(*) begin case(_zz_104) - `BranchCtrlEnum_defaultEncoding_INC : _zz_104_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_104_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_104_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_104_string = "JALR"; - default : _zz_104_string = "????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; + default : _zz_104_string = "?????????"; endcase end always @(*) begin case(_zz_105) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_105_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_105_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_105_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_105_string = "ECALL"; - default : _zz_105_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; + default : _zz_105_string = "????"; endcase end always @(*) begin case(_zz_106) - `Input2Kind_defaultEncoding_RS : _zz_106_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_106_string = "IMM_I"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; default : _zz_106_string = "?????"; endcase end + always @(*) begin + case(_zz_107) + `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; + default : _zz_107_string = "?????"; + endcase + end always @(*) begin case(decode_to_execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; @@ -2595,15 +2616,15 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(decode_to_execute_CfuPlugin_CFU_ENCODING) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "IMM_I"; - default : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "?????"; + case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); + assign memory_MUL_LOW = ($signed(_zz_289) + $signed(_zz_297)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2611,43 +2632,42 @@ module VexRiscv_inner ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_297; - assign execute_REGFILE_WRITE_DATA = _zz_108; + assign execute_SHIFT_RIGHT = _zz_299; + assign execute_REGFILE_WRITE_DATA = _zz_109; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_227[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_228[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_299[0]; - assign decode_IS_RS1_SIGNED = _zz_300[0]; - assign decode_IS_DIV = _zz_301[0]; + assign decode_IS_RS2_SIGNED = _zz_301[0]; + assign decode_IS_RS1_SIGNED = _zz_302[0]; + assign decode_IS_DIV = _zz_303[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_302[0]; - assign decode_CfuPlugin_CFU_ENCODING = _zz_1; + assign decode_IS_MUL = _zz_304[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; + assign decode_CfuPlugin_CFU_ENCODING = _zz_93[29 : 29]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_305[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_304[0]; + assign decode_IS_CSR = _zz_306[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; - assign decode_MEMORY_MANAGMENT = _zz_306[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_307[0]; + assign decode_MEMORY_MANAGMENT = _zz_308[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_307[0]; + assign decode_MEMORY_WR = _zz_309[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_310[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_311[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2685,7 +2705,8 @@ module VexRiscv_inner ( end assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_ENCODING = _zz_32; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; + assign execute_CfuPlugin_CFU_ENCODING = decode_to_execute_CfuPlugin_CFU_ENCODING; assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; @@ -2693,18 +2714,18 @@ module VexRiscv_inner ( assign memory_ENV_CTRL = _zz_33; assign execute_ENV_CTRL = _zz_34; assign writeBack_ENV_CTRL = _zz_35; - assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; - assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_130; + assign execute_BRANCH_COND_RESULT = _zz_131; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_310[0]; - assign decode_RS1_USE = _zz_311[0]; + assign decode_RS2_USE = _zz_312[0]; + assign decode_RS1_USE = _zz_313[0]; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_248)begin + if(_zz_250)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2717,28 +2738,28 @@ module VexRiscv_inner ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_119)begin - if((_zz_120 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_121; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_122; end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_123)begin + if(_zz_251)begin + if(_zz_252)begin + if(_zz_124)begin decode_RS2 = _zz_57; end end end - if(_zz_251)begin + if(_zz_253)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin + if(_zz_126)begin decode_RS2 = _zz_38; end end end - if(_zz_252)begin + if(_zz_254)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin + if(_zz_128)begin decode_RS2 = _zz_37; end end @@ -2747,28 +2768,28 @@ module VexRiscv_inner ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_119)begin - if((_zz_120 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_121; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_122; end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_122)begin + if(_zz_251)begin + if(_zz_252)begin + if(_zz_123)begin decode_RS1 = _zz_57; end end end - if(_zz_251)begin + if(_zz_253)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_124)begin + if(_zz_125)begin decode_RS1 = _zz_38; end end end - if(_zz_252)begin + if(_zz_254)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_126)begin + if(_zz_127)begin decode_RS1 = _zz_37; end end @@ -2781,7 +2802,7 @@ module VexRiscv_inner ( if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_116; + _zz_38 = _zz_117; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin _zz_38 = memory_SHIFT_RIGHT; @@ -2793,7 +2814,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_253)begin + if(_zz_255)begin _zz_38 = memory_DivPlugin_div_result; end end @@ -2806,13 +2827,13 @@ module VexRiscv_inner ( assign _zz_41 = execute_PC; assign execute_SRC2_CTRL = _zz_42; assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_312[0]; - assign decode_SRC_ADD_ZERO = _zz_313[0]; + assign decode_SRC_USE_SUB_LESS = _zz_314[0]; + assign decode_SRC_ADD_ZERO = _zz_315[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_114; - assign execute_SRC1 = _zz_109; + assign execute_SRC2 = _zz_115; + assign execute_SRC1 = _zz_110; assign execute_ALU_BITWISE_CTRL = _zz_45; assign _zz_46 = writeBack_INSTRUCTION; assign _zz_47 = writeBack_REGFILE_WRITE_VALID; @@ -2825,25 +2846,25 @@ module VexRiscv_inner ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_314[0]; + decode_REGFILE_WRITE_VALID = _zz_316[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_391) == 32'h00000003),{(_zz_392 == _zz_393),{_zz_394,{_zz_395,_zz_396}}}}}}} != 23'h0); always @ (*) begin _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_286) + case(_zz_288) 2'b00 : begin - _zz_57 = _zz_360; + _zz_57 = _zz_363; end default : begin - _zz_57 = _zz_361; + _zz_57 = _zz_364; end endcase end @@ -2862,32 +2883,32 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_315[0]; - assign decode_FLUSH_ALL = _zz_316[0]; + assign decode_MEMORY_ENABLE = _zz_317[0]; + assign decode_FLUSH_ALL = _zz_318[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_254)begin + if(_zz_256)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_255)begin + if(_zz_257)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_256)begin + if(_zz_258)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_257)begin + if(_zz_259)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2895,7 +2916,7 @@ module VexRiscv_inner ( assign decode_BRANCH_CTRL = _zz_58; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_59 = memory_FORMAL_PC_NEXT; + _zz_59 = execute_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin _zz_59 = BranchPlugin_jumpInterface_payload; end @@ -2920,7 +2941,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_117 || _zz_118)))begin + if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2933,7 +2954,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_258)begin + if(_zz_260)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2947,22 +2968,22 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_258)begin + if(_zz_260)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_243 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_244 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_259)begin + if(_zz_261)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_248)begin + if(_zz_250)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2981,7 +3002,7 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(_zz_262)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -2992,7 +3013,10 @@ module VexRiscv_inner ( assign execute_arbitration_flushIt = 1'b0; always @ (*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_262)begin execute_arbitration_flushNext = 1'b1; end end @@ -3004,7 +3028,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_253)begin + if(_zz_255)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3014,7 +3038,7 @@ module VexRiscv_inner ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_260)begin + if(CfuPlugin_joinException_valid)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3025,10 +3049,7 @@ module VexRiscv_inner ( assign memory_arbitration_flushIt = 1'b0; always @ (*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(_zz_260)begin + if(CfuPlugin_joinException_valid)begin memory_arbitration_flushNext = 1'b1; end end @@ -3066,10 +3087,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(_zz_263)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_262)begin + if(_zz_264)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3083,10 +3104,10 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_261)begin + if(_zz_263)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_262)begin + if(_zz_264)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3100,7 +3121,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_259)begin + if(_zz_261)begin CsrPlugin_inWfi = 1'b1; end end @@ -3108,21 +3129,21 @@ module VexRiscv_inner ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_261)begin + if(_zz_263)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_262)begin + if(_zz_264)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_261)begin + if(_zz_263)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_262)begin - case(_zz_263) + if(_zz_264)begin + case(_zz_265) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3138,11 +3159,11 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_62 = (_zz_61 & (~ _zz_317)); + assign _zz_62 = (_zz_61 & (~ _zz_319)); assign _zz_63 = _zz_62[3]; assign _zz_64 = (_zz_62[1] || _zz_63); assign _zz_65 = (_zz_62[2] || _zz_63); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_248; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3162,7 +3183,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_319); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_321); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3253,7 +3274,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_75 = _zz_320[11]; + assign _zz_75 = _zz_322[11]; always @ (*) begin _zz_76[18] = _zz_75; _zz_76[17] = _zz_75; @@ -3277,13 +3298,13 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_321[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_323[31])); if(_zz_81)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_77 = _zz_322[19]; + assign _zz_77 = _zz_324[19]; always @ (*) begin _zz_78[10] = _zz_77; _zz_78[9] = _zz_77; @@ -3298,7 +3319,7 @@ module VexRiscv_inner ( _zz_78[0] = _zz_77; end - assign _zz_79 = _zz_323[11]; + assign _zz_79 = _zz_325[11]; always @ (*) begin _zz_80[18] = _zz_79; _zz_80[17] = _zz_79; @@ -3324,16 +3345,16 @@ module VexRiscv_inner ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_81 = _zz_324[1]; + _zz_81 = _zz_326[1]; end default : begin - _zz_81 = _zz_325[1]; + _zz_81 = _zz_327[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_82 = _zz_326[19]; + assign _zz_82 = _zz_328[19]; always @ (*) begin _zz_83[10] = _zz_82; _zz_83[9] = _zz_82; @@ -3348,7 +3369,7 @@ module VexRiscv_inner ( _zz_83[0] = _zz_82; end - assign _zz_84 = _zz_327[11]; + assign _zz_84 = _zz_329[11]; always @ (*) begin _zz_85[18] = _zz_84; _zz_85[17] = _zz_84; @@ -3371,7 +3392,7 @@ module VexRiscv_inner ( _zz_85[0] = _zz_84; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_406,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_407,_zz_408},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_409,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_410,_zz_411},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3380,52 +3401,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_219; + assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_220 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_221 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_220; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_224 = (CsrPlugin_privilege == 2'b00); + assign _zz_223 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_224 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_225 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_257)begin + if(_zz_259)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_255)begin + if(_zz_257)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_225 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_255)begin - _zz_225 = 1'b1; + _zz_226 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_257)begin + _zz_226 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_256)begin + if(_zz_258)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_254)begin + if(_zz_256)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_256)begin + if(_zz_258)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_254)begin + if(_zz_256)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3435,9 +3456,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_217 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_218 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_244 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_245 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3464,8 +3485,8 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_227 = execute_SRC_ADD; + assign _zz_227 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_228 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3480,27 +3501,27 @@ module VexRiscv_inner ( endcase end - assign _zz_243 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_228 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_229 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_228; + assign _zz_244 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_229 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_230 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_229; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_229; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_230; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_230 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_231 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_230 = 1'b1; + _zz_231 = 1'b1; end end - assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_232 = (CsrPlugin_privilege == 2'b00); - assign _zz_233 = writeBack_REGFILE_WRITE_DATA; + assign _zz_232 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_233 = (CsrPlugin_privilege == 2'b00); + assign _zz_234 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_264)begin + if(_zz_266)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3510,7 +3531,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_264)begin + if(_zz_266)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3529,15 +3550,15 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_264)begin + if(_zz_266)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_330}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_331}; end end end @@ -3610,7 +3631,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_284) + case(_zz_286) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_90; end @@ -3643,50 +3664,51 @@ module VexRiscv_inner ( assign DBusCachedPlugin_mmuBus_busy = 1'b0; assign _zz_94 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); assign _zz_95 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_409 == _zz_410) != 1'b0),{(_zz_411 != 1'b0),{1'b0,{_zz_412,{_zz_413,_zz_414}}}}}}}; - assign _zz_99 = _zz_93[2 : 1]; - assign _zz_56 = _zz_99; - assign _zz_100 = _zz_93[7 : 6]; - assign _zz_55 = _zz_100; - assign _zz_101 = _zz_93[9 : 8]; - assign _zz_54 = _zz_101; - assign _zz_102 = _zz_93[19 : 18]; - assign _zz_53 = _zz_102; - assign _zz_103 = _zz_93[22 : 21]; - assign _zz_52 = _zz_103; - assign _zz_104 = _zz_93[24 : 23]; - assign _zz_51 = _zz_104; - assign _zz_105 = _zz_93[27 : 26]; - assign _zz_50 = _zz_105; - assign _zz_106 = _zz_93[29 : 29]; - assign _zz_49 = _zz_106; + assign _zz_96 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_98 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_93 = {(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{((_zz_412 == _zz_413) != 1'b0),{(_zz_414 != 1'b0),{(_zz_415 != _zz_416),{_zz_417,{_zz_418,_zz_419}}}}}}}; + assign _zz_100 = _zz_93[2 : 1]; + assign _zz_56 = _zz_100; + assign _zz_101 = _zz_93[7 : 6]; + assign _zz_55 = _zz_101; + assign _zz_102 = _zz_93[9 : 8]; + assign _zz_54 = _zz_102; + assign _zz_103 = _zz_93[19 : 18]; + assign _zz_53 = _zz_103; + assign _zz_104 = _zz_93[22 : 21]; + assign _zz_52 = _zz_104; + assign _zz_105 = _zz_93[24 : 23]; + assign _zz_51 = _zz_105; + assign _zz_106 = _zz_93[27 : 26]; + assign _zz_50 = _zz_106; + assign _zz_107 = _zz_93[30 : 30]; + assign _zz_49 = _zz_107; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_245; - assign decode_RegFilePlugin_rs2Data = _zz_246; + assign decode_RegFilePlugin_rs1Data = _zz_246; + assign decode_RegFilePlugin_rs2Data = _zz_247; always @ (*) begin lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_107)begin + if(_zz_108)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_107)begin + if(_zz_108)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_107)begin + if(_zz_108)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -3708,13 +3730,13 @@ module VexRiscv_inner ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_108 = execute_IntAluPlugin_bitwise; + _zz_109 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_108 = {31'd0, _zz_330}; + _zz_109 = {31'd0, _zz_332}; end default : begin - _zz_108 = execute_SRC_ADD_SUB; + _zz_109 = execute_SRC_ADD_SUB; end endcase end @@ -3722,87 +3744,87 @@ module VexRiscv_inner ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_109 = execute_RS1; + _zz_110 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_109 = {29'd0, _zz_331}; + _zz_110 = {29'd0, _zz_333}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_109 = {27'd0, _zz_332}; + _zz_110 = {27'd0, _zz_334}; end endcase end - assign _zz_110 = _zz_333[11]; - always @ (*) begin - _zz_111[19] = _zz_110; - _zz_111[18] = _zz_110; - _zz_111[17] = _zz_110; - _zz_111[16] = _zz_110; - _zz_111[15] = _zz_110; - _zz_111[14] = _zz_110; - _zz_111[13] = _zz_110; - _zz_111[12] = _zz_110; - _zz_111[11] = _zz_110; - _zz_111[10] = _zz_110; - _zz_111[9] = _zz_110; - _zz_111[8] = _zz_110; - _zz_111[7] = _zz_110; - _zz_111[6] = _zz_110; - _zz_111[5] = _zz_110; - _zz_111[4] = _zz_110; - _zz_111[3] = _zz_110; - _zz_111[2] = _zz_110; - _zz_111[1] = _zz_110; - _zz_111[0] = _zz_110; - end - - assign _zz_112 = _zz_334[11]; - always @ (*) begin - _zz_113[19] = _zz_112; - _zz_113[18] = _zz_112; - _zz_113[17] = _zz_112; - _zz_113[16] = _zz_112; - _zz_113[15] = _zz_112; - _zz_113[14] = _zz_112; - _zz_113[13] = _zz_112; - _zz_113[12] = _zz_112; - _zz_113[11] = _zz_112; - _zz_113[10] = _zz_112; - _zz_113[9] = _zz_112; - _zz_113[8] = _zz_112; - _zz_113[7] = _zz_112; - _zz_113[6] = _zz_112; - _zz_113[5] = _zz_112; - _zz_113[4] = _zz_112; - _zz_113[3] = _zz_112; - _zz_113[2] = _zz_112; - _zz_113[1] = _zz_112; - _zz_113[0] = _zz_112; + assign _zz_111 = _zz_335[11]; + always @ (*) begin + _zz_112[19] = _zz_111; + _zz_112[18] = _zz_111; + _zz_112[17] = _zz_111; + _zz_112[16] = _zz_111; + _zz_112[15] = _zz_111; + _zz_112[14] = _zz_111; + _zz_112[13] = _zz_111; + _zz_112[12] = _zz_111; + _zz_112[11] = _zz_111; + _zz_112[10] = _zz_111; + _zz_112[9] = _zz_111; + _zz_112[8] = _zz_111; + _zz_112[7] = _zz_111; + _zz_112[6] = _zz_111; + _zz_112[5] = _zz_111; + _zz_112[4] = _zz_111; + _zz_112[3] = _zz_111; + _zz_112[2] = _zz_111; + _zz_112[1] = _zz_111; + _zz_112[0] = _zz_111; + end + + assign _zz_113 = _zz_336[11]; + always @ (*) begin + _zz_114[19] = _zz_113; + _zz_114[18] = _zz_113; + _zz_114[17] = _zz_113; + _zz_114[16] = _zz_113; + _zz_114[15] = _zz_113; + _zz_114[14] = _zz_113; + _zz_114[13] = _zz_113; + _zz_114[12] = _zz_113; + _zz_114[11] = _zz_113; + _zz_114[10] = _zz_113; + _zz_114[9] = _zz_113; + _zz_114[8] = _zz_113; + _zz_114[7] = _zz_113; + _zz_114[6] = _zz_113; + _zz_114[5] = _zz_113; + _zz_114[4] = _zz_113; + _zz_114[3] = _zz_113; + _zz_114[2] = _zz_113; + _zz_114[1] = _zz_113; + _zz_114[0] = _zz_113; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_114 = execute_RS2; + _zz_115 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_114 = {_zz_111,execute_INSTRUCTION[31 : 20]}; + _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_114 = {_zz_113,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_114 = _zz_41; + _zz_115 = _zz_41; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_335; + execute_SrcPlugin_addSub = _zz_337; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3811,246 +3833,246 @@ module VexRiscv_inner ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_115[0] = execute_SRC1[31]; - _zz_115[1] = execute_SRC1[30]; - _zz_115[2] = execute_SRC1[29]; - _zz_115[3] = execute_SRC1[28]; - _zz_115[4] = execute_SRC1[27]; - _zz_115[5] = execute_SRC1[26]; - _zz_115[6] = execute_SRC1[25]; - _zz_115[7] = execute_SRC1[24]; - _zz_115[8] = execute_SRC1[23]; - _zz_115[9] = execute_SRC1[22]; - _zz_115[10] = execute_SRC1[21]; - _zz_115[11] = execute_SRC1[20]; - _zz_115[12] = execute_SRC1[19]; - _zz_115[13] = execute_SRC1[18]; - _zz_115[14] = execute_SRC1[17]; - _zz_115[15] = execute_SRC1[16]; - _zz_115[16] = execute_SRC1[15]; - _zz_115[17] = execute_SRC1[14]; - _zz_115[18] = execute_SRC1[13]; - _zz_115[19] = execute_SRC1[12]; - _zz_115[20] = execute_SRC1[11]; - _zz_115[21] = execute_SRC1[10]; - _zz_115[22] = execute_SRC1[9]; - _zz_115[23] = execute_SRC1[8]; - _zz_115[24] = execute_SRC1[7]; - _zz_115[25] = execute_SRC1[6]; - _zz_115[26] = execute_SRC1[5]; - _zz_115[27] = execute_SRC1[4]; - _zz_115[28] = execute_SRC1[3]; - _zz_115[29] = execute_SRC1[2]; - _zz_115[30] = execute_SRC1[1]; - _zz_115[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_115 : execute_SRC1); - always @ (*) begin - _zz_116[0] = memory_SHIFT_RIGHT[31]; - _zz_116[1] = memory_SHIFT_RIGHT[30]; - _zz_116[2] = memory_SHIFT_RIGHT[29]; - _zz_116[3] = memory_SHIFT_RIGHT[28]; - _zz_116[4] = memory_SHIFT_RIGHT[27]; - _zz_116[5] = memory_SHIFT_RIGHT[26]; - _zz_116[6] = memory_SHIFT_RIGHT[25]; - _zz_116[7] = memory_SHIFT_RIGHT[24]; - _zz_116[8] = memory_SHIFT_RIGHT[23]; - _zz_116[9] = memory_SHIFT_RIGHT[22]; - _zz_116[10] = memory_SHIFT_RIGHT[21]; - _zz_116[11] = memory_SHIFT_RIGHT[20]; - _zz_116[12] = memory_SHIFT_RIGHT[19]; - _zz_116[13] = memory_SHIFT_RIGHT[18]; - _zz_116[14] = memory_SHIFT_RIGHT[17]; - _zz_116[15] = memory_SHIFT_RIGHT[16]; - _zz_116[16] = memory_SHIFT_RIGHT[15]; - _zz_116[17] = memory_SHIFT_RIGHT[14]; - _zz_116[18] = memory_SHIFT_RIGHT[13]; - _zz_116[19] = memory_SHIFT_RIGHT[12]; - _zz_116[20] = memory_SHIFT_RIGHT[11]; - _zz_116[21] = memory_SHIFT_RIGHT[10]; - _zz_116[22] = memory_SHIFT_RIGHT[9]; - _zz_116[23] = memory_SHIFT_RIGHT[8]; - _zz_116[24] = memory_SHIFT_RIGHT[7]; - _zz_116[25] = memory_SHIFT_RIGHT[6]; - _zz_116[26] = memory_SHIFT_RIGHT[5]; - _zz_116[27] = memory_SHIFT_RIGHT[4]; - _zz_116[28] = memory_SHIFT_RIGHT[3]; - _zz_116[29] = memory_SHIFT_RIGHT[2]; - _zz_116[30] = memory_SHIFT_RIGHT[1]; - _zz_116[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_117 = 1'b0; - if(_zz_265)begin - if(_zz_266)begin - if(_zz_122)begin - _zz_117 = 1'b1; - end - end - end + _zz_116[0] = execute_SRC1[31]; + _zz_116[1] = execute_SRC1[30]; + _zz_116[2] = execute_SRC1[29]; + _zz_116[3] = execute_SRC1[28]; + _zz_116[4] = execute_SRC1[27]; + _zz_116[5] = execute_SRC1[26]; + _zz_116[6] = execute_SRC1[25]; + _zz_116[7] = execute_SRC1[24]; + _zz_116[8] = execute_SRC1[23]; + _zz_116[9] = execute_SRC1[22]; + _zz_116[10] = execute_SRC1[21]; + _zz_116[11] = execute_SRC1[20]; + _zz_116[12] = execute_SRC1[19]; + _zz_116[13] = execute_SRC1[18]; + _zz_116[14] = execute_SRC1[17]; + _zz_116[15] = execute_SRC1[16]; + _zz_116[16] = execute_SRC1[15]; + _zz_116[17] = execute_SRC1[14]; + _zz_116[18] = execute_SRC1[13]; + _zz_116[19] = execute_SRC1[12]; + _zz_116[20] = execute_SRC1[11]; + _zz_116[21] = execute_SRC1[10]; + _zz_116[22] = execute_SRC1[9]; + _zz_116[23] = execute_SRC1[8]; + _zz_116[24] = execute_SRC1[7]; + _zz_116[25] = execute_SRC1[6]; + _zz_116[26] = execute_SRC1[5]; + _zz_116[27] = execute_SRC1[4]; + _zz_116[28] = execute_SRC1[3]; + _zz_116[29] = execute_SRC1[2]; + _zz_116[30] = execute_SRC1[1]; + _zz_116[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); + always @ (*) begin + _zz_117[0] = memory_SHIFT_RIGHT[31]; + _zz_117[1] = memory_SHIFT_RIGHT[30]; + _zz_117[2] = memory_SHIFT_RIGHT[29]; + _zz_117[3] = memory_SHIFT_RIGHT[28]; + _zz_117[4] = memory_SHIFT_RIGHT[27]; + _zz_117[5] = memory_SHIFT_RIGHT[26]; + _zz_117[6] = memory_SHIFT_RIGHT[25]; + _zz_117[7] = memory_SHIFT_RIGHT[24]; + _zz_117[8] = memory_SHIFT_RIGHT[23]; + _zz_117[9] = memory_SHIFT_RIGHT[22]; + _zz_117[10] = memory_SHIFT_RIGHT[21]; + _zz_117[11] = memory_SHIFT_RIGHT[20]; + _zz_117[12] = memory_SHIFT_RIGHT[19]; + _zz_117[13] = memory_SHIFT_RIGHT[18]; + _zz_117[14] = memory_SHIFT_RIGHT[17]; + _zz_117[15] = memory_SHIFT_RIGHT[16]; + _zz_117[16] = memory_SHIFT_RIGHT[15]; + _zz_117[17] = memory_SHIFT_RIGHT[14]; + _zz_117[18] = memory_SHIFT_RIGHT[13]; + _zz_117[19] = memory_SHIFT_RIGHT[12]; + _zz_117[20] = memory_SHIFT_RIGHT[11]; + _zz_117[21] = memory_SHIFT_RIGHT[10]; + _zz_117[22] = memory_SHIFT_RIGHT[9]; + _zz_117[23] = memory_SHIFT_RIGHT[8]; + _zz_117[24] = memory_SHIFT_RIGHT[7]; + _zz_117[25] = memory_SHIFT_RIGHT[6]; + _zz_117[26] = memory_SHIFT_RIGHT[5]; + _zz_117[27] = memory_SHIFT_RIGHT[4]; + _zz_117[28] = memory_SHIFT_RIGHT[3]; + _zz_117[29] = memory_SHIFT_RIGHT[2]; + _zz_117[30] = memory_SHIFT_RIGHT[1]; + _zz_117[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_118 = 1'b0; if(_zz_267)begin if(_zz_268)begin - if(_zz_124)begin - _zz_117 = 1'b1; + if(_zz_123)begin + _zz_118 = 1'b1; end end end if(_zz_269)begin if(_zz_270)begin - if(_zz_126)begin - _zz_117 = 1'b1; + if(_zz_125)begin + _zz_118 = 1'b1; + end + end + end + if(_zz_271)begin + if(_zz_272)begin + if(_zz_127)begin + _zz_118 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_117 = 1'b0; + _zz_118 = 1'b0; end end always @ (*) begin - _zz_118 = 1'b0; - if(_zz_265)begin - if(_zz_266)begin - if(_zz_123)begin - _zz_118 = 1'b1; - end - end - end + _zz_119 = 1'b0; if(_zz_267)begin if(_zz_268)begin - if(_zz_125)begin - _zz_118 = 1'b1; + if(_zz_124)begin + _zz_119 = 1'b1; end end end if(_zz_269)begin if(_zz_270)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(_zz_126)begin + _zz_119 = 1'b1; + end + end + end + if(_zz_271)begin + if(_zz_272)begin + if(_zz_128)begin + _zz_119 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_118 = 1'b0; + _zz_119 = 1'b0; end end - assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_128 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_128 == 3'b000)) begin - _zz_129 = execute_BranchPlugin_eq; - end else if((_zz_128 == 3'b001)) begin - _zz_129 = (! execute_BranchPlugin_eq); - end else if((((_zz_128 & 3'b101) == 3'b101))) begin - _zz_129 = (! execute_SRC_LESS); + assign _zz_129 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_129 == 3'b000)) begin + _zz_130 = execute_BranchPlugin_eq; + end else if((_zz_129 == 3'b001)) begin + _zz_130 = (! execute_BranchPlugin_eq); + end else if((((_zz_129 & 3'b101) == 3'b101))) begin + _zz_130 = (! execute_SRC_LESS); end else begin - _zz_129 = execute_SRC_LESS; + _zz_130 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_130 = 1'b0; + _zz_131 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_130 = 1'b1; + _zz_131 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_130 = 1'b1; + _zz_131 = 1'b1; end default : begin - _zz_130 = _zz_129; + _zz_131 = _zz_130; end endcase end - assign _zz_131 = _zz_342[11]; - always @ (*) begin - _zz_132[19] = _zz_131; - _zz_132[18] = _zz_131; - _zz_132[17] = _zz_131; - _zz_132[16] = _zz_131; - _zz_132[15] = _zz_131; - _zz_132[14] = _zz_131; - _zz_132[13] = _zz_131; - _zz_132[12] = _zz_131; - _zz_132[11] = _zz_131; - _zz_132[10] = _zz_131; - _zz_132[9] = _zz_131; - _zz_132[8] = _zz_131; - _zz_132[7] = _zz_131; - _zz_132[6] = _zz_131; - _zz_132[5] = _zz_131; - _zz_132[4] = _zz_131; - _zz_132[3] = _zz_131; - _zz_132[2] = _zz_131; - _zz_132[1] = _zz_131; - _zz_132[0] = _zz_131; - end - - assign _zz_133 = _zz_343[19]; - always @ (*) begin - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; - end - - assign _zz_135 = _zz_344[11]; - always @ (*) begin - _zz_136[18] = _zz_135; - _zz_136[17] = _zz_135; - _zz_136[16] = _zz_135; - _zz_136[15] = _zz_135; - _zz_136[14] = _zz_135; - _zz_136[13] = _zz_135; - _zz_136[12] = _zz_135; - _zz_136[11] = _zz_135; - _zz_136[10] = _zz_135; - _zz_136[9] = _zz_135; - _zz_136[8] = _zz_135; - _zz_136[7] = _zz_135; - _zz_136[6] = _zz_135; - _zz_136[5] = _zz_135; - _zz_136[4] = _zz_135; - _zz_136[3] = _zz_135; - _zz_136[2] = _zz_135; - _zz_136[1] = _zz_135; - _zz_136[0] = _zz_135; + assign _zz_132 = _zz_344[11]; + always @ (*) begin + _zz_133[19] = _zz_132; + _zz_133[18] = _zz_132; + _zz_133[17] = _zz_132; + _zz_133[16] = _zz_132; + _zz_133[15] = _zz_132; + _zz_133[14] = _zz_132; + _zz_133[13] = _zz_132; + _zz_133[12] = _zz_132; + _zz_133[11] = _zz_132; + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; + end + + assign _zz_134 = _zz_345[19]; + always @ (*) begin + _zz_135[10] = _zz_134; + _zz_135[9] = _zz_134; + _zz_135[8] = _zz_134; + _zz_135[7] = _zz_134; + _zz_135[6] = _zz_134; + _zz_135[5] = _zz_134; + _zz_135[4] = _zz_134; + _zz_135[3] = _zz_134; + _zz_135[2] = _zz_134; + _zz_135[1] = _zz_134; + _zz_135[0] = _zz_134; + end + + assign _zz_136 = _zz_346[11]; + always @ (*) begin + _zz_137[18] = _zz_136; + _zz_137[17] = _zz_136; + _zz_137[16] = _zz_136; + _zz_137[15] = _zz_136; + _zz_137[14] = _zz_136; + _zz_137[13] = _zz_136; + _zz_137[12] = _zz_136; + _zz_137[11] = _zz_136; + _zz_137[10] = _zz_136; + _zz_137[9] = _zz_136; + _zz_137[8] = _zz_136; + _zz_137[7] = _zz_136; + _zz_137[6] = _zz_136; + _zz_137[5] = _zz_136; + _zz_137[4] = _zz_136; + _zz_137[3] = _zz_136; + _zz_137[2] = _zz_136; + _zz_137[1] = _zz_136; + _zz_137[0] = _zz_136; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_137 = (_zz_345[1] ^ execute_RS1[1]); + _zz_138 = (_zz_347[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_137 = _zz_346[1]; + _zz_138 = _zz_348[1]; end default : begin - _zz_137 = _zz_347[1]; + _zz_138 = _zz_349[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_137); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4062,88 +4084,94 @@ module VexRiscv_inner ( endcase end - assign _zz_138 = _zz_348[11]; + assign _zz_139 = _zz_350[11]; always @ (*) begin - _zz_139[19] = _zz_138; - _zz_139[18] = _zz_138; - _zz_139[17] = _zz_138; - _zz_139[16] = _zz_138; - _zz_139[15] = _zz_138; - _zz_139[14] = _zz_138; - _zz_139[13] = _zz_138; - _zz_139[12] = _zz_138; - _zz_139[11] = _zz_138; - _zz_139[10] = _zz_138; - _zz_139[9] = _zz_138; - _zz_139[8] = _zz_138; - _zz_139[7] = _zz_138; - _zz_139[6] = _zz_138; - _zz_139[5] = _zz_138; - _zz_139[4] = _zz_138; - _zz_139[3] = _zz_138; - _zz_139[2] = _zz_138; - _zz_139[1] = _zz_138; - _zz_139[0] = _zz_138; + _zz_140[19] = _zz_139; + _zz_140[18] = _zz_139; + _zz_140[17] = _zz_139; + _zz_140[16] = _zz_139; + _zz_140[15] = _zz_139; + _zz_140[14] = _zz_139; + _zz_140[13] = _zz_139; + _zz_140[12] = _zz_139; + _zz_140[11] = _zz_139; + _zz_140[10] = _zz_139; + _zz_140[9] = _zz_139; + _zz_140[8] = _zz_139; + _zz_140[7] = _zz_139; + _zz_140[6] = _zz_139; + _zz_140[5] = _zz_139; + _zz_140[4] = _zz_139; + _zz_140[3] = _zz_139; + _zz_140[2] = _zz_139; + _zz_140[1] = _zz_139; + _zz_140[0] = _zz_139; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_577,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_578,_zz_579},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_583,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_584,_zz_585},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_351}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_353}; end end endcase end - assign _zz_140 = _zz_349[19]; - always @ (*) begin - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; - end - - assign _zz_142 = _zz_350[11]; - always @ (*) begin - _zz_143[18] = _zz_142; - _zz_143[17] = _zz_142; - _zz_143[16] = _zz_142; - _zz_143[15] = _zz_142; - _zz_143[14] = _zz_142; - _zz_143[13] = _zz_142; - _zz_143[12] = _zz_142; - _zz_143[11] = _zz_142; - _zz_143[10] = _zz_142; - _zz_143[9] = _zz_142; - _zz_143[8] = _zz_142; - _zz_143[7] = _zz_142; - _zz_143[6] = _zz_142; - _zz_143[5] = _zz_142; - _zz_143[4] = _zz_142; - _zz_143[3] = _zz_142; - _zz_143[2] = _zz_142; - _zz_143[1] = _zz_142; - _zz_143[0] = _zz_142; + assign _zz_141 = _zz_351[19]; + always @ (*) begin + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; + end + + assign _zz_143 = _zz_352[11]; + always @ (*) begin + _zz_144[18] = _zz_143; + _zz_144[17] = _zz_143; + _zz_144[16] = _zz_143; + _zz_144[15] = _zz_143; + _zz_144[14] = _zz_143; + _zz_144[13] = _zz_143; + _zz_144[12] = _zz_143; + _zz_144[11] = _zz_143; + _zz_144[10] = _zz_143; + _zz_144[9] = _zz_143; + _zz_144[8] = _zz_143; + _zz_144[7] = _zz_143; + _zz_144[6] = _zz_143; + _zz_144[5] = _zz_143; + _zz_144[4] = _zz_143; + _zz_144[3] = _zz_143; + _zz_144[2] = _zz_143; + _zz_144[1] = _zz_143; + _zz_144[0] = _zz_143; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); - assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; - assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; - assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin CsrPlugin_privilege = 2'b11; @@ -4152,18 +4180,18 @@ module VexRiscv_inner ( end end - assign _zz_144 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_145 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_146 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_148 = _zz_352[0]; - assign _zz_149 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_150 = _zz_354[0]; + assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_149 = _zz_354[0]; + assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_151 = _zz_356[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_258)begin + if(_zz_260)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4173,7 +4201,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(_zz_262)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -4183,7 +4211,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_260)begin + if(CfuPlugin_joinException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4414,7 +4442,7 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_271)begin + if(_zz_273)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4433,20 +4461,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_272)begin + if(_zz_274)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_273)begin + if(_zz_275)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_272)begin + if(_zz_274)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_273)begin + if(_zz_275)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4461,14 +4489,14 @@ module VexRiscv_inner ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_271)begin + if(_zz_273)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_271)begin + if(_zz_273)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4477,7 +4505,7 @@ module VexRiscv_inner ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_285) + case(_zz_287) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4490,45 +4518,50 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_356; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign execute_CfuPlugin_functionsIds_0 = _zz_358; + assign execute_CfuPlugin_functionsIds_1 = {6'd0, _zz_359}; + assign CfuPlugin_bus_cmd_payload_function_id = _zz_249; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_167 = _zz_357[11]; - always @ (*) begin - _zz_168[19] = _zz_167; - _zz_168[18] = _zz_167; - _zz_168[17] = _zz_167; - _zz_168[16] = _zz_167; - _zz_168[15] = _zz_167; - _zz_168[14] = _zz_167; - _zz_168[13] = _zz_167; - _zz_168[12] = _zz_167; - _zz_168[11] = _zz_167; - _zz_168[10] = _zz_167; - _zz_168[9] = _zz_167; - _zz_168[8] = _zz_167; - _zz_168[7] = _zz_167; - _zz_168[6] = _zz_167; - _zz_168[5] = _zz_167; - _zz_168[4] = _zz_167; - _zz_168[3] = _zz_167; - _zz_168[2] = _zz_167; - _zz_168[1] = _zz_167; - _zz_168[0] = _zz_167; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_ENCODING) + assign _zz_168 = _zz_360[7]; + always @ (*) begin + _zz_169[23] = _zz_168; + _zz_169[22] = _zz_168; + _zz_169[21] = _zz_168; + _zz_169[20] = _zz_168; + _zz_169[19] = _zz_168; + _zz_169[18] = _zz_168; + _zz_169[17] = _zz_168; + _zz_169[16] = _zz_168; + _zz_169[15] = _zz_168; + _zz_169[14] = _zz_168; + _zz_169[13] = _zz_168; + _zz_169[12] = _zz_168; + _zz_169[11] = _zz_168; + _zz_169[10] = _zz_168; + _zz_169[9] = _zz_168; + _zz_169[8] = _zz_168; + _zz_169[7] = _zz_168; + _zz_169[6] = _zz_168; + _zz_169[5] = _zz_168; + _zz_169[4] = _zz_168; + _zz_169[3] = _zz_168; + _zz_169[2] = _zz_168; + _zz_169[1] = _zz_168; + _zz_169[0] = _zz_168; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_169 = execute_RS2; + _zz_170 = execute_RS2; end default : begin - _zz_169 = {_zz_168,execute_INSTRUCTION[31 : 20]}; + _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_169; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4554,7 +4587,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_274) + case(_zz_276) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4568,7 +4601,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_274) + case(_zz_276) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4587,12 +4620,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_358) + $signed(_zz_359)); + assign writeBack_MulPlugin_result = ($signed(_zz_361) + $signed(_zz_362)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_253)begin - if(_zz_275)begin + if(_zz_255)begin + if(_zz_277)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4600,7 +4633,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_276)begin + if(_zz_278)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4611,28 +4644,28 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_363); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_366); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_170 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_170[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_364); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_365 : _zz_366); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_367[31:0]; - assign _zz_171 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_172 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_173 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_367); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_368 : _zz_369); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_370[31:0]; + assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_174[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_174[31 : 0] = execute_RS1; + _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_175[31 : 0] = execute_RS1; end - assign _zz_176 = (_zz_175 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_176 != 32'h0); + assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_177 != 32'h0); assign _zz_29 = decode_SRC1_CTRL; assign _zz_27 = _zz_56; assign _zz_43 = decode_to_execute_SRC1_CTRL; @@ -4660,9 +4693,9 @@ module VexRiscv_inner ( assign _zz_34 = decode_to_execute_ENV_CTRL; assign _zz_33 = execute_to_memory_ENV_CTRL; assign _zz_35 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_ENCODING; + assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; assign _zz_1 = _zz_49; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_ENCODING; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4684,272 +4717,272 @@ module VexRiscv_inner ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_177 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_177[12 : 0] = 13'h1000; - _zz_177[25 : 20] = 6'h20; + _zz_178[12 : 0] = 13'h1000; + _zz_178[25 : 20] = 6'h20; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_178[3 : 0] = 4'b1011; + _zz_179[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_179[4 : 0] = 5'h16; + _zz_180[4 : 0] = 5'h16; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_180[5 : 0] = 6'h21; + _zz_181[5 : 0] = 6'h21; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_181[31 : 30] = CsrPlugin_misa_base; - _zz_181[25 : 0] = CsrPlugin_misa_extensions; + _zz_182[31 : 30] = CsrPlugin_misa_base; + _zz_182[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_182[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_182[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_182[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_183[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_183[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_183[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_183[11 : 11] = CsrPlugin_mip_MEIP; - _zz_183[7 : 7] = CsrPlugin_mip_MTIP; - _zz_183[3 : 3] = CsrPlugin_mip_MSIP; + _zz_184[11 : 11] = CsrPlugin_mip_MEIP; + _zz_184[7 : 7] = CsrPlugin_mip_MTIP; + _zz_184[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_184[11 : 11] = CsrPlugin_mie_MEIE; - _zz_184[7 : 7] = CsrPlugin_mie_MTIE; - _zz_184[3 : 3] = CsrPlugin_mie_MSIE; + _zz_185[11 : 11] = CsrPlugin_mie_MEIE; + _zz_185[7 : 7] = CsrPlugin_mie_MTIE; + _zz_185[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_185[31 : 2] = CsrPlugin_mtvec_base; - _zz_185[1 : 0] = CsrPlugin_mtvec_mode; + _zz_186[31 : 2] = CsrPlugin_mtvec_base; + _zz_186[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_186[31 : 0] = CsrPlugin_mepc; + _zz_187[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_187[31 : 0] = CsrPlugin_mscratch; + _zz_188[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_188[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_188[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_189[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_189[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_189[31 : 0] = CsrPlugin_mtval; + _zz_190[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_191[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_192[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_193[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_194[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_195[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_196[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_197[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_198[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_199 = 32'h0; if(execute_CsrPlugin_csr_2820)begin - _zz_198[31 : 0] = _zz_151; + _zz_199[31 : 0] = _zz_152; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_200 = 32'h0; if(execute_CsrPlugin_csr_2822)begin - _zz_199[31 : 0] = _zz_153; + _zz_200[31 : 0] = _zz_154; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_201 = 32'h0; if(execute_CsrPlugin_csr_2824)begin - _zz_200[31 : 0] = _zz_155; + _zz_201[31 : 0] = _zz_156; end end always @ (*) begin - _zz_201 = 32'h0; + _zz_202 = 32'h0; if(execute_CsrPlugin_csr_2826)begin - _zz_201[31 : 0] = _zz_157; + _zz_202[31 : 0] = _zz_158; end end always @ (*) begin - _zz_202 = 32'h0; + _zz_203 = 32'h0; if(execute_CsrPlugin_csr_2828)begin - _zz_202[31 : 0] = _zz_159; + _zz_203[31 : 0] = _zz_160; end end always @ (*) begin - _zz_203 = 32'h0; + _zz_204 = 32'h0; if(execute_CsrPlugin_csr_2830)begin - _zz_203[31 : 0] = _zz_161; + _zz_204[31 : 0] = _zz_162; end end always @ (*) begin - _zz_204 = 32'h0; + _zz_205 = 32'h0; if(execute_CsrPlugin_csr_2832)begin - _zz_204[31 : 0] = _zz_163; + _zz_205[31 : 0] = _zz_164; end end always @ (*) begin - _zz_205 = 32'h0; + _zz_206 = 32'h0; if(execute_CsrPlugin_csr_2834)begin - _zz_205[31 : 0] = _zz_165; + _zz_206[31 : 0] = _zz_166; end end always @ (*) begin - _zz_206 = 32'h0; + _zz_207 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_206[31 : 0] = _zz_175; + _zz_207[31 : 0] = _zz_176; end end always @ (*) begin - _zz_207 = 32'h0; + _zz_208 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_207[31 : 0] = _zz_176; + _zz_208[31 : 0] = _zz_177; end end - assign execute_CsrPlugin_readData = (((((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_580 | _zz_181) | (_zz_182 | _zz_183))) | (((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191)))) | ((((_zz_192 | _zz_193) | (_zz_194 | _zz_195)) | ((_zz_196 | _zz_197) | (_zz_198 | _zz_199))) | (((_zz_200 | _zz_201) | (_zz_202 | _zz_203)) | ((_zz_204 | _zz_205) | (_zz_206 | _zz_207))))); - assign iBusWishbone_ADR = {_zz_384,_zz_208}; - assign iBusWishbone_CTI = ((_zz_208 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_178 | _zz_179) | (_zz_180 | _zz_181)) | ((_zz_586 | _zz_182) | (_zz_183 | _zz_184))) | (((_zz_185 | _zz_186) | (_zz_187 | _zz_188)) | ((_zz_189 | _zz_190) | (_zz_191 | _zz_192)))) | ((((_zz_193 | _zz_194) | (_zz_195 | _zz_196)) | ((_zz_197 | _zz_198) | (_zz_199 | _zz_200))) | (((_zz_201 | _zz_202) | (_zz_203 | _zz_204)) | ((_zz_205 | _zz_206) | (_zz_207 | _zz_208))))); + assign iBusWishbone_ADR = {_zz_387,_zz_209}; + assign iBusWishbone_CTI = ((_zz_209 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_277)begin + if(_zz_279)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_277)begin + if(_zz_279)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_209; + assign iBus_rsp_valid = _zz_210; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_215 = (dBus_cmd_payload_length != 3'b000); - assign _zz_211 = dBus_cmd_valid; - assign _zz_213 = dBus_cmd_payload_wr; - assign _zz_214 = (_zz_210 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_212 && (_zz_213 || _zz_214)); - assign dBusWishbone_ADR = ((_zz_215 ? {{dBus_cmd_payload_address[31 : 5],_zz_210},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_215 ? (_zz_214 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_216 = (dBus_cmd_payload_length != 3'b000); + assign _zz_212 = dBus_cmd_valid; + assign _zz_214 = dBus_cmd_payload_wr; + assign _zz_215 = (_zz_211 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_213 && (_zz_214 || _zz_215)); + assign dBusWishbone_ADR = ((_zz_216 ? {{dBus_cmd_payload_address[31 : 5],_zz_211},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_216 ? (_zz_215 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_213 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_213; + assign dBusWishbone_SEL = (_zz_214 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_214; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_212 = (_zz_211 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_211; - assign dBusWishbone_STB = _zz_211; - assign dBus_rsp_valid = _zz_216; + assign _zz_213 = (_zz_212 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_212; + assign dBusWishbone_STB = _zz_212; + assign dBus_rsp_valid = _zz_217; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4971,8 +5004,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; DBusCachedPlugin_rspCounter <= _zz_87; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_107 <= 1'b1; - _zz_119 <= 1'b0; + _zz_108 <= 1'b1; + _zz_120 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4996,15 +5029,15 @@ module VexRiscv_inner ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_175 <= 32'h0; + _zz_176 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_208 <= 3'b000; - _zz_209 <= 1'b0; - _zz_210 <= 3'b000; - _zz_216 <= 1'b0; + _zz_209 <= 3'b000; + _zz_210 <= 1'b0; + _zz_211 <= 3'b000; + _zz_217 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5085,7 +5118,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_278)begin + if(_zz_280)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5094,8 +5127,8 @@ module VexRiscv_inner ( if(dBus_rsp_valid)begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_107 <= 1'b0; - _zz_119 <= (_zz_47 && writeBack_arbitration_isFiring); + _zz_108 <= 1'b0; + _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5117,14 +5150,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_279)begin - if(_zz_280)begin + if(_zz_281)begin + if(_zz_282)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_281)begin + if(_zz_283)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_282)begin + if(_zz_284)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5149,7 +5182,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_261)begin + if(_zz_263)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5160,8 +5193,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_262)begin - case(_zz_263) + if(_zz_264)begin + case(_zz_265) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5171,7 +5204,7 @@ module VexRiscv_inner ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_146,{_zz_145,_zz_144}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -5187,7 +5220,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_283)begin + if(_zz_285)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; @@ -5221,35 +5254,35 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_377[0]; - CsrPlugin_mstatus_MIE <= _zz_378[0]; + CsrPlugin_mstatus_MPIE <= _zz_380[0]; + CsrPlugin_mstatus_MIE <= _zz_381[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_380[0]; - CsrPlugin_mie_MTIE <= _zz_381[0]; - CsrPlugin_mie_MSIE <= _zz_382[0]; + CsrPlugin_mie_MEIE <= _zz_383[0]; + CsrPlugin_mie_MTIE <= _zz_384[0]; + CsrPlugin_mie_MSIE <= _zz_385[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_175 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_277)begin + if(_zz_279)begin if(iBusWishbone_ACK)begin - _zz_208 <= (_zz_208 + 3'b001); + _zz_209 <= (_zz_209 + 3'b001); end end - _zz_209 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_211 && _zz_212))begin - _zz_210 <= (_zz_210 + 3'b001); - if(_zz_214)begin - _zz_210 <= 3'b000; + _zz_210 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_212 && _zz_213))begin + _zz_211 <= (_zz_211 + 3'b001); + if(_zz_215)begin + _zz_211 <= 3'b000; end end - _zz_216 <= ((_zz_211 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_217 <= ((_zz_212 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5263,7 +5296,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_278)begin + if(_zz_280)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5281,8 +5314,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - _zz_120 <= _zz_46[11 : 7]; - _zz_121 <= _zz_57; + _zz_121 <= _zz_46[11 : 7]; + _zz_122 <= _zz_57; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5290,37 +5323,37 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_258)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_260)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + if(_zz_262)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(_zz_260)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; end if(DBusCachedPlugin_exceptionBus_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_279)begin - if(_zz_280)begin + if(_zz_281)begin + if(_zz_282)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_281)begin + if(_zz_283)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_282)begin + if(_zz_284)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_261)begin + if(_zz_263)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5334,31 +5367,31 @@ module VexRiscv_inner ( end endcase end - if(_zz_152[0])begin - _zz_151 <= (_zz_151 + 32'h00000001); + if(_zz_153[0])begin + _zz_152 <= (_zz_152 + 32'h00000001); end - if(_zz_154[0])begin - _zz_153 <= (_zz_153 + 32'h00000001); + if(_zz_155[0])begin + _zz_154 <= (_zz_154 + 32'h00000001); end - if(_zz_156[0])begin - _zz_155 <= (_zz_155 + 32'h00000001); + if(_zz_157[0])begin + _zz_156 <= (_zz_156 + 32'h00000001); end - if(_zz_158[0])begin - _zz_157 <= (_zz_157 + 32'h00000001); + if(_zz_159[0])begin + _zz_158 <= (_zz_158 + 32'h00000001); end - if(_zz_160[0])begin - _zz_159 <= (_zz_159 + 32'h00000001); + if(_zz_161[0])begin + _zz_160 <= (_zz_160 + 32'h00000001); end - if(_zz_162[0])begin - _zz_161 <= (_zz_161 + 32'h00000001); + if(_zz_163[0])begin + _zz_162 <= (_zz_162 + 32'h00000001); end - if(_zz_164[0])begin - _zz_163 <= (_zz_163 + 32'h00000001); + if(_zz_165[0])begin + _zz_164 <= (_zz_164 + 32'h00000001); end - if(_zz_166[0])begin - _zz_165 <= (_zz_165 + 32'h00000001); + if(_zz_167[0])begin + _zz_166 <= (_zz_166 + 32'h00000001); end - if(_zz_283)begin + if(_zz_285)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5368,20 +5401,20 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_253)begin - if(_zz_275)begin + if(_zz_255)begin + if(_zz_277)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_368[31:0]; + memory_DivPlugin_div_result <= _zz_371[31:0]; end end end - if(_zz_276)begin + if(_zz_278)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_173 ? (~ _zz_174) : _zz_174) + _zz_374); - memory_DivPlugin_rs2 <= ((_zz_172 ? (~ execute_RS2) : execute_RS2) + _zz_376); - memory_DivPlugin_div_needRevert <= ((_zz_173 ^ (_zz_172 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_377); + memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_379); + memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5406,10 +5439,10 @@ module VexRiscv_inner ( decode_to_execute_FORMAL_PC_NEXT <= _zz_60; end if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + execute_to_memory_FORMAL_PC_NEXT <= _zz_59; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_59; + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; @@ -5496,7 +5529,10 @@ module VexRiscv_inner ( decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENCODING <= _zz_2; + decode_to_execute_CfuPlugin_CFU_ENCODING <= decode_CfuPlugin_CFU_ENCODING; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_MUL <= decode_IS_MUL; @@ -5552,12 +5588,6 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; - end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; end @@ -5701,7 +5731,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_379[0]; + CsrPlugin_mip_MSIP <= _zz_382[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5722,7 +5752,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_383[0]; + CsrPlugin_mcause_interrupt <= _zz_386[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5753,82 +5783,82 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_2820)begin if(execute_CsrPlugin_writeEnable)begin - _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2821)begin if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2822)begin if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2823)begin if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2824)begin if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2825)begin if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2826)begin if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2827)begin if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2828)begin if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2829)begin if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2830)begin if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2831)begin if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2832)begin if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2833)begin if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2834)begin if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2835)begin if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index 65743dd..f7381ba 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : 767476cae91f564ec9eab25516eb1664b04c1224 `define Input2Kind_defaultEncoding_type [0:0] @@ -54,7 +54,7 @@ module VexRiscv_inner ( input softwareInterrupt, output CfuPlugin_bus_cmd_valid, input CfuPlugin_bus_cmd_ready, - output [19:0] CfuPlugin_bus_cmd_payload_function_id, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, input CfuPlugin_bus_rsp_valid, @@ -95,7 +95,6 @@ module VexRiscv_inner ( input reset, input debugReset ); - wire _zz_220; wire _zz_221; wire _zz_222; wire _zz_223; @@ -103,16 +102,16 @@ module VexRiscv_inner ( wire _zz_225; wire _zz_226; wire _zz_227; - reg _zz_228; - wire _zz_229; - wire [31:0] _zz_230; - wire _zz_231; - wire [31:0] _zz_232; - reg _zz_233; - wire _zz_234; + wire _zz_228; + reg _zz_229; + wire _zz_230; + wire [31:0] _zz_231; + wire _zz_232; + wire [31:0] _zz_233; + reg _zz_234; wire _zz_235; - wire [31:0] _zz_236; - wire _zz_237; + wire _zz_236; + wire [31:0] _zz_237; wire _zz_238; wire _zz_239; wire _zz_240; @@ -120,12 +119,14 @@ module VexRiscv_inner ( wire _zz_242; wire _zz_243; wire _zz_244; - wire [3:0] _zz_245; - wire _zz_246; + wire _zz_245; + wire [3:0] _zz_246; wire _zz_247; - reg [31:0] _zz_248; + wire _zz_248; reg [31:0] _zz_249; reg [31:0] _zz_250; + reg [31:0] _zz_251; + reg [9:0] _zz_252; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -158,8 +159,6 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_251; - wire _zz_252; wire _zz_253; wire _zz_254; wire _zz_255; @@ -176,9 +175,9 @@ module VexRiscv_inner ( wire _zz_266; wire _zz_267; wire _zz_268; - wire [1:0] _zz_269; + wire _zz_269; wire _zz_270; - wire _zz_271; + wire [1:0] _zz_271; wire _zz_272; wire _zz_273; wire _zz_274; @@ -187,34 +186,34 @@ module VexRiscv_inner ( wire _zz_277; wire _zz_278; wire _zz_279; - wire [1:0] _zz_280; + wire _zz_280; wire _zz_281; - wire _zz_282; - wire [5:0] _zz_283; + wire [1:0] _zz_282; + wire _zz_283; wire _zz_284; - wire _zz_285; + wire [5:0] _zz_285; wire _zz_286; wire _zz_287; wire _zz_288; wire _zz_289; wire _zz_290; - wire [1:0] _zz_291; + wire _zz_291; wire _zz_292; wire [1:0] _zz_293; - wire [51:0] _zz_294; - wire [51:0] _zz_295; + wire _zz_294; + wire [1:0] _zz_295; wire [51:0] _zz_296; - wire [32:0] _zz_297; + wire [51:0] _zz_297; wire [51:0] _zz_298; - wire [49:0] _zz_299; + wire [32:0] _zz_299; wire [51:0] _zz_300; wire [49:0] _zz_301; wire [51:0] _zz_302; - wire [32:0] _zz_303; - wire [31:0] _zz_304; + wire [49:0] _zz_303; + wire [51:0] _zz_304; wire [32:0] _zz_305; - wire [0:0] _zz_306; - wire [0:0] _zz_307; + wire [31:0] _zz_306; + wire [32:0] _zz_307; wire [0:0] _zz_308; wire [0:0] _zz_309; wire [0:0] _zz_310; @@ -232,135 +231,135 @@ module VexRiscv_inner ( wire [0:0] _zz_322; wire [0:0] _zz_323; wire [0:0] _zz_324; - wire [3:0] _zz_325; - wire [2:0] _zz_326; - wire [31:0] _zz_327; - wire [11:0] _zz_328; + wire [0:0] _zz_325; + wire [0:0] _zz_326; + wire [3:0] _zz_327; + wire [2:0] _zz_328; wire [31:0] _zz_329; - wire [19:0] _zz_330; - wire [11:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [19:0] _zz_334; - wire [11:0] _zz_335; - wire [2:0] _zz_336; - wire [2:0] _zz_337; - wire [0:0] _zz_338; + wire [11:0] _zz_330; + wire [31:0] _zz_331; + wire [19:0] _zz_332; + wire [11:0] _zz_333; + wire [31:0] _zz_334; + wire [31:0] _zz_335; + wire [19:0] _zz_336; + wire [11:0] _zz_337; + wire [2:0] _zz_338; wire [2:0] _zz_339; - wire [4:0] _zz_340; - wire [11:0] _zz_341; - wire [11:0] _zz_342; - wire [31:0] _zz_343; - wire [31:0] _zz_344; + wire [0:0] _zz_340; + wire [2:0] _zz_341; + wire [4:0] _zz_342; + wire [11:0] _zz_343; + wire [11:0] _zz_344; wire [31:0] _zz_345; wire [31:0] _zz_346; wire [31:0] _zz_347; wire [31:0] _zz_348; wire [31:0] _zz_349; - wire [11:0] _zz_350; - wire [19:0] _zz_351; + wire [31:0] _zz_350; + wire [31:0] _zz_351; wire [11:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; + wire [19:0] _zz_353; + wire [11:0] _zz_354; wire [31:0] _zz_355; - wire [11:0] _zz_356; - wire [19:0] _zz_357; + wire [31:0] _zz_356; + wire [31:0] _zz_357; wire [11:0] _zz_358; - wire [2:0] _zz_359; - wire [1:0] _zz_360; - wire [1:0] _zz_361; + wire [19:0] _zz_359; + wire [11:0] _zz_360; + wire [2:0] _zz_361; wire [1:0] _zz_362; wire [1:0] _zz_363; - wire [19:0] _zz_364; - wire [11:0] _zz_365; - wire [65:0] _zz_366; - wire [65:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; - wire [0:0] _zz_370; - wire [5:0] _zz_371; - wire [32:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; + wire [1:0] _zz_364; + wire [1:0] _zz_365; + wire [9:0] _zz_366; + wire [3:0] _zz_367; + wire [7:0] _zz_368; + wire [65:0] _zz_369; + wire [65:0] _zz_370; + wire [31:0] _zz_371; + wire [31:0] _zz_372; + wire [0:0] _zz_373; + wire [5:0] _zz_374; wire [32:0] _zz_375; - wire [32:0] _zz_376; - wire [32:0] _zz_377; + wire [31:0] _zz_376; + wire [31:0] _zz_377; wire [32:0] _zz_378; - wire [0:0] _zz_379; + wire [32:0] _zz_379; wire [32:0] _zz_380; - wire [0:0] _zz_381; - wire [32:0] _zz_382; - wire [0:0] _zz_383; - wire [31:0] _zz_384; - wire [0:0] _zz_385; + wire [32:0] _zz_381; + wire [0:0] _zz_382; + wire [32:0] _zz_383; + wire [0:0] _zz_384; + wire [32:0] _zz_385; wire [0:0] _zz_386; - wire [0:0] _zz_387; + wire [31:0] _zz_387; wire [0:0] _zz_388; wire [0:0] _zz_389; wire [0:0] _zz_390; wire [0:0] _zz_391; - wire [26:0] _zz_392; - wire _zz_393; - wire _zz_394; - wire [1:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire _zz_399; - wire [0:0] _zz_400; - wire [14:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [8:0] _zz_407; - wire [31:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire _zz_411; - wire [0:0] _zz_412; - wire [2:0] _zz_413; + wire [0:0] _zz_392; + wire [0:0] _zz_393; + wire [0:0] _zz_394; + wire [26:0] _zz_395; + wire _zz_396; + wire _zz_397; + wire [1:0] _zz_398; + wire [31:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; + wire _zz_402; + wire [0:0] _zz_403; + wire [15:0] _zz_404; + wire [31:0] _zz_405; + wire [31:0] _zz_406; + wire [31:0] _zz_407; + wire _zz_408; + wire [0:0] _zz_409; + wire [9:0] _zz_410; + wire [31:0] _zz_411; + wire [31:0] _zz_412; + wire [31:0] _zz_413; wire _zz_414; - wire _zz_415; - wire _zz_416; - wire [31:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire _zz_420; + wire [0:0] _zz_415; + wire [3:0] _zz_416; + wire _zz_417; + wire _zz_418; + wire _zz_419; + wire [31:0] _zz_420; wire [0:0] _zz_421; - wire [28:0] _zz_422; - wire [0:0] _zz_423; + wire [0:0] _zz_422; + wire _zz_423; wire [0:0] _zz_424; - wire [0:0] _zz_425; - wire [0:0] _zz_426; - wire _zz_427; - wire [0:0] _zz_428; - wire [23:0] _zz_429; - wire [31:0] _zz_430; + wire [29:0] _zz_425; + wire [1:0] _zz_426; + wire [1:0] _zz_427; + wire _zz_428; + wire [0:0] _zz_429; + wire [24:0] _zz_430; wire [31:0] _zz_431; wire [31:0] _zz_432; - wire _zz_433; + wire [31:0] _zz_433; wire _zz_434; - wire [0:0] _zz_435; + wire _zz_435; wire [0:0] _zz_436; wire [0:0] _zz_437; wire [0:0] _zz_438; - wire _zz_439; - wire [0:0] _zz_440; - wire [20:0] _zz_441; - wire [31:0] _zz_442; + wire [0:0] _zz_439; + wire _zz_440; + wire [0:0] _zz_441; + wire [20:0] _zz_442; wire [31:0] _zz_443; - wire _zz_444; + wire [31:0] _zz_444; wire _zz_445; - wire [0:0] _zz_446; - wire [1:0] _zz_447; - wire [0:0] _zz_448; + wire _zz_446; + wire [0:0] _zz_447; + wire [1:0] _zz_448; wire [0:0] _zz_449; - wire _zz_450; - wire [0:0] _zz_451; - wire [17:0] _zz_452; - wire [31:0] _zz_453; + wire [0:0] _zz_450; + wire _zz_451; + wire [0:0] _zz_452; + wire [17:0] _zz_453; wire [31:0] _zz_454; wire [31:0] _zz_455; wire [31:0] _zz_456; @@ -368,36 +367,36 @@ module VexRiscv_inner ( wire [31:0] _zz_458; wire [31:0] _zz_459; wire [31:0] _zz_460; - wire _zz_461; - wire [1:0] _zz_462; + wire [31:0] _zz_461; + wire _zz_462; wire [1:0] _zz_463; - wire _zz_464; - wire [0:0] _zz_465; - wire [14:0] _zz_466; - wire [31:0] _zz_467; + wire [1:0] _zz_464; + wire _zz_465; + wire [0:0] _zz_466; + wire [14:0] _zz_467; wire [31:0] _zz_468; wire [31:0] _zz_469; wire [31:0] _zz_470; wire [31:0] _zz_471; wire [31:0] _zz_472; - wire [0:0] _zz_473; - wire [1:0] _zz_474; - wire [4:0] _zz_475; + wire [31:0] _zz_473; + wire [0:0] _zz_474; + wire [1:0] _zz_475; wire [4:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [11:0] _zz_479; - wire [31:0] _zz_480; + wire [4:0] _zz_477; + wire _zz_478; + wire [0:0] _zz_479; + wire [11:0] _zz_480; wire [31:0] _zz_481; wire [31:0] _zz_482; wire [31:0] _zz_483; wire [31:0] _zz_484; wire [31:0] _zz_485; - wire _zz_486; - wire [0:0] _zz_487; - wire [1:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; + wire [31:0] _zz_486; + wire [31:0] _zz_487; + wire _zz_488; + wire [0:0] _zz_489; + wire [1:0] _zz_490; wire [0:0] _zz_491; wire [4:0] _zz_492; wire [4:0] _zz_493; @@ -418,7 +417,7 @@ module VexRiscv_inner ( wire [0:0] _zz_508; wire [2:0] _zz_509; wire [0:0] _zz_510; - wire [4:0] _zz_511; + wire [5:0] _zz_511; wire [1:0] _zz_512; wire [1:0] _zz_513; wire _zz_514; @@ -437,7 +436,7 @@ module VexRiscv_inner ( wire [0:0] _zz_527; wire _zz_528; wire [0:0] _zz_529; - wire [2:0] _zz_530; + wire [3:0] _zz_530; wire _zz_531; wire [0:0] _zz_532; wire [0:0] _zz_533; @@ -461,7 +460,7 @@ module VexRiscv_inner ( wire [31:0] _zz_551; wire _zz_552; wire [0:0] _zz_553; - wire [0:0] _zz_554; + wire [1:0] _zz_554; wire [31:0] _zz_555; wire [31:0] _zz_556; wire [31:0] _zz_557; @@ -474,37 +473,45 @@ module VexRiscv_inner ( wire [0:0] _zz_564; wire [2:0] _zz_565; wire [31:0] _zz_566; - wire [31:0] _zz_567; - wire [31:0] _zz_568; + wire _zz_567; + wire _zz_568; wire [31:0] _zz_569; - wire [31:0] _zz_570; - wire [31:0] _zz_571; - wire _zz_572; - wire [0:0] _zz_573; - wire [1:0] _zz_574; - wire _zz_575; - wire [2:0] _zz_576; - wire [2:0] _zz_577; - wire _zz_578; - wire [0:0] _zz_579; - wire [0:0] _zz_580; + wire _zz_570; + wire [0:0] _zz_571; + wire [1:0] _zz_572; + wire _zz_573; + wire [2:0] _zz_574; + wire [2:0] _zz_575; + wire _zz_576; + wire [0:0] _zz_577; + wire [0:0] _zz_578; + wire [31:0] _zz_579; + wire [31:0] _zz_580; wire [31:0] _zz_581; wire [31:0] _zz_582; wire [31:0] _zz_583; - wire [31:0] _zz_584; - wire [31:0] _zz_585; + wire _zz_584; + wire _zz_585; wire [31:0] _zz_586; - wire [31:0] _zz_587; - wire _zz_588; - wire _zz_589; - wire _zz_590; + wire _zz_587; + wire [0:0] _zz_588; + wire [0:0] _zz_589; + wire [0:0] _zz_590; wire [0:0] _zz_591; - wire [0:0] _zz_592; - wire _zz_593; - wire _zz_594; - wire _zz_595; - wire _zz_596; + wire [1:0] _zz_592; + wire [1:0] _zz_593; + wire [0:0] _zz_594; + wire [0:0] _zz_595; + wire [31:0] _zz_596; wire [31:0] _zz_597; + wire [31:0] _zz_598; + wire [31:0] _zz_599; + wire [31:0] _zz_600; + wire [31:0] _zz_601; + wire _zz_602; + wire _zz_603; + wire _zz_604; + wire [31:0] _zz_605; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -513,8 +520,6 @@ module VexRiscv_inner ( wire [31:0] execute_MUL_LL; wire writeBack_CfuPlugin_CFU_IN_FLIGHT; wire execute_CfuPlugin_CFU_IN_FLIGHT; - wire [31:0] execute_BRANCH_CALC; - wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; wire [1:0] memory_MEMORY_ADDRESS_LOW; @@ -530,10 +535,11 @@ module VexRiscv_inner ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_ENCODING; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; wire `Input2Kind_defaultEncoding_type _zz_1; wire `Input2Kind_defaultEncoding_type _zz_2; wire `Input2Kind_defaultEncoding_type _zz_3; + wire [0:0] decode_CfuPlugin_CFU_ENCODING; wire decode_CfuPlugin_CFU_ENABLE; wire `EnvCtrlEnum_defaultEncoding_type _zz_4; wire `EnvCtrlEnum_defaultEncoding_type _zz_5; @@ -596,8 +602,9 @@ module VexRiscv_inner ( reg _zz_30; reg _zz_31; wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_ENCODING; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; wire `Input2Kind_defaultEncoding_type _zz_32; + wire [0:0] execute_CfuPlugin_CFU_ENCODING; wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; @@ -608,8 +615,8 @@ module VexRiscv_inner ( wire `EnvCtrlEnum_defaultEncoding_type _zz_34; wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_35; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; @@ -808,7 +815,7 @@ module VexRiscv_inner ( wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; + reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; reg CsrPlugin_inWfi /* verilator public */ ; @@ -970,20 +977,21 @@ module VexRiscv_inner ( wire _zz_92; reg [31:0] _zz_93; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [34:0] _zz_94; + wire [35:0] _zz_94; wire _zz_95; wire _zz_96; wire _zz_97; wire _zz_98; wire _zz_99; - wire `Src1CtrlEnum_defaultEncoding_type _zz_100; - wire `AluCtrlEnum_defaultEncoding_type _zz_101; - wire `Src2CtrlEnum_defaultEncoding_type _zz_102; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; - wire `BranchCtrlEnum_defaultEncoding_type _zz_105; - wire `EnvCtrlEnum_defaultEncoding_type _zz_106; - wire `Input2Kind_defaultEncoding_type _zz_107; + wire _zz_100; + wire `Src1CtrlEnum_defaultEncoding_type _zz_101; + wire `AluCtrlEnum_defaultEncoding_type _zz_102; + wire `Src2CtrlEnum_defaultEncoding_type _zz_103; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_104; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_105; + wire `BranchCtrlEnum_defaultEncoding_type _zz_106; + wire `EnvCtrlEnum_defaultEncoding_type _zz_107; + wire `Input2Kind_defaultEncoding_type _zz_108; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -991,52 +999,52 @@ module VexRiscv_inner ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_108; + reg _zz_109; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_109; reg [31:0] _zz_110; - wire _zz_111; - reg [19:0] _zz_112; - wire _zz_113; - reg [19:0] _zz_114; - reg [31:0] _zz_115; + reg [31:0] _zz_111; + wire _zz_112; + reg [19:0] _zz_113; + wire _zz_114; + reg [19:0] _zz_115; + reg [31:0] _zz_116; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_116; - wire [31:0] execute_FullBarrelShifterPlugin_reversed; reg [31:0] _zz_117; - reg _zz_118; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_118; reg _zz_119; reg _zz_120; - reg [4:0] _zz_121; - reg [31:0] _zz_122; - wire _zz_123; + reg _zz_121; + reg [4:0] _zz_122; + reg [31:0] _zz_123; wire _zz_124; wire _zz_125; wire _zz_126; wire _zz_127; wire _zz_128; + wire _zz_129; wire execute_BranchPlugin_eq; - wire [2:0] _zz_129; - reg _zz_130; + wire [2:0] _zz_130; reg _zz_131; - wire _zz_132; - reg [19:0] _zz_133; - wire _zz_134; - reg [10:0] _zz_135; - wire _zz_136; - reg [18:0] _zz_137; - reg _zz_138; + reg _zz_132; + wire _zz_133; + reg [19:0] _zz_134; + wire _zz_135; + reg [10:0] _zz_136; + wire _zz_137; + reg [18:0] _zz_138; + reg _zz_139; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_139; - reg [19:0] _zz_140; - wire _zz_141; - reg [10:0] _zz_142; - wire _zz_143; - reg [18:0] _zz_144; + wire _zz_140; + reg [19:0] _zz_141; + wire _zz_142; + reg [10:0] _zz_143; + wire _zz_144; + reg [18:0] _zz_145; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1058,9 +1066,9 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_145; wire _zz_146; wire _zz_147; + wire _zz_148; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1073,10 +1081,10 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_148; - wire _zz_149; - wire [1:0] _zz_150; - wire _zz_151; + wire [1:0] _zz_149; + wire _zz_150; + wire [1:0] _zz_151; + wire _zz_152; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1105,7 +1113,6 @@ module VexRiscv_inner ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_152; reg [31:0] _zz_153; reg [31:0] _zz_154; reg [31:0] _zz_155; @@ -1121,13 +1128,15 @@ module VexRiscv_inner ( reg [31:0] _zz_165; reg [31:0] _zz_166; reg [31:0] _zz_167; + reg [31:0] _zz_168; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; - wire [19:0] execute_CfuPlugin_functionsIds_0; - wire _zz_168; - reg [19:0] _zz_169; - reg [31:0] _zz_170; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire [9:0] execute_CfuPlugin_functionsIds_1; + wire _zz_169; + reg [23:0] _zz_170; + reg [31:0] _zz_171; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1159,18 +1168,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_171; + wire [31:0] _zz_172; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_172; - wire _zz_173; + wire [31:0] _zz_173; wire _zz_174; - reg [32:0] _zz_175; + wire _zz_175; + reg [32:0] _zz_176; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_176; - wire [31:0] _zz_177; + reg [31:0] _zz_177; + wire [31:0] _zz_178; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1180,7 +1189,7 @@ module VexRiscv_inner ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_178; + reg _zz_179; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1220,7 +1229,8 @@ module VexRiscv_inner ( reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_ENCODING; + reg [0:0] decode_to_execute_CfuPlugin_CFU_ENCODING; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; reg decode_to_execute_IS_MUL; reg execute_to_memory_IS_MUL; reg memory_to_writeBack_IS_MUL; @@ -1240,8 +1250,6 @@ module VexRiscv_inner ( reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_BRANCH_DO; - reg [31:0] execute_to_memory_BRANCH_CALC; reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; reg [31:0] execute_to_memory_MUL_LL; @@ -1250,7 +1258,7 @@ module VexRiscv_inner ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_179; + reg [2:0] _zz_180; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; @@ -1291,7 +1299,6 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_180; reg [31:0] _zz_181; reg [31:0] _zz_182; reg [31:0] _zz_183; @@ -1322,19 +1329,20 @@ module VexRiscv_inner ( reg [31:0] _zz_208; reg [31:0] _zz_209; reg [31:0] _zz_210; - reg [2:0] _zz_211; - reg _zz_212; + reg [31:0] _zz_211; + reg [2:0] _zz_212; + reg _zz_213; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_213; - wire _zz_214; + reg [2:0] _zz_214; wire _zz_215; wire _zz_216; wire _zz_217; wire _zz_218; - reg _zz_219; + wire _zz_219; + reg _zz_220; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] decode_CfuPlugin_CFU_ENCODING_string; + reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; reg [39:0] _zz_3_string; @@ -1370,7 +1378,7 @@ module VexRiscv_inner ( reg [95:0] _zz_27_string; reg [95:0] _zz_28_string; reg [95:0] _zz_29_string; - reg [39:0] execute_CfuPlugin_CFU_ENCODING_string; + reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] _zz_32_string; reg [39:0] memory_ENV_CTRL_string; reg [39:0] _zz_33_string; @@ -1402,14 +1410,14 @@ module VexRiscv_inner ( reg [95:0] _zz_56_string; reg [31:0] decode_BRANCH_CTRL_string; reg [31:0] _zz_58_string; - reg [95:0] _zz_100_string; - reg [63:0] _zz_101_string; - reg [23:0] _zz_102_string; - reg [39:0] _zz_103_string; - reg [71:0] _zz_104_string; - reg [31:0] _zz_105_string; - reg [39:0] _zz_106_string; + reg [95:0] _zz_101_string; + reg [63:0] _zz_102_string; + reg [23:0] _zz_103_string; + reg [39:0] _zz_104_string; + reg [71:0] _zz_105_string; + reg [31:0] _zz_106_string; reg [39:0] _zz_107_string; + reg [39:0] _zz_108_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1420,256 +1428,254 @@ module VexRiscv_inner ( reg [39:0] decode_to_execute_ENV_CTRL_string; reg [39:0] execute_to_memory_ENV_CTRL_string; reg [39:0] memory_to_writeBack_ENV_CTRL_string; - reg [39:0] decode_to_execute_CfuPlugin_CFU_ENCODING_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; `endif (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_251 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_253 = 1'b1; - assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_256 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_257 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_258 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_259 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_260 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_261 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_262 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_263 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_264 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_265 = ({CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_268 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_269 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_270 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_271 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_272 = (1'b0 || (! 1'b1)); - assign _zz_273 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_274 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_275 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_276 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_277 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_278 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_280 = execute_INSTRUCTION[13 : 12]; - assign _zz_281 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_282 = (! memory_arbitration_isStuck); - assign _zz_283 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_284 = (iBus_cmd_valid || (_zz_211 != 3'b000)); - assign _zz_285 = (_zz_247 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_286 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_287 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_288 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_289 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_290 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_291 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_292 = execute_INSTRUCTION[13]; + assign _zz_253 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_254 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_255 = 1'b1; + assign _zz_256 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_257 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_258 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_259 = ((_zz_226 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_260 = ((_zz_226 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_261 = ((_zz_226 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_262 = ((_zz_226 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_263 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_264 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_265 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_266 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_267 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_268 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_269 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_270 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_271 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_272 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_273 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_274 = (1'b0 || (! 1'b1)); + assign _zz_275 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_276 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_277 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_278 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_279 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_280 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_281 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_282 = execute_INSTRUCTION[13 : 12]; + assign _zz_283 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_284 = (! memory_arbitration_isStuck); + assign _zz_285 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_286 = (iBus_cmd_valid || (_zz_212 != 3'b000)); + assign _zz_287 = (_zz_248 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_288 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_289 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_290 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_291 = ((_zz_148 && 1'b1) && (! 1'b0)); + assign _zz_292 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); assign _zz_293 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_294 = ($signed(_zz_295) + $signed(_zz_300)); - assign _zz_295 = ($signed(_zz_296) + $signed(_zz_298)); - assign _zz_296 = 52'h0; - assign _zz_297 = {1'b0,memory_MUL_LL}; - assign _zz_298 = {{19{_zz_297[32]}}, _zz_297}; - assign _zz_299 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; - assign _zz_301 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_294 = execute_INSTRUCTION[13]; + assign _zz_295 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_296 = ($signed(_zz_297) + $signed(_zz_302)); + assign _zz_297 = ($signed(_zz_298) + $signed(_zz_300)); + assign _zz_298 = 52'h0; + assign _zz_299 = {1'b0,memory_MUL_LL}; + assign _zz_300 = {{19{_zz_299[32]}}, _zz_299}; + assign _zz_301 = ({16'd0,memory_MUL_LH} <<< 16); assign _zz_302 = {{2{_zz_301[49]}}, _zz_301}; - assign _zz_303 = ($signed(_zz_305) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_304 = _zz_303[31 : 0]; - assign _zz_305 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_306 = _zz_94[33 : 33]; - assign _zz_307 = _zz_94[32 : 32]; - assign _zz_308 = _zz_94[31 : 31]; - assign _zz_309 = _zz_94[30 : 30]; - assign _zz_310 = _zz_94[28 : 28]; - assign _zz_311 = _zz_94[25 : 25]; - assign _zz_312 = _zz_94[17 : 17]; - assign _zz_313 = _zz_94[16 : 16]; - assign _zz_314 = _zz_94[13 : 13]; - assign _zz_315 = _zz_94[12 : 12]; - assign _zz_316 = _zz_94[11 : 11]; - assign _zz_317 = _zz_94[34 : 34]; - assign _zz_318 = _zz_94[15 : 15]; - assign _zz_319 = _zz_94[5 : 5]; - assign _zz_320 = _zz_94[3 : 3]; - assign _zz_321 = _zz_94[20 : 20]; - assign _zz_322 = _zz_94[10 : 10]; - assign _zz_323 = _zz_94[4 : 4]; - assign _zz_324 = _zz_94[0 : 0]; - assign _zz_325 = (_zz_62 - 4'b0001); - assign _zz_326 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_327 = {29'd0, _zz_326}; - assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_329 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_331 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_332 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_333 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_334 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_335 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_338 = execute_SRC_LESS; - assign _zz_339 = 3'b100; - assign _zz_340 = execute_INSTRUCTION[19 : 15]; - assign _zz_341 = execute_INSTRUCTION[31 : 20]; - assign _zz_342 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_343 = ($signed(_zz_344) + $signed(_zz_347)); - assign _zz_344 = ($signed(_zz_345) + $signed(_zz_346)); - assign _zz_345 = execute_SRC1; - assign _zz_346 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_347 = (execute_SRC_USE_SUB_LESS ? _zz_348 : _zz_349); - assign _zz_348 = 32'h00000001; - assign _zz_349 = 32'h0; - assign _zz_350 = execute_INSTRUCTION[31 : 20]; - assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_353 = {_zz_133,execute_INSTRUCTION[31 : 20]}; - assign _zz_354 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_355 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_356 = execute_INSTRUCTION[31 : 20]; - assign _zz_357 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_359 = 3'b100; - assign _zz_360 = (_zz_148 & (~ _zz_361)); - assign _zz_361 = (_zz_148 - 2'b01); - assign _zz_362 = (_zz_150 & (~ _zz_363)); - assign _zz_363 = (_zz_150 - 2'b01); - assign _zz_364 = execute_INSTRUCTION[31 : 12]; - assign _zz_365 = execute_INSTRUCTION[31 : 20]; - assign _zz_366 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_367 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_368 = writeBack_MUL_LOW[31 : 0]; - assign _zz_369 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_370 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_371 = {5'd0, _zz_370}; - assign _zz_372 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_373 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_374 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_375 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_376 = _zz_377; - assign _zz_377 = _zz_378; - assign _zz_378 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_380); - assign _zz_379 = memory_DivPlugin_div_needRevert; - assign _zz_380 = {32'd0, _zz_379}; - assign _zz_381 = _zz_174; - assign _zz_382 = {32'd0, _zz_381}; - assign _zz_383 = _zz_173; - assign _zz_384 = {31'd0, _zz_383}; - assign _zz_385 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_386 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_387 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_388 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_303 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_304 = {{2{_zz_303[49]}}, _zz_303}; + assign _zz_305 = ($signed(_zz_307) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_306 = _zz_305[31 : 0]; + assign _zz_307 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_308 = _zz_94[34 : 34]; + assign _zz_309 = _zz_94[33 : 33]; + assign _zz_310 = _zz_94[32 : 32]; + assign _zz_311 = _zz_94[31 : 31]; + assign _zz_312 = _zz_94[28 : 28]; + assign _zz_313 = _zz_94[25 : 25]; + assign _zz_314 = _zz_94[17 : 17]; + assign _zz_315 = _zz_94[16 : 16]; + assign _zz_316 = _zz_94[13 : 13]; + assign _zz_317 = _zz_94[12 : 12]; + assign _zz_318 = _zz_94[11 : 11]; + assign _zz_319 = _zz_94[35 : 35]; + assign _zz_320 = _zz_94[15 : 15]; + assign _zz_321 = _zz_94[5 : 5]; + assign _zz_322 = _zz_94[3 : 3]; + assign _zz_323 = _zz_94[20 : 20]; + assign _zz_324 = _zz_94[10 : 10]; + assign _zz_325 = _zz_94[4 : 4]; + assign _zz_326 = _zz_94[0 : 0]; + assign _zz_327 = (_zz_62 - 4'b0001); + assign _zz_328 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_329 = {29'd0, _zz_328}; + assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_331 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_332 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_333 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_334 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_335 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_336 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_337 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_338 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_339 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_340 = execute_SRC_LESS; + assign _zz_341 = 3'b100; + assign _zz_342 = execute_INSTRUCTION[19 : 15]; + assign _zz_343 = execute_INSTRUCTION[31 : 20]; + assign _zz_344 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_345 = ($signed(_zz_346) + $signed(_zz_349)); + assign _zz_346 = ($signed(_zz_347) + $signed(_zz_348)); + assign _zz_347 = execute_SRC1; + assign _zz_348 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_349 = (execute_SRC_USE_SUB_LESS ? _zz_350 : _zz_351); + assign _zz_350 = 32'h00000001; + assign _zz_351 = 32'h0; + assign _zz_352 = execute_INSTRUCTION[31 : 20]; + assign _zz_353 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_354 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_355 = {_zz_134,execute_INSTRUCTION[31 : 20]}; + assign _zz_356 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_357 = {{_zz_138,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_358 = execute_INSTRUCTION[31 : 20]; + assign _zz_359 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_360 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_361 = 3'b100; + assign _zz_362 = (_zz_149 & (~ _zz_363)); + assign _zz_363 = (_zz_149 - 2'b01); + assign _zz_364 = (_zz_151 & (~ _zz_365)); + assign _zz_365 = (_zz_151 - 2'b01); + assign _zz_366 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_367 = execute_INSTRUCTION[23 : 20]; + assign _zz_368 = execute_INSTRUCTION[31 : 24]; + assign _zz_369 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_370 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_371 = writeBack_MUL_LOW[31 : 0]; + assign _zz_372 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_373 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_374 = {5'd0, _zz_373}; + assign _zz_375 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_376 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_377 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_378 = {_zz_172,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_379 = _zz_380; + assign _zz_380 = _zz_381; + assign _zz_381 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_173) : _zz_173)} + _zz_383); + assign _zz_382 = memory_DivPlugin_div_needRevert; + assign _zz_383 = {32'd0, _zz_382}; + assign _zz_384 = _zz_175; + assign _zz_385 = {32'd0, _zz_384}; + assign _zz_386 = _zz_174; + assign _zz_387 = {31'd0, _zz_386}; + assign _zz_388 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_389 = execute_CsrPlugin_writeData[3 : 3]; assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_391 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_392 = (iBus_cmd_payload_address >>> 5); - assign _zz_393 = 1'b1; - assign _zz_394 = 1'b1; - assign _zz_395 = {_zz_66,_zz_65}; - assign _zz_396 = 32'h0000106f; - assign _zz_397 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_398 = 32'h00001073; - assign _zz_399 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_400 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_401 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_402) == 32'h00000003),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; - assign _zz_402 = 32'h0000207f; - assign _zz_403 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_404 = 32'h00000003; - assign _zz_405 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_406 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_407 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_408) == 32'h00005013),{(_zz_409 == _zz_410),{_zz_411,{_zz_412,_zz_413}}}}}}; - assign _zz_408 = 32'hbc00707f; - assign _zz_409 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_410 = 32'h00001013; - assign _zz_411 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_412 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_413 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; - assign _zz_414 = decode_INSTRUCTION[31]; - assign _zz_415 = decode_INSTRUCTION[31]; - assign _zz_416 = decode_INSTRUCTION[7]; - assign _zz_417 = 32'h10103050; - assign _zz_418 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_419 = 1'b0; - assign _zz_420 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_421 = 1'b0; - assign _zz_422 = {(_zz_98 != 1'b0),{({_zz_423,_zz_424} != 2'b00),{(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}}}; - assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h10000050); - assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00000050); - assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00000050); - assign _zz_426 = 1'b0; - assign _zz_427 = ({_zz_433,_zz_434} != 2'b00); - assign _zz_428 = ({_zz_435,_zz_436} != 2'b00); - assign _zz_429 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; - assign _zz_430 = 32'h10203050; - assign _zz_431 = 32'h10103050; - assign _zz_432 = 32'h00103050; - assign _zz_433 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_434 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_435 = _zz_97; - assign _zz_436 = ((decode_INSTRUCTION & _zz_442) == 32'h00000004); - assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000040); - assign _zz_438 = 1'b0; - assign _zz_439 = ({_zz_444,_zz_445} != 2'b00); - assign _zz_440 = ({_zz_446,_zz_447} != 3'b000); - assign _zz_441 = {(_zz_448 != _zz_449),{_zz_450,{_zz_451,_zz_452}}}; - assign _zz_442 = 32'h0000001c; - assign _zz_443 = 32'h00000058; - assign _zz_444 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_445 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h40001010); - assign _zz_447 = {(_zz_454 == _zz_455),(_zz_456 == _zz_457)}; - assign _zz_448 = ((decode_INSTRUCTION & _zz_458) == 32'h00000024); - assign _zz_449 = 1'b0; - assign _zz_450 = ((_zz_459 == _zz_460) != 1'b0); - assign _zz_451 = (_zz_461 != 1'b0); - assign _zz_452 = {(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}; - assign _zz_453 = 32'h40003054; - assign _zz_454 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_455 = 32'h00001010; - assign _zz_456 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_457 = 32'h00001010; - assign _zz_458 = 32'h00000064; - assign _zz_459 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_460 = 32'h00001000; - assign _zz_461 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_462 = {(_zz_467 == _zz_468),(_zz_469 == _zz_470)}; - assign _zz_463 = 2'b00; - assign _zz_464 = ((_zz_471 == _zz_472) != 1'b0); - assign _zz_465 = ({_zz_473,_zz_474} != 3'b000); - assign _zz_466 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; - assign _zz_467 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_468 = 32'h00002000; - assign _zz_469 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_470 = 32'h00001000; - assign _zz_471 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_472 = 32'h00004004; - assign _zz_473 = _zz_98; - assign _zz_474 = {(_zz_480 == _zz_481),(_zz_482 == _zz_483)}; - assign _zz_475 = {(_zz_484 == _zz_485),{_zz_486,{_zz_487,_zz_488}}}; - assign _zz_476 = 5'h0; - assign _zz_477 = ((_zz_489 == _zz_490) != 1'b0); - assign _zz_478 = ({_zz_491,_zz_492} != 6'h0); - assign _zz_479 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; - assign _zz_480 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_481 = 32'h00000020; - assign _zz_482 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_483 = 32'h00000020; - assign _zz_484 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_485 = 32'h00002040; - assign _zz_486 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); - assign _zz_487 = (_zz_499 == _zz_500); - assign _zz_488 = {_zz_501,_zz_502}; - assign _zz_489 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_490 = 32'h00000020; + assign _zz_391 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_392 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_393 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_394 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_395 = (iBus_cmd_payload_address >>> 5); + assign _zz_396 = 1'b1; + assign _zz_397 = 1'b1; + assign _zz_398 = {_zz_66,_zz_65}; + assign _zz_399 = 32'h0000106f; + assign _zz_400 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_401 = 32'h00001073; + assign _zz_402 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_403 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_404 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_405) == 32'h00000003),{(_zz_406 == _zz_407),{_zz_408,{_zz_409,_zz_410}}}}}}; + assign _zz_405 = 32'h0000207f; + assign _zz_406 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_407 = 32'h00000003; + assign _zz_408 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_409 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_410 = {((decode_INSTRUCTION & 32'h00007077) == 32'h00000023),{((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_411) == 32'h0000500f),{(_zz_412 == _zz_413),{_zz_414,{_zz_415,_zz_416}}}}}}; + assign _zz_411 = 32'h01f0707f; + assign _zz_412 = (decode_INSTRUCTION & 32'hbc00707f); + assign _zz_413 = 32'h00005013; + assign _zz_414 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); + assign _zz_415 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_416 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}}; + assign _zz_417 = decode_INSTRUCTION[31]; + assign _zz_418 = decode_INSTRUCTION[31]; + assign _zz_419 = decode_INSTRUCTION[7]; + assign _zz_420 = 32'h10103050; + assign _zz_421 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_422 = 1'b0; + assign _zz_423 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_424 = (_zz_99 != 1'b0); + assign _zz_425 = {(_zz_99 != 1'b0),{(_zz_97 != 1'b0),{(_zz_426 != _zz_427),{_zz_428,{_zz_429,_zz_430}}}}}; + assign _zz_426 = {((decode_INSTRUCTION & _zz_431) == 32'h10000050),((decode_INSTRUCTION & _zz_432) == 32'h00000050)}; + assign _zz_427 = 2'b00; + assign _zz_428 = (((decode_INSTRUCTION & _zz_433) == 32'h00000050) != 1'b0); + assign _zz_429 = ({_zz_434,_zz_435} != 2'b00); + assign _zz_430 = {({_zz_436,_zz_437} != 2'b00),{(_zz_438 != _zz_439),{_zz_440,{_zz_441,_zz_442}}}}; + assign _zz_431 = 32'h10203050; + assign _zz_432 = 32'h10103050; + assign _zz_433 = 32'h00103050; + assign _zz_434 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_435 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_436 = _zz_98; + assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000004); + assign _zz_438 = ((decode_INSTRUCTION & _zz_444) == 32'h00000040); + assign _zz_439 = 1'b0; + assign _zz_440 = ({_zz_445,_zz_446} != 2'b00); + assign _zz_441 = ({_zz_447,_zz_448} != 3'b000); + assign _zz_442 = {(_zz_449 != _zz_450),{_zz_451,{_zz_452,_zz_453}}}; + assign _zz_443 = 32'h0000001c; + assign _zz_444 = 32'h00000058; + assign _zz_445 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_446 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_447 = ((decode_INSTRUCTION & _zz_454) == 32'h40001010); + assign _zz_448 = {(_zz_455 == _zz_456),(_zz_457 == _zz_458)}; + assign _zz_449 = ((decode_INSTRUCTION & _zz_459) == 32'h00000024); + assign _zz_450 = 1'b0; + assign _zz_451 = ((_zz_460 == _zz_461) != 1'b0); + assign _zz_452 = (_zz_462 != 1'b0); + assign _zz_453 = {(_zz_463 != _zz_464),{_zz_465,{_zz_466,_zz_467}}}; + assign _zz_454 = 32'h40003054; + assign _zz_455 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_456 = 32'h00001010; + assign _zz_457 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_458 = 32'h00001010; + assign _zz_459 = 32'h00000064; + assign _zz_460 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_461 = 32'h00001000; + assign _zz_462 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_463 = {(_zz_468 == _zz_469),(_zz_470 == _zz_471)}; + assign _zz_464 = 2'b00; + assign _zz_465 = ((_zz_472 == _zz_473) != 1'b0); + assign _zz_466 = ({_zz_474,_zz_475} != 3'b000); + assign _zz_467 = {(_zz_476 != _zz_477),{_zz_478,{_zz_479,_zz_480}}}; + assign _zz_468 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_469 = 32'h00002000; + assign _zz_470 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_471 = 32'h00001000; + assign _zz_472 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_473 = 32'h00004004; + assign _zz_474 = ((decode_INSTRUCTION & _zz_481) == 32'h00000008); + assign _zz_475 = {(_zz_482 == _zz_483),(_zz_484 == _zz_485)}; + assign _zz_476 = {(_zz_486 == _zz_487),{_zz_488,{_zz_489,_zz_490}}}; + assign _zz_477 = 5'h0; + assign _zz_478 = (_zz_99 != 1'b0); + assign _zz_479 = ({_zz_491,_zz_492} != 6'h0); + assign _zz_480 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; + assign _zz_481 = 32'h0000002c; + assign _zz_482 = (decode_INSTRUCTION & 32'h00000054); + assign _zz_483 = 32'h00000040; + assign _zz_484 = (decode_INSTRUCTION & 32'h0000006c); + assign _zz_485 = 32'h00000020; + assign _zz_486 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_487 = 32'h00002040; + assign _zz_488 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); + assign _zz_489 = (_zz_499 == _zz_500); + assign _zz_490 = {_zz_501,_zz_502}; assign _zz_491 = (_zz_503 == _zz_504); assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; assign _zz_493 = {_zz_96,{_zz_508,_zz_509}}; assign _zz_494 = 5'h0; - assign _zz_495 = ({_zz_510,_zz_511} != 6'h0); + assign _zz_495 = ({_zz_510,_zz_511} != 7'h0); assign _zz_496 = (_zz_512 != _zz_513); assign _zz_497 = {_zz_514,{_zz_515,_zz_516}}; assign _zz_498 = 32'h00001040; @@ -1684,7 +1690,7 @@ module VexRiscv_inner ( assign _zz_507 = {_zz_520,{_zz_521,_zz_522}}; assign _zz_508 = (_zz_523 == _zz_524); assign _zz_509 = {_zz_525,{_zz_526,_zz_527}}; - assign _zz_510 = _zz_97; + assign _zz_510 = _zz_98; assign _zz_511 = {_zz_528,{_zz_529,_zz_530}}; assign _zz_512 = {_zz_96,_zz_531}; assign _zz_513 = 2'b00; @@ -1721,66 +1727,74 @@ module VexRiscv_inner ( assign _zz_544 = 32'h00001030; assign _zz_545 = (decode_INSTRUCTION & 32'h02002060); assign _zz_546 = 32'h00002020; - assign _zz_547 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_547 = (decode_INSTRUCTION & 32'h02003028); assign _zz_548 = 32'h00000020; assign _zz_549 = 32'h00001010; assign _zz_550 = (decode_INSTRUCTION & 32'h00002010); assign _zz_551 = 32'h00002010; assign _zz_552 = ((decode_INSTRUCTION & _zz_566) == 32'h00000010); - assign _zz_553 = (_zz_567 == _zz_568); - assign _zz_554 = (_zz_569 == _zz_570); + assign _zz_553 = _zz_97; + assign _zz_554 = {_zz_567,_zz_568}; assign _zz_555 = 32'h00000070; assign _zz_556 = (decode_INSTRUCTION & 32'h00000020); assign _zz_557 = 32'h0; assign _zz_558 = (decode_INSTRUCTION & 32'h00004014); assign _zz_559 = 32'h00004010; - assign _zz_560 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); - assign _zz_561 = {_zz_572,{_zz_573,_zz_574}}; + assign _zz_560 = ((decode_INSTRUCTION & _zz_569) == 32'h00002010); + assign _zz_561 = {_zz_570,{_zz_571,_zz_572}}; assign _zz_562 = 4'b0000; - assign _zz_563 = (_zz_575 != 1'b0); - assign _zz_564 = (_zz_576 != _zz_577); - assign _zz_565 = {_zz_578,{_zz_579,_zz_580}}; + assign _zz_563 = (_zz_573 != 1'b0); + assign _zz_564 = (_zz_574 != _zz_575); + assign _zz_565 = {_zz_576,{_zz_577,_zz_578}}; assign _zz_566 = 32'h00000050; - assign _zz_567 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_568 = 32'h00000004; - assign _zz_569 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_570 = 32'h0; - assign _zz_571 = 32'h00006014; - assign _zz_572 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_573 = ((decode_INSTRUCTION & _zz_581) == 32'h0); - assign _zz_574 = {(_zz_582 == _zz_583),(_zz_584 == _zz_585)}; - assign _zz_575 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_576 = {(_zz_586 == _zz_587),{_zz_588,_zz_589}}; - assign _zz_577 = 3'b000; - assign _zz_578 = ({_zz_590,_zz_95} != 2'b00); - assign _zz_579 = ({_zz_591,_zz_592} != 2'b00); - assign _zz_580 = (_zz_593 != 1'b0); - assign _zz_581 = 32'h00000018; - assign _zz_582 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_583 = 32'h00002000; - assign _zz_584 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_585 = 32'h00001000; - assign _zz_586 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_587 = 32'h00000040; - assign _zz_588 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_589 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_590 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_591 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_592 = _zz_95; - assign _zz_593 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); - assign _zz_594 = execute_INSTRUCTION[31]; - assign _zz_595 = execute_INSTRUCTION[31]; - assign _zz_596 = execute_INSTRUCTION[7]; - assign _zz_597 = 32'h0; + assign _zz_567 = ((decode_INSTRUCTION & _zz_579) == 32'h00000004); + assign _zz_568 = ((decode_INSTRUCTION & _zz_580) == 32'h0); + assign _zz_569 = 32'h00006014; + assign _zz_570 = ((decode_INSTRUCTION & _zz_581) == 32'h0); + assign _zz_571 = (_zz_582 == _zz_583); + assign _zz_572 = {_zz_584,_zz_585}; + assign _zz_573 = ((decode_INSTRUCTION & _zz_586) == 32'h0); + assign _zz_574 = {_zz_587,{_zz_588,_zz_589}}; + assign _zz_575 = 3'b000; + assign _zz_576 = ({_zz_590,_zz_591} != 2'b00); + assign _zz_577 = (_zz_592 != _zz_593); + assign _zz_578 = (_zz_594 != _zz_595); + assign _zz_579 = 32'h0000000c; + assign _zz_580 = 32'h00000028; + assign _zz_581 = 32'h00000044; + assign _zz_582 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_583 = 32'h0; + assign _zz_584 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_585 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_586 = 32'h00000058; + assign _zz_587 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_588 = ((decode_INSTRUCTION & _zz_596) == 32'h00002010); + assign _zz_589 = ((decode_INSTRUCTION & _zz_597) == 32'h40000030); + assign _zz_590 = ((decode_INSTRUCTION & _zz_598) == 32'h00000004); + assign _zz_591 = _zz_95; + assign _zz_592 = {(_zz_599 == _zz_600),_zz_95}; + assign _zz_593 = 2'b00; + assign _zz_594 = ((decode_INSTRUCTION & _zz_601) == 32'h00001004); + assign _zz_595 = 1'b0; + assign _zz_596 = 32'h00002014; + assign _zz_597 = 32'h40000034; + assign _zz_598 = 32'h00000014; + assign _zz_599 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_600 = 32'h00000004; + assign _zz_601 = 32'h00005054; + assign _zz_602 = execute_INSTRUCTION[31]; + assign _zz_603 = execute_INSTRUCTION[31]; + assign _zz_604 = execute_INSTRUCTION[7]; + assign _zz_605 = 32'h0; always @ (posedge clk) begin - if(_zz_393) begin - _zz_248 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_396) begin + _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_394) begin - _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_397) begin + _zz_250 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1791,13 +1805,13 @@ module VexRiscv_inner ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_220 ), //i - .io_cpu_prefetch_isValid (_zz_221 ), //i + .io_flush (_zz_221 ), //i + .io_cpu_prefetch_isValid (_zz_222 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_222 ), //i - .io_cpu_fetch_isStuck (_zz_223 ), //i - .io_cpu_fetch_isRemoved (_zz_224 ), //i + .io_cpu_fetch_isValid (_zz_223 ), //i + .io_cpu_fetch_isStuck (_zz_224 ), //i + .io_cpu_fetch_isRemoved (_zz_225 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1810,8 +1824,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_225 ), //i - .io_cpu_decode_isStuck (_zz_226 ), //i + .io_cpu_decode_isValid (_zz_226 ), //i + .io_cpu_decode_isStuck (_zz_227 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1819,8 +1833,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_227 ), //i - .io_cpu_fill_valid (_zz_228 ), //i + .io_cpu_decode_isUser (_zz_228 ), //i + .io_cpu_fill_valid (_zz_229 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1829,26 +1843,26 @@ module VexRiscv_inner ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_16 (_zz_179[2:0] ), //i + ._zz_16 (_zz_180[2:0] ), //i ._zz_17 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_229 ), //i - .io_cpu_execute_address (_zz_230[31:0] ), //i + .io_cpu_execute_isValid (_zz_230 ), //i + .io_cpu_execute_address (_zz_231[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_89[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_231 ), //i + .io_cpu_memory_isValid (_zz_232 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_232[31:0] ), //i + .io_cpu_memory_address (_zz_233[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_233 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_234 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1856,31 +1870,31 @@ module VexRiscv_inner ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_234 ), //i + .io_cpu_writeBack_isValid (_zz_235 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_235 ), //i + .io_cpu_writeBack_isUser (_zz_236 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_236[31:0] ), //i + .io_cpu_writeBack_address (_zz_237[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_237 ), //i - .io_cpu_writeBack_fence_SR (_zz_238 ), //i - .io_cpu_writeBack_fence_SO (_zz_239 ), //i - .io_cpu_writeBack_fence_SI (_zz_240 ), //i - .io_cpu_writeBack_fence_PW (_zz_241 ), //i - .io_cpu_writeBack_fence_PR (_zz_242 ), //i - .io_cpu_writeBack_fence_PO (_zz_243 ), //i - .io_cpu_writeBack_fence_PI (_zz_244 ), //i - .io_cpu_writeBack_fence_FM (_zz_245[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_238 ), //i + .io_cpu_writeBack_fence_SR (_zz_239 ), //i + .io_cpu_writeBack_fence_SO (_zz_240 ), //i + .io_cpu_writeBack_fence_SI (_zz_241 ), //i + .io_cpu_writeBack_fence_PW (_zz_242 ), //i + .io_cpu_writeBack_fence_PR (_zz_243 ), //i + .io_cpu_writeBack_fence_PO (_zz_244 ), //i + .io_cpu_writeBack_fence_PI (_zz_245 ), //i + .io_cpu_writeBack_fence_FM (_zz_246[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_246 ), //i + .io_cpu_flush_valid (_zz_247 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_247 ), //i + .io_mem_cmd_ready (_zz_248 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1896,28 +1910,39 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_395) + case(_zz_398) 2'b00 : begin - _zz_250 = DBusCachedPlugin_redoBranch_payload; + _zz_251 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_250 = CsrPlugin_jumpInterface_payload; + _zz_251 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_250 = BranchPlugin_jumpInterface_payload; + _zz_251 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_251 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(execute_CfuPlugin_CFU_ENCODING) + 1'b0 : begin + _zz_252 = execute_CfuPlugin_functionsIds_0; end default : begin - _zz_250 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_252 = execute_CfuPlugin_functionsIds_1; end endcase end `ifndef SYNTHESIS always @(*) begin - case(decode_CfuPlugin_CFU_ENCODING) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_ENCODING_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_ENCODING_string = "IMM_I"; - default : decode_CfuPlugin_CFU_ENCODING_string = "?????"; + case(decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin @@ -2222,10 +2247,10 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(execute_CfuPlugin_CFU_ENCODING) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_ENCODING_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_ENCODING_string = "IMM_I"; - default : execute_CfuPlugin_CFU_ENCODING_string = "?????"; + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin @@ -2497,74 +2522,74 @@ module VexRiscv_inner ( default : _zz_58_string = "????"; endcase end - always @(*) begin - case(_zz_100) - `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; - default : _zz_100_string = "????????????"; - endcase - end always @(*) begin case(_zz_101) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; - default : _zz_101_string = "????????"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_101_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_101_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_101_string = "URS1 "; + default : _zz_101_string = "????????????"; endcase end always @(*) begin case(_zz_102) - `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; - default : _zz_102_string = "???"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_102_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_102_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_102_string = "BITWISE "; + default : _zz_102_string = "????????"; endcase end always @(*) begin case(_zz_103) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; - default : _zz_103_string = "?????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_103_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_103_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_103_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_103_string = "PC "; + default : _zz_103_string = "???"; endcase end always @(*) begin case(_zz_104) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; - default : _zz_104_string = "?????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_104_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_104_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_104_string = "AND_1"; + default : _zz_104_string = "?????"; endcase end always @(*) begin case(_zz_105) - `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; - default : _zz_105_string = "????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_105_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_105_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_105_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_105_string = "SRA_1 "; + default : _zz_105_string = "?????????"; endcase end always @(*) begin case(_zz_106) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; - default : _zz_106_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_106_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_106_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_106_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_106_string = "JALR"; + default : _zz_106_string = "????"; endcase end always @(*) begin case(_zz_107) - `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_107_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_107_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_107_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_107_string = "ECALL"; default : _zz_107_string = "?????"; endcase end + always @(*) begin + case(_zz_108) + `Input2Kind_defaultEncoding_RS : _zz_108_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_108_string = "IMM_I"; + default : _zz_108_string = "?????"; + endcase + end always @(*) begin case(decode_to_execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; @@ -2654,15 +2679,15 @@ module VexRiscv_inner ( endcase end always @(*) begin - case(decode_to_execute_CfuPlugin_CFU_ENCODING) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "IMM_I"; - default : decode_to_execute_CfuPlugin_CFU_ENCODING_string = "?????"; + case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_294) + $signed(_zz_302)); + assign memory_MUL_LOW = ($signed(_zz_296) + $signed(_zz_304)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2670,44 +2695,43 @@ module VexRiscv_inner ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_304; - assign execute_REGFILE_WRITE_DATA = _zz_109; + assign execute_SHIFT_RIGHT = _zz_306; + assign execute_REGFILE_WRITE_DATA = _zz_110; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_230[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_231[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_306[0]; - assign decode_IS_RS1_SIGNED = _zz_307[0]; - assign decode_IS_DIV = _zz_308[0]; + assign decode_IS_RS2_SIGNED = _zz_308[0]; + assign decode_IS_RS1_SIGNED = _zz_309[0]; + assign decode_IS_DIV = _zz_310[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_309[0]; - assign decode_CfuPlugin_CFU_ENCODING = _zz_1; + assign decode_IS_MUL = _zz_311[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_310[0]; + assign decode_CfuPlugin_CFU_ENCODING = _zz_94[29 : 29]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_312[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_311[0]; + assign decode_IS_CSR = _zz_313[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_312[0]; - assign decode_MEMORY_MANAGMENT = _zz_313[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_314[0]; + assign decode_MEMORY_MANAGMENT = _zz_315[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_314[0]; + assign decode_MEMORY_WR = _zz_316[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_315[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_316[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_317[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_318[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2721,7 +2745,7 @@ module VexRiscv_inner ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_317[0]; + assign decode_IS_EBREAK = _zz_319[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2747,7 +2771,8 @@ module VexRiscv_inner ( end assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_ENCODING = _zz_32; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; + assign execute_CfuPlugin_CFU_ENCODING = decode_to_execute_CfuPlugin_CFU_ENCODING; assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; @@ -2755,18 +2780,18 @@ module VexRiscv_inner ( assign memory_ENV_CTRL = _zz_33; assign execute_ENV_CTRL = _zz_34; assign writeBack_ENV_CTRL = _zz_35; - assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; - assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_131; + assign execute_BRANCH_COND_RESULT = _zz_132; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_318[0]; - assign decode_RS1_USE = _zz_319[0]; + assign decode_RS2_USE = _zz_320[0]; + assign decode_RS1_USE = _zz_321[0]; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_251)begin + if(_zz_253)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2779,28 +2804,28 @@ module VexRiscv_inner ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_122; + if(_zz_121)begin + if((_zz_122 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_123; end end - if(_zz_252)begin - if(_zz_253)begin - if(_zz_124)begin + if(_zz_254)begin + if(_zz_255)begin + if(_zz_125)begin decode_RS2 = _zz_57; end end end - if(_zz_254)begin + if(_zz_256)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_126)begin + if(_zz_127)begin decode_RS2 = _zz_38; end end end - if(_zz_255)begin + if(_zz_257)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_128)begin + if(_zz_129)begin decode_RS2 = _zz_37; end end @@ -2809,28 +2834,28 @@ module VexRiscv_inner ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_122; + if(_zz_121)begin + if((_zz_122 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_123; end end - if(_zz_252)begin - if(_zz_253)begin - if(_zz_123)begin + if(_zz_254)begin + if(_zz_255)begin + if(_zz_124)begin decode_RS1 = _zz_57; end end end - if(_zz_254)begin + if(_zz_256)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin + if(_zz_126)begin decode_RS1 = _zz_38; end end end - if(_zz_255)begin + if(_zz_257)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin + if(_zz_128)begin decode_RS1 = _zz_37; end end @@ -2843,7 +2868,7 @@ module VexRiscv_inner ( if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_117; + _zz_38 = _zz_118; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin _zz_38 = memory_SHIFT_RIGHT; @@ -2855,7 +2880,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_256)begin + if(_zz_258)begin _zz_38 = memory_DivPlugin_div_result; end end @@ -2868,13 +2893,13 @@ module VexRiscv_inner ( assign _zz_41 = execute_PC; assign execute_SRC2_CTRL = _zz_42; assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_320[0]; - assign decode_SRC_ADD_ZERO = _zz_321[0]; + assign decode_SRC_USE_SUB_LESS = _zz_322[0]; + assign decode_SRC_ADD_ZERO = _zz_323[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_115; - assign execute_SRC1 = _zz_110; + assign execute_SRC2 = _zz_116; + assign execute_SRC1 = _zz_111; assign execute_ALU_BITWISE_CTRL = _zz_45; assign _zz_46 = writeBack_INSTRUCTION; assign _zz_47 = writeBack_REGFILE_WRITE_VALID; @@ -2887,25 +2912,25 @@ module VexRiscv_inner ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_322[0]; + decode_REGFILE_WRITE_VALID = _zz_324[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_399) == 32'h00000003),{(_zz_400 == _zz_401),{_zz_402,{_zz_403,_zz_404}}}}}}} != 23'h0); always @ (*) begin _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_293) + case(_zz_295) 2'b00 : begin - _zz_57 = _zz_368; + _zz_57 = _zz_371; end default : begin - _zz_57 = _zz_369; + _zz_57 = _zz_372; end endcase end @@ -2924,32 +2949,32 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_323[0]; - assign decode_FLUSH_ALL = _zz_324[0]; + assign decode_MEMORY_ENABLE = _zz_325[0]; + assign decode_FLUSH_ALL = _zz_326[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_257)begin + if(_zz_259)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_258)begin + if(_zz_260)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_259)begin + if(_zz_261)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_260)begin + if(_zz_262)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2957,7 +2982,7 @@ module VexRiscv_inner ( assign decode_BRANCH_CTRL = _zz_58; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_59 = memory_FORMAL_PC_NEXT; + _zz_59 = execute_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin _zz_59 = BranchPlugin_jumpInterface_payload; end @@ -2978,7 +3003,7 @@ module VexRiscv_inner ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_179) + case(_zz_180) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2989,7 +3014,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin + if((decode_arbitration_isValid && (_zz_119 || _zz_120)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -3002,7 +3027,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_261)begin + if(_zz_263)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3016,22 +3041,22 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(_zz_263)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_246 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_247 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_262)begin + if(_zz_264)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_251)begin + if(_zz_253)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3046,14 +3071,14 @@ module VexRiscv_inner ( if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_263)begin + if(_zz_265)begin execute_arbitration_haltByOther = 1'b1; end end always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(_zz_266)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -3063,8 +3088,8 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_263)begin - if(_zz_264)begin + if(_zz_265)begin + if(_zz_267)begin execute_arbitration_flushIt = 1'b1; end end @@ -3072,11 +3097,14 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_263)begin - if(_zz_264)begin + if(_zz_266)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_265)begin + if(_zz_267)begin execute_arbitration_flushNext = 1'b1; end end @@ -3089,7 +3117,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_256)begin + if(_zz_258)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3099,7 +3127,7 @@ module VexRiscv_inner ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_265)begin + if(CfuPlugin_joinException_valid)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3110,10 +3138,7 @@ module VexRiscv_inner ( assign memory_arbitration_flushIt = 1'b0; always @ (*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(_zz_265)begin + if(CfuPlugin_joinException_valid)begin memory_arbitration_flushNext = 1'b1; end end @@ -3151,10 +3176,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_266)begin + if(_zz_268)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_267)begin + if(_zz_269)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3168,21 +3193,21 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_266)begin + if(_zz_268)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_267)begin + if(_zz_269)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_263)begin - if(_zz_264)begin + if(_zz_265)begin + if(_zz_267)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_268)begin + if(_zz_270)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3203,7 +3228,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_262)begin + if(_zz_264)begin CsrPlugin_inWfi = 1'b1; end end @@ -3217,21 +3242,21 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_266)begin + if(_zz_268)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_267)begin + if(_zz_269)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_266)begin + if(_zz_268)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_267)begin - case(_zz_269) + if(_zz_269)begin + case(_zz_271) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3265,11 +3290,11 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_63 = (_zz_62 & (~ _zz_325)); + assign _zz_63 = (_zz_62 & (~ _zz_327)); assign _zz_64 = _zz_63[3]; assign _zz_65 = (_zz_63[1] || _zz_64); assign _zz_66 = (_zz_63[2] || _zz_64); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_250; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_251; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3289,7 +3314,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_327); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_329); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3381,7 +3406,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_179) + case(_zz_180) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3393,7 +3418,7 @@ module VexRiscv_inner ( endcase end - assign _zz_76 = _zz_328[11]; + assign _zz_76 = _zz_330[11]; always @ (*) begin _zz_77[18] = _zz_76; _zz_77[17] = _zz_76; @@ -3417,13 +3442,13 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_329[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_331[31])); if(_zz_82)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_78 = _zz_330[19]; + assign _zz_78 = _zz_332[19]; always @ (*) begin _zz_79[10] = _zz_78; _zz_79[9] = _zz_78; @@ -3438,7 +3463,7 @@ module VexRiscv_inner ( _zz_79[0] = _zz_78; end - assign _zz_80 = _zz_331[11]; + assign _zz_80 = _zz_333[11]; always @ (*) begin _zz_81[18] = _zz_80; _zz_81[17] = _zz_80; @@ -3464,16 +3489,16 @@ module VexRiscv_inner ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_82 = _zz_332[1]; + _zz_82 = _zz_334[1]; end default : begin - _zz_82 = _zz_333[1]; + _zz_82 = _zz_335[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_83 = _zz_334[19]; + assign _zz_83 = _zz_336[19]; always @ (*) begin _zz_84[10] = _zz_83; _zz_84[9] = _zz_83; @@ -3488,7 +3513,7 @@ module VexRiscv_inner ( _zz_84[0] = _zz_83; end - assign _zz_85 = _zz_335[11]; + assign _zz_85 = _zz_337[11]; always @ (*) begin _zz_86[18] = _zz_85; _zz_86[17] = _zz_85; @@ -3511,7 +3536,7 @@ module VexRiscv_inner ( _zz_86[0] = _zz_85; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_414,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_415,_zz_416},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_417,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_418,_zz_419},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3520,52 +3545,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_222; + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_223 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_224 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_223; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_225 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_226 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_227 = (CsrPlugin_privilege == 2'b00); + assign _zz_226 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_227 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_228 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_260)begin + if(_zz_262)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_258)begin + if(_zz_260)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_228 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_258)begin - _zz_228 = 1'b1; + _zz_229 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_260)begin + _zz_229 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_259)begin + if(_zz_261)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_257)begin + if(_zz_259)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_259)begin + if(_zz_261)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_257)begin + if(_zz_259)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3575,9 +3600,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_220 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_221 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_247 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_248 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3604,8 +3629,8 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_229 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_230 = execute_SRC_ADD; + assign _zz_230 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_231 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3620,27 +3645,27 @@ module VexRiscv_inner ( endcase end - assign _zz_246 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_231 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_232 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_231; + assign _zz_247 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_232 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_233 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_232; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_232; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_233; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_233 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_234 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_233 = 1'b1; + _zz_234 = 1'b1; end end - assign _zz_234 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_235 = (CsrPlugin_privilege == 2'b00); - assign _zz_236 = writeBack_REGFILE_WRITE_DATA; + assign _zz_235 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_236 = (CsrPlugin_privilege == 2'b00); + assign _zz_237 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_270)begin + if(_zz_272)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3650,7 +3675,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_270)begin + if(_zz_272)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3669,15 +3694,15 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_270)begin + if(_zz_272)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_338}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_339}; end end end @@ -3750,7 +3775,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_291) + case(_zz_293) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_91; end @@ -3783,50 +3808,51 @@ module VexRiscv_inner ( assign DBusCachedPlugin_mmuBus_busy = 1'b0; assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); assign _zz_96 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_94 = {(((decode_INSTRUCTION & _zz_417) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}; - assign _zz_100 = _zz_94[2 : 1]; - assign _zz_56 = _zz_100; - assign _zz_101 = _zz_94[7 : 6]; - assign _zz_55 = _zz_101; - assign _zz_102 = _zz_94[9 : 8]; - assign _zz_54 = _zz_102; - assign _zz_103 = _zz_94[19 : 18]; - assign _zz_53 = _zz_103; - assign _zz_104 = _zz_94[22 : 21]; - assign _zz_52 = _zz_104; - assign _zz_105 = _zz_94[24 : 23]; - assign _zz_51 = _zz_105; - assign _zz_106 = _zz_94[27 : 26]; - assign _zz_50 = _zz_106; - assign _zz_107 = _zz_94[29 : 29]; - assign _zz_49 = _zz_107; + assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_98 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_99 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_100 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_94 = {(((decode_INSTRUCTION & _zz_420) == 32'h00100050) != 1'b0),{(_zz_100 != 1'b0),{(_zz_100 != 1'b0),{(_zz_421 != _zz_422),{_zz_423,{_zz_424,_zz_425}}}}}}; + assign _zz_101 = _zz_94[2 : 1]; + assign _zz_56 = _zz_101; + assign _zz_102 = _zz_94[7 : 6]; + assign _zz_55 = _zz_102; + assign _zz_103 = _zz_94[9 : 8]; + assign _zz_54 = _zz_103; + assign _zz_104 = _zz_94[19 : 18]; + assign _zz_53 = _zz_104; + assign _zz_105 = _zz_94[22 : 21]; + assign _zz_52 = _zz_105; + assign _zz_106 = _zz_94[24 : 23]; + assign _zz_51 = _zz_106; + assign _zz_107 = _zz_94[27 : 26]; + assign _zz_50 = _zz_107; + assign _zz_108 = _zz_94[30 : 30]; + assign _zz_49 = _zz_108; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_248; - assign decode_RegFilePlugin_rs2Data = _zz_249; + assign decode_RegFilePlugin_rs1Data = _zz_249; + assign decode_RegFilePlugin_rs2Data = _zz_250; always @ (*) begin lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_108)begin + if(_zz_109)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_108)begin + if(_zz_109)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_108)begin + if(_zz_109)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -3848,13 +3874,13 @@ module VexRiscv_inner ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_109 = execute_IntAluPlugin_bitwise; + _zz_110 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_109 = {31'd0, _zz_338}; + _zz_110 = {31'd0, _zz_340}; end default : begin - _zz_109 = execute_SRC_ADD_SUB; + _zz_110 = execute_SRC_ADD_SUB; end endcase end @@ -3862,87 +3888,87 @@ module VexRiscv_inner ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_110 = execute_RS1; + _zz_111 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_110 = {29'd0, _zz_339}; + _zz_111 = {29'd0, _zz_341}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_111 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_110 = {27'd0, _zz_340}; + _zz_111 = {27'd0, _zz_342}; end endcase end - assign _zz_111 = _zz_341[11]; - always @ (*) begin - _zz_112[19] = _zz_111; - _zz_112[18] = _zz_111; - _zz_112[17] = _zz_111; - _zz_112[16] = _zz_111; - _zz_112[15] = _zz_111; - _zz_112[14] = _zz_111; - _zz_112[13] = _zz_111; - _zz_112[12] = _zz_111; - _zz_112[11] = _zz_111; - _zz_112[10] = _zz_111; - _zz_112[9] = _zz_111; - _zz_112[8] = _zz_111; - _zz_112[7] = _zz_111; - _zz_112[6] = _zz_111; - _zz_112[5] = _zz_111; - _zz_112[4] = _zz_111; - _zz_112[3] = _zz_111; - _zz_112[2] = _zz_111; - _zz_112[1] = _zz_111; - _zz_112[0] = _zz_111; - end - - assign _zz_113 = _zz_342[11]; - always @ (*) begin - _zz_114[19] = _zz_113; - _zz_114[18] = _zz_113; - _zz_114[17] = _zz_113; - _zz_114[16] = _zz_113; - _zz_114[15] = _zz_113; - _zz_114[14] = _zz_113; - _zz_114[13] = _zz_113; - _zz_114[12] = _zz_113; - _zz_114[11] = _zz_113; - _zz_114[10] = _zz_113; - _zz_114[9] = _zz_113; - _zz_114[8] = _zz_113; - _zz_114[7] = _zz_113; - _zz_114[6] = _zz_113; - _zz_114[5] = _zz_113; - _zz_114[4] = _zz_113; - _zz_114[3] = _zz_113; - _zz_114[2] = _zz_113; - _zz_114[1] = _zz_113; - _zz_114[0] = _zz_113; + assign _zz_112 = _zz_343[11]; + always @ (*) begin + _zz_113[19] = _zz_112; + _zz_113[18] = _zz_112; + _zz_113[17] = _zz_112; + _zz_113[16] = _zz_112; + _zz_113[15] = _zz_112; + _zz_113[14] = _zz_112; + _zz_113[13] = _zz_112; + _zz_113[12] = _zz_112; + _zz_113[11] = _zz_112; + _zz_113[10] = _zz_112; + _zz_113[9] = _zz_112; + _zz_113[8] = _zz_112; + _zz_113[7] = _zz_112; + _zz_113[6] = _zz_112; + _zz_113[5] = _zz_112; + _zz_113[4] = _zz_112; + _zz_113[3] = _zz_112; + _zz_113[2] = _zz_112; + _zz_113[1] = _zz_112; + _zz_113[0] = _zz_112; + end + + assign _zz_114 = _zz_344[11]; + always @ (*) begin + _zz_115[19] = _zz_114; + _zz_115[18] = _zz_114; + _zz_115[17] = _zz_114; + _zz_115[16] = _zz_114; + _zz_115[15] = _zz_114; + _zz_115[14] = _zz_114; + _zz_115[13] = _zz_114; + _zz_115[12] = _zz_114; + _zz_115[11] = _zz_114; + _zz_115[10] = _zz_114; + _zz_115[9] = _zz_114; + _zz_115[8] = _zz_114; + _zz_115[7] = _zz_114; + _zz_115[6] = _zz_114; + _zz_115[5] = _zz_114; + _zz_115[4] = _zz_114; + _zz_115[3] = _zz_114; + _zz_115[2] = _zz_114; + _zz_115[1] = _zz_114; + _zz_115[0] = _zz_114; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_115 = execute_RS2; + _zz_116 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; + _zz_116 = {_zz_113,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_116 = {_zz_115,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_115 = _zz_41; + _zz_116 = _zz_41; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_343; + execute_SrcPlugin_addSub = _zz_345; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3951,246 +3977,246 @@ module VexRiscv_inner ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_116[0] = execute_SRC1[31]; - _zz_116[1] = execute_SRC1[30]; - _zz_116[2] = execute_SRC1[29]; - _zz_116[3] = execute_SRC1[28]; - _zz_116[4] = execute_SRC1[27]; - _zz_116[5] = execute_SRC1[26]; - _zz_116[6] = execute_SRC1[25]; - _zz_116[7] = execute_SRC1[24]; - _zz_116[8] = execute_SRC1[23]; - _zz_116[9] = execute_SRC1[22]; - _zz_116[10] = execute_SRC1[21]; - _zz_116[11] = execute_SRC1[20]; - _zz_116[12] = execute_SRC1[19]; - _zz_116[13] = execute_SRC1[18]; - _zz_116[14] = execute_SRC1[17]; - _zz_116[15] = execute_SRC1[16]; - _zz_116[16] = execute_SRC1[15]; - _zz_116[17] = execute_SRC1[14]; - _zz_116[18] = execute_SRC1[13]; - _zz_116[19] = execute_SRC1[12]; - _zz_116[20] = execute_SRC1[11]; - _zz_116[21] = execute_SRC1[10]; - _zz_116[22] = execute_SRC1[9]; - _zz_116[23] = execute_SRC1[8]; - _zz_116[24] = execute_SRC1[7]; - _zz_116[25] = execute_SRC1[6]; - _zz_116[26] = execute_SRC1[5]; - _zz_116[27] = execute_SRC1[4]; - _zz_116[28] = execute_SRC1[3]; - _zz_116[29] = execute_SRC1[2]; - _zz_116[30] = execute_SRC1[1]; - _zz_116[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); - always @ (*) begin - _zz_117[0] = memory_SHIFT_RIGHT[31]; - _zz_117[1] = memory_SHIFT_RIGHT[30]; - _zz_117[2] = memory_SHIFT_RIGHT[29]; - _zz_117[3] = memory_SHIFT_RIGHT[28]; - _zz_117[4] = memory_SHIFT_RIGHT[27]; - _zz_117[5] = memory_SHIFT_RIGHT[26]; - _zz_117[6] = memory_SHIFT_RIGHT[25]; - _zz_117[7] = memory_SHIFT_RIGHT[24]; - _zz_117[8] = memory_SHIFT_RIGHT[23]; - _zz_117[9] = memory_SHIFT_RIGHT[22]; - _zz_117[10] = memory_SHIFT_RIGHT[21]; - _zz_117[11] = memory_SHIFT_RIGHT[20]; - _zz_117[12] = memory_SHIFT_RIGHT[19]; - _zz_117[13] = memory_SHIFT_RIGHT[18]; - _zz_117[14] = memory_SHIFT_RIGHT[17]; - _zz_117[15] = memory_SHIFT_RIGHT[16]; - _zz_117[16] = memory_SHIFT_RIGHT[15]; - _zz_117[17] = memory_SHIFT_RIGHT[14]; - _zz_117[18] = memory_SHIFT_RIGHT[13]; - _zz_117[19] = memory_SHIFT_RIGHT[12]; - _zz_117[20] = memory_SHIFT_RIGHT[11]; - _zz_117[21] = memory_SHIFT_RIGHT[10]; - _zz_117[22] = memory_SHIFT_RIGHT[9]; - _zz_117[23] = memory_SHIFT_RIGHT[8]; - _zz_117[24] = memory_SHIFT_RIGHT[7]; - _zz_117[25] = memory_SHIFT_RIGHT[6]; - _zz_117[26] = memory_SHIFT_RIGHT[5]; - _zz_117[27] = memory_SHIFT_RIGHT[4]; - _zz_117[28] = memory_SHIFT_RIGHT[3]; - _zz_117[29] = memory_SHIFT_RIGHT[2]; - _zz_117[30] = memory_SHIFT_RIGHT[1]; - _zz_117[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_118 = 1'b0; - if(_zz_271)begin - if(_zz_272)begin - if(_zz_123)begin - _zz_118 = 1'b1; - end - end - end + _zz_117[0] = execute_SRC1[31]; + _zz_117[1] = execute_SRC1[30]; + _zz_117[2] = execute_SRC1[29]; + _zz_117[3] = execute_SRC1[28]; + _zz_117[4] = execute_SRC1[27]; + _zz_117[5] = execute_SRC1[26]; + _zz_117[6] = execute_SRC1[25]; + _zz_117[7] = execute_SRC1[24]; + _zz_117[8] = execute_SRC1[23]; + _zz_117[9] = execute_SRC1[22]; + _zz_117[10] = execute_SRC1[21]; + _zz_117[11] = execute_SRC1[20]; + _zz_117[12] = execute_SRC1[19]; + _zz_117[13] = execute_SRC1[18]; + _zz_117[14] = execute_SRC1[17]; + _zz_117[15] = execute_SRC1[16]; + _zz_117[16] = execute_SRC1[15]; + _zz_117[17] = execute_SRC1[14]; + _zz_117[18] = execute_SRC1[13]; + _zz_117[19] = execute_SRC1[12]; + _zz_117[20] = execute_SRC1[11]; + _zz_117[21] = execute_SRC1[10]; + _zz_117[22] = execute_SRC1[9]; + _zz_117[23] = execute_SRC1[8]; + _zz_117[24] = execute_SRC1[7]; + _zz_117[25] = execute_SRC1[6]; + _zz_117[26] = execute_SRC1[5]; + _zz_117[27] = execute_SRC1[4]; + _zz_117[28] = execute_SRC1[3]; + _zz_117[29] = execute_SRC1[2]; + _zz_117[30] = execute_SRC1[1]; + _zz_117[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_117 : execute_SRC1); + always @ (*) begin + _zz_118[0] = memory_SHIFT_RIGHT[31]; + _zz_118[1] = memory_SHIFT_RIGHT[30]; + _zz_118[2] = memory_SHIFT_RIGHT[29]; + _zz_118[3] = memory_SHIFT_RIGHT[28]; + _zz_118[4] = memory_SHIFT_RIGHT[27]; + _zz_118[5] = memory_SHIFT_RIGHT[26]; + _zz_118[6] = memory_SHIFT_RIGHT[25]; + _zz_118[7] = memory_SHIFT_RIGHT[24]; + _zz_118[8] = memory_SHIFT_RIGHT[23]; + _zz_118[9] = memory_SHIFT_RIGHT[22]; + _zz_118[10] = memory_SHIFT_RIGHT[21]; + _zz_118[11] = memory_SHIFT_RIGHT[20]; + _zz_118[12] = memory_SHIFT_RIGHT[19]; + _zz_118[13] = memory_SHIFT_RIGHT[18]; + _zz_118[14] = memory_SHIFT_RIGHT[17]; + _zz_118[15] = memory_SHIFT_RIGHT[16]; + _zz_118[16] = memory_SHIFT_RIGHT[15]; + _zz_118[17] = memory_SHIFT_RIGHT[14]; + _zz_118[18] = memory_SHIFT_RIGHT[13]; + _zz_118[19] = memory_SHIFT_RIGHT[12]; + _zz_118[20] = memory_SHIFT_RIGHT[11]; + _zz_118[21] = memory_SHIFT_RIGHT[10]; + _zz_118[22] = memory_SHIFT_RIGHT[9]; + _zz_118[23] = memory_SHIFT_RIGHT[8]; + _zz_118[24] = memory_SHIFT_RIGHT[7]; + _zz_118[25] = memory_SHIFT_RIGHT[6]; + _zz_118[26] = memory_SHIFT_RIGHT[5]; + _zz_118[27] = memory_SHIFT_RIGHT[4]; + _zz_118[28] = memory_SHIFT_RIGHT[3]; + _zz_118[29] = memory_SHIFT_RIGHT[2]; + _zz_118[30] = memory_SHIFT_RIGHT[1]; + _zz_118[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_119 = 1'b0; if(_zz_273)begin if(_zz_274)begin - if(_zz_125)begin - _zz_118 = 1'b1; + if(_zz_124)begin + _zz_119 = 1'b1; end end end if(_zz_275)begin if(_zz_276)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(_zz_126)begin + _zz_119 = 1'b1; + end + end + end + if(_zz_277)begin + if(_zz_278)begin + if(_zz_128)begin + _zz_119 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_118 = 1'b0; + _zz_119 = 1'b0; end end always @ (*) begin - _zz_119 = 1'b0; - if(_zz_271)begin - if(_zz_272)begin - if(_zz_124)begin - _zz_119 = 1'b1; - end - end - end + _zz_120 = 1'b0; if(_zz_273)begin if(_zz_274)begin - if(_zz_126)begin - _zz_119 = 1'b1; + if(_zz_125)begin + _zz_120 = 1'b1; end end end if(_zz_275)begin if(_zz_276)begin - if(_zz_128)begin - _zz_119 = 1'b1; + if(_zz_127)begin + _zz_120 = 1'b1; + end + end + end + if(_zz_277)begin + if(_zz_278)begin + if(_zz_129)begin + _zz_120 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_119 = 1'b0; + _zz_120 = 1'b0; end end - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_125 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_127 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_129 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_129 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_129 == 3'b000)) begin - _zz_130 = execute_BranchPlugin_eq; - end else if((_zz_129 == 3'b001)) begin - _zz_130 = (! execute_BranchPlugin_eq); - end else if((((_zz_129 & 3'b101) == 3'b101))) begin - _zz_130 = (! execute_SRC_LESS); + assign _zz_130 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_130 == 3'b000)) begin + _zz_131 = execute_BranchPlugin_eq; + end else if((_zz_130 == 3'b001)) begin + _zz_131 = (! execute_BranchPlugin_eq); + end else if((((_zz_130 & 3'b101) == 3'b101))) begin + _zz_131 = (! execute_SRC_LESS); end else begin - _zz_130 = execute_SRC_LESS; + _zz_131 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_131 = 1'b0; + _zz_132 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_131 = 1'b1; + _zz_132 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_131 = 1'b1; + _zz_132 = 1'b1; end default : begin - _zz_131 = _zz_130; + _zz_132 = _zz_131; end endcase end - assign _zz_132 = _zz_350[11]; - always @ (*) begin - _zz_133[19] = _zz_132; - _zz_133[18] = _zz_132; - _zz_133[17] = _zz_132; - _zz_133[16] = _zz_132; - _zz_133[15] = _zz_132; - _zz_133[14] = _zz_132; - _zz_133[13] = _zz_132; - _zz_133[12] = _zz_132; - _zz_133[11] = _zz_132; - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; - end - - assign _zz_134 = _zz_351[19]; - always @ (*) begin - _zz_135[10] = _zz_134; - _zz_135[9] = _zz_134; - _zz_135[8] = _zz_134; - _zz_135[7] = _zz_134; - _zz_135[6] = _zz_134; - _zz_135[5] = _zz_134; - _zz_135[4] = _zz_134; - _zz_135[3] = _zz_134; - _zz_135[2] = _zz_134; - _zz_135[1] = _zz_134; - _zz_135[0] = _zz_134; - end - - assign _zz_136 = _zz_352[11]; - always @ (*) begin - _zz_137[18] = _zz_136; - _zz_137[17] = _zz_136; - _zz_137[16] = _zz_136; - _zz_137[15] = _zz_136; - _zz_137[14] = _zz_136; - _zz_137[13] = _zz_136; - _zz_137[12] = _zz_136; - _zz_137[11] = _zz_136; - _zz_137[10] = _zz_136; - _zz_137[9] = _zz_136; - _zz_137[8] = _zz_136; - _zz_137[7] = _zz_136; - _zz_137[6] = _zz_136; - _zz_137[5] = _zz_136; - _zz_137[4] = _zz_136; - _zz_137[3] = _zz_136; - _zz_137[2] = _zz_136; - _zz_137[1] = _zz_136; - _zz_137[0] = _zz_136; + assign _zz_133 = _zz_352[11]; + always @ (*) begin + _zz_134[19] = _zz_133; + _zz_134[18] = _zz_133; + _zz_134[17] = _zz_133; + _zz_134[16] = _zz_133; + _zz_134[15] = _zz_133; + _zz_134[14] = _zz_133; + _zz_134[13] = _zz_133; + _zz_134[12] = _zz_133; + _zz_134[11] = _zz_133; + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; + end + + assign _zz_135 = _zz_353[19]; + always @ (*) begin + _zz_136[10] = _zz_135; + _zz_136[9] = _zz_135; + _zz_136[8] = _zz_135; + _zz_136[7] = _zz_135; + _zz_136[6] = _zz_135; + _zz_136[5] = _zz_135; + _zz_136[4] = _zz_135; + _zz_136[3] = _zz_135; + _zz_136[2] = _zz_135; + _zz_136[1] = _zz_135; + _zz_136[0] = _zz_135; + end + + assign _zz_137 = _zz_354[11]; + always @ (*) begin + _zz_138[18] = _zz_137; + _zz_138[17] = _zz_137; + _zz_138[16] = _zz_137; + _zz_138[15] = _zz_137; + _zz_138[14] = _zz_137; + _zz_138[13] = _zz_137; + _zz_138[12] = _zz_137; + _zz_138[11] = _zz_137; + _zz_138[10] = _zz_137; + _zz_138[9] = _zz_137; + _zz_138[8] = _zz_137; + _zz_138[7] = _zz_137; + _zz_138[6] = _zz_137; + _zz_138[5] = _zz_137; + _zz_138[4] = _zz_137; + _zz_138[3] = _zz_137; + _zz_138[2] = _zz_137; + _zz_138[1] = _zz_137; + _zz_138[0] = _zz_137; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_138 = (_zz_353[1] ^ execute_RS1[1]); + _zz_139 = (_zz_355[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_138 = _zz_354[1]; + _zz_139 = _zz_356[1]; end default : begin - _zz_138 = _zz_355[1]; + _zz_139 = _zz_357[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_139); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4202,88 +4228,94 @@ module VexRiscv_inner ( endcase end - assign _zz_139 = _zz_356[11]; + assign _zz_140 = _zz_358[11]; always @ (*) begin - _zz_140[19] = _zz_139; - _zz_140[18] = _zz_139; - _zz_140[17] = _zz_139; - _zz_140[16] = _zz_139; - _zz_140[15] = _zz_139; - _zz_140[14] = _zz_139; - _zz_140[13] = _zz_139; - _zz_140[12] = _zz_139; - _zz_140[11] = _zz_139; - _zz_140[10] = _zz_139; - _zz_140[9] = _zz_139; - _zz_140[8] = _zz_139; - _zz_140[7] = _zz_139; - _zz_140[6] = _zz_139; - _zz_140[5] = _zz_139; - _zz_140[4] = _zz_139; - _zz_140[3] = _zz_139; - _zz_140[2] = _zz_139; - _zz_140[1] = _zz_139; - _zz_140[0] = _zz_139; + _zz_141[19] = _zz_140; + _zz_141[18] = _zz_140; + _zz_141[17] = _zz_140; + _zz_141[16] = _zz_140; + _zz_141[15] = _zz_140; + _zz_141[14] = _zz_140; + _zz_141[13] = _zz_140; + _zz_141[12] = _zz_140; + _zz_141[11] = _zz_140; + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_141,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_594,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_595,_zz_596},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_143,{{{_zz_602,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_145,{{{_zz_603,_zz_604},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_359}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_361}; end end endcase end - assign _zz_141 = _zz_357[19]; - always @ (*) begin - _zz_142[10] = _zz_141; - _zz_142[9] = _zz_141; - _zz_142[8] = _zz_141; - _zz_142[7] = _zz_141; - _zz_142[6] = _zz_141; - _zz_142[5] = _zz_141; - _zz_142[4] = _zz_141; - _zz_142[3] = _zz_141; - _zz_142[2] = _zz_141; - _zz_142[1] = _zz_141; - _zz_142[0] = _zz_141; - end - - assign _zz_143 = _zz_358[11]; - always @ (*) begin - _zz_144[18] = _zz_143; - _zz_144[17] = _zz_143; - _zz_144[16] = _zz_143; - _zz_144[15] = _zz_143; - _zz_144[14] = _zz_143; - _zz_144[13] = _zz_143; - _zz_144[12] = _zz_143; - _zz_144[11] = _zz_143; - _zz_144[10] = _zz_143; - _zz_144[9] = _zz_143; - _zz_144[8] = _zz_143; - _zz_144[7] = _zz_143; - _zz_144[6] = _zz_143; - _zz_144[5] = _zz_143; - _zz_144[4] = _zz_143; - _zz_144[3] = _zz_143; - _zz_144[2] = _zz_143; - _zz_144[1] = _zz_143; - _zz_144[0] = _zz_143; + assign _zz_142 = _zz_359[19]; + always @ (*) begin + _zz_143[10] = _zz_142; + _zz_143[9] = _zz_142; + _zz_143[8] = _zz_142; + _zz_143[7] = _zz_142; + _zz_143[6] = _zz_142; + _zz_143[5] = _zz_142; + _zz_143[4] = _zz_142; + _zz_143[3] = _zz_142; + _zz_143[2] = _zz_142; + _zz_143[1] = _zz_142; + _zz_143[0] = _zz_142; + end + + assign _zz_144 = _zz_360[11]; + always @ (*) begin + _zz_145[18] = _zz_144; + _zz_145[17] = _zz_144; + _zz_145[16] = _zz_144; + _zz_145[15] = _zz_144; + _zz_145[14] = _zz_144; + _zz_145[13] = _zz_144; + _zz_145[12] = _zz_144; + _zz_145[11] = _zz_144; + _zz_145[10] = _zz_144; + _zz_145[9] = _zz_144; + _zz_145[8] = _zz_144; + _zz_145[7] = _zz_144; + _zz_145[6] = _zz_144; + _zz_145[5] = _zz_144; + _zz_145[4] = _zz_144; + _zz_145[3] = _zz_144; + _zz_145[2] = _zz_144; + _zz_145[1] = _zz_144; + _zz_145[0] = _zz_144; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); - assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; - assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; - assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; always @ (*) begin CsrPlugin_privilege = 2'b11; @@ -4292,18 +4324,18 @@ module VexRiscv_inner ( end end - assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_146 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_147 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_148 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_149 = _zz_360[0]; - assign _zz_150 = {CfuPlugin_joinException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_151 = _zz_362[0]; + assign _zz_149 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_150 = _zz_362[0]; + assign _zz_151 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_152 = _zz_364[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_261)begin + if(_zz_263)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4313,7 +4345,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(_zz_266)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -4323,7 +4355,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_265)begin + if(CfuPlugin_joinException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4554,7 +4586,7 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_277)begin + if(_zz_279)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4573,20 +4605,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_278)begin + if(_zz_280)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_279)begin + if(_zz_281)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_278)begin + if(_zz_280)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_279)begin + if(_zz_281)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4601,14 +4633,14 @@ module VexRiscv_inner ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_277)begin + if(_zz_279)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_277)begin + if(_zz_279)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4617,7 +4649,7 @@ module VexRiscv_inner ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_292) + case(_zz_294) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4630,45 +4662,50 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_364; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign execute_CfuPlugin_functionsIds_0 = _zz_366; + assign execute_CfuPlugin_functionsIds_1 = {6'd0, _zz_367}; + assign CfuPlugin_bus_cmd_payload_function_id = _zz_252; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_168 = _zz_365[11]; - always @ (*) begin - _zz_169[19] = _zz_168; - _zz_169[18] = _zz_168; - _zz_169[17] = _zz_168; - _zz_169[16] = _zz_168; - _zz_169[15] = _zz_168; - _zz_169[14] = _zz_168; - _zz_169[13] = _zz_168; - _zz_169[12] = _zz_168; - _zz_169[11] = _zz_168; - _zz_169[10] = _zz_168; - _zz_169[9] = _zz_168; - _zz_169[8] = _zz_168; - _zz_169[7] = _zz_168; - _zz_169[6] = _zz_168; - _zz_169[5] = _zz_168; - _zz_169[4] = _zz_168; - _zz_169[3] = _zz_168; - _zz_169[2] = _zz_168; - _zz_169[1] = _zz_168; - _zz_169[0] = _zz_168; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_ENCODING) + assign _zz_169 = _zz_368[7]; + always @ (*) begin + _zz_170[23] = _zz_169; + _zz_170[22] = _zz_169; + _zz_170[21] = _zz_169; + _zz_170[20] = _zz_169; + _zz_170[19] = _zz_169; + _zz_170[18] = _zz_169; + _zz_170[17] = _zz_169; + _zz_170[16] = _zz_169; + _zz_170[15] = _zz_169; + _zz_170[14] = _zz_169; + _zz_170[13] = _zz_169; + _zz_170[12] = _zz_169; + _zz_170[11] = _zz_169; + _zz_170[10] = _zz_169; + _zz_170[9] = _zz_169; + _zz_170[8] = _zz_169; + _zz_170[7] = _zz_169; + _zz_170[6] = _zz_169; + _zz_170[5] = _zz_169; + _zz_170[4] = _zz_169; + _zz_170[3] = _zz_169; + _zz_170[2] = _zz_169; + _zz_170[1] = _zz_169; + _zz_170[0] = _zz_169; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_170 = execute_RS2; + _zz_171 = execute_RS2; end default : begin - _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 20]}; + _zz_171 = {_zz_170,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_171; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4694,7 +4731,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_280) + case(_zz_282) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4708,7 +4745,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_280) + case(_zz_282) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4727,12 +4764,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_366) + $signed(_zz_367)); + assign writeBack_MulPlugin_result = ($signed(_zz_369) + $signed(_zz_370)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_256)begin - if(_zz_281)begin + if(_zz_258)begin + if(_zz_283)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4740,7 +4777,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_282)begin + if(_zz_284)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4751,32 +4788,32 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_374); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_372); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_373 : _zz_374); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_375[31:0]; - assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_172 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_172[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_375); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_376 : _zz_377); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_378[31:0]; + assign _zz_173 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_174 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_175 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_175[31 : 0] = execute_RS1; + _zz_176[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_176[31 : 0] = execute_RS1; end - assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_177 != 32'h0); + assign _zz_178 = (_zz_177 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_178 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_283) + case(_zz_285) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4790,7 +4827,7 @@ module VexRiscv_inner ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_178))begin + if((! _zz_179))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4802,7 +4839,7 @@ module VexRiscv_inner ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_283) + case(_zz_285) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4844,9 +4881,9 @@ module VexRiscv_inner ( assign _zz_34 = decode_to_execute_ENV_CTRL; assign _zz_33 = execute_to_memory_ENV_CTRL; assign _zz_35 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_ENCODING; + assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; assign _zz_1 = _zz_49; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_ENCODING; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4869,7 +4906,7 @@ module VexRiscv_inner ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_179) + case(_zz_180) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4879,272 +4916,272 @@ module VexRiscv_inner ( end always @ (*) begin - _zz_180 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_180[12 : 0] = 13'h1000; - _zz_180[25 : 20] = 6'h20; + _zz_181[12 : 0] = 13'h1000; + _zz_181[25 : 20] = 6'h20; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_181[3 : 0] = 4'b1011; + _zz_182[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_182[4 : 0] = 5'h16; + _zz_183[4 : 0] = 5'h16; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_183[5 : 0] = 6'h21; + _zz_184[5 : 0] = 6'h21; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_184[31 : 30] = CsrPlugin_misa_base; - _zz_184[25 : 0] = CsrPlugin_misa_extensions; + _zz_185[31 : 30] = CsrPlugin_misa_base; + _zz_185[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_186[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_186[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_186[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_186[11 : 11] = CsrPlugin_mip_MEIP; - _zz_186[7 : 7] = CsrPlugin_mip_MTIP; - _zz_186[3 : 3] = CsrPlugin_mip_MSIP; + _zz_187[11 : 11] = CsrPlugin_mip_MEIP; + _zz_187[7 : 7] = CsrPlugin_mip_MTIP; + _zz_187[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_187[11 : 11] = CsrPlugin_mie_MEIE; - _zz_187[7 : 7] = CsrPlugin_mie_MTIE; - _zz_187[3 : 3] = CsrPlugin_mie_MSIE; + _zz_188[11 : 11] = CsrPlugin_mie_MEIE; + _zz_188[7 : 7] = CsrPlugin_mie_MTIE; + _zz_188[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_188[31 : 2] = CsrPlugin_mtvec_base; - _zz_188[1 : 0] = CsrPlugin_mtvec_mode; + _zz_189[31 : 2] = CsrPlugin_mtvec_base; + _zz_189[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_189[31 : 0] = CsrPlugin_mepc; + _zz_190[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_190[31 : 0] = CsrPlugin_mscratch; + _zz_191[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_192[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_192[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_192[31 : 0] = CsrPlugin_mtval; + _zz_193[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_198[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_199 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_199[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_200 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_200[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_201 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_201[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_201 = 32'h0; + _zz_202 = 32'h0; if(execute_CsrPlugin_csr_2820)begin - _zz_201[31 : 0] = _zz_152; + _zz_202[31 : 0] = _zz_153; end end always @ (*) begin - _zz_202 = 32'h0; + _zz_203 = 32'h0; if(execute_CsrPlugin_csr_2822)begin - _zz_202[31 : 0] = _zz_154; + _zz_203[31 : 0] = _zz_155; end end always @ (*) begin - _zz_203 = 32'h0; + _zz_204 = 32'h0; if(execute_CsrPlugin_csr_2824)begin - _zz_203[31 : 0] = _zz_156; + _zz_204[31 : 0] = _zz_157; end end always @ (*) begin - _zz_204 = 32'h0; + _zz_205 = 32'h0; if(execute_CsrPlugin_csr_2826)begin - _zz_204[31 : 0] = _zz_158; + _zz_205[31 : 0] = _zz_159; end end always @ (*) begin - _zz_205 = 32'h0; + _zz_206 = 32'h0; if(execute_CsrPlugin_csr_2828)begin - _zz_205[31 : 0] = _zz_160; + _zz_206[31 : 0] = _zz_161; end end always @ (*) begin - _zz_206 = 32'h0; + _zz_207 = 32'h0; if(execute_CsrPlugin_csr_2830)begin - _zz_206[31 : 0] = _zz_162; + _zz_207[31 : 0] = _zz_163; end end always @ (*) begin - _zz_207 = 32'h0; + _zz_208 = 32'h0; if(execute_CsrPlugin_csr_2832)begin - _zz_207[31 : 0] = _zz_164; + _zz_208[31 : 0] = _zz_165; end end always @ (*) begin - _zz_208 = 32'h0; + _zz_209 = 32'h0; if(execute_CsrPlugin_csr_2834)begin - _zz_208[31 : 0] = _zz_166; + _zz_209[31 : 0] = _zz_167; end end always @ (*) begin - _zz_209 = 32'h0; + _zz_210 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_209[31 : 0] = _zz_176; + _zz_210[31 : 0] = _zz_177; end end always @ (*) begin - _zz_210 = 32'h0; + _zz_211 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_210[31 : 0] = _zz_177; + _zz_211[31 : 0] = _zz_178; end end - assign execute_CsrPlugin_readData = (((((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_597 | _zz_184) | (_zz_185 | _zz_186))) | (((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194)))) | ((((_zz_195 | _zz_196) | (_zz_197 | _zz_198)) | ((_zz_199 | _zz_200) | (_zz_201 | _zz_202))) | (((_zz_203 | _zz_204) | (_zz_205 | _zz_206)) | ((_zz_207 | _zz_208) | (_zz_209 | _zz_210))))); - assign iBusWishbone_ADR = {_zz_392,_zz_211}; - assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_181 | _zz_182) | (_zz_183 | _zz_184)) | ((_zz_605 | _zz_185) | (_zz_186 | _zz_187))) | (((_zz_188 | _zz_189) | (_zz_190 | _zz_191)) | ((_zz_192 | _zz_193) | (_zz_194 | _zz_195)))) | ((((_zz_196 | _zz_197) | (_zz_198 | _zz_199)) | ((_zz_200 | _zz_201) | (_zz_202 | _zz_203))) | (((_zz_204 | _zz_205) | (_zz_206 | _zz_207)) | ((_zz_208 | _zz_209) | (_zz_210 | _zz_211))))); + assign iBusWishbone_ADR = {_zz_395,_zz_212}; + assign iBusWishbone_CTI = ((_zz_212 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_284)begin + if(_zz_286)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_284)begin + if(_zz_286)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_212; + assign iBus_rsp_valid = _zz_213; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_218 = (dBus_cmd_payload_length != 3'b000); - assign _zz_214 = dBus_cmd_valid; - assign _zz_216 = dBus_cmd_payload_wr; - assign _zz_217 = (_zz_213 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_215 && (_zz_216 || _zz_217)); - assign dBusWishbone_ADR = ((_zz_218 ? {{dBus_cmd_payload_address[31 : 5],_zz_213},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_218 ? (_zz_217 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_219 = (dBus_cmd_payload_length != 3'b000); + assign _zz_215 = dBus_cmd_valid; + assign _zz_217 = dBus_cmd_payload_wr; + assign _zz_218 = (_zz_214 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_216 && (_zz_217 || _zz_218)); + assign dBusWishbone_ADR = ((_zz_219 ? {{dBus_cmd_payload_address[31 : 5],_zz_214},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_219 ? (_zz_218 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_216 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_216; + assign dBusWishbone_SEL = (_zz_217 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_217; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_215 = (_zz_214 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_214; - assign dBusWishbone_STB = _zz_214; - assign dBus_rsp_valid = _zz_219; + assign _zz_216 = (_zz_215 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_215; + assign dBusWishbone_STB = _zz_215; + assign dBus_rsp_valid = _zz_220; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5166,8 +5203,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; DBusCachedPlugin_rspCounter <= _zz_88; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_108 <= 1'b1; - _zz_120 <= 1'b0; + _zz_109 <= 1'b1; + _zz_121 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -5191,16 +5228,16 @@ module VexRiscv_inner ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_176 <= 32'h0; + _zz_177 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_179 <= 3'b000; + _zz_180 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_211 <= 3'b000; - _zz_212 <= 1'b0; - _zz_213 <= 3'b000; - _zz_219 <= 1'b0; + _zz_212 <= 3'b000; + _zz_213 <= 1'b0; + _zz_214 <= 3'b000; + _zz_220 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5281,7 +5318,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_285)begin + if(_zz_287)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5290,8 +5327,8 @@ module VexRiscv_inner ( if(dBus_rsp_valid)begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_108 <= 1'b0; - _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); + _zz_109 <= 1'b0; + _zz_121 <= (_zz_47 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5313,14 +5350,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_286)begin - if(_zz_287)begin + if(_zz_288)begin + if(_zz_289)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_288)begin + if(_zz_290)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_289)begin + if(_zz_291)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5345,7 +5382,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_266)begin + if(_zz_268)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5356,8 +5393,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_267)begin - case(_zz_269) + if(_zz_269)begin + case(_zz_271) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5367,7 +5404,7 @@ module VexRiscv_inner ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_148,{_zz_147,_zz_146}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -5383,7 +5420,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_290)begin + if(_zz_292)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; @@ -5408,25 +5445,25 @@ module VexRiscv_inner ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_179) + case(_zz_180) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_179 <= 3'b001; + _zz_180 <= 3'b001; end end 3'b001 : begin - _zz_179 <= 3'b010; + _zz_180 <= 3'b010; end 3'b010 : begin - _zz_179 <= 3'b011; + _zz_180 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_179 <= 3'b100; + _zz_180 <= 3'b100; end end 3'b100 : begin - _zz_179 <= 3'b000; + _zz_180 <= 3'b000; end default : begin end @@ -5440,35 +5477,35 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_385[0]; - CsrPlugin_mstatus_MIE <= _zz_386[0]; + CsrPlugin_mstatus_MPIE <= _zz_388[0]; + CsrPlugin_mstatus_MIE <= _zz_389[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_388[0]; - CsrPlugin_mie_MTIE <= _zz_389[0]; - CsrPlugin_mie_MSIE <= _zz_390[0]; + CsrPlugin_mie_MEIE <= _zz_391[0]; + CsrPlugin_mie_MTIE <= _zz_392[0]; + CsrPlugin_mie_MSIE <= _zz_393[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_177 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_284)begin + if(_zz_286)begin if(iBusWishbone_ACK)begin - _zz_211 <= (_zz_211 + 3'b001); + _zz_212 <= (_zz_212 + 3'b001); end end - _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_214 && _zz_215))begin - _zz_213 <= (_zz_213 + 3'b001); - if(_zz_217)begin - _zz_213 <= 3'b000; + _zz_213 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_215 && _zz_216))begin + _zz_214 <= (_zz_214 + 3'b001); + if(_zz_218)begin + _zz_214 <= 3'b000; end end - _zz_219 <= ((_zz_214 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_220 <= ((_zz_215 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5482,7 +5519,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_285)begin + if(_zz_287)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5500,8 +5537,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - _zz_121 <= _zz_46[11 : 7]; - _zz_122 <= _zz_57; + _zz_122 <= _zz_46[11 : 7]; + _zz_123 <= _zz_57; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5509,37 +5546,37 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_261)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_263)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + if(_zz_266)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_152 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_152 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(_zz_265)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; end if(DBusCachedPlugin_exceptionBus_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_286)begin - if(_zz_287)begin + if(_zz_288)begin + if(_zz_289)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_288)begin + if(_zz_290)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_289)begin + if(_zz_291)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_266)begin + if(_zz_268)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5553,31 +5590,31 @@ module VexRiscv_inner ( end endcase end - if(_zz_153[0])begin - _zz_152 <= (_zz_152 + 32'h00000001); + if(_zz_154[0])begin + _zz_153 <= (_zz_153 + 32'h00000001); end - if(_zz_155[0])begin - _zz_154 <= (_zz_154 + 32'h00000001); + if(_zz_156[0])begin + _zz_155 <= (_zz_155 + 32'h00000001); end - if(_zz_157[0])begin - _zz_156 <= (_zz_156 + 32'h00000001); + if(_zz_158[0])begin + _zz_157 <= (_zz_157 + 32'h00000001); end - if(_zz_159[0])begin - _zz_158 <= (_zz_158 + 32'h00000001); + if(_zz_160[0])begin + _zz_159 <= (_zz_159 + 32'h00000001); end - if(_zz_161[0])begin - _zz_160 <= (_zz_160 + 32'h00000001); + if(_zz_162[0])begin + _zz_161 <= (_zz_161 + 32'h00000001); end - if(_zz_163[0])begin - _zz_162 <= (_zz_162 + 32'h00000001); + if(_zz_164[0])begin + _zz_163 <= (_zz_163 + 32'h00000001); end - if(_zz_165[0])begin - _zz_164 <= (_zz_164 + 32'h00000001); + if(_zz_166[0])begin + _zz_165 <= (_zz_165 + 32'h00000001); end - if(_zz_167[0])begin - _zz_166 <= (_zz_166 + 32'h00000001); + if(_zz_168[0])begin + _zz_167 <= (_zz_167 + 32'h00000001); end - if(_zz_290)begin + if(_zz_292)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5587,20 +5624,20 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_256)begin - if(_zz_281)begin + if(_zz_258)begin + if(_zz_283)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_376[31:0]; + memory_DivPlugin_div_result <= _zz_379[31:0]; end end end - if(_zz_282)begin + if(_zz_284)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_382); - memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_384); - memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_175 ? (~ _zz_176) : _zz_176) + _zz_385); + memory_DivPlugin_rs2 <= ((_zz_174 ? (~ execute_RS2) : execute_RS2) + _zz_387); + memory_DivPlugin_div_needRevert <= ((_zz_175 ^ (_zz_174 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5625,10 +5662,10 @@ module VexRiscv_inner ( decode_to_execute_FORMAL_PC_NEXT <= _zz_60; end if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + execute_to_memory_FORMAL_PC_NEXT <= _zz_59; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_59; + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; @@ -5715,7 +5752,10 @@ module VexRiscv_inner ( decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENCODING <= _zz_2; + decode_to_execute_CfuPlugin_CFU_ENCODING <= decode_CfuPlugin_CFU_ENCODING; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_MUL <= decode_IS_MUL; @@ -5774,12 +5814,6 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; - end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; end @@ -5923,7 +5957,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_387[0]; + CsrPlugin_mip_MSIP <= _zz_390[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5944,7 +5978,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_391[0]; + CsrPlugin_mcause_interrupt <= _zz_394[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5975,82 +6009,82 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_2820)begin if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2821)begin if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2822)begin if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2823)begin if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2824)begin if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2825)begin if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2826)begin if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2827)begin if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2828)begin if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2829)begin if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2830)begin if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2831)begin if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2832)begin if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2833)begin if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2834)begin if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2835)begin if(execute_CsrPlugin_writeEnable)begin - _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -6067,8 +6101,8 @@ module VexRiscv_inner ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_57; end - _zz_178 <= debug_bus_cmd_payload_address[2]; - if(_zz_263)begin + _zz_179 <= debug_bus_cmd_payload_address[2]; + if(_zz_265)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -6086,7 +6120,7 @@ module VexRiscv_inner ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_283) + case(_zz_285) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -6114,13 +6148,13 @@ module VexRiscv_inner ( end endcase end - if(_zz_263)begin - if(_zz_264)begin + if(_zz_265)begin + if(_zz_267)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_268)begin + if(_zz_270)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index 1e12d0b..95eb44b 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -183,7 +183,8 @@ object GenCoreDefault{ pessimisticAddressMatch = false ), new BranchPlugin( - earlyBranch = false, + // If using CFU, use earlyBranch to avoid incorrect CFU execution + earlyBranch = argConfig.cfu, catchAddressMisaligned = true ), new CsrPlugin( @@ -211,7 +212,7 @@ object GenCoreDefault{ // CFU R-type CfuPluginEncoding ( instruction = M"-------------------------0001011", - functionId = List(31 downto 25, 14 downto 12), + functionId = List(14 downto 12, 31 downto 25), input2Kind = CfuPlugin.Input2Kind.RS ), // CFU I-type diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v index 75ccab0..ce1e64d 100644 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v @@ -36,7 +36,7 @@ module VexRiscv ( wire CfuPlugin_bus_cmd_valid; wire CfuPlugin_bus_cmd_ready; - wire [19:0] CfuPlugin_bus_cmd_payload_function_id; + wire [9:0] CfuPlugin_bus_cmd_payload_function_id; wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; wire CfuPlugin_bus_rsp_valid; diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v index 069b86c..6d9f587 100644 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v @@ -44,7 +44,7 @@ module VexRiscv ( wire CfuPlugin_bus_cmd_valid; wire CfuPlugin_bus_cmd_ready; - wire [19:0] CfuPlugin_bus_cmd_payload_function_id; + wire [9:0] CfuPlugin_bus_cmd_payload_function_id; wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; wire CfuPlugin_bus_rsp_valid; From c8881985e0b323f1b12cab3ed0bd455d6c406944 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Thu, 8 Apr 2021 10:07:49 -0700 Subject: [PATCH 12/30] Remove I-format CFU instruction; it impacts timing. Signed-off-by: Tim Callahan --- .../verilog/VexRiscv_FullCfu.v | 2814 ++++++++--------- .../verilog/VexRiscv_FullCfuDebug.v | 2668 ++++++++-------- .../main/scala/vexriscv/GenCoreDefault.scala | 13 +- 3 files changed, 2714 insertions(+), 2781 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index 094c87d..aec1870 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 767476cae91f564ec9eab25516eb1664b04c1224 +// Git hash : eafff82697ae47892bb4654e4bb7d282a4b9807c `define Input2Kind_defaultEncoding_type [0:0] @@ -87,6 +87,7 @@ module VexRiscv_inner ( input clk, input reset ); + wire _zz_217; wire _zz_218; wire _zz_219; wire _zz_220; @@ -94,16 +95,16 @@ module VexRiscv_inner ( wire _zz_222; wire _zz_223; wire _zz_224; - wire _zz_225; - reg _zz_226; - wire _zz_227; - wire [31:0] _zz_228; - wire _zz_229; - wire [31:0] _zz_230; - reg _zz_231; + reg _zz_225; + wire _zz_226; + wire [31:0] _zz_227; + wire _zz_228; + wire [31:0] _zz_229; + reg _zz_230; + wire _zz_231; wire _zz_232; - wire _zz_233; - wire [31:0] _zz_234; + wire [31:0] _zz_233; + wire _zz_234; wire _zz_235; wire _zz_236; wire _zz_237; @@ -111,14 +112,12 @@ module VexRiscv_inner ( wire _zz_239; wire _zz_240; wire _zz_241; - wire _zz_242; - wire [3:0] _zz_243; + wire [3:0] _zz_242; + wire _zz_243; wire _zz_244; - wire _zz_245; + reg [31:0] _zz_245; reg [31:0] _zz_246; reg [31:0] _zz_247; - reg [31:0] _zz_248; - reg [9:0] _zz_249; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -151,6 +150,8 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_248; + wire _zz_249; wire _zz_250; wire _zz_251; wire _zz_252; @@ -164,9 +165,9 @@ module VexRiscv_inner ( wire _zz_260; wire _zz_261; wire _zz_262; - wire _zz_263; + wire [1:0] _zz_263; wire _zz_264; - wire [1:0] _zz_265; + wire _zz_265; wire _zz_266; wire _zz_267; wire _zz_268; @@ -175,9 +176,9 @@ module VexRiscv_inner ( wire _zz_271; wire _zz_272; wire _zz_273; - wire _zz_274; + wire [1:0] _zz_274; wire _zz_275; - wire [1:0] _zz_276; + wire _zz_276; wire _zz_277; wire _zz_278; wire _zz_279; @@ -185,23 +186,23 @@ module VexRiscv_inner ( wire _zz_281; wire _zz_282; wire _zz_283; - wire _zz_284; + wire [1:0] _zz_284; wire _zz_285; wire [1:0] _zz_286; - wire _zz_287; - wire [1:0] _zz_288; + wire [51:0] _zz_287; + wire [51:0] _zz_288; wire [51:0] _zz_289; - wire [51:0] _zz_290; + wire [32:0] _zz_290; wire [51:0] _zz_291; - wire [32:0] _zz_292; + wire [49:0] _zz_292; wire [51:0] _zz_293; wire [49:0] _zz_294; wire [51:0] _zz_295; - wire [49:0] _zz_296; - wire [51:0] _zz_297; + wire [32:0] _zz_296; + wire [31:0] _zz_297; wire [32:0] _zz_298; - wire [31:0] _zz_299; - wire [32:0] _zz_300; + wire [0:0] _zz_299; + wire [0:0] _zz_300; wire [0:0] _zz_301; wire [0:0] _zz_302; wire [0:0] _zz_303; @@ -218,276 +219,270 @@ module VexRiscv_inner ( wire [0:0] _zz_314; wire [0:0] _zz_315; wire [0:0] _zz_316; - wire [0:0] _zz_317; - wire [0:0] _zz_318; - wire [3:0] _zz_319; - wire [2:0] _zz_320; + wire [3:0] _zz_317; + wire [2:0] _zz_318; + wire [31:0] _zz_319; + wire [11:0] _zz_320; wire [31:0] _zz_321; - wire [11:0] _zz_322; - wire [31:0] _zz_323; - wire [19:0] _zz_324; - wire [11:0] _zz_325; - wire [31:0] _zz_326; - wire [31:0] _zz_327; - wire [19:0] _zz_328; - wire [11:0] _zz_329; - wire [2:0] _zz_330; + wire [19:0] _zz_322; + wire [11:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [19:0] _zz_326; + wire [11:0] _zz_327; + wire [2:0] _zz_328; + wire [2:0] _zz_329; + wire [0:0] _zz_330; wire [2:0] _zz_331; - wire [0:0] _zz_332; - wire [2:0] _zz_333; - wire [4:0] _zz_334; - wire [11:0] _zz_335; - wire [11:0] _zz_336; + wire [4:0] _zz_332; + wire [11:0] _zz_333; + wire [11:0] _zz_334; + wire [31:0] _zz_335; + wire [31:0] _zz_336; wire [31:0] _zz_337; wire [31:0] _zz_338; wire [31:0] _zz_339; wire [31:0] _zz_340; wire [31:0] _zz_341; - wire [31:0] _zz_342; - wire [31:0] _zz_343; + wire [11:0] _zz_342; + wire [19:0] _zz_343; wire [11:0] _zz_344; - wire [19:0] _zz_345; - wire [11:0] _zz_346; + wire [31:0] _zz_345; + wire [31:0] _zz_346; wire [31:0] _zz_347; - wire [31:0] _zz_348; - wire [31:0] _zz_349; + wire [11:0] _zz_348; + wire [19:0] _zz_349; wire [11:0] _zz_350; - wire [19:0] _zz_351; - wire [11:0] _zz_352; - wire [2:0] _zz_353; + wire [2:0] _zz_351; + wire [1:0] _zz_352; + wire [1:0] _zz_353; wire [1:0] _zz_354; wire [1:0] _zz_355; - wire [1:0] _zz_356; - wire [1:0] _zz_357; - wire [9:0] _zz_358; - wire [3:0] _zz_359; - wire [7:0] _zz_360; - wire [65:0] _zz_361; - wire [65:0] _zz_362; - wire [31:0] _zz_363; - wire [31:0] _zz_364; - wire [0:0] _zz_365; - wire [5:0] _zz_366; + wire [9:0] _zz_356; + wire [7:0] _zz_357; + wire [65:0] _zz_358; + wire [65:0] _zz_359; + wire [31:0] _zz_360; + wire [31:0] _zz_361; + wire [0:0] _zz_362; + wire [5:0] _zz_363; + wire [32:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; wire [32:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; + wire [32:0] _zz_368; + wire [32:0] _zz_369; wire [32:0] _zz_370; - wire [32:0] _zz_371; + wire [0:0] _zz_371; wire [32:0] _zz_372; - wire [32:0] _zz_373; - wire [0:0] _zz_374; - wire [32:0] _zz_375; - wire [0:0] _zz_376; - wire [32:0] _zz_377; + wire [0:0] _zz_373; + wire [32:0] _zz_374; + wire [0:0] _zz_375; + wire [31:0] _zz_376; + wire [0:0] _zz_377; wire [0:0] _zz_378; - wire [31:0] _zz_379; + wire [0:0] _zz_379; wire [0:0] _zz_380; wire [0:0] _zz_381; wire [0:0] _zz_382; wire [0:0] _zz_383; - wire [0:0] _zz_384; - wire [0:0] _zz_385; - wire [0:0] _zz_386; - wire [26:0] _zz_387; - wire _zz_388; - wire _zz_389; - wire [1:0] _zz_390; - wire [31:0] _zz_391; - wire [31:0] _zz_392; - wire [31:0] _zz_393; - wire _zz_394; - wire [0:0] _zz_395; - wire [15:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire [31:0] _zz_399; - wire _zz_400; - wire [0:0] _zz_401; - wire [9:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire [31:0] _zz_405; + wire [26:0] _zz_384; + wire _zz_385; + wire _zz_386; + wire [1:0] _zz_387; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire _zz_391; + wire [0:0] _zz_392; + wire [14:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire [31:0] _zz_396; + wire _zz_397; + wire [0:0] _zz_398; + wire [8:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; + wire [31:0] _zz_402; + wire _zz_403; + wire [0:0] _zz_404; + wire [2:0] _zz_405; wire _zz_406; - wire [0:0] _zz_407; - wire [3:0] _zz_408; - wire _zz_409; - wire _zz_410; + wire _zz_407; + wire _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; wire _zz_411; - wire [31:0] _zz_412; - wire [31:0] _zz_413; - wire _zz_414; - wire [0:0] _zz_415; - wire [0:0] _zz_416; - wire _zz_417; + wire _zz_412; + wire [0:0] _zz_413; + wire [26:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; wire [0:0] _zz_418; - wire [27:0] _zz_419; - wire [31:0] _zz_420; - wire [31:0] _zz_421; + wire [0:0] _zz_419; + wire [1:0] _zz_420; + wire [1:0] _zz_421; wire _zz_422; - wire [1:0] _zz_423; - wire [1:0] _zz_424; - wire _zz_425; - wire [0:0] _zz_426; - wire [22:0] _zz_427; + wire [0:0] _zz_423; + wire [21:0] _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire [31:0] _zz_427; wire [31:0] _zz_428; wire [31:0] _zz_429; wire [31:0] _zz_430; - wire [31:0] _zz_431; - wire _zz_432; - wire _zz_433; - wire [1:0] _zz_434; - wire [1:0] _zz_435; - wire _zz_436; - wire [0:0] _zz_437; - wire [19:0] _zz_438; + wire [0:0] _zz_431; + wire [0:0] _zz_432; + wire [2:0] _zz_433; + wire [2:0] _zz_434; + wire _zz_435; + wire [0:0] _zz_436; + wire [18:0] _zz_437; + wire [31:0] _zz_438; wire [31:0] _zz_439; wire [31:0] _zz_440; wire [31:0] _zz_441; - wire [31:0] _zz_442; + wire _zz_442; wire _zz_443; - wire [0:0] _zz_444; - wire [0:0] _zz_445; + wire [31:0] _zz_444; + wire [31:0] _zz_445; wire _zz_446; wire [0:0] _zz_447; wire [0:0] _zz_448; wire _zz_449; wire [0:0] _zz_450; - wire [16:0] _zz_451; + wire [15:0] _zz_451; wire [31:0] _zz_452; - wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [31:0] _zz_456; - wire [0:0] _zz_457; - wire [0:0] _zz_458; + wire _zz_453; + wire _zz_454; + wire _zz_455; + wire [2:0] _zz_456; + wire [2:0] _zz_457; + wire _zz_458; wire [0:0] _zz_459; - wire [0:0] _zz_460; + wire [12:0] _zz_460; wire _zz_461; - wire [0:0] _zz_462; - wire [13:0] _zz_463; - wire [31:0] _zz_464; - wire [31:0] _zz_465; - wire [31:0] _zz_466; - wire _zz_467; - wire [0:0] _zz_468; - wire [0:0] _zz_469; + wire _zz_462; + wire _zz_463; + wire [0:0] _zz_464; + wire [2:0] _zz_465; + wire _zz_466; + wire [5:0] _zz_467; + wire [5:0] _zz_468; + wire _zz_469; wire [0:0] _zz_470; - wire [3:0] _zz_471; - wire [0:0] _zz_472; - wire [0:0] _zz_473; - wire _zz_474; - wire [0:0] _zz_475; - wire [10:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; - wire [31:0] _zz_479; + wire [9:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; + wire [31:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; + wire _zz_477; + wire [0:0] _zz_478; + wire [0:0] _zz_479; wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire _zz_482; - wire [0:0] _zz_483; + wire _zz_481; + wire [0:0] _zz_482; + wire [3:0] _zz_483; wire [0:0] _zz_484; - wire _zz_485; - wire [0:0] _zz_486; - wire [3:0] _zz_487; - wire [0:0] _zz_488; - wire [3:0] _zz_489; - wire [6:0] _zz_490; - wire [6:0] _zz_491; - wire _zz_492; - wire [0:0] _zz_493; - wire [7:0] _zz_494; + wire [3:0] _zz_485; + wire [5:0] _zz_486; + wire [5:0] _zz_487; + wire _zz_488; + wire [0:0] _zz_489; + wire [7:0] _zz_490; + wire [31:0] _zz_491; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; wire [31:0] _zz_495; wire [31:0] _zz_496; wire [31:0] _zz_497; wire [31:0] _zz_498; - wire [31:0] _zz_499; - wire [31:0] _zz_500; - wire [31:0] _zz_501; - wire [31:0] _zz_502; - wire [0:0] _zz_503; - wire [1:0] _zz_504; - wire _zz_505; + wire [0:0] _zz_499; + wire [1:0] _zz_500; + wire _zz_501; + wire [0:0] _zz_502; + wire [1:0] _zz_503; + wire [0:0] _zz_504; + wire [3:0] _zz_505; wire [0:0] _zz_506; - wire [1:0] _zz_507; - wire [0:0] _zz_508; - wire [4:0] _zz_509; - wire [0:0] _zz_510; + wire [0:0] _zz_507; + wire [1:0] _zz_508; + wire [1:0] _zz_509; + wire _zz_510; wire [0:0] _zz_511; - wire [1:0] _zz_512; - wire [1:0] _zz_513; - wire _zz_514; - wire [0:0] _zz_515; - wire [5:0] _zz_516; + wire [5:0] _zz_512; + wire [31:0] _zz_513; + wire [31:0] _zz_514; + wire _zz_515; + wire _zz_516; wire [31:0] _zz_517; wire [31:0] _zz_518; - wire _zz_519; + wire [31:0] _zz_519; wire _zz_520; - wire [31:0] _zz_521; + wire _zz_521; wire [31:0] _zz_522; wire [31:0] _zz_523; wire _zz_524; - wire _zz_525; - wire [31:0] _zz_526; + wire [0:0] _zz_525; + wire [1:0] _zz_526; wire [31:0] _zz_527; - wire _zz_528; - wire [0:0] _zz_529; - wire [2:0] _zz_530; - wire [31:0] _zz_531; - wire [31:0] _zz_532; + wire [31:0] _zz_528; + wire _zz_529; + wire _zz_530; + wire [0:0] _zz_531; + wire [0:0] _zz_532; wire _zz_533; - wire _zz_534; - wire [0:0] _zz_535; - wire [0:0] _zz_536; - wire _zz_537; - wire [0:0] _zz_538; - wire [3:0] _zz_539; + wire [0:0] _zz_534; + wire [3:0] _zz_535; + wire [31:0] _zz_536; + wire [31:0] _zz_537; + wire [31:0] _zz_538; + wire [31:0] _zz_539; wire [31:0] _zz_540; wire [31:0] _zz_541; wire [31:0] _zz_542; - wire [31:0] _zz_543; - wire [31:0] _zz_544; + wire _zz_543; + wire _zz_544; wire [31:0] _zz_545; wire [31:0] _zz_546; - wire [0:0] _zz_547; - wire [0:0] _zz_548; - wire [31:0] _zz_549; - wire [31:0] _zz_550; - wire [31:0] _zz_551; - wire [31:0] _zz_552; - wire [0:0] _zz_553; - wire [2:0] _zz_554; - wire [0:0] _zz_555; - wire [0:0] _zz_556; - wire _zz_557; - wire [0:0] _zz_558; - wire [1:0] _zz_559; - wire [31:0] _zz_560; + wire [31:0] _zz_547; + wire [31:0] _zz_548; + wire [0:0] _zz_549; + wire [2:0] _zz_550; + wire [0:0] _zz_551; + wire [0:0] _zz_552; + wire _zz_553; + wire [0:0] _zz_554; + wire [1:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire _zz_559; + wire _zz_560; wire [31:0] _zz_561; - wire [31:0] _zz_562; - wire [31:0] _zz_563; - wire [31:0] _zz_564; - wire _zz_565; - wire _zz_566; - wire [31:0] _zz_567; - wire _zz_568; + wire _zz_562; + wire [0:0] _zz_563; + wire [0:0] _zz_564; + wire [0:0] _zz_565; + wire [0:0] _zz_566; + wire [1:0] _zz_567; + wire [1:0] _zz_568; wire [0:0] _zz_569; wire [0:0] _zz_570; - wire [0:0] _zz_571; - wire [0:0] _zz_572; - wire [1:0] _zz_573; - wire [1:0] _zz_574; - wire [0:0] _zz_575; - wire [0:0] _zz_576; - wire [31:0] _zz_577; - wire [31:0] _zz_578; - wire [31:0] _zz_579; + wire [31:0] _zz_571; + wire [31:0] _zz_572; + wire [31:0] _zz_573; + wire [31:0] _zz_574; + wire [31:0] _zz_575; + wire [31:0] _zz_576; + wire _zz_577; + wire _zz_578; + wire _zz_579; wire [31:0] _zz_580; - wire [31:0] _zz_581; - wire [31:0] _zz_582; - wire _zz_583; - wire _zz_584; - wire _zz_585; - wire [31:0] _zz_586; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -514,7 +509,6 @@ module VexRiscv_inner ( wire `Input2Kind_defaultEncoding_type _zz_1; wire `Input2Kind_defaultEncoding_type _zz_2; wire `Input2Kind_defaultEncoding_type _zz_3; - wire [0:0] decode_CfuPlugin_CFU_ENCODING; wire decode_CfuPlugin_CFU_ENABLE; wire `EnvCtrlEnum_defaultEncoding_type _zz_4; wire `EnvCtrlEnum_defaultEncoding_type _zz_5; @@ -577,7 +571,6 @@ module VexRiscv_inner ( wire memory_CfuPlugin_CFU_IN_FLIGHT; wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; wire `Input2Kind_defaultEncoding_type _zz_32; - wire [0:0] execute_CfuPlugin_CFU_ENCODING; wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; @@ -946,21 +939,20 @@ module VexRiscv_inner ( wire _zz_91; reg [31:0] _zz_92; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [34:0] _zz_93; + wire [33:0] _zz_93; wire _zz_94; wire _zz_95; wire _zz_96; wire _zz_97; wire _zz_98; - wire _zz_99; - wire `Src1CtrlEnum_defaultEncoding_type _zz_100; - wire `AluCtrlEnum_defaultEncoding_type _zz_101; - wire `Src2CtrlEnum_defaultEncoding_type _zz_102; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; - wire `BranchCtrlEnum_defaultEncoding_type _zz_105; - wire `EnvCtrlEnum_defaultEncoding_type _zz_106; - wire `Input2Kind_defaultEncoding_type _zz_107; + wire `Src1CtrlEnum_defaultEncoding_type _zz_99; + wire `AluCtrlEnum_defaultEncoding_type _zz_100; + wire `Src2CtrlEnum_defaultEncoding_type _zz_101; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_102; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_103; + wire `BranchCtrlEnum_defaultEncoding_type _zz_104; + wire `EnvCtrlEnum_defaultEncoding_type _zz_105; + wire `Input2Kind_defaultEncoding_type _zz_106; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -968,52 +960,52 @@ module VexRiscv_inner ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_108; + reg _zz_107; reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_108; reg [31:0] _zz_109; - reg [31:0] _zz_110; - wire _zz_111; - reg [19:0] _zz_112; - wire _zz_113; - reg [19:0] _zz_114; - reg [31:0] _zz_115; + wire _zz_110; + reg [19:0] _zz_111; + wire _zz_112; + reg [19:0] _zz_113; + reg [31:0] _zz_114; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_116; + reg [31:0] _zz_115; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_117; + reg [31:0] _zz_116; + reg _zz_117; reg _zz_118; reg _zz_119; - reg _zz_120; - reg [4:0] _zz_121; - reg [31:0] _zz_122; + reg [4:0] _zz_120; + reg [31:0] _zz_121; + wire _zz_122; wire _zz_123; wire _zz_124; wire _zz_125; wire _zz_126; wire _zz_127; - wire _zz_128; wire execute_BranchPlugin_eq; - wire [2:0] _zz_129; + wire [2:0] _zz_128; + reg _zz_129; reg _zz_130; - reg _zz_131; - wire _zz_132; - reg [19:0] _zz_133; - wire _zz_134; - reg [10:0] _zz_135; - wire _zz_136; - reg [18:0] _zz_137; - reg _zz_138; + wire _zz_131; + reg [19:0] _zz_132; + wire _zz_133; + reg [10:0] _zz_134; + wire _zz_135; + reg [18:0] _zz_136; + reg _zz_137; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_139; - reg [19:0] _zz_140; - wire _zz_141; - reg [10:0] _zz_142; - wire _zz_143; - reg [18:0] _zz_144; + wire _zz_138; + reg [19:0] _zz_139; + wire _zz_140; + reg [10:0] _zz_141; + wire _zz_142; + reg [18:0] _zz_143; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1035,9 +1027,9 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_144; wire _zz_145; wire _zz_146; - wire _zz_147; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1050,10 +1042,10 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_148; - wire _zz_149; - wire [1:0] _zz_150; - wire _zz_151; + wire [1:0] _zz_147; + wire _zz_148; + wire [1:0] _zz_149; + wire _zz_150; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1082,6 +1074,7 @@ module VexRiscv_inner ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_151; reg [31:0] _zz_152; reg [31:0] _zz_153; reg [31:0] _zz_154; @@ -1097,15 +1090,13 @@ module VexRiscv_inner ( reg [31:0] _zz_164; reg [31:0] _zz_165; reg [31:0] _zz_166; - reg [31:0] _zz_167; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire [9:0] execute_CfuPlugin_functionsIds_1; - wire _zz_168; - reg [23:0] _zz_169; - reg [31:0] _zz_170; + wire _zz_167; + reg [23:0] _zz_168; + reg [31:0] _zz_169; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1137,18 +1128,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_171; + wire [31:0] _zz_170; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_172; + wire [31:0] _zz_171; + wire _zz_172; wire _zz_173; - wire _zz_174; - reg [32:0] _zz_175; + reg [32:0] _zz_174; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_176; - wire [31:0] _zz_177; + reg [31:0] _zz_175; + wire [31:0] _zz_176; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1186,7 +1177,6 @@ module VexRiscv_inner ( reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg [0:0] decode_to_execute_CfuPlugin_CFU_ENCODING; reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; reg decode_to_execute_IS_MUL; reg execute_to_memory_IS_MUL; @@ -1254,6 +1244,7 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_177; reg [31:0] _zz_178; reg [31:0] _zz_179; reg [31:0] _zz_180; @@ -1284,17 +1275,16 @@ module VexRiscv_inner ( reg [31:0] _zz_205; reg [31:0] _zz_206; reg [31:0] _zz_207; - reg [31:0] _zz_208; - reg [2:0] _zz_209; - reg _zz_210; + reg [2:0] _zz_208; + reg _zz_209; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_211; + reg [2:0] _zz_210; + wire _zz_211; wire _zz_212; wire _zz_213; wire _zz_214; wire _zz_215; - wire _zz_216; - reg _zz_217; + reg _zz_216; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; @@ -1365,14 +1355,14 @@ module VexRiscv_inner ( reg [95:0] _zz_56_string; reg [31:0] decode_BRANCH_CTRL_string; reg [31:0] _zz_58_string; - reg [95:0] _zz_100_string; - reg [63:0] _zz_101_string; - reg [23:0] _zz_102_string; - reg [39:0] _zz_103_string; - reg [71:0] _zz_104_string; - reg [31:0] _zz_105_string; + reg [95:0] _zz_99_string; + reg [63:0] _zz_100_string; + reg [23:0] _zz_101_string; + reg [39:0] _zz_102_string; + reg [71:0] _zz_103_string; + reg [31:0] _zz_104_string; + reg [39:0] _zz_105_string; reg [39:0] _zz_106_string; - reg [39:0] _zz_107_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1388,352 +1378,348 @@ module VexRiscv_inner ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_250 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_251 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_252 = 1'b1; - assign _zz_253 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_254 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_255 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_256 = ((_zz_223 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_257 = ((_zz_223 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_258 = ((_zz_223 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_259 = ((_zz_223 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_260 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_261 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_262 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_263 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_264 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_265 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_266 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_267 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_268 = (1'b0 || (! 1'b1)); - assign _zz_269 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_270 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_271 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_272 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_273 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_274 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_275 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_276 = execute_INSTRUCTION[13 : 12]; - assign _zz_277 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_278 = (! memory_arbitration_isStuck); - assign _zz_279 = (iBus_cmd_valid || (_zz_209 != 3'b000)); - assign _zz_280 = (_zz_245 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_281 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_282 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_283 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_284 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_285 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_248 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_249 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_250 = 1'b1; + assign _zz_251 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_252 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_254 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_255 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_256 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_257 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_260 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_264 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_265 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_266 = (1'b0 || (! 1'b1)); + assign _zz_267 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_268 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_270 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_271 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_272 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_273 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_274 = execute_INSTRUCTION[13 : 12]; + assign _zz_275 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_276 = (! memory_arbitration_isStuck); + assign _zz_277 = (iBus_cmd_valid || (_zz_208 != 3'b000)); + assign _zz_278 = (_zz_244 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_280 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_281 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_282 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_285 = execute_INSTRUCTION[13]; assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_287 = execute_INSTRUCTION[13]; - assign _zz_288 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_289 = ($signed(_zz_290) + $signed(_zz_295)); - assign _zz_290 = ($signed(_zz_291) + $signed(_zz_293)); - assign _zz_291 = 52'h0; - assign _zz_292 = {1'b0,memory_MUL_LL}; - assign _zz_293 = {{19{_zz_292[32]}}, _zz_292}; - assign _zz_294 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); + assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); + assign _zz_289 = 52'h0; + assign _zz_290 = {1'b0,memory_MUL_LL}; + assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; + assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; + assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; - assign _zz_296 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_297 = {{2{_zz_296[49]}}, _zz_296}; - assign _zz_298 = ($signed(_zz_300) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_299 = _zz_298[31 : 0]; - assign _zz_300 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_301 = _zz_93[34 : 34]; - assign _zz_302 = _zz_93[33 : 33]; - assign _zz_303 = _zz_93[32 : 32]; - assign _zz_304 = _zz_93[31 : 31]; - assign _zz_305 = _zz_93[28 : 28]; - assign _zz_306 = _zz_93[25 : 25]; - assign _zz_307 = _zz_93[17 : 17]; - assign _zz_308 = _zz_93[16 : 16]; - assign _zz_309 = _zz_93[13 : 13]; - assign _zz_310 = _zz_93[12 : 12]; - assign _zz_311 = _zz_93[11 : 11]; - assign _zz_312 = _zz_93[15 : 15]; - assign _zz_313 = _zz_93[5 : 5]; - assign _zz_314 = _zz_93[3 : 3]; - assign _zz_315 = _zz_93[20 : 20]; - assign _zz_316 = _zz_93[10 : 10]; - assign _zz_317 = _zz_93[4 : 4]; - assign _zz_318 = _zz_93[0 : 0]; - assign _zz_319 = (_zz_61 - 4'b0001); - assign _zz_320 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_321 = {29'd0, _zz_320}; - assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_323 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_324 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_325 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_326 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_327 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_329 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_330 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_331 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_332 = execute_SRC_LESS; - assign _zz_333 = 3'b100; - assign _zz_334 = execute_INSTRUCTION[19 : 15]; - assign _zz_335 = execute_INSTRUCTION[31 : 20]; - assign _zz_336 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_337 = ($signed(_zz_338) + $signed(_zz_341)); - assign _zz_338 = ($signed(_zz_339) + $signed(_zz_340)); - assign _zz_339 = execute_SRC1; - assign _zz_340 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_341 = (execute_SRC_USE_SUB_LESS ? _zz_342 : _zz_343); - assign _zz_342 = 32'h00000001; - assign _zz_343 = 32'h0; - assign _zz_344 = execute_INSTRUCTION[31 : 20]; - assign _zz_345 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_346 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_347 = {_zz_133,execute_INSTRUCTION[31 : 20]}; - assign _zz_348 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_349 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_350 = execute_INSTRUCTION[31 : 20]; - assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_353 = 3'b100; - assign _zz_354 = (_zz_148 & (~ _zz_355)); - assign _zz_355 = (_zz_148 - 2'b01); - assign _zz_356 = (_zz_150 & (~ _zz_357)); - assign _zz_357 = (_zz_150 - 2'b01); - assign _zz_358 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_359 = execute_INSTRUCTION[23 : 20]; - assign _zz_360 = execute_INSTRUCTION[31 : 24]; - assign _zz_361 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_362 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_363 = writeBack_MUL_LOW[31 : 0]; - assign _zz_364 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_365 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_366 = {5'd0, _zz_365}; - assign _zz_367 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_368 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_369 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_370 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_371 = _zz_372; - assign _zz_372 = _zz_373; - assign _zz_373 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_375); - assign _zz_374 = memory_DivPlugin_div_needRevert; - assign _zz_375 = {32'd0, _zz_374}; - assign _zz_376 = _zz_174; - assign _zz_377 = {32'd0, _zz_376}; - assign _zz_378 = _zz_173; - assign _zz_379 = {31'd0, _zz_378}; - assign _zz_380 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_381 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_297 = _zz_296[31 : 0]; + assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_299 = _zz_93[33 : 33]; + assign _zz_300 = _zz_93[32 : 32]; + assign _zz_301 = _zz_93[31 : 31]; + assign _zz_302 = _zz_93[30 : 30]; + assign _zz_303 = _zz_93[28 : 28]; + assign _zz_304 = _zz_93[25 : 25]; + assign _zz_305 = _zz_93[17 : 17]; + assign _zz_306 = _zz_93[16 : 16]; + assign _zz_307 = _zz_93[13 : 13]; + assign _zz_308 = _zz_93[12 : 12]; + assign _zz_309 = _zz_93[11 : 11]; + assign _zz_310 = _zz_93[15 : 15]; + assign _zz_311 = _zz_93[5 : 5]; + assign _zz_312 = _zz_93[3 : 3]; + assign _zz_313 = _zz_93[20 : 20]; + assign _zz_314 = _zz_93[10 : 10]; + assign _zz_315 = _zz_93[4 : 4]; + assign _zz_316 = _zz_93[0 : 0]; + assign _zz_317 = (_zz_61 - 4'b0001); + assign _zz_318 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_319 = {29'd0, _zz_318}; + assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_321 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_324 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_325 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_326 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_328 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_329 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_330 = execute_SRC_LESS; + assign _zz_331 = 3'b100; + assign _zz_332 = execute_INSTRUCTION[19 : 15]; + assign _zz_333 = execute_INSTRUCTION[31 : 20]; + assign _zz_334 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_335 = ($signed(_zz_336) + $signed(_zz_339)); + assign _zz_336 = ($signed(_zz_337) + $signed(_zz_338)); + assign _zz_337 = execute_SRC1; + assign _zz_338 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_339 = (execute_SRC_USE_SUB_LESS ? _zz_340 : _zz_341); + assign _zz_340 = 32'h00000001; + assign _zz_341 = 32'h0; + assign _zz_342 = execute_INSTRUCTION[31 : 20]; + assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_345 = {_zz_132,execute_INSTRUCTION[31 : 20]}; + assign _zz_346 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_347 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_348 = execute_INSTRUCTION[31 : 20]; + assign _zz_349 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_351 = 3'b100; + assign _zz_352 = (_zz_147 & (~ _zz_353)); + assign _zz_353 = (_zz_147 - 2'b01); + assign _zz_354 = (_zz_149 & (~ _zz_355)); + assign _zz_355 = (_zz_149 - 2'b01); + assign _zz_356 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_357 = execute_INSTRUCTION[31 : 24]; + assign _zz_358 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_359 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_360 = writeBack_MUL_LOW[31 : 0]; + assign _zz_361 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_362 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_363 = {5'd0, _zz_362}; + assign _zz_364 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_365 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_366 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_367 = {_zz_170,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_368 = _zz_369; + assign _zz_369 = _zz_370; + assign _zz_370 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_171) : _zz_171)} + _zz_372); + assign _zz_371 = memory_DivPlugin_div_needRevert; + assign _zz_372 = {32'd0, _zz_371}; + assign _zz_373 = _zz_173; + assign _zz_374 = {32'd0, _zz_373}; + assign _zz_375 = _zz_172; + assign _zz_376 = {31'd0, _zz_375}; + assign _zz_377 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_378 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_380 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_381 = execute_CsrPlugin_writeData[7 : 7]; assign _zz_382 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_383 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_384 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_385 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_386 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_387 = (iBus_cmd_payload_address >>> 5); - assign _zz_388 = 1'b1; - assign _zz_389 = 1'b1; - assign _zz_390 = {_zz_65,_zz_64}; - assign _zz_391 = 32'h0000106f; - assign _zz_392 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_393 = 32'h00001073; - assign _zz_394 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_395 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_396 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_397) == 32'h00000003),{(_zz_398 == _zz_399),{_zz_400,{_zz_401,_zz_402}}}}}}; - assign _zz_397 = 32'h0000207f; - assign _zz_398 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_399 = 32'h00000003; - assign _zz_400 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_401 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_402 = {((decode_INSTRUCTION & 32'h00007077) == 32'h00000023),{((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_403) == 32'h0000500f),{(_zz_404 == _zz_405),{_zz_406,{_zz_407,_zz_408}}}}}}; - assign _zz_403 = 32'h01f0707f; - assign _zz_404 = (decode_INSTRUCTION & 32'hbc00707f); - assign _zz_405 = 32'h00005013; - assign _zz_406 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); - assign _zz_407 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_408 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}}; - assign _zz_409 = decode_INSTRUCTION[31]; - assign _zz_410 = decode_INSTRUCTION[31]; - assign _zz_411 = decode_INSTRUCTION[7]; - assign _zz_412 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_413 = 32'h02004020; - assign _zz_414 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_415 = _zz_98; - assign _zz_416 = 1'b0; - assign _zz_417 = (_zz_98 != 1'b0); - assign _zz_418 = (_zz_96 != 1'b0); - assign _zz_419 = {((_zz_420 == _zz_421) != 1'b0),{(_zz_422 != 1'b0),{(_zz_423 != _zz_424),{_zz_425,{_zz_426,_zz_427}}}}}; - assign _zz_420 = (decode_INSTRUCTION & 32'h00203050); - assign _zz_421 = 32'h00000050; - assign _zz_422 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050); - assign _zz_423 = {(_zz_428 == _zz_429),(_zz_430 == _zz_431)}; - assign _zz_424 = 2'b00; - assign _zz_425 = ({_zz_97,_zz_432} != 2'b00); - assign _zz_426 = (_zz_433 != 1'b0); - assign _zz_427 = {(_zz_434 != _zz_435),{_zz_436,{_zz_437,_zz_438}}}; - assign _zz_428 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_429 = 32'h00001050; - assign _zz_430 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_431 = 32'h00002050; - assign _zz_432 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_433 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_434 = {(_zz_439 == _zz_440),(_zz_441 == _zz_442)}; - assign _zz_435 = 2'b00; - assign _zz_436 = ({_zz_443,{_zz_444,_zz_445}} != 3'b000); - assign _zz_437 = (_zz_446 != 1'b0); - assign _zz_438 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; - assign _zz_439 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_440 = 32'h00005010; - assign _zz_441 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_442 = 32'h00005020; - assign _zz_443 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_444 = ((decode_INSTRUCTION & _zz_452) == 32'h00001010); - assign _zz_445 = ((decode_INSTRUCTION & _zz_453) == 32'h00001010); - assign _zz_446 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_447 = ((decode_INSTRUCTION & _zz_454) == 32'h00001000); + assign _zz_383 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_384 = (iBus_cmd_payload_address >>> 5); + assign _zz_385 = 1'b1; + assign _zz_386 = 1'b1; + assign _zz_387 = {_zz_65,_zz_64}; + assign _zz_388 = 32'h0000106f; + assign _zz_389 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_390 = 32'h00001073; + assign _zz_391 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_392 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_393 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_394) == 32'h00000003),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; + assign _zz_394 = 32'h0000207f; + assign _zz_395 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_396 = 32'h00000003; + assign _zz_397 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_398 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_399 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_400) == 32'h00005013),{(_zz_401 == _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; + assign _zz_400 = 32'hbc00707f; + assign _zz_401 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_402 = 32'h00001013; + assign _zz_403 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_405 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_406 = decode_INSTRUCTION[31]; + assign _zz_407 = decode_INSTRUCTION[31]; + assign _zz_408 = decode_INSTRUCTION[7]; + assign _zz_409 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_410 = 32'h02004020; + assign _zz_411 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_412 = (_zz_97 != 1'b0); + assign _zz_413 = (((decode_INSTRUCTION & _zz_415) == 32'h00000050) != 1'b0); + assign _zz_414 = {((_zz_416 == _zz_417) != 1'b0),{({_zz_418,_zz_419} != 2'b00),{(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}}}; + assign _zz_415 = 32'h00203050; + assign _zz_416 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_417 = 32'h00000050; + assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00001050); + assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00002050); + assign _zz_420 = {_zz_96,(_zz_427 == _zz_428)}; + assign _zz_421 = 2'b00; + assign _zz_422 = ((_zz_429 == _zz_430) != 1'b0); + assign _zz_423 = ({_zz_431,_zz_432} != 2'b00); + assign _zz_424 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; + assign _zz_425 = 32'h00001050; + assign _zz_426 = 32'h00002050; + assign _zz_427 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_428 = 32'h00000004; + assign _zz_429 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_430 = 32'h00000040; + assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h00005010); + assign _zz_432 = ((decode_INSTRUCTION & _zz_439) == 32'h00005020); + assign _zz_433 = {(_zz_440 == _zz_441),{_zz_442,_zz_443}}; + assign _zz_434 = 3'b000; + assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); + assign _zz_436 = (_zz_446 != 1'b0); + assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; + assign _zz_438 = 32'h00007034; + assign _zz_439 = 32'h02007064; + assign _zz_440 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_441 = 32'h40001010; + assign _zz_442 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_443 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_445 = 32'h00000024; + assign _zz_446 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_447 = ((decode_INSTRUCTION & _zz_452) == 32'h00002000); assign _zz_448 = 1'b0; - assign _zz_449 = ((_zz_455 == _zz_456) != 1'b0); - assign _zz_450 = ({_zz_457,_zz_458} != 2'b00); - assign _zz_451 = {(_zz_459 != _zz_460),{_zz_461,{_zz_462,_zz_463}}}; - assign _zz_452 = 32'h00007034; - assign _zz_453 = 32'h02007054; - assign _zz_454 = 32'h00001000; - assign _zz_455 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_456 = 32'h00002000; - assign _zz_457 = ((decode_INSTRUCTION & _zz_464) == 32'h00002000); - assign _zz_458 = ((decode_INSTRUCTION & _zz_465) == 32'h00001000); - assign _zz_459 = ((decode_INSTRUCTION & _zz_466) == 32'h00004004); - assign _zz_460 = 1'b0; - assign _zz_461 = ({_zz_467,{_zz_468,_zz_469}} != 3'b000); - assign _zz_462 = ({_zz_470,_zz_471} != 5'h0); - assign _zz_463 = {(_zz_472 != _zz_473),{_zz_474,{_zz_475,_zz_476}}}; - assign _zz_464 = 32'h00002010; - assign _zz_465 = 32'h00005000; - assign _zz_466 = 32'h00004054; - assign _zz_467 = ((decode_INSTRUCTION & 32'h0000002c) == 32'h00000008); - assign _zz_468 = ((decode_INSTRUCTION & _zz_477) == 32'h00000040); - assign _zz_469 = ((decode_INSTRUCTION & _zz_478) == 32'h00000020); - assign _zz_470 = ((decode_INSTRUCTION & _zz_479) == 32'h00002040); - assign _zz_471 = {(_zz_480 == _zz_481),{_zz_482,{_zz_483,_zz_484}}}; - assign _zz_472 = _zz_98; - assign _zz_473 = 1'b0; - assign _zz_474 = ({_zz_485,{_zz_486,_zz_487}} != 6'h0); - assign _zz_475 = ({_zz_488,_zz_489} != 5'h0); - assign _zz_476 = {(_zz_490 != _zz_491),{_zz_492,{_zz_493,_zz_494}}}; - assign _zz_477 = 32'h00000054; - assign _zz_478 = 32'h0000006c; - assign _zz_479 = 32'h00002040; - assign _zz_480 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_481 = 32'h00001040; - assign _zz_482 = ((decode_INSTRUCTION & _zz_495) == 32'h00000040); - assign _zz_483 = (_zz_496 == _zz_497); - assign _zz_484 = (_zz_498 == _zz_499); - assign _zz_485 = ((decode_INSTRUCTION & _zz_500) == 32'h00000008); - assign _zz_486 = (_zz_501 == _zz_502); - assign _zz_487 = {_zz_95,{_zz_503,_zz_504}}; - assign _zz_488 = _zz_95; - assign _zz_489 = {_zz_505,{_zz_506,_zz_507}}; - assign _zz_490 = {_zz_97,{_zz_508,_zz_509}}; - assign _zz_491 = 7'h0; - assign _zz_492 = ({_zz_510,_zz_511} != 2'b00); - assign _zz_493 = (_zz_512 != _zz_513); - assign _zz_494 = {_zz_514,{_zz_515,_zz_516}}; - assign _zz_495 = 32'h00000050; - assign _zz_496 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_497 = 32'h00000040; - assign _zz_498 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_499 = 32'h0; - assign _zz_500 = 32'h00000008; - assign _zz_501 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_502 = 32'h00000040; - assign _zz_503 = (_zz_517 == _zz_518); - assign _zz_504 = {_zz_519,_zz_520}; - assign _zz_505 = ((decode_INSTRUCTION & _zz_521) == 32'h00002010); - assign _zz_506 = (_zz_522 == _zz_523); - assign _zz_507 = {_zz_524,_zz_525}; - assign _zz_508 = (_zz_526 == _zz_527); - assign _zz_509 = {_zz_528,{_zz_529,_zz_530}}; - assign _zz_510 = _zz_95; - assign _zz_511 = (_zz_531 == _zz_532); - assign _zz_512 = {_zz_95,_zz_533}; - assign _zz_513 = 2'b00; - assign _zz_514 = (_zz_534 != 1'b0); - assign _zz_515 = (_zz_535 != _zz_536); - assign _zz_516 = {_zz_537,{_zz_538,_zz_539}}; - assign _zz_517 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_518 = 32'h00004020; - assign _zz_519 = ((decode_INSTRUCTION & _zz_540) == 32'h00000010); - assign _zz_520 = ((decode_INSTRUCTION & _zz_541) == 32'h00000020); - assign _zz_521 = 32'h00002030; - assign _zz_522 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_523 = 32'h00000010; - assign _zz_524 = ((decode_INSTRUCTION & _zz_542) == 32'h00002020); - assign _zz_525 = ((decode_INSTRUCTION & _zz_543) == 32'h00000020); - assign _zz_526 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_527 = 32'h00001010; - assign _zz_528 = ((decode_INSTRUCTION & _zz_544) == 32'h00002010); - assign _zz_529 = (_zz_545 == _zz_546); - assign _zz_530 = {_zz_96,{_zz_547,_zz_548}}; - assign _zz_531 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_532 = 32'h00000020; - assign _zz_533 = ((decode_INSTRUCTION & _zz_549) == 32'h0); - assign _zz_534 = ((decode_INSTRUCTION & _zz_550) == 32'h00004010); - assign _zz_535 = (_zz_551 == _zz_552); - assign _zz_536 = 1'b0; - assign _zz_537 = ({_zz_553,_zz_554} != 4'b0000); - assign _zz_538 = (_zz_555 != _zz_556); - assign _zz_539 = {_zz_557,{_zz_558,_zz_559}}; - assign _zz_540 = 32'h00000030; - assign _zz_541 = 32'h02000020; - assign _zz_542 = 32'h02002060; - assign _zz_543 = 32'h02003028; - assign _zz_544 = 32'h00002010; - assign _zz_545 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_546 = 32'h00000010; - assign _zz_547 = ((decode_INSTRUCTION & _zz_560) == 32'h00000004); - assign _zz_548 = ((decode_INSTRUCTION & _zz_561) == 32'h0); - assign _zz_549 = 32'h00000020; - assign _zz_550 = 32'h00004014; - assign _zz_551 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_552 = 32'h00002010; - assign _zz_553 = ((decode_INSTRUCTION & _zz_562) == 32'h0); - assign _zz_554 = {(_zz_563 == _zz_564),{_zz_565,_zz_566}}; - assign _zz_555 = ((decode_INSTRUCTION & _zz_567) == 32'h0); - assign _zz_556 = 1'b0; - assign _zz_557 = ({_zz_568,{_zz_569,_zz_570}} != 3'b000); - assign _zz_558 = ({_zz_571,_zz_572} != 2'b00); - assign _zz_559 = {(_zz_573 != _zz_574),(_zz_575 != _zz_576)}; - assign _zz_560 = 32'h0000000c; - assign _zz_561 = 32'h00000028; - assign _zz_562 = 32'h00000044; - assign _zz_563 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_564 = 32'h0; - assign _zz_565 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_566 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_567 = 32'h00000058; - assign _zz_568 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_569 = ((decode_INSTRUCTION & _zz_577) == 32'h00002010); - assign _zz_570 = ((decode_INSTRUCTION & _zz_578) == 32'h40000030); - assign _zz_571 = ((decode_INSTRUCTION & _zz_579) == 32'h00000004); - assign _zz_572 = _zz_94; - assign _zz_573 = {(_zz_580 == _zz_581),_zz_94}; - assign _zz_574 = 2'b00; - assign _zz_575 = ((decode_INSTRUCTION & _zz_582) == 32'h00001004); - assign _zz_576 = 1'b0; - assign _zz_577 = 32'h00002014; - assign _zz_578 = 32'h40000034; - assign _zz_579 = 32'h00000014; - assign _zz_580 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_581 = 32'h00000004; - assign _zz_582 = 32'h00005054; - assign _zz_583 = execute_INSTRUCTION[31]; - assign _zz_584 = execute_INSTRUCTION[31]; - assign _zz_585 = execute_INSTRUCTION[7]; - assign _zz_586 = 32'h0; + assign _zz_449 = ({_zz_453,_zz_454} != 2'b00); + assign _zz_450 = (_zz_455 != 1'b0); + assign _zz_451 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; + assign _zz_452 = 32'h00003000; + assign _zz_453 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_454 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_455 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_456 = {_zz_97,{_zz_461,_zz_462}}; + assign _zz_457 = 3'b000; + assign _zz_458 = ({_zz_463,{_zz_464,_zz_465}} != 5'h0); + assign _zz_459 = (_zz_466 != 1'b0); + assign _zz_460 = {(_zz_467 != _zz_468),{_zz_469,{_zz_470,_zz_471}}}; + assign _zz_461 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); + assign _zz_462 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); + assign _zz_463 = ((decode_INSTRUCTION & _zz_474) == 32'h00002040); + assign _zz_464 = (_zz_475 == _zz_476); + assign _zz_465 = {_zz_477,{_zz_478,_zz_479}}; + assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000020); + assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; + assign _zz_468 = 6'h0; + assign _zz_469 = ({_zz_484,_zz_485} != 5'h0); + assign _zz_470 = (_zz_486 != _zz_487); + assign _zz_471 = {_zz_488,{_zz_489,_zz_490}}; + assign _zz_472 = 32'h00000034; + assign _zz_473 = 32'h00000064; + assign _zz_474 = 32'h00002040; + assign _zz_475 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_476 = 32'h00001040; + assign _zz_477 = ((decode_INSTRUCTION & _zz_491) == 32'h00000040); + assign _zz_478 = (_zz_492 == _zz_493); + assign _zz_479 = (_zz_494 == _zz_495); + assign _zz_480 = 32'h00000020; + assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00000008); + assign _zz_482 = (_zz_497 == _zz_498); + assign _zz_483 = {_zz_95,{_zz_499,_zz_500}}; + assign _zz_484 = _zz_95; + assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; + assign _zz_486 = {_zz_96,{_zz_504,_zz_505}}; + assign _zz_487 = 6'h0; + assign _zz_488 = ({_zz_506,_zz_507} != 2'b00); + assign _zz_489 = (_zz_508 != _zz_509); + assign _zz_490 = {_zz_510,{_zz_511,_zz_512}}; + assign _zz_491 = 32'h00000050; + assign _zz_492 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_493 = 32'h00000040; + assign _zz_494 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_495 = 32'h0; + assign _zz_496 = 32'h00000008; + assign _zz_497 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_498 = 32'h00000040; + assign _zz_499 = (_zz_513 == _zz_514); + assign _zz_500 = {_zz_515,_zz_516}; + assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00002010); + assign _zz_502 = (_zz_518 == _zz_519); + assign _zz_503 = {_zz_520,_zz_521}; + assign _zz_504 = (_zz_522 == _zz_523); + assign _zz_505 = {_zz_524,{_zz_525,_zz_526}}; + assign _zz_506 = _zz_95; + assign _zz_507 = (_zz_527 == _zz_528); + assign _zz_508 = {_zz_95,_zz_529}; + assign _zz_509 = 2'b00; + assign _zz_510 = (_zz_530 != 1'b0); + assign _zz_511 = (_zz_531 != _zz_532); + assign _zz_512 = {_zz_533,{_zz_534,_zz_535}}; + assign _zz_513 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_514 = 32'h00004020; + assign _zz_515 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); + assign _zz_516 = ((decode_INSTRUCTION & _zz_537) == 32'h00000020); + assign _zz_517 = 32'h00002030; + assign _zz_518 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_519 = 32'h00000010; + assign _zz_520 = ((decode_INSTRUCTION & _zz_538) == 32'h00002020); + assign _zz_521 = ((decode_INSTRUCTION & _zz_539) == 32'h00000020); + assign _zz_522 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_523 = 32'h00001010; + assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00002010); + assign _zz_525 = (_zz_541 == _zz_542); + assign _zz_526 = {_zz_543,_zz_544}; + assign _zz_527 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_528 = 32'h00000020; + assign _zz_529 = ((decode_INSTRUCTION & _zz_545) == 32'h0); + assign _zz_530 = ((decode_INSTRUCTION & _zz_546) == 32'h00004010); + assign _zz_531 = (_zz_547 == _zz_548); + assign _zz_532 = 1'b0; + assign _zz_533 = ({_zz_549,_zz_550} != 4'b0000); + assign _zz_534 = (_zz_551 != _zz_552); + assign _zz_535 = {_zz_553,{_zz_554,_zz_555}}; + assign _zz_536 = 32'h00000030; + assign _zz_537 = 32'h02000020; + assign _zz_538 = 32'h02002060; + assign _zz_539 = 32'h02003020; + assign _zz_540 = 32'h00002010; + assign _zz_541 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_542 = 32'h00000010; + assign _zz_543 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_544 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_545 = 32'h00000020; + assign _zz_546 = 32'h00004014; + assign _zz_547 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_548 = 32'h00002010; + assign _zz_549 = ((decode_INSTRUCTION & _zz_556) == 32'h0); + assign _zz_550 = {(_zz_557 == _zz_558),{_zz_559,_zz_560}}; + assign _zz_551 = ((decode_INSTRUCTION & _zz_561) == 32'h0); + assign _zz_552 = 1'b0; + assign _zz_553 = ({_zz_562,{_zz_563,_zz_564}} != 3'b000); + assign _zz_554 = ({_zz_565,_zz_566} != 2'b00); + assign _zz_555 = {(_zz_567 != _zz_568),(_zz_569 != _zz_570)}; + assign _zz_556 = 32'h00000044; + assign _zz_557 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_558 = 32'h0; + assign _zz_559 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_560 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_561 = 32'h00000058; + assign _zz_562 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_563 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); + assign _zz_564 = ((decode_INSTRUCTION & _zz_572) == 32'h40000030); + assign _zz_565 = ((decode_INSTRUCTION & _zz_573) == 32'h00000004); + assign _zz_566 = _zz_94; + assign _zz_567 = {(_zz_574 == _zz_575),_zz_94}; + assign _zz_568 = 2'b00; + assign _zz_569 = ((decode_INSTRUCTION & _zz_576) == 32'h00001004); + assign _zz_570 = 1'b0; + assign _zz_571 = 32'h00002014; + assign _zz_572 = 32'h40000034; + assign _zz_573 = 32'h00000014; + assign _zz_574 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_575 = 32'h00000004; + assign _zz_576 = 32'h00005054; + assign _zz_577 = execute_INSTRUCTION[31]; + assign _zz_578 = execute_INSTRUCTION[31]; + assign _zz_579 = execute_INSTRUCTION[7]; + assign _zz_580 = 32'h0; always @ (posedge clk) begin - if(_zz_388) begin - _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_385) begin + _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_389) begin - _zz_247 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_386) begin + _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1744,13 +1730,13 @@ module VexRiscv_inner ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_218 ), //i - .io_cpu_prefetch_isValid (_zz_219 ), //i + .io_flush (_zz_217 ), //i + .io_cpu_prefetch_isValid (_zz_218 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_220 ), //i - .io_cpu_fetch_isStuck (_zz_221 ), //i - .io_cpu_fetch_isRemoved (_zz_222 ), //i + .io_cpu_fetch_isValid (_zz_219 ), //i + .io_cpu_fetch_isStuck (_zz_220 ), //i + .io_cpu_fetch_isRemoved (_zz_221 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1763,8 +1749,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_223 ), //i - .io_cpu_decode_isStuck (_zz_224 ), //i + .io_cpu_decode_isValid (_zz_222 ), //i + .io_cpu_decode_isStuck (_zz_223 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1772,8 +1758,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_225 ), //i - .io_cpu_fill_valid (_zz_226 ), //i + .io_cpu_decode_isUser (_zz_224 ), //i + .io_cpu_fill_valid (_zz_225 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1786,20 +1772,20 @@ module VexRiscv_inner ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_227 ), //i - .io_cpu_execute_address (_zz_228[31:0] ), //i + .io_cpu_execute_isValid (_zz_226 ), //i + .io_cpu_execute_address (_zz_227[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_88[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_229 ), //i + .io_cpu_memory_isValid (_zz_228 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_230[31:0] ), //i + .io_cpu_memory_address (_zz_229[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_231 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_230 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1807,31 +1793,31 @@ module VexRiscv_inner ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_232 ), //i + .io_cpu_writeBack_isValid (_zz_231 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_233 ), //i + .io_cpu_writeBack_isUser (_zz_232 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_234[31:0] ), //i + .io_cpu_writeBack_address (_zz_233[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_235 ), //i - .io_cpu_writeBack_fence_SR (_zz_236 ), //i - .io_cpu_writeBack_fence_SO (_zz_237 ), //i - .io_cpu_writeBack_fence_SI (_zz_238 ), //i - .io_cpu_writeBack_fence_PW (_zz_239 ), //i - .io_cpu_writeBack_fence_PR (_zz_240 ), //i - .io_cpu_writeBack_fence_PO (_zz_241 ), //i - .io_cpu_writeBack_fence_PI (_zz_242 ), //i - .io_cpu_writeBack_fence_FM (_zz_243[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_234 ), //i + .io_cpu_writeBack_fence_SR (_zz_235 ), //i + .io_cpu_writeBack_fence_SO (_zz_236 ), //i + .io_cpu_writeBack_fence_SI (_zz_237 ), //i + .io_cpu_writeBack_fence_PW (_zz_238 ), //i + .io_cpu_writeBack_fence_PR (_zz_239 ), //i + .io_cpu_writeBack_fence_PO (_zz_240 ), //i + .io_cpu_writeBack_fence_PI (_zz_241 ), //i + .io_cpu_writeBack_fence_FM (_zz_242[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_244 ), //i + .io_cpu_flush_valid (_zz_243 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_245 ), //i + .io_mem_cmd_ready (_zz_244 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1847,29 +1833,18 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_390) + case(_zz_387) 2'b00 : begin - _zz_248 = DBusCachedPlugin_redoBranch_payload; + _zz_247 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_248 = CsrPlugin_jumpInterface_payload; + _zz_247 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_248 = BranchPlugin_jumpInterface_payload; + _zz_247 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_248 = IBusCachedPlugin_predictionJumpInterface_payload; - end - endcase - end - - always @(*) begin - case(execute_CfuPlugin_CFU_ENCODING) - 1'b0 : begin - _zz_249 = execute_CfuPlugin_functionsIds_0; - end - default : begin - _zz_249 = execute_CfuPlugin_functionsIds_1; + _zz_247 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2459,74 +2434,74 @@ module VexRiscv_inner ( default : _zz_58_string = "????"; endcase end + always @(*) begin + case(_zz_99) + `Src1CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_99_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99_string = "URS1 "; + default : _zz_99_string = "????????????"; + endcase + end always @(*) begin case(_zz_100) - `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; - default : _zz_100_string = "????????????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_100_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_100_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_100_string = "BITWISE "; + default : _zz_100_string = "????????"; endcase end always @(*) begin case(_zz_101) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; - default : _zz_101_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_101_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_101_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_101_string = "PC "; + default : _zz_101_string = "???"; endcase end always @(*) begin case(_zz_102) - `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; - default : _zz_102_string = "???"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_102_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_102_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_102_string = "AND_1"; + default : _zz_102_string = "?????"; endcase end always @(*) begin case(_zz_103) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; - default : _zz_103_string = "?????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_103_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_103_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_103_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_103_string = "SRA_1 "; + default : _zz_103_string = "?????????"; endcase end always @(*) begin case(_zz_104) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; - default : _zz_104_string = "?????????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_104_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_104_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_104_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_104_string = "JALR"; + default : _zz_104_string = "????"; endcase end always @(*) begin case(_zz_105) - `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; - default : _zz_105_string = "????"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_105_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_105_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_105_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_105_string = "ECALL"; + default : _zz_105_string = "?????"; endcase end always @(*) begin case(_zz_106) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; + `Input2Kind_defaultEncoding_RS : _zz_106_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_106_string = "IMM_I"; default : _zz_106_string = "?????"; endcase end - always @(*) begin - case(_zz_107) - `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; - default : _zz_107_string = "?????"; - endcase - end always @(*) begin case(decode_to_execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; @@ -2624,7 +2599,7 @@ module VexRiscv_inner ( end `endif - assign memory_MUL_LOW = ($signed(_zz_289) + $signed(_zz_297)); + assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2632,42 +2607,41 @@ module VexRiscv_inner ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_299; - assign execute_REGFILE_WRITE_DATA = _zz_109; + assign execute_SHIFT_RIGHT = _zz_297; + assign execute_REGFILE_WRITE_DATA = _zz_108; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_228[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_227[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_301[0]; - assign decode_IS_RS1_SIGNED = _zz_302[0]; - assign decode_IS_DIV = _zz_303[0]; + assign decode_IS_RS2_SIGNED = _zz_299[0]; + assign decode_IS_RS1_SIGNED = _zz_300[0]; + assign decode_IS_DIV = _zz_301[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_304[0]; + assign decode_IS_MUL = _zz_302[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENCODING = _zz_93[29 : 29]; - assign decode_CfuPlugin_CFU_ENABLE = _zz_305[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_306[0]; + assign decode_IS_CSR = _zz_304[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_307[0]; - assign decode_MEMORY_MANAGMENT = _zz_308[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; + assign decode_MEMORY_MANAGMENT = _zz_306[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_309[0]; + assign decode_MEMORY_WR = _zz_307[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_310[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_311[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2706,7 +2680,6 @@ module VexRiscv_inner ( assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENCODING = decode_to_execute_CfuPlugin_CFU_ENCODING; assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; @@ -2719,13 +2692,13 @@ module VexRiscv_inner ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_131; + assign execute_BRANCH_COND_RESULT = _zz_130; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_312[0]; - assign decode_RS1_USE = _zz_313[0]; + assign decode_RS2_USE = _zz_310[0]; + assign decode_RS1_USE = _zz_311[0]; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_250)begin + if(_zz_248)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2738,28 +2711,28 @@ module VexRiscv_inner ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_122; + if(_zz_119)begin + if((_zz_120 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_121; end end - if(_zz_251)begin - if(_zz_252)begin - if(_zz_124)begin + if(_zz_249)begin + if(_zz_250)begin + if(_zz_123)begin decode_RS2 = _zz_57; end end end - if(_zz_253)begin + if(_zz_251)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_126)begin + if(_zz_125)begin decode_RS2 = _zz_38; end end end - if(_zz_254)begin + if(_zz_252)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_128)begin + if(_zz_127)begin decode_RS2 = _zz_37; end end @@ -2768,28 +2741,28 @@ module VexRiscv_inner ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_122; + if(_zz_119)begin + if((_zz_120 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_121; end end - if(_zz_251)begin - if(_zz_252)begin - if(_zz_123)begin + if(_zz_249)begin + if(_zz_250)begin + if(_zz_122)begin decode_RS1 = _zz_57; end end end - if(_zz_253)begin + if(_zz_251)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin + if(_zz_124)begin decode_RS1 = _zz_38; end end end - if(_zz_254)begin + if(_zz_252)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin + if(_zz_126)begin decode_RS1 = _zz_37; end end @@ -2802,7 +2775,7 @@ module VexRiscv_inner ( if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_117; + _zz_38 = _zz_116; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin _zz_38 = memory_SHIFT_RIGHT; @@ -2814,7 +2787,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_255)begin + if(_zz_253)begin _zz_38 = memory_DivPlugin_div_result; end end @@ -2827,13 +2800,13 @@ module VexRiscv_inner ( assign _zz_41 = execute_PC; assign execute_SRC2_CTRL = _zz_42; assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_314[0]; - assign decode_SRC_ADD_ZERO = _zz_315[0]; + assign decode_SRC_USE_SUB_LESS = _zz_312[0]; + assign decode_SRC_ADD_ZERO = _zz_313[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_115; - assign execute_SRC1 = _zz_110; + assign execute_SRC2 = _zz_114; + assign execute_SRC1 = _zz_109; assign execute_ALU_BITWISE_CTRL = _zz_45; assign _zz_46 = writeBack_INSTRUCTION; assign _zz_47 = writeBack_REGFILE_WRITE_VALID; @@ -2846,25 +2819,25 @@ module VexRiscv_inner ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_316[0]; + decode_REGFILE_WRITE_VALID = _zz_314[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_391) == 32'h00000003),{(_zz_392 == _zz_393),{_zz_394,{_zz_395,_zz_396}}}}}}} != 23'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}} != 22'h0); always @ (*) begin _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_288) + case(_zz_286) 2'b00 : begin - _zz_57 = _zz_363; + _zz_57 = _zz_360; end default : begin - _zz_57 = _zz_364; + _zz_57 = _zz_361; end endcase end @@ -2883,32 +2856,32 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_317[0]; - assign decode_FLUSH_ALL = _zz_318[0]; + assign decode_MEMORY_ENABLE = _zz_315[0]; + assign decode_FLUSH_ALL = _zz_316[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_256)begin + if(_zz_254)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_257)begin + if(_zz_255)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_258)begin + if(_zz_256)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_259)begin + if(_zz_257)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2941,7 +2914,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin + if((decode_arbitration_isValid && (_zz_117 || _zz_118)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2954,7 +2927,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_260)begin + if(_zz_258)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2968,22 +2941,22 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_260)begin + if(_zz_258)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_244 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_243 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_261)begin + if(_zz_259)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_250)begin + if(_zz_248)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3002,7 +2975,7 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_262)begin + if(_zz_260)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -3016,7 +2989,7 @@ module VexRiscv_inner ( if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_262)begin + if(_zz_260)begin execute_arbitration_flushNext = 1'b1; end end @@ -3028,7 +3001,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_255)begin + if(_zz_253)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3087,10 +3060,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_263)begin + if(_zz_261)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_264)begin + if(_zz_262)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3104,10 +3077,10 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_263)begin + if(_zz_261)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_264)begin + if(_zz_262)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3121,7 +3094,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_261)begin + if(_zz_259)begin CsrPlugin_inWfi = 1'b1; end end @@ -3129,21 +3102,21 @@ module VexRiscv_inner ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_263)begin + if(_zz_261)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_264)begin + if(_zz_262)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_263)begin + if(_zz_261)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_264)begin - case(_zz_265) + if(_zz_262)begin + case(_zz_263) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3159,11 +3132,11 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_62 = (_zz_61 & (~ _zz_319)); + assign _zz_62 = (_zz_61 & (~ _zz_317)); assign _zz_63 = _zz_62[3]; assign _zz_64 = (_zz_62[1] || _zz_63); assign _zz_65 = (_zz_62[2] || _zz_63); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_248; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3183,7 +3156,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_321); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_319); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3274,7 +3247,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_75 = _zz_322[11]; + assign _zz_75 = _zz_320[11]; always @ (*) begin _zz_76[18] = _zz_75; _zz_76[17] = _zz_75; @@ -3298,13 +3271,13 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_323[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_321[31])); if(_zz_81)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_77 = _zz_324[19]; + assign _zz_77 = _zz_322[19]; always @ (*) begin _zz_78[10] = _zz_77; _zz_78[9] = _zz_77; @@ -3319,7 +3292,7 @@ module VexRiscv_inner ( _zz_78[0] = _zz_77; end - assign _zz_79 = _zz_325[11]; + assign _zz_79 = _zz_323[11]; always @ (*) begin _zz_80[18] = _zz_79; _zz_80[17] = _zz_79; @@ -3345,16 +3318,16 @@ module VexRiscv_inner ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_81 = _zz_326[1]; + _zz_81 = _zz_324[1]; end default : begin - _zz_81 = _zz_327[1]; + _zz_81 = _zz_325[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_82 = _zz_328[19]; + assign _zz_82 = _zz_326[19]; always @ (*) begin _zz_83[10] = _zz_82; _zz_83[9] = _zz_82; @@ -3369,7 +3342,7 @@ module VexRiscv_inner ( _zz_83[0] = _zz_82; end - assign _zz_84 = _zz_329[11]; + assign _zz_84 = _zz_327[11]; always @ (*) begin _zz_85[18] = _zz_84; _zz_85[17] = _zz_84; @@ -3392,7 +3365,7 @@ module VexRiscv_inner ( _zz_85[0] = _zz_84; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_409,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_410,_zz_411},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_406,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_407,_zz_408},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3401,52 +3374,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_220 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_221 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_220; + assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_219; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_223 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_224 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_225 = (CsrPlugin_privilege == 2'b00); + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_224 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_259)begin + if(_zz_257)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_257)begin + if(_zz_255)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_226 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_257)begin - _zz_226 = 1'b1; + _zz_225 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_255)begin + _zz_225 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_258)begin + if(_zz_256)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_256)begin + if(_zz_254)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_258)begin + if(_zz_256)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_256)begin + if(_zz_254)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3456,9 +3429,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_218 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_217 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_245 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_244 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3485,8 +3458,8 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_227 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_228 = execute_SRC_ADD; + assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_227 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3501,27 +3474,27 @@ module VexRiscv_inner ( endcase end - assign _zz_244 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_229 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_230 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_229; + assign _zz_243 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_228 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_229 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_228; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_230; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_229; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_231 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_230 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_231 = 1'b1; + _zz_230 = 1'b1; end end - assign _zz_232 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_233 = (CsrPlugin_privilege == 2'b00); - assign _zz_234 = writeBack_REGFILE_WRITE_DATA; + assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_232 = (CsrPlugin_privilege == 2'b00); + assign _zz_233 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_266)begin + if(_zz_264)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3531,7 +3504,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_266)begin + if(_zz_264)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3550,15 +3523,15 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_266)begin + if(_zz_264)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_330}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_331}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; end end end @@ -3631,7 +3604,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_286) + case(_zz_284) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_90; end @@ -3664,51 +3637,50 @@ module VexRiscv_inner ( assign DBusCachedPlugin_mmuBus_busy = 1'b0; assign _zz_94 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); assign _zz_95 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_96 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_98 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_93 = {(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{((_zz_412 == _zz_413) != 1'b0),{(_zz_414 != 1'b0),{(_zz_415 != _zz_416),{_zz_417,{_zz_418,_zz_419}}}}}}}; - assign _zz_100 = _zz_93[2 : 1]; - assign _zz_56 = _zz_100; - assign _zz_101 = _zz_93[7 : 6]; - assign _zz_55 = _zz_101; - assign _zz_102 = _zz_93[9 : 8]; - assign _zz_54 = _zz_102; - assign _zz_103 = _zz_93[19 : 18]; - assign _zz_53 = _zz_103; - assign _zz_104 = _zz_93[22 : 21]; - assign _zz_52 = _zz_104; - assign _zz_105 = _zz_93[24 : 23]; - assign _zz_51 = _zz_105; - assign _zz_106 = _zz_93[27 : 26]; - assign _zz_50 = _zz_106; - assign _zz_107 = _zz_93[30 : 30]; - assign _zz_49 = _zz_107; + assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_409 == _zz_410) != 1'b0),{(_zz_411 != 1'b0),{1'b0,{_zz_412,{_zz_413,_zz_414}}}}}}}; + assign _zz_99 = _zz_93[2 : 1]; + assign _zz_56 = _zz_99; + assign _zz_100 = _zz_93[7 : 6]; + assign _zz_55 = _zz_100; + assign _zz_101 = _zz_93[9 : 8]; + assign _zz_54 = _zz_101; + assign _zz_102 = _zz_93[19 : 18]; + assign _zz_53 = _zz_102; + assign _zz_103 = _zz_93[22 : 21]; + assign _zz_52 = _zz_103; + assign _zz_104 = _zz_93[24 : 23]; + assign _zz_51 = _zz_104; + assign _zz_105 = _zz_93[27 : 26]; + assign _zz_50 = _zz_105; + assign _zz_106 = _zz_93[29 : 29]; + assign _zz_49 = _zz_106; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_246; - assign decode_RegFilePlugin_rs2Data = _zz_247; + assign decode_RegFilePlugin_rs1Data = _zz_245; + assign decode_RegFilePlugin_rs2Data = _zz_246; always @ (*) begin lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_108)begin + if(_zz_107)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_108)begin + if(_zz_107)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_108)begin + if(_zz_107)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -3730,13 +3702,13 @@ module VexRiscv_inner ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_109 = execute_IntAluPlugin_bitwise; + _zz_108 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_109 = {31'd0, _zz_332}; + _zz_108 = {31'd0, _zz_330}; end default : begin - _zz_109 = execute_SRC_ADD_SUB; + _zz_108 = execute_SRC_ADD_SUB; end endcase end @@ -3744,87 +3716,87 @@ module VexRiscv_inner ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_110 = execute_RS1; + _zz_109 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_110 = {29'd0, _zz_333}; + _zz_109 = {29'd0, _zz_331}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_110 = {27'd0, _zz_334}; + _zz_109 = {27'd0, _zz_332}; end endcase end - assign _zz_111 = _zz_335[11]; - always @ (*) begin - _zz_112[19] = _zz_111; - _zz_112[18] = _zz_111; - _zz_112[17] = _zz_111; - _zz_112[16] = _zz_111; - _zz_112[15] = _zz_111; - _zz_112[14] = _zz_111; - _zz_112[13] = _zz_111; - _zz_112[12] = _zz_111; - _zz_112[11] = _zz_111; - _zz_112[10] = _zz_111; - _zz_112[9] = _zz_111; - _zz_112[8] = _zz_111; - _zz_112[7] = _zz_111; - _zz_112[6] = _zz_111; - _zz_112[5] = _zz_111; - _zz_112[4] = _zz_111; - _zz_112[3] = _zz_111; - _zz_112[2] = _zz_111; - _zz_112[1] = _zz_111; - _zz_112[0] = _zz_111; - end - - assign _zz_113 = _zz_336[11]; - always @ (*) begin - _zz_114[19] = _zz_113; - _zz_114[18] = _zz_113; - _zz_114[17] = _zz_113; - _zz_114[16] = _zz_113; - _zz_114[15] = _zz_113; - _zz_114[14] = _zz_113; - _zz_114[13] = _zz_113; - _zz_114[12] = _zz_113; - _zz_114[11] = _zz_113; - _zz_114[10] = _zz_113; - _zz_114[9] = _zz_113; - _zz_114[8] = _zz_113; - _zz_114[7] = _zz_113; - _zz_114[6] = _zz_113; - _zz_114[5] = _zz_113; - _zz_114[4] = _zz_113; - _zz_114[3] = _zz_113; - _zz_114[2] = _zz_113; - _zz_114[1] = _zz_113; - _zz_114[0] = _zz_113; + assign _zz_110 = _zz_333[11]; + always @ (*) begin + _zz_111[19] = _zz_110; + _zz_111[18] = _zz_110; + _zz_111[17] = _zz_110; + _zz_111[16] = _zz_110; + _zz_111[15] = _zz_110; + _zz_111[14] = _zz_110; + _zz_111[13] = _zz_110; + _zz_111[12] = _zz_110; + _zz_111[11] = _zz_110; + _zz_111[10] = _zz_110; + _zz_111[9] = _zz_110; + _zz_111[8] = _zz_110; + _zz_111[7] = _zz_110; + _zz_111[6] = _zz_110; + _zz_111[5] = _zz_110; + _zz_111[4] = _zz_110; + _zz_111[3] = _zz_110; + _zz_111[2] = _zz_110; + _zz_111[1] = _zz_110; + _zz_111[0] = _zz_110; + end + + assign _zz_112 = _zz_334[11]; + always @ (*) begin + _zz_113[19] = _zz_112; + _zz_113[18] = _zz_112; + _zz_113[17] = _zz_112; + _zz_113[16] = _zz_112; + _zz_113[15] = _zz_112; + _zz_113[14] = _zz_112; + _zz_113[13] = _zz_112; + _zz_113[12] = _zz_112; + _zz_113[11] = _zz_112; + _zz_113[10] = _zz_112; + _zz_113[9] = _zz_112; + _zz_113[8] = _zz_112; + _zz_113[7] = _zz_112; + _zz_113[6] = _zz_112; + _zz_113[5] = _zz_112; + _zz_113[4] = _zz_112; + _zz_113[3] = _zz_112; + _zz_113[2] = _zz_112; + _zz_113[1] = _zz_112; + _zz_113[0] = _zz_112; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_115 = execute_RS2; + _zz_114 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; + _zz_114 = {_zz_111,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_114 = {_zz_113,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_115 = _zz_41; + _zz_114 = _zz_41; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_337; + execute_SrcPlugin_addSub = _zz_335; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3833,246 +3805,246 @@ module VexRiscv_inner ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_116[0] = execute_SRC1[31]; - _zz_116[1] = execute_SRC1[30]; - _zz_116[2] = execute_SRC1[29]; - _zz_116[3] = execute_SRC1[28]; - _zz_116[4] = execute_SRC1[27]; - _zz_116[5] = execute_SRC1[26]; - _zz_116[6] = execute_SRC1[25]; - _zz_116[7] = execute_SRC1[24]; - _zz_116[8] = execute_SRC1[23]; - _zz_116[9] = execute_SRC1[22]; - _zz_116[10] = execute_SRC1[21]; - _zz_116[11] = execute_SRC1[20]; - _zz_116[12] = execute_SRC1[19]; - _zz_116[13] = execute_SRC1[18]; - _zz_116[14] = execute_SRC1[17]; - _zz_116[15] = execute_SRC1[16]; - _zz_116[16] = execute_SRC1[15]; - _zz_116[17] = execute_SRC1[14]; - _zz_116[18] = execute_SRC1[13]; - _zz_116[19] = execute_SRC1[12]; - _zz_116[20] = execute_SRC1[11]; - _zz_116[21] = execute_SRC1[10]; - _zz_116[22] = execute_SRC1[9]; - _zz_116[23] = execute_SRC1[8]; - _zz_116[24] = execute_SRC1[7]; - _zz_116[25] = execute_SRC1[6]; - _zz_116[26] = execute_SRC1[5]; - _zz_116[27] = execute_SRC1[4]; - _zz_116[28] = execute_SRC1[3]; - _zz_116[29] = execute_SRC1[2]; - _zz_116[30] = execute_SRC1[1]; - _zz_116[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); - always @ (*) begin - _zz_117[0] = memory_SHIFT_RIGHT[31]; - _zz_117[1] = memory_SHIFT_RIGHT[30]; - _zz_117[2] = memory_SHIFT_RIGHT[29]; - _zz_117[3] = memory_SHIFT_RIGHT[28]; - _zz_117[4] = memory_SHIFT_RIGHT[27]; - _zz_117[5] = memory_SHIFT_RIGHT[26]; - _zz_117[6] = memory_SHIFT_RIGHT[25]; - _zz_117[7] = memory_SHIFT_RIGHT[24]; - _zz_117[8] = memory_SHIFT_RIGHT[23]; - _zz_117[9] = memory_SHIFT_RIGHT[22]; - _zz_117[10] = memory_SHIFT_RIGHT[21]; - _zz_117[11] = memory_SHIFT_RIGHT[20]; - _zz_117[12] = memory_SHIFT_RIGHT[19]; - _zz_117[13] = memory_SHIFT_RIGHT[18]; - _zz_117[14] = memory_SHIFT_RIGHT[17]; - _zz_117[15] = memory_SHIFT_RIGHT[16]; - _zz_117[16] = memory_SHIFT_RIGHT[15]; - _zz_117[17] = memory_SHIFT_RIGHT[14]; - _zz_117[18] = memory_SHIFT_RIGHT[13]; - _zz_117[19] = memory_SHIFT_RIGHT[12]; - _zz_117[20] = memory_SHIFT_RIGHT[11]; - _zz_117[21] = memory_SHIFT_RIGHT[10]; - _zz_117[22] = memory_SHIFT_RIGHT[9]; - _zz_117[23] = memory_SHIFT_RIGHT[8]; - _zz_117[24] = memory_SHIFT_RIGHT[7]; - _zz_117[25] = memory_SHIFT_RIGHT[6]; - _zz_117[26] = memory_SHIFT_RIGHT[5]; - _zz_117[27] = memory_SHIFT_RIGHT[4]; - _zz_117[28] = memory_SHIFT_RIGHT[3]; - _zz_117[29] = memory_SHIFT_RIGHT[2]; - _zz_117[30] = memory_SHIFT_RIGHT[1]; - _zz_117[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_118 = 1'b0; + _zz_115[0] = execute_SRC1[31]; + _zz_115[1] = execute_SRC1[30]; + _zz_115[2] = execute_SRC1[29]; + _zz_115[3] = execute_SRC1[28]; + _zz_115[4] = execute_SRC1[27]; + _zz_115[5] = execute_SRC1[26]; + _zz_115[6] = execute_SRC1[25]; + _zz_115[7] = execute_SRC1[24]; + _zz_115[8] = execute_SRC1[23]; + _zz_115[9] = execute_SRC1[22]; + _zz_115[10] = execute_SRC1[21]; + _zz_115[11] = execute_SRC1[20]; + _zz_115[12] = execute_SRC1[19]; + _zz_115[13] = execute_SRC1[18]; + _zz_115[14] = execute_SRC1[17]; + _zz_115[15] = execute_SRC1[16]; + _zz_115[16] = execute_SRC1[15]; + _zz_115[17] = execute_SRC1[14]; + _zz_115[18] = execute_SRC1[13]; + _zz_115[19] = execute_SRC1[12]; + _zz_115[20] = execute_SRC1[11]; + _zz_115[21] = execute_SRC1[10]; + _zz_115[22] = execute_SRC1[9]; + _zz_115[23] = execute_SRC1[8]; + _zz_115[24] = execute_SRC1[7]; + _zz_115[25] = execute_SRC1[6]; + _zz_115[26] = execute_SRC1[5]; + _zz_115[27] = execute_SRC1[4]; + _zz_115[28] = execute_SRC1[3]; + _zz_115[29] = execute_SRC1[2]; + _zz_115[30] = execute_SRC1[1]; + _zz_115[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_115 : execute_SRC1); + always @ (*) begin + _zz_116[0] = memory_SHIFT_RIGHT[31]; + _zz_116[1] = memory_SHIFT_RIGHT[30]; + _zz_116[2] = memory_SHIFT_RIGHT[29]; + _zz_116[3] = memory_SHIFT_RIGHT[28]; + _zz_116[4] = memory_SHIFT_RIGHT[27]; + _zz_116[5] = memory_SHIFT_RIGHT[26]; + _zz_116[6] = memory_SHIFT_RIGHT[25]; + _zz_116[7] = memory_SHIFT_RIGHT[24]; + _zz_116[8] = memory_SHIFT_RIGHT[23]; + _zz_116[9] = memory_SHIFT_RIGHT[22]; + _zz_116[10] = memory_SHIFT_RIGHT[21]; + _zz_116[11] = memory_SHIFT_RIGHT[20]; + _zz_116[12] = memory_SHIFT_RIGHT[19]; + _zz_116[13] = memory_SHIFT_RIGHT[18]; + _zz_116[14] = memory_SHIFT_RIGHT[17]; + _zz_116[15] = memory_SHIFT_RIGHT[16]; + _zz_116[16] = memory_SHIFT_RIGHT[15]; + _zz_116[17] = memory_SHIFT_RIGHT[14]; + _zz_116[18] = memory_SHIFT_RIGHT[13]; + _zz_116[19] = memory_SHIFT_RIGHT[12]; + _zz_116[20] = memory_SHIFT_RIGHT[11]; + _zz_116[21] = memory_SHIFT_RIGHT[10]; + _zz_116[22] = memory_SHIFT_RIGHT[9]; + _zz_116[23] = memory_SHIFT_RIGHT[8]; + _zz_116[24] = memory_SHIFT_RIGHT[7]; + _zz_116[25] = memory_SHIFT_RIGHT[6]; + _zz_116[26] = memory_SHIFT_RIGHT[5]; + _zz_116[27] = memory_SHIFT_RIGHT[4]; + _zz_116[28] = memory_SHIFT_RIGHT[3]; + _zz_116[29] = memory_SHIFT_RIGHT[2]; + _zz_116[30] = memory_SHIFT_RIGHT[1]; + _zz_116[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_117 = 1'b0; + if(_zz_265)begin + if(_zz_266)begin + if(_zz_122)begin + _zz_117 = 1'b1; + end + end + end if(_zz_267)begin if(_zz_268)begin - if(_zz_123)begin - _zz_118 = 1'b1; + if(_zz_124)begin + _zz_117 = 1'b1; end end end if(_zz_269)begin if(_zz_270)begin - if(_zz_125)begin - _zz_118 = 1'b1; - end - end - end - if(_zz_271)begin - if(_zz_272)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(_zz_126)begin + _zz_117 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_118 = 1'b0; + _zz_117 = 1'b0; end end always @ (*) begin - _zz_119 = 1'b0; + _zz_118 = 1'b0; + if(_zz_265)begin + if(_zz_266)begin + if(_zz_123)begin + _zz_118 = 1'b1; + end + end + end if(_zz_267)begin if(_zz_268)begin - if(_zz_124)begin - _zz_119 = 1'b1; + if(_zz_125)begin + _zz_118 = 1'b1; end end end if(_zz_269)begin if(_zz_270)begin - if(_zz_126)begin - _zz_119 = 1'b1; - end - end - end - if(_zz_271)begin - if(_zz_272)begin - if(_zz_128)begin - _zz_119 = 1'b1; + if(_zz_127)begin + _zz_118 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_119 = 1'b0; + _zz_118 = 1'b0; end end - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_129 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_129 == 3'b000)) begin - _zz_130 = execute_BranchPlugin_eq; - end else if((_zz_129 == 3'b001)) begin - _zz_130 = (! execute_BranchPlugin_eq); - end else if((((_zz_129 & 3'b101) == 3'b101))) begin - _zz_130 = (! execute_SRC_LESS); + assign _zz_128 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_128 == 3'b000)) begin + _zz_129 = execute_BranchPlugin_eq; + end else if((_zz_128 == 3'b001)) begin + _zz_129 = (! execute_BranchPlugin_eq); + end else if((((_zz_128 & 3'b101) == 3'b101))) begin + _zz_129 = (! execute_SRC_LESS); end else begin - _zz_130 = execute_SRC_LESS; + _zz_129 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_131 = 1'b0; + _zz_130 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_131 = 1'b1; + _zz_130 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_131 = 1'b1; + _zz_130 = 1'b1; end default : begin - _zz_131 = _zz_130; + _zz_130 = _zz_129; end endcase end - assign _zz_132 = _zz_344[11]; - always @ (*) begin - _zz_133[19] = _zz_132; - _zz_133[18] = _zz_132; - _zz_133[17] = _zz_132; - _zz_133[16] = _zz_132; - _zz_133[15] = _zz_132; - _zz_133[14] = _zz_132; - _zz_133[13] = _zz_132; - _zz_133[12] = _zz_132; - _zz_133[11] = _zz_132; - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; - end - - assign _zz_134 = _zz_345[19]; - always @ (*) begin - _zz_135[10] = _zz_134; - _zz_135[9] = _zz_134; - _zz_135[8] = _zz_134; - _zz_135[7] = _zz_134; - _zz_135[6] = _zz_134; - _zz_135[5] = _zz_134; - _zz_135[4] = _zz_134; - _zz_135[3] = _zz_134; - _zz_135[2] = _zz_134; - _zz_135[1] = _zz_134; - _zz_135[0] = _zz_134; - end - - assign _zz_136 = _zz_346[11]; - always @ (*) begin - _zz_137[18] = _zz_136; - _zz_137[17] = _zz_136; - _zz_137[16] = _zz_136; - _zz_137[15] = _zz_136; - _zz_137[14] = _zz_136; - _zz_137[13] = _zz_136; - _zz_137[12] = _zz_136; - _zz_137[11] = _zz_136; - _zz_137[10] = _zz_136; - _zz_137[9] = _zz_136; - _zz_137[8] = _zz_136; - _zz_137[7] = _zz_136; - _zz_137[6] = _zz_136; - _zz_137[5] = _zz_136; - _zz_137[4] = _zz_136; - _zz_137[3] = _zz_136; - _zz_137[2] = _zz_136; - _zz_137[1] = _zz_136; - _zz_137[0] = _zz_136; + assign _zz_131 = _zz_342[11]; + always @ (*) begin + _zz_132[19] = _zz_131; + _zz_132[18] = _zz_131; + _zz_132[17] = _zz_131; + _zz_132[16] = _zz_131; + _zz_132[15] = _zz_131; + _zz_132[14] = _zz_131; + _zz_132[13] = _zz_131; + _zz_132[12] = _zz_131; + _zz_132[11] = _zz_131; + _zz_132[10] = _zz_131; + _zz_132[9] = _zz_131; + _zz_132[8] = _zz_131; + _zz_132[7] = _zz_131; + _zz_132[6] = _zz_131; + _zz_132[5] = _zz_131; + _zz_132[4] = _zz_131; + _zz_132[3] = _zz_131; + _zz_132[2] = _zz_131; + _zz_132[1] = _zz_131; + _zz_132[0] = _zz_131; + end + + assign _zz_133 = _zz_343[19]; + always @ (*) begin + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; + end + + assign _zz_135 = _zz_344[11]; + always @ (*) begin + _zz_136[18] = _zz_135; + _zz_136[17] = _zz_135; + _zz_136[16] = _zz_135; + _zz_136[15] = _zz_135; + _zz_136[14] = _zz_135; + _zz_136[13] = _zz_135; + _zz_136[12] = _zz_135; + _zz_136[11] = _zz_135; + _zz_136[10] = _zz_135; + _zz_136[9] = _zz_135; + _zz_136[8] = _zz_135; + _zz_136[7] = _zz_135; + _zz_136[6] = _zz_135; + _zz_136[5] = _zz_135; + _zz_136[4] = _zz_135; + _zz_136[3] = _zz_135; + _zz_136[2] = _zz_135; + _zz_136[1] = _zz_135; + _zz_136[0] = _zz_135; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_138 = (_zz_347[1] ^ execute_RS1[1]); + _zz_137 = (_zz_345[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_138 = _zz_348[1]; + _zz_137 = _zz_346[1]; end default : begin - _zz_138 = _zz_349[1]; + _zz_137 = _zz_347[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_137); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4084,80 +4056,80 @@ module VexRiscv_inner ( endcase end - assign _zz_139 = _zz_350[11]; + assign _zz_138 = _zz_348[11]; always @ (*) begin - _zz_140[19] = _zz_139; - _zz_140[18] = _zz_139; - _zz_140[17] = _zz_139; - _zz_140[16] = _zz_139; - _zz_140[15] = _zz_139; - _zz_140[14] = _zz_139; - _zz_140[13] = _zz_139; - _zz_140[12] = _zz_139; - _zz_140[11] = _zz_139; - _zz_140[10] = _zz_139; - _zz_140[9] = _zz_139; - _zz_140[8] = _zz_139; - _zz_140[7] = _zz_139; - _zz_140[6] = _zz_139; - _zz_140[5] = _zz_139; - _zz_140[4] = _zz_139; - _zz_140[3] = _zz_139; - _zz_140[2] = _zz_139; - _zz_140[1] = _zz_139; - _zz_140[0] = _zz_139; + _zz_139[19] = _zz_138; + _zz_139[18] = _zz_138; + _zz_139[17] = _zz_138; + _zz_139[16] = _zz_138; + _zz_139[15] = _zz_138; + _zz_139[14] = _zz_138; + _zz_139[13] = _zz_138; + _zz_139[12] = _zz_138; + _zz_139[11] = _zz_138; + _zz_139[10] = _zz_138; + _zz_139[9] = _zz_138; + _zz_139[8] = _zz_138; + _zz_139[7] = _zz_138; + _zz_139[6] = _zz_138; + _zz_139[5] = _zz_138; + _zz_139[4] = _zz_138; + _zz_139[3] = _zz_138; + _zz_139[2] = _zz_138; + _zz_139[1] = _zz_138; + _zz_139[0] = _zz_138; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_583,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_584,_zz_585},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_577,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_578,_zz_579},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_353}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_351}; end end endcase end - assign _zz_141 = _zz_351[19]; - always @ (*) begin - _zz_142[10] = _zz_141; - _zz_142[9] = _zz_141; - _zz_142[8] = _zz_141; - _zz_142[7] = _zz_141; - _zz_142[6] = _zz_141; - _zz_142[5] = _zz_141; - _zz_142[4] = _zz_141; - _zz_142[3] = _zz_141; - _zz_142[2] = _zz_141; - _zz_142[1] = _zz_141; - _zz_142[0] = _zz_141; - end - - assign _zz_143 = _zz_352[11]; - always @ (*) begin - _zz_144[18] = _zz_143; - _zz_144[17] = _zz_143; - _zz_144[16] = _zz_143; - _zz_144[15] = _zz_143; - _zz_144[14] = _zz_143; - _zz_144[13] = _zz_143; - _zz_144[12] = _zz_143; - _zz_144[11] = _zz_143; - _zz_144[10] = _zz_143; - _zz_144[9] = _zz_143; - _zz_144[8] = _zz_143; - _zz_144[7] = _zz_143; - _zz_144[6] = _zz_143; - _zz_144[5] = _zz_143; - _zz_144[4] = _zz_143; - _zz_144[3] = _zz_143; - _zz_144[2] = _zz_143; - _zz_144[1] = _zz_143; - _zz_144[0] = _zz_143; + assign _zz_140 = _zz_349[19]; + always @ (*) begin + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; + end + + assign _zz_142 = _zz_350[11]; + always @ (*) begin + _zz_143[18] = _zz_142; + _zz_143[17] = _zz_142; + _zz_143[16] = _zz_142; + _zz_143[15] = _zz_142; + _zz_143[14] = _zz_142; + _zz_143[13] = _zz_142; + _zz_143[12] = _zz_142; + _zz_143[11] = _zz_142; + _zz_143[10] = _zz_142; + _zz_143[9] = _zz_142; + _zz_143[8] = _zz_142; + _zz_143[7] = _zz_142; + _zz_143[6] = _zz_142; + _zz_143[5] = _zz_142; + _zz_143[4] = _zz_142; + _zz_143[3] = _zz_142; + _zz_143[2] = _zz_142; + _zz_143[1] = _zz_142; + _zz_143[0] = _zz_142; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -4180,18 +4152,18 @@ module VexRiscv_inner ( end end - assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_144 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_145 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_146 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_149 = _zz_354[0]; - assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_151 = _zz_356[0]; + assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_148 = _zz_352[0]; + assign _zz_149 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_150 = _zz_354[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_260)begin + if(_zz_258)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4201,7 +4173,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_262)begin + if(_zz_260)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -4442,7 +4414,7 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_273)begin + if(_zz_271)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4461,20 +4433,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_274)begin + if(_zz_272)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_275)begin + if(_zz_273)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_274)begin + if(_zz_272)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_275)begin + if(_zz_273)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4489,14 +4461,14 @@ module VexRiscv_inner ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_273)begin + if(_zz_271)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_273)begin + if(_zz_271)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4505,7 +4477,7 @@ module VexRiscv_inner ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_287) + case(_zz_285) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4518,50 +4490,49 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_358; - assign execute_CfuPlugin_functionsIds_1 = {6'd0, _zz_359}; - assign CfuPlugin_bus_cmd_payload_function_id = _zz_249; + assign execute_CfuPlugin_functionsIds_0 = _zz_356; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_168 = _zz_360[7]; - always @ (*) begin - _zz_169[23] = _zz_168; - _zz_169[22] = _zz_168; - _zz_169[21] = _zz_168; - _zz_169[20] = _zz_168; - _zz_169[19] = _zz_168; - _zz_169[18] = _zz_168; - _zz_169[17] = _zz_168; - _zz_169[16] = _zz_168; - _zz_169[15] = _zz_168; - _zz_169[14] = _zz_168; - _zz_169[13] = _zz_168; - _zz_169[12] = _zz_168; - _zz_169[11] = _zz_168; - _zz_169[10] = _zz_168; - _zz_169[9] = _zz_168; - _zz_169[8] = _zz_168; - _zz_169[7] = _zz_168; - _zz_169[6] = _zz_168; - _zz_169[5] = _zz_168; - _zz_169[4] = _zz_168; - _zz_169[3] = _zz_168; - _zz_169[2] = _zz_168; - _zz_169[1] = _zz_168; - _zz_169[0] = _zz_168; + assign _zz_167 = _zz_357[7]; + always @ (*) begin + _zz_168[23] = _zz_167; + _zz_168[22] = _zz_167; + _zz_168[21] = _zz_167; + _zz_168[20] = _zz_167; + _zz_168[19] = _zz_167; + _zz_168[18] = _zz_167; + _zz_168[17] = _zz_167; + _zz_168[16] = _zz_167; + _zz_168[15] = _zz_167; + _zz_168[14] = _zz_167; + _zz_168[13] = _zz_167; + _zz_168[12] = _zz_167; + _zz_168[11] = _zz_167; + _zz_168[10] = _zz_167; + _zz_168[9] = _zz_167; + _zz_168[8] = _zz_167; + _zz_168[7] = _zz_167; + _zz_168[6] = _zz_167; + _zz_168[5] = _zz_167; + _zz_168[4] = _zz_167; + _zz_168[3] = _zz_167; + _zz_168[2] = _zz_167; + _zz_168[1] = _zz_167; + _zz_168[0] = _zz_167; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_170 = execute_RS2; + _zz_169 = execute_RS2; end default : begin - _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 24]}; + _zz_169 = {_zz_168,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_169; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4587,7 +4558,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_276) + case(_zz_274) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4601,7 +4572,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_276) + case(_zz_274) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4620,12 +4591,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_361) + $signed(_zz_362)); + assign writeBack_MulPlugin_result = ($signed(_zz_358) + $signed(_zz_359)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_255)begin - if(_zz_277)begin + if(_zz_253)begin + if(_zz_275)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4633,7 +4604,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_278)begin + if(_zz_276)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4644,28 +4615,28 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_366); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_363); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_367); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_368 : _zz_369); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_370[31:0]; - assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_170 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_170[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_364); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_365 : _zz_366); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_367[31:0]; + assign _zz_171 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_172 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_173 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_175[31 : 0] = execute_RS1; + _zz_174[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_174[31 : 0] = execute_RS1; end - assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_177 != 32'h0); + assign _zz_176 = (_zz_175 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_176 != 32'h0); assign _zz_29 = decode_SRC1_CTRL; assign _zz_27 = _zz_56; assign _zz_43 = decode_to_execute_SRC1_CTRL; @@ -4717,272 +4688,272 @@ module VexRiscv_inner ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_178 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_178[12 : 0] = 13'h1000; - _zz_178[25 : 20] = 6'h20; + _zz_177[12 : 0] = 13'h1000; + _zz_177[25 : 20] = 6'h20; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_179[3 : 0] = 4'b1011; + _zz_178[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_180[4 : 0] = 5'h16; + _zz_179[4 : 0] = 5'h16; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_181[5 : 0] = 6'h21; + _zz_180[5 : 0] = 6'h21; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_182[31 : 30] = CsrPlugin_misa_base; - _zz_182[25 : 0] = CsrPlugin_misa_extensions; + _zz_181[31 : 30] = CsrPlugin_misa_base; + _zz_181[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_183[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_183[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_183[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_182[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_182[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_182[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_184[11 : 11] = CsrPlugin_mip_MEIP; - _zz_184[7 : 7] = CsrPlugin_mip_MTIP; - _zz_184[3 : 3] = CsrPlugin_mip_MSIP; + _zz_183[11 : 11] = CsrPlugin_mip_MEIP; + _zz_183[7 : 7] = CsrPlugin_mip_MTIP; + _zz_183[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_185[11 : 11] = CsrPlugin_mie_MEIE; - _zz_185[7 : 7] = CsrPlugin_mie_MTIE; - _zz_185[3 : 3] = CsrPlugin_mie_MSIE; + _zz_184[11 : 11] = CsrPlugin_mie_MEIE; + _zz_184[7 : 7] = CsrPlugin_mie_MTIE; + _zz_184[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_186[31 : 2] = CsrPlugin_mtvec_base; - _zz_186[1 : 0] = CsrPlugin_mtvec_mode; + _zz_185[31 : 2] = CsrPlugin_mtvec_base; + _zz_185[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_187[31 : 0] = CsrPlugin_mepc; + _zz_186[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_188[31 : 0] = CsrPlugin_mscratch; + _zz_187[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_189[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_189[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_188[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_188[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_190[31 : 0] = CsrPlugin_mtval; + _zz_189[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_191[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_192[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_193[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_194[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_195[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_196[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_197[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_198[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_2820)begin - _zz_199[31 : 0] = _zz_152; + _zz_198[31 : 0] = _zz_151; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_199 = 32'h0; if(execute_CsrPlugin_csr_2822)begin - _zz_200[31 : 0] = _zz_154; + _zz_199[31 : 0] = _zz_153; end end always @ (*) begin - _zz_201 = 32'h0; + _zz_200 = 32'h0; if(execute_CsrPlugin_csr_2824)begin - _zz_201[31 : 0] = _zz_156; + _zz_200[31 : 0] = _zz_155; end end always @ (*) begin - _zz_202 = 32'h0; + _zz_201 = 32'h0; if(execute_CsrPlugin_csr_2826)begin - _zz_202[31 : 0] = _zz_158; + _zz_201[31 : 0] = _zz_157; end end always @ (*) begin - _zz_203 = 32'h0; + _zz_202 = 32'h0; if(execute_CsrPlugin_csr_2828)begin - _zz_203[31 : 0] = _zz_160; + _zz_202[31 : 0] = _zz_159; end end always @ (*) begin - _zz_204 = 32'h0; + _zz_203 = 32'h0; if(execute_CsrPlugin_csr_2830)begin - _zz_204[31 : 0] = _zz_162; + _zz_203[31 : 0] = _zz_161; end end always @ (*) begin - _zz_205 = 32'h0; + _zz_204 = 32'h0; if(execute_CsrPlugin_csr_2832)begin - _zz_205[31 : 0] = _zz_164; + _zz_204[31 : 0] = _zz_163; end end always @ (*) begin - _zz_206 = 32'h0; + _zz_205 = 32'h0; if(execute_CsrPlugin_csr_2834)begin - _zz_206[31 : 0] = _zz_166; + _zz_205[31 : 0] = _zz_165; end end always @ (*) begin - _zz_207 = 32'h0; + _zz_206 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_207[31 : 0] = _zz_176; + _zz_206[31 : 0] = _zz_175; end end always @ (*) begin - _zz_208 = 32'h0; + _zz_207 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_208[31 : 0] = _zz_177; + _zz_207[31 : 0] = _zz_176; end end - assign execute_CsrPlugin_readData = (((((_zz_178 | _zz_179) | (_zz_180 | _zz_181)) | ((_zz_586 | _zz_182) | (_zz_183 | _zz_184))) | (((_zz_185 | _zz_186) | (_zz_187 | _zz_188)) | ((_zz_189 | _zz_190) | (_zz_191 | _zz_192)))) | ((((_zz_193 | _zz_194) | (_zz_195 | _zz_196)) | ((_zz_197 | _zz_198) | (_zz_199 | _zz_200))) | (((_zz_201 | _zz_202) | (_zz_203 | _zz_204)) | ((_zz_205 | _zz_206) | (_zz_207 | _zz_208))))); - assign iBusWishbone_ADR = {_zz_387,_zz_209}; - assign iBusWishbone_CTI = ((_zz_209 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_580 | _zz_181) | (_zz_182 | _zz_183))) | (((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191)))) | ((((_zz_192 | _zz_193) | (_zz_194 | _zz_195)) | ((_zz_196 | _zz_197) | (_zz_198 | _zz_199))) | (((_zz_200 | _zz_201) | (_zz_202 | _zz_203)) | ((_zz_204 | _zz_205) | (_zz_206 | _zz_207))))); + assign iBusWishbone_ADR = {_zz_384,_zz_208}; + assign iBusWishbone_CTI = ((_zz_208 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_279)begin + if(_zz_277)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_279)begin + if(_zz_277)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_210; + assign iBus_rsp_valid = _zz_209; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_216 = (dBus_cmd_payload_length != 3'b000); - assign _zz_212 = dBus_cmd_valid; - assign _zz_214 = dBus_cmd_payload_wr; - assign _zz_215 = (_zz_211 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_213 && (_zz_214 || _zz_215)); - assign dBusWishbone_ADR = ((_zz_216 ? {{dBus_cmd_payload_address[31 : 5],_zz_211},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_216 ? (_zz_215 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_215 = (dBus_cmd_payload_length != 3'b000); + assign _zz_211 = dBus_cmd_valid; + assign _zz_213 = dBus_cmd_payload_wr; + assign _zz_214 = (_zz_210 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_212 && (_zz_213 || _zz_214)); + assign dBusWishbone_ADR = ((_zz_215 ? {{dBus_cmd_payload_address[31 : 5],_zz_210},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_215 ? (_zz_214 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_214 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_214; + assign dBusWishbone_SEL = (_zz_213 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_213; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_213 = (_zz_212 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_212; - assign dBusWishbone_STB = _zz_212; - assign dBus_rsp_valid = _zz_217; + assign _zz_212 = (_zz_211 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_211; + assign dBusWishbone_STB = _zz_211; + assign dBus_rsp_valid = _zz_216; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5004,8 +4975,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; DBusCachedPlugin_rspCounter <= _zz_87; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_108 <= 1'b1; - _zz_120 <= 1'b0; + _zz_107 <= 1'b1; + _zz_119 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -5029,15 +5000,15 @@ module VexRiscv_inner ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_176 <= 32'h0; + _zz_175 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_209 <= 3'b000; - _zz_210 <= 1'b0; - _zz_211 <= 3'b000; - _zz_217 <= 1'b0; + _zz_208 <= 3'b000; + _zz_209 <= 1'b0; + _zz_210 <= 3'b000; + _zz_216 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5118,7 +5089,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_280)begin + if(_zz_278)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5127,8 +5098,8 @@ module VexRiscv_inner ( if(dBus_rsp_valid)begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_108 <= 1'b0; - _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); + _zz_107 <= 1'b0; + _zz_119 <= (_zz_47 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5150,14 +5121,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_281)begin - if(_zz_282)begin + if(_zz_279)begin + if(_zz_280)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_283)begin + if(_zz_281)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_284)begin + if(_zz_282)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5182,7 +5153,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_263)begin + if(_zz_261)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5193,8 +5164,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_264)begin - case(_zz_265) + if(_zz_262)begin + case(_zz_263) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5204,7 +5175,7 @@ module VexRiscv_inner ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_146,{_zz_145,_zz_144}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -5220,7 +5191,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_285)begin + if(_zz_283)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; @@ -5254,35 +5225,35 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_380[0]; - CsrPlugin_mstatus_MIE <= _zz_381[0]; + CsrPlugin_mstatus_MPIE <= _zz_377[0]; + CsrPlugin_mstatus_MIE <= _zz_378[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_383[0]; - CsrPlugin_mie_MTIE <= _zz_384[0]; - CsrPlugin_mie_MSIE <= _zz_385[0]; + CsrPlugin_mie_MEIE <= _zz_380[0]; + CsrPlugin_mie_MTIE <= _zz_381[0]; + CsrPlugin_mie_MSIE <= _zz_382[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_175 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_279)begin + if(_zz_277)begin if(iBusWishbone_ACK)begin - _zz_209 <= (_zz_209 + 3'b001); + _zz_208 <= (_zz_208 + 3'b001); end end - _zz_210 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_212 && _zz_213))begin - _zz_211 <= (_zz_211 + 3'b001); - if(_zz_215)begin - _zz_211 <= 3'b000; + _zz_209 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_211 && _zz_212))begin + _zz_210 <= (_zz_210 + 3'b001); + if(_zz_214)begin + _zz_210 <= 3'b000; end end - _zz_217 <= ((_zz_212 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_216 <= ((_zz_211 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5296,7 +5267,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_280)begin + if(_zz_278)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5314,8 +5285,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - _zz_121 <= _zz_46[11 : 7]; - _zz_122 <= _zz_57; + _zz_120 <= _zz_46[11 : 7]; + _zz_121 <= _zz_57; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5323,13 +5294,13 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_260)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_258)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(_zz_262)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_260)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end if(CfuPlugin_joinException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; @@ -5339,21 +5310,21 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_281)begin - if(_zz_282)begin + if(_zz_279)begin + if(_zz_280)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_283)begin + if(_zz_281)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_284)begin + if(_zz_282)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_263)begin + if(_zz_261)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5367,31 +5338,31 @@ module VexRiscv_inner ( end endcase end - if(_zz_153[0])begin - _zz_152 <= (_zz_152 + 32'h00000001); + if(_zz_152[0])begin + _zz_151 <= (_zz_151 + 32'h00000001); end - if(_zz_155[0])begin - _zz_154 <= (_zz_154 + 32'h00000001); + if(_zz_154[0])begin + _zz_153 <= (_zz_153 + 32'h00000001); end - if(_zz_157[0])begin - _zz_156 <= (_zz_156 + 32'h00000001); + if(_zz_156[0])begin + _zz_155 <= (_zz_155 + 32'h00000001); end - if(_zz_159[0])begin - _zz_158 <= (_zz_158 + 32'h00000001); + if(_zz_158[0])begin + _zz_157 <= (_zz_157 + 32'h00000001); end - if(_zz_161[0])begin - _zz_160 <= (_zz_160 + 32'h00000001); + if(_zz_160[0])begin + _zz_159 <= (_zz_159 + 32'h00000001); end - if(_zz_163[0])begin - _zz_162 <= (_zz_162 + 32'h00000001); + if(_zz_162[0])begin + _zz_161 <= (_zz_161 + 32'h00000001); end - if(_zz_165[0])begin - _zz_164 <= (_zz_164 + 32'h00000001); + if(_zz_164[0])begin + _zz_163 <= (_zz_163 + 32'h00000001); end - if(_zz_167[0])begin - _zz_166 <= (_zz_166 + 32'h00000001); + if(_zz_166[0])begin + _zz_165 <= (_zz_165 + 32'h00000001); end - if(_zz_285)begin + if(_zz_283)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5401,20 +5372,20 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_255)begin - if(_zz_277)begin + if(_zz_253)begin + if(_zz_275)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_371[31:0]; + memory_DivPlugin_div_result <= _zz_368[31:0]; end end end - if(_zz_278)begin + if(_zz_276)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_377); - memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_379); - memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_173 ? (~ _zz_174) : _zz_174) + _zz_374); + memory_DivPlugin_rs2 <= ((_zz_172 ? (~ execute_RS2) : execute_RS2) + _zz_376); + memory_DivPlugin_div_needRevert <= ((_zz_173 ^ (_zz_172 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5528,9 +5499,6 @@ module VexRiscv_inner ( if((! execute_arbitration_isStuck))begin decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENCODING <= decode_CfuPlugin_CFU_ENCODING; - end if((! execute_arbitration_isStuck))begin decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; end @@ -5731,7 +5699,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_382[0]; + CsrPlugin_mip_MSIP <= _zz_379[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5752,7 +5720,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_386[0]; + CsrPlugin_mcause_interrupt <= _zz_383[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5783,82 +5751,82 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_2820)begin if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2821)begin if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2822)begin if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2823)begin if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2824)begin if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2825)begin if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2826)begin if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2827)begin if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2828)begin if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2829)begin if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2830)begin if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2831)begin if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2832)begin if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2833)begin if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2834)begin if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2835)begin if(execute_CsrPlugin_writeEnable)begin - _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index f7381ba..868da11 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 767476cae91f564ec9eab25516eb1664b04c1224 +// Git hash : eafff82697ae47892bb4654e4bb7d282a4b9807c `define Input2Kind_defaultEncoding_type [0:0] @@ -95,6 +95,7 @@ module VexRiscv_inner ( input reset, input debugReset ); + wire _zz_220; wire _zz_221; wire _zz_222; wire _zz_223; @@ -102,16 +103,16 @@ module VexRiscv_inner ( wire _zz_225; wire _zz_226; wire _zz_227; - wire _zz_228; - reg _zz_229; - wire _zz_230; - wire [31:0] _zz_231; - wire _zz_232; - wire [31:0] _zz_233; - reg _zz_234; + reg _zz_228; + wire _zz_229; + wire [31:0] _zz_230; + wire _zz_231; + wire [31:0] _zz_232; + reg _zz_233; + wire _zz_234; wire _zz_235; - wire _zz_236; - wire [31:0] _zz_237; + wire [31:0] _zz_236; + wire _zz_237; wire _zz_238; wire _zz_239; wire _zz_240; @@ -119,14 +120,12 @@ module VexRiscv_inner ( wire _zz_242; wire _zz_243; wire _zz_244; - wire _zz_245; - wire [3:0] _zz_246; + wire [3:0] _zz_245; + wire _zz_246; wire _zz_247; - wire _zz_248; + reg [31:0] _zz_248; reg [31:0] _zz_249; reg [31:0] _zz_250; - reg [31:0] _zz_251; - reg [9:0] _zz_252; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -159,6 +158,8 @@ module VexRiscv_inner ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_251; + wire _zz_252; wire _zz_253; wire _zz_254; wire _zz_255; @@ -175,9 +176,9 @@ module VexRiscv_inner ( wire _zz_266; wire _zz_267; wire _zz_268; - wire _zz_269; + wire [1:0] _zz_269; wire _zz_270; - wire [1:0] _zz_271; + wire _zz_271; wire _zz_272; wire _zz_273; wire _zz_274; @@ -186,34 +187,34 @@ module VexRiscv_inner ( wire _zz_277; wire _zz_278; wire _zz_279; - wire _zz_280; + wire [1:0] _zz_280; wire _zz_281; - wire [1:0] _zz_282; - wire _zz_283; + wire _zz_282; + wire [5:0] _zz_283; wire _zz_284; - wire [5:0] _zz_285; + wire _zz_285; wire _zz_286; wire _zz_287; wire _zz_288; wire _zz_289; wire _zz_290; - wire _zz_291; + wire [1:0] _zz_291; wire _zz_292; wire [1:0] _zz_293; - wire _zz_294; - wire [1:0] _zz_295; + wire [51:0] _zz_294; + wire [51:0] _zz_295; wire [51:0] _zz_296; - wire [51:0] _zz_297; + wire [32:0] _zz_297; wire [51:0] _zz_298; - wire [32:0] _zz_299; + wire [49:0] _zz_299; wire [51:0] _zz_300; wire [49:0] _zz_301; wire [51:0] _zz_302; - wire [49:0] _zz_303; - wire [51:0] _zz_304; + wire [32:0] _zz_303; + wire [31:0] _zz_304; wire [32:0] _zz_305; - wire [31:0] _zz_306; - wire [32:0] _zz_307; + wire [0:0] _zz_306; + wire [0:0] _zz_307; wire [0:0] _zz_308; wire [0:0] _zz_309; wire [0:0] _zz_310; @@ -231,135 +232,135 @@ module VexRiscv_inner ( wire [0:0] _zz_322; wire [0:0] _zz_323; wire [0:0] _zz_324; - wire [0:0] _zz_325; - wire [0:0] _zz_326; - wire [3:0] _zz_327; - wire [2:0] _zz_328; + wire [3:0] _zz_325; + wire [2:0] _zz_326; + wire [31:0] _zz_327; + wire [11:0] _zz_328; wire [31:0] _zz_329; - wire [11:0] _zz_330; - wire [31:0] _zz_331; - wire [19:0] _zz_332; - wire [11:0] _zz_333; - wire [31:0] _zz_334; - wire [31:0] _zz_335; - wire [19:0] _zz_336; - wire [11:0] _zz_337; - wire [2:0] _zz_338; + wire [19:0] _zz_330; + wire [11:0] _zz_331; + wire [31:0] _zz_332; + wire [31:0] _zz_333; + wire [19:0] _zz_334; + wire [11:0] _zz_335; + wire [2:0] _zz_336; + wire [2:0] _zz_337; + wire [0:0] _zz_338; wire [2:0] _zz_339; - wire [0:0] _zz_340; - wire [2:0] _zz_341; - wire [4:0] _zz_342; - wire [11:0] _zz_343; - wire [11:0] _zz_344; + wire [4:0] _zz_340; + wire [11:0] _zz_341; + wire [11:0] _zz_342; + wire [31:0] _zz_343; + wire [31:0] _zz_344; wire [31:0] _zz_345; wire [31:0] _zz_346; wire [31:0] _zz_347; wire [31:0] _zz_348; wire [31:0] _zz_349; - wire [31:0] _zz_350; - wire [31:0] _zz_351; + wire [11:0] _zz_350; + wire [19:0] _zz_351; wire [11:0] _zz_352; - wire [19:0] _zz_353; - wire [11:0] _zz_354; + wire [31:0] _zz_353; + wire [31:0] _zz_354; wire [31:0] _zz_355; - wire [31:0] _zz_356; - wire [31:0] _zz_357; + wire [11:0] _zz_356; + wire [19:0] _zz_357; wire [11:0] _zz_358; - wire [19:0] _zz_359; - wire [11:0] _zz_360; - wire [2:0] _zz_361; + wire [2:0] _zz_359; + wire [1:0] _zz_360; + wire [1:0] _zz_361; wire [1:0] _zz_362; wire [1:0] _zz_363; - wire [1:0] _zz_364; - wire [1:0] _zz_365; - wire [9:0] _zz_366; - wire [3:0] _zz_367; - wire [7:0] _zz_368; - wire [65:0] _zz_369; - wire [65:0] _zz_370; - wire [31:0] _zz_371; - wire [31:0] _zz_372; - wire [0:0] _zz_373; - wire [5:0] _zz_374; + wire [9:0] _zz_364; + wire [7:0] _zz_365; + wire [65:0] _zz_366; + wire [65:0] _zz_367; + wire [31:0] _zz_368; + wire [31:0] _zz_369; + wire [0:0] _zz_370; + wire [5:0] _zz_371; + wire [32:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; wire [32:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; + wire [32:0] _zz_376; + wire [32:0] _zz_377; wire [32:0] _zz_378; - wire [32:0] _zz_379; + wire [0:0] _zz_379; wire [32:0] _zz_380; - wire [32:0] _zz_381; - wire [0:0] _zz_382; - wire [32:0] _zz_383; - wire [0:0] _zz_384; - wire [32:0] _zz_385; + wire [0:0] _zz_381; + wire [32:0] _zz_382; + wire [0:0] _zz_383; + wire [31:0] _zz_384; + wire [0:0] _zz_385; wire [0:0] _zz_386; - wire [31:0] _zz_387; + wire [0:0] _zz_387; wire [0:0] _zz_388; wire [0:0] _zz_389; wire [0:0] _zz_390; wire [0:0] _zz_391; - wire [0:0] _zz_392; - wire [0:0] _zz_393; - wire [0:0] _zz_394; - wire [26:0] _zz_395; - wire _zz_396; - wire _zz_397; - wire [1:0] _zz_398; - wire [31:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire _zz_402; - wire [0:0] _zz_403; - wire [15:0] _zz_404; - wire [31:0] _zz_405; - wire [31:0] _zz_406; - wire [31:0] _zz_407; - wire _zz_408; - wire [0:0] _zz_409; - wire [9:0] _zz_410; - wire [31:0] _zz_411; - wire [31:0] _zz_412; - wire [31:0] _zz_413; + wire [26:0] _zz_392; + wire _zz_393; + wire _zz_394; + wire [1:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire _zz_399; + wire [0:0] _zz_400; + wire [14:0] _zz_401; + wire [31:0] _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire _zz_405; + wire [0:0] _zz_406; + wire [8:0] _zz_407; + wire [31:0] _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire _zz_411; + wire [0:0] _zz_412; + wire [2:0] _zz_413; wire _zz_414; - wire [0:0] _zz_415; - wire [3:0] _zz_416; - wire _zz_417; - wire _zz_418; - wire _zz_419; - wire [31:0] _zz_420; + wire _zz_415; + wire _zz_416; + wire [31:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire _zz_420; wire [0:0] _zz_421; - wire [0:0] _zz_422; - wire _zz_423; + wire [28:0] _zz_422; + wire [0:0] _zz_423; wire [0:0] _zz_424; - wire [29:0] _zz_425; - wire [1:0] _zz_426; - wire [1:0] _zz_427; - wire _zz_428; - wire [0:0] _zz_429; - wire [24:0] _zz_430; + wire [0:0] _zz_425; + wire [0:0] _zz_426; + wire _zz_427; + wire [0:0] _zz_428; + wire [23:0] _zz_429; + wire [31:0] _zz_430; wire [31:0] _zz_431; wire [31:0] _zz_432; - wire [31:0] _zz_433; + wire _zz_433; wire _zz_434; - wire _zz_435; + wire [0:0] _zz_435; wire [0:0] _zz_436; wire [0:0] _zz_437; wire [0:0] _zz_438; - wire [0:0] _zz_439; - wire _zz_440; - wire [0:0] _zz_441; - wire [20:0] _zz_442; + wire _zz_439; + wire [0:0] _zz_440; + wire [20:0] _zz_441; + wire [31:0] _zz_442; wire [31:0] _zz_443; - wire [31:0] _zz_444; + wire _zz_444; wire _zz_445; - wire _zz_446; - wire [0:0] _zz_447; - wire [1:0] _zz_448; + wire [0:0] _zz_446; + wire [1:0] _zz_447; + wire [0:0] _zz_448; wire [0:0] _zz_449; - wire [0:0] _zz_450; - wire _zz_451; - wire [0:0] _zz_452; - wire [17:0] _zz_453; + wire _zz_450; + wire [0:0] _zz_451; + wire [17:0] _zz_452; + wire [31:0] _zz_453; wire [31:0] _zz_454; wire [31:0] _zz_455; wire [31:0] _zz_456; @@ -367,36 +368,36 @@ module VexRiscv_inner ( wire [31:0] _zz_458; wire [31:0] _zz_459; wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire _zz_462; + wire _zz_461; + wire [1:0] _zz_462; wire [1:0] _zz_463; - wire [1:0] _zz_464; - wire _zz_465; - wire [0:0] _zz_466; - wire [14:0] _zz_467; + wire _zz_464; + wire [0:0] _zz_465; + wire [14:0] _zz_466; + wire [31:0] _zz_467; wire [31:0] _zz_468; wire [31:0] _zz_469; wire [31:0] _zz_470; wire [31:0] _zz_471; wire [31:0] _zz_472; - wire [31:0] _zz_473; - wire [0:0] _zz_474; - wire [1:0] _zz_475; + wire [0:0] _zz_473; + wire [1:0] _zz_474; + wire [4:0] _zz_475; wire [4:0] _zz_476; - wire [4:0] _zz_477; - wire _zz_478; - wire [0:0] _zz_479; - wire [11:0] _zz_480; + wire _zz_477; + wire [0:0] _zz_478; + wire [11:0] _zz_479; + wire [31:0] _zz_480; wire [31:0] _zz_481; wire [31:0] _zz_482; wire [31:0] _zz_483; wire [31:0] _zz_484; wire [31:0] _zz_485; - wire [31:0] _zz_486; - wire [31:0] _zz_487; - wire _zz_488; - wire [0:0] _zz_489; - wire [1:0] _zz_490; + wire _zz_486; + wire [0:0] _zz_487; + wire [1:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; wire [0:0] _zz_491; wire [4:0] _zz_492; wire [4:0] _zz_493; @@ -417,7 +418,7 @@ module VexRiscv_inner ( wire [0:0] _zz_508; wire [2:0] _zz_509; wire [0:0] _zz_510; - wire [5:0] _zz_511; + wire [4:0] _zz_511; wire [1:0] _zz_512; wire [1:0] _zz_513; wire _zz_514; @@ -436,7 +437,7 @@ module VexRiscv_inner ( wire [0:0] _zz_527; wire _zz_528; wire [0:0] _zz_529; - wire [3:0] _zz_530; + wire [2:0] _zz_530; wire _zz_531; wire [0:0] _zz_532; wire [0:0] _zz_533; @@ -460,7 +461,7 @@ module VexRiscv_inner ( wire [31:0] _zz_551; wire _zz_552; wire [0:0] _zz_553; - wire [1:0] _zz_554; + wire [0:0] _zz_554; wire [31:0] _zz_555; wire [31:0] _zz_556; wire [31:0] _zz_557; @@ -473,45 +474,37 @@ module VexRiscv_inner ( wire [0:0] _zz_564; wire [2:0] _zz_565; wire [31:0] _zz_566; - wire _zz_567; - wire _zz_568; + wire [31:0] _zz_567; + wire [31:0] _zz_568; wire [31:0] _zz_569; - wire _zz_570; - wire [0:0] _zz_571; - wire [1:0] _zz_572; - wire _zz_573; - wire [2:0] _zz_574; - wire [2:0] _zz_575; - wire _zz_576; - wire [0:0] _zz_577; - wire [0:0] _zz_578; - wire [31:0] _zz_579; - wire [31:0] _zz_580; + wire [31:0] _zz_570; + wire [31:0] _zz_571; + wire _zz_572; + wire [0:0] _zz_573; + wire [1:0] _zz_574; + wire _zz_575; + wire [2:0] _zz_576; + wire [2:0] _zz_577; + wire _zz_578; + wire [0:0] _zz_579; + wire [0:0] _zz_580; wire [31:0] _zz_581; wire [31:0] _zz_582; wire [31:0] _zz_583; - wire _zz_584; - wire _zz_585; + wire [31:0] _zz_584; + wire [31:0] _zz_585; wire [31:0] _zz_586; - wire _zz_587; - wire [0:0] _zz_588; - wire [0:0] _zz_589; - wire [0:0] _zz_590; + wire [31:0] _zz_587; + wire _zz_588; + wire _zz_589; + wire _zz_590; wire [0:0] _zz_591; - wire [1:0] _zz_592; - wire [1:0] _zz_593; - wire [0:0] _zz_594; - wire [0:0] _zz_595; - wire [31:0] _zz_596; + wire [0:0] _zz_592; + wire _zz_593; + wire _zz_594; + wire _zz_595; + wire _zz_596; wire [31:0] _zz_597; - wire [31:0] _zz_598; - wire [31:0] _zz_599; - wire [31:0] _zz_600; - wire [31:0] _zz_601; - wire _zz_602; - wire _zz_603; - wire _zz_604; - wire [31:0] _zz_605; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -539,7 +532,6 @@ module VexRiscv_inner ( wire `Input2Kind_defaultEncoding_type _zz_1; wire `Input2Kind_defaultEncoding_type _zz_2; wire `Input2Kind_defaultEncoding_type _zz_3; - wire [0:0] decode_CfuPlugin_CFU_ENCODING; wire decode_CfuPlugin_CFU_ENABLE; wire `EnvCtrlEnum_defaultEncoding_type _zz_4; wire `EnvCtrlEnum_defaultEncoding_type _zz_5; @@ -604,7 +596,6 @@ module VexRiscv_inner ( wire memory_CfuPlugin_CFU_IN_FLIGHT; wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; wire `Input2Kind_defaultEncoding_type _zz_32; - wire [0:0] execute_CfuPlugin_CFU_ENCODING; wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; @@ -977,21 +968,20 @@ module VexRiscv_inner ( wire _zz_92; reg [31:0] _zz_93; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [35:0] _zz_94; + wire [34:0] _zz_94; wire _zz_95; wire _zz_96; wire _zz_97; wire _zz_98; wire _zz_99; - wire _zz_100; - wire `Src1CtrlEnum_defaultEncoding_type _zz_101; - wire `AluCtrlEnum_defaultEncoding_type _zz_102; - wire `Src2CtrlEnum_defaultEncoding_type _zz_103; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_104; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_105; - wire `BranchCtrlEnum_defaultEncoding_type _zz_106; - wire `EnvCtrlEnum_defaultEncoding_type _zz_107; - wire `Input2Kind_defaultEncoding_type _zz_108; + wire `Src1CtrlEnum_defaultEncoding_type _zz_100; + wire `AluCtrlEnum_defaultEncoding_type _zz_101; + wire `Src2CtrlEnum_defaultEncoding_type _zz_102; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; + wire `BranchCtrlEnum_defaultEncoding_type _zz_105; + wire `EnvCtrlEnum_defaultEncoding_type _zz_106; + wire `Input2Kind_defaultEncoding_type _zz_107; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -999,52 +989,52 @@ module VexRiscv_inner ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_109; + reg _zz_108; reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_109; reg [31:0] _zz_110; - reg [31:0] _zz_111; - wire _zz_112; - reg [19:0] _zz_113; - wire _zz_114; - reg [19:0] _zz_115; - reg [31:0] _zz_116; + wire _zz_111; + reg [19:0] _zz_112; + wire _zz_113; + reg [19:0] _zz_114; + reg [31:0] _zz_115; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_117; + reg [31:0] _zz_116; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_118; + reg [31:0] _zz_117; + reg _zz_118; reg _zz_119; reg _zz_120; - reg _zz_121; - reg [4:0] _zz_122; - reg [31:0] _zz_123; + reg [4:0] _zz_121; + reg [31:0] _zz_122; + wire _zz_123; wire _zz_124; wire _zz_125; wire _zz_126; wire _zz_127; wire _zz_128; - wire _zz_129; wire execute_BranchPlugin_eq; - wire [2:0] _zz_130; + wire [2:0] _zz_129; + reg _zz_130; reg _zz_131; - reg _zz_132; - wire _zz_133; - reg [19:0] _zz_134; - wire _zz_135; - reg [10:0] _zz_136; - wire _zz_137; - reg [18:0] _zz_138; - reg _zz_139; + wire _zz_132; + reg [19:0] _zz_133; + wire _zz_134; + reg [10:0] _zz_135; + wire _zz_136; + reg [18:0] _zz_137; + reg _zz_138; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_140; - reg [19:0] _zz_141; - wire _zz_142; - reg [10:0] _zz_143; - wire _zz_144; - reg [18:0] _zz_145; + wire _zz_139; + reg [19:0] _zz_140; + wire _zz_141; + reg [10:0] _zz_142; + wire _zz_143; + reg [18:0] _zz_144; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1066,9 +1056,9 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_145; wire _zz_146; wire _zz_147; - wire _zz_148; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1081,10 +1071,10 @@ module VexRiscv_inner ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_149; - wire _zz_150; - wire [1:0] _zz_151; - wire _zz_152; + wire [1:0] _zz_148; + wire _zz_149; + wire [1:0] _zz_150; + wire _zz_151; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1113,6 +1103,7 @@ module VexRiscv_inner ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_152; reg [31:0] _zz_153; reg [31:0] _zz_154; reg [31:0] _zz_155; @@ -1128,15 +1119,13 @@ module VexRiscv_inner ( reg [31:0] _zz_165; reg [31:0] _zz_166; reg [31:0] _zz_167; - reg [31:0] _zz_168; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire [9:0] execute_CfuPlugin_functionsIds_1; - wire _zz_169; - reg [23:0] _zz_170; - reg [31:0] _zz_171; + wire _zz_168; + reg [23:0] _zz_169; + reg [31:0] _zz_170; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1168,18 +1157,18 @@ module VexRiscv_inner ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_172; + wire [31:0] _zz_171; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_173; + wire [31:0] _zz_172; + wire _zz_173; wire _zz_174; - wire _zz_175; - reg [32:0] _zz_176; + reg [32:0] _zz_175; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_177; - wire [31:0] _zz_178; + reg [31:0] _zz_176; + wire [31:0] _zz_177; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1189,7 +1178,7 @@ module VexRiscv_inner ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_179; + reg _zz_178; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1229,7 +1218,6 @@ module VexRiscv_inner ( reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg [0:0] decode_to_execute_CfuPlugin_CFU_ENCODING; reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; reg decode_to_execute_IS_MUL; reg execute_to_memory_IS_MUL; @@ -1258,7 +1246,7 @@ module VexRiscv_inner ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_180; + reg [2:0] _zz_179; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; @@ -1299,6 +1287,7 @@ module VexRiscv_inner ( reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_180; reg [31:0] _zz_181; reg [31:0] _zz_182; reg [31:0] _zz_183; @@ -1329,17 +1318,16 @@ module VexRiscv_inner ( reg [31:0] _zz_208; reg [31:0] _zz_209; reg [31:0] _zz_210; - reg [31:0] _zz_211; - reg [2:0] _zz_212; - reg _zz_213; + reg [2:0] _zz_211; + reg _zz_212; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_214; + reg [2:0] _zz_213; + wire _zz_214; wire _zz_215; wire _zz_216; wire _zz_217; wire _zz_218; - wire _zz_219; - reg _zz_220; + reg _zz_219; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; @@ -1410,14 +1398,14 @@ module VexRiscv_inner ( reg [95:0] _zz_56_string; reg [31:0] decode_BRANCH_CTRL_string; reg [31:0] _zz_58_string; - reg [95:0] _zz_101_string; - reg [63:0] _zz_102_string; - reg [23:0] _zz_103_string; - reg [39:0] _zz_104_string; - reg [71:0] _zz_105_string; - reg [31:0] _zz_106_string; + reg [95:0] _zz_100_string; + reg [63:0] _zz_101_string; + reg [23:0] _zz_102_string; + reg [39:0] _zz_103_string; + reg [71:0] _zz_104_string; + reg [31:0] _zz_105_string; + reg [39:0] _zz_106_string; reg [39:0] _zz_107_string; - reg [39:0] _zz_108_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1433,249 +1421,251 @@ module VexRiscv_inner ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_253 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_254 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_255 = 1'b1; - assign _zz_256 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_257 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_258 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_259 = ((_zz_226 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_260 = ((_zz_226 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_261 = ((_zz_226 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_262 = ((_zz_226 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_263 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_264 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_265 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_266 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_267 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_268 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_269 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_270 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_271 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_272 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_273 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_274 = (1'b0 || (! 1'b1)); - assign _zz_275 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_276 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_277 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_278 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_279 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_280 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_281 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_282 = execute_INSTRUCTION[13 : 12]; - assign _zz_283 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_284 = (! memory_arbitration_isStuck); - assign _zz_285 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_286 = (iBus_cmd_valid || (_zz_212 != 3'b000)); - assign _zz_287 = (_zz_248 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_288 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_289 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_290 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_291 = ((_zz_148 && 1'b1) && (! 1'b0)); - assign _zz_292 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_251 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_253 = 1'b1; + assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_256 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_257 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_258 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_259 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_260 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_261 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_262 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_263 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_264 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_265 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_268 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_269 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_270 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_271 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_272 = (1'b0 || (! 1'b1)); + assign _zz_273 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_274 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_275 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_276 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_277 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_278 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_280 = execute_INSTRUCTION[13 : 12]; + assign _zz_281 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_282 = (! memory_arbitration_isStuck); + assign _zz_283 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_284 = (iBus_cmd_valid || (_zz_211 != 3'b000)); + assign _zz_285 = (_zz_247 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_286 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_287 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_288 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_289 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_290 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_291 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_292 = execute_INSTRUCTION[13]; assign _zz_293 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_294 = execute_INSTRUCTION[13]; - assign _zz_295 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_296 = ($signed(_zz_297) + $signed(_zz_302)); - assign _zz_297 = ($signed(_zz_298) + $signed(_zz_300)); - assign _zz_298 = 52'h0; - assign _zz_299 = {1'b0,memory_MUL_LL}; - assign _zz_300 = {{19{_zz_299[32]}}, _zz_299}; - assign _zz_301 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_294 = ($signed(_zz_295) + $signed(_zz_300)); + assign _zz_295 = ($signed(_zz_296) + $signed(_zz_298)); + assign _zz_296 = 52'h0; + assign _zz_297 = {1'b0,memory_MUL_LL}; + assign _zz_298 = {{19{_zz_297[32]}}, _zz_297}; + assign _zz_299 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; + assign _zz_301 = ({16'd0,memory_MUL_HL} <<< 16); assign _zz_302 = {{2{_zz_301[49]}}, _zz_301}; - assign _zz_303 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_304 = {{2{_zz_303[49]}}, _zz_303}; - assign _zz_305 = ($signed(_zz_307) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_306 = _zz_305[31 : 0]; - assign _zz_307 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_308 = _zz_94[34 : 34]; - assign _zz_309 = _zz_94[33 : 33]; - assign _zz_310 = _zz_94[32 : 32]; - assign _zz_311 = _zz_94[31 : 31]; - assign _zz_312 = _zz_94[28 : 28]; - assign _zz_313 = _zz_94[25 : 25]; - assign _zz_314 = _zz_94[17 : 17]; - assign _zz_315 = _zz_94[16 : 16]; - assign _zz_316 = _zz_94[13 : 13]; - assign _zz_317 = _zz_94[12 : 12]; - assign _zz_318 = _zz_94[11 : 11]; - assign _zz_319 = _zz_94[35 : 35]; - assign _zz_320 = _zz_94[15 : 15]; - assign _zz_321 = _zz_94[5 : 5]; - assign _zz_322 = _zz_94[3 : 3]; - assign _zz_323 = _zz_94[20 : 20]; - assign _zz_324 = _zz_94[10 : 10]; - assign _zz_325 = _zz_94[4 : 4]; - assign _zz_326 = _zz_94[0 : 0]; - assign _zz_327 = (_zz_62 - 4'b0001); - assign _zz_328 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_329 = {29'd0, _zz_328}; - assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_331 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_332 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_333 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_334 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_335 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_336 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_337 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_338 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_339 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_340 = execute_SRC_LESS; - assign _zz_341 = 3'b100; - assign _zz_342 = execute_INSTRUCTION[19 : 15]; - assign _zz_343 = execute_INSTRUCTION[31 : 20]; - assign _zz_344 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_345 = ($signed(_zz_346) + $signed(_zz_349)); - assign _zz_346 = ($signed(_zz_347) + $signed(_zz_348)); - assign _zz_347 = execute_SRC1; - assign _zz_348 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_349 = (execute_SRC_USE_SUB_LESS ? _zz_350 : _zz_351); - assign _zz_350 = 32'h00000001; - assign _zz_351 = 32'h0; - assign _zz_352 = execute_INSTRUCTION[31 : 20]; - assign _zz_353 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_354 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_355 = {_zz_134,execute_INSTRUCTION[31 : 20]}; - assign _zz_356 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_357 = {{_zz_138,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_358 = execute_INSTRUCTION[31 : 20]; - assign _zz_359 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_360 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_361 = 3'b100; - assign _zz_362 = (_zz_149 & (~ _zz_363)); - assign _zz_363 = (_zz_149 - 2'b01); - assign _zz_364 = (_zz_151 & (~ _zz_365)); - assign _zz_365 = (_zz_151 - 2'b01); - assign _zz_366 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_367 = execute_INSTRUCTION[23 : 20]; - assign _zz_368 = execute_INSTRUCTION[31 : 24]; - assign _zz_369 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_370 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_371 = writeBack_MUL_LOW[31 : 0]; - assign _zz_372 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_373 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_374 = {5'd0, _zz_373}; - assign _zz_375 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_376 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_377 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_378 = {_zz_172,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_379 = _zz_380; - assign _zz_380 = _zz_381; - assign _zz_381 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_173) : _zz_173)} + _zz_383); - assign _zz_382 = memory_DivPlugin_div_needRevert; - assign _zz_383 = {32'd0, _zz_382}; - assign _zz_384 = _zz_175; - assign _zz_385 = {32'd0, _zz_384}; - assign _zz_386 = _zz_174; - assign _zz_387 = {31'd0, _zz_386}; - assign _zz_388 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_389 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_303 = ($signed(_zz_305) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_304 = _zz_303[31 : 0]; + assign _zz_305 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_306 = _zz_94[33 : 33]; + assign _zz_307 = _zz_94[32 : 32]; + assign _zz_308 = _zz_94[31 : 31]; + assign _zz_309 = _zz_94[30 : 30]; + assign _zz_310 = _zz_94[28 : 28]; + assign _zz_311 = _zz_94[25 : 25]; + assign _zz_312 = _zz_94[17 : 17]; + assign _zz_313 = _zz_94[16 : 16]; + assign _zz_314 = _zz_94[13 : 13]; + assign _zz_315 = _zz_94[12 : 12]; + assign _zz_316 = _zz_94[11 : 11]; + assign _zz_317 = _zz_94[34 : 34]; + assign _zz_318 = _zz_94[15 : 15]; + assign _zz_319 = _zz_94[5 : 5]; + assign _zz_320 = _zz_94[3 : 3]; + assign _zz_321 = _zz_94[20 : 20]; + assign _zz_322 = _zz_94[10 : 10]; + assign _zz_323 = _zz_94[4 : 4]; + assign _zz_324 = _zz_94[0 : 0]; + assign _zz_325 = (_zz_62 - 4'b0001); + assign _zz_326 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_327 = {29'd0, _zz_326}; + assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_329 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_331 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_332 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_333 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_334 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_335 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_338 = execute_SRC_LESS; + assign _zz_339 = 3'b100; + assign _zz_340 = execute_INSTRUCTION[19 : 15]; + assign _zz_341 = execute_INSTRUCTION[31 : 20]; + assign _zz_342 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_343 = ($signed(_zz_344) + $signed(_zz_347)); + assign _zz_344 = ($signed(_zz_345) + $signed(_zz_346)); + assign _zz_345 = execute_SRC1; + assign _zz_346 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_347 = (execute_SRC_USE_SUB_LESS ? _zz_348 : _zz_349); + assign _zz_348 = 32'h00000001; + assign _zz_349 = 32'h0; + assign _zz_350 = execute_INSTRUCTION[31 : 20]; + assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_353 = {_zz_133,execute_INSTRUCTION[31 : 20]}; + assign _zz_354 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_355 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_356 = execute_INSTRUCTION[31 : 20]; + assign _zz_357 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_359 = 3'b100; + assign _zz_360 = (_zz_148 & (~ _zz_361)); + assign _zz_361 = (_zz_148 - 2'b01); + assign _zz_362 = (_zz_150 & (~ _zz_363)); + assign _zz_363 = (_zz_150 - 2'b01); + assign _zz_364 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_365 = execute_INSTRUCTION[31 : 24]; + assign _zz_366 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_367 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_368 = writeBack_MUL_LOW[31 : 0]; + assign _zz_369 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_370 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_371 = {5'd0, _zz_370}; + assign _zz_372 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_373 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_374 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_375 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_376 = _zz_377; + assign _zz_377 = _zz_378; + assign _zz_378 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_380); + assign _zz_379 = memory_DivPlugin_div_needRevert; + assign _zz_380 = {32'd0, _zz_379}; + assign _zz_381 = _zz_174; + assign _zz_382 = {32'd0, _zz_381}; + assign _zz_383 = _zz_173; + assign _zz_384 = {31'd0, _zz_383}; + assign _zz_385 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_386 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_387 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_388 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_391 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_392 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_393 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_394 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_395 = (iBus_cmd_payload_address >>> 5); - assign _zz_396 = 1'b1; - assign _zz_397 = 1'b1; - assign _zz_398 = {_zz_66,_zz_65}; - assign _zz_399 = 32'h0000106f; - assign _zz_400 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_401 = 32'h00001073; - assign _zz_402 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_403 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_404 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_405) == 32'h00000003),{(_zz_406 == _zz_407),{_zz_408,{_zz_409,_zz_410}}}}}}; - assign _zz_405 = 32'h0000207f; - assign _zz_406 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_407 = 32'h00000003; - assign _zz_408 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_409 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_410 = {((decode_INSTRUCTION & 32'h00007077) == 32'h00000023),{((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_411) == 32'h0000500f),{(_zz_412 == _zz_413),{_zz_414,{_zz_415,_zz_416}}}}}}; - assign _zz_411 = 32'h01f0707f; - assign _zz_412 = (decode_INSTRUCTION & 32'hbc00707f); - assign _zz_413 = 32'h00005013; - assign _zz_414 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); - assign _zz_415 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_416 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}}; - assign _zz_417 = decode_INSTRUCTION[31]; - assign _zz_418 = decode_INSTRUCTION[31]; - assign _zz_419 = decode_INSTRUCTION[7]; - assign _zz_420 = 32'h10103050; - assign _zz_421 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_422 = 1'b0; - assign _zz_423 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_424 = (_zz_99 != 1'b0); - assign _zz_425 = {(_zz_99 != 1'b0),{(_zz_97 != 1'b0),{(_zz_426 != _zz_427),{_zz_428,{_zz_429,_zz_430}}}}}; - assign _zz_426 = {((decode_INSTRUCTION & _zz_431) == 32'h10000050),((decode_INSTRUCTION & _zz_432) == 32'h00000050)}; - assign _zz_427 = 2'b00; - assign _zz_428 = (((decode_INSTRUCTION & _zz_433) == 32'h00000050) != 1'b0); - assign _zz_429 = ({_zz_434,_zz_435} != 2'b00); - assign _zz_430 = {({_zz_436,_zz_437} != 2'b00),{(_zz_438 != _zz_439),{_zz_440,{_zz_441,_zz_442}}}}; - assign _zz_431 = 32'h10203050; - assign _zz_432 = 32'h10103050; - assign _zz_433 = 32'h00103050; - assign _zz_434 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_435 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_436 = _zz_98; - assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000004); - assign _zz_438 = ((decode_INSTRUCTION & _zz_444) == 32'h00000040); - assign _zz_439 = 1'b0; - assign _zz_440 = ({_zz_445,_zz_446} != 2'b00); - assign _zz_441 = ({_zz_447,_zz_448} != 3'b000); - assign _zz_442 = {(_zz_449 != _zz_450),{_zz_451,{_zz_452,_zz_453}}}; - assign _zz_443 = 32'h0000001c; - assign _zz_444 = 32'h00000058; - assign _zz_445 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_446 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_447 = ((decode_INSTRUCTION & _zz_454) == 32'h40001010); - assign _zz_448 = {(_zz_455 == _zz_456),(_zz_457 == _zz_458)}; - assign _zz_449 = ((decode_INSTRUCTION & _zz_459) == 32'h00000024); - assign _zz_450 = 1'b0; - assign _zz_451 = ((_zz_460 == _zz_461) != 1'b0); - assign _zz_452 = (_zz_462 != 1'b0); - assign _zz_453 = {(_zz_463 != _zz_464),{_zz_465,{_zz_466,_zz_467}}}; - assign _zz_454 = 32'h40003054; - assign _zz_455 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_456 = 32'h00001010; - assign _zz_457 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_458 = 32'h00001010; - assign _zz_459 = 32'h00000064; - assign _zz_460 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_461 = 32'h00001000; - assign _zz_462 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_463 = {(_zz_468 == _zz_469),(_zz_470 == _zz_471)}; - assign _zz_464 = 2'b00; - assign _zz_465 = ((_zz_472 == _zz_473) != 1'b0); - assign _zz_466 = ({_zz_474,_zz_475} != 3'b000); - assign _zz_467 = {(_zz_476 != _zz_477),{_zz_478,{_zz_479,_zz_480}}}; - assign _zz_468 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_469 = 32'h00002000; - assign _zz_470 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_471 = 32'h00001000; - assign _zz_472 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_473 = 32'h00004004; - assign _zz_474 = ((decode_INSTRUCTION & _zz_481) == 32'h00000008); - assign _zz_475 = {(_zz_482 == _zz_483),(_zz_484 == _zz_485)}; - assign _zz_476 = {(_zz_486 == _zz_487),{_zz_488,{_zz_489,_zz_490}}}; - assign _zz_477 = 5'h0; - assign _zz_478 = (_zz_99 != 1'b0); - assign _zz_479 = ({_zz_491,_zz_492} != 6'h0); - assign _zz_480 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; - assign _zz_481 = 32'h0000002c; - assign _zz_482 = (decode_INSTRUCTION & 32'h00000054); - assign _zz_483 = 32'h00000040; - assign _zz_484 = (decode_INSTRUCTION & 32'h0000006c); - assign _zz_485 = 32'h00000020; - assign _zz_486 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_487 = 32'h00002040; - assign _zz_488 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); - assign _zz_489 = (_zz_499 == _zz_500); - assign _zz_490 = {_zz_501,_zz_502}; + assign _zz_391 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_392 = (iBus_cmd_payload_address >>> 5); + assign _zz_393 = 1'b1; + assign _zz_394 = 1'b1; + assign _zz_395 = {_zz_66,_zz_65}; + assign _zz_396 = 32'h0000106f; + assign _zz_397 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_398 = 32'h00001073; + assign _zz_399 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_400 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_401 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_402) == 32'h00000003),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; + assign _zz_402 = 32'h0000207f; + assign _zz_403 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_404 = 32'h00000003; + assign _zz_405 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_406 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_407 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_408) == 32'h00005013),{(_zz_409 == _zz_410),{_zz_411,{_zz_412,_zz_413}}}}}}; + assign _zz_408 = 32'hbc00707f; + assign _zz_409 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_410 = 32'h00001013; + assign _zz_411 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_412 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_413 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_414 = decode_INSTRUCTION[31]; + assign _zz_415 = decode_INSTRUCTION[31]; + assign _zz_416 = decode_INSTRUCTION[7]; + assign _zz_417 = 32'h10103050; + assign _zz_418 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_419 = 1'b0; + assign _zz_420 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_421 = 1'b0; + assign _zz_422 = {(_zz_98 != 1'b0),{({_zz_423,_zz_424} != 2'b00),{(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}}}; + assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h10000050); + assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00000050); + assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00000050); + assign _zz_426 = 1'b0; + assign _zz_427 = ({_zz_433,_zz_434} != 2'b00); + assign _zz_428 = ({_zz_435,_zz_436} != 2'b00); + assign _zz_429 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; + assign _zz_430 = 32'h10203050; + assign _zz_431 = 32'h10103050; + assign _zz_432 = 32'h00103050; + assign _zz_433 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_434 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_435 = _zz_97; + assign _zz_436 = ((decode_INSTRUCTION & _zz_442) == 32'h00000004); + assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000040); + assign _zz_438 = 1'b0; + assign _zz_439 = ({_zz_444,_zz_445} != 2'b00); + assign _zz_440 = ({_zz_446,_zz_447} != 3'b000); + assign _zz_441 = {(_zz_448 != _zz_449),{_zz_450,{_zz_451,_zz_452}}}; + assign _zz_442 = 32'h0000001c; + assign _zz_443 = 32'h00000058; + assign _zz_444 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_445 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h40001010); + assign _zz_447 = {(_zz_454 == _zz_455),(_zz_456 == _zz_457)}; + assign _zz_448 = ((decode_INSTRUCTION & _zz_458) == 32'h00000024); + assign _zz_449 = 1'b0; + assign _zz_450 = ((_zz_459 == _zz_460) != 1'b0); + assign _zz_451 = (_zz_461 != 1'b0); + assign _zz_452 = {(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}; + assign _zz_453 = 32'h40003054; + assign _zz_454 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_455 = 32'h00001010; + assign _zz_456 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_457 = 32'h00001010; + assign _zz_458 = 32'h00000064; + assign _zz_459 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_460 = 32'h00001000; + assign _zz_461 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_462 = {(_zz_467 == _zz_468),(_zz_469 == _zz_470)}; + assign _zz_463 = 2'b00; + assign _zz_464 = ((_zz_471 == _zz_472) != 1'b0); + assign _zz_465 = ({_zz_473,_zz_474} != 3'b000); + assign _zz_466 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; + assign _zz_467 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_468 = 32'h00002000; + assign _zz_469 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_470 = 32'h00001000; + assign _zz_471 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_472 = 32'h00004004; + assign _zz_473 = _zz_98; + assign _zz_474 = {(_zz_480 == _zz_481),(_zz_482 == _zz_483)}; + assign _zz_475 = {(_zz_484 == _zz_485),{_zz_486,{_zz_487,_zz_488}}}; + assign _zz_476 = 5'h0; + assign _zz_477 = ((_zz_489 == _zz_490) != 1'b0); + assign _zz_478 = ({_zz_491,_zz_492} != 6'h0); + assign _zz_479 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; + assign _zz_480 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_481 = 32'h00000020; + assign _zz_482 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_483 = 32'h00000020; + assign _zz_484 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_485 = 32'h00002040; + assign _zz_486 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); + assign _zz_487 = (_zz_499 == _zz_500); + assign _zz_488 = {_zz_501,_zz_502}; + assign _zz_489 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_490 = 32'h00000020; assign _zz_491 = (_zz_503 == _zz_504); assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; assign _zz_493 = {_zz_96,{_zz_508,_zz_509}}; assign _zz_494 = 5'h0; - assign _zz_495 = ({_zz_510,_zz_511} != 7'h0); + assign _zz_495 = ({_zz_510,_zz_511} != 6'h0); assign _zz_496 = (_zz_512 != _zz_513); assign _zz_497 = {_zz_514,{_zz_515,_zz_516}}; assign _zz_498 = 32'h00001040; @@ -1690,7 +1680,7 @@ module VexRiscv_inner ( assign _zz_507 = {_zz_520,{_zz_521,_zz_522}}; assign _zz_508 = (_zz_523 == _zz_524); assign _zz_509 = {_zz_525,{_zz_526,_zz_527}}; - assign _zz_510 = _zz_98; + assign _zz_510 = _zz_97; assign _zz_511 = {_zz_528,{_zz_529,_zz_530}}; assign _zz_512 = {_zz_96,_zz_531}; assign _zz_513 = 2'b00; @@ -1727,74 +1717,66 @@ module VexRiscv_inner ( assign _zz_544 = 32'h00001030; assign _zz_545 = (decode_INSTRUCTION & 32'h02002060); assign _zz_546 = 32'h00002020; - assign _zz_547 = (decode_INSTRUCTION & 32'h02003028); + assign _zz_547 = (decode_INSTRUCTION & 32'h02003020); assign _zz_548 = 32'h00000020; assign _zz_549 = 32'h00001010; assign _zz_550 = (decode_INSTRUCTION & 32'h00002010); assign _zz_551 = 32'h00002010; assign _zz_552 = ((decode_INSTRUCTION & _zz_566) == 32'h00000010); - assign _zz_553 = _zz_97; - assign _zz_554 = {_zz_567,_zz_568}; + assign _zz_553 = (_zz_567 == _zz_568); + assign _zz_554 = (_zz_569 == _zz_570); assign _zz_555 = 32'h00000070; assign _zz_556 = (decode_INSTRUCTION & 32'h00000020); assign _zz_557 = 32'h0; assign _zz_558 = (decode_INSTRUCTION & 32'h00004014); assign _zz_559 = 32'h00004010; - assign _zz_560 = ((decode_INSTRUCTION & _zz_569) == 32'h00002010); - assign _zz_561 = {_zz_570,{_zz_571,_zz_572}}; + assign _zz_560 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); + assign _zz_561 = {_zz_572,{_zz_573,_zz_574}}; assign _zz_562 = 4'b0000; - assign _zz_563 = (_zz_573 != 1'b0); - assign _zz_564 = (_zz_574 != _zz_575); - assign _zz_565 = {_zz_576,{_zz_577,_zz_578}}; + assign _zz_563 = (_zz_575 != 1'b0); + assign _zz_564 = (_zz_576 != _zz_577); + assign _zz_565 = {_zz_578,{_zz_579,_zz_580}}; assign _zz_566 = 32'h00000050; - assign _zz_567 = ((decode_INSTRUCTION & _zz_579) == 32'h00000004); - assign _zz_568 = ((decode_INSTRUCTION & _zz_580) == 32'h0); - assign _zz_569 = 32'h00006014; - assign _zz_570 = ((decode_INSTRUCTION & _zz_581) == 32'h0); - assign _zz_571 = (_zz_582 == _zz_583); - assign _zz_572 = {_zz_584,_zz_585}; - assign _zz_573 = ((decode_INSTRUCTION & _zz_586) == 32'h0); - assign _zz_574 = {_zz_587,{_zz_588,_zz_589}}; - assign _zz_575 = 3'b000; - assign _zz_576 = ({_zz_590,_zz_591} != 2'b00); - assign _zz_577 = (_zz_592 != _zz_593); - assign _zz_578 = (_zz_594 != _zz_595); - assign _zz_579 = 32'h0000000c; - assign _zz_580 = 32'h00000028; - assign _zz_581 = 32'h00000044; - assign _zz_582 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_583 = 32'h0; - assign _zz_584 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_585 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_586 = 32'h00000058; - assign _zz_587 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_588 = ((decode_INSTRUCTION & _zz_596) == 32'h00002010); - assign _zz_589 = ((decode_INSTRUCTION & _zz_597) == 32'h40000030); - assign _zz_590 = ((decode_INSTRUCTION & _zz_598) == 32'h00000004); - assign _zz_591 = _zz_95; - assign _zz_592 = {(_zz_599 == _zz_600),_zz_95}; - assign _zz_593 = 2'b00; - assign _zz_594 = ((decode_INSTRUCTION & _zz_601) == 32'h00001004); - assign _zz_595 = 1'b0; - assign _zz_596 = 32'h00002014; - assign _zz_597 = 32'h40000034; - assign _zz_598 = 32'h00000014; - assign _zz_599 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_600 = 32'h00000004; - assign _zz_601 = 32'h00005054; - assign _zz_602 = execute_INSTRUCTION[31]; - assign _zz_603 = execute_INSTRUCTION[31]; - assign _zz_604 = execute_INSTRUCTION[7]; - assign _zz_605 = 32'h0; + assign _zz_567 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_568 = 32'h00000004; + assign _zz_569 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_570 = 32'h0; + assign _zz_571 = 32'h00006014; + assign _zz_572 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_573 = ((decode_INSTRUCTION & _zz_581) == 32'h0); + assign _zz_574 = {(_zz_582 == _zz_583),(_zz_584 == _zz_585)}; + assign _zz_575 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_576 = {(_zz_586 == _zz_587),{_zz_588,_zz_589}}; + assign _zz_577 = 3'b000; + assign _zz_578 = ({_zz_590,_zz_95} != 2'b00); + assign _zz_579 = ({_zz_591,_zz_592} != 2'b00); + assign _zz_580 = (_zz_593 != 1'b0); + assign _zz_581 = 32'h00000018; + assign _zz_582 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_583 = 32'h00002000; + assign _zz_584 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_585 = 32'h00001000; + assign _zz_586 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_587 = 32'h00000040; + assign _zz_588 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_589 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_590 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_591 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_592 = _zz_95; + assign _zz_593 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_594 = execute_INSTRUCTION[31]; + assign _zz_595 = execute_INSTRUCTION[31]; + assign _zz_596 = execute_INSTRUCTION[7]; + assign _zz_597 = 32'h0; always @ (posedge clk) begin - if(_zz_396) begin - _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_393) begin + _zz_248 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_397) begin - _zz_250 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_394) begin + _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1805,13 +1787,13 @@ module VexRiscv_inner ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_221 ), //i - .io_cpu_prefetch_isValid (_zz_222 ), //i + .io_flush (_zz_220 ), //i + .io_cpu_prefetch_isValid (_zz_221 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_223 ), //i - .io_cpu_fetch_isStuck (_zz_224 ), //i - .io_cpu_fetch_isRemoved (_zz_225 ), //i + .io_cpu_fetch_isValid (_zz_222 ), //i + .io_cpu_fetch_isStuck (_zz_223 ), //i + .io_cpu_fetch_isRemoved (_zz_224 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1824,8 +1806,8 @@ module VexRiscv_inner ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_226 ), //i - .io_cpu_decode_isStuck (_zz_227 ), //i + .io_cpu_decode_isValid (_zz_225 ), //i + .io_cpu_decode_isStuck (_zz_226 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1833,8 +1815,8 @@ module VexRiscv_inner ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_228 ), //i - .io_cpu_fill_valid (_zz_229 ), //i + .io_cpu_decode_isUser (_zz_227 ), //i + .io_cpu_fill_valid (_zz_228 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1843,26 +1825,26 @@ module VexRiscv_inner ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_16 (_zz_180[2:0] ), //i + ._zz_16 (_zz_179[2:0] ), //i ._zz_17 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_230 ), //i - .io_cpu_execute_address (_zz_231[31:0] ), //i + .io_cpu_execute_isValid (_zz_229 ), //i + .io_cpu_execute_address (_zz_230[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_89[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_232 ), //i + .io_cpu_memory_isValid (_zz_231 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_233[31:0] ), //i + .io_cpu_memory_address (_zz_232[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_234 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_233 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1870,31 +1852,31 @@ module VexRiscv_inner ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_235 ), //i + .io_cpu_writeBack_isValid (_zz_234 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_236 ), //i + .io_cpu_writeBack_isUser (_zz_235 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_237[31:0] ), //i + .io_cpu_writeBack_address (_zz_236[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_238 ), //i - .io_cpu_writeBack_fence_SR (_zz_239 ), //i - .io_cpu_writeBack_fence_SO (_zz_240 ), //i - .io_cpu_writeBack_fence_SI (_zz_241 ), //i - .io_cpu_writeBack_fence_PW (_zz_242 ), //i - .io_cpu_writeBack_fence_PR (_zz_243 ), //i - .io_cpu_writeBack_fence_PO (_zz_244 ), //i - .io_cpu_writeBack_fence_PI (_zz_245 ), //i - .io_cpu_writeBack_fence_FM (_zz_246[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_237 ), //i + .io_cpu_writeBack_fence_SR (_zz_238 ), //i + .io_cpu_writeBack_fence_SO (_zz_239 ), //i + .io_cpu_writeBack_fence_SI (_zz_240 ), //i + .io_cpu_writeBack_fence_PW (_zz_241 ), //i + .io_cpu_writeBack_fence_PR (_zz_242 ), //i + .io_cpu_writeBack_fence_PO (_zz_243 ), //i + .io_cpu_writeBack_fence_PI (_zz_244 ), //i + .io_cpu_writeBack_fence_FM (_zz_245[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_247 ), //i + .io_cpu_flush_valid (_zz_246 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_248 ), //i + .io_mem_cmd_ready (_zz_247 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1910,29 +1892,18 @@ module VexRiscv_inner ( .reset (reset ) //i ); always @(*) begin - case(_zz_398) + case(_zz_395) 2'b00 : begin - _zz_251 = DBusCachedPlugin_redoBranch_payload; + _zz_250 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_251 = CsrPlugin_jumpInterface_payload; + _zz_250 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_251 = BranchPlugin_jumpInterface_payload; - end - default : begin - _zz_251 = IBusCachedPlugin_predictionJumpInterface_payload; - end - endcase - end - - always @(*) begin - case(execute_CfuPlugin_CFU_ENCODING) - 1'b0 : begin - _zz_252 = execute_CfuPlugin_functionsIds_0; + _zz_250 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_252 = execute_CfuPlugin_functionsIds_1; + _zz_250 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2522,74 +2493,74 @@ module VexRiscv_inner ( default : _zz_58_string = "????"; endcase end + always @(*) begin + case(_zz_100) + `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; + default : _zz_100_string = "????????????"; + endcase + end always @(*) begin case(_zz_101) - `Src1CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_101_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_101_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_101_string = "URS1 "; - default : _zz_101_string = "????????????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; + default : _zz_101_string = "????????"; endcase end always @(*) begin case(_zz_102) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_102_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_102_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_102_string = "BITWISE "; - default : _zz_102_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; + default : _zz_102_string = "???"; endcase end always @(*) begin case(_zz_103) - `Src2CtrlEnum_defaultEncoding_RS : _zz_103_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_103_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_103_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_103_string = "PC "; - default : _zz_103_string = "???"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; + default : _zz_103_string = "?????"; endcase end always @(*) begin case(_zz_104) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_104_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_104_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_104_string = "AND_1"; - default : _zz_104_string = "?????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; + default : _zz_104_string = "?????????"; endcase end always @(*) begin case(_zz_105) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_105_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_105_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_105_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_105_string = "SRA_1 "; - default : _zz_105_string = "?????????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; + default : _zz_105_string = "????"; endcase end always @(*) begin case(_zz_106) - `BranchCtrlEnum_defaultEncoding_INC : _zz_106_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_106_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_106_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_106_string = "JALR"; - default : _zz_106_string = "????"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; + default : _zz_106_string = "?????"; endcase end always @(*) begin case(_zz_107) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_107_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_107_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_107_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_107_string = "ECALL"; + `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; default : _zz_107_string = "?????"; endcase end - always @(*) begin - case(_zz_108) - `Input2Kind_defaultEncoding_RS : _zz_108_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_108_string = "IMM_I"; - default : _zz_108_string = "?????"; - endcase - end always @(*) begin case(decode_to_execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; @@ -2687,7 +2658,7 @@ module VexRiscv_inner ( end `endif - assign memory_MUL_LOW = ($signed(_zz_296) + $signed(_zz_304)); + assign memory_MUL_LOW = ($signed(_zz_294) + $signed(_zz_302)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2695,43 +2666,42 @@ module VexRiscv_inner ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_306; - assign execute_REGFILE_WRITE_DATA = _zz_110; + assign execute_SHIFT_RIGHT = _zz_304; + assign execute_REGFILE_WRITE_DATA = _zz_109; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_231[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_230[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_308[0]; - assign decode_IS_RS1_SIGNED = _zz_309[0]; - assign decode_IS_DIV = _zz_310[0]; + assign decode_IS_RS2_SIGNED = _zz_306[0]; + assign decode_IS_RS1_SIGNED = _zz_307[0]; + assign decode_IS_DIV = _zz_308[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_311[0]; + assign decode_IS_MUL = _zz_309[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENCODING = _zz_94[29 : 29]; - assign decode_CfuPlugin_CFU_ENABLE = _zz_312[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_310[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_313[0]; + assign decode_IS_CSR = _zz_311[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_314[0]; - assign decode_MEMORY_MANAGMENT = _zz_315[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_312[0]; + assign decode_MEMORY_MANAGMENT = _zz_313[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_316[0]; + assign decode_MEMORY_WR = _zz_314[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_317[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_318[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_315[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_316[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2745,7 +2715,7 @@ module VexRiscv_inner ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_319[0]; + assign decode_IS_EBREAK = _zz_317[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2772,7 +2742,6 @@ module VexRiscv_inner ( assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENCODING = decode_to_execute_CfuPlugin_CFU_ENCODING; assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; @@ -2785,13 +2754,13 @@ module VexRiscv_inner ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_132; + assign execute_BRANCH_COND_RESULT = _zz_131; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_320[0]; - assign decode_RS1_USE = _zz_321[0]; + assign decode_RS2_USE = _zz_318[0]; + assign decode_RS1_USE = _zz_319[0]; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_253)begin + if(_zz_251)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2804,28 +2773,28 @@ module VexRiscv_inner ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_121)begin - if((_zz_122 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_123; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_122; end end - if(_zz_254)begin - if(_zz_255)begin - if(_zz_125)begin + if(_zz_252)begin + if(_zz_253)begin + if(_zz_124)begin decode_RS2 = _zz_57; end end end - if(_zz_256)begin + if(_zz_254)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_127)begin + if(_zz_126)begin decode_RS2 = _zz_38; end end end - if(_zz_257)begin + if(_zz_255)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_129)begin + if(_zz_128)begin decode_RS2 = _zz_37; end end @@ -2834,28 +2803,28 @@ module VexRiscv_inner ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_121)begin - if((_zz_122 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_123; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_122; end end - if(_zz_254)begin - if(_zz_255)begin - if(_zz_124)begin + if(_zz_252)begin + if(_zz_253)begin + if(_zz_123)begin decode_RS1 = _zz_57; end end end - if(_zz_256)begin + if(_zz_254)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_126)begin + if(_zz_125)begin decode_RS1 = _zz_38; end end end - if(_zz_257)begin + if(_zz_255)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_128)begin + if(_zz_127)begin decode_RS1 = _zz_37; end end @@ -2868,7 +2837,7 @@ module VexRiscv_inner ( if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_118; + _zz_38 = _zz_117; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin _zz_38 = memory_SHIFT_RIGHT; @@ -2880,7 +2849,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_258)begin + if(_zz_256)begin _zz_38 = memory_DivPlugin_div_result; end end @@ -2893,13 +2862,13 @@ module VexRiscv_inner ( assign _zz_41 = execute_PC; assign execute_SRC2_CTRL = _zz_42; assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_322[0]; - assign decode_SRC_ADD_ZERO = _zz_323[0]; + assign decode_SRC_USE_SUB_LESS = _zz_320[0]; + assign decode_SRC_ADD_ZERO = _zz_321[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_116; - assign execute_SRC1 = _zz_111; + assign execute_SRC2 = _zz_115; + assign execute_SRC1 = _zz_110; assign execute_ALU_BITWISE_CTRL = _zz_45; assign _zz_46 = writeBack_INSTRUCTION; assign _zz_47 = writeBack_REGFILE_WRITE_VALID; @@ -2912,25 +2881,25 @@ module VexRiscv_inner ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_324[0]; + decode_REGFILE_WRITE_VALID = _zz_322[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_399) == 32'h00000003),{(_zz_400 == _zz_401),{_zz_402,{_zz_403,_zz_404}}}}}}} != 23'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}} != 22'h0); always @ (*) begin _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_295) + case(_zz_293) 2'b00 : begin - _zz_57 = _zz_371; + _zz_57 = _zz_368; end default : begin - _zz_57 = _zz_372; + _zz_57 = _zz_369; end endcase end @@ -2949,32 +2918,32 @@ module VexRiscv_inner ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_325[0]; - assign decode_FLUSH_ALL = _zz_326[0]; + assign decode_MEMORY_ENABLE = _zz_323[0]; + assign decode_FLUSH_ALL = _zz_324[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_259)begin + if(_zz_257)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_260)begin + if(_zz_258)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_261)begin + if(_zz_259)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_262)begin + if(_zz_260)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -3003,7 +2972,7 @@ module VexRiscv_inner ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_180) + case(_zz_179) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -3014,7 +2983,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_119 || _zz_120)))begin + if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -3027,7 +2996,7 @@ module VexRiscv_inner ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_263)begin + if(_zz_261)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3041,22 +3010,22 @@ module VexRiscv_inner ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_263)begin + if(_zz_261)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_247 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_246 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_264)begin + if(_zz_262)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_253)begin + if(_zz_251)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3071,14 +3040,14 @@ module VexRiscv_inner ( if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_265)begin + if(_zz_263)begin execute_arbitration_haltByOther = 1'b1; end end always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_266)begin + if(_zz_264)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -3088,8 +3057,8 @@ module VexRiscv_inner ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_265)begin - if(_zz_267)begin + if(_zz_263)begin + if(_zz_265)begin execute_arbitration_flushIt = 1'b1; end end @@ -3100,11 +3069,11 @@ module VexRiscv_inner ( if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_266)begin + if(_zz_264)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_265)begin - if(_zz_267)begin + if(_zz_263)begin + if(_zz_265)begin execute_arbitration_flushNext = 1'b1; end end @@ -3117,7 +3086,7 @@ module VexRiscv_inner ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_258)begin + if(_zz_256)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3176,10 +3145,10 @@ module VexRiscv_inner ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_268)begin + if(_zz_266)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_269)begin + if(_zz_267)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3193,21 +3162,21 @@ module VexRiscv_inner ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_268)begin + if(_zz_266)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_269)begin + if(_zz_267)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_265)begin - if(_zz_267)begin + if(_zz_263)begin + if(_zz_265)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_270)begin + if(_zz_268)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3228,7 +3197,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_264)begin + if(_zz_262)begin CsrPlugin_inWfi = 1'b1; end end @@ -3242,21 +3211,21 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_268)begin + if(_zz_266)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_269)begin + if(_zz_267)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_268)begin + if(_zz_266)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_269)begin - case(_zz_271) + if(_zz_267)begin + case(_zz_269) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3290,11 +3259,11 @@ module VexRiscv_inner ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_63 = (_zz_62 & (~ _zz_327)); + assign _zz_63 = (_zz_62 & (~ _zz_325)); assign _zz_64 = _zz_63[3]; assign _zz_65 = (_zz_63[1] || _zz_64); assign _zz_66 = (_zz_63[2] || _zz_64); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_251; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_250; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3314,7 +3283,7 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_329); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_327); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3406,7 +3375,7 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_180) + case(_zz_179) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3418,7 +3387,7 @@ module VexRiscv_inner ( endcase end - assign _zz_76 = _zz_330[11]; + assign _zz_76 = _zz_328[11]; always @ (*) begin _zz_77[18] = _zz_76; _zz_77[17] = _zz_76; @@ -3442,13 +3411,13 @@ module VexRiscv_inner ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_331[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_329[31])); if(_zz_82)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_78 = _zz_332[19]; + assign _zz_78 = _zz_330[19]; always @ (*) begin _zz_79[10] = _zz_78; _zz_79[9] = _zz_78; @@ -3463,7 +3432,7 @@ module VexRiscv_inner ( _zz_79[0] = _zz_78; end - assign _zz_80 = _zz_333[11]; + assign _zz_80 = _zz_331[11]; always @ (*) begin _zz_81[18] = _zz_80; _zz_81[17] = _zz_80; @@ -3489,16 +3458,16 @@ module VexRiscv_inner ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_82 = _zz_334[1]; + _zz_82 = _zz_332[1]; end default : begin - _zz_82 = _zz_335[1]; + _zz_82 = _zz_333[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_83 = _zz_336[19]; + assign _zz_83 = _zz_334[19]; always @ (*) begin _zz_84[10] = _zz_83; _zz_84[9] = _zz_83; @@ -3513,7 +3482,7 @@ module VexRiscv_inner ( _zz_84[0] = _zz_83; end - assign _zz_85 = _zz_337[11]; + assign _zz_85 = _zz_335[11]; always @ (*) begin _zz_86[18] = _zz_85; _zz_86[17] = _zz_85; @@ -3536,7 +3505,7 @@ module VexRiscv_inner ( _zz_86[0] = _zz_85; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_417,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_418,_zz_419},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_414,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_415,_zz_416},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3545,52 +3514,52 @@ module VexRiscv_inner ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_223 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_224 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_223; + assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_222; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_226 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_227 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_228 = (CsrPlugin_privilege == 2'b00); + assign _zz_225 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_226 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_227 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_262)begin + if(_zz_260)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_260)begin + if(_zz_258)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_229 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_260)begin - _zz_229 = 1'b1; + _zz_228 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_258)begin + _zz_228 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_261)begin + if(_zz_259)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_259)begin + if(_zz_257)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_261)begin + if(_zz_259)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_259)begin + if(_zz_257)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3600,9 +3569,9 @@ module VexRiscv_inner ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_221 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_220 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_248 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_247 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3629,8 +3598,8 @@ module VexRiscv_inner ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_230 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_231 = execute_SRC_ADD; + assign _zz_229 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_230 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3645,27 +3614,27 @@ module VexRiscv_inner ( endcase end - assign _zz_247 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_232 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_233 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_232; + assign _zz_246 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_231 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_232 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_231; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_233; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_232; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_234 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_233 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_234 = 1'b1; + _zz_233 = 1'b1; end end - assign _zz_235 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_236 = (CsrPlugin_privilege == 2'b00); - assign _zz_237 = writeBack_REGFILE_WRITE_DATA; + assign _zz_234 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_235 = (CsrPlugin_privilege == 2'b00); + assign _zz_236 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_272)begin + if(_zz_270)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3675,7 +3644,7 @@ module VexRiscv_inner ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_272)begin + if(_zz_270)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3694,15 +3663,15 @@ module VexRiscv_inner ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_272)begin + if(_zz_270)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_338}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_339}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; end end end @@ -3775,7 +3744,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_293) + case(_zz_291) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_91; end @@ -3808,51 +3777,50 @@ module VexRiscv_inner ( assign DBusCachedPlugin_mmuBus_busy = 1'b0; assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); assign _zz_96 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_98 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_99 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz_100 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_94 = {(((decode_INSTRUCTION & _zz_420) == 32'h00100050) != 1'b0),{(_zz_100 != 1'b0),{(_zz_100 != 1'b0),{(_zz_421 != _zz_422),{_zz_423,{_zz_424,_zz_425}}}}}}; - assign _zz_101 = _zz_94[2 : 1]; - assign _zz_56 = _zz_101; - assign _zz_102 = _zz_94[7 : 6]; - assign _zz_55 = _zz_102; - assign _zz_103 = _zz_94[9 : 8]; - assign _zz_54 = _zz_103; - assign _zz_104 = _zz_94[19 : 18]; - assign _zz_53 = _zz_104; - assign _zz_105 = _zz_94[22 : 21]; - assign _zz_52 = _zz_105; - assign _zz_106 = _zz_94[24 : 23]; - assign _zz_51 = _zz_106; - assign _zz_107 = _zz_94[27 : 26]; - assign _zz_50 = _zz_107; - assign _zz_108 = _zz_94[30 : 30]; - assign _zz_49 = _zz_108; + assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_94 = {(((decode_INSTRUCTION & _zz_417) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}; + assign _zz_100 = _zz_94[2 : 1]; + assign _zz_56 = _zz_100; + assign _zz_101 = _zz_94[7 : 6]; + assign _zz_55 = _zz_101; + assign _zz_102 = _zz_94[9 : 8]; + assign _zz_54 = _zz_102; + assign _zz_103 = _zz_94[19 : 18]; + assign _zz_53 = _zz_103; + assign _zz_104 = _zz_94[22 : 21]; + assign _zz_52 = _zz_104; + assign _zz_105 = _zz_94[24 : 23]; + assign _zz_51 = _zz_105; + assign _zz_106 = _zz_94[27 : 26]; + assign _zz_50 = _zz_106; + assign _zz_107 = _zz_94[29 : 29]; + assign _zz_49 = _zz_107; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_249; - assign decode_RegFilePlugin_rs2Data = _zz_250; + assign decode_RegFilePlugin_rs1Data = _zz_248; + assign decode_RegFilePlugin_rs2Data = _zz_249; always @ (*) begin lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_109)begin + if(_zz_108)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_109)begin + if(_zz_108)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_109)begin + if(_zz_108)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -3874,13 +3842,13 @@ module VexRiscv_inner ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_110 = execute_IntAluPlugin_bitwise; + _zz_109 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_110 = {31'd0, _zz_340}; + _zz_109 = {31'd0, _zz_338}; end default : begin - _zz_110 = execute_SRC_ADD_SUB; + _zz_109 = execute_SRC_ADD_SUB; end endcase end @@ -3888,87 +3856,87 @@ module VexRiscv_inner ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_111 = execute_RS1; + _zz_110 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_111 = {29'd0, _zz_341}; + _zz_110 = {29'd0, _zz_339}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_111 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_111 = {27'd0, _zz_342}; + _zz_110 = {27'd0, _zz_340}; end endcase end - assign _zz_112 = _zz_343[11]; - always @ (*) begin - _zz_113[19] = _zz_112; - _zz_113[18] = _zz_112; - _zz_113[17] = _zz_112; - _zz_113[16] = _zz_112; - _zz_113[15] = _zz_112; - _zz_113[14] = _zz_112; - _zz_113[13] = _zz_112; - _zz_113[12] = _zz_112; - _zz_113[11] = _zz_112; - _zz_113[10] = _zz_112; - _zz_113[9] = _zz_112; - _zz_113[8] = _zz_112; - _zz_113[7] = _zz_112; - _zz_113[6] = _zz_112; - _zz_113[5] = _zz_112; - _zz_113[4] = _zz_112; - _zz_113[3] = _zz_112; - _zz_113[2] = _zz_112; - _zz_113[1] = _zz_112; - _zz_113[0] = _zz_112; - end - - assign _zz_114 = _zz_344[11]; - always @ (*) begin - _zz_115[19] = _zz_114; - _zz_115[18] = _zz_114; - _zz_115[17] = _zz_114; - _zz_115[16] = _zz_114; - _zz_115[15] = _zz_114; - _zz_115[14] = _zz_114; - _zz_115[13] = _zz_114; - _zz_115[12] = _zz_114; - _zz_115[11] = _zz_114; - _zz_115[10] = _zz_114; - _zz_115[9] = _zz_114; - _zz_115[8] = _zz_114; - _zz_115[7] = _zz_114; - _zz_115[6] = _zz_114; - _zz_115[5] = _zz_114; - _zz_115[4] = _zz_114; - _zz_115[3] = _zz_114; - _zz_115[2] = _zz_114; - _zz_115[1] = _zz_114; - _zz_115[0] = _zz_114; + assign _zz_111 = _zz_341[11]; + always @ (*) begin + _zz_112[19] = _zz_111; + _zz_112[18] = _zz_111; + _zz_112[17] = _zz_111; + _zz_112[16] = _zz_111; + _zz_112[15] = _zz_111; + _zz_112[14] = _zz_111; + _zz_112[13] = _zz_111; + _zz_112[12] = _zz_111; + _zz_112[11] = _zz_111; + _zz_112[10] = _zz_111; + _zz_112[9] = _zz_111; + _zz_112[8] = _zz_111; + _zz_112[7] = _zz_111; + _zz_112[6] = _zz_111; + _zz_112[5] = _zz_111; + _zz_112[4] = _zz_111; + _zz_112[3] = _zz_111; + _zz_112[2] = _zz_111; + _zz_112[1] = _zz_111; + _zz_112[0] = _zz_111; + end + + assign _zz_113 = _zz_342[11]; + always @ (*) begin + _zz_114[19] = _zz_113; + _zz_114[18] = _zz_113; + _zz_114[17] = _zz_113; + _zz_114[16] = _zz_113; + _zz_114[15] = _zz_113; + _zz_114[14] = _zz_113; + _zz_114[13] = _zz_113; + _zz_114[12] = _zz_113; + _zz_114[11] = _zz_113; + _zz_114[10] = _zz_113; + _zz_114[9] = _zz_113; + _zz_114[8] = _zz_113; + _zz_114[7] = _zz_113; + _zz_114[6] = _zz_113; + _zz_114[5] = _zz_113; + _zz_114[4] = _zz_113; + _zz_114[3] = _zz_113; + _zz_114[2] = _zz_113; + _zz_114[1] = _zz_113; + _zz_114[0] = _zz_113; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_116 = execute_RS2; + _zz_115 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_116 = {_zz_113,execute_INSTRUCTION[31 : 20]}; + _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_116 = {_zz_115,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_116 = _zz_41; + _zz_115 = _zz_41; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_345; + execute_SrcPlugin_addSub = _zz_343; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3977,246 +3945,246 @@ module VexRiscv_inner ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_117[0] = execute_SRC1[31]; - _zz_117[1] = execute_SRC1[30]; - _zz_117[2] = execute_SRC1[29]; - _zz_117[3] = execute_SRC1[28]; - _zz_117[4] = execute_SRC1[27]; - _zz_117[5] = execute_SRC1[26]; - _zz_117[6] = execute_SRC1[25]; - _zz_117[7] = execute_SRC1[24]; - _zz_117[8] = execute_SRC1[23]; - _zz_117[9] = execute_SRC1[22]; - _zz_117[10] = execute_SRC1[21]; - _zz_117[11] = execute_SRC1[20]; - _zz_117[12] = execute_SRC1[19]; - _zz_117[13] = execute_SRC1[18]; - _zz_117[14] = execute_SRC1[17]; - _zz_117[15] = execute_SRC1[16]; - _zz_117[16] = execute_SRC1[15]; - _zz_117[17] = execute_SRC1[14]; - _zz_117[18] = execute_SRC1[13]; - _zz_117[19] = execute_SRC1[12]; - _zz_117[20] = execute_SRC1[11]; - _zz_117[21] = execute_SRC1[10]; - _zz_117[22] = execute_SRC1[9]; - _zz_117[23] = execute_SRC1[8]; - _zz_117[24] = execute_SRC1[7]; - _zz_117[25] = execute_SRC1[6]; - _zz_117[26] = execute_SRC1[5]; - _zz_117[27] = execute_SRC1[4]; - _zz_117[28] = execute_SRC1[3]; - _zz_117[29] = execute_SRC1[2]; - _zz_117[30] = execute_SRC1[1]; - _zz_117[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_117 : execute_SRC1); - always @ (*) begin - _zz_118[0] = memory_SHIFT_RIGHT[31]; - _zz_118[1] = memory_SHIFT_RIGHT[30]; - _zz_118[2] = memory_SHIFT_RIGHT[29]; - _zz_118[3] = memory_SHIFT_RIGHT[28]; - _zz_118[4] = memory_SHIFT_RIGHT[27]; - _zz_118[5] = memory_SHIFT_RIGHT[26]; - _zz_118[6] = memory_SHIFT_RIGHT[25]; - _zz_118[7] = memory_SHIFT_RIGHT[24]; - _zz_118[8] = memory_SHIFT_RIGHT[23]; - _zz_118[9] = memory_SHIFT_RIGHT[22]; - _zz_118[10] = memory_SHIFT_RIGHT[21]; - _zz_118[11] = memory_SHIFT_RIGHT[20]; - _zz_118[12] = memory_SHIFT_RIGHT[19]; - _zz_118[13] = memory_SHIFT_RIGHT[18]; - _zz_118[14] = memory_SHIFT_RIGHT[17]; - _zz_118[15] = memory_SHIFT_RIGHT[16]; - _zz_118[16] = memory_SHIFT_RIGHT[15]; - _zz_118[17] = memory_SHIFT_RIGHT[14]; - _zz_118[18] = memory_SHIFT_RIGHT[13]; - _zz_118[19] = memory_SHIFT_RIGHT[12]; - _zz_118[20] = memory_SHIFT_RIGHT[11]; - _zz_118[21] = memory_SHIFT_RIGHT[10]; - _zz_118[22] = memory_SHIFT_RIGHT[9]; - _zz_118[23] = memory_SHIFT_RIGHT[8]; - _zz_118[24] = memory_SHIFT_RIGHT[7]; - _zz_118[25] = memory_SHIFT_RIGHT[6]; - _zz_118[26] = memory_SHIFT_RIGHT[5]; - _zz_118[27] = memory_SHIFT_RIGHT[4]; - _zz_118[28] = memory_SHIFT_RIGHT[3]; - _zz_118[29] = memory_SHIFT_RIGHT[2]; - _zz_118[30] = memory_SHIFT_RIGHT[1]; - _zz_118[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_119 = 1'b0; + _zz_116[0] = execute_SRC1[31]; + _zz_116[1] = execute_SRC1[30]; + _zz_116[2] = execute_SRC1[29]; + _zz_116[3] = execute_SRC1[28]; + _zz_116[4] = execute_SRC1[27]; + _zz_116[5] = execute_SRC1[26]; + _zz_116[6] = execute_SRC1[25]; + _zz_116[7] = execute_SRC1[24]; + _zz_116[8] = execute_SRC1[23]; + _zz_116[9] = execute_SRC1[22]; + _zz_116[10] = execute_SRC1[21]; + _zz_116[11] = execute_SRC1[20]; + _zz_116[12] = execute_SRC1[19]; + _zz_116[13] = execute_SRC1[18]; + _zz_116[14] = execute_SRC1[17]; + _zz_116[15] = execute_SRC1[16]; + _zz_116[16] = execute_SRC1[15]; + _zz_116[17] = execute_SRC1[14]; + _zz_116[18] = execute_SRC1[13]; + _zz_116[19] = execute_SRC1[12]; + _zz_116[20] = execute_SRC1[11]; + _zz_116[21] = execute_SRC1[10]; + _zz_116[22] = execute_SRC1[9]; + _zz_116[23] = execute_SRC1[8]; + _zz_116[24] = execute_SRC1[7]; + _zz_116[25] = execute_SRC1[6]; + _zz_116[26] = execute_SRC1[5]; + _zz_116[27] = execute_SRC1[4]; + _zz_116[28] = execute_SRC1[3]; + _zz_116[29] = execute_SRC1[2]; + _zz_116[30] = execute_SRC1[1]; + _zz_116[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); + always @ (*) begin + _zz_117[0] = memory_SHIFT_RIGHT[31]; + _zz_117[1] = memory_SHIFT_RIGHT[30]; + _zz_117[2] = memory_SHIFT_RIGHT[29]; + _zz_117[3] = memory_SHIFT_RIGHT[28]; + _zz_117[4] = memory_SHIFT_RIGHT[27]; + _zz_117[5] = memory_SHIFT_RIGHT[26]; + _zz_117[6] = memory_SHIFT_RIGHT[25]; + _zz_117[7] = memory_SHIFT_RIGHT[24]; + _zz_117[8] = memory_SHIFT_RIGHT[23]; + _zz_117[9] = memory_SHIFT_RIGHT[22]; + _zz_117[10] = memory_SHIFT_RIGHT[21]; + _zz_117[11] = memory_SHIFT_RIGHT[20]; + _zz_117[12] = memory_SHIFT_RIGHT[19]; + _zz_117[13] = memory_SHIFT_RIGHT[18]; + _zz_117[14] = memory_SHIFT_RIGHT[17]; + _zz_117[15] = memory_SHIFT_RIGHT[16]; + _zz_117[16] = memory_SHIFT_RIGHT[15]; + _zz_117[17] = memory_SHIFT_RIGHT[14]; + _zz_117[18] = memory_SHIFT_RIGHT[13]; + _zz_117[19] = memory_SHIFT_RIGHT[12]; + _zz_117[20] = memory_SHIFT_RIGHT[11]; + _zz_117[21] = memory_SHIFT_RIGHT[10]; + _zz_117[22] = memory_SHIFT_RIGHT[9]; + _zz_117[23] = memory_SHIFT_RIGHT[8]; + _zz_117[24] = memory_SHIFT_RIGHT[7]; + _zz_117[25] = memory_SHIFT_RIGHT[6]; + _zz_117[26] = memory_SHIFT_RIGHT[5]; + _zz_117[27] = memory_SHIFT_RIGHT[4]; + _zz_117[28] = memory_SHIFT_RIGHT[3]; + _zz_117[29] = memory_SHIFT_RIGHT[2]; + _zz_117[30] = memory_SHIFT_RIGHT[1]; + _zz_117[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_118 = 1'b0; + if(_zz_271)begin + if(_zz_272)begin + if(_zz_123)begin + _zz_118 = 1'b1; + end + end + end if(_zz_273)begin if(_zz_274)begin - if(_zz_124)begin - _zz_119 = 1'b1; + if(_zz_125)begin + _zz_118 = 1'b1; end end end if(_zz_275)begin if(_zz_276)begin - if(_zz_126)begin - _zz_119 = 1'b1; - end - end - end - if(_zz_277)begin - if(_zz_278)begin - if(_zz_128)begin - _zz_119 = 1'b1; + if(_zz_127)begin + _zz_118 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_119 = 1'b0; + _zz_118 = 1'b0; end end always @ (*) begin - _zz_120 = 1'b0; + _zz_119 = 1'b0; + if(_zz_271)begin + if(_zz_272)begin + if(_zz_124)begin + _zz_119 = 1'b1; + end + end + end if(_zz_273)begin if(_zz_274)begin - if(_zz_125)begin - _zz_120 = 1'b1; + if(_zz_126)begin + _zz_119 = 1'b1; end end end if(_zz_275)begin if(_zz_276)begin - if(_zz_127)begin - _zz_120 = 1'b1; - end - end - end - if(_zz_277)begin - if(_zz_278)begin - if(_zz_129)begin - _zz_120 = 1'b1; + if(_zz_128)begin + _zz_119 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_120 = 1'b0; + _zz_119 = 1'b0; end end - assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_125 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_127 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_129 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_130 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_130 == 3'b000)) begin - _zz_131 = execute_BranchPlugin_eq; - end else if((_zz_130 == 3'b001)) begin - _zz_131 = (! execute_BranchPlugin_eq); - end else if((((_zz_130 & 3'b101) == 3'b101))) begin - _zz_131 = (! execute_SRC_LESS); + assign _zz_129 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_129 == 3'b000)) begin + _zz_130 = execute_BranchPlugin_eq; + end else if((_zz_129 == 3'b001)) begin + _zz_130 = (! execute_BranchPlugin_eq); + end else if((((_zz_129 & 3'b101) == 3'b101))) begin + _zz_130 = (! execute_SRC_LESS); end else begin - _zz_131 = execute_SRC_LESS; + _zz_130 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_132 = 1'b0; + _zz_131 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_132 = 1'b1; + _zz_131 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_132 = 1'b1; + _zz_131 = 1'b1; end default : begin - _zz_132 = _zz_131; + _zz_131 = _zz_130; end endcase end - assign _zz_133 = _zz_352[11]; - always @ (*) begin - _zz_134[19] = _zz_133; - _zz_134[18] = _zz_133; - _zz_134[17] = _zz_133; - _zz_134[16] = _zz_133; - _zz_134[15] = _zz_133; - _zz_134[14] = _zz_133; - _zz_134[13] = _zz_133; - _zz_134[12] = _zz_133; - _zz_134[11] = _zz_133; - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; - end - - assign _zz_135 = _zz_353[19]; - always @ (*) begin - _zz_136[10] = _zz_135; - _zz_136[9] = _zz_135; - _zz_136[8] = _zz_135; - _zz_136[7] = _zz_135; - _zz_136[6] = _zz_135; - _zz_136[5] = _zz_135; - _zz_136[4] = _zz_135; - _zz_136[3] = _zz_135; - _zz_136[2] = _zz_135; - _zz_136[1] = _zz_135; - _zz_136[0] = _zz_135; - end - - assign _zz_137 = _zz_354[11]; - always @ (*) begin - _zz_138[18] = _zz_137; - _zz_138[17] = _zz_137; - _zz_138[16] = _zz_137; - _zz_138[15] = _zz_137; - _zz_138[14] = _zz_137; - _zz_138[13] = _zz_137; - _zz_138[12] = _zz_137; - _zz_138[11] = _zz_137; - _zz_138[10] = _zz_137; - _zz_138[9] = _zz_137; - _zz_138[8] = _zz_137; - _zz_138[7] = _zz_137; - _zz_138[6] = _zz_137; - _zz_138[5] = _zz_137; - _zz_138[4] = _zz_137; - _zz_138[3] = _zz_137; - _zz_138[2] = _zz_137; - _zz_138[1] = _zz_137; - _zz_138[0] = _zz_137; + assign _zz_132 = _zz_350[11]; + always @ (*) begin + _zz_133[19] = _zz_132; + _zz_133[18] = _zz_132; + _zz_133[17] = _zz_132; + _zz_133[16] = _zz_132; + _zz_133[15] = _zz_132; + _zz_133[14] = _zz_132; + _zz_133[13] = _zz_132; + _zz_133[12] = _zz_132; + _zz_133[11] = _zz_132; + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; + end + + assign _zz_134 = _zz_351[19]; + always @ (*) begin + _zz_135[10] = _zz_134; + _zz_135[9] = _zz_134; + _zz_135[8] = _zz_134; + _zz_135[7] = _zz_134; + _zz_135[6] = _zz_134; + _zz_135[5] = _zz_134; + _zz_135[4] = _zz_134; + _zz_135[3] = _zz_134; + _zz_135[2] = _zz_134; + _zz_135[1] = _zz_134; + _zz_135[0] = _zz_134; + end + + assign _zz_136 = _zz_352[11]; + always @ (*) begin + _zz_137[18] = _zz_136; + _zz_137[17] = _zz_136; + _zz_137[16] = _zz_136; + _zz_137[15] = _zz_136; + _zz_137[14] = _zz_136; + _zz_137[13] = _zz_136; + _zz_137[12] = _zz_136; + _zz_137[11] = _zz_136; + _zz_137[10] = _zz_136; + _zz_137[9] = _zz_136; + _zz_137[8] = _zz_136; + _zz_137[7] = _zz_136; + _zz_137[6] = _zz_136; + _zz_137[5] = _zz_136; + _zz_137[4] = _zz_136; + _zz_137[3] = _zz_136; + _zz_137[2] = _zz_136; + _zz_137[1] = _zz_136; + _zz_137[0] = _zz_136; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_139 = (_zz_355[1] ^ execute_RS1[1]); + _zz_138 = (_zz_353[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_139 = _zz_356[1]; + _zz_138 = _zz_354[1]; end default : begin - _zz_139 = _zz_357[1]; + _zz_138 = _zz_355[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_139); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4228,80 +4196,80 @@ module VexRiscv_inner ( endcase end - assign _zz_140 = _zz_358[11]; + assign _zz_139 = _zz_356[11]; always @ (*) begin - _zz_141[19] = _zz_140; - _zz_141[18] = _zz_140; - _zz_141[17] = _zz_140; - _zz_141[16] = _zz_140; - _zz_141[15] = _zz_140; - _zz_141[14] = _zz_140; - _zz_141[13] = _zz_140; - _zz_141[12] = _zz_140; - _zz_141[11] = _zz_140; - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; + _zz_140[19] = _zz_139; + _zz_140[18] = _zz_139; + _zz_140[17] = _zz_139; + _zz_140[16] = _zz_139; + _zz_140[15] = _zz_139; + _zz_140[14] = _zz_139; + _zz_140[13] = _zz_139; + _zz_140[12] = _zz_139; + _zz_140[11] = _zz_139; + _zz_140[10] = _zz_139; + _zz_140[9] = _zz_139; + _zz_140[8] = _zz_139; + _zz_140[7] = _zz_139; + _zz_140[6] = _zz_139; + _zz_140[5] = _zz_139; + _zz_140[4] = _zz_139; + _zz_140[3] = _zz_139; + _zz_140[2] = _zz_139; + _zz_140[1] = _zz_139; + _zz_140[0] = _zz_139; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_141,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_143,{{{_zz_602,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_145,{{{_zz_603,_zz_604},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_594,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_595,_zz_596},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_361}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_359}; end end endcase end - assign _zz_142 = _zz_359[19]; - always @ (*) begin - _zz_143[10] = _zz_142; - _zz_143[9] = _zz_142; - _zz_143[8] = _zz_142; - _zz_143[7] = _zz_142; - _zz_143[6] = _zz_142; - _zz_143[5] = _zz_142; - _zz_143[4] = _zz_142; - _zz_143[3] = _zz_142; - _zz_143[2] = _zz_142; - _zz_143[1] = _zz_142; - _zz_143[0] = _zz_142; - end - - assign _zz_144 = _zz_360[11]; - always @ (*) begin - _zz_145[18] = _zz_144; - _zz_145[17] = _zz_144; - _zz_145[16] = _zz_144; - _zz_145[15] = _zz_144; - _zz_145[14] = _zz_144; - _zz_145[13] = _zz_144; - _zz_145[12] = _zz_144; - _zz_145[11] = _zz_144; - _zz_145[10] = _zz_144; - _zz_145[9] = _zz_144; - _zz_145[8] = _zz_144; - _zz_145[7] = _zz_144; - _zz_145[6] = _zz_144; - _zz_145[5] = _zz_144; - _zz_145[4] = _zz_144; - _zz_145[3] = _zz_144; - _zz_145[2] = _zz_144; - _zz_145[1] = _zz_144; - _zz_145[0] = _zz_144; + assign _zz_141 = _zz_357[19]; + always @ (*) begin + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; + end + + assign _zz_143 = _zz_358[11]; + always @ (*) begin + _zz_144[18] = _zz_143; + _zz_144[17] = _zz_143; + _zz_144[16] = _zz_143; + _zz_144[15] = _zz_143; + _zz_144[14] = _zz_143; + _zz_144[13] = _zz_143; + _zz_144[12] = _zz_143; + _zz_144[11] = _zz_143; + _zz_144[10] = _zz_143; + _zz_144[9] = _zz_143; + _zz_144[8] = _zz_143; + _zz_144[7] = _zz_143; + _zz_144[6] = _zz_143; + _zz_144[5] = _zz_143; + _zz_144[4] = _zz_143; + _zz_144[3] = _zz_143; + _zz_144[2] = _zz_143; + _zz_144[1] = _zz_143; + _zz_144[0] = _zz_143; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -4324,18 +4292,18 @@ module VexRiscv_inner ( end end - assign _zz_146 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_147 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_148 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_149 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_150 = _zz_362[0]; - assign _zz_151 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_152 = _zz_364[0]; + assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_149 = _zz_360[0]; + assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_151 = _zz_362[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_263)begin + if(_zz_261)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4345,7 +4313,7 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_266)begin + if(_zz_264)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -4586,7 +4554,7 @@ module VexRiscv_inner ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_279)begin + if(_zz_277)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4605,20 +4573,20 @@ module VexRiscv_inner ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_280)begin + if(_zz_278)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_281)begin + if(_zz_279)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_280)begin + if(_zz_278)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_281)begin + if(_zz_279)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4633,14 +4601,14 @@ module VexRiscv_inner ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_279)begin + if(_zz_277)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_279)begin + if(_zz_277)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4649,7 +4617,7 @@ module VexRiscv_inner ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_294) + case(_zz_292) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4662,50 +4630,49 @@ module VexRiscv_inner ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_366; - assign execute_CfuPlugin_functionsIds_1 = {6'd0, _zz_367}; - assign CfuPlugin_bus_cmd_payload_function_id = _zz_252; + assign execute_CfuPlugin_functionsIds_0 = _zz_364; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_169 = _zz_368[7]; - always @ (*) begin - _zz_170[23] = _zz_169; - _zz_170[22] = _zz_169; - _zz_170[21] = _zz_169; - _zz_170[20] = _zz_169; - _zz_170[19] = _zz_169; - _zz_170[18] = _zz_169; - _zz_170[17] = _zz_169; - _zz_170[16] = _zz_169; - _zz_170[15] = _zz_169; - _zz_170[14] = _zz_169; - _zz_170[13] = _zz_169; - _zz_170[12] = _zz_169; - _zz_170[11] = _zz_169; - _zz_170[10] = _zz_169; - _zz_170[9] = _zz_169; - _zz_170[8] = _zz_169; - _zz_170[7] = _zz_169; - _zz_170[6] = _zz_169; - _zz_170[5] = _zz_169; - _zz_170[4] = _zz_169; - _zz_170[3] = _zz_169; - _zz_170[2] = _zz_169; - _zz_170[1] = _zz_169; - _zz_170[0] = _zz_169; + assign _zz_168 = _zz_365[7]; + always @ (*) begin + _zz_169[23] = _zz_168; + _zz_169[22] = _zz_168; + _zz_169[21] = _zz_168; + _zz_169[20] = _zz_168; + _zz_169[19] = _zz_168; + _zz_169[18] = _zz_168; + _zz_169[17] = _zz_168; + _zz_169[16] = _zz_168; + _zz_169[15] = _zz_168; + _zz_169[14] = _zz_168; + _zz_169[13] = _zz_168; + _zz_169[12] = _zz_168; + _zz_169[11] = _zz_168; + _zz_169[10] = _zz_168; + _zz_169[9] = _zz_168; + _zz_169[8] = _zz_168; + _zz_169[7] = _zz_168; + _zz_169[6] = _zz_168; + _zz_169[5] = _zz_168; + _zz_169[4] = _zz_168; + _zz_169[3] = _zz_168; + _zz_169[2] = _zz_168; + _zz_169[1] = _zz_168; + _zz_169[0] = _zz_168; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_171 = execute_RS2; + _zz_170 = execute_RS2; end default : begin - _zz_171 = {_zz_170,execute_INSTRUCTION[31 : 24]}; + _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_171; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4731,7 +4698,7 @@ module VexRiscv_inner ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_282) + case(_zz_280) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4745,7 +4712,7 @@ module VexRiscv_inner ( end always @ (*) begin - case(_zz_282) + case(_zz_280) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4764,12 +4731,12 @@ module VexRiscv_inner ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_369) + $signed(_zz_370)); + assign writeBack_MulPlugin_result = ($signed(_zz_366) + $signed(_zz_367)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_258)begin - if(_zz_283)begin + if(_zz_256)begin + if(_zz_281)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4777,7 +4744,7 @@ module VexRiscv_inner ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_284)begin + if(_zz_282)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4788,32 +4755,32 @@ module VexRiscv_inner ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_374); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_172 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_172[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_375); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_376 : _zz_377); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_378[31:0]; - assign _zz_173 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_174 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_175 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_372); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_373 : _zz_374); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_375[31:0]; + assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_176[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_176[31 : 0] = execute_RS1; + _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_175[31 : 0] = execute_RS1; end - assign _zz_178 = (_zz_177 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_178 != 32'h0); + assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_177 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_285) + case(_zz_283) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4827,7 +4794,7 @@ module VexRiscv_inner ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_179))begin + if((! _zz_178))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4839,7 +4806,7 @@ module VexRiscv_inner ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_285) + case(_zz_283) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4906,7 +4873,7 @@ module VexRiscv_inner ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_180) + case(_zz_179) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4916,272 +4883,272 @@ module VexRiscv_inner ( end always @ (*) begin - _zz_181 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_181[12 : 0] = 13'h1000; - _zz_181[25 : 20] = 6'h20; + _zz_180[12 : 0] = 13'h1000; + _zz_180[25 : 20] = 6'h20; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_182[3 : 0] = 4'b1011; + _zz_181[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_183[4 : 0] = 5'h16; + _zz_182[4 : 0] = 5'h16; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_184[5 : 0] = 6'h21; + _zz_183[5 : 0] = 6'h21; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_185[31 : 30] = CsrPlugin_misa_base; - _zz_185[25 : 0] = CsrPlugin_misa_extensions; + _zz_184[31 : 30] = CsrPlugin_misa_base; + _zz_184[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_186[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_186[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_186[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_187[11 : 11] = CsrPlugin_mip_MEIP; - _zz_187[7 : 7] = CsrPlugin_mip_MTIP; - _zz_187[3 : 3] = CsrPlugin_mip_MSIP; + _zz_186[11 : 11] = CsrPlugin_mip_MEIP; + _zz_186[7 : 7] = CsrPlugin_mip_MTIP; + _zz_186[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_188[11 : 11] = CsrPlugin_mie_MEIE; - _zz_188[7 : 7] = CsrPlugin_mie_MTIE; - _zz_188[3 : 3] = CsrPlugin_mie_MSIE; + _zz_187[11 : 11] = CsrPlugin_mie_MEIE; + _zz_187[7 : 7] = CsrPlugin_mie_MTIE; + _zz_187[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_189[31 : 2] = CsrPlugin_mtvec_base; - _zz_189[1 : 0] = CsrPlugin_mtvec_mode; + _zz_188[31 : 2] = CsrPlugin_mtvec_base; + _zz_188[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_190[31 : 0] = CsrPlugin_mepc; + _zz_189[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_191[31 : 0] = CsrPlugin_mscratch; + _zz_190[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_192[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_192[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_193[31 : 0] = CsrPlugin_mtval; + _zz_192[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_198[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_199[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_199 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_200[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_201 = 32'h0; + _zz_200 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_201[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_202 = 32'h0; + _zz_201 = 32'h0; if(execute_CsrPlugin_csr_2820)begin - _zz_202[31 : 0] = _zz_153; + _zz_201[31 : 0] = _zz_152; end end always @ (*) begin - _zz_203 = 32'h0; + _zz_202 = 32'h0; if(execute_CsrPlugin_csr_2822)begin - _zz_203[31 : 0] = _zz_155; + _zz_202[31 : 0] = _zz_154; end end always @ (*) begin - _zz_204 = 32'h0; + _zz_203 = 32'h0; if(execute_CsrPlugin_csr_2824)begin - _zz_204[31 : 0] = _zz_157; + _zz_203[31 : 0] = _zz_156; end end always @ (*) begin - _zz_205 = 32'h0; + _zz_204 = 32'h0; if(execute_CsrPlugin_csr_2826)begin - _zz_205[31 : 0] = _zz_159; + _zz_204[31 : 0] = _zz_158; end end always @ (*) begin - _zz_206 = 32'h0; + _zz_205 = 32'h0; if(execute_CsrPlugin_csr_2828)begin - _zz_206[31 : 0] = _zz_161; + _zz_205[31 : 0] = _zz_160; end end always @ (*) begin - _zz_207 = 32'h0; + _zz_206 = 32'h0; if(execute_CsrPlugin_csr_2830)begin - _zz_207[31 : 0] = _zz_163; + _zz_206[31 : 0] = _zz_162; end end always @ (*) begin - _zz_208 = 32'h0; + _zz_207 = 32'h0; if(execute_CsrPlugin_csr_2832)begin - _zz_208[31 : 0] = _zz_165; + _zz_207[31 : 0] = _zz_164; end end always @ (*) begin - _zz_209 = 32'h0; + _zz_208 = 32'h0; if(execute_CsrPlugin_csr_2834)begin - _zz_209[31 : 0] = _zz_167; + _zz_208[31 : 0] = _zz_166; end end always @ (*) begin - _zz_210 = 32'h0; + _zz_209 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_210[31 : 0] = _zz_177; + _zz_209[31 : 0] = _zz_176; end end always @ (*) begin - _zz_211 = 32'h0; + _zz_210 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_211[31 : 0] = _zz_178; + _zz_210[31 : 0] = _zz_177; end end - assign execute_CsrPlugin_readData = (((((_zz_181 | _zz_182) | (_zz_183 | _zz_184)) | ((_zz_605 | _zz_185) | (_zz_186 | _zz_187))) | (((_zz_188 | _zz_189) | (_zz_190 | _zz_191)) | ((_zz_192 | _zz_193) | (_zz_194 | _zz_195)))) | ((((_zz_196 | _zz_197) | (_zz_198 | _zz_199)) | ((_zz_200 | _zz_201) | (_zz_202 | _zz_203))) | (((_zz_204 | _zz_205) | (_zz_206 | _zz_207)) | ((_zz_208 | _zz_209) | (_zz_210 | _zz_211))))); - assign iBusWishbone_ADR = {_zz_395,_zz_212}; - assign iBusWishbone_CTI = ((_zz_212 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_597 | _zz_184) | (_zz_185 | _zz_186))) | (((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194)))) | ((((_zz_195 | _zz_196) | (_zz_197 | _zz_198)) | ((_zz_199 | _zz_200) | (_zz_201 | _zz_202))) | (((_zz_203 | _zz_204) | (_zz_205 | _zz_206)) | ((_zz_207 | _zz_208) | (_zz_209 | _zz_210))))); + assign iBusWishbone_ADR = {_zz_392,_zz_211}; + assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_286)begin + if(_zz_284)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_286)begin + if(_zz_284)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_213; + assign iBus_rsp_valid = _zz_212; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_219 = (dBus_cmd_payload_length != 3'b000); - assign _zz_215 = dBus_cmd_valid; - assign _zz_217 = dBus_cmd_payload_wr; - assign _zz_218 = (_zz_214 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_216 && (_zz_217 || _zz_218)); - assign dBusWishbone_ADR = ((_zz_219 ? {{dBus_cmd_payload_address[31 : 5],_zz_214},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_219 ? (_zz_218 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_218 = (dBus_cmd_payload_length != 3'b000); + assign _zz_214 = dBus_cmd_valid; + assign _zz_216 = dBus_cmd_payload_wr; + assign _zz_217 = (_zz_213 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_215 && (_zz_216 || _zz_217)); + assign dBusWishbone_ADR = ((_zz_218 ? {{dBus_cmd_payload_address[31 : 5],_zz_213},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_218 ? (_zz_217 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_217 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_217; + assign dBusWishbone_SEL = (_zz_216 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_216; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_216 = (_zz_215 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_215; - assign dBusWishbone_STB = _zz_215; - assign dBus_rsp_valid = _zz_220; + assign _zz_215 = (_zz_214 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_214; + assign dBusWishbone_STB = _zz_214; + assign dBus_rsp_valid = _zz_219; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5203,8 +5170,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; DBusCachedPlugin_rspCounter <= _zz_88; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_109 <= 1'b1; - _zz_121 <= 1'b0; + _zz_108 <= 1'b1; + _zz_120 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -5228,16 +5195,16 @@ module VexRiscv_inner ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_177 <= 32'h0; + _zz_176 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_180 <= 3'b000; + _zz_179 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_212 <= 3'b000; - _zz_213 <= 1'b0; - _zz_214 <= 3'b000; - _zz_220 <= 1'b0; + _zz_211 <= 3'b000; + _zz_212 <= 1'b0; + _zz_213 <= 3'b000; + _zz_219 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5318,7 +5285,7 @@ module VexRiscv_inner ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_287)begin + if(_zz_285)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5327,8 +5294,8 @@ module VexRiscv_inner ( if(dBus_rsp_valid)begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_109 <= 1'b0; - _zz_121 <= (_zz_47 && writeBack_arbitration_isFiring); + _zz_108 <= 1'b0; + _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5350,14 +5317,14 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_288)begin - if(_zz_289)begin + if(_zz_286)begin + if(_zz_287)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_290)begin + if(_zz_288)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_291)begin + if(_zz_289)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5382,7 +5349,7 @@ module VexRiscv_inner ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_268)begin + if(_zz_266)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5393,8 +5360,8 @@ module VexRiscv_inner ( end endcase end - if(_zz_269)begin - case(_zz_271) + if(_zz_267)begin + case(_zz_269) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5404,7 +5371,7 @@ module VexRiscv_inner ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_148,{_zz_147,_zz_146}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -5420,7 +5387,7 @@ module VexRiscv_inner ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_292)begin + if(_zz_290)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; @@ -5445,25 +5412,25 @@ module VexRiscv_inner ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_180) + case(_zz_179) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_180 <= 3'b001; + _zz_179 <= 3'b001; end end 3'b001 : begin - _zz_180 <= 3'b010; + _zz_179 <= 3'b010; end 3'b010 : begin - _zz_180 <= 3'b011; + _zz_179 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_180 <= 3'b100; + _zz_179 <= 3'b100; end end 3'b100 : begin - _zz_180 <= 3'b000; + _zz_179 <= 3'b000; end default : begin end @@ -5477,35 +5444,35 @@ module VexRiscv_inner ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_388[0]; - CsrPlugin_mstatus_MIE <= _zz_389[0]; + CsrPlugin_mstatus_MPIE <= _zz_385[0]; + CsrPlugin_mstatus_MIE <= _zz_386[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_391[0]; - CsrPlugin_mie_MTIE <= _zz_392[0]; - CsrPlugin_mie_MSIE <= _zz_393[0]; + CsrPlugin_mie_MEIE <= _zz_388[0]; + CsrPlugin_mie_MTIE <= _zz_389[0]; + CsrPlugin_mie_MSIE <= _zz_390[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_177 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_286)begin + if(_zz_284)begin if(iBusWishbone_ACK)begin - _zz_212 <= (_zz_212 + 3'b001); + _zz_211 <= (_zz_211 + 3'b001); end end - _zz_213 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_215 && _zz_216))begin - _zz_214 <= (_zz_214 + 3'b001); - if(_zz_218)begin - _zz_214 <= 3'b000; + _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_214 && _zz_215))begin + _zz_213 <= (_zz_213 + 3'b001); + if(_zz_217)begin + _zz_213 <= 3'b000; end end - _zz_220 <= ((_zz_215 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_219 <= ((_zz_214 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5519,7 +5486,7 @@ module VexRiscv_inner ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_287)begin + if(_zz_285)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5537,8 +5504,8 @@ module VexRiscv_inner ( dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end - _zz_122 <= _zz_46[11 : 7]; - _zz_123 <= _zz_57; + _zz_121 <= _zz_46[11 : 7]; + _zz_122 <= _zz_57; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5546,13 +5513,13 @@ module VexRiscv_inner ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_263)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_261)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(_zz_266)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_152 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_152 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_264)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end if(CfuPlugin_joinException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; @@ -5562,21 +5529,21 @@ module VexRiscv_inner ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_288)begin - if(_zz_289)begin + if(_zz_286)begin + if(_zz_287)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_290)begin + if(_zz_288)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_291)begin + if(_zz_289)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_268)begin + if(_zz_266)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5590,31 +5557,31 @@ module VexRiscv_inner ( end endcase end - if(_zz_154[0])begin - _zz_153 <= (_zz_153 + 32'h00000001); + if(_zz_153[0])begin + _zz_152 <= (_zz_152 + 32'h00000001); end - if(_zz_156[0])begin - _zz_155 <= (_zz_155 + 32'h00000001); + if(_zz_155[0])begin + _zz_154 <= (_zz_154 + 32'h00000001); end - if(_zz_158[0])begin - _zz_157 <= (_zz_157 + 32'h00000001); + if(_zz_157[0])begin + _zz_156 <= (_zz_156 + 32'h00000001); end - if(_zz_160[0])begin - _zz_159 <= (_zz_159 + 32'h00000001); + if(_zz_159[0])begin + _zz_158 <= (_zz_158 + 32'h00000001); end - if(_zz_162[0])begin - _zz_161 <= (_zz_161 + 32'h00000001); + if(_zz_161[0])begin + _zz_160 <= (_zz_160 + 32'h00000001); end - if(_zz_164[0])begin - _zz_163 <= (_zz_163 + 32'h00000001); + if(_zz_163[0])begin + _zz_162 <= (_zz_162 + 32'h00000001); end - if(_zz_166[0])begin - _zz_165 <= (_zz_165 + 32'h00000001); + if(_zz_165[0])begin + _zz_164 <= (_zz_164 + 32'h00000001); end - if(_zz_168[0])begin - _zz_167 <= (_zz_167 + 32'h00000001); + if(_zz_167[0])begin + _zz_166 <= (_zz_166 + 32'h00000001); end - if(_zz_292)begin + if(_zz_290)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5624,20 +5591,20 @@ module VexRiscv_inner ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_258)begin - if(_zz_283)begin + if(_zz_256)begin + if(_zz_281)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_379[31:0]; + memory_DivPlugin_div_result <= _zz_376[31:0]; end end end - if(_zz_284)begin + if(_zz_282)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_175 ? (~ _zz_176) : _zz_176) + _zz_385); - memory_DivPlugin_rs2 <= ((_zz_174 ? (~ execute_RS2) : execute_RS2) + _zz_387); - memory_DivPlugin_div_needRevert <= ((_zz_175 ^ (_zz_174 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_382); + memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_384); + memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5751,9 +5718,6 @@ module VexRiscv_inner ( if((! execute_arbitration_isStuck))begin decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENCODING <= decode_CfuPlugin_CFU_ENCODING; - end if((! execute_arbitration_isStuck))begin decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; end @@ -5957,7 +5921,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_390[0]; + CsrPlugin_mip_MSIP <= _zz_387[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5978,7 +5942,7 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_394[0]; + CsrPlugin_mcause_interrupt <= _zz_391[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -6009,82 +5973,82 @@ module VexRiscv_inner ( end if(execute_CsrPlugin_csr_2820)begin if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2821)begin if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2822)begin if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2823)begin if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2824)begin if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2825)begin if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2826)begin if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2827)begin if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2828)begin if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2829)begin if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2830)begin if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2831)begin if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2832)begin if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2833)begin if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2834)begin if(execute_CsrPlugin_writeEnable)begin - _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; end end if(execute_CsrPlugin_csr_2835)begin if(execute_CsrPlugin_writeEnable)begin - _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -6101,8 +6065,8 @@ module VexRiscv_inner ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_57; end - _zz_179 <= debug_bus_cmd_payload_address[2]; - if(_zz_265)begin + _zz_178 <= debug_bus_cmd_payload_address[2]; + if(_zz_263)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -6120,7 +6084,7 @@ module VexRiscv_inner ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_285) + case(_zz_283) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -6148,13 +6112,13 @@ module VexRiscv_inner ( end endcase end - if(_zz_265)begin - if(_zz_267)begin + if(_zz_263)begin + if(_zz_265)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_270)begin + if(_zz_268)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index 95eb44b..de3058b 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -214,13 +214,14 @@ object GenCoreDefault{ instruction = M"-------------------------0001011", functionId = List(14 downto 12, 31 downto 25), input2Kind = CfuPlugin.Input2Kind.RS - ), - // CFU I-type - CfuPluginEncoding ( - instruction = M"-----------------000-----0101011", - functionId = List(23 downto 20), - input2Kind = CfuPlugin.Input2Kind.IMM_I ) + //, + // CFU I-type + //CfuPluginEncoding ( + // instruction = M"-----------------000-----0101011", + // functionId = List(23 downto 20), + // input2Kind = CfuPlugin.Input2Kind.IMM_I + //) ), busParameter = CfuBusParameter( CFU_VERSION = 0, From b31d499bc540d49b8e1c2b15ed57ceed1844b7bf Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Sun, 25 Apr 2021 14:22:54 -0700 Subject: [PATCH 13/30] Add 'SlimCfu' variants; add missing reset/rst connections. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 16 +- .../verilog/VexRiscv_SlimCfu.v | 6031 ++++++++++++++++ .../verilog/VexRiscv_SlimCfu.yaml | 4 + .../verilog/VexRiscv_SlimCfuDebug.v | 6308 +++++++++++++++++ .../verilog/VexRiscv_SlimCfuDebug.yaml | 5 + pythondata_cpu_vexriscv/verilog/genWrapper.py | 6 +- .../verilog/wrapVexRiscv_FullCfu.v | 3 +- .../verilog/wrapVexRiscv_FullCfuDebug.v | 3 +- .../verilog/wrapVexRiscv_SlimCfu.v | 105 + .../verilog/wrapVexRiscv_SlimCfuDebug.v | 121 + 10 files changed, 12597 insertions(+), 5 deletions(-) create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml create mode 100644 pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfu.v create mode 100644 pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfuDebug.v diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index 187afee..1a9acd9 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -1,6 +1,6 @@ SRC := ${shell find . -type f -name \*.scala} -all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v +all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_SlimCfu.v VexRiscv_SlimCfuDebug.v VexRiscv.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault" @@ -46,6 +46,20 @@ VexRiscv_FullCfuDebug.v: $(SRC) /bin/mv tmp.v $@ ./genWrapper.py $@ > wrap$@ +# CFU versions must have module name changed because they will be wrapped +VexRiscv_SlimCfu.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 2048 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfu" + sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v + /bin/mv tmp.v $@ + ./genWrapper.py $@ > wrap$@ + +# CFU versions must have module name changed because they will be wrapped +VexRiscv_SlimCfuDebug.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 2048 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfuDebug" + sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v + /bin/mv tmp.v $@ + ./genWrapper.py $@ > wrap$@ + VexRiscv_Linux.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal --outputFile VexRiscv_Linux" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v new file mode 100644 index 0000000..78b516c --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v @@ -0,0 +1,6031 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : c8881985e0b323f1b12cab3ed0bd455d6c406944 + + +`define Input2Kind_defaultEncoding_type [0:0] +`define Input2Kind_defaultEncoding_RS 1'b0 +`define Input2Kind_defaultEncoding_IMM_I 1'b1 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv_inner ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input CfuPlugin_bus_rsp_payload_response_ok, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + wire _zz_219; + wire _zz_220; + wire _zz_221; + reg _zz_222; + reg [31:0] _zz_223; + reg [31:0] _zz_224; + reg [31:0] _zz_225; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire [1:0] _zz_242; + wire _zz_243; + wire _zz_244; + wire _zz_245; + wire _zz_246; + wire _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire [1:0] _zz_254; + wire _zz_255; + wire _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire _zz_263; + wire [1:0] _zz_264; + wire _zz_265; + wire [1:0] _zz_266; + wire [51:0] _zz_267; + wire [51:0] _zz_268; + wire [51:0] _zz_269; + wire [32:0] _zz_270; + wire [51:0] _zz_271; + wire [49:0] _zz_272; + wire [51:0] _zz_273; + wire [49:0] _zz_274; + wire [51:0] _zz_275; + wire [32:0] _zz_276; + wire [31:0] _zz_277; + wire [32:0] _zz_278; + wire [0:0] _zz_279; + wire [0:0] _zz_280; + wire [0:0] _zz_281; + wire [0:0] _zz_282; + wire [0:0] _zz_283; + wire [0:0] _zz_284; + wire [0:0] _zz_285; + wire [0:0] _zz_286; + wire [0:0] _zz_287; + wire [0:0] _zz_288; + wire [0:0] _zz_289; + wire [0:0] _zz_290; + wire [0:0] _zz_291; + wire [0:0] _zz_292; + wire [0:0] _zz_293; + wire [0:0] _zz_294; + wire [0:0] _zz_295; + wire [3:0] _zz_296; + wire [2:0] _zz_297; + wire [31:0] _zz_298; + wire [11:0] _zz_299; + wire [31:0] _zz_300; + wire [19:0] _zz_301; + wire [11:0] _zz_302; + wire [31:0] _zz_303; + wire [31:0] _zz_304; + wire [19:0] _zz_305; + wire [11:0] _zz_306; + wire [2:0] _zz_307; + wire [0:0] _zz_308; + wire [2:0] _zz_309; + wire [4:0] _zz_310; + wire [11:0] _zz_311; + wire [11:0] _zz_312; + wire [31:0] _zz_313; + wire [31:0] _zz_314; + wire [31:0] _zz_315; + wire [31:0] _zz_316; + wire [31:0] _zz_317; + wire [31:0] _zz_318; + wire [31:0] _zz_319; + wire [11:0] _zz_320; + wire [19:0] _zz_321; + wire [11:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [11:0] _zz_326; + wire [19:0] _zz_327; + wire [11:0] _zz_328; + wire [2:0] _zz_329; + wire [1:0] _zz_330; + wire [1:0] _zz_331; + wire [1:0] _zz_332; + wire [1:0] _zz_333; + wire [1:0] _zz_334; + wire [1:0] _zz_335; + wire [9:0] _zz_336; + wire [7:0] _zz_337; + wire [65:0] _zz_338; + wire [65:0] _zz_339; + wire [31:0] _zz_340; + wire [31:0] _zz_341; + wire [0:0] _zz_342; + wire [5:0] _zz_343; + wire [32:0] _zz_344; + wire [31:0] _zz_345; + wire [31:0] _zz_346; + wire [32:0] _zz_347; + wire [32:0] _zz_348; + wire [32:0] _zz_349; + wire [32:0] _zz_350; + wire [0:0] _zz_351; + wire [32:0] _zz_352; + wire [0:0] _zz_353; + wire [32:0] _zz_354; + wire [0:0] _zz_355; + wire [31:0] _zz_356; + wire [0:0] _zz_357; + wire [0:0] _zz_358; + wire [0:0] _zz_359; + wire [0:0] _zz_360; + wire [0:0] _zz_361; + wire [0:0] _zz_362; + wire [0:0] _zz_363; + wire [26:0] _zz_364; + wire _zz_365; + wire _zz_366; + wire [1:0] _zz_367; + wire [31:0] _zz_368; + wire [31:0] _zz_369; + wire [31:0] _zz_370; + wire _zz_371; + wire [0:0] _zz_372; + wire [13:0] _zz_373; + wire [31:0] _zz_374; + wire [31:0] _zz_375; + wire [31:0] _zz_376; + wire _zz_377; + wire [0:0] _zz_378; + wire [7:0] _zz_379; + wire [31:0] _zz_380; + wire [31:0] _zz_381; + wire [31:0] _zz_382; + wire _zz_383; + wire [0:0] _zz_384; + wire [1:0] _zz_385; + wire _zz_386; + wire _zz_387; + wire _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire _zz_391; + wire _zz_392; + wire [0:0] _zz_393; + wire [25:0] _zz_394; + wire [31:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [0:0] _zz_398; + wire [0:0] _zz_399; + wire [1:0] _zz_400; + wire [1:0] _zz_401; + wire _zz_402; + wire [0:0] _zz_403; + wire [20:0] _zz_404; + wire [31:0] _zz_405; + wire [31:0] _zz_406; + wire [31:0] _zz_407; + wire [31:0] _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire [0:0] _zz_411; + wire [0:0] _zz_412; + wire [2:0] _zz_413; + wire [2:0] _zz_414; + wire _zz_415; + wire [0:0] _zz_416; + wire [17:0] _zz_417; + wire [31:0] _zz_418; + wire [31:0] _zz_419; + wire [31:0] _zz_420; + wire [31:0] _zz_421; + wire _zz_422; + wire _zz_423; + wire [31:0] _zz_424; + wire [31:0] _zz_425; + wire _zz_426; + wire [0:0] _zz_427; + wire [0:0] _zz_428; + wire _zz_429; + wire [0:0] _zz_430; + wire [14:0] _zz_431; + wire [31:0] _zz_432; + wire _zz_433; + wire _zz_434; + wire [0:0] _zz_435; + wire [1:0] _zz_436; + wire [4:0] _zz_437; + wire [4:0] _zz_438; + wire _zz_439; + wire [0:0] _zz_440; + wire [11:0] _zz_441; + wire [31:0] _zz_442; + wire [31:0] _zz_443; + wire [31:0] _zz_444; + wire [31:0] _zz_445; + wire [31:0] _zz_446; + wire [31:0] _zz_447; + wire _zz_448; + wire [0:0] _zz_449; + wire [1:0] _zz_450; + wire [31:0] _zz_451; + wire [31:0] _zz_452; + wire [0:0] _zz_453; + wire [4:0] _zz_454; + wire [4:0] _zz_455; + wire [4:0] _zz_456; + wire _zz_457; + wire [0:0] _zz_458; + wire [8:0] _zz_459; + wire [31:0] _zz_460; + wire [31:0] _zz_461; + wire [31:0] _zz_462; + wire _zz_463; + wire _zz_464; + wire [31:0] _zz_465; + wire [31:0] _zz_466; + wire _zz_467; + wire [0:0] _zz_468; + wire [2:0] _zz_469; + wire [0:0] _zz_470; + wire [2:0] _zz_471; + wire [0:0] _zz_472; + wire [4:0] _zz_473; + wire [1:0] _zz_474; + wire [1:0] _zz_475; + wire _zz_476; + wire [0:0] _zz_477; + wire [6:0] _zz_478; + wire [31:0] _zz_479; + wire [31:0] _zz_480; + wire [31:0] _zz_481; + wire _zz_482; + wire [0:0] _zz_483; + wire [0:0] _zz_484; + wire [31:0] _zz_485; + wire [31:0] _zz_486; + wire _zz_487; + wire [0:0] _zz_488; + wire [0:0] _zz_489; + wire _zz_490; + wire [0:0] _zz_491; + wire [2:0] _zz_492; + wire _zz_493; + wire [0:0] _zz_494; + wire [0:0] _zz_495; + wire [0:0] _zz_496; + wire [0:0] _zz_497; + wire _zz_498; + wire [0:0] _zz_499; + wire [4:0] _zz_500; + wire [31:0] _zz_501; + wire [31:0] _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire [31:0] _zz_505; + wire [31:0] _zz_506; + wire [31:0] _zz_507; + wire [31:0] _zz_508; + wire [31:0] _zz_509; + wire [31:0] _zz_510; + wire [31:0] _zz_511; + wire [31:0] _zz_512; + wire [31:0] _zz_513; + wire _zz_514; + wire [0:0] _zz_515; + wire [0:0] _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire [31:0] _zz_520; + wire [31:0] _zz_521; + wire _zz_522; + wire [3:0] _zz_523; + wire [3:0] _zz_524; + wire _zz_525; + wire [0:0] _zz_526; + wire [2:0] _zz_527; + wire [31:0] _zz_528; + wire [31:0] _zz_529; + wire [31:0] _zz_530; + wire [31:0] _zz_531; + wire [31:0] _zz_532; + wire [31:0] _zz_533; + wire _zz_534; + wire [0:0] _zz_535; + wire [1:0] _zz_536; + wire _zz_537; + wire [2:0] _zz_538; + wire [2:0] _zz_539; + wire _zz_540; + wire [0:0] _zz_541; + wire [0:0] _zz_542; + wire [31:0] _zz_543; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; + wire [31:0] _zz_549; + wire _zz_550; + wire _zz_551; + wire _zz_552; + wire [0:0] _zz_553; + wire [0:0] _zz_554; + wire _zz_555; + wire _zz_556; + wire _zz_557; + wire _zz_558; + wire [31:0] _zz_559; + wire [51:0] memory_MUL_LOW; + wire [31:0] memory_MEMORY_READ_DATA; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_1; + wire `Input2Kind_defaultEncoding_type _zz_2; + wire `Input2Kind_defaultEncoding_type _zz_3; + wire decode_CfuPlugin_CFU_ENABLE; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `AluCtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + reg _zz_30; + reg _zz_31; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_32; + wire execute_CfuPlugin_CFU_ENABLE; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_37; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_38; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_41; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; + wire [31:0] _zz_46; + wire _zz_47; + reg _zz_48; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `Input2Kind_defaultEncoding_type _zz_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; + wire `Src2CtrlEnum_defaultEncoding_type _zz_54; + wire `AluCtrlEnum_defaultEncoding_type _zz_55; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_57; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP2_physicalAddress; + wire memory_MMU_RSP2_isIoAccess; + wire memory_MMU_RSP2_isPaging; + wire memory_MMU_RSP2_allowRead; + wire memory_MMU_RSP2_allowWrite; + wire memory_MMU_RSP2_allowExecute; + wire memory_MMU_RSP2_exception; + wire memory_MMU_RSP2_refilling; + wire memory_MMU_RSP2_bypassTranslation; + wire [31:0] memory_PC; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire execute_MMU_FAULT; + wire [31:0] execute_MMU_RSP2_physicalAddress; + wire execute_MMU_RSP2_isIoAccess; + wire execute_MMU_RSP2_isPaging; + wire execute_MMU_RSP2_allowRead; + wire execute_MMU_RSP2_allowWrite; + wire execute_MMU_RSP2_allowExecute; + wire execute_MMU_RSP2_exception; + wire execute_MMU_RSP2_refilling; + wire execute_MMU_RSP2_bypassTranslation; + wire [31:0] execute_SRC_ADD; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_59; + reg [31:0] _zz_60; + reg [31:0] _zz_61; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire DBusSimplePlugin_mmuBus_cmd_0_isValid; + wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire DBusSimplePlugin_mmuBus_rsp_isPaging; + wire DBusSimplePlugin_mmuBus_rsp_allowRead; + wire DBusSimplePlugin_mmuBus_rsp_allowWrite; + wire DBusSimplePlugin_mmuBus_rsp_allowExecute; + wire DBusSimplePlugin_mmuBus_rsp_exception; + wire DBusSimplePlugin_mmuBus_rsp_refilling; + wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire DBusSimplePlugin_mmuBus_end; + wire DBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_redoBranch_valid; + wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + reg CfuPlugin_joinException_valid; + wire [3:0] CfuPlugin_joinException_payload_code; + wire [31:0] CfuPlugin_joinException_payload_badAddr; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_62; + wire [3:0] _zz_63; + wire _zz_64; + wire _zz_65; + wire _zz_66; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_67; + wire _zz_68; + wire _zz_69; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_70; + wire _zz_71; + reg _zz_72; + wire _zz_73; + reg _zz_74; + reg [31:0] _zz_75; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_76; + reg [18:0] _zz_77; + wire _zz_78; + reg [10:0] _zz_79; + wire _zz_80; + reg [18:0] _zz_81; + reg _zz_82; + wire _zz_83; + reg [10:0] _zz_84; + wire _zz_85; + reg [18:0] _zz_86; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_87; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire _zz_88; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_89; + reg [3:0] _zz_90; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_91; + reg [31:0] _zz_92; + wire _zz_93; + reg [31:0] _zz_94; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [32:0] _zz_95; + wire _zz_96; + wire _zz_97; + wire _zz_98; + wire _zz_99; + wire _zz_100; + wire `Src1CtrlEnum_defaultEncoding_type _zz_101; + wire `AluCtrlEnum_defaultEncoding_type _zz_102; + wire `Src2CtrlEnum_defaultEncoding_type _zz_103; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_104; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_105; + wire `BranchCtrlEnum_defaultEncoding_type _zz_106; + wire `EnvCtrlEnum_defaultEncoding_type _zz_107; + wire `Input2Kind_defaultEncoding_type _zz_108; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_109; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_110; + reg [31:0] _zz_111; + wire _zz_112; + reg [19:0] _zz_113; + wire _zz_114; + reg [19:0] _zz_115; + reg [31:0] _zz_116; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_117; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_118; + reg _zz_119; + reg _zz_120; + reg _zz_121; + reg [4:0] _zz_122; + reg [31:0] _zz_123; + wire _zz_124; + wire _zz_125; + wire _zz_126; + wire _zz_127; + wire _zz_128; + wire _zz_129; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_130; + reg _zz_131; + reg _zz_132; + wire _zz_133; + reg [19:0] _zz_134; + wire _zz_135; + reg [10:0] _zz_136; + wire _zz_137; + reg [18:0] _zz_138; + reg _zz_139; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_140; + reg [19:0] _zz_141; + wire _zz_142; + reg [10:0] _zz_143; + wire _zz_144; + reg [18:0] _zz_145; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_146; + wire _zz_147; + wire _zz_148; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_149; + wire _zz_150; + wire [1:0] _zz_151; + wire _zz_152; + wire [1:0] _zz_153; + wire _zz_154; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_171; + reg [23:0] _zz_172; + reg [31:0] _zz_173; + wire memory_CfuPlugin_rsp_valid; + reg memory_CfuPlugin_rsp_ready; + wire memory_CfuPlugin_rsp_payload_response_ok; + wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_s2mPipe_rValid; + reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_174; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_175; + wire _zz_176; + wire _zz_177; + reg [32:0] _zz_178; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_179; + wire [31:0] _zz_180; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; + reg execute_to_memory_MMU_RSP2_isIoAccess; + reg execute_to_memory_MMU_RSP2_isPaging; + reg execute_to_memory_MMU_RSP2_allowRead; + reg execute_to_memory_MMU_RSP2_allowWrite; + reg execute_to_memory_MMU_RSP2_allowExecute; + reg execute_to_memory_MMU_RSP2_exception; + reg execute_to_memory_MMU_RSP2_refilling; + reg execute_to_memory_MMU_RSP2_bypassTranslation; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_2820; + reg execute_CsrPlugin_csr_2821; + reg execute_CsrPlugin_csr_2822; + reg execute_CsrPlugin_csr_2823; + reg execute_CsrPlugin_csr_2824; + reg execute_CsrPlugin_csr_2825; + reg execute_CsrPlugin_csr_2826; + reg execute_CsrPlugin_csr_2827; + reg execute_CsrPlugin_csr_2828; + reg execute_CsrPlugin_csr_2829; + reg execute_CsrPlugin_csr_2830; + reg execute_CsrPlugin_csr_2831; + reg execute_CsrPlugin_csr_2832; + reg execute_CsrPlugin_csr_2833; + reg execute_CsrPlugin_csr_2834; + reg execute_CsrPlugin_csr_2835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; + reg [31:0] _zz_199; + reg [31:0] _zz_200; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + reg [31:0] _zz_208; + reg [31:0] _zz_209; + reg [31:0] _zz_210; + reg [2:0] _zz_211; + reg _zz_212; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_213; + `ifndef SYNTHESIS + reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [39:0] _zz_10_string; + reg [31:0] _zz_11_string; + reg [31:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [71:0] _zz_17_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [39:0] _zz_20_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [23:0] _zz_23_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [63:0] _zz_26_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [95:0] _zz_29_string; + reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_32_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_33_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_34_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_35_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_36_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_39_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_40_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_42_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_43_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_44_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_45_string; + reg [39:0] _zz_49_string; + reg [39:0] _zz_50_string; + reg [31:0] _zz_51_string; + reg [71:0] _zz_52_string; + reg [39:0] _zz_53_string; + reg [23:0] _zz_54_string; + reg [63:0] _zz_55_string; + reg [95:0] _zz_56_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_58_string; + reg [95:0] _zz_101_string; + reg [63:0] _zz_102_string; + reg [23:0] _zz_103_string; + reg [39:0] _zz_104_string; + reg [71:0] _zz_105_string; + reg [31:0] _zz_106_string; + reg [39:0] _zz_107_string; + reg [39:0] _zz_108_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_226 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_227 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_228 = 1'b1; + assign _zz_229 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_230 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_231 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_232 = ((_zz_219 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_233 = ((_zz_219 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_234 = ((_zz_219 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_235 = ((_zz_219 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_236 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_237 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_238 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_239 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_240 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_241 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_242 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_243 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_244 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_245 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_246 = (1'b0 || (! 1'b1)); + assign _zz_247 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_248 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_249 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_250 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_251 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_252 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_253 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_254 = execute_INSTRUCTION[13 : 12]; + assign _zz_255 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_256 = (! memory_arbitration_isStuck); + assign _zz_257 = (iBus_cmd_valid || (_zz_211 != 3'b000)); + assign _zz_258 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_259 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_260 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_261 = ((_zz_148 && 1'b1) && (! 1'b0)); + assign _zz_262 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_263 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_264 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_265 = execute_INSTRUCTION[13]; + assign _zz_266 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_267 = ($signed(_zz_268) + $signed(_zz_273)); + assign _zz_268 = ($signed(_zz_269) + $signed(_zz_271)); + assign _zz_269 = 52'h0; + assign _zz_270 = {1'b0,memory_MUL_LL}; + assign _zz_271 = {{19{_zz_270[32]}}, _zz_270}; + assign _zz_272 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_273 = {{2{_zz_272[49]}}, _zz_272}; + assign _zz_274 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_275 = {{2{_zz_274[49]}}, _zz_274}; + assign _zz_276 = ($signed(_zz_278) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_277 = _zz_276[31 : 0]; + assign _zz_278 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_279 = _zz_95[32 : 32]; + assign _zz_280 = _zz_95[31 : 31]; + assign _zz_281 = _zz_95[30 : 30]; + assign _zz_282 = _zz_95[29 : 29]; + assign _zz_283 = _zz_95[27 : 27]; + assign _zz_284 = _zz_95[24 : 24]; + assign _zz_285 = _zz_95[16 : 16]; + assign _zz_286 = _zz_95[13 : 13]; + assign _zz_287 = _zz_95[12 : 12]; + assign _zz_288 = _zz_95[11 : 11]; + assign _zz_289 = _zz_95[15 : 15]; + assign _zz_290 = _zz_95[5 : 5]; + assign _zz_291 = _zz_95[3 : 3]; + assign _zz_292 = _zz_95[19 : 19]; + assign _zz_293 = _zz_95[10 : 10]; + assign _zz_294 = _zz_95[4 : 4]; + assign _zz_295 = _zz_95[0 : 0]; + assign _zz_296 = (_zz_62 - 4'b0001); + assign _zz_297 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_298 = {29'd0, _zz_297}; + assign _zz_299 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_300 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_301 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_302 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_303 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_304 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_305 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_306 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_307 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_308 = execute_SRC_LESS; + assign _zz_309 = 3'b100; + assign _zz_310 = execute_INSTRUCTION[19 : 15]; + assign _zz_311 = execute_INSTRUCTION[31 : 20]; + assign _zz_312 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_313 = ($signed(_zz_314) + $signed(_zz_317)); + assign _zz_314 = ($signed(_zz_315) + $signed(_zz_316)); + assign _zz_315 = execute_SRC1; + assign _zz_316 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_317 = (execute_SRC_USE_SUB_LESS ? _zz_318 : _zz_319); + assign _zz_318 = 32'h00000001; + assign _zz_319 = 32'h0; + assign _zz_320 = execute_INSTRUCTION[31 : 20]; + assign _zz_321 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_322 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_323 = {_zz_134,execute_INSTRUCTION[31 : 20]}; + assign _zz_324 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_325 = {{_zz_138,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_326 = execute_INSTRUCTION[31 : 20]; + assign _zz_327 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_329 = 3'b100; + assign _zz_330 = (_zz_149 & (~ _zz_331)); + assign _zz_331 = (_zz_149 - 2'b01); + assign _zz_332 = (_zz_151 & (~ _zz_333)); + assign _zz_333 = (_zz_151 - 2'b01); + assign _zz_334 = (_zz_153 & (~ _zz_335)); + assign _zz_335 = (_zz_153 - 2'b01); + assign _zz_336 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_337 = execute_INSTRUCTION[31 : 24]; + assign _zz_338 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_339 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_340 = writeBack_MUL_LOW[31 : 0]; + assign _zz_341 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_342 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_343 = {5'd0, _zz_342}; + assign _zz_344 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_345 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_346 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_347 = {_zz_174,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_348 = _zz_349; + assign _zz_349 = _zz_350; + assign _zz_350 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_175) : _zz_175)} + _zz_352); + assign _zz_351 = memory_DivPlugin_div_needRevert; + assign _zz_352 = {32'd0, _zz_351}; + assign _zz_353 = _zz_177; + assign _zz_354 = {32'd0, _zz_353}; + assign _zz_355 = _zz_176; + assign _zz_356 = {31'd0, _zz_355}; + assign _zz_357 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_358 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_359 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_360 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_361 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_362 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_363 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_364 = (iBus_cmd_payload_address >>> 5); + assign _zz_365 = 1'b1; + assign _zz_366 = 1'b1; + assign _zz_367 = {_zz_66,_zz_65}; + assign _zz_368 = 32'h0000106f; + assign _zz_369 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_370 = 32'h00001073; + assign _zz_371 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_372 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_373 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_374) == 32'h00000003),{(_zz_375 == _zz_376),{_zz_377,{_zz_378,_zz_379}}}}}}; + assign _zz_374 = 32'h0000207f; + assign _zz_375 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_376 = 32'h00000003; + assign _zz_377 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_378 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_379 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_380) == 32'h00001013),{(_zz_381 == _zz_382),{_zz_383,{_zz_384,_zz_385}}}}}}; + assign _zz_380 = 32'hfc00307f; + assign _zz_381 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_382 = 32'h00005033; + assign _zz_383 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_384 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_385 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_386 = decode_INSTRUCTION[31]; + assign _zz_387 = decode_INSTRUCTION[31]; + assign _zz_388 = decode_INSTRUCTION[7]; + assign _zz_389 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_390 = 32'h02004020; + assign _zz_391 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_392 = (_zz_99 != 1'b0); + assign _zz_393 = (((decode_INSTRUCTION & _zz_395) == 32'h00000050) != 1'b0); + assign _zz_394 = {((_zz_396 == _zz_397) != 1'b0),{({_zz_398,_zz_399} != 2'b00),{(_zz_400 != _zz_401),{_zz_402,{_zz_403,_zz_404}}}}}; + assign _zz_395 = 32'h00203050; + assign _zz_396 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_397 = 32'h00000050; + assign _zz_398 = ((decode_INSTRUCTION & _zz_405) == 32'h00001050); + assign _zz_399 = ((decode_INSTRUCTION & _zz_406) == 32'h00002050); + assign _zz_400 = {_zz_98,(_zz_407 == _zz_408)}; + assign _zz_401 = 2'b00; + assign _zz_402 = ((_zz_409 == _zz_410) != 1'b0); + assign _zz_403 = ({_zz_411,_zz_412} != 2'b00); + assign _zz_404 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; + assign _zz_405 = 32'h00001050; + assign _zz_406 = 32'h00002050; + assign _zz_407 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_408 = 32'h00000004; + assign _zz_409 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_410 = 32'h00000040; + assign _zz_411 = ((decode_INSTRUCTION & _zz_418) == 32'h00005010); + assign _zz_412 = ((decode_INSTRUCTION & _zz_419) == 32'h00005020); + assign _zz_413 = {(_zz_420 == _zz_421),{_zz_422,_zz_423}}; + assign _zz_414 = 3'b000; + assign _zz_415 = ((_zz_424 == _zz_425) != 1'b0); + assign _zz_416 = (_zz_426 != 1'b0); + assign _zz_417 = {(_zz_427 != _zz_428),{_zz_429,{_zz_430,_zz_431}}}; + assign _zz_418 = 32'h00007034; + assign _zz_419 = 32'h02007064; + assign _zz_420 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_421 = 32'h40001010; + assign _zz_422 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_423 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_424 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_425 = 32'h00000024; + assign _zz_426 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_427 = ((decode_INSTRUCTION & _zz_432) == 32'h00002000); + assign _zz_428 = 1'b0; + assign _zz_429 = ({_zz_433,_zz_434} != 2'b00); + assign _zz_430 = ({_zz_435,_zz_436} != 3'b000); + assign _zz_431 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; + assign _zz_432 = 32'h00003000; + assign _zz_433 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_434 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_435 = _zz_99; + assign _zz_436 = {(_zz_442 == _zz_443),(_zz_444 == _zz_445)}; + assign _zz_437 = {(_zz_446 == _zz_447),{_zz_448,{_zz_449,_zz_450}}}; + assign _zz_438 = 5'h0; + assign _zz_439 = ((_zz_451 == _zz_452) != 1'b0); + assign _zz_440 = ({_zz_453,_zz_454} != 6'h0); + assign _zz_441 = {(_zz_455 != _zz_456),{_zz_457,{_zz_458,_zz_459}}}; + assign _zz_442 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_443 = 32'h00000020; + assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_445 = 32'h00000020; + assign _zz_446 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_447 = 32'h00002040; + assign _zz_448 = ((decode_INSTRUCTION & _zz_460) == 32'h00001040); + assign _zz_449 = (_zz_461 == _zz_462); + assign _zz_450 = {_zz_463,_zz_464}; + assign _zz_451 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_452 = 32'h00000020; + assign _zz_453 = (_zz_465 == _zz_466); + assign _zz_454 = {_zz_467,{_zz_468,_zz_469}}; + assign _zz_455 = {_zz_97,{_zz_470,_zz_471}}; + assign _zz_456 = 5'h0; + assign _zz_457 = ({_zz_472,_zz_473} != 6'h0); + assign _zz_458 = (_zz_474 != _zz_475); + assign _zz_459 = {_zz_476,{_zz_477,_zz_478}}; + assign _zz_460 = 32'h00001040; + assign _zz_461 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_462 = 32'h00000040; + assign _zz_463 = ((decode_INSTRUCTION & _zz_479) == 32'h00000040); + assign _zz_464 = ((decode_INSTRUCTION & _zz_480) == 32'h0); + assign _zz_465 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_466 = 32'h00000008; + assign _zz_467 = ((decode_INSTRUCTION & _zz_481) == 32'h00000040); + assign _zz_468 = _zz_97; + assign _zz_469 = {_zz_482,{_zz_483,_zz_484}}; + assign _zz_470 = (_zz_485 == _zz_486); + assign _zz_471 = {_zz_487,{_zz_488,_zz_489}}; + assign _zz_472 = _zz_98; + assign _zz_473 = {_zz_490,{_zz_491,_zz_492}}; + assign _zz_474 = {_zz_97,_zz_493}; + assign _zz_475 = 2'b00; + assign _zz_476 = ({_zz_494,_zz_495} != 2'b00); + assign _zz_477 = (_zz_496 != _zz_497); + assign _zz_478 = {_zz_498,{_zz_499,_zz_500}}; + assign _zz_479 = 32'h00400040; + assign _zz_480 = 32'h00000038; + assign _zz_481 = 32'h00000040; + assign _zz_482 = ((decode_INSTRUCTION & _zz_501) == 32'h00004020); + assign _zz_483 = (_zz_502 == _zz_503); + assign _zz_484 = (_zz_504 == _zz_505); + assign _zz_485 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_486 = 32'h00002010; + assign _zz_487 = ((decode_INSTRUCTION & _zz_506) == 32'h00000010); + assign _zz_488 = (_zz_507 == _zz_508); + assign _zz_489 = (_zz_509 == _zz_510); + assign _zz_490 = ((decode_INSTRUCTION & _zz_511) == 32'h00001010); + assign _zz_491 = (_zz_512 == _zz_513); + assign _zz_492 = {_zz_514,{_zz_515,_zz_516}}; + assign _zz_493 = ((decode_INSTRUCTION & _zz_517) == 32'h00000020); + assign _zz_494 = _zz_97; + assign _zz_495 = (_zz_518 == _zz_519); + assign _zz_496 = (_zz_520 == _zz_521); + assign _zz_497 = 1'b0; + assign _zz_498 = (_zz_522 != 1'b0); + assign _zz_499 = (_zz_523 != _zz_524); + assign _zz_500 = {_zz_525,{_zz_526,_zz_527}}; + assign _zz_501 = 32'h00004020; + assign _zz_502 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_503 = 32'h00000010; + assign _zz_504 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_505 = 32'h00000020; + assign _zz_506 = 32'h00001030; + assign _zz_507 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_508 = 32'h00002020; + assign _zz_509 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_510 = 32'h00000020; + assign _zz_511 = 32'h00001010; + assign _zz_512 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_513 = 32'h00002010; + assign _zz_514 = ((decode_INSTRUCTION & _zz_528) == 32'h00000010); + assign _zz_515 = (_zz_529 == _zz_530); + assign _zz_516 = (_zz_531 == _zz_532); + assign _zz_517 = 32'h00000070; + assign _zz_518 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_519 = 32'h0; + assign _zz_520 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_521 = 32'h00004010; + assign _zz_522 = ((decode_INSTRUCTION & _zz_533) == 32'h00002010); + assign _zz_523 = {_zz_534,{_zz_535,_zz_536}}; + assign _zz_524 = 4'b0000; + assign _zz_525 = (_zz_537 != 1'b0); + assign _zz_526 = (_zz_538 != _zz_539); + assign _zz_527 = {_zz_540,{_zz_541,_zz_542}}; + assign _zz_528 = 32'h00000050; + assign _zz_529 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_530 = 32'h00000004; + assign _zz_531 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_532 = 32'h0; + assign _zz_533 = 32'h00006014; + assign _zz_534 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_535 = ((decode_INSTRUCTION & _zz_543) == 32'h0); + assign _zz_536 = {(_zz_544 == _zz_545),(_zz_546 == _zz_547)}; + assign _zz_537 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_538 = {(_zz_548 == _zz_549),{_zz_550,_zz_551}}; + assign _zz_539 = 3'b000; + assign _zz_540 = ({_zz_552,_zz_96} != 2'b00); + assign _zz_541 = ({_zz_553,_zz_554} != 2'b00); + assign _zz_542 = (_zz_555 != 1'b0); + assign _zz_543 = 32'h00000018; + assign _zz_544 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_545 = 32'h00002000; + assign _zz_546 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_547 = 32'h00001000; + assign _zz_548 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_549 = 32'h00000040; + assign _zz_550 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_551 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_552 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_553 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_554 = _zz_96; + assign _zz_555 = ((decode_INSTRUCTION & 32'h00001054) == 32'h00001004); + assign _zz_556 = execute_INSTRUCTION[31]; + assign _zz_557 = execute_INSTRUCTION[31]; + assign _zz_558 = execute_INSTRUCTION[7]; + assign _zz_559 = 32'h0; + always @ (posedge clk) begin + if(_zz_365) begin + _zz_223 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_366) begin + _zz_224 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_48) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_214 ), //i + .io_cpu_prefetch_isValid (_zz_215 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_216 ), //i + .io_cpu_fetch_isStuck (_zz_217 ), //i + .io_cpu_fetch_isRemoved (_zz_218 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_219 ), //i + .io_cpu_decode_isStuck (_zz_220 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_221 ), //i + .io_cpu_fill_valid (_zz_222 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_367) + 2'b00 : begin + _zz_225 = CsrPlugin_jumpInterface_payload; + end + 2'b01 : begin + _zz_225 = DBusSimplePlugin_redoBranch_payload; + end + 2'b10 : begin + _zz_225 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_225 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_1) + `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; + default : _zz_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_2) + `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; + default : _zz_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_3) + `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; + default : _zz_10_string = "?????"; + endcase + end + always @(*) begin + case(_zz_11) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; + default : _zz_12_string = "????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; + default : _zz_17_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; + default : _zz_20_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(_zz_23) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(_zz_26) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; + default : _zz_26_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_29) + `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; + default : _zz_29_string = "????????????"; + endcase + end + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; + default : _zz_32_string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_36) + `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; + default : _zz_36_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_39) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; + default : _zz_39_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_40) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; + default : _zz_40_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_42) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; + default : _zz_42_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_43) + `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; + default : _zz_43_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_44) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; + default : _zz_44_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; + default : _zz_45_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; + default : _zz_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_50) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; + default : _zz_50_string = "?????"; + endcase + end + always @(*) begin + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; + endcase + end + always @(*) begin + case(_zz_52) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; + default : _zz_52_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_53) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; + default : _zz_53_string = "?????"; + endcase + end + always @(*) begin + case(_zz_54) + `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; + default : _zz_54_string = "???"; + endcase + end + always @(*) begin + case(_zz_55) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; + default : _zz_55_string = "????????"; + endcase + end + always @(*) begin + case(_zz_56) + `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; + default : _zz_56_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_58) + `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; + default : _zz_58_string = "????"; + endcase + end + always @(*) begin + case(_zz_101) + `Src1CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_101_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_101_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_101_string = "URS1 "; + default : _zz_101_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_102) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_102_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_102_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_102_string = "BITWISE "; + default : _zz_102_string = "????????"; + endcase + end + always @(*) begin + case(_zz_103) + `Src2CtrlEnum_defaultEncoding_RS : _zz_103_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_103_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_103_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_103_string = "PC "; + default : _zz_103_string = "???"; + endcase + end + always @(*) begin + case(_zz_104) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_104_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_104_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_104_string = "AND_1"; + default : _zz_104_string = "?????"; + endcase + end + always @(*) begin + case(_zz_105) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_105_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_105_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_105_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_105_string = "SRA_1 "; + default : _zz_105_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_106) + `BranchCtrlEnum_defaultEncoding_INC : _zz_106_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_106_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_106_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_106_string = "JALR"; + default : _zz_106_string = "????"; + endcase + end + always @(*) begin + case(_zz_107) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_107_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_107_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_107_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_107_string = "ECALL"; + default : _zz_107_string = "?????"; + endcase + end + always @(*) begin + case(_zz_108) + `Input2Kind_defaultEncoding_RS : _zz_108_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_108_string = "IMM_I"; + default : _zz_108_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_267) + $signed(_zz_275)); + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign execute_SHIFT_RIGHT = _zz_277; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_110; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_279[0]; + assign decode_IS_RS1_SIGNED = _zz_280[0]; + assign decode_IS_DIV = _zz_281[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_282[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; + assign _zz_2 = _zz_3; + assign decode_CfuPlugin_CFU_ENABLE = _zz_283[0]; + assign _zz_4 = _zz_5; + assign _zz_6 = _zz_7; + assign decode_ENV_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_IS_CSR = _zz_284[0]; + assign _zz_11 = _zz_12; + assign _zz_13 = _zz_14; + assign decode_SHIFT_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_ALU_BITWISE_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_SRC_LESS_UNSIGNED = _zz_285[0]; + assign decode_MEMORY_STORE = _zz_286[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_287[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_288[0]; + assign decode_SRC2_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_ALU_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_SRC1_CTRL = _zz_27; + assign _zz_28 = _zz_29; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + always @ (*) begin + _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck)begin + _zz_30 = 1'b0; + end + end + + always @ (*) begin + _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck)begin + _zz_31 = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_33; + assign execute_ENV_CTRL = _zz_34; + assign writeBack_ENV_CTRL = _zz_35; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_132; + assign execute_BRANCH_CTRL = _zz_36; + assign decode_RS2_USE = _zz_289[0]; + assign decode_RS1_USE = _zz_290[0]; + always @ (*) begin + _zz_37 = execute_REGFILE_WRITE_DATA; + if(_zz_226)begin + _zz_37 = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_121)begin + if((_zz_122 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_123; + end + end + if(_zz_227)begin + if(_zz_228)begin + if(_zz_125)begin + decode_RS2 = _zz_57; + end + end + end + if(_zz_229)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_127)begin + decode_RS2 = _zz_38; + end + end + end + if(_zz_230)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_129)begin + decode_RS2 = _zz_37; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_121)begin + if((_zz_122 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_123; + end + end + if(_zz_227)begin + if(_zz_228)begin + if(_zz_124)begin + decode_RS1 = _zz_57; + end + end + end + if(_zz_229)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_126)begin + decode_RS1 = _zz_38; + end + end + end + if(_zz_230)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_128)begin + decode_RS1 = _zz_37; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_38 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_38 = _zz_118; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_38 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_231)begin + _zz_38 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_39; + assign execute_SHIFT_CTRL = _zz_40; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_41 = execute_PC; + assign execute_SRC2_CTRL = _zz_42; + assign execute_SRC1_CTRL = _zz_43; + assign decode_SRC_USE_SUB_LESS = _zz_291[0]; + assign decode_SRC_ADD_ZERO = _zz_292[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_44; + assign execute_SRC2 = _zz_116; + assign execute_SRC1 = _zz_111; + assign execute_ALU_BITWISE_CTRL = _zz_45; + assign _zz_46 = writeBack_INSTRUCTION; + assign _zz_47 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_48 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_48 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_293[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_368) == 32'h00000003),{(_zz_369 == _zz_370),{_zz_371,{_zz_372,_zz_373}}}}}}} != 21'h0); + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + always @ (*) begin + _zz_57 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_57 = writeBack_DBusSimplePlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_266) + 2'b00 : begin + _zz_57 = _zz_340; + end + default : begin + _zz_57 = _zz_341; + end + endcase + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; + assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; + assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; + assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; + assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; + assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; + assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; + assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; + assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; + assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; + assign memory_PC = execute_to_memory_PC; + assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); + assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; + assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; + assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; + assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; + assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; + assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; + assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; + assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); + assign decode_MEMORY_ENABLE = _zz_294[0]; + assign decode_FLUSH_ALL = _zz_295[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_232)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_233)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_234)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_235)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_58; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_59 = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_59 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_60 = memory_FORMAL_PC_NEXT; + if(DBusSimplePlugin_redoBranch_valid)begin + _zz_60 = DBusSimplePlugin_redoBranch_payload; + end + end + + always @ (*) begin + _zz_61 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_61 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_119 || _zz_120)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_236)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_236)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_88)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_237)begin + if((! execute_CsrPlugin_wfiWake))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_226)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(_zz_238)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_238)begin + execute_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if((! memory_CfuPlugin_rsp_valid))begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_231)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(_zz_239)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushIt = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(_zz_239)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_240)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_241)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_240)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_241)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_237)begin + CsrPlugin_inWfi = 1'b1; + end + end + + assign CsrPlugin_thirdPartyWake = 1'b0; + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_240)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_241)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_240)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_241)begin + case(_zz_242) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; + assign _zz_63 = (_zz_62 & (~ _zz_296)); + assign _zz_64 = _zz_63[3]; + assign _zz_65 = (_zz_63[1] || _zz_64); + assign _zz_66 = (_zz_63[2] || _zz_64); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_225; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_298); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_69 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_69); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_69); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_70; + assign _zz_70 = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_71 = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_73)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_73 = _zz_74; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_73; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_75; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign _zz_76 = _zz_299[11]; + always @ (*) begin + _zz_77[18] = _zz_76; + _zz_77[17] = _zz_76; + _zz_77[16] = _zz_76; + _zz_77[15] = _zz_76; + _zz_77[14] = _zz_76; + _zz_77[13] = _zz_76; + _zz_77[12] = _zz_76; + _zz_77[11] = _zz_76; + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7] = _zz_76; + _zz_77[6] = _zz_76; + _zz_77[5] = _zz_76; + _zz_77[4] = _zz_76; + _zz_77[3] = _zz_76; + _zz_77[2] = _zz_76; + _zz_77[1] = _zz_76; + _zz_77[0] = _zz_76; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_300[31])); + if(_zz_82)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_78 = _zz_301[19]; + always @ (*) begin + _zz_79[10] = _zz_78; + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7] = _zz_78; + _zz_79[6] = _zz_78; + _zz_79[5] = _zz_78; + _zz_79[4] = _zz_78; + _zz_79[3] = _zz_78; + _zz_79[2] = _zz_78; + _zz_79[1] = _zz_78; + _zz_79[0] = _zz_78; + end + + assign _zz_80 = _zz_302[11]; + always @ (*) begin + _zz_81[18] = _zz_80; + _zz_81[17] = _zz_80; + _zz_81[16] = _zz_80; + _zz_81[15] = _zz_80; + _zz_81[14] = _zz_80; + _zz_81[13] = _zz_80; + _zz_81[12] = _zz_80; + _zz_81[11] = _zz_80; + _zz_81[10] = _zz_80; + _zz_81[9] = _zz_80; + _zz_81[8] = _zz_80; + _zz_81[7] = _zz_80; + _zz_81[6] = _zz_80; + _zz_81[5] = _zz_80; + _zz_81[4] = _zz_80; + _zz_81[3] = _zz_80; + _zz_81[2] = _zz_80; + _zz_81[1] = _zz_80; + _zz_81[0] = _zz_80; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_82 = _zz_303[1]; + end + default : begin + _zz_82 = _zz_304[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_83 = _zz_305[19]; + always @ (*) begin + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7] = _zz_83; + _zz_84[6] = _zz_83; + _zz_84[5] = _zz_83; + _zz_84[4] = _zz_83; + _zz_84[3] = _zz_83; + _zz_84[2] = _zz_83; + _zz_84[1] = _zz_83; + _zz_84[0] = _zz_83; + end + + assign _zz_85 = _zz_306[11]; + always @ (*) begin + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7] = _zz_85; + _zz_86[6] = _zz_85; + _zz_86[5] = _zz_85; + _zz_86[4] = _zz_85; + _zz_86[3] = _zz_85; + _zz_86[2] = _zz_85; + _zz_86[1] = _zz_85; + _zz_86[0] = _zz_85; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_386,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_387,_zz_388},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_215 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_216 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_217 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_216; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_221 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_235)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_233)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_222 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_233)begin + _zz_222 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_234)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_232)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_234)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_232)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_214 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_88 = 1'b0; + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_88)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_89 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_89 = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_89; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_90 = 4'b0001; + end + 2'b01 : begin + _zz_90 = 4'b0011; + end + default : begin + _zz_90 = 4'b1111; + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_90 <<< dBus_cmd_payload_address[1 : 0]); + assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; + assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; + assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + if(_zz_243)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_MMU_RSP2_refilling)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end else begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + end + if(_zz_244)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; + if(_zz_243)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_307}; + end + if(! memory_MMU_RSP2_refilling) begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); + end + end + end + + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; + always @ (*) begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + if(memory_MMU_RSP2_refilling)begin + DBusSimplePlugin_redoBranch_valid = 1'b1; + end + if(_zz_244)begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + end + end + + assign DBusSimplePlugin_redoBranch_payload = memory_PC; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_91 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_92[31] = _zz_91; + _zz_92[30] = _zz_91; + _zz_92[29] = _zz_91; + _zz_92[28] = _zz_91; + _zz_92[27] = _zz_91; + _zz_92[26] = _zz_91; + _zz_92[25] = _zz_91; + _zz_92[24] = _zz_91; + _zz_92[23] = _zz_91; + _zz_92[22] = _zz_91; + _zz_92[21] = _zz_91; + _zz_92[20] = _zz_91; + _zz_92[19] = _zz_91; + _zz_92[18] = _zz_91; + _zz_92[17] = _zz_91; + _zz_92[16] = _zz_91; + _zz_92[15] = _zz_91; + _zz_92[14] = _zz_91; + _zz_92[13] = _zz_91; + _zz_92[12] = _zz_91; + _zz_92[11] = _zz_91; + _zz_92[10] = _zz_91; + _zz_92[9] = _zz_91; + _zz_92[8] = _zz_91; + _zz_92[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_93 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_94[31] = _zz_93; + _zz_94[30] = _zz_93; + _zz_94[29] = _zz_93; + _zz_94[28] = _zz_93; + _zz_94[27] = _zz_93; + _zz_94[26] = _zz_93; + _zz_94[25] = _zz_93; + _zz_94[24] = _zz_93; + _zz_94[23] = _zz_93; + _zz_94[22] = _zz_93; + _zz_94[21] = _zz_93; + _zz_94[20] = _zz_93; + _zz_94[19] = _zz_93; + _zz_94[18] = _zz_93; + _zz_94[17] = _zz_93; + _zz_94[16] = _zz_93; + _zz_94[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_264) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_92; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_94; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusSimplePlugin_mmuBus_busy = 1'b0; + assign _zz_96 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_97 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_98 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_99 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_100 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_95 = {(_zz_100 != 1'b0),{(_zz_100 != 1'b0),{((_zz_389 == _zz_390) != 1'b0),{(_zz_391 != 1'b0),{1'b0,{_zz_392,{_zz_393,_zz_394}}}}}}}; + assign _zz_101 = _zz_95[2 : 1]; + assign _zz_56 = _zz_101; + assign _zz_102 = _zz_95[7 : 6]; + assign _zz_55 = _zz_102; + assign _zz_103 = _zz_95[9 : 8]; + assign _zz_54 = _zz_103; + assign _zz_104 = _zz_95[18 : 17]; + assign _zz_53 = _zz_104; + assign _zz_105 = _zz_95[21 : 20]; + assign _zz_52 = _zz_105; + assign _zz_106 = _zz_95[23 : 22]; + assign _zz_51 = _zz_106; + assign _zz_107 = _zz_95[26 : 25]; + assign _zz_50 = _zz_107; + assign _zz_108 = _zz_95[28 : 28]; + assign _zz_49 = _zz_108; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_223; + assign decode_RegFilePlugin_rs2Data = _zz_224; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); + if(_zz_109)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; + if(_zz_109)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_57; + if(_zz_109)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_110 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_110 = {31'd0, _zz_308}; + end + default : begin + _zz_110 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_111 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_111 = {29'd0, _zz_309}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_111 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_111 = {27'd0, _zz_310}; + end + endcase + end + + assign _zz_112 = _zz_311[11]; + always @ (*) begin + _zz_113[19] = _zz_112; + _zz_113[18] = _zz_112; + _zz_113[17] = _zz_112; + _zz_113[16] = _zz_112; + _zz_113[15] = _zz_112; + _zz_113[14] = _zz_112; + _zz_113[13] = _zz_112; + _zz_113[12] = _zz_112; + _zz_113[11] = _zz_112; + _zz_113[10] = _zz_112; + _zz_113[9] = _zz_112; + _zz_113[8] = _zz_112; + _zz_113[7] = _zz_112; + _zz_113[6] = _zz_112; + _zz_113[5] = _zz_112; + _zz_113[4] = _zz_112; + _zz_113[3] = _zz_112; + _zz_113[2] = _zz_112; + _zz_113[1] = _zz_112; + _zz_113[0] = _zz_112; + end + + assign _zz_114 = _zz_312[11]; + always @ (*) begin + _zz_115[19] = _zz_114; + _zz_115[18] = _zz_114; + _zz_115[17] = _zz_114; + _zz_115[16] = _zz_114; + _zz_115[15] = _zz_114; + _zz_115[14] = _zz_114; + _zz_115[13] = _zz_114; + _zz_115[12] = _zz_114; + _zz_115[11] = _zz_114; + _zz_115[10] = _zz_114; + _zz_115[9] = _zz_114; + _zz_115[8] = _zz_114; + _zz_115[7] = _zz_114; + _zz_115[6] = _zz_114; + _zz_115[5] = _zz_114; + _zz_115[4] = _zz_114; + _zz_115[3] = _zz_114; + _zz_115[2] = _zz_114; + _zz_115[1] = _zz_114; + _zz_115[0] = _zz_114; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_116 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_116 = {_zz_113,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_116 = {_zz_115,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_116 = _zz_41; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_313; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_117[0] = execute_SRC1[31]; + _zz_117[1] = execute_SRC1[30]; + _zz_117[2] = execute_SRC1[29]; + _zz_117[3] = execute_SRC1[28]; + _zz_117[4] = execute_SRC1[27]; + _zz_117[5] = execute_SRC1[26]; + _zz_117[6] = execute_SRC1[25]; + _zz_117[7] = execute_SRC1[24]; + _zz_117[8] = execute_SRC1[23]; + _zz_117[9] = execute_SRC1[22]; + _zz_117[10] = execute_SRC1[21]; + _zz_117[11] = execute_SRC1[20]; + _zz_117[12] = execute_SRC1[19]; + _zz_117[13] = execute_SRC1[18]; + _zz_117[14] = execute_SRC1[17]; + _zz_117[15] = execute_SRC1[16]; + _zz_117[16] = execute_SRC1[15]; + _zz_117[17] = execute_SRC1[14]; + _zz_117[18] = execute_SRC1[13]; + _zz_117[19] = execute_SRC1[12]; + _zz_117[20] = execute_SRC1[11]; + _zz_117[21] = execute_SRC1[10]; + _zz_117[22] = execute_SRC1[9]; + _zz_117[23] = execute_SRC1[8]; + _zz_117[24] = execute_SRC1[7]; + _zz_117[25] = execute_SRC1[6]; + _zz_117[26] = execute_SRC1[5]; + _zz_117[27] = execute_SRC1[4]; + _zz_117[28] = execute_SRC1[3]; + _zz_117[29] = execute_SRC1[2]; + _zz_117[30] = execute_SRC1[1]; + _zz_117[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_117 : execute_SRC1); + always @ (*) begin + _zz_118[0] = memory_SHIFT_RIGHT[31]; + _zz_118[1] = memory_SHIFT_RIGHT[30]; + _zz_118[2] = memory_SHIFT_RIGHT[29]; + _zz_118[3] = memory_SHIFT_RIGHT[28]; + _zz_118[4] = memory_SHIFT_RIGHT[27]; + _zz_118[5] = memory_SHIFT_RIGHT[26]; + _zz_118[6] = memory_SHIFT_RIGHT[25]; + _zz_118[7] = memory_SHIFT_RIGHT[24]; + _zz_118[8] = memory_SHIFT_RIGHT[23]; + _zz_118[9] = memory_SHIFT_RIGHT[22]; + _zz_118[10] = memory_SHIFT_RIGHT[21]; + _zz_118[11] = memory_SHIFT_RIGHT[20]; + _zz_118[12] = memory_SHIFT_RIGHT[19]; + _zz_118[13] = memory_SHIFT_RIGHT[18]; + _zz_118[14] = memory_SHIFT_RIGHT[17]; + _zz_118[15] = memory_SHIFT_RIGHT[16]; + _zz_118[16] = memory_SHIFT_RIGHT[15]; + _zz_118[17] = memory_SHIFT_RIGHT[14]; + _zz_118[18] = memory_SHIFT_RIGHT[13]; + _zz_118[19] = memory_SHIFT_RIGHT[12]; + _zz_118[20] = memory_SHIFT_RIGHT[11]; + _zz_118[21] = memory_SHIFT_RIGHT[10]; + _zz_118[22] = memory_SHIFT_RIGHT[9]; + _zz_118[23] = memory_SHIFT_RIGHT[8]; + _zz_118[24] = memory_SHIFT_RIGHT[7]; + _zz_118[25] = memory_SHIFT_RIGHT[6]; + _zz_118[26] = memory_SHIFT_RIGHT[5]; + _zz_118[27] = memory_SHIFT_RIGHT[4]; + _zz_118[28] = memory_SHIFT_RIGHT[3]; + _zz_118[29] = memory_SHIFT_RIGHT[2]; + _zz_118[30] = memory_SHIFT_RIGHT[1]; + _zz_118[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_119 = 1'b0; + if(_zz_245)begin + if(_zz_246)begin + if(_zz_124)begin + _zz_119 = 1'b1; + end + end + end + if(_zz_247)begin + if(_zz_248)begin + if(_zz_126)begin + _zz_119 = 1'b1; + end + end + end + if(_zz_249)begin + if(_zz_250)begin + if(_zz_128)begin + _zz_119 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_119 = 1'b0; + end + end + + always @ (*) begin + _zz_120 = 1'b0; + if(_zz_245)begin + if(_zz_246)begin + if(_zz_125)begin + _zz_120 = 1'b1; + end + end + end + if(_zz_247)begin + if(_zz_248)begin + if(_zz_127)begin + _zz_120 = 1'b1; + end + end + end + if(_zz_249)begin + if(_zz_250)begin + if(_zz_129)begin + _zz_120 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_120 = 1'b0; + end + end + + assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_125 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_127 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_129 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_130 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_130 == 3'b000)) begin + _zz_131 = execute_BranchPlugin_eq; + end else if((_zz_130 == 3'b001)) begin + _zz_131 = (! execute_BranchPlugin_eq); + end else if((((_zz_130 & 3'b101) == 3'b101))) begin + _zz_131 = (! execute_SRC_LESS); + end else begin + _zz_131 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_132 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_132 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_132 = 1'b1; + end + default : begin + _zz_132 = _zz_131; + end + endcase + end + + assign _zz_133 = _zz_320[11]; + always @ (*) begin + _zz_134[19] = _zz_133; + _zz_134[18] = _zz_133; + _zz_134[17] = _zz_133; + _zz_134[16] = _zz_133; + _zz_134[15] = _zz_133; + _zz_134[14] = _zz_133; + _zz_134[13] = _zz_133; + _zz_134[12] = _zz_133; + _zz_134[11] = _zz_133; + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; + end + + assign _zz_135 = _zz_321[19]; + always @ (*) begin + _zz_136[10] = _zz_135; + _zz_136[9] = _zz_135; + _zz_136[8] = _zz_135; + _zz_136[7] = _zz_135; + _zz_136[6] = _zz_135; + _zz_136[5] = _zz_135; + _zz_136[4] = _zz_135; + _zz_136[3] = _zz_135; + _zz_136[2] = _zz_135; + _zz_136[1] = _zz_135; + _zz_136[0] = _zz_135; + end + + assign _zz_137 = _zz_322[11]; + always @ (*) begin + _zz_138[18] = _zz_137; + _zz_138[17] = _zz_137; + _zz_138[16] = _zz_137; + _zz_138[15] = _zz_137; + _zz_138[14] = _zz_137; + _zz_138[13] = _zz_137; + _zz_138[12] = _zz_137; + _zz_138[11] = _zz_137; + _zz_138[10] = _zz_137; + _zz_138[9] = _zz_137; + _zz_138[8] = _zz_137; + _zz_138[7] = _zz_137; + _zz_138[6] = _zz_137; + _zz_138[5] = _zz_137; + _zz_138[4] = _zz_137; + _zz_138[3] = _zz_137; + _zz_138[2] = _zz_137; + _zz_138[1] = _zz_137; + _zz_138[0] = _zz_137; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_139 = (_zz_323[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_139 = _zz_324[1]; + end + default : begin + _zz_139 = _zz_325[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_139); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_140 = _zz_326[11]; + always @ (*) begin + _zz_141[19] = _zz_140; + _zz_141[18] = _zz_140; + _zz_141[17] = _zz_140; + _zz_141[16] = _zz_140; + _zz_141[15] = _zz_140; + _zz_141[14] = _zz_140; + _zz_141[13] = _zz_140; + _zz_141[12] = _zz_140; + _zz_141[11] = _zz_140; + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_141,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_143,{{{_zz_556,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_145,{{{_zz_557,_zz_558},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_329}; + end + end + endcase + end + + assign _zz_142 = _zz_327[19]; + always @ (*) begin + _zz_143[10] = _zz_142; + _zz_143[9] = _zz_142; + _zz_143[8] = _zz_142; + _zz_143[7] = _zz_142; + _zz_143[6] = _zz_142; + _zz_143[5] = _zz_142; + _zz_143[4] = _zz_142; + _zz_143[3] = _zz_142; + _zz_143[2] = _zz_142; + _zz_143[1] = _zz_142; + _zz_143[0] = _zz_142; + end + + assign _zz_144 = _zz_328[11]; + always @ (*) begin + _zz_145[18] = _zz_144; + _zz_145[17] = _zz_144; + _zz_145[16] = _zz_144; + _zz_145[15] = _zz_144; + _zz_145[14] = _zz_144; + _zz_145[13] = _zz_144; + _zz_145[12] = _zz_144; + _zz_145[11] = _zz_144; + _zz_145[10] = _zz_144; + _zz_145[9] = _zz_144; + _zz_145[8] = _zz_144; + _zz_145[7] = _zz_144; + _zz_145[6] = _zz_144; + _zz_145[5] = _zz_144; + _zz_145[4] = _zz_144; + _zz_145[3] = _zz_144; + _zz_145[2] = _zz_144; + _zz_145[1] = _zz_144; + _zz_145[0] = _zz_144; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_146 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_147 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_148 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_149 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_150 = _zz_330[0]; + assign _zz_151 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_152 = _zz_332[0]; + assign _zz_153 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_154 = _zz_334[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_236)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_238)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(_zz_239)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2820)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2822)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2824)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2826)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2828)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2830)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_251)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_252)begin + CsrPlugin_selfException_valid = 1'b1; + end + if(_zz_253)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_252)begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(_zz_253)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_251)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_251)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_265) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign execute_CfuPlugin_functionsIds_0 = _zz_336; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_171 = _zz_337[7]; + always @ (*) begin + _zz_172[23] = _zz_171; + _zz_172[22] = _zz_171; + _zz_172[21] = _zz_171; + _zz_172[20] = _zz_171; + _zz_172[19] = _zz_171; + _zz_172[18] = _zz_171; + _zz_172[17] = _zz_171; + _zz_172[16] = _zz_171; + _zz_172[15] = _zz_171; + _zz_172[14] = _zz_171; + _zz_172[13] = _zz_171; + _zz_172[12] = _zz_171; + _zz_172[11] = _zz_171; + _zz_172[10] = _zz_171; + _zz_172[9] = _zz_171; + _zz_172[8] = _zz_171; + _zz_172[7] = _zz_171; + _zz_172[6] = _zz_171; + _zz_172[5] = _zz_171; + _zz_172[4] = _zz_171; + _zz_172[3] = _zz_171; + _zz_172[2] = _zz_171; + _zz_172[1] = _zz_171; + _zz_172[0] = _zz_171; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : begin + _zz_173 = execute_RS2; + end + default : begin + _zz_173 = {_zz_172,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_173; + assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); + assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); + assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @ (*) begin + CfuPlugin_joinException_valid = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if(memory_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); + end + end + end + + assign CfuPlugin_joinException_payload_code = 4'b1111; + assign CfuPlugin_joinException_payload_badAddr = 32'h0; + always @ (*) begin + memory_CfuPlugin_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_254) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_254) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_338) + $signed(_zz_339)); + assign memory_DivPlugin_frontendOk = 1'b1; + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_231)begin + if(_zz_255)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_256)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_343); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_174 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_174[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_344); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_345 : _zz_346); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_347[31:0]; + assign _zz_175 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_176 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_177 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_178[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_178[31 : 0] = execute_RS1; + end + + assign _zz_180 = (_zz_179 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_180 != 32'h0); + assign _zz_29 = decode_SRC1_CTRL; + assign _zz_27 = _zz_56; + assign _zz_43 = decode_to_execute_SRC1_CTRL; + assign _zz_26 = decode_ALU_CTRL; + assign _zz_24 = _zz_55; + assign _zz_44 = decode_to_execute_ALU_CTRL; + assign _zz_23 = decode_SRC2_CTRL; + assign _zz_21 = _zz_54; + assign _zz_42 = decode_to_execute_SRC2_CTRL; + assign _zz_20 = decode_ALU_BITWISE_CTRL; + assign _zz_18 = _zz_53; + assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_17 = decode_SHIFT_CTRL; + assign _zz_14 = execute_SHIFT_CTRL; + assign _zz_15 = _zz_52; + assign _zz_40 = decode_to_execute_SHIFT_CTRL; + assign _zz_39 = execute_to_memory_SHIFT_CTRL; + assign _zz_12 = decode_BRANCH_CTRL; + assign _zz_58 = _zz_51; + assign _zz_36 = decode_to_execute_BRANCH_CTRL; + assign _zz_10 = decode_ENV_CTRL; + assign _zz_7 = execute_ENV_CTRL; + assign _zz_5 = memory_ENV_CTRL; + assign _zz_8 = _zz_50; + assign _zz_34 = decode_to_execute_ENV_CTRL; + assign _zz_33 = execute_to_memory_ENV_CTRL; + assign _zz_35 = memory_to_writeBack_ENV_CTRL; + assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_1 = _zz_49; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_181[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_182[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_183[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_184 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_184[31 : 30] = CsrPlugin_misa_base; + _zz_184[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_185 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_186 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_186[11 : 11] = CsrPlugin_mip_MEIP; + _zz_186[7 : 7] = CsrPlugin_mip_MTIP; + _zz_186[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_187 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_187[11 : 11] = CsrPlugin_mie_MEIE; + _zz_187[7 : 7] = CsrPlugin_mie_MTIE; + _zz_187[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_188 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_188[31 : 2] = CsrPlugin_mtvec_base; + _zz_188[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_189 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_189[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_190 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_190[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_191 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_192 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_192[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_193 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_194 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_195 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_196 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_197 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_198 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_199 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_200 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_201 = 32'h0; + if(execute_CsrPlugin_csr_2820)begin + _zz_201[31 : 0] = _zz_155; + end + end + + always @ (*) begin + _zz_202 = 32'h0; + if(execute_CsrPlugin_csr_2822)begin + _zz_202[31 : 0] = _zz_157; + end + end + + always @ (*) begin + _zz_203 = 32'h0; + if(execute_CsrPlugin_csr_2824)begin + _zz_203[31 : 0] = _zz_159; + end + end + + always @ (*) begin + _zz_204 = 32'h0; + if(execute_CsrPlugin_csr_2826)begin + _zz_204[31 : 0] = _zz_161; + end + end + + always @ (*) begin + _zz_205 = 32'h0; + if(execute_CsrPlugin_csr_2828)begin + _zz_205[31 : 0] = _zz_163; + end + end + + always @ (*) begin + _zz_206 = 32'h0; + if(execute_CsrPlugin_csr_2830)begin + _zz_206[31 : 0] = _zz_165; + end + end + + always @ (*) begin + _zz_207 = 32'h0; + if(execute_CsrPlugin_csr_2832)begin + _zz_207[31 : 0] = _zz_167; + end + end + + always @ (*) begin + _zz_208 = 32'h0; + if(execute_CsrPlugin_csr_2834)begin + _zz_208[31 : 0] = _zz_169; + end + end + + always @ (*) begin + _zz_209 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_209[31 : 0] = _zz_179; + end + end + + always @ (*) begin + _zz_210 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_210[31 : 0] = _zz_180; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_181 | _zz_182) | (_zz_183 | _zz_559)) | ((_zz_184 | _zz_185) | (_zz_186 | _zz_187))) | (((_zz_188 | _zz_189) | (_zz_190 | _zz_191)) | ((_zz_192 | _zz_193) | (_zz_194 | _zz_195)))) | ((((_zz_196 | _zz_197) | (_zz_198 | _zz_199)) | ((_zz_200 | _zz_201) | (_zz_202 | _zz_203))) | (((_zz_204 | _zz_205) | (_zz_206 | _zz_207)) | ((_zz_208 | _zz_209) | _zz_210)))); + assign iBusWishbone_ADR = {_zz_364,_zz_211}; + assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'h0; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_257)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_257)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_212; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = 3'b000; + assign dBusWishbone_BTE = 2'b00; + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_213 = 4'b0001; + end + 2'b01 : begin + _zz_213 = 4'b0011; + end + default : begin + _zz_213 = 4'b1111; + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = (_zz_213 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = 4'b1111; + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_72 <= 1'b0; + _zz_74 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_87; + IBusCachedPlugin_rspCounter <= 32'h0; + _zz_109 <= 1'b1; + _zz_121 <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_CfuPlugin_hold <= 1'b0; + execute_CfuPlugin_fired <= 1'b0; + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_179 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; + _zz_211 <= 3'b000; + _zz_212 <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_72 <= 1'b0; + end + if(_zz_70)begin + _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_74 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_74 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + _zz_109 <= 1'b0; + _zz_121 <= (_zz_47 && writeBack_arbitration_isFiring); + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_258)begin + if(_zz_259)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_260)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_261)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_240)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_241)begin + case(_zz_242) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_148,{_zz_147,_zz_146}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(execute_CfuPlugin_schedule)begin + execute_CfuPlugin_hold <= 1'b1; + end + if(CfuPlugin_bus_cmd_ready)begin + execute_CfuPlugin_hold <= 1'b0; + end + if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + execute_CfuPlugin_fired <= 1'b1; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_CfuPlugin_fired <= 1'b0; + end + if(memory_CfuPlugin_rsp_ready)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + end + if(_zz_262)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + end + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! memory_arbitration_isStuck))begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_357[0]; + CsrPlugin_mstatus_MIE <= _zz_358[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_360[0]; + CsrPlugin_mie_MTIE <= _zz_361[0]; + CsrPlugin_mie_MSIE <= _zz_362[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_179 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_257)begin + if(iBusWishbone_ACK)begin + _zz_211 <= (_zz_211 + 3'b001); + end + end + _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_263)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_75 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + _zz_122 <= _zz_46[11 : 7]; + _zz_123 <= _zz_57; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_236)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_238)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_154 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_154 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + end + if(_zz_239)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_152 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_152 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + end + if(_zz_258)begin + if(_zz_259)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_260)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_261)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_240)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(_zz_156[0])begin + _zz_155 <= (_zz_155 + 32'h00000001); + end + if(_zz_158[0])begin + _zz_157 <= (_zz_157 + 32'h00000001); + end + if(_zz_160[0])begin + _zz_159 <= (_zz_159 + 32'h00000001); + end + if(_zz_162[0])begin + _zz_161 <= (_zz_161 + 32'h00000001); + end + if(_zz_164[0])begin + _zz_163 <= (_zz_163 + 32'h00000001); + end + if(_zz_166[0])begin + _zz_165 <= (_zz_165 + 32'h00000001); + end + if(_zz_168[0])begin + _zz_167 <= (_zz_167 + 32'h00000001); + end + if(_zz_170[0])begin + _zz_169 <= (_zz_169 + 32'h00000001); + end + if(_zz_262)begin + CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_231)begin + if(_zz_255)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_348[31:0]; + end + end + end + if(_zz_256)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_177 ? (~ _zz_178) : _zz_178) + _zz_354); + memory_DivPlugin_rs2 <= ((_zz_176 ? (~ execute_RS2) : execute_RS2) + _zz_356); + memory_DivPlugin_div_needRevert <= ((_zz_177 ^ (_zz_176 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_41; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_61; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_60; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_28; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_16; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_13; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; + execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; + execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; + execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; + execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; + execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; + execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; + execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; + execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_359[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_363[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_169 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_170 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_263)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_9; + reg [22:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [22:0] _zz_15; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [8:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [8:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; + + assign _zz_11 = (! lineLoader_flushCounter[6]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_3 <= lineLoader_flushCounter[6]; + if(_zz_12)begin + lineLoader_flushCounter <= 7'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml new file mode 100644 index 0000000..b55f8e5 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml @@ -0,0 +1,4 @@ +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v new file mode 100644 index 0000000..d92c012 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v @@ -0,0 +1,6308 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : c8881985e0b323f1b12cab3ed0bd455d6c406944 + + +`define Input2Kind_defaultEncoding_type [0:0] +`define Input2Kind_defaultEncoding_RS 1'b0 +`define Input2Kind_defaultEncoding_IMM_I 1'b1 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv_inner ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input CfuPlugin_bus_rsp_payload_response_ok, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_216; + wire _zz_217; + wire _zz_218; + wire _zz_219; + wire _zz_220; + wire _zz_221; + wire _zz_222; + wire _zz_223; + reg _zz_224; + reg [31:0] _zz_225; + reg [31:0] _zz_226; + reg [31:0] _zz_227; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire _zz_245; + wire _zz_246; + wire [1:0] _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire _zz_255; + wire _zz_256; + wire _zz_257; + wire _zz_258; + wire [1:0] _zz_259; + wire _zz_260; + wire _zz_261; + wire [5:0] _zz_262; + wire _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire _zz_269; + wire [1:0] _zz_270; + wire _zz_271; + wire [1:0] _zz_272; + wire [51:0] _zz_273; + wire [51:0] _zz_274; + wire [51:0] _zz_275; + wire [32:0] _zz_276; + wire [51:0] _zz_277; + wire [49:0] _zz_278; + wire [51:0] _zz_279; + wire [49:0] _zz_280; + wire [51:0] _zz_281; + wire [32:0] _zz_282; + wire [31:0] _zz_283; + wire [32:0] _zz_284; + wire [0:0] _zz_285; + wire [0:0] _zz_286; + wire [0:0] _zz_287; + wire [0:0] _zz_288; + wire [0:0] _zz_289; + wire [0:0] _zz_290; + wire [0:0] _zz_291; + wire [0:0] _zz_292; + wire [0:0] _zz_293; + wire [0:0] _zz_294; + wire [0:0] _zz_295; + wire [0:0] _zz_296; + wire [0:0] _zz_297; + wire [0:0] _zz_298; + wire [0:0] _zz_299; + wire [0:0] _zz_300; + wire [0:0] _zz_301; + wire [0:0] _zz_302; + wire [3:0] _zz_303; + wire [2:0] _zz_304; + wire [31:0] _zz_305; + wire [11:0] _zz_306; + wire [31:0] _zz_307; + wire [19:0] _zz_308; + wire [11:0] _zz_309; + wire [31:0] _zz_310; + wire [31:0] _zz_311; + wire [19:0] _zz_312; + wire [11:0] _zz_313; + wire [2:0] _zz_314; + wire [0:0] _zz_315; + wire [2:0] _zz_316; + wire [4:0] _zz_317; + wire [11:0] _zz_318; + wire [11:0] _zz_319; + wire [31:0] _zz_320; + wire [31:0] _zz_321; + wire [31:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [31:0] _zz_326; + wire [11:0] _zz_327; + wire [19:0] _zz_328; + wire [11:0] _zz_329; + wire [31:0] _zz_330; + wire [31:0] _zz_331; + wire [31:0] _zz_332; + wire [11:0] _zz_333; + wire [19:0] _zz_334; + wire [11:0] _zz_335; + wire [2:0] _zz_336; + wire [1:0] _zz_337; + wire [1:0] _zz_338; + wire [1:0] _zz_339; + wire [1:0] _zz_340; + wire [1:0] _zz_341; + wire [1:0] _zz_342; + wire [9:0] _zz_343; + wire [7:0] _zz_344; + wire [65:0] _zz_345; + wire [65:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; + wire [0:0] _zz_349; + wire [5:0] _zz_350; + wire [32:0] _zz_351; + wire [31:0] _zz_352; + wire [31:0] _zz_353; + wire [32:0] _zz_354; + wire [32:0] _zz_355; + wire [32:0] _zz_356; + wire [32:0] _zz_357; + wire [0:0] _zz_358; + wire [32:0] _zz_359; + wire [0:0] _zz_360; + wire [32:0] _zz_361; + wire [0:0] _zz_362; + wire [31:0] _zz_363; + wire [0:0] _zz_364; + wire [0:0] _zz_365; + wire [0:0] _zz_366; + wire [0:0] _zz_367; + wire [0:0] _zz_368; + wire [0:0] _zz_369; + wire [0:0] _zz_370; + wire [26:0] _zz_371; + wire _zz_372; + wire _zz_373; + wire [1:0] _zz_374; + wire [31:0] _zz_375; + wire [31:0] _zz_376; + wire [31:0] _zz_377; + wire _zz_378; + wire [0:0] _zz_379; + wire [13:0] _zz_380; + wire [31:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire _zz_384; + wire [0:0] _zz_385; + wire [7:0] _zz_386; + wire [31:0] _zz_387; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire _zz_390; + wire [0:0] _zz_391; + wire [1:0] _zz_392; + wire _zz_393; + wire _zz_394; + wire _zz_395; + wire [31:0] _zz_396; + wire [0:0] _zz_397; + wire [0:0] _zz_398; + wire _zz_399; + wire [0:0] _zz_400; + wire [27:0] _zz_401; + wire [0:0] _zz_402; + wire [0:0] _zz_403; + wire [0:0] _zz_404; + wire [0:0] _zz_405; + wire _zz_406; + wire [0:0] _zz_407; + wire [22:0] _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire [31:0] _zz_411; + wire _zz_412; + wire _zz_413; + wire [0:0] _zz_414; + wire [0:0] _zz_415; + wire [0:0] _zz_416; + wire [0:0] _zz_417; + wire _zz_418; + wire [0:0] _zz_419; + wire [19:0] _zz_420; + wire [31:0] _zz_421; + wire [31:0] _zz_422; + wire _zz_423; + wire _zz_424; + wire [0:0] _zz_425; + wire [1:0] _zz_426; + wire [0:0] _zz_427; + wire [0:0] _zz_428; + wire _zz_429; + wire [0:0] _zz_430; + wire [16:0] _zz_431; + wire [31:0] _zz_432; + wire [31:0] _zz_433; + wire [31:0] _zz_434; + wire [31:0] _zz_435; + wire [31:0] _zz_436; + wire [31:0] _zz_437; + wire [31:0] _zz_438; + wire [31:0] _zz_439; + wire _zz_440; + wire [1:0] _zz_441; + wire [1:0] _zz_442; + wire _zz_443; + wire [0:0] _zz_444; + wire [13:0] _zz_445; + wire [31:0] _zz_446; + wire [31:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire [0:0] _zz_450; + wire [0:0] _zz_451; + wire [0:0] _zz_452; + wire [3:0] _zz_453; + wire [0:0] _zz_454; + wire [0:0] _zz_455; + wire _zz_456; + wire [0:0] _zz_457; + wire [10:0] _zz_458; + wire [31:0] _zz_459; + wire [31:0] _zz_460; + wire [31:0] _zz_461; + wire [31:0] _zz_462; + wire [31:0] _zz_463; + wire _zz_464; + wire [0:0] _zz_465; + wire [0:0] _zz_466; + wire [31:0] _zz_467; + wire _zz_468; + wire [0:0] _zz_469; + wire [3:0] _zz_470; + wire [0:0] _zz_471; + wire [3:0] _zz_472; + wire [5:0] _zz_473; + wire [5:0] _zz_474; + wire _zz_475; + wire [0:0] _zz_476; + wire [7:0] _zz_477; + wire [31:0] _zz_478; + wire [31:0] _zz_479; + wire [31:0] _zz_480; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire [0:0] _zz_486; + wire [1:0] _zz_487; + wire _zz_488; + wire [0:0] _zz_489; + wire [1:0] _zz_490; + wire [0:0] _zz_491; + wire [3:0] _zz_492; + wire [0:0] _zz_493; + wire [0:0] _zz_494; + wire [1:0] _zz_495; + wire [1:0] _zz_496; + wire _zz_497; + wire [0:0] _zz_498; + wire [5:0] _zz_499; + wire [31:0] _zz_500; + wire [31:0] _zz_501; + wire _zz_502; + wire _zz_503; + wire [31:0] _zz_504; + wire [31:0] _zz_505; + wire [31:0] _zz_506; + wire _zz_507; + wire _zz_508; + wire [31:0] _zz_509; + wire [31:0] _zz_510; + wire _zz_511; + wire [0:0] _zz_512; + wire [1:0] _zz_513; + wire [31:0] _zz_514; + wire [31:0] _zz_515; + wire _zz_516; + wire _zz_517; + wire [0:0] _zz_518; + wire [0:0] _zz_519; + wire _zz_520; + wire [0:0] _zz_521; + wire [3:0] _zz_522; + wire [31:0] _zz_523; + wire [31:0] _zz_524; + wire [31:0] _zz_525; + wire [31:0] _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; + wire [31:0] _zz_529; + wire _zz_530; + wire _zz_531; + wire [31:0] _zz_532; + wire [31:0] _zz_533; + wire [31:0] _zz_534; + wire [31:0] _zz_535; + wire [0:0] _zz_536; + wire [2:0] _zz_537; + wire [0:0] _zz_538; + wire [0:0] _zz_539; + wire _zz_540; + wire [0:0] _zz_541; + wire [1:0] _zz_542; + wire [31:0] _zz_543; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire _zz_546; + wire _zz_547; + wire [31:0] _zz_548; + wire _zz_549; + wire [0:0] _zz_550; + wire [0:0] _zz_551; + wire [0:0] _zz_552; + wire [0:0] _zz_553; + wire [1:0] _zz_554; + wire [1:0] _zz_555; + wire [0:0] _zz_556; + wire [0:0] _zz_557; + wire [31:0] _zz_558; + wire [31:0] _zz_559; + wire [31:0] _zz_560; + wire [31:0] _zz_561; + wire [31:0] _zz_562; + wire [31:0] _zz_563; + wire _zz_564; + wire _zz_565; + wire _zz_566; + wire [31:0] _zz_567; + wire [51:0] memory_MUL_LOW; + wire [31:0] memory_MEMORY_READ_DATA; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_1; + wire `Input2Kind_defaultEncoding_type _zz_2; + wire `Input2Kind_defaultEncoding_type _zz_3; + wire decode_CfuPlugin_CFU_ENABLE; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `AluCtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + reg _zz_30; + reg _zz_31; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_32; + wire execute_CfuPlugin_CFU_ENABLE; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_37; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_38; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_41; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; + wire [31:0] _zz_46; + wire _zz_47; + reg _zz_48; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `Input2Kind_defaultEncoding_type _zz_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; + wire `Src2CtrlEnum_defaultEncoding_type _zz_54; + wire `AluCtrlEnum_defaultEncoding_type _zz_55; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_57; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP2_physicalAddress; + wire memory_MMU_RSP2_isIoAccess; + wire memory_MMU_RSP2_isPaging; + wire memory_MMU_RSP2_allowRead; + wire memory_MMU_RSP2_allowWrite; + wire memory_MMU_RSP2_allowExecute; + wire memory_MMU_RSP2_exception; + wire memory_MMU_RSP2_refilling; + wire memory_MMU_RSP2_bypassTranslation; + wire [31:0] memory_PC; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire execute_MMU_FAULT; + wire [31:0] execute_MMU_RSP2_physicalAddress; + wire execute_MMU_RSP2_isIoAccess; + wire execute_MMU_RSP2_isPaging; + wire execute_MMU_RSP2_allowRead; + wire execute_MMU_RSP2_allowWrite; + wire execute_MMU_RSP2_allowExecute; + wire execute_MMU_RSP2_exception; + wire execute_MMU_RSP2_refilling; + wire execute_MMU_RSP2_bypassTranslation; + wire [31:0] execute_SRC_ADD; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_59; + reg [31:0] _zz_60; + reg [31:0] _zz_61; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire DBusSimplePlugin_mmuBus_cmd_0_isValid; + wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire DBusSimplePlugin_mmuBus_rsp_isPaging; + wire DBusSimplePlugin_mmuBus_rsp_allowRead; + wire DBusSimplePlugin_mmuBus_rsp_allowWrite; + wire DBusSimplePlugin_mmuBus_rsp_allowExecute; + wire DBusSimplePlugin_mmuBus_rsp_exception; + wire DBusSimplePlugin_mmuBus_rsp_refilling; + wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire DBusSimplePlugin_mmuBus_end; + wire DBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_redoBranch_valid; + wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CfuPlugin_joinException_valid; + wire [3:0] CfuPlugin_joinException_payload_code; + wire [31:0] CfuPlugin_joinException_payload_badAddr; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_62; + wire [3:0] _zz_63; + wire _zz_64; + wire _zz_65; + wire _zz_66; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_67; + wire _zz_68; + wire _zz_69; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_70; + wire _zz_71; + reg _zz_72; + wire _zz_73; + reg _zz_74; + reg [31:0] _zz_75; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_76; + reg [18:0] _zz_77; + wire _zz_78; + reg [10:0] _zz_79; + wire _zz_80; + reg [18:0] _zz_81; + reg _zz_82; + wire _zz_83; + reg [10:0] _zz_84; + wire _zz_85; + reg [18:0] _zz_86; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_87; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire _zz_88; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_89; + reg [3:0] _zz_90; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_91; + reg [31:0] _zz_92; + wire _zz_93; + reg [31:0] _zz_94; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [33:0] _zz_95; + wire _zz_96; + wire _zz_97; + wire _zz_98; + wire _zz_99; + wire _zz_100; + wire `Src1CtrlEnum_defaultEncoding_type _zz_101; + wire `AluCtrlEnum_defaultEncoding_type _zz_102; + wire `Src2CtrlEnum_defaultEncoding_type _zz_103; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_104; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_105; + wire `BranchCtrlEnum_defaultEncoding_type _zz_106; + wire `EnvCtrlEnum_defaultEncoding_type _zz_107; + wire `Input2Kind_defaultEncoding_type _zz_108; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_109; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_110; + reg [31:0] _zz_111; + wire _zz_112; + reg [19:0] _zz_113; + wire _zz_114; + reg [19:0] _zz_115; + reg [31:0] _zz_116; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_117; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_118; + reg _zz_119; + reg _zz_120; + reg _zz_121; + reg [4:0] _zz_122; + reg [31:0] _zz_123; + wire _zz_124; + wire _zz_125; + wire _zz_126; + wire _zz_127; + wire _zz_128; + wire _zz_129; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_130; + reg _zz_131; + reg _zz_132; + wire _zz_133; + reg [19:0] _zz_134; + wire _zz_135; + reg [10:0] _zz_136; + wire _zz_137; + reg [18:0] _zz_138; + reg _zz_139; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_140; + reg [19:0] _zz_141; + wire _zz_142; + reg [10:0] _zz_143; + wire _zz_144; + reg [18:0] _zz_145; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_146; + wire _zz_147; + wire _zz_148; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_149; + wire _zz_150; + wire [1:0] _zz_151; + wire _zz_152; + wire [1:0] _zz_153; + wire _zz_154; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_171; + reg [23:0] _zz_172; + reg [31:0] _zz_173; + wire memory_CfuPlugin_rsp_valid; + reg memory_CfuPlugin_rsp_ready; + wire memory_CfuPlugin_rsp_payload_response_ok; + wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_s2mPipe_rValid; + reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_174; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_175; + wire _zz_176; + wire _zz_177; + reg [32:0] _zz_178; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_179; + wire [31:0] _zz_180; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_181; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; + reg execute_to_memory_MMU_RSP2_isIoAccess; + reg execute_to_memory_MMU_RSP2_isPaging; + reg execute_to_memory_MMU_RSP2_allowRead; + reg execute_to_memory_MMU_RSP2_allowWrite; + reg execute_to_memory_MMU_RSP2_allowExecute; + reg execute_to_memory_MMU_RSP2_exception; + reg execute_to_memory_MMU_RSP2_refilling; + reg execute_to_memory_MMU_RSP2_bypassTranslation; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_182; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_2820; + reg execute_CsrPlugin_csr_2821; + reg execute_CsrPlugin_csr_2822; + reg execute_CsrPlugin_csr_2823; + reg execute_CsrPlugin_csr_2824; + reg execute_CsrPlugin_csr_2825; + reg execute_CsrPlugin_csr_2826; + reg execute_CsrPlugin_csr_2827; + reg execute_CsrPlugin_csr_2828; + reg execute_CsrPlugin_csr_2829; + reg execute_CsrPlugin_csr_2830; + reg execute_CsrPlugin_csr_2831; + reg execute_CsrPlugin_csr_2832; + reg execute_CsrPlugin_csr_2833; + reg execute_CsrPlugin_csr_2834; + reg execute_CsrPlugin_csr_2835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; + reg [31:0] _zz_199; + reg [31:0] _zz_200; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + reg [31:0] _zz_208; + reg [31:0] _zz_209; + reg [31:0] _zz_210; + reg [31:0] _zz_211; + reg [31:0] _zz_212; + reg [2:0] _zz_213; + reg _zz_214; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_215; + `ifndef SYNTHESIS + reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [39:0] _zz_10_string; + reg [31:0] _zz_11_string; + reg [31:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [71:0] _zz_17_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [39:0] _zz_20_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [23:0] _zz_23_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [63:0] _zz_26_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [95:0] _zz_29_string; + reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_32_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_33_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_34_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_35_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_36_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_39_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_40_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_42_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_43_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_44_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_45_string; + reg [39:0] _zz_49_string; + reg [39:0] _zz_50_string; + reg [31:0] _zz_51_string; + reg [71:0] _zz_52_string; + reg [39:0] _zz_53_string; + reg [23:0] _zz_54_string; + reg [63:0] _zz_55_string; + reg [95:0] _zz_56_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_58_string; + reg [95:0] _zz_101_string; + reg [63:0] _zz_102_string; + reg [23:0] _zz_103_string; + reg [39:0] _zz_104_string; + reg [71:0] _zz_105_string; + reg [31:0] _zz_106_string; + reg [39:0] _zz_107_string; + reg [39:0] _zz_108_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_228 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_229 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_230 = 1'b1; + assign _zz_231 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_232 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_233 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_234 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_235 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_236 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_237 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_238 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_239 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_240 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_241 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_242 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_243 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_244 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_245 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_246 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_247 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_248 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_249 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_250 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_251 = (1'b0 || (! 1'b1)); + assign _zz_252 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_253 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_254 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_255 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_256 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_257 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_258 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_259 = execute_INSTRUCTION[13 : 12]; + assign _zz_260 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_261 = (! memory_arbitration_isStuck); + assign _zz_262 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_263 = (iBus_cmd_valid || (_zz_213 != 3'b000)); + assign _zz_264 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_265 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_266 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_267 = ((_zz_148 && 1'b1) && (! 1'b0)); + assign _zz_268 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_269 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_270 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_271 = execute_INSTRUCTION[13]; + assign _zz_272 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_273 = ($signed(_zz_274) + $signed(_zz_279)); + assign _zz_274 = ($signed(_zz_275) + $signed(_zz_277)); + assign _zz_275 = 52'h0; + assign _zz_276 = {1'b0,memory_MUL_LL}; + assign _zz_277 = {{19{_zz_276[32]}}, _zz_276}; + assign _zz_278 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_279 = {{2{_zz_278[49]}}, _zz_278}; + assign _zz_280 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_281 = {{2{_zz_280[49]}}, _zz_280}; + assign _zz_282 = ($signed(_zz_284) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_283 = _zz_282[31 : 0]; + assign _zz_284 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_285 = _zz_95[32 : 32]; + assign _zz_286 = _zz_95[31 : 31]; + assign _zz_287 = _zz_95[30 : 30]; + assign _zz_288 = _zz_95[29 : 29]; + assign _zz_289 = _zz_95[27 : 27]; + assign _zz_290 = _zz_95[24 : 24]; + assign _zz_291 = _zz_95[16 : 16]; + assign _zz_292 = _zz_95[13 : 13]; + assign _zz_293 = _zz_95[12 : 12]; + assign _zz_294 = _zz_95[11 : 11]; + assign _zz_295 = _zz_95[33 : 33]; + assign _zz_296 = _zz_95[15 : 15]; + assign _zz_297 = _zz_95[5 : 5]; + assign _zz_298 = _zz_95[3 : 3]; + assign _zz_299 = _zz_95[19 : 19]; + assign _zz_300 = _zz_95[10 : 10]; + assign _zz_301 = _zz_95[4 : 4]; + assign _zz_302 = _zz_95[0 : 0]; + assign _zz_303 = (_zz_62 - 4'b0001); + assign _zz_304 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_305 = {29'd0, _zz_304}; + assign _zz_306 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_307 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_308 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_309 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_310 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_311 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_312 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_313 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_314 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_315 = execute_SRC_LESS; + assign _zz_316 = 3'b100; + assign _zz_317 = execute_INSTRUCTION[19 : 15]; + assign _zz_318 = execute_INSTRUCTION[31 : 20]; + assign _zz_319 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_320 = ($signed(_zz_321) + $signed(_zz_324)); + assign _zz_321 = ($signed(_zz_322) + $signed(_zz_323)); + assign _zz_322 = execute_SRC1; + assign _zz_323 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_324 = (execute_SRC_USE_SUB_LESS ? _zz_325 : _zz_326); + assign _zz_325 = 32'h00000001; + assign _zz_326 = 32'h0; + assign _zz_327 = execute_INSTRUCTION[31 : 20]; + assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_329 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_330 = {_zz_134,execute_INSTRUCTION[31 : 20]}; + assign _zz_331 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_332 = {{_zz_138,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_333 = execute_INSTRUCTION[31 : 20]; + assign _zz_334 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_335 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_336 = 3'b100; + assign _zz_337 = (_zz_149 & (~ _zz_338)); + assign _zz_338 = (_zz_149 - 2'b01); + assign _zz_339 = (_zz_151 & (~ _zz_340)); + assign _zz_340 = (_zz_151 - 2'b01); + assign _zz_341 = (_zz_153 & (~ _zz_342)); + assign _zz_342 = (_zz_153 - 2'b01); + assign _zz_343 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_344 = execute_INSTRUCTION[31 : 24]; + assign _zz_345 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_346 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_347 = writeBack_MUL_LOW[31 : 0]; + assign _zz_348 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_349 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_350 = {5'd0, _zz_349}; + assign _zz_351 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_352 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_353 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_354 = {_zz_174,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_355 = _zz_356; + assign _zz_356 = _zz_357; + assign _zz_357 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_175) : _zz_175)} + _zz_359); + assign _zz_358 = memory_DivPlugin_div_needRevert; + assign _zz_359 = {32'd0, _zz_358}; + assign _zz_360 = _zz_177; + assign _zz_361 = {32'd0, _zz_360}; + assign _zz_362 = _zz_176; + assign _zz_363 = {31'd0, _zz_362}; + assign _zz_364 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_365 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_366 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_367 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_368 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_369 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_370 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_371 = (iBus_cmd_payload_address >>> 5); + assign _zz_372 = 1'b1; + assign _zz_373 = 1'b1; + assign _zz_374 = {_zz_66,_zz_65}; + assign _zz_375 = 32'h0000106f; + assign _zz_376 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_377 = 32'h00001073; + assign _zz_378 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_379 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_380 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_381) == 32'h00000003),{(_zz_382 == _zz_383),{_zz_384,{_zz_385,_zz_386}}}}}}; + assign _zz_381 = 32'h0000207f; + assign _zz_382 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_383 = 32'h00000003; + assign _zz_384 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_385 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_386 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_387) == 32'h00001013),{(_zz_388 == _zz_389),{_zz_390,{_zz_391,_zz_392}}}}}}; + assign _zz_387 = 32'hfc00307f; + assign _zz_388 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_389 = 32'h00005033; + assign _zz_390 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_391 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_392 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz_393 = decode_INSTRUCTION[31]; + assign _zz_394 = decode_INSTRUCTION[31]; + assign _zz_395 = decode_INSTRUCTION[7]; + assign _zz_396 = 32'h10103050; + assign _zz_397 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_398 = 1'b0; + assign _zz_399 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_400 = 1'b0; + assign _zz_401 = {(_zz_99 != 1'b0),{({_zz_402,_zz_403} != 2'b00),{(_zz_404 != _zz_405),{_zz_406,{_zz_407,_zz_408}}}}}; + assign _zz_402 = ((decode_INSTRUCTION & _zz_409) == 32'h10000050); + assign _zz_403 = ((decode_INSTRUCTION & _zz_410) == 32'h00000050); + assign _zz_404 = ((decode_INSTRUCTION & _zz_411) == 32'h00000050); + assign _zz_405 = 1'b0; + assign _zz_406 = ({_zz_412,_zz_413} != 2'b00); + assign _zz_407 = ({_zz_414,_zz_415} != 2'b00); + assign _zz_408 = {(_zz_416 != _zz_417),{_zz_418,{_zz_419,_zz_420}}}; + assign _zz_409 = 32'h10203050; + assign _zz_410 = 32'h10103050; + assign _zz_411 = 32'h00103050; + assign _zz_412 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_413 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_414 = _zz_98; + assign _zz_415 = ((decode_INSTRUCTION & _zz_421) == 32'h00000004); + assign _zz_416 = ((decode_INSTRUCTION & _zz_422) == 32'h00000040); + assign _zz_417 = 1'b0; + assign _zz_418 = ({_zz_423,_zz_424} != 2'b00); + assign _zz_419 = ({_zz_425,_zz_426} != 3'b000); + assign _zz_420 = {(_zz_427 != _zz_428),{_zz_429,{_zz_430,_zz_431}}}; + assign _zz_421 = 32'h0000001c; + assign _zz_422 = 32'h00000058; + assign _zz_423 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_424 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h40001010); + assign _zz_426 = {(_zz_433 == _zz_434),(_zz_435 == _zz_436)}; + assign _zz_427 = ((decode_INSTRUCTION & _zz_437) == 32'h00000024); + assign _zz_428 = 1'b0; + assign _zz_429 = ((_zz_438 == _zz_439) != 1'b0); + assign _zz_430 = (_zz_440 != 1'b0); + assign _zz_431 = {(_zz_441 != _zz_442),{_zz_443,{_zz_444,_zz_445}}}; + assign _zz_432 = 32'h40003054; + assign _zz_433 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_434 = 32'h00001010; + assign _zz_435 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_436 = 32'h00001010; + assign _zz_437 = 32'h00000064; + assign _zz_438 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_439 = 32'h00001000; + assign _zz_440 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_441 = {(_zz_446 == _zz_447),(_zz_448 == _zz_449)}; + assign _zz_442 = 2'b00; + assign _zz_443 = ({_zz_99,{_zz_450,_zz_451}} != 3'b000); + assign _zz_444 = ({_zz_452,_zz_453} != 5'h0); + assign _zz_445 = {(_zz_454 != _zz_455),{_zz_456,{_zz_457,_zz_458}}}; + assign _zz_446 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_447 = 32'h00002000; + assign _zz_448 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_449 = 32'h00001000; + assign _zz_450 = ((decode_INSTRUCTION & _zz_459) == 32'h00000020); + assign _zz_451 = ((decode_INSTRUCTION & _zz_460) == 32'h00000020); + assign _zz_452 = ((decode_INSTRUCTION & _zz_461) == 32'h00002040); + assign _zz_453 = {(_zz_462 == _zz_463),{_zz_464,{_zz_465,_zz_466}}}; + assign _zz_454 = ((decode_INSTRUCTION & _zz_467) == 32'h00000020); + assign _zz_455 = 1'b0; + assign _zz_456 = ({_zz_468,{_zz_469,_zz_470}} != 6'h0); + assign _zz_457 = ({_zz_471,_zz_472} != 5'h0); + assign _zz_458 = {(_zz_473 != _zz_474),{_zz_475,{_zz_476,_zz_477}}}; + assign _zz_459 = 32'h00000034; + assign _zz_460 = 32'h00000064; + assign _zz_461 = 32'h00002040; + assign _zz_462 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_463 = 32'h00001040; + assign _zz_464 = ((decode_INSTRUCTION & _zz_478) == 32'h00000040); + assign _zz_465 = (_zz_479 == _zz_480); + assign _zz_466 = (_zz_481 == _zz_482); + assign _zz_467 = 32'h00000020; + assign _zz_468 = ((decode_INSTRUCTION & _zz_483) == 32'h00000008); + assign _zz_469 = (_zz_484 == _zz_485); + assign _zz_470 = {_zz_97,{_zz_486,_zz_487}}; + assign _zz_471 = _zz_97; + assign _zz_472 = {_zz_488,{_zz_489,_zz_490}}; + assign _zz_473 = {_zz_98,{_zz_491,_zz_492}}; + assign _zz_474 = 6'h0; + assign _zz_475 = ({_zz_493,_zz_494} != 2'b00); + assign _zz_476 = (_zz_495 != _zz_496); + assign _zz_477 = {_zz_497,{_zz_498,_zz_499}}; + assign _zz_478 = 32'h00100040; + assign _zz_479 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_480 = 32'h00000040; + assign _zz_481 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_482 = 32'h0; + assign _zz_483 = 32'h00000008; + assign _zz_484 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_485 = 32'h00000040; + assign _zz_486 = (_zz_500 == _zz_501); + assign _zz_487 = {_zz_502,_zz_503}; + assign _zz_488 = ((decode_INSTRUCTION & _zz_504) == 32'h00002010); + assign _zz_489 = (_zz_505 == _zz_506); + assign _zz_490 = {_zz_507,_zz_508}; + assign _zz_491 = (_zz_509 == _zz_510); + assign _zz_492 = {_zz_511,{_zz_512,_zz_513}}; + assign _zz_493 = _zz_97; + assign _zz_494 = (_zz_514 == _zz_515); + assign _zz_495 = {_zz_97,_zz_516}; + assign _zz_496 = 2'b00; + assign _zz_497 = (_zz_517 != 1'b0); + assign _zz_498 = (_zz_518 != _zz_519); + assign _zz_499 = {_zz_520,{_zz_521,_zz_522}}; + assign _zz_500 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_501 = 32'h00004020; + assign _zz_502 = ((decode_INSTRUCTION & _zz_523) == 32'h00000010); + assign _zz_503 = ((decode_INSTRUCTION & _zz_524) == 32'h00000020); + assign _zz_504 = 32'h00002030; + assign _zz_505 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_506 = 32'h00000010; + assign _zz_507 = ((decode_INSTRUCTION & _zz_525) == 32'h00002020); + assign _zz_508 = ((decode_INSTRUCTION & _zz_526) == 32'h00000020); + assign _zz_509 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_510 = 32'h00001010; + assign _zz_511 = ((decode_INSTRUCTION & _zz_527) == 32'h00002010); + assign _zz_512 = (_zz_528 == _zz_529); + assign _zz_513 = {_zz_530,_zz_531}; + assign _zz_514 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_515 = 32'h00000020; + assign _zz_516 = ((decode_INSTRUCTION & _zz_532) == 32'h0); + assign _zz_517 = ((decode_INSTRUCTION & _zz_533) == 32'h00004010); + assign _zz_518 = (_zz_534 == _zz_535); + assign _zz_519 = 1'b0; + assign _zz_520 = ({_zz_536,_zz_537} != 4'b0000); + assign _zz_521 = (_zz_538 != _zz_539); + assign _zz_522 = {_zz_540,{_zz_541,_zz_542}}; + assign _zz_523 = 32'h00000030; + assign _zz_524 = 32'h02000020; + assign _zz_525 = 32'h02002060; + assign _zz_526 = 32'h02003020; + assign _zz_527 = 32'h00002010; + assign _zz_528 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_529 = 32'h00000010; + assign _zz_530 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_531 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_532 = 32'h00000020; + assign _zz_533 = 32'h00004014; + assign _zz_534 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_535 = 32'h00002010; + assign _zz_536 = ((decode_INSTRUCTION & _zz_543) == 32'h0); + assign _zz_537 = {(_zz_544 == _zz_545),{_zz_546,_zz_547}}; + assign _zz_538 = ((decode_INSTRUCTION & _zz_548) == 32'h0); + assign _zz_539 = 1'b0; + assign _zz_540 = ({_zz_549,{_zz_550,_zz_551}} != 3'b000); + assign _zz_541 = ({_zz_552,_zz_553} != 2'b00); + assign _zz_542 = {(_zz_554 != _zz_555),(_zz_556 != _zz_557)}; + assign _zz_543 = 32'h00000044; + assign _zz_544 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_545 = 32'h0; + assign _zz_546 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_547 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_548 = 32'h00000058; + assign _zz_549 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_550 = ((decode_INSTRUCTION & _zz_558) == 32'h00002010); + assign _zz_551 = ((decode_INSTRUCTION & _zz_559) == 32'h40000030); + assign _zz_552 = ((decode_INSTRUCTION & _zz_560) == 32'h00000004); + assign _zz_553 = _zz_96; + assign _zz_554 = {(_zz_561 == _zz_562),_zz_96}; + assign _zz_555 = 2'b00; + assign _zz_556 = ((decode_INSTRUCTION & _zz_563) == 32'h00001004); + assign _zz_557 = 1'b0; + assign _zz_558 = 32'h00002014; + assign _zz_559 = 32'h40000034; + assign _zz_560 = 32'h00000014; + assign _zz_561 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_562 = 32'h00000004; + assign _zz_563 = 32'h00001054; + assign _zz_564 = execute_INSTRUCTION[31]; + assign _zz_565 = execute_INSTRUCTION[31]; + assign _zz_566 = execute_INSTRUCTION[7]; + assign _zz_567 = 32'h0; + always @ (posedge clk) begin + if(_zz_372) begin + _zz_225 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_373) begin + _zz_226 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_48) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_216 ), //i + .io_cpu_prefetch_isValid (_zz_217 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_218 ), //i + .io_cpu_fetch_isStuck (_zz_219 ), //i + .io_cpu_fetch_isRemoved (_zz_220 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_221 ), //i + .io_cpu_decode_isStuck (_zz_222 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_223 ), //i + .io_cpu_fill_valid (_zz_224 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_9 (_zz_182[2:0] ), //i + ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_374) + 2'b00 : begin + _zz_227 = CsrPlugin_jumpInterface_payload; + end + 2'b01 : begin + _zz_227 = DBusSimplePlugin_redoBranch_payload; + end + 2'b10 : begin + _zz_227 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_227 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_1) + `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; + default : _zz_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_2) + `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; + default : _zz_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_3) + `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; + default : _zz_10_string = "?????"; + endcase + end + always @(*) begin + case(_zz_11) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; + default : _zz_12_string = "????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; + default : _zz_17_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; + default : _zz_20_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(_zz_23) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(_zz_26) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; + default : _zz_26_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_29) + `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; + default : _zz_29_string = "????????????"; + endcase + end + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; + default : _zz_32_string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_36) + `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; + default : _zz_36_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_39) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; + default : _zz_39_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_40) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; + default : _zz_40_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_42) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; + default : _zz_42_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_43) + `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; + default : _zz_43_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_44) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; + default : _zz_44_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; + default : _zz_45_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; + default : _zz_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_50) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; + default : _zz_50_string = "?????"; + endcase + end + always @(*) begin + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; + endcase + end + always @(*) begin + case(_zz_52) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; + default : _zz_52_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_53) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; + default : _zz_53_string = "?????"; + endcase + end + always @(*) begin + case(_zz_54) + `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; + default : _zz_54_string = "???"; + endcase + end + always @(*) begin + case(_zz_55) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; + default : _zz_55_string = "????????"; + endcase + end + always @(*) begin + case(_zz_56) + `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; + default : _zz_56_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_58) + `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; + default : _zz_58_string = "????"; + endcase + end + always @(*) begin + case(_zz_101) + `Src1CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_101_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_101_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_101_string = "URS1 "; + default : _zz_101_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_102) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_102_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_102_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_102_string = "BITWISE "; + default : _zz_102_string = "????????"; + endcase + end + always @(*) begin + case(_zz_103) + `Src2CtrlEnum_defaultEncoding_RS : _zz_103_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_103_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_103_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_103_string = "PC "; + default : _zz_103_string = "???"; + endcase + end + always @(*) begin + case(_zz_104) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_104_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_104_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_104_string = "AND_1"; + default : _zz_104_string = "?????"; + endcase + end + always @(*) begin + case(_zz_105) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_105_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_105_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_105_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_105_string = "SRA_1 "; + default : _zz_105_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_106) + `BranchCtrlEnum_defaultEncoding_INC : _zz_106_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_106_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_106_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_106_string = "JALR"; + default : _zz_106_string = "????"; + endcase + end + always @(*) begin + case(_zz_107) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_107_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_107_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_107_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_107_string = "ECALL"; + default : _zz_107_string = "?????"; + endcase + end + always @(*) begin + case(_zz_108) + `Input2Kind_defaultEncoding_RS : _zz_108_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_108_string = "IMM_I"; + default : _zz_108_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_273) + $signed(_zz_281)); + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign execute_SHIFT_RIGHT = _zz_283; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_110; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_285[0]; + assign decode_IS_RS1_SIGNED = _zz_286[0]; + assign decode_IS_DIV = _zz_287[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_288[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; + assign _zz_2 = _zz_3; + assign decode_CfuPlugin_CFU_ENABLE = _zz_289[0]; + assign _zz_4 = _zz_5; + assign _zz_6 = _zz_7; + assign decode_ENV_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_IS_CSR = _zz_290[0]; + assign _zz_11 = _zz_12; + assign _zz_13 = _zz_14; + assign decode_SHIFT_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_ALU_BITWISE_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_SRC_LESS_UNSIGNED = _zz_291[0]; + assign decode_MEMORY_STORE = _zz_292[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_293[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_294[0]; + assign decode_SRC2_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_ALU_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_SRC1_CTRL = _zz_27; + assign _zz_28 = _zz_29; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_295[0]; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + always @ (*) begin + _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck)begin + _zz_30 = 1'b0; + end + end + + always @ (*) begin + _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck)begin + _zz_31 = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_33; + assign execute_ENV_CTRL = _zz_34; + assign writeBack_ENV_CTRL = _zz_35; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_132; + assign execute_BRANCH_CTRL = _zz_36; + assign decode_RS2_USE = _zz_296[0]; + assign decode_RS1_USE = _zz_297[0]; + always @ (*) begin + _zz_37 = execute_REGFILE_WRITE_DATA; + if(_zz_228)begin + _zz_37 = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_121)begin + if((_zz_122 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_123; + end + end + if(_zz_229)begin + if(_zz_230)begin + if(_zz_125)begin + decode_RS2 = _zz_57; + end + end + end + if(_zz_231)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_127)begin + decode_RS2 = _zz_38; + end + end + end + if(_zz_232)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_129)begin + decode_RS2 = _zz_37; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_121)begin + if((_zz_122 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_123; + end + end + if(_zz_229)begin + if(_zz_230)begin + if(_zz_124)begin + decode_RS1 = _zz_57; + end + end + end + if(_zz_231)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_126)begin + decode_RS1 = _zz_38; + end + end + end + if(_zz_232)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_128)begin + decode_RS1 = _zz_37; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_38 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_38 = _zz_118; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_38 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_233)begin + _zz_38 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_39; + assign execute_SHIFT_CTRL = _zz_40; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_41 = execute_PC; + assign execute_SRC2_CTRL = _zz_42; + assign execute_SRC1_CTRL = _zz_43; + assign decode_SRC_USE_SUB_LESS = _zz_298[0]; + assign decode_SRC_ADD_ZERO = _zz_299[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_44; + assign execute_SRC2 = _zz_116; + assign execute_SRC1 = _zz_111; + assign execute_ALU_BITWISE_CTRL = _zz_45; + assign _zz_46 = writeBack_INSTRUCTION; + assign _zz_47 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_48 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_48 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_300[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_375) == 32'h00000003),{(_zz_376 == _zz_377),{_zz_378,{_zz_379,_zz_380}}}}}}} != 21'h0); + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + always @ (*) begin + _zz_57 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_57 = writeBack_DBusSimplePlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_272) + 2'b00 : begin + _zz_57 = _zz_347; + end + default : begin + _zz_57 = _zz_348; + end + endcase + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; + assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; + assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; + assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; + assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; + assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; + assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; + assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; + assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; + assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; + assign memory_PC = execute_to_memory_PC; + assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); + assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; + assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; + assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; + assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; + assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; + assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; + assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; + assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); + assign decode_MEMORY_ENABLE = _zz_301[0]; + assign decode_FLUSH_ALL = _zz_302[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_234)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_235)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_236)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_237)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_58; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_59 = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_59 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_60 = memory_FORMAL_PC_NEXT; + if(DBusSimplePlugin_redoBranch_valid)begin + _zz_60 = DBusSimplePlugin_redoBranch_payload; + end + end + + always @ (*) begin + _zz_61 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_61 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + case(_zz_182) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_119 || _zz_120)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_238)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_238)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_88)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_239)begin + if((! execute_CsrPlugin_wfiWake))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_228)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if(_zz_240)begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(_zz_241)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushIt = 1'b0; + if(_zz_240)begin + if(_zz_242)begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_241)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_240)begin + if(_zz_242)begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if((! memory_CfuPlugin_rsp_valid))begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_233)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(_zz_243)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushIt = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(_zz_243)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_244)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_245)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_244)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_245)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_240)begin + if(_zz_242)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_246)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_239)begin + CsrPlugin_inWfi = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_244)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_245)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_244)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_245)begin + case(_zz_247) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode)begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + end + end + + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; + assign _zz_63 = (_zz_62 & (~ _zz_303)); + assign _zz_64 = _zz_63[3]; + assign _zz_65 = (_zz_63[1] || _zz_64); + assign _zz_66 = (_zz_63[2] || _zz_64); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_227; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_305); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_69 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_69); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_69); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_70; + assign _zz_70 = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_71 = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_73)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_73 = _zz_74; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_73; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_75; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + always @ (*) begin + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_182) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + end + + assign _zz_76 = _zz_306[11]; + always @ (*) begin + _zz_77[18] = _zz_76; + _zz_77[17] = _zz_76; + _zz_77[16] = _zz_76; + _zz_77[15] = _zz_76; + _zz_77[14] = _zz_76; + _zz_77[13] = _zz_76; + _zz_77[12] = _zz_76; + _zz_77[11] = _zz_76; + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7] = _zz_76; + _zz_77[6] = _zz_76; + _zz_77[5] = _zz_76; + _zz_77[4] = _zz_76; + _zz_77[3] = _zz_76; + _zz_77[2] = _zz_76; + _zz_77[1] = _zz_76; + _zz_77[0] = _zz_76; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_307[31])); + if(_zz_82)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_78 = _zz_308[19]; + always @ (*) begin + _zz_79[10] = _zz_78; + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7] = _zz_78; + _zz_79[6] = _zz_78; + _zz_79[5] = _zz_78; + _zz_79[4] = _zz_78; + _zz_79[3] = _zz_78; + _zz_79[2] = _zz_78; + _zz_79[1] = _zz_78; + _zz_79[0] = _zz_78; + end + + assign _zz_80 = _zz_309[11]; + always @ (*) begin + _zz_81[18] = _zz_80; + _zz_81[17] = _zz_80; + _zz_81[16] = _zz_80; + _zz_81[15] = _zz_80; + _zz_81[14] = _zz_80; + _zz_81[13] = _zz_80; + _zz_81[12] = _zz_80; + _zz_81[11] = _zz_80; + _zz_81[10] = _zz_80; + _zz_81[9] = _zz_80; + _zz_81[8] = _zz_80; + _zz_81[7] = _zz_80; + _zz_81[6] = _zz_80; + _zz_81[5] = _zz_80; + _zz_81[4] = _zz_80; + _zz_81[3] = _zz_80; + _zz_81[2] = _zz_80; + _zz_81[1] = _zz_80; + _zz_81[0] = _zz_80; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_82 = _zz_310[1]; + end + default : begin + _zz_82 = _zz_311[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_83 = _zz_312[19]; + always @ (*) begin + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7] = _zz_83; + _zz_84[6] = _zz_83; + _zz_84[5] = _zz_83; + _zz_84[4] = _zz_83; + _zz_84[3] = _zz_83; + _zz_84[2] = _zz_83; + _zz_84[1] = _zz_83; + _zz_84[0] = _zz_83; + end + + assign _zz_85 = _zz_313[11]; + always @ (*) begin + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7] = _zz_85; + _zz_86[6] = _zz_85; + _zz_86[5] = _zz_85; + _zz_86[4] = _zz_85; + _zz_86[3] = _zz_85; + _zz_86[2] = _zz_85; + _zz_86[1] = _zz_85; + _zz_86[0] = _zz_85; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_393,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_394,_zz_395},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_217 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_219 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_218; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_222 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_223 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_237)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_235)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_224 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_235)begin + _zz_224 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_236)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_234)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_236)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_234)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_216 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_88 = 1'b0; + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_88)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_89 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_89 = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_89; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_90 = 4'b0001; + end + 2'b01 : begin + _zz_90 = 4'b0011; + end + default : begin + _zz_90 = 4'b1111; + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_90 <<< dBus_cmd_payload_address[1 : 0]); + assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; + assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; + assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + if(_zz_248)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_MMU_RSP2_refilling)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end else begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + end + if(_zz_249)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; + if(_zz_248)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_314}; + end + if(! memory_MMU_RSP2_refilling) begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); + end + end + end + + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; + always @ (*) begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + if(memory_MMU_RSP2_refilling)begin + DBusSimplePlugin_redoBranch_valid = 1'b1; + end + if(_zz_249)begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + end + end + + assign DBusSimplePlugin_redoBranch_payload = memory_PC; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_91 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_92[31] = _zz_91; + _zz_92[30] = _zz_91; + _zz_92[29] = _zz_91; + _zz_92[28] = _zz_91; + _zz_92[27] = _zz_91; + _zz_92[26] = _zz_91; + _zz_92[25] = _zz_91; + _zz_92[24] = _zz_91; + _zz_92[23] = _zz_91; + _zz_92[22] = _zz_91; + _zz_92[21] = _zz_91; + _zz_92[20] = _zz_91; + _zz_92[19] = _zz_91; + _zz_92[18] = _zz_91; + _zz_92[17] = _zz_91; + _zz_92[16] = _zz_91; + _zz_92[15] = _zz_91; + _zz_92[14] = _zz_91; + _zz_92[13] = _zz_91; + _zz_92[12] = _zz_91; + _zz_92[11] = _zz_91; + _zz_92[10] = _zz_91; + _zz_92[9] = _zz_91; + _zz_92[8] = _zz_91; + _zz_92[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_93 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_94[31] = _zz_93; + _zz_94[30] = _zz_93; + _zz_94[29] = _zz_93; + _zz_94[28] = _zz_93; + _zz_94[27] = _zz_93; + _zz_94[26] = _zz_93; + _zz_94[25] = _zz_93; + _zz_94[24] = _zz_93; + _zz_94[23] = _zz_93; + _zz_94[22] = _zz_93; + _zz_94[21] = _zz_93; + _zz_94[20] = _zz_93; + _zz_94[19] = _zz_93; + _zz_94[18] = _zz_93; + _zz_94[17] = _zz_93; + _zz_94[16] = _zz_93; + _zz_94[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_270) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_92; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_94; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusSimplePlugin_mmuBus_busy = 1'b0; + assign _zz_96 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_97 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_98 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_99 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_100 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_95 = {(((decode_INSTRUCTION & _zz_396) == 32'h00100050) != 1'b0),{(_zz_100 != 1'b0),{(_zz_100 != 1'b0),{(_zz_397 != _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}; + assign _zz_101 = _zz_95[2 : 1]; + assign _zz_56 = _zz_101; + assign _zz_102 = _zz_95[7 : 6]; + assign _zz_55 = _zz_102; + assign _zz_103 = _zz_95[9 : 8]; + assign _zz_54 = _zz_103; + assign _zz_104 = _zz_95[18 : 17]; + assign _zz_53 = _zz_104; + assign _zz_105 = _zz_95[21 : 20]; + assign _zz_52 = _zz_105; + assign _zz_106 = _zz_95[23 : 22]; + assign _zz_51 = _zz_106; + assign _zz_107 = _zz_95[26 : 25]; + assign _zz_50 = _zz_107; + assign _zz_108 = _zz_95[28 : 28]; + assign _zz_49 = _zz_108; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_225; + assign decode_RegFilePlugin_rs2Data = _zz_226; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); + if(_zz_109)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; + if(_zz_109)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_57; + if(_zz_109)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_110 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_110 = {31'd0, _zz_315}; + end + default : begin + _zz_110 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_111 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_111 = {29'd0, _zz_316}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_111 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_111 = {27'd0, _zz_317}; + end + endcase + end + + assign _zz_112 = _zz_318[11]; + always @ (*) begin + _zz_113[19] = _zz_112; + _zz_113[18] = _zz_112; + _zz_113[17] = _zz_112; + _zz_113[16] = _zz_112; + _zz_113[15] = _zz_112; + _zz_113[14] = _zz_112; + _zz_113[13] = _zz_112; + _zz_113[12] = _zz_112; + _zz_113[11] = _zz_112; + _zz_113[10] = _zz_112; + _zz_113[9] = _zz_112; + _zz_113[8] = _zz_112; + _zz_113[7] = _zz_112; + _zz_113[6] = _zz_112; + _zz_113[5] = _zz_112; + _zz_113[4] = _zz_112; + _zz_113[3] = _zz_112; + _zz_113[2] = _zz_112; + _zz_113[1] = _zz_112; + _zz_113[0] = _zz_112; + end + + assign _zz_114 = _zz_319[11]; + always @ (*) begin + _zz_115[19] = _zz_114; + _zz_115[18] = _zz_114; + _zz_115[17] = _zz_114; + _zz_115[16] = _zz_114; + _zz_115[15] = _zz_114; + _zz_115[14] = _zz_114; + _zz_115[13] = _zz_114; + _zz_115[12] = _zz_114; + _zz_115[11] = _zz_114; + _zz_115[10] = _zz_114; + _zz_115[9] = _zz_114; + _zz_115[8] = _zz_114; + _zz_115[7] = _zz_114; + _zz_115[6] = _zz_114; + _zz_115[5] = _zz_114; + _zz_115[4] = _zz_114; + _zz_115[3] = _zz_114; + _zz_115[2] = _zz_114; + _zz_115[1] = _zz_114; + _zz_115[0] = _zz_114; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_116 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_116 = {_zz_113,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_116 = {_zz_115,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_116 = _zz_41; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_320; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_117[0] = execute_SRC1[31]; + _zz_117[1] = execute_SRC1[30]; + _zz_117[2] = execute_SRC1[29]; + _zz_117[3] = execute_SRC1[28]; + _zz_117[4] = execute_SRC1[27]; + _zz_117[5] = execute_SRC1[26]; + _zz_117[6] = execute_SRC1[25]; + _zz_117[7] = execute_SRC1[24]; + _zz_117[8] = execute_SRC1[23]; + _zz_117[9] = execute_SRC1[22]; + _zz_117[10] = execute_SRC1[21]; + _zz_117[11] = execute_SRC1[20]; + _zz_117[12] = execute_SRC1[19]; + _zz_117[13] = execute_SRC1[18]; + _zz_117[14] = execute_SRC1[17]; + _zz_117[15] = execute_SRC1[16]; + _zz_117[16] = execute_SRC1[15]; + _zz_117[17] = execute_SRC1[14]; + _zz_117[18] = execute_SRC1[13]; + _zz_117[19] = execute_SRC1[12]; + _zz_117[20] = execute_SRC1[11]; + _zz_117[21] = execute_SRC1[10]; + _zz_117[22] = execute_SRC1[9]; + _zz_117[23] = execute_SRC1[8]; + _zz_117[24] = execute_SRC1[7]; + _zz_117[25] = execute_SRC1[6]; + _zz_117[26] = execute_SRC1[5]; + _zz_117[27] = execute_SRC1[4]; + _zz_117[28] = execute_SRC1[3]; + _zz_117[29] = execute_SRC1[2]; + _zz_117[30] = execute_SRC1[1]; + _zz_117[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_117 : execute_SRC1); + always @ (*) begin + _zz_118[0] = memory_SHIFT_RIGHT[31]; + _zz_118[1] = memory_SHIFT_RIGHT[30]; + _zz_118[2] = memory_SHIFT_RIGHT[29]; + _zz_118[3] = memory_SHIFT_RIGHT[28]; + _zz_118[4] = memory_SHIFT_RIGHT[27]; + _zz_118[5] = memory_SHIFT_RIGHT[26]; + _zz_118[6] = memory_SHIFT_RIGHT[25]; + _zz_118[7] = memory_SHIFT_RIGHT[24]; + _zz_118[8] = memory_SHIFT_RIGHT[23]; + _zz_118[9] = memory_SHIFT_RIGHT[22]; + _zz_118[10] = memory_SHIFT_RIGHT[21]; + _zz_118[11] = memory_SHIFT_RIGHT[20]; + _zz_118[12] = memory_SHIFT_RIGHT[19]; + _zz_118[13] = memory_SHIFT_RIGHT[18]; + _zz_118[14] = memory_SHIFT_RIGHT[17]; + _zz_118[15] = memory_SHIFT_RIGHT[16]; + _zz_118[16] = memory_SHIFT_RIGHT[15]; + _zz_118[17] = memory_SHIFT_RIGHT[14]; + _zz_118[18] = memory_SHIFT_RIGHT[13]; + _zz_118[19] = memory_SHIFT_RIGHT[12]; + _zz_118[20] = memory_SHIFT_RIGHT[11]; + _zz_118[21] = memory_SHIFT_RIGHT[10]; + _zz_118[22] = memory_SHIFT_RIGHT[9]; + _zz_118[23] = memory_SHIFT_RIGHT[8]; + _zz_118[24] = memory_SHIFT_RIGHT[7]; + _zz_118[25] = memory_SHIFT_RIGHT[6]; + _zz_118[26] = memory_SHIFT_RIGHT[5]; + _zz_118[27] = memory_SHIFT_RIGHT[4]; + _zz_118[28] = memory_SHIFT_RIGHT[3]; + _zz_118[29] = memory_SHIFT_RIGHT[2]; + _zz_118[30] = memory_SHIFT_RIGHT[1]; + _zz_118[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_119 = 1'b0; + if(_zz_250)begin + if(_zz_251)begin + if(_zz_124)begin + _zz_119 = 1'b1; + end + end + end + if(_zz_252)begin + if(_zz_253)begin + if(_zz_126)begin + _zz_119 = 1'b1; + end + end + end + if(_zz_254)begin + if(_zz_255)begin + if(_zz_128)begin + _zz_119 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_119 = 1'b0; + end + end + + always @ (*) begin + _zz_120 = 1'b0; + if(_zz_250)begin + if(_zz_251)begin + if(_zz_125)begin + _zz_120 = 1'b1; + end + end + end + if(_zz_252)begin + if(_zz_253)begin + if(_zz_127)begin + _zz_120 = 1'b1; + end + end + end + if(_zz_254)begin + if(_zz_255)begin + if(_zz_129)begin + _zz_120 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_120 = 1'b0; + end + end + + assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_125 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_127 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_129 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_130 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_130 == 3'b000)) begin + _zz_131 = execute_BranchPlugin_eq; + end else if((_zz_130 == 3'b001)) begin + _zz_131 = (! execute_BranchPlugin_eq); + end else if((((_zz_130 & 3'b101) == 3'b101))) begin + _zz_131 = (! execute_SRC_LESS); + end else begin + _zz_131 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_132 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_132 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_132 = 1'b1; + end + default : begin + _zz_132 = _zz_131; + end + endcase + end + + assign _zz_133 = _zz_327[11]; + always @ (*) begin + _zz_134[19] = _zz_133; + _zz_134[18] = _zz_133; + _zz_134[17] = _zz_133; + _zz_134[16] = _zz_133; + _zz_134[15] = _zz_133; + _zz_134[14] = _zz_133; + _zz_134[13] = _zz_133; + _zz_134[12] = _zz_133; + _zz_134[11] = _zz_133; + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; + end + + assign _zz_135 = _zz_328[19]; + always @ (*) begin + _zz_136[10] = _zz_135; + _zz_136[9] = _zz_135; + _zz_136[8] = _zz_135; + _zz_136[7] = _zz_135; + _zz_136[6] = _zz_135; + _zz_136[5] = _zz_135; + _zz_136[4] = _zz_135; + _zz_136[3] = _zz_135; + _zz_136[2] = _zz_135; + _zz_136[1] = _zz_135; + _zz_136[0] = _zz_135; + end + + assign _zz_137 = _zz_329[11]; + always @ (*) begin + _zz_138[18] = _zz_137; + _zz_138[17] = _zz_137; + _zz_138[16] = _zz_137; + _zz_138[15] = _zz_137; + _zz_138[14] = _zz_137; + _zz_138[13] = _zz_137; + _zz_138[12] = _zz_137; + _zz_138[11] = _zz_137; + _zz_138[10] = _zz_137; + _zz_138[9] = _zz_137; + _zz_138[8] = _zz_137; + _zz_138[7] = _zz_137; + _zz_138[6] = _zz_137; + _zz_138[5] = _zz_137; + _zz_138[4] = _zz_137; + _zz_138[3] = _zz_137; + _zz_138[2] = _zz_137; + _zz_138[1] = _zz_137; + _zz_138[0] = _zz_137; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_139 = (_zz_330[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_139 = _zz_331[1]; + end + default : begin + _zz_139 = _zz_332[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_139); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_140 = _zz_333[11]; + always @ (*) begin + _zz_141[19] = _zz_140; + _zz_141[18] = _zz_140; + _zz_141[17] = _zz_140; + _zz_141[16] = _zz_140; + _zz_141[15] = _zz_140; + _zz_141[14] = _zz_140; + _zz_141[13] = _zz_140; + _zz_141[12] = _zz_140; + _zz_141[11] = _zz_140; + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_141,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_143,{{{_zz_564,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_145,{{{_zz_565,_zz_566},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_336}; + end + end + endcase + end + + assign _zz_142 = _zz_334[19]; + always @ (*) begin + _zz_143[10] = _zz_142; + _zz_143[9] = _zz_142; + _zz_143[8] = _zz_142; + _zz_143[7] = _zz_142; + _zz_143[6] = _zz_142; + _zz_143[5] = _zz_142; + _zz_143[4] = _zz_142; + _zz_143[3] = _zz_142; + _zz_143[2] = _zz_142; + _zz_143[1] = _zz_142; + _zz_143[0] = _zz_142; + end + + assign _zz_144 = _zz_335[11]; + always @ (*) begin + _zz_145[18] = _zz_144; + _zz_145[17] = _zz_144; + _zz_145[16] = _zz_144; + _zz_145[15] = _zz_144; + _zz_145[14] = _zz_144; + _zz_145[13] = _zz_144; + _zz_145[12] = _zz_144; + _zz_145[11] = _zz_144; + _zz_145[10] = _zz_144; + _zz_145[9] = _zz_144; + _zz_145[8] = _zz_144; + _zz_145[7] = _zz_144; + _zz_145[6] = _zz_144; + _zz_145[5] = _zz_144; + _zz_145[4] = _zz_144; + _zz_145[3] = _zz_144; + _zz_145[2] = _zz_144; + _zz_145[1] = _zz_144; + _zz_145[0] = _zz_144; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_146 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_147 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_148 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_149 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_150 = _zz_337[0]; + assign _zz_151 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_152 = _zz_339[0]; + assign _zz_153 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_154 = _zz_341[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_238)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_241)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(_zz_243)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2820)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2822)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2824)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2826)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2828)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2830)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_256)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_257)begin + CsrPlugin_selfException_valid = 1'b1; + end + if(_zz_258)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_257)begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(_zz_258)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_256)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_256)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_271) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign execute_CfuPlugin_functionsIds_0 = _zz_343; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_171 = _zz_344[7]; + always @ (*) begin + _zz_172[23] = _zz_171; + _zz_172[22] = _zz_171; + _zz_172[21] = _zz_171; + _zz_172[20] = _zz_171; + _zz_172[19] = _zz_171; + _zz_172[18] = _zz_171; + _zz_172[17] = _zz_171; + _zz_172[16] = _zz_171; + _zz_172[15] = _zz_171; + _zz_172[14] = _zz_171; + _zz_172[13] = _zz_171; + _zz_172[12] = _zz_171; + _zz_172[11] = _zz_171; + _zz_172[10] = _zz_171; + _zz_172[9] = _zz_171; + _zz_172[8] = _zz_171; + _zz_172[7] = _zz_171; + _zz_172[6] = _zz_171; + _zz_172[5] = _zz_171; + _zz_172[4] = _zz_171; + _zz_172[3] = _zz_171; + _zz_172[2] = _zz_171; + _zz_172[1] = _zz_171; + _zz_172[0] = _zz_171; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : begin + _zz_173 = execute_RS2; + end + default : begin + _zz_173 = {_zz_172,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_173; + assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); + assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); + assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @ (*) begin + CfuPlugin_joinException_valid = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if(memory_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); + end + end + end + + assign CfuPlugin_joinException_payload_code = 4'b1111; + assign CfuPlugin_joinException_payload_badAddr = 32'h0; + always @ (*) begin + memory_CfuPlugin_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_259) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_259) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_345) + $signed(_zz_346)); + assign memory_DivPlugin_frontendOk = 1'b1; + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_233)begin + if(_zz_260)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_261)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_350); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_174 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_174[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_351); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_352 : _zz_353); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_354[31:0]; + assign _zz_175 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_176 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_177 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_178[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_178[31 : 0] = execute_RS1; + end + + assign _zz_180 = (_zz_179 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_180 != 32'h0); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_262) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_181))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + always @ (*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_262) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_29 = decode_SRC1_CTRL; + assign _zz_27 = _zz_56; + assign _zz_43 = decode_to_execute_SRC1_CTRL; + assign _zz_26 = decode_ALU_CTRL; + assign _zz_24 = _zz_55; + assign _zz_44 = decode_to_execute_ALU_CTRL; + assign _zz_23 = decode_SRC2_CTRL; + assign _zz_21 = _zz_54; + assign _zz_42 = decode_to_execute_SRC2_CTRL; + assign _zz_20 = decode_ALU_BITWISE_CTRL; + assign _zz_18 = _zz_53; + assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_17 = decode_SHIFT_CTRL; + assign _zz_14 = execute_SHIFT_CTRL; + assign _zz_15 = _zz_52; + assign _zz_40 = decode_to_execute_SHIFT_CTRL; + assign _zz_39 = execute_to_memory_SHIFT_CTRL; + assign _zz_12 = decode_BRANCH_CTRL; + assign _zz_58 = _zz_51; + assign _zz_36 = decode_to_execute_BRANCH_CTRL; + assign _zz_10 = decode_ENV_CTRL; + assign _zz_7 = execute_ENV_CTRL; + assign _zz_5 = memory_ENV_CTRL; + assign _zz_8 = _zz_50; + assign _zz_34 = decode_to_execute_ENV_CTRL; + assign _zz_33 = execute_to_memory_ENV_CTRL; + assign _zz_35 = memory_to_writeBack_ENV_CTRL; + assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_1 = _zz_49; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(_zz_182) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_183[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_184 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_184[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_185 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_185[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_186 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_186[31 : 30] = CsrPlugin_misa_base; + _zz_186[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_187 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_187[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_187[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_187[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_188 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_188[11 : 11] = CsrPlugin_mip_MEIP; + _zz_188[7 : 7] = CsrPlugin_mip_MTIP; + _zz_188[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_189 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_189[11 : 11] = CsrPlugin_mie_MEIE; + _zz_189[7 : 7] = CsrPlugin_mie_MTIE; + _zz_189[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_190 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_190[31 : 2] = CsrPlugin_mtvec_base; + _zz_190[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_191 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_191[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_192 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_192[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_193 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_193[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_193[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_194 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_194[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_195 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_195[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_196 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_196[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_197 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_197[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_198 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_198[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_199 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_199[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_200 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_200[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_201 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_201[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_202 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_202[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_203 = 32'h0; + if(execute_CsrPlugin_csr_2820)begin + _zz_203[31 : 0] = _zz_155; + end + end + + always @ (*) begin + _zz_204 = 32'h0; + if(execute_CsrPlugin_csr_2822)begin + _zz_204[31 : 0] = _zz_157; + end + end + + always @ (*) begin + _zz_205 = 32'h0; + if(execute_CsrPlugin_csr_2824)begin + _zz_205[31 : 0] = _zz_159; + end + end + + always @ (*) begin + _zz_206 = 32'h0; + if(execute_CsrPlugin_csr_2826)begin + _zz_206[31 : 0] = _zz_161; + end + end + + always @ (*) begin + _zz_207 = 32'h0; + if(execute_CsrPlugin_csr_2828)begin + _zz_207[31 : 0] = _zz_163; + end + end + + always @ (*) begin + _zz_208 = 32'h0; + if(execute_CsrPlugin_csr_2830)begin + _zz_208[31 : 0] = _zz_165; + end + end + + always @ (*) begin + _zz_209 = 32'h0; + if(execute_CsrPlugin_csr_2832)begin + _zz_209[31 : 0] = _zz_167; + end + end + + always @ (*) begin + _zz_210 = 32'h0; + if(execute_CsrPlugin_csr_2834)begin + _zz_210[31 : 0] = _zz_169; + end + end + + always @ (*) begin + _zz_211 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_211[31 : 0] = _zz_179; + end + end + + always @ (*) begin + _zz_212 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_212[31 : 0] = _zz_180; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_183 | _zz_184) | (_zz_185 | _zz_567)) | ((_zz_186 | _zz_187) | (_zz_188 | _zz_189))) | (((_zz_190 | _zz_191) | (_zz_192 | _zz_193)) | ((_zz_194 | _zz_195) | (_zz_196 | _zz_197)))) | ((((_zz_198 | _zz_199) | (_zz_200 | _zz_201)) | ((_zz_202 | _zz_203) | (_zz_204 | _zz_205))) | (((_zz_206 | _zz_207) | (_zz_208 | _zz_209)) | ((_zz_210 | _zz_211) | _zz_212)))); + assign iBusWishbone_ADR = {_zz_371,_zz_213}; + assign iBusWishbone_CTI = ((_zz_213 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'h0; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_263)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_263)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_214; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = 3'b000; + assign dBusWishbone_BTE = 2'b00; + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_215 = 4'b0001; + end + 2'b01 : begin + _zz_215 = 4'b0011; + end + default : begin + _zz_215 = 4'b1111; + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = (_zz_215 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = 4'b1111; + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_72 <= 1'b0; + _zz_74 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_87; + IBusCachedPlugin_rspCounter <= 32'h0; + _zz_109 <= 1'b1; + _zz_121 <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_CfuPlugin_hold <= 1'b0; + execute_CfuPlugin_fired <= 1'b0; + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_179 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_182 <= 3'b000; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; + _zz_213 <= 3'b000; + _zz_214 <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_72 <= 1'b0; + end + if(_zz_70)begin + _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_74 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_74 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + _zz_109 <= 1'b0; + _zz_121 <= (_zz_47 && writeBack_arbitration_isFiring); + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_264)begin + if(_zz_265)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_266)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_267)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_244)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_245)begin + case(_zz_247) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_148,{_zz_147,_zz_146}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(execute_CfuPlugin_schedule)begin + execute_CfuPlugin_hold <= 1'b1; + end + if(CfuPlugin_bus_cmd_ready)begin + execute_CfuPlugin_hold <= 1'b0; + end + if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + execute_CfuPlugin_fired <= 1'b1; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_CfuPlugin_fired <= 1'b0; + end + if(memory_CfuPlugin_rsp_ready)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + end + if(_zz_268)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + end + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! memory_arbitration_isStuck))begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_182) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_182 <= 3'b001; + end + end + 3'b001 : begin + _zz_182 <= 3'b010; + end + 3'b010 : begin + _zz_182 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_182 <= 3'b100; + end + end + 3'b100 : begin + _zz_182 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_364[0]; + CsrPlugin_mstatus_MIE <= _zz_365[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_367[0]; + CsrPlugin_mie_MTIE <= _zz_368[0]; + CsrPlugin_mie_MSIE <= _zz_369[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_179 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_263)begin + if(iBusWishbone_ACK)begin + _zz_213 <= (_zz_213 + 3'b001); + end + end + _zz_214 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_269)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_75 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + _zz_122 <= _zz_46[11 : 7]; + _zz_123 <= _zz_57; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_238)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_241)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_154 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_154 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + end + if(_zz_243)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_152 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_152 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + end + if(_zz_264)begin + if(_zz_265)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_266)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_267)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_244)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(_zz_156[0])begin + _zz_155 <= (_zz_155 + 32'h00000001); + end + if(_zz_158[0])begin + _zz_157 <= (_zz_157 + 32'h00000001); + end + if(_zz_160[0])begin + _zz_159 <= (_zz_159 + 32'h00000001); + end + if(_zz_162[0])begin + _zz_161 <= (_zz_161 + 32'h00000001); + end + if(_zz_164[0])begin + _zz_163 <= (_zz_163 + 32'h00000001); + end + if(_zz_166[0])begin + _zz_165 <= (_zz_165 + 32'h00000001); + end + if(_zz_168[0])begin + _zz_167 <= (_zz_167 + 32'h00000001); + end + if(_zz_170[0])begin + _zz_169 <= (_zz_169 + 32'h00000001); + end + if(_zz_268)begin + CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_233)begin + if(_zz_260)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_355[31:0]; + end + end + end + if(_zz_261)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_177 ? (~ _zz_178) : _zz_178) + _zz_361); + memory_DivPlugin_rs2 <= ((_zz_176 ? (~ execute_RS2) : execute_RS2) + _zz_363); + memory_DivPlugin_div_needRevert <= ((_zz_177 ^ (_zz_176 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_41; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_61; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_60; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_28; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_16; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_13; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; + execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; + execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; + execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; + execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; + execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; + execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; + execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; + execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_366[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_370[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_169 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_170 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_269)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_57; + end + _zz_181 <= debug_bus_cmd_payload_address[2]; + if(_zz_240)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_262) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(_zz_240)begin + if(_zz_242)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_246)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_9, + input [31:0] _zz_10, + input clk, + input reset +); + reg [31:0] _zz_11; + reg [22:0] _zz_12; + wire _zz_13; + wire _zz_14; + wire [0:0] _zz_15; + wire [0:0] _zz_16; + wire [22:0] _zz_17; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [8:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [8:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; + + assign _zz_13 = (! lineLoader_flushCounter[6]); + assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_15 = _zz_8[0 : 0]; + assign _zz_16 = _zz_8[1 : 1]; + assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_11 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_12 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_13)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_12; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_14)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_13)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_3 <= lineLoader_flushCounter[6]; + if(_zz_14)begin + lineLoader_flushCounter <= 7'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + if((_zz_9 != 3'b000))begin + io_cpu_fetch_data_regNextWhen <= _zz_10; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml new file mode 100644 index 0000000..75d2f32 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml @@ -0,0 +1,5 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/genWrapper.py b/pythondata_cpu_vexriscv/verilog/genWrapper.py index a648eba..5d2d549 100755 --- a/pythondata_cpu_vexriscv/verilog/genWrapper.py +++ b/pythondata_cpu_vexriscv/verilog/genWrapper.py @@ -73,7 +73,7 @@ if re.match("CfuPlugin_bus", pname): print(" wire {:10} {};".format(ppins[pname], pname)) last_cfu_port = pname - if pname == "clk": + if pname == "clk" or pname == "reset": last_cfu_port = pname print("\n\n") @@ -94,10 +94,12 @@ # print("Cfu Cfu(") for pname in pnames: - if re.match("CfuPlugin_bus_|^clk$", pname): + if re.match("CfuPlugin_bus_|^clk$|^reset$", pname): parts = pname.split("_"); if parts[0] == "CfuPlugin": parts[0] = "io" + if parts[0] == "reset": + parts[0] = "rst" cfu_pname = "_".join(parts) comma = "," if (pname != last_cfu_port) else "" print(" .{}({}){}".format(cfu_pname, pname, comma)) diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v index ce1e64d..3f4f226 100644 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v @@ -97,7 +97,8 @@ Cfu Cfu( .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), - .clk(clk) + .clk(clk), + .rst(reset) ); diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v index 6d9f587..22a4933 100644 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v @@ -113,7 +113,8 @@ Cfu Cfu( .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), - .clk(clk) + .clk(clk), + .rst(reset) ); diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfu.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfu.v new file mode 100644 index 0000000..8ae1d39 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfu.v @@ -0,0 +1,105 @@ +// +// wrapper auto-generated from VexRiscv_SlimCfu.v +// + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output iBusWishbone_CYC, + output iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + + + wire CfuPlugin_bus_cmd_valid; + wire CfuPlugin_bus_cmd_ready; + wire [9:0] CfuPlugin_bus_cmd_payload_function_id; + wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; + wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; + wire CfuPlugin_bus_rsp_valid; + wire CfuPlugin_bus_rsp_ready; + wire CfuPlugin_bus_rsp_payload_response_ok; + wire [31:0] CfuPlugin_bus_rsp_payload_outputs_0; + + + +VexRiscv_inner VexRiscv_inner( + .externalResetVector(externalResetVector), + .timerInterrupt(timerInterrupt), + .softwareInterrupt(softwareInterrupt), + .CfuPlugin_bus_cmd_valid(CfuPlugin_bus_cmd_valid), + .CfuPlugin_bus_cmd_ready(CfuPlugin_bus_cmd_ready), + .CfuPlugin_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), + .CfuPlugin_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), + .CfuPlugin_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), + .CfuPlugin_bus_rsp_valid(CfuPlugin_bus_rsp_valid), + .CfuPlugin_bus_rsp_ready(CfuPlugin_bus_rsp_ready), + .CfuPlugin_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), + .CfuPlugin_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), + .externalInterruptArray(externalInterruptArray), + .iBusWishbone_CYC(iBusWishbone_CYC), + .iBusWishbone_STB(iBusWishbone_STB), + .iBusWishbone_ACK(iBusWishbone_ACK), + .iBusWishbone_WE(iBusWishbone_WE), + .iBusWishbone_ADR(iBusWishbone_ADR), + .iBusWishbone_DAT_MISO(iBusWishbone_DAT_MISO), + .iBusWishbone_DAT_MOSI(iBusWishbone_DAT_MOSI), + .iBusWishbone_SEL(iBusWishbone_SEL), + .iBusWishbone_ERR(iBusWishbone_ERR), + .iBusWishbone_CTI(iBusWishbone_CTI), + .iBusWishbone_BTE(iBusWishbone_BTE), + .dBusWishbone_CYC(dBusWishbone_CYC), + .dBusWishbone_STB(dBusWishbone_STB), + .dBusWishbone_ACK(dBusWishbone_ACK), + .dBusWishbone_WE(dBusWishbone_WE), + .dBusWishbone_ADR(dBusWishbone_ADR), + .dBusWishbone_DAT_MISO(dBusWishbone_DAT_MISO), + .dBusWishbone_DAT_MOSI(dBusWishbone_DAT_MOSI), + .dBusWishbone_SEL(dBusWishbone_SEL), + .dBusWishbone_ERR(dBusWishbone_ERR), + .dBusWishbone_CTI(dBusWishbone_CTI), + .dBusWishbone_BTE(dBusWishbone_BTE), + .clk(clk), + .reset(reset) +); + + +Cfu Cfu( + .io_bus_cmd_valid(CfuPlugin_bus_cmd_valid), + .io_bus_cmd_ready(CfuPlugin_bus_cmd_ready), + .io_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), + .io_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), + .io_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), + .io_bus_rsp_valid(CfuPlugin_bus_rsp_valid), + .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), + .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), + .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), + .clk(clk), + .rst(reset) +); + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfuDebug.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfuDebug.v new file mode 100644 index 0000000..1c09f8f --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfuDebug.v @@ -0,0 +1,121 @@ +// +// wrapper auto-generated from VexRiscv_SlimCfuDebug.v +// + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBusWishbone_CYC, + output iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + + + wire CfuPlugin_bus_cmd_valid; + wire CfuPlugin_bus_cmd_ready; + wire [9:0] CfuPlugin_bus_cmd_payload_function_id; + wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; + wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; + wire CfuPlugin_bus_rsp_valid; + wire CfuPlugin_bus_rsp_ready; + wire CfuPlugin_bus_rsp_payload_response_ok; + wire [31:0] CfuPlugin_bus_rsp_payload_outputs_0; + + + +VexRiscv_inner VexRiscv_inner( + .externalResetVector(externalResetVector), + .timerInterrupt(timerInterrupt), + .softwareInterrupt(softwareInterrupt), + .CfuPlugin_bus_cmd_valid(CfuPlugin_bus_cmd_valid), + .CfuPlugin_bus_cmd_ready(CfuPlugin_bus_cmd_ready), + .CfuPlugin_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), + .CfuPlugin_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), + .CfuPlugin_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), + .CfuPlugin_bus_rsp_valid(CfuPlugin_bus_rsp_valid), + .CfuPlugin_bus_rsp_ready(CfuPlugin_bus_rsp_ready), + .CfuPlugin_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), + .CfuPlugin_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), + .externalInterruptArray(externalInterruptArray), + .debug_bus_cmd_valid(debug_bus_cmd_valid), + .debug_bus_cmd_ready(debug_bus_cmd_ready), + .debug_bus_cmd_payload_wr(debug_bus_cmd_payload_wr), + .debug_bus_cmd_payload_address(debug_bus_cmd_payload_address), + .debug_bus_cmd_payload_data(debug_bus_cmd_payload_data), + .debug_bus_rsp_data(debug_bus_rsp_data), + .debug_resetOut(debug_resetOut), + .iBusWishbone_CYC(iBusWishbone_CYC), + .iBusWishbone_STB(iBusWishbone_STB), + .iBusWishbone_ACK(iBusWishbone_ACK), + .iBusWishbone_WE(iBusWishbone_WE), + .iBusWishbone_ADR(iBusWishbone_ADR), + .iBusWishbone_DAT_MISO(iBusWishbone_DAT_MISO), + .iBusWishbone_DAT_MOSI(iBusWishbone_DAT_MOSI), + .iBusWishbone_SEL(iBusWishbone_SEL), + .iBusWishbone_ERR(iBusWishbone_ERR), + .iBusWishbone_CTI(iBusWishbone_CTI), + .iBusWishbone_BTE(iBusWishbone_BTE), + .dBusWishbone_CYC(dBusWishbone_CYC), + .dBusWishbone_STB(dBusWishbone_STB), + .dBusWishbone_ACK(dBusWishbone_ACK), + .dBusWishbone_WE(dBusWishbone_WE), + .dBusWishbone_ADR(dBusWishbone_ADR), + .dBusWishbone_DAT_MISO(dBusWishbone_DAT_MISO), + .dBusWishbone_DAT_MOSI(dBusWishbone_DAT_MOSI), + .dBusWishbone_SEL(dBusWishbone_SEL), + .dBusWishbone_ERR(dBusWishbone_ERR), + .dBusWishbone_CTI(dBusWishbone_CTI), + .dBusWishbone_BTE(dBusWishbone_BTE), + .clk(clk), + .reset(reset), + .debugReset(debugReset) +); + + +Cfu Cfu( + .io_bus_cmd_valid(CfuPlugin_bus_cmd_valid), + .io_bus_cmd_ready(CfuPlugin_bus_cmd_ready), + .io_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), + .io_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), + .io_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), + .io_bus_rsp_valid(CfuPlugin_bus_rsp_valid), + .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), + .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), + .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), + .clk(clk), + .rst(reset) +); + + +endmodule From 6db4891bfe4078a7b5fdad5e4653428f87060c21 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Thu, 29 Apr 2021 16:35:12 -0700 Subject: [PATCH 14/30] Slim: reduce Icache size to 1kB. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index 1a9acd9..d001f38 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -48,14 +48,14 @@ VexRiscv_FullCfuDebug.v: $(SRC) # CFU versions must have module name changed because they will be wrapped VexRiscv_SlimCfu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 2048 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfu" + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 1024 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfu" sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v /bin/mv tmp.v $@ ./genWrapper.py $@ > wrap$@ # CFU versions must have module name changed because they will be wrapped VexRiscv_SlimCfuDebug.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 2048 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfuDebug" + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 1024 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfuDebug" sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v /bin/mv tmp.v $@ ./genWrapper.py $@ > wrap$@ From 528360a7191bdbc0680626d1bac060849f006c30 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Thu, 29 Apr 2021 16:37:14 -0700 Subject: [PATCH 15/30] Rebuild SlimCfu CPUs w/ 1kB Icache. Signed-off-by: Tim Callahan --- .../verilog/VexRiscv_SlimCfu.v | 52 +++++++++---------- .../verilog/VexRiscv_SlimCfu.yaml | 2 +- .../verilog/VexRiscv_SlimCfuDebug.v | 52 +++++++++---------- .../verilog/VexRiscv_SlimCfuDebug.yaml | 2 +- 4 files changed, 54 insertions(+), 54 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v index 78b516c..058aa53 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : c8881985e0b323f1b12cab3ed0bd455d6c406944 +// Git hash : 6db4891bfe4078a7b5fdad5e4653428f87060c21 `define Input2Kind_defaultEncoding_type [0:0] @@ -5788,12 +5788,12 @@ module InstructionCache ( input reset ); reg [31:0] _zz_9; - reg [22:0] _zz_10; + reg [23:0] _zz_10; wire _zz_11; wire _zz_12; wire [0:0] _zz_13; wire [0:0] _zz_14; - wire [22:0] _zz_15; + wire [23:0] _zz_15; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -5801,7 +5801,7 @@ module InstructionCache ( (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; - reg [6:0] lineLoader_flushCounter; + reg [5:0] lineLoader_flushCounter; reg _zz_3; reg lineLoader_cmdSent; reg lineLoader_wayToAllocate_willIncrement; @@ -5810,23 +5810,23 @@ module InstructionCache ( wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; wire lineLoader_write_tag_0_valid; - wire [5:0] lineLoader_write_tag_0_payload_address; + wire [4:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire [21:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [8:0] lineLoader_write_data_0_payload_address; + wire [7:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [8:0] _zz_4; + wire [7:0] _zz_4; wire _zz_5; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_6; + wire [4:0] _zz_6; wire _zz_7; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8; + wire [21:0] fetchStage_read_waysValues_0_tag_address; + wire [23:0] _zz_8; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; @@ -5844,10 +5844,10 @@ module InstructionCache ( reg decodeStage_mmuRsp_bypassTranslation; reg decodeStage_hit_valid; reg decodeStage_hit_error; - (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; - (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; + (* ram_style = "block" *) reg [31:0] banks_0 [0:255]; + (* ram_style = "block" *) reg [23:0] ways_0_tags [0:31]; - assign _zz_11 = (! lineLoader_flushCounter[6]); + assign _zz_11 = (! lineLoader_flushCounter[5]); assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); assign _zz_13 = _zz_8[0 : 0]; assign _zz_14 = _zz_8[1 : 1]; @@ -5925,25 +5925,25 @@ module InstructionCache ( assign lineLoader_wayToAllocate_willClear = 1'b0; assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[5])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; + assign _zz_4 = io_cpu_prefetch_pc[9 : 2]; assign _zz_5 = (! io_cpu_fetch_isStuck); assign fetchStage_read_banksValue_0_dataMem = _zz_9; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; + assign _zz_6 = io_cpu_prefetch_pc[9 : 5]; assign _zz_7 = (! io_cpu_fetch_isStuck); assign _zz_8 = _zz_10; assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); + assign fetchStage_read_waysValues_0_tag_address = _zz_8[23 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 10])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; @@ -5999,11 +5999,11 @@ module InstructionCache ( lineLoader_address <= io_cpu_fill_payload; end if(_zz_11)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + lineLoader_flushCounter <= (lineLoader_flushCounter + 6'h01); end - _zz_3 <= lineLoader_flushCounter[6]; + _zz_3 <= lineLoader_flushCounter[5]; if(_zz_12)begin - lineLoader_flushCounter <= 7'h0; + lineLoader_flushCounter <= 6'h0; end if((! io_cpu_decode_isStuck))begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml index b55f8e5..6a862d2 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml @@ -1,4 +1,4 @@ iBus: !!vexriscv.BusReport flushInstructions: [4111, 19, 19, 19] - info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024} kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v index d92c012..64fdc05 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : c8881985e0b323f1b12cab3ed0bd455d6c406944 +// Git hash : 6db4891bfe4078a7b5fdad5e4653428f87060c21 `define Input2Kind_defaultEncoding_type [0:0] @@ -6062,12 +6062,12 @@ module InstructionCache ( input reset ); reg [31:0] _zz_11; - reg [22:0] _zz_12; + reg [23:0] _zz_12; wire _zz_13; wire _zz_14; wire [0:0] _zz_15; wire [0:0] _zz_16; - wire [22:0] _zz_17; + wire [23:0] _zz_17; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6075,7 +6075,7 @@ module InstructionCache ( (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; - reg [6:0] lineLoader_flushCounter; + reg [5:0] lineLoader_flushCounter; reg _zz_3; reg lineLoader_cmdSent; reg lineLoader_wayToAllocate_willIncrement; @@ -6084,23 +6084,23 @@ module InstructionCache ( wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; wire lineLoader_write_tag_0_valid; - wire [5:0] lineLoader_write_tag_0_payload_address; + wire [4:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire [21:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [8:0] lineLoader_write_data_0_payload_address; + wire [7:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [8:0] _zz_4; + wire [7:0] _zz_4; wire _zz_5; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_6; + wire [4:0] _zz_6; wire _zz_7; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8; + wire [21:0] fetchStage_read_waysValues_0_tag_address; + wire [23:0] _zz_8; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; @@ -6118,10 +6118,10 @@ module InstructionCache ( reg decodeStage_mmuRsp_bypassTranslation; reg decodeStage_hit_valid; reg decodeStage_hit_error; - (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; - (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; + (* ram_style = "block" *) reg [31:0] banks_0 [0:255]; + (* ram_style = "block" *) reg [23:0] ways_0_tags [0:31]; - assign _zz_13 = (! lineLoader_flushCounter[6]); + assign _zz_13 = (! lineLoader_flushCounter[5]); assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); assign _zz_15 = _zz_8[0 : 0]; assign _zz_16 = _zz_8[1 : 1]; @@ -6199,25 +6199,25 @@ module InstructionCache ( assign lineLoader_wayToAllocate_willClear = 1'b0; assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[5])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; + assign _zz_4 = io_cpu_prefetch_pc[9 : 2]; assign _zz_5 = (! io_cpu_fetch_isStuck); assign fetchStage_read_banksValue_0_dataMem = _zz_11; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; + assign _zz_6 = io_cpu_prefetch_pc[9 : 5]; assign _zz_7 = (! io_cpu_fetch_isStuck); assign _zz_8 = _zz_12; assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); + assign fetchStage_read_waysValues_0_tag_address = _zz_8[23 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 10])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; @@ -6273,11 +6273,11 @@ module InstructionCache ( lineLoader_address <= io_cpu_fill_payload; end if(_zz_13)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + lineLoader_flushCounter <= (lineLoader_flushCounter + 6'h01); end - _zz_3 <= lineLoader_flushCounter[6]; + _zz_3 <= lineLoader_flushCounter[5]; if(_zz_14)begin - lineLoader_flushCounter <= 7'h0; + lineLoader_flushCounter <= 6'h0; end if((! io_cpu_decode_isStuck))begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml index 75d2f32..d5a4c13 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml @@ -1,5 +1,5 @@ debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} iBus: !!vexriscv.BusReport flushInstructions: [4111, 19, 19, 19] - info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024} kind: cached From e78ff1c6772b33f1f3adf05557c1928a170ed641 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Wed, 2 Jun 2021 21:29:15 -0700 Subject: [PATCH 16/30] Remove wrapper mechanism for VexRiscv/CFU. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 12 -- .../verilog/wrapVexRiscv_FullCfu.v | 105 --------------- .../verilog/wrapVexRiscv_FullCfuDebug.v | 121 ------------------ .../verilog/wrapVexRiscv_SlimCfu.v | 105 --------------- .../verilog/wrapVexRiscv_SlimCfuDebug.v | 121 ------------------ 5 files changed, 464 deletions(-) delete mode 100644 pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v delete mode 100644 pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v delete mode 100644 pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfu.v delete mode 100644 pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfuDebug.v diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index d001f38..5a69c1f 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -35,30 +35,18 @@ VexRiscv_FullDebug.v: $(SRC) # CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfu.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfu" - sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v - /bin/mv tmp.v $@ - ./genWrapper.py $@ > wrap$@ # CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfuDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfuDebug" - sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v - /bin/mv tmp.v $@ - ./genWrapper.py $@ > wrap$@ # CFU versions must have module name changed because they will be wrapped VexRiscv_SlimCfu.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 1024 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfu" - sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v - /bin/mv tmp.v $@ - ./genWrapper.py $@ > wrap$@ # CFU versions must have module name changed because they will be wrapped VexRiscv_SlimCfuDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 1024 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfuDebug" - sed -e 's/module VexRiscv/module VexRiscv_inner/' $@ > tmp.v - /bin/mv tmp.v $@ - ./genWrapper.py $@ > wrap$@ VexRiscv_Linux.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal --outputFile VexRiscv_Linux" diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v deleted file mode 100644 index 3f4f226..0000000 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfu.v +++ /dev/null @@ -1,105 +0,0 @@ -// -// wrapper auto-generated from VexRiscv_FullCfu.v -// - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - output iBusWishbone_CYC, - output iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [2:0] iBusWishbone_CTI, - output [1:0] iBusWishbone_BTE, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [2:0] dBusWishbone_CTI, - output [1:0] dBusWishbone_BTE, - input clk, - input reset -); - - - wire CfuPlugin_bus_cmd_valid; - wire CfuPlugin_bus_cmd_ready; - wire [9:0] CfuPlugin_bus_cmd_payload_function_id; - wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; - wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; - wire CfuPlugin_bus_rsp_valid; - wire CfuPlugin_bus_rsp_ready; - wire CfuPlugin_bus_rsp_payload_response_ok; - wire [31:0] CfuPlugin_bus_rsp_payload_outputs_0; - - - -VexRiscv_inner VexRiscv_inner( - .externalResetVector(externalResetVector), - .timerInterrupt(timerInterrupt), - .softwareInterrupt(softwareInterrupt), - .CfuPlugin_bus_cmd_valid(CfuPlugin_bus_cmd_valid), - .CfuPlugin_bus_cmd_ready(CfuPlugin_bus_cmd_ready), - .CfuPlugin_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), - .CfuPlugin_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), - .CfuPlugin_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), - .CfuPlugin_bus_rsp_valid(CfuPlugin_bus_rsp_valid), - .CfuPlugin_bus_rsp_ready(CfuPlugin_bus_rsp_ready), - .CfuPlugin_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), - .CfuPlugin_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), - .externalInterruptArray(externalInterruptArray), - .iBusWishbone_CYC(iBusWishbone_CYC), - .iBusWishbone_STB(iBusWishbone_STB), - .iBusWishbone_ACK(iBusWishbone_ACK), - .iBusWishbone_WE(iBusWishbone_WE), - .iBusWishbone_ADR(iBusWishbone_ADR), - .iBusWishbone_DAT_MISO(iBusWishbone_DAT_MISO), - .iBusWishbone_DAT_MOSI(iBusWishbone_DAT_MOSI), - .iBusWishbone_SEL(iBusWishbone_SEL), - .iBusWishbone_ERR(iBusWishbone_ERR), - .iBusWishbone_CTI(iBusWishbone_CTI), - .iBusWishbone_BTE(iBusWishbone_BTE), - .dBusWishbone_CYC(dBusWishbone_CYC), - .dBusWishbone_STB(dBusWishbone_STB), - .dBusWishbone_ACK(dBusWishbone_ACK), - .dBusWishbone_WE(dBusWishbone_WE), - .dBusWishbone_ADR(dBusWishbone_ADR), - .dBusWishbone_DAT_MISO(dBusWishbone_DAT_MISO), - .dBusWishbone_DAT_MOSI(dBusWishbone_DAT_MOSI), - .dBusWishbone_SEL(dBusWishbone_SEL), - .dBusWishbone_ERR(dBusWishbone_ERR), - .dBusWishbone_CTI(dBusWishbone_CTI), - .dBusWishbone_BTE(dBusWishbone_BTE), - .clk(clk), - .reset(reset) -); - - -Cfu Cfu( - .io_bus_cmd_valid(CfuPlugin_bus_cmd_valid), - .io_bus_cmd_ready(CfuPlugin_bus_cmd_ready), - .io_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), - .io_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), - .io_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), - .io_bus_rsp_valid(CfuPlugin_bus_rsp_valid), - .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), - .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), - .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), - .clk(clk), - .rst(reset) -); - - -endmodule diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v deleted file mode 100644 index 22a4933..0000000 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_FullCfuDebug.v +++ /dev/null @@ -1,121 +0,0 @@ -// -// wrapper auto-generated from VexRiscv_FullCfuDebug.v -// - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - input debug_bus_cmd_valid, - output debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output [31:0] debug_bus_rsp_data, - output debug_resetOut, - output iBusWishbone_CYC, - output iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [2:0] iBusWishbone_CTI, - output [1:0] iBusWishbone_BTE, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [2:0] dBusWishbone_CTI, - output [1:0] dBusWishbone_BTE, - input clk, - input reset, - input debugReset -); - - - wire CfuPlugin_bus_cmd_valid; - wire CfuPlugin_bus_cmd_ready; - wire [9:0] CfuPlugin_bus_cmd_payload_function_id; - wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; - wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; - wire CfuPlugin_bus_rsp_valid; - wire CfuPlugin_bus_rsp_ready; - wire CfuPlugin_bus_rsp_payload_response_ok; - wire [31:0] CfuPlugin_bus_rsp_payload_outputs_0; - - - -VexRiscv_inner VexRiscv_inner( - .externalResetVector(externalResetVector), - .timerInterrupt(timerInterrupt), - .softwareInterrupt(softwareInterrupt), - .CfuPlugin_bus_cmd_valid(CfuPlugin_bus_cmd_valid), - .CfuPlugin_bus_cmd_ready(CfuPlugin_bus_cmd_ready), - .CfuPlugin_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), - .CfuPlugin_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), - .CfuPlugin_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), - .CfuPlugin_bus_rsp_valid(CfuPlugin_bus_rsp_valid), - .CfuPlugin_bus_rsp_ready(CfuPlugin_bus_rsp_ready), - .CfuPlugin_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), - .CfuPlugin_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), - .externalInterruptArray(externalInterruptArray), - .debug_bus_cmd_valid(debug_bus_cmd_valid), - .debug_bus_cmd_ready(debug_bus_cmd_ready), - .debug_bus_cmd_payload_wr(debug_bus_cmd_payload_wr), - .debug_bus_cmd_payload_address(debug_bus_cmd_payload_address), - .debug_bus_cmd_payload_data(debug_bus_cmd_payload_data), - .debug_bus_rsp_data(debug_bus_rsp_data), - .debug_resetOut(debug_resetOut), - .iBusWishbone_CYC(iBusWishbone_CYC), - .iBusWishbone_STB(iBusWishbone_STB), - .iBusWishbone_ACK(iBusWishbone_ACK), - .iBusWishbone_WE(iBusWishbone_WE), - .iBusWishbone_ADR(iBusWishbone_ADR), - .iBusWishbone_DAT_MISO(iBusWishbone_DAT_MISO), - .iBusWishbone_DAT_MOSI(iBusWishbone_DAT_MOSI), - .iBusWishbone_SEL(iBusWishbone_SEL), - .iBusWishbone_ERR(iBusWishbone_ERR), - .iBusWishbone_CTI(iBusWishbone_CTI), - .iBusWishbone_BTE(iBusWishbone_BTE), - .dBusWishbone_CYC(dBusWishbone_CYC), - .dBusWishbone_STB(dBusWishbone_STB), - .dBusWishbone_ACK(dBusWishbone_ACK), - .dBusWishbone_WE(dBusWishbone_WE), - .dBusWishbone_ADR(dBusWishbone_ADR), - .dBusWishbone_DAT_MISO(dBusWishbone_DAT_MISO), - .dBusWishbone_DAT_MOSI(dBusWishbone_DAT_MOSI), - .dBusWishbone_SEL(dBusWishbone_SEL), - .dBusWishbone_ERR(dBusWishbone_ERR), - .dBusWishbone_CTI(dBusWishbone_CTI), - .dBusWishbone_BTE(dBusWishbone_BTE), - .clk(clk), - .reset(reset), - .debugReset(debugReset) -); - - -Cfu Cfu( - .io_bus_cmd_valid(CfuPlugin_bus_cmd_valid), - .io_bus_cmd_ready(CfuPlugin_bus_cmd_ready), - .io_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), - .io_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), - .io_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), - .io_bus_rsp_valid(CfuPlugin_bus_rsp_valid), - .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), - .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), - .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), - .clk(clk), - .rst(reset) -); - - -endmodule diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfu.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfu.v deleted file mode 100644 index 8ae1d39..0000000 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfu.v +++ /dev/null @@ -1,105 +0,0 @@ -// -// wrapper auto-generated from VexRiscv_SlimCfu.v -// - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - output iBusWishbone_CYC, - output iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [2:0] iBusWishbone_CTI, - output [1:0] iBusWishbone_BTE, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [2:0] dBusWishbone_CTI, - output [1:0] dBusWishbone_BTE, - input clk, - input reset -); - - - wire CfuPlugin_bus_cmd_valid; - wire CfuPlugin_bus_cmd_ready; - wire [9:0] CfuPlugin_bus_cmd_payload_function_id; - wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; - wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; - wire CfuPlugin_bus_rsp_valid; - wire CfuPlugin_bus_rsp_ready; - wire CfuPlugin_bus_rsp_payload_response_ok; - wire [31:0] CfuPlugin_bus_rsp_payload_outputs_0; - - - -VexRiscv_inner VexRiscv_inner( - .externalResetVector(externalResetVector), - .timerInterrupt(timerInterrupt), - .softwareInterrupt(softwareInterrupt), - .CfuPlugin_bus_cmd_valid(CfuPlugin_bus_cmd_valid), - .CfuPlugin_bus_cmd_ready(CfuPlugin_bus_cmd_ready), - .CfuPlugin_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), - .CfuPlugin_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), - .CfuPlugin_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), - .CfuPlugin_bus_rsp_valid(CfuPlugin_bus_rsp_valid), - .CfuPlugin_bus_rsp_ready(CfuPlugin_bus_rsp_ready), - .CfuPlugin_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), - .CfuPlugin_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), - .externalInterruptArray(externalInterruptArray), - .iBusWishbone_CYC(iBusWishbone_CYC), - .iBusWishbone_STB(iBusWishbone_STB), - .iBusWishbone_ACK(iBusWishbone_ACK), - .iBusWishbone_WE(iBusWishbone_WE), - .iBusWishbone_ADR(iBusWishbone_ADR), - .iBusWishbone_DAT_MISO(iBusWishbone_DAT_MISO), - .iBusWishbone_DAT_MOSI(iBusWishbone_DAT_MOSI), - .iBusWishbone_SEL(iBusWishbone_SEL), - .iBusWishbone_ERR(iBusWishbone_ERR), - .iBusWishbone_CTI(iBusWishbone_CTI), - .iBusWishbone_BTE(iBusWishbone_BTE), - .dBusWishbone_CYC(dBusWishbone_CYC), - .dBusWishbone_STB(dBusWishbone_STB), - .dBusWishbone_ACK(dBusWishbone_ACK), - .dBusWishbone_WE(dBusWishbone_WE), - .dBusWishbone_ADR(dBusWishbone_ADR), - .dBusWishbone_DAT_MISO(dBusWishbone_DAT_MISO), - .dBusWishbone_DAT_MOSI(dBusWishbone_DAT_MOSI), - .dBusWishbone_SEL(dBusWishbone_SEL), - .dBusWishbone_ERR(dBusWishbone_ERR), - .dBusWishbone_CTI(dBusWishbone_CTI), - .dBusWishbone_BTE(dBusWishbone_BTE), - .clk(clk), - .reset(reset) -); - - -Cfu Cfu( - .io_bus_cmd_valid(CfuPlugin_bus_cmd_valid), - .io_bus_cmd_ready(CfuPlugin_bus_cmd_ready), - .io_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), - .io_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), - .io_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), - .io_bus_rsp_valid(CfuPlugin_bus_rsp_valid), - .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), - .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), - .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), - .clk(clk), - .rst(reset) -); - - -endmodule diff --git a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfuDebug.v b/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfuDebug.v deleted file mode 100644 index 1c09f8f..0000000 --- a/pythondata_cpu_vexriscv/verilog/wrapVexRiscv_SlimCfuDebug.v +++ /dev/null @@ -1,121 +0,0 @@ -// -// wrapper auto-generated from VexRiscv_SlimCfuDebug.v -// - -module VexRiscv ( - input [31:0] externalResetVector, - input timerInterrupt, - input softwareInterrupt, - input [31:0] externalInterruptArray, - input debug_bus_cmd_valid, - output debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output [31:0] debug_bus_rsp_data, - output debug_resetOut, - output iBusWishbone_CYC, - output iBusWishbone_STB, - input iBusWishbone_ACK, - output iBusWishbone_WE, - output [29:0] iBusWishbone_ADR, - input [31:0] iBusWishbone_DAT_MISO, - output [31:0] iBusWishbone_DAT_MOSI, - output [3:0] iBusWishbone_SEL, - input iBusWishbone_ERR, - output [2:0] iBusWishbone_CTI, - output [1:0] iBusWishbone_BTE, - output dBusWishbone_CYC, - output dBusWishbone_STB, - input dBusWishbone_ACK, - output dBusWishbone_WE, - output [29:0] dBusWishbone_ADR, - input [31:0] dBusWishbone_DAT_MISO, - output [31:0] dBusWishbone_DAT_MOSI, - output [3:0] dBusWishbone_SEL, - input dBusWishbone_ERR, - output [2:0] dBusWishbone_CTI, - output [1:0] dBusWishbone_BTE, - input clk, - input reset, - input debugReset -); - - - wire CfuPlugin_bus_cmd_valid; - wire CfuPlugin_bus_cmd_ready; - wire [9:0] CfuPlugin_bus_cmd_payload_function_id; - wire [31:0] CfuPlugin_bus_cmd_payload_inputs_0; - wire [31:0] CfuPlugin_bus_cmd_payload_inputs_1; - wire CfuPlugin_bus_rsp_valid; - wire CfuPlugin_bus_rsp_ready; - wire CfuPlugin_bus_rsp_payload_response_ok; - wire [31:0] CfuPlugin_bus_rsp_payload_outputs_0; - - - -VexRiscv_inner VexRiscv_inner( - .externalResetVector(externalResetVector), - .timerInterrupt(timerInterrupt), - .softwareInterrupt(softwareInterrupt), - .CfuPlugin_bus_cmd_valid(CfuPlugin_bus_cmd_valid), - .CfuPlugin_bus_cmd_ready(CfuPlugin_bus_cmd_ready), - .CfuPlugin_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), - .CfuPlugin_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), - .CfuPlugin_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), - .CfuPlugin_bus_rsp_valid(CfuPlugin_bus_rsp_valid), - .CfuPlugin_bus_rsp_ready(CfuPlugin_bus_rsp_ready), - .CfuPlugin_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), - .CfuPlugin_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), - .externalInterruptArray(externalInterruptArray), - .debug_bus_cmd_valid(debug_bus_cmd_valid), - .debug_bus_cmd_ready(debug_bus_cmd_ready), - .debug_bus_cmd_payload_wr(debug_bus_cmd_payload_wr), - .debug_bus_cmd_payload_address(debug_bus_cmd_payload_address), - .debug_bus_cmd_payload_data(debug_bus_cmd_payload_data), - .debug_bus_rsp_data(debug_bus_rsp_data), - .debug_resetOut(debug_resetOut), - .iBusWishbone_CYC(iBusWishbone_CYC), - .iBusWishbone_STB(iBusWishbone_STB), - .iBusWishbone_ACK(iBusWishbone_ACK), - .iBusWishbone_WE(iBusWishbone_WE), - .iBusWishbone_ADR(iBusWishbone_ADR), - .iBusWishbone_DAT_MISO(iBusWishbone_DAT_MISO), - .iBusWishbone_DAT_MOSI(iBusWishbone_DAT_MOSI), - .iBusWishbone_SEL(iBusWishbone_SEL), - .iBusWishbone_ERR(iBusWishbone_ERR), - .iBusWishbone_CTI(iBusWishbone_CTI), - .iBusWishbone_BTE(iBusWishbone_BTE), - .dBusWishbone_CYC(dBusWishbone_CYC), - .dBusWishbone_STB(dBusWishbone_STB), - .dBusWishbone_ACK(dBusWishbone_ACK), - .dBusWishbone_WE(dBusWishbone_WE), - .dBusWishbone_ADR(dBusWishbone_ADR), - .dBusWishbone_DAT_MISO(dBusWishbone_DAT_MISO), - .dBusWishbone_DAT_MOSI(dBusWishbone_DAT_MOSI), - .dBusWishbone_SEL(dBusWishbone_SEL), - .dBusWishbone_ERR(dBusWishbone_ERR), - .dBusWishbone_CTI(dBusWishbone_CTI), - .dBusWishbone_BTE(dBusWishbone_BTE), - .clk(clk), - .reset(reset), - .debugReset(debugReset) -); - - -Cfu Cfu( - .io_bus_cmd_valid(CfuPlugin_bus_cmd_valid), - .io_bus_cmd_ready(CfuPlugin_bus_cmd_ready), - .io_bus_cmd_payload_function_id(CfuPlugin_bus_cmd_payload_function_id), - .io_bus_cmd_payload_inputs_0(CfuPlugin_bus_cmd_payload_inputs_0), - .io_bus_cmd_payload_inputs_1(CfuPlugin_bus_cmd_payload_inputs_1), - .io_bus_rsp_valid(CfuPlugin_bus_rsp_valid), - .io_bus_rsp_ready(CfuPlugin_bus_rsp_ready), - .io_bus_rsp_payload_response_ok(CfuPlugin_bus_rsp_payload_response_ok), - .io_bus_rsp_payload_outputs_0(CfuPlugin_bus_rsp_payload_outputs_0), - .clk(clk), - .rst(reset) -); - - -endmodule From aa12b0d45ab170fd03927c0d06fa62f6bd8e840f Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Wed, 2 Jun 2021 21:38:19 -0700 Subject: [PATCH 17/30] Rebuild Verilogs at hash e78ff1c. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/VexRiscv.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v | 4 ++-- pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v | 4 ++-- pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v | 2 +- pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v | 4 ++-- pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v | 4 ++-- 17 files changed, 21 insertions(+), 21 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv.v b/pythondata_cpu_vexriscv/verilog/VexRiscv.v index 8a23a18..f4629e6 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v index d5319fc..21879f2 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v index ace5e1a..6d43c55 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index aec1870..00fd249 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : eafff82697ae47892bb4654e4bb7d282a4b9807c +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define Input2Kind_defaultEncoding_type [0:0] @@ -48,7 +48,7 @@ `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -module VexRiscv_inner ( +module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index 868da11..f54d4b8 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : eafff82697ae47892bb4654e4bb7d282a4b9807c +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define Input2Kind_defaultEncoding_type [0:0] @@ -48,7 +48,7 @@ `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -module VexRiscv_inner ( +module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v index c944f80..4d3116e 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v index 6d1a3b4..7ca7550 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v index 9d11f1a..c0e4bb3 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v index d014909..3ebd2f1 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v index 3ce89ef..6330d5a 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v index 389fed5..dd57d2f 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v index 115224b..4dd8855 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v index 2ec5a6a..92696e4 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v index 490f8bc..ea879f1 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v index f1b3c6a..a777070 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9f870869a08c2f08812676be9bb2baffad2dbfe2 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define EnvCtrlEnum_defaultEncoding_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v index 058aa53..7cb4c40 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 6db4891bfe4078a7b5fdad5e4653428f87060c21 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define Input2Kind_defaultEncoding_type [0:0] @@ -48,7 +48,7 @@ `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -module VexRiscv_inner ( +module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v index 64fdc05..65db630 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 6db4891bfe4078a7b5fdad5e4653428f87060c21 +// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 `define Input2Kind_defaultEncoding_type [0:0] @@ -48,7 +48,7 @@ `define Src1CtrlEnum_defaultEncoding_URS1 2'b11 -module VexRiscv_inner ( +module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, From 848042f3e4812615884ef1061d617c4d5bf6e8c2 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Fri, 11 Jun 2021 11:30:37 -0700 Subject: [PATCH 18/30] Add VexRiscv for Fomu -- minimal, plus hard muldiv, plus mcycle. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 8 +- .../verilog/VexRiscv_Fomu.v | 4371 +++++++++++++++ .../verilog/VexRiscv_Fomu.yaml | 1 + .../verilog/VexRiscv_FomuCfu.v | 4935 +++++++++++++++++ .../verilog/VexRiscv_FomuCfu.yaml | 1 + .../main/scala/vexriscv/GenCoreDefault.scala | 4 +- 6 files changed, 9318 insertions(+), 2 deletions(-) create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index 5a69c1f..bce4596 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -1,6 +1,6 @@ SRC := ${shell find . -type f -name \*.scala} -all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_SlimCfu.v VexRiscv_SlimCfuDebug.v +all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_SlimCfu.v VexRiscv_SlimCfuDebug.v VexRiscv_Fomu.v VexRiscv_FomuCfu.v VexRiscv.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault" @@ -26,6 +26,12 @@ VexRiscv_Min.v: $(SRC) VexRiscv_MinDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 0 --dCacheSize 0 --mulDiv false --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_MinDebug" +VexRiscv_Fomu.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault --iCacheSize 0 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_Fomu" + +VexRiscv_FomuCfu.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault -d --cfu true --iCacheSize 0 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_FomuCfu" + VexRiscv_Full.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --outputFile VexRiscv_Full" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v new file mode 100644 index 0000000..3f216eb --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v @@ -0,0 +1,4371 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : aa12b0d45ab170fd03927c0d06fa62f6bd8e840f + + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output iBusWishbone_CYC, + output iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_134; + wire _zz_135; + reg [31:0] _zz_136; + reg [31:0] _zz_137; + reg [31:0] _zz_138; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_139; + wire _zz_140; + wire _zz_141; + wire _zz_142; + wire _zz_143; + wire _zz_144; + wire _zz_145; + wire _zz_146; + wire _zz_147; + wire [1:0] _zz_148; + wire _zz_149; + wire _zz_150; + wire _zz_151; + wire _zz_152; + wire _zz_153; + wire _zz_154; + wire _zz_155; + wire _zz_156; + wire _zz_157; + wire _zz_158; + wire _zz_159; + wire _zz_160; + wire _zz_161; + wire _zz_162; + wire _zz_163; + wire _zz_164; + wire _zz_165; + wire _zz_166; + wire _zz_167; + wire [1:0] _zz_168; + wire _zz_169; + wire [0:0] _zz_170; + wire [0:0] _zz_171; + wire [0:0] _zz_172; + wire [0:0] _zz_173; + wire [0:0] _zz_174; + wire [0:0] _zz_175; + wire [0:0] _zz_176; + wire [0:0] _zz_177; + wire [0:0] _zz_178; + wire [0:0] _zz_179; + wire [0:0] _zz_180; + wire [0:0] _zz_181; + wire [0:0] _zz_182; + wire [0:0] _zz_183; + wire [0:0] _zz_184; + wire [2:0] _zz_185; + wire [2:0] _zz_186; + wire [31:0] _zz_187; + wire [2:0] _zz_188; + wire [0:0] _zz_189; + wire [2:0] _zz_190; + wire [0:0] _zz_191; + wire [2:0] _zz_192; + wire [0:0] _zz_193; + wire [2:0] _zz_194; + wire [0:0] _zz_195; + wire [2:0] _zz_196; + wire [2:0] _zz_197; + wire [0:0] _zz_198; + wire [2:0] _zz_199; + wire [4:0] _zz_200; + wire [11:0] _zz_201; + wire [11:0] _zz_202; + wire [31:0] _zz_203; + wire [31:0] _zz_204; + wire [31:0] _zz_205; + wire [31:0] _zz_206; + wire [31:0] _zz_207; + wire [31:0] _zz_208; + wire [31:0] _zz_209; + wire [31:0] _zz_210; + wire [32:0] _zz_211; + wire [19:0] _zz_212; + wire [11:0] _zz_213; + wire [11:0] _zz_214; + wire [1:0] _zz_215; + wire [1:0] _zz_216; + wire [1:0] _zz_217; + wire [1:0] _zz_218; + wire [0:0] _zz_219; + wire [5:0] _zz_220; + wire [33:0] _zz_221; + wire [32:0] _zz_222; + wire [33:0] _zz_223; + wire [32:0] _zz_224; + wire [33:0] _zz_225; + wire [32:0] _zz_226; + wire [0:0] _zz_227; + wire [5:0] _zz_228; + wire [32:0] _zz_229; + wire [31:0] _zz_230; + wire [31:0] _zz_231; + wire [32:0] _zz_232; + wire [32:0] _zz_233; + wire [32:0] _zz_234; + wire [32:0] _zz_235; + wire [0:0] _zz_236; + wire [32:0] _zz_237; + wire [0:0] _zz_238; + wire [32:0] _zz_239; + wire [0:0] _zz_240; + wire [31:0] _zz_241; + wire [0:0] _zz_242; + wire [0:0] _zz_243; + wire [0:0] _zz_244; + wire [0:0] _zz_245; + wire [0:0] _zz_246; + wire [0:0] _zz_247; + wire _zz_248; + wire _zz_249; + wire [1:0] _zz_250; + wire [31:0] _zz_251; + wire [31:0] _zz_252; + wire [31:0] _zz_253; + wire _zz_254; + wire [0:0] _zz_255; + wire [12:0] _zz_256; + wire [31:0] _zz_257; + wire [31:0] _zz_258; + wire [31:0] _zz_259; + wire _zz_260; + wire [0:0] _zz_261; + wire [6:0] _zz_262; + wire [31:0] _zz_263; + wire [31:0] _zz_264; + wire [31:0] _zz_265; + wire _zz_266; + wire [0:0] _zz_267; + wire [0:0] _zz_268; + wire [31:0] _zz_269; + wire [0:0] _zz_270; + wire [1:0] _zz_271; + wire [0:0] _zz_272; + wire [0:0] _zz_273; + wire _zz_274; + wire [0:0] _zz_275; + wire [23:0] _zz_276; + wire [31:0] _zz_277; + wire [31:0] _zz_278; + wire [31:0] _zz_279; + wire [0:0] _zz_280; + wire [0:0] _zz_281; + wire [1:0] _zz_282; + wire [1:0] _zz_283; + wire _zz_284; + wire [0:0] _zz_285; + wire [19:0] _zz_286; + wire [31:0] _zz_287; + wire [31:0] _zz_288; + wire [31:0] _zz_289; + wire [31:0] _zz_290; + wire [31:0] _zz_291; + wire [31:0] _zz_292; + wire [0:0] _zz_293; + wire [0:0] _zz_294; + wire [2:0] _zz_295; + wire [2:0] _zz_296; + wire _zz_297; + wire [0:0] _zz_298; + wire [16:0] _zz_299; + wire [31:0] _zz_300; + wire [31:0] _zz_301; + wire [31:0] _zz_302; + wire [31:0] _zz_303; + wire _zz_304; + wire _zz_305; + wire _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire _zz_312; + wire [0:0] _zz_313; + wire [13:0] _zz_314; + wire [31:0] _zz_315; + wire [31:0] _zz_316; + wire [31:0] _zz_317; + wire [31:0] _zz_318; + wire [31:0] _zz_319; + wire [31:0] _zz_320; + wire [31:0] _zz_321; + wire [31:0] _zz_322; + wire [0:0] _zz_323; + wire [0:0] _zz_324; + wire [1:0] _zz_325; + wire [1:0] _zz_326; + wire _zz_327; + wire [0:0] _zz_328; + wire [11:0] _zz_329; + wire [31:0] _zz_330; + wire [31:0] _zz_331; + wire [31:0] _zz_332; + wire [31:0] _zz_333; + wire [31:0] _zz_334; + wire [31:0] _zz_335; + wire _zz_336; + wire [0:0] _zz_337; + wire [0:0] _zz_338; + wire _zz_339; + wire [0:0] _zz_340; + wire [0:0] _zz_341; + wire _zz_342; + wire [0:0] _zz_343; + wire [8:0] _zz_344; + wire [31:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [0:0] _zz_348; + wire [0:0] _zz_349; + wire [0:0] _zz_350; + wire [4:0] _zz_351; + wire [1:0] _zz_352; + wire [1:0] _zz_353; + wire _zz_354; + wire [0:0] _zz_355; + wire [5:0] _zz_356; + wire [31:0] _zz_357; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire [31:0] _zz_360; + wire _zz_361; + wire [0:0] _zz_362; + wire [1:0] _zz_363; + wire [31:0] _zz_364; + wire [31:0] _zz_365; + wire _zz_366; + wire [0:0] _zz_367; + wire [0:0] _zz_368; + wire [0:0] _zz_369; + wire [0:0] _zz_370; + wire _zz_371; + wire [0:0] _zz_372; + wire [2:0] _zz_373; + wire [31:0] _zz_374; + wire [31:0] _zz_375; + wire [31:0] _zz_376; + wire _zz_377; + wire _zz_378; + wire [31:0] _zz_379; + wire [31:0] _zz_380; + wire [31:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire [31:0] _zz_384; + wire [31:0] _zz_385; + wire [0:0] _zz_386; + wire [2:0] _zz_387; + wire [0:0] _zz_388; + wire [0:0] _zz_389; + wire _zz_390; + wire [0:0] _zz_391; + wire [0:0] _zz_392; + wire [31:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire _zz_396; + wire _zz_397; + wire [31:0] _zz_398; + wire _zz_399; + wire [0:0] _zz_400; + wire [0:0] _zz_401; + wire [0:0] _zz_402; + wire [0:0] _zz_403; + wire [0:0] _zz_404; + wire [0:0] _zz_405; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire [31:0] decode_RS2; + wire [31:0] decode_RS1; + wire decode_IS_DIV; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `BranchCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_17; + wire `Src2CtrlEnum_defaultEncoding_type _zz_18; + wire `Src2CtrlEnum_defaultEncoding_type _zz_19; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_MUL; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + reg [31:0] _zz_26; + wire memory_IS_MUL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] _zz_31; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_32; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_33; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_34; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_35; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_36; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_37; + wire [31:0] _zz_38; + wire _zz_39; + reg _zz_40; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_41; + wire `BranchCtrlEnum_defaultEncoding_type _zz_42; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_43; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_44; + wire `Src2CtrlEnum_defaultEncoding_type _zz_45; + wire `AluCtrlEnum_defaultEncoding_type _zz_46; + wire `Src1CtrlEnum_defaultEncoding_type _zz_47; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_48; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP2_physicalAddress; + wire memory_MMU_RSP2_isIoAccess; + wire memory_MMU_RSP2_isPaging; + wire memory_MMU_RSP2_allowRead; + wire memory_MMU_RSP2_allowWrite; + wire memory_MMU_RSP2_allowExecute; + wire memory_MMU_RSP2_exception; + wire memory_MMU_RSP2_refilling; + wire memory_MMU_RSP2_bypassTranslation; + wire [31:0] memory_PC; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire execute_MMU_FAULT; + wire [31:0] execute_MMU_RSP2_physicalAddress; + wire execute_MMU_RSP2_isIoAccess; + wire execute_MMU_RSP2_isPaging; + wire execute_MMU_RSP2_allowRead; + wire execute_MMU_RSP2_allowWrite; + wire execute_MMU_RSP2_allowExecute; + wire execute_MMU_RSP2_exception; + wire execute_MMU_RSP2_refilling; + wire execute_MMU_RSP2_bypassTranslation; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire decode_MEMORY_ENABLE; + reg [31:0] _zz_49; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusSimplePlugin_fetcherHalt; + reg IBusSimplePlugin_incomingInstruction; + wire IBusSimplePlugin_pcValids_0; + wire IBusSimplePlugin_pcValids_1; + wire IBusSimplePlugin_pcValids_2; + wire IBusSimplePlugin_pcValids_3; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + wire [31:0] iBus_cmd_payload_pc; + wire iBus_rsp_valid; + wire iBus_rsp_payload_error; + wire [31:0] iBus_rsp_payload_inst; + wire IBusSimplePlugin_decodeExceptionPort_valid; + reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; + wire IBusSimplePlugin_mmuBus_cmd_0_isValid; + wire IBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire IBusSimplePlugin_mmuBus_rsp_isPaging; + wire IBusSimplePlugin_mmuBus_rsp_allowRead; + wire IBusSimplePlugin_mmuBus_rsp_allowWrite; + wire IBusSimplePlugin_mmuBus_rsp_allowExecute; + wire IBusSimplePlugin_mmuBus_rsp_exception; + wire IBusSimplePlugin_mmuBus_rsp_refilling; + wire IBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire IBusSimplePlugin_mmuBus_end; + wire IBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire DBusSimplePlugin_mmuBus_cmd_0_isValid; + wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire DBusSimplePlugin_mmuBus_rsp_isPaging; + wire DBusSimplePlugin_mmuBus_rsp_allowRead; + wire DBusSimplePlugin_mmuBus_rsp_allowWrite; + wire DBusSimplePlugin_mmuBus_rsp_allowExecute; + wire DBusSimplePlugin_mmuBus_rsp_exception; + wire DBusSimplePlugin_mmuBus_rsp_refilling; + wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire DBusSimplePlugin_mmuBus_end; + wire DBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_redoBranch_valid; + wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusSimplePlugin_externalFlush; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire [2:0] _zz_50; + wire [2:0] _zz_51; + wire _zz_52; + wire _zz_53; + wire IBusSimplePlugin_fetchPc_output_valid; + wire IBusSimplePlugin_fetchPc_output_ready; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusSimplePlugin_fetchPc_correction; + reg IBusSimplePlugin_fetchPc_correctionReg; + wire IBusSimplePlugin_fetchPc_corrected; + reg IBusSimplePlugin_fetchPc_pcRegPropagate; + reg IBusSimplePlugin_fetchPc_booted; + reg IBusSimplePlugin_fetchPc_inc; + reg [31:0] IBusSimplePlugin_fetchPc_pc; + wire IBusSimplePlugin_fetchPc_redo_valid; + wire [31:0] IBusSimplePlugin_fetchPc_redo_payload; + reg IBusSimplePlugin_fetchPc_flushed; + reg IBusSimplePlugin_iBusRsp_redoFetch; + wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + reg IBusSimplePlugin_iBusRsp_stages_0_halt; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_halt; + wire _zz_54; + wire _zz_55; + wire IBusSimplePlugin_iBusRsp_flush; + wire _zz_56; + wire _zz_57; + reg _zz_58; + reg IBusSimplePlugin_iBusRsp_readyForError; + wire IBusSimplePlugin_iBusRsp_output_valid; + wire IBusSimplePlugin_iBusRsp_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; + wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; + wire IBusSimplePlugin_injector_decodeInput_valid; + wire IBusSimplePlugin_injector_decodeInput_ready; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; + wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; + reg _zz_59; + reg [31:0] _zz_60; + reg _zz_61; + reg [31:0] _zz_62; + reg _zz_63; + reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; + reg IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_ready; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + wire IBusSimplePlugin_pending_inc; + wire IBusSimplePlugin_pending_dec; + reg [2:0] IBusSimplePlugin_pending_value; + wire [2:0] IBusSimplePlugin_pending_next; + wire IBusSimplePlugin_cmdFork_canEmit; + reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; + reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; + reg IBusSimplePlugin_mmu_joinCtx_isPaging; + reg IBusSimplePlugin_mmu_joinCtx_allowRead; + reg IBusSimplePlugin_mmu_joinCtx_allowWrite; + reg IBusSimplePlugin_mmu_joinCtx_allowExecute; + reg IBusSimplePlugin_mmu_joinCtx_exception; + reg IBusSimplePlugin_mmu_joinCtx_refilling; + reg IBusSimplePlugin_mmu_joinCtx_bypassTranslation; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_join_ready; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_payload_isRvc; + reg IBusSimplePlugin_rspJoin_exceptionDetected; + wire _zz_64; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire _zz_65; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_66; + reg [3:0] _zz_67; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_68; + reg [31:0] _zz_69; + wire _zz_70; + reg [31:0] _zz_71; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [29:0] _zz_72; + wire _zz_73; + wire _zz_74; + wire _zz_75; + wire _zz_76; + wire _zz_77; + wire _zz_78; + wire `Src1CtrlEnum_defaultEncoding_type _zz_79; + wire `AluCtrlEnum_defaultEncoding_type _zz_80; + wire `Src2CtrlEnum_defaultEncoding_type _zz_81; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_82; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_83; + wire `BranchCtrlEnum_defaultEncoding_type _zz_84; + wire `EnvCtrlEnum_defaultEncoding_type _zz_85; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_86; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_87; + reg [31:0] _zz_88; + wire _zz_89; + reg [19:0] _zz_90; + wire _zz_91; + reg [19:0] _zz_92; + reg [31:0] _zz_93; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_94; + reg _zz_95; + reg _zz_96; + reg _zz_97; + reg [4:0] _zz_98; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_99; + reg _zz_100; + reg _zz_101; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_102; + reg [10:0] _zz_103; + wire _zz_104; + reg [19:0] _zz_105; + wire _zz_106; + reg [18:0] _zz_107; + reg [31:0] _zz_108; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_109; + wire _zz_110; + wire _zz_111; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_112; + wire _zz_113; + wire [1:0] _zz_114; + wire _zz_115; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_mul_counter_willIncrement; + reg memory_MulDivIterativePlugin_mul_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; + wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire [31:0] _zz_116; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [31:0] _zz_117; + wire _zz_118; + wire _zz_119; + reg [32:0] _zz_120; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_121; + wire [31:0] _zz_122; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; + reg execute_to_memory_MMU_RSP2_isIoAccess; + reg execute_to_memory_MMU_RSP2_isPaging; + reg execute_to_memory_MMU_RSP2_allowRead; + reg execute_to_memory_MMU_RSP2_allowWrite; + reg execute_to_memory_MMU_RSP2_allowExecute; + reg execute_to_memory_MMU_RSP2_exception; + reg execute_to_memory_MMU_RSP2_refilling; + reg execute_to_memory_MMU_RSP2_bypassTranslation; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_123; + reg [31:0] _zz_124; + reg [31:0] _zz_125; + reg [31:0] _zz_126; + reg [31:0] _zz_127; + reg [31:0] _zz_128; + reg [31:0] _zz_129; + reg [31:0] _zz_130; + reg [31:0] _zz_131; + reg [31:0] _zz_132; + wire iBus_cmd_m2sPipe_valid; + wire iBus_cmd_m2sPipe_ready; + wire [31:0] iBus_cmd_m2sPipe_payload_pc; + reg iBus_cmd_m2sPipe_rValid; + reg [31:0] iBus_cmd_m2sPipe_rData_pc; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_133; + `ifndef SYNTHESIS + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [31:0] _zz_10_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_11_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_14_string; + reg [39:0] _zz_15_string; + reg [39:0] _zz_16_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_17_string; + reg [23:0] _zz_18_string; + reg [23:0] _zz_19_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_20_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_23_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_27_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_29_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_30_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_32_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_34_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_35_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_36_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_37_string; + reg [39:0] _zz_41_string; + reg [31:0] _zz_42_string; + reg [71:0] _zz_43_string; + reg [39:0] _zz_44_string; + reg [23:0] _zz_45_string; + reg [63:0] _zz_46_string; + reg [95:0] _zz_47_string; + reg [95:0] _zz_79_string; + reg [63:0] _zz_80_string; + reg [23:0] _zz_81_string; + reg [39:0] _zz_82_string; + reg [71:0] _zz_83_string; + reg [31:0] _zz_84_string; + reg [39:0] _zz_85_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_139 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_140 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_141 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_142 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_143 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_144 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_145 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_146 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_147 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_148 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_149 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); + assign _zz_150 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_151 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_152 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_153 = (1'b1 || (! 1'b1)); + assign _zz_154 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_155 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_156 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_157 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_158 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_159 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_160 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_161 = (! memory_arbitration_isStuck); + assign _zz_162 = (! execute_arbitration_isStuckByOthers); + assign _zz_163 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_164 = ((_zz_109 && 1'b1) && (! 1'b0)); + assign _zz_165 = ((_zz_110 && 1'b1) && (! 1'b0)); + assign _zz_166 = ((_zz_111 && 1'b1) && (! 1'b0)); + assign _zz_167 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_168 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_169 = execute_INSTRUCTION[13]; + assign _zz_170 = _zz_72[29 : 29]; + assign _zz_171 = _zz_72[28 : 28]; + assign _zz_172 = _zz_72[27 : 27]; + assign _zz_173 = _zz_72[26 : 26]; + assign _zz_174 = _zz_72[23 : 23]; + assign _zz_175 = _zz_72[15 : 15]; + assign _zz_176 = _zz_72[12 : 12]; + assign _zz_177 = _zz_72[11 : 11]; + assign _zz_178 = _zz_72[10 : 10]; + assign _zz_179 = _zz_72[14 : 14]; + assign _zz_180 = _zz_72[4 : 4]; + assign _zz_181 = _zz_72[2 : 2]; + assign _zz_182 = _zz_72[18 : 18]; + assign _zz_183 = _zz_72[9 : 9]; + assign _zz_184 = _zz_72[3 : 3]; + assign _zz_185 = (_zz_50 - 3'b001); + assign _zz_186 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_187 = {29'd0, _zz_186}; + assign _zz_188 = (IBusSimplePlugin_pending_value + _zz_190); + assign _zz_189 = IBusSimplePlugin_pending_inc; + assign _zz_190 = {2'd0, _zz_189}; + assign _zz_191 = IBusSimplePlugin_pending_dec; + assign _zz_192 = {2'd0, _zz_191}; + assign _zz_193 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_194 = {2'd0, _zz_193}; + assign _zz_195 = IBusSimplePlugin_pending_dec; + assign _zz_196 = {2'd0, _zz_195}; + assign _zz_197 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_198 = execute_SRC_LESS; + assign _zz_199 = 3'b100; + assign _zz_200 = execute_INSTRUCTION[19 : 15]; + assign _zz_201 = execute_INSTRUCTION[31 : 20]; + assign _zz_202 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_203 = ($signed(_zz_204) + $signed(_zz_207)); + assign _zz_204 = ($signed(_zz_205) + $signed(_zz_206)); + assign _zz_205 = execute_SRC1; + assign _zz_206 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_207 = (execute_SRC_USE_SUB_LESS ? _zz_208 : _zz_209); + assign _zz_208 = 32'h00000001; + assign _zz_209 = 32'h0; + assign _zz_210 = (_zz_211 >>> 1); + assign _zz_211 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_212 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_213 = execute_INSTRUCTION[31 : 20]; + assign _zz_214 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_215 = (_zz_112 & (~ _zz_216)); + assign _zz_216 = (_zz_112 - 2'b01); + assign _zz_217 = (_zz_114 & (~ _zz_218)); + assign _zz_218 = (_zz_114 - 2'b01); + assign _zz_219 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_220 = {5'd0, _zz_219}; + assign _zz_221 = (_zz_223 + _zz_225); + assign _zz_222 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_223 = {{1{_zz_222[32]}}, _zz_222}; + assign _zz_224 = _zz_226; + assign _zz_225 = {{1{_zz_224[32]}}, _zz_224}; + assign _zz_226 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_227 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_228 = {5'd0, _zz_227}; + assign _zz_229 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_230 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_231 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_232 = {_zz_116,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_233 = _zz_234; + assign _zz_234 = _zz_235; + assign _zz_235 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_117) : _zz_117)} + _zz_237); + assign _zz_236 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_237 = {32'd0, _zz_236}; + assign _zz_238 = _zz_119; + assign _zz_239 = {32'd0, _zz_238}; + assign _zz_240 = _zz_118; + assign _zz_241 = {31'd0, _zz_240}; + assign _zz_242 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_243 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_244 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_245 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_246 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_247 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_248 = 1'b1; + assign _zz_249 = 1'b1; + assign _zz_250 = {_zz_53,_zz_52}; + assign _zz_251 = 32'h0000107f; + assign _zz_252 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_253 = 32'h00002073; + assign _zz_254 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_255 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_256 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_257) == 32'h00000003),{(_zz_258 == _zz_259),{_zz_260,{_zz_261,_zz_262}}}}}}; + assign _zz_257 = 32'h0000505f; + assign _zz_258 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_259 = 32'h00000063; + assign _zz_260 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_261 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_262 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_263) == 32'h00005033),{(_zz_264 == _zz_265),{_zz_266,{_zz_267,_zz_268}}}}}}; + assign _zz_263 = 32'hbe00707f; + assign _zz_264 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_265 = 32'h00000033; + assign _zz_266 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_267 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_268 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_269 = 32'h02004064; + assign _zz_270 = _zz_78; + assign _zz_271 = {_zz_76,_zz_77}; + assign _zz_272 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_273 = 1'b0; + assign _zz_274 = (((decode_INSTRUCTION & _zz_277) == 32'h00000050) != 1'b0); + assign _zz_275 = ((_zz_278 == _zz_279) != 1'b0); + assign _zz_276 = {({_zz_280,_zz_281} != 2'b00),{(_zz_282 != _zz_283),{_zz_284,{_zz_285,_zz_286}}}}; + assign _zz_277 = 32'h10003050; + assign _zz_278 = (decode_INSTRUCTION & 32'h10403050); + assign _zz_279 = 32'h10000050; + assign _zz_280 = ((decode_INSTRUCTION & _zz_287) == 32'h00001050); + assign _zz_281 = ((decode_INSTRUCTION & _zz_288) == 32'h00002050); + assign _zz_282 = {_zz_75,(_zz_289 == _zz_290)}; + assign _zz_283 = 2'b00; + assign _zz_284 = ((_zz_291 == _zz_292) != 1'b0); + assign _zz_285 = ({_zz_293,_zz_294} != 2'b00); + assign _zz_286 = {(_zz_295 != _zz_296),{_zz_297,{_zz_298,_zz_299}}}; + assign _zz_287 = 32'h00001050; + assign _zz_288 = 32'h00002050; + assign _zz_289 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_290 = 32'h00000004; + assign _zz_291 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_292 = 32'h00000040; + assign _zz_293 = ((decode_INSTRUCTION & _zz_300) == 32'h00005010); + assign _zz_294 = ((decode_INSTRUCTION & _zz_301) == 32'h00005020); + assign _zz_295 = {(_zz_302 == _zz_303),{_zz_304,_zz_305}}; + assign _zz_296 = 3'b000; + assign _zz_297 = ({_zz_306,{_zz_307,_zz_308}} != 3'b000); + assign _zz_298 = (_zz_309 != 1'b0); + assign _zz_299 = {(_zz_310 != _zz_311),{_zz_312,{_zz_313,_zz_314}}}; + assign _zz_300 = 32'h00007034; + assign _zz_301 = 32'h02007064; + assign _zz_302 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_303 = 32'h40001010; + assign _zz_304 = ((decode_INSTRUCTION & _zz_315) == 32'h00001010); + assign _zz_305 = ((decode_INSTRUCTION & _zz_316) == 32'h00001010); + assign _zz_306 = ((decode_INSTRUCTION & _zz_317) == 32'h00000024); + assign _zz_307 = (_zz_318 == _zz_319); + assign _zz_308 = (_zz_320 == _zz_321); + assign _zz_309 = ((decode_INSTRUCTION & _zz_322) == 32'h00001000); + assign _zz_310 = _zz_76; + assign _zz_311 = 1'b0; + assign _zz_312 = ({_zz_323,_zz_324} != 2'b00); + assign _zz_313 = (_zz_325 != _zz_326); + assign _zz_314 = {_zz_327,{_zz_328,_zz_329}}; + assign _zz_315 = 32'h00007034; + assign _zz_316 = 32'h02007054; + assign _zz_317 = 32'h00000064; + assign _zz_318 = (decode_INSTRUCTION & 32'h00003034); + assign _zz_319 = 32'h00001010; + assign _zz_320 = (decode_INSTRUCTION & 32'h02003054); + assign _zz_321 = 32'h00001010; + assign _zz_322 = 32'h00001000; + assign _zz_323 = ((decode_INSTRUCTION & _zz_330) == 32'h00002000); + assign _zz_324 = ((decode_INSTRUCTION & _zz_331) == 32'h00001000); + assign _zz_325 = {(_zz_332 == _zz_333),(_zz_334 == _zz_335)}; + assign _zz_326 = 2'b00; + assign _zz_327 = ({_zz_336,{_zz_337,_zz_338}} != 3'b000); + assign _zz_328 = (_zz_339 != 1'b0); + assign _zz_329 = {(_zz_340 != _zz_341),{_zz_342,{_zz_343,_zz_344}}}; + assign _zz_330 = 32'h00002010; + assign _zz_331 = 32'h00005000; + assign _zz_332 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_333 = 32'h00000020; + assign _zz_334 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_335 = 32'h00000020; + assign _zz_336 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_337 = ((decode_INSTRUCTION & _zz_345) == 32'h0); + assign _zz_338 = ((decode_INSTRUCTION & _zz_346) == 32'h00000040); + assign _zz_339 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_340 = ((decode_INSTRUCTION & _zz_347) == 32'h00000010); + assign _zz_341 = 1'b0; + assign _zz_342 = ({_zz_74,{_zz_348,_zz_349}} != 3'b000); + assign _zz_343 = ({_zz_350,_zz_351} != 6'h0); + assign _zz_344 = {(_zz_352 != _zz_353),{_zz_354,{_zz_355,_zz_356}}}; + assign _zz_345 = 32'h00000038; + assign _zz_346 = 32'h00403040; + assign _zz_347 = 32'h00000010; + assign _zz_348 = ((decode_INSTRUCTION & _zz_357) == 32'h00000010); + assign _zz_349 = ((decode_INSTRUCTION & _zz_358) == 32'h00000020); + assign _zz_350 = _zz_75; + assign _zz_351 = {(_zz_359 == _zz_360),{_zz_361,{_zz_362,_zz_363}}}; + assign _zz_352 = {_zz_74,(_zz_364 == _zz_365)}; + assign _zz_353 = 2'b00; + assign _zz_354 = ({_zz_74,_zz_366} != 2'b00); + assign _zz_355 = ({_zz_367,_zz_368} != 2'b00); + assign _zz_356 = {(_zz_369 != _zz_370),{_zz_371,{_zz_372,_zz_373}}}; + assign _zz_357 = 32'h00000030; + assign _zz_358 = 32'h02000060; + assign _zz_359 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_360 = 32'h00001010; + assign _zz_361 = ((decode_INSTRUCTION & _zz_374) == 32'h00002010); + assign _zz_362 = (_zz_375 == _zz_376); + assign _zz_363 = {_zz_377,_zz_378}; + assign _zz_364 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_365 = 32'h00000020; + assign _zz_366 = ((decode_INSTRUCTION & _zz_379) == 32'h0); + assign _zz_367 = (_zz_380 == _zz_381); + assign _zz_368 = (_zz_382 == _zz_383); + assign _zz_369 = (_zz_384 == _zz_385); + assign _zz_370 = 1'b0; + assign _zz_371 = ({_zz_386,_zz_387} != 4'b0000); + assign _zz_372 = (_zz_388 != _zz_389); + assign _zz_373 = {_zz_390,{_zz_391,_zz_392}}; + assign _zz_374 = 32'h00002010; + assign _zz_375 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_376 = 32'h00000010; + assign _zz_377 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_378 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_379 = 32'h00000020; + assign _zz_380 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_381 = 32'h00006010; + assign _zz_382 = (decode_INSTRUCTION & 32'h00005014); + assign _zz_383 = 32'h00004010; + assign _zz_384 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_385 = 32'h00002010; + assign _zz_386 = ((decode_INSTRUCTION & _zz_393) == 32'h0); + assign _zz_387 = {(_zz_394 == _zz_395),{_zz_396,_zz_397}}; + assign _zz_388 = ((decode_INSTRUCTION & _zz_398) == 32'h0); + assign _zz_389 = 1'b0; + assign _zz_390 = ({_zz_399,{_zz_400,_zz_401}} != 3'b000); + assign _zz_391 = ({_zz_402,_zz_403} != 2'b00); + assign _zz_392 = ({_zz_404,_zz_405} != 2'b00); + assign _zz_393 = 32'h00000044; + assign _zz_394 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_395 = 32'h0; + assign _zz_396 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_397 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_398 = 32'h00000058; + assign _zz_399 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_400 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_401 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz_402 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_403 = _zz_73; + assign _zz_404 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_405 = _zz_73; + always @ (posedge clk) begin + if(_zz_248) begin + _zz_136 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_249) begin + _zz_137 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_40) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid (iBus_rsp_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_payload_error ), //i + .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (_zz_134 ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o + .io_flush (_zz_135 ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_250) + 2'b00 : begin + _zz_138 = CsrPlugin_jumpInterface_payload; + end + 2'b01 : begin + _zz_138 = DBusSimplePlugin_redoBranch_payload; + end + default : begin + _zz_138 = BranchPlugin_jumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; + default : _zz_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_2) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; + default : _zz_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_3) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; + endcase + end + always @(*) begin + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; + endcase + end + always @(*) begin + case(_zz_10) + `BranchCtrlEnum_defaultEncoding_INC : _zz_10_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_10_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_10_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_10_string = "JALR"; + default : _zz_10_string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_14) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; + default : _zz_14_string = "?????"; + endcase + end + always @(*) begin + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; + endcase + end + always @(*) begin + case(_zz_16) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + default : _zz_16_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_17) + `Src2CtrlEnum_defaultEncoding_RS : _zz_17_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_17_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_17_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_17_string = "PC "; + default : _zz_17_string = "???"; + endcase + end + always @(*) begin + case(_zz_18) + `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; + default : _zz_18_string = "???"; + endcase + end + always @(*) begin + case(_zz_19) + `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; + default : _zz_19_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; + default : _zz_20_string = "????????"; + endcase + end + always @(*) begin + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; + endcase + end + always @(*) begin + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_23) + `Src1CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_23_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_23_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_23_string = "URS1 "; + default : _zz_23_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_30) + `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; + default : _zz_30_string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_32) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_32_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_32_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_32_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_32_string = "SRA_1 "; + default : _zz_32_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_34) + `Src2CtrlEnum_defaultEncoding_RS : _zz_34_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_34_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_34_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_34_string = "PC "; + default : _zz_34_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_35) + `Src1CtrlEnum_defaultEncoding_RS : _zz_35_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_35_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_35_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_35_string = "URS1 "; + default : _zz_35_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_36) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_36_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_36_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_36_string = "BITWISE "; + default : _zz_36_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_37) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_37_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_37_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_37_string = "AND_1"; + default : _zz_37_string = "?????"; + endcase + end + always @(*) begin + case(_zz_41) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_41_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_41_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_41_string = "ECALL"; + default : _zz_41_string = "?????"; + endcase + end + always @(*) begin + case(_zz_42) + `BranchCtrlEnum_defaultEncoding_INC : _zz_42_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_42_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_42_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_42_string = "JALR"; + default : _zz_42_string = "????"; + endcase + end + always @(*) begin + case(_zz_43) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_43_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_43_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_43_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_43_string = "SRA_1 "; + default : _zz_43_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_44) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_44_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_44_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_44_string = "AND_1"; + default : _zz_44_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `Src2CtrlEnum_defaultEncoding_RS : _zz_45_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_45_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_45_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_45_string = "PC "; + default : _zz_45_string = "???"; + endcase + end + always @(*) begin + case(_zz_46) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_46_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_46_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_46_string = "BITWISE "; + default : _zz_46_string = "????????"; + endcase + end + always @(*) begin + case(_zz_47) + `Src1CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_47_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_47_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_47_string = "URS1 "; + default : _zz_47_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_79) + `Src1CtrlEnum_defaultEncoding_RS : _zz_79_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_79_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_79_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_79_string = "URS1 "; + default : _zz_79_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_80) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_80_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_80_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_80_string = "BITWISE "; + default : _zz_80_string = "????????"; + endcase + end + always @(*) begin + case(_zz_81) + `Src2CtrlEnum_defaultEncoding_RS : _zz_81_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_81_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_81_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_81_string = "PC "; + default : _zz_81_string = "???"; + endcase + end + always @(*) begin + case(_zz_82) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_82_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_82_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_82_string = "AND_1"; + default : _zz_82_string = "?????"; + endcase + end + always @(*) begin + case(_zz_83) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_83_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_83_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_83_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_83_string = "SRA_1 "; + default : _zz_83_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_84) + `BranchCtrlEnum_defaultEncoding_INC : _zz_84_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_84_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_84_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_84_string = "JALR"; + default : _zz_84_string = "????"; + endcase + end + always @(*) begin + case(_zz_85) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_85_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_85_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_85_string = "ECALL"; + default : _zz_85_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + `endif + + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_101; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_87; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_RS2 = decode_RegFilePlugin_rs2Data; + assign decode_RS1 = decode_RegFilePlugin_rs1Data; + assign decode_IS_DIV = _zz_170[0]; + assign decode_IS_RS2_SIGNED = _zz_171[0]; + assign decode_IS_RS1_SIGNED = _zz_172[0]; + assign decode_IS_MUL = _zz_173[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_174[0]; + assign decode_BRANCH_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_SHIFT_CTRL = _zz_11; + assign _zz_12 = _zz_13; + assign decode_ALU_BITWISE_CTRL = _zz_14; + assign _zz_15 = _zz_16; + assign decode_SRC_LESS_UNSIGNED = _zz_175[0]; + assign decode_MEMORY_STORE = _zz_176[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_177[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_178[0]; + assign decode_SRC2_CTRL = _zz_17; + assign _zz_18 = _zz_19; + assign decode_ALU_CTRL = _zz_20; + assign _zz_21 = _zz_22; + assign decode_SRC1_CTRL = _zz_23; + assign _zz_24 = _zz_25; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + always @ (*) begin + _zz_26 = memory_REGFILE_WRITE_DATA; + if(_zz_139)begin + _zz_26 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + end + if(_zz_140)begin + _zz_26 = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_27; + assign execute_ENV_CTRL = _zz_28; + assign writeBack_ENV_CTRL = _zz_29; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_CTRL = _zz_30; + assign decode_RS2_USE = _zz_179[0]; + assign decode_RS1_USE = _zz_180[0]; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_31 = execute_REGFILE_WRITE_DATA; + if(_zz_141)begin + _zz_31 = _zz_94; + end + if(_zz_142)begin + _zz_31 = execute_CsrPlugin_readData; + end + end + + assign execute_SHIFT_CTRL = _zz_32; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_33 = execute_PC; + assign execute_SRC2_CTRL = _zz_34; + assign execute_SRC1_CTRL = _zz_35; + assign decode_SRC_USE_SUB_LESS = _zz_181[0]; + assign decode_SRC_ADD_ZERO = _zz_182[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_36; + assign execute_SRC2 = _zz_93; + assign execute_SRC1 = _zz_88; + assign execute_ALU_BITWISE_CTRL = _zz_37; + assign _zz_38 = writeBack_INSTRUCTION; + assign _zz_39 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_40 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_40 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_183[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_251) == 32'h00001073),{(_zz_252 == _zz_253),{_zz_254,{_zz_255,_zz_256}}}}}}} != 20'h0); + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + always @ (*) begin + _zz_48 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_48 = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; + assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; + assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; + assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; + assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; + assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; + assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; + assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; + assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; + assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; + assign memory_PC = execute_to_memory_PC; + assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); + assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; + assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; + assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; + assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; + assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; + assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; + assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; + assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); + assign decode_MEMORY_ENABLE = _zz_184[0]; + always @ (*) begin + _zz_49 = memory_FORMAL_PC_NEXT; + if(DBusSimplePlugin_redoBranch_valid)begin + _zz_49 = DBusSimplePlugin_redoBranch_payload; + end + if(BranchPlugin_jumpInterface_valid)begin + _zz_49 = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_95 || _zz_96)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_143)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(_zz_143)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_65)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_141)begin + if((! execute_LightShifterPlugin_done))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_142)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_139)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_144)begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_140)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(_zz_145)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushIt = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(_zz_145)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_146)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_147)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusSimplePlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_146)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_147)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_incomingInstruction = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + end + + assign CsrPlugin_inWfi = 1'b0; + assign CsrPlugin_thirdPartyWake = 1'b0; + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_146)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_147)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_146)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_147)begin + case(_zz_148) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); + assign _zz_50 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; + assign _zz_51 = (_zz_50 & (~ _zz_185)); + assign _zz_52 = _zz_51[1]; + assign _zz_53 = _zz_51[2]; + assign IBusSimplePlugin_jump_pcLoad_payload = _zz_138; + always @ (*) begin + IBusSimplePlugin_fetchPc_correction = 1'b0; + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); + always @ (*) begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_187); + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; + end + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + end + IBusSimplePlugin_fetchPc_pc[0] = 1'b0; + IBusSimplePlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_flushed = 1'b0; + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); + assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; + always @ (*) begin + IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin + IBusSimplePlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; + assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; + always @ (*) begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; + end + if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin + if(IBusSimplePlugin_mmuBus_rsp_refilling)begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; + end + if(IBusSimplePlugin_mmuBus_rsp_exception)begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + end + end + end + + assign _zz_54 = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_54); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_54); + assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; + assign _zz_55 = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_55); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_55); + assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_fetchPc_redo_valid = IBusSimplePlugin_iBusRsp_redoFetch; + assign IBusSimplePlugin_fetchPc_redo_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_56; + assign _zz_56 = ((1'b0 && (! _zz_57)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_57 = _zz_58; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_57; + assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + always @ (*) begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b1; + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + if((! IBusSimplePlugin_pcValids_0))begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_59; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_60; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_61; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_62; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_63; + assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; + assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; + assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; + assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; + assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; + assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; + assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; + assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; + assign IBusSimplePlugin_pending_next = (_zz_188 - _zz_192); + assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); + always @ (*) begin + IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); + if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin + if(IBusSimplePlugin_mmuBus_rsp_refilling)begin + IBusSimplePlugin_cmd_valid = 1'b0; + end + if(IBusSimplePlugin_mmuBus_rsp_exception)begin + IBusSimplePlugin_cmd_valid = 1'b0; + end + end + end + + assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_mmuBus_cmd_0_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; + assign IBusSimplePlugin_mmuBus_cmd_0_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_externalFlush); + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],2'b00}; + assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign _zz_134 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_134); + assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; + always @ (*) begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + end + end + + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + always @ (*) begin + IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; + if(_zz_149)begin + IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; + end + end + + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign _zz_64 = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_64); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_64); + assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; + always @ (*) begin + IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_149)begin + IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; + end + end + + assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],2'b00}; + assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError); + assign _zz_65 = 1'b0; + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_65)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_66 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_66 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_66 = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_66; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_67 = 4'b0001; + end + 2'b01 : begin + _zz_67 = 4'b0011; + end + default : begin + _zz_67 = 4'b1111; + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_67 <<< dBus_cmd_payload_address[1 : 0]); + assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; + assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; + assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + if(_zz_150)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_MMU_RSP2_refilling)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end else begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + end + if(_zz_151)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; + if(_zz_150)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_197}; + end + if(! memory_MMU_RSP2_refilling) begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); + end + end + end + + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; + always @ (*) begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + if(memory_MMU_RSP2_refilling)begin + DBusSimplePlugin_redoBranch_valid = 1'b1; + end + if(_zz_151)begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + end + end + + assign DBusSimplePlugin_redoBranch_payload = memory_PC; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_68 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_69[31] = _zz_68; + _zz_69[30] = _zz_68; + _zz_69[29] = _zz_68; + _zz_69[28] = _zz_68; + _zz_69[27] = _zz_68; + _zz_69[26] = _zz_68; + _zz_69[25] = _zz_68; + _zz_69[24] = _zz_68; + _zz_69[23] = _zz_68; + _zz_69[22] = _zz_68; + _zz_69[21] = _zz_68; + _zz_69[20] = _zz_68; + _zz_69[19] = _zz_68; + _zz_69[18] = _zz_68; + _zz_69[17] = _zz_68; + _zz_69[16] = _zz_68; + _zz_69[15] = _zz_68; + _zz_69[14] = _zz_68; + _zz_69[13] = _zz_68; + _zz_69[12] = _zz_68; + _zz_69[11] = _zz_68; + _zz_69[10] = _zz_68; + _zz_69[9] = _zz_68; + _zz_69[8] = _zz_68; + _zz_69[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_70 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_71[31] = _zz_70; + _zz_71[30] = _zz_70; + _zz_71[29] = _zz_70; + _zz_71[28] = _zz_70; + _zz_71[27] = _zz_70; + _zz_71[26] = _zz_70; + _zz_71[25] = _zz_70; + _zz_71[24] = _zz_70; + _zz_71[23] = _zz_70; + _zz_71[22] = _zz_70; + _zz_71[21] = _zz_70; + _zz_71[20] = _zz_70; + _zz_71[19] = _zz_70; + _zz_71[18] = _zz_70; + _zz_71[17] = _zz_70; + _zz_71[16] = _zz_70; + _zz_71[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_168) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_69; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_71; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; + assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusSimplePlugin_mmuBus_busy = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusSimplePlugin_mmuBus_busy = 1'b0; + assign _zz_73 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_74 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_75 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_76 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_77 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); + assign _zz_78 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); + assign _zz_72 = {(((decode_INSTRUCTION & _zz_269) == 32'h02004020) != 1'b0),{({_zz_78,_zz_77} != 2'b00),{({_zz_270,_zz_271} != 3'b000),{(_zz_272 != _zz_273),{_zz_274,{_zz_275,_zz_276}}}}}}; + assign _zz_79 = _zz_72[1 : 0]; + assign _zz_47 = _zz_79; + assign _zz_80 = _zz_72[6 : 5]; + assign _zz_46 = _zz_80; + assign _zz_81 = _zz_72[8 : 7]; + assign _zz_45 = _zz_81; + assign _zz_82 = _zz_72[17 : 16]; + assign _zz_44 = _zz_82; + assign _zz_83 = _zz_72[20 : 19]; + assign _zz_43 = _zz_83; + assign _zz_84 = _zz_72[22 : 21]; + assign _zz_42 = _zz_84; + assign _zz_85 = _zz_72[25 : 24]; + assign _zz_41 = _zz_85; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_136; + assign decode_RegFilePlugin_rs2Data = _zz_137; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_39 && writeBack_arbitration_isFiring); + if(_zz_86)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_38[11 : 7]; + if(_zz_86)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_48; + if(_zz_86)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_87 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_87 = {31'd0, _zz_198}; + end + default : begin + _zz_87 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_88 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_88 = {29'd0, _zz_199}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_88 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_88 = {27'd0, _zz_200}; + end + endcase + end + + assign _zz_89 = _zz_201[11]; + always @ (*) begin + _zz_90[19] = _zz_89; + _zz_90[18] = _zz_89; + _zz_90[17] = _zz_89; + _zz_90[16] = _zz_89; + _zz_90[15] = _zz_89; + _zz_90[14] = _zz_89; + _zz_90[13] = _zz_89; + _zz_90[12] = _zz_89; + _zz_90[11] = _zz_89; + _zz_90[10] = _zz_89; + _zz_90[9] = _zz_89; + _zz_90[8] = _zz_89; + _zz_90[7] = _zz_89; + _zz_90[6] = _zz_89; + _zz_90[5] = _zz_89; + _zz_90[4] = _zz_89; + _zz_90[3] = _zz_89; + _zz_90[2] = _zz_89; + _zz_90[1] = _zz_89; + _zz_90[0] = _zz_89; + end + + assign _zz_91 = _zz_202[11]; + always @ (*) begin + _zz_92[19] = _zz_91; + _zz_92[18] = _zz_91; + _zz_92[17] = _zz_91; + _zz_92[16] = _zz_91; + _zz_92[15] = _zz_91; + _zz_92[14] = _zz_91; + _zz_92[13] = _zz_91; + _zz_92[12] = _zz_91; + _zz_92[11] = _zz_91; + _zz_92[10] = _zz_91; + _zz_92[9] = _zz_91; + _zz_92[8] = _zz_91; + _zz_92[7] = _zz_91; + _zz_92[6] = _zz_91; + _zz_92[5] = _zz_91; + _zz_92[4] = _zz_91; + _zz_92[3] = _zz_91; + _zz_92[2] = _zz_91; + _zz_92[1] = _zz_91; + _zz_92[0] = _zz_91; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_93 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_93 = {_zz_90,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_93 = {_zz_92,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_93 = _zz_33; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_203; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_94 = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_94 = _zz_210; + end + endcase + end + + always @ (*) begin + _zz_95 = 1'b0; + if(_zz_97)begin + if((_zz_98 == decode_INSTRUCTION[19 : 15]))begin + _zz_95 = 1'b1; + end + end + if(_zz_152)begin + if(_zz_153)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_95 = 1'b1; + end + end + end + if(_zz_154)begin + if(_zz_155)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_95 = 1'b1; + end + end + end + if(_zz_156)begin + if(_zz_157)begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_95 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_95 = 1'b0; + end + end + + always @ (*) begin + _zz_96 = 1'b0; + if(_zz_97)begin + if((_zz_98 == decode_INSTRUCTION[24 : 20]))begin + _zz_96 = 1'b1; + end + end + if(_zz_152)begin + if(_zz_153)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_96 = 1'b1; + end + end + end + if(_zz_154)begin + if(_zz_155)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_96 = 1'b1; + end + end + end + if(_zz_156)begin + if(_zz_157)begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_96 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_96 = 1'b0; + end + end + + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_99 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_99 == 3'b000)) begin + _zz_100 = execute_BranchPlugin_eq; + end else if((_zz_99 == 3'b001)) begin + _zz_100 = (! execute_BranchPlugin_eq); + end else if((((_zz_99 & 3'b101) == 3'b101))) begin + _zz_100 = (! execute_SRC_LESS); + end else begin + _zz_100 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_101 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_101 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_101 = 1'b1; + end + default : begin + _zz_101 = _zz_100; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_102 = _zz_212[19]; + always @ (*) begin + _zz_103[10] = _zz_102; + _zz_103[9] = _zz_102; + _zz_103[8] = _zz_102; + _zz_103[7] = _zz_102; + _zz_103[6] = _zz_102; + _zz_103[5] = _zz_102; + _zz_103[4] = _zz_102; + _zz_103[3] = _zz_102; + _zz_103[2] = _zz_102; + _zz_103[1] = _zz_102; + _zz_103[0] = _zz_102; + end + + assign _zz_104 = _zz_213[11]; + always @ (*) begin + _zz_105[19] = _zz_104; + _zz_105[18] = _zz_104; + _zz_105[17] = _zz_104; + _zz_105[16] = _zz_104; + _zz_105[15] = _zz_104; + _zz_105[14] = _zz_104; + _zz_105[13] = _zz_104; + _zz_105[12] = _zz_104; + _zz_105[11] = _zz_104; + _zz_105[10] = _zz_104; + _zz_105[9] = _zz_104; + _zz_105[8] = _zz_104; + _zz_105[7] = _zz_104; + _zz_105[6] = _zz_104; + _zz_105[5] = _zz_104; + _zz_105[4] = _zz_104; + _zz_105[3] = _zz_104; + _zz_105[2] = _zz_104; + _zz_105[1] = _zz_104; + _zz_105[0] = _zz_104; + end + + assign _zz_106 = _zz_214[11]; + always @ (*) begin + _zz_107[18] = _zz_106; + _zz_107[17] = _zz_106; + _zz_107[16] = _zz_106; + _zz_107[15] = _zz_106; + _zz_107[14] = _zz_106; + _zz_107[13] = _zz_106; + _zz_107[12] = _zz_106; + _zz_107[11] = _zz_106; + _zz_107[10] = _zz_106; + _zz_107[9] = _zz_106; + _zz_107[8] = _zz_106; + _zz_107[7] = _zz_106; + _zz_107[6] = _zz_106; + _zz_107[5] = _zz_106; + _zz_107[4] = _zz_106; + _zz_107[3] = _zz_106; + _zz_107[2] = _zz_106; + _zz_107[1] = _zz_106; + _zz_107[0] = _zz_106; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_108 = {{_zz_103,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_108 = {_zz_105,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_108 = {{_zz_107,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_108; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign _zz_109 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_110 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_111 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_112 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; + assign _zz_113 = _zz_215[0]; + assign _zz_114 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_115 = _zz_217[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_143)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(_zz_145)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_158)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_159)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_159)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_158)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_158)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_169) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + always @ (*) begin + memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; + if(_zz_139)begin + if(_zz_144)begin + memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); + assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); + always @ (*) begin + if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_220); + end + if(memory_MulDivIterativePlugin_mul_counter_willClear)begin + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(_zz_140)begin + if(_zz_160)begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(_zz_161)begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_228); + end + if(memory_MulDivIterativePlugin_div_counter_willClear)begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_116 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_116[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_229); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_230 : _zz_231); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_232[31:0]; + assign _zz_117 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_118 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_119 = ((execute_IS_MUL && _zz_118) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_120[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_120[31 : 0] = execute_RS1; + end + + assign _zz_122 = (_zz_121 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_122 != 32'h0); + assign _zz_25 = decode_SRC1_CTRL; + assign _zz_23 = _zz_47; + assign _zz_35 = decode_to_execute_SRC1_CTRL; + assign _zz_22 = decode_ALU_CTRL; + assign _zz_20 = _zz_46; + assign _zz_36 = decode_to_execute_ALU_CTRL; + assign _zz_19 = decode_SRC2_CTRL; + assign _zz_17 = _zz_45; + assign _zz_34 = decode_to_execute_SRC2_CTRL; + assign _zz_16 = decode_ALU_BITWISE_CTRL; + assign _zz_14 = _zz_44; + assign _zz_37 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_13 = decode_SHIFT_CTRL; + assign _zz_11 = _zz_43; + assign _zz_32 = decode_to_execute_SHIFT_CTRL; + assign _zz_10 = decode_BRANCH_CTRL; + assign _zz_8 = _zz_42; + assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_41; + assign _zz_28 = decode_to_execute_ENV_CTRL; + assign _zz_27 = execute_to_memory_ENV_CTRL; + assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_123 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_123[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_123[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_123[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_124 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_124[11 : 11] = CsrPlugin_mip_MEIP; + _zz_124[7 : 7] = CsrPlugin_mip_MTIP; + _zz_124[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_125 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_125[11 : 11] = CsrPlugin_mie_MEIE; + _zz_125[7 : 7] = CsrPlugin_mie_MTIE; + _zz_125[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_126 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_126[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_127 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_127[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_127[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_128 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_128[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_129 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_129[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_130 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_130[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_131 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_131[31 : 0] = _zz_121; + end + end + + always @ (*) begin + _zz_132 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_132[31 : 0] = _zz_122; + end + end + + assign execute_CsrPlugin_readData = ((((_zz_123 | _zz_124) | (_zz_125 | _zz_126)) | ((_zz_127 | _zz_128) | (_zz_129 | _zz_130))) | (_zz_131 | _zz_132)); + assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); + assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; + assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; + assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); + assign iBusWishbone_CTI = 3'b000; + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'h0; + assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; + assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; + assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK); + assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = 3'b000; + assign dBusWishbone_BTE = 2'b00; + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_133 = 4'b0001; + end + 2'b01 : begin + _zz_133 = 4'b0011; + end + default : begin + _zz_133 = 4'b1111; + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = (_zz_133 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = 4'b1111; + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + assign _zz_135 = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + IBusSimplePlugin_fetchPc_booted <= 1'b0; + IBusSimplePlugin_fetchPc_inc <= 1'b0; + _zz_58 <= 1'b0; + _zz_59 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusSimplePlugin_pending_value <= 3'b000; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; + _zz_86 <= 1'b1; + execute_LightShifterPlugin_isActive <= 1'b0; + _zz_97 <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + _zz_121 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + iBus_cmd_m2sPipe_rValid <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusSimplePlugin_fetchPc_correction)begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + end + IBusSimplePlugin_fetchPc_booted <= 1'b1; + if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + end + if(IBusSimplePlugin_iBusRsp_flush)begin + _zz_58 <= 1'b0; + end + if(_zz_56)begin + _zz_58 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(decode_arbitration_removeIt)begin + _zz_59 <= 1'b0; + end + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_59 <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_194); + if(IBusSimplePlugin_iBusRsp_flush)begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_196); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + _zz_86 <= 1'b0; + if(_zz_141)begin + if(_zz_162)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + _zz_97 <= (_zz_39 && writeBack_arbitration_isFiring); + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_163)begin + if(_zz_164)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_165)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_166)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_146)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_147)begin + case(_zz_148) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_111,{_zz_110,_zz_109}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_242[0]; + CsrPlugin_mstatus_MIE <= _zz_243[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_245[0]; + CsrPlugin_mie_MTIE <= _zz_246[0]; + CsrPlugin_mie_MSIE <= _zz_247[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_121 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(iBus_cmd_ready)begin + iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; + end + if(_zz_167)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_60 <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_61 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_62 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_63 <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; + end + if(IBusSimplePlugin_injector_decodeInput_ready)begin + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + end + if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin + IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; + IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; + IBusSimplePlugin_mmu_joinCtx_isPaging <= IBusSimplePlugin_mmuBus_rsp_isPaging; + IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; + IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; + IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; + IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; + IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; + IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; + end + if(_zz_141)begin + if(_zz_162)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); + end + end + _zz_98 <= _zz_38[11 : 7]; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_143)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_113 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_113 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(_zz_145)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_115 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_115 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + end + if(_zz_163)begin + if(_zz_164)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_165)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_166)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_146)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(_zz_139)begin + if(_zz_144)begin + memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_221,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + end + end + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(_zz_140)begin + if(_zz_160)begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_result <= _zz_233[31:0]; + end + end + end + if(_zz_161)begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_119 ? (~ _zz_120) : _zz_120) + _zz_239); + memory_MulDivIterativePlugin_rs2 <= ((_zz_118 ? (~ execute_RS2) : execute_RS2) + _zz_241); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_119 ^ (_zz_118 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_33; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_49; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_24; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_21; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_18; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_15; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_12; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_9; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; + execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; + execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; + execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; + execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; + execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; + execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; + execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; + execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + end + if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_26; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_244[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(iBus_cmd_ready)begin + iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; + end + if(_zz_167)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + +endmodule + +module StreamFifoLowLatency ( + input io_push_valid, + output io_push_ready, + input io_push_payload_error, + input [31:0] io_push_payload_inst, + output reg io_pop_valid, + input io_pop_ready, + output reg io_pop_payload_error, + output reg [31:0] io_pop_payload_inst, + input io_flush, + output [0:0] io_occupancy, + input clk, + input reset +); + wire _zz_4; + wire [0:0] _zz_5; + reg _zz_1; + reg pushPtr_willIncrement; + reg pushPtr_willClear; + wire pushPtr_willOverflowIfInc; + wire pushPtr_willOverflow; + reg popPtr_willIncrement; + reg popPtr_willClear; + wire popPtr_willOverflowIfInc; + wire popPtr_willOverflow; + wire ptrMatch; + reg risingOccupancy; + wire empty; + wire full; + wire pushing; + wire popping; + wire [32:0] _zz_2; + reg [32:0] _zz_3; + + assign _zz_4 = (! empty); + assign _zz_5 = _zz_2[0 : 0]; + always @ (*) begin + _zz_1 = 1'b0; + if(pushing)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + pushPtr_willIncrement = 1'b0; + if(pushing)begin + pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + pushPtr_willClear = 1'b0; + if(io_flush)begin + pushPtr_willClear = 1'b1; + end + end + + assign pushPtr_willOverflowIfInc = 1'b1; + assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); + always @ (*) begin + popPtr_willIncrement = 1'b0; + if(popping)begin + popPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + popPtr_willClear = 1'b0; + if(io_flush)begin + popPtr_willClear = 1'b1; + end + end + + assign popPtr_willOverflowIfInc = 1'b1; + assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); + assign ptrMatch = 1'b1; + assign empty = (ptrMatch && (! risingOccupancy)); + assign full = (ptrMatch && risingOccupancy); + assign pushing = (io_push_valid && io_push_ready); + assign popping = (io_pop_valid && io_pop_ready); + assign io_push_ready = (! full); + always @ (*) begin + if(_zz_4)begin + io_pop_valid = 1'b1; + end else begin + io_pop_valid = io_push_valid; + end + end + + assign _zz_2 = _zz_3; + always @ (*) begin + if(_zz_4)begin + io_pop_payload_error = _zz_5[0]; + end else begin + io_pop_payload_error = io_push_payload_error; + end + end + + always @ (*) begin + if(_zz_4)begin + io_pop_payload_inst = _zz_2[32 : 1]; + end else begin + io_pop_payload_inst = io_push_payload_inst; + end + end + + assign io_occupancy = (risingOccupancy && ptrMatch); + always @ (posedge clk) begin + if(reset) begin + risingOccupancy <= 1'b0; + end else begin + if((pushing != popping))begin + risingOccupancy <= pushing; + end + if(io_flush)begin + risingOccupancy <= 1'b0; + end + end + end + + always @ (posedge clk) begin + if(_zz_1)begin + _zz_3 <= {io_push_payload_inst,io_push_payload_error}; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml new file mode 100644 index 0000000..0967ef4 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml @@ -0,0 +1 @@ +{} diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v new file mode 100644 index 0000000..97bd61e --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v @@ -0,0 +1,4935 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : aa12b0d45ab170fd03927c0d06fa62f6bd8e840f + + +`define Input2Kind_defaultEncoding_type [0:0] +`define Input2Kind_defaultEncoding_RS 1'b0 +`define Input2Kind_defaultEncoding_IMM_I 1'b1 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input CfuPlugin_bus_rsp_payload_response_ok, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output iBusWishbone_CYC, + output iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_151; + wire _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_156; + wire _zz_157; + wire _zz_158; + wire _zz_159; + wire _zz_160; + wire _zz_161; + wire _zz_162; + wire _zz_163; + wire _zz_164; + wire _zz_165; + wire _zz_166; + wire _zz_167; + wire _zz_168; + wire [1:0] _zz_169; + wire _zz_170; + wire _zz_171; + wire _zz_172; + wire _zz_173; + wire _zz_174; + wire _zz_175; + wire _zz_176; + wire _zz_177; + wire _zz_178; + wire _zz_179; + wire _zz_180; + wire _zz_181; + wire _zz_182; + wire [5:0] _zz_183; + wire _zz_184; + wire _zz_185; + wire _zz_186; + wire _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + wire [1:0] _zz_191; + wire _zz_192; + wire [0:0] _zz_193; + wire [0:0] _zz_194; + wire [0:0] _zz_195; + wire [0:0] _zz_196; + wire [0:0] _zz_197; + wire [0:0] _zz_198; + wire [0:0] _zz_199; + wire [0:0] _zz_200; + wire [0:0] _zz_201; + wire [0:0] _zz_202; + wire [0:0] _zz_203; + wire [0:0] _zz_204; + wire [0:0] _zz_205; + wire [0:0] _zz_206; + wire [0:0] _zz_207; + wire [0:0] _zz_208; + wire [0:0] _zz_209; + wire [2:0] _zz_210; + wire [2:0] _zz_211; + wire [31:0] _zz_212; + wire [2:0] _zz_213; + wire [0:0] _zz_214; + wire [2:0] _zz_215; + wire [0:0] _zz_216; + wire [2:0] _zz_217; + wire [0:0] _zz_218; + wire [2:0] _zz_219; + wire [0:0] _zz_220; + wire [2:0] _zz_221; + wire [2:0] _zz_222; + wire [0:0] _zz_223; + wire [2:0] _zz_224; + wire [4:0] _zz_225; + wire [11:0] _zz_226; + wire [11:0] _zz_227; + wire [31:0] _zz_228; + wire [31:0] _zz_229; + wire [31:0] _zz_230; + wire [31:0] _zz_231; + wire [31:0] _zz_232; + wire [31:0] _zz_233; + wire [31:0] _zz_234; + wire [31:0] _zz_235; + wire [32:0] _zz_236; + wire [19:0] _zz_237; + wire [11:0] _zz_238; + wire [11:0] _zz_239; + wire [1:0] _zz_240; + wire [1:0] _zz_241; + wire [1:0] _zz_242; + wire [1:0] _zz_243; + wire [1:0] _zz_244; + wire [1:0] _zz_245; + wire [9:0] _zz_246; + wire [7:0] _zz_247; + wire [0:0] _zz_248; + wire [5:0] _zz_249; + wire [33:0] _zz_250; + wire [32:0] _zz_251; + wire [33:0] _zz_252; + wire [32:0] _zz_253; + wire [33:0] _zz_254; + wire [32:0] _zz_255; + wire [0:0] _zz_256; + wire [5:0] _zz_257; + wire [32:0] _zz_258; + wire [31:0] _zz_259; + wire [31:0] _zz_260; + wire [32:0] _zz_261; + wire [32:0] _zz_262; + wire [32:0] _zz_263; + wire [32:0] _zz_264; + wire [0:0] _zz_265; + wire [32:0] _zz_266; + wire [0:0] _zz_267; + wire [32:0] _zz_268; + wire [0:0] _zz_269; + wire [31:0] _zz_270; + wire [0:0] _zz_271; + wire [0:0] _zz_272; + wire [0:0] _zz_273; + wire [0:0] _zz_274; + wire [0:0] _zz_275; + wire [0:0] _zz_276; + wire _zz_277; + wire _zz_278; + wire [1:0] _zz_279; + wire [31:0] _zz_280; + wire [31:0] _zz_281; + wire [31:0] _zz_282; + wire _zz_283; + wire [0:0] _zz_284; + wire [13:0] _zz_285; + wire [31:0] _zz_286; + wire [31:0] _zz_287; + wire [31:0] _zz_288; + wire _zz_289; + wire [0:0] _zz_290; + wire [7:0] _zz_291; + wire [31:0] _zz_292; + wire [31:0] _zz_293; + wire [31:0] _zz_294; + wire _zz_295; + wire [0:0] _zz_296; + wire [1:0] _zz_297; + wire [31:0] _zz_298; + wire [31:0] _zz_299; + wire [31:0] _zz_300; + wire [0:0] _zz_301; + wire [0:0] _zz_302; + wire [2:0] _zz_303; + wire [2:0] _zz_304; + wire _zz_305; + wire [0:0] _zz_306; + wire [26:0] _zz_307; + wire [31:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire _zz_311; + wire [0:0] _zz_312; + wire [22:0] _zz_313; + wire [31:0] _zz_314; + wire _zz_315; + wire _zz_316; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire _zz_321; + wire [0:0] _zz_322; + wire [18:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire _zz_326; + wire _zz_327; + wire [0:0] _zz_328; + wire [1:0] _zz_329; + wire [2:0] _zz_330; + wire [2:0] _zz_331; + wire _zz_332; + wire [0:0] _zz_333; + wire [15:0] _zz_334; + wire [31:0] _zz_335; + wire [31:0] _zz_336; + wire [31:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [31:0] _zz_340; + wire [31:0] _zz_341; + wire _zz_342; + wire _zz_343; + wire [31:0] _zz_344; + wire [31:0] _zz_345; + wire [1:0] _zz_346; + wire [1:0] _zz_347; + wire _zz_348; + wire [0:0] _zz_349; + wire [12:0] _zz_350; + wire [31:0] _zz_351; + wire [31:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; + wire [0:0] _zz_355; + wire [0:0] _zz_356; + wire [0:0] _zz_357; + wire [1:0] _zz_358; + wire [0:0] _zz_359; + wire [0:0] _zz_360; + wire _zz_361; + wire [0:0] _zz_362; + wire [9:0] _zz_363; + wire [31:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire [31:0] _zz_367; + wire [31:0] _zz_368; + wire [31:0] _zz_369; + wire [31:0] _zz_370; + wire [31:0] _zz_371; + wire _zz_372; + wire _zz_373; + wire [0:0] _zz_374; + wire [1:0] _zz_375; + wire [5:0] _zz_376; + wire [5:0] _zz_377; + wire _zz_378; + wire [0:0] _zz_379; + wire [6:0] _zz_380; + wire [31:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire [31:0] _zz_384; + wire _zz_385; + wire [0:0] _zz_386; + wire [2:0] _zz_387; + wire _zz_388; + wire [0:0] _zz_389; + wire [0:0] _zz_390; + wire [1:0] _zz_391; + wire [1:0] _zz_392; + wire _zz_393; + wire [0:0] _zz_394; + wire [3:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire _zz_399; + wire [0:0] _zz_400; + wire [0:0] _zz_401; + wire [31:0] _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire _zz_405; + wire _zz_406; + wire _zz_407; + wire [3:0] _zz_408; + wire [3:0] _zz_409; + wire _zz_410; + wire [0:0] _zz_411; + wire [1:0] _zz_412; + wire [31:0] _zz_413; + wire [31:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire [31:0] _zz_418; + wire [31:0] _zz_419; + wire [31:0] _zz_420; + wire _zz_421; + wire [0:0] _zz_422; + wire [1:0] _zz_423; + wire _zz_424; + wire [2:0] _zz_425; + wire [2:0] _zz_426; + wire _zz_427; + wire _zz_428; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire [31:0] _zz_431; + wire [31:0] _zz_432; + wire [31:0] _zz_433; + wire [31:0] _zz_434; + wire [31:0] _zz_435; + wire _zz_436; + wire _zz_437; + wire _zz_438; + wire _zz_439; + wire [31:0] memory_MEMORY_READ_DATA; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC2_FORCE_ZERO; + wire [31:0] decode_RS2; + wire [31:0] decode_RS1; + wire decode_IS_DIV; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_MUL; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_1; + wire `Input2Kind_defaultEncoding_type _zz_2; + wire `Input2Kind_defaultEncoding_type _zz_3; + wire decode_CfuPlugin_CFU_ENABLE; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12; + wire `BranchCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_MUL; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire memory_IS_MUL; + reg _zz_29; + reg _zz_30; + reg [31:0] _zz_31; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_32; + wire execute_CfuPlugin_CFU_ENABLE; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire decode_RS2_USE; + wire decode_RS1_USE; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] _zz_37; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_38; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_39; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_40; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_41; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_42; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_44; + wire _zz_45; + reg _zz_46; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `Input2Kind_defaultEncoding_type _zz_47; + wire `EnvCtrlEnum_defaultEncoding_type _zz_48; + wire `BranchCtrlEnum_defaultEncoding_type _zz_49; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_50; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_51; + wire `Src2CtrlEnum_defaultEncoding_type _zz_52; + wire `AluCtrlEnum_defaultEncoding_type _zz_53; + wire `Src1CtrlEnum_defaultEncoding_type _zz_54; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_55; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP2_physicalAddress; + wire memory_MMU_RSP2_isIoAccess; + wire memory_MMU_RSP2_isPaging; + wire memory_MMU_RSP2_allowRead; + wire memory_MMU_RSP2_allowWrite; + wire memory_MMU_RSP2_allowExecute; + wire memory_MMU_RSP2_exception; + wire memory_MMU_RSP2_refilling; + wire memory_MMU_RSP2_bypassTranslation; + wire [31:0] memory_PC; + wire memory_ALIGNEMENT_FAULT; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; + wire execute_MMU_FAULT; + wire [31:0] execute_MMU_RSP2_physicalAddress; + wire execute_MMU_RSP2_isIoAccess; + wire execute_MMU_RSP2_isPaging; + wire execute_MMU_RSP2_allowRead; + wire execute_MMU_RSP2_allowWrite; + wire execute_MMU_RSP2_allowExecute; + wire execute_MMU_RSP2_exception; + wire execute_MMU_RSP2_refilling; + wire execute_MMU_RSP2_bypassTranslation; + wire [31:0] execute_SRC_ADD; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire decode_MEMORY_ENABLE; + reg [31:0] _zz_56; + reg [31:0] _zz_57; + wire [31:0] decode_PC; + wire [31:0] decode_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusSimplePlugin_fetcherHalt; + reg IBusSimplePlugin_incomingInstruction; + wire IBusSimplePlugin_pcValids_0; + wire IBusSimplePlugin_pcValids_1; + wire IBusSimplePlugin_pcValids_2; + wire IBusSimplePlugin_pcValids_3; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + wire [31:0] iBus_cmd_payload_pc; + wire iBus_rsp_valid; + wire iBus_rsp_payload_error; + wire [31:0] iBus_rsp_payload_inst; + wire IBusSimplePlugin_decodeExceptionPort_valid; + reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; + wire IBusSimplePlugin_mmuBus_cmd_0_isValid; + wire IBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire IBusSimplePlugin_mmuBus_rsp_isPaging; + wire IBusSimplePlugin_mmuBus_rsp_allowRead; + wire IBusSimplePlugin_mmuBus_rsp_allowWrite; + wire IBusSimplePlugin_mmuBus_rsp_allowExecute; + wire IBusSimplePlugin_mmuBus_rsp_exception; + wire IBusSimplePlugin_mmuBus_rsp_refilling; + wire IBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire IBusSimplePlugin_mmuBus_end; + wire IBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire DBusSimplePlugin_mmuBus_cmd_0_isValid; + wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; + wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; + wire DBusSimplePlugin_mmuBus_rsp_isPaging; + wire DBusSimplePlugin_mmuBus_rsp_allowRead; + wire DBusSimplePlugin_mmuBus_rsp_allowWrite; + wire DBusSimplePlugin_mmuBus_rsp_allowExecute; + wire DBusSimplePlugin_mmuBus_rsp_exception; + wire DBusSimplePlugin_mmuBus_rsp_refilling; + wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + wire DBusSimplePlugin_mmuBus_end; + wire DBusSimplePlugin_mmuBus_busy; + reg DBusSimplePlugin_redoBranch_valid; + wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CfuPlugin_joinException_valid; + wire [3:0] CfuPlugin_joinException_payload_code; + wire [31:0] CfuPlugin_joinException_payload_badAddr; + reg IBusSimplePlugin_injectionPort_valid; + reg IBusSimplePlugin_injectionPort_ready; + wire [31:0] IBusSimplePlugin_injectionPort_payload; + wire IBusSimplePlugin_externalFlush; + wire IBusSimplePlugin_jump_pcLoad_valid; + wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; + wire [2:0] _zz_58; + wire [2:0] _zz_59; + wire _zz_60; + wire _zz_61; + wire IBusSimplePlugin_fetchPc_output_valid; + wire IBusSimplePlugin_fetchPc_output_ready; + wire [31:0] IBusSimplePlugin_fetchPc_output_payload; + reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusSimplePlugin_fetchPc_correction; + reg IBusSimplePlugin_fetchPc_correctionReg; + wire IBusSimplePlugin_fetchPc_corrected; + reg IBusSimplePlugin_fetchPc_pcRegPropagate; + reg IBusSimplePlugin_fetchPc_booted; + reg IBusSimplePlugin_fetchPc_inc; + reg [31:0] IBusSimplePlugin_fetchPc_pc; + wire IBusSimplePlugin_fetchPc_redo_valid; + wire [31:0] IBusSimplePlugin_fetchPc_redo_payload; + reg IBusSimplePlugin_fetchPc_flushed; + reg IBusSimplePlugin_iBusRsp_redoFetch; + wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; + reg IBusSimplePlugin_iBusRsp_stages_0_halt; + wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; + wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; + wire IBusSimplePlugin_iBusRsp_stages_1_halt; + wire _zz_62; + wire _zz_63; + wire IBusSimplePlugin_iBusRsp_flush; + wire _zz_64; + wire _zz_65; + reg _zz_66; + reg IBusSimplePlugin_iBusRsp_readyForError; + wire IBusSimplePlugin_iBusRsp_output_valid; + wire IBusSimplePlugin_iBusRsp_output_ready; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; + wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; + wire IBusSimplePlugin_injector_decodeInput_valid; + wire IBusSimplePlugin_injector_decodeInput_ready; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; + wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; + reg _zz_67; + reg [31:0] _zz_68; + reg _zz_69; + reg [31:0] _zz_70; + reg _zz_71; + reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; + reg IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_ready; + wire [31:0] IBusSimplePlugin_cmd_payload_pc; + wire IBusSimplePlugin_pending_inc; + wire IBusSimplePlugin_pending_dec; + reg [2:0] IBusSimplePlugin_pending_value; + wire [2:0] IBusSimplePlugin_pending_next; + wire IBusSimplePlugin_cmdFork_canEmit; + reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; + reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; + reg IBusSimplePlugin_mmu_joinCtx_isPaging; + reg IBusSimplePlugin_mmu_joinCtx_allowRead; + reg IBusSimplePlugin_mmu_joinCtx_allowWrite; + reg IBusSimplePlugin_mmu_joinCtx_allowExecute; + reg IBusSimplePlugin_mmu_joinCtx_exception; + reg IBusSimplePlugin_mmu_joinCtx_refilling; + reg IBusSimplePlugin_mmu_joinCtx_bypassTranslation; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; + wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; + reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire IBusSimplePlugin_rspJoin_join_valid; + wire IBusSimplePlugin_rspJoin_join_ready; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; + wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; + wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + wire IBusSimplePlugin_rspJoin_join_payload_isRvc; + reg IBusSimplePlugin_rspJoin_exceptionDetected; + wire _zz_72; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + wire _zz_73; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_74; + reg [3:0] _zz_75; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_76; + reg [31:0] _zz_77; + wire _zz_78; + reg [31:0] _zz_79; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [32:0] _zz_80; + wire _zz_81; + wire _zz_82; + wire _zz_83; + wire _zz_84; + wire _zz_85; + wire _zz_86; + wire _zz_87; + wire `Src1CtrlEnum_defaultEncoding_type _zz_88; + wire `AluCtrlEnum_defaultEncoding_type _zz_89; + wire `Src2CtrlEnum_defaultEncoding_type _zz_90; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_91; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_92; + wire `BranchCtrlEnum_defaultEncoding_type _zz_93; + wire `EnvCtrlEnum_defaultEncoding_type _zz_94; + wire `Input2Kind_defaultEncoding_type _zz_95; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_96; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_97; + reg [31:0] _zz_98; + wire _zz_99; + reg [19:0] _zz_100; + wire _zz_101; + reg [19:0] _zz_102; + reg [31:0] _zz_103; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_104; + reg _zz_105; + reg _zz_106; + reg _zz_107; + reg [4:0] _zz_108; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_109; + reg _zz_110; + reg _zz_111; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_112; + reg [10:0] _zz_113; + wire _zz_114; + reg [19:0] _zz_115; + wire _zz_116; + reg [18:0] _zz_117; + reg [31:0] _zz_118; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_119; + wire _zz_120; + wire _zz_121; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_122; + wire _zz_123; + wire [1:0] _zz_124; + wire _zz_125; + wire [1:0] _zz_126; + wire _zz_127; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_128; + reg [23:0] _zz_129; + reg [31:0] _zz_130; + wire memory_CfuPlugin_rsp_valid; + reg memory_CfuPlugin_rsp_ready; + wire memory_CfuPlugin_rsp_payload_response_ok; + wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_s2mPipe_rValid; + reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_mul_counter_willIncrement; + reg memory_MulDivIterativePlugin_mul_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; + wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_needRevert; + reg memory_MulDivIterativePlugin_div_counter_willIncrement; + reg memory_MulDivIterativePlugin_div_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_div_counter_value; + wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_div_counter_willOverflow; + reg memory_MulDivIterativePlugin_div_done; + reg [31:0] memory_MulDivIterativePlugin_div_result; + wire [31:0] _zz_131; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; + wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [31:0] _zz_132; + wire _zz_133; + wire _zz_134; + reg [32:0] _zz_135; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_136; + wire [31:0] _zz_137; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_138; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg execute_to_memory_ALIGNEMENT_FAULT; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; + reg execute_to_memory_MMU_RSP2_isIoAccess; + reg execute_to_memory_MMU_RSP2_isPaging; + reg execute_to_memory_MMU_RSP2_allowRead; + reg execute_to_memory_MMU_RSP2_allowWrite; + reg execute_to_memory_MMU_RSP2_allowExecute; + reg execute_to_memory_MMU_RSP2_exception; + reg execute_to_memory_MMU_RSP2_refilling; + reg execute_to_memory_MMU_RSP2_bypassTranslation; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg [2:0] _zz_139; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_140; + reg [31:0] _zz_141; + reg [31:0] _zz_142; + reg [31:0] _zz_143; + reg [31:0] _zz_144; + reg [31:0] _zz_145; + reg [31:0] _zz_146; + reg [31:0] _zz_147; + reg [31:0] _zz_148; + reg [31:0] _zz_149; + wire iBus_cmd_m2sPipe_valid; + wire iBus_cmd_m2sPipe_ready; + wire [31:0] iBus_cmd_m2sPipe_payload_pc; + reg iBus_cmd_m2sPipe_rValid; + reg [31:0] iBus_cmd_m2sPipe_rData_pc; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_150; + `ifndef SYNTHESIS + reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [39:0] _zz_10_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_11_string; + reg [31:0] _zz_12_string; + reg [31:0] _zz_13_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_14_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_17_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_20_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_23_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_26_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_32_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_33_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_34_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_35_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_36_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_38_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_40_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_41_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_42_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_43_string; + reg [39:0] _zz_47_string; + reg [39:0] _zz_48_string; + reg [31:0] _zz_49_string; + reg [71:0] _zz_50_string; + reg [39:0] _zz_51_string; + reg [23:0] _zz_52_string; + reg [63:0] _zz_53_string; + reg [95:0] _zz_54_string; + reg [95:0] _zz_88_string; + reg [63:0] _zz_89_string; + reg [23:0] _zz_90_string; + reg [39:0] _zz_91_string; + reg [71:0] _zz_92_string; + reg [31:0] _zz_93_string; + reg [39:0] _zz_94_string; + reg [39:0] _zz_95_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_156 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_157 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_158 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_159 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_160 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_161 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_162 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_163 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_164 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_165 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_166 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_167 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_168 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); + assign _zz_169 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_170 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); + assign _zz_171 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign _zz_172 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_173 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_174 = (1'b1 || (! 1'b1)); + assign _zz_175 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_176 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_177 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_178 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_179 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_180 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_181 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_182 = (! memory_arbitration_isStuck); + assign _zz_183 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_184 = (! execute_arbitration_isStuckByOthers); + assign _zz_185 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_186 = ((_zz_119 && 1'b1) && (! 1'b0)); + assign _zz_187 = ((_zz_120 && 1'b1) && (! 1'b0)); + assign _zz_188 = ((_zz_121 && 1'b1) && (! 1'b0)); + assign _zz_189 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_190 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_191 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_192 = execute_INSTRUCTION[13]; + assign _zz_193 = _zz_80[31 : 31]; + assign _zz_194 = _zz_80[30 : 30]; + assign _zz_195 = _zz_80[29 : 29]; + assign _zz_196 = _zz_80[28 : 28]; + assign _zz_197 = _zz_80[26 : 26]; + assign _zz_198 = _zz_80[23 : 23]; + assign _zz_199 = _zz_80[15 : 15]; + assign _zz_200 = _zz_80[12 : 12]; + assign _zz_201 = _zz_80[11 : 11]; + assign _zz_202 = _zz_80[10 : 10]; + assign _zz_203 = _zz_80[32 : 32]; + assign _zz_204 = _zz_80[14 : 14]; + assign _zz_205 = _zz_80[4 : 4]; + assign _zz_206 = _zz_80[2 : 2]; + assign _zz_207 = _zz_80[18 : 18]; + assign _zz_208 = _zz_80[9 : 9]; + assign _zz_209 = _zz_80[3 : 3]; + assign _zz_210 = (_zz_58 - 3'b001); + assign _zz_211 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_212 = {29'd0, _zz_211}; + assign _zz_213 = (IBusSimplePlugin_pending_value + _zz_215); + assign _zz_214 = IBusSimplePlugin_pending_inc; + assign _zz_215 = {2'd0, _zz_214}; + assign _zz_216 = IBusSimplePlugin_pending_dec; + assign _zz_217 = {2'd0, _zz_216}; + assign _zz_218 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_219 = {2'd0, _zz_218}; + assign _zz_220 = IBusSimplePlugin_pending_dec; + assign _zz_221 = {2'd0, _zz_220}; + assign _zz_222 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz_223 = execute_SRC_LESS; + assign _zz_224 = 3'b100; + assign _zz_225 = execute_INSTRUCTION[19 : 15]; + assign _zz_226 = execute_INSTRUCTION[31 : 20]; + assign _zz_227 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_228 = ($signed(_zz_229) + $signed(_zz_232)); + assign _zz_229 = ($signed(_zz_230) + $signed(_zz_231)); + assign _zz_230 = execute_SRC1; + assign _zz_231 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_232 = (execute_SRC_USE_SUB_LESS ? _zz_233 : _zz_234); + assign _zz_233 = 32'h00000001; + assign _zz_234 = 32'h0; + assign _zz_235 = (_zz_236 >>> 1); + assign _zz_236 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_237 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_238 = execute_INSTRUCTION[31 : 20]; + assign _zz_239 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_240 = (_zz_122 & (~ _zz_241)); + assign _zz_241 = (_zz_122 - 2'b01); + assign _zz_242 = (_zz_124 & (~ _zz_243)); + assign _zz_243 = (_zz_124 - 2'b01); + assign _zz_244 = (_zz_126 & (~ _zz_245)); + assign _zz_245 = (_zz_126 - 2'b01); + assign _zz_246 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_247 = execute_INSTRUCTION[31 : 24]; + assign _zz_248 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_249 = {5'd0, _zz_248}; + assign _zz_250 = (_zz_252 + _zz_254); + assign _zz_251 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_252 = {{1{_zz_251[32]}}, _zz_251}; + assign _zz_253 = _zz_255; + assign _zz_254 = {{1{_zz_253[32]}}, _zz_253}; + assign _zz_255 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_256 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_257 = {5'd0, _zz_256}; + assign _zz_258 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_259 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_260 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_261 = {_zz_131,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_262 = _zz_263; + assign _zz_263 = _zz_264; + assign _zz_264 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_132) : _zz_132)} + _zz_266); + assign _zz_265 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_266 = {32'd0, _zz_265}; + assign _zz_267 = _zz_134; + assign _zz_268 = {32'd0, _zz_267}; + assign _zz_269 = _zz_133; + assign _zz_270 = {31'd0, _zz_269}; + assign _zz_271 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_272 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_273 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_274 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_275 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_276 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_277 = 1'b1; + assign _zz_278 = 1'b1; + assign _zz_279 = {_zz_61,_zz_60}; + assign _zz_280 = 32'h0000106f; + assign _zz_281 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_282 = 32'h00001073; + assign _zz_283 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_284 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_285 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_286) == 32'h00000003),{(_zz_287 == _zz_288),{_zz_289,{_zz_290,_zz_291}}}}}}; + assign _zz_286 = 32'h0000207f; + assign _zz_287 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_288 = 32'h00000003; + assign _zz_289 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_290 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_291 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & _zz_292) == 32'h00005013),{(_zz_293 == _zz_294),{_zz_295,{_zz_296,_zz_297}}}}}}; + assign _zz_292 = 32'hbc00707f; + assign _zz_293 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_294 = 32'h00005033; + assign _zz_295 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_296 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_297 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz_298 = 32'h10103050; + assign _zz_299 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_300 = 32'h02004020; + assign _zz_301 = _zz_87; + assign _zz_302 = _zz_86; + assign _zz_303 = {_zz_87,{_zz_85,_zz_86}}; + assign _zz_304 = 3'b000; + assign _zz_305 = (((decode_INSTRUCTION & _zz_308) == 32'h02000030) != 1'b0); + assign _zz_306 = 1'b0; + assign _zz_307 = {(_zz_84 != 1'b0),{(_zz_309 != _zz_310),{_zz_311,{_zz_312,_zz_313}}}}; + assign _zz_308 = 32'h02004074; + assign _zz_309 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz_310 = 1'b0; + assign _zz_311 = (((decode_INSTRUCTION & _zz_314) == 32'h10000050) != 1'b0); + assign _zz_312 = ({_zz_315,_zz_316} != 2'b00); + assign _zz_313 = {({_zz_317,_zz_318} != 2'b00),{(_zz_319 != _zz_320),{_zz_321,{_zz_322,_zz_323}}}}; + assign _zz_314 = 32'h10403050; + assign _zz_315 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_316 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_317 = _zz_83; + assign _zz_318 = ((decode_INSTRUCTION & _zz_324) == 32'h00000004); + assign _zz_319 = ((decode_INSTRUCTION & _zz_325) == 32'h00000040); + assign _zz_320 = 1'b0; + assign _zz_321 = ({_zz_326,_zz_327} != 2'b00); + assign _zz_322 = ({_zz_328,_zz_329} != 3'b000); + assign _zz_323 = {(_zz_330 != _zz_331),{_zz_332,{_zz_333,_zz_334}}}; + assign _zz_324 = 32'h0000001c; + assign _zz_325 = 32'h00000058; + assign _zz_326 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_327 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_328 = ((decode_INSTRUCTION & _zz_335) == 32'h40001010); + assign _zz_329 = {(_zz_336 == _zz_337),(_zz_338 == _zz_339)}; + assign _zz_330 = {(_zz_340 == _zz_341),{_zz_342,_zz_343}}; + assign _zz_331 = 3'b000; + assign _zz_332 = ((_zz_344 == _zz_345) != 1'b0); + assign _zz_333 = (_zz_85 != 1'b0); + assign _zz_334 = {(_zz_346 != _zz_347),{_zz_348,{_zz_349,_zz_350}}}; + assign _zz_335 = 32'h40003054; + assign _zz_336 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_337 = 32'h00001010; + assign _zz_338 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_339 = 32'h00001010; + assign _zz_340 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_341 = 32'h00000024; + assign _zz_342 = ((decode_INSTRUCTION & 32'h00003034) == 32'h00001010); + assign _zz_343 = ((decode_INSTRUCTION & 32'h02003054) == 32'h00001010); + assign _zz_344 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_345 = 32'h00001000; + assign _zz_346 = {(_zz_351 == _zz_352),(_zz_353 == _zz_354)}; + assign _zz_347 = 2'b00; + assign _zz_348 = ({_zz_84,{_zz_355,_zz_356}} != 3'b000); + assign _zz_349 = ({_zz_357,_zz_358} != 3'b000); + assign _zz_350 = {(_zz_359 != _zz_360),{_zz_361,{_zz_362,_zz_363}}}; + assign _zz_351 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_352 = 32'h00002000; + assign _zz_353 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_354 = 32'h00001000; + assign _zz_355 = ((decode_INSTRUCTION & _zz_364) == 32'h00000020); + assign _zz_356 = ((decode_INSTRUCTION & _zz_365) == 32'h00000020); + assign _zz_357 = ((decode_INSTRUCTION & _zz_366) == 32'h00000040); + assign _zz_358 = {(_zz_367 == _zz_368),(_zz_369 == _zz_370)}; + assign _zz_359 = ((decode_INSTRUCTION & _zz_371) == 32'h00000020); + assign _zz_360 = 1'b0; + assign _zz_361 = ({_zz_372,_zz_373} != 2'b00); + assign _zz_362 = ({_zz_374,_zz_375} != 3'b000); + assign _zz_363 = {(_zz_376 != _zz_377),{_zz_378,{_zz_379,_zz_380}}}; + assign _zz_364 = 32'h00000034; + assign _zz_365 = 32'h00000064; + assign _zz_366 = 32'h00000050; + assign _zz_367 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_368 = 32'h0; + assign _zz_369 = (decode_INSTRUCTION & 32'h00103040); + assign _zz_370 = 32'h00000040; + assign _zz_371 = 32'h00000020; + assign _zz_372 = ((decode_INSTRUCTION & 32'h00000008) == 32'h00000008); + assign _zz_373 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); + assign _zz_374 = _zz_82; + assign _zz_375 = {(_zz_381 == _zz_382),(_zz_383 == _zz_384)}; + assign _zz_376 = {_zz_83,{_zz_385,{_zz_386,_zz_387}}}; + assign _zz_377 = 6'h0; + assign _zz_378 = ({_zz_82,_zz_388} != 2'b00); + assign _zz_379 = ({_zz_389,_zz_390} != 2'b00); + assign _zz_380 = {(_zz_391 != _zz_392),{_zz_393,{_zz_394,_zz_395}}}; + assign _zz_381 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_382 = 32'h00000010; + assign _zz_383 = (decode_INSTRUCTION & 32'h02000060); + assign _zz_384 = 32'h00000020; + assign _zz_385 = ((decode_INSTRUCTION & _zz_396) == 32'h00001010); + assign _zz_386 = (_zz_397 == _zz_398); + assign _zz_387 = {_zz_399,{_zz_400,_zz_401}}; + assign _zz_388 = ((decode_INSTRUCTION & _zz_402) == 32'h00000020); + assign _zz_389 = _zz_82; + assign _zz_390 = (_zz_403 == _zz_404); + assign _zz_391 = {_zz_405,_zz_406}; + assign _zz_392 = 2'b00; + assign _zz_393 = (_zz_407 != 1'b0); + assign _zz_394 = (_zz_408 != _zz_409); + assign _zz_395 = {_zz_410,{_zz_411,_zz_412}}; + assign _zz_396 = 32'h00001010; + assign _zz_397 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_398 = 32'h00002010; + assign _zz_399 = ((decode_INSTRUCTION & _zz_413) == 32'h00000010); + assign _zz_400 = (_zz_414 == _zz_415); + assign _zz_401 = (_zz_416 == _zz_417); + assign _zz_402 = 32'h00000070; + assign _zz_403 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_404 = 32'h0; + assign _zz_405 = ((decode_INSTRUCTION & _zz_418) == 32'h00006010); + assign _zz_406 = ((decode_INSTRUCTION & _zz_419) == 32'h00004010); + assign _zz_407 = ((decode_INSTRUCTION & _zz_420) == 32'h00002010); + assign _zz_408 = {_zz_421,{_zz_422,_zz_423}}; + assign _zz_409 = 4'b0000; + assign _zz_410 = (_zz_424 != 1'b0); + assign _zz_411 = (_zz_425 != _zz_426); + assign _zz_412 = {_zz_427,_zz_428}; + assign _zz_413 = 32'h00000050; + assign _zz_414 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_415 = 32'h00000004; + assign _zz_416 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_417 = 32'h0; + assign _zz_418 = 32'h00006014; + assign _zz_419 = 32'h00005014; + assign _zz_420 = 32'h00006014; + assign _zz_421 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_422 = ((decode_INSTRUCTION & _zz_429) == 32'h0); + assign _zz_423 = {(_zz_430 == _zz_431),(_zz_432 == _zz_433)}; + assign _zz_424 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_425 = {(_zz_434 == _zz_435),{_zz_436,_zz_437}}; + assign _zz_426 = 3'b000; + assign _zz_427 = ({_zz_438,_zz_81} != 2'b00); + assign _zz_428 = ({_zz_439,_zz_81} != 2'b00); + assign _zz_429 = 32'h00000018; + assign _zz_430 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_431 = 32'h00002000; + assign _zz_432 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_433 = 32'h00001000; + assign _zz_434 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_435 = 32'h00000040; + assign _zz_436 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_437 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz_438 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_439 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + always @ (posedge clk) begin + if(_zz_277) begin + _zz_153 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_278) begin + _zz_154 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_46) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( + .io_push_valid (iBus_rsp_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_payload_error ), //i + .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (_zz_151 ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o + .io_flush (_zz_152 ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_279) + 2'b00 : begin + _zz_155 = CsrPlugin_jumpInterface_payload; + end + 2'b01 : begin + _zz_155 = DBusSimplePlugin_redoBranch_payload; + end + default : begin + _zz_155 = BranchPlugin_jumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_1) + `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; + default : _zz_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_2) + `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; + default : _zz_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_3) + `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; + default : _zz_10_string = "?????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_11) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; + default : _zz_12_string = "????"; + endcase + end + always @(*) begin + case(_zz_13) + `BranchCtrlEnum_defaultEncoding_INC : _zz_13_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_13_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_13_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_13_string = "JALR"; + default : _zz_13_string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; + default : _zz_32_string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_36) + `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; + default : _zz_36_string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_38) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38_string = "SRA_1 "; + default : _zz_38_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_40) + `Src2CtrlEnum_defaultEncoding_RS : _zz_40_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_40_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_40_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_40_string = "PC "; + default : _zz_40_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_41) + `Src1CtrlEnum_defaultEncoding_RS : _zz_41_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_41_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_41_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_41_string = "URS1 "; + default : _zz_41_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_42) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_42_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_42_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_42_string = "BITWISE "; + default : _zz_42_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_43) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; + default : _zz_43_string = "?????"; + endcase + end + always @(*) begin + case(_zz_47) + `Input2Kind_defaultEncoding_RS : _zz_47_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_47_string = "IMM_I"; + default : _zz_47_string = "?????"; + endcase + end + always @(*) begin + case(_zz_48) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_48_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_48_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_48_string = "ECALL"; + default : _zz_48_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `BranchCtrlEnum_defaultEncoding_INC : _zz_49_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_49_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_49_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_49_string = "JALR"; + default : _zz_49_string = "????"; + endcase + end + always @(*) begin + case(_zz_50) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_50_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_50_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_50_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_50_string = "SRA_1 "; + default : _zz_50_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_51) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_51_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_51_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_51_string = "AND_1"; + default : _zz_51_string = "?????"; + endcase + end + always @(*) begin + case(_zz_52) + `Src2CtrlEnum_defaultEncoding_RS : _zz_52_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_52_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_52_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_52_string = "PC "; + default : _zz_52_string = "???"; + endcase + end + always @(*) begin + case(_zz_53) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_53_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_53_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_53_string = "BITWISE "; + default : _zz_53_string = "????????"; + endcase + end + always @(*) begin + case(_zz_54) + `Src1CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_54_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54_string = "URS1 "; + default : _zz_54_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_88) + `Src1CtrlEnum_defaultEncoding_RS : _zz_88_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_88_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_88_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_88_string = "URS1 "; + default : _zz_88_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_89) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_89_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_89_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_89_string = "BITWISE "; + default : _zz_89_string = "????????"; + endcase + end + always @(*) begin + case(_zz_90) + `Src2CtrlEnum_defaultEncoding_RS : _zz_90_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_90_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_90_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_90_string = "PC "; + default : _zz_90_string = "???"; + endcase + end + always @(*) begin + case(_zz_91) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_91_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_91_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_91_string = "AND_1"; + default : _zz_91_string = "?????"; + endcase + end + always @(*) begin + case(_zz_92) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_92_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_92_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_92_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_92_string = "SRA_1 "; + default : _zz_92_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_93) + `BranchCtrlEnum_defaultEncoding_INC : _zz_93_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_93_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_93_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_93_string = "JALR"; + default : _zz_93_string = "????"; + endcase + end + always @(*) begin + case(_zz_94) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_94_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_94_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_94_string = "ECALL"; + default : _zz_94_string = "?????"; + endcase + end + always @(*) begin + case(_zz_95) + `Input2Kind_defaultEncoding_RS : _zz_95_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_95_string = "IMM_I"; + default : _zz_95_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + `endif + + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_97; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_RS2 = decode_RegFilePlugin_rs2Data; + assign decode_RS1 = decode_RegFilePlugin_rs1Data; + assign decode_IS_DIV = _zz_193[0]; + assign decode_IS_RS2_SIGNED = _zz_194[0]; + assign decode_IS_RS1_SIGNED = _zz_195[0]; + assign decode_IS_MUL = _zz_196[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; + assign _zz_2 = _zz_3; + assign decode_CfuPlugin_CFU_ENABLE = _zz_197[0]; + assign _zz_4 = _zz_5; + assign _zz_6 = _zz_7; + assign decode_ENV_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_IS_CSR = _zz_198[0]; + assign decode_BRANCH_CTRL = _zz_11; + assign _zz_12 = _zz_13; + assign decode_SHIFT_CTRL = _zz_14; + assign _zz_15 = _zz_16; + assign decode_ALU_BITWISE_CTRL = _zz_17; + assign _zz_18 = _zz_19; + assign decode_SRC_LESS_UNSIGNED = _zz_199[0]; + assign decode_MEMORY_STORE = _zz_200[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_201[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_202[0]; + assign decode_SRC2_CTRL = _zz_20; + assign _zz_21 = _zz_22; + assign decode_ALU_CTRL = _zz_23; + assign _zz_24 = _zz_25; + assign decode_SRC1_CTRL = _zz_26; + assign _zz_27 = _zz_28; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_203[0]; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + always @ (*) begin + _zz_29 = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck)begin + _zz_29 = 1'b0; + end + end + + always @ (*) begin + _zz_30 = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck)begin + _zz_30 = 1'b0; + end + end + + always @ (*) begin + _zz_31 = memory_REGFILE_WRITE_DATA; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_31 = memory_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_156)begin + _zz_31 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + end + if(_zz_157)begin + _zz_31 = memory_MulDivIterativePlugin_div_result; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_33; + assign execute_ENV_CTRL = _zz_34; + assign writeBack_ENV_CTRL = _zz_35; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_111; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_CTRL = _zz_36; + assign decode_RS2_USE = _zz_204[0]; + assign decode_RS1_USE = _zz_205[0]; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_37 = execute_REGFILE_WRITE_DATA; + if(_zz_158)begin + _zz_37 = _zz_104; + end + if(_zz_159)begin + _zz_37 = execute_CsrPlugin_readData; + end + end + + assign execute_SHIFT_CTRL = _zz_38; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_39 = execute_PC; + assign execute_SRC2_CTRL = _zz_40; + assign execute_SRC1_CTRL = _zz_41; + assign decode_SRC_USE_SUB_LESS = _zz_206[0]; + assign decode_SRC_ADD_ZERO = _zz_207[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_42; + assign execute_SRC2 = _zz_103; + assign execute_SRC1 = _zz_98; + assign execute_ALU_BITWISE_CTRL = _zz_43; + assign _zz_44 = writeBack_INSTRUCTION; + assign _zz_45 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_46 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_46 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_208[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_280) == 32'h00000003),{(_zz_281 == _zz_282),{_zz_283,{_zz_284,_zz_285}}}}}}} != 21'h0); + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + always @ (*) begin + _zz_55 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_55 = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; + assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; + assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; + assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; + assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; + assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; + assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; + assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; + assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; + assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; + assign memory_PC = execute_to_memory_PC; + assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); + assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; + assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; + assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; + assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; + assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; + assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; + assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; + assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); + assign decode_MEMORY_ENABLE = _zz_209[0]; + always @ (*) begin + _zz_56 = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_56 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_57 = memory_FORMAL_PC_NEXT; + if(DBusSimplePlugin_redoBranch_valid)begin + _zz_57 = DBusSimplePlugin_redoBranch_payload; + end + end + + assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; + assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + case(_zz_139) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_105 || _zz_106)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_160)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(_zz_160)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_73)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_158)begin + if((! execute_LightShifterPlugin_done))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_159)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if(_zz_161)begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(_zz_162)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushIt = 1'b0; + if(_zz_161)begin + if(_zz_163)begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_162)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_161)begin + if(_zz_163)begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if((! memory_CfuPlugin_rsp_valid))begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_156)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_164)begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_157)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(_zz_165)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushIt = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushNext = 1'b1; + end + if(_zz_165)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_166)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_167)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusSimplePlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_166)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_167)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_161)begin + if(_zz_163)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + if(_zz_168)begin + IBusSimplePlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_incomingInstruction = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_incomingInstruction = 1'b1; + end + end + + assign CsrPlugin_inWfi = 1'b0; + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_166)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_167)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_166)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_167)begin + case(_zz_169) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode)begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + end + end + + assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); + assign _zz_58 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; + assign _zz_59 = (_zz_58 & (~ _zz_210)); + assign _zz_60 = _zz_59[1]; + assign _zz_61 = _zz_59[2]; + assign IBusSimplePlugin_jump_pcLoad_payload = _zz_155; + always @ (*) begin + IBusSimplePlugin_fetchPc_correction = 1'b0; + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); + always @ (*) begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin + IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_212); + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; + end + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + end + IBusSimplePlugin_fetchPc_pc[0] = 1'b0; + IBusSimplePlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusSimplePlugin_fetchPc_flushed = 1'b0; + if(IBusSimplePlugin_fetchPc_redo_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + if(IBusSimplePlugin_jump_pcLoad_valid)begin + IBusSimplePlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); + assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; + always @ (*) begin + IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin + IBusSimplePlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; + assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; + assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; + always @ (*) begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; + end + if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin + if(IBusSimplePlugin_mmuBus_rsp_refilling)begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; + end + if(IBusSimplePlugin_mmuBus_rsp_exception)begin + IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; + end + end + end + + assign _zz_62 = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_62); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_62); + assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; + assign _zz_63 = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_63); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_63); + assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_fetchPc_redo_valid = IBusSimplePlugin_iBusRsp_redoFetch; + assign IBusSimplePlugin_fetchPc_redo_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; + assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_64; + assign _zz_64 = ((1'b0 && (! _zz_65)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_65 = _zz_66; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_65; + assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + always @ (*) begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b1; + if(IBusSimplePlugin_injector_decodeInput_valid)begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + if((! IBusSimplePlugin_pcValids_0))begin + IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_67; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_68; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_69; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_70; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_71; + assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; + assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; + assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; + assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; + assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); + always @ (*) begin + decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; + case(_zz_139) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + end + + assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; + assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; + assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; + assign IBusSimplePlugin_pending_next = (_zz_213 - _zz_217); + assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); + always @ (*) begin + IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); + if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin + if(IBusSimplePlugin_mmuBus_rsp_refilling)begin + IBusSimplePlugin_cmd_valid = 1'b0; + end + if(IBusSimplePlugin_mmuBus_rsp_exception)begin + IBusSimplePlugin_cmd_valid = 1'b0; + end + end + end + + assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_mmuBus_cmd_0_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; + assign IBusSimplePlugin_mmuBus_cmd_0_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; + assign IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_externalFlush); + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],2'b00}; + assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; + assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; + assign _zz_151 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_151); + assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; + always @ (*) begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; + if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin + IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + end + end + + assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + always @ (*) begin + IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; + if(_zz_170)begin + IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; + end + end + + assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; + assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; + assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign _zz_72 = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_72); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_72); + assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; + assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; + assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; + always @ (*) begin + IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_170)begin + IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; + end + end + + assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],2'b00}; + assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError); + assign _zz_73 = 1'b0; + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_73)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_74 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_74 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_74 = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_74; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_75 = 4'b0001; + end + 2'b01 : begin + _zz_75 = 4'b0011; + end + default : begin + _zz_75 = 4'b1111; + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_75 <<< dBus_cmd_payload_address[1 : 0]); + assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; + assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; + assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + if(_zz_171)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if(memory_MMU_RSP2_refilling)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end else begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + end + if(_zz_172)begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; + if(_zz_171)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; + end + if(memory_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_222}; + end + if(! memory_MMU_RSP2_refilling) begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); + end + end + end + + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; + always @ (*) begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + if(memory_MMU_RSP2_refilling)begin + DBusSimplePlugin_redoBranch_valid = 1'b1; + end + if(_zz_172)begin + DBusSimplePlugin_redoBranch_valid = 1'b0; + end + end + + assign DBusSimplePlugin_redoBranch_payload = memory_PC; + always @ (*) begin + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_76 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_77[31] = _zz_76; + _zz_77[30] = _zz_76; + _zz_77[29] = _zz_76; + _zz_77[28] = _zz_76; + _zz_77[27] = _zz_76; + _zz_77[26] = _zz_76; + _zz_77[25] = _zz_76; + _zz_77[24] = _zz_76; + _zz_77[23] = _zz_76; + _zz_77[22] = _zz_76; + _zz_77[21] = _zz_76; + _zz_77[20] = _zz_76; + _zz_77[19] = _zz_76; + _zz_77[18] = _zz_76; + _zz_77[17] = _zz_76; + _zz_77[16] = _zz_76; + _zz_77[15] = _zz_76; + _zz_77[14] = _zz_76; + _zz_77[13] = _zz_76; + _zz_77[12] = _zz_76; + _zz_77[11] = _zz_76; + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_78 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_79[31] = _zz_78; + _zz_79[30] = _zz_78; + _zz_79[29] = _zz_78; + _zz_79[28] = _zz_78; + _zz_79[27] = _zz_78; + _zz_79[26] = _zz_78; + _zz_79[25] = _zz_78; + _zz_79[24] = _zz_78; + _zz_79[23] = _zz_78; + _zz_79[22] = _zz_78; + _zz_79[21] = _zz_78; + _zz_79[20] = _zz_78; + _zz_79[19] = _zz_78; + _zz_79[18] = _zz_78; + _zz_79[17] = _zz_78; + _zz_79[16] = _zz_78; + _zz_79[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_191) + 2'b00 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_77; + end + 2'b01 : begin + writeBack_DBusSimplePlugin_rspFormated = _zz_79; + end + default : begin + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; + assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusSimplePlugin_mmuBus_busy = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; + assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; + assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusSimplePlugin_mmuBus_busy = 1'b0; + assign _zz_81 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_82 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_83 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_84 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_85 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_86 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); + assign _zz_87 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); + assign _zz_80 = {(((decode_INSTRUCTION & _zz_298) == 32'h00100050) != 1'b0),{((_zz_299 == _zz_300) != 1'b0),{({_zz_301,_zz_302} != 2'b00),{(_zz_303 != _zz_304),{_zz_305,{_zz_306,_zz_307}}}}}}; + assign _zz_88 = _zz_80[1 : 0]; + assign _zz_54 = _zz_88; + assign _zz_89 = _zz_80[6 : 5]; + assign _zz_53 = _zz_89; + assign _zz_90 = _zz_80[8 : 7]; + assign _zz_52 = _zz_90; + assign _zz_91 = _zz_80[17 : 16]; + assign _zz_51 = _zz_91; + assign _zz_92 = _zz_80[20 : 19]; + assign _zz_50 = _zz_92; + assign _zz_93 = _zz_80[22 : 21]; + assign _zz_49 = _zz_93; + assign _zz_94 = _zz_80[25 : 24]; + assign _zz_48 = _zz_94; + assign _zz_95 = _zz_80[27 : 27]; + assign _zz_47 = _zz_95; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_153; + assign decode_RegFilePlugin_rs2Data = _zz_154; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); + if(_zz_96)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; + if(_zz_96)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_55; + if(_zz_96)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_97 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_97 = {31'd0, _zz_223}; + end + default : begin + _zz_97 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_98 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_98 = {29'd0, _zz_224}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_98 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_98 = {27'd0, _zz_225}; + end + endcase + end + + assign _zz_99 = _zz_226[11]; + always @ (*) begin + _zz_100[19] = _zz_99; + _zz_100[18] = _zz_99; + _zz_100[17] = _zz_99; + _zz_100[16] = _zz_99; + _zz_100[15] = _zz_99; + _zz_100[14] = _zz_99; + _zz_100[13] = _zz_99; + _zz_100[12] = _zz_99; + _zz_100[11] = _zz_99; + _zz_100[10] = _zz_99; + _zz_100[9] = _zz_99; + _zz_100[8] = _zz_99; + _zz_100[7] = _zz_99; + _zz_100[6] = _zz_99; + _zz_100[5] = _zz_99; + _zz_100[4] = _zz_99; + _zz_100[3] = _zz_99; + _zz_100[2] = _zz_99; + _zz_100[1] = _zz_99; + _zz_100[0] = _zz_99; + end + + assign _zz_101 = _zz_227[11]; + always @ (*) begin + _zz_102[19] = _zz_101; + _zz_102[18] = _zz_101; + _zz_102[17] = _zz_101; + _zz_102[16] = _zz_101; + _zz_102[15] = _zz_101; + _zz_102[14] = _zz_101; + _zz_102[13] = _zz_101; + _zz_102[12] = _zz_101; + _zz_102[11] = _zz_101; + _zz_102[10] = _zz_101; + _zz_102[9] = _zz_101; + _zz_102[8] = _zz_101; + _zz_102[7] = _zz_101; + _zz_102[6] = _zz_101; + _zz_102[5] = _zz_101; + _zz_102[4] = _zz_101; + _zz_102[3] = _zz_101; + _zz_102[2] = _zz_101; + _zz_102[1] = _zz_101; + _zz_102[0] = _zz_101; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_103 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_103 = {_zz_100,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_103 = {_zz_102,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_103 = _zz_39; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_228; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_104 = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_104 = _zz_235; + end + endcase + end + + always @ (*) begin + _zz_105 = 1'b0; + if(_zz_107)begin + if((_zz_108 == decode_INSTRUCTION[19 : 15]))begin + _zz_105 = 1'b1; + end + end + if(_zz_173)begin + if(_zz_174)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_105 = 1'b1; + end + end + end + if(_zz_175)begin + if(_zz_176)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_105 = 1'b1; + end + end + end + if(_zz_177)begin + if(_zz_178)begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_105 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_105 = 1'b0; + end + end + + always @ (*) begin + _zz_106 = 1'b0; + if(_zz_107)begin + if((_zz_108 == decode_INSTRUCTION[24 : 20]))begin + _zz_106 = 1'b1; + end + end + if(_zz_173)begin + if(_zz_174)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_106 = 1'b1; + end + end + end + if(_zz_175)begin + if(_zz_176)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_106 = 1'b1; + end + end + end + if(_zz_177)begin + if(_zz_178)begin + if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_106 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_106 = 1'b0; + end + end + + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_109 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_109 == 3'b000)) begin + _zz_110 = execute_BranchPlugin_eq; + end else if((_zz_109 == 3'b001)) begin + _zz_110 = (! execute_BranchPlugin_eq); + end else if((((_zz_109 & 3'b101) == 3'b101))) begin + _zz_110 = (! execute_SRC_LESS); + end else begin + _zz_110 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_111 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_111 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_111 = 1'b1; + end + default : begin + _zz_111 = _zz_110; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_112 = _zz_237[19]; + always @ (*) begin + _zz_113[10] = _zz_112; + _zz_113[9] = _zz_112; + _zz_113[8] = _zz_112; + _zz_113[7] = _zz_112; + _zz_113[6] = _zz_112; + _zz_113[5] = _zz_112; + _zz_113[4] = _zz_112; + _zz_113[3] = _zz_112; + _zz_113[2] = _zz_112; + _zz_113[1] = _zz_112; + _zz_113[0] = _zz_112; + end + + assign _zz_114 = _zz_238[11]; + always @ (*) begin + _zz_115[19] = _zz_114; + _zz_115[18] = _zz_114; + _zz_115[17] = _zz_114; + _zz_115[16] = _zz_114; + _zz_115[15] = _zz_114; + _zz_115[14] = _zz_114; + _zz_115[13] = _zz_114; + _zz_115[12] = _zz_114; + _zz_115[11] = _zz_114; + _zz_115[10] = _zz_114; + _zz_115[9] = _zz_114; + _zz_115[8] = _zz_114; + _zz_115[7] = _zz_114; + _zz_115[6] = _zz_114; + _zz_115[5] = _zz_114; + _zz_115[4] = _zz_114; + _zz_115[3] = _zz_114; + _zz_115[2] = _zz_114; + _zz_115[1] = _zz_114; + _zz_115[0] = _zz_114; + end + + assign _zz_116 = _zz_239[11]; + always @ (*) begin + _zz_117[18] = _zz_116; + _zz_117[17] = _zz_116; + _zz_117[16] = _zz_116; + _zz_117[15] = _zz_116; + _zz_117[14] = _zz_116; + _zz_117[13] = _zz_116; + _zz_117[12] = _zz_116; + _zz_117[11] = _zz_116; + _zz_117[10] = _zz_116; + _zz_117[9] = _zz_116; + _zz_117[8] = _zz_116; + _zz_117[7] = _zz_116; + _zz_117[6] = _zz_116; + _zz_117[5] = _zz_116; + _zz_117[4] = _zz_116; + _zz_117[3] = _zz_116; + _zz_117[2] = _zz_116; + _zz_117[1] = _zz_116; + _zz_117[0] = _zz_116; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_118 = {{_zz_113,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_118 = {_zz_115,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_118 = {{_zz_117,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_118; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign CsrPlugin_misa_base = 2'b01; + assign CsrPlugin_misa_extensions = 26'h0000042; + assign _zz_119 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_120 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_121 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_122 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; + assign _zz_123 = _zz_240[0]; + assign _zz_124 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_125 = _zz_242[0]; + assign _zz_126 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_127 = _zz_244[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_160)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_162)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(_zz_165)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_179)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_180)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_180)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_179)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_179)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_192) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign execute_CfuPlugin_functionsIds_0 = _zz_246; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_128 = _zz_247[7]; + always @ (*) begin + _zz_129[23] = _zz_128; + _zz_129[22] = _zz_128; + _zz_129[21] = _zz_128; + _zz_129[20] = _zz_128; + _zz_129[19] = _zz_128; + _zz_129[18] = _zz_128; + _zz_129[17] = _zz_128; + _zz_129[16] = _zz_128; + _zz_129[15] = _zz_128; + _zz_129[14] = _zz_128; + _zz_129[13] = _zz_128; + _zz_129[12] = _zz_128; + _zz_129[11] = _zz_128; + _zz_129[10] = _zz_128; + _zz_129[9] = _zz_128; + _zz_129[8] = _zz_128; + _zz_129[7] = _zz_128; + _zz_129[6] = _zz_128; + _zz_129[5] = _zz_128; + _zz_129[4] = _zz_128; + _zz_129[3] = _zz_128; + _zz_129[2] = _zz_128; + _zz_129[1] = _zz_128; + _zz_129[0] = _zz_128; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : begin + _zz_130 = execute_RS2; + end + default : begin + _zz_130 = {_zz_129,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_130; + assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); + assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); + assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @ (*) begin + CfuPlugin_joinException_valid = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if(memory_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); + end + end + end + + assign CfuPlugin_joinException_payload_code = 4'b1111; + assign CfuPlugin_joinException_payload_badAddr = 32'h0; + always @ (*) begin + memory_CfuPlugin_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + always @ (*) begin + memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; + if(_zz_156)begin + if(_zz_164)begin + memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); + assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); + always @ (*) begin + if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_249); + end + if(memory_MulDivIterativePlugin_mul_counter_willClear)begin + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; + if(_zz_157)begin + if(_zz_181)begin + memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; + if(_zz_182)begin + memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); + assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end else begin + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_257); + end + if(memory_MulDivIterativePlugin_div_counter_willClear)begin + memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_131 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_131[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_258); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_259 : _zz_260); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_261[31:0]; + assign _zz_132 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_133 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_134 = ((execute_IS_MUL && _zz_133) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_135[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_135[31 : 0] = execute_RS1; + end + + assign _zz_137 = (_zz_136 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_137 != 32'h0); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_183) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + debug_bus_cmd_ready = IBusSimplePlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_138))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + always @ (*) begin + IBusSimplePlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_183) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + IBusSimplePlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusSimplePlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_28 = decode_SRC1_CTRL; + assign _zz_26 = _zz_54; + assign _zz_41 = decode_to_execute_SRC1_CTRL; + assign _zz_25 = decode_ALU_CTRL; + assign _zz_23 = _zz_53; + assign _zz_42 = decode_to_execute_ALU_CTRL; + assign _zz_22 = decode_SRC2_CTRL; + assign _zz_20 = _zz_52; + assign _zz_40 = decode_to_execute_SRC2_CTRL; + assign _zz_19 = decode_ALU_BITWISE_CTRL; + assign _zz_17 = _zz_51; + assign _zz_43 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_16 = decode_SHIFT_CTRL; + assign _zz_14 = _zz_50; + assign _zz_38 = decode_to_execute_SHIFT_CTRL; + assign _zz_13 = decode_BRANCH_CTRL; + assign _zz_11 = _zz_49; + assign _zz_36 = decode_to_execute_BRANCH_CTRL; + assign _zz_10 = decode_ENV_CTRL; + assign _zz_7 = execute_ENV_CTRL; + assign _zz_5 = memory_ENV_CTRL; + assign _zz_8 = _zz_48; + assign _zz_34 = decode_to_execute_ENV_CTRL; + assign _zz_33 = execute_to_memory_ENV_CTRL; + assign _zz_35 = memory_to_writeBack_ENV_CTRL; + assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_1 = _zz_47; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + IBusSimplePlugin_injectionPort_ready = 1'b0; + case(_zz_139) + 3'b100 : begin + IBusSimplePlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_140 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_140[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_140[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_140[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_141 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_141[11 : 11] = CsrPlugin_mip_MEIP; + _zz_141[7 : 7] = CsrPlugin_mip_MTIP; + _zz_141[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_142 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_142[11 : 11] = CsrPlugin_mie_MEIE; + _zz_142[7 : 7] = CsrPlugin_mie_MTIE; + _zz_142[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_143 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_143[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_144 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_144[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_144[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_145 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_145[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_146 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_146[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_147 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_147[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_148 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_148[31 : 0] = _zz_136; + end + end + + always @ (*) begin + _zz_149 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_149[31 : 0] = _zz_137; + end + end + + assign execute_CsrPlugin_readData = ((((_zz_140 | _zz_141) | (_zz_142 | _zz_143)) | ((_zz_144 | _zz_145) | (_zz_146 | _zz_147))) | (_zz_148 | _zz_149)); + assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); + assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; + assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; + assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); + assign iBusWishbone_CTI = 3'b000; + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'h0; + assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; + assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; + assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK); + assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = 3'b000; + assign dBusWishbone_BTE = 2'b00; + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_150 = 4'b0001; + end + 2'b01 : begin + _zz_150 = 4'b0011; + end + default : begin + _zz_150 = 4'b1111; + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = (_zz_150 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = 4'b1111; + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + assign _zz_152 = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + IBusSimplePlugin_fetchPc_booted <= 1'b0; + IBusSimplePlugin_fetchPc_inc <= 1'b0; + _zz_66 <= 1'b0; + _zz_67 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusSimplePlugin_pending_value <= 3'b000; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; + _zz_96 <= 1'b1; + execute_LightShifterPlugin_isActive <= 1'b0; + _zz_107 <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_CfuPlugin_hold <= 1'b0; + execute_CfuPlugin_fired <= 1'b0; + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; + memory_MulDivIterativePlugin_div_counter_value <= 6'h0; + _zz_136 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_139 <= 3'b000; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; + iBus_cmd_m2sPipe_rValid <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusSimplePlugin_fetchPc_correction)begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + end + IBusSimplePlugin_fetchPc_booted <= 1'b1; + if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin + IBusSimplePlugin_fetchPc_inc <= 1'b0; + end + if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + end + if(IBusSimplePlugin_iBusRsp_flush)begin + _zz_66 <= 1'b0; + end + if(_zz_64)begin + _zz_66 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(decode_arbitration_removeIt)begin + _zz_67 <= 1'b0; + end + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_67 <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; + end + if(IBusSimplePlugin_fetchPc_flushed)begin + IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_219); + if(IBusSimplePlugin_iBusRsp_flush)begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_221); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + _zz_96 <= 1'b0; + if(_zz_158)begin + if(_zz_184)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + _zz_107 <= (_zz_45 && writeBack_arbitration_isFiring); + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_185)begin + if(_zz_186)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_187)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_188)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_166)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_167)begin + case(_zz_169) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_121,{_zz_120,_zz_119}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(execute_CfuPlugin_schedule)begin + execute_CfuPlugin_hold <= 1'b1; + end + if(CfuPlugin_bus_cmd_ready)begin + execute_CfuPlugin_hold <= 1'b0; + end + if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + execute_CfuPlugin_fired <= 1'b1; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_CfuPlugin_fired <= 1'b0; + end + if(memory_CfuPlugin_rsp_ready)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + end + if(_zz_189)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + end + memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; + memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + if((! memory_arbitration_isStuck))begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_139) + 3'b000 : begin + if(IBusSimplePlugin_injectionPort_valid)begin + _zz_139 <= 3'b001; + end + end + 3'b001 : begin + _zz_139 <= 3'b010; + end + 3'b010 : begin + _zz_139 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_139 <= 3'b100; + end + end + 3'b100 : begin + _zz_139 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_271[0]; + CsrPlugin_mstatus_MIE <= _zz_272[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_274[0]; + CsrPlugin_mie_MTIE <= _zz_275[0]; + CsrPlugin_mie_MSIE <= _zz_276[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_136 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(iBus_cmd_ready)begin + iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; + end + if(_zz_190)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusSimplePlugin_iBusRsp_output_ready)begin + _zz_68 <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_69 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_70 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_71 <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; + end + if(IBusSimplePlugin_injector_decodeInput_ready)begin + IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + end + if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin + IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; + IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; + IBusSimplePlugin_mmu_joinCtx_isPaging <= IBusSimplePlugin_mmuBus_rsp_isPaging; + IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; + IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; + IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; + IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; + IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; + IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; + end + if(_zz_158)begin + if(_zz_184)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); + end + end + _zz_108 <= _zz_44[11 : 7]; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_160)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_123 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_123 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_162)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_127 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_127 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + end + if(_zz_165)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_125 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_125 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + end + if(_zz_185)begin + if(_zz_186)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_187)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_188)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_166)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(_zz_189)begin + CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if(_zz_156)begin + if(_zz_164)begin + memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_250,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + end + end + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_div_done <= 1'b0; + end + if(_zz_157)begin + if(_zz_181)begin + memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; + memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; + if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + memory_MulDivIterativePlugin_div_result <= _zz_262[31:0]; + end + end + end + if(_zz_182)begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_134 ? (~ _zz_135) : _zz_135) + _zz_268); + memory_MulDivIterativePlugin_rs2 <= ((_zz_133 ? (~ execute_RS2) : execute_RS2) + _zz_270); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_134 ^ (_zz_133 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_39; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_56; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_57; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_27; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_24; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_21; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_18; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_15; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_12; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; + execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; + execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; + execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; + execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; + execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; + execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; + execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; + execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + end + if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_29; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end + if((_zz_139 != 3'b000))begin + _zz_70 <= IBusSimplePlugin_injectionPort_payload; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_273[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(iBus_cmd_ready)begin + iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; + end + if(_zz_190)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusSimplePlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_55; + end + _zz_138 <= debug_bus_cmd_payload_address[2]; + if(_zz_161)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_183) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(_zz_161)begin + if(_zz_163)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_168)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module StreamFifoLowLatency ( + input io_push_valid, + output io_push_ready, + input io_push_payload_error, + input [31:0] io_push_payload_inst, + output reg io_pop_valid, + input io_pop_ready, + output reg io_pop_payload_error, + output reg [31:0] io_pop_payload_inst, + input io_flush, + output [0:0] io_occupancy, + input clk, + input reset +); + wire _zz_4; + wire [0:0] _zz_5; + reg _zz_1; + reg pushPtr_willIncrement; + reg pushPtr_willClear; + wire pushPtr_willOverflowIfInc; + wire pushPtr_willOverflow; + reg popPtr_willIncrement; + reg popPtr_willClear; + wire popPtr_willOverflowIfInc; + wire popPtr_willOverflow; + wire ptrMatch; + reg risingOccupancy; + wire empty; + wire full; + wire pushing; + wire popping; + wire [32:0] _zz_2; + reg [32:0] _zz_3; + + assign _zz_4 = (! empty); + assign _zz_5 = _zz_2[0 : 0]; + always @ (*) begin + _zz_1 = 1'b0; + if(pushing)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + pushPtr_willIncrement = 1'b0; + if(pushing)begin + pushPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + pushPtr_willClear = 1'b0; + if(io_flush)begin + pushPtr_willClear = 1'b1; + end + end + + assign pushPtr_willOverflowIfInc = 1'b1; + assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); + always @ (*) begin + popPtr_willIncrement = 1'b0; + if(popping)begin + popPtr_willIncrement = 1'b1; + end + end + + always @ (*) begin + popPtr_willClear = 1'b0; + if(io_flush)begin + popPtr_willClear = 1'b1; + end + end + + assign popPtr_willOverflowIfInc = 1'b1; + assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); + assign ptrMatch = 1'b1; + assign empty = (ptrMatch && (! risingOccupancy)); + assign full = (ptrMatch && risingOccupancy); + assign pushing = (io_push_valid && io_push_ready); + assign popping = (io_pop_valid && io_pop_ready); + assign io_push_ready = (! full); + always @ (*) begin + if(_zz_4)begin + io_pop_valid = 1'b1; + end else begin + io_pop_valid = io_push_valid; + end + end + + assign _zz_2 = _zz_3; + always @ (*) begin + if(_zz_4)begin + io_pop_payload_error = _zz_5[0]; + end else begin + io_pop_payload_error = io_push_payload_error; + end + end + + always @ (*) begin + if(_zz_4)begin + io_pop_payload_inst = _zz_2[32 : 1]; + end else begin + io_pop_payload_inst = io_push_payload_inst; + end + end + + assign io_occupancy = (risingOccupancy && ptrMatch); + always @ (posedge clk) begin + if(reset) begin + risingOccupancy <= 1'b0; + end else begin + if((pushing != popping))begin + risingOccupancy <= pushing; + end + if(io_flush)begin + risingOccupancy <= 1'b0; + end + end + end + + always @ (posedge clk) begin + if(_zz_1)begin + _zz_3 <= {io_push_payload_inst,io_push_payload_error}; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml new file mode 100644 index 0000000..3eeb252 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml @@ -0,0 +1 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index de3058b..9edf0fe 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -6,6 +6,7 @@ import spinal.lib._ import spinal.lib.sim.Phase import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} import vexriscv.plugin.CsrAccess.WRITE_ONLY +import vexriscv.plugin.CsrAccess.READ_ONLY import vexriscv.plugin._ import scala.collection.mutable.ArrayBuffer @@ -78,7 +79,7 @@ object GenCoreDefault{ opt[String]("machineTrapVector") action { (v, c) => c.copy(machineTrapVector = BigInt(if(v.startsWith("0x")) v.tail.tail else v, 16)) } text("Specify the CPU machine trap vector in hexadecimal. If not specified, it take a unknown value when the design boot") opt[String]("prediction") action { (v, c) => c.copy(prediction = predictionMap(v)) } text("switch between regular CSR and array like one") opt[String]("outputFile") action { (v, c) => c.copy(outputFile = v) } text("output file name") - opt[String]("csrPluginConfig") action { (v, c) => c.copy(csrPluginConfig = v) } text("switch between 'small', 'all', 'linux' and 'linux-minimal' version of control and status registers configuration") + opt[String]("csrPluginConfig") action { (v, c) => c.copy(csrPluginConfig = v) } text("switch between 'small', 'mcycle', 'all', 'linux' and 'linux-minimal' version of control and status registers configuration") } val argConfig = parser.parse(args, ArgConfig()).get val linux = argConfig.csrPluginConfig.startsWith("linux") @@ -190,6 +191,7 @@ object GenCoreDefault{ new CsrPlugin( argConfig.csrPluginConfig match { case "small" => CsrPluginConfig.small(mtvecInit = argConfig.machineTrapVector).copy(mtvecAccess = WRITE_ONLY, ecallGen = true, wfiGenAsNop = true) + case "mcycle" => CsrPluginConfig.small(mtvecInit = argConfig.machineTrapVector).copy(mcycleAccess = READ_ONLY, mtvecAccess = WRITE_ONLY, ecallGen = true, wfiGenAsNop = true) case "all" => CsrPluginConfig.all(mtvecInit = argConfig.machineTrapVector) case "linux" => CsrPluginConfig.linuxFull(mtVecInit = argConfig.machineTrapVector).copy(ebreakGen = false) case "linux-minimal" => CsrPluginConfig.linuxMinimal(mtVecInit = argConfig.machineTrapVector).copy(ebreakGen = false) From 301554ed50130998df7c9b3fa2a900ddbefe2027 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Fri, 11 Jun 2021 13:18:35 -0700 Subject: [PATCH 19/30] Trim Fomu variants by removing alignment etc. checks. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 4 +- .../verilog/VexRiscv_Fomu.v | 1966 +++++++-------- .../verilog/VexRiscv_FomuCfu.v | 2194 ++++++++--------- .../main/scala/vexriscv/GenCoreDefault.scala | 14 +- 4 files changed, 2004 insertions(+), 2174 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index bce4596..9c4c5fc 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -27,10 +27,10 @@ VexRiscv_MinDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 0 --dCacheSize 0 --mulDiv false --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_MinDebug" VexRiscv_Fomu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --iCacheSize 0 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_Fomu" + sbt compile "runMain vexriscv.GenCoreDefault --safe false --iCacheSize 0 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_Fomu" VexRiscv_FomuCfu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault -d --cfu true --iCacheSize 0 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_FomuCfu" + sbt compile "runMain vexriscv.GenCoreDefault --safe false -d --cfu true --iCacheSize 0 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_FomuCfu" VexRiscv_Full.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --outputFile VexRiscv_Full" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v index 3f216eb..0e5d63c 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : aa12b0d45ab170fd03927c0d06fa62f6bd8e840f +// Git hash : 848042f3e4812615884ef1061d617c4d5bf6e8c2 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -25,17 +25,17 @@ `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 `define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + `define Src2CtrlEnum_defaultEncoding_type [1:0] `define Src2CtrlEnum_defaultEncoding_RS 2'b00 `define Src2CtrlEnum_defaultEncoding_IMI 2'b01 `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - `define Src1CtrlEnum_defaultEncoding_type [1:0] `define Src1CtrlEnum_defaultEncoding_RS 2'b00 `define Src1CtrlEnum_defaultEncoding_IMU 2'b01 @@ -73,16 +73,19 @@ module VexRiscv ( input clk, input reset ); - wire _zz_134; - wire _zz_135; - reg [31:0] _zz_136; - reg [31:0] _zz_137; - reg [31:0] _zz_138; + wire _zz_131; + wire _zz_132; + reg [31:0] _zz_133; + reg [31:0] _zz_134; + reg [31:0] _zz_135; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_136; + wire _zz_137; + wire _zz_138; wire _zz_139; wire _zz_140; wire _zz_141; @@ -92,7 +95,7 @@ module VexRiscv ( wire _zz_145; wire _zz_146; wire _zz_147; - wire [1:0] _zz_148; + wire _zz_148; wire _zz_149; wire _zz_150; wire _zz_151; @@ -105,15 +108,15 @@ module VexRiscv ( wire _zz_158; wire _zz_159; wire _zz_160; - wire _zz_161; - wire _zz_162; + wire [1:0] _zz_161; + wire [1:0] _zz_162; wire _zz_163; - wire _zz_164; - wire _zz_165; - wire _zz_166; - wire _zz_167; - wire [1:0] _zz_168; - wire _zz_169; + wire [0:0] _zz_164; + wire [0:0] _zz_165; + wire [0:0] _zz_166; + wire [0:0] _zz_167; + wire [0:0] _zz_168; + wire [0:0] _zz_169; wire [0:0] _zz_170; wire [0:0] _zz_171; wire [0:0] _zz_172; @@ -123,233 +126,210 @@ module VexRiscv ( wire [0:0] _zz_176; wire [0:0] _zz_177; wire [0:0] _zz_178; - wire [0:0] _zz_179; - wire [0:0] _zz_180; - wire [0:0] _zz_181; - wire [0:0] _zz_182; + wire [2:0] _zz_179; + wire [2:0] _zz_180; + wire [31:0] _zz_181; + wire [2:0] _zz_182; wire [0:0] _zz_183; - wire [0:0] _zz_184; - wire [2:0] _zz_185; + wire [2:0] _zz_184; + wire [0:0] _zz_185; wire [2:0] _zz_186; - wire [31:0] _zz_187; + wire [0:0] _zz_187; wire [2:0] _zz_188; wire [0:0] _zz_189; wire [2:0] _zz_190; wire [0:0] _zz_191; wire [2:0] _zz_192; - wire [0:0] _zz_193; - wire [2:0] _zz_194; - wire [0:0] _zz_195; - wire [2:0] _zz_196; - wire [2:0] _zz_197; - wire [0:0] _zz_198; - wire [2:0] _zz_199; - wire [4:0] _zz_200; - wire [11:0] _zz_201; - wire [11:0] _zz_202; + wire [4:0] _zz_193; + wire [11:0] _zz_194; + wire [11:0] _zz_195; + wire [31:0] _zz_196; + wire [31:0] _zz_197; + wire [31:0] _zz_198; + wire [31:0] _zz_199; + wire [31:0] _zz_200; + wire [31:0] _zz_201; + wire [31:0] _zz_202; wire [31:0] _zz_203; - wire [31:0] _zz_204; - wire [31:0] _zz_205; - wire [31:0] _zz_206; - wire [31:0] _zz_207; - wire [31:0] _zz_208; - wire [31:0] _zz_209; - wire [31:0] _zz_210; + wire [32:0] _zz_204; + wire [19:0] _zz_205; + wire [11:0] _zz_206; + wire [11:0] _zz_207; + wire [0:0] _zz_208; + wire [5:0] _zz_209; + wire [33:0] _zz_210; wire [32:0] _zz_211; - wire [19:0] _zz_212; - wire [11:0] _zz_213; - wire [11:0] _zz_214; - wire [1:0] _zz_215; - wire [1:0] _zz_216; - wire [1:0] _zz_217; - wire [1:0] _zz_218; - wire [0:0] _zz_219; - wire [5:0] _zz_220; - wire [33:0] _zz_221; + wire [33:0] _zz_212; + wire [32:0] _zz_213; + wire [33:0] _zz_214; + wire [32:0] _zz_215; + wire [0:0] _zz_216; + wire [5:0] _zz_217; + wire [32:0] _zz_218; + wire [31:0] _zz_219; + wire [31:0] _zz_220; + wire [32:0] _zz_221; wire [32:0] _zz_222; - wire [33:0] _zz_223; + wire [32:0] _zz_223; wire [32:0] _zz_224; - wire [33:0] _zz_225; + wire [0:0] _zz_225; wire [32:0] _zz_226; wire [0:0] _zz_227; - wire [5:0] _zz_228; - wire [32:0] _zz_229; + wire [32:0] _zz_228; + wire [0:0] _zz_229; wire [31:0] _zz_230; - wire [31:0] _zz_231; - wire [32:0] _zz_232; - wire [32:0] _zz_233; - wire [32:0] _zz_234; - wire [32:0] _zz_235; + wire [0:0] _zz_231; + wire [0:0] _zz_232; + wire [0:0] _zz_233; + wire [0:0] _zz_234; + wire [0:0] _zz_235; wire [0:0] _zz_236; - wire [32:0] _zz_237; - wire [0:0] _zz_238; - wire [32:0] _zz_239; - wire [0:0] _zz_240; - wire [31:0] _zz_241; - wire [0:0] _zz_242; + wire _zz_237; + wire _zz_238; + wire [1:0] _zz_239; + wire [31:0] _zz_240; + wire [0:0] _zz_241; + wire [1:0] _zz_242; wire [0:0] _zz_243; wire [0:0] _zz_244; - wire [0:0] _zz_245; + wire _zz_245; wire [0:0] _zz_246; - wire [0:0] _zz_247; - wire _zz_248; - wire _zz_249; - wire [1:0] _zz_250; - wire [31:0] _zz_251; - wire [31:0] _zz_252; - wire [31:0] _zz_253; - wire _zz_254; - wire [0:0] _zz_255; - wire [12:0] _zz_256; - wire [31:0] _zz_257; + wire [23:0] _zz_247; + wire [31:0] _zz_248; + wire [31:0] _zz_249; + wire [31:0] _zz_250; + wire [0:0] _zz_251; + wire [0:0] _zz_252; + wire [1:0] _zz_253; + wire [1:0] _zz_254; + wire _zz_255; + wire [0:0] _zz_256; + wire [19:0] _zz_257; wire [31:0] _zz_258; wire [31:0] _zz_259; - wire _zz_260; - wire [0:0] _zz_261; - wire [6:0] _zz_262; + wire [31:0] _zz_260; + wire [31:0] _zz_261; + wire [31:0] _zz_262; wire [31:0] _zz_263; - wire [31:0] _zz_264; - wire [31:0] _zz_265; - wire _zz_266; - wire [0:0] _zz_267; - wire [0:0] _zz_268; - wire [31:0] _zz_269; - wire [0:0] _zz_270; - wire [1:0] _zz_271; - wire [0:0] _zz_272; - wire [0:0] _zz_273; - wire _zz_274; - wire [0:0] _zz_275; - wire [23:0] _zz_276; - wire [31:0] _zz_277; - wire [31:0] _zz_278; - wire [31:0] _zz_279; + wire [0:0] _zz_264; + wire [0:0] _zz_265; + wire [1:0] _zz_266; + wire [1:0] _zz_267; + wire _zz_268; + wire [0:0] _zz_269; + wire [16:0] _zz_270; + wire [31:0] _zz_271; + wire [31:0] _zz_272; + wire [31:0] _zz_273; + wire [31:0] _zz_274; + wire [31:0] _zz_275; + wire [31:0] _zz_276; + wire _zz_277; + wire [0:0] _zz_278; + wire [0:0] _zz_279; wire [0:0] _zz_280; - wire [0:0] _zz_281; - wire [1:0] _zz_282; - wire [1:0] _zz_283; + wire [1:0] _zz_281; + wire [0:0] _zz_282; + wire [0:0] _zz_283; wire _zz_284; wire [0:0] _zz_285; - wire [19:0] _zz_286; + wire [13:0] _zz_286; wire [31:0] _zz_287; wire [31:0] _zz_288; wire [31:0] _zz_289; wire [31:0] _zz_290; wire [31:0] _zz_291; wire [31:0] _zz_292; - wire [0:0] _zz_293; - wire [0:0] _zz_294; - wire [2:0] _zz_295; - wire [2:0] _zz_296; - wire _zz_297; - wire [0:0] _zz_298; - wire [16:0] _zz_299; - wire [31:0] _zz_300; - wire [31:0] _zz_301; - wire [31:0] _zz_302; + wire [31:0] _zz_293; + wire _zz_294; + wire _zz_295; + wire [31:0] _zz_296; + wire [31:0] _zz_297; + wire [1:0] _zz_298; + wire [1:0] _zz_299; + wire _zz_300; + wire [0:0] _zz_301; + wire [11:0] _zz_302; wire [31:0] _zz_303; - wire _zz_304; - wire _zz_305; - wire _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire _zz_312; - wire [0:0] _zz_313; - wire [13:0] _zz_314; + wire [31:0] _zz_304; + wire [31:0] _zz_305; + wire [31:0] _zz_306; + wire _zz_307; + wire _zz_308; + wire [1:0] _zz_309; + wire [1:0] _zz_310; + wire _zz_311; + wire [0:0] _zz_312; + wire [8:0] _zz_313; + wire [31:0] _zz_314; wire [31:0] _zz_315; wire [31:0] _zz_316; wire [31:0] _zz_317; wire [31:0] _zz_318; wire [31:0] _zz_319; - wire [31:0] _zz_320; - wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [0:0] _zz_323; + wire _zz_320; + wire [2:0] _zz_321; + wire [2:0] _zz_322; + wire _zz_323; wire [0:0] _zz_324; - wire [1:0] _zz_325; - wire [1:0] _zz_326; + wire [5:0] _zz_325; + wire _zz_326; wire _zz_327; wire [0:0] _zz_328; - wire [11:0] _zz_329; - wire [31:0] _zz_330; - wire [31:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [31:0] _zz_334; - wire [31:0] _zz_335; - wire _zz_336; - wire [0:0] _zz_337; - wire [0:0] _zz_338; - wire _zz_339; - wire [0:0] _zz_340; - wire [0:0] _zz_341; - wire _zz_342; - wire [0:0] _zz_343; - wire [8:0] _zz_344; + wire [3:0] _zz_329; + wire [0:0] _zz_330; + wire [0:0] _zz_331; + wire [1:0] _zz_332; + wire [1:0] _zz_333; + wire _zz_334; + wire [0:0] _zz_335; + wire [2:0] _zz_336; + wire [31:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [31:0] _zz_340; + wire _zz_341; + wire [0:0] _zz_342; + wire [1:0] _zz_343; + wire [31:0] _zz_344; wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [0:0] _zz_348; + wire _zz_346; + wire [0:0] _zz_347; + wire [2:0] _zz_348; wire [0:0] _zz_349; wire [0:0] _zz_350; - wire [4:0] _zz_351; - wire [1:0] _zz_352; - wire [1:0] _zz_353; - wire _zz_354; - wire [0:0] _zz_355; - wire [5:0] _zz_356; - wire [31:0] _zz_357; - wire [31:0] _zz_358; + wire _zz_351; + wire [0:0] _zz_352; + wire [0:0] _zz_353; + wire [31:0] _zz_354; + wire [31:0] _zz_355; + wire [31:0] _zz_356; + wire _zz_357; + wire _zz_358; wire [31:0] _zz_359; wire [31:0] _zz_360; - wire _zz_361; - wire [0:0] _zz_362; - wire [1:0] _zz_363; - wire [31:0] _zz_364; + wire [31:0] _zz_361; + wire _zz_362; + wire [0:0] _zz_363; + wire [0:0] _zz_364; wire [31:0] _zz_365; - wire _zz_366; + wire [31:0] _zz_366; wire [0:0] _zz_367; - wire [0:0] _zz_368; - wire [0:0] _zz_369; - wire [0:0] _zz_370; - wire _zz_371; - wire [0:0] _zz_372; - wire [2:0] _zz_373; + wire [1:0] _zz_368; + wire [1:0] _zz_369; + wire [1:0] _zz_370; + wire [1:0] _zz_371; + wire [1:0] _zz_372; + wire [31:0] _zz_373; wire [31:0] _zz_374; wire [31:0] _zz_375; wire [31:0] _zz_376; - wire _zz_377; - wire _zz_378; + wire [31:0] _zz_377; + wire [31:0] _zz_378; wire [31:0] _zz_379; wire [31:0] _zz_380; wire [31:0] _zz_381; wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire [31:0] _zz_384; - wire [31:0] _zz_385; - wire [0:0] _zz_386; - wire [2:0] _zz_387; - wire [0:0] _zz_388; - wire [0:0] _zz_389; - wire _zz_390; - wire [0:0] _zz_391; - wire [0:0] _zz_392; - wire [31:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire _zz_396; - wire _zz_397; - wire [31:0] _zz_398; - wire _zz_399; - wire [0:0] _zz_400; - wire [0:0] _zz_401; - wire [0:0] _zz_402; - wire [0:0] _zz_403; - wire [0:0] _zz_404; - wire [0:0] _zz_405; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -388,18 +368,18 @@ module VexRiscv ( wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; wire decode_SRC_LESS_UNSIGNED; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_17; + wire `AluCtrlEnum_defaultEncoding_type _zz_18; + wire `AluCtrlEnum_defaultEncoding_type _zz_19; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_17; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; wire `Src1CtrlEnum_defaultEncoding_type _zz_23; wire `Src1CtrlEnum_defaultEncoding_type _zz_24; @@ -464,13 +444,12 @@ module VexRiscv ( reg _zz_40; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; wire `EnvCtrlEnum_defaultEncoding_type _zz_41; wire `BranchCtrlEnum_defaultEncoding_type _zz_42; wire `ShiftCtrlEnum_defaultEncoding_type _zz_43; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_44; - wire `Src2CtrlEnum_defaultEncoding_type _zz_45; - wire `AluCtrlEnum_defaultEncoding_type _zz_46; + wire `AluCtrlEnum_defaultEncoding_type _zz_45; + wire `Src2CtrlEnum_defaultEncoding_type _zz_46; wire `Src1CtrlEnum_defaultEncoding_type _zz_47; wire writeBack_MEMORY_STORE; reg [31:0] _zz_48; @@ -488,7 +467,6 @@ module VexRiscv ( wire memory_MMU_RSP2_refilling; wire memory_MMU_RSP2_bypassTranslation; wire [31:0] memory_PC; - wire memory_ALIGNEMENT_FAULT; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; @@ -612,14 +590,8 @@ module VexRiscv ( wire DBusSimplePlugin_mmuBus_busy; reg DBusSimplePlugin_redoBranch_valid; wire [31:0] DBusSimplePlugin_redoBranch_payload; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; - wire BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; wire CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -765,13 +737,14 @@ module VexRiscv ( wire _zz_76; wire _zz_77; wire _zz_78; - wire `Src1CtrlEnum_defaultEncoding_type _zz_79; - wire `AluCtrlEnum_defaultEncoding_type _zz_80; + wire _zz_79; + wire `Src1CtrlEnum_defaultEncoding_type _zz_80; wire `Src2CtrlEnum_defaultEncoding_type _zz_81; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_82; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_83; - wire `BranchCtrlEnum_defaultEncoding_type _zz_84; - wire `EnvCtrlEnum_defaultEncoding_type _zz_85; + wire `AluCtrlEnum_defaultEncoding_type _zz_82; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_83; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_84; + wire `BranchCtrlEnum_defaultEncoding_type _zz_85; + wire `EnvCtrlEnum_defaultEncoding_type _zz_86; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -779,15 +752,15 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_86; + reg _zz_87; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_87; reg [31:0] _zz_88; - wire _zz_89; - reg [19:0] _zz_90; - wire _zz_91; - reg [19:0] _zz_92; - reg [31:0] _zz_93; + reg [31:0] _zz_89; + wire _zz_90; + reg [19:0] _zz_91; + wire _zz_92; + reg [19:0] _zz_93; + reg [31:0] _zz_94; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; @@ -796,23 +769,23 @@ module VexRiscv ( wire [4:0] execute_LightShifterPlugin_amplitude; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_94; - reg _zz_95; + reg [31:0] _zz_95; reg _zz_96; reg _zz_97; - reg [4:0] _zz_98; + reg _zz_98; + reg [4:0] _zz_99; wire execute_BranchPlugin_eq; - wire [2:0] _zz_99; - reg _zz_100; + wire [2:0] _zz_100; reg _zz_101; + reg _zz_102; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_102; - reg [10:0] _zz_103; - wire _zz_104; - reg [19:0] _zz_105; - wire _zz_106; - reg [18:0] _zz_107; - reg [31:0] _zz_108; + wire _zz_103; + reg [10:0] _zz_104; + wire _zz_105; + reg [19:0] _zz_106; + wire _zz_107; + reg [18:0] _zz_108; + reg [31:0] _zz_109; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -834,9 +807,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_109; wire _zz_110; wire _zz_111; + wire _zz_112; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -849,10 +822,6 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_112; - wire _zz_113; - wire [1:0] _zz_114; - wire _zz_115; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -900,18 +869,18 @@ module VexRiscv ( wire memory_MulDivIterativePlugin_div_counter_willOverflow; reg memory_MulDivIterativePlugin_div_done; reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_116; + wire [31:0] _zz_113; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [31:0] _zz_117; - wire _zz_118; - wire _zz_119; - reg [32:0] _zz_120; + wire [31:0] _zz_114; + wire _zz_115; + wire _zz_116; + reg [32:0] _zz_117; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_121; - wire [31:0] _zz_122; + reg [31:0] _zz_118; + wire [31:0] _zz_119; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -926,7 +895,6 @@ module VexRiscv ( reg decode_to_execute_MEMORY_ENABLE; reg execute_to_memory_MEMORY_ENABLE; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; reg decode_to_execute_REGFILE_WRITE_VALID; reg execute_to_memory_REGFILE_WRITE_VALID; @@ -937,6 +905,7 @@ module VexRiscv ( reg decode_to_execute_MEMORY_STORE; reg execute_to_memory_MEMORY_STORE; reg memory_to_writeBack_MEMORY_STORE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; reg decode_to_execute_SRC_LESS_UNSIGNED; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; @@ -956,7 +925,6 @@ module VexRiscv ( reg decode_to_execute_SRC2_FORCE_ZERO; reg decode_to_execute_CSR_WRITE_OPCODE; reg decode_to_execute_CSR_READ_OPCODE; - reg execute_to_memory_ALIGNEMENT_FAULT; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; reg execute_to_memory_MMU_FAULT; @@ -985,6 +953,9 @@ module VexRiscv ( reg execute_CsrPlugin_csr_2944; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_120; + reg [31:0] _zz_121; + reg [31:0] _zz_122; reg [31:0] _zz_123; reg [31:0] _zz_124; reg [31:0] _zz_125; @@ -992,9 +963,6 @@ module VexRiscv ( reg [31:0] _zz_127; reg [31:0] _zz_128; reg [31:0] _zz_129; - reg [31:0] _zz_130; - reg [31:0] _zz_131; - reg [31:0] _zz_132; wire iBus_cmd_m2sPipe_valid; wire iBus_cmd_m2sPipe_ready; wire [31:0] iBus_cmd_m2sPipe_payload_pc; @@ -1012,7 +980,7 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_133; + reg [3:0] _zz_130; `ifndef SYNTHESIS reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; @@ -1034,14 +1002,14 @@ module VexRiscv ( reg [39:0] _zz_14_string; reg [39:0] _zz_15_string; reg [39:0] _zz_16_string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_17_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_20_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; + reg [63:0] _zz_17_string; + reg [63:0] _zz_18_string; + reg [63:0] _zz_19_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_20_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; reg [95:0] decode_SRC1_CTRL_string; reg [95:0] _zz_23_string; reg [95:0] _zz_24_string; @@ -1068,19 +1036,19 @@ module VexRiscv ( reg [31:0] _zz_42_string; reg [71:0] _zz_43_string; reg [39:0] _zz_44_string; - reg [23:0] _zz_45_string; - reg [63:0] _zz_46_string; + reg [63:0] _zz_45_string; + reg [23:0] _zz_46_string; reg [95:0] _zz_47_string; - reg [95:0] _zz_79_string; - reg [63:0] _zz_80_string; + reg [95:0] _zz_80_string; reg [23:0] _zz_81_string; - reg [39:0] _zz_82_string; - reg [71:0] _zz_83_string; - reg [31:0] _zz_84_string; - reg [39:0] _zz_85_string; + reg [63:0] _zz_82_string; + reg [39:0] _zz_83_string; + reg [71:0] _zz_84_string; + reg [31:0] _zz_85_string; + reg [39:0] _zz_86_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; @@ -1091,282 +1059,262 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_139 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_140 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_141 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_142 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_143 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_144 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_145 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_146 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_147 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_148 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_149 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_150 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_151 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_152 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_153 = (1'b1 || (! 1'b1)); - assign _zz_154 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_155 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_156 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_157 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_158 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_159 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_160 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_161 = (! memory_arbitration_isStuck); - assign _zz_162 = (! execute_arbitration_isStuckByOthers); - assign _zz_163 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_164 = ((_zz_109 && 1'b1) && (! 1'b0)); - assign _zz_165 = ((_zz_110 && 1'b1) && (! 1'b0)); - assign _zz_166 = ((_zz_111 && 1'b1) && (! 1'b0)); - assign _zz_167 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_168 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_169 = execute_INSTRUCTION[13]; - assign _zz_170 = _zz_72[29 : 29]; - assign _zz_171 = _zz_72[28 : 28]; - assign _zz_172 = _zz_72[27 : 27]; - assign _zz_173 = _zz_72[26 : 26]; - assign _zz_174 = _zz_72[23 : 23]; - assign _zz_175 = _zz_72[15 : 15]; - assign _zz_176 = _zz_72[12 : 12]; - assign _zz_177 = _zz_72[11 : 11]; - assign _zz_178 = _zz_72[10 : 10]; - assign _zz_179 = _zz_72[14 : 14]; - assign _zz_180 = _zz_72[4 : 4]; - assign _zz_181 = _zz_72[2 : 2]; - assign _zz_182 = _zz_72[18 : 18]; - assign _zz_183 = _zz_72[9 : 9]; - assign _zz_184 = _zz_72[3 : 3]; - assign _zz_185 = (_zz_50 - 3'b001); - assign _zz_186 = {IBusSimplePlugin_fetchPc_inc,2'b00}; - assign _zz_187 = {29'd0, _zz_186}; - assign _zz_188 = (IBusSimplePlugin_pending_value + _zz_190); - assign _zz_189 = IBusSimplePlugin_pending_inc; + assign _zz_136 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_137 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_138 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_139 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_140 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_141 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_142 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_143 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); + assign _zz_144 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_145 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_146 = (1'b1 || (! 1'b1)); + assign _zz_147 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_148 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_149 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_150 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_151 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_152 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_153 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_154 = (! memory_arbitration_isStuck); + assign _zz_155 = (! execute_arbitration_isStuckByOthers); + assign _zz_156 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_157 = ((_zz_110 && 1'b1) && (! 1'b0)); + assign _zz_158 = ((_zz_111 && 1'b1) && (! 1'b0)); + assign _zz_159 = ((_zz_112 && 1'b1) && (! 1'b0)); + assign _zz_160 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_161 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_162 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_163 = execute_INSTRUCTION[13]; + assign _zz_164 = _zz_72[29 : 29]; + assign _zz_165 = _zz_72[28 : 28]; + assign _zz_166 = _zz_72[27 : 27]; + assign _zz_167 = _zz_72[26 : 26]; + assign _zz_168 = _zz_72[23 : 23]; + assign _zz_169 = _zz_72[14 : 14]; + assign _zz_170 = _zz_72[10 : 10]; + assign _zz_171 = _zz_72[9 : 9]; + assign _zz_172 = _zz_72[8 : 8]; + assign _zz_173 = _zz_72[11 : 11]; + assign _zz_174 = _zz_72[4 : 4]; + assign _zz_175 = _zz_72[2 : 2]; + assign _zz_176 = _zz_72[17 : 17]; + assign _zz_177 = _zz_72[7 : 7]; + assign _zz_178 = _zz_72[3 : 3]; + assign _zz_179 = (_zz_50 - 3'b001); + assign _zz_180 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_181 = {29'd0, _zz_180}; + assign _zz_182 = (IBusSimplePlugin_pending_value + _zz_184); + assign _zz_183 = IBusSimplePlugin_pending_inc; + assign _zz_184 = {2'd0, _zz_183}; + assign _zz_185 = IBusSimplePlugin_pending_dec; + assign _zz_186 = {2'd0, _zz_185}; + assign _zz_187 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_188 = {2'd0, _zz_187}; + assign _zz_189 = IBusSimplePlugin_pending_dec; assign _zz_190 = {2'd0, _zz_189}; - assign _zz_191 = IBusSimplePlugin_pending_dec; - assign _zz_192 = {2'd0, _zz_191}; - assign _zz_193 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); - assign _zz_194 = {2'd0, _zz_193}; - assign _zz_195 = IBusSimplePlugin_pending_dec; - assign _zz_196 = {2'd0, _zz_195}; - assign _zz_197 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_198 = execute_SRC_LESS; - assign _zz_199 = 3'b100; - assign _zz_200 = execute_INSTRUCTION[19 : 15]; - assign _zz_201 = execute_INSTRUCTION[31 : 20]; - assign _zz_202 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_203 = ($signed(_zz_204) + $signed(_zz_207)); - assign _zz_204 = ($signed(_zz_205) + $signed(_zz_206)); - assign _zz_205 = execute_SRC1; - assign _zz_206 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_207 = (execute_SRC_USE_SUB_LESS ? _zz_208 : _zz_209); - assign _zz_208 = 32'h00000001; - assign _zz_209 = 32'h0; - assign _zz_210 = (_zz_211 >>> 1); - assign _zz_211 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_212 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_213 = execute_INSTRUCTION[31 : 20]; - assign _zz_214 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_215 = (_zz_112 & (~ _zz_216)); - assign _zz_216 = (_zz_112 - 2'b01); - assign _zz_217 = (_zz_114 & (~ _zz_218)); - assign _zz_218 = (_zz_114 - 2'b01); - assign _zz_219 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_220 = {5'd0, _zz_219}; - assign _zz_221 = (_zz_223 + _zz_225); - assign _zz_222 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_223 = {{1{_zz_222[32]}}, _zz_222}; - assign _zz_224 = _zz_226; - assign _zz_225 = {{1{_zz_224[32]}}, _zz_224}; - assign _zz_226 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_227 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_228 = {5'd0, _zz_227}; - assign _zz_229 = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_230 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_231 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_232 = {_zz_116,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_233 = _zz_234; - assign _zz_234 = _zz_235; - assign _zz_235 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_117) : _zz_117)} + _zz_237); - assign _zz_236 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_237 = {32'd0, _zz_236}; - assign _zz_238 = _zz_119; - assign _zz_239 = {32'd0, _zz_238}; - assign _zz_240 = _zz_118; - assign _zz_241 = {31'd0, _zz_240}; - assign _zz_242 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_243 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_244 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_245 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_246 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_247 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_248 = 1'b1; - assign _zz_249 = 1'b1; - assign _zz_250 = {_zz_53,_zz_52}; - assign _zz_251 = 32'h0000107f; - assign _zz_252 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_253 = 32'h00002073; - assign _zz_254 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_255 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_256 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_257) == 32'h00000003),{(_zz_258 == _zz_259),{_zz_260,{_zz_261,_zz_262}}}}}}; - assign _zz_257 = 32'h0000505f; - assign _zz_258 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_259 = 32'h00000063; - assign _zz_260 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_261 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_262 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_263) == 32'h00005033),{(_zz_264 == _zz_265),{_zz_266,{_zz_267,_zz_268}}}}}}; - assign _zz_263 = 32'hbe00707f; - assign _zz_264 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_265 = 32'h00000033; - assign _zz_266 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_267 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_268 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); - assign _zz_269 = 32'h02004064; - assign _zz_270 = _zz_78; - assign _zz_271 = {_zz_76,_zz_77}; - assign _zz_272 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_273 = 1'b0; - assign _zz_274 = (((decode_INSTRUCTION & _zz_277) == 32'h00000050) != 1'b0); - assign _zz_275 = ((_zz_278 == _zz_279) != 1'b0); - assign _zz_276 = {({_zz_280,_zz_281} != 2'b00),{(_zz_282 != _zz_283),{_zz_284,{_zz_285,_zz_286}}}}; - assign _zz_277 = 32'h10003050; - assign _zz_278 = (decode_INSTRUCTION & 32'h10403050); - assign _zz_279 = 32'h10000050; - assign _zz_280 = ((decode_INSTRUCTION & _zz_287) == 32'h00001050); - assign _zz_281 = ((decode_INSTRUCTION & _zz_288) == 32'h00002050); - assign _zz_282 = {_zz_75,(_zz_289 == _zz_290)}; - assign _zz_283 = 2'b00; - assign _zz_284 = ((_zz_291 == _zz_292) != 1'b0); - assign _zz_285 = ({_zz_293,_zz_294} != 2'b00); - assign _zz_286 = {(_zz_295 != _zz_296),{_zz_297,{_zz_298,_zz_299}}}; - assign _zz_287 = 32'h00001050; - assign _zz_288 = 32'h00002050; - assign _zz_289 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_290 = 32'h00000004; - assign _zz_291 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_292 = 32'h00000040; - assign _zz_293 = ((decode_INSTRUCTION & _zz_300) == 32'h00005010); - assign _zz_294 = ((decode_INSTRUCTION & _zz_301) == 32'h00005020); - assign _zz_295 = {(_zz_302 == _zz_303),{_zz_304,_zz_305}}; - assign _zz_296 = 3'b000; - assign _zz_297 = ({_zz_306,{_zz_307,_zz_308}} != 3'b000); - assign _zz_298 = (_zz_309 != 1'b0); - assign _zz_299 = {(_zz_310 != _zz_311),{_zz_312,{_zz_313,_zz_314}}}; - assign _zz_300 = 32'h00007034; - assign _zz_301 = 32'h02007064; - assign _zz_302 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_303 = 32'h40001010; - assign _zz_304 = ((decode_INSTRUCTION & _zz_315) == 32'h00001010); - assign _zz_305 = ((decode_INSTRUCTION & _zz_316) == 32'h00001010); - assign _zz_306 = ((decode_INSTRUCTION & _zz_317) == 32'h00000024); - assign _zz_307 = (_zz_318 == _zz_319); - assign _zz_308 = (_zz_320 == _zz_321); - assign _zz_309 = ((decode_INSTRUCTION & _zz_322) == 32'h00001000); - assign _zz_310 = _zz_76; - assign _zz_311 = 1'b0; - assign _zz_312 = ({_zz_323,_zz_324} != 2'b00); - assign _zz_313 = (_zz_325 != _zz_326); - assign _zz_314 = {_zz_327,{_zz_328,_zz_329}}; - assign _zz_315 = 32'h00007034; - assign _zz_316 = 32'h02007054; - assign _zz_317 = 32'h00000064; - assign _zz_318 = (decode_INSTRUCTION & 32'h00003034); - assign _zz_319 = 32'h00001010; - assign _zz_320 = (decode_INSTRUCTION & 32'h02003054); - assign _zz_321 = 32'h00001010; - assign _zz_322 = 32'h00001000; - assign _zz_323 = ((decode_INSTRUCTION & _zz_330) == 32'h00002000); - assign _zz_324 = ((decode_INSTRUCTION & _zz_331) == 32'h00001000); - assign _zz_325 = {(_zz_332 == _zz_333),(_zz_334 == _zz_335)}; - assign _zz_326 = 2'b00; - assign _zz_327 = ({_zz_336,{_zz_337,_zz_338}} != 3'b000); - assign _zz_328 = (_zz_339 != 1'b0); - assign _zz_329 = {(_zz_340 != _zz_341),{_zz_342,{_zz_343,_zz_344}}}; - assign _zz_330 = 32'h00002010; - assign _zz_331 = 32'h00005000; - assign _zz_332 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_333 = 32'h00000020; - assign _zz_334 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_335 = 32'h00000020; - assign _zz_336 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); - assign _zz_337 = ((decode_INSTRUCTION & _zz_345) == 32'h0); - assign _zz_338 = ((decode_INSTRUCTION & _zz_346) == 32'h00000040); - assign _zz_339 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz_340 = ((decode_INSTRUCTION & _zz_347) == 32'h00000010); - assign _zz_341 = 1'b0; - assign _zz_342 = ({_zz_74,{_zz_348,_zz_349}} != 3'b000); - assign _zz_343 = ({_zz_350,_zz_351} != 6'h0); - assign _zz_344 = {(_zz_352 != _zz_353),{_zz_354,{_zz_355,_zz_356}}}; - assign _zz_345 = 32'h00000038; - assign _zz_346 = 32'h00403040; - assign _zz_347 = 32'h00000010; - assign _zz_348 = ((decode_INSTRUCTION & _zz_357) == 32'h00000010); - assign _zz_349 = ((decode_INSTRUCTION & _zz_358) == 32'h00000020); - assign _zz_350 = _zz_75; - assign _zz_351 = {(_zz_359 == _zz_360),{_zz_361,{_zz_362,_zz_363}}}; - assign _zz_352 = {_zz_74,(_zz_364 == _zz_365)}; - assign _zz_353 = 2'b00; - assign _zz_354 = ({_zz_74,_zz_366} != 2'b00); - assign _zz_355 = ({_zz_367,_zz_368} != 2'b00); - assign _zz_356 = {(_zz_369 != _zz_370),{_zz_371,{_zz_372,_zz_373}}}; - assign _zz_357 = 32'h00000030; - assign _zz_358 = 32'h02000060; - assign _zz_359 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_360 = 32'h00001010; - assign _zz_361 = ((decode_INSTRUCTION & _zz_374) == 32'h00002010); - assign _zz_362 = (_zz_375 == _zz_376); - assign _zz_363 = {_zz_377,_zz_378}; - assign _zz_364 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_365 = 32'h00000020; - assign _zz_366 = ((decode_INSTRUCTION & _zz_379) == 32'h0); - assign _zz_367 = (_zz_380 == _zz_381); - assign _zz_368 = (_zz_382 == _zz_383); - assign _zz_369 = (_zz_384 == _zz_385); - assign _zz_370 = 1'b0; - assign _zz_371 = ({_zz_386,_zz_387} != 4'b0000); - assign _zz_372 = (_zz_388 != _zz_389); - assign _zz_373 = {_zz_390,{_zz_391,_zz_392}}; - assign _zz_374 = 32'h00002010; - assign _zz_375 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_376 = 32'h00000010; - assign _zz_377 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_378 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); - assign _zz_379 = 32'h00000020; - assign _zz_380 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_381 = 32'h00006010; - assign _zz_382 = (decode_INSTRUCTION & 32'h00005014); - assign _zz_383 = 32'h00004010; - assign _zz_384 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_385 = 32'h00002010; - assign _zz_386 = ((decode_INSTRUCTION & _zz_393) == 32'h0); - assign _zz_387 = {(_zz_394 == _zz_395),{_zz_396,_zz_397}}; - assign _zz_388 = ((decode_INSTRUCTION & _zz_398) == 32'h0); - assign _zz_389 = 1'b0; - assign _zz_390 = ({_zz_399,{_zz_400,_zz_401}} != 3'b000); - assign _zz_391 = ({_zz_402,_zz_403} != 2'b00); - assign _zz_392 = ({_zz_404,_zz_405} != 2'b00); - assign _zz_393 = 32'h00000044; - assign _zz_394 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_395 = 32'h0; - assign _zz_396 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_397 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_398 = 32'h00000058; - assign _zz_399 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_400 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_401 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz_402 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_403 = _zz_73; - assign _zz_404 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_405 = _zz_73; + assign _zz_191 = execute_SRC_LESS; + assign _zz_192 = 3'b100; + assign _zz_193 = execute_INSTRUCTION[19 : 15]; + assign _zz_194 = execute_INSTRUCTION[31 : 20]; + assign _zz_195 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_196 = ($signed(_zz_197) + $signed(_zz_200)); + assign _zz_197 = ($signed(_zz_198) + $signed(_zz_199)); + assign _zz_198 = execute_SRC1; + assign _zz_199 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_200 = (execute_SRC_USE_SUB_LESS ? _zz_201 : _zz_202); + assign _zz_201 = 32'h00000001; + assign _zz_202 = 32'h0; + assign _zz_203 = (_zz_204 >>> 1); + assign _zz_204 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_205 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_206 = execute_INSTRUCTION[31 : 20]; + assign _zz_207 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_208 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_209 = {5'd0, _zz_208}; + assign _zz_210 = (_zz_212 + _zz_214); + assign _zz_211 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_212 = {{1{_zz_211[32]}}, _zz_211}; + assign _zz_213 = _zz_215; + assign _zz_214 = {{1{_zz_213[32]}}, _zz_213}; + assign _zz_215 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_216 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_217 = {5'd0, _zz_216}; + assign _zz_218 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_219 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_220 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_221 = {_zz_113,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_222 = _zz_223; + assign _zz_223 = _zz_224; + assign _zz_224 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_114) : _zz_114)} + _zz_226); + assign _zz_225 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_226 = {32'd0, _zz_225}; + assign _zz_227 = _zz_116; + assign _zz_228 = {32'd0, _zz_227}; + assign _zz_229 = _zz_115; + assign _zz_230 = {31'd0, _zz_229}; + assign _zz_231 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_232 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_233 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_234 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_235 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_236 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_237 = 1'b1; + assign _zz_238 = 1'b1; + assign _zz_239 = {_zz_53,_zz_52}; + assign _zz_240 = 32'h02004064; + assign _zz_241 = _zz_79; + assign _zz_242 = {_zz_77,_zz_78}; + assign _zz_243 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_244 = 1'b0; + assign _zz_245 = (((decode_INSTRUCTION & _zz_248) == 32'h00000050) != 1'b0); + assign _zz_246 = ((_zz_249 == _zz_250) != 1'b0); + assign _zz_247 = {({_zz_251,_zz_252} != 2'b00),{(_zz_253 != _zz_254),{_zz_255,{_zz_256,_zz_257}}}}; + assign _zz_248 = 32'h10003050; + assign _zz_249 = (decode_INSTRUCTION & 32'h10403050); + assign _zz_250 = 32'h10000050; + assign _zz_251 = ((decode_INSTRUCTION & _zz_258) == 32'h00001050); + assign _zz_252 = ((decode_INSTRUCTION & _zz_259) == 32'h00002050); + assign _zz_253 = {_zz_76,(_zz_260 == _zz_261)}; + assign _zz_254 = 2'b00; + assign _zz_255 = ((_zz_262 == _zz_263) != 1'b0); + assign _zz_256 = ({_zz_264,_zz_265} != 2'b00); + assign _zz_257 = {(_zz_266 != _zz_267),{_zz_268,{_zz_269,_zz_270}}}; + assign _zz_258 = 32'h00001050; + assign _zz_259 = 32'h00002050; + assign _zz_260 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_261 = 32'h00000004; + assign _zz_262 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_263 = 32'h00000040; + assign _zz_264 = ((decode_INSTRUCTION & _zz_271) == 32'h00000040); + assign _zz_265 = ((decode_INSTRUCTION & _zz_272) == 32'h00000040); + assign _zz_266 = {(_zz_273 == _zz_274),(_zz_275 == _zz_276)}; + assign _zz_267 = 2'b00; + assign _zz_268 = ({_zz_277,{_zz_278,_zz_279}} != 3'b000); + assign _zz_269 = ({_zz_280,_zz_281} != 3'b000); + assign _zz_270 = {(_zz_282 != _zz_283),{_zz_284,{_zz_285,_zz_286}}}; + assign _zz_271 = 32'h00000050; + assign _zz_272 = 32'h00403040; + assign _zz_273 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_274 = 32'h00005010; + assign _zz_275 = (decode_INSTRUCTION & 32'h02007064); + assign _zz_276 = 32'h00005020; + assign _zz_277 = ((decode_INSTRUCTION & _zz_287) == 32'h40001010); + assign _zz_278 = (_zz_288 == _zz_289); + assign _zz_279 = (_zz_290 == _zz_291); + assign _zz_280 = (_zz_292 == _zz_293); + assign _zz_281 = {_zz_294,_zz_295}; + assign _zz_282 = (_zz_296 == _zz_297); + assign _zz_283 = 1'b0; + assign _zz_284 = (_zz_77 != 1'b0); + assign _zz_285 = (_zz_298 != _zz_299); + assign _zz_286 = {_zz_300,{_zz_301,_zz_302}}; + assign _zz_287 = 32'h40003054; + assign _zz_288 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_289 = 32'h00001010; + assign _zz_290 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_291 = 32'h00001010; + assign _zz_292 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_293 = 32'h00000024; + assign _zz_294 = ((decode_INSTRUCTION & 32'h00003034) == 32'h00001010); + assign _zz_295 = ((decode_INSTRUCTION & 32'h02003054) == 32'h00001010); + assign _zz_296 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_297 = 32'h00001000; + assign _zz_298 = {(_zz_303 == _zz_304),(_zz_305 == _zz_306)}; + assign _zz_299 = 2'b00; + assign _zz_300 = ({_zz_307,_zz_308} != 2'b00); + assign _zz_301 = (_zz_74 != 1'b0); + assign _zz_302 = {(_zz_309 != _zz_310),{_zz_311,{_zz_312,_zz_313}}}; + assign _zz_303 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_304 = 32'h00002000; + assign _zz_305 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_306 = 32'h00001000; + assign _zz_307 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00006000); + assign _zz_308 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00004000); + assign _zz_309 = {(_zz_314 == _zz_315),(_zz_316 == _zz_317)}; + assign _zz_310 = 2'b00; + assign _zz_311 = ((_zz_318 == _zz_319) != 1'b0); + assign _zz_312 = (_zz_320 != 1'b0); + assign _zz_313 = {(_zz_321 != _zz_322),{_zz_323,{_zz_324,_zz_325}}}; + assign _zz_314 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_315 = 32'h00000020; + assign _zz_316 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_317 = 32'h00000020; + assign _zz_318 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_319 = 32'h00000020; + assign _zz_320 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); + assign _zz_321 = {_zz_75,{_zz_326,_zz_327}}; + assign _zz_322 = 3'b000; + assign _zz_323 = ({_zz_76,{_zz_328,_zz_329}} != 6'h0); + assign _zz_324 = ({_zz_330,_zz_331} != 2'b00); + assign _zz_325 = {(_zz_332 != _zz_333),{_zz_334,{_zz_335,_zz_336}}}; + assign _zz_326 = ((decode_INSTRUCTION & _zz_337) == 32'h00000010); + assign _zz_327 = ((decode_INSTRUCTION & _zz_338) == 32'h00000020); + assign _zz_328 = (_zz_339 == _zz_340); + assign _zz_329 = {_zz_341,{_zz_342,_zz_343}}; + assign _zz_330 = _zz_75; + assign _zz_331 = (_zz_344 == _zz_345); + assign _zz_332 = {_zz_75,_zz_346}; + assign _zz_333 = 2'b00; + assign _zz_334 = ({_zz_347,_zz_348} != 4'b0000); + assign _zz_335 = (_zz_349 != _zz_350); + assign _zz_336 = {_zz_351,{_zz_352,_zz_353}}; + assign _zz_337 = 32'h00000030; + assign _zz_338 = 32'h02000060; + assign _zz_339 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_340 = 32'h00001010; + assign _zz_341 = ((decode_INSTRUCTION & _zz_354) == 32'h00002010); + assign _zz_342 = (_zz_355 == _zz_356); + assign _zz_343 = {_zz_357,_zz_358}; + assign _zz_344 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_345 = 32'h00000020; + assign _zz_346 = ((decode_INSTRUCTION & _zz_359) == 32'h0); + assign _zz_347 = (_zz_360 == _zz_361); + assign _zz_348 = {_zz_362,{_zz_363,_zz_364}}; + assign _zz_349 = (_zz_365 == _zz_366); + assign _zz_350 = 1'b0; + assign _zz_351 = ({_zz_367,_zz_368} != 3'b000); + assign _zz_352 = (_zz_369 != _zz_370); + assign _zz_353 = (_zz_371 != _zz_372); + assign _zz_354 = 32'h00002010; + assign _zz_355 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_356 = 32'h00000010; + assign _zz_357 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_358 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz_359 = 32'h00000020; + assign _zz_360 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_361 = 32'h0; + assign _zz_362 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz_363 = _zz_74; + assign _zz_364 = ((decode_INSTRUCTION & _zz_373) == 32'h00001000); + assign _zz_365 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_366 = 32'h0; + assign _zz_367 = ((decode_INSTRUCTION & _zz_374) == 32'h00000040); + assign _zz_368 = {(_zz_375 == _zz_376),(_zz_377 == _zz_378)}; + assign _zz_369 = {(_zz_379 == _zz_380),_zz_73}; + assign _zz_370 = 2'b00; + assign _zz_371 = {(_zz_381 == _zz_382),_zz_73}; + assign _zz_372 = 2'b00; + assign _zz_373 = 32'h00005004; + assign _zz_374 = 32'h00000044; + assign _zz_375 = (decode_INSTRUCTION & 32'h00002014); + assign _zz_376 = 32'h00002010; + assign _zz_377 = (decode_INSTRUCTION & 32'h40004034); + assign _zz_378 = 32'h40000030; + assign _zz_379 = (decode_INSTRUCTION & 32'h00000014); + assign _zz_380 = 32'h00000004; + assign _zz_381 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_382 = 32'h00000004; always @ (posedge clk) begin - if(_zz_248) begin - _zz_136 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_237) begin + _zz_133 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_249) begin - _zz_137 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_238) begin + _zz_134 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1382,24 +1330,24 @@ module VexRiscv ( .io_push_payload_error (iBus_rsp_payload_error ), //i .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o - .io_pop_ready (_zz_134 ), //i + .io_pop_ready (_zz_131 ), //i .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o - .io_flush (_zz_135 ), //i + .io_flush (_zz_132 ), //i .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o .clk (clk ), //i .reset (reset ) //i ); always @(*) begin - case(_zz_250) + case(_zz_239) 2'b00 : begin - _zz_138 = CsrPlugin_jumpInterface_payload; + _zz_135 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_138 = DBusSimplePlugin_redoBranch_payload; + _zz_135 = DBusSimplePlugin_redoBranch_payload; end default : begin - _zz_138 = BranchPlugin_jumpInterface_payload; + _zz_135 = BranchPlugin_jumpInterface_payload; end endcase end @@ -1574,71 +1522,71 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(_zz_17) - `Src2CtrlEnum_defaultEncoding_RS : _zz_17_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_17_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_17_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_17_string = "PC "; - default : _zz_17_string = "???"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17_string = "BITWISE "; + default : _zz_17_string = "????????"; endcase end always @(*) begin case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18_string = "BITWISE "; + default : _zz_18_string = "????????"; endcase end always @(*) begin case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19_string = "BITWISE "; + default : _zz_19_string = "????????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(_zz_20) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; - default : _zz_20_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; endcase end always @(*) begin case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; endcase end always @(*) begin case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; endcase end always @(*) begin @@ -1865,19 +1813,19 @@ module VexRiscv ( end always @(*) begin case(_zz_45) - `Src2CtrlEnum_defaultEncoding_RS : _zz_45_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_45_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_45_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_45_string = "PC "; - default : _zz_45_string = "???"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; + default : _zz_45_string = "????????"; endcase end always @(*) begin case(_zz_46) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_46_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_46_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_46_string = "BITWISE "; - default : _zz_46_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_46_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_46_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_46_string = "PC "; + default : _zz_46_string = "???"; endcase end always @(*) begin @@ -1889,21 +1837,13 @@ module VexRiscv ( default : _zz_47_string = "????????????"; endcase end - always @(*) begin - case(_zz_79) - `Src1CtrlEnum_defaultEncoding_RS : _zz_79_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_79_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_79_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_79_string = "URS1 "; - default : _zz_79_string = "????????????"; - endcase - end always @(*) begin case(_zz_80) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_80_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_80_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_80_string = "BITWISE "; - default : _zz_80_string = "????????"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_80_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_80_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_80_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_80_string = "URS1 "; + default : _zz_80_string = "????????????"; endcase end always @(*) begin @@ -1917,36 +1857,44 @@ module VexRiscv ( end always @(*) begin case(_zz_82) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_82_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_82_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_82_string = "AND_1"; - default : _zz_82_string = "?????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_82_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_82_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_82_string = "BITWISE "; + default : _zz_82_string = "????????"; endcase end always @(*) begin case(_zz_83) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_83_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_83_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_83_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_83_string = "SRA_1 "; - default : _zz_83_string = "?????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_83_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_83_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_83_string = "AND_1"; + default : _zz_83_string = "?????"; endcase end always @(*) begin case(_zz_84) - `BranchCtrlEnum_defaultEncoding_INC : _zz_84_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_84_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_84_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_84_string = "JALR"; - default : _zz_84_string = "????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_84_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_84_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_84_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_84_string = "SRA_1 "; + default : _zz_84_string = "?????????"; endcase end always @(*) begin case(_zz_85) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_85_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_85_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_85_string = "ECALL"; - default : _zz_85_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_85_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_85_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_85_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_85_string = "JALR"; + default : _zz_85_string = "????"; + endcase + end + always @(*) begin + case(_zz_86) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_86_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_86_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_86_string = "ECALL"; + default : _zz_86_string = "?????"; endcase end always @(*) begin @@ -1958,14 +1906,6 @@ module VexRiscv ( default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end always @(*) begin case(decode_to_execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; @@ -1975,6 +1915,14 @@ module VexRiscv ( default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; @@ -2029,9 +1977,9 @@ module VexRiscv ( assign memory_MEMORY_READ_DATA = dBus_rsp_data; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_101; + assign execute_BRANCH_DO = _zz_102; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_87; + assign execute_REGFILE_WRITE_DATA = _zz_88; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); @@ -2039,29 +1987,29 @@ module VexRiscv ( assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign decode_IS_DIV = _zz_170[0]; - assign decode_IS_RS2_SIGNED = _zz_171[0]; - assign decode_IS_RS1_SIGNED = _zz_172[0]; - assign decode_IS_MUL = _zz_173[0]; + assign decode_IS_DIV = _zz_164[0]; + assign decode_IS_RS2_SIGNED = _zz_165[0]; + assign decode_IS_RS1_SIGNED = _zz_166[0]; + assign decode_IS_MUL = _zz_167[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_174[0]; + assign decode_IS_CSR = _zz_168[0]; assign decode_BRANCH_CTRL = _zz_8; assign _zz_9 = _zz_10; assign decode_SHIFT_CTRL = _zz_11; assign _zz_12 = _zz_13; assign decode_ALU_BITWISE_CTRL = _zz_14; assign _zz_15 = _zz_16; - assign decode_SRC_LESS_UNSIGNED = _zz_175[0]; - assign decode_MEMORY_STORE = _zz_176[0]; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_177[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_178[0]; - assign decode_SRC2_CTRL = _zz_17; + assign decode_SRC_LESS_UNSIGNED = _zz_169[0]; + assign decode_ALU_CTRL = _zz_17; assign _zz_18 = _zz_19; - assign decode_ALU_CTRL = _zz_20; + assign decode_MEMORY_STORE = _zz_170[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_171[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_172[0]; + assign decode_SRC2_CTRL = _zz_20; assign _zz_21 = _zz_22; assign decode_SRC1_CTRL = _zz_23; assign _zz_24 = _zz_25; @@ -2076,10 +2024,10 @@ module VexRiscv ( assign memory_IS_DIV = execute_to_memory_IS_DIV; always @ (*) begin _zz_26 = memory_REGFILE_WRITE_DATA; - if(_zz_139)begin + if(_zz_136)begin _zz_26 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_140)begin + if(_zz_137)begin _zz_26 = memory_MulDivIterativePlugin_div_result; end end @@ -2096,8 +2044,8 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_179[0]; - assign decode_RS1_USE = _zz_180[0]; + assign decode_RS2_USE = _zz_173[0]; + assign decode_RS1_USE = _zz_174[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; @@ -2106,10 +2054,10 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_141)begin - _zz_31 = _zz_94; + if(_zz_138)begin + _zz_31 = _zz_95; end - if(_zz_142)begin + if(_zz_139)begin _zz_31 = execute_CsrPlugin_readData; end end @@ -2121,13 +2069,13 @@ module VexRiscv ( assign _zz_33 = execute_PC; assign execute_SRC2_CTRL = _zz_34; assign execute_SRC1_CTRL = _zz_35; - assign decode_SRC_USE_SUB_LESS = _zz_181[0]; - assign decode_SRC_ADD_ZERO = _zz_182[0]; + assign decode_SRC_USE_SUB_LESS = _zz_175[0]; + assign decode_SRC_ADD_ZERO = _zz_176[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_36; - assign execute_SRC2 = _zz_93; - assign execute_SRC1 = _zz_88; + assign execute_SRC2 = _zz_94; + assign execute_SRC1 = _zz_89; assign execute_ALU_BITWISE_CTRL = _zz_37; assign _zz_38 = writeBack_INSTRUCTION; assign _zz_39 = writeBack_REGFILE_WRITE_VALID; @@ -2140,13 +2088,12 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_183[0]; + decode_REGFILE_WRITE_VALID = _zz_177[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_251) == 32'h00001073),{(_zz_252 == _zz_253),{_zz_254,{_zz_255,_zz_256}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin _zz_48 = writeBack_REGFILE_WRITE_DATA; @@ -2169,7 +2116,6 @@ module VexRiscv ( assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; assign memory_PC = execute_to_memory_PC; - assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; @@ -2188,8 +2134,8 @@ module VexRiscv ( assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_184[0]; + assign execute_ALIGNEMENT_FAULT = 1'b0; + assign decode_MEMORY_ENABLE = _zz_178[0]; always @ (*) begin _zz_49 = memory_FORMAL_PC_NEXT; if(DBusSimplePlugin_redoBranch_valid)begin @@ -2213,7 +2159,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_95 || _zz_96)))begin + if((decode_arbitration_isValid && (_zz_96 || _zz_97)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2226,7 +2172,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_143)begin + if(IBusSimplePlugin_decodeExceptionPort_valid)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2237,7 +2183,7 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(_zz_143)begin + if(IBusSimplePlugin_decodeExceptionPort_valid)begin decode_arbitration_flushNext = 1'b1; end end @@ -2247,12 +2193,12 @@ module VexRiscv ( if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_65)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_141)begin + if(_zz_138)begin if((! execute_LightShifterPlugin_done))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_142)begin + if(_zz_139)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2283,15 +2229,15 @@ module VexRiscv ( if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_139)begin + if(_zz_136)begin if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_144)begin + if(_zz_140)begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_140)begin + if(_zz_137)begin if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2301,7 +2247,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_145)begin + if(DBusSimplePlugin_memoryExceptionPort_valid)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2324,7 +2270,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_145)begin + if(DBusSimplePlugin_memoryExceptionPort_valid)begin memory_arbitration_flushNext = 1'b1; end end @@ -2341,10 +2287,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_146)begin + if(_zz_141)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_147)begin + if(_zz_142)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2358,10 +2304,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_146)begin + if(_zz_141)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_147)begin + if(_zz_142)begin IBusSimplePlugin_fetcherHalt = 1'b1; end end @@ -2380,21 +2326,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_146)begin + if(_zz_141)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_147)begin + if(_zz_142)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_146)begin + if(_zz_141)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_147)begin - case(_zz_148) + if(_zz_142)begin + case(_zz_162) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2410,10 +2356,10 @@ module VexRiscv ( assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); assign _zz_50 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_51 = (_zz_50 & (~ _zz_185)); + assign _zz_51 = (_zz_50 & (~ _zz_179)); assign _zz_52 = _zz_51[1]; assign _zz_53 = _zz_51[2]; - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_138; + assign IBusSimplePlugin_jump_pcLoad_payload = _zz_135; always @ (*) begin IBusSimplePlugin_fetchPc_correction = 1'b0; if(IBusSimplePlugin_fetchPc_redo_valid)begin @@ -2433,7 +2379,7 @@ module VexRiscv ( end always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_187); + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_181); if(IBusSimplePlugin_fetchPc_redo_valid)begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; end @@ -2523,7 +2469,7 @@ module VexRiscv ( assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pending_next = (_zz_188 - _zz_192); + assign IBusSimplePlugin_pending_next = (_zz_182 - _zz_186); assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); always @ (*) begin IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); @@ -2547,8 +2493,8 @@ module VexRiscv ( assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - assign _zz_134 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); - assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_134); + assign _zz_131 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_131); assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; always @ (*) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; @@ -2560,7 +2506,7 @@ module VexRiscv ( assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; always @ (*) begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_149)begin + if(_zz_143)begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; end end @@ -2581,7 +2527,7 @@ module VexRiscv ( assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; always @ (*) begin IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_149)begin + if(_zz_143)begin IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; end end @@ -2640,12 +2586,6 @@ module VexRiscv ( assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_150)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end else begin @@ -2653,19 +2593,13 @@ module VexRiscv ( DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_151)begin + if(_zz_144)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_150)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; - end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_197}; - end if(! memory_MMU_RSP2_refilling) begin if(memory_MMU_FAULT)begin DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); @@ -2679,7 +2613,7 @@ module VexRiscv ( if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_151)begin + if(_zz_144)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -2753,7 +2687,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_168) + case(_zz_161) 2'b00 : begin writeBack_DBusSimplePlugin_rspFormated = _zz_69; end @@ -2785,50 +2719,48 @@ module VexRiscv ( assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; assign _zz_73 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_74 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_75 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_76 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_77 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); - assign _zz_78 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); - assign _zz_72 = {(((decode_INSTRUCTION & _zz_269) == 32'h02004020) != 1'b0),{({_zz_78,_zz_77} != 2'b00),{({_zz_270,_zz_271} != 3'b000),{(_zz_272 != _zz_273),{_zz_274,{_zz_275,_zz_276}}}}}}; - assign _zz_79 = _zz_72[1 : 0]; - assign _zz_47 = _zz_79; - assign _zz_80 = _zz_72[6 : 5]; - assign _zz_46 = _zz_80; - assign _zz_81 = _zz_72[8 : 7]; - assign _zz_45 = _zz_81; - assign _zz_82 = _zz_72[17 : 16]; - assign _zz_44 = _zz_82; - assign _zz_83 = _zz_72[20 : 19]; - assign _zz_43 = _zz_83; - assign _zz_84 = _zz_72[22 : 21]; - assign _zz_42 = _zz_84; - assign _zz_85 = _zz_72[25 : 24]; - assign _zz_41 = _zz_85; - assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = 4'b0010; - assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign _zz_74 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_75 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_76 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_77 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_78 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); + assign _zz_79 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); + assign _zz_72 = {(((decode_INSTRUCTION & _zz_240) == 32'h02004020) != 1'b0),{({_zz_79,_zz_78} != 2'b00),{({_zz_241,_zz_242} != 3'b000),{(_zz_243 != _zz_244),{_zz_245,{_zz_246,_zz_247}}}}}}; + assign _zz_80 = _zz_72[1 : 0]; + assign _zz_47 = _zz_80; + assign _zz_81 = _zz_72[6 : 5]; + assign _zz_46 = _zz_81; + assign _zz_82 = _zz_72[13 : 12]; + assign _zz_45 = _zz_82; + assign _zz_83 = _zz_72[16 : 15]; + assign _zz_44 = _zz_83; + assign _zz_84 = _zz_72[19 : 18]; + assign _zz_43 = _zz_84; + assign _zz_85 = _zz_72[22 : 21]; + assign _zz_42 = _zz_85; + assign _zz_86 = _zz_72[25 : 24]; + assign _zz_41 = _zz_86; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_136; - assign decode_RegFilePlugin_rs2Data = _zz_137; + assign decode_RegFilePlugin_rs1Data = _zz_133; + assign decode_RegFilePlugin_rs2Data = _zz_134; always @ (*) begin lastStageRegFileWrite_valid = (_zz_39 && writeBack_arbitration_isFiring); - if(_zz_86)begin + if(_zz_87)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin lastStageRegFileWrite_payload_address = _zz_38[11 : 7]; - if(_zz_86)begin + if(_zz_87)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin lastStageRegFileWrite_payload_data = _zz_48; - if(_zz_86)begin + if(_zz_87)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -2850,13 +2782,13 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_87 = execute_IntAluPlugin_bitwise; + _zz_88 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_87 = {31'd0, _zz_198}; + _zz_88 = {31'd0, _zz_191}; end default : begin - _zz_87 = execute_SRC_ADD_SUB; + _zz_88 = execute_SRC_ADD_SUB; end endcase end @@ -2864,87 +2796,87 @@ module VexRiscv ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_88 = execute_RS1; + _zz_89 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_88 = {29'd0, _zz_199}; + _zz_89 = {29'd0, _zz_192}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_88 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_89 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_88 = {27'd0, _zz_200}; + _zz_89 = {27'd0, _zz_193}; end endcase end - assign _zz_89 = _zz_201[11]; + assign _zz_90 = _zz_194[11]; always @ (*) begin - _zz_90[19] = _zz_89; - _zz_90[18] = _zz_89; - _zz_90[17] = _zz_89; - _zz_90[16] = _zz_89; - _zz_90[15] = _zz_89; - _zz_90[14] = _zz_89; - _zz_90[13] = _zz_89; - _zz_90[12] = _zz_89; - _zz_90[11] = _zz_89; - _zz_90[10] = _zz_89; - _zz_90[9] = _zz_89; - _zz_90[8] = _zz_89; - _zz_90[7] = _zz_89; - _zz_90[6] = _zz_89; - _zz_90[5] = _zz_89; - _zz_90[4] = _zz_89; - _zz_90[3] = _zz_89; - _zz_90[2] = _zz_89; - _zz_90[1] = _zz_89; - _zz_90[0] = _zz_89; - end - - assign _zz_91 = _zz_202[11]; + _zz_91[19] = _zz_90; + _zz_91[18] = _zz_90; + _zz_91[17] = _zz_90; + _zz_91[16] = _zz_90; + _zz_91[15] = _zz_90; + _zz_91[14] = _zz_90; + _zz_91[13] = _zz_90; + _zz_91[12] = _zz_90; + _zz_91[11] = _zz_90; + _zz_91[10] = _zz_90; + _zz_91[9] = _zz_90; + _zz_91[8] = _zz_90; + _zz_91[7] = _zz_90; + _zz_91[6] = _zz_90; + _zz_91[5] = _zz_90; + _zz_91[4] = _zz_90; + _zz_91[3] = _zz_90; + _zz_91[2] = _zz_90; + _zz_91[1] = _zz_90; + _zz_91[0] = _zz_90; + end + + assign _zz_92 = _zz_195[11]; always @ (*) begin - _zz_92[19] = _zz_91; - _zz_92[18] = _zz_91; - _zz_92[17] = _zz_91; - _zz_92[16] = _zz_91; - _zz_92[15] = _zz_91; - _zz_92[14] = _zz_91; - _zz_92[13] = _zz_91; - _zz_92[12] = _zz_91; - _zz_92[11] = _zz_91; - _zz_92[10] = _zz_91; - _zz_92[9] = _zz_91; - _zz_92[8] = _zz_91; - _zz_92[7] = _zz_91; - _zz_92[6] = _zz_91; - _zz_92[5] = _zz_91; - _zz_92[4] = _zz_91; - _zz_92[3] = _zz_91; - _zz_92[2] = _zz_91; - _zz_92[1] = _zz_91; - _zz_92[0] = _zz_91; + _zz_93[19] = _zz_92; + _zz_93[18] = _zz_92; + _zz_93[17] = _zz_92; + _zz_93[16] = _zz_92; + _zz_93[15] = _zz_92; + _zz_93[14] = _zz_92; + _zz_93[13] = _zz_92; + _zz_93[12] = _zz_92; + _zz_93[11] = _zz_92; + _zz_93[10] = _zz_92; + _zz_93[9] = _zz_92; + _zz_93[8] = _zz_92; + _zz_93[7] = _zz_92; + _zz_93[6] = _zz_92; + _zz_93[5] = _zz_92; + _zz_93[4] = _zz_92; + _zz_93[3] = _zz_92; + _zz_93[2] = _zz_92; + _zz_93[1] = _zz_92; + _zz_93[0] = _zz_92; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_93 = execute_RS2; + _zz_94 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_93 = {_zz_90,execute_INSTRUCTION[31 : 20]}; + _zz_94 = {_zz_91,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_93 = {_zz_92,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_94 = {_zz_93,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_93 = _zz_33; + _zz_94 = _zz_33; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_203; + execute_SrcPlugin_addSub = _zz_196; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -2958,195 +2890,192 @@ module VexRiscv ( always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_94 = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_95 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_94 = _zz_210; + _zz_95 = _zz_203; end endcase end always @ (*) begin - _zz_95 = 1'b0; - if(_zz_97)begin - if((_zz_98 == decode_INSTRUCTION[19 : 15]))begin - _zz_95 = 1'b1; + _zz_96 = 1'b0; + if(_zz_98)begin + if((_zz_99 == decode_INSTRUCTION[19 : 15]))begin + _zz_96 = 1'b1; end end - if(_zz_152)begin - if(_zz_153)begin + if(_zz_145)begin + if(_zz_146)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_95 = 1'b1; + _zz_96 = 1'b1; end end end - if(_zz_154)begin - if(_zz_155)begin + if(_zz_147)begin + if(_zz_148)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_95 = 1'b1; + _zz_96 = 1'b1; end end end - if(_zz_156)begin - if(_zz_157)begin + if(_zz_149)begin + if(_zz_150)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_95 = 1'b1; + _zz_96 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_95 = 1'b0; + _zz_96 = 1'b0; end end always @ (*) begin - _zz_96 = 1'b0; - if(_zz_97)begin - if((_zz_98 == decode_INSTRUCTION[24 : 20]))begin - _zz_96 = 1'b1; + _zz_97 = 1'b0; + if(_zz_98)begin + if((_zz_99 == decode_INSTRUCTION[24 : 20]))begin + _zz_97 = 1'b1; end end - if(_zz_152)begin - if(_zz_153)begin + if(_zz_145)begin + if(_zz_146)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_96 = 1'b1; + _zz_97 = 1'b1; end end end - if(_zz_154)begin - if(_zz_155)begin + if(_zz_147)begin + if(_zz_148)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_96 = 1'b1; + _zz_97 = 1'b1; end end end - if(_zz_156)begin - if(_zz_157)begin + if(_zz_149)begin + if(_zz_150)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_96 = 1'b1; + _zz_97 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_96 = 1'b0; + _zz_97 = 1'b0; end end assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_99 = execute_INSTRUCTION[14 : 12]; + assign _zz_100 = execute_INSTRUCTION[14 : 12]; always @ (*) begin - if((_zz_99 == 3'b000)) begin - _zz_100 = execute_BranchPlugin_eq; - end else if((_zz_99 == 3'b001)) begin - _zz_100 = (! execute_BranchPlugin_eq); - end else if((((_zz_99 & 3'b101) == 3'b101))) begin - _zz_100 = (! execute_SRC_LESS); + if((_zz_100 == 3'b000)) begin + _zz_101 = execute_BranchPlugin_eq; + end else if((_zz_100 == 3'b001)) begin + _zz_101 = (! execute_BranchPlugin_eq); + end else if((((_zz_100 & 3'b101) == 3'b101))) begin + _zz_101 = (! execute_SRC_LESS); end else begin - _zz_100 = execute_SRC_LESS; + _zz_101 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_101 = 1'b0; + _zz_102 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_101 = 1'b1; + _zz_102 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_101 = 1'b1; + _zz_102 = 1'b1; end default : begin - _zz_101 = _zz_100; + _zz_102 = _zz_101; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_102 = _zz_212[19]; + assign _zz_103 = _zz_205[19]; always @ (*) begin - _zz_103[10] = _zz_102; - _zz_103[9] = _zz_102; - _zz_103[8] = _zz_102; - _zz_103[7] = _zz_102; - _zz_103[6] = _zz_102; - _zz_103[5] = _zz_102; - _zz_103[4] = _zz_102; - _zz_103[3] = _zz_102; - _zz_103[2] = _zz_102; - _zz_103[1] = _zz_102; - _zz_103[0] = _zz_102; - end - - assign _zz_104 = _zz_213[11]; + _zz_104[10] = _zz_103; + _zz_104[9] = _zz_103; + _zz_104[8] = _zz_103; + _zz_104[7] = _zz_103; + _zz_104[6] = _zz_103; + _zz_104[5] = _zz_103; + _zz_104[4] = _zz_103; + _zz_104[3] = _zz_103; + _zz_104[2] = _zz_103; + _zz_104[1] = _zz_103; + _zz_104[0] = _zz_103; + end + + assign _zz_105 = _zz_206[11]; always @ (*) begin - _zz_105[19] = _zz_104; - _zz_105[18] = _zz_104; - _zz_105[17] = _zz_104; - _zz_105[16] = _zz_104; - _zz_105[15] = _zz_104; - _zz_105[14] = _zz_104; - _zz_105[13] = _zz_104; - _zz_105[12] = _zz_104; - _zz_105[11] = _zz_104; - _zz_105[10] = _zz_104; - _zz_105[9] = _zz_104; - _zz_105[8] = _zz_104; - _zz_105[7] = _zz_104; - _zz_105[6] = _zz_104; - _zz_105[5] = _zz_104; - _zz_105[4] = _zz_104; - _zz_105[3] = _zz_104; - _zz_105[2] = _zz_104; - _zz_105[1] = _zz_104; - _zz_105[0] = _zz_104; - end - - assign _zz_106 = _zz_214[11]; + _zz_106[19] = _zz_105; + _zz_106[18] = _zz_105; + _zz_106[17] = _zz_105; + _zz_106[16] = _zz_105; + _zz_106[15] = _zz_105; + _zz_106[14] = _zz_105; + _zz_106[13] = _zz_105; + _zz_106[12] = _zz_105; + _zz_106[11] = _zz_105; + _zz_106[10] = _zz_105; + _zz_106[9] = _zz_105; + _zz_106[8] = _zz_105; + _zz_106[7] = _zz_105; + _zz_106[6] = _zz_105; + _zz_106[5] = _zz_105; + _zz_106[4] = _zz_105; + _zz_106[3] = _zz_105; + _zz_106[2] = _zz_105; + _zz_106[1] = _zz_105; + _zz_106[0] = _zz_105; + end + + assign _zz_107 = _zz_207[11]; always @ (*) begin - _zz_107[18] = _zz_106; - _zz_107[17] = _zz_106; - _zz_107[16] = _zz_106; - _zz_107[15] = _zz_106; - _zz_107[14] = _zz_106; - _zz_107[13] = _zz_106; - _zz_107[12] = _zz_106; - _zz_107[11] = _zz_106; - _zz_107[10] = _zz_106; - _zz_107[9] = _zz_106; - _zz_107[8] = _zz_106; - _zz_107[7] = _zz_106; - _zz_107[6] = _zz_106; - _zz_107[5] = _zz_106; - _zz_107[4] = _zz_106; - _zz_107[3] = _zz_106; - _zz_107[2] = _zz_106; - _zz_107[1] = _zz_106; - _zz_107[0] = _zz_106; + _zz_108[18] = _zz_107; + _zz_108[17] = _zz_107; + _zz_108[16] = _zz_107; + _zz_108[15] = _zz_107; + _zz_108[14] = _zz_107; + _zz_108[13] = _zz_107; + _zz_108[12] = _zz_107; + _zz_108[11] = _zz_107; + _zz_108[10] = _zz_107; + _zz_108[9] = _zz_107; + _zz_108[8] = _zz_107; + _zz_108[7] = _zz_107; + _zz_108[6] = _zz_107; + _zz_108[5] = _zz_107; + _zz_108[4] = _zz_107; + _zz_108[3] = _zz_107; + _zz_108[2] = _zz_107; + _zz_108[1] = _zz_107; + _zz_108[0] = _zz_107; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_108 = {{_zz_103,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_109 = {{_zz_104,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_108 = {_zz_105,execute_INSTRUCTION[31 : 20]}; + _zz_109 = {_zz_106,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_108 = {{_zz_107,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_109 = {{_zz_108,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_108; + assign execute_BranchPlugin_branch_src2 = _zz_109; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; - assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); - assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; - assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; always @ (*) begin CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin @@ -3156,18 +3085,14 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_109 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_110 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_111 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_110 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_111 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_112 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_112 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; - assign _zz_113 = _zz_215[0]; - assign _zz_114 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_115 = _zz_217[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_143)begin + if(IBusSimplePlugin_decodeExceptionPort_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3187,7 +3112,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_145)begin + if(DBusSimplePlugin_memoryExceptionPort_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3305,7 +3230,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_158)begin + if(_zz_151)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3324,14 +3249,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_159)begin + if(_zz_152)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_159)begin + if(_zz_152)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3346,14 +3271,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_158)begin + if(_zz_151)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_158)begin + if(_zz_151)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -3362,7 +3287,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_169) + case(_zz_163) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3376,8 +3301,8 @@ module VexRiscv ( assign memory_MulDivIterativePlugin_frontendOk = 1'b1; always @ (*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_139)begin - if(_zz_144)begin + if(_zz_136)begin + if(_zz_140)begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end @@ -3396,7 +3321,7 @@ module VexRiscv ( if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_220); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_209); end if(memory_MulDivIterativePlugin_mul_counter_willClear)begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; @@ -3405,8 +3330,8 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_140)begin - if(_zz_160)begin + if(_zz_137)begin + if(_zz_153)begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end @@ -3414,7 +3339,7 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_161)begin + if(_zz_154)begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end @@ -3425,37 +3350,37 @@ module VexRiscv ( if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_228); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_217); end if(memory_MulDivIterativePlugin_div_counter_willClear)begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end end - assign _zz_116 = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_116[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_229); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_230 : _zz_231); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_232[31:0]; - assign _zz_117 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_118 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_119 = ((execute_IS_MUL && _zz_118) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_113 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_113[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_218); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_219 : _zz_220); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_221[31:0]; + assign _zz_114 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_115 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_116 = ((execute_IS_MUL && _zz_115) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_120[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_120[31 : 0] = execute_RS1; + _zz_117[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_117[31 : 0] = execute_RS1; end - assign _zz_122 = (_zz_121 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_122 != 32'h0); + assign _zz_119 = (_zz_118 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_119 != 32'h0); assign _zz_25 = decode_SRC1_CTRL; assign _zz_23 = _zz_47; assign _zz_35 = decode_to_execute_SRC1_CTRL; - assign _zz_22 = decode_ALU_CTRL; + assign _zz_22 = decode_SRC2_CTRL; assign _zz_20 = _zz_46; - assign _zz_36 = decode_to_execute_ALU_CTRL; - assign _zz_19 = decode_SRC2_CTRL; - assign _zz_17 = _zz_45; assign _zz_34 = decode_to_execute_SRC2_CTRL; + assign _zz_19 = decode_ALU_CTRL; + assign _zz_17 = _zz_45; + assign _zz_36 = decode_to_execute_ALU_CTRL; assign _zz_16 = decode_ALU_BITWISE_CTRL; assign _zz_14 = _zz_44; assign _zz_37 = decode_to_execute_ALU_BITWISE_CTRL; @@ -3493,83 +3418,83 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_123 = 32'h0; + _zz_120 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_123[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_123[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_123[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_120[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_120[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_120[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_124 = 32'h0; + _zz_121 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_124[11 : 11] = CsrPlugin_mip_MEIP; - _zz_124[7 : 7] = CsrPlugin_mip_MTIP; - _zz_124[3 : 3] = CsrPlugin_mip_MSIP; + _zz_121[11 : 11] = CsrPlugin_mip_MEIP; + _zz_121[7 : 7] = CsrPlugin_mip_MTIP; + _zz_121[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_125 = 32'h0; + _zz_122 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_125[11 : 11] = CsrPlugin_mie_MEIE; - _zz_125[7 : 7] = CsrPlugin_mie_MTIE; - _zz_125[3 : 3] = CsrPlugin_mie_MSIE; + _zz_122[11 : 11] = CsrPlugin_mie_MEIE; + _zz_122[7 : 7] = CsrPlugin_mie_MTIE; + _zz_122[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_126 = 32'h0; + _zz_123 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_126[31 : 0] = CsrPlugin_mepc; + _zz_123[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_127 = 32'h0; + _zz_124 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_127[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_127[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_124[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_124[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_128 = 32'h0; + _zz_125 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_128[31 : 0] = CsrPlugin_mtval; + _zz_125[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_129 = 32'h0; + _zz_126 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_129[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_126[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_130 = 32'h0; + _zz_127 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_130[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_127[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_131 = 32'h0; + _zz_128 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_131[31 : 0] = _zz_121; + _zz_128[31 : 0] = _zz_118; end end always @ (*) begin - _zz_132 = 32'h0; + _zz_129 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_132[31 : 0] = _zz_122; + _zz_129[31 : 0] = _zz_119; end end - assign execute_CsrPlugin_readData = ((((_zz_123 | _zz_124) | (_zz_125 | _zz_126)) | ((_zz_127 | _zz_128) | (_zz_129 | _zz_130))) | (_zz_131 | _zz_132)); + assign execute_CsrPlugin_readData = ((((_zz_120 | _zz_121) | (_zz_122 | _zz_123)) | ((_zz_124 | _zz_125) | (_zz_126 | _zz_127))) | (_zz_128 | _zz_129)); assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; @@ -3597,19 +3522,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_133 = 4'b0001; + _zz_130 = 4'b0001; end 2'b01 : begin - _zz_133 = 4'b0011; + _zz_130 = 4'b0011; end default : begin - _zz_133 = 4'b1111; + _zz_130 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_133 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_130 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -3623,7 +3548,7 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - assign _zz_135 = 1'b0; + assign _zz_132 = 1'b0; always @ (posedge clk) begin if(reset) begin IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; @@ -3639,9 +3564,9 @@ module VexRiscv ( IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; IBusSimplePlugin_pending_value <= 3'b000; IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; - _zz_86 <= 1'b1; + _zz_87 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_97 <= 1'b0; + _zz_98 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3660,7 +3585,7 @@ module VexRiscv ( execute_CsrPlugin_wfiWake <= 1'b0; memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - _zz_121 <= 32'h0; + _zz_118 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; @@ -3742,9 +3667,9 @@ module VexRiscv ( IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_194); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_188); if(IBusSimplePlugin_iBusRsp_flush)begin - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_196); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_190); end `ifndef SYNTHESIS `ifdef FORMAL @@ -3766,9 +3691,9 @@ module VexRiscv ( end `endif `endif - _zz_86 <= 1'b0; - if(_zz_141)begin - if(_zz_162)begin + _zz_87 <= 1'b0; + if(_zz_138)begin + if(_zz_155)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -3778,7 +3703,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_97 <= (_zz_39 && writeBack_arbitration_isFiring); + _zz_98 <= (_zz_39 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -3800,14 +3725,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_163)begin - if(_zz_164)begin + if(_zz_156)begin + if(_zz_157)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_165)begin + if(_zz_158)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_166)begin + if(_zz_159)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -3831,7 +3756,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_146)begin + if(_zz_141)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3842,8 +3767,8 @@ module VexRiscv ( end endcase end - if(_zz_147)begin - case(_zz_148) + if(_zz_142)begin + case(_zz_162) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3853,7 +3778,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_111,{_zz_110,_zz_109}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_112,{_zz_111,_zz_110}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin @@ -3877,26 +3802,26 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_242[0]; - CsrPlugin_mstatus_MIE <= _zz_243[0]; + CsrPlugin_mstatus_MPIE <= _zz_231[0]; + CsrPlugin_mstatus_MIE <= _zz_232[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_245[0]; - CsrPlugin_mie_MTIE <= _zz_246[0]; - CsrPlugin_mie_MSIE <= _zz_247[0]; + CsrPlugin_mie_MEIE <= _zz_234[0]; + CsrPlugin_mie_MTIE <= _zz_235[0]; + CsrPlugin_mie_MSIE <= _zz_236[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_121 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_118 <= execute_CsrPlugin_writeData[31 : 0]; end end if(iBus_cmd_ready)begin iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; end - if(_zz_167)begin + if(_zz_160)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -3927,12 +3852,12 @@ module VexRiscv ( IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; end - if(_zz_141)begin - if(_zz_162)begin + if(_zz_138)begin + if(_zz_155)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - _zz_98 <= _zz_38[11 : 7]; + _zz_99 <= _zz_38[11 : 7]; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -3940,33 +3865,33 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_143)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_113 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_113 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(IBusSimplePlugin_decodeExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= IBusSimplePlugin_decodeExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= IBusSimplePlugin_decodeExceptionPort_payload_badAddr; end if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_145)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_115 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_115 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(DBusSimplePlugin_memoryExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusSimplePlugin_memoryExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusSimplePlugin_memoryExceptionPort_payload_badAddr; end - if(_zz_163)begin - if(_zz_164)begin + if(_zz_156)begin + if(_zz_157)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_165)begin + if(_zz_158)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_166)begin + if(_zz_159)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_146)begin + if(_zz_141)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -3980,10 +3905,10 @@ module VexRiscv ( end endcase end - if(_zz_139)begin - if(_zz_144)begin + if(_zz_136)begin + if(_zz_140)begin memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_221,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_210,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin @@ -3992,20 +3917,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_MulDivIterativePlugin_div_done <= 1'b0; end - if(_zz_140)begin - if(_zz_160)begin + if(_zz_137)begin + if(_zz_153)begin memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_result <= _zz_233[31:0]; + memory_MulDivIterativePlugin_div_result <= _zz_222[31:0]; end end end - if(_zz_161)begin + if(_zz_154)begin memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_119 ? (~ _zz_120) : _zz_120) + _zz_239); - memory_MulDivIterativePlugin_rs2 <= ((_zz_118 ? (~ execute_RS2) : execute_RS2) + _zz_241); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_119 ^ (_zz_118 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_MulDivIterativePlugin_rs1 <= ((_zz_116 ? (~ _zz_117) : _zz_117) + _zz_228); + memory_MulDivIterativePlugin_rs2 <= ((_zz_115 ? (~ execute_RS2) : execute_RS2) + _zz_230); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_116 ^ (_zz_115 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -4051,10 +3976,7 @@ module VexRiscv ( memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_21; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_18; + decode_to_execute_SRC2_CTRL <= _zz_21; end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; @@ -4083,6 +4005,9 @@ module VexRiscv ( if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_18; + end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end @@ -4140,9 +4065,6 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; - end if((! memory_arbitration_isStuck))begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end @@ -4213,7 +4135,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_244[0]; + CsrPlugin_mip_MSIP <= _zz_233[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -4230,7 +4152,7 @@ module VexRiscv ( if(iBus_cmd_ready)begin iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; end - if(_zz_167)begin + if(_zz_160)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v index 97bd61e..72929d7 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : aa12b0d45ab170fd03927c0d06fa62f6bd8e840f +// Git hash : 848042f3e4812615884ef1061d617c4d5bf6e8c2 `define Input2Kind_defaultEncoding_type [0:0] @@ -29,17 +29,17 @@ `define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 `define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + `define Src2CtrlEnum_defaultEncoding_type [1:0] `define Src2CtrlEnum_defaultEncoding_RS 2'b00 `define Src2CtrlEnum_defaultEncoding_IMI 2'b01 `define Src2CtrlEnum_defaultEncoding_IMS 2'b10 `define Src2CtrlEnum_defaultEncoding_PC 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - `define Src1CtrlEnum_defaultEncoding_type [1:0] `define Src1CtrlEnum_defaultEncoding_RS 2'b00 `define Src1CtrlEnum_defaultEncoding_IMU 2'b01 @@ -94,16 +94,19 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_151; - wire _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; + wire _zz_148; + wire _zz_149; + reg [31:0] _zz_150; + reg [31:0] _zz_151; + reg [31:0] _zz_152; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_153; + wire _zz_154; + wire _zz_155; wire _zz_156; wire _zz_157; wire _zz_158; @@ -112,12 +115,12 @@ module VexRiscv ( wire _zz_161; wire _zz_162; wire _zz_163; - wire _zz_164; + wire [1:0] _zz_164; wire _zz_165; wire _zz_166; wire _zz_167; wire _zz_168; - wire [1:0] _zz_169; + wire _zz_169; wire _zz_170; wire _zz_171; wire _zz_172; @@ -125,22 +128,22 @@ module VexRiscv ( wire _zz_174; wire _zz_175; wire _zz_176; - wire _zz_177; + wire [5:0] _zz_177; wire _zz_178; wire _zz_179; wire _zz_180; wire _zz_181; wire _zz_182; - wire [5:0] _zz_183; + wire _zz_183; wire _zz_184; - wire _zz_185; + wire [1:0] _zz_185; wire _zz_186; - wire _zz_187; - wire _zz_188; - wire _zz_189; - wire _zz_190; - wire [1:0] _zz_191; - wire _zz_192; + wire [0:0] _zz_187; + wire [0:0] _zz_188; + wire [0:0] _zz_189; + wire [0:0] _zz_190; + wire [0:0] _zz_191; + wire [0:0] _zz_192; wire [0:0] _zz_193; wire [0:0] _zz_194; wire [0:0] _zz_195; @@ -152,242 +155,214 @@ module VexRiscv ( wire [0:0] _zz_201; wire [0:0] _zz_202; wire [0:0] _zz_203; - wire [0:0] _zz_204; - wire [0:0] _zz_205; - wire [0:0] _zz_206; - wire [0:0] _zz_207; + wire [2:0] _zz_204; + wire [2:0] _zz_205; + wire [31:0] _zz_206; + wire [2:0] _zz_207; wire [0:0] _zz_208; - wire [0:0] _zz_209; - wire [2:0] _zz_210; + wire [2:0] _zz_209; + wire [0:0] _zz_210; wire [2:0] _zz_211; - wire [31:0] _zz_212; + wire [0:0] _zz_212; wire [2:0] _zz_213; wire [0:0] _zz_214; wire [2:0] _zz_215; wire [0:0] _zz_216; wire [2:0] _zz_217; - wire [0:0] _zz_218; - wire [2:0] _zz_219; - wire [0:0] _zz_220; - wire [2:0] _zz_221; - wire [2:0] _zz_222; - wire [0:0] _zz_223; - wire [2:0] _zz_224; - wire [4:0] _zz_225; - wire [11:0] _zz_226; - wire [11:0] _zz_227; + wire [4:0] _zz_218; + wire [11:0] _zz_219; + wire [11:0] _zz_220; + wire [31:0] _zz_221; + wire [31:0] _zz_222; + wire [31:0] _zz_223; + wire [31:0] _zz_224; + wire [31:0] _zz_225; + wire [31:0] _zz_226; + wire [31:0] _zz_227; wire [31:0] _zz_228; - wire [31:0] _zz_229; - wire [31:0] _zz_230; - wire [31:0] _zz_231; - wire [31:0] _zz_232; - wire [31:0] _zz_233; - wire [31:0] _zz_234; - wire [31:0] _zz_235; - wire [32:0] _zz_236; - wire [19:0] _zz_237; - wire [11:0] _zz_238; - wire [11:0] _zz_239; - wire [1:0] _zz_240; - wire [1:0] _zz_241; - wire [1:0] _zz_242; - wire [1:0] _zz_243; - wire [1:0] _zz_244; - wire [1:0] _zz_245; - wire [9:0] _zz_246; - wire [7:0] _zz_247; - wire [0:0] _zz_248; - wire [5:0] _zz_249; - wire [33:0] _zz_250; + wire [32:0] _zz_229; + wire [19:0] _zz_230; + wire [11:0] _zz_231; + wire [11:0] _zz_232; + wire [1:0] _zz_233; + wire [1:0] _zz_234; + wire [9:0] _zz_235; + wire [7:0] _zz_236; + wire [0:0] _zz_237; + wire [5:0] _zz_238; + wire [33:0] _zz_239; + wire [32:0] _zz_240; + wire [33:0] _zz_241; + wire [32:0] _zz_242; + wire [33:0] _zz_243; + wire [32:0] _zz_244; + wire [0:0] _zz_245; + wire [5:0] _zz_246; + wire [32:0] _zz_247; + wire [31:0] _zz_248; + wire [31:0] _zz_249; + wire [32:0] _zz_250; wire [32:0] _zz_251; - wire [33:0] _zz_252; + wire [32:0] _zz_252; wire [32:0] _zz_253; - wire [33:0] _zz_254; + wire [0:0] _zz_254; wire [32:0] _zz_255; wire [0:0] _zz_256; - wire [5:0] _zz_257; - wire [32:0] _zz_258; + wire [32:0] _zz_257; + wire [0:0] _zz_258; wire [31:0] _zz_259; - wire [31:0] _zz_260; - wire [32:0] _zz_261; - wire [32:0] _zz_262; - wire [32:0] _zz_263; - wire [32:0] _zz_264; + wire [0:0] _zz_260; + wire [0:0] _zz_261; + wire [0:0] _zz_262; + wire [0:0] _zz_263; + wire [0:0] _zz_264; wire [0:0] _zz_265; - wire [32:0] _zz_266; - wire [0:0] _zz_267; - wire [32:0] _zz_268; - wire [0:0] _zz_269; + wire _zz_266; + wire _zz_267; + wire [1:0] _zz_268; + wire [31:0] _zz_269; wire [31:0] _zz_270; - wire [0:0] _zz_271; + wire [31:0] _zz_271; wire [0:0] _zz_272; wire [0:0] _zz_273; - wire [0:0] _zz_274; - wire [0:0] _zz_275; - wire [0:0] _zz_276; - wire _zz_277; - wire _zz_278; - wire [1:0] _zz_279; - wire [31:0] _zz_280; - wire [31:0] _zz_281; - wire [31:0] _zz_282; - wire _zz_283; - wire [0:0] _zz_284; - wire [13:0] _zz_285; - wire [31:0] _zz_286; - wire [31:0] _zz_287; - wire [31:0] _zz_288; - wire _zz_289; + wire [2:0] _zz_274; + wire [2:0] _zz_275; + wire _zz_276; + wire [0:0] _zz_277; + wire [26:0] _zz_278; + wire [31:0] _zz_279; + wire [0:0] _zz_280; + wire [0:0] _zz_281; + wire _zz_282; + wire [0:0] _zz_283; + wire [22:0] _zz_284; + wire [31:0] _zz_285; + wire _zz_286; + wire _zz_287; + wire [0:0] _zz_288; + wire [0:0] _zz_289; wire [0:0] _zz_290; - wire [7:0] _zz_291; - wire [31:0] _zz_292; - wire [31:0] _zz_293; - wire [31:0] _zz_294; - wire _zz_295; - wire [0:0] _zz_296; - wire [1:0] _zz_297; - wire [31:0] _zz_298; - wire [31:0] _zz_299; - wire [31:0] _zz_300; - wire [0:0] _zz_301; - wire [0:0] _zz_302; - wire [2:0] _zz_303; - wire [2:0] _zz_304; - wire _zz_305; - wire [0:0] _zz_306; - wire [26:0] _zz_307; + wire [0:0] _zz_291; + wire _zz_292; + wire [0:0] _zz_293; + wire [18:0] _zz_294; + wire [31:0] _zz_295; + wire [31:0] _zz_296; + wire _zz_297; + wire _zz_298; + wire [0:0] _zz_299; + wire [0:0] _zz_300; + wire [2:0] _zz_301; + wire [2:0] _zz_302; + wire _zz_303; + wire [0:0] _zz_304; + wire [15:0] _zz_305; + wire [31:0] _zz_306; + wire [31:0] _zz_307; wire [31:0] _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; + wire [31:0] _zz_309; + wire _zz_310; wire _zz_311; - wire [0:0] _zz_312; - wire [22:0] _zz_313; - wire [31:0] _zz_314; + wire _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; wire _zz_315; - wire _zz_316; + wire [0:0] _zz_316; wire [0:0] _zz_317; - wire [0:0] _zz_318; + wire _zz_318; wire [0:0] _zz_319; - wire [0:0] _zz_320; - wire _zz_321; - wire [0:0] _zz_322; - wire [18:0] _zz_323; + wire [12:0] _zz_320; + wire [31:0] _zz_321; + wire [31:0] _zz_322; + wire [31:0] _zz_323; wire [31:0] _zz_324; wire [31:0] _zz_325; - wire _zz_326; - wire _zz_327; - wire [0:0] _zz_328; - wire [1:0] _zz_329; - wire [2:0] _zz_330; - wire [2:0] _zz_331; - wire _zz_332; - wire [0:0] _zz_333; - wire [15:0] _zz_334; - wire [31:0] _zz_335; + wire [31:0] _zz_326; + wire [31:0] _zz_327; + wire [31:0] _zz_328; + wire [0:0] _zz_329; + wire [0:0] _zz_330; + wire [1:0] _zz_331; + wire [1:0] _zz_332; + wire _zz_333; + wire [0:0] _zz_334; + wire [10:0] _zz_335; wire [31:0] _zz_336; wire [31:0] _zz_337; wire [31:0] _zz_338; wire [31:0] _zz_339; wire [31:0] _zz_340; wire [31:0] _zz_341; - wire _zz_342; - wire _zz_343; - wire [31:0] _zz_344; - wire [31:0] _zz_345; - wire [1:0] _zz_346; - wire [1:0] _zz_347; - wire _zz_348; - wire [0:0] _zz_349; - wire [12:0] _zz_350; + wire [0:0] _zz_342; + wire [1:0] _zz_343; + wire [0:0] _zz_344; + wire [0:0] _zz_345; + wire _zz_346; + wire [0:0] _zz_347; + wire [7:0] _zz_348; + wire [31:0] _zz_349; + wire [31:0] _zz_350; wire [31:0] _zz_351; wire [31:0] _zz_352; wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire [0:0] _zz_355; + wire _zz_354; + wire _zz_355; wire [0:0] _zz_356; - wire [0:0] _zz_357; - wire [1:0] _zz_358; - wire [0:0] _zz_359; - wire [0:0] _zz_360; - wire _zz_361; - wire [0:0] _zz_362; - wire [9:0] _zz_363; + wire [1:0] _zz_357; + wire [5:0] _zz_358; + wire [5:0] _zz_359; + wire _zz_360; + wire [0:0] _zz_361; + wire [4:0] _zz_362; + wire [31:0] _zz_363; wire [31:0] _zz_364; wire [31:0] _zz_365; wire [31:0] _zz_366; - wire [31:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; - wire [31:0] _zz_370; - wire [31:0] _zz_371; - wire _zz_372; - wire _zz_373; - wire [0:0] _zz_374; - wire [1:0] _zz_375; - wire [5:0] _zz_376; - wire [5:0] _zz_377; - wire _zz_378; - wire [0:0] _zz_379; - wire [6:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; + wire _zz_367; + wire [0:0] _zz_368; + wire [2:0] _zz_369; + wire _zz_370; + wire [0:0] _zz_371; + wire [0:0] _zz_372; + wire [3:0] _zz_373; + wire [3:0] _zz_374; + wire _zz_375; + wire [0:0] _zz_376; + wire [1:0] _zz_377; + wire [31:0] _zz_378; + wire [31:0] _zz_379; + wire [31:0] _zz_380; + wire _zz_381; + wire [0:0] _zz_382; + wire [0:0] _zz_383; wire [31:0] _zz_384; - wire _zz_385; - wire [0:0] _zz_386; - wire [2:0] _zz_387; - wire _zz_388; - wire [0:0] _zz_389; - wire [0:0] _zz_390; - wire [1:0] _zz_391; - wire [1:0] _zz_392; + wire [31:0] _zz_385; + wire [31:0] _zz_386; + wire _zz_387; + wire [0:0] _zz_388; + wire [1:0] _zz_389; + wire _zz_390; + wire [2:0] _zz_391; + wire [2:0] _zz_392; wire _zz_393; - wire [0:0] _zz_394; - wire [3:0] _zz_395; + wire _zz_394; + wire [31:0] _zz_395; wire [31:0] _zz_396; wire [31:0] _zz_397; wire [31:0] _zz_398; - wire _zz_399; - wire [0:0] _zz_400; - wire [0:0] _zz_401; + wire [31:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; wire [31:0] _zz_402; - wire [31:0] _zz_403; + wire _zz_403; wire [31:0] _zz_404; wire _zz_405; - wire _zz_406; - wire _zz_407; - wire [3:0] _zz_408; - wire [3:0] _zz_409; - wire _zz_410; + wire [0:0] _zz_406; + wire [0:0] _zz_407; + wire [0:0] _zz_408; + wire [0:0] _zz_409; + wire [0:0] _zz_410; wire [0:0] _zz_411; - wire [1:0] _zz_412; - wire [31:0] _zz_413; - wire [31:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; - wire [31:0] _zz_418; - wire [31:0] _zz_419; - wire [31:0] _zz_420; - wire _zz_421; - wire [0:0] _zz_422; - wire [1:0] _zz_423; - wire _zz_424; - wire [2:0] _zz_425; - wire [2:0] _zz_426; - wire _zz_427; - wire _zz_428; - wire [31:0] _zz_429; - wire [31:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire [31:0] _zz_433; - wire [31:0] _zz_434; - wire [31:0] _zz_435; - wire _zz_436; - wire _zz_437; - wire _zz_438; - wire _zz_439; wire [31:0] memory_MEMORY_READ_DATA; wire writeBack_CfuPlugin_CFU_IN_FLIGHT; wire execute_CfuPlugin_CFU_IN_FLIGHT; @@ -432,18 +407,18 @@ module VexRiscv ( wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; wire decode_SRC_LESS_UNSIGNED; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; - wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `Src2CtrlEnum_defaultEncoding_type _zz_24; + wire `Src2CtrlEnum_defaultEncoding_type _zz_25; wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; wire `Src1CtrlEnum_defaultEncoding_type _zz_26; wire `Src1CtrlEnum_defaultEncoding_type _zz_27; @@ -516,14 +491,13 @@ module VexRiscv ( reg _zz_46; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; - wire decode_LEGAL_INSTRUCTION; wire `Input2Kind_defaultEncoding_type _zz_47; wire `EnvCtrlEnum_defaultEncoding_type _zz_48; wire `BranchCtrlEnum_defaultEncoding_type _zz_49; wire `ShiftCtrlEnum_defaultEncoding_type _zz_50; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_51; - wire `Src2CtrlEnum_defaultEncoding_type _zz_52; - wire `AluCtrlEnum_defaultEncoding_type _zz_53; + wire `AluCtrlEnum_defaultEncoding_type _zz_52; + wire `Src2CtrlEnum_defaultEncoding_type _zz_53; wire `Src1CtrlEnum_defaultEncoding_type _zz_54; wire writeBack_MEMORY_STORE; reg [31:0] _zz_55; @@ -541,7 +515,6 @@ module VexRiscv ( wire memory_MMU_RSP2_refilling; wire memory_MMU_RSP2_bypassTranslation; wire [31:0] memory_PC; - wire memory_ALIGNEMENT_FAULT; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; @@ -666,14 +639,8 @@ module VexRiscv ( wire DBusSimplePlugin_mmuBus_busy; reg DBusSimplePlugin_redoBranch_valid; wire [31:0] DBusSimplePlugin_redoBranch_payload; - wire decodeExceptionPort_valid; - wire [3:0] decodeExceptionPort_payload_code; - wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; - reg BranchPlugin_branchExceptionPort_valid; - wire [3:0] BranchPlugin_branchExceptionPort_payload_code; - wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; wire CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -826,14 +793,15 @@ module VexRiscv ( wire _zz_85; wire _zz_86; wire _zz_87; - wire `Src1CtrlEnum_defaultEncoding_type _zz_88; - wire `AluCtrlEnum_defaultEncoding_type _zz_89; + wire _zz_88; + wire `Src1CtrlEnum_defaultEncoding_type _zz_89; wire `Src2CtrlEnum_defaultEncoding_type _zz_90; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_91; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_92; - wire `BranchCtrlEnum_defaultEncoding_type _zz_93; - wire `EnvCtrlEnum_defaultEncoding_type _zz_94; - wire `Input2Kind_defaultEncoding_type _zz_95; + wire `AluCtrlEnum_defaultEncoding_type _zz_91; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_92; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_93; + wire `BranchCtrlEnum_defaultEncoding_type _zz_94; + wire `EnvCtrlEnum_defaultEncoding_type _zz_95; + wire `Input2Kind_defaultEncoding_type _zz_96; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -841,15 +809,15 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_96; + reg _zz_97; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_97; reg [31:0] _zz_98; - wire _zz_99; - reg [19:0] _zz_100; - wire _zz_101; - reg [19:0] _zz_102; - reg [31:0] _zz_103; + reg [31:0] _zz_99; + wire _zz_100; + reg [19:0] _zz_101; + wire _zz_102; + reg [19:0] _zz_103; + reg [31:0] _zz_104; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; @@ -858,23 +826,23 @@ module VexRiscv ( wire [4:0] execute_LightShifterPlugin_amplitude; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_104; - reg _zz_105; + reg [31:0] _zz_105; reg _zz_106; reg _zz_107; - reg [4:0] _zz_108; + reg _zz_108; + reg [4:0] _zz_109; wire execute_BranchPlugin_eq; - wire [2:0] _zz_109; - reg _zz_110; + wire [2:0] _zz_110; reg _zz_111; + reg _zz_112; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_112; - reg [10:0] _zz_113; - wire _zz_114; - reg [19:0] _zz_115; - wire _zz_116; - reg [18:0] _zz_117; - reg [31:0] _zz_118; + wire _zz_113; + reg [10:0] _zz_114; + wire _zz_115; + reg [19:0] _zz_116; + wire _zz_117; + reg [18:0] _zz_118; + reg [31:0] _zz_119; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -896,9 +864,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_119; wire _zz_120; wire _zz_121; + wire _zz_122; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -911,12 +879,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_122; - wire _zz_123; - wire [1:0] _zz_124; - wire _zz_125; - wire [1:0] _zz_126; - wire _zz_127; + wire [1:0] _zz_123; + wire _zz_124; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -949,9 +913,9 @@ module VexRiscv ( reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_128; - reg [23:0] _zz_129; - reg [31:0] _zz_130; + wire _zz_125; + reg [23:0] _zz_126; + reg [31:0] _zz_127; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -978,18 +942,18 @@ module VexRiscv ( wire memory_MulDivIterativePlugin_div_counter_willOverflow; reg memory_MulDivIterativePlugin_div_done; reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_131; + wire [31:0] _zz_128; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [31:0] _zz_132; - wire _zz_133; - wire _zz_134; - reg [32:0] _zz_135; + wire [31:0] _zz_129; + wire _zz_130; + wire _zz_131; + reg [32:0] _zz_132; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_136; - wire [31:0] _zz_137; + reg [31:0] _zz_133; + wire [31:0] _zz_134; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -999,7 +963,7 @@ module VexRiscv ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_138; + reg _zz_135; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1016,7 +980,6 @@ module VexRiscv ( reg decode_to_execute_MEMORY_ENABLE; reg execute_to_memory_MEMORY_ENABLE; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; reg decode_to_execute_REGFILE_WRITE_VALID; reg execute_to_memory_REGFILE_WRITE_VALID; @@ -1027,6 +990,7 @@ module VexRiscv ( reg decode_to_execute_MEMORY_STORE; reg execute_to_memory_MEMORY_STORE; reg memory_to_writeBack_MEMORY_STORE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; reg decode_to_execute_SRC_LESS_UNSIGNED; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; @@ -1049,7 +1013,6 @@ module VexRiscv ( reg decode_to_execute_CSR_WRITE_OPCODE; reg decode_to_execute_CSR_READ_OPCODE; reg decode_to_execute_DO_EBREAK; - reg execute_to_memory_ALIGNEMENT_FAULT; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; reg execute_to_memory_MMU_FAULT; @@ -1067,7 +1030,7 @@ module VexRiscv ( reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg [2:0] _zz_139; + reg [2:0] _zz_136; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_836; reg execute_CsrPlugin_csr_772; @@ -1079,6 +1042,9 @@ module VexRiscv ( reg execute_CsrPlugin_csr_2944; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_137; + reg [31:0] _zz_138; + reg [31:0] _zz_139; reg [31:0] _zz_140; reg [31:0] _zz_141; reg [31:0] _zz_142; @@ -1086,9 +1052,6 @@ module VexRiscv ( reg [31:0] _zz_144; reg [31:0] _zz_145; reg [31:0] _zz_146; - reg [31:0] _zz_147; - reg [31:0] _zz_148; - reg [31:0] _zz_149; wire iBus_cmd_m2sPipe_valid; wire iBus_cmd_m2sPipe_ready; wire [31:0] iBus_cmd_m2sPipe_payload_pc; @@ -1106,7 +1069,7 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_150; + reg [3:0] _zz_147; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] _zz_1_string; @@ -1132,14 +1095,14 @@ module VexRiscv ( reg [39:0] _zz_17_string; reg [39:0] _zz_18_string; reg [39:0] _zz_19_string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_20_string; - reg [23:0] _zz_21_string; - reg [23:0] _zz_22_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_23_string; - reg [63:0] _zz_24_string; - reg [63:0] _zz_25_string; + reg [63:0] _zz_20_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_23_string; + reg [23:0] _zz_24_string; + reg [23:0] _zz_25_string; reg [95:0] decode_SRC1_CTRL_string; reg [95:0] _zz_26_string; reg [95:0] _zz_27_string; @@ -1169,20 +1132,20 @@ module VexRiscv ( reg [31:0] _zz_49_string; reg [71:0] _zz_50_string; reg [39:0] _zz_51_string; - reg [23:0] _zz_52_string; - reg [63:0] _zz_53_string; + reg [63:0] _zz_52_string; + reg [23:0] _zz_53_string; reg [95:0] _zz_54_string; - reg [95:0] _zz_88_string; - reg [63:0] _zz_89_string; + reg [95:0] _zz_89_string; reg [23:0] _zz_90_string; - reg [39:0] _zz_91_string; - reg [71:0] _zz_92_string; - reg [31:0] _zz_93_string; - reg [39:0] _zz_94_string; + reg [63:0] _zz_91_string; + reg [39:0] _zz_92_string; + reg [71:0] _zz_93_string; + reg [31:0] _zz_94_string; reg [39:0] _zz_95_string; + reg [39:0] _zz_96_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; @@ -1194,299 +1157,274 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_156 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_157 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_158 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_159 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_160 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_161 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_162 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_163 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_164 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_165 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_166 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_167 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_168 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); - assign _zz_169 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_170 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_171 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_172 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_173 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_174 = (1'b1 || (! 1'b1)); - assign _zz_175 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_176 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_177 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_178 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_179 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_180 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_181 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_182 = (! memory_arbitration_isStuck); - assign _zz_183 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_184 = (! execute_arbitration_isStuckByOthers); - assign _zz_185 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_186 = ((_zz_119 && 1'b1) && (! 1'b0)); - assign _zz_187 = ((_zz_120 && 1'b1) && (! 1'b0)); - assign _zz_188 = ((_zz_121 && 1'b1) && (! 1'b0)); - assign _zz_189 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_190 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_191 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_192 = execute_INSTRUCTION[13]; - assign _zz_193 = _zz_80[31 : 31]; - assign _zz_194 = _zz_80[30 : 30]; - assign _zz_195 = _zz_80[29 : 29]; - assign _zz_196 = _zz_80[28 : 28]; - assign _zz_197 = _zz_80[26 : 26]; - assign _zz_198 = _zz_80[23 : 23]; - assign _zz_199 = _zz_80[15 : 15]; - assign _zz_200 = _zz_80[12 : 12]; - assign _zz_201 = _zz_80[11 : 11]; - assign _zz_202 = _zz_80[10 : 10]; - assign _zz_203 = _zz_80[32 : 32]; - assign _zz_204 = _zz_80[14 : 14]; - assign _zz_205 = _zz_80[4 : 4]; - assign _zz_206 = _zz_80[2 : 2]; - assign _zz_207 = _zz_80[18 : 18]; - assign _zz_208 = _zz_80[9 : 9]; - assign _zz_209 = _zz_80[3 : 3]; - assign _zz_210 = (_zz_58 - 3'b001); - assign _zz_211 = {IBusSimplePlugin_fetchPc_inc,2'b00}; - assign _zz_212 = {29'd0, _zz_211}; - assign _zz_213 = (IBusSimplePlugin_pending_value + _zz_215); - assign _zz_214 = IBusSimplePlugin_pending_inc; + assign _zz_153 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_154 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_155 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_156 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_157 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_158 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_159 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_160 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_161 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_162 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_163 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); + assign _zz_164 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_165 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); + assign _zz_166 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_167 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_168 = (1'b1 || (! 1'b1)); + assign _zz_169 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_170 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_171 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_172 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_173 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_174 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_175 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_176 = (! memory_arbitration_isStuck); + assign _zz_177 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_178 = (! execute_arbitration_isStuckByOthers); + assign _zz_179 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_180 = ((_zz_120 && 1'b1) && (! 1'b0)); + assign _zz_181 = ((_zz_121 && 1'b1) && (! 1'b0)); + assign _zz_182 = ((_zz_122 && 1'b1) && (! 1'b0)); + assign _zz_183 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_184 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_185 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_186 = execute_INSTRUCTION[13]; + assign _zz_187 = _zz_80[31 : 31]; + assign _zz_188 = _zz_80[30 : 30]; + assign _zz_189 = _zz_80[29 : 29]; + assign _zz_190 = _zz_80[28 : 28]; + assign _zz_191 = _zz_80[26 : 26]; + assign _zz_192 = _zz_80[23 : 23]; + assign _zz_193 = _zz_80[14 : 14]; + assign _zz_194 = _zz_80[10 : 10]; + assign _zz_195 = _zz_80[9 : 9]; + assign _zz_196 = _zz_80[8 : 8]; + assign _zz_197 = _zz_80[32 : 32]; + assign _zz_198 = _zz_80[11 : 11]; + assign _zz_199 = _zz_80[4 : 4]; + assign _zz_200 = _zz_80[2 : 2]; + assign _zz_201 = _zz_80[17 : 17]; + assign _zz_202 = _zz_80[7 : 7]; + assign _zz_203 = _zz_80[3 : 3]; + assign _zz_204 = (_zz_58 - 3'b001); + assign _zz_205 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_206 = {29'd0, _zz_205}; + assign _zz_207 = (IBusSimplePlugin_pending_value + _zz_209); + assign _zz_208 = IBusSimplePlugin_pending_inc; + assign _zz_209 = {2'd0, _zz_208}; + assign _zz_210 = IBusSimplePlugin_pending_dec; + assign _zz_211 = {2'd0, _zz_210}; + assign _zz_212 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_213 = {2'd0, _zz_212}; + assign _zz_214 = IBusSimplePlugin_pending_dec; assign _zz_215 = {2'd0, _zz_214}; - assign _zz_216 = IBusSimplePlugin_pending_dec; - assign _zz_217 = {2'd0, _zz_216}; - assign _zz_218 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); - assign _zz_219 = {2'd0, _zz_218}; - assign _zz_220 = IBusSimplePlugin_pending_dec; - assign _zz_221 = {2'd0, _zz_220}; - assign _zz_222 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_223 = execute_SRC_LESS; - assign _zz_224 = 3'b100; - assign _zz_225 = execute_INSTRUCTION[19 : 15]; - assign _zz_226 = execute_INSTRUCTION[31 : 20]; - assign _zz_227 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_228 = ($signed(_zz_229) + $signed(_zz_232)); - assign _zz_229 = ($signed(_zz_230) + $signed(_zz_231)); - assign _zz_230 = execute_SRC1; - assign _zz_231 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_232 = (execute_SRC_USE_SUB_LESS ? _zz_233 : _zz_234); - assign _zz_233 = 32'h00000001; - assign _zz_234 = 32'h0; - assign _zz_235 = (_zz_236 >>> 1); - assign _zz_236 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_237 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_238 = execute_INSTRUCTION[31 : 20]; - assign _zz_239 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_240 = (_zz_122 & (~ _zz_241)); - assign _zz_241 = (_zz_122 - 2'b01); - assign _zz_242 = (_zz_124 & (~ _zz_243)); - assign _zz_243 = (_zz_124 - 2'b01); - assign _zz_244 = (_zz_126 & (~ _zz_245)); - assign _zz_245 = (_zz_126 - 2'b01); - assign _zz_246 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_247 = execute_INSTRUCTION[31 : 24]; - assign _zz_248 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_249 = {5'd0, _zz_248}; - assign _zz_250 = (_zz_252 + _zz_254); - assign _zz_251 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_252 = {{1{_zz_251[32]}}, _zz_251}; - assign _zz_253 = _zz_255; - assign _zz_254 = {{1{_zz_253[32]}}, _zz_253}; - assign _zz_255 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_256 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_257 = {5'd0, _zz_256}; - assign _zz_258 = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_259 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_260 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_261 = {_zz_131,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_262 = _zz_263; - assign _zz_263 = _zz_264; - assign _zz_264 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_132) : _zz_132)} + _zz_266); - assign _zz_265 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_266 = {32'd0, _zz_265}; - assign _zz_267 = _zz_134; - assign _zz_268 = {32'd0, _zz_267}; - assign _zz_269 = _zz_133; - assign _zz_270 = {31'd0, _zz_269}; - assign _zz_271 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_272 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_273 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_274 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_275 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_276 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_277 = 1'b1; - assign _zz_278 = 1'b1; - assign _zz_279 = {_zz_61,_zz_60}; - assign _zz_280 = 32'h0000106f; - assign _zz_281 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_282 = 32'h00001073; - assign _zz_283 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_284 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_285 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_286) == 32'h00000003),{(_zz_287 == _zz_288),{_zz_289,{_zz_290,_zz_291}}}}}}; - assign _zz_286 = 32'h0000207f; - assign _zz_287 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_288 = 32'h00000003; - assign _zz_289 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_290 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_291 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & _zz_292) == 32'h00005013),{(_zz_293 == _zz_294),{_zz_295,{_zz_296,_zz_297}}}}}}; - assign _zz_292 = 32'hbc00707f; - assign _zz_293 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_294 = 32'h00005033; - assign _zz_295 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_296 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_297 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz_298 = 32'h10103050; - assign _zz_299 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_300 = 32'h02004020; - assign _zz_301 = _zz_87; - assign _zz_302 = _zz_86; - assign _zz_303 = {_zz_87,{_zz_85,_zz_86}}; - assign _zz_304 = 3'b000; - assign _zz_305 = (((decode_INSTRUCTION & _zz_308) == 32'h02000030) != 1'b0); - assign _zz_306 = 1'b0; - assign _zz_307 = {(_zz_84 != 1'b0),{(_zz_309 != _zz_310),{_zz_311,{_zz_312,_zz_313}}}}; - assign _zz_308 = 32'h02004074; - assign _zz_309 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); - assign _zz_310 = 1'b0; - assign _zz_311 = (((decode_INSTRUCTION & _zz_314) == 32'h10000050) != 1'b0); - assign _zz_312 = ({_zz_315,_zz_316} != 2'b00); - assign _zz_313 = {({_zz_317,_zz_318} != 2'b00),{(_zz_319 != _zz_320),{_zz_321,{_zz_322,_zz_323}}}}; - assign _zz_314 = 32'h10403050; - assign _zz_315 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_316 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_317 = _zz_83; - assign _zz_318 = ((decode_INSTRUCTION & _zz_324) == 32'h00000004); - assign _zz_319 = ((decode_INSTRUCTION & _zz_325) == 32'h00000040); - assign _zz_320 = 1'b0; - assign _zz_321 = ({_zz_326,_zz_327} != 2'b00); - assign _zz_322 = ({_zz_328,_zz_329} != 3'b000); - assign _zz_323 = {(_zz_330 != _zz_331),{_zz_332,{_zz_333,_zz_334}}}; - assign _zz_324 = 32'h0000001c; - assign _zz_325 = 32'h00000058; - assign _zz_326 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_327 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_328 = ((decode_INSTRUCTION & _zz_335) == 32'h40001010); - assign _zz_329 = {(_zz_336 == _zz_337),(_zz_338 == _zz_339)}; - assign _zz_330 = {(_zz_340 == _zz_341),{_zz_342,_zz_343}}; - assign _zz_331 = 3'b000; - assign _zz_332 = ((_zz_344 == _zz_345) != 1'b0); - assign _zz_333 = (_zz_85 != 1'b0); - assign _zz_334 = {(_zz_346 != _zz_347),{_zz_348,{_zz_349,_zz_350}}}; - assign _zz_335 = 32'h40003054; - assign _zz_336 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_337 = 32'h00001010; - assign _zz_338 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_339 = 32'h00001010; - assign _zz_340 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_341 = 32'h00000024; - assign _zz_342 = ((decode_INSTRUCTION & 32'h00003034) == 32'h00001010); - assign _zz_343 = ((decode_INSTRUCTION & 32'h02003054) == 32'h00001010); - assign _zz_344 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_345 = 32'h00001000; - assign _zz_346 = {(_zz_351 == _zz_352),(_zz_353 == _zz_354)}; - assign _zz_347 = 2'b00; - assign _zz_348 = ({_zz_84,{_zz_355,_zz_356}} != 3'b000); - assign _zz_349 = ({_zz_357,_zz_358} != 3'b000); - assign _zz_350 = {(_zz_359 != _zz_360),{_zz_361,{_zz_362,_zz_363}}}; - assign _zz_351 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_352 = 32'h00002000; - assign _zz_353 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_354 = 32'h00001000; - assign _zz_355 = ((decode_INSTRUCTION & _zz_364) == 32'h00000020); - assign _zz_356 = ((decode_INSTRUCTION & _zz_365) == 32'h00000020); - assign _zz_357 = ((decode_INSTRUCTION & _zz_366) == 32'h00000040); - assign _zz_358 = {(_zz_367 == _zz_368),(_zz_369 == _zz_370)}; - assign _zz_359 = ((decode_INSTRUCTION & _zz_371) == 32'h00000020); - assign _zz_360 = 1'b0; - assign _zz_361 = ({_zz_372,_zz_373} != 2'b00); - assign _zz_362 = ({_zz_374,_zz_375} != 3'b000); - assign _zz_363 = {(_zz_376 != _zz_377),{_zz_378,{_zz_379,_zz_380}}}; - assign _zz_364 = 32'h00000034; - assign _zz_365 = 32'h00000064; - assign _zz_366 = 32'h00000050; - assign _zz_367 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_368 = 32'h0; - assign _zz_369 = (decode_INSTRUCTION & 32'h00103040); - assign _zz_370 = 32'h00000040; - assign _zz_371 = 32'h00000020; - assign _zz_372 = ((decode_INSTRUCTION & 32'h00000008) == 32'h00000008); - assign _zz_373 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); - assign _zz_374 = _zz_82; - assign _zz_375 = {(_zz_381 == _zz_382),(_zz_383 == _zz_384)}; - assign _zz_376 = {_zz_83,{_zz_385,{_zz_386,_zz_387}}}; - assign _zz_377 = 6'h0; - assign _zz_378 = ({_zz_82,_zz_388} != 2'b00); - assign _zz_379 = ({_zz_389,_zz_390} != 2'b00); - assign _zz_380 = {(_zz_391 != _zz_392),{_zz_393,{_zz_394,_zz_395}}}; - assign _zz_381 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_382 = 32'h00000010; - assign _zz_383 = (decode_INSTRUCTION & 32'h02000060); - assign _zz_384 = 32'h00000020; - assign _zz_385 = ((decode_INSTRUCTION & _zz_396) == 32'h00001010); - assign _zz_386 = (_zz_397 == _zz_398); - assign _zz_387 = {_zz_399,{_zz_400,_zz_401}}; - assign _zz_388 = ((decode_INSTRUCTION & _zz_402) == 32'h00000020); - assign _zz_389 = _zz_82; - assign _zz_390 = (_zz_403 == _zz_404); - assign _zz_391 = {_zz_405,_zz_406}; - assign _zz_392 = 2'b00; - assign _zz_393 = (_zz_407 != 1'b0); - assign _zz_394 = (_zz_408 != _zz_409); - assign _zz_395 = {_zz_410,{_zz_411,_zz_412}}; - assign _zz_396 = 32'h00001010; - assign _zz_397 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_398 = 32'h00002010; - assign _zz_399 = ((decode_INSTRUCTION & _zz_413) == 32'h00000010); - assign _zz_400 = (_zz_414 == _zz_415); - assign _zz_401 = (_zz_416 == _zz_417); - assign _zz_402 = 32'h00000070; - assign _zz_403 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_404 = 32'h0; - assign _zz_405 = ((decode_INSTRUCTION & _zz_418) == 32'h00006010); - assign _zz_406 = ((decode_INSTRUCTION & _zz_419) == 32'h00004010); - assign _zz_407 = ((decode_INSTRUCTION & _zz_420) == 32'h00002010); - assign _zz_408 = {_zz_421,{_zz_422,_zz_423}}; - assign _zz_409 = 4'b0000; - assign _zz_410 = (_zz_424 != 1'b0); - assign _zz_411 = (_zz_425 != _zz_426); - assign _zz_412 = {_zz_427,_zz_428}; - assign _zz_413 = 32'h00000050; - assign _zz_414 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_415 = 32'h00000004; - assign _zz_416 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_417 = 32'h0; - assign _zz_418 = 32'h00006014; - assign _zz_419 = 32'h00005014; - assign _zz_420 = 32'h00006014; - assign _zz_421 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_422 = ((decode_INSTRUCTION & _zz_429) == 32'h0); - assign _zz_423 = {(_zz_430 == _zz_431),(_zz_432 == _zz_433)}; - assign _zz_424 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_425 = {(_zz_434 == _zz_435),{_zz_436,_zz_437}}; - assign _zz_426 = 3'b000; - assign _zz_427 = ({_zz_438,_zz_81} != 2'b00); - assign _zz_428 = ({_zz_439,_zz_81} != 2'b00); - assign _zz_429 = 32'h00000018; - assign _zz_430 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_431 = 32'h00002000; - assign _zz_432 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_433 = 32'h00001000; - assign _zz_434 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_435 = 32'h00000040; - assign _zz_436 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_437 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz_438 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_439 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_216 = execute_SRC_LESS; + assign _zz_217 = 3'b100; + assign _zz_218 = execute_INSTRUCTION[19 : 15]; + assign _zz_219 = execute_INSTRUCTION[31 : 20]; + assign _zz_220 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_221 = ($signed(_zz_222) + $signed(_zz_225)); + assign _zz_222 = ($signed(_zz_223) + $signed(_zz_224)); + assign _zz_223 = execute_SRC1; + assign _zz_224 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_225 = (execute_SRC_USE_SUB_LESS ? _zz_226 : _zz_227); + assign _zz_226 = 32'h00000001; + assign _zz_227 = 32'h0; + assign _zz_228 = (_zz_229 >>> 1); + assign _zz_229 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_230 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_231 = execute_INSTRUCTION[31 : 20]; + assign _zz_232 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_233 = (_zz_123 & (~ _zz_234)); + assign _zz_234 = (_zz_123 - 2'b01); + assign _zz_235 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_236 = execute_INSTRUCTION[31 : 24]; + assign _zz_237 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_238 = {5'd0, _zz_237}; + assign _zz_239 = (_zz_241 + _zz_243); + assign _zz_240 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_241 = {{1{_zz_240[32]}}, _zz_240}; + assign _zz_242 = _zz_244; + assign _zz_243 = {{1{_zz_242[32]}}, _zz_242}; + assign _zz_244 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_245 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_246 = {5'd0, _zz_245}; + assign _zz_247 = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_248 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_249 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_250 = {_zz_128,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_251 = _zz_252; + assign _zz_252 = _zz_253; + assign _zz_253 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_129) : _zz_129)} + _zz_255); + assign _zz_254 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_255 = {32'd0, _zz_254}; + assign _zz_256 = _zz_131; + assign _zz_257 = {32'd0, _zz_256}; + assign _zz_258 = _zz_130; + assign _zz_259 = {31'd0, _zz_258}; + assign _zz_260 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_261 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_262 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_263 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_264 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_265 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_266 = 1'b1; + assign _zz_267 = 1'b1; + assign _zz_268 = {_zz_61,_zz_60}; + assign _zz_269 = 32'h10103050; + assign _zz_270 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_271 = 32'h02004020; + assign _zz_272 = _zz_88; + assign _zz_273 = _zz_87; + assign _zz_274 = {_zz_88,{_zz_86,_zz_87}}; + assign _zz_275 = 3'b000; + assign _zz_276 = (((decode_INSTRUCTION & _zz_279) == 32'h02000030) != 1'b0); + assign _zz_277 = 1'b0; + assign _zz_278 = {(_zz_85 != 1'b0),{(_zz_280 != _zz_281),{_zz_282,{_zz_283,_zz_284}}}}; + assign _zz_279 = 32'h02004074; + assign _zz_280 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz_281 = 1'b0; + assign _zz_282 = (((decode_INSTRUCTION & _zz_285) == 32'h10000050) != 1'b0); + assign _zz_283 = ({_zz_286,_zz_287} != 2'b00); + assign _zz_284 = {({_zz_288,_zz_289} != 2'b00),{(_zz_290 != _zz_291),{_zz_292,{_zz_293,_zz_294}}}}; + assign _zz_285 = 32'h10403050; + assign _zz_286 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_287 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_288 = _zz_84; + assign _zz_289 = ((decode_INSTRUCTION & _zz_295) == 32'h00000004); + assign _zz_290 = ((decode_INSTRUCTION & _zz_296) == 32'h00000040); + assign _zz_291 = 1'b0; + assign _zz_292 = ({_zz_297,_zz_298} != 2'b00); + assign _zz_293 = ({_zz_299,_zz_300} != 2'b00); + assign _zz_294 = {(_zz_301 != _zz_302),{_zz_303,{_zz_304,_zz_305}}}; + assign _zz_295 = 32'h0000001c; + assign _zz_296 = 32'h00000058; + assign _zz_297 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_298 = ((decode_INSTRUCTION & 32'h00103040) == 32'h00000040); + assign _zz_299 = ((decode_INSTRUCTION & _zz_306) == 32'h00005010); + assign _zz_300 = ((decode_INSTRUCTION & _zz_307) == 32'h00005020); + assign _zz_301 = {(_zz_308 == _zz_309),{_zz_310,_zz_311}}; + assign _zz_302 = 3'b000; + assign _zz_303 = ({_zz_312,{_zz_313,_zz_314}} != 3'b000); + assign _zz_304 = (_zz_315 != 1'b0); + assign _zz_305 = {(_zz_316 != _zz_317),{_zz_318,{_zz_319,_zz_320}}}; + assign _zz_306 = 32'h00007034; + assign _zz_307 = 32'h02007064; + assign _zz_308 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_309 = 32'h40001010; + assign _zz_310 = ((decode_INSTRUCTION & _zz_321) == 32'h00001010); + assign _zz_311 = ((decode_INSTRUCTION & _zz_322) == 32'h00001010); + assign _zz_312 = ((decode_INSTRUCTION & _zz_323) == 32'h00000024); + assign _zz_313 = (_zz_324 == _zz_325); + assign _zz_314 = (_zz_326 == _zz_327); + assign _zz_315 = ((decode_INSTRUCTION & _zz_328) == 32'h00001000); + assign _zz_316 = _zz_86; + assign _zz_317 = 1'b0; + assign _zz_318 = ({_zz_329,_zz_330} != 2'b00); + assign _zz_319 = (_zz_331 != _zz_332); + assign _zz_320 = {_zz_333,{_zz_334,_zz_335}}; + assign _zz_321 = 32'h00007034; + assign _zz_322 = 32'h02007054; + assign _zz_323 = 32'h00000064; + assign _zz_324 = (decode_INSTRUCTION & 32'h00003034); + assign _zz_325 = 32'h00001010; + assign _zz_326 = (decode_INSTRUCTION & 32'h02003054); + assign _zz_327 = 32'h00001010; + assign _zz_328 = 32'h00001000; + assign _zz_329 = ((decode_INSTRUCTION & _zz_336) == 32'h00002000); + assign _zz_330 = ((decode_INSTRUCTION & _zz_337) == 32'h00001000); + assign _zz_331 = {(_zz_338 == _zz_339),(_zz_340 == _zz_341)}; + assign _zz_332 = 2'b00; + assign _zz_333 = (_zz_82 != 1'b0); + assign _zz_334 = ({_zz_342,_zz_343} != 3'b000); + assign _zz_335 = {(_zz_344 != _zz_345),{_zz_346,{_zz_347,_zz_348}}}; + assign _zz_336 = 32'h00002010; + assign _zz_337 = 32'h00005000; + assign _zz_338 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_339 = 32'h00006000; + assign _zz_340 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_341 = 32'h00004000; + assign _zz_342 = _zz_85; + assign _zz_343 = {(_zz_349 == _zz_350),(_zz_351 == _zz_352)}; + assign _zz_344 = ((decode_INSTRUCTION & _zz_353) == 32'h00000020); + assign _zz_345 = 1'b0; + assign _zz_346 = ({_zz_354,_zz_355} != 2'b00); + assign _zz_347 = ({_zz_356,_zz_357} != 3'b000); + assign _zz_348 = {(_zz_358 != _zz_359),{_zz_360,{_zz_361,_zz_362}}}; + assign _zz_349 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_350 = 32'h00000020; + assign _zz_351 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_352 = 32'h00000020; + assign _zz_353 = 32'h00000020; + assign _zz_354 = ((decode_INSTRUCTION & 32'h00000008) == 32'h00000008); + assign _zz_355 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); + assign _zz_356 = _zz_83; + assign _zz_357 = {(_zz_363 == _zz_364),(_zz_365 == _zz_366)}; + assign _zz_358 = {_zz_84,{_zz_367,{_zz_368,_zz_369}}}; + assign _zz_359 = 6'h0; + assign _zz_360 = ({_zz_83,_zz_370} != 2'b00); + assign _zz_361 = ({_zz_371,_zz_372} != 2'b00); + assign _zz_362 = {(_zz_373 != _zz_374),{_zz_375,{_zz_376,_zz_377}}}; + assign _zz_363 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_364 = 32'h00000010; + assign _zz_365 = (decode_INSTRUCTION & 32'h02000060); + assign _zz_366 = 32'h00000020; + assign _zz_367 = ((decode_INSTRUCTION & _zz_378) == 32'h00001010); + assign _zz_368 = (_zz_379 == _zz_380); + assign _zz_369 = {_zz_381,{_zz_382,_zz_383}}; + assign _zz_370 = ((decode_INSTRUCTION & _zz_384) == 32'h00000020); + assign _zz_371 = _zz_83; + assign _zz_372 = (_zz_385 == _zz_386); + assign _zz_373 = {_zz_387,{_zz_388,_zz_389}}; + assign _zz_374 = 4'b0000; + assign _zz_375 = (_zz_390 != 1'b0); + assign _zz_376 = (_zz_391 != _zz_392); + assign _zz_377 = {_zz_393,_zz_394}; + assign _zz_378 = 32'h00001010; + assign _zz_379 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_380 = 32'h00002010; + assign _zz_381 = ((decode_INSTRUCTION & _zz_395) == 32'h00000010); + assign _zz_382 = (_zz_396 == _zz_397); + assign _zz_383 = (_zz_398 == _zz_399); + assign _zz_384 = 32'h00000070; + assign _zz_385 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_386 = 32'h0; + assign _zz_387 = ((decode_INSTRUCTION & _zz_400) == 32'h0); + assign _zz_388 = (_zz_401 == _zz_402); + assign _zz_389 = {_zz_82,_zz_403}; + assign _zz_390 = ((decode_INSTRUCTION & _zz_404) == 32'h0); + assign _zz_391 = {_zz_405,{_zz_406,_zz_407}}; + assign _zz_392 = 3'b000; + assign _zz_393 = ({_zz_408,_zz_409} != 2'b00); + assign _zz_394 = ({_zz_410,_zz_411} != 2'b00); + assign _zz_395 = 32'h00000050; + assign _zz_396 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_397 = 32'h00000004; + assign _zz_398 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_399 = 32'h0; + assign _zz_400 = 32'h00000044; + assign _zz_401 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_402 = 32'h0; + assign _zz_403 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_404 = 32'h00000058; + assign _zz_405 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_406 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_407 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz_408 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_409 = _zz_81; + assign _zz_410 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_411 = _zz_81; always @ (posedge clk) begin - if(_zz_277) begin - _zz_153 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_266) begin + _zz_150 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_278) begin - _zz_154 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_267) begin + _zz_151 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1502,24 +1440,24 @@ module VexRiscv ( .io_push_payload_error (iBus_rsp_payload_error ), //i .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o - .io_pop_ready (_zz_151 ), //i + .io_pop_ready (_zz_148 ), //i .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o - .io_flush (_zz_152 ), //i + .io_flush (_zz_149 ), //i .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o .clk (clk ), //i .reset (reset ) //i ); always @(*) begin - case(_zz_279) + case(_zz_268) 2'b00 : begin - _zz_155 = CsrPlugin_jumpInterface_payload; + _zz_152 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_155 = DBusSimplePlugin_redoBranch_payload; + _zz_152 = DBusSimplePlugin_redoBranch_payload; end default : begin - _zz_155 = BranchPlugin_jumpInterface_payload; + _zz_152 = BranchPlugin_jumpInterface_payload; end endcase end @@ -1722,71 +1660,71 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; + default : _zz_20_string = "????????"; endcase end always @(*) begin case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; endcase end always @(*) begin case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; endcase end always @(*) begin case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_24_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_24_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_24_string = "PC "; + default : _zz_24_string = "???"; endcase end always @(*) begin case(_zz_25) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; - default : _zz_25_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_25_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_25_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_25_string = "PC "; + default : _zz_25_string = "???"; endcase end always @(*) begin @@ -2034,19 +1972,19 @@ module VexRiscv ( end always @(*) begin case(_zz_52) - `Src2CtrlEnum_defaultEncoding_RS : _zz_52_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_52_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_52_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_52_string = "PC "; - default : _zz_52_string = "???"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_52_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_52_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_52_string = "BITWISE "; + default : _zz_52_string = "????????"; endcase end always @(*) begin case(_zz_53) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_53_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_53_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_53_string = "BITWISE "; - default : _zz_53_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_53_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_53_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_53_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_53_string = "PC "; + default : _zz_53_string = "???"; endcase end always @(*) begin @@ -2058,21 +1996,13 @@ module VexRiscv ( default : _zz_54_string = "????????????"; endcase end - always @(*) begin - case(_zz_88) - `Src1CtrlEnum_defaultEncoding_RS : _zz_88_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_88_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_88_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_88_string = "URS1 "; - default : _zz_88_string = "????????????"; - endcase - end always @(*) begin case(_zz_89) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_89_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_89_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_89_string = "BITWISE "; - default : _zz_89_string = "????????"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_89_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_89_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_89_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_89_string = "URS1 "; + default : _zz_89_string = "????????????"; endcase end always @(*) begin @@ -2086,45 +2016,53 @@ module VexRiscv ( end always @(*) begin case(_zz_91) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_91_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_91_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_91_string = "AND_1"; - default : _zz_91_string = "?????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_91_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_91_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_91_string = "BITWISE "; + default : _zz_91_string = "????????"; endcase end always @(*) begin case(_zz_92) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_92_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_92_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_92_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_92_string = "SRA_1 "; - default : _zz_92_string = "?????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_92_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_92_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_92_string = "AND_1"; + default : _zz_92_string = "?????"; endcase end always @(*) begin case(_zz_93) - `BranchCtrlEnum_defaultEncoding_INC : _zz_93_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_93_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_93_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_93_string = "JALR"; - default : _zz_93_string = "????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_93_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_93_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_93_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_93_string = "SRA_1 "; + default : _zz_93_string = "?????????"; endcase end always @(*) begin case(_zz_94) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_94_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_94_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_94_string = "ECALL"; - default : _zz_94_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_94_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_94_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_94_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_94_string = "JALR"; + default : _zz_94_string = "????"; endcase end always @(*) begin case(_zz_95) - `Input2Kind_defaultEncoding_RS : _zz_95_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_95_string = "IMM_I"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_95_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_95_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_95_string = "ECALL"; default : _zz_95_string = "?????"; endcase end + always @(*) begin + case(_zz_96) + `Input2Kind_defaultEncoding_RS : _zz_96_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_96_string = "IMM_I"; + default : _zz_96_string = "?????"; + endcase + end always @(*) begin case(decode_to_execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; @@ -2134,14 +2072,6 @@ module VexRiscv ( default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end - always @(*) begin - case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; - default : decode_to_execute_ALU_CTRL_string = "????????"; - endcase - end always @(*) begin case(decode_to_execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; @@ -2151,6 +2081,14 @@ module VexRiscv ( default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; @@ -2214,7 +2152,7 @@ module VexRiscv ( assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_97; + assign execute_REGFILE_WRITE_DATA = _zz_98; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); @@ -2223,32 +2161,32 @@ module VexRiscv ( assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign decode_IS_DIV = _zz_193[0]; - assign decode_IS_RS2_SIGNED = _zz_194[0]; - assign decode_IS_RS1_SIGNED = _zz_195[0]; - assign decode_IS_MUL = _zz_196[0]; + assign decode_IS_DIV = _zz_187[0]; + assign decode_IS_RS2_SIGNED = _zz_188[0]; + assign decode_IS_RS1_SIGNED = _zz_189[0]; + assign decode_IS_MUL = _zz_190[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_197[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_191[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_198[0]; + assign decode_IS_CSR = _zz_192[0]; assign decode_BRANCH_CTRL = _zz_11; assign _zz_12 = _zz_13; assign decode_SHIFT_CTRL = _zz_14; assign _zz_15 = _zz_16; assign decode_ALU_BITWISE_CTRL = _zz_17; assign _zz_18 = _zz_19; - assign decode_SRC_LESS_UNSIGNED = _zz_199[0]; - assign decode_MEMORY_STORE = _zz_200[0]; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_201[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_202[0]; - assign decode_SRC2_CTRL = _zz_20; + assign decode_SRC_LESS_UNSIGNED = _zz_193[0]; + assign decode_ALU_CTRL = _zz_20; assign _zz_21 = _zz_22; - assign decode_ALU_CTRL = _zz_23; + assign decode_MEMORY_STORE = _zz_194[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_195[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_196[0]; + assign decode_SRC2_CTRL = _zz_23; assign _zz_24 = _zz_25; assign decode_SRC1_CTRL = _zz_26; assign _zz_27 = _zz_28; @@ -2257,7 +2195,7 @@ module VexRiscv ( assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_203[0]; + assign decode_IS_EBREAK = _zz_197[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_MUL = decode_to_execute_IS_MUL; @@ -2283,10 +2221,10 @@ module VexRiscv ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_31 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_156)begin + if(_zz_153)begin _zz_31 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_157)begin + if(_zz_154)begin _zz_31 = memory_MulDivIterativePlugin_div_result; end end @@ -2301,12 +2239,12 @@ module VexRiscv ( assign execute_ENV_CTRL = _zz_34; assign writeBack_ENV_CTRL = _zz_35; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_111; + assign execute_BRANCH_DO = _zz_112; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_204[0]; - assign decode_RS1_USE = _zz_205[0]; + assign decode_RS2_USE = _zz_198[0]; + assign decode_RS1_USE = _zz_199[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; @@ -2315,10 +2253,10 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_158)begin - _zz_37 = _zz_104; + if(_zz_155)begin + _zz_37 = _zz_105; end - if(_zz_159)begin + if(_zz_156)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2330,13 +2268,13 @@ module VexRiscv ( assign _zz_39 = execute_PC; assign execute_SRC2_CTRL = _zz_40; assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_206[0]; - assign decode_SRC_ADD_ZERO = _zz_207[0]; + assign decode_SRC_USE_SUB_LESS = _zz_200[0]; + assign decode_SRC_ADD_ZERO = _zz_201[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_42; - assign execute_SRC2 = _zz_103; - assign execute_SRC1 = _zz_98; + assign execute_SRC2 = _zz_104; + assign execute_SRC1 = _zz_99; assign execute_ALU_BITWISE_CTRL = _zz_43; assign _zz_44 = writeBack_INSTRUCTION; assign _zz_45 = writeBack_REGFILE_WRITE_VALID; @@ -2349,13 +2287,12 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_208[0]; + decode_REGFILE_WRITE_VALID = _zz_202[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_280) == 32'h00000003),{(_zz_281 == _zz_282),{_zz_283,{_zz_284,_zz_285}}}}}}} != 21'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin _zz_55 = writeBack_REGFILE_WRITE_DATA; @@ -2378,7 +2315,6 @@ module VexRiscv ( assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; assign memory_PC = execute_to_memory_PC; - assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; @@ -2397,8 +2333,8 @@ module VexRiscv ( assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_209[0]; + assign execute_ALIGNEMENT_FAULT = 1'b0; + assign decode_MEMORY_ENABLE = _zz_203[0]; always @ (*) begin _zz_56 = execute_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin @@ -2422,7 +2358,7 @@ module VexRiscv ( if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_139) + case(_zz_136) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2433,7 +2369,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_105 || _zz_106)))begin + if((decode_arbitration_isValid && (_zz_106 || _zz_107)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2446,7 +2382,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_160)begin + if(IBusSimplePlugin_decodeExceptionPort_valid)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2457,7 +2393,7 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(_zz_160)begin + if(IBusSimplePlugin_decodeExceptionPort_valid)begin decode_arbitration_flushNext = 1'b1; end end @@ -2467,12 +2403,12 @@ module VexRiscv ( if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_73)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_158)begin + if(_zz_155)begin if((! execute_LightShifterPlugin_done))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_159)begin + if(_zz_156)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2484,14 +2420,14 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_161)begin + if(_zz_157)begin execute_arbitration_haltByOther = 1'b1; end end always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_162)begin + if(CsrPlugin_selfException_valid)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -2501,8 +2437,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_161)begin - if(_zz_163)begin + if(_zz_157)begin + if(_zz_158)begin execute_arbitration_flushIt = 1'b1; end end @@ -2513,11 +2449,11 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_162)begin + if(CsrPlugin_selfException_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_161)begin - if(_zz_163)begin + if(_zz_157)begin + if(_zz_158)begin execute_arbitration_flushNext = 1'b1; end end @@ -2533,15 +2469,15 @@ module VexRiscv ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_156)begin + if(_zz_153)begin if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_164)begin + if(_zz_159)begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_157)begin + if(_zz_154)begin if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2551,7 +2487,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_165)begin + if(_zz_160)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2571,7 +2507,7 @@ module VexRiscv ( if(DBusSimplePlugin_redoBranch_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_165)begin + if(_zz_160)begin memory_arbitration_flushNext = 1'b1; end end @@ -2588,10 +2524,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_166)begin + if(_zz_161)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_167)begin + if(_zz_162)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2605,21 +2541,21 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_166)begin + if(_zz_161)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_167)begin + if(_zz_162)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_161)begin - if(_zz_163)begin + if(_zz_157)begin + if(_zz_158)begin IBusSimplePlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_168)begin + if(_zz_163)begin IBusSimplePlugin_fetcherHalt = 1'b1; end end @@ -2644,21 +2580,21 @@ module VexRiscv ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_166)begin + if(_zz_161)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_167)begin + if(_zz_162)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_166)begin + if(_zz_161)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_167)begin - case(_zz_169) + if(_zz_162)begin + case(_zz_164) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2692,10 +2628,10 @@ module VexRiscv ( assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); assign _zz_58 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_59 = (_zz_58 & (~ _zz_210)); + assign _zz_59 = (_zz_58 & (~ _zz_204)); assign _zz_60 = _zz_59[1]; assign _zz_61 = _zz_59[2]; - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_155; + assign IBusSimplePlugin_jump_pcLoad_payload = _zz_152; always @ (*) begin IBusSimplePlugin_fetchPc_correction = 1'b0; if(IBusSimplePlugin_fetchPc_redo_valid)begin @@ -2715,7 +2651,7 @@ module VexRiscv ( end always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_212); + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_206); if(IBusSimplePlugin_fetchPc_redo_valid)begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; end @@ -2803,7 +2739,7 @@ module VexRiscv ( assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; - case(_zz_139) + case(_zz_136) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -2818,7 +2754,7 @@ module VexRiscv ( assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pending_next = (_zz_213 - _zz_217); + assign IBusSimplePlugin_pending_next = (_zz_207 - _zz_211); assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); always @ (*) begin IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); @@ -2842,8 +2778,8 @@ module VexRiscv ( assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - assign _zz_151 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); - assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_151); + assign _zz_148 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_148); assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; always @ (*) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; @@ -2855,7 +2791,7 @@ module VexRiscv ( assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; always @ (*) begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_170)begin + if(_zz_165)begin IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; end end @@ -2876,7 +2812,7 @@ module VexRiscv ( assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; always @ (*) begin IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_170)begin + if(_zz_165)begin IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; end end @@ -2935,12 +2871,6 @@ module VexRiscv ( assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_171)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end else begin @@ -2948,19 +2878,13 @@ module VexRiscv ( DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_172)begin + if(_zz_166)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_171)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; - end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_222}; - end if(! memory_MMU_RSP2_refilling) begin if(memory_MMU_FAULT)begin DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); @@ -2974,7 +2898,7 @@ module VexRiscv ( if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_172)begin + if(_zz_166)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -3048,7 +2972,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_191) + case(_zz_185) 2'b00 : begin writeBack_DBusSimplePlugin_rspFormated = _zz_77; end @@ -3080,53 +3004,51 @@ module VexRiscv ( assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; assign _zz_81 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_82 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_83 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_84 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_85 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_86 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); - assign _zz_87 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); - assign _zz_80 = {(((decode_INSTRUCTION & _zz_298) == 32'h00100050) != 1'b0),{((_zz_299 == _zz_300) != 1'b0),{({_zz_301,_zz_302} != 2'b00),{(_zz_303 != _zz_304),{_zz_305,{_zz_306,_zz_307}}}}}}; - assign _zz_88 = _zz_80[1 : 0]; - assign _zz_54 = _zz_88; - assign _zz_89 = _zz_80[6 : 5]; - assign _zz_53 = _zz_89; - assign _zz_90 = _zz_80[8 : 7]; - assign _zz_52 = _zz_90; - assign _zz_91 = _zz_80[17 : 16]; - assign _zz_51 = _zz_91; - assign _zz_92 = _zz_80[20 : 19]; - assign _zz_50 = _zz_92; - assign _zz_93 = _zz_80[22 : 21]; - assign _zz_49 = _zz_93; - assign _zz_94 = _zz_80[25 : 24]; - assign _zz_48 = _zz_94; - assign _zz_95 = _zz_80[27 : 27]; - assign _zz_47 = _zz_95; - assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); - assign decodeExceptionPort_payload_code = 4'b0010; - assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign _zz_82 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_83 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_84 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_85 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_86 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_87 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); + assign _zz_88 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); + assign _zz_80 = {(((decode_INSTRUCTION & _zz_269) == 32'h00100050) != 1'b0),{((_zz_270 == _zz_271) != 1'b0),{({_zz_272,_zz_273} != 2'b00),{(_zz_274 != _zz_275),{_zz_276,{_zz_277,_zz_278}}}}}}; + assign _zz_89 = _zz_80[1 : 0]; + assign _zz_54 = _zz_89; + assign _zz_90 = _zz_80[6 : 5]; + assign _zz_53 = _zz_90; + assign _zz_91 = _zz_80[13 : 12]; + assign _zz_52 = _zz_91; + assign _zz_92 = _zz_80[16 : 15]; + assign _zz_51 = _zz_92; + assign _zz_93 = _zz_80[19 : 18]; + assign _zz_50 = _zz_93; + assign _zz_94 = _zz_80[22 : 21]; + assign _zz_49 = _zz_94; + assign _zz_95 = _zz_80[25 : 24]; + assign _zz_48 = _zz_95; + assign _zz_96 = _zz_80[27 : 27]; + assign _zz_47 = _zz_96; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_153; - assign decode_RegFilePlugin_rs2Data = _zz_154; + assign decode_RegFilePlugin_rs1Data = _zz_150; + assign decode_RegFilePlugin_rs2Data = _zz_151; always @ (*) begin lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); - if(_zz_96)begin + if(_zz_97)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; - if(_zz_96)begin + if(_zz_97)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin lastStageRegFileWrite_payload_data = _zz_55; - if(_zz_96)begin + if(_zz_97)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -3148,13 +3070,13 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_97 = execute_IntAluPlugin_bitwise; + _zz_98 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_97 = {31'd0, _zz_223}; + _zz_98 = {31'd0, _zz_216}; end default : begin - _zz_97 = execute_SRC_ADD_SUB; + _zz_98 = execute_SRC_ADD_SUB; end endcase end @@ -3162,87 +3084,87 @@ module VexRiscv ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_98 = execute_RS1; + _zz_99 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_98 = {29'd0, _zz_224}; + _zz_99 = {29'd0, _zz_217}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_98 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_99 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_98 = {27'd0, _zz_225}; + _zz_99 = {27'd0, _zz_218}; end endcase end - assign _zz_99 = _zz_226[11]; + assign _zz_100 = _zz_219[11]; always @ (*) begin - _zz_100[19] = _zz_99; - _zz_100[18] = _zz_99; - _zz_100[17] = _zz_99; - _zz_100[16] = _zz_99; - _zz_100[15] = _zz_99; - _zz_100[14] = _zz_99; - _zz_100[13] = _zz_99; - _zz_100[12] = _zz_99; - _zz_100[11] = _zz_99; - _zz_100[10] = _zz_99; - _zz_100[9] = _zz_99; - _zz_100[8] = _zz_99; - _zz_100[7] = _zz_99; - _zz_100[6] = _zz_99; - _zz_100[5] = _zz_99; - _zz_100[4] = _zz_99; - _zz_100[3] = _zz_99; - _zz_100[2] = _zz_99; - _zz_100[1] = _zz_99; - _zz_100[0] = _zz_99; - end - - assign _zz_101 = _zz_227[11]; + _zz_101[19] = _zz_100; + _zz_101[18] = _zz_100; + _zz_101[17] = _zz_100; + _zz_101[16] = _zz_100; + _zz_101[15] = _zz_100; + _zz_101[14] = _zz_100; + _zz_101[13] = _zz_100; + _zz_101[12] = _zz_100; + _zz_101[11] = _zz_100; + _zz_101[10] = _zz_100; + _zz_101[9] = _zz_100; + _zz_101[8] = _zz_100; + _zz_101[7] = _zz_100; + _zz_101[6] = _zz_100; + _zz_101[5] = _zz_100; + _zz_101[4] = _zz_100; + _zz_101[3] = _zz_100; + _zz_101[2] = _zz_100; + _zz_101[1] = _zz_100; + _zz_101[0] = _zz_100; + end + + assign _zz_102 = _zz_220[11]; always @ (*) begin - _zz_102[19] = _zz_101; - _zz_102[18] = _zz_101; - _zz_102[17] = _zz_101; - _zz_102[16] = _zz_101; - _zz_102[15] = _zz_101; - _zz_102[14] = _zz_101; - _zz_102[13] = _zz_101; - _zz_102[12] = _zz_101; - _zz_102[11] = _zz_101; - _zz_102[10] = _zz_101; - _zz_102[9] = _zz_101; - _zz_102[8] = _zz_101; - _zz_102[7] = _zz_101; - _zz_102[6] = _zz_101; - _zz_102[5] = _zz_101; - _zz_102[4] = _zz_101; - _zz_102[3] = _zz_101; - _zz_102[2] = _zz_101; - _zz_102[1] = _zz_101; - _zz_102[0] = _zz_101; + _zz_103[19] = _zz_102; + _zz_103[18] = _zz_102; + _zz_103[17] = _zz_102; + _zz_103[16] = _zz_102; + _zz_103[15] = _zz_102; + _zz_103[14] = _zz_102; + _zz_103[13] = _zz_102; + _zz_103[12] = _zz_102; + _zz_103[11] = _zz_102; + _zz_103[10] = _zz_102; + _zz_103[9] = _zz_102; + _zz_103[8] = _zz_102; + _zz_103[7] = _zz_102; + _zz_103[6] = _zz_102; + _zz_103[5] = _zz_102; + _zz_103[4] = _zz_102; + _zz_103[3] = _zz_102; + _zz_103[2] = _zz_102; + _zz_103[1] = _zz_102; + _zz_103[0] = _zz_102; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_103 = execute_RS2; + _zz_104 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_103 = {_zz_100,execute_INSTRUCTION[31 : 20]}; + _zz_104 = {_zz_101,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_103 = {_zz_102,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_104 = {_zz_103,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_103 = _zz_39; + _zz_104 = _zz_39; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_228; + execute_SrcPlugin_addSub = _zz_221; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3256,201 +3178,192 @@ module VexRiscv ( always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_104 = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_105 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_104 = _zz_235; + _zz_105 = _zz_228; end endcase end always @ (*) begin - _zz_105 = 1'b0; - if(_zz_107)begin - if((_zz_108 == decode_INSTRUCTION[19 : 15]))begin - _zz_105 = 1'b1; + _zz_106 = 1'b0; + if(_zz_108)begin + if((_zz_109 == decode_INSTRUCTION[19 : 15]))begin + _zz_106 = 1'b1; end end - if(_zz_173)begin - if(_zz_174)begin + if(_zz_167)begin + if(_zz_168)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_105 = 1'b1; + _zz_106 = 1'b1; end end end - if(_zz_175)begin - if(_zz_176)begin + if(_zz_169)begin + if(_zz_170)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_105 = 1'b1; + _zz_106 = 1'b1; end end end - if(_zz_177)begin - if(_zz_178)begin + if(_zz_171)begin + if(_zz_172)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_105 = 1'b1; + _zz_106 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_105 = 1'b0; + _zz_106 = 1'b0; end end always @ (*) begin - _zz_106 = 1'b0; - if(_zz_107)begin - if((_zz_108 == decode_INSTRUCTION[24 : 20]))begin - _zz_106 = 1'b1; + _zz_107 = 1'b0; + if(_zz_108)begin + if((_zz_109 == decode_INSTRUCTION[24 : 20]))begin + _zz_107 = 1'b1; end end - if(_zz_173)begin - if(_zz_174)begin + if(_zz_167)begin + if(_zz_168)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_106 = 1'b1; + _zz_107 = 1'b1; end end end - if(_zz_175)begin - if(_zz_176)begin + if(_zz_169)begin + if(_zz_170)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_106 = 1'b1; + _zz_107 = 1'b1; end end end - if(_zz_177)begin - if(_zz_178)begin + if(_zz_171)begin + if(_zz_172)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_106 = 1'b1; + _zz_107 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_106 = 1'b0; + _zz_107 = 1'b0; end end assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_109 = execute_INSTRUCTION[14 : 12]; + assign _zz_110 = execute_INSTRUCTION[14 : 12]; always @ (*) begin - if((_zz_109 == 3'b000)) begin - _zz_110 = execute_BranchPlugin_eq; - end else if((_zz_109 == 3'b001)) begin - _zz_110 = (! execute_BranchPlugin_eq); - end else if((((_zz_109 & 3'b101) == 3'b101))) begin - _zz_110 = (! execute_SRC_LESS); + if((_zz_110 == 3'b000)) begin + _zz_111 = execute_BranchPlugin_eq; + end else if((_zz_110 == 3'b001)) begin + _zz_111 = (! execute_BranchPlugin_eq); + end else if((((_zz_110 & 3'b101) == 3'b101))) begin + _zz_111 = (! execute_SRC_LESS); end else begin - _zz_110 = execute_SRC_LESS; + _zz_111 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_111 = 1'b0; + _zz_112 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_111 = 1'b1; + _zz_112 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_111 = 1'b1; + _zz_112 = 1'b1; end default : begin - _zz_111 = _zz_110; + _zz_112 = _zz_111; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_112 = _zz_237[19]; + assign _zz_113 = _zz_230[19]; always @ (*) begin - _zz_113[10] = _zz_112; - _zz_113[9] = _zz_112; - _zz_113[8] = _zz_112; - _zz_113[7] = _zz_112; - _zz_113[6] = _zz_112; - _zz_113[5] = _zz_112; - _zz_113[4] = _zz_112; - _zz_113[3] = _zz_112; - _zz_113[2] = _zz_112; - _zz_113[1] = _zz_112; - _zz_113[0] = _zz_112; - end - - assign _zz_114 = _zz_238[11]; + _zz_114[10] = _zz_113; + _zz_114[9] = _zz_113; + _zz_114[8] = _zz_113; + _zz_114[7] = _zz_113; + _zz_114[6] = _zz_113; + _zz_114[5] = _zz_113; + _zz_114[4] = _zz_113; + _zz_114[3] = _zz_113; + _zz_114[2] = _zz_113; + _zz_114[1] = _zz_113; + _zz_114[0] = _zz_113; + end + + assign _zz_115 = _zz_231[11]; always @ (*) begin - _zz_115[19] = _zz_114; - _zz_115[18] = _zz_114; - _zz_115[17] = _zz_114; - _zz_115[16] = _zz_114; - _zz_115[15] = _zz_114; - _zz_115[14] = _zz_114; - _zz_115[13] = _zz_114; - _zz_115[12] = _zz_114; - _zz_115[11] = _zz_114; - _zz_115[10] = _zz_114; - _zz_115[9] = _zz_114; - _zz_115[8] = _zz_114; - _zz_115[7] = _zz_114; - _zz_115[6] = _zz_114; - _zz_115[5] = _zz_114; - _zz_115[4] = _zz_114; - _zz_115[3] = _zz_114; - _zz_115[2] = _zz_114; - _zz_115[1] = _zz_114; - _zz_115[0] = _zz_114; - end - - assign _zz_116 = _zz_239[11]; + _zz_116[19] = _zz_115; + _zz_116[18] = _zz_115; + _zz_116[17] = _zz_115; + _zz_116[16] = _zz_115; + _zz_116[15] = _zz_115; + _zz_116[14] = _zz_115; + _zz_116[13] = _zz_115; + _zz_116[12] = _zz_115; + _zz_116[11] = _zz_115; + _zz_116[10] = _zz_115; + _zz_116[9] = _zz_115; + _zz_116[8] = _zz_115; + _zz_116[7] = _zz_115; + _zz_116[6] = _zz_115; + _zz_116[5] = _zz_115; + _zz_116[4] = _zz_115; + _zz_116[3] = _zz_115; + _zz_116[2] = _zz_115; + _zz_116[1] = _zz_115; + _zz_116[0] = _zz_115; + end + + assign _zz_117 = _zz_232[11]; always @ (*) begin - _zz_117[18] = _zz_116; - _zz_117[17] = _zz_116; - _zz_117[16] = _zz_116; - _zz_117[15] = _zz_116; - _zz_117[14] = _zz_116; - _zz_117[13] = _zz_116; - _zz_117[12] = _zz_116; - _zz_117[11] = _zz_116; - _zz_117[10] = _zz_116; - _zz_117[9] = _zz_116; - _zz_117[8] = _zz_116; - _zz_117[7] = _zz_116; - _zz_117[6] = _zz_116; - _zz_117[5] = _zz_116; - _zz_117[4] = _zz_116; - _zz_117[3] = _zz_116; - _zz_117[2] = _zz_116; - _zz_117[1] = _zz_116; - _zz_117[0] = _zz_116; + _zz_118[18] = _zz_117; + _zz_118[17] = _zz_117; + _zz_118[16] = _zz_117; + _zz_118[15] = _zz_117; + _zz_118[14] = _zz_117; + _zz_118[13] = _zz_117; + _zz_118[12] = _zz_117; + _zz_118[11] = _zz_117; + _zz_118[10] = _zz_117; + _zz_118[9] = _zz_117; + _zz_118[8] = _zz_117; + _zz_118[7] = _zz_117; + _zz_118[6] = _zz_117; + _zz_118[5] = _zz_117; + _zz_118[4] = _zz_117; + _zz_118[3] = _zz_117; + _zz_118[2] = _zz_117; + _zz_118[1] = _zz_117; + _zz_118[0] = _zz_117; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_118 = {{_zz_113,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_119 = {{_zz_114,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_118 = {_zz_115,execute_INSTRUCTION[31 : 20]}; + _zz_119 = {_zz_116,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_118 = {{_zz_117,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_119 = {{_zz_118,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_118; + assign execute_BranchPlugin_branch_src2 = _zz_119; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; - always @ (*) begin - BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); - if(1'b0)begin - BranchPlugin_branchExceptionPort_valid = 1'b0; - end - end - - assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; - assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; always @ (*) begin CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin @@ -3460,20 +3373,16 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_119 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_120 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_121 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_120 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_121 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_122 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_122 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; - assign _zz_123 = _zz_240[0]; - assign _zz_124 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_125 = _zz_242[0]; - assign _zz_126 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_127 = _zz_244[0]; + assign _zz_123 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_124 = _zz_233[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_160)begin + if(IBusSimplePlugin_decodeExceptionPort_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3483,7 +3392,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_162)begin + if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -3493,7 +3402,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_165)begin + if(_zz_160)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3611,7 +3520,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_179)begin + if(_zz_173)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3630,14 +3539,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_180)begin + if(_zz_174)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_180)begin + if(_zz_174)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3652,14 +3561,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_179)begin + if(_zz_173)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_179)begin + if(_zz_173)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -3668,7 +3577,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_192) + case(_zz_186) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3681,49 +3590,49 @@ module VexRiscv ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_246; + assign execute_CfuPlugin_functionsIds_0 = _zz_235; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_128 = _zz_247[7]; + assign _zz_125 = _zz_236[7]; always @ (*) begin - _zz_129[23] = _zz_128; - _zz_129[22] = _zz_128; - _zz_129[21] = _zz_128; - _zz_129[20] = _zz_128; - _zz_129[19] = _zz_128; - _zz_129[18] = _zz_128; - _zz_129[17] = _zz_128; - _zz_129[16] = _zz_128; - _zz_129[15] = _zz_128; - _zz_129[14] = _zz_128; - _zz_129[13] = _zz_128; - _zz_129[12] = _zz_128; - _zz_129[11] = _zz_128; - _zz_129[10] = _zz_128; - _zz_129[9] = _zz_128; - _zz_129[8] = _zz_128; - _zz_129[7] = _zz_128; - _zz_129[6] = _zz_128; - _zz_129[5] = _zz_128; - _zz_129[4] = _zz_128; - _zz_129[3] = _zz_128; - _zz_129[2] = _zz_128; - _zz_129[1] = _zz_128; - _zz_129[0] = _zz_128; + _zz_126[23] = _zz_125; + _zz_126[22] = _zz_125; + _zz_126[21] = _zz_125; + _zz_126[20] = _zz_125; + _zz_126[19] = _zz_125; + _zz_126[18] = _zz_125; + _zz_126[17] = _zz_125; + _zz_126[16] = _zz_125; + _zz_126[15] = _zz_125; + _zz_126[14] = _zz_125; + _zz_126[13] = _zz_125; + _zz_126[12] = _zz_125; + _zz_126[11] = _zz_125; + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_130 = execute_RS2; + _zz_127 = execute_RS2; end default : begin - _zz_130 = {_zz_129,execute_INSTRUCTION[31 : 24]}; + _zz_127 = {_zz_126,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_130; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_127; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -3749,8 +3658,8 @@ module VexRiscv ( assign memory_MulDivIterativePlugin_frontendOk = 1'b1; always @ (*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_156)begin - if(_zz_164)begin + if(_zz_153)begin + if(_zz_159)begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end @@ -3769,7 +3678,7 @@ module VexRiscv ( if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_249); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_238); end if(memory_MulDivIterativePlugin_mul_counter_willClear)begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; @@ -3778,8 +3687,8 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_157)begin - if(_zz_181)begin + if(_zz_154)begin + if(_zz_175)begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end @@ -3787,7 +3696,7 @@ module VexRiscv ( always @ (*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_182)begin + if(_zz_176)begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end @@ -3798,32 +3707,32 @@ module VexRiscv ( if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_257); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_246); end if(memory_MulDivIterativePlugin_div_counter_willClear)begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end end - assign _zz_131 = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_131[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_258); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_259 : _zz_260); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_261[31:0]; - assign _zz_132 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_133 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_134 = ((execute_IS_MUL && _zz_133) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_128 = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_128[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_247); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_248 : _zz_249); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_250[31:0]; + assign _zz_129 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign _zz_130 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_131 = ((execute_IS_MUL && _zz_130) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_135[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_135[31 : 0] = execute_RS1; + _zz_132[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_132[31 : 0] = execute_RS1; end - assign _zz_137 = (_zz_136 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_137 != 32'h0); + assign _zz_134 = (_zz_133 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_134 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_183) + case(_zz_177) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusSimplePlugin_injectionPort_ready; @@ -3837,7 +3746,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_138))begin + if((! _zz_135))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -3849,7 +3758,7 @@ module VexRiscv ( always @ (*) begin IBusSimplePlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_183) + case(_zz_177) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusSimplePlugin_injectionPort_valid = 1'b1; @@ -3867,12 +3776,12 @@ module VexRiscv ( assign _zz_28 = decode_SRC1_CTRL; assign _zz_26 = _zz_54; assign _zz_41 = decode_to_execute_SRC1_CTRL; - assign _zz_25 = decode_ALU_CTRL; + assign _zz_25 = decode_SRC2_CTRL; assign _zz_23 = _zz_53; - assign _zz_42 = decode_to_execute_ALU_CTRL; - assign _zz_22 = decode_SRC2_CTRL; - assign _zz_20 = _zz_52; assign _zz_40 = decode_to_execute_SRC2_CTRL; + assign _zz_22 = decode_ALU_CTRL; + assign _zz_20 = _zz_52; + assign _zz_42 = decode_to_execute_ALU_CTRL; assign _zz_19 = decode_ALU_BITWISE_CTRL; assign _zz_17 = _zz_51; assign _zz_43 = decode_to_execute_ALU_BITWISE_CTRL; @@ -3914,7 +3823,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusSimplePlugin_injectionPort_ready = 1'b0; - case(_zz_139) + case(_zz_136) 3'b100 : begin IBusSimplePlugin_injectionPort_ready = 1'b1; end @@ -3924,83 +3833,83 @@ module VexRiscv ( end always @ (*) begin - _zz_140 = 32'h0; + _zz_137 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_140[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_140[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_140[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_137[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_137[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_137[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_141 = 32'h0; + _zz_138 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_141[11 : 11] = CsrPlugin_mip_MEIP; - _zz_141[7 : 7] = CsrPlugin_mip_MTIP; - _zz_141[3 : 3] = CsrPlugin_mip_MSIP; + _zz_138[11 : 11] = CsrPlugin_mip_MEIP; + _zz_138[7 : 7] = CsrPlugin_mip_MTIP; + _zz_138[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_142 = 32'h0; + _zz_139 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_142[11 : 11] = CsrPlugin_mie_MEIE; - _zz_142[7 : 7] = CsrPlugin_mie_MTIE; - _zz_142[3 : 3] = CsrPlugin_mie_MSIE; + _zz_139[11 : 11] = CsrPlugin_mie_MEIE; + _zz_139[7 : 7] = CsrPlugin_mie_MTIE; + _zz_139[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_143 = 32'h0; + _zz_140 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_143[31 : 0] = CsrPlugin_mepc; + _zz_140[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_144 = 32'h0; + _zz_141 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_144[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_144[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_141[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_141[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_145 = 32'h0; + _zz_142 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_145[31 : 0] = CsrPlugin_mtval; + _zz_142[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_146 = 32'h0; + _zz_143 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_146[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_143[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_147 = 32'h0; + _zz_144 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_147[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_144[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_148 = 32'h0; + _zz_145 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_148[31 : 0] = _zz_136; + _zz_145[31 : 0] = _zz_133; end end always @ (*) begin - _zz_149 = 32'h0; + _zz_146 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_149[31 : 0] = _zz_137; + _zz_146[31 : 0] = _zz_134; end end - assign execute_CsrPlugin_readData = ((((_zz_140 | _zz_141) | (_zz_142 | _zz_143)) | ((_zz_144 | _zz_145) | (_zz_146 | _zz_147))) | (_zz_148 | _zz_149)); + assign execute_CsrPlugin_readData = ((((_zz_137 | _zz_138) | (_zz_139 | _zz_140)) | ((_zz_141 | _zz_142) | (_zz_143 | _zz_144))) | (_zz_145 | _zz_146)); assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; @@ -4028,19 +3937,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_150 = 4'b0001; + _zz_147 = 4'b0001; end 2'b01 : begin - _zz_150 = 4'b0011; + _zz_147 = 4'b0011; end default : begin - _zz_150 = 4'b1111; + _zz_147 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_150 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_147 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -4054,7 +3963,7 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - assign _zz_152 = 1'b0; + assign _zz_149 = 1'b0; always @ (posedge clk) begin if(reset) begin IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; @@ -4070,9 +3979,9 @@ module VexRiscv ( IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; IBusSimplePlugin_pending_value <= 3'b000; IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; - _zz_96 <= 1'b1; + _zz_97 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_107 <= 1'b0; + _zz_108 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -4094,11 +4003,11 @@ module VexRiscv ( CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - _zz_136 <= 32'h0; + _zz_133 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_139 <= 3'b000; + _zz_136 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; iBus_cmd_m2sPipe_rValid <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; @@ -4178,9 +4087,9 @@ module VexRiscv ( IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_219); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_213); if(IBusSimplePlugin_iBusRsp_flush)begin - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_221); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_215); end `ifndef SYNTHESIS `ifdef FORMAL @@ -4202,9 +4111,9 @@ module VexRiscv ( end `endif `endif - _zz_96 <= 1'b0; - if(_zz_158)begin - if(_zz_184)begin + _zz_97 <= 1'b0; + if(_zz_155)begin + if(_zz_178)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -4214,7 +4123,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_107 <= (_zz_45 && writeBack_arbitration_isFiring); + _zz_108 <= (_zz_45 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4236,14 +4145,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_185)begin - if(_zz_186)begin + if(_zz_179)begin + if(_zz_180)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_187)begin + if(_zz_181)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_188)begin + if(_zz_182)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4267,7 +4176,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_166)begin + if(_zz_161)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4278,8 +4187,8 @@ module VexRiscv ( end endcase end - if(_zz_167)begin - case(_zz_169) + if(_zz_162)begin + case(_zz_164) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4289,7 +4198,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_121,{_zz_120,_zz_119}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_122,{_zz_121,_zz_120}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -4305,7 +4214,7 @@ module VexRiscv ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_189)begin + if(_zz_183)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; @@ -4331,25 +4240,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_139) + case(_zz_136) 3'b000 : begin if(IBusSimplePlugin_injectionPort_valid)begin - _zz_139 <= 3'b001; + _zz_136 <= 3'b001; end end 3'b001 : begin - _zz_139 <= 3'b010; + _zz_136 <= 3'b010; end 3'b010 : begin - _zz_139 <= 3'b011; + _zz_136 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_139 <= 3'b100; + _zz_136 <= 3'b100; end end 3'b100 : begin - _zz_139 <= 3'b000; + _zz_136 <= 3'b000; end default : begin end @@ -4357,26 +4266,26 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_271[0]; - CsrPlugin_mstatus_MIE <= _zz_272[0]; + CsrPlugin_mstatus_MPIE <= _zz_260[0]; + CsrPlugin_mstatus_MIE <= _zz_261[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_274[0]; - CsrPlugin_mie_MTIE <= _zz_275[0]; - CsrPlugin_mie_MSIE <= _zz_276[0]; + CsrPlugin_mie_MEIE <= _zz_263[0]; + CsrPlugin_mie_MTIE <= _zz_264[0]; + CsrPlugin_mie_MSIE <= _zz_265[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_136 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_133 <= execute_CsrPlugin_writeData[31 : 0]; end end if(iBus_cmd_ready)begin iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; end - if(_zz_190)begin + if(_zz_184)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -4407,12 +4316,12 @@ module VexRiscv ( IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; end - if(_zz_158)begin - if(_zz_184)begin + if(_zz_155)begin + if(_zz_178)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - _zz_108 <= _zz_44[11 : 7]; + _zz_109 <= _zz_44[11 : 7]; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -4420,33 +4329,33 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_160)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_123 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_123 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(IBusSimplePlugin_decodeExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= IBusSimplePlugin_decodeExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= IBusSimplePlugin_decodeExceptionPort_payload_badAddr; end - if(_zz_162)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_127 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_127 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_165)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_125 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_125 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(_zz_160)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_124 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_124 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); end - if(_zz_185)begin - if(_zz_186)begin + if(_zz_179)begin + if(_zz_180)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_187)begin + if(_zz_181)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_188)begin + if(_zz_182)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_166)begin + if(_zz_161)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4460,14 +4369,14 @@ module VexRiscv ( end endcase end - if(_zz_189)begin + if(_zz_183)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end - if(_zz_156)begin - if(_zz_164)begin + if(_zz_153)begin + if(_zz_159)begin memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_250,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_239,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin @@ -4476,20 +4385,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_MulDivIterativePlugin_div_done <= 1'b0; end - if(_zz_157)begin - if(_zz_181)begin + if(_zz_154)begin + if(_zz_175)begin memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_result <= _zz_262[31:0]; + memory_MulDivIterativePlugin_div_result <= _zz_251[31:0]; end end end - if(_zz_182)begin + if(_zz_176)begin memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_134 ? (~ _zz_135) : _zz_135) + _zz_268); - memory_MulDivIterativePlugin_rs2 <= ((_zz_133 ? (~ execute_RS2) : execute_RS2) + _zz_270); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_134 ^ (_zz_133 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_MulDivIterativePlugin_rs1 <= ((_zz_131 ? (~ _zz_132) : _zz_132) + _zz_257); + memory_MulDivIterativePlugin_rs2 <= ((_zz_130 ? (~ execute_RS2) : execute_RS2) + _zz_259); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_131 ^ (_zz_130 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -4535,10 +4444,7 @@ module VexRiscv ( memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_24; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_21; + decode_to_execute_SRC2_CTRL <= _zz_24; end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; @@ -4567,6 +4473,9 @@ module VexRiscv ( if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_21; + end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end @@ -4633,9 +4542,6 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; - end if((! memory_arbitration_isStuck))begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end @@ -4668,7 +4574,7 @@ module VexRiscv ( if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end - if((_zz_139 != 3'b000))begin + if((_zz_136 != 3'b000))begin _zz_70 <= IBusSimplePlugin_injectionPort_payload; end if((! execute_arbitration_isStuck))begin @@ -4706,7 +4612,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_273[0]; + CsrPlugin_mip_MSIP <= _zz_262[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -4723,7 +4629,7 @@ module VexRiscv ( if(iBus_cmd_ready)begin iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; end - if(_zz_190)begin + if(_zz_184)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; @@ -4741,8 +4647,8 @@ module VexRiscv ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_55; end - _zz_138 <= debug_bus_cmd_payload_address[2]; - if(_zz_161)begin + _zz_135 <= debug_bus_cmd_payload_address[2]; + if(_zz_157)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -4760,7 +4666,7 @@ module VexRiscv ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_183) + case(_zz_177) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -4788,13 +4694,13 @@ module VexRiscv ( end endcase end - if(_zz_161)begin - if(_zz_163)begin + if(_zz_157)begin + if(_zz_158)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_168)begin + if(_zz_163)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index 9edf0fe..a1097b3 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -23,6 +23,7 @@ object SpinalConfig extends spinal.core.SpinalConfig( case class ArgConfig( debug : Boolean = false, + safe : Boolean = true, iCacheSize : Int = 4096, dCacheSize : Int = 4096, mulDiv : Boolean = true, @@ -65,6 +66,7 @@ object GenCoreDefault{ opt[Int]("dCacheSize") action { (v, c) => c.copy(dCacheSize = v) } text("Set data cache size, 0 mean no cache") opt[Boolean]("mulDiv") action { (v, c) => c.copy(mulDiv = v) } text("set RV32IM") opt[Boolean]("cfu") action { (v, c) => c.copy(cfu = v) } text("If true, add SIMD ADD custom function unit") + opt[Boolean]("safe") action { (v, c) => c.copy(safe = v) } text("Default true; if false, disable many checks.") opt[Int]("perfCSRs") action { (v, c) => c.copy(perfCSRs = v) } text("Number of pausable performance counter CSRs to add (default 0)") opt[Boolean]("atomics") action { (v, c) => c.copy(mulDiv = v) } text("set RV32I[A]") opt[Boolean]("compressedGen") action { (v, c) => c.copy(compressedGen = v) } text("set RV32I[C]") @@ -112,8 +114,8 @@ object GenCoreDefault{ addressWidth = 32, cpuDataWidth = 32, memDataWidth = 32, - catchIllegalAccess = true, - catchAccessFault = true, + catchIllegalAccess = argConfig.safe, + catchAccessFault = argConfig.safe, asyncTagMemory = false, twoCycleRam = false, twoCycleCache = !argConfig.compressedGen @@ -123,8 +125,8 @@ object GenCoreDefault{ if(argConfig.dCacheSize <= 0){ new DBusSimplePlugin( - catchAddressMisaligned = true, - catchAccessFault = true, + catchAddressMisaligned = argConfig.safe, + catchAccessFault = argConfig.safe, withLrSc = linux || argConfig.atomics, memoryTranslatorPortConfig = if(linux) MmuPortConfig(portTlbSize = 4) ) @@ -158,7 +160,7 @@ object GenCoreDefault{ ioRange = _.msb ), new DecoderSimplePlugin( - catchIllegalInstruction = true + catchIllegalInstruction = argConfig.safe ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, @@ -186,7 +188,7 @@ object GenCoreDefault{ new BranchPlugin( // If using CFU, use earlyBranch to avoid incorrect CFU execution earlyBranch = argConfig.cfu, - catchAddressMisaligned = true + catchAddressMisaligned = argConfig.safe ), new CsrPlugin( argConfig.csrPluginConfig match { From 9188280a1849281e1aa648799464f334e11b7217 Mon Sep 17 00:00:00 2001 From: Joey Bushagour Date: Mon, 19 Jul 2021 17:23:13 -0500 Subject: [PATCH 20/30] Tweak the Fomu variant to remove division, debug, and writeback/memory stages. --- pythondata_cpu_vexriscv/verilog/Makefile | 4 +- .../verilog/VexRiscv_Fomu.v | 4464 +++++++-------- .../verilog/VexRiscv_Fomu.yaml | 5 +- .../verilog/VexRiscv_FomuCfu.v | 5074 +++++++---------- .../verilog/VexRiscv_FomuCfu.yaml | 5 +- .../main/scala/vexriscv/GenCoreDefault.scala | 18 +- 6 files changed, 4046 insertions(+), 5524 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index 9c4c5fc..beeba80 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -27,10 +27,10 @@ VexRiscv_MinDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 0 --dCacheSize 0 --mulDiv false --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_MinDebug" VexRiscv_Fomu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --safe false --iCacheSize 0 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_Fomu" + sbt compile "runMain vexriscv.GenCoreDefault --safe false --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --memoryAndWritebackStage false --outputFile VexRiscv_Fomu" VexRiscv_FomuCfu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --safe false -d --cfu true --iCacheSize 0 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_FomuCfu" + sbt compile "runMain vexriscv.GenCoreDefault --safe false --cfu true --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --memoryAndWritebackStage false --outputFile VexRiscv_FomuCfu" VexRiscv_Full.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --outputFile VexRiscv_Full" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v index 0e5d63c..233ec9c 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 848042f3e4812615884ef1061d617c4d5bf6e8c2 +// Git hash : 301554ed50130998df7c9b3fa2a900ddbefe2027 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -48,8 +48,8 @@ module VexRiscv ( input timerInterrupt, input softwareInterrupt, input [31:0] externalInterruptArray, - output iBusWishbone_CYC, - output iBusWishbone_STB, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, input iBusWishbone_ACK, output iBusWishbone_WE, output [29:0] iBusWishbone_ADR, @@ -73,21 +73,40 @@ module VexRiscv ( input clk, input reset ); + wire _zz_119; + wire _zz_120; + wire _zz_121; + wire _zz_122; + wire _zz_123; + wire _zz_124; + wire _zz_125; + wire _zz_126; + reg _zz_127; + reg [31:0] _zz_128; + reg [31:0] _zz_129; + reg [31:0] _zz_130; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; wire _zz_131; wire _zz_132; - reg [31:0] _zz_133; - reg [31:0] _zz_134; - reg [31:0] _zz_135; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; - wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_133; + wire _zz_134; + wire _zz_135; wire _zz_136; wire _zz_137; wire _zz_138; wire _zz_139; - wire _zz_140; + wire [1:0] _zz_140; wire _zz_141; wire _zz_142; wire _zz_143; @@ -100,376 +119,283 @@ module VexRiscv ( wire _zz_150; wire _zz_151; wire _zz_152; - wire _zz_153; + wire [1:0] _zz_153; wire _zz_154; - wire _zz_155; - wire _zz_156; - wire _zz_157; - wire _zz_158; - wire _zz_159; - wire _zz_160; - wire [1:0] _zz_161; - wire [1:0] _zz_162; - wire _zz_163; + wire [0:0] _zz_155; + wire [0:0] _zz_156; + wire [0:0] _zz_157; + wire [0:0] _zz_158; + wire [0:0] _zz_159; + wire [0:0] _zz_160; + wire [0:0] _zz_161; + wire [0:0] _zz_162; + wire [0:0] _zz_163; wire [0:0] _zz_164; wire [0:0] _zz_165; wire [0:0] _zz_166; wire [0:0] _zz_167; - wire [0:0] _zz_168; - wire [0:0] _zz_169; - wire [0:0] _zz_170; + wire [2:0] _zz_168; + wire [2:0] _zz_169; + wire [31:0] _zz_170; wire [0:0] _zz_171; - wire [0:0] _zz_172; - wire [0:0] _zz_173; - wire [0:0] _zz_174; - wire [0:0] _zz_175; - wire [0:0] _zz_176; - wire [0:0] _zz_177; - wire [0:0] _zz_178; - wire [2:0] _zz_179; - wire [2:0] _zz_180; + wire [2:0] _zz_172; + wire [4:0] _zz_173; + wire [11:0] _zz_174; + wire [11:0] _zz_175; + wire [31:0] _zz_176; + wire [31:0] _zz_177; + wire [31:0] _zz_178; + wire [31:0] _zz_179; + wire [31:0] _zz_180; wire [31:0] _zz_181; - wire [2:0] _zz_182; - wire [0:0] _zz_183; - wire [2:0] _zz_184; - wire [0:0] _zz_185; - wire [2:0] _zz_186; - wire [0:0] _zz_187; - wire [2:0] _zz_188; - wire [0:0] _zz_189; - wire [2:0] _zz_190; - wire [0:0] _zz_191; - wire [2:0] _zz_192; - wire [4:0] _zz_193; - wire [11:0] _zz_194; - wire [11:0] _zz_195; - wire [31:0] _zz_196; - wire [31:0] _zz_197; - wire [31:0] _zz_198; - wire [31:0] _zz_199; - wire [31:0] _zz_200; + wire [31:0] _zz_182; + wire [31:0] _zz_183; + wire [32:0] _zz_184; + wire [19:0] _zz_185; + wire [11:0] _zz_186; + wire [11:0] _zz_187; + wire [1:0] _zz_188; + wire [1:0] _zz_189; + wire [0:0] _zz_190; + wire [5:0] _zz_191; + wire [33:0] _zz_192; + wire [32:0] _zz_193; + wire [33:0] _zz_194; + wire [32:0] _zz_195; + wire [33:0] _zz_196; + wire [32:0] _zz_197; + wire [0:0] _zz_198; + wire [32:0] _zz_199; + wire [0:0] _zz_200; wire [31:0] _zz_201; - wire [31:0] _zz_202; - wire [31:0] _zz_203; - wire [32:0] _zz_204; - wire [19:0] _zz_205; - wire [11:0] _zz_206; - wire [11:0] _zz_207; - wire [0:0] _zz_208; - wire [5:0] _zz_209; - wire [33:0] _zz_210; - wire [32:0] _zz_211; - wire [33:0] _zz_212; - wire [32:0] _zz_213; - wire [33:0] _zz_214; - wire [32:0] _zz_215; + wire [0:0] _zz_202; + wire [0:0] _zz_203; + wire [0:0] _zz_204; + wire [0:0] _zz_205; + wire [0:0] _zz_206; + wire [0:0] _zz_207; + wire [26:0] _zz_208; + wire _zz_209; + wire _zz_210; + wire [1:0] _zz_211; + wire [31:0] _zz_212; + wire [31:0] _zz_213; + wire [31:0] _zz_214; + wire _zz_215; wire [0:0] _zz_216; - wire [5:0] _zz_217; - wire [32:0] _zz_218; + wire [13:0] _zz_217; + wire [31:0] _zz_218; wire [31:0] _zz_219; wire [31:0] _zz_220; - wire [32:0] _zz_221; - wire [32:0] _zz_222; - wire [32:0] _zz_223; - wire [32:0] _zz_224; - wire [0:0] _zz_225; - wire [32:0] _zz_226; - wire [0:0] _zz_227; - wire [32:0] _zz_228; - wire [0:0] _zz_229; - wire [31:0] _zz_230; + wire _zz_221; + wire [0:0] _zz_222; + wire [7:0] _zz_223; + wire [31:0] _zz_224; + wire [31:0] _zz_225; + wire [31:0] _zz_226; + wire _zz_227; + wire [0:0] _zz_228; + wire [1:0] _zz_229; + wire _zz_230; wire [0:0] _zz_231; wire [0:0] _zz_232; - wire [0:0] _zz_233; + wire _zz_233; wire [0:0] _zz_234; - wire [0:0] _zz_235; - wire [0:0] _zz_236; + wire [23:0] _zz_235; + wire [31:0] _zz_236; wire _zz_237; wire _zz_238; - wire [1:0] _zz_239; - wire [31:0] _zz_240; + wire [0:0] _zz_239; + wire [0:0] _zz_240; wire [0:0] _zz_241; - wire [1:0] _zz_242; - wire [0:0] _zz_243; + wire [0:0] _zz_242; + wire _zz_243; wire [0:0] _zz_244; - wire _zz_245; - wire [0:0] _zz_246; - wire [23:0] _zz_247; - wire [31:0] _zz_248; - wire [31:0] _zz_249; - wire [31:0] _zz_250; - wire [0:0] _zz_251; - wire [0:0] _zz_252; - wire [1:0] _zz_253; - wire [1:0] _zz_254; - wire _zz_255; - wire [0:0] _zz_256; - wire [19:0] _zz_257; - wire [31:0] _zz_258; - wire [31:0] _zz_259; - wire [31:0] _zz_260; - wire [31:0] _zz_261; - wire [31:0] _zz_262; - wire [31:0] _zz_263; + wire [19:0] _zz_245; + wire [31:0] _zz_246; + wire [31:0] _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire [2:0] _zz_251; + wire [2:0] _zz_252; + wire _zz_253; + wire [0:0] _zz_254; + wire [16:0] _zz_255; + wire [31:0] _zz_256; + wire [31:0] _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire [0:0] _zz_261; + wire [0:0] _zz_262; + wire _zz_263; wire [0:0] _zz_264; wire [0:0] _zz_265; - wire [1:0] _zz_266; - wire [1:0] _zz_267; - wire _zz_268; - wire [0:0] _zz_269; - wire [16:0] _zz_270; - wire [31:0] _zz_271; - wire [31:0] _zz_272; - wire [31:0] _zz_273; - wire [31:0] _zz_274; - wire [31:0] _zz_275; - wire [31:0] _zz_276; + wire _zz_266; + wire [0:0] _zz_267; + wire [13:0] _zz_268; + wire [31:0] _zz_269; + wire [31:0] _zz_270; + wire _zz_271; + wire _zz_272; + wire [0:0] _zz_273; + wire [0:0] _zz_274; + wire [0:0] _zz_275; + wire [0:0] _zz_276; wire _zz_277; wire [0:0] _zz_278; - wire [0:0] _zz_279; - wire [0:0] _zz_280; - wire [1:0] _zz_281; - wire [0:0] _zz_282; - wire [0:0] _zz_283; + wire [10:0] _zz_279; + wire [31:0] _zz_280; + wire [31:0] _zz_281; + wire _zz_282; + wire _zz_283; wire _zz_284; wire [0:0] _zz_285; - wire [13:0] _zz_286; - wire [31:0] _zz_287; - wire [31:0] _zz_288; - wire [31:0] _zz_289; - wire [31:0] _zz_290; - wire [31:0] _zz_291; - wire [31:0] _zz_292; - wire [31:0] _zz_293; - wire _zz_294; - wire _zz_295; - wire [31:0] _zz_296; - wire [31:0] _zz_297; - wire [1:0] _zz_298; - wire [1:0] _zz_299; - wire _zz_300; - wire [0:0] _zz_301; - wire [11:0] _zz_302; - wire [31:0] _zz_303; + wire [0:0] _zz_286; + wire _zz_287; + wire [0:0] _zz_288; + wire [7:0] _zz_289; + wire [0:0] _zz_290; + wire [3:0] _zz_291; + wire [0:0] _zz_292; + wire [0:0] _zz_293; + wire [1:0] _zz_294; + wire [1:0] _zz_295; + wire _zz_296; + wire [0:0] _zz_297; + wire [3:0] _zz_298; + wire [31:0] _zz_299; + wire [31:0] _zz_300; + wire [31:0] _zz_301; + wire [0:0] _zz_302; + wire [0:0] _zz_303; wire [31:0] _zz_304; wire [31:0] _zz_305; wire [31:0] _zz_306; wire _zz_307; - wire _zz_308; + wire [0:0] _zz_308; wire [1:0] _zz_309; - wire [1:0] _zz_310; - wire _zz_311; - wire [0:0] _zz_312; - wire [8:0] _zz_313; - wire [31:0] _zz_314; - wire [31:0] _zz_315; + wire _zz_310; + wire [2:0] _zz_311; + wire [2:0] _zz_312; + wire _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; wire [31:0] _zz_316; wire [31:0] _zz_317; wire [31:0] _zz_318; wire [31:0] _zz_319; - wire _zz_320; - wire [2:0] _zz_321; - wire [2:0] _zz_322; + wire [31:0] _zz_320; + wire [31:0] _zz_321; + wire [31:0] _zz_322; wire _zz_323; - wire [0:0] _zz_324; - wire [5:0] _zz_325; - wire _zz_326; - wire _zz_327; + wire [31:0] _zz_324; + wire _zz_325; + wire [0:0] _zz_326; + wire [0:0] _zz_327; wire [0:0] _zz_328; - wire [3:0] _zz_329; - wire [0:0] _zz_330; - wire [0:0] _zz_331; - wire [1:0] _zz_332; - wire [1:0] _zz_333; - wire _zz_334; - wire [0:0] _zz_335; - wire [2:0] _zz_336; + wire [0:0] _zz_329; + wire [1:0] _zz_330; + wire [1:0] _zz_331; + wire [0:0] _zz_332; + wire [0:0] _zz_333; + wire [31:0] _zz_334; + wire [31:0] _zz_335; + wire [31:0] _zz_336; wire [31:0] _zz_337; wire [31:0] _zz_338; wire [31:0] _zz_339; - wire [31:0] _zz_340; - wire _zz_341; - wire [0:0] _zz_342; - wire [1:0] _zz_343; - wire [31:0] _zz_344; - wire [31:0] _zz_345; - wire _zz_346; - wire [0:0] _zz_347; - wire [2:0] _zz_348; - wire [0:0] _zz_349; - wire [0:0] _zz_350; - wire _zz_351; - wire [0:0] _zz_352; - wire [0:0] _zz_353; - wire [31:0] _zz_354; - wire [31:0] _zz_355; - wire [31:0] _zz_356; - wire _zz_357; - wire _zz_358; - wire [31:0] _zz_359; - wire [31:0] _zz_360; - wire [31:0] _zz_361; - wire _zz_362; - wire [0:0] _zz_363; - wire [0:0] _zz_364; - wire [31:0] _zz_365; - wire [31:0] _zz_366; - wire [0:0] _zz_367; - wire [1:0] _zz_368; - wire [1:0] _zz_369; - wire [1:0] _zz_370; - wire [1:0] _zz_371; - wire [1:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire [31:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire [31:0] _zz_378; - wire [31:0] _zz_379; - wire [31:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] memory_MEMORY_READ_DATA; - wire [31:0] execute_BRANCH_CALC; - wire execute_BRANCH_DO; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; wire decode_SRC2_FORCE_ZERO; wire [31:0] decode_RS2; wire [31:0] decode_RS1; - wire decode_IS_DIV; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_MUL; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_1; wire `EnvCtrlEnum_defaultEncoding_type _zz_2; wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; wire decode_IS_CSR; wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `BranchCtrlEnum_defaultEncoding_type _zz_10; + wire `BranchCtrlEnum_defaultEncoding_type _zz_4; + wire `BranchCtrlEnum_defaultEncoding_type _zz_5; + wire `BranchCtrlEnum_defaultEncoding_type _zz_6; wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_7; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_8; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_9; wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_10; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_11; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_12; wire decode_SRC_LESS_UNSIGNED; wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_17; - wire `AluCtrlEnum_defaultEncoding_type _zz_18; - wire `AluCtrlEnum_defaultEncoding_type _zz_19; + wire `AluCtrlEnum_defaultEncoding_type _zz_13; + wire `AluCtrlEnum_defaultEncoding_type _zz_14; + wire `AluCtrlEnum_defaultEncoding_type _zz_15; wire decode_MEMORY_STORE; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_MUL; wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - reg [31:0] _zz_26; - wire memory_IS_MUL; + wire execute_IS_MUL; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; - wire [31:0] memory_BRANCH_CALC; - wire memory_BRANCH_DO; - wire [31:0] execute_PC; + wire `EnvCtrlEnum_defaultEncoding_type _zz_16; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; wire [31:0] execute_RS1; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `BranchCtrlEnum_defaultEncoding_type _zz_17; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] _zz_31; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_18; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_33; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_34; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] _zz_19; + wire [31:0] _zz_20; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire [31:0] _zz_22; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_23; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_36; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_37; - wire [31:0] _zz_38; - wire _zz_39; - reg _zz_40; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25; + wire [31:0] _zz_26; + wire _zz_27; + reg _zz_28; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; - wire `EnvCtrlEnum_defaultEncoding_type _zz_41; - wire `BranchCtrlEnum_defaultEncoding_type _zz_42; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_43; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_44; - wire `AluCtrlEnum_defaultEncoding_type _zz_45; - wire `Src2CtrlEnum_defaultEncoding_type _zz_46; - wire `Src1CtrlEnum_defaultEncoding_type _zz_47; - wire writeBack_MEMORY_STORE; - reg [31:0] _zz_48; - wire writeBack_MEMORY_ENABLE; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP2_physicalAddress; - wire memory_MMU_RSP2_isIoAccess; - wire memory_MMU_RSP2_isPaging; - wire memory_MMU_RSP2_allowRead; - wire memory_MMU_RSP2_allowWrite; - wire memory_MMU_RSP2_allowExecute; - wire memory_MMU_RSP2_exception; - wire memory_MMU_RSP2_refilling; - wire memory_MMU_RSP2_bypassTranslation; - wire [31:0] memory_PC; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_STORE; - wire memory_MEMORY_ENABLE; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_31; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_32; + wire `AluCtrlEnum_defaultEncoding_type _zz_33; + wire `Src2CtrlEnum_defaultEncoding_type _zz_34; + wire `Src1CtrlEnum_defaultEncoding_type _zz_35; + reg [31:0] _zz_36; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] execute_MEMORY_READ_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; wire execute_MMU_FAULT; wire [31:0] execute_MMU_RSP2_physicalAddress; wire execute_MMU_RSP2_isIoAccess; @@ -482,16 +408,17 @@ module VexRiscv ( wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; wire [31:0] execute_RS2; - wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; wire decode_MEMORY_ENABLE; - reg [31:0] _zz_49; - wire [31:0] decode_PC; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; wire [31:0] decode_INSTRUCTION; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; + wire [31:0] decode_PC; + wire [31:0] execute_PC; + wire [31:0] execute_INSTRUCTION; reg decode_arbitration_haltItself; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; @@ -506,7 +433,7 @@ module VexRiscv ( reg execute_arbitration_haltItself; wire execute_arbitration_haltByOther; reg execute_arbitration_removeIt; - wire execute_arbitration_flushIt; + reg execute_arbitration_flushIt; reg execute_arbitration_flushNext; reg execute_arbitration_isValid; wire execute_arbitration_isStuck; @@ -514,62 +441,29 @@ module VexRiscv ( wire execute_arbitration_isFlushed; wire execute_arbitration_isMoving; wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - wire writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - wire writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; wire [31:0] lastStageInstruction /* verilator public */ ; wire [31:0] lastStagePc /* verilator public */ ; wire lastStageIsValid /* verilator public */ ; wire lastStageIsFiring /* verilator public */ ; - reg IBusSimplePlugin_fetcherHalt; - reg IBusSimplePlugin_incomingInstruction; - wire IBusSimplePlugin_pcValids_0; - wire IBusSimplePlugin_pcValids_1; - wire IBusSimplePlugin_pcValids_2; - wire IBusSimplePlugin_pcValids_3; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - wire [31:0] iBus_cmd_payload_pc; - wire iBus_rsp_valid; - wire iBus_rsp_payload_error; - wire [31:0] iBus_rsp_payload_inst; - wire IBusSimplePlugin_decodeExceptionPort_valid; - reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; - wire IBusSimplePlugin_mmuBus_cmd_0_isValid; - wire IBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire IBusSimplePlugin_mmuBus_rsp_isPaging; - wire IBusSimplePlugin_mmuBus_rsp_allowRead; - wire IBusSimplePlugin_mmuBus_rsp_allowWrite; - wire IBusSimplePlugin_mmuBus_rsp_allowExecute; - wire IBusSimplePlugin_mmuBus_rsp_exception; - wire IBusSimplePlugin_mmuBus_rsp_refilling; - wire IBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire IBusSimplePlugin_mmuBus_end; - wire IBusSimplePlugin_mmuBus_busy; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; reg DBusSimplePlugin_memoryExceptionPort_valid; reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; @@ -590,6 +484,9 @@ module VexRiscv ( wire DBusSimplePlugin_mmuBus_busy; reg DBusSimplePlugin_redoBranch_valid; wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; wire CsrPlugin_inWfi /* verilator public */ ; @@ -598,8 +495,6 @@ module VexRiscv ( reg [31:0] CsrPlugin_jumpInterface_payload; wire CsrPlugin_exceptionPendings_0; wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; wire externalInterrupt; wire contextSwitching; reg [1:0] CsrPlugin_privilege; @@ -609,107 +504,84 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; - wire IBusSimplePlugin_externalFlush; - wire IBusSimplePlugin_jump_pcLoad_valid; - wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; - wire [2:0] _zz_50; - wire [2:0] _zz_51; - wire _zz_52; - wire _zz_53; - wire IBusSimplePlugin_fetchPc_output_valid; - wire IBusSimplePlugin_fetchPc_output_ready; - wire [31:0] IBusSimplePlugin_fetchPc_output_payload; - reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusSimplePlugin_fetchPc_correction; - reg IBusSimplePlugin_fetchPc_correctionReg; - wire IBusSimplePlugin_fetchPc_corrected; - reg IBusSimplePlugin_fetchPc_pcRegPropagate; - reg IBusSimplePlugin_fetchPc_booted; - reg IBusSimplePlugin_fetchPc_inc; - reg [31:0] IBusSimplePlugin_fetchPc_pc; - wire IBusSimplePlugin_fetchPc_redo_valid; - wire [31:0] IBusSimplePlugin_fetchPc_redo_payload; - reg IBusSimplePlugin_fetchPc_flushed; - reg IBusSimplePlugin_iBusRsp_redoFetch; - wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; - wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; - wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; - wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; - reg IBusSimplePlugin_iBusRsp_stages_0_halt; - wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; - wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; - wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; - wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; - wire IBusSimplePlugin_iBusRsp_stages_1_halt; - wire _zz_54; - wire _zz_55; - wire IBusSimplePlugin_iBusRsp_flush; - wire _zz_56; - wire _zz_57; - reg _zz_58; - reg IBusSimplePlugin_iBusRsp_readyForError; - wire IBusSimplePlugin_iBusRsp_output_valid; - wire IBusSimplePlugin_iBusRsp_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; - wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; - wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; - wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; - wire IBusSimplePlugin_injector_decodeInput_valid; - wire IBusSimplePlugin_injector_decodeInput_ready; - wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; - wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; - wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; - reg _zz_59; - reg [31:0] _zz_60; - reg _zz_61; - reg [31:0] _zz_62; - reg _zz_63; - reg IBusSimplePlugin_injector_nextPcCalc_valids_0; - reg IBusSimplePlugin_injector_nextPcCalc_valids_1; - reg IBusSimplePlugin_injector_nextPcCalc_valids_2; - reg IBusSimplePlugin_injector_nextPcCalc_valids_3; - reg IBusSimplePlugin_injector_nextPcCalc_valids_4; - reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; - reg IBusSimplePlugin_cmd_valid; - wire IBusSimplePlugin_cmd_ready; - wire [31:0] IBusSimplePlugin_cmd_payload_pc; - wire IBusSimplePlugin_pending_inc; - wire IBusSimplePlugin_pending_dec; - reg [2:0] IBusSimplePlugin_pending_value; - wire [2:0] IBusSimplePlugin_pending_next; - wire IBusSimplePlugin_cmdFork_canEmit; - reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; - reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; - reg IBusSimplePlugin_mmu_joinCtx_isPaging; - reg IBusSimplePlugin_mmu_joinCtx_allowRead; - reg IBusSimplePlugin_mmu_joinCtx_allowWrite; - reg IBusSimplePlugin_mmu_joinCtx_allowExecute; - reg IBusSimplePlugin_mmu_joinCtx_exception; - reg IBusSimplePlugin_mmu_joinCtx_refilling; - reg IBusSimplePlugin_mmu_joinCtx_bypassTranslation; - wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; - wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; - wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; - wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; - reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; - wire IBusSimplePlugin_rspJoin_rspBuffer_flush; - wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; - reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; - wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; - wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; - wire IBusSimplePlugin_rspJoin_join_valid; - wire IBusSimplePlugin_rspJoin_join_ready; - wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; - wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; - wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; - wire IBusSimplePlugin_rspJoin_join_payload_isRvc; - reg IBusSimplePlugin_rspJoin_exceptionDetected; - wire _zz_64; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_37; + wire [2:0] _zz_38; + wire _zz_39; + wire _zz_40; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_41; + wire _zz_42; + wire _zz_43; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_44; + wire _zz_45; + reg _zz_46; + wire _zz_47; + reg _zz_48; + reg [31:0] _zz_49; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_50; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; wire dBus_cmd_valid; wire dBus_cmd_ready; wire dBus_cmd_payload_wr; @@ -719,32 +591,32 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - wire _zz_65; + reg _zz_51; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_66; - reg [3:0] _zz_67; + reg [31:0] _zz_52; + reg [3:0] _zz_53; wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_68; - reg [31:0] _zz_69; - wire _zz_70; - reg [31:0] _zz_71; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [29:0] _zz_72; - wire _zz_73; - wire _zz_74; - wire _zz_75; - wire _zz_76; - wire _zz_77; - wire _zz_78; - wire _zz_79; - wire `Src1CtrlEnum_defaultEncoding_type _zz_80; - wire `Src2CtrlEnum_defaultEncoding_type _zz_81; - wire `AluCtrlEnum_defaultEncoding_type _zz_82; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_83; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_84; - wire `BranchCtrlEnum_defaultEncoding_type _zz_85; - wire `EnvCtrlEnum_defaultEncoding_type _zz_86; + reg [31:0] execute_DBusSimplePlugin_rspShifted; + wire _zz_54; + reg [31:0] _zz_55; + wire _zz_56; + reg [31:0] _zz_57; + reg [31:0] execute_DBusSimplePlugin_rspFormated; + wire [29:0] _zz_58; + wire _zz_59; + wire _zz_60; + wire _zz_61; + wire _zz_62; + wire _zz_63; + wire _zz_64; + wire _zz_65; + wire `Src1CtrlEnum_defaultEncoding_type _zz_66; + wire `Src2CtrlEnum_defaultEncoding_type _zz_67; + wire `AluCtrlEnum_defaultEncoding_type _zz_68; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_69; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_70; + wire `BranchCtrlEnum_defaultEncoding_type _zz_71; + wire `EnvCtrlEnum_defaultEncoding_type _zz_72; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -752,40 +624,41 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_87; + reg _zz_73; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_88; - reg [31:0] _zz_89; - wire _zz_90; - reg [19:0] _zz_91; - wire _zz_92; - reg [19:0] _zz_93; - reg [31:0] _zz_94; + reg [31:0] _zz_74; + reg [31:0] _zz_75; + wire _zz_76; + reg [19:0] _zz_77; + wire _zz_78; + reg [19:0] _zz_79; + reg [31:0] _zz_80; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; wire execute_LightShifterPlugin_isShift; reg [4:0] execute_LightShifterPlugin_amplitudeReg; wire [4:0] execute_LightShifterPlugin_amplitude; + reg [31:0] execute_LightShifterPlugin_shiftReg; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_95; - reg _zz_96; - reg _zz_97; - reg _zz_98; - reg [4:0] _zz_99; + reg [31:0] _zz_81; + reg _zz_82; + reg _zz_83; + reg _zz_84; + reg [4:0] _zz_85; wire execute_BranchPlugin_eq; - wire [2:0] _zz_100; - reg _zz_101; - reg _zz_102; + wire [2:0] _zz_86; + reg _zz_87; + reg _zz_88; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_103; - reg [10:0] _zz_104; - wire _zz_105; - reg [19:0] _zz_106; - wire _zz_107; - reg [18:0] _zz_108; - reg [31:0] _zz_109; + wire _zz_89; + reg [10:0] _zz_90; + wire _zz_91; + reg [19:0] _zz_92; + wire _zz_93; + reg [18:0] _zz_94; + reg [31:0] _zz_95; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -807,29 +680,25 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_110; - wire _zz_111; - wire _zz_112; + wire _zz_96; + wire _zz_97; + wire _zz_98; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_99; + wire _zz_100; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; - reg CsrPlugin_pipelineLiberator_pcValids_1; - reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; reg CsrPlugin_pipelineLiberator_done; wire CsrPlugin_interruptJump /* verilator public */ ; @@ -850,61 +719,29 @@ module VexRiscv ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - wire memory_MulDivIterativePlugin_frontendOk; - reg memory_MulDivIterativePlugin_mul_counter_willIncrement; - reg memory_MulDivIterativePlugin_mul_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; - wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_mul_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_needRevert; - reg memory_MulDivIterativePlugin_div_counter_willIncrement; - reg memory_MulDivIterativePlugin_div_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_div_counter_value; - wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_div_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_done; - reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_113; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [31:0] _zz_114; - wire _zz_115; - wire _zz_116; - reg [32:0] _zz_117; + reg [32:0] execute_MulDivIterativePlugin_rs1; + reg [31:0] execute_MulDivIterativePlugin_rs2; + reg [64:0] execute_MulDivIterativePlugin_accumulator; + reg execute_MulDivIterativePlugin_frontendOk; + reg execute_MulDivIterativePlugin_mul_counter_willIncrement; + reg execute_MulDivIterativePlugin_mul_counter_willClear; + reg [5:0] execute_MulDivIterativePlugin_mul_counter_valueNext; + reg [5:0] execute_MulDivIterativePlugin_mul_counter_value; + wire execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc; + wire execute_MulDivIterativePlugin_mul_counter_willOverflow; + wire _zz_101; + wire _zz_102; + reg [32:0] _zz_103; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_118; - wire [31:0] _zz_119; + reg [31:0] _zz_104; + wire [31:0] _zz_105; reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; reg decode_to_execute_SRC_USE_SUB_LESS; reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; reg decode_to_execute_MEMORY_STORE; - reg execute_to_memory_MEMORY_STORE; - reg memory_to_writeBack_MEMORY_STORE; reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; reg decode_to_execute_SRC_LESS_UNSIGNED; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; @@ -912,36 +749,16 @@ module VexRiscv ( reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; reg decode_to_execute_IS_CSR; reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; reg decode_to_execute_IS_RS1_SIGNED; reg decode_to_execute_IS_RS2_SIGNED; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; reg [31:0] decode_to_execute_RS1; reg [31:0] decode_to_execute_RS2; reg decode_to_execute_SRC2_FORCE_ZERO; + reg [31:0] decode_to_execute_SRC1; + reg [31:0] decode_to_execute_SRC2; reg decode_to_execute_CSR_WRITE_OPCODE; reg decode_to_execute_CSR_READ_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_MMU_FAULT; - reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; - reg execute_to_memory_MMU_RSP2_isIoAccess; - reg execute_to_memory_MMU_RSP2_isPaging; - reg execute_to_memory_MMU_RSP2_allowRead; - reg execute_to_memory_MMU_RSP2_allowWrite; - reg execute_to_memory_MMU_RSP2_allowExecute; - reg execute_to_memory_MMU_RSP2_exception; - reg execute_to_memory_MMU_RSP2_refilling; - reg execute_to_memory_MMU_RSP2_bypassTranslation; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg execute_to_memory_BRANCH_DO; - reg [31:0] execute_to_memory_BRANCH_CALC; - reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_836; reg execute_CsrPlugin_csr_772; @@ -953,21 +770,19 @@ module VexRiscv ( reg execute_CsrPlugin_csr_2944; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_120; - reg [31:0] _zz_121; - reg [31:0] _zz_122; - reg [31:0] _zz_123; - reg [31:0] _zz_124; - reg [31:0] _zz_125; - reg [31:0] _zz_126; - reg [31:0] _zz_127; - reg [31:0] _zz_128; - reg [31:0] _zz_129; - wire iBus_cmd_m2sPipe_valid; - wire iBus_cmd_m2sPipe_ready; - wire [31:0] iBus_cmd_m2sPipe_payload_pc; - reg iBus_cmd_m2sPipe_rValid; - reg [31:0] iBus_cmd_m2sPipe_rData_pc; + reg [31:0] _zz_106; + reg [31:0] _zz_107; + reg [31:0] _zz_108; + reg [31:0] _zz_109; + reg [31:0] _zz_110; + reg [31:0] _zz_111; + reg [31:0] _zz_112; + reg [31:0] _zz_113; + reg [31:0] _zz_114; + reg [31:0] _zz_115; + reg [2:0] _zz_116; + reg _zz_117; + reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; wire dBus_cmd_halfPipe_payload_wr; @@ -980,379 +795,357 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_130; + reg [3:0] _zz_118; `ifndef SYNTHESIS + reg [39:0] decode_ENV_CTRL_string; reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [31:0] _zz_10_string; + reg [31:0] _zz_4_string; + reg [31:0] _zz_5_string; + reg [31:0] _zz_6_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_11_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; + reg [71:0] _zz_7_string; + reg [71:0] _zz_8_string; + reg [71:0] _zz_9_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_14_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; + reg [39:0] _zz_10_string; + reg [39:0] _zz_11_string; + reg [39:0] _zz_12_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_17_string; - reg [63:0] _zz_18_string; - reg [63:0] _zz_19_string; + reg [63:0] _zz_13_string; + reg [63:0] _zz_14_string; + reg [63:0] _zz_15_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_16_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_17_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_18_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_20_string; reg [23:0] _zz_21_string; - reg [23:0] _zz_22_string; reg [95:0] decode_SRC1_CTRL_string; reg [95:0] _zz_23_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27_string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28_string; - reg [39:0] writeBack_ENV_CTRL_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_24_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_25_string; reg [39:0] _zz_29_string; - reg [31:0] execute_BRANCH_CTRL_string; reg [31:0] _zz_30_string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_32_string; - reg [23:0] execute_SRC2_CTRL_string; + reg [71:0] _zz_31_string; + reg [39:0] _zz_32_string; + reg [63:0] _zz_33_string; reg [23:0] _zz_34_string; - reg [95:0] execute_SRC1_CTRL_string; reg [95:0] _zz_35_string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_36_string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_37_string; - reg [39:0] _zz_41_string; - reg [31:0] _zz_42_string; - reg [71:0] _zz_43_string; - reg [39:0] _zz_44_string; - reg [63:0] _zz_45_string; - reg [23:0] _zz_46_string; - reg [95:0] _zz_47_string; - reg [95:0] _zz_80_string; - reg [23:0] _zz_81_string; - reg [63:0] _zz_82_string; - reg [39:0] _zz_83_string; - reg [71:0] _zz_84_string; - reg [31:0] _zz_85_string; - reg [39:0] _zz_86_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [95:0] _zz_66_string; + reg [23:0] _zz_67_string; + reg [63:0] _zz_68_string; + reg [39:0] _zz_69_string; + reg [71:0] _zz_70_string; + reg [31:0] _zz_71_string; + reg [39:0] _zz_72_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; `endif (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_136 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_137 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_138 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_139 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_140 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_141 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_142 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_143 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_144 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_145 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_146 = (1'b1 || (! 1'b1)); - assign _zz_147 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_148 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_149 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_150 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_151 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_152 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_153 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_154 = (! memory_arbitration_isStuck); - assign _zz_155 = (! execute_arbitration_isStuckByOthers); - assign _zz_156 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_157 = ((_zz_110 && 1'b1) && (! 1'b0)); - assign _zz_158 = ((_zz_111 && 1'b1) && (! 1'b0)); - assign _zz_159 = ((_zz_112 && 1'b1) && (! 1'b0)); - assign _zz_160 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_161 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_162 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_163 = execute_INSTRUCTION[13]; - assign _zz_164 = _zz_72[29 : 29]; - assign _zz_165 = _zz_72[28 : 28]; - assign _zz_166 = _zz_72[27 : 27]; - assign _zz_167 = _zz_72[26 : 26]; - assign _zz_168 = _zz_72[23 : 23]; - assign _zz_169 = _zz_72[14 : 14]; - assign _zz_170 = _zz_72[10 : 10]; - assign _zz_171 = _zz_72[9 : 9]; - assign _zz_172 = _zz_72[8 : 8]; - assign _zz_173 = _zz_72[11 : 11]; - assign _zz_174 = _zz_72[4 : 4]; - assign _zz_175 = _zz_72[2 : 2]; - assign _zz_176 = _zz_72[17 : 17]; - assign _zz_177 = _zz_72[7 : 7]; - assign _zz_178 = _zz_72[3 : 3]; - assign _zz_179 = (_zz_50 - 3'b001); - assign _zz_180 = {IBusSimplePlugin_fetchPc_inc,2'b00}; - assign _zz_181 = {29'd0, _zz_180}; - assign _zz_182 = (IBusSimplePlugin_pending_value + _zz_184); - assign _zz_183 = IBusSimplePlugin_pending_inc; - assign _zz_184 = {2'd0, _zz_183}; - assign _zz_185 = IBusSimplePlugin_pending_dec; - assign _zz_186 = {2'd0, _zz_185}; - assign _zz_187 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); - assign _zz_188 = {2'd0, _zz_187}; - assign _zz_189 = IBusSimplePlugin_pending_dec; - assign _zz_190 = {2'd0, _zz_189}; - assign _zz_191 = execute_SRC_LESS; - assign _zz_192 = 3'b100; - assign _zz_193 = execute_INSTRUCTION[19 : 15]; - assign _zz_194 = execute_INSTRUCTION[31 : 20]; - assign _zz_195 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_196 = ($signed(_zz_197) + $signed(_zz_200)); - assign _zz_197 = ($signed(_zz_198) + $signed(_zz_199)); - assign _zz_198 = execute_SRC1; - assign _zz_199 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_200 = (execute_SRC_USE_SUB_LESS ? _zz_201 : _zz_202); - assign _zz_201 = 32'h00000001; - assign _zz_202 = 32'h0; - assign _zz_203 = (_zz_204 >>> 1); - assign _zz_204 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_205 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_206 = execute_INSTRUCTION[31 : 20]; - assign _zz_207 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_208 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_209 = {5'd0, _zz_208}; - assign _zz_210 = (_zz_212 + _zz_214); - assign _zz_211 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_212 = {{1{_zz_211[32]}}, _zz_211}; - assign _zz_213 = _zz_215; - assign _zz_214 = {{1{_zz_213[32]}}, _zz_213}; - assign _zz_215 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_216 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_217 = {5'd0, _zz_216}; - assign _zz_218 = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_219 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_220 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_221 = {_zz_113,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_222 = _zz_223; - assign _zz_223 = _zz_224; - assign _zz_224 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_114) : _zz_114)} + _zz_226); - assign _zz_225 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_226 = {32'd0, _zz_225}; - assign _zz_227 = _zz_116; - assign _zz_228 = {32'd0, _zz_227}; - assign _zz_229 = _zz_115; - assign _zz_230 = {31'd0, _zz_229}; - assign _zz_231 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_232 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_233 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_234 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_235 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_236 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_237 = 1'b1; - assign _zz_238 = 1'b1; - assign _zz_239 = {_zz_53,_zz_52}; - assign _zz_240 = 32'h02004064; - assign _zz_241 = _zz_79; - assign _zz_242 = {_zz_77,_zz_78}; - assign _zz_243 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_244 = 1'b0; - assign _zz_245 = (((decode_INSTRUCTION & _zz_248) == 32'h00000050) != 1'b0); - assign _zz_246 = ((_zz_249 == _zz_250) != 1'b0); - assign _zz_247 = {({_zz_251,_zz_252} != 2'b00),{(_zz_253 != _zz_254),{_zz_255,{_zz_256,_zz_257}}}}; - assign _zz_248 = 32'h10003050; - assign _zz_249 = (decode_INSTRUCTION & 32'h10403050); - assign _zz_250 = 32'h10000050; - assign _zz_251 = ((decode_INSTRUCTION & _zz_258) == 32'h00001050); - assign _zz_252 = ((decode_INSTRUCTION & _zz_259) == 32'h00002050); - assign _zz_253 = {_zz_76,(_zz_260 == _zz_261)}; - assign _zz_254 = 2'b00; - assign _zz_255 = ((_zz_262 == _zz_263) != 1'b0); - assign _zz_256 = ({_zz_264,_zz_265} != 2'b00); - assign _zz_257 = {(_zz_266 != _zz_267),{_zz_268,{_zz_269,_zz_270}}}; - assign _zz_258 = 32'h00001050; - assign _zz_259 = 32'h00002050; - assign _zz_260 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_261 = 32'h00000004; - assign _zz_262 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_263 = 32'h00000040; - assign _zz_264 = ((decode_INSTRUCTION & _zz_271) == 32'h00000040); - assign _zz_265 = ((decode_INSTRUCTION & _zz_272) == 32'h00000040); - assign _zz_266 = {(_zz_273 == _zz_274),(_zz_275 == _zz_276)}; - assign _zz_267 = 2'b00; - assign _zz_268 = ({_zz_277,{_zz_278,_zz_279}} != 3'b000); - assign _zz_269 = ({_zz_280,_zz_281} != 3'b000); - assign _zz_270 = {(_zz_282 != _zz_283),{_zz_284,{_zz_285,_zz_286}}}; - assign _zz_271 = 32'h00000050; - assign _zz_272 = 32'h00403040; - assign _zz_273 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_274 = 32'h00005010; - assign _zz_275 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_276 = 32'h00005020; - assign _zz_277 = ((decode_INSTRUCTION & _zz_287) == 32'h40001010); - assign _zz_278 = (_zz_288 == _zz_289); - assign _zz_279 = (_zz_290 == _zz_291); - assign _zz_280 = (_zz_292 == _zz_293); - assign _zz_281 = {_zz_294,_zz_295}; - assign _zz_282 = (_zz_296 == _zz_297); - assign _zz_283 = 1'b0; - assign _zz_284 = (_zz_77 != 1'b0); - assign _zz_285 = (_zz_298 != _zz_299); - assign _zz_286 = {_zz_300,{_zz_301,_zz_302}}; - assign _zz_287 = 32'h40003054; - assign _zz_288 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_289 = 32'h00001010; - assign _zz_290 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_291 = 32'h00001010; - assign _zz_292 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_293 = 32'h00000024; - assign _zz_294 = ((decode_INSTRUCTION & 32'h00003034) == 32'h00001010); - assign _zz_295 = ((decode_INSTRUCTION & 32'h02003054) == 32'h00001010); - assign _zz_296 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_297 = 32'h00001000; - assign _zz_298 = {(_zz_303 == _zz_304),(_zz_305 == _zz_306)}; - assign _zz_299 = 2'b00; - assign _zz_300 = ({_zz_307,_zz_308} != 2'b00); - assign _zz_301 = (_zz_74 != 1'b0); - assign _zz_302 = {(_zz_309 != _zz_310),{_zz_311,{_zz_312,_zz_313}}}; - assign _zz_303 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_304 = 32'h00002000; - assign _zz_305 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_306 = 32'h00001000; - assign _zz_307 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00006000); - assign _zz_308 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00004000); - assign _zz_309 = {(_zz_314 == _zz_315),(_zz_316 == _zz_317)}; - assign _zz_310 = 2'b00; - assign _zz_311 = ((_zz_318 == _zz_319) != 1'b0); - assign _zz_312 = (_zz_320 != 1'b0); - assign _zz_313 = {(_zz_321 != _zz_322),{_zz_323,{_zz_324,_zz_325}}}; - assign _zz_314 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_315 = 32'h00000020; - assign _zz_316 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_317 = 32'h00000020; - assign _zz_318 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_319 = 32'h00000020; - assign _zz_320 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); - assign _zz_321 = {_zz_75,{_zz_326,_zz_327}}; - assign _zz_322 = 3'b000; - assign _zz_323 = ({_zz_76,{_zz_328,_zz_329}} != 6'h0); - assign _zz_324 = ({_zz_330,_zz_331} != 2'b00); - assign _zz_325 = {(_zz_332 != _zz_333),{_zz_334,{_zz_335,_zz_336}}}; - assign _zz_326 = ((decode_INSTRUCTION & _zz_337) == 32'h00000010); - assign _zz_327 = ((decode_INSTRUCTION & _zz_338) == 32'h00000020); - assign _zz_328 = (_zz_339 == _zz_340); - assign _zz_329 = {_zz_341,{_zz_342,_zz_343}}; - assign _zz_330 = _zz_75; - assign _zz_331 = (_zz_344 == _zz_345); - assign _zz_332 = {_zz_75,_zz_346}; - assign _zz_333 = 2'b00; - assign _zz_334 = ({_zz_347,_zz_348} != 4'b0000); - assign _zz_335 = (_zz_349 != _zz_350); - assign _zz_336 = {_zz_351,{_zz_352,_zz_353}}; - assign _zz_337 = 32'h00000030; - assign _zz_338 = 32'h02000060; - assign _zz_339 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_340 = 32'h00001010; - assign _zz_341 = ((decode_INSTRUCTION & _zz_354) == 32'h00002010); - assign _zz_342 = (_zz_355 == _zz_356); - assign _zz_343 = {_zz_357,_zz_358}; - assign _zz_344 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_345 = 32'h00000020; - assign _zz_346 = ((decode_INSTRUCTION & _zz_359) == 32'h0); - assign _zz_347 = (_zz_360 == _zz_361); - assign _zz_348 = {_zz_362,{_zz_363,_zz_364}}; - assign _zz_349 = (_zz_365 == _zz_366); - assign _zz_350 = 1'b0; - assign _zz_351 = ({_zz_367,_zz_368} != 3'b000); - assign _zz_352 = (_zz_369 != _zz_370); - assign _zz_353 = (_zz_371 != _zz_372); - assign _zz_354 = 32'h00002010; - assign _zz_355 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_356 = 32'h00000010; - assign _zz_357 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_358 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); - assign _zz_359 = 32'h00000020; - assign _zz_360 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_361 = 32'h0; - assign _zz_362 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); - assign _zz_363 = _zz_74; - assign _zz_364 = ((decode_INSTRUCTION & _zz_373) == 32'h00001000); - assign _zz_365 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_366 = 32'h0; - assign _zz_367 = ((decode_INSTRUCTION & _zz_374) == 32'h00000040); - assign _zz_368 = {(_zz_375 == _zz_376),(_zz_377 == _zz_378)}; - assign _zz_369 = {(_zz_379 == _zz_380),_zz_73}; - assign _zz_370 = 2'b00; - assign _zz_371 = {(_zz_381 == _zz_382),_zz_73}; - assign _zz_372 = 2'b00; - assign _zz_373 = 32'h00005004; - assign _zz_374 = 32'h00000044; - assign _zz_375 = (decode_INSTRUCTION & 32'h00002014); - assign _zz_376 = 32'h00002010; - assign _zz_377 = (decode_INSTRUCTION & 32'h40004034); - assign _zz_378 = 32'h40000030; - assign _zz_379 = (decode_INSTRUCTION & 32'h00000014); - assign _zz_380 = 32'h00000004; - assign _zz_381 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_382 = 32'h00000004; + assign _zz_131 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_132 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_133 = (execute_arbitration_isValid && execute_IS_MUL); + assign _zz_134 = ((_zz_124 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_135 = ((_zz_124 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_136 = (execute_MulDivIterativePlugin_frontendOk && (! execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_137 = ({CsrPlugin_selfException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_138 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_139 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_140 = execute_INSTRUCTION[29 : 28]; + assign _zz_141 = (! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))); + assign _zz_142 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_143 = (1'b1 || (! 1'b1)); + assign _zz_144 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_145 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_146 = (iBus_cmd_valid || (_zz_116 != 3'b000)); + assign _zz_147 = (! execute_arbitration_isStuckByOthers); + assign _zz_148 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_149 = ((_zz_96 && 1'b1) && (! 1'b0)); + assign _zz_150 = ((_zz_97 && 1'b1) && (! 1'b0)); + assign _zz_151 = ((_zz_98 && 1'b1) && (! 1'b0)); + assign _zz_152 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_153 = execute_INSTRUCTION[13 : 12]; + assign _zz_154 = execute_INSTRUCTION[13]; + assign _zz_155 = _zz_58[29 : 29]; + assign _zz_156 = _zz_58[28 : 28]; + assign _zz_157 = _zz_58[27 : 27]; + assign _zz_158 = _zz_58[24 : 24]; + assign _zz_159 = _zz_58[15 : 15]; + assign _zz_160 = _zz_58[11 : 11]; + assign _zz_161 = _zz_58[12 : 12]; + assign _zz_162 = _zz_58[5 : 5]; + assign _zz_163 = _zz_58[3 : 3]; + assign _zz_164 = _zz_58[18 : 18]; + assign _zz_165 = _zz_58[8 : 8]; + assign _zz_166 = _zz_58[4 : 4]; + assign _zz_167 = _zz_58[0 : 0]; + assign _zz_168 = (_zz_37 - 3'b001); + assign _zz_169 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_170 = {29'd0, _zz_169}; + assign _zz_171 = execute_SRC_LESS; + assign _zz_172 = 3'b100; + assign _zz_173 = decode_INSTRUCTION[19 : 15]; + assign _zz_174 = decode_INSTRUCTION[31 : 20]; + assign _zz_175 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_176 = ($signed(_zz_177) + $signed(_zz_180)); + assign _zz_177 = ($signed(_zz_178) + $signed(_zz_179)); + assign _zz_178 = execute_SRC1; + assign _zz_179 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_180 = (execute_SRC_USE_SUB_LESS ? _zz_181 : _zz_182); + assign _zz_181 = 32'h00000001; + assign _zz_182 = 32'h0; + assign _zz_183 = (_zz_184 >>> 1); + assign _zz_184 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_185 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_186 = execute_INSTRUCTION[31 : 20]; + assign _zz_187 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_188 = (_zz_99 & (~ _zz_189)); + assign _zz_189 = (_zz_99 - 2'b01); + assign _zz_190 = execute_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_191 = {5'd0, _zz_190}; + assign _zz_192 = (_zz_194 + _zz_196); + assign _zz_193 = (execute_MulDivIterativePlugin_rs2[0] ? execute_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_194 = {{1{_zz_193[32]}}, _zz_193}; + assign _zz_195 = _zz_197; + assign _zz_196 = {{1{_zz_195[32]}}, _zz_195}; + assign _zz_197 = (execute_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_198 = _zz_102; + assign _zz_199 = {32'd0, _zz_198}; + assign _zz_200 = _zz_101; + assign _zz_201 = {31'd0, _zz_200}; + assign _zz_202 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_203 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_204 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_205 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_206 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_207 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_208 = (iBus_cmd_payload_address >>> 5); + assign _zz_209 = 1'b1; + assign _zz_210 = 1'b1; + assign _zz_211 = {_zz_40,_zz_39}; + assign _zz_212 = 32'h0000107f; + assign _zz_213 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_214 = 32'h00002073; + assign _zz_215 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_216 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_217 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_218) == 32'h00000003),{(_zz_219 == _zz_220),{_zz_221,{_zz_222,_zz_223}}}}}}; + assign _zz_218 = 32'h0000505f; + assign _zz_219 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_220 = 32'h00000063; + assign _zz_221 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_222 = ((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033); + assign _zz_223 = {((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_224) == 32'h00001013),{(_zz_225 == _zz_226),{_zz_227,{_zz_228,_zz_229}}}}}}; + assign _zz_224 = 32'hfc00705f; + assign _zz_225 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_226 = 32'h00005033; + assign _zz_227 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_228 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_229 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_230 = ((decode_INSTRUCTION & 32'h02000074) == 32'h02000030); + assign _zz_231 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz_232 = 1'b0; + assign _zz_233 = (((decode_INSTRUCTION & _zz_236) == 32'h10000050) != 1'b0); + assign _zz_234 = ({_zz_237,_zz_238} != 2'b00); + assign _zz_235 = {({_zz_239,_zz_240} != 2'b00),{(_zz_241 != _zz_242),{_zz_243,{_zz_244,_zz_245}}}}; + assign _zz_236 = 32'h10403050; + assign _zz_237 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_238 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_239 = _zz_63; + assign _zz_240 = ((decode_INSTRUCTION & _zz_246) == 32'h00000004); + assign _zz_241 = ((decode_INSTRUCTION & _zz_247) == 32'h00000040); + assign _zz_242 = 1'b0; + assign _zz_243 = ({_zz_248,_zz_249} != 2'b00); + assign _zz_244 = (_zz_250 != 1'b0); + assign _zz_245 = {(_zz_251 != _zz_252),{_zz_253,{_zz_254,_zz_255}}}; + assign _zz_246 = 32'h0000001c; + assign _zz_247 = 32'h00000058; + assign _zz_248 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_249 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); + assign _zz_250 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); + assign _zz_251 = {(_zz_256 == _zz_257),{_zz_258,_zz_259}}; + assign _zz_252 = 3'b000; + assign _zz_253 = ({_zz_260,{_zz_261,_zz_262}} != 3'b000); + assign _zz_254 = (_zz_263 != 1'b0); + assign _zz_255 = {(_zz_264 != _zz_265),{_zz_266,{_zz_267,_zz_268}}}; + assign _zz_256 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_257 = 32'h40001010; + assign _zz_258 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_259 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_260 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_261 = ((decode_INSTRUCTION & _zz_269) == 32'h00001010); + assign _zz_262 = ((decode_INSTRUCTION & _zz_270) == 32'h00001010); + assign _zz_263 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_264 = _zz_64; + assign _zz_265 = 1'b0; + assign _zz_266 = ({_zz_271,_zz_272} != 2'b00); + assign _zz_267 = ({_zz_273,_zz_274} != 2'b00); + assign _zz_268 = {(_zz_275 != _zz_276),{_zz_277,{_zz_278,_zz_279}}}; + assign _zz_269 = 32'h00003034; + assign _zz_270 = 32'h02003054; + assign _zz_271 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_272 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_273 = ((decode_INSTRUCTION & _zz_280) == 32'h00006000); + assign _zz_274 = ((decode_INSTRUCTION & _zz_281) == 32'h00004000); + assign _zz_275 = _zz_60; + assign _zz_276 = 1'b0; + assign _zz_277 = ({_zz_282,_zz_283} != 2'b00); + assign _zz_278 = (_zz_284 != 1'b0); + assign _zz_279 = {(_zz_285 != _zz_286),{_zz_287,{_zz_288,_zz_289}}}; + assign _zz_280 = 32'h00006004; + assign _zz_281 = 32'h00005004; + assign _zz_282 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_283 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_284 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_285 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); + assign _zz_286 = 1'b0; + assign _zz_287 = (_zz_62 != 1'b0); + assign _zz_288 = ({_zz_63,{_zz_290,_zz_291}} != 6'h0); + assign _zz_289 = {({_zz_292,_zz_293} != 2'b00),{(_zz_294 != _zz_295),{_zz_296,{_zz_297,_zz_298}}}}; + assign _zz_290 = ((decode_INSTRUCTION & _zz_299) == 32'h00001010); + assign _zz_291 = {(_zz_300 == _zz_301),{_zz_62,{_zz_302,_zz_303}}}; + assign _zz_292 = _zz_61; + assign _zz_293 = ((decode_INSTRUCTION & _zz_304) == 32'h00000020); + assign _zz_294 = {_zz_61,(_zz_305 == _zz_306)}; + assign _zz_295 = 2'b00; + assign _zz_296 = ({_zz_307,{_zz_308,_zz_309}} != 4'b0000); + assign _zz_297 = (_zz_310 != 1'b0); + assign _zz_298 = {(_zz_311 != _zz_312),{_zz_313,{_zz_314,_zz_315}}}; + assign _zz_299 = 32'h00001010; + assign _zz_300 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_301 = 32'h00002010; + assign _zz_302 = (_zz_316 == _zz_317); + assign _zz_303 = (_zz_318 == _zz_319); + assign _zz_304 = 32'h00000070; + assign _zz_305 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_306 = 32'h0; + assign _zz_307 = ((decode_INSTRUCTION & _zz_320) == 32'h0); + assign _zz_308 = (_zz_321 == _zz_322); + assign _zz_309 = {_zz_60,_zz_323}; + assign _zz_310 = ((decode_INSTRUCTION & _zz_324) == 32'h0); + assign _zz_311 = {_zz_325,{_zz_326,_zz_327}}; + assign _zz_312 = 3'b000; + assign _zz_313 = ({_zz_328,_zz_329} != 2'b00); + assign _zz_314 = (_zz_330 != _zz_331); + assign _zz_315 = (_zz_332 != _zz_333); + assign _zz_316 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_317 = 32'h00000004; + assign _zz_318 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_319 = 32'h0; + assign _zz_320 = 32'h00000044; + assign _zz_321 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_322 = 32'h0; + assign _zz_323 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_324 = 32'h00000058; + assign _zz_325 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_326 = ((decode_INSTRUCTION & _zz_334) == 32'h00002010); + assign _zz_327 = ((decode_INSTRUCTION & _zz_335) == 32'h40000030); + assign _zz_328 = ((decode_INSTRUCTION & _zz_336) == 32'h00000004); + assign _zz_329 = _zz_59; + assign _zz_330 = {(_zz_337 == _zz_338),_zz_59}; + assign _zz_331 = 2'b00; + assign _zz_332 = ((decode_INSTRUCTION & _zz_339) == 32'h00001008); + assign _zz_333 = 1'b0; + assign _zz_334 = 32'h00002014; + assign _zz_335 = 32'h40004034; + assign _zz_336 = 32'h00000014; + assign _zz_337 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_338 = 32'h00000004; + assign _zz_339 = 32'h00001048; always @ (posedge clk) begin - if(_zz_237) begin - _zz_133 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_209) begin + _zz_128 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_238) begin - _zz_134 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_210) begin + _zz_129 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_40) begin + if(_zz_28) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( - .io_push_valid (iBus_rsp_valid ), //i - .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o - .io_push_payload_error (iBus_rsp_payload_error ), //i - .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i - .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o - .io_pop_ready (_zz_131 ), //i - .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o - .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o - .io_flush (_zz_132 ), //i - .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o - .clk (clk ), //i - .reset (reset ) //i + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_119 ), //i + .io_cpu_prefetch_isValid (_zz_120 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_121 ), //i + .io_cpu_fetch_isStuck (_zz_122 ), //i + .io_cpu_fetch_isRemoved (_zz_123 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_124 ), //i + .io_cpu_decode_isStuck (_zz_125 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_126 ), //i + .io_cpu_fill_valid (_zz_127 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_239) + case(_zz_211) 2'b00 : begin - _zz_135 = CsrPlugin_jumpInterface_payload; + _zz_130 = DBusSimplePlugin_redoBranch_payload; end 2'b01 : begin - _zz_135 = DBusSimplePlugin_redoBranch_payload; + _zz_130 = CsrPlugin_jumpInterface_payload; end default : begin - _zz_135 = BranchPlugin_jumpInterface_payload; + _zz_130 = BranchPlugin_jumpInterface_payload; end endcase end `ifndef SYNTHESIS + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end always @(*) begin case(_zz_1) `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; @@ -1378,179 +1171,191 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; + case(_zz_4) + `BranchCtrlEnum_defaultEncoding_INC : _zz_4_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_4_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_4_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_4_string = "JALR"; + default : _zz_4_string = "????"; endcase end always @(*) begin case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_5_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_5_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_5_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_5_string = "JALR"; + default : _zz_5_string = "????"; endcase end always @(*) begin case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_6_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_6_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_6_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_6_string = "JALR"; + default : _zz_6_string = "????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; + case(_zz_7) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_7_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_7_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_7_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_7_string = "SRA_1 "; + default : _zz_7_string = "?????????"; endcase end always @(*) begin case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_8_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_8_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_8_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_8_string = "SRA_1 "; + default : _zz_8_string = "?????????"; endcase end always @(*) begin case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_9_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_9_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_9_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_9_string = "SRA_1 "; + default : _zz_9_string = "?????????"; endcase end always @(*) begin - case(_zz_10) - `BranchCtrlEnum_defaultEncoding_INC : _zz_10_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_10_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_10_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_10_string = "JALR"; - default : _zz_10_string = "????"; + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(_zz_10) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_10_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_10_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_10_string = "AND_1"; + default : _zz_10_string = "?????"; endcase end always @(*) begin case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_11_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_11_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_11_string = "AND_1"; + default : _zz_11_string = "?????"; endcase end always @(*) begin case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_12_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_12_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_12_string = "AND_1"; + default : _zz_12_string = "?????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(_zz_13) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_13_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_13_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_13_string = "BITWISE "; + default : _zz_13_string = "????????"; endcase end always @(*) begin case(_zz_14) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; - default : _zz_14_string = "?????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_14_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_14_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_14_string = "BITWISE "; + default : _zz_14_string = "????????"; endcase end always @(*) begin case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_15_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_15_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_15_string = "BITWISE "; + default : _zz_15_string = "????????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_16_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_16_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_16_string = "ECALL"; default : _zz_16_string = "?????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(_zz_17) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17_string = "BITWISE "; - default : _zz_17_string = "????????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_17_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_17_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_17_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_17_string = "JALR"; + default : _zz_17_string = "????"; endcase end always @(*) begin - case(_zz_18) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18_string = "BITWISE "; - default : _zz_18_string = "????????"; + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_19) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19_string = "BITWISE "; - default : _zz_19_string = "????????"; + case(_zz_18) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_18_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_18_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_18_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_18_string = "SRA_1 "; + default : _zz_18_string = "?????????"; endcase end always @(*) begin @@ -1562,15 +1367,6 @@ module VexRiscv ( default : decode_SRC2_CTRL_string = "???"; endcase end - always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; - endcase - end always @(*) begin case(_zz_21) `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; @@ -1580,15 +1376,6 @@ module VexRiscv ( default : _zz_21_string = "???"; endcase end - always @(*) begin - case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; - endcase - end always @(*) begin case(decode_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; @@ -1608,61 +1395,35 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; - default : execute_ENV_CTRL_string = "?????"; + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; - default : writeBack_ENV_CTRL_string = "?????"; + case(_zz_25) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25_string = "AND_1"; + default : _zz_25_string = "?????"; endcase end always @(*) begin @@ -1673,15 +1434,6 @@ module VexRiscv ( default : _zz_29_string = "?????"; endcase end - always @(*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; - endcase - end always @(*) begin case(_zz_30) `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; @@ -1692,30 +1444,28 @@ module VexRiscv ( endcase end always @(*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; + case(_zz_31) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_31_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_31_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_31_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_31_string = "SRA_1 "; + default : _zz_31_string = "?????????"; endcase end always @(*) begin case(_zz_32) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_32_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_32_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_32_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_32_string = "SRA_1 "; - default : _zz_32_string = "?????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_32_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_32_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_32_string = "AND_1"; + default : _zz_32_string = "?????"; endcase end always @(*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; - default : execute_SRC2_CTRL_string = "???"; + case(_zz_33) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_33_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_33_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_33_string = "BITWISE "; + default : _zz_33_string = "????????"; endcase end always @(*) begin @@ -1727,15 +1477,6 @@ module VexRiscv ( default : _zz_34_string = "???"; endcase end - always @(*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; - default : execute_SRC1_CTRL_string = "????????????"; - endcase - end always @(*) begin case(_zz_35) `Src1CtrlEnum_defaultEncoding_RS : _zz_35_string = "RS "; @@ -1746,173 +1487,63 @@ module VexRiscv ( endcase end always @(*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; - endcase - end - always @(*) begin - case(_zz_36) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_36_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_36_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_36_string = "BITWISE "; - default : _zz_36_string = "????????"; - endcase - end - always @(*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_37) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_37_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_37_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_37_string = "AND_1"; - default : _zz_37_string = "?????"; - endcase - end - always @(*) begin - case(_zz_41) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_41_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_41_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_41_string = "ECALL"; - default : _zz_41_string = "?????"; - endcase - end - always @(*) begin - case(_zz_42) - `BranchCtrlEnum_defaultEncoding_INC : _zz_42_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_42_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_42_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_42_string = "JALR"; - default : _zz_42_string = "????"; - endcase - end - always @(*) begin - case(_zz_43) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_43_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_43_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_43_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_43_string = "SRA_1 "; - default : _zz_43_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_44) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_44_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_44_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_44_string = "AND_1"; - default : _zz_44_string = "?????"; - endcase - end - always @(*) begin - case(_zz_45) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; - default : _zz_45_string = "????????"; + case(_zz_66) + `Src1CtrlEnum_defaultEncoding_RS : _zz_66_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_66_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_66_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_66_string = "URS1 "; + default : _zz_66_string = "????????????"; endcase end always @(*) begin - case(_zz_46) - `Src2CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_46_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_46_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_46_string = "PC "; - default : _zz_46_string = "???"; + case(_zz_67) + `Src2CtrlEnum_defaultEncoding_RS : _zz_67_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_67_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_67_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_67_string = "PC "; + default : _zz_67_string = "???"; endcase end always @(*) begin - case(_zz_47) - `Src1CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_47_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_47_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_47_string = "URS1 "; - default : _zz_47_string = "????????????"; + case(_zz_68) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_68_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_68_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_68_string = "BITWISE "; + default : _zz_68_string = "????????"; endcase end always @(*) begin - case(_zz_80) - `Src1CtrlEnum_defaultEncoding_RS : _zz_80_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_80_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_80_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_80_string = "URS1 "; - default : _zz_80_string = "????????????"; + case(_zz_69) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_69_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_69_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_69_string = "AND_1"; + default : _zz_69_string = "?????"; endcase end always @(*) begin - case(_zz_81) - `Src2CtrlEnum_defaultEncoding_RS : _zz_81_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_81_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_81_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_81_string = "PC "; - default : _zz_81_string = "???"; + case(_zz_70) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_70_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_70_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_70_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_70_string = "SRA_1 "; + default : _zz_70_string = "?????????"; endcase end always @(*) begin - case(_zz_82) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_82_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_82_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_82_string = "BITWISE "; - default : _zz_82_string = "????????"; + case(_zz_71) + `BranchCtrlEnum_defaultEncoding_INC : _zz_71_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_71_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_71_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_71_string = "JALR"; + default : _zz_71_string = "????"; endcase end always @(*) begin - case(_zz_83) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_83_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_83_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_83_string = "AND_1"; - default : _zz_83_string = "?????"; - endcase - end - always @(*) begin - case(_zz_84) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_84_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_84_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_84_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_84_string = "SRA_1 "; - default : _zz_84_string = "?????????"; - endcase - end - always @(*) begin - case(_zz_85) - `BranchCtrlEnum_defaultEncoding_INC : _zz_85_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_85_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_85_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_85_string = "JALR"; - default : _zz_85_string = "????"; - endcase - end - always @(*) begin - case(_zz_86) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_86_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_86_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_86_string = "ECALL"; - default : _zz_86_string = "?????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; - default : decode_to_execute_SRC2_CTRL_string = "???"; + case(_zz_72) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_72_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_72_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_72_string = "ECALL"; + default : _zz_72_string = "?????"; endcase end always @(*) begin @@ -1957,168 +1588,101 @@ module VexRiscv ( default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end - always @(*) begin - case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; - default : execute_to_memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; - default : memory_to_writeBack_ENV_CTRL_string = "?????"; - endcase - end `endif - assign memory_MEMORY_READ_DATA = dBus_rsp_data; - assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_102; - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_88; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2 = _zz_80; + assign decode_SRC1 = _zz_75; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign decode_IS_DIV = _zz_164[0]; - assign decode_IS_RS2_SIGNED = _zz_165[0]; - assign decode_IS_RS1_SIGNED = _zz_166[0]; - assign decode_IS_MUL = _zz_167[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_168[0]; - assign decode_BRANCH_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_SHIFT_CTRL = _zz_11; - assign _zz_12 = _zz_13; - assign decode_ALU_BITWISE_CTRL = _zz_14; - assign _zz_15 = _zz_16; - assign decode_SRC_LESS_UNSIGNED = _zz_169[0]; - assign decode_ALU_CTRL = _zz_17; - assign _zz_18 = _zz_19; - assign decode_MEMORY_STORE = _zz_170[0]; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_171[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_172[0]; - assign decode_SRC2_CTRL = _zz_20; - assign _zz_21 = _zz_22; - assign decode_SRC1_CTRL = _zz_23; - assign _zz_24 = _zz_25; - assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; - assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign decode_IS_RS2_SIGNED = _zz_155[0]; + assign decode_IS_RS1_SIGNED = _zz_156[0]; + assign decode_IS_MUL = _zz_157[0]; + assign decode_ENV_CTRL = _zz_1; + assign _zz_2 = _zz_3; + assign decode_IS_CSR = _zz_158[0]; + assign decode_BRANCH_CTRL = _zz_4; + assign _zz_5 = _zz_6; + assign decode_SHIFT_CTRL = _zz_7; + assign _zz_8 = _zz_9; + assign decode_ALU_BITWISE_CTRL = _zz_10; + assign _zz_11 = _zz_12; + assign decode_SRC_LESS_UNSIGNED = _zz_159[0]; + assign decode_ALU_CTRL = _zz_13; + assign _zz_14 = _zz_15; + assign decode_MEMORY_STORE = _zz_160[0]; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_DIV = decode_to_execute_IS_DIV; - assign execute_IS_MUL = decode_to_execute_IS_MUL; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; - assign memory_IS_DIV = execute_to_memory_IS_DIV; - always @ (*) begin - _zz_26 = memory_REGFILE_WRITE_DATA; - if(_zz_136)begin - _zz_26 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); - end - if(_zz_137)begin - _zz_26 = memory_MulDivIterativePlugin_div_result; - end - end - - assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27; - assign execute_ENV_CTRL = _zz_28; - assign writeBack_ENV_CTRL = _zz_29; - assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; - assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; - assign execute_PC = decode_to_execute_PC; + assign execute_ENV_CTRL = _zz_16; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_88; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_173[0]; - assign decode_RS1_USE = _zz_174[0]; + assign execute_BRANCH_CTRL = _zz_17; + assign decode_RS2_USE = _zz_161[0]; + assign decode_RS1_USE = _zz_162[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; - assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; - assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; - assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_138)begin - _zz_31 = _zz_95; - end - if(_zz_139)begin - _zz_31 = execute_CsrPlugin_readData; - end - end - - assign execute_SHIFT_CTRL = _zz_32; + assign execute_SHIFT_CTRL = _zz_18; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_33 = execute_PC; - assign execute_SRC2_CTRL = _zz_34; - assign execute_SRC1_CTRL = _zz_35; - assign decode_SRC_USE_SUB_LESS = _zz_175[0]; - assign decode_SRC_ADD_ZERO = _zz_176[0]; + assign _zz_19 = decode_PC; + assign _zz_20 = decode_RS2; + assign decode_SRC2_CTRL = _zz_21; + assign _zz_22 = decode_RS1; + assign decode_SRC1_CTRL = _zz_23; + assign decode_SRC_USE_SUB_LESS = _zz_163[0]; + assign decode_SRC_ADD_ZERO = _zz_164[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_36; - assign execute_SRC2 = _zz_94; - assign execute_SRC1 = _zz_89; - assign execute_ALU_BITWISE_CTRL = _zz_37; - assign _zz_38 = writeBack_INSTRUCTION; - assign _zz_39 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_40 = 1'b0; + assign execute_ALU_CTRL = _zz_24; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_25; + assign _zz_26 = execute_INSTRUCTION; + assign _zz_27 = execute_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_28 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_40 = 1'b1; + _zz_28 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_177[0]; + decode_REGFILE_WRITE_VALID = _zz_165[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_212) == 32'h00001073),{(_zz_213 == _zz_214),{_zz_215,{_zz_216,_zz_217}}}}}}} != 21'h0); always @ (*) begin - _zz_48 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_48 = writeBack_DBusSimplePlugin_rspFormated; + _zz_36 = execute_REGFILE_WRITE_DATA; + if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin + _zz_36 = execute_DBusSimplePlugin_rspFormated; + end + if(_zz_131)begin + _zz_36 = _zz_81; + end + if(_zz_132)begin + _zz_36 = execute_CsrPlugin_readData; + end + if(_zz_133)begin + _zz_36 = ((execute_INSTRUCTION[13 : 12] == 2'b00) ? execute_MulDivIterativePlugin_accumulator[31 : 0] : execute_MulDivIterativePlugin_accumulator[63 : 32]); end end - assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; - assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; - assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; - assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; - assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; - assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; - assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; - assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; - assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; - assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; - assign memory_PC = execute_to_memory_PC; - assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; - assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; - assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign execute_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_REGFILE_WRITE_DATA = _zz_74; assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; @@ -2131,25 +1695,29 @@ module VexRiscv ( assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = 1'b0; - assign decode_MEMORY_ENABLE = _zz_178[0]; + assign decode_MEMORY_ENABLE = _zz_166[0]; + assign decode_FLUSH_ALL = _zz_167[0]; always @ (*) begin - _zz_49 = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_49 = DBusSimplePlugin_redoBranch_payload; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_134)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end - if(BranchPlugin_jumpInterface_valid)begin - _zz_49 = BranchPlugin_jumpInterface_payload; + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_135)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; - assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; - assign writeBack_PC = memory_to_writeBack_PC; - assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign execute_PC = decode_to_execute_PC; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; always @ (*) begin decode_arbitration_haltItself = 1'b0; if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin @@ -2159,20 +1727,20 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_96 || _zz_97)))begin + if((decode_arbitration_isValid && (_zz_82 || _zz_83)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != 1'b0))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(IBusSimplePlugin_decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2183,142 +1751,97 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusSimplePlugin_decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_65)))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_51)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_138)begin + if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && ((! dBus_rsp_ready) || (! _zz_51))))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_131)begin if((! execute_LightShifterPlugin_done))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_139)begin + if(_zz_132)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end end - end - - assign execute_arbitration_haltByOther = 1'b0; - always @ (*) begin - execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin - execute_arbitration_removeIt = 1'b1; - end - if(execute_arbitration_isFlushed)begin - execute_arbitration_removeIt = 1'b1; - end - end - - assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin - execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin - execute_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin - memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin - memory_arbitration_haltItself = 1'b1; - end - if(_zz_136)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin - memory_arbitration_haltItself = 1'b1; - end - if(_zz_140)begin - memory_arbitration_haltItself = 1'b1; + if(_zz_133)begin + if(((! execute_MulDivIterativePlugin_frontendOk) || (! execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + execute_arbitration_haltItself = 1'b1; end - end - if(_zz_137)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin - memory_arbitration_haltItself = 1'b1; + if(_zz_136)begin + execute_arbitration_haltItself = 1'b1; end end end - assign memory_arbitration_haltByOther = 1'b0; + assign execute_arbitration_haltByOther = 1'b0; always @ (*) begin - memory_arbitration_removeIt = 1'b0; - if(DBusSimplePlugin_memoryExceptionPort_valid)begin - memory_arbitration_removeIt = 1'b1; + execute_arbitration_removeIt = 1'b0; + if(_zz_137)begin + execute_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin - memory_arbitration_removeIt = 1'b1; + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; end end always @ (*) begin - memory_arbitration_flushIt = 1'b0; + execute_arbitration_flushIt = 1'b0; if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; + execute_arbitration_flushIt = 1'b1; end end always @ (*) begin - memory_arbitration_flushNext = 1'b0; + execute_arbitration_flushNext = 1'b0; if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushNext = 1'b1; + execute_arbitration_flushNext = 1'b1; end if(BranchPlugin_jumpInterface_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(DBusSimplePlugin_memoryExceptionPort_valid)begin - memory_arbitration_flushNext = 1'b1; + execute_arbitration_flushNext = 1'b1; end - end - - assign writeBack_arbitration_haltItself = 1'b0; - assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin - writeBack_arbitration_removeIt = 1'b0; - if(writeBack_arbitration_isFlushed)begin - writeBack_arbitration_removeIt = 1'b1; + if(_zz_137)begin + execute_arbitration_flushNext = 1'b1; end - end - - assign writeBack_arbitration_flushIt = 1'b0; - always @ (*) begin - writeBack_arbitration_flushNext = 1'b0; - if(_zz_141)begin - writeBack_arbitration_flushNext = 1'b1; + if(_zz_138)begin + execute_arbitration_flushNext = 1'b1; end - if(_zz_142)begin - writeBack_arbitration_flushNext = 1'b1; + if(_zz_139)begin + execute_arbitration_flushNext = 1'b1; end end - assign lastStageInstruction = writeBack_INSTRUCTION; - assign lastStagePc = writeBack_PC; - assign lastStageIsValid = writeBack_arbitration_isValid; - assign lastStageIsFiring = writeBack_arbitration_isFiring; + assign lastStageInstruction = execute_INSTRUCTION; + assign lastStagePc = execute_PC; + assign lastStageIsValid = execute_arbitration_isValid; + assign lastStageIsFiring = execute_arbitration_isFiring; always @ (*) begin - IBusSimplePlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin - IBusSimplePlugin_fetcherHalt = 1'b1; + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode} != 2'b00))begin + IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_141)begin - IBusSimplePlugin_fetcherHalt = 1'b1; + if(_zz_138)begin + IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_142)begin - IBusSimplePlugin_fetcherHalt = 1'b1; + if(_zz_139)begin + IBusCachedPlugin_fetcherHalt = 1'b1; end end always @ (*) begin - IBusSimplePlugin_incomingInstruction = 1'b0; - if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin - IBusSimplePlugin_incomingInstruction = 1'b1; - end - if(IBusSimplePlugin_injector_decodeInput_valid)begin - IBusSimplePlugin_incomingInstruction = 1'b1; + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; end end @@ -2326,21 +1849,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_141)begin + if(_zz_138)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_142)begin + if(_zz_139)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_141)begin + if(_zz_138)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_142)begin - case(_zz_162) + if(_zz_139)begin + case(_zz_140) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2353,188 +1876,164 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; - assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); - assign _zz_50 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_51 = (_zz_50 & (~ _zz_179)); - assign _zz_52 = _zz_51[1]; - assign _zz_53 = _zz_51[2]; - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_135; + assign IBusCachedPlugin_externalFlush = ({execute_arbitration_flushNext,decode_arbitration_flushNext} != 2'b00); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); + assign _zz_37 = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}}; + assign _zz_38 = (_zz_37 & (~ _zz_168)); + assign _zz_39 = _zz_38[1]; + assign _zz_40 = _zz_38[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_130; always @ (*) begin - IBusSimplePlugin_fetchPc_correction = 1'b0; - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_correction = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusSimplePlugin_jump_pcLoad_valid)begin - IBusSimplePlugin_fetchPc_correction = 1'b1; + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; end end - assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin - IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin - IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_181); - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_170); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusSimplePlugin_jump_pcLoad_valid)begin - IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end - IBusSimplePlugin_fetchPc_pc[0] = 1'b0; - IBusSimplePlugin_fetchPc_pc[1] = 1'b0; + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end always @ (*) begin - IBusSimplePlugin_fetchPc_flushed = 1'b0; - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_flushed = 1'b1; + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusSimplePlugin_jump_pcLoad_valid)begin - IBusSimplePlugin_fetchPc_flushed = 1'b1; + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; end end - assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); - assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; always @ (*) begin - IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin - IBusSimplePlugin_iBusRsp_redoFetch = 1'b1; + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end - assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; - assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; - assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; always @ (*) begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; - end - if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin - if(IBusSimplePlugin_mmuBus_rsp_refilling)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; - end - if(IBusSimplePlugin_mmuBus_rsp_exception)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - end + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_54 = (! IBusSimplePlugin_iBusRsp_stages_0_halt); - assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_54); - assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_54); - assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; - assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; - assign _zz_55 = (! IBusSimplePlugin_iBusRsp_stages_1_halt); - assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_55); - assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_55); - assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; - assign IBusSimplePlugin_fetchPc_redo_valid = IBusSimplePlugin_iBusRsp_redoFetch; - assign IBusSimplePlugin_fetchPc_redo_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; - assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); - assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_56; - assign _zz_56 = ((1'b0 && (! _zz_57)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); - assign _zz_57 = _zz_58; - assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_57; - assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + assign _zz_41 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_41); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_41); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin - IBusSimplePlugin_iBusRsp_readyForError = 1'b1; - if(IBusSimplePlugin_injector_decodeInput_valid)begin - IBusSimplePlugin_iBusRsp_readyForError = 1'b0; - end - if((! IBusSimplePlugin_pcValids_0))begin - IBusSimplePlugin_iBusRsp_readyForError = 1'b0; + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); - assign IBusSimplePlugin_injector_decodeInput_valid = _zz_59; - assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_60; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_61; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_62; - assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_63; - assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; - assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; - assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; - assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; - assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - assign decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; - assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; - assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; - assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pending_next = (_zz_182 - _zz_186); - assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); + assign _zz_42 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_42); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_42); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin - IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); - if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin - if(IBusSimplePlugin_mmuBus_rsp_refilling)begin - IBusSimplePlugin_cmd_valid = 1'b0; - end - if(IBusSimplePlugin_mmuBus_rsp_exception)begin - IBusSimplePlugin_cmd_valid = 1'b0; - end + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_2 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); - assign IBusSimplePlugin_mmuBus_cmd_0_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; - assign IBusSimplePlugin_mmuBus_cmd_0_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; - assign IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_externalFlush); - assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],2'b00}; - assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); - assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); - assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; - assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - assign _zz_131 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); - assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_131); - assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; + assign _zz_43 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_43); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_43); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_44; + assign _zz_44 = ((1'b0 && (! _zz_45)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_45 = _zz_46; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_45; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_47)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_47 = _zz_48; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_47; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_49; always @ (*) begin - IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; - if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin - IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end - assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_120 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_121 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_122 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_121; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_124 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_125 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_126 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin - IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_143)begin - IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_135)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_134)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); - assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; - assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; - assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; - assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; - assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); - assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); - assign _zz_64 = (! IBusSimplePlugin_rspJoin_exceptionDetected); - assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_64); - assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_64); - assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; - assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; - assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; - assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; always @ (*) begin - IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_143)begin - IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; + _zz_127 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_134)begin + _zz_127 = 1'b1; end end - assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],2'b00}; - assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError); - assign _zz_65 = 1'b0; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_119 = (decode_arbitration_isValid && decode_FLUSH_ALL); always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin @@ -2545,39 +2044,39 @@ module VexRiscv ( end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_65)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_51)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_66 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_52 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_66 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_52 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_66 = execute_RS2[31 : 0]; + _zz_52 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_66; + assign dBus_cmd_payload_data = _zz_52; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_67 = 4'b0001; + _zz_53 = 4'b0001; end 2'b01 : begin - _zz_67 = 4'b0011; + _zz_53 = 4'b0011; end default : begin - _zz_67 = 4'b1111; + _zz_53 = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_67 <<< dBus_cmd_payload_address[1 : 0]); + assign execute_DBusSimplePlugin_formalMask = (_zz_53 <<< dBus_cmd_payload_address[1 : 0]); assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; @@ -2586,129 +2085,129 @@ module VexRiscv ( assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin + if(execute_MMU_RSP2_refilling)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end else begin - if(memory_MMU_FAULT)begin + if(execute_MMU_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_144)begin + if(_zz_141)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(! memory_MMU_RSP2_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); + if(! execute_MMU_RSP2_refilling) begin + if(execute_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (execute_MEMORY_STORE ? 4'b1111 : 4'b1101); end end end - assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA; always @ (*) begin DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin + if(execute_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_144)begin + if(_zz_141)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end - assign DBusSimplePlugin_redoBranch_payload = memory_PC; + assign DBusSimplePlugin_redoBranch_payload = execute_PC; always @ (*) begin - writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; - case(writeBack_MEMORY_ADDRESS_LOW) + execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; + case(execute_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8]; end 2'b10 : begin - writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16]; end 2'b11 : begin - writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24]; end default : begin end endcase end - assign _zz_68 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_69[31] = _zz_68; - _zz_69[30] = _zz_68; - _zz_69[29] = _zz_68; - _zz_69[28] = _zz_68; - _zz_69[27] = _zz_68; - _zz_69[26] = _zz_68; - _zz_69[25] = _zz_68; - _zz_69[24] = _zz_68; - _zz_69[23] = _zz_68; - _zz_69[22] = _zz_68; - _zz_69[21] = _zz_68; - _zz_69[20] = _zz_68; - _zz_69[19] = _zz_68; - _zz_69[18] = _zz_68; - _zz_69[17] = _zz_68; - _zz_69[16] = _zz_68; - _zz_69[15] = _zz_68; - _zz_69[14] = _zz_68; - _zz_69[13] = _zz_68; - _zz_69[12] = _zz_68; - _zz_69[11] = _zz_68; - _zz_69[10] = _zz_68; - _zz_69[9] = _zz_68; - _zz_69[8] = _zz_68; - _zz_69[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_70 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_71[31] = _zz_70; - _zz_71[30] = _zz_70; - _zz_71[29] = _zz_70; - _zz_71[28] = _zz_70; - _zz_71[27] = _zz_70; - _zz_71[26] = _zz_70; - _zz_71[25] = _zz_70; - _zz_71[24] = _zz_70; - _zz_71[23] = _zz_70; - _zz_71[22] = _zz_70; - _zz_71[21] = _zz_70; - _zz_71[20] = _zz_70; - _zz_71[19] = _zz_70; - _zz_71[18] = _zz_70; - _zz_71[17] = _zz_70; - _zz_71[16] = _zz_70; - _zz_71[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_161) + assign _zz_54 = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_55[31] = _zz_54; + _zz_55[30] = _zz_54; + _zz_55[29] = _zz_54; + _zz_55[28] = _zz_54; + _zz_55[27] = _zz_54; + _zz_55[26] = _zz_54; + _zz_55[25] = _zz_54; + _zz_55[24] = _zz_54; + _zz_55[23] = _zz_54; + _zz_55[22] = _zz_54; + _zz_55[21] = _zz_54; + _zz_55[20] = _zz_54; + _zz_55[19] = _zz_54; + _zz_55[18] = _zz_54; + _zz_55[17] = _zz_54; + _zz_55[16] = _zz_54; + _zz_55[15] = _zz_54; + _zz_55[14] = _zz_54; + _zz_55[13] = _zz_54; + _zz_55[12] = _zz_54; + _zz_55[11] = _zz_54; + _zz_55[10] = _zz_54; + _zz_55[9] = _zz_54; + _zz_55[8] = _zz_54; + _zz_55[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_56 = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_57[31] = _zz_56; + _zz_57[30] = _zz_56; + _zz_57[29] = _zz_56; + _zz_57[28] = _zz_56; + _zz_57[27] = _zz_56; + _zz_57[26] = _zz_56; + _zz_57[25] = _zz_56; + _zz_57[24] = _zz_56; + _zz_57[23] = _zz_56; + _zz_57[22] = _zz_56; + _zz_57[21] = _zz_56; + _zz_57[20] = _zz_56; + _zz_57[19] = _zz_56; + _zz_57[18] = _zz_56; + _zz_57[17] = _zz_56; + _zz_57[16] = _zz_56; + _zz_57[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_153) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_69; + execute_DBusSimplePlugin_rspFormated = _zz_55; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_71; + execute_DBusSimplePlugin_rspFormated = _zz_57; end default : begin - writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; end endcase end - assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign IBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign IBusSimplePlugin_mmuBus_busy = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -2718,49 +2217,52 @@ module VexRiscv ( assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_73 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_74 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_75 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_76 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_77 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_78 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); - assign _zz_79 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); - assign _zz_72 = {(((decode_INSTRUCTION & _zz_240) == 32'h02004020) != 1'b0),{({_zz_79,_zz_78} != 2'b00),{({_zz_241,_zz_242} != 3'b000),{(_zz_243 != _zz_244),{_zz_245,{_zz_246,_zz_247}}}}}}; - assign _zz_80 = _zz_72[1 : 0]; - assign _zz_47 = _zz_80; - assign _zz_81 = _zz_72[6 : 5]; - assign _zz_46 = _zz_81; - assign _zz_82 = _zz_72[13 : 12]; - assign _zz_45 = _zz_82; - assign _zz_83 = _zz_72[16 : 15]; - assign _zz_44 = _zz_83; - assign _zz_84 = _zz_72[19 : 18]; - assign _zz_43 = _zz_84; - assign _zz_85 = _zz_72[22 : 21]; - assign _zz_42 = _zz_85; - assign _zz_86 = _zz_72[25 : 24]; - assign _zz_41 = _zz_86; + assign _zz_59 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_60 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_61 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_62 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz_63 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_64 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_65 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00001000); + assign _zz_58 = {(_zz_65 != 1'b0),{({_zz_65,_zz_64} != 2'b00),{(_zz_230 != 1'b0),{(_zz_231 != _zz_232),{_zz_233,{_zz_234,_zz_235}}}}}}; + assign _zz_66 = _zz_58[2 : 1]; + assign _zz_35 = _zz_66; + assign _zz_67 = _zz_58[7 : 6]; + assign _zz_34 = _zz_67; + assign _zz_68 = _zz_58[14 : 13]; + assign _zz_33 = _zz_68; + assign _zz_69 = _zz_58[17 : 16]; + assign _zz_32 = _zz_69; + assign _zz_70 = _zz_58[20 : 19]; + assign _zz_31 = _zz_70; + assign _zz_71 = _zz_58[23 : 22]; + assign _zz_30 = _zz_71; + assign _zz_72 = _zz_58[26 : 25]; + assign _zz_29 = _zz_72; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_133; - assign decode_RegFilePlugin_rs2Data = _zz_134; + assign decode_RegFilePlugin_rs1Data = _zz_128; + assign decode_RegFilePlugin_rs2Data = _zz_129; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_39 && writeBack_arbitration_isFiring); - if(_zz_87)begin + lastStageRegFileWrite_valid = (_zz_27 && execute_arbitration_isFiring); + if(_zz_73)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_38[11 : 7]; - if(_zz_87)begin + lastStageRegFileWrite_payload_address = _zz_26[11 : 7]; + if(_zz_73)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_48; - if(_zz_87)begin + lastStageRegFileWrite_payload_data = _zz_36; + if(_zz_73)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -2782,101 +2284,101 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_88 = execute_IntAluPlugin_bitwise; + _zz_74 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_88 = {31'd0, _zz_191}; + _zz_74 = {31'd0, _zz_171}; end default : begin - _zz_88 = execute_SRC_ADD_SUB; + _zz_74 = execute_SRC_ADD_SUB; end endcase end always @ (*) begin - case(execute_SRC1_CTRL) + case(decode_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_89 = execute_RS1; + _zz_75 = _zz_22; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_89 = {29'd0, _zz_192}; + _zz_75 = {29'd0, _zz_172}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_89 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_75 = {decode_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_89 = {27'd0, _zz_193}; - end - endcase - end - - assign _zz_90 = _zz_194[11]; - always @ (*) begin - _zz_91[19] = _zz_90; - _zz_91[18] = _zz_90; - _zz_91[17] = _zz_90; - _zz_91[16] = _zz_90; - _zz_91[15] = _zz_90; - _zz_91[14] = _zz_90; - _zz_91[13] = _zz_90; - _zz_91[12] = _zz_90; - _zz_91[11] = _zz_90; - _zz_91[10] = _zz_90; - _zz_91[9] = _zz_90; - _zz_91[8] = _zz_90; - _zz_91[7] = _zz_90; - _zz_91[6] = _zz_90; - _zz_91[5] = _zz_90; - _zz_91[4] = _zz_90; - _zz_91[3] = _zz_90; - _zz_91[2] = _zz_90; - _zz_91[1] = _zz_90; - _zz_91[0] = _zz_90; + _zz_75 = {27'd0, _zz_173}; + end + endcase + end + + assign _zz_76 = _zz_174[11]; + always @ (*) begin + _zz_77[19] = _zz_76; + _zz_77[18] = _zz_76; + _zz_77[17] = _zz_76; + _zz_77[16] = _zz_76; + _zz_77[15] = _zz_76; + _zz_77[14] = _zz_76; + _zz_77[13] = _zz_76; + _zz_77[12] = _zz_76; + _zz_77[11] = _zz_76; + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7] = _zz_76; + _zz_77[6] = _zz_76; + _zz_77[5] = _zz_76; + _zz_77[4] = _zz_76; + _zz_77[3] = _zz_76; + _zz_77[2] = _zz_76; + _zz_77[1] = _zz_76; + _zz_77[0] = _zz_76; + end + + assign _zz_78 = _zz_175[11]; + always @ (*) begin + _zz_79[19] = _zz_78; + _zz_79[18] = _zz_78; + _zz_79[17] = _zz_78; + _zz_79[16] = _zz_78; + _zz_79[15] = _zz_78; + _zz_79[14] = _zz_78; + _zz_79[13] = _zz_78; + _zz_79[12] = _zz_78; + _zz_79[11] = _zz_78; + _zz_79[10] = _zz_78; + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7] = _zz_78; + _zz_79[6] = _zz_78; + _zz_79[5] = _zz_78; + _zz_79[4] = _zz_78; + _zz_79[3] = _zz_78; + _zz_79[2] = _zz_78; + _zz_79[1] = _zz_78; + _zz_79[0] = _zz_78; end - assign _zz_92 = _zz_195[11]; always @ (*) begin - _zz_93[19] = _zz_92; - _zz_93[18] = _zz_92; - _zz_93[17] = _zz_92; - _zz_93[16] = _zz_92; - _zz_93[15] = _zz_92; - _zz_93[14] = _zz_92; - _zz_93[13] = _zz_92; - _zz_93[12] = _zz_92; - _zz_93[11] = _zz_92; - _zz_93[10] = _zz_92; - _zz_93[9] = _zz_92; - _zz_93[8] = _zz_92; - _zz_93[7] = _zz_92; - _zz_93[6] = _zz_92; - _zz_93[5] = _zz_92; - _zz_93[4] = _zz_92; - _zz_93[3] = _zz_92; - _zz_93[2] = _zz_92; - _zz_93[1] = _zz_92; - _zz_93[0] = _zz_92; - end - - always @ (*) begin - case(execute_SRC2_CTRL) + case(decode_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_94 = execute_RS2; + _zz_80 = _zz_20; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_94 = {_zz_91,execute_INSTRUCTION[31 : 20]}; + _zz_80 = {_zz_77,decode_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_94 = {_zz_93,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_80 = {_zz_79,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; end default : begin - _zz_94 = _zz_33; + _zz_80 = _zz_19; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_196; + execute_SrcPlugin_addSub = _zz_176; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -2885,197 +2387,169 @@ module VexRiscv ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); - assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_95 = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_81 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_95 = _zz_203; + _zz_81 = _zz_183; end endcase end always @ (*) begin - _zz_96 = 1'b0; - if(_zz_98)begin - if((_zz_99 == decode_INSTRUCTION[19 : 15]))begin - _zz_96 = 1'b1; - end - end - if(_zz_145)begin - if(_zz_146)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_96 = 1'b1; - end - end - end - if(_zz_147)begin - if(_zz_148)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_96 = 1'b1; - end + _zz_82 = 1'b0; + if(_zz_84)begin + if((_zz_85 == decode_INSTRUCTION[19 : 15]))begin + _zz_82 = 1'b1; end end - if(_zz_149)begin - if(_zz_150)begin + if(_zz_142)begin + if(_zz_143)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_96 = 1'b1; + _zz_82 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_96 = 1'b0; + _zz_82 = 1'b0; end end always @ (*) begin - _zz_97 = 1'b0; - if(_zz_98)begin - if((_zz_99 == decode_INSTRUCTION[24 : 20]))begin - _zz_97 = 1'b1; - end - end - if(_zz_145)begin - if(_zz_146)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_97 = 1'b1; - end - end - end - if(_zz_147)begin - if(_zz_148)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_97 = 1'b1; - end + _zz_83 = 1'b0; + if(_zz_84)begin + if((_zz_85 == decode_INSTRUCTION[24 : 20]))begin + _zz_83 = 1'b1; end end - if(_zz_149)begin - if(_zz_150)begin + if(_zz_142)begin + if(_zz_143)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_97 = 1'b1; + _zz_83 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_97 = 1'b0; + _zz_83 = 1'b0; end end assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_100 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_100 == 3'b000)) begin - _zz_101 = execute_BranchPlugin_eq; - end else if((_zz_100 == 3'b001)) begin - _zz_101 = (! execute_BranchPlugin_eq); - end else if((((_zz_100 & 3'b101) == 3'b101))) begin - _zz_101 = (! execute_SRC_LESS); + assign _zz_86 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_86 == 3'b000)) begin + _zz_87 = execute_BranchPlugin_eq; + end else if((_zz_86 == 3'b001)) begin + _zz_87 = (! execute_BranchPlugin_eq); + end else if((((_zz_86 & 3'b101) == 3'b101))) begin + _zz_87 = (! execute_SRC_LESS); end else begin - _zz_101 = execute_SRC_LESS; + _zz_87 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_102 = 1'b0; + _zz_88 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_102 = 1'b1; + _zz_88 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_102 = 1'b1; + _zz_88 = 1'b1; end default : begin - _zz_102 = _zz_101; + _zz_88 = _zz_87; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_103 = _zz_205[19]; - always @ (*) begin - _zz_104[10] = _zz_103; - _zz_104[9] = _zz_103; - _zz_104[8] = _zz_103; - _zz_104[7] = _zz_103; - _zz_104[6] = _zz_103; - _zz_104[5] = _zz_103; - _zz_104[4] = _zz_103; - _zz_104[3] = _zz_103; - _zz_104[2] = _zz_103; - _zz_104[1] = _zz_103; - _zz_104[0] = _zz_103; - end - - assign _zz_105 = _zz_206[11]; - always @ (*) begin - _zz_106[19] = _zz_105; - _zz_106[18] = _zz_105; - _zz_106[17] = _zz_105; - _zz_106[16] = _zz_105; - _zz_106[15] = _zz_105; - _zz_106[14] = _zz_105; - _zz_106[13] = _zz_105; - _zz_106[12] = _zz_105; - _zz_106[11] = _zz_105; - _zz_106[10] = _zz_105; - _zz_106[9] = _zz_105; - _zz_106[8] = _zz_105; - _zz_106[7] = _zz_105; - _zz_106[6] = _zz_105; - _zz_106[5] = _zz_105; - _zz_106[4] = _zz_105; - _zz_106[3] = _zz_105; - _zz_106[2] = _zz_105; - _zz_106[1] = _zz_105; - _zz_106[0] = _zz_105; - end - - assign _zz_107 = _zz_207[11]; - always @ (*) begin - _zz_108[18] = _zz_107; - _zz_108[17] = _zz_107; - _zz_108[16] = _zz_107; - _zz_108[15] = _zz_107; - _zz_108[14] = _zz_107; - _zz_108[13] = _zz_107; - _zz_108[12] = _zz_107; - _zz_108[11] = _zz_107; - _zz_108[10] = _zz_107; - _zz_108[9] = _zz_107; - _zz_108[8] = _zz_107; - _zz_108[7] = _zz_107; - _zz_108[6] = _zz_107; - _zz_108[5] = _zz_107; - _zz_108[4] = _zz_107; - _zz_108[3] = _zz_107; - _zz_108[2] = _zz_107; - _zz_108[1] = _zz_107; - _zz_108[0] = _zz_107; + assign _zz_89 = _zz_185[19]; + always @ (*) begin + _zz_90[10] = _zz_89; + _zz_90[9] = _zz_89; + _zz_90[8] = _zz_89; + _zz_90[7] = _zz_89; + _zz_90[6] = _zz_89; + _zz_90[5] = _zz_89; + _zz_90[4] = _zz_89; + _zz_90[3] = _zz_89; + _zz_90[2] = _zz_89; + _zz_90[1] = _zz_89; + _zz_90[0] = _zz_89; + end + + assign _zz_91 = _zz_186[11]; + always @ (*) begin + _zz_92[19] = _zz_91; + _zz_92[18] = _zz_91; + _zz_92[17] = _zz_91; + _zz_92[16] = _zz_91; + _zz_92[15] = _zz_91; + _zz_92[14] = _zz_91; + _zz_92[13] = _zz_91; + _zz_92[12] = _zz_91; + _zz_92[11] = _zz_91; + _zz_92[10] = _zz_91; + _zz_92[9] = _zz_91; + _zz_92[8] = _zz_91; + _zz_92[7] = _zz_91; + _zz_92[6] = _zz_91; + _zz_92[5] = _zz_91; + _zz_92[4] = _zz_91; + _zz_92[3] = _zz_91; + _zz_92[2] = _zz_91; + _zz_92[1] = _zz_91; + _zz_92[0] = _zz_91; + end + + assign _zz_93 = _zz_187[11]; + always @ (*) begin + _zz_94[18] = _zz_93; + _zz_94[17] = _zz_93; + _zz_94[16] = _zz_93; + _zz_94[15] = _zz_93; + _zz_94[14] = _zz_93; + _zz_94[13] = _zz_93; + _zz_94[12] = _zz_93; + _zz_94[11] = _zz_93; + _zz_94[10] = _zz_93; + _zz_94[9] = _zz_93; + _zz_94[8] = _zz_93; + _zz_94[7] = _zz_93; + _zz_94[6] = _zz_93; + _zz_94[5] = _zz_93; + _zz_94[4] = _zz_93; + _zz_94[3] = _zz_93; + _zz_94[2] = _zz_93; + _zz_94[1] = _zz_93; + _zz_94[0] = _zz_93; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_109 = {{_zz_104,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_95 = {{_zz_90,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_109 = {_zz_106,execute_INSTRUCTION[31 : 20]}; + _zz_95 = {_zz_92,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_109 = {{_zz_108,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_95 = {{_zz_94,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_109; + assign execute_BranchPlugin_branch_src2 = _zz_95; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); - assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; always @ (*) begin CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin @@ -3085,14 +2559,16 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_110 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_111 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_112 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_96 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_97 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_98 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_99 = {CsrPlugin_selfException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_100 = _zz_188[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(IBusSimplePlugin_decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3102,7 +2578,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(_zz_137)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -3110,33 +2586,14 @@ module VexRiscv ( end end - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(DBusSimplePlugin_memoryExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; - end - end - - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(writeBack_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; - end - end - assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_0; + if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != 1'b0))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -3182,7 +2639,7 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + assign execute_CsrPlugin_blockedBySideEffects = (1'b0 || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; if(execute_CsrPlugin_csr_768)begin @@ -3230,7 +2687,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_151)begin + if(_zz_144)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3249,14 +2706,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_152)begin + if(_zz_145)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_152)begin + if(_zz_145)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3271,14 +2728,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_151)begin + if(_zz_144)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_151)begin + if(_zz_144)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -3287,7 +2744,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_163) + case(_zz_154) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3298,217 +2755,172 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign memory_MulDivIterativePlugin_frontendOk = 1'b1; - always @ (*) begin - memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_136)begin - if(_zz_140)begin - memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; - end - end - end - - always @ (*) begin - memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; - if((! memory_arbitration_isStuck))begin - memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; - end - end - - assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); - assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); - always @ (*) begin - if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; - end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_209); - end - if(memory_MulDivIterativePlugin_mul_counter_willClear)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; - end - end - always @ (*) begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_137)begin - if(_zz_153)begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + execute_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; + if(_zz_133)begin + if(_zz_136)begin + execute_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end end always @ (*) begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_154)begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + execute_MulDivIterativePlugin_mul_counter_willClear = 1'b0; + if((! execute_arbitration_isStuck))begin + execute_MulDivIterativePlugin_mul_counter_willClear = 1'b1; end end - assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); - assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + assign execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (execute_MulDivIterativePlugin_mul_counter_value == 6'h20); + assign execute_MulDivIterativePlugin_mul_counter_willOverflow = (execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc && execute_MulDivIterativePlugin_mul_counter_willIncrement); always @ (*) begin - if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + if(execute_MulDivIterativePlugin_mul_counter_willOverflow)begin + execute_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_217); - end - if(memory_MulDivIterativePlugin_div_counter_willClear)begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; - end - end - - assign _zz_113 = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_113[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_218); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_219 : _zz_220); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_221[31:0]; - assign _zz_114 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_115 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_116 = ((execute_IS_MUL && _zz_115) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_117[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_117[31 : 0] = execute_RS1; - end - - assign _zz_119 = (_zz_118 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_119 != 32'h0); - assign _zz_25 = decode_SRC1_CTRL; - assign _zz_23 = _zz_47; - assign _zz_35 = decode_to_execute_SRC1_CTRL; - assign _zz_22 = decode_SRC2_CTRL; - assign _zz_20 = _zz_46; - assign _zz_34 = decode_to_execute_SRC2_CTRL; - assign _zz_19 = decode_ALU_CTRL; - assign _zz_17 = _zz_45; - assign _zz_36 = decode_to_execute_ALU_CTRL; - assign _zz_16 = decode_ALU_BITWISE_CTRL; - assign _zz_14 = _zz_44; - assign _zz_37 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_13 = decode_SHIFT_CTRL; - assign _zz_11 = _zz_43; - assign _zz_32 = decode_to_execute_SHIFT_CTRL; - assign _zz_10 = decode_BRANCH_CTRL; - assign _zz_8 = _zz_42; - assign _zz_30 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_41; - assign _zz_28 = decode_to_execute_ENV_CTRL; - assign _zz_27 = execute_to_memory_ENV_CTRL; - assign _zz_29 = memory_to_writeBack_ENV_CTRL; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + execute_MulDivIterativePlugin_mul_counter_valueNext = (execute_MulDivIterativePlugin_mul_counter_value + _zz_191); + end + if(execute_MulDivIterativePlugin_mul_counter_willClear)begin + execute_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + end + end + + assign _zz_101 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_102 = ((execute_IS_MUL && _zz_101) || 1'b0); + always @ (*) begin + _zz_103[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_103[31 : 0] = execute_RS1; + end + + assign _zz_105 = (_zz_104 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_105 != 32'h0); + assign _zz_23 = _zz_35; + assign _zz_21 = _zz_34; + assign _zz_15 = decode_ALU_CTRL; + assign _zz_13 = _zz_33; + assign _zz_24 = decode_to_execute_ALU_CTRL; + assign _zz_12 = decode_ALU_BITWISE_CTRL; + assign _zz_10 = _zz_32; + assign _zz_25 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_9 = decode_SHIFT_CTRL; + assign _zz_7 = _zz_31; + assign _zz_18 = decode_to_execute_SHIFT_CTRL; + assign _zz_6 = decode_BRANCH_CTRL; + assign _zz_4 = _zz_30; + assign _zz_17 = decode_to_execute_BRANCH_CTRL; + assign _zz_3 = decode_ENV_CTRL; + assign _zz_1 = _zz_29; + assign _zz_16 = decode_to_execute_ENV_CTRL; + assign decode_arbitration_isFlushed = ((execute_arbitration_flushNext != 1'b0) || ({execute_arbitration_flushIt,decode_arbitration_flushIt} != 2'b00)); + assign execute_arbitration_isFlushed = (1'b0 || (execute_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0); assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); - assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); - assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); - assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); - assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); - assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); - assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); - assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_120 = 32'h0; + _zz_106 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_120[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_120[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_120[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_106[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_106[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_106[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_121 = 32'h0; + _zz_107 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_121[11 : 11] = CsrPlugin_mip_MEIP; - _zz_121[7 : 7] = CsrPlugin_mip_MTIP; - _zz_121[3 : 3] = CsrPlugin_mip_MSIP; + _zz_107[11 : 11] = CsrPlugin_mip_MEIP; + _zz_107[7 : 7] = CsrPlugin_mip_MTIP; + _zz_107[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_122 = 32'h0; + _zz_108 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_122[11 : 11] = CsrPlugin_mie_MEIE; - _zz_122[7 : 7] = CsrPlugin_mie_MTIE; - _zz_122[3 : 3] = CsrPlugin_mie_MSIE; + _zz_108[11 : 11] = CsrPlugin_mie_MEIE; + _zz_108[7 : 7] = CsrPlugin_mie_MTIE; + _zz_108[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_123 = 32'h0; + _zz_109 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_123[31 : 0] = CsrPlugin_mepc; + _zz_109[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_124 = 32'h0; + _zz_110 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_124[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_124[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_110[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_110[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_125 = 32'h0; + _zz_111 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_125[31 : 0] = CsrPlugin_mtval; + _zz_111[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_126 = 32'h0; + _zz_112 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_126[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_112[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_127 = 32'h0; + _zz_113 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_127[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_113[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_128 = 32'h0; + _zz_114 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_128[31 : 0] = _zz_118; + _zz_114[31 : 0] = _zz_104; end end always @ (*) begin - _zz_129 = 32'h0; + _zz_115 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_129[31 : 0] = _zz_119; + _zz_115[31 : 0] = _zz_105; end end - assign execute_CsrPlugin_readData = ((((_zz_120 | _zz_121) | (_zz_122 | _zz_123)) | ((_zz_124 | _zz_125) | (_zz_126 | _zz_127))) | (_zz_128 | _zz_129)); - assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); - assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; - assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; - assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); - assign iBusWishbone_CTI = 3'b000; + assign execute_CsrPlugin_readData = ((((_zz_106 | _zz_107) | (_zz_108 | _zz_109)) | ((_zz_110 | _zz_111) | (_zz_112 | _zz_113))) | (_zz_114 | _zz_115)); + assign iBusWishbone_ADR = {_zz_208,_zz_116}; + assign iBusWishbone_CTI = ((_zz_116 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; - assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; - assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; - assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK); - assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_146)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_146)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_117; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; @@ -3522,19 +2934,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_130 = 4'b0001; + _zz_118 = 4'b0001; end 2'b01 : begin - _zz_130 = 4'b0011; + _zz_118 = 4'b0011; end default : begin - _zz_130 = 4'b1111; + _zz_118 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_130 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_118 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -3548,25 +2960,23 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - assign _zz_132 = 1'b0; always @ (posedge clk) begin if(reset) begin - IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; - IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; - IBusSimplePlugin_fetchPc_booted <= 1'b0; - IBusSimplePlugin_fetchPc_inc <= 1'b0; - _zz_58 <= 1'b0; - _zz_59 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusSimplePlugin_pending_value <= 3'b000; - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; - _zz_87 <= 1'b1; + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_46 <= 1'b0; + _zz_48 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_50; + IBusCachedPlugin_rspCounter <= 32'h0; + _zz_51 <= 1'b0; + _zz_73 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_98 <= 1'b0; + _zz_84 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3575,125 +2985,86 @@ module VexRiscv ( CsrPlugin_mie_MSIE <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; - memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - _zz_118 <= 32'h0; + execute_MulDivIterativePlugin_frontendOk <= 1'b0; + execute_MulDivIterativePlugin_mul_counter_value <= 6'h0; + _zz_104 <= 32'h0; execute_arbitration_isValid <= 1'b0; - memory_arbitration_isValid <= 1'b0; - writeBack_arbitration_isValid <= 1'b0; - iBus_cmd_m2sPipe_rValid <= 1'b0; + _zz_116 <= 3'b000; + _zz_117 <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin - if(IBusSimplePlugin_fetchPc_correction)begin - IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin - IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end - IBusSimplePlugin_fetchPc_booted <= 1'b1; - if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin - IBusSimplePlugin_fetchPc_inc <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin - IBusSimplePlugin_fetchPc_inc <= 1'b1; + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin - IBusSimplePlugin_fetchPc_inc <= 1'b0; + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin - IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusSimplePlugin_iBusRsp_flush)begin - _zz_58 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_46 <= 1'b0; end - if(_zz_56)begin - _zz_58 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_44)begin + _zz_46 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(decode_arbitration_removeIt)begin - _zz_59 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_48 <= 1'b0; end - if(IBusSimplePlugin_iBusRsp_output_ready)begin - _zz_59 <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_48 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin - IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; - end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! memory_arbitration_isStuck))begin - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + if((dBus_cmd_valid && dBus_cmd_ready))begin + _zz_51 <= 1'b1; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if((! writeBack_arbitration_isStuck))begin - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; - end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_188); - if(IBusSimplePlugin_iBusRsp_flush)begin - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_190); + if((! execute_arbitration_isStuck))begin + _zz_51 <= 1'b0; end - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); - `else - if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin - $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); - $finish; - end - `endif - `endif - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); - `else - if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin - $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); - $finish; - end - `endif - `endif - _zz_87 <= 1'b0; - if(_zz_138)begin - if(_zz_155)begin + _zz_73 <= 1'b0; + if(_zz_131)begin + if(_zz_147)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -3703,7 +3074,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_98 <= (_zz_39 && writeBack_arbitration_isFiring); + _zz_84 <= (_zz_27 && execute_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -3712,27 +3083,17 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - end - if((! memory_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - end - if((! writeBack_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_156)begin - if(_zz_157)begin + if(_zz_148)begin + if(_zz_149)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_158)begin + if(_zz_150)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_159)begin + if(_zz_151)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -3740,23 +3101,15 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin - CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; - end - if((! writeBack_arbitration_isStuck))begin - CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; - end end if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end if(CsrPlugin_interruptJump)begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_141)begin + if(_zz_138)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3767,8 +3120,8 @@ module VexRiscv ( end endcase end - if(_zz_142)begin - case(_zz_162) + if(_zz_139)begin + case(_zz_140) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3778,50 +3131,46 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_112,{_zz_111,_zz_110}} != 3'b000) || CsrPlugin_thirdPartyWake); - memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; - memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; + execute_CsrPlugin_wfiWake <= (({_zz_98,{_zz_97,_zz_96}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(((execute_arbitration_isValid && (! 1'b0)) && (1'b0 || execute_IS_MUL)))begin + execute_MulDivIterativePlugin_frontendOk <= 1'b1; + end + if(execute_arbitration_isMoving)begin + execute_MulDivIterativePlugin_frontendOk <= 1'b0; + end + execute_MulDivIterativePlugin_mul_counter_value <= execute_MulDivIterativePlugin_mul_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin - memory_arbitration_isValid <= 1'b0; - end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin - memory_arbitration_isValid <= execute_arbitration_isValid; - end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin - writeBack_arbitration_isValid <= 1'b0; - end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; - end if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_231[0]; - CsrPlugin_mstatus_MIE <= _zz_232[0]; + CsrPlugin_mstatus_MPIE <= _zz_202[0]; + CsrPlugin_mstatus_MIE <= _zz_203[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_234[0]; - CsrPlugin_mie_MTIE <= _zz_235[0]; - CsrPlugin_mie_MSIE <= _zz_236[0]; + CsrPlugin_mie_MEIE <= _zz_205[0]; + CsrPlugin_mie_MTIE <= _zz_206[0]; + CsrPlugin_mie_MSIE <= _zz_207[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_118 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_104 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(iBus_cmd_ready)begin - iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; + if(_zz_146)begin + if(iBusWishbone_ACK)begin + _zz_116 <= (_zz_116 + 3'b001); + end end - if(_zz_160)begin + _zz_117 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_152)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -3832,71 +3181,59 @@ module VexRiscv ( end always @ (posedge clk) begin - if(IBusSimplePlugin_iBusRsp_output_ready)begin - _zz_60 <= IBusSimplePlugin_iBusRsp_output_payload_pc; - _zz_61 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; - _zz_62 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; - _zz_63 <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; - end - if(IBusSimplePlugin_injector_decodeInput_ready)begin - IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; - end - if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin - IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; - IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; - IBusSimplePlugin_mmu_joinCtx_isPaging <= IBusSimplePlugin_mmuBus_rsp_isPaging; - IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; - IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; - IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; - IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; - IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; - IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_49 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(_zz_138)begin - if(_zz_155)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_LightShifterPlugin_shiftReg <= _zz_36; + end + if(_zz_131)begin + if(_zz_147)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - _zz_99 <= _zz_38[11 : 7]; + _zz_85 <= _zz_26[11 : 7]; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(execute_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(IBusSimplePlugin_decodeExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= IBusSimplePlugin_decodeExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= IBusSimplePlugin_decodeExceptionPort_payload_badAddr; - end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + if(decodeExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= decodeExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= decodeExceptionPort_payload_badAddr; end - if(DBusSimplePlugin_memoryExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusSimplePlugin_memoryExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + if(_zz_137)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_100 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_100 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(_zz_156)begin - if(_zz_157)begin + if(_zz_148)begin + if(_zz_149)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_158)begin + if(_zz_150)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_159)begin + if(_zz_151)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_141)begin + if(_zz_138)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; + CsrPlugin_mepc <= execute_PC; if(CsrPlugin_hadException)begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end @@ -3905,139 +3242,63 @@ module VexRiscv ( end endcase end - if(_zz_136)begin - if(_zz_140)begin - memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_210,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); - end - end - if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_done <= 1'b1; - end - if((! memory_arbitration_isStuck))begin - memory_MulDivIterativePlugin_div_done <= 1'b0; - end - if(_zz_137)begin - if(_zz_153)begin - memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; - memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; - if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_result <= _zz_222[31:0]; - end + if(_zz_133)begin + if(_zz_136)begin + execute_MulDivIterativePlugin_rs2 <= (execute_MulDivIterativePlugin_rs2 >>> 1); + execute_MulDivIterativePlugin_accumulator <= ({_zz_192,execute_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end - if(_zz_154)begin - memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_116 ? (~ _zz_117) : _zz_117) + _zz_228); - memory_MulDivIterativePlugin_rs2 <= ((_zz_115 ? (~ execute_RS2) : execute_RS2) + _zz_230); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_116 ^ (_zz_115 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if((! execute_MulDivIterativePlugin_frontendOk))begin + execute_MulDivIterativePlugin_accumulator <= 65'h0; + execute_MulDivIterativePlugin_rs1 <= ((_zz_102 ? (~ _zz_103) : _zz_103) + _zz_199); + execute_MulDivIterativePlugin_rs2 <= ((_zz_101 ? (~ execute_RS2) : execute_RS2) + _zz_201); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_33; - end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin + decode_to_execute_PC <= _zz_19; end if((! execute_arbitration_isStuck))begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end if((! execute_arbitration_isStuck))begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_49; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_24; - end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_21; - end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; - end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; - end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_18; + decode_to_execute_ALU_CTRL <= _zz_14; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_15; + decode_to_execute_ALU_BITWISE_CTRL <= _zz_11; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_12; + decode_to_execute_SHIFT_CTRL <= _zz_8; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_9; + decode_to_execute_BRANCH_CTRL <= _zz_5; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_CSR <= decode_IS_CSR; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + decode_to_execute_ENV_CTRL <= _zz_2; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; - end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end @@ -4045,19 +3306,19 @@ module VexRiscv ( decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + decode_to_execute_RS1 <= _zz_22; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= _zz_20; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + decode_to_execute_SRC1 <= decode_SRC1; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + decode_to_execute_SRC2 <= decode_SRC2; end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; @@ -4065,41 +3326,6 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; - execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; - execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; - execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; - execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; - execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; - execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; - execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; - execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; - end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_26; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; - end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end @@ -4135,7 +3361,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_233[0]; + CsrPlugin_mip_MSIP <= _zz_204[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -4149,10 +3375,8 @@ module VexRiscv ( CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end end - if(iBus_cmd_ready)begin - iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; - end - if(_zz_160)begin + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_152)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; @@ -4163,129 +3387,285 @@ module VexRiscv ( endmodule -module StreamFifoLowLatency ( - input io_push_valid, - output io_push_ready, - input io_push_payload_error, - input [31:0] io_push_payload_inst, - output reg io_pop_valid, - input io_pop_ready, - output reg io_pop_payload_error, - output reg [31:0] io_pop_payload_inst, +module InstructionCache ( input io_flush, - output [0:0] io_occupancy, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, input clk, input reset ); - wire _zz_4; - wire [0:0] _zz_5; + reg [31:0] _zz_9; + reg [24:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [24:0] _zz_15; reg _zz_1; - reg pushPtr_willIncrement; - reg pushPtr_willClear; - wire pushPtr_willOverflowIfInc; - wire pushPtr_willOverflow; - reg popPtr_willIncrement; - reg popPtr_willClear; - wire popPtr_willOverflowIfInc; - wire popPtr_willOverflow; - wire ptrMatch; - reg risingOccupancy; - wire empty; - wire full; - wire pushing; - wire popping; - wire [32:0] _zz_2; - reg [32:0] _zz_3; - - assign _zz_4 = (! empty); - assign _zz_5 = _zz_2[0 : 0]; - always @ (*) begin - _zz_1 = 1'b0; - if(pushing)begin - _zz_1 = 1'b1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [4:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [3:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [22:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [6:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [6:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [3:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [22:0] fetchStage_read_waysValues_0_tag_address; + wire [24:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:127]; + (* ram_style = "block" *) reg [24:0] ways_0_tags [0:15]; + + assign _zz_11 = (! lineLoader_flushCounter[4]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (*) begin - pushPtr_willIncrement = 1'b0; - if(pushing)begin - pushPtr_willIncrement = 1'b1; + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; end end - always @ (*) begin - pushPtr_willClear = 1'b0; - if(io_flush)begin - pushPtr_willClear = 1'b1; + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; end end - assign pushPtr_willOverflowIfInc = 1'b1; - assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); - always @ (*) begin - popPtr_willIncrement = 1'b0; - if(popping)begin - popPtr_willIncrement = 1'b1; + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; end end always @ (*) begin - popPtr_willClear = 1'b0; - if(io_flush)begin - popPtr_willClear = 1'b1; + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; end end - assign popPtr_willOverflowIfInc = 1'b1; - assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); - assign ptrMatch = 1'b1; - assign empty = (ptrMatch && (! risingOccupancy)); - assign full = (ptrMatch && risingOccupancy); - assign pushing = (io_push_valid && io_push_ready); - assign popping = (io_pop_valid && io_pop_ready); - assign io_push_ready = (! full); always @ (*) begin - if(_zz_4)begin - io_pop_valid = 1'b1; - end else begin - io_pop_valid = io_push_valid; + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; end end - assign _zz_2 = _zz_3; always @ (*) begin - if(_zz_4)begin - io_pop_payload_error = _zz_5[0]; - end else begin - io_pop_payload_error = io_push_payload_error; + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end end end always @ (*) begin - if(_zz_4)begin - io_pop_payload_inst = _zz_2[32 : 1]; - end else begin - io_pop_payload_inst = io_push_payload_inst; + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; end - end - - assign io_occupancy = (risingOccupancy && ptrMatch); + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[4])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[4] ? lineLoader_address[8 : 5] : lineLoader_flushCounter[3 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[4]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 9]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[8 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[8 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[8 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[24 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 9])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; always @ (posedge clk) begin if(reset) begin - risingOccupancy <= 1'b0; + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; end else begin - if((pushing != popping))begin - risingOccupancy <= pushing; + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end if(io_flush)begin - risingOccupancy <= 1'b0; + lineLoader_flushPending <= 1'b1; + end + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end end end end always @ (posedge clk) begin - if(_zz_1)begin - _zz_3 <= {io_push_payload_inst,io_push_payload_error}; + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 5'h01); + end + _zz_3 <= lineLoader_flushCounter[4]; + if(_zz_12)begin + lineLoader_flushCounter <= 5'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml index 0967ef4..fa5fb80 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml @@ -1 +1,4 @@ -{} +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 512} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v index 72929d7..70b319e 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 848042f3e4812615884ef1061d617c4d5bf6e8c2 +// Git hash : 301554ed50130998df7c9b3fa2a900ddbefe2027 `define Input2Kind_defaultEncoding_type [0:0] @@ -61,15 +61,8 @@ module VexRiscv ( input CfuPlugin_bus_rsp_payload_response_ok, input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, input [31:0] externalInterruptArray, - input debug_bus_cmd_valid, - output reg debug_bus_cmd_ready, - input debug_bus_cmd_payload_wr, - input [7:0] debug_bus_cmd_payload_address, - input [31:0] debug_bus_cmd_payload_data, - output reg [31:0] debug_bus_rsp_data, - output debug_resetOut, - output iBusWishbone_CYC, - output iBusWishbone_STB, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, input iBusWishbone_ACK, output iBusWishbone_WE, output [29:0] iBusWishbone_ADR, @@ -91,22 +84,44 @@ module VexRiscv ( output [2:0] dBusWishbone_CTI, output [1:0] dBusWishbone_BTE, input clk, - input reset, - input debugReset + input reset ); + wire _zz_132; + wire _zz_133; + wire _zz_134; + wire _zz_135; + wire _zz_136; + wire _zz_137; + wire _zz_138; + wire _zz_139; + reg _zz_140; + reg [31:0] _zz_141; + reg [31:0] _zz_142; + reg [31:0] _zz_143; + reg [3:0] _zz_144; + reg [31:0] _zz_145; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_146; + wire _zz_147; wire _zz_148; wire _zz_149; - reg [31:0] _zz_150; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; - wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; - wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; + wire _zz_150; + wire _zz_151; + wire _zz_152; wire _zz_153; wire _zz_154; - wire _zz_155; + wire [1:0] _zz_155; wire _zz_156; wire _zz_157; wire _zz_158; @@ -115,268 +130,228 @@ module VexRiscv ( wire _zz_161; wire _zz_162; wire _zz_163; - wire [1:0] _zz_164; + wire _zz_164; wire _zz_165; wire _zz_166; wire _zz_167; - wire _zz_168; + wire [1:0] _zz_168; wire _zz_169; - wire _zz_170; - wire _zz_171; - wire _zz_172; - wire _zz_173; - wire _zz_174; - wire _zz_175; - wire _zz_176; - wire [5:0] _zz_177; - wire _zz_178; - wire _zz_179; - wire _zz_180; - wire _zz_181; - wire _zz_182; - wire _zz_183; - wire _zz_184; - wire [1:0] _zz_185; - wire _zz_186; + wire [0:0] _zz_170; + wire [0:0] _zz_171; + wire [0:0] _zz_172; + wire [0:0] _zz_173; + wire [0:0] _zz_174; + wire [0:0] _zz_175; + wire [0:0] _zz_176; + wire [0:0] _zz_177; + wire [0:0] _zz_178; + wire [0:0] _zz_179; + wire [0:0] _zz_180; + wire [0:0] _zz_181; + wire [0:0] _zz_182; + wire [0:0] _zz_183; + wire [2:0] _zz_184; + wire [2:0] _zz_185; + wire [31:0] _zz_186; wire [0:0] _zz_187; - wire [0:0] _zz_188; - wire [0:0] _zz_189; - wire [0:0] _zz_190; - wire [0:0] _zz_191; - wire [0:0] _zz_192; - wire [0:0] _zz_193; - wire [0:0] _zz_194; - wire [0:0] _zz_195; - wire [0:0] _zz_196; - wire [0:0] _zz_197; - wire [0:0] _zz_198; - wire [0:0] _zz_199; - wire [0:0] _zz_200; - wire [0:0] _zz_201; - wire [0:0] _zz_202; - wire [0:0] _zz_203; + wire [2:0] _zz_188; + wire [4:0] _zz_189; + wire [11:0] _zz_190; + wire [11:0] _zz_191; + wire [31:0] _zz_192; + wire [31:0] _zz_193; + wire [31:0] _zz_194; + wire [31:0] _zz_195; + wire [31:0] _zz_196; + wire [31:0] _zz_197; + wire [31:0] _zz_198; + wire [31:0] _zz_199; + wire [32:0] _zz_200; + wire [19:0] _zz_201; + wire [11:0] _zz_202; + wire [11:0] _zz_203; wire [2:0] _zz_204; - wire [2:0] _zz_205; - wire [31:0] _zz_206; - wire [2:0] _zz_207; - wire [0:0] _zz_208; - wire [2:0] _zz_209; - wire [0:0] _zz_210; - wire [2:0] _zz_211; - wire [0:0] _zz_212; - wire [2:0] _zz_213; - wire [0:0] _zz_214; - wire [2:0] _zz_215; - wire [0:0] _zz_216; - wire [2:0] _zz_217; - wire [4:0] _zz_218; - wire [11:0] _zz_219; - wire [11:0] _zz_220; - wire [31:0] _zz_221; - wire [31:0] _zz_222; - wire [31:0] _zz_223; - wire [31:0] _zz_224; - wire [31:0] _zz_225; - wire [31:0] _zz_226; - wire [31:0] _zz_227; - wire [31:0] _zz_228; - wire [32:0] _zz_229; - wire [19:0] _zz_230; - wire [11:0] _zz_231; - wire [11:0] _zz_232; - wire [1:0] _zz_233; - wire [1:0] _zz_234; - wire [9:0] _zz_235; - wire [7:0] _zz_236; - wire [0:0] _zz_237; - wire [5:0] _zz_238; - wire [33:0] _zz_239; - wire [32:0] _zz_240; - wire [33:0] _zz_241; - wire [32:0] _zz_242; - wire [33:0] _zz_243; - wire [32:0] _zz_244; + wire [9:0] _zz_205; + wire [7:0] _zz_206; + wire [0:0] _zz_207; + wire [5:0] _zz_208; + wire [33:0] _zz_209; + wire [32:0] _zz_210; + wire [33:0] _zz_211; + wire [32:0] _zz_212; + wire [33:0] _zz_213; + wire [32:0] _zz_214; + wire [0:0] _zz_215; + wire [32:0] _zz_216; + wire [0:0] _zz_217; + wire [31:0] _zz_218; + wire [0:0] _zz_219; + wire [0:0] _zz_220; + wire [0:0] _zz_221; + wire [0:0] _zz_222; + wire [0:0] _zz_223; + wire [0:0] _zz_224; + wire [26:0] _zz_225; + wire _zz_226; + wire _zz_227; + wire [1:0] _zz_228; + wire [31:0] _zz_229; + wire [31:0] _zz_230; + wire [31:0] _zz_231; + wire _zz_232; + wire [0:0] _zz_233; + wire [14:0] _zz_234; + wire [31:0] _zz_235; + wire [31:0] _zz_236; + wire [31:0] _zz_237; + wire _zz_238; + wire [0:0] _zz_239; + wire [8:0] _zz_240; + wire [31:0] _zz_241; + wire [31:0] _zz_242; + wire [31:0] _zz_243; + wire _zz_244; wire [0:0] _zz_245; - wire [5:0] _zz_246; - wire [32:0] _zz_247; + wire [2:0] _zz_246; + wire [31:0] _zz_247; wire [31:0] _zz_248; - wire [31:0] _zz_249; - wire [32:0] _zz_250; - wire [32:0] _zz_251; - wire [32:0] _zz_252; - wire [32:0] _zz_253; - wire [0:0] _zz_254; - wire [32:0] _zz_255; - wire [0:0] _zz_256; - wire [32:0] _zz_257; + wire [0:0] _zz_249; + wire [0:0] _zz_250; + wire _zz_251; + wire [0:0] _zz_252; + wire [24:0] _zz_253; + wire [31:0] _zz_254; + wire _zz_255; + wire _zz_256; + wire [0:0] _zz_257; wire [0:0] _zz_258; - wire [31:0] _zz_259; + wire [0:0] _zz_259; wire [0:0] _zz_260; - wire [0:0] _zz_261; + wire _zz_261; wire [0:0] _zz_262; - wire [0:0] _zz_263; - wire [0:0] _zz_264; - wire [0:0] _zz_265; + wire [19:0] _zz_263; + wire [31:0] _zz_264; + wire [31:0] _zz_265; wire _zz_266; wire _zz_267; - wire [1:0] _zz_268; - wire [31:0] _zz_269; - wire [31:0] _zz_270; - wire [31:0] _zz_271; + wire _zz_268; + wire [2:0] _zz_269; + wire [2:0] _zz_270; + wire _zz_271; wire [0:0] _zz_272; - wire [0:0] _zz_273; - wire [2:0] _zz_274; - wire [2:0] _zz_275; + wire [16:0] _zz_273; + wire [31:0] _zz_274; + wire [31:0] _zz_275; wire _zz_276; - wire [0:0] _zz_277; - wire [26:0] _zz_278; - wire [31:0] _zz_279; + wire _zz_277; + wire _zz_278; + wire [0:0] _zz_279; wire [0:0] _zz_280; - wire [0:0] _zz_281; - wire _zz_282; + wire _zz_281; + wire [0:0] _zz_282; wire [0:0] _zz_283; - wire [22:0] _zz_284; - wire [31:0] _zz_285; - wire _zz_286; - wire _zz_287; - wire [0:0] _zz_288; - wire [0:0] _zz_289; - wire [0:0] _zz_290; - wire [0:0] _zz_291; - wire _zz_292; - wire [0:0] _zz_293; - wire [18:0] _zz_294; - wire [31:0] _zz_295; - wire [31:0] _zz_296; - wire _zz_297; - wire _zz_298; - wire [0:0] _zz_299; + wire _zz_284; + wire [0:0] _zz_285; + wire [13:0] _zz_286; + wire [31:0] _zz_287; + wire [31:0] _zz_288; + wire [31:0] _zz_289; + wire [31:0] _zz_290; + wire [31:0] _zz_291; + wire [31:0] _zz_292; + wire [31:0] _zz_293; + wire [31:0] _zz_294; + wire [0:0] _zz_295; + wire [0:0] _zz_296; + wire [1:0] _zz_297; + wire [1:0] _zz_298; + wire _zz_299; wire [0:0] _zz_300; - wire [2:0] _zz_301; - wire [2:0] _zz_302; - wire _zz_303; - wire [0:0] _zz_304; - wire [15:0] _zz_305; + wire [11:0] _zz_301; + wire [31:0] _zz_302; + wire [31:0] _zz_303; + wire [31:0] _zz_304; + wire [31:0] _zz_305; wire [31:0] _zz_306; wire [31:0] _zz_307; - wire [31:0] _zz_308; - wire [31:0] _zz_309; - wire _zz_310; - wire _zz_311; + wire [0:0] _zz_308; + wire [1:0] _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; wire _zz_312; wire [0:0] _zz_313; - wire [0:0] _zz_314; - wire _zz_315; - wire [0:0] _zz_316; - wire [0:0] _zz_317; - wire _zz_318; - wire [0:0] _zz_319; - wire [12:0] _zz_320; - wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [31:0] _zz_326; - wire [31:0] _zz_327; - wire [31:0] _zz_328; - wire [0:0] _zz_329; - wire [0:0] _zz_330; - wire [1:0] _zz_331; - wire [1:0] _zz_332; - wire _zz_333; - wire [0:0] _zz_334; - wire [10:0] _zz_335; - wire [31:0] _zz_336; - wire [31:0] _zz_337; + wire [8:0] _zz_314; + wire [31:0] _zz_315; + wire [31:0] _zz_316; + wire [31:0] _zz_317; + wire [31:0] _zz_318; + wire [31:0] _zz_319; + wire _zz_320; + wire _zz_321; + wire [5:0] _zz_322; + wire [5:0] _zz_323; + wire _zz_324; + wire [0:0] _zz_325; + wire [5:0] _zz_326; + wire _zz_327; + wire [0:0] _zz_328; + wire [2:0] _zz_329; + wire _zz_330; + wire [0:0] _zz_331; + wire [0:0] _zz_332; + wire [3:0] _zz_333; + wire [3:0] _zz_334; + wire _zz_335; + wire [0:0] _zz_336; + wire [2:0] _zz_337; wire [31:0] _zz_338; wire [31:0] _zz_339; wire [31:0] _zz_340; - wire [31:0] _zz_341; + wire [0:0] _zz_341; wire [0:0] _zz_342; - wire [1:0] _zz_343; - wire [0:0] _zz_344; - wire [0:0] _zz_345; + wire [31:0] _zz_343; + wire [31:0] _zz_344; + wire [31:0] _zz_345; wire _zz_346; wire [0:0] _zz_347; - wire [7:0] _zz_348; - wire [31:0] _zz_349; - wire [31:0] _zz_350; - wire [31:0] _zz_351; - wire [31:0] _zz_352; - wire [31:0] _zz_353; - wire _zz_354; - wire _zz_355; - wire [0:0] _zz_356; - wire [1:0] _zz_357; - wire [5:0] _zz_358; - wire [5:0] _zz_359; - wire _zz_360; - wire [0:0] _zz_361; - wire [4:0] _zz_362; + wire [1:0] _zz_348; + wire _zz_349; + wire [2:0] _zz_350; + wire [2:0] _zz_351; + wire _zz_352; + wire [0:0] _zz_353; + wire [0:0] _zz_354; + wire [31:0] _zz_355; + wire [31:0] _zz_356; + wire [31:0] _zz_357; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire [31:0] _zz_360; + wire [31:0] _zz_361; + wire _zz_362; wire [31:0] _zz_363; - wire [31:0] _zz_364; - wire [31:0] _zz_365; - wire [31:0] _zz_366; - wire _zz_367; + wire _zz_364; + wire [0:0] _zz_365; + wire [0:0] _zz_366; + wire [0:0] _zz_367; wire [0:0] _zz_368; - wire [2:0] _zz_369; - wire _zz_370; + wire [1:0] _zz_369; + wire [1:0] _zz_370; wire [0:0] _zz_371; wire [0:0] _zz_372; - wire [3:0] _zz_373; - wire [3:0] _zz_374; - wire _zz_375; - wire [0:0] _zz_376; - wire [1:0] _zz_377; + wire [31:0] _zz_373; + wire [31:0] _zz_374; + wire [31:0] _zz_375; + wire [31:0] _zz_376; + wire [31:0] _zz_377; wire [31:0] _zz_378; - wire [31:0] _zz_379; - wire [31:0] _zz_380; - wire _zz_381; - wire [0:0] _zz_382; - wire [0:0] _zz_383; - wire [31:0] _zz_384; - wire [31:0] _zz_385; - wire [31:0] _zz_386; - wire _zz_387; - wire [0:0] _zz_388; - wire [1:0] _zz_389; - wire _zz_390; - wire [2:0] _zz_391; - wire [2:0] _zz_392; - wire _zz_393; - wire _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire [31:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire [31:0] _zz_402; - wire _zz_403; - wire [31:0] _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [0:0] _zz_407; - wire [0:0] _zz_408; - wire [0:0] _zz_409; - wire [0:0] _zz_410; - wire [0:0] _zz_411; - wire [31:0] memory_MEMORY_READ_DATA; - wire writeBack_CfuPlugin_CFU_IN_FLIGHT; - wire execute_CfuPlugin_CFU_IN_FLIGHT; - wire [31:0] writeBack_REGFILE_WRITE_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire decode_DO_EBREAK; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; + wire [31:0] decode_SRC2; + wire [31:0] decode_SRC1; wire decode_SRC2_FORCE_ZERO; wire [31:0] decode_RS2; wire [31:0] decode_RS1; - wire decode_IS_DIV; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_MUL; @@ -385,139 +360,91 @@ module VexRiscv ( wire `Input2Kind_defaultEncoding_type _zz_2; wire `Input2Kind_defaultEncoding_type _zz_3; wire decode_CfuPlugin_CFU_ENABLE; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_4; wire `EnvCtrlEnum_defaultEncoding_type _zz_5; wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10; wire decode_IS_CSR; wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12; - wire `BranchCtrlEnum_defaultEncoding_type _zz_13; + wire `BranchCtrlEnum_defaultEncoding_type _zz_7; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_13; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; wire decode_SRC_LESS_UNSIGNED; wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_16; + wire `AluCtrlEnum_defaultEncoding_type _zz_17; + wire `AluCtrlEnum_defaultEncoding_type _zz_18; wire decode_MEMORY_STORE; - wire execute_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_MEMORY_STAGE; - wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `Src2CtrlEnum_defaultEncoding_type _zz_24; - wire `Src2CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; - wire `Src1CtrlEnum_defaultEncoding_type _zz_28; - wire [31:0] writeBack_FORMAL_PC_NEXT; - wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; - wire execute_DO_EBREAK; - wire decode_IS_EBREAK; wire execute_IS_RS1_SIGNED; - wire execute_IS_DIV; - wire execute_IS_MUL; wire execute_IS_RS2_SIGNED; - wire memory_IS_DIV; - wire memory_IS_MUL; - reg _zz_29; - reg _zz_30; - reg [31:0] _zz_31; - wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire execute_IS_MUL; + wire execute_CfuPlugin_CFU_IN_FLIGHT; wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_32; + wire `Input2Kind_defaultEncoding_type _zz_19; wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_defaultEncoding_type _zz_20; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; - wire [31:0] execute_PC; wire [31:0] execute_RS1; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire `BranchCtrlEnum_defaultEncoding_type _zz_21; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; - wire execute_BYPASSABLE_EXECUTE_STAGE; - wire memory_REGFILE_WRITE_VALID; - wire [31:0] memory_INSTRUCTION; - wire memory_BYPASSABLE_MEMORY_STAGE; - wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] _zz_37; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_38; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_22; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_39; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_40; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_41; + wire [31:0] _zz_23; + wire [31:0] _zz_24; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_25; + wire [31:0] _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_42; + wire `AluCtrlEnum_defaultEncoding_type _zz_28; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; - wire [31:0] _zz_44; - wire _zz_45; - reg _zz_46; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] _zz_30; + wire _zz_31; + reg _zz_32; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; - wire `Input2Kind_defaultEncoding_type _zz_47; - wire `EnvCtrlEnum_defaultEncoding_type _zz_48; - wire `BranchCtrlEnum_defaultEncoding_type _zz_49; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_50; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_51; - wire `AluCtrlEnum_defaultEncoding_type _zz_52; - wire `Src2CtrlEnum_defaultEncoding_type _zz_53; - wire `Src1CtrlEnum_defaultEncoding_type _zz_54; - wire writeBack_MEMORY_STORE; - reg [31:0] _zz_55; - wire writeBack_MEMORY_ENABLE; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP2_physicalAddress; - wire memory_MMU_RSP2_isIoAccess; - wire memory_MMU_RSP2_isPaging; - wire memory_MMU_RSP2_allowRead; - wire memory_MMU_RSP2_allowWrite; - wire memory_MMU_RSP2_allowExecute; - wire memory_MMU_RSP2_exception; - wire memory_MMU_RSP2_refilling; - wire memory_MMU_RSP2_bypassTranslation; - wire [31:0] memory_PC; - wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_STORE; - wire memory_MEMORY_ENABLE; + wire decode_LEGAL_INSTRUCTION; + wire `Input2Kind_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; + wire `BranchCtrlEnum_defaultEncoding_type _zz_35; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_36; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_37; + wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire `Src2CtrlEnum_defaultEncoding_type _zz_39; + wire `Src1CtrlEnum_defaultEncoding_type _zz_40; + reg [31:0] _zz_41; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] execute_MEMORY_READ_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; wire execute_MMU_FAULT; wire [31:0] execute_MMU_RSP2_physicalAddress; wire execute_MMU_RSP2_isIoAccess; @@ -530,30 +457,30 @@ module VexRiscv ( wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; wire [31:0] execute_RS2; - wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; wire decode_MEMORY_ENABLE; - reg [31:0] _zz_56; - reg [31:0] _zz_57; - wire [31:0] decode_PC; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; wire [31:0] decode_INSTRUCTION; - wire [31:0] writeBack_PC; - wire [31:0] writeBack_INSTRUCTION; + wire [31:0] decode_PC; + wire [31:0] execute_PC; + wire [31:0] execute_INSTRUCTION; reg decode_arbitration_haltItself; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; wire decode_arbitration_flushIt; reg decode_arbitration_flushNext; - reg decode_arbitration_isValid; + wire decode_arbitration_isValid; wire decode_arbitration_isStuck; wire decode_arbitration_isStuckByOthers; wire decode_arbitration_isFlushed; wire decode_arbitration_isMoving; wire decode_arbitration_isFiring; reg execute_arbitration_haltItself; - reg execute_arbitration_haltByOther; + wire execute_arbitration_haltByOther; reg execute_arbitration_removeIt; reg execute_arbitration_flushIt; reg execute_arbitration_flushNext; @@ -563,62 +490,29 @@ module VexRiscv ( wire execute_arbitration_isFlushed; wire execute_arbitration_isMoving; wire execute_arbitration_isFiring; - reg memory_arbitration_haltItself; - wire memory_arbitration_haltByOther; - reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; - reg memory_arbitration_flushNext; - reg memory_arbitration_isValid; - wire memory_arbitration_isStuck; - wire memory_arbitration_isStuckByOthers; - wire memory_arbitration_isFlushed; - wire memory_arbitration_isMoving; - wire memory_arbitration_isFiring; - wire writeBack_arbitration_haltItself; - wire writeBack_arbitration_haltByOther; - reg writeBack_arbitration_removeIt; - wire writeBack_arbitration_flushIt; - reg writeBack_arbitration_flushNext; - reg writeBack_arbitration_isValid; - wire writeBack_arbitration_isStuck; - wire writeBack_arbitration_isStuckByOthers; - wire writeBack_arbitration_isFlushed; - wire writeBack_arbitration_isMoving; - wire writeBack_arbitration_isFiring; wire [31:0] lastStageInstruction /* verilator public */ ; wire [31:0] lastStagePc /* verilator public */ ; wire lastStageIsValid /* verilator public */ ; wire lastStageIsFiring /* verilator public */ ; - reg IBusSimplePlugin_fetcherHalt; - reg IBusSimplePlugin_incomingInstruction; - wire IBusSimplePlugin_pcValids_0; - wire IBusSimplePlugin_pcValids_1; - wire IBusSimplePlugin_pcValids_2; - wire IBusSimplePlugin_pcValids_3; - wire iBus_cmd_valid; - wire iBus_cmd_ready; - wire [31:0] iBus_cmd_payload_pc; - wire iBus_rsp_valid; - wire iBus_rsp_payload_error; - wire [31:0] iBus_rsp_payload_inst; - wire IBusSimplePlugin_decodeExceptionPort_valid; - reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; - wire IBusSimplePlugin_mmuBus_cmd_0_isValid; - wire IBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire IBusSimplePlugin_mmuBus_rsp_isPaging; - wire IBusSimplePlugin_mmuBus_rsp_allowRead; - wire IBusSimplePlugin_mmuBus_rsp_allowWrite; - wire IBusSimplePlugin_mmuBus_rsp_allowExecute; - wire IBusSimplePlugin_mmuBus_rsp_exception; - wire IBusSimplePlugin_mmuBus_rsp_refilling; - wire IBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire IBusSimplePlugin_mmuBus_end; - wire IBusSimplePlugin_mmuBus_busy; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; reg DBusSimplePlugin_memoryExceptionPort_valid; reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; @@ -639,132 +533,107 @@ module VexRiscv ( wire DBusSimplePlugin_mmuBus_busy; reg DBusSimplePlugin_redoBranch_valid; wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; wire CsrPlugin_inWfi /* verilator public */ ; - reg CsrPlugin_thirdPartyWake; + wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; reg [31:0] CsrPlugin_jumpInterface_payload; wire CsrPlugin_exceptionPendings_0; wire CsrPlugin_exceptionPendings_1; - wire CsrPlugin_exceptionPendings_2; - wire CsrPlugin_exceptionPendings_3; wire externalInterrupt; wire contextSwitching; reg [1:0] CsrPlugin_privilege; - reg CsrPlugin_forceMachineWire; + wire CsrPlugin_forceMachineWire; reg CsrPlugin_selfException_valid; reg [3:0] CsrPlugin_selfException_payload_code; wire [31:0] CsrPlugin_selfException_payload_badAddr; - reg CsrPlugin_allowInterrupts; - reg CsrPlugin_allowException; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; reg CfuPlugin_joinException_valid; wire [3:0] CfuPlugin_joinException_payload_code; wire [31:0] CfuPlugin_joinException_payload_badAddr; - reg IBusSimplePlugin_injectionPort_valid; - reg IBusSimplePlugin_injectionPort_ready; - wire [31:0] IBusSimplePlugin_injectionPort_payload; - wire IBusSimplePlugin_externalFlush; - wire IBusSimplePlugin_jump_pcLoad_valid; - wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; - wire [2:0] _zz_58; - wire [2:0] _zz_59; - wire _zz_60; - wire _zz_61; - wire IBusSimplePlugin_fetchPc_output_valid; - wire IBusSimplePlugin_fetchPc_output_ready; - wire [31:0] IBusSimplePlugin_fetchPc_output_payload; - reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; - reg IBusSimplePlugin_fetchPc_correction; - reg IBusSimplePlugin_fetchPc_correctionReg; - wire IBusSimplePlugin_fetchPc_corrected; - reg IBusSimplePlugin_fetchPc_pcRegPropagate; - reg IBusSimplePlugin_fetchPc_booted; - reg IBusSimplePlugin_fetchPc_inc; - reg [31:0] IBusSimplePlugin_fetchPc_pc; - wire IBusSimplePlugin_fetchPc_redo_valid; - wire [31:0] IBusSimplePlugin_fetchPc_redo_payload; - reg IBusSimplePlugin_fetchPc_flushed; - reg IBusSimplePlugin_iBusRsp_redoFetch; - wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; - wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; - wire IBusSimplePlugin_iBusRsp_stages_0_output_valid; - wire IBusSimplePlugin_iBusRsp_stages_0_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_output_payload; - reg IBusSimplePlugin_iBusRsp_stages_0_halt; - wire IBusSimplePlugin_iBusRsp_stages_1_input_valid; - wire IBusSimplePlugin_iBusRsp_stages_1_input_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_input_payload; - wire IBusSimplePlugin_iBusRsp_stages_1_output_valid; - wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; - wire IBusSimplePlugin_iBusRsp_stages_1_halt; - wire _zz_62; - wire _zz_63; - wire IBusSimplePlugin_iBusRsp_flush; - wire _zz_64; - wire _zz_65; - reg _zz_66; - reg IBusSimplePlugin_iBusRsp_readyForError; - wire IBusSimplePlugin_iBusRsp_output_valid; - wire IBusSimplePlugin_iBusRsp_output_ready; - wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_pc; - wire IBusSimplePlugin_iBusRsp_output_payload_rsp_error; - wire [31:0] IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; - wire IBusSimplePlugin_iBusRsp_output_payload_isRvc; - wire IBusSimplePlugin_injector_decodeInput_valid; - wire IBusSimplePlugin_injector_decodeInput_ready; - wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_pc; - wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; - wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; - wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; - reg _zz_67; - reg [31:0] _zz_68; - reg _zz_69; - reg [31:0] _zz_70; - reg _zz_71; - reg IBusSimplePlugin_injector_nextPcCalc_valids_0; - reg IBusSimplePlugin_injector_nextPcCalc_valids_1; - reg IBusSimplePlugin_injector_nextPcCalc_valids_2; - reg IBusSimplePlugin_injector_nextPcCalc_valids_3; - reg IBusSimplePlugin_injector_nextPcCalc_valids_4; - reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; - reg IBusSimplePlugin_cmd_valid; - wire IBusSimplePlugin_cmd_ready; - wire [31:0] IBusSimplePlugin_cmd_payload_pc; - wire IBusSimplePlugin_pending_inc; - wire IBusSimplePlugin_pending_dec; - reg [2:0] IBusSimplePlugin_pending_value; - wire [2:0] IBusSimplePlugin_pending_next; - wire IBusSimplePlugin_cmdFork_canEmit; - reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; - reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; - reg IBusSimplePlugin_mmu_joinCtx_isPaging; - reg IBusSimplePlugin_mmu_joinCtx_allowRead; - reg IBusSimplePlugin_mmu_joinCtx_allowWrite; - reg IBusSimplePlugin_mmu_joinCtx_allowExecute; - reg IBusSimplePlugin_mmu_joinCtx_exception; - reg IBusSimplePlugin_mmu_joinCtx_refilling; - reg IBusSimplePlugin_mmu_joinCtx_bypassTranslation; - wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; - wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; - wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; - wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; - reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; - wire IBusSimplePlugin_rspJoin_rspBuffer_flush; - wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; - reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; - wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; - wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; - wire IBusSimplePlugin_rspJoin_join_valid; - wire IBusSimplePlugin_rspJoin_join_ready; - wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; - wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; - wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; - wire IBusSimplePlugin_rspJoin_join_payload_isRvc; - reg IBusSimplePlugin_rspJoin_exceptionDetected; - wire _zz_72; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_42; + wire [2:0] _zz_43; + wire _zz_44; + wire _zz_45; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_46; + wire _zz_47; + wire _zz_48; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_49; + wire _zz_50; + reg _zz_51; + wire _zz_52; + reg _zz_53; + reg [31:0] _zz_54; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_55; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; wire dBus_cmd_valid; wire dBus_cmd_ready; wire dBus_cmd_payload_wr; @@ -774,34 +643,34 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - wire _zz_73; + reg _zz_56; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_74; - reg [3:0] _zz_75; + reg [31:0] _zz_57; + reg [3:0] _zz_58; wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_76; - reg [31:0] _zz_77; - wire _zz_78; - reg [31:0] _zz_79; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [32:0] _zz_80; - wire _zz_81; - wire _zz_82; - wire _zz_83; - wire _zz_84; - wire _zz_85; - wire _zz_86; - wire _zz_87; - wire _zz_88; - wire `Src1CtrlEnum_defaultEncoding_type _zz_89; - wire `Src2CtrlEnum_defaultEncoding_type _zz_90; - wire `AluCtrlEnum_defaultEncoding_type _zz_91; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_92; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_93; - wire `BranchCtrlEnum_defaultEncoding_type _zz_94; - wire `EnvCtrlEnum_defaultEncoding_type _zz_95; - wire `Input2Kind_defaultEncoding_type _zz_96; + reg [31:0] execute_DBusSimplePlugin_rspShifted; + wire _zz_59; + reg [31:0] _zz_60; + wire _zz_61; + reg [31:0] _zz_62; + reg [31:0] execute_DBusSimplePlugin_rspFormated; + wire [31:0] _zz_63; + wire _zz_64; + wire _zz_65; + wire _zz_66; + wire _zz_67; + wire _zz_68; + wire _zz_69; + wire _zz_70; + wire _zz_71; + wire `Src1CtrlEnum_defaultEncoding_type _zz_72; + wire `Src2CtrlEnum_defaultEncoding_type _zz_73; + wire `AluCtrlEnum_defaultEncoding_type _zz_74; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_75; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_76; + wire `BranchCtrlEnum_defaultEncoding_type _zz_77; + wire `EnvCtrlEnum_defaultEncoding_type _zz_78; + wire `Input2Kind_defaultEncoding_type _zz_79; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -809,40 +678,41 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_97; + reg _zz_80; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_98; - reg [31:0] _zz_99; - wire _zz_100; - reg [19:0] _zz_101; - wire _zz_102; - reg [19:0] _zz_103; - reg [31:0] _zz_104; + reg [31:0] _zz_81; + reg [31:0] _zz_82; + wire _zz_83; + reg [19:0] _zz_84; + wire _zz_85; + reg [19:0] _zz_86; + reg [31:0] _zz_87; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; wire execute_LightShifterPlugin_isShift; reg [4:0] execute_LightShifterPlugin_amplitudeReg; wire [4:0] execute_LightShifterPlugin_amplitude; + reg [31:0] execute_LightShifterPlugin_shiftReg; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_105; - reg _zz_106; - reg _zz_107; - reg _zz_108; - reg [4:0] _zz_109; + reg [31:0] _zz_88; + reg _zz_89; + reg _zz_90; + reg _zz_91; + reg [4:0] _zz_92; wire execute_BranchPlugin_eq; - wire [2:0] _zz_110; - reg _zz_111; - reg _zz_112; + wire [2:0] _zz_93; + reg _zz_94; + reg _zz_95; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_113; - reg [10:0] _zz_114; - wire _zz_115; - reg [19:0] _zz_116; - wire _zz_117; - reg [18:0] _zz_118; - reg [31:0] _zz_119; + wire _zz_96; + reg [10:0] _zz_97; + wire _zz_98; + reg [19:0] _zz_99; + wire _zz_100; + reg [18:0] _zz_101; + reg [31:0] _zz_102; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -864,31 +734,28 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_120; - wire _zz_121; - wire _zz_122; + wire _zz_103; + wire _zz_104; + wire _zz_105; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_123; - wire _zz_124; + wire [2:0] _zz_106; + wire [2:0] _zz_107; + wire _zz_108; + wire _zz_109; + wire [1:0] _zz_110; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; - reg CsrPlugin_pipelineLiberator_pcValids_1; - reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; reg CsrPlugin_pipelineLiberator_done; wire CsrPlugin_interruptJump /* verilator public */ ; @@ -913,83 +780,36 @@ module VexRiscv ( reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_125; - reg [23:0] _zz_126; - reg [31:0] _zz_127; - wire memory_CfuPlugin_rsp_valid; - reg memory_CfuPlugin_rsp_ready; - wire memory_CfuPlugin_rsp_payload_response_ok; - wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_s2mPipe_rValid; - reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - wire memory_MulDivIterativePlugin_frontendOk; - reg memory_MulDivIterativePlugin_mul_counter_willIncrement; - reg memory_MulDivIterativePlugin_mul_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; - wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_mul_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_needRevert; - reg memory_MulDivIterativePlugin_div_counter_willIncrement; - reg memory_MulDivIterativePlugin_div_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_div_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_div_counter_value; - wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_div_counter_willOverflow; - reg memory_MulDivIterativePlugin_div_done; - reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_128; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; - wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; - wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [31:0] _zz_129; - wire _zz_130; - wire _zz_131; - reg [32:0] _zz_132; + wire _zz_111; + reg [23:0] _zz_112; + reg [31:0] _zz_113; + wire execute_CfuPlugin_rsp_valid; + reg execute_CfuPlugin_rsp_ready; + wire execute_CfuPlugin_rsp_payload_response_ok; + wire [31:0] execute_CfuPlugin_rsp_payload_outputs_0; + reg [32:0] execute_MulDivIterativePlugin_rs1; + reg [31:0] execute_MulDivIterativePlugin_rs2; + reg [64:0] execute_MulDivIterativePlugin_accumulator; + reg execute_MulDivIterativePlugin_frontendOk; + reg execute_MulDivIterativePlugin_mul_counter_willIncrement; + reg execute_MulDivIterativePlugin_mul_counter_willClear; + reg [5:0] execute_MulDivIterativePlugin_mul_counter_valueNext; + reg [5:0] execute_MulDivIterativePlugin_mul_counter_value; + wire execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc; + wire execute_MulDivIterativePlugin_mul_counter_willOverflow; + wire _zz_114; + wire _zz_115; + reg [32:0] _zz_116; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_133; - wire [31:0] _zz_134; - reg DebugPlugin_firstCycle; - reg DebugPlugin_secondCycle; - reg DebugPlugin_resetIt; - reg DebugPlugin_haltIt; - reg DebugPlugin_stepIt; - reg DebugPlugin_isPipBusy; - reg DebugPlugin_godmode; - reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_135; - wire DebugPlugin_allowEBreak; - reg DebugPlugin_resetIt_regNext; + reg [31:0] _zz_117; + wire [31:0] _zz_118; reg [31:0] decode_to_execute_PC; - reg [31:0] execute_to_memory_PC; - reg [31:0] memory_to_writeBack_PC; reg [31:0] decode_to_execute_INSTRUCTION; - reg [31:0] execute_to_memory_INSTRUCTION; - reg [31:0] memory_to_writeBack_INSTRUCTION; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; - reg [31:0] execute_to_memory_FORMAL_PC_NEXT; - reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; reg decode_to_execute_SRC_USE_SUB_LESS; reg decode_to_execute_MEMORY_ENABLE; - reg execute_to_memory_MEMORY_ENABLE; - reg memory_to_writeBack_MEMORY_ENABLE; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; reg decode_to_execute_REGFILE_WRITE_VALID; - reg execute_to_memory_REGFILE_WRITE_VALID; - reg memory_to_writeBack_REGFILE_WRITE_VALID; - reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; - reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; reg decode_to_execute_MEMORY_STORE; - reg execute_to_memory_MEMORY_STORE; - reg memory_to_writeBack_MEMORY_STORE; reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; reg decode_to_execute_SRC_LESS_UNSIGNED; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; @@ -997,40 +817,18 @@ module VexRiscv ( reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; reg decode_to_execute_IS_CSR; reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; reg decode_to_execute_CfuPlugin_CFU_ENABLE; reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; reg decode_to_execute_IS_MUL; - reg execute_to_memory_IS_MUL; reg decode_to_execute_IS_RS1_SIGNED; reg decode_to_execute_IS_RS2_SIGNED; - reg decode_to_execute_IS_DIV; - reg execute_to_memory_IS_DIV; reg [31:0] decode_to_execute_RS1; reg [31:0] decode_to_execute_RS2; reg decode_to_execute_SRC2_FORCE_ZERO; + reg [31:0] decode_to_execute_SRC1; + reg [31:0] decode_to_execute_SRC2; reg decode_to_execute_CSR_WRITE_OPCODE; reg decode_to_execute_CSR_READ_OPCODE; - reg decode_to_execute_DO_EBREAK; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_MMU_FAULT; - reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; - reg execute_to_memory_MMU_RSP2_isIoAccess; - reg execute_to_memory_MMU_RSP2_isPaging; - reg execute_to_memory_MMU_RSP2_allowRead; - reg execute_to_memory_MMU_RSP2_allowWrite; - reg execute_to_memory_MMU_RSP2_allowExecute; - reg execute_to_memory_MMU_RSP2_exception; - reg execute_to_memory_MMU_RSP2_refilling; - reg execute_to_memory_MMU_RSP2_bypassTranslation; - reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; - reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; - reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg [2:0] _zz_136; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_836; reg execute_CsrPlugin_csr_772; @@ -1042,21 +840,19 @@ module VexRiscv ( reg execute_CsrPlugin_csr_2944; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_137; - reg [31:0] _zz_138; - reg [31:0] _zz_139; - reg [31:0] _zz_140; - reg [31:0] _zz_141; - reg [31:0] _zz_142; - reg [31:0] _zz_143; - reg [31:0] _zz_144; - reg [31:0] _zz_145; - reg [31:0] _zz_146; - wire iBus_cmd_m2sPipe_valid; - wire iBus_cmd_m2sPipe_ready; - wire [31:0] iBus_cmd_m2sPipe_payload_pc; - reg iBus_cmd_m2sPipe_rValid; - reg [31:0] iBus_cmd_m2sPipe_rData_pc; + reg [31:0] _zz_119; + reg [31:0] _zz_120; + reg [31:0] _zz_121; + reg [31:0] _zz_122; + reg [31:0] _zz_123; + reg [31:0] _zz_124; + reg [31:0] _zz_125; + reg [31:0] _zz_126; + reg [31:0] _zz_127; + reg [31:0] _zz_128; + reg [2:0] _zz_129; + reg _zz_130; + reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; wire dBus_cmd_halfPipe_payload_wr; @@ -1069,395 +865,394 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_147; + reg [3:0] _zz_131; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; reg [39:0] _zz_3_string; + reg [39:0] decode_ENV_CTRL_string; reg [39:0] _zz_4_string; reg [39:0] _zz_5_string; reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8_string; - reg [39:0] _zz_9_string; - reg [39:0] _zz_10_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_11_string; - reg [31:0] _zz_12_string; - reg [31:0] _zz_13_string; + reg [31:0] _zz_7_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_14_string; - reg [71:0] _zz_15_string; - reg [71:0] _zz_16_string; + reg [71:0] _zz_10_string; + reg [71:0] _zz_11_string; + reg [71:0] _zz_12_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_17_string; - reg [39:0] _zz_18_string; - reg [39:0] _zz_19_string; + reg [39:0] _zz_13_string; + reg [39:0] _zz_14_string; + reg [39:0] _zz_15_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_20_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; - reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_23_string; - reg [23:0] _zz_24_string; - reg [23:0] _zz_25_string; - reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_26_string; - reg [95:0] _zz_27_string; - reg [95:0] _zz_28_string; + reg [63:0] _zz_16_string; + reg [63:0] _zz_17_string; + reg [63:0] _zz_18_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_32_string; - reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_19_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34_string; - reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_20_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_36_string; + reg [31:0] _zz_21_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_38_string; - reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_40_string; - reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_41_string; + reg [71:0] _zz_22_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_25_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_27_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_42_string; + reg [63:0] _zz_28_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_43_string; - reg [39:0] _zz_47_string; - reg [39:0] _zz_48_string; - reg [31:0] _zz_49_string; - reg [71:0] _zz_50_string; - reg [39:0] _zz_51_string; - reg [63:0] _zz_52_string; - reg [23:0] _zz_53_string; - reg [95:0] _zz_54_string; - reg [95:0] _zz_89_string; - reg [23:0] _zz_90_string; - reg [63:0] _zz_91_string; - reg [39:0] _zz_92_string; - reg [71:0] _zz_93_string; - reg [31:0] _zz_94_string; - reg [39:0] _zz_95_string; - reg [39:0] _zz_96_string; - reg [95:0] decode_to_execute_SRC1_CTRL_string; - reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] _zz_29_string; + reg [39:0] _zz_33_string; + reg [39:0] _zz_34_string; + reg [31:0] _zz_35_string; + reg [71:0] _zz_36_string; + reg [39:0] _zz_37_string; + reg [63:0] _zz_38_string; + reg [23:0] _zz_39_string; + reg [95:0] _zz_40_string; + reg [95:0] _zz_72_string; + reg [23:0] _zz_73_string; + reg [63:0] _zz_74_string; + reg [39:0] _zz_75_string; + reg [71:0] _zz_76_string; + reg [31:0] _zz_77_string; + reg [39:0] _zz_78_string; + reg [39:0] _zz_79_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [39:0] decode_to_execute_ENV_CTRL_string; - reg [39:0] execute_to_memory_ENV_CTRL_string; - reg [39:0] memory_to_writeBack_ENV_CTRL_string; reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; `endif (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_153 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_154 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_155 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_156 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_157 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_158 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_159 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_160 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_161 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_162 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_163 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); - assign _zz_164 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_165 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_166 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_167 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_168 = (1'b1 || (! 1'b1)); - assign _zz_169 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_170 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_171 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_172 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_173 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_174 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_175 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_176 = (! memory_arbitration_isStuck); - assign _zz_177 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_178 = (! execute_arbitration_isStuckByOthers); - assign _zz_179 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_180 = ((_zz_120 && 1'b1) && (! 1'b0)); - assign _zz_181 = ((_zz_121 && 1'b1) && (! 1'b0)); - assign _zz_182 = ((_zz_122 && 1'b1) && (! 1'b0)); - assign _zz_183 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_184 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_185 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_186 = execute_INSTRUCTION[13]; - assign _zz_187 = _zz_80[31 : 31]; - assign _zz_188 = _zz_80[30 : 30]; - assign _zz_189 = _zz_80[29 : 29]; - assign _zz_190 = _zz_80[28 : 28]; - assign _zz_191 = _zz_80[26 : 26]; - assign _zz_192 = _zz_80[23 : 23]; - assign _zz_193 = _zz_80[14 : 14]; - assign _zz_194 = _zz_80[10 : 10]; - assign _zz_195 = _zz_80[9 : 9]; - assign _zz_196 = _zz_80[8 : 8]; - assign _zz_197 = _zz_80[32 : 32]; - assign _zz_198 = _zz_80[11 : 11]; - assign _zz_199 = _zz_80[4 : 4]; - assign _zz_200 = _zz_80[2 : 2]; - assign _zz_201 = _zz_80[17 : 17]; - assign _zz_202 = _zz_80[7 : 7]; - assign _zz_203 = _zz_80[3 : 3]; - assign _zz_204 = (_zz_58 - 3'b001); - assign _zz_205 = {IBusSimplePlugin_fetchPc_inc,2'b00}; - assign _zz_206 = {29'd0, _zz_205}; - assign _zz_207 = (IBusSimplePlugin_pending_value + _zz_209); - assign _zz_208 = IBusSimplePlugin_pending_inc; - assign _zz_209 = {2'd0, _zz_208}; - assign _zz_210 = IBusSimplePlugin_pending_dec; - assign _zz_211 = {2'd0, _zz_210}; - assign _zz_212 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); - assign _zz_213 = {2'd0, _zz_212}; - assign _zz_214 = IBusSimplePlugin_pending_dec; - assign _zz_215 = {2'd0, _zz_214}; - assign _zz_216 = execute_SRC_LESS; - assign _zz_217 = 3'b100; - assign _zz_218 = execute_INSTRUCTION[19 : 15]; - assign _zz_219 = execute_INSTRUCTION[31 : 20]; - assign _zz_220 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_221 = ($signed(_zz_222) + $signed(_zz_225)); - assign _zz_222 = ($signed(_zz_223) + $signed(_zz_224)); - assign _zz_223 = execute_SRC1; - assign _zz_224 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_225 = (execute_SRC_USE_SUB_LESS ? _zz_226 : _zz_227); - assign _zz_226 = 32'h00000001; - assign _zz_227 = 32'h0; - assign _zz_228 = (_zz_229 >>> 1); - assign _zz_229 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_230 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_231 = execute_INSTRUCTION[31 : 20]; - assign _zz_232 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_233 = (_zz_123 & (~ _zz_234)); - assign _zz_234 = (_zz_123 - 2'b01); - assign _zz_235 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_236 = execute_INSTRUCTION[31 : 24]; - assign _zz_237 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_238 = {5'd0, _zz_237}; - assign _zz_239 = (_zz_241 + _zz_243); - assign _zz_240 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_241 = {{1{_zz_240[32]}}, _zz_240}; - assign _zz_242 = _zz_244; - assign _zz_243 = {{1{_zz_242[32]}}, _zz_242}; - assign _zz_244 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_245 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_246 = {5'd0, _zz_245}; - assign _zz_247 = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_248 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_249 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_250 = {_zz_128,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_251 = _zz_252; - assign _zz_252 = _zz_253; - assign _zz_253 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_129) : _zz_129)} + _zz_255); - assign _zz_254 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_255 = {32'd0, _zz_254}; - assign _zz_256 = _zz_131; - assign _zz_257 = {32'd0, _zz_256}; - assign _zz_258 = _zz_130; - assign _zz_259 = {31'd0, _zz_258}; - assign _zz_260 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_261 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_262 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_263 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_264 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_265 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_266 = 1'b1; - assign _zz_267 = 1'b1; - assign _zz_268 = {_zz_61,_zz_60}; - assign _zz_269 = 32'h10103050; - assign _zz_270 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_271 = 32'h02004020; - assign _zz_272 = _zz_88; - assign _zz_273 = _zz_87; - assign _zz_274 = {_zz_88,{_zz_86,_zz_87}}; - assign _zz_275 = 3'b000; - assign _zz_276 = (((decode_INSTRUCTION & _zz_279) == 32'h02000030) != 1'b0); - assign _zz_277 = 1'b0; - assign _zz_278 = {(_zz_85 != 1'b0),{(_zz_280 != _zz_281),{_zz_282,{_zz_283,_zz_284}}}}; - assign _zz_279 = 32'h02004074; - assign _zz_280 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); - assign _zz_281 = 1'b0; - assign _zz_282 = (((decode_INSTRUCTION & _zz_285) == 32'h10000050) != 1'b0); - assign _zz_283 = ({_zz_286,_zz_287} != 2'b00); - assign _zz_284 = {({_zz_288,_zz_289} != 2'b00),{(_zz_290 != _zz_291),{_zz_292,{_zz_293,_zz_294}}}}; - assign _zz_285 = 32'h10403050; - assign _zz_286 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_287 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_288 = _zz_84; - assign _zz_289 = ((decode_INSTRUCTION & _zz_295) == 32'h00000004); - assign _zz_290 = ((decode_INSTRUCTION & _zz_296) == 32'h00000040); - assign _zz_291 = 1'b0; - assign _zz_292 = ({_zz_297,_zz_298} != 2'b00); - assign _zz_293 = ({_zz_299,_zz_300} != 2'b00); - assign _zz_294 = {(_zz_301 != _zz_302),{_zz_303,{_zz_304,_zz_305}}}; - assign _zz_295 = 32'h0000001c; - assign _zz_296 = 32'h00000058; - assign _zz_297 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); - assign _zz_298 = ((decode_INSTRUCTION & 32'h00103040) == 32'h00000040); - assign _zz_299 = ((decode_INSTRUCTION & _zz_306) == 32'h00005010); - assign _zz_300 = ((decode_INSTRUCTION & _zz_307) == 32'h00005020); - assign _zz_301 = {(_zz_308 == _zz_309),{_zz_310,_zz_311}}; - assign _zz_302 = 3'b000; - assign _zz_303 = ({_zz_312,{_zz_313,_zz_314}} != 3'b000); - assign _zz_304 = (_zz_315 != 1'b0); - assign _zz_305 = {(_zz_316 != _zz_317),{_zz_318,{_zz_319,_zz_320}}}; - assign _zz_306 = 32'h00007034; - assign _zz_307 = 32'h02007064; - assign _zz_308 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_309 = 32'h40001010; - assign _zz_310 = ((decode_INSTRUCTION & _zz_321) == 32'h00001010); - assign _zz_311 = ((decode_INSTRUCTION & _zz_322) == 32'h00001010); - assign _zz_312 = ((decode_INSTRUCTION & _zz_323) == 32'h00000024); - assign _zz_313 = (_zz_324 == _zz_325); - assign _zz_314 = (_zz_326 == _zz_327); - assign _zz_315 = ((decode_INSTRUCTION & _zz_328) == 32'h00001000); - assign _zz_316 = _zz_86; - assign _zz_317 = 1'b0; - assign _zz_318 = ({_zz_329,_zz_330} != 2'b00); - assign _zz_319 = (_zz_331 != _zz_332); - assign _zz_320 = {_zz_333,{_zz_334,_zz_335}}; - assign _zz_321 = 32'h00007034; - assign _zz_322 = 32'h02007054; - assign _zz_323 = 32'h00000064; - assign _zz_324 = (decode_INSTRUCTION & 32'h00003034); - assign _zz_325 = 32'h00001010; - assign _zz_326 = (decode_INSTRUCTION & 32'h02003054); - assign _zz_327 = 32'h00001010; - assign _zz_328 = 32'h00001000; - assign _zz_329 = ((decode_INSTRUCTION & _zz_336) == 32'h00002000); - assign _zz_330 = ((decode_INSTRUCTION & _zz_337) == 32'h00001000); - assign _zz_331 = {(_zz_338 == _zz_339),(_zz_340 == _zz_341)}; - assign _zz_332 = 2'b00; - assign _zz_333 = (_zz_82 != 1'b0); - assign _zz_334 = ({_zz_342,_zz_343} != 3'b000); - assign _zz_335 = {(_zz_344 != _zz_345),{_zz_346,{_zz_347,_zz_348}}}; - assign _zz_336 = 32'h00002010; - assign _zz_337 = 32'h00005000; - assign _zz_338 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_339 = 32'h00006000; - assign _zz_340 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_341 = 32'h00004000; - assign _zz_342 = _zz_85; - assign _zz_343 = {(_zz_349 == _zz_350),(_zz_351 == _zz_352)}; - assign _zz_344 = ((decode_INSTRUCTION & _zz_353) == 32'h00000020); - assign _zz_345 = 1'b0; - assign _zz_346 = ({_zz_354,_zz_355} != 2'b00); - assign _zz_347 = ({_zz_356,_zz_357} != 3'b000); - assign _zz_348 = {(_zz_358 != _zz_359),{_zz_360,{_zz_361,_zz_362}}}; - assign _zz_349 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_350 = 32'h00000020; - assign _zz_351 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_352 = 32'h00000020; - assign _zz_353 = 32'h00000020; - assign _zz_354 = ((decode_INSTRUCTION & 32'h00000008) == 32'h00000008); - assign _zz_355 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); - assign _zz_356 = _zz_83; - assign _zz_357 = {(_zz_363 == _zz_364),(_zz_365 == _zz_366)}; - assign _zz_358 = {_zz_84,{_zz_367,{_zz_368,_zz_369}}}; - assign _zz_359 = 6'h0; - assign _zz_360 = ({_zz_83,_zz_370} != 2'b00); - assign _zz_361 = ({_zz_371,_zz_372} != 2'b00); - assign _zz_362 = {(_zz_373 != _zz_374),{_zz_375,{_zz_376,_zz_377}}}; - assign _zz_363 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_364 = 32'h00000010; - assign _zz_365 = (decode_INSTRUCTION & 32'h02000060); - assign _zz_366 = 32'h00000020; - assign _zz_367 = ((decode_INSTRUCTION & _zz_378) == 32'h00001010); - assign _zz_368 = (_zz_379 == _zz_380); - assign _zz_369 = {_zz_381,{_zz_382,_zz_383}}; - assign _zz_370 = ((decode_INSTRUCTION & _zz_384) == 32'h00000020); - assign _zz_371 = _zz_83; - assign _zz_372 = (_zz_385 == _zz_386); - assign _zz_373 = {_zz_387,{_zz_388,_zz_389}}; - assign _zz_374 = 4'b0000; - assign _zz_375 = (_zz_390 != 1'b0); - assign _zz_376 = (_zz_391 != _zz_392); - assign _zz_377 = {_zz_393,_zz_394}; - assign _zz_378 = 32'h00001010; - assign _zz_379 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_380 = 32'h00002010; - assign _zz_381 = ((decode_INSTRUCTION & _zz_395) == 32'h00000010); - assign _zz_382 = (_zz_396 == _zz_397); - assign _zz_383 = (_zz_398 == _zz_399); - assign _zz_384 = 32'h00000070; - assign _zz_385 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_386 = 32'h0; - assign _zz_387 = ((decode_INSTRUCTION & _zz_400) == 32'h0); - assign _zz_388 = (_zz_401 == _zz_402); - assign _zz_389 = {_zz_82,_zz_403}; - assign _zz_390 = ((decode_INSTRUCTION & _zz_404) == 32'h0); - assign _zz_391 = {_zz_405,{_zz_406,_zz_407}}; - assign _zz_392 = 3'b000; - assign _zz_393 = ({_zz_408,_zz_409} != 2'b00); - assign _zz_394 = ({_zz_410,_zz_411} != 2'b00); - assign _zz_395 = 32'h00000050; - assign _zz_396 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_397 = 32'h00000004; - assign _zz_398 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_399 = 32'h0; - assign _zz_400 = 32'h00000044; - assign _zz_401 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_402 = 32'h0; - assign _zz_403 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_404 = 32'h00000058; - assign _zz_405 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_406 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_407 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz_408 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_409 = _zz_81; - assign _zz_410 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_411 = _zz_81; + assign _zz_146 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_147 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_148 = (execute_arbitration_isValid && execute_IS_MUL); + assign _zz_149 = ((_zz_137 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_150 = ((_zz_137 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_151 = (execute_MulDivIterativePlugin_frontendOk && (! execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_152 = ({CfuPlugin_joinException_valid,{CsrPlugin_selfException_valid,DBusSimplePlugin_memoryExceptionPort_valid}} != 3'b000); + assign _zz_153 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_154 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_155 = execute_INSTRUCTION[29 : 28]; + assign _zz_156 = (! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))); + assign _zz_157 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_158 = (1'b1 || (! 1'b1)); + assign _zz_159 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_160 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_161 = (iBus_cmd_valid || (_zz_129 != 3'b000)); + assign _zz_162 = (! execute_arbitration_isStuckByOthers); + assign _zz_163 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_164 = ((_zz_103 && 1'b1) && (! 1'b0)); + assign _zz_165 = ((_zz_104 && 1'b1) && (! 1'b0)); + assign _zz_166 = ((_zz_105 && 1'b1) && (! 1'b0)); + assign _zz_167 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_168 = execute_INSTRUCTION[13 : 12]; + assign _zz_169 = execute_INSTRUCTION[13]; + assign _zz_170 = _zz_63[31 : 31]; + assign _zz_171 = _zz_63[30 : 30]; + assign _zz_172 = _zz_63[29 : 29]; + assign _zz_173 = _zz_63[27 : 27]; + assign _zz_174 = _zz_63[24 : 24]; + assign _zz_175 = _zz_63[15 : 15]; + assign _zz_176 = _zz_63[11 : 11]; + assign _zz_177 = _zz_63[12 : 12]; + assign _zz_178 = _zz_63[5 : 5]; + assign _zz_179 = _zz_63[3 : 3]; + assign _zz_180 = _zz_63[18 : 18]; + assign _zz_181 = _zz_63[8 : 8]; + assign _zz_182 = _zz_63[4 : 4]; + assign _zz_183 = _zz_63[0 : 0]; + assign _zz_184 = (_zz_42 - 3'b001); + assign _zz_185 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_186 = {29'd0, _zz_185}; + assign _zz_187 = execute_SRC_LESS; + assign _zz_188 = 3'b100; + assign _zz_189 = decode_INSTRUCTION[19 : 15]; + assign _zz_190 = decode_INSTRUCTION[31 : 20]; + assign _zz_191 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; + assign _zz_192 = ($signed(_zz_193) + $signed(_zz_196)); + assign _zz_193 = ($signed(_zz_194) + $signed(_zz_195)); + assign _zz_194 = execute_SRC1; + assign _zz_195 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_196 = (execute_SRC_USE_SUB_LESS ? _zz_197 : _zz_198); + assign _zz_197 = 32'h00000001; + assign _zz_198 = 32'h0; + assign _zz_199 = (_zz_200 >>> 1); + assign _zz_200 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_201 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_202 = execute_INSTRUCTION[31 : 20]; + assign _zz_203 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_204 = (_zz_106 - 3'b001); + assign _zz_205 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_206 = execute_INSTRUCTION[31 : 24]; + assign _zz_207 = execute_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_208 = {5'd0, _zz_207}; + assign _zz_209 = (_zz_211 + _zz_213); + assign _zz_210 = (execute_MulDivIterativePlugin_rs2[0] ? execute_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_211 = {{1{_zz_210[32]}}, _zz_210}; + assign _zz_212 = _zz_214; + assign _zz_213 = {{1{_zz_212[32]}}, _zz_212}; + assign _zz_214 = (execute_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_215 = _zz_115; + assign _zz_216 = {32'd0, _zz_215}; + assign _zz_217 = _zz_114; + assign _zz_218 = {31'd0, _zz_217}; + assign _zz_219 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_220 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_221 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_222 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_223 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_224 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_225 = (iBus_cmd_payload_address >>> 5); + assign _zz_226 = 1'b1; + assign _zz_227 = 1'b1; + assign _zz_228 = {_zz_45,_zz_44}; + assign _zz_229 = 32'h0000106f; + assign _zz_230 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_231 = 32'h00001073; + assign _zz_232 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_233 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_234 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_235) == 32'h00000003),{(_zz_236 == _zz_237),{_zz_238,{_zz_239,_zz_240}}}}}}; + assign _zz_235 = 32'h0000207f; + assign _zz_236 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_237 = 32'h00000003; + assign _zz_238 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_239 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_240 = {((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033),{((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_241) == 32'h00005013),{(_zz_242 == _zz_243),{_zz_244,{_zz_245,_zz_246}}}}}}; + assign _zz_241 = 32'hbc00707f; + assign _zz_242 = (decode_INSTRUCTION & 32'hfc00705f); + assign _zz_243 = 32'h00001013; + assign _zz_244 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_245 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_246 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_247 = (decode_INSTRUCTION & 32'h02000074); + assign _zz_248 = 32'h02000030; + assign _zz_249 = _zz_69; + assign _zz_250 = 1'b0; + assign _zz_251 = (((decode_INSTRUCTION & 32'h10003050) == 32'h00000050) != 1'b0); + assign _zz_252 = (((decode_INSTRUCTION & _zz_254) == 32'h10000050) != 1'b0); + assign _zz_253 = {({_zz_255,_zz_256} != 2'b00),{({_zz_257,_zz_258} != 2'b00),{(_zz_259 != _zz_260),{_zz_261,{_zz_262,_zz_263}}}}}; + assign _zz_254 = 32'h10403050; + assign _zz_255 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_256 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_257 = _zz_68; + assign _zz_258 = ((decode_INSTRUCTION & _zz_264) == 32'h00000004); + assign _zz_259 = ((decode_INSTRUCTION & _zz_265) == 32'h00000040); + assign _zz_260 = 1'b0; + assign _zz_261 = ({_zz_266,_zz_267} != 2'b00); + assign _zz_262 = (_zz_268 != 1'b0); + assign _zz_263 = {(_zz_269 != _zz_270),{_zz_271,{_zz_272,_zz_273}}}; + assign _zz_264 = 32'h0000001c; + assign _zz_265 = 32'h00000058; + assign _zz_266 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_267 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); + assign _zz_268 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); + assign _zz_269 = {(_zz_274 == _zz_275),{_zz_276,_zz_277}}; + assign _zz_270 = 3'b000; + assign _zz_271 = ({_zz_278,{_zz_279,_zz_280}} != 3'b000); + assign _zz_272 = (_zz_281 != 1'b0); + assign _zz_273 = {(_zz_282 != _zz_283),{_zz_284,{_zz_285,_zz_286}}}; + assign _zz_274 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_275 = 32'h40001010; + assign _zz_276 = ((decode_INSTRUCTION & _zz_287) == 32'h00001010); + assign _zz_277 = ((decode_INSTRUCTION & _zz_288) == 32'h00001010); + assign _zz_278 = ((decode_INSTRUCTION & _zz_289) == 32'h00000024); + assign _zz_279 = (_zz_290 == _zz_291); + assign _zz_280 = (_zz_292 == _zz_293); + assign _zz_281 = ((decode_INSTRUCTION & _zz_294) == 32'h00001000); + assign _zz_282 = _zz_70; + assign _zz_283 = 1'b0; + assign _zz_284 = ({_zz_295,_zz_296} != 2'b00); + assign _zz_285 = (_zz_297 != _zz_298); + assign _zz_286 = {_zz_299,{_zz_300,_zz_301}}; + assign _zz_287 = 32'h00007034; + assign _zz_288 = 32'h02007054; + assign _zz_289 = 32'h00000064; + assign _zz_290 = (decode_INSTRUCTION & 32'h00003034); + assign _zz_291 = 32'h00001010; + assign _zz_292 = (decode_INSTRUCTION & 32'h02003054); + assign _zz_293 = 32'h00001010; + assign _zz_294 = 32'h00001000; + assign _zz_295 = ((decode_INSTRUCTION & _zz_302) == 32'h00002000); + assign _zz_296 = ((decode_INSTRUCTION & _zz_303) == 32'h00001000); + assign _zz_297 = {(_zz_304 == _zz_305),(_zz_306 == _zz_307)}; + assign _zz_298 = 2'b00; + assign _zz_299 = (_zz_65 != 1'b0); + assign _zz_300 = ({_zz_308,_zz_309} != 3'b000); + assign _zz_301 = {(_zz_310 != _zz_311),{_zz_312,{_zz_313,_zz_314}}}; + assign _zz_302 = 32'h00002010; + assign _zz_303 = 32'h00005000; + assign _zz_304 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_305 = 32'h00006000; + assign _zz_306 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_307 = 32'h00004000; + assign _zz_308 = _zz_69; + assign _zz_309 = {(_zz_315 == _zz_316),(_zz_317 == _zz_318)}; + assign _zz_310 = ((decode_INSTRUCTION & _zz_319) == 32'h00000020); + assign _zz_311 = 1'b0; + assign _zz_312 = ({_zz_320,_zz_321} != 2'b00); + assign _zz_313 = (_zz_67 != 1'b0); + assign _zz_314 = {(_zz_322 != _zz_323),{_zz_324,{_zz_325,_zz_326}}}; + assign _zz_315 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_316 = 32'h00000020; + assign _zz_317 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_318 = 32'h00000020; + assign _zz_319 = 32'h00000020; + assign _zz_320 = ((decode_INSTRUCTION & 32'h00000008) == 32'h00000008); + assign _zz_321 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); + assign _zz_322 = {_zz_68,{_zz_327,{_zz_328,_zz_329}}}; + assign _zz_323 = 6'h0; + assign _zz_324 = ({_zz_66,_zz_330} != 2'b00); + assign _zz_325 = ({_zz_331,_zz_332} != 2'b00); + assign _zz_326 = {(_zz_333 != _zz_334),{_zz_335,{_zz_336,_zz_337}}}; + assign _zz_327 = ((decode_INSTRUCTION & _zz_338) == 32'h00001010); + assign _zz_328 = (_zz_339 == _zz_340); + assign _zz_329 = {_zz_67,{_zz_341,_zz_342}}; + assign _zz_330 = ((decode_INSTRUCTION & _zz_343) == 32'h00000020); + assign _zz_331 = _zz_66; + assign _zz_332 = (_zz_344 == _zz_345); + assign _zz_333 = {_zz_346,{_zz_347,_zz_348}}; + assign _zz_334 = 4'b0000; + assign _zz_335 = (_zz_349 != 1'b0); + assign _zz_336 = (_zz_350 != _zz_351); + assign _zz_337 = {_zz_352,{_zz_353,_zz_354}}; + assign _zz_338 = 32'h00001010; + assign _zz_339 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_340 = 32'h00002010; + assign _zz_341 = (_zz_355 == _zz_356); + assign _zz_342 = (_zz_357 == _zz_358); + assign _zz_343 = 32'h00000070; + assign _zz_344 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_345 = 32'h0; + assign _zz_346 = ((decode_INSTRUCTION & _zz_359) == 32'h0); + assign _zz_347 = (_zz_360 == _zz_361); + assign _zz_348 = {_zz_65,_zz_362}; + assign _zz_349 = ((decode_INSTRUCTION & _zz_363) == 32'h0); + assign _zz_350 = {_zz_364,{_zz_365,_zz_366}}; + assign _zz_351 = 3'b000; + assign _zz_352 = ({_zz_367,_zz_368} != 2'b00); + assign _zz_353 = (_zz_369 != _zz_370); + assign _zz_354 = (_zz_371 != _zz_372); + assign _zz_355 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_356 = 32'h00000004; + assign _zz_357 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_358 = 32'h0; + assign _zz_359 = 32'h00000044; + assign _zz_360 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_361 = 32'h0; + assign _zz_362 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_363 = 32'h00000058; + assign _zz_364 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_365 = ((decode_INSTRUCTION & _zz_373) == 32'h00002010); + assign _zz_366 = ((decode_INSTRUCTION & _zz_374) == 32'h40000030); + assign _zz_367 = ((decode_INSTRUCTION & _zz_375) == 32'h00000004); + assign _zz_368 = _zz_64; + assign _zz_369 = {(_zz_376 == _zz_377),_zz_64}; + assign _zz_370 = 2'b00; + assign _zz_371 = ((decode_INSTRUCTION & _zz_378) == 32'h00001004); + assign _zz_372 = 1'b0; + assign _zz_373 = 32'h00002014; + assign _zz_374 = 32'h40004034; + assign _zz_375 = 32'h00000014; + assign _zz_376 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_377 = 32'h00000004; + assign _zz_378 = 32'h00001054; always @ (posedge clk) begin - if(_zz_266) begin - _zz_150 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_226) begin + _zz_141 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_267) begin - _zz_151 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_227) begin + _zz_142 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_46) begin + if(_zz_32) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end - StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( - .io_push_valid (iBus_rsp_valid ), //i - .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o - .io_push_payload_error (iBus_rsp_payload_error ), //i - .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i - .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o - .io_pop_ready (_zz_148 ), //i - .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o - .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o - .io_flush (_zz_149 ), //i - .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o - .clk (clk ), //i - .reset (reset ) //i + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_132 ), //i + .io_cpu_prefetch_isValid (_zz_133 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_134 ), //i + .io_cpu_fetch_isStuck (_zz_135 ), //i + .io_cpu_fetch_isRemoved (_zz_136 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_137 ), //i + .io_cpu_decode_isStuck (_zz_138 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_139 ), //i + .io_cpu_fill_valid (_zz_140 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_268) + case(_zz_228) + 2'b00 : begin + _zz_143 = DBusSimplePlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_143 = CsrPlugin_jumpInterface_payload; + end + default : begin + _zz_143 = BranchPlugin_jumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_110) 2'b00 : begin - _zz_152 = CsrPlugin_jumpInterface_payload; + _zz_144 = DBusSimplePlugin_memoryExceptionPort_payload_code; + _zz_145 = DBusSimplePlugin_memoryExceptionPort_payload_badAddr; end 2'b01 : begin - _zz_152 = DBusSimplePlugin_redoBranch_payload; + _zz_144 = CsrPlugin_selfException_payload_code; + _zz_145 = CsrPlugin_selfException_payload_badAddr; end default : begin - _zz_152 = BranchPlugin_jumpInterface_payload; + _zz_144 = CfuPlugin_joinException_payload_code; + _zz_145 = CfuPlugin_joinException_payload_badAddr; end endcase end @@ -1491,6 +1286,14 @@ module VexRiscv ( default : _zz_3_string = "?????"; endcase end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end always @(*) begin case(_zz_4) `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; @@ -1515,46 +1318,6 @@ module VexRiscv ( default : _zz_6_string = "?????"; endcase end - always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; - endcase - end - always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_8) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; - default : _zz_8_string = "?????"; - endcase - end - always @(*) begin - case(_zz_9) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; - default : _zz_9_string = "?????"; - endcase - end - always @(*) begin - case(_zz_10) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; - default : _zz_10_string = "?????"; - endcase - end always @(*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; @@ -1565,30 +1328,30 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_11) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; - default : _zz_11_string = "????"; + case(_zz_7) + `BranchCtrlEnum_defaultEncoding_INC : _zz_7_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_7_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_7_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_7_string = "JALR"; + default : _zz_7_string = "????"; endcase end always @(*) begin - case(_zz_12) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; - default : _zz_12_string = "????"; + case(_zz_8) + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; endcase end always @(*) begin - case(_zz_13) - `BranchCtrlEnum_defaultEncoding_INC : _zz_13_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_13_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_13_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_13_string = "JALR"; - default : _zz_13_string = "????"; + case(_zz_9) + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; endcase end always @(*) begin @@ -1601,30 +1364,30 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_10) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; + default : _zz_10_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_11) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; endcase end always @(*) begin - case(_zz_16) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; - default : _zz_16_string = "?????????"; + case(_zz_12) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; endcase end always @(*) begin @@ -1636,27 +1399,27 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_13) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_13_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_13_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_13_string = "AND_1"; + default : _zz_13_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_14) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; + default : _zz_14_string = "?????"; endcase end always @(*) begin - case(_zz_19) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; - default : _zz_19_string = "?????"; + case(_zz_15) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; endcase end always @(*) begin @@ -1668,99 +1431,27 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_20) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; - default : _zz_20_string = "????????"; - endcase - end - always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; - endcase - end - always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; - endcase - end - always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; - endcase - end - always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; - endcase - end - always @(*) begin - case(_zz_24) - `Src2CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_24_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_24_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_24_string = "PC "; - default : _zz_24_string = "???"; - endcase - end - always @(*) begin - case(_zz_25) - `Src2CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_25_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_25_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_25_string = "PC "; - default : _zz_25_string = "???"; - endcase - end - always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; - endcase - end - always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_16) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_16_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_16_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_16_string = "BITWISE "; + default : _zz_16_string = "????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_17) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17_string = "BITWISE "; + default : _zz_17_string = "????????"; endcase end always @(*) begin - case(_zz_28) - `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; - default : _zz_28_string = "????????????"; + case(_zz_18) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18_string = "BITWISE "; + default : _zz_18_string = "????????"; endcase end always @(*) begin @@ -1771,26 +1462,10 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_32) - `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; - default : _zz_32_string = "?????"; - endcase - end - always @(*) begin - case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; - default : memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_19) + `Input2Kind_defaultEncoding_RS : _zz_19_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_19_string = "IMM_I"; + default : _zz_19_string = "?????"; endcase end always @(*) begin @@ -1802,27 +1477,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; - endcase - end - always @(*) begin - case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; - default : writeBack_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_20) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_20_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_20_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_20_string = "ECALL"; + default : _zz_20_string = "?????"; endcase end always @(*) begin @@ -1835,12 +1494,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_36) - `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; - default : _zz_36_string = "????"; + case(_zz_21) + `BranchCtrlEnum_defaultEncoding_INC : _zz_21_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_21_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_21_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_21_string = "JALR"; + default : _zz_21_string = "????"; endcase end always @(*) begin @@ -1853,48 +1512,48 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_38) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38_string = "SRA_1 "; - default : _zz_38_string = "?????????"; + case(_zz_22) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22_string = "SRA_1 "; + default : _zz_22_string = "?????????"; endcase end always @(*) begin - case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; - default : execute_SRC2_CTRL_string = "???"; + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_40) - `Src2CtrlEnum_defaultEncoding_RS : _zz_40_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_40_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_40_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_40_string = "PC "; - default : _zz_40_string = "???"; + case(_zz_25) + `Src2CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_25_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_25_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_25_string = "PC "; + default : _zz_25_string = "???"; endcase end always @(*) begin - case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; - default : execute_SRC1_CTRL_string = "????????????"; + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_41) - `Src1CtrlEnum_defaultEncoding_RS : _zz_41_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_41_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_41_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_41_string = "URS1 "; - default : _zz_41_string = "????????????"; + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; endcase end always @(*) begin @@ -1906,11 +1565,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_42) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_42_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_42_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_42_string = "BITWISE "; - default : _zz_42_string = "????????"; + case(_zz_28) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_28_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_28_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_28_string = "BITWISE "; + default : _zz_28_string = "????????"; endcase end always @(*) begin @@ -1922,163 +1581,145 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_43) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; - default : _zz_43_string = "?????"; - endcase - end - always @(*) begin - case(_zz_47) - `Input2Kind_defaultEncoding_RS : _zz_47_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_47_string = "IMM_I"; - default : _zz_47_string = "?????"; - endcase - end - always @(*) begin - case(_zz_48) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_48_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_48_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_48_string = "ECALL"; - default : _zz_48_string = "?????"; + case(_zz_29) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_29_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_29_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_29_string = "AND_1"; + default : _zz_29_string = "?????"; endcase end always @(*) begin - case(_zz_49) - `BranchCtrlEnum_defaultEncoding_INC : _zz_49_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_49_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_49_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_49_string = "JALR"; - default : _zz_49_string = "????"; + case(_zz_33) + `Input2Kind_defaultEncoding_RS : _zz_33_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_33_string = "IMM_I"; + default : _zz_33_string = "?????"; endcase end always @(*) begin - case(_zz_50) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_50_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_50_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_50_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_50_string = "SRA_1 "; - default : _zz_50_string = "?????????"; + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; endcase end always @(*) begin - case(_zz_51) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_51_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_51_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_51_string = "AND_1"; - default : _zz_51_string = "?????"; + case(_zz_35) + `BranchCtrlEnum_defaultEncoding_INC : _zz_35_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_35_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_35_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_35_string = "JALR"; + default : _zz_35_string = "????"; endcase end always @(*) begin - case(_zz_52) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_52_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_52_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_52_string = "BITWISE "; - default : _zz_52_string = "????????"; + case(_zz_36) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_36_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_36_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_36_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_36_string = "SRA_1 "; + default : _zz_36_string = "?????????"; endcase end always @(*) begin - case(_zz_53) - `Src2CtrlEnum_defaultEncoding_RS : _zz_53_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_53_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_53_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_53_string = "PC "; - default : _zz_53_string = "???"; + case(_zz_37) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_37_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_37_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_37_string = "AND_1"; + default : _zz_37_string = "?????"; endcase end always @(*) begin - case(_zz_54) - `Src1CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_54_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54_string = "URS1 "; - default : _zz_54_string = "????????????"; + case(_zz_38) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; + default : _zz_38_string = "????????"; endcase end always @(*) begin - case(_zz_89) - `Src1CtrlEnum_defaultEncoding_RS : _zz_89_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_89_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_89_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_89_string = "URS1 "; - default : _zz_89_string = "????????????"; + case(_zz_39) + `Src2CtrlEnum_defaultEncoding_RS : _zz_39_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_39_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_39_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_39_string = "PC "; + default : _zz_39_string = "???"; endcase end always @(*) begin - case(_zz_90) - `Src2CtrlEnum_defaultEncoding_RS : _zz_90_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_90_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_90_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_90_string = "PC "; - default : _zz_90_string = "???"; + case(_zz_40) + `Src1CtrlEnum_defaultEncoding_RS : _zz_40_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_40_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_40_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_40_string = "URS1 "; + default : _zz_40_string = "????????????"; endcase end always @(*) begin - case(_zz_91) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_91_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_91_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_91_string = "BITWISE "; - default : _zz_91_string = "????????"; + case(_zz_72) + `Src1CtrlEnum_defaultEncoding_RS : _zz_72_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_72_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_72_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_72_string = "URS1 "; + default : _zz_72_string = "????????????"; endcase end always @(*) begin - case(_zz_92) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_92_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_92_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_92_string = "AND_1"; - default : _zz_92_string = "?????"; + case(_zz_73) + `Src2CtrlEnum_defaultEncoding_RS : _zz_73_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_73_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_73_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_73_string = "PC "; + default : _zz_73_string = "???"; endcase end always @(*) begin - case(_zz_93) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_93_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_93_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_93_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_93_string = "SRA_1 "; - default : _zz_93_string = "?????????"; + case(_zz_74) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_74_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_74_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_74_string = "BITWISE "; + default : _zz_74_string = "????????"; endcase end always @(*) begin - case(_zz_94) - `BranchCtrlEnum_defaultEncoding_INC : _zz_94_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_94_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_94_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_94_string = "JALR"; - default : _zz_94_string = "????"; + case(_zz_75) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_75_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_75_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_75_string = "AND_1"; + default : _zz_75_string = "?????"; endcase end always @(*) begin - case(_zz_95) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_95_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_95_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_95_string = "ECALL"; - default : _zz_95_string = "?????"; + case(_zz_76) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_76_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_76_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_76_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_76_string = "SRA_1 "; + default : _zz_76_string = "?????????"; endcase end always @(*) begin - case(_zz_96) - `Input2Kind_defaultEncoding_RS : _zz_96_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_96_string = "IMM_I"; - default : _zz_96_string = "?????"; + case(_zz_77) + `BranchCtrlEnum_defaultEncoding_INC : _zz_77_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_77_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_77_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_77_string = "JALR"; + default : _zz_77_string = "????"; endcase end always @(*) begin - case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; - default : decode_to_execute_SRC1_CTRL_string = "????????????"; + case(_zz_78) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_78_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_78_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_78_string = "ECALL"; + default : _zz_78_string = "?????"; endcase end always @(*) begin - case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; - default : decode_to_execute_SRC2_CTRL_string = "???"; + case(_zz_79) + `Input2Kind_defaultEncoding_RS : _zz_79_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_79_string = "IMM_I"; + default : _zz_79_string = "?????"; endcase end always @(*) begin @@ -2123,22 +1764,6 @@ module VexRiscv ( default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end - always @(*) begin - case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; - default : execute_to_memory_ENV_CTRL_string = "?????"; - endcase - end - always @(*) begin - case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; - default : memory_to_writeBack_ENV_CTRL_string = "?????"; - endcase - end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; @@ -2148,176 +1773,108 @@ module VexRiscv ( end `endif - assign memory_MEMORY_READ_DATA = dBus_rsp_data; - assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_98; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; - assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_SRC2 = _zz_87; + assign decode_SRC1 = _zz_82; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign decode_IS_DIV = _zz_187[0]; - assign decode_IS_RS2_SIGNED = _zz_188[0]; - assign decode_IS_RS1_SIGNED = _zz_189[0]; - assign decode_IS_MUL = _zz_190[0]; + assign decode_IS_RS2_SIGNED = _zz_170[0]; + assign decode_IS_RS1_SIGNED = _zz_171[0]; + assign decode_IS_MUL = _zz_172[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_191[0]; - assign _zz_4 = _zz_5; - assign _zz_6 = _zz_7; - assign decode_ENV_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_192[0]; - assign decode_BRANCH_CTRL = _zz_11; - assign _zz_12 = _zz_13; - assign decode_SHIFT_CTRL = _zz_14; - assign _zz_15 = _zz_16; - assign decode_ALU_BITWISE_CTRL = _zz_17; - assign _zz_18 = _zz_19; - assign decode_SRC_LESS_UNSIGNED = _zz_193[0]; - assign decode_ALU_CTRL = _zz_20; - assign _zz_21 = _zz_22; - assign decode_MEMORY_STORE = _zz_194[0]; - assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_195[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_196[0]; - assign decode_SRC2_CTRL = _zz_23; - assign _zz_24 = _zz_25; - assign decode_SRC1_CTRL = _zz_26; - assign _zz_27 = _zz_28; - assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; - assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign decode_CfuPlugin_CFU_ENABLE = _zz_173[0]; + assign decode_ENV_CTRL = _zz_4; + assign _zz_5 = _zz_6; + assign decode_IS_CSR = _zz_174[0]; + assign decode_BRANCH_CTRL = _zz_7; + assign _zz_8 = _zz_9; + assign decode_SHIFT_CTRL = _zz_10; + assign _zz_11 = _zz_12; + assign decode_ALU_BITWISE_CTRL = _zz_13; + assign _zz_14 = _zz_15; + assign decode_SRC_LESS_UNSIGNED = _zz_175[0]; + assign decode_ALU_CTRL = _zz_16; + assign _zz_17 = _zz_18; + assign decode_MEMORY_STORE = _zz_176[0]; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); - assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_197[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_DIV = decode_to_execute_IS_DIV; - assign execute_IS_MUL = decode_to_execute_IS_MUL; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; - assign memory_IS_DIV = execute_to_memory_IS_DIV; - assign memory_IS_MUL = execute_to_memory_IS_MUL; - always @ (*) begin - _zz_29 = memory_CfuPlugin_CFU_IN_FLIGHT; - if(memory_arbitration_isStuck)begin - _zz_29 = 1'b0; - end - end - - always @ (*) begin - _zz_30 = execute_CfuPlugin_CFU_IN_FLIGHT; - if(execute_arbitration_isStuck)begin - _zz_30 = 1'b0; - end - end - - always @ (*) begin - _zz_31 = memory_REGFILE_WRITE_DATA; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_31 = memory_CfuPlugin_rsp_payload_outputs_0; - end - if(_zz_153)begin - _zz_31 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); - end - if(_zz_154)begin - _zz_31 = memory_MulDivIterativePlugin_div_result; - end - end - - assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_19; assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33; - assign execute_ENV_CTRL = _zz_34; - assign writeBack_ENV_CTRL = _zz_35; + assign execute_ENV_CTRL = _zz_20; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_112; - assign execute_PC = decode_to_execute_PC; + assign execute_BRANCH_DO = _zz_95; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_198[0]; - assign decode_RS1_USE = _zz_199[0]; + assign execute_BRANCH_CTRL = _zz_21; + assign decode_RS2_USE = _zz_177[0]; + assign decode_RS1_USE = _zz_178[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; - assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; - assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; - assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_155)begin - _zz_37 = _zz_105; - end - if(_zz_156)begin - _zz_37 = execute_CsrPlugin_readData; - end - end - - assign execute_SHIFT_CTRL = _zz_38; + assign execute_SHIFT_CTRL = _zz_22; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_39 = execute_PC; - assign execute_SRC2_CTRL = _zz_40; - assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_200[0]; - assign decode_SRC_ADD_ZERO = _zz_201[0]; + assign _zz_23 = decode_PC; + assign _zz_24 = decode_RS2; + assign decode_SRC2_CTRL = _zz_25; + assign _zz_26 = decode_RS1; + assign decode_SRC1_CTRL = _zz_27; + assign decode_SRC_USE_SUB_LESS = _zz_179[0]; + assign decode_SRC_ADD_ZERO = _zz_180[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_42; - assign execute_SRC2 = _zz_104; - assign execute_SRC1 = _zz_99; - assign execute_ALU_BITWISE_CTRL = _zz_43; - assign _zz_44 = writeBack_INSTRUCTION; - assign _zz_45 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_46 = 1'b0; + assign execute_ALU_CTRL = _zz_28; + assign execute_SRC2 = decode_to_execute_SRC2; + assign execute_SRC1 = decode_to_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_29; + assign _zz_30 = execute_INSTRUCTION; + assign _zz_31 = execute_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_32 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_46 = 1'b1; + _zz_32 = 1'b1; end end - assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_202[0]; + decode_REGFILE_WRITE_VALID = _zz_181[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_229) == 32'h00000003),{(_zz_230 == _zz_231),{_zz_232,{_zz_233,_zz_234}}}}}}} != 22'h0); always @ (*) begin - _zz_55 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_55 = writeBack_DBusSimplePlugin_rspFormated; - end - end - - assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; - assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; - assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; - assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; - assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; - assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; - assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; - assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; - assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; - assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; - assign memory_PC = execute_to_memory_PC; - assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; - assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; - assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + _zz_41 = execute_REGFILE_WRITE_DATA; + if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin + _zz_41 = execute_DBusSimplePlugin_rspFormated; + end + if(_zz_146)begin + _zz_41 = _zz_88; + end + if(_zz_147)begin + _zz_41 = execute_CsrPlugin_readData; + end + if(execute_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_41 = execute_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_148)begin + _zz_41 = ((execute_INSTRUCTION[13 : 12] == 2'b00) ? execute_MulDivIterativePlugin_accumulator[31 : 0] : execute_MulDivIterativePlugin_accumulator[63 : 32]); + end + end + + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign execute_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_REGFILE_WRITE_DATA = _zz_81; assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; @@ -2330,59 +1887,52 @@ module VexRiscv ( assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = 1'b0; - assign decode_MEMORY_ENABLE = _zz_203[0]; + assign decode_MEMORY_ENABLE = _zz_182[0]; + assign decode_FLUSH_ALL = _zz_183[0]; always @ (*) begin - _zz_56 = execute_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_56 = BranchPlugin_jumpInterface_payload; + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_149)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin - _zz_57 = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_57 = DBusSimplePlugin_redoBranch_payload; + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_150)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_PC = IBusSimplePlugin_injector_decodeInput_payload_pc; - assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; - assign writeBack_PC = memory_to_writeBack_PC; - assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign execute_PC = decode_to_execute_PC; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; always @ (*) begin decode_arbitration_haltItself = 1'b0; if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_136) - 3'b010 : begin - decode_arbitration_haltItself = 1'b1; - end - default : begin - end - endcase end always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_106 || _zz_107)))begin + if((decode_arbitration_isValid && (_zz_89 || _zz_90)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != 1'b0))begin decode_arbitration_haltByOther = 1'b1; end end always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(IBusSimplePlugin_decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2393,22 +1943,25 @@ module VexRiscv ( assign decode_arbitration_flushIt = 1'b0; always @ (*) begin decode_arbitration_flushNext = 1'b0; - if(IBusSimplePlugin_decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_73)))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_56)))begin + execute_arbitration_haltItself = 1'b1; + end + if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && ((! dBus_rsp_ready) || (! _zz_56))))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_155)begin + if(_zz_146)begin if((! execute_LightShifterPlugin_done))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_156)begin + if(_zz_147)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2416,18 +1969,25 @@ module VexRiscv ( if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin execute_arbitration_haltItself = 1'b1; end - end - - always @ (*) begin - execute_arbitration_haltByOther = 1'b0; - if(_zz_157)begin - execute_arbitration_haltByOther = 1'b1; + if(execute_CfuPlugin_CFU_IN_FLIGHT)begin + if((! execute_CfuPlugin_rsp_valid))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_148)begin + if(((! execute_MulDivIterativePlugin_frontendOk) || (! execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_151)begin + execute_arbitration_haltItself = 1'b1; + end end end + assign execute_arbitration_haltByOther = 1'b0; always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(_zz_152)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -2437,164 +1997,73 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_157)begin - if(_zz_158)begin - execute_arbitration_flushIt = 1'b1; - end + if(DBusSimplePlugin_redoBranch_valid)begin + execute_arbitration_flushIt = 1'b1; end end always @ (*) begin execute_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(DBusSimplePlugin_redoBranch_valid)begin execute_arbitration_flushNext = 1'b1; end - if(CsrPlugin_selfException_valid)begin + if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_157)begin - if(_zz_158)begin - execute_arbitration_flushNext = 1'b1; - end - end - end - - always @ (*) begin - memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin - memory_arbitration_haltItself = 1'b1; - end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if((! memory_CfuPlugin_rsp_valid))begin - memory_arbitration_haltItself = 1'b1; - end + if(_zz_152)begin + execute_arbitration_flushNext = 1'b1; end if(_zz_153)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin - memory_arbitration_haltItself = 1'b1; - end - if(_zz_159)begin - memory_arbitration_haltItself = 1'b1; - end + execute_arbitration_flushNext = 1'b1; end if(_zz_154)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin - memory_arbitration_haltItself = 1'b1; - end - end - end - - assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin - memory_arbitration_removeIt = 1'b0; - if(_zz_160)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin - memory_arbitration_removeIt = 1'b1; - end - end - - always @ (*) begin - memory_arbitration_flushIt = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; - end - end - - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(_zz_160)begin - memory_arbitration_flushNext = 1'b1; - end - end - - assign writeBack_arbitration_haltItself = 1'b0; - assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin - writeBack_arbitration_removeIt = 1'b0; - if(writeBack_arbitration_isFlushed)begin - writeBack_arbitration_removeIt = 1'b1; - end - end - - assign writeBack_arbitration_flushIt = 1'b0; - always @ (*) begin - writeBack_arbitration_flushNext = 1'b0; - if(_zz_161)begin - writeBack_arbitration_flushNext = 1'b1; - end - if(_zz_162)begin - writeBack_arbitration_flushNext = 1'b1; + execute_arbitration_flushNext = 1'b1; end end - assign lastStageInstruction = writeBack_INSTRUCTION; - assign lastStagePc = writeBack_PC; - assign lastStageIsValid = writeBack_arbitration_isValid; - assign lastStageIsFiring = writeBack_arbitration_isFiring; + assign lastStageInstruction = execute_INSTRUCTION; + assign lastStagePc = execute_PC; + assign lastStageIsValid = execute_arbitration_isValid; + assign lastStageIsFiring = execute_arbitration_isFiring; always @ (*) begin - IBusSimplePlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin - IBusSimplePlugin_fetcherHalt = 1'b1; - end - if(_zz_161)begin - IBusSimplePlugin_fetcherHalt = 1'b1; - end - if(_zz_162)begin - IBusSimplePlugin_fetcherHalt = 1'b1; + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode} != 2'b00))begin + IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_157)begin - if(_zz_158)begin - IBusSimplePlugin_fetcherHalt = 1'b1; - end - end - if(DebugPlugin_haltIt)begin - IBusSimplePlugin_fetcherHalt = 1'b1; + if(_zz_153)begin + IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_163)begin - IBusSimplePlugin_fetcherHalt = 1'b1; + if(_zz_154)begin + IBusCachedPlugin_fetcherHalt = 1'b1; end end always @ (*) begin - IBusSimplePlugin_incomingInstruction = 1'b0; - if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin - IBusSimplePlugin_incomingInstruction = 1'b1; - end - if(IBusSimplePlugin_injector_decodeInput_valid)begin - IBusSimplePlugin_incomingInstruction = 1'b1; + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; end end assign CsrPlugin_inWfi = 1'b0; - always @ (*) begin - CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin - CsrPlugin_thirdPartyWake = 1'b1; - end - end - + assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_161)begin + if(_zz_153)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_162)begin + if(_zz_154)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_161)begin + if(_zz_153)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_162)begin - case(_zz_164) + if(_zz_154)begin + case(_zz_155) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2604,222 +2073,167 @@ module VexRiscv ( end end + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_externalFlush = ({execute_arbitration_flushNext,decode_arbitration_flushNext} != 2'b00); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); + assign _zz_42 = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}}; + assign _zz_43 = (_zz_42 & (~ _zz_184)); + assign _zz_44 = _zz_43[1]; + assign _zz_45 = _zz_43[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_143; always @ (*) begin - CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin - CsrPlugin_forceMachineWire = 1'b1; + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); always @ (*) begin - CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin - CsrPlugin_allowInterrupts = 1'b0; + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end always @ (*) begin - CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin - CsrPlugin_allowException = 1'b0; + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_186); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); - assign _zz_58 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_59 = (_zz_58 & (~ _zz_204)); - assign _zz_60 = _zz_59[1]; - assign _zz_61 = _zz_59[2]; - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_152; always @ (*) begin - IBusSimplePlugin_fetchPc_correction = 1'b0; - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_correction = 1'b1; + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusSimplePlugin_jump_pcLoad_valid)begin - IBusSimplePlugin_fetchPc_correction = 1'b1; + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; end end - assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; always @ (*) begin - IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin - IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_206); - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; - end - if(IBusSimplePlugin_jump_pcLoad_valid)begin - IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end - IBusSimplePlugin_fetchPc_pc[0] = 1'b0; - IBusSimplePlugin_fetchPc_pc[1] = 1'b0; end + assign _zz_46 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_46); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_46); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin - IBusSimplePlugin_fetchPc_flushed = 1'b0; - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_flushed = 1'b1; - end - if(IBusSimplePlugin_jump_pcLoad_valid)begin - IBusSimplePlugin_fetchPc_flushed = 1'b1; + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); - assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; + assign _zz_47 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_47); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_47); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin - IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin - IBusSimplePlugin_iBusRsp_redoFetch = 1'b1; + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_2 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; - assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; - assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; - always @ (*) begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; - end - if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin - if(IBusSimplePlugin_mmuBus_rsp_refilling)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; - end - if(IBusSimplePlugin_mmuBus_rsp_exception)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - end - end - end - - assign _zz_62 = (! IBusSimplePlugin_iBusRsp_stages_0_halt); - assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_62); - assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_62); - assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; - assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; - assign _zz_63 = (! IBusSimplePlugin_iBusRsp_stages_1_halt); - assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_63); - assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_63); - assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; - assign IBusSimplePlugin_fetchPc_redo_valid = IBusSimplePlugin_iBusRsp_redoFetch; - assign IBusSimplePlugin_fetchPc_redo_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; - assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); - assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_64; - assign _zz_64 = ((1'b0 && (! _zz_65)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); - assign _zz_65 = _zz_66; - assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_65; - assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; + assign _zz_48 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_48); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_48); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_49; + assign _zz_49 = ((1'b0 && (! _zz_50)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_50 = _zz_51; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_50; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_52)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_52 = _zz_53; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_52; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_54; always @ (*) begin - IBusSimplePlugin_iBusRsp_readyForError = 1'b1; - if(IBusSimplePlugin_injector_decodeInput_valid)begin - IBusSimplePlugin_iBusRsp_readyForError = 1'b0; - end - if((! IBusSimplePlugin_pcValids_0))begin - IBusSimplePlugin_iBusRsp_readyForError = 1'b0; - end - end - - assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); - assign IBusSimplePlugin_injector_decodeInput_valid = _zz_67; - assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_68; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_69; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_70; - assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_71; - assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; - assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; - assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; - assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; - assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - always @ (*) begin - decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; - case(_zz_136) - 3'b010 : begin - decode_arbitration_isValid = 1'b1; - end - 3'b011 : begin - decode_arbitration_isValid = 1'b1; - end - default : begin - end - endcase + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end end - assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; - assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; - assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pending_next = (_zz_207 - _zz_211); - assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin - IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); - if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin - if(IBusSimplePlugin_mmuBus_rsp_refilling)begin - IBusSimplePlugin_cmd_valid = 1'b0; - end - if(IBusSimplePlugin_mmuBus_rsp_exception)begin - IBusSimplePlugin_cmd_valid = 1'b0; - end - end - end - - assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); - assign IBusSimplePlugin_mmuBus_cmd_0_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; - assign IBusSimplePlugin_mmuBus_cmd_0_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; - assign IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_externalFlush); - assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],2'b00}; - assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); - assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); - assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; - assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - assign _zz_148 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); - assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_148); - assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_133 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_134 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_135 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_134; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_137 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_138 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_139 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin - IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; - if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin - IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_150)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_149)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; always @ (*) begin - IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_165)begin - IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; - end - end - - assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); - assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; - assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; - assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; - assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; - assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); - assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); - assign _zz_72 = (! IBusSimplePlugin_rspJoin_exceptionDetected); - assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_72); - assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_72); - assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; - assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; - assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; - assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; - always @ (*) begin - IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_165)begin - IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; + _zz_140 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_149)begin + _zz_140 = 1'b1; end end - assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],2'b00}; - assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError); - assign _zz_73 = 1'b0; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_132 = (decode_arbitration_isValid && decode_FLUSH_ALL); always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin @@ -2830,39 +2244,39 @@ module VexRiscv ( end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_73)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_56)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_74 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_57 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_74 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_57 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_74 = execute_RS2[31 : 0]; + _zz_57 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_74; + assign dBus_cmd_payload_data = _zz_57; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_75 = 4'b0001; + _zz_58 = 4'b0001; end 2'b01 : begin - _zz_75 = 4'b0011; + _zz_58 = 4'b0011; end default : begin - _zz_75 = 4'b1111; + _zz_58 = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_75 <<< dBus_cmd_payload_address[1 : 0]); + assign execute_DBusSimplePlugin_formalMask = (_zz_58 <<< dBus_cmd_payload_address[1 : 0]); assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; @@ -2871,129 +2285,129 @@ module VexRiscv ( assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin + if(execute_MMU_RSP2_refilling)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end else begin - if(memory_MMU_FAULT)begin + if(execute_MMU_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_166)begin + if(_zz_156)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(! memory_MMU_RSP2_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); + if(! execute_MMU_RSP2_refilling) begin + if(execute_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (execute_MEMORY_STORE ? 4'b1111 : 4'b1101); end end end - assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA; always @ (*) begin DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin + if(execute_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_166)begin + if(_zz_156)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end - assign DBusSimplePlugin_redoBranch_payload = memory_PC; + assign DBusSimplePlugin_redoBranch_payload = execute_PC; always @ (*) begin - writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; - case(writeBack_MEMORY_ADDRESS_LOW) + execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; + case(execute_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8]; end 2'b10 : begin - writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16]; end 2'b11 : begin - writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24]; end default : begin end endcase end - assign _zz_76 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_77[31] = _zz_76; - _zz_77[30] = _zz_76; - _zz_77[29] = _zz_76; - _zz_77[28] = _zz_76; - _zz_77[27] = _zz_76; - _zz_77[26] = _zz_76; - _zz_77[25] = _zz_76; - _zz_77[24] = _zz_76; - _zz_77[23] = _zz_76; - _zz_77[22] = _zz_76; - _zz_77[21] = _zz_76; - _zz_77[20] = _zz_76; - _zz_77[19] = _zz_76; - _zz_77[18] = _zz_76; - _zz_77[17] = _zz_76; - _zz_77[16] = _zz_76; - _zz_77[15] = _zz_76; - _zz_77[14] = _zz_76; - _zz_77[13] = _zz_76; - _zz_77[12] = _zz_76; - _zz_77[11] = _zz_76; - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_78 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_79[31] = _zz_78; - _zz_79[30] = _zz_78; - _zz_79[29] = _zz_78; - _zz_79[28] = _zz_78; - _zz_79[27] = _zz_78; - _zz_79[26] = _zz_78; - _zz_79[25] = _zz_78; - _zz_79[24] = _zz_78; - _zz_79[23] = _zz_78; - _zz_79[22] = _zz_78; - _zz_79[21] = _zz_78; - _zz_79[20] = _zz_78; - _zz_79[19] = _zz_78; - _zz_79[18] = _zz_78; - _zz_79[17] = _zz_78; - _zz_79[16] = _zz_78; - _zz_79[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_185) + assign _zz_59 = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_60[31] = _zz_59; + _zz_60[30] = _zz_59; + _zz_60[29] = _zz_59; + _zz_60[28] = _zz_59; + _zz_60[27] = _zz_59; + _zz_60[26] = _zz_59; + _zz_60[25] = _zz_59; + _zz_60[24] = _zz_59; + _zz_60[23] = _zz_59; + _zz_60[22] = _zz_59; + _zz_60[21] = _zz_59; + _zz_60[20] = _zz_59; + _zz_60[19] = _zz_59; + _zz_60[18] = _zz_59; + _zz_60[17] = _zz_59; + _zz_60[16] = _zz_59; + _zz_60[15] = _zz_59; + _zz_60[14] = _zz_59; + _zz_60[13] = _zz_59; + _zz_60[12] = _zz_59; + _zz_60[11] = _zz_59; + _zz_60[10] = _zz_59; + _zz_60[9] = _zz_59; + _zz_60[8] = _zz_59; + _zz_60[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_61 = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_62[31] = _zz_61; + _zz_62[30] = _zz_61; + _zz_62[29] = _zz_61; + _zz_62[28] = _zz_61; + _zz_62[27] = _zz_61; + _zz_62[26] = _zz_61; + _zz_62[25] = _zz_61; + _zz_62[24] = _zz_61; + _zz_62[23] = _zz_61; + _zz_62[22] = _zz_61; + _zz_62[21] = _zz_61; + _zz_62[20] = _zz_61; + _zz_62[19] = _zz_61; + _zz_62[18] = _zz_61; + _zz_62[17] = _zz_61; + _zz_62[16] = _zz_61; + _zz_62[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_168) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_77; + execute_DBusSimplePlugin_rspFormated = _zz_60; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_79; + execute_DBusSimplePlugin_rspFormated = _zz_62; end default : begin - writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; end endcase end - assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign IBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign IBusSimplePlugin_mmuBus_busy = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3003,52 +2417,55 @@ module VexRiscv ( assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_81 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_82 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_83 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_84 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_85 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_86 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_87 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); - assign _zz_88 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); - assign _zz_80 = {(((decode_INSTRUCTION & _zz_269) == 32'h00100050) != 1'b0),{((_zz_270 == _zz_271) != 1'b0),{({_zz_272,_zz_273} != 2'b00),{(_zz_274 != _zz_275),{_zz_276,{_zz_277,_zz_278}}}}}}; - assign _zz_89 = _zz_80[1 : 0]; - assign _zz_54 = _zz_89; - assign _zz_90 = _zz_80[6 : 5]; - assign _zz_53 = _zz_90; - assign _zz_91 = _zz_80[13 : 12]; - assign _zz_52 = _zz_91; - assign _zz_92 = _zz_80[16 : 15]; - assign _zz_51 = _zz_92; - assign _zz_93 = _zz_80[19 : 18]; - assign _zz_50 = _zz_93; - assign _zz_94 = _zz_80[22 : 21]; - assign _zz_49 = _zz_94; - assign _zz_95 = _zz_80[25 : 24]; - assign _zz_48 = _zz_95; - assign _zz_96 = _zz_80[27 : 27]; - assign _zz_47 = _zz_96; + assign _zz_64 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_65 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_66 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_67 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz_68 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_69 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_70 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_71 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00001000); + assign _zz_63 = {(_zz_71 != 1'b0),{({_zz_71,_zz_70} != 2'b00),{((_zz_247 == _zz_248) != 1'b0),{1'b0,{(_zz_249 != _zz_250),{_zz_251,{_zz_252,_zz_253}}}}}}}; + assign _zz_72 = _zz_63[2 : 1]; + assign _zz_40 = _zz_72; + assign _zz_73 = _zz_63[7 : 6]; + assign _zz_39 = _zz_73; + assign _zz_74 = _zz_63[14 : 13]; + assign _zz_38 = _zz_74; + assign _zz_75 = _zz_63[17 : 16]; + assign _zz_37 = _zz_75; + assign _zz_76 = _zz_63[20 : 19]; + assign _zz_36 = _zz_76; + assign _zz_77 = _zz_63[23 : 22]; + assign _zz_35 = _zz_77; + assign _zz_78 = _zz_63[26 : 25]; + assign _zz_34 = _zz_78; + assign _zz_79 = _zz_63[28 : 28]; + assign _zz_33 = _zz_79; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_150; - assign decode_RegFilePlugin_rs2Data = _zz_151; + assign decode_RegFilePlugin_rs1Data = _zz_141; + assign decode_RegFilePlugin_rs2Data = _zz_142; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); - if(_zz_97)begin + lastStageRegFileWrite_valid = (_zz_31 && execute_arbitration_isFiring); + if(_zz_80)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; - if(_zz_97)begin + lastStageRegFileWrite_payload_address = _zz_30[11 : 7]; + if(_zz_80)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_55; - if(_zz_97)begin + lastStageRegFileWrite_payload_data = _zz_41; + if(_zz_80)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -3070,101 +2487,101 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_98 = execute_IntAluPlugin_bitwise; + _zz_81 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_98 = {31'd0, _zz_216}; + _zz_81 = {31'd0, _zz_187}; end default : begin - _zz_98 = execute_SRC_ADD_SUB; + _zz_81 = execute_SRC_ADD_SUB; end endcase end always @ (*) begin - case(execute_SRC1_CTRL) + case(decode_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_99 = execute_RS1; + _zz_82 = _zz_26; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_99 = {29'd0, _zz_217}; + _zz_82 = {29'd0, _zz_188}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_99 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_82 = {decode_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_99 = {27'd0, _zz_218}; - end - endcase - end - - assign _zz_100 = _zz_219[11]; - always @ (*) begin - _zz_101[19] = _zz_100; - _zz_101[18] = _zz_100; - _zz_101[17] = _zz_100; - _zz_101[16] = _zz_100; - _zz_101[15] = _zz_100; - _zz_101[14] = _zz_100; - _zz_101[13] = _zz_100; - _zz_101[12] = _zz_100; - _zz_101[11] = _zz_100; - _zz_101[10] = _zz_100; - _zz_101[9] = _zz_100; - _zz_101[8] = _zz_100; - _zz_101[7] = _zz_100; - _zz_101[6] = _zz_100; - _zz_101[5] = _zz_100; - _zz_101[4] = _zz_100; - _zz_101[3] = _zz_100; - _zz_101[2] = _zz_100; - _zz_101[1] = _zz_100; - _zz_101[0] = _zz_100; - end - - assign _zz_102 = _zz_220[11]; - always @ (*) begin - _zz_103[19] = _zz_102; - _zz_103[18] = _zz_102; - _zz_103[17] = _zz_102; - _zz_103[16] = _zz_102; - _zz_103[15] = _zz_102; - _zz_103[14] = _zz_102; - _zz_103[13] = _zz_102; - _zz_103[12] = _zz_102; - _zz_103[11] = _zz_102; - _zz_103[10] = _zz_102; - _zz_103[9] = _zz_102; - _zz_103[8] = _zz_102; - _zz_103[7] = _zz_102; - _zz_103[6] = _zz_102; - _zz_103[5] = _zz_102; - _zz_103[4] = _zz_102; - _zz_103[3] = _zz_102; - _zz_103[2] = _zz_102; - _zz_103[1] = _zz_102; - _zz_103[0] = _zz_102; + _zz_82 = {27'd0, _zz_189}; + end + endcase + end + + assign _zz_83 = _zz_190[11]; + always @ (*) begin + _zz_84[19] = _zz_83; + _zz_84[18] = _zz_83; + _zz_84[17] = _zz_83; + _zz_84[16] = _zz_83; + _zz_84[15] = _zz_83; + _zz_84[14] = _zz_83; + _zz_84[13] = _zz_83; + _zz_84[12] = _zz_83; + _zz_84[11] = _zz_83; + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7] = _zz_83; + _zz_84[6] = _zz_83; + _zz_84[5] = _zz_83; + _zz_84[4] = _zz_83; + _zz_84[3] = _zz_83; + _zz_84[2] = _zz_83; + _zz_84[1] = _zz_83; + _zz_84[0] = _zz_83; + end + + assign _zz_85 = _zz_191[11]; + always @ (*) begin + _zz_86[19] = _zz_85; + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7] = _zz_85; + _zz_86[6] = _zz_85; + _zz_86[5] = _zz_85; + _zz_86[4] = _zz_85; + _zz_86[3] = _zz_85; + _zz_86[2] = _zz_85; + _zz_86[1] = _zz_85; + _zz_86[0] = _zz_85; end always @ (*) begin - case(execute_SRC2_CTRL) + case(decode_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_104 = execute_RS2; + _zz_87 = _zz_24; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_104 = {_zz_101,execute_INSTRUCTION[31 : 20]}; + _zz_87 = {_zz_84,decode_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_104 = {_zz_103,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_87 = {_zz_86,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; end default : begin - _zz_104 = _zz_39; + _zz_87 = _zz_23; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_221; + execute_SrcPlugin_addSub = _zz_192; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3173,194 +2590,166 @@ module VexRiscv ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); - assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_105 = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_88 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_105 = _zz_228; + _zz_88 = _zz_199; end endcase end - - always @ (*) begin - _zz_106 = 1'b0; - if(_zz_108)begin - if((_zz_109 == decode_INSTRUCTION[19 : 15]))begin - _zz_106 = 1'b1; - end - end - if(_zz_167)begin - if(_zz_168)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_106 = 1'b1; - end - end - end - if(_zz_169)begin - if(_zz_170)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_106 = 1'b1; - end + + always @ (*) begin + _zz_89 = 1'b0; + if(_zz_91)begin + if((_zz_92 == decode_INSTRUCTION[19 : 15]))begin + _zz_89 = 1'b1; end end - if(_zz_171)begin - if(_zz_172)begin + if(_zz_157)begin + if(_zz_158)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_106 = 1'b1; + _zz_89 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_106 = 1'b0; + _zz_89 = 1'b0; end end always @ (*) begin - _zz_107 = 1'b0; - if(_zz_108)begin - if((_zz_109 == decode_INSTRUCTION[24 : 20]))begin - _zz_107 = 1'b1; - end - end - if(_zz_167)begin - if(_zz_168)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_107 = 1'b1; - end + _zz_90 = 1'b0; + if(_zz_91)begin + if((_zz_92 == decode_INSTRUCTION[24 : 20]))begin + _zz_90 = 1'b1; end end - if(_zz_169)begin - if(_zz_170)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_107 = 1'b1; - end - end - end - if(_zz_171)begin - if(_zz_172)begin + if(_zz_157)begin + if(_zz_158)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_107 = 1'b1; + _zz_90 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_107 = 1'b0; + _zz_90 = 1'b0; end end assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_110 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_110 == 3'b000)) begin - _zz_111 = execute_BranchPlugin_eq; - end else if((_zz_110 == 3'b001)) begin - _zz_111 = (! execute_BranchPlugin_eq); - end else if((((_zz_110 & 3'b101) == 3'b101))) begin - _zz_111 = (! execute_SRC_LESS); + assign _zz_93 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_93 == 3'b000)) begin + _zz_94 = execute_BranchPlugin_eq; + end else if((_zz_93 == 3'b001)) begin + _zz_94 = (! execute_BranchPlugin_eq); + end else if((((_zz_93 & 3'b101) == 3'b101))) begin + _zz_94 = (! execute_SRC_LESS); end else begin - _zz_111 = execute_SRC_LESS; + _zz_94 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_112 = 1'b0; + _zz_95 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_112 = 1'b1; + _zz_95 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_112 = 1'b1; + _zz_95 = 1'b1; end default : begin - _zz_112 = _zz_111; + _zz_95 = _zz_94; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_113 = _zz_230[19]; - always @ (*) begin - _zz_114[10] = _zz_113; - _zz_114[9] = _zz_113; - _zz_114[8] = _zz_113; - _zz_114[7] = _zz_113; - _zz_114[6] = _zz_113; - _zz_114[5] = _zz_113; - _zz_114[4] = _zz_113; - _zz_114[3] = _zz_113; - _zz_114[2] = _zz_113; - _zz_114[1] = _zz_113; - _zz_114[0] = _zz_113; - end - - assign _zz_115 = _zz_231[11]; - always @ (*) begin - _zz_116[19] = _zz_115; - _zz_116[18] = _zz_115; - _zz_116[17] = _zz_115; - _zz_116[16] = _zz_115; - _zz_116[15] = _zz_115; - _zz_116[14] = _zz_115; - _zz_116[13] = _zz_115; - _zz_116[12] = _zz_115; - _zz_116[11] = _zz_115; - _zz_116[10] = _zz_115; - _zz_116[9] = _zz_115; - _zz_116[8] = _zz_115; - _zz_116[7] = _zz_115; - _zz_116[6] = _zz_115; - _zz_116[5] = _zz_115; - _zz_116[4] = _zz_115; - _zz_116[3] = _zz_115; - _zz_116[2] = _zz_115; - _zz_116[1] = _zz_115; - _zz_116[0] = _zz_115; - end - - assign _zz_117 = _zz_232[11]; + assign _zz_96 = _zz_201[19]; + always @ (*) begin + _zz_97[10] = _zz_96; + _zz_97[9] = _zz_96; + _zz_97[8] = _zz_96; + _zz_97[7] = _zz_96; + _zz_97[6] = _zz_96; + _zz_97[5] = _zz_96; + _zz_97[4] = _zz_96; + _zz_97[3] = _zz_96; + _zz_97[2] = _zz_96; + _zz_97[1] = _zz_96; + _zz_97[0] = _zz_96; + end + + assign _zz_98 = _zz_202[11]; + always @ (*) begin + _zz_99[19] = _zz_98; + _zz_99[18] = _zz_98; + _zz_99[17] = _zz_98; + _zz_99[16] = _zz_98; + _zz_99[15] = _zz_98; + _zz_99[14] = _zz_98; + _zz_99[13] = _zz_98; + _zz_99[12] = _zz_98; + _zz_99[11] = _zz_98; + _zz_99[10] = _zz_98; + _zz_99[9] = _zz_98; + _zz_99[8] = _zz_98; + _zz_99[7] = _zz_98; + _zz_99[6] = _zz_98; + _zz_99[5] = _zz_98; + _zz_99[4] = _zz_98; + _zz_99[3] = _zz_98; + _zz_99[2] = _zz_98; + _zz_99[1] = _zz_98; + _zz_99[0] = _zz_98; + end + + assign _zz_100 = _zz_203[11]; always @ (*) begin - _zz_118[18] = _zz_117; - _zz_118[17] = _zz_117; - _zz_118[16] = _zz_117; - _zz_118[15] = _zz_117; - _zz_118[14] = _zz_117; - _zz_118[13] = _zz_117; - _zz_118[12] = _zz_117; - _zz_118[11] = _zz_117; - _zz_118[10] = _zz_117; - _zz_118[9] = _zz_117; - _zz_118[8] = _zz_117; - _zz_118[7] = _zz_117; - _zz_118[6] = _zz_117; - _zz_118[5] = _zz_117; - _zz_118[4] = _zz_117; - _zz_118[3] = _zz_117; - _zz_118[2] = _zz_117; - _zz_118[1] = _zz_117; - _zz_118[0] = _zz_117; + _zz_101[18] = _zz_100; + _zz_101[17] = _zz_100; + _zz_101[16] = _zz_100; + _zz_101[15] = _zz_100; + _zz_101[14] = _zz_100; + _zz_101[13] = _zz_100; + _zz_101[12] = _zz_100; + _zz_101[11] = _zz_100; + _zz_101[10] = _zz_100; + _zz_101[9] = _zz_100; + _zz_101[8] = _zz_100; + _zz_101[7] = _zz_100; + _zz_101[6] = _zz_100; + _zz_101[5] = _zz_100; + _zz_101[4] = _zz_100; + _zz_101[3] = _zz_100; + _zz_101[2] = _zz_100; + _zz_101[1] = _zz_100; + _zz_101[0] = _zz_100; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_119 = {{_zz_114,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_102 = {{_zz_97,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_119 = {_zz_116,execute_INSTRUCTION[31 : 20]}; + _zz_102 = {_zz_99,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_119 = {{_zz_118,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_102 = {{_zz_101,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_119; + assign execute_BranchPlugin_branch_src2 = _zz_102; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; @@ -3373,16 +2762,19 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_120 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_121 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_122 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_103 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_104 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_105 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_123 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_124 = _zz_233[0]; + assign _zz_106 = {CfuPlugin_joinException_valid,{CsrPlugin_selfException_valid,DBusSimplePlugin_memoryExceptionPort_valid}}; + assign _zz_107 = (_zz_106 & (~ _zz_204)); + assign _zz_108 = _zz_107[1]; + assign _zz_109 = _zz_107[2]; + assign _zz_110 = {_zz_109,_zz_108}; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(IBusSimplePlugin_decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3392,7 +2784,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(_zz_152)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -3400,33 +2792,14 @@ module VexRiscv ( end end - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_160)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; - end - end - - always @ (*) begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(writeBack_arbitration_isFlushed)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; - end - end - assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_0; + if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != 1'b0))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -3472,7 +2845,7 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + assign execute_CsrPlugin_blockedBySideEffects = (1'b0 || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; if(execute_CsrPlugin_csr_768)begin @@ -3520,7 +2893,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_173)begin + if(_zz_159)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3539,14 +2912,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_174)begin + if(_zz_160)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_174)begin + if(_zz_160)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3561,14 +2934,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_173)begin + if(_zz_159)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_173)begin + if(_zz_159)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -3577,7 +2950,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_186) + case(_zz_169) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3590,58 +2963,58 @@ module VexRiscv ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_235; + assign execute_CfuPlugin_functionsIds_0 = _zz_205; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_125 = _zz_236[7]; - always @ (*) begin - _zz_126[23] = _zz_125; - _zz_126[22] = _zz_125; - _zz_126[21] = _zz_125; - _zz_126[20] = _zz_125; - _zz_126[19] = _zz_125; - _zz_126[18] = _zz_125; - _zz_126[17] = _zz_125; - _zz_126[16] = _zz_125; - _zz_126[15] = _zz_125; - _zz_126[14] = _zz_125; - _zz_126[13] = _zz_125; - _zz_126[12] = _zz_125; - _zz_126[11] = _zz_125; - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; + assign _zz_111 = _zz_206[7]; + always @ (*) begin + _zz_112[23] = _zz_111; + _zz_112[22] = _zz_111; + _zz_112[21] = _zz_111; + _zz_112[20] = _zz_111; + _zz_112[19] = _zz_111; + _zz_112[18] = _zz_111; + _zz_112[17] = _zz_111; + _zz_112[16] = _zz_111; + _zz_112[15] = _zz_111; + _zz_112[14] = _zz_111; + _zz_112[13] = _zz_111; + _zz_112[12] = _zz_111; + _zz_112[11] = _zz_111; + _zz_112[10] = _zz_111; + _zz_112[9] = _zz_111; + _zz_112[8] = _zz_111; + _zz_112[7] = _zz_111; + _zz_112[6] = _zz_111; + _zz_112[5] = _zz_111; + _zz_112[4] = _zz_111; + _zz_112[3] = _zz_111; + _zz_112[2] = _zz_111; + _zz_112[1] = _zz_111; + _zz_112[0] = _zz_111; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_127 = execute_RS2; + _zz_113 = execute_RS2; end default : begin - _zz_127 = {_zz_126,execute_INSTRUCTION[31 : 24]}; + _zz_113 = {_zz_112,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_127; - assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); - assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); - assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); - assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_113; + assign execute_CfuPlugin_rsp_valid = CfuPlugin_bus_rsp_valid; + assign CfuPlugin_bus_rsp_ready = execute_CfuPlugin_rsp_ready; + assign execute_CfuPlugin_rsp_payload_response_ok = CfuPlugin_bus_rsp_payload_response_ok; + assign execute_CfuPlugin_rsp_payload_outputs_0 = CfuPlugin_bus_rsp_payload_outputs_0; always @ (*) begin CfuPlugin_joinException_valid = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if(memory_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); + if(execute_CfuPlugin_CFU_IN_FLIGHT)begin + if(execute_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! execute_CfuPlugin_rsp_payload_response_ok); end end end @@ -3649,281 +3022,181 @@ module VexRiscv ( assign CfuPlugin_joinException_payload_code = 4'b1111; assign CfuPlugin_joinException_payload_badAddr = 32'h0; always @ (*) begin - memory_CfuPlugin_rsp_ready = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); - end - end - - assign memory_MulDivIterativePlugin_frontendOk = 1'b1; - always @ (*) begin - memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_153)begin - if(_zz_159)begin - memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; - end - end - end - - always @ (*) begin - memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; - if((! memory_arbitration_isStuck))begin - memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; - end - end - - assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); - assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); - always @ (*) begin - if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; - end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_238); - end - if(memory_MulDivIterativePlugin_mul_counter_willClear)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + execute_CfuPlugin_rsp_ready = 1'b0; + if(execute_CfuPlugin_CFU_IN_FLIGHT)begin + execute_CfuPlugin_rsp_ready = (! execute_arbitration_isStuckByOthers); end end always @ (*) begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_154)begin - if(_zz_175)begin - memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; + execute_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; + if(_zz_148)begin + if(_zz_151)begin + execute_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end end always @ (*) begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_176)begin - memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; + execute_MulDivIterativePlugin_mul_counter_willClear = 1'b0; + if((! execute_arbitration_isStuck))begin + execute_MulDivIterativePlugin_mul_counter_willClear = 1'b1; end end - assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); - assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); + assign execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (execute_MulDivIterativePlugin_mul_counter_value == 6'h20); + assign execute_MulDivIterativePlugin_mul_counter_willOverflow = (execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc && execute_MulDivIterativePlugin_mul_counter_willIncrement); always @ (*) begin - if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; + if(execute_MulDivIterativePlugin_mul_counter_willOverflow)begin + execute_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_246); - end - if(memory_MulDivIterativePlugin_div_counter_willClear)begin - memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; - end - end - - assign _zz_128 = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_128[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_247); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_248 : _zz_249); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_250[31:0]; - assign _zz_129 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_130 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_131 = ((execute_IS_MUL && _zz_130) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_132[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_132[31 : 0] = execute_RS1; - end - - assign _zz_134 = (_zz_133 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_134 != 32'h0); - always @ (*) begin - debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_177) - 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin - debug_bus_cmd_ready = IBusSimplePlugin_injectionPort_ready; - end - end - default : begin - end - endcase - end - end - - always @ (*) begin - debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_135))begin - debug_bus_rsp_data[0] = DebugPlugin_resetIt; - debug_bus_rsp_data[1] = DebugPlugin_haltIt; - debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; - debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; - debug_bus_rsp_data[4] = DebugPlugin_stepIt; - end - end - - always @ (*) begin - IBusSimplePlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_177) - 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin - IBusSimplePlugin_injectionPort_valid = 1'b1; - end - end - default : begin - end - endcase - end - end - - assign IBusSimplePlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); - assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_28 = decode_SRC1_CTRL; - assign _zz_26 = _zz_54; - assign _zz_41 = decode_to_execute_SRC1_CTRL; - assign _zz_25 = decode_SRC2_CTRL; - assign _zz_23 = _zz_53; - assign _zz_40 = decode_to_execute_SRC2_CTRL; - assign _zz_22 = decode_ALU_CTRL; - assign _zz_20 = _zz_52; - assign _zz_42 = decode_to_execute_ALU_CTRL; - assign _zz_19 = decode_ALU_BITWISE_CTRL; - assign _zz_17 = _zz_51; - assign _zz_43 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_16 = decode_SHIFT_CTRL; - assign _zz_14 = _zz_50; - assign _zz_38 = decode_to_execute_SHIFT_CTRL; - assign _zz_13 = decode_BRANCH_CTRL; - assign _zz_11 = _zz_49; - assign _zz_36 = decode_to_execute_BRANCH_CTRL; - assign _zz_10 = decode_ENV_CTRL; - assign _zz_7 = execute_ENV_CTRL; - assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_48; - assign _zz_34 = decode_to_execute_ENV_CTRL; - assign _zz_33 = execute_to_memory_ENV_CTRL; - assign _zz_35 = memory_to_writeBack_ENV_CTRL; + execute_MulDivIterativePlugin_mul_counter_valueNext = (execute_MulDivIterativePlugin_mul_counter_value + _zz_208); + end + if(execute_MulDivIterativePlugin_mul_counter_willClear)begin + execute_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + end + end + + assign _zz_114 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_115 = ((execute_IS_MUL && _zz_114) || 1'b0); + always @ (*) begin + _zz_116[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_116[31 : 0] = execute_RS1; + end + + assign _zz_118 = (_zz_117 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_118 != 32'h0); + assign _zz_27 = _zz_40; + assign _zz_25 = _zz_39; + assign _zz_18 = decode_ALU_CTRL; + assign _zz_16 = _zz_38; + assign _zz_28 = decode_to_execute_ALU_CTRL; + assign _zz_15 = decode_ALU_BITWISE_CTRL; + assign _zz_13 = _zz_37; + assign _zz_29 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_12 = decode_SHIFT_CTRL; + assign _zz_10 = _zz_36; + assign _zz_22 = decode_to_execute_SHIFT_CTRL; + assign _zz_9 = decode_BRANCH_CTRL; + assign _zz_7 = _zz_35; + assign _zz_21 = decode_to_execute_BRANCH_CTRL; + assign _zz_6 = decode_ENV_CTRL; + assign _zz_4 = _zz_34; + assign _zz_20 = decode_to_execute_ENV_CTRL; assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_47; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; - assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); - assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); - assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); - assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign _zz_1 = _zz_33; + assign _zz_19 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign decode_arbitration_isFlushed = ((execute_arbitration_flushNext != 1'b0) || ({execute_arbitration_flushIt,decode_arbitration_flushIt} != 2'b00)); + assign execute_arbitration_isFlushed = (1'b0 || (execute_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0); assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); - assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); - assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); - assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); - assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); - assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); - assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); - assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); - assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - IBusSimplePlugin_injectionPort_ready = 1'b0; - case(_zz_136) - 3'b100 : begin - IBusSimplePlugin_injectionPort_ready = 1'b1; - end - default : begin - end - endcase - end - always @ (*) begin - _zz_137 = 32'h0; + _zz_119 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_137[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_137[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_137[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_119[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_119[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_119[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_138 = 32'h0; + _zz_120 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_138[11 : 11] = CsrPlugin_mip_MEIP; - _zz_138[7 : 7] = CsrPlugin_mip_MTIP; - _zz_138[3 : 3] = CsrPlugin_mip_MSIP; + _zz_120[11 : 11] = CsrPlugin_mip_MEIP; + _zz_120[7 : 7] = CsrPlugin_mip_MTIP; + _zz_120[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_139 = 32'h0; + _zz_121 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_139[11 : 11] = CsrPlugin_mie_MEIE; - _zz_139[7 : 7] = CsrPlugin_mie_MTIE; - _zz_139[3 : 3] = CsrPlugin_mie_MSIE; + _zz_121[11 : 11] = CsrPlugin_mie_MEIE; + _zz_121[7 : 7] = CsrPlugin_mie_MTIE; + _zz_121[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_140 = 32'h0; + _zz_122 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_140[31 : 0] = CsrPlugin_mepc; + _zz_122[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_141 = 32'h0; + _zz_123 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_141[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_141[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_123[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_123[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_142 = 32'h0; + _zz_124 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_142[31 : 0] = CsrPlugin_mtval; + _zz_124[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_143 = 32'h0; + _zz_125 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_143[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_125[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_144 = 32'h0; + _zz_126 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_144[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_126[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_145 = 32'h0; + _zz_127 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_145[31 : 0] = _zz_133; + _zz_127[31 : 0] = _zz_117; end end always @ (*) begin - _zz_146 = 32'h0; + _zz_128 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_146[31 : 0] = _zz_134; + _zz_128[31 : 0] = _zz_118; end end - assign execute_CsrPlugin_readData = ((((_zz_137 | _zz_138) | (_zz_139 | _zz_140)) | ((_zz_141 | _zz_142) | (_zz_143 | _zz_144))) | (_zz_145 | _zz_146)); - assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); - assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; - assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; - assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); - assign iBusWishbone_CTI = 3'b000; + assign execute_CsrPlugin_readData = ((((_zz_119 | _zz_120) | (_zz_121 | _zz_122)) | ((_zz_123 | _zz_124) | (_zz_125 | _zz_126))) | (_zz_127 | _zz_128)); + assign iBusWishbone_ADR = {_zz_225,_zz_129}; + assign iBusWishbone_CTI = ((_zz_129 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; - assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; - assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; - assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK); - assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_161)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_161)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_130; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; @@ -3937,19 +3210,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_147 = 4'b0001; + _zz_131 = 4'b0001; end 2'b01 : begin - _zz_147 = 4'b0011; + _zz_131 = 4'b0011; end default : begin - _zz_147 = 4'b1111; + _zz_131 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_147 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_131 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -3963,25 +3236,23 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - assign _zz_149 = 1'b0; always @ (posedge clk) begin if(reset) begin - IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; - IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; - IBusSimplePlugin_fetchPc_booted <= 1'b0; - IBusSimplePlugin_fetchPc_inc <= 1'b0; - _zz_66 <= 1'b0; - _zz_67 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusSimplePlugin_pending_value <= 3'b000; - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; - _zz_97 <= 1'b1; + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_51 <= 1'b0; + _zz_53 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_55; + IBusCachedPlugin_rspCounter <= 32'h0; + _zz_56 <= 1'b0; + _zz_80 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_108 <= 1'b0; + _zz_91 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3990,130 +3261,88 @@ module VexRiscv ( CsrPlugin_mie_MSIE <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; - memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - _zz_133 <= 32'h0; + execute_MulDivIterativePlugin_frontendOk <= 1'b0; + execute_MulDivIterativePlugin_mul_counter_value <= 6'h0; + _zz_117 <= 32'h0; execute_arbitration_isValid <= 1'b0; - memory_arbitration_isValid <= 1'b0; - writeBack_arbitration_isValid <= 1'b0; - _zz_136 <= 3'b000; - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - iBus_cmd_m2sPipe_rValid <= 1'b0; + _zz_129 <= 3'b000; + _zz_130 <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin - if(IBusSimplePlugin_fetchPc_correction)begin - IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin - IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end - IBusSimplePlugin_fetchPc_booted <= 1'b1; - if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin - IBusSimplePlugin_fetchPc_inc <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin - IBusSimplePlugin_fetchPc_inc <= 1'b1; + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin - IBusSimplePlugin_fetchPc_inc <= 1'b0; + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin - IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusSimplePlugin_iBusRsp_flush)begin - _zz_66 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_51 <= 1'b0; end - if(_zz_64)begin - _zz_66 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_49)begin + _zz_51 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(decode_arbitration_removeIt)begin - _zz_67 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_53 <= 1'b0; end - if(IBusSimplePlugin_iBusRsp_output_ready)begin - _zz_67 <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_53 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin - IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end if((! execute_arbitration_isStuck))begin - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if((! memory_arbitration_isStuck))begin - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; + if((dBus_cmd_valid && dBus_cmd_ready))begin + _zz_56 <= 1'b1; end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; - end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - if((! writeBack_arbitration_isStuck))begin - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; - end - if(IBusSimplePlugin_fetchPc_flushed)begin - IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; - end - IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_213); - if(IBusSimplePlugin_iBusRsp_flush)begin - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_215); + if((! execute_arbitration_isStuck))begin + _zz_56 <= 1'b0; end - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); - `else - if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin - $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); - $finish; - end - `endif - `endif - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); - `else - if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin - $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); - $finish; - end - `endif - `endif - _zz_97 <= 1'b0; - if(_zz_155)begin - if(_zz_178)begin + _zz_80 <= 1'b0; + if(_zz_146)begin + if(_zz_162)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -4123,7 +3352,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_108 <= (_zz_45 && writeBack_arbitration_isFiring); + _zz_91 <= (_zz_31 && execute_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -4132,27 +3361,17 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; - end - if((! memory_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; - end - if((! writeBack_arbitration_isStuck))begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); - end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_179)begin - if(_zz_180)begin + if(_zz_163)begin + if(_zz_164)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_181)begin + if(_zz_165)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_182)begin + if(_zz_166)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4160,23 +3379,15 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin - CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; - end - if((! writeBack_arbitration_isStuck))begin - CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; - end end if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; - CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end if(CsrPlugin_interruptJump)begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_161)begin + if(_zz_153)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4187,8 +3398,8 @@ module VexRiscv ( end endcase end - if(_zz_162)begin - case(_zz_164) + if(_zz_154)begin + case(_zz_155) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4198,7 +3409,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_122,{_zz_121,_zz_120}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_105,{_zz_104,_zz_103}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -4211,81 +3422,45 @@ module VexRiscv ( if((! execute_arbitration_isStuckByOthers))begin execute_CfuPlugin_fired <= 1'b0; end - if(memory_CfuPlugin_rsp_ready)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + if(((execute_arbitration_isValid && (! 1'b0)) && (1'b0 || execute_IS_MUL)))begin + execute_MulDivIterativePlugin_frontendOk <= 1'b1; end - if(_zz_183)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; - end - memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; - memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + if(execute_arbitration_isMoving)begin + execute_MulDivIterativePlugin_frontendOk <= 1'b0; end + execute_MulDivIterativePlugin_mul_counter_value <= execute_MulDivIterativePlugin_mul_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin - memory_arbitration_isValid <= 1'b0; - end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin - memory_arbitration_isValid <= execute_arbitration_isValid; - end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin - writeBack_arbitration_isValid <= 1'b0; - end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin - writeBack_arbitration_isValid <= memory_arbitration_isValid; - end - case(_zz_136) - 3'b000 : begin - if(IBusSimplePlugin_injectionPort_valid)begin - _zz_136 <= 3'b001; - end - end - 3'b001 : begin - _zz_136 <= 3'b010; - end - 3'b010 : begin - _zz_136 <= 3'b011; - end - 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_136 <= 3'b100; - end - end - 3'b100 : begin - _zz_136 <= 3'b000; - end - default : begin - end - endcase if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_260[0]; - CsrPlugin_mstatus_MIE <= _zz_261[0]; + CsrPlugin_mstatus_MPIE <= _zz_219[0]; + CsrPlugin_mstatus_MIE <= _zz_220[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_263[0]; - CsrPlugin_mie_MTIE <= _zz_264[0]; - CsrPlugin_mie_MSIE <= _zz_265[0]; + CsrPlugin_mie_MEIE <= _zz_222[0]; + CsrPlugin_mie_MTIE <= _zz_223[0]; + CsrPlugin_mie_MSIE <= _zz_224[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_133 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_117 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(iBus_cmd_ready)begin - iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; + if(_zz_161)begin + if(iBusWishbone_ACK)begin + _zz_129 <= (_zz_129 + 3'b001); + end end - if(_zz_184)begin + _zz_130 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_167)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -4296,71 +3471,59 @@ module VexRiscv ( end always @ (posedge clk) begin - if(IBusSimplePlugin_iBusRsp_output_ready)begin - _zz_68 <= IBusSimplePlugin_iBusRsp_output_payload_pc; - _zz_69 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; - _zz_70 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; - _zz_71 <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; - end - if(IBusSimplePlugin_injector_decodeInput_ready)begin - IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; - end - if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin - IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; - IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; - IBusSimplePlugin_mmu_joinCtx_isPaging <= IBusSimplePlugin_mmuBus_rsp_isPaging; - IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; - IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; - IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; - IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; - IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; - IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; - end - if(_zz_155)begin - if(_zz_178)begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_54 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_LightShifterPlugin_shiftReg <= _zz_41; + end + if(_zz_146)begin + if(_zz_162)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - _zz_109 <= _zz_44[11 : 7]; + _zz_92 <= _zz_30[11 : 7]; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(execute_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(IBusSimplePlugin_decodeExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= IBusSimplePlugin_decodeExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= IBusSimplePlugin_decodeExceptionPort_payload_badAddr; + if(decodeExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= decodeExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= decodeExceptionPort_payload_badAddr; end - if(CsrPlugin_selfException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; - end - if(_zz_160)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_124 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_124 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(_zz_152)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= _zz_144; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= _zz_145; end - if(_zz_179)begin - if(_zz_180)begin + if(_zz_163)begin + if(_zz_164)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_181)begin + if(_zz_165)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_182)begin + if(_zz_166)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_161)begin + if(_zz_153)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= writeBack_PC; + CsrPlugin_mepc <= execute_PC; if(CsrPlugin_hadException)begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end @@ -4369,136 +3532,59 @@ module VexRiscv ( end endcase end - if(_zz_183)begin - CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; - end - if(_zz_153)begin - if(_zz_159)begin - memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_239,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); - end - end - if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_done <= 1'b1; - end - if((! memory_arbitration_isStuck))begin - memory_MulDivIterativePlugin_div_done <= 1'b0; - end - if(_zz_154)begin - if(_zz_175)begin - memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; - memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; - if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_result <= _zz_251[31:0]; - end + if(_zz_148)begin + if(_zz_151)begin + execute_MulDivIterativePlugin_rs2 <= (execute_MulDivIterativePlugin_rs2 >>> 1); + execute_MulDivIterativePlugin_accumulator <= ({_zz_209,execute_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end - if(_zz_176)begin - memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_131 ? (~ _zz_132) : _zz_132) + _zz_257); - memory_MulDivIterativePlugin_rs2 <= ((_zz_130 ? (~ execute_RS2) : execute_RS2) + _zz_259); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_131 ^ (_zz_130 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if((! execute_MulDivIterativePlugin_frontendOk))begin + execute_MulDivIterativePlugin_accumulator <= 65'h0; + execute_MulDivIterativePlugin_rs1 <= ((_zz_115 ? (~ _zz_116) : _zz_116) + _zz_216); + execute_MulDivIterativePlugin_rs2 <= ((_zz_114 ? (~ execute_RS2) : execute_RS2) + _zz_218); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin - decode_to_execute_PC <= decode_PC; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_39; - end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin - memory_to_writeBack_PC <= memory_PC; + if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin + decode_to_execute_PC <= _zz_23; end if((! execute_arbitration_isStuck))begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; - end if((! execute_arbitration_isStuck))begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_56; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_57; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_27; - end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_24; - end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; - end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; - end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_21; + decode_to_execute_ALU_CTRL <= _zz_17; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_18; + decode_to_execute_ALU_BITWISE_CTRL <= _zz_14; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_15; + decode_to_execute_SHIFT_CTRL <= _zz_11; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_12; + decode_to_execute_BRANCH_CTRL <= _zz_8; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_CSR <= decode_IS_CSR; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4; + decode_to_execute_ENV_CTRL <= _zz_5; end if((! execute_arbitration_isStuck))begin decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; @@ -4509,9 +3595,6 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_MUL <= execute_IS_MUL; - end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end @@ -4519,19 +3602,19 @@ module VexRiscv ( decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_DIV <= decode_IS_DIV; + decode_to_execute_RS1 <= _zz_26; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_DIV <= execute_IS_DIV; + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= _zz_24; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= decode_RS1; + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= decode_RS2; + decode_to_execute_SRC1 <= decode_SRC1; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + decode_to_execute_SRC2 <= decode_SRC2; end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; @@ -4539,44 +3622,6 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; - execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; - execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; - execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; - execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; - execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; - execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; - execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; - execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; - end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_31; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_29; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; - end - if((_zz_136 != 3'b000))begin - _zz_70 <= IBusSimplePlugin_injectionPort_payload; - end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end @@ -4612,7 +3657,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_262[0]; + CsrPlugin_mip_MSIP <= _zz_221[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -4626,10 +3671,8 @@ module VexRiscv ( CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; end end - if(iBus_cmd_ready)begin - iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; - end - if(_zz_184)begin + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_167)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; @@ -4637,203 +3680,288 @@ module VexRiscv ( end end - always @ (posedge clk) begin - DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin - DebugPlugin_firstCycle <= 1'b1; - end - DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusSimplePlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_55; - end - _zz_135 <= debug_bus_cmd_payload_address[2]; - if(_zz_157)begin - DebugPlugin_busReadDataReg <= execute_PC; - end - DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; - end - - always @ (posedge clk) begin - if(debugReset) begin - DebugPlugin_resetIt <= 1'b0; - DebugPlugin_haltIt <= 1'b0; - DebugPlugin_stepIt <= 1'b0; - DebugPlugin_godmode <= 1'b0; - DebugPlugin_haltedByBreak <= 1'b0; - end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin - DebugPlugin_godmode <= 1'b1; - end - if(debug_bus_cmd_valid)begin - case(_zz_177) - 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin - DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin - DebugPlugin_resetIt <= 1'b1; - end - if(debug_bus_cmd_payload_data[24])begin - DebugPlugin_resetIt <= 1'b0; - end - if(debug_bus_cmd_payload_data[17])begin - DebugPlugin_haltIt <= 1'b1; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_haltIt <= 1'b0; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_haltedByBreak <= 1'b0; - end - if(debug_bus_cmd_payload_data[25])begin - DebugPlugin_godmode <= 1'b0; - end - end - end - default : begin - end - endcase - end - if(_zz_157)begin - if(_zz_158)begin - DebugPlugin_haltIt <= 1'b1; - DebugPlugin_haltedByBreak <= 1'b1; - end - end - if(_zz_163)begin - if(decode_arbitration_isValid)begin - DebugPlugin_haltIt <= 1'b1; - end - end - end - end - endmodule -module StreamFifoLowLatency ( - input io_push_valid, - output io_push_ready, - input io_push_payload_error, - input [31:0] io_push_payload_inst, - output reg io_pop_valid, - input io_pop_ready, - output reg io_pop_payload_error, - output reg [31:0] io_pop_payload_inst, +module InstructionCache ( input io_flush, - output [0:0] io_occupancy, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, input clk, input reset ); - wire _zz_4; - wire [0:0] _zz_5; + reg [31:0] _zz_9; + reg [24:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [24:0] _zz_15; reg _zz_1; - reg pushPtr_willIncrement; - reg pushPtr_willClear; - wire pushPtr_willOverflowIfInc; - wire pushPtr_willOverflow; - reg popPtr_willIncrement; - reg popPtr_willClear; - wire popPtr_willOverflowIfInc; - wire popPtr_willOverflow; - wire ptrMatch; - reg risingOccupancy; - wire empty; - wire full; - wire pushing; - wire popping; - wire [32:0] _zz_2; - reg [32:0] _zz_3; - - assign _zz_4 = (! empty); - assign _zz_5 = _zz_2[0 : 0]; - always @ (*) begin - _zz_1 = 1'b0; - if(pushing)begin - _zz_1 = 1'b1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [4:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [3:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [22:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [6:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [6:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [3:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [22:0] fetchStage_read_waysValues_0_tag_address; + wire [24:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:127]; + (* ram_style = "block" *) reg [24:0] ways_0_tags [0:15]; + + assign _zz_11 = (! lineLoader_flushCounter[4]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (*) begin - pushPtr_willIncrement = 1'b0; - if(pushing)begin - pushPtr_willIncrement = 1'b1; + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; end end - always @ (*) begin - pushPtr_willClear = 1'b0; - if(io_flush)begin - pushPtr_willClear = 1'b1; + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; end end - assign pushPtr_willOverflowIfInc = 1'b1; - assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); - always @ (*) begin - popPtr_willIncrement = 1'b0; - if(popping)begin - popPtr_willIncrement = 1'b1; + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; end end always @ (*) begin - popPtr_willClear = 1'b0; - if(io_flush)begin - popPtr_willClear = 1'b1; + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; end end - assign popPtr_willOverflowIfInc = 1'b1; - assign popPtr_willOverflow = (popPtr_willOverflowIfInc && popPtr_willIncrement); - assign ptrMatch = 1'b1; - assign empty = (ptrMatch && (! risingOccupancy)); - assign full = (ptrMatch && risingOccupancy); - assign pushing = (io_push_valid && io_push_ready); - assign popping = (io_pop_valid && io_pop_ready); - assign io_push_ready = (! full); always @ (*) begin - if(_zz_4)begin - io_pop_valid = 1'b1; - end else begin - io_pop_valid = io_push_valid; + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; end end - assign _zz_2 = _zz_3; always @ (*) begin - if(_zz_4)begin - io_pop_payload_error = _zz_5[0]; - end else begin - io_pop_payload_error = io_push_payload_error; + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end end end always @ (*) begin - if(_zz_4)begin - io_pop_payload_inst = _zz_2[32 : 1]; - end else begin - io_pop_payload_inst = io_push_payload_inst; + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; end - end - - assign io_occupancy = (risingOccupancy && ptrMatch); + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[4])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[4] ? lineLoader_address[8 : 5] : lineLoader_flushCounter[3 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[4]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 9]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[8 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[8 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[8 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[24 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 9])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; always @ (posedge clk) begin if(reset) begin - risingOccupancy <= 1'b0; + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; end else begin - if((pushing != popping))begin - risingOccupancy <= pushing; + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; end if(io_flush)begin - risingOccupancy <= 1'b0; + lineLoader_flushPending <= 1'b1; + end + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end end end end always @ (posedge clk) begin - if(_zz_1)begin - _zz_3 <= {io_push_payload_inst,io_push_payload_error}; + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 5'h01); + end + _zz_3 <= lineLoader_flushCounter[4]; + if(_zz_12)begin + lineLoader_flushCounter <= 5'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml index 3eeb252..fa5fb80 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml @@ -1 +1,4 @@ -debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 512} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index a1097b3..d6f2792 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -32,12 +32,14 @@ case class ArgConfig( atomics: Boolean = false, compressedGen: Boolean = false, singleCycleMulDiv : Boolean = true, + hardwareDiv: Boolean = true, singleCycleShift : Boolean = true, relaxedPcCalculation : Boolean = false, bypass : Boolean = true, externalInterruptArray : Boolean = true, resetVector : BigInt = null, machineTrapVector : BigInt = null, + memoryAndWritebackStage : Boolean = true, prediction : BranchPrediction = STATIC, outputFile : String = "VexRiscv", csrPluginConfig : String = "small", @@ -71,6 +73,7 @@ object GenCoreDefault{ opt[Boolean]("atomics") action { (v, c) => c.copy(mulDiv = v) } text("set RV32I[A]") opt[Boolean]("compressedGen") action { (v, c) => c.copy(compressedGen = v) } text("set RV32I[C]") opt[Boolean]("singleCycleMulDiv") action { (v, c) => c.copy(singleCycleMulDiv = v) } text("If true, MUL/DIV are single-cycle") + opt[Boolean]("hardwareDiv") action { (v, c) => c.copy(hardwareDiv = v) } text ("Default true; if false, turns off any _iterative_ hardware division.") opt[Boolean]("singleCycleShift") action { (v, c) => c.copy(singleCycleShift = v) } text("If true, SHIFTS are single-cycle") opt[Boolean]("relaxedPcCalculation") action { (v, c) => c.copy(relaxedPcCalculation = v) } text("If true, one extra stage will be added to the fetch to improve timings") opt[Boolean]("bypass") action { (v, c) => c.copy(bypass = v) } text("set pipeline interlock/bypass") @@ -79,6 +82,7 @@ object GenCoreDefault{ opt[Boolean]("dBusCachedEarlyWaysHits") action { (v, c) => c.copy(dBusCachedEarlyWaysHits = v) } text("If set, the d$ way hit calculation is done in the memory stage, else in the writeback stage.") opt[String]("resetVector") action { (v, c) => c.copy(resetVector = BigInt(if(v.startsWith("0x")) v.tail.tail else v, 16)) } text("Specify the CPU reset vector in hexadecimal. If not specified, an 32 bits input is added to the CPU to set durring instanciation") opt[String]("machineTrapVector") action { (v, c) => c.copy(machineTrapVector = BigInt(if(v.startsWith("0x")) v.tail.tail else v, 16)) } text("Specify the CPU machine trap vector in hexadecimal. If not specified, it take a unknown value when the design boot") + opt[Boolean]("memoryAndWritebackStage") action { (v, c) => c.copy(memoryAndWritebackStage = v) } text("Default true; if false, removes the memory and writeback stages.") opt[String]("prediction") action { (v, c) => c.copy(prediction = predictionMap(v)) } text("switch between regular CSR and array like one") opt[String]("outputFile") action { (v, c) => c.copy(outputFile = v) } text("output file name") opt[String]("csrPluginConfig") action { (v, c) => c.copy(csrPluginConfig = v) } text("switch between 'small', 'mcycle', 'all', 'linux' and 'linux-minimal' version of control and status registers configuration") @@ -160,7 +164,7 @@ object GenCoreDefault{ ioRange = _.msb ), new DecoderSimplePlugin( - catchIllegalInstruction = argConfig.safe + catchIllegalInstruction = argConfig.safe || !argConfig.hardwareDiv ), new RegFilePlugin( regFileReadyKind = plugin.SYNC, @@ -169,7 +173,7 @@ object GenCoreDefault{ new IntAluPlugin, new SrcPlugin( separatedAddSub = false, - executeInsertion = true + executeInsertion = argConfig.memoryAndWritebackStage ), if(argConfig.singleCycleShift) { new FullBarrelShifterPlugin @@ -187,7 +191,7 @@ object GenCoreDefault{ ), new BranchPlugin( // If using CFU, use earlyBranch to avoid incorrect CFU execution - earlyBranch = argConfig.cfu, + earlyBranch = argConfig.cfu || !argConfig.memoryAndWritebackStage, catchAddressMisaligned = argConfig.safe ), new CsrPlugin( @@ -255,7 +259,7 @@ object GenCoreDefault{ plugins ++= List( new MulDivIterativePlugin( genMul = true, - genDiv = true, + genDiv = argConfig.hardwareDiv, mulUnrollFactor = 1, divUnrollFactor = 1 ) @@ -278,7 +282,11 @@ object GenCoreDefault{ } // CPU configuration - val cpuConfig = VexRiscvConfig(plugins.toList) + val cpuConfig = VexRiscvConfig( + withMemoryStage = argConfig.memoryAndWritebackStage, + withWriteBackStage = argConfig.memoryAndWritebackStage, + plugins.toList + ) // CPU instantiation val cpu = new VexRiscv(cpuConfig) From d8ec2d84c3160c3a9131beef2db359dce7a2e4a4 Mon Sep 17 00:00:00 2001 From: Joey Bushagour Date: Mon, 2 Aug 2021 12:29:06 -0500 Subject: [PATCH 21/30] Require a memory and writeback stage for the CFU plugin. Signed-off-by: Joey Bushagour --- pythondata_cpu_vexriscv/verilog/Makefile | 4 +- .../verilog/VexRiscv_Fomu.v | 3405 +++++++++------ .../verilog/VexRiscv_FomuCfu.v | 3768 ++++++++++------- .../main/scala/vexriscv/GenCoreDefault.scala | 4 + 4 files changed, 4245 insertions(+), 2936 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index beeba80..6cb3346 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -27,10 +27,10 @@ VexRiscv_MinDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 0 --dCacheSize 0 --mulDiv false --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_MinDebug" VexRiscv_Fomu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --safe false --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --memoryAndWritebackStage false --outputFile VexRiscv_Fomu" + sbt compile "runMain vexriscv.GenCoreDefault --safe false --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --outputFile VexRiscv_Fomu" VexRiscv_FomuCfu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --safe false --cfu true --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --memoryAndWritebackStage false --outputFile VexRiscv_FomuCfu" + sbt compile "runMain vexriscv.GenCoreDefault --safe false --cfu true --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --outputFile VexRiscv_FomuCfu" VexRiscv_Full.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --outputFile VexRiscv_Full" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v index 233ec9c..b9a7259 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 301554ed50130998df7c9b3fa2a900ddbefe2027 +// Git hash : 43e13174d8583db5f4cd45d2b3515bc206a0010a `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -73,18 +73,18 @@ module VexRiscv ( input clk, input reset ); - wire _zz_119; - wire _zz_120; - wire _zz_121; - wire _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; - wire _zz_126; - reg _zz_127; - reg [31:0] _zz_128; - reg [31:0] _zz_129; - reg [31:0] _zz_130; + wire _zz_129; + wire _zz_130; + wire _zz_131; + wire _zz_132; + wire _zz_133; + wire _zz_134; + wire _zz_135; + wire _zz_136; + reg _zz_137; + reg [31:0] _zz_138; + reg [31:0] _zz_139; + reg [31:0] _zz_140; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -97,16 +97,6 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_131; - wire _zz_132; - wire _zz_133; - wire _zz_134; - wire _zz_135; - wire _zz_136; - wire _zz_137; - wire _zz_138; - wire _zz_139; - wire [1:0] _zz_140; wire _zz_141; wire _zz_142; wire _zz_143; @@ -115,287 +105,357 @@ module VexRiscv ( wire _zz_146; wire _zz_147; wire _zz_148; - wire _zz_149; + wire [1:0] _zz_149; wire _zz_150; wire _zz_151; wire _zz_152; - wire [1:0] _zz_153; + wire _zz_153; wire _zz_154; - wire [0:0] _zz_155; - wire [0:0] _zz_156; - wire [0:0] _zz_157; - wire [0:0] _zz_158; - wire [0:0] _zz_159; - wire [0:0] _zz_160; - wire [0:0] _zz_161; - wire [0:0] _zz_162; - wire [0:0] _zz_163; - wire [0:0] _zz_164; - wire [0:0] _zz_165; - wire [0:0] _zz_166; - wire [0:0] _zz_167; - wire [2:0] _zz_168; - wire [2:0] _zz_169; - wire [31:0] _zz_170; + wire _zz_155; + wire _zz_156; + wire _zz_157; + wire _zz_158; + wire _zz_159; + wire _zz_160; + wire _zz_161; + wire _zz_162; + wire _zz_163; + wire _zz_164; + wire _zz_165; + wire [1:0] _zz_166; + wire _zz_167; + wire [0:0] _zz_168; + wire [0:0] _zz_169; + wire [0:0] _zz_170; wire [0:0] _zz_171; - wire [2:0] _zz_172; - wire [4:0] _zz_173; - wire [11:0] _zz_174; - wire [11:0] _zz_175; - wire [31:0] _zz_176; - wire [31:0] _zz_177; - wire [31:0] _zz_178; - wire [31:0] _zz_179; - wire [31:0] _zz_180; - wire [31:0] _zz_181; - wire [31:0] _zz_182; - wire [31:0] _zz_183; - wire [32:0] _zz_184; - wire [19:0] _zz_185; - wire [11:0] _zz_186; - wire [11:0] _zz_187; - wire [1:0] _zz_188; - wire [1:0] _zz_189; - wire [0:0] _zz_190; - wire [5:0] _zz_191; - wire [33:0] _zz_192; - wire [32:0] _zz_193; - wire [33:0] _zz_194; - wire [32:0] _zz_195; - wire [33:0] _zz_196; - wire [32:0] _zz_197; - wire [0:0] _zz_198; + wire [0:0] _zz_172; + wire [0:0] _zz_173; + wire [0:0] _zz_174; + wire [0:0] _zz_175; + wire [0:0] _zz_176; + wire [0:0] _zz_177; + wire [0:0] _zz_178; + wire [0:0] _zz_179; + wire [0:0] _zz_180; + wire [0:0] _zz_181; + wire [0:0] _zz_182; + wire [2:0] _zz_183; + wire [2:0] _zz_184; + wire [31:0] _zz_185; + wire [0:0] _zz_186; + wire [2:0] _zz_187; + wire [4:0] _zz_188; + wire [11:0] _zz_189; + wire [11:0] _zz_190; + wire [31:0] _zz_191; + wire [31:0] _zz_192; + wire [31:0] _zz_193; + wire [31:0] _zz_194; + wire [31:0] _zz_195; + wire [31:0] _zz_196; + wire [31:0] _zz_197; + wire [31:0] _zz_198; wire [32:0] _zz_199; - wire [0:0] _zz_200; - wire [31:0] _zz_201; - wire [0:0] _zz_202; + wire [19:0] _zz_200; + wire [11:0] _zz_201; + wire [11:0] _zz_202; wire [0:0] _zz_203; - wire [0:0] _zz_204; - wire [0:0] _zz_205; - wire [0:0] _zz_206; - wire [0:0] _zz_207; - wire [26:0] _zz_208; - wire _zz_209; - wire _zz_210; - wire [1:0] _zz_211; - wire [31:0] _zz_212; - wire [31:0] _zz_213; + wire [5:0] _zz_204; + wire [33:0] _zz_205; + wire [32:0] _zz_206; + wire [33:0] _zz_207; + wire [32:0] _zz_208; + wire [33:0] _zz_209; + wire [32:0] _zz_210; + wire [0:0] _zz_211; + wire [32:0] _zz_212; + wire [0:0] _zz_213; wire [31:0] _zz_214; - wire _zz_215; + wire [0:0] _zz_215; wire [0:0] _zz_216; - wire [13:0] _zz_217; - wire [31:0] _zz_218; - wire [31:0] _zz_219; - wire [31:0] _zz_220; - wire _zz_221; - wire [0:0] _zz_222; - wire [7:0] _zz_223; - wire [31:0] _zz_224; + wire [0:0] _zz_217; + wire [0:0] _zz_218; + wire [0:0] _zz_219; + wire [0:0] _zz_220; + wire [26:0] _zz_221; + wire _zz_222; + wire _zz_223; + wire [1:0] _zz_224; wire [31:0] _zz_225; wire [31:0] _zz_226; - wire _zz_227; - wire [0:0] _zz_228; - wire [1:0] _zz_229; - wire _zz_230; - wire [0:0] _zz_231; - wire [0:0] _zz_232; - wire _zz_233; - wire [0:0] _zz_234; - wire [23:0] _zz_235; - wire [31:0] _zz_236; - wire _zz_237; - wire _zz_238; - wire [0:0] _zz_239; - wire [0:0] _zz_240; + wire [31:0] _zz_227; + wire _zz_228; + wire [0:0] _zz_229; + wire [13:0] _zz_230; + wire [31:0] _zz_231; + wire [31:0] _zz_232; + wire [31:0] _zz_233; + wire _zz_234; + wire [0:0] _zz_235; + wire [7:0] _zz_236; + wire [31:0] _zz_237; + wire [31:0] _zz_238; + wire [31:0] _zz_239; + wire _zz_240; wire [0:0] _zz_241; - wire [0:0] _zz_242; + wire [1:0] _zz_242; wire _zz_243; wire [0:0] _zz_244; - wire [19:0] _zz_245; - wire [31:0] _zz_246; - wire [31:0] _zz_247; - wire _zz_248; - wire _zz_249; + wire [0:0] _zz_245; + wire _zz_246; + wire [0:0] _zz_247; + wire [23:0] _zz_248; + wire [31:0] _zz_249; wire _zz_250; - wire [2:0] _zz_251; - wire [2:0] _zz_252; - wire _zz_253; + wire _zz_251; + wire [0:0] _zz_252; + wire [0:0] _zz_253; wire [0:0] _zz_254; - wire [16:0] _zz_255; - wire [31:0] _zz_256; - wire [31:0] _zz_257; - wire _zz_258; - wire _zz_259; - wire _zz_260; - wire [0:0] _zz_261; - wire [0:0] _zz_262; + wire [0:0] _zz_255; + wire _zz_256; + wire [0:0] _zz_257; + wire [19:0] _zz_258; + wire [31:0] _zz_259; + wire [31:0] _zz_260; + wire _zz_261; + wire _zz_262; wire _zz_263; - wire [0:0] _zz_264; - wire [0:0] _zz_265; + wire [2:0] _zz_264; + wire [2:0] _zz_265; wire _zz_266; wire [0:0] _zz_267; - wire [13:0] _zz_268; + wire [16:0] _zz_268; wire [31:0] _zz_269; wire [31:0] _zz_270; wire _zz_271; wire _zz_272; - wire [0:0] _zz_273; + wire _zz_273; wire [0:0] _zz_274; wire [0:0] _zz_275; - wire [0:0] _zz_276; - wire _zz_277; + wire _zz_276; + wire [0:0] _zz_277; wire [0:0] _zz_278; - wire [10:0] _zz_279; - wire [31:0] _zz_280; - wire [31:0] _zz_281; - wire _zz_282; - wire _zz_283; + wire _zz_279; + wire [0:0] _zz_280; + wire [13:0] _zz_281; + wire [31:0] _zz_282; + wire [31:0] _zz_283; wire _zz_284; - wire [0:0] _zz_285; + wire _zz_285; wire [0:0] _zz_286; - wire _zz_287; + wire [0:0] _zz_287; wire [0:0] _zz_288; - wire [7:0] _zz_289; - wire [0:0] _zz_290; - wire [3:0] _zz_291; - wire [0:0] _zz_292; - wire [0:0] _zz_293; - wire [1:0] _zz_294; - wire [1:0] _zz_295; + wire [0:0] _zz_289; + wire _zz_290; + wire [0:0] _zz_291; + wire [10:0] _zz_292; + wire [31:0] _zz_293; + wire [31:0] _zz_294; + wire _zz_295; wire _zz_296; - wire [0:0] _zz_297; - wire [3:0] _zz_298; - wire [31:0] _zz_299; - wire [31:0] _zz_300; - wire [31:0] _zz_301; - wire [0:0] _zz_302; - wire [0:0] _zz_303; - wire [31:0] _zz_304; - wire [31:0] _zz_305; - wire [31:0] _zz_306; - wire _zz_307; - wire [0:0] _zz_308; + wire _zz_297; + wire [0:0] _zz_298; + wire [0:0] _zz_299; + wire _zz_300; + wire [0:0] _zz_301; + wire [7:0] _zz_302; + wire [31:0] _zz_303; + wire [0:0] _zz_304; + wire [0:0] _zz_305; + wire [0:0] _zz_306; + wire [4:0] _zz_307; + wire [1:0] _zz_308; wire [1:0] _zz_309; wire _zz_310; - wire [2:0] _zz_311; - wire [2:0] _zz_312; - wire _zz_313; - wire [0:0] _zz_314; - wire [0:0] _zz_315; + wire [0:0] _zz_311; + wire [4:0] _zz_312; + wire [31:0] _zz_313; + wire [31:0] _zz_314; + wire [31:0] _zz_315; wire [31:0] _zz_316; - wire [31:0] _zz_317; - wire [31:0] _zz_318; - wire [31:0] _zz_319; + wire _zz_317; + wire [0:0] _zz_318; + wire [1:0] _zz_319; wire [31:0] _zz_320; wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire _zz_323; - wire [31:0] _zz_324; - wire _zz_325; + wire _zz_322; + wire [0:0] _zz_323; + wire [2:0] _zz_324; + wire [0:0] _zz_325; wire [0:0] _zz_326; - wire [0:0] _zz_327; + wire _zz_327; wire [0:0] _zz_328; - wire [0:0] _zz_329; - wire [1:0] _zz_330; - wire [1:0] _zz_331; - wire [0:0] _zz_332; - wire [0:0] _zz_333; - wire [31:0] _zz_334; + wire [1:0] _zz_329; + wire [31:0] _zz_330; + wire [31:0] _zz_331; + wire [31:0] _zz_332; + wire _zz_333; + wire _zz_334; wire [31:0] _zz_335; wire [31:0] _zz_336; wire [31:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; + wire _zz_338; + wire [0:0] _zz_339; + wire [0:0] _zz_340; + wire [31:0] _zz_341; + wire [31:0] _zz_342; + wire [0:0] _zz_343; + wire [1:0] _zz_344; + wire [1:0] _zz_345; + wire [1:0] _zz_346; + wire _zz_347; + wire _zz_348; + wire [31:0] _zz_349; + wire [31:0] _zz_350; + wire [31:0] _zz_351; + wire [31:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; + wire [31:0] _zz_355; + wire _zz_356; + wire _zz_357; + wire _zz_358; + wire [0:0] _zz_359; + wire [0:0] _zz_360; + wire _zz_361; + wire [31:0] memory_MEMORY_READ_DATA; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; - wire [31:0] decode_SRC2; - wire [31:0] decode_SRC1; wire decode_SRC2_FORCE_ZERO; wire [31:0] decode_RS2; wire [31:0] decode_RS1; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_1; wire `EnvCtrlEnum_defaultEncoding_type _zz_2; wire `EnvCtrlEnum_defaultEncoding_type _zz_3; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; wire decode_IS_CSR; wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_4; - wire `BranchCtrlEnum_defaultEncoding_type _zz_5; - wire `BranchCtrlEnum_defaultEncoding_type _zz_6; + wire `BranchCtrlEnum_defaultEncoding_type _zz_8; + wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `BranchCtrlEnum_defaultEncoding_type _zz_10; wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_7; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_8; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_9; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_10; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_11; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_12; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; wire decode_SRC_LESS_UNSIGNED; wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_13; - wire `AluCtrlEnum_defaultEncoding_type _zz_14; - wire `AluCtrlEnum_defaultEncoding_type _zz_15; + wire `AluCtrlEnum_defaultEncoding_type _zz_17; + wire `AluCtrlEnum_defaultEncoding_type _zz_18; + wire `AluCtrlEnum_defaultEncoding_type _zz_19; wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_20; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_23; + wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire execute_IS_RS1_SIGNED; - wire execute_IS_RS2_SIGNED; wire execute_IS_MUL; + wire execute_IS_RS2_SIGNED; + reg [31:0] _zz_26; + wire memory_IS_MUL; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_27; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_16; - wire [31:0] execute_BRANCH_CALC; - wire execute_BRANCH_DO; + wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; wire [31:0] execute_RS1; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_17; + wire `BranchCtrlEnum_defaultEncoding_type _zz_30; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] _zz_31; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_18; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_32; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_19; - wire [31:0] _zz_20; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire [31:0] _zz_22; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_23; + wire [31:0] _zz_33; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_34; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_35; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_36; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_25; - wire [31:0] _zz_26; - wire _zz_27; - reg _zz_28; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_37; + wire [31:0] _zz_38; + wire _zz_39; + reg _zz_40; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_31; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_32; - wire `AluCtrlEnum_defaultEncoding_type _zz_33; - wire `Src2CtrlEnum_defaultEncoding_type _zz_34; - wire `Src1CtrlEnum_defaultEncoding_type _zz_35; - reg [31:0] _zz_36; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire [31:0] execute_MEMORY_READ_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; + wire `EnvCtrlEnum_defaultEncoding_type _zz_41; + wire `BranchCtrlEnum_defaultEncoding_type _zz_42; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_43; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_defaultEncoding_type _zz_45; + wire `Src2CtrlEnum_defaultEncoding_type _zz_46; + wire `Src1CtrlEnum_defaultEncoding_type _zz_47; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_48; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP2_physicalAddress; + wire memory_MMU_RSP2_isIoAccess; + wire memory_MMU_RSP2_isPaging; + wire memory_MMU_RSP2_allowRead; + wire memory_MMU_RSP2_allowWrite; + wire memory_MMU_RSP2_allowExecute; + wire memory_MMU_RSP2_exception; + wire memory_MMU_RSP2_refilling; + wire memory_MMU_RSP2_bypassTranslation; + wire [31:0] memory_PC; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; wire execute_MMU_FAULT; wire [31:0] execute_MMU_RSP2_physicalAddress; wire execute_MMU_RSP2_isIoAccess; @@ -408,6 +468,7 @@ module VexRiscv ( wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; @@ -416,9 +477,10 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_49; wire [31:0] decode_PC; - wire [31:0] execute_PC; - wire [31:0] execute_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; reg decode_arbitration_haltItself; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; @@ -433,7 +495,7 @@ module VexRiscv ( reg execute_arbitration_haltItself; wire execute_arbitration_haltByOther; reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; + wire execute_arbitration_flushIt; reg execute_arbitration_flushNext; reg execute_arbitration_isValid; wire execute_arbitration_isStuck; @@ -441,6 +503,28 @@ module VexRiscv ( wire execute_arbitration_isFlushed; wire execute_arbitration_isMoving; wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; wire [31:0] lastStageInstruction /* verilator public */ ; wire [31:0] lastStagePc /* verilator public */ ; wire lastStageIsValid /* verilator public */ ; @@ -449,6 +533,8 @@ module VexRiscv ( reg IBusCachedPlugin_incomingInstruction; wire IBusCachedPlugin_pcValids_0; wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; wire IBusCachedPlugin_mmuBus_cmd_0_isValid; wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; @@ -495,6 +581,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_jumpInterface_payload; wire CsrPlugin_exceptionPendings_0; wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; wire externalInterrupt; wire contextSwitching; reg [1:0] CsrPlugin_privilege; @@ -507,10 +595,10 @@ module VexRiscv ( wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_37; - wire [2:0] _zz_38; - wire _zz_39; - wire _zz_40; + wire [2:0] _zz_50; + wire [2:0] _zz_51; + wire _zz_52; + wire _zz_53; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; @@ -547,16 +635,16 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_41; - wire _zz_42; - wire _zz_43; + wire _zz_54; + wire _zz_55; + wire _zz_56; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_44; - wire _zz_45; - reg _zz_46; - wire _zz_47; - reg _zz_48; - reg [31:0] _zz_49; + wire _zz_57; + wire _zz_58; + reg _zz_59; + wire _zz_60; + reg _zz_61; + reg [31:0] _zz_62; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -567,6 +655,8 @@ module VexRiscv ( reg IBusCachedPlugin_injector_nextPcCalc_valids_0; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -574,7 +664,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_50; + wire [31:0] _zz_63; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -591,32 +681,31 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - reg _zz_51; + wire _zz_64; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_52; - reg [3:0] _zz_53; + reg [31:0] _zz_65; + reg [3:0] _zz_66; wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] execute_DBusSimplePlugin_rspShifted; - wire _zz_54; - reg [31:0] _zz_55; - wire _zz_56; - reg [31:0] _zz_57; - reg [31:0] execute_DBusSimplePlugin_rspFormated; - wire [29:0] _zz_58; - wire _zz_59; - wire _zz_60; - wire _zz_61; - wire _zz_62; - wire _zz_63; - wire _zz_64; - wire _zz_65; - wire `Src1CtrlEnum_defaultEncoding_type _zz_66; - wire `Src2CtrlEnum_defaultEncoding_type _zz_67; - wire `AluCtrlEnum_defaultEncoding_type _zz_68; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_69; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_70; - wire `BranchCtrlEnum_defaultEncoding_type _zz_71; - wire `EnvCtrlEnum_defaultEncoding_type _zz_72; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_67; + reg [31:0] _zz_68; + wire _zz_69; + reg [31:0] _zz_70; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [29:0] _zz_71; + wire _zz_72; + wire _zz_73; + wire _zz_74; + wire _zz_75; + wire _zz_76; + wire _zz_77; + wire `Src1CtrlEnum_defaultEncoding_type _zz_78; + wire `Src2CtrlEnum_defaultEncoding_type _zz_79; + wire `AluCtrlEnum_defaultEncoding_type _zz_80; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_81; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_82; + wire `BranchCtrlEnum_defaultEncoding_type _zz_83; + wire `EnvCtrlEnum_defaultEncoding_type _zz_84; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -624,41 +713,40 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_73; + reg _zz_85; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_74; - reg [31:0] _zz_75; - wire _zz_76; - reg [19:0] _zz_77; - wire _zz_78; - reg [19:0] _zz_79; - reg [31:0] _zz_80; + reg [31:0] _zz_86; + reg [31:0] _zz_87; + wire _zz_88; + reg [19:0] _zz_89; + wire _zz_90; + reg [19:0] _zz_91; + reg [31:0] _zz_92; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; wire execute_LightShifterPlugin_isShift; reg [4:0] execute_LightShifterPlugin_amplitudeReg; wire [4:0] execute_LightShifterPlugin_amplitude; - reg [31:0] execute_LightShifterPlugin_shiftReg; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_81; - reg _zz_82; - reg _zz_83; - reg _zz_84; - reg [4:0] _zz_85; + reg [31:0] _zz_93; + reg _zz_94; + reg _zz_95; + reg _zz_96; + reg [4:0] _zz_97; wire execute_BranchPlugin_eq; - wire [2:0] _zz_86; - reg _zz_87; - reg _zz_88; + wire [2:0] _zz_98; + reg _zz_99; + reg _zz_100; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_89; - reg [10:0] _zz_90; - wire _zz_91; - reg [19:0] _zz_92; - wire _zz_93; - reg [18:0] _zz_94; - reg [31:0] _zz_95; + wire _zz_101; + reg [10:0] _zz_102; + wire _zz_103; + reg [19:0] _zz_104; + wire _zz_105; + reg [18:0] _zz_106; + reg [31:0] _zz_107; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -680,25 +768,29 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_96; - wire _zz_97; - wire _zz_98; + wire _zz_108; + wire _zz_109; + wire _zz_110; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_99; - wire _zz_100; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; reg CsrPlugin_pipelineLiberator_done; wire CsrPlugin_interruptJump /* verilator public */ ; @@ -719,29 +811,46 @@ module VexRiscv ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [32:0] execute_MulDivIterativePlugin_rs1; - reg [31:0] execute_MulDivIterativePlugin_rs2; - reg [64:0] execute_MulDivIterativePlugin_accumulator; - reg execute_MulDivIterativePlugin_frontendOk; - reg execute_MulDivIterativePlugin_mul_counter_willIncrement; - reg execute_MulDivIterativePlugin_mul_counter_willClear; - reg [5:0] execute_MulDivIterativePlugin_mul_counter_valueNext; - reg [5:0] execute_MulDivIterativePlugin_mul_counter_value; - wire execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc; - wire execute_MulDivIterativePlugin_mul_counter_willOverflow; - wire _zz_101; - wire _zz_102; - reg [32:0] _zz_103; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_mul_counter_willIncrement; + reg memory_MulDivIterativePlugin_mul_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; + wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + wire _zz_111; + wire _zz_112; + reg [32:0] _zz_113; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_104; - wire [31:0] _zz_105; + reg [31:0] _zz_114; + wire [31:0] _zz_115; reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; reg decode_to_execute_SRC_USE_SUB_LESS; reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; reg decode_to_execute_SRC_LESS_UNSIGNED; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; @@ -749,16 +858,34 @@ module VexRiscv ( reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; reg decode_to_execute_IS_CSR; reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; reg decode_to_execute_IS_RS1_SIGNED; reg decode_to_execute_IS_RS2_SIGNED; reg [31:0] decode_to_execute_RS1; reg [31:0] decode_to_execute_RS2; reg decode_to_execute_SRC2_FORCE_ZERO; - reg [31:0] decode_to_execute_SRC1; - reg [31:0] decode_to_execute_SRC2; reg decode_to_execute_CSR_WRITE_OPCODE; reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; + reg execute_to_memory_MMU_RSP2_isIoAccess; + reg execute_to_memory_MMU_RSP2_isPaging; + reg execute_to_memory_MMU_RSP2_allowRead; + reg execute_to_memory_MMU_RSP2_allowWrite; + reg execute_to_memory_MMU_RSP2_allowExecute; + reg execute_to_memory_MMU_RSP2_exception; + reg execute_to_memory_MMU_RSP2_refilling; + reg execute_to_memory_MMU_RSP2_bypassTranslation; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg execute_to_memory_BRANCH_DO; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_836; reg execute_CsrPlugin_csr_772; @@ -770,18 +897,18 @@ module VexRiscv ( reg execute_CsrPlugin_csr_2944; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_106; - reg [31:0] _zz_107; - reg [31:0] _zz_108; - reg [31:0] _zz_109; - reg [31:0] _zz_110; - reg [31:0] _zz_111; - reg [31:0] _zz_112; - reg [31:0] _zz_113; - reg [31:0] _zz_114; - reg [31:0] _zz_115; - reg [2:0] _zz_116; - reg _zz_117; + reg [31:0] _zz_116; + reg [31:0] _zz_117; + reg [31:0] _zz_118; + reg [31:0] _zz_119; + reg [31:0] _zz_120; + reg [31:0] _zz_121; + reg [31:0] _zz_122; + reg [31:0] _zz_123; + reg [31:0] _zz_124; + reg [31:0] _zz_125; + reg [2:0] _zz_126; + reg _zz_127; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -795,300 +922,332 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_118; + reg [3:0] _zz_128; `ifndef SYNTHESIS - reg [39:0] decode_ENV_CTRL_string; reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_4_string; - reg [31:0] _zz_5_string; - reg [31:0] _zz_6_string; + reg [31:0] _zz_8_string; + reg [31:0] _zz_9_string; + reg [31:0] _zz_10_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_7_string; - reg [71:0] _zz_8_string; - reg [71:0] _zz_9_string; + reg [71:0] _zz_11_string; + reg [71:0] _zz_12_string; + reg [71:0] _zz_13_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_10_string; - reg [39:0] _zz_11_string; - reg [39:0] _zz_12_string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_13_string; - reg [63:0] _zz_14_string; - reg [63:0] _zz_15_string; - reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_14_string; + reg [39:0] _zz_15_string; reg [39:0] _zz_16_string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_17_string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_18_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_17_string; + reg [63:0] _zz_18_string; + reg [63:0] _zz_19_string; reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_20_string; reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; reg [95:0] decode_SRC1_CTRL_string; reg [95:0] _zz_23_string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_24_string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_25_string; + reg [95:0] _zz_24_string; + reg [95:0] _zz_25_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_27_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_28_string; + reg [39:0] writeBack_ENV_CTRL_string; reg [39:0] _zz_29_string; + reg [31:0] execute_BRANCH_CTRL_string; reg [31:0] _zz_30_string; - reg [71:0] _zz_31_string; - reg [39:0] _zz_32_string; - reg [63:0] _zz_33_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_32_string; + reg [23:0] execute_SRC2_CTRL_string; reg [23:0] _zz_34_string; + reg [95:0] execute_SRC1_CTRL_string; reg [95:0] _zz_35_string; - reg [95:0] _zz_66_string; - reg [23:0] _zz_67_string; - reg [63:0] _zz_68_string; - reg [39:0] _zz_69_string; - reg [71:0] _zz_70_string; - reg [31:0] _zz_71_string; - reg [39:0] _zz_72_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_36_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_37_string; + reg [39:0] _zz_41_string; + reg [31:0] _zz_42_string; + reg [71:0] _zz_43_string; + reg [39:0] _zz_44_string; + reg [63:0] _zz_45_string; + reg [23:0] _zz_46_string; + reg [95:0] _zz_47_string; + reg [95:0] _zz_78_string; + reg [23:0] _zz_79_string; + reg [63:0] _zz_80_string; + reg [39:0] _zz_81_string; + reg [71:0] _zz_82_string; + reg [31:0] _zz_83_string; + reg [39:0] _zz_84_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; `endif (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_131 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_132 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_133 = (execute_arbitration_isValid && execute_IS_MUL); - assign _zz_134 = ((_zz_124 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_135 = ((_zz_124 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_136 = (execute_MulDivIterativePlugin_frontendOk && (! execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_137 = ({CsrPlugin_selfException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_138 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_139 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_140 = execute_INSTRUCTION[29 : 28]; - assign _zz_141 = (! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))); - assign _zz_142 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_143 = (1'b1 || (! 1'b1)); - assign _zz_144 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_145 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_146 = (iBus_cmd_valid || (_zz_116 != 3'b000)); - assign _zz_147 = (! execute_arbitration_isStuckByOthers); - assign _zz_148 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_149 = ((_zz_96 && 1'b1) && (! 1'b0)); - assign _zz_150 = ((_zz_97 && 1'b1) && (! 1'b0)); - assign _zz_151 = ((_zz_98 && 1'b1) && (! 1'b0)); - assign _zz_152 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_153 = execute_INSTRUCTION[13 : 12]; - assign _zz_154 = execute_INSTRUCTION[13]; - assign _zz_155 = _zz_58[29 : 29]; - assign _zz_156 = _zz_58[28 : 28]; - assign _zz_157 = _zz_58[27 : 27]; - assign _zz_158 = _zz_58[24 : 24]; - assign _zz_159 = _zz_58[15 : 15]; - assign _zz_160 = _zz_58[11 : 11]; - assign _zz_161 = _zz_58[12 : 12]; - assign _zz_162 = _zz_58[5 : 5]; - assign _zz_163 = _zz_58[3 : 3]; - assign _zz_164 = _zz_58[18 : 18]; - assign _zz_165 = _zz_58[8 : 8]; - assign _zz_166 = _zz_58[4 : 4]; - assign _zz_167 = _zz_58[0 : 0]; - assign _zz_168 = (_zz_37 - 3'b001); - assign _zz_169 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_170 = {29'd0, _zz_169}; - assign _zz_171 = execute_SRC_LESS; - assign _zz_172 = 3'b100; - assign _zz_173 = decode_INSTRUCTION[19 : 15]; - assign _zz_174 = decode_INSTRUCTION[31 : 20]; - assign _zz_175 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; - assign _zz_176 = ($signed(_zz_177) + $signed(_zz_180)); - assign _zz_177 = ($signed(_zz_178) + $signed(_zz_179)); - assign _zz_178 = execute_SRC1; - assign _zz_179 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_180 = (execute_SRC_USE_SUB_LESS ? _zz_181 : _zz_182); - assign _zz_181 = 32'h00000001; - assign _zz_182 = 32'h0; - assign _zz_183 = (_zz_184 >>> 1); - assign _zz_184 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_185 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_186 = execute_INSTRUCTION[31 : 20]; - assign _zz_187 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_188 = (_zz_99 & (~ _zz_189)); - assign _zz_189 = (_zz_99 - 2'b01); - assign _zz_190 = execute_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_191 = {5'd0, _zz_190}; - assign _zz_192 = (_zz_194 + _zz_196); - assign _zz_193 = (execute_MulDivIterativePlugin_rs2[0] ? execute_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_194 = {{1{_zz_193[32]}}, _zz_193}; - assign _zz_195 = _zz_197; - assign _zz_196 = {{1{_zz_195[32]}}, _zz_195}; - assign _zz_197 = (execute_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_198 = _zz_102; - assign _zz_199 = {32'd0, _zz_198}; - assign _zz_200 = _zz_101; - assign _zz_201 = {31'd0, _zz_200}; - assign _zz_202 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_203 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_204 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_205 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_206 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_207 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_208 = (iBus_cmd_payload_address >>> 5); - assign _zz_209 = 1'b1; - assign _zz_210 = 1'b1; - assign _zz_211 = {_zz_40,_zz_39}; - assign _zz_212 = 32'h0000107f; - assign _zz_213 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_214 = 32'h00002073; - assign _zz_215 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_216 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_217 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_218) == 32'h00000003),{(_zz_219 == _zz_220),{_zz_221,{_zz_222,_zz_223}}}}}}; - assign _zz_218 = 32'h0000505f; - assign _zz_219 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_220 = 32'h00000063; - assign _zz_221 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_222 = ((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033); - assign _zz_223 = {((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_224) == 32'h00001013),{(_zz_225 == _zz_226),{_zz_227,{_zz_228,_zz_229}}}}}}; - assign _zz_224 = 32'hfc00705f; - assign _zz_225 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_226 = 32'h00005033; - assign _zz_227 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_228 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_229 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; - assign _zz_230 = ((decode_INSTRUCTION & 32'h02000074) == 32'h02000030); - assign _zz_231 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); - assign _zz_232 = 1'b0; - assign _zz_233 = (((decode_INSTRUCTION & _zz_236) == 32'h10000050) != 1'b0); - assign _zz_234 = ({_zz_237,_zz_238} != 2'b00); - assign _zz_235 = {({_zz_239,_zz_240} != 2'b00),{(_zz_241 != _zz_242),{_zz_243,{_zz_244,_zz_245}}}}; - assign _zz_236 = 32'h10403050; - assign _zz_237 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_238 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_239 = _zz_63; - assign _zz_240 = ((decode_INSTRUCTION & _zz_246) == 32'h00000004); - assign _zz_241 = ((decode_INSTRUCTION & _zz_247) == 32'h00000040); - assign _zz_242 = 1'b0; - assign _zz_243 = ({_zz_248,_zz_249} != 2'b00); - assign _zz_244 = (_zz_250 != 1'b0); - assign _zz_245 = {(_zz_251 != _zz_252),{_zz_253,{_zz_254,_zz_255}}}; - assign _zz_246 = 32'h0000001c; - assign _zz_247 = 32'h00000058; - assign _zz_248 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); - assign _zz_249 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); - assign _zz_250 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); - assign _zz_251 = {(_zz_256 == _zz_257),{_zz_258,_zz_259}}; - assign _zz_252 = 3'b000; - assign _zz_253 = ({_zz_260,{_zz_261,_zz_262}} != 3'b000); - assign _zz_254 = (_zz_263 != 1'b0); - assign _zz_255 = {(_zz_264 != _zz_265),{_zz_266,{_zz_267,_zz_268}}}; - assign _zz_256 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_257 = 32'h40001010; - assign _zz_258 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_259 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_260 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_261 = ((decode_INSTRUCTION & _zz_269) == 32'h00001010); - assign _zz_262 = ((decode_INSTRUCTION & _zz_270) == 32'h00001010); - assign _zz_263 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_264 = _zz_64; - assign _zz_265 = 1'b0; - assign _zz_266 = ({_zz_271,_zz_272} != 2'b00); - assign _zz_267 = ({_zz_273,_zz_274} != 2'b00); - assign _zz_268 = {(_zz_275 != _zz_276),{_zz_277,{_zz_278,_zz_279}}}; - assign _zz_269 = 32'h00003034; - assign _zz_270 = 32'h02003054; - assign _zz_271 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_272 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_273 = ((decode_INSTRUCTION & _zz_280) == 32'h00006000); - assign _zz_274 = ((decode_INSTRUCTION & _zz_281) == 32'h00004000); - assign _zz_275 = _zz_60; - assign _zz_276 = 1'b0; - assign _zz_277 = ({_zz_282,_zz_283} != 2'b00); - assign _zz_278 = (_zz_284 != 1'b0); - assign _zz_279 = {(_zz_285 != _zz_286),{_zz_287,{_zz_288,_zz_289}}}; - assign _zz_280 = 32'h00006004; - assign _zz_281 = 32'h00005004; - assign _zz_282 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); - assign _zz_283 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_284 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz_285 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); - assign _zz_286 = 1'b0; - assign _zz_287 = (_zz_62 != 1'b0); - assign _zz_288 = ({_zz_63,{_zz_290,_zz_291}} != 6'h0); - assign _zz_289 = {({_zz_292,_zz_293} != 2'b00),{(_zz_294 != _zz_295),{_zz_296,{_zz_297,_zz_298}}}}; - assign _zz_290 = ((decode_INSTRUCTION & _zz_299) == 32'h00001010); - assign _zz_291 = {(_zz_300 == _zz_301),{_zz_62,{_zz_302,_zz_303}}}; - assign _zz_292 = _zz_61; - assign _zz_293 = ((decode_INSTRUCTION & _zz_304) == 32'h00000020); - assign _zz_294 = {_zz_61,(_zz_305 == _zz_306)}; - assign _zz_295 = 2'b00; - assign _zz_296 = ({_zz_307,{_zz_308,_zz_309}} != 4'b0000); - assign _zz_297 = (_zz_310 != 1'b0); - assign _zz_298 = {(_zz_311 != _zz_312),{_zz_313,{_zz_314,_zz_315}}}; - assign _zz_299 = 32'h00001010; - assign _zz_300 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_301 = 32'h00002010; - assign _zz_302 = (_zz_316 == _zz_317); - assign _zz_303 = (_zz_318 == _zz_319); - assign _zz_304 = 32'h00000070; - assign _zz_305 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_306 = 32'h0; - assign _zz_307 = ((decode_INSTRUCTION & _zz_320) == 32'h0); - assign _zz_308 = (_zz_321 == _zz_322); - assign _zz_309 = {_zz_60,_zz_323}; - assign _zz_310 = ((decode_INSTRUCTION & _zz_324) == 32'h0); - assign _zz_311 = {_zz_325,{_zz_326,_zz_327}}; - assign _zz_312 = 3'b000; - assign _zz_313 = ({_zz_328,_zz_329} != 2'b00); - assign _zz_314 = (_zz_330 != _zz_331); - assign _zz_315 = (_zz_332 != _zz_333); - assign _zz_316 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_317 = 32'h00000004; - assign _zz_318 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_319 = 32'h0; - assign _zz_320 = 32'h00000044; - assign _zz_321 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_322 = 32'h0; - assign _zz_323 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_324 = 32'h00000058; - assign _zz_325 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_326 = ((decode_INSTRUCTION & _zz_334) == 32'h00002010); - assign _zz_327 = ((decode_INSTRUCTION & _zz_335) == 32'h40000030); - assign _zz_328 = ((decode_INSTRUCTION & _zz_336) == 32'h00000004); - assign _zz_329 = _zz_59; - assign _zz_330 = {(_zz_337 == _zz_338),_zz_59}; - assign _zz_331 = 2'b00; - assign _zz_332 = ((decode_INSTRUCTION & _zz_339) == 32'h00001008); - assign _zz_333 = 1'b0; - assign _zz_334 = 32'h00002014; - assign _zz_335 = 32'h40004034; - assign _zz_336 = 32'h00000014; - assign _zz_337 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_338 = 32'h00000004; - assign _zz_339 = 32'h00001048; + assign _zz_141 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_142 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_143 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_144 = ((_zz_134 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_145 = ((_zz_134 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_146 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_147 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_148 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_149 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_150 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_151 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_152 = (1'b1 || (! 1'b1)); + assign _zz_153 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_154 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_155 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_156 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_157 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_158 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_159 = (iBus_cmd_valid || (_zz_126 != 3'b000)); + assign _zz_160 = (! execute_arbitration_isStuckByOthers); + assign _zz_161 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_162 = ((_zz_108 && 1'b1) && (! 1'b0)); + assign _zz_163 = ((_zz_109 && 1'b1) && (! 1'b0)); + assign _zz_164 = ((_zz_110 && 1'b1) && (! 1'b0)); + assign _zz_165 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_166 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_167 = execute_INSTRUCTION[13]; + assign _zz_168 = _zz_71[29 : 29]; + assign _zz_169 = _zz_71[28 : 28]; + assign _zz_170 = _zz_71[27 : 27]; + assign _zz_171 = _zz_71[24 : 24]; + assign _zz_172 = _zz_71[15 : 15]; + assign _zz_173 = _zz_71[11 : 11]; + assign _zz_174 = _zz_71[10 : 10]; + assign _zz_175 = _zz_71[9 : 9]; + assign _zz_176 = _zz_71[12 : 12]; + assign _zz_177 = _zz_71[5 : 5]; + assign _zz_178 = _zz_71[3 : 3]; + assign _zz_179 = _zz_71[18 : 18]; + assign _zz_180 = _zz_71[8 : 8]; + assign _zz_181 = _zz_71[4 : 4]; + assign _zz_182 = _zz_71[0 : 0]; + assign _zz_183 = (_zz_50 - 3'b001); + assign _zz_184 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_185 = {29'd0, _zz_184}; + assign _zz_186 = execute_SRC_LESS; + assign _zz_187 = 3'b100; + assign _zz_188 = execute_INSTRUCTION[19 : 15]; + assign _zz_189 = execute_INSTRUCTION[31 : 20]; + assign _zz_190 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_191 = ($signed(_zz_192) + $signed(_zz_195)); + assign _zz_192 = ($signed(_zz_193) + $signed(_zz_194)); + assign _zz_193 = execute_SRC1; + assign _zz_194 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_195 = (execute_SRC_USE_SUB_LESS ? _zz_196 : _zz_197); + assign _zz_196 = 32'h00000001; + assign _zz_197 = 32'h0; + assign _zz_198 = (_zz_199 >>> 1); + assign _zz_199 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_200 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_201 = execute_INSTRUCTION[31 : 20]; + assign _zz_202 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_203 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_204 = {5'd0, _zz_203}; + assign _zz_205 = (_zz_207 + _zz_209); + assign _zz_206 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_207 = {{1{_zz_206[32]}}, _zz_206}; + assign _zz_208 = _zz_210; + assign _zz_209 = {{1{_zz_208[32]}}, _zz_208}; + assign _zz_210 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_211 = _zz_112; + assign _zz_212 = {32'd0, _zz_211}; + assign _zz_213 = _zz_111; + assign _zz_214 = {31'd0, _zz_213}; + assign _zz_215 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_216 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_217 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_218 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_219 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_220 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_221 = (iBus_cmd_payload_address >>> 5); + assign _zz_222 = 1'b1; + assign _zz_223 = 1'b1; + assign _zz_224 = {_zz_53,_zz_52}; + assign _zz_225 = 32'h0000107f; + assign _zz_226 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_227 = 32'h00002073; + assign _zz_228 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_229 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_230 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_231) == 32'h00000003),{(_zz_232 == _zz_233),{_zz_234,{_zz_235,_zz_236}}}}}}; + assign _zz_231 = 32'h0000505f; + assign _zz_232 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_233 = 32'h00000063; + assign _zz_234 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_235 = ((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033); + assign _zz_236 = {((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_237) == 32'h00001013),{(_zz_238 == _zz_239),{_zz_240,{_zz_241,_zz_242}}}}}}; + assign _zz_237 = 32'hfc00705f; + assign _zz_238 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_239 = 32'h00005033; + assign _zz_240 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_241 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_242 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_243 = ((decode_INSTRUCTION & 32'h02000074) == 32'h02000030); + assign _zz_244 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz_245 = 1'b0; + assign _zz_246 = (((decode_INSTRUCTION & _zz_249) == 32'h10000050) != 1'b0); + assign _zz_247 = ({_zz_250,_zz_251} != 2'b00); + assign _zz_248 = {({_zz_252,_zz_253} != 2'b00),{(_zz_254 != _zz_255),{_zz_256,{_zz_257,_zz_258}}}}; + assign _zz_249 = 32'h10403050; + assign _zz_250 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_251 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_252 = _zz_75; + assign _zz_253 = ((decode_INSTRUCTION & _zz_259) == 32'h00000004); + assign _zz_254 = ((decode_INSTRUCTION & _zz_260) == 32'h00000040); + assign _zz_255 = 1'b0; + assign _zz_256 = ({_zz_261,_zz_262} != 2'b00); + assign _zz_257 = (_zz_263 != 1'b0); + assign _zz_258 = {(_zz_264 != _zz_265),{_zz_266,{_zz_267,_zz_268}}}; + assign _zz_259 = 32'h0000001c; + assign _zz_260 = 32'h00000058; + assign _zz_261 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_262 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); + assign _zz_263 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); + assign _zz_264 = {(_zz_269 == _zz_270),{_zz_271,_zz_272}}; + assign _zz_265 = 3'b000; + assign _zz_266 = ({_zz_273,{_zz_274,_zz_275}} != 3'b000); + assign _zz_267 = (_zz_276 != 1'b0); + assign _zz_268 = {(_zz_277 != _zz_278),{_zz_279,{_zz_280,_zz_281}}}; + assign _zz_269 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_270 = 32'h40001010; + assign _zz_271 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_272 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_273 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz_274 = ((decode_INSTRUCTION & _zz_282) == 32'h00001010); + assign _zz_275 = ((decode_INSTRUCTION & _zz_283) == 32'h00001010); + assign _zz_276 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_277 = _zz_76; + assign _zz_278 = 1'b0; + assign _zz_279 = ({_zz_284,_zz_285} != 2'b00); + assign _zz_280 = ({_zz_286,_zz_287} != 2'b00); + assign _zz_281 = {(_zz_288 != _zz_289),{_zz_290,{_zz_291,_zz_292}}}; + assign _zz_282 = 32'h00003034; + assign _zz_283 = 32'h02003054; + assign _zz_284 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_285 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_286 = ((decode_INSTRUCTION & _zz_293) == 32'h00006000); + assign _zz_287 = ((decode_INSTRUCTION & _zz_294) == 32'h00004000); + assign _zz_288 = _zz_73; + assign _zz_289 = 1'b0; + assign _zz_290 = ({_zz_295,_zz_296} != 2'b00); + assign _zz_291 = (_zz_297 != 1'b0); + assign _zz_292 = {(_zz_298 != _zz_299),{_zz_300,{_zz_301,_zz_302}}}; + assign _zz_293 = 32'h00006004; + assign _zz_294 = 32'h00005004; + assign _zz_295 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz_296 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz_297 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz_298 = ((decode_INSTRUCTION & _zz_303) == 32'h00000010); + assign _zz_299 = 1'b0; + assign _zz_300 = ({_zz_74,{_zz_304,_zz_305}} != 3'b000); + assign _zz_301 = ({_zz_306,_zz_307} != 6'h0); + assign _zz_302 = {(_zz_308 != _zz_309),{_zz_310,{_zz_311,_zz_312}}}; + assign _zz_303 = 32'h00000010; + assign _zz_304 = ((decode_INSTRUCTION & _zz_313) == 32'h00000010); + assign _zz_305 = ((decode_INSTRUCTION & _zz_314) == 32'h00000020); + assign _zz_306 = _zz_75; + assign _zz_307 = {(_zz_315 == _zz_316),{_zz_317,{_zz_318,_zz_319}}}; + assign _zz_308 = {_zz_74,(_zz_320 == _zz_321)}; + assign _zz_309 = 2'b00; + assign _zz_310 = ({_zz_74,_zz_322} != 2'b00); + assign _zz_311 = ({_zz_323,_zz_324} != 4'b0000); + assign _zz_312 = {(_zz_325 != _zz_326),{_zz_327,{_zz_328,_zz_329}}}; + assign _zz_313 = 32'h00000030; + assign _zz_314 = 32'h02000060; + assign _zz_315 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_316 = 32'h00001010; + assign _zz_317 = ((decode_INSTRUCTION & _zz_330) == 32'h00002010); + assign _zz_318 = (_zz_331 == _zz_332); + assign _zz_319 = {_zz_333,_zz_334}; + assign _zz_320 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_321 = 32'h00000020; + assign _zz_322 = ((decode_INSTRUCTION & _zz_335) == 32'h0); + assign _zz_323 = (_zz_336 == _zz_337); + assign _zz_324 = {_zz_338,{_zz_339,_zz_340}}; + assign _zz_325 = (_zz_341 == _zz_342); + assign _zz_326 = 1'b0; + assign _zz_327 = ({_zz_343,_zz_344} != 3'b000); + assign _zz_328 = (_zz_345 != _zz_346); + assign _zz_329 = {_zz_347,_zz_348}; + assign _zz_330 = 32'h00002010; + assign _zz_331 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_332 = 32'h00000010; + assign _zz_333 = ((decode_INSTRUCTION & _zz_349) == 32'h00000004); + assign _zz_334 = ((decode_INSTRUCTION & _zz_350) == 32'h0); + assign _zz_335 = 32'h00000020; + assign _zz_336 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_337 = 32'h0; + assign _zz_338 = ((decode_INSTRUCTION & _zz_351) == 32'h0); + assign _zz_339 = _zz_73; + assign _zz_340 = (_zz_352 == _zz_353); + assign _zz_341 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_342 = 32'h0; + assign _zz_343 = (_zz_354 == _zz_355); + assign _zz_344 = {_zz_356,_zz_357}; + assign _zz_345 = {_zz_358,_zz_72}; + assign _zz_346 = 2'b00; + assign _zz_347 = ({_zz_359,_zz_360} != 2'b00); + assign _zz_348 = (_zz_361 != 1'b0); + assign _zz_349 = 32'h0000000c; + assign _zz_350 = 32'h00000028; + assign _zz_351 = 32'h00000018; + assign _zz_352 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_353 = 32'h00001000; + assign _zz_354 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_355 = 32'h00000040; + assign _zz_356 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_357 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz_358 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_359 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_360 = _zz_72; + assign _zz_361 = ((decode_INSTRUCTION & 32'h00001048) == 32'h00001008); always @ (posedge clk) begin - if(_zz_209) begin - _zz_128 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_222) begin + _zz_138 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_210) begin - _zz_129 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_223) begin + _zz_139 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_28) begin + if(_zz_40) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_119 ), //i - .io_cpu_prefetch_isValid (_zz_120 ), //i + .io_flush (_zz_129 ), //i + .io_cpu_prefetch_isValid (_zz_130 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_121 ), //i - .io_cpu_fetch_isStuck (_zz_122 ), //i - .io_cpu_fetch_isRemoved (_zz_123 ), //i + .io_cpu_fetch_isValid (_zz_131 ), //i + .io_cpu_fetch_isStuck (_zz_132 ), //i + .io_cpu_fetch_isRemoved (_zz_133 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1101,8 +1260,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_124 ), //i - .io_cpu_decode_isStuck (_zz_125 ), //i + .io_cpu_decode_isValid (_zz_134 ), //i + .io_cpu_decode_isStuck (_zz_135 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1110,8 +1269,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_126 ), //i - .io_cpu_fill_valid (_zz_127 ), //i + .io_cpu_decode_isUser (_zz_136 ), //i + .io_cpu_fill_valid (_zz_137 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1124,28 +1283,20 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_211) + case(_zz_224) 2'b00 : begin - _zz_130 = DBusSimplePlugin_redoBranch_payload; + _zz_140 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_130 = CsrPlugin_jumpInterface_payload; + _zz_140 = DBusSimplePlugin_redoBranch_payload; end default : begin - _zz_130 = BranchPlugin_jumpInterface_payload; + _zz_140 = BranchPlugin_jumpInterface_payload; end endcase end `ifndef SYNTHESIS - always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; - endcase - end always @(*) begin case(_zz_1) `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; @@ -1171,191 +1322,179 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; - default : decode_BRANCH_CTRL_string = "????"; + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `BranchCtrlEnum_defaultEncoding_INC : _zz_4_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_4_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_4_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_4_string = "JALR"; - default : _zz_4_string = "????"; + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_5) - `BranchCtrlEnum_defaultEncoding_INC : _zz_5_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_5_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_5_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_5_string = "JALR"; - default : _zz_5_string = "????"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; endcase end always @(*) begin case(_zz_6) - `BranchCtrlEnum_defaultEncoding_INC : _zz_6_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_6_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_6_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_6_string = "JALR"; - default : _zz_6_string = "????"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; endcase end always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_7_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_7_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_7_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_7_string = "SRA_1 "; - default : _zz_7_string = "?????????"; + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(_zz_8) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_8_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_8_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_8_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_8_string = "SRA_1 "; - default : _zz_8_string = "?????????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; + default : _zz_8_string = "????"; endcase end always @(*) begin case(_zz_9) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_9_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_9_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_9_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_9_string = "SRA_1 "; - default : _zz_9_string = "?????????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; + default : _zz_9_string = "????"; endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(_zz_10) + `BranchCtrlEnum_defaultEncoding_INC : _zz_10_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_10_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_10_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_10_string = "JALR"; + default : _zz_10_string = "????"; endcase end always @(*) begin - case(_zz_10) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_10_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_10_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_10_string = "AND_1"; - default : _zz_10_string = "?????"; + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(_zz_11) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_11_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_11_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_11_string = "AND_1"; - default : _zz_11_string = "?????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; + default : _zz_11_string = "?????????"; endcase end always @(*) begin case(_zz_12) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_12_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_12_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_12_string = "AND_1"; - default : _zz_12_string = "?????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; + default : _zz_12_string = "?????????"; endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_13_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_13_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_13_string = "BITWISE "; - default : _zz_13_string = "????????"; + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(_zz_14) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_14_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_14_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_14_string = "BITWISE "; - default : _zz_14_string = "????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; + default : _zz_14_string = "?????"; endcase end always @(*) begin case(_zz_15) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_15_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_15_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_15_string = "BITWISE "; - default : _zz_15_string = "????????"; - endcase - end - always @(*) begin - case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; - default : execute_ENV_CTRL_string = "?????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; + default : _zz_15_string = "?????"; endcase end always @(*) begin case(_zz_16) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_16_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_16_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_16_string = "ECALL"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; default : _zz_16_string = "?????"; endcase end always @(*) begin - case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; - default : execute_BRANCH_CTRL_string = "????"; + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(_zz_17) - `BranchCtrlEnum_defaultEncoding_INC : _zz_17_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_17_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_17_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_17_string = "JALR"; - default : _zz_17_string = "????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17_string = "BITWISE "; + default : _zz_17_string = "????????"; endcase end always @(*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; - default : execute_SHIFT_CTRL_string = "?????????"; + case(_zz_18) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18_string = "BITWISE "; + default : _zz_18_string = "????????"; endcase end always @(*) begin - case(_zz_18) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_18_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_18_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_18_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_18_string = "SRA_1 "; - default : _zz_18_string = "?????????"; + case(_zz_19) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19_string = "BITWISE "; + default : _zz_19_string = "????????"; endcase end always @(*) begin @@ -1367,6 +1506,15 @@ module VexRiscv ( default : decode_SRC2_CTRL_string = "???"; endcase end + always @(*) begin + case(_zz_20) + `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; + default : _zz_20_string = "???"; + endcase + end always @(*) begin case(_zz_21) `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; @@ -1376,6 +1524,15 @@ module VexRiscv ( default : _zz_21_string = "???"; endcase end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end always @(*) begin case(decode_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; @@ -1395,35 +1552,61 @@ module VexRiscv ( endcase end always @(*) begin - case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; - default : execute_ALU_CTRL_string = "????????"; + case(_zz_24) + `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; + default : _zz_24_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_25) + `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; + default : _zz_25_string = "????????????"; endcase end always @(*) begin - case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; - default : execute_ALU_BITWISE_CTRL_string = "?????"; + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_25) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_25_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_25_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_25_string = "AND_1"; - default : _zz_25_string = "?????"; + case(_zz_27) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; + default : _zz_27_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_28) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; + default : _zz_28_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin @@ -1434,6 +1617,15 @@ module VexRiscv ( default : _zz_29_string = "?????"; endcase end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end always @(*) begin case(_zz_30) `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; @@ -1444,28 +1636,30 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_31) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_31_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_31_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_31_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_31_string = "SRA_1 "; - default : _zz_31_string = "?????????"; + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(_zz_32) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_32_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_32_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_32_string = "AND_1"; - default : _zz_32_string = "?????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_32_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_32_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_32_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_32_string = "SRA_1 "; + default : _zz_32_string = "?????????"; endcase end always @(*) begin - case(_zz_33) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_33_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_33_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_33_string = "BITWISE "; - default : _zz_33_string = "????????"; + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin @@ -1477,6 +1671,15 @@ module VexRiscv ( default : _zz_34_string = "???"; endcase end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end always @(*) begin case(_zz_35) `Src1CtrlEnum_defaultEncoding_RS : _zz_35_string = "RS "; @@ -1487,63 +1690,173 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_66) - `Src1CtrlEnum_defaultEncoding_RS : _zz_66_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_66_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_66_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_66_string = "URS1 "; - default : _zz_66_string = "????????????"; + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_36) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_36_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_36_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_36_string = "BITWISE "; + default : _zz_36_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_37) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_37_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_37_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_37_string = "AND_1"; + default : _zz_37_string = "?????"; + endcase + end + always @(*) begin + case(_zz_41) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_41_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_41_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_41_string = "ECALL"; + default : _zz_41_string = "?????"; + endcase + end + always @(*) begin + case(_zz_42) + `BranchCtrlEnum_defaultEncoding_INC : _zz_42_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_42_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_42_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_42_string = "JALR"; + default : _zz_42_string = "????"; + endcase + end + always @(*) begin + case(_zz_43) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_43_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_43_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_43_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_43_string = "SRA_1 "; + default : _zz_43_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_44) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_44_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_44_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_44_string = "AND_1"; + default : _zz_44_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; + default : _zz_45_string = "????????"; + endcase + end + always @(*) begin + case(_zz_46) + `Src2CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_46_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_46_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_46_string = "PC "; + default : _zz_46_string = "???"; + endcase + end + always @(*) begin + case(_zz_47) + `Src1CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_47_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_47_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_47_string = "URS1 "; + default : _zz_47_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_78) + `Src1CtrlEnum_defaultEncoding_RS : _zz_78_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_78_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_78_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_78_string = "URS1 "; + default : _zz_78_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_79) + `Src2CtrlEnum_defaultEncoding_RS : _zz_79_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_79_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_79_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_79_string = "PC "; + default : _zz_79_string = "???"; + endcase + end + always @(*) begin + case(_zz_80) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_80_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_80_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_80_string = "BITWISE "; + default : _zz_80_string = "????????"; endcase end always @(*) begin - case(_zz_67) - `Src2CtrlEnum_defaultEncoding_RS : _zz_67_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_67_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_67_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_67_string = "PC "; - default : _zz_67_string = "???"; + case(_zz_81) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_81_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_81_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_81_string = "AND_1"; + default : _zz_81_string = "?????"; endcase end always @(*) begin - case(_zz_68) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_68_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_68_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_68_string = "BITWISE "; - default : _zz_68_string = "????????"; + case(_zz_82) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_82_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_82_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_82_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_82_string = "SRA_1 "; + default : _zz_82_string = "?????????"; endcase end always @(*) begin - case(_zz_69) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_69_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_69_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_69_string = "AND_1"; - default : _zz_69_string = "?????"; + case(_zz_83) + `BranchCtrlEnum_defaultEncoding_INC : _zz_83_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_83_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_83_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_83_string = "JALR"; + default : _zz_83_string = "????"; endcase end always @(*) begin - case(_zz_70) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_70_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_70_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_70_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_70_string = "SRA_1 "; - default : _zz_70_string = "?????????"; + case(_zz_84) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_84_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_84_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_84_string = "ECALL"; + default : _zz_84_string = "?????"; endcase end always @(*) begin - case(_zz_71) - `BranchCtrlEnum_defaultEncoding_INC : _zz_71_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_71_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_71_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_71_string = "JALR"; - default : _zz_71_string = "????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_72) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_72_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_72_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_72_string = "ECALL"; - default : _zz_72_string = "?????"; + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin @@ -1588,101 +1901,163 @@ module VexRiscv ( default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end `endif + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = _zz_100; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_86; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); - assign decode_SRC2 = _zz_80; - assign decode_SRC1 = _zz_75; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign decode_IS_RS2_SIGNED = _zz_155[0]; - assign decode_IS_RS1_SIGNED = _zz_156[0]; - assign decode_IS_MUL = _zz_157[0]; - assign decode_ENV_CTRL = _zz_1; - assign _zz_2 = _zz_3; - assign decode_IS_CSR = _zz_158[0]; - assign decode_BRANCH_CTRL = _zz_4; - assign _zz_5 = _zz_6; - assign decode_SHIFT_CTRL = _zz_7; - assign _zz_8 = _zz_9; - assign decode_ALU_BITWISE_CTRL = _zz_10; - assign _zz_11 = _zz_12; - assign decode_SRC_LESS_UNSIGNED = _zz_159[0]; - assign decode_ALU_CTRL = _zz_13; - assign _zz_14 = _zz_15; - assign decode_MEMORY_STORE = _zz_160[0]; + assign decode_IS_RS2_SIGNED = _zz_168[0]; + assign decode_IS_RS1_SIGNED = _zz_169[0]; + assign decode_IS_MUL = _zz_170[0]; + assign _zz_1 = _zz_2; + assign _zz_3 = _zz_4; + assign decode_ENV_CTRL = _zz_5; + assign _zz_6 = _zz_7; + assign decode_IS_CSR = _zz_171[0]; + assign decode_BRANCH_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_SHIFT_CTRL = _zz_11; + assign _zz_12 = _zz_13; + assign decode_ALU_BITWISE_CTRL = _zz_14; + assign _zz_15 = _zz_16; + assign decode_SRC_LESS_UNSIGNED = _zz_172[0]; + assign decode_ALU_CTRL = _zz_17; + assign _zz_18 = _zz_19; + assign decode_MEMORY_STORE = _zz_173[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_174[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_175[0]; + assign decode_SRC2_CTRL = _zz_20; + assign _zz_21 = _zz_22; + assign decode_SRC1_CTRL = _zz_23; + assign _zz_24 = _zz_25; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + always @ (*) begin + _zz_26 = memory_REGFILE_WRITE_DATA; + if(_zz_141)begin + _zz_26 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + end + end + + assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign execute_ENV_CTRL = _zz_16; - assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_88; + assign memory_ENV_CTRL = _zz_27; + assign execute_ENV_CTRL = _zz_28; + assign writeBack_ENV_CTRL = _zz_29; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_17; - assign decode_RS2_USE = _zz_161[0]; - assign decode_RS1_USE = _zz_162[0]; + assign execute_BRANCH_CTRL = _zz_30; + assign decode_RS2_USE = _zz_176[0]; + assign decode_RS1_USE = _zz_177[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign execute_SHIFT_CTRL = _zz_18; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_31 = execute_REGFILE_WRITE_DATA; + if(_zz_142)begin + _zz_31 = _zz_93; + end + if(_zz_143)begin + _zz_31 = execute_CsrPlugin_readData; + end + end + + assign execute_SHIFT_CTRL = _zz_32; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_19 = decode_PC; - assign _zz_20 = decode_RS2; - assign decode_SRC2_CTRL = _zz_21; - assign _zz_22 = decode_RS1; - assign decode_SRC1_CTRL = _zz_23; - assign decode_SRC_USE_SUB_LESS = _zz_163[0]; - assign decode_SRC_ADD_ZERO = _zz_164[0]; + assign _zz_33 = execute_PC; + assign execute_SRC2_CTRL = _zz_34; + assign execute_SRC1_CTRL = _zz_35; + assign decode_SRC_USE_SUB_LESS = _zz_178[0]; + assign decode_SRC_ADD_ZERO = _zz_179[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_24; - assign execute_SRC2 = decode_to_execute_SRC2; - assign execute_SRC1 = decode_to_execute_SRC1; - assign execute_ALU_BITWISE_CTRL = _zz_25; - assign _zz_26 = execute_INSTRUCTION; - assign _zz_27 = execute_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_28 = 1'b0; + assign execute_ALU_CTRL = _zz_36; + assign execute_SRC2 = _zz_92; + assign execute_SRC1 = _zz_87; + assign execute_ALU_BITWISE_CTRL = _zz_37; + assign _zz_38 = writeBack_INSTRUCTION; + assign _zz_39 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_40 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_28 = 1'b1; + _zz_40 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_165[0]; + decode_REGFILE_WRITE_VALID = _zz_180[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_212) == 32'h00001073),{(_zz_213 == _zz_214),{_zz_215,{_zz_216,_zz_217}}}}}}} != 21'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_225) == 32'h00001073),{(_zz_226 == _zz_227),{_zz_228,{_zz_229,_zz_230}}}}}}} != 21'h0); + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin - _zz_36 = execute_REGFILE_WRITE_DATA; - if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin - _zz_36 = execute_DBusSimplePlugin_rspFormated; - end - if(_zz_131)begin - _zz_36 = _zz_81; - end - if(_zz_132)begin - _zz_36 = execute_CsrPlugin_readData; - end - if(_zz_133)begin - _zz_36 = ((execute_INSTRUCTION[13 : 12] == 2'b00) ? execute_MulDivIterativePlugin_accumulator[31 : 0] : execute_MulDivIterativePlugin_accumulator[63 : 32]); + _zz_48 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_48 = writeBack_DBusSimplePlugin_rspFormated; end end - assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; - assign execute_MEMORY_READ_DATA = dBus_rsp_data; - assign execute_REGFILE_WRITE_DATA = _zz_74; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; + assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; + assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; + assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; + assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; + assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; + assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; + assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; + assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; + assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; + assign memory_PC = execute_to_memory_PC; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; @@ -1695,29 +2070,40 @@ module VexRiscv ( assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = 1'b0; - assign decode_MEMORY_ENABLE = _zz_166[0]; - assign decode_FLUSH_ALL = _zz_167[0]; + assign decode_MEMORY_ENABLE = _zz_181[0]; + assign decode_FLUSH_ALL = _zz_182[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_134)begin + if(_zz_144)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_135)begin + if(_zz_145)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_49 = memory_FORMAL_PC_NEXT; + if(DBusSimplePlugin_redoBranch_valid)begin + _zz_49 = DBusSimplePlugin_redoBranch_payload; + end + if(BranchPlugin_jumpInterface_valid)begin + _zz_49 = BranchPlugin_jumpInterface_payload; + end + end + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; - assign execute_PC = decode_to_execute_PC; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin decode_arbitration_haltItself = 1'b0; if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin @@ -1727,13 +2113,13 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_82 || _zz_83)))begin + if((decode_arbitration_isValid && (_zz_94 || _zz_95)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin decode_arbitration_haltByOther = 1'b1; end - if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != 1'b0))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end @@ -1758,36 +2144,25 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_51)))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)))begin execute_arbitration_haltItself = 1'b1; end - if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && ((! dBus_rsp_ready) || (! _zz_51))))begin - execute_arbitration_haltItself = 1'b1; - end - if(_zz_131)begin + if(_zz_142)begin if((! execute_LightShifterPlugin_done))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_132)begin + if(_zz_143)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_133)begin - if(((! execute_MulDivIterativePlugin_frontendOk) || (! execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin - execute_arbitration_haltItself = 1'b1; - end - if(_zz_136)begin - execute_arbitration_haltItself = 1'b1; - end - end end assign execute_arbitration_haltByOther = 1'b0; always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_137)begin + if(CsrPlugin_selfException_valid)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -1795,45 +2170,93 @@ module VexRiscv ( end end + assign execute_arbitration_flushIt = 1'b0; + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid)begin + execute_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_141)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_146)begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(DBusSimplePlugin_memoryExceptionPort_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + always @ (*) begin - execute_arbitration_flushIt = 1'b0; + memory_arbitration_flushIt = 1'b0; if(DBusSimplePlugin_redoBranch_valid)begin - execute_arbitration_flushIt = 1'b1; + memory_arbitration_flushIt = 1'b1; end end always @ (*) begin - execute_arbitration_flushNext = 1'b0; + memory_arbitration_flushNext = 1'b0; if(DBusSimplePlugin_redoBranch_valid)begin - execute_arbitration_flushNext = 1'b1; + memory_arbitration_flushNext = 1'b1; end if(BranchPlugin_jumpInterface_valid)begin - execute_arbitration_flushNext = 1'b1; + memory_arbitration_flushNext = 1'b1; end - if(_zz_137)begin - execute_arbitration_flushNext = 1'b1; + if(DBusSimplePlugin_memoryExceptionPort_valid)begin + memory_arbitration_flushNext = 1'b1; end - if(_zz_138)begin - execute_arbitration_flushNext = 1'b1; + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; end - if(_zz_139)begin - execute_arbitration_flushNext = 1'b1; + end + + assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(_zz_147)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_148)begin + writeBack_arbitration_flushNext = 1'b1; end end - assign lastStageInstruction = execute_INSTRUCTION; - assign lastStagePc = execute_PC; - assign lastStageIsValid = execute_arbitration_isValid; - assign lastStageIsFiring = execute_arbitration_isFiring; + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode} != 2'b00))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_138)begin + if(_zz_147)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_139)begin + if(_zz_148)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -1849,21 +2272,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_138)begin + if(_zz_147)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_139)begin + if(_zz_148)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_138)begin + if(_zz_147)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_139)begin - case(_zz_140) + if(_zz_148)begin + case(_zz_149) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -1876,13 +2299,13 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; - assign IBusCachedPlugin_externalFlush = ({execute_arbitration_flushNext,decode_arbitration_flushNext} != 2'b00); + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); - assign _zz_37 = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}}; - assign _zz_38 = (_zz_37 & (~ _zz_168)); - assign _zz_39 = _zz_38[1]; - assign _zz_40 = _zz_38[2]; - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_130; + assign _zz_50 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; + assign _zz_51 = (_zz_50 & (~ _zz_183)); + assign _zz_52 = _zz_51[1]; + assign _zz_53 = _zz_51[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_140; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -1902,7 +2325,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_170); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_185); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -1942,9 +2365,9 @@ module VexRiscv ( end end - assign _zz_41 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_41); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_41); + assign _zz_54 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_54); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_54); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; @@ -1953,9 +2376,9 @@ module VexRiscv ( end end - assign _zz_42 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_42); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_42); + assign _zz_55 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_55); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_55); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; @@ -1964,22 +2387,22 @@ module VexRiscv ( end end - assign _zz_43 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_43); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_43); + assign _zz_56 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_56); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_56); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_44; - assign _zz_44 = ((1'b0 && (! _zz_45)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_45 = _zz_46; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_45; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_57; + assign _zz_57 = ((1'b0 && (! _zz_58)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_58 = _zz_59; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_58; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_47)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_47 = _zz_48; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_47; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_49; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_60)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_60 = _zz_61; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_60; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_62; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -1989,6 +2412,8 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; @@ -1999,33 +2424,33 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_120 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_121 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_122 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_121; + assign _zz_130 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_131 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_132 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_131; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_124 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_125 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_126 = (CsrPlugin_privilege == 2'b00); + assign _zz_134 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_135 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_136 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_135)begin + if(_zz_145)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_134)begin + if(_zz_144)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_127 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_134)begin - _zz_127 = 1'b1; + _zz_137 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_144)begin + _zz_137 = 1'b1; end end @@ -2033,7 +2458,8 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_119 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_129 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_64 = 1'b0; always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin @@ -2044,39 +2470,39 @@ module VexRiscv ( end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_51)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_52 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_65 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_52 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_65 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_52 = execute_RS2[31 : 0]; + _zz_65 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_52; + assign dBus_cmd_payload_data = _zz_65; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_53 = 4'b0001; + _zz_66 = 4'b0001; end 2'b01 : begin - _zz_53 = 4'b0011; + _zz_66 = 4'b0011; end default : begin - _zz_53 = 4'b1111; + _zz_66 = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_53 <<< dBus_cmd_payload_address[1 : 0]); + assign execute_DBusSimplePlugin_formalMask = (_zz_66 <<< dBus_cmd_payload_address[1 : 0]); assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; @@ -2085,116 +2511,116 @@ module VexRiscv ( assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(execute_MMU_RSP2_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end else begin - if(execute_MMU_FAULT)begin + if(memory_MMU_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_141)begin + if(_zz_150)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(! execute_MMU_RSP2_refilling) begin - if(execute_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (execute_MEMORY_STORE ? 4'b1111 : 4'b1101); + if(! memory_MMU_RSP2_refilling) begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); end end end - assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA; + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; always @ (*) begin DBusSimplePlugin_redoBranch_valid = 1'b0; - if(execute_MMU_RSP2_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_141)begin + if(_zz_150)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end - assign DBusSimplePlugin_redoBranch_payload = execute_PC; + assign DBusSimplePlugin_redoBranch_payload = memory_PC; always @ (*) begin - execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; - case(execute_MEMORY_ADDRESS_LOW) + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8]; + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; end 2'b10 : begin - execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16]; + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; end 2'b11 : begin - execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24]; + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; end default : begin end endcase end - assign _zz_54 = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); - always @ (*) begin - _zz_55[31] = _zz_54; - _zz_55[30] = _zz_54; - _zz_55[29] = _zz_54; - _zz_55[28] = _zz_54; - _zz_55[27] = _zz_54; - _zz_55[26] = _zz_54; - _zz_55[25] = _zz_54; - _zz_55[24] = _zz_54; - _zz_55[23] = _zz_54; - _zz_55[22] = _zz_54; - _zz_55[21] = _zz_54; - _zz_55[20] = _zz_54; - _zz_55[19] = _zz_54; - _zz_55[18] = _zz_54; - _zz_55[17] = _zz_54; - _zz_55[16] = _zz_54; - _zz_55[15] = _zz_54; - _zz_55[14] = _zz_54; - _zz_55[13] = _zz_54; - _zz_55[12] = _zz_54; - _zz_55[11] = _zz_54; - _zz_55[10] = _zz_54; - _zz_55[9] = _zz_54; - _zz_55[8] = _zz_54; - _zz_55[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_56 = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); - always @ (*) begin - _zz_57[31] = _zz_56; - _zz_57[30] = _zz_56; - _zz_57[29] = _zz_56; - _zz_57[28] = _zz_56; - _zz_57[27] = _zz_56; - _zz_57[26] = _zz_56; - _zz_57[25] = _zz_56; - _zz_57[24] = _zz_56; - _zz_57[23] = _zz_56; - _zz_57[22] = _zz_56; - _zz_57[21] = _zz_56; - _zz_57[20] = _zz_56; - _zz_57[19] = _zz_56; - _zz_57[18] = _zz_56; - _zz_57[17] = _zz_56; - _zz_57[16] = _zz_56; - _zz_57[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_153) + assign _zz_67 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_68[31] = _zz_67; + _zz_68[30] = _zz_67; + _zz_68[29] = _zz_67; + _zz_68[28] = _zz_67; + _zz_68[27] = _zz_67; + _zz_68[26] = _zz_67; + _zz_68[25] = _zz_67; + _zz_68[24] = _zz_67; + _zz_68[23] = _zz_67; + _zz_68[22] = _zz_67; + _zz_68[21] = _zz_67; + _zz_68[20] = _zz_67; + _zz_68[19] = _zz_67; + _zz_68[18] = _zz_67; + _zz_68[17] = _zz_67; + _zz_68[16] = _zz_67; + _zz_68[15] = _zz_67; + _zz_68[14] = _zz_67; + _zz_68[13] = _zz_67; + _zz_68[12] = _zz_67; + _zz_68[11] = _zz_67; + _zz_68[10] = _zz_67; + _zz_68[9] = _zz_67; + _zz_68[8] = _zz_67; + _zz_68[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_69 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_70[31] = _zz_69; + _zz_70[30] = _zz_69; + _zz_70[29] = _zz_69; + _zz_70[28] = _zz_69; + _zz_70[27] = _zz_69; + _zz_70[26] = _zz_69; + _zz_70[25] = _zz_69; + _zz_70[24] = _zz_69; + _zz_70[23] = _zz_69; + _zz_70[22] = _zz_69; + _zz_70[21] = _zz_69; + _zz_70[20] = _zz_69; + _zz_70[19] = _zz_69; + _zz_70[18] = _zz_69; + _zz_70[17] = _zz_69; + _zz_70[16] = _zz_69; + _zz_70[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_166) 2'b00 : begin - execute_DBusSimplePlugin_rspFormated = _zz_55; + writeBack_DBusSimplePlugin_rspFormated = _zz_68; end 2'b01 : begin - execute_DBusSimplePlugin_rspFormated = _zz_57; + writeBack_DBusSimplePlugin_rspFormated = _zz_70; end default : begin - execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; end endcase end @@ -2217,52 +2643,51 @@ module VexRiscv ( assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_59 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_60 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_61 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_62 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); - assign _zz_63 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_64 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_65 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00001000); - assign _zz_58 = {(_zz_65 != 1'b0),{({_zz_65,_zz_64} != 2'b00),{(_zz_230 != 1'b0),{(_zz_231 != _zz_232),{_zz_233,{_zz_234,_zz_235}}}}}}; - assign _zz_66 = _zz_58[2 : 1]; - assign _zz_35 = _zz_66; - assign _zz_67 = _zz_58[7 : 6]; - assign _zz_34 = _zz_67; - assign _zz_68 = _zz_58[14 : 13]; - assign _zz_33 = _zz_68; - assign _zz_69 = _zz_58[17 : 16]; - assign _zz_32 = _zz_69; - assign _zz_70 = _zz_58[20 : 19]; - assign _zz_31 = _zz_70; - assign _zz_71 = _zz_58[23 : 22]; - assign _zz_30 = _zz_71; - assign _zz_72 = _zz_58[26 : 25]; - assign _zz_29 = _zz_72; + assign _zz_72 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_73 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_74 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_75 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_76 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_77 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00001000); + assign _zz_71 = {(_zz_77 != 1'b0),{({_zz_77,_zz_76} != 2'b00),{(_zz_243 != 1'b0),{(_zz_244 != _zz_245),{_zz_246,{_zz_247,_zz_248}}}}}}; + assign _zz_78 = _zz_71[2 : 1]; + assign _zz_47 = _zz_78; + assign _zz_79 = _zz_71[7 : 6]; + assign _zz_46 = _zz_79; + assign _zz_80 = _zz_71[14 : 13]; + assign _zz_45 = _zz_80; + assign _zz_81 = _zz_71[17 : 16]; + assign _zz_44 = _zz_81; + assign _zz_82 = _zz_71[20 : 19]; + assign _zz_43 = _zz_82; + assign _zz_83 = _zz_71[23 : 22]; + assign _zz_42 = _zz_83; + assign _zz_84 = _zz_71[26 : 25]; + assign _zz_41 = _zz_84; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_128; - assign decode_RegFilePlugin_rs2Data = _zz_129; + assign decode_RegFilePlugin_rs1Data = _zz_138; + assign decode_RegFilePlugin_rs2Data = _zz_139; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_27 && execute_arbitration_isFiring); - if(_zz_73)begin + lastStageRegFileWrite_valid = (_zz_39 && writeBack_arbitration_isFiring); + if(_zz_85)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_26[11 : 7]; - if(_zz_73)begin + lastStageRegFileWrite_payload_address = _zz_38[11 : 7]; + if(_zz_85)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_36; - if(_zz_73)begin + lastStageRegFileWrite_payload_data = _zz_48; + if(_zz_85)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -2284,101 +2709,101 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_74 = execute_IntAluPlugin_bitwise; + _zz_86 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_74 = {31'd0, _zz_171}; + _zz_86 = {31'd0, _zz_186}; end default : begin - _zz_74 = execute_SRC_ADD_SUB; + _zz_86 = execute_SRC_ADD_SUB; end endcase end always @ (*) begin - case(decode_SRC1_CTRL) + case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_75 = _zz_22; + _zz_87 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_75 = {29'd0, _zz_172}; + _zz_87 = {29'd0, _zz_187}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_75 = {decode_INSTRUCTION[31 : 12],12'h0}; + _zz_87 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_75 = {27'd0, _zz_173}; - end - endcase - end - - assign _zz_76 = _zz_174[11]; - always @ (*) begin - _zz_77[19] = _zz_76; - _zz_77[18] = _zz_76; - _zz_77[17] = _zz_76; - _zz_77[16] = _zz_76; - _zz_77[15] = _zz_76; - _zz_77[14] = _zz_76; - _zz_77[13] = _zz_76; - _zz_77[12] = _zz_76; - _zz_77[11] = _zz_76; - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7] = _zz_76; - _zz_77[6] = _zz_76; - _zz_77[5] = _zz_76; - _zz_77[4] = _zz_76; - _zz_77[3] = _zz_76; - _zz_77[2] = _zz_76; - _zz_77[1] = _zz_76; - _zz_77[0] = _zz_76; - end - - assign _zz_78 = _zz_175[11]; - always @ (*) begin - _zz_79[19] = _zz_78; - _zz_79[18] = _zz_78; - _zz_79[17] = _zz_78; - _zz_79[16] = _zz_78; - _zz_79[15] = _zz_78; - _zz_79[14] = _zz_78; - _zz_79[13] = _zz_78; - _zz_79[12] = _zz_78; - _zz_79[11] = _zz_78; - _zz_79[10] = _zz_78; - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7] = _zz_78; - _zz_79[6] = _zz_78; - _zz_79[5] = _zz_78; - _zz_79[4] = _zz_78; - _zz_79[3] = _zz_78; - _zz_79[2] = _zz_78; - _zz_79[1] = _zz_78; - _zz_79[0] = _zz_78; + _zz_87 = {27'd0, _zz_188}; + end + endcase end + assign _zz_88 = _zz_189[11]; always @ (*) begin - case(decode_SRC2_CTRL) + _zz_89[19] = _zz_88; + _zz_89[18] = _zz_88; + _zz_89[17] = _zz_88; + _zz_89[16] = _zz_88; + _zz_89[15] = _zz_88; + _zz_89[14] = _zz_88; + _zz_89[13] = _zz_88; + _zz_89[12] = _zz_88; + _zz_89[11] = _zz_88; + _zz_89[10] = _zz_88; + _zz_89[9] = _zz_88; + _zz_89[8] = _zz_88; + _zz_89[7] = _zz_88; + _zz_89[6] = _zz_88; + _zz_89[5] = _zz_88; + _zz_89[4] = _zz_88; + _zz_89[3] = _zz_88; + _zz_89[2] = _zz_88; + _zz_89[1] = _zz_88; + _zz_89[0] = _zz_88; + end + + assign _zz_90 = _zz_190[11]; + always @ (*) begin + _zz_91[19] = _zz_90; + _zz_91[18] = _zz_90; + _zz_91[17] = _zz_90; + _zz_91[16] = _zz_90; + _zz_91[15] = _zz_90; + _zz_91[14] = _zz_90; + _zz_91[13] = _zz_90; + _zz_91[12] = _zz_90; + _zz_91[11] = _zz_90; + _zz_91[10] = _zz_90; + _zz_91[9] = _zz_90; + _zz_91[8] = _zz_90; + _zz_91[7] = _zz_90; + _zz_91[6] = _zz_90; + _zz_91[5] = _zz_90; + _zz_91[4] = _zz_90; + _zz_91[3] = _zz_90; + _zz_91[2] = _zz_90; + _zz_91[1] = _zz_90; + _zz_91[0] = _zz_90; + end + + always @ (*) begin + case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_80 = _zz_20; + _zz_92 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_80 = {_zz_77,decode_INSTRUCTION[31 : 20]}; + _zz_92 = {_zz_89,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_80 = {_zz_79,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + _zz_92 = {_zz_91,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_80 = _zz_19; + _zz_92 = _zz_33; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_176; + execute_SrcPlugin_addSub = _zz_191; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -2387,169 +2812,197 @@ module VexRiscv ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); - assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_81 = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_93 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_81 = _zz_183; + _zz_93 = _zz_198; end endcase end always @ (*) begin - _zz_82 = 1'b0; - if(_zz_84)begin - if((_zz_85 == decode_INSTRUCTION[19 : 15]))begin - _zz_82 = 1'b1; + _zz_94 = 1'b0; + if(_zz_96)begin + if((_zz_97 == decode_INSTRUCTION[19 : 15]))begin + _zz_94 = 1'b1; end end - if(_zz_142)begin - if(_zz_143)begin + if(_zz_151)begin + if(_zz_152)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_94 = 1'b1; + end + end + end + if(_zz_153)begin + if(_zz_154)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_94 = 1'b1; + end + end + end + if(_zz_155)begin + if(_zz_156)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_82 = 1'b1; + _zz_94 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_82 = 1'b0; + _zz_94 = 1'b0; end end always @ (*) begin - _zz_83 = 1'b0; - if(_zz_84)begin - if((_zz_85 == decode_INSTRUCTION[24 : 20]))begin - _zz_83 = 1'b1; + _zz_95 = 1'b0; + if(_zz_96)begin + if((_zz_97 == decode_INSTRUCTION[24 : 20]))begin + _zz_95 = 1'b1; end end - if(_zz_142)begin - if(_zz_143)begin + if(_zz_151)begin + if(_zz_152)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_95 = 1'b1; + end + end + end + if(_zz_153)begin + if(_zz_154)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_95 = 1'b1; + end + end + end + if(_zz_155)begin + if(_zz_156)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_83 = 1'b1; + _zz_95 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_83 = 1'b0; + _zz_95 = 1'b0; end end assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_86 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_86 == 3'b000)) begin - _zz_87 = execute_BranchPlugin_eq; - end else if((_zz_86 == 3'b001)) begin - _zz_87 = (! execute_BranchPlugin_eq); - end else if((((_zz_86 & 3'b101) == 3'b101))) begin - _zz_87 = (! execute_SRC_LESS); + assign _zz_98 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_98 == 3'b000)) begin + _zz_99 = execute_BranchPlugin_eq; + end else if((_zz_98 == 3'b001)) begin + _zz_99 = (! execute_BranchPlugin_eq); + end else if((((_zz_98 & 3'b101) == 3'b101))) begin + _zz_99 = (! execute_SRC_LESS); end else begin - _zz_87 = execute_SRC_LESS; + _zz_99 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_88 = 1'b0; + _zz_100 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_88 = 1'b1; + _zz_100 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_88 = 1'b1; + _zz_100 = 1'b1; end default : begin - _zz_88 = _zz_87; + _zz_100 = _zz_99; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_89 = _zz_185[19]; - always @ (*) begin - _zz_90[10] = _zz_89; - _zz_90[9] = _zz_89; - _zz_90[8] = _zz_89; - _zz_90[7] = _zz_89; - _zz_90[6] = _zz_89; - _zz_90[5] = _zz_89; - _zz_90[4] = _zz_89; - _zz_90[3] = _zz_89; - _zz_90[2] = _zz_89; - _zz_90[1] = _zz_89; - _zz_90[0] = _zz_89; - end - - assign _zz_91 = _zz_186[11]; - always @ (*) begin - _zz_92[19] = _zz_91; - _zz_92[18] = _zz_91; - _zz_92[17] = _zz_91; - _zz_92[16] = _zz_91; - _zz_92[15] = _zz_91; - _zz_92[14] = _zz_91; - _zz_92[13] = _zz_91; - _zz_92[12] = _zz_91; - _zz_92[11] = _zz_91; - _zz_92[10] = _zz_91; - _zz_92[9] = _zz_91; - _zz_92[8] = _zz_91; - _zz_92[7] = _zz_91; - _zz_92[6] = _zz_91; - _zz_92[5] = _zz_91; - _zz_92[4] = _zz_91; - _zz_92[3] = _zz_91; - _zz_92[2] = _zz_91; - _zz_92[1] = _zz_91; - _zz_92[0] = _zz_91; - end - - assign _zz_93 = _zz_187[11]; - always @ (*) begin - _zz_94[18] = _zz_93; - _zz_94[17] = _zz_93; - _zz_94[16] = _zz_93; - _zz_94[15] = _zz_93; - _zz_94[14] = _zz_93; - _zz_94[13] = _zz_93; - _zz_94[12] = _zz_93; - _zz_94[11] = _zz_93; - _zz_94[10] = _zz_93; - _zz_94[9] = _zz_93; - _zz_94[8] = _zz_93; - _zz_94[7] = _zz_93; - _zz_94[6] = _zz_93; - _zz_94[5] = _zz_93; - _zz_94[4] = _zz_93; - _zz_94[3] = _zz_93; - _zz_94[2] = _zz_93; - _zz_94[1] = _zz_93; - _zz_94[0] = _zz_93; + assign _zz_101 = _zz_200[19]; + always @ (*) begin + _zz_102[10] = _zz_101; + _zz_102[9] = _zz_101; + _zz_102[8] = _zz_101; + _zz_102[7] = _zz_101; + _zz_102[6] = _zz_101; + _zz_102[5] = _zz_101; + _zz_102[4] = _zz_101; + _zz_102[3] = _zz_101; + _zz_102[2] = _zz_101; + _zz_102[1] = _zz_101; + _zz_102[0] = _zz_101; + end + + assign _zz_103 = _zz_201[11]; + always @ (*) begin + _zz_104[19] = _zz_103; + _zz_104[18] = _zz_103; + _zz_104[17] = _zz_103; + _zz_104[16] = _zz_103; + _zz_104[15] = _zz_103; + _zz_104[14] = _zz_103; + _zz_104[13] = _zz_103; + _zz_104[12] = _zz_103; + _zz_104[11] = _zz_103; + _zz_104[10] = _zz_103; + _zz_104[9] = _zz_103; + _zz_104[8] = _zz_103; + _zz_104[7] = _zz_103; + _zz_104[6] = _zz_103; + _zz_104[5] = _zz_103; + _zz_104[4] = _zz_103; + _zz_104[3] = _zz_103; + _zz_104[2] = _zz_103; + _zz_104[1] = _zz_103; + _zz_104[0] = _zz_103; + end + + assign _zz_105 = _zz_202[11]; + always @ (*) begin + _zz_106[18] = _zz_105; + _zz_106[17] = _zz_105; + _zz_106[16] = _zz_105; + _zz_106[15] = _zz_105; + _zz_106[14] = _zz_105; + _zz_106[13] = _zz_105; + _zz_106[12] = _zz_105; + _zz_106[11] = _zz_105; + _zz_106[10] = _zz_105; + _zz_106[9] = _zz_105; + _zz_106[8] = _zz_105; + _zz_106[7] = _zz_105; + _zz_106[6] = _zz_105; + _zz_106[5] = _zz_105; + _zz_106[4] = _zz_105; + _zz_106[3] = _zz_105; + _zz_106[2] = _zz_105; + _zz_106[1] = _zz_105; + _zz_106[0] = _zz_105; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_95 = {{_zz_90,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_107 = {{_zz_102,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_95 = {_zz_92,execute_INSTRUCTION[31 : 20]}; + _zz_107 = {_zz_104,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_95 = {{_zz_94,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_107 = {{_zz_106,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_95; + assign execute_BranchPlugin_branch_src2 = _zz_107; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); - assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); - assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; always @ (*) begin CsrPlugin_privilege = 2'b11; if(CsrPlugin_forceMachineWire)begin @@ -2559,13 +3012,11 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_96 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_97 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_98 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_108 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_109 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_110 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_99 = {CsrPlugin_selfException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_100 = _zz_188[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; if(decodeExceptionPort_valid)begin @@ -2578,7 +3029,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_137)begin + if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -2586,14 +3037,33 @@ module VexRiscv ( end end + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(DBusSimplePlugin_memoryExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException); + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_0; - if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != 1'b0))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -2639,7 +3109,7 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign execute_CsrPlugin_blockedBySideEffects = (1'b0 || 1'b0); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; if(execute_CsrPlugin_csr_768)begin @@ -2687,7 +3157,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_144)begin + if(_zz_157)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -2706,14 +3176,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_145)begin + if(_zz_158)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_145)begin + if(_zz_158)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -2728,14 +3198,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_144)begin + if(_zz_157)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_144)begin + if(_zz_157)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -2744,7 +3214,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_154) + case(_zz_167) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -2755,171 +3225,190 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; always @ (*) begin - execute_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_133)begin - if(_zz_136)begin - execute_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; + memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; + if(_zz_141)begin + if(_zz_146)begin + memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end end always @ (*) begin - execute_MulDivIterativePlugin_mul_counter_willClear = 1'b0; - if((! execute_arbitration_isStuck))begin - execute_MulDivIterativePlugin_mul_counter_willClear = 1'b1; + memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; end end - assign execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (execute_MulDivIterativePlugin_mul_counter_value == 6'h20); - assign execute_MulDivIterativePlugin_mul_counter_willOverflow = (execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc && execute_MulDivIterativePlugin_mul_counter_willIncrement); + assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); + assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); always @ (*) begin - if(execute_MulDivIterativePlugin_mul_counter_willOverflow)begin - execute_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - execute_MulDivIterativePlugin_mul_counter_valueNext = (execute_MulDivIterativePlugin_mul_counter_value + _zz_191); - end - if(execute_MulDivIterativePlugin_mul_counter_willClear)begin - execute_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; - end - end - - assign _zz_101 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_102 = ((execute_IS_MUL && _zz_101) || 1'b0); - always @ (*) begin - _zz_103[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_103[31 : 0] = execute_RS1; - end - - assign _zz_105 = (_zz_104 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_105 != 32'h0); - assign _zz_23 = _zz_35; - assign _zz_21 = _zz_34; - assign _zz_15 = decode_ALU_CTRL; - assign _zz_13 = _zz_33; - assign _zz_24 = decode_to_execute_ALU_CTRL; - assign _zz_12 = decode_ALU_BITWISE_CTRL; - assign _zz_10 = _zz_32; - assign _zz_25 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_9 = decode_SHIFT_CTRL; - assign _zz_7 = _zz_31; - assign _zz_18 = decode_to_execute_SHIFT_CTRL; - assign _zz_6 = decode_BRANCH_CTRL; - assign _zz_4 = _zz_30; - assign _zz_17 = decode_to_execute_BRANCH_CTRL; - assign _zz_3 = decode_ENV_CTRL; - assign _zz_1 = _zz_29; - assign _zz_16 = decode_to_execute_ENV_CTRL; - assign decode_arbitration_isFlushed = ((execute_arbitration_flushNext != 1'b0) || ({execute_arbitration_flushIt,decode_arbitration_flushIt} != 2'b00)); - assign execute_arbitration_isFlushed = (1'b0 || (execute_arbitration_flushIt != 1'b0)); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_204); + end + if(memory_MulDivIterativePlugin_mul_counter_willClear)begin + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + end + end + + assign _zz_111 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_112 = ((execute_IS_MUL && _zz_111) || 1'b0); + always @ (*) begin + _zz_113[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_113[31 : 0] = execute_RS1; + end + + assign _zz_115 = (_zz_114 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_115 != 32'h0); + assign _zz_25 = decode_SRC1_CTRL; + assign _zz_23 = _zz_47; + assign _zz_35 = decode_to_execute_SRC1_CTRL; + assign _zz_22 = decode_SRC2_CTRL; + assign _zz_20 = _zz_46; + assign _zz_34 = decode_to_execute_SRC2_CTRL; + assign _zz_19 = decode_ALU_CTRL; + assign _zz_17 = _zz_45; + assign _zz_36 = decode_to_execute_ALU_CTRL; + assign _zz_16 = decode_ALU_BITWISE_CTRL; + assign _zz_14 = _zz_44; + assign _zz_37 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_13 = decode_SHIFT_CTRL; + assign _zz_11 = _zz_43; + assign _zz_32 = decode_to_execute_SHIFT_CTRL; + assign _zz_10 = decode_BRANCH_CTRL; + assign _zz_8 = _zz_42; + assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_7 = decode_ENV_CTRL; + assign _zz_4 = execute_ENV_CTRL; + assign _zz_2 = memory_ENV_CTRL; + assign _zz_5 = _zz_41; + assign _zz_28 = decode_to_execute_ENV_CTRL; + assign _zz_27 = execute_to_memory_ENV_CTRL; + assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_106 = 32'h0; + _zz_116 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_106[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_106[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_106[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_116[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_116[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_116[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_107 = 32'h0; + _zz_117 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_107[11 : 11] = CsrPlugin_mip_MEIP; - _zz_107[7 : 7] = CsrPlugin_mip_MTIP; - _zz_107[3 : 3] = CsrPlugin_mip_MSIP; + _zz_117[11 : 11] = CsrPlugin_mip_MEIP; + _zz_117[7 : 7] = CsrPlugin_mip_MTIP; + _zz_117[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_108 = 32'h0; + _zz_118 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_108[11 : 11] = CsrPlugin_mie_MEIE; - _zz_108[7 : 7] = CsrPlugin_mie_MTIE; - _zz_108[3 : 3] = CsrPlugin_mie_MSIE; + _zz_118[11 : 11] = CsrPlugin_mie_MEIE; + _zz_118[7 : 7] = CsrPlugin_mie_MTIE; + _zz_118[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_109 = 32'h0; + _zz_119 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_109[31 : 0] = CsrPlugin_mepc; + _zz_119[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_110 = 32'h0; + _zz_120 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_110[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_110[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_120[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_120[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_111 = 32'h0; + _zz_121 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_111[31 : 0] = CsrPlugin_mtval; + _zz_121[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_112 = 32'h0; + _zz_122 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_112[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_122[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_113 = 32'h0; + _zz_123 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_113[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_123[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_114 = 32'h0; + _zz_124 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_114[31 : 0] = _zz_104; + _zz_124[31 : 0] = _zz_114; end end always @ (*) begin - _zz_115 = 32'h0; + _zz_125 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_115[31 : 0] = _zz_105; + _zz_125[31 : 0] = _zz_115; end end - assign execute_CsrPlugin_readData = ((((_zz_106 | _zz_107) | (_zz_108 | _zz_109)) | ((_zz_110 | _zz_111) | (_zz_112 | _zz_113))) | (_zz_114 | _zz_115)); - assign iBusWishbone_ADR = {_zz_208,_zz_116}; - assign iBusWishbone_CTI = ((_zz_116 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = ((((_zz_116 | _zz_117) | (_zz_118 | _zz_119)) | ((_zz_120 | _zz_121) | (_zz_122 | _zz_123))) | (_zz_124 | _zz_125)); + assign iBusWishbone_ADR = {_zz_221,_zz_126}; + assign iBusWishbone_CTI = ((_zz_126 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_146)begin + if(_zz_159)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_146)begin + if(_zz_159)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_117; + assign iBus_rsp_valid = _zz_127; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; @@ -2934,19 +3423,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_118 = 4'b0001; + _zz_128 = 4'b0001; end 2'b01 : begin - _zz_118 = 4'b0011; + _zz_128 = 4'b0011; end default : begin - _zz_118 = 4'b1111; + _zz_128 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_118 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_128 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -2966,17 +3455,18 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_46 <= 1'b0; - _zz_48 <= 1'b0; + _zz_59 <= 1'b0; + _zz_61 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_50; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_63; IBusCachedPlugin_rspCounter <= 32'h0; - _zz_51 <= 1'b0; - _zz_73 <= 1'b1; + _zz_85 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_84 <= 1'b0; + _zz_96 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -2985,16 +3475,21 @@ module VexRiscv ( CsrPlugin_mie_MSIE <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - execute_MulDivIterativePlugin_frontendOk <= 1'b0; - execute_MulDivIterativePlugin_mul_counter_value <= 6'h0; - _zz_104 <= 32'h0; + memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; + _zz_114 <= 32'h0; execute_arbitration_isValid <= 1'b0; - _zz_116 <= 3'b000; - _zz_117 <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_126 <= 3'b000; + _zz_127 <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin @@ -3018,16 +3513,16 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_46 <= 1'b0; + _zz_59 <= 1'b0; end - if(_zz_44)begin - _zz_46 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_57)begin + _zz_59 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_48 <= 1'b0; + _zz_61 <= 1'b0; end if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_48 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + _zz_61 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; @@ -3053,18 +3548,50 @@ module VexRiscv ( if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((dBus_cmd_valid && dBus_cmd_ready))begin - _zz_51 <= 1'b1; + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if((! execute_arbitration_isStuck))begin - _zz_51 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - _zz_73 <= 1'b0; - if(_zz_131)begin - if(_zz_147)begin + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + _zz_85 <= 1'b0; + if(_zz_142)begin + if(_zz_160)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -3074,7 +3601,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_84 <= (_zz_27 && execute_arbitration_isFiring); + _zz_96 <= (_zz_39 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -3083,17 +3610,27 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_148)begin - if(_zz_149)begin + if(_zz_161)begin + if(_zz_162)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_150)begin + if(_zz_163)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_151)begin + if(_zz_164)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -3101,15 +3638,23 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end end if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end if(CsrPlugin_interruptJump)begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_138)begin + if(_zz_147)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3120,8 +3665,8 @@ module VexRiscv ( end endcase end - if(_zz_139)begin - case(_zz_140) + if(_zz_148)begin + case(_zz_149) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3131,46 +3676,52 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_98,{_zz_97,_zz_96}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(((execute_arbitration_isValid && (! 1'b0)) && (1'b0 || execute_IS_MUL)))begin - execute_MulDivIterativePlugin_frontendOk <= 1'b1; - end - if(execute_arbitration_isMoving)begin - execute_MulDivIterativePlugin_frontendOk <= 1'b0; - end - execute_MulDivIterativePlugin_mul_counter_value <= execute_MulDivIterativePlugin_mul_counter_valueNext; + execute_CsrPlugin_wfiWake <= (({_zz_110,{_zz_109,_zz_108}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin execute_arbitration_isValid <= decode_arbitration_isValid; end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_202[0]; - CsrPlugin_mstatus_MIE <= _zz_203[0]; + CsrPlugin_mstatus_MPIE <= _zz_215[0]; + CsrPlugin_mstatus_MIE <= _zz_216[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_205[0]; - CsrPlugin_mie_MTIE <= _zz_206[0]; - CsrPlugin_mie_MSIE <= _zz_207[0]; + CsrPlugin_mie_MEIE <= _zz_218[0]; + CsrPlugin_mie_MTIE <= _zz_219[0]; + CsrPlugin_mie_MSIE <= _zz_220[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_104 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_114 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_146)begin + if(_zz_159)begin if(iBusWishbone_ACK)begin - _zz_116 <= (_zz_116 + 3'b001); + _zz_126 <= (_zz_126 + 3'b001); end end - _zz_117 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_152)begin + _zz_127 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_165)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -3182,7 +3733,7 @@ module VexRiscv ( always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_49 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_62 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; @@ -3190,50 +3741,51 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if((! execute_arbitration_isStuckByOthers))begin - execute_LightShifterPlugin_shiftReg <= _zz_36; - end - if(_zz_131)begin - if(_zz_147)begin + if(_zz_142)begin + if(_zz_160)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - _zz_85 <= _zz_26[11 : 7]; + _zz_97 <= _zz_38[11 : 7]; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(execute_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end if(decodeExceptionPort_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= decodeExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= decodeExceptionPort_payload_badAddr; end - if(_zz_137)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_100 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_100 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_148)begin - if(_zz_149)begin + if(DBusSimplePlugin_memoryExceptionPort_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusSimplePlugin_memoryExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + end + if(_zz_161)begin + if(_zz_162)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_150)begin + if(_zz_163)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_151)begin + if(_zz_164)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_138)begin + if(_zz_147)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= execute_PC; + CsrPlugin_mepc <= writeBack_PC; if(CsrPlugin_hadException)begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end @@ -3242,63 +3794,123 @@ module VexRiscv ( end endcase end - if(_zz_133)begin - if(_zz_136)begin - execute_MulDivIterativePlugin_rs2 <= (execute_MulDivIterativePlugin_rs2 >>> 1); - execute_MulDivIterativePlugin_accumulator <= ({_zz_192,execute_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + if(_zz_141)begin + if(_zz_146)begin + memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_205,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end - if((! execute_MulDivIterativePlugin_frontendOk))begin - execute_MulDivIterativePlugin_accumulator <= 65'h0; - execute_MulDivIterativePlugin_rs1 <= ((_zz_102 ? (~ _zz_103) : _zz_103) + _zz_199); - execute_MulDivIterativePlugin_rs2 <= ((_zz_101 ? (~ execute_RS2) : execute_RS2) + _zz_201); + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_112 ? (~ _zz_113) : _zz_113) + _zz_212); + memory_MulDivIterativePlugin_rs2 <= ((_zz_111 ? (~ execute_RS2) : execute_RS2) + _zz_214); end externalInterruptArray_regNext <= externalInterruptArray; - if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin - decode_to_execute_PC <= _zz_19; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_33; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; end if((! execute_arbitration_isStuck))begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end if((! execute_arbitration_isStuck))begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_49; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_24; + end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_21; + end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_14; + decode_to_execute_ALU_CTRL <= _zz_18; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_11; + decode_to_execute_ALU_BITWISE_CTRL <= _zz_15; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_8; + decode_to_execute_SHIFT_CTRL <= _zz_12; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_5; + decode_to_execute_BRANCH_CTRL <= _zz_9; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_CSR <= decode_IS_CSR; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_2; + decode_to_execute_ENV_CTRL <= _zz_6; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_3; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_1; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_MUL <= decode_IS_MUL; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end @@ -3306,26 +3918,55 @@ module VexRiscv ( decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= _zz_22; + decode_to_execute_RS1 <= decode_RS1; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= _zz_20; + decode_to_execute_RS2 <= decode_RS2; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1 <= decode_SRC1; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2 <= decode_SRC2; - end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; + execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; + execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; + execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; + execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; + execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; + execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; + execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; + execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + end + if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_26; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end @@ -3361,7 +4002,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_204[0]; + CsrPlugin_mip_MSIP <= _zz_217[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -3376,7 +4017,7 @@ module VexRiscv ( end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_152)begin + if(_zz_165)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v index 70b319e..3c21cd3 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 301554ed50130998df7c9b3fa2a900ddbefe2027 +// Git hash : 43e13174d8583db5f4cd45d2b3515bc206a0010a `define Input2Kind_defaultEncoding_type [0:0] @@ -86,20 +86,18 @@ module VexRiscv ( input clk, input reset ); - wire _zz_132; - wire _zz_133; - wire _zz_134; - wire _zz_135; - wire _zz_136; - wire _zz_137; - wire _zz_138; - wire _zz_139; - reg _zz_140; - reg [31:0] _zz_141; - reg [31:0] _zz_142; - reg [31:0] _zz_143; - reg [3:0] _zz_144; - reg [31:0] _zz_145; + wire _zz_144; + wire _zz_145; + wire _zz_146; + wire _zz_147; + wire _zz_148; + wire _zz_149; + wire _zz_150; + wire _zz_151; + reg _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -112,16 +110,6 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_146; - wire _zz_147; - wire _zz_148; - wire _zz_149; - wire _zz_150; - wire _zz_151; - wire _zz_152; - wire _zz_153; - wire _zz_154; - wire [1:0] _zz_155; wire _zz_156; wire _zz_157; wire _zz_158; @@ -131,224 +119,255 @@ module VexRiscv ( wire _zz_162; wire _zz_163; wire _zz_164; - wire _zz_165; + wire [1:0] _zz_165; wire _zz_166; wire _zz_167; - wire [1:0] _zz_168; + wire _zz_168; wire _zz_169; - wire [0:0] _zz_170; - wire [0:0] _zz_171; - wire [0:0] _zz_172; - wire [0:0] _zz_173; - wire [0:0] _zz_174; - wire [0:0] _zz_175; - wire [0:0] _zz_176; - wire [0:0] _zz_177; - wire [0:0] _zz_178; - wire [0:0] _zz_179; - wire [0:0] _zz_180; - wire [0:0] _zz_181; - wire [0:0] _zz_182; - wire [0:0] _zz_183; - wire [2:0] _zz_184; - wire [2:0] _zz_185; - wire [31:0] _zz_186; + wire _zz_170; + wire _zz_171; + wire _zz_172; + wire _zz_173; + wire _zz_174; + wire _zz_175; + wire _zz_176; + wire _zz_177; + wire _zz_178; + wire _zz_179; + wire _zz_180; + wire _zz_181; + wire _zz_182; + wire [1:0] _zz_183; + wire _zz_184; + wire [0:0] _zz_185; + wire [0:0] _zz_186; wire [0:0] _zz_187; - wire [2:0] _zz_188; - wire [4:0] _zz_189; - wire [11:0] _zz_190; - wire [11:0] _zz_191; - wire [31:0] _zz_192; - wire [31:0] _zz_193; - wire [31:0] _zz_194; - wire [31:0] _zz_195; - wire [31:0] _zz_196; - wire [31:0] _zz_197; - wire [31:0] _zz_198; - wire [31:0] _zz_199; - wire [32:0] _zz_200; - wire [19:0] _zz_201; - wire [11:0] _zz_202; - wire [11:0] _zz_203; - wire [2:0] _zz_204; - wire [9:0] _zz_205; - wire [7:0] _zz_206; - wire [0:0] _zz_207; - wire [5:0] _zz_208; - wire [33:0] _zz_209; - wire [32:0] _zz_210; - wire [33:0] _zz_211; - wire [32:0] _zz_212; - wire [33:0] _zz_213; - wire [32:0] _zz_214; - wire [0:0] _zz_215; - wire [32:0] _zz_216; - wire [0:0] _zz_217; - wire [31:0] _zz_218; - wire [0:0] _zz_219; - wire [0:0] _zz_220; - wire [0:0] _zz_221; - wire [0:0] _zz_222; - wire [0:0] _zz_223; - wire [0:0] _zz_224; - wire [26:0] _zz_225; - wire _zz_226; - wire _zz_227; - wire [1:0] _zz_228; - wire [31:0] _zz_229; - wire [31:0] _zz_230; - wire [31:0] _zz_231; - wire _zz_232; + wire [0:0] _zz_188; + wire [0:0] _zz_189; + wire [0:0] _zz_190; + wire [0:0] _zz_191; + wire [0:0] _zz_192; + wire [0:0] _zz_193; + wire [0:0] _zz_194; + wire [0:0] _zz_195; + wire [0:0] _zz_196; + wire [0:0] _zz_197; + wire [0:0] _zz_198; + wire [0:0] _zz_199; + wire [0:0] _zz_200; + wire [2:0] _zz_201; + wire [2:0] _zz_202; + wire [31:0] _zz_203; + wire [0:0] _zz_204; + wire [2:0] _zz_205; + wire [4:0] _zz_206; + wire [11:0] _zz_207; + wire [11:0] _zz_208; + wire [31:0] _zz_209; + wire [31:0] _zz_210; + wire [31:0] _zz_211; + wire [31:0] _zz_212; + wire [31:0] _zz_213; + wire [31:0] _zz_214; + wire [31:0] _zz_215; + wire [31:0] _zz_216; + wire [32:0] _zz_217; + wire [19:0] _zz_218; + wire [11:0] _zz_219; + wire [11:0] _zz_220; + wire [1:0] _zz_221; + wire [1:0] _zz_222; + wire [9:0] _zz_223; + wire [7:0] _zz_224; + wire [0:0] _zz_225; + wire [5:0] _zz_226; + wire [33:0] _zz_227; + wire [32:0] _zz_228; + wire [33:0] _zz_229; + wire [32:0] _zz_230; + wire [33:0] _zz_231; + wire [32:0] _zz_232; wire [0:0] _zz_233; - wire [14:0] _zz_234; - wire [31:0] _zz_235; + wire [32:0] _zz_234; + wire [0:0] _zz_235; wire [31:0] _zz_236; - wire [31:0] _zz_237; - wire _zz_238; + wire [0:0] _zz_237; + wire [0:0] _zz_238; wire [0:0] _zz_239; - wire [8:0] _zz_240; - wire [31:0] _zz_241; - wire [31:0] _zz_242; - wire [31:0] _zz_243; + wire [0:0] _zz_240; + wire [0:0] _zz_241; + wire [0:0] _zz_242; + wire [26:0] _zz_243; wire _zz_244; - wire [0:0] _zz_245; - wire [2:0] _zz_246; + wire _zz_245; + wire [1:0] _zz_246; wire [31:0] _zz_247; wire [31:0] _zz_248; - wire [0:0] _zz_249; - wire [0:0] _zz_250; - wire _zz_251; - wire [0:0] _zz_252; - wire [24:0] _zz_253; + wire [31:0] _zz_249; + wire _zz_250; + wire [0:0] _zz_251; + wire [14:0] _zz_252; + wire [31:0] _zz_253; wire [31:0] _zz_254; - wire _zz_255; + wire [31:0] _zz_255; wire _zz_256; wire [0:0] _zz_257; - wire [0:0] _zz_258; - wire [0:0] _zz_259; - wire [0:0] _zz_260; - wire _zz_261; - wire [0:0] _zz_262; - wire [19:0] _zz_263; - wire [31:0] _zz_264; + wire [8:0] _zz_258; + wire [31:0] _zz_259; + wire [31:0] _zz_260; + wire [31:0] _zz_261; + wire _zz_262; + wire [0:0] _zz_263; + wire [2:0] _zz_264; wire [31:0] _zz_265; - wire _zz_266; - wire _zz_267; - wire _zz_268; - wire [2:0] _zz_269; - wire [2:0] _zz_270; - wire _zz_271; - wire [0:0] _zz_272; - wire [16:0] _zz_273; - wire [31:0] _zz_274; - wire [31:0] _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire [0:0] _zz_279; + wire [31:0] _zz_266; + wire [0:0] _zz_267; + wire [0:0] _zz_268; + wire _zz_269; + wire [0:0] _zz_270; + wire [24:0] _zz_271; + wire [31:0] _zz_272; + wire _zz_273; + wire _zz_274; + wire [0:0] _zz_275; + wire [0:0] _zz_276; + wire [0:0] _zz_277; + wire [0:0] _zz_278; + wire _zz_279; wire [0:0] _zz_280; - wire _zz_281; - wire [0:0] _zz_282; - wire [0:0] _zz_283; + wire [19:0] _zz_281; + wire [31:0] _zz_282; + wire [31:0] _zz_283; wire _zz_284; - wire [0:0] _zz_285; - wire [13:0] _zz_286; - wire [31:0] _zz_287; - wire [31:0] _zz_288; - wire [31:0] _zz_289; - wire [31:0] _zz_290; - wire [31:0] _zz_291; + wire _zz_285; + wire _zz_286; + wire [2:0] _zz_287; + wire [2:0] _zz_288; + wire _zz_289; + wire [0:0] _zz_290; + wire [16:0] _zz_291; wire [31:0] _zz_292; wire [31:0] _zz_293; - wire [31:0] _zz_294; - wire [0:0] _zz_295; - wire [0:0] _zz_296; - wire [1:0] _zz_297; - wire [1:0] _zz_298; + wire _zz_294; + wire _zz_295; + wire _zz_296; + wire [0:0] _zz_297; + wire [0:0] _zz_298; wire _zz_299; wire [0:0] _zz_300; - wire [11:0] _zz_301; - wire [31:0] _zz_302; - wire [31:0] _zz_303; - wire [31:0] _zz_304; + wire [0:0] _zz_301; + wire _zz_302; + wire [0:0] _zz_303; + wire [13:0] _zz_304; wire [31:0] _zz_305; wire [31:0] _zz_306; wire [31:0] _zz_307; - wire [0:0] _zz_308; - wire [1:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire _zz_312; + wire [31:0] _zz_308; + wire [31:0] _zz_309; + wire [31:0] _zz_310; + wire [31:0] _zz_311; + wire [31:0] _zz_312; wire [0:0] _zz_313; - wire [8:0] _zz_314; - wire [31:0] _zz_315; - wire [31:0] _zz_316; - wire [31:0] _zz_317; - wire [31:0] _zz_318; - wire [31:0] _zz_319; - wire _zz_320; - wire _zz_321; - wire [5:0] _zz_322; - wire [5:0] _zz_323; - wire _zz_324; - wire [0:0] _zz_325; - wire [5:0] _zz_326; - wire _zz_327; + wire [0:0] _zz_314; + wire [1:0] _zz_315; + wire [1:0] _zz_316; + wire _zz_317; + wire [0:0] _zz_318; + wire [11:0] _zz_319; + wire [31:0] _zz_320; + wire [31:0] _zz_321; + wire [31:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [0:0] _zz_326; + wire [1:0] _zz_327; wire [0:0] _zz_328; - wire [2:0] _zz_329; + wire [0:0] _zz_329; wire _zz_330; wire [0:0] _zz_331; - wire [0:0] _zz_332; - wire [3:0] _zz_333; - wire [3:0] _zz_334; - wire _zz_335; - wire [0:0] _zz_336; - wire [2:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire [31:0] _zz_340; - wire [0:0] _zz_341; - wire [0:0] _zz_342; - wire [31:0] _zz_343; - wire [31:0] _zz_344; - wire [31:0] _zz_345; - wire _zz_346; - wire [0:0] _zz_347; - wire [1:0] _zz_348; - wire _zz_349; - wire [2:0] _zz_350; - wire [2:0] _zz_351; - wire _zz_352; - wire [0:0] _zz_353; - wire [0:0] _zz_354; - wire [31:0] _zz_355; - wire [31:0] _zz_356; - wire [31:0] _zz_357; - wire [31:0] _zz_358; - wire [31:0] _zz_359; - wire [31:0] _zz_360; - wire [31:0] _zz_361; - wire _zz_362; + wire [8:0] _zz_332; + wire [31:0] _zz_333; + wire [31:0] _zz_334; + wire [31:0] _zz_335; + wire [31:0] _zz_336; + wire [31:0] _zz_337; + wire _zz_338; + wire _zz_339; + wire [0:0] _zz_340; + wire [1:0] _zz_341; + wire [5:0] _zz_342; + wire [5:0] _zz_343; + wire _zz_344; + wire [0:0] _zz_345; + wire [5:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; + wire [31:0] _zz_349; + wire [31:0] _zz_350; + wire _zz_351; + wire [0:0] _zz_352; + wire [2:0] _zz_353; + wire _zz_354; + wire [0:0] _zz_355; + wire [0:0] _zz_356; + wire [3:0] _zz_357; + wire [3:0] _zz_358; + wire _zz_359; + wire [0:0] _zz_360; + wire [2:0] _zz_361; + wire [31:0] _zz_362; wire [31:0] _zz_363; - wire _zz_364; - wire [0:0] _zz_365; + wire [31:0] _zz_364; + wire _zz_365; wire [0:0] _zz_366; wire [0:0] _zz_367; - wire [0:0] _zz_368; - wire [1:0] _zz_369; - wire [1:0] _zz_370; - wire [0:0] _zz_371; + wire [31:0] _zz_368; + wire [31:0] _zz_369; + wire [31:0] _zz_370; + wire _zz_371; wire [0:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire [31:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire [31:0] _zz_378; + wire [1:0] _zz_373; + wire _zz_374; + wire [2:0] _zz_375; + wire [2:0] _zz_376; + wire _zz_377; + wire [0:0] _zz_378; + wire [0:0] _zz_379; + wire [31:0] _zz_380; + wire [31:0] _zz_381; + wire [31:0] _zz_382; + wire [31:0] _zz_383; + wire [31:0] _zz_384; + wire [31:0] _zz_385; + wire [31:0] _zz_386; + wire [31:0] _zz_387; + wire _zz_388; + wire [31:0] _zz_389; + wire _zz_390; + wire [0:0] _zz_391; + wire [0:0] _zz_392; + wire [0:0] _zz_393; + wire [0:0] _zz_394; + wire [1:0] _zz_395; + wire [1:0] _zz_396; + wire [0:0] _zz_397; + wire [0:0] _zz_398; + wire [31:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; + wire [31:0] _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire [31:0] memory_MEMORY_READ_DATA; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; - wire [31:0] decode_SRC2; - wire [31:0] decode_SRC1; wire decode_SRC2_FORCE_ZERO; wire [31:0] decode_RS2; wire [31:0] decode_RS1; @@ -360,91 +379,136 @@ module VexRiscv ( wire `Input2Kind_defaultEncoding_type _zz_2; wire `Input2Kind_defaultEncoding_type _zz_3; wire decode_CfuPlugin_CFU_ENABLE; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; wire `EnvCtrlEnum_defaultEncoding_type _zz_4; wire `EnvCtrlEnum_defaultEncoding_type _zz_5; wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; wire decode_IS_CSR; wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_7; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12; + wire `BranchCtrlEnum_defaultEncoding_type _zz_13; wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_13; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; wire decode_SRC_LESS_UNSIGNED; wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_16; - wire `AluCtrlEnum_defaultEncoding_type _zz_17; - wire `AluCtrlEnum_defaultEncoding_type _zz_18; + wire `AluCtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_defaultEncoding_type _zz_22; wire decode_MEMORY_STORE; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `Src2CtrlEnum_defaultEncoding_type _zz_24; + wire `Src2CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire execute_IS_RS1_SIGNED; - wire execute_IS_RS2_SIGNED; wire execute_IS_MUL; - wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire execute_IS_RS2_SIGNED; + wire memory_IS_MUL; + reg _zz_29; + reg _zz_30; + reg [31:0] _zz_31; + wire memory_CfuPlugin_CFU_IN_FLIGHT; wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_19; + wire `Input2Kind_defaultEncoding_type _zz_32; wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_20; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; + wire [31:0] execute_PC; wire [31:0] execute_RS1; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_21; + wire `BranchCtrlEnum_defaultEncoding_type _zz_36; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] _zz_37; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_22; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_38; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_23; - wire [31:0] _zz_24; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_25; - wire [31:0] _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire [31:0] _zz_39; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_40; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_41; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_28; + wire `AluCtrlEnum_defaultEncoding_type _zz_42; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_29; - wire [31:0] _zz_30; - wire _zz_31; - reg _zz_32; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_44; + wire _zz_45; + reg _zz_46; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_33; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; - wire `BranchCtrlEnum_defaultEncoding_type _zz_35; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_36; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_37; - wire `AluCtrlEnum_defaultEncoding_type _zz_38; - wire `Src2CtrlEnum_defaultEncoding_type _zz_39; - wire `Src1CtrlEnum_defaultEncoding_type _zz_40; - reg [31:0] _zz_41; - wire [1:0] execute_MEMORY_ADDRESS_LOW; - wire [31:0] execute_MEMORY_READ_DATA; - wire [31:0] execute_REGFILE_WRITE_DATA; + wire `Input2Kind_defaultEncoding_type _zz_47; + wire `EnvCtrlEnum_defaultEncoding_type _zz_48; + wire `BranchCtrlEnum_defaultEncoding_type _zz_49; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_50; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_51; + wire `AluCtrlEnum_defaultEncoding_type _zz_52; + wire `Src2CtrlEnum_defaultEncoding_type _zz_53; + wire `Src1CtrlEnum_defaultEncoding_type _zz_54; + wire writeBack_MEMORY_STORE; + reg [31:0] _zz_55; + wire writeBack_MEMORY_ENABLE; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire [31:0] writeBack_MEMORY_READ_DATA; + wire memory_MMU_FAULT; + wire [31:0] memory_MMU_RSP2_physicalAddress; + wire memory_MMU_RSP2_isIoAccess; + wire memory_MMU_RSP2_isPaging; + wire memory_MMU_RSP2_allowRead; + wire memory_MMU_RSP2_allowWrite; + wire memory_MMU_RSP2_allowExecute; + wire memory_MMU_RSP2_exception; + wire memory_MMU_RSP2_refilling; + wire memory_MMU_RSP2_bypassTranslation; + wire [31:0] memory_PC; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_STORE; + wire memory_MEMORY_ENABLE; wire execute_MMU_FAULT; wire [31:0] execute_MMU_RSP2_physicalAddress; wire execute_MMU_RSP2_isIoAccess; @@ -457,6 +521,7 @@ module VexRiscv ( wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; @@ -465,9 +530,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_56; + reg [31:0] _zz_57; wire [31:0] decode_PC; - wire [31:0] execute_PC; - wire [31:0] execute_INSTRUCTION; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; reg decode_arbitration_haltItself; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; @@ -482,7 +549,7 @@ module VexRiscv ( reg execute_arbitration_haltItself; wire execute_arbitration_haltByOther; reg execute_arbitration_removeIt; - reg execute_arbitration_flushIt; + wire execute_arbitration_flushIt; reg execute_arbitration_flushNext; reg execute_arbitration_isValid; wire execute_arbitration_isStuck; @@ -490,6 +557,28 @@ module VexRiscv ( wire execute_arbitration_isFlushed; wire execute_arbitration_isMoving; wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + reg memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + wire writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; wire [31:0] lastStageInstruction /* verilator public */ ; wire [31:0] lastStagePc /* verilator public */ ; wire lastStageIsValid /* verilator public */ ; @@ -498,6 +587,8 @@ module VexRiscv ( reg IBusCachedPlugin_incomingInstruction; wire IBusCachedPlugin_pcValids_0; wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; wire IBusCachedPlugin_mmuBus_cmd_0_isValid; wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; @@ -544,6 +635,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_jumpInterface_payload; wire CsrPlugin_exceptionPendings_0; wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; wire externalInterrupt; wire contextSwitching; reg [1:0] CsrPlugin_privilege; @@ -559,10 +652,10 @@ module VexRiscv ( wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_42; - wire [2:0] _zz_43; - wire _zz_44; - wire _zz_45; + wire [2:0] _zz_58; + wire [2:0] _zz_59; + wire _zz_60; + wire _zz_61; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; @@ -599,16 +692,16 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_46; - wire _zz_47; - wire _zz_48; + wire _zz_62; + wire _zz_63; + wire _zz_64; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_49; - wire _zz_50; - reg _zz_51; - wire _zz_52; - reg _zz_53; - reg [31:0] _zz_54; + wire _zz_65; + wire _zz_66; + reg _zz_67; + wire _zz_68; + reg _zz_69; + reg [31:0] _zz_70; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -619,6 +712,8 @@ module VexRiscv ( reg IBusCachedPlugin_injector_nextPcCalc_valids_0; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -626,7 +721,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_55; + wire [31:0] _zz_71; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -643,34 +738,33 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - reg _zz_56; + wire _zz_72; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_57; - reg [3:0] _zz_58; + reg [31:0] _zz_73; + reg [3:0] _zz_74; wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] execute_DBusSimplePlugin_rspShifted; - wire _zz_59; - reg [31:0] _zz_60; - wire _zz_61; - reg [31:0] _zz_62; - reg [31:0] execute_DBusSimplePlugin_rspFormated; - wire [31:0] _zz_63; - wire _zz_64; - wire _zz_65; - wire _zz_66; - wire _zz_67; - wire _zz_68; - wire _zz_69; - wire _zz_70; - wire _zz_71; - wire `Src1CtrlEnum_defaultEncoding_type _zz_72; - wire `Src2CtrlEnum_defaultEncoding_type _zz_73; - wire `AluCtrlEnum_defaultEncoding_type _zz_74; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_75; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_76; - wire `BranchCtrlEnum_defaultEncoding_type _zz_77; - wire `EnvCtrlEnum_defaultEncoding_type _zz_78; - wire `Input2Kind_defaultEncoding_type _zz_79; + reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire _zz_75; + reg [31:0] _zz_76; + wire _zz_77; + reg [31:0] _zz_78; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [31:0] _zz_79; + wire _zz_80; + wire _zz_81; + wire _zz_82; + wire _zz_83; + wire _zz_84; + wire _zz_85; + wire _zz_86; + wire `Src1CtrlEnum_defaultEncoding_type _zz_87; + wire `Src2CtrlEnum_defaultEncoding_type _zz_88; + wire `AluCtrlEnum_defaultEncoding_type _zz_89; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_90; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_91; + wire `BranchCtrlEnum_defaultEncoding_type _zz_92; + wire `EnvCtrlEnum_defaultEncoding_type _zz_93; + wire `Input2Kind_defaultEncoding_type _zz_94; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -678,41 +772,40 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_80; + reg _zz_95; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_81; - reg [31:0] _zz_82; - wire _zz_83; - reg [19:0] _zz_84; - wire _zz_85; - reg [19:0] _zz_86; - reg [31:0] _zz_87; + reg [31:0] _zz_96; + reg [31:0] _zz_97; + wire _zz_98; + reg [19:0] _zz_99; + wire _zz_100; + reg [19:0] _zz_101; + reg [31:0] _zz_102; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; wire execute_LightShifterPlugin_isShift; reg [4:0] execute_LightShifterPlugin_amplitudeReg; wire [4:0] execute_LightShifterPlugin_amplitude; - reg [31:0] execute_LightShifterPlugin_shiftReg; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_88; - reg _zz_89; - reg _zz_90; - reg _zz_91; - reg [4:0] _zz_92; + reg [31:0] _zz_103; + reg _zz_104; + reg _zz_105; + reg _zz_106; + reg [4:0] _zz_107; wire execute_BranchPlugin_eq; - wire [2:0] _zz_93; - reg _zz_94; - reg _zz_95; + wire [2:0] _zz_108; + reg _zz_109; + reg _zz_110; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_96; - reg [10:0] _zz_97; - wire _zz_98; - reg [19:0] _zz_99; - wire _zz_100; - reg [18:0] _zz_101; - reg [31:0] _zz_102; + wire _zz_111; + reg [10:0] _zz_112; + wire _zz_113; + reg [19:0] _zz_114; + wire _zz_115; + reg [18:0] _zz_116; + reg [31:0] _zz_117; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -734,28 +827,31 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_103; - wire _zz_104; - wire _zz_105; + wire _zz_118; + wire _zz_119; + wire _zz_120; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [2:0] _zz_106; - wire [2:0] _zz_107; - wire _zz_108; - wire _zz_109; - wire [1:0] _zz_110; + wire [1:0] _zz_121; + wire _zz_122; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; reg CsrPlugin_pipelineLiberator_done; wire CsrPlugin_interruptJump /* verilator public */ ; @@ -780,36 +876,56 @@ module VexRiscv ( reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_111; - reg [23:0] _zz_112; - reg [31:0] _zz_113; - wire execute_CfuPlugin_rsp_valid; - reg execute_CfuPlugin_rsp_ready; - wire execute_CfuPlugin_rsp_payload_response_ok; - wire [31:0] execute_CfuPlugin_rsp_payload_outputs_0; - reg [32:0] execute_MulDivIterativePlugin_rs1; - reg [31:0] execute_MulDivIterativePlugin_rs2; - reg [64:0] execute_MulDivIterativePlugin_accumulator; - reg execute_MulDivIterativePlugin_frontendOk; - reg execute_MulDivIterativePlugin_mul_counter_willIncrement; - reg execute_MulDivIterativePlugin_mul_counter_willClear; - reg [5:0] execute_MulDivIterativePlugin_mul_counter_valueNext; - reg [5:0] execute_MulDivIterativePlugin_mul_counter_value; - wire execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc; - wire execute_MulDivIterativePlugin_mul_counter_willOverflow; - wire _zz_114; - wire _zz_115; - reg [32:0] _zz_116; + wire _zz_123; + reg [23:0] _zz_124; + reg [31:0] _zz_125; + wire memory_CfuPlugin_rsp_valid; + reg memory_CfuPlugin_rsp_ready; + wire memory_CfuPlugin_rsp_payload_response_ok; + wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_s2mPipe_rValid; + reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; + reg [32:0] memory_MulDivIterativePlugin_rs1; + reg [31:0] memory_MulDivIterativePlugin_rs2; + reg [64:0] memory_MulDivIterativePlugin_accumulator; + wire memory_MulDivIterativePlugin_frontendOk; + reg memory_MulDivIterativePlugin_mul_counter_willIncrement; + reg memory_MulDivIterativePlugin_mul_counter_willClear; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; + reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; + wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; + wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + wire _zz_126; + wire _zz_127; + reg [32:0] _zz_128; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_117; - wire [31:0] _zz_118; + reg [31:0] _zz_129; + wire [31:0] _zz_130; reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; reg decode_to_execute_SRC_USE_SUB_LESS; reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; reg decode_to_execute_MEMORY_STORE; + reg execute_to_memory_MEMORY_STORE; + reg memory_to_writeBack_MEMORY_STORE; reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; reg decode_to_execute_SRC_LESS_UNSIGNED; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; @@ -817,18 +933,36 @@ module VexRiscv ( reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; reg decode_to_execute_IS_CSR; reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; reg decode_to_execute_CfuPlugin_CFU_ENABLE; reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; reg decode_to_execute_IS_RS1_SIGNED; reg decode_to_execute_IS_RS2_SIGNED; reg [31:0] decode_to_execute_RS1; reg [31:0] decode_to_execute_RS2; reg decode_to_execute_SRC2_FORCE_ZERO; - reg [31:0] decode_to_execute_SRC1; - reg [31:0] decode_to_execute_SRC2; reg decode_to_execute_CSR_WRITE_OPCODE; reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg execute_to_memory_MMU_FAULT; + reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; + reg execute_to_memory_MMU_RSP2_isIoAccess; + reg execute_to_memory_MMU_RSP2_isPaging; + reg execute_to_memory_MMU_RSP2_allowRead; + reg execute_to_memory_MMU_RSP2_allowWrite; + reg execute_to_memory_MMU_RSP2_allowExecute; + reg execute_to_memory_MMU_RSP2_exception; + reg execute_to_memory_MMU_RSP2_refilling; + reg execute_to_memory_MMU_RSP2_bypassTranslation; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_836; reg execute_CsrPlugin_csr_772; @@ -840,18 +974,18 @@ module VexRiscv ( reg execute_CsrPlugin_csr_2944; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_119; - reg [31:0] _zz_120; - reg [31:0] _zz_121; - reg [31:0] _zz_122; - reg [31:0] _zz_123; - reg [31:0] _zz_124; - reg [31:0] _zz_125; - reg [31:0] _zz_126; - reg [31:0] _zz_127; - reg [31:0] _zz_128; - reg [2:0] _zz_129; - reg _zz_130; + reg [31:0] _zz_131; + reg [31:0] _zz_132; + reg [31:0] _zz_133; + reg [31:0] _zz_134; + reg [31:0] _zz_135; + reg [31:0] _zz_136; + reg [31:0] _zz_137; + reg [31:0] _zz_138; + reg [31:0] _zz_139; + reg [31:0] _zz_140; + reg [2:0] _zz_141; + reg _zz_142; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -865,333 +999,369 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_131; + reg [3:0] _zz_143; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; reg [39:0] _zz_3_string; - reg [39:0] decode_ENV_CTRL_string; reg [39:0] _zz_4_string; reg [39:0] _zz_5_string; reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [39:0] _zz_10_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; + reg [31:0] _zz_11_string; + reg [31:0] _zz_12_string; + reg [31:0] _zz_13_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; - reg [71:0] _zz_12_string; + reg [71:0] _zz_14_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_13_string; - reg [39:0] _zz_14_string; - reg [39:0] _zz_15_string; - reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_16_string; - reg [63:0] _zz_17_string; - reg [63:0] _zz_18_string; - reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_17_string; + reg [39:0] _zz_18_string; reg [39:0] _zz_19_string; - reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_20_string; - reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_21_string; - reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_22_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_20_string; + reg [63:0] _zz_21_string; + reg [63:0] _zz_22_string; reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_23_string; + reg [23:0] _zz_24_string; reg [23:0] _zz_25_string; reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_26_string; reg [95:0] _zz_27_string; - reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_28_string; - reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_29_string; + reg [95:0] _zz_28_string; + reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_32_string; + reg [39:0] memory_ENV_CTRL_string; reg [39:0] _zz_33_string; + reg [39:0] execute_ENV_CTRL_string; reg [39:0] _zz_34_string; - reg [31:0] _zz_35_string; - reg [71:0] _zz_36_string; - reg [39:0] _zz_37_string; - reg [63:0] _zz_38_string; - reg [23:0] _zz_39_string; - reg [95:0] _zz_40_string; - reg [95:0] _zz_72_string; - reg [23:0] _zz_73_string; - reg [63:0] _zz_74_string; - reg [39:0] _zz_75_string; - reg [71:0] _zz_76_string; - reg [31:0] _zz_77_string; - reg [39:0] _zz_78_string; - reg [39:0] _zz_79_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_35_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_36_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_38_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_40_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_41_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_42_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_43_string; + reg [39:0] _zz_47_string; + reg [39:0] _zz_48_string; + reg [31:0] _zz_49_string; + reg [71:0] _zz_50_string; + reg [39:0] _zz_51_string; + reg [63:0] _zz_52_string; + reg [23:0] _zz_53_string; + reg [95:0] _zz_54_string; + reg [95:0] _zz_87_string; + reg [23:0] _zz_88_string; + reg [63:0] _zz_89_string; + reg [39:0] _zz_90_string; + reg [71:0] _zz_91_string; + reg [31:0] _zz_92_string; + reg [39:0] _zz_93_string; + reg [39:0] _zz_94_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; `endif (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_146 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_147 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_148 = (execute_arbitration_isValid && execute_IS_MUL); - assign _zz_149 = ((_zz_137 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_150 = ((_zz_137 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_151 = (execute_MulDivIterativePlugin_frontendOk && (! execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_152 = ({CfuPlugin_joinException_valid,{CsrPlugin_selfException_valid,DBusSimplePlugin_memoryExceptionPort_valid}} != 3'b000); - assign _zz_153 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_154 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_155 = execute_INSTRUCTION[29 : 28]; - assign _zz_156 = (! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))); - assign _zz_157 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_158 = (1'b1 || (! 1'b1)); - assign _zz_159 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_160 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_161 = (iBus_cmd_valid || (_zz_129 != 3'b000)); - assign _zz_162 = (! execute_arbitration_isStuckByOthers); - assign _zz_163 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_164 = ((_zz_103 && 1'b1) && (! 1'b0)); - assign _zz_165 = ((_zz_104 && 1'b1) && (! 1'b0)); - assign _zz_166 = ((_zz_105 && 1'b1) && (! 1'b0)); - assign _zz_167 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_168 = execute_INSTRUCTION[13 : 12]; - assign _zz_169 = execute_INSTRUCTION[13]; - assign _zz_170 = _zz_63[31 : 31]; - assign _zz_171 = _zz_63[30 : 30]; - assign _zz_172 = _zz_63[29 : 29]; - assign _zz_173 = _zz_63[27 : 27]; - assign _zz_174 = _zz_63[24 : 24]; - assign _zz_175 = _zz_63[15 : 15]; - assign _zz_176 = _zz_63[11 : 11]; - assign _zz_177 = _zz_63[12 : 12]; - assign _zz_178 = _zz_63[5 : 5]; - assign _zz_179 = _zz_63[3 : 3]; - assign _zz_180 = _zz_63[18 : 18]; - assign _zz_181 = _zz_63[8 : 8]; - assign _zz_182 = _zz_63[4 : 4]; - assign _zz_183 = _zz_63[0 : 0]; - assign _zz_184 = (_zz_42 - 3'b001); - assign _zz_185 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_186 = {29'd0, _zz_185}; - assign _zz_187 = execute_SRC_LESS; - assign _zz_188 = 3'b100; - assign _zz_189 = decode_INSTRUCTION[19 : 15]; - assign _zz_190 = decode_INSTRUCTION[31 : 20]; - assign _zz_191 = {decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}; - assign _zz_192 = ($signed(_zz_193) + $signed(_zz_196)); - assign _zz_193 = ($signed(_zz_194) + $signed(_zz_195)); - assign _zz_194 = execute_SRC1; - assign _zz_195 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_196 = (execute_SRC_USE_SUB_LESS ? _zz_197 : _zz_198); - assign _zz_197 = 32'h00000001; - assign _zz_198 = 32'h0; - assign _zz_199 = (_zz_200 >>> 1); - assign _zz_200 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_201 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_202 = execute_INSTRUCTION[31 : 20]; - assign _zz_203 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_204 = (_zz_106 - 3'b001); - assign _zz_205 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_206 = execute_INSTRUCTION[31 : 24]; - assign _zz_207 = execute_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_208 = {5'd0, _zz_207}; - assign _zz_209 = (_zz_211 + _zz_213); - assign _zz_210 = (execute_MulDivIterativePlugin_rs2[0] ? execute_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_211 = {{1{_zz_210[32]}}, _zz_210}; - assign _zz_212 = _zz_214; - assign _zz_213 = {{1{_zz_212[32]}}, _zz_212}; - assign _zz_214 = (execute_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_215 = _zz_115; - assign _zz_216 = {32'd0, _zz_215}; - assign _zz_217 = _zz_114; - assign _zz_218 = {31'd0, _zz_217}; - assign _zz_219 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_220 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_221 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_222 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_223 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_224 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_225 = (iBus_cmd_payload_address >>> 5); - assign _zz_226 = 1'b1; - assign _zz_227 = 1'b1; - assign _zz_228 = {_zz_45,_zz_44}; - assign _zz_229 = 32'h0000106f; - assign _zz_230 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_231 = 32'h00001073; - assign _zz_232 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_233 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_234 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_235) == 32'h00000003),{(_zz_236 == _zz_237),{_zz_238,{_zz_239,_zz_240}}}}}}; - assign _zz_235 = 32'h0000207f; - assign _zz_236 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_237 = 32'h00000003; - assign _zz_238 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_239 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_240 = {((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033),{((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_241) == 32'h00005013),{(_zz_242 == _zz_243),{_zz_244,{_zz_245,_zz_246}}}}}}; - assign _zz_241 = 32'hbc00707f; - assign _zz_242 = (decode_INSTRUCTION & 32'hfc00705f); - assign _zz_243 = 32'h00001013; - assign _zz_244 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_245 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_246 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_247 = (decode_INSTRUCTION & 32'h02000074); - assign _zz_248 = 32'h02000030; - assign _zz_249 = _zz_69; - assign _zz_250 = 1'b0; - assign _zz_251 = (((decode_INSTRUCTION & 32'h10003050) == 32'h00000050) != 1'b0); - assign _zz_252 = (((decode_INSTRUCTION & _zz_254) == 32'h10000050) != 1'b0); - assign _zz_253 = {({_zz_255,_zz_256} != 2'b00),{({_zz_257,_zz_258} != 2'b00),{(_zz_259 != _zz_260),{_zz_261,{_zz_262,_zz_263}}}}}; - assign _zz_254 = 32'h10403050; - assign _zz_255 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_256 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_257 = _zz_68; - assign _zz_258 = ((decode_INSTRUCTION & _zz_264) == 32'h00000004); - assign _zz_259 = ((decode_INSTRUCTION & _zz_265) == 32'h00000040); - assign _zz_260 = 1'b0; - assign _zz_261 = ({_zz_266,_zz_267} != 2'b00); - assign _zz_262 = (_zz_268 != 1'b0); - assign _zz_263 = {(_zz_269 != _zz_270),{_zz_271,{_zz_272,_zz_273}}}; - assign _zz_264 = 32'h0000001c; - assign _zz_265 = 32'h00000058; - assign _zz_266 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); - assign _zz_267 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); - assign _zz_268 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); - assign _zz_269 = {(_zz_274 == _zz_275),{_zz_276,_zz_277}}; - assign _zz_270 = 3'b000; - assign _zz_271 = ({_zz_278,{_zz_279,_zz_280}} != 3'b000); - assign _zz_272 = (_zz_281 != 1'b0); - assign _zz_273 = {(_zz_282 != _zz_283),{_zz_284,{_zz_285,_zz_286}}}; - assign _zz_274 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_275 = 32'h40001010; - assign _zz_276 = ((decode_INSTRUCTION & _zz_287) == 32'h00001010); - assign _zz_277 = ((decode_INSTRUCTION & _zz_288) == 32'h00001010); - assign _zz_278 = ((decode_INSTRUCTION & _zz_289) == 32'h00000024); - assign _zz_279 = (_zz_290 == _zz_291); - assign _zz_280 = (_zz_292 == _zz_293); - assign _zz_281 = ((decode_INSTRUCTION & _zz_294) == 32'h00001000); - assign _zz_282 = _zz_70; - assign _zz_283 = 1'b0; - assign _zz_284 = ({_zz_295,_zz_296} != 2'b00); - assign _zz_285 = (_zz_297 != _zz_298); - assign _zz_286 = {_zz_299,{_zz_300,_zz_301}}; - assign _zz_287 = 32'h00007034; - assign _zz_288 = 32'h02007054; - assign _zz_289 = 32'h00000064; - assign _zz_290 = (decode_INSTRUCTION & 32'h00003034); - assign _zz_291 = 32'h00001010; - assign _zz_292 = (decode_INSTRUCTION & 32'h02003054); - assign _zz_293 = 32'h00001010; - assign _zz_294 = 32'h00001000; - assign _zz_295 = ((decode_INSTRUCTION & _zz_302) == 32'h00002000); - assign _zz_296 = ((decode_INSTRUCTION & _zz_303) == 32'h00001000); - assign _zz_297 = {(_zz_304 == _zz_305),(_zz_306 == _zz_307)}; - assign _zz_298 = 2'b00; - assign _zz_299 = (_zz_65 != 1'b0); - assign _zz_300 = ({_zz_308,_zz_309} != 3'b000); - assign _zz_301 = {(_zz_310 != _zz_311),{_zz_312,{_zz_313,_zz_314}}}; - assign _zz_302 = 32'h00002010; - assign _zz_303 = 32'h00005000; - assign _zz_304 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_305 = 32'h00006000; - assign _zz_306 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_307 = 32'h00004000; - assign _zz_308 = _zz_69; - assign _zz_309 = {(_zz_315 == _zz_316),(_zz_317 == _zz_318)}; - assign _zz_310 = ((decode_INSTRUCTION & _zz_319) == 32'h00000020); - assign _zz_311 = 1'b0; - assign _zz_312 = ({_zz_320,_zz_321} != 2'b00); - assign _zz_313 = (_zz_67 != 1'b0); - assign _zz_314 = {(_zz_322 != _zz_323),{_zz_324,{_zz_325,_zz_326}}}; - assign _zz_315 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_316 = 32'h00000020; - assign _zz_317 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_318 = 32'h00000020; - assign _zz_319 = 32'h00000020; - assign _zz_320 = ((decode_INSTRUCTION & 32'h00000008) == 32'h00000008); - assign _zz_321 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); - assign _zz_322 = {_zz_68,{_zz_327,{_zz_328,_zz_329}}}; - assign _zz_323 = 6'h0; - assign _zz_324 = ({_zz_66,_zz_330} != 2'b00); - assign _zz_325 = ({_zz_331,_zz_332} != 2'b00); - assign _zz_326 = {(_zz_333 != _zz_334),{_zz_335,{_zz_336,_zz_337}}}; - assign _zz_327 = ((decode_INSTRUCTION & _zz_338) == 32'h00001010); - assign _zz_328 = (_zz_339 == _zz_340); - assign _zz_329 = {_zz_67,{_zz_341,_zz_342}}; - assign _zz_330 = ((decode_INSTRUCTION & _zz_343) == 32'h00000020); - assign _zz_331 = _zz_66; - assign _zz_332 = (_zz_344 == _zz_345); - assign _zz_333 = {_zz_346,{_zz_347,_zz_348}}; - assign _zz_334 = 4'b0000; - assign _zz_335 = (_zz_349 != 1'b0); - assign _zz_336 = (_zz_350 != _zz_351); - assign _zz_337 = {_zz_352,{_zz_353,_zz_354}}; - assign _zz_338 = 32'h00001010; - assign _zz_339 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_340 = 32'h00002010; - assign _zz_341 = (_zz_355 == _zz_356); - assign _zz_342 = (_zz_357 == _zz_358); - assign _zz_343 = 32'h00000070; - assign _zz_344 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_345 = 32'h0; - assign _zz_346 = ((decode_INSTRUCTION & _zz_359) == 32'h0); - assign _zz_347 = (_zz_360 == _zz_361); - assign _zz_348 = {_zz_65,_zz_362}; - assign _zz_349 = ((decode_INSTRUCTION & _zz_363) == 32'h0); - assign _zz_350 = {_zz_364,{_zz_365,_zz_366}}; - assign _zz_351 = 3'b000; - assign _zz_352 = ({_zz_367,_zz_368} != 2'b00); - assign _zz_353 = (_zz_369 != _zz_370); - assign _zz_354 = (_zz_371 != _zz_372); - assign _zz_355 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_356 = 32'h00000004; - assign _zz_357 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_358 = 32'h0; - assign _zz_359 = 32'h00000044; - assign _zz_360 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_361 = 32'h0; - assign _zz_362 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_363 = 32'h00000058; - assign _zz_364 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_365 = ((decode_INSTRUCTION & _zz_373) == 32'h00002010); - assign _zz_366 = ((decode_INSTRUCTION & _zz_374) == 32'h40000030); - assign _zz_367 = ((decode_INSTRUCTION & _zz_375) == 32'h00000004); - assign _zz_368 = _zz_64; - assign _zz_369 = {(_zz_376 == _zz_377),_zz_64}; - assign _zz_370 = 2'b00; - assign _zz_371 = ((decode_INSTRUCTION & _zz_378) == 32'h00001004); - assign _zz_372 = 1'b0; - assign _zz_373 = 32'h00002014; - assign _zz_374 = 32'h40004034; - assign _zz_375 = 32'h00000014; - assign _zz_376 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_377 = 32'h00000004; - assign _zz_378 = 32'h00001054; + assign _zz_156 = (memory_arbitration_isValid && memory_IS_MUL); + assign _zz_157 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + assign _zz_158 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_159 = ((_zz_149 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_160 = ((_zz_149 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_161 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign _zz_162 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_163 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_164 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_165 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_166 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_167 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_168 = (1'b1 || (! 1'b1)); + assign _zz_169 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_170 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_171 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_172 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_173 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_174 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_175 = (iBus_cmd_valid || (_zz_141 != 3'b000)); + assign _zz_176 = (! execute_arbitration_isStuckByOthers); + assign _zz_177 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_178 = ((_zz_118 && 1'b1) && (! 1'b0)); + assign _zz_179 = ((_zz_119 && 1'b1) && (! 1'b0)); + assign _zz_180 = ((_zz_120 && 1'b1) && (! 1'b0)); + assign _zz_181 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_182 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_183 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_184 = execute_INSTRUCTION[13]; + assign _zz_185 = _zz_79[31 : 31]; + assign _zz_186 = _zz_79[30 : 30]; + assign _zz_187 = _zz_79[29 : 29]; + assign _zz_188 = _zz_79[27 : 27]; + assign _zz_189 = _zz_79[24 : 24]; + assign _zz_190 = _zz_79[15 : 15]; + assign _zz_191 = _zz_79[11 : 11]; + assign _zz_192 = _zz_79[10 : 10]; + assign _zz_193 = _zz_79[9 : 9]; + assign _zz_194 = _zz_79[12 : 12]; + assign _zz_195 = _zz_79[5 : 5]; + assign _zz_196 = _zz_79[3 : 3]; + assign _zz_197 = _zz_79[18 : 18]; + assign _zz_198 = _zz_79[8 : 8]; + assign _zz_199 = _zz_79[4 : 4]; + assign _zz_200 = _zz_79[0 : 0]; + assign _zz_201 = (_zz_58 - 3'b001); + assign _zz_202 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_203 = {29'd0, _zz_202}; + assign _zz_204 = execute_SRC_LESS; + assign _zz_205 = 3'b100; + assign _zz_206 = execute_INSTRUCTION[19 : 15]; + assign _zz_207 = execute_INSTRUCTION[31 : 20]; + assign _zz_208 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_209 = ($signed(_zz_210) + $signed(_zz_213)); + assign _zz_210 = ($signed(_zz_211) + $signed(_zz_212)); + assign _zz_211 = execute_SRC1; + assign _zz_212 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_213 = (execute_SRC_USE_SUB_LESS ? _zz_214 : _zz_215); + assign _zz_214 = 32'h00000001; + assign _zz_215 = 32'h0; + assign _zz_216 = (_zz_217 >>> 1); + assign _zz_217 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_218 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_219 = execute_INSTRUCTION[31 : 20]; + assign _zz_220 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_221 = (_zz_121 & (~ _zz_222)); + assign _zz_222 = (_zz_121 - 2'b01); + assign _zz_223 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_224 = execute_INSTRUCTION[31 : 24]; + assign _zz_225 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_226 = {5'd0, _zz_225}; + assign _zz_227 = (_zz_229 + _zz_231); + assign _zz_228 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_229 = {{1{_zz_228[32]}}, _zz_228}; + assign _zz_230 = _zz_232; + assign _zz_231 = {{1{_zz_230[32]}}, _zz_230}; + assign _zz_232 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_233 = _zz_127; + assign _zz_234 = {32'd0, _zz_233}; + assign _zz_235 = _zz_126; + assign _zz_236 = {31'd0, _zz_235}; + assign _zz_237 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_238 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_239 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_240 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_241 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_242 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_243 = (iBus_cmd_payload_address >>> 5); + assign _zz_244 = 1'b1; + assign _zz_245 = 1'b1; + assign _zz_246 = {_zz_61,_zz_60}; + assign _zz_247 = 32'h0000106f; + assign _zz_248 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_249 = 32'h00001073; + assign _zz_250 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_251 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_252 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_253) == 32'h00000003),{(_zz_254 == _zz_255),{_zz_256,{_zz_257,_zz_258}}}}}}; + assign _zz_253 = 32'h0000207f; + assign _zz_254 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_255 = 32'h00000003; + assign _zz_256 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_257 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_258 = {((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033),{((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_259) == 32'h00005013),{(_zz_260 == _zz_261),{_zz_262,{_zz_263,_zz_264}}}}}}; + assign _zz_259 = 32'hbc00707f; + assign _zz_260 = (decode_INSTRUCTION & 32'hfc00705f); + assign _zz_261 = 32'h00001013; + assign _zz_262 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_263 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_264 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_265 = (decode_INSTRUCTION & 32'h02000074); + assign _zz_266 = 32'h02000030; + assign _zz_267 = _zz_84; + assign _zz_268 = 1'b0; + assign _zz_269 = (((decode_INSTRUCTION & 32'h10003050) == 32'h00000050) != 1'b0); + assign _zz_270 = (((decode_INSTRUCTION & _zz_272) == 32'h10000050) != 1'b0); + assign _zz_271 = {({_zz_273,_zz_274} != 2'b00),{({_zz_275,_zz_276} != 2'b00),{(_zz_277 != _zz_278),{_zz_279,{_zz_280,_zz_281}}}}}; + assign _zz_272 = 32'h10403050; + assign _zz_273 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_274 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_275 = _zz_83; + assign _zz_276 = ((decode_INSTRUCTION & _zz_282) == 32'h00000004); + assign _zz_277 = ((decode_INSTRUCTION & _zz_283) == 32'h00000040); + assign _zz_278 = 1'b0; + assign _zz_279 = ({_zz_284,_zz_285} != 2'b00); + assign _zz_280 = (_zz_286 != 1'b0); + assign _zz_281 = {(_zz_287 != _zz_288),{_zz_289,{_zz_290,_zz_291}}}; + assign _zz_282 = 32'h0000001c; + assign _zz_283 = 32'h00000058; + assign _zz_284 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz_285 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); + assign _zz_286 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); + assign _zz_287 = {(_zz_292 == _zz_293),{_zz_294,_zz_295}}; + assign _zz_288 = 3'b000; + assign _zz_289 = ({_zz_296,{_zz_297,_zz_298}} != 3'b000); + assign _zz_290 = (_zz_299 != 1'b0); + assign _zz_291 = {(_zz_300 != _zz_301),{_zz_302,{_zz_303,_zz_304}}}; + assign _zz_292 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_293 = 32'h40001010; + assign _zz_294 = ((decode_INSTRUCTION & _zz_305) == 32'h00001010); + assign _zz_295 = ((decode_INSTRUCTION & _zz_306) == 32'h00001010); + assign _zz_296 = ((decode_INSTRUCTION & _zz_307) == 32'h00000024); + assign _zz_297 = (_zz_308 == _zz_309); + assign _zz_298 = (_zz_310 == _zz_311); + assign _zz_299 = ((decode_INSTRUCTION & _zz_312) == 32'h00001000); + assign _zz_300 = _zz_85; + assign _zz_301 = 1'b0; + assign _zz_302 = ({_zz_313,_zz_314} != 2'b00); + assign _zz_303 = (_zz_315 != _zz_316); + assign _zz_304 = {_zz_317,{_zz_318,_zz_319}}; + assign _zz_305 = 32'h00007034; + assign _zz_306 = 32'h02007054; + assign _zz_307 = 32'h00000064; + assign _zz_308 = (decode_INSTRUCTION & 32'h00003034); + assign _zz_309 = 32'h00001010; + assign _zz_310 = (decode_INSTRUCTION & 32'h02003054); + assign _zz_311 = 32'h00001010; + assign _zz_312 = 32'h00001000; + assign _zz_313 = ((decode_INSTRUCTION & _zz_320) == 32'h00002000); + assign _zz_314 = ((decode_INSTRUCTION & _zz_321) == 32'h00001000); + assign _zz_315 = {(_zz_322 == _zz_323),(_zz_324 == _zz_325)}; + assign _zz_316 = 2'b00; + assign _zz_317 = (_zz_81 != 1'b0); + assign _zz_318 = ({_zz_326,_zz_327} != 3'b000); + assign _zz_319 = {(_zz_328 != _zz_329),{_zz_330,{_zz_331,_zz_332}}}; + assign _zz_320 = 32'h00002010; + assign _zz_321 = 32'h00005000; + assign _zz_322 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_323 = 32'h00006000; + assign _zz_324 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_325 = 32'h00004000; + assign _zz_326 = _zz_84; + assign _zz_327 = {(_zz_333 == _zz_334),(_zz_335 == _zz_336)}; + assign _zz_328 = ((decode_INSTRUCTION & _zz_337) == 32'h00000020); + assign _zz_329 = 1'b0; + assign _zz_330 = ({_zz_338,_zz_339} != 2'b00); + assign _zz_331 = ({_zz_340,_zz_341} != 3'b000); + assign _zz_332 = {(_zz_342 != _zz_343),{_zz_344,{_zz_345,_zz_346}}}; + assign _zz_333 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_334 = 32'h00000020; + assign _zz_335 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_336 = 32'h00000020; + assign _zz_337 = 32'h00000020; + assign _zz_338 = ((decode_INSTRUCTION & 32'h00000008) == 32'h00000008); + assign _zz_339 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); + assign _zz_340 = _zz_82; + assign _zz_341 = {(_zz_347 == _zz_348),(_zz_349 == _zz_350)}; + assign _zz_342 = {_zz_83,{_zz_351,{_zz_352,_zz_353}}}; + assign _zz_343 = 6'h0; + assign _zz_344 = ({_zz_82,_zz_354} != 2'b00); + assign _zz_345 = ({_zz_355,_zz_356} != 2'b00); + assign _zz_346 = {(_zz_357 != _zz_358),{_zz_359,{_zz_360,_zz_361}}}; + assign _zz_347 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_348 = 32'h00000010; + assign _zz_349 = (decode_INSTRUCTION & 32'h02000060); + assign _zz_350 = 32'h00000020; + assign _zz_351 = ((decode_INSTRUCTION & _zz_362) == 32'h00001010); + assign _zz_352 = (_zz_363 == _zz_364); + assign _zz_353 = {_zz_365,{_zz_366,_zz_367}}; + assign _zz_354 = ((decode_INSTRUCTION & _zz_368) == 32'h00000020); + assign _zz_355 = _zz_82; + assign _zz_356 = (_zz_369 == _zz_370); + assign _zz_357 = {_zz_371,{_zz_372,_zz_373}}; + assign _zz_358 = 4'b0000; + assign _zz_359 = (_zz_374 != 1'b0); + assign _zz_360 = (_zz_375 != _zz_376); + assign _zz_361 = {_zz_377,{_zz_378,_zz_379}}; + assign _zz_362 = 32'h00001010; + assign _zz_363 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_364 = 32'h00002010; + assign _zz_365 = ((decode_INSTRUCTION & _zz_380) == 32'h00000010); + assign _zz_366 = (_zz_381 == _zz_382); + assign _zz_367 = (_zz_383 == _zz_384); + assign _zz_368 = 32'h00000070; + assign _zz_369 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_370 = 32'h0; + assign _zz_371 = ((decode_INSTRUCTION & _zz_385) == 32'h0); + assign _zz_372 = (_zz_386 == _zz_387); + assign _zz_373 = {_zz_81,_zz_388}; + assign _zz_374 = ((decode_INSTRUCTION & _zz_389) == 32'h0); + assign _zz_375 = {_zz_390,{_zz_391,_zz_392}}; + assign _zz_376 = 3'b000; + assign _zz_377 = ({_zz_393,_zz_394} != 2'b00); + assign _zz_378 = (_zz_395 != _zz_396); + assign _zz_379 = (_zz_397 != _zz_398); + assign _zz_380 = 32'h00000050; + assign _zz_381 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_382 = 32'h00000004; + assign _zz_383 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_384 = 32'h0; + assign _zz_385 = 32'h00000044; + assign _zz_386 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_387 = 32'h0; + assign _zz_388 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_389 = 32'h00000058; + assign _zz_390 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_391 = ((decode_INSTRUCTION & _zz_399) == 32'h00002010); + assign _zz_392 = ((decode_INSTRUCTION & _zz_400) == 32'h40000030); + assign _zz_393 = ((decode_INSTRUCTION & _zz_401) == 32'h00000004); + assign _zz_394 = _zz_80; + assign _zz_395 = {(_zz_402 == _zz_403),_zz_80}; + assign _zz_396 = 2'b00; + assign _zz_397 = ((decode_INSTRUCTION & _zz_404) == 32'h00001004); + assign _zz_398 = 1'b0; + assign _zz_399 = 32'h00002014; + assign _zz_400 = 32'h40004034; + assign _zz_401 = 32'h00000014; + assign _zz_402 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_403 = 32'h00000004; + assign _zz_404 = 32'h00001054; always @ (posedge clk) begin - if(_zz_226) begin - _zz_141 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_244) begin + _zz_153 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_227) begin - _zz_142 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_245) begin + _zz_154 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_32) begin + if(_zz_46) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_132 ), //i - .io_cpu_prefetch_isValid (_zz_133 ), //i + .io_flush (_zz_144 ), //i + .io_cpu_prefetch_isValid (_zz_145 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_134 ), //i - .io_cpu_fetch_isStuck (_zz_135 ), //i - .io_cpu_fetch_isRemoved (_zz_136 ), //i + .io_cpu_fetch_isValid (_zz_146 ), //i + .io_cpu_fetch_isStuck (_zz_147 ), //i + .io_cpu_fetch_isRemoved (_zz_148 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1204,8 +1374,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_137 ), //i - .io_cpu_decode_isStuck (_zz_138 ), //i + .io_cpu_decode_isValid (_zz_149 ), //i + .io_cpu_decode_isStuck (_zz_150 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1213,8 +1383,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_139 ), //i - .io_cpu_fill_valid (_zz_140 ), //i + .io_cpu_decode_isUser (_zz_151 ), //i + .io_cpu_fill_valid (_zz_152 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1227,32 +1397,15 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_228) - 2'b00 : begin - _zz_143 = DBusSimplePlugin_redoBranch_payload; - end - 2'b01 : begin - _zz_143 = CsrPlugin_jumpInterface_payload; - end - default : begin - _zz_143 = BranchPlugin_jumpInterface_payload; - end - endcase - end - - always @(*) begin - case(_zz_110) + case(_zz_246) 2'b00 : begin - _zz_144 = DBusSimplePlugin_memoryExceptionPort_payload_code; - _zz_145 = DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + _zz_155 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_144 = CsrPlugin_selfException_payload_code; - _zz_145 = CsrPlugin_selfException_payload_badAddr; + _zz_155 = DBusSimplePlugin_redoBranch_payload; end default : begin - _zz_144 = CfuPlugin_joinException_payload_code; - _zz_145 = CfuPlugin_joinException_payload_badAddr; + _zz_155 = BranchPlugin_jumpInterface_payload; end endcase end @@ -1286,14 +1439,6 @@ module VexRiscv ( default : _zz_3_string = "?????"; endcase end - always @(*) begin - case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; - default : decode_ENV_CTRL_string = "?????"; - endcase - end always @(*) begin case(_zz_4) `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; @@ -1318,6 +1463,46 @@ module VexRiscv ( default : _zz_6_string = "?????"; endcase end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; + default : _zz_10_string = "?????"; + endcase + end always @(*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; @@ -1328,30 +1513,30 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_7) - `BranchCtrlEnum_defaultEncoding_INC : _zz_7_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_7_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_7_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_7_string = "JALR"; - default : _zz_7_string = "????"; + case(_zz_11) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; + default : _zz_11_string = "????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_12) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; + default : _zz_12_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_13) + `BranchCtrlEnum_defaultEncoding_INC : _zz_13_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_13_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_13_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_13_string = "JALR"; + default : _zz_13_string = "????"; endcase end always @(*) begin @@ -1364,30 +1549,30 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; endcase end always @(*) begin @@ -1399,27 +1584,27 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_13) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_13_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_13_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_13_string = "AND_1"; - default : _zz_13_string = "?????"; + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; endcase end always @(*) begin - case(_zz_14) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; - default : _zz_14_string = "?????"; + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; endcase end always @(*) begin @@ -1431,27 +1616,99 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_16) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_16_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_16_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_16_string = "BITWISE "; - default : _zz_16_string = "????????"; + case(_zz_20) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; + default : _zz_20_string = "????????"; endcase end always @(*) begin - case(_zz_17) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17_string = "BITWISE "; - default : _zz_17_string = "????????"; + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; endcase end always @(*) begin - case(_zz_18) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18_string = "BITWISE "; - default : _zz_18_string = "????????"; + case(_zz_22) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; + default : _zz_22_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_23) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; + endcase + end + always @(*) begin + case(_zz_24) + `Src2CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_24_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_24_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_24_string = "PC "; + default : _zz_24_string = "???"; + endcase + end + always @(*) begin + case(_zz_25) + `Src2CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_25_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_25_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_25_string = "PC "; + default : _zz_25_string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; endcase end always @(*) begin @@ -1462,10 +1719,26 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_19) - `Input2Kind_defaultEncoding_RS : _zz_19_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_19_string = "IMM_I"; - default : _zz_19_string = "?????"; + case(_zz_32) + `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; + default : _zz_32_string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; endcase end always @(*) begin @@ -1477,11 +1750,27 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_20) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_20_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_20_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_20_string = "ECALL"; - default : _zz_20_string = "?????"; + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; endcase end always @(*) begin @@ -1494,12 +1783,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_21) - `BranchCtrlEnum_defaultEncoding_INC : _zz_21_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_21_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_21_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_21_string = "JALR"; - default : _zz_21_string = "????"; + case(_zz_36) + `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; + default : _zz_36_string = "????"; endcase end always @(*) begin @@ -1512,48 +1801,48 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_22) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_22_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_22_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_22_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_22_string = "SRA_1 "; - default : _zz_22_string = "?????????"; + case(_zz_38) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38_string = "SRA_1 "; + default : _zz_38_string = "?????????"; endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_25) - `Src2CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_25_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_25_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_25_string = "PC "; - default : _zz_25_string = "???"; + case(_zz_40) + `Src2CtrlEnum_defaultEncoding_RS : _zz_40_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_40_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_40_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_40_string = "PC "; + default : _zz_40_string = "???"; endcase end always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_41) + `Src1CtrlEnum_defaultEncoding_RS : _zz_41_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_41_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_41_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_41_string = "URS1 "; + default : _zz_41_string = "????????????"; endcase end always @(*) begin @@ -1565,11 +1854,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_28) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_28_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_28_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_28_string = "BITWISE "; - default : _zz_28_string = "????????"; + case(_zz_42) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_42_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_42_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_42_string = "BITWISE "; + default : _zz_42_string = "????????"; endcase end always @(*) begin @@ -1581,145 +1870,163 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_29) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_29_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_29_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_29_string = "AND_1"; - default : _zz_29_string = "?????"; + case(_zz_43) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; + default : _zz_43_string = "?????"; endcase end always @(*) begin - case(_zz_33) - `Input2Kind_defaultEncoding_RS : _zz_33_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_33_string = "IMM_I"; - default : _zz_33_string = "?????"; + case(_zz_47) + `Input2Kind_defaultEncoding_RS : _zz_47_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_47_string = "IMM_I"; + default : _zz_47_string = "?????"; endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; + case(_zz_48) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_48_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_48_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_48_string = "ECALL"; + default : _zz_48_string = "?????"; endcase end always @(*) begin - case(_zz_35) - `BranchCtrlEnum_defaultEncoding_INC : _zz_35_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_35_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_35_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_35_string = "JALR"; - default : _zz_35_string = "????"; + case(_zz_49) + `BranchCtrlEnum_defaultEncoding_INC : _zz_49_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_49_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_49_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_49_string = "JALR"; + default : _zz_49_string = "????"; endcase end always @(*) begin - case(_zz_36) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_36_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_36_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_36_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_36_string = "SRA_1 "; - default : _zz_36_string = "?????????"; + case(_zz_50) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_50_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_50_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_50_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_50_string = "SRA_1 "; + default : _zz_50_string = "?????????"; endcase end always @(*) begin - case(_zz_37) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_37_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_37_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_37_string = "AND_1"; - default : _zz_37_string = "?????"; + case(_zz_51) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_51_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_51_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_51_string = "AND_1"; + default : _zz_51_string = "?????"; endcase end always @(*) begin - case(_zz_38) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; - default : _zz_38_string = "????????"; + case(_zz_52) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_52_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_52_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_52_string = "BITWISE "; + default : _zz_52_string = "????????"; endcase end always @(*) begin - case(_zz_39) - `Src2CtrlEnum_defaultEncoding_RS : _zz_39_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_39_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_39_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_39_string = "PC "; - default : _zz_39_string = "???"; + case(_zz_53) + `Src2CtrlEnum_defaultEncoding_RS : _zz_53_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_53_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_53_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_53_string = "PC "; + default : _zz_53_string = "???"; endcase end always @(*) begin - case(_zz_40) - `Src1CtrlEnum_defaultEncoding_RS : _zz_40_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_40_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_40_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_40_string = "URS1 "; - default : _zz_40_string = "????????????"; + case(_zz_54) + `Src1CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_54_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54_string = "URS1 "; + default : _zz_54_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_87) + `Src1CtrlEnum_defaultEncoding_RS : _zz_87_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_87_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_87_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_87_string = "URS1 "; + default : _zz_87_string = "????????????"; endcase end always @(*) begin - case(_zz_72) - `Src1CtrlEnum_defaultEncoding_RS : _zz_72_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_72_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_72_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_72_string = "URS1 "; - default : _zz_72_string = "????????????"; + case(_zz_88) + `Src2CtrlEnum_defaultEncoding_RS : _zz_88_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_88_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_88_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_88_string = "PC "; + default : _zz_88_string = "???"; endcase end always @(*) begin - case(_zz_73) - `Src2CtrlEnum_defaultEncoding_RS : _zz_73_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_73_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_73_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_73_string = "PC "; - default : _zz_73_string = "???"; + case(_zz_89) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_89_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_89_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_89_string = "BITWISE "; + default : _zz_89_string = "????????"; endcase end always @(*) begin - case(_zz_74) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_74_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_74_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_74_string = "BITWISE "; - default : _zz_74_string = "????????"; + case(_zz_90) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_90_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_90_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_90_string = "AND_1"; + default : _zz_90_string = "?????"; endcase end always @(*) begin - case(_zz_75) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_75_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_75_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_75_string = "AND_1"; - default : _zz_75_string = "?????"; + case(_zz_91) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_91_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_91_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_91_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_91_string = "SRA_1 "; + default : _zz_91_string = "?????????"; endcase end always @(*) begin - case(_zz_76) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_76_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_76_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_76_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_76_string = "SRA_1 "; - default : _zz_76_string = "?????????"; + case(_zz_92) + `BranchCtrlEnum_defaultEncoding_INC : _zz_92_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_92_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_92_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_92_string = "JALR"; + default : _zz_92_string = "????"; endcase end always @(*) begin - case(_zz_77) - `BranchCtrlEnum_defaultEncoding_INC : _zz_77_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_77_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_77_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_77_string = "JALR"; - default : _zz_77_string = "????"; + case(_zz_93) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_93_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_93_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_93_string = "ECALL"; + default : _zz_93_string = "?????"; endcase end always @(*) begin - case(_zz_78) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_78_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_78_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_78_string = "ECALL"; - default : _zz_78_string = "?????"; + case(_zz_94) + `Input2Kind_defaultEncoding_RS : _zz_94_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_94_string = "IMM_I"; + default : _zz_94_string = "?????"; endcase end always @(*) begin - case(_zz_79) - `Input2Kind_defaultEncoding_RS : _zz_79_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_79_string = "IMM_I"; - default : _zz_79_string = "?????"; + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin @@ -1764,6 +2071,22 @@ module VexRiscv ( default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; @@ -1773,108 +2096,168 @@ module VexRiscv ( end `endif + assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_96; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); - assign decode_SRC2 = _zz_87; - assign decode_SRC1 = _zz_82; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign decode_IS_RS2_SIGNED = _zz_170[0]; - assign decode_IS_RS1_SIGNED = _zz_171[0]; - assign decode_IS_MUL = _zz_172[0]; + assign decode_IS_RS2_SIGNED = _zz_185[0]; + assign decode_IS_RS1_SIGNED = _zz_186[0]; + assign decode_IS_MUL = _zz_187[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_173[0]; - assign decode_ENV_CTRL = _zz_4; - assign _zz_5 = _zz_6; - assign decode_IS_CSR = _zz_174[0]; - assign decode_BRANCH_CTRL = _zz_7; - assign _zz_8 = _zz_9; - assign decode_SHIFT_CTRL = _zz_10; - assign _zz_11 = _zz_12; - assign decode_ALU_BITWISE_CTRL = _zz_13; - assign _zz_14 = _zz_15; - assign decode_SRC_LESS_UNSIGNED = _zz_175[0]; - assign decode_ALU_CTRL = _zz_16; - assign _zz_17 = _zz_18; - assign decode_MEMORY_STORE = _zz_176[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_188[0]; + assign _zz_4 = _zz_5; + assign _zz_6 = _zz_7; + assign decode_ENV_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_IS_CSR = _zz_189[0]; + assign decode_BRANCH_CTRL = _zz_11; + assign _zz_12 = _zz_13; + assign decode_SHIFT_CTRL = _zz_14; + assign _zz_15 = _zz_16; + assign decode_ALU_BITWISE_CTRL = _zz_17; + assign _zz_18 = _zz_19; + assign decode_SRC_LESS_UNSIGNED = _zz_190[0]; + assign decode_ALU_CTRL = _zz_20; + assign _zz_21 = _zz_22; + assign decode_MEMORY_STORE = _zz_191[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_192[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_193[0]; + assign decode_SRC2_CTRL = _zz_23; + assign _zz_24 = _zz_25; + assign decode_SRC1_CTRL = _zz_26; + assign _zz_27 = _zz_28; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_19; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + always @ (*) begin + _zz_29 = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck)begin + _zz_29 = 1'b0; + end + end + + always @ (*) begin + _zz_30 = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck)begin + _zz_30 = 1'b0; + end + end + + always @ (*) begin + _zz_31 = memory_REGFILE_WRITE_DATA; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_31 = memory_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_156)begin + _zz_31 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign execute_ENV_CTRL = _zz_20; + assign memory_ENV_CTRL = _zz_33; + assign execute_ENV_CTRL = _zz_34; + assign writeBack_ENV_CTRL = _zz_35; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_95; + assign execute_BRANCH_DO = _zz_110; + assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_21; - assign decode_RS2_USE = _zz_177[0]; - assign decode_RS1_USE = _zz_178[0]; + assign execute_BRANCH_CTRL = _zz_36; + assign decode_RS2_USE = _zz_194[0]; + assign decode_RS1_USE = _zz_195[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; - assign execute_SHIFT_CTRL = _zz_22; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_37 = execute_REGFILE_WRITE_DATA; + if(_zz_157)begin + _zz_37 = _zz_103; + end + if(_zz_158)begin + _zz_37 = execute_CsrPlugin_readData; + end + end + + assign execute_SHIFT_CTRL = _zz_38; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_23 = decode_PC; - assign _zz_24 = decode_RS2; - assign decode_SRC2_CTRL = _zz_25; - assign _zz_26 = decode_RS1; - assign decode_SRC1_CTRL = _zz_27; - assign decode_SRC_USE_SUB_LESS = _zz_179[0]; - assign decode_SRC_ADD_ZERO = _zz_180[0]; + assign _zz_39 = execute_PC; + assign execute_SRC2_CTRL = _zz_40; + assign execute_SRC1_CTRL = _zz_41; + assign decode_SRC_USE_SUB_LESS = _zz_196[0]; + assign decode_SRC_ADD_ZERO = _zz_197[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_28; - assign execute_SRC2 = decode_to_execute_SRC2; - assign execute_SRC1 = decode_to_execute_SRC1; - assign execute_ALU_BITWISE_CTRL = _zz_29; - assign _zz_30 = execute_INSTRUCTION; - assign _zz_31 = execute_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_32 = 1'b0; + assign execute_ALU_CTRL = _zz_42; + assign execute_SRC2 = _zz_102; + assign execute_SRC1 = _zz_97; + assign execute_ALU_BITWISE_CTRL = _zz_43; + assign _zz_44 = writeBack_INSTRUCTION; + assign _zz_45 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_46 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_32 = 1'b1; + _zz_46 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_181[0]; + decode_REGFILE_WRITE_VALID = _zz_198[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_229) == 32'h00000003),{(_zz_230 == _zz_231),{_zz_232,{_zz_233,_zz_234}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_247) == 32'h00000003),{(_zz_248 == _zz_249),{_zz_250,{_zz_251,_zz_252}}}}}}} != 22'h0); + assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin - _zz_41 = execute_REGFILE_WRITE_DATA; - if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin - _zz_41 = execute_DBusSimplePlugin_rspFormated; - end - if(_zz_146)begin - _zz_41 = _zz_88; - end - if(_zz_147)begin - _zz_41 = execute_CsrPlugin_readData; - end - if(execute_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_41 = execute_CfuPlugin_rsp_payload_outputs_0; - end - if(_zz_148)begin - _zz_41 = ((execute_INSTRUCTION[13 : 12] == 2'b00) ? execute_MulDivIterativePlugin_accumulator[31 : 0] : execute_MulDivIterativePlugin_accumulator[63 : 32]); - end - end - - assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; - assign execute_MEMORY_READ_DATA = dBus_rsp_data; - assign execute_REGFILE_WRITE_DATA = _zz_81; + _zz_55 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_55 = writeBack_DBusSimplePlugin_rspFormated; + end + end + + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; + assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; + assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; + assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; + assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; + assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; + assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; + assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; + assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; + assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; + assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; + assign memory_PC = execute_to_memory_PC; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; @@ -1887,29 +2270,44 @@ module VexRiscv ( assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = 1'b0; - assign decode_MEMORY_ENABLE = _zz_182[0]; - assign decode_FLUSH_ALL = _zz_183[0]; + assign decode_MEMORY_ENABLE = _zz_199[0]; + assign decode_FLUSH_ALL = _zz_200[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_149)begin + if(_zz_159)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_150)begin + if(_zz_160)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_56 = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_56 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_57 = memory_FORMAL_PC_NEXT; + if(DBusSimplePlugin_redoBranch_valid)begin + _zz_57 = DBusSimplePlugin_redoBranch_payload; + end + end + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; - assign execute_PC = decode_to_execute_PC; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin decode_arbitration_haltItself = 1'b0; if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin @@ -1919,13 +2317,13 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_89 || _zz_90)))begin + if((decode_arbitration_isValid && (_zz_104 || _zz_105)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin decode_arbitration_haltByOther = 1'b1; end - if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != 1'b0))begin + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin decode_arbitration_haltByOther = 1'b1; end end @@ -1950,18 +2348,15 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_56)))begin - execute_arbitration_haltItself = 1'b1; - end - if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && ((! dBus_rsp_ready) || (! _zz_56))))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_72)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_146)begin + if(_zz_157)begin if((! execute_LightShifterPlugin_done))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_147)begin + if(_zz_158)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -1969,25 +2364,12 @@ module VexRiscv ( if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin execute_arbitration_haltItself = 1'b1; end - if(execute_CfuPlugin_CFU_IN_FLIGHT)begin - if((! execute_CfuPlugin_rsp_valid))begin - execute_arbitration_haltItself = 1'b1; - end - end - if(_zz_148)begin - if(((! execute_MulDivIterativePlugin_frontendOk) || (! execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin - execute_arbitration_haltItself = 1'b1; - end - if(_zz_151)begin - execute_arbitration_haltItself = 1'b1; - end - end end assign execute_arbitration_haltByOther = 1'b0; always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_152)begin + if(CsrPlugin_selfException_valid)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -1995,45 +2377,98 @@ module VexRiscv ( end end + assign execute_arbitration_flushIt = 1'b0; always @ (*) begin - execute_arbitration_flushIt = 1'b0; + execute_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(CsrPlugin_selfException_valid)begin + execute_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + memory_arbitration_haltItself = 1'b1; + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if((! memory_CfuPlugin_rsp_valid))begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_156)begin + if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + memory_arbitration_haltItself = 1'b1; + end + if(_zz_161)begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(_zz_162)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushIt = 1'b0; + if(DBusSimplePlugin_redoBranch_valid)begin + memory_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_flushNext = 1'b0; if(DBusSimplePlugin_redoBranch_valid)begin - execute_arbitration_flushIt = 1'b1; + memory_arbitration_flushNext = 1'b1; + end + if(_zz_162)begin + memory_arbitration_flushNext = 1'b1; + end + end + + assign writeBack_arbitration_haltItself = 1'b0; + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; end end + assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin - execute_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - execute_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_jumpInterface_valid)begin - execute_arbitration_flushNext = 1'b1; - end - if(_zz_152)begin - execute_arbitration_flushNext = 1'b1; - end - if(_zz_153)begin - execute_arbitration_flushNext = 1'b1; + writeBack_arbitration_flushNext = 1'b0; + if(_zz_163)begin + writeBack_arbitration_flushNext = 1'b1; end - if(_zz_154)begin - execute_arbitration_flushNext = 1'b1; + if(_zz_164)begin + writeBack_arbitration_flushNext = 1'b1; end end - assign lastStageInstruction = execute_INSTRUCTION; - assign lastStagePc = execute_PC; - assign lastStageIsValid = execute_arbitration_isValid; - assign lastStageIsFiring = execute_arbitration_isFiring; + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; always @ (*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode} != 2'b00))begin + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_153)begin + if(_zz_163)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_154)begin + if(_zz_164)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -2049,21 +2484,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_153)begin + if(_zz_163)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_154)begin + if(_zz_164)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_153)begin + if(_zz_163)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_154)begin - case(_zz_155) + if(_zz_164)begin + case(_zz_165) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2076,13 +2511,13 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; - assign IBusCachedPlugin_externalFlush = ({execute_arbitration_flushNext,decode_arbitration_flushNext} != 2'b00); + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); - assign _zz_42 = {BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}}; - assign _zz_43 = (_zz_42 & (~ _zz_184)); - assign _zz_44 = _zz_43[1]; - assign _zz_45 = _zz_43[2]; - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_143; + assign _zz_58 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; + assign _zz_59 = (_zz_58 & (~ _zz_201)); + assign _zz_60 = _zz_59[1]; + assign _zz_61 = _zz_59[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_155; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -2102,7 +2537,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_186); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_203); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -2142,9 +2577,9 @@ module VexRiscv ( end end - assign _zz_46 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_46); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_46); + assign _zz_62 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_62); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_62); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; @@ -2153,9 +2588,9 @@ module VexRiscv ( end end - assign _zz_47 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_47); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_47); + assign _zz_63 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_63); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_63); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; @@ -2164,22 +2599,22 @@ module VexRiscv ( end end - assign _zz_48 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_48); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_48); + assign _zz_64 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_64); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_64); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_49; - assign _zz_49 = ((1'b0 && (! _zz_50)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_50 = _zz_51; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_50; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_65; + assign _zz_65 = ((1'b0 && (! _zz_66)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_66 = _zz_67; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_66; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_52)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_52 = _zz_53; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_52; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_54; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_68)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_68 = _zz_69; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_68; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_70; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -2189,6 +2624,8 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; @@ -2199,33 +2636,33 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_133 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_134 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_135 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_134; + assign _zz_145 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_146 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_147 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_146; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_137 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_138 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_139 = (CsrPlugin_privilege == 2'b00); + assign _zz_149 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_150 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_151 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_150)begin + if(_zz_160)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_149)begin + if(_zz_159)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_140 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_149)begin - _zz_140 = 1'b1; + _zz_152 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_159)begin + _zz_152 = 1'b1; end end @@ -2233,7 +2670,8 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_132 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_144 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_72 = 1'b0; always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin @@ -2244,39 +2682,39 @@ module VexRiscv ( end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_56)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_72)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_57 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_73 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_57 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_73 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_57 = execute_RS2[31 : 0]; + _zz_73 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_57; + assign dBus_cmd_payload_data = _zz_73; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_58 = 4'b0001; + _zz_74 = 4'b0001; end 2'b01 : begin - _zz_58 = 4'b0011; + _zz_74 = 4'b0011; end default : begin - _zz_58 = 4'b1111; + _zz_74 = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_58 <<< dBus_cmd_payload_address[1 : 0]); + assign execute_DBusSimplePlugin_formalMask = (_zz_74 <<< dBus_cmd_payload_address[1 : 0]); assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; @@ -2285,116 +2723,116 @@ module VexRiscv ( assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; always @ (*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(execute_MMU_RSP2_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end else begin - if(execute_MMU_FAULT)begin + if(memory_MMU_FAULT)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_156)begin + if(_zz_166)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end always @ (*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(! execute_MMU_RSP2_refilling) begin - if(execute_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (execute_MEMORY_STORE ? 4'b1111 : 4'b1101); + if(! memory_MMU_RSP2_refilling) begin + if(memory_MMU_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); end end end - assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA; + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; always @ (*) begin DBusSimplePlugin_redoBranch_valid = 1'b0; - if(execute_MMU_RSP2_refilling)begin + if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_156)begin + if(_zz_166)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end - assign DBusSimplePlugin_redoBranch_payload = execute_PC; + assign DBusSimplePlugin_redoBranch_payload = memory_PC; always @ (*) begin - execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; - case(execute_MEMORY_ADDRESS_LOW) + writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8]; + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; end 2'b10 : begin - execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16]; + writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; end 2'b11 : begin - execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24]; + writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; end default : begin end endcase end - assign _zz_59 = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); - always @ (*) begin - _zz_60[31] = _zz_59; - _zz_60[30] = _zz_59; - _zz_60[29] = _zz_59; - _zz_60[28] = _zz_59; - _zz_60[27] = _zz_59; - _zz_60[26] = _zz_59; - _zz_60[25] = _zz_59; - _zz_60[24] = _zz_59; - _zz_60[23] = _zz_59; - _zz_60[22] = _zz_59; - _zz_60[21] = _zz_59; - _zz_60[20] = _zz_59; - _zz_60[19] = _zz_59; - _zz_60[18] = _zz_59; - _zz_60[17] = _zz_59; - _zz_60[16] = _zz_59; - _zz_60[15] = _zz_59; - _zz_60[14] = _zz_59; - _zz_60[13] = _zz_59; - _zz_60[12] = _zz_59; - _zz_60[11] = _zz_59; - _zz_60[10] = _zz_59; - _zz_60[9] = _zz_59; - _zz_60[8] = _zz_59; - _zz_60[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_61 = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); - always @ (*) begin - _zz_62[31] = _zz_61; - _zz_62[30] = _zz_61; - _zz_62[29] = _zz_61; - _zz_62[28] = _zz_61; - _zz_62[27] = _zz_61; - _zz_62[26] = _zz_61; - _zz_62[25] = _zz_61; - _zz_62[24] = _zz_61; - _zz_62[23] = _zz_61; - _zz_62[22] = _zz_61; - _zz_62[21] = _zz_61; - _zz_62[20] = _zz_61; - _zz_62[19] = _zz_61; - _zz_62[18] = _zz_61; - _zz_62[17] = _zz_61; - _zz_62[16] = _zz_61; - _zz_62[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_168) + assign _zz_75 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_76[31] = _zz_75; + _zz_76[30] = _zz_75; + _zz_76[29] = _zz_75; + _zz_76[28] = _zz_75; + _zz_76[27] = _zz_75; + _zz_76[26] = _zz_75; + _zz_76[25] = _zz_75; + _zz_76[24] = _zz_75; + _zz_76[23] = _zz_75; + _zz_76[22] = _zz_75; + _zz_76[21] = _zz_75; + _zz_76[20] = _zz_75; + _zz_76[19] = _zz_75; + _zz_76[18] = _zz_75; + _zz_76[17] = _zz_75; + _zz_76[16] = _zz_75; + _zz_76[15] = _zz_75; + _zz_76[14] = _zz_75; + _zz_76[13] = _zz_75; + _zz_76[12] = _zz_75; + _zz_76[11] = _zz_75; + _zz_76[10] = _zz_75; + _zz_76[9] = _zz_75; + _zz_76[8] = _zz_75; + _zz_76[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_77 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_78[31] = _zz_77; + _zz_78[30] = _zz_77; + _zz_78[29] = _zz_77; + _zz_78[28] = _zz_77; + _zz_78[27] = _zz_77; + _zz_78[26] = _zz_77; + _zz_78[25] = _zz_77; + _zz_78[24] = _zz_77; + _zz_78[23] = _zz_77; + _zz_78[22] = _zz_77; + _zz_78[21] = _zz_77; + _zz_78[20] = _zz_77; + _zz_78[19] = _zz_77; + _zz_78[18] = _zz_77; + _zz_78[17] = _zz_77; + _zz_78[16] = _zz_77; + _zz_78[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_183) 2'b00 : begin - execute_DBusSimplePlugin_rspFormated = _zz_60; + writeBack_DBusSimplePlugin_rspFormated = _zz_76; end 2'b01 : begin - execute_DBusSimplePlugin_rspFormated = _zz_62; + writeBack_DBusSimplePlugin_rspFormated = _zz_78; end default : begin - execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; + writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; end endcase end @@ -2417,55 +2855,54 @@ module VexRiscv ( assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_64 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_65 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_66 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_67 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); - assign _zz_68 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_69 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_70 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_71 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00001000); - assign _zz_63 = {(_zz_71 != 1'b0),{({_zz_71,_zz_70} != 2'b00),{((_zz_247 == _zz_248) != 1'b0),{1'b0,{(_zz_249 != _zz_250),{_zz_251,{_zz_252,_zz_253}}}}}}}; - assign _zz_72 = _zz_63[2 : 1]; - assign _zz_40 = _zz_72; - assign _zz_73 = _zz_63[7 : 6]; - assign _zz_39 = _zz_73; - assign _zz_74 = _zz_63[14 : 13]; - assign _zz_38 = _zz_74; - assign _zz_75 = _zz_63[17 : 16]; - assign _zz_37 = _zz_75; - assign _zz_76 = _zz_63[20 : 19]; - assign _zz_36 = _zz_76; - assign _zz_77 = _zz_63[23 : 22]; - assign _zz_35 = _zz_77; - assign _zz_78 = _zz_63[26 : 25]; - assign _zz_34 = _zz_78; - assign _zz_79 = _zz_63[28 : 28]; - assign _zz_33 = _zz_79; + assign _zz_80 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_81 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_82 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_83 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_84 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_85 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_86 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00001000); + assign _zz_79 = {(_zz_86 != 1'b0),{({_zz_86,_zz_85} != 2'b00),{((_zz_265 == _zz_266) != 1'b0),{1'b0,{(_zz_267 != _zz_268),{_zz_269,{_zz_270,_zz_271}}}}}}}; + assign _zz_87 = _zz_79[2 : 1]; + assign _zz_54 = _zz_87; + assign _zz_88 = _zz_79[7 : 6]; + assign _zz_53 = _zz_88; + assign _zz_89 = _zz_79[14 : 13]; + assign _zz_52 = _zz_89; + assign _zz_90 = _zz_79[17 : 16]; + assign _zz_51 = _zz_90; + assign _zz_91 = _zz_79[20 : 19]; + assign _zz_50 = _zz_91; + assign _zz_92 = _zz_79[23 : 22]; + assign _zz_49 = _zz_92; + assign _zz_93 = _zz_79[26 : 25]; + assign _zz_48 = _zz_93; + assign _zz_94 = _zz_79[28 : 28]; + assign _zz_47 = _zz_94; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_141; - assign decode_RegFilePlugin_rs2Data = _zz_142; + assign decode_RegFilePlugin_rs1Data = _zz_153; + assign decode_RegFilePlugin_rs2Data = _zz_154; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_31 && execute_arbitration_isFiring); - if(_zz_80)begin + lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); + if(_zz_95)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_30[11 : 7]; - if(_zz_80)begin + lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; + if(_zz_95)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_41; - if(_zz_80)begin + lastStageRegFileWrite_payload_data = _zz_55; + if(_zz_95)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -2487,101 +2924,101 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_81 = execute_IntAluPlugin_bitwise; + _zz_96 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_81 = {31'd0, _zz_187}; + _zz_96 = {31'd0, _zz_204}; end default : begin - _zz_81 = execute_SRC_ADD_SUB; + _zz_96 = execute_SRC_ADD_SUB; end endcase end always @ (*) begin - case(decode_SRC1_CTRL) + case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_82 = _zz_26; + _zz_97 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_82 = {29'd0, _zz_188}; + _zz_97 = {29'd0, _zz_205}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_82 = {decode_INSTRUCTION[31 : 12],12'h0}; + _zz_97 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_82 = {27'd0, _zz_189}; - end - endcase - end - - assign _zz_83 = _zz_190[11]; - always @ (*) begin - _zz_84[19] = _zz_83; - _zz_84[18] = _zz_83; - _zz_84[17] = _zz_83; - _zz_84[16] = _zz_83; - _zz_84[15] = _zz_83; - _zz_84[14] = _zz_83; - _zz_84[13] = _zz_83; - _zz_84[12] = _zz_83; - _zz_84[11] = _zz_83; - _zz_84[10] = _zz_83; - _zz_84[9] = _zz_83; - _zz_84[8] = _zz_83; - _zz_84[7] = _zz_83; - _zz_84[6] = _zz_83; - _zz_84[5] = _zz_83; - _zz_84[4] = _zz_83; - _zz_84[3] = _zz_83; - _zz_84[2] = _zz_83; - _zz_84[1] = _zz_83; - _zz_84[0] = _zz_83; - end - - assign _zz_85 = _zz_191[11]; - always @ (*) begin - _zz_86[19] = _zz_85; - _zz_86[18] = _zz_85; - _zz_86[17] = _zz_85; - _zz_86[16] = _zz_85; - _zz_86[15] = _zz_85; - _zz_86[14] = _zz_85; - _zz_86[13] = _zz_85; - _zz_86[12] = _zz_85; - _zz_86[11] = _zz_85; - _zz_86[10] = _zz_85; - _zz_86[9] = _zz_85; - _zz_86[8] = _zz_85; - _zz_86[7] = _zz_85; - _zz_86[6] = _zz_85; - _zz_86[5] = _zz_85; - _zz_86[4] = _zz_85; - _zz_86[3] = _zz_85; - _zz_86[2] = _zz_85; - _zz_86[1] = _zz_85; - _zz_86[0] = _zz_85; + _zz_97 = {27'd0, _zz_206}; + end + endcase end + assign _zz_98 = _zz_207[11]; always @ (*) begin - case(decode_SRC2_CTRL) + _zz_99[19] = _zz_98; + _zz_99[18] = _zz_98; + _zz_99[17] = _zz_98; + _zz_99[16] = _zz_98; + _zz_99[15] = _zz_98; + _zz_99[14] = _zz_98; + _zz_99[13] = _zz_98; + _zz_99[12] = _zz_98; + _zz_99[11] = _zz_98; + _zz_99[10] = _zz_98; + _zz_99[9] = _zz_98; + _zz_99[8] = _zz_98; + _zz_99[7] = _zz_98; + _zz_99[6] = _zz_98; + _zz_99[5] = _zz_98; + _zz_99[4] = _zz_98; + _zz_99[3] = _zz_98; + _zz_99[2] = _zz_98; + _zz_99[1] = _zz_98; + _zz_99[0] = _zz_98; + end + + assign _zz_100 = _zz_208[11]; + always @ (*) begin + _zz_101[19] = _zz_100; + _zz_101[18] = _zz_100; + _zz_101[17] = _zz_100; + _zz_101[16] = _zz_100; + _zz_101[15] = _zz_100; + _zz_101[14] = _zz_100; + _zz_101[13] = _zz_100; + _zz_101[12] = _zz_100; + _zz_101[11] = _zz_100; + _zz_101[10] = _zz_100; + _zz_101[9] = _zz_100; + _zz_101[8] = _zz_100; + _zz_101[7] = _zz_100; + _zz_101[6] = _zz_100; + _zz_101[5] = _zz_100; + _zz_101[4] = _zz_100; + _zz_101[3] = _zz_100; + _zz_101[2] = _zz_100; + _zz_101[1] = _zz_100; + _zz_101[0] = _zz_100; + end + + always @ (*) begin + case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_87 = _zz_24; + _zz_102 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_87 = {_zz_84,decode_INSTRUCTION[31 : 20]}; + _zz_102 = {_zz_99,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_87 = {_zz_86,{decode_INSTRUCTION[31 : 25],decode_INSTRUCTION[11 : 7]}}; + _zz_102 = {_zz_101,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_87 = _zz_23; + _zz_102 = _zz_39; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_192; + execute_SrcPlugin_addSub = _zz_209; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -2590,166 +3027,194 @@ module VexRiscv ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); - assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); always @ (*) begin case(execute_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_88 = (execute_LightShifterPlugin_shiftInput <<< 1); + _zz_103 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_88 = _zz_199; + _zz_103 = _zz_216; end endcase end always @ (*) begin - _zz_89 = 1'b0; - if(_zz_91)begin - if((_zz_92 == decode_INSTRUCTION[19 : 15]))begin - _zz_89 = 1'b1; + _zz_104 = 1'b0; + if(_zz_106)begin + if((_zz_107 == decode_INSTRUCTION[19 : 15]))begin + _zz_104 = 1'b1; end end - if(_zz_157)begin - if(_zz_158)begin + if(_zz_167)begin + if(_zz_168)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_104 = 1'b1; + end + end + end + if(_zz_169)begin + if(_zz_170)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin + _zz_104 = 1'b1; + end + end + end + if(_zz_171)begin + if(_zz_172)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_89 = 1'b1; + _zz_104 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_89 = 1'b0; + _zz_104 = 1'b0; end end always @ (*) begin - _zz_90 = 1'b0; - if(_zz_91)begin - if((_zz_92 == decode_INSTRUCTION[24 : 20]))begin - _zz_90 = 1'b1; + _zz_105 = 1'b0; + if(_zz_106)begin + if((_zz_107 == decode_INSTRUCTION[24 : 20]))begin + _zz_105 = 1'b1; end end - if(_zz_157)begin - if(_zz_158)begin + if(_zz_167)begin + if(_zz_168)begin + if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_105 = 1'b1; + end + end + end + if(_zz_169)begin + if(_zz_170)begin + if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin + _zz_105 = 1'b1; + end + end + end + if(_zz_171)begin + if(_zz_172)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_90 = 1'b1; + _zz_105 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_90 = 1'b0; + _zz_105 = 1'b0; end end assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_93 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_93 == 3'b000)) begin - _zz_94 = execute_BranchPlugin_eq; - end else if((_zz_93 == 3'b001)) begin - _zz_94 = (! execute_BranchPlugin_eq); - end else if((((_zz_93 & 3'b101) == 3'b101))) begin - _zz_94 = (! execute_SRC_LESS); + assign _zz_108 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_108 == 3'b000)) begin + _zz_109 = execute_BranchPlugin_eq; + end else if((_zz_108 == 3'b001)) begin + _zz_109 = (! execute_BranchPlugin_eq); + end else if((((_zz_108 & 3'b101) == 3'b101))) begin + _zz_109 = (! execute_SRC_LESS); end else begin - _zz_94 = execute_SRC_LESS; + _zz_109 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_95 = 1'b0; + _zz_110 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_95 = 1'b1; + _zz_110 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_95 = 1'b1; + _zz_110 = 1'b1; end default : begin - _zz_95 = _zz_94; + _zz_110 = _zz_109; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_96 = _zz_201[19]; + assign _zz_111 = _zz_218[19]; always @ (*) begin - _zz_97[10] = _zz_96; - _zz_97[9] = _zz_96; - _zz_97[8] = _zz_96; - _zz_97[7] = _zz_96; - _zz_97[6] = _zz_96; - _zz_97[5] = _zz_96; - _zz_97[4] = _zz_96; - _zz_97[3] = _zz_96; - _zz_97[2] = _zz_96; - _zz_97[1] = _zz_96; - _zz_97[0] = _zz_96; + _zz_112[10] = _zz_111; + _zz_112[9] = _zz_111; + _zz_112[8] = _zz_111; + _zz_112[7] = _zz_111; + _zz_112[6] = _zz_111; + _zz_112[5] = _zz_111; + _zz_112[4] = _zz_111; + _zz_112[3] = _zz_111; + _zz_112[2] = _zz_111; + _zz_112[1] = _zz_111; + _zz_112[0] = _zz_111; end - assign _zz_98 = _zz_202[11]; + assign _zz_113 = _zz_219[11]; always @ (*) begin - _zz_99[19] = _zz_98; - _zz_99[18] = _zz_98; - _zz_99[17] = _zz_98; - _zz_99[16] = _zz_98; - _zz_99[15] = _zz_98; - _zz_99[14] = _zz_98; - _zz_99[13] = _zz_98; - _zz_99[12] = _zz_98; - _zz_99[11] = _zz_98; - _zz_99[10] = _zz_98; - _zz_99[9] = _zz_98; - _zz_99[8] = _zz_98; - _zz_99[7] = _zz_98; - _zz_99[6] = _zz_98; - _zz_99[5] = _zz_98; - _zz_99[4] = _zz_98; - _zz_99[3] = _zz_98; - _zz_99[2] = _zz_98; - _zz_99[1] = _zz_98; - _zz_99[0] = _zz_98; - end - - assign _zz_100 = _zz_203[11]; + _zz_114[19] = _zz_113; + _zz_114[18] = _zz_113; + _zz_114[17] = _zz_113; + _zz_114[16] = _zz_113; + _zz_114[15] = _zz_113; + _zz_114[14] = _zz_113; + _zz_114[13] = _zz_113; + _zz_114[12] = _zz_113; + _zz_114[11] = _zz_113; + _zz_114[10] = _zz_113; + _zz_114[9] = _zz_113; + _zz_114[8] = _zz_113; + _zz_114[7] = _zz_113; + _zz_114[6] = _zz_113; + _zz_114[5] = _zz_113; + _zz_114[4] = _zz_113; + _zz_114[3] = _zz_113; + _zz_114[2] = _zz_113; + _zz_114[1] = _zz_113; + _zz_114[0] = _zz_113; + end + + assign _zz_115 = _zz_220[11]; always @ (*) begin - _zz_101[18] = _zz_100; - _zz_101[17] = _zz_100; - _zz_101[16] = _zz_100; - _zz_101[15] = _zz_100; - _zz_101[14] = _zz_100; - _zz_101[13] = _zz_100; - _zz_101[12] = _zz_100; - _zz_101[11] = _zz_100; - _zz_101[10] = _zz_100; - _zz_101[9] = _zz_100; - _zz_101[8] = _zz_100; - _zz_101[7] = _zz_100; - _zz_101[6] = _zz_100; - _zz_101[5] = _zz_100; - _zz_101[4] = _zz_100; - _zz_101[3] = _zz_100; - _zz_101[2] = _zz_100; - _zz_101[1] = _zz_100; - _zz_101[0] = _zz_100; + _zz_116[18] = _zz_115; + _zz_116[17] = _zz_115; + _zz_116[16] = _zz_115; + _zz_116[15] = _zz_115; + _zz_116[14] = _zz_115; + _zz_116[13] = _zz_115; + _zz_116[12] = _zz_115; + _zz_116[11] = _zz_115; + _zz_116[10] = _zz_115; + _zz_116[9] = _zz_115; + _zz_116[8] = _zz_115; + _zz_116[7] = _zz_115; + _zz_116[6] = _zz_115; + _zz_116[5] = _zz_115; + _zz_116[4] = _zz_115; + _zz_116[3] = _zz_115; + _zz_116[2] = _zz_115; + _zz_116[1] = _zz_115; + _zz_116[0] = _zz_115; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_102 = {{_zz_97,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_117 = {{_zz_112,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_102 = {_zz_99,execute_INSTRUCTION[31 : 20]}; + _zz_117 = {_zz_114,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_102 = {{_zz_101,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_117 = {{_zz_116,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_102; + assign execute_BranchPlugin_branch_src2 = _zz_117; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; @@ -2762,16 +3227,13 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_103 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_104 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_105 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_118 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_119 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_120 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_106 = {CfuPlugin_joinException_valid,{CsrPlugin_selfException_valid,DBusSimplePlugin_memoryExceptionPort_valid}}; - assign _zz_107 = (_zz_106 & (~ _zz_204)); - assign _zz_108 = _zz_107[1]; - assign _zz_109 = _zz_107[2]; - assign _zz_110 = {_zz_109,_zz_108}; + assign _zz_121 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_122 = _zz_221[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; if(decodeExceptionPort_valid)begin @@ -2784,7 +3246,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_152)begin + if(CsrPlugin_selfException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -2792,14 +3254,33 @@ module VexRiscv ( end end + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(_zz_162)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException); + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); always @ (*) begin - CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_0; - if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != 1'b0))begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin CsrPlugin_pipelineLiberator_done = 1'b0; end if(CsrPlugin_hadException)begin @@ -2845,7 +3326,7 @@ module VexRiscv ( end assign contextSwitching = CsrPlugin_jumpInterface_valid; - assign execute_CsrPlugin_blockedBySideEffects = (1'b0 || 1'b0); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; if(execute_CsrPlugin_csr_768)begin @@ -2893,7 +3374,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_159)begin + if(_zz_173)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -2912,14 +3393,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_160)begin + if(_zz_174)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_160)begin + if(_zz_174)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -2934,14 +3415,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_159)begin + if(_zz_173)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_159)begin + if(_zz_173)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -2950,7 +3431,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_169) + case(_zz_184) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -2963,58 +3444,58 @@ module VexRiscv ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_205; + assign execute_CfuPlugin_functionsIds_0 = _zz_223; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_111 = _zz_206[7]; - always @ (*) begin - _zz_112[23] = _zz_111; - _zz_112[22] = _zz_111; - _zz_112[21] = _zz_111; - _zz_112[20] = _zz_111; - _zz_112[19] = _zz_111; - _zz_112[18] = _zz_111; - _zz_112[17] = _zz_111; - _zz_112[16] = _zz_111; - _zz_112[15] = _zz_111; - _zz_112[14] = _zz_111; - _zz_112[13] = _zz_111; - _zz_112[12] = _zz_111; - _zz_112[11] = _zz_111; - _zz_112[10] = _zz_111; - _zz_112[9] = _zz_111; - _zz_112[8] = _zz_111; - _zz_112[7] = _zz_111; - _zz_112[6] = _zz_111; - _zz_112[5] = _zz_111; - _zz_112[4] = _zz_111; - _zz_112[3] = _zz_111; - _zz_112[2] = _zz_111; - _zz_112[1] = _zz_111; - _zz_112[0] = _zz_111; + assign _zz_123 = _zz_224[7]; + always @ (*) begin + _zz_124[23] = _zz_123; + _zz_124[22] = _zz_123; + _zz_124[21] = _zz_123; + _zz_124[20] = _zz_123; + _zz_124[19] = _zz_123; + _zz_124[18] = _zz_123; + _zz_124[17] = _zz_123; + _zz_124[16] = _zz_123; + _zz_124[15] = _zz_123; + _zz_124[14] = _zz_123; + _zz_124[13] = _zz_123; + _zz_124[12] = _zz_123; + _zz_124[11] = _zz_123; + _zz_124[10] = _zz_123; + _zz_124[9] = _zz_123; + _zz_124[8] = _zz_123; + _zz_124[7] = _zz_123; + _zz_124[6] = _zz_123; + _zz_124[5] = _zz_123; + _zz_124[4] = _zz_123; + _zz_124[3] = _zz_123; + _zz_124[2] = _zz_123; + _zz_124[1] = _zz_123; + _zz_124[0] = _zz_123; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_113 = execute_RS2; + _zz_125 = execute_RS2; end default : begin - _zz_113 = {_zz_112,execute_INSTRUCTION[31 : 24]}; + _zz_125 = {_zz_124,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_113; - assign execute_CfuPlugin_rsp_valid = CfuPlugin_bus_rsp_valid; - assign CfuPlugin_bus_rsp_ready = execute_CfuPlugin_rsp_ready; - assign execute_CfuPlugin_rsp_payload_response_ok = CfuPlugin_bus_rsp_payload_response_ok; - assign execute_CfuPlugin_rsp_payload_outputs_0 = CfuPlugin_bus_rsp_payload_outputs_0; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_125; + assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); + assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); + assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); always @ (*) begin CfuPlugin_joinException_valid = 1'b0; - if(execute_CfuPlugin_CFU_IN_FLIGHT)begin - if(execute_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! execute_CfuPlugin_rsp_payload_response_ok); + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if(memory_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); end end end @@ -3022,180 +3503,199 @@ module VexRiscv ( assign CfuPlugin_joinException_payload_code = 4'b1111; assign CfuPlugin_joinException_payload_badAddr = 32'h0; always @ (*) begin - execute_CfuPlugin_rsp_ready = 1'b0; - if(execute_CfuPlugin_CFU_IN_FLIGHT)begin - execute_CfuPlugin_rsp_ready = (! execute_arbitration_isStuckByOthers); + memory_CfuPlugin_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); end end + assign memory_MulDivIterativePlugin_frontendOk = 1'b1; always @ (*) begin - execute_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_148)begin - if(_zz_151)begin - execute_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; + memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; + if(_zz_156)begin + if(_zz_161)begin + memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end end always @ (*) begin - execute_MulDivIterativePlugin_mul_counter_willClear = 1'b0; - if((! execute_arbitration_isStuck))begin - execute_MulDivIterativePlugin_mul_counter_willClear = 1'b1; + memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; end end - assign execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (execute_MulDivIterativePlugin_mul_counter_value == 6'h20); - assign execute_MulDivIterativePlugin_mul_counter_willOverflow = (execute_MulDivIterativePlugin_mul_counter_willOverflowIfInc && execute_MulDivIterativePlugin_mul_counter_willIncrement); + assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); + assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); always @ (*) begin - if(execute_MulDivIterativePlugin_mul_counter_willOverflow)begin - execute_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - execute_MulDivIterativePlugin_mul_counter_valueNext = (execute_MulDivIterativePlugin_mul_counter_value + _zz_208); - end - if(execute_MulDivIterativePlugin_mul_counter_willClear)begin - execute_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; - end - end - - assign _zz_114 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_115 = ((execute_IS_MUL && _zz_114) || 1'b0); - always @ (*) begin - _zz_116[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_116[31 : 0] = execute_RS1; - end - - assign _zz_118 = (_zz_117 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_118 != 32'h0); - assign _zz_27 = _zz_40; - assign _zz_25 = _zz_39; - assign _zz_18 = decode_ALU_CTRL; - assign _zz_16 = _zz_38; - assign _zz_28 = decode_to_execute_ALU_CTRL; - assign _zz_15 = decode_ALU_BITWISE_CTRL; - assign _zz_13 = _zz_37; - assign _zz_29 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_12 = decode_SHIFT_CTRL; - assign _zz_10 = _zz_36; - assign _zz_22 = decode_to_execute_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_7 = _zz_35; - assign _zz_21 = decode_to_execute_BRANCH_CTRL; - assign _zz_6 = decode_ENV_CTRL; - assign _zz_4 = _zz_34; - assign _zz_20 = decode_to_execute_ENV_CTRL; + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_226); + end + if(memory_MulDivIterativePlugin_mul_counter_willClear)begin + memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; + end + end + + assign _zz_126 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_127 = ((execute_IS_MUL && _zz_126) || 1'b0); + always @ (*) begin + _zz_128[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_128[31 : 0] = execute_RS1; + end + + assign _zz_130 = (_zz_129 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_130 != 32'h0); + assign _zz_28 = decode_SRC1_CTRL; + assign _zz_26 = _zz_54; + assign _zz_41 = decode_to_execute_SRC1_CTRL; + assign _zz_25 = decode_SRC2_CTRL; + assign _zz_23 = _zz_53; + assign _zz_40 = decode_to_execute_SRC2_CTRL; + assign _zz_22 = decode_ALU_CTRL; + assign _zz_20 = _zz_52; + assign _zz_42 = decode_to_execute_ALU_CTRL; + assign _zz_19 = decode_ALU_BITWISE_CTRL; + assign _zz_17 = _zz_51; + assign _zz_43 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_16 = decode_SHIFT_CTRL; + assign _zz_14 = _zz_50; + assign _zz_38 = decode_to_execute_SHIFT_CTRL; + assign _zz_13 = decode_BRANCH_CTRL; + assign _zz_11 = _zz_49; + assign _zz_36 = decode_to_execute_BRANCH_CTRL; + assign _zz_10 = decode_ENV_CTRL; + assign _zz_7 = execute_ENV_CTRL; + assign _zz_5 = memory_ENV_CTRL; + assign _zz_8 = _zz_48; + assign _zz_34 = decode_to_execute_ENV_CTRL; + assign _zz_33 = execute_to_memory_ENV_CTRL; + assign _zz_35 = memory_to_writeBack_ENV_CTRL; assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_33; - assign _zz_19 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; - assign decode_arbitration_isFlushed = ((execute_arbitration_flushNext != 1'b0) || ({execute_arbitration_flushIt,decode_arbitration_flushIt} != 2'b00)); - assign execute_arbitration_isFlushed = (1'b0 || (execute_arbitration_flushIt != 1'b0)); - assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); + assign _zz_1 = _zz_47; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); - assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_119 = 32'h0; + _zz_131 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_119[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_119[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_119[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_131[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_131[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_131[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_120 = 32'h0; + _zz_132 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_120[11 : 11] = CsrPlugin_mip_MEIP; - _zz_120[7 : 7] = CsrPlugin_mip_MTIP; - _zz_120[3 : 3] = CsrPlugin_mip_MSIP; + _zz_132[11 : 11] = CsrPlugin_mip_MEIP; + _zz_132[7 : 7] = CsrPlugin_mip_MTIP; + _zz_132[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_121 = 32'h0; + _zz_133 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_121[11 : 11] = CsrPlugin_mie_MEIE; - _zz_121[7 : 7] = CsrPlugin_mie_MTIE; - _zz_121[3 : 3] = CsrPlugin_mie_MSIE; + _zz_133[11 : 11] = CsrPlugin_mie_MEIE; + _zz_133[7 : 7] = CsrPlugin_mie_MTIE; + _zz_133[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_122 = 32'h0; + _zz_134 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_122[31 : 0] = CsrPlugin_mepc; + _zz_134[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_123 = 32'h0; + _zz_135 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_123[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_123[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_135[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_135[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_124 = 32'h0; + _zz_136 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_124[31 : 0] = CsrPlugin_mtval; + _zz_136[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_125 = 32'h0; + _zz_137 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_125[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_137[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_126 = 32'h0; + _zz_138 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_126[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_138[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_127 = 32'h0; + _zz_139 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_127[31 : 0] = _zz_117; + _zz_139[31 : 0] = _zz_129; end end always @ (*) begin - _zz_128 = 32'h0; + _zz_140 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_128[31 : 0] = _zz_118; + _zz_140[31 : 0] = _zz_130; end end - assign execute_CsrPlugin_readData = ((((_zz_119 | _zz_120) | (_zz_121 | _zz_122)) | ((_zz_123 | _zz_124) | (_zz_125 | _zz_126))) | (_zz_127 | _zz_128)); - assign iBusWishbone_ADR = {_zz_225,_zz_129}; - assign iBusWishbone_CTI = ((_zz_129 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = ((((_zz_131 | _zz_132) | (_zz_133 | _zz_134)) | ((_zz_135 | _zz_136) | (_zz_137 | _zz_138))) | (_zz_139 | _zz_140)); + assign iBusWishbone_ADR = {_zz_243,_zz_141}; + assign iBusWishbone_CTI = ((_zz_141 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_161)begin + if(_zz_175)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_161)begin + if(_zz_175)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_130; + assign iBus_rsp_valid = _zz_142; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; @@ -3210,19 +3710,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_131 = 4'b0001; + _zz_143 = 4'b0001; end 2'b01 : begin - _zz_131 = 4'b0011; + _zz_143 = 4'b0011; end default : begin - _zz_131 = 4'b1111; + _zz_143 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_131 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_143 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -3242,17 +3742,18 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_51 <= 1'b0; - _zz_53 <= 1'b0; + _zz_67 <= 1'b0; + _zz_69 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_55; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_71; IBusCachedPlugin_rspCounter <= 32'h0; - _zz_56 <= 1'b0; - _zz_80 <= 1'b1; + _zz_95 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_91 <= 1'b0; + _zz_106 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3261,18 +3762,25 @@ module VexRiscv ( CsrPlugin_mie_MSIE <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; CsrPlugin_interrupt_valid <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - execute_MulDivIterativePlugin_frontendOk <= 1'b0; - execute_MulDivIterativePlugin_mul_counter_value <= 6'h0; - _zz_117 <= 32'h0; + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; + _zz_129 <= 32'h0; execute_arbitration_isValid <= 1'b0; - _zz_129 <= 3'b000; - _zz_130 <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; + _zz_141 <= 3'b000; + _zz_142 <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin @@ -3296,16 +3804,16 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_51 <= 1'b0; + _zz_67 <= 1'b0; end - if(_zz_49)begin - _zz_51 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_65)begin + _zz_67 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_53 <= 1'b0; + _zz_69 <= 1'b0; end if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_53 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + _zz_69 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; @@ -3331,18 +3839,50 @@ module VexRiscv ( if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(iBus_rsp_valid)begin - IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((dBus_cmd_valid && dBus_cmd_ready))begin - _zz_56 <= 1'b1; + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if((! execute_arbitration_isStuck))begin - _zz_56 <= 1'b0; + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_80 <= 1'b0; - if(_zz_146)begin - if(_zz_162)begin + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); + `else + if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); + $finish; + end + `endif + `endif + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); + `else + if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin + $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); + $finish; + end + `endif + `endif + _zz_95 <= 1'b0; + if(_zz_157)begin + if(_zz_176)begin execute_LightShifterPlugin_isActive <= 1'b1; if(execute_LightShifterPlugin_done)begin execute_LightShifterPlugin_isActive <= 1'b0; @@ -3352,7 +3892,7 @@ module VexRiscv ( if(execute_arbitration_removeIt)begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_91 <= (_zz_31 && execute_arbitration_isFiring); + _zz_106 <= (_zz_45 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -3361,17 +3901,27 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin - CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_163)begin - if(_zz_164)begin + if(_zz_177)begin + if(_zz_178)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_165)begin + if(_zz_179)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_166)begin + if(_zz_180)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -3379,15 +3929,23 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end end if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end if(CsrPlugin_interruptJump)begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_153)begin + if(_zz_163)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3398,8 +3956,8 @@ module VexRiscv ( end endcase end - if(_zz_154)begin - case(_zz_155) + if(_zz_164)begin + case(_zz_165) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3409,7 +3967,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_105,{_zz_104,_zz_103}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_120,{_zz_119,_zz_118}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -3422,45 +3980,60 @@ module VexRiscv ( if((! execute_arbitration_isStuckByOthers))begin execute_CfuPlugin_fired <= 1'b0; end - if(((execute_arbitration_isValid && (! 1'b0)) && (1'b0 || execute_IS_MUL)))begin - execute_MulDivIterativePlugin_frontendOk <= 1'b1; + if(memory_CfuPlugin_rsp_ready)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + end + if(_zz_181)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end - if(execute_arbitration_isMoving)begin - execute_MulDivIterativePlugin_frontendOk <= 1'b0; + memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; + if((! memory_arbitration_isStuck))begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; end - execute_MulDivIterativePlugin_mul_counter_value <= execute_MulDivIterativePlugin_mul_counter_valueNext; if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin execute_arbitration_isValid <= decode_arbitration_isValid; end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_219[0]; - CsrPlugin_mstatus_MIE <= _zz_220[0]; + CsrPlugin_mstatus_MPIE <= _zz_237[0]; + CsrPlugin_mstatus_MIE <= _zz_238[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_222[0]; - CsrPlugin_mie_MTIE <= _zz_223[0]; - CsrPlugin_mie_MSIE <= _zz_224[0]; + CsrPlugin_mie_MEIE <= _zz_240[0]; + CsrPlugin_mie_MTIE <= _zz_241[0]; + CsrPlugin_mie_MSIE <= _zz_242[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_117 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_129 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_161)begin + if(_zz_175)begin if(iBusWishbone_ACK)begin - _zz_129 <= (_zz_129 + 3'b001); + _zz_141 <= (_zz_141 + 3'b001); end end - _zz_130 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_167)begin + _zz_142 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_182)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -3472,7 +4045,7 @@ module VexRiscv ( always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_54 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_70 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; @@ -3480,50 +4053,51 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if((! execute_arbitration_isStuckByOthers))begin - execute_LightShifterPlugin_shiftReg <= _zz_41; - end - if(_zz_146)begin - if(_zz_162)begin + if(_zz_157)begin + if(_zz_176)begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - _zz_92 <= _zz_30[11 : 7]; + _zz_107 <= _zz_44[11 : 7]; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(execute_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end if(decodeExceptionPort_valid)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= decodeExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= decodeExceptionPort_payload_badAddr; end - if(_zz_152)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= _zz_144; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= _zz_145; + if(CsrPlugin_selfException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_163)begin - if(_zz_164)begin + if(_zz_162)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_122 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_122 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + end + if(_zz_177)begin + if(_zz_178)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_165)begin + if(_zz_179)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_166)begin + if(_zz_180)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_153)begin + if(_zz_163)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; - CsrPlugin_mepc <= execute_PC; + CsrPlugin_mepc <= writeBack_PC; if(CsrPlugin_hadException)begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end @@ -3532,59 +4106,120 @@ module VexRiscv ( end endcase end - if(_zz_148)begin - if(_zz_151)begin - execute_MulDivIterativePlugin_rs2 <= (execute_MulDivIterativePlugin_rs2 >>> 1); - execute_MulDivIterativePlugin_accumulator <= ({_zz_209,execute_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + if(_zz_181)begin + CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if(_zz_156)begin + if(_zz_161)begin + memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_227,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end - if((! execute_MulDivIterativePlugin_frontendOk))begin - execute_MulDivIterativePlugin_accumulator <= 65'h0; - execute_MulDivIterativePlugin_rs1 <= ((_zz_115 ? (~ _zz_116) : _zz_116) + _zz_216); - execute_MulDivIterativePlugin_rs2 <= ((_zz_114 ? (~ execute_RS2) : execute_RS2) + _zz_218); + if((! memory_arbitration_isStuck))begin + memory_MulDivIterativePlugin_accumulator <= 65'h0; + memory_MulDivIterativePlugin_rs1 <= ((_zz_127 ? (~ _zz_128) : _zz_128) + _zz_234); + memory_MulDivIterativePlugin_rs2 <= ((_zz_126 ? (~ execute_RS2) : execute_RS2) + _zz_236); end externalInterruptArray_regNext <= externalInterruptArray; - if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin - decode_to_execute_PC <= _zz_23; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_39; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; end if((! execute_arbitration_isStuck))begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end if((! execute_arbitration_isStuck))begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_56; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_57; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_27; + end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_24; + end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end if((! execute_arbitration_isStuck))begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_17; + decode_to_execute_ALU_CTRL <= _zz_21; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_14; + decode_to_execute_ALU_BITWISE_CTRL <= _zz_18; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_11; + decode_to_execute_SHIFT_CTRL <= _zz_15; end if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + decode_to_execute_BRANCH_CTRL <= _zz_12; end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_CSR <= decode_IS_CSR; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_5; + decode_to_execute_ENV_CTRL <= _zz_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4; end if((! execute_arbitration_isStuck))begin decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; @@ -3595,6 +4230,9 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin decode_to_execute_IS_MUL <= decode_IS_MUL; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end if((! execute_arbitration_isStuck))begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end @@ -3602,26 +4240,52 @@ module VexRiscv ( decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS1 <= _zz_26; + decode_to_execute_RS1 <= decode_RS1; end if((! execute_arbitration_isStuck))begin - decode_to_execute_RS2 <= _zz_24; + decode_to_execute_RS2 <= decode_RS2; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1 <= decode_SRC1; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2 <= decode_SRC2; - end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; + execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; + execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; + execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; + execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; + execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; + execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; + execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; + execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + end + if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_29; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end @@ -3657,7 +4321,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_221[0]; + CsrPlugin_mip_MSIP <= _zz_239[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -3672,7 +4336,7 @@ module VexRiscv ( end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_167)begin + if(_zz_182)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index d6f2792..60d8c57 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -90,6 +90,10 @@ object GenCoreDefault{ val argConfig = parser.parse(args, ArgConfig()).get val linux = argConfig.csrPluginConfig.startsWith("linux") + if (!argConfig.memoryAndWritebackStage && argConfig.cfu) { + throw new RuntimeException("CFU plugin requires a memory and writeback stage.") + } + SpinalConfig.copy(netlistFileName = argConfig.outputFile + ".v").generateVerilog { // Generate CPU plugin list val plugins = ArrayBuffer[Plugin[VexRiscv]]() From 9face5f3bd7dcd579630757378b154a34e863a24 Mon Sep 17 00:00:00 2001 From: Joey Bushagour Date: Mon, 9 Aug 2021 14:08:21 -0500 Subject: [PATCH 22/30] Add icache, single-cycle-shift, and single-cycle multiply to the Fomu variant. Signed-off-by: Joey Bushagour --- pythondata_cpu_vexriscv/verilog/Makefile | 4 +- .../verilog/VexRiscv_Fomu.v | 2799 ++++++++------- .../verilog/VexRiscv_Fomu.yaml | 2 +- .../verilog/VexRiscv_FomuCfu.v | 3017 +++++++++-------- .../verilog/VexRiscv_FomuCfu.yaml | 2 +- .../main/scala/vexriscv/GenCoreDefault.scala | 8 +- 6 files changed, 3064 insertions(+), 2768 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index 6cb3346..db48c99 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -27,10 +27,10 @@ VexRiscv_MinDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault -d --iCacheSize 0 --dCacheSize 0 --mulDiv false --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --outputFile VexRiscv_MinDebug" VexRiscv_Fomu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --safe false --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --outputFile VexRiscv_Fomu" + sbt compile "runMain vexriscv.GenCoreDefault --safe false --iCacheSize 2048 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift true --singleCycleMulDiv true --bypass false --prediction none --hardwareDiv false --outputFile VexRiscv_Fomu" VexRiscv_FomuCfu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --safe false --cfu true --iCacheSize 512 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift false --singleCycleMulDiv false --bypass false --prediction none --hardwareDiv false --outputFile VexRiscv_FomuCfu" + sbt compile "runMain vexriscv.GenCoreDefault --safe false --cfu true --iCacheSize 2048 --dCacheSize 0 --csrPluginConfig mcycle --mulDiv true --singleCycleShift true --singleCycleMulDiv true --bypass false --prediction none --hardwareDiv false --outputFile VexRiscv_FomuCfu" VexRiscv_Full.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all --outputFile VexRiscv_Full" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v index b9a7259..a3a8c57 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 43e13174d8583db5f4cd45d2b3515bc206a0010a +// Git hash : d8ec2d84c3160c3a9131beef2db359dce7a2e4a4 `define EnvCtrlEnum_defaultEncoding_type [1:0] @@ -73,6 +73,7 @@ module VexRiscv ( input clk, input reset ); + wire _zz_128; wire _zz_129; wire _zz_130; wire _zz_131; @@ -80,11 +81,10 @@ module VexRiscv ( wire _zz_133; wire _zz_134; wire _zz_135; - wire _zz_136; - reg _zz_137; + reg _zz_136; + reg [31:0] _zz_137; reg [31:0] _zz_138; reg [31:0] _zz_139; - reg [31:0] _zz_140; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -97,230 +97,255 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_140; wire _zz_141; wire _zz_142; wire _zz_143; wire _zz_144; - wire _zz_145; + wire [1:0] _zz_145; wire _zz_146; wire _zz_147; wire _zz_148; - wire [1:0] _zz_149; + wire _zz_149; wire _zz_150; wire _zz_151; wire _zz_152; wire _zz_153; wire _zz_154; - wire _zz_155; + wire [1:0] _zz_155; wire _zz_156; wire _zz_157; wire _zz_158; wire _zz_159; wire _zz_160; wire _zz_161; - wire _zz_162; + wire [1:0] _zz_162; wire _zz_163; - wire _zz_164; - wire _zz_165; - wire [1:0] _zz_166; - wire _zz_167; - wire [0:0] _zz_168; - wire [0:0] _zz_169; - wire [0:0] _zz_170; - wire [0:0] _zz_171; - wire [0:0] _zz_172; - wire [0:0] _zz_173; - wire [0:0] _zz_174; - wire [0:0] _zz_175; - wire [0:0] _zz_176; + wire [1:0] _zz_164; + wire [51:0] _zz_165; + wire [51:0] _zz_166; + wire [51:0] _zz_167; + wire [32:0] _zz_168; + wire [51:0] _zz_169; + wire [49:0] _zz_170; + wire [51:0] _zz_171; + wire [49:0] _zz_172; + wire [51:0] _zz_173; + wire [32:0] _zz_174; + wire [31:0] _zz_175; + wire [32:0] _zz_176; wire [0:0] _zz_177; wire [0:0] _zz_178; wire [0:0] _zz_179; wire [0:0] _zz_180; wire [0:0] _zz_181; wire [0:0] _zz_182; - wire [2:0] _zz_183; - wire [2:0] _zz_184; - wire [31:0] _zz_185; + wire [0:0] _zz_183; + wire [0:0] _zz_184; + wire [0:0] _zz_185; wire [0:0] _zz_186; - wire [2:0] _zz_187; - wire [4:0] _zz_188; - wire [11:0] _zz_189; - wire [11:0] _zz_190; - wire [31:0] _zz_191; + wire [0:0] _zz_187; + wire [0:0] _zz_188; + wire [0:0] _zz_189; + wire [2:0] _zz_190; + wire [2:0] _zz_191; wire [31:0] _zz_192; - wire [31:0] _zz_193; - wire [31:0] _zz_194; - wire [31:0] _zz_195; - wire [31:0] _zz_196; - wire [31:0] _zz_197; + wire [0:0] _zz_193; + wire [2:0] _zz_194; + wire [4:0] _zz_195; + wire [11:0] _zz_196; + wire [11:0] _zz_197; wire [31:0] _zz_198; - wire [32:0] _zz_199; - wire [19:0] _zz_200; - wire [11:0] _zz_201; - wire [11:0] _zz_202; - wire [0:0] _zz_203; - wire [5:0] _zz_204; - wire [33:0] _zz_205; - wire [32:0] _zz_206; - wire [33:0] _zz_207; - wire [32:0] _zz_208; - wire [33:0] _zz_209; - wire [32:0] _zz_210; - wire [0:0] _zz_211; - wire [32:0] _zz_212; + wire [31:0] _zz_199; + wire [31:0] _zz_200; + wire [31:0] _zz_201; + wire [31:0] _zz_202; + wire [31:0] _zz_203; + wire [31:0] _zz_204; + wire [19:0] _zz_205; + wire [11:0] _zz_206; + wire [11:0] _zz_207; + wire [65:0] _zz_208; + wire [65:0] _zz_209; + wire [31:0] _zz_210; + wire [31:0] _zz_211; + wire [0:0] _zz_212; wire [0:0] _zz_213; - wire [31:0] _zz_214; + wire [0:0] _zz_214; wire [0:0] _zz_215; wire [0:0] _zz_216; wire [0:0] _zz_217; - wire [0:0] _zz_218; - wire [0:0] _zz_219; - wire [0:0] _zz_220; - wire [26:0] _zz_221; - wire _zz_222; - wire _zz_223; - wire [1:0] _zz_224; - wire [31:0] _zz_225; - wire [31:0] _zz_226; - wire [31:0] _zz_227; - wire _zz_228; - wire [0:0] _zz_229; - wire [13:0] _zz_230; - wire [31:0] _zz_231; - wire [31:0] _zz_232; - wire [31:0] _zz_233; - wire _zz_234; - wire [0:0] _zz_235; - wire [7:0] _zz_236; - wire [31:0] _zz_237; - wire [31:0] _zz_238; - wire [31:0] _zz_239; - wire _zz_240; - wire [0:0] _zz_241; - wire [1:0] _zz_242; + wire [26:0] _zz_218; + wire _zz_219; + wire _zz_220; + wire [1:0] _zz_221; + wire [31:0] _zz_222; + wire [31:0] _zz_223; + wire [31:0] _zz_224; + wire _zz_225; + wire [0:0] _zz_226; + wire [13:0] _zz_227; + wire [31:0] _zz_228; + wire [31:0] _zz_229; + wire [31:0] _zz_230; + wire _zz_231; + wire [0:0] _zz_232; + wire [7:0] _zz_233; + wire [31:0] _zz_234; + wire [31:0] _zz_235; + wire [31:0] _zz_236; + wire _zz_237; + wire [0:0] _zz_238; + wire [1:0] _zz_239; + wire [31:0] _zz_240; + wire [31:0] _zz_241; + wire [31:0] _zz_242; wire _zz_243; - wire [0:0] _zz_244; - wire [0:0] _zz_245; + wire [1:0] _zz_244; + wire [1:0] _zz_245; wire _zz_246; wire [0:0] _zz_247; - wire [23:0] _zz_248; + wire [21:0] _zz_248; wire [31:0] _zz_249; - wire _zz_250; - wire _zz_251; - wire [0:0] _zz_252; - wire [0:0] _zz_253; - wire [0:0] _zz_254; - wire [0:0] _zz_255; - wire _zz_256; - wire [0:0] _zz_257; - wire [19:0] _zz_258; - wire [31:0] _zz_259; + wire [31:0] _zz_250; + wire [31:0] _zz_251; + wire [31:0] _zz_252; + wire _zz_253; + wire _zz_254; + wire [1:0] _zz_255; + wire [1:0] _zz_256; + wire _zz_257; + wire [0:0] _zz_258; + wire [18:0] _zz_259; wire [31:0] _zz_260; - wire _zz_261; - wire _zz_262; - wire _zz_263; - wire [2:0] _zz_264; - wire [2:0] _zz_265; - wire _zz_266; - wire [0:0] _zz_267; - wire [16:0] _zz_268; - wire [31:0] _zz_269; - wire [31:0] _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire [0:0] _zz_274; - wire [0:0] _zz_275; - wire _zz_276; - wire [0:0] _zz_277; - wire [0:0] _zz_278; - wire _zz_279; - wire [0:0] _zz_280; - wire [13:0] _zz_281; - wire [31:0] _zz_282; - wire [31:0] _zz_283; + wire [31:0] _zz_261; + wire [31:0] _zz_262; + wire [31:0] _zz_263; + wire [31:0] _zz_264; + wire [31:0] _zz_265; + wire [0:0] _zz_266; + wire [1:0] _zz_267; + wire [0:0] _zz_268; + wire [0:0] _zz_269; + wire _zz_270; + wire [0:0] _zz_271; + wire [15:0] _zz_272; + wire [31:0] _zz_273; + wire [31:0] _zz_274; + wire [31:0] _zz_275; + wire [31:0] _zz_276; + wire [31:0] _zz_277; + wire [31:0] _zz_278; + wire [31:0] _zz_279; + wire [31:0] _zz_280; + wire _zz_281; + wire [1:0] _zz_282; + wire [1:0] _zz_283; wire _zz_284; - wire _zz_285; - wire [0:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; - wire [0:0] _zz_289; - wire _zz_290; - wire [0:0] _zz_291; - wire [10:0] _zz_292; - wire [31:0] _zz_293; - wire [31:0] _zz_294; + wire [0:0] _zz_285; + wire [12:0] _zz_286; + wire [31:0] _zz_287; + wire [31:0] _zz_288; + wire [31:0] _zz_289; + wire [31:0] _zz_290; + wire [31:0] _zz_291; + wire [31:0] _zz_292; + wire [1:0] _zz_293; + wire [1:0] _zz_294; wire _zz_295; - wire _zz_296; - wire _zz_297; - wire [0:0] _zz_298; - wire [0:0] _zz_299; - wire _zz_300; - wire [0:0] _zz_301; - wire [7:0] _zz_302; - wire [31:0] _zz_303; + wire [0:0] _zz_296; + wire [9:0] _zz_297; + wire [31:0] _zz_298; + wire [31:0] _zz_299; + wire [31:0] _zz_300; + wire _zz_301; + wire [0:0] _zz_302; + wire [1:0] _zz_303; wire [0:0] _zz_304; - wire [0:0] _zz_305; - wire [0:0] _zz_306; - wire [4:0] _zz_307; - wire [1:0] _zz_308; - wire [1:0] _zz_309; - wire _zz_310; - wire [0:0] _zz_311; - wire [4:0] _zz_312; + wire [3:0] _zz_305; + wire [5:0] _zz_306; + wire [5:0] _zz_307; + wire _zz_308; + wire [0:0] _zz_309; + wire [5:0] _zz_310; + wire [31:0] _zz_311; + wire [31:0] _zz_312; wire [31:0] _zz_313; wire [31:0] _zz_314; wire [31:0] _zz_315; wire [31:0] _zz_316; wire _zz_317; wire [0:0] _zz_318; - wire [1:0] _zz_319; - wire [31:0] _zz_320; - wire [31:0] _zz_321; - wire _zz_322; - wire [0:0] _zz_323; - wire [2:0] _zz_324; + wire [0:0] _zz_319; + wire _zz_320; + wire [0:0] _zz_321; + wire [2:0] _zz_322; + wire _zz_323; + wire [0:0] _zz_324; wire [0:0] _zz_325; - wire [0:0] _zz_326; - wire _zz_327; - wire [0:0] _zz_328; - wire [1:0] _zz_329; - wire [31:0] _zz_330; + wire [3:0] _zz_326; + wire [3:0] _zz_327; + wire _zz_328; + wire [0:0] _zz_329; + wire [2:0] _zz_330; wire [31:0] _zz_331; wire [31:0] _zz_332; - wire _zz_333; - wire _zz_334; + wire [31:0] _zz_333; + wire [31:0] _zz_334; wire [31:0] _zz_335; wire [31:0] _zz_336; wire [31:0] _zz_337; - wire _zz_338; - wire [0:0] _zz_339; + wire [31:0] _zz_338; + wire _zz_339; wire [0:0] _zz_340; - wire [31:0] _zz_341; + wire [0:0] _zz_341; wire [31:0] _zz_342; - wire [0:0] _zz_343; - wire [1:0] _zz_344; - wire [1:0] _zz_345; - wire [1:0] _zz_346; - wire _zz_347; + wire [31:0] _zz_343; + wire [31:0] _zz_344; + wire _zz_345; + wire [0:0] _zz_346; + wire [1:0] _zz_347; wire _zz_348; - wire [31:0] _zz_349; - wire [31:0] _zz_350; - wire [31:0] _zz_351; - wire [31:0] _zz_352; - wire [31:0] _zz_353; + wire [2:0] _zz_349; + wire [2:0] _zz_350; + wire _zz_351; + wire [0:0] _zz_352; + wire [0:0] _zz_353; wire [31:0] _zz_354; wire [31:0] _zz_355; - wire _zz_356; - wire _zz_357; - wire _zz_358; - wire [0:0] _zz_359; - wire [0:0] _zz_360; - wire _zz_361; + wire [31:0] _zz_356; + wire [31:0] _zz_357; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire [31:0] _zz_360; + wire [31:0] _zz_361; + wire _zz_362; + wire [31:0] _zz_363; + wire _zz_364; + wire [0:0] _zz_365; + wire [0:0] _zz_366; + wire [0:0] _zz_367; + wire [0:0] _zz_368; + wire [1:0] _zz_369; + wire [1:0] _zz_370; + wire [0:0] _zz_371; + wire [0:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; + wire [31:0] _zz_375; + wire [31:0] _zz_376; + wire [31:0] _zz_377; + wire [31:0] _zz_378; + wire [51:0] memory_MUL_LOW; wire [31:0] memory_MEMORY_READ_DATA; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; wire [1:0] memory_MEMORY_ADDRESS_LOW; @@ -330,8 +355,8 @@ module VexRiscv ( wire decode_SRC2_FORCE_ZERO; wire [31:0] decode_RS2; wire [31:0] decode_RS1; - wire decode_IS_RS2_SIGNED; - wire decode_IS_RS1_SIGNED; + wire memory_IS_MUL; + wire execute_IS_MUL; wire decode_IS_MUL; wire `EnvCtrlEnum_defaultEncoding_type _zz_1; wire `EnvCtrlEnum_defaultEncoding_type _zz_2; @@ -346,55 +371,59 @@ module VexRiscv ( wire `BranchCtrlEnum_defaultEncoding_type _zz_8; wire `BranchCtrlEnum_defaultEncoding_type _zz_9; wire `BranchCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; wire decode_SRC_LESS_UNSIGNED; wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_17; - wire `AluCtrlEnum_defaultEncoding_type _zz_18; wire `AluCtrlEnum_defaultEncoding_type _zz_19; + wire `AluCtrlEnum_defaultEncoding_type _zz_20; + wire `AluCtrlEnum_defaultEncoding_type _zz_21; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `Src2CtrlEnum_defaultEncoding_type _zz_24; wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; - wire execute_IS_RS1_SIGNED; - wire execute_IS_MUL; - wire execute_IS_RS2_SIGNED; - reg [31:0] _zz_26; - wire memory_IS_MUL; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + reg [31:0] _zz_28; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_defaultEncoding_type _zz_29; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_defaultEncoding_type _zz_30; wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `EnvCtrlEnum_defaultEncoding_type _zz_31; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; - wire [31:0] execute_RS1; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `BranchCtrlEnum_defaultEncoding_type _zz_32; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; @@ -403,42 +432,45 @@ module VexRiscv ( wire [31:0] memory_INSTRUCTION; wire memory_BYPASSABLE_MEMORY_STAGE; wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] _zz_31; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_33; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_32; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_35; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_33; + wire [31:0] _zz_36; wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_34; + wire `Src2CtrlEnum_defaultEncoding_type _zz_37; wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_35; + wire `Src1CtrlEnum_defaultEncoding_type _zz_38; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_36; + wire `AluCtrlEnum_defaultEncoding_type _zz_39; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_37; - wire [31:0] _zz_38; - wire _zz_39; - reg _zz_40; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_40; + wire [31:0] _zz_41; + wire _zz_42; + reg _zz_43; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_41; - wire `BranchCtrlEnum_defaultEncoding_type _zz_42; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_43; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_44; - wire `AluCtrlEnum_defaultEncoding_type _zz_45; - wire `Src2CtrlEnum_defaultEncoding_type _zz_46; - wire `Src1CtrlEnum_defaultEncoding_type _zz_47; + wire `EnvCtrlEnum_defaultEncoding_type _zz_44; + wire `BranchCtrlEnum_defaultEncoding_type _zz_45; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_46; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47; + wire `AluCtrlEnum_defaultEncoding_type _zz_48; + wire `Src2CtrlEnum_defaultEncoding_type _zz_49; + wire `Src1CtrlEnum_defaultEncoding_type _zz_50; wire writeBack_MEMORY_STORE; - reg [31:0] _zz_48; + reg [31:0] _zz_51; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; @@ -467,7 +499,7 @@ module VexRiscv ( wire execute_MMU_RSP2_refilling; wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; - wire [31:0] execute_RS2; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; @@ -477,7 +509,7 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_49; + reg [31:0] _zz_52; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -595,10 +627,10 @@ module VexRiscv ( wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_50; - wire [2:0] _zz_51; - wire _zz_52; - wire _zz_53; + wire [2:0] _zz_53; + wire [2:0] _zz_54; + wire _zz_55; + wire _zz_56; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; @@ -635,16 +667,16 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_54; - wire _zz_55; - wire _zz_56; - wire IBusCachedPlugin_iBusRsp_flush; wire _zz_57; wire _zz_58; - reg _zz_59; + wire _zz_59; + wire IBusCachedPlugin_iBusRsp_flush; wire _zz_60; - reg _zz_61; - reg [31:0] _zz_62; + wire _zz_61; + reg _zz_62; + wire _zz_63; + reg _zz_64; + reg [31:0] _zz_65; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -664,7 +696,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_63; + wire [31:0] _zz_66; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -681,31 +713,29 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - wire _zz_64; + wire _zz_67; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_65; - reg [3:0] _zz_66; + reg [31:0] _zz_68; + reg [3:0] _zz_69; wire [3:0] execute_DBusSimplePlugin_formalMask; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_67; - reg [31:0] _zz_68; - wire _zz_69; - reg [31:0] _zz_70; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [29:0] _zz_71; + wire _zz_70; + reg [31:0] _zz_71; wire _zz_72; - wire _zz_73; - wire _zz_74; + reg [31:0] _zz_73; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [27:0] _zz_74; wire _zz_75; wire _zz_76; wire _zz_77; - wire `Src1CtrlEnum_defaultEncoding_type _zz_78; - wire `Src2CtrlEnum_defaultEncoding_type _zz_79; - wire `AluCtrlEnum_defaultEncoding_type _zz_80; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_81; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_82; - wire `BranchCtrlEnum_defaultEncoding_type _zz_83; - wire `EnvCtrlEnum_defaultEncoding_type _zz_84; + wire _zz_78; + wire `Src1CtrlEnum_defaultEncoding_type _zz_79; + wire `Src2CtrlEnum_defaultEncoding_type _zz_80; + wire `AluCtrlEnum_defaultEncoding_type _zz_81; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_82; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_83; + wire `BranchCtrlEnum_defaultEncoding_type _zz_84; + wire `EnvCtrlEnum_defaultEncoding_type _zz_85; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -713,40 +743,37 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_85; + reg _zz_86; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_86; reg [31:0] _zz_87; - wire _zz_88; - reg [19:0] _zz_89; - wire _zz_90; - reg [19:0] _zz_91; - reg [31:0] _zz_92; + reg [31:0] _zz_88; + wire _zz_89; + reg [19:0] _zz_90; + wire _zz_91; + reg [19:0] _zz_92; + reg [31:0] _zz_93; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; - reg execute_LightShifterPlugin_isActive; - wire execute_LightShifterPlugin_isShift; - reg [4:0] execute_LightShifterPlugin_amplitudeReg; - wire [4:0] execute_LightShifterPlugin_amplitude; - wire [31:0] execute_LightShifterPlugin_shiftInput; - wire execute_LightShifterPlugin_done; - reg [31:0] _zz_93; - reg _zz_94; - reg _zz_95; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_94; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_95; reg _zz_96; - reg [4:0] _zz_97; + reg _zz_97; + reg _zz_98; + reg [4:0] _zz_99; wire execute_BranchPlugin_eq; - wire [2:0] _zz_98; - reg _zz_99; - reg _zz_100; + wire [2:0] _zz_100; + reg _zz_101; + reg _zz_102; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_101; - reg [10:0] _zz_102; wire _zz_103; - reg [19:0] _zz_104; + reg [10:0] _zz_104; wire _zz_105; - reg [18:0] _zz_106; - reg [31:0] _zz_107; + reg [19:0] _zz_106; + wire _zz_107; + reg [18:0] _zz_108; + reg [31:0] _zz_109; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -768,9 +795,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_108; - wire _zz_109; wire _zz_110; + wire _zz_111; + wire _zz_112; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -811,22 +838,20 @@ module VexRiscv ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - wire memory_MulDivIterativePlugin_frontendOk; - reg memory_MulDivIterativePlugin_mul_counter_willIncrement; - reg memory_MulDivIterativePlugin_mul_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; - wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_mul_counter_willOverflow; - wire _zz_111; - wire _zz_112; - reg [32:0] _zz_113; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_114; - wire [31:0] _zz_115; + reg [31:0] _zz_113; + wire [31:0] _zz_114; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -855,6 +880,7 @@ module VexRiscv ( reg decode_to_execute_SRC_LESS_UNSIGNED; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; reg decode_to_execute_IS_CSR; reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; @@ -862,8 +888,7 @@ module VexRiscv ( reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; reg decode_to_execute_IS_MUL; reg execute_to_memory_IS_MUL; - reg decode_to_execute_IS_RS1_SIGNED; - reg decode_to_execute_IS_RS2_SIGNED; + reg memory_to_writeBack_IS_MUL; reg [31:0] decode_to_execute_RS1; reg [31:0] decode_to_execute_RS2; reg decode_to_execute_SRC2_FORCE_ZERO; @@ -883,9 +908,16 @@ module VexRiscv ( reg execute_to_memory_MMU_RSP2_bypassTranslation; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; reg execute_to_memory_BRANCH_DO; reg [31:0] execute_to_memory_BRANCH_CALC; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg [51:0] memory_to_writeBack_MUL_LOW; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_836; reg execute_CsrPlugin_csr_772; @@ -897,6 +929,7 @@ module VexRiscv ( reg execute_CsrPlugin_csr_2944; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_115; reg [31:0] _zz_116; reg [31:0] _zz_117; reg [31:0] _zz_118; @@ -906,9 +939,8 @@ module VexRiscv ( reg [31:0] _zz_122; reg [31:0] _zz_123; reg [31:0] _zz_124; - reg [31:0] _zz_125; - reg [2:0] _zz_126; - reg _zz_127; + reg [2:0] _zz_125; + reg _zz_126; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -922,7 +954,7 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_128; + reg [3:0] _zz_127; `ifndef SYNTHESIS reg [39:0] _zz_1_string; reg [39:0] _zz_2_string; @@ -936,63 +968,68 @@ module VexRiscv ( reg [31:0] _zz_8_string; reg [31:0] _zz_9_string; reg [31:0] _zz_10_string; - reg [71:0] decode_SHIFT_CTRL_string; reg [71:0] _zz_11_string; reg [71:0] _zz_12_string; + reg [71:0] decode_SHIFT_CTRL_string; reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [71:0] _zz_15_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_14_string; - reg [39:0] _zz_15_string; reg [39:0] _zz_16_string; + reg [39:0] _zz_17_string; + reg [39:0] _zz_18_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_17_string; - reg [63:0] _zz_18_string; reg [63:0] _zz_19_string; + reg [63:0] _zz_20_string; + reg [63:0] _zz_21_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_20_string; - reg [23:0] _zz_21_string; reg [23:0] _zz_22_string; + reg [23:0] _zz_23_string; + reg [23:0] _zz_24_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_23_string; - reg [95:0] _zz_24_string; reg [95:0] _zz_25_string; + reg [95:0] _zz_26_string; + reg [95:0] _zz_27_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_29_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_30_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_31_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_30_string; + reg [31:0] _zz_32_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_34_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_32_string; + reg [71:0] _zz_35_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_34_string; + reg [23:0] _zz_37_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_35_string; + reg [95:0] _zz_38_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_36_string; + reg [63:0] _zz_39_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_37_string; - reg [39:0] _zz_41_string; - reg [31:0] _zz_42_string; - reg [71:0] _zz_43_string; + reg [39:0] _zz_40_string; reg [39:0] _zz_44_string; - reg [63:0] _zz_45_string; - reg [23:0] _zz_46_string; - reg [95:0] _zz_47_string; - reg [95:0] _zz_78_string; - reg [23:0] _zz_79_string; - reg [63:0] _zz_80_string; - reg [39:0] _zz_81_string; - reg [71:0] _zz_82_string; - reg [31:0] _zz_83_string; - reg [39:0] _zz_84_string; + reg [31:0] _zz_45_string; + reg [71:0] _zz_46_string; + reg [39:0] _zz_47_string; + reg [63:0] _zz_48_string; + reg [23:0] _zz_49_string; + reg [95:0] _zz_50_string; + reg [95:0] _zz_79_string; + reg [23:0] _zz_80_string; + reg [63:0] _zz_81_string; + reg [39:0] _zz_82_string; + reg [71:0] _zz_83_string; + reg [31:0] _zz_84_string; + reg [39:0] _zz_85_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [39:0] decode_to_execute_ENV_CTRL_string; reg [39:0] execute_to_memory_ENV_CTRL_string; @@ -1001,253 +1038,271 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_141 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_142 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_143 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_144 = ((_zz_134 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_145 = ((_zz_134 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_146 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_147 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_148 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_149 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_150 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_151 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_152 = (1'b1 || (! 1'b1)); - assign _zz_153 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_154 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_155 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_156 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_157 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_158 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_159 = (iBus_cmd_valid || (_zz_126 != 3'b000)); - assign _zz_160 = (! execute_arbitration_isStuckByOthers); - assign _zz_161 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_162 = ((_zz_108 && 1'b1) && (! 1'b0)); - assign _zz_163 = ((_zz_109 && 1'b1) && (! 1'b0)); - assign _zz_164 = ((_zz_110 && 1'b1) && (! 1'b0)); - assign _zz_165 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_166 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_167 = execute_INSTRUCTION[13]; - assign _zz_168 = _zz_71[29 : 29]; - assign _zz_169 = _zz_71[28 : 28]; - assign _zz_170 = _zz_71[27 : 27]; - assign _zz_171 = _zz_71[24 : 24]; - assign _zz_172 = _zz_71[15 : 15]; - assign _zz_173 = _zz_71[11 : 11]; - assign _zz_174 = _zz_71[10 : 10]; - assign _zz_175 = _zz_71[9 : 9]; - assign _zz_176 = _zz_71[12 : 12]; - assign _zz_177 = _zz_71[5 : 5]; - assign _zz_178 = _zz_71[3 : 3]; - assign _zz_179 = _zz_71[18 : 18]; - assign _zz_180 = _zz_71[8 : 8]; - assign _zz_181 = _zz_71[4 : 4]; - assign _zz_182 = _zz_71[0 : 0]; - assign _zz_183 = (_zz_50 - 3'b001); - assign _zz_184 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_185 = {29'd0, _zz_184}; - assign _zz_186 = execute_SRC_LESS; - assign _zz_187 = 3'b100; - assign _zz_188 = execute_INSTRUCTION[19 : 15]; - assign _zz_189 = execute_INSTRUCTION[31 : 20]; - assign _zz_190 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_191 = ($signed(_zz_192) + $signed(_zz_195)); - assign _zz_192 = ($signed(_zz_193) + $signed(_zz_194)); - assign _zz_193 = execute_SRC1; - assign _zz_194 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_195 = (execute_SRC_USE_SUB_LESS ? _zz_196 : _zz_197); - assign _zz_196 = 32'h00000001; - assign _zz_197 = 32'h0; - assign _zz_198 = (_zz_199 >>> 1); - assign _zz_199 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_200 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_201 = execute_INSTRUCTION[31 : 20]; - assign _zz_202 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_203 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_204 = {5'd0, _zz_203}; - assign _zz_205 = (_zz_207 + _zz_209); - assign _zz_206 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_207 = {{1{_zz_206[32]}}, _zz_206}; - assign _zz_208 = _zz_210; - assign _zz_209 = {{1{_zz_208[32]}}, _zz_208}; - assign _zz_210 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_211 = _zz_112; - assign _zz_212 = {32'd0, _zz_211}; - assign _zz_213 = _zz_111; - assign _zz_214 = {31'd0, _zz_213}; - assign _zz_215 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_216 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_140 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_141 = ((_zz_133 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_142 = ((_zz_133 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_143 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_144 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_145 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_146 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_147 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_148 = (1'b1 || (! 1'b1)); + assign _zz_149 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_150 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_151 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_152 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_153 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_154 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_155 = execute_INSTRUCTION[13 : 12]; + assign _zz_156 = (iBus_cmd_valid || (_zz_125 != 3'b000)); + assign _zz_157 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_158 = ((_zz_110 && 1'b1) && (! 1'b0)); + assign _zz_159 = ((_zz_111 && 1'b1) && (! 1'b0)); + assign _zz_160 = ((_zz_112 && 1'b1) && (! 1'b0)); + assign _zz_161 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_162 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_163 = execute_INSTRUCTION[13]; + assign _zz_164 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_165 = ($signed(_zz_166) + $signed(_zz_171)); + assign _zz_166 = ($signed(_zz_167) + $signed(_zz_169)); + assign _zz_167 = 52'h0; + assign _zz_168 = {1'b0,memory_MUL_LL}; + assign _zz_169 = {{19{_zz_168[32]}}, _zz_168}; + assign _zz_170 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_171 = {{2{_zz_170[49]}}, _zz_170}; + assign _zz_172 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_173 = {{2{_zz_172[49]}}, _zz_172}; + assign _zz_174 = ($signed(_zz_176) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_175 = _zz_174[31 : 0]; + assign _zz_176 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_177 = _zz_74[27 : 27]; + assign _zz_178 = _zz_74[24 : 24]; + assign _zz_179 = _zz_74[15 : 15]; + assign _zz_180 = _zz_74[11 : 11]; + assign _zz_181 = _zz_74[10 : 10]; + assign _zz_182 = _zz_74[9 : 9]; + assign _zz_183 = _zz_74[12 : 12]; + assign _zz_184 = _zz_74[5 : 5]; + assign _zz_185 = _zz_74[3 : 3]; + assign _zz_186 = _zz_74[18 : 18]; + assign _zz_187 = _zz_74[8 : 8]; + assign _zz_188 = _zz_74[4 : 4]; + assign _zz_189 = _zz_74[0 : 0]; + assign _zz_190 = (_zz_53 - 3'b001); + assign _zz_191 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_192 = {29'd0, _zz_191}; + assign _zz_193 = execute_SRC_LESS; + assign _zz_194 = 3'b100; + assign _zz_195 = execute_INSTRUCTION[19 : 15]; + assign _zz_196 = execute_INSTRUCTION[31 : 20]; + assign _zz_197 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_198 = ($signed(_zz_199) + $signed(_zz_202)); + assign _zz_199 = ($signed(_zz_200) + $signed(_zz_201)); + assign _zz_200 = execute_SRC1; + assign _zz_201 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_202 = (execute_SRC_USE_SUB_LESS ? _zz_203 : _zz_204); + assign _zz_203 = 32'h00000001; + assign _zz_204 = 32'h0; + assign _zz_205 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_206 = execute_INSTRUCTION[31 : 20]; + assign _zz_207 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_208 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_209 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_210 = writeBack_MUL_LOW[31 : 0]; + assign _zz_211 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_212 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_213 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_214 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_215 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_216 = execute_CsrPlugin_writeData[7 : 7]; assign _zz_217 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_218 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_219 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_220 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_221 = (iBus_cmd_payload_address >>> 5); - assign _zz_222 = 1'b1; - assign _zz_223 = 1'b1; - assign _zz_224 = {_zz_53,_zz_52}; - assign _zz_225 = 32'h0000107f; - assign _zz_226 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_227 = 32'h00002073; - assign _zz_228 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_229 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_230 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_231) == 32'h00000003),{(_zz_232 == _zz_233),{_zz_234,{_zz_235,_zz_236}}}}}}; - assign _zz_231 = 32'h0000505f; - assign _zz_232 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_233 = 32'h00000063; - assign _zz_234 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_235 = ((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033); - assign _zz_236 = {((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_237) == 32'h00001013),{(_zz_238 == _zz_239),{_zz_240,{_zz_241,_zz_242}}}}}}; - assign _zz_237 = 32'hfc00705f; - assign _zz_238 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_239 = 32'h00005033; - assign _zz_240 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_241 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_242 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; - assign _zz_243 = ((decode_INSTRUCTION & 32'h02000074) == 32'h02000030); - assign _zz_244 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); - assign _zz_245 = 1'b0; - assign _zz_246 = (((decode_INSTRUCTION & _zz_249) == 32'h10000050) != 1'b0); - assign _zz_247 = ({_zz_250,_zz_251} != 2'b00); - assign _zz_248 = {({_zz_252,_zz_253} != 2'b00),{(_zz_254 != _zz_255),{_zz_256,{_zz_257,_zz_258}}}}; - assign _zz_249 = 32'h10403050; - assign _zz_250 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_251 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_252 = _zz_75; - assign _zz_253 = ((decode_INSTRUCTION & _zz_259) == 32'h00000004); - assign _zz_254 = ((decode_INSTRUCTION & _zz_260) == 32'h00000040); - assign _zz_255 = 1'b0; - assign _zz_256 = ({_zz_261,_zz_262} != 2'b00); - assign _zz_257 = (_zz_263 != 1'b0); - assign _zz_258 = {(_zz_264 != _zz_265),{_zz_266,{_zz_267,_zz_268}}}; - assign _zz_259 = 32'h0000001c; - assign _zz_260 = 32'h00000058; - assign _zz_261 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); - assign _zz_262 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); - assign _zz_263 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); - assign _zz_264 = {(_zz_269 == _zz_270),{_zz_271,_zz_272}}; - assign _zz_265 = 3'b000; - assign _zz_266 = ({_zz_273,{_zz_274,_zz_275}} != 3'b000); - assign _zz_267 = (_zz_276 != 1'b0); - assign _zz_268 = {(_zz_277 != _zz_278),{_zz_279,{_zz_280,_zz_281}}}; - assign _zz_269 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_270 = 32'h40001010; - assign _zz_271 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_272 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_273 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_274 = ((decode_INSTRUCTION & _zz_282) == 32'h00001010); - assign _zz_275 = ((decode_INSTRUCTION & _zz_283) == 32'h00001010); - assign _zz_276 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_277 = _zz_76; - assign _zz_278 = 1'b0; - assign _zz_279 = ({_zz_284,_zz_285} != 2'b00); - assign _zz_280 = ({_zz_286,_zz_287} != 2'b00); - assign _zz_281 = {(_zz_288 != _zz_289),{_zz_290,{_zz_291,_zz_292}}}; - assign _zz_282 = 32'h00003034; - assign _zz_283 = 32'h02003054; - assign _zz_284 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_285 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_286 = ((decode_INSTRUCTION & _zz_293) == 32'h00006000); - assign _zz_287 = ((decode_INSTRUCTION & _zz_294) == 32'h00004000); - assign _zz_288 = _zz_73; - assign _zz_289 = 1'b0; - assign _zz_290 = ({_zz_295,_zz_296} != 2'b00); - assign _zz_291 = (_zz_297 != 1'b0); - assign _zz_292 = {(_zz_298 != _zz_299),{_zz_300,{_zz_301,_zz_302}}}; - assign _zz_293 = 32'h00006004; - assign _zz_294 = 32'h00005004; - assign _zz_295 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); - assign _zz_296 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_297 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz_298 = ((decode_INSTRUCTION & _zz_303) == 32'h00000010); - assign _zz_299 = 1'b0; - assign _zz_300 = ({_zz_74,{_zz_304,_zz_305}} != 3'b000); - assign _zz_301 = ({_zz_306,_zz_307} != 6'h0); - assign _zz_302 = {(_zz_308 != _zz_309),{_zz_310,{_zz_311,_zz_312}}}; - assign _zz_303 = 32'h00000010; - assign _zz_304 = ((decode_INSTRUCTION & _zz_313) == 32'h00000010); - assign _zz_305 = ((decode_INSTRUCTION & _zz_314) == 32'h00000020); - assign _zz_306 = _zz_75; - assign _zz_307 = {(_zz_315 == _zz_316),{_zz_317,{_zz_318,_zz_319}}}; - assign _zz_308 = {_zz_74,(_zz_320 == _zz_321)}; - assign _zz_309 = 2'b00; - assign _zz_310 = ({_zz_74,_zz_322} != 2'b00); - assign _zz_311 = ({_zz_323,_zz_324} != 4'b0000); - assign _zz_312 = {(_zz_325 != _zz_326),{_zz_327,{_zz_328,_zz_329}}}; - assign _zz_313 = 32'h00000030; - assign _zz_314 = 32'h02000060; - assign _zz_315 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_316 = 32'h00001010; - assign _zz_317 = ((decode_INSTRUCTION & _zz_330) == 32'h00002010); - assign _zz_318 = (_zz_331 == _zz_332); - assign _zz_319 = {_zz_333,_zz_334}; - assign _zz_320 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_321 = 32'h00000020; - assign _zz_322 = ((decode_INSTRUCTION & _zz_335) == 32'h0); - assign _zz_323 = (_zz_336 == _zz_337); - assign _zz_324 = {_zz_338,{_zz_339,_zz_340}}; - assign _zz_325 = (_zz_341 == _zz_342); - assign _zz_326 = 1'b0; - assign _zz_327 = ({_zz_343,_zz_344} != 3'b000); - assign _zz_328 = (_zz_345 != _zz_346); - assign _zz_329 = {_zz_347,_zz_348}; - assign _zz_330 = 32'h00002010; - assign _zz_331 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_332 = 32'h00000010; - assign _zz_333 = ((decode_INSTRUCTION & _zz_349) == 32'h00000004); - assign _zz_334 = ((decode_INSTRUCTION & _zz_350) == 32'h0); + assign _zz_218 = (iBus_cmd_payload_address >>> 5); + assign _zz_219 = 1'b1; + assign _zz_220 = 1'b1; + assign _zz_221 = {_zz_56,_zz_55}; + assign _zz_222 = 32'h0000107f; + assign _zz_223 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_224 = 32'h00002073; + assign _zz_225 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_226 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_227 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_228) == 32'h00000003),{(_zz_229 == _zz_230),{_zz_231,{_zz_232,_zz_233}}}}}}; + assign _zz_228 = 32'h0000505f; + assign _zz_229 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_230 = 32'h00000063; + assign _zz_231 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_232 = ((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033); + assign _zz_233 = {((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_234) == 32'h00001013),{(_zz_235 == _zz_236),{_zz_237,{_zz_238,_zz_239}}}}}}; + assign _zz_234 = 32'hfc00307f; + assign _zz_235 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_236 = 32'h00005033; + assign _zz_237 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_238 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_239 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_240 = 32'h02000074; + assign _zz_241 = (decode_INSTRUCTION & 32'h10003050); + assign _zz_242 = 32'h00000050; + assign _zz_243 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz_244 = {(_zz_249 == _zz_250),(_zz_251 == _zz_252)}; + assign _zz_245 = 2'b00; + assign _zz_246 = ({_zz_78,_zz_253} != 2'b00); + assign _zz_247 = (_zz_254 != 1'b0); + assign _zz_248 = {(_zz_255 != _zz_256),{_zz_257,{_zz_258,_zz_259}}}; + assign _zz_249 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_250 = 32'h00001050; + assign _zz_251 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_252 = 32'h00002050; + assign _zz_253 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_254 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_255 = {(_zz_260 == _zz_261),(_zz_262 == _zz_263)}; + assign _zz_256 = 2'b00; + assign _zz_257 = ((_zz_264 == _zz_265) != 1'b0); + assign _zz_258 = ({_zz_266,_zz_267} != 3'b000); + assign _zz_259 = {(_zz_268 != _zz_269),{_zz_270,{_zz_271,_zz_272}}}; + assign _zz_260 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_261 = 32'h00000040; + assign _zz_262 = (decode_INSTRUCTION & 32'h00403040); + assign _zz_263 = 32'h00000040; + assign _zz_264 = (decode_INSTRUCTION & 32'h00007054); + assign _zz_265 = 32'h00005010; + assign _zz_266 = ((decode_INSTRUCTION & _zz_273) == 32'h40001010); + assign _zz_267 = {(_zz_274 == _zz_275),(_zz_276 == _zz_277)}; + assign _zz_268 = ((decode_INSTRUCTION & _zz_278) == 32'h00000024); + assign _zz_269 = 1'b0; + assign _zz_270 = ((_zz_279 == _zz_280) != 1'b0); + assign _zz_271 = (_zz_281 != 1'b0); + assign _zz_272 = {(_zz_282 != _zz_283),{_zz_284,{_zz_285,_zz_286}}}; + assign _zz_273 = 32'h40003054; + assign _zz_274 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_275 = 32'h00001010; + assign _zz_276 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_277 = 32'h00001010; + assign _zz_278 = 32'h00000064; + assign _zz_279 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_280 = 32'h00001000; + assign _zz_281 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_282 = {(_zz_287 == _zz_288),(_zz_289 == _zz_290)}; + assign _zz_283 = 2'b00; + assign _zz_284 = ((_zz_291 == _zz_292) != 1'b0); + assign _zz_285 = (_zz_76 != 1'b0); + assign _zz_286 = {(_zz_293 != _zz_294),{_zz_295,{_zz_296,_zz_297}}}; + assign _zz_287 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_288 = 32'h00002000; + assign _zz_289 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_290 = 32'h00001000; + assign _zz_291 = (decode_INSTRUCTION & 32'h00004004); + assign _zz_292 = 32'h00004000; + assign _zz_293 = {((decode_INSTRUCTION & _zz_298) == 32'h00000020),((decode_INSTRUCTION & _zz_299) == 32'h00000020)}; + assign _zz_294 = 2'b00; + assign _zz_295 = (((decode_INSTRUCTION & _zz_300) == 32'h00000020) != 1'b0); + assign _zz_296 = ({_zz_301,{_zz_302,_zz_303}} != 4'b0000); + assign _zz_297 = {({_zz_304,_zz_305} != 5'h0),{(_zz_306 != _zz_307),{_zz_308,{_zz_309,_zz_310}}}}; + assign _zz_298 = 32'h00000034; + assign _zz_299 = 32'h00000064; + assign _zz_300 = 32'h00000020; + assign _zz_301 = ((decode_INSTRUCTION & 32'h00000040) == 32'h00000040); + assign _zz_302 = _zz_77; + assign _zz_303 = {(_zz_311 == _zz_312),(_zz_313 == _zz_314)}; + assign _zz_304 = _zz_77; + assign _zz_305 = {(_zz_315 == _zz_316),{_zz_317,{_zz_318,_zz_319}}}; + assign _zz_306 = {_zz_78,{_zz_320,{_zz_321,_zz_322}}}; + assign _zz_307 = 6'h0; + assign _zz_308 = ({_zz_77,_zz_323} != 2'b00); + assign _zz_309 = ({_zz_324,_zz_325} != 2'b00); + assign _zz_310 = {(_zz_326 != _zz_327),{_zz_328,{_zz_329,_zz_330}}}; + assign _zz_311 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_312 = 32'h00000010; + assign _zz_313 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_314 = 32'h00000020; + assign _zz_315 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_316 = 32'h00002010; + assign _zz_317 = ((decode_INSTRUCTION & _zz_331) == 32'h00000010); + assign _zz_318 = (_zz_332 == _zz_333); + assign _zz_319 = (_zz_334 == _zz_335); + assign _zz_320 = ((decode_INSTRUCTION & _zz_336) == 32'h00001010); + assign _zz_321 = (_zz_337 == _zz_338); + assign _zz_322 = {_zz_339,{_zz_340,_zz_341}}; + assign _zz_323 = ((decode_INSTRUCTION & _zz_342) == 32'h00000020); + assign _zz_324 = _zz_77; + assign _zz_325 = (_zz_343 == _zz_344); + assign _zz_326 = {_zz_345,{_zz_346,_zz_347}}; + assign _zz_327 = 4'b0000; + assign _zz_328 = (_zz_348 != 1'b0); + assign _zz_329 = (_zz_349 != _zz_350); + assign _zz_330 = {_zz_351,{_zz_352,_zz_353}}; + assign _zz_331 = 32'h00001030; + assign _zz_332 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_333 = 32'h00002020; + assign _zz_334 = (decode_INSTRUCTION & 32'h02003020); assign _zz_335 = 32'h00000020; - assign _zz_336 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_337 = 32'h0; - assign _zz_338 = ((decode_INSTRUCTION & _zz_351) == 32'h0); - assign _zz_339 = _zz_73; - assign _zz_340 = (_zz_352 == _zz_353); - assign _zz_341 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_342 = 32'h0; - assign _zz_343 = (_zz_354 == _zz_355); - assign _zz_344 = {_zz_356,_zz_357}; - assign _zz_345 = {_zz_358,_zz_72}; - assign _zz_346 = 2'b00; - assign _zz_347 = ({_zz_359,_zz_360} != 2'b00); - assign _zz_348 = (_zz_361 != 1'b0); - assign _zz_349 = 32'h0000000c; - assign _zz_350 = 32'h00000028; - assign _zz_351 = 32'h00000018; - assign _zz_352 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_353 = 32'h00001000; - assign _zz_354 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_355 = 32'h00000040; - assign _zz_356 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_357 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz_358 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_359 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_360 = _zz_72; - assign _zz_361 = ((decode_INSTRUCTION & 32'h00001048) == 32'h00001008); + assign _zz_336 = 32'h00001010; + assign _zz_337 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_338 = 32'h00002010; + assign _zz_339 = ((decode_INSTRUCTION & _zz_354) == 32'h00000010); + assign _zz_340 = (_zz_355 == _zz_356); + assign _zz_341 = (_zz_357 == _zz_358); + assign _zz_342 = 32'h00000070; + assign _zz_343 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_344 = 32'h0; + assign _zz_345 = ((decode_INSTRUCTION & _zz_359) == 32'h0); + assign _zz_346 = (_zz_360 == _zz_361); + assign _zz_347 = {_zz_76,_zz_362}; + assign _zz_348 = ((decode_INSTRUCTION & _zz_363) == 32'h0); + assign _zz_349 = {_zz_364,{_zz_365,_zz_366}}; + assign _zz_350 = 3'b000; + assign _zz_351 = ({_zz_367,_zz_368} != 2'b00); + assign _zz_352 = (_zz_369 != _zz_370); + assign _zz_353 = (_zz_371 != _zz_372); + assign _zz_354 = 32'h00000050; + assign _zz_355 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_356 = 32'h00000004; + assign _zz_357 = (decode_INSTRUCTION & 32'h00000028); + assign _zz_358 = 32'h0; + assign _zz_359 = 32'h00000044; + assign _zz_360 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_361 = 32'h0; + assign _zz_362 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_363 = 32'h00000058; + assign _zz_364 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_365 = ((decode_INSTRUCTION & _zz_373) == 32'h00002010); + assign _zz_366 = ((decode_INSTRUCTION & _zz_374) == 32'h40000030); + assign _zz_367 = ((decode_INSTRUCTION & _zz_375) == 32'h00000004); + assign _zz_368 = _zz_75; + assign _zz_369 = {(_zz_376 == _zz_377),_zz_75}; + assign _zz_370 = 2'b00; + assign _zz_371 = ((decode_INSTRUCTION & _zz_378) == 32'h00001008); + assign _zz_372 = 1'b0; + assign _zz_373 = 32'h00002014; + assign _zz_374 = 32'h40000034; + assign _zz_375 = 32'h00000014; + assign _zz_376 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_377 = 32'h00000004; + assign _zz_378 = 32'h00001048; always @ (posedge clk) begin - if(_zz_222) begin - _zz_138 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_219) begin + _zz_137 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_223) begin - _zz_139 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_220) begin + _zz_138 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_40) begin + if(_zz_43) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_129 ), //i - .io_cpu_prefetch_isValid (_zz_130 ), //i + .io_flush (_zz_128 ), //i + .io_cpu_prefetch_isValid (_zz_129 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_131 ), //i - .io_cpu_fetch_isStuck (_zz_132 ), //i - .io_cpu_fetch_isRemoved (_zz_133 ), //i + .io_cpu_fetch_isValid (_zz_130 ), //i + .io_cpu_fetch_isStuck (_zz_131 ), //i + .io_cpu_fetch_isRemoved (_zz_132 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1260,8 +1315,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_134 ), //i - .io_cpu_decode_isStuck (_zz_135 ), //i + .io_cpu_decode_isValid (_zz_133 ), //i + .io_cpu_decode_isStuck (_zz_134 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1269,8 +1324,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_136 ), //i - .io_cpu_fill_valid (_zz_137 ), //i + .io_cpu_decode_isUser (_zz_135 ), //i + .io_cpu_fill_valid (_zz_136 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1283,15 +1338,15 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_224) + case(_zz_221) 2'b00 : begin - _zz_140 = CsrPlugin_jumpInterface_payload; + _zz_139 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_140 = DBusSimplePlugin_redoBranch_payload; + _zz_139 = DBusSimplePlugin_redoBranch_payload; end default : begin - _zz_140 = BranchPlugin_jumpInterface_payload; + _zz_139 = BranchPlugin_jumpInterface_payload; end endcase end @@ -1397,15 +1452,6 @@ module VexRiscv ( default : _zz_10_string = "????"; endcase end - always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end always @(*) begin case(_zz_11) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; @@ -1424,6 +1470,15 @@ module VexRiscv ( default : _zz_12_string = "?????????"; endcase end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end always @(*) begin case(_zz_13) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; @@ -1434,27 +1489,29 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; - default : _zz_14_string = "?????"; + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin @@ -1466,27 +1523,27 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(_zz_17) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; + default : _zz_17_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_17_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_17_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_17_string = "BITWISE "; - default : _zz_17_string = "????????"; + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_18_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_18_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_18_string = "BITWISE "; - default : _zz_18_string = "????????"; + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin @@ -1498,30 +1555,28 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(_zz_20) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; + default : _zz_20_string = "????????"; endcase end always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + case(_zz_21) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; + default : _zz_21_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin @@ -1534,30 +1589,30 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(_zz_23) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; endcase end always @(*) begin - case(_zz_23) - `Src1CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_23_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_23_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_23_string = "URS1 "; - default : _zz_23_string = "????????????"; + case(_zz_24) + `Src2CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_24_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_24_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_24_string = "PC "; + default : _zz_24_string = "???"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin @@ -1569,6 +1624,24 @@ module VexRiscv ( default : _zz_25_string = "????????????"; endcase end + always @(*) begin + case(_zz_26) + `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; + default : _zz_26_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end always @(*) begin case(memory_ENV_CTRL) `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; @@ -1578,11 +1651,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_29) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; + default : _zz_29_string = "?????"; endcase end always @(*) begin @@ -1594,11 +1667,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_30) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_30_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_30_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30_string = "ECALL"; + default : _zz_30_string = "?????"; endcase end always @(*) begin @@ -1610,11 +1683,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_31) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_31_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_31_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_31_string = "ECALL"; + default : _zz_31_string = "?????"; endcase end always @(*) begin @@ -1627,12 +1700,30 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_30) - `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; - default : _zz_30_string = "????"; + case(_zz_32) + `BranchCtrlEnum_defaultEncoding_INC : _zz_32_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_32_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_32_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_32_string = "JALR"; + default : _zz_32_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_34) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; + default : _zz_34_string = "?????????"; endcase end always @(*) begin @@ -1645,12 +1736,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_32) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_32_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_32_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_32_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_32_string = "SRA_1 "; - default : _zz_32_string = "?????????"; + case(_zz_35) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35_string = "SRA_1 "; + default : _zz_35_string = "?????????"; endcase end always @(*) begin @@ -1663,12 +1754,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_34) - `Src2CtrlEnum_defaultEncoding_RS : _zz_34_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_34_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_34_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_34_string = "PC "; - default : _zz_34_string = "???"; + case(_zz_37) + `Src2CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_37_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_37_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_37_string = "PC "; + default : _zz_37_string = "???"; endcase end always @(*) begin @@ -1681,12 +1772,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_35) - `Src1CtrlEnum_defaultEncoding_RS : _zz_35_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_35_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_35_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_35_string = "URS1 "; - default : _zz_35_string = "????????????"; + case(_zz_38) + `Src1CtrlEnum_defaultEncoding_RS : _zz_38_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_38_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_38_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_38_string = "URS1 "; + default : _zz_38_string = "????????????"; endcase end always @(*) begin @@ -1698,11 +1789,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_36) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_36_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_36_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_36_string = "BITWISE "; - default : _zz_36_string = "????????"; + case(_zz_39) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_39_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_39_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_39_string = "BITWISE "; + default : _zz_39_string = "????????"; endcase end always @(*) begin @@ -1714,131 +1805,131 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_37) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_37_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_37_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_37_string = "AND_1"; - default : _zz_37_string = "?????"; - endcase - end - always @(*) begin - case(_zz_41) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_41_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_41_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_41_string = "ECALL"; - default : _zz_41_string = "?????"; + case(_zz_40) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_40_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_40_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_40_string = "AND_1"; + default : _zz_40_string = "?????"; endcase end always @(*) begin - case(_zz_42) - `BranchCtrlEnum_defaultEncoding_INC : _zz_42_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_42_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_42_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_42_string = "JALR"; - default : _zz_42_string = "????"; + case(_zz_44) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_44_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_44_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_44_string = "ECALL"; + default : _zz_44_string = "?????"; endcase end always @(*) begin - case(_zz_43) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_43_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_43_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_43_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_43_string = "SRA_1 "; - default : _zz_43_string = "?????????"; + case(_zz_45) + `BranchCtrlEnum_defaultEncoding_INC : _zz_45_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_45_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_45_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_45_string = "JALR"; + default : _zz_45_string = "????"; endcase end always @(*) begin - case(_zz_44) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_44_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_44_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_44_string = "AND_1"; - default : _zz_44_string = "?????"; + case(_zz_46) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46_string = "SRA_1 "; + default : _zz_46_string = "?????????"; endcase end always @(*) begin - case(_zz_45) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; - default : _zz_45_string = "????????"; + case(_zz_47) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47_string = "AND_1"; + default : _zz_47_string = "?????"; endcase end always @(*) begin - case(_zz_46) - `Src2CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_46_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_46_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_46_string = "PC "; - default : _zz_46_string = "???"; + case(_zz_48) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; + default : _zz_48_string = "????????"; endcase end always @(*) begin - case(_zz_47) - `Src1CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_47_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_47_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_47_string = "URS1 "; - default : _zz_47_string = "????????????"; + case(_zz_49) + `Src2CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_49_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_49_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_49_string = "PC "; + default : _zz_49_string = "???"; endcase end always @(*) begin - case(_zz_78) - `Src1CtrlEnum_defaultEncoding_RS : _zz_78_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_78_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_78_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_78_string = "URS1 "; - default : _zz_78_string = "????????????"; + case(_zz_50) + `Src1CtrlEnum_defaultEncoding_RS : _zz_50_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_50_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_50_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_50_string = "URS1 "; + default : _zz_50_string = "????????????"; endcase end always @(*) begin case(_zz_79) - `Src2CtrlEnum_defaultEncoding_RS : _zz_79_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_79_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_79_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_79_string = "PC "; - default : _zz_79_string = "???"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_79_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_79_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_79_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_79_string = "URS1 "; + default : _zz_79_string = "????????????"; endcase end always @(*) begin case(_zz_80) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_80_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_80_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_80_string = "BITWISE "; - default : _zz_80_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_80_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_80_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_80_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_80_string = "PC "; + default : _zz_80_string = "???"; endcase end always @(*) begin case(_zz_81) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_81_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_81_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_81_string = "AND_1"; - default : _zz_81_string = "?????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_81_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_81_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_81_string = "BITWISE "; + default : _zz_81_string = "????????"; endcase end always @(*) begin case(_zz_82) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_82_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_82_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_82_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_82_string = "SRA_1 "; - default : _zz_82_string = "?????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_82_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_82_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_82_string = "AND_1"; + default : _zz_82_string = "?????"; endcase end always @(*) begin case(_zz_83) - `BranchCtrlEnum_defaultEncoding_INC : _zz_83_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_83_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_83_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_83_string = "JALR"; - default : _zz_83_string = "????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_83_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_83_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_83_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_83_string = "SRA_1 "; + default : _zz_83_string = "?????????"; endcase end always @(*) begin case(_zz_84) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_84_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_84_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_84_string = "ECALL"; - default : _zz_84_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_84_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_84_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_84_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_84_string = "JALR"; + default : _zz_84_string = "????"; + endcase + end + always @(*) begin + case(_zz_85) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_85_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_85_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_85_string = "ECALL"; + default : _zz_85_string = "?????"; endcase end always @(*) begin @@ -1884,6 +1975,15 @@ module VexRiscv ( default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end always @(*) begin case(decode_to_execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; @@ -1919,11 +2019,18 @@ module VexRiscv ( end `endif + assign memory_MUL_LOW = ($signed(_zz_165) + $signed(_zz_173)); assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_100; + assign execute_BRANCH_DO = _zz_102; + assign execute_SHIFT_RIGHT = _zz_175; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_86; + assign execute_REGFILE_WRITE_DATA = _zz_87; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); @@ -1931,113 +2038,134 @@ module VexRiscv ( assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign decode_IS_RS2_SIGNED = _zz_168[0]; - assign decode_IS_RS1_SIGNED = _zz_169[0]; - assign decode_IS_MUL = _zz_170[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_177[0]; assign _zz_1 = _zz_2; assign _zz_3 = _zz_4; assign decode_ENV_CTRL = _zz_5; assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_171[0]; + assign decode_IS_CSR = _zz_178[0]; assign decode_BRANCH_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_SHIFT_CTRL = _zz_11; - assign _zz_12 = _zz_13; - assign decode_ALU_BITWISE_CTRL = _zz_14; - assign _zz_15 = _zz_16; - assign decode_SRC_LESS_UNSIGNED = _zz_172[0]; - assign decode_ALU_CTRL = _zz_17; - assign _zz_18 = _zz_19; - assign decode_MEMORY_STORE = _zz_173[0]; + assign _zz_11 = _zz_12; + assign decode_SHIFT_CTRL = _zz_13; + assign _zz_14 = _zz_15; + assign decode_ALU_BITWISE_CTRL = _zz_16; + assign _zz_17 = _zz_18; + assign decode_SRC_LESS_UNSIGNED = _zz_179[0]; + assign decode_ALU_CTRL = _zz_19; + assign _zz_20 = _zz_21; + assign decode_MEMORY_STORE = _zz_180[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_174[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_175[0]; - assign decode_SRC2_CTRL = _zz_20; - assign _zz_21 = _zz_22; - assign decode_SRC1_CTRL = _zz_23; - assign _zz_24 = _zz_25; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_181[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_182[0]; + assign decode_SRC2_CTRL = _zz_22; + assign _zz_23 = _zz_24; + assign decode_SRC1_CTRL = _zz_25; + assign _zz_26 = _zz_27; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); - assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; always @ (*) begin - _zz_26 = memory_REGFILE_WRITE_DATA; - if(_zz_141)begin - _zz_26 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + _zz_28 = execute_REGFILE_WRITE_DATA; + if(_zz_140)begin + _zz_28 = execute_CsrPlugin_readData; end end - assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27; - assign execute_ENV_CTRL = _zz_28; - assign writeBack_ENV_CTRL = _zz_29; + assign memory_ENV_CTRL = _zz_29; + assign execute_ENV_CTRL = _zz_30; + assign writeBack_ENV_CTRL = _zz_31; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_176[0]; - assign decode_RS1_USE = _zz_177[0]; + assign execute_BRANCH_CTRL = _zz_32; + assign decode_RS2_USE = _zz_183[0]; + assign decode_RS1_USE = _zz_184[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_142)begin - _zz_31 = _zz_93; - end - if(_zz_143)begin - _zz_31 = execute_CsrPlugin_readData; + _zz_33 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_33 = _zz_95; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_33 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase end end - assign execute_SHIFT_CTRL = _zz_32; + assign memory_SHIFT_CTRL = _zz_34; + assign execute_SHIFT_CTRL = _zz_35; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_33 = execute_PC; - assign execute_SRC2_CTRL = _zz_34; - assign execute_SRC1_CTRL = _zz_35; - assign decode_SRC_USE_SUB_LESS = _zz_178[0]; - assign decode_SRC_ADD_ZERO = _zz_179[0]; + assign _zz_36 = execute_PC; + assign execute_SRC2_CTRL = _zz_37; + assign execute_SRC1_CTRL = _zz_38; + assign decode_SRC_USE_SUB_LESS = _zz_185[0]; + assign decode_SRC_ADD_ZERO = _zz_186[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_36; - assign execute_SRC2 = _zz_92; - assign execute_SRC1 = _zz_87; - assign execute_ALU_BITWISE_CTRL = _zz_37; - assign _zz_38 = writeBack_INSTRUCTION; - assign _zz_39 = writeBack_REGFILE_WRITE_VALID; + assign execute_ALU_CTRL = _zz_39; + assign execute_SRC2 = _zz_93; + assign execute_SRC1 = _zz_88; + assign execute_ALU_BITWISE_CTRL = _zz_40; + assign _zz_41 = writeBack_INSTRUCTION; + assign _zz_42 = writeBack_REGFILE_WRITE_VALID; always @ (*) begin - _zz_40 = 1'b0; + _zz_43 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_40 = 1'b1; + _zz_43 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_180[0]; + decode_REGFILE_WRITE_VALID = _zz_187[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_225) == 32'h00001073),{(_zz_226 == _zz_227),{_zz_228,{_zz_229,_zz_230}}}}}}} != 21'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_222) == 32'h00001073),{(_zz_223 == _zz_224),{_zz_225,{_zz_226,_zz_227}}}}}}} != 21'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin - _zz_48 = writeBack_REGFILE_WRITE_DATA; + _zz_51 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_48 = writeBack_DBusSimplePlugin_rspFormated; + _zz_51 = writeBack_DBusSimplePlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_164) + 2'b00 : begin + _zz_51 = _zz_210; + end + default : begin + _zz_51 = _zz_211; + end + endcase end end @@ -2074,30 +2202,30 @@ module VexRiscv ( assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = 1'b0; - assign decode_MEMORY_ENABLE = _zz_181[0]; - assign decode_FLUSH_ALL = _zz_182[0]; + assign decode_MEMORY_ENABLE = _zz_188[0]; + assign decode_FLUSH_ALL = _zz_189[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_144)begin + if(_zz_141)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_145)begin + if(_zz_142)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_49 = memory_FORMAL_PC_NEXT; + _zz_52 = memory_FORMAL_PC_NEXT; if(DBusSimplePlugin_redoBranch_valid)begin - _zz_49 = DBusSimplePlugin_redoBranch_payload; + _zz_52 = DBusSimplePlugin_redoBranch_payload; end if(BranchPlugin_jumpInterface_valid)begin - _zz_49 = BranchPlugin_jumpInterface_payload; + _zz_52 = BranchPlugin_jumpInterface_payload; end end @@ -2113,7 +2241,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_94 || _zz_95)))begin + if((decode_arbitration_isValid && (_zz_96 || _zz_97)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2144,15 +2272,10 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_67)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_142)begin - if((! execute_LightShifterPlugin_done))begin - execute_arbitration_haltItself = 1'b1; - end - end - if(_zz_143)begin + if(_zz_140)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2183,14 +2306,6 @@ module VexRiscv ( if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin memory_arbitration_haltItself = 1'b1; end - if(_zz_141)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin - memory_arbitration_haltItself = 1'b1; - end - if(_zz_146)begin - memory_arbitration_haltItself = 1'b1; - end - end end assign memory_arbitration_haltByOther = 1'b0; @@ -2236,10 +2351,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_147)begin + if(_zz_143)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_148)begin + if(_zz_144)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2253,10 +2368,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_147)begin + if(_zz_143)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_148)begin + if(_zz_144)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -2272,21 +2387,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_147)begin + if(_zz_143)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_148)begin + if(_zz_144)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_147)begin + if(_zz_143)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_148)begin - case(_zz_149) + if(_zz_144)begin + case(_zz_145) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2301,11 +2416,11 @@ module VexRiscv ( assign CsrPlugin_allowException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); - assign _zz_50 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_51 = (_zz_50 & (~ _zz_183)); - assign _zz_52 = _zz_51[1]; - assign _zz_53 = _zz_51[2]; - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_140; + assign _zz_53 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; + assign _zz_54 = (_zz_53 & (~ _zz_190)); + assign _zz_55 = _zz_54[1]; + assign _zz_56 = _zz_54[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_139; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -2325,7 +2440,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_185); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_192); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -2365,9 +2480,9 @@ module VexRiscv ( end end - assign _zz_54 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_54); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_54); + assign _zz_57 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_57); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_57); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; @@ -2376,9 +2491,9 @@ module VexRiscv ( end end - assign _zz_55 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_55); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_55); + assign _zz_58 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_58); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_58); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; @@ -2387,22 +2502,22 @@ module VexRiscv ( end end - assign _zz_56 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_56); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_56); + assign _zz_59 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_59); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_59); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_57; - assign _zz_57 = ((1'b0 && (! _zz_58)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_58 = _zz_59; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_58; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_60; + assign _zz_60 = ((1'b0 && (! _zz_61)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_61 = _zz_62; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_61; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_60)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_60 = _zz_61; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_60; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_62; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_63)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_63 = _zz_64; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_63; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_65; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -2424,33 +2539,33 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_130 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_131 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_132 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_131; + assign _zz_129 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_130 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_131 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_130; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_134 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_135 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_136 = (CsrPlugin_privilege == 2'b00); + assign _zz_133 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_134 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_135 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_145)begin + if(_zz_142)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_144)begin + if(_zz_141)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_137 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_144)begin - _zz_137 = 1'b1; + _zz_136 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_141)begin + _zz_136 = 1'b1; end end @@ -2458,8 +2573,8 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_129 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign _zz_64 = 1'b0; + assign _zz_128 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_67 = 1'b0; always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin @@ -2470,39 +2585,39 @@ module VexRiscv ( end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_67)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_65 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_68 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_65 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_68 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_65 = execute_RS2[31 : 0]; + _zz_68 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_65; + assign dBus_cmd_payload_data = _zz_68; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_66 = 4'b0001; + _zz_69 = 4'b0001; end 2'b01 : begin - _zz_66 = 4'b0011; + _zz_69 = 4'b0011; end default : begin - _zz_66 = 4'b1111; + _zz_69 = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_66 <<< dBus_cmd_payload_address[1 : 0]); + assign execute_DBusSimplePlugin_formalMask = (_zz_69 <<< dBus_cmd_payload_address[1 : 0]); assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; @@ -2518,7 +2633,7 @@ module VexRiscv ( DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_150)begin + if(_zz_146)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end @@ -2538,7 +2653,7 @@ module VexRiscv ( if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_150)begin + if(_zz_146)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -2561,63 +2676,63 @@ module VexRiscv ( endcase end - assign _zz_67 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + assign _zz_70 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); always @ (*) begin - _zz_68[31] = _zz_67; - _zz_68[30] = _zz_67; - _zz_68[29] = _zz_67; - _zz_68[28] = _zz_67; - _zz_68[27] = _zz_67; - _zz_68[26] = _zz_67; - _zz_68[25] = _zz_67; - _zz_68[24] = _zz_67; - _zz_68[23] = _zz_67; - _zz_68[22] = _zz_67; - _zz_68[21] = _zz_67; - _zz_68[20] = _zz_67; - _zz_68[19] = _zz_67; - _zz_68[18] = _zz_67; - _zz_68[17] = _zz_67; - _zz_68[16] = _zz_67; - _zz_68[15] = _zz_67; - _zz_68[14] = _zz_67; - _zz_68[13] = _zz_67; - _zz_68[12] = _zz_67; - _zz_68[11] = _zz_67; - _zz_68[10] = _zz_67; - _zz_68[9] = _zz_67; - _zz_68[8] = _zz_67; - _zz_68[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_69 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + _zz_71[31] = _zz_70; + _zz_71[30] = _zz_70; + _zz_71[29] = _zz_70; + _zz_71[28] = _zz_70; + _zz_71[27] = _zz_70; + _zz_71[26] = _zz_70; + _zz_71[25] = _zz_70; + _zz_71[24] = _zz_70; + _zz_71[23] = _zz_70; + _zz_71[22] = _zz_70; + _zz_71[21] = _zz_70; + _zz_71[20] = _zz_70; + _zz_71[19] = _zz_70; + _zz_71[18] = _zz_70; + _zz_71[17] = _zz_70; + _zz_71[16] = _zz_70; + _zz_71[15] = _zz_70; + _zz_71[14] = _zz_70; + _zz_71[13] = _zz_70; + _zz_71[12] = _zz_70; + _zz_71[11] = _zz_70; + _zz_71[10] = _zz_70; + _zz_71[9] = _zz_70; + _zz_71[8] = _zz_70; + _zz_71[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_72 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); always @ (*) begin - _zz_70[31] = _zz_69; - _zz_70[30] = _zz_69; - _zz_70[29] = _zz_69; - _zz_70[28] = _zz_69; - _zz_70[27] = _zz_69; - _zz_70[26] = _zz_69; - _zz_70[25] = _zz_69; - _zz_70[24] = _zz_69; - _zz_70[23] = _zz_69; - _zz_70[22] = _zz_69; - _zz_70[21] = _zz_69; - _zz_70[20] = _zz_69; - _zz_70[19] = _zz_69; - _zz_70[18] = _zz_69; - _zz_70[17] = _zz_69; - _zz_70[16] = _zz_69; - _zz_70[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + _zz_73[31] = _zz_72; + _zz_73[30] = _zz_72; + _zz_73[29] = _zz_72; + _zz_73[28] = _zz_72; + _zz_73[27] = _zz_72; + _zz_73[26] = _zz_72; + _zz_73[25] = _zz_72; + _zz_73[24] = _zz_72; + _zz_73[23] = _zz_72; + _zz_73[22] = _zz_72; + _zz_73[21] = _zz_72; + _zz_73[20] = _zz_72; + _zz_73[19] = _zz_72; + _zz_73[18] = _zz_72; + _zz_73[17] = _zz_72; + _zz_73[16] = _zz_72; + _zz_73[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; end always @ (*) begin - case(_zz_166) + case(_zz_162) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_68; + writeBack_DBusSimplePlugin_rspFormated = _zz_71; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_70; + writeBack_DBusSimplePlugin_rspFormated = _zz_73; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -2643,51 +2758,49 @@ module VexRiscv ( assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_72 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_73 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_74 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_75 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_76 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_77 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00001000); - assign _zz_71 = {(_zz_77 != 1'b0),{({_zz_77,_zz_76} != 2'b00),{(_zz_243 != 1'b0),{(_zz_244 != _zz_245),{_zz_246,{_zz_247,_zz_248}}}}}}; - assign _zz_78 = _zz_71[2 : 1]; - assign _zz_47 = _zz_78; - assign _zz_79 = _zz_71[7 : 6]; - assign _zz_46 = _zz_79; - assign _zz_80 = _zz_71[14 : 13]; - assign _zz_45 = _zz_80; - assign _zz_81 = _zz_71[17 : 16]; - assign _zz_44 = _zz_81; - assign _zz_82 = _zz_71[20 : 19]; - assign _zz_43 = _zz_82; - assign _zz_83 = _zz_71[23 : 22]; - assign _zz_42 = _zz_83; - assign _zz_84 = _zz_71[26 : 25]; - assign _zz_41 = _zz_84; + assign _zz_75 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_76 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_77 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_78 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_74 = {(((decode_INSTRUCTION & _zz_240) == 32'h02000030) != 1'b0),{((_zz_241 == _zz_242) != 1'b0),{(_zz_243 != 1'b0),{(_zz_244 != _zz_245),{_zz_246,{_zz_247,_zz_248}}}}}}; + assign _zz_79 = _zz_74[2 : 1]; + assign _zz_50 = _zz_79; + assign _zz_80 = _zz_74[7 : 6]; + assign _zz_49 = _zz_80; + assign _zz_81 = _zz_74[14 : 13]; + assign _zz_48 = _zz_81; + assign _zz_82 = _zz_74[17 : 16]; + assign _zz_47 = _zz_82; + assign _zz_83 = _zz_74[20 : 19]; + assign _zz_46 = _zz_83; + assign _zz_84 = _zz_74[23 : 22]; + assign _zz_45 = _zz_84; + assign _zz_85 = _zz_74[26 : 25]; + assign _zz_44 = _zz_85; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_138; - assign decode_RegFilePlugin_rs2Data = _zz_139; + assign decode_RegFilePlugin_rs1Data = _zz_137; + assign decode_RegFilePlugin_rs2Data = _zz_138; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_39 && writeBack_arbitration_isFiring); - if(_zz_85)begin + lastStageRegFileWrite_valid = (_zz_42 && writeBack_arbitration_isFiring); + if(_zz_86)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_38[11 : 7]; - if(_zz_85)begin + lastStageRegFileWrite_payload_address = _zz_41[11 : 7]; + if(_zz_86)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_48; - if(_zz_85)begin + lastStageRegFileWrite_payload_data = _zz_51; + if(_zz_86)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -2709,13 +2822,13 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_86 = execute_IntAluPlugin_bitwise; + _zz_87 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_86 = {31'd0, _zz_186}; + _zz_87 = {31'd0, _zz_193}; end default : begin - _zz_86 = execute_SRC_ADD_SUB; + _zz_87 = execute_SRC_ADD_SUB; end endcase end @@ -2723,232 +2836,265 @@ module VexRiscv ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_87 = execute_RS1; + _zz_88 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_87 = {29'd0, _zz_187}; + _zz_88 = {29'd0, _zz_194}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_87 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_88 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_87 = {27'd0, _zz_188}; + _zz_88 = {27'd0, _zz_195}; end endcase end - assign _zz_88 = _zz_189[11]; + assign _zz_89 = _zz_196[11]; always @ (*) begin - _zz_89[19] = _zz_88; - _zz_89[18] = _zz_88; - _zz_89[17] = _zz_88; - _zz_89[16] = _zz_88; - _zz_89[15] = _zz_88; - _zz_89[14] = _zz_88; - _zz_89[13] = _zz_88; - _zz_89[12] = _zz_88; - _zz_89[11] = _zz_88; - _zz_89[10] = _zz_88; - _zz_89[9] = _zz_88; - _zz_89[8] = _zz_88; - _zz_89[7] = _zz_88; - _zz_89[6] = _zz_88; - _zz_89[5] = _zz_88; - _zz_89[4] = _zz_88; - _zz_89[3] = _zz_88; - _zz_89[2] = _zz_88; - _zz_89[1] = _zz_88; - _zz_89[0] = _zz_88; - end - - assign _zz_90 = _zz_190[11]; + _zz_90[19] = _zz_89; + _zz_90[18] = _zz_89; + _zz_90[17] = _zz_89; + _zz_90[16] = _zz_89; + _zz_90[15] = _zz_89; + _zz_90[14] = _zz_89; + _zz_90[13] = _zz_89; + _zz_90[12] = _zz_89; + _zz_90[11] = _zz_89; + _zz_90[10] = _zz_89; + _zz_90[9] = _zz_89; + _zz_90[8] = _zz_89; + _zz_90[7] = _zz_89; + _zz_90[6] = _zz_89; + _zz_90[5] = _zz_89; + _zz_90[4] = _zz_89; + _zz_90[3] = _zz_89; + _zz_90[2] = _zz_89; + _zz_90[1] = _zz_89; + _zz_90[0] = _zz_89; + end + + assign _zz_91 = _zz_197[11]; always @ (*) begin - _zz_91[19] = _zz_90; - _zz_91[18] = _zz_90; - _zz_91[17] = _zz_90; - _zz_91[16] = _zz_90; - _zz_91[15] = _zz_90; - _zz_91[14] = _zz_90; - _zz_91[13] = _zz_90; - _zz_91[12] = _zz_90; - _zz_91[11] = _zz_90; - _zz_91[10] = _zz_90; - _zz_91[9] = _zz_90; - _zz_91[8] = _zz_90; - _zz_91[7] = _zz_90; - _zz_91[6] = _zz_90; - _zz_91[5] = _zz_90; - _zz_91[4] = _zz_90; - _zz_91[3] = _zz_90; - _zz_91[2] = _zz_90; - _zz_91[1] = _zz_90; - _zz_91[0] = _zz_90; + _zz_92[19] = _zz_91; + _zz_92[18] = _zz_91; + _zz_92[17] = _zz_91; + _zz_92[16] = _zz_91; + _zz_92[15] = _zz_91; + _zz_92[14] = _zz_91; + _zz_92[13] = _zz_91; + _zz_92[12] = _zz_91; + _zz_92[11] = _zz_91; + _zz_92[10] = _zz_91; + _zz_92[9] = _zz_91; + _zz_92[8] = _zz_91; + _zz_92[7] = _zz_91; + _zz_92[6] = _zz_91; + _zz_92[5] = _zz_91; + _zz_92[4] = _zz_91; + _zz_92[3] = _zz_91; + _zz_92[2] = _zz_91; + _zz_92[1] = _zz_91; + _zz_92[0] = _zz_91; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_92 = execute_RS2; + _zz_93 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_92 = {_zz_89,execute_INSTRUCTION[31 : 20]}; + _zz_93 = {_zz_90,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_92 = {_zz_91,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_93 = {_zz_92,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_92 = _zz_33; + _zz_93 = _zz_36; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_191; + execute_SrcPlugin_addSub = _zz_198; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); - assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); - assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); - assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_93 = (execute_LightShifterPlugin_shiftInput <<< 1); - end - default : begin - _zz_93 = _zz_198; - end - endcase + _zz_94[0] = execute_SRC1[31]; + _zz_94[1] = execute_SRC1[30]; + _zz_94[2] = execute_SRC1[29]; + _zz_94[3] = execute_SRC1[28]; + _zz_94[4] = execute_SRC1[27]; + _zz_94[5] = execute_SRC1[26]; + _zz_94[6] = execute_SRC1[25]; + _zz_94[7] = execute_SRC1[24]; + _zz_94[8] = execute_SRC1[23]; + _zz_94[9] = execute_SRC1[22]; + _zz_94[10] = execute_SRC1[21]; + _zz_94[11] = execute_SRC1[20]; + _zz_94[12] = execute_SRC1[19]; + _zz_94[13] = execute_SRC1[18]; + _zz_94[14] = execute_SRC1[17]; + _zz_94[15] = execute_SRC1[16]; + _zz_94[16] = execute_SRC1[15]; + _zz_94[17] = execute_SRC1[14]; + _zz_94[18] = execute_SRC1[13]; + _zz_94[19] = execute_SRC1[12]; + _zz_94[20] = execute_SRC1[11]; + _zz_94[21] = execute_SRC1[10]; + _zz_94[22] = execute_SRC1[9]; + _zz_94[23] = execute_SRC1[8]; + _zz_94[24] = execute_SRC1[7]; + _zz_94[25] = execute_SRC1[6]; + _zz_94[26] = execute_SRC1[5]; + _zz_94[27] = execute_SRC1[4]; + _zz_94[28] = execute_SRC1[3]; + _zz_94[29] = execute_SRC1[2]; + _zz_94[30] = execute_SRC1[1]; + _zz_94[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_94 : execute_SRC1); + always @ (*) begin + _zz_95[0] = memory_SHIFT_RIGHT[31]; + _zz_95[1] = memory_SHIFT_RIGHT[30]; + _zz_95[2] = memory_SHIFT_RIGHT[29]; + _zz_95[3] = memory_SHIFT_RIGHT[28]; + _zz_95[4] = memory_SHIFT_RIGHT[27]; + _zz_95[5] = memory_SHIFT_RIGHT[26]; + _zz_95[6] = memory_SHIFT_RIGHT[25]; + _zz_95[7] = memory_SHIFT_RIGHT[24]; + _zz_95[8] = memory_SHIFT_RIGHT[23]; + _zz_95[9] = memory_SHIFT_RIGHT[22]; + _zz_95[10] = memory_SHIFT_RIGHT[21]; + _zz_95[11] = memory_SHIFT_RIGHT[20]; + _zz_95[12] = memory_SHIFT_RIGHT[19]; + _zz_95[13] = memory_SHIFT_RIGHT[18]; + _zz_95[14] = memory_SHIFT_RIGHT[17]; + _zz_95[15] = memory_SHIFT_RIGHT[16]; + _zz_95[16] = memory_SHIFT_RIGHT[15]; + _zz_95[17] = memory_SHIFT_RIGHT[14]; + _zz_95[18] = memory_SHIFT_RIGHT[13]; + _zz_95[19] = memory_SHIFT_RIGHT[12]; + _zz_95[20] = memory_SHIFT_RIGHT[11]; + _zz_95[21] = memory_SHIFT_RIGHT[10]; + _zz_95[22] = memory_SHIFT_RIGHT[9]; + _zz_95[23] = memory_SHIFT_RIGHT[8]; + _zz_95[24] = memory_SHIFT_RIGHT[7]; + _zz_95[25] = memory_SHIFT_RIGHT[6]; + _zz_95[26] = memory_SHIFT_RIGHT[5]; + _zz_95[27] = memory_SHIFT_RIGHT[4]; + _zz_95[28] = memory_SHIFT_RIGHT[3]; + _zz_95[29] = memory_SHIFT_RIGHT[2]; + _zz_95[30] = memory_SHIFT_RIGHT[1]; + _zz_95[31] = memory_SHIFT_RIGHT[0]; end always @ (*) begin - _zz_94 = 1'b0; - if(_zz_96)begin - if((_zz_97 == decode_INSTRUCTION[19 : 15]))begin - _zz_94 = 1'b1; + _zz_96 = 1'b0; + if(_zz_98)begin + if((_zz_99 == decode_INSTRUCTION[19 : 15]))begin + _zz_96 = 1'b1; end end - if(_zz_151)begin - if(_zz_152)begin + if(_zz_147)begin + if(_zz_148)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_94 = 1'b1; + _zz_96 = 1'b1; end end end - if(_zz_153)begin - if(_zz_154)begin + if(_zz_149)begin + if(_zz_150)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_94 = 1'b1; + _zz_96 = 1'b1; end end end - if(_zz_155)begin - if(_zz_156)begin + if(_zz_151)begin + if(_zz_152)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_94 = 1'b1; + _zz_96 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_94 = 1'b0; + _zz_96 = 1'b0; end end always @ (*) begin - _zz_95 = 1'b0; - if(_zz_96)begin - if((_zz_97 == decode_INSTRUCTION[24 : 20]))begin - _zz_95 = 1'b1; + _zz_97 = 1'b0; + if(_zz_98)begin + if((_zz_99 == decode_INSTRUCTION[24 : 20]))begin + _zz_97 = 1'b1; end end - if(_zz_151)begin - if(_zz_152)begin + if(_zz_147)begin + if(_zz_148)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_95 = 1'b1; + _zz_97 = 1'b1; end end end - if(_zz_153)begin - if(_zz_154)begin + if(_zz_149)begin + if(_zz_150)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_95 = 1'b1; + _zz_97 = 1'b1; end end end - if(_zz_155)begin - if(_zz_156)begin + if(_zz_151)begin + if(_zz_152)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_95 = 1'b1; + _zz_97 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_95 = 1'b0; + _zz_97 = 1'b0; end end assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_98 = execute_INSTRUCTION[14 : 12]; + assign _zz_100 = execute_INSTRUCTION[14 : 12]; always @ (*) begin - if((_zz_98 == 3'b000)) begin - _zz_99 = execute_BranchPlugin_eq; - end else if((_zz_98 == 3'b001)) begin - _zz_99 = (! execute_BranchPlugin_eq); - end else if((((_zz_98 & 3'b101) == 3'b101))) begin - _zz_99 = (! execute_SRC_LESS); + if((_zz_100 == 3'b000)) begin + _zz_101 = execute_BranchPlugin_eq; + end else if((_zz_100 == 3'b001)) begin + _zz_101 = (! execute_BranchPlugin_eq); + end else if((((_zz_100 & 3'b101) == 3'b101))) begin + _zz_101 = (! execute_SRC_LESS); end else begin - _zz_99 = execute_SRC_LESS; + _zz_101 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_100 = 1'b0; + _zz_102 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_100 = 1'b1; + _zz_102 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_100 = 1'b1; + _zz_102 = 1'b1; end default : begin - _zz_100 = _zz_99; + _zz_102 = _zz_101; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_101 = _zz_200[19]; - always @ (*) begin - _zz_102[10] = _zz_101; - _zz_102[9] = _zz_101; - _zz_102[8] = _zz_101; - _zz_102[7] = _zz_101; - _zz_102[6] = _zz_101; - _zz_102[5] = _zz_101; - _zz_102[4] = _zz_101; - _zz_102[3] = _zz_101; - _zz_102[2] = _zz_101; - _zz_102[1] = _zz_101; - _zz_102[0] = _zz_101; - end - - assign _zz_103 = _zz_201[11]; + assign _zz_103 = _zz_205[19]; always @ (*) begin - _zz_104[19] = _zz_103; - _zz_104[18] = _zz_103; - _zz_104[17] = _zz_103; - _zz_104[16] = _zz_103; - _zz_104[15] = _zz_103; - _zz_104[14] = _zz_103; - _zz_104[13] = _zz_103; - _zz_104[12] = _zz_103; - _zz_104[11] = _zz_103; _zz_104[10] = _zz_103; _zz_104[9] = _zz_103; _zz_104[8] = _zz_103; @@ -2962,8 +3108,9 @@ module VexRiscv ( _zz_104[0] = _zz_103; end - assign _zz_105 = _zz_202[11]; + assign _zz_105 = _zz_206[11]; always @ (*) begin + _zz_106[19] = _zz_105; _zz_106[18] = _zz_105; _zz_106[17] = _zz_105; _zz_106[16] = _zz_105; @@ -2985,21 +3132,44 @@ module VexRiscv ( _zz_106[0] = _zz_105; end + assign _zz_107 = _zz_207[11]; + always @ (*) begin + _zz_108[18] = _zz_107; + _zz_108[17] = _zz_107; + _zz_108[16] = _zz_107; + _zz_108[15] = _zz_107; + _zz_108[14] = _zz_107; + _zz_108[13] = _zz_107; + _zz_108[12] = _zz_107; + _zz_108[11] = _zz_107; + _zz_108[10] = _zz_107; + _zz_108[9] = _zz_107; + _zz_108[8] = _zz_107; + _zz_108[7] = _zz_107; + _zz_108[6] = _zz_107; + _zz_108[5] = _zz_107; + _zz_108[4] = _zz_107; + _zz_108[3] = _zz_107; + _zz_108[2] = _zz_107; + _zz_108[1] = _zz_107; + _zz_108[0] = _zz_107; + end + always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_107 = {{_zz_102,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_109 = {{_zz_104,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_107 = {_zz_104,execute_INSTRUCTION[31 : 20]}; + _zz_109 = {_zz_106,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_107 = {{_zz_106,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_109 = {{_zz_108,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_107; + assign execute_BranchPlugin_branch_src2 = _zz_109; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; @@ -3012,9 +3182,9 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_108 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_109 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_110 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_110 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_111 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_112 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); always @ (*) begin @@ -3157,7 +3327,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_157)begin + if(_zz_153)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3176,14 +3346,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_158)begin + if(_zz_154)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_158)begin + if(_zz_154)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3198,14 +3368,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_157)begin + if(_zz_153)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_157)begin + if(_zz_153)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -3214,7 +3384,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_167) + case(_zz_163) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3225,70 +3395,72 @@ module VexRiscv ( end assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_141)begin - if(_zz_146)begin - memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; + case(_zz_155) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; end - end - end - - always @ (*) begin - memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; - if((! memory_arbitration_isStuck))begin - memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; - end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase end - assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); - assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); always @ (*) begin - if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; - end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_204); - end - if(memory_MulDivIterativePlugin_mul_counter_willClear)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; - end + case(_zz_155) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase end - assign _zz_111 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_112 = ((execute_IS_MUL && _zz_111) || 1'b0); - always @ (*) begin - _zz_113[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_113[31 : 0] = execute_RS1; - end - - assign _zz_115 = (_zz_114 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_115 != 32'h0); - assign _zz_25 = decode_SRC1_CTRL; - assign _zz_23 = _zz_47; - assign _zz_35 = decode_to_execute_SRC1_CTRL; - assign _zz_22 = decode_SRC2_CTRL; - assign _zz_20 = _zz_46; - assign _zz_34 = decode_to_execute_SRC2_CTRL; - assign _zz_19 = decode_ALU_CTRL; - assign _zz_17 = _zz_45; - assign _zz_36 = decode_to_execute_ALU_CTRL; - assign _zz_16 = decode_ALU_BITWISE_CTRL; - assign _zz_14 = _zz_44; - assign _zz_37 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_13 = decode_SHIFT_CTRL; - assign _zz_11 = _zz_43; - assign _zz_32 = decode_to_execute_SHIFT_CTRL; + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_208) + $signed(_zz_209)); + assign _zz_114 = (_zz_113 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_114 != 32'h0); + assign _zz_27 = decode_SRC1_CTRL; + assign _zz_25 = _zz_50; + assign _zz_38 = decode_to_execute_SRC1_CTRL; + assign _zz_24 = decode_SRC2_CTRL; + assign _zz_22 = _zz_49; + assign _zz_37 = decode_to_execute_SRC2_CTRL; + assign _zz_21 = decode_ALU_CTRL; + assign _zz_19 = _zz_48; + assign _zz_39 = decode_to_execute_ALU_CTRL; + assign _zz_18 = decode_ALU_BITWISE_CTRL; + assign _zz_16 = _zz_47; + assign _zz_40 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_15 = decode_SHIFT_CTRL; + assign _zz_12 = execute_SHIFT_CTRL; + assign _zz_13 = _zz_46; + assign _zz_35 = decode_to_execute_SHIFT_CTRL; + assign _zz_34 = execute_to_memory_SHIFT_CTRL; assign _zz_10 = decode_BRANCH_CTRL; - assign _zz_8 = _zz_42; - assign _zz_30 = decode_to_execute_BRANCH_CTRL; + assign _zz_8 = _zz_45; + assign _zz_32 = decode_to_execute_BRANCH_CTRL; assign _zz_7 = decode_ENV_CTRL; assign _zz_4 = execute_ENV_CTRL; assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_41; - assign _zz_28 = decode_to_execute_ENV_CTRL; - assign _zz_27 = execute_to_memory_ENV_CTRL; - assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign _zz_5 = _zz_44; + assign _zz_30 = decode_to_execute_ENV_CTRL; + assign _zz_29 = execute_to_memory_ENV_CTRL; + assign _zz_31 = memory_to_writeBack_ENV_CTRL; assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -3310,105 +3482,105 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_116 = 32'h0; + _zz_115 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_116[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_116[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_116[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_115[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_115[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_115[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_117 = 32'h0; + _zz_116 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_117[11 : 11] = CsrPlugin_mip_MEIP; - _zz_117[7 : 7] = CsrPlugin_mip_MTIP; - _zz_117[3 : 3] = CsrPlugin_mip_MSIP; + _zz_116[11 : 11] = CsrPlugin_mip_MEIP; + _zz_116[7 : 7] = CsrPlugin_mip_MTIP; + _zz_116[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_118 = 32'h0; + _zz_117 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_118[11 : 11] = CsrPlugin_mie_MEIE; - _zz_118[7 : 7] = CsrPlugin_mie_MTIE; - _zz_118[3 : 3] = CsrPlugin_mie_MSIE; + _zz_117[11 : 11] = CsrPlugin_mie_MEIE; + _zz_117[7 : 7] = CsrPlugin_mie_MTIE; + _zz_117[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_119 = 32'h0; + _zz_118 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_119[31 : 0] = CsrPlugin_mepc; + _zz_118[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_120 = 32'h0; + _zz_119 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_120[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_120[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_119[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_119[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_121 = 32'h0; + _zz_120 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_121[31 : 0] = CsrPlugin_mtval; + _zz_120[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_122 = 32'h0; + _zz_121 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_122[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_121[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_123 = 32'h0; + _zz_122 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_123[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_122[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_124 = 32'h0; + _zz_123 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_124[31 : 0] = _zz_114; + _zz_123[31 : 0] = _zz_113; end end always @ (*) begin - _zz_125 = 32'h0; + _zz_124 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_125[31 : 0] = _zz_115; + _zz_124[31 : 0] = _zz_114; end end - assign execute_CsrPlugin_readData = ((((_zz_116 | _zz_117) | (_zz_118 | _zz_119)) | ((_zz_120 | _zz_121) | (_zz_122 | _zz_123))) | (_zz_124 | _zz_125)); - assign iBusWishbone_ADR = {_zz_221,_zz_126}; - assign iBusWishbone_CTI = ((_zz_126 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = ((((_zz_115 | _zz_116) | (_zz_117 | _zz_118)) | ((_zz_119 | _zz_120) | (_zz_121 | _zz_122))) | (_zz_123 | _zz_124)); + assign iBusWishbone_ADR = {_zz_218,_zz_125}; + assign iBusWishbone_CTI = ((_zz_125 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_159)begin + if(_zz_156)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_159)begin + if(_zz_156)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_127; + assign iBus_rsp_valid = _zz_126; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; @@ -3423,19 +3595,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_128 = 4'b0001; + _zz_127 = 4'b0001; end 2'b01 : begin - _zz_128 = 4'b0011; + _zz_127 = 4'b0011; end default : begin - _zz_128 = 4'b1111; + _zz_127 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_128 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_127 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -3455,18 +3627,17 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_59 <= 1'b0; - _zz_61 <= 1'b0; + _zz_62 <= 1'b0; + _zz_64 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_63; + IBusCachedPlugin_rspCounter <= _zz_66; IBusCachedPlugin_rspCounter <= 32'h0; - _zz_85 <= 1'b1; - execute_LightShifterPlugin_isActive <= 1'b0; - _zz_96 <= 1'b0; + _zz_86 <= 1'b1; + _zz_98 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3483,13 +3654,12 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; - _zz_114 <= 32'h0; + _zz_113 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_126 <= 3'b000; - _zz_127 <= 1'b0; + _zz_125 <= 3'b000; + _zz_126 <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin @@ -3513,16 +3683,16 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_59 <= 1'b0; + _zz_62 <= 1'b0; end - if(_zz_57)begin - _zz_59 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_60)begin + _zz_62 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_61 <= 1'b0; + _zz_64 <= 1'b0; end if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_61 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + _zz_64 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; @@ -3589,19 +3759,8 @@ module VexRiscv ( end `endif `endif - _zz_85 <= 1'b0; - if(_zz_142)begin - if(_zz_160)begin - execute_LightShifterPlugin_isActive <= 1'b1; - if(execute_LightShifterPlugin_done)begin - execute_LightShifterPlugin_isActive <= 1'b0; - end - end - end - if(execute_arbitration_removeIt)begin - execute_LightShifterPlugin_isActive <= 1'b0; - end - _zz_96 <= (_zz_39 && writeBack_arbitration_isFiring); + _zz_86 <= 1'b0; + _zz_98 <= (_zz_42 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -3623,14 +3782,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_161)begin - if(_zz_162)begin + if(_zz_157)begin + if(_zz_158)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_163)begin + if(_zz_159)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_164)begin + if(_zz_160)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -3654,7 +3813,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_147)begin + if(_zz_143)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3665,8 +3824,8 @@ module VexRiscv ( end endcase end - if(_zz_148)begin - case(_zz_149) + if(_zz_144)begin + case(_zz_145) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3676,8 +3835,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_110,{_zz_109,_zz_108}} != 3'b000) || CsrPlugin_thirdPartyWake); - memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; + execute_CsrPlugin_wfiWake <= (({_zz_112,{_zz_111,_zz_110}} != 3'b000) || CsrPlugin_thirdPartyWake); if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; end @@ -3699,29 +3857,29 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_215[0]; - CsrPlugin_mstatus_MIE <= _zz_216[0]; + CsrPlugin_mstatus_MPIE <= _zz_212[0]; + CsrPlugin_mstatus_MIE <= _zz_213[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_218[0]; - CsrPlugin_mie_MTIE <= _zz_219[0]; - CsrPlugin_mie_MSIE <= _zz_220[0]; + CsrPlugin_mie_MEIE <= _zz_215[0]; + CsrPlugin_mie_MTIE <= _zz_216[0]; + CsrPlugin_mie_MSIE <= _zz_217[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_114 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_113 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_159)begin + if(_zz_156)begin if(iBusWishbone_ACK)begin - _zz_126 <= (_zz_126 + 3'b001); + _zz_125 <= (_zz_125 + 3'b001); end end - _zz_127 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_165)begin + _zz_126 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_161)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -3733,7 +3891,7 @@ module VexRiscv ( always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_62 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_65 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; @@ -3741,12 +3899,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_142)begin - if(_zz_160)begin - execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); - end - end - _zz_97 <= _zz_38[11 : 7]; + _zz_99 <= _zz_41[11 : 7]; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -3766,21 +3919,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusSimplePlugin_memoryExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusSimplePlugin_memoryExceptionPort_payload_badAddr; end - if(_zz_161)begin - if(_zz_162)begin + if(_zz_157)begin + if(_zz_158)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_163)begin + if(_zz_159)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_164)begin + if(_zz_160)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_147)begin + if(_zz_143)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -3794,23 +3947,12 @@ module VexRiscv ( end endcase end - if(_zz_141)begin - if(_zz_146)begin - memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_205,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); - end - end - if((! memory_arbitration_isStuck))begin - memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_112 ? (~ _zz_113) : _zz_113) + _zz_212); - memory_MulDivIterativePlugin_rs2 <= ((_zz_111 ? (~ execute_RS2) : execute_RS2) + _zz_214); - end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin decode_to_execute_PC <= decode_PC; end if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_33; + execute_to_memory_PC <= _zz_36; end if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin memory_to_writeBack_PC <= memory_PC; @@ -3831,10 +3973,10 @@ module VexRiscv ( execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_49; + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_24; + decode_to_execute_SRC1_CTRL <= _zz_26; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; @@ -3849,7 +3991,7 @@ module VexRiscv ( memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_21; + decode_to_execute_SRC2_CTRL <= _zz_23; end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; @@ -3879,16 +4021,19 @@ module VexRiscv ( memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_18; + decode_to_execute_ALU_CTRL <= _zz_20; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_15; + decode_to_execute_ALU_BITWISE_CTRL <= _zz_17; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_12; + decode_to_execute_SHIFT_CTRL <= _zz_14; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_11; end if((! execute_arbitration_isStuck))begin decode_to_execute_BRANCH_CTRL <= _zz_9; @@ -3911,11 +4056,8 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; end if((! execute_arbitration_isStuck))begin decode_to_execute_RS1 <= decode_RS1; @@ -3952,11 +4094,14 @@ module VexRiscv ( execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_28; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_26; + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_33; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end if((! memory_arbitration_isStuck))begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; @@ -3964,9 +4109,27 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end @@ -4002,7 +4165,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_217[0]; + CsrPlugin_mip_MSIP <= _zz_214[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -4017,7 +4180,7 @@ module VexRiscv ( end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_165)begin + if(_zz_161)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; @@ -4071,12 +4234,12 @@ module InstructionCache ( input reset ); reg [31:0] _zz_9; - reg [24:0] _zz_10; + reg [22:0] _zz_10; wire _zz_11; wire _zz_12; wire [0:0] _zz_13; wire [0:0] _zz_14; - wire [24:0] _zz_15; + wire [22:0] _zz_15; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -4084,7 +4247,7 @@ module InstructionCache ( (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; - reg [4:0] lineLoader_flushCounter; + reg [6:0] lineLoader_flushCounter; reg _zz_3; reg lineLoader_cmdSent; reg lineLoader_wayToAllocate_willIncrement; @@ -4093,23 +4256,23 @@ module InstructionCache ( wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; wire lineLoader_write_tag_0_valid; - wire [3:0] lineLoader_write_tag_0_payload_address; + wire [5:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [22:0] lineLoader_write_tag_0_payload_data_address; + wire [20:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [6:0] lineLoader_write_data_0_payload_address; + wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [6:0] _zz_4; + wire [8:0] _zz_4; wire _zz_5; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [3:0] _zz_6; + wire [5:0] _zz_6; wire _zz_7; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [22:0] fetchStage_read_waysValues_0_tag_address; - wire [24:0] _zz_8; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_8; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; @@ -4127,10 +4290,10 @@ module InstructionCache ( reg decodeStage_mmuRsp_bypassTranslation; reg decodeStage_hit_valid; reg decodeStage_hit_error; - (* ram_style = "block" *) reg [31:0] banks_0 [0:127]; - (* ram_style = "block" *) reg [24:0] ways_0_tags [0:15]; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_11 = (! lineLoader_flushCounter[4]); + assign _zz_11 = (! lineLoader_flushCounter[6]); assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); assign _zz_13 = _zz_8[0 : 0]; assign _zz_14 = _zz_8[1 : 1]; @@ -4208,25 +4371,25 @@ module InstructionCache ( assign lineLoader_wayToAllocate_willClear = 1'b0; assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[4])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[4] ? lineLoader_address[8 : 5] : lineLoader_flushCounter[3 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[4]; + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 9]; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[8 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[8 : 2]; + assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; assign _zz_5 = (! io_cpu_fetch_isStuck); assign fetchStage_read_banksValue_0_dataMem = _zz_9; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[8 : 5]; + assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; assign _zz_7 = (! io_cpu_fetch_isStuck); assign _zz_8 = _zz_10; assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[24 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 9])); + assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; @@ -4282,11 +4445,11 @@ module InstructionCache ( lineLoader_address <= io_cpu_fill_payload; end if(_zz_11)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 5'h01); + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[4]; + _zz_3 <= lineLoader_flushCounter[6]; if(_zz_12)begin - lineLoader_flushCounter <= 5'h0; + lineLoader_flushCounter <= 7'h0; end if((! io_cpu_decode_isStuck))begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml index fa5fb80..b55f8e5 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.yaml @@ -1,4 +1,4 @@ iBus: !!vexriscv.BusReport flushInstructions: [4111, 19, 19, 19] - info: !!vexriscv.CacheReport {bytePerLine: 32, size: 512} + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v index 3c21cd3..1371328 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 43e13174d8583db5f4cd45d2b3515bc206a0010a +// Git hash : d8ec2d84c3160c3a9131beef2db359dce7a2e4a4 `define Input2Kind_defaultEncoding_type [0:0] @@ -86,6 +86,7 @@ module VexRiscv ( input clk, input reset ); + wire _zz_143; wire _zz_144; wire _zz_145; wire _zz_146; @@ -93,11 +94,10 @@ module VexRiscv ( wire _zz_148; wire _zz_149; wire _zz_150; - wire _zz_151; - reg _zz_152; + reg _zz_151; + reg [31:0] _zz_152; reg [31:0] _zz_153; reg [31:0] _zz_154; - reg [31:0] _zz_155; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -110,22 +110,23 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_155; wire _zz_156; wire _zz_157; wire _zz_158; wire _zz_159; wire _zz_160; - wire _zz_161; + wire [1:0] _zz_161; wire _zz_162; wire _zz_163; wire _zz_164; - wire [1:0] _zz_165; + wire _zz_165; wire _zz_166; wire _zz_167; wire _zz_168; wire _zz_169; wire _zz_170; - wire _zz_171; + wire [1:0] _zz_171; wire _zz_172; wire _zz_173; wire _zz_174; @@ -133,21 +134,21 @@ module VexRiscv ( wire _zz_176; wire _zz_177; wire _zz_178; - wire _zz_179; + wire [1:0] _zz_179; wire _zz_180; - wire _zz_181; - wire _zz_182; - wire [1:0] _zz_183; - wire _zz_184; - wire [0:0] _zz_185; - wire [0:0] _zz_186; - wire [0:0] _zz_187; - wire [0:0] _zz_188; - wire [0:0] _zz_189; - wire [0:0] _zz_190; - wire [0:0] _zz_191; - wire [0:0] _zz_192; - wire [0:0] _zz_193; + wire [1:0] _zz_181; + wire [51:0] _zz_182; + wire [51:0] _zz_183; + wire [51:0] _zz_184; + wire [32:0] _zz_185; + wire [51:0] _zz_186; + wire [49:0] _zz_187; + wire [51:0] _zz_188; + wire [49:0] _zz_189; + wire [51:0] _zz_190; + wire [32:0] _zz_191; + wire [31:0] _zz_192; + wire [32:0] _zz_193; wire [0:0] _zz_194; wire [0:0] _zz_195; wire [0:0] _zz_196; @@ -155,213 +156,222 @@ module VexRiscv ( wire [0:0] _zz_198; wire [0:0] _zz_199; wire [0:0] _zz_200; - wire [2:0] _zz_201; - wire [2:0] _zz_202; - wire [31:0] _zz_203; + wire [0:0] _zz_201; + wire [0:0] _zz_202; + wire [0:0] _zz_203; wire [0:0] _zz_204; - wire [2:0] _zz_205; - wire [4:0] _zz_206; - wire [11:0] _zz_207; - wire [11:0] _zz_208; - wire [31:0] _zz_209; + wire [0:0] _zz_205; + wire [0:0] _zz_206; + wire [0:0] _zz_207; + wire [2:0] _zz_208; + wire [2:0] _zz_209; wire [31:0] _zz_210; - wire [31:0] _zz_211; - wire [31:0] _zz_212; - wire [31:0] _zz_213; - wire [31:0] _zz_214; - wire [31:0] _zz_215; + wire [0:0] _zz_211; + wire [2:0] _zz_212; + wire [4:0] _zz_213; + wire [11:0] _zz_214; + wire [11:0] _zz_215; wire [31:0] _zz_216; - wire [32:0] _zz_217; - wire [19:0] _zz_218; - wire [11:0] _zz_219; - wire [11:0] _zz_220; - wire [1:0] _zz_221; - wire [1:0] _zz_222; - wire [9:0] _zz_223; - wire [7:0] _zz_224; - wire [0:0] _zz_225; - wire [5:0] _zz_226; - wire [33:0] _zz_227; - wire [32:0] _zz_228; - wire [33:0] _zz_229; - wire [32:0] _zz_230; - wire [33:0] _zz_231; - wire [32:0] _zz_232; - wire [0:0] _zz_233; - wire [32:0] _zz_234; + wire [31:0] _zz_217; + wire [31:0] _zz_218; + wire [31:0] _zz_219; + wire [31:0] _zz_220; + wire [31:0] _zz_221; + wire [31:0] _zz_222; + wire [19:0] _zz_223; + wire [11:0] _zz_224; + wire [11:0] _zz_225; + wire [1:0] _zz_226; + wire [1:0] _zz_227; + wire [9:0] _zz_228; + wire [7:0] _zz_229; + wire [65:0] _zz_230; + wire [65:0] _zz_231; + wire [31:0] _zz_232; + wire [31:0] _zz_233; + wire [0:0] _zz_234; wire [0:0] _zz_235; - wire [31:0] _zz_236; + wire [0:0] _zz_236; wire [0:0] _zz_237; wire [0:0] _zz_238; wire [0:0] _zz_239; - wire [0:0] _zz_240; - wire [0:0] _zz_241; - wire [0:0] _zz_242; - wire [26:0] _zz_243; - wire _zz_244; - wire _zz_245; - wire [1:0] _zz_246; - wire [31:0] _zz_247; - wire [31:0] _zz_248; - wire [31:0] _zz_249; - wire _zz_250; - wire [0:0] _zz_251; - wire [14:0] _zz_252; - wire [31:0] _zz_253; - wire [31:0] _zz_254; - wire [31:0] _zz_255; - wire _zz_256; - wire [0:0] _zz_257; - wire [8:0] _zz_258; - wire [31:0] _zz_259; - wire [31:0] _zz_260; - wire [31:0] _zz_261; + wire [26:0] _zz_240; + wire _zz_241; + wire _zz_242; + wire [1:0] _zz_243; + wire [31:0] _zz_244; + wire [31:0] _zz_245; + wire [31:0] _zz_246; + wire _zz_247; + wire [0:0] _zz_248; + wire [14:0] _zz_249; + wire [31:0] _zz_250; + wire [31:0] _zz_251; + wire [31:0] _zz_252; + wire _zz_253; + wire [0:0] _zz_254; + wire [8:0] _zz_255; + wire [31:0] _zz_256; + wire [31:0] _zz_257; + wire [31:0] _zz_258; + wire _zz_259; + wire [0:0] _zz_260; + wire [2:0] _zz_261; wire _zz_262; wire [0:0] _zz_263; - wire [2:0] _zz_264; - wire [31:0] _zz_265; - wire [31:0] _zz_266; - wire [0:0] _zz_267; - wire [0:0] _zz_268; - wire _zz_269; - wire [0:0] _zz_270; - wire [24:0] _zz_271; - wire [31:0] _zz_272; + wire [0:0] _zz_264; + wire _zz_265; + wire [0:0] _zz_266; + wire [22:0] _zz_267; + wire [31:0] _zz_268; + wire [31:0] _zz_269; + wire [31:0] _zz_270; + wire [31:0] _zz_271; + wire _zz_272; wire _zz_273; - wire _zz_274; - wire [0:0] _zz_275; - wire [0:0] _zz_276; + wire [1:0] _zz_274; + wire [1:0] _zz_275; + wire _zz_276; wire [0:0] _zz_277; - wire [0:0] _zz_278; - wire _zz_279; - wire [0:0] _zz_280; - wire [19:0] _zz_281; + wire [18:0] _zz_278; + wire [31:0] _zz_279; + wire [31:0] _zz_280; + wire [31:0] _zz_281; wire [31:0] _zz_282; wire [31:0] _zz_283; - wire _zz_284; - wire _zz_285; - wire _zz_286; - wire [2:0] _zz_287; - wire [2:0] _zz_288; + wire [31:0] _zz_284; + wire [0:0] _zz_285; + wire [1:0] _zz_286; + wire [0:0] _zz_287; + wire [0:0] _zz_288; wire _zz_289; wire [0:0] _zz_290; - wire [16:0] _zz_291; + wire [15:0] _zz_291; wire [31:0] _zz_292; wire [31:0] _zz_293; - wire _zz_294; - wire _zz_295; - wire _zz_296; - wire [0:0] _zz_297; - wire [0:0] _zz_298; - wire _zz_299; - wire [0:0] _zz_300; - wire [0:0] _zz_301; - wire _zz_302; - wire [0:0] _zz_303; - wire [13:0] _zz_304; - wire [31:0] _zz_305; + wire [31:0] _zz_294; + wire [31:0] _zz_295; + wire [31:0] _zz_296; + wire [31:0] _zz_297; + wire [31:0] _zz_298; + wire [31:0] _zz_299; + wire _zz_300; + wire [1:0] _zz_301; + wire [1:0] _zz_302; + wire _zz_303; + wire [0:0] _zz_304; + wire [12:0] _zz_305; wire [31:0] _zz_306; wire [31:0] _zz_307; wire [31:0] _zz_308; wire [31:0] _zz_309; wire [31:0] _zz_310; wire [31:0] _zz_311; - wire [31:0] _zz_312; - wire [0:0] _zz_313; - wire [0:0] _zz_314; - wire [1:0] _zz_315; - wire [1:0] _zz_316; - wire _zz_317; - wire [0:0] _zz_318; - wire [11:0] _zz_319; + wire [2:0] _zz_312; + wire [2:0] _zz_313; + wire _zz_314; + wire [0:0] _zz_315; + wire [9:0] _zz_316; + wire [31:0] _zz_317; + wire [31:0] _zz_318; + wire [31:0] _zz_319; wire [31:0] _zz_320; wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [0:0] _zz_326; - wire [1:0] _zz_327; - wire [0:0] _zz_328; - wire [0:0] _zz_329; - wire _zz_330; - wire [0:0] _zz_331; - wire [8:0] _zz_332; + wire _zz_322; + wire [0:0] _zz_323; + wire [2:0] _zz_324; + wire [0:0] _zz_325; + wire [3:0] _zz_326; + wire [5:0] _zz_327; + wire [5:0] _zz_328; + wire _zz_329; + wire [0:0] _zz_330; + wire [5:0] _zz_331; + wire [31:0] _zz_332; wire [31:0] _zz_333; wire [31:0] _zz_334; - wire [31:0] _zz_335; - wire [31:0] _zz_336; - wire [31:0] _zz_337; - wire _zz_338; - wire _zz_339; + wire [0:0] _zz_335; + wire [0:0] _zz_336; + wire _zz_337; + wire [0:0] _zz_338; + wire [1:0] _zz_339; wire [0:0] _zz_340; - wire [1:0] _zz_341; - wire [5:0] _zz_342; - wire [5:0] _zz_343; - wire _zz_344; - wire [0:0] _zz_345; - wire [5:0] _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; + wire [3:0] _zz_341; + wire [0:0] _zz_342; + wire [0:0] _zz_343; + wire [1:0] _zz_344; + wire [1:0] _zz_345; + wire _zz_346; + wire [0:0] _zz_347; + wire [3:0] _zz_348; wire [31:0] _zz_349; wire [31:0] _zz_350; - wire _zz_351; - wire [0:0] _zz_352; - wire [2:0] _zz_353; - wire _zz_354; - wire [0:0] _zz_355; - wire [0:0] _zz_356; - wire [3:0] _zz_357; - wire [3:0] _zz_358; - wire _zz_359; - wire [0:0] _zz_360; - wire [2:0] _zz_361; - wire [31:0] _zz_362; + wire [31:0] _zz_351; + wire [31:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; + wire [31:0] _zz_355; + wire _zz_356; + wire _zz_357; + wire [31:0] _zz_358; + wire [31:0] _zz_359; + wire _zz_360; + wire [0:0] _zz_361; + wire [1:0] _zz_362; wire [31:0] _zz_363; wire [31:0] _zz_364; wire _zz_365; wire [0:0] _zz_366; - wire [0:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; - wire [31:0] _zz_370; - wire _zz_371; - wire [0:0] _zz_372; - wire [1:0] _zz_373; - wire _zz_374; - wire [2:0] _zz_375; - wire [2:0] _zz_376; - wire _zz_377; - wire [0:0] _zz_378; - wire [0:0] _zz_379; + wire [2:0] _zz_367; + wire [0:0] _zz_368; + wire [0:0] _zz_369; + wire _zz_370; + wire [0:0] _zz_371; + wire [1:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; + wire [31:0] _zz_375; + wire [31:0] _zz_376; + wire [31:0] _zz_377; + wire _zz_378; + wire _zz_379; wire [31:0] _zz_380; wire [31:0] _zz_381; wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire [31:0] _zz_384; - wire [31:0] _zz_385; + wire _zz_383; + wire [0:0] _zz_384; + wire [0:0] _zz_385; wire [31:0] _zz_386; wire [31:0] _zz_387; - wire _zz_388; - wire [31:0] _zz_389; - wire _zz_390; - wire [0:0] _zz_391; - wire [0:0] _zz_392; - wire [0:0] _zz_393; - wire [0:0] _zz_394; - wire [1:0] _zz_395; - wire [1:0] _zz_396; - wire [0:0] _zz_397; - wire [0:0] _zz_398; + wire [0:0] _zz_388; + wire [1:0] _zz_389; + wire [1:0] _zz_390; + wire [1:0] _zz_391; + wire _zz_392; + wire _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; wire [31:0] _zz_399; wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; + wire _zz_401; + wire _zz_402; + wire _zz_403; + wire [0:0] _zz_404; + wire [0:0] _zz_405; + wire _zz_406; + wire [51:0] memory_MUL_LOW; wire [31:0] memory_MEMORY_READ_DATA; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; wire writeBack_CfuPlugin_CFU_IN_FLIGHT; wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] execute_SHIFT_RIGHT; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; wire [1:0] memory_MEMORY_ADDRESS_LOW; @@ -371,8 +381,8 @@ module VexRiscv ( wire decode_SRC2_FORCE_ZERO; wire [31:0] decode_RS2; wire [31:0] decode_RS1; - wire decode_IS_RS2_SIGNED; - wire decode_IS_RS1_SIGNED; + wire memory_IS_MUL; + wire execute_IS_MUL; wire decode_IS_MUL; wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; wire `Input2Kind_defaultEncoding_type _zz_1; @@ -392,61 +402,65 @@ module VexRiscv ( wire `BranchCtrlEnum_defaultEncoding_type _zz_11; wire `BranchCtrlEnum_defaultEncoding_type _zz_12; wire `BranchCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_18; wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_21; wire decode_SRC_LESS_UNSIGNED; wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; wire `AluCtrlEnum_defaultEncoding_type _zz_22; + wire `AluCtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `Src2CtrlEnum_defaultEncoding_type _zz_24; wire `Src2CtrlEnum_defaultEncoding_type _zz_25; + wire `Src2CtrlEnum_defaultEncoding_type _zz_26; + wire `Src2CtrlEnum_defaultEncoding_type _zz_27; wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire `Src1CtrlEnum_defaultEncoding_type _zz_30; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; - wire execute_IS_RS1_SIGNED; - wire execute_IS_MUL; - wire execute_IS_RS2_SIGNED; - wire memory_IS_MUL; - reg _zz_29; - reg _zz_30; - reg [31:0] _zz_31; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + reg _zz_31; + reg _zz_32; wire memory_CfuPlugin_CFU_IN_FLIGHT; wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_32; + wire `Input2Kind_defaultEncoding_type _zz_33; wire execute_CfuPlugin_CFU_ENABLE; + reg [31:0] _zz_34; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; + wire `EnvCtrlEnum_defaultEncoding_type _zz_36; wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_defaultEncoding_type _zz_37; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_PC; - wire [31:0] execute_RS1; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire `BranchCtrlEnum_defaultEncoding_type _zz_38; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; @@ -455,43 +469,46 @@ module VexRiscv ( wire [31:0] memory_INSTRUCTION; wire memory_BYPASSABLE_MEMORY_STAGE; wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] _zz_37; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_39; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_38; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_41; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_39; + wire [31:0] _zz_42; wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_40; + wire `Src2CtrlEnum_defaultEncoding_type _zz_43; wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_41; + wire `Src1CtrlEnum_defaultEncoding_type _zz_44; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_42; + wire `AluCtrlEnum_defaultEncoding_type _zz_45; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; - wire [31:0] _zz_44; - wire _zz_45; - reg _zz_46; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; + wire [31:0] _zz_47; + wire _zz_48; + reg _zz_49; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_47; - wire `EnvCtrlEnum_defaultEncoding_type _zz_48; - wire `BranchCtrlEnum_defaultEncoding_type _zz_49; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_50; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_51; - wire `AluCtrlEnum_defaultEncoding_type _zz_52; - wire `Src2CtrlEnum_defaultEncoding_type _zz_53; - wire `Src1CtrlEnum_defaultEncoding_type _zz_54; + wire `Input2Kind_defaultEncoding_type _zz_50; + wire `EnvCtrlEnum_defaultEncoding_type _zz_51; + wire `BranchCtrlEnum_defaultEncoding_type _zz_52; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_53; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_54; + wire `AluCtrlEnum_defaultEncoding_type _zz_55; + wire `Src2CtrlEnum_defaultEncoding_type _zz_56; + wire `Src1CtrlEnum_defaultEncoding_type _zz_57; wire writeBack_MEMORY_STORE; - reg [31:0] _zz_55; + reg [31:0] _zz_58; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; @@ -520,7 +537,7 @@ module VexRiscv ( wire execute_MMU_RSP2_refilling; wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; - wire [31:0] execute_RS2; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; @@ -530,8 +547,8 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_56; - reg [31:0] _zz_57; + reg [31:0] _zz_59; + reg [31:0] _zz_60; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -652,10 +669,10 @@ module VexRiscv ( wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_58; - wire [2:0] _zz_59; - wire _zz_60; - wire _zz_61; + wire [2:0] _zz_61; + wire [2:0] _zz_62; + wire _zz_63; + wire _zz_64; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; @@ -692,16 +709,16 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_62; - wire _zz_63; - wire _zz_64; - wire IBusCachedPlugin_iBusRsp_flush; wire _zz_65; wire _zz_66; - reg _zz_67; + wire _zz_67; + wire IBusCachedPlugin_iBusRsp_flush; wire _zz_68; - reg _zz_69; - reg [31:0] _zz_70; + wire _zz_69; + reg _zz_70; + wire _zz_71; + reg _zz_72; + reg [31:0] _zz_73; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -721,7 +738,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_71; + wire [31:0] _zz_74; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -738,33 +755,31 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - wire _zz_72; + wire _zz_75; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_73; - reg [3:0] _zz_74; + reg [31:0] _zz_76; + reg [3:0] _zz_77; wire [3:0] execute_DBusSimplePlugin_formalMask; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_75; - reg [31:0] _zz_76; - wire _zz_77; - reg [31:0] _zz_78; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [31:0] _zz_79; + wire _zz_78; + reg [31:0] _zz_79; wire _zz_80; - wire _zz_81; - wire _zz_82; + reg [31:0] _zz_81; + reg [31:0] writeBack_DBusSimplePlugin_rspFormated; + wire [29:0] _zz_82; wire _zz_83; wire _zz_84; wire _zz_85; wire _zz_86; - wire `Src1CtrlEnum_defaultEncoding_type _zz_87; - wire `Src2CtrlEnum_defaultEncoding_type _zz_88; - wire `AluCtrlEnum_defaultEncoding_type _zz_89; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_90; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_91; - wire `BranchCtrlEnum_defaultEncoding_type _zz_92; - wire `EnvCtrlEnum_defaultEncoding_type _zz_93; - wire `Input2Kind_defaultEncoding_type _zz_94; + wire _zz_87; + wire `Src1CtrlEnum_defaultEncoding_type _zz_88; + wire `Src2CtrlEnum_defaultEncoding_type _zz_89; + wire `AluCtrlEnum_defaultEncoding_type _zz_90; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_91; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_92; + wire `BranchCtrlEnum_defaultEncoding_type _zz_93; + wire `EnvCtrlEnum_defaultEncoding_type _zz_94; + wire `Input2Kind_defaultEncoding_type _zz_95; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -772,40 +787,37 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_95; + reg _zz_96; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_96; reg [31:0] _zz_97; - wire _zz_98; - reg [19:0] _zz_99; - wire _zz_100; - reg [19:0] _zz_101; - reg [31:0] _zz_102; + reg [31:0] _zz_98; + wire _zz_99; + reg [19:0] _zz_100; + wire _zz_101; + reg [19:0] _zz_102; + reg [31:0] _zz_103; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; - reg execute_LightShifterPlugin_isActive; - wire execute_LightShifterPlugin_isShift; - reg [4:0] execute_LightShifterPlugin_amplitudeReg; - wire [4:0] execute_LightShifterPlugin_amplitude; - wire [31:0] execute_LightShifterPlugin_shiftInput; - wire execute_LightShifterPlugin_done; - reg [31:0] _zz_103; - reg _zz_104; - reg _zz_105; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_104; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_105; reg _zz_106; - reg [4:0] _zz_107; + reg _zz_107; + reg _zz_108; + reg [4:0] _zz_109; wire execute_BranchPlugin_eq; - wire [2:0] _zz_108; - reg _zz_109; - reg _zz_110; + wire [2:0] _zz_110; + reg _zz_111; + reg _zz_112; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_111; - reg [10:0] _zz_112; wire _zz_113; - reg [19:0] _zz_114; + reg [10:0] _zz_114; wire _zz_115; - reg [18:0] _zz_116; - reg [31:0] _zz_117; + reg [19:0] _zz_116; + wire _zz_117; + reg [18:0] _zz_118; + reg [31:0] _zz_119; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -827,9 +839,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_118; - wire _zz_119; wire _zz_120; + wire _zz_121; + wire _zz_122; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -842,8 +854,8 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_121; - wire _zz_122; + wire [1:0] _zz_123; + wire _zz_124; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -876,9 +888,9 @@ module VexRiscv ( reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_123; - reg [23:0] _zz_124; - reg [31:0] _zz_125; + wire _zz_125; + reg [23:0] _zz_126; + reg [31:0] _zz_127; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -886,22 +898,20 @@ module VexRiscv ( reg CfuPlugin_bus_rsp_s2mPipe_rValid; reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; - reg [32:0] memory_MulDivIterativePlugin_rs1; - reg [31:0] memory_MulDivIterativePlugin_rs2; - reg [64:0] memory_MulDivIterativePlugin_accumulator; - wire memory_MulDivIterativePlugin_frontendOk; - reg memory_MulDivIterativePlugin_mul_counter_willIncrement; - reg memory_MulDivIterativePlugin_mul_counter_willClear; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_valueNext; - reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; - wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; - wire memory_MulDivIterativePlugin_mul_counter_willOverflow; - wire _zz_126; - wire _zz_127; - reg [32:0] _zz_128; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_129; - wire [31:0] _zz_130; + reg [31:0] _zz_128; + wire [31:0] _zz_129; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -930,6 +940,7 @@ module VexRiscv ( reg decode_to_execute_SRC_LESS_UNSIGNED; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; reg decode_to_execute_IS_CSR; reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; @@ -939,8 +950,7 @@ module VexRiscv ( reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; reg decode_to_execute_IS_MUL; reg execute_to_memory_IS_MUL; - reg decode_to_execute_IS_RS1_SIGNED; - reg decode_to_execute_IS_RS2_SIGNED; + reg memory_to_writeBack_IS_MUL; reg [31:0] decode_to_execute_RS1; reg [31:0] decode_to_execute_RS2; reg decode_to_execute_SRC2_FORCE_ZERO; @@ -960,9 +970,16 @@ module VexRiscv ( reg execute_to_memory_MMU_RSP2_bypassTranslation; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + reg [51:0] memory_to_writeBack_MUL_LOW; reg execute_CsrPlugin_csr_768; reg execute_CsrPlugin_csr_836; reg execute_CsrPlugin_csr_772; @@ -974,6 +991,7 @@ module VexRiscv ( reg execute_CsrPlugin_csr_2944; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_130; reg [31:0] _zz_131; reg [31:0] _zz_132; reg [31:0] _zz_133; @@ -983,9 +1001,8 @@ module VexRiscv ( reg [31:0] _zz_137; reg [31:0] _zz_138; reg [31:0] _zz_139; - reg [31:0] _zz_140; - reg [2:0] _zz_141; - reg _zz_142; + reg [2:0] _zz_140; + reg _zz_141; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -999,7 +1016,7 @@ module VexRiscv ( reg [31:0] dBus_cmd_halfPipe_regs_payload_address; reg [31:0] dBus_cmd_halfPipe_regs_payload_data; reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_143; + reg [3:0] _zz_142; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] _zz_1_string; @@ -1017,67 +1034,72 @@ module VexRiscv ( reg [31:0] _zz_11_string; reg [31:0] _zz_12_string; reg [31:0] _zz_13_string; - reg [71:0] decode_SHIFT_CTRL_string; reg [71:0] _zz_14_string; reg [71:0] _zz_15_string; + reg [71:0] decode_SHIFT_CTRL_string; reg [71:0] _zz_16_string; + reg [71:0] _zz_17_string; + reg [71:0] _zz_18_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_17_string; - reg [39:0] _zz_18_string; reg [39:0] _zz_19_string; + reg [39:0] _zz_20_string; + reg [39:0] _zz_21_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_20_string; - reg [63:0] _zz_21_string; reg [63:0] _zz_22_string; + reg [63:0] _zz_23_string; + reg [63:0] _zz_24_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_23_string; - reg [23:0] _zz_24_string; reg [23:0] _zz_25_string; + reg [23:0] _zz_26_string; + reg [23:0] _zz_27_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_26_string; - reg [95:0] _zz_27_string; reg [95:0] _zz_28_string; + reg [95:0] _zz_29_string; + reg [95:0] _zz_30_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_32_string; - reg [39:0] memory_ENV_CTRL_string; reg [39:0] _zz_33_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_35_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34_string; + reg [39:0] _zz_36_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_37_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_36_string; + reg [31:0] _zz_38_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_40_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_38_string; + reg [71:0] _zz_41_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_40_string; + reg [23:0] _zz_43_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_41_string; + reg [95:0] _zz_44_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_42_string; + reg [63:0] _zz_45_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_43_string; - reg [39:0] _zz_47_string; - reg [39:0] _zz_48_string; - reg [31:0] _zz_49_string; - reg [71:0] _zz_50_string; + reg [39:0] _zz_46_string; + reg [39:0] _zz_50_string; reg [39:0] _zz_51_string; - reg [63:0] _zz_52_string; - reg [23:0] _zz_53_string; - reg [95:0] _zz_54_string; - reg [95:0] _zz_87_string; - reg [23:0] _zz_88_string; - reg [63:0] _zz_89_string; - reg [39:0] _zz_90_string; - reg [71:0] _zz_91_string; - reg [31:0] _zz_92_string; - reg [39:0] _zz_93_string; + reg [31:0] _zz_52_string; + reg [71:0] _zz_53_string; + reg [39:0] _zz_54_string; + reg [63:0] _zz_55_string; + reg [23:0] _zz_56_string; + reg [95:0] _zz_57_string; + reg [95:0] _zz_88_string; + reg [23:0] _zz_89_string; + reg [63:0] _zz_90_string; + reg [39:0] _zz_91_string; + reg [71:0] _zz_92_string; + reg [31:0] _zz_93_string; reg [39:0] _zz_94_string; + reg [39:0] _zz_95_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; reg [31:0] decode_to_execute_BRANCH_CTRL_string; reg [39:0] decode_to_execute_ENV_CTRL_string; reg [39:0] execute_to_memory_ENV_CTRL_string; @@ -1087,281 +1109,284 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_156 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_157 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_158 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_159 = ((_zz_149 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_160 = ((_zz_149 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_161 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_162 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_163 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_164 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_165 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_166 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_167 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_168 = (1'b1 || (! 1'b1)); - assign _zz_169 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_170 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_171 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_172 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_173 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_174 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_175 = (iBus_cmd_valid || (_zz_141 != 3'b000)); - assign _zz_176 = (! execute_arbitration_isStuckByOthers); - assign _zz_177 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_178 = ((_zz_118 && 1'b1) && (! 1'b0)); - assign _zz_179 = ((_zz_119 && 1'b1) && (! 1'b0)); - assign _zz_180 = ((_zz_120 && 1'b1) && (! 1'b0)); - assign _zz_181 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_182 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_183 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_184 = execute_INSTRUCTION[13]; - assign _zz_185 = _zz_79[31 : 31]; - assign _zz_186 = _zz_79[30 : 30]; - assign _zz_187 = _zz_79[29 : 29]; - assign _zz_188 = _zz_79[27 : 27]; - assign _zz_189 = _zz_79[24 : 24]; - assign _zz_190 = _zz_79[15 : 15]; - assign _zz_191 = _zz_79[11 : 11]; - assign _zz_192 = _zz_79[10 : 10]; - assign _zz_193 = _zz_79[9 : 9]; - assign _zz_194 = _zz_79[12 : 12]; - assign _zz_195 = _zz_79[5 : 5]; - assign _zz_196 = _zz_79[3 : 3]; - assign _zz_197 = _zz_79[18 : 18]; - assign _zz_198 = _zz_79[8 : 8]; - assign _zz_199 = _zz_79[4 : 4]; - assign _zz_200 = _zz_79[0 : 0]; - assign _zz_201 = (_zz_58 - 3'b001); - assign _zz_202 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_203 = {29'd0, _zz_202}; - assign _zz_204 = execute_SRC_LESS; - assign _zz_205 = 3'b100; - assign _zz_206 = execute_INSTRUCTION[19 : 15]; - assign _zz_207 = execute_INSTRUCTION[31 : 20]; - assign _zz_208 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_209 = ($signed(_zz_210) + $signed(_zz_213)); - assign _zz_210 = ($signed(_zz_211) + $signed(_zz_212)); - assign _zz_211 = execute_SRC1; - assign _zz_212 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_213 = (execute_SRC_USE_SUB_LESS ? _zz_214 : _zz_215); - assign _zz_214 = 32'h00000001; - assign _zz_215 = 32'h0; - assign _zz_216 = (_zz_217 >>> 1); - assign _zz_217 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_218 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_219 = execute_INSTRUCTION[31 : 20]; - assign _zz_220 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_221 = (_zz_121 & (~ _zz_222)); - assign _zz_222 = (_zz_121 - 2'b01); - assign _zz_223 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_224 = execute_INSTRUCTION[31 : 24]; - assign _zz_225 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_226 = {5'd0, _zz_225}; - assign _zz_227 = (_zz_229 + _zz_231); - assign _zz_228 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_229 = {{1{_zz_228[32]}}, _zz_228}; - assign _zz_230 = _zz_232; - assign _zz_231 = {{1{_zz_230[32]}}, _zz_230}; - assign _zz_232 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_233 = _zz_127; - assign _zz_234 = {32'd0, _zz_233}; - assign _zz_235 = _zz_126; - assign _zz_236 = {31'd0, _zz_235}; - assign _zz_237 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_238 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_155 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_156 = ((_zz_148 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_157 = ((_zz_148 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_158 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_159 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_160 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_161 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_162 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + assign _zz_163 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_164 = (1'b1 || (! 1'b1)); + assign _zz_165 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_166 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_167 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_168 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_169 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_170 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_171 = execute_INSTRUCTION[13 : 12]; + assign _zz_172 = (iBus_cmd_valid || (_zz_140 != 3'b000)); + assign _zz_173 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_174 = ((_zz_120 && 1'b1) && (! 1'b0)); + assign _zz_175 = ((_zz_121 && 1'b1) && (! 1'b0)); + assign _zz_176 = ((_zz_122 && 1'b1) && (! 1'b0)); + assign _zz_177 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_178 = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_179 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_180 = execute_INSTRUCTION[13]; + assign _zz_181 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_182 = ($signed(_zz_183) + $signed(_zz_188)); + assign _zz_183 = ($signed(_zz_184) + $signed(_zz_186)); + assign _zz_184 = 52'h0; + assign _zz_185 = {1'b0,memory_MUL_LL}; + assign _zz_186 = {{19{_zz_185[32]}}, _zz_185}; + assign _zz_187 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_188 = {{2{_zz_187[49]}}, _zz_187}; + assign _zz_189 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_190 = {{2{_zz_189[49]}}, _zz_189}; + assign _zz_191 = ($signed(_zz_193) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_192 = _zz_191[31 : 0]; + assign _zz_193 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_194 = _zz_82[29 : 29]; + assign _zz_195 = _zz_82[27 : 27]; + assign _zz_196 = _zz_82[24 : 24]; + assign _zz_197 = _zz_82[15 : 15]; + assign _zz_198 = _zz_82[11 : 11]; + assign _zz_199 = _zz_82[10 : 10]; + assign _zz_200 = _zz_82[9 : 9]; + assign _zz_201 = _zz_82[12 : 12]; + assign _zz_202 = _zz_82[5 : 5]; + assign _zz_203 = _zz_82[3 : 3]; + assign _zz_204 = _zz_82[18 : 18]; + assign _zz_205 = _zz_82[8 : 8]; + assign _zz_206 = _zz_82[4 : 4]; + assign _zz_207 = _zz_82[0 : 0]; + assign _zz_208 = (_zz_61 - 3'b001); + assign _zz_209 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_210 = {29'd0, _zz_209}; + assign _zz_211 = execute_SRC_LESS; + assign _zz_212 = 3'b100; + assign _zz_213 = execute_INSTRUCTION[19 : 15]; + assign _zz_214 = execute_INSTRUCTION[31 : 20]; + assign _zz_215 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_216 = ($signed(_zz_217) + $signed(_zz_220)); + assign _zz_217 = ($signed(_zz_218) + $signed(_zz_219)); + assign _zz_218 = execute_SRC1; + assign _zz_219 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_220 = (execute_SRC_USE_SUB_LESS ? _zz_221 : _zz_222); + assign _zz_221 = 32'h00000001; + assign _zz_222 = 32'h0; + assign _zz_223 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_224 = execute_INSTRUCTION[31 : 20]; + assign _zz_225 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_226 = (_zz_123 & (~ _zz_227)); + assign _zz_227 = (_zz_123 - 2'b01); + assign _zz_228 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_229 = execute_INSTRUCTION[31 : 24]; + assign _zz_230 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_231 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_232 = writeBack_MUL_LOW[31 : 0]; + assign _zz_233 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_234 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_235 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_236 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_237 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_238 = execute_CsrPlugin_writeData[7 : 7]; assign _zz_239 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_240 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_241 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_242 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_243 = (iBus_cmd_payload_address >>> 5); - assign _zz_244 = 1'b1; - assign _zz_245 = 1'b1; - assign _zz_246 = {_zz_61,_zz_60}; - assign _zz_247 = 32'h0000106f; - assign _zz_248 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_249 = 32'h00001073; - assign _zz_250 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_251 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_252 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_253) == 32'h00000003),{(_zz_254 == _zz_255),{_zz_256,{_zz_257,_zz_258}}}}}}; - assign _zz_253 = 32'h0000207f; - assign _zz_254 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_255 = 32'h00000003; - assign _zz_256 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_257 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_258 = {((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033),{((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_259) == 32'h00005013),{(_zz_260 == _zz_261),{_zz_262,{_zz_263,_zz_264}}}}}}; - assign _zz_259 = 32'hbc00707f; - assign _zz_260 = (decode_INSTRUCTION & 32'hfc00705f); - assign _zz_261 = 32'h00001013; - assign _zz_262 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_263 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_264 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_265 = (decode_INSTRUCTION & 32'h02000074); - assign _zz_266 = 32'h02000030; - assign _zz_267 = _zz_84; - assign _zz_268 = 1'b0; - assign _zz_269 = (((decode_INSTRUCTION & 32'h10003050) == 32'h00000050) != 1'b0); - assign _zz_270 = (((decode_INSTRUCTION & _zz_272) == 32'h10000050) != 1'b0); - assign _zz_271 = {({_zz_273,_zz_274} != 2'b00),{({_zz_275,_zz_276} != 2'b00),{(_zz_277 != _zz_278),{_zz_279,{_zz_280,_zz_281}}}}}; - assign _zz_272 = 32'h10403050; - assign _zz_273 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_274 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_275 = _zz_83; - assign _zz_276 = ((decode_INSTRUCTION & _zz_282) == 32'h00000004); - assign _zz_277 = ((decode_INSTRUCTION & _zz_283) == 32'h00000040); - assign _zz_278 = 1'b0; - assign _zz_279 = ({_zz_284,_zz_285} != 2'b00); - assign _zz_280 = (_zz_286 != 1'b0); - assign _zz_281 = {(_zz_287 != _zz_288),{_zz_289,{_zz_290,_zz_291}}}; - assign _zz_282 = 32'h0000001c; - assign _zz_283 = 32'h00000058; - assign _zz_284 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); - assign _zz_285 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); - assign _zz_286 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); - assign _zz_287 = {(_zz_292 == _zz_293),{_zz_294,_zz_295}}; - assign _zz_288 = 3'b000; - assign _zz_289 = ({_zz_296,{_zz_297,_zz_298}} != 3'b000); - assign _zz_290 = (_zz_299 != 1'b0); - assign _zz_291 = {(_zz_300 != _zz_301),{_zz_302,{_zz_303,_zz_304}}}; - assign _zz_292 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_293 = 32'h40001010; - assign _zz_294 = ((decode_INSTRUCTION & _zz_305) == 32'h00001010); - assign _zz_295 = ((decode_INSTRUCTION & _zz_306) == 32'h00001010); - assign _zz_296 = ((decode_INSTRUCTION & _zz_307) == 32'h00000024); - assign _zz_297 = (_zz_308 == _zz_309); - assign _zz_298 = (_zz_310 == _zz_311); - assign _zz_299 = ((decode_INSTRUCTION & _zz_312) == 32'h00001000); - assign _zz_300 = _zz_85; - assign _zz_301 = 1'b0; - assign _zz_302 = ({_zz_313,_zz_314} != 2'b00); - assign _zz_303 = (_zz_315 != _zz_316); - assign _zz_304 = {_zz_317,{_zz_318,_zz_319}}; - assign _zz_305 = 32'h00007034; - assign _zz_306 = 32'h02007054; - assign _zz_307 = 32'h00000064; - assign _zz_308 = (decode_INSTRUCTION & 32'h00003034); - assign _zz_309 = 32'h00001010; - assign _zz_310 = (decode_INSTRUCTION & 32'h02003054); - assign _zz_311 = 32'h00001010; - assign _zz_312 = 32'h00001000; - assign _zz_313 = ((decode_INSTRUCTION & _zz_320) == 32'h00002000); - assign _zz_314 = ((decode_INSTRUCTION & _zz_321) == 32'h00001000); - assign _zz_315 = {(_zz_322 == _zz_323),(_zz_324 == _zz_325)}; - assign _zz_316 = 2'b00; - assign _zz_317 = (_zz_81 != 1'b0); - assign _zz_318 = ({_zz_326,_zz_327} != 3'b000); - assign _zz_319 = {(_zz_328 != _zz_329),{_zz_330,{_zz_331,_zz_332}}}; - assign _zz_320 = 32'h00002010; - assign _zz_321 = 32'h00005000; - assign _zz_322 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_323 = 32'h00006000; - assign _zz_324 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_325 = 32'h00004000; - assign _zz_326 = _zz_84; - assign _zz_327 = {(_zz_333 == _zz_334),(_zz_335 == _zz_336)}; - assign _zz_328 = ((decode_INSTRUCTION & _zz_337) == 32'h00000020); - assign _zz_329 = 1'b0; - assign _zz_330 = ({_zz_338,_zz_339} != 2'b00); - assign _zz_331 = ({_zz_340,_zz_341} != 3'b000); - assign _zz_332 = {(_zz_342 != _zz_343),{_zz_344,{_zz_345,_zz_346}}}; - assign _zz_333 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_334 = 32'h00000020; - assign _zz_335 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_336 = 32'h00000020; - assign _zz_337 = 32'h00000020; - assign _zz_338 = ((decode_INSTRUCTION & 32'h00000008) == 32'h00000008); - assign _zz_339 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); - assign _zz_340 = _zz_82; - assign _zz_341 = {(_zz_347 == _zz_348),(_zz_349 == _zz_350)}; - assign _zz_342 = {_zz_83,{_zz_351,{_zz_352,_zz_353}}}; - assign _zz_343 = 6'h0; - assign _zz_344 = ({_zz_82,_zz_354} != 2'b00); - assign _zz_345 = ({_zz_355,_zz_356} != 2'b00); - assign _zz_346 = {(_zz_357 != _zz_358),{_zz_359,{_zz_360,_zz_361}}}; - assign _zz_347 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_348 = 32'h00000010; - assign _zz_349 = (decode_INSTRUCTION & 32'h02000060); - assign _zz_350 = 32'h00000020; - assign _zz_351 = ((decode_INSTRUCTION & _zz_362) == 32'h00001010); - assign _zz_352 = (_zz_363 == _zz_364); - assign _zz_353 = {_zz_365,{_zz_366,_zz_367}}; - assign _zz_354 = ((decode_INSTRUCTION & _zz_368) == 32'h00000020); - assign _zz_355 = _zz_82; - assign _zz_356 = (_zz_369 == _zz_370); - assign _zz_357 = {_zz_371,{_zz_372,_zz_373}}; - assign _zz_358 = 4'b0000; - assign _zz_359 = (_zz_374 != 1'b0); - assign _zz_360 = (_zz_375 != _zz_376); - assign _zz_361 = {_zz_377,{_zz_378,_zz_379}}; - assign _zz_362 = 32'h00001010; - assign _zz_363 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_364 = 32'h00002010; - assign _zz_365 = ((decode_INSTRUCTION & _zz_380) == 32'h00000010); + assign _zz_240 = (iBus_cmd_payload_address >>> 5); + assign _zz_241 = 1'b1; + assign _zz_242 = 1'b1; + assign _zz_243 = {_zz_64,_zz_63}; + assign _zz_244 = 32'h0000106f; + assign _zz_245 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_246 = 32'h00001073; + assign _zz_247 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_248 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_249 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_250) == 32'h00000003),{(_zz_251 == _zz_252),{_zz_253,{_zz_254,_zz_255}}}}}}; + assign _zz_250 = 32'h0000207f; + assign _zz_251 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_252 = 32'h00000003; + assign _zz_253 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_254 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_255 = {((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033),{((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_256) == 32'h00005013),{(_zz_257 == _zz_258),{_zz_259,{_zz_260,_zz_261}}}}}}; + assign _zz_256 = 32'hbc00707f; + assign _zz_257 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_258 = 32'h00001013; + assign _zz_259 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_260 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_261 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_262 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz_263 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz_264 = 1'b0; + assign _zz_265 = ({(_zz_268 == _zz_269),(_zz_270 == _zz_271)} != 2'b00); + assign _zz_266 = ({_zz_86,_zz_272} != 2'b00); + assign _zz_267 = {(_zz_273 != 1'b0),{(_zz_274 != _zz_275),{_zz_276,{_zz_277,_zz_278}}}}; + assign _zz_268 = (decode_INSTRUCTION & 32'h00001050); + assign _zz_269 = 32'h00001050; + assign _zz_270 = (decode_INSTRUCTION & 32'h00002050); + assign _zz_271 = 32'h00002050; + assign _zz_272 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz_273 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz_274 = {(_zz_279 == _zz_280),(_zz_281 == _zz_282)}; + assign _zz_275 = 2'b00; + assign _zz_276 = ((_zz_283 == _zz_284) != 1'b0); + assign _zz_277 = ({_zz_285,_zz_286} != 3'b000); + assign _zz_278 = {(_zz_287 != _zz_288),{_zz_289,{_zz_290,_zz_291}}}; + assign _zz_279 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_280 = 32'h00000040; + assign _zz_281 = (decode_INSTRUCTION & 32'h00403040); + assign _zz_282 = 32'h00000040; + assign _zz_283 = (decode_INSTRUCTION & 32'h00007054); + assign _zz_284 = 32'h00005010; + assign _zz_285 = ((decode_INSTRUCTION & _zz_292) == 32'h40001010); + assign _zz_286 = {(_zz_293 == _zz_294),(_zz_295 == _zz_296)}; + assign _zz_287 = ((decode_INSTRUCTION & _zz_297) == 32'h00000024); + assign _zz_288 = 1'b0; + assign _zz_289 = ((_zz_298 == _zz_299) != 1'b0); + assign _zz_290 = (_zz_300 != 1'b0); + assign _zz_291 = {(_zz_301 != _zz_302),{_zz_303,{_zz_304,_zz_305}}}; + assign _zz_292 = 32'h40003054; + assign _zz_293 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_294 = 32'h00001010; + assign _zz_295 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_296 = 32'h00001010; + assign _zz_297 = 32'h00000064; + assign _zz_298 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_299 = 32'h00001000; + assign _zz_300 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_301 = {(_zz_306 == _zz_307),(_zz_308 == _zz_309)}; + assign _zz_302 = 2'b00; + assign _zz_303 = ((_zz_310 == _zz_311) != 1'b0); + assign _zz_304 = (_zz_84 != 1'b0); + assign _zz_305 = {(_zz_312 != _zz_313),{_zz_314,{_zz_315,_zz_316}}}; + assign _zz_306 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_307 = 32'h00002000; + assign _zz_308 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_309 = 32'h00001000; + assign _zz_310 = (decode_INSTRUCTION & 32'h00004004); + assign _zz_311 = 32'h00004000; + assign _zz_312 = {_zz_87,{(_zz_317 == _zz_318),(_zz_319 == _zz_320)}}; + assign _zz_313 = 3'b000; + assign _zz_314 = (((decode_INSTRUCTION & _zz_321) == 32'h00000020) != 1'b0); + assign _zz_315 = ({_zz_322,{_zz_323,_zz_324}} != 5'h0); + assign _zz_316 = {({_zz_325,_zz_326} != 5'h0),{(_zz_327 != _zz_328),{_zz_329,{_zz_330,_zz_331}}}}; + assign _zz_317 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_318 = 32'h00000020; + assign _zz_319 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_320 = 32'h00000020; + assign _zz_321 = 32'h00000020; + assign _zz_322 = ((decode_INSTRUCTION & _zz_332) == 32'h00000008); + assign _zz_323 = (_zz_333 == _zz_334); + assign _zz_324 = {_zz_85,{_zz_335,_zz_336}}; + assign _zz_325 = _zz_85; + assign _zz_326 = {_zz_337,{_zz_338,_zz_339}}; + assign _zz_327 = {_zz_86,{_zz_340,_zz_341}}; + assign _zz_328 = 6'h0; + assign _zz_329 = ({_zz_342,_zz_343} != 2'b00); + assign _zz_330 = (_zz_344 != _zz_345); + assign _zz_331 = {_zz_346,{_zz_347,_zz_348}}; + assign _zz_332 = 32'h00000008; + assign _zz_333 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_334 = 32'h00000040; + assign _zz_335 = (_zz_349 == _zz_350); + assign _zz_336 = (_zz_351 == _zz_352); + assign _zz_337 = ((decode_INSTRUCTION & _zz_353) == 32'h00002010); + assign _zz_338 = (_zz_354 == _zz_355); + assign _zz_339 = {_zz_356,_zz_357}; + assign _zz_340 = (_zz_358 == _zz_359); + assign _zz_341 = {_zz_360,{_zz_361,_zz_362}}; + assign _zz_342 = _zz_85; + assign _zz_343 = (_zz_363 == _zz_364); + assign _zz_344 = {_zz_85,_zz_365}; + assign _zz_345 = 2'b00; + assign _zz_346 = ({_zz_366,_zz_367} != 4'b0000); + assign _zz_347 = (_zz_368 != _zz_369); + assign _zz_348 = {_zz_370,{_zz_371,_zz_372}}; + assign _zz_349 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_350 = 32'h00000010; + assign _zz_351 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_352 = 32'h00000020; + assign _zz_353 = 32'h00002030; + assign _zz_354 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_355 = 32'h00000010; + assign _zz_356 = ((decode_INSTRUCTION & _zz_373) == 32'h00002020); + assign _zz_357 = ((decode_INSTRUCTION & _zz_374) == 32'h00000020); + assign _zz_358 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_359 = 32'h00001010; + assign _zz_360 = ((decode_INSTRUCTION & _zz_375) == 32'h00002010); + assign _zz_361 = (_zz_376 == _zz_377); + assign _zz_362 = {_zz_378,_zz_379}; + assign _zz_363 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_364 = 32'h00000020; + assign _zz_365 = ((decode_INSTRUCTION & _zz_380) == 32'h0); assign _zz_366 = (_zz_381 == _zz_382); - assign _zz_367 = (_zz_383 == _zz_384); - assign _zz_368 = 32'h00000070; - assign _zz_369 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_370 = 32'h0; - assign _zz_371 = ((decode_INSTRUCTION & _zz_385) == 32'h0); - assign _zz_372 = (_zz_386 == _zz_387); - assign _zz_373 = {_zz_81,_zz_388}; - assign _zz_374 = ((decode_INSTRUCTION & _zz_389) == 32'h0); - assign _zz_375 = {_zz_390,{_zz_391,_zz_392}}; - assign _zz_376 = 3'b000; - assign _zz_377 = ({_zz_393,_zz_394} != 2'b00); - assign _zz_378 = (_zz_395 != _zz_396); - assign _zz_379 = (_zz_397 != _zz_398); - assign _zz_380 = 32'h00000050; - assign _zz_381 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_382 = 32'h00000004; - assign _zz_383 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_384 = 32'h0; - assign _zz_385 = 32'h00000044; - assign _zz_386 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_367 = {_zz_383,{_zz_384,_zz_385}}; + assign _zz_368 = (_zz_386 == _zz_387); + assign _zz_369 = 1'b0; + assign _zz_370 = ({_zz_388,_zz_389} != 3'b000); + assign _zz_371 = (_zz_390 != _zz_391); + assign _zz_372 = {_zz_392,_zz_393}; + assign _zz_373 = 32'h02002060; + assign _zz_374 = 32'h02003020; + assign _zz_375 = 32'h00002010; + assign _zz_376 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_377 = 32'h00000010; + assign _zz_378 = ((decode_INSTRUCTION & _zz_394) == 32'h00000004); + assign _zz_379 = ((decode_INSTRUCTION & _zz_395) == 32'h0); + assign _zz_380 = 32'h00000020; + assign _zz_381 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_382 = 32'h0; + assign _zz_383 = ((decode_INSTRUCTION & _zz_396) == 32'h0); + assign _zz_384 = _zz_84; + assign _zz_385 = (_zz_397 == _zz_398); + assign _zz_386 = (decode_INSTRUCTION & 32'h00000058); assign _zz_387 = 32'h0; - assign _zz_388 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_389 = 32'h00000058; - assign _zz_390 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_391 = ((decode_INSTRUCTION & _zz_399) == 32'h00002010); - assign _zz_392 = ((decode_INSTRUCTION & _zz_400) == 32'h40000030); - assign _zz_393 = ((decode_INSTRUCTION & _zz_401) == 32'h00000004); - assign _zz_394 = _zz_80; - assign _zz_395 = {(_zz_402 == _zz_403),_zz_80}; - assign _zz_396 = 2'b00; - assign _zz_397 = ((decode_INSTRUCTION & _zz_404) == 32'h00001004); - assign _zz_398 = 1'b0; - assign _zz_399 = 32'h00002014; - assign _zz_400 = 32'h40004034; - assign _zz_401 = 32'h00000014; - assign _zz_402 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_403 = 32'h00000004; - assign _zz_404 = 32'h00001054; + assign _zz_388 = (_zz_399 == _zz_400); + assign _zz_389 = {_zz_401,_zz_402}; + assign _zz_390 = {_zz_403,_zz_83}; + assign _zz_391 = 2'b00; + assign _zz_392 = ({_zz_404,_zz_405} != 2'b00); + assign _zz_393 = (_zz_406 != 1'b0); + assign _zz_394 = 32'h0000000c; + assign _zz_395 = 32'h00000024; + assign _zz_396 = 32'h00000018; + assign _zz_397 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_398 = 32'h00001000; + assign _zz_399 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_400 = 32'h00000040; + assign _zz_401 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_402 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_403 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_404 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_405 = _zz_83; + assign _zz_406 = ((decode_INSTRUCTION & 32'h00001054) == 32'h00001004); always @ (posedge clk) begin - if(_zz_244) begin - _zz_153 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_241) begin + _zz_152 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_245) begin - _zz_154 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_242) begin + _zz_153 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end always @ (posedge clk) begin - if(_zz_46) begin + if(_zz_49) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_144 ), //i - .io_cpu_prefetch_isValid (_zz_145 ), //i + .io_flush (_zz_143 ), //i + .io_cpu_prefetch_isValid (_zz_144 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_146 ), //i - .io_cpu_fetch_isStuck (_zz_147 ), //i - .io_cpu_fetch_isRemoved (_zz_148 ), //i + .io_cpu_fetch_isValid (_zz_145 ), //i + .io_cpu_fetch_isStuck (_zz_146 ), //i + .io_cpu_fetch_isRemoved (_zz_147 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1374,8 +1399,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_149 ), //i - .io_cpu_decode_isStuck (_zz_150 ), //i + .io_cpu_decode_isValid (_zz_148 ), //i + .io_cpu_decode_isStuck (_zz_149 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1383,8 +1408,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_151 ), //i - .io_cpu_fill_valid (_zz_152 ), //i + .io_cpu_decode_isUser (_zz_150 ), //i + .io_cpu_fill_valid (_zz_151 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1397,15 +1422,15 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_246) + case(_zz_243) 2'b00 : begin - _zz_155 = CsrPlugin_jumpInterface_payload; + _zz_154 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_155 = DBusSimplePlugin_redoBranch_payload; + _zz_154 = DBusSimplePlugin_redoBranch_payload; end default : begin - _zz_155 = BranchPlugin_jumpInterface_payload; + _zz_154 = BranchPlugin_jumpInterface_payload; end endcase end @@ -1539,15 +1564,6 @@ module VexRiscv ( default : _zz_13_string = "????"; endcase end - always @(*) begin - case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; - default : decode_SHIFT_CTRL_string = "?????????"; - endcase - end always @(*) begin case(_zz_14) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; @@ -1566,6 +1582,15 @@ module VexRiscv ( default : _zz_15_string = "?????????"; endcase end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end always @(*) begin case(_zz_16) `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; @@ -1576,27 +1601,29 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; - default : decode_ALU_BITWISE_CTRL_string = "?????"; + case(_zz_17) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; + default : _zz_17_string = "?????????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_18) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_18_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_18_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_18_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_18_string = "SRA_1 "; + default : _zz_18_string = "?????????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin @@ -1608,27 +1635,27 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; - default : decode_ALU_CTRL_string = "????????"; + case(_zz_20) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; + default : _zz_20_string = "?????"; endcase end always @(*) begin - case(_zz_20) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; - default : _zz_20_string = "????????"; + case(_zz_21) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_21_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_21_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_21_string = "AND_1"; + default : _zz_21_string = "?????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin @@ -1640,30 +1667,28 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; - default : decode_SRC2_CTRL_string = "???"; + case(_zz_23) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; + default : _zz_23_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `Src2CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_24_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_24_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_24_string = "PC "; - default : _zz_24_string = "???"; + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin @@ -1676,30 +1701,30 @@ module VexRiscv ( endcase end always @(*) begin - case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; - default : decode_SRC1_CTRL_string = "????????????"; + case(_zz_26) + `Src2CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_26_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_26_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_26_string = "PC "; + default : _zz_26_string = "???"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_27) + `Src2CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_27_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_27_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_27_string = "PC "; + default : _zz_27_string = "???"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin @@ -1711,6 +1736,24 @@ module VexRiscv ( default : _zz_28_string = "????????????"; endcase end + always @(*) begin + case(_zz_29) + `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; + default : _zz_29_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_30) + `Src1CtrlEnum_defaultEncoding_RS : _zz_30_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_30_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_30_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_30_string = "URS1 "; + default : _zz_30_string = "????????????"; + endcase + end always @(*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; @@ -1719,10 +1762,10 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_32) - `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; - default : _zz_32_string = "?????"; + case(_zz_33) + `Input2Kind_defaultEncoding_RS : _zz_33_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_33_string = "IMM_I"; + default : _zz_33_string = "?????"; endcase end always @(*) begin @@ -1734,11 +1777,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; endcase end always @(*) begin @@ -1750,11 +1793,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; + case(_zz_36) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_36_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_36_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_36_string = "ECALL"; + default : _zz_36_string = "?????"; endcase end always @(*) begin @@ -1766,11 +1809,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_37) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_37_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_37_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_37_string = "ECALL"; + default : _zz_37_string = "?????"; endcase end always @(*) begin @@ -1783,12 +1826,30 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_36) - `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; - default : _zz_36_string = "????"; + case(_zz_38) + `BranchCtrlEnum_defaultEncoding_INC : _zz_38_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_38_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_38_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_38_string = "JALR"; + default : _zz_38_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_40) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; + default : _zz_40_string = "?????????"; endcase end always @(*) begin @@ -1801,12 +1862,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_38) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_38_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_38_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_38_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_38_string = "SRA_1 "; - default : _zz_38_string = "?????????"; + case(_zz_41) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_41_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_41_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_41_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_41_string = "SRA_1 "; + default : _zz_41_string = "?????????"; endcase end always @(*) begin @@ -1819,12 +1880,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_40) - `Src2CtrlEnum_defaultEncoding_RS : _zz_40_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_40_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_40_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_40_string = "PC "; - default : _zz_40_string = "???"; + case(_zz_43) + `Src2CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_43_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_43_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_43_string = "PC "; + default : _zz_43_string = "???"; endcase end always @(*) begin @@ -1837,12 +1898,12 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_41) - `Src1CtrlEnum_defaultEncoding_RS : _zz_41_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_41_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_41_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_41_string = "URS1 "; - default : _zz_41_string = "????????????"; + case(_zz_44) + `Src1CtrlEnum_defaultEncoding_RS : _zz_44_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_44_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_44_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_44_string = "URS1 "; + default : _zz_44_string = "????????????"; endcase end always @(*) begin @@ -1854,11 +1915,11 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_42) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_42_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_42_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_42_string = "BITWISE "; - default : _zz_42_string = "????????"; + case(_zz_45) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; + default : _zz_45_string = "????????"; endcase end always @(*) begin @@ -1870,147 +1931,147 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_43) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; - default : _zz_43_string = "?????"; - endcase - end - always @(*) begin - case(_zz_47) - `Input2Kind_defaultEncoding_RS : _zz_47_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_47_string = "IMM_I"; - default : _zz_47_string = "?????"; - endcase - end - always @(*) begin - case(_zz_48) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_48_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_48_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_48_string = "ECALL"; - default : _zz_48_string = "?????"; - endcase - end - always @(*) begin - case(_zz_49) - `BranchCtrlEnum_defaultEncoding_INC : _zz_49_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_49_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_49_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_49_string = "JALR"; - default : _zz_49_string = "????"; + case(_zz_46) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; + default : _zz_46_string = "?????"; endcase end always @(*) begin case(_zz_50) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_50_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_50_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_50_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_50_string = "SRA_1 "; - default : _zz_50_string = "?????????"; + `Input2Kind_defaultEncoding_RS : _zz_50_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_50_string = "IMM_I"; + default : _zz_50_string = "?????"; endcase end always @(*) begin case(_zz_51) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_51_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_51_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_51_string = "AND_1"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_51_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_51_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_51_string = "ECALL"; default : _zz_51_string = "?????"; endcase end always @(*) begin case(_zz_52) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_52_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_52_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_52_string = "BITWISE "; - default : _zz_52_string = "????????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_52_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_52_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_52_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_52_string = "JALR"; + default : _zz_52_string = "????"; endcase end always @(*) begin case(_zz_53) - `Src2CtrlEnum_defaultEncoding_RS : _zz_53_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_53_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_53_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_53_string = "PC "; - default : _zz_53_string = "???"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_53_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_53_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_53_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_53_string = "SRA_1 "; + default : _zz_53_string = "?????????"; endcase end always @(*) begin case(_zz_54) - `Src1CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_54_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_54_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_54_string = "URS1 "; - default : _zz_54_string = "????????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_54_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_54_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_54_string = "AND_1"; + default : _zz_54_string = "?????"; endcase end always @(*) begin - case(_zz_87) - `Src1CtrlEnum_defaultEncoding_RS : _zz_87_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_87_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_87_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_87_string = "URS1 "; - default : _zz_87_string = "????????????"; + case(_zz_55) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; + default : _zz_55_string = "????????"; + endcase + end + always @(*) begin + case(_zz_56) + `Src2CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_56_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_56_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_56_string = "PC "; + default : _zz_56_string = "???"; + endcase + end + always @(*) begin + case(_zz_57) + `Src1CtrlEnum_defaultEncoding_RS : _zz_57_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_57_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_57_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_57_string = "URS1 "; + default : _zz_57_string = "????????????"; endcase end always @(*) begin case(_zz_88) - `Src2CtrlEnum_defaultEncoding_RS : _zz_88_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_88_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_88_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_88_string = "PC "; - default : _zz_88_string = "???"; + `Src1CtrlEnum_defaultEncoding_RS : _zz_88_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_88_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_88_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_88_string = "URS1 "; + default : _zz_88_string = "????????????"; endcase end always @(*) begin case(_zz_89) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_89_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_89_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_89_string = "BITWISE "; - default : _zz_89_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_89_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_89_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_89_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_89_string = "PC "; + default : _zz_89_string = "???"; endcase end always @(*) begin case(_zz_90) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_90_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_90_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_90_string = "AND_1"; - default : _zz_90_string = "?????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_90_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_90_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_90_string = "BITWISE "; + default : _zz_90_string = "????????"; endcase end always @(*) begin case(_zz_91) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_91_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_91_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_91_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_91_string = "SRA_1 "; - default : _zz_91_string = "?????????"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_91_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_91_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_91_string = "AND_1"; + default : _zz_91_string = "?????"; endcase end always @(*) begin case(_zz_92) - `BranchCtrlEnum_defaultEncoding_INC : _zz_92_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_92_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_92_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_92_string = "JALR"; - default : _zz_92_string = "????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_92_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_92_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_92_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_92_string = "SRA_1 "; + default : _zz_92_string = "?????????"; endcase end always @(*) begin case(_zz_93) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_93_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_93_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_93_string = "ECALL"; - default : _zz_93_string = "?????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_93_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_93_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_93_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_93_string = "JALR"; + default : _zz_93_string = "????"; endcase end always @(*) begin case(_zz_94) - `Input2Kind_defaultEncoding_RS : _zz_94_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_94_string = "IMM_I"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_94_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_94_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_94_string = "ECALL"; default : _zz_94_string = "?????"; endcase end + always @(*) begin + case(_zz_95) + `Input2Kind_defaultEncoding_RS : _zz_95_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_95_string = "IMM_I"; + default : _zz_95_string = "?????"; + endcase + end always @(*) begin case(decode_to_execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; @@ -2054,6 +2115,15 @@ module VexRiscv ( default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end always @(*) begin case(decode_to_execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; @@ -2096,11 +2166,18 @@ module VexRiscv ( end `endif + assign memory_MUL_LOW = ($signed(_zz_182) + $signed(_zz_190)); assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign execute_SHIFT_RIGHT = _zz_192; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_96; + assign execute_REGFILE_WRITE_DATA = _zz_97; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); @@ -2108,136 +2185,157 @@ module VexRiscv ( assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign decode_IS_RS2_SIGNED = _zz_185[0]; - assign decode_IS_RS1_SIGNED = _zz_186[0]; - assign decode_IS_MUL = _zz_187[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_194[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_188[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_195[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_189[0]; + assign decode_IS_CSR = _zz_196[0]; assign decode_BRANCH_CTRL = _zz_11; assign _zz_12 = _zz_13; - assign decode_SHIFT_CTRL = _zz_14; - assign _zz_15 = _zz_16; - assign decode_ALU_BITWISE_CTRL = _zz_17; - assign _zz_18 = _zz_19; - assign decode_SRC_LESS_UNSIGNED = _zz_190[0]; - assign decode_ALU_CTRL = _zz_20; - assign _zz_21 = _zz_22; - assign decode_MEMORY_STORE = _zz_191[0]; + assign _zz_14 = _zz_15; + assign decode_SHIFT_CTRL = _zz_16; + assign _zz_17 = _zz_18; + assign decode_ALU_BITWISE_CTRL = _zz_19; + assign _zz_20 = _zz_21; + assign decode_SRC_LESS_UNSIGNED = _zz_197[0]; + assign decode_ALU_CTRL = _zz_22; + assign _zz_23 = _zz_24; + assign decode_MEMORY_STORE = _zz_198[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_192[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_193[0]; - assign decode_SRC2_CTRL = _zz_23; - assign _zz_24 = _zz_25; - assign decode_SRC1_CTRL = _zz_26; - assign _zz_27 = _zz_28; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_199[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_200[0]; + assign decode_SRC2_CTRL = _zz_25; + assign _zz_26 = _zz_27; + assign decode_SRC1_CTRL = _zz_28; + assign _zz_29 = _zz_30; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); - assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; - assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; - assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; always @ (*) begin - _zz_29 = memory_CfuPlugin_CFU_IN_FLIGHT; + _zz_31 = memory_CfuPlugin_CFU_IN_FLIGHT; if(memory_arbitration_isStuck)begin - _zz_29 = 1'b0; + _zz_31 = 1'b0; end end always @ (*) begin - _zz_30 = execute_CfuPlugin_CFU_IN_FLIGHT; + _zz_32 = execute_CfuPlugin_CFU_IN_FLIGHT; if(execute_arbitration_isStuck)begin - _zz_30 = 1'b0; + _zz_32 = 1'b0; end end + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_33; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; always @ (*) begin - _zz_31 = memory_REGFILE_WRITE_DATA; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_31 = memory_CfuPlugin_rsp_payload_outputs_0; - end - if(_zz_156)begin - _zz_31 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + _zz_34 = execute_REGFILE_WRITE_DATA; + if(_zz_155)begin + _zz_34 = execute_CsrPlugin_readData; end end - assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33; - assign execute_ENV_CTRL = _zz_34; - assign writeBack_ENV_CTRL = _zz_35; + assign memory_ENV_CTRL = _zz_35; + assign execute_ENV_CTRL = _zz_36; + assign writeBack_ENV_CTRL = _zz_37; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_110; + assign execute_BRANCH_DO = _zz_112; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_194[0]; - assign decode_RS1_USE = _zz_195[0]; + assign execute_BRANCH_CTRL = _zz_38; + assign decode_RS2_USE = _zz_201[0]; + assign decode_RS1_USE = _zz_202[0]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; always @ (*) begin - _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_157)begin - _zz_37 = _zz_103; + _zz_39 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_39 = _zz_105; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_39 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase end - if(_zz_158)begin - _zz_37 = execute_CsrPlugin_readData; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_39 = memory_CfuPlugin_rsp_payload_outputs_0; end end - assign execute_SHIFT_CTRL = _zz_38; + assign memory_SHIFT_CTRL = _zz_40; + assign execute_SHIFT_CTRL = _zz_41; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_39 = execute_PC; - assign execute_SRC2_CTRL = _zz_40; - assign execute_SRC1_CTRL = _zz_41; - assign decode_SRC_USE_SUB_LESS = _zz_196[0]; - assign decode_SRC_ADD_ZERO = _zz_197[0]; + assign _zz_42 = execute_PC; + assign execute_SRC2_CTRL = _zz_43; + assign execute_SRC1_CTRL = _zz_44; + assign decode_SRC_USE_SUB_LESS = _zz_203[0]; + assign decode_SRC_ADD_ZERO = _zz_204[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_42; - assign execute_SRC2 = _zz_102; - assign execute_SRC1 = _zz_97; - assign execute_ALU_BITWISE_CTRL = _zz_43; - assign _zz_44 = writeBack_INSTRUCTION; - assign _zz_45 = writeBack_REGFILE_WRITE_VALID; + assign execute_ALU_CTRL = _zz_45; + assign execute_SRC2 = _zz_103; + assign execute_SRC1 = _zz_98; + assign execute_ALU_BITWISE_CTRL = _zz_46; + assign _zz_47 = writeBack_INSTRUCTION; + assign _zz_48 = writeBack_REGFILE_WRITE_VALID; always @ (*) begin - _zz_46 = 1'b0; + _zz_49 = 1'b0; if(lastStageRegFileWrite_valid)begin - _zz_46 = 1'b1; + _zz_49 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_198[0]; + decode_REGFILE_WRITE_VALID = _zz_205[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_247) == 32'h00000003),{(_zz_248 == _zz_249),{_zz_250,{_zz_251,_zz_252}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_244) == 32'h00000003),{(_zz_245 == _zz_246),{_zz_247,{_zz_248,_zz_249}}}}}}} != 22'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; always @ (*) begin - _zz_55 = writeBack_REGFILE_WRITE_DATA; + _zz_58 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_55 = writeBack_DBusSimplePlugin_rspFormated; + _zz_58 = writeBack_DBusSimplePlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_181) + 2'b00 : begin + _zz_58 = _zz_232; + end + default : begin + _zz_58 = _zz_233; + end + endcase end end @@ -2274,34 +2372,34 @@ module VexRiscv ( assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = 1'b0; - assign decode_MEMORY_ENABLE = _zz_199[0]; - assign decode_FLUSH_ALL = _zz_200[0]; + assign decode_MEMORY_ENABLE = _zz_206[0]; + assign decode_FLUSH_ALL = _zz_207[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_159)begin + if(_zz_156)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_160)begin + if(_zz_157)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; always @ (*) begin - _zz_56 = execute_FORMAL_PC_NEXT; + _zz_59 = execute_FORMAL_PC_NEXT; if(BranchPlugin_jumpInterface_valid)begin - _zz_56 = BranchPlugin_jumpInterface_payload; + _zz_59 = BranchPlugin_jumpInterface_payload; end end always @ (*) begin - _zz_57 = memory_FORMAL_PC_NEXT; + _zz_60 = memory_FORMAL_PC_NEXT; if(DBusSimplePlugin_redoBranch_valid)begin - _zz_57 = DBusSimplePlugin_redoBranch_payload; + _zz_60 = DBusSimplePlugin_redoBranch_payload; end end @@ -2317,7 +2415,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_104 || _zz_105)))begin + if((decode_arbitration_isValid && (_zz_106 || _zz_107)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2348,15 +2446,10 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_72)))begin + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_75)))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_157)begin - if((! execute_LightShifterPlugin_done))begin - execute_arbitration_haltItself = 1'b1; - end - end - if(_zz_158)begin + if(_zz_155)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2398,20 +2491,12 @@ module VexRiscv ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_156)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin - memory_arbitration_haltItself = 1'b1; - end - if(_zz_161)begin - memory_arbitration_haltItself = 1'b1; - end - end end assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_162)begin + if(_zz_158)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2431,7 +2516,7 @@ module VexRiscv ( if(DBusSimplePlugin_redoBranch_valid)begin memory_arbitration_flushNext = 1'b1; end - if(_zz_162)begin + if(_zz_158)begin memory_arbitration_flushNext = 1'b1; end end @@ -2448,10 +2533,10 @@ module VexRiscv ( assign writeBack_arbitration_flushIt = 1'b0; always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_163)begin + if(_zz_159)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_164)begin + if(_zz_160)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2465,10 +2550,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_163)begin + if(_zz_159)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_164)begin + if(_zz_160)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -2484,21 +2569,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_163)begin + if(_zz_159)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_164)begin + if(_zz_160)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_163)begin + if(_zz_159)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_164)begin - case(_zz_165) + if(_zz_160)begin + case(_zz_161) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2513,11 +2598,11 @@ module VexRiscv ( assign CsrPlugin_allowException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); - assign _zz_58 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_59 = (_zz_58 & (~ _zz_201)); - assign _zz_60 = _zz_59[1]; - assign _zz_61 = _zz_59[2]; - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_155; + assign _zz_61 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; + assign _zz_62 = (_zz_61 & (~ _zz_208)); + assign _zz_63 = _zz_62[1]; + assign _zz_64 = _zz_62[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_154; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -2537,7 +2622,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_203); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_210); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -2577,9 +2662,9 @@ module VexRiscv ( end end - assign _zz_62 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_62); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_62); + assign _zz_65 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_65); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_65); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; @@ -2588,9 +2673,9 @@ module VexRiscv ( end end - assign _zz_63 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_63); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_63); + assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_66); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; @@ -2599,22 +2684,22 @@ module VexRiscv ( end end - assign _zz_64 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_64); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_64); + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_67); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_65; - assign _zz_65 = ((1'b0 && (! _zz_66)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_66 = _zz_67; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_66; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_68; + assign _zz_68 = ((1'b0 && (! _zz_69)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_69 = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_69; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_68)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_68 = _zz_69; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_68; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_71 = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_73; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -2636,33 +2721,33 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_145 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_146 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_147 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_146; + assign _zz_144 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_145 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_146 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_145; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_149 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_150 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_151 = (CsrPlugin_privilege == 2'b00); + assign _zz_148 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_149 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_150 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_160)begin + if(_zz_157)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_159)begin + if(_zz_156)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_152 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_159)begin - _zz_152 = 1'b1; + _zz_151 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_156)begin + _zz_151 = 1'b1; end end @@ -2670,8 +2755,8 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_144 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign _zz_72 = 1'b0; + assign _zz_143 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_75 = 1'b0; always @ (*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; if(execute_ALIGNEMENT_FAULT)begin @@ -2682,39 +2767,39 @@ module VexRiscv ( end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_72)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_75)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_73 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_76 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_73 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_76 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_73 = execute_RS2[31 : 0]; + _zz_76 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_73; + assign dBus_cmd_payload_data = _zz_76; always @ (*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_74 = 4'b0001; + _zz_77 = 4'b0001; end 2'b01 : begin - _zz_74 = 4'b0011; + _zz_77 = 4'b0011; end default : begin - _zz_74 = 4'b1111; + _zz_77 = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_74 <<< dBus_cmd_payload_address[1 : 0]); + assign execute_DBusSimplePlugin_formalMask = (_zz_77 <<< dBus_cmd_payload_address[1 : 0]); assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; @@ -2730,7 +2815,7 @@ module VexRiscv ( DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end end - if(_zz_166)begin + if(_zz_162)begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end @@ -2750,7 +2835,7 @@ module VexRiscv ( if(memory_MMU_RSP2_refilling)begin DBusSimplePlugin_redoBranch_valid = 1'b1; end - if(_zz_166)begin + if(_zz_162)begin DBusSimplePlugin_redoBranch_valid = 1'b0; end end @@ -2773,63 +2858,63 @@ module VexRiscv ( endcase end - assign _zz_75 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + assign _zz_78 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); always @ (*) begin - _zz_76[31] = _zz_75; - _zz_76[30] = _zz_75; - _zz_76[29] = _zz_75; - _zz_76[28] = _zz_75; - _zz_76[27] = _zz_75; - _zz_76[26] = _zz_75; - _zz_76[25] = _zz_75; - _zz_76[24] = _zz_75; - _zz_76[23] = _zz_75; - _zz_76[22] = _zz_75; - _zz_76[21] = _zz_75; - _zz_76[20] = _zz_75; - _zz_76[19] = _zz_75; - _zz_76[18] = _zz_75; - _zz_76[17] = _zz_75; - _zz_76[16] = _zz_75; - _zz_76[15] = _zz_75; - _zz_76[14] = _zz_75; - _zz_76[13] = _zz_75; - _zz_76[12] = _zz_75; - _zz_76[11] = _zz_75; - _zz_76[10] = _zz_75; - _zz_76[9] = _zz_75; - _zz_76[8] = _zz_75; - _zz_76[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_77 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + _zz_79[31] = _zz_78; + _zz_79[30] = _zz_78; + _zz_79[29] = _zz_78; + _zz_79[28] = _zz_78; + _zz_79[27] = _zz_78; + _zz_79[26] = _zz_78; + _zz_79[25] = _zz_78; + _zz_79[24] = _zz_78; + _zz_79[23] = _zz_78; + _zz_79[22] = _zz_78; + _zz_79[21] = _zz_78; + _zz_79[20] = _zz_78; + _zz_79[19] = _zz_78; + _zz_79[18] = _zz_78; + _zz_79[17] = _zz_78; + _zz_79[16] = _zz_78; + _zz_79[15] = _zz_78; + _zz_79[14] = _zz_78; + _zz_79[13] = _zz_78; + _zz_79[12] = _zz_78; + _zz_79[11] = _zz_78; + _zz_79[10] = _zz_78; + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_80 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); always @ (*) begin - _zz_78[31] = _zz_77; - _zz_78[30] = _zz_77; - _zz_78[29] = _zz_77; - _zz_78[28] = _zz_77; - _zz_78[27] = _zz_77; - _zz_78[26] = _zz_77; - _zz_78[25] = _zz_77; - _zz_78[24] = _zz_77; - _zz_78[23] = _zz_77; - _zz_78[22] = _zz_77; - _zz_78[21] = _zz_77; - _zz_78[20] = _zz_77; - _zz_78[19] = _zz_77; - _zz_78[18] = _zz_77; - _zz_78[17] = _zz_77; - _zz_78[16] = _zz_77; - _zz_78[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + _zz_81[31] = _zz_80; + _zz_81[30] = _zz_80; + _zz_81[29] = _zz_80; + _zz_81[28] = _zz_80; + _zz_81[27] = _zz_80; + _zz_81[26] = _zz_80; + _zz_81[25] = _zz_80; + _zz_81[24] = _zz_80; + _zz_81[23] = _zz_80; + _zz_81[22] = _zz_80; + _zz_81[21] = _zz_80; + _zz_81[20] = _zz_80; + _zz_81[19] = _zz_80; + _zz_81[18] = _zz_80; + _zz_81[17] = _zz_80; + _zz_81[16] = _zz_80; + _zz_81[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; end always @ (*) begin - case(_zz_183) + case(_zz_179) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_76; + writeBack_DBusSimplePlugin_rspFormated = _zz_79; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_78; + writeBack_DBusSimplePlugin_rspFormated = _zz_81; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -2855,54 +2940,52 @@ module VexRiscv ( assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_80 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_81 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_82 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_83 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_84 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_85 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_86 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00001000); - assign _zz_79 = {(_zz_86 != 1'b0),{({_zz_86,_zz_85} != 2'b00),{((_zz_265 == _zz_266) != 1'b0),{1'b0,{(_zz_267 != _zz_268),{_zz_269,{_zz_270,_zz_271}}}}}}}; - assign _zz_87 = _zz_79[2 : 1]; - assign _zz_54 = _zz_87; - assign _zz_88 = _zz_79[7 : 6]; - assign _zz_53 = _zz_88; - assign _zz_89 = _zz_79[14 : 13]; - assign _zz_52 = _zz_89; - assign _zz_90 = _zz_79[17 : 16]; - assign _zz_51 = _zz_90; - assign _zz_91 = _zz_79[20 : 19]; - assign _zz_50 = _zz_91; - assign _zz_92 = _zz_79[23 : 22]; - assign _zz_49 = _zz_92; - assign _zz_93 = _zz_79[26 : 25]; - assign _zz_48 = _zz_93; - assign _zz_94 = _zz_79[28 : 28]; - assign _zz_47 = _zz_94; + assign _zz_83 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_84 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_85 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_86 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_87 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_82 = {(((decode_INSTRUCTION & 32'h02000074) == 32'h02000030) != 1'b0),{1'b0,{(_zz_87 != 1'b0),{(_zz_262 != 1'b0),{(_zz_263 != _zz_264),{_zz_265,{_zz_266,_zz_267}}}}}}}; + assign _zz_88 = _zz_82[2 : 1]; + assign _zz_57 = _zz_88; + assign _zz_89 = _zz_82[7 : 6]; + assign _zz_56 = _zz_89; + assign _zz_90 = _zz_82[14 : 13]; + assign _zz_55 = _zz_90; + assign _zz_91 = _zz_82[17 : 16]; + assign _zz_54 = _zz_91; + assign _zz_92 = _zz_82[20 : 19]; + assign _zz_53 = _zz_92; + assign _zz_93 = _zz_82[23 : 22]; + assign _zz_52 = _zz_93; + assign _zz_94 = _zz_82[26 : 25]; + assign _zz_51 = _zz_94; + assign _zz_95 = _zz_82[28 : 28]; + assign _zz_50 = _zz_95; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_153; - assign decode_RegFilePlugin_rs2Data = _zz_154; + assign decode_RegFilePlugin_rs1Data = _zz_152; + assign decode_RegFilePlugin_rs2Data = _zz_153; always @ (*) begin - lastStageRegFileWrite_valid = (_zz_45 && writeBack_arbitration_isFiring); - if(_zz_95)begin + lastStageRegFileWrite_valid = (_zz_48 && writeBack_arbitration_isFiring); + if(_zz_96)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_44[11 : 7]; - if(_zz_95)begin + lastStageRegFileWrite_payload_address = _zz_47[11 : 7]; + if(_zz_96)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_55; - if(_zz_95)begin + lastStageRegFileWrite_payload_data = _zz_58; + if(_zz_96)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -2924,13 +3007,13 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_96 = execute_IntAluPlugin_bitwise; + _zz_97 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_96 = {31'd0, _zz_204}; + _zz_97 = {31'd0, _zz_211}; end default : begin - _zz_96 = execute_SRC_ADD_SUB; + _zz_97 = execute_SRC_ADD_SUB; end endcase end @@ -2938,232 +3021,265 @@ module VexRiscv ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_97 = execute_RS1; + _zz_98 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_97 = {29'd0, _zz_205}; + _zz_98 = {29'd0, _zz_212}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_97 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_98 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_97 = {27'd0, _zz_206}; + _zz_98 = {27'd0, _zz_213}; end endcase end - assign _zz_98 = _zz_207[11]; + assign _zz_99 = _zz_214[11]; always @ (*) begin - _zz_99[19] = _zz_98; - _zz_99[18] = _zz_98; - _zz_99[17] = _zz_98; - _zz_99[16] = _zz_98; - _zz_99[15] = _zz_98; - _zz_99[14] = _zz_98; - _zz_99[13] = _zz_98; - _zz_99[12] = _zz_98; - _zz_99[11] = _zz_98; - _zz_99[10] = _zz_98; - _zz_99[9] = _zz_98; - _zz_99[8] = _zz_98; - _zz_99[7] = _zz_98; - _zz_99[6] = _zz_98; - _zz_99[5] = _zz_98; - _zz_99[4] = _zz_98; - _zz_99[3] = _zz_98; - _zz_99[2] = _zz_98; - _zz_99[1] = _zz_98; - _zz_99[0] = _zz_98; - end - - assign _zz_100 = _zz_208[11]; + _zz_100[19] = _zz_99; + _zz_100[18] = _zz_99; + _zz_100[17] = _zz_99; + _zz_100[16] = _zz_99; + _zz_100[15] = _zz_99; + _zz_100[14] = _zz_99; + _zz_100[13] = _zz_99; + _zz_100[12] = _zz_99; + _zz_100[11] = _zz_99; + _zz_100[10] = _zz_99; + _zz_100[9] = _zz_99; + _zz_100[8] = _zz_99; + _zz_100[7] = _zz_99; + _zz_100[6] = _zz_99; + _zz_100[5] = _zz_99; + _zz_100[4] = _zz_99; + _zz_100[3] = _zz_99; + _zz_100[2] = _zz_99; + _zz_100[1] = _zz_99; + _zz_100[0] = _zz_99; + end + + assign _zz_101 = _zz_215[11]; always @ (*) begin - _zz_101[19] = _zz_100; - _zz_101[18] = _zz_100; - _zz_101[17] = _zz_100; - _zz_101[16] = _zz_100; - _zz_101[15] = _zz_100; - _zz_101[14] = _zz_100; - _zz_101[13] = _zz_100; - _zz_101[12] = _zz_100; - _zz_101[11] = _zz_100; - _zz_101[10] = _zz_100; - _zz_101[9] = _zz_100; - _zz_101[8] = _zz_100; - _zz_101[7] = _zz_100; - _zz_101[6] = _zz_100; - _zz_101[5] = _zz_100; - _zz_101[4] = _zz_100; - _zz_101[3] = _zz_100; - _zz_101[2] = _zz_100; - _zz_101[1] = _zz_100; - _zz_101[0] = _zz_100; + _zz_102[19] = _zz_101; + _zz_102[18] = _zz_101; + _zz_102[17] = _zz_101; + _zz_102[16] = _zz_101; + _zz_102[15] = _zz_101; + _zz_102[14] = _zz_101; + _zz_102[13] = _zz_101; + _zz_102[12] = _zz_101; + _zz_102[11] = _zz_101; + _zz_102[10] = _zz_101; + _zz_102[9] = _zz_101; + _zz_102[8] = _zz_101; + _zz_102[7] = _zz_101; + _zz_102[6] = _zz_101; + _zz_102[5] = _zz_101; + _zz_102[4] = _zz_101; + _zz_102[3] = _zz_101; + _zz_102[2] = _zz_101; + _zz_102[1] = _zz_101; + _zz_102[0] = _zz_101; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_102 = execute_RS2; + _zz_103 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_102 = {_zz_99,execute_INSTRUCTION[31 : 20]}; + _zz_103 = {_zz_100,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_102 = {_zz_101,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_103 = {_zz_102,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_102 = _zz_39; + _zz_103 = _zz_42; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_209; + execute_SrcPlugin_addSub = _zz_216; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); - assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); - assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); - assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_103 = (execute_LightShifterPlugin_shiftInput <<< 1); - end - default : begin - _zz_103 = _zz_216; - end - endcase + _zz_104[0] = execute_SRC1[31]; + _zz_104[1] = execute_SRC1[30]; + _zz_104[2] = execute_SRC1[29]; + _zz_104[3] = execute_SRC1[28]; + _zz_104[4] = execute_SRC1[27]; + _zz_104[5] = execute_SRC1[26]; + _zz_104[6] = execute_SRC1[25]; + _zz_104[7] = execute_SRC1[24]; + _zz_104[8] = execute_SRC1[23]; + _zz_104[9] = execute_SRC1[22]; + _zz_104[10] = execute_SRC1[21]; + _zz_104[11] = execute_SRC1[20]; + _zz_104[12] = execute_SRC1[19]; + _zz_104[13] = execute_SRC1[18]; + _zz_104[14] = execute_SRC1[17]; + _zz_104[15] = execute_SRC1[16]; + _zz_104[16] = execute_SRC1[15]; + _zz_104[17] = execute_SRC1[14]; + _zz_104[18] = execute_SRC1[13]; + _zz_104[19] = execute_SRC1[12]; + _zz_104[20] = execute_SRC1[11]; + _zz_104[21] = execute_SRC1[10]; + _zz_104[22] = execute_SRC1[9]; + _zz_104[23] = execute_SRC1[8]; + _zz_104[24] = execute_SRC1[7]; + _zz_104[25] = execute_SRC1[6]; + _zz_104[26] = execute_SRC1[5]; + _zz_104[27] = execute_SRC1[4]; + _zz_104[28] = execute_SRC1[3]; + _zz_104[29] = execute_SRC1[2]; + _zz_104[30] = execute_SRC1[1]; + _zz_104[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_104 : execute_SRC1); + always @ (*) begin + _zz_105[0] = memory_SHIFT_RIGHT[31]; + _zz_105[1] = memory_SHIFT_RIGHT[30]; + _zz_105[2] = memory_SHIFT_RIGHT[29]; + _zz_105[3] = memory_SHIFT_RIGHT[28]; + _zz_105[4] = memory_SHIFT_RIGHT[27]; + _zz_105[5] = memory_SHIFT_RIGHT[26]; + _zz_105[6] = memory_SHIFT_RIGHT[25]; + _zz_105[7] = memory_SHIFT_RIGHT[24]; + _zz_105[8] = memory_SHIFT_RIGHT[23]; + _zz_105[9] = memory_SHIFT_RIGHT[22]; + _zz_105[10] = memory_SHIFT_RIGHT[21]; + _zz_105[11] = memory_SHIFT_RIGHT[20]; + _zz_105[12] = memory_SHIFT_RIGHT[19]; + _zz_105[13] = memory_SHIFT_RIGHT[18]; + _zz_105[14] = memory_SHIFT_RIGHT[17]; + _zz_105[15] = memory_SHIFT_RIGHT[16]; + _zz_105[16] = memory_SHIFT_RIGHT[15]; + _zz_105[17] = memory_SHIFT_RIGHT[14]; + _zz_105[18] = memory_SHIFT_RIGHT[13]; + _zz_105[19] = memory_SHIFT_RIGHT[12]; + _zz_105[20] = memory_SHIFT_RIGHT[11]; + _zz_105[21] = memory_SHIFT_RIGHT[10]; + _zz_105[22] = memory_SHIFT_RIGHT[9]; + _zz_105[23] = memory_SHIFT_RIGHT[8]; + _zz_105[24] = memory_SHIFT_RIGHT[7]; + _zz_105[25] = memory_SHIFT_RIGHT[6]; + _zz_105[26] = memory_SHIFT_RIGHT[5]; + _zz_105[27] = memory_SHIFT_RIGHT[4]; + _zz_105[28] = memory_SHIFT_RIGHT[3]; + _zz_105[29] = memory_SHIFT_RIGHT[2]; + _zz_105[30] = memory_SHIFT_RIGHT[1]; + _zz_105[31] = memory_SHIFT_RIGHT[0]; end always @ (*) begin - _zz_104 = 1'b0; - if(_zz_106)begin - if((_zz_107 == decode_INSTRUCTION[19 : 15]))begin - _zz_104 = 1'b1; + _zz_106 = 1'b0; + if(_zz_108)begin + if((_zz_109 == decode_INSTRUCTION[19 : 15]))begin + _zz_106 = 1'b1; end end - if(_zz_167)begin - if(_zz_168)begin + if(_zz_163)begin + if(_zz_164)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_104 = 1'b1; + _zz_106 = 1'b1; end end end - if(_zz_169)begin - if(_zz_170)begin + if(_zz_165)begin + if(_zz_166)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_104 = 1'b1; + _zz_106 = 1'b1; end end end - if(_zz_171)begin - if(_zz_172)begin + if(_zz_167)begin + if(_zz_168)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_104 = 1'b1; + _zz_106 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_104 = 1'b0; + _zz_106 = 1'b0; end end always @ (*) begin - _zz_105 = 1'b0; - if(_zz_106)begin - if((_zz_107 == decode_INSTRUCTION[24 : 20]))begin - _zz_105 = 1'b1; + _zz_107 = 1'b0; + if(_zz_108)begin + if((_zz_109 == decode_INSTRUCTION[24 : 20]))begin + _zz_107 = 1'b1; end end - if(_zz_167)begin - if(_zz_168)begin + if(_zz_163)begin + if(_zz_164)begin if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_105 = 1'b1; + _zz_107 = 1'b1; end end end - if(_zz_169)begin - if(_zz_170)begin + if(_zz_165)begin + if(_zz_166)begin if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_105 = 1'b1; + _zz_107 = 1'b1; end end end - if(_zz_171)begin - if(_zz_172)begin + if(_zz_167)begin + if(_zz_168)begin if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_105 = 1'b1; + _zz_107 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_105 = 1'b0; + _zz_107 = 1'b0; end end assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_108 = execute_INSTRUCTION[14 : 12]; + assign _zz_110 = execute_INSTRUCTION[14 : 12]; always @ (*) begin - if((_zz_108 == 3'b000)) begin - _zz_109 = execute_BranchPlugin_eq; - end else if((_zz_108 == 3'b001)) begin - _zz_109 = (! execute_BranchPlugin_eq); - end else if((((_zz_108 & 3'b101) == 3'b101))) begin - _zz_109 = (! execute_SRC_LESS); + if((_zz_110 == 3'b000)) begin + _zz_111 = execute_BranchPlugin_eq; + end else if((_zz_110 == 3'b001)) begin + _zz_111 = (! execute_BranchPlugin_eq); + end else if((((_zz_110 & 3'b101) == 3'b101))) begin + _zz_111 = (! execute_SRC_LESS); end else begin - _zz_109 = execute_SRC_LESS; + _zz_111 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_110 = 1'b0; + _zz_112 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_110 = 1'b1; + _zz_112 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_110 = 1'b1; + _zz_112 = 1'b1; end default : begin - _zz_110 = _zz_109; + _zz_112 = _zz_111; end endcase end assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_111 = _zz_218[19]; - always @ (*) begin - _zz_112[10] = _zz_111; - _zz_112[9] = _zz_111; - _zz_112[8] = _zz_111; - _zz_112[7] = _zz_111; - _zz_112[6] = _zz_111; - _zz_112[5] = _zz_111; - _zz_112[4] = _zz_111; - _zz_112[3] = _zz_111; - _zz_112[2] = _zz_111; - _zz_112[1] = _zz_111; - _zz_112[0] = _zz_111; - end - - assign _zz_113 = _zz_219[11]; + assign _zz_113 = _zz_223[19]; always @ (*) begin - _zz_114[19] = _zz_113; - _zz_114[18] = _zz_113; - _zz_114[17] = _zz_113; - _zz_114[16] = _zz_113; - _zz_114[15] = _zz_113; - _zz_114[14] = _zz_113; - _zz_114[13] = _zz_113; - _zz_114[12] = _zz_113; - _zz_114[11] = _zz_113; _zz_114[10] = _zz_113; _zz_114[9] = _zz_113; _zz_114[8] = _zz_113; @@ -3177,8 +3293,9 @@ module VexRiscv ( _zz_114[0] = _zz_113; end - assign _zz_115 = _zz_220[11]; + assign _zz_115 = _zz_224[11]; always @ (*) begin + _zz_116[19] = _zz_115; _zz_116[18] = _zz_115; _zz_116[17] = _zz_115; _zz_116[16] = _zz_115; @@ -3200,21 +3317,44 @@ module VexRiscv ( _zz_116[0] = _zz_115; end + assign _zz_117 = _zz_225[11]; + always @ (*) begin + _zz_118[18] = _zz_117; + _zz_118[17] = _zz_117; + _zz_118[16] = _zz_117; + _zz_118[15] = _zz_117; + _zz_118[14] = _zz_117; + _zz_118[13] = _zz_117; + _zz_118[12] = _zz_117; + _zz_118[11] = _zz_117; + _zz_118[10] = _zz_117; + _zz_118[9] = _zz_117; + _zz_118[8] = _zz_117; + _zz_118[7] = _zz_117; + _zz_118[6] = _zz_117; + _zz_118[5] = _zz_117; + _zz_118[4] = _zz_117; + _zz_118[3] = _zz_117; + _zz_118[2] = _zz_117; + _zz_118[1] = _zz_117; + _zz_118[0] = _zz_117; + end + always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_117 = {{_zz_112,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + _zz_119 = {{_zz_114,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_117 = {_zz_114,execute_INSTRUCTION[31 : 20]}; + _zz_119 = {_zz_116,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_117 = {{_zz_116,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_119 = {{_zz_118,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_117; + assign execute_BranchPlugin_branch_src2 = _zz_119; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; @@ -3227,13 +3367,13 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_118 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_119 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_120 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_120 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_121 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_122 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_121 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_122 = _zz_221[0]; + assign _zz_123 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_124 = _zz_226[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; if(decodeExceptionPort_valid)begin @@ -3256,7 +3396,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_162)begin + if(_zz_158)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3374,7 +3514,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_173)begin + if(_zz_169)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -3393,14 +3533,14 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_174)begin + if(_zz_170)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_174)begin + if(_zz_170)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3415,14 +3555,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_173)begin + if(_zz_169)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_173)begin + if(_zz_169)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -3431,7 +3571,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_184) + case(_zz_180) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -3444,49 +3584,49 @@ module VexRiscv ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_223; + assign execute_CfuPlugin_functionsIds_0 = _zz_228; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_123 = _zz_224[7]; + assign _zz_125 = _zz_229[7]; always @ (*) begin - _zz_124[23] = _zz_123; - _zz_124[22] = _zz_123; - _zz_124[21] = _zz_123; - _zz_124[20] = _zz_123; - _zz_124[19] = _zz_123; - _zz_124[18] = _zz_123; - _zz_124[17] = _zz_123; - _zz_124[16] = _zz_123; - _zz_124[15] = _zz_123; - _zz_124[14] = _zz_123; - _zz_124[13] = _zz_123; - _zz_124[12] = _zz_123; - _zz_124[11] = _zz_123; - _zz_124[10] = _zz_123; - _zz_124[9] = _zz_123; - _zz_124[8] = _zz_123; - _zz_124[7] = _zz_123; - _zz_124[6] = _zz_123; - _zz_124[5] = _zz_123; - _zz_124[4] = _zz_123; - _zz_124[3] = _zz_123; - _zz_124[2] = _zz_123; - _zz_124[1] = _zz_123; - _zz_124[0] = _zz_123; + _zz_126[23] = _zz_125; + _zz_126[22] = _zz_125; + _zz_126[21] = _zz_125; + _zz_126[20] = _zz_125; + _zz_126[19] = _zz_125; + _zz_126[18] = _zz_125; + _zz_126[17] = _zz_125; + _zz_126[16] = _zz_125; + _zz_126[15] = _zz_125; + _zz_126[14] = _zz_125; + _zz_126[13] = _zz_125; + _zz_126[12] = _zz_125; + _zz_126[11] = _zz_125; + _zz_126[10] = _zz_125; + _zz_126[9] = _zz_125; + _zz_126[8] = _zz_125; + _zz_126[7] = _zz_125; + _zz_126[6] = _zz_125; + _zz_126[5] = _zz_125; + _zz_126[4] = _zz_125; + _zz_126[3] = _zz_125; + _zz_126[2] = _zz_125; + _zz_126[1] = _zz_125; + _zz_126[0] = _zz_125; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_125 = execute_RS2; + _zz_127 = execute_RS2; end default : begin - _zz_125 = {_zz_124,execute_INSTRUCTION[31 : 24]}; + _zz_127 = {_zz_126,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_125; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_127; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -3509,73 +3649,75 @@ module VexRiscv ( end end - assign memory_MulDivIterativePlugin_frontendOk = 1'b1; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_156)begin - if(_zz_161)begin - memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; + case(_zz_171) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; end - end - end - - always @ (*) begin - memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; - if((! memory_arbitration_isStuck))begin - memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; - end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase end - assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); - assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); always @ (*) begin - if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; - end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_226); - end - if(memory_MulDivIterativePlugin_mul_counter_willClear)begin - memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; - end + case(_zz_171) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase end - assign _zz_126 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_127 = ((execute_IS_MUL && _zz_126) || 1'b0); - always @ (*) begin - _zz_128[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_128[31 : 0] = execute_RS1; - end - - assign _zz_130 = (_zz_129 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_130 != 32'h0); - assign _zz_28 = decode_SRC1_CTRL; - assign _zz_26 = _zz_54; - assign _zz_41 = decode_to_execute_SRC1_CTRL; - assign _zz_25 = decode_SRC2_CTRL; - assign _zz_23 = _zz_53; - assign _zz_40 = decode_to_execute_SRC2_CTRL; - assign _zz_22 = decode_ALU_CTRL; - assign _zz_20 = _zz_52; - assign _zz_42 = decode_to_execute_ALU_CTRL; - assign _zz_19 = decode_ALU_BITWISE_CTRL; - assign _zz_17 = _zz_51; - assign _zz_43 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_16 = decode_SHIFT_CTRL; - assign _zz_14 = _zz_50; - assign _zz_38 = decode_to_execute_SHIFT_CTRL; + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_230) + $signed(_zz_231)); + assign _zz_129 = (_zz_128 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_129 != 32'h0); + assign _zz_30 = decode_SRC1_CTRL; + assign _zz_28 = _zz_57; + assign _zz_44 = decode_to_execute_SRC1_CTRL; + assign _zz_27 = decode_SRC2_CTRL; + assign _zz_25 = _zz_56; + assign _zz_43 = decode_to_execute_SRC2_CTRL; + assign _zz_24 = decode_ALU_CTRL; + assign _zz_22 = _zz_55; + assign _zz_45 = decode_to_execute_ALU_CTRL; + assign _zz_21 = decode_ALU_BITWISE_CTRL; + assign _zz_19 = _zz_54; + assign _zz_46 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_18 = decode_SHIFT_CTRL; + assign _zz_15 = execute_SHIFT_CTRL; + assign _zz_16 = _zz_53; + assign _zz_41 = decode_to_execute_SHIFT_CTRL; + assign _zz_40 = execute_to_memory_SHIFT_CTRL; assign _zz_13 = decode_BRANCH_CTRL; - assign _zz_11 = _zz_49; - assign _zz_36 = decode_to_execute_BRANCH_CTRL; + assign _zz_11 = _zz_52; + assign _zz_38 = decode_to_execute_BRANCH_CTRL; assign _zz_10 = decode_ENV_CTRL; assign _zz_7 = execute_ENV_CTRL; assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_48; - assign _zz_34 = decode_to_execute_ENV_CTRL; - assign _zz_33 = execute_to_memory_ENV_CTRL; - assign _zz_35 = memory_to_writeBack_ENV_CTRL; + assign _zz_8 = _zz_51; + assign _zz_36 = decode_to_execute_ENV_CTRL; + assign _zz_35 = execute_to_memory_ENV_CTRL; + assign _zz_37 = memory_to_writeBack_ENV_CTRL; assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_47; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_1 = _zz_50; + assign _zz_33 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -3597,105 +3739,105 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_131 = 32'h0; + _zz_130 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_131[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_131[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_131[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_130[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_130[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_130[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_132 = 32'h0; + _zz_131 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_132[11 : 11] = CsrPlugin_mip_MEIP; - _zz_132[7 : 7] = CsrPlugin_mip_MTIP; - _zz_132[3 : 3] = CsrPlugin_mip_MSIP; + _zz_131[11 : 11] = CsrPlugin_mip_MEIP; + _zz_131[7 : 7] = CsrPlugin_mip_MTIP; + _zz_131[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_133 = 32'h0; + _zz_132 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_133[11 : 11] = CsrPlugin_mie_MEIE; - _zz_133[7 : 7] = CsrPlugin_mie_MTIE; - _zz_133[3 : 3] = CsrPlugin_mie_MSIE; + _zz_132[11 : 11] = CsrPlugin_mie_MEIE; + _zz_132[7 : 7] = CsrPlugin_mie_MTIE; + _zz_132[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_134 = 32'h0; + _zz_133 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_134[31 : 0] = CsrPlugin_mepc; + _zz_133[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_135 = 32'h0; + _zz_134 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_135[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_135[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_134[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_134[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_136 = 32'h0; + _zz_135 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_136[31 : 0] = CsrPlugin_mtval; + _zz_135[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_137 = 32'h0; + _zz_136 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_137[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_136[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_138 = 32'h0; + _zz_137 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_138[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_137[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_139 = 32'h0; + _zz_138 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_139[31 : 0] = _zz_129; + _zz_138[31 : 0] = _zz_128; end end always @ (*) begin - _zz_140 = 32'h0; + _zz_139 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_140[31 : 0] = _zz_130; + _zz_139[31 : 0] = _zz_129; end end - assign execute_CsrPlugin_readData = ((((_zz_131 | _zz_132) | (_zz_133 | _zz_134)) | ((_zz_135 | _zz_136) | (_zz_137 | _zz_138))) | (_zz_139 | _zz_140)); - assign iBusWishbone_ADR = {_zz_243,_zz_141}; - assign iBusWishbone_CTI = ((_zz_141 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = ((((_zz_130 | _zz_131) | (_zz_132 | _zz_133)) | ((_zz_134 | _zz_135) | (_zz_136 | _zz_137))) | (_zz_138 | _zz_139)); + assign iBusWishbone_ADR = {_zz_240,_zz_140}; + assign iBusWishbone_CTI = ((_zz_140 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_175)begin + if(_zz_172)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_175)begin + if(_zz_172)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_142; + assign iBus_rsp_valid = _zz_141; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; @@ -3710,19 +3852,19 @@ module VexRiscv ( always @ (*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_143 = 4'b0001; + _zz_142 = 4'b0001; end 2'b01 : begin - _zz_143 = 4'b0011; + _zz_142 = 4'b0011; end default : begin - _zz_143 = 4'b1111; + _zz_142 = 4'b1111; end endcase end always @ (*) begin - dBusWishbone_SEL = (_zz_143 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + dBusWishbone_SEL = (_zz_142 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); if((! dBus_cmd_halfPipe_payload_wr))begin dBusWishbone_SEL = 4'b1111; end @@ -3742,18 +3884,17 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_67 <= 1'b0; - _zz_69 <= 1'b0; + _zz_70 <= 1'b0; + _zz_72 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_71; + IBusCachedPlugin_rspCounter <= _zz_74; IBusCachedPlugin_rspCounter <= 32'h0; - _zz_95 <= 1'b1; - execute_LightShifterPlugin_isActive <= 1'b0; - _zz_106 <= 1'b0; + _zz_96 <= 1'b1; + _zz_108 <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3773,14 +3914,13 @@ module VexRiscv ( execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; - _zz_129 <= 32'h0; + _zz_128 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_141 <= 3'b000; - _zz_142 <= 1'b0; + _zz_140 <= 3'b000; + _zz_141 <= 1'b0; dBus_cmd_halfPipe_regs_valid <= 1'b0; dBus_cmd_halfPipe_regs_ready <= 1'b1; end else begin @@ -3804,16 +3944,16 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_67 <= 1'b0; + _zz_70 <= 1'b0; end - if(_zz_65)begin - _zz_67 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_68)begin + _zz_70 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_69 <= 1'b0; + _zz_72 <= 1'b0; end if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_69 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; @@ -3880,19 +4020,8 @@ module VexRiscv ( end `endif `endif - _zz_95 <= 1'b0; - if(_zz_157)begin - if(_zz_176)begin - execute_LightShifterPlugin_isActive <= 1'b1; - if(execute_LightShifterPlugin_done)begin - execute_LightShifterPlugin_isActive <= 1'b0; - end - end - end - if(execute_arbitration_removeIt)begin - execute_LightShifterPlugin_isActive <= 1'b0; - end - _zz_106 <= (_zz_45 && writeBack_arbitration_isFiring); + _zz_96 <= 1'b0; + _zz_108 <= (_zz_48 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -3914,14 +4043,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_177)begin - if(_zz_178)begin + if(_zz_173)begin + if(_zz_174)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_179)begin + if(_zz_175)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_180)begin + if(_zz_176)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -3945,7 +4074,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_163)begin + if(_zz_159)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3956,8 +4085,8 @@ module VexRiscv ( end endcase end - if(_zz_164)begin - case(_zz_165) + if(_zz_160)begin + case(_zz_161) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3967,7 +4096,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_120,{_zz_119,_zz_118}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_122,{_zz_121,_zz_120}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -3983,12 +4112,11 @@ module VexRiscv ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_181)begin + if(_zz_177)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end - memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_32; end if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin execute_arbitration_isValid <= 1'b0; @@ -4011,29 +4139,29 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_237[0]; - CsrPlugin_mstatus_MIE <= _zz_238[0]; + CsrPlugin_mstatus_MPIE <= _zz_234[0]; + CsrPlugin_mstatus_MIE <= _zz_235[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_240[0]; - CsrPlugin_mie_MTIE <= _zz_241[0]; - CsrPlugin_mie_MSIE <= _zz_242[0]; + CsrPlugin_mie_MEIE <= _zz_237[0]; + CsrPlugin_mie_MTIE <= _zz_238[0]; + CsrPlugin_mie_MSIE <= _zz_239[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_129 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_128 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_175)begin + if(_zz_172)begin if(iBusWishbone_ACK)begin - _zz_141 <= (_zz_141 + 3'b001); + _zz_140 <= (_zz_140 + 3'b001); end end - _zz_142 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_182)begin + _zz_141 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_178)begin dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); end else begin @@ -4045,7 +4173,7 @@ module VexRiscv ( always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_70 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_73 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; @@ -4053,12 +4181,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_157)begin - if(_zz_176)begin - execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); - end - end - _zz_107 <= _zz_44[11 : 7]; + _zz_109 <= _zz_47[11 : 7]; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -4074,25 +4197,25 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_162)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_122 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_122 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(_zz_158)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_124 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_124 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); end - if(_zz_177)begin - if(_zz_178)begin + if(_zz_173)begin + if(_zz_174)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_179)begin + if(_zz_175)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_180)begin + if(_zz_176)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_163)begin + if(_zz_159)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -4106,27 +4229,16 @@ module VexRiscv ( end endcase end - if(_zz_181)begin + if(_zz_177)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end - if(_zz_156)begin - if(_zz_161)begin - memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_227,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); - end - end - if((! memory_arbitration_isStuck))begin - memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_127 ? (~ _zz_128) : _zz_128) + _zz_234); - memory_MulDivIterativePlugin_rs2 <= ((_zz_126 ? (~ execute_RS2) : execute_RS2) + _zz_236); - end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin decode_to_execute_PC <= decode_PC; end if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_39; + execute_to_memory_PC <= _zz_42; end if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin memory_to_writeBack_PC <= memory_PC; @@ -4144,13 +4256,13 @@ module VexRiscv ( decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_56; + execute_to_memory_FORMAL_PC_NEXT <= _zz_59; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_57; + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_60; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_27; + decode_to_execute_SRC1_CTRL <= _zz_29; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; @@ -4165,7 +4277,7 @@ module VexRiscv ( memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_24; + decode_to_execute_SRC2_CTRL <= _zz_26; end if((! execute_arbitration_isStuck))begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; @@ -4195,16 +4307,19 @@ module VexRiscv ( memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_21; + decode_to_execute_ALU_CTRL <= _zz_23; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_18; + decode_to_execute_ALU_BITWISE_CTRL <= _zz_20; end if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_15; + decode_to_execute_SHIFT_CTRL <= _zz_17; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_14; end if((! execute_arbitration_isStuck))begin decode_to_execute_BRANCH_CTRL <= _zz_12; @@ -4233,11 +4348,8 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; end if((! execute_arbitration_isStuck))begin decode_to_execute_RS1 <= decode_RS1; @@ -4274,18 +4386,39 @@ module VexRiscv ( execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_34; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_39; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_31; + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_29; + memory_to_writeBack_MUL_HH <= memory_MUL_HH; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end @@ -4321,7 +4454,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_239[0]; + CsrPlugin_mip_MSIP <= _zz_236[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -4336,7 +4469,7 @@ module VexRiscv ( end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_182)begin + if(_zz_178)begin dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; @@ -4390,12 +4523,12 @@ module InstructionCache ( input reset ); reg [31:0] _zz_9; - reg [24:0] _zz_10; + reg [22:0] _zz_10; wire _zz_11; wire _zz_12; wire [0:0] _zz_13; wire [0:0] _zz_14; - wire [24:0] _zz_15; + wire [22:0] _zz_15; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -4403,7 +4536,7 @@ module InstructionCache ( (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; - reg [4:0] lineLoader_flushCounter; + reg [6:0] lineLoader_flushCounter; reg _zz_3; reg lineLoader_cmdSent; reg lineLoader_wayToAllocate_willIncrement; @@ -4412,23 +4545,23 @@ module InstructionCache ( wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; wire lineLoader_write_tag_0_valid; - wire [3:0] lineLoader_write_tag_0_payload_address; + wire [5:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [22:0] lineLoader_write_tag_0_payload_data_address; + wire [20:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [6:0] lineLoader_write_data_0_payload_address; + wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [6:0] _zz_4; + wire [8:0] _zz_4; wire _zz_5; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [3:0] _zz_6; + wire [5:0] _zz_6; wire _zz_7; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [22:0] fetchStage_read_waysValues_0_tag_address; - wire [24:0] _zz_8; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_8; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; @@ -4446,10 +4579,10 @@ module InstructionCache ( reg decodeStage_mmuRsp_bypassTranslation; reg decodeStage_hit_valid; reg decodeStage_hit_error; - (* ram_style = "block" *) reg [31:0] banks_0 [0:127]; - (* ram_style = "block" *) reg [24:0] ways_0_tags [0:15]; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_11 = (! lineLoader_flushCounter[4]); + assign _zz_11 = (! lineLoader_flushCounter[6]); assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); assign _zz_13 = _zz_8[0 : 0]; assign _zz_14 = _zz_8[1 : 1]; @@ -4527,25 +4660,25 @@ module InstructionCache ( assign lineLoader_wayToAllocate_willClear = 1'b0; assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[4])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[4] ? lineLoader_address[8 : 5] : lineLoader_flushCounter[3 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[4]; + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 9]; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[8 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[8 : 2]; + assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; assign _zz_5 = (! io_cpu_fetch_isStuck); assign fetchStage_read_banksValue_0_dataMem = _zz_9; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[8 : 5]; + assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; assign _zz_7 = (! io_cpu_fetch_isStuck); assign _zz_8 = _zz_10; assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[24 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 9])); + assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; @@ -4601,11 +4734,11 @@ module InstructionCache ( lineLoader_address <= io_cpu_fill_payload; end if(_zz_11)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 5'h01); + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[4]; + _zz_3 <= lineLoader_flushCounter[6]; if(_zz_12)begin - lineLoader_flushCounter <= 5'h0; + lineLoader_flushCounter <= 7'h0; end if((! io_cpu_decode_isStuck))begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml index fa5fb80..b55f8e5 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.yaml @@ -1,4 +1,4 @@ iBus: !!vexriscv.BusReport flushInstructions: [4111, 19, 19, 19] - info: !!vexriscv.CacheReport {bytePerLine: 32, size: 512} + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala index 60d8c57..c597a30 100644 --- a/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala +++ b/pythondata_cpu_vexriscv/verilog/src/main/scala/vexriscv/GenCoreDefault.scala @@ -255,10 +255,10 @@ object GenCoreDefault{ if(argConfig.mulDiv) { if(argConfig.singleCycleMulDiv) { - plugins ++= List( - new MulPlugin, - new DivPlugin - ) + plugins ++= List(new MulPlugin) + if (argConfig.hardwareDiv) { + plugins ++= List(new DivPlugin) + } }else { plugins ++= List( new MulDivIterativePlugin( From 5bb91146a62643cf606443d5366c69720906549c Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Mon, 30 Aug 2021 23:29:03 -0700 Subject: [PATCH 23/30] New "perf" variant has perfCSRs. Also increase "Slim" D$ to 4kB, I$ to 2kB. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 16 +- .../verilog/VexRiscv_FullCfu.v | 2362 +++--- .../verilog/VexRiscv_FullCfuDebug.v | 2462 +++--- .../verilog/VexRiscv_PerfCfu.v | 7159 ++++++++++++++++ .../verilog/VexRiscv_PerfCfu.yaml | 4 + .../verilog/VexRiscv_PerfCfuDebug.v | 7457 +++++++++++++++++ .../verilog/VexRiscv_PerfCfuDebug.yaml | 5 + .../verilog/VexRiscv_SlimCfu.v | 4758 ++++++----- .../verilog/VexRiscv_SlimCfu.yaml | 2 +- .../verilog/VexRiscv_SlimCfuDebug.v | 4813 ++++++----- .../verilog/VexRiscv_SlimCfuDebug.yaml | 2 +- 11 files changed, 22112 insertions(+), 6928 deletions(-) create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.yaml create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.yaml diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index db48c99..bf7337a 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -1,6 +1,6 @@ SRC := ${shell find . -type f -name \*.scala} -all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_SlimCfu.v VexRiscv_SlimCfuDebug.v VexRiscv_Fomu.v VexRiscv_FomuCfu.v +all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_SlimCfu.v VexRiscv_SlimCfuDebug.v VexRiscv_Fomu.v VexRiscv_FomuCfu.v VexRiscv_PerfCfu.v VexRiscv_PerfCfuDebug.v VexRiscv.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault" @@ -38,21 +38,23 @@ VexRiscv_Full.v: $(SRC) VexRiscv_FullDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --outputFile VexRiscv_FullDebug" -# CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfu.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfu" -# CFU versions must have module name changed because they will be wrapped VexRiscv_FullCfuDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfuDebug" -# CFU versions must have module name changed because they will be wrapped +VexRiscv_PerfCfu.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_PerfCfu" + +VexRiscv_PerfCfuDebug.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_PerfCfuDebug" + VexRiscv_SlimCfu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 1024 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfu" + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all --cfu true --outputFile VexRiscv_SlimCfu" -# CFU versions must have module name changed because they will be wrapped VexRiscv_SlimCfuDebug.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 0 --iCacheSize 1024 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimCfuDebug" + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all -d --cfu true --outputFile VexRiscv_SlimCfuDebug" VexRiscv_Linux.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal --outputFile VexRiscv_Linux" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index 00fd249..0511bba 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 +// Git hash : 9c3529c14328ee22a18ec0f74e66ca59de7346c3 `define Input2Kind_defaultEncoding_type [0:0] @@ -87,37 +87,37 @@ module VexRiscv ( input clk, input reset ); + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + reg _zz_201; + wire _zz_202; + wire [31:0] _zz_203; + wire _zz_204; + wire [31:0] _zz_205; + reg _zz_206; + wire _zz_207; + wire _zz_208; + wire [31:0] _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; wire _zz_217; - wire _zz_218; + wire [3:0] _zz_218; wire _zz_219; wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - reg _zz_225; - wire _zz_226; - wire [31:0] _zz_227; - wire _zz_228; - wire [31:0] _zz_229; - reg _zz_230; - wire _zz_231; - wire _zz_232; - wire [31:0] _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire [3:0] _zz_242; - wire _zz_243; - wire _zz_244; - reg [31:0] _zz_245; - reg [31:0] _zz_246; - reg [31:0] _zz_247; + reg [31:0] _zz_221; + reg [31:0] _zz_222; + reg [31:0] _zz_223; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -150,9 +150,33 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire [1:0] _zz_239; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire _zz_245; + wire _zz_246; + wire _zz_247; wire _zz_248; wire _zz_249; - wire _zz_250; + wire [1:0] _zz_250; wire _zz_251; wire _zz_252; wire _zz_253; @@ -162,327 +186,303 @@ module VexRiscv ( wire _zz_257; wire _zz_258; wire _zz_259; - wire _zz_260; + wire [1:0] _zz_260; wire _zz_261; - wire _zz_262; - wire [1:0] _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire _zz_267; - wire _zz_268; - wire _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire [1:0] _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire _zz_279; - wire _zz_280; - wire _zz_281; - wire _zz_282; - wire _zz_283; - wire [1:0] _zz_284; - wire _zz_285; - wire [1:0] _zz_286; - wire [51:0] _zz_287; - wire [51:0] _zz_288; - wire [51:0] _zz_289; - wire [32:0] _zz_290; - wire [51:0] _zz_291; - wire [49:0] _zz_292; - wire [51:0] _zz_293; - wire [49:0] _zz_294; - wire [51:0] _zz_295; - wire [32:0] _zz_296; + wire [1:0] _zz_262; + wire [51:0] _zz_263; + wire [51:0] _zz_264; + wire [51:0] _zz_265; + wire [32:0] _zz_266; + wire [51:0] _zz_267; + wire [49:0] _zz_268; + wire [51:0] _zz_269; + wire [49:0] _zz_270; + wire [51:0] _zz_271; + wire [32:0] _zz_272; + wire [31:0] _zz_273; + wire [32:0] _zz_274; + wire [0:0] _zz_275; + wire [0:0] _zz_276; + wire [0:0] _zz_277; + wire [0:0] _zz_278; + wire [0:0] _zz_279; + wire [0:0] _zz_280; + wire [0:0] _zz_281; + wire [0:0] _zz_282; + wire [0:0] _zz_283; + wire [0:0] _zz_284; + wire [0:0] _zz_285; + wire [0:0] _zz_286; + wire [0:0] _zz_287; + wire [0:0] _zz_288; + wire [0:0] _zz_289; + wire [0:0] _zz_290; + wire [0:0] _zz_291; + wire [0:0] _zz_292; + wire [3:0] _zz_293; + wire [2:0] _zz_294; + wire [31:0] _zz_295; + wire [11:0] _zz_296; wire [31:0] _zz_297; - wire [32:0] _zz_298; - wire [0:0] _zz_299; - wire [0:0] _zz_300; - wire [0:0] _zz_301; - wire [0:0] _zz_302; - wire [0:0] _zz_303; - wire [0:0] _zz_304; - wire [0:0] _zz_305; + wire [19:0] _zz_298; + wire [11:0] _zz_299; + wire [31:0] _zz_300; + wire [31:0] _zz_301; + wire [19:0] _zz_302; + wire [11:0] _zz_303; + wire [2:0] _zz_304; + wire [2:0] _zz_305; wire [0:0] _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire [0:0] _zz_312; - wire [0:0] _zz_313; - wire [0:0] _zz_314; - wire [0:0] _zz_315; - wire [0:0] _zz_316; - wire [3:0] _zz_317; - wire [2:0] _zz_318; - wire [31:0] _zz_319; + wire [2:0] _zz_307; + wire [4:0] _zz_308; + wire [11:0] _zz_309; + wire [11:0] _zz_310; + wire [31:0] _zz_311; + wire [31:0] _zz_312; + wire [31:0] _zz_313; + wire [31:0] _zz_314; + wire [31:0] _zz_315; + wire [31:0] _zz_316; + wire [31:0] _zz_317; + wire [11:0] _zz_318; + wire [19:0] _zz_319; wire [11:0] _zz_320; wire [31:0] _zz_321; - wire [19:0] _zz_322; - wire [11:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [19:0] _zz_326; - wire [11:0] _zz_327; - wire [2:0] _zz_328; - wire [2:0] _zz_329; - wire [0:0] _zz_330; - wire [2:0] _zz_331; - wire [4:0] _zz_332; - wire [11:0] _zz_333; - wire [11:0] _zz_334; - wire [31:0] _zz_335; + wire [31:0] _zz_322; + wire [31:0] _zz_323; + wire [11:0] _zz_324; + wire [19:0] _zz_325; + wire [11:0] _zz_326; + wire [2:0] _zz_327; + wire [1:0] _zz_328; + wire [1:0] _zz_329; + wire [1:0] _zz_330; + wire [1:0] _zz_331; + wire [9:0] _zz_332; + wire [7:0] _zz_333; + wire [65:0] _zz_334; + wire [65:0] _zz_335; wire [31:0] _zz_336; wire [31:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire [31:0] _zz_340; + wire [0:0] _zz_338; + wire [5:0] _zz_339; + wire [32:0] _zz_340; wire [31:0] _zz_341; - wire [11:0] _zz_342; - wire [19:0] _zz_343; - wire [11:0] _zz_344; - wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [11:0] _zz_348; - wire [19:0] _zz_349; - wire [11:0] _zz_350; - wire [2:0] _zz_351; - wire [1:0] _zz_352; - wire [1:0] _zz_353; - wire [1:0] _zz_354; - wire [1:0] _zz_355; - wire [9:0] _zz_356; - wire [7:0] _zz_357; - wire [65:0] _zz_358; - wire [65:0] _zz_359; - wire [31:0] _zz_360; - wire [31:0] _zz_361; - wire [0:0] _zz_362; - wire [5:0] _zz_363; - wire [32:0] _zz_364; + wire [31:0] _zz_342; + wire [32:0] _zz_343; + wire [32:0] _zz_344; + wire [32:0] _zz_345; + wire [32:0] _zz_346; + wire [0:0] _zz_347; + wire [32:0] _zz_348; + wire [0:0] _zz_349; + wire [32:0] _zz_350; + wire [0:0] _zz_351; + wire [31:0] _zz_352; + wire [0:0] _zz_353; + wire [0:0] _zz_354; + wire [0:0] _zz_355; + wire [0:0] _zz_356; + wire [0:0] _zz_357; + wire [0:0] _zz_358; + wire [0:0] _zz_359; + wire [26:0] _zz_360; + wire _zz_361; + wire _zz_362; + wire [1:0] _zz_363; + wire [31:0] _zz_364; wire [31:0] _zz_365; wire [31:0] _zz_366; - wire [32:0] _zz_367; - wire [32:0] _zz_368; - wire [32:0] _zz_369; - wire [32:0] _zz_370; - wire [0:0] _zz_371; - wire [32:0] _zz_372; - wire [0:0] _zz_373; - wire [32:0] _zz_374; - wire [0:0] _zz_375; + wire _zz_367; + wire [0:0] _zz_368; + wire [14:0] _zz_369; + wire [31:0] _zz_370; + wire [31:0] _zz_371; + wire [31:0] _zz_372; + wire _zz_373; + wire [0:0] _zz_374; + wire [8:0] _zz_375; wire [31:0] _zz_376; - wire [0:0] _zz_377; - wire [0:0] _zz_378; - wire [0:0] _zz_379; + wire [31:0] _zz_377; + wire [31:0] _zz_378; + wire _zz_379; wire [0:0] _zz_380; - wire [0:0] _zz_381; - wire [0:0] _zz_382; - wire [0:0] _zz_383; - wire [26:0] _zz_384; - wire _zz_385; - wire _zz_386; - wire [1:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire _zz_391; - wire [0:0] _zz_392; - wire [14:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire _zz_397; - wire [0:0] _zz_398; - wire [8:0] _zz_399; - wire [31:0] _zz_400; + wire [2:0] _zz_381; + wire _zz_382; + wire _zz_383; + wire _zz_384; + wire [31:0] _zz_385; + wire [31:0] _zz_386; + wire _zz_387; + wire _zz_388; + wire [0:0] _zz_389; + wire [26:0] _zz_390; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire [31:0] _zz_393; + wire [0:0] _zz_394; + wire [0:0] _zz_395; + wire [1:0] _zz_396; + wire [1:0] _zz_397; + wire _zz_398; + wire [0:0] _zz_399; + wire [21:0] _zz_400; wire [31:0] _zz_401; wire [31:0] _zz_402; - wire _zz_403; - wire [0:0] _zz_404; - wire [2:0] _zz_405; - wire _zz_406; - wire _zz_407; - wire _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire [31:0] _zz_405; + wire [31:0] _zz_406; + wire [0:0] _zz_407; + wire [0:0] _zz_408; + wire [2:0] _zz_409; + wire [2:0] _zz_410; wire _zz_411; - wire _zz_412; - wire [0:0] _zz_413; - wire [26:0] _zz_414; + wire [0:0] _zz_412; + wire [18:0] _zz_413; + wire [31:0] _zz_414; wire [31:0] _zz_415; wire [31:0] _zz_416; wire [31:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire [1:0] _zz_420; - wire [1:0] _zz_421; + wire _zz_418; + wire _zz_419; + wire [31:0] _zz_420; + wire [31:0] _zz_421; wire _zz_422; wire [0:0] _zz_423; - wire [21:0] _zz_424; - wire [31:0] _zz_425; - wire [31:0] _zz_426; - wire [31:0] _zz_427; + wire [0:0] _zz_424; + wire _zz_425; + wire [0:0] _zz_426; + wire [15:0] _zz_427; wire [31:0] _zz_428; - wire [31:0] _zz_429; - wire [31:0] _zz_430; - wire [0:0] _zz_431; - wire [0:0] _zz_432; + wire _zz_429; + wire _zz_430; + wire _zz_431; + wire [2:0] _zz_432; wire [2:0] _zz_433; - wire [2:0] _zz_434; - wire _zz_435; - wire [0:0] _zz_436; - wire [18:0] _zz_437; - wire [31:0] _zz_438; - wire [31:0] _zz_439; - wire [31:0] _zz_440; - wire [31:0] _zz_441; + wire _zz_434; + wire [0:0] _zz_435; + wire [12:0] _zz_436; + wire _zz_437; + wire _zz_438; + wire _zz_439; + wire [0:0] _zz_440; + wire [2:0] _zz_441; wire _zz_442; - wire _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire _zz_446; - wire [0:0] _zz_447; - wire [0:0] _zz_448; - wire _zz_449; - wire [0:0] _zz_450; - wire [15:0] _zz_451; + wire [5:0] _zz_443; + wire [5:0] _zz_444; + wire _zz_445; + wire [0:0] _zz_446; + wire [9:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire [31:0] _zz_450; + wire [31:0] _zz_451; wire [31:0] _zz_452; wire _zz_453; - wire _zz_454; - wire _zz_455; - wire [2:0] _zz_456; - wire [2:0] _zz_457; - wire _zz_458; - wire [0:0] _zz_459; - wire [12:0] _zz_460; - wire _zz_461; - wire _zz_462; - wire _zz_463; - wire [0:0] _zz_464; - wire [2:0] _zz_465; - wire _zz_466; - wire [5:0] _zz_467; - wire [5:0] _zz_468; - wire _zz_469; - wire [0:0] _zz_470; - wire [9:0] _zz_471; + wire [0:0] _zz_454; + wire [0:0] _zz_455; + wire [31:0] _zz_456; + wire _zz_457; + wire [0:0] _zz_458; + wire [3:0] _zz_459; + wire [0:0] _zz_460; + wire [3:0] _zz_461; + wire [5:0] _zz_462; + wire [5:0] _zz_463; + wire _zz_464; + wire [0:0] _zz_465; + wire [7:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; wire [31:0] _zz_472; wire [31:0] _zz_473; wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; + wire [0:0] _zz_475; + wire [1:0] _zz_476; wire _zz_477; wire [0:0] _zz_478; - wire [0:0] _zz_479; - wire [31:0] _zz_480; - wire _zz_481; + wire [1:0] _zz_479; + wire [0:0] _zz_480; + wire [3:0] _zz_481; wire [0:0] _zz_482; - wire [3:0] _zz_483; - wire [0:0] _zz_484; - wire [3:0] _zz_485; - wire [5:0] _zz_486; - wire [5:0] _zz_487; - wire _zz_488; - wire [0:0] _zz_489; - wire [7:0] _zz_490; - wire [31:0] _zz_491; - wire [31:0] _zz_492; + wire [0:0] _zz_483; + wire [1:0] _zz_484; + wire [1:0] _zz_485; + wire _zz_486; + wire [0:0] _zz_487; + wire [5:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; + wire _zz_491; + wire _zz_492; wire [31:0] _zz_493; wire [31:0] _zz_494; wire [31:0] _zz_495; - wire [31:0] _zz_496; - wire [31:0] _zz_497; + wire _zz_496; + wire _zz_497; wire [31:0] _zz_498; - wire [0:0] _zz_499; - wire [1:0] _zz_500; - wire _zz_501; - wire [0:0] _zz_502; - wire [1:0] _zz_503; - wire [0:0] _zz_504; - wire [3:0] _zz_505; - wire [0:0] _zz_506; + wire [31:0] _zz_499; + wire _zz_500; + wire [0:0] _zz_501; + wire [1:0] _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire _zz_505; + wire _zz_506; wire [0:0] _zz_507; - wire [1:0] _zz_508; - wire [1:0] _zz_509; - wire _zz_510; - wire [0:0] _zz_511; - wire [5:0] _zz_512; + wire [0:0] _zz_508; + wire _zz_509; + wire [0:0] _zz_510; + wire [3:0] _zz_511; + wire [31:0] _zz_512; wire [31:0] _zz_513; wire [31:0] _zz_514; - wire _zz_515; - wire _zz_516; + wire [31:0] _zz_515; + wire [31:0] _zz_516; wire [31:0] _zz_517; wire [31:0] _zz_518; - wire [31:0] _zz_519; + wire _zz_519; wire _zz_520; - wire _zz_521; + wire [31:0] _zz_521; wire [31:0] _zz_522; wire [31:0] _zz_523; - wire _zz_524; + wire [31:0] _zz_524; wire [0:0] _zz_525; - wire [1:0] _zz_526; - wire [31:0] _zz_527; - wire [31:0] _zz_528; + wire [2:0] _zz_526; + wire [0:0] _zz_527; + wire [0:0] _zz_528; wire _zz_529; - wire _zz_530; - wire [0:0] _zz_531; - wire [0:0] _zz_532; - wire _zz_533; - wire [0:0] _zz_534; - wire [3:0] _zz_535; - wire [31:0] _zz_536; + wire [0:0] _zz_530; + wire [1:0] _zz_531; + wire [31:0] _zz_532; + wire [31:0] _zz_533; + wire [31:0] _zz_534; + wire _zz_535; + wire _zz_536; wire [31:0] _zz_537; - wire [31:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire [31:0] _zz_541; - wire [31:0] _zz_542; - wire _zz_543; - wire _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; + wire _zz_538; + wire [0:0] _zz_539; + wire [0:0] _zz_540; + wire [0:0] _zz_541; + wire [0:0] _zz_542; + wire [1:0] _zz_543; + wire [1:0] _zz_544; + wire [0:0] _zz_545; + wire [0:0] _zz_546; wire [31:0] _zz_547; wire [31:0] _zz_548; - wire [0:0] _zz_549; - wire [2:0] _zz_550; - wire [0:0] _zz_551; - wire [0:0] _zz_552; + wire [31:0] _zz_549; + wire [31:0] _zz_550; + wire [31:0] _zz_551; + wire [31:0] _zz_552; wire _zz_553; - wire [0:0] _zz_554; - wire [1:0] _zz_555; + wire _zz_554; + wire _zz_555; wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire _zz_559; - wire _zz_560; - wire [31:0] _zz_561; - wire _zz_562; - wire [0:0] _zz_563; - wire [0:0] _zz_564; - wire [0:0] _zz_565; - wire [0:0] _zz_566; - wire [1:0] _zz_567; - wire [1:0] _zz_568; - wire [0:0] _zz_569; - wire [0:0] _zz_570; - wire [31:0] _zz_571; - wire [31:0] _zz_572; - wire [31:0] _zz_573; - wire [31:0] _zz_574; - wire [31:0] _zz_575; - wire [31:0] _zz_576; - wire _zz_577; - wire _zz_578; - wire _zz_579; - wire [31:0] _zz_580; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1074,29 +1074,13 @@ module VexRiscv ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_167; - reg [23:0] _zz_168; - reg [31:0] _zz_169; + wire _zz_151; + reg [23:0] _zz_152; + reg [31:0] _zz_153; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1128,18 +1112,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_170; + wire [31:0] _zz_154; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_171; - wire _zz_172; - wire _zz_173; - reg [32:0] _zz_174; + wire [31:0] _zz_155; + wire _zz_156; + wire _zz_157; + reg [32:0] _zz_158; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_175; - wire [31:0] _zz_176; + reg [31:0] _zz_159; + wire [31:0] _zz_160; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1226,24 +1210,24 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3200; reg execute_CsrPlugin_csr_3074; reg execute_CsrPlugin_csr_3202; - reg execute_CsrPlugin_csr_2820; - reg execute_CsrPlugin_csr_2821; - reg execute_CsrPlugin_csr_2822; - reg execute_CsrPlugin_csr_2823; - reg execute_CsrPlugin_csr_2824; - reg execute_CsrPlugin_csr_2825; - reg execute_CsrPlugin_csr_2826; - reg execute_CsrPlugin_csr_2827; - reg execute_CsrPlugin_csr_2828; - reg execute_CsrPlugin_csr_2829; - reg execute_CsrPlugin_csr_2830; - reg execute_CsrPlugin_csr_2831; - reg execute_CsrPlugin_csr_2832; - reg execute_CsrPlugin_csr_2833; - reg execute_CsrPlugin_csr_2834; - reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; reg [31:0] _zz_177; reg [31:0] _zz_178; reg [31:0] _zz_179; @@ -1251,40 +1235,16 @@ module VexRiscv ( reg [31:0] _zz_181; reg [31:0] _zz_182; reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [31:0] _zz_199; - reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; - reg [2:0] _zz_208; - reg _zz_209; + reg [2:0] _zz_184; + reg _zz_185; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - reg _zz_216; + reg [2:0] _zz_186; + wire _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + wire _zz_191; + reg _zz_192; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; @@ -1378,348 +1338,348 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_248 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_249 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_250 = 1'b1; - assign _zz_251 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_252 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_254 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_255 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_256 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_257 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_260 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_264 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_265 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_266 = (1'b0 || (! 1'b1)); - assign _zz_267 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_268 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_270 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_271 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_272 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_273 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_274 = execute_INSTRUCTION[13 : 12]; - assign _zz_275 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_276 = (! memory_arbitration_isStuck); - assign _zz_277 = (iBus_cmd_valid || (_zz_208 != 3'b000)); - assign _zz_278 = (_zz_244 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_280 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_281 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_282 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_285 = execute_INSTRUCTION[13]; - assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); - assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); - assign _zz_289 = 52'h0; - assign _zz_290 = {1'b0,memory_MUL_LL}; - assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; - assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; - assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; - assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_297 = _zz_296[31 : 0]; - assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_299 = _zz_93[33 : 33]; - assign _zz_300 = _zz_93[32 : 32]; - assign _zz_301 = _zz_93[31 : 31]; - assign _zz_302 = _zz_93[30 : 30]; - assign _zz_303 = _zz_93[28 : 28]; - assign _zz_304 = _zz_93[25 : 25]; - assign _zz_305 = _zz_93[17 : 17]; - assign _zz_306 = _zz_93[16 : 16]; - assign _zz_307 = _zz_93[13 : 13]; - assign _zz_308 = _zz_93[12 : 12]; - assign _zz_309 = _zz_93[11 : 11]; - assign _zz_310 = _zz_93[15 : 15]; - assign _zz_311 = _zz_93[5 : 5]; - assign _zz_312 = _zz_93[3 : 3]; - assign _zz_313 = _zz_93[20 : 20]; - assign _zz_314 = _zz_93[10 : 10]; - assign _zz_315 = _zz_93[4 : 4]; - assign _zz_316 = _zz_93[0 : 0]; - assign _zz_317 = (_zz_61 - 4'b0001); - assign _zz_318 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_319 = {29'd0, _zz_318}; - assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_321 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_324 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_325 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_326 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_328 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_329 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_330 = execute_SRC_LESS; - assign _zz_331 = 3'b100; - assign _zz_332 = execute_INSTRUCTION[19 : 15]; - assign _zz_333 = execute_INSTRUCTION[31 : 20]; - assign _zz_334 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_335 = ($signed(_zz_336) + $signed(_zz_339)); - assign _zz_336 = ($signed(_zz_337) + $signed(_zz_338)); - assign _zz_337 = execute_SRC1; - assign _zz_338 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_339 = (execute_SRC_USE_SUB_LESS ? _zz_340 : _zz_341); - assign _zz_340 = 32'h00000001; - assign _zz_341 = 32'h0; - assign _zz_342 = execute_INSTRUCTION[31 : 20]; - assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_345 = {_zz_132,execute_INSTRUCTION[31 : 20]}; - assign _zz_346 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_347 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_348 = execute_INSTRUCTION[31 : 20]; - assign _zz_349 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_351 = 3'b100; - assign _zz_352 = (_zz_147 & (~ _zz_353)); - assign _zz_353 = (_zz_147 - 2'b01); - assign _zz_354 = (_zz_149 & (~ _zz_355)); - assign _zz_355 = (_zz_149 - 2'b01); - assign _zz_356 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_357 = execute_INSTRUCTION[31 : 24]; - assign _zz_358 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_359 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_360 = writeBack_MUL_LOW[31 : 0]; - assign _zz_361 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_362 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_363 = {5'd0, _zz_362}; - assign _zz_364 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_365 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_366 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_367 = {_zz_170,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_368 = _zz_369; - assign _zz_369 = _zz_370; - assign _zz_370 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_171) : _zz_171)} + _zz_372); - assign _zz_371 = memory_DivPlugin_div_needRevert; - assign _zz_372 = {32'd0, _zz_371}; - assign _zz_373 = _zz_173; - assign _zz_374 = {32'd0, _zz_373}; - assign _zz_375 = _zz_172; - assign _zz_376 = {31'd0, _zz_375}; - assign _zz_377 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_378 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_380 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_381 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_382 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_383 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_384 = (iBus_cmd_payload_address >>> 5); - assign _zz_385 = 1'b1; - assign _zz_386 = 1'b1; - assign _zz_387 = {_zz_65,_zz_64}; - assign _zz_388 = 32'h0000106f; - assign _zz_389 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_390 = 32'h00001073; - assign _zz_391 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_392 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_393 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_394) == 32'h00000003),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; - assign _zz_394 = 32'h0000207f; - assign _zz_395 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_396 = 32'h00000003; - assign _zz_397 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_398 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_399 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_400) == 32'h00005013),{(_zz_401 == _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; - assign _zz_400 = 32'hbc00707f; - assign _zz_401 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_402 = 32'h00001013; - assign _zz_403 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_405 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_406 = decode_INSTRUCTION[31]; - assign _zz_407 = decode_INSTRUCTION[31]; - assign _zz_408 = decode_INSTRUCTION[7]; - assign _zz_409 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_410 = 32'h02004020; - assign _zz_411 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_412 = (_zz_97 != 1'b0); - assign _zz_413 = (((decode_INSTRUCTION & _zz_415) == 32'h00000050) != 1'b0); - assign _zz_414 = {((_zz_416 == _zz_417) != 1'b0),{({_zz_418,_zz_419} != 2'b00),{(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}}}; - assign _zz_415 = 32'h00203050; - assign _zz_416 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_417 = 32'h00000050; - assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00001050); - assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00002050); - assign _zz_420 = {_zz_96,(_zz_427 == _zz_428)}; - assign _zz_421 = 2'b00; - assign _zz_422 = ((_zz_429 == _zz_430) != 1'b0); - assign _zz_423 = ({_zz_431,_zz_432} != 2'b00); - assign _zz_424 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; - assign _zz_425 = 32'h00001050; - assign _zz_426 = 32'h00002050; - assign _zz_427 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_428 = 32'h00000004; - assign _zz_429 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_430 = 32'h00000040; - assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h00005010); - assign _zz_432 = ((decode_INSTRUCTION & _zz_439) == 32'h00005020); - assign _zz_433 = {(_zz_440 == _zz_441),{_zz_442,_zz_443}}; - assign _zz_434 = 3'b000; - assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); - assign _zz_436 = (_zz_446 != 1'b0); - assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; - assign _zz_438 = 32'h00007034; - assign _zz_439 = 32'h02007064; - assign _zz_440 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_441 = 32'h40001010; - assign _zz_442 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_443 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_445 = 32'h00000024; - assign _zz_446 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_447 = ((decode_INSTRUCTION & _zz_452) == 32'h00002000); - assign _zz_448 = 1'b0; - assign _zz_449 = ({_zz_453,_zz_454} != 2'b00); - assign _zz_450 = (_zz_455 != 1'b0); - assign _zz_451 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; - assign _zz_452 = 32'h00003000; - assign _zz_453 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_454 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_455 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_456 = {_zz_97,{_zz_461,_zz_462}}; - assign _zz_457 = 3'b000; - assign _zz_458 = ({_zz_463,{_zz_464,_zz_465}} != 5'h0); - assign _zz_459 = (_zz_466 != 1'b0); - assign _zz_460 = {(_zz_467 != _zz_468),{_zz_469,{_zz_470,_zz_471}}}; - assign _zz_461 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); - assign _zz_462 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); - assign _zz_463 = ((decode_INSTRUCTION & _zz_474) == 32'h00002040); - assign _zz_464 = (_zz_475 == _zz_476); - assign _zz_465 = {_zz_477,{_zz_478,_zz_479}}; - assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000020); - assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; - assign _zz_468 = 6'h0; - assign _zz_469 = ({_zz_484,_zz_485} != 5'h0); - assign _zz_470 = (_zz_486 != _zz_487); - assign _zz_471 = {_zz_488,{_zz_489,_zz_490}}; - assign _zz_472 = 32'h00000034; - assign _zz_473 = 32'h00000064; - assign _zz_474 = 32'h00002040; - assign _zz_475 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_476 = 32'h00001040; - assign _zz_477 = ((decode_INSTRUCTION & _zz_491) == 32'h00000040); - assign _zz_478 = (_zz_492 == _zz_493); - assign _zz_479 = (_zz_494 == _zz_495); - assign _zz_480 = 32'h00000020; - assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00000008); - assign _zz_482 = (_zz_497 == _zz_498); - assign _zz_483 = {_zz_95,{_zz_499,_zz_500}}; - assign _zz_484 = _zz_95; - assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; - assign _zz_486 = {_zz_96,{_zz_504,_zz_505}}; - assign _zz_487 = 6'h0; - assign _zz_488 = ({_zz_506,_zz_507} != 2'b00); - assign _zz_489 = (_zz_508 != _zz_509); - assign _zz_490 = {_zz_510,{_zz_511,_zz_512}}; - assign _zz_491 = 32'h00000050; - assign _zz_492 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_493 = 32'h00000040; - assign _zz_494 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_495 = 32'h0; - assign _zz_496 = 32'h00000008; - assign _zz_497 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_498 = 32'h00000040; - assign _zz_499 = (_zz_513 == _zz_514); - assign _zz_500 = {_zz_515,_zz_516}; - assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00002010); - assign _zz_502 = (_zz_518 == _zz_519); - assign _zz_503 = {_zz_520,_zz_521}; - assign _zz_504 = (_zz_522 == _zz_523); - assign _zz_505 = {_zz_524,{_zz_525,_zz_526}}; - assign _zz_506 = _zz_95; - assign _zz_507 = (_zz_527 == _zz_528); - assign _zz_508 = {_zz_95,_zz_529}; - assign _zz_509 = 2'b00; - assign _zz_510 = (_zz_530 != 1'b0); - assign _zz_511 = (_zz_531 != _zz_532); - assign _zz_512 = {_zz_533,{_zz_534,_zz_535}}; - assign _zz_513 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_514 = 32'h00004020; - assign _zz_515 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); - assign _zz_516 = ((decode_INSTRUCTION & _zz_537) == 32'h00000020); - assign _zz_517 = 32'h00002030; - assign _zz_518 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_519 = 32'h00000010; - assign _zz_520 = ((decode_INSTRUCTION & _zz_538) == 32'h00002020); - assign _zz_521 = ((decode_INSTRUCTION & _zz_539) == 32'h00000020); - assign _zz_522 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_523 = 32'h00001010; - assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00002010); - assign _zz_525 = (_zz_541 == _zz_542); - assign _zz_526 = {_zz_543,_zz_544}; - assign _zz_527 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_528 = 32'h00000020; - assign _zz_529 = ((decode_INSTRUCTION & _zz_545) == 32'h0); - assign _zz_530 = ((decode_INSTRUCTION & _zz_546) == 32'h00004010); - assign _zz_531 = (_zz_547 == _zz_548); - assign _zz_532 = 1'b0; - assign _zz_533 = ({_zz_549,_zz_550} != 4'b0000); - assign _zz_534 = (_zz_551 != _zz_552); - assign _zz_535 = {_zz_553,{_zz_554,_zz_555}}; - assign _zz_536 = 32'h00000030; - assign _zz_537 = 32'h02000020; - assign _zz_538 = 32'h02002060; - assign _zz_539 = 32'h02003020; - assign _zz_540 = 32'h00002010; - assign _zz_541 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_542 = 32'h00000010; - assign _zz_543 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_544 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_545 = 32'h00000020; - assign _zz_546 = 32'h00004014; - assign _zz_547 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_548 = 32'h00002010; - assign _zz_549 = ((decode_INSTRUCTION & _zz_556) == 32'h0); - assign _zz_550 = {(_zz_557 == _zz_558),{_zz_559,_zz_560}}; - assign _zz_551 = ((decode_INSTRUCTION & _zz_561) == 32'h0); - assign _zz_552 = 1'b0; - assign _zz_553 = ({_zz_562,{_zz_563,_zz_564}} != 3'b000); - assign _zz_554 = ({_zz_565,_zz_566} != 2'b00); - assign _zz_555 = {(_zz_567 != _zz_568),(_zz_569 != _zz_570)}; - assign _zz_556 = 32'h00000044; - assign _zz_557 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_558 = 32'h0; - assign _zz_559 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_560 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_561 = 32'h00000058; - assign _zz_562 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_563 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); - assign _zz_564 = ((decode_INSTRUCTION & _zz_572) == 32'h40000030); - assign _zz_565 = ((decode_INSTRUCTION & _zz_573) == 32'h00000004); - assign _zz_566 = _zz_94; - assign _zz_567 = {(_zz_574 == _zz_575),_zz_94}; - assign _zz_568 = 2'b00; - assign _zz_569 = ((decode_INSTRUCTION & _zz_576) == 32'h00001004); - assign _zz_570 = 1'b0; - assign _zz_571 = 32'h00002014; - assign _zz_572 = 32'h40000034; - assign _zz_573 = 32'h00000014; - assign _zz_574 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_575 = 32'h00000004; - assign _zz_576 = 32'h00005054; - assign _zz_577 = execute_INSTRUCTION[31]; - assign _zz_578 = execute_INSTRUCTION[31]; - assign _zz_579 = execute_INSTRUCTION[7]; - assign _zz_580 = 32'h0; + assign _zz_224 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_225 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_226 = 1'b1; + assign _zz_227 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_228 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_229 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_230 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_231 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_232 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_233 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_234 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_235 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_236 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_237 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_238 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_239 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_240 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_241 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_242 = (1'b0 || (! 1'b1)); + assign _zz_243 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_244 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_245 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_246 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_247 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_248 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_249 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_250 = execute_INSTRUCTION[13 : 12]; + assign _zz_251 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_252 = (! memory_arbitration_isStuck); + assign _zz_253 = (iBus_cmd_valid || (_zz_184 != 3'b000)); + assign _zz_254 = (_zz_220 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_255 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_256 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_257 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_258 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_259 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_260 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_261 = execute_INSTRUCTION[13]; + assign _zz_262 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_263 = ($signed(_zz_264) + $signed(_zz_269)); + assign _zz_264 = ($signed(_zz_265) + $signed(_zz_267)); + assign _zz_265 = 52'h0; + assign _zz_266 = {1'b0,memory_MUL_LL}; + assign _zz_267 = {{19{_zz_266[32]}}, _zz_266}; + assign _zz_268 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_269 = {{2{_zz_268[49]}}, _zz_268}; + assign _zz_270 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_271 = {{2{_zz_270[49]}}, _zz_270}; + assign _zz_272 = ($signed(_zz_274) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_273 = _zz_272[31 : 0]; + assign _zz_274 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_275 = _zz_93[33 : 33]; + assign _zz_276 = _zz_93[32 : 32]; + assign _zz_277 = _zz_93[31 : 31]; + assign _zz_278 = _zz_93[30 : 30]; + assign _zz_279 = _zz_93[28 : 28]; + assign _zz_280 = _zz_93[25 : 25]; + assign _zz_281 = _zz_93[17 : 17]; + assign _zz_282 = _zz_93[16 : 16]; + assign _zz_283 = _zz_93[13 : 13]; + assign _zz_284 = _zz_93[12 : 12]; + assign _zz_285 = _zz_93[11 : 11]; + assign _zz_286 = _zz_93[15 : 15]; + assign _zz_287 = _zz_93[5 : 5]; + assign _zz_288 = _zz_93[3 : 3]; + assign _zz_289 = _zz_93[20 : 20]; + assign _zz_290 = _zz_93[10 : 10]; + assign _zz_291 = _zz_93[4 : 4]; + assign _zz_292 = _zz_93[0 : 0]; + assign _zz_293 = (_zz_61 - 4'b0001); + assign _zz_294 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_295 = {29'd0, _zz_294}; + assign _zz_296 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_297 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_298 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_299 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_300 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_301 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_302 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_303 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_304 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_305 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_306 = execute_SRC_LESS; + assign _zz_307 = 3'b100; + assign _zz_308 = execute_INSTRUCTION[19 : 15]; + assign _zz_309 = execute_INSTRUCTION[31 : 20]; + assign _zz_310 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_311 = ($signed(_zz_312) + $signed(_zz_315)); + assign _zz_312 = ($signed(_zz_313) + $signed(_zz_314)); + assign _zz_313 = execute_SRC1; + assign _zz_314 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_315 = (execute_SRC_USE_SUB_LESS ? _zz_316 : _zz_317); + assign _zz_316 = 32'h00000001; + assign _zz_317 = 32'h0; + assign _zz_318 = execute_INSTRUCTION[31 : 20]; + assign _zz_319 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_320 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_321 = {_zz_132,execute_INSTRUCTION[31 : 20]}; + assign _zz_322 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_323 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_324 = execute_INSTRUCTION[31 : 20]; + assign _zz_325 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_326 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_327 = 3'b100; + assign _zz_328 = (_zz_147 & (~ _zz_329)); + assign _zz_329 = (_zz_147 - 2'b01); + assign _zz_330 = (_zz_149 & (~ _zz_331)); + assign _zz_331 = (_zz_149 - 2'b01); + assign _zz_332 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_333 = execute_INSTRUCTION[31 : 24]; + assign _zz_334 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_335 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_336 = writeBack_MUL_LOW[31 : 0]; + assign _zz_337 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_338 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_339 = {5'd0, _zz_338}; + assign _zz_340 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_341 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_342 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_343 = {_zz_154,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_344 = _zz_345; + assign _zz_345 = _zz_346; + assign _zz_346 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_155) : _zz_155)} + _zz_348); + assign _zz_347 = memory_DivPlugin_div_needRevert; + assign _zz_348 = {32'd0, _zz_347}; + assign _zz_349 = _zz_157; + assign _zz_350 = {32'd0, _zz_349}; + assign _zz_351 = _zz_156; + assign _zz_352 = {31'd0, _zz_351}; + assign _zz_353 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_354 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_355 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_356 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_357 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_358 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_359 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_360 = (iBus_cmd_payload_address >>> 5); + assign _zz_361 = 1'b1; + assign _zz_362 = 1'b1; + assign _zz_363 = {_zz_65,_zz_64}; + assign _zz_364 = 32'h0000106f; + assign _zz_365 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_366 = 32'h00001073; + assign _zz_367 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_368 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_369 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_370) == 32'h00000003),{(_zz_371 == _zz_372),{_zz_373,{_zz_374,_zz_375}}}}}}; + assign _zz_370 = 32'h0000207f; + assign _zz_371 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_372 = 32'h00000003; + assign _zz_373 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_374 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_375 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_376) == 32'h00005013),{(_zz_377 == _zz_378),{_zz_379,{_zz_380,_zz_381}}}}}}; + assign _zz_376 = 32'hbc00707f; + assign _zz_377 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_378 = 32'h00001013; + assign _zz_379 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_380 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_381 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_382 = decode_INSTRUCTION[31]; + assign _zz_383 = decode_INSTRUCTION[31]; + assign _zz_384 = decode_INSTRUCTION[7]; + assign _zz_385 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_386 = 32'h02004020; + assign _zz_387 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_388 = (_zz_97 != 1'b0); + assign _zz_389 = (((decode_INSTRUCTION & _zz_391) == 32'h00000050) != 1'b0); + assign _zz_390 = {((_zz_392 == _zz_393) != 1'b0),{({_zz_394,_zz_395} != 2'b00),{(_zz_396 != _zz_397),{_zz_398,{_zz_399,_zz_400}}}}}; + assign _zz_391 = 32'h00203050; + assign _zz_392 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_393 = 32'h00000050; + assign _zz_394 = ((decode_INSTRUCTION & _zz_401) == 32'h00001050); + assign _zz_395 = ((decode_INSTRUCTION & _zz_402) == 32'h00002050); + assign _zz_396 = {_zz_96,(_zz_403 == _zz_404)}; + assign _zz_397 = 2'b00; + assign _zz_398 = ((_zz_405 == _zz_406) != 1'b0); + assign _zz_399 = ({_zz_407,_zz_408} != 2'b00); + assign _zz_400 = {(_zz_409 != _zz_410),{_zz_411,{_zz_412,_zz_413}}}; + assign _zz_401 = 32'h00001050; + assign _zz_402 = 32'h00002050; + assign _zz_403 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_404 = 32'h00000004; + assign _zz_405 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_406 = 32'h00000040; + assign _zz_407 = ((decode_INSTRUCTION & _zz_414) == 32'h00005010); + assign _zz_408 = ((decode_INSTRUCTION & _zz_415) == 32'h00005020); + assign _zz_409 = {(_zz_416 == _zz_417),{_zz_418,_zz_419}}; + assign _zz_410 = 3'b000; + assign _zz_411 = ((_zz_420 == _zz_421) != 1'b0); + assign _zz_412 = (_zz_422 != 1'b0); + assign _zz_413 = {(_zz_423 != _zz_424),{_zz_425,{_zz_426,_zz_427}}}; + assign _zz_414 = 32'h00007034; + assign _zz_415 = 32'h02007064; + assign _zz_416 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_417 = 32'h40001010; + assign _zz_418 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_419 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_420 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_421 = 32'h00000024; + assign _zz_422 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_423 = ((decode_INSTRUCTION & _zz_428) == 32'h00002000); + assign _zz_424 = 1'b0; + assign _zz_425 = ({_zz_429,_zz_430} != 2'b00); + assign _zz_426 = (_zz_431 != 1'b0); + assign _zz_427 = {(_zz_432 != _zz_433),{_zz_434,{_zz_435,_zz_436}}}; + assign _zz_428 = 32'h00003000; + assign _zz_429 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_430 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_431 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_432 = {_zz_97,{_zz_437,_zz_438}}; + assign _zz_433 = 3'b000; + assign _zz_434 = ({_zz_439,{_zz_440,_zz_441}} != 5'h0); + assign _zz_435 = (_zz_442 != 1'b0); + assign _zz_436 = {(_zz_443 != _zz_444),{_zz_445,{_zz_446,_zz_447}}}; + assign _zz_437 = ((decode_INSTRUCTION & _zz_448) == 32'h00000020); + assign _zz_438 = ((decode_INSTRUCTION & _zz_449) == 32'h00000020); + assign _zz_439 = ((decode_INSTRUCTION & _zz_450) == 32'h00002040); + assign _zz_440 = (_zz_451 == _zz_452); + assign _zz_441 = {_zz_453,{_zz_454,_zz_455}}; + assign _zz_442 = ((decode_INSTRUCTION & _zz_456) == 32'h00000020); + assign _zz_443 = {_zz_457,{_zz_458,_zz_459}}; + assign _zz_444 = 6'h0; + assign _zz_445 = ({_zz_460,_zz_461} != 5'h0); + assign _zz_446 = (_zz_462 != _zz_463); + assign _zz_447 = {_zz_464,{_zz_465,_zz_466}}; + assign _zz_448 = 32'h00000034; + assign _zz_449 = 32'h00000064; + assign _zz_450 = 32'h00002040; + assign _zz_451 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_452 = 32'h00001040; + assign _zz_453 = ((decode_INSTRUCTION & _zz_467) == 32'h00000040); + assign _zz_454 = (_zz_468 == _zz_469); + assign _zz_455 = (_zz_470 == _zz_471); + assign _zz_456 = 32'h00000020; + assign _zz_457 = ((decode_INSTRUCTION & _zz_472) == 32'h00000008); + assign _zz_458 = (_zz_473 == _zz_474); + assign _zz_459 = {_zz_95,{_zz_475,_zz_476}}; + assign _zz_460 = _zz_95; + assign _zz_461 = {_zz_477,{_zz_478,_zz_479}}; + assign _zz_462 = {_zz_96,{_zz_480,_zz_481}}; + assign _zz_463 = 6'h0; + assign _zz_464 = ({_zz_482,_zz_483} != 2'b00); + assign _zz_465 = (_zz_484 != _zz_485); + assign _zz_466 = {_zz_486,{_zz_487,_zz_488}}; + assign _zz_467 = 32'h00000050; + assign _zz_468 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_469 = 32'h00000040; + assign _zz_470 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_471 = 32'h0; + assign _zz_472 = 32'h00000008; + assign _zz_473 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_474 = 32'h00000040; + assign _zz_475 = (_zz_489 == _zz_490); + assign _zz_476 = {_zz_491,_zz_492}; + assign _zz_477 = ((decode_INSTRUCTION & _zz_493) == 32'h00002010); + assign _zz_478 = (_zz_494 == _zz_495); + assign _zz_479 = {_zz_496,_zz_497}; + assign _zz_480 = (_zz_498 == _zz_499); + assign _zz_481 = {_zz_500,{_zz_501,_zz_502}}; + assign _zz_482 = _zz_95; + assign _zz_483 = (_zz_503 == _zz_504); + assign _zz_484 = {_zz_95,_zz_505}; + assign _zz_485 = 2'b00; + assign _zz_486 = (_zz_506 != 1'b0); + assign _zz_487 = (_zz_507 != _zz_508); + assign _zz_488 = {_zz_509,{_zz_510,_zz_511}}; + assign _zz_489 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_490 = 32'h00004020; + assign _zz_491 = ((decode_INSTRUCTION & _zz_512) == 32'h00000010); + assign _zz_492 = ((decode_INSTRUCTION & _zz_513) == 32'h00000020); + assign _zz_493 = 32'h00002030; + assign _zz_494 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_495 = 32'h00000010; + assign _zz_496 = ((decode_INSTRUCTION & _zz_514) == 32'h00002020); + assign _zz_497 = ((decode_INSTRUCTION & _zz_515) == 32'h00000020); + assign _zz_498 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_499 = 32'h00001010; + assign _zz_500 = ((decode_INSTRUCTION & _zz_516) == 32'h00002010); + assign _zz_501 = (_zz_517 == _zz_518); + assign _zz_502 = {_zz_519,_zz_520}; + assign _zz_503 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_504 = 32'h00000020; + assign _zz_505 = ((decode_INSTRUCTION & _zz_521) == 32'h0); + assign _zz_506 = ((decode_INSTRUCTION & _zz_522) == 32'h00004010); + assign _zz_507 = (_zz_523 == _zz_524); + assign _zz_508 = 1'b0; + assign _zz_509 = ({_zz_525,_zz_526} != 4'b0000); + assign _zz_510 = (_zz_527 != _zz_528); + assign _zz_511 = {_zz_529,{_zz_530,_zz_531}}; + assign _zz_512 = 32'h00000030; + assign _zz_513 = 32'h02000020; + assign _zz_514 = 32'h02002060; + assign _zz_515 = 32'h02003020; + assign _zz_516 = 32'h00002010; + assign _zz_517 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_518 = 32'h00000010; + assign _zz_519 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_520 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_521 = 32'h00000020; + assign _zz_522 = 32'h00004014; + assign _zz_523 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_524 = 32'h00002010; + assign _zz_525 = ((decode_INSTRUCTION & _zz_532) == 32'h0); + assign _zz_526 = {(_zz_533 == _zz_534),{_zz_535,_zz_536}}; + assign _zz_527 = ((decode_INSTRUCTION & _zz_537) == 32'h0); + assign _zz_528 = 1'b0; + assign _zz_529 = ({_zz_538,{_zz_539,_zz_540}} != 3'b000); + assign _zz_530 = ({_zz_541,_zz_542} != 2'b00); + assign _zz_531 = {(_zz_543 != _zz_544),(_zz_545 != _zz_546)}; + assign _zz_532 = 32'h00000044; + assign _zz_533 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_534 = 32'h0; + assign _zz_535 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_536 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_537 = 32'h00000058; + assign _zz_538 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_539 = ((decode_INSTRUCTION & _zz_547) == 32'h00002010); + assign _zz_540 = ((decode_INSTRUCTION & _zz_548) == 32'h40000030); + assign _zz_541 = ((decode_INSTRUCTION & _zz_549) == 32'h00000004); + assign _zz_542 = _zz_94; + assign _zz_543 = {(_zz_550 == _zz_551),_zz_94}; + assign _zz_544 = 2'b00; + assign _zz_545 = ((decode_INSTRUCTION & _zz_552) == 32'h00001004); + assign _zz_546 = 1'b0; + assign _zz_547 = 32'h00002014; + assign _zz_548 = 32'h40000034; + assign _zz_549 = 32'h00000014; + assign _zz_550 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_551 = 32'h00000004; + assign _zz_552 = 32'h00005054; + assign _zz_553 = execute_INSTRUCTION[31]; + assign _zz_554 = execute_INSTRUCTION[31]; + assign _zz_555 = execute_INSTRUCTION[7]; + assign _zz_556 = 32'h0; always @ (posedge clk) begin - if(_zz_385) begin - _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_361) begin + _zz_221 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_386) begin - _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_362) begin + _zz_222 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1730,13 +1690,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_217 ), //i - .io_cpu_prefetch_isValid (_zz_218 ), //i + .io_flush (_zz_193 ), //i + .io_cpu_prefetch_isValid (_zz_194 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_219 ), //i - .io_cpu_fetch_isStuck (_zz_220 ), //i - .io_cpu_fetch_isRemoved (_zz_221 ), //i + .io_cpu_fetch_isValid (_zz_195 ), //i + .io_cpu_fetch_isStuck (_zz_196 ), //i + .io_cpu_fetch_isRemoved (_zz_197 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1749,8 +1709,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_222 ), //i - .io_cpu_decode_isStuck (_zz_223 ), //i + .io_cpu_decode_isValid (_zz_198 ), //i + .io_cpu_decode_isStuck (_zz_199 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1758,8 +1718,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_224 ), //i - .io_cpu_fill_valid (_zz_225 ), //i + .io_cpu_decode_isUser (_zz_200 ), //i + .io_cpu_fill_valid (_zz_201 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1772,20 +1732,20 @@ module VexRiscv ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_226 ), //i - .io_cpu_execute_address (_zz_227[31:0] ), //i + .io_cpu_execute_isValid (_zz_202 ), //i + .io_cpu_execute_address (_zz_203[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_88[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_228 ), //i + .io_cpu_memory_isValid (_zz_204 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_229[31:0] ), //i + .io_cpu_memory_address (_zz_205[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_230 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_206 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1793,31 +1753,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_231 ), //i + .io_cpu_writeBack_isValid (_zz_207 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_232 ), //i + .io_cpu_writeBack_isUser (_zz_208 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_233[31:0] ), //i + .io_cpu_writeBack_address (_zz_209[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_234 ), //i - .io_cpu_writeBack_fence_SR (_zz_235 ), //i - .io_cpu_writeBack_fence_SO (_zz_236 ), //i - .io_cpu_writeBack_fence_SI (_zz_237 ), //i - .io_cpu_writeBack_fence_PW (_zz_238 ), //i - .io_cpu_writeBack_fence_PR (_zz_239 ), //i - .io_cpu_writeBack_fence_PO (_zz_240 ), //i - .io_cpu_writeBack_fence_PI (_zz_241 ), //i - .io_cpu_writeBack_fence_FM (_zz_242[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_210 ), //i + .io_cpu_writeBack_fence_SR (_zz_211 ), //i + .io_cpu_writeBack_fence_SO (_zz_212 ), //i + .io_cpu_writeBack_fence_SI (_zz_213 ), //i + .io_cpu_writeBack_fence_PW (_zz_214 ), //i + .io_cpu_writeBack_fence_PR (_zz_215 ), //i + .io_cpu_writeBack_fence_PO (_zz_216 ), //i + .io_cpu_writeBack_fence_PI (_zz_217 ), //i + .io_cpu_writeBack_fence_FM (_zz_218[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_243 ), //i + .io_cpu_flush_valid (_zz_219 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_244 ), //i + .io_mem_cmd_ready (_zz_220 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1833,18 +1793,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_387) + case(_zz_363) 2'b00 : begin - _zz_247 = DBusCachedPlugin_redoBranch_payload; + _zz_223 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_247 = CsrPlugin_jumpInterface_payload; + _zz_223 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_247 = BranchPlugin_jumpInterface_payload; + _zz_223 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_247 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_223 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2599,7 +2559,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); + assign memory_MUL_LOW = ($signed(_zz_263) + $signed(_zz_271)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2607,41 +2567,41 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_297; + assign execute_SHIFT_RIGHT = _zz_273; assign execute_REGFILE_WRITE_DATA = _zz_108; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_227[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_203[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_299[0]; - assign decode_IS_RS1_SIGNED = _zz_300[0]; - assign decode_IS_DIV = _zz_301[0]; + assign decode_IS_RS2_SIGNED = _zz_275[0]; + assign decode_IS_RS1_SIGNED = _zz_276[0]; + assign decode_IS_DIV = _zz_277[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_302[0]; + assign decode_IS_MUL = _zz_278[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_279[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_304[0]; + assign decode_IS_CSR = _zz_280[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; - assign decode_MEMORY_MANAGMENT = _zz_306[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_281[0]; + assign decode_MEMORY_MANAGMENT = _zz_282[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_307[0]; + assign decode_MEMORY_WR = _zz_283[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_284[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_285[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2694,11 +2654,11 @@ module VexRiscv ( assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_COND_RESULT = _zz_130; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_310[0]; - assign decode_RS1_USE = _zz_311[0]; + assign decode_RS2_USE = _zz_286[0]; + assign decode_RS1_USE = _zz_287[0]; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_248)begin + if(_zz_224)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2716,21 +2676,21 @@ module VexRiscv ( decode_RS2 = _zz_121; end end - if(_zz_249)begin - if(_zz_250)begin + if(_zz_225)begin + if(_zz_226)begin if(_zz_123)begin decode_RS2 = _zz_57; end end end - if(_zz_251)begin + if(_zz_227)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_125)begin decode_RS2 = _zz_38; end end end - if(_zz_252)begin + if(_zz_228)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_127)begin decode_RS2 = _zz_37; @@ -2746,21 +2706,21 @@ module VexRiscv ( decode_RS1 = _zz_121; end end - if(_zz_249)begin - if(_zz_250)begin + if(_zz_225)begin + if(_zz_226)begin if(_zz_122)begin decode_RS1 = _zz_57; end end end - if(_zz_251)begin + if(_zz_227)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_124)begin decode_RS1 = _zz_38; end end end - if(_zz_252)begin + if(_zz_228)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_126)begin decode_RS1 = _zz_37; @@ -2787,7 +2747,7 @@ module VexRiscv ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_253)begin + if(_zz_229)begin _zz_38 = memory_DivPlugin_div_result; end end @@ -2800,8 +2760,8 @@ module VexRiscv ( assign _zz_41 = execute_PC; assign execute_SRC2_CTRL = _zz_42; assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_312[0]; - assign decode_SRC_ADD_ZERO = _zz_313[0]; + assign decode_SRC_USE_SUB_LESS = _zz_288[0]; + assign decode_SRC_ADD_ZERO = _zz_289[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_44; @@ -2819,25 +2779,25 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_314[0]; + decode_REGFILE_WRITE_VALID = _zz_290[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_364) == 32'h00000003),{(_zz_365 == _zz_366),{_zz_367,{_zz_368,_zz_369}}}}}}} != 22'h0); always @ (*) begin _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_286) + case(_zz_262) 2'b00 : begin - _zz_57 = _zz_360; + _zz_57 = _zz_336; end default : begin - _zz_57 = _zz_361; + _zz_57 = _zz_337; end endcase end @@ -2856,32 +2816,32 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_315[0]; - assign decode_FLUSH_ALL = _zz_316[0]; + assign decode_MEMORY_ENABLE = _zz_291[0]; + assign decode_FLUSH_ALL = _zz_292[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_254)begin + if(_zz_230)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_255)begin + if(_zz_231)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_256)begin + if(_zz_232)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_257)begin + if(_zz_233)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2927,7 +2887,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_258)begin + if(_zz_234)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2941,22 +2901,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_258)begin + if(_zz_234)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_243 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_219 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_259)begin + if(_zz_235)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_248)begin + if(_zz_224)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2975,7 +2935,7 @@ module VexRiscv ( always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_260)begin + if(_zz_236)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -2989,7 +2949,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_260)begin + if(_zz_236)begin execute_arbitration_flushNext = 1'b1; end end @@ -3001,7 +2961,7 @@ module VexRiscv ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_253)begin + if(_zz_229)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3060,10 +3020,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(_zz_237)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_262)begin + if(_zz_238)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3077,10 +3037,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_261)begin + if(_zz_237)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_262)begin + if(_zz_238)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3094,7 +3054,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_259)begin + if(_zz_235)begin CsrPlugin_inWfi = 1'b1; end end @@ -3102,21 +3062,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_261)begin + if(_zz_237)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_262)begin + if(_zz_238)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_261)begin + if(_zz_237)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_262)begin - case(_zz_263) + if(_zz_238)begin + case(_zz_239) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3132,11 +3092,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_62 = (_zz_61 & (~ _zz_317)); + assign _zz_62 = (_zz_61 & (~ _zz_293)); assign _zz_63 = _zz_62[3]; assign _zz_64 = (_zz_62[1] || _zz_63); assign _zz_65 = (_zz_62[2] || _zz_63); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_223; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3156,7 +3116,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_319); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_295); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3247,7 +3207,7 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_75 = _zz_320[11]; + assign _zz_75 = _zz_296[11]; always @ (*) begin _zz_76[18] = _zz_75; _zz_76[17] = _zz_75; @@ -3271,13 +3231,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_321[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_297[31])); if(_zz_81)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_77 = _zz_322[19]; + assign _zz_77 = _zz_298[19]; always @ (*) begin _zz_78[10] = _zz_77; _zz_78[9] = _zz_77; @@ -3292,7 +3252,7 @@ module VexRiscv ( _zz_78[0] = _zz_77; end - assign _zz_79 = _zz_323[11]; + assign _zz_79 = _zz_299[11]; always @ (*) begin _zz_80[18] = _zz_79; _zz_80[17] = _zz_79; @@ -3318,16 +3278,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_81 = _zz_324[1]; + _zz_81 = _zz_300[1]; end default : begin - _zz_81 = _zz_325[1]; + _zz_81 = _zz_301[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_82 = _zz_326[19]; + assign _zz_82 = _zz_302[19]; always @ (*) begin _zz_83[10] = _zz_82; _zz_83[9] = _zz_82; @@ -3342,7 +3302,7 @@ module VexRiscv ( _zz_83[0] = _zz_82; end - assign _zz_84 = _zz_327[11]; + assign _zz_84 = _zz_303[11]; always @ (*) begin _zz_85[18] = _zz_84; _zz_85[17] = _zz_84; @@ -3365,7 +3325,7 @@ module VexRiscv ( _zz_85[0] = _zz_84; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_406,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_407,_zz_408},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_382,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_383,_zz_384},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3374,52 +3334,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_219; + assign _zz_194 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_195 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_196 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_195; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_224 = (CsrPlugin_privilege == 2'b00); + assign _zz_198 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_199 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_200 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_257)begin + if(_zz_233)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_255)begin + if(_zz_231)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_225 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_255)begin - _zz_225 = 1'b1; + _zz_201 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_231)begin + _zz_201 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_256)begin + if(_zz_232)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_254)begin + if(_zz_230)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_256)begin + if(_zz_232)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_254)begin + if(_zz_230)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3429,9 +3389,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_217 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_193 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_244 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_220 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3458,8 +3418,8 @@ module VexRiscv ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_227 = execute_SRC_ADD; + assign _zz_202 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_203 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3474,27 +3434,27 @@ module VexRiscv ( endcase end - assign _zz_243 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_228 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_229 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_228; + assign _zz_219 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_204 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_205 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_204; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_229; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_205; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_230 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_206 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_230 = 1'b1; + _zz_206 = 1'b1; end end - assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_232 = (CsrPlugin_privilege == 2'b00); - assign _zz_233 = writeBack_REGFILE_WRITE_DATA; + assign _zz_207 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_208 = (CsrPlugin_privilege == 2'b00); + assign _zz_209 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_264)begin + if(_zz_240)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3504,7 +3464,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_264)begin + if(_zz_240)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3523,15 +3483,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_264)begin + if(_zz_240)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_304}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_305}; end end end @@ -3604,7 +3564,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_284) + case(_zz_260) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_90; end @@ -3640,7 +3600,7 @@ module VexRiscv ( assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_409 == _zz_410) != 1'b0),{(_zz_411 != 1'b0),{1'b0,{_zz_412,{_zz_413,_zz_414}}}}}}}; + assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_385 == _zz_386) != 1'b0),{(_zz_387 != 1'b0),{1'b0,{_zz_388,{_zz_389,_zz_390}}}}}}}; assign _zz_99 = _zz_93[2 : 1]; assign _zz_56 = _zz_99; assign _zz_100 = _zz_93[7 : 6]; @@ -3662,8 +3622,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_245; - assign decode_RegFilePlugin_rs2Data = _zz_246; + assign decode_RegFilePlugin_rs1Data = _zz_221; + assign decode_RegFilePlugin_rs2Data = _zz_222; always @ (*) begin lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); if(_zz_107)begin @@ -3705,7 +3665,7 @@ module VexRiscv ( _zz_108 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_108 = {31'd0, _zz_330}; + _zz_108 = {31'd0, _zz_306}; end default : begin _zz_108 = execute_SRC_ADD_SUB; @@ -3719,18 +3679,18 @@ module VexRiscv ( _zz_109 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_109 = {29'd0, _zz_331}; + _zz_109 = {29'd0, _zz_307}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_109 = {27'd0, _zz_332}; + _zz_109 = {27'd0, _zz_308}; end endcase end - assign _zz_110 = _zz_333[11]; + assign _zz_110 = _zz_309[11]; always @ (*) begin _zz_111[19] = _zz_110; _zz_111[18] = _zz_110; @@ -3754,7 +3714,7 @@ module VexRiscv ( _zz_111[0] = _zz_110; end - assign _zz_112 = _zz_334[11]; + assign _zz_112 = _zz_310[11]; always @ (*) begin _zz_113[19] = _zz_112; _zz_113[18] = _zz_112; @@ -3796,7 +3756,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_335; + execute_SrcPlugin_addSub = _zz_311; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3877,22 +3837,22 @@ module VexRiscv ( always @ (*) begin _zz_117 = 1'b0; - if(_zz_265)begin - if(_zz_266)begin + if(_zz_241)begin + if(_zz_242)begin if(_zz_122)begin _zz_117 = 1'b1; end end end - if(_zz_267)begin - if(_zz_268)begin + if(_zz_243)begin + if(_zz_244)begin if(_zz_124)begin _zz_117 = 1'b1; end end end - if(_zz_269)begin - if(_zz_270)begin + if(_zz_245)begin + if(_zz_246)begin if(_zz_126)begin _zz_117 = 1'b1; end @@ -3905,22 +3865,22 @@ module VexRiscv ( always @ (*) begin _zz_118 = 1'b0; - if(_zz_265)begin - if(_zz_266)begin + if(_zz_241)begin + if(_zz_242)begin if(_zz_123)begin _zz_118 = 1'b1; end end end - if(_zz_267)begin - if(_zz_268)begin + if(_zz_243)begin + if(_zz_244)begin if(_zz_125)begin _zz_118 = 1'b1; end end end - if(_zz_269)begin - if(_zz_270)begin + if(_zz_245)begin + if(_zz_246)begin if(_zz_127)begin _zz_118 = 1'b1; end @@ -3968,7 +3928,7 @@ module VexRiscv ( endcase end - assign _zz_131 = _zz_342[11]; + assign _zz_131 = _zz_318[11]; always @ (*) begin _zz_132[19] = _zz_131; _zz_132[18] = _zz_131; @@ -3992,7 +3952,7 @@ module VexRiscv ( _zz_132[0] = _zz_131; end - assign _zz_133 = _zz_343[19]; + assign _zz_133 = _zz_319[19]; always @ (*) begin _zz_134[10] = _zz_133; _zz_134[9] = _zz_133; @@ -4007,7 +3967,7 @@ module VexRiscv ( _zz_134[0] = _zz_133; end - assign _zz_135 = _zz_344[11]; + assign _zz_135 = _zz_320[11]; always @ (*) begin _zz_136[18] = _zz_135; _zz_136[17] = _zz_135; @@ -4033,13 +3993,13 @@ module VexRiscv ( always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_137 = (_zz_345[1] ^ execute_RS1[1]); + _zz_137 = (_zz_321[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_137 = _zz_346[1]; + _zz_137 = _zz_322[1]; end default : begin - _zz_137 = _zz_347[1]; + _zz_137 = _zz_323[1]; end endcase end @@ -4056,7 +4016,7 @@ module VexRiscv ( endcase end - assign _zz_138 = _zz_348[11]; + assign _zz_138 = _zz_324[11]; always @ (*) begin _zz_139[19] = _zz_138; _zz_139[18] = _zz_138; @@ -4086,15 +4046,15 @@ module VexRiscv ( execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_577,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_578,_zz_579},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_553,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_554,_zz_555},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_351}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_327}; end end endcase end - assign _zz_140 = _zz_349[19]; + assign _zz_140 = _zz_325[19]; always @ (*) begin _zz_141[10] = _zz_140; _zz_141[9] = _zz_140; @@ -4109,7 +4069,7 @@ module VexRiscv ( _zz_141[0] = _zz_140; end - assign _zz_142 = _zz_350[11]; + assign _zz_142 = _zz_326[11]; always @ (*) begin _zz_143[18] = _zz_142; _zz_143[17] = _zz_142; @@ -4158,12 +4118,12 @@ module VexRiscv ( assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_148 = _zz_352[0]; + assign _zz_148 = _zz_328[0]; assign _zz_149 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_150 = _zz_354[0]; + assign _zz_150 = _zz_330[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_258)begin + if(_zz_234)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4173,7 +4133,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_260)begin + if(_zz_236)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -4342,70 +4302,6 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2822)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2824)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2826)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2828)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2830)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2832)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2834)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end if(execute_CsrPlugin_csr_3008)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4414,7 +4310,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_271)begin + if(_zz_247)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4433,20 +4329,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_272)begin + if(_zz_248)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_273)begin + if(_zz_249)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_272)begin + if(_zz_248)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_273)begin + if(_zz_249)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4461,14 +4357,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_271)begin + if(_zz_247)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_271)begin + if(_zz_247)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4477,7 +4373,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_285) + case(_zz_261) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4490,49 +4386,49 @@ module VexRiscv ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_356; + assign execute_CfuPlugin_functionsIds_0 = _zz_332; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_167 = _zz_357[7]; - always @ (*) begin - _zz_168[23] = _zz_167; - _zz_168[22] = _zz_167; - _zz_168[21] = _zz_167; - _zz_168[20] = _zz_167; - _zz_168[19] = _zz_167; - _zz_168[18] = _zz_167; - _zz_168[17] = _zz_167; - _zz_168[16] = _zz_167; - _zz_168[15] = _zz_167; - _zz_168[14] = _zz_167; - _zz_168[13] = _zz_167; - _zz_168[12] = _zz_167; - _zz_168[11] = _zz_167; - _zz_168[10] = _zz_167; - _zz_168[9] = _zz_167; - _zz_168[8] = _zz_167; - _zz_168[7] = _zz_167; - _zz_168[6] = _zz_167; - _zz_168[5] = _zz_167; - _zz_168[4] = _zz_167; - _zz_168[3] = _zz_167; - _zz_168[2] = _zz_167; - _zz_168[1] = _zz_167; - _zz_168[0] = _zz_167; + assign _zz_151 = _zz_333[7]; + always @ (*) begin + _zz_152[23] = _zz_151; + _zz_152[22] = _zz_151; + _zz_152[21] = _zz_151; + _zz_152[20] = _zz_151; + _zz_152[19] = _zz_151; + _zz_152[18] = _zz_151; + _zz_152[17] = _zz_151; + _zz_152[16] = _zz_151; + _zz_152[15] = _zz_151; + _zz_152[14] = _zz_151; + _zz_152[13] = _zz_151; + _zz_152[12] = _zz_151; + _zz_152[11] = _zz_151; + _zz_152[10] = _zz_151; + _zz_152[9] = _zz_151; + _zz_152[8] = _zz_151; + _zz_152[7] = _zz_151; + _zz_152[6] = _zz_151; + _zz_152[5] = _zz_151; + _zz_152[4] = _zz_151; + _zz_152[3] = _zz_151; + _zz_152[2] = _zz_151; + _zz_152[1] = _zz_151; + _zz_152[0] = _zz_151; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_169 = execute_RS2; + _zz_153 = execute_RS2; end default : begin - _zz_169 = {_zz_168,execute_INSTRUCTION[31 : 24]}; + _zz_153 = {_zz_152,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_169; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_153; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4558,7 +4454,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_274) + case(_zz_250) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4572,7 +4468,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_274) + case(_zz_250) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4591,12 +4487,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_358) + $signed(_zz_359)); + assign writeBack_MulPlugin_result = ($signed(_zz_334) + $signed(_zz_335)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_253)begin - if(_zz_275)begin + if(_zz_229)begin + if(_zz_251)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4604,7 +4500,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_276)begin + if(_zz_252)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4615,28 +4511,28 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_363); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_339); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_170 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_170[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_364); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_365 : _zz_366); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_367[31:0]; - assign _zz_171 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_172 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_173 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_154 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_154[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_340); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_341 : _zz_342); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_343[31:0]; + assign _zz_155 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_156 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_157 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_174[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_174[31 : 0] = execute_RS1; + _zz_158[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_158[31 : 0] = execute_RS1; end - assign _zz_176 = (_zz_175 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_176 != 32'h0); + assign _zz_160 = (_zz_159 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_160 != 32'h0); assign _zz_29 = decode_SRC1_CTRL; assign _zz_27 = _zz_56; assign _zz_43 = decode_to_execute_SRC1_CTRL; @@ -4688,272 +4584,216 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_177 = 32'h0; + _zz_161 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_177[12 : 0] = 13'h1000; - _zz_177[25 : 20] = 6'h20; + _zz_161[12 : 0] = 13'h1000; + _zz_161[25 : 20] = 6'h20; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_162 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_178[3 : 0] = 4'b1011; + _zz_162[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_163 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_179[4 : 0] = 5'h16; + _zz_163[4 : 0] = 5'h16; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_164 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_180[5 : 0] = 6'h21; + _zz_164[5 : 0] = 6'h21; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_165 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_181[31 : 30] = CsrPlugin_misa_base; - _zz_181[25 : 0] = CsrPlugin_misa_extensions; + _zz_165[31 : 30] = CsrPlugin_misa_base; + _zz_165[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_166 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_182[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_182[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_182[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_166[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_166[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_166[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_167 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_183[11 : 11] = CsrPlugin_mip_MEIP; - _zz_183[7 : 7] = CsrPlugin_mip_MTIP; - _zz_183[3 : 3] = CsrPlugin_mip_MSIP; + _zz_167[11 : 11] = CsrPlugin_mip_MEIP; + _zz_167[7 : 7] = CsrPlugin_mip_MTIP; + _zz_167[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_168 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_184[11 : 11] = CsrPlugin_mie_MEIE; - _zz_184[7 : 7] = CsrPlugin_mie_MTIE; - _zz_184[3 : 3] = CsrPlugin_mie_MSIE; + _zz_168[11 : 11] = CsrPlugin_mie_MEIE; + _zz_168[7 : 7] = CsrPlugin_mie_MTIE; + _zz_168[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_169 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_185[31 : 2] = CsrPlugin_mtvec_base; - _zz_185[1 : 0] = CsrPlugin_mtvec_mode; + _zz_169[31 : 2] = CsrPlugin_mtvec_base; + _zz_169[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_170 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_186[31 : 0] = CsrPlugin_mepc; + _zz_170[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_171 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_187[31 : 0] = CsrPlugin_mscratch; + _zz_171[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_188[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_188[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_172[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_172[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_189[31 : 0] = CsrPlugin_mtval; + _zz_173[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_174[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_175[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_176[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_177[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_178[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_179[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_180[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; - end - end - - always @ (*) begin - _zz_198 = 32'h0; - if(execute_CsrPlugin_csr_2820)begin - _zz_198[31 : 0] = _zz_151; - end - end - - always @ (*) begin - _zz_199 = 32'h0; - if(execute_CsrPlugin_csr_2822)begin - _zz_199[31 : 0] = _zz_153; - end - end - - always @ (*) begin - _zz_200 = 32'h0; - if(execute_CsrPlugin_csr_2824)begin - _zz_200[31 : 0] = _zz_155; - end - end - - always @ (*) begin - _zz_201 = 32'h0; - if(execute_CsrPlugin_csr_2826)begin - _zz_201[31 : 0] = _zz_157; - end - end - - always @ (*) begin - _zz_202 = 32'h0; - if(execute_CsrPlugin_csr_2828)begin - _zz_202[31 : 0] = _zz_159; - end - end - - always @ (*) begin - _zz_203 = 32'h0; - if(execute_CsrPlugin_csr_2830)begin - _zz_203[31 : 0] = _zz_161; - end - end - - always @ (*) begin - _zz_204 = 32'h0; - if(execute_CsrPlugin_csr_2832)begin - _zz_204[31 : 0] = _zz_163; - end - end - - always @ (*) begin - _zz_205 = 32'h0; - if(execute_CsrPlugin_csr_2834)begin - _zz_205[31 : 0] = _zz_165; + _zz_181[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_206 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_206[31 : 0] = _zz_175; + _zz_182[31 : 0] = _zz_159; end end always @ (*) begin - _zz_207 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_207[31 : 0] = _zz_176; + _zz_183[31 : 0] = _zz_160; end end - assign execute_CsrPlugin_readData = (((((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_580 | _zz_181) | (_zz_182 | _zz_183))) | (((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191)))) | ((((_zz_192 | _zz_193) | (_zz_194 | _zz_195)) | ((_zz_196 | _zz_197) | (_zz_198 | _zz_199))) | (((_zz_200 | _zz_201) | (_zz_202 | _zz_203)) | ((_zz_204 | _zz_205) | (_zz_206 | _zz_207))))); - assign iBusWishbone_ADR = {_zz_384,_zz_208}; - assign iBusWishbone_CTI = ((_zz_208 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_161 | _zz_162) | (_zz_163 | _zz_164)) | ((_zz_556 | _zz_165) | (_zz_166 | _zz_167))) | (((_zz_168 | _zz_169) | (_zz_170 | _zz_171)) | ((_zz_172 | _zz_173) | (_zz_174 | _zz_175)))) | (((_zz_176 | _zz_177) | (_zz_178 | _zz_179)) | ((_zz_180 | _zz_181) | (_zz_182 | _zz_183)))); + assign iBusWishbone_ADR = {_zz_360,_zz_184}; + assign iBusWishbone_CTI = ((_zz_184 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_277)begin + if(_zz_253)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_277)begin + if(_zz_253)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_209; + assign iBus_rsp_valid = _zz_185; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_215 = (dBus_cmd_payload_length != 3'b000); - assign _zz_211 = dBus_cmd_valid; - assign _zz_213 = dBus_cmd_payload_wr; - assign _zz_214 = (_zz_210 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_212 && (_zz_213 || _zz_214)); - assign dBusWishbone_ADR = ((_zz_215 ? {{dBus_cmd_payload_address[31 : 5],_zz_210},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_215 ? (_zz_214 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_191 = (dBus_cmd_payload_length != 3'b000); + assign _zz_187 = dBus_cmd_valid; + assign _zz_189 = dBus_cmd_payload_wr; + assign _zz_190 = (_zz_186 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_188 && (_zz_189 || _zz_190)); + assign dBusWishbone_ADR = ((_zz_191 ? {{dBus_cmd_payload_address[31 : 5],_zz_186},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_191 ? (_zz_190 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_213 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_213; + assign dBusWishbone_SEL = (_zz_189 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_189; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_212 = (_zz_211 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_211; - assign dBusWishbone_STB = _zz_211; - assign dBus_rsp_valid = _zz_216; + assign _zz_188 = (_zz_187 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_187; + assign dBusWishbone_STB = _zz_187; + assign dBus_rsp_valid = _zz_192; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5000,15 +4840,15 @@ module VexRiscv ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_175 <= 32'h0; + _zz_159 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_208 <= 3'b000; - _zz_209 <= 1'b0; - _zz_210 <= 3'b000; - _zz_216 <= 1'b0; + _zz_184 <= 3'b000; + _zz_185 <= 1'b0; + _zz_186 <= 3'b000; + _zz_192 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5089,7 +4929,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_278)begin + if(_zz_254)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5121,14 +4961,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_279)begin - if(_zz_280)begin + if(_zz_255)begin + if(_zz_256)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_281)begin + if(_zz_257)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_282)begin + if(_zz_258)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5153,7 +4993,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_261)begin + if(_zz_237)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5164,8 +5004,8 @@ module VexRiscv ( end endcase end - if(_zz_262)begin - case(_zz_263) + if(_zz_238)begin + case(_zz_239) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5191,7 +5031,7 @@ module VexRiscv ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_283)begin + if(_zz_259)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; @@ -5225,35 +5065,35 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_377[0]; - CsrPlugin_mstatus_MIE <= _zz_378[0]; + CsrPlugin_mstatus_MPIE <= _zz_353[0]; + CsrPlugin_mstatus_MIE <= _zz_354[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_380[0]; - CsrPlugin_mie_MTIE <= _zz_381[0]; - CsrPlugin_mie_MSIE <= _zz_382[0]; + CsrPlugin_mie_MEIE <= _zz_356[0]; + CsrPlugin_mie_MTIE <= _zz_357[0]; + CsrPlugin_mie_MSIE <= _zz_358[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_175 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_277)begin + if(_zz_253)begin if(iBusWishbone_ACK)begin - _zz_208 <= (_zz_208 + 3'b001); + _zz_184 <= (_zz_184 + 3'b001); end end - _zz_209 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_211 && _zz_212))begin - _zz_210 <= (_zz_210 + 3'b001); - if(_zz_214)begin - _zz_210 <= 3'b000; + _zz_185 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_187 && _zz_188))begin + _zz_186 <= (_zz_186 + 3'b001); + if(_zz_190)begin + _zz_186 <= 3'b000; end end - _zz_216 <= ((_zz_211 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_192 <= ((_zz_187 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5267,7 +5107,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_278)begin + if(_zz_254)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5294,11 +5134,11 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_258)begin + if(_zz_234)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(_zz_260)begin + if(_zz_236)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end @@ -5310,21 +5150,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_279)begin - if(_zz_280)begin + if(_zz_255)begin + if(_zz_256)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_281)begin + if(_zz_257)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_282)begin + if(_zz_258)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_261)begin + if(_zz_237)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5338,31 +5178,7 @@ module VexRiscv ( end endcase end - if(_zz_152[0])begin - _zz_151 <= (_zz_151 + 32'h00000001); - end - if(_zz_154[0])begin - _zz_153 <= (_zz_153 + 32'h00000001); - end - if(_zz_156[0])begin - _zz_155 <= (_zz_155 + 32'h00000001); - end - if(_zz_158[0])begin - _zz_157 <= (_zz_157 + 32'h00000001); - end - if(_zz_160[0])begin - _zz_159 <= (_zz_159 + 32'h00000001); - end - if(_zz_162[0])begin - _zz_161 <= (_zz_161 + 32'h00000001); - end - if(_zz_164[0])begin - _zz_163 <= (_zz_163 + 32'h00000001); - end - if(_zz_166[0])begin - _zz_165 <= (_zz_165 + 32'h00000001); - end - if(_zz_283)begin + if(_zz_259)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5372,20 +5188,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_253)begin - if(_zz_275)begin + if(_zz_229)begin + if(_zz_251)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_368[31:0]; + memory_DivPlugin_div_result <= _zz_344[31:0]; end end end - if(_zz_276)begin + if(_zz_252)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_173 ? (~ _zz_174) : _zz_174) + _zz_374); - memory_DivPlugin_rs2 <= ((_zz_172 ? (~ execute_RS2) : execute_RS2) + _zz_376); - memory_DivPlugin_div_needRevert <= ((_zz_173 ^ (_zz_172 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_157 ? (~ _zz_158) : _zz_158) + _zz_350); + memory_DivPlugin_rs2 <= ((_zz_156 ? (~ execute_RS2) : execute_RS2) + _zz_352); + memory_DivPlugin_div_needRevert <= ((_zz_157 ^ (_zz_156 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5643,54 +5459,6 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); - end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end @@ -5699,7 +5467,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_379[0]; + CsrPlugin_mip_MSIP <= _zz_355[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5720,7 +5488,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_383[0]; + CsrPlugin_mcause_interrupt <= _zz_359[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5749,86 +5517,6 @@ module VexRiscv ( CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end end - if(execute_CsrPlugin_csr_2820)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2822)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2824)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2826)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2828)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2830)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2832)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2834)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; - end - end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index f54d4b8..8310b54 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 +// Git hash : 9c3529c14328ee22a18ec0f74e66ca59de7346c3 `define Input2Kind_defaultEncoding_type [0:0] @@ -95,37 +95,37 @@ module VexRiscv ( input reset, input debugReset ); + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + wire _zz_201; + wire _zz_202; + wire _zz_203; + reg _zz_204; + wire _zz_205; + wire [31:0] _zz_206; + wire _zz_207; + wire [31:0] _zz_208; + reg _zz_209; + wire _zz_210; + wire _zz_211; + wire [31:0] _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + wire _zz_219; wire _zz_220; - wire _zz_221; + wire [3:0] _zz_221; wire _zz_222; wire _zz_223; - wire _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - reg _zz_228; - wire _zz_229; - wire [31:0] _zz_230; - wire _zz_231; - wire [31:0] _zz_232; - reg _zz_233; - wire _zz_234; - wire _zz_235; - wire [31:0] _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire [3:0] _zz_245; - wire _zz_246; - wire _zz_247; - reg [31:0] _zz_248; - reg [31:0] _zz_249; - reg [31:0] _zz_250; + reg [31:0] _zz_224; + reg [31:0] _zz_225; + reg [31:0] _zz_226; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -158,15 +158,39 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_227; + wire _zz_228; + wire _zz_229; + wire _zz_230; + wire _zz_231; + wire _zz_232; + wire _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire [1:0] _zz_245; + wire _zz_246; + wire _zz_247; + wire _zz_248; + wire _zz_249; + wire _zz_250; wire _zz_251; wire _zz_252; wire _zz_253; wire _zz_254; wire _zz_255; - wire _zz_256; + wire [1:0] _zz_256; wire _zz_257; wire _zz_258; - wire _zz_259; + wire [5:0] _zz_259; wire _zz_260; wire _zz_261; wire _zz_262; @@ -174,337 +198,313 @@ module VexRiscv ( wire _zz_264; wire _zz_265; wire _zz_266; - wire _zz_267; + wire [1:0] _zz_267; wire _zz_268; wire [1:0] _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire _zz_279; - wire [1:0] _zz_280; - wire _zz_281; - wire _zz_282; - wire [5:0] _zz_283; - wire _zz_284; - wire _zz_285; - wire _zz_286; - wire _zz_287; - wire _zz_288; - wire _zz_289; - wire _zz_290; - wire [1:0] _zz_291; - wire _zz_292; - wire [1:0] _zz_293; - wire [51:0] _zz_294; - wire [51:0] _zz_295; - wire [51:0] _zz_296; - wire [32:0] _zz_297; - wire [51:0] _zz_298; - wire [49:0] _zz_299; - wire [51:0] _zz_300; - wire [49:0] _zz_301; - wire [51:0] _zz_302; - wire [32:0] _zz_303; - wire [31:0] _zz_304; - wire [32:0] _zz_305; - wire [0:0] _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire [0:0] _zz_312; - wire [0:0] _zz_313; + wire [51:0] _zz_270; + wire [51:0] _zz_271; + wire [51:0] _zz_272; + wire [32:0] _zz_273; + wire [51:0] _zz_274; + wire [49:0] _zz_275; + wire [51:0] _zz_276; + wire [49:0] _zz_277; + wire [51:0] _zz_278; + wire [32:0] _zz_279; + wire [31:0] _zz_280; + wire [32:0] _zz_281; + wire [0:0] _zz_282; + wire [0:0] _zz_283; + wire [0:0] _zz_284; + wire [0:0] _zz_285; + wire [0:0] _zz_286; + wire [0:0] _zz_287; + wire [0:0] _zz_288; + wire [0:0] _zz_289; + wire [0:0] _zz_290; + wire [0:0] _zz_291; + wire [0:0] _zz_292; + wire [0:0] _zz_293; + wire [0:0] _zz_294; + wire [0:0] _zz_295; + wire [0:0] _zz_296; + wire [0:0] _zz_297; + wire [0:0] _zz_298; + wire [0:0] _zz_299; + wire [0:0] _zz_300; + wire [3:0] _zz_301; + wire [2:0] _zz_302; + wire [31:0] _zz_303; + wire [11:0] _zz_304; + wire [31:0] _zz_305; + wire [19:0] _zz_306; + wire [11:0] _zz_307; + wire [31:0] _zz_308; + wire [31:0] _zz_309; + wire [19:0] _zz_310; + wire [11:0] _zz_311; + wire [2:0] _zz_312; + wire [2:0] _zz_313; wire [0:0] _zz_314; - wire [0:0] _zz_315; - wire [0:0] _zz_316; - wire [0:0] _zz_317; - wire [0:0] _zz_318; - wire [0:0] _zz_319; - wire [0:0] _zz_320; - wire [0:0] _zz_321; - wire [0:0] _zz_322; - wire [0:0] _zz_323; - wire [0:0] _zz_324; - wire [3:0] _zz_325; - wire [2:0] _zz_326; - wire [31:0] _zz_327; + wire [2:0] _zz_315; + wire [4:0] _zz_316; + wire [11:0] _zz_317; + wire [11:0] _zz_318; + wire [31:0] _zz_319; + wire [31:0] _zz_320; + wire [31:0] _zz_321; + wire [31:0] _zz_322; + wire [31:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [11:0] _zz_326; + wire [19:0] _zz_327; wire [11:0] _zz_328; wire [31:0] _zz_329; - wire [19:0] _zz_330; - wire [11:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [19:0] _zz_334; - wire [11:0] _zz_335; - wire [2:0] _zz_336; - wire [2:0] _zz_337; - wire [0:0] _zz_338; - wire [2:0] _zz_339; - wire [4:0] _zz_340; - wire [11:0] _zz_341; - wire [11:0] _zz_342; - wire [31:0] _zz_343; + wire [31:0] _zz_330; + wire [31:0] _zz_331; + wire [11:0] _zz_332; + wire [19:0] _zz_333; + wire [11:0] _zz_334; + wire [2:0] _zz_335; + wire [1:0] _zz_336; + wire [1:0] _zz_337; + wire [1:0] _zz_338; + wire [1:0] _zz_339; + wire [9:0] _zz_340; + wire [7:0] _zz_341; + wire [65:0] _zz_342; + wire [65:0] _zz_343; wire [31:0] _zz_344; wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; + wire [0:0] _zz_346; + wire [5:0] _zz_347; + wire [32:0] _zz_348; wire [31:0] _zz_349; - wire [11:0] _zz_350; - wire [19:0] _zz_351; - wire [11:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire [31:0] _zz_355; - wire [11:0] _zz_356; - wire [19:0] _zz_357; - wire [11:0] _zz_358; - wire [2:0] _zz_359; - wire [1:0] _zz_360; - wire [1:0] _zz_361; - wire [1:0] _zz_362; - wire [1:0] _zz_363; - wire [9:0] _zz_364; - wire [7:0] _zz_365; - wire [65:0] _zz_366; - wire [65:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; - wire [0:0] _zz_370; - wire [5:0] _zz_371; - wire [32:0] _zz_372; + wire [31:0] _zz_350; + wire [32:0] _zz_351; + wire [32:0] _zz_352; + wire [32:0] _zz_353; + wire [32:0] _zz_354; + wire [0:0] _zz_355; + wire [32:0] _zz_356; + wire [0:0] _zz_357; + wire [32:0] _zz_358; + wire [0:0] _zz_359; + wire [31:0] _zz_360; + wire [0:0] _zz_361; + wire [0:0] _zz_362; + wire [0:0] _zz_363; + wire [0:0] _zz_364; + wire [0:0] _zz_365; + wire [0:0] _zz_366; + wire [0:0] _zz_367; + wire [26:0] _zz_368; + wire _zz_369; + wire _zz_370; + wire [1:0] _zz_371; + wire [31:0] _zz_372; wire [31:0] _zz_373; wire [31:0] _zz_374; - wire [32:0] _zz_375; - wire [32:0] _zz_376; - wire [32:0] _zz_377; - wire [32:0] _zz_378; - wire [0:0] _zz_379; - wire [32:0] _zz_380; - wire [0:0] _zz_381; - wire [32:0] _zz_382; - wire [0:0] _zz_383; + wire _zz_375; + wire [0:0] _zz_376; + wire [14:0] _zz_377; + wire [31:0] _zz_378; + wire [31:0] _zz_379; + wire [31:0] _zz_380; + wire _zz_381; + wire [0:0] _zz_382; + wire [8:0] _zz_383; wire [31:0] _zz_384; - wire [0:0] _zz_385; - wire [0:0] _zz_386; - wire [0:0] _zz_387; + wire [31:0] _zz_385; + wire [31:0] _zz_386; + wire _zz_387; wire [0:0] _zz_388; - wire [0:0] _zz_389; - wire [0:0] _zz_390; - wire [0:0] _zz_391; - wire [26:0] _zz_392; - wire _zz_393; - wire _zz_394; - wire [1:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire _zz_399; + wire [2:0] _zz_389; + wire _zz_390; + wire _zz_391; + wire _zz_392; + wire [31:0] _zz_393; + wire [0:0] _zz_394; + wire [0:0] _zz_395; + wire _zz_396; + wire [0:0] _zz_397; + wire [28:0] _zz_398; + wire [0:0] _zz_399; wire [0:0] _zz_400; - wire [14:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [8:0] _zz_407; + wire [0:0] _zz_401; + wire [0:0] _zz_402; + wire _zz_403; + wire [0:0] _zz_404; + wire [23:0] _zz_405; + wire [31:0] _zz_406; + wire [31:0] _zz_407; wire [31:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire _zz_411; + wire _zz_409; + wire _zz_410; + wire [0:0] _zz_411; wire [0:0] _zz_412; - wire [2:0] _zz_413; - wire _zz_414; + wire [0:0] _zz_413; + wire [0:0] _zz_414; wire _zz_415; - wire _zz_416; - wire [31:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; + wire [0:0] _zz_416; + wire [20:0] _zz_417; + wire [31:0] _zz_418; + wire [31:0] _zz_419; wire _zz_420; - wire [0:0] _zz_421; - wire [28:0] _zz_422; - wire [0:0] _zz_423; + wire _zz_421; + wire [0:0] _zz_422; + wire [1:0] _zz_423; wire [0:0] _zz_424; wire [0:0] _zz_425; - wire [0:0] _zz_426; - wire _zz_427; - wire [0:0] _zz_428; - wire [23:0] _zz_429; + wire _zz_426; + wire [0:0] _zz_427; + wire [17:0] _zz_428; + wire [31:0] _zz_429; wire [31:0] _zz_430; wire [31:0] _zz_431; wire [31:0] _zz_432; - wire _zz_433; - wire _zz_434; - wire [0:0] _zz_435; - wire [0:0] _zz_436; - wire [0:0] _zz_437; - wire [0:0] _zz_438; - wire _zz_439; - wire [0:0] _zz_440; - wire [20:0] _zz_441; - wire [31:0] _zz_442; + wire [31:0] _zz_433; + wire [31:0] _zz_434; + wire [31:0] _zz_435; + wire [31:0] _zz_436; + wire _zz_437; + wire [1:0] _zz_438; + wire [1:0] _zz_439; + wire _zz_440; + wire [0:0] _zz_441; + wire [14:0] _zz_442; wire [31:0] _zz_443; - wire _zz_444; - wire _zz_445; - wire [0:0] _zz_446; - wire [1:0] _zz_447; - wire [0:0] _zz_448; + wire [31:0] _zz_444; + wire [31:0] _zz_445; + wire [31:0] _zz_446; + wire [31:0] _zz_447; + wire [31:0] _zz_448; wire [0:0] _zz_449; - wire _zz_450; - wire [0:0] _zz_451; - wire [17:0] _zz_452; - wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; + wire [1:0] _zz_450; + wire [4:0] _zz_451; + wire [4:0] _zz_452; + wire _zz_453; + wire [0:0] _zz_454; + wire [11:0] _zz_455; wire [31:0] _zz_456; wire [31:0] _zz_457; wire [31:0] _zz_458; wire [31:0] _zz_459; wire [31:0] _zz_460; - wire _zz_461; - wire [1:0] _zz_462; - wire [1:0] _zz_463; - wire _zz_464; - wire [0:0] _zz_465; - wire [14:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire [31:0] _zz_471; - wire [31:0] _zz_472; - wire [0:0] _zz_473; - wire [1:0] _zz_474; - wire [4:0] _zz_475; - wire [4:0] _zz_476; + wire [31:0] _zz_461; + wire _zz_462; + wire [0:0] _zz_463; + wire [1:0] _zz_464; + wire [31:0] _zz_465; + wire [31:0] _zz_466; + wire [0:0] _zz_467; + wire [4:0] _zz_468; + wire [4:0] _zz_469; + wire [4:0] _zz_470; + wire _zz_471; + wire [0:0] _zz_472; + wire [8:0] _zz_473; + wire [31:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; wire _zz_477; - wire [0:0] _zz_478; - wire [11:0] _zz_479; + wire _zz_478; + wire [31:0] _zz_479; wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire [31:0] _zz_485; - wire _zz_486; - wire [0:0] _zz_487; + wire _zz_481; + wire [0:0] _zz_482; + wire [2:0] _zz_483; + wire [0:0] _zz_484; + wire [2:0] _zz_485; + wire [0:0] _zz_486; + wire [4:0] _zz_487; wire [1:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; + wire [1:0] _zz_489; + wire _zz_490; wire [0:0] _zz_491; - wire [4:0] _zz_492; - wire [4:0] _zz_493; - wire [4:0] _zz_494; - wire _zz_495; - wire [0:0] _zz_496; - wire [8:0] _zz_497; - wire [31:0] _zz_498; + wire [6:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire _zz_496; + wire [0:0] _zz_497; + wire [0:0] _zz_498; wire [31:0] _zz_499; wire [31:0] _zz_500; wire _zz_501; - wire _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire _zz_505; - wire [0:0] _zz_506; - wire [2:0] _zz_507; + wire [0:0] _zz_502; + wire [0:0] _zz_503; + wire _zz_504; + wire [0:0] _zz_505; + wire [2:0] _zz_506; + wire _zz_507; wire [0:0] _zz_508; - wire [2:0] _zz_509; + wire [0:0] _zz_509; wire [0:0] _zz_510; - wire [4:0] _zz_511; - wire [1:0] _zz_512; - wire [1:0] _zz_513; - wire _zz_514; - wire [0:0] _zz_515; - wire [6:0] _zz_516; + wire [0:0] _zz_511; + wire _zz_512; + wire [0:0] _zz_513; + wire [4:0] _zz_514; + wire [31:0] _zz_515; + wire [31:0] _zz_516; wire [31:0] _zz_517; wire [31:0] _zz_518; wire [31:0] _zz_519; - wire _zz_520; - wire [0:0] _zz_521; - wire [0:0] _zz_522; + wire [31:0] _zz_520; + wire [31:0] _zz_521; + wire [31:0] _zz_522; wire [31:0] _zz_523; wire [31:0] _zz_524; - wire _zz_525; - wire [0:0] _zz_526; - wire [0:0] _zz_527; + wire [31:0] _zz_525; + wire [31:0] _zz_526; + wire [31:0] _zz_527; wire _zz_528; wire [0:0] _zz_529; - wire [2:0] _zz_530; - wire _zz_531; - wire [0:0] _zz_532; - wire [0:0] _zz_533; - wire [0:0] _zz_534; - wire [0:0] _zz_535; + wire [0:0] _zz_530; + wire [31:0] _zz_531; + wire [31:0] _zz_532; + wire [31:0] _zz_533; + wire [31:0] _zz_534; + wire [31:0] _zz_535; wire _zz_536; - wire [0:0] _zz_537; - wire [4:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire [31:0] _zz_541; + wire [3:0] _zz_537; + wire [3:0] _zz_538; + wire _zz_539; + wire [0:0] _zz_540; + wire [2:0] _zz_541; wire [31:0] _zz_542; wire [31:0] _zz_543; wire [31:0] _zz_544; wire [31:0] _zz_545; wire [31:0] _zz_546; wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire [31:0] _zz_549; - wire [31:0] _zz_550; - wire [31:0] _zz_551; - wire _zz_552; - wire [0:0] _zz_553; - wire [0:0] _zz_554; - wire [31:0] _zz_555; - wire [31:0] _zz_556; + wire _zz_548; + wire [0:0] _zz_549; + wire [1:0] _zz_550; + wire _zz_551; + wire [2:0] _zz_552; + wire [2:0] _zz_553; + wire _zz_554; + wire [0:0] _zz_555; + wire [0:0] _zz_556; wire [31:0] _zz_557; wire [31:0] _zz_558; wire [31:0] _zz_559; - wire _zz_560; - wire [3:0] _zz_561; - wire [3:0] _zz_562; - wire _zz_563; - wire [0:0] _zz_564; - wire [2:0] _zz_565; - wire [31:0] _zz_566; - wire [31:0] _zz_567; - wire [31:0] _zz_568; - wire [31:0] _zz_569; - wire [31:0] _zz_570; - wire [31:0] _zz_571; + wire [31:0] _zz_560; + wire [31:0] _zz_561; + wire [31:0] _zz_562; + wire [31:0] _zz_563; + wire _zz_564; + wire _zz_565; + wire _zz_566; + wire [0:0] _zz_567; + wire [0:0] _zz_568; + wire _zz_569; + wire _zz_570; + wire _zz_571; wire _zz_572; - wire [0:0] _zz_573; - wire [1:0] _zz_574; - wire _zz_575; - wire [2:0] _zz_576; - wire [2:0] _zz_577; - wire _zz_578; - wire [0:0] _zz_579; - wire [0:0] _zz_580; - wire [31:0] _zz_581; - wire [31:0] _zz_582; - wire [31:0] _zz_583; - wire [31:0] _zz_584; - wire [31:0] _zz_585; - wire [31:0] _zz_586; - wire [31:0] _zz_587; - wire _zz_588; - wire _zz_589; - wire _zz_590; - wire [0:0] _zz_591; - wire [0:0] _zz_592; - wire _zz_593; - wire _zz_594; - wire _zz_595; - wire _zz_596; - wire [31:0] _zz_597; + wire [31:0] _zz_573; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1103,29 +1103,13 @@ module VexRiscv ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_168; - reg [23:0] _zz_169; - reg [31:0] _zz_170; + wire _zz_152; + reg [23:0] _zz_153; + reg [31:0] _zz_154; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1157,18 +1141,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_171; + wire [31:0] _zz_155; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_172; - wire _zz_173; - wire _zz_174; - reg [32:0] _zz_175; + wire [31:0] _zz_156; + wire _zz_157; + wire _zz_158; + reg [32:0] _zz_159; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_176; - wire [31:0] _zz_177; + reg [31:0] _zz_160; + wire [31:0] _zz_161; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1178,7 +1162,7 @@ module VexRiscv ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_178; + reg _zz_162; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1246,7 +1230,7 @@ module VexRiscv ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_179; + reg [2:0] _zz_163; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; @@ -1269,24 +1253,24 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3200; reg execute_CsrPlugin_csr_3074; reg execute_CsrPlugin_csr_3202; - reg execute_CsrPlugin_csr_2820; - reg execute_CsrPlugin_csr_2821; - reg execute_CsrPlugin_csr_2822; - reg execute_CsrPlugin_csr_2823; - reg execute_CsrPlugin_csr_2824; - reg execute_CsrPlugin_csr_2825; - reg execute_CsrPlugin_csr_2826; - reg execute_CsrPlugin_csr_2827; - reg execute_CsrPlugin_csr_2828; - reg execute_CsrPlugin_csr_2829; - reg execute_CsrPlugin_csr_2830; - reg execute_CsrPlugin_csr_2831; - reg execute_CsrPlugin_csr_2832; - reg execute_CsrPlugin_csr_2833; - reg execute_CsrPlugin_csr_2834; - reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; reg [31:0] _zz_180; reg [31:0] _zz_181; reg [31:0] _zz_182; @@ -1294,40 +1278,16 @@ module VexRiscv ( reg [31:0] _zz_184; reg [31:0] _zz_185; reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [31:0] _zz_199; - reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; - reg [31:0] _zz_208; - reg [31:0] _zz_209; - reg [31:0] _zz_210; - reg [2:0] _zz_211; - reg _zz_212; + reg [2:0] _zz_187; + reg _zz_188; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - reg _zz_219; + reg [2:0] _zz_189; + wire _zz_190; + wire _zz_191; + wire _zz_192; + wire _zz_193; + wire _zz_194; + reg _zz_195; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; @@ -1421,362 +1381,362 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_251 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_253 = 1'b1; - assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_256 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_257 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_258 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_259 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_260 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_261 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_262 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_263 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_264 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_265 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_268 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_269 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_270 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_271 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_272 = (1'b0 || (! 1'b1)); - assign _zz_273 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_274 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_275 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_276 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_277 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_278 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_280 = execute_INSTRUCTION[13 : 12]; - assign _zz_281 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_282 = (! memory_arbitration_isStuck); - assign _zz_283 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_284 = (iBus_cmd_valid || (_zz_211 != 3'b000)); - assign _zz_285 = (_zz_247 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_286 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_287 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_288 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_289 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_290 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_291 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_292 = execute_INSTRUCTION[13]; - assign _zz_293 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_294 = ($signed(_zz_295) + $signed(_zz_300)); - assign _zz_295 = ($signed(_zz_296) + $signed(_zz_298)); - assign _zz_296 = 52'h0; - assign _zz_297 = {1'b0,memory_MUL_LL}; - assign _zz_298 = {{19{_zz_297[32]}}, _zz_297}; - assign _zz_299 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; - assign _zz_301 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_302 = {{2{_zz_301[49]}}, _zz_301}; - assign _zz_303 = ($signed(_zz_305) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_304 = _zz_303[31 : 0]; - assign _zz_305 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_306 = _zz_94[33 : 33]; - assign _zz_307 = _zz_94[32 : 32]; - assign _zz_308 = _zz_94[31 : 31]; - assign _zz_309 = _zz_94[30 : 30]; - assign _zz_310 = _zz_94[28 : 28]; - assign _zz_311 = _zz_94[25 : 25]; - assign _zz_312 = _zz_94[17 : 17]; - assign _zz_313 = _zz_94[16 : 16]; - assign _zz_314 = _zz_94[13 : 13]; - assign _zz_315 = _zz_94[12 : 12]; - assign _zz_316 = _zz_94[11 : 11]; - assign _zz_317 = _zz_94[34 : 34]; - assign _zz_318 = _zz_94[15 : 15]; - assign _zz_319 = _zz_94[5 : 5]; - assign _zz_320 = _zz_94[3 : 3]; - assign _zz_321 = _zz_94[20 : 20]; - assign _zz_322 = _zz_94[10 : 10]; - assign _zz_323 = _zz_94[4 : 4]; - assign _zz_324 = _zz_94[0 : 0]; - assign _zz_325 = (_zz_62 - 4'b0001); - assign _zz_326 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_327 = {29'd0, _zz_326}; - assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_329 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_331 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_332 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_333 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_334 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_335 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_338 = execute_SRC_LESS; - assign _zz_339 = 3'b100; - assign _zz_340 = execute_INSTRUCTION[19 : 15]; - assign _zz_341 = execute_INSTRUCTION[31 : 20]; - assign _zz_342 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_343 = ($signed(_zz_344) + $signed(_zz_347)); - assign _zz_344 = ($signed(_zz_345) + $signed(_zz_346)); - assign _zz_345 = execute_SRC1; - assign _zz_346 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_347 = (execute_SRC_USE_SUB_LESS ? _zz_348 : _zz_349); - assign _zz_348 = 32'h00000001; - assign _zz_349 = 32'h0; - assign _zz_350 = execute_INSTRUCTION[31 : 20]; - assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_353 = {_zz_133,execute_INSTRUCTION[31 : 20]}; - assign _zz_354 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_355 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_356 = execute_INSTRUCTION[31 : 20]; - assign _zz_357 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_359 = 3'b100; - assign _zz_360 = (_zz_148 & (~ _zz_361)); - assign _zz_361 = (_zz_148 - 2'b01); - assign _zz_362 = (_zz_150 & (~ _zz_363)); - assign _zz_363 = (_zz_150 - 2'b01); - assign _zz_364 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_365 = execute_INSTRUCTION[31 : 24]; - assign _zz_366 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_367 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_368 = writeBack_MUL_LOW[31 : 0]; - assign _zz_369 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_370 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_371 = {5'd0, _zz_370}; - assign _zz_372 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_373 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_374 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_375 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_376 = _zz_377; - assign _zz_377 = _zz_378; - assign _zz_378 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_380); - assign _zz_379 = memory_DivPlugin_div_needRevert; - assign _zz_380 = {32'd0, _zz_379}; - assign _zz_381 = _zz_174; - assign _zz_382 = {32'd0, _zz_381}; - assign _zz_383 = _zz_173; - assign _zz_384 = {31'd0, _zz_383}; - assign _zz_385 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_386 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_387 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_388 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_391 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_392 = (iBus_cmd_payload_address >>> 5); - assign _zz_393 = 1'b1; - assign _zz_394 = 1'b1; - assign _zz_395 = {_zz_66,_zz_65}; - assign _zz_396 = 32'h0000106f; - assign _zz_397 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_398 = 32'h00001073; - assign _zz_399 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_400 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_401 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_402) == 32'h00000003),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; - assign _zz_402 = 32'h0000207f; - assign _zz_403 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_404 = 32'h00000003; - assign _zz_405 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_406 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_407 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_408) == 32'h00005013),{(_zz_409 == _zz_410),{_zz_411,{_zz_412,_zz_413}}}}}}; - assign _zz_408 = 32'hbc00707f; - assign _zz_409 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_410 = 32'h00001013; - assign _zz_411 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_412 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_413 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; - assign _zz_414 = decode_INSTRUCTION[31]; - assign _zz_415 = decode_INSTRUCTION[31]; - assign _zz_416 = decode_INSTRUCTION[7]; - assign _zz_417 = 32'h10103050; - assign _zz_418 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_419 = 1'b0; - assign _zz_420 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_421 = 1'b0; - assign _zz_422 = {(_zz_98 != 1'b0),{({_zz_423,_zz_424} != 2'b00),{(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}}}; - assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h10000050); - assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00000050); - assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00000050); - assign _zz_426 = 1'b0; - assign _zz_427 = ({_zz_433,_zz_434} != 2'b00); - assign _zz_428 = ({_zz_435,_zz_436} != 2'b00); - assign _zz_429 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; - assign _zz_430 = 32'h10203050; - assign _zz_431 = 32'h10103050; - assign _zz_432 = 32'h00103050; - assign _zz_433 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_434 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_435 = _zz_97; - assign _zz_436 = ((decode_INSTRUCTION & _zz_442) == 32'h00000004); - assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000040); - assign _zz_438 = 1'b0; - assign _zz_439 = ({_zz_444,_zz_445} != 2'b00); - assign _zz_440 = ({_zz_446,_zz_447} != 3'b000); - assign _zz_441 = {(_zz_448 != _zz_449),{_zz_450,{_zz_451,_zz_452}}}; - assign _zz_442 = 32'h0000001c; - assign _zz_443 = 32'h00000058; - assign _zz_444 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_445 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h40001010); - assign _zz_447 = {(_zz_454 == _zz_455),(_zz_456 == _zz_457)}; - assign _zz_448 = ((decode_INSTRUCTION & _zz_458) == 32'h00000024); - assign _zz_449 = 1'b0; - assign _zz_450 = ((_zz_459 == _zz_460) != 1'b0); - assign _zz_451 = (_zz_461 != 1'b0); - assign _zz_452 = {(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}; - assign _zz_453 = 32'h40003054; - assign _zz_454 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_455 = 32'h00001010; - assign _zz_456 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_457 = 32'h00001010; - assign _zz_458 = 32'h00000064; - assign _zz_459 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_460 = 32'h00001000; - assign _zz_461 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_462 = {(_zz_467 == _zz_468),(_zz_469 == _zz_470)}; - assign _zz_463 = 2'b00; - assign _zz_464 = ((_zz_471 == _zz_472) != 1'b0); - assign _zz_465 = ({_zz_473,_zz_474} != 3'b000); - assign _zz_466 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; - assign _zz_467 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_468 = 32'h00002000; - assign _zz_469 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_470 = 32'h00001000; - assign _zz_471 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_472 = 32'h00004004; - assign _zz_473 = _zz_98; - assign _zz_474 = {(_zz_480 == _zz_481),(_zz_482 == _zz_483)}; - assign _zz_475 = {(_zz_484 == _zz_485),{_zz_486,{_zz_487,_zz_488}}}; - assign _zz_476 = 5'h0; - assign _zz_477 = ((_zz_489 == _zz_490) != 1'b0); - assign _zz_478 = ({_zz_491,_zz_492} != 6'h0); - assign _zz_479 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; - assign _zz_480 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_481 = 32'h00000020; - assign _zz_482 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_483 = 32'h00000020; - assign _zz_484 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_485 = 32'h00002040; - assign _zz_486 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); - assign _zz_487 = (_zz_499 == _zz_500); - assign _zz_488 = {_zz_501,_zz_502}; - assign _zz_489 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_490 = 32'h00000020; - assign _zz_491 = (_zz_503 == _zz_504); - assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; - assign _zz_493 = {_zz_96,{_zz_508,_zz_509}}; - assign _zz_494 = 5'h0; - assign _zz_495 = ({_zz_510,_zz_511} != 6'h0); - assign _zz_496 = (_zz_512 != _zz_513); - assign _zz_497 = {_zz_514,{_zz_515,_zz_516}}; - assign _zz_498 = 32'h00001040; - assign _zz_499 = (decode_INSTRUCTION & 32'h00100040); - assign _zz_500 = 32'h00000040; - assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00000040); - assign _zz_502 = ((decode_INSTRUCTION & _zz_518) == 32'h0); - assign _zz_503 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_504 = 32'h00000008; - assign _zz_505 = ((decode_INSTRUCTION & _zz_519) == 32'h00000040); - assign _zz_506 = _zz_96; - assign _zz_507 = {_zz_520,{_zz_521,_zz_522}}; - assign _zz_508 = (_zz_523 == _zz_524); - assign _zz_509 = {_zz_525,{_zz_526,_zz_527}}; - assign _zz_510 = _zz_97; - assign _zz_511 = {_zz_528,{_zz_529,_zz_530}}; - assign _zz_512 = {_zz_96,_zz_531}; - assign _zz_513 = 2'b00; - assign _zz_514 = ({_zz_532,_zz_533} != 2'b00); - assign _zz_515 = (_zz_534 != _zz_535); - assign _zz_516 = {_zz_536,{_zz_537,_zz_538}}; - assign _zz_517 = 32'h00000050; - assign _zz_518 = 32'h00000038; - assign _zz_519 = 32'h00000040; - assign _zz_520 = ((decode_INSTRUCTION & _zz_539) == 32'h00004020); - assign _zz_521 = (_zz_540 == _zz_541); - assign _zz_522 = (_zz_542 == _zz_543); - assign _zz_523 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_524 = 32'h00002010; - assign _zz_525 = ((decode_INSTRUCTION & _zz_544) == 32'h00000010); - assign _zz_526 = (_zz_545 == _zz_546); - assign _zz_527 = (_zz_547 == _zz_548); - assign _zz_528 = ((decode_INSTRUCTION & _zz_549) == 32'h00001010); - assign _zz_529 = (_zz_550 == _zz_551); - assign _zz_530 = {_zz_552,{_zz_553,_zz_554}}; - assign _zz_531 = ((decode_INSTRUCTION & _zz_555) == 32'h00000020); - assign _zz_532 = _zz_96; - assign _zz_533 = (_zz_556 == _zz_557); - assign _zz_534 = (_zz_558 == _zz_559); - assign _zz_535 = 1'b0; - assign _zz_536 = (_zz_560 != 1'b0); - assign _zz_537 = (_zz_561 != _zz_562); - assign _zz_538 = {_zz_563,{_zz_564,_zz_565}}; - assign _zz_539 = 32'h00004020; - assign _zz_540 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_541 = 32'h00000010; - assign _zz_542 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_543 = 32'h00000020; - assign _zz_544 = 32'h00001030; - assign _zz_545 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_546 = 32'h00002020; - assign _zz_547 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_548 = 32'h00000020; - assign _zz_549 = 32'h00001010; - assign _zz_550 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_551 = 32'h00002010; - assign _zz_552 = ((decode_INSTRUCTION & _zz_566) == 32'h00000010); - assign _zz_553 = (_zz_567 == _zz_568); - assign _zz_554 = (_zz_569 == _zz_570); - assign _zz_555 = 32'h00000070; - assign _zz_556 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_557 = 32'h0; - assign _zz_558 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_559 = 32'h00004010; - assign _zz_560 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); - assign _zz_561 = {_zz_572,{_zz_573,_zz_574}}; - assign _zz_562 = 4'b0000; - assign _zz_563 = (_zz_575 != 1'b0); - assign _zz_564 = (_zz_576 != _zz_577); - assign _zz_565 = {_zz_578,{_zz_579,_zz_580}}; - assign _zz_566 = 32'h00000050; - assign _zz_567 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_568 = 32'h00000004; - assign _zz_569 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_570 = 32'h0; - assign _zz_571 = 32'h00006014; - assign _zz_572 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_573 = ((decode_INSTRUCTION & _zz_581) == 32'h0); - assign _zz_574 = {(_zz_582 == _zz_583),(_zz_584 == _zz_585)}; - assign _zz_575 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_576 = {(_zz_586 == _zz_587),{_zz_588,_zz_589}}; - assign _zz_577 = 3'b000; - assign _zz_578 = ({_zz_590,_zz_95} != 2'b00); - assign _zz_579 = ({_zz_591,_zz_592} != 2'b00); - assign _zz_580 = (_zz_593 != 1'b0); - assign _zz_581 = 32'h00000018; - assign _zz_582 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_583 = 32'h00002000; - assign _zz_584 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_585 = 32'h00001000; - assign _zz_586 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_587 = 32'h00000040; - assign _zz_588 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_589 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_590 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_591 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_592 = _zz_95; - assign _zz_593 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); - assign _zz_594 = execute_INSTRUCTION[31]; - assign _zz_595 = execute_INSTRUCTION[31]; - assign _zz_596 = execute_INSTRUCTION[7]; - assign _zz_597 = 32'h0; + assign _zz_227 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_228 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_229 = 1'b1; + assign _zz_230 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_231 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_232 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_233 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_234 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_235 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_236 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_237 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_238 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_239 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_240 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_241 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_242 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_243 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_244 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_245 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_246 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_247 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_248 = (1'b0 || (! 1'b1)); + assign _zz_249 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_250 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_251 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_252 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_253 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_254 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_255 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_256 = execute_INSTRUCTION[13 : 12]; + assign _zz_257 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_258 = (! memory_arbitration_isStuck); + assign _zz_259 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_260 = (iBus_cmd_valid || (_zz_187 != 3'b000)); + assign _zz_261 = (_zz_223 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_262 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_263 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_264 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_265 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_266 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_267 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_268 = execute_INSTRUCTION[13]; + assign _zz_269 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_270 = ($signed(_zz_271) + $signed(_zz_276)); + assign _zz_271 = ($signed(_zz_272) + $signed(_zz_274)); + assign _zz_272 = 52'h0; + assign _zz_273 = {1'b0,memory_MUL_LL}; + assign _zz_274 = {{19{_zz_273[32]}}, _zz_273}; + assign _zz_275 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_276 = {{2{_zz_275[49]}}, _zz_275}; + assign _zz_277 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_278 = {{2{_zz_277[49]}}, _zz_277}; + assign _zz_279 = ($signed(_zz_281) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_280 = _zz_279[31 : 0]; + assign _zz_281 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_282 = _zz_94[33 : 33]; + assign _zz_283 = _zz_94[32 : 32]; + assign _zz_284 = _zz_94[31 : 31]; + assign _zz_285 = _zz_94[30 : 30]; + assign _zz_286 = _zz_94[28 : 28]; + assign _zz_287 = _zz_94[25 : 25]; + assign _zz_288 = _zz_94[17 : 17]; + assign _zz_289 = _zz_94[16 : 16]; + assign _zz_290 = _zz_94[13 : 13]; + assign _zz_291 = _zz_94[12 : 12]; + assign _zz_292 = _zz_94[11 : 11]; + assign _zz_293 = _zz_94[34 : 34]; + assign _zz_294 = _zz_94[15 : 15]; + assign _zz_295 = _zz_94[5 : 5]; + assign _zz_296 = _zz_94[3 : 3]; + assign _zz_297 = _zz_94[20 : 20]; + assign _zz_298 = _zz_94[10 : 10]; + assign _zz_299 = _zz_94[4 : 4]; + assign _zz_300 = _zz_94[0 : 0]; + assign _zz_301 = (_zz_62 - 4'b0001); + assign _zz_302 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_303 = {29'd0, _zz_302}; + assign _zz_304 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_305 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_306 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_307 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_308 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_309 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_310 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_311 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_312 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_313 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_314 = execute_SRC_LESS; + assign _zz_315 = 3'b100; + assign _zz_316 = execute_INSTRUCTION[19 : 15]; + assign _zz_317 = execute_INSTRUCTION[31 : 20]; + assign _zz_318 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_319 = ($signed(_zz_320) + $signed(_zz_323)); + assign _zz_320 = ($signed(_zz_321) + $signed(_zz_322)); + assign _zz_321 = execute_SRC1; + assign _zz_322 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_323 = (execute_SRC_USE_SUB_LESS ? _zz_324 : _zz_325); + assign _zz_324 = 32'h00000001; + assign _zz_325 = 32'h0; + assign _zz_326 = execute_INSTRUCTION[31 : 20]; + assign _zz_327 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_329 = {_zz_133,execute_INSTRUCTION[31 : 20]}; + assign _zz_330 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_331 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_332 = execute_INSTRUCTION[31 : 20]; + assign _zz_333 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_334 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_335 = 3'b100; + assign _zz_336 = (_zz_148 & (~ _zz_337)); + assign _zz_337 = (_zz_148 - 2'b01); + assign _zz_338 = (_zz_150 & (~ _zz_339)); + assign _zz_339 = (_zz_150 - 2'b01); + assign _zz_340 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_341 = execute_INSTRUCTION[31 : 24]; + assign _zz_342 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_343 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_344 = writeBack_MUL_LOW[31 : 0]; + assign _zz_345 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_346 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_347 = {5'd0, _zz_346}; + assign _zz_348 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_349 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_350 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_351 = {_zz_155,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_352 = _zz_353; + assign _zz_353 = _zz_354; + assign _zz_354 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_156) : _zz_156)} + _zz_356); + assign _zz_355 = memory_DivPlugin_div_needRevert; + assign _zz_356 = {32'd0, _zz_355}; + assign _zz_357 = _zz_158; + assign _zz_358 = {32'd0, _zz_357}; + assign _zz_359 = _zz_157; + assign _zz_360 = {31'd0, _zz_359}; + assign _zz_361 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_362 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_363 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_364 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_365 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_366 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_367 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_368 = (iBus_cmd_payload_address >>> 5); + assign _zz_369 = 1'b1; + assign _zz_370 = 1'b1; + assign _zz_371 = {_zz_66,_zz_65}; + assign _zz_372 = 32'h0000106f; + assign _zz_373 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_374 = 32'h00001073; + assign _zz_375 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_376 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_377 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_378) == 32'h00000003),{(_zz_379 == _zz_380),{_zz_381,{_zz_382,_zz_383}}}}}}; + assign _zz_378 = 32'h0000207f; + assign _zz_379 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_380 = 32'h00000003; + assign _zz_381 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_382 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_383 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_384) == 32'h00005013),{(_zz_385 == _zz_386),{_zz_387,{_zz_388,_zz_389}}}}}}; + assign _zz_384 = 32'hbc00707f; + assign _zz_385 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_386 = 32'h00001013; + assign _zz_387 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_388 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_389 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_390 = decode_INSTRUCTION[31]; + assign _zz_391 = decode_INSTRUCTION[31]; + assign _zz_392 = decode_INSTRUCTION[7]; + assign _zz_393 = 32'h10103050; + assign _zz_394 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_395 = 1'b0; + assign _zz_396 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_397 = 1'b0; + assign _zz_398 = {(_zz_98 != 1'b0),{({_zz_399,_zz_400} != 2'b00),{(_zz_401 != _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}; + assign _zz_399 = ((decode_INSTRUCTION & _zz_406) == 32'h10000050); + assign _zz_400 = ((decode_INSTRUCTION & _zz_407) == 32'h00000050); + assign _zz_401 = ((decode_INSTRUCTION & _zz_408) == 32'h00000050); + assign _zz_402 = 1'b0; + assign _zz_403 = ({_zz_409,_zz_410} != 2'b00); + assign _zz_404 = ({_zz_411,_zz_412} != 2'b00); + assign _zz_405 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; + assign _zz_406 = 32'h10203050; + assign _zz_407 = 32'h10103050; + assign _zz_408 = 32'h00103050; + assign _zz_409 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_410 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_411 = _zz_97; + assign _zz_412 = ((decode_INSTRUCTION & _zz_418) == 32'h00000004); + assign _zz_413 = ((decode_INSTRUCTION & _zz_419) == 32'h00000040); + assign _zz_414 = 1'b0; + assign _zz_415 = ({_zz_420,_zz_421} != 2'b00); + assign _zz_416 = ({_zz_422,_zz_423} != 3'b000); + assign _zz_417 = {(_zz_424 != _zz_425),{_zz_426,{_zz_427,_zz_428}}}; + assign _zz_418 = 32'h0000001c; + assign _zz_419 = 32'h00000058; + assign _zz_420 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_421 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_422 = ((decode_INSTRUCTION & _zz_429) == 32'h40001010); + assign _zz_423 = {(_zz_430 == _zz_431),(_zz_432 == _zz_433)}; + assign _zz_424 = ((decode_INSTRUCTION & _zz_434) == 32'h00000024); + assign _zz_425 = 1'b0; + assign _zz_426 = ((_zz_435 == _zz_436) != 1'b0); + assign _zz_427 = (_zz_437 != 1'b0); + assign _zz_428 = {(_zz_438 != _zz_439),{_zz_440,{_zz_441,_zz_442}}}; + assign _zz_429 = 32'h40003054; + assign _zz_430 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_431 = 32'h00001010; + assign _zz_432 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_433 = 32'h00001010; + assign _zz_434 = 32'h00000064; + assign _zz_435 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_436 = 32'h00001000; + assign _zz_437 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_438 = {(_zz_443 == _zz_444),(_zz_445 == _zz_446)}; + assign _zz_439 = 2'b00; + assign _zz_440 = ((_zz_447 == _zz_448) != 1'b0); + assign _zz_441 = ({_zz_449,_zz_450} != 3'b000); + assign _zz_442 = {(_zz_451 != _zz_452),{_zz_453,{_zz_454,_zz_455}}}; + assign _zz_443 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_444 = 32'h00002000; + assign _zz_445 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_446 = 32'h00001000; + assign _zz_447 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_448 = 32'h00004004; + assign _zz_449 = _zz_98; + assign _zz_450 = {(_zz_456 == _zz_457),(_zz_458 == _zz_459)}; + assign _zz_451 = {(_zz_460 == _zz_461),{_zz_462,{_zz_463,_zz_464}}}; + assign _zz_452 = 5'h0; + assign _zz_453 = ((_zz_465 == _zz_466) != 1'b0); + assign _zz_454 = ({_zz_467,_zz_468} != 6'h0); + assign _zz_455 = {(_zz_469 != _zz_470),{_zz_471,{_zz_472,_zz_473}}}; + assign _zz_456 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_457 = 32'h00000020; + assign _zz_458 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_459 = 32'h00000020; + assign _zz_460 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_461 = 32'h00002040; + assign _zz_462 = ((decode_INSTRUCTION & _zz_474) == 32'h00001040); + assign _zz_463 = (_zz_475 == _zz_476); + assign _zz_464 = {_zz_477,_zz_478}; + assign _zz_465 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_466 = 32'h00000020; + assign _zz_467 = (_zz_479 == _zz_480); + assign _zz_468 = {_zz_481,{_zz_482,_zz_483}}; + assign _zz_469 = {_zz_96,{_zz_484,_zz_485}}; + assign _zz_470 = 5'h0; + assign _zz_471 = ({_zz_486,_zz_487} != 6'h0); + assign _zz_472 = (_zz_488 != _zz_489); + assign _zz_473 = {_zz_490,{_zz_491,_zz_492}}; + assign _zz_474 = 32'h00001040; + assign _zz_475 = (decode_INSTRUCTION & 32'h00100040); + assign _zz_476 = 32'h00000040; + assign _zz_477 = ((decode_INSTRUCTION & _zz_493) == 32'h00000040); + assign _zz_478 = ((decode_INSTRUCTION & _zz_494) == 32'h0); + assign _zz_479 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_480 = 32'h00000008; + assign _zz_481 = ((decode_INSTRUCTION & _zz_495) == 32'h00000040); + assign _zz_482 = _zz_96; + assign _zz_483 = {_zz_496,{_zz_497,_zz_498}}; + assign _zz_484 = (_zz_499 == _zz_500); + assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; + assign _zz_486 = _zz_97; + assign _zz_487 = {_zz_504,{_zz_505,_zz_506}}; + assign _zz_488 = {_zz_96,_zz_507}; + assign _zz_489 = 2'b00; + assign _zz_490 = ({_zz_508,_zz_509} != 2'b00); + assign _zz_491 = (_zz_510 != _zz_511); + assign _zz_492 = {_zz_512,{_zz_513,_zz_514}}; + assign _zz_493 = 32'h00000050; + assign _zz_494 = 32'h00000038; + assign _zz_495 = 32'h00000040; + assign _zz_496 = ((decode_INSTRUCTION & _zz_515) == 32'h00004020); + assign _zz_497 = (_zz_516 == _zz_517); + assign _zz_498 = (_zz_518 == _zz_519); + assign _zz_499 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_500 = 32'h00002010; + assign _zz_501 = ((decode_INSTRUCTION & _zz_520) == 32'h00000010); + assign _zz_502 = (_zz_521 == _zz_522); + assign _zz_503 = (_zz_523 == _zz_524); + assign _zz_504 = ((decode_INSTRUCTION & _zz_525) == 32'h00001010); + assign _zz_505 = (_zz_526 == _zz_527); + assign _zz_506 = {_zz_528,{_zz_529,_zz_530}}; + assign _zz_507 = ((decode_INSTRUCTION & _zz_531) == 32'h00000020); + assign _zz_508 = _zz_96; + assign _zz_509 = (_zz_532 == _zz_533); + assign _zz_510 = (_zz_534 == _zz_535); + assign _zz_511 = 1'b0; + assign _zz_512 = (_zz_536 != 1'b0); + assign _zz_513 = (_zz_537 != _zz_538); + assign _zz_514 = {_zz_539,{_zz_540,_zz_541}}; + assign _zz_515 = 32'h00004020; + assign _zz_516 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_517 = 32'h00000010; + assign _zz_518 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_519 = 32'h00000020; + assign _zz_520 = 32'h00001030; + assign _zz_521 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_522 = 32'h00002020; + assign _zz_523 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_524 = 32'h00000020; + assign _zz_525 = 32'h00001010; + assign _zz_526 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_527 = 32'h00002010; + assign _zz_528 = ((decode_INSTRUCTION & _zz_542) == 32'h00000010); + assign _zz_529 = (_zz_543 == _zz_544); + assign _zz_530 = (_zz_545 == _zz_546); + assign _zz_531 = 32'h00000070; + assign _zz_532 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_533 = 32'h0; + assign _zz_534 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_535 = 32'h00004010; + assign _zz_536 = ((decode_INSTRUCTION & _zz_547) == 32'h00002010); + assign _zz_537 = {_zz_548,{_zz_549,_zz_550}}; + assign _zz_538 = 4'b0000; + assign _zz_539 = (_zz_551 != 1'b0); + assign _zz_540 = (_zz_552 != _zz_553); + assign _zz_541 = {_zz_554,{_zz_555,_zz_556}}; + assign _zz_542 = 32'h00000050; + assign _zz_543 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_544 = 32'h00000004; + assign _zz_545 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_546 = 32'h0; + assign _zz_547 = 32'h00006014; + assign _zz_548 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_549 = ((decode_INSTRUCTION & _zz_557) == 32'h0); + assign _zz_550 = {(_zz_558 == _zz_559),(_zz_560 == _zz_561)}; + assign _zz_551 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_552 = {(_zz_562 == _zz_563),{_zz_564,_zz_565}}; + assign _zz_553 = 3'b000; + assign _zz_554 = ({_zz_566,_zz_95} != 2'b00); + assign _zz_555 = ({_zz_567,_zz_568} != 2'b00); + assign _zz_556 = (_zz_569 != 1'b0); + assign _zz_557 = 32'h00000018; + assign _zz_558 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_559 = 32'h00002000; + assign _zz_560 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_561 = 32'h00001000; + assign _zz_562 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_563 = 32'h00000040; + assign _zz_564 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_565 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_566 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_567 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_568 = _zz_95; + assign _zz_569 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_570 = execute_INSTRUCTION[31]; + assign _zz_571 = execute_INSTRUCTION[31]; + assign _zz_572 = execute_INSTRUCTION[7]; + assign _zz_573 = 32'h0; always @ (posedge clk) begin - if(_zz_393) begin - _zz_248 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_369) begin + _zz_224 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_394) begin - _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_370) begin + _zz_225 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1787,13 +1747,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_220 ), //i - .io_cpu_prefetch_isValid (_zz_221 ), //i + .io_flush (_zz_196 ), //i + .io_cpu_prefetch_isValid (_zz_197 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_222 ), //i - .io_cpu_fetch_isStuck (_zz_223 ), //i - .io_cpu_fetch_isRemoved (_zz_224 ), //i + .io_cpu_fetch_isValid (_zz_198 ), //i + .io_cpu_fetch_isStuck (_zz_199 ), //i + .io_cpu_fetch_isRemoved (_zz_200 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1806,8 +1766,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_225 ), //i - .io_cpu_decode_isStuck (_zz_226 ), //i + .io_cpu_decode_isValid (_zz_201 ), //i + .io_cpu_decode_isStuck (_zz_202 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1815,8 +1775,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_227 ), //i - .io_cpu_fill_valid (_zz_228 ), //i + .io_cpu_decode_isUser (_zz_203 ), //i + .io_cpu_fill_valid (_zz_204 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1825,26 +1785,26 @@ module VexRiscv ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_16 (_zz_179[2:0] ), //i + ._zz_16 (_zz_163[2:0] ), //i ._zz_17 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_229 ), //i - .io_cpu_execute_address (_zz_230[31:0] ), //i + .io_cpu_execute_isValid (_zz_205 ), //i + .io_cpu_execute_address (_zz_206[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_89[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_231 ), //i + .io_cpu_memory_isValid (_zz_207 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_232[31:0] ), //i + .io_cpu_memory_address (_zz_208[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_233 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_209 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1852,31 +1812,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_234 ), //i + .io_cpu_writeBack_isValid (_zz_210 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_235 ), //i + .io_cpu_writeBack_isUser (_zz_211 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_236[31:0] ), //i + .io_cpu_writeBack_address (_zz_212[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_237 ), //i - .io_cpu_writeBack_fence_SR (_zz_238 ), //i - .io_cpu_writeBack_fence_SO (_zz_239 ), //i - .io_cpu_writeBack_fence_SI (_zz_240 ), //i - .io_cpu_writeBack_fence_PW (_zz_241 ), //i - .io_cpu_writeBack_fence_PR (_zz_242 ), //i - .io_cpu_writeBack_fence_PO (_zz_243 ), //i - .io_cpu_writeBack_fence_PI (_zz_244 ), //i - .io_cpu_writeBack_fence_FM (_zz_245[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_213 ), //i + .io_cpu_writeBack_fence_SR (_zz_214 ), //i + .io_cpu_writeBack_fence_SO (_zz_215 ), //i + .io_cpu_writeBack_fence_SI (_zz_216 ), //i + .io_cpu_writeBack_fence_PW (_zz_217 ), //i + .io_cpu_writeBack_fence_PR (_zz_218 ), //i + .io_cpu_writeBack_fence_PO (_zz_219 ), //i + .io_cpu_writeBack_fence_PI (_zz_220 ), //i + .io_cpu_writeBack_fence_FM (_zz_221[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_246 ), //i + .io_cpu_flush_valid (_zz_222 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_247 ), //i + .io_mem_cmd_ready (_zz_223 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1892,18 +1852,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_395) + case(_zz_371) 2'b00 : begin - _zz_250 = DBusCachedPlugin_redoBranch_payload; + _zz_226 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_250 = CsrPlugin_jumpInterface_payload; + _zz_226 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_250 = BranchPlugin_jumpInterface_payload; + _zz_226 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_250 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_226 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2658,7 +2618,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_294) + $signed(_zz_302)); + assign memory_MUL_LOW = ($signed(_zz_270) + $signed(_zz_278)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2666,42 +2626,42 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_304; + assign execute_SHIFT_RIGHT = _zz_280; assign execute_REGFILE_WRITE_DATA = _zz_109; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_230[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_206[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_306[0]; - assign decode_IS_RS1_SIGNED = _zz_307[0]; - assign decode_IS_DIV = _zz_308[0]; + assign decode_IS_RS2_SIGNED = _zz_282[0]; + assign decode_IS_RS1_SIGNED = _zz_283[0]; + assign decode_IS_DIV = _zz_284[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_309[0]; + assign decode_IS_MUL = _zz_285[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_310[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_286[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_311[0]; + assign decode_IS_CSR = _zz_287[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_312[0]; - assign decode_MEMORY_MANAGMENT = _zz_313[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_288[0]; + assign decode_MEMORY_MANAGMENT = _zz_289[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_314[0]; + assign decode_MEMORY_WR = _zz_290[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_315[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_316[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_291[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_292[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2715,7 +2675,7 @@ module VexRiscv ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_317[0]; + assign decode_IS_EBREAK = _zz_293[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2756,11 +2716,11 @@ module VexRiscv ( assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_COND_RESULT = _zz_131; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_318[0]; - assign decode_RS1_USE = _zz_319[0]; + assign decode_RS2_USE = _zz_294[0]; + assign decode_RS1_USE = _zz_295[0]; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_251)begin + if(_zz_227)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2778,21 +2738,21 @@ module VexRiscv ( decode_RS2 = _zz_122; end end - if(_zz_252)begin - if(_zz_253)begin + if(_zz_228)begin + if(_zz_229)begin if(_zz_124)begin decode_RS2 = _zz_57; end end end - if(_zz_254)begin + if(_zz_230)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_126)begin decode_RS2 = _zz_38; end end end - if(_zz_255)begin + if(_zz_231)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_128)begin decode_RS2 = _zz_37; @@ -2808,21 +2768,21 @@ module VexRiscv ( decode_RS1 = _zz_122; end end - if(_zz_252)begin - if(_zz_253)begin + if(_zz_228)begin + if(_zz_229)begin if(_zz_123)begin decode_RS1 = _zz_57; end end end - if(_zz_254)begin + if(_zz_230)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_125)begin decode_RS1 = _zz_38; end end end - if(_zz_255)begin + if(_zz_231)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_127)begin decode_RS1 = _zz_37; @@ -2849,7 +2809,7 @@ module VexRiscv ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_256)begin + if(_zz_232)begin _zz_38 = memory_DivPlugin_div_result; end end @@ -2862,8 +2822,8 @@ module VexRiscv ( assign _zz_41 = execute_PC; assign execute_SRC2_CTRL = _zz_42; assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_320[0]; - assign decode_SRC_ADD_ZERO = _zz_321[0]; + assign decode_SRC_USE_SUB_LESS = _zz_296[0]; + assign decode_SRC_ADD_ZERO = _zz_297[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_44; @@ -2881,25 +2841,25 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_322[0]; + decode_REGFILE_WRITE_VALID = _zz_298[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_372) == 32'h00000003),{(_zz_373 == _zz_374),{_zz_375,{_zz_376,_zz_377}}}}}}} != 22'h0); always @ (*) begin _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_293) + case(_zz_269) 2'b00 : begin - _zz_57 = _zz_368; + _zz_57 = _zz_344; end default : begin - _zz_57 = _zz_369; + _zz_57 = _zz_345; end endcase end @@ -2918,32 +2878,32 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_323[0]; - assign decode_FLUSH_ALL = _zz_324[0]; + assign decode_MEMORY_ENABLE = _zz_299[0]; + assign decode_FLUSH_ALL = _zz_300[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_257)begin + if(_zz_233)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_258)begin + if(_zz_234)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_259)begin + if(_zz_235)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_260)begin + if(_zz_236)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2972,7 +2932,7 @@ module VexRiscv ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_179) + case(_zz_163) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2996,7 +2956,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_261)begin + if(_zz_237)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -3010,22 +2970,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(_zz_237)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_246 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_222 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_262)begin + if(_zz_238)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_251)begin + if(_zz_227)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3040,14 +3000,14 @@ module VexRiscv ( if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_263)begin + if(_zz_239)begin execute_arbitration_haltByOther = 1'b1; end end always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_264)begin + if(_zz_240)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -3057,8 +3017,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_263)begin - if(_zz_265)begin + if(_zz_239)begin + if(_zz_241)begin execute_arbitration_flushIt = 1'b1; end end @@ -3069,11 +3029,11 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_264)begin + if(_zz_240)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_263)begin - if(_zz_265)begin + if(_zz_239)begin + if(_zz_241)begin execute_arbitration_flushNext = 1'b1; end end @@ -3086,7 +3046,7 @@ module VexRiscv ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_256)begin + if(_zz_232)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3145,10 +3105,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_266)begin + if(_zz_242)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_267)begin + if(_zz_243)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3162,21 +3122,21 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_266)begin + if(_zz_242)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_267)begin + if(_zz_243)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_263)begin - if(_zz_265)begin + if(_zz_239)begin + if(_zz_241)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_268)begin + if(_zz_244)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3197,7 +3157,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_262)begin + if(_zz_238)begin CsrPlugin_inWfi = 1'b1; end end @@ -3211,21 +3171,21 @@ module VexRiscv ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_266)begin + if(_zz_242)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_267)begin + if(_zz_243)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_266)begin + if(_zz_242)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_267)begin - case(_zz_269) + if(_zz_243)begin + case(_zz_245) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3259,11 +3219,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_63 = (_zz_62 & (~ _zz_325)); + assign _zz_63 = (_zz_62 & (~ _zz_301)); assign _zz_64 = _zz_63[3]; assign _zz_65 = (_zz_63[1] || _zz_64); assign _zz_66 = (_zz_63[2] || _zz_64); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_250; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_226; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3283,7 +3243,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_327); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_303); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3375,7 +3335,7 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_179) + case(_zz_163) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3387,7 +3347,7 @@ module VexRiscv ( endcase end - assign _zz_76 = _zz_328[11]; + assign _zz_76 = _zz_304[11]; always @ (*) begin _zz_77[18] = _zz_76; _zz_77[17] = _zz_76; @@ -3411,13 +3371,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_329[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_305[31])); if(_zz_82)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_78 = _zz_330[19]; + assign _zz_78 = _zz_306[19]; always @ (*) begin _zz_79[10] = _zz_78; _zz_79[9] = _zz_78; @@ -3432,7 +3392,7 @@ module VexRiscv ( _zz_79[0] = _zz_78; end - assign _zz_80 = _zz_331[11]; + assign _zz_80 = _zz_307[11]; always @ (*) begin _zz_81[18] = _zz_80; _zz_81[17] = _zz_80; @@ -3458,16 +3418,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_82 = _zz_332[1]; + _zz_82 = _zz_308[1]; end default : begin - _zz_82 = _zz_333[1]; + _zz_82 = _zz_309[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_83 = _zz_334[19]; + assign _zz_83 = _zz_310[19]; always @ (*) begin _zz_84[10] = _zz_83; _zz_84[9] = _zz_83; @@ -3482,7 +3442,7 @@ module VexRiscv ( _zz_84[0] = _zz_83; end - assign _zz_85 = _zz_335[11]; + assign _zz_85 = _zz_311[11]; always @ (*) begin _zz_86[18] = _zz_85; _zz_86[17] = _zz_85; @@ -3505,7 +3465,7 @@ module VexRiscv ( _zz_86[0] = _zz_85; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_414,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_415,_zz_416},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_390,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_391,_zz_392},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3514,52 +3474,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_222; + assign _zz_197 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_198 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_199 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_198; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_225 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_226 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_227 = (CsrPlugin_privilege == 2'b00); + assign _zz_201 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_202 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_203 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_260)begin + if(_zz_236)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_258)begin + if(_zz_234)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_228 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_258)begin - _zz_228 = 1'b1; + _zz_204 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_234)begin + _zz_204 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_259)begin + if(_zz_235)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_257)begin + if(_zz_233)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_259)begin + if(_zz_235)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_257)begin + if(_zz_233)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3569,9 +3529,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_220 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_196 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_247 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_223 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3598,8 +3558,8 @@ module VexRiscv ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_229 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_230 = execute_SRC_ADD; + assign _zz_205 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_206 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3614,27 +3574,27 @@ module VexRiscv ( endcase end - assign _zz_246 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_231 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_232 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_231; + assign _zz_222 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_207 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_208 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_207; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_232; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_208; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_233 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_209 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_233 = 1'b1; + _zz_209 = 1'b1; end end - assign _zz_234 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_235 = (CsrPlugin_privilege == 2'b00); - assign _zz_236 = writeBack_REGFILE_WRITE_DATA; + assign _zz_210 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_211 = (CsrPlugin_privilege == 2'b00); + assign _zz_212 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_270)begin + if(_zz_246)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3644,7 +3604,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_270)begin + if(_zz_246)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3663,15 +3623,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_270)begin + if(_zz_246)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_312}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_313}; end end end @@ -3744,7 +3704,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_291) + case(_zz_267) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_91; end @@ -3780,7 +3740,7 @@ module VexRiscv ( assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_94 = {(((decode_INSTRUCTION & _zz_417) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}; + assign _zz_94 = {(((decode_INSTRUCTION & _zz_393) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_394 != _zz_395),{_zz_396,{_zz_397,_zz_398}}}}}}; assign _zz_100 = _zz_94[2 : 1]; assign _zz_56 = _zz_100; assign _zz_101 = _zz_94[7 : 6]; @@ -3802,8 +3762,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_248; - assign decode_RegFilePlugin_rs2Data = _zz_249; + assign decode_RegFilePlugin_rs1Data = _zz_224; + assign decode_RegFilePlugin_rs2Data = _zz_225; always @ (*) begin lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); if(_zz_108)begin @@ -3845,7 +3805,7 @@ module VexRiscv ( _zz_109 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_109 = {31'd0, _zz_338}; + _zz_109 = {31'd0, _zz_314}; end default : begin _zz_109 = execute_SRC_ADD_SUB; @@ -3859,18 +3819,18 @@ module VexRiscv ( _zz_110 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_110 = {29'd0, _zz_339}; + _zz_110 = {29'd0, _zz_315}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_110 = {27'd0, _zz_340}; + _zz_110 = {27'd0, _zz_316}; end endcase end - assign _zz_111 = _zz_341[11]; + assign _zz_111 = _zz_317[11]; always @ (*) begin _zz_112[19] = _zz_111; _zz_112[18] = _zz_111; @@ -3894,7 +3854,7 @@ module VexRiscv ( _zz_112[0] = _zz_111; end - assign _zz_113 = _zz_342[11]; + assign _zz_113 = _zz_318[11]; always @ (*) begin _zz_114[19] = _zz_113; _zz_114[18] = _zz_113; @@ -3936,7 +3896,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_343; + execute_SrcPlugin_addSub = _zz_319; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -4017,22 +3977,22 @@ module VexRiscv ( always @ (*) begin _zz_118 = 1'b0; - if(_zz_271)begin - if(_zz_272)begin + if(_zz_247)begin + if(_zz_248)begin if(_zz_123)begin _zz_118 = 1'b1; end end end - if(_zz_273)begin - if(_zz_274)begin + if(_zz_249)begin + if(_zz_250)begin if(_zz_125)begin _zz_118 = 1'b1; end end end - if(_zz_275)begin - if(_zz_276)begin + if(_zz_251)begin + if(_zz_252)begin if(_zz_127)begin _zz_118 = 1'b1; end @@ -4045,22 +4005,22 @@ module VexRiscv ( always @ (*) begin _zz_119 = 1'b0; - if(_zz_271)begin - if(_zz_272)begin + if(_zz_247)begin + if(_zz_248)begin if(_zz_124)begin _zz_119 = 1'b1; end end end - if(_zz_273)begin - if(_zz_274)begin + if(_zz_249)begin + if(_zz_250)begin if(_zz_126)begin _zz_119 = 1'b1; end end end - if(_zz_275)begin - if(_zz_276)begin + if(_zz_251)begin + if(_zz_252)begin if(_zz_128)begin _zz_119 = 1'b1; end @@ -4108,7 +4068,7 @@ module VexRiscv ( endcase end - assign _zz_132 = _zz_350[11]; + assign _zz_132 = _zz_326[11]; always @ (*) begin _zz_133[19] = _zz_132; _zz_133[18] = _zz_132; @@ -4132,7 +4092,7 @@ module VexRiscv ( _zz_133[0] = _zz_132; end - assign _zz_134 = _zz_351[19]; + assign _zz_134 = _zz_327[19]; always @ (*) begin _zz_135[10] = _zz_134; _zz_135[9] = _zz_134; @@ -4147,7 +4107,7 @@ module VexRiscv ( _zz_135[0] = _zz_134; end - assign _zz_136 = _zz_352[11]; + assign _zz_136 = _zz_328[11]; always @ (*) begin _zz_137[18] = _zz_136; _zz_137[17] = _zz_136; @@ -4173,13 +4133,13 @@ module VexRiscv ( always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_138 = (_zz_353[1] ^ execute_RS1[1]); + _zz_138 = (_zz_329[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_138 = _zz_354[1]; + _zz_138 = _zz_330[1]; end default : begin - _zz_138 = _zz_355[1]; + _zz_138 = _zz_331[1]; end endcase end @@ -4196,7 +4156,7 @@ module VexRiscv ( endcase end - assign _zz_139 = _zz_356[11]; + assign _zz_139 = _zz_332[11]; always @ (*) begin _zz_140[19] = _zz_139; _zz_140[18] = _zz_139; @@ -4226,15 +4186,15 @@ module VexRiscv ( execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_594,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_595,_zz_596},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_570,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_571,_zz_572},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_359}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_335}; end end endcase end - assign _zz_141 = _zz_357[19]; + assign _zz_141 = _zz_333[19]; always @ (*) begin _zz_142[10] = _zz_141; _zz_142[9] = _zz_141; @@ -4249,7 +4209,7 @@ module VexRiscv ( _zz_142[0] = _zz_141; end - assign _zz_143 = _zz_358[11]; + assign _zz_143 = _zz_334[11]; always @ (*) begin _zz_144[18] = _zz_143; _zz_144[17] = _zz_143; @@ -4298,12 +4258,12 @@ module VexRiscv ( assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_149 = _zz_360[0]; + assign _zz_149 = _zz_336[0]; assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_151 = _zz_362[0]; + assign _zz_151 = _zz_338[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_261)begin + if(_zz_237)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4313,7 +4273,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_264)begin + if(_zz_240)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -4482,70 +4442,6 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2822)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2824)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2826)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2828)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2830)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2832)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2834)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end if(execute_CsrPlugin_csr_3008)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4554,7 +4450,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_277)begin + if(_zz_253)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4573,20 +4469,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_278)begin + if(_zz_254)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_279)begin + if(_zz_255)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_278)begin + if(_zz_254)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_279)begin + if(_zz_255)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4601,14 +4497,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_277)begin + if(_zz_253)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_277)begin + if(_zz_253)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4617,7 +4513,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_292) + case(_zz_268) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4630,49 +4526,49 @@ module VexRiscv ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_364; + assign execute_CfuPlugin_functionsIds_0 = _zz_340; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_168 = _zz_365[7]; - always @ (*) begin - _zz_169[23] = _zz_168; - _zz_169[22] = _zz_168; - _zz_169[21] = _zz_168; - _zz_169[20] = _zz_168; - _zz_169[19] = _zz_168; - _zz_169[18] = _zz_168; - _zz_169[17] = _zz_168; - _zz_169[16] = _zz_168; - _zz_169[15] = _zz_168; - _zz_169[14] = _zz_168; - _zz_169[13] = _zz_168; - _zz_169[12] = _zz_168; - _zz_169[11] = _zz_168; - _zz_169[10] = _zz_168; - _zz_169[9] = _zz_168; - _zz_169[8] = _zz_168; - _zz_169[7] = _zz_168; - _zz_169[6] = _zz_168; - _zz_169[5] = _zz_168; - _zz_169[4] = _zz_168; - _zz_169[3] = _zz_168; - _zz_169[2] = _zz_168; - _zz_169[1] = _zz_168; - _zz_169[0] = _zz_168; + assign _zz_152 = _zz_341[7]; + always @ (*) begin + _zz_153[23] = _zz_152; + _zz_153[22] = _zz_152; + _zz_153[21] = _zz_152; + _zz_153[20] = _zz_152; + _zz_153[19] = _zz_152; + _zz_153[18] = _zz_152; + _zz_153[17] = _zz_152; + _zz_153[16] = _zz_152; + _zz_153[15] = _zz_152; + _zz_153[14] = _zz_152; + _zz_153[13] = _zz_152; + _zz_153[12] = _zz_152; + _zz_153[11] = _zz_152; + _zz_153[10] = _zz_152; + _zz_153[9] = _zz_152; + _zz_153[8] = _zz_152; + _zz_153[7] = _zz_152; + _zz_153[6] = _zz_152; + _zz_153[5] = _zz_152; + _zz_153[4] = _zz_152; + _zz_153[3] = _zz_152; + _zz_153[2] = _zz_152; + _zz_153[1] = _zz_152; + _zz_153[0] = _zz_152; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_170 = execute_RS2; + _zz_154 = execute_RS2; end default : begin - _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 24]}; + _zz_154 = {_zz_153,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_154; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4698,7 +4594,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_280) + case(_zz_256) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4712,7 +4608,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_280) + case(_zz_256) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4731,12 +4627,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_366) + $signed(_zz_367)); + assign writeBack_MulPlugin_result = ($signed(_zz_342) + $signed(_zz_343)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_256)begin - if(_zz_281)begin + if(_zz_232)begin + if(_zz_257)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4744,7 +4640,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_282)begin + if(_zz_258)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4755,32 +4651,32 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_347); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_372); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_373 : _zz_374); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_375[31:0]; - assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_155 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_155[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_348); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_349 : _zz_350); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_351[31:0]; + assign _zz_156 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_157 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_158 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_175[31 : 0] = execute_RS1; + _zz_159[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_159[31 : 0] = execute_RS1; end - assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_177 != 32'h0); + assign _zz_161 = (_zz_160 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_161 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_283) + case(_zz_259) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4794,7 +4690,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_178))begin + if((! _zz_162))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4806,7 +4702,7 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_283) + case(_zz_259) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4873,7 +4769,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_179) + case(_zz_163) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4883,272 +4779,216 @@ module VexRiscv ( end always @ (*) begin - _zz_180 = 32'h0; + _zz_164 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_180[12 : 0] = 13'h1000; - _zz_180[25 : 20] = 6'h20; + _zz_164[12 : 0] = 13'h1000; + _zz_164[25 : 20] = 6'h20; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_165 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_181[3 : 0] = 4'b1011; + _zz_165[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_166 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_182[4 : 0] = 5'h16; + _zz_166[4 : 0] = 5'h16; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_167 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_183[5 : 0] = 6'h21; + _zz_167[5 : 0] = 6'h21; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_168 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_184[31 : 30] = CsrPlugin_misa_base; - _zz_184[25 : 0] = CsrPlugin_misa_extensions; + _zz_168[31 : 30] = CsrPlugin_misa_base; + _zz_168[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_169 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_169[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_169[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_169[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_170 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_186[11 : 11] = CsrPlugin_mip_MEIP; - _zz_186[7 : 7] = CsrPlugin_mip_MTIP; - _zz_186[3 : 3] = CsrPlugin_mip_MSIP; + _zz_170[11 : 11] = CsrPlugin_mip_MEIP; + _zz_170[7 : 7] = CsrPlugin_mip_MTIP; + _zz_170[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_171 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_187[11 : 11] = CsrPlugin_mie_MEIE; - _zz_187[7 : 7] = CsrPlugin_mie_MTIE; - _zz_187[3 : 3] = CsrPlugin_mie_MSIE; + _zz_171[11 : 11] = CsrPlugin_mie_MEIE; + _zz_171[7 : 7] = CsrPlugin_mie_MTIE; + _zz_171[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_188[31 : 2] = CsrPlugin_mtvec_base; - _zz_188[1 : 0] = CsrPlugin_mtvec_mode; + _zz_172[31 : 2] = CsrPlugin_mtvec_base; + _zz_172[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_189[31 : 0] = CsrPlugin_mepc; + _zz_173[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_190[31 : 0] = CsrPlugin_mscratch; + _zz_174[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_175[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_175[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_192[31 : 0] = CsrPlugin_mtval; + _zz_176[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_177[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_178[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_179[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_180[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_181[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_182[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_183[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; - end - end - - always @ (*) begin - _zz_201 = 32'h0; - if(execute_CsrPlugin_csr_2820)begin - _zz_201[31 : 0] = _zz_152; - end - end - - always @ (*) begin - _zz_202 = 32'h0; - if(execute_CsrPlugin_csr_2822)begin - _zz_202[31 : 0] = _zz_154; + _zz_184[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_203 = 32'h0; - if(execute_CsrPlugin_csr_2824)begin - _zz_203[31 : 0] = _zz_156; - end - end - - always @ (*) begin - _zz_204 = 32'h0; - if(execute_CsrPlugin_csr_2826)begin - _zz_204[31 : 0] = _zz_158; - end - end - - always @ (*) begin - _zz_205 = 32'h0; - if(execute_CsrPlugin_csr_2828)begin - _zz_205[31 : 0] = _zz_160; - end - end - - always @ (*) begin - _zz_206 = 32'h0; - if(execute_CsrPlugin_csr_2830)begin - _zz_206[31 : 0] = _zz_162; - end - end - - always @ (*) begin - _zz_207 = 32'h0; - if(execute_CsrPlugin_csr_2832)begin - _zz_207[31 : 0] = _zz_164; - end - end - - always @ (*) begin - _zz_208 = 32'h0; - if(execute_CsrPlugin_csr_2834)begin - _zz_208[31 : 0] = _zz_166; - end - end - - always @ (*) begin - _zz_209 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_209[31 : 0] = _zz_176; + _zz_185[31 : 0] = _zz_160; end end always @ (*) begin - _zz_210 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_210[31 : 0] = _zz_177; + _zz_186[31 : 0] = _zz_161; end end - assign execute_CsrPlugin_readData = (((((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_597 | _zz_184) | (_zz_185 | _zz_186))) | (((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194)))) | ((((_zz_195 | _zz_196) | (_zz_197 | _zz_198)) | ((_zz_199 | _zz_200) | (_zz_201 | _zz_202))) | (((_zz_203 | _zz_204) | (_zz_205 | _zz_206)) | ((_zz_207 | _zz_208) | (_zz_209 | _zz_210))))); - assign iBusWishbone_ADR = {_zz_392,_zz_211}; - assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_164 | _zz_165) | (_zz_166 | _zz_167)) | ((_zz_573 | _zz_168) | (_zz_169 | _zz_170))) | (((_zz_171 | _zz_172) | (_zz_173 | _zz_174)) | ((_zz_175 | _zz_176) | (_zz_177 | _zz_178)))) | (((_zz_179 | _zz_180) | (_zz_181 | _zz_182)) | ((_zz_183 | _zz_184) | (_zz_185 | _zz_186)))); + assign iBusWishbone_ADR = {_zz_368,_zz_187}; + assign iBusWishbone_CTI = ((_zz_187 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_284)begin + if(_zz_260)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_284)begin + if(_zz_260)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_212; + assign iBus_rsp_valid = _zz_188; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_218 = (dBus_cmd_payload_length != 3'b000); - assign _zz_214 = dBus_cmd_valid; - assign _zz_216 = dBus_cmd_payload_wr; - assign _zz_217 = (_zz_213 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_215 && (_zz_216 || _zz_217)); - assign dBusWishbone_ADR = ((_zz_218 ? {{dBus_cmd_payload_address[31 : 5],_zz_213},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_218 ? (_zz_217 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_194 = (dBus_cmd_payload_length != 3'b000); + assign _zz_190 = dBus_cmd_valid; + assign _zz_192 = dBus_cmd_payload_wr; + assign _zz_193 = (_zz_189 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_191 && (_zz_192 || _zz_193)); + assign dBusWishbone_ADR = ((_zz_194 ? {{dBus_cmd_payload_address[31 : 5],_zz_189},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_194 ? (_zz_193 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_216 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_216; + assign dBusWishbone_SEL = (_zz_192 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_192; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_215 = (_zz_214 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_214; - assign dBusWishbone_STB = _zz_214; - assign dBus_rsp_valid = _zz_219; + assign _zz_191 = (_zz_190 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_190; + assign dBusWishbone_STB = _zz_190; + assign dBus_rsp_valid = _zz_195; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5195,16 +5035,16 @@ module VexRiscv ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_176 <= 32'h0; + _zz_160 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_179 <= 3'b000; + _zz_163 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_211 <= 3'b000; - _zz_212 <= 1'b0; - _zz_213 <= 3'b000; - _zz_219 <= 1'b0; + _zz_187 <= 3'b000; + _zz_188 <= 1'b0; + _zz_189 <= 3'b000; + _zz_195 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5285,7 +5125,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_285)begin + if(_zz_261)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5317,14 +5157,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_286)begin - if(_zz_287)begin + if(_zz_262)begin + if(_zz_263)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_288)begin + if(_zz_264)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_289)begin + if(_zz_265)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5349,7 +5189,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_266)begin + if(_zz_242)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5360,8 +5200,8 @@ module VexRiscv ( end endcase end - if(_zz_267)begin - case(_zz_269) + if(_zz_243)begin + case(_zz_245) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5387,7 +5227,7 @@ module VexRiscv ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_290)begin + if(_zz_266)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; @@ -5412,25 +5252,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_179) + case(_zz_163) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_179 <= 3'b001; + _zz_163 <= 3'b001; end end 3'b001 : begin - _zz_179 <= 3'b010; + _zz_163 <= 3'b010; end 3'b010 : begin - _zz_179 <= 3'b011; + _zz_163 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_179 <= 3'b100; + _zz_163 <= 3'b100; end end 3'b100 : begin - _zz_179 <= 3'b000; + _zz_163 <= 3'b000; end default : begin end @@ -5444,35 +5284,35 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_385[0]; - CsrPlugin_mstatus_MIE <= _zz_386[0]; + CsrPlugin_mstatus_MPIE <= _zz_361[0]; + CsrPlugin_mstatus_MIE <= _zz_362[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_388[0]; - CsrPlugin_mie_MTIE <= _zz_389[0]; - CsrPlugin_mie_MSIE <= _zz_390[0]; + CsrPlugin_mie_MEIE <= _zz_364[0]; + CsrPlugin_mie_MTIE <= _zz_365[0]; + CsrPlugin_mie_MSIE <= _zz_366[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_284)begin + if(_zz_260)begin if(iBusWishbone_ACK)begin - _zz_211 <= (_zz_211 + 3'b001); + _zz_187 <= (_zz_187 + 3'b001); end end - _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_214 && _zz_215))begin - _zz_213 <= (_zz_213 + 3'b001); - if(_zz_217)begin - _zz_213 <= 3'b000; + _zz_188 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_190 && _zz_191))begin + _zz_189 <= (_zz_189 + 3'b001); + if(_zz_193)begin + _zz_189 <= 3'b000; end end - _zz_219 <= ((_zz_214 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_195 <= ((_zz_190 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5486,7 +5326,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_285)begin + if(_zz_261)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5513,11 +5353,11 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_261)begin + if(_zz_237)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(_zz_264)begin + if(_zz_240)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end @@ -5529,21 +5369,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_286)begin - if(_zz_287)begin + if(_zz_262)begin + if(_zz_263)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_288)begin + if(_zz_264)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_289)begin + if(_zz_265)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_266)begin + if(_zz_242)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5557,31 +5397,7 @@ module VexRiscv ( end endcase end - if(_zz_153[0])begin - _zz_152 <= (_zz_152 + 32'h00000001); - end - if(_zz_155[0])begin - _zz_154 <= (_zz_154 + 32'h00000001); - end - if(_zz_157[0])begin - _zz_156 <= (_zz_156 + 32'h00000001); - end - if(_zz_159[0])begin - _zz_158 <= (_zz_158 + 32'h00000001); - end - if(_zz_161[0])begin - _zz_160 <= (_zz_160 + 32'h00000001); - end - if(_zz_163[0])begin - _zz_162 <= (_zz_162 + 32'h00000001); - end - if(_zz_165[0])begin - _zz_164 <= (_zz_164 + 32'h00000001); - end - if(_zz_167[0])begin - _zz_166 <= (_zz_166 + 32'h00000001); - end - if(_zz_290)begin + if(_zz_266)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5591,20 +5407,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_256)begin - if(_zz_281)begin + if(_zz_232)begin + if(_zz_257)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_376[31:0]; + memory_DivPlugin_div_result <= _zz_352[31:0]; end end end - if(_zz_282)begin + if(_zz_258)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_382); - memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_384); - memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_158 ? (~ _zz_159) : _zz_159) + _zz_358); + memory_DivPlugin_rs2 <= ((_zz_157 ? (~ execute_RS2) : execute_RS2) + _zz_360); + memory_DivPlugin_div_needRevert <= ((_zz_158 ^ (_zz_157 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5865,54 +5681,6 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); - end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end @@ -5921,7 +5689,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_387[0]; + CsrPlugin_mip_MSIP <= _zz_363[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5942,7 +5710,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_391[0]; + CsrPlugin_mcause_interrupt <= _zz_367[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5971,86 +5739,6 @@ module VexRiscv ( CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end end - if(execute_CsrPlugin_csr_2820)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2822)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2824)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2826)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2828)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2830)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2832)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2834)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; - end - end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end @@ -6065,8 +5753,8 @@ module VexRiscv ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_57; end - _zz_178 <= debug_bus_cmd_payload_address[2]; - if(_zz_263)begin + _zz_162 <= debug_bus_cmd_payload_address[2]; + if(_zz_239)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -6084,7 +5772,7 @@ module VexRiscv ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_283) + case(_zz_259) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -6112,13 +5800,13 @@ module VexRiscv ( end endcase end - if(_zz_263)begin - if(_zz_265)begin + if(_zz_239)begin + if(_zz_241)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_268)begin + if(_zz_244)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v new file mode 100644 index 0000000..b41f53f --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v @@ -0,0 +1,7159 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : 9c3529c14328ee22a18ec0f74e66ca59de7346c3 + + +`define Input2Kind_defaultEncoding_type [0:0] +`define Input2Kind_defaultEncoding_RS 1'b0 +`define Input2Kind_defaultEncoding_IMM_I 1'b1 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input CfuPlugin_bus_rsp_payload_response_ok, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_217; + wire _zz_218; + wire _zz_219; + wire _zz_220; + wire _zz_221; + wire _zz_222; + wire _zz_223; + wire _zz_224; + reg _zz_225; + wire _zz_226; + wire [31:0] _zz_227; + wire _zz_228; + wire [31:0] _zz_229; + reg _zz_230; + wire _zz_231; + wire _zz_232; + wire [31:0] _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire [3:0] _zz_242; + wire _zz_243; + wire _zz_244; + reg [31:0] _zz_245; + reg [31:0] _zz_246; + reg [31:0] _zz_247; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire _zz_255; + wire _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire [1:0] _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire [1:0] _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire [1:0] _zz_284; + wire _zz_285; + wire [1:0] _zz_286; + wire [51:0] _zz_287; + wire [51:0] _zz_288; + wire [51:0] _zz_289; + wire [32:0] _zz_290; + wire [51:0] _zz_291; + wire [49:0] _zz_292; + wire [51:0] _zz_293; + wire [49:0] _zz_294; + wire [51:0] _zz_295; + wire [32:0] _zz_296; + wire [31:0] _zz_297; + wire [32:0] _zz_298; + wire [0:0] _zz_299; + wire [0:0] _zz_300; + wire [0:0] _zz_301; + wire [0:0] _zz_302; + wire [0:0] _zz_303; + wire [0:0] _zz_304; + wire [0:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [3:0] _zz_317; + wire [2:0] _zz_318; + wire [31:0] _zz_319; + wire [11:0] _zz_320; + wire [31:0] _zz_321; + wire [19:0] _zz_322; + wire [11:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [19:0] _zz_326; + wire [11:0] _zz_327; + wire [2:0] _zz_328; + wire [2:0] _zz_329; + wire [0:0] _zz_330; + wire [2:0] _zz_331; + wire [4:0] _zz_332; + wire [11:0] _zz_333; + wire [11:0] _zz_334; + wire [31:0] _zz_335; + wire [31:0] _zz_336; + wire [31:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [31:0] _zz_340; + wire [31:0] _zz_341; + wire [11:0] _zz_342; + wire [19:0] _zz_343; + wire [11:0] _zz_344; + wire [31:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [11:0] _zz_348; + wire [19:0] _zz_349; + wire [11:0] _zz_350; + wire [2:0] _zz_351; + wire [1:0] _zz_352; + wire [1:0] _zz_353; + wire [1:0] _zz_354; + wire [1:0] _zz_355; + wire [9:0] _zz_356; + wire [7:0] _zz_357; + wire [65:0] _zz_358; + wire [65:0] _zz_359; + wire [31:0] _zz_360; + wire [31:0] _zz_361; + wire [0:0] _zz_362; + wire [5:0] _zz_363; + wire [32:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire [32:0] _zz_367; + wire [32:0] _zz_368; + wire [32:0] _zz_369; + wire [32:0] _zz_370; + wire [0:0] _zz_371; + wire [32:0] _zz_372; + wire [0:0] _zz_373; + wire [32:0] _zz_374; + wire [0:0] _zz_375; + wire [31:0] _zz_376; + wire [0:0] _zz_377; + wire [0:0] _zz_378; + wire [0:0] _zz_379; + wire [0:0] _zz_380; + wire [0:0] _zz_381; + wire [0:0] _zz_382; + wire [0:0] _zz_383; + wire [26:0] _zz_384; + wire _zz_385; + wire _zz_386; + wire [1:0] _zz_387; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire _zz_391; + wire [0:0] _zz_392; + wire [14:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire [31:0] _zz_396; + wire _zz_397; + wire [0:0] _zz_398; + wire [8:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; + wire [31:0] _zz_402; + wire _zz_403; + wire [0:0] _zz_404; + wire [2:0] _zz_405; + wire _zz_406; + wire _zz_407; + wire _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire _zz_411; + wire _zz_412; + wire [0:0] _zz_413; + wire [26:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire [1:0] _zz_420; + wire [1:0] _zz_421; + wire _zz_422; + wire [0:0] _zz_423; + wire [21:0] _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire [31:0] _zz_427; + wire [31:0] _zz_428; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire [0:0] _zz_431; + wire [0:0] _zz_432; + wire [2:0] _zz_433; + wire [2:0] _zz_434; + wire _zz_435; + wire [0:0] _zz_436; + wire [18:0] _zz_437; + wire [31:0] _zz_438; + wire [31:0] _zz_439; + wire [31:0] _zz_440; + wire [31:0] _zz_441; + wire _zz_442; + wire _zz_443; + wire [31:0] _zz_444; + wire [31:0] _zz_445; + wire _zz_446; + wire [0:0] _zz_447; + wire [0:0] _zz_448; + wire _zz_449; + wire [0:0] _zz_450; + wire [15:0] _zz_451; + wire [31:0] _zz_452; + wire _zz_453; + wire _zz_454; + wire _zz_455; + wire [2:0] _zz_456; + wire [2:0] _zz_457; + wire _zz_458; + wire [0:0] _zz_459; + wire [12:0] _zz_460; + wire _zz_461; + wire _zz_462; + wire _zz_463; + wire [0:0] _zz_464; + wire [2:0] _zz_465; + wire _zz_466; + wire [5:0] _zz_467; + wire [5:0] _zz_468; + wire _zz_469; + wire [0:0] _zz_470; + wire [9:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; + wire [31:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; + wire _zz_477; + wire [0:0] _zz_478; + wire [0:0] _zz_479; + wire [31:0] _zz_480; + wire _zz_481; + wire [0:0] _zz_482; + wire [3:0] _zz_483; + wire [0:0] _zz_484; + wire [3:0] _zz_485; + wire [5:0] _zz_486; + wire [5:0] _zz_487; + wire _zz_488; + wire [0:0] _zz_489; + wire [7:0] _zz_490; + wire [31:0] _zz_491; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire [31:0] _zz_497; + wire [31:0] _zz_498; + wire [0:0] _zz_499; + wire [1:0] _zz_500; + wire _zz_501; + wire [0:0] _zz_502; + wire [1:0] _zz_503; + wire [0:0] _zz_504; + wire [3:0] _zz_505; + wire [0:0] _zz_506; + wire [0:0] _zz_507; + wire [1:0] _zz_508; + wire [1:0] _zz_509; + wire _zz_510; + wire [0:0] _zz_511; + wire [5:0] _zz_512; + wire [31:0] _zz_513; + wire [31:0] _zz_514; + wire _zz_515; + wire _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire _zz_520; + wire _zz_521; + wire [31:0] _zz_522; + wire [31:0] _zz_523; + wire _zz_524; + wire [0:0] _zz_525; + wire [1:0] _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; + wire _zz_529; + wire _zz_530; + wire [0:0] _zz_531; + wire [0:0] _zz_532; + wire _zz_533; + wire [0:0] _zz_534; + wire [3:0] _zz_535; + wire [31:0] _zz_536; + wire [31:0] _zz_537; + wire [31:0] _zz_538; + wire [31:0] _zz_539; + wire [31:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire _zz_543; + wire _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; + wire [0:0] _zz_549; + wire [2:0] _zz_550; + wire [0:0] _zz_551; + wire [0:0] _zz_552; + wire _zz_553; + wire [0:0] _zz_554; + wire [1:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire _zz_559; + wire _zz_560; + wire [31:0] _zz_561; + wire _zz_562; + wire [0:0] _zz_563; + wire [0:0] _zz_564; + wire [0:0] _zz_565; + wire [0:0] _zz_566; + wire [1:0] _zz_567; + wire [1:0] _zz_568; + wire [0:0] _zz_569; + wire [0:0] _zz_570; + wire [31:0] _zz_571; + wire [31:0] _zz_572; + wire [31:0] _zz_573; + wire [31:0] _zz_574; + wire [31:0] _zz_575; + wire [31:0] _zz_576; + wire _zz_577; + wire _zz_578; + wire _zz_579; + wire [31:0] _zz_580; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_1; + wire `Input2Kind_defaultEncoding_type _zz_2; + wire `Input2Kind_defaultEncoding_type _zz_3; + wire decode_CfuPlugin_CFU_ENABLE; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `AluCtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + reg _zz_30; + reg _zz_31; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_32; + wire execute_CfuPlugin_CFU_ENABLE; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_37; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_38; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_41; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; + wire [31:0] _zz_46; + wire _zz_47; + reg _zz_48; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `Input2Kind_defaultEncoding_type _zz_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; + wire `Src2CtrlEnum_defaultEncoding_type _zz_54; + wire `AluCtrlEnum_defaultEncoding_type _zz_55; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56; + reg [31:0] _zz_57; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_59; + reg [31:0] _zz_60; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + reg CfuPlugin_joinException_valid; + wire [3:0] CfuPlugin_joinException_payload_code; + wire [31:0] CfuPlugin_joinException_payload_badAddr; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_61; + wire [3:0] _zz_62; + wire _zz_63; + wire _zz_64; + wire _zz_65; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_66; + wire _zz_67; + wire _zz_68; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_69; + wire _zz_70; + reg _zz_71; + wire _zz_72; + reg _zz_73; + reg [31:0] _zz_74; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_75; + reg [18:0] _zz_76; + wire _zz_77; + reg [10:0] _zz_78; + wire _zz_79; + reg [18:0] _zz_80; + reg _zz_81; + wire _zz_82; + reg [10:0] _zz_83; + wire _zz_84; + reg [18:0] _zz_85; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_86; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_87; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_88; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_89; + reg [31:0] _zz_90; + wire _zz_91; + reg [31:0] _zz_92; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [33:0] _zz_93; + wire _zz_94; + wire _zz_95; + wire _zz_96; + wire _zz_97; + wire _zz_98; + wire `Src1CtrlEnum_defaultEncoding_type _zz_99; + wire `AluCtrlEnum_defaultEncoding_type _zz_100; + wire `Src2CtrlEnum_defaultEncoding_type _zz_101; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_102; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_103; + wire `BranchCtrlEnum_defaultEncoding_type _zz_104; + wire `EnvCtrlEnum_defaultEncoding_type _zz_105; + wire `Input2Kind_defaultEncoding_type _zz_106; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_107; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_108; + reg [31:0] _zz_109; + wire _zz_110; + reg [19:0] _zz_111; + wire _zz_112; + reg [19:0] _zz_113; + reg [31:0] _zz_114; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_115; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_116; + reg _zz_117; + reg _zz_118; + reg _zz_119; + reg [4:0] _zz_120; + reg [31:0] _zz_121; + wire _zz_122; + wire _zz_123; + wire _zz_124; + wire _zz_125; + wire _zz_126; + wire _zz_127; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_128; + reg _zz_129; + reg _zz_130; + wire _zz_131; + reg [19:0] _zz_132; + wire _zz_133; + reg [10:0] _zz_134; + wire _zz_135; + reg [18:0] _zz_136; + reg _zz_137; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_138; + reg [19:0] _zz_139; + wire _zz_140; + reg [10:0] _zz_141; + wire _zz_142; + reg [18:0] _zz_143; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_144; + wire _zz_145; + wire _zz_146; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_147; + wire _zz_148; + wire [1:0] _zz_149; + wire _zz_150; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_167; + reg [23:0] _zz_168; + reg [31:0] _zz_169; + wire memory_CfuPlugin_rsp_valid; + reg memory_CfuPlugin_rsp_ready; + wire memory_CfuPlugin_rsp_payload_response_ok; + wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_s2mPipe_rValid; + reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_170; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_171; + wire _zz_172; + wire _zz_173; + reg [32:0] _zz_174; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_175; + wire [31:0] _zz_176; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_2820; + reg execute_CsrPlugin_csr_2821; + reg execute_CsrPlugin_csr_2822; + reg execute_CsrPlugin_csr_2823; + reg execute_CsrPlugin_csr_2824; + reg execute_CsrPlugin_csr_2825; + reg execute_CsrPlugin_csr_2826; + reg execute_CsrPlugin_csr_2827; + reg execute_CsrPlugin_csr_2828; + reg execute_CsrPlugin_csr_2829; + reg execute_CsrPlugin_csr_2830; + reg execute_CsrPlugin_csr_2831; + reg execute_CsrPlugin_csr_2832; + reg execute_CsrPlugin_csr_2833; + reg execute_CsrPlugin_csr_2834; + reg execute_CsrPlugin_csr_2835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; + reg [31:0] _zz_199; + reg [31:0] _zz_200; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + reg [2:0] _zz_208; + reg _zz_209; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + reg _zz_216; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [39:0] _zz_10_string; + reg [31:0] _zz_11_string; + reg [31:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [71:0] _zz_17_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [39:0] _zz_20_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [23:0] _zz_23_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [63:0] _zz_26_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [95:0] _zz_29_string; + reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_32_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_33_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_34_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_35_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_36_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_39_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_40_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_42_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_43_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_44_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_45_string; + reg [39:0] _zz_49_string; + reg [39:0] _zz_50_string; + reg [31:0] _zz_51_string; + reg [71:0] _zz_52_string; + reg [39:0] _zz_53_string; + reg [23:0] _zz_54_string; + reg [63:0] _zz_55_string; + reg [95:0] _zz_56_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_58_string; + reg [95:0] _zz_99_string; + reg [63:0] _zz_100_string; + reg [23:0] _zz_101_string; + reg [39:0] _zz_102_string; + reg [71:0] _zz_103_string; + reg [31:0] _zz_104_string; + reg [39:0] _zz_105_string; + reg [39:0] _zz_106_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_248 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_249 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_250 = 1'b1; + assign _zz_251 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_252 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_254 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_255 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_256 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_257 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_260 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_264 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_265 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_266 = (1'b0 || (! 1'b1)); + assign _zz_267 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_268 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_270 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_271 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_272 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_273 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_274 = execute_INSTRUCTION[13 : 12]; + assign _zz_275 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_276 = (! memory_arbitration_isStuck); + assign _zz_277 = (iBus_cmd_valid || (_zz_208 != 3'b000)); + assign _zz_278 = (_zz_244 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_280 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_281 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_282 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_285 = execute_INSTRUCTION[13]; + assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); + assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); + assign _zz_289 = 52'h0; + assign _zz_290 = {1'b0,memory_MUL_LL}; + assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; + assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; + assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; + assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_297 = _zz_296[31 : 0]; + assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_299 = _zz_93[33 : 33]; + assign _zz_300 = _zz_93[32 : 32]; + assign _zz_301 = _zz_93[31 : 31]; + assign _zz_302 = _zz_93[30 : 30]; + assign _zz_303 = _zz_93[28 : 28]; + assign _zz_304 = _zz_93[25 : 25]; + assign _zz_305 = _zz_93[17 : 17]; + assign _zz_306 = _zz_93[16 : 16]; + assign _zz_307 = _zz_93[13 : 13]; + assign _zz_308 = _zz_93[12 : 12]; + assign _zz_309 = _zz_93[11 : 11]; + assign _zz_310 = _zz_93[15 : 15]; + assign _zz_311 = _zz_93[5 : 5]; + assign _zz_312 = _zz_93[3 : 3]; + assign _zz_313 = _zz_93[20 : 20]; + assign _zz_314 = _zz_93[10 : 10]; + assign _zz_315 = _zz_93[4 : 4]; + assign _zz_316 = _zz_93[0 : 0]; + assign _zz_317 = (_zz_61 - 4'b0001); + assign _zz_318 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_319 = {29'd0, _zz_318}; + assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_321 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_324 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_325 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_326 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_328 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_329 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_330 = execute_SRC_LESS; + assign _zz_331 = 3'b100; + assign _zz_332 = execute_INSTRUCTION[19 : 15]; + assign _zz_333 = execute_INSTRUCTION[31 : 20]; + assign _zz_334 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_335 = ($signed(_zz_336) + $signed(_zz_339)); + assign _zz_336 = ($signed(_zz_337) + $signed(_zz_338)); + assign _zz_337 = execute_SRC1; + assign _zz_338 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_339 = (execute_SRC_USE_SUB_LESS ? _zz_340 : _zz_341); + assign _zz_340 = 32'h00000001; + assign _zz_341 = 32'h0; + assign _zz_342 = execute_INSTRUCTION[31 : 20]; + assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_345 = {_zz_132,execute_INSTRUCTION[31 : 20]}; + assign _zz_346 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_347 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_348 = execute_INSTRUCTION[31 : 20]; + assign _zz_349 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_351 = 3'b100; + assign _zz_352 = (_zz_147 & (~ _zz_353)); + assign _zz_353 = (_zz_147 - 2'b01); + assign _zz_354 = (_zz_149 & (~ _zz_355)); + assign _zz_355 = (_zz_149 - 2'b01); + assign _zz_356 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_357 = execute_INSTRUCTION[31 : 24]; + assign _zz_358 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_359 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_360 = writeBack_MUL_LOW[31 : 0]; + assign _zz_361 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_362 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_363 = {5'd0, _zz_362}; + assign _zz_364 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_365 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_366 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_367 = {_zz_170,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_368 = _zz_369; + assign _zz_369 = _zz_370; + assign _zz_370 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_171) : _zz_171)} + _zz_372); + assign _zz_371 = memory_DivPlugin_div_needRevert; + assign _zz_372 = {32'd0, _zz_371}; + assign _zz_373 = _zz_173; + assign _zz_374 = {32'd0, _zz_373}; + assign _zz_375 = _zz_172; + assign _zz_376 = {31'd0, _zz_375}; + assign _zz_377 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_378 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_380 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_381 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_382 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_383 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_384 = (iBus_cmd_payload_address >>> 5); + assign _zz_385 = 1'b1; + assign _zz_386 = 1'b1; + assign _zz_387 = {_zz_65,_zz_64}; + assign _zz_388 = 32'h0000106f; + assign _zz_389 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_390 = 32'h00001073; + assign _zz_391 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_392 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_393 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_394) == 32'h00000003),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; + assign _zz_394 = 32'h0000207f; + assign _zz_395 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_396 = 32'h00000003; + assign _zz_397 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_398 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_399 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_400) == 32'h00005013),{(_zz_401 == _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; + assign _zz_400 = 32'hbc00707f; + assign _zz_401 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_402 = 32'h00001013; + assign _zz_403 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_405 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_406 = decode_INSTRUCTION[31]; + assign _zz_407 = decode_INSTRUCTION[31]; + assign _zz_408 = decode_INSTRUCTION[7]; + assign _zz_409 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_410 = 32'h02004020; + assign _zz_411 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_412 = (_zz_97 != 1'b0); + assign _zz_413 = (((decode_INSTRUCTION & _zz_415) == 32'h00000050) != 1'b0); + assign _zz_414 = {((_zz_416 == _zz_417) != 1'b0),{({_zz_418,_zz_419} != 2'b00),{(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}}}; + assign _zz_415 = 32'h00203050; + assign _zz_416 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_417 = 32'h00000050; + assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00001050); + assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00002050); + assign _zz_420 = {_zz_96,(_zz_427 == _zz_428)}; + assign _zz_421 = 2'b00; + assign _zz_422 = ((_zz_429 == _zz_430) != 1'b0); + assign _zz_423 = ({_zz_431,_zz_432} != 2'b00); + assign _zz_424 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; + assign _zz_425 = 32'h00001050; + assign _zz_426 = 32'h00002050; + assign _zz_427 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_428 = 32'h00000004; + assign _zz_429 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_430 = 32'h00000040; + assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h00005010); + assign _zz_432 = ((decode_INSTRUCTION & _zz_439) == 32'h00005020); + assign _zz_433 = {(_zz_440 == _zz_441),{_zz_442,_zz_443}}; + assign _zz_434 = 3'b000; + assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); + assign _zz_436 = (_zz_446 != 1'b0); + assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; + assign _zz_438 = 32'h00007034; + assign _zz_439 = 32'h02007064; + assign _zz_440 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_441 = 32'h40001010; + assign _zz_442 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_443 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_445 = 32'h00000024; + assign _zz_446 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_447 = ((decode_INSTRUCTION & _zz_452) == 32'h00002000); + assign _zz_448 = 1'b0; + assign _zz_449 = ({_zz_453,_zz_454} != 2'b00); + assign _zz_450 = (_zz_455 != 1'b0); + assign _zz_451 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; + assign _zz_452 = 32'h00003000; + assign _zz_453 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_454 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_455 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_456 = {_zz_97,{_zz_461,_zz_462}}; + assign _zz_457 = 3'b000; + assign _zz_458 = ({_zz_463,{_zz_464,_zz_465}} != 5'h0); + assign _zz_459 = (_zz_466 != 1'b0); + assign _zz_460 = {(_zz_467 != _zz_468),{_zz_469,{_zz_470,_zz_471}}}; + assign _zz_461 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); + assign _zz_462 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); + assign _zz_463 = ((decode_INSTRUCTION & _zz_474) == 32'h00002040); + assign _zz_464 = (_zz_475 == _zz_476); + assign _zz_465 = {_zz_477,{_zz_478,_zz_479}}; + assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000020); + assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; + assign _zz_468 = 6'h0; + assign _zz_469 = ({_zz_484,_zz_485} != 5'h0); + assign _zz_470 = (_zz_486 != _zz_487); + assign _zz_471 = {_zz_488,{_zz_489,_zz_490}}; + assign _zz_472 = 32'h00000034; + assign _zz_473 = 32'h00000064; + assign _zz_474 = 32'h00002040; + assign _zz_475 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_476 = 32'h00001040; + assign _zz_477 = ((decode_INSTRUCTION & _zz_491) == 32'h00000040); + assign _zz_478 = (_zz_492 == _zz_493); + assign _zz_479 = (_zz_494 == _zz_495); + assign _zz_480 = 32'h00000020; + assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00000008); + assign _zz_482 = (_zz_497 == _zz_498); + assign _zz_483 = {_zz_95,{_zz_499,_zz_500}}; + assign _zz_484 = _zz_95; + assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; + assign _zz_486 = {_zz_96,{_zz_504,_zz_505}}; + assign _zz_487 = 6'h0; + assign _zz_488 = ({_zz_506,_zz_507} != 2'b00); + assign _zz_489 = (_zz_508 != _zz_509); + assign _zz_490 = {_zz_510,{_zz_511,_zz_512}}; + assign _zz_491 = 32'h00000050; + assign _zz_492 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_493 = 32'h00000040; + assign _zz_494 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_495 = 32'h0; + assign _zz_496 = 32'h00000008; + assign _zz_497 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_498 = 32'h00000040; + assign _zz_499 = (_zz_513 == _zz_514); + assign _zz_500 = {_zz_515,_zz_516}; + assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00002010); + assign _zz_502 = (_zz_518 == _zz_519); + assign _zz_503 = {_zz_520,_zz_521}; + assign _zz_504 = (_zz_522 == _zz_523); + assign _zz_505 = {_zz_524,{_zz_525,_zz_526}}; + assign _zz_506 = _zz_95; + assign _zz_507 = (_zz_527 == _zz_528); + assign _zz_508 = {_zz_95,_zz_529}; + assign _zz_509 = 2'b00; + assign _zz_510 = (_zz_530 != 1'b0); + assign _zz_511 = (_zz_531 != _zz_532); + assign _zz_512 = {_zz_533,{_zz_534,_zz_535}}; + assign _zz_513 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_514 = 32'h00004020; + assign _zz_515 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); + assign _zz_516 = ((decode_INSTRUCTION & _zz_537) == 32'h00000020); + assign _zz_517 = 32'h00002030; + assign _zz_518 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_519 = 32'h00000010; + assign _zz_520 = ((decode_INSTRUCTION & _zz_538) == 32'h00002020); + assign _zz_521 = ((decode_INSTRUCTION & _zz_539) == 32'h00000020); + assign _zz_522 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_523 = 32'h00001010; + assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00002010); + assign _zz_525 = (_zz_541 == _zz_542); + assign _zz_526 = {_zz_543,_zz_544}; + assign _zz_527 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_528 = 32'h00000020; + assign _zz_529 = ((decode_INSTRUCTION & _zz_545) == 32'h0); + assign _zz_530 = ((decode_INSTRUCTION & _zz_546) == 32'h00004010); + assign _zz_531 = (_zz_547 == _zz_548); + assign _zz_532 = 1'b0; + assign _zz_533 = ({_zz_549,_zz_550} != 4'b0000); + assign _zz_534 = (_zz_551 != _zz_552); + assign _zz_535 = {_zz_553,{_zz_554,_zz_555}}; + assign _zz_536 = 32'h00000030; + assign _zz_537 = 32'h02000020; + assign _zz_538 = 32'h02002060; + assign _zz_539 = 32'h02003020; + assign _zz_540 = 32'h00002010; + assign _zz_541 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_542 = 32'h00000010; + assign _zz_543 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_544 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_545 = 32'h00000020; + assign _zz_546 = 32'h00004014; + assign _zz_547 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_548 = 32'h00002010; + assign _zz_549 = ((decode_INSTRUCTION & _zz_556) == 32'h0); + assign _zz_550 = {(_zz_557 == _zz_558),{_zz_559,_zz_560}}; + assign _zz_551 = ((decode_INSTRUCTION & _zz_561) == 32'h0); + assign _zz_552 = 1'b0; + assign _zz_553 = ({_zz_562,{_zz_563,_zz_564}} != 3'b000); + assign _zz_554 = ({_zz_565,_zz_566} != 2'b00); + assign _zz_555 = {(_zz_567 != _zz_568),(_zz_569 != _zz_570)}; + assign _zz_556 = 32'h00000044; + assign _zz_557 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_558 = 32'h0; + assign _zz_559 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_560 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_561 = 32'h00000058; + assign _zz_562 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_563 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); + assign _zz_564 = ((decode_INSTRUCTION & _zz_572) == 32'h40000030); + assign _zz_565 = ((decode_INSTRUCTION & _zz_573) == 32'h00000004); + assign _zz_566 = _zz_94; + assign _zz_567 = {(_zz_574 == _zz_575),_zz_94}; + assign _zz_568 = 2'b00; + assign _zz_569 = ((decode_INSTRUCTION & _zz_576) == 32'h00001004); + assign _zz_570 = 1'b0; + assign _zz_571 = 32'h00002014; + assign _zz_572 = 32'h40000034; + assign _zz_573 = 32'h00000014; + assign _zz_574 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_575 = 32'h00000004; + assign _zz_576 = 32'h00005054; + assign _zz_577 = execute_INSTRUCTION[31]; + assign _zz_578 = execute_INSTRUCTION[31]; + assign _zz_579 = execute_INSTRUCTION[7]; + assign _zz_580 = 32'h0; + always @ (posedge clk) begin + if(_zz_385) begin + _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_386) begin + _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_48) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_217 ), //i + .io_cpu_prefetch_isValid (_zz_218 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_219 ), //i + .io_cpu_fetch_isStuck (_zz_220 ), //i + .io_cpu_fetch_isRemoved (_zz_221 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_222 ), //i + .io_cpu_decode_isStuck (_zz_223 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_224 ), //i + .io_cpu_fill_valid (_zz_225 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_226 ), //i + .io_cpu_execute_address (_zz_227[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_88[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_228 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_229[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_230 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_231 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_232 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_233[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_234 ), //i + .io_cpu_writeBack_fence_SR (_zz_235 ), //i + .io_cpu_writeBack_fence_SO (_zz_236 ), //i + .io_cpu_writeBack_fence_SI (_zz_237 ), //i + .io_cpu_writeBack_fence_PW (_zz_238 ), //i + .io_cpu_writeBack_fence_PR (_zz_239 ), //i + .io_cpu_writeBack_fence_PO (_zz_240 ), //i + .io_cpu_writeBack_fence_PI (_zz_241 ), //i + .io_cpu_writeBack_fence_FM (_zz_242[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_243 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_244 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_387) + 2'b00 : begin + _zz_247 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_247 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_247 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_247 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_1) + `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; + default : _zz_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_2) + `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; + default : _zz_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_3) + `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; + default : _zz_10_string = "?????"; + endcase + end + always @(*) begin + case(_zz_11) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; + default : _zz_12_string = "????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; + default : _zz_17_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; + default : _zz_20_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(_zz_23) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(_zz_26) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; + default : _zz_26_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_29) + `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; + default : _zz_29_string = "????????????"; + endcase + end + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; + default : _zz_32_string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_36) + `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; + default : _zz_36_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_39) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; + default : _zz_39_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_40) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; + default : _zz_40_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_42) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; + default : _zz_42_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_43) + `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; + default : _zz_43_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_44) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; + default : _zz_44_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; + default : _zz_45_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; + default : _zz_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_50) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; + default : _zz_50_string = "?????"; + endcase + end + always @(*) begin + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; + endcase + end + always @(*) begin + case(_zz_52) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; + default : _zz_52_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_53) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; + default : _zz_53_string = "?????"; + endcase + end + always @(*) begin + case(_zz_54) + `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; + default : _zz_54_string = "???"; + endcase + end + always @(*) begin + case(_zz_55) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; + default : _zz_55_string = "????????"; + endcase + end + always @(*) begin + case(_zz_56) + `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; + default : _zz_56_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_58) + `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; + default : _zz_58_string = "????"; + endcase + end + always @(*) begin + case(_zz_99) + `Src1CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_99_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99_string = "URS1 "; + default : _zz_99_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_100) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_100_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_100_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_100_string = "BITWISE "; + default : _zz_100_string = "????????"; + endcase + end + always @(*) begin + case(_zz_101) + `Src2CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_101_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_101_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_101_string = "PC "; + default : _zz_101_string = "???"; + endcase + end + always @(*) begin + case(_zz_102) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_102_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_102_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_102_string = "AND_1"; + default : _zz_102_string = "?????"; + endcase + end + always @(*) begin + case(_zz_103) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_103_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_103_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_103_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_103_string = "SRA_1 "; + default : _zz_103_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_104) + `BranchCtrlEnum_defaultEncoding_INC : _zz_104_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_104_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_104_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_104_string = "JALR"; + default : _zz_104_string = "????"; + endcase + end + always @(*) begin + case(_zz_105) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_105_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_105_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_105_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_105_string = "ECALL"; + default : _zz_105_string = "?????"; + endcase + end + always @(*) begin + case(_zz_106) + `Input2Kind_defaultEncoding_RS : _zz_106_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_106_string = "IMM_I"; + default : _zz_106_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign execute_SHIFT_RIGHT = _zz_297; + assign execute_REGFILE_WRITE_DATA = _zz_108; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_227[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_299[0]; + assign decode_IS_RS1_SIGNED = _zz_300[0]; + assign decode_IS_DIV = _zz_301[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_302[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; + assign _zz_2 = _zz_3; + assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; + assign _zz_4 = _zz_5; + assign _zz_6 = _zz_7; + assign decode_ENV_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_IS_CSR = _zz_304[0]; + assign _zz_11 = _zz_12; + assign _zz_13 = _zz_14; + assign decode_SHIFT_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_ALU_BITWISE_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; + assign decode_MEMORY_MANAGMENT = _zz_306[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_307[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; + assign decode_SRC2_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_ALU_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_SRC1_CTRL = _zz_27; + assign _zz_28 = _zz_29; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + always @ (*) begin + _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck)begin + _zz_30 = 1'b0; + end + end + + always @ (*) begin + _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck)begin + _zz_31 = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_33; + assign execute_ENV_CTRL = _zz_34; + assign writeBack_ENV_CTRL = _zz_35; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_130; + assign execute_BRANCH_CTRL = _zz_36; + assign decode_RS2_USE = _zz_310[0]; + assign decode_RS1_USE = _zz_311[0]; + always @ (*) begin + _zz_37 = execute_REGFILE_WRITE_DATA; + if(_zz_248)begin + _zz_37 = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_119)begin + if((_zz_120 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_121; + end + end + if(_zz_249)begin + if(_zz_250)begin + if(_zz_123)begin + decode_RS2 = _zz_57; + end + end + end + if(_zz_251)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_125)begin + decode_RS2 = _zz_38; + end + end + end + if(_zz_252)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_127)begin + decode_RS2 = _zz_37; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_119)begin + if((_zz_120 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_121; + end + end + if(_zz_249)begin + if(_zz_250)begin + if(_zz_122)begin + decode_RS1 = _zz_57; + end + end + end + if(_zz_251)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_124)begin + decode_RS1 = _zz_38; + end + end + end + if(_zz_252)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_126)begin + decode_RS1 = _zz_37; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_38 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_38 = _zz_116; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_38 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_253)begin + _zz_38 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_39; + assign execute_SHIFT_CTRL = _zz_40; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_41 = execute_PC; + assign execute_SRC2_CTRL = _zz_42; + assign execute_SRC1_CTRL = _zz_43; + assign decode_SRC_USE_SUB_LESS = _zz_312[0]; + assign decode_SRC_ADD_ZERO = _zz_313[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_44; + assign execute_SRC2 = _zz_114; + assign execute_SRC1 = _zz_109; + assign execute_ALU_BITWISE_CTRL = _zz_45; + assign _zz_46 = writeBack_INSTRUCTION; + assign _zz_47 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_48 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_48 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_314[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}} != 22'h0); + always @ (*) begin + _zz_57 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_286) + 2'b00 : begin + _zz_57 = _zz_360; + end + default : begin + _zz_57 = _zz_361; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_315[0]; + assign decode_FLUSH_ALL = _zz_316[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_254)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_255)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_256)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_257)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_58; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_59 = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_59 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_60 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_117 || _zz_118)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_258)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_258)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((_zz_243 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_259)begin + if((! execute_CsrPlugin_wfiWake))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_248)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(_zz_260)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_260)begin + execute_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if((! memory_CfuPlugin_rsp_valid))begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_253)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(CfuPlugin_joinException_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(CfuPlugin_joinException_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_261)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_262)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_261)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_262)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_259)begin + CsrPlugin_inWfi = 1'b1; + end + end + + assign CsrPlugin_thirdPartyWake = 1'b0; + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_261)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_262)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_261)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_262)begin + case(_zz_263) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_62 = (_zz_61 & (~ _zz_317)); + assign _zz_63 = _zz_62[3]; + assign _zz_64 = (_zz_62[1] || _zz_63); + assign _zz_65 = (_zz_62[2] || _zz_63); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_319); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_69; + assign _zz_69 = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_70 = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_72)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_72 = _zz_73; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_74; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign _zz_75 = _zz_320[11]; + always @ (*) begin + _zz_76[18] = _zz_75; + _zz_76[17] = _zz_75; + _zz_76[16] = _zz_75; + _zz_76[15] = _zz_75; + _zz_76[14] = _zz_75; + _zz_76[13] = _zz_75; + _zz_76[12] = _zz_75; + _zz_76[11] = _zz_75; + _zz_76[10] = _zz_75; + _zz_76[9] = _zz_75; + _zz_76[8] = _zz_75; + _zz_76[7] = _zz_75; + _zz_76[6] = _zz_75; + _zz_76[5] = _zz_75; + _zz_76[4] = _zz_75; + _zz_76[3] = _zz_75; + _zz_76[2] = _zz_75; + _zz_76[1] = _zz_75; + _zz_76[0] = _zz_75; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_321[31])); + if(_zz_81)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_77 = _zz_322[19]; + always @ (*) begin + _zz_78[10] = _zz_77; + _zz_78[9] = _zz_77; + _zz_78[8] = _zz_77; + _zz_78[7] = _zz_77; + _zz_78[6] = _zz_77; + _zz_78[5] = _zz_77; + _zz_78[4] = _zz_77; + _zz_78[3] = _zz_77; + _zz_78[2] = _zz_77; + _zz_78[1] = _zz_77; + _zz_78[0] = _zz_77; + end + + assign _zz_79 = _zz_323[11]; + always @ (*) begin + _zz_80[18] = _zz_79; + _zz_80[17] = _zz_79; + _zz_80[16] = _zz_79; + _zz_80[15] = _zz_79; + _zz_80[14] = _zz_79; + _zz_80[13] = _zz_79; + _zz_80[12] = _zz_79; + _zz_80[11] = _zz_79; + _zz_80[10] = _zz_79; + _zz_80[9] = _zz_79; + _zz_80[8] = _zz_79; + _zz_80[7] = _zz_79; + _zz_80[6] = _zz_79; + _zz_80[5] = _zz_79; + _zz_80[4] = _zz_79; + _zz_80[3] = _zz_79; + _zz_80[2] = _zz_79; + _zz_80[1] = _zz_79; + _zz_80[0] = _zz_79; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_81 = _zz_324[1]; + end + default : begin + _zz_81 = _zz_325[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_82 = _zz_326[19]; + always @ (*) begin + _zz_83[10] = _zz_82; + _zz_83[9] = _zz_82; + _zz_83[8] = _zz_82; + _zz_83[7] = _zz_82; + _zz_83[6] = _zz_82; + _zz_83[5] = _zz_82; + _zz_83[4] = _zz_82; + _zz_83[3] = _zz_82; + _zz_83[2] = _zz_82; + _zz_83[1] = _zz_82; + _zz_83[0] = _zz_82; + end + + assign _zz_84 = _zz_327[11]; + always @ (*) begin + _zz_85[18] = _zz_84; + _zz_85[17] = _zz_84; + _zz_85[16] = _zz_84; + _zz_85[15] = _zz_84; + _zz_85[14] = _zz_84; + _zz_85[13] = _zz_84; + _zz_85[12] = _zz_84; + _zz_85[11] = _zz_84; + _zz_85[10] = _zz_84; + _zz_85[9] = _zz_84; + _zz_85[8] = _zz_84; + _zz_85[7] = _zz_84; + _zz_85[6] = _zz_84; + _zz_85[5] = _zz_84; + _zz_85[4] = _zz_84; + _zz_85[3] = _zz_84; + _zz_85[2] = _zz_84; + _zz_85[1] = _zz_84; + _zz_85[0] = _zz_84; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_406,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_407,_zz_408},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_219; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_224 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_257)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_255)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_225 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_255)begin + _zz_225 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_256)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_254)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_256)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_254)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_217 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_244 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_227 = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_88 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_88 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_88 = execute_RS2[31 : 0]; + end + endcase + end + + assign _zz_243 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_228 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_229 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_228; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_229; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @ (*) begin + _zz_230 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_230 = 1'b1; + end + end + + assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_232 = (CsrPlugin_privilege == 2'b00); + assign _zz_233 = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_264)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_264)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_264)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_89 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_90[31] = _zz_89; + _zz_90[30] = _zz_89; + _zz_90[29] = _zz_89; + _zz_90[28] = _zz_89; + _zz_90[27] = _zz_89; + _zz_90[26] = _zz_89; + _zz_90[25] = _zz_89; + _zz_90[24] = _zz_89; + _zz_90[23] = _zz_89; + _zz_90[22] = _zz_89; + _zz_90[21] = _zz_89; + _zz_90[20] = _zz_89; + _zz_90[19] = _zz_89; + _zz_90[18] = _zz_89; + _zz_90[17] = _zz_89; + _zz_90[16] = _zz_89; + _zz_90[15] = _zz_89; + _zz_90[14] = _zz_89; + _zz_90[13] = _zz_89; + _zz_90[12] = _zz_89; + _zz_90[11] = _zz_89; + _zz_90[10] = _zz_89; + _zz_90[9] = _zz_89; + _zz_90[8] = _zz_89; + _zz_90[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_91 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_92[31] = _zz_91; + _zz_92[30] = _zz_91; + _zz_92[29] = _zz_91; + _zz_92[28] = _zz_91; + _zz_92[27] = _zz_91; + _zz_92[26] = _zz_91; + _zz_92[25] = _zz_91; + _zz_92[24] = _zz_91; + _zz_92[23] = _zz_91; + _zz_92[22] = _zz_91; + _zz_92[21] = _zz_91; + _zz_92[20] = _zz_91; + _zz_92[19] = _zz_91; + _zz_92[18] = _zz_91; + _zz_92[17] = _zz_91; + _zz_92[16] = _zz_91; + _zz_92[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_284) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_90; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_92; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_94 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_95 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_409 == _zz_410) != 1'b0),{(_zz_411 != 1'b0),{1'b0,{_zz_412,{_zz_413,_zz_414}}}}}}}; + assign _zz_99 = _zz_93[2 : 1]; + assign _zz_56 = _zz_99; + assign _zz_100 = _zz_93[7 : 6]; + assign _zz_55 = _zz_100; + assign _zz_101 = _zz_93[9 : 8]; + assign _zz_54 = _zz_101; + assign _zz_102 = _zz_93[19 : 18]; + assign _zz_53 = _zz_102; + assign _zz_103 = _zz_93[22 : 21]; + assign _zz_52 = _zz_103; + assign _zz_104 = _zz_93[24 : 23]; + assign _zz_51 = _zz_104; + assign _zz_105 = _zz_93[27 : 26]; + assign _zz_50 = _zz_105; + assign _zz_106 = _zz_93[29 : 29]; + assign _zz_49 = _zz_106; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_245; + assign decode_RegFilePlugin_rs2Data = _zz_246; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); + if(_zz_107)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; + if(_zz_107)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_57; + if(_zz_107)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_108 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_108 = {31'd0, _zz_330}; + end + default : begin + _zz_108 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_109 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_109 = {29'd0, _zz_331}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_109 = {27'd0, _zz_332}; + end + endcase + end + + assign _zz_110 = _zz_333[11]; + always @ (*) begin + _zz_111[19] = _zz_110; + _zz_111[18] = _zz_110; + _zz_111[17] = _zz_110; + _zz_111[16] = _zz_110; + _zz_111[15] = _zz_110; + _zz_111[14] = _zz_110; + _zz_111[13] = _zz_110; + _zz_111[12] = _zz_110; + _zz_111[11] = _zz_110; + _zz_111[10] = _zz_110; + _zz_111[9] = _zz_110; + _zz_111[8] = _zz_110; + _zz_111[7] = _zz_110; + _zz_111[6] = _zz_110; + _zz_111[5] = _zz_110; + _zz_111[4] = _zz_110; + _zz_111[3] = _zz_110; + _zz_111[2] = _zz_110; + _zz_111[1] = _zz_110; + _zz_111[0] = _zz_110; + end + + assign _zz_112 = _zz_334[11]; + always @ (*) begin + _zz_113[19] = _zz_112; + _zz_113[18] = _zz_112; + _zz_113[17] = _zz_112; + _zz_113[16] = _zz_112; + _zz_113[15] = _zz_112; + _zz_113[14] = _zz_112; + _zz_113[13] = _zz_112; + _zz_113[12] = _zz_112; + _zz_113[11] = _zz_112; + _zz_113[10] = _zz_112; + _zz_113[9] = _zz_112; + _zz_113[8] = _zz_112; + _zz_113[7] = _zz_112; + _zz_113[6] = _zz_112; + _zz_113[5] = _zz_112; + _zz_113[4] = _zz_112; + _zz_113[3] = _zz_112; + _zz_113[2] = _zz_112; + _zz_113[1] = _zz_112; + _zz_113[0] = _zz_112; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_114 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_114 = {_zz_111,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_114 = {_zz_113,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_114 = _zz_41; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_335; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_115[0] = execute_SRC1[31]; + _zz_115[1] = execute_SRC1[30]; + _zz_115[2] = execute_SRC1[29]; + _zz_115[3] = execute_SRC1[28]; + _zz_115[4] = execute_SRC1[27]; + _zz_115[5] = execute_SRC1[26]; + _zz_115[6] = execute_SRC1[25]; + _zz_115[7] = execute_SRC1[24]; + _zz_115[8] = execute_SRC1[23]; + _zz_115[9] = execute_SRC1[22]; + _zz_115[10] = execute_SRC1[21]; + _zz_115[11] = execute_SRC1[20]; + _zz_115[12] = execute_SRC1[19]; + _zz_115[13] = execute_SRC1[18]; + _zz_115[14] = execute_SRC1[17]; + _zz_115[15] = execute_SRC1[16]; + _zz_115[16] = execute_SRC1[15]; + _zz_115[17] = execute_SRC1[14]; + _zz_115[18] = execute_SRC1[13]; + _zz_115[19] = execute_SRC1[12]; + _zz_115[20] = execute_SRC1[11]; + _zz_115[21] = execute_SRC1[10]; + _zz_115[22] = execute_SRC1[9]; + _zz_115[23] = execute_SRC1[8]; + _zz_115[24] = execute_SRC1[7]; + _zz_115[25] = execute_SRC1[6]; + _zz_115[26] = execute_SRC1[5]; + _zz_115[27] = execute_SRC1[4]; + _zz_115[28] = execute_SRC1[3]; + _zz_115[29] = execute_SRC1[2]; + _zz_115[30] = execute_SRC1[1]; + _zz_115[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_115 : execute_SRC1); + always @ (*) begin + _zz_116[0] = memory_SHIFT_RIGHT[31]; + _zz_116[1] = memory_SHIFT_RIGHT[30]; + _zz_116[2] = memory_SHIFT_RIGHT[29]; + _zz_116[3] = memory_SHIFT_RIGHT[28]; + _zz_116[4] = memory_SHIFT_RIGHT[27]; + _zz_116[5] = memory_SHIFT_RIGHT[26]; + _zz_116[6] = memory_SHIFT_RIGHT[25]; + _zz_116[7] = memory_SHIFT_RIGHT[24]; + _zz_116[8] = memory_SHIFT_RIGHT[23]; + _zz_116[9] = memory_SHIFT_RIGHT[22]; + _zz_116[10] = memory_SHIFT_RIGHT[21]; + _zz_116[11] = memory_SHIFT_RIGHT[20]; + _zz_116[12] = memory_SHIFT_RIGHT[19]; + _zz_116[13] = memory_SHIFT_RIGHT[18]; + _zz_116[14] = memory_SHIFT_RIGHT[17]; + _zz_116[15] = memory_SHIFT_RIGHT[16]; + _zz_116[16] = memory_SHIFT_RIGHT[15]; + _zz_116[17] = memory_SHIFT_RIGHT[14]; + _zz_116[18] = memory_SHIFT_RIGHT[13]; + _zz_116[19] = memory_SHIFT_RIGHT[12]; + _zz_116[20] = memory_SHIFT_RIGHT[11]; + _zz_116[21] = memory_SHIFT_RIGHT[10]; + _zz_116[22] = memory_SHIFT_RIGHT[9]; + _zz_116[23] = memory_SHIFT_RIGHT[8]; + _zz_116[24] = memory_SHIFT_RIGHT[7]; + _zz_116[25] = memory_SHIFT_RIGHT[6]; + _zz_116[26] = memory_SHIFT_RIGHT[5]; + _zz_116[27] = memory_SHIFT_RIGHT[4]; + _zz_116[28] = memory_SHIFT_RIGHT[3]; + _zz_116[29] = memory_SHIFT_RIGHT[2]; + _zz_116[30] = memory_SHIFT_RIGHT[1]; + _zz_116[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_117 = 1'b0; + if(_zz_265)begin + if(_zz_266)begin + if(_zz_122)begin + _zz_117 = 1'b1; + end + end + end + if(_zz_267)begin + if(_zz_268)begin + if(_zz_124)begin + _zz_117 = 1'b1; + end + end + end + if(_zz_269)begin + if(_zz_270)begin + if(_zz_126)begin + _zz_117 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_117 = 1'b0; + end + end + + always @ (*) begin + _zz_118 = 1'b0; + if(_zz_265)begin + if(_zz_266)begin + if(_zz_123)begin + _zz_118 = 1'b1; + end + end + end + if(_zz_267)begin + if(_zz_268)begin + if(_zz_125)begin + _zz_118 = 1'b1; + end + end + end + if(_zz_269)begin + if(_zz_270)begin + if(_zz_127)begin + _zz_118 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_118 = 1'b0; + end + end + + assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_128 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_128 == 3'b000)) begin + _zz_129 = execute_BranchPlugin_eq; + end else if((_zz_128 == 3'b001)) begin + _zz_129 = (! execute_BranchPlugin_eq); + end else if((((_zz_128 & 3'b101) == 3'b101))) begin + _zz_129 = (! execute_SRC_LESS); + end else begin + _zz_129 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_130 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_130 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_130 = 1'b1; + end + default : begin + _zz_130 = _zz_129; + end + endcase + end + + assign _zz_131 = _zz_342[11]; + always @ (*) begin + _zz_132[19] = _zz_131; + _zz_132[18] = _zz_131; + _zz_132[17] = _zz_131; + _zz_132[16] = _zz_131; + _zz_132[15] = _zz_131; + _zz_132[14] = _zz_131; + _zz_132[13] = _zz_131; + _zz_132[12] = _zz_131; + _zz_132[11] = _zz_131; + _zz_132[10] = _zz_131; + _zz_132[9] = _zz_131; + _zz_132[8] = _zz_131; + _zz_132[7] = _zz_131; + _zz_132[6] = _zz_131; + _zz_132[5] = _zz_131; + _zz_132[4] = _zz_131; + _zz_132[3] = _zz_131; + _zz_132[2] = _zz_131; + _zz_132[1] = _zz_131; + _zz_132[0] = _zz_131; + end + + assign _zz_133 = _zz_343[19]; + always @ (*) begin + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; + end + + assign _zz_135 = _zz_344[11]; + always @ (*) begin + _zz_136[18] = _zz_135; + _zz_136[17] = _zz_135; + _zz_136[16] = _zz_135; + _zz_136[15] = _zz_135; + _zz_136[14] = _zz_135; + _zz_136[13] = _zz_135; + _zz_136[12] = _zz_135; + _zz_136[11] = _zz_135; + _zz_136[10] = _zz_135; + _zz_136[9] = _zz_135; + _zz_136[8] = _zz_135; + _zz_136[7] = _zz_135; + _zz_136[6] = _zz_135; + _zz_136[5] = _zz_135; + _zz_136[4] = _zz_135; + _zz_136[3] = _zz_135; + _zz_136[2] = _zz_135; + _zz_136[1] = _zz_135; + _zz_136[0] = _zz_135; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_137 = (_zz_345[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_137 = _zz_346[1]; + end + default : begin + _zz_137 = _zz_347[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_137); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_138 = _zz_348[11]; + always @ (*) begin + _zz_139[19] = _zz_138; + _zz_139[18] = _zz_138; + _zz_139[17] = _zz_138; + _zz_139[16] = _zz_138; + _zz_139[15] = _zz_138; + _zz_139[14] = _zz_138; + _zz_139[13] = _zz_138; + _zz_139[12] = _zz_138; + _zz_139[11] = _zz_138; + _zz_139[10] = _zz_138; + _zz_139[9] = _zz_138; + _zz_139[8] = _zz_138; + _zz_139[7] = _zz_138; + _zz_139[6] = _zz_138; + _zz_139[5] = _zz_138; + _zz_139[4] = _zz_138; + _zz_139[3] = _zz_138; + _zz_139[2] = _zz_138; + _zz_139[1] = _zz_138; + _zz_139[0] = _zz_138; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_577,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_578,_zz_579},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_351}; + end + end + endcase + end + + assign _zz_140 = _zz_349[19]; + always @ (*) begin + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; + end + + assign _zz_142 = _zz_350[11]; + always @ (*) begin + _zz_143[18] = _zz_142; + _zz_143[17] = _zz_142; + _zz_143[16] = _zz_142; + _zz_143[15] = _zz_142; + _zz_143[14] = _zz_142; + _zz_143[13] = _zz_142; + _zz_143[12] = _zz_142; + _zz_143[11] = _zz_142; + _zz_143[10] = _zz_142; + _zz_143[9] = _zz_142; + _zz_143[8] = _zz_142; + _zz_143[7] = _zz_142; + _zz_143[6] = _zz_142; + _zz_143[5] = _zz_142; + _zz_143[4] = _zz_142; + _zz_143[3] = _zz_142; + _zz_143[2] = _zz_142; + _zz_143[1] = _zz_142; + _zz_143[0] = _zz_142; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_144 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_145 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_146 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_148 = _zz_352[0]; + assign _zz_149 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_150 = _zz_354[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_258)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_260)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2820)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2822)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2824)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2826)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2828)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2830)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_271)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_272)begin + CsrPlugin_selfException_valid = 1'b1; + end + if(_zz_273)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_272)begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(_zz_273)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_271)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_271)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_285) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign execute_CfuPlugin_functionsIds_0 = _zz_356; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_167 = _zz_357[7]; + always @ (*) begin + _zz_168[23] = _zz_167; + _zz_168[22] = _zz_167; + _zz_168[21] = _zz_167; + _zz_168[20] = _zz_167; + _zz_168[19] = _zz_167; + _zz_168[18] = _zz_167; + _zz_168[17] = _zz_167; + _zz_168[16] = _zz_167; + _zz_168[15] = _zz_167; + _zz_168[14] = _zz_167; + _zz_168[13] = _zz_167; + _zz_168[12] = _zz_167; + _zz_168[11] = _zz_167; + _zz_168[10] = _zz_167; + _zz_168[9] = _zz_167; + _zz_168[8] = _zz_167; + _zz_168[7] = _zz_167; + _zz_168[6] = _zz_167; + _zz_168[5] = _zz_167; + _zz_168[4] = _zz_167; + _zz_168[3] = _zz_167; + _zz_168[2] = _zz_167; + _zz_168[1] = _zz_167; + _zz_168[0] = _zz_167; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : begin + _zz_169 = execute_RS2; + end + default : begin + _zz_169 = {_zz_168,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_169; + assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); + assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); + assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @ (*) begin + CfuPlugin_joinException_valid = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if(memory_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); + end + end + end + + assign CfuPlugin_joinException_payload_code = 4'b1111; + assign CfuPlugin_joinException_payload_badAddr = 32'h0; + always @ (*) begin + memory_CfuPlugin_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_274) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_274) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_358) + $signed(_zz_359)); + assign memory_DivPlugin_frontendOk = 1'b1; + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_253)begin + if(_zz_275)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_276)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_363); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_170 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_170[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_364); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_365 : _zz_366); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_367[31:0]; + assign _zz_171 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_172 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_173 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_174[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_174[31 : 0] = execute_RS1; + end + + assign _zz_176 = (_zz_175 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_176 != 32'h0); + assign _zz_29 = decode_SRC1_CTRL; + assign _zz_27 = _zz_56; + assign _zz_43 = decode_to_execute_SRC1_CTRL; + assign _zz_26 = decode_ALU_CTRL; + assign _zz_24 = _zz_55; + assign _zz_44 = decode_to_execute_ALU_CTRL; + assign _zz_23 = decode_SRC2_CTRL; + assign _zz_21 = _zz_54; + assign _zz_42 = decode_to_execute_SRC2_CTRL; + assign _zz_20 = decode_ALU_BITWISE_CTRL; + assign _zz_18 = _zz_53; + assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_17 = decode_SHIFT_CTRL; + assign _zz_14 = execute_SHIFT_CTRL; + assign _zz_15 = _zz_52; + assign _zz_40 = decode_to_execute_SHIFT_CTRL; + assign _zz_39 = execute_to_memory_SHIFT_CTRL; + assign _zz_12 = decode_BRANCH_CTRL; + assign _zz_58 = _zz_51; + assign _zz_36 = decode_to_execute_BRANCH_CTRL; + assign _zz_10 = decode_ENV_CTRL; + assign _zz_7 = execute_ENV_CTRL; + assign _zz_5 = memory_ENV_CTRL; + assign _zz_8 = _zz_50; + assign _zz_34 = decode_to_execute_ENV_CTRL; + assign _zz_33 = execute_to_memory_ENV_CTRL; + assign _zz_35 = memory_to_writeBack_ENV_CTRL; + assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_1 = _zz_49; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_177[12 : 0] = 13'h1000; + _zz_177[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_178[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_179[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_180[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_181[31 : 30] = CsrPlugin_misa_base; + _zz_181[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_182[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_182[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_182[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_183[11 : 11] = CsrPlugin_mip_MEIP; + _zz_183[7 : 7] = CsrPlugin_mip_MTIP; + _zz_183[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_184 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_184[11 : 11] = CsrPlugin_mie_MEIE; + _zz_184[7 : 7] = CsrPlugin_mie_MTIE; + _zz_184[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_185 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_185[31 : 2] = CsrPlugin_mtvec_base; + _zz_185[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_186 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_186[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_187 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_187[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_188 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_188[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_188[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_189 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_189[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_190 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_191 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_192 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_193 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_194 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_195 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_196 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_197 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_198 = 32'h0; + if(execute_CsrPlugin_csr_2820)begin + _zz_198[31 : 0] = _zz_151; + end + end + + always @ (*) begin + _zz_199 = 32'h0; + if(execute_CsrPlugin_csr_2822)begin + _zz_199[31 : 0] = _zz_153; + end + end + + always @ (*) begin + _zz_200 = 32'h0; + if(execute_CsrPlugin_csr_2824)begin + _zz_200[31 : 0] = _zz_155; + end + end + + always @ (*) begin + _zz_201 = 32'h0; + if(execute_CsrPlugin_csr_2826)begin + _zz_201[31 : 0] = _zz_157; + end + end + + always @ (*) begin + _zz_202 = 32'h0; + if(execute_CsrPlugin_csr_2828)begin + _zz_202[31 : 0] = _zz_159; + end + end + + always @ (*) begin + _zz_203 = 32'h0; + if(execute_CsrPlugin_csr_2830)begin + _zz_203[31 : 0] = _zz_161; + end + end + + always @ (*) begin + _zz_204 = 32'h0; + if(execute_CsrPlugin_csr_2832)begin + _zz_204[31 : 0] = _zz_163; + end + end + + always @ (*) begin + _zz_205 = 32'h0; + if(execute_CsrPlugin_csr_2834)begin + _zz_205[31 : 0] = _zz_165; + end + end + + always @ (*) begin + _zz_206 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_206[31 : 0] = _zz_175; + end + end + + always @ (*) begin + _zz_207 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_207[31 : 0] = _zz_176; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_580 | _zz_181) | (_zz_182 | _zz_183))) | (((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191)))) | ((((_zz_192 | _zz_193) | (_zz_194 | _zz_195)) | ((_zz_196 | _zz_197) | (_zz_198 | _zz_199))) | (((_zz_200 | _zz_201) | (_zz_202 | _zz_203)) | ((_zz_204 | _zz_205) | (_zz_206 | _zz_207))))); + assign iBusWishbone_ADR = {_zz_384,_zz_208}; + assign iBusWishbone_CTI = ((_zz_208 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'h0; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_277)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_277)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_209; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_215 = (dBus_cmd_payload_length != 3'b000); + assign _zz_211 = dBus_cmd_valid; + assign _zz_213 = dBus_cmd_payload_wr; + assign _zz_214 = (_zz_210 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_212 && (_zz_213 || _zz_214)); + assign dBusWishbone_ADR = ((_zz_215 ? {{dBus_cmd_payload_address[31 : 5],_zz_210},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_215 ? (_zz_214 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_213 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_213; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_212 = (_zz_211 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_211; + assign dBusWishbone_STB = _zz_211; + assign dBus_rsp_valid = _zz_216; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_71 <= 1'b0; + _zz_73 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_86; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_87; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_107 <= 1'b1; + _zz_119 <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_CfuPlugin_hold <= 1'b0; + execute_CfuPlugin_fired <= 1'b0; + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_175 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; + _zz_208 <= 3'b000; + _zz_209 <= 1'b0; + _zz_210 <= 3'b000; + _zz_216 <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_71 <= 1'b0; + end + if(_zz_69)begin + _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_73 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_73 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(_zz_278)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_107 <= 1'b0; + _zz_119 <= (_zz_47 && writeBack_arbitration_isFiring); + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_279)begin + if(_zz_280)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_281)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_282)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_261)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_262)begin + case(_zz_263) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_146,{_zz_145,_zz_144}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(execute_CfuPlugin_schedule)begin + execute_CfuPlugin_hold <= 1'b1; + end + if(CfuPlugin_bus_cmd_ready)begin + execute_CfuPlugin_hold <= 1'b0; + end + if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + execute_CfuPlugin_fired <= 1'b1; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_CfuPlugin_fired <= 1'b0; + end + if(memory_CfuPlugin_rsp_ready)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + end + if(_zz_283)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + end + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! memory_arbitration_isStuck))begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_377[0]; + CsrPlugin_mstatus_MIE <= _zz_378[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_380[0]; + CsrPlugin_mie_MTIE <= _zz_381[0]; + CsrPlugin_mie_MSIE <= _zz_382[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_175 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_277)begin + if(iBusWishbone_ACK)begin + _zz_208 <= (_zz_208 + 3'b001); + end + end + _zz_209 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_211 && _zz_212))begin + _zz_210 <= (_zz_210 + 3'b001); + if(_zz_214)begin + _zz_210 <= 3'b000; + end + end + _zz_216 <= ((_zz_211 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_74 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_278)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + _zz_120 <= _zz_46[11 : 7]; + _zz_121 <= _zz_57; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_258)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_260)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + end + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_279)begin + if(_zz_280)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_281)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_282)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_261)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(_zz_152[0])begin + _zz_151 <= (_zz_151 + 32'h00000001); + end + if(_zz_154[0])begin + _zz_153 <= (_zz_153 + 32'h00000001); + end + if(_zz_156[0])begin + _zz_155 <= (_zz_155 + 32'h00000001); + end + if(_zz_158[0])begin + _zz_157 <= (_zz_157 + 32'h00000001); + end + if(_zz_160[0])begin + _zz_159 <= (_zz_159 + 32'h00000001); + end + if(_zz_162[0])begin + _zz_161 <= (_zz_161 + 32'h00000001); + end + if(_zz_164[0])begin + _zz_163 <= (_zz_163 + 32'h00000001); + end + if(_zz_166[0])begin + _zz_165 <= (_zz_165 + 32'h00000001); + end + if(_zz_283)begin + CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_253)begin + if(_zz_275)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_368[31:0]; + end + end + end + if(_zz_276)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_173 ? (~ _zz_174) : _zz_174) + _zz_374); + memory_DivPlugin_rs2 <= ((_zz_172 ? (~ execute_RS2) : execute_RS2) + _zz_376); + memory_DivPlugin_div_needRevert <= ((_zz_173 ^ (_zz_172 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_41; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_28; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_16; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_13; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_379[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_383[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_19; + reg [31:0] _zz_20; + reg [21:0] _zz_21; + reg [31:0] _zz_22; + wire _zz_23; + wire _zz_24; + wire _zz_25; + wire _zz_26; + wire _zz_27; + wire _zz_28; + wire _zz_29; + wire [0:0] _zz_30; + wire [0:0] _zz_31; + wire [0:0] _zz_32; + wire [0:0] _zz_33; + wire [0:0] _zz_34; + wire [0:0] _zz_35; + wire [2:0] _zz_36; + wire [2:0] _zz_37; + wire [21:0] _zz_38; + wire [21:0] _zz_39; + reg _zz_1; + reg _zz_2; + reg _zz_3; + reg _zz_4; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [1:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [1:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [1:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_5; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_6; + wire _zz_7; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire _zz_8; + wire ways_1_tagsReadRsp_valid; + wire ways_1_tagsReadRsp_error; + wire [19:0] ways_1_tagsReadRsp_address; + wire [21:0] _zz_9; + wire _zz_10; + wire [31:0] ways_1_dataReadRspMem; + wire [31:0] ways_1_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_11; + wire [3:0] stage0_mask; + reg [1:0] stage0_dataColisions; + wire [9:0] _zz_12; + wire [3:0] _zz_13; + wire [1:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [1:0] stageA_wayHits; + reg [1:0] _zz_14; + reg [1:0] stageA_wayInvalidate; + reg [1:0] stage0_dataColisions_regNextWhen; + reg [1:0] _zz_15; + wire [9:0] _zz_16; + wire [3:0] _zz_17; + wire [1:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg stageB_tagsReadRsp_1_valid; + reg stageB_tagsReadRsp_1_error; + reg [19:0] stageB_tagsReadRsp_1_address; + reg [31:0] stageB_dataReadRsp_0; + reg [31:0] stageB_dataReadRsp_1; + reg [1:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [1:0] stageB_dataColisions; + reg stageB_unaligned; + reg [1:0] stageB_waysHitsBeforeInvalidate; + wire [1:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + reg [1:0] _zz_18; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [1:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_40; + reg [7:0] _zz_41; + reg [7:0] _zz_42; + reg [7:0] _zz_43; + (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol3 [0:1023]; + reg [7:0] _zz_44; + reg [7:0] _zz_45; + reg [7:0] _zz_46; + reg [7:0] _zz_47; + + assign _zz_23 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_24 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_25 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_26 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_27 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_28 = (! stageB_flusher_hold); + assign _zz_29 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_30 = _zz_6[0 : 0]; + assign _zz_31 = _zz_6[1 : 1]; + assign _zz_32 = _zz_9[0 : 0]; + assign _zz_33 = _zz_9[1 : 1]; + assign _zz_34 = 1'b1; + assign _zz_35 = loader_counter_willIncrement; + assign _zz_36 = {2'd0, _zz_35}; + assign _zz_37 = {loader_waysAllocator,loader_waysAllocator[1]}; + assign _zz_38 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + assign _zz_39 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_5) begin + _zz_19 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_4) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_38; + end + end + + always @ (*) begin + _zz_20 = {_zz_43, _zz_42, _zz_41, _zz_40}; + end + always @ (posedge clk) begin + if(_zz_7) begin + _zz_40 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_41 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_42 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_43 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_3) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_3) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_3) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_3) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (posedge clk) begin + if(_zz_8) begin + _zz_21 <= ways_1_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_1_tags[tagsWriteCmd_payload_address] <= _zz_39; + end + end + + always @ (*) begin + _zz_22 = {_zz_47, _zz_46, _zz_45, _zz_44}; + end + always @ (posedge clk) begin + if(_zz_10) begin + _zz_44 <= ways_1_data_symbol0[dataReadCmd_payload]; + _zz_45 <= ways_1_data_symbol1[dataReadCmd_payload]; + _zz_46 <= ways_1_data_symbol2[dataReadCmd_payload]; + _zz_47 <= ways_1_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_1_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_1_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_1_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_1_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[1]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[1]))begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + _zz_3 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_3 = 1'b1; + end + end + + always @ (*) begin + _zz_4 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_4 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_5 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_6 = _zz_19; + assign ways_0_tagsReadRsp_valid = _zz_30[0]; + assign ways_0_tagsReadRsp_error = _zz_31[0]; + assign ways_0_tagsReadRsp_address = _zz_6[21 : 2]; + assign _zz_7 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_20; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + assign _zz_8 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_9 = _zz_21; + assign ways_1_tagsReadRsp_valid = _zz_32[0]; + assign ways_1_tagsReadRsp_error = _zz_33[0]; + assign ways_1_tagsReadRsp_address = _zz_9[21 : 2]; + assign _zz_10 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_1_dataReadRspMem = _zz_22; + assign ways_1_dataReadRsp = ways_1_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_23)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_23)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_23)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_23)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_24)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 2'bxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 2'b11; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + if(_zz_24)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_25)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 2'bxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_25)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_25)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_25)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_34[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(_zz_25)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_11 = 4'b0001; + end + 2'b01 : begin + _zz_11 = 4'b0011; + end + default : begin + _zz_11 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_11 <<< io_cpu_execute_address[1 : 0]); + assign _zz_12 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_13 = dataWriteCmd_payload_mask[3 : 0]; + always @ (*) begin + stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); + stage0_dataColisions[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); + end + + assign stage0_wayInvalidate = 2'b00; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + always @ (*) begin + _zz_14[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + _zz_14[1] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_1_tagsReadRsp_address) && ways_1_tagsReadRsp_valid); + end + + assign stageA_wayHits = _zz_14; + assign _zz_16 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_17 = dataWriteCmd_payload_mask[3 : 0]; + always @ (*) begin + _zz_15[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); + _zz_15[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); + end + + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_15); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 2'b00); + assign stageB_dataMux = (stageB_waysHits[0] ? stageB_dataReadRsp_0 : stageB_dataReadRsp_1); + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(! _zz_27) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(_zz_24)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_26)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_27)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(_zz_24)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(_zz_27)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(_zz_27)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 2'b00)))begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_18) != 2'b00) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_26)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_27)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(_zz_24)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(_zz_27)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(_zz_27)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(! _zz_27) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + always @ (*) begin + _zz_18[0] = stageB_tagsReadRsp_0_error; + _zz_18[1] = stageB_tagsReadRsp_1_error; + end + + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_25)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_36); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_1_valid <= ways_1_tagsReadRsp_valid; + stageB_tagsReadRsp_1_error <= ways_1_tagsReadRsp_error; + stageB_tagsReadRsp_1_address <= ways_1_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_1 <= ways_1_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_28)begin + if(_zz_29)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 2'b01; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_28)begin + if(! _zz_29) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_25)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_37[1:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_16; + reg [31:0] _zz_17; + reg [21:0] _zz_18; + reg [21:0] _zz_19; + reg _zz_20; + reg [31:0] _zz_21; + wire _zz_22; + wire _zz_23; + wire [0:0] _zz_24; + wire [0:0] _zz_25; + wire [0:0] _zz_26; + wire [0:0] _zz_27; + wire [21:0] _zz_28; + wire [21:0] _zz_29; + reg _zz_1; + reg _zz_2; + reg _zz_3; + reg _zz_4; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_5; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + reg [0:0] lineLoader_wayToAllocate_valueNext; + reg [0:0] lineLoader_wayToAllocate_value; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_tag_1_valid; + wire [6:0] lineLoader_write_tag_1_payload_address; + wire lineLoader_write_tag_1_payload_data_valid; + wire lineLoader_write_tag_1_payload_data_error; + wire [19:0] lineLoader_write_tag_1_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire lineLoader_write_data_1_valid; + wire [9:0] lineLoader_write_data_1_payload_address; + wire [31:0] lineLoader_write_data_1_payload_data; + wire [9:0] _zz_6; + wire _zz_7; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [9:0] _zz_8; + wire _zz_9; + wire [31:0] fetchStage_read_banksValue_1_dataMem; + wire [31:0] fetchStage_read_banksValue_1_data; + wire [6:0] _zz_10; + wire _zz_11; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_12; + wire [6:0] _zz_13; + wire _zz_14; + wire fetchStage_read_waysValues_1_tag_valid; + wire fetchStage_read_waysValues_1_tag_error; + wire [19:0] fetchStage_read_waysValues_1_tag_address; + wire [21:0] _zz_15; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_hits_1; + wire fetchStage_hit_valid; + wire [0:0] fetchStage_hit_wayId; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [31:0] banks_1 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; + + assign _zz_22 = (! lineLoader_flushCounter[7]); + assign _zz_23 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_24 = _zz_12[0 : 0]; + assign _zz_25 = _zz_12[1 : 1]; + assign _zz_26 = _zz_15[0 : 0]; + assign _zz_27 = _zz_15[1 : 1]; + assign _zz_28 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + assign _zz_29 = {lineLoader_write_tag_1_payload_data_address,{lineLoader_write_tag_1_payload_data_error,lineLoader_write_tag_1_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_16 <= banks_0[_zz_6]; + end + end + + always @ (posedge clk) begin + if(_zz_1) begin + banks_1[lineLoader_write_data_1_payload_address] <= lineLoader_write_data_1_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9) begin + _zz_17 <= banks_1[_zz_8]; + end + end + + always @ (posedge clk) begin + if(_zz_4) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_28; + end + end + + always @ (posedge clk) begin + if(_zz_11) begin + _zz_18 <= ways_0_tags[_zz_10]; + end + end + + always @ (posedge clk) begin + if(_zz_3) begin + ways_1_tags[lineLoader_write_tag_1_payload_address] <= _zz_29; + end + end + + always @ (posedge clk) begin + if(_zz_14) begin + _zz_19 <= ways_1_tags[_zz_13]; + end + end + + always @(*) begin + case(fetchStage_hit_wayId) + 1'b0 : begin + _zz_20 = fetchStage_read_waysValues_0_tag_error; + _zz_21 = fetchStage_read_banksValue_0_data; + end + default : begin + _zz_20 = fetchStage_read_waysValues_1_tag_error; + _zz_21 = fetchStage_read_banksValue_1_data; + end + endcase + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_1_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + _zz_3 = 1'b0; + if(lineLoader_write_tag_1_valid)begin + _zz_3 = 1'b1; + end + end + + always @ (*) begin + _zz_4 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_4 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_22)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_5))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = (lineLoader_wayToAllocate_value == 1'b1); + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + always @ (*) begin + lineLoader_wayToAllocate_valueNext = (lineLoader_wayToAllocate_value + lineLoader_wayToAllocate_willIncrement); + if(lineLoader_wayToAllocate_willClear)begin + lineLoader_wayToAllocate_valueNext = 1'b0; + end + end + + assign lineLoader_write_tag_0_valid = (((lineLoader_wayToAllocate_value == 1'b0) && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_tag_1_valid = (((lineLoader_wayToAllocate_value == 1'b1) && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_1_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_1_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_1_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_1_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b0)); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign lineLoader_write_data_1_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b1)); + assign lineLoader_write_data_1_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_1_payload_data = io_mem_rsp_payload_data; + assign _zz_6 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_16; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_8 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_9 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_1_dataMem = _zz_17; + assign fetchStage_read_banksValue_1_data = fetchStage_read_banksValue_1_dataMem[31 : 0]; + assign _zz_10 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_11 = (! io_cpu_fetch_isStuck); + assign _zz_12 = _zz_18; + assign fetchStage_read_waysValues_0_tag_valid = _zz_24[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_25[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_12[21 : 2]; + assign _zz_13 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_14 = (! io_cpu_fetch_isStuck); + assign _zz_15 = _zz_19; + assign fetchStage_read_waysValues_1_tag_valid = _zz_26[0]; + assign fetchStage_read_waysValues_1_tag_error = _zz_27[0]; + assign fetchStage_read_waysValues_1_tag_address = _zz_15[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_hits_1 = (fetchStage_read_waysValues_1_tag_valid && (fetchStage_read_waysValues_1_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = ({fetchStage_hit_hits_1,fetchStage_hit_hits_0} != 2'b00); + assign fetchStage_hit_wayId = fetchStage_hit_hits_1; + assign fetchStage_hit_error = _zz_20; + assign fetchStage_hit_data = _zz_21; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wayToAllocate_value <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_23)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + lineLoader_wayToAllocate_value <= lineLoader_wayToAllocate_valueNext; + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_22)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_5 <= lineLoader_flushCounter[7]; + if(_zz_23)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.yaml new file mode 100644 index 0000000..1f28413 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.yaml @@ -0,0 +1,4 @@ +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 8192} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v new file mode 100644 index 0000000..a4cf26a --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v @@ -0,0 +1,7457 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : 9c3529c14328ee22a18ec0f74e66ca59de7346c3 + + +`define Input2Kind_defaultEncoding_type [0:0] +`define Input2Kind_defaultEncoding_RS 1'b0 +`define Input2Kind_defaultEncoding_IMM_I 1'b1 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input CfuPlugin_bus_rsp_payload_response_ok, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_220; + wire _zz_221; + wire _zz_222; + wire _zz_223; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + reg _zz_228; + wire _zz_229; + wire [31:0] _zz_230; + wire _zz_231; + wire [31:0] _zz_232; + reg _zz_233; + wire _zz_234; + wire _zz_235; + wire [31:0] _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire [3:0] _zz_245; + wire _zz_246; + wire _zz_247; + reg [31:0] _zz_248; + reg [31:0] _zz_249; + reg [31:0] _zz_250; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire _zz_255; + wire _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire [1:0] _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire [1:0] _zz_280; + wire _zz_281; + wire _zz_282; + wire [5:0] _zz_283; + wire _zz_284; + wire _zz_285; + wire _zz_286; + wire _zz_287; + wire _zz_288; + wire _zz_289; + wire _zz_290; + wire [1:0] _zz_291; + wire _zz_292; + wire [1:0] _zz_293; + wire [51:0] _zz_294; + wire [51:0] _zz_295; + wire [51:0] _zz_296; + wire [32:0] _zz_297; + wire [51:0] _zz_298; + wire [49:0] _zz_299; + wire [51:0] _zz_300; + wire [49:0] _zz_301; + wire [51:0] _zz_302; + wire [32:0] _zz_303; + wire [31:0] _zz_304; + wire [32:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire [0:0] _zz_321; + wire [0:0] _zz_322; + wire [0:0] _zz_323; + wire [0:0] _zz_324; + wire [3:0] _zz_325; + wire [2:0] _zz_326; + wire [31:0] _zz_327; + wire [11:0] _zz_328; + wire [31:0] _zz_329; + wire [19:0] _zz_330; + wire [11:0] _zz_331; + wire [31:0] _zz_332; + wire [31:0] _zz_333; + wire [19:0] _zz_334; + wire [11:0] _zz_335; + wire [2:0] _zz_336; + wire [2:0] _zz_337; + wire [0:0] _zz_338; + wire [2:0] _zz_339; + wire [4:0] _zz_340; + wire [11:0] _zz_341; + wire [11:0] _zz_342; + wire [31:0] _zz_343; + wire [31:0] _zz_344; + wire [31:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; + wire [31:0] _zz_349; + wire [11:0] _zz_350; + wire [19:0] _zz_351; + wire [11:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; + wire [31:0] _zz_355; + wire [11:0] _zz_356; + wire [19:0] _zz_357; + wire [11:0] _zz_358; + wire [2:0] _zz_359; + wire [1:0] _zz_360; + wire [1:0] _zz_361; + wire [1:0] _zz_362; + wire [1:0] _zz_363; + wire [9:0] _zz_364; + wire [7:0] _zz_365; + wire [65:0] _zz_366; + wire [65:0] _zz_367; + wire [31:0] _zz_368; + wire [31:0] _zz_369; + wire [0:0] _zz_370; + wire [5:0] _zz_371; + wire [32:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; + wire [32:0] _zz_375; + wire [32:0] _zz_376; + wire [32:0] _zz_377; + wire [32:0] _zz_378; + wire [0:0] _zz_379; + wire [32:0] _zz_380; + wire [0:0] _zz_381; + wire [32:0] _zz_382; + wire [0:0] _zz_383; + wire [31:0] _zz_384; + wire [0:0] _zz_385; + wire [0:0] _zz_386; + wire [0:0] _zz_387; + wire [0:0] _zz_388; + wire [0:0] _zz_389; + wire [0:0] _zz_390; + wire [0:0] _zz_391; + wire [26:0] _zz_392; + wire _zz_393; + wire _zz_394; + wire [1:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire _zz_399; + wire [0:0] _zz_400; + wire [14:0] _zz_401; + wire [31:0] _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire _zz_405; + wire [0:0] _zz_406; + wire [8:0] _zz_407; + wire [31:0] _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire _zz_411; + wire [0:0] _zz_412; + wire [2:0] _zz_413; + wire _zz_414; + wire _zz_415; + wire _zz_416; + wire [31:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire _zz_420; + wire [0:0] _zz_421; + wire [28:0] _zz_422; + wire [0:0] _zz_423; + wire [0:0] _zz_424; + wire [0:0] _zz_425; + wire [0:0] _zz_426; + wire _zz_427; + wire [0:0] _zz_428; + wire [23:0] _zz_429; + wire [31:0] _zz_430; + wire [31:0] _zz_431; + wire [31:0] _zz_432; + wire _zz_433; + wire _zz_434; + wire [0:0] _zz_435; + wire [0:0] _zz_436; + wire [0:0] _zz_437; + wire [0:0] _zz_438; + wire _zz_439; + wire [0:0] _zz_440; + wire [20:0] _zz_441; + wire [31:0] _zz_442; + wire [31:0] _zz_443; + wire _zz_444; + wire _zz_445; + wire [0:0] _zz_446; + wire [1:0] _zz_447; + wire [0:0] _zz_448; + wire [0:0] _zz_449; + wire _zz_450; + wire [0:0] _zz_451; + wire [17:0] _zz_452; + wire [31:0] _zz_453; + wire [31:0] _zz_454; + wire [31:0] _zz_455; + wire [31:0] _zz_456; + wire [31:0] _zz_457; + wire [31:0] _zz_458; + wire [31:0] _zz_459; + wire [31:0] _zz_460; + wire _zz_461; + wire [1:0] _zz_462; + wire [1:0] _zz_463; + wire _zz_464; + wire [0:0] _zz_465; + wire [14:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [0:0] _zz_473; + wire [1:0] _zz_474; + wire [4:0] _zz_475; + wire [4:0] _zz_476; + wire _zz_477; + wire [0:0] _zz_478; + wire [11:0] _zz_479; + wire [31:0] _zz_480; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire _zz_486; + wire [0:0] _zz_487; + wire [1:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; + wire [0:0] _zz_491; + wire [4:0] _zz_492; + wire [4:0] _zz_493; + wire [4:0] _zz_494; + wire _zz_495; + wire [0:0] _zz_496; + wire [8:0] _zz_497; + wire [31:0] _zz_498; + wire [31:0] _zz_499; + wire [31:0] _zz_500; + wire _zz_501; + wire _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire _zz_505; + wire [0:0] _zz_506; + wire [2:0] _zz_507; + wire [0:0] _zz_508; + wire [2:0] _zz_509; + wire [0:0] _zz_510; + wire [4:0] _zz_511; + wire [1:0] _zz_512; + wire [1:0] _zz_513; + wire _zz_514; + wire [0:0] _zz_515; + wire [6:0] _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire _zz_520; + wire [0:0] _zz_521; + wire [0:0] _zz_522; + wire [31:0] _zz_523; + wire [31:0] _zz_524; + wire _zz_525; + wire [0:0] _zz_526; + wire [0:0] _zz_527; + wire _zz_528; + wire [0:0] _zz_529; + wire [2:0] _zz_530; + wire _zz_531; + wire [0:0] _zz_532; + wire [0:0] _zz_533; + wire [0:0] _zz_534; + wire [0:0] _zz_535; + wire _zz_536; + wire [0:0] _zz_537; + wire [4:0] _zz_538; + wire [31:0] _zz_539; + wire [31:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire [31:0] _zz_543; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; + wire [31:0] _zz_549; + wire [31:0] _zz_550; + wire [31:0] _zz_551; + wire _zz_552; + wire [0:0] _zz_553; + wire [0:0] _zz_554; + wire [31:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire [31:0] _zz_559; + wire _zz_560; + wire [3:0] _zz_561; + wire [3:0] _zz_562; + wire _zz_563; + wire [0:0] _zz_564; + wire [2:0] _zz_565; + wire [31:0] _zz_566; + wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [31:0] _zz_570; + wire [31:0] _zz_571; + wire _zz_572; + wire [0:0] _zz_573; + wire [1:0] _zz_574; + wire _zz_575; + wire [2:0] _zz_576; + wire [2:0] _zz_577; + wire _zz_578; + wire [0:0] _zz_579; + wire [0:0] _zz_580; + wire [31:0] _zz_581; + wire [31:0] _zz_582; + wire [31:0] _zz_583; + wire [31:0] _zz_584; + wire [31:0] _zz_585; + wire [31:0] _zz_586; + wire [31:0] _zz_587; + wire _zz_588; + wire _zz_589; + wire _zz_590; + wire [0:0] _zz_591; + wire [0:0] _zz_592; + wire _zz_593; + wire _zz_594; + wire _zz_595; + wire _zz_596; + wire [31:0] _zz_597; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_1; + wire `Input2Kind_defaultEncoding_type _zz_2; + wire `Input2Kind_defaultEncoding_type _zz_3; + wire decode_CfuPlugin_CFU_ENABLE; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `AluCtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + reg _zz_30; + reg _zz_31; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_32; + wire execute_CfuPlugin_CFU_ENABLE; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_37; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_38; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_41; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; + wire [31:0] _zz_46; + wire _zz_47; + reg _zz_48; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `Input2Kind_defaultEncoding_type _zz_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; + wire `Src2CtrlEnum_defaultEncoding_type _zz_54; + wire `AluCtrlEnum_defaultEncoding_type _zz_55; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56; + reg [31:0] _zz_57; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_59; + reg [31:0] _zz_60; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_61; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CfuPlugin_joinException_valid; + wire [3:0] CfuPlugin_joinException_payload_code; + wire [31:0] CfuPlugin_joinException_payload_badAddr; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_62; + wire [3:0] _zz_63; + wire _zz_64; + wire _zz_65; + wire _zz_66; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_67; + wire _zz_68; + wire _zz_69; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_70; + wire _zz_71; + reg _zz_72; + wire _zz_73; + reg _zz_74; + reg [31:0] _zz_75; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_76; + reg [18:0] _zz_77; + wire _zz_78; + reg [10:0] _zz_79; + wire _zz_80; + reg [18:0] _zz_81; + reg _zz_82; + wire _zz_83; + reg [10:0] _zz_84; + wire _zz_85; + reg [18:0] _zz_86; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_87; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_88; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_89; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_90; + reg [31:0] _zz_91; + wire _zz_92; + reg [31:0] _zz_93; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [34:0] _zz_94; + wire _zz_95; + wire _zz_96; + wire _zz_97; + wire _zz_98; + wire _zz_99; + wire `Src1CtrlEnum_defaultEncoding_type _zz_100; + wire `AluCtrlEnum_defaultEncoding_type _zz_101; + wire `Src2CtrlEnum_defaultEncoding_type _zz_102; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; + wire `BranchCtrlEnum_defaultEncoding_type _zz_105; + wire `EnvCtrlEnum_defaultEncoding_type _zz_106; + wire `Input2Kind_defaultEncoding_type _zz_107; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_108; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_109; + reg [31:0] _zz_110; + wire _zz_111; + reg [19:0] _zz_112; + wire _zz_113; + reg [19:0] _zz_114; + reg [31:0] _zz_115; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_116; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_117; + reg _zz_118; + reg _zz_119; + reg _zz_120; + reg [4:0] _zz_121; + reg [31:0] _zz_122; + wire _zz_123; + wire _zz_124; + wire _zz_125; + wire _zz_126; + wire _zz_127; + wire _zz_128; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_129; + reg _zz_130; + reg _zz_131; + wire _zz_132; + reg [19:0] _zz_133; + wire _zz_134; + reg [10:0] _zz_135; + wire _zz_136; + reg [18:0] _zz_137; + reg _zz_138; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_139; + reg [19:0] _zz_140; + wire _zz_141; + reg [10:0] _zz_142; + wire _zz_143; + reg [18:0] _zz_144; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_145; + wire _zz_146; + wire _zz_147; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_148; + wire _zz_149; + wire [1:0] _zz_150; + wire _zz_151; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_168; + reg [23:0] _zz_169; + reg [31:0] _zz_170; + wire memory_CfuPlugin_rsp_valid; + reg memory_CfuPlugin_rsp_ready; + wire memory_CfuPlugin_rsp_payload_response_ok; + wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_s2mPipe_rValid; + reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_171; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_172; + wire _zz_173; + wire _zz_174; + reg [32:0] _zz_175; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_176; + wire [31:0] _zz_177; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_178; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_179; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_2820; + reg execute_CsrPlugin_csr_2821; + reg execute_CsrPlugin_csr_2822; + reg execute_CsrPlugin_csr_2823; + reg execute_CsrPlugin_csr_2824; + reg execute_CsrPlugin_csr_2825; + reg execute_CsrPlugin_csr_2826; + reg execute_CsrPlugin_csr_2827; + reg execute_CsrPlugin_csr_2828; + reg execute_CsrPlugin_csr_2829; + reg execute_CsrPlugin_csr_2830; + reg execute_CsrPlugin_csr_2831; + reg execute_CsrPlugin_csr_2832; + reg execute_CsrPlugin_csr_2833; + reg execute_CsrPlugin_csr_2834; + reg execute_CsrPlugin_csr_2835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; + reg [31:0] _zz_199; + reg [31:0] _zz_200; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + reg [31:0] _zz_208; + reg [31:0] _zz_209; + reg [31:0] _zz_210; + reg [2:0] _zz_211; + reg _zz_212; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + reg _zz_219; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [39:0] _zz_10_string; + reg [31:0] _zz_11_string; + reg [31:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [71:0] _zz_17_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [39:0] _zz_20_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [23:0] _zz_23_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [63:0] _zz_26_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [95:0] _zz_29_string; + reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_32_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_33_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_34_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_35_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_36_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_39_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_40_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_42_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_43_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_44_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_45_string; + reg [39:0] _zz_49_string; + reg [39:0] _zz_50_string; + reg [31:0] _zz_51_string; + reg [71:0] _zz_52_string; + reg [39:0] _zz_53_string; + reg [23:0] _zz_54_string; + reg [63:0] _zz_55_string; + reg [95:0] _zz_56_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_58_string; + reg [95:0] _zz_100_string; + reg [63:0] _zz_101_string; + reg [23:0] _zz_102_string; + reg [39:0] _zz_103_string; + reg [71:0] _zz_104_string; + reg [31:0] _zz_105_string; + reg [39:0] _zz_106_string; + reg [39:0] _zz_107_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_251 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_253 = 1'b1; + assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_256 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_257 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_258 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_259 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_260 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_261 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_262 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_263 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_264 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_265 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_268 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_269 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_270 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_271 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_272 = (1'b0 || (! 1'b1)); + assign _zz_273 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_274 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_275 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_276 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_277 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_278 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_280 = execute_INSTRUCTION[13 : 12]; + assign _zz_281 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_282 = (! memory_arbitration_isStuck); + assign _zz_283 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_284 = (iBus_cmd_valid || (_zz_211 != 3'b000)); + assign _zz_285 = (_zz_247 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_286 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_287 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_288 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_289 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_290 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_291 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_292 = execute_INSTRUCTION[13]; + assign _zz_293 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_294 = ($signed(_zz_295) + $signed(_zz_300)); + assign _zz_295 = ($signed(_zz_296) + $signed(_zz_298)); + assign _zz_296 = 52'h0; + assign _zz_297 = {1'b0,memory_MUL_LL}; + assign _zz_298 = {{19{_zz_297[32]}}, _zz_297}; + assign _zz_299 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; + assign _zz_301 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_302 = {{2{_zz_301[49]}}, _zz_301}; + assign _zz_303 = ($signed(_zz_305) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_304 = _zz_303[31 : 0]; + assign _zz_305 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_306 = _zz_94[33 : 33]; + assign _zz_307 = _zz_94[32 : 32]; + assign _zz_308 = _zz_94[31 : 31]; + assign _zz_309 = _zz_94[30 : 30]; + assign _zz_310 = _zz_94[28 : 28]; + assign _zz_311 = _zz_94[25 : 25]; + assign _zz_312 = _zz_94[17 : 17]; + assign _zz_313 = _zz_94[16 : 16]; + assign _zz_314 = _zz_94[13 : 13]; + assign _zz_315 = _zz_94[12 : 12]; + assign _zz_316 = _zz_94[11 : 11]; + assign _zz_317 = _zz_94[34 : 34]; + assign _zz_318 = _zz_94[15 : 15]; + assign _zz_319 = _zz_94[5 : 5]; + assign _zz_320 = _zz_94[3 : 3]; + assign _zz_321 = _zz_94[20 : 20]; + assign _zz_322 = _zz_94[10 : 10]; + assign _zz_323 = _zz_94[4 : 4]; + assign _zz_324 = _zz_94[0 : 0]; + assign _zz_325 = (_zz_62 - 4'b0001); + assign _zz_326 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_327 = {29'd0, _zz_326}; + assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_329 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_331 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_332 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_333 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_334 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_335 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_338 = execute_SRC_LESS; + assign _zz_339 = 3'b100; + assign _zz_340 = execute_INSTRUCTION[19 : 15]; + assign _zz_341 = execute_INSTRUCTION[31 : 20]; + assign _zz_342 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_343 = ($signed(_zz_344) + $signed(_zz_347)); + assign _zz_344 = ($signed(_zz_345) + $signed(_zz_346)); + assign _zz_345 = execute_SRC1; + assign _zz_346 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_347 = (execute_SRC_USE_SUB_LESS ? _zz_348 : _zz_349); + assign _zz_348 = 32'h00000001; + assign _zz_349 = 32'h0; + assign _zz_350 = execute_INSTRUCTION[31 : 20]; + assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_353 = {_zz_133,execute_INSTRUCTION[31 : 20]}; + assign _zz_354 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_355 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_356 = execute_INSTRUCTION[31 : 20]; + assign _zz_357 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_359 = 3'b100; + assign _zz_360 = (_zz_148 & (~ _zz_361)); + assign _zz_361 = (_zz_148 - 2'b01); + assign _zz_362 = (_zz_150 & (~ _zz_363)); + assign _zz_363 = (_zz_150 - 2'b01); + assign _zz_364 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_365 = execute_INSTRUCTION[31 : 24]; + assign _zz_366 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_367 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_368 = writeBack_MUL_LOW[31 : 0]; + assign _zz_369 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_370 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_371 = {5'd0, _zz_370}; + assign _zz_372 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_373 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_374 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_375 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_376 = _zz_377; + assign _zz_377 = _zz_378; + assign _zz_378 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_380); + assign _zz_379 = memory_DivPlugin_div_needRevert; + assign _zz_380 = {32'd0, _zz_379}; + assign _zz_381 = _zz_174; + assign _zz_382 = {32'd0, _zz_381}; + assign _zz_383 = _zz_173; + assign _zz_384 = {31'd0, _zz_383}; + assign _zz_385 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_386 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_387 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_388 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_391 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_392 = (iBus_cmd_payload_address >>> 5); + assign _zz_393 = 1'b1; + assign _zz_394 = 1'b1; + assign _zz_395 = {_zz_66,_zz_65}; + assign _zz_396 = 32'h0000106f; + assign _zz_397 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_398 = 32'h00001073; + assign _zz_399 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_400 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_401 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_402) == 32'h00000003),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; + assign _zz_402 = 32'h0000207f; + assign _zz_403 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_404 = 32'h00000003; + assign _zz_405 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_406 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_407 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_408) == 32'h00005013),{(_zz_409 == _zz_410),{_zz_411,{_zz_412,_zz_413}}}}}}; + assign _zz_408 = 32'hbc00707f; + assign _zz_409 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_410 = 32'h00001013; + assign _zz_411 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_412 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_413 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_414 = decode_INSTRUCTION[31]; + assign _zz_415 = decode_INSTRUCTION[31]; + assign _zz_416 = decode_INSTRUCTION[7]; + assign _zz_417 = 32'h10103050; + assign _zz_418 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_419 = 1'b0; + assign _zz_420 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_421 = 1'b0; + assign _zz_422 = {(_zz_98 != 1'b0),{({_zz_423,_zz_424} != 2'b00),{(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}}}; + assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h10000050); + assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00000050); + assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00000050); + assign _zz_426 = 1'b0; + assign _zz_427 = ({_zz_433,_zz_434} != 2'b00); + assign _zz_428 = ({_zz_435,_zz_436} != 2'b00); + assign _zz_429 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; + assign _zz_430 = 32'h10203050; + assign _zz_431 = 32'h10103050; + assign _zz_432 = 32'h00103050; + assign _zz_433 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_434 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_435 = _zz_97; + assign _zz_436 = ((decode_INSTRUCTION & _zz_442) == 32'h00000004); + assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000040); + assign _zz_438 = 1'b0; + assign _zz_439 = ({_zz_444,_zz_445} != 2'b00); + assign _zz_440 = ({_zz_446,_zz_447} != 3'b000); + assign _zz_441 = {(_zz_448 != _zz_449),{_zz_450,{_zz_451,_zz_452}}}; + assign _zz_442 = 32'h0000001c; + assign _zz_443 = 32'h00000058; + assign _zz_444 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_445 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h40001010); + assign _zz_447 = {(_zz_454 == _zz_455),(_zz_456 == _zz_457)}; + assign _zz_448 = ((decode_INSTRUCTION & _zz_458) == 32'h00000024); + assign _zz_449 = 1'b0; + assign _zz_450 = ((_zz_459 == _zz_460) != 1'b0); + assign _zz_451 = (_zz_461 != 1'b0); + assign _zz_452 = {(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}; + assign _zz_453 = 32'h40003054; + assign _zz_454 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_455 = 32'h00001010; + assign _zz_456 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_457 = 32'h00001010; + assign _zz_458 = 32'h00000064; + assign _zz_459 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_460 = 32'h00001000; + assign _zz_461 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_462 = {(_zz_467 == _zz_468),(_zz_469 == _zz_470)}; + assign _zz_463 = 2'b00; + assign _zz_464 = ((_zz_471 == _zz_472) != 1'b0); + assign _zz_465 = ({_zz_473,_zz_474} != 3'b000); + assign _zz_466 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; + assign _zz_467 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_468 = 32'h00002000; + assign _zz_469 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_470 = 32'h00001000; + assign _zz_471 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_472 = 32'h00004004; + assign _zz_473 = _zz_98; + assign _zz_474 = {(_zz_480 == _zz_481),(_zz_482 == _zz_483)}; + assign _zz_475 = {(_zz_484 == _zz_485),{_zz_486,{_zz_487,_zz_488}}}; + assign _zz_476 = 5'h0; + assign _zz_477 = ((_zz_489 == _zz_490) != 1'b0); + assign _zz_478 = ({_zz_491,_zz_492} != 6'h0); + assign _zz_479 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; + assign _zz_480 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_481 = 32'h00000020; + assign _zz_482 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_483 = 32'h00000020; + assign _zz_484 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_485 = 32'h00002040; + assign _zz_486 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); + assign _zz_487 = (_zz_499 == _zz_500); + assign _zz_488 = {_zz_501,_zz_502}; + assign _zz_489 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_490 = 32'h00000020; + assign _zz_491 = (_zz_503 == _zz_504); + assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; + assign _zz_493 = {_zz_96,{_zz_508,_zz_509}}; + assign _zz_494 = 5'h0; + assign _zz_495 = ({_zz_510,_zz_511} != 6'h0); + assign _zz_496 = (_zz_512 != _zz_513); + assign _zz_497 = {_zz_514,{_zz_515,_zz_516}}; + assign _zz_498 = 32'h00001040; + assign _zz_499 = (decode_INSTRUCTION & 32'h00100040); + assign _zz_500 = 32'h00000040; + assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00000040); + assign _zz_502 = ((decode_INSTRUCTION & _zz_518) == 32'h0); + assign _zz_503 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_504 = 32'h00000008; + assign _zz_505 = ((decode_INSTRUCTION & _zz_519) == 32'h00000040); + assign _zz_506 = _zz_96; + assign _zz_507 = {_zz_520,{_zz_521,_zz_522}}; + assign _zz_508 = (_zz_523 == _zz_524); + assign _zz_509 = {_zz_525,{_zz_526,_zz_527}}; + assign _zz_510 = _zz_97; + assign _zz_511 = {_zz_528,{_zz_529,_zz_530}}; + assign _zz_512 = {_zz_96,_zz_531}; + assign _zz_513 = 2'b00; + assign _zz_514 = ({_zz_532,_zz_533} != 2'b00); + assign _zz_515 = (_zz_534 != _zz_535); + assign _zz_516 = {_zz_536,{_zz_537,_zz_538}}; + assign _zz_517 = 32'h00000050; + assign _zz_518 = 32'h00000038; + assign _zz_519 = 32'h00000040; + assign _zz_520 = ((decode_INSTRUCTION & _zz_539) == 32'h00004020); + assign _zz_521 = (_zz_540 == _zz_541); + assign _zz_522 = (_zz_542 == _zz_543); + assign _zz_523 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_524 = 32'h00002010; + assign _zz_525 = ((decode_INSTRUCTION & _zz_544) == 32'h00000010); + assign _zz_526 = (_zz_545 == _zz_546); + assign _zz_527 = (_zz_547 == _zz_548); + assign _zz_528 = ((decode_INSTRUCTION & _zz_549) == 32'h00001010); + assign _zz_529 = (_zz_550 == _zz_551); + assign _zz_530 = {_zz_552,{_zz_553,_zz_554}}; + assign _zz_531 = ((decode_INSTRUCTION & _zz_555) == 32'h00000020); + assign _zz_532 = _zz_96; + assign _zz_533 = (_zz_556 == _zz_557); + assign _zz_534 = (_zz_558 == _zz_559); + assign _zz_535 = 1'b0; + assign _zz_536 = (_zz_560 != 1'b0); + assign _zz_537 = (_zz_561 != _zz_562); + assign _zz_538 = {_zz_563,{_zz_564,_zz_565}}; + assign _zz_539 = 32'h00004020; + assign _zz_540 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_541 = 32'h00000010; + assign _zz_542 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_543 = 32'h00000020; + assign _zz_544 = 32'h00001030; + assign _zz_545 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_546 = 32'h00002020; + assign _zz_547 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_548 = 32'h00000020; + assign _zz_549 = 32'h00001010; + assign _zz_550 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_551 = 32'h00002010; + assign _zz_552 = ((decode_INSTRUCTION & _zz_566) == 32'h00000010); + assign _zz_553 = (_zz_567 == _zz_568); + assign _zz_554 = (_zz_569 == _zz_570); + assign _zz_555 = 32'h00000070; + assign _zz_556 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_557 = 32'h0; + assign _zz_558 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_559 = 32'h00004010; + assign _zz_560 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); + assign _zz_561 = {_zz_572,{_zz_573,_zz_574}}; + assign _zz_562 = 4'b0000; + assign _zz_563 = (_zz_575 != 1'b0); + assign _zz_564 = (_zz_576 != _zz_577); + assign _zz_565 = {_zz_578,{_zz_579,_zz_580}}; + assign _zz_566 = 32'h00000050; + assign _zz_567 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_568 = 32'h00000004; + assign _zz_569 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_570 = 32'h0; + assign _zz_571 = 32'h00006014; + assign _zz_572 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_573 = ((decode_INSTRUCTION & _zz_581) == 32'h0); + assign _zz_574 = {(_zz_582 == _zz_583),(_zz_584 == _zz_585)}; + assign _zz_575 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_576 = {(_zz_586 == _zz_587),{_zz_588,_zz_589}}; + assign _zz_577 = 3'b000; + assign _zz_578 = ({_zz_590,_zz_95} != 2'b00); + assign _zz_579 = ({_zz_591,_zz_592} != 2'b00); + assign _zz_580 = (_zz_593 != 1'b0); + assign _zz_581 = 32'h00000018; + assign _zz_582 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_583 = 32'h00002000; + assign _zz_584 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_585 = 32'h00001000; + assign _zz_586 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_587 = 32'h00000040; + assign _zz_588 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_589 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_590 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_591 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_592 = _zz_95; + assign _zz_593 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_594 = execute_INSTRUCTION[31]; + assign _zz_595 = execute_INSTRUCTION[31]; + assign _zz_596 = execute_INSTRUCTION[7]; + assign _zz_597 = 32'h0; + always @ (posedge clk) begin + if(_zz_393) begin + _zz_248 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_394) begin + _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_48) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_220 ), //i + .io_cpu_prefetch_isValid (_zz_221 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_222 ), //i + .io_cpu_fetch_isStuck (_zz_223 ), //i + .io_cpu_fetch_isRemoved (_zz_224 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_225 ), //i + .io_cpu_decode_isStuck (_zz_226 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_227 ), //i + .io_cpu_fill_valid (_zz_228 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_16 (_zz_179[2:0] ), //i + ._zz_17 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_229 ), //i + .io_cpu_execute_address (_zz_230[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_89[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_231 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_232[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_233 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_234 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_235 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_236[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_237 ), //i + .io_cpu_writeBack_fence_SR (_zz_238 ), //i + .io_cpu_writeBack_fence_SO (_zz_239 ), //i + .io_cpu_writeBack_fence_SI (_zz_240 ), //i + .io_cpu_writeBack_fence_PW (_zz_241 ), //i + .io_cpu_writeBack_fence_PR (_zz_242 ), //i + .io_cpu_writeBack_fence_PO (_zz_243 ), //i + .io_cpu_writeBack_fence_PI (_zz_244 ), //i + .io_cpu_writeBack_fence_FM (_zz_245[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_246 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_247 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_395) + 2'b00 : begin + _zz_250 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_250 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_250 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_250 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_1) + `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; + default : _zz_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_2) + `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; + default : _zz_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_3) + `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; + default : _zz_10_string = "?????"; + endcase + end + always @(*) begin + case(_zz_11) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; + default : _zz_12_string = "????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; + default : _zz_17_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; + default : _zz_20_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(_zz_23) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(_zz_26) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; + default : _zz_26_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_29) + `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; + default : _zz_29_string = "????????????"; + endcase + end + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; + default : _zz_32_string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_36) + `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; + default : _zz_36_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_39) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; + default : _zz_39_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_40) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; + default : _zz_40_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_42) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; + default : _zz_42_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_43) + `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; + default : _zz_43_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_44) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; + default : _zz_44_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; + default : _zz_45_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; + default : _zz_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_50) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; + default : _zz_50_string = "?????"; + endcase + end + always @(*) begin + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; + endcase + end + always @(*) begin + case(_zz_52) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; + default : _zz_52_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_53) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; + default : _zz_53_string = "?????"; + endcase + end + always @(*) begin + case(_zz_54) + `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; + default : _zz_54_string = "???"; + endcase + end + always @(*) begin + case(_zz_55) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; + default : _zz_55_string = "????????"; + endcase + end + always @(*) begin + case(_zz_56) + `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; + default : _zz_56_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_58) + `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; + default : _zz_58_string = "????"; + endcase + end + always @(*) begin + case(_zz_100) + `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; + default : _zz_100_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_101) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; + default : _zz_101_string = "????????"; + endcase + end + always @(*) begin + case(_zz_102) + `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; + default : _zz_102_string = "???"; + endcase + end + always @(*) begin + case(_zz_103) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; + default : _zz_103_string = "?????"; + endcase + end + always @(*) begin + case(_zz_104) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; + default : _zz_104_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_105) + `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; + default : _zz_105_string = "????"; + endcase + end + always @(*) begin + case(_zz_106) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; + default : _zz_106_string = "?????"; + endcase + end + always @(*) begin + case(_zz_107) + `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; + default : _zz_107_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_294) + $signed(_zz_302)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign execute_SHIFT_RIGHT = _zz_304; + assign execute_REGFILE_WRITE_DATA = _zz_109; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_230[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_306[0]; + assign decode_IS_RS1_SIGNED = _zz_307[0]; + assign decode_IS_DIV = _zz_308[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_309[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; + assign _zz_2 = _zz_3; + assign decode_CfuPlugin_CFU_ENABLE = _zz_310[0]; + assign _zz_4 = _zz_5; + assign _zz_6 = _zz_7; + assign decode_ENV_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_IS_CSR = _zz_311[0]; + assign _zz_11 = _zz_12; + assign _zz_13 = _zz_14; + assign decode_SHIFT_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_ALU_BITWISE_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_SRC_LESS_UNSIGNED = _zz_312[0]; + assign decode_MEMORY_MANAGMENT = _zz_313[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_314[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_315[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_316[0]; + assign decode_SRC2_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_ALU_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_SRC1_CTRL = _zz_27; + assign _zz_28 = _zz_29; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_317[0]; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + always @ (*) begin + _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck)begin + _zz_30 = 1'b0; + end + end + + always @ (*) begin + _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck)begin + _zz_31 = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_33; + assign execute_ENV_CTRL = _zz_34; + assign writeBack_ENV_CTRL = _zz_35; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_131; + assign execute_BRANCH_CTRL = _zz_36; + assign decode_RS2_USE = _zz_318[0]; + assign decode_RS1_USE = _zz_319[0]; + always @ (*) begin + _zz_37 = execute_REGFILE_WRITE_DATA; + if(_zz_251)begin + _zz_37 = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_122; + end + end + if(_zz_252)begin + if(_zz_253)begin + if(_zz_124)begin + decode_RS2 = _zz_57; + end + end + end + if(_zz_254)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_126)begin + decode_RS2 = _zz_38; + end + end + end + if(_zz_255)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_128)begin + decode_RS2 = _zz_37; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_122; + end + end + if(_zz_252)begin + if(_zz_253)begin + if(_zz_123)begin + decode_RS1 = _zz_57; + end + end + end + if(_zz_254)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_125)begin + decode_RS1 = _zz_38; + end + end + end + if(_zz_255)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_127)begin + decode_RS1 = _zz_37; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_38 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_38 = _zz_117; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_38 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_256)begin + _zz_38 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_39; + assign execute_SHIFT_CTRL = _zz_40; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_41 = execute_PC; + assign execute_SRC2_CTRL = _zz_42; + assign execute_SRC1_CTRL = _zz_43; + assign decode_SRC_USE_SUB_LESS = _zz_320[0]; + assign decode_SRC_ADD_ZERO = _zz_321[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_44; + assign execute_SRC2 = _zz_115; + assign execute_SRC1 = _zz_110; + assign execute_ALU_BITWISE_CTRL = _zz_45; + assign _zz_46 = writeBack_INSTRUCTION; + assign _zz_47 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_48 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_48 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_322[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}} != 22'h0); + always @ (*) begin + _zz_57 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_293) + 2'b00 : begin + _zz_57 = _zz_368; + end + default : begin + _zz_57 = _zz_369; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_323[0]; + assign decode_FLUSH_ALL = _zz_324[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_257)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_258)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_259)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_260)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_58; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_59 = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_59 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_60 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + case(_zz_179) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_261)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_261)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((_zz_246 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_262)begin + if((! execute_CsrPlugin_wfiWake))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_251)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_263)begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(_zz_264)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushIt = 1'b0; + if(_zz_263)begin + if(_zz_265)begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_264)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_263)begin + if(_zz_265)begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if((! memory_CfuPlugin_rsp_valid))begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_256)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(CfuPlugin_joinException_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(CfuPlugin_joinException_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_266)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_267)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_266)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_267)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_263)begin + if(_zz_265)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_268)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + _zz_61 = 1'b0; + if(DebugPlugin_godmode)begin + _zz_61 = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_262)begin + CsrPlugin_inWfi = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_266)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_267)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_266)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_267)begin + case(_zz_269) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode)begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + end + end + + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_63 = (_zz_62 & (~ _zz_325)); + assign _zz_64 = _zz_63[3]; + assign _zz_65 = (_zz_63[1] || _zz_64); + assign _zz_66 = (_zz_63[2] || _zz_64); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_250; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_327); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_69 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_69); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_69); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_70; + assign _zz_70 = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_71 = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_73)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_73 = _zz_74; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_73; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_75; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + always @ (*) begin + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_179) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + end + + assign _zz_76 = _zz_328[11]; + always @ (*) begin + _zz_77[18] = _zz_76; + _zz_77[17] = _zz_76; + _zz_77[16] = _zz_76; + _zz_77[15] = _zz_76; + _zz_77[14] = _zz_76; + _zz_77[13] = _zz_76; + _zz_77[12] = _zz_76; + _zz_77[11] = _zz_76; + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7] = _zz_76; + _zz_77[6] = _zz_76; + _zz_77[5] = _zz_76; + _zz_77[4] = _zz_76; + _zz_77[3] = _zz_76; + _zz_77[2] = _zz_76; + _zz_77[1] = _zz_76; + _zz_77[0] = _zz_76; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_329[31])); + if(_zz_82)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_78 = _zz_330[19]; + always @ (*) begin + _zz_79[10] = _zz_78; + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7] = _zz_78; + _zz_79[6] = _zz_78; + _zz_79[5] = _zz_78; + _zz_79[4] = _zz_78; + _zz_79[3] = _zz_78; + _zz_79[2] = _zz_78; + _zz_79[1] = _zz_78; + _zz_79[0] = _zz_78; + end + + assign _zz_80 = _zz_331[11]; + always @ (*) begin + _zz_81[18] = _zz_80; + _zz_81[17] = _zz_80; + _zz_81[16] = _zz_80; + _zz_81[15] = _zz_80; + _zz_81[14] = _zz_80; + _zz_81[13] = _zz_80; + _zz_81[12] = _zz_80; + _zz_81[11] = _zz_80; + _zz_81[10] = _zz_80; + _zz_81[9] = _zz_80; + _zz_81[8] = _zz_80; + _zz_81[7] = _zz_80; + _zz_81[6] = _zz_80; + _zz_81[5] = _zz_80; + _zz_81[4] = _zz_80; + _zz_81[3] = _zz_80; + _zz_81[2] = _zz_80; + _zz_81[1] = _zz_80; + _zz_81[0] = _zz_80; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_82 = _zz_332[1]; + end + default : begin + _zz_82 = _zz_333[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_83 = _zz_334[19]; + always @ (*) begin + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7] = _zz_83; + _zz_84[6] = _zz_83; + _zz_84[5] = _zz_83; + _zz_84[4] = _zz_83; + _zz_84[3] = _zz_83; + _zz_84[2] = _zz_83; + _zz_84[1] = _zz_83; + _zz_84[0] = _zz_83; + end + + assign _zz_85 = _zz_335[11]; + always @ (*) begin + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7] = _zz_85; + _zz_86[6] = _zz_85; + _zz_86[5] = _zz_85; + _zz_86[4] = _zz_85; + _zz_86[3] = _zz_85; + _zz_86[2] = _zz_85; + _zz_86[1] = _zz_85; + _zz_86[0] = _zz_85; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_414,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_415,_zz_416},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_222; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_225 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_226 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_227 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_260)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_258)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_228 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_258)begin + _zz_228 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_259)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_257)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_259)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_257)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_220 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_247 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_229 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_230 = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_89 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_89 = execute_RS2[31 : 0]; + end + endcase + end + + assign _zz_246 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_231 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_232 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_231; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_232; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @ (*) begin + _zz_233 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_233 = 1'b1; + end + end + + assign _zz_234 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_235 = (CsrPlugin_privilege == 2'b00); + assign _zz_236 = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_270)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_270)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_270)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_90 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_91[31] = _zz_90; + _zz_91[30] = _zz_90; + _zz_91[29] = _zz_90; + _zz_91[28] = _zz_90; + _zz_91[27] = _zz_90; + _zz_91[26] = _zz_90; + _zz_91[25] = _zz_90; + _zz_91[24] = _zz_90; + _zz_91[23] = _zz_90; + _zz_91[22] = _zz_90; + _zz_91[21] = _zz_90; + _zz_91[20] = _zz_90; + _zz_91[19] = _zz_90; + _zz_91[18] = _zz_90; + _zz_91[17] = _zz_90; + _zz_91[16] = _zz_90; + _zz_91[15] = _zz_90; + _zz_91[14] = _zz_90; + _zz_91[13] = _zz_90; + _zz_91[12] = _zz_90; + _zz_91[11] = _zz_90; + _zz_91[10] = _zz_90; + _zz_91[9] = _zz_90; + _zz_91[8] = _zz_90; + _zz_91[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_92 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_93[31] = _zz_92; + _zz_93[30] = _zz_92; + _zz_93[29] = _zz_92; + _zz_93[28] = _zz_92; + _zz_93[27] = _zz_92; + _zz_93[26] = _zz_92; + _zz_93[25] = _zz_92; + _zz_93[24] = _zz_92; + _zz_93[23] = _zz_92; + _zz_93[22] = _zz_92; + _zz_93[21] = _zz_92; + _zz_93[20] = _zz_92; + _zz_93[19] = _zz_92; + _zz_93[18] = _zz_92; + _zz_93[17] = _zz_92; + _zz_93[16] = _zz_92; + _zz_93[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_291) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_91; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_93; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_96 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_94 = {(((decode_INSTRUCTION & _zz_417) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}; + assign _zz_100 = _zz_94[2 : 1]; + assign _zz_56 = _zz_100; + assign _zz_101 = _zz_94[7 : 6]; + assign _zz_55 = _zz_101; + assign _zz_102 = _zz_94[9 : 8]; + assign _zz_54 = _zz_102; + assign _zz_103 = _zz_94[19 : 18]; + assign _zz_53 = _zz_103; + assign _zz_104 = _zz_94[22 : 21]; + assign _zz_52 = _zz_104; + assign _zz_105 = _zz_94[24 : 23]; + assign _zz_51 = _zz_105; + assign _zz_106 = _zz_94[27 : 26]; + assign _zz_50 = _zz_106; + assign _zz_107 = _zz_94[29 : 29]; + assign _zz_49 = _zz_107; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_248; + assign decode_RegFilePlugin_rs2Data = _zz_249; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); + if(_zz_108)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; + if(_zz_108)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_57; + if(_zz_108)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_109 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_109 = {31'd0, _zz_338}; + end + default : begin + _zz_109 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_110 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_110 = {29'd0, _zz_339}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_110 = {27'd0, _zz_340}; + end + endcase + end + + assign _zz_111 = _zz_341[11]; + always @ (*) begin + _zz_112[19] = _zz_111; + _zz_112[18] = _zz_111; + _zz_112[17] = _zz_111; + _zz_112[16] = _zz_111; + _zz_112[15] = _zz_111; + _zz_112[14] = _zz_111; + _zz_112[13] = _zz_111; + _zz_112[12] = _zz_111; + _zz_112[11] = _zz_111; + _zz_112[10] = _zz_111; + _zz_112[9] = _zz_111; + _zz_112[8] = _zz_111; + _zz_112[7] = _zz_111; + _zz_112[6] = _zz_111; + _zz_112[5] = _zz_111; + _zz_112[4] = _zz_111; + _zz_112[3] = _zz_111; + _zz_112[2] = _zz_111; + _zz_112[1] = _zz_111; + _zz_112[0] = _zz_111; + end + + assign _zz_113 = _zz_342[11]; + always @ (*) begin + _zz_114[19] = _zz_113; + _zz_114[18] = _zz_113; + _zz_114[17] = _zz_113; + _zz_114[16] = _zz_113; + _zz_114[15] = _zz_113; + _zz_114[14] = _zz_113; + _zz_114[13] = _zz_113; + _zz_114[12] = _zz_113; + _zz_114[11] = _zz_113; + _zz_114[10] = _zz_113; + _zz_114[9] = _zz_113; + _zz_114[8] = _zz_113; + _zz_114[7] = _zz_113; + _zz_114[6] = _zz_113; + _zz_114[5] = _zz_113; + _zz_114[4] = _zz_113; + _zz_114[3] = _zz_113; + _zz_114[2] = _zz_113; + _zz_114[1] = _zz_113; + _zz_114[0] = _zz_113; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_115 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_115 = _zz_41; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_343; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_116[0] = execute_SRC1[31]; + _zz_116[1] = execute_SRC1[30]; + _zz_116[2] = execute_SRC1[29]; + _zz_116[3] = execute_SRC1[28]; + _zz_116[4] = execute_SRC1[27]; + _zz_116[5] = execute_SRC1[26]; + _zz_116[6] = execute_SRC1[25]; + _zz_116[7] = execute_SRC1[24]; + _zz_116[8] = execute_SRC1[23]; + _zz_116[9] = execute_SRC1[22]; + _zz_116[10] = execute_SRC1[21]; + _zz_116[11] = execute_SRC1[20]; + _zz_116[12] = execute_SRC1[19]; + _zz_116[13] = execute_SRC1[18]; + _zz_116[14] = execute_SRC1[17]; + _zz_116[15] = execute_SRC1[16]; + _zz_116[16] = execute_SRC1[15]; + _zz_116[17] = execute_SRC1[14]; + _zz_116[18] = execute_SRC1[13]; + _zz_116[19] = execute_SRC1[12]; + _zz_116[20] = execute_SRC1[11]; + _zz_116[21] = execute_SRC1[10]; + _zz_116[22] = execute_SRC1[9]; + _zz_116[23] = execute_SRC1[8]; + _zz_116[24] = execute_SRC1[7]; + _zz_116[25] = execute_SRC1[6]; + _zz_116[26] = execute_SRC1[5]; + _zz_116[27] = execute_SRC1[4]; + _zz_116[28] = execute_SRC1[3]; + _zz_116[29] = execute_SRC1[2]; + _zz_116[30] = execute_SRC1[1]; + _zz_116[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); + always @ (*) begin + _zz_117[0] = memory_SHIFT_RIGHT[31]; + _zz_117[1] = memory_SHIFT_RIGHT[30]; + _zz_117[2] = memory_SHIFT_RIGHT[29]; + _zz_117[3] = memory_SHIFT_RIGHT[28]; + _zz_117[4] = memory_SHIFT_RIGHT[27]; + _zz_117[5] = memory_SHIFT_RIGHT[26]; + _zz_117[6] = memory_SHIFT_RIGHT[25]; + _zz_117[7] = memory_SHIFT_RIGHT[24]; + _zz_117[8] = memory_SHIFT_RIGHT[23]; + _zz_117[9] = memory_SHIFT_RIGHT[22]; + _zz_117[10] = memory_SHIFT_RIGHT[21]; + _zz_117[11] = memory_SHIFT_RIGHT[20]; + _zz_117[12] = memory_SHIFT_RIGHT[19]; + _zz_117[13] = memory_SHIFT_RIGHT[18]; + _zz_117[14] = memory_SHIFT_RIGHT[17]; + _zz_117[15] = memory_SHIFT_RIGHT[16]; + _zz_117[16] = memory_SHIFT_RIGHT[15]; + _zz_117[17] = memory_SHIFT_RIGHT[14]; + _zz_117[18] = memory_SHIFT_RIGHT[13]; + _zz_117[19] = memory_SHIFT_RIGHT[12]; + _zz_117[20] = memory_SHIFT_RIGHT[11]; + _zz_117[21] = memory_SHIFT_RIGHT[10]; + _zz_117[22] = memory_SHIFT_RIGHT[9]; + _zz_117[23] = memory_SHIFT_RIGHT[8]; + _zz_117[24] = memory_SHIFT_RIGHT[7]; + _zz_117[25] = memory_SHIFT_RIGHT[6]; + _zz_117[26] = memory_SHIFT_RIGHT[5]; + _zz_117[27] = memory_SHIFT_RIGHT[4]; + _zz_117[28] = memory_SHIFT_RIGHT[3]; + _zz_117[29] = memory_SHIFT_RIGHT[2]; + _zz_117[30] = memory_SHIFT_RIGHT[1]; + _zz_117[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_118 = 1'b0; + if(_zz_271)begin + if(_zz_272)begin + if(_zz_123)begin + _zz_118 = 1'b1; + end + end + end + if(_zz_273)begin + if(_zz_274)begin + if(_zz_125)begin + _zz_118 = 1'b1; + end + end + end + if(_zz_275)begin + if(_zz_276)begin + if(_zz_127)begin + _zz_118 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_118 = 1'b0; + end + end + + always @ (*) begin + _zz_119 = 1'b0; + if(_zz_271)begin + if(_zz_272)begin + if(_zz_124)begin + _zz_119 = 1'b1; + end + end + end + if(_zz_273)begin + if(_zz_274)begin + if(_zz_126)begin + _zz_119 = 1'b1; + end + end + end + if(_zz_275)begin + if(_zz_276)begin + if(_zz_128)begin + _zz_119 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_119 = 1'b0; + end + end + + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_129 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_129 == 3'b000)) begin + _zz_130 = execute_BranchPlugin_eq; + end else if((_zz_129 == 3'b001)) begin + _zz_130 = (! execute_BranchPlugin_eq); + end else if((((_zz_129 & 3'b101) == 3'b101))) begin + _zz_130 = (! execute_SRC_LESS); + end else begin + _zz_130 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_131 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_131 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_131 = 1'b1; + end + default : begin + _zz_131 = _zz_130; + end + endcase + end + + assign _zz_132 = _zz_350[11]; + always @ (*) begin + _zz_133[19] = _zz_132; + _zz_133[18] = _zz_132; + _zz_133[17] = _zz_132; + _zz_133[16] = _zz_132; + _zz_133[15] = _zz_132; + _zz_133[14] = _zz_132; + _zz_133[13] = _zz_132; + _zz_133[12] = _zz_132; + _zz_133[11] = _zz_132; + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; + end + + assign _zz_134 = _zz_351[19]; + always @ (*) begin + _zz_135[10] = _zz_134; + _zz_135[9] = _zz_134; + _zz_135[8] = _zz_134; + _zz_135[7] = _zz_134; + _zz_135[6] = _zz_134; + _zz_135[5] = _zz_134; + _zz_135[4] = _zz_134; + _zz_135[3] = _zz_134; + _zz_135[2] = _zz_134; + _zz_135[1] = _zz_134; + _zz_135[0] = _zz_134; + end + + assign _zz_136 = _zz_352[11]; + always @ (*) begin + _zz_137[18] = _zz_136; + _zz_137[17] = _zz_136; + _zz_137[16] = _zz_136; + _zz_137[15] = _zz_136; + _zz_137[14] = _zz_136; + _zz_137[13] = _zz_136; + _zz_137[12] = _zz_136; + _zz_137[11] = _zz_136; + _zz_137[10] = _zz_136; + _zz_137[9] = _zz_136; + _zz_137[8] = _zz_136; + _zz_137[7] = _zz_136; + _zz_137[6] = _zz_136; + _zz_137[5] = _zz_136; + _zz_137[4] = _zz_136; + _zz_137[3] = _zz_136; + _zz_137[2] = _zz_136; + _zz_137[1] = _zz_136; + _zz_137[0] = _zz_136; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_138 = (_zz_353[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_138 = _zz_354[1]; + end + default : begin + _zz_138 = _zz_355[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_139 = _zz_356[11]; + always @ (*) begin + _zz_140[19] = _zz_139; + _zz_140[18] = _zz_139; + _zz_140[17] = _zz_139; + _zz_140[16] = _zz_139; + _zz_140[15] = _zz_139; + _zz_140[14] = _zz_139; + _zz_140[13] = _zz_139; + _zz_140[12] = _zz_139; + _zz_140[11] = _zz_139; + _zz_140[10] = _zz_139; + _zz_140[9] = _zz_139; + _zz_140[8] = _zz_139; + _zz_140[7] = _zz_139; + _zz_140[6] = _zz_139; + _zz_140[5] = _zz_139; + _zz_140[4] = _zz_139; + _zz_140[3] = _zz_139; + _zz_140[2] = _zz_139; + _zz_140[1] = _zz_139; + _zz_140[0] = _zz_139; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_594,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_595,_zz_596},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_359}; + end + end + endcase + end + + assign _zz_141 = _zz_357[19]; + always @ (*) begin + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; + end + + assign _zz_143 = _zz_358[11]; + always @ (*) begin + _zz_144[18] = _zz_143; + _zz_144[17] = _zz_143; + _zz_144[16] = _zz_143; + _zz_144[15] = _zz_143; + _zz_144[14] = _zz_143; + _zz_144[13] = _zz_143; + _zz_144[12] = _zz_143; + _zz_144[11] = _zz_143; + _zz_144[10] = _zz_143; + _zz_144[9] = _zz_143; + _zz_144[8] = _zz_143; + _zz_144[7] = _zz_143; + _zz_144[6] = _zz_143; + _zz_144[5] = _zz_143; + _zz_144[4] = _zz_143; + _zz_144[3] = _zz_143; + _zz_144[2] = _zz_143; + _zz_144[1] = _zz_143; + _zz_144[0] = _zz_143; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_149 = _zz_360[0]; + assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_151 = _zz_362[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_261)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_264)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2820)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2822)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2824)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2826)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2828)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2830)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_277)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_278)begin + CsrPlugin_selfException_valid = 1'b1; + end + if(_zz_279)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_278)begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(_zz_279)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_277)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_277)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_292) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign execute_CfuPlugin_functionsIds_0 = _zz_364; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_168 = _zz_365[7]; + always @ (*) begin + _zz_169[23] = _zz_168; + _zz_169[22] = _zz_168; + _zz_169[21] = _zz_168; + _zz_169[20] = _zz_168; + _zz_169[19] = _zz_168; + _zz_169[18] = _zz_168; + _zz_169[17] = _zz_168; + _zz_169[16] = _zz_168; + _zz_169[15] = _zz_168; + _zz_169[14] = _zz_168; + _zz_169[13] = _zz_168; + _zz_169[12] = _zz_168; + _zz_169[11] = _zz_168; + _zz_169[10] = _zz_168; + _zz_169[9] = _zz_168; + _zz_169[8] = _zz_168; + _zz_169[7] = _zz_168; + _zz_169[6] = _zz_168; + _zz_169[5] = _zz_168; + _zz_169[4] = _zz_168; + _zz_169[3] = _zz_168; + _zz_169[2] = _zz_168; + _zz_169[1] = _zz_168; + _zz_169[0] = _zz_168; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : begin + _zz_170 = execute_RS2; + end + default : begin + _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; + assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); + assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); + assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @ (*) begin + CfuPlugin_joinException_valid = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if(memory_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); + end + end + end + + assign CfuPlugin_joinException_payload_code = 4'b1111; + assign CfuPlugin_joinException_payload_badAddr = 32'h0; + always @ (*) begin + memory_CfuPlugin_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_280) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_280) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_366) + $signed(_zz_367)); + assign memory_DivPlugin_frontendOk = 1'b1; + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_256)begin + if(_zz_281)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_282)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_372); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_373 : _zz_374); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_375[31:0]; + assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_175[31 : 0] = execute_RS1; + end + + assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_177 != 32'h0); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_283) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_178))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + always @ (*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_283) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_29 = decode_SRC1_CTRL; + assign _zz_27 = _zz_56; + assign _zz_43 = decode_to_execute_SRC1_CTRL; + assign _zz_26 = decode_ALU_CTRL; + assign _zz_24 = _zz_55; + assign _zz_44 = decode_to_execute_ALU_CTRL; + assign _zz_23 = decode_SRC2_CTRL; + assign _zz_21 = _zz_54; + assign _zz_42 = decode_to_execute_SRC2_CTRL; + assign _zz_20 = decode_ALU_BITWISE_CTRL; + assign _zz_18 = _zz_53; + assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_17 = decode_SHIFT_CTRL; + assign _zz_14 = execute_SHIFT_CTRL; + assign _zz_15 = _zz_52; + assign _zz_40 = decode_to_execute_SHIFT_CTRL; + assign _zz_39 = execute_to_memory_SHIFT_CTRL; + assign _zz_12 = decode_BRANCH_CTRL; + assign _zz_58 = _zz_51; + assign _zz_36 = decode_to_execute_BRANCH_CTRL; + assign _zz_10 = decode_ENV_CTRL; + assign _zz_7 = execute_ENV_CTRL; + assign _zz_5 = memory_ENV_CTRL; + assign _zz_8 = _zz_50; + assign _zz_34 = decode_to_execute_ENV_CTRL; + assign _zz_33 = execute_to_memory_ENV_CTRL; + assign _zz_35 = memory_to_writeBack_ENV_CTRL; + assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_1 = _zz_49; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(_zz_179) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_180[12 : 0] = 13'h1000; + _zz_180[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_181[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_182[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_183[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_184 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_184[31 : 30] = CsrPlugin_misa_base; + _zz_184[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_185 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_186 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_186[11 : 11] = CsrPlugin_mip_MEIP; + _zz_186[7 : 7] = CsrPlugin_mip_MTIP; + _zz_186[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_187 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_187[11 : 11] = CsrPlugin_mie_MEIE; + _zz_187[7 : 7] = CsrPlugin_mie_MTIE; + _zz_187[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_188 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_188[31 : 2] = CsrPlugin_mtvec_base; + _zz_188[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_189 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_189[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_190 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_190[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_191 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_192 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_192[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_193 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_194 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_195 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_196 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_197 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_198 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_199 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_200 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_201 = 32'h0; + if(execute_CsrPlugin_csr_2820)begin + _zz_201[31 : 0] = _zz_152; + end + end + + always @ (*) begin + _zz_202 = 32'h0; + if(execute_CsrPlugin_csr_2822)begin + _zz_202[31 : 0] = _zz_154; + end + end + + always @ (*) begin + _zz_203 = 32'h0; + if(execute_CsrPlugin_csr_2824)begin + _zz_203[31 : 0] = _zz_156; + end + end + + always @ (*) begin + _zz_204 = 32'h0; + if(execute_CsrPlugin_csr_2826)begin + _zz_204[31 : 0] = _zz_158; + end + end + + always @ (*) begin + _zz_205 = 32'h0; + if(execute_CsrPlugin_csr_2828)begin + _zz_205[31 : 0] = _zz_160; + end + end + + always @ (*) begin + _zz_206 = 32'h0; + if(execute_CsrPlugin_csr_2830)begin + _zz_206[31 : 0] = _zz_162; + end + end + + always @ (*) begin + _zz_207 = 32'h0; + if(execute_CsrPlugin_csr_2832)begin + _zz_207[31 : 0] = _zz_164; + end + end + + always @ (*) begin + _zz_208 = 32'h0; + if(execute_CsrPlugin_csr_2834)begin + _zz_208[31 : 0] = _zz_166; + end + end + + always @ (*) begin + _zz_209 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_209[31 : 0] = _zz_176; + end + end + + always @ (*) begin + _zz_210 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_210[31 : 0] = _zz_177; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_597 | _zz_184) | (_zz_185 | _zz_186))) | (((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194)))) | ((((_zz_195 | _zz_196) | (_zz_197 | _zz_198)) | ((_zz_199 | _zz_200) | (_zz_201 | _zz_202))) | (((_zz_203 | _zz_204) | (_zz_205 | _zz_206)) | ((_zz_207 | _zz_208) | (_zz_209 | _zz_210))))); + assign iBusWishbone_ADR = {_zz_392,_zz_211}; + assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'h0; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_284)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_284)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_212; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_218 = (dBus_cmd_payload_length != 3'b000); + assign _zz_214 = dBus_cmd_valid; + assign _zz_216 = dBus_cmd_payload_wr; + assign _zz_217 = (_zz_213 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_215 && (_zz_216 || _zz_217)); + assign dBusWishbone_ADR = ((_zz_218 ? {{dBus_cmd_payload_address[31 : 5],_zz_213},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_218 ? (_zz_217 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_216 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_216; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_215 = (_zz_214 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_214; + assign dBusWishbone_STB = _zz_214; + assign dBus_rsp_valid = _zz_219; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_72 <= 1'b0; + _zz_74 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_87; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_88; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_108 <= 1'b1; + _zz_120 <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_CfuPlugin_hold <= 1'b0; + execute_CfuPlugin_fired <= 1'b0; + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_176 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_179 <= 3'b000; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; + _zz_211 <= 3'b000; + _zz_212 <= 1'b0; + _zz_213 <= 3'b000; + _zz_219 <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_72 <= 1'b0; + end + if(_zz_70)begin + _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_74 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_74 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(_zz_285)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_108 <= 1'b0; + _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_286)begin + if(_zz_287)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_288)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_289)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_266)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_267)begin + case(_zz_269) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(execute_CfuPlugin_schedule)begin + execute_CfuPlugin_hold <= 1'b1; + end + if(CfuPlugin_bus_cmd_ready)begin + execute_CfuPlugin_hold <= 1'b0; + end + if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + execute_CfuPlugin_fired <= 1'b1; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_CfuPlugin_fired <= 1'b0; + end + if(memory_CfuPlugin_rsp_ready)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + end + if(_zz_290)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + end + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! memory_arbitration_isStuck))begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_179) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_179 <= 3'b001; + end + end + 3'b001 : begin + _zz_179 <= 3'b010; + end + 3'b010 : begin + _zz_179 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_179 <= 3'b100; + end + end + 3'b100 : begin + _zz_179 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_385[0]; + CsrPlugin_mstatus_MIE <= _zz_386[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_388[0]; + CsrPlugin_mie_MTIE <= _zz_389[0]; + CsrPlugin_mie_MSIE <= _zz_390[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_284)begin + if(iBusWishbone_ACK)begin + _zz_211 <= (_zz_211 + 3'b001); + end + end + _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_214 && _zz_215))begin + _zz_213 <= (_zz_213 + 3'b001); + if(_zz_217)begin + _zz_213 <= 3'b000; + end + end + _zz_219 <= ((_zz_214 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_75 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_285)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + _zz_121 <= _zz_46[11 : 7]; + _zz_122 <= _zz_57; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_261)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_264)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + end + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_286)begin + if(_zz_287)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_288)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_289)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_266)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(_zz_153[0])begin + _zz_152 <= (_zz_152 + 32'h00000001); + end + if(_zz_155[0])begin + _zz_154 <= (_zz_154 + 32'h00000001); + end + if(_zz_157[0])begin + _zz_156 <= (_zz_156 + 32'h00000001); + end + if(_zz_159[0])begin + _zz_158 <= (_zz_158 + 32'h00000001); + end + if(_zz_161[0])begin + _zz_160 <= (_zz_160 + 32'h00000001); + end + if(_zz_163[0])begin + _zz_162 <= (_zz_162 + 32'h00000001); + end + if(_zz_165[0])begin + _zz_164 <= (_zz_164 + 32'h00000001); + end + if(_zz_167[0])begin + _zz_166 <= (_zz_166 + 32'h00000001); + end + if(_zz_290)begin + CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_256)begin + if(_zz_281)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_376[31:0]; + end + end + end + if(_zz_282)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_382); + memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_384); + memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_41; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_28; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_16; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_13; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_387[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_391[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_57; + end + _zz_178 <= debug_bus_cmd_payload_address[2]; + if(_zz_263)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_283) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(_zz_263)begin + if(_zz_265)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_268)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_19; + reg [31:0] _zz_20; + reg [21:0] _zz_21; + reg [31:0] _zz_22; + wire _zz_23; + wire _zz_24; + wire _zz_25; + wire _zz_26; + wire _zz_27; + wire _zz_28; + wire _zz_29; + wire [0:0] _zz_30; + wire [0:0] _zz_31; + wire [0:0] _zz_32; + wire [0:0] _zz_33; + wire [0:0] _zz_34; + wire [0:0] _zz_35; + wire [2:0] _zz_36; + wire [2:0] _zz_37; + wire [21:0] _zz_38; + wire [21:0] _zz_39; + reg _zz_1; + reg _zz_2; + reg _zz_3; + reg _zz_4; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [1:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [1:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [1:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_5; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_6; + wire _zz_7; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire _zz_8; + wire ways_1_tagsReadRsp_valid; + wire ways_1_tagsReadRsp_error; + wire [19:0] ways_1_tagsReadRsp_address; + wire [21:0] _zz_9; + wire _zz_10; + wire [31:0] ways_1_dataReadRspMem; + wire [31:0] ways_1_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_11; + wire [3:0] stage0_mask; + reg [1:0] stage0_dataColisions; + wire [9:0] _zz_12; + wire [3:0] _zz_13; + wire [1:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [1:0] stageA_wayHits; + reg [1:0] _zz_14; + reg [1:0] stageA_wayInvalidate; + reg [1:0] stage0_dataColisions_regNextWhen; + reg [1:0] _zz_15; + wire [9:0] _zz_16; + wire [3:0] _zz_17; + wire [1:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg stageB_tagsReadRsp_1_valid; + reg stageB_tagsReadRsp_1_error; + reg [19:0] stageB_tagsReadRsp_1_address; + reg [31:0] stageB_dataReadRsp_0; + reg [31:0] stageB_dataReadRsp_1; + reg [1:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [1:0] stageB_dataColisions; + reg stageB_unaligned; + reg [1:0] stageB_waysHitsBeforeInvalidate; + wire [1:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + reg [1:0] _zz_18; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [1:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_40; + reg [7:0] _zz_41; + reg [7:0] _zz_42; + reg [7:0] _zz_43; + (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_1_data_symbol3 [0:1023]; + reg [7:0] _zz_44; + reg [7:0] _zz_45; + reg [7:0] _zz_46; + reg [7:0] _zz_47; + + assign _zz_23 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_24 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_25 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_26 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_27 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_28 = (! stageB_flusher_hold); + assign _zz_29 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_30 = _zz_6[0 : 0]; + assign _zz_31 = _zz_6[1 : 1]; + assign _zz_32 = _zz_9[0 : 0]; + assign _zz_33 = _zz_9[1 : 1]; + assign _zz_34 = 1'b1; + assign _zz_35 = loader_counter_willIncrement; + assign _zz_36 = {2'd0, _zz_35}; + assign _zz_37 = {loader_waysAllocator,loader_waysAllocator[1]}; + assign _zz_38 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + assign _zz_39 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_5) begin + _zz_19 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_4) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_38; + end + end + + always @ (*) begin + _zz_20 = {_zz_43, _zz_42, _zz_41, _zz_40}; + end + always @ (posedge clk) begin + if(_zz_7) begin + _zz_40 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_41 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_42 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_43 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_3) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_3) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_3) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_3) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (posedge clk) begin + if(_zz_8) begin + _zz_21 <= ways_1_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_1_tags[tagsWriteCmd_payload_address] <= _zz_39; + end + end + + always @ (*) begin + _zz_22 = {_zz_47, _zz_46, _zz_45, _zz_44}; + end + always @ (posedge clk) begin + if(_zz_10) begin + _zz_44 <= ways_1_data_symbol0[dataReadCmd_payload]; + _zz_45 <= ways_1_data_symbol1[dataReadCmd_payload]; + _zz_46 <= ways_1_data_symbol2[dataReadCmd_payload]; + _zz_47 <= ways_1_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_1_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_1_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_1_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_1_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[1]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[1]))begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + _zz_3 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_3 = 1'b1; + end + end + + always @ (*) begin + _zz_4 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_4 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_5 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_6 = _zz_19; + assign ways_0_tagsReadRsp_valid = _zz_30[0]; + assign ways_0_tagsReadRsp_error = _zz_31[0]; + assign ways_0_tagsReadRsp_address = _zz_6[21 : 2]; + assign _zz_7 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_20; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + assign _zz_8 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_9 = _zz_21; + assign ways_1_tagsReadRsp_valid = _zz_32[0]; + assign ways_1_tagsReadRsp_error = _zz_33[0]; + assign ways_1_tagsReadRsp_address = _zz_9[21 : 2]; + assign _zz_10 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_1_dataReadRspMem = _zz_22; + assign ways_1_dataReadRsp = ways_1_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_23)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_23)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_23)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_23)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_24)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 2'bxx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 2'b11; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + if(_zz_24)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_25)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 2'bxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_25)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_25)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_25)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_34[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(_zz_25)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_11 = 4'b0001; + end + 2'b01 : begin + _zz_11 = 4'b0011; + end + default : begin + _zz_11 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_11 <<< io_cpu_execute_address[1 : 0]); + assign _zz_12 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_13 = dataWriteCmd_payload_mask[3 : 0]; + always @ (*) begin + stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); + stage0_dataColisions[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); + end + + assign stage0_wayInvalidate = 2'b00; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + always @ (*) begin + _zz_14[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + _zz_14[1] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_1_tagsReadRsp_address) && ways_1_tagsReadRsp_valid); + end + + assign stageA_wayHits = _zz_14; + assign _zz_16 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_17 = dataWriteCmd_payload_mask[3 : 0]; + always @ (*) begin + _zz_15[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); + _zz_15[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); + end + + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_15); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 2'b00); + assign stageB_dataMux = (stageB_waysHits[0] ? stageB_dataReadRsp_0 : stageB_dataReadRsp_1); + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(! _zz_27) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(_zz_24)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_26)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_27)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(_zz_24)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(_zz_27)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(_zz_27)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 2'b00)))begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_18) != 2'b00) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_26)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_27)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(_zz_24)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(_zz_27)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(_zz_27)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_26) begin + if(! _zz_27) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + always @ (*) begin + _zz_18[0] = stageB_tagsReadRsp_0_error; + _zz_18[1] = stageB_tagsReadRsp_1_error; + end + + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_25)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_36); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_1_valid <= ways_1_tagsReadRsp_valid; + stageB_tagsReadRsp_1_error <= ways_1_tagsReadRsp_error; + stageB_tagsReadRsp_1_address <= ways_1_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_1 <= ways_1_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_28)begin + if(_zz_29)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 2'b01; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_28)begin + if(! _zz_29) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_25)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_37[1:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_16, + input [31:0] _zz_17, + input clk, + input reset +); + reg [31:0] _zz_18; + reg [31:0] _zz_19; + reg [21:0] _zz_20; + reg [21:0] _zz_21; + reg _zz_22; + reg [31:0] _zz_23; + wire _zz_24; + wire _zz_25; + wire [0:0] _zz_26; + wire [0:0] _zz_27; + wire [0:0] _zz_28; + wire [0:0] _zz_29; + wire [21:0] _zz_30; + wire [21:0] _zz_31; + reg _zz_1; + reg _zz_2; + reg _zz_3; + reg _zz_4; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_5; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + reg [0:0] lineLoader_wayToAllocate_valueNext; + reg [0:0] lineLoader_wayToAllocate_value; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_tag_1_valid; + wire [6:0] lineLoader_write_tag_1_payload_address; + wire lineLoader_write_tag_1_payload_data_valid; + wire lineLoader_write_tag_1_payload_data_error; + wire [19:0] lineLoader_write_tag_1_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire lineLoader_write_data_1_valid; + wire [9:0] lineLoader_write_data_1_payload_address; + wire [31:0] lineLoader_write_data_1_payload_data; + wire [9:0] _zz_6; + wire _zz_7; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [9:0] _zz_8; + wire _zz_9; + wire [31:0] fetchStage_read_banksValue_1_dataMem; + wire [31:0] fetchStage_read_banksValue_1_data; + wire [6:0] _zz_10; + wire _zz_11; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_12; + wire [6:0] _zz_13; + wire _zz_14; + wire fetchStage_read_waysValues_1_tag_valid; + wire fetchStage_read_waysValues_1_tag_error; + wire [19:0] fetchStage_read_waysValues_1_tag_address; + wire [21:0] _zz_15; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_hits_1; + wire fetchStage_hit_valid; + wire [0:0] fetchStage_hit_wayId; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; + (* ram_style = "block" *) reg [31:0] banks_1 [0:1023]; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; + + assign _zz_24 = (! lineLoader_flushCounter[7]); + assign _zz_25 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_26 = _zz_12[0 : 0]; + assign _zz_27 = _zz_12[1 : 1]; + assign _zz_28 = _zz_15[0 : 0]; + assign _zz_29 = _zz_15[1 : 1]; + assign _zz_30 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + assign _zz_31 = {lineLoader_write_tag_1_payload_data_address,{lineLoader_write_tag_1_payload_data_error,lineLoader_write_tag_1_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_18 <= banks_0[_zz_6]; + end + end + + always @ (posedge clk) begin + if(_zz_1) begin + banks_1[lineLoader_write_data_1_payload_address] <= lineLoader_write_data_1_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9) begin + _zz_19 <= banks_1[_zz_8]; + end + end + + always @ (posedge clk) begin + if(_zz_4) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_30; + end + end + + always @ (posedge clk) begin + if(_zz_11) begin + _zz_20 <= ways_0_tags[_zz_10]; + end + end + + always @ (posedge clk) begin + if(_zz_3) begin + ways_1_tags[lineLoader_write_tag_1_payload_address] <= _zz_31; + end + end + + always @ (posedge clk) begin + if(_zz_14) begin + _zz_21 <= ways_1_tags[_zz_13]; + end + end + + always @(*) begin + case(fetchStage_hit_wayId) + 1'b0 : begin + _zz_22 = fetchStage_read_waysValues_0_tag_error; + _zz_23 = fetchStage_read_banksValue_0_data; + end + default : begin + _zz_22 = fetchStage_read_waysValues_1_tag_error; + _zz_23 = fetchStage_read_banksValue_1_data; + end + endcase + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_1_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + _zz_3 = 1'b0; + if(lineLoader_write_tag_1_valid)begin + _zz_3 = 1'b1; + end + end + + always @ (*) begin + _zz_4 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_4 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_24)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_5))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = (lineLoader_wayToAllocate_value == 1'b1); + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + always @ (*) begin + lineLoader_wayToAllocate_valueNext = (lineLoader_wayToAllocate_value + lineLoader_wayToAllocate_willIncrement); + if(lineLoader_wayToAllocate_willClear)begin + lineLoader_wayToAllocate_valueNext = 1'b0; + end + end + + assign lineLoader_write_tag_0_valid = (((lineLoader_wayToAllocate_value == 1'b0) && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_tag_1_valid = (((lineLoader_wayToAllocate_value == 1'b1) && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_1_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_1_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_1_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_1_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b0)); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign lineLoader_write_data_1_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b1)); + assign lineLoader_write_data_1_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_1_payload_data = io_mem_rsp_payload_data; + assign _zz_6 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_18; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_8 = io_cpu_prefetch_pc[11 : 2]; + assign _zz_9 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_1_dataMem = _zz_19; + assign fetchStage_read_banksValue_1_data = fetchStage_read_banksValue_1_dataMem[31 : 0]; + assign _zz_10 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_11 = (! io_cpu_fetch_isStuck); + assign _zz_12 = _zz_20; + assign fetchStage_read_waysValues_0_tag_valid = _zz_26[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_27[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_12[21 : 2]; + assign _zz_13 = io_cpu_prefetch_pc[11 : 5]; + assign _zz_14 = (! io_cpu_fetch_isStuck); + assign _zz_15 = _zz_21; + assign fetchStage_read_waysValues_1_tag_valid = _zz_28[0]; + assign fetchStage_read_waysValues_1_tag_error = _zz_29[0]; + assign fetchStage_read_waysValues_1_tag_address = _zz_15[21 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_hits_1 = (fetchStage_read_waysValues_1_tag_valid && (fetchStage_read_waysValues_1_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); + assign fetchStage_hit_valid = ({fetchStage_hit_hits_1,fetchStage_hit_hits_0} != 2'b00); + assign fetchStage_hit_wayId = fetchStage_hit_hits_1; + assign fetchStage_hit_error = _zz_22; + assign fetchStage_hit_data = _zz_23; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wayToAllocate_value <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_25)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + lineLoader_wayToAllocate_value <= lineLoader_wayToAllocate_valueNext; + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_24)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_5 <= lineLoader_flushCounter[7]; + if(_zz_25)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + if((_zz_16 != 3'b000))begin + io_cpu_fetch_data_regNextWhen <= _zz_17; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.yaml new file mode 100644 index 0000000..c869dbe --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.yaml @@ -0,0 +1,5 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 8192} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v index 7cb4c40..3333139 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 +// Git hash : e1ac7eb3083970f73e62f222f2f3e8520116f2e8 `define Input2Kind_defaultEncoding_type [0:0] @@ -80,25 +80,44 @@ module VexRiscv ( output [29:0] dBusWishbone_ADR, input [31:0] dBusWishbone_DAT_MISO, output [31:0] dBusWishbone_DAT_MOSI, - output reg [3:0] dBusWishbone_SEL, + output [3:0] dBusWishbone_SEL, input dBusWishbone_ERR, output [2:0] dBusWishbone_CTI, output [1:0] dBusWishbone_BTE, input clk, input reset ); + wire _zz_193; + wire _zz_194; + wire _zz_195; + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + reg _zz_201; + wire _zz_202; + wire [31:0] _zz_203; + wire _zz_204; + wire [31:0] _zz_205; + reg _zz_206; + wire _zz_207; + wire _zz_208; + wire [31:0] _zz_209; + wire _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; wire _zz_214; wire _zz_215; wire _zz_216; wire _zz_217; - wire _zz_218; + wire [3:0] _zz_218; wire _zz_219; wire _zz_220; - wire _zz_221; - reg _zz_222; + reg [31:0] _zz_221; + reg [31:0] _zz_222; reg [31:0] _zz_223; - reg [31:0] _zz_224; - reg [31:0] _zz_225; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -111,6 +130,28 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_224; + wire _zz_225; wire _zz_226; wire _zz_227; wire _zz_228; @@ -124,10 +165,10 @@ module VexRiscv ( wire _zz_236; wire _zz_237; wire _zz_238; - wire _zz_239; + wire [1:0] _zz_239; wire _zz_240; wire _zz_241; - wire [1:0] _zz_242; + wire _zz_242; wire _zz_243; wire _zz_244; wire _zz_245; @@ -135,35 +176,35 @@ module VexRiscv ( wire _zz_247; wire _zz_248; wire _zz_249; - wire _zz_250; + wire [1:0] _zz_250; wire _zz_251; wire _zz_252; wire _zz_253; - wire [1:0] _zz_254; + wire _zz_254; wire _zz_255; wire _zz_256; wire _zz_257; wire _zz_258; wire _zz_259; - wire _zz_260; + wire [1:0] _zz_260; wire _zz_261; - wire _zz_262; - wire _zz_263; - wire [1:0] _zz_264; - wire _zz_265; - wire [1:0] _zz_266; + wire [1:0] _zz_262; + wire [51:0] _zz_263; + wire [51:0] _zz_264; + wire [51:0] _zz_265; + wire [32:0] _zz_266; wire [51:0] _zz_267; - wire [51:0] _zz_268; + wire [49:0] _zz_268; wire [51:0] _zz_269; - wire [32:0] _zz_270; + wire [49:0] _zz_270; wire [51:0] _zz_271; - wire [49:0] _zz_272; - wire [51:0] _zz_273; - wire [49:0] _zz_274; - wire [51:0] _zz_275; - wire [32:0] _zz_276; - wire [31:0] _zz_277; - wire [32:0] _zz_278; + wire [32:0] _zz_272; + wire [31:0] _zz_273; + wire [32:0] _zz_274; + wire [0:0] _zz_275; + wire [0:0] _zz_276; + wire [0:0] _zz_277; + wire [0:0] _zz_278; wire [0:0] _zz_279; wire [0:0] _zz_280; wire [0:0] _zz_281; @@ -178,275 +219,271 @@ module VexRiscv ( wire [0:0] _zz_290; wire [0:0] _zz_291; wire [0:0] _zz_292; - wire [0:0] _zz_293; - wire [0:0] _zz_294; - wire [0:0] _zz_295; - wire [3:0] _zz_296; - wire [2:0] _zz_297; - wire [31:0] _zz_298; + wire [3:0] _zz_293; + wire [2:0] _zz_294; + wire [31:0] _zz_295; + wire [11:0] _zz_296; + wire [31:0] _zz_297; + wire [19:0] _zz_298; wire [11:0] _zz_299; wire [31:0] _zz_300; - wire [19:0] _zz_301; - wire [11:0] _zz_302; - wire [31:0] _zz_303; - wire [31:0] _zz_304; - wire [19:0] _zz_305; - wire [11:0] _zz_306; + wire [31:0] _zz_301; + wire [19:0] _zz_302; + wire [11:0] _zz_303; + wire [2:0] _zz_304; + wire [2:0] _zz_305; + wire [0:0] _zz_306; wire [2:0] _zz_307; - wire [0:0] _zz_308; - wire [2:0] _zz_309; - wire [4:0] _zz_310; - wire [11:0] _zz_311; - wire [11:0] _zz_312; + wire [4:0] _zz_308; + wire [11:0] _zz_309; + wire [11:0] _zz_310; + wire [31:0] _zz_311; + wire [31:0] _zz_312; wire [31:0] _zz_313; wire [31:0] _zz_314; wire [31:0] _zz_315; wire [31:0] _zz_316; wire [31:0] _zz_317; - wire [31:0] _zz_318; - wire [31:0] _zz_319; + wire [11:0] _zz_318; + wire [19:0] _zz_319; wire [11:0] _zz_320; - wire [19:0] _zz_321; - wire [11:0] _zz_322; + wire [31:0] _zz_321; + wire [31:0] _zz_322; wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; + wire [11:0] _zz_324; + wire [19:0] _zz_325; wire [11:0] _zz_326; - wire [19:0] _zz_327; - wire [11:0] _zz_328; - wire [2:0] _zz_329; + wire [2:0] _zz_327; + wire [1:0] _zz_328; + wire [1:0] _zz_329; wire [1:0] _zz_330; wire [1:0] _zz_331; - wire [1:0] _zz_332; - wire [1:0] _zz_333; - wire [1:0] _zz_334; - wire [1:0] _zz_335; - wire [9:0] _zz_336; - wire [7:0] _zz_337; - wire [65:0] _zz_338; - wire [65:0] _zz_339; - wire [31:0] _zz_340; + wire [9:0] _zz_332; + wire [7:0] _zz_333; + wire [65:0] _zz_334; + wire [65:0] _zz_335; + wire [31:0] _zz_336; + wire [31:0] _zz_337; + wire [0:0] _zz_338; + wire [5:0] _zz_339; + wire [32:0] _zz_340; wire [31:0] _zz_341; - wire [0:0] _zz_342; - wire [5:0] _zz_343; + wire [31:0] _zz_342; + wire [32:0] _zz_343; wire [32:0] _zz_344; - wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [32:0] _zz_347; + wire [32:0] _zz_345; + wire [32:0] _zz_346; + wire [0:0] _zz_347; wire [32:0] _zz_348; - wire [32:0] _zz_349; + wire [0:0] _zz_349; wire [32:0] _zz_350; wire [0:0] _zz_351; - wire [32:0] _zz_352; + wire [31:0] _zz_352; wire [0:0] _zz_353; - wire [32:0] _zz_354; + wire [0:0] _zz_354; wire [0:0] _zz_355; - wire [31:0] _zz_356; + wire [0:0] _zz_356; wire [0:0] _zz_357; wire [0:0] _zz_358; wire [0:0] _zz_359; - wire [0:0] _zz_360; - wire [0:0] _zz_361; - wire [0:0] _zz_362; - wire [0:0] _zz_363; - wire [26:0] _zz_364; - wire _zz_365; - wire _zz_366; - wire [1:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; + wire [26:0] _zz_360; + wire _zz_361; + wire _zz_362; + wire [1:0] _zz_363; + wire [31:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire _zz_367; + wire [0:0] _zz_368; + wire [14:0] _zz_369; wire [31:0] _zz_370; - wire _zz_371; - wire [0:0] _zz_372; - wire [13:0] _zz_373; - wire [31:0] _zz_374; - wire [31:0] _zz_375; + wire [31:0] _zz_371; + wire [31:0] _zz_372; + wire _zz_373; + wire [0:0] _zz_374; + wire [8:0] _zz_375; wire [31:0] _zz_376; - wire _zz_377; - wire [0:0] _zz_378; - wire [7:0] _zz_379; - wire [31:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; + wire [31:0] _zz_377; + wire [31:0] _zz_378; + wire _zz_379; + wire [0:0] _zz_380; + wire [2:0] _zz_381; + wire _zz_382; wire _zz_383; - wire [0:0] _zz_384; - wire [1:0] _zz_385; - wire _zz_386; + wire _zz_384; + wire [31:0] _zz_385; + wire [31:0] _zz_386; wire _zz_387; wire _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire _zz_391; - wire _zz_392; - wire [0:0] _zz_393; - wire [25:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [0:0] _zz_398; + wire [0:0] _zz_389; + wire [26:0] _zz_390; + wire [31:0] _zz_391; + wire [31:0] _zz_392; + wire [31:0] _zz_393; + wire [0:0] _zz_394; + wire [0:0] _zz_395; + wire [1:0] _zz_396; + wire [1:0] _zz_397; + wire _zz_398; wire [0:0] _zz_399; - wire [1:0] _zz_400; - wire [1:0] _zz_401; - wire _zz_402; - wire [0:0] _zz_403; - wire [20:0] _zz_404; + wire [21:0] _zz_400; + wire [31:0] _zz_401; + wire [31:0] _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; wire [31:0] _zz_405; wire [31:0] _zz_406; - wire [31:0] _zz_407; - wire [31:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire [0:0] _zz_411; + wire [0:0] _zz_407; + wire [0:0] _zz_408; + wire [2:0] _zz_409; + wire [2:0] _zz_410; + wire _zz_411; wire [0:0] _zz_412; - wire [2:0] _zz_413; - wire [2:0] _zz_414; - wire _zz_415; - wire [0:0] _zz_416; - wire [17:0] _zz_417; - wire [31:0] _zz_418; - wire [31:0] _zz_419; + wire [18:0] _zz_413; + wire [31:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire _zz_418; + wire _zz_419; wire [31:0] _zz_420; wire [31:0] _zz_421; wire _zz_422; - wire _zz_423; - wire [31:0] _zz_424; - wire [31:0] _zz_425; - wire _zz_426; - wire [0:0] _zz_427; - wire [0:0] _zz_428; + wire [0:0] _zz_423; + wire [0:0] _zz_424; + wire _zz_425; + wire [0:0] _zz_426; + wire [15:0] _zz_427; + wire [31:0] _zz_428; wire _zz_429; - wire [0:0] _zz_430; - wire [14:0] _zz_431; - wire [31:0] _zz_432; - wire _zz_433; + wire _zz_430; + wire _zz_431; + wire [2:0] _zz_432; + wire [2:0] _zz_433; wire _zz_434; wire [0:0] _zz_435; - wire [1:0] _zz_436; - wire [4:0] _zz_437; - wire [4:0] _zz_438; + wire [12:0] _zz_436; + wire _zz_437; + wire _zz_438; wire _zz_439; wire [0:0] _zz_440; - wire [11:0] _zz_441; - wire [31:0] _zz_442; - wire [31:0] _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire [31:0] _zz_446; - wire [31:0] _zz_447; - wire _zz_448; - wire [0:0] _zz_449; - wire [1:0] _zz_450; + wire [2:0] _zz_441; + wire _zz_442; + wire [5:0] _zz_443; + wire [5:0] _zz_444; + wire _zz_445; + wire [0:0] _zz_446; + wire [9:0] _zz_447; + wire [31:0] _zz_448; + wire [31:0] _zz_449; + wire [31:0] _zz_450; wire [31:0] _zz_451; wire [31:0] _zz_452; - wire [0:0] _zz_453; - wire [4:0] _zz_454; - wire [4:0] _zz_455; - wire [4:0] _zz_456; + wire _zz_453; + wire [0:0] _zz_454; + wire [0:0] _zz_455; + wire [31:0] _zz_456; wire _zz_457; wire [0:0] _zz_458; - wire [8:0] _zz_459; - wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire [31:0] _zz_462; - wire _zz_463; + wire [3:0] _zz_459; + wire [0:0] _zz_460; + wire [3:0] _zz_461; + wire [5:0] _zz_462; + wire [5:0] _zz_463; wire _zz_464; - wire [31:0] _zz_465; - wire [31:0] _zz_466; - wire _zz_467; - wire [0:0] _zz_468; - wire [2:0] _zz_469; - wire [0:0] _zz_470; - wire [2:0] _zz_471; - wire [0:0] _zz_472; - wire [4:0] _zz_473; - wire [1:0] _zz_474; - wire [1:0] _zz_475; - wire _zz_476; - wire [0:0] _zz_477; - wire [6:0] _zz_478; - wire [31:0] _zz_479; - wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire _zz_482; + wire [0:0] _zz_465; + wire [7:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; + wire [31:0] _zz_474; + wire [0:0] _zz_475; + wire [1:0] _zz_476; + wire _zz_477; + wire [0:0] _zz_478; + wire [1:0] _zz_479; + wire [0:0] _zz_480; + wire [3:0] _zz_481; + wire [0:0] _zz_482; wire [0:0] _zz_483; - wire [0:0] _zz_484; - wire [31:0] _zz_485; - wire [31:0] _zz_486; - wire _zz_487; - wire [0:0] _zz_488; - wire [0:0] _zz_489; - wire _zz_490; - wire [0:0] _zz_491; - wire [2:0] _zz_492; - wire _zz_493; - wire [0:0] _zz_494; - wire [0:0] _zz_495; - wire [0:0] _zz_496; - wire [0:0] _zz_497; - wire _zz_498; - wire [0:0] _zz_499; - wire [4:0] _zz_500; - wire [31:0] _zz_501; - wire [31:0] _zz_502; + wire [1:0] _zz_484; + wire [1:0] _zz_485; + wire _zz_486; + wire [0:0] _zz_487; + wire [5:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; + wire _zz_491; + wire _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire _zz_496; + wire _zz_497; + wire [31:0] _zz_498; + wire [31:0] _zz_499; + wire _zz_500; + wire [0:0] _zz_501; + wire [1:0] _zz_502; wire [31:0] _zz_503; wire [31:0] _zz_504; - wire [31:0] _zz_505; - wire [31:0] _zz_506; - wire [31:0] _zz_507; - wire [31:0] _zz_508; - wire [31:0] _zz_509; - wire [31:0] _zz_510; - wire [31:0] _zz_511; + wire _zz_505; + wire _zz_506; + wire [0:0] _zz_507; + wire [0:0] _zz_508; + wire _zz_509; + wire [0:0] _zz_510; + wire [3:0] _zz_511; wire [31:0] _zz_512; wire [31:0] _zz_513; - wire _zz_514; - wire [0:0] _zz_515; - wire [0:0] _zz_516; + wire [31:0] _zz_514; + wire [31:0] _zz_515; + wire [31:0] _zz_516; wire [31:0] _zz_517; wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire [31:0] _zz_520; + wire _zz_519; + wire _zz_520; wire [31:0] _zz_521; - wire _zz_522; - wire [3:0] _zz_523; - wire [3:0] _zz_524; - wire _zz_525; - wire [0:0] _zz_526; - wire [2:0] _zz_527; - wire [31:0] _zz_528; - wire [31:0] _zz_529; - wire [31:0] _zz_530; - wire [31:0] _zz_531; + wire [31:0] _zz_522; + wire [31:0] _zz_523; + wire [31:0] _zz_524; + wire [0:0] _zz_525; + wire [2:0] _zz_526; + wire [0:0] _zz_527; + wire [0:0] _zz_528; + wire _zz_529; + wire [0:0] _zz_530; + wire [1:0] _zz_531; wire [31:0] _zz_532; wire [31:0] _zz_533; - wire _zz_534; - wire [0:0] _zz_535; - wire [1:0] _zz_536; - wire _zz_537; - wire [2:0] _zz_538; - wire [2:0] _zz_539; - wire _zz_540; + wire [31:0] _zz_534; + wire _zz_535; + wire _zz_536; + wire [31:0] _zz_537; + wire _zz_538; + wire [0:0] _zz_539; + wire [0:0] _zz_540; wire [0:0] _zz_541; wire [0:0] _zz_542; - wire [31:0] _zz_543; - wire [31:0] _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; + wire [1:0] _zz_543; + wire [1:0] _zz_544; + wire [0:0] _zz_545; + wire [0:0] _zz_546; wire [31:0] _zz_547; wire [31:0] _zz_548; wire [31:0] _zz_549; - wire _zz_550; - wire _zz_551; - wire _zz_552; - wire [0:0] _zz_553; - wire [0:0] _zz_554; + wire [31:0] _zz_550; + wire [31:0] _zz_551; + wire [31:0] _zz_552; + wire _zz_553; + wire _zz_554; wire _zz_555; - wire _zz_556; - wire _zz_557; - wire _zz_558; - wire [31:0] _zz_559; + wire [31:0] _zz_556; wire [51:0] memory_MUL_LOW; - wire [31:0] memory_MEMORY_READ_DATA; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; @@ -455,7 +492,6 @@ module VexRiscv ( wire writeBack_CfuPlugin_CFU_IN_FLIGHT; wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; - wire [31:0] writeBack_REGFILE_WRITE_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; wire [1:0] memory_MEMORY_ADDRESS_LOW; wire [1:0] execute_MEMORY_ADDRESS_LOW; @@ -496,7 +532,9 @@ module VexRiscv ( wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; wire decode_SRC_LESS_UNSIGNED; - wire decode_MEMORY_STORE; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; @@ -512,10 +550,12 @@ module VexRiscv ( wire `Src1CtrlEnum_defaultEncoding_type _zz_27; wire `Src1CtrlEnum_defaultEncoding_type _zz_28; wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; wire execute_IS_RS1_SIGNED; wire execute_IS_DIV; wire execute_IS_RS2_SIGNED; @@ -598,42 +638,20 @@ module VexRiscv ( wire `Src2CtrlEnum_defaultEncoding_type _zz_54; wire `AluCtrlEnum_defaultEncoding_type _zz_55; wire `Src1CtrlEnum_defaultEncoding_type _zz_56; - wire writeBack_MEMORY_STORE; reg [31:0] _zz_57; - wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP2_physicalAddress; - wire memory_MMU_RSP2_isIoAccess; - wire memory_MMU_RSP2_isPaging; - wire memory_MMU_RSP2_allowRead; - wire memory_MMU_RSP2_allowWrite; - wire memory_MMU_RSP2_allowExecute; - wire memory_MMU_RSP2_exception; - wire memory_MMU_RSP2_refilling; - wire memory_MMU_RSP2_bypassTranslation; - wire [31:0] memory_PC; - wire memory_ALIGNEMENT_FAULT; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP2_physicalAddress; - wire execute_MMU_RSP2_isIoAccess; - wire execute_MMU_RSP2_isPaging; - wire execute_MMU_RSP2_allowRead; - wire execute_MMU_RSP2_allowWrite; - wire execute_MMU_RSP2_allowExecute; - wire execute_MMU_RSP2_exception; - wire execute_MMU_RSP2_refilling; - wire execute_MMU_RSP2_bypassTranslation; - wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; - wire [31:0] execute_INSTRUCTION; - wire execute_MEMORY_STORE; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; wire execute_MEMORY_ENABLE; - wire execute_ALIGNEMENT_FAULT; + wire [31:0] execute_INSTRUCTION; wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_4; @@ -645,7 +663,6 @@ module VexRiscv ( wire [31:0] decode_INSTRUCTION; reg [31:0] _zz_59; reg [31:0] _zz_60; - reg [31:0] _zz_61; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -661,7 +678,7 @@ module VexRiscv ( wire decode_arbitration_isMoving; wire decode_arbitration_isFiring; reg execute_arbitration_haltItself; - wire execute_arbitration_haltByOther; + reg execute_arbitration_haltByOther; reg execute_arbitration_removeIt; wire execute_arbitration_flushIt; reg execute_arbitration_flushNext; @@ -674,7 +691,7 @@ module VexRiscv ( reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; + wire memory_arbitration_flushIt; reg memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; @@ -682,10 +699,10 @@ module VexRiscv ( wire memory_arbitration_isFlushed; wire memory_arbitration_isMoving; wire memory_arbitration_isFiring; - wire writeBack_arbitration_haltItself; + reg writeBack_arbitration_haltItself; wire writeBack_arbitration_haltByOther; reg writeBack_arbitration_removeIt; - wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushIt; reg writeBack_arbitration_flushNext; reg writeBack_arbitration_isValid; wire writeBack_arbitration_isStuck; @@ -725,26 +742,39 @@ module VexRiscv ( wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; wire IBusCachedPlugin_mmuBus_end; wire IBusCachedPlugin_mmuBus_busy; - reg DBusSimplePlugin_memoryExceptionPort_valid; - reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; - wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_0_isValid; - wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_isPaging; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -776,11 +806,11 @@ module VexRiscv ( wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_61; wire [3:0] _zz_62; - wire [3:0] _zz_63; + wire _zz_63; wire _zz_64; wire _zz_65; - wire _zz_66; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; @@ -817,16 +847,16 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_66; wire _zz_67; wire _zz_68; - wire _zz_69; wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_69; wire _zz_70; - wire _zz_71; - reg _zz_72; - wire _zz_73; - reg _zz_74; - reg [31:0] _zz_75; + reg _zz_71; + wire _zz_72; + reg _zz_73; + reg [31:0] _zz_74; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -839,17 +869,17 @@ module VexRiscv ( reg IBusCachedPlugin_injector_nextPcCalc_valids_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_76; - reg [18:0] _zz_77; - wire _zz_78; - reg [10:0] _zz_79; - wire _zz_80; - reg [18:0] _zz_81; - reg _zz_82; - wire _zz_83; - reg [10:0] _zz_84; - wire _zz_85; - reg [18:0] _zz_86; + wire _zz_75; + reg [18:0] _zz_76; + wire _zz_77; + reg [10:0] _zz_78; + wire _zz_79; + reg [18:0] _zz_80; + reg _zz_81; + wire _zz_82; + reg [10:0] _zz_83; + wire _zz_84; + reg [18:0] _zz_85; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -857,7 +887,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_87; + wire [31:0] _zz_86; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -865,40 +895,64 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [1:0] dBus_cmd_payload_size; - wire dBus_rsp_ready; - wire dBus_rsp_error; - wire [31:0] dBus_rsp_data; - wire _zz_88; - reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_89; - reg [3:0] _zz_90; - wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] writeBack_DBusSimplePlugin_rspShifted; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_87; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_88; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_89; + reg [31:0] _zz_90; wire _zz_91; reg [31:0] _zz_92; - wire _zz_93; - reg [31:0] _zz_94; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [32:0] _zz_95; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [33:0] _zz_93; + wire _zz_94; + wire _zz_95; wire _zz_96; wire _zz_97; wire _zz_98; - wire _zz_99; - wire _zz_100; - wire `Src1CtrlEnum_defaultEncoding_type _zz_101; - wire `AluCtrlEnum_defaultEncoding_type _zz_102; - wire `Src2CtrlEnum_defaultEncoding_type _zz_103; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_104; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_105; - wire `BranchCtrlEnum_defaultEncoding_type _zz_106; - wire `EnvCtrlEnum_defaultEncoding_type _zz_107; - wire `Input2Kind_defaultEncoding_type _zz_108; + wire `Src1CtrlEnum_defaultEncoding_type _zz_99; + wire `AluCtrlEnum_defaultEncoding_type _zz_100; + wire `Src2CtrlEnum_defaultEncoding_type _zz_101; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_102; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_103; + wire `BranchCtrlEnum_defaultEncoding_type _zz_104; + wire `EnvCtrlEnum_defaultEncoding_type _zz_105; + wire `Input2Kind_defaultEncoding_type _zz_106; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -906,52 +960,52 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_109; + reg _zz_107; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_110; - reg [31:0] _zz_111; + reg [31:0] _zz_108; + reg [31:0] _zz_109; + wire _zz_110; + reg [19:0] _zz_111; wire _zz_112; reg [19:0] _zz_113; - wire _zz_114; - reg [19:0] _zz_115; - reg [31:0] _zz_116; + reg [31:0] _zz_114; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_117; + reg [31:0] _zz_115; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_118; + reg [31:0] _zz_116; + reg _zz_117; + reg _zz_118; reg _zz_119; - reg _zz_120; - reg _zz_121; - reg [4:0] _zz_122; - reg [31:0] _zz_123; + reg [4:0] _zz_120; + reg [31:0] _zz_121; + wire _zz_122; + wire _zz_123; wire _zz_124; wire _zz_125; wire _zz_126; wire _zz_127; - wire _zz_128; - wire _zz_129; wire execute_BranchPlugin_eq; - wire [2:0] _zz_130; - reg _zz_131; - reg _zz_132; + wire [2:0] _zz_128; + reg _zz_129; + reg _zz_130; + wire _zz_131; + reg [19:0] _zz_132; wire _zz_133; - reg [19:0] _zz_134; + reg [10:0] _zz_134; wire _zz_135; - reg [10:0] _zz_136; - wire _zz_137; - reg [18:0] _zz_138; - reg _zz_139; + reg [18:0] _zz_136; + reg _zz_137; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_138; + reg [19:0] _zz_139; wire _zz_140; - reg [19:0] _zz_141; + reg [10:0] _zz_141; wire _zz_142; - reg [10:0] _zz_143; - wire _zz_144; - reg [18:0] _zz_145; + reg [18:0] _zz_143; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -973,9 +1027,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_144; + wire _zz_145; wire _zz_146; - wire _zz_147; - wire _zz_148; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -988,12 +1042,10 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_147; + wire _zz_148; wire [1:0] _zz_149; wire _zz_150; - wire [1:0] _zz_151; - wire _zz_152; - wire [1:0] _zz_153; - wire _zz_154; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1022,29 +1074,13 @@ module VexRiscv ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_171; - reg [23:0] _zz_172; - reg [31:0] _zz_173; + wire _zz_151; + reg [23:0] _zz_152; + reg [31:0] _zz_153; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1076,18 +1112,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_174; + wire [31:0] _zz_154; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_175; - wire _zz_176; - wire _zz_177; - reg [32:0] _zz_178; + wire [31:0] _zz_155; + wire _zz_156; + wire _zz_157; + reg [32:0] _zz_158; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_179; - wire [31:0] _zz_180; + reg [31:0] _zz_159; + wire [31:0] _zz_160; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1097,6 +1133,7 @@ module VexRiscv ( reg [31:0] decode_to_execute_FORMAL_PC_NEXT; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; reg decode_to_execute_SRC_USE_SUB_LESS; reg decode_to_execute_MEMORY_ENABLE; @@ -1110,9 +1147,10 @@ module VexRiscv ( reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg decode_to_execute_MEMORY_STORE; - reg execute_to_memory_MEMORY_STORE; - reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; reg decode_to_execute_SRC_LESS_UNSIGNED; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; @@ -1137,19 +1175,8 @@ module VexRiscv ( reg decode_to_execute_PREDICTION_HAD_BRANCHED2; reg decode_to_execute_CSR_WRITE_OPCODE; reg decode_to_execute_CSR_READ_OPCODE; - reg execute_to_memory_ALIGNEMENT_FAULT; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_MMU_FAULT; - reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; - reg execute_to_memory_MMU_RSP2_isIoAccess; - reg execute_to_memory_MMU_RSP2_isPaging; - reg execute_to_memory_MMU_RSP2_allowRead; - reg execute_to_memory_MMU_RSP2_allowWrite; - reg execute_to_memory_MMU_RSP2_allowExecute; - reg execute_to_memory_MMU_RSP2_exception; - reg execute_to_memory_MMU_RSP2_refilling; - reg execute_to_memory_MMU_RSP2_bypassTranslation; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; reg [31:0] execute_to_memory_SHIFT_RIGHT; @@ -1160,8 +1187,8 @@ module VexRiscv ( reg [33:0] execute_to_memory_MUL_HL; reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; - reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; reg [51:0] memory_to_writeBack_MUL_LOW; + reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; reg execute_CsrPlugin_csr_3859; @@ -1183,70 +1210,42 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3200; reg execute_CsrPlugin_csr_3074; reg execute_CsrPlugin_csr_3202; - reg execute_CsrPlugin_csr_2820; - reg execute_CsrPlugin_csr_2821; - reg execute_CsrPlugin_csr_2822; - reg execute_CsrPlugin_csr_2823; - reg execute_CsrPlugin_csr_2824; - reg execute_CsrPlugin_csr_2825; - reg execute_CsrPlugin_csr_2826; - reg execute_CsrPlugin_csr_2827; - reg execute_CsrPlugin_csr_2828; - reg execute_CsrPlugin_csr_2829; - reg execute_CsrPlugin_csr_2830; - reg execute_CsrPlugin_csr_2831; - reg execute_CsrPlugin_csr_2832; - reg execute_CsrPlugin_csr_2833; - reg execute_CsrPlugin_csr_2834; - reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; reg [31:0] _zz_181; reg [31:0] _zz_182; reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [31:0] _zz_199; - reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; - reg [31:0] _zz_208; - reg [31:0] _zz_209; - reg [31:0] _zz_210; - reg [2:0] _zz_211; - reg _zz_212; + reg [2:0] _zz_184; + reg _zz_185; reg [31:0] iBusWishbone_DAT_MISO_regNext; - wire dBus_cmd_halfPipe_valid; - wire dBus_cmd_halfPipe_ready; - wire dBus_cmd_halfPipe_payload_wr; - wire [31:0] dBus_cmd_halfPipe_payload_address; - wire [31:0] dBus_cmd_halfPipe_payload_data; - wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_213; + reg [2:0] _zz_186; + wire _zz_187; + wire _zz_188; + wire _zz_189; + wire _zz_190; + wire _zz_191; + reg _zz_192; + reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] _zz_1_string; @@ -1316,14 +1315,14 @@ module VexRiscv ( reg [95:0] _zz_56_string; reg [31:0] decode_BRANCH_CTRL_string; reg [31:0] _zz_58_string; - reg [95:0] _zz_101_string; - reg [63:0] _zz_102_string; - reg [23:0] _zz_103_string; - reg [39:0] _zz_104_string; - reg [71:0] _zz_105_string; - reg [31:0] _zz_106_string; - reg [39:0] _zz_107_string; - reg [39:0] _zz_108_string; + reg [95:0] _zz_99_string; + reg [63:0] _zz_100_string; + reg [23:0] _zz_101_string; + reg [39:0] _zz_102_string; + reg [71:0] _zz_103_string; + reg [31:0] _zz_104_string; + reg [39:0] _zz_105_string; + reg [39:0] _zz_106_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1339,349 +1338,348 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_226 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_227 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_228 = 1'b1; - assign _zz_229 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_230 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_231 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_232 = ((_zz_219 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_233 = ((_zz_219 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_234 = ((_zz_219 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_235 = ((_zz_219 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_236 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_237 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_238 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_239 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_240 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_241 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_242 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_243 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_244 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_245 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_246 = (1'b0 || (! 1'b1)); - assign _zz_247 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_248 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_249 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_250 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_251 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_252 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_253 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_254 = execute_INSTRUCTION[13 : 12]; - assign _zz_255 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_256 = (! memory_arbitration_isStuck); - assign _zz_257 = (iBus_cmd_valid || (_zz_211 != 3'b000)); - assign _zz_258 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_259 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_260 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_261 = ((_zz_148 && 1'b1) && (! 1'b0)); - assign _zz_262 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_263 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_264 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_265 = execute_INSTRUCTION[13]; - assign _zz_266 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_267 = ($signed(_zz_268) + $signed(_zz_273)); - assign _zz_268 = ($signed(_zz_269) + $signed(_zz_271)); - assign _zz_269 = 52'h0; - assign _zz_270 = {1'b0,memory_MUL_LL}; - assign _zz_271 = {{19{_zz_270[32]}}, _zz_270}; - assign _zz_272 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_273 = {{2{_zz_272[49]}}, _zz_272}; - assign _zz_274 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_275 = {{2{_zz_274[49]}}, _zz_274}; - assign _zz_276 = ($signed(_zz_278) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_277 = _zz_276[31 : 0]; - assign _zz_278 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_279 = _zz_95[32 : 32]; - assign _zz_280 = _zz_95[31 : 31]; - assign _zz_281 = _zz_95[30 : 30]; - assign _zz_282 = _zz_95[29 : 29]; - assign _zz_283 = _zz_95[27 : 27]; - assign _zz_284 = _zz_95[24 : 24]; - assign _zz_285 = _zz_95[16 : 16]; - assign _zz_286 = _zz_95[13 : 13]; - assign _zz_287 = _zz_95[12 : 12]; - assign _zz_288 = _zz_95[11 : 11]; - assign _zz_289 = _zz_95[15 : 15]; - assign _zz_290 = _zz_95[5 : 5]; - assign _zz_291 = _zz_95[3 : 3]; - assign _zz_292 = _zz_95[19 : 19]; - assign _zz_293 = _zz_95[10 : 10]; - assign _zz_294 = _zz_95[4 : 4]; - assign _zz_295 = _zz_95[0 : 0]; - assign _zz_296 = (_zz_62 - 4'b0001); - assign _zz_297 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_298 = {29'd0, _zz_297}; + assign _zz_224 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_225 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_226 = 1'b1; + assign _zz_227 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_228 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_229 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_230 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_231 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_232 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_233 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_234 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_235 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_236 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_237 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_238 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_239 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_240 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_241 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_242 = (1'b0 || (! 1'b1)); + assign _zz_243 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_244 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_245 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_246 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_247 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_248 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_249 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_250 = execute_INSTRUCTION[13 : 12]; + assign _zz_251 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_252 = (! memory_arbitration_isStuck); + assign _zz_253 = (iBus_cmd_valid || (_zz_184 != 3'b000)); + assign _zz_254 = (_zz_220 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_255 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_256 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_257 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_258 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_259 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_260 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_261 = execute_INSTRUCTION[13]; + assign _zz_262 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_263 = ($signed(_zz_264) + $signed(_zz_269)); + assign _zz_264 = ($signed(_zz_265) + $signed(_zz_267)); + assign _zz_265 = 52'h0; + assign _zz_266 = {1'b0,memory_MUL_LL}; + assign _zz_267 = {{19{_zz_266[32]}}, _zz_266}; + assign _zz_268 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_269 = {{2{_zz_268[49]}}, _zz_268}; + assign _zz_270 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_271 = {{2{_zz_270[49]}}, _zz_270}; + assign _zz_272 = ($signed(_zz_274) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_273 = _zz_272[31 : 0]; + assign _zz_274 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_275 = _zz_93[33 : 33]; + assign _zz_276 = _zz_93[32 : 32]; + assign _zz_277 = _zz_93[31 : 31]; + assign _zz_278 = _zz_93[30 : 30]; + assign _zz_279 = _zz_93[28 : 28]; + assign _zz_280 = _zz_93[25 : 25]; + assign _zz_281 = _zz_93[17 : 17]; + assign _zz_282 = _zz_93[16 : 16]; + assign _zz_283 = _zz_93[13 : 13]; + assign _zz_284 = _zz_93[12 : 12]; + assign _zz_285 = _zz_93[11 : 11]; + assign _zz_286 = _zz_93[15 : 15]; + assign _zz_287 = _zz_93[5 : 5]; + assign _zz_288 = _zz_93[3 : 3]; + assign _zz_289 = _zz_93[20 : 20]; + assign _zz_290 = _zz_93[10 : 10]; + assign _zz_291 = _zz_93[4 : 4]; + assign _zz_292 = _zz_93[0 : 0]; + assign _zz_293 = (_zz_61 - 4'b0001); + assign _zz_294 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_295 = {29'd0, _zz_294}; + assign _zz_296 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_297 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_298 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; assign _zz_299 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_300 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_301 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_302 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_303 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_304 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_305 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_306 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_307 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_308 = execute_SRC_LESS; - assign _zz_309 = 3'b100; - assign _zz_310 = execute_INSTRUCTION[19 : 15]; - assign _zz_311 = execute_INSTRUCTION[31 : 20]; - assign _zz_312 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_313 = ($signed(_zz_314) + $signed(_zz_317)); - assign _zz_314 = ($signed(_zz_315) + $signed(_zz_316)); - assign _zz_315 = execute_SRC1; - assign _zz_316 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_317 = (execute_SRC_USE_SUB_LESS ? _zz_318 : _zz_319); - assign _zz_318 = 32'h00000001; - assign _zz_319 = 32'h0; - assign _zz_320 = execute_INSTRUCTION[31 : 20]; - assign _zz_321 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_322 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_323 = {_zz_134,execute_INSTRUCTION[31 : 20]}; - assign _zz_324 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_325 = {{_zz_138,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_326 = execute_INSTRUCTION[31 : 20]; - assign _zz_327 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_329 = 3'b100; + assign _zz_300 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_301 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_302 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_303 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_304 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_305 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_306 = execute_SRC_LESS; + assign _zz_307 = 3'b100; + assign _zz_308 = execute_INSTRUCTION[19 : 15]; + assign _zz_309 = execute_INSTRUCTION[31 : 20]; + assign _zz_310 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_311 = ($signed(_zz_312) + $signed(_zz_315)); + assign _zz_312 = ($signed(_zz_313) + $signed(_zz_314)); + assign _zz_313 = execute_SRC1; + assign _zz_314 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_315 = (execute_SRC_USE_SUB_LESS ? _zz_316 : _zz_317); + assign _zz_316 = 32'h00000001; + assign _zz_317 = 32'h0; + assign _zz_318 = execute_INSTRUCTION[31 : 20]; + assign _zz_319 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_320 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_321 = {_zz_132,execute_INSTRUCTION[31 : 20]}; + assign _zz_322 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_323 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_324 = execute_INSTRUCTION[31 : 20]; + assign _zz_325 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_326 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_327 = 3'b100; + assign _zz_328 = (_zz_147 & (~ _zz_329)); + assign _zz_329 = (_zz_147 - 2'b01); assign _zz_330 = (_zz_149 & (~ _zz_331)); assign _zz_331 = (_zz_149 - 2'b01); - assign _zz_332 = (_zz_151 & (~ _zz_333)); - assign _zz_333 = (_zz_151 - 2'b01); - assign _zz_334 = (_zz_153 & (~ _zz_335)); - assign _zz_335 = (_zz_153 - 2'b01); - assign _zz_336 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_337 = execute_INSTRUCTION[31 : 24]; - assign _zz_338 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_339 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_340 = writeBack_MUL_LOW[31 : 0]; - assign _zz_341 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_342 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_343 = {5'd0, _zz_342}; - assign _zz_344 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_345 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_346 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_347 = {_zz_174,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_348 = _zz_349; - assign _zz_349 = _zz_350; - assign _zz_350 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_175) : _zz_175)} + _zz_352); - assign _zz_351 = memory_DivPlugin_div_needRevert; - assign _zz_352 = {32'd0, _zz_351}; - assign _zz_353 = _zz_177; - assign _zz_354 = {32'd0, _zz_353}; - assign _zz_355 = _zz_176; - assign _zz_356 = {31'd0, _zz_355}; + assign _zz_332 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_333 = execute_INSTRUCTION[31 : 24]; + assign _zz_334 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_335 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_336 = writeBack_MUL_LOW[31 : 0]; + assign _zz_337 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_338 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_339 = {5'd0, _zz_338}; + assign _zz_340 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_341 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_342 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_343 = {_zz_154,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_344 = _zz_345; + assign _zz_345 = _zz_346; + assign _zz_346 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_155) : _zz_155)} + _zz_348); + assign _zz_347 = memory_DivPlugin_div_needRevert; + assign _zz_348 = {32'd0, _zz_347}; + assign _zz_349 = _zz_157; + assign _zz_350 = {32'd0, _zz_349}; + assign _zz_351 = _zz_156; + assign _zz_352 = {31'd0, _zz_351}; + assign _zz_353 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_354 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_355 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_356 = execute_CsrPlugin_writeData[11 : 11]; assign _zz_357 = execute_CsrPlugin_writeData[7 : 7]; assign _zz_358 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_359 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_360 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_361 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_362 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_363 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_364 = (iBus_cmd_payload_address >>> 5); - assign _zz_365 = 1'b1; - assign _zz_366 = 1'b1; - assign _zz_367 = {_zz_66,_zz_65}; - assign _zz_368 = 32'h0000106f; - assign _zz_369 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_370 = 32'h00001073; - assign _zz_371 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_372 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_373 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_374) == 32'h00000003),{(_zz_375 == _zz_376),{_zz_377,{_zz_378,_zz_379}}}}}}; - assign _zz_374 = 32'h0000207f; - assign _zz_375 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_376 = 32'h00000003; - assign _zz_377 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_378 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_379 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_380) == 32'h00001013),{(_zz_381 == _zz_382),{_zz_383,{_zz_384,_zz_385}}}}}}; - assign _zz_380 = 32'hfc00307f; - assign _zz_381 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_382 = 32'h00005033; - assign _zz_383 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_384 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_385 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; - assign _zz_386 = decode_INSTRUCTION[31]; - assign _zz_387 = decode_INSTRUCTION[31]; - assign _zz_388 = decode_INSTRUCTION[7]; - assign _zz_389 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_390 = 32'h02004020; - assign _zz_391 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_392 = (_zz_99 != 1'b0); - assign _zz_393 = (((decode_INSTRUCTION & _zz_395) == 32'h00000050) != 1'b0); - assign _zz_394 = {((_zz_396 == _zz_397) != 1'b0),{({_zz_398,_zz_399} != 2'b00),{(_zz_400 != _zz_401),{_zz_402,{_zz_403,_zz_404}}}}}; - assign _zz_395 = 32'h00203050; - assign _zz_396 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_397 = 32'h00000050; - assign _zz_398 = ((decode_INSTRUCTION & _zz_405) == 32'h00001050); - assign _zz_399 = ((decode_INSTRUCTION & _zz_406) == 32'h00002050); - assign _zz_400 = {_zz_98,(_zz_407 == _zz_408)}; - assign _zz_401 = 2'b00; - assign _zz_402 = ((_zz_409 == _zz_410) != 1'b0); - assign _zz_403 = ({_zz_411,_zz_412} != 2'b00); - assign _zz_404 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; - assign _zz_405 = 32'h00001050; - assign _zz_406 = 32'h00002050; - assign _zz_407 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_408 = 32'h00000004; - assign _zz_409 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_410 = 32'h00000040; - assign _zz_411 = ((decode_INSTRUCTION & _zz_418) == 32'h00005010); - assign _zz_412 = ((decode_INSTRUCTION & _zz_419) == 32'h00005020); - assign _zz_413 = {(_zz_420 == _zz_421),{_zz_422,_zz_423}}; - assign _zz_414 = 3'b000; - assign _zz_415 = ((_zz_424 == _zz_425) != 1'b0); - assign _zz_416 = (_zz_426 != 1'b0); - assign _zz_417 = {(_zz_427 != _zz_428),{_zz_429,{_zz_430,_zz_431}}}; - assign _zz_418 = 32'h00007034; - assign _zz_419 = 32'h02007064; - assign _zz_420 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_421 = 32'h40001010; - assign _zz_422 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_423 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_424 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_425 = 32'h00000024; - assign _zz_426 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_427 = ((decode_INSTRUCTION & _zz_432) == 32'h00002000); - assign _zz_428 = 1'b0; - assign _zz_429 = ({_zz_433,_zz_434} != 2'b00); - assign _zz_430 = ({_zz_435,_zz_436} != 3'b000); - assign _zz_431 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; - assign _zz_432 = 32'h00003000; - assign _zz_433 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_434 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_435 = _zz_99; - assign _zz_436 = {(_zz_442 == _zz_443),(_zz_444 == _zz_445)}; - assign _zz_437 = {(_zz_446 == _zz_447),{_zz_448,{_zz_449,_zz_450}}}; - assign _zz_438 = 5'h0; - assign _zz_439 = ((_zz_451 == _zz_452) != 1'b0); - assign _zz_440 = ({_zz_453,_zz_454} != 6'h0); - assign _zz_441 = {(_zz_455 != _zz_456),{_zz_457,{_zz_458,_zz_459}}}; - assign _zz_442 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_443 = 32'h00000020; - assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_445 = 32'h00000020; - assign _zz_446 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_447 = 32'h00002040; - assign _zz_448 = ((decode_INSTRUCTION & _zz_460) == 32'h00001040); - assign _zz_449 = (_zz_461 == _zz_462); - assign _zz_450 = {_zz_463,_zz_464}; - assign _zz_451 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_452 = 32'h00000020; - assign _zz_453 = (_zz_465 == _zz_466); - assign _zz_454 = {_zz_467,{_zz_468,_zz_469}}; - assign _zz_455 = {_zz_97,{_zz_470,_zz_471}}; - assign _zz_456 = 5'h0; - assign _zz_457 = ({_zz_472,_zz_473} != 6'h0); - assign _zz_458 = (_zz_474 != _zz_475); - assign _zz_459 = {_zz_476,{_zz_477,_zz_478}}; - assign _zz_460 = 32'h00001040; - assign _zz_461 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_462 = 32'h00000040; - assign _zz_463 = ((decode_INSTRUCTION & _zz_479) == 32'h00000040); - assign _zz_464 = ((decode_INSTRUCTION & _zz_480) == 32'h0); - assign _zz_465 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_466 = 32'h00000008; - assign _zz_467 = ((decode_INSTRUCTION & _zz_481) == 32'h00000040); - assign _zz_468 = _zz_97; - assign _zz_469 = {_zz_482,{_zz_483,_zz_484}}; - assign _zz_470 = (_zz_485 == _zz_486); - assign _zz_471 = {_zz_487,{_zz_488,_zz_489}}; - assign _zz_472 = _zz_98; - assign _zz_473 = {_zz_490,{_zz_491,_zz_492}}; - assign _zz_474 = {_zz_97,_zz_493}; - assign _zz_475 = 2'b00; - assign _zz_476 = ({_zz_494,_zz_495} != 2'b00); - assign _zz_477 = (_zz_496 != _zz_497); - assign _zz_478 = {_zz_498,{_zz_499,_zz_500}}; - assign _zz_479 = 32'h00400040; - assign _zz_480 = 32'h00000038; - assign _zz_481 = 32'h00000040; - assign _zz_482 = ((decode_INSTRUCTION & _zz_501) == 32'h00004020); - assign _zz_483 = (_zz_502 == _zz_503); - assign _zz_484 = (_zz_504 == _zz_505); - assign _zz_485 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_486 = 32'h00002010; - assign _zz_487 = ((decode_INSTRUCTION & _zz_506) == 32'h00000010); - assign _zz_488 = (_zz_507 == _zz_508); - assign _zz_489 = (_zz_509 == _zz_510); - assign _zz_490 = ((decode_INSTRUCTION & _zz_511) == 32'h00001010); - assign _zz_491 = (_zz_512 == _zz_513); - assign _zz_492 = {_zz_514,{_zz_515,_zz_516}}; - assign _zz_493 = ((decode_INSTRUCTION & _zz_517) == 32'h00000020); - assign _zz_494 = _zz_97; - assign _zz_495 = (_zz_518 == _zz_519); - assign _zz_496 = (_zz_520 == _zz_521); - assign _zz_497 = 1'b0; - assign _zz_498 = (_zz_522 != 1'b0); - assign _zz_499 = (_zz_523 != _zz_524); - assign _zz_500 = {_zz_525,{_zz_526,_zz_527}}; - assign _zz_501 = 32'h00004020; - assign _zz_502 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_503 = 32'h00000010; - assign _zz_504 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_505 = 32'h00000020; - assign _zz_506 = 32'h00001030; - assign _zz_507 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_508 = 32'h00002020; - assign _zz_509 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_510 = 32'h00000020; - assign _zz_511 = 32'h00001010; - assign _zz_512 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_513 = 32'h00002010; - assign _zz_514 = ((decode_INSTRUCTION & _zz_528) == 32'h00000010); - assign _zz_515 = (_zz_529 == _zz_530); - assign _zz_516 = (_zz_531 == _zz_532); - assign _zz_517 = 32'h00000070; - assign _zz_518 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_519 = 32'h0; - assign _zz_520 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_521 = 32'h00004010; - assign _zz_522 = ((decode_INSTRUCTION & _zz_533) == 32'h00002010); - assign _zz_523 = {_zz_534,{_zz_535,_zz_536}}; - assign _zz_524 = 4'b0000; - assign _zz_525 = (_zz_537 != 1'b0); - assign _zz_526 = (_zz_538 != _zz_539); - assign _zz_527 = {_zz_540,{_zz_541,_zz_542}}; - assign _zz_528 = 32'h00000050; - assign _zz_529 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_530 = 32'h00000004; - assign _zz_531 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_532 = 32'h0; - assign _zz_533 = 32'h00006014; - assign _zz_534 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_535 = ((decode_INSTRUCTION & _zz_543) == 32'h0); - assign _zz_536 = {(_zz_544 == _zz_545),(_zz_546 == _zz_547)}; - assign _zz_537 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_538 = {(_zz_548 == _zz_549),{_zz_550,_zz_551}}; - assign _zz_539 = 3'b000; - assign _zz_540 = ({_zz_552,_zz_96} != 2'b00); - assign _zz_541 = ({_zz_553,_zz_554} != 2'b00); - assign _zz_542 = (_zz_555 != 1'b0); - assign _zz_543 = 32'h00000018; - assign _zz_544 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_545 = 32'h00002000; - assign _zz_546 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_547 = 32'h00001000; - assign _zz_548 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_549 = 32'h00000040; - assign _zz_550 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_551 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_552 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_553 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_554 = _zz_96; - assign _zz_555 = ((decode_INSTRUCTION & 32'h00001054) == 32'h00001004); - assign _zz_556 = execute_INSTRUCTION[31]; - assign _zz_557 = execute_INSTRUCTION[31]; - assign _zz_558 = execute_INSTRUCTION[7]; - assign _zz_559 = 32'h0; + assign _zz_359 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_360 = (iBus_cmd_payload_address >>> 5); + assign _zz_361 = 1'b1; + assign _zz_362 = 1'b1; + assign _zz_363 = {_zz_65,_zz_64}; + assign _zz_364 = 32'h0000106f; + assign _zz_365 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_366 = 32'h00001073; + assign _zz_367 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_368 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_369 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_370) == 32'h00000003),{(_zz_371 == _zz_372),{_zz_373,{_zz_374,_zz_375}}}}}}; + assign _zz_370 = 32'h0000207f; + assign _zz_371 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_372 = 32'h00000003; + assign _zz_373 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_374 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_375 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_376) == 32'h00005013),{(_zz_377 == _zz_378),{_zz_379,{_zz_380,_zz_381}}}}}}; + assign _zz_376 = 32'hbc00707f; + assign _zz_377 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_378 = 32'h00001013; + assign _zz_379 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_380 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_381 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_382 = decode_INSTRUCTION[31]; + assign _zz_383 = decode_INSTRUCTION[31]; + assign _zz_384 = decode_INSTRUCTION[7]; + assign _zz_385 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_386 = 32'h02004020; + assign _zz_387 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_388 = (_zz_97 != 1'b0); + assign _zz_389 = (((decode_INSTRUCTION & _zz_391) == 32'h00000050) != 1'b0); + assign _zz_390 = {((_zz_392 == _zz_393) != 1'b0),{({_zz_394,_zz_395} != 2'b00),{(_zz_396 != _zz_397),{_zz_398,{_zz_399,_zz_400}}}}}; + assign _zz_391 = 32'h00203050; + assign _zz_392 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_393 = 32'h00000050; + assign _zz_394 = ((decode_INSTRUCTION & _zz_401) == 32'h00001050); + assign _zz_395 = ((decode_INSTRUCTION & _zz_402) == 32'h00002050); + assign _zz_396 = {_zz_96,(_zz_403 == _zz_404)}; + assign _zz_397 = 2'b00; + assign _zz_398 = ((_zz_405 == _zz_406) != 1'b0); + assign _zz_399 = ({_zz_407,_zz_408} != 2'b00); + assign _zz_400 = {(_zz_409 != _zz_410),{_zz_411,{_zz_412,_zz_413}}}; + assign _zz_401 = 32'h00001050; + assign _zz_402 = 32'h00002050; + assign _zz_403 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_404 = 32'h00000004; + assign _zz_405 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_406 = 32'h00000040; + assign _zz_407 = ((decode_INSTRUCTION & _zz_414) == 32'h00005010); + assign _zz_408 = ((decode_INSTRUCTION & _zz_415) == 32'h00005020); + assign _zz_409 = {(_zz_416 == _zz_417),{_zz_418,_zz_419}}; + assign _zz_410 = 3'b000; + assign _zz_411 = ((_zz_420 == _zz_421) != 1'b0); + assign _zz_412 = (_zz_422 != 1'b0); + assign _zz_413 = {(_zz_423 != _zz_424),{_zz_425,{_zz_426,_zz_427}}}; + assign _zz_414 = 32'h00007034; + assign _zz_415 = 32'h02007064; + assign _zz_416 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_417 = 32'h40001010; + assign _zz_418 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_419 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_420 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_421 = 32'h00000024; + assign _zz_422 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_423 = ((decode_INSTRUCTION & _zz_428) == 32'h00002000); + assign _zz_424 = 1'b0; + assign _zz_425 = ({_zz_429,_zz_430} != 2'b00); + assign _zz_426 = (_zz_431 != 1'b0); + assign _zz_427 = {(_zz_432 != _zz_433),{_zz_434,{_zz_435,_zz_436}}}; + assign _zz_428 = 32'h00003000; + assign _zz_429 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_430 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_431 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_432 = {_zz_97,{_zz_437,_zz_438}}; + assign _zz_433 = 3'b000; + assign _zz_434 = ({_zz_439,{_zz_440,_zz_441}} != 5'h0); + assign _zz_435 = (_zz_442 != 1'b0); + assign _zz_436 = {(_zz_443 != _zz_444),{_zz_445,{_zz_446,_zz_447}}}; + assign _zz_437 = ((decode_INSTRUCTION & _zz_448) == 32'h00000020); + assign _zz_438 = ((decode_INSTRUCTION & _zz_449) == 32'h00000020); + assign _zz_439 = ((decode_INSTRUCTION & _zz_450) == 32'h00002040); + assign _zz_440 = (_zz_451 == _zz_452); + assign _zz_441 = {_zz_453,{_zz_454,_zz_455}}; + assign _zz_442 = ((decode_INSTRUCTION & _zz_456) == 32'h00000020); + assign _zz_443 = {_zz_457,{_zz_458,_zz_459}}; + assign _zz_444 = 6'h0; + assign _zz_445 = ({_zz_460,_zz_461} != 5'h0); + assign _zz_446 = (_zz_462 != _zz_463); + assign _zz_447 = {_zz_464,{_zz_465,_zz_466}}; + assign _zz_448 = 32'h00000034; + assign _zz_449 = 32'h00000064; + assign _zz_450 = 32'h00002040; + assign _zz_451 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_452 = 32'h00001040; + assign _zz_453 = ((decode_INSTRUCTION & _zz_467) == 32'h00000040); + assign _zz_454 = (_zz_468 == _zz_469); + assign _zz_455 = (_zz_470 == _zz_471); + assign _zz_456 = 32'h00000020; + assign _zz_457 = ((decode_INSTRUCTION & _zz_472) == 32'h00000008); + assign _zz_458 = (_zz_473 == _zz_474); + assign _zz_459 = {_zz_95,{_zz_475,_zz_476}}; + assign _zz_460 = _zz_95; + assign _zz_461 = {_zz_477,{_zz_478,_zz_479}}; + assign _zz_462 = {_zz_96,{_zz_480,_zz_481}}; + assign _zz_463 = 6'h0; + assign _zz_464 = ({_zz_482,_zz_483} != 2'b00); + assign _zz_465 = (_zz_484 != _zz_485); + assign _zz_466 = {_zz_486,{_zz_487,_zz_488}}; + assign _zz_467 = 32'h00000050; + assign _zz_468 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_469 = 32'h00000040; + assign _zz_470 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_471 = 32'h0; + assign _zz_472 = 32'h00000008; + assign _zz_473 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_474 = 32'h00000040; + assign _zz_475 = (_zz_489 == _zz_490); + assign _zz_476 = {_zz_491,_zz_492}; + assign _zz_477 = ((decode_INSTRUCTION & _zz_493) == 32'h00002010); + assign _zz_478 = (_zz_494 == _zz_495); + assign _zz_479 = {_zz_496,_zz_497}; + assign _zz_480 = (_zz_498 == _zz_499); + assign _zz_481 = {_zz_500,{_zz_501,_zz_502}}; + assign _zz_482 = _zz_95; + assign _zz_483 = (_zz_503 == _zz_504); + assign _zz_484 = {_zz_95,_zz_505}; + assign _zz_485 = 2'b00; + assign _zz_486 = (_zz_506 != 1'b0); + assign _zz_487 = (_zz_507 != _zz_508); + assign _zz_488 = {_zz_509,{_zz_510,_zz_511}}; + assign _zz_489 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_490 = 32'h00004020; + assign _zz_491 = ((decode_INSTRUCTION & _zz_512) == 32'h00000010); + assign _zz_492 = ((decode_INSTRUCTION & _zz_513) == 32'h00000020); + assign _zz_493 = 32'h00002030; + assign _zz_494 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_495 = 32'h00000010; + assign _zz_496 = ((decode_INSTRUCTION & _zz_514) == 32'h00002020); + assign _zz_497 = ((decode_INSTRUCTION & _zz_515) == 32'h00000020); + assign _zz_498 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_499 = 32'h00001010; + assign _zz_500 = ((decode_INSTRUCTION & _zz_516) == 32'h00002010); + assign _zz_501 = (_zz_517 == _zz_518); + assign _zz_502 = {_zz_519,_zz_520}; + assign _zz_503 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_504 = 32'h00000020; + assign _zz_505 = ((decode_INSTRUCTION & _zz_521) == 32'h0); + assign _zz_506 = ((decode_INSTRUCTION & _zz_522) == 32'h00004010); + assign _zz_507 = (_zz_523 == _zz_524); + assign _zz_508 = 1'b0; + assign _zz_509 = ({_zz_525,_zz_526} != 4'b0000); + assign _zz_510 = (_zz_527 != _zz_528); + assign _zz_511 = {_zz_529,{_zz_530,_zz_531}}; + assign _zz_512 = 32'h00000030; + assign _zz_513 = 32'h02000020; + assign _zz_514 = 32'h02002060; + assign _zz_515 = 32'h02003020; + assign _zz_516 = 32'h00002010; + assign _zz_517 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_518 = 32'h00000010; + assign _zz_519 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_520 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_521 = 32'h00000020; + assign _zz_522 = 32'h00004014; + assign _zz_523 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_524 = 32'h00002010; + assign _zz_525 = ((decode_INSTRUCTION & _zz_532) == 32'h0); + assign _zz_526 = {(_zz_533 == _zz_534),{_zz_535,_zz_536}}; + assign _zz_527 = ((decode_INSTRUCTION & _zz_537) == 32'h0); + assign _zz_528 = 1'b0; + assign _zz_529 = ({_zz_538,{_zz_539,_zz_540}} != 3'b000); + assign _zz_530 = ({_zz_541,_zz_542} != 2'b00); + assign _zz_531 = {(_zz_543 != _zz_544),(_zz_545 != _zz_546)}; + assign _zz_532 = 32'h00000044; + assign _zz_533 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_534 = 32'h0; + assign _zz_535 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_536 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_537 = 32'h00000058; + assign _zz_538 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_539 = ((decode_INSTRUCTION & _zz_547) == 32'h00002010); + assign _zz_540 = ((decode_INSTRUCTION & _zz_548) == 32'h40000030); + assign _zz_541 = ((decode_INSTRUCTION & _zz_549) == 32'h00000004); + assign _zz_542 = _zz_94; + assign _zz_543 = {(_zz_550 == _zz_551),_zz_94}; + assign _zz_544 = 2'b00; + assign _zz_545 = ((decode_INSTRUCTION & _zz_552) == 32'h00001004); + assign _zz_546 = 1'b0; + assign _zz_547 = 32'h00002014; + assign _zz_548 = 32'h40000034; + assign _zz_549 = 32'h00000014; + assign _zz_550 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_551 = 32'h00000004; + assign _zz_552 = 32'h00005054; + assign _zz_553 = execute_INSTRUCTION[31]; + assign _zz_554 = execute_INSTRUCTION[31]; + assign _zz_555 = execute_INSTRUCTION[7]; + assign _zz_556 = 32'h0; always @ (posedge clk) begin - if(_zz_365) begin - _zz_223 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_361) begin + _zz_221 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_366) begin - _zz_224 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_362) begin + _zz_222 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1692,13 +1690,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_214 ), //i - .io_cpu_prefetch_isValid (_zz_215 ), //i + .io_flush (_zz_193 ), //i + .io_cpu_prefetch_isValid (_zz_194 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_216 ), //i - .io_cpu_fetch_isStuck (_zz_217 ), //i - .io_cpu_fetch_isRemoved (_zz_218 ), //i + .io_cpu_fetch_isValid (_zz_195 ), //i + .io_cpu_fetch_isStuck (_zz_196 ), //i + .io_cpu_fetch_isRemoved (_zz_197 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1711,8 +1709,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_219 ), //i - .io_cpu_decode_isStuck (_zz_220 ), //i + .io_cpu_decode_isValid (_zz_198 ), //i + .io_cpu_decode_isStuck (_zz_199 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1720,8 +1718,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_221 ), //i - .io_cpu_fill_valid (_zz_222 ), //i + .io_cpu_decode_isUser (_zz_200 ), //i + .io_cpu_fill_valid (_zz_201 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1733,19 +1731,80 @@ module VexRiscv ( .clk (clk ), //i .reset (reset ) //i ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_202 ), //i + .io_cpu_execute_address (_zz_203[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_88[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_204 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_205[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_206 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_207 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_208 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_209[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_210 ), //i + .io_cpu_writeBack_fence_SR (_zz_211 ), //i + .io_cpu_writeBack_fence_SO (_zz_212 ), //i + .io_cpu_writeBack_fence_SI (_zz_213 ), //i + .io_cpu_writeBack_fence_PW (_zz_214 ), //i + .io_cpu_writeBack_fence_PR (_zz_215 ), //i + .io_cpu_writeBack_fence_PO (_zz_216 ), //i + .io_cpu_writeBack_fence_PI (_zz_217 ), //i + .io_cpu_writeBack_fence_FM (_zz_218[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_219 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_220 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); always @(*) begin - case(_zz_367) + case(_zz_363) 2'b00 : begin - _zz_225 = CsrPlugin_jumpInterface_payload; + _zz_223 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_225 = DBusSimplePlugin_redoBranch_payload; + _zz_223 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_225 = BranchPlugin_jumpInterface_payload; + _zz_223 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_225 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_223 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2336,71 +2395,71 @@ module VexRiscv ( endcase end always @(*) begin - case(_zz_101) - `Src1CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_101_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_101_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_101_string = "URS1 "; - default : _zz_101_string = "????????????"; + case(_zz_99) + `Src1CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_99_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99_string = "URS1 "; + default : _zz_99_string = "????????????"; endcase end always @(*) begin - case(_zz_102) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_102_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_102_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_102_string = "BITWISE "; - default : _zz_102_string = "????????"; + case(_zz_100) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_100_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_100_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_100_string = "BITWISE "; + default : _zz_100_string = "????????"; endcase end always @(*) begin - case(_zz_103) - `Src2CtrlEnum_defaultEncoding_RS : _zz_103_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_103_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_103_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_103_string = "PC "; - default : _zz_103_string = "???"; + case(_zz_101) + `Src2CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_101_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_101_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_101_string = "PC "; + default : _zz_101_string = "???"; endcase end always @(*) begin - case(_zz_104) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_104_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_104_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_104_string = "AND_1"; - default : _zz_104_string = "?????"; + case(_zz_102) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_102_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_102_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_102_string = "AND_1"; + default : _zz_102_string = "?????"; endcase end always @(*) begin - case(_zz_105) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_105_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_105_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_105_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_105_string = "SRA_1 "; - default : _zz_105_string = "?????????"; + case(_zz_103) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_103_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_103_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_103_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_103_string = "SRA_1 "; + default : _zz_103_string = "?????????"; endcase end always @(*) begin - case(_zz_106) - `BranchCtrlEnum_defaultEncoding_INC : _zz_106_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_106_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_106_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_106_string = "JALR"; - default : _zz_106_string = "????"; + case(_zz_104) + `BranchCtrlEnum_defaultEncoding_INC : _zz_104_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_104_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_104_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_104_string = "JALR"; + default : _zz_104_string = "????"; endcase end always @(*) begin - case(_zz_107) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_107_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_107_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_107_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_107_string = "ECALL"; - default : _zz_107_string = "?????"; + case(_zz_105) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_105_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_105_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_105_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_105_string = "ECALL"; + default : _zz_105_string = "?????"; endcase end always @(*) begin - case(_zz_108) - `Input2Kind_defaultEncoding_RS : _zz_108_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_108_string = "IMM_I"; - default : _zz_108_string = "?????"; + case(_zz_106) + `Input2Kind_defaultEncoding_RS : _zz_106_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_106_string = "IMM_I"; + default : _zz_106_string = "?????"; endcase end always @(*) begin @@ -2500,8 +2559,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_267) + $signed(_zz_275)); - assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign memory_MUL_LOW = ($signed(_zz_263) + $signed(_zz_271)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2509,50 +2567,53 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_277; - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_110; + assign execute_SHIFT_RIGHT = _zz_273; + assign execute_REGFILE_WRITE_DATA = _zz_108; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_203[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_279[0]; - assign decode_IS_RS1_SIGNED = _zz_280[0]; - assign decode_IS_DIV = _zz_281[0]; + assign decode_IS_RS2_SIGNED = _zz_275[0]; + assign decode_IS_RS1_SIGNED = _zz_276[0]; + assign decode_IS_DIV = _zz_277[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_282[0]; + assign decode_IS_MUL = _zz_278[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_283[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_279[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_284[0]; + assign decode_IS_CSR = _zz_280[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_285[0]; - assign decode_MEMORY_STORE = _zz_286[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_281[0]; + assign decode_MEMORY_MANAGMENT = _zz_282[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_283[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_287[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_288[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_284[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_285[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; assign _zz_25 = _zz_26; assign decode_SRC1_CTRL = _zz_27; assign _zz_28 = _zz_29; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2591,13 +2652,13 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_132; + assign execute_BRANCH_COND_RESULT = _zz_130; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_289[0]; - assign decode_RS1_USE = _zz_290[0]; + assign decode_RS2_USE = _zz_286[0]; + assign decode_RS1_USE = _zz_287[0]; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_226)begin + if(_zz_224)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2610,28 +2671,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_121)begin - if((_zz_122 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_123; + if(_zz_119)begin + if((_zz_120 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_121; end end - if(_zz_227)begin - if(_zz_228)begin - if(_zz_125)begin + if(_zz_225)begin + if(_zz_226)begin + if(_zz_123)begin decode_RS2 = _zz_57; end end end - if(_zz_229)begin + if(_zz_227)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_127)begin + if(_zz_125)begin decode_RS2 = _zz_38; end end end - if(_zz_230)begin + if(_zz_228)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_129)begin + if(_zz_127)begin decode_RS2 = _zz_37; end end @@ -2640,28 +2701,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_121)begin - if((_zz_122 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_123; + if(_zz_119)begin + if((_zz_120 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_121; end end - if(_zz_227)begin - if(_zz_228)begin - if(_zz_124)begin + if(_zz_225)begin + if(_zz_226)begin + if(_zz_122)begin decode_RS1 = _zz_57; end end end - if(_zz_229)begin + if(_zz_227)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_126)begin + if(_zz_124)begin decode_RS1 = _zz_38; end end end - if(_zz_230)begin + if(_zz_228)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_128)begin + if(_zz_126)begin decode_RS1 = _zz_37; end end @@ -2674,7 +2735,7 @@ module VexRiscv ( if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_118; + _zz_38 = _zz_116; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin _zz_38 = memory_SHIFT_RIGHT; @@ -2686,7 +2747,7 @@ module VexRiscv ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_231)begin + if(_zz_229)begin _zz_38 = memory_DivPlugin_div_result; end end @@ -2699,13 +2760,13 @@ module VexRiscv ( assign _zz_41 = execute_PC; assign execute_SRC2_CTRL = _zz_42; assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_291[0]; - assign decode_SRC_ADD_ZERO = _zz_292[0]; + assign decode_SRC_USE_SUB_LESS = _zz_288[0]; + assign decode_SRC_ADD_ZERO = _zz_289[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_116; - assign execute_SRC1 = _zz_111; + assign execute_SRC2 = _zz_114; + assign execute_SRC1 = _zz_109; assign execute_ALU_BITWISE_CTRL = _zz_45; assign _zz_46 = writeBack_INSTRUCTION; assign _zz_47 = writeBack_REGFILE_WRITE_VALID; @@ -2718,91 +2779,69 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_293[0]; + decode_REGFILE_WRITE_VALID = _zz_290[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_368) == 32'h00000003),{(_zz_369 == _zz_370),{_zz_371,{_zz_372,_zz_373}}}}}}} != 21'h0); - assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_364) == 32'h00000003),{(_zz_365 == _zz_366),{_zz_367,{_zz_368,_zz_369}}}}}}} != 22'h0); always @ (*) begin _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_57 = writeBack_DBusSimplePlugin_rspFormated; + _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_266) + case(_zz_262) 2'b00 : begin - _zz_57 = _zz_340; + _zz_57 = _zz_336; end default : begin - _zz_57 = _zz_341; + _zz_57 = _zz_337; end endcase end end - assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; - assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; - assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; - assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; - assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; - assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; - assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; - assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; - assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; - assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; - assign memory_PC = execute_to_memory_PC; - assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; - assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); - assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; - assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; - assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; - assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; - assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_294[0]; - assign decode_FLUSH_ALL = _zz_295[0]; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_291[0]; + assign decode_FLUSH_ALL = _zz_292[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_232)begin + if(_zz_230)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_233)begin + if(_zz_231)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_234)begin + if(_zz_232)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_235)begin + if(_zz_233)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2817,16 +2856,9 @@ module VexRiscv ( end always @ (*) begin - _zz_60 = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_60 = DBusSimplePlugin_redoBranch_payload; - end - end - - always @ (*) begin - _zz_61 = decode_FORMAL_PC_NEXT; + _zz_60 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_61 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; end end @@ -2835,14 +2867,14 @@ module VexRiscv ( assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end end always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_119 || _zz_120)))begin + if((decode_arbitration_isValid && (_zz_117 || _zz_118)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2855,7 +2887,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_236)begin + if(_zz_234)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2869,22 +2901,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_236)begin + if(_zz_234)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_88)))begin + if(((_zz_219 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_237)begin + if(_zz_235)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_226)begin + if(_zz_224)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2894,10 +2926,16 @@ module VexRiscv ( end end - assign execute_arbitration_haltByOther = 1'b0; + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + end + always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_238)begin + if(_zz_236)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -2911,22 +2949,19 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_238)begin + if(_zz_236)begin execute_arbitration_flushNext = 1'b1; end end always @ (*) begin memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin - memory_arbitration_haltItself = 1'b1; - end if(memory_CfuPlugin_CFU_IN_FLIGHT)begin if((! memory_CfuPlugin_rsp_valid))begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_231)begin + if(_zz_229)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -2936,7 +2971,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_239)begin + if(CfuPlugin_joinException_valid)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -2944,39 +2979,51 @@ module VexRiscv ( end end + assign memory_arbitration_flushIt = 1'b0; always @ (*) begin - memory_arbitration_flushIt = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; + memory_arbitration_flushNext = 1'b0; + if(CfuPlugin_joinException_valid)begin + memory_arbitration_flushNext = 1'b1; end end always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(_zz_239)begin - memory_arbitration_flushNext = 1'b1; + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; end end - assign writeBack_arbitration_haltItself = 1'b0; assign writeBack_arbitration_haltByOther = 1'b0; always @ (*) begin writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end if(writeBack_arbitration_isFlushed)begin writeBack_arbitration_removeIt = 1'b1; end end - assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_240)begin + if(DBusCachedPlugin_redoBranch_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_241)begin + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_237)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_238)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2990,10 +3037,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_240)begin + if(_zz_237)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_241)begin + if(_zz_238)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3007,7 +3054,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_237)begin + if(_zz_235)begin CsrPlugin_inWfi = 1'b1; end end @@ -3015,21 +3062,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_240)begin + if(_zz_237)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_241)begin + if(_zz_238)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_240)begin + if(_zz_237)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_241)begin - case(_zz_242) + if(_zz_238)begin + case(_zz_239) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3043,13 +3090,13 @@ module VexRiscv ( assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; - assign _zz_63 = (_zz_62 & (~ _zz_296)); - assign _zz_64 = _zz_63[3]; - assign _zz_65 = (_zz_63[1] || _zz_64); - assign _zz_66 = (_zz_63[2] || _zz_64); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_225; + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_62 = (_zz_61 & (~ _zz_293)); + assign _zz_63 = _zz_62[3]; + assign _zz_64 = (_zz_62[1] || _zz_63); + assign _zz_65 = (_zz_62[2] || _zz_63); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_223; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3069,7 +3116,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_298); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_295); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3109,9 +3156,9 @@ module VexRiscv ( end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_67); + assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_66); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; @@ -3120,9 +3167,9 @@ module VexRiscv ( end end - assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_68); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_68); + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_67); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; always @ (*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; @@ -3131,22 +3178,22 @@ module VexRiscv ( end end - assign _zz_69 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_69); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_69); + assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_68); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_70; - assign _zz_70 = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_71 = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_69; + assign _zz_69 = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_70 = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_70; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_73)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_73 = _zz_74; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_73; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_75; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_72)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_72 = _zz_73; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_74; always @ (*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; if((! IBusCachedPlugin_pcValids_0))begin @@ -3160,125 +3207,125 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_76 = _zz_299[11]; - always @ (*) begin - _zz_77[18] = _zz_76; - _zz_77[17] = _zz_76; - _zz_77[16] = _zz_76; - _zz_77[15] = _zz_76; - _zz_77[14] = _zz_76; - _zz_77[13] = _zz_76; - _zz_77[12] = _zz_76; - _zz_77[11] = _zz_76; - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7] = _zz_76; - _zz_77[6] = _zz_76; - _zz_77[5] = _zz_76; - _zz_77[4] = _zz_76; - _zz_77[3] = _zz_76; - _zz_77[2] = _zz_76; - _zz_77[1] = _zz_76; - _zz_77[0] = _zz_76; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_300[31])); - if(_zz_82)begin + assign _zz_75 = _zz_296[11]; + always @ (*) begin + _zz_76[18] = _zz_75; + _zz_76[17] = _zz_75; + _zz_76[16] = _zz_75; + _zz_76[15] = _zz_75; + _zz_76[14] = _zz_75; + _zz_76[13] = _zz_75; + _zz_76[12] = _zz_75; + _zz_76[11] = _zz_75; + _zz_76[10] = _zz_75; + _zz_76[9] = _zz_75; + _zz_76[8] = _zz_75; + _zz_76[7] = _zz_75; + _zz_76[6] = _zz_75; + _zz_76[5] = _zz_75; + _zz_76[4] = _zz_75; + _zz_76[3] = _zz_75; + _zz_76[2] = _zz_75; + _zz_76[1] = _zz_75; + _zz_76[0] = _zz_75; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_297[31])); + if(_zz_81)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_78 = _zz_301[19]; + assign _zz_77 = _zz_298[19]; always @ (*) begin - _zz_79[10] = _zz_78; - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7] = _zz_78; - _zz_79[6] = _zz_78; - _zz_79[5] = _zz_78; - _zz_79[4] = _zz_78; - _zz_79[3] = _zz_78; - _zz_79[2] = _zz_78; - _zz_79[1] = _zz_78; - _zz_79[0] = _zz_78; + _zz_78[10] = _zz_77; + _zz_78[9] = _zz_77; + _zz_78[8] = _zz_77; + _zz_78[7] = _zz_77; + _zz_78[6] = _zz_77; + _zz_78[5] = _zz_77; + _zz_78[4] = _zz_77; + _zz_78[3] = _zz_77; + _zz_78[2] = _zz_77; + _zz_78[1] = _zz_77; + _zz_78[0] = _zz_77; end - assign _zz_80 = _zz_302[11]; + assign _zz_79 = _zz_299[11]; always @ (*) begin - _zz_81[18] = _zz_80; - _zz_81[17] = _zz_80; - _zz_81[16] = _zz_80; - _zz_81[15] = _zz_80; - _zz_81[14] = _zz_80; - _zz_81[13] = _zz_80; - _zz_81[12] = _zz_80; - _zz_81[11] = _zz_80; - _zz_81[10] = _zz_80; - _zz_81[9] = _zz_80; - _zz_81[8] = _zz_80; - _zz_81[7] = _zz_80; - _zz_81[6] = _zz_80; - _zz_81[5] = _zz_80; - _zz_81[4] = _zz_80; - _zz_81[3] = _zz_80; - _zz_81[2] = _zz_80; - _zz_81[1] = _zz_80; - _zz_81[0] = _zz_80; + _zz_80[18] = _zz_79; + _zz_80[17] = _zz_79; + _zz_80[16] = _zz_79; + _zz_80[15] = _zz_79; + _zz_80[14] = _zz_79; + _zz_80[13] = _zz_79; + _zz_80[12] = _zz_79; + _zz_80[11] = _zz_79; + _zz_80[10] = _zz_79; + _zz_80[9] = _zz_79; + _zz_80[8] = _zz_79; + _zz_80[7] = _zz_79; + _zz_80[6] = _zz_79; + _zz_80[5] = _zz_79; + _zz_80[4] = _zz_79; + _zz_80[3] = _zz_79; + _zz_80[2] = _zz_79; + _zz_80[1] = _zz_79; + _zz_80[0] = _zz_79; end always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_82 = _zz_303[1]; + _zz_81 = _zz_300[1]; end default : begin - _zz_82 = _zz_304[1]; + _zz_81 = _zz_301[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_83 = _zz_305[19]; - always @ (*) begin - _zz_84[10] = _zz_83; - _zz_84[9] = _zz_83; - _zz_84[8] = _zz_83; - _zz_84[7] = _zz_83; - _zz_84[6] = _zz_83; - _zz_84[5] = _zz_83; - _zz_84[4] = _zz_83; - _zz_84[3] = _zz_83; - _zz_84[2] = _zz_83; - _zz_84[1] = _zz_83; - _zz_84[0] = _zz_83; - end - - assign _zz_85 = _zz_306[11]; - always @ (*) begin - _zz_86[18] = _zz_85; - _zz_86[17] = _zz_85; - _zz_86[16] = _zz_85; - _zz_86[15] = _zz_85; - _zz_86[14] = _zz_85; - _zz_86[13] = _zz_85; - _zz_86[12] = _zz_85; - _zz_86[11] = _zz_85; - _zz_86[10] = _zz_85; - _zz_86[9] = _zz_85; - _zz_86[8] = _zz_85; - _zz_86[7] = _zz_85; - _zz_86[6] = _zz_85; - _zz_86[5] = _zz_85; - _zz_86[4] = _zz_85; - _zz_86[3] = _zz_85; - _zz_86[2] = _zz_85; - _zz_86[1] = _zz_85; - _zz_86[0] = _zz_85; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_386,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_387,_zz_388},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_82 = _zz_302[19]; + always @ (*) begin + _zz_83[10] = _zz_82; + _zz_83[9] = _zz_82; + _zz_83[8] = _zz_82; + _zz_83[7] = _zz_82; + _zz_83[6] = _zz_82; + _zz_83[5] = _zz_82; + _zz_83[4] = _zz_82; + _zz_83[3] = _zz_82; + _zz_83[2] = _zz_82; + _zz_83[1] = _zz_82; + _zz_83[0] = _zz_82; + end + + assign _zz_84 = _zz_303[11]; + always @ (*) begin + _zz_85[18] = _zz_84; + _zz_85[17] = _zz_84; + _zz_85[16] = _zz_84; + _zz_85[15] = _zz_84; + _zz_85[14] = _zz_84; + _zz_85[13] = _zz_84; + _zz_85[12] = _zz_84; + _zz_85[11] = _zz_84; + _zz_85[10] = _zz_84; + _zz_85[9] = _zz_84; + _zz_85[8] = _zz_84; + _zz_85[7] = _zz_84; + _zz_85[6] = _zz_84; + _zz_85[5] = _zz_84; + _zz_85[4] = _zz_84; + _zz_85[3] = _zz_84; + _zz_85[2] = _zz_84; + _zz_85[1] = _zz_84; + _zz_85[0] = _zz_84; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_382,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_383,_zz_384},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3287,52 +3334,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_215 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_216 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_217 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_216; + assign _zz_194 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_195 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_196 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_195; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_221 = (CsrPlugin_privilege == 2'b00); + assign _zz_198 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_199 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_200 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_235)begin + if(_zz_233)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_233)begin + if(_zz_231)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_222 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_233)begin - _zz_222 = 1'b1; + _zz_201 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_231)begin + _zz_201 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_234)begin + if(_zz_232)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_232)begin + if(_zz_230)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_234)begin + if(_zz_232)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_232)begin + if(_zz_230)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3342,122 +3389,160 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_214 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign _zz_88 = 1'b0; - always @ (*) begin - execute_DBusSimplePlugin_skipCmd = 1'b0; - if(execute_ALIGNEMENT_FAULT)begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - end - - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_88)); - assign dBus_cmd_payload_wr = execute_MEMORY_STORE; - assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin - case(dBus_cmd_payload_size) + assign _zz_193 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_220 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_202 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_203 = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_88 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_89 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_88 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_89 = execute_RS2[31 : 0]; + _zz_88 = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_89; + assign _zz_219 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_204 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_205 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_204; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_205; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - case(dBus_cmd_payload_size) - 2'b00 : begin - _zz_90 = 4'b0001; - end - 2'b01 : begin - _zz_90 = 4'b0011; - end - default : begin - _zz_90 = 4'b1111; - end - endcase + _zz_206 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_206 = 1'b1; + end end - assign execute_DBusSimplePlugin_formalMask = (_zz_90 <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; - assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign _zz_207 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_208 = (CsrPlugin_privilege == 2'b00); + assign _zz_209 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_243)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end else begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_240)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; end end - if(_zz_244)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end end + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_243)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; - end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_307}; - end - if(! memory_MMU_RSP2_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_240)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end - assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_redoBranch_valid = 1'b1; - end - if(_zz_244)begin - DBusSimplePlugin_redoBranch_valid = 1'b0; + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_240)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_304}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_305}; + end end end - assign DBusSimplePlugin_redoBranch_payload = memory_PC; always @ (*) begin - writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; end 2'b10 : begin - writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; end 2'b11 : begin - writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; end default : begin end endcase end - assign _zz_91 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + assign _zz_89 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_90[31] = _zz_89; + _zz_90[30] = _zz_89; + _zz_90[29] = _zz_89; + _zz_90[28] = _zz_89; + _zz_90[27] = _zz_89; + _zz_90[26] = _zz_89; + _zz_90[25] = _zz_89; + _zz_90[24] = _zz_89; + _zz_90[23] = _zz_89; + _zz_90[22] = _zz_89; + _zz_90[21] = _zz_89; + _zz_90[20] = _zz_89; + _zz_90[19] = _zz_89; + _zz_90[18] = _zz_89; + _zz_90[17] = _zz_89; + _zz_90[16] = _zz_89; + _zz_90[15] = _zz_89; + _zz_90[14] = _zz_89; + _zz_90[13] = _zz_89; + _zz_90[12] = _zz_89; + _zz_90[11] = _zz_89; + _zz_90[10] = _zz_89; + _zz_90[9] = _zz_89; + _zz_90[8] = _zz_89; + _zz_90[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_91 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); always @ (*) begin _zz_92[31] = _zz_91; _zz_92[30] = _zz_91; @@ -3475,48 +3560,19 @@ module VexRiscv ( _zz_92[18] = _zz_91; _zz_92[17] = _zz_91; _zz_92[16] = _zz_91; - _zz_92[15] = _zz_91; - _zz_92[14] = _zz_91; - _zz_92[13] = _zz_91; - _zz_92[12] = _zz_91; - _zz_92[11] = _zz_91; - _zz_92[10] = _zz_91; - _zz_92[9] = _zz_91; - _zz_92[8] = _zz_91; - _zz_92[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_93 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_94[31] = _zz_93; - _zz_94[30] = _zz_93; - _zz_94[29] = _zz_93; - _zz_94[28] = _zz_93; - _zz_94[27] = _zz_93; - _zz_94[26] = _zz_93; - _zz_94[25] = _zz_93; - _zz_94[24] = _zz_93; - _zz_94[23] = _zz_93; - _zz_94[22] = _zz_93; - _zz_94[21] = _zz_93; - _zz_94[20] = _zz_93; - _zz_94[19] = _zz_93; - _zz_94[18] = _zz_93; - _zz_94[17] = _zz_93; - _zz_94[16] = _zz_93; - _zz_94[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_264) + _zz_92[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_260) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_92; + writeBack_DBusCachedPlugin_rspFormated = _zz_90; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_94; + writeBack_DBusCachedPlugin_rspFormated = _zz_92; end default : begin - writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; end endcase end @@ -3530,61 +3586,61 @@ module VexRiscv ( assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_96 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_97 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_98 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_99 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_100 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_95 = {(_zz_100 != 1'b0),{(_zz_100 != 1'b0),{((_zz_389 == _zz_390) != 1'b0),{(_zz_391 != 1'b0),{1'b0,{_zz_392,{_zz_393,_zz_394}}}}}}}; - assign _zz_101 = _zz_95[2 : 1]; - assign _zz_56 = _zz_101; - assign _zz_102 = _zz_95[7 : 6]; - assign _zz_55 = _zz_102; - assign _zz_103 = _zz_95[9 : 8]; - assign _zz_54 = _zz_103; - assign _zz_104 = _zz_95[18 : 17]; - assign _zz_53 = _zz_104; - assign _zz_105 = _zz_95[21 : 20]; - assign _zz_52 = _zz_105; - assign _zz_106 = _zz_95[23 : 22]; - assign _zz_51 = _zz_106; - assign _zz_107 = _zz_95[26 : 25]; - assign _zz_50 = _zz_107; - assign _zz_108 = _zz_95[28 : 28]; - assign _zz_49 = _zz_108; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_94 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_95 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_385 == _zz_386) != 1'b0),{(_zz_387 != 1'b0),{1'b0,{_zz_388,{_zz_389,_zz_390}}}}}}}; + assign _zz_99 = _zz_93[2 : 1]; + assign _zz_56 = _zz_99; + assign _zz_100 = _zz_93[7 : 6]; + assign _zz_55 = _zz_100; + assign _zz_101 = _zz_93[9 : 8]; + assign _zz_54 = _zz_101; + assign _zz_102 = _zz_93[19 : 18]; + assign _zz_53 = _zz_102; + assign _zz_103 = _zz_93[22 : 21]; + assign _zz_52 = _zz_103; + assign _zz_104 = _zz_93[24 : 23]; + assign _zz_51 = _zz_104; + assign _zz_105 = _zz_93[27 : 26]; + assign _zz_50 = _zz_105; + assign _zz_106 = _zz_93[29 : 29]; + assign _zz_49 = _zz_106; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_223; - assign decode_RegFilePlugin_rs2Data = _zz_224; + assign decode_RegFilePlugin_rs1Data = _zz_221; + assign decode_RegFilePlugin_rs2Data = _zz_222; always @ (*) begin lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_109)begin + if(_zz_107)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_109)begin + if(_zz_107)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_109)begin + if(_zz_107)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -3606,13 +3662,13 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_110 = execute_IntAluPlugin_bitwise; + _zz_108 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_110 = {31'd0, _zz_308}; + _zz_108 = {31'd0, _zz_306}; end default : begin - _zz_110 = execute_SRC_ADD_SUB; + _zz_108 = execute_SRC_ADD_SUB; end endcase end @@ -3620,21 +3676,45 @@ module VexRiscv ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_111 = execute_RS1; + _zz_109 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_111 = {29'd0, _zz_309}; + _zz_109 = {29'd0, _zz_307}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_111 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_111 = {27'd0, _zz_310}; + _zz_109 = {27'd0, _zz_308}; end endcase end - assign _zz_112 = _zz_311[11]; + assign _zz_110 = _zz_309[11]; + always @ (*) begin + _zz_111[19] = _zz_110; + _zz_111[18] = _zz_110; + _zz_111[17] = _zz_110; + _zz_111[16] = _zz_110; + _zz_111[15] = _zz_110; + _zz_111[14] = _zz_110; + _zz_111[13] = _zz_110; + _zz_111[12] = _zz_110; + _zz_111[11] = _zz_110; + _zz_111[10] = _zz_110; + _zz_111[9] = _zz_110; + _zz_111[8] = _zz_110; + _zz_111[7] = _zz_110; + _zz_111[6] = _zz_110; + _zz_111[5] = _zz_110; + _zz_111[4] = _zz_110; + _zz_111[3] = _zz_110; + _zz_111[2] = _zz_110; + _zz_111[1] = _zz_110; + _zz_111[0] = _zz_110; + end + + assign _zz_112 = _zz_310[11]; always @ (*) begin _zz_113[19] = _zz_112; _zz_113[18] = _zz_112; @@ -3658,49 +3738,25 @@ module VexRiscv ( _zz_113[0] = _zz_112; end - assign _zz_114 = _zz_312[11]; - always @ (*) begin - _zz_115[19] = _zz_114; - _zz_115[18] = _zz_114; - _zz_115[17] = _zz_114; - _zz_115[16] = _zz_114; - _zz_115[15] = _zz_114; - _zz_115[14] = _zz_114; - _zz_115[13] = _zz_114; - _zz_115[12] = _zz_114; - _zz_115[11] = _zz_114; - _zz_115[10] = _zz_114; - _zz_115[9] = _zz_114; - _zz_115[8] = _zz_114; - _zz_115[7] = _zz_114; - _zz_115[6] = _zz_114; - _zz_115[5] = _zz_114; - _zz_115[4] = _zz_114; - _zz_115[3] = _zz_114; - _zz_115[2] = _zz_114; - _zz_115[1] = _zz_114; - _zz_115[0] = _zz_114; - end - always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_116 = execute_RS2; + _zz_114 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_116 = {_zz_113,execute_INSTRUCTION[31 : 20]}; + _zz_114 = {_zz_111,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_116 = {_zz_115,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_114 = {_zz_113,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_116 = _zz_41; + _zz_114 = _zz_41; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_313; + execute_SrcPlugin_addSub = _zz_311; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3709,180 +3765,195 @@ module VexRiscv ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_117[0] = execute_SRC1[31]; - _zz_117[1] = execute_SRC1[30]; - _zz_117[2] = execute_SRC1[29]; - _zz_117[3] = execute_SRC1[28]; - _zz_117[4] = execute_SRC1[27]; - _zz_117[5] = execute_SRC1[26]; - _zz_117[6] = execute_SRC1[25]; - _zz_117[7] = execute_SRC1[24]; - _zz_117[8] = execute_SRC1[23]; - _zz_117[9] = execute_SRC1[22]; - _zz_117[10] = execute_SRC1[21]; - _zz_117[11] = execute_SRC1[20]; - _zz_117[12] = execute_SRC1[19]; - _zz_117[13] = execute_SRC1[18]; - _zz_117[14] = execute_SRC1[17]; - _zz_117[15] = execute_SRC1[16]; - _zz_117[16] = execute_SRC1[15]; - _zz_117[17] = execute_SRC1[14]; - _zz_117[18] = execute_SRC1[13]; - _zz_117[19] = execute_SRC1[12]; - _zz_117[20] = execute_SRC1[11]; - _zz_117[21] = execute_SRC1[10]; - _zz_117[22] = execute_SRC1[9]; - _zz_117[23] = execute_SRC1[8]; - _zz_117[24] = execute_SRC1[7]; - _zz_117[25] = execute_SRC1[6]; - _zz_117[26] = execute_SRC1[5]; - _zz_117[27] = execute_SRC1[4]; - _zz_117[28] = execute_SRC1[3]; - _zz_117[29] = execute_SRC1[2]; - _zz_117[30] = execute_SRC1[1]; - _zz_117[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_117 : execute_SRC1); - always @ (*) begin - _zz_118[0] = memory_SHIFT_RIGHT[31]; - _zz_118[1] = memory_SHIFT_RIGHT[30]; - _zz_118[2] = memory_SHIFT_RIGHT[29]; - _zz_118[3] = memory_SHIFT_RIGHT[28]; - _zz_118[4] = memory_SHIFT_RIGHT[27]; - _zz_118[5] = memory_SHIFT_RIGHT[26]; - _zz_118[6] = memory_SHIFT_RIGHT[25]; - _zz_118[7] = memory_SHIFT_RIGHT[24]; - _zz_118[8] = memory_SHIFT_RIGHT[23]; - _zz_118[9] = memory_SHIFT_RIGHT[22]; - _zz_118[10] = memory_SHIFT_RIGHT[21]; - _zz_118[11] = memory_SHIFT_RIGHT[20]; - _zz_118[12] = memory_SHIFT_RIGHT[19]; - _zz_118[13] = memory_SHIFT_RIGHT[18]; - _zz_118[14] = memory_SHIFT_RIGHT[17]; - _zz_118[15] = memory_SHIFT_RIGHT[16]; - _zz_118[16] = memory_SHIFT_RIGHT[15]; - _zz_118[17] = memory_SHIFT_RIGHT[14]; - _zz_118[18] = memory_SHIFT_RIGHT[13]; - _zz_118[19] = memory_SHIFT_RIGHT[12]; - _zz_118[20] = memory_SHIFT_RIGHT[11]; - _zz_118[21] = memory_SHIFT_RIGHT[10]; - _zz_118[22] = memory_SHIFT_RIGHT[9]; - _zz_118[23] = memory_SHIFT_RIGHT[8]; - _zz_118[24] = memory_SHIFT_RIGHT[7]; - _zz_118[25] = memory_SHIFT_RIGHT[6]; - _zz_118[26] = memory_SHIFT_RIGHT[5]; - _zz_118[27] = memory_SHIFT_RIGHT[4]; - _zz_118[28] = memory_SHIFT_RIGHT[3]; - _zz_118[29] = memory_SHIFT_RIGHT[2]; - _zz_118[30] = memory_SHIFT_RIGHT[1]; - _zz_118[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_119 = 1'b0; - if(_zz_245)begin - if(_zz_246)begin - if(_zz_124)begin - _zz_119 = 1'b1; + _zz_115[0] = execute_SRC1[31]; + _zz_115[1] = execute_SRC1[30]; + _zz_115[2] = execute_SRC1[29]; + _zz_115[3] = execute_SRC1[28]; + _zz_115[4] = execute_SRC1[27]; + _zz_115[5] = execute_SRC1[26]; + _zz_115[6] = execute_SRC1[25]; + _zz_115[7] = execute_SRC1[24]; + _zz_115[8] = execute_SRC1[23]; + _zz_115[9] = execute_SRC1[22]; + _zz_115[10] = execute_SRC1[21]; + _zz_115[11] = execute_SRC1[20]; + _zz_115[12] = execute_SRC1[19]; + _zz_115[13] = execute_SRC1[18]; + _zz_115[14] = execute_SRC1[17]; + _zz_115[15] = execute_SRC1[16]; + _zz_115[16] = execute_SRC1[15]; + _zz_115[17] = execute_SRC1[14]; + _zz_115[18] = execute_SRC1[13]; + _zz_115[19] = execute_SRC1[12]; + _zz_115[20] = execute_SRC1[11]; + _zz_115[21] = execute_SRC1[10]; + _zz_115[22] = execute_SRC1[9]; + _zz_115[23] = execute_SRC1[8]; + _zz_115[24] = execute_SRC1[7]; + _zz_115[25] = execute_SRC1[6]; + _zz_115[26] = execute_SRC1[5]; + _zz_115[27] = execute_SRC1[4]; + _zz_115[28] = execute_SRC1[3]; + _zz_115[29] = execute_SRC1[2]; + _zz_115[30] = execute_SRC1[1]; + _zz_115[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_115 : execute_SRC1); + always @ (*) begin + _zz_116[0] = memory_SHIFT_RIGHT[31]; + _zz_116[1] = memory_SHIFT_RIGHT[30]; + _zz_116[2] = memory_SHIFT_RIGHT[29]; + _zz_116[3] = memory_SHIFT_RIGHT[28]; + _zz_116[4] = memory_SHIFT_RIGHT[27]; + _zz_116[5] = memory_SHIFT_RIGHT[26]; + _zz_116[6] = memory_SHIFT_RIGHT[25]; + _zz_116[7] = memory_SHIFT_RIGHT[24]; + _zz_116[8] = memory_SHIFT_RIGHT[23]; + _zz_116[9] = memory_SHIFT_RIGHT[22]; + _zz_116[10] = memory_SHIFT_RIGHT[21]; + _zz_116[11] = memory_SHIFT_RIGHT[20]; + _zz_116[12] = memory_SHIFT_RIGHT[19]; + _zz_116[13] = memory_SHIFT_RIGHT[18]; + _zz_116[14] = memory_SHIFT_RIGHT[17]; + _zz_116[15] = memory_SHIFT_RIGHT[16]; + _zz_116[16] = memory_SHIFT_RIGHT[15]; + _zz_116[17] = memory_SHIFT_RIGHT[14]; + _zz_116[18] = memory_SHIFT_RIGHT[13]; + _zz_116[19] = memory_SHIFT_RIGHT[12]; + _zz_116[20] = memory_SHIFT_RIGHT[11]; + _zz_116[21] = memory_SHIFT_RIGHT[10]; + _zz_116[22] = memory_SHIFT_RIGHT[9]; + _zz_116[23] = memory_SHIFT_RIGHT[8]; + _zz_116[24] = memory_SHIFT_RIGHT[7]; + _zz_116[25] = memory_SHIFT_RIGHT[6]; + _zz_116[26] = memory_SHIFT_RIGHT[5]; + _zz_116[27] = memory_SHIFT_RIGHT[4]; + _zz_116[28] = memory_SHIFT_RIGHT[3]; + _zz_116[29] = memory_SHIFT_RIGHT[2]; + _zz_116[30] = memory_SHIFT_RIGHT[1]; + _zz_116[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_117 = 1'b0; + if(_zz_241)begin + if(_zz_242)begin + if(_zz_122)begin + _zz_117 = 1'b1; end end end - if(_zz_247)begin - if(_zz_248)begin - if(_zz_126)begin - _zz_119 = 1'b1; + if(_zz_243)begin + if(_zz_244)begin + if(_zz_124)begin + _zz_117 = 1'b1; end end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_128)begin - _zz_119 = 1'b1; + if(_zz_245)begin + if(_zz_246)begin + if(_zz_126)begin + _zz_117 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_119 = 1'b0; + _zz_117 = 1'b0; end end always @ (*) begin - _zz_120 = 1'b0; - if(_zz_245)begin - if(_zz_246)begin - if(_zz_125)begin - _zz_120 = 1'b1; + _zz_118 = 1'b0; + if(_zz_241)begin + if(_zz_242)begin + if(_zz_123)begin + _zz_118 = 1'b1; end end end - if(_zz_247)begin - if(_zz_248)begin - if(_zz_127)begin - _zz_120 = 1'b1; + if(_zz_243)begin + if(_zz_244)begin + if(_zz_125)begin + _zz_118 = 1'b1; end end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_129)begin - _zz_120 = 1'b1; + if(_zz_245)begin + if(_zz_246)begin + if(_zz_127)begin + _zz_118 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_120 = 1'b0; + _zz_118 = 1'b0; end end - assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_125 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_127 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_129 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_130 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_130 == 3'b000)) begin - _zz_131 = execute_BranchPlugin_eq; - end else if((_zz_130 == 3'b001)) begin - _zz_131 = (! execute_BranchPlugin_eq); - end else if((((_zz_130 & 3'b101) == 3'b101))) begin - _zz_131 = (! execute_SRC_LESS); + assign _zz_128 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_128 == 3'b000)) begin + _zz_129 = execute_BranchPlugin_eq; + end else if((_zz_128 == 3'b001)) begin + _zz_129 = (! execute_BranchPlugin_eq); + end else if((((_zz_128 & 3'b101) == 3'b101))) begin + _zz_129 = (! execute_SRC_LESS); end else begin - _zz_131 = execute_SRC_LESS; + _zz_129 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_132 = 1'b0; + _zz_130 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_132 = 1'b1; + _zz_130 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_132 = 1'b1; + _zz_130 = 1'b1; end default : begin - _zz_132 = _zz_131; + _zz_130 = _zz_129; end endcase end - assign _zz_133 = _zz_320[11]; + assign _zz_131 = _zz_318[11]; + always @ (*) begin + _zz_132[19] = _zz_131; + _zz_132[18] = _zz_131; + _zz_132[17] = _zz_131; + _zz_132[16] = _zz_131; + _zz_132[15] = _zz_131; + _zz_132[14] = _zz_131; + _zz_132[13] = _zz_131; + _zz_132[12] = _zz_131; + _zz_132[11] = _zz_131; + _zz_132[10] = _zz_131; + _zz_132[9] = _zz_131; + _zz_132[8] = _zz_131; + _zz_132[7] = _zz_131; + _zz_132[6] = _zz_131; + _zz_132[5] = _zz_131; + _zz_132[4] = _zz_131; + _zz_132[3] = _zz_131; + _zz_132[2] = _zz_131; + _zz_132[1] = _zz_131; + _zz_132[0] = _zz_131; + end + + assign _zz_133 = _zz_319[19]; always @ (*) begin - _zz_134[19] = _zz_133; - _zz_134[18] = _zz_133; - _zz_134[17] = _zz_133; - _zz_134[16] = _zz_133; - _zz_134[15] = _zz_133; - _zz_134[14] = _zz_133; - _zz_134[13] = _zz_133; - _zz_134[12] = _zz_133; - _zz_134[11] = _zz_133; _zz_134[10] = _zz_133; _zz_134[9] = _zz_133; _zz_134[8] = _zz_133; @@ -3896,8 +3967,16 @@ module VexRiscv ( _zz_134[0] = _zz_133; end - assign _zz_135 = _zz_321[19]; + assign _zz_135 = _zz_320[11]; always @ (*) begin + _zz_136[18] = _zz_135; + _zz_136[17] = _zz_135; + _zz_136[16] = _zz_135; + _zz_136[15] = _zz_135; + _zz_136[14] = _zz_135; + _zz_136[13] = _zz_135; + _zz_136[12] = _zz_135; + _zz_136[11] = _zz_135; _zz_136[10] = _zz_135; _zz_136[9] = _zz_135; _zz_136[8] = _zz_135; @@ -3911,44 +3990,21 @@ module VexRiscv ( _zz_136[0] = _zz_135; end - assign _zz_137 = _zz_322[11]; - always @ (*) begin - _zz_138[18] = _zz_137; - _zz_138[17] = _zz_137; - _zz_138[16] = _zz_137; - _zz_138[15] = _zz_137; - _zz_138[14] = _zz_137; - _zz_138[13] = _zz_137; - _zz_138[12] = _zz_137; - _zz_138[11] = _zz_137; - _zz_138[10] = _zz_137; - _zz_138[9] = _zz_137; - _zz_138[8] = _zz_137; - _zz_138[7] = _zz_137; - _zz_138[6] = _zz_137; - _zz_138[5] = _zz_137; - _zz_138[4] = _zz_137; - _zz_138[3] = _zz_137; - _zz_138[2] = _zz_137; - _zz_138[1] = _zz_137; - _zz_138[0] = _zz_137; - end - always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_139 = (_zz_323[1] ^ execute_RS1[1]); + _zz_137 = (_zz_321[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_139 = _zz_324[1]; + _zz_137 = _zz_322[1]; end default : begin - _zz_139 = _zz_325[1]; + _zz_137 = _zz_323[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_139); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_137); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -3960,50 +4016,73 @@ module VexRiscv ( endcase end - assign _zz_140 = _zz_326[11]; + assign _zz_138 = _zz_324[11]; always @ (*) begin - _zz_141[19] = _zz_140; - _zz_141[18] = _zz_140; - _zz_141[17] = _zz_140; - _zz_141[16] = _zz_140; - _zz_141[15] = _zz_140; - _zz_141[14] = _zz_140; - _zz_141[13] = _zz_140; - _zz_141[12] = _zz_140; - _zz_141[11] = _zz_140; - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; + _zz_139[19] = _zz_138; + _zz_139[18] = _zz_138; + _zz_139[17] = _zz_138; + _zz_139[16] = _zz_138; + _zz_139[15] = _zz_138; + _zz_139[14] = _zz_138; + _zz_139[13] = _zz_138; + _zz_139[12] = _zz_138; + _zz_139[11] = _zz_138; + _zz_139[10] = _zz_138; + _zz_139[9] = _zz_138; + _zz_139[8] = _zz_138; + _zz_139[7] = _zz_138; + _zz_139[6] = _zz_138; + _zz_139[5] = _zz_138; + _zz_139[4] = _zz_138; + _zz_139[3] = _zz_138; + _zz_139[2] = _zz_138; + _zz_139[1] = _zz_138; + _zz_139[0] = _zz_138; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_141,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_143,{{{_zz_556,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_145,{{{_zz_557,_zz_558},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_553,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_554,_zz_555},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_329}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_327}; end end endcase end - assign _zz_142 = _zz_327[19]; + assign _zz_140 = _zz_325[19]; always @ (*) begin - _zz_143[10] = _zz_142; - _zz_143[9] = _zz_142; - _zz_143[8] = _zz_142; - _zz_143[7] = _zz_142; + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; + end + + assign _zz_142 = _zz_326[11]; + always @ (*) begin + _zz_143[18] = _zz_142; + _zz_143[17] = _zz_142; + _zz_143[16] = _zz_142; + _zz_143[15] = _zz_142; + _zz_143[14] = _zz_142; + _zz_143[13] = _zz_142; + _zz_143[12] = _zz_142; + _zz_143[11] = _zz_142; + _zz_143[10] = _zz_142; + _zz_143[9] = _zz_142; + _zz_143[8] = _zz_142; + _zz_143[7] = _zz_142; _zz_143[6] = _zz_142; _zz_143[5] = _zz_142; _zz_143[4] = _zz_142; @@ -4013,29 +4092,6 @@ module VexRiscv ( _zz_143[0] = _zz_142; end - assign _zz_144 = _zz_328[11]; - always @ (*) begin - _zz_145[18] = _zz_144; - _zz_145[17] = _zz_144; - _zz_145[16] = _zz_144; - _zz_145[15] = _zz_144; - _zz_145[14] = _zz_144; - _zz_145[13] = _zz_144; - _zz_145[12] = _zz_144; - _zz_145[11] = _zz_144; - _zz_145[10] = _zz_144; - _zz_145[9] = _zz_144; - _zz_145[8] = _zz_144; - _zz_145[7] = _zz_144; - _zz_145[6] = _zz_144; - _zz_145[5] = _zz_144; - _zz_145[4] = _zz_144; - _zz_145[3] = _zz_144; - _zz_145[2] = _zz_144; - _zz_145[1] = _zz_144; - _zz_145[0] = _zz_144; - end - assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; @@ -4056,20 +4112,18 @@ module VexRiscv ( end end - assign _zz_146 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_147 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_148 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_144 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_145 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_146 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_149 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_148 = _zz_328[0]; + assign _zz_149 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; assign _zz_150 = _zz_330[0]; - assign _zz_151 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_152 = _zz_332[0]; - assign _zz_153 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_154 = _zz_334[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_236)begin + if(_zz_234)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4079,7 +4133,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_238)begin + if(_zz_236)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -4089,7 +4143,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_239)begin + if(CfuPlugin_joinException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4099,6 +4153,9 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end if(writeBack_arbitration_isFlushed)begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end @@ -4161,6 +4218,11 @@ module VexRiscv ( assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end if(execute_CsrPlugin_csr_3857)begin if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; @@ -4240,70 +4302,6 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2822)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2824)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2826)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2828)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2830)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2832)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2834)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end if(execute_CsrPlugin_csr_3008)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4312,7 +4310,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_251)begin + if(_zz_247)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4331,20 +4329,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_252)begin + if(_zz_248)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_253)begin + if(_zz_249)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_252)begin + if(_zz_248)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_253)begin + if(_zz_249)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4359,14 +4357,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_251)begin + if(_zz_247)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_251)begin + if(_zz_247)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4375,7 +4373,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_265) + case(_zz_261) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4388,49 +4386,49 @@ module VexRiscv ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_336; + assign execute_CfuPlugin_functionsIds_0 = _zz_332; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_171 = _zz_337[7]; - always @ (*) begin - _zz_172[23] = _zz_171; - _zz_172[22] = _zz_171; - _zz_172[21] = _zz_171; - _zz_172[20] = _zz_171; - _zz_172[19] = _zz_171; - _zz_172[18] = _zz_171; - _zz_172[17] = _zz_171; - _zz_172[16] = _zz_171; - _zz_172[15] = _zz_171; - _zz_172[14] = _zz_171; - _zz_172[13] = _zz_171; - _zz_172[12] = _zz_171; - _zz_172[11] = _zz_171; - _zz_172[10] = _zz_171; - _zz_172[9] = _zz_171; - _zz_172[8] = _zz_171; - _zz_172[7] = _zz_171; - _zz_172[6] = _zz_171; - _zz_172[5] = _zz_171; - _zz_172[4] = _zz_171; - _zz_172[3] = _zz_171; - _zz_172[2] = _zz_171; - _zz_172[1] = _zz_171; - _zz_172[0] = _zz_171; + assign _zz_151 = _zz_333[7]; + always @ (*) begin + _zz_152[23] = _zz_151; + _zz_152[22] = _zz_151; + _zz_152[21] = _zz_151; + _zz_152[20] = _zz_151; + _zz_152[19] = _zz_151; + _zz_152[18] = _zz_151; + _zz_152[17] = _zz_151; + _zz_152[16] = _zz_151; + _zz_152[15] = _zz_151; + _zz_152[14] = _zz_151; + _zz_152[13] = _zz_151; + _zz_152[12] = _zz_151; + _zz_152[11] = _zz_151; + _zz_152[10] = _zz_151; + _zz_152[9] = _zz_151; + _zz_152[8] = _zz_151; + _zz_152[7] = _zz_151; + _zz_152[6] = _zz_151; + _zz_152[5] = _zz_151; + _zz_152[4] = _zz_151; + _zz_152[3] = _zz_151; + _zz_152[2] = _zz_151; + _zz_152[1] = _zz_151; + _zz_152[0] = _zz_151; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_173 = execute_RS2; + _zz_153 = execute_RS2; end default : begin - _zz_173 = {_zz_172,execute_INSTRUCTION[31 : 24]}; + _zz_153 = {_zz_152,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_173; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_153; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4456,7 +4454,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_254) + case(_zz_250) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4470,7 +4468,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_254) + case(_zz_250) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4489,12 +4487,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_338) + $signed(_zz_339)); + assign writeBack_MulPlugin_result = ($signed(_zz_334) + $signed(_zz_335)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_231)begin - if(_zz_255)begin + if(_zz_229)begin + if(_zz_251)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4502,7 +4500,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_256)begin + if(_zz_252)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4513,28 +4511,28 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_343); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_339); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_174 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_174[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_344); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_345 : _zz_346); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_347[31:0]; - assign _zz_175 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_176 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_177 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_154 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_154[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_340); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_341 : _zz_342); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_343[31:0]; + assign _zz_155 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_156 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_157 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_178[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_178[31 : 0] = execute_RS1; + _zz_158[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_158[31 : 0] = execute_RS1; end - assign _zz_180 = (_zz_179 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_180 != 32'h0); + assign _zz_160 = (_zz_159 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_160 != 32'h0); assign _zz_29 = decode_SRC1_CTRL; assign _zz_27 = _zz_56; assign _zz_43 = decode_to_execute_SRC1_CTRL; @@ -4586,304 +4584,239 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_181 = 32'h0; + _zz_161 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_161[12 : 0] = 13'h1000; + _zz_161[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_162 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_181[3 : 0] = 4'b1011; + _zz_162[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_163 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_182[4 : 0] = 5'h16; + _zz_163[4 : 0] = 5'h16; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_164 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_183[5 : 0] = 6'h21; + _zz_164[5 : 0] = 6'h21; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_165 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_184[31 : 30] = CsrPlugin_misa_base; - _zz_184[25 : 0] = CsrPlugin_misa_extensions; + _zz_165[31 : 30] = CsrPlugin_misa_base; + _zz_165[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_166 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_166[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_166[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_166[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_167 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_186[11 : 11] = CsrPlugin_mip_MEIP; - _zz_186[7 : 7] = CsrPlugin_mip_MTIP; - _zz_186[3 : 3] = CsrPlugin_mip_MSIP; + _zz_167[11 : 11] = CsrPlugin_mip_MEIP; + _zz_167[7 : 7] = CsrPlugin_mip_MTIP; + _zz_167[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_168 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_187[11 : 11] = CsrPlugin_mie_MEIE; - _zz_187[7 : 7] = CsrPlugin_mie_MTIE; - _zz_187[3 : 3] = CsrPlugin_mie_MSIE; + _zz_168[11 : 11] = CsrPlugin_mie_MEIE; + _zz_168[7 : 7] = CsrPlugin_mie_MTIE; + _zz_168[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_169 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_188[31 : 2] = CsrPlugin_mtvec_base; - _zz_188[1 : 0] = CsrPlugin_mtvec_mode; + _zz_169[31 : 2] = CsrPlugin_mtvec_base; + _zz_169[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_170 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_189[31 : 0] = CsrPlugin_mepc; + _zz_170[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_171 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_190[31 : 0] = CsrPlugin_mscratch; + _zz_171[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_172[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_172[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_192[31 : 0] = CsrPlugin_mtval; + _zz_173[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_174[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_175[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_176[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_177[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_178[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_179[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_180[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; - end - end - - always @ (*) begin - _zz_201 = 32'h0; - if(execute_CsrPlugin_csr_2820)begin - _zz_201[31 : 0] = _zz_155; - end - end - - always @ (*) begin - _zz_202 = 32'h0; - if(execute_CsrPlugin_csr_2822)begin - _zz_202[31 : 0] = _zz_157; - end - end - - always @ (*) begin - _zz_203 = 32'h0; - if(execute_CsrPlugin_csr_2824)begin - _zz_203[31 : 0] = _zz_159; - end - end - - always @ (*) begin - _zz_204 = 32'h0; - if(execute_CsrPlugin_csr_2826)begin - _zz_204[31 : 0] = _zz_161; - end - end - - always @ (*) begin - _zz_205 = 32'h0; - if(execute_CsrPlugin_csr_2828)begin - _zz_205[31 : 0] = _zz_163; - end - end - - always @ (*) begin - _zz_206 = 32'h0; - if(execute_CsrPlugin_csr_2830)begin - _zz_206[31 : 0] = _zz_165; - end - end - - always @ (*) begin - _zz_207 = 32'h0; - if(execute_CsrPlugin_csr_2832)begin - _zz_207[31 : 0] = _zz_167; + _zz_181[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_208 = 32'h0; - if(execute_CsrPlugin_csr_2834)begin - _zz_208[31 : 0] = _zz_169; - end - end - - always @ (*) begin - _zz_209 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_209[31 : 0] = _zz_179; + _zz_182[31 : 0] = _zz_159; end end always @ (*) begin - _zz_210 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_210[31 : 0] = _zz_180; + _zz_183[31 : 0] = _zz_160; end end - assign execute_CsrPlugin_readData = (((((_zz_181 | _zz_182) | (_zz_183 | _zz_559)) | ((_zz_184 | _zz_185) | (_zz_186 | _zz_187))) | (((_zz_188 | _zz_189) | (_zz_190 | _zz_191)) | ((_zz_192 | _zz_193) | (_zz_194 | _zz_195)))) | ((((_zz_196 | _zz_197) | (_zz_198 | _zz_199)) | ((_zz_200 | _zz_201) | (_zz_202 | _zz_203))) | (((_zz_204 | _zz_205) | (_zz_206 | _zz_207)) | ((_zz_208 | _zz_209) | _zz_210)))); - assign iBusWishbone_ADR = {_zz_364,_zz_211}; - assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_161 | _zz_162) | (_zz_163 | _zz_164)) | ((_zz_556 | _zz_165) | (_zz_166 | _zz_167))) | (((_zz_168 | _zz_169) | (_zz_170 | _zz_171)) | ((_zz_172 | _zz_173) | (_zz_174 | _zz_175)))) | (((_zz_176 | _zz_177) | (_zz_178 | _zz_179)) | ((_zz_180 | _zz_181) | (_zz_182 | _zz_183)))); + assign iBusWishbone_ADR = {_zz_360,_zz_184}; + assign iBusWishbone_CTI = ((_zz_184 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_257)begin + if(_zz_253)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_257)begin + if(_zz_253)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_212; + assign iBus_rsp_valid = _zz_185; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; - assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; - assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; - assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; - assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; - assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; - assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); - assign dBusWishbone_CTI = 3'b000; + assign _zz_191 = (dBus_cmd_payload_length != 3'b000); + assign _zz_187 = dBus_cmd_valid; + assign _zz_189 = dBus_cmd_payload_wr; + assign _zz_190 = (_zz_186 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_188 && (_zz_189 || _zz_190)); + assign dBusWishbone_ADR = ((_zz_191 ? {{dBus_cmd_payload_address[31 : 5],_zz_186},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_191 ? (_zz_190 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - always @ (*) begin - case(dBus_cmd_halfPipe_payload_size) - 2'b00 : begin - _zz_213 = 4'b0001; - end - 2'b01 : begin - _zz_213 = 4'b0011; - end - default : begin - _zz_213 = 4'b1111; - end - endcase - end - - always @ (*) begin - dBusWishbone_SEL = (_zz_213 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - if((! dBus_cmd_halfPipe_payload_wr))begin - dBusWishbone_SEL = 4'b1111; - end - end - - assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; - assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; - assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); - assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; - assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; - assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); - assign dBus_rsp_data = dBusWishbone_DAT_MISO; - assign dBus_rsp_error = 1'b0; + assign dBusWishbone_SEL = (_zz_189 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_189; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_188 = (_zz_187 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_187; + assign dBusWishbone_STB = _zz_187; + assign dBus_rsp_valid = _zz_192; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_72 <= 1'b0; - _zz_74 <= 1'b0; + _zz_71 <= 1'b0; + _zz_73 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_87; + IBusCachedPlugin_rspCounter <= _zz_86; IBusCachedPlugin_rspCounter <= 32'h0; - _zz_109 <= 1'b1; - _zz_121 <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_87; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_107 <= 1'b1; + _zz_119 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4907,15 +4840,15 @@ module VexRiscv ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_179 <= 32'h0; + _zz_159 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_211 <= 3'b000; - _zz_212 <= 1'b0; - dBus_cmd_halfPipe_regs_valid <= 1'b0; - dBus_cmd_halfPipe_regs_ready <= 1'b1; + _zz_184 <= 3'b000; + _zz_185 <= 1'b0; + _zz_186 <= 3'b000; + _zz_192 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -4937,16 +4870,16 @@ module VexRiscv ( IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_72 <= 1'b0; + _zz_71 <= 1'b0; end - if(_zz_70)begin - _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_69)begin + _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_74 <= 1'b0; + _zz_73 <= 1'b0; end if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_74 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + _zz_73 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end if(IBusCachedPlugin_fetchPc_flushed)begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; @@ -4993,28 +4926,20 @@ module VexRiscv ( if(iBus_rsp_valid)begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); - `else - if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin - $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); - $finish; - end - `endif - `endif - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); - `else - if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin - $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); - $finish; - end - `endif - `endif - _zz_109 <= 1'b0; - _zz_121 <= (_zz_47 && writeBack_arbitration_isFiring); + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(_zz_254)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_107 <= 1'b0; + _zz_119 <= (_zz_47 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5036,14 +4961,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_258)begin - if(_zz_259)begin + if(_zz_255)begin + if(_zz_256)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_260)begin + if(_zz_257)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_261)begin + if(_zz_258)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5068,7 +4993,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_240)begin + if(_zz_237)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5079,8 +5004,8 @@ module VexRiscv ( end endcase end - if(_zz_241)begin - case(_zz_242) + if(_zz_238)begin + case(_zz_239) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5090,7 +5015,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_148,{_zz_147,_zz_146}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_146,{_zz_145,_zz_144}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -5106,7 +5031,7 @@ module VexRiscv ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_262)begin + if(_zz_259)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; @@ -5140,41 +5065,41 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_357[0]; - CsrPlugin_mstatus_MIE <= _zz_358[0]; + CsrPlugin_mstatus_MPIE <= _zz_353[0]; + CsrPlugin_mstatus_MIE <= _zz_354[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_360[0]; - CsrPlugin_mie_MTIE <= _zz_361[0]; - CsrPlugin_mie_MSIE <= _zz_362[0]; + CsrPlugin_mie_MEIE <= _zz_356[0]; + CsrPlugin_mie_MTIE <= _zz_357[0]; + CsrPlugin_mie_MSIE <= _zz_358[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_179 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_257)begin + if(_zz_253)begin if(iBusWishbone_ACK)begin - _zz_211 <= (_zz_211 + 3'b001); + _zz_184 <= (_zz_184 + 3'b001); end end - _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_263)begin - dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; - dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); - end else begin - dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); - dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + _zz_185 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_187 && _zz_188))begin + _zz_186 <= (_zz_186 + 3'b001); + if(_zz_190)begin + _zz_186 <= 3'b000; + end end + _zz_192 <= ((_zz_187 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end always @ (posedge clk) begin if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_75 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + _zz_74 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; @@ -5182,8 +5107,26 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - _zz_122 <= _zz_46[11 : 7]; - _zz_123 <= _zz_57; + if(_zz_254)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + _zz_120 <= _zz_46[11 : 7]; + _zz_121 <= _zz_57; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5191,33 +5134,37 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end + if(_zz_234)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end if(_zz_236)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(_zz_238)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_154 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_154 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; end - if(_zz_239)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_152 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_152 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_258)begin - if(_zz_259)begin + if(_zz_255)begin + if(_zz_256)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_260)begin + if(_zz_257)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_261)begin + if(_zz_258)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_240)begin + if(_zz_237)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5231,31 +5178,7 @@ module VexRiscv ( end endcase end - if(_zz_156[0])begin - _zz_155 <= (_zz_155 + 32'h00000001); - end - if(_zz_158[0])begin - _zz_157 <= (_zz_157 + 32'h00000001); - end - if(_zz_160[0])begin - _zz_159 <= (_zz_159 + 32'h00000001); - end - if(_zz_162[0])begin - _zz_161 <= (_zz_161 + 32'h00000001); - end - if(_zz_164[0])begin - _zz_163 <= (_zz_163 + 32'h00000001); - end - if(_zz_166[0])begin - _zz_165 <= (_zz_165 + 32'h00000001); - end - if(_zz_168[0])begin - _zz_167 <= (_zz_167 + 32'h00000001); - end - if(_zz_170[0])begin - _zz_169 <= (_zz_169 + 32'h00000001); - end - if(_zz_262)begin + if(_zz_259)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5265,20 +5188,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_231)begin - if(_zz_255)begin + if(_zz_229)begin + if(_zz_251)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_348[31:0]; + memory_DivPlugin_div_result <= _zz_344[31:0]; end end end - if(_zz_256)begin + if(_zz_252)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_177 ? (~ _zz_178) : _zz_178) + _zz_354); - memory_DivPlugin_rs2 <= ((_zz_176 ? (~ execute_RS2) : execute_RS2) + _zz_356); - memory_DivPlugin_div_needRevert <= ((_zz_177 ^ (_zz_176 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_157 ? (~ _zz_158) : _zz_158) + _zz_350); + memory_DivPlugin_rs2 <= ((_zz_156 ? (~ execute_RS2) : execute_RS2) + _zz_352); + memory_DivPlugin_div_needRevert <= ((_zz_157 ^ (_zz_156 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5300,13 +5223,16 @@ module VexRiscv ( memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_61; + decode_to_execute_FORMAL_PC_NEXT <= _zz_60; end if((! memory_arbitration_isStuck))begin execute_to_memory_FORMAL_PC_NEXT <= _zz_59; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_60; + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC1_CTRL <= _zz_28; @@ -5348,13 +5274,16 @@ module VexRiscv ( execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; @@ -5428,29 +5357,12 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; - end if((! memory_arbitration_isStuck))begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; - execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; - execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; - execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; - execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; - execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; - execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; - execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; - execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; - end if((! memory_arbitration_isStuck))begin execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; end @@ -5478,12 +5390,12 @@ module VexRiscv ( if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; - end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end @@ -5547,54 +5459,6 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); - end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end @@ -5603,7 +5467,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_359[0]; + CsrPlugin_mip_MSIP <= _zz_355[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5624,7 +5488,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_363[0]; + CsrPlugin_mcause_interrupt <= _zz_359[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5653,92 +5517,808 @@ module VexRiscv ( CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end end - if(execute_CsrPlugin_csr_2820)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; - end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; - end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; end - if(execute_CsrPlugin_csr_2822)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; - end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; - end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end - if(execute_CsrPlugin_csr_2824)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; - end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; end end - if(execute_CsrPlugin_csr_2826)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end end end - if(execute_CsrPlugin_csr_2828)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + if(_zz_13)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end end end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end end end - if(execute_CsrPlugin_csr_2830)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end end end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end end end - if(execute_CsrPlugin_csr_2832)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end end end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end end end - if(execute_CsrPlugin_csr_2834)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_169 <= execute_CsrPlugin_writeData[31 : 0]; + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end end end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_170 <= execute_CsrPlugin_writeData[31 : 0]; + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end end end - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_263)begin - dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; - dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; - dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; - dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; + end end end @@ -5788,12 +6368,12 @@ module InstructionCache ( input reset ); reg [31:0] _zz_9; - reg [23:0] _zz_10; + reg [22:0] _zz_10; wire _zz_11; wire _zz_12; wire [0:0] _zz_13; wire [0:0] _zz_14; - wire [23:0] _zz_15; + wire [22:0] _zz_15; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -5801,7 +6381,7 @@ module InstructionCache ( (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; - reg [5:0] lineLoader_flushCounter; + reg [6:0] lineLoader_flushCounter; reg _zz_3; reg lineLoader_cmdSent; reg lineLoader_wayToAllocate_willIncrement; @@ -5810,23 +6390,23 @@ module InstructionCache ( wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; wire lineLoader_write_tag_0_valid; - wire [4:0] lineLoader_write_tag_0_payload_address; + wire [5:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [21:0] lineLoader_write_tag_0_payload_data_address; + wire [20:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [7:0] lineLoader_write_data_0_payload_address; + wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [7:0] _zz_4; + wire [8:0] _zz_4; wire _zz_5; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [4:0] _zz_6; + wire [5:0] _zz_6; wire _zz_7; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [21:0] fetchStage_read_waysValues_0_tag_address; - wire [23:0] _zz_8; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_8; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; @@ -5844,10 +6424,10 @@ module InstructionCache ( reg decodeStage_mmuRsp_bypassTranslation; reg decodeStage_hit_valid; reg decodeStage_hit_error; - (* ram_style = "block" *) reg [31:0] banks_0 [0:255]; - (* ram_style = "block" *) reg [23:0] ways_0_tags [0:31]; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_11 = (! lineLoader_flushCounter[5]); + assign _zz_11 = (! lineLoader_flushCounter[6]); assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); assign _zz_13 = _zz_8[0 : 0]; assign _zz_14 = _zz_8[1 : 1]; @@ -5925,25 +6505,25 @@ module InstructionCache ( assign lineLoader_wayToAllocate_willClear = 1'b0; assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[5])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[9 : 2]; + assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; assign _zz_5 = (! io_cpu_fetch_isStuck); assign fetchStage_read_banksValue_0_dataMem = _zz_9; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[9 : 5]; + assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; assign _zz_7 = (! io_cpu_fetch_isStuck); assign _zz_8 = _zz_10; assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[23 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 10])); + assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; @@ -5999,11 +6579,11 @@ module InstructionCache ( lineLoader_address <= io_cpu_fill_payload; end if(_zz_11)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 6'h01); + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[5]; + _zz_3 <= lineLoader_flushCounter[6]; if(_zz_12)begin - lineLoader_flushCounter <= 6'h0; + lineLoader_flushCounter <= 7'h0; end if((! io_cpu_decode_isStuck))begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml index 6a862d2..b55f8e5 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.yaml @@ -1,4 +1,4 @@ iBus: !!vexriscv.BusReport flushInstructions: [4111, 19, 19, 19] - info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024} + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v index 65db630..d02aef8 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 +// Git hash : e1ac7eb3083970f73e62f222f2f3e8520116f2e8 `define Input2Kind_defaultEncoding_type [0:0] @@ -87,7 +87,7 @@ module VexRiscv ( output [29:0] dBusWishbone_ADR, input [31:0] dBusWishbone_DAT_MISO, output [31:0] dBusWishbone_DAT_MOSI, - output reg [3:0] dBusWishbone_SEL, + output [3:0] dBusWishbone_SEL, input dBusWishbone_ERR, output [2:0] dBusWishbone_CTI, output [1:0] dBusWishbone_BTE, @@ -95,18 +95,37 @@ module VexRiscv ( input reset, input debugReset ); + wire _zz_196; + wire _zz_197; + wire _zz_198; + wire _zz_199; + wire _zz_200; + wire _zz_201; + wire _zz_202; + wire _zz_203; + reg _zz_204; + wire _zz_205; + wire [31:0] _zz_206; + wire _zz_207; + wire [31:0] _zz_208; + reg _zz_209; + wire _zz_210; + wire _zz_211; + wire [31:0] _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; wire _zz_216; wire _zz_217; wire _zz_218; wire _zz_219; wire _zz_220; - wire _zz_221; + wire [3:0] _zz_221; wire _zz_222; wire _zz_223; - reg _zz_224; + reg [31:0] _zz_224; reg [31:0] _zz_225; reg [31:0] _zz_226; - reg [31:0] _zz_227; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -119,6 +138,27 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_227; wire _zz_228; wire _zz_229; wire _zz_230; @@ -136,9 +176,9 @@ module VexRiscv ( wire _zz_242; wire _zz_243; wire _zz_244; - wire _zz_245; + wire [1:0] _zz_245; wire _zz_246; - wire [1:0] _zz_247; + wire _zz_247; wire _zz_248; wire _zz_249; wire _zz_250; @@ -147,35 +187,35 @@ module VexRiscv ( wire _zz_253; wire _zz_254; wire _zz_255; - wire _zz_256; + wire [1:0] _zz_256; wire _zz_257; wire _zz_258; - wire [1:0] _zz_259; + wire [5:0] _zz_259; wire _zz_260; wire _zz_261; - wire [5:0] _zz_262; + wire _zz_262; wire _zz_263; wire _zz_264; wire _zz_265; wire _zz_266; - wire _zz_267; + wire [1:0] _zz_267; wire _zz_268; - wire _zz_269; - wire [1:0] _zz_270; - wire _zz_271; - wire [1:0] _zz_272; - wire [51:0] _zz_273; + wire [1:0] _zz_269; + wire [51:0] _zz_270; + wire [51:0] _zz_271; + wire [51:0] _zz_272; + wire [32:0] _zz_273; wire [51:0] _zz_274; - wire [51:0] _zz_275; - wire [32:0] _zz_276; - wire [51:0] _zz_277; - wire [49:0] _zz_278; - wire [51:0] _zz_279; - wire [49:0] _zz_280; - wire [51:0] _zz_281; - wire [32:0] _zz_282; - wire [31:0] _zz_283; - wire [32:0] _zz_284; + wire [49:0] _zz_275; + wire [51:0] _zz_276; + wire [49:0] _zz_277; + wire [51:0] _zz_278; + wire [32:0] _zz_279; + wire [31:0] _zz_280; + wire [32:0] _zz_281; + wire [0:0] _zz_282; + wire [0:0] _zz_283; + wire [0:0] _zz_284; wire [0:0] _zz_285; wire [0:0] _zz_286; wire [0:0] _zz_287; @@ -192,263 +232,263 @@ module VexRiscv ( wire [0:0] _zz_298; wire [0:0] _zz_299; wire [0:0] _zz_300; - wire [0:0] _zz_301; - wire [0:0] _zz_302; - wire [3:0] _zz_303; - wire [2:0] _zz_304; + wire [3:0] _zz_301; + wire [2:0] _zz_302; + wire [31:0] _zz_303; + wire [11:0] _zz_304; wire [31:0] _zz_305; - wire [11:0] _zz_306; - wire [31:0] _zz_307; - wire [19:0] _zz_308; - wire [11:0] _zz_309; - wire [31:0] _zz_310; - wire [31:0] _zz_311; - wire [19:0] _zz_312; - wire [11:0] _zz_313; - wire [2:0] _zz_314; - wire [0:0] _zz_315; - wire [2:0] _zz_316; - wire [4:0] _zz_317; + wire [19:0] _zz_306; + wire [11:0] _zz_307; + wire [31:0] _zz_308; + wire [31:0] _zz_309; + wire [19:0] _zz_310; + wire [11:0] _zz_311; + wire [2:0] _zz_312; + wire [2:0] _zz_313; + wire [0:0] _zz_314; + wire [2:0] _zz_315; + wire [4:0] _zz_316; + wire [11:0] _zz_317; wire [11:0] _zz_318; - wire [11:0] _zz_319; + wire [31:0] _zz_319; wire [31:0] _zz_320; wire [31:0] _zz_321; wire [31:0] _zz_322; wire [31:0] _zz_323; wire [31:0] _zz_324; wire [31:0] _zz_325; - wire [31:0] _zz_326; - wire [11:0] _zz_327; - wire [19:0] _zz_328; - wire [11:0] _zz_329; + wire [11:0] _zz_326; + wire [19:0] _zz_327; + wire [11:0] _zz_328; + wire [31:0] _zz_329; wire [31:0] _zz_330; wire [31:0] _zz_331; - wire [31:0] _zz_332; - wire [11:0] _zz_333; - wire [19:0] _zz_334; - wire [11:0] _zz_335; - wire [2:0] _zz_336; + wire [11:0] _zz_332; + wire [19:0] _zz_333; + wire [11:0] _zz_334; + wire [2:0] _zz_335; + wire [1:0] _zz_336; wire [1:0] _zz_337; wire [1:0] _zz_338; wire [1:0] _zz_339; - wire [1:0] _zz_340; - wire [1:0] _zz_341; - wire [1:0] _zz_342; - wire [9:0] _zz_343; - wire [7:0] _zz_344; - wire [65:0] _zz_345; - wire [65:0] _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; - wire [0:0] _zz_349; - wire [5:0] _zz_350; + wire [9:0] _zz_340; + wire [7:0] _zz_341; + wire [65:0] _zz_342; + wire [65:0] _zz_343; + wire [31:0] _zz_344; + wire [31:0] _zz_345; + wire [0:0] _zz_346; + wire [5:0] _zz_347; + wire [32:0] _zz_348; + wire [31:0] _zz_349; + wire [31:0] _zz_350; wire [32:0] _zz_351; - wire [31:0] _zz_352; - wire [31:0] _zz_353; + wire [32:0] _zz_352; + wire [32:0] _zz_353; wire [32:0] _zz_354; - wire [32:0] _zz_355; + wire [0:0] _zz_355; wire [32:0] _zz_356; - wire [32:0] _zz_357; - wire [0:0] _zz_358; - wire [32:0] _zz_359; - wire [0:0] _zz_360; - wire [32:0] _zz_361; + wire [0:0] _zz_357; + wire [32:0] _zz_358; + wire [0:0] _zz_359; + wire [31:0] _zz_360; + wire [0:0] _zz_361; wire [0:0] _zz_362; - wire [31:0] _zz_363; + wire [0:0] _zz_363; wire [0:0] _zz_364; wire [0:0] _zz_365; wire [0:0] _zz_366; wire [0:0] _zz_367; - wire [0:0] _zz_368; - wire [0:0] _zz_369; - wire [0:0] _zz_370; - wire [26:0] _zz_371; - wire _zz_372; - wire _zz_373; - wire [1:0] _zz_374; - wire [31:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire _zz_378; - wire [0:0] _zz_379; - wire [13:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire _zz_384; - wire [0:0] _zz_385; - wire [7:0] _zz_386; - wire [31:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; + wire [26:0] _zz_368; + wire _zz_369; + wire _zz_370; + wire [1:0] _zz_371; + wire [31:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; + wire _zz_375; + wire [0:0] _zz_376; + wire [14:0] _zz_377; + wire [31:0] _zz_378; + wire [31:0] _zz_379; + wire [31:0] _zz_380; + wire _zz_381; + wire [0:0] _zz_382; + wire [8:0] _zz_383; + wire [31:0] _zz_384; + wire [31:0] _zz_385; + wire [31:0] _zz_386; + wire _zz_387; + wire [0:0] _zz_388; + wire [2:0] _zz_389; wire _zz_390; - wire [0:0] _zz_391; - wire [1:0] _zz_392; - wire _zz_393; - wire _zz_394; - wire _zz_395; - wire [31:0] _zz_396; + wire _zz_391; + wire _zz_392; + wire [31:0] _zz_393; + wire [0:0] _zz_394; + wire [0:0] _zz_395; + wire _zz_396; wire [0:0] _zz_397; - wire [0:0] _zz_398; - wire _zz_399; + wire [28:0] _zz_398; + wire [0:0] _zz_399; wire [0:0] _zz_400; - wire [27:0] _zz_401; + wire [0:0] _zz_401; wire [0:0] _zz_402; - wire [0:0] _zz_403; + wire _zz_403; wire [0:0] _zz_404; - wire [0:0] _zz_405; - wire _zz_406; - wire [0:0] _zz_407; - wire [22:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire [31:0] _zz_411; - wire _zz_412; - wire _zz_413; + wire [23:0] _zz_405; + wire [31:0] _zz_406; + wire [31:0] _zz_407; + wire [31:0] _zz_408; + wire _zz_409; + wire _zz_410; + wire [0:0] _zz_411; + wire [0:0] _zz_412; + wire [0:0] _zz_413; wire [0:0] _zz_414; - wire [0:0] _zz_415; + wire _zz_415; wire [0:0] _zz_416; - wire [0:0] _zz_417; - wire _zz_418; - wire [0:0] _zz_419; - wire [19:0] _zz_420; - wire [31:0] _zz_421; - wire [31:0] _zz_422; - wire _zz_423; - wire _zz_424; + wire [20:0] _zz_417; + wire [31:0] _zz_418; + wire [31:0] _zz_419; + wire _zz_420; + wire _zz_421; + wire [0:0] _zz_422; + wire [1:0] _zz_423; + wire [0:0] _zz_424; wire [0:0] _zz_425; - wire [1:0] _zz_426; + wire _zz_426; wire [0:0] _zz_427; - wire [0:0] _zz_428; - wire _zz_429; - wire [0:0] _zz_430; - wire [16:0] _zz_431; + wire [17:0] _zz_428; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire [31:0] _zz_431; wire [31:0] _zz_432; wire [31:0] _zz_433; wire [31:0] _zz_434; wire [31:0] _zz_435; wire [31:0] _zz_436; - wire [31:0] _zz_437; - wire [31:0] _zz_438; - wire [31:0] _zz_439; + wire _zz_437; + wire [1:0] _zz_438; + wire [1:0] _zz_439; wire _zz_440; - wire [1:0] _zz_441; - wire [1:0] _zz_442; - wire _zz_443; - wire [0:0] _zz_444; - wire [13:0] _zz_445; + wire [0:0] _zz_441; + wire [14:0] _zz_442; + wire [31:0] _zz_443; + wire [31:0] _zz_444; + wire [31:0] _zz_445; wire [31:0] _zz_446; wire [31:0] _zz_447; wire [31:0] _zz_448; - wire [31:0] _zz_449; - wire [0:0] _zz_450; - wire [0:0] _zz_451; - wire [0:0] _zz_452; - wire [3:0] _zz_453; + wire [0:0] _zz_449; + wire [1:0] _zz_450; + wire [4:0] _zz_451; + wire [4:0] _zz_452; + wire _zz_453; wire [0:0] _zz_454; - wire [0:0] _zz_455; - wire _zz_456; - wire [0:0] _zz_457; - wire [10:0] _zz_458; + wire [11:0] _zz_455; + wire [31:0] _zz_456; + wire [31:0] _zz_457; + wire [31:0] _zz_458; wire [31:0] _zz_459; wire [31:0] _zz_460; wire [31:0] _zz_461; - wire [31:0] _zz_462; - wire [31:0] _zz_463; - wire _zz_464; - wire [0:0] _zz_465; - wire [0:0] _zz_466; - wire [31:0] _zz_467; - wire _zz_468; - wire [0:0] _zz_469; - wire [3:0] _zz_470; - wire [0:0] _zz_471; - wire [3:0] _zz_472; - wire [5:0] _zz_473; - wire [5:0] _zz_474; - wire _zz_475; - wire [0:0] _zz_476; - wire [7:0] _zz_477; - wire [31:0] _zz_478; + wire _zz_462; + wire [0:0] _zz_463; + wire [1:0] _zz_464; + wire [31:0] _zz_465; + wire [31:0] _zz_466; + wire [0:0] _zz_467; + wire [4:0] _zz_468; + wire [4:0] _zz_469; + wire [4:0] _zz_470; + wire _zz_471; + wire [0:0] _zz_472; + wire [8:0] _zz_473; + wire [31:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; + wire _zz_477; + wire _zz_478; wire [31:0] _zz_479; wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire [31:0] _zz_485; + wire _zz_481; + wire [0:0] _zz_482; + wire [2:0] _zz_483; + wire [0:0] _zz_484; + wire [2:0] _zz_485; wire [0:0] _zz_486; - wire [1:0] _zz_487; - wire _zz_488; - wire [0:0] _zz_489; - wire [1:0] _zz_490; + wire [4:0] _zz_487; + wire [1:0] _zz_488; + wire [1:0] _zz_489; + wire _zz_490; wire [0:0] _zz_491; - wire [3:0] _zz_492; - wire [0:0] _zz_493; - wire [0:0] _zz_494; - wire [1:0] _zz_495; - wire [1:0] _zz_496; - wire _zz_497; + wire [6:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire _zz_496; + wire [0:0] _zz_497; wire [0:0] _zz_498; - wire [5:0] _zz_499; + wire [31:0] _zz_499; wire [31:0] _zz_500; - wire [31:0] _zz_501; - wire _zz_502; - wire _zz_503; - wire [31:0] _zz_504; - wire [31:0] _zz_505; - wire [31:0] _zz_506; + wire _zz_501; + wire [0:0] _zz_502; + wire [0:0] _zz_503; + wire _zz_504; + wire [0:0] _zz_505; + wire [2:0] _zz_506; wire _zz_507; - wire _zz_508; - wire [31:0] _zz_509; - wire [31:0] _zz_510; - wire _zz_511; - wire [0:0] _zz_512; - wire [1:0] _zz_513; - wire [31:0] _zz_514; + wire [0:0] _zz_508; + wire [0:0] _zz_509; + wire [0:0] _zz_510; + wire [0:0] _zz_511; + wire _zz_512; + wire [0:0] _zz_513; + wire [4:0] _zz_514; wire [31:0] _zz_515; - wire _zz_516; - wire _zz_517; - wire [0:0] _zz_518; - wire [0:0] _zz_519; - wire _zz_520; - wire [0:0] _zz_521; - wire [3:0] _zz_522; + wire [31:0] _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire [31:0] _zz_520; + wire [31:0] _zz_521; + wire [31:0] _zz_522; wire [31:0] _zz_523; wire [31:0] _zz_524; wire [31:0] _zz_525; wire [31:0] _zz_526; wire [31:0] _zz_527; - wire [31:0] _zz_528; - wire [31:0] _zz_529; - wire _zz_530; - wire _zz_531; + wire _zz_528; + wire [0:0] _zz_529; + wire [0:0] _zz_530; + wire [31:0] _zz_531; wire [31:0] _zz_532; wire [31:0] _zz_533; wire [31:0] _zz_534; wire [31:0] _zz_535; - wire [0:0] _zz_536; - wire [2:0] _zz_537; - wire [0:0] _zz_538; - wire [0:0] _zz_539; - wire _zz_540; - wire [0:0] _zz_541; - wire [1:0] _zz_542; + wire _zz_536; + wire [3:0] _zz_537; + wire [3:0] _zz_538; + wire _zz_539; + wire [0:0] _zz_540; + wire [2:0] _zz_541; + wire [31:0] _zz_542; wire [31:0] _zz_543; wire [31:0] _zz_544; wire [31:0] _zz_545; - wire _zz_546; - wire _zz_547; - wire [31:0] _zz_548; - wire _zz_549; - wire [0:0] _zz_550; - wire [0:0] _zz_551; - wire [0:0] _zz_552; - wire [0:0] _zz_553; - wire [1:0] _zz_554; - wire [1:0] _zz_555; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire _zz_548; + wire [0:0] _zz_549; + wire [1:0] _zz_550; + wire _zz_551; + wire [2:0] _zz_552; + wire [2:0] _zz_553; + wire _zz_554; + wire [0:0] _zz_555; wire [0:0] _zz_556; - wire [0:0] _zz_557; + wire [31:0] _zz_557; wire [31:0] _zz_558; wire [31:0] _zz_559; wire [31:0] _zz_560; @@ -458,9 +498,14 @@ module VexRiscv ( wire _zz_564; wire _zz_565; wire _zz_566; - wire [31:0] _zz_567; + wire [0:0] _zz_567; + wire [0:0] _zz_568; + wire _zz_569; + wire _zz_570; + wire _zz_571; + wire _zz_572; + wire [31:0] _zz_573; wire [51:0] memory_MUL_LOW; - wire [31:0] memory_MEMORY_READ_DATA; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; @@ -469,7 +514,6 @@ module VexRiscv ( wire writeBack_CfuPlugin_CFU_IN_FLIGHT; wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; - wire [31:0] writeBack_REGFILE_WRITE_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; wire [1:0] memory_MEMORY_ADDRESS_LOW; wire [1:0] execute_MEMORY_ADDRESS_LOW; @@ -511,7 +555,9 @@ module VexRiscv ( wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; wire decode_SRC_LESS_UNSIGNED; - wire decode_MEMORY_STORE; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; @@ -527,10 +573,12 @@ module VexRiscv ( wire `Src1CtrlEnum_defaultEncoding_type _zz_27; wire `Src1CtrlEnum_defaultEncoding_type _zz_28; wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; wire execute_DO_EBREAK; wire decode_IS_EBREAK; wire execute_IS_RS1_SIGNED; @@ -615,42 +663,20 @@ module VexRiscv ( wire `Src2CtrlEnum_defaultEncoding_type _zz_54; wire `AluCtrlEnum_defaultEncoding_type _zz_55; wire `Src1CtrlEnum_defaultEncoding_type _zz_56; - wire writeBack_MEMORY_STORE; reg [31:0] _zz_57; - wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; - wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP2_physicalAddress; - wire memory_MMU_RSP2_isIoAccess; - wire memory_MMU_RSP2_isPaging; - wire memory_MMU_RSP2_allowRead; - wire memory_MMU_RSP2_allowWrite; - wire memory_MMU_RSP2_allowExecute; - wire memory_MMU_RSP2_exception; - wire memory_MMU_RSP2_refilling; - wire memory_MMU_RSP2_bypassTranslation; - wire [31:0] memory_PC; - wire memory_ALIGNEMENT_FAULT; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; - wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP2_physicalAddress; - wire execute_MMU_RSP2_isIoAccess; - wire execute_MMU_RSP2_isPaging; - wire execute_MMU_RSP2_allowRead; - wire execute_MMU_RSP2_allowWrite; - wire execute_MMU_RSP2_allowExecute; - wire execute_MMU_RSP2_exception; - wire execute_MMU_RSP2_refilling; - wire execute_MMU_RSP2_bypassTranslation; - wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; - wire [31:0] execute_INSTRUCTION; - wire execute_MEMORY_STORE; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; wire execute_MEMORY_ENABLE; - wire execute_ALIGNEMENT_FAULT; + wire [31:0] execute_INSTRUCTION; wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_4; @@ -662,7 +688,6 @@ module VexRiscv ( wire [31:0] decode_INSTRUCTION; reg [31:0] _zz_59; reg [31:0] _zz_60; - reg [31:0] _zz_61; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -691,7 +716,7 @@ module VexRiscv ( reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; + wire memory_arbitration_flushIt; reg memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; @@ -699,10 +724,10 @@ module VexRiscv ( wire memory_arbitration_isFlushed; wire memory_arbitration_isMoving; wire memory_arbitration_isFiring; - wire writeBack_arbitration_haltItself; + reg writeBack_arbitration_haltItself; wire writeBack_arbitration_haltByOther; reg writeBack_arbitration_removeIt; - wire writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushIt; reg writeBack_arbitration_flushNext; reg writeBack_arbitration_isValid; wire writeBack_arbitration_isStuck; @@ -742,26 +767,40 @@ module VexRiscv ( wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; wire IBusCachedPlugin_mmuBus_end; wire IBusCachedPlugin_mmuBus_busy; - reg DBusSimplePlugin_memoryExceptionPort_valid; - reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; - wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_0_isValid; - wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_isPaging; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_61; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -885,40 +924,64 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; - wire dBus_cmd_valid; - wire dBus_cmd_ready; - wire dBus_cmd_payload_wr; - wire [31:0] dBus_cmd_payload_address; - wire [31:0] dBus_cmd_payload_data; - wire [1:0] dBus_cmd_payload_size; - wire dBus_rsp_ready; - wire dBus_rsp_error; - wire [31:0] dBus_rsp_data; - wire _zz_88; - reg execute_DBusSimplePlugin_skipCmd; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_88; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; reg [31:0] _zz_89; - reg [3:0] _zz_90; - wire [3:0] execute_DBusSimplePlugin_formalMask; - reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_91; - reg [31:0] _zz_92; - wire _zz_93; - reg [31:0] _zz_94; - reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [33:0] _zz_95; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_90; + reg [31:0] _zz_91; + wire _zz_92; + reg [31:0] _zz_93; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [34:0] _zz_94; + wire _zz_95; wire _zz_96; wire _zz_97; wire _zz_98; wire _zz_99; - wire _zz_100; - wire `Src1CtrlEnum_defaultEncoding_type _zz_101; - wire `AluCtrlEnum_defaultEncoding_type _zz_102; - wire `Src2CtrlEnum_defaultEncoding_type _zz_103; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_104; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_105; - wire `BranchCtrlEnum_defaultEncoding_type _zz_106; - wire `EnvCtrlEnum_defaultEncoding_type _zz_107; - wire `Input2Kind_defaultEncoding_type _zz_108; + wire `Src1CtrlEnum_defaultEncoding_type _zz_100; + wire `AluCtrlEnum_defaultEncoding_type _zz_101; + wire `Src2CtrlEnum_defaultEncoding_type _zz_102; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; + wire `BranchCtrlEnum_defaultEncoding_type _zz_105; + wire `EnvCtrlEnum_defaultEncoding_type _zz_106; + wire `Input2Kind_defaultEncoding_type _zz_107; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -926,52 +989,52 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_109; + reg _zz_108; reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_109; reg [31:0] _zz_110; - reg [31:0] _zz_111; - wire _zz_112; - reg [19:0] _zz_113; - wire _zz_114; - reg [19:0] _zz_115; - reg [31:0] _zz_116; + wire _zz_111; + reg [19:0] _zz_112; + wire _zz_113; + reg [19:0] _zz_114; + reg [31:0] _zz_115; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_117; + reg [31:0] _zz_116; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_118; + reg [31:0] _zz_117; + reg _zz_118; reg _zz_119; reg _zz_120; - reg _zz_121; - reg [4:0] _zz_122; - reg [31:0] _zz_123; + reg [4:0] _zz_121; + reg [31:0] _zz_122; + wire _zz_123; wire _zz_124; wire _zz_125; wire _zz_126; wire _zz_127; wire _zz_128; - wire _zz_129; wire execute_BranchPlugin_eq; - wire [2:0] _zz_130; + wire [2:0] _zz_129; + reg _zz_130; reg _zz_131; - reg _zz_132; - wire _zz_133; - reg [19:0] _zz_134; - wire _zz_135; - reg [10:0] _zz_136; - wire _zz_137; - reg [18:0] _zz_138; - reg _zz_139; + wire _zz_132; + reg [19:0] _zz_133; + wire _zz_134; + reg [10:0] _zz_135; + wire _zz_136; + reg [18:0] _zz_137; + reg _zz_138; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_140; - reg [19:0] _zz_141; - wire _zz_142; - reg [10:0] _zz_143; - wire _zz_144; - reg [18:0] _zz_145; + wire _zz_139; + reg [19:0] _zz_140; + wire _zz_141; + reg [10:0] _zz_142; + wire _zz_143; + reg [18:0] _zz_144; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -993,9 +1056,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_145; wire _zz_146; wire _zz_147; - wire _zz_148; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1008,12 +1071,10 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_149; - wire _zz_150; - wire [1:0] _zz_151; - wire _zz_152; - wire [1:0] _zz_153; - wire _zz_154; + wire [1:0] _zz_148; + wire _zz_149; + wire [1:0] _zz_150; + wire _zz_151; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; @@ -1042,29 +1103,13 @@ module VexRiscv ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_171; - reg [23:0] _zz_172; - reg [31:0] _zz_173; + wire _zz_152; + reg [23:0] _zz_153; + reg [31:0] _zz_154; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1096,18 +1141,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_174; + wire [31:0] _zz_155; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_175; - wire _zz_176; - wire _zz_177; - reg [32:0] _zz_178; + wire [31:0] _zz_156; + wire _zz_157; + wire _zz_158; + reg [32:0] _zz_159; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_179; - wire [31:0] _zz_180; + reg [31:0] _zz_160; + wire [31:0] _zz_161; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1117,7 +1162,7 @@ module VexRiscv ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_181; + reg _zz_162; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1129,6 +1174,7 @@ module VexRiscv ( reg [31:0] decode_to_execute_FORMAL_PC_NEXT; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; reg decode_to_execute_SRC_USE_SUB_LESS; reg decode_to_execute_MEMORY_ENABLE; @@ -1142,9 +1188,10 @@ module VexRiscv ( reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; - reg decode_to_execute_MEMORY_STORE; - reg execute_to_memory_MEMORY_STORE; - reg memory_to_writeBack_MEMORY_STORE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; reg decode_to_execute_SRC_LESS_UNSIGNED; reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; @@ -1170,19 +1217,8 @@ module VexRiscv ( reg decode_to_execute_CSR_WRITE_OPCODE; reg decode_to_execute_CSR_READ_OPCODE; reg decode_to_execute_DO_EBREAK; - reg execute_to_memory_ALIGNEMENT_FAULT; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_MMU_FAULT; - reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; - reg execute_to_memory_MMU_RSP2_isIoAccess; - reg execute_to_memory_MMU_RSP2_isPaging; - reg execute_to_memory_MMU_RSP2_allowRead; - reg execute_to_memory_MMU_RSP2_allowWrite; - reg execute_to_memory_MMU_RSP2_allowExecute; - reg execute_to_memory_MMU_RSP2_exception; - reg execute_to_memory_MMU_RSP2_refilling; - reg execute_to_memory_MMU_RSP2_bypassTranslation; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; reg [31:0] execute_to_memory_SHIFT_RIGHT; @@ -1193,9 +1229,9 @@ module VexRiscv ( reg [33:0] execute_to_memory_MUL_HL; reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; - reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_182; + reg [2:0] _zz_163; + reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; reg execute_CsrPlugin_csr_3859; @@ -1217,70 +1253,42 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3200; reg execute_CsrPlugin_csr_3074; reg execute_CsrPlugin_csr_3202; - reg execute_CsrPlugin_csr_2820; - reg execute_CsrPlugin_csr_2821; - reg execute_CsrPlugin_csr_2822; - reg execute_CsrPlugin_csr_2823; - reg execute_CsrPlugin_csr_2824; - reg execute_CsrPlugin_csr_2825; - reg execute_CsrPlugin_csr_2826; - reg execute_CsrPlugin_csr_2827; - reg execute_CsrPlugin_csr_2828; - reg execute_CsrPlugin_csr_2829; - reg execute_CsrPlugin_csr_2830; - reg execute_CsrPlugin_csr_2831; - reg execute_CsrPlugin_csr_2832; - reg execute_CsrPlugin_csr_2833; - reg execute_CsrPlugin_csr_2834; - reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + reg [31:0] _zz_168; + reg [31:0] _zz_169; + reg [31:0] _zz_170; + reg [31:0] _zz_171; + reg [31:0] _zz_172; + reg [31:0] _zz_173; + reg [31:0] _zz_174; + reg [31:0] _zz_175; + reg [31:0] _zz_176; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; reg [31:0] _zz_183; reg [31:0] _zz_184; reg [31:0] _zz_185; reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [31:0] _zz_199; - reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; - reg [31:0] _zz_208; - reg [31:0] _zz_209; - reg [31:0] _zz_210; - reg [31:0] _zz_211; - reg [31:0] _zz_212; - reg [2:0] _zz_213; - reg _zz_214; + reg [2:0] _zz_187; + reg _zz_188; reg [31:0] iBusWishbone_DAT_MISO_regNext; - wire dBus_cmd_halfPipe_valid; - wire dBus_cmd_halfPipe_ready; - wire dBus_cmd_halfPipe_payload_wr; - wire [31:0] dBus_cmd_halfPipe_payload_address; - wire [31:0] dBus_cmd_halfPipe_payload_data; - wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_215; + reg [2:0] _zz_189; + wire _zz_190; + wire _zz_191; + wire _zz_192; + wire _zz_193; + wire _zz_194; + reg _zz_195; + reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] _zz_1_string; @@ -1350,14 +1358,14 @@ module VexRiscv ( reg [95:0] _zz_56_string; reg [31:0] decode_BRANCH_CTRL_string; reg [31:0] _zz_58_string; - reg [95:0] _zz_101_string; - reg [63:0] _zz_102_string; - reg [23:0] _zz_103_string; - reg [39:0] _zz_104_string; - reg [71:0] _zz_105_string; - reg [31:0] _zz_106_string; + reg [95:0] _zz_100_string; + reg [63:0] _zz_101_string; + reg [23:0] _zz_102_string; + reg [39:0] _zz_103_string; + reg [71:0] _zz_104_string; + reg [31:0] _zz_105_string; + reg [39:0] _zz_106_string; reg [39:0] _zz_107_string; - reg [39:0] _zz_108_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1373,355 +1381,362 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_228 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_229 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_230 = 1'b1; - assign _zz_231 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_232 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_233 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_234 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_235 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_236 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_237 = ((_zz_221 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_238 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_239 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_240 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_241 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_242 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_243 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_244 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_245 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_246 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_247 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_248 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_249 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_250 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_251 = (1'b0 || (! 1'b1)); - assign _zz_252 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_253 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_254 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_255 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_256 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_257 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_258 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_259 = execute_INSTRUCTION[13 : 12]; - assign _zz_260 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_261 = (! memory_arbitration_isStuck); - assign _zz_262 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_263 = (iBus_cmd_valid || (_zz_213 != 3'b000)); - assign _zz_264 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_265 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_266 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_267 = ((_zz_148 && 1'b1) && (! 1'b0)); - assign _zz_268 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_269 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_270 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_271 = execute_INSTRUCTION[13]; - assign _zz_272 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_273 = ($signed(_zz_274) + $signed(_zz_279)); - assign _zz_274 = ($signed(_zz_275) + $signed(_zz_277)); - assign _zz_275 = 52'h0; - assign _zz_276 = {1'b0,memory_MUL_LL}; - assign _zz_277 = {{19{_zz_276[32]}}, _zz_276}; - assign _zz_278 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_279 = {{2{_zz_278[49]}}, _zz_278}; - assign _zz_280 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_281 = {{2{_zz_280[49]}}, _zz_280}; - assign _zz_282 = ($signed(_zz_284) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_283 = _zz_282[31 : 0]; - assign _zz_284 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_285 = _zz_95[32 : 32]; - assign _zz_286 = _zz_95[31 : 31]; - assign _zz_287 = _zz_95[30 : 30]; - assign _zz_288 = _zz_95[29 : 29]; - assign _zz_289 = _zz_95[27 : 27]; - assign _zz_290 = _zz_95[24 : 24]; - assign _zz_291 = _zz_95[16 : 16]; - assign _zz_292 = _zz_95[13 : 13]; - assign _zz_293 = _zz_95[12 : 12]; - assign _zz_294 = _zz_95[11 : 11]; - assign _zz_295 = _zz_95[33 : 33]; - assign _zz_296 = _zz_95[15 : 15]; - assign _zz_297 = _zz_95[5 : 5]; - assign _zz_298 = _zz_95[3 : 3]; - assign _zz_299 = _zz_95[19 : 19]; - assign _zz_300 = _zz_95[10 : 10]; - assign _zz_301 = _zz_95[4 : 4]; - assign _zz_302 = _zz_95[0 : 0]; - assign _zz_303 = (_zz_62 - 4'b0001); - assign _zz_304 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_305 = {29'd0, _zz_304}; - assign _zz_306 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_307 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_308 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_309 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_310 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_311 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_312 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_313 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_314 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_315 = execute_SRC_LESS; - assign _zz_316 = 3'b100; - assign _zz_317 = execute_INSTRUCTION[19 : 15]; - assign _zz_318 = execute_INSTRUCTION[31 : 20]; - assign _zz_319 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_320 = ($signed(_zz_321) + $signed(_zz_324)); - assign _zz_321 = ($signed(_zz_322) + $signed(_zz_323)); - assign _zz_322 = execute_SRC1; - assign _zz_323 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_324 = (execute_SRC_USE_SUB_LESS ? _zz_325 : _zz_326); - assign _zz_325 = 32'h00000001; - assign _zz_326 = 32'h0; - assign _zz_327 = execute_INSTRUCTION[31 : 20]; - assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_329 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_330 = {_zz_134,execute_INSTRUCTION[31 : 20]}; - assign _zz_331 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_332 = {{_zz_138,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_333 = execute_INSTRUCTION[31 : 20]; - assign _zz_334 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_335 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_336 = 3'b100; - assign _zz_337 = (_zz_149 & (~ _zz_338)); - assign _zz_338 = (_zz_149 - 2'b01); - assign _zz_339 = (_zz_151 & (~ _zz_340)); - assign _zz_340 = (_zz_151 - 2'b01); - assign _zz_341 = (_zz_153 & (~ _zz_342)); - assign _zz_342 = (_zz_153 - 2'b01); - assign _zz_343 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_344 = execute_INSTRUCTION[31 : 24]; - assign _zz_345 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_346 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_347 = writeBack_MUL_LOW[31 : 0]; - assign _zz_348 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_349 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_350 = {5'd0, _zz_349}; - assign _zz_351 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_352 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_353 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_354 = {_zz_174,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_355 = _zz_356; - assign _zz_356 = _zz_357; - assign _zz_357 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_175) : _zz_175)} + _zz_359); - assign _zz_358 = memory_DivPlugin_div_needRevert; - assign _zz_359 = {32'd0, _zz_358}; - assign _zz_360 = _zz_177; - assign _zz_361 = {32'd0, _zz_360}; - assign _zz_362 = _zz_176; - assign _zz_363 = {31'd0, _zz_362}; - assign _zz_364 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_365 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_227 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_228 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_229 = 1'b1; + assign _zz_230 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_231 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_232 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_233 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_234 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_235 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_236 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_237 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_238 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_239 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_240 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_241 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_242 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_243 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_244 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_245 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_246 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_247 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_248 = (1'b0 || (! 1'b1)); + assign _zz_249 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_250 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_251 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_252 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_253 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_254 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_255 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_256 = execute_INSTRUCTION[13 : 12]; + assign _zz_257 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_258 = (! memory_arbitration_isStuck); + assign _zz_259 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_260 = (iBus_cmd_valid || (_zz_187 != 3'b000)); + assign _zz_261 = (_zz_223 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_262 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_263 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_264 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_265 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_266 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_267 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_268 = execute_INSTRUCTION[13]; + assign _zz_269 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_270 = ($signed(_zz_271) + $signed(_zz_276)); + assign _zz_271 = ($signed(_zz_272) + $signed(_zz_274)); + assign _zz_272 = 52'h0; + assign _zz_273 = {1'b0,memory_MUL_LL}; + assign _zz_274 = {{19{_zz_273[32]}}, _zz_273}; + assign _zz_275 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_276 = {{2{_zz_275[49]}}, _zz_275}; + assign _zz_277 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_278 = {{2{_zz_277[49]}}, _zz_277}; + assign _zz_279 = ($signed(_zz_281) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_280 = _zz_279[31 : 0]; + assign _zz_281 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_282 = _zz_94[33 : 33]; + assign _zz_283 = _zz_94[32 : 32]; + assign _zz_284 = _zz_94[31 : 31]; + assign _zz_285 = _zz_94[30 : 30]; + assign _zz_286 = _zz_94[28 : 28]; + assign _zz_287 = _zz_94[25 : 25]; + assign _zz_288 = _zz_94[17 : 17]; + assign _zz_289 = _zz_94[16 : 16]; + assign _zz_290 = _zz_94[13 : 13]; + assign _zz_291 = _zz_94[12 : 12]; + assign _zz_292 = _zz_94[11 : 11]; + assign _zz_293 = _zz_94[34 : 34]; + assign _zz_294 = _zz_94[15 : 15]; + assign _zz_295 = _zz_94[5 : 5]; + assign _zz_296 = _zz_94[3 : 3]; + assign _zz_297 = _zz_94[20 : 20]; + assign _zz_298 = _zz_94[10 : 10]; + assign _zz_299 = _zz_94[4 : 4]; + assign _zz_300 = _zz_94[0 : 0]; + assign _zz_301 = (_zz_62 - 4'b0001); + assign _zz_302 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_303 = {29'd0, _zz_302}; + assign _zz_304 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_305 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_306 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_307 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_308 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_309 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_310 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_311 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_312 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_313 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_314 = execute_SRC_LESS; + assign _zz_315 = 3'b100; + assign _zz_316 = execute_INSTRUCTION[19 : 15]; + assign _zz_317 = execute_INSTRUCTION[31 : 20]; + assign _zz_318 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_319 = ($signed(_zz_320) + $signed(_zz_323)); + assign _zz_320 = ($signed(_zz_321) + $signed(_zz_322)); + assign _zz_321 = execute_SRC1; + assign _zz_322 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_323 = (execute_SRC_USE_SUB_LESS ? _zz_324 : _zz_325); + assign _zz_324 = 32'h00000001; + assign _zz_325 = 32'h0; + assign _zz_326 = execute_INSTRUCTION[31 : 20]; + assign _zz_327 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_329 = {_zz_133,execute_INSTRUCTION[31 : 20]}; + assign _zz_330 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_331 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_332 = execute_INSTRUCTION[31 : 20]; + assign _zz_333 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_334 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_335 = 3'b100; + assign _zz_336 = (_zz_148 & (~ _zz_337)); + assign _zz_337 = (_zz_148 - 2'b01); + assign _zz_338 = (_zz_150 & (~ _zz_339)); + assign _zz_339 = (_zz_150 - 2'b01); + assign _zz_340 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_341 = execute_INSTRUCTION[31 : 24]; + assign _zz_342 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_343 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_344 = writeBack_MUL_LOW[31 : 0]; + assign _zz_345 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_346 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_347 = {5'd0, _zz_346}; + assign _zz_348 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_349 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_350 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_351 = {_zz_155,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_352 = _zz_353; + assign _zz_353 = _zz_354; + assign _zz_354 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_156) : _zz_156)} + _zz_356); + assign _zz_355 = memory_DivPlugin_div_needRevert; + assign _zz_356 = {32'd0, _zz_355}; + assign _zz_357 = _zz_158; + assign _zz_358 = {32'd0, _zz_357}; + assign _zz_359 = _zz_157; + assign _zz_360 = {31'd0, _zz_359}; + assign _zz_361 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_362 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_363 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_364 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_365 = execute_CsrPlugin_writeData[7 : 7]; assign _zz_366 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_367 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_368 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_369 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_370 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_371 = (iBus_cmd_payload_address >>> 5); - assign _zz_372 = 1'b1; - assign _zz_373 = 1'b1; - assign _zz_374 = {_zz_66,_zz_65}; - assign _zz_375 = 32'h0000106f; - assign _zz_376 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_377 = 32'h00001073; - assign _zz_378 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_379 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_380 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_381) == 32'h00000003),{(_zz_382 == _zz_383),{_zz_384,{_zz_385,_zz_386}}}}}}; - assign _zz_381 = 32'h0000207f; - assign _zz_382 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_383 = 32'h00000003; - assign _zz_384 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_385 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_386 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_387) == 32'h00001013),{(_zz_388 == _zz_389),{_zz_390,{_zz_391,_zz_392}}}}}}; - assign _zz_387 = 32'hfc00307f; - assign _zz_388 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_389 = 32'h00005033; - assign _zz_390 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_391 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_392 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz_393 = decode_INSTRUCTION[31]; - assign _zz_394 = decode_INSTRUCTION[31]; - assign _zz_395 = decode_INSTRUCTION[7]; - assign _zz_396 = 32'h10103050; - assign _zz_397 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_398 = 1'b0; - assign _zz_399 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_400 = 1'b0; - assign _zz_401 = {(_zz_99 != 1'b0),{({_zz_402,_zz_403} != 2'b00),{(_zz_404 != _zz_405),{_zz_406,{_zz_407,_zz_408}}}}}; - assign _zz_402 = ((decode_INSTRUCTION & _zz_409) == 32'h10000050); - assign _zz_403 = ((decode_INSTRUCTION & _zz_410) == 32'h00000050); - assign _zz_404 = ((decode_INSTRUCTION & _zz_411) == 32'h00000050); - assign _zz_405 = 1'b0; - assign _zz_406 = ({_zz_412,_zz_413} != 2'b00); - assign _zz_407 = ({_zz_414,_zz_415} != 2'b00); - assign _zz_408 = {(_zz_416 != _zz_417),{_zz_418,{_zz_419,_zz_420}}}; - assign _zz_409 = 32'h10203050; - assign _zz_410 = 32'h10103050; - assign _zz_411 = 32'h00103050; - assign _zz_412 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_413 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_414 = _zz_98; - assign _zz_415 = ((decode_INSTRUCTION & _zz_421) == 32'h00000004); - assign _zz_416 = ((decode_INSTRUCTION & _zz_422) == 32'h00000040); - assign _zz_417 = 1'b0; - assign _zz_418 = ({_zz_423,_zz_424} != 2'b00); - assign _zz_419 = ({_zz_425,_zz_426} != 3'b000); - assign _zz_420 = {(_zz_427 != _zz_428),{_zz_429,{_zz_430,_zz_431}}}; - assign _zz_421 = 32'h0000001c; - assign _zz_422 = 32'h00000058; - assign _zz_423 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_424 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h40001010); - assign _zz_426 = {(_zz_433 == _zz_434),(_zz_435 == _zz_436)}; - assign _zz_427 = ((decode_INSTRUCTION & _zz_437) == 32'h00000024); - assign _zz_428 = 1'b0; - assign _zz_429 = ((_zz_438 == _zz_439) != 1'b0); - assign _zz_430 = (_zz_440 != 1'b0); - assign _zz_431 = {(_zz_441 != _zz_442),{_zz_443,{_zz_444,_zz_445}}}; - assign _zz_432 = 32'h40003054; - assign _zz_433 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_434 = 32'h00001010; - assign _zz_435 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_436 = 32'h00001010; - assign _zz_437 = 32'h00000064; - assign _zz_438 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_439 = 32'h00001000; - assign _zz_440 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_441 = {(_zz_446 == _zz_447),(_zz_448 == _zz_449)}; - assign _zz_442 = 2'b00; - assign _zz_443 = ({_zz_99,{_zz_450,_zz_451}} != 3'b000); - assign _zz_444 = ({_zz_452,_zz_453} != 5'h0); - assign _zz_445 = {(_zz_454 != _zz_455),{_zz_456,{_zz_457,_zz_458}}}; - assign _zz_446 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_447 = 32'h00002000; - assign _zz_448 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_449 = 32'h00001000; - assign _zz_450 = ((decode_INSTRUCTION & _zz_459) == 32'h00000020); - assign _zz_451 = ((decode_INSTRUCTION & _zz_460) == 32'h00000020); - assign _zz_452 = ((decode_INSTRUCTION & _zz_461) == 32'h00002040); - assign _zz_453 = {(_zz_462 == _zz_463),{_zz_464,{_zz_465,_zz_466}}}; - assign _zz_454 = ((decode_INSTRUCTION & _zz_467) == 32'h00000020); - assign _zz_455 = 1'b0; - assign _zz_456 = ({_zz_468,{_zz_469,_zz_470}} != 6'h0); - assign _zz_457 = ({_zz_471,_zz_472} != 5'h0); - assign _zz_458 = {(_zz_473 != _zz_474),{_zz_475,{_zz_476,_zz_477}}}; - assign _zz_459 = 32'h00000034; - assign _zz_460 = 32'h00000064; + assign _zz_367 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_368 = (iBus_cmd_payload_address >>> 5); + assign _zz_369 = 1'b1; + assign _zz_370 = 1'b1; + assign _zz_371 = {_zz_66,_zz_65}; + assign _zz_372 = 32'h0000106f; + assign _zz_373 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_374 = 32'h00001073; + assign _zz_375 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_376 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_377 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_378) == 32'h00000003),{(_zz_379 == _zz_380),{_zz_381,{_zz_382,_zz_383}}}}}}; + assign _zz_378 = 32'h0000207f; + assign _zz_379 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_380 = 32'h00000003; + assign _zz_381 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_382 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_383 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_384) == 32'h00005013),{(_zz_385 == _zz_386),{_zz_387,{_zz_388,_zz_389}}}}}}; + assign _zz_384 = 32'hbc00707f; + assign _zz_385 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_386 = 32'h00001013; + assign _zz_387 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_388 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_389 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_390 = decode_INSTRUCTION[31]; + assign _zz_391 = decode_INSTRUCTION[31]; + assign _zz_392 = decode_INSTRUCTION[7]; + assign _zz_393 = 32'h10103050; + assign _zz_394 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_395 = 1'b0; + assign _zz_396 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_397 = 1'b0; + assign _zz_398 = {(_zz_98 != 1'b0),{({_zz_399,_zz_400} != 2'b00),{(_zz_401 != _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}; + assign _zz_399 = ((decode_INSTRUCTION & _zz_406) == 32'h10000050); + assign _zz_400 = ((decode_INSTRUCTION & _zz_407) == 32'h00000050); + assign _zz_401 = ((decode_INSTRUCTION & _zz_408) == 32'h00000050); + assign _zz_402 = 1'b0; + assign _zz_403 = ({_zz_409,_zz_410} != 2'b00); + assign _zz_404 = ({_zz_411,_zz_412} != 2'b00); + assign _zz_405 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; + assign _zz_406 = 32'h10203050; + assign _zz_407 = 32'h10103050; + assign _zz_408 = 32'h00103050; + assign _zz_409 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_410 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_411 = _zz_97; + assign _zz_412 = ((decode_INSTRUCTION & _zz_418) == 32'h00000004); + assign _zz_413 = ((decode_INSTRUCTION & _zz_419) == 32'h00000040); + assign _zz_414 = 1'b0; + assign _zz_415 = ({_zz_420,_zz_421} != 2'b00); + assign _zz_416 = ({_zz_422,_zz_423} != 3'b000); + assign _zz_417 = {(_zz_424 != _zz_425),{_zz_426,{_zz_427,_zz_428}}}; + assign _zz_418 = 32'h0000001c; + assign _zz_419 = 32'h00000058; + assign _zz_420 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_421 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_422 = ((decode_INSTRUCTION & _zz_429) == 32'h40001010); + assign _zz_423 = {(_zz_430 == _zz_431),(_zz_432 == _zz_433)}; + assign _zz_424 = ((decode_INSTRUCTION & _zz_434) == 32'h00000024); + assign _zz_425 = 1'b0; + assign _zz_426 = ((_zz_435 == _zz_436) != 1'b0); + assign _zz_427 = (_zz_437 != 1'b0); + assign _zz_428 = {(_zz_438 != _zz_439),{_zz_440,{_zz_441,_zz_442}}}; + assign _zz_429 = 32'h40003054; + assign _zz_430 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_431 = 32'h00001010; + assign _zz_432 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_433 = 32'h00001010; + assign _zz_434 = 32'h00000064; + assign _zz_435 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_436 = 32'h00001000; + assign _zz_437 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_438 = {(_zz_443 == _zz_444),(_zz_445 == _zz_446)}; + assign _zz_439 = 2'b00; + assign _zz_440 = ((_zz_447 == _zz_448) != 1'b0); + assign _zz_441 = ({_zz_449,_zz_450} != 3'b000); + assign _zz_442 = {(_zz_451 != _zz_452),{_zz_453,{_zz_454,_zz_455}}}; + assign _zz_443 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_444 = 32'h00002000; + assign _zz_445 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_446 = 32'h00001000; + assign _zz_447 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_448 = 32'h00004004; + assign _zz_449 = _zz_98; + assign _zz_450 = {(_zz_456 == _zz_457),(_zz_458 == _zz_459)}; + assign _zz_451 = {(_zz_460 == _zz_461),{_zz_462,{_zz_463,_zz_464}}}; + assign _zz_452 = 5'h0; + assign _zz_453 = ((_zz_465 == _zz_466) != 1'b0); + assign _zz_454 = ({_zz_467,_zz_468} != 6'h0); + assign _zz_455 = {(_zz_469 != _zz_470),{_zz_471,{_zz_472,_zz_473}}}; + assign _zz_456 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_457 = 32'h00000020; + assign _zz_458 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_459 = 32'h00000020; + assign _zz_460 = (decode_INSTRUCTION & 32'h00002040); assign _zz_461 = 32'h00002040; - assign _zz_462 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_463 = 32'h00001040; - assign _zz_464 = ((decode_INSTRUCTION & _zz_478) == 32'h00000040); - assign _zz_465 = (_zz_479 == _zz_480); - assign _zz_466 = (_zz_481 == _zz_482); - assign _zz_467 = 32'h00000020; - assign _zz_468 = ((decode_INSTRUCTION & _zz_483) == 32'h00000008); - assign _zz_469 = (_zz_484 == _zz_485); - assign _zz_470 = {_zz_97,{_zz_486,_zz_487}}; - assign _zz_471 = _zz_97; - assign _zz_472 = {_zz_488,{_zz_489,_zz_490}}; - assign _zz_473 = {_zz_98,{_zz_491,_zz_492}}; - assign _zz_474 = 6'h0; - assign _zz_475 = ({_zz_493,_zz_494} != 2'b00); - assign _zz_476 = (_zz_495 != _zz_496); - assign _zz_477 = {_zz_497,{_zz_498,_zz_499}}; - assign _zz_478 = 32'h00100040; - assign _zz_479 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_480 = 32'h00000040; - assign _zz_481 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_482 = 32'h0; - assign _zz_483 = 32'h00000008; - assign _zz_484 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_485 = 32'h00000040; - assign _zz_486 = (_zz_500 == _zz_501); - assign _zz_487 = {_zz_502,_zz_503}; - assign _zz_488 = ((decode_INSTRUCTION & _zz_504) == 32'h00002010); - assign _zz_489 = (_zz_505 == _zz_506); - assign _zz_490 = {_zz_507,_zz_508}; - assign _zz_491 = (_zz_509 == _zz_510); - assign _zz_492 = {_zz_511,{_zz_512,_zz_513}}; - assign _zz_493 = _zz_97; - assign _zz_494 = (_zz_514 == _zz_515); - assign _zz_495 = {_zz_97,_zz_516}; - assign _zz_496 = 2'b00; - assign _zz_497 = (_zz_517 != 1'b0); - assign _zz_498 = (_zz_518 != _zz_519); - assign _zz_499 = {_zz_520,{_zz_521,_zz_522}}; - assign _zz_500 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_501 = 32'h00004020; - assign _zz_502 = ((decode_INSTRUCTION & _zz_523) == 32'h00000010); - assign _zz_503 = ((decode_INSTRUCTION & _zz_524) == 32'h00000020); - assign _zz_504 = 32'h00002030; - assign _zz_505 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_506 = 32'h00000010; - assign _zz_507 = ((decode_INSTRUCTION & _zz_525) == 32'h00002020); - assign _zz_508 = ((decode_INSTRUCTION & _zz_526) == 32'h00000020); - assign _zz_509 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_510 = 32'h00001010; - assign _zz_511 = ((decode_INSTRUCTION & _zz_527) == 32'h00002010); - assign _zz_512 = (_zz_528 == _zz_529); - assign _zz_513 = {_zz_530,_zz_531}; - assign _zz_514 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_515 = 32'h00000020; - assign _zz_516 = ((decode_INSTRUCTION & _zz_532) == 32'h0); - assign _zz_517 = ((decode_INSTRUCTION & _zz_533) == 32'h00004010); - assign _zz_518 = (_zz_534 == _zz_535); - assign _zz_519 = 1'b0; - assign _zz_520 = ({_zz_536,_zz_537} != 4'b0000); - assign _zz_521 = (_zz_538 != _zz_539); - assign _zz_522 = {_zz_540,{_zz_541,_zz_542}}; - assign _zz_523 = 32'h00000030; - assign _zz_524 = 32'h02000020; - assign _zz_525 = 32'h02002060; - assign _zz_526 = 32'h02003020; + assign _zz_462 = ((decode_INSTRUCTION & _zz_474) == 32'h00001040); + assign _zz_463 = (_zz_475 == _zz_476); + assign _zz_464 = {_zz_477,_zz_478}; + assign _zz_465 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_466 = 32'h00000020; + assign _zz_467 = (_zz_479 == _zz_480); + assign _zz_468 = {_zz_481,{_zz_482,_zz_483}}; + assign _zz_469 = {_zz_96,{_zz_484,_zz_485}}; + assign _zz_470 = 5'h0; + assign _zz_471 = ({_zz_486,_zz_487} != 6'h0); + assign _zz_472 = (_zz_488 != _zz_489); + assign _zz_473 = {_zz_490,{_zz_491,_zz_492}}; + assign _zz_474 = 32'h00001040; + assign _zz_475 = (decode_INSTRUCTION & 32'h00100040); + assign _zz_476 = 32'h00000040; + assign _zz_477 = ((decode_INSTRUCTION & _zz_493) == 32'h00000040); + assign _zz_478 = ((decode_INSTRUCTION & _zz_494) == 32'h0); + assign _zz_479 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_480 = 32'h00000008; + assign _zz_481 = ((decode_INSTRUCTION & _zz_495) == 32'h00000040); + assign _zz_482 = _zz_96; + assign _zz_483 = {_zz_496,{_zz_497,_zz_498}}; + assign _zz_484 = (_zz_499 == _zz_500); + assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; + assign _zz_486 = _zz_97; + assign _zz_487 = {_zz_504,{_zz_505,_zz_506}}; + assign _zz_488 = {_zz_96,_zz_507}; + assign _zz_489 = 2'b00; + assign _zz_490 = ({_zz_508,_zz_509} != 2'b00); + assign _zz_491 = (_zz_510 != _zz_511); + assign _zz_492 = {_zz_512,{_zz_513,_zz_514}}; + assign _zz_493 = 32'h00000050; + assign _zz_494 = 32'h00000038; + assign _zz_495 = 32'h00000040; + assign _zz_496 = ((decode_INSTRUCTION & _zz_515) == 32'h00004020); + assign _zz_497 = (_zz_516 == _zz_517); + assign _zz_498 = (_zz_518 == _zz_519); + assign _zz_499 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_500 = 32'h00002010; + assign _zz_501 = ((decode_INSTRUCTION & _zz_520) == 32'h00000010); + assign _zz_502 = (_zz_521 == _zz_522); + assign _zz_503 = (_zz_523 == _zz_524); + assign _zz_504 = ((decode_INSTRUCTION & _zz_525) == 32'h00001010); + assign _zz_505 = (_zz_526 == _zz_527); + assign _zz_506 = {_zz_528,{_zz_529,_zz_530}}; + assign _zz_507 = ((decode_INSTRUCTION & _zz_531) == 32'h00000020); + assign _zz_508 = _zz_96; + assign _zz_509 = (_zz_532 == _zz_533); + assign _zz_510 = (_zz_534 == _zz_535); + assign _zz_511 = 1'b0; + assign _zz_512 = (_zz_536 != 1'b0); + assign _zz_513 = (_zz_537 != _zz_538); + assign _zz_514 = {_zz_539,{_zz_540,_zz_541}}; + assign _zz_515 = 32'h00004020; + assign _zz_516 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_517 = 32'h00000010; + assign _zz_518 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_519 = 32'h00000020; + assign _zz_520 = 32'h00001030; + assign _zz_521 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_522 = 32'h00002020; + assign _zz_523 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_524 = 32'h00000020; + assign _zz_525 = 32'h00001010; + assign _zz_526 = (decode_INSTRUCTION & 32'h00002010); assign _zz_527 = 32'h00002010; - assign _zz_528 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_529 = 32'h00000010; - assign _zz_530 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_531 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_532 = 32'h00000020; - assign _zz_533 = 32'h00004014; - assign _zz_534 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_535 = 32'h00002010; - assign _zz_536 = ((decode_INSTRUCTION & _zz_543) == 32'h0); - assign _zz_537 = {(_zz_544 == _zz_545),{_zz_546,_zz_547}}; - assign _zz_538 = ((decode_INSTRUCTION & _zz_548) == 32'h0); - assign _zz_539 = 1'b0; - assign _zz_540 = ({_zz_549,{_zz_550,_zz_551}} != 3'b000); - assign _zz_541 = ({_zz_552,_zz_553} != 2'b00); - assign _zz_542 = {(_zz_554 != _zz_555),(_zz_556 != _zz_557)}; - assign _zz_543 = 32'h00000044; - assign _zz_544 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_545 = 32'h0; - assign _zz_546 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_547 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_548 = 32'h00000058; - assign _zz_549 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_550 = ((decode_INSTRUCTION & _zz_558) == 32'h00002010); - assign _zz_551 = ((decode_INSTRUCTION & _zz_559) == 32'h40000030); - assign _zz_552 = ((decode_INSTRUCTION & _zz_560) == 32'h00000004); - assign _zz_553 = _zz_96; - assign _zz_554 = {(_zz_561 == _zz_562),_zz_96}; - assign _zz_555 = 2'b00; - assign _zz_556 = ((decode_INSTRUCTION & _zz_563) == 32'h00001004); - assign _zz_557 = 1'b0; - assign _zz_558 = 32'h00002014; - assign _zz_559 = 32'h40000034; - assign _zz_560 = 32'h00000014; - assign _zz_561 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_562 = 32'h00000004; - assign _zz_563 = 32'h00001054; - assign _zz_564 = execute_INSTRUCTION[31]; - assign _zz_565 = execute_INSTRUCTION[31]; - assign _zz_566 = execute_INSTRUCTION[7]; - assign _zz_567 = 32'h0; + assign _zz_528 = ((decode_INSTRUCTION & _zz_542) == 32'h00000010); + assign _zz_529 = (_zz_543 == _zz_544); + assign _zz_530 = (_zz_545 == _zz_546); + assign _zz_531 = 32'h00000070; + assign _zz_532 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_533 = 32'h0; + assign _zz_534 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_535 = 32'h00004010; + assign _zz_536 = ((decode_INSTRUCTION & _zz_547) == 32'h00002010); + assign _zz_537 = {_zz_548,{_zz_549,_zz_550}}; + assign _zz_538 = 4'b0000; + assign _zz_539 = (_zz_551 != 1'b0); + assign _zz_540 = (_zz_552 != _zz_553); + assign _zz_541 = {_zz_554,{_zz_555,_zz_556}}; + assign _zz_542 = 32'h00000050; + assign _zz_543 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_544 = 32'h00000004; + assign _zz_545 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_546 = 32'h0; + assign _zz_547 = 32'h00006014; + assign _zz_548 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_549 = ((decode_INSTRUCTION & _zz_557) == 32'h0); + assign _zz_550 = {(_zz_558 == _zz_559),(_zz_560 == _zz_561)}; + assign _zz_551 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_552 = {(_zz_562 == _zz_563),{_zz_564,_zz_565}}; + assign _zz_553 = 3'b000; + assign _zz_554 = ({_zz_566,_zz_95} != 2'b00); + assign _zz_555 = ({_zz_567,_zz_568} != 2'b00); + assign _zz_556 = (_zz_569 != 1'b0); + assign _zz_557 = 32'h00000018; + assign _zz_558 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_559 = 32'h00002000; + assign _zz_560 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_561 = 32'h00001000; + assign _zz_562 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_563 = 32'h00000040; + assign _zz_564 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_565 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_566 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_567 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_568 = _zz_95; + assign _zz_569 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_570 = execute_INSTRUCTION[31]; + assign _zz_571 = execute_INSTRUCTION[31]; + assign _zz_572 = execute_INSTRUCTION[7]; + assign _zz_573 = 32'h0; always @ (posedge clk) begin - if(_zz_372) begin - _zz_225 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_369) begin + _zz_224 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_373) begin - _zz_226 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_370) begin + _zz_225 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1732,13 +1747,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_216 ), //i - .io_cpu_prefetch_isValid (_zz_217 ), //i + .io_flush (_zz_196 ), //i + .io_cpu_prefetch_isValid (_zz_197 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_218 ), //i - .io_cpu_fetch_isStuck (_zz_219 ), //i - .io_cpu_fetch_isRemoved (_zz_220 ), //i + .io_cpu_fetch_isValid (_zz_198 ), //i + .io_cpu_fetch_isStuck (_zz_199 ), //i + .io_cpu_fetch_isRemoved (_zz_200 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1751,8 +1766,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_221 ), //i - .io_cpu_decode_isStuck (_zz_222 ), //i + .io_cpu_decode_isValid (_zz_201 ), //i + .io_cpu_decode_isStuck (_zz_202 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1760,8 +1775,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_223 ), //i - .io_cpu_fill_valid (_zz_224 ), //i + .io_cpu_decode_isUser (_zz_203 ), //i + .io_cpu_fill_valid (_zz_204 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1770,24 +1785,85 @@ module VexRiscv ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_182[2:0] ), //i + ._zz_9 (_zz_163[2:0] ), //i ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_205 ), //i + .io_cpu_execute_address (_zz_206[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_89[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_207 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_208[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_209 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_210 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_211 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_212[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_213 ), //i + .io_cpu_writeBack_fence_SR (_zz_214 ), //i + .io_cpu_writeBack_fence_SO (_zz_215 ), //i + .io_cpu_writeBack_fence_SI (_zz_216 ), //i + .io_cpu_writeBack_fence_PW (_zz_217 ), //i + .io_cpu_writeBack_fence_PR (_zz_218 ), //i + .io_cpu_writeBack_fence_PO (_zz_219 ), //i + .io_cpu_writeBack_fence_PI (_zz_220 ), //i + .io_cpu_writeBack_fence_FM (_zz_221[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_222 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_223 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); always @(*) begin - case(_zz_374) + case(_zz_371) 2'b00 : begin - _zz_227 = CsrPlugin_jumpInterface_payload; + _zz_226 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_227 = DBusSimplePlugin_redoBranch_payload; + _zz_226 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_227 = BranchPlugin_jumpInterface_payload; + _zz_226 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_227 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_226 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2377,74 +2453,74 @@ module VexRiscv ( default : _zz_58_string = "????"; endcase end + always @(*) begin + case(_zz_100) + `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; + default : _zz_100_string = "????????????"; + endcase + end always @(*) begin case(_zz_101) - `Src1CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_101_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_101_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_101_string = "URS1 "; - default : _zz_101_string = "????????????"; + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; + default : _zz_101_string = "????????"; endcase end always @(*) begin case(_zz_102) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_102_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_102_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_102_string = "BITWISE "; - default : _zz_102_string = "????????"; + `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; + default : _zz_102_string = "???"; endcase end always @(*) begin case(_zz_103) - `Src2CtrlEnum_defaultEncoding_RS : _zz_103_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_103_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_103_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_103_string = "PC "; - default : _zz_103_string = "???"; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; + default : _zz_103_string = "?????"; endcase end always @(*) begin case(_zz_104) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_104_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_104_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_104_string = "AND_1"; - default : _zz_104_string = "?????"; + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; + default : _zz_104_string = "?????????"; endcase end always @(*) begin case(_zz_105) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_105_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_105_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_105_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_105_string = "SRA_1 "; - default : _zz_105_string = "?????????"; + `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; + default : _zz_105_string = "????"; endcase end always @(*) begin case(_zz_106) - `BranchCtrlEnum_defaultEncoding_INC : _zz_106_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_106_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_106_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_106_string = "JALR"; - default : _zz_106_string = "????"; + `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; + default : _zz_106_string = "?????"; endcase end always @(*) begin case(_zz_107) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_107_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_107_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_107_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_107_string = "ECALL"; + `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; default : _zz_107_string = "?????"; endcase end - always @(*) begin - case(_zz_108) - `Input2Kind_defaultEncoding_RS : _zz_108_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_108_string = "IMM_I"; - default : _zz_108_string = "?????"; - endcase - end always @(*) begin case(decode_to_execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; @@ -2542,8 +2618,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_273) + $signed(_zz_281)); - assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign memory_MUL_LOW = ($signed(_zz_270) + $signed(_zz_278)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2551,53 +2626,56 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_283; - assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_110; + assign execute_SHIFT_RIGHT = _zz_280; + assign execute_REGFILE_WRITE_DATA = _zz_109; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_206[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_285[0]; - assign decode_IS_RS1_SIGNED = _zz_286[0]; - assign decode_IS_DIV = _zz_287[0]; + assign decode_IS_RS2_SIGNED = _zz_282[0]; + assign decode_IS_RS1_SIGNED = _zz_283[0]; + assign decode_IS_DIV = _zz_284[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_288[0]; + assign decode_IS_MUL = _zz_285[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_289[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_286[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_290[0]; + assign decode_IS_CSR = _zz_287[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_291[0]; - assign decode_MEMORY_STORE = _zz_292[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_288[0]; + assign decode_MEMORY_MANAGMENT = _zz_289[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_290[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_293[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_294[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_291[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_292[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; assign _zz_25 = _zz_26; assign decode_SRC1_CTRL = _zz_27; assign _zz_28 = _zz_29; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_295[0]; + assign decode_IS_EBREAK = _zz_293[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2636,13 +2714,13 @@ module VexRiscv ( assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_132; + assign execute_BRANCH_COND_RESULT = _zz_131; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_296[0]; - assign decode_RS1_USE = _zz_297[0]; + assign decode_RS2_USE = _zz_294[0]; + assign decode_RS1_USE = _zz_295[0]; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_228)begin + if(_zz_227)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2655,28 +2733,28 @@ module VexRiscv ( assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; always @ (*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_121)begin - if((_zz_122 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_123; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_122; end end - if(_zz_229)begin - if(_zz_230)begin - if(_zz_125)begin + if(_zz_228)begin + if(_zz_229)begin + if(_zz_124)begin decode_RS2 = _zz_57; end end end - if(_zz_231)begin + if(_zz_230)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_127)begin + if(_zz_126)begin decode_RS2 = _zz_38; end end end - if(_zz_232)begin + if(_zz_231)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_129)begin + if(_zz_128)begin decode_RS2 = _zz_37; end end @@ -2685,28 +2763,28 @@ module VexRiscv ( always @ (*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_121)begin - if((_zz_122 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_123; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_122; end end - if(_zz_229)begin - if(_zz_230)begin - if(_zz_124)begin + if(_zz_228)begin + if(_zz_229)begin + if(_zz_123)begin decode_RS1 = _zz_57; end end end - if(_zz_231)begin + if(_zz_230)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_126)begin + if(_zz_125)begin decode_RS1 = _zz_38; end end end - if(_zz_232)begin + if(_zz_231)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_128)begin + if(_zz_127)begin decode_RS1 = _zz_37; end end @@ -2719,7 +2797,7 @@ module VexRiscv ( if(memory_arbitration_isValid)begin case(memory_SHIFT_CTRL) `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_118; + _zz_38 = _zz_117; end `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin _zz_38 = memory_SHIFT_RIGHT; @@ -2731,7 +2809,7 @@ module VexRiscv ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_233)begin + if(_zz_232)begin _zz_38 = memory_DivPlugin_div_result; end end @@ -2744,13 +2822,13 @@ module VexRiscv ( assign _zz_41 = execute_PC; assign execute_SRC2_CTRL = _zz_42; assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_298[0]; - assign decode_SRC_ADD_ZERO = _zz_299[0]; + assign decode_SRC_USE_SUB_LESS = _zz_296[0]; + assign decode_SRC_ADD_ZERO = _zz_297[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_116; - assign execute_SRC1 = _zz_111; + assign execute_SRC2 = _zz_115; + assign execute_SRC1 = _zz_110; assign execute_ALU_BITWISE_CTRL = _zz_45; assign _zz_46 = writeBack_INSTRUCTION; assign _zz_47 = writeBack_REGFILE_WRITE_VALID; @@ -2763,91 +2841,69 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_300[0]; + decode_REGFILE_WRITE_VALID = _zz_298[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_375) == 32'h00000003),{(_zz_376 == _zz_377),{_zz_378,{_zz_379,_zz_380}}}}}}} != 21'h0); - assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_372) == 32'h00000003),{(_zz_373 == _zz_374),{_zz_375,{_zz_376,_zz_377}}}}}}} != 22'h0); always @ (*) begin _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_57 = writeBack_DBusSimplePlugin_rspFormated; + _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_272) + case(_zz_269) 2'b00 : begin - _zz_57 = _zz_347; + _zz_57 = _zz_344; end default : begin - _zz_57 = _zz_348; + _zz_57 = _zz_345; end endcase end end - assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; - assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; - assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; - assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; - assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; - assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; - assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; - assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; - assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; - assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; - assign memory_PC = execute_to_memory_PC; - assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; - assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); - assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; - assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; - assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; - assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; - assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; - assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; - assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_301[0]; - assign decode_FLUSH_ALL = _zz_302[0]; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_299[0]; + assign decode_FLUSH_ALL = _zz_300[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_234)begin + if(_zz_233)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_235)begin + if(_zz_234)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_236)begin + if(_zz_235)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_237)begin + if(_zz_236)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2862,16 +2918,9 @@ module VexRiscv ( end always @ (*) begin - _zz_60 = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_60 = DBusSimplePlugin_redoBranch_payload; - end - end - - always @ (*) begin - _zz_61 = decode_FORMAL_PC_NEXT; + _zz_60 = decode_FORMAL_PC_NEXT; if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_61 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; end end @@ -2880,10 +2929,10 @@ module VexRiscv ( assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; always @ (*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_182) + case(_zz_163) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2894,7 +2943,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_119 || _zz_120)))begin + if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin decode_arbitration_haltByOther = 1'b1; end if(CsrPlugin_pipelineLiberator_active)begin @@ -2907,7 +2956,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_238)begin + if(_zz_237)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2921,22 +2970,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_238)begin + if(_zz_237)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_88)))begin + if(((_zz_222 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_239)begin + if(_zz_238)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_228)begin + if(_zz_227)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2948,14 +2997,17 @@ module VexRiscv ( always @ (*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_240)begin + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_239)begin execute_arbitration_haltByOther = 1'b1; end end always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_241)begin + if(_zz_240)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -2965,8 +3017,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_240)begin - if(_zz_242)begin + if(_zz_239)begin + if(_zz_241)begin execute_arbitration_flushIt = 1'b1; end end @@ -2977,11 +3029,11 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_241)begin + if(_zz_240)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_240)begin - if(_zz_242)begin + if(_zz_239)begin + if(_zz_241)begin execute_arbitration_flushNext = 1'b1; end end @@ -2989,15 +3041,12 @@ module VexRiscv ( always @ (*) begin memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin - memory_arbitration_haltItself = 1'b1; - end if(memory_CfuPlugin_CFU_IN_FLIGHT)begin if((! memory_CfuPlugin_rsp_valid))begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_233)begin + if(_zz_232)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3007,7 +3056,7 @@ module VexRiscv ( assign memory_arbitration_haltByOther = 1'b0; always @ (*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_243)begin + if(CfuPlugin_joinException_valid)begin memory_arbitration_removeIt = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -3015,39 +3064,51 @@ module VexRiscv ( end end + assign memory_arbitration_flushIt = 1'b0; always @ (*) begin - memory_arbitration_flushIt = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; + memory_arbitration_flushNext = 1'b0; + if(CfuPlugin_joinException_valid)begin + memory_arbitration_flushNext = 1'b1; end end always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(_zz_243)begin - memory_arbitration_flushNext = 1'b1; + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; end end - assign writeBack_arbitration_haltItself = 1'b0; assign writeBack_arbitration_haltByOther = 1'b0; always @ (*) begin writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end if(writeBack_arbitration_isFlushed)begin writeBack_arbitration_removeIt = 1'b1; end end - assign writeBack_arbitration_flushIt = 1'b0; + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + always @ (*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_244)begin + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_242)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_245)begin + if(_zz_243)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3061,21 +3122,21 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_244)begin + if(_zz_242)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_245)begin + if(_zz_243)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_240)begin - if(_zz_242)begin + if(_zz_239)begin + if(_zz_241)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_246)begin + if(_zz_244)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3087,9 +3148,16 @@ module VexRiscv ( end end + always @ (*) begin + _zz_61 = 1'b0; + if(DebugPlugin_godmode)begin + _zz_61 = 1'b1; + end + end + always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_239)begin + if(_zz_238)begin CsrPlugin_inWfi = 1'b1; end end @@ -3103,21 +3171,21 @@ module VexRiscv ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_244)begin + if(_zz_242)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_245)begin + if(_zz_243)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_244)begin + if(_zz_242)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_245)begin - case(_zz_247) + if(_zz_243)begin + case(_zz_245) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3149,13 +3217,13 @@ module VexRiscv ( end assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; - assign _zz_63 = (_zz_62 & (~ _zz_303)); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_63 = (_zz_62 & (~ _zz_301)); assign _zz_64 = _zz_63[3]; assign _zz_65 = (_zz_63[1] || _zz_64); assign _zz_66 = (_zz_63[2] || _zz_64); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_227; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_226; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3175,7 +3243,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_305); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_303); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3267,7 +3335,7 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_182) + case(_zz_163) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3279,7 +3347,7 @@ module VexRiscv ( endcase end - assign _zz_76 = _zz_306[11]; + assign _zz_76 = _zz_304[11]; always @ (*) begin _zz_77[18] = _zz_76; _zz_77[17] = _zz_76; @@ -3303,13 +3371,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_307[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_305[31])); if(_zz_82)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_78 = _zz_308[19]; + assign _zz_78 = _zz_306[19]; always @ (*) begin _zz_79[10] = _zz_78; _zz_79[9] = _zz_78; @@ -3324,7 +3392,7 @@ module VexRiscv ( _zz_79[0] = _zz_78; end - assign _zz_80 = _zz_309[11]; + assign _zz_80 = _zz_307[11]; always @ (*) begin _zz_81[18] = _zz_80; _zz_81[17] = _zz_80; @@ -3350,16 +3418,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_82 = _zz_310[1]; + _zz_82 = _zz_308[1]; end default : begin - _zz_82 = _zz_311[1]; + _zz_82 = _zz_309[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_83 = _zz_312[19]; + assign _zz_83 = _zz_310[19]; always @ (*) begin _zz_84[10] = _zz_83; _zz_84[9] = _zz_83; @@ -3374,7 +3442,7 @@ module VexRiscv ( _zz_84[0] = _zz_83; end - assign _zz_85 = _zz_313[11]; + assign _zz_85 = _zz_311[11]; always @ (*) begin _zz_86[18] = _zz_85; _zz_86[17] = _zz_85; @@ -3397,7 +3465,7 @@ module VexRiscv ( _zz_86[0] = _zz_85; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_393,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_394,_zz_395},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_390,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_391,_zz_392},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3406,52 +3474,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_217 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_219 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_218; + assign _zz_197 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_198 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_199 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_198; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_222 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_223 = (CsrPlugin_privilege == 2'b00); + assign _zz_201 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_202 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_203 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_237)begin + if(_zz_236)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_235)begin + if(_zz_234)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_224 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_235)begin - _zz_224 = 1'b1; + _zz_204 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_234)begin + _zz_204 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_236)begin + if(_zz_235)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_234)begin + if(_zz_233)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_236)begin + if(_zz_235)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_234)begin + if(_zz_233)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3461,23 +3529,39 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_216 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign _zz_88 = 1'b0; - always @ (*) begin - execute_DBusSimplePlugin_skipCmd = 1'b0; - if(execute_ALIGNEMENT_FAULT)begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - end - - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_88)); - assign dBus_cmd_payload_wr = execute_MEMORY_STORE; - assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin - case(dBus_cmd_payload_size) + assign _zz_196 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_223 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_205 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_206 = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) 2'b00 : begin _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end @@ -3490,152 +3574,145 @@ module VexRiscv ( endcase end - assign dBus_cmd_payload_data = _zz_89; + assign _zz_222 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_207 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_208 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_207; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_208; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - case(dBus_cmd_payload_size) - 2'b00 : begin - _zz_90 = 4'b0001; - end - 2'b01 : begin - _zz_90 = 4'b0011; - end - default : begin - _zz_90 = 4'b1111; - end - endcase + _zz_209 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_209 = 1'b1; + end end - assign execute_DBusSimplePlugin_formalMask = (_zz_90 <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; - assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; + assign _zz_210 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_211 = (CsrPlugin_privilege == 2'b00); + assign _zz_212 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_248)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end else begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_246)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; end end - if(_zz_249)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end end + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_248)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; - end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_314}; - end - if(! memory_MMU_RSP2_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_246)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end - assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_redoBranch_valid = 1'b1; - end - if(_zz_249)begin - DBusSimplePlugin_redoBranch_valid = 1'b0; + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_246)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_312}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_313}; + end end end - assign DBusSimplePlugin_redoBranch_payload = memory_PC; always @ (*) begin - writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin - writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[15 : 8]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; end 2'b10 : begin - writeBack_DBusSimplePlugin_rspShifted[15 : 0] = writeBack_MEMORY_READ_DATA[31 : 16]; + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; end 2'b11 : begin - writeBack_DBusSimplePlugin_rspShifted[7 : 0] = writeBack_MEMORY_READ_DATA[31 : 24]; + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; end default : begin end endcase end - assign _zz_91 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_92[31] = _zz_91; - _zz_92[30] = _zz_91; - _zz_92[29] = _zz_91; - _zz_92[28] = _zz_91; - _zz_92[27] = _zz_91; - _zz_92[26] = _zz_91; - _zz_92[25] = _zz_91; - _zz_92[24] = _zz_91; - _zz_92[23] = _zz_91; - _zz_92[22] = _zz_91; - _zz_92[21] = _zz_91; - _zz_92[20] = _zz_91; - _zz_92[19] = _zz_91; - _zz_92[18] = _zz_91; - _zz_92[17] = _zz_91; - _zz_92[16] = _zz_91; - _zz_92[15] = _zz_91; - _zz_92[14] = _zz_91; - _zz_92[13] = _zz_91; - _zz_92[12] = _zz_91; - _zz_92[11] = _zz_91; - _zz_92[10] = _zz_91; - _zz_92[9] = _zz_91; - _zz_92[8] = _zz_91; - _zz_92[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_93 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_94[31] = _zz_93; - _zz_94[30] = _zz_93; - _zz_94[29] = _zz_93; - _zz_94[28] = _zz_93; - _zz_94[27] = _zz_93; - _zz_94[26] = _zz_93; - _zz_94[25] = _zz_93; - _zz_94[24] = _zz_93; - _zz_94[23] = _zz_93; - _zz_94[22] = _zz_93; - _zz_94[21] = _zz_93; - _zz_94[20] = _zz_93; - _zz_94[19] = _zz_93; - _zz_94[18] = _zz_93; - _zz_94[17] = _zz_93; - _zz_94[16] = _zz_93; - _zz_94[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_270) + assign _zz_90 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_91[31] = _zz_90; + _zz_91[30] = _zz_90; + _zz_91[29] = _zz_90; + _zz_91[28] = _zz_90; + _zz_91[27] = _zz_90; + _zz_91[26] = _zz_90; + _zz_91[25] = _zz_90; + _zz_91[24] = _zz_90; + _zz_91[23] = _zz_90; + _zz_91[22] = _zz_90; + _zz_91[21] = _zz_90; + _zz_91[20] = _zz_90; + _zz_91[19] = _zz_90; + _zz_91[18] = _zz_90; + _zz_91[17] = _zz_90; + _zz_91[16] = _zz_90; + _zz_91[15] = _zz_90; + _zz_91[14] = _zz_90; + _zz_91[13] = _zz_90; + _zz_91[12] = _zz_90; + _zz_91[11] = _zz_90; + _zz_91[10] = _zz_90; + _zz_91[9] = _zz_90; + _zz_91[8] = _zz_90; + _zz_91[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_92 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_93[31] = _zz_92; + _zz_93[30] = _zz_92; + _zz_93[29] = _zz_92; + _zz_93[28] = _zz_92; + _zz_93[27] = _zz_92; + _zz_93[26] = _zz_92; + _zz_93[25] = _zz_92; + _zz_93[24] = _zz_92; + _zz_93[23] = _zz_92; + _zz_93[22] = _zz_92; + _zz_93[21] = _zz_92; + _zz_93[20] = _zz_92; + _zz_93[19] = _zz_92; + _zz_93[18] = _zz_92; + _zz_93[17] = _zz_92; + _zz_93[16] = _zz_92; + _zz_93[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_267) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_92; + writeBack_DBusCachedPlugin_rspFormated = _zz_91; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_94; + writeBack_DBusCachedPlugin_rspFormated = _zz_93; end default : begin - writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; end endcase end @@ -3649,61 +3726,61 @@ module VexRiscv ( assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_96 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_97 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_98 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_99 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_100 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_95 = {(((decode_INSTRUCTION & _zz_396) == 32'h00100050) != 1'b0),{(_zz_100 != 1'b0),{(_zz_100 != 1'b0),{(_zz_397 != _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}; - assign _zz_101 = _zz_95[2 : 1]; - assign _zz_56 = _zz_101; - assign _zz_102 = _zz_95[7 : 6]; - assign _zz_55 = _zz_102; - assign _zz_103 = _zz_95[9 : 8]; - assign _zz_54 = _zz_103; - assign _zz_104 = _zz_95[18 : 17]; - assign _zz_53 = _zz_104; - assign _zz_105 = _zz_95[21 : 20]; - assign _zz_52 = _zz_105; - assign _zz_106 = _zz_95[23 : 22]; - assign _zz_51 = _zz_106; - assign _zz_107 = _zz_95[26 : 25]; - assign _zz_50 = _zz_107; - assign _zz_108 = _zz_95[28 : 28]; - assign _zz_49 = _zz_108; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_96 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_94 = {(((decode_INSTRUCTION & _zz_393) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_394 != _zz_395),{_zz_396,{_zz_397,_zz_398}}}}}}; + assign _zz_100 = _zz_94[2 : 1]; + assign _zz_56 = _zz_100; + assign _zz_101 = _zz_94[7 : 6]; + assign _zz_55 = _zz_101; + assign _zz_102 = _zz_94[9 : 8]; + assign _zz_54 = _zz_102; + assign _zz_103 = _zz_94[19 : 18]; + assign _zz_53 = _zz_103; + assign _zz_104 = _zz_94[22 : 21]; + assign _zz_52 = _zz_104; + assign _zz_105 = _zz_94[24 : 23]; + assign _zz_51 = _zz_105; + assign _zz_106 = _zz_94[27 : 26]; + assign _zz_50 = _zz_106; + assign _zz_107 = _zz_94[29 : 29]; + assign _zz_49 = _zz_107; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_225; - assign decode_RegFilePlugin_rs2Data = _zz_226; + assign decode_RegFilePlugin_rs1Data = _zz_224; + assign decode_RegFilePlugin_rs2Data = _zz_225; always @ (*) begin lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_109)begin + if(_zz_108)begin lastStageRegFileWrite_valid = 1'b1; end end always @ (*) begin lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_109)begin + if(_zz_108)begin lastStageRegFileWrite_payload_address = 5'h0; end end always @ (*) begin lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_109)begin + if(_zz_108)begin lastStageRegFileWrite_payload_data = 32'h0; end end @@ -3725,13 +3802,13 @@ module VexRiscv ( always @ (*) begin case(execute_ALU_CTRL) `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_110 = execute_IntAluPlugin_bitwise; + _zz_109 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_110 = {31'd0, _zz_315}; + _zz_109 = {31'd0, _zz_314}; end default : begin - _zz_110 = execute_SRC_ADD_SUB; + _zz_109 = execute_SRC_ADD_SUB; end endcase end @@ -3739,87 +3816,87 @@ module VexRiscv ( always @ (*) begin case(execute_SRC1_CTRL) `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_111 = execute_RS1; + _zz_110 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_111 = {29'd0, _zz_316}; + _zz_110 = {29'd0, _zz_315}; end `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_111 = {execute_INSTRUCTION[31 : 12],12'h0}; + _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_111 = {27'd0, _zz_317}; + _zz_110 = {27'd0, _zz_316}; end endcase end - assign _zz_112 = _zz_318[11]; - always @ (*) begin - _zz_113[19] = _zz_112; - _zz_113[18] = _zz_112; - _zz_113[17] = _zz_112; - _zz_113[16] = _zz_112; - _zz_113[15] = _zz_112; - _zz_113[14] = _zz_112; - _zz_113[13] = _zz_112; - _zz_113[12] = _zz_112; - _zz_113[11] = _zz_112; - _zz_113[10] = _zz_112; - _zz_113[9] = _zz_112; - _zz_113[8] = _zz_112; - _zz_113[7] = _zz_112; - _zz_113[6] = _zz_112; - _zz_113[5] = _zz_112; - _zz_113[4] = _zz_112; - _zz_113[3] = _zz_112; - _zz_113[2] = _zz_112; - _zz_113[1] = _zz_112; - _zz_113[0] = _zz_112; - end - - assign _zz_114 = _zz_319[11]; - always @ (*) begin - _zz_115[19] = _zz_114; - _zz_115[18] = _zz_114; - _zz_115[17] = _zz_114; - _zz_115[16] = _zz_114; - _zz_115[15] = _zz_114; - _zz_115[14] = _zz_114; - _zz_115[13] = _zz_114; - _zz_115[12] = _zz_114; - _zz_115[11] = _zz_114; - _zz_115[10] = _zz_114; - _zz_115[9] = _zz_114; - _zz_115[8] = _zz_114; - _zz_115[7] = _zz_114; - _zz_115[6] = _zz_114; - _zz_115[5] = _zz_114; - _zz_115[4] = _zz_114; - _zz_115[3] = _zz_114; - _zz_115[2] = _zz_114; - _zz_115[1] = _zz_114; - _zz_115[0] = _zz_114; + assign _zz_111 = _zz_317[11]; + always @ (*) begin + _zz_112[19] = _zz_111; + _zz_112[18] = _zz_111; + _zz_112[17] = _zz_111; + _zz_112[16] = _zz_111; + _zz_112[15] = _zz_111; + _zz_112[14] = _zz_111; + _zz_112[13] = _zz_111; + _zz_112[12] = _zz_111; + _zz_112[11] = _zz_111; + _zz_112[10] = _zz_111; + _zz_112[9] = _zz_111; + _zz_112[8] = _zz_111; + _zz_112[7] = _zz_111; + _zz_112[6] = _zz_111; + _zz_112[5] = _zz_111; + _zz_112[4] = _zz_111; + _zz_112[3] = _zz_111; + _zz_112[2] = _zz_111; + _zz_112[1] = _zz_111; + _zz_112[0] = _zz_111; + end + + assign _zz_113 = _zz_318[11]; + always @ (*) begin + _zz_114[19] = _zz_113; + _zz_114[18] = _zz_113; + _zz_114[17] = _zz_113; + _zz_114[16] = _zz_113; + _zz_114[15] = _zz_113; + _zz_114[14] = _zz_113; + _zz_114[13] = _zz_113; + _zz_114[12] = _zz_113; + _zz_114[11] = _zz_113; + _zz_114[10] = _zz_113; + _zz_114[9] = _zz_113; + _zz_114[8] = _zz_113; + _zz_114[7] = _zz_113; + _zz_114[6] = _zz_113; + _zz_114[5] = _zz_113; + _zz_114[4] = _zz_113; + _zz_114[3] = _zz_113; + _zz_114[2] = _zz_113; + _zz_114[1] = _zz_113; + _zz_114[0] = _zz_113; end always @ (*) begin case(execute_SRC2_CTRL) `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_116 = execute_RS2; + _zz_115 = execute_RS2; end `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_116 = {_zz_113,execute_INSTRUCTION[31 : 20]}; + _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; end `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_116 = {_zz_115,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_116 = _zz_41; + _zz_115 = _zz_41; end endcase end always @ (*) begin - execute_SrcPlugin_addSub = _zz_320; + execute_SrcPlugin_addSub = _zz_319; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3828,246 +3905,246 @@ module VexRiscv ( assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; always @ (*) begin - _zz_117[0] = execute_SRC1[31]; - _zz_117[1] = execute_SRC1[30]; - _zz_117[2] = execute_SRC1[29]; - _zz_117[3] = execute_SRC1[28]; - _zz_117[4] = execute_SRC1[27]; - _zz_117[5] = execute_SRC1[26]; - _zz_117[6] = execute_SRC1[25]; - _zz_117[7] = execute_SRC1[24]; - _zz_117[8] = execute_SRC1[23]; - _zz_117[9] = execute_SRC1[22]; - _zz_117[10] = execute_SRC1[21]; - _zz_117[11] = execute_SRC1[20]; - _zz_117[12] = execute_SRC1[19]; - _zz_117[13] = execute_SRC1[18]; - _zz_117[14] = execute_SRC1[17]; - _zz_117[15] = execute_SRC1[16]; - _zz_117[16] = execute_SRC1[15]; - _zz_117[17] = execute_SRC1[14]; - _zz_117[18] = execute_SRC1[13]; - _zz_117[19] = execute_SRC1[12]; - _zz_117[20] = execute_SRC1[11]; - _zz_117[21] = execute_SRC1[10]; - _zz_117[22] = execute_SRC1[9]; - _zz_117[23] = execute_SRC1[8]; - _zz_117[24] = execute_SRC1[7]; - _zz_117[25] = execute_SRC1[6]; - _zz_117[26] = execute_SRC1[5]; - _zz_117[27] = execute_SRC1[4]; - _zz_117[28] = execute_SRC1[3]; - _zz_117[29] = execute_SRC1[2]; - _zz_117[30] = execute_SRC1[1]; - _zz_117[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_117 : execute_SRC1); - always @ (*) begin - _zz_118[0] = memory_SHIFT_RIGHT[31]; - _zz_118[1] = memory_SHIFT_RIGHT[30]; - _zz_118[2] = memory_SHIFT_RIGHT[29]; - _zz_118[3] = memory_SHIFT_RIGHT[28]; - _zz_118[4] = memory_SHIFT_RIGHT[27]; - _zz_118[5] = memory_SHIFT_RIGHT[26]; - _zz_118[6] = memory_SHIFT_RIGHT[25]; - _zz_118[7] = memory_SHIFT_RIGHT[24]; - _zz_118[8] = memory_SHIFT_RIGHT[23]; - _zz_118[9] = memory_SHIFT_RIGHT[22]; - _zz_118[10] = memory_SHIFT_RIGHT[21]; - _zz_118[11] = memory_SHIFT_RIGHT[20]; - _zz_118[12] = memory_SHIFT_RIGHT[19]; - _zz_118[13] = memory_SHIFT_RIGHT[18]; - _zz_118[14] = memory_SHIFT_RIGHT[17]; - _zz_118[15] = memory_SHIFT_RIGHT[16]; - _zz_118[16] = memory_SHIFT_RIGHT[15]; - _zz_118[17] = memory_SHIFT_RIGHT[14]; - _zz_118[18] = memory_SHIFT_RIGHT[13]; - _zz_118[19] = memory_SHIFT_RIGHT[12]; - _zz_118[20] = memory_SHIFT_RIGHT[11]; - _zz_118[21] = memory_SHIFT_RIGHT[10]; - _zz_118[22] = memory_SHIFT_RIGHT[9]; - _zz_118[23] = memory_SHIFT_RIGHT[8]; - _zz_118[24] = memory_SHIFT_RIGHT[7]; - _zz_118[25] = memory_SHIFT_RIGHT[6]; - _zz_118[26] = memory_SHIFT_RIGHT[5]; - _zz_118[27] = memory_SHIFT_RIGHT[4]; - _zz_118[28] = memory_SHIFT_RIGHT[3]; - _zz_118[29] = memory_SHIFT_RIGHT[2]; - _zz_118[30] = memory_SHIFT_RIGHT[1]; - _zz_118[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_119 = 1'b0; - if(_zz_250)begin - if(_zz_251)begin - if(_zz_124)begin - _zz_119 = 1'b1; + _zz_116[0] = execute_SRC1[31]; + _zz_116[1] = execute_SRC1[30]; + _zz_116[2] = execute_SRC1[29]; + _zz_116[3] = execute_SRC1[28]; + _zz_116[4] = execute_SRC1[27]; + _zz_116[5] = execute_SRC1[26]; + _zz_116[6] = execute_SRC1[25]; + _zz_116[7] = execute_SRC1[24]; + _zz_116[8] = execute_SRC1[23]; + _zz_116[9] = execute_SRC1[22]; + _zz_116[10] = execute_SRC1[21]; + _zz_116[11] = execute_SRC1[20]; + _zz_116[12] = execute_SRC1[19]; + _zz_116[13] = execute_SRC1[18]; + _zz_116[14] = execute_SRC1[17]; + _zz_116[15] = execute_SRC1[16]; + _zz_116[16] = execute_SRC1[15]; + _zz_116[17] = execute_SRC1[14]; + _zz_116[18] = execute_SRC1[13]; + _zz_116[19] = execute_SRC1[12]; + _zz_116[20] = execute_SRC1[11]; + _zz_116[21] = execute_SRC1[10]; + _zz_116[22] = execute_SRC1[9]; + _zz_116[23] = execute_SRC1[8]; + _zz_116[24] = execute_SRC1[7]; + _zz_116[25] = execute_SRC1[6]; + _zz_116[26] = execute_SRC1[5]; + _zz_116[27] = execute_SRC1[4]; + _zz_116[28] = execute_SRC1[3]; + _zz_116[29] = execute_SRC1[2]; + _zz_116[30] = execute_SRC1[1]; + _zz_116[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); + always @ (*) begin + _zz_117[0] = memory_SHIFT_RIGHT[31]; + _zz_117[1] = memory_SHIFT_RIGHT[30]; + _zz_117[2] = memory_SHIFT_RIGHT[29]; + _zz_117[3] = memory_SHIFT_RIGHT[28]; + _zz_117[4] = memory_SHIFT_RIGHT[27]; + _zz_117[5] = memory_SHIFT_RIGHT[26]; + _zz_117[6] = memory_SHIFT_RIGHT[25]; + _zz_117[7] = memory_SHIFT_RIGHT[24]; + _zz_117[8] = memory_SHIFT_RIGHT[23]; + _zz_117[9] = memory_SHIFT_RIGHT[22]; + _zz_117[10] = memory_SHIFT_RIGHT[21]; + _zz_117[11] = memory_SHIFT_RIGHT[20]; + _zz_117[12] = memory_SHIFT_RIGHT[19]; + _zz_117[13] = memory_SHIFT_RIGHT[18]; + _zz_117[14] = memory_SHIFT_RIGHT[17]; + _zz_117[15] = memory_SHIFT_RIGHT[16]; + _zz_117[16] = memory_SHIFT_RIGHT[15]; + _zz_117[17] = memory_SHIFT_RIGHT[14]; + _zz_117[18] = memory_SHIFT_RIGHT[13]; + _zz_117[19] = memory_SHIFT_RIGHT[12]; + _zz_117[20] = memory_SHIFT_RIGHT[11]; + _zz_117[21] = memory_SHIFT_RIGHT[10]; + _zz_117[22] = memory_SHIFT_RIGHT[9]; + _zz_117[23] = memory_SHIFT_RIGHT[8]; + _zz_117[24] = memory_SHIFT_RIGHT[7]; + _zz_117[25] = memory_SHIFT_RIGHT[6]; + _zz_117[26] = memory_SHIFT_RIGHT[5]; + _zz_117[27] = memory_SHIFT_RIGHT[4]; + _zz_117[28] = memory_SHIFT_RIGHT[3]; + _zz_117[29] = memory_SHIFT_RIGHT[2]; + _zz_117[30] = memory_SHIFT_RIGHT[1]; + _zz_117[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_118 = 1'b0; + if(_zz_247)begin + if(_zz_248)begin + if(_zz_123)begin + _zz_118 = 1'b1; end end end - if(_zz_252)begin - if(_zz_253)begin - if(_zz_126)begin - _zz_119 = 1'b1; + if(_zz_249)begin + if(_zz_250)begin + if(_zz_125)begin + _zz_118 = 1'b1; end end end - if(_zz_254)begin - if(_zz_255)begin - if(_zz_128)begin - _zz_119 = 1'b1; + if(_zz_251)begin + if(_zz_252)begin + if(_zz_127)begin + _zz_118 = 1'b1; end end end if((! decode_RS1_USE))begin - _zz_119 = 1'b0; + _zz_118 = 1'b0; end end always @ (*) begin - _zz_120 = 1'b0; - if(_zz_250)begin - if(_zz_251)begin - if(_zz_125)begin - _zz_120 = 1'b1; + _zz_119 = 1'b0; + if(_zz_247)begin + if(_zz_248)begin + if(_zz_124)begin + _zz_119 = 1'b1; end end end - if(_zz_252)begin - if(_zz_253)begin - if(_zz_127)begin - _zz_120 = 1'b1; + if(_zz_249)begin + if(_zz_250)begin + if(_zz_126)begin + _zz_119 = 1'b1; end end end - if(_zz_254)begin - if(_zz_255)begin - if(_zz_129)begin - _zz_120 = 1'b1; + if(_zz_251)begin + if(_zz_252)begin + if(_zz_128)begin + _zz_119 = 1'b1; end end end if((! decode_RS2_USE))begin - _zz_120 = 1'b0; + _zz_119 = 1'b0; end end - assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_125 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_127 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_129 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_130 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_130 == 3'b000)) begin - _zz_131 = execute_BranchPlugin_eq; - end else if((_zz_130 == 3'b001)) begin - _zz_131 = (! execute_BranchPlugin_eq); - end else if((((_zz_130 & 3'b101) == 3'b101))) begin - _zz_131 = (! execute_SRC_LESS); + assign _zz_129 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_129 == 3'b000)) begin + _zz_130 = execute_BranchPlugin_eq; + end else if((_zz_129 == 3'b001)) begin + _zz_130 = (! execute_BranchPlugin_eq); + end else if((((_zz_129 & 3'b101) == 3'b101))) begin + _zz_130 = (! execute_SRC_LESS); end else begin - _zz_131 = execute_SRC_LESS; + _zz_130 = execute_SRC_LESS; end end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_132 = 1'b0; + _zz_131 = 1'b0; end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_132 = 1'b1; + _zz_131 = 1'b1; end `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_132 = 1'b1; + _zz_131 = 1'b1; end default : begin - _zz_132 = _zz_131; + _zz_131 = _zz_130; end endcase end - assign _zz_133 = _zz_327[11]; - always @ (*) begin - _zz_134[19] = _zz_133; - _zz_134[18] = _zz_133; - _zz_134[17] = _zz_133; - _zz_134[16] = _zz_133; - _zz_134[15] = _zz_133; - _zz_134[14] = _zz_133; - _zz_134[13] = _zz_133; - _zz_134[12] = _zz_133; - _zz_134[11] = _zz_133; - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; - end - - assign _zz_135 = _zz_328[19]; - always @ (*) begin - _zz_136[10] = _zz_135; - _zz_136[9] = _zz_135; - _zz_136[8] = _zz_135; - _zz_136[7] = _zz_135; - _zz_136[6] = _zz_135; - _zz_136[5] = _zz_135; - _zz_136[4] = _zz_135; - _zz_136[3] = _zz_135; - _zz_136[2] = _zz_135; - _zz_136[1] = _zz_135; - _zz_136[0] = _zz_135; - end - - assign _zz_137 = _zz_329[11]; - always @ (*) begin - _zz_138[18] = _zz_137; - _zz_138[17] = _zz_137; - _zz_138[16] = _zz_137; - _zz_138[15] = _zz_137; - _zz_138[14] = _zz_137; - _zz_138[13] = _zz_137; - _zz_138[12] = _zz_137; - _zz_138[11] = _zz_137; - _zz_138[10] = _zz_137; - _zz_138[9] = _zz_137; - _zz_138[8] = _zz_137; - _zz_138[7] = _zz_137; - _zz_138[6] = _zz_137; - _zz_138[5] = _zz_137; - _zz_138[4] = _zz_137; - _zz_138[3] = _zz_137; - _zz_138[2] = _zz_137; - _zz_138[1] = _zz_137; - _zz_138[0] = _zz_137; + assign _zz_132 = _zz_326[11]; + always @ (*) begin + _zz_133[19] = _zz_132; + _zz_133[18] = _zz_132; + _zz_133[17] = _zz_132; + _zz_133[16] = _zz_132; + _zz_133[15] = _zz_132; + _zz_133[14] = _zz_132; + _zz_133[13] = _zz_132; + _zz_133[12] = _zz_132; + _zz_133[11] = _zz_132; + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; + end + + assign _zz_134 = _zz_327[19]; + always @ (*) begin + _zz_135[10] = _zz_134; + _zz_135[9] = _zz_134; + _zz_135[8] = _zz_134; + _zz_135[7] = _zz_134; + _zz_135[6] = _zz_134; + _zz_135[5] = _zz_134; + _zz_135[4] = _zz_134; + _zz_135[3] = _zz_134; + _zz_135[2] = _zz_134; + _zz_135[1] = _zz_134; + _zz_135[0] = _zz_134; + end + + assign _zz_136 = _zz_328[11]; + always @ (*) begin + _zz_137[18] = _zz_136; + _zz_137[17] = _zz_136; + _zz_137[16] = _zz_136; + _zz_137[15] = _zz_136; + _zz_137[14] = _zz_136; + _zz_137[13] = _zz_136; + _zz_137[12] = _zz_136; + _zz_137[11] = _zz_136; + _zz_137[10] = _zz_136; + _zz_137[9] = _zz_136; + _zz_137[8] = _zz_136; + _zz_137[7] = _zz_136; + _zz_137[6] = _zz_136; + _zz_137[5] = _zz_136; + _zz_137[4] = _zz_136; + _zz_137[3] = _zz_136; + _zz_137[2] = _zz_136; + _zz_137[1] = _zz_136; + _zz_137[0] = _zz_136; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_139 = (_zz_330[1] ^ execute_RS1[1]); + _zz_138 = (_zz_329[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_139 = _zz_331[1]; + _zz_138 = _zz_330[1]; end default : begin - _zz_139 = _zz_332[1]; + _zz_138 = _zz_331[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_139); + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin @@ -4079,80 +4156,80 @@ module VexRiscv ( endcase end - assign _zz_140 = _zz_333[11]; + assign _zz_139 = _zz_332[11]; always @ (*) begin - _zz_141[19] = _zz_140; - _zz_141[18] = _zz_140; - _zz_141[17] = _zz_140; - _zz_141[16] = _zz_140; - _zz_141[15] = _zz_140; - _zz_141[14] = _zz_140; - _zz_141[13] = _zz_140; - _zz_141[12] = _zz_140; - _zz_141[11] = _zz_140; - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; + _zz_140[19] = _zz_139; + _zz_140[18] = _zz_139; + _zz_140[17] = _zz_139; + _zz_140[16] = _zz_139; + _zz_140[15] = _zz_139; + _zz_140[14] = _zz_139; + _zz_140[13] = _zz_139; + _zz_140[12] = _zz_139; + _zz_140[11] = _zz_139; + _zz_140[10] = _zz_139; + _zz_140[9] = _zz_139; + _zz_140[8] = _zz_139; + _zz_140[7] = _zz_139; + _zz_140[6] = _zz_139; + _zz_140[5] = _zz_139; + _zz_140[4] = _zz_139; + _zz_140[3] = _zz_139; + _zz_140[2] = _zz_139; + _zz_140[1] = _zz_139; + _zz_140[0] = _zz_139; end always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_141,execute_INSTRUCTION[31 : 20]}; + execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_143,{{{_zz_564,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_145,{{{_zz_565,_zz_566},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_570,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_571,_zz_572},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_336}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_335}; end end endcase end - assign _zz_142 = _zz_334[19]; - always @ (*) begin - _zz_143[10] = _zz_142; - _zz_143[9] = _zz_142; - _zz_143[8] = _zz_142; - _zz_143[7] = _zz_142; - _zz_143[6] = _zz_142; - _zz_143[5] = _zz_142; - _zz_143[4] = _zz_142; - _zz_143[3] = _zz_142; - _zz_143[2] = _zz_142; - _zz_143[1] = _zz_142; - _zz_143[0] = _zz_142; - end - - assign _zz_144 = _zz_335[11]; - always @ (*) begin - _zz_145[18] = _zz_144; - _zz_145[17] = _zz_144; - _zz_145[16] = _zz_144; - _zz_145[15] = _zz_144; - _zz_145[14] = _zz_144; - _zz_145[13] = _zz_144; - _zz_145[12] = _zz_144; - _zz_145[11] = _zz_144; - _zz_145[10] = _zz_144; - _zz_145[9] = _zz_144; - _zz_145[8] = _zz_144; - _zz_145[7] = _zz_144; - _zz_145[6] = _zz_144; - _zz_145[5] = _zz_144; - _zz_145[4] = _zz_144; - _zz_145[3] = _zz_144; - _zz_145[2] = _zz_144; - _zz_145[1] = _zz_144; - _zz_145[0] = _zz_144; + assign _zz_141 = _zz_333[19]; + always @ (*) begin + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; + end + + assign _zz_143 = _zz_334[11]; + always @ (*) begin + _zz_144[18] = _zz_143; + _zz_144[17] = _zz_143; + _zz_144[16] = _zz_143; + _zz_144[15] = _zz_143; + _zz_144[14] = _zz_143; + _zz_144[13] = _zz_143; + _zz_144[12] = _zz_143; + _zz_144[11] = _zz_143; + _zz_144[10] = _zz_143; + _zz_144[9] = _zz_143; + _zz_144[8] = _zz_143; + _zz_144[7] = _zz_143; + _zz_144[6] = _zz_143; + _zz_144[5] = _zz_143; + _zz_144[4] = _zz_143; + _zz_144[3] = _zz_143; + _zz_144[2] = _zz_143; + _zz_144[1] = _zz_143; + _zz_144[0] = _zz_143; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -4175,20 +4252,18 @@ module VexRiscv ( end end - assign _zz_146 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_147 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_148 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_149 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_150 = _zz_337[0]; - assign _zz_151 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_152 = _zz_339[0]; - assign _zz_153 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_154 = _zz_341[0]; + assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_149 = _zz_336[0]; + assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_151 = _zz_338[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_238)begin + if(_zz_237)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4198,7 +4273,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_241)begin + if(_zz_240)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -4208,7 +4283,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_243)begin + if(CfuPlugin_joinException_valid)begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end if(memory_arbitration_isFlushed)begin @@ -4218,6 +4293,9 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end if(writeBack_arbitration_isFlushed)begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end @@ -4280,6 +4358,11 @@ module VexRiscv ( assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); always @ (*) begin execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end if(execute_CsrPlugin_csr_3857)begin if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; @@ -4359,111 +4442,47 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_csr_3008)begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2822)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end + if(_zz_253)begin + execute_CsrPlugin_illegalAccess = 1'b1; end - if(execute_CsrPlugin_csr_2824)begin + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2826)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2828)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2830)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2832)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2834)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CSR_WRITE_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_3008)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(_zz_256)begin - execute_CsrPlugin_illegalAccess = 1'b1; - end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - - always @ (*) begin - execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin - execute_CsrPlugin_illegalInstruction = 1'b1; + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; end end end always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_257)begin + if(_zz_254)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_258)begin + if(_zz_255)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_257)begin + if(_zz_254)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_258)begin + if(_zz_255)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4478,14 +4497,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_256)begin + if(_zz_253)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_256)begin + if(_zz_253)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4494,7 +4513,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_271) + case(_zz_268) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4507,49 +4526,49 @@ module VexRiscv ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_343; + assign execute_CfuPlugin_functionsIds_0 = _zz_340; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_171 = _zz_344[7]; - always @ (*) begin - _zz_172[23] = _zz_171; - _zz_172[22] = _zz_171; - _zz_172[21] = _zz_171; - _zz_172[20] = _zz_171; - _zz_172[19] = _zz_171; - _zz_172[18] = _zz_171; - _zz_172[17] = _zz_171; - _zz_172[16] = _zz_171; - _zz_172[15] = _zz_171; - _zz_172[14] = _zz_171; - _zz_172[13] = _zz_171; - _zz_172[12] = _zz_171; - _zz_172[11] = _zz_171; - _zz_172[10] = _zz_171; - _zz_172[9] = _zz_171; - _zz_172[8] = _zz_171; - _zz_172[7] = _zz_171; - _zz_172[6] = _zz_171; - _zz_172[5] = _zz_171; - _zz_172[4] = _zz_171; - _zz_172[3] = _zz_171; - _zz_172[2] = _zz_171; - _zz_172[1] = _zz_171; - _zz_172[0] = _zz_171; + assign _zz_152 = _zz_341[7]; + always @ (*) begin + _zz_153[23] = _zz_152; + _zz_153[22] = _zz_152; + _zz_153[21] = _zz_152; + _zz_153[20] = _zz_152; + _zz_153[19] = _zz_152; + _zz_153[18] = _zz_152; + _zz_153[17] = _zz_152; + _zz_153[16] = _zz_152; + _zz_153[15] = _zz_152; + _zz_153[14] = _zz_152; + _zz_153[13] = _zz_152; + _zz_153[12] = _zz_152; + _zz_153[11] = _zz_152; + _zz_153[10] = _zz_152; + _zz_153[9] = _zz_152; + _zz_153[8] = _zz_152; + _zz_153[7] = _zz_152; + _zz_153[6] = _zz_152; + _zz_153[5] = _zz_152; + _zz_153[4] = _zz_152; + _zz_153[3] = _zz_152; + _zz_153[2] = _zz_152; + _zz_153[1] = _zz_152; + _zz_153[0] = _zz_152; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_173 = execute_RS2; + _zz_154 = execute_RS2; end default : begin - _zz_173 = {_zz_172,execute_INSTRUCTION[31 : 24]}; + _zz_154 = {_zz_153,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_173; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_154; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4575,7 +4594,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_259) + case(_zz_256) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4589,7 +4608,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_259) + case(_zz_256) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4608,12 +4627,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_345) + $signed(_zz_346)); + assign writeBack_MulPlugin_result = ($signed(_zz_342) + $signed(_zz_343)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_233)begin - if(_zz_260)begin + if(_zz_232)begin + if(_zz_257)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4621,7 +4640,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_261)begin + if(_zz_258)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4632,32 +4651,32 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_350); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_347); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_174 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_174[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_351); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_352 : _zz_353); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_354[31:0]; - assign _zz_175 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_176 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_177 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_155 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_155[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_348); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_349 : _zz_350); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_351[31:0]; + assign _zz_156 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_157 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_158 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_178[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_178[31 : 0] = execute_RS1; + _zz_159[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_159[31 : 0] = execute_RS1; end - assign _zz_180 = (_zz_179 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_180 != 32'h0); + assign _zz_161 = (_zz_160 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_161 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_262) + case(_zz_259) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4671,7 +4690,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_181))begin + if((! _zz_162))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4683,7 +4702,7 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_262) + case(_zz_259) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4750,7 +4769,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_182) + case(_zz_163) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4760,287 +4779,218 @@ module VexRiscv ( end always @ (*) begin - _zz_183 = 32'h0; + _zz_164 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_164[12 : 0] = 13'h1000; + _zz_164[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_165 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_183[3 : 0] = 4'b1011; + _zz_165[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_166 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_184[4 : 0] = 5'h16; + _zz_166[4 : 0] = 5'h16; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_167 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_185[5 : 0] = 6'h21; + _zz_167[5 : 0] = 6'h21; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_168 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_186[31 : 30] = CsrPlugin_misa_base; - _zz_186[25 : 0] = CsrPlugin_misa_extensions; + _zz_168[31 : 30] = CsrPlugin_misa_base; + _zz_168[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_187 = 32'h0; + _zz_169 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_187[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_187[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_187[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_169[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_169[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_169[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_188 = 32'h0; + _zz_170 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_188[11 : 11] = CsrPlugin_mip_MEIP; - _zz_188[7 : 7] = CsrPlugin_mip_MTIP; - _zz_188[3 : 3] = CsrPlugin_mip_MSIP; + _zz_170[11 : 11] = CsrPlugin_mip_MEIP; + _zz_170[7 : 7] = CsrPlugin_mip_MTIP; + _zz_170[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_189 = 32'h0; + _zz_171 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_189[11 : 11] = CsrPlugin_mie_MEIE; - _zz_189[7 : 7] = CsrPlugin_mie_MTIE; - _zz_189[3 : 3] = CsrPlugin_mie_MSIE; + _zz_171[11 : 11] = CsrPlugin_mie_MEIE; + _zz_171[7 : 7] = CsrPlugin_mie_MTIE; + _zz_171[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_190 = 32'h0; + _zz_172 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_190[31 : 2] = CsrPlugin_mtvec_base; - _zz_190[1 : 0] = CsrPlugin_mtvec_mode; + _zz_172[31 : 2] = CsrPlugin_mtvec_base; + _zz_172[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_191 = 32'h0; + _zz_173 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_191[31 : 0] = CsrPlugin_mepc; + _zz_173[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_192 = 32'h0; + _zz_174 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_192[31 : 0] = CsrPlugin_mscratch; + _zz_174[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_193 = 32'h0; + _zz_175 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_193[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_193[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_175[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_175[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_194 = 32'h0; + _zz_176 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_194[31 : 0] = CsrPlugin_mtval; + _zz_176[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_195 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_195[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_177[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_196 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_196[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_178[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_197 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_197[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_179[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_198 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_198[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_180[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_199 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_199[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_181[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_200 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_200[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_182[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_201 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_201[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_183[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_202 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_202[31 : 0] = CsrPlugin_minstret[63 : 32]; - end - end - - always @ (*) begin - _zz_203 = 32'h0; - if(execute_CsrPlugin_csr_2820)begin - _zz_203[31 : 0] = _zz_155; - end - end - - always @ (*) begin - _zz_204 = 32'h0; - if(execute_CsrPlugin_csr_2822)begin - _zz_204[31 : 0] = _zz_157; - end - end - - always @ (*) begin - _zz_205 = 32'h0; - if(execute_CsrPlugin_csr_2824)begin - _zz_205[31 : 0] = _zz_159; - end - end - - always @ (*) begin - _zz_206 = 32'h0; - if(execute_CsrPlugin_csr_2826)begin - _zz_206[31 : 0] = _zz_161; - end - end - - always @ (*) begin - _zz_207 = 32'h0; - if(execute_CsrPlugin_csr_2828)begin - _zz_207[31 : 0] = _zz_163; - end - end - - always @ (*) begin - _zz_208 = 32'h0; - if(execute_CsrPlugin_csr_2830)begin - _zz_208[31 : 0] = _zz_165; - end - end - - always @ (*) begin - _zz_209 = 32'h0; - if(execute_CsrPlugin_csr_2832)begin - _zz_209[31 : 0] = _zz_167; - end - end - - always @ (*) begin - _zz_210 = 32'h0; - if(execute_CsrPlugin_csr_2834)begin - _zz_210[31 : 0] = _zz_169; + _zz_184[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_211 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_211[31 : 0] = _zz_179; + _zz_185[31 : 0] = _zz_160; end end always @ (*) begin - _zz_212 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_212[31 : 0] = _zz_180; + _zz_186[31 : 0] = _zz_161; end end - assign execute_CsrPlugin_readData = (((((_zz_183 | _zz_184) | (_zz_185 | _zz_567)) | ((_zz_186 | _zz_187) | (_zz_188 | _zz_189))) | (((_zz_190 | _zz_191) | (_zz_192 | _zz_193)) | ((_zz_194 | _zz_195) | (_zz_196 | _zz_197)))) | ((((_zz_198 | _zz_199) | (_zz_200 | _zz_201)) | ((_zz_202 | _zz_203) | (_zz_204 | _zz_205))) | (((_zz_206 | _zz_207) | (_zz_208 | _zz_209)) | ((_zz_210 | _zz_211) | _zz_212)))); - assign iBusWishbone_ADR = {_zz_371,_zz_213}; - assign iBusWishbone_CTI = ((_zz_213 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_164 | _zz_165) | (_zz_166 | _zz_167)) | ((_zz_573 | _zz_168) | (_zz_169 | _zz_170))) | (((_zz_171 | _zz_172) | (_zz_173 | _zz_174)) | ((_zz_175 | _zz_176) | (_zz_177 | _zz_178)))) | (((_zz_179 | _zz_180) | (_zz_181 | _zz_182)) | ((_zz_183 | _zz_184) | (_zz_185 | _zz_186)))); + assign iBusWishbone_ADR = {_zz_368,_zz_187}; + assign iBusWishbone_CTI = ((_zz_187 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_263)begin + if(_zz_260)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_263)begin + if(_zz_260)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_214; + assign iBus_rsp_valid = _zz_188; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; - assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; - assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; - assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; - assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; - assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; - assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); - assign dBusWishbone_CTI = 3'b000; + assign _zz_194 = (dBus_cmd_payload_length != 3'b000); + assign _zz_190 = dBus_cmd_valid; + assign _zz_192 = dBus_cmd_payload_wr; + assign _zz_193 = (_zz_189 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_191 && (_zz_192 || _zz_193)); + assign dBusWishbone_ADR = ((_zz_194 ? {{dBus_cmd_payload_address[31 : 5],_zz_189},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_194 ? (_zz_193 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - always @ (*) begin - case(dBus_cmd_halfPipe_payload_size) - 2'b00 : begin - _zz_215 = 4'b0001; - end - 2'b01 : begin - _zz_215 = 4'b0011; - end - default : begin - _zz_215 = 4'b1111; - end - endcase - end - - always @ (*) begin - dBusWishbone_SEL = (_zz_215 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - if((! dBus_cmd_halfPipe_payload_wr))begin - dBusWishbone_SEL = 4'b1111; - end - end - - assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; - assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; - assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); - assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; - assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; - assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); - assign dBus_rsp_data = dBusWishbone_DAT_MISO; - assign dBus_rsp_error = 1'b0; + assign dBusWishbone_SEL = (_zz_192 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_192; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_191 = (_zz_190 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_190; + assign dBusWishbone_STB = _zz_190; + assign dBus_rsp_valid = _zz_195; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; @@ -5056,8 +5006,12 @@ module VexRiscv ( IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; IBusCachedPlugin_rspCounter <= _zz_87; IBusCachedPlugin_rspCounter <= 32'h0; - _zz_109 <= 1'b1; - _zz_121 <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_88; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_108 <= 1'b1; + _zz_120 <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -5081,16 +5035,16 @@ module VexRiscv ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_179 <= 32'h0; + _zz_160 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_182 <= 3'b000; + _zz_163 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_213 <= 3'b000; - _zz_214 <= 1'b0; - dBus_cmd_halfPipe_regs_valid <= 1'b0; - dBus_cmd_halfPipe_regs_ready <= 1'b1; + _zz_187 <= 3'b000; + _zz_188 <= 1'b0; + _zz_189 <= 3'b000; + _zz_195 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5168,28 +5122,20 @@ module VexRiscv ( if(iBus_rsp_valid)begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))); - `else - if(!(! (((dBus_rsp_ready && memory_MEMORY_ENABLE) && memory_arbitration_isValid) && memory_arbitration_isStuck))) begin - $display("FAILURE DBusSimplePlugin doesn't allow memory stage stall when read happend"); - $finish; - end - `endif - `endif - `ifndef SYNTHESIS - `ifdef FORMAL - assert((! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))); - `else - if(!(! (((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_STORE)) && writeBack_arbitration_isStuck))) begin - $display("FAILURE DBusSimplePlugin doesn't allow writeback stage stall when read happend"); - $finish; - end - `endif - `endif - _zz_109 <= 1'b0; - _zz_121 <= (_zz_47 && writeBack_arbitration_isFiring); + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(_zz_261)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_108 <= 1'b0; + _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); if((! decode_arbitration_isStuck))begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin @@ -5211,14 +5157,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_264)begin - if(_zz_265)begin + if(_zz_262)begin + if(_zz_263)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_266)begin + if(_zz_264)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_267)begin + if(_zz_265)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5243,7 +5189,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_244)begin + if(_zz_242)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5254,8 +5200,8 @@ module VexRiscv ( end endcase end - if(_zz_245)begin - case(_zz_247) + if(_zz_243)begin + case(_zz_245) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5265,7 +5211,7 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_148,{_zz_147,_zz_146}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); if(execute_CfuPlugin_schedule)begin execute_CfuPlugin_hold <= 1'b1; end @@ -5281,7 +5227,7 @@ module VexRiscv ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_268)begin + if(_zz_266)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; @@ -5306,25 +5252,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_182) + case(_zz_163) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_182 <= 3'b001; + _zz_163 <= 3'b001; end end 3'b001 : begin - _zz_182 <= 3'b010; + _zz_163 <= 3'b010; end 3'b010 : begin - _zz_182 <= 3'b011; + _zz_163 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_182 <= 3'b100; + _zz_163 <= 3'b100; end end 3'b100 : begin - _zz_182 <= 3'b000; + _zz_163 <= 3'b000; end default : begin end @@ -5338,35 +5284,35 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_364[0]; - CsrPlugin_mstatus_MIE <= _zz_365[0]; + CsrPlugin_mstatus_MPIE <= _zz_361[0]; + CsrPlugin_mstatus_MIE <= _zz_362[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_367[0]; - CsrPlugin_mie_MTIE <= _zz_368[0]; - CsrPlugin_mie_MSIE <= _zz_369[0]; + CsrPlugin_mie_MEIE <= _zz_364[0]; + CsrPlugin_mie_MTIE <= _zz_365[0]; + CsrPlugin_mie_MSIE <= _zz_366[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_179 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_263)begin + if(_zz_260)begin if(iBusWishbone_ACK)begin - _zz_213 <= (_zz_213 + 3'b001); + _zz_187 <= (_zz_187 + 3'b001); end end - _zz_214 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_269)begin - dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; - dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); - end else begin - dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); - dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + _zz_188 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_190 && _zz_191))begin + _zz_189 <= (_zz_189 + 3'b001); + if(_zz_193)begin + _zz_189 <= 3'b000; + end end + _zz_195 <= ((_zz_190 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5380,8 +5326,26 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - _zz_122 <= _zz_46[11 : 7]; - _zz_123 <= _zz_57; + if(_zz_261)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + _zz_121 <= _zz_46[11 : 7]; + _zz_122 <= _zz_57; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; @@ -5389,33 +5353,37 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_238)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_237)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(_zz_241)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_154 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_154 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_240)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(_zz_243)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_152 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_152 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; end - if(_zz_264)begin - if(_zz_265)begin + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_262)begin + if(_zz_263)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_266)begin + if(_zz_264)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_267)begin + if(_zz_265)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_244)begin + if(_zz_242)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5429,31 +5397,7 @@ module VexRiscv ( end endcase end - if(_zz_156[0])begin - _zz_155 <= (_zz_155 + 32'h00000001); - end - if(_zz_158[0])begin - _zz_157 <= (_zz_157 + 32'h00000001); - end - if(_zz_160[0])begin - _zz_159 <= (_zz_159 + 32'h00000001); - end - if(_zz_162[0])begin - _zz_161 <= (_zz_161 + 32'h00000001); - end - if(_zz_164[0])begin - _zz_163 <= (_zz_163 + 32'h00000001); - end - if(_zz_166[0])begin - _zz_165 <= (_zz_165 + 32'h00000001); - end - if(_zz_168[0])begin - _zz_167 <= (_zz_167 + 32'h00000001); - end - if(_zz_170[0])begin - _zz_169 <= (_zz_169 + 32'h00000001); - end - if(_zz_268)begin + if(_zz_266)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5463,20 +5407,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_233)begin - if(_zz_260)begin + if(_zz_232)begin + if(_zz_257)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_355[31:0]; + memory_DivPlugin_div_result <= _zz_352[31:0]; end end end - if(_zz_261)begin + if(_zz_258)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_177 ? (~ _zz_178) : _zz_178) + _zz_361); - memory_DivPlugin_rs2 <= ((_zz_176 ? (~ execute_RS2) : execute_RS2) + _zz_363); - memory_DivPlugin_div_needRevert <= ((_zz_177 ^ (_zz_176 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_158 ? (~ _zz_159) : _zz_159) + _zz_358); + memory_DivPlugin_rs2 <= ((_zz_157 ? (~ execute_RS2) : execute_RS2) + _zz_360); + memory_DivPlugin_div_needRevert <= ((_zz_158 ^ (_zz_157 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5498,13 +5442,16 @@ module VexRiscv ( memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_61; + decode_to_execute_FORMAL_PC_NEXT <= _zz_60; end if((! memory_arbitration_isStuck))begin execute_to_memory_FORMAL_PC_NEXT <= _zz_59; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_60; + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC1_CTRL <= _zz_28; @@ -5546,13 +5493,16 @@ module VexRiscv ( execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end if((! execute_arbitration_isStuck))begin - decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end if((! execute_arbitration_isStuck))begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; @@ -5629,29 +5579,12 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; - end if((! memory_arbitration_isStuck))begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; - execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; - execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; - execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; - execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; - execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; - execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; - execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; - execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; - end if((! memory_arbitration_isStuck))begin execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; end @@ -5679,12 +5612,12 @@ module VexRiscv ( if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; - end if((! writeBack_arbitration_isStuck))begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end @@ -5748,54 +5681,6 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); - end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end @@ -5804,7 +5689,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_366[0]; + CsrPlugin_mip_MSIP <= _zz_363[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5825,7 +5710,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_370[0]; + CsrPlugin_mcause_interrupt <= _zz_367[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5854,125 +5739,40 @@ module VexRiscv ( CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end end - if(execute_CsrPlugin_csr_2820)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2822)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; - end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; end - if(execute_CsrPlugin_csr_2824)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; - end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_57; end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; - end + _zz_162 <= debug_bus_cmd_payload_address[2]; + if(_zz_239)begin + DebugPlugin_busReadDataReg <= execute_PC; end - if(execute_CsrPlugin_csr_2826)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2828)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2830)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2832)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2834)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_169 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_170 <= execute_CsrPlugin_writeData[31 : 0]; - end - end - iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_269)begin - dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; - dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; - dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; - dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; - end - end - - always @ (posedge clk) begin - DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin - DebugPlugin_firstCycle <= 1'b1; - end - DebugPlugin_secondCycle <= DebugPlugin_firstCycle; - DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_57; - end - _zz_181 <= debug_bus_cmd_payload_address[2]; - if(_zz_240)begin - DebugPlugin_busReadDataReg <= execute_PC; - end - DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; - end - - always @ (posedge clk) begin - if(debugReset) begin - DebugPlugin_resetIt <= 1'b0; - DebugPlugin_haltIt <= 1'b0; - DebugPlugin_stepIt <= 1'b0; - DebugPlugin_godmode <= 1'b0; - DebugPlugin_haltedByBreak <= 1'b0; - end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin - DebugPlugin_godmode <= 1'b1; + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_262) + case(_zz_259) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -6000,13 +5800,13 @@ module VexRiscv ( end endcase end - if(_zz_240)begin - if(_zz_242)begin + if(_zz_239)begin + if(_zz_241)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_246)begin + if(_zz_244)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end @@ -6015,6 +5815,807 @@ module VexRiscv ( end +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; + end + end + end + + endmodule module InstructionCache ( @@ -6062,12 +6663,12 @@ module InstructionCache ( input reset ); reg [31:0] _zz_11; - reg [23:0] _zz_12; + reg [22:0] _zz_12; wire _zz_13; wire _zz_14; wire [0:0] _zz_15; wire [0:0] _zz_16; - wire [23:0] _zz_17; + wire [22:0] _zz_17; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6075,7 +6676,7 @@ module InstructionCache ( (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; - reg [5:0] lineLoader_flushCounter; + reg [6:0] lineLoader_flushCounter; reg _zz_3; reg lineLoader_cmdSent; reg lineLoader_wayToAllocate_willIncrement; @@ -6084,23 +6685,23 @@ module InstructionCache ( wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; wire lineLoader_write_tag_0_valid; - wire [4:0] lineLoader_write_tag_0_payload_address; + wire [5:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [21:0] lineLoader_write_tag_0_payload_data_address; + wire [20:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [7:0] lineLoader_write_data_0_payload_address; + wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [7:0] _zz_4; + wire [8:0] _zz_4; wire _zz_5; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [4:0] _zz_6; + wire [5:0] _zz_6; wire _zz_7; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [21:0] fetchStage_read_waysValues_0_tag_address; - wire [23:0] _zz_8; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_8; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; @@ -6118,10 +6719,10 @@ module InstructionCache ( reg decodeStage_mmuRsp_bypassTranslation; reg decodeStage_hit_valid; reg decodeStage_hit_error; - (* ram_style = "block" *) reg [31:0] banks_0 [0:255]; - (* ram_style = "block" *) reg [23:0] ways_0_tags [0:31]; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_13 = (! lineLoader_flushCounter[5]); + assign _zz_13 = (! lineLoader_flushCounter[6]); assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); assign _zz_15 = _zz_8[0 : 0]; assign _zz_16 = _zz_8[1 : 1]; @@ -6199,25 +6800,25 @@ module InstructionCache ( assign lineLoader_wayToAllocate_willClear = 1'b0; assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[5])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[9 : 2]; + assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; assign _zz_5 = (! io_cpu_fetch_isStuck); assign fetchStage_read_banksValue_0_dataMem = _zz_11; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[9 : 5]; + assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; assign _zz_7 = (! io_cpu_fetch_isStuck); assign _zz_8 = _zz_12; assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[23 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 10])); + assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; @@ -6273,11 +6874,11 @@ module InstructionCache ( lineLoader_address <= io_cpu_fill_payload; end if(_zz_13)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 6'h01); + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[5]; + _zz_3 <= lineLoader_flushCounter[6]; if(_zz_14)begin - lineLoader_flushCounter <= 6'h0; + lineLoader_flushCounter <= 7'h0; end if((! io_cpu_decode_isStuck))begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml index d5a4c13..75d2f32 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.yaml @@ -1,5 +1,5 @@ debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} iBus: !!vexriscv.BusReport flushInstructions: [4111, 19, 19, 19] - info: !!vexriscv.CacheReport {bytePerLine: 32, size: 1024} + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} kind: cached From cbb04d34fec970ebb660147932da0bb4bb5adce0 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Tue, 31 Aug 2021 12:08:32 -0700 Subject: [PATCH 24/30] Rebuild affected verilogs with correct hash comment (5bb9114). Signed-off-by: Tim Callahan --- .../verilog/VexRiscv_FullCfu.v | 2362 +++++++++------- .../verilog/VexRiscv_FullCfuDebug.v | 2462 ++++++++++------- .../verilog/VexRiscv_PerfCfu.v | 2 +- .../verilog/VexRiscv_PerfCfuDebug.v | 2 +- .../verilog/VexRiscv_SlimCfu.v | 2 +- .../verilog/VexRiscv_SlimCfuDebug.v | 2 +- 6 files changed, 2728 insertions(+), 2104 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index 0511bba..c5eea43 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9c3529c14328ee22a18ec0f74e66ca59de7346c3 +// Git hash : 5bb91146a62643cf606443d5366c69720906549c `define Input2Kind_defaultEncoding_type [0:0] @@ -87,37 +87,37 @@ module VexRiscv ( input clk, input reset ); - wire _zz_193; - wire _zz_194; - wire _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - reg _zz_201; - wire _zz_202; - wire [31:0] _zz_203; - wire _zz_204; - wire [31:0] _zz_205; - reg _zz_206; - wire _zz_207; - wire _zz_208; - wire [31:0] _zz_209; - wire _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; wire _zz_217; - wire [3:0] _zz_218; + wire _zz_218; wire _zz_219; wire _zz_220; - reg [31:0] _zz_221; - reg [31:0] _zz_222; - reg [31:0] _zz_223; + wire _zz_221; + wire _zz_222; + wire _zz_223; + wire _zz_224; + reg _zz_225; + wire _zz_226; + wire [31:0] _zz_227; + wire _zz_228; + wire [31:0] _zz_229; + reg _zz_230; + wire _zz_231; + wire _zz_232; + wire [31:0] _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire [3:0] _zz_242; + wire _zz_243; + wire _zz_244; + reg [31:0] _zz_245; + reg [31:0] _zz_246; + reg [31:0] _zz_247; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -150,33 +150,9 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - wire _zz_228; - wire _zz_229; - wire _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire [1:0] _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire _zz_245; - wire _zz_246; - wire _zz_247; wire _zz_248; wire _zz_249; - wire [1:0] _zz_250; + wire _zz_250; wire _zz_251; wire _zz_252; wire _zz_253; @@ -186,303 +162,327 @@ module VexRiscv ( wire _zz_257; wire _zz_258; wire _zz_259; - wire [1:0] _zz_260; + wire _zz_260; wire _zz_261; - wire [1:0] _zz_262; - wire [51:0] _zz_263; - wire [51:0] _zz_264; - wire [51:0] _zz_265; - wire [32:0] _zz_266; - wire [51:0] _zz_267; - wire [49:0] _zz_268; - wire [51:0] _zz_269; - wire [49:0] _zz_270; - wire [51:0] _zz_271; - wire [32:0] _zz_272; - wire [31:0] _zz_273; - wire [32:0] _zz_274; - wire [0:0] _zz_275; - wire [0:0] _zz_276; - wire [0:0] _zz_277; - wire [0:0] _zz_278; - wire [0:0] _zz_279; - wire [0:0] _zz_280; - wire [0:0] _zz_281; - wire [0:0] _zz_282; - wire [0:0] _zz_283; - wire [0:0] _zz_284; - wire [0:0] _zz_285; - wire [0:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; - wire [0:0] _zz_289; - wire [0:0] _zz_290; - wire [0:0] _zz_291; - wire [0:0] _zz_292; - wire [3:0] _zz_293; - wire [2:0] _zz_294; - wire [31:0] _zz_295; - wire [11:0] _zz_296; + wire _zz_262; + wire [1:0] _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire [1:0] _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire [1:0] _zz_284; + wire _zz_285; + wire [1:0] _zz_286; + wire [51:0] _zz_287; + wire [51:0] _zz_288; + wire [51:0] _zz_289; + wire [32:0] _zz_290; + wire [51:0] _zz_291; + wire [49:0] _zz_292; + wire [51:0] _zz_293; + wire [49:0] _zz_294; + wire [51:0] _zz_295; + wire [32:0] _zz_296; wire [31:0] _zz_297; - wire [19:0] _zz_298; - wire [11:0] _zz_299; - wire [31:0] _zz_300; - wire [31:0] _zz_301; - wire [19:0] _zz_302; - wire [11:0] _zz_303; - wire [2:0] _zz_304; - wire [2:0] _zz_305; + wire [32:0] _zz_298; + wire [0:0] _zz_299; + wire [0:0] _zz_300; + wire [0:0] _zz_301; + wire [0:0] _zz_302; + wire [0:0] _zz_303; + wire [0:0] _zz_304; + wire [0:0] _zz_305; wire [0:0] _zz_306; - wire [2:0] _zz_307; - wire [4:0] _zz_308; - wire [11:0] _zz_309; - wire [11:0] _zz_310; - wire [31:0] _zz_311; - wire [31:0] _zz_312; - wire [31:0] _zz_313; - wire [31:0] _zz_314; - wire [31:0] _zz_315; - wire [31:0] _zz_316; - wire [31:0] _zz_317; - wire [11:0] _zz_318; - wire [19:0] _zz_319; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [3:0] _zz_317; + wire [2:0] _zz_318; + wire [31:0] _zz_319; wire [11:0] _zz_320; wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [11:0] _zz_324; - wire [19:0] _zz_325; - wire [11:0] _zz_326; - wire [2:0] _zz_327; - wire [1:0] _zz_328; - wire [1:0] _zz_329; - wire [1:0] _zz_330; - wire [1:0] _zz_331; - wire [9:0] _zz_332; - wire [7:0] _zz_333; - wire [65:0] _zz_334; - wire [65:0] _zz_335; + wire [19:0] _zz_322; + wire [11:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [19:0] _zz_326; + wire [11:0] _zz_327; + wire [2:0] _zz_328; + wire [2:0] _zz_329; + wire [0:0] _zz_330; + wire [2:0] _zz_331; + wire [4:0] _zz_332; + wire [11:0] _zz_333; + wire [11:0] _zz_334; + wire [31:0] _zz_335; wire [31:0] _zz_336; wire [31:0] _zz_337; - wire [0:0] _zz_338; - wire [5:0] _zz_339; - wire [32:0] _zz_340; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [31:0] _zz_340; wire [31:0] _zz_341; - wire [31:0] _zz_342; - wire [32:0] _zz_343; - wire [32:0] _zz_344; - wire [32:0] _zz_345; - wire [32:0] _zz_346; - wire [0:0] _zz_347; - wire [32:0] _zz_348; - wire [0:0] _zz_349; - wire [32:0] _zz_350; - wire [0:0] _zz_351; - wire [31:0] _zz_352; - wire [0:0] _zz_353; - wire [0:0] _zz_354; - wire [0:0] _zz_355; - wire [0:0] _zz_356; - wire [0:0] _zz_357; - wire [0:0] _zz_358; - wire [0:0] _zz_359; - wire [26:0] _zz_360; - wire _zz_361; - wire _zz_362; - wire [1:0] _zz_363; - wire [31:0] _zz_364; + wire [11:0] _zz_342; + wire [19:0] _zz_343; + wire [11:0] _zz_344; + wire [31:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [11:0] _zz_348; + wire [19:0] _zz_349; + wire [11:0] _zz_350; + wire [2:0] _zz_351; + wire [1:0] _zz_352; + wire [1:0] _zz_353; + wire [1:0] _zz_354; + wire [1:0] _zz_355; + wire [9:0] _zz_356; + wire [7:0] _zz_357; + wire [65:0] _zz_358; + wire [65:0] _zz_359; + wire [31:0] _zz_360; + wire [31:0] _zz_361; + wire [0:0] _zz_362; + wire [5:0] _zz_363; + wire [32:0] _zz_364; wire [31:0] _zz_365; wire [31:0] _zz_366; - wire _zz_367; - wire [0:0] _zz_368; - wire [14:0] _zz_369; - wire [31:0] _zz_370; - wire [31:0] _zz_371; - wire [31:0] _zz_372; - wire _zz_373; - wire [0:0] _zz_374; - wire [8:0] _zz_375; + wire [32:0] _zz_367; + wire [32:0] _zz_368; + wire [32:0] _zz_369; + wire [32:0] _zz_370; + wire [0:0] _zz_371; + wire [32:0] _zz_372; + wire [0:0] _zz_373; + wire [32:0] _zz_374; + wire [0:0] _zz_375; wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire [31:0] _zz_378; - wire _zz_379; + wire [0:0] _zz_377; + wire [0:0] _zz_378; + wire [0:0] _zz_379; wire [0:0] _zz_380; - wire [2:0] _zz_381; - wire _zz_382; - wire _zz_383; - wire _zz_384; - wire [31:0] _zz_385; - wire [31:0] _zz_386; - wire _zz_387; - wire _zz_388; - wire [0:0] _zz_389; - wire [26:0] _zz_390; - wire [31:0] _zz_391; - wire [31:0] _zz_392; - wire [31:0] _zz_393; - wire [0:0] _zz_394; - wire [0:0] _zz_395; - wire [1:0] _zz_396; - wire [1:0] _zz_397; - wire _zz_398; - wire [0:0] _zz_399; - wire [21:0] _zz_400; + wire [0:0] _zz_381; + wire [0:0] _zz_382; + wire [0:0] _zz_383; + wire [26:0] _zz_384; + wire _zz_385; + wire _zz_386; + wire [1:0] _zz_387; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire _zz_391; + wire [0:0] _zz_392; + wire [14:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire [31:0] _zz_396; + wire _zz_397; + wire [0:0] _zz_398; + wire [8:0] _zz_399; + wire [31:0] _zz_400; wire [31:0] _zz_401; wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire [31:0] _zz_405; - wire [31:0] _zz_406; - wire [0:0] _zz_407; - wire [0:0] _zz_408; - wire [2:0] _zz_409; - wire [2:0] _zz_410; + wire _zz_403; + wire [0:0] _zz_404; + wire [2:0] _zz_405; + wire _zz_406; + wire _zz_407; + wire _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; wire _zz_411; - wire [0:0] _zz_412; - wire [18:0] _zz_413; - wire [31:0] _zz_414; + wire _zz_412; + wire [0:0] _zz_413; + wire [26:0] _zz_414; wire [31:0] _zz_415; wire [31:0] _zz_416; wire [31:0] _zz_417; - wire _zz_418; - wire _zz_419; - wire [31:0] _zz_420; - wire [31:0] _zz_421; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire [1:0] _zz_420; + wire [1:0] _zz_421; wire _zz_422; wire [0:0] _zz_423; - wire [0:0] _zz_424; - wire _zz_425; - wire [0:0] _zz_426; - wire [15:0] _zz_427; + wire [21:0] _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire [31:0] _zz_427; wire [31:0] _zz_428; - wire _zz_429; - wire _zz_430; - wire _zz_431; - wire [2:0] _zz_432; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire [0:0] _zz_431; + wire [0:0] _zz_432; wire [2:0] _zz_433; - wire _zz_434; - wire [0:0] _zz_435; - wire [12:0] _zz_436; - wire _zz_437; - wire _zz_438; - wire _zz_439; - wire [0:0] _zz_440; - wire [2:0] _zz_441; + wire [2:0] _zz_434; + wire _zz_435; + wire [0:0] _zz_436; + wire [18:0] _zz_437; + wire [31:0] _zz_438; + wire [31:0] _zz_439; + wire [31:0] _zz_440; + wire [31:0] _zz_441; wire _zz_442; - wire [5:0] _zz_443; - wire [5:0] _zz_444; - wire _zz_445; - wire [0:0] _zz_446; - wire [9:0] _zz_447; - wire [31:0] _zz_448; - wire [31:0] _zz_449; - wire [31:0] _zz_450; - wire [31:0] _zz_451; + wire _zz_443; + wire [31:0] _zz_444; + wire [31:0] _zz_445; + wire _zz_446; + wire [0:0] _zz_447; + wire [0:0] _zz_448; + wire _zz_449; + wire [0:0] _zz_450; + wire [15:0] _zz_451; wire [31:0] _zz_452; wire _zz_453; - wire [0:0] _zz_454; - wire [0:0] _zz_455; - wire [31:0] _zz_456; - wire _zz_457; - wire [0:0] _zz_458; - wire [3:0] _zz_459; - wire [0:0] _zz_460; - wire [3:0] _zz_461; - wire [5:0] _zz_462; - wire [5:0] _zz_463; - wire _zz_464; - wire [0:0] _zz_465; - wire [7:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire [31:0] _zz_471; + wire _zz_454; + wire _zz_455; + wire [2:0] _zz_456; + wire [2:0] _zz_457; + wire _zz_458; + wire [0:0] _zz_459; + wire [12:0] _zz_460; + wire _zz_461; + wire _zz_462; + wire _zz_463; + wire [0:0] _zz_464; + wire [2:0] _zz_465; + wire _zz_466; + wire [5:0] _zz_467; + wire [5:0] _zz_468; + wire _zz_469; + wire [0:0] _zz_470; + wire [9:0] _zz_471; wire [31:0] _zz_472; wire [31:0] _zz_473; wire [31:0] _zz_474; - wire [0:0] _zz_475; - wire [1:0] _zz_476; + wire [31:0] _zz_475; + wire [31:0] _zz_476; wire _zz_477; wire [0:0] _zz_478; - wire [1:0] _zz_479; - wire [0:0] _zz_480; - wire [3:0] _zz_481; + wire [0:0] _zz_479; + wire [31:0] _zz_480; + wire _zz_481; wire [0:0] _zz_482; - wire [0:0] _zz_483; - wire [1:0] _zz_484; - wire [1:0] _zz_485; - wire _zz_486; - wire [0:0] _zz_487; - wire [5:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; - wire _zz_491; - wire _zz_492; + wire [3:0] _zz_483; + wire [0:0] _zz_484; + wire [3:0] _zz_485; + wire [5:0] _zz_486; + wire [5:0] _zz_487; + wire _zz_488; + wire [0:0] _zz_489; + wire [7:0] _zz_490; + wire [31:0] _zz_491; + wire [31:0] _zz_492; wire [31:0] _zz_493; wire [31:0] _zz_494; wire [31:0] _zz_495; - wire _zz_496; - wire _zz_497; + wire [31:0] _zz_496; + wire [31:0] _zz_497; wire [31:0] _zz_498; - wire [31:0] _zz_499; - wire _zz_500; - wire [0:0] _zz_501; - wire [1:0] _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire _zz_505; - wire _zz_506; + wire [0:0] _zz_499; + wire [1:0] _zz_500; + wire _zz_501; + wire [0:0] _zz_502; + wire [1:0] _zz_503; + wire [0:0] _zz_504; + wire [3:0] _zz_505; + wire [0:0] _zz_506; wire [0:0] _zz_507; - wire [0:0] _zz_508; - wire _zz_509; - wire [0:0] _zz_510; - wire [3:0] _zz_511; - wire [31:0] _zz_512; + wire [1:0] _zz_508; + wire [1:0] _zz_509; + wire _zz_510; + wire [0:0] _zz_511; + wire [5:0] _zz_512; wire [31:0] _zz_513; wire [31:0] _zz_514; - wire [31:0] _zz_515; - wire [31:0] _zz_516; + wire _zz_515; + wire _zz_516; wire [31:0] _zz_517; wire [31:0] _zz_518; - wire _zz_519; + wire [31:0] _zz_519; wire _zz_520; - wire [31:0] _zz_521; + wire _zz_521; wire [31:0] _zz_522; wire [31:0] _zz_523; - wire [31:0] _zz_524; + wire _zz_524; wire [0:0] _zz_525; - wire [2:0] _zz_526; - wire [0:0] _zz_527; - wire [0:0] _zz_528; + wire [1:0] _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; wire _zz_529; - wire [0:0] _zz_530; - wire [1:0] _zz_531; - wire [31:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire _zz_535; - wire _zz_536; + wire _zz_530; + wire [0:0] _zz_531; + wire [0:0] _zz_532; + wire _zz_533; + wire [0:0] _zz_534; + wire [3:0] _zz_535; + wire [31:0] _zz_536; wire [31:0] _zz_537; - wire _zz_538; - wire [0:0] _zz_539; - wire [0:0] _zz_540; - wire [0:0] _zz_541; - wire [0:0] _zz_542; - wire [1:0] _zz_543; - wire [1:0] _zz_544; - wire [0:0] _zz_545; - wire [0:0] _zz_546; + wire [31:0] _zz_538; + wire [31:0] _zz_539; + wire [31:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire _zz_543; + wire _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; wire [31:0] _zz_547; wire [31:0] _zz_548; - wire [31:0] _zz_549; - wire [31:0] _zz_550; - wire [31:0] _zz_551; - wire [31:0] _zz_552; + wire [0:0] _zz_549; + wire [2:0] _zz_550; + wire [0:0] _zz_551; + wire [0:0] _zz_552; wire _zz_553; - wire _zz_554; - wire _zz_555; + wire [0:0] _zz_554; + wire [1:0] _zz_555; wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire _zz_559; + wire _zz_560; + wire [31:0] _zz_561; + wire _zz_562; + wire [0:0] _zz_563; + wire [0:0] _zz_564; + wire [0:0] _zz_565; + wire [0:0] _zz_566; + wire [1:0] _zz_567; + wire [1:0] _zz_568; + wire [0:0] _zz_569; + wire [0:0] _zz_570; + wire [31:0] _zz_571; + wire [31:0] _zz_572; + wire [31:0] _zz_573; + wire [31:0] _zz_574; + wire [31:0] _zz_575; + wire [31:0] _zz_576; + wire _zz_577; + wire _zz_578; + wire _zz_579; + wire [31:0] _zz_580; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1074,13 +1074,29 @@ module VexRiscv ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_151; - reg [23:0] _zz_152; - reg [31:0] _zz_153; + wire _zz_167; + reg [23:0] _zz_168; + reg [31:0] _zz_169; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1112,18 +1128,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_154; + wire [31:0] _zz_170; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_155; - wire _zz_156; - wire _zz_157; - reg [32:0] _zz_158; + wire [31:0] _zz_171; + wire _zz_172; + wire _zz_173; + reg [32:0] _zz_174; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_159; - wire [31:0] _zz_160; + reg [31:0] _zz_175; + wire [31:0] _zz_176; reg [31:0] decode_to_execute_PC; reg [31:0] execute_to_memory_PC; reg [31:0] memory_to_writeBack_PC; @@ -1210,24 +1226,24 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3200; reg execute_CsrPlugin_csr_3074; reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_2820; + reg execute_CsrPlugin_csr_2821; + reg execute_CsrPlugin_csr_2822; + reg execute_CsrPlugin_csr_2823; + reg execute_CsrPlugin_csr_2824; + reg execute_CsrPlugin_csr_2825; + reg execute_CsrPlugin_csr_2826; + reg execute_CsrPlugin_csr_2827; + reg execute_CsrPlugin_csr_2828; + reg execute_CsrPlugin_csr_2829; + reg execute_CsrPlugin_csr_2830; + reg execute_CsrPlugin_csr_2831; + reg execute_CsrPlugin_csr_2832; + reg execute_CsrPlugin_csr_2833; + reg execute_CsrPlugin_csr_2834; + reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; reg [31:0] _zz_177; reg [31:0] _zz_178; reg [31:0] _zz_179; @@ -1235,16 +1251,40 @@ module VexRiscv ( reg [31:0] _zz_181; reg [31:0] _zz_182; reg [31:0] _zz_183; - reg [2:0] _zz_184; - reg _zz_185; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; + reg [31:0] _zz_199; + reg [31:0] _zz_200; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + reg [2:0] _zz_208; + reg _zz_209; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_186; - wire _zz_187; - wire _zz_188; - wire _zz_189; - wire _zz_190; - wire _zz_191; - reg _zz_192; + reg [2:0] _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + reg _zz_216; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; @@ -1338,348 +1378,348 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_224 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_225 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_226 = 1'b1; - assign _zz_227 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_228 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_229 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_230 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_231 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_232 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_233 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_234 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_235 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_236 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_237 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_238 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_239 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_240 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_241 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_242 = (1'b0 || (! 1'b1)); - assign _zz_243 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_244 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_245 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_246 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_247 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_248 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_249 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_250 = execute_INSTRUCTION[13 : 12]; - assign _zz_251 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_252 = (! memory_arbitration_isStuck); - assign _zz_253 = (iBus_cmd_valid || (_zz_184 != 3'b000)); - assign _zz_254 = (_zz_220 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_255 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_256 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_257 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_258 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_259 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_260 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_261 = execute_INSTRUCTION[13]; - assign _zz_262 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_263 = ($signed(_zz_264) + $signed(_zz_269)); - assign _zz_264 = ($signed(_zz_265) + $signed(_zz_267)); - assign _zz_265 = 52'h0; - assign _zz_266 = {1'b0,memory_MUL_LL}; - assign _zz_267 = {{19{_zz_266[32]}}, _zz_266}; - assign _zz_268 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_269 = {{2{_zz_268[49]}}, _zz_268}; - assign _zz_270 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_271 = {{2{_zz_270[49]}}, _zz_270}; - assign _zz_272 = ($signed(_zz_274) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_273 = _zz_272[31 : 0]; - assign _zz_274 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_275 = _zz_93[33 : 33]; - assign _zz_276 = _zz_93[32 : 32]; - assign _zz_277 = _zz_93[31 : 31]; - assign _zz_278 = _zz_93[30 : 30]; - assign _zz_279 = _zz_93[28 : 28]; - assign _zz_280 = _zz_93[25 : 25]; - assign _zz_281 = _zz_93[17 : 17]; - assign _zz_282 = _zz_93[16 : 16]; - assign _zz_283 = _zz_93[13 : 13]; - assign _zz_284 = _zz_93[12 : 12]; - assign _zz_285 = _zz_93[11 : 11]; - assign _zz_286 = _zz_93[15 : 15]; - assign _zz_287 = _zz_93[5 : 5]; - assign _zz_288 = _zz_93[3 : 3]; - assign _zz_289 = _zz_93[20 : 20]; - assign _zz_290 = _zz_93[10 : 10]; - assign _zz_291 = _zz_93[4 : 4]; - assign _zz_292 = _zz_93[0 : 0]; - assign _zz_293 = (_zz_61 - 4'b0001); - assign _zz_294 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_295 = {29'd0, _zz_294}; - assign _zz_296 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_297 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_298 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_299 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_300 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_301 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_302 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_303 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_304 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_305 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_306 = execute_SRC_LESS; - assign _zz_307 = 3'b100; - assign _zz_308 = execute_INSTRUCTION[19 : 15]; - assign _zz_309 = execute_INSTRUCTION[31 : 20]; - assign _zz_310 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_311 = ($signed(_zz_312) + $signed(_zz_315)); - assign _zz_312 = ($signed(_zz_313) + $signed(_zz_314)); - assign _zz_313 = execute_SRC1; - assign _zz_314 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_315 = (execute_SRC_USE_SUB_LESS ? _zz_316 : _zz_317); - assign _zz_316 = 32'h00000001; - assign _zz_317 = 32'h0; - assign _zz_318 = execute_INSTRUCTION[31 : 20]; - assign _zz_319 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_320 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_321 = {_zz_132,execute_INSTRUCTION[31 : 20]}; - assign _zz_322 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_323 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_324 = execute_INSTRUCTION[31 : 20]; - assign _zz_325 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_326 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_327 = 3'b100; - assign _zz_328 = (_zz_147 & (~ _zz_329)); - assign _zz_329 = (_zz_147 - 2'b01); - assign _zz_330 = (_zz_149 & (~ _zz_331)); - assign _zz_331 = (_zz_149 - 2'b01); - assign _zz_332 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_333 = execute_INSTRUCTION[31 : 24]; - assign _zz_334 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_335 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_336 = writeBack_MUL_LOW[31 : 0]; - assign _zz_337 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_338 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_339 = {5'd0, _zz_338}; - assign _zz_340 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_341 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_342 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_343 = {_zz_154,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_344 = _zz_345; - assign _zz_345 = _zz_346; - assign _zz_346 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_155) : _zz_155)} + _zz_348); - assign _zz_347 = memory_DivPlugin_div_needRevert; - assign _zz_348 = {32'd0, _zz_347}; - assign _zz_349 = _zz_157; - assign _zz_350 = {32'd0, _zz_349}; - assign _zz_351 = _zz_156; - assign _zz_352 = {31'd0, _zz_351}; - assign _zz_353 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_354 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_355 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_356 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_357 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_358 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_359 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_360 = (iBus_cmd_payload_address >>> 5); - assign _zz_361 = 1'b1; - assign _zz_362 = 1'b1; - assign _zz_363 = {_zz_65,_zz_64}; - assign _zz_364 = 32'h0000106f; - assign _zz_365 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_366 = 32'h00001073; - assign _zz_367 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_368 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_369 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_370) == 32'h00000003),{(_zz_371 == _zz_372),{_zz_373,{_zz_374,_zz_375}}}}}}; - assign _zz_370 = 32'h0000207f; - assign _zz_371 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_372 = 32'h00000003; - assign _zz_373 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_374 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_375 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_376) == 32'h00005013),{(_zz_377 == _zz_378),{_zz_379,{_zz_380,_zz_381}}}}}}; - assign _zz_376 = 32'hbc00707f; - assign _zz_377 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_378 = 32'h00001013; - assign _zz_379 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_380 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_381 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_382 = decode_INSTRUCTION[31]; - assign _zz_383 = decode_INSTRUCTION[31]; - assign _zz_384 = decode_INSTRUCTION[7]; - assign _zz_385 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_386 = 32'h02004020; - assign _zz_387 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_388 = (_zz_97 != 1'b0); - assign _zz_389 = (((decode_INSTRUCTION & _zz_391) == 32'h00000050) != 1'b0); - assign _zz_390 = {((_zz_392 == _zz_393) != 1'b0),{({_zz_394,_zz_395} != 2'b00),{(_zz_396 != _zz_397),{_zz_398,{_zz_399,_zz_400}}}}}; - assign _zz_391 = 32'h00203050; - assign _zz_392 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_393 = 32'h00000050; - assign _zz_394 = ((decode_INSTRUCTION & _zz_401) == 32'h00001050); - assign _zz_395 = ((decode_INSTRUCTION & _zz_402) == 32'h00002050); - assign _zz_396 = {_zz_96,(_zz_403 == _zz_404)}; - assign _zz_397 = 2'b00; - assign _zz_398 = ((_zz_405 == _zz_406) != 1'b0); - assign _zz_399 = ({_zz_407,_zz_408} != 2'b00); - assign _zz_400 = {(_zz_409 != _zz_410),{_zz_411,{_zz_412,_zz_413}}}; - assign _zz_401 = 32'h00001050; - assign _zz_402 = 32'h00002050; - assign _zz_403 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_404 = 32'h00000004; - assign _zz_405 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_406 = 32'h00000040; - assign _zz_407 = ((decode_INSTRUCTION & _zz_414) == 32'h00005010); - assign _zz_408 = ((decode_INSTRUCTION & _zz_415) == 32'h00005020); - assign _zz_409 = {(_zz_416 == _zz_417),{_zz_418,_zz_419}}; - assign _zz_410 = 3'b000; - assign _zz_411 = ((_zz_420 == _zz_421) != 1'b0); - assign _zz_412 = (_zz_422 != 1'b0); - assign _zz_413 = {(_zz_423 != _zz_424),{_zz_425,{_zz_426,_zz_427}}}; - assign _zz_414 = 32'h00007034; - assign _zz_415 = 32'h02007064; - assign _zz_416 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_417 = 32'h40001010; - assign _zz_418 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_419 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_420 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_421 = 32'h00000024; - assign _zz_422 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_423 = ((decode_INSTRUCTION & _zz_428) == 32'h00002000); - assign _zz_424 = 1'b0; - assign _zz_425 = ({_zz_429,_zz_430} != 2'b00); - assign _zz_426 = (_zz_431 != 1'b0); - assign _zz_427 = {(_zz_432 != _zz_433),{_zz_434,{_zz_435,_zz_436}}}; - assign _zz_428 = 32'h00003000; - assign _zz_429 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_430 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_431 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_432 = {_zz_97,{_zz_437,_zz_438}}; - assign _zz_433 = 3'b000; - assign _zz_434 = ({_zz_439,{_zz_440,_zz_441}} != 5'h0); - assign _zz_435 = (_zz_442 != 1'b0); - assign _zz_436 = {(_zz_443 != _zz_444),{_zz_445,{_zz_446,_zz_447}}}; - assign _zz_437 = ((decode_INSTRUCTION & _zz_448) == 32'h00000020); - assign _zz_438 = ((decode_INSTRUCTION & _zz_449) == 32'h00000020); - assign _zz_439 = ((decode_INSTRUCTION & _zz_450) == 32'h00002040); - assign _zz_440 = (_zz_451 == _zz_452); - assign _zz_441 = {_zz_453,{_zz_454,_zz_455}}; - assign _zz_442 = ((decode_INSTRUCTION & _zz_456) == 32'h00000020); - assign _zz_443 = {_zz_457,{_zz_458,_zz_459}}; - assign _zz_444 = 6'h0; - assign _zz_445 = ({_zz_460,_zz_461} != 5'h0); - assign _zz_446 = (_zz_462 != _zz_463); - assign _zz_447 = {_zz_464,{_zz_465,_zz_466}}; - assign _zz_448 = 32'h00000034; - assign _zz_449 = 32'h00000064; - assign _zz_450 = 32'h00002040; - assign _zz_451 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_452 = 32'h00001040; - assign _zz_453 = ((decode_INSTRUCTION & _zz_467) == 32'h00000040); - assign _zz_454 = (_zz_468 == _zz_469); - assign _zz_455 = (_zz_470 == _zz_471); - assign _zz_456 = 32'h00000020; - assign _zz_457 = ((decode_INSTRUCTION & _zz_472) == 32'h00000008); - assign _zz_458 = (_zz_473 == _zz_474); - assign _zz_459 = {_zz_95,{_zz_475,_zz_476}}; - assign _zz_460 = _zz_95; - assign _zz_461 = {_zz_477,{_zz_478,_zz_479}}; - assign _zz_462 = {_zz_96,{_zz_480,_zz_481}}; - assign _zz_463 = 6'h0; - assign _zz_464 = ({_zz_482,_zz_483} != 2'b00); - assign _zz_465 = (_zz_484 != _zz_485); - assign _zz_466 = {_zz_486,{_zz_487,_zz_488}}; - assign _zz_467 = 32'h00000050; - assign _zz_468 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_469 = 32'h00000040; - assign _zz_470 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_471 = 32'h0; - assign _zz_472 = 32'h00000008; - assign _zz_473 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_474 = 32'h00000040; - assign _zz_475 = (_zz_489 == _zz_490); - assign _zz_476 = {_zz_491,_zz_492}; - assign _zz_477 = ((decode_INSTRUCTION & _zz_493) == 32'h00002010); - assign _zz_478 = (_zz_494 == _zz_495); - assign _zz_479 = {_zz_496,_zz_497}; - assign _zz_480 = (_zz_498 == _zz_499); - assign _zz_481 = {_zz_500,{_zz_501,_zz_502}}; - assign _zz_482 = _zz_95; - assign _zz_483 = (_zz_503 == _zz_504); - assign _zz_484 = {_zz_95,_zz_505}; - assign _zz_485 = 2'b00; - assign _zz_486 = (_zz_506 != 1'b0); - assign _zz_487 = (_zz_507 != _zz_508); - assign _zz_488 = {_zz_509,{_zz_510,_zz_511}}; - assign _zz_489 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_490 = 32'h00004020; - assign _zz_491 = ((decode_INSTRUCTION & _zz_512) == 32'h00000010); - assign _zz_492 = ((decode_INSTRUCTION & _zz_513) == 32'h00000020); - assign _zz_493 = 32'h00002030; - assign _zz_494 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_495 = 32'h00000010; - assign _zz_496 = ((decode_INSTRUCTION & _zz_514) == 32'h00002020); - assign _zz_497 = ((decode_INSTRUCTION & _zz_515) == 32'h00000020); - assign _zz_498 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_499 = 32'h00001010; - assign _zz_500 = ((decode_INSTRUCTION & _zz_516) == 32'h00002010); - assign _zz_501 = (_zz_517 == _zz_518); - assign _zz_502 = {_zz_519,_zz_520}; - assign _zz_503 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_504 = 32'h00000020; - assign _zz_505 = ((decode_INSTRUCTION & _zz_521) == 32'h0); - assign _zz_506 = ((decode_INSTRUCTION & _zz_522) == 32'h00004010); - assign _zz_507 = (_zz_523 == _zz_524); - assign _zz_508 = 1'b0; - assign _zz_509 = ({_zz_525,_zz_526} != 4'b0000); - assign _zz_510 = (_zz_527 != _zz_528); - assign _zz_511 = {_zz_529,{_zz_530,_zz_531}}; - assign _zz_512 = 32'h00000030; - assign _zz_513 = 32'h02000020; - assign _zz_514 = 32'h02002060; - assign _zz_515 = 32'h02003020; - assign _zz_516 = 32'h00002010; - assign _zz_517 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_518 = 32'h00000010; - assign _zz_519 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_520 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_521 = 32'h00000020; - assign _zz_522 = 32'h00004014; - assign _zz_523 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_524 = 32'h00002010; - assign _zz_525 = ((decode_INSTRUCTION & _zz_532) == 32'h0); - assign _zz_526 = {(_zz_533 == _zz_534),{_zz_535,_zz_536}}; - assign _zz_527 = ((decode_INSTRUCTION & _zz_537) == 32'h0); - assign _zz_528 = 1'b0; - assign _zz_529 = ({_zz_538,{_zz_539,_zz_540}} != 3'b000); - assign _zz_530 = ({_zz_541,_zz_542} != 2'b00); - assign _zz_531 = {(_zz_543 != _zz_544),(_zz_545 != _zz_546)}; - assign _zz_532 = 32'h00000044; - assign _zz_533 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_534 = 32'h0; - assign _zz_535 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_536 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_537 = 32'h00000058; - assign _zz_538 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_539 = ((decode_INSTRUCTION & _zz_547) == 32'h00002010); - assign _zz_540 = ((decode_INSTRUCTION & _zz_548) == 32'h40000030); - assign _zz_541 = ((decode_INSTRUCTION & _zz_549) == 32'h00000004); - assign _zz_542 = _zz_94; - assign _zz_543 = {(_zz_550 == _zz_551),_zz_94}; - assign _zz_544 = 2'b00; - assign _zz_545 = ((decode_INSTRUCTION & _zz_552) == 32'h00001004); - assign _zz_546 = 1'b0; - assign _zz_547 = 32'h00002014; - assign _zz_548 = 32'h40000034; - assign _zz_549 = 32'h00000014; - assign _zz_550 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_551 = 32'h00000004; - assign _zz_552 = 32'h00005054; - assign _zz_553 = execute_INSTRUCTION[31]; - assign _zz_554 = execute_INSTRUCTION[31]; - assign _zz_555 = execute_INSTRUCTION[7]; - assign _zz_556 = 32'h0; + assign _zz_248 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_249 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_250 = 1'b1; + assign _zz_251 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_252 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_254 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_255 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_256 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_257 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_260 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_264 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_265 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_266 = (1'b0 || (! 1'b1)); + assign _zz_267 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_268 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_270 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_271 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_272 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_273 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_274 = execute_INSTRUCTION[13 : 12]; + assign _zz_275 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_276 = (! memory_arbitration_isStuck); + assign _zz_277 = (iBus_cmd_valid || (_zz_208 != 3'b000)); + assign _zz_278 = (_zz_244 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_280 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_281 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_282 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_285 = execute_INSTRUCTION[13]; + assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); + assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); + assign _zz_289 = 52'h0; + assign _zz_290 = {1'b0,memory_MUL_LL}; + assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; + assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; + assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; + assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_297 = _zz_296[31 : 0]; + assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_299 = _zz_93[33 : 33]; + assign _zz_300 = _zz_93[32 : 32]; + assign _zz_301 = _zz_93[31 : 31]; + assign _zz_302 = _zz_93[30 : 30]; + assign _zz_303 = _zz_93[28 : 28]; + assign _zz_304 = _zz_93[25 : 25]; + assign _zz_305 = _zz_93[17 : 17]; + assign _zz_306 = _zz_93[16 : 16]; + assign _zz_307 = _zz_93[13 : 13]; + assign _zz_308 = _zz_93[12 : 12]; + assign _zz_309 = _zz_93[11 : 11]; + assign _zz_310 = _zz_93[15 : 15]; + assign _zz_311 = _zz_93[5 : 5]; + assign _zz_312 = _zz_93[3 : 3]; + assign _zz_313 = _zz_93[20 : 20]; + assign _zz_314 = _zz_93[10 : 10]; + assign _zz_315 = _zz_93[4 : 4]; + assign _zz_316 = _zz_93[0 : 0]; + assign _zz_317 = (_zz_61 - 4'b0001); + assign _zz_318 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_319 = {29'd0, _zz_318}; + assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_321 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_324 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_325 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_326 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_328 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_329 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_330 = execute_SRC_LESS; + assign _zz_331 = 3'b100; + assign _zz_332 = execute_INSTRUCTION[19 : 15]; + assign _zz_333 = execute_INSTRUCTION[31 : 20]; + assign _zz_334 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_335 = ($signed(_zz_336) + $signed(_zz_339)); + assign _zz_336 = ($signed(_zz_337) + $signed(_zz_338)); + assign _zz_337 = execute_SRC1; + assign _zz_338 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_339 = (execute_SRC_USE_SUB_LESS ? _zz_340 : _zz_341); + assign _zz_340 = 32'h00000001; + assign _zz_341 = 32'h0; + assign _zz_342 = execute_INSTRUCTION[31 : 20]; + assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_345 = {_zz_132,execute_INSTRUCTION[31 : 20]}; + assign _zz_346 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_347 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_348 = execute_INSTRUCTION[31 : 20]; + assign _zz_349 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_351 = 3'b100; + assign _zz_352 = (_zz_147 & (~ _zz_353)); + assign _zz_353 = (_zz_147 - 2'b01); + assign _zz_354 = (_zz_149 & (~ _zz_355)); + assign _zz_355 = (_zz_149 - 2'b01); + assign _zz_356 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_357 = execute_INSTRUCTION[31 : 24]; + assign _zz_358 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_359 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_360 = writeBack_MUL_LOW[31 : 0]; + assign _zz_361 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_362 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_363 = {5'd0, _zz_362}; + assign _zz_364 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_365 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_366 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_367 = {_zz_170,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_368 = _zz_369; + assign _zz_369 = _zz_370; + assign _zz_370 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_171) : _zz_171)} + _zz_372); + assign _zz_371 = memory_DivPlugin_div_needRevert; + assign _zz_372 = {32'd0, _zz_371}; + assign _zz_373 = _zz_173; + assign _zz_374 = {32'd0, _zz_373}; + assign _zz_375 = _zz_172; + assign _zz_376 = {31'd0, _zz_375}; + assign _zz_377 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_378 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_380 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_381 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_382 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_383 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_384 = (iBus_cmd_payload_address >>> 5); + assign _zz_385 = 1'b1; + assign _zz_386 = 1'b1; + assign _zz_387 = {_zz_65,_zz_64}; + assign _zz_388 = 32'h0000106f; + assign _zz_389 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_390 = 32'h00001073; + assign _zz_391 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_392 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_393 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_394) == 32'h00000003),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; + assign _zz_394 = 32'h0000207f; + assign _zz_395 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_396 = 32'h00000003; + assign _zz_397 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_398 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_399 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_400) == 32'h00005013),{(_zz_401 == _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; + assign _zz_400 = 32'hbc00707f; + assign _zz_401 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_402 = 32'h00001013; + assign _zz_403 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_405 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_406 = decode_INSTRUCTION[31]; + assign _zz_407 = decode_INSTRUCTION[31]; + assign _zz_408 = decode_INSTRUCTION[7]; + assign _zz_409 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_410 = 32'h02004020; + assign _zz_411 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_412 = (_zz_97 != 1'b0); + assign _zz_413 = (((decode_INSTRUCTION & _zz_415) == 32'h00000050) != 1'b0); + assign _zz_414 = {((_zz_416 == _zz_417) != 1'b0),{({_zz_418,_zz_419} != 2'b00),{(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}}}; + assign _zz_415 = 32'h00203050; + assign _zz_416 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_417 = 32'h00000050; + assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00001050); + assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00002050); + assign _zz_420 = {_zz_96,(_zz_427 == _zz_428)}; + assign _zz_421 = 2'b00; + assign _zz_422 = ((_zz_429 == _zz_430) != 1'b0); + assign _zz_423 = ({_zz_431,_zz_432} != 2'b00); + assign _zz_424 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; + assign _zz_425 = 32'h00001050; + assign _zz_426 = 32'h00002050; + assign _zz_427 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_428 = 32'h00000004; + assign _zz_429 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_430 = 32'h00000040; + assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h00005010); + assign _zz_432 = ((decode_INSTRUCTION & _zz_439) == 32'h00005020); + assign _zz_433 = {(_zz_440 == _zz_441),{_zz_442,_zz_443}}; + assign _zz_434 = 3'b000; + assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); + assign _zz_436 = (_zz_446 != 1'b0); + assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; + assign _zz_438 = 32'h00007034; + assign _zz_439 = 32'h02007064; + assign _zz_440 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_441 = 32'h40001010; + assign _zz_442 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_443 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_445 = 32'h00000024; + assign _zz_446 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_447 = ((decode_INSTRUCTION & _zz_452) == 32'h00002000); + assign _zz_448 = 1'b0; + assign _zz_449 = ({_zz_453,_zz_454} != 2'b00); + assign _zz_450 = (_zz_455 != 1'b0); + assign _zz_451 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; + assign _zz_452 = 32'h00003000; + assign _zz_453 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_454 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_455 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_456 = {_zz_97,{_zz_461,_zz_462}}; + assign _zz_457 = 3'b000; + assign _zz_458 = ({_zz_463,{_zz_464,_zz_465}} != 5'h0); + assign _zz_459 = (_zz_466 != 1'b0); + assign _zz_460 = {(_zz_467 != _zz_468),{_zz_469,{_zz_470,_zz_471}}}; + assign _zz_461 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); + assign _zz_462 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); + assign _zz_463 = ((decode_INSTRUCTION & _zz_474) == 32'h00002040); + assign _zz_464 = (_zz_475 == _zz_476); + assign _zz_465 = {_zz_477,{_zz_478,_zz_479}}; + assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000020); + assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; + assign _zz_468 = 6'h0; + assign _zz_469 = ({_zz_484,_zz_485} != 5'h0); + assign _zz_470 = (_zz_486 != _zz_487); + assign _zz_471 = {_zz_488,{_zz_489,_zz_490}}; + assign _zz_472 = 32'h00000034; + assign _zz_473 = 32'h00000064; + assign _zz_474 = 32'h00002040; + assign _zz_475 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_476 = 32'h00001040; + assign _zz_477 = ((decode_INSTRUCTION & _zz_491) == 32'h00000040); + assign _zz_478 = (_zz_492 == _zz_493); + assign _zz_479 = (_zz_494 == _zz_495); + assign _zz_480 = 32'h00000020; + assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00000008); + assign _zz_482 = (_zz_497 == _zz_498); + assign _zz_483 = {_zz_95,{_zz_499,_zz_500}}; + assign _zz_484 = _zz_95; + assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; + assign _zz_486 = {_zz_96,{_zz_504,_zz_505}}; + assign _zz_487 = 6'h0; + assign _zz_488 = ({_zz_506,_zz_507} != 2'b00); + assign _zz_489 = (_zz_508 != _zz_509); + assign _zz_490 = {_zz_510,{_zz_511,_zz_512}}; + assign _zz_491 = 32'h00000050; + assign _zz_492 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_493 = 32'h00000040; + assign _zz_494 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_495 = 32'h0; + assign _zz_496 = 32'h00000008; + assign _zz_497 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_498 = 32'h00000040; + assign _zz_499 = (_zz_513 == _zz_514); + assign _zz_500 = {_zz_515,_zz_516}; + assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00002010); + assign _zz_502 = (_zz_518 == _zz_519); + assign _zz_503 = {_zz_520,_zz_521}; + assign _zz_504 = (_zz_522 == _zz_523); + assign _zz_505 = {_zz_524,{_zz_525,_zz_526}}; + assign _zz_506 = _zz_95; + assign _zz_507 = (_zz_527 == _zz_528); + assign _zz_508 = {_zz_95,_zz_529}; + assign _zz_509 = 2'b00; + assign _zz_510 = (_zz_530 != 1'b0); + assign _zz_511 = (_zz_531 != _zz_532); + assign _zz_512 = {_zz_533,{_zz_534,_zz_535}}; + assign _zz_513 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_514 = 32'h00004020; + assign _zz_515 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); + assign _zz_516 = ((decode_INSTRUCTION & _zz_537) == 32'h00000020); + assign _zz_517 = 32'h00002030; + assign _zz_518 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_519 = 32'h00000010; + assign _zz_520 = ((decode_INSTRUCTION & _zz_538) == 32'h00002020); + assign _zz_521 = ((decode_INSTRUCTION & _zz_539) == 32'h00000020); + assign _zz_522 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_523 = 32'h00001010; + assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00002010); + assign _zz_525 = (_zz_541 == _zz_542); + assign _zz_526 = {_zz_543,_zz_544}; + assign _zz_527 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_528 = 32'h00000020; + assign _zz_529 = ((decode_INSTRUCTION & _zz_545) == 32'h0); + assign _zz_530 = ((decode_INSTRUCTION & _zz_546) == 32'h00004010); + assign _zz_531 = (_zz_547 == _zz_548); + assign _zz_532 = 1'b0; + assign _zz_533 = ({_zz_549,_zz_550} != 4'b0000); + assign _zz_534 = (_zz_551 != _zz_552); + assign _zz_535 = {_zz_553,{_zz_554,_zz_555}}; + assign _zz_536 = 32'h00000030; + assign _zz_537 = 32'h02000020; + assign _zz_538 = 32'h02002060; + assign _zz_539 = 32'h02003020; + assign _zz_540 = 32'h00002010; + assign _zz_541 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_542 = 32'h00000010; + assign _zz_543 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_544 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_545 = 32'h00000020; + assign _zz_546 = 32'h00004014; + assign _zz_547 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_548 = 32'h00002010; + assign _zz_549 = ((decode_INSTRUCTION & _zz_556) == 32'h0); + assign _zz_550 = {(_zz_557 == _zz_558),{_zz_559,_zz_560}}; + assign _zz_551 = ((decode_INSTRUCTION & _zz_561) == 32'h0); + assign _zz_552 = 1'b0; + assign _zz_553 = ({_zz_562,{_zz_563,_zz_564}} != 3'b000); + assign _zz_554 = ({_zz_565,_zz_566} != 2'b00); + assign _zz_555 = {(_zz_567 != _zz_568),(_zz_569 != _zz_570)}; + assign _zz_556 = 32'h00000044; + assign _zz_557 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_558 = 32'h0; + assign _zz_559 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_560 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_561 = 32'h00000058; + assign _zz_562 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_563 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); + assign _zz_564 = ((decode_INSTRUCTION & _zz_572) == 32'h40000030); + assign _zz_565 = ((decode_INSTRUCTION & _zz_573) == 32'h00000004); + assign _zz_566 = _zz_94; + assign _zz_567 = {(_zz_574 == _zz_575),_zz_94}; + assign _zz_568 = 2'b00; + assign _zz_569 = ((decode_INSTRUCTION & _zz_576) == 32'h00001004); + assign _zz_570 = 1'b0; + assign _zz_571 = 32'h00002014; + assign _zz_572 = 32'h40000034; + assign _zz_573 = 32'h00000014; + assign _zz_574 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_575 = 32'h00000004; + assign _zz_576 = 32'h00005054; + assign _zz_577 = execute_INSTRUCTION[31]; + assign _zz_578 = execute_INSTRUCTION[31]; + assign _zz_579 = execute_INSTRUCTION[7]; + assign _zz_580 = 32'h0; always @ (posedge clk) begin - if(_zz_361) begin - _zz_221 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_385) begin + _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_362) begin - _zz_222 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_386) begin + _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1690,13 +1730,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_193 ), //i - .io_cpu_prefetch_isValid (_zz_194 ), //i + .io_flush (_zz_217 ), //i + .io_cpu_prefetch_isValid (_zz_218 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_195 ), //i - .io_cpu_fetch_isStuck (_zz_196 ), //i - .io_cpu_fetch_isRemoved (_zz_197 ), //i + .io_cpu_fetch_isValid (_zz_219 ), //i + .io_cpu_fetch_isStuck (_zz_220 ), //i + .io_cpu_fetch_isRemoved (_zz_221 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1709,8 +1749,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_198 ), //i - .io_cpu_decode_isStuck (_zz_199 ), //i + .io_cpu_decode_isValid (_zz_222 ), //i + .io_cpu_decode_isStuck (_zz_223 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1718,8 +1758,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_200 ), //i - .io_cpu_fill_valid (_zz_201 ), //i + .io_cpu_decode_isUser (_zz_224 ), //i + .io_cpu_fill_valid (_zz_225 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1732,20 +1772,20 @@ module VexRiscv ( .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_202 ), //i - .io_cpu_execute_address (_zz_203[31:0] ), //i + .io_cpu_execute_isValid (_zz_226 ), //i + .io_cpu_execute_address (_zz_227[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_88[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_204 ), //i + .io_cpu_memory_isValid (_zz_228 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_205[31:0] ), //i + .io_cpu_memory_address (_zz_229[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_206 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_230 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1753,31 +1793,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_207 ), //i + .io_cpu_writeBack_isValid (_zz_231 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_208 ), //i + .io_cpu_writeBack_isUser (_zz_232 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_209[31:0] ), //i + .io_cpu_writeBack_address (_zz_233[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_210 ), //i - .io_cpu_writeBack_fence_SR (_zz_211 ), //i - .io_cpu_writeBack_fence_SO (_zz_212 ), //i - .io_cpu_writeBack_fence_SI (_zz_213 ), //i - .io_cpu_writeBack_fence_PW (_zz_214 ), //i - .io_cpu_writeBack_fence_PR (_zz_215 ), //i - .io_cpu_writeBack_fence_PO (_zz_216 ), //i - .io_cpu_writeBack_fence_PI (_zz_217 ), //i - .io_cpu_writeBack_fence_FM (_zz_218[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_234 ), //i + .io_cpu_writeBack_fence_SR (_zz_235 ), //i + .io_cpu_writeBack_fence_SO (_zz_236 ), //i + .io_cpu_writeBack_fence_SI (_zz_237 ), //i + .io_cpu_writeBack_fence_PW (_zz_238 ), //i + .io_cpu_writeBack_fence_PR (_zz_239 ), //i + .io_cpu_writeBack_fence_PO (_zz_240 ), //i + .io_cpu_writeBack_fence_PI (_zz_241 ), //i + .io_cpu_writeBack_fence_FM (_zz_242[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_219 ), //i + .io_cpu_flush_valid (_zz_243 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_220 ), //i + .io_mem_cmd_ready (_zz_244 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1793,18 +1833,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_363) + case(_zz_387) 2'b00 : begin - _zz_223 = DBusCachedPlugin_redoBranch_payload; + _zz_247 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_223 = CsrPlugin_jumpInterface_payload; + _zz_247 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_223 = BranchPlugin_jumpInterface_payload; + _zz_247 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_223 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_247 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2559,7 +2599,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_263) + $signed(_zz_271)); + assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2567,41 +2607,41 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_273; + assign execute_SHIFT_RIGHT = _zz_297; assign execute_REGFILE_WRITE_DATA = _zz_108; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_203[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_227[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_275[0]; - assign decode_IS_RS1_SIGNED = _zz_276[0]; - assign decode_IS_DIV = _zz_277[0]; + assign decode_IS_RS2_SIGNED = _zz_299[0]; + assign decode_IS_RS1_SIGNED = _zz_300[0]; + assign decode_IS_DIV = _zz_301[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_278[0]; + assign decode_IS_MUL = _zz_302[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_279[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_280[0]; + assign decode_IS_CSR = _zz_304[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_281[0]; - assign decode_MEMORY_MANAGMENT = _zz_282[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; + assign decode_MEMORY_MANAGMENT = _zz_306[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_283[0]; + assign decode_MEMORY_WR = _zz_307[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_284[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_285[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2654,11 +2694,11 @@ module VexRiscv ( assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_COND_RESULT = _zz_130; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_286[0]; - assign decode_RS1_USE = _zz_287[0]; + assign decode_RS2_USE = _zz_310[0]; + assign decode_RS1_USE = _zz_311[0]; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_224)begin + if(_zz_248)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2676,21 +2716,21 @@ module VexRiscv ( decode_RS2 = _zz_121; end end - if(_zz_225)begin - if(_zz_226)begin + if(_zz_249)begin + if(_zz_250)begin if(_zz_123)begin decode_RS2 = _zz_57; end end end - if(_zz_227)begin + if(_zz_251)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_125)begin decode_RS2 = _zz_38; end end end - if(_zz_228)begin + if(_zz_252)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_127)begin decode_RS2 = _zz_37; @@ -2706,21 +2746,21 @@ module VexRiscv ( decode_RS1 = _zz_121; end end - if(_zz_225)begin - if(_zz_226)begin + if(_zz_249)begin + if(_zz_250)begin if(_zz_122)begin decode_RS1 = _zz_57; end end end - if(_zz_227)begin + if(_zz_251)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_124)begin decode_RS1 = _zz_38; end end end - if(_zz_228)begin + if(_zz_252)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_126)begin decode_RS1 = _zz_37; @@ -2747,7 +2787,7 @@ module VexRiscv ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_229)begin + if(_zz_253)begin _zz_38 = memory_DivPlugin_div_result; end end @@ -2760,8 +2800,8 @@ module VexRiscv ( assign _zz_41 = execute_PC; assign execute_SRC2_CTRL = _zz_42; assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_288[0]; - assign decode_SRC_ADD_ZERO = _zz_289[0]; + assign decode_SRC_USE_SUB_LESS = _zz_312[0]; + assign decode_SRC_ADD_ZERO = _zz_313[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_44; @@ -2779,25 +2819,25 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_290[0]; + decode_REGFILE_WRITE_VALID = _zz_314[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_364) == 32'h00000003),{(_zz_365 == _zz_366),{_zz_367,{_zz_368,_zz_369}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}} != 22'h0); always @ (*) begin _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_262) + case(_zz_286) 2'b00 : begin - _zz_57 = _zz_336; + _zz_57 = _zz_360; end default : begin - _zz_57 = _zz_337; + _zz_57 = _zz_361; end endcase end @@ -2816,32 +2856,32 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_291[0]; - assign decode_FLUSH_ALL = _zz_292[0]; + assign decode_MEMORY_ENABLE = _zz_315[0]; + assign decode_FLUSH_ALL = _zz_316[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_230)begin + if(_zz_254)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_231)begin + if(_zz_255)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_232)begin + if(_zz_256)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_233)begin + if(_zz_257)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2887,7 +2927,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_234)begin + if(_zz_258)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2901,22 +2941,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_234)begin + if(_zz_258)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_219 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_243 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_235)begin + if(_zz_259)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_224)begin + if(_zz_248)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -2935,7 +2975,7 @@ module VexRiscv ( always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_236)begin + if(_zz_260)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -2949,7 +2989,7 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_236)begin + if(_zz_260)begin execute_arbitration_flushNext = 1'b1; end end @@ -2961,7 +3001,7 @@ module VexRiscv ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_229)begin + if(_zz_253)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3020,10 +3060,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_237)begin + if(_zz_261)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_238)begin + if(_zz_262)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3037,10 +3077,10 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_237)begin + if(_zz_261)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_238)begin + if(_zz_262)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3054,7 +3094,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_235)begin + if(_zz_259)begin CsrPlugin_inWfi = 1'b1; end end @@ -3062,21 +3102,21 @@ module VexRiscv ( assign CsrPlugin_thirdPartyWake = 1'b0; always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_237)begin + if(_zz_261)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_238)begin + if(_zz_262)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_237)begin + if(_zz_261)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_238)begin - case(_zz_239) + if(_zz_262)begin + case(_zz_263) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3092,11 +3132,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_62 = (_zz_61 & (~ _zz_293)); + assign _zz_62 = (_zz_61 & (~ _zz_317)); assign _zz_63 = _zz_62[3]; assign _zz_64 = (_zz_62[1] || _zz_63); assign _zz_65 = (_zz_62[2] || _zz_63); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_223; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3116,7 +3156,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_295); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_319); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3207,7 +3247,7 @@ module VexRiscv ( assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_75 = _zz_296[11]; + assign _zz_75 = _zz_320[11]; always @ (*) begin _zz_76[18] = _zz_75; _zz_76[17] = _zz_75; @@ -3231,13 +3271,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_297[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_321[31])); if(_zz_81)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_77 = _zz_298[19]; + assign _zz_77 = _zz_322[19]; always @ (*) begin _zz_78[10] = _zz_77; _zz_78[9] = _zz_77; @@ -3252,7 +3292,7 @@ module VexRiscv ( _zz_78[0] = _zz_77; end - assign _zz_79 = _zz_299[11]; + assign _zz_79 = _zz_323[11]; always @ (*) begin _zz_80[18] = _zz_79; _zz_80[17] = _zz_79; @@ -3278,16 +3318,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_81 = _zz_300[1]; + _zz_81 = _zz_324[1]; end default : begin - _zz_81 = _zz_301[1]; + _zz_81 = _zz_325[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_82 = _zz_302[19]; + assign _zz_82 = _zz_326[19]; always @ (*) begin _zz_83[10] = _zz_82; _zz_83[9] = _zz_82; @@ -3302,7 +3342,7 @@ module VexRiscv ( _zz_83[0] = _zz_82; end - assign _zz_84 = _zz_303[11]; + assign _zz_84 = _zz_327[11]; always @ (*) begin _zz_85[18] = _zz_84; _zz_85[17] = _zz_84; @@ -3325,7 +3365,7 @@ module VexRiscv ( _zz_85[0] = _zz_84; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_382,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_383,_zz_384},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_406,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_407,_zz_408},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3334,52 +3374,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_194 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_195 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_196 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_195; + assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_219; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_198 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_199 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_200 = (CsrPlugin_privilege == 2'b00); + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_224 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_233)begin + if(_zz_257)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_231)begin + if(_zz_255)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_201 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_231)begin - _zz_201 = 1'b1; + _zz_225 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_255)begin + _zz_225 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_232)begin + if(_zz_256)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_230)begin + if(_zz_254)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_232)begin + if(_zz_256)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_230)begin + if(_zz_254)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3389,9 +3429,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_193 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_217 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_220 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_244 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3418,8 +3458,8 @@ module VexRiscv ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_202 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_203 = execute_SRC_ADD; + assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_227 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3434,27 +3474,27 @@ module VexRiscv ( endcase end - assign _zz_219 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_204 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_205 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_204; + assign _zz_243 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_228 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_229 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_228; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_205; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_229; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_206 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_230 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_206 = 1'b1; + _zz_230 = 1'b1; end end - assign _zz_207 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_208 = (CsrPlugin_privilege == 2'b00); - assign _zz_209 = writeBack_REGFILE_WRITE_DATA; + assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_232 = (CsrPlugin_privilege == 2'b00); + assign _zz_233 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_240)begin + if(_zz_264)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3464,7 +3504,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_240)begin + if(_zz_264)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3483,15 +3523,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_240)begin + if(_zz_264)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_304}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_305}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; end end end @@ -3564,7 +3604,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_260) + case(_zz_284) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_90; end @@ -3600,7 +3640,7 @@ module VexRiscv ( assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_385 == _zz_386) != 1'b0),{(_zz_387 != 1'b0),{1'b0,{_zz_388,{_zz_389,_zz_390}}}}}}}; + assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_409 == _zz_410) != 1'b0),{(_zz_411 != 1'b0),{1'b0,{_zz_412,{_zz_413,_zz_414}}}}}}}; assign _zz_99 = _zz_93[2 : 1]; assign _zz_56 = _zz_99; assign _zz_100 = _zz_93[7 : 6]; @@ -3622,8 +3662,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_221; - assign decode_RegFilePlugin_rs2Data = _zz_222; + assign decode_RegFilePlugin_rs1Data = _zz_245; + assign decode_RegFilePlugin_rs2Data = _zz_246; always @ (*) begin lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); if(_zz_107)begin @@ -3665,7 +3705,7 @@ module VexRiscv ( _zz_108 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_108 = {31'd0, _zz_306}; + _zz_108 = {31'd0, _zz_330}; end default : begin _zz_108 = execute_SRC_ADD_SUB; @@ -3679,18 +3719,18 @@ module VexRiscv ( _zz_109 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_109 = {29'd0, _zz_307}; + _zz_109 = {29'd0, _zz_331}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_109 = {27'd0, _zz_308}; + _zz_109 = {27'd0, _zz_332}; end endcase end - assign _zz_110 = _zz_309[11]; + assign _zz_110 = _zz_333[11]; always @ (*) begin _zz_111[19] = _zz_110; _zz_111[18] = _zz_110; @@ -3714,7 +3754,7 @@ module VexRiscv ( _zz_111[0] = _zz_110; end - assign _zz_112 = _zz_310[11]; + assign _zz_112 = _zz_334[11]; always @ (*) begin _zz_113[19] = _zz_112; _zz_113[18] = _zz_112; @@ -3756,7 +3796,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_311; + execute_SrcPlugin_addSub = _zz_335; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3837,22 +3877,22 @@ module VexRiscv ( always @ (*) begin _zz_117 = 1'b0; - if(_zz_241)begin - if(_zz_242)begin + if(_zz_265)begin + if(_zz_266)begin if(_zz_122)begin _zz_117 = 1'b1; end end end - if(_zz_243)begin - if(_zz_244)begin + if(_zz_267)begin + if(_zz_268)begin if(_zz_124)begin _zz_117 = 1'b1; end end end - if(_zz_245)begin - if(_zz_246)begin + if(_zz_269)begin + if(_zz_270)begin if(_zz_126)begin _zz_117 = 1'b1; end @@ -3865,22 +3905,22 @@ module VexRiscv ( always @ (*) begin _zz_118 = 1'b0; - if(_zz_241)begin - if(_zz_242)begin + if(_zz_265)begin + if(_zz_266)begin if(_zz_123)begin _zz_118 = 1'b1; end end end - if(_zz_243)begin - if(_zz_244)begin + if(_zz_267)begin + if(_zz_268)begin if(_zz_125)begin _zz_118 = 1'b1; end end end - if(_zz_245)begin - if(_zz_246)begin + if(_zz_269)begin + if(_zz_270)begin if(_zz_127)begin _zz_118 = 1'b1; end @@ -3928,7 +3968,7 @@ module VexRiscv ( endcase end - assign _zz_131 = _zz_318[11]; + assign _zz_131 = _zz_342[11]; always @ (*) begin _zz_132[19] = _zz_131; _zz_132[18] = _zz_131; @@ -3952,7 +3992,7 @@ module VexRiscv ( _zz_132[0] = _zz_131; end - assign _zz_133 = _zz_319[19]; + assign _zz_133 = _zz_343[19]; always @ (*) begin _zz_134[10] = _zz_133; _zz_134[9] = _zz_133; @@ -3967,7 +4007,7 @@ module VexRiscv ( _zz_134[0] = _zz_133; end - assign _zz_135 = _zz_320[11]; + assign _zz_135 = _zz_344[11]; always @ (*) begin _zz_136[18] = _zz_135; _zz_136[17] = _zz_135; @@ -3993,13 +4033,13 @@ module VexRiscv ( always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_137 = (_zz_321[1] ^ execute_RS1[1]); + _zz_137 = (_zz_345[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_137 = _zz_322[1]; + _zz_137 = _zz_346[1]; end default : begin - _zz_137 = _zz_323[1]; + _zz_137 = _zz_347[1]; end endcase end @@ -4016,7 +4056,7 @@ module VexRiscv ( endcase end - assign _zz_138 = _zz_324[11]; + assign _zz_138 = _zz_348[11]; always @ (*) begin _zz_139[19] = _zz_138; _zz_139[18] = _zz_138; @@ -4046,15 +4086,15 @@ module VexRiscv ( execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_553,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_554,_zz_555},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_577,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_578,_zz_579},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_327}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_351}; end end endcase end - assign _zz_140 = _zz_325[19]; + assign _zz_140 = _zz_349[19]; always @ (*) begin _zz_141[10] = _zz_140; _zz_141[9] = _zz_140; @@ -4069,7 +4109,7 @@ module VexRiscv ( _zz_141[0] = _zz_140; end - assign _zz_142 = _zz_326[11]; + assign _zz_142 = _zz_350[11]; always @ (*) begin _zz_143[18] = _zz_142; _zz_143[17] = _zz_142; @@ -4118,12 +4158,12 @@ module VexRiscv ( assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_148 = _zz_328[0]; + assign _zz_148 = _zz_352[0]; assign _zz_149 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_150 = _zz_330[0]; + assign _zz_150 = _zz_354[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_234)begin + if(_zz_258)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4133,7 +4173,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_236)begin + if(_zz_260)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -4302,6 +4342,70 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end + if(execute_CsrPlugin_csr_2820)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2822)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2824)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2826)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2828)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2830)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end if(execute_CsrPlugin_csr_3008)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4310,7 +4414,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_247)begin + if(_zz_271)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4329,20 +4433,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_248)begin + if(_zz_272)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_249)begin + if(_zz_273)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_248)begin + if(_zz_272)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_249)begin + if(_zz_273)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4357,14 +4461,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_247)begin + if(_zz_271)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_247)begin + if(_zz_271)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4373,7 +4477,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_261) + case(_zz_285) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4386,49 +4490,49 @@ module VexRiscv ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_332; + assign execute_CfuPlugin_functionsIds_0 = _zz_356; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_151 = _zz_333[7]; - always @ (*) begin - _zz_152[23] = _zz_151; - _zz_152[22] = _zz_151; - _zz_152[21] = _zz_151; - _zz_152[20] = _zz_151; - _zz_152[19] = _zz_151; - _zz_152[18] = _zz_151; - _zz_152[17] = _zz_151; - _zz_152[16] = _zz_151; - _zz_152[15] = _zz_151; - _zz_152[14] = _zz_151; - _zz_152[13] = _zz_151; - _zz_152[12] = _zz_151; - _zz_152[11] = _zz_151; - _zz_152[10] = _zz_151; - _zz_152[9] = _zz_151; - _zz_152[8] = _zz_151; - _zz_152[7] = _zz_151; - _zz_152[6] = _zz_151; - _zz_152[5] = _zz_151; - _zz_152[4] = _zz_151; - _zz_152[3] = _zz_151; - _zz_152[2] = _zz_151; - _zz_152[1] = _zz_151; - _zz_152[0] = _zz_151; + assign _zz_167 = _zz_357[7]; + always @ (*) begin + _zz_168[23] = _zz_167; + _zz_168[22] = _zz_167; + _zz_168[21] = _zz_167; + _zz_168[20] = _zz_167; + _zz_168[19] = _zz_167; + _zz_168[18] = _zz_167; + _zz_168[17] = _zz_167; + _zz_168[16] = _zz_167; + _zz_168[15] = _zz_167; + _zz_168[14] = _zz_167; + _zz_168[13] = _zz_167; + _zz_168[12] = _zz_167; + _zz_168[11] = _zz_167; + _zz_168[10] = _zz_167; + _zz_168[9] = _zz_167; + _zz_168[8] = _zz_167; + _zz_168[7] = _zz_167; + _zz_168[6] = _zz_167; + _zz_168[5] = _zz_167; + _zz_168[4] = _zz_167; + _zz_168[3] = _zz_167; + _zz_168[2] = _zz_167; + _zz_168[1] = _zz_167; + _zz_168[0] = _zz_167; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_153 = execute_RS2; + _zz_169 = execute_RS2; end default : begin - _zz_153 = {_zz_152,execute_INSTRUCTION[31 : 24]}; + _zz_169 = {_zz_168,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_153; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_169; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4454,7 +4558,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_250) + case(_zz_274) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4468,7 +4572,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_250) + case(_zz_274) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4487,12 +4591,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_334) + $signed(_zz_335)); + assign writeBack_MulPlugin_result = ($signed(_zz_358) + $signed(_zz_359)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_229)begin - if(_zz_251)begin + if(_zz_253)begin + if(_zz_275)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4500,7 +4604,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_252)begin + if(_zz_276)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4511,28 +4615,28 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_339); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_363); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_154 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_154[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_340); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_341 : _zz_342); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_343[31:0]; - assign _zz_155 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_156 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_157 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_170 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_170[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_364); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_365 : _zz_366); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_367[31:0]; + assign _zz_171 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_172 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_173 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_158[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_158[31 : 0] = execute_RS1; + _zz_174[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_174[31 : 0] = execute_RS1; end - assign _zz_160 = (_zz_159 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_160 != 32'h0); + assign _zz_176 = (_zz_175 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_176 != 32'h0); assign _zz_29 = decode_SRC1_CTRL; assign _zz_27 = _zz_56; assign _zz_43 = decode_to_execute_SRC1_CTRL; @@ -4584,216 +4688,272 @@ module VexRiscv ( assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin - _zz_161 = 32'h0; + _zz_177 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_161[12 : 0] = 13'h1000; - _zz_161[25 : 20] = 6'h20; + _zz_177[12 : 0] = 13'h1000; + _zz_177[25 : 20] = 6'h20; end end always @ (*) begin - _zz_162 = 32'h0; + _zz_178 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_162[3 : 0] = 4'b1011; + _zz_178[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_163 = 32'h0; + _zz_179 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_163[4 : 0] = 5'h16; + _zz_179[4 : 0] = 5'h16; end end always @ (*) begin - _zz_164 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_164[5 : 0] = 6'h21; + _zz_180[5 : 0] = 6'h21; end end always @ (*) begin - _zz_165 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_165[31 : 30] = CsrPlugin_misa_base; - _zz_165[25 : 0] = CsrPlugin_misa_extensions; + _zz_181[31 : 30] = CsrPlugin_misa_base; + _zz_181[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_166 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_166[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_166[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_166[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_182[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_182[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_182[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_167 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_167[11 : 11] = CsrPlugin_mip_MEIP; - _zz_167[7 : 7] = CsrPlugin_mip_MTIP; - _zz_167[3 : 3] = CsrPlugin_mip_MSIP; + _zz_183[11 : 11] = CsrPlugin_mip_MEIP; + _zz_183[7 : 7] = CsrPlugin_mip_MTIP; + _zz_183[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_168 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_168[11 : 11] = CsrPlugin_mie_MEIE; - _zz_168[7 : 7] = CsrPlugin_mie_MTIE; - _zz_168[3 : 3] = CsrPlugin_mie_MSIE; + _zz_184[11 : 11] = CsrPlugin_mie_MEIE; + _zz_184[7 : 7] = CsrPlugin_mie_MTIE; + _zz_184[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_169 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_169[31 : 2] = CsrPlugin_mtvec_base; - _zz_169[1 : 0] = CsrPlugin_mtvec_mode; + _zz_185[31 : 2] = CsrPlugin_mtvec_base; + _zz_185[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_170 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_170[31 : 0] = CsrPlugin_mepc; + _zz_186[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_171[31 : 0] = CsrPlugin_mscratch; + _zz_187[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_172[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_172[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_188[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_188[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_173[31 : 0] = CsrPlugin_mtval; + _zz_189[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_174[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_175[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_176[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_177[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_178[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_179[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_180[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_181[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_198 = 32'h0; + if(execute_CsrPlugin_csr_2820)begin + _zz_198[31 : 0] = _zz_151; + end + end + + always @ (*) begin + _zz_199 = 32'h0; + if(execute_CsrPlugin_csr_2822)begin + _zz_199[31 : 0] = _zz_153; + end + end + + always @ (*) begin + _zz_200 = 32'h0; + if(execute_CsrPlugin_csr_2824)begin + _zz_200[31 : 0] = _zz_155; + end + end + + always @ (*) begin + _zz_201 = 32'h0; + if(execute_CsrPlugin_csr_2826)begin + _zz_201[31 : 0] = _zz_157; + end + end + + always @ (*) begin + _zz_202 = 32'h0; + if(execute_CsrPlugin_csr_2828)begin + _zz_202[31 : 0] = _zz_159; + end + end + + always @ (*) begin + _zz_203 = 32'h0; + if(execute_CsrPlugin_csr_2830)begin + _zz_203[31 : 0] = _zz_161; + end + end + + always @ (*) begin + _zz_204 = 32'h0; + if(execute_CsrPlugin_csr_2832)begin + _zz_204[31 : 0] = _zz_163; + end + end + + always @ (*) begin + _zz_205 = 32'h0; + if(execute_CsrPlugin_csr_2834)begin + _zz_205[31 : 0] = _zz_165; + end + end + + always @ (*) begin + _zz_206 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_182[31 : 0] = _zz_159; + _zz_206[31 : 0] = _zz_175; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_207 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_183[31 : 0] = _zz_160; + _zz_207[31 : 0] = _zz_176; end end - assign execute_CsrPlugin_readData = (((((_zz_161 | _zz_162) | (_zz_163 | _zz_164)) | ((_zz_556 | _zz_165) | (_zz_166 | _zz_167))) | (((_zz_168 | _zz_169) | (_zz_170 | _zz_171)) | ((_zz_172 | _zz_173) | (_zz_174 | _zz_175)))) | (((_zz_176 | _zz_177) | (_zz_178 | _zz_179)) | ((_zz_180 | _zz_181) | (_zz_182 | _zz_183)))); - assign iBusWishbone_ADR = {_zz_360,_zz_184}; - assign iBusWishbone_CTI = ((_zz_184 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_580 | _zz_181) | (_zz_182 | _zz_183))) | (((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191)))) | ((((_zz_192 | _zz_193) | (_zz_194 | _zz_195)) | ((_zz_196 | _zz_197) | (_zz_198 | _zz_199))) | (((_zz_200 | _zz_201) | (_zz_202 | _zz_203)) | ((_zz_204 | _zz_205) | (_zz_206 | _zz_207))))); + assign iBusWishbone_ADR = {_zz_384,_zz_208}; + assign iBusWishbone_CTI = ((_zz_208 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_253)begin + if(_zz_277)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_253)begin + if(_zz_277)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_185; + assign iBus_rsp_valid = _zz_209; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_191 = (dBus_cmd_payload_length != 3'b000); - assign _zz_187 = dBus_cmd_valid; - assign _zz_189 = dBus_cmd_payload_wr; - assign _zz_190 = (_zz_186 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_188 && (_zz_189 || _zz_190)); - assign dBusWishbone_ADR = ((_zz_191 ? {{dBus_cmd_payload_address[31 : 5],_zz_186},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_191 ? (_zz_190 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_215 = (dBus_cmd_payload_length != 3'b000); + assign _zz_211 = dBus_cmd_valid; + assign _zz_213 = dBus_cmd_payload_wr; + assign _zz_214 = (_zz_210 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_212 && (_zz_213 || _zz_214)); + assign dBusWishbone_ADR = ((_zz_215 ? {{dBus_cmd_payload_address[31 : 5],_zz_210},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_215 ? (_zz_214 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_189 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_189; + assign dBusWishbone_SEL = (_zz_213 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_213; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_188 = (_zz_187 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_187; - assign dBusWishbone_STB = _zz_187; - assign dBus_rsp_valid = _zz_192; + assign _zz_212 = (_zz_211 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_211; + assign dBusWishbone_STB = _zz_211; + assign dBus_rsp_valid = _zz_216; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -4840,15 +5000,15 @@ module VexRiscv ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_159 <= 32'h0; + _zz_175 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_184 <= 3'b000; - _zz_185 <= 1'b0; - _zz_186 <= 3'b000; - _zz_192 <= 1'b0; + _zz_208 <= 3'b000; + _zz_209 <= 1'b0; + _zz_210 <= 3'b000; + _zz_216 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -4929,7 +5089,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_254)begin + if(_zz_278)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -4961,14 +5121,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_255)begin - if(_zz_256)begin + if(_zz_279)begin + if(_zz_280)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_257)begin + if(_zz_281)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_258)begin + if(_zz_282)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -4993,7 +5153,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_237)begin + if(_zz_261)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5004,8 +5164,8 @@ module VexRiscv ( end endcase end - if(_zz_238)begin - case(_zz_239) + if(_zz_262)begin + case(_zz_263) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5031,7 +5191,7 @@ module VexRiscv ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_259)begin + if(_zz_283)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; @@ -5065,35 +5225,35 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_353[0]; - CsrPlugin_mstatus_MIE <= _zz_354[0]; + CsrPlugin_mstatus_MPIE <= _zz_377[0]; + CsrPlugin_mstatus_MIE <= _zz_378[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_356[0]; - CsrPlugin_mie_MTIE <= _zz_357[0]; - CsrPlugin_mie_MSIE <= _zz_358[0]; + CsrPlugin_mie_MEIE <= _zz_380[0]; + CsrPlugin_mie_MTIE <= _zz_381[0]; + CsrPlugin_mie_MSIE <= _zz_382[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_175 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_253)begin + if(_zz_277)begin if(iBusWishbone_ACK)begin - _zz_184 <= (_zz_184 + 3'b001); + _zz_208 <= (_zz_208 + 3'b001); end end - _zz_185 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_187 && _zz_188))begin - _zz_186 <= (_zz_186 + 3'b001); - if(_zz_190)begin - _zz_186 <= 3'b000; + _zz_209 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_211 && _zz_212))begin + _zz_210 <= (_zz_210 + 3'b001); + if(_zz_214)begin + _zz_210 <= 3'b000; end end - _zz_192 <= ((_zz_187 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_216 <= ((_zz_211 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5107,7 +5267,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_254)begin + if(_zz_278)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5134,11 +5294,11 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_234)begin + if(_zz_258)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(_zz_236)begin + if(_zz_260)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end @@ -5150,21 +5310,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_255)begin - if(_zz_256)begin + if(_zz_279)begin + if(_zz_280)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_257)begin + if(_zz_281)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_258)begin + if(_zz_282)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_237)begin + if(_zz_261)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5178,7 +5338,31 @@ module VexRiscv ( end endcase end - if(_zz_259)begin + if(_zz_152[0])begin + _zz_151 <= (_zz_151 + 32'h00000001); + end + if(_zz_154[0])begin + _zz_153 <= (_zz_153 + 32'h00000001); + end + if(_zz_156[0])begin + _zz_155 <= (_zz_155 + 32'h00000001); + end + if(_zz_158[0])begin + _zz_157 <= (_zz_157 + 32'h00000001); + end + if(_zz_160[0])begin + _zz_159 <= (_zz_159 + 32'h00000001); + end + if(_zz_162[0])begin + _zz_161 <= (_zz_161 + 32'h00000001); + end + if(_zz_164[0])begin + _zz_163 <= (_zz_163 + 32'h00000001); + end + if(_zz_166[0])begin + _zz_165 <= (_zz_165 + 32'h00000001); + end + if(_zz_283)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5188,20 +5372,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_229)begin - if(_zz_251)begin + if(_zz_253)begin + if(_zz_275)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_344[31:0]; + memory_DivPlugin_div_result <= _zz_368[31:0]; end end end - if(_zz_252)begin + if(_zz_276)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_157 ? (~ _zz_158) : _zz_158) + _zz_350); - memory_DivPlugin_rs2 <= ((_zz_156 ? (~ execute_RS2) : execute_RS2) + _zz_352); - memory_DivPlugin_div_needRevert <= ((_zz_157 ^ (_zz_156 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_173 ? (~ _zz_174) : _zz_174) + _zz_374); + memory_DivPlugin_rs2 <= ((_zz_172 ? (~ execute_RS2) : execute_RS2) + _zz_376); + memory_DivPlugin_div_needRevert <= ((_zz_173 ^ (_zz_172 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5459,6 +5643,54 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end @@ -5467,7 +5699,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_355[0]; + CsrPlugin_mip_MSIP <= _zz_379[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5488,7 +5720,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_359[0]; + CsrPlugin_mcause_interrupt <= _zz_383[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5517,6 +5749,86 @@ module VexRiscv ( CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end end + if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + end + end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index 8310b54..6613f83 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9c3529c14328ee22a18ec0f74e66ca59de7346c3 +// Git hash : 5bb91146a62643cf606443d5366c69720906549c `define Input2Kind_defaultEncoding_type [0:0] @@ -95,37 +95,37 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - reg _zz_204; - wire _zz_205; - wire [31:0] _zz_206; - wire _zz_207; - wire [31:0] _zz_208; - reg _zz_209; - wire _zz_210; - wire _zz_211; - wire [31:0] _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - wire _zz_219; wire _zz_220; - wire [3:0] _zz_221; + wire _zz_221; wire _zz_222; wire _zz_223; - reg [31:0] _zz_224; - reg [31:0] _zz_225; - reg [31:0] _zz_226; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + reg _zz_228; + wire _zz_229; + wire [31:0] _zz_230; + wire _zz_231; + wire [31:0] _zz_232; + reg _zz_233; + wire _zz_234; + wire _zz_235; + wire [31:0] _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire [3:0] _zz_245; + wire _zz_246; + wire _zz_247; + reg [31:0] _zz_248; + reg [31:0] _zz_249; + reg [31:0] _zz_250; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -158,39 +158,15 @@ module VexRiscv ( wire [3:0] dataCache_1_io_mem_cmd_payload_mask; wire [2:0] dataCache_1_io_mem_cmd_payload_length; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_227; - wire _zz_228; - wire _zz_229; - wire _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire [1:0] _zz_245; - wire _zz_246; - wire _zz_247; - wire _zz_248; - wire _zz_249; - wire _zz_250; wire _zz_251; wire _zz_252; wire _zz_253; wire _zz_254; wire _zz_255; - wire [1:0] _zz_256; + wire _zz_256; wire _zz_257; wire _zz_258; - wire [5:0] _zz_259; + wire _zz_259; wire _zz_260; wire _zz_261; wire _zz_262; @@ -198,313 +174,337 @@ module VexRiscv ( wire _zz_264; wire _zz_265; wire _zz_266; - wire [1:0] _zz_267; + wire _zz_267; wire _zz_268; wire [1:0] _zz_269; - wire [51:0] _zz_270; - wire [51:0] _zz_271; - wire [51:0] _zz_272; - wire [32:0] _zz_273; - wire [51:0] _zz_274; - wire [49:0] _zz_275; - wire [51:0] _zz_276; - wire [49:0] _zz_277; - wire [51:0] _zz_278; - wire [32:0] _zz_279; - wire [31:0] _zz_280; - wire [32:0] _zz_281; - wire [0:0] _zz_282; - wire [0:0] _zz_283; - wire [0:0] _zz_284; - wire [0:0] _zz_285; - wire [0:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; - wire [0:0] _zz_289; - wire [0:0] _zz_290; - wire [0:0] _zz_291; - wire [0:0] _zz_292; - wire [0:0] _zz_293; - wire [0:0] _zz_294; - wire [0:0] _zz_295; - wire [0:0] _zz_296; - wire [0:0] _zz_297; - wire [0:0] _zz_298; - wire [0:0] _zz_299; - wire [0:0] _zz_300; - wire [3:0] _zz_301; - wire [2:0] _zz_302; - wire [31:0] _zz_303; - wire [11:0] _zz_304; - wire [31:0] _zz_305; - wire [19:0] _zz_306; - wire [11:0] _zz_307; - wire [31:0] _zz_308; - wire [31:0] _zz_309; - wire [19:0] _zz_310; - wire [11:0] _zz_311; - wire [2:0] _zz_312; - wire [2:0] _zz_313; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire [1:0] _zz_280; + wire _zz_281; + wire _zz_282; + wire [5:0] _zz_283; + wire _zz_284; + wire _zz_285; + wire _zz_286; + wire _zz_287; + wire _zz_288; + wire _zz_289; + wire _zz_290; + wire [1:0] _zz_291; + wire _zz_292; + wire [1:0] _zz_293; + wire [51:0] _zz_294; + wire [51:0] _zz_295; + wire [51:0] _zz_296; + wire [32:0] _zz_297; + wire [51:0] _zz_298; + wire [49:0] _zz_299; + wire [51:0] _zz_300; + wire [49:0] _zz_301; + wire [51:0] _zz_302; + wire [32:0] _zz_303; + wire [31:0] _zz_304; + wire [32:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; wire [0:0] _zz_314; - wire [2:0] _zz_315; - wire [4:0] _zz_316; - wire [11:0] _zz_317; - wire [11:0] _zz_318; - wire [31:0] _zz_319; - wire [31:0] _zz_320; - wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [11:0] _zz_326; - wire [19:0] _zz_327; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire [0:0] _zz_321; + wire [0:0] _zz_322; + wire [0:0] _zz_323; + wire [0:0] _zz_324; + wire [3:0] _zz_325; + wire [2:0] _zz_326; + wire [31:0] _zz_327; wire [11:0] _zz_328; wire [31:0] _zz_329; - wire [31:0] _zz_330; - wire [31:0] _zz_331; - wire [11:0] _zz_332; - wire [19:0] _zz_333; - wire [11:0] _zz_334; - wire [2:0] _zz_335; - wire [1:0] _zz_336; - wire [1:0] _zz_337; - wire [1:0] _zz_338; - wire [1:0] _zz_339; - wire [9:0] _zz_340; - wire [7:0] _zz_341; - wire [65:0] _zz_342; - wire [65:0] _zz_343; + wire [19:0] _zz_330; + wire [11:0] _zz_331; + wire [31:0] _zz_332; + wire [31:0] _zz_333; + wire [19:0] _zz_334; + wire [11:0] _zz_335; + wire [2:0] _zz_336; + wire [2:0] _zz_337; + wire [0:0] _zz_338; + wire [2:0] _zz_339; + wire [4:0] _zz_340; + wire [11:0] _zz_341; + wire [11:0] _zz_342; + wire [31:0] _zz_343; wire [31:0] _zz_344; wire [31:0] _zz_345; - wire [0:0] _zz_346; - wire [5:0] _zz_347; - wire [32:0] _zz_348; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; wire [31:0] _zz_349; - wire [31:0] _zz_350; - wire [32:0] _zz_351; - wire [32:0] _zz_352; - wire [32:0] _zz_353; - wire [32:0] _zz_354; - wire [0:0] _zz_355; - wire [32:0] _zz_356; - wire [0:0] _zz_357; - wire [32:0] _zz_358; - wire [0:0] _zz_359; - wire [31:0] _zz_360; - wire [0:0] _zz_361; - wire [0:0] _zz_362; - wire [0:0] _zz_363; - wire [0:0] _zz_364; - wire [0:0] _zz_365; - wire [0:0] _zz_366; - wire [0:0] _zz_367; - wire [26:0] _zz_368; - wire _zz_369; - wire _zz_370; - wire [1:0] _zz_371; - wire [31:0] _zz_372; + wire [11:0] _zz_350; + wire [19:0] _zz_351; + wire [11:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; + wire [31:0] _zz_355; + wire [11:0] _zz_356; + wire [19:0] _zz_357; + wire [11:0] _zz_358; + wire [2:0] _zz_359; + wire [1:0] _zz_360; + wire [1:0] _zz_361; + wire [1:0] _zz_362; + wire [1:0] _zz_363; + wire [9:0] _zz_364; + wire [7:0] _zz_365; + wire [65:0] _zz_366; + wire [65:0] _zz_367; + wire [31:0] _zz_368; + wire [31:0] _zz_369; + wire [0:0] _zz_370; + wire [5:0] _zz_371; + wire [32:0] _zz_372; wire [31:0] _zz_373; wire [31:0] _zz_374; - wire _zz_375; - wire [0:0] _zz_376; - wire [14:0] _zz_377; - wire [31:0] _zz_378; - wire [31:0] _zz_379; - wire [31:0] _zz_380; - wire _zz_381; - wire [0:0] _zz_382; - wire [8:0] _zz_383; + wire [32:0] _zz_375; + wire [32:0] _zz_376; + wire [32:0] _zz_377; + wire [32:0] _zz_378; + wire [0:0] _zz_379; + wire [32:0] _zz_380; + wire [0:0] _zz_381; + wire [32:0] _zz_382; + wire [0:0] _zz_383; wire [31:0] _zz_384; - wire [31:0] _zz_385; - wire [31:0] _zz_386; - wire _zz_387; + wire [0:0] _zz_385; + wire [0:0] _zz_386; + wire [0:0] _zz_387; wire [0:0] _zz_388; - wire [2:0] _zz_389; - wire _zz_390; - wire _zz_391; - wire _zz_392; - wire [31:0] _zz_393; - wire [0:0] _zz_394; - wire [0:0] _zz_395; - wire _zz_396; - wire [0:0] _zz_397; - wire [28:0] _zz_398; - wire [0:0] _zz_399; + wire [0:0] _zz_389; + wire [0:0] _zz_390; + wire [0:0] _zz_391; + wire [26:0] _zz_392; + wire _zz_393; + wire _zz_394; + wire [1:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire _zz_399; wire [0:0] _zz_400; - wire [0:0] _zz_401; - wire [0:0] _zz_402; - wire _zz_403; - wire [0:0] _zz_404; - wire [23:0] _zz_405; - wire [31:0] _zz_406; - wire [31:0] _zz_407; + wire [14:0] _zz_401; + wire [31:0] _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire _zz_405; + wire [0:0] _zz_406; + wire [8:0] _zz_407; wire [31:0] _zz_408; - wire _zz_409; - wire _zz_410; - wire [0:0] _zz_411; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire _zz_411; wire [0:0] _zz_412; - wire [0:0] _zz_413; - wire [0:0] _zz_414; + wire [2:0] _zz_413; + wire _zz_414; wire _zz_415; - wire [0:0] _zz_416; - wire [20:0] _zz_417; - wire [31:0] _zz_418; - wire [31:0] _zz_419; + wire _zz_416; + wire [31:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; wire _zz_420; - wire _zz_421; - wire [0:0] _zz_422; - wire [1:0] _zz_423; + wire [0:0] _zz_421; + wire [28:0] _zz_422; + wire [0:0] _zz_423; wire [0:0] _zz_424; wire [0:0] _zz_425; - wire _zz_426; - wire [0:0] _zz_427; - wire [17:0] _zz_428; - wire [31:0] _zz_429; + wire [0:0] _zz_426; + wire _zz_427; + wire [0:0] _zz_428; + wire [23:0] _zz_429; wire [31:0] _zz_430; wire [31:0] _zz_431; wire [31:0] _zz_432; - wire [31:0] _zz_433; - wire [31:0] _zz_434; - wire [31:0] _zz_435; - wire [31:0] _zz_436; - wire _zz_437; - wire [1:0] _zz_438; - wire [1:0] _zz_439; - wire _zz_440; - wire [0:0] _zz_441; - wire [14:0] _zz_442; + wire _zz_433; + wire _zz_434; + wire [0:0] _zz_435; + wire [0:0] _zz_436; + wire [0:0] _zz_437; + wire [0:0] _zz_438; + wire _zz_439; + wire [0:0] _zz_440; + wire [20:0] _zz_441; + wire [31:0] _zz_442; wire [31:0] _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire [31:0] _zz_446; - wire [31:0] _zz_447; - wire [31:0] _zz_448; + wire _zz_444; + wire _zz_445; + wire [0:0] _zz_446; + wire [1:0] _zz_447; + wire [0:0] _zz_448; wire [0:0] _zz_449; - wire [1:0] _zz_450; - wire [4:0] _zz_451; - wire [4:0] _zz_452; - wire _zz_453; - wire [0:0] _zz_454; - wire [11:0] _zz_455; + wire _zz_450; + wire [0:0] _zz_451; + wire [17:0] _zz_452; + wire [31:0] _zz_453; + wire [31:0] _zz_454; + wire [31:0] _zz_455; wire [31:0] _zz_456; wire [31:0] _zz_457; wire [31:0] _zz_458; wire [31:0] _zz_459; wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire _zz_462; - wire [0:0] _zz_463; - wire [1:0] _zz_464; - wire [31:0] _zz_465; - wire [31:0] _zz_466; - wire [0:0] _zz_467; - wire [4:0] _zz_468; - wire [4:0] _zz_469; - wire [4:0] _zz_470; - wire _zz_471; - wire [0:0] _zz_472; - wire [8:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; + wire _zz_461; + wire [1:0] _zz_462; + wire [1:0] _zz_463; + wire _zz_464; + wire [0:0] _zz_465; + wire [14:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [0:0] _zz_473; + wire [1:0] _zz_474; + wire [4:0] _zz_475; + wire [4:0] _zz_476; wire _zz_477; - wire _zz_478; - wire [31:0] _zz_479; + wire [0:0] _zz_478; + wire [11:0] _zz_479; wire [31:0] _zz_480; - wire _zz_481; - wire [0:0] _zz_482; - wire [2:0] _zz_483; - wire [0:0] _zz_484; - wire [2:0] _zz_485; - wire [0:0] _zz_486; - wire [4:0] _zz_487; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire _zz_486; + wire [0:0] _zz_487; wire [1:0] _zz_488; - wire [1:0] _zz_489; - wire _zz_490; + wire [31:0] _zz_489; + wire [31:0] _zz_490; wire [0:0] _zz_491; - wire [6:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; - wire _zz_496; - wire [0:0] _zz_497; - wire [0:0] _zz_498; + wire [4:0] _zz_492; + wire [4:0] _zz_493; + wire [4:0] _zz_494; + wire _zz_495; + wire [0:0] _zz_496; + wire [8:0] _zz_497; + wire [31:0] _zz_498; wire [31:0] _zz_499; wire [31:0] _zz_500; wire _zz_501; - wire [0:0] _zz_502; - wire [0:0] _zz_503; - wire _zz_504; - wire [0:0] _zz_505; - wire [2:0] _zz_506; - wire _zz_507; + wire _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire _zz_505; + wire [0:0] _zz_506; + wire [2:0] _zz_507; wire [0:0] _zz_508; - wire [0:0] _zz_509; + wire [2:0] _zz_509; wire [0:0] _zz_510; - wire [0:0] _zz_511; - wire _zz_512; - wire [0:0] _zz_513; - wire [4:0] _zz_514; - wire [31:0] _zz_515; - wire [31:0] _zz_516; + wire [4:0] _zz_511; + wire [1:0] _zz_512; + wire [1:0] _zz_513; + wire _zz_514; + wire [0:0] _zz_515; + wire [6:0] _zz_516; wire [31:0] _zz_517; wire [31:0] _zz_518; wire [31:0] _zz_519; - wire [31:0] _zz_520; - wire [31:0] _zz_521; - wire [31:0] _zz_522; + wire _zz_520; + wire [0:0] _zz_521; + wire [0:0] _zz_522; wire [31:0] _zz_523; wire [31:0] _zz_524; - wire [31:0] _zz_525; - wire [31:0] _zz_526; - wire [31:0] _zz_527; + wire _zz_525; + wire [0:0] _zz_526; + wire [0:0] _zz_527; wire _zz_528; wire [0:0] _zz_529; - wire [0:0] _zz_530; - wire [31:0] _zz_531; - wire [31:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire [31:0] _zz_535; + wire [2:0] _zz_530; + wire _zz_531; + wire [0:0] _zz_532; + wire [0:0] _zz_533; + wire [0:0] _zz_534; + wire [0:0] _zz_535; wire _zz_536; - wire [3:0] _zz_537; - wire [3:0] _zz_538; - wire _zz_539; - wire [0:0] _zz_540; - wire [2:0] _zz_541; + wire [0:0] _zz_537; + wire [4:0] _zz_538; + wire [31:0] _zz_539; + wire [31:0] _zz_540; + wire [31:0] _zz_541; wire [31:0] _zz_542; wire [31:0] _zz_543; wire [31:0] _zz_544; wire [31:0] _zz_545; wire [31:0] _zz_546; wire [31:0] _zz_547; - wire _zz_548; - wire [0:0] _zz_549; - wire [1:0] _zz_550; - wire _zz_551; - wire [2:0] _zz_552; - wire [2:0] _zz_553; - wire _zz_554; - wire [0:0] _zz_555; - wire [0:0] _zz_556; + wire [31:0] _zz_548; + wire [31:0] _zz_549; + wire [31:0] _zz_550; + wire [31:0] _zz_551; + wire _zz_552; + wire [0:0] _zz_553; + wire [0:0] _zz_554; + wire [31:0] _zz_555; + wire [31:0] _zz_556; wire [31:0] _zz_557; wire [31:0] _zz_558; wire [31:0] _zz_559; - wire [31:0] _zz_560; - wire [31:0] _zz_561; - wire [31:0] _zz_562; - wire [31:0] _zz_563; - wire _zz_564; - wire _zz_565; - wire _zz_566; - wire [0:0] _zz_567; - wire [0:0] _zz_568; - wire _zz_569; - wire _zz_570; - wire _zz_571; + wire _zz_560; + wire [3:0] _zz_561; + wire [3:0] _zz_562; + wire _zz_563; + wire [0:0] _zz_564; + wire [2:0] _zz_565; + wire [31:0] _zz_566; + wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [31:0] _zz_570; + wire [31:0] _zz_571; wire _zz_572; - wire [31:0] _zz_573; + wire [0:0] _zz_573; + wire [1:0] _zz_574; + wire _zz_575; + wire [2:0] _zz_576; + wire [2:0] _zz_577; + wire _zz_578; + wire [0:0] _zz_579; + wire [0:0] _zz_580; + wire [31:0] _zz_581; + wire [31:0] _zz_582; + wire [31:0] _zz_583; + wire [31:0] _zz_584; + wire [31:0] _zz_585; + wire [31:0] _zz_586; + wire [31:0] _zz_587; + wire _zz_588; + wire _zz_589; + wire _zz_590; + wire [0:0] _zz_591; + wire [0:0] _zz_592; + wire _zz_593; + wire _zz_594; + wire _zz_595; + wire _zz_596; + wire [31:0] _zz_597; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -1103,13 +1103,29 @@ module VexRiscv ( wire [31:0] execute_CsrPlugin_readToWriteData; reg [31:0] execute_CsrPlugin_writeData; wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; wire execute_CfuPlugin_schedule; reg execute_CfuPlugin_hold; reg execute_CfuPlugin_fired; wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_152; - reg [23:0] _zz_153; - reg [31:0] _zz_154; + wire _zz_168; + reg [23:0] _zz_169; + reg [31:0] _zz_170; wire memory_CfuPlugin_rsp_valid; reg memory_CfuPlugin_rsp_ready; wire memory_CfuPlugin_rsp_payload_response_ok; @@ -1141,18 +1157,18 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_155; + wire [31:0] _zz_171; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_156; - wire _zz_157; - wire _zz_158; - reg [32:0] _zz_159; + wire [31:0] _zz_172; + wire _zz_173; + wire _zz_174; + reg [32:0] _zz_175; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_160; - wire [31:0] _zz_161; + reg [31:0] _zz_176; + wire [31:0] _zz_177; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1162,7 +1178,7 @@ module VexRiscv ( reg DebugPlugin_godmode; reg DebugPlugin_haltedByBreak; reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_162; + reg _zz_178; wire DebugPlugin_allowEBreak; reg DebugPlugin_resetIt_regNext; reg [31:0] decode_to_execute_PC; @@ -1230,7 +1246,7 @@ module VexRiscv ( reg [33:0] execute_to_memory_MUL_HH; reg [33:0] memory_to_writeBack_MUL_HH; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_163; + reg [2:0] _zz_179; reg execute_CsrPlugin_csr_3264; reg execute_CsrPlugin_csr_3857; reg execute_CsrPlugin_csr_3858; @@ -1253,24 +1269,24 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3200; reg execute_CsrPlugin_csr_3074; reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_2820; + reg execute_CsrPlugin_csr_2821; + reg execute_CsrPlugin_csr_2822; + reg execute_CsrPlugin_csr_2823; + reg execute_CsrPlugin_csr_2824; + reg execute_CsrPlugin_csr_2825; + reg execute_CsrPlugin_csr_2826; + reg execute_CsrPlugin_csr_2827; + reg execute_CsrPlugin_csr_2828; + reg execute_CsrPlugin_csr_2829; + reg execute_CsrPlugin_csr_2830; + reg execute_CsrPlugin_csr_2831; + reg execute_CsrPlugin_csr_2832; + reg execute_CsrPlugin_csr_2833; + reg execute_CsrPlugin_csr_2834; + reg execute_CsrPlugin_csr_2835; reg execute_CsrPlugin_csr_3008; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; reg [31:0] _zz_180; reg [31:0] _zz_181; reg [31:0] _zz_182; @@ -1278,16 +1294,40 @@ module VexRiscv ( reg [31:0] _zz_184; reg [31:0] _zz_185; reg [31:0] _zz_186; - reg [2:0] _zz_187; - reg _zz_188; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; + reg [31:0] _zz_199; + reg [31:0] _zz_200; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + reg [31:0] _zz_208; + reg [31:0] _zz_209; + reg [31:0] _zz_210; + reg [2:0] _zz_211; + reg _zz_212; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_189; - wire _zz_190; - wire _zz_191; - wire _zz_192; - wire _zz_193; - wire _zz_194; - reg _zz_195; + reg [2:0] _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + reg _zz_219; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; @@ -1381,362 +1421,362 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_227 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_228 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_229 = 1'b1; - assign _zz_230 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_231 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_232 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_233 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_234 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_235 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_236 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_237 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_238 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_239 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_240 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_241 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_242 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_243 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_244 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_245 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_246 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_247 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_248 = (1'b0 || (! 1'b1)); - assign _zz_249 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_250 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_251 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_252 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_253 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_254 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_255 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_256 = execute_INSTRUCTION[13 : 12]; - assign _zz_257 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_258 = (! memory_arbitration_isStuck); - assign _zz_259 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_260 = (iBus_cmd_valid || (_zz_187 != 3'b000)); - assign _zz_261 = (_zz_223 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_262 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_263 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_264 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_265 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_266 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_267 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_268 = execute_INSTRUCTION[13]; - assign _zz_269 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_270 = ($signed(_zz_271) + $signed(_zz_276)); - assign _zz_271 = ($signed(_zz_272) + $signed(_zz_274)); - assign _zz_272 = 52'h0; - assign _zz_273 = {1'b0,memory_MUL_LL}; - assign _zz_274 = {{19{_zz_273[32]}}, _zz_273}; - assign _zz_275 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_276 = {{2{_zz_275[49]}}, _zz_275}; - assign _zz_277 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_278 = {{2{_zz_277[49]}}, _zz_277}; - assign _zz_279 = ($signed(_zz_281) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_280 = _zz_279[31 : 0]; - assign _zz_281 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_282 = _zz_94[33 : 33]; - assign _zz_283 = _zz_94[32 : 32]; - assign _zz_284 = _zz_94[31 : 31]; - assign _zz_285 = _zz_94[30 : 30]; - assign _zz_286 = _zz_94[28 : 28]; - assign _zz_287 = _zz_94[25 : 25]; - assign _zz_288 = _zz_94[17 : 17]; - assign _zz_289 = _zz_94[16 : 16]; - assign _zz_290 = _zz_94[13 : 13]; - assign _zz_291 = _zz_94[12 : 12]; - assign _zz_292 = _zz_94[11 : 11]; - assign _zz_293 = _zz_94[34 : 34]; - assign _zz_294 = _zz_94[15 : 15]; - assign _zz_295 = _zz_94[5 : 5]; - assign _zz_296 = _zz_94[3 : 3]; - assign _zz_297 = _zz_94[20 : 20]; - assign _zz_298 = _zz_94[10 : 10]; - assign _zz_299 = _zz_94[4 : 4]; - assign _zz_300 = _zz_94[0 : 0]; - assign _zz_301 = (_zz_62 - 4'b0001); - assign _zz_302 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_303 = {29'd0, _zz_302}; - assign _zz_304 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_305 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_306 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_307 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_308 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_309 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_310 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_311 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_312 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_313 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_314 = execute_SRC_LESS; - assign _zz_315 = 3'b100; - assign _zz_316 = execute_INSTRUCTION[19 : 15]; - assign _zz_317 = execute_INSTRUCTION[31 : 20]; - assign _zz_318 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_319 = ($signed(_zz_320) + $signed(_zz_323)); - assign _zz_320 = ($signed(_zz_321) + $signed(_zz_322)); - assign _zz_321 = execute_SRC1; - assign _zz_322 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_323 = (execute_SRC_USE_SUB_LESS ? _zz_324 : _zz_325); - assign _zz_324 = 32'h00000001; - assign _zz_325 = 32'h0; - assign _zz_326 = execute_INSTRUCTION[31 : 20]; - assign _zz_327 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_329 = {_zz_133,execute_INSTRUCTION[31 : 20]}; - assign _zz_330 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_331 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_332 = execute_INSTRUCTION[31 : 20]; - assign _zz_333 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_334 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_335 = 3'b100; - assign _zz_336 = (_zz_148 & (~ _zz_337)); - assign _zz_337 = (_zz_148 - 2'b01); - assign _zz_338 = (_zz_150 & (~ _zz_339)); - assign _zz_339 = (_zz_150 - 2'b01); - assign _zz_340 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_341 = execute_INSTRUCTION[31 : 24]; - assign _zz_342 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_343 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_344 = writeBack_MUL_LOW[31 : 0]; - assign _zz_345 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_346 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_347 = {5'd0, _zz_346}; - assign _zz_348 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_349 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_350 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_351 = {_zz_155,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_352 = _zz_353; - assign _zz_353 = _zz_354; - assign _zz_354 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_156) : _zz_156)} + _zz_356); - assign _zz_355 = memory_DivPlugin_div_needRevert; - assign _zz_356 = {32'd0, _zz_355}; - assign _zz_357 = _zz_158; - assign _zz_358 = {32'd0, _zz_357}; - assign _zz_359 = _zz_157; - assign _zz_360 = {31'd0, _zz_359}; - assign _zz_361 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_362 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_363 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_364 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_365 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_366 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_367 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_368 = (iBus_cmd_payload_address >>> 5); - assign _zz_369 = 1'b1; - assign _zz_370 = 1'b1; - assign _zz_371 = {_zz_66,_zz_65}; - assign _zz_372 = 32'h0000106f; - assign _zz_373 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_374 = 32'h00001073; - assign _zz_375 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_376 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_377 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_378) == 32'h00000003),{(_zz_379 == _zz_380),{_zz_381,{_zz_382,_zz_383}}}}}}; - assign _zz_378 = 32'h0000207f; - assign _zz_379 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_380 = 32'h00000003; - assign _zz_381 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_382 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_383 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_384) == 32'h00005013),{(_zz_385 == _zz_386),{_zz_387,{_zz_388,_zz_389}}}}}}; - assign _zz_384 = 32'hbc00707f; - assign _zz_385 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_386 = 32'h00001013; - assign _zz_387 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_388 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_389 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; - assign _zz_390 = decode_INSTRUCTION[31]; - assign _zz_391 = decode_INSTRUCTION[31]; - assign _zz_392 = decode_INSTRUCTION[7]; - assign _zz_393 = 32'h10103050; - assign _zz_394 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_395 = 1'b0; - assign _zz_396 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_397 = 1'b0; - assign _zz_398 = {(_zz_98 != 1'b0),{({_zz_399,_zz_400} != 2'b00),{(_zz_401 != _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}; - assign _zz_399 = ((decode_INSTRUCTION & _zz_406) == 32'h10000050); - assign _zz_400 = ((decode_INSTRUCTION & _zz_407) == 32'h00000050); - assign _zz_401 = ((decode_INSTRUCTION & _zz_408) == 32'h00000050); - assign _zz_402 = 1'b0; - assign _zz_403 = ({_zz_409,_zz_410} != 2'b00); - assign _zz_404 = ({_zz_411,_zz_412} != 2'b00); - assign _zz_405 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; - assign _zz_406 = 32'h10203050; - assign _zz_407 = 32'h10103050; - assign _zz_408 = 32'h00103050; - assign _zz_409 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_410 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_411 = _zz_97; - assign _zz_412 = ((decode_INSTRUCTION & _zz_418) == 32'h00000004); - assign _zz_413 = ((decode_INSTRUCTION & _zz_419) == 32'h00000040); - assign _zz_414 = 1'b0; - assign _zz_415 = ({_zz_420,_zz_421} != 2'b00); - assign _zz_416 = ({_zz_422,_zz_423} != 3'b000); - assign _zz_417 = {(_zz_424 != _zz_425),{_zz_426,{_zz_427,_zz_428}}}; - assign _zz_418 = 32'h0000001c; - assign _zz_419 = 32'h00000058; - assign _zz_420 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_421 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_422 = ((decode_INSTRUCTION & _zz_429) == 32'h40001010); - assign _zz_423 = {(_zz_430 == _zz_431),(_zz_432 == _zz_433)}; - assign _zz_424 = ((decode_INSTRUCTION & _zz_434) == 32'h00000024); - assign _zz_425 = 1'b0; - assign _zz_426 = ((_zz_435 == _zz_436) != 1'b0); - assign _zz_427 = (_zz_437 != 1'b0); - assign _zz_428 = {(_zz_438 != _zz_439),{_zz_440,{_zz_441,_zz_442}}}; - assign _zz_429 = 32'h40003054; - assign _zz_430 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_431 = 32'h00001010; - assign _zz_432 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_433 = 32'h00001010; - assign _zz_434 = 32'h00000064; - assign _zz_435 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_436 = 32'h00001000; - assign _zz_437 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_438 = {(_zz_443 == _zz_444),(_zz_445 == _zz_446)}; - assign _zz_439 = 2'b00; - assign _zz_440 = ((_zz_447 == _zz_448) != 1'b0); - assign _zz_441 = ({_zz_449,_zz_450} != 3'b000); - assign _zz_442 = {(_zz_451 != _zz_452),{_zz_453,{_zz_454,_zz_455}}}; - assign _zz_443 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_444 = 32'h00002000; - assign _zz_445 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_446 = 32'h00001000; - assign _zz_447 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_448 = 32'h00004004; - assign _zz_449 = _zz_98; - assign _zz_450 = {(_zz_456 == _zz_457),(_zz_458 == _zz_459)}; - assign _zz_451 = {(_zz_460 == _zz_461),{_zz_462,{_zz_463,_zz_464}}}; - assign _zz_452 = 5'h0; - assign _zz_453 = ((_zz_465 == _zz_466) != 1'b0); - assign _zz_454 = ({_zz_467,_zz_468} != 6'h0); - assign _zz_455 = {(_zz_469 != _zz_470),{_zz_471,{_zz_472,_zz_473}}}; - assign _zz_456 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_457 = 32'h00000020; - assign _zz_458 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_459 = 32'h00000020; - assign _zz_460 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_461 = 32'h00002040; - assign _zz_462 = ((decode_INSTRUCTION & _zz_474) == 32'h00001040); - assign _zz_463 = (_zz_475 == _zz_476); - assign _zz_464 = {_zz_477,_zz_478}; - assign _zz_465 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_466 = 32'h00000020; - assign _zz_467 = (_zz_479 == _zz_480); - assign _zz_468 = {_zz_481,{_zz_482,_zz_483}}; - assign _zz_469 = {_zz_96,{_zz_484,_zz_485}}; - assign _zz_470 = 5'h0; - assign _zz_471 = ({_zz_486,_zz_487} != 6'h0); - assign _zz_472 = (_zz_488 != _zz_489); - assign _zz_473 = {_zz_490,{_zz_491,_zz_492}}; - assign _zz_474 = 32'h00001040; - assign _zz_475 = (decode_INSTRUCTION & 32'h00100040); - assign _zz_476 = 32'h00000040; - assign _zz_477 = ((decode_INSTRUCTION & _zz_493) == 32'h00000040); - assign _zz_478 = ((decode_INSTRUCTION & _zz_494) == 32'h0); - assign _zz_479 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_480 = 32'h00000008; - assign _zz_481 = ((decode_INSTRUCTION & _zz_495) == 32'h00000040); - assign _zz_482 = _zz_96; - assign _zz_483 = {_zz_496,{_zz_497,_zz_498}}; - assign _zz_484 = (_zz_499 == _zz_500); - assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; - assign _zz_486 = _zz_97; - assign _zz_487 = {_zz_504,{_zz_505,_zz_506}}; - assign _zz_488 = {_zz_96,_zz_507}; - assign _zz_489 = 2'b00; - assign _zz_490 = ({_zz_508,_zz_509} != 2'b00); - assign _zz_491 = (_zz_510 != _zz_511); - assign _zz_492 = {_zz_512,{_zz_513,_zz_514}}; - assign _zz_493 = 32'h00000050; - assign _zz_494 = 32'h00000038; - assign _zz_495 = 32'h00000040; - assign _zz_496 = ((decode_INSTRUCTION & _zz_515) == 32'h00004020); - assign _zz_497 = (_zz_516 == _zz_517); - assign _zz_498 = (_zz_518 == _zz_519); - assign _zz_499 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_500 = 32'h00002010; - assign _zz_501 = ((decode_INSTRUCTION & _zz_520) == 32'h00000010); - assign _zz_502 = (_zz_521 == _zz_522); - assign _zz_503 = (_zz_523 == _zz_524); - assign _zz_504 = ((decode_INSTRUCTION & _zz_525) == 32'h00001010); - assign _zz_505 = (_zz_526 == _zz_527); - assign _zz_506 = {_zz_528,{_zz_529,_zz_530}}; - assign _zz_507 = ((decode_INSTRUCTION & _zz_531) == 32'h00000020); - assign _zz_508 = _zz_96; - assign _zz_509 = (_zz_532 == _zz_533); - assign _zz_510 = (_zz_534 == _zz_535); - assign _zz_511 = 1'b0; - assign _zz_512 = (_zz_536 != 1'b0); - assign _zz_513 = (_zz_537 != _zz_538); - assign _zz_514 = {_zz_539,{_zz_540,_zz_541}}; - assign _zz_515 = 32'h00004020; - assign _zz_516 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_517 = 32'h00000010; - assign _zz_518 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_519 = 32'h00000020; - assign _zz_520 = 32'h00001030; - assign _zz_521 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_522 = 32'h00002020; - assign _zz_523 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_524 = 32'h00000020; - assign _zz_525 = 32'h00001010; - assign _zz_526 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_527 = 32'h00002010; - assign _zz_528 = ((decode_INSTRUCTION & _zz_542) == 32'h00000010); - assign _zz_529 = (_zz_543 == _zz_544); - assign _zz_530 = (_zz_545 == _zz_546); - assign _zz_531 = 32'h00000070; - assign _zz_532 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_533 = 32'h0; - assign _zz_534 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_535 = 32'h00004010; - assign _zz_536 = ((decode_INSTRUCTION & _zz_547) == 32'h00002010); - assign _zz_537 = {_zz_548,{_zz_549,_zz_550}}; - assign _zz_538 = 4'b0000; - assign _zz_539 = (_zz_551 != 1'b0); - assign _zz_540 = (_zz_552 != _zz_553); - assign _zz_541 = {_zz_554,{_zz_555,_zz_556}}; - assign _zz_542 = 32'h00000050; - assign _zz_543 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_544 = 32'h00000004; - assign _zz_545 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_546 = 32'h0; - assign _zz_547 = 32'h00006014; - assign _zz_548 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_549 = ((decode_INSTRUCTION & _zz_557) == 32'h0); - assign _zz_550 = {(_zz_558 == _zz_559),(_zz_560 == _zz_561)}; - assign _zz_551 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_552 = {(_zz_562 == _zz_563),{_zz_564,_zz_565}}; - assign _zz_553 = 3'b000; - assign _zz_554 = ({_zz_566,_zz_95} != 2'b00); - assign _zz_555 = ({_zz_567,_zz_568} != 2'b00); - assign _zz_556 = (_zz_569 != 1'b0); - assign _zz_557 = 32'h00000018; - assign _zz_558 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_559 = 32'h00002000; - assign _zz_560 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_561 = 32'h00001000; - assign _zz_562 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_563 = 32'h00000040; - assign _zz_564 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_565 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_566 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_567 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_568 = _zz_95; - assign _zz_569 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); - assign _zz_570 = execute_INSTRUCTION[31]; - assign _zz_571 = execute_INSTRUCTION[31]; - assign _zz_572 = execute_INSTRUCTION[7]; - assign _zz_573 = 32'h0; + assign _zz_251 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_253 = 1'b1; + assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_256 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_257 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_258 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_259 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_260 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_261 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_262 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_263 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_264 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_265 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_268 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_269 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_270 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_271 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_272 = (1'b0 || (! 1'b1)); + assign _zz_273 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_274 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_275 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_276 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_277 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_278 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_280 = execute_INSTRUCTION[13 : 12]; + assign _zz_281 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_282 = (! memory_arbitration_isStuck); + assign _zz_283 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_284 = (iBus_cmd_valid || (_zz_211 != 3'b000)); + assign _zz_285 = (_zz_247 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_286 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_287 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_288 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_289 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_290 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_291 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_292 = execute_INSTRUCTION[13]; + assign _zz_293 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_294 = ($signed(_zz_295) + $signed(_zz_300)); + assign _zz_295 = ($signed(_zz_296) + $signed(_zz_298)); + assign _zz_296 = 52'h0; + assign _zz_297 = {1'b0,memory_MUL_LL}; + assign _zz_298 = {{19{_zz_297[32]}}, _zz_297}; + assign _zz_299 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; + assign _zz_301 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_302 = {{2{_zz_301[49]}}, _zz_301}; + assign _zz_303 = ($signed(_zz_305) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_304 = _zz_303[31 : 0]; + assign _zz_305 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_306 = _zz_94[33 : 33]; + assign _zz_307 = _zz_94[32 : 32]; + assign _zz_308 = _zz_94[31 : 31]; + assign _zz_309 = _zz_94[30 : 30]; + assign _zz_310 = _zz_94[28 : 28]; + assign _zz_311 = _zz_94[25 : 25]; + assign _zz_312 = _zz_94[17 : 17]; + assign _zz_313 = _zz_94[16 : 16]; + assign _zz_314 = _zz_94[13 : 13]; + assign _zz_315 = _zz_94[12 : 12]; + assign _zz_316 = _zz_94[11 : 11]; + assign _zz_317 = _zz_94[34 : 34]; + assign _zz_318 = _zz_94[15 : 15]; + assign _zz_319 = _zz_94[5 : 5]; + assign _zz_320 = _zz_94[3 : 3]; + assign _zz_321 = _zz_94[20 : 20]; + assign _zz_322 = _zz_94[10 : 10]; + assign _zz_323 = _zz_94[4 : 4]; + assign _zz_324 = _zz_94[0 : 0]; + assign _zz_325 = (_zz_62 - 4'b0001); + assign _zz_326 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_327 = {29'd0, _zz_326}; + assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_329 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_331 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_332 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_333 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_334 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_335 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_338 = execute_SRC_LESS; + assign _zz_339 = 3'b100; + assign _zz_340 = execute_INSTRUCTION[19 : 15]; + assign _zz_341 = execute_INSTRUCTION[31 : 20]; + assign _zz_342 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_343 = ($signed(_zz_344) + $signed(_zz_347)); + assign _zz_344 = ($signed(_zz_345) + $signed(_zz_346)); + assign _zz_345 = execute_SRC1; + assign _zz_346 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_347 = (execute_SRC_USE_SUB_LESS ? _zz_348 : _zz_349); + assign _zz_348 = 32'h00000001; + assign _zz_349 = 32'h0; + assign _zz_350 = execute_INSTRUCTION[31 : 20]; + assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_353 = {_zz_133,execute_INSTRUCTION[31 : 20]}; + assign _zz_354 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_355 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_356 = execute_INSTRUCTION[31 : 20]; + assign _zz_357 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_359 = 3'b100; + assign _zz_360 = (_zz_148 & (~ _zz_361)); + assign _zz_361 = (_zz_148 - 2'b01); + assign _zz_362 = (_zz_150 & (~ _zz_363)); + assign _zz_363 = (_zz_150 - 2'b01); + assign _zz_364 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_365 = execute_INSTRUCTION[31 : 24]; + assign _zz_366 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_367 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_368 = writeBack_MUL_LOW[31 : 0]; + assign _zz_369 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_370 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_371 = {5'd0, _zz_370}; + assign _zz_372 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_373 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_374 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_375 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_376 = _zz_377; + assign _zz_377 = _zz_378; + assign _zz_378 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_380); + assign _zz_379 = memory_DivPlugin_div_needRevert; + assign _zz_380 = {32'd0, _zz_379}; + assign _zz_381 = _zz_174; + assign _zz_382 = {32'd0, _zz_381}; + assign _zz_383 = _zz_173; + assign _zz_384 = {31'd0, _zz_383}; + assign _zz_385 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_386 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_387 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_388 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_391 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_392 = (iBus_cmd_payload_address >>> 5); + assign _zz_393 = 1'b1; + assign _zz_394 = 1'b1; + assign _zz_395 = {_zz_66,_zz_65}; + assign _zz_396 = 32'h0000106f; + assign _zz_397 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_398 = 32'h00001073; + assign _zz_399 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_400 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_401 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_402) == 32'h00000003),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; + assign _zz_402 = 32'h0000207f; + assign _zz_403 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_404 = 32'h00000003; + assign _zz_405 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_406 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_407 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_408) == 32'h00005013),{(_zz_409 == _zz_410),{_zz_411,{_zz_412,_zz_413}}}}}}; + assign _zz_408 = 32'hbc00707f; + assign _zz_409 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_410 = 32'h00001013; + assign _zz_411 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_412 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_413 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_414 = decode_INSTRUCTION[31]; + assign _zz_415 = decode_INSTRUCTION[31]; + assign _zz_416 = decode_INSTRUCTION[7]; + assign _zz_417 = 32'h10103050; + assign _zz_418 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_419 = 1'b0; + assign _zz_420 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_421 = 1'b0; + assign _zz_422 = {(_zz_98 != 1'b0),{({_zz_423,_zz_424} != 2'b00),{(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}}}; + assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h10000050); + assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00000050); + assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00000050); + assign _zz_426 = 1'b0; + assign _zz_427 = ({_zz_433,_zz_434} != 2'b00); + assign _zz_428 = ({_zz_435,_zz_436} != 2'b00); + assign _zz_429 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; + assign _zz_430 = 32'h10203050; + assign _zz_431 = 32'h10103050; + assign _zz_432 = 32'h00103050; + assign _zz_433 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_434 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_435 = _zz_97; + assign _zz_436 = ((decode_INSTRUCTION & _zz_442) == 32'h00000004); + assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000040); + assign _zz_438 = 1'b0; + assign _zz_439 = ({_zz_444,_zz_445} != 2'b00); + assign _zz_440 = ({_zz_446,_zz_447} != 3'b000); + assign _zz_441 = {(_zz_448 != _zz_449),{_zz_450,{_zz_451,_zz_452}}}; + assign _zz_442 = 32'h0000001c; + assign _zz_443 = 32'h00000058; + assign _zz_444 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_445 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h40001010); + assign _zz_447 = {(_zz_454 == _zz_455),(_zz_456 == _zz_457)}; + assign _zz_448 = ((decode_INSTRUCTION & _zz_458) == 32'h00000024); + assign _zz_449 = 1'b0; + assign _zz_450 = ((_zz_459 == _zz_460) != 1'b0); + assign _zz_451 = (_zz_461 != 1'b0); + assign _zz_452 = {(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}; + assign _zz_453 = 32'h40003054; + assign _zz_454 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_455 = 32'h00001010; + assign _zz_456 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_457 = 32'h00001010; + assign _zz_458 = 32'h00000064; + assign _zz_459 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_460 = 32'h00001000; + assign _zz_461 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_462 = {(_zz_467 == _zz_468),(_zz_469 == _zz_470)}; + assign _zz_463 = 2'b00; + assign _zz_464 = ((_zz_471 == _zz_472) != 1'b0); + assign _zz_465 = ({_zz_473,_zz_474} != 3'b000); + assign _zz_466 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; + assign _zz_467 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_468 = 32'h00002000; + assign _zz_469 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_470 = 32'h00001000; + assign _zz_471 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_472 = 32'h00004004; + assign _zz_473 = _zz_98; + assign _zz_474 = {(_zz_480 == _zz_481),(_zz_482 == _zz_483)}; + assign _zz_475 = {(_zz_484 == _zz_485),{_zz_486,{_zz_487,_zz_488}}}; + assign _zz_476 = 5'h0; + assign _zz_477 = ((_zz_489 == _zz_490) != 1'b0); + assign _zz_478 = ({_zz_491,_zz_492} != 6'h0); + assign _zz_479 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; + assign _zz_480 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_481 = 32'h00000020; + assign _zz_482 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_483 = 32'h00000020; + assign _zz_484 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_485 = 32'h00002040; + assign _zz_486 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); + assign _zz_487 = (_zz_499 == _zz_500); + assign _zz_488 = {_zz_501,_zz_502}; + assign _zz_489 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_490 = 32'h00000020; + assign _zz_491 = (_zz_503 == _zz_504); + assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; + assign _zz_493 = {_zz_96,{_zz_508,_zz_509}}; + assign _zz_494 = 5'h0; + assign _zz_495 = ({_zz_510,_zz_511} != 6'h0); + assign _zz_496 = (_zz_512 != _zz_513); + assign _zz_497 = {_zz_514,{_zz_515,_zz_516}}; + assign _zz_498 = 32'h00001040; + assign _zz_499 = (decode_INSTRUCTION & 32'h00100040); + assign _zz_500 = 32'h00000040; + assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00000040); + assign _zz_502 = ((decode_INSTRUCTION & _zz_518) == 32'h0); + assign _zz_503 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_504 = 32'h00000008; + assign _zz_505 = ((decode_INSTRUCTION & _zz_519) == 32'h00000040); + assign _zz_506 = _zz_96; + assign _zz_507 = {_zz_520,{_zz_521,_zz_522}}; + assign _zz_508 = (_zz_523 == _zz_524); + assign _zz_509 = {_zz_525,{_zz_526,_zz_527}}; + assign _zz_510 = _zz_97; + assign _zz_511 = {_zz_528,{_zz_529,_zz_530}}; + assign _zz_512 = {_zz_96,_zz_531}; + assign _zz_513 = 2'b00; + assign _zz_514 = ({_zz_532,_zz_533} != 2'b00); + assign _zz_515 = (_zz_534 != _zz_535); + assign _zz_516 = {_zz_536,{_zz_537,_zz_538}}; + assign _zz_517 = 32'h00000050; + assign _zz_518 = 32'h00000038; + assign _zz_519 = 32'h00000040; + assign _zz_520 = ((decode_INSTRUCTION & _zz_539) == 32'h00004020); + assign _zz_521 = (_zz_540 == _zz_541); + assign _zz_522 = (_zz_542 == _zz_543); + assign _zz_523 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_524 = 32'h00002010; + assign _zz_525 = ((decode_INSTRUCTION & _zz_544) == 32'h00000010); + assign _zz_526 = (_zz_545 == _zz_546); + assign _zz_527 = (_zz_547 == _zz_548); + assign _zz_528 = ((decode_INSTRUCTION & _zz_549) == 32'h00001010); + assign _zz_529 = (_zz_550 == _zz_551); + assign _zz_530 = {_zz_552,{_zz_553,_zz_554}}; + assign _zz_531 = ((decode_INSTRUCTION & _zz_555) == 32'h00000020); + assign _zz_532 = _zz_96; + assign _zz_533 = (_zz_556 == _zz_557); + assign _zz_534 = (_zz_558 == _zz_559); + assign _zz_535 = 1'b0; + assign _zz_536 = (_zz_560 != 1'b0); + assign _zz_537 = (_zz_561 != _zz_562); + assign _zz_538 = {_zz_563,{_zz_564,_zz_565}}; + assign _zz_539 = 32'h00004020; + assign _zz_540 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_541 = 32'h00000010; + assign _zz_542 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_543 = 32'h00000020; + assign _zz_544 = 32'h00001030; + assign _zz_545 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_546 = 32'h00002020; + assign _zz_547 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_548 = 32'h00000020; + assign _zz_549 = 32'h00001010; + assign _zz_550 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_551 = 32'h00002010; + assign _zz_552 = ((decode_INSTRUCTION & _zz_566) == 32'h00000010); + assign _zz_553 = (_zz_567 == _zz_568); + assign _zz_554 = (_zz_569 == _zz_570); + assign _zz_555 = 32'h00000070; + assign _zz_556 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_557 = 32'h0; + assign _zz_558 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_559 = 32'h00004010; + assign _zz_560 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); + assign _zz_561 = {_zz_572,{_zz_573,_zz_574}}; + assign _zz_562 = 4'b0000; + assign _zz_563 = (_zz_575 != 1'b0); + assign _zz_564 = (_zz_576 != _zz_577); + assign _zz_565 = {_zz_578,{_zz_579,_zz_580}}; + assign _zz_566 = 32'h00000050; + assign _zz_567 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_568 = 32'h00000004; + assign _zz_569 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_570 = 32'h0; + assign _zz_571 = 32'h00006014; + assign _zz_572 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_573 = ((decode_INSTRUCTION & _zz_581) == 32'h0); + assign _zz_574 = {(_zz_582 == _zz_583),(_zz_584 == _zz_585)}; + assign _zz_575 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_576 = {(_zz_586 == _zz_587),{_zz_588,_zz_589}}; + assign _zz_577 = 3'b000; + assign _zz_578 = ({_zz_590,_zz_95} != 2'b00); + assign _zz_579 = ({_zz_591,_zz_592} != 2'b00); + assign _zz_580 = (_zz_593 != 1'b0); + assign _zz_581 = 32'h00000018; + assign _zz_582 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_583 = 32'h00002000; + assign _zz_584 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_585 = 32'h00001000; + assign _zz_586 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_587 = 32'h00000040; + assign _zz_588 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_589 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_590 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_591 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_592 = _zz_95; + assign _zz_593 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_594 = execute_INSTRUCTION[31]; + assign _zz_595 = execute_INSTRUCTION[31]; + assign _zz_596 = execute_INSTRUCTION[7]; + assign _zz_597 = 32'h0; always @ (posedge clk) begin - if(_zz_369) begin - _zz_224 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + if(_zz_393) begin + _zz_248 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; end end always @ (posedge clk) begin - if(_zz_370) begin - _zz_225 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + if(_zz_394) begin + _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; end end @@ -1747,13 +1787,13 @@ module VexRiscv ( end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_196 ), //i - .io_cpu_prefetch_isValid (_zz_197 ), //i + .io_flush (_zz_220 ), //i + .io_cpu_prefetch_isValid (_zz_221 ), //i .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_198 ), //i - .io_cpu_fetch_isStuck (_zz_199 ), //i - .io_cpu_fetch_isRemoved (_zz_200 ), //i + .io_cpu_fetch_isValid (_zz_222 ), //i + .io_cpu_fetch_isStuck (_zz_223 ), //i + .io_cpu_fetch_isRemoved (_zz_224 ), //i .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i @@ -1766,8 +1806,8 @@ module VexRiscv ( .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_201 ), //i - .io_cpu_decode_isStuck (_zz_202 ), //i + .io_cpu_decode_isValid (_zz_225 ), //i + .io_cpu_decode_isStuck (_zz_226 ), //i .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o @@ -1775,8 +1815,8 @@ module VexRiscv ( .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_203 ), //i - .io_cpu_fill_valid (_zz_204 ), //i + .io_cpu_decode_isUser (_zz_227 ), //i + .io_cpu_fill_valid (_zz_228 ), //i .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o .io_mem_cmd_ready (iBus_cmd_ready ), //i @@ -1785,26 +1825,26 @@ module VexRiscv ( .io_mem_rsp_valid (iBus_rsp_valid ), //i .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_16 (_zz_163[2:0] ), //i + ._zz_16 (_zz_179[2:0] ), //i ._zz_17 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i .clk (clk ), //i .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_205 ), //i - .io_cpu_execute_address (_zz_206[31:0] ), //i + .io_cpu_execute_isValid (_zz_229 ), //i + .io_cpu_execute_address (_zz_230[31:0] ), //i .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i .io_cpu_execute_args_data (_zz_89[31:0] ), //i .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_207 ), //i + .io_cpu_memory_isValid (_zz_231 ), //i .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_208[31:0] ), //i + .io_cpu_memory_address (_zz_232[31:0] ), //i .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_209 ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_233 ), //i .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i @@ -1812,31 +1852,31 @@ module VexRiscv ( .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_210 ), //i + .io_cpu_writeBack_isValid (_zz_234 ), //i .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_211 ), //i + .io_cpu_writeBack_isUser (_zz_235 ), //i .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_212[31:0] ), //i + .io_cpu_writeBack_address (_zz_236[31:0] ), //i .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_213 ), //i - .io_cpu_writeBack_fence_SR (_zz_214 ), //i - .io_cpu_writeBack_fence_SO (_zz_215 ), //i - .io_cpu_writeBack_fence_SI (_zz_216 ), //i - .io_cpu_writeBack_fence_PW (_zz_217 ), //i - .io_cpu_writeBack_fence_PR (_zz_218 ), //i - .io_cpu_writeBack_fence_PO (_zz_219 ), //i - .io_cpu_writeBack_fence_PI (_zz_220 ), //i - .io_cpu_writeBack_fence_FM (_zz_221[3:0] ), //i + .io_cpu_writeBack_fence_SW (_zz_237 ), //i + .io_cpu_writeBack_fence_SR (_zz_238 ), //i + .io_cpu_writeBack_fence_SO (_zz_239 ), //i + .io_cpu_writeBack_fence_SI (_zz_240 ), //i + .io_cpu_writeBack_fence_PW (_zz_241 ), //i + .io_cpu_writeBack_fence_PR (_zz_242 ), //i + .io_cpu_writeBack_fence_PO (_zz_243 ), //i + .io_cpu_writeBack_fence_PI (_zz_244 ), //i + .io_cpu_writeBack_fence_FM (_zz_245[3:0] ), //i .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_222 ), //i + .io_cpu_flush_valid (_zz_246 ), //i .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_223 ), //i + .io_mem_cmd_ready (_zz_247 ), //i .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o @@ -1852,18 +1892,18 @@ module VexRiscv ( .reset (reset ) //i ); always @(*) begin - case(_zz_371) + case(_zz_395) 2'b00 : begin - _zz_226 = DBusCachedPlugin_redoBranch_payload; + _zz_250 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_226 = CsrPlugin_jumpInterface_payload; + _zz_250 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_226 = BranchPlugin_jumpInterface_payload; + _zz_250 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_226 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_250 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end @@ -2618,7 +2658,7 @@ module VexRiscv ( end `endif - assign memory_MUL_LOW = ($signed(_zz_270) + $signed(_zz_278)); + assign memory_MUL_LOW = ($signed(_zz_294) + $signed(_zz_302)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2626,42 +2666,42 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_280; + assign execute_SHIFT_RIGHT = _zz_304; assign execute_REGFILE_WRITE_DATA = _zz_109; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_206[1 : 0]; + assign execute_MEMORY_ADDRESS_LOW = _zz_230[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_282[0]; - assign decode_IS_RS1_SIGNED = _zz_283[0]; - assign decode_IS_DIV = _zz_284[0]; + assign decode_IS_RS2_SIGNED = _zz_306[0]; + assign decode_IS_RS1_SIGNED = _zz_307[0]; + assign decode_IS_DIV = _zz_308[0]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_285[0]; + assign decode_IS_MUL = _zz_309[0]; assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_286[0]; + assign decode_CfuPlugin_CFU_ENABLE = _zz_310[0]; assign _zz_4 = _zz_5; assign _zz_6 = _zz_7; assign decode_ENV_CTRL = _zz_8; assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_287[0]; + assign decode_IS_CSR = _zz_311[0]; assign _zz_11 = _zz_12; assign _zz_13 = _zz_14; assign decode_SHIFT_CTRL = _zz_15; assign _zz_16 = _zz_17; assign decode_ALU_BITWISE_CTRL = _zz_18; assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_288[0]; - assign decode_MEMORY_MANAGMENT = _zz_289[0]; + assign decode_SRC_LESS_UNSIGNED = _zz_312[0]; + assign decode_MEMORY_MANAGMENT = _zz_313[0]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_290[0]; + assign decode_MEMORY_WR = _zz_314[0]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_291[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_292[0]; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_315[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_316[0]; assign decode_SRC2_CTRL = _zz_21; assign _zz_22 = _zz_23; assign decode_ALU_CTRL = _zz_24; @@ -2675,7 +2715,7 @@ module VexRiscv ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_293[0]; + assign decode_IS_EBREAK = _zz_317[0]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2716,11 +2756,11 @@ module VexRiscv ( assign execute_RS1 = decode_to_execute_RS1; assign execute_BRANCH_COND_RESULT = _zz_131; assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_294[0]; - assign decode_RS1_USE = _zz_295[0]; + assign decode_RS2_USE = _zz_318[0]; + assign decode_RS1_USE = _zz_319[0]; always @ (*) begin _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_227)begin + if(_zz_251)begin _zz_37 = execute_CsrPlugin_readData; end end @@ -2738,21 +2778,21 @@ module VexRiscv ( decode_RS2 = _zz_122; end end - if(_zz_228)begin - if(_zz_229)begin + if(_zz_252)begin + if(_zz_253)begin if(_zz_124)begin decode_RS2 = _zz_57; end end end - if(_zz_230)begin + if(_zz_254)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_126)begin decode_RS2 = _zz_38; end end end - if(_zz_231)begin + if(_zz_255)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_128)begin decode_RS2 = _zz_37; @@ -2768,21 +2808,21 @@ module VexRiscv ( decode_RS1 = _zz_122; end end - if(_zz_228)begin - if(_zz_229)begin + if(_zz_252)begin + if(_zz_253)begin if(_zz_123)begin decode_RS1 = _zz_57; end end end - if(_zz_230)begin + if(_zz_254)begin if(memory_BYPASSABLE_MEMORY_STAGE)begin if(_zz_125)begin decode_RS1 = _zz_38; end end end - if(_zz_231)begin + if(_zz_255)begin if(execute_BYPASSABLE_EXECUTE_STAGE)begin if(_zz_127)begin decode_RS1 = _zz_37; @@ -2809,7 +2849,7 @@ module VexRiscv ( if(memory_CfuPlugin_CFU_IN_FLIGHT)begin _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; end - if(_zz_232)begin + if(_zz_256)begin _zz_38 = memory_DivPlugin_div_result; end end @@ -2822,8 +2862,8 @@ module VexRiscv ( assign _zz_41 = execute_PC; assign execute_SRC2_CTRL = _zz_42; assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_296[0]; - assign decode_SRC_ADD_ZERO = _zz_297[0]; + assign decode_SRC_USE_SUB_LESS = _zz_320[0]; + assign decode_SRC_ADD_ZERO = _zz_321[0]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; assign execute_ALU_CTRL = _zz_44; @@ -2841,25 +2881,25 @@ module VexRiscv ( assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_298[0]; + decode_REGFILE_WRITE_VALID = _zz_322[0]; if((decode_INSTRUCTION[11 : 7] == 5'h0))begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_372) == 32'h00000003),{(_zz_373 == _zz_374),{_zz_375,{_zz_376,_zz_377}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}} != 22'h0); always @ (*) begin _zz_57 = writeBack_REGFILE_WRITE_DATA; if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin _zz_57 = writeBack_DBusCachedPlugin_rspFormated; end if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_269) + case(_zz_293) 2'b00 : begin - _zz_57 = _zz_344; + _zz_57 = _zz_368; end default : begin - _zz_57 = _zz_345; + _zz_57 = _zz_369; end endcase end @@ -2878,32 +2918,32 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_299[0]; - assign decode_FLUSH_ALL = _zz_300[0]; + assign decode_MEMORY_ENABLE = _zz_323[0]; + assign decode_FLUSH_ALL = _zz_324[0]; always @ (*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_233)begin + if(_zz_257)begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_234)begin + if(_zz_258)begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_235)begin + if(_zz_259)begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end always @ (*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_236)begin + if(_zz_260)begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end @@ -2932,7 +2972,7 @@ module VexRiscv ( if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin decode_arbitration_haltItself = 1'b1; end - case(_zz_163) + case(_zz_179) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2956,7 +2996,7 @@ module VexRiscv ( always @ (*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_237)begin + if(_zz_261)begin decode_arbitration_removeIt = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -2970,22 +3010,22 @@ module VexRiscv ( if(IBusCachedPlugin_predictionJumpInterface_valid)begin decode_arbitration_flushNext = 1'b1; end - if(_zz_237)begin + if(_zz_261)begin decode_arbitration_flushNext = 1'b1; end end always @ (*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_222 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(((_zz_246 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin execute_arbitration_haltItself = 1'b1; end - if(_zz_238)begin + if(_zz_262)begin if((! execute_CsrPlugin_wfiWake))begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_227)begin + if(_zz_251)begin if(execute_CsrPlugin_blockedBySideEffects)begin execute_arbitration_haltItself = 1'b1; end @@ -3000,14 +3040,14 @@ module VexRiscv ( if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_239)begin + if(_zz_263)begin execute_arbitration_haltByOther = 1'b1; end end always @ (*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_240)begin + if(_zz_264)begin execute_arbitration_removeIt = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -3017,8 +3057,8 @@ module VexRiscv ( always @ (*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_239)begin - if(_zz_241)begin + if(_zz_263)begin + if(_zz_265)begin execute_arbitration_flushIt = 1'b1; end end @@ -3029,11 +3069,11 @@ module VexRiscv ( if(BranchPlugin_jumpInterface_valid)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_240)begin + if(_zz_264)begin execute_arbitration_flushNext = 1'b1; end - if(_zz_239)begin - if(_zz_241)begin + if(_zz_263)begin + if(_zz_265)begin execute_arbitration_flushNext = 1'b1; end end @@ -3046,7 +3086,7 @@ module VexRiscv ( memory_arbitration_haltItself = 1'b1; end end - if(_zz_232)begin + if(_zz_256)begin if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin memory_arbitration_haltItself = 1'b1; end @@ -3105,10 +3145,10 @@ module VexRiscv ( if(DBusCachedPlugin_exceptionBus_valid)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_242)begin + if(_zz_266)begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_243)begin + if(_zz_267)begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3122,21 +3162,21 @@ module VexRiscv ( if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_242)begin + if(_zz_266)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_243)begin + if(_zz_267)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_239)begin - if(_zz_241)begin + if(_zz_263)begin + if(_zz_265)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end if(DebugPlugin_haltIt)begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_244)begin + if(_zz_268)begin IBusCachedPlugin_fetcherHalt = 1'b1; end end @@ -3157,7 +3197,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_238)begin + if(_zz_262)begin CsrPlugin_inWfi = 1'b1; end end @@ -3171,21 +3211,21 @@ module VexRiscv ( always @ (*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_242)begin + if(_zz_266)begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_243)begin + if(_zz_267)begin CsrPlugin_jumpInterface_valid = 1'b1; end end always @ (*) begin CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_242)begin + if(_zz_266)begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_243)begin - case(_zz_245) + if(_zz_267)begin + case(_zz_269) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3219,11 +3259,11 @@ module VexRiscv ( assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_63 = (_zz_62 & (~ _zz_301)); + assign _zz_63 = (_zz_62 & (~ _zz_325)); assign _zz_64 = _zz_63[3]; assign _zz_65 = (_zz_63[1] || _zz_64); assign _zz_66 = (_zz_63[2] || _zz_64); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_226; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_250; always @ (*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; if(IBusCachedPlugin_fetchPc_redo_valid)begin @@ -3243,7 +3283,7 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_303); + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_327); if(IBusCachedPlugin_fetchPc_redo_valid)begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end @@ -3335,7 +3375,7 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); always @ (*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_163) + case(_zz_179) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3347,7 +3387,7 @@ module VexRiscv ( endcase end - assign _zz_76 = _zz_304[11]; + assign _zz_76 = _zz_328[11]; always @ (*) begin _zz_77[18] = _zz_76; _zz_77[17] = _zz_76; @@ -3371,13 +3411,13 @@ module VexRiscv ( end always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_305[31])); + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_329[31])); if(_zz_82)begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_78 = _zz_306[19]; + assign _zz_78 = _zz_330[19]; always @ (*) begin _zz_79[10] = _zz_78; _zz_79[9] = _zz_78; @@ -3392,7 +3432,7 @@ module VexRiscv ( _zz_79[0] = _zz_78; end - assign _zz_80 = _zz_307[11]; + assign _zz_80 = _zz_331[11]; always @ (*) begin _zz_81[18] = _zz_80; _zz_81[17] = _zz_80; @@ -3418,16 +3458,16 @@ module VexRiscv ( always @ (*) begin case(decode_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_82 = _zz_308[1]; + _zz_82 = _zz_332[1]; end default : begin - _zz_82 = _zz_309[1]; + _zz_82 = _zz_333[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_83 = _zz_310[19]; + assign _zz_83 = _zz_334[19]; always @ (*) begin _zz_84[10] = _zz_83; _zz_84[9] = _zz_83; @@ -3442,7 +3482,7 @@ module VexRiscv ( _zz_84[0] = _zz_83; end - assign _zz_85 = _zz_311[11]; + assign _zz_85 = _zz_335[11]; always @ (*) begin _zz_86[18] = _zz_85; _zz_86[17] = _zz_85; @@ -3465,7 +3505,7 @@ module VexRiscv ( _zz_86[0] = _zz_85; end - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_390,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_391,_zz_392},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_414,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_415,_zz_416},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; always @ (*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; @@ -3474,52 +3514,52 @@ module VexRiscv ( assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_197 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_198 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_199 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_198; + assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_222; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_201 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_202 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_203 = (CsrPlugin_privilege == 2'b00); + assign _zz_225 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_226 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_227 = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; always @ (*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_236)begin + if(_zz_260)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_234)begin + if(_zz_258)begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end always @ (*) begin - _zz_204 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_234)begin - _zz_204 = 1'b1; + _zz_228 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_258)begin + _zz_228 = 1'b1; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_235)begin + if(_zz_259)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_233)begin + if(_zz_257)begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end always @ (*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_235)begin + if(_zz_259)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_233)begin + if(_zz_257)begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end @@ -3529,9 +3569,9 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_196 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_220 = (decode_arbitration_isValid && decode_FLUSH_ALL); assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_223 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_247 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); @@ -3558,8 +3598,8 @@ module VexRiscv ( assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_205 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_206 = execute_SRC_ADD; + assign _zz_229 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_230 = execute_SRC_ADD; always @ (*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin @@ -3574,27 +3614,27 @@ module VexRiscv ( endcase end - assign _zz_222 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_207 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_208 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_207; + assign _zz_246 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_231 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_232 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_231; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_208; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_232; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); always @ (*) begin - _zz_209 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + _zz_233 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_209 = 1'b1; + _zz_233 = 1'b1; end end - assign _zz_210 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_211 = (CsrPlugin_privilege == 2'b00); - assign _zz_212 = writeBack_REGFILE_WRITE_DATA; + assign _zz_234 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_235 = (CsrPlugin_privilege == 2'b00); + assign _zz_236 = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_246)begin + if(_zz_270)begin if(dataCache_1_io_cpu_redo)begin DBusCachedPlugin_redoBranch_valid = 1'b1; end @@ -3604,7 +3644,7 @@ module VexRiscv ( assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; always @ (*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_246)begin + if(_zz_270)begin if(dataCache_1_io_cpu_writeBack_accessError)begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end @@ -3623,15 +3663,15 @@ module VexRiscv ( assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; always @ (*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_246)begin + if(_zz_270)begin if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_312}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; end if(dataCache_1_io_cpu_writeBack_mmuException)begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_313}; + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; end end end @@ -3704,7 +3744,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_267) + case(_zz_291) 2'b00 : begin writeBack_DBusCachedPlugin_rspFormated = _zz_91; end @@ -3740,7 +3780,7 @@ module VexRiscv ( assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_94 = {(((decode_INSTRUCTION & _zz_393) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_394 != _zz_395),{_zz_396,{_zz_397,_zz_398}}}}}}; + assign _zz_94 = {(((decode_INSTRUCTION & _zz_417) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}; assign _zz_100 = _zz_94[2 : 1]; assign _zz_56 = _zz_100; assign _zz_101 = _zz_94[7 : 6]; @@ -3762,8 +3802,8 @@ module VexRiscv ( assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_224; - assign decode_RegFilePlugin_rs2Data = _zz_225; + assign decode_RegFilePlugin_rs1Data = _zz_248; + assign decode_RegFilePlugin_rs2Data = _zz_249; always @ (*) begin lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); if(_zz_108)begin @@ -3805,7 +3845,7 @@ module VexRiscv ( _zz_109 = execute_IntAluPlugin_bitwise; end `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_109 = {31'd0, _zz_314}; + _zz_109 = {31'd0, _zz_338}; end default : begin _zz_109 = execute_SRC_ADD_SUB; @@ -3819,18 +3859,18 @@ module VexRiscv ( _zz_110 = execute_RS1; end `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_110 = {29'd0, _zz_315}; + _zz_110 = {29'd0, _zz_339}; end `Src1CtrlEnum_defaultEncoding_IMU : begin _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_110 = {27'd0, _zz_316}; + _zz_110 = {27'd0, _zz_340}; end endcase end - assign _zz_111 = _zz_317[11]; + assign _zz_111 = _zz_341[11]; always @ (*) begin _zz_112[19] = _zz_111; _zz_112[18] = _zz_111; @@ -3854,7 +3894,7 @@ module VexRiscv ( _zz_112[0] = _zz_111; end - assign _zz_113 = _zz_318[11]; + assign _zz_113 = _zz_342[11]; always @ (*) begin _zz_114[19] = _zz_113; _zz_114[18] = _zz_113; @@ -3896,7 +3936,7 @@ module VexRiscv ( end always @ (*) begin - execute_SrcPlugin_addSub = _zz_319; + execute_SrcPlugin_addSub = _zz_343; if(execute_SRC2_FORCE_ZERO)begin execute_SrcPlugin_addSub = execute_SRC1; end @@ -3977,22 +4017,22 @@ module VexRiscv ( always @ (*) begin _zz_118 = 1'b0; - if(_zz_247)begin - if(_zz_248)begin + if(_zz_271)begin + if(_zz_272)begin if(_zz_123)begin _zz_118 = 1'b1; end end end - if(_zz_249)begin - if(_zz_250)begin + if(_zz_273)begin + if(_zz_274)begin if(_zz_125)begin _zz_118 = 1'b1; end end end - if(_zz_251)begin - if(_zz_252)begin + if(_zz_275)begin + if(_zz_276)begin if(_zz_127)begin _zz_118 = 1'b1; end @@ -4005,22 +4045,22 @@ module VexRiscv ( always @ (*) begin _zz_119 = 1'b0; - if(_zz_247)begin - if(_zz_248)begin + if(_zz_271)begin + if(_zz_272)begin if(_zz_124)begin _zz_119 = 1'b1; end end end - if(_zz_249)begin - if(_zz_250)begin + if(_zz_273)begin + if(_zz_274)begin if(_zz_126)begin _zz_119 = 1'b1; end end end - if(_zz_251)begin - if(_zz_252)begin + if(_zz_275)begin + if(_zz_276)begin if(_zz_128)begin _zz_119 = 1'b1; end @@ -4068,7 +4108,7 @@ module VexRiscv ( endcase end - assign _zz_132 = _zz_326[11]; + assign _zz_132 = _zz_350[11]; always @ (*) begin _zz_133[19] = _zz_132; _zz_133[18] = _zz_132; @@ -4092,7 +4132,7 @@ module VexRiscv ( _zz_133[0] = _zz_132; end - assign _zz_134 = _zz_327[19]; + assign _zz_134 = _zz_351[19]; always @ (*) begin _zz_135[10] = _zz_134; _zz_135[9] = _zz_134; @@ -4107,7 +4147,7 @@ module VexRiscv ( _zz_135[0] = _zz_134; end - assign _zz_136 = _zz_328[11]; + assign _zz_136 = _zz_352[11]; always @ (*) begin _zz_137[18] = _zz_136; _zz_137[17] = _zz_136; @@ -4133,13 +4173,13 @@ module VexRiscv ( always @ (*) begin case(execute_BRANCH_CTRL) `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_138 = (_zz_329[1] ^ execute_RS1[1]); + _zz_138 = (_zz_353[1] ^ execute_RS1[1]); end `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_138 = _zz_330[1]; + _zz_138 = _zz_354[1]; end default : begin - _zz_138 = _zz_331[1]; + _zz_138 = _zz_355[1]; end endcase end @@ -4156,7 +4196,7 @@ module VexRiscv ( endcase end - assign _zz_139 = _zz_332[11]; + assign _zz_139 = _zz_356[11]; always @ (*) begin _zz_140[19] = _zz_139; _zz_140[18] = _zz_139; @@ -4186,15 +4226,15 @@ module VexRiscv ( execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_570,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_571,_zz_572},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_594,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_595,_zz_596},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_335}; + execute_BranchPlugin_branch_src2 = {29'd0, _zz_359}; end end endcase end - assign _zz_141 = _zz_333[19]; + assign _zz_141 = _zz_357[19]; always @ (*) begin _zz_142[10] = _zz_141; _zz_142[9] = _zz_141; @@ -4209,7 +4249,7 @@ module VexRiscv ( _zz_142[0] = _zz_141; end - assign _zz_143 = _zz_334[11]; + assign _zz_143 = _zz_358[11]; always @ (*) begin _zz_144[18] = _zz_143; _zz_144[17] = _zz_143; @@ -4258,12 +4298,12 @@ module VexRiscv ( assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_149 = _zz_336[0]; + assign _zz_149 = _zz_360[0]; assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_151 = _zz_338[0]; + assign _zz_151 = _zz_362[0]; always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_237)begin + if(_zz_261)begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end if(decode_arbitration_isFlushed)begin @@ -4273,7 +4313,7 @@ module VexRiscv ( always @ (*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_240)begin + if(_zz_264)begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end if(execute_arbitration_isFlushed)begin @@ -4442,6 +4482,70 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end + if(execute_CsrPlugin_csr_2820)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2822)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2824)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2826)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2828)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2830)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end if(execute_CsrPlugin_csr_3008)begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4450,7 +4554,7 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_253)begin + if(_zz_277)begin execute_CsrPlugin_illegalAccess = 1'b1; end if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin @@ -4469,20 +4573,20 @@ module VexRiscv ( always @ (*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_254)begin + if(_zz_278)begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_255)begin + if(_zz_279)begin CsrPlugin_selfException_valid = 1'b1; end end always @ (*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_254)begin + if(_zz_278)begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_255)begin + if(_zz_279)begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4497,14 +4601,14 @@ module VexRiscv ( assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; always @ (*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_253)begin + if(_zz_277)begin execute_CsrPlugin_writeInstruction = 1'b0; end end always @ (*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_253)begin + if(_zz_277)begin execute_CsrPlugin_readInstruction = 1'b0; end end @@ -4513,7 +4617,7 @@ module VexRiscv ( assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; always @ (*) begin - case(_zz_268) + case(_zz_292) 1'b0 : begin execute_CsrPlugin_writeData = execute_SRC1; end @@ -4526,49 +4630,49 @@ module VexRiscv ( assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_340; + assign execute_CfuPlugin_functionsIds_0 = _zz_364; assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_152 = _zz_341[7]; - always @ (*) begin - _zz_153[23] = _zz_152; - _zz_153[22] = _zz_152; - _zz_153[21] = _zz_152; - _zz_153[20] = _zz_152; - _zz_153[19] = _zz_152; - _zz_153[18] = _zz_152; - _zz_153[17] = _zz_152; - _zz_153[16] = _zz_152; - _zz_153[15] = _zz_152; - _zz_153[14] = _zz_152; - _zz_153[13] = _zz_152; - _zz_153[12] = _zz_152; - _zz_153[11] = _zz_152; - _zz_153[10] = _zz_152; - _zz_153[9] = _zz_152; - _zz_153[8] = _zz_152; - _zz_153[7] = _zz_152; - _zz_153[6] = _zz_152; - _zz_153[5] = _zz_152; - _zz_153[4] = _zz_152; - _zz_153[3] = _zz_152; - _zz_153[2] = _zz_152; - _zz_153[1] = _zz_152; - _zz_153[0] = _zz_152; + assign _zz_168 = _zz_365[7]; + always @ (*) begin + _zz_169[23] = _zz_168; + _zz_169[22] = _zz_168; + _zz_169[21] = _zz_168; + _zz_169[20] = _zz_168; + _zz_169[19] = _zz_168; + _zz_169[18] = _zz_168; + _zz_169[17] = _zz_168; + _zz_169[16] = _zz_168; + _zz_169[15] = _zz_168; + _zz_169[14] = _zz_168; + _zz_169[13] = _zz_168; + _zz_169[12] = _zz_168; + _zz_169[11] = _zz_168; + _zz_169[10] = _zz_168; + _zz_169[9] = _zz_168; + _zz_169[8] = _zz_168; + _zz_169[7] = _zz_168; + _zz_169[6] = _zz_168; + _zz_169[5] = _zz_168; + _zz_169[4] = _zz_168; + _zz_169[3] = _zz_168; + _zz_169[2] = _zz_168; + _zz_169[1] = _zz_168; + _zz_169[0] = _zz_168; end always @ (*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) `Input2Kind_defaultEncoding_RS : begin - _zz_154 = execute_RS2; + _zz_170 = execute_RS2; end default : begin - _zz_154 = {_zz_153,execute_INSTRUCTION[31 : 24]}; + _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 24]}; end endcase end - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_154; + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); @@ -4594,7 +4698,7 @@ module VexRiscv ( assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; always @ (*) begin - case(_zz_256) + case(_zz_280) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4608,7 +4712,7 @@ module VexRiscv ( end always @ (*) begin - case(_zz_256) + case(_zz_280) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4627,12 +4731,12 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_342) + $signed(_zz_343)); + assign writeBack_MulPlugin_result = ($signed(_zz_366) + $signed(_zz_367)); assign memory_DivPlugin_frontendOk = 1'b1; always @ (*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_232)begin - if(_zz_257)begin + if(_zz_256)begin + if(_zz_281)begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end @@ -4640,7 +4744,7 @@ module VexRiscv ( always @ (*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_258)begin + if(_zz_282)begin memory_DivPlugin_div_counter_willClear = 1'b1; end end @@ -4651,32 +4755,32 @@ module VexRiscv ( if(memory_DivPlugin_div_counter_willOverflow)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_347); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371); end if(memory_DivPlugin_div_counter_willClear)begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_155 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_155[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_348); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_349 : _zz_350); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_351[31:0]; - assign _zz_156 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_157 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_158 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_372); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_373 : _zz_374); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_375[31:0]; + assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); always @ (*) begin - _zz_159[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_159[31 : 0] = execute_RS1; + _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_175[31 : 0] = execute_RS1; end - assign _zz_161 = (_zz_160 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_161 != 32'h0); + assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_177 != 32'h0); always @ (*) begin debug_bus_cmd_ready = 1'b1; if(debug_bus_cmd_valid)begin - case(_zz_259) + case(_zz_283) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; @@ -4690,7 +4794,7 @@ module VexRiscv ( always @ (*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_162))begin + if((! _zz_178))begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4702,7 +4806,7 @@ module VexRiscv ( always @ (*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; if(debug_bus_cmd_valid)begin - case(_zz_259) + case(_zz_283) 6'h01 : begin if(debug_bus_cmd_payload_wr)begin IBusCachedPlugin_injectionPort_valid = 1'b1; @@ -4769,7 +4873,7 @@ module VexRiscv ( assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); always @ (*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_163) + case(_zz_179) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4779,216 +4883,272 @@ module VexRiscv ( end always @ (*) begin - _zz_164 = 32'h0; + _zz_180 = 32'h0; if(execute_CsrPlugin_csr_3264)begin - _zz_164[12 : 0] = 13'h1000; - _zz_164[25 : 20] = 6'h20; + _zz_180[12 : 0] = 13'h1000; + _zz_180[25 : 20] = 6'h20; end end always @ (*) begin - _zz_165 = 32'h0; + _zz_181 = 32'h0; if(execute_CsrPlugin_csr_3857)begin - _zz_165[3 : 0] = 4'b1011; + _zz_181[3 : 0] = 4'b1011; end end always @ (*) begin - _zz_166 = 32'h0; + _zz_182 = 32'h0; if(execute_CsrPlugin_csr_3858)begin - _zz_166[4 : 0] = 5'h16; + _zz_182[4 : 0] = 5'h16; end end always @ (*) begin - _zz_167 = 32'h0; + _zz_183 = 32'h0; if(execute_CsrPlugin_csr_3859)begin - _zz_167[5 : 0] = 6'h21; + _zz_183[5 : 0] = 6'h21; end end always @ (*) begin - _zz_168 = 32'h0; + _zz_184 = 32'h0; if(execute_CsrPlugin_csr_769)begin - _zz_168[31 : 30] = CsrPlugin_misa_base; - _zz_168[25 : 0] = CsrPlugin_misa_extensions; + _zz_184[31 : 30] = CsrPlugin_misa_base; + _zz_184[25 : 0] = CsrPlugin_misa_extensions; end end always @ (*) begin - _zz_169 = 32'h0; + _zz_185 = 32'h0; if(execute_CsrPlugin_csr_768)begin - _zz_169[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_169[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_169[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; end end always @ (*) begin - _zz_170 = 32'h0; + _zz_186 = 32'h0; if(execute_CsrPlugin_csr_836)begin - _zz_170[11 : 11] = CsrPlugin_mip_MEIP; - _zz_170[7 : 7] = CsrPlugin_mip_MTIP; - _zz_170[3 : 3] = CsrPlugin_mip_MSIP; + _zz_186[11 : 11] = CsrPlugin_mip_MEIP; + _zz_186[7 : 7] = CsrPlugin_mip_MTIP; + _zz_186[3 : 3] = CsrPlugin_mip_MSIP; end end always @ (*) begin - _zz_171 = 32'h0; + _zz_187 = 32'h0; if(execute_CsrPlugin_csr_772)begin - _zz_171[11 : 11] = CsrPlugin_mie_MEIE; - _zz_171[7 : 7] = CsrPlugin_mie_MTIE; - _zz_171[3 : 3] = CsrPlugin_mie_MSIE; + _zz_187[11 : 11] = CsrPlugin_mie_MEIE; + _zz_187[7 : 7] = CsrPlugin_mie_MTIE; + _zz_187[3 : 3] = CsrPlugin_mie_MSIE; end end always @ (*) begin - _zz_172 = 32'h0; + _zz_188 = 32'h0; if(execute_CsrPlugin_csr_773)begin - _zz_172[31 : 2] = CsrPlugin_mtvec_base; - _zz_172[1 : 0] = CsrPlugin_mtvec_mode; + _zz_188[31 : 2] = CsrPlugin_mtvec_base; + _zz_188[1 : 0] = CsrPlugin_mtvec_mode; end end always @ (*) begin - _zz_173 = 32'h0; + _zz_189 = 32'h0; if(execute_CsrPlugin_csr_833)begin - _zz_173[31 : 0] = CsrPlugin_mepc; + _zz_189[31 : 0] = CsrPlugin_mepc; end end always @ (*) begin - _zz_174 = 32'h0; + _zz_190 = 32'h0; if(execute_CsrPlugin_csr_832)begin - _zz_174[31 : 0] = CsrPlugin_mscratch; + _zz_190[31 : 0] = CsrPlugin_mscratch; end end always @ (*) begin - _zz_175 = 32'h0; + _zz_191 = 32'h0; if(execute_CsrPlugin_csr_834)begin - _zz_175[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_175[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @ (*) begin - _zz_176 = 32'h0; + _zz_192 = 32'h0; if(execute_CsrPlugin_csr_835)begin - _zz_176[31 : 0] = CsrPlugin_mtval; + _zz_192[31 : 0] = CsrPlugin_mtval; end end always @ (*) begin - _zz_177 = 32'h0; + _zz_193 = 32'h0; if(execute_CsrPlugin_csr_2816)begin - _zz_177[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_178 = 32'h0; + _zz_194 = 32'h0; if(execute_CsrPlugin_csr_2944)begin - _zz_178[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_179 = 32'h0; + _zz_195 = 32'h0; if(execute_CsrPlugin_csr_2818)begin - _zz_179[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_180 = 32'h0; + _zz_196 = 32'h0; if(execute_CsrPlugin_csr_2946)begin - _zz_180[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_181 = 32'h0; + _zz_197 = 32'h0; if(execute_CsrPlugin_csr_3072)begin - _zz_181[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @ (*) begin - _zz_182 = 32'h0; + _zz_198 = 32'h0; if(execute_CsrPlugin_csr_3200)begin - _zz_182[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @ (*) begin - _zz_183 = 32'h0; + _zz_199 = 32'h0; if(execute_CsrPlugin_csr_3074)begin - _zz_183[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @ (*) begin - _zz_184 = 32'h0; + _zz_200 = 32'h0; if(execute_CsrPlugin_csr_3202)begin - _zz_184[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @ (*) begin - _zz_185 = 32'h0; + _zz_201 = 32'h0; + if(execute_CsrPlugin_csr_2820)begin + _zz_201[31 : 0] = _zz_152; + end + end + + always @ (*) begin + _zz_202 = 32'h0; + if(execute_CsrPlugin_csr_2822)begin + _zz_202[31 : 0] = _zz_154; + end + end + + always @ (*) begin + _zz_203 = 32'h0; + if(execute_CsrPlugin_csr_2824)begin + _zz_203[31 : 0] = _zz_156; + end + end + + always @ (*) begin + _zz_204 = 32'h0; + if(execute_CsrPlugin_csr_2826)begin + _zz_204[31 : 0] = _zz_158; + end + end + + always @ (*) begin + _zz_205 = 32'h0; + if(execute_CsrPlugin_csr_2828)begin + _zz_205[31 : 0] = _zz_160; + end + end + + always @ (*) begin + _zz_206 = 32'h0; + if(execute_CsrPlugin_csr_2830)begin + _zz_206[31 : 0] = _zz_162; + end + end + + always @ (*) begin + _zz_207 = 32'h0; + if(execute_CsrPlugin_csr_2832)begin + _zz_207[31 : 0] = _zz_164; + end + end + + always @ (*) begin + _zz_208 = 32'h0; + if(execute_CsrPlugin_csr_2834)begin + _zz_208[31 : 0] = _zz_166; + end + end + + always @ (*) begin + _zz_209 = 32'h0; if(execute_CsrPlugin_csr_3008)begin - _zz_185[31 : 0] = _zz_160; + _zz_209[31 : 0] = _zz_176; end end always @ (*) begin - _zz_186 = 32'h0; + _zz_210 = 32'h0; if(execute_CsrPlugin_csr_4032)begin - _zz_186[31 : 0] = _zz_161; + _zz_210[31 : 0] = _zz_177; end end - assign execute_CsrPlugin_readData = (((((_zz_164 | _zz_165) | (_zz_166 | _zz_167)) | ((_zz_573 | _zz_168) | (_zz_169 | _zz_170))) | (((_zz_171 | _zz_172) | (_zz_173 | _zz_174)) | ((_zz_175 | _zz_176) | (_zz_177 | _zz_178)))) | (((_zz_179 | _zz_180) | (_zz_181 | _zz_182)) | ((_zz_183 | _zz_184) | (_zz_185 | _zz_186)))); - assign iBusWishbone_ADR = {_zz_368,_zz_187}; - assign iBusWishbone_CTI = ((_zz_187 == 3'b111) ? 3'b111 : 3'b010); + assign execute_CsrPlugin_readData = (((((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_597 | _zz_184) | (_zz_185 | _zz_186))) | (((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194)))) | ((((_zz_195 | _zz_196) | (_zz_197 | _zz_198)) | ((_zz_199 | _zz_200) | (_zz_201 | _zz_202))) | (((_zz_203 | _zz_204) | (_zz_205 | _zz_206)) | ((_zz_207 | _zz_208) | (_zz_209 | _zz_210))))); + assign iBusWishbone_ADR = {_zz_392,_zz_211}; + assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; assign iBusWishbone_DAT_MOSI = 32'h0; always @ (*) begin iBusWishbone_CYC = 1'b0; - if(_zz_260)begin + if(_zz_284)begin iBusWishbone_CYC = 1'b1; end end always @ (*) begin iBusWishbone_STB = 1'b0; - if(_zz_260)begin + if(_zz_284)begin iBusWishbone_STB = 1'b1; end end assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_188; + assign iBus_rsp_valid = _zz_212; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_194 = (dBus_cmd_payload_length != 3'b000); - assign _zz_190 = dBus_cmd_valid; - assign _zz_192 = dBus_cmd_payload_wr; - assign _zz_193 = (_zz_189 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_191 && (_zz_192 || _zz_193)); - assign dBusWishbone_ADR = ((_zz_194 ? {{dBus_cmd_payload_address[31 : 5],_zz_189},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_194 ? (_zz_193 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_218 = (dBus_cmd_payload_length != 3'b000); + assign _zz_214 = dBus_cmd_valid; + assign _zz_216 = dBus_cmd_payload_wr; + assign _zz_217 = (_zz_213 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_215 && (_zz_216 || _zz_217)); + assign dBusWishbone_ADR = ((_zz_218 ? {{dBus_cmd_payload_address[31 : 5],_zz_213},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_218 ? (_zz_217 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_192 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_192; + assign dBusWishbone_SEL = (_zz_216 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_216; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_191 = (_zz_190 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_190; - assign dBusWishbone_STB = _zz_190; - assign dBus_rsp_valid = _zz_195; + assign _zz_215 = (_zz_214 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_214; + assign dBusWishbone_STB = _zz_214; + assign dBus_rsp_valid = _zz_219; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; always @ (posedge clk) begin @@ -5035,16 +5195,16 @@ module VexRiscv ( execute_CfuPlugin_fired <= 1'b0; CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_160 <= 32'h0; + _zz_176 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_163 <= 3'b000; + _zz_179 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_187 <= 3'b000; - _zz_188 <= 1'b0; - _zz_189 <= 3'b000; - _zz_195 <= 1'b0; + _zz_211 <= 3'b000; + _zz_212 <= 1'b0; + _zz_213 <= 3'b000; + _zz_219 <= 1'b0; end else begin if(IBusCachedPlugin_fetchPc_correction)begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; @@ -5125,7 +5285,7 @@ module VexRiscv ( if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; end - if(_zz_261)begin + if(_zz_285)begin dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; end if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin @@ -5157,14 +5317,14 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_262)begin - if(_zz_263)begin + if(_zz_286)begin + if(_zz_287)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_264)begin + if(_zz_288)begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_265)begin + if(_zz_289)begin CsrPlugin_interrupt_valid <= 1'b1; end end @@ -5189,7 +5349,7 @@ module VexRiscv ( CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_242)begin + if(_zz_266)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5200,8 +5360,8 @@ module VexRiscv ( end endcase end - if(_zz_243)begin - case(_zz_245) + if(_zz_267)begin + case(_zz_269) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5227,7 +5387,7 @@ module VexRiscv ( if(memory_CfuPlugin_rsp_ready)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; end - if(_zz_266)begin + if(_zz_290)begin CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; end memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; @@ -5252,25 +5412,25 @@ module VexRiscv ( if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_163) + case(_zz_179) 3'b000 : begin if(IBusCachedPlugin_injectionPort_valid)begin - _zz_163 <= 3'b001; + _zz_179 <= 3'b001; end end 3'b001 : begin - _zz_163 <= 3'b010; + _zz_179 <= 3'b010; end 3'b010 : begin - _zz_163 <= 3'b011; + _zz_179 <= 3'b011; end 3'b011 : begin if((! decode_arbitration_isStuck))begin - _zz_163 <= 3'b100; + _zz_179 <= 3'b100; end end 3'b100 : begin - _zz_163 <= 3'b000; + _zz_179 <= 3'b000; end default : begin end @@ -5284,35 +5444,35 @@ module VexRiscv ( if(execute_CsrPlugin_csr_768)begin if(execute_CsrPlugin_writeEnable)begin CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_361[0]; - CsrPlugin_mstatus_MIE <= _zz_362[0]; + CsrPlugin_mstatus_MPIE <= _zz_385[0]; + CsrPlugin_mstatus_MIE <= _zz_386[0]; end end if(execute_CsrPlugin_csr_772)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_364[0]; - CsrPlugin_mie_MTIE <= _zz_365[0]; - CsrPlugin_mie_MSIE <= _zz_366[0]; + CsrPlugin_mie_MEIE <= _zz_388[0]; + CsrPlugin_mie_MTIE <= _zz_389[0]; + CsrPlugin_mie_MSIE <= _zz_390[0]; end end if(execute_CsrPlugin_csr_3008)begin if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; end end - if(_zz_260)begin + if(_zz_284)begin if(iBusWishbone_ACK)begin - _zz_187 <= (_zz_187 + 3'b001); + _zz_211 <= (_zz_211 + 3'b001); end end - _zz_188 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_190 && _zz_191))begin - _zz_189 <= (_zz_189 + 3'b001); - if(_zz_193)begin - _zz_189 <= 3'b000; + _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_214 && _zz_215))begin + _zz_213 <= (_zz_213 + 3'b001); + if(_zz_217)begin + _zz_213 <= 3'b000; end end - _zz_195 <= ((_zz_190 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_219 <= ((_zz_214 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end @@ -5326,7 +5486,7 @@ module VexRiscv ( if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_261)begin + if(_zz_285)begin dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; @@ -5353,11 +5513,11 @@ module VexRiscv ( if(writeBack_arbitration_isFiring)begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_237)begin + if(_zz_261)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(_zz_240)begin + if(_zz_264)begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end @@ -5369,21 +5529,21 @@ module VexRiscv ( CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_262)begin - if(_zz_263)begin + if(_zz_286)begin + if(_zz_287)begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_264)begin + if(_zz_288)begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_265)begin + if(_zz_289)begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_242)begin + if(_zz_266)begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); @@ -5397,7 +5557,31 @@ module VexRiscv ( end endcase end - if(_zz_266)begin + if(_zz_153[0])begin + _zz_152 <= (_zz_152 + 32'h00000001); + end + if(_zz_155[0])begin + _zz_154 <= (_zz_154 + 32'h00000001); + end + if(_zz_157[0])begin + _zz_156 <= (_zz_156 + 32'h00000001); + end + if(_zz_159[0])begin + _zz_158 <= (_zz_158 + 32'h00000001); + end + if(_zz_161[0])begin + _zz_160 <= (_zz_160 + 32'h00000001); + end + if(_zz_163[0])begin + _zz_162 <= (_zz_162 + 32'h00000001); + end + if(_zz_165[0])begin + _zz_164 <= (_zz_164 + 32'h00000001); + end + if(_zz_167[0])begin + _zz_166 <= (_zz_166 + 32'h00000001); + end + if(_zz_290)begin CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end @@ -5407,20 +5591,20 @@ module VexRiscv ( if((! memory_arbitration_isStuck))begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_232)begin - if(_zz_257)begin + if(_zz_256)begin + if(_zz_281)begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_352[31:0]; + memory_DivPlugin_div_result <= _zz_376[31:0]; end end end - if(_zz_258)begin + if(_zz_282)begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_158 ? (~ _zz_159) : _zz_159) + _zz_358); - memory_DivPlugin_rs2 <= ((_zz_157 ? (~ execute_RS2) : execute_RS2) + _zz_360); - memory_DivPlugin_div_needRevert <= ((_zz_158 ^ (_zz_157 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_382); + memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_384); + memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; if((! execute_arbitration_isStuck))begin @@ -5681,6 +5865,54 @@ module VexRiscv ( if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); + end if((! execute_arbitration_isStuck))begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end @@ -5689,7 +5921,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_836)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_363[0]; + CsrPlugin_mip_MSIP <= _zz_387[0]; end end if(execute_CsrPlugin_csr_773)begin @@ -5710,7 +5942,7 @@ module VexRiscv ( end if(execute_CsrPlugin_csr_834)begin if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_367[0]; + CsrPlugin_mcause_interrupt <= _zz_391[0]; CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; end end @@ -5739,6 +5971,86 @@ module VexRiscv ( CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; end end + if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + end + end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end @@ -5753,8 +6065,8 @@ module VexRiscv ( if(writeBack_arbitration_isValid)begin DebugPlugin_busReadDataReg <= _zz_57; end - _zz_162 <= debug_bus_cmd_payload_address[2]; - if(_zz_239)begin + _zz_178 <= debug_bus_cmd_payload_address[2]; + if(_zz_263)begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; @@ -5772,7 +6084,7 @@ module VexRiscv ( DebugPlugin_godmode <= 1'b1; end if(debug_bus_cmd_valid)begin - case(_zz_259) + case(_zz_283) 6'h0 : begin if(debug_bus_cmd_payload_wr)begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; @@ -5800,13 +6112,13 @@ module VexRiscv ( end endcase end - if(_zz_239)begin - if(_zz_241)begin + if(_zz_263)begin + if(_zz_265)begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_244)begin + if(_zz_268)begin if(decode_arbitration_isValid)begin DebugPlugin_haltIt <= 1'b1; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v index b41f53f..c5eea43 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9c3529c14328ee22a18ec0f74e66ca59de7346c3 +// Git hash : 5bb91146a62643cf606443d5366c69720906549c `define Input2Kind_defaultEncoding_type [0:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v index a4cf26a..6613f83 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : 9c3529c14328ee22a18ec0f74e66ca59de7346c3 +// Git hash : 5bb91146a62643cf606443d5366c69720906549c `define Input2Kind_defaultEncoding_type [0:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v index 3333139..b12ad4a 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : e1ac7eb3083970f73e62f222f2f3e8520116f2e8 +// Git hash : 5bb91146a62643cf606443d5366c69720906549c `define Input2Kind_defaultEncoding_type [0:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v index d02aef8..cf5ad7e 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 // Component : VexRiscv -// Git hash : e1ac7eb3083970f73e62f222f2f3e8520116f2e8 +// Git hash : 5bb91146a62643cf606443d5366c69720906549c `define Input2Kind_defaultEncoding_type [0:0] From 7490bb269e39e0be9c7192d3b82891eccfa36db2 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Thu, 16 Sep 2021 16:02:25 -0700 Subject: [PATCH 25/30] Add slimperf+cfu variant. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 8 +- .../verilog/VexRiscv_SlimPerfCfu.v | 6923 ++++++++++++++++ .../verilog/VexRiscv_SlimPerfCfu.yaml | 4 + .../verilog/VexRiscv_SlimPerfCfuDebug.v | 7221 +++++++++++++++++ .../verilog/VexRiscv_SlimPerfCfuDebug.yaml | 5 + 5 files changed, 14160 insertions(+), 1 deletion(-) create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.yaml create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.yaml diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index bf7337a..80a1e6f 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -1,6 +1,6 @@ SRC := ${shell find . -type f -name \*.scala} -all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_SlimCfu.v VexRiscv_SlimCfuDebug.v VexRiscv_Fomu.v VexRiscv_FomuCfu.v VexRiscv_PerfCfu.v VexRiscv_PerfCfuDebug.v +all: VexRiscv.v VexRiscv_Debug.v VexRiscv_Lite.v VexRiscv_LiteDebug.v VexRiscv_IMAC.v VexRiscv_IMACDebug.v VexRiscv_Min.v VexRiscv_MinDebug.v VexRiscv_Full.v VexRiscv_FullDebug.v VexRiscv_Linux.v VexRiscv_LinuxDebug.v VexRiscv_LinuxNoDspFmax.v VexRiscv_FullCfu.v VexRiscv_FullCfuDebug.v VexRiscv_SlimCfu.v VexRiscv_SlimCfuDebug.v VexRiscv_Fomu.v VexRiscv_FomuCfu.v VexRiscv_PerfCfu.v VexRiscv_PerfCfuDebug.v VexRiscv_SlimPerfCfu.v VexRiscv_SlimPerfCfuDebug.v VexRiscv.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault" @@ -56,6 +56,12 @@ VexRiscv_SlimCfu.v: $(SRC) VexRiscv_SlimCfuDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all -d --cfu true --outputFile VexRiscv_SlimCfuDebug" +VexRiscv_SlimPerfCfu.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimPerfCfu" + +VexRiscv_SlimPerfCfuDebug.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_SlimPerfCfuDebug" + VexRiscv_Linux.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig linux-minimal --outputFile VexRiscv_Linux" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.v new file mode 100644 index 0000000..a049b7e --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.v @@ -0,0 +1,6923 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : cbb04d34fec970ebb660147932da0bb4bb5adce0 + + +`define Input2Kind_defaultEncoding_type [0:0] +`define Input2Kind_defaultEncoding_RS 1'b0 +`define Input2Kind_defaultEncoding_IMM_I 1'b1 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input CfuPlugin_bus_rsp_payload_response_ok, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire _zz_217; + wire _zz_218; + wire _zz_219; + wire _zz_220; + wire _zz_221; + wire _zz_222; + wire _zz_223; + wire _zz_224; + reg _zz_225; + wire _zz_226; + wire [31:0] _zz_227; + wire _zz_228; + wire [31:0] _zz_229; + reg _zz_230; + wire _zz_231; + wire _zz_232; + wire [31:0] _zz_233; + wire _zz_234; + wire _zz_235; + wire _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire [3:0] _zz_242; + wire _zz_243; + wire _zz_244; + reg [31:0] _zz_245; + reg [31:0] _zz_246; + reg [31:0] _zz_247; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_248; + wire _zz_249; + wire _zz_250; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire _zz_255; + wire _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire [1:0] _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire [1:0] _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire _zz_280; + wire _zz_281; + wire _zz_282; + wire _zz_283; + wire [1:0] _zz_284; + wire _zz_285; + wire [1:0] _zz_286; + wire [51:0] _zz_287; + wire [51:0] _zz_288; + wire [51:0] _zz_289; + wire [32:0] _zz_290; + wire [51:0] _zz_291; + wire [49:0] _zz_292; + wire [51:0] _zz_293; + wire [49:0] _zz_294; + wire [51:0] _zz_295; + wire [32:0] _zz_296; + wire [31:0] _zz_297; + wire [32:0] _zz_298; + wire [0:0] _zz_299; + wire [0:0] _zz_300; + wire [0:0] _zz_301; + wire [0:0] _zz_302; + wire [0:0] _zz_303; + wire [0:0] _zz_304; + wire [0:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [3:0] _zz_317; + wire [2:0] _zz_318; + wire [31:0] _zz_319; + wire [11:0] _zz_320; + wire [31:0] _zz_321; + wire [19:0] _zz_322; + wire [11:0] _zz_323; + wire [31:0] _zz_324; + wire [31:0] _zz_325; + wire [19:0] _zz_326; + wire [11:0] _zz_327; + wire [2:0] _zz_328; + wire [2:0] _zz_329; + wire [0:0] _zz_330; + wire [2:0] _zz_331; + wire [4:0] _zz_332; + wire [11:0] _zz_333; + wire [11:0] _zz_334; + wire [31:0] _zz_335; + wire [31:0] _zz_336; + wire [31:0] _zz_337; + wire [31:0] _zz_338; + wire [31:0] _zz_339; + wire [31:0] _zz_340; + wire [31:0] _zz_341; + wire [11:0] _zz_342; + wire [19:0] _zz_343; + wire [11:0] _zz_344; + wire [31:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [11:0] _zz_348; + wire [19:0] _zz_349; + wire [11:0] _zz_350; + wire [2:0] _zz_351; + wire [1:0] _zz_352; + wire [1:0] _zz_353; + wire [1:0] _zz_354; + wire [1:0] _zz_355; + wire [9:0] _zz_356; + wire [7:0] _zz_357; + wire [65:0] _zz_358; + wire [65:0] _zz_359; + wire [31:0] _zz_360; + wire [31:0] _zz_361; + wire [0:0] _zz_362; + wire [5:0] _zz_363; + wire [32:0] _zz_364; + wire [31:0] _zz_365; + wire [31:0] _zz_366; + wire [32:0] _zz_367; + wire [32:0] _zz_368; + wire [32:0] _zz_369; + wire [32:0] _zz_370; + wire [0:0] _zz_371; + wire [32:0] _zz_372; + wire [0:0] _zz_373; + wire [32:0] _zz_374; + wire [0:0] _zz_375; + wire [31:0] _zz_376; + wire [0:0] _zz_377; + wire [0:0] _zz_378; + wire [0:0] _zz_379; + wire [0:0] _zz_380; + wire [0:0] _zz_381; + wire [0:0] _zz_382; + wire [0:0] _zz_383; + wire [26:0] _zz_384; + wire _zz_385; + wire _zz_386; + wire [1:0] _zz_387; + wire [31:0] _zz_388; + wire [31:0] _zz_389; + wire [31:0] _zz_390; + wire _zz_391; + wire [0:0] _zz_392; + wire [14:0] _zz_393; + wire [31:0] _zz_394; + wire [31:0] _zz_395; + wire [31:0] _zz_396; + wire _zz_397; + wire [0:0] _zz_398; + wire [8:0] _zz_399; + wire [31:0] _zz_400; + wire [31:0] _zz_401; + wire [31:0] _zz_402; + wire _zz_403; + wire [0:0] _zz_404; + wire [2:0] _zz_405; + wire _zz_406; + wire _zz_407; + wire _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire _zz_411; + wire _zz_412; + wire [0:0] _zz_413; + wire [26:0] _zz_414; + wire [31:0] _zz_415; + wire [31:0] _zz_416; + wire [31:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire [1:0] _zz_420; + wire [1:0] _zz_421; + wire _zz_422; + wire [0:0] _zz_423; + wire [21:0] _zz_424; + wire [31:0] _zz_425; + wire [31:0] _zz_426; + wire [31:0] _zz_427; + wire [31:0] _zz_428; + wire [31:0] _zz_429; + wire [31:0] _zz_430; + wire [0:0] _zz_431; + wire [0:0] _zz_432; + wire [2:0] _zz_433; + wire [2:0] _zz_434; + wire _zz_435; + wire [0:0] _zz_436; + wire [18:0] _zz_437; + wire [31:0] _zz_438; + wire [31:0] _zz_439; + wire [31:0] _zz_440; + wire [31:0] _zz_441; + wire _zz_442; + wire _zz_443; + wire [31:0] _zz_444; + wire [31:0] _zz_445; + wire _zz_446; + wire [0:0] _zz_447; + wire [0:0] _zz_448; + wire _zz_449; + wire [0:0] _zz_450; + wire [15:0] _zz_451; + wire [31:0] _zz_452; + wire _zz_453; + wire _zz_454; + wire _zz_455; + wire [2:0] _zz_456; + wire [2:0] _zz_457; + wire _zz_458; + wire [0:0] _zz_459; + wire [12:0] _zz_460; + wire _zz_461; + wire _zz_462; + wire _zz_463; + wire [0:0] _zz_464; + wire [2:0] _zz_465; + wire _zz_466; + wire [5:0] _zz_467; + wire [5:0] _zz_468; + wire _zz_469; + wire [0:0] _zz_470; + wire [9:0] _zz_471; + wire [31:0] _zz_472; + wire [31:0] _zz_473; + wire [31:0] _zz_474; + wire [31:0] _zz_475; + wire [31:0] _zz_476; + wire _zz_477; + wire [0:0] _zz_478; + wire [0:0] _zz_479; + wire [31:0] _zz_480; + wire _zz_481; + wire [0:0] _zz_482; + wire [3:0] _zz_483; + wire [0:0] _zz_484; + wire [3:0] _zz_485; + wire [5:0] _zz_486; + wire [5:0] _zz_487; + wire _zz_488; + wire [0:0] _zz_489; + wire [7:0] _zz_490; + wire [31:0] _zz_491; + wire [31:0] _zz_492; + wire [31:0] _zz_493; + wire [31:0] _zz_494; + wire [31:0] _zz_495; + wire [31:0] _zz_496; + wire [31:0] _zz_497; + wire [31:0] _zz_498; + wire [0:0] _zz_499; + wire [1:0] _zz_500; + wire _zz_501; + wire [0:0] _zz_502; + wire [1:0] _zz_503; + wire [0:0] _zz_504; + wire [3:0] _zz_505; + wire [0:0] _zz_506; + wire [0:0] _zz_507; + wire [1:0] _zz_508; + wire [1:0] _zz_509; + wire _zz_510; + wire [0:0] _zz_511; + wire [5:0] _zz_512; + wire [31:0] _zz_513; + wire [31:0] _zz_514; + wire _zz_515; + wire _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire _zz_520; + wire _zz_521; + wire [31:0] _zz_522; + wire [31:0] _zz_523; + wire _zz_524; + wire [0:0] _zz_525; + wire [1:0] _zz_526; + wire [31:0] _zz_527; + wire [31:0] _zz_528; + wire _zz_529; + wire _zz_530; + wire [0:0] _zz_531; + wire [0:0] _zz_532; + wire _zz_533; + wire [0:0] _zz_534; + wire [3:0] _zz_535; + wire [31:0] _zz_536; + wire [31:0] _zz_537; + wire [31:0] _zz_538; + wire [31:0] _zz_539; + wire [31:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire _zz_543; + wire _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; + wire [0:0] _zz_549; + wire [2:0] _zz_550; + wire [0:0] _zz_551; + wire [0:0] _zz_552; + wire _zz_553; + wire [0:0] _zz_554; + wire [1:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire _zz_559; + wire _zz_560; + wire [31:0] _zz_561; + wire _zz_562; + wire [0:0] _zz_563; + wire [0:0] _zz_564; + wire [0:0] _zz_565; + wire [0:0] _zz_566; + wire [1:0] _zz_567; + wire [1:0] _zz_568; + wire [0:0] _zz_569; + wire [0:0] _zz_570; + wire [31:0] _zz_571; + wire [31:0] _zz_572; + wire [31:0] _zz_573; + wire [31:0] _zz_574; + wire [31:0] _zz_575; + wire [31:0] _zz_576; + wire _zz_577; + wire _zz_578; + wire _zz_579; + wire [31:0] _zz_580; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_1; + wire `Input2Kind_defaultEncoding_type _zz_2; + wire `Input2Kind_defaultEncoding_type _zz_3; + wire decode_CfuPlugin_CFU_ENABLE; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `AluCtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + reg _zz_30; + reg _zz_31; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_32; + wire execute_CfuPlugin_CFU_ENABLE; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_37; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_38; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_41; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; + wire [31:0] _zz_46; + wire _zz_47; + reg _zz_48; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `Input2Kind_defaultEncoding_type _zz_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; + wire `Src2CtrlEnum_defaultEncoding_type _zz_54; + wire `AluCtrlEnum_defaultEncoding_type _zz_55; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56; + reg [31:0] _zz_57; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_59; + reg [31:0] _zz_60; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + reg CfuPlugin_joinException_valid; + wire [3:0] CfuPlugin_joinException_payload_code; + wire [31:0] CfuPlugin_joinException_payload_badAddr; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_61; + wire [3:0] _zz_62; + wire _zz_63; + wire _zz_64; + wire _zz_65; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_66; + wire _zz_67; + wire _zz_68; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_69; + wire _zz_70; + reg _zz_71; + wire _zz_72; + reg _zz_73; + reg [31:0] _zz_74; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_75; + reg [18:0] _zz_76; + wire _zz_77; + reg [10:0] _zz_78; + wire _zz_79; + reg [18:0] _zz_80; + reg _zz_81; + wire _zz_82; + reg [10:0] _zz_83; + wire _zz_84; + reg [18:0] _zz_85; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_86; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_87; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_88; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_89; + reg [31:0] _zz_90; + wire _zz_91; + reg [31:0] _zz_92; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [33:0] _zz_93; + wire _zz_94; + wire _zz_95; + wire _zz_96; + wire _zz_97; + wire _zz_98; + wire `Src1CtrlEnum_defaultEncoding_type _zz_99; + wire `AluCtrlEnum_defaultEncoding_type _zz_100; + wire `Src2CtrlEnum_defaultEncoding_type _zz_101; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_102; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_103; + wire `BranchCtrlEnum_defaultEncoding_type _zz_104; + wire `EnvCtrlEnum_defaultEncoding_type _zz_105; + wire `Input2Kind_defaultEncoding_type _zz_106; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_107; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_108; + reg [31:0] _zz_109; + wire _zz_110; + reg [19:0] _zz_111; + wire _zz_112; + reg [19:0] _zz_113; + reg [31:0] _zz_114; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_115; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_116; + reg _zz_117; + reg _zz_118; + reg _zz_119; + reg [4:0] _zz_120; + reg [31:0] _zz_121; + wire _zz_122; + wire _zz_123; + wire _zz_124; + wire _zz_125; + wire _zz_126; + wire _zz_127; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_128; + reg _zz_129; + reg _zz_130; + wire _zz_131; + reg [19:0] _zz_132; + wire _zz_133; + reg [10:0] _zz_134; + wire _zz_135; + reg [18:0] _zz_136; + reg _zz_137; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_138; + reg [19:0] _zz_139; + wire _zz_140; + reg [10:0] _zz_141; + wire _zz_142; + reg [18:0] _zz_143; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_144; + wire _zz_145; + wire _zz_146; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_147; + wire _zz_148; + wire [1:0] _zz_149; + wire _zz_150; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_151; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_167; + reg [23:0] _zz_168; + reg [31:0] _zz_169; + wire memory_CfuPlugin_rsp_valid; + reg memory_CfuPlugin_rsp_ready; + wire memory_CfuPlugin_rsp_payload_response_ok; + wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_s2mPipe_rValid; + reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_170; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_171; + wire _zz_172; + wire _zz_173; + reg [32:0] _zz_174; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_175; + wire [31:0] _zz_176; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_2820; + reg execute_CsrPlugin_csr_2821; + reg execute_CsrPlugin_csr_2822; + reg execute_CsrPlugin_csr_2823; + reg execute_CsrPlugin_csr_2824; + reg execute_CsrPlugin_csr_2825; + reg execute_CsrPlugin_csr_2826; + reg execute_CsrPlugin_csr_2827; + reg execute_CsrPlugin_csr_2828; + reg execute_CsrPlugin_csr_2829; + reg execute_CsrPlugin_csr_2830; + reg execute_CsrPlugin_csr_2831; + reg execute_CsrPlugin_csr_2832; + reg execute_CsrPlugin_csr_2833; + reg execute_CsrPlugin_csr_2834; + reg execute_CsrPlugin_csr_2835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_177; + reg [31:0] _zz_178; + reg [31:0] _zz_179; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; + reg [31:0] _zz_199; + reg [31:0] _zz_200; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + reg [2:0] _zz_208; + reg _zz_209; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_210; + wire _zz_211; + wire _zz_212; + wire _zz_213; + wire _zz_214; + wire _zz_215; + reg _zz_216; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [39:0] _zz_10_string; + reg [31:0] _zz_11_string; + reg [31:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [71:0] _zz_17_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [39:0] _zz_20_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [23:0] _zz_23_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [63:0] _zz_26_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [95:0] _zz_29_string; + reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_32_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_33_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_34_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_35_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_36_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_39_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_40_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_42_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_43_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_44_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_45_string; + reg [39:0] _zz_49_string; + reg [39:0] _zz_50_string; + reg [31:0] _zz_51_string; + reg [71:0] _zz_52_string; + reg [39:0] _zz_53_string; + reg [23:0] _zz_54_string; + reg [63:0] _zz_55_string; + reg [95:0] _zz_56_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_58_string; + reg [95:0] _zz_99_string; + reg [63:0] _zz_100_string; + reg [23:0] _zz_101_string; + reg [39:0] _zz_102_string; + reg [71:0] _zz_103_string; + reg [31:0] _zz_104_string; + reg [39:0] _zz_105_string; + reg [39:0] _zz_106_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_248 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_249 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_250 = 1'b1; + assign _zz_251 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_252 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_254 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_255 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_256 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_257 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_260 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_264 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_265 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_266 = (1'b0 || (! 1'b1)); + assign _zz_267 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_268 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_270 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_271 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_272 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_273 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_274 = execute_INSTRUCTION[13 : 12]; + assign _zz_275 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_276 = (! memory_arbitration_isStuck); + assign _zz_277 = (iBus_cmd_valid || (_zz_208 != 3'b000)); + assign _zz_278 = (_zz_244 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_280 = ((_zz_144 && 1'b1) && (! 1'b0)); + assign _zz_281 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_282 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_285 = execute_INSTRUCTION[13]; + assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); + assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); + assign _zz_289 = 52'h0; + assign _zz_290 = {1'b0,memory_MUL_LL}; + assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; + assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; + assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; + assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_297 = _zz_296[31 : 0]; + assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_299 = _zz_93[33 : 33]; + assign _zz_300 = _zz_93[32 : 32]; + assign _zz_301 = _zz_93[31 : 31]; + assign _zz_302 = _zz_93[30 : 30]; + assign _zz_303 = _zz_93[28 : 28]; + assign _zz_304 = _zz_93[25 : 25]; + assign _zz_305 = _zz_93[17 : 17]; + assign _zz_306 = _zz_93[16 : 16]; + assign _zz_307 = _zz_93[13 : 13]; + assign _zz_308 = _zz_93[12 : 12]; + assign _zz_309 = _zz_93[11 : 11]; + assign _zz_310 = _zz_93[15 : 15]; + assign _zz_311 = _zz_93[5 : 5]; + assign _zz_312 = _zz_93[3 : 3]; + assign _zz_313 = _zz_93[20 : 20]; + assign _zz_314 = _zz_93[10 : 10]; + assign _zz_315 = _zz_93[4 : 4]; + assign _zz_316 = _zz_93[0 : 0]; + assign _zz_317 = (_zz_61 - 4'b0001); + assign _zz_318 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_319 = {29'd0, _zz_318}; + assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_321 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_324 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_325 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_326 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_328 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_329 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_330 = execute_SRC_LESS; + assign _zz_331 = 3'b100; + assign _zz_332 = execute_INSTRUCTION[19 : 15]; + assign _zz_333 = execute_INSTRUCTION[31 : 20]; + assign _zz_334 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_335 = ($signed(_zz_336) + $signed(_zz_339)); + assign _zz_336 = ($signed(_zz_337) + $signed(_zz_338)); + assign _zz_337 = execute_SRC1; + assign _zz_338 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_339 = (execute_SRC_USE_SUB_LESS ? _zz_340 : _zz_341); + assign _zz_340 = 32'h00000001; + assign _zz_341 = 32'h0; + assign _zz_342 = execute_INSTRUCTION[31 : 20]; + assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_345 = {_zz_132,execute_INSTRUCTION[31 : 20]}; + assign _zz_346 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_347 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_348 = execute_INSTRUCTION[31 : 20]; + assign _zz_349 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_351 = 3'b100; + assign _zz_352 = (_zz_147 & (~ _zz_353)); + assign _zz_353 = (_zz_147 - 2'b01); + assign _zz_354 = (_zz_149 & (~ _zz_355)); + assign _zz_355 = (_zz_149 - 2'b01); + assign _zz_356 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_357 = execute_INSTRUCTION[31 : 24]; + assign _zz_358 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_359 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_360 = writeBack_MUL_LOW[31 : 0]; + assign _zz_361 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_362 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_363 = {5'd0, _zz_362}; + assign _zz_364 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_365 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_366 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_367 = {_zz_170,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_368 = _zz_369; + assign _zz_369 = _zz_370; + assign _zz_370 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_171) : _zz_171)} + _zz_372); + assign _zz_371 = memory_DivPlugin_div_needRevert; + assign _zz_372 = {32'd0, _zz_371}; + assign _zz_373 = _zz_173; + assign _zz_374 = {32'd0, _zz_373}; + assign _zz_375 = _zz_172; + assign _zz_376 = {31'd0, _zz_375}; + assign _zz_377 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_378 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_380 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_381 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_382 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_383 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_384 = (iBus_cmd_payload_address >>> 5); + assign _zz_385 = 1'b1; + assign _zz_386 = 1'b1; + assign _zz_387 = {_zz_65,_zz_64}; + assign _zz_388 = 32'h0000106f; + assign _zz_389 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_390 = 32'h00001073; + assign _zz_391 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_392 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_393 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_394) == 32'h00000003),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; + assign _zz_394 = 32'h0000207f; + assign _zz_395 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_396 = 32'h00000003; + assign _zz_397 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_398 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_399 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_400) == 32'h00005013),{(_zz_401 == _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; + assign _zz_400 = 32'hbc00707f; + assign _zz_401 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_402 = 32'h00001013; + assign _zz_403 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_405 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_406 = decode_INSTRUCTION[31]; + assign _zz_407 = decode_INSTRUCTION[31]; + assign _zz_408 = decode_INSTRUCTION[7]; + assign _zz_409 = (decode_INSTRUCTION & 32'h02004064); + assign _zz_410 = 32'h02004020; + assign _zz_411 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz_412 = (_zz_97 != 1'b0); + assign _zz_413 = (((decode_INSTRUCTION & _zz_415) == 32'h00000050) != 1'b0); + assign _zz_414 = {((_zz_416 == _zz_417) != 1'b0),{({_zz_418,_zz_419} != 2'b00),{(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}}}; + assign _zz_415 = 32'h00203050; + assign _zz_416 = (decode_INSTRUCTION & 32'h00403050); + assign _zz_417 = 32'h00000050; + assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00001050); + assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00002050); + assign _zz_420 = {_zz_96,(_zz_427 == _zz_428)}; + assign _zz_421 = 2'b00; + assign _zz_422 = ((_zz_429 == _zz_430) != 1'b0); + assign _zz_423 = ({_zz_431,_zz_432} != 2'b00); + assign _zz_424 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; + assign _zz_425 = 32'h00001050; + assign _zz_426 = 32'h00002050; + assign _zz_427 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz_428 = 32'h00000004; + assign _zz_429 = (decode_INSTRUCTION & 32'h00000058); + assign _zz_430 = 32'h00000040; + assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h00005010); + assign _zz_432 = ((decode_INSTRUCTION & _zz_439) == 32'h00005020); + assign _zz_433 = {(_zz_440 == _zz_441),{_zz_442,_zz_443}}; + assign _zz_434 = 3'b000; + assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); + assign _zz_436 = (_zz_446 != 1'b0); + assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; + assign _zz_438 = 32'h00007034; + assign _zz_439 = 32'h02007064; + assign _zz_440 = (decode_INSTRUCTION & 32'h40003054); + assign _zz_441 = 32'h40001010; + assign _zz_442 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz_443 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_445 = 32'h00000024; + assign _zz_446 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz_447 = ((decode_INSTRUCTION & _zz_452) == 32'h00002000); + assign _zz_448 = 1'b0; + assign _zz_449 = ({_zz_453,_zz_454} != 2'b00); + assign _zz_450 = (_zz_455 != 1'b0); + assign _zz_451 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; + assign _zz_452 = 32'h00003000; + assign _zz_453 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz_454 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz_455 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); + assign _zz_456 = {_zz_97,{_zz_461,_zz_462}}; + assign _zz_457 = 3'b000; + assign _zz_458 = ({_zz_463,{_zz_464,_zz_465}} != 5'h0); + assign _zz_459 = (_zz_466 != 1'b0); + assign _zz_460 = {(_zz_467 != _zz_468),{_zz_469,{_zz_470,_zz_471}}}; + assign _zz_461 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); + assign _zz_462 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); + assign _zz_463 = ((decode_INSTRUCTION & _zz_474) == 32'h00002040); + assign _zz_464 = (_zz_475 == _zz_476); + assign _zz_465 = {_zz_477,{_zz_478,_zz_479}}; + assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000020); + assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; + assign _zz_468 = 6'h0; + assign _zz_469 = ({_zz_484,_zz_485} != 5'h0); + assign _zz_470 = (_zz_486 != _zz_487); + assign _zz_471 = {_zz_488,{_zz_489,_zz_490}}; + assign _zz_472 = 32'h00000034; + assign _zz_473 = 32'h00000064; + assign _zz_474 = 32'h00002040; + assign _zz_475 = (decode_INSTRUCTION & 32'h00001040); + assign _zz_476 = 32'h00001040; + assign _zz_477 = ((decode_INSTRUCTION & _zz_491) == 32'h00000040); + assign _zz_478 = (_zz_492 == _zz_493); + assign _zz_479 = (_zz_494 == _zz_495); + assign _zz_480 = 32'h00000020; + assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00000008); + assign _zz_482 = (_zz_497 == _zz_498); + assign _zz_483 = {_zz_95,{_zz_499,_zz_500}}; + assign _zz_484 = _zz_95; + assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; + assign _zz_486 = {_zz_96,{_zz_504,_zz_505}}; + assign _zz_487 = 6'h0; + assign _zz_488 = ({_zz_506,_zz_507} != 2'b00); + assign _zz_489 = (_zz_508 != _zz_509); + assign _zz_490 = {_zz_510,{_zz_511,_zz_512}}; + assign _zz_491 = 32'h00000050; + assign _zz_492 = (decode_INSTRUCTION & 32'h00400040); + assign _zz_493 = 32'h00000040; + assign _zz_494 = (decode_INSTRUCTION & 32'h00000038); + assign _zz_495 = 32'h0; + assign _zz_496 = 32'h00000008; + assign _zz_497 = (decode_INSTRUCTION & 32'h00000040); + assign _zz_498 = 32'h00000040; + assign _zz_499 = (_zz_513 == _zz_514); + assign _zz_500 = {_zz_515,_zz_516}; + assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00002010); + assign _zz_502 = (_zz_518 == _zz_519); + assign _zz_503 = {_zz_520,_zz_521}; + assign _zz_504 = (_zz_522 == _zz_523); + assign _zz_505 = {_zz_524,{_zz_525,_zz_526}}; + assign _zz_506 = _zz_95; + assign _zz_507 = (_zz_527 == _zz_528); + assign _zz_508 = {_zz_95,_zz_529}; + assign _zz_509 = 2'b00; + assign _zz_510 = (_zz_530 != 1'b0); + assign _zz_511 = (_zz_531 != _zz_532); + assign _zz_512 = {_zz_533,{_zz_534,_zz_535}}; + assign _zz_513 = (decode_INSTRUCTION & 32'h00004020); + assign _zz_514 = 32'h00004020; + assign _zz_515 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); + assign _zz_516 = ((decode_INSTRUCTION & _zz_537) == 32'h00000020); + assign _zz_517 = 32'h00002030; + assign _zz_518 = (decode_INSTRUCTION & 32'h00001030); + assign _zz_519 = 32'h00000010; + assign _zz_520 = ((decode_INSTRUCTION & _zz_538) == 32'h00002020); + assign _zz_521 = ((decode_INSTRUCTION & _zz_539) == 32'h00000020); + assign _zz_522 = (decode_INSTRUCTION & 32'h00001010); + assign _zz_523 = 32'h00001010; + assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00002010); + assign _zz_525 = (_zz_541 == _zz_542); + assign _zz_526 = {_zz_543,_zz_544}; + assign _zz_527 = (decode_INSTRUCTION & 32'h00000070); + assign _zz_528 = 32'h00000020; + assign _zz_529 = ((decode_INSTRUCTION & _zz_545) == 32'h0); + assign _zz_530 = ((decode_INSTRUCTION & _zz_546) == 32'h00004010); + assign _zz_531 = (_zz_547 == _zz_548); + assign _zz_532 = 1'b0; + assign _zz_533 = ({_zz_549,_zz_550} != 4'b0000); + assign _zz_534 = (_zz_551 != _zz_552); + assign _zz_535 = {_zz_553,{_zz_554,_zz_555}}; + assign _zz_536 = 32'h00000030; + assign _zz_537 = 32'h02000020; + assign _zz_538 = 32'h02002060; + assign _zz_539 = 32'h02003020; + assign _zz_540 = 32'h00002010; + assign _zz_541 = (decode_INSTRUCTION & 32'h00000050); + assign _zz_542 = 32'h00000010; + assign _zz_543 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_544 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz_545 = 32'h00000020; + assign _zz_546 = 32'h00004014; + assign _zz_547 = (decode_INSTRUCTION & 32'h00006014); + assign _zz_548 = 32'h00002010; + assign _zz_549 = ((decode_INSTRUCTION & _zz_556) == 32'h0); + assign _zz_550 = {(_zz_557 == _zz_558),{_zz_559,_zz_560}}; + assign _zz_551 = ((decode_INSTRUCTION & _zz_561) == 32'h0); + assign _zz_552 = 1'b0; + assign _zz_553 = ({_zz_562,{_zz_563,_zz_564}} != 3'b000); + assign _zz_554 = ({_zz_565,_zz_566} != 2'b00); + assign _zz_555 = {(_zz_567 != _zz_568),(_zz_569 != _zz_570)}; + assign _zz_556 = 32'h00000044; + assign _zz_557 = (decode_INSTRUCTION & 32'h00000018); + assign _zz_558 = 32'h0; + assign _zz_559 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_560 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz_561 = 32'h00000058; + assign _zz_562 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz_563 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); + assign _zz_564 = ((decode_INSTRUCTION & _zz_572) == 32'h40000030); + assign _zz_565 = ((decode_INSTRUCTION & _zz_573) == 32'h00000004); + assign _zz_566 = _zz_94; + assign _zz_567 = {(_zz_574 == _zz_575),_zz_94}; + assign _zz_568 = 2'b00; + assign _zz_569 = ((decode_INSTRUCTION & _zz_576) == 32'h00001004); + assign _zz_570 = 1'b0; + assign _zz_571 = 32'h00002014; + assign _zz_572 = 32'h40000034; + assign _zz_573 = 32'h00000014; + assign _zz_574 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_575 = 32'h00000004; + assign _zz_576 = 32'h00005054; + assign _zz_577 = execute_INSTRUCTION[31]; + assign _zz_578 = execute_INSTRUCTION[31]; + assign _zz_579 = execute_INSTRUCTION[7]; + assign _zz_580 = 32'h0; + always @ (posedge clk) begin + if(_zz_385) begin + _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_386) begin + _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_48) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_217 ), //i + .io_cpu_prefetch_isValid (_zz_218 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_219 ), //i + .io_cpu_fetch_isStuck (_zz_220 ), //i + .io_cpu_fetch_isRemoved (_zz_221 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_222 ), //i + .io_cpu_decode_isStuck (_zz_223 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_224 ), //i + .io_cpu_fill_valid (_zz_225 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_226 ), //i + .io_cpu_execute_address (_zz_227[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_88[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_228 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_229[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_230 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_231 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_232 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_233[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_234 ), //i + .io_cpu_writeBack_fence_SR (_zz_235 ), //i + .io_cpu_writeBack_fence_SO (_zz_236 ), //i + .io_cpu_writeBack_fence_SI (_zz_237 ), //i + .io_cpu_writeBack_fence_PW (_zz_238 ), //i + .io_cpu_writeBack_fence_PR (_zz_239 ), //i + .io_cpu_writeBack_fence_PO (_zz_240 ), //i + .io_cpu_writeBack_fence_PI (_zz_241 ), //i + .io_cpu_writeBack_fence_FM (_zz_242[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_243 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_244 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_387) + 2'b00 : begin + _zz_247 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_247 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_247 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_247 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_1) + `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; + default : _zz_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_2) + `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; + default : _zz_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_3) + `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; + default : _zz_10_string = "?????"; + endcase + end + always @(*) begin + case(_zz_11) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; + default : _zz_12_string = "????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; + default : _zz_17_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; + default : _zz_20_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(_zz_23) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(_zz_26) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; + default : _zz_26_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_29) + `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; + default : _zz_29_string = "????????????"; + endcase + end + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; + default : _zz_32_string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_36) + `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; + default : _zz_36_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_39) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; + default : _zz_39_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_40) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; + default : _zz_40_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_42) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; + default : _zz_42_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_43) + `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; + default : _zz_43_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_44) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; + default : _zz_44_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; + default : _zz_45_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; + default : _zz_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_50) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; + default : _zz_50_string = "?????"; + endcase + end + always @(*) begin + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; + endcase + end + always @(*) begin + case(_zz_52) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; + default : _zz_52_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_53) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; + default : _zz_53_string = "?????"; + endcase + end + always @(*) begin + case(_zz_54) + `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; + default : _zz_54_string = "???"; + endcase + end + always @(*) begin + case(_zz_55) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; + default : _zz_55_string = "????????"; + endcase + end + always @(*) begin + case(_zz_56) + `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; + default : _zz_56_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_58) + `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; + default : _zz_58_string = "????"; + endcase + end + always @(*) begin + case(_zz_99) + `Src1CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_99_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99_string = "URS1 "; + default : _zz_99_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_100) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_100_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_100_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_100_string = "BITWISE "; + default : _zz_100_string = "????????"; + endcase + end + always @(*) begin + case(_zz_101) + `Src2CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_101_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_101_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_101_string = "PC "; + default : _zz_101_string = "???"; + endcase + end + always @(*) begin + case(_zz_102) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_102_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_102_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_102_string = "AND_1"; + default : _zz_102_string = "?????"; + endcase + end + always @(*) begin + case(_zz_103) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_103_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_103_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_103_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_103_string = "SRA_1 "; + default : _zz_103_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_104) + `BranchCtrlEnum_defaultEncoding_INC : _zz_104_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_104_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_104_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_104_string = "JALR"; + default : _zz_104_string = "????"; + endcase + end + always @(*) begin + case(_zz_105) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_105_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_105_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_105_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_105_string = "ECALL"; + default : _zz_105_string = "?????"; + endcase + end + always @(*) begin + case(_zz_106) + `Input2Kind_defaultEncoding_RS : _zz_106_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_106_string = "IMM_I"; + default : _zz_106_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign execute_SHIFT_RIGHT = _zz_297; + assign execute_REGFILE_WRITE_DATA = _zz_108; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_227[1 : 0]; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_299[0]; + assign decode_IS_RS1_SIGNED = _zz_300[0]; + assign decode_IS_DIV = _zz_301[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_302[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; + assign _zz_2 = _zz_3; + assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; + assign _zz_4 = _zz_5; + assign _zz_6 = _zz_7; + assign decode_ENV_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_IS_CSR = _zz_304[0]; + assign _zz_11 = _zz_12; + assign _zz_13 = _zz_14; + assign decode_SHIFT_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_ALU_BITWISE_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; + assign decode_MEMORY_MANAGMENT = _zz_306[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_307[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; + assign decode_SRC2_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_ALU_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_SRC1_CTRL = _zz_27; + assign _zz_28 = _zz_29; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + always @ (*) begin + _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck)begin + _zz_30 = 1'b0; + end + end + + always @ (*) begin + _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck)begin + _zz_31 = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_33; + assign execute_ENV_CTRL = _zz_34; + assign writeBack_ENV_CTRL = _zz_35; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_130; + assign execute_BRANCH_CTRL = _zz_36; + assign decode_RS2_USE = _zz_310[0]; + assign decode_RS1_USE = _zz_311[0]; + always @ (*) begin + _zz_37 = execute_REGFILE_WRITE_DATA; + if(_zz_248)begin + _zz_37 = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_119)begin + if((_zz_120 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_121; + end + end + if(_zz_249)begin + if(_zz_250)begin + if(_zz_123)begin + decode_RS2 = _zz_57; + end + end + end + if(_zz_251)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_125)begin + decode_RS2 = _zz_38; + end + end + end + if(_zz_252)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_127)begin + decode_RS2 = _zz_37; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_119)begin + if((_zz_120 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_121; + end + end + if(_zz_249)begin + if(_zz_250)begin + if(_zz_122)begin + decode_RS1 = _zz_57; + end + end + end + if(_zz_251)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_124)begin + decode_RS1 = _zz_38; + end + end + end + if(_zz_252)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_126)begin + decode_RS1 = _zz_37; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_38 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_38 = _zz_116; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_38 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_253)begin + _zz_38 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_39; + assign execute_SHIFT_CTRL = _zz_40; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_41 = execute_PC; + assign execute_SRC2_CTRL = _zz_42; + assign execute_SRC1_CTRL = _zz_43; + assign decode_SRC_USE_SUB_LESS = _zz_312[0]; + assign decode_SRC_ADD_ZERO = _zz_313[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_44; + assign execute_SRC2 = _zz_114; + assign execute_SRC1 = _zz_109; + assign execute_ALU_BITWISE_CTRL = _zz_45; + assign _zz_46 = writeBack_INSTRUCTION; + assign _zz_47 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_48 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_48 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_314[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}} != 22'h0); + always @ (*) begin + _zz_57 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_286) + 2'b00 : begin + _zz_57 = _zz_360; + end + default : begin + _zz_57 = _zz_361; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_315[0]; + assign decode_FLUSH_ALL = _zz_316[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_254)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_255)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_256)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_257)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_58; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_59 = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_59 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_60 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_117 || _zz_118)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_258)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_258)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((_zz_243 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_259)begin + if((! execute_CsrPlugin_wfiWake))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_248)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(_zz_260)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_260)begin + execute_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if((! memory_CfuPlugin_rsp_valid))begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_253)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(CfuPlugin_joinException_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(CfuPlugin_joinException_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_261)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_262)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_261)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_262)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_259)begin + CsrPlugin_inWfi = 1'b1; + end + end + + assign CsrPlugin_thirdPartyWake = 1'b0; + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_261)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_262)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_261)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_262)begin + case(_zz_263) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_62 = (_zz_61 & (~ _zz_317)); + assign _zz_63 = _zz_62[3]; + assign _zz_64 = (_zz_62[1] || _zz_63); + assign _zz_65 = (_zz_62[2] || _zz_63); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_319); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_66); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_69; + assign _zz_69 = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_70 = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_72)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_72 = _zz_73; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_74; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign _zz_75 = _zz_320[11]; + always @ (*) begin + _zz_76[18] = _zz_75; + _zz_76[17] = _zz_75; + _zz_76[16] = _zz_75; + _zz_76[15] = _zz_75; + _zz_76[14] = _zz_75; + _zz_76[13] = _zz_75; + _zz_76[12] = _zz_75; + _zz_76[11] = _zz_75; + _zz_76[10] = _zz_75; + _zz_76[9] = _zz_75; + _zz_76[8] = _zz_75; + _zz_76[7] = _zz_75; + _zz_76[6] = _zz_75; + _zz_76[5] = _zz_75; + _zz_76[4] = _zz_75; + _zz_76[3] = _zz_75; + _zz_76[2] = _zz_75; + _zz_76[1] = _zz_75; + _zz_76[0] = _zz_75; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_321[31])); + if(_zz_81)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_77 = _zz_322[19]; + always @ (*) begin + _zz_78[10] = _zz_77; + _zz_78[9] = _zz_77; + _zz_78[8] = _zz_77; + _zz_78[7] = _zz_77; + _zz_78[6] = _zz_77; + _zz_78[5] = _zz_77; + _zz_78[4] = _zz_77; + _zz_78[3] = _zz_77; + _zz_78[2] = _zz_77; + _zz_78[1] = _zz_77; + _zz_78[0] = _zz_77; + end + + assign _zz_79 = _zz_323[11]; + always @ (*) begin + _zz_80[18] = _zz_79; + _zz_80[17] = _zz_79; + _zz_80[16] = _zz_79; + _zz_80[15] = _zz_79; + _zz_80[14] = _zz_79; + _zz_80[13] = _zz_79; + _zz_80[12] = _zz_79; + _zz_80[11] = _zz_79; + _zz_80[10] = _zz_79; + _zz_80[9] = _zz_79; + _zz_80[8] = _zz_79; + _zz_80[7] = _zz_79; + _zz_80[6] = _zz_79; + _zz_80[5] = _zz_79; + _zz_80[4] = _zz_79; + _zz_80[3] = _zz_79; + _zz_80[2] = _zz_79; + _zz_80[1] = _zz_79; + _zz_80[0] = _zz_79; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_81 = _zz_324[1]; + end + default : begin + _zz_81 = _zz_325[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_82 = _zz_326[19]; + always @ (*) begin + _zz_83[10] = _zz_82; + _zz_83[9] = _zz_82; + _zz_83[8] = _zz_82; + _zz_83[7] = _zz_82; + _zz_83[6] = _zz_82; + _zz_83[5] = _zz_82; + _zz_83[4] = _zz_82; + _zz_83[3] = _zz_82; + _zz_83[2] = _zz_82; + _zz_83[1] = _zz_82; + _zz_83[0] = _zz_82; + end + + assign _zz_84 = _zz_327[11]; + always @ (*) begin + _zz_85[18] = _zz_84; + _zz_85[17] = _zz_84; + _zz_85[16] = _zz_84; + _zz_85[15] = _zz_84; + _zz_85[14] = _zz_84; + _zz_85[13] = _zz_84; + _zz_85[12] = _zz_84; + _zz_85[11] = _zz_84; + _zz_85[10] = _zz_84; + _zz_85[9] = _zz_84; + _zz_85[8] = _zz_84; + _zz_85[7] = _zz_84; + _zz_85[6] = _zz_84; + _zz_85[5] = _zz_84; + _zz_85[4] = _zz_84; + _zz_85[3] = _zz_84; + _zz_85[2] = _zz_84; + _zz_85[1] = _zz_84; + _zz_85[0] = _zz_84; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_406,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_407,_zz_408},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_219; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_224 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_257)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_255)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_225 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_255)begin + _zz_225 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_256)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_254)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_256)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_254)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_217 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_244 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_227 = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_88 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_88 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_88 = execute_RS2[31 : 0]; + end + endcase + end + + assign _zz_243 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_228 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_229 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_228; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_229; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @ (*) begin + _zz_230 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_230 = 1'b1; + end + end + + assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_232 = (CsrPlugin_privilege == 2'b00); + assign _zz_233 = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_264)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_264)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_264)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_89 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_90[31] = _zz_89; + _zz_90[30] = _zz_89; + _zz_90[29] = _zz_89; + _zz_90[28] = _zz_89; + _zz_90[27] = _zz_89; + _zz_90[26] = _zz_89; + _zz_90[25] = _zz_89; + _zz_90[24] = _zz_89; + _zz_90[23] = _zz_89; + _zz_90[22] = _zz_89; + _zz_90[21] = _zz_89; + _zz_90[20] = _zz_89; + _zz_90[19] = _zz_89; + _zz_90[18] = _zz_89; + _zz_90[17] = _zz_89; + _zz_90[16] = _zz_89; + _zz_90[15] = _zz_89; + _zz_90[14] = _zz_89; + _zz_90[13] = _zz_89; + _zz_90[12] = _zz_89; + _zz_90[11] = _zz_89; + _zz_90[10] = _zz_89; + _zz_90[9] = _zz_89; + _zz_90[8] = _zz_89; + _zz_90[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_91 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_92[31] = _zz_91; + _zz_92[30] = _zz_91; + _zz_92[29] = _zz_91; + _zz_92[28] = _zz_91; + _zz_92[27] = _zz_91; + _zz_92[26] = _zz_91; + _zz_92[25] = _zz_91; + _zz_92[24] = _zz_91; + _zz_92[23] = _zz_91; + _zz_92[22] = _zz_91; + _zz_92[21] = _zz_91; + _zz_92[20] = _zz_91; + _zz_92[19] = _zz_91; + _zz_92[18] = _zz_91; + _zz_92[17] = _zz_91; + _zz_92[16] = _zz_91; + _zz_92[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_284) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_90; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_92; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_94 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_95 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_409 == _zz_410) != 1'b0),{(_zz_411 != 1'b0),{1'b0,{_zz_412,{_zz_413,_zz_414}}}}}}}; + assign _zz_99 = _zz_93[2 : 1]; + assign _zz_56 = _zz_99; + assign _zz_100 = _zz_93[7 : 6]; + assign _zz_55 = _zz_100; + assign _zz_101 = _zz_93[9 : 8]; + assign _zz_54 = _zz_101; + assign _zz_102 = _zz_93[19 : 18]; + assign _zz_53 = _zz_102; + assign _zz_103 = _zz_93[22 : 21]; + assign _zz_52 = _zz_103; + assign _zz_104 = _zz_93[24 : 23]; + assign _zz_51 = _zz_104; + assign _zz_105 = _zz_93[27 : 26]; + assign _zz_50 = _zz_105; + assign _zz_106 = _zz_93[29 : 29]; + assign _zz_49 = _zz_106; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_245; + assign decode_RegFilePlugin_rs2Data = _zz_246; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); + if(_zz_107)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; + if(_zz_107)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_57; + if(_zz_107)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_108 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_108 = {31'd0, _zz_330}; + end + default : begin + _zz_108 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_109 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_109 = {29'd0, _zz_331}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_109 = {27'd0, _zz_332}; + end + endcase + end + + assign _zz_110 = _zz_333[11]; + always @ (*) begin + _zz_111[19] = _zz_110; + _zz_111[18] = _zz_110; + _zz_111[17] = _zz_110; + _zz_111[16] = _zz_110; + _zz_111[15] = _zz_110; + _zz_111[14] = _zz_110; + _zz_111[13] = _zz_110; + _zz_111[12] = _zz_110; + _zz_111[11] = _zz_110; + _zz_111[10] = _zz_110; + _zz_111[9] = _zz_110; + _zz_111[8] = _zz_110; + _zz_111[7] = _zz_110; + _zz_111[6] = _zz_110; + _zz_111[5] = _zz_110; + _zz_111[4] = _zz_110; + _zz_111[3] = _zz_110; + _zz_111[2] = _zz_110; + _zz_111[1] = _zz_110; + _zz_111[0] = _zz_110; + end + + assign _zz_112 = _zz_334[11]; + always @ (*) begin + _zz_113[19] = _zz_112; + _zz_113[18] = _zz_112; + _zz_113[17] = _zz_112; + _zz_113[16] = _zz_112; + _zz_113[15] = _zz_112; + _zz_113[14] = _zz_112; + _zz_113[13] = _zz_112; + _zz_113[12] = _zz_112; + _zz_113[11] = _zz_112; + _zz_113[10] = _zz_112; + _zz_113[9] = _zz_112; + _zz_113[8] = _zz_112; + _zz_113[7] = _zz_112; + _zz_113[6] = _zz_112; + _zz_113[5] = _zz_112; + _zz_113[4] = _zz_112; + _zz_113[3] = _zz_112; + _zz_113[2] = _zz_112; + _zz_113[1] = _zz_112; + _zz_113[0] = _zz_112; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_114 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_114 = {_zz_111,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_114 = {_zz_113,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_114 = _zz_41; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_335; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_115[0] = execute_SRC1[31]; + _zz_115[1] = execute_SRC1[30]; + _zz_115[2] = execute_SRC1[29]; + _zz_115[3] = execute_SRC1[28]; + _zz_115[4] = execute_SRC1[27]; + _zz_115[5] = execute_SRC1[26]; + _zz_115[6] = execute_SRC1[25]; + _zz_115[7] = execute_SRC1[24]; + _zz_115[8] = execute_SRC1[23]; + _zz_115[9] = execute_SRC1[22]; + _zz_115[10] = execute_SRC1[21]; + _zz_115[11] = execute_SRC1[20]; + _zz_115[12] = execute_SRC1[19]; + _zz_115[13] = execute_SRC1[18]; + _zz_115[14] = execute_SRC1[17]; + _zz_115[15] = execute_SRC1[16]; + _zz_115[16] = execute_SRC1[15]; + _zz_115[17] = execute_SRC1[14]; + _zz_115[18] = execute_SRC1[13]; + _zz_115[19] = execute_SRC1[12]; + _zz_115[20] = execute_SRC1[11]; + _zz_115[21] = execute_SRC1[10]; + _zz_115[22] = execute_SRC1[9]; + _zz_115[23] = execute_SRC1[8]; + _zz_115[24] = execute_SRC1[7]; + _zz_115[25] = execute_SRC1[6]; + _zz_115[26] = execute_SRC1[5]; + _zz_115[27] = execute_SRC1[4]; + _zz_115[28] = execute_SRC1[3]; + _zz_115[29] = execute_SRC1[2]; + _zz_115[30] = execute_SRC1[1]; + _zz_115[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_115 : execute_SRC1); + always @ (*) begin + _zz_116[0] = memory_SHIFT_RIGHT[31]; + _zz_116[1] = memory_SHIFT_RIGHT[30]; + _zz_116[2] = memory_SHIFT_RIGHT[29]; + _zz_116[3] = memory_SHIFT_RIGHT[28]; + _zz_116[4] = memory_SHIFT_RIGHT[27]; + _zz_116[5] = memory_SHIFT_RIGHT[26]; + _zz_116[6] = memory_SHIFT_RIGHT[25]; + _zz_116[7] = memory_SHIFT_RIGHT[24]; + _zz_116[8] = memory_SHIFT_RIGHT[23]; + _zz_116[9] = memory_SHIFT_RIGHT[22]; + _zz_116[10] = memory_SHIFT_RIGHT[21]; + _zz_116[11] = memory_SHIFT_RIGHT[20]; + _zz_116[12] = memory_SHIFT_RIGHT[19]; + _zz_116[13] = memory_SHIFT_RIGHT[18]; + _zz_116[14] = memory_SHIFT_RIGHT[17]; + _zz_116[15] = memory_SHIFT_RIGHT[16]; + _zz_116[16] = memory_SHIFT_RIGHT[15]; + _zz_116[17] = memory_SHIFT_RIGHT[14]; + _zz_116[18] = memory_SHIFT_RIGHT[13]; + _zz_116[19] = memory_SHIFT_RIGHT[12]; + _zz_116[20] = memory_SHIFT_RIGHT[11]; + _zz_116[21] = memory_SHIFT_RIGHT[10]; + _zz_116[22] = memory_SHIFT_RIGHT[9]; + _zz_116[23] = memory_SHIFT_RIGHT[8]; + _zz_116[24] = memory_SHIFT_RIGHT[7]; + _zz_116[25] = memory_SHIFT_RIGHT[6]; + _zz_116[26] = memory_SHIFT_RIGHT[5]; + _zz_116[27] = memory_SHIFT_RIGHT[4]; + _zz_116[28] = memory_SHIFT_RIGHT[3]; + _zz_116[29] = memory_SHIFT_RIGHT[2]; + _zz_116[30] = memory_SHIFT_RIGHT[1]; + _zz_116[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_117 = 1'b0; + if(_zz_265)begin + if(_zz_266)begin + if(_zz_122)begin + _zz_117 = 1'b1; + end + end + end + if(_zz_267)begin + if(_zz_268)begin + if(_zz_124)begin + _zz_117 = 1'b1; + end + end + end + if(_zz_269)begin + if(_zz_270)begin + if(_zz_126)begin + _zz_117 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_117 = 1'b0; + end + end + + always @ (*) begin + _zz_118 = 1'b0; + if(_zz_265)begin + if(_zz_266)begin + if(_zz_123)begin + _zz_118 = 1'b1; + end + end + end + if(_zz_267)begin + if(_zz_268)begin + if(_zz_125)begin + _zz_118 = 1'b1; + end + end + end + if(_zz_269)begin + if(_zz_270)begin + if(_zz_127)begin + _zz_118 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_118 = 1'b0; + end + end + + assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_128 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_128 == 3'b000)) begin + _zz_129 = execute_BranchPlugin_eq; + end else if((_zz_128 == 3'b001)) begin + _zz_129 = (! execute_BranchPlugin_eq); + end else if((((_zz_128 & 3'b101) == 3'b101))) begin + _zz_129 = (! execute_SRC_LESS); + end else begin + _zz_129 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_130 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_130 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_130 = 1'b1; + end + default : begin + _zz_130 = _zz_129; + end + endcase + end + + assign _zz_131 = _zz_342[11]; + always @ (*) begin + _zz_132[19] = _zz_131; + _zz_132[18] = _zz_131; + _zz_132[17] = _zz_131; + _zz_132[16] = _zz_131; + _zz_132[15] = _zz_131; + _zz_132[14] = _zz_131; + _zz_132[13] = _zz_131; + _zz_132[12] = _zz_131; + _zz_132[11] = _zz_131; + _zz_132[10] = _zz_131; + _zz_132[9] = _zz_131; + _zz_132[8] = _zz_131; + _zz_132[7] = _zz_131; + _zz_132[6] = _zz_131; + _zz_132[5] = _zz_131; + _zz_132[4] = _zz_131; + _zz_132[3] = _zz_131; + _zz_132[2] = _zz_131; + _zz_132[1] = _zz_131; + _zz_132[0] = _zz_131; + end + + assign _zz_133 = _zz_343[19]; + always @ (*) begin + _zz_134[10] = _zz_133; + _zz_134[9] = _zz_133; + _zz_134[8] = _zz_133; + _zz_134[7] = _zz_133; + _zz_134[6] = _zz_133; + _zz_134[5] = _zz_133; + _zz_134[4] = _zz_133; + _zz_134[3] = _zz_133; + _zz_134[2] = _zz_133; + _zz_134[1] = _zz_133; + _zz_134[0] = _zz_133; + end + + assign _zz_135 = _zz_344[11]; + always @ (*) begin + _zz_136[18] = _zz_135; + _zz_136[17] = _zz_135; + _zz_136[16] = _zz_135; + _zz_136[15] = _zz_135; + _zz_136[14] = _zz_135; + _zz_136[13] = _zz_135; + _zz_136[12] = _zz_135; + _zz_136[11] = _zz_135; + _zz_136[10] = _zz_135; + _zz_136[9] = _zz_135; + _zz_136[8] = _zz_135; + _zz_136[7] = _zz_135; + _zz_136[6] = _zz_135; + _zz_136[5] = _zz_135; + _zz_136[4] = _zz_135; + _zz_136[3] = _zz_135; + _zz_136[2] = _zz_135; + _zz_136[1] = _zz_135; + _zz_136[0] = _zz_135; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_137 = (_zz_345[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_137 = _zz_346[1]; + end + default : begin + _zz_137 = _zz_347[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_137); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_138 = _zz_348[11]; + always @ (*) begin + _zz_139[19] = _zz_138; + _zz_139[18] = _zz_138; + _zz_139[17] = _zz_138; + _zz_139[16] = _zz_138; + _zz_139[15] = _zz_138; + _zz_139[14] = _zz_138; + _zz_139[13] = _zz_138; + _zz_139[12] = _zz_138; + _zz_139[11] = _zz_138; + _zz_139[10] = _zz_138; + _zz_139[9] = _zz_138; + _zz_139[8] = _zz_138; + _zz_139[7] = _zz_138; + _zz_139[6] = _zz_138; + _zz_139[5] = _zz_138; + _zz_139[4] = _zz_138; + _zz_139[3] = _zz_138; + _zz_139[2] = _zz_138; + _zz_139[1] = _zz_138; + _zz_139[0] = _zz_138; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_577,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_578,_zz_579},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_351}; + end + end + endcase + end + + assign _zz_140 = _zz_349[19]; + always @ (*) begin + _zz_141[10] = _zz_140; + _zz_141[9] = _zz_140; + _zz_141[8] = _zz_140; + _zz_141[7] = _zz_140; + _zz_141[6] = _zz_140; + _zz_141[5] = _zz_140; + _zz_141[4] = _zz_140; + _zz_141[3] = _zz_140; + _zz_141[2] = _zz_140; + _zz_141[1] = _zz_140; + _zz_141[0] = _zz_140; + end + + assign _zz_142 = _zz_350[11]; + always @ (*) begin + _zz_143[18] = _zz_142; + _zz_143[17] = _zz_142; + _zz_143[16] = _zz_142; + _zz_143[15] = _zz_142; + _zz_143[14] = _zz_142; + _zz_143[13] = _zz_142; + _zz_143[12] = _zz_142; + _zz_143[11] = _zz_142; + _zz_143[10] = _zz_142; + _zz_143[9] = _zz_142; + _zz_143[8] = _zz_142; + _zz_143[7] = _zz_142; + _zz_143[6] = _zz_142; + _zz_143[5] = _zz_142; + _zz_143[4] = _zz_142; + _zz_143[3] = _zz_142; + _zz_143[2] = _zz_142; + _zz_143[1] = _zz_142; + _zz_143[0] = _zz_142; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_144 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_145 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_146 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_148 = _zz_352[0]; + assign _zz_149 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_150 = _zz_354[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_258)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_260)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2820)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2822)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2824)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2826)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2828)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2830)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_271)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_272)begin + CsrPlugin_selfException_valid = 1'b1; + end + if(_zz_273)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_272)begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(_zz_273)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_271)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_271)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_285) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign execute_CfuPlugin_functionsIds_0 = _zz_356; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_167 = _zz_357[7]; + always @ (*) begin + _zz_168[23] = _zz_167; + _zz_168[22] = _zz_167; + _zz_168[21] = _zz_167; + _zz_168[20] = _zz_167; + _zz_168[19] = _zz_167; + _zz_168[18] = _zz_167; + _zz_168[17] = _zz_167; + _zz_168[16] = _zz_167; + _zz_168[15] = _zz_167; + _zz_168[14] = _zz_167; + _zz_168[13] = _zz_167; + _zz_168[12] = _zz_167; + _zz_168[11] = _zz_167; + _zz_168[10] = _zz_167; + _zz_168[9] = _zz_167; + _zz_168[8] = _zz_167; + _zz_168[7] = _zz_167; + _zz_168[6] = _zz_167; + _zz_168[5] = _zz_167; + _zz_168[4] = _zz_167; + _zz_168[3] = _zz_167; + _zz_168[2] = _zz_167; + _zz_168[1] = _zz_167; + _zz_168[0] = _zz_167; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : begin + _zz_169 = execute_RS2; + end + default : begin + _zz_169 = {_zz_168,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_169; + assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); + assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); + assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @ (*) begin + CfuPlugin_joinException_valid = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if(memory_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); + end + end + end + + assign CfuPlugin_joinException_payload_code = 4'b1111; + assign CfuPlugin_joinException_payload_badAddr = 32'h0; + always @ (*) begin + memory_CfuPlugin_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_274) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_274) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_358) + $signed(_zz_359)); + assign memory_DivPlugin_frontendOk = 1'b1; + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_253)begin + if(_zz_275)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_276)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_363); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_170 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_170[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_364); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_365 : _zz_366); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_367[31:0]; + assign _zz_171 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_172 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_173 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_174[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_174[31 : 0] = execute_RS1; + end + + assign _zz_176 = (_zz_175 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_176 != 32'h0); + assign _zz_29 = decode_SRC1_CTRL; + assign _zz_27 = _zz_56; + assign _zz_43 = decode_to_execute_SRC1_CTRL; + assign _zz_26 = decode_ALU_CTRL; + assign _zz_24 = _zz_55; + assign _zz_44 = decode_to_execute_ALU_CTRL; + assign _zz_23 = decode_SRC2_CTRL; + assign _zz_21 = _zz_54; + assign _zz_42 = decode_to_execute_SRC2_CTRL; + assign _zz_20 = decode_ALU_BITWISE_CTRL; + assign _zz_18 = _zz_53; + assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_17 = decode_SHIFT_CTRL; + assign _zz_14 = execute_SHIFT_CTRL; + assign _zz_15 = _zz_52; + assign _zz_40 = decode_to_execute_SHIFT_CTRL; + assign _zz_39 = execute_to_memory_SHIFT_CTRL; + assign _zz_12 = decode_BRANCH_CTRL; + assign _zz_58 = _zz_51; + assign _zz_36 = decode_to_execute_BRANCH_CTRL; + assign _zz_10 = decode_ENV_CTRL; + assign _zz_7 = execute_ENV_CTRL; + assign _zz_5 = memory_ENV_CTRL; + assign _zz_8 = _zz_50; + assign _zz_34 = decode_to_execute_ENV_CTRL; + assign _zz_33 = execute_to_memory_ENV_CTRL; + assign _zz_35 = memory_to_writeBack_ENV_CTRL; + assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_1 = _zz_49; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_177 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_177[12 : 0] = 13'h1000; + _zz_177[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_178 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_178[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_179 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_179[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_180[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_181[31 : 30] = CsrPlugin_misa_base; + _zz_181[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_182[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_182[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_182[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_183[11 : 11] = CsrPlugin_mip_MEIP; + _zz_183[7 : 7] = CsrPlugin_mip_MTIP; + _zz_183[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_184 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_184[11 : 11] = CsrPlugin_mie_MEIE; + _zz_184[7 : 7] = CsrPlugin_mie_MTIE; + _zz_184[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_185 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_185[31 : 2] = CsrPlugin_mtvec_base; + _zz_185[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_186 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_186[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_187 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_187[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_188 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_188[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_188[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_189 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_189[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_190 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_191 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_192 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_193 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_194 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_195 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_196 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_197 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_198 = 32'h0; + if(execute_CsrPlugin_csr_2820)begin + _zz_198[31 : 0] = _zz_151; + end + end + + always @ (*) begin + _zz_199 = 32'h0; + if(execute_CsrPlugin_csr_2822)begin + _zz_199[31 : 0] = _zz_153; + end + end + + always @ (*) begin + _zz_200 = 32'h0; + if(execute_CsrPlugin_csr_2824)begin + _zz_200[31 : 0] = _zz_155; + end + end + + always @ (*) begin + _zz_201 = 32'h0; + if(execute_CsrPlugin_csr_2826)begin + _zz_201[31 : 0] = _zz_157; + end + end + + always @ (*) begin + _zz_202 = 32'h0; + if(execute_CsrPlugin_csr_2828)begin + _zz_202[31 : 0] = _zz_159; + end + end + + always @ (*) begin + _zz_203 = 32'h0; + if(execute_CsrPlugin_csr_2830)begin + _zz_203[31 : 0] = _zz_161; + end + end + + always @ (*) begin + _zz_204 = 32'h0; + if(execute_CsrPlugin_csr_2832)begin + _zz_204[31 : 0] = _zz_163; + end + end + + always @ (*) begin + _zz_205 = 32'h0; + if(execute_CsrPlugin_csr_2834)begin + _zz_205[31 : 0] = _zz_165; + end + end + + always @ (*) begin + _zz_206 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_206[31 : 0] = _zz_175; + end + end + + always @ (*) begin + _zz_207 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_207[31 : 0] = _zz_176; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_580 | _zz_181) | (_zz_182 | _zz_183))) | (((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191)))) | ((((_zz_192 | _zz_193) | (_zz_194 | _zz_195)) | ((_zz_196 | _zz_197) | (_zz_198 | _zz_199))) | (((_zz_200 | _zz_201) | (_zz_202 | _zz_203)) | ((_zz_204 | _zz_205) | (_zz_206 | _zz_207))))); + assign iBusWishbone_ADR = {_zz_384,_zz_208}; + assign iBusWishbone_CTI = ((_zz_208 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'h0; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_277)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_277)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_209; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_215 = (dBus_cmd_payload_length != 3'b000); + assign _zz_211 = dBus_cmd_valid; + assign _zz_213 = dBus_cmd_payload_wr; + assign _zz_214 = (_zz_210 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_212 && (_zz_213 || _zz_214)); + assign dBusWishbone_ADR = ((_zz_215 ? {{dBus_cmd_payload_address[31 : 5],_zz_210},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_215 ? (_zz_214 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_213 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_213; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_212 = (_zz_211 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_211; + assign dBusWishbone_STB = _zz_211; + assign dBus_rsp_valid = _zz_216; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_71 <= 1'b0; + _zz_73 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_86; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_87; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_107 <= 1'b1; + _zz_119 <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_CfuPlugin_hold <= 1'b0; + execute_CfuPlugin_fired <= 1'b0; + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_175 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; + _zz_208 <= 3'b000; + _zz_209 <= 1'b0; + _zz_210 <= 3'b000; + _zz_216 <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_71 <= 1'b0; + end + if(_zz_69)begin + _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_73 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_73 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(_zz_278)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_107 <= 1'b0; + _zz_119 <= (_zz_47 && writeBack_arbitration_isFiring); + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_279)begin + if(_zz_280)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_281)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_282)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_261)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_262)begin + case(_zz_263) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_146,{_zz_145,_zz_144}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(execute_CfuPlugin_schedule)begin + execute_CfuPlugin_hold <= 1'b1; + end + if(CfuPlugin_bus_cmd_ready)begin + execute_CfuPlugin_hold <= 1'b0; + end + if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + execute_CfuPlugin_fired <= 1'b1; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_CfuPlugin_fired <= 1'b0; + end + if(memory_CfuPlugin_rsp_ready)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + end + if(_zz_283)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + end + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! memory_arbitration_isStuck))begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_377[0]; + CsrPlugin_mstatus_MIE <= _zz_378[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_380[0]; + CsrPlugin_mie_MTIE <= _zz_381[0]; + CsrPlugin_mie_MSIE <= _zz_382[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_175 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_277)begin + if(iBusWishbone_ACK)begin + _zz_208 <= (_zz_208 + 3'b001); + end + end + _zz_209 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_211 && _zz_212))begin + _zz_210 <= (_zz_210 + 3'b001); + if(_zz_214)begin + _zz_210 <= 3'b000; + end + end + _zz_216 <= ((_zz_211 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_74 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_278)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + _zz_120 <= _zz_46[11 : 7]; + _zz_121 <= _zz_57; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_258)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_260)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + end + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_279)begin + if(_zz_280)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_281)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_282)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_261)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(_zz_152[0])begin + _zz_151 <= (_zz_151 + 32'h00000001); + end + if(_zz_154[0])begin + _zz_153 <= (_zz_153 + 32'h00000001); + end + if(_zz_156[0])begin + _zz_155 <= (_zz_155 + 32'h00000001); + end + if(_zz_158[0])begin + _zz_157 <= (_zz_157 + 32'h00000001); + end + if(_zz_160[0])begin + _zz_159 <= (_zz_159 + 32'h00000001); + end + if(_zz_162[0])begin + _zz_161 <= (_zz_161 + 32'h00000001); + end + if(_zz_164[0])begin + _zz_163 <= (_zz_163 + 32'h00000001); + end + if(_zz_166[0])begin + _zz_165 <= (_zz_165 + 32'h00000001); + end + if(_zz_283)begin + CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_253)begin + if(_zz_275)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_368[31:0]; + end + end + end + if(_zz_276)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_173 ? (~ _zz_174) : _zz_174) + _zz_374); + memory_DivPlugin_rs2 <= ((_zz_172 ? (~ execute_RS2) : execute_RS2) + _zz_376); + memory_DivPlugin_div_needRevert <= ((_zz_173 ^ (_zz_172 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_41; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_28; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_16; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_13; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_379[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_383[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_9; + reg [22:0] _zz_10; + wire _zz_11; + wire _zz_12; + wire [0:0] _zz_13; + wire [0:0] _zz_14; + wire [22:0] _zz_15; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [8:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [8:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; + + assign _zz_11 = (! lineLoader_flushCounter[6]); + assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_13 = _zz_8[0 : 0]; + assign _zz_14 = _zz_8[1 : 1]; + assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_9 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_10 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_11)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_10; + assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_12)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_11)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_3 <= lineLoader_flushCounter[6]; + if(_zz_12)begin + lineLoader_flushCounter <= 7'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.yaml new file mode 100644 index 0000000..b55f8e5 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.yaml @@ -0,0 +1,4 @@ +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.v new file mode 100644 index 0000000..81f1a5b --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.v @@ -0,0 +1,7221 @@ +// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Component : VexRiscv +// Git hash : cbb04d34fec970ebb660147932da0bb4bb5adce0 + + +`define Input2Kind_defaultEncoding_type [0:0] +`define Input2Kind_defaultEncoding_RS 1'b0 +`define Input2Kind_defaultEncoding_IMM_I 1'b1 + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input CfuPlugin_bus_rsp_payload_response_ok, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, + input [31:0] externalInterruptArray, + input debug_bus_cmd_valid, + output reg debug_bus_cmd_ready, + input debug_bus_cmd_payload_wr, + input [7:0] debug_bus_cmd_payload_address, + input [31:0] debug_bus_cmd_payload_data, + output reg [31:0] debug_bus_rsp_data, + output debug_resetOut, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset, + input debugReset +); + wire _zz_220; + wire _zz_221; + wire _zz_222; + wire _zz_223; + wire _zz_224; + wire _zz_225; + wire _zz_226; + wire _zz_227; + reg _zz_228; + wire _zz_229; + wire [31:0] _zz_230; + wire _zz_231; + wire [31:0] _zz_232; + reg _zz_233; + wire _zz_234; + wire _zz_235; + wire [31:0] _zz_236; + wire _zz_237; + wire _zz_238; + wire _zz_239; + wire _zz_240; + wire _zz_241; + wire _zz_242; + wire _zz_243; + wire _zz_244; + wire [3:0] _zz_245; + wire _zz_246; + wire _zz_247; + reg [31:0] _zz_248; + reg [31:0] _zz_249; + reg [31:0] _zz_250; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire dataCache_1_io_mem_cmd_payload_last; + wire _zz_251; + wire _zz_252; + wire _zz_253; + wire _zz_254; + wire _zz_255; + wire _zz_256; + wire _zz_257; + wire _zz_258; + wire _zz_259; + wire _zz_260; + wire _zz_261; + wire _zz_262; + wire _zz_263; + wire _zz_264; + wire _zz_265; + wire _zz_266; + wire _zz_267; + wire _zz_268; + wire [1:0] _zz_269; + wire _zz_270; + wire _zz_271; + wire _zz_272; + wire _zz_273; + wire _zz_274; + wire _zz_275; + wire _zz_276; + wire _zz_277; + wire _zz_278; + wire _zz_279; + wire [1:0] _zz_280; + wire _zz_281; + wire _zz_282; + wire [5:0] _zz_283; + wire _zz_284; + wire _zz_285; + wire _zz_286; + wire _zz_287; + wire _zz_288; + wire _zz_289; + wire _zz_290; + wire [1:0] _zz_291; + wire _zz_292; + wire [1:0] _zz_293; + wire [51:0] _zz_294; + wire [51:0] _zz_295; + wire [51:0] _zz_296; + wire [32:0] _zz_297; + wire [51:0] _zz_298; + wire [49:0] _zz_299; + wire [51:0] _zz_300; + wire [49:0] _zz_301; + wire [51:0] _zz_302; + wire [32:0] _zz_303; + wire [31:0] _zz_304; + wire [32:0] _zz_305; + wire [0:0] _zz_306; + wire [0:0] _zz_307; + wire [0:0] _zz_308; + wire [0:0] _zz_309; + wire [0:0] _zz_310; + wire [0:0] _zz_311; + wire [0:0] _zz_312; + wire [0:0] _zz_313; + wire [0:0] _zz_314; + wire [0:0] _zz_315; + wire [0:0] _zz_316; + wire [0:0] _zz_317; + wire [0:0] _zz_318; + wire [0:0] _zz_319; + wire [0:0] _zz_320; + wire [0:0] _zz_321; + wire [0:0] _zz_322; + wire [0:0] _zz_323; + wire [0:0] _zz_324; + wire [3:0] _zz_325; + wire [2:0] _zz_326; + wire [31:0] _zz_327; + wire [11:0] _zz_328; + wire [31:0] _zz_329; + wire [19:0] _zz_330; + wire [11:0] _zz_331; + wire [31:0] _zz_332; + wire [31:0] _zz_333; + wire [19:0] _zz_334; + wire [11:0] _zz_335; + wire [2:0] _zz_336; + wire [2:0] _zz_337; + wire [0:0] _zz_338; + wire [2:0] _zz_339; + wire [4:0] _zz_340; + wire [11:0] _zz_341; + wire [11:0] _zz_342; + wire [31:0] _zz_343; + wire [31:0] _zz_344; + wire [31:0] _zz_345; + wire [31:0] _zz_346; + wire [31:0] _zz_347; + wire [31:0] _zz_348; + wire [31:0] _zz_349; + wire [11:0] _zz_350; + wire [19:0] _zz_351; + wire [11:0] _zz_352; + wire [31:0] _zz_353; + wire [31:0] _zz_354; + wire [31:0] _zz_355; + wire [11:0] _zz_356; + wire [19:0] _zz_357; + wire [11:0] _zz_358; + wire [2:0] _zz_359; + wire [1:0] _zz_360; + wire [1:0] _zz_361; + wire [1:0] _zz_362; + wire [1:0] _zz_363; + wire [9:0] _zz_364; + wire [7:0] _zz_365; + wire [65:0] _zz_366; + wire [65:0] _zz_367; + wire [31:0] _zz_368; + wire [31:0] _zz_369; + wire [0:0] _zz_370; + wire [5:0] _zz_371; + wire [32:0] _zz_372; + wire [31:0] _zz_373; + wire [31:0] _zz_374; + wire [32:0] _zz_375; + wire [32:0] _zz_376; + wire [32:0] _zz_377; + wire [32:0] _zz_378; + wire [0:0] _zz_379; + wire [32:0] _zz_380; + wire [0:0] _zz_381; + wire [32:0] _zz_382; + wire [0:0] _zz_383; + wire [31:0] _zz_384; + wire [0:0] _zz_385; + wire [0:0] _zz_386; + wire [0:0] _zz_387; + wire [0:0] _zz_388; + wire [0:0] _zz_389; + wire [0:0] _zz_390; + wire [0:0] _zz_391; + wire [26:0] _zz_392; + wire _zz_393; + wire _zz_394; + wire [1:0] _zz_395; + wire [31:0] _zz_396; + wire [31:0] _zz_397; + wire [31:0] _zz_398; + wire _zz_399; + wire [0:0] _zz_400; + wire [14:0] _zz_401; + wire [31:0] _zz_402; + wire [31:0] _zz_403; + wire [31:0] _zz_404; + wire _zz_405; + wire [0:0] _zz_406; + wire [8:0] _zz_407; + wire [31:0] _zz_408; + wire [31:0] _zz_409; + wire [31:0] _zz_410; + wire _zz_411; + wire [0:0] _zz_412; + wire [2:0] _zz_413; + wire _zz_414; + wire _zz_415; + wire _zz_416; + wire [31:0] _zz_417; + wire [0:0] _zz_418; + wire [0:0] _zz_419; + wire _zz_420; + wire [0:0] _zz_421; + wire [28:0] _zz_422; + wire [0:0] _zz_423; + wire [0:0] _zz_424; + wire [0:0] _zz_425; + wire [0:0] _zz_426; + wire _zz_427; + wire [0:0] _zz_428; + wire [23:0] _zz_429; + wire [31:0] _zz_430; + wire [31:0] _zz_431; + wire [31:0] _zz_432; + wire _zz_433; + wire _zz_434; + wire [0:0] _zz_435; + wire [0:0] _zz_436; + wire [0:0] _zz_437; + wire [0:0] _zz_438; + wire _zz_439; + wire [0:0] _zz_440; + wire [20:0] _zz_441; + wire [31:0] _zz_442; + wire [31:0] _zz_443; + wire _zz_444; + wire _zz_445; + wire [0:0] _zz_446; + wire [1:0] _zz_447; + wire [0:0] _zz_448; + wire [0:0] _zz_449; + wire _zz_450; + wire [0:0] _zz_451; + wire [17:0] _zz_452; + wire [31:0] _zz_453; + wire [31:0] _zz_454; + wire [31:0] _zz_455; + wire [31:0] _zz_456; + wire [31:0] _zz_457; + wire [31:0] _zz_458; + wire [31:0] _zz_459; + wire [31:0] _zz_460; + wire _zz_461; + wire [1:0] _zz_462; + wire [1:0] _zz_463; + wire _zz_464; + wire [0:0] _zz_465; + wire [14:0] _zz_466; + wire [31:0] _zz_467; + wire [31:0] _zz_468; + wire [31:0] _zz_469; + wire [31:0] _zz_470; + wire [31:0] _zz_471; + wire [31:0] _zz_472; + wire [0:0] _zz_473; + wire [1:0] _zz_474; + wire [4:0] _zz_475; + wire [4:0] _zz_476; + wire _zz_477; + wire [0:0] _zz_478; + wire [11:0] _zz_479; + wire [31:0] _zz_480; + wire [31:0] _zz_481; + wire [31:0] _zz_482; + wire [31:0] _zz_483; + wire [31:0] _zz_484; + wire [31:0] _zz_485; + wire _zz_486; + wire [0:0] _zz_487; + wire [1:0] _zz_488; + wire [31:0] _zz_489; + wire [31:0] _zz_490; + wire [0:0] _zz_491; + wire [4:0] _zz_492; + wire [4:0] _zz_493; + wire [4:0] _zz_494; + wire _zz_495; + wire [0:0] _zz_496; + wire [8:0] _zz_497; + wire [31:0] _zz_498; + wire [31:0] _zz_499; + wire [31:0] _zz_500; + wire _zz_501; + wire _zz_502; + wire [31:0] _zz_503; + wire [31:0] _zz_504; + wire _zz_505; + wire [0:0] _zz_506; + wire [2:0] _zz_507; + wire [0:0] _zz_508; + wire [2:0] _zz_509; + wire [0:0] _zz_510; + wire [4:0] _zz_511; + wire [1:0] _zz_512; + wire [1:0] _zz_513; + wire _zz_514; + wire [0:0] _zz_515; + wire [6:0] _zz_516; + wire [31:0] _zz_517; + wire [31:0] _zz_518; + wire [31:0] _zz_519; + wire _zz_520; + wire [0:0] _zz_521; + wire [0:0] _zz_522; + wire [31:0] _zz_523; + wire [31:0] _zz_524; + wire _zz_525; + wire [0:0] _zz_526; + wire [0:0] _zz_527; + wire _zz_528; + wire [0:0] _zz_529; + wire [2:0] _zz_530; + wire _zz_531; + wire [0:0] _zz_532; + wire [0:0] _zz_533; + wire [0:0] _zz_534; + wire [0:0] _zz_535; + wire _zz_536; + wire [0:0] _zz_537; + wire [4:0] _zz_538; + wire [31:0] _zz_539; + wire [31:0] _zz_540; + wire [31:0] _zz_541; + wire [31:0] _zz_542; + wire [31:0] _zz_543; + wire [31:0] _zz_544; + wire [31:0] _zz_545; + wire [31:0] _zz_546; + wire [31:0] _zz_547; + wire [31:0] _zz_548; + wire [31:0] _zz_549; + wire [31:0] _zz_550; + wire [31:0] _zz_551; + wire _zz_552; + wire [0:0] _zz_553; + wire [0:0] _zz_554; + wire [31:0] _zz_555; + wire [31:0] _zz_556; + wire [31:0] _zz_557; + wire [31:0] _zz_558; + wire [31:0] _zz_559; + wire _zz_560; + wire [3:0] _zz_561; + wire [3:0] _zz_562; + wire _zz_563; + wire [0:0] _zz_564; + wire [2:0] _zz_565; + wire [31:0] _zz_566; + wire [31:0] _zz_567; + wire [31:0] _zz_568; + wire [31:0] _zz_569; + wire [31:0] _zz_570; + wire [31:0] _zz_571; + wire _zz_572; + wire [0:0] _zz_573; + wire [1:0] _zz_574; + wire _zz_575; + wire [2:0] _zz_576; + wire [2:0] _zz_577; + wire _zz_578; + wire [0:0] _zz_579; + wire [0:0] _zz_580; + wire [31:0] _zz_581; + wire [31:0] _zz_582; + wire [31:0] _zz_583; + wire [31:0] _zz_584; + wire [31:0] _zz_585; + wire [31:0] _zz_586; + wire [31:0] _zz_587; + wire _zz_588; + wire _zz_589; + wire _zz_590; + wire [0:0] _zz_591; + wire [0:0] _zz_592; + wire _zz_593; + wire _zz_594; + wire _zz_595; + wire _zz_596; + wire [31:0] _zz_597; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DO_EBREAK; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_1; + wire `Input2Kind_defaultEncoding_type _zz_2; + wire `Input2Kind_defaultEncoding_type _zz_3; + wire decode_CfuPlugin_CFU_ENABLE; + wire `EnvCtrlEnum_defaultEncoding_type _zz_4; + wire `EnvCtrlEnum_defaultEncoding_type _zz_5; + wire `EnvCtrlEnum_defaultEncoding_type _zz_6; + wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_8; + wire `EnvCtrlEnum_defaultEncoding_type _zz_9; + wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire decode_IS_CSR; + wire `BranchCtrlEnum_defaultEncoding_type _zz_11; + wire `BranchCtrlEnum_defaultEncoding_type _zz_12; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_21; + wire `Src2CtrlEnum_defaultEncoding_type _zz_22; + wire `Src2CtrlEnum_defaultEncoding_type _zz_23; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_defaultEncoding_type _zz_25; + wire `AluCtrlEnum_defaultEncoding_type _zz_26; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src1CtrlEnum_defaultEncoding_type _zz_28; + wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_DO_EBREAK; + wire decode_IS_EBREAK; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + reg _zz_30; + reg _zz_31; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_defaultEncoding_type _zz_32; + wire execute_CfuPlugin_CFU_ENABLE; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_33; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_34; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_37; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_38; + wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_41; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_42; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; + wire [31:0] _zz_46; + wire _zz_47; + reg _zz_48; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `Input2Kind_defaultEncoding_type _zz_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; + wire `Src2CtrlEnum_defaultEncoding_type _zz_54; + wire `AluCtrlEnum_defaultEncoding_type _zz_55; + wire `Src1CtrlEnum_defaultEncoding_type _zz_56; + reg [31:0] _zz_57; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_59; + reg [31:0] _zz_60; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + reg decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + reg execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg _zz_61; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_inWfi /* verilator public */ ; + reg CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + reg CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + reg CsrPlugin_allowInterrupts; + reg CsrPlugin_allowException; + reg CfuPlugin_joinException_valid; + wire [3:0] CfuPlugin_joinException_payload_code; + wire [31:0] CfuPlugin_joinException_payload_badAddr; + reg IBusCachedPlugin_injectionPort_valid; + reg IBusCachedPlugin_injectionPort_ready; + wire [31:0] IBusCachedPlugin_injectionPort_payload; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_62; + wire [3:0] _zz_63; + wire _zz_64; + wire _zz_65; + wire _zz_66; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_67; + wire _zz_68; + wire _zz_69; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_70; + wire _zz_71; + reg _zz_72; + wire _zz_73; + reg _zz_74; + reg [31:0] _zz_75; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire _zz_76; + reg [18:0] _zz_77; + wire _zz_78; + reg [10:0] _zz_79; + wire _zz_80; + reg [18:0] _zz_81; + reg _zz_82; + wire _zz_83; + reg [10:0] _zz_84; + wire _zz_85; + reg [18:0] _zz_86; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_87; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + wire [31:0] _zz_88; + reg [31:0] DBusCachedPlugin_rspCounter; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_89; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire _zz_90; + reg [31:0] _zz_91; + wire _zz_92; + reg [31:0] _zz_93; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire [34:0] _zz_94; + wire _zz_95; + wire _zz_96; + wire _zz_97; + wire _zz_98; + wire _zz_99; + wire `Src1CtrlEnum_defaultEncoding_type _zz_100; + wire `AluCtrlEnum_defaultEncoding_type _zz_101; + wire `Src2CtrlEnum_defaultEncoding_type _zz_102; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; + wire `BranchCtrlEnum_defaultEncoding_type _zz_105; + wire `EnvCtrlEnum_defaultEncoding_type _zz_106; + wire `Input2Kind_defaultEncoding_type _zz_107; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_108; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_109; + reg [31:0] _zz_110; + wire _zz_111; + reg [19:0] _zz_112; + wire _zz_113; + reg [19:0] _zz_114; + reg [31:0] _zz_115; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_116; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_117; + reg _zz_118; + reg _zz_119; + reg _zz_120; + reg [4:0] _zz_121; + reg [31:0] _zz_122; + wire _zz_123; + wire _zz_124; + wire _zz_125; + wire _zz_126; + wire _zz_127; + wire _zz_128; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_129; + reg _zz_130; + reg _zz_131; + wire _zz_132; + reg [19:0] _zz_133; + wire _zz_134; + reg [10:0] _zz_135; + wire _zz_136; + reg [18:0] _zz_137; + reg _zz_138; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_139; + reg [19:0] _zz_140; + wire _zz_141; + reg [10:0] _zz_142; + wire _zz_143; + reg [18:0] _zz_144; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_145; + wire _zz_146; + wire _zz_147; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_148; + wire _zz_149; + wire [1:0] _zz_150; + wire _zz_151; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + reg execute_CsrPlugin_wfiWake; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire [31:0] execute_CsrPlugin_readData; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_152; + reg [31:0] _zz_153; + reg [31:0] _zz_154; + reg [31:0] _zz_155; + reg [31:0] _zz_156; + reg [31:0] _zz_157; + reg [31:0] _zz_158; + reg [31:0] _zz_159; + reg [31:0] _zz_160; + reg [31:0] _zz_161; + reg [31:0] _zz_162; + reg [31:0] _zz_163; + reg [31:0] _zz_164; + reg [31:0] _zz_165; + reg [31:0] _zz_166; + reg [31:0] _zz_167; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_168; + reg [23:0] _zz_169; + reg [31:0] _zz_170; + wire memory_CfuPlugin_rsp_valid; + reg memory_CfuPlugin_rsp_ready; + wire memory_CfuPlugin_rsp_payload_response_ok; + wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_s2mPipe_rValid; + reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; + reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + reg [31:0] memory_DivPlugin_div_result; + wire [31:0] _zz_171; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire [31:0] _zz_172; + wire _zz_173; + wire _zz_174; + reg [32:0] _zz_175; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_176; + wire [31:0] _zz_177; + reg DebugPlugin_firstCycle; + reg DebugPlugin_secondCycle; + reg DebugPlugin_resetIt; + reg DebugPlugin_haltIt; + reg DebugPlugin_stepIt; + reg DebugPlugin_isPipBusy; + reg DebugPlugin_godmode; + reg DebugPlugin_haltedByBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_178; + wire DebugPlugin_allowEBreak; + reg DebugPlugin_resetIt_regNext; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_MEMORY_ENABLE; + reg execute_to_memory_MEMORY_ENABLE; + reg memory_to_writeBack_MEMORY_ENABLE; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg execute_to_memory_REGFILE_WRITE_VALID; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + reg decode_to_execute_MEMORY_WR; + reg execute_to_memory_MEMORY_WR; + reg memory_to_writeBack_MEMORY_WR; + reg decode_to_execute_MEMORY_MANAGMENT; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_IS_CSR; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + reg decode_to_execute_IS_MUL; + reg execute_to_memory_IS_MUL; + reg memory_to_writeBack_IS_MUL; + reg decode_to_execute_IS_DIV; + reg execute_to_memory_IS_DIV; + reg decode_to_execute_IS_RS1_SIGNED; + reg decode_to_execute_IS_RS2_SIGNED; + reg [31:0] decode_to_execute_RS1; + reg [31:0] decode_to_execute_RS2; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg decode_to_execute_CSR_READ_OPCODE; + reg decode_to_execute_DO_EBREAK; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg [31:0] execute_to_memory_MUL_LL; + reg [33:0] execute_to_memory_MUL_LH; + reg [33:0] execute_to_memory_MUL_HL; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg [2:0] _zz_179; + reg execute_CsrPlugin_csr_3264; + reg execute_CsrPlugin_csr_3857; + reg execute_CsrPlugin_csr_3858; + reg execute_CsrPlugin_csr_3859; + reg execute_CsrPlugin_csr_3860; + reg execute_CsrPlugin_csr_769; + reg execute_CsrPlugin_csr_768; + reg execute_CsrPlugin_csr_836; + reg execute_CsrPlugin_csr_772; + reg execute_CsrPlugin_csr_773; + reg execute_CsrPlugin_csr_833; + reg execute_CsrPlugin_csr_832; + reg execute_CsrPlugin_csr_834; + reg execute_CsrPlugin_csr_835; + reg execute_CsrPlugin_csr_2816; + reg execute_CsrPlugin_csr_2944; + reg execute_CsrPlugin_csr_2818; + reg execute_CsrPlugin_csr_2946; + reg execute_CsrPlugin_csr_3072; + reg execute_CsrPlugin_csr_3200; + reg execute_CsrPlugin_csr_3074; + reg execute_CsrPlugin_csr_3202; + reg execute_CsrPlugin_csr_2820; + reg execute_CsrPlugin_csr_2821; + reg execute_CsrPlugin_csr_2822; + reg execute_CsrPlugin_csr_2823; + reg execute_CsrPlugin_csr_2824; + reg execute_CsrPlugin_csr_2825; + reg execute_CsrPlugin_csr_2826; + reg execute_CsrPlugin_csr_2827; + reg execute_CsrPlugin_csr_2828; + reg execute_CsrPlugin_csr_2829; + reg execute_CsrPlugin_csr_2830; + reg execute_CsrPlugin_csr_2831; + reg execute_CsrPlugin_csr_2832; + reg execute_CsrPlugin_csr_2833; + reg execute_CsrPlugin_csr_2834; + reg execute_CsrPlugin_csr_2835; + reg execute_CsrPlugin_csr_3008; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_180; + reg [31:0] _zz_181; + reg [31:0] _zz_182; + reg [31:0] _zz_183; + reg [31:0] _zz_184; + reg [31:0] _zz_185; + reg [31:0] _zz_186; + reg [31:0] _zz_187; + reg [31:0] _zz_188; + reg [31:0] _zz_189; + reg [31:0] _zz_190; + reg [31:0] _zz_191; + reg [31:0] _zz_192; + reg [31:0] _zz_193; + reg [31:0] _zz_194; + reg [31:0] _zz_195; + reg [31:0] _zz_196; + reg [31:0] _zz_197; + reg [31:0] _zz_198; + reg [31:0] _zz_199; + reg [31:0] _zz_200; + reg [31:0] _zz_201; + reg [31:0] _zz_202; + reg [31:0] _zz_203; + reg [31:0] _zz_204; + reg [31:0] _zz_205; + reg [31:0] _zz_206; + reg [31:0] _zz_207; + reg [31:0] _zz_208; + reg [31:0] _zz_209; + reg [31:0] _zz_210; + reg [2:0] _zz_211; + reg _zz_212; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_213; + wire _zz_214; + wire _zz_215; + wire _zz_216; + wire _zz_217; + wire _zz_218; + reg _zz_219; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_1_string; + reg [39:0] _zz_2_string; + reg [39:0] _zz_3_string; + reg [39:0] _zz_4_string; + reg [39:0] _zz_5_string; + reg [39:0] _zz_6_string; + reg [39:0] _zz_7_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_8_string; + reg [39:0] _zz_9_string; + reg [39:0] _zz_10_string; + reg [31:0] _zz_11_string; + reg [31:0] _zz_12_string; + reg [71:0] _zz_13_string; + reg [71:0] _zz_14_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_15_string; + reg [71:0] _zz_16_string; + reg [71:0] _zz_17_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_18_string; + reg [39:0] _zz_19_string; + reg [39:0] _zz_20_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_21_string; + reg [23:0] _zz_22_string; + reg [23:0] _zz_23_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_24_string; + reg [63:0] _zz_25_string; + reg [63:0] _zz_26_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_27_string; + reg [95:0] _zz_28_string; + reg [95:0] _zz_29_string; + reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_32_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_33_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_34_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_35_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_36_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_39_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_40_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_42_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_43_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_44_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_45_string; + reg [39:0] _zz_49_string; + reg [39:0] _zz_50_string; + reg [31:0] _zz_51_string; + reg [71:0] _zz_52_string; + reg [39:0] _zz_53_string; + reg [23:0] _zz_54_string; + reg [63:0] _zz_55_string; + reg [95:0] _zz_56_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_58_string; + reg [95:0] _zz_100_string; + reg [63:0] _zz_101_string; + reg [23:0] _zz_102_string; + reg [39:0] _zz_103_string; + reg [71:0] _zz_104_string; + reg [31:0] _zz_105_string; + reg [39:0] _zz_106_string; + reg [39:0] _zz_107_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + reg [39:0] decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_251 = (execute_arbitration_isValid && execute_IS_CSR); + assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_253 = 1'b1; + assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_256 = (memory_arbitration_isValid && memory_IS_DIV); + assign _zz_257 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign _zz_258 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign _zz_259 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign _zz_260 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_261 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_262 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + assign _zz_263 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign _zz_264 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_265 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_268 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); + assign _zz_269 = writeBack_INSTRUCTION[29 : 28]; + assign _zz_270 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_271 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign _zz_272 = (1'b0 || (! 1'b1)); + assign _zz_273 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign _zz_274 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign _zz_275 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign _zz_276 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign _zz_277 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign _zz_278 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); + assign _zz_280 = execute_INSTRUCTION[13 : 12]; + assign _zz_281 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_282 = (! memory_arbitration_isStuck); + assign _zz_283 = debug_bus_cmd_payload_address[7 : 2]; + assign _zz_284 = (iBus_cmd_valid || (_zz_211 != 3'b000)); + assign _zz_285 = (_zz_247 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); + assign _zz_286 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign _zz_287 = ((_zz_145 && 1'b1) && (! 1'b0)); + assign _zz_288 = ((_zz_146 && 1'b1) && (! 1'b0)); + assign _zz_289 = ((_zz_147 && 1'b1) && (! 1'b0)); + assign _zz_290 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); + assign _zz_291 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_292 = execute_INSTRUCTION[13]; + assign _zz_293 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_294 = ($signed(_zz_295) + $signed(_zz_300)); + assign _zz_295 = ($signed(_zz_296) + $signed(_zz_298)); + assign _zz_296 = 52'h0; + assign _zz_297 = {1'b0,memory_MUL_LL}; + assign _zz_298 = {{19{_zz_297[32]}}, _zz_297}; + assign _zz_299 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; + assign _zz_301 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_302 = {{2{_zz_301[49]}}, _zz_301}; + assign _zz_303 = ($signed(_zz_305) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_304 = _zz_303[31 : 0]; + assign _zz_305 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_306 = _zz_94[33 : 33]; + assign _zz_307 = _zz_94[32 : 32]; + assign _zz_308 = _zz_94[31 : 31]; + assign _zz_309 = _zz_94[30 : 30]; + assign _zz_310 = _zz_94[28 : 28]; + assign _zz_311 = _zz_94[25 : 25]; + assign _zz_312 = _zz_94[17 : 17]; + assign _zz_313 = _zz_94[16 : 16]; + assign _zz_314 = _zz_94[13 : 13]; + assign _zz_315 = _zz_94[12 : 12]; + assign _zz_316 = _zz_94[11 : 11]; + assign _zz_317 = _zz_94[34 : 34]; + assign _zz_318 = _zz_94[15 : 15]; + assign _zz_319 = _zz_94[5 : 5]; + assign _zz_320 = _zz_94[3 : 3]; + assign _zz_321 = _zz_94[20 : 20]; + assign _zz_322 = _zz_94[10 : 10]; + assign _zz_323 = _zz_94[4 : 4]; + assign _zz_324 = _zz_94[0 : 0]; + assign _zz_325 = (_zz_62 - 4'b0001); + assign _zz_326 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_327 = {29'd0, _zz_326}; + assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_329 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_331 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_332 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_333 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_334 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz_335 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_338 = execute_SRC_LESS; + assign _zz_339 = 3'b100; + assign _zz_340 = execute_INSTRUCTION[19 : 15]; + assign _zz_341 = execute_INSTRUCTION[31 : 20]; + assign _zz_342 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_343 = ($signed(_zz_344) + $signed(_zz_347)); + assign _zz_344 = ($signed(_zz_345) + $signed(_zz_346)); + assign _zz_345 = execute_SRC1; + assign _zz_346 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_347 = (execute_SRC_USE_SUB_LESS ? _zz_348 : _zz_349); + assign _zz_348 = 32'h00000001; + assign _zz_349 = 32'h0; + assign _zz_350 = execute_INSTRUCTION[31 : 20]; + assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_353 = {_zz_133,execute_INSTRUCTION[31 : 20]}; + assign _zz_354 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz_355 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz_356 = execute_INSTRUCTION[31 : 20]; + assign _zz_357 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_359 = 3'b100; + assign _zz_360 = (_zz_148 & (~ _zz_361)); + assign _zz_361 = (_zz_148 - 2'b01); + assign _zz_362 = (_zz_150 & (~ _zz_363)); + assign _zz_363 = (_zz_150 - 2'b01); + assign _zz_364 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_365 = execute_INSTRUCTION[31 : 24]; + assign _zz_366 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_367 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_368 = writeBack_MUL_LOW[31 : 0]; + assign _zz_369 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_370 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_371 = {5'd0, _zz_370}; + assign _zz_372 = {1'd0, memory_DivPlugin_rs2}; + assign _zz_373 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_374 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_375 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_376 = _zz_377; + assign _zz_377 = _zz_378; + assign _zz_378 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_380); + assign _zz_379 = memory_DivPlugin_div_needRevert; + assign _zz_380 = {32'd0, _zz_379}; + assign _zz_381 = _zz_174; + assign _zz_382 = {32'd0, _zz_381}; + assign _zz_383 = _zz_173; + assign _zz_384 = {31'd0, _zz_383}; + assign _zz_385 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_386 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_387 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_388 = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_391 = execute_CsrPlugin_writeData[31 : 31]; + assign _zz_392 = (iBus_cmd_payload_address >>> 5); + assign _zz_393 = 1'b1; + assign _zz_394 = 1'b1; + assign _zz_395 = {_zz_66,_zz_65}; + assign _zz_396 = 32'h0000106f; + assign _zz_397 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_398 = 32'h00001073; + assign _zz_399 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_400 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_401 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_402) == 32'h00000003),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; + assign _zz_402 = 32'h0000207f; + assign _zz_403 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_404 = 32'h00000003; + assign _zz_405 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_406 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_407 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_408) == 32'h00005013),{(_zz_409 == _zz_410),{_zz_411,{_zz_412,_zz_413}}}}}}; + assign _zz_408 = 32'hbc00707f; + assign _zz_409 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_410 = 32'h00001013; + assign _zz_411 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_412 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_413 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_414 = decode_INSTRUCTION[31]; + assign _zz_415 = decode_INSTRUCTION[31]; + assign _zz_416 = decode_INSTRUCTION[7]; + assign _zz_417 = 32'h10103050; + assign _zz_418 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz_419 = 1'b0; + assign _zz_420 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); + assign _zz_421 = 1'b0; + assign _zz_422 = {(_zz_98 != 1'b0),{({_zz_423,_zz_424} != 2'b00),{(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}}}; + assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h10000050); + assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00000050); + assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00000050); + assign _zz_426 = 1'b0; + assign _zz_427 = ({_zz_433,_zz_434} != 2'b00); + assign _zz_428 = ({_zz_435,_zz_436} != 2'b00); + assign _zz_429 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; + assign _zz_430 = 32'h10203050; + assign _zz_431 = 32'h10103050; + assign _zz_432 = 32'h00103050; + assign _zz_433 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz_434 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz_435 = _zz_97; + assign _zz_436 = ((decode_INSTRUCTION & _zz_442) == 32'h00000004); + assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000040); + assign _zz_438 = 1'b0; + assign _zz_439 = ({_zz_444,_zz_445} != 2'b00); + assign _zz_440 = ({_zz_446,_zz_447} != 3'b000); + assign _zz_441 = {(_zz_448 != _zz_449),{_zz_450,{_zz_451,_zz_452}}}; + assign _zz_442 = 32'h0000001c; + assign _zz_443 = 32'h00000058; + assign _zz_444 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz_445 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h40001010); + assign _zz_447 = {(_zz_454 == _zz_455),(_zz_456 == _zz_457)}; + assign _zz_448 = ((decode_INSTRUCTION & _zz_458) == 32'h00000024); + assign _zz_449 = 1'b0; + assign _zz_450 = ((_zz_459 == _zz_460) != 1'b0); + assign _zz_451 = (_zz_461 != 1'b0); + assign _zz_452 = {(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}; + assign _zz_453 = 32'h40003054; + assign _zz_454 = (decode_INSTRUCTION & 32'h00007034); + assign _zz_455 = 32'h00001010; + assign _zz_456 = (decode_INSTRUCTION & 32'h02007054); + assign _zz_457 = 32'h00001010; + assign _zz_458 = 32'h00000064; + assign _zz_459 = (decode_INSTRUCTION & 32'h00001000); + assign _zz_460 = 32'h00001000; + assign _zz_461 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_462 = {(_zz_467 == _zz_468),(_zz_469 == _zz_470)}; + assign _zz_463 = 2'b00; + assign _zz_464 = ((_zz_471 == _zz_472) != 1'b0); + assign _zz_465 = ({_zz_473,_zz_474} != 3'b000); + assign _zz_466 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; + assign _zz_467 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_468 = 32'h00002000; + assign _zz_469 = (decode_INSTRUCTION & 32'h00005000); + assign _zz_470 = 32'h00001000; + assign _zz_471 = (decode_INSTRUCTION & 32'h00004054); + assign _zz_472 = 32'h00004004; + assign _zz_473 = _zz_98; + assign _zz_474 = {(_zz_480 == _zz_481),(_zz_482 == _zz_483)}; + assign _zz_475 = {(_zz_484 == _zz_485),{_zz_486,{_zz_487,_zz_488}}}; + assign _zz_476 = 5'h0; + assign _zz_477 = ((_zz_489 == _zz_490) != 1'b0); + assign _zz_478 = ({_zz_491,_zz_492} != 6'h0); + assign _zz_479 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; + assign _zz_480 = (decode_INSTRUCTION & 32'h00000034); + assign _zz_481 = 32'h00000020; + assign _zz_482 = (decode_INSTRUCTION & 32'h00000064); + assign _zz_483 = 32'h00000020; + assign _zz_484 = (decode_INSTRUCTION & 32'h00002040); + assign _zz_485 = 32'h00002040; + assign _zz_486 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); + assign _zz_487 = (_zz_499 == _zz_500); + assign _zz_488 = {_zz_501,_zz_502}; + assign _zz_489 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_490 = 32'h00000020; + assign _zz_491 = (_zz_503 == _zz_504); + assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; + assign _zz_493 = {_zz_96,{_zz_508,_zz_509}}; + assign _zz_494 = 5'h0; + assign _zz_495 = ({_zz_510,_zz_511} != 6'h0); + assign _zz_496 = (_zz_512 != _zz_513); + assign _zz_497 = {_zz_514,{_zz_515,_zz_516}}; + assign _zz_498 = 32'h00001040; + assign _zz_499 = (decode_INSTRUCTION & 32'h00100040); + assign _zz_500 = 32'h00000040; + assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00000040); + assign _zz_502 = ((decode_INSTRUCTION & _zz_518) == 32'h0); + assign _zz_503 = (decode_INSTRUCTION & 32'h00000008); + assign _zz_504 = 32'h00000008; + assign _zz_505 = ((decode_INSTRUCTION & _zz_519) == 32'h00000040); + assign _zz_506 = _zz_96; + assign _zz_507 = {_zz_520,{_zz_521,_zz_522}}; + assign _zz_508 = (_zz_523 == _zz_524); + assign _zz_509 = {_zz_525,{_zz_526,_zz_527}}; + assign _zz_510 = _zz_97; + assign _zz_511 = {_zz_528,{_zz_529,_zz_530}}; + assign _zz_512 = {_zz_96,_zz_531}; + assign _zz_513 = 2'b00; + assign _zz_514 = ({_zz_532,_zz_533} != 2'b00); + assign _zz_515 = (_zz_534 != _zz_535); + assign _zz_516 = {_zz_536,{_zz_537,_zz_538}}; + assign _zz_517 = 32'h00000050; + assign _zz_518 = 32'h00000038; + assign _zz_519 = 32'h00000040; + assign _zz_520 = ((decode_INSTRUCTION & _zz_539) == 32'h00004020); + assign _zz_521 = (_zz_540 == _zz_541); + assign _zz_522 = (_zz_542 == _zz_543); + assign _zz_523 = (decode_INSTRUCTION & 32'h00002030); + assign _zz_524 = 32'h00002010; + assign _zz_525 = ((decode_INSTRUCTION & _zz_544) == 32'h00000010); + assign _zz_526 = (_zz_545 == _zz_546); + assign _zz_527 = (_zz_547 == _zz_548); + assign _zz_528 = ((decode_INSTRUCTION & _zz_549) == 32'h00001010); + assign _zz_529 = (_zz_550 == _zz_551); + assign _zz_530 = {_zz_552,{_zz_553,_zz_554}}; + assign _zz_531 = ((decode_INSTRUCTION & _zz_555) == 32'h00000020); + assign _zz_532 = _zz_96; + assign _zz_533 = (_zz_556 == _zz_557); + assign _zz_534 = (_zz_558 == _zz_559); + assign _zz_535 = 1'b0; + assign _zz_536 = (_zz_560 != 1'b0); + assign _zz_537 = (_zz_561 != _zz_562); + assign _zz_538 = {_zz_563,{_zz_564,_zz_565}}; + assign _zz_539 = 32'h00004020; + assign _zz_540 = (decode_INSTRUCTION & 32'h00000030); + assign _zz_541 = 32'h00000010; + assign _zz_542 = (decode_INSTRUCTION & 32'h02000020); + assign _zz_543 = 32'h00000020; + assign _zz_544 = 32'h00001030; + assign _zz_545 = (decode_INSTRUCTION & 32'h02002060); + assign _zz_546 = 32'h00002020; + assign _zz_547 = (decode_INSTRUCTION & 32'h02003020); + assign _zz_548 = 32'h00000020; + assign _zz_549 = 32'h00001010; + assign _zz_550 = (decode_INSTRUCTION & 32'h00002010); + assign _zz_551 = 32'h00002010; + assign _zz_552 = ((decode_INSTRUCTION & _zz_566) == 32'h00000010); + assign _zz_553 = (_zz_567 == _zz_568); + assign _zz_554 = (_zz_569 == _zz_570); + assign _zz_555 = 32'h00000070; + assign _zz_556 = (decode_INSTRUCTION & 32'h00000020); + assign _zz_557 = 32'h0; + assign _zz_558 = (decode_INSTRUCTION & 32'h00004014); + assign _zz_559 = 32'h00004010; + assign _zz_560 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); + assign _zz_561 = {_zz_572,{_zz_573,_zz_574}}; + assign _zz_562 = 4'b0000; + assign _zz_563 = (_zz_575 != 1'b0); + assign _zz_564 = (_zz_576 != _zz_577); + assign _zz_565 = {_zz_578,{_zz_579,_zz_580}}; + assign _zz_566 = 32'h00000050; + assign _zz_567 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz_568 = 32'h00000004; + assign _zz_569 = (decode_INSTRUCTION & 32'h00000024); + assign _zz_570 = 32'h0; + assign _zz_571 = 32'h00006014; + assign _zz_572 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz_573 = ((decode_INSTRUCTION & _zz_581) == 32'h0); + assign _zz_574 = {(_zz_582 == _zz_583),(_zz_584 == _zz_585)}; + assign _zz_575 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz_576 = {(_zz_586 == _zz_587),{_zz_588,_zz_589}}; + assign _zz_577 = 3'b000; + assign _zz_578 = ({_zz_590,_zz_95} != 2'b00); + assign _zz_579 = ({_zz_591,_zz_592} != 2'b00); + assign _zz_580 = (_zz_593 != 1'b0); + assign _zz_581 = 32'h00000018; + assign _zz_582 = (decode_INSTRUCTION & 32'h00006004); + assign _zz_583 = 32'h00002000; + assign _zz_584 = (decode_INSTRUCTION & 32'h00005004); + assign _zz_585 = 32'h00001000; + assign _zz_586 = (decode_INSTRUCTION & 32'h00000044); + assign _zz_587 = 32'h00000040; + assign _zz_588 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz_589 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz_590 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz_591 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz_592 = _zz_95; + assign _zz_593 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); + assign _zz_594 = execute_INSTRUCTION[31]; + assign _zz_595 = execute_INSTRUCTION[31]; + assign _zz_596 = execute_INSTRUCTION[7]; + assign _zz_597 = 32'h0; + always @ (posedge clk) begin + if(_zz_393) begin + _zz_248 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_394) begin + _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_48) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_220 ), //i + .io_cpu_prefetch_isValid (_zz_221 ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_222 ), //i + .io_cpu_fetch_isStuck (_zz_223 ), //i + .io_cpu_fetch_isRemoved (_zz_224 ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_decode_isValid (_zz_225 ), //i + .io_cpu_decode_isStuck (_zz_226 ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_227 ), //i + .io_cpu_fill_valid (_zz_228 ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_9 (_zz_179[2:0] ), //i + ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (_zz_229 ), //i + .io_cpu_execute_address (_zz_230[31:0] ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_89[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (_zz_231 ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_232[31:0] ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuRsp_isIoAccess (_zz_233 ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (_zz_234 ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_235 ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_236[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (_zz_237 ), //i + .io_cpu_writeBack_fence_SR (_zz_238 ), //i + .io_cpu_writeBack_fence_SO (_zz_239 ), //i + .io_cpu_writeBack_fence_SI (_zz_240 ), //i + .io_cpu_writeBack_fence_PW (_zz_241 ), //i + .io_cpu_writeBack_fence_PR (_zz_242 ), //i + .io_cpu_writeBack_fence_PO (_zz_243 ), //i + .io_cpu_writeBack_fence_PI (_zz_244 ), //i + .io_cpu_writeBack_fence_FM (_zz_245[3:0] ), //i + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_246 ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_247 ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_395) + 2'b00 : begin + _zz_250 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_250 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_250 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_250 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_1) + `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; + default : _zz_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_2) + `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; + default : _zz_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_3) + `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; + default : _zz_3_string = "?????"; + endcase + end + always @(*) begin + case(_zz_4) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; + default : _zz_4_string = "?????"; + endcase + end + always @(*) begin + case(_zz_5) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; + default : _zz_5_string = "?????"; + endcase + end + always @(*) begin + case(_zz_6) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; + default : _zz_6_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; + default : _zz_7_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_8) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; + default : _zz_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_9) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; + default : _zz_9_string = "?????"; + endcase + end + always @(*) begin + case(_zz_10) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; + default : _zz_10_string = "?????"; + endcase + end + always @(*) begin + case(_zz_11) + `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; + default : _zz_11_string = "????"; + endcase + end + always @(*) begin + case(_zz_12) + `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; + default : _zz_12_string = "????"; + endcase + end + always @(*) begin + case(_zz_13) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; + default : _zz_13_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_14) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; + default : _zz_14_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_15) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; + default : _zz_15_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; + default : _zz_16_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; + default : _zz_17_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_18) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; + default : _zz_18_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; + default : _zz_19_string = "?????"; + endcase + end + always @(*) begin + case(_zz_20) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; + default : _zz_20_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_21) + `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; + default : _zz_21_string = "???"; + endcase + end + always @(*) begin + case(_zz_22) + `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; + default : _zz_22_string = "???"; + endcase + end + always @(*) begin + case(_zz_23) + `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; + default : _zz_23_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_24) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; + default : _zz_24_string = "????????"; + endcase + end + always @(*) begin + case(_zz_25) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; + default : _zz_25_string = "????????"; + endcase + end + always @(*) begin + case(_zz_26) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; + default : _zz_26_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_27) + `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; + default : _zz_27_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_28) + `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; + default : _zz_28_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_29) + `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; + default : _zz_29_string = "????????????"; + endcase + end + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + always @(*) begin + case(_zz_32) + `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; + default : _zz_32_string = "?????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_33) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; + default : _zz_33_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_34) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; + default : _zz_34_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_35) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; + default : _zz_35_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_36) + `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; + default : _zz_36_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_39) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; + default : _zz_39_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_40) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; + default : _zz_40_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_42) + `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; + default : _zz_42_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_43) + `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; + default : _zz_43_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_44) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; + default : _zz_44_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_45) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; + default : _zz_45_string = "?????"; + endcase + end + always @(*) begin + case(_zz_49) + `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; + default : _zz_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_50) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; + default : _zz_50_string = "?????"; + endcase + end + always @(*) begin + case(_zz_51) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; + default : _zz_51_string = "????"; + endcase + end + always @(*) begin + case(_zz_52) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; + default : _zz_52_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_53) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; + default : _zz_53_string = "?????"; + endcase + end + always @(*) begin + case(_zz_54) + `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; + default : _zz_54_string = "???"; + endcase + end + always @(*) begin + case(_zz_55) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; + default : _zz_55_string = "????????"; + endcase + end + always @(*) begin + case(_zz_56) + `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; + default : _zz_56_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_58) + `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; + default : _zz_58_string = "????"; + endcase + end + always @(*) begin + case(_zz_100) + `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; + default : _zz_100_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_101) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; + default : _zz_101_string = "????????"; + endcase + end + always @(*) begin + case(_zz_102) + `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; + default : _zz_102_string = "???"; + endcase + end + always @(*) begin + case(_zz_103) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; + default : _zz_103_string = "?????"; + endcase + end + always @(*) begin + case(_zz_104) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; + default : _zz_104_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_105) + `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; + default : _zz_105_string = "????"; + endcase + end + always @(*) begin + case(_zz_106) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; + default : _zz_106_string = "?????"; + endcase + end + always @(*) begin + case(_zz_107) + `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; + default : _zz_107_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_294) + $signed(_zz_302)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); + assign execute_SHIFT_RIGHT = _zz_304; + assign execute_REGFILE_WRITE_DATA = _zz_109; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_230[1 : 0]; + assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_306[0]; + assign decode_IS_RS1_SIGNED = _zz_307[0]; + assign decode_IS_DIV = _zz_308[0]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_309[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; + assign _zz_2 = _zz_3; + assign decode_CfuPlugin_CFU_ENABLE = _zz_310[0]; + assign _zz_4 = _zz_5; + assign _zz_6 = _zz_7; + assign decode_ENV_CTRL = _zz_8; + assign _zz_9 = _zz_10; + assign decode_IS_CSR = _zz_311[0]; + assign _zz_11 = _zz_12; + assign _zz_13 = _zz_14; + assign decode_SHIFT_CTRL = _zz_15; + assign _zz_16 = _zz_17; + assign decode_ALU_BITWISE_CTRL = _zz_18; + assign _zz_19 = _zz_20; + assign decode_SRC_LESS_UNSIGNED = _zz_312[0]; + assign decode_MEMORY_MANAGMENT = _zz_313[0]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_314[0]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_315[0]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_316[0]; + assign decode_SRC2_CTRL = _zz_21; + assign _zz_22 = _zz_23; + assign decode_ALU_CTRL = _zz_24; + assign _zz_25 = _zz_26; + assign decode_SRC1_CTRL = _zz_27; + assign _zz_28 = _zz_29; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; + assign decode_IS_EBREAK = _zz_317[0]; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + always @ (*) begin + _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck)begin + _zz_30 = 1'b0; + end + end + + always @ (*) begin + _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck)begin + _zz_31 = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_33; + assign execute_ENV_CTRL = _zz_34; + assign writeBack_ENV_CTRL = _zz_35; + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_131; + assign execute_BRANCH_CTRL = _zz_36; + assign decode_RS2_USE = _zz_318[0]; + assign decode_RS1_USE = _zz_319[0]; + always @ (*) begin + _zz_37 = execute_REGFILE_WRITE_DATA; + if(_zz_251)begin + _zz_37 = execute_CsrPlugin_readData; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin + decode_RS2 = _zz_122; + end + end + if(_zz_252)begin + if(_zz_253)begin + if(_zz_124)begin + decode_RS2 = _zz_57; + end + end + end + if(_zz_254)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_126)begin + decode_RS2 = _zz_38; + end + end + end + if(_zz_255)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_128)begin + decode_RS2 = _zz_37; + end + end + end + end + + always @ (*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(_zz_120)begin + if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin + decode_RS1 = _zz_122; + end + end + if(_zz_252)begin + if(_zz_253)begin + if(_zz_123)begin + decode_RS1 = _zz_57; + end + end + end + if(_zz_254)begin + if(memory_BYPASSABLE_MEMORY_STAGE)begin + if(_zz_125)begin + decode_RS1 = _zz_38; + end + end + end + if(_zz_255)begin + if(execute_BYPASSABLE_EXECUTE_STAGE)begin + if(_zz_127)begin + decode_RS1 = _zz_37; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @ (*) begin + _zz_38 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid)begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_38 = _zz_117; + end + `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin + _zz_38 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + end + if(_zz_256)begin + _zz_38 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_39; + assign execute_SHIFT_CTRL = _zz_40; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_41 = execute_PC; + assign execute_SRC2_CTRL = _zz_42; + assign execute_SRC1_CTRL = _zz_43; + assign decode_SRC_USE_SUB_LESS = _zz_320[0]; + assign decode_SRC_ADD_ZERO = _zz_321[0]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_44; + assign execute_SRC2 = _zz_115; + assign execute_SRC1 = _zz_110; + assign execute_ALU_BITWISE_CTRL = _zz_45; + assign _zz_46 = writeBack_INSTRUCTION; + assign _zz_47 = writeBack_REGFILE_WRITE_VALID; + always @ (*) begin + _zz_48 = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_48 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_322[0]; + if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}} != 22'h0); + always @ (*) begin + _zz_57 = writeBack_REGFILE_WRITE_DATA; + if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin + _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + end + if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin + case(_zz_293) + 2'b00 : begin + _zz_57 = _zz_368; + end + default : begin + _zz_57 = _zz_369; + end + endcase + end + end + + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_323[0]; + assign decode_FLUSH_ALL = _zz_324[0]; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(_zz_257)begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(_zz_258)begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(_zz_259)begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_260)begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_58; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @ (*) begin + _zz_59 = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_59 = BranchPlugin_jumpInterface_payload; + end + end + + always @ (*) begin + _zz_60 = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + case(_zz_179) + 3'b010 : begin + decode_arbitration_haltItself = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_261)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @ (*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid)begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_261)begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if(((_zz_246 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + execute_arbitration_haltItself = 1'b1; + end + if(_zz_262)begin + if((! execute_CsrPlugin_wfiWake))begin + execute_arbitration_haltItself = 1'b1; + end + end + if(_zz_251)begin + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + execute_arbitration_haltByOther = 1'b1; + end + if(_zz_263)begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(_zz_264)begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_flushIt = 1'b0; + if(_zz_263)begin + if(_zz_265)begin + execute_arbitration_flushIt = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_264)begin + execute_arbitration_flushNext = 1'b1; + end + if(_zz_263)begin + if(_zz_265)begin + execute_arbitration_flushNext = 1'b1; + end + end + end + + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if((! memory_CfuPlugin_rsp_valid))begin + memory_arbitration_haltItself = 1'b1; + end + end + if(_zz_256)begin + if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(CfuPlugin_joinException_valid)begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(CfuPlugin_joinException_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1_io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_266)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_267)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_266)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_267)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_263)begin + if(_zz_265)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + if(DebugPlugin_haltIt)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_268)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + _zz_61 = 1'b0; + if(DebugPlugin_godmode)begin + _zz_61 = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_inWfi = 1'b0; + if(_zz_262)begin + CsrPlugin_inWfi = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_thirdPartyWake = 1'b0; + if(DebugPlugin_haltIt)begin + CsrPlugin_thirdPartyWake = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(_zz_266)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_267)begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_jumpInterface_payload = 32'h0; + if(_zz_266)begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(_zz_267)begin + case(_zz_269) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + always @ (*) begin + CsrPlugin_forceMachineWire = 1'b0; + if(DebugPlugin_godmode)begin + CsrPlugin_forceMachineWire = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_allowInterrupts = 1'b1; + if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + CsrPlugin_allowInterrupts = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_allowException = 1'b1; + if(DebugPlugin_godmode)begin + CsrPlugin_allowException = 1'b0; + end + end + + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_63 = (_zz_62 & (~ _zz_325)); + assign _zz_64 = _zz_63[3]; + assign _zz_65 = (_zz_63[1] || _zz_64); + assign _zz_66 = (_zz_63[2] || _zz_64); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_250; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @ (*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_327); + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_67); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_68); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_69 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_69); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_69); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_70; + assign _zz_70 = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_71 = _zz_72; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_73)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_73 = _zz_74; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_73; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_75; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + always @ (*) begin + decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + case(_zz_179) + 3'b010 : begin + decode_arbitration_isValid = 1'b1; + end + 3'b011 : begin + decode_arbitration_isValid = 1'b1; + end + default : begin + end + endcase + end + + assign _zz_76 = _zz_328[11]; + always @ (*) begin + _zz_77[18] = _zz_76; + _zz_77[17] = _zz_76; + _zz_77[16] = _zz_76; + _zz_77[15] = _zz_76; + _zz_77[14] = _zz_76; + _zz_77[13] = _zz_76; + _zz_77[12] = _zz_76; + _zz_77[11] = _zz_76; + _zz_77[10] = _zz_76; + _zz_77[9] = _zz_76; + _zz_77[8] = _zz_76; + _zz_77[7] = _zz_76; + _zz_77[6] = _zz_76; + _zz_77[5] = _zz_76; + _zz_77[4] = _zz_76; + _zz_77[3] = _zz_76; + _zz_77[2] = _zz_76; + _zz_77[1] = _zz_76; + _zz_77[0] = _zz_76; + end + + always @ (*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_329[31])); + if(_zz_82)begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_78 = _zz_330[19]; + always @ (*) begin + _zz_79[10] = _zz_78; + _zz_79[9] = _zz_78; + _zz_79[8] = _zz_78; + _zz_79[7] = _zz_78; + _zz_79[6] = _zz_78; + _zz_79[5] = _zz_78; + _zz_79[4] = _zz_78; + _zz_79[3] = _zz_78; + _zz_79[2] = _zz_78; + _zz_79[1] = _zz_78; + _zz_79[0] = _zz_78; + end + + assign _zz_80 = _zz_331[11]; + always @ (*) begin + _zz_81[18] = _zz_80; + _zz_81[17] = _zz_80; + _zz_81[16] = _zz_80; + _zz_81[15] = _zz_80; + _zz_81[14] = _zz_80; + _zz_81[13] = _zz_80; + _zz_81[12] = _zz_80; + _zz_81[11] = _zz_80; + _zz_81[10] = _zz_80; + _zz_81[9] = _zz_80; + _zz_81[8] = _zz_80; + _zz_81[7] = _zz_80; + _zz_81[6] = _zz_80; + _zz_81[5] = _zz_80; + _zz_81[4] = _zz_80; + _zz_81[3] = _zz_80; + _zz_81[2] = _zz_80; + _zz_81[1] = _zz_80; + _zz_81[0] = _zz_80; + end + + always @ (*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_82 = _zz_332[1]; + end + default : begin + _zz_82 = _zz_333[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_83 = _zz_334[19]; + always @ (*) begin + _zz_84[10] = _zz_83; + _zz_84[9] = _zz_83; + _zz_84[8] = _zz_83; + _zz_84[7] = _zz_83; + _zz_84[6] = _zz_83; + _zz_84[5] = _zz_83; + _zz_84[4] = _zz_83; + _zz_84[3] = _zz_83; + _zz_84[2] = _zz_83; + _zz_84[1] = _zz_83; + _zz_84[0] = _zz_83; + end + + assign _zz_85 = _zz_335[11]; + always @ (*) begin + _zz_86[18] = _zz_85; + _zz_86[17] = _zz_85; + _zz_86[16] = _zz_85; + _zz_86[15] = _zz_85; + _zz_86[14] = _zz_85; + _zz_86[13] = _zz_85; + _zz_86[12] = _zz_85; + _zz_86[11] = _zz_85; + _zz_86[10] = _zz_85; + _zz_86[9] = _zz_85; + _zz_86[8] = _zz_85; + _zz_86[7] = _zz_85; + _zz_86[6] = _zz_85; + _zz_86[5] = _zz_85; + _zz_86[4] = _zz_85; + _zz_86[3] = _zz_85; + _zz_86[2] = _zz_85; + _zz_86[1] = _zz_85; + _zz_86[0] = _zz_85; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_414,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_415,_zz_416},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_222; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign _zz_225 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_226 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_227 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_260)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_258)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @ (*) begin + _zz_228 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_258)begin + _zz_228 = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_259)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_257)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(_zz_259)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(_zz_257)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign _zz_220 = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign _zz_247 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); + assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign _zz_229 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_230 = execute_SRC_ADD; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_89 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_89 = execute_RS2[31 : 0]; + end + endcase + end + + assign _zz_246 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign _zz_231 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign _zz_232 = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_231; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_232; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @ (*) begin + _zz_233 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin + _zz_233 = 1'b1; + end + end + + assign _zz_234 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_235 = (CsrPlugin_privilege == 2'b00); + assign _zz_236 = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_270)begin + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_270)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(_zz_270)begin + if(dataCache_1_io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; + end + if(dataCache_1_io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_90 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_91[31] = _zz_90; + _zz_91[30] = _zz_90; + _zz_91[29] = _zz_90; + _zz_91[28] = _zz_90; + _zz_91[27] = _zz_90; + _zz_91[26] = _zz_90; + _zz_91[25] = _zz_90; + _zz_91[24] = _zz_90; + _zz_91[23] = _zz_90; + _zz_91[22] = _zz_90; + _zz_91[21] = _zz_90; + _zz_91[20] = _zz_90; + _zz_91[19] = _zz_90; + _zz_91[18] = _zz_90; + _zz_91[17] = _zz_90; + _zz_91[16] = _zz_90; + _zz_91[15] = _zz_90; + _zz_91[14] = _zz_90; + _zz_91[13] = _zz_90; + _zz_91[12] = _zz_90; + _zz_91[11] = _zz_90; + _zz_91[10] = _zz_90; + _zz_91[9] = _zz_90; + _zz_91[8] = _zz_90; + _zz_91[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; + end + + assign _zz_92 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @ (*) begin + _zz_93[31] = _zz_92; + _zz_93[30] = _zz_92; + _zz_93[29] = _zz_92; + _zz_93[28] = _zz_92; + _zz_93[27] = _zz_92; + _zz_93[26] = _zz_92; + _zz_93[25] = _zz_92; + _zz_93[24] = _zz_92; + _zz_93[23] = _zz_92; + _zz_93[22] = _zz_92; + _zz_93[21] = _zz_92; + _zz_93[20] = _zz_92; + _zz_93[19] = _zz_92; + _zz_93[18] = _zz_92; + _zz_93[17] = _zz_92; + _zz_93[16] = _zz_92; + _zz_93[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_291) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_91; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_93; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end + endcase + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_96 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_94 = {(((decode_INSTRUCTION & _zz_417) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}; + assign _zz_100 = _zz_94[2 : 1]; + assign _zz_56 = _zz_100; + assign _zz_101 = _zz_94[7 : 6]; + assign _zz_55 = _zz_101; + assign _zz_102 = _zz_94[9 : 8]; + assign _zz_54 = _zz_102; + assign _zz_103 = _zz_94[19 : 18]; + assign _zz_53 = _zz_103; + assign _zz_104 = _zz_94[22 : 21]; + assign _zz_52 = _zz_104; + assign _zz_105 = _zz_94[24 : 23]; + assign _zz_51 = _zz_105; + assign _zz_106 = _zz_94[27 : 26]; + assign _zz_50 = _zz_106; + assign _zz_107 = _zz_94[29 : 29]; + assign _zz_49 = _zz_107; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_248; + assign decode_RegFilePlugin_rs2Data = _zz_249; + always @ (*) begin + lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); + if(_zz_108)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; + if(_zz_108)begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @ (*) begin + lastStageRegFileWrite_payload_data = _zz_57; + if(_zz_108)begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_109 = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_109 = {31'd0, _zz_338}; + end + default : begin + _zz_109 = execute_SRC_ADD_SUB; + end + endcase + end + + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_110 = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_110 = {29'd0, _zz_339}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_110 = {27'd0, _zz_340}; + end + endcase + end + + assign _zz_111 = _zz_341[11]; + always @ (*) begin + _zz_112[19] = _zz_111; + _zz_112[18] = _zz_111; + _zz_112[17] = _zz_111; + _zz_112[16] = _zz_111; + _zz_112[15] = _zz_111; + _zz_112[14] = _zz_111; + _zz_112[13] = _zz_111; + _zz_112[12] = _zz_111; + _zz_112[11] = _zz_111; + _zz_112[10] = _zz_111; + _zz_112[9] = _zz_111; + _zz_112[8] = _zz_111; + _zz_112[7] = _zz_111; + _zz_112[6] = _zz_111; + _zz_112[5] = _zz_111; + _zz_112[4] = _zz_111; + _zz_112[3] = _zz_111; + _zz_112[2] = _zz_111; + _zz_112[1] = _zz_111; + _zz_112[0] = _zz_111; + end + + assign _zz_113 = _zz_342[11]; + always @ (*) begin + _zz_114[19] = _zz_113; + _zz_114[18] = _zz_113; + _zz_114[17] = _zz_113; + _zz_114[16] = _zz_113; + _zz_114[15] = _zz_113; + _zz_114[14] = _zz_113; + _zz_114[13] = _zz_113; + _zz_114[12] = _zz_113; + _zz_114[11] = _zz_113; + _zz_114[10] = _zz_113; + _zz_114[9] = _zz_113; + _zz_114[8] = _zz_113; + _zz_114[7] = _zz_113; + _zz_114[6] = _zz_113; + _zz_114[5] = _zz_113; + _zz_114[4] = _zz_113; + _zz_114[3] = _zz_113; + _zz_114[2] = _zz_113; + _zz_114[1] = _zz_113; + _zz_114[0] = _zz_113; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_115 = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_115 = _zz_41; + end + endcase + end + + always @ (*) begin + execute_SrcPlugin_addSub = _zz_343; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @ (*) begin + _zz_116[0] = execute_SRC1[31]; + _zz_116[1] = execute_SRC1[30]; + _zz_116[2] = execute_SRC1[29]; + _zz_116[3] = execute_SRC1[28]; + _zz_116[4] = execute_SRC1[27]; + _zz_116[5] = execute_SRC1[26]; + _zz_116[6] = execute_SRC1[25]; + _zz_116[7] = execute_SRC1[24]; + _zz_116[8] = execute_SRC1[23]; + _zz_116[9] = execute_SRC1[22]; + _zz_116[10] = execute_SRC1[21]; + _zz_116[11] = execute_SRC1[20]; + _zz_116[12] = execute_SRC1[19]; + _zz_116[13] = execute_SRC1[18]; + _zz_116[14] = execute_SRC1[17]; + _zz_116[15] = execute_SRC1[16]; + _zz_116[16] = execute_SRC1[15]; + _zz_116[17] = execute_SRC1[14]; + _zz_116[18] = execute_SRC1[13]; + _zz_116[19] = execute_SRC1[12]; + _zz_116[20] = execute_SRC1[11]; + _zz_116[21] = execute_SRC1[10]; + _zz_116[22] = execute_SRC1[9]; + _zz_116[23] = execute_SRC1[8]; + _zz_116[24] = execute_SRC1[7]; + _zz_116[25] = execute_SRC1[6]; + _zz_116[26] = execute_SRC1[5]; + _zz_116[27] = execute_SRC1[4]; + _zz_116[28] = execute_SRC1[3]; + _zz_116[29] = execute_SRC1[2]; + _zz_116[30] = execute_SRC1[1]; + _zz_116[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); + always @ (*) begin + _zz_117[0] = memory_SHIFT_RIGHT[31]; + _zz_117[1] = memory_SHIFT_RIGHT[30]; + _zz_117[2] = memory_SHIFT_RIGHT[29]; + _zz_117[3] = memory_SHIFT_RIGHT[28]; + _zz_117[4] = memory_SHIFT_RIGHT[27]; + _zz_117[5] = memory_SHIFT_RIGHT[26]; + _zz_117[6] = memory_SHIFT_RIGHT[25]; + _zz_117[7] = memory_SHIFT_RIGHT[24]; + _zz_117[8] = memory_SHIFT_RIGHT[23]; + _zz_117[9] = memory_SHIFT_RIGHT[22]; + _zz_117[10] = memory_SHIFT_RIGHT[21]; + _zz_117[11] = memory_SHIFT_RIGHT[20]; + _zz_117[12] = memory_SHIFT_RIGHT[19]; + _zz_117[13] = memory_SHIFT_RIGHT[18]; + _zz_117[14] = memory_SHIFT_RIGHT[17]; + _zz_117[15] = memory_SHIFT_RIGHT[16]; + _zz_117[16] = memory_SHIFT_RIGHT[15]; + _zz_117[17] = memory_SHIFT_RIGHT[14]; + _zz_117[18] = memory_SHIFT_RIGHT[13]; + _zz_117[19] = memory_SHIFT_RIGHT[12]; + _zz_117[20] = memory_SHIFT_RIGHT[11]; + _zz_117[21] = memory_SHIFT_RIGHT[10]; + _zz_117[22] = memory_SHIFT_RIGHT[9]; + _zz_117[23] = memory_SHIFT_RIGHT[8]; + _zz_117[24] = memory_SHIFT_RIGHT[7]; + _zz_117[25] = memory_SHIFT_RIGHT[6]; + _zz_117[26] = memory_SHIFT_RIGHT[5]; + _zz_117[27] = memory_SHIFT_RIGHT[4]; + _zz_117[28] = memory_SHIFT_RIGHT[3]; + _zz_117[29] = memory_SHIFT_RIGHT[2]; + _zz_117[30] = memory_SHIFT_RIGHT[1]; + _zz_117[31] = memory_SHIFT_RIGHT[0]; + end + + always @ (*) begin + _zz_118 = 1'b0; + if(_zz_271)begin + if(_zz_272)begin + if(_zz_123)begin + _zz_118 = 1'b1; + end + end + end + if(_zz_273)begin + if(_zz_274)begin + if(_zz_125)begin + _zz_118 = 1'b1; + end + end + end + if(_zz_275)begin + if(_zz_276)begin + if(_zz_127)begin + _zz_118 = 1'b1; + end + end + end + if((! decode_RS1_USE))begin + _zz_118 = 1'b0; + end + end + + always @ (*) begin + _zz_119 = 1'b0; + if(_zz_271)begin + if(_zz_272)begin + if(_zz_124)begin + _zz_119 = 1'b1; + end + end + end + if(_zz_273)begin + if(_zz_274)begin + if(_zz_126)begin + _zz_119 = 1'b1; + end + end + end + if(_zz_275)begin + if(_zz_276)begin + if(_zz_128)begin + _zz_119 = 1'b1; + end + end + end + if((! decode_RS2_USE))begin + _zz_119 = 1'b0; + end + end + + assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_129 = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_129 == 3'b000)) begin + _zz_130 = execute_BranchPlugin_eq; + end else if((_zz_129 == 3'b001)) begin + _zz_130 = (! execute_BranchPlugin_eq); + end else if((((_zz_129 & 3'b101) == 3'b101))) begin + _zz_130 = (! execute_SRC_LESS); + end else begin + _zz_130 = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_131 = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_131 = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_131 = 1'b1; + end + default : begin + _zz_131 = _zz_130; + end + endcase + end + + assign _zz_132 = _zz_350[11]; + always @ (*) begin + _zz_133[19] = _zz_132; + _zz_133[18] = _zz_132; + _zz_133[17] = _zz_132; + _zz_133[16] = _zz_132; + _zz_133[15] = _zz_132; + _zz_133[14] = _zz_132; + _zz_133[13] = _zz_132; + _zz_133[12] = _zz_132; + _zz_133[11] = _zz_132; + _zz_133[10] = _zz_132; + _zz_133[9] = _zz_132; + _zz_133[8] = _zz_132; + _zz_133[7] = _zz_132; + _zz_133[6] = _zz_132; + _zz_133[5] = _zz_132; + _zz_133[4] = _zz_132; + _zz_133[3] = _zz_132; + _zz_133[2] = _zz_132; + _zz_133[1] = _zz_132; + _zz_133[0] = _zz_132; + end + + assign _zz_134 = _zz_351[19]; + always @ (*) begin + _zz_135[10] = _zz_134; + _zz_135[9] = _zz_134; + _zz_135[8] = _zz_134; + _zz_135[7] = _zz_134; + _zz_135[6] = _zz_134; + _zz_135[5] = _zz_134; + _zz_135[4] = _zz_134; + _zz_135[3] = _zz_134; + _zz_135[2] = _zz_134; + _zz_135[1] = _zz_134; + _zz_135[0] = _zz_134; + end + + assign _zz_136 = _zz_352[11]; + always @ (*) begin + _zz_137[18] = _zz_136; + _zz_137[17] = _zz_136; + _zz_137[16] = _zz_136; + _zz_137[15] = _zz_136; + _zz_137[14] = _zz_136; + _zz_137[13] = _zz_136; + _zz_137[12] = _zz_136; + _zz_137[11] = _zz_136; + _zz_137[10] = _zz_136; + _zz_137[9] = _zz_136; + _zz_137[8] = _zz_136; + _zz_137[7] = _zz_136; + _zz_137[6] = _zz_136; + _zz_137[5] = _zz_136; + _zz_137[4] = _zz_136; + _zz_137[3] = _zz_136; + _zz_137[2] = _zz_136; + _zz_137[1] = _zz_136; + _zz_137[0] = _zz_136; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_138 = (_zz_353[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_138 = _zz_354[1]; + end + default : begin + _zz_138 = _zz_355[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_139 = _zz_356[11]; + always @ (*) begin + _zz_140[19] = _zz_139; + _zz_140[18] = _zz_139; + _zz_140[17] = _zz_139; + _zz_140[16] = _zz_139; + _zz_140[15] = _zz_139; + _zz_140[14] = _zz_139; + _zz_140[13] = _zz_139; + _zz_140[12] = _zz_139; + _zz_140[11] = _zz_139; + _zz_140[10] = _zz_139; + _zz_140[9] = _zz_139; + _zz_140[8] = _zz_139; + _zz_140[7] = _zz_139; + _zz_140[6] = _zz_139; + _zz_140[5] = _zz_139; + _zz_140[4] = _zz_139; + _zz_140[3] = _zz_139; + _zz_140[2] = _zz_139; + _zz_140[1] = _zz_139; + _zz_140[0] = _zz_139; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_594,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_595,_zz_596},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2)begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_359}; + end + end + endcase + end + + assign _zz_141 = _zz_357[19]; + always @ (*) begin + _zz_142[10] = _zz_141; + _zz_142[9] = _zz_141; + _zz_142[8] = _zz_141; + _zz_142[7] = _zz_141; + _zz_142[6] = _zz_141; + _zz_142[5] = _zz_141; + _zz_142[4] = _zz_141; + _zz_142[3] = _zz_141; + _zz_142[2] = _zz_141; + _zz_142[1] = _zz_141; + _zz_142[0] = _zz_141; + end + + assign _zz_143 = _zz_358[11]; + always @ (*) begin + _zz_144[18] = _zz_143; + _zz_144[17] = _zz_143; + _zz_144[16] = _zz_143; + _zz_144[15] = _zz_143; + _zz_144[14] = _zz_143; + _zz_144[13] = _zz_143; + _zz_144[12] = _zz_143; + _zz_144[11] = _zz_143; + _zz_144[10] = _zz_143; + _zz_144[9] = _zz_143; + _zz_144[8] = _zz_143; + _zz_144[7] = _zz_143; + _zz_144[6] = _zz_143; + _zz_144[5] = _zz_143; + _zz_144[4] = _zz_143; + _zz_144[3] = _zz_143; + _zz_144[2] = _zz_143; + _zz_144[1] = _zz_143; + _zz_144[0] = _zz_143; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @ (*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_149 = _zz_360[0]; + assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_151 = _zz_362[0]; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_261)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_264)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @ (*) begin + CsrPlugin_xtvec_base = 30'h0; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3264)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3857)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3200)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3074)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3202)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2820)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2822)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2824)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2826)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2828)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2830)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2832)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_2834)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032)begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(_zz_277)begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + if(_zz_278)begin + CsrPlugin_selfException_valid = 1'b1; + end + if(_zz_279)begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(_zz_278)begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(_zz_279)begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + always @ (*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(_zz_277)begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(_zz_277)begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_292) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign execute_CfuPlugin_functionsIds_0 = _zz_364; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_168 = _zz_365[7]; + always @ (*) begin + _zz_169[23] = _zz_168; + _zz_169[22] = _zz_168; + _zz_169[21] = _zz_168; + _zz_169[20] = _zz_168; + _zz_169[19] = _zz_168; + _zz_169[18] = _zz_168; + _zz_169[17] = _zz_168; + _zz_169[16] = _zz_168; + _zz_169[15] = _zz_168; + _zz_169[14] = _zz_168; + _zz_169[13] = _zz_168; + _zz_169[12] = _zz_168; + _zz_169[11] = _zz_168; + _zz_169[10] = _zz_168; + _zz_169[9] = _zz_168; + _zz_169[8] = _zz_168; + _zz_169[7] = _zz_168; + _zz_169[6] = _zz_168; + _zz_169[5] = _zz_168; + _zz_169[4] = _zz_168; + _zz_169[3] = _zz_168; + _zz_169[2] = _zz_168; + _zz_169[1] = _zz_168; + _zz_169[0] = _zz_168; + end + + always @ (*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_defaultEncoding_RS : begin + _zz_170 = execute_RS2; + end + default : begin + _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; + assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); + assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); + assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @ (*) begin + CfuPlugin_joinException_valid = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + if(memory_arbitration_isValid)begin + CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); + end + end + end + + assign CfuPlugin_joinException_payload_code = 4'b1111; + assign CfuPlugin_joinException_payload_badAddr = 32'h0; + always @ (*) begin + memory_CfuPlugin_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT)begin + memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + always @ (*) begin + case(_zz_280) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @ (*) begin + case(_zz_280) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_366) + $signed(_zz_367)); + assign memory_DivPlugin_frontendOk = 1'b1; + always @ (*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(_zz_256)begin + if(_zz_281)begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(_zz_282)begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @ (*) begin + if(memory_DivPlugin_div_counter_willOverflow)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371); + end + if(memory_DivPlugin_div_counter_willClear)begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_372); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_373 : _zz_374); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_375[31:0]; + assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @ (*) begin + _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_175[31 : 0] = execute_RS1; + end + + assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_177 != 32'h0); + always @ (*) begin + debug_bus_cmd_ready = 1'b1; + if(debug_bus_cmd_valid)begin + case(_zz_283) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; + end + end + default : begin + end + endcase + end + end + + always @ (*) begin + debug_bus_rsp_data = DebugPlugin_busReadDataReg; + if((! _zz_178))begin + debug_bus_rsp_data[0] = DebugPlugin_resetIt; + debug_bus_rsp_data[1] = DebugPlugin_haltIt; + debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; + debug_bus_rsp_data[3] = DebugPlugin_haltedByBreak; + debug_bus_rsp_data[4] = DebugPlugin_stepIt; + end + end + + always @ (*) begin + IBusCachedPlugin_injectionPort_valid = 1'b0; + if(debug_bus_cmd_valid)begin + case(_zz_283) + 6'h01 : begin + if(debug_bus_cmd_payload_wr)begin + IBusCachedPlugin_injectionPort_valid = 1'b1; + end + end + default : begin + end + endcase + end + end + + assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; + assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign debug_resetOut = DebugPlugin_resetIt_regNext; + assign _zz_29 = decode_SRC1_CTRL; + assign _zz_27 = _zz_56; + assign _zz_43 = decode_to_execute_SRC1_CTRL; + assign _zz_26 = decode_ALU_CTRL; + assign _zz_24 = _zz_55; + assign _zz_44 = decode_to_execute_ALU_CTRL; + assign _zz_23 = decode_SRC2_CTRL; + assign _zz_21 = _zz_54; + assign _zz_42 = decode_to_execute_SRC2_CTRL; + assign _zz_20 = decode_ALU_BITWISE_CTRL; + assign _zz_18 = _zz_53; + assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_17 = decode_SHIFT_CTRL; + assign _zz_14 = execute_SHIFT_CTRL; + assign _zz_15 = _zz_52; + assign _zz_40 = decode_to_execute_SHIFT_CTRL; + assign _zz_39 = execute_to_memory_SHIFT_CTRL; + assign _zz_12 = decode_BRANCH_CTRL; + assign _zz_58 = _zz_51; + assign _zz_36 = decode_to_execute_BRANCH_CTRL; + assign _zz_10 = decode_ENV_CTRL; + assign _zz_7 = execute_ENV_CTRL; + assign _zz_5 = memory_ENV_CTRL; + assign _zz_8 = _zz_50; + assign _zz_34 = decode_to_execute_ENV_CTRL; + assign _zz_33 = execute_to_memory_ENV_CTRL; + assign _zz_35 = memory_to_writeBack_ENV_CTRL; + assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_1 = _zz_49; + assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + IBusCachedPlugin_injectionPort_ready = 1'b0; + case(_zz_179) + 3'b100 : begin + IBusCachedPlugin_injectionPort_ready = 1'b1; + end + default : begin + end + endcase + end + + always @ (*) begin + _zz_180 = 32'h0; + if(execute_CsrPlugin_csr_3264)begin + _zz_180[12 : 0] = 13'h1000; + _zz_180[25 : 20] = 6'h20; + end + end + + always @ (*) begin + _zz_181 = 32'h0; + if(execute_CsrPlugin_csr_3857)begin + _zz_181[3 : 0] = 4'b1011; + end + end + + always @ (*) begin + _zz_182 = 32'h0; + if(execute_CsrPlugin_csr_3858)begin + _zz_182[4 : 0] = 5'h16; + end + end + + always @ (*) begin + _zz_183 = 32'h0; + if(execute_CsrPlugin_csr_3859)begin + _zz_183[5 : 0] = 6'h21; + end + end + + always @ (*) begin + _zz_184 = 32'h0; + if(execute_CsrPlugin_csr_769)begin + _zz_184[31 : 30] = CsrPlugin_misa_base; + _zz_184[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @ (*) begin + _zz_185 = 32'h0; + if(execute_CsrPlugin_csr_768)begin + _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @ (*) begin + _zz_186 = 32'h0; + if(execute_CsrPlugin_csr_836)begin + _zz_186[11 : 11] = CsrPlugin_mip_MEIP; + _zz_186[7 : 7] = CsrPlugin_mip_MTIP; + _zz_186[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @ (*) begin + _zz_187 = 32'h0; + if(execute_CsrPlugin_csr_772)begin + _zz_187[11 : 11] = CsrPlugin_mie_MEIE; + _zz_187[7 : 7] = CsrPlugin_mie_MTIE; + _zz_187[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @ (*) begin + _zz_188 = 32'h0; + if(execute_CsrPlugin_csr_773)begin + _zz_188[31 : 2] = CsrPlugin_mtvec_base; + _zz_188[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @ (*) begin + _zz_189 = 32'h0; + if(execute_CsrPlugin_csr_833)begin + _zz_189[31 : 0] = CsrPlugin_mepc; + end + end + + always @ (*) begin + _zz_190 = 32'h0; + if(execute_CsrPlugin_csr_832)begin + _zz_190[31 : 0] = CsrPlugin_mscratch; + end + end + + always @ (*) begin + _zz_191 = 32'h0; + if(execute_CsrPlugin_csr_834)begin + _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @ (*) begin + _zz_192 = 32'h0; + if(execute_CsrPlugin_csr_835)begin + _zz_192[31 : 0] = CsrPlugin_mtval; + end + end + + always @ (*) begin + _zz_193 = 32'h0; + if(execute_CsrPlugin_csr_2816)begin + _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_194 = 32'h0; + if(execute_CsrPlugin_csr_2944)begin + _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_195 = 32'h0; + if(execute_CsrPlugin_csr_2818)begin + _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_196 = 32'h0; + if(execute_CsrPlugin_csr_2946)begin + _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_197 = 32'h0; + if(execute_CsrPlugin_csr_3072)begin + _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @ (*) begin + _zz_198 = 32'h0; + if(execute_CsrPlugin_csr_3200)begin + _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @ (*) begin + _zz_199 = 32'h0; + if(execute_CsrPlugin_csr_3074)begin + _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @ (*) begin + _zz_200 = 32'h0; + if(execute_CsrPlugin_csr_3202)begin + _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @ (*) begin + _zz_201 = 32'h0; + if(execute_CsrPlugin_csr_2820)begin + _zz_201[31 : 0] = _zz_152; + end + end + + always @ (*) begin + _zz_202 = 32'h0; + if(execute_CsrPlugin_csr_2822)begin + _zz_202[31 : 0] = _zz_154; + end + end + + always @ (*) begin + _zz_203 = 32'h0; + if(execute_CsrPlugin_csr_2824)begin + _zz_203[31 : 0] = _zz_156; + end + end + + always @ (*) begin + _zz_204 = 32'h0; + if(execute_CsrPlugin_csr_2826)begin + _zz_204[31 : 0] = _zz_158; + end + end + + always @ (*) begin + _zz_205 = 32'h0; + if(execute_CsrPlugin_csr_2828)begin + _zz_205[31 : 0] = _zz_160; + end + end + + always @ (*) begin + _zz_206 = 32'h0; + if(execute_CsrPlugin_csr_2830)begin + _zz_206[31 : 0] = _zz_162; + end + end + + always @ (*) begin + _zz_207 = 32'h0; + if(execute_CsrPlugin_csr_2832)begin + _zz_207[31 : 0] = _zz_164; + end + end + + always @ (*) begin + _zz_208 = 32'h0; + if(execute_CsrPlugin_csr_2834)begin + _zz_208[31 : 0] = _zz_166; + end + end + + always @ (*) begin + _zz_209 = 32'h0; + if(execute_CsrPlugin_csr_3008)begin + _zz_209[31 : 0] = _zz_176; + end + end + + always @ (*) begin + _zz_210 = 32'h0; + if(execute_CsrPlugin_csr_4032)begin + _zz_210[31 : 0] = _zz_177; + end + end + + assign execute_CsrPlugin_readData = (((((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_597 | _zz_184) | (_zz_185 | _zz_186))) | (((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194)))) | ((((_zz_195 | _zz_196) | (_zz_197 | _zz_198)) | ((_zz_199 | _zz_200) | (_zz_201 | _zz_202))) | (((_zz_203 | _zz_204) | (_zz_205 | _zz_206)) | ((_zz_207 | _zz_208) | (_zz_209 | _zz_210))))); + assign iBusWishbone_ADR = {_zz_392,_zz_211}; + assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'h0; + always @ (*) begin + iBusWishbone_CYC = 1'b0; + if(_zz_284)begin + iBusWishbone_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWishbone_STB = 1'b0; + if(_zz_284)begin + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_212; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_218 = (dBus_cmd_payload_length != 3'b000); + assign _zz_214 = dBus_cmd_valid; + assign _zz_216 = dBus_cmd_payload_wr; + assign _zz_217 = (_zz_213 == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_215 && (_zz_216 || _zz_217)); + assign dBusWishbone_ADR = ((_zz_218 ? {{dBus_cmd_payload_address[31 : 5],_zz_213},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_218 ? (_zz_217 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_216 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_216; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_215 = (_zz_214 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_214; + assign dBusWishbone_STB = _zz_214; + assign dBus_rsp_valid = _zz_219; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_72 <= 1'b0; + _zz_74 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_87; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_88; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_108 <= 1'b1; + _zz_120 <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + execute_CfuPlugin_hold <= 1'b0; + execute_CfuPlugin_fired <= 1'b0; + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_176 <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_179 <= 3'b000; + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; + _zz_211 <= 3'b000; + _zz_212 <= 1'b0; + _zz_213 <= 3'b000; + _zz_219 <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_72 <= 1'b0; + end + if(_zz_70)begin + _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_74 <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_74 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + end + if(_zz_285)begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_108 <= 1'b0; + _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(_zz_286)begin + if(_zz_287)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_288)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(_zz_289)begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); + if(CsrPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump)begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_266)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_267)begin + case(_zz_269) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(execute_CfuPlugin_schedule)begin + execute_CfuPlugin_hold <= 1'b1; + end + if(CfuPlugin_bus_cmd_ready)begin + execute_CfuPlugin_hold <= 1'b0; + end + if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + execute_CfuPlugin_fired <= 1'b1; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_CfuPlugin_fired <= 1'b0; + end + if(memory_CfuPlugin_rsp_ready)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + end + if(_zz_290)begin + CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + end + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if((! memory_arbitration_isStuck))begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + case(_zz_179) + 3'b000 : begin + if(IBusCachedPlugin_injectionPort_valid)begin + _zz_179 <= 3'b001; + end + end + 3'b001 : begin + _zz_179 <= 3'b010; + end + 3'b010 : begin + _zz_179 <= 3'b011; + end + 3'b011 : begin + if((! decode_arbitration_isStuck))begin + _zz_179 <= 3'b100; + end + end + 3'b100 : begin + _zz_179 <= 3'b000; + end + default : begin + end + endcase + if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; + CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_385[0]; + CsrPlugin_mstatus_MIE <= _zz_386[0]; + end + end + if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_388[0]; + CsrPlugin_mie_MTIE <= _zz_389[0]; + CsrPlugin_mie_MSIE <= _zz_390[0]; + end + end + if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(_zz_284)begin + if(iBusWishbone_ACK)begin + _zz_211 <= (_zz_211 + 3'b001); + end + end + _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_214 && _zz_215))begin + _zz_213 <= (_zz_213 + 3'b001); + if(_zz_217)begin + _zz_213 <= 3'b000; + end + end + _zz_219 <= ((_zz_214 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_75 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_285)begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; + dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + _zz_121 <= _zz_46[11 : 7]; + _zz_122 <= _zz_57; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_261)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_264)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + end + if(CfuPlugin_joinException_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(_zz_286)begin + if(_zz_287)begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_288)begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(_zz_289)begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(_zz_266)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(_zz_153[0])begin + _zz_152 <= (_zz_152 + 32'h00000001); + end + if(_zz_155[0])begin + _zz_154 <= (_zz_154 + 32'h00000001); + end + if(_zz_157[0])begin + _zz_156 <= (_zz_156 + 32'h00000001); + end + if(_zz_159[0])begin + _zz_158 <= (_zz_158 + 32'h00000001); + end + if(_zz_161[0])begin + _zz_160 <= (_zz_160 + 32'h00000001); + end + if(_zz_163[0])begin + _zz_162 <= (_zz_162 + 32'h00000001); + end + if(_zz_165[0])begin + _zz_164 <= (_zz_164 + 32'h00000001); + end + if(_zz_167[0])begin + _zz_166 <= (_zz_166 + 32'h00000001); + end + if(_zz_290)begin + CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; + CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + memory_DivPlugin_div_done <= 1'b0; + end + if(_zz_256)begin + if(_zz_281)begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if((memory_DivPlugin_div_counter_value == 6'h20))begin + memory_DivPlugin_div_result <= _zz_376[31:0]; + end + end + end + if(_zz_282)begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_382); + memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_384); + memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_41; + end + if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_28; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_16; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_CTRL <= _zz_13; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_ENV_CTRL <= _zz_6; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_ENV_CTRL <= _zz_4; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS1 <= decode_RS1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS2 <= decode_RS2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if((! execute_arbitration_isStuck))begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_387[0]; + end + end + if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcause_interrupt <= _zz_391[0]; + CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2821)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2823)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2825)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2827)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2829)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2831)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2833)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2835)begin + if(execute_CsrPlugin_writeEnable)begin + _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + always @ (posedge clk) begin + DebugPlugin_firstCycle <= 1'b0; + if(debug_bus_cmd_ready)begin + DebugPlugin_firstCycle <= 1'b1; + end + DebugPlugin_secondCycle <= DebugPlugin_firstCycle; + DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); + if(writeBack_arbitration_isValid)begin + DebugPlugin_busReadDataReg <= _zz_57; + end + _zz_178 <= debug_bus_cmd_payload_address[2]; + if(_zz_263)begin + DebugPlugin_busReadDataReg <= execute_PC; + end + DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; + end + + always @ (posedge clk) begin + if(debugReset) begin + DebugPlugin_resetIt <= 1'b0; + DebugPlugin_haltIt <= 1'b0; + DebugPlugin_stepIt <= 1'b0; + DebugPlugin_godmode <= 1'b0; + DebugPlugin_haltedByBreak <= 1'b0; + end else begin + if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + DebugPlugin_godmode <= 1'b1; + end + if(debug_bus_cmd_valid)begin + case(_zz_283) + 6'h0 : begin + if(debug_bus_cmd_payload_wr)begin + DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; + if(debug_bus_cmd_payload_data[16])begin + DebugPlugin_resetIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[24])begin + DebugPlugin_resetIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[17])begin + DebugPlugin_haltIt <= 1'b1; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltIt <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_haltedByBreak <= 1'b0; + end + if(debug_bus_cmd_payload_data[25])begin + DebugPlugin_godmode <= 1'b0; + end + end + end + default : begin + end + endcase + end + if(_zz_263)begin + if(_zz_265)begin + DebugPlugin_haltIt <= 1'b1; + DebugPlugin_haltedByBreak <= 1'b1; + end + end + if(_zz_268)begin + if(decode_arbitration_isValid)begin + DebugPlugin_haltIt <= 1'b1; + end + end + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10; + reg [31:0] _zz_11; + wire _zz_12; + wire _zz_13; + wire _zz_14; + wire _zz_15; + wire _zz_16; + wire _zz_17; + wire _zz_18; + wire [0:0] _zz_19; + wire [0:0] _zz_20; + wire [9:0] _zz_21; + wire [9:0] _zz_22; + wire [0:0] _zz_23; + wire [0:0] _zz_24; + wire [2:0] _zz_25; + wire [1:0] _zz_26; + wire [21:0] _zz_27; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_4; + wire _zz_5; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire rspSync; + wire rspLast; + reg memCmdSent; + reg [3:0] _zz_6; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire [0:0] _zz_7; + reg [0:0] stageA_wayInvalidate; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_8; + wire [0:0] stageA_dataColisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + reg [0:0] stageB_dataColisions; + reg stageB_unaligned; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_valid; + wire stageB_flusher_hold; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire [0:0] _zz_9; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire loader_done; + reg loader_valid_regNext; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_28; + reg [7:0] _zz_29; + reg [7:0] _zz_30; + reg [7:0] _zz_31; + + assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign _zz_17 = (! stageB_flusher_hold); + assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_19 = _zz_4[0 : 0]; + assign _zz_20 = _zz_4[1 : 1]; + assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_23 = 1'b1; + assign _zz_24 = loader_counter_willIncrement; + assign _zz_25 = {2'd0, _zz_24}; + assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3) begin + _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + end + end + + always @ (*) begin + _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + end + always @ (posedge clk) begin + if(_zz_5) begin + _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4 = _zz_10; + assign ways_0_tagsReadRsp_valid = _zz_19[0]; + assign ways_0_tagsReadRsp_error = _zz_20[0]; + assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; + assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_11; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_done)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done)begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done)begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_done)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + if(_zz_13)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_14)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(_zz_14)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(_zz_14)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(_zz_14)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache)begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_23[0])begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(_zz_14)begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign io_cpu_execute_haltIt = 1'b0; + assign rspSync = 1'b1; + assign rspLast = 1'b1; + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6 = 4'b0001; + end + 2'b01 : begin + _zz_6 = 4'b0011; + end + default : begin + _zz_6 = 4'b1111; + end + endcase + end + + assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign stageA_wayHits = _zz_7; + assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign stageB_consistancyHazard = 1'b0; + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_16)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(_zz_13)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = stageB_request_data; + always @ (*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + io_cpu_redo = 1'b1; + end + if((loader_valid && (! loader_valid_regNext)))begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache)begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(_zz_15)begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(_zz_16)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(_zz_13)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = 3'b000; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(_zz_16)begin + io_mem_cmd_payload_length = 3'b000; + end else begin + io_mem_cmd_payload_length = 3'b111; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_isExternalAmo) begin + if(! _zz_15) begin + if(! _zz_16) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + always @ (*) begin + if(stageB_bypassCache)begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_14)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_25); + if(loader_counter_willClear)begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign loader_done = loader_counter_willOverflow; + assign io_cpu_execute_refilling = loader_valid; + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if((! io_cpu_memory_isStuck))begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataColisions <= stageA_dataColisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(_zz_18)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + loader_valid_regNext <= loader_valid; + end + + always @ (posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_ready)begin + memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + memCmdSent <= 1'b0; + end + if(stageB_flusher_valid)begin + if(_zz_17)begin + if(! _zz_18) begin + stageB_flusher_valid <= 1'b0; + end + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("FAILURE writeBack stuck by another plugin is not allowed"); + $finish; + end + `endif + `endif + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill)begin + loader_killReg <= 1'b1; + end + if(_zz_14)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_26[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input [2:0] _zz_9, + input [31:0] _zz_10, + input clk, + input reset +); + reg [31:0] _zz_11; + reg [22:0] _zz_12; + wire _zz_13; + wire _zz_14; + wire [0:0] _zz_15; + wire [0:0] _zz_16; + wire [22:0] _zz_17; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + reg _zz_3; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [8:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire [8:0] _zz_4; + wire _zz_5; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_6; + wire _zz_7; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_8; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [31:0] io_cpu_fetch_data_regNextWhen; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + reg decodeStage_hit_valid; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; + + assign _zz_13 = (! lineLoader_flushCounter[6]); + assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_15 = _zz_8[0 : 0]; + assign _zz_16 = _zz_8[1 : 1]; + assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_5) begin + _zz_11 <= banks_0[_zz_4]; + end + end + + always @ (posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + end + end + + always @ (posedge clk) begin + if(_zz_7) begin + _zz_12 <= ways_0_tags[_zz_6]; + end + end + + always @ (*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1 = 1'b1; + end + end + + always @ (*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2 = 1'b1; + end + end + + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == 3'b111))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_13)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; + assign _zz_5 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; + assign _zz_7 = (! io_cpu_fetch_isStuck); + assign _zz_8 = _zz_12; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_14)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_13)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_3 <= lineLoader_flushCounter[6]; + if(_zz_14)begin + lineLoader_flushCounter <= 7'h0; + end + if((! io_cpu_decode_isStuck))begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_error <= fetchStage_hit_error; + end + if((_zz_9 != 3'b000))begin + io_cpu_fetch_data_regNextWhen <= _zz_10; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.yaml new file mode 100644 index 0000000..75d2f32 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.yaml @@ -0,0 +1,5 @@ +debug: !!vexriscv.DebugReport {hardwareBreakpointCount: 0} +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} + kind: cached From 9f85993307e913719381223ade365fdc0b477d2e Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Mon, 20 Sep 2021 21:09:39 -0700 Subject: [PATCH 26/30] Rebuild Verilogs at 593e180. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/VexRiscv.v | 6502 ++++++------ .../verilog/VexRiscv_Debug.v | 6723 ++++++------ .../verilog/VexRiscv_Fomu.v | 4757 ++++----- .../verilog/VexRiscv_FomuCfu.v | 5206 +++++----- .../verilog/VexRiscv_Full.v | 6902 +++++++------ .../verilog/VexRiscv_FullCfu.v | 8127 +++++++-------- .../verilog/VexRiscv_FullCfuDebug.v | 8384 +++++++-------- .../verilog/VexRiscv_FullDebug.v | 7123 +++++++------ .../verilog/VexRiscv_IMAC.v | 7162 +++++++------ .../verilog/VexRiscv_IMACDebug.v | 7383 +++++++------- .../verilog/VexRiscv_Linux.v | 8763 ++++++++-------- .../verilog/VexRiscv_LinuxDebug.v | 9016 +++++++++-------- .../verilog/VexRiscv_LinuxNoDspFmax.v | 8261 +++++++-------- .../verilog/VexRiscv_Lite.v | 5377 +++++----- .../verilog/VexRiscv_LiteDebug.v | 5581 +++++----- .../verilog/VexRiscv_Min.v | 4283 ++++---- .../verilog/VexRiscv_MinDebug.v | 4483 ++++---- .../verilog/VexRiscv_PerfCfu.v | 8127 +++++++-------- .../verilog/VexRiscv_PerfCfuDebug.v | 8384 +++++++-------- .../verilog/VexRiscv_Secure.v | 2 +- .../verilog/VexRiscv_SecureDebug.v | 2 +- .../verilog/VexRiscv_SlimCfu.v | 7365 +++++++------- .../verilog/VexRiscv_SlimCfuDebug.v | 7622 +++++++------- .../verilog/VexRiscv_SlimPerfCfu.v | 7759 +++++++------- .../verilog/VexRiscv_SlimPerfCfuDebug.v | 8016 ++++++++------- 25 files changed, 83502 insertions(+), 77808 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv.v b/pythondata_cpu_vexriscv/verilog/VexRiscv.v index f4629e6..59cf28d 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv.v @@ -1,46 +1,46 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b10 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -73,37 +73,37 @@ module VexRiscv ( input clk, input reset ); - wire _zz_165; - wire _zz_166; - wire _zz_167; - wire _zz_168; - wire _zz_169; - wire _zz_170; - wire _zz_171; - wire _zz_172; - reg _zz_173; - wire _zz_174; - wire [31:0] _zz_175; - wire _zz_176; - wire [31:0] _zz_177; - reg _zz_178; - wire _zz_179; - wire _zz_180; - wire [31:0] _zz_181; - wire _zz_182; - wire _zz_183; - wire _zz_184; - wire _zz_185; - wire _zz_186; - wire _zz_187; - wire _zz_188; - wire _zz_189; - wire [3:0] _zz_190; - wire _zz_191; - wire _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -126,6 +126,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -134,320 +135,267 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - wire _zz_204; - wire _zz_205; - wire _zz_206; - wire _zz_207; - wire _zz_208; - wire [1:0] _zz_209; - wire _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - wire [1:0] _zz_219; - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - wire [1:0] _zz_228; - wire _zz_229; - wire [1:0] _zz_230; - wire [51:0] _zz_231; - wire [51:0] _zz_232; - wire [51:0] _zz_233; - wire [32:0] _zz_234; - wire [51:0] _zz_235; - wire [49:0] _zz_236; - wire [51:0] _zz_237; - wire [49:0] _zz_238; - wire [51:0] _zz_239; - wire [32:0] _zz_240; - wire [31:0] _zz_241; - wire [32:0] _zz_242; - wire [0:0] _zz_243; - wire [0:0] _zz_244; - wire [0:0] _zz_245; - wire [0:0] _zz_246; - wire [0:0] _zz_247; - wire [0:0] _zz_248; - wire [0:0] _zz_249; - wire [0:0] _zz_250; - wire [0:0] _zz_251; - wire [0:0] _zz_252; - wire [0:0] _zz_253; - wire [0:0] _zz_254; - wire [0:0] _zz_255; - wire [0:0] _zz_256; - wire [0:0] _zz_257; - wire [0:0] _zz_258; - wire [0:0] _zz_259; - wire [3:0] _zz_260; - wire [2:0] _zz_261; - wire [31:0] _zz_262; - wire [11:0] _zz_263; - wire [31:0] _zz_264; - wire [19:0] _zz_265; - wire [11:0] _zz_266; - wire [31:0] _zz_267; - wire [31:0] _zz_268; - wire [19:0] _zz_269; - wire [11:0] _zz_270; - wire [2:0] _zz_271; - wire [2:0] _zz_272; - wire [0:0] _zz_273; - wire [2:0] _zz_274; - wire [4:0] _zz_275; - wire [11:0] _zz_276; - wire [11:0] _zz_277; - wire [31:0] _zz_278; - wire [31:0] _zz_279; - wire [31:0] _zz_280; - wire [31:0] _zz_281; - wire [31:0] _zz_282; - wire [31:0] _zz_283; - wire [31:0] _zz_284; - wire [11:0] _zz_285; - wire [19:0] _zz_286; - wire [11:0] _zz_287; - wire [31:0] _zz_288; - wire [31:0] _zz_289; - wire [31:0] _zz_290; - wire [11:0] _zz_291; - wire [19:0] _zz_292; - wire [11:0] _zz_293; - wire [2:0] _zz_294; - wire [1:0] _zz_295; - wire [1:0] _zz_296; - wire [65:0] _zz_297; - wire [65:0] _zz_298; - wire [31:0] _zz_299; - wire [31:0] _zz_300; - wire [0:0] _zz_301; - wire [5:0] _zz_302; - wire [32:0] _zz_303; - wire [31:0] _zz_304; - wire [31:0] _zz_305; - wire [32:0] _zz_306; - wire [32:0] _zz_307; - wire [32:0] _zz_308; - wire [32:0] _zz_309; - wire [0:0] _zz_310; - wire [32:0] _zz_311; - wire [0:0] _zz_312; - wire [32:0] _zz_313; - wire [0:0] _zz_314; - wire [31:0] _zz_315; - wire [0:0] _zz_316; - wire [0:0] _zz_317; - wire [0:0] _zz_318; - wire [0:0] _zz_319; - wire [0:0] _zz_320; - wire [0:0] _zz_321; - wire [26:0] _zz_322; - wire _zz_323; - wire _zz_324; - wire [1:0] _zz_325; - wire [31:0] _zz_326; - wire [31:0] _zz_327; - wire [31:0] _zz_328; - wire _zz_329; - wire [0:0] _zz_330; - wire [13:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [31:0] _zz_334; - wire _zz_335; - wire [0:0] _zz_336; - wire [7:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire [31:0] _zz_340; - wire _zz_341; - wire [0:0] _zz_342; - wire [1:0] _zz_343; - wire _zz_344; - wire _zz_345; - wire _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; - wire _zz_349; - wire [0:0] _zz_350; - wire [0:0] _zz_351; - wire _zz_352; - wire [0:0] _zz_353; - wire [24:0] _zz_354; - wire [31:0] _zz_355; - wire _zz_356; - wire _zz_357; - wire [0:0] _zz_358; - wire [0:0] _zz_359; - wire [0:0] _zz_360; - wire [0:0] _zz_361; - wire _zz_362; - wire [0:0] _zz_363; - wire [20:0] _zz_364; - wire [31:0] _zz_365; - wire [31:0] _zz_366; - wire _zz_367; - wire _zz_368; - wire [0:0] _zz_369; - wire [1:0] _zz_370; - wire [0:0] _zz_371; - wire [0:0] _zz_372; - wire _zz_373; - wire [0:0] _zz_374; - wire [17:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire [31:0] _zz_378; - wire [31:0] _zz_379; - wire [31:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire _zz_384; - wire [1:0] _zz_385; - wire [1:0] _zz_386; - wire _zz_387; - wire [0:0] _zz_388; - wire [14:0] _zz_389; - wire [31:0] _zz_390; - wire [31:0] _zz_391; - wire [31:0] _zz_392; - wire [31:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [0:0] _zz_396; - wire [0:0] _zz_397; - wire [2:0] _zz_398; - wire [2:0] _zz_399; - wire _zz_400; - wire [0:0] _zz_401; - wire [11:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire [31:0] _zz_405; - wire [31:0] _zz_406; - wire _zz_407; - wire _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire [0:0] _zz_411; - wire [3:0] _zz_412; - wire [4:0] _zz_413; - wire [4:0] _zz_414; - wire _zz_415; - wire [0:0] _zz_416; - wire [8:0] _zz_417; - wire [31:0] _zz_418; - wire [31:0] _zz_419; - wire [31:0] _zz_420; - wire [31:0] _zz_421; - wire [0:0] _zz_422; - wire [1:0] _zz_423; - wire [0:0] _zz_424; - wire [2:0] _zz_425; - wire [0:0] _zz_426; - wire [4:0] _zz_427; - wire [1:0] _zz_428; - wire [1:0] _zz_429; - wire _zz_430; - wire [0:0] _zz_431; - wire [6:0] _zz_432; - wire [31:0] _zz_433; - wire [31:0] _zz_434; - wire _zz_435; - wire _zz_436; - wire [31:0] _zz_437; - wire [31:0] _zz_438; - wire _zz_439; - wire [0:0] _zz_440; - wire [0:0] _zz_441; - wire _zz_442; - wire [0:0] _zz_443; - wire [2:0] _zz_444; - wire _zz_445; - wire [0:0] _zz_446; - wire [0:0] _zz_447; - wire [0:0] _zz_448; - wire [0:0] _zz_449; - wire _zz_450; - wire [0:0] _zz_451; - wire [4:0] _zz_452; - wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [31:0] _zz_456; - wire [31:0] _zz_457; - wire [31:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire [31:0] _zz_462; - wire _zz_463; - wire [0:0] _zz_464; - wire [0:0] _zz_465; - wire [31:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire _zz_471; - wire [3:0] _zz_472; - wire [3:0] _zz_473; - wire _zz_474; - wire [0:0] _zz_475; - wire [2:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; - wire [31:0] _zz_479; - wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire _zz_483; - wire [0:0] _zz_484; - wire [1:0] _zz_485; - wire _zz_486; - wire [2:0] _zz_487; - wire [2:0] _zz_488; - wire _zz_489; - wire [0:0] _zz_490; - wire [0:0] _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; - wire [31:0] _zz_496; - wire [31:0] _zz_497; - wire [31:0] _zz_498; - wire _zz_499; - wire _zz_500; - wire _zz_501; - wire [0:0] _zz_502; - wire [0:0] _zz_503; - wire _zz_504; - wire _zz_505; - wire _zz_506; - wire _zz_507; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_1; + wire _zz__zz_decode_IS_RS2_SIGNED_2; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_3; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_4; + wire _zz__zz_decode_IS_RS2_SIGNED_5; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_6; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_7; + wire _zz__zz_decode_IS_RS2_SIGNED_8; + wire _zz__zz_decode_IS_RS2_SIGNED_9; + wire [24:0] _zz__zz_decode_IS_RS2_SIGNED_10; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_11; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_12; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_13; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_14; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_15; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_16; + wire _zz__zz_decode_IS_RS2_SIGNED_17; + wire _zz__zz_decode_IS_RS2_SIGNED_18; + wire _zz__zz_decode_IS_RS2_SIGNED_19; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_20; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_21; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_22; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_23; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_24; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_25; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_26; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_27; + wire [20:0] _zz__zz_decode_IS_RS2_SIGNED_28; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_29; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_30; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_31; + wire _zz__zz_decode_IS_RS2_SIGNED_32; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_33; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_34; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_35; + wire _zz__zz_decode_IS_RS2_SIGNED_36; + wire [17:0] _zz__zz_decode_IS_RS2_SIGNED_37; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_38; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_39; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_40; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_41; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_42; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_43; + wire _zz__zz_decode_IS_RS2_SIGNED_44; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_45; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_46; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_47; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_48; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_49; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_50; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_51; + wire [14:0] _zz__zz_decode_IS_RS2_SIGNED_52; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_53; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_54; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_55; + wire _zz__zz_decode_IS_RS2_SIGNED_56; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_57; + wire _zz__zz_decode_IS_RS2_SIGNED_58; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_59; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_60; + wire _zz__zz_decode_IS_RS2_SIGNED_61; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_62; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_63; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_64; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_65; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_66; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_67; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_68; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_69; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_70; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_71; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_72; + wire _zz__zz_decode_IS_RS2_SIGNED_73; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_74; + wire _zz__zz_decode_IS_RS2_SIGNED_75; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_76; + wire [11:0] _zz__zz_decode_IS_RS2_SIGNED_77; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_78; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_79; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_80; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_81; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_82; + wire _zz__zz_decode_IS_RS2_SIGNED_83; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_84; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_85; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_86; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_87; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_88; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_89; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_90; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_91; + wire _zz__zz_decode_IS_RS2_SIGNED_92; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_93; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_94; + wire _zz__zz_decode_IS_RS2_SIGNED_95; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_96; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_97; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_98; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_99; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_100; + wire _zz__zz_decode_IS_RS2_SIGNED_101; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_102; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_103; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_104; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_105; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_106; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_107; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_108; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_109; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_110; + wire _zz__zz_decode_IS_RS2_SIGNED_111; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_112; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_113; + wire [8:0] _zz__zz_decode_IS_RS2_SIGNED_114; + wire _zz__zz_decode_IS_RS2_SIGNED_115; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_116; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_117; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_118; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_119; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_120; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_121; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_122; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_123; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_124; + wire [6:0] _zz__zz_decode_IS_RS2_SIGNED_125; + wire _zz__zz_decode_IS_RS2_SIGNED_126; + wire _zz__zz_decode_IS_RS2_SIGNED_127; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_128; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_129; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_130; + wire _zz__zz_decode_IS_RS2_SIGNED_131; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_132; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_133; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_134; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_135; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_136; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_137; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_138; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_139; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_140; + wire _zz__zz_decode_IS_RS2_SIGNED_141; + wire _zz__zz_decode_IS_RS2_SIGNED_142; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_143; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_144; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_145; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_146; + wire _zz__zz_decode_IS_RS2_SIGNED_147; + wire _zz__zz_decode_IS_RS2_SIGNED_148; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_149; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_150; + wire _zz__zz_decode_IS_RS2_SIGNED_151; + wire _zz__zz_decode_IS_RS2_SIGNED_152; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_153; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_154; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_155; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_156; + wire _zz__zz_decode_IS_RS2_SIGNED_157; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -458,8 +406,8 @@ module VexRiscv ( wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; @@ -470,27 +418,27 @@ module VexRiscv ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -498,18 +446,18 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; @@ -529,23 +477,23 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_31; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -555,45 +503,45 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_32; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_35; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_36; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; - wire [31:0] _zz_40; - wire _zz_41; - reg _zz_42; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_43; - wire `BranchCtrlEnum_defaultEncoding_type _zz_44; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; - wire `Src2CtrlEnum_defaultEncoding_type _zz_47; - wire `AluCtrlEnum_defaultEncoding_type _zz_48; - wire `Src1CtrlEnum_defaultEncoding_type _zz_49; - reg [31:0] _zz_50; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -611,11 +559,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_52; - reg [31:0] _zz_53; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -702,7 +650,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -736,6 +684,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; wire CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -753,28 +706,34 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_54; - wire [3:0] _zz_55; - wire _zz_56; - wire _zz_57; - wire _zz_58; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -797,16 +756,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_59; - wire _zz_60; - wire _zz_61; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_62; - wire _zz_63; - reg _zz_64; - wire _zz_65; - reg _zz_66; - reg [31:0] _zz_67; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -814,22 +775,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_68; - reg [18:0] _zz_69; - wire _zz_70; - reg [10:0] _zz_71; - wire _zz_72; - reg [18:0] _zz_73; - reg _zz_74; - wire _zz_75; - reg [10:0] _zz_76; - wire _zz_77; - reg [18:0] _zz_78; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -837,7 +805,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_79; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -845,23 +813,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -869,38 +842,54 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_80; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_81; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_82; - reg [31:0] _zz_83; - wire _zz_84; - reg [31:0] _zz_85; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [31:0] _zz_86; - wire _zz_87; - wire _zz_88; - wire _zz_89; - wire _zz_90; - wire `Src1CtrlEnum_defaultEncoding_type _zz_91; - wire `AluCtrlEnum_defaultEncoding_type _zz_92; - wire `Src2CtrlEnum_defaultEncoding_type _zz_93; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_94; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_95; - wire `BranchCtrlEnum_defaultEncoding_type _zz_96; - wire `EnvCtrlEnum_defaultEncoding_type _zz_97; + wire when_DBusCachedPlugin_l484; + wire [31:0] _zz_decode_IS_RS2_SIGNED; + wire _zz_decode_IS_RS2_SIGNED_1; + wire _zz_decode_IS_RS2_SIGNED_2; + wire _zz_decode_IS_RS2_SIGNED_3; + wire _zz_decode_IS_RS2_SIGNED_4; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -908,52 +897,70 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_98; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_99; - reg [31:0] _zz_100; - wire _zz_101; - reg [19:0] _zz_102; - wire _zz_103; - reg [19:0] _zz_104; - reg [31:0] _zz_105; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_106; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_107; - reg _zz_108; - reg _zz_109; - reg _zz_110; - reg [4:0] _zz_111; - reg [31:0] _zz_112; - wire _zz_113; - wire _zz_114; - wire _zz_115; - wire _zz_116; - wire _zz_117; - wire _zz_118; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_119; - reg _zz_120; - reg _zz_121; - wire _zz_122; - reg [19:0] _zz_123; - wire _zz_124; - reg [10:0] _zz_125; - wire _zz_126; - reg [18:0] _zz_127; - reg _zz_128; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_129; - reg [19:0] _zz_130; - wire _zz_131; - reg [10:0] _zz_132; - wire _zz_133; - reg [18:0] _zz_134; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; @@ -974,9 +981,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_135; - wire _zz_136; - wire _zz_137; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -989,40 +996,64 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_138; - wire _zz_139; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1030,6 +1061,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1042,180 +1075,268 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_140; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_141; - wire _zz_142; - wire _zz_143; - reg [32:0] _zz_144; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_145; - wire [31:0] _zz_146; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_44; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_45; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_46; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_47; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_48; reg decode_to_execute_CSR_READ_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_49; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_50; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_51; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_52; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_53; reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_54; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_55; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_57; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_60; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_61; reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_147; - reg [31:0] _zz_148; - reg [31:0] _zz_149; - reg [31:0] _zz_150; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [2:0] _zz_156; - reg _zz_157; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_158; - wire _zz_159; - wire _zz_160; - wire _zz_161; - wire _zz_162; - wire _zz_163; - reg _zz_164; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; - reg [39:0] _zz_17_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; - reg [23:0] _zz_20_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; - reg [63:0] _zz_23_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; - reg [95:0] _zz_26_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_30_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_33_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_34_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_36_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_37_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_38_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_39_string; - reg [39:0] _zz_43_string; - reg [31:0] _zz_44_string; - reg [71:0] _zz_45_string; - reg [39:0] _zz_46_string; - reg [23:0] _zz_47_string; - reg [63:0] _zz_48_string; - reg [95:0] _zz_49_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_51_string; - reg [95:0] _zz_91_string; - reg [63:0] _zz_92_string; - reg [23:0] _zz_93_string; - reg [39:0] _zz_94_string; - reg [71:0] _zz_95_string; - reg [31:0] _zz_96_string; - reg [39:0] _zz_97_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1230,1125 +1351,1096 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_196 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_197 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_198 = 1'b1; - assign _zz_199 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_200 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_201 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_202 = ((_zz_170 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_203 = ((_zz_170 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_204 = ((_zz_170 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_205 = ((_zz_170 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_206 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_207 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_208 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_209 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_210 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_211 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_212 = (1'b0 || (! 1'b1)); - assign _zz_213 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_214 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_215 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_216 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_217 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_218 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_219 = execute_INSTRUCTION[13 : 12]; - assign _zz_220 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_221 = (! memory_arbitration_isStuck); - assign _zz_222 = (iBus_cmd_valid || (_zz_156 != 3'b000)); - assign _zz_223 = (_zz_192 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_224 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_225 = ((_zz_135 && 1'b1) && (! 1'b0)); - assign _zz_226 = ((_zz_136 && 1'b1) && (! 1'b0)); - assign _zz_227 = ((_zz_137 && 1'b1) && (! 1'b0)); - assign _zz_228 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_229 = execute_INSTRUCTION[13]; - assign _zz_230 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_231 = ($signed(_zz_232) + $signed(_zz_237)); - assign _zz_232 = ($signed(_zz_233) + $signed(_zz_235)); - assign _zz_233 = 52'h0; - assign _zz_234 = {1'b0,memory_MUL_LL}; - assign _zz_235 = {{19{_zz_234[32]}}, _zz_234}; - assign _zz_236 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_237 = {{2{_zz_236[49]}}, _zz_236}; - assign _zz_238 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_239 = {{2{_zz_238[49]}}, _zz_238}; - assign _zz_240 = ($signed(_zz_242) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_241 = _zz_240[31 : 0]; - assign _zz_242 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_243 = _zz_86[31 : 31]; - assign _zz_244 = _zz_86[30 : 30]; - assign _zz_245 = _zz_86[29 : 29]; - assign _zz_246 = _zz_86[28 : 28]; - assign _zz_247 = _zz_86[25 : 25]; - assign _zz_248 = _zz_86[17 : 17]; - assign _zz_249 = _zz_86[16 : 16]; - assign _zz_250 = _zz_86[13 : 13]; - assign _zz_251 = _zz_86[12 : 12]; - assign _zz_252 = _zz_86[11 : 11]; - assign _zz_253 = _zz_86[15 : 15]; - assign _zz_254 = _zz_86[5 : 5]; - assign _zz_255 = _zz_86[3 : 3]; - assign _zz_256 = _zz_86[20 : 20]; - assign _zz_257 = _zz_86[10 : 10]; - assign _zz_258 = _zz_86[4 : 4]; - assign _zz_259 = _zz_86[0 : 0]; - assign _zz_260 = (_zz_54 - 4'b0001); - assign _zz_261 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_262 = {29'd0, _zz_261}; - assign _zz_263 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_264 = {{_zz_69,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_265 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_266 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_267 = {{_zz_71,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_268 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_269 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_270 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_271 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_272 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_273 = execute_SRC_LESS; - assign _zz_274 = 3'b100; - assign _zz_275 = execute_INSTRUCTION[19 : 15]; - assign _zz_276 = execute_INSTRUCTION[31 : 20]; - assign _zz_277 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_278 = ($signed(_zz_279) + $signed(_zz_282)); - assign _zz_279 = ($signed(_zz_280) + $signed(_zz_281)); - assign _zz_280 = execute_SRC1; - assign _zz_281 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_282 = (execute_SRC_USE_SUB_LESS ? _zz_283 : _zz_284); - assign _zz_283 = 32'h00000001; - assign _zz_284 = 32'h0; - assign _zz_285 = execute_INSTRUCTION[31 : 20]; - assign _zz_286 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_287 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_288 = {_zz_123,execute_INSTRUCTION[31 : 20]}; - assign _zz_289 = {{_zz_125,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_290 = {{_zz_127,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_291 = execute_INSTRUCTION[31 : 20]; - assign _zz_292 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_293 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_294 = 3'b100; - assign _zz_295 = (_zz_138 & (~ _zz_296)); - assign _zz_296 = (_zz_138 - 2'b01); - assign _zz_297 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_298 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_299 = writeBack_MUL_LOW[31 : 0]; - assign _zz_300 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_301 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_302 = {5'd0, _zz_301}; - assign _zz_303 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_304 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_305 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_306 = {_zz_140,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_307 = _zz_308; - assign _zz_308 = _zz_309; - assign _zz_309 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_141) : _zz_141)} + _zz_311); - assign _zz_310 = memory_DivPlugin_div_needRevert; - assign _zz_311 = {32'd0, _zz_310}; - assign _zz_312 = _zz_143; - assign _zz_313 = {32'd0, _zz_312}; - assign _zz_314 = _zz_142; - assign _zz_315 = {31'd0, _zz_314}; - assign _zz_316 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_317 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_318 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_319 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_320 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_321 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_322 = (iBus_cmd_payload_address >>> 5); - assign _zz_323 = 1'b1; - assign _zz_324 = 1'b1; - assign _zz_325 = {_zz_58,_zz_57}; - assign _zz_326 = 32'h0000107f; - assign _zz_327 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_328 = 32'h00002073; - assign _zz_329 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_330 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_331 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_332) == 32'h00000003),{(_zz_333 == _zz_334),{_zz_335,{_zz_336,_zz_337}}}}}}; - assign _zz_332 = 32'h0000505f; - assign _zz_333 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_334 = 32'h00000063; - assign _zz_335 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_336 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_337 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_338) == 32'h00001013),{(_zz_339 == _zz_340),{_zz_341,{_zz_342,_zz_343}}}}}}; - assign _zz_338 = 32'hfc00307f; - assign _zz_339 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_340 = 32'h00005033; - assign _zz_341 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_342 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_343 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; - assign _zz_344 = decode_INSTRUCTION[31]; - assign _zz_345 = decode_INSTRUCTION[31]; - assign _zz_346 = decode_INSTRUCTION[7]; - assign _zz_347 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_348 = 32'h02004020; - assign _zz_349 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_350 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); - assign _zz_351 = 1'b0; - assign _zz_352 = (((decode_INSTRUCTION & _zz_355) == 32'h10000050) != 1'b0); - assign _zz_353 = ({_zz_356,_zz_357} != 2'b00); - assign _zz_354 = {({_zz_358,_zz_359} != 2'b00),{(_zz_360 != _zz_361),{_zz_362,{_zz_363,_zz_364}}}}; - assign _zz_355 = 32'h10403050; - assign _zz_356 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_357 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_358 = _zz_89; - assign _zz_359 = ((decode_INSTRUCTION & _zz_365) == 32'h00000004); - assign _zz_360 = ((decode_INSTRUCTION & _zz_366) == 32'h00000040); - assign _zz_361 = 1'b0; - assign _zz_362 = ({_zz_367,_zz_368} != 2'b00); - assign _zz_363 = ({_zz_369,_zz_370} != 3'b000); - assign _zz_364 = {(_zz_371 != _zz_372),{_zz_373,{_zz_374,_zz_375}}}; - assign _zz_365 = 32'h0000001c; - assign _zz_366 = 32'h00000058; - assign _zz_367 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_368 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_369 = ((decode_INSTRUCTION & _zz_376) == 32'h40001010); - assign _zz_370 = {(_zz_377 == _zz_378),(_zz_379 == _zz_380)}; - assign _zz_371 = ((decode_INSTRUCTION & _zz_381) == 32'h00000024); - assign _zz_372 = 1'b0; - assign _zz_373 = ((_zz_382 == _zz_383) != 1'b0); - assign _zz_374 = (_zz_384 != 1'b0); - assign _zz_375 = {(_zz_385 != _zz_386),{_zz_387,{_zz_388,_zz_389}}}; - assign _zz_376 = 32'h40003054; - assign _zz_377 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_378 = 32'h00001010; - assign _zz_379 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_380 = 32'h00001010; - assign _zz_381 = 32'h00000064; - assign _zz_382 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_383 = 32'h00001000; - assign _zz_384 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_385 = {(_zz_390 == _zz_391),(_zz_392 == _zz_393)}; - assign _zz_386 = 2'b00; - assign _zz_387 = ((_zz_394 == _zz_395) != 1'b0); - assign _zz_388 = ({_zz_396,_zz_397} != 2'b00); - assign _zz_389 = {(_zz_398 != _zz_399),{_zz_400,{_zz_401,_zz_402}}}; - assign _zz_390 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_391 = 32'h00002000; - assign _zz_392 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_393 = 32'h00001000; - assign _zz_394 = (decode_INSTRUCTION & 32'h00004048); - assign _zz_395 = 32'h00004008; - assign _zz_396 = ((decode_INSTRUCTION & _zz_403) == 32'h00000020); - assign _zz_397 = ((decode_INSTRUCTION & _zz_404) == 32'h00000020); - assign _zz_398 = {(_zz_405 == _zz_406),{_zz_407,_zz_408}}; - assign _zz_399 = 3'b000; - assign _zz_400 = ((_zz_409 == _zz_410) != 1'b0); - assign _zz_401 = ({_zz_411,_zz_412} != 5'h0); - assign _zz_402 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; - assign _zz_403 = 32'h00000034; - assign _zz_404 = 32'h00000064; - assign _zz_405 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_406 = 32'h00000040; - assign _zz_407 = ((decode_INSTRUCTION & _zz_418) == 32'h0); - assign _zz_408 = ((decode_INSTRUCTION & _zz_419) == 32'h00000040); - assign _zz_409 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_410 = 32'h00000020; - assign _zz_411 = (_zz_420 == _zz_421); - assign _zz_412 = {_zz_88,{_zz_422,_zz_423}}; - assign _zz_413 = {_zz_88,{_zz_424,_zz_425}}; - assign _zz_414 = 5'h0; - assign _zz_415 = ({_zz_426,_zz_427} != 6'h0); - assign _zz_416 = (_zz_428 != _zz_429); - assign _zz_417 = {_zz_430,{_zz_431,_zz_432}}; - assign _zz_418 = 32'h00000038; - assign _zz_419 = 32'h00403040; - assign _zz_420 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_421 = 32'h00000040; - assign _zz_422 = (_zz_433 == _zz_434); - assign _zz_423 = {_zz_435,_zz_436}; - assign _zz_424 = (_zz_437 == _zz_438); - assign _zz_425 = {_zz_439,{_zz_440,_zz_441}}; - assign _zz_426 = _zz_89; - assign _zz_427 = {_zz_442,{_zz_443,_zz_444}}; - assign _zz_428 = {_zz_88,_zz_445}; - assign _zz_429 = 2'b00; - assign _zz_430 = ({_zz_446,_zz_447} != 2'b00); - assign _zz_431 = (_zz_448 != _zz_449); - assign _zz_432 = {_zz_450,{_zz_451,_zz_452}}; - assign _zz_433 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_434 = 32'h00004020; - assign _zz_435 = ((decode_INSTRUCTION & _zz_453) == 32'h00000010); - assign _zz_436 = ((decode_INSTRUCTION & _zz_454) == 32'h00000020); - assign _zz_437 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_438 = 32'h00002010; - assign _zz_439 = ((decode_INSTRUCTION & _zz_455) == 32'h00000010); - assign _zz_440 = (_zz_456 == _zz_457); - assign _zz_441 = (_zz_458 == _zz_459); - assign _zz_442 = ((decode_INSTRUCTION & _zz_460) == 32'h00001010); - assign _zz_443 = (_zz_461 == _zz_462); - assign _zz_444 = {_zz_463,{_zz_464,_zz_465}}; - assign _zz_445 = ((decode_INSTRUCTION & _zz_466) == 32'h00000020); - assign _zz_446 = _zz_88; - assign _zz_447 = (_zz_467 == _zz_468); - assign _zz_448 = (_zz_469 == _zz_470); - assign _zz_449 = 1'b0; - assign _zz_450 = (_zz_471 != 1'b0); - assign _zz_451 = (_zz_472 != _zz_473); - assign _zz_452 = {_zz_474,{_zz_475,_zz_476}}; - assign _zz_453 = 32'h00000030; - assign _zz_454 = 32'h02000020; - assign _zz_455 = 32'h00001030; - assign _zz_456 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_457 = 32'h00002020; - assign _zz_458 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_459 = 32'h00000020; - assign _zz_460 = 32'h00001010; - assign _zz_461 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_462 = 32'h00002010; - assign _zz_463 = ((decode_INSTRUCTION & _zz_477) == 32'h00000010); - assign _zz_464 = (_zz_478 == _zz_479); - assign _zz_465 = (_zz_480 == _zz_481); - assign _zz_466 = 32'h00000070; - assign _zz_467 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_468 = 32'h0; - assign _zz_469 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_470 = 32'h00004010; - assign _zz_471 = ((decode_INSTRUCTION & _zz_482) == 32'h00002010); - assign _zz_472 = {_zz_483,{_zz_484,_zz_485}}; - assign _zz_473 = 4'b0000; - assign _zz_474 = (_zz_486 != 1'b0); - assign _zz_475 = (_zz_487 != _zz_488); - assign _zz_476 = {_zz_489,{_zz_490,_zz_491}}; - assign _zz_477 = 32'h00000050; - assign _zz_478 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_479 = 32'h00000004; - assign _zz_480 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_481 = 32'h0; - assign _zz_482 = 32'h00006014; - assign _zz_483 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_484 = ((decode_INSTRUCTION & _zz_492) == 32'h0); - assign _zz_485 = {(_zz_493 == _zz_494),(_zz_495 == _zz_496)}; - assign _zz_486 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_487 = {(_zz_497 == _zz_498),{_zz_499,_zz_500}}; - assign _zz_488 = 3'b000; - assign _zz_489 = ({_zz_501,_zz_87} != 2'b00); - assign _zz_490 = ({_zz_502,_zz_503} != 2'b00); - assign _zz_491 = (_zz_504 != 1'b0); - assign _zz_492 = 32'h00000018; - assign _zz_493 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_494 = 32'h00002000; - assign _zz_495 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_496 = 32'h00001000; - assign _zz_497 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_498 = 32'h00000040; - assign _zz_499 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_500 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_501 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_502 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_503 = _zz_87; - assign _zz_504 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); - assign _zz_505 = execute_INSTRUCTION[31]; - assign _zz_506 = execute_INSTRUCTION[31]; - assign _zz_507 = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_323) begin - _zz_193 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_324) begin - _zz_194 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_42) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_IS_RS2_SIGNED = (decode_INSTRUCTION & 32'h02004064); + assign _zz__zz_decode_IS_RS2_SIGNED_1 = 32'h02004020; + assign _zz__zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz__zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_4 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_5 = (((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_6) == 32'h10000050) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_7 = ({_zz__zz_decode_IS_RS2_SIGNED_8,_zz__zz_decode_IS_RS2_SIGNED_9} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_10 = {({_zz__zz_decode_IS_RS2_SIGNED_11,_zz__zz_decode_IS_RS2_SIGNED_12} != 2'b00),{(_zz__zz_decode_IS_RS2_SIGNED_14 != _zz__zz_decode_IS_RS2_SIGNED_16),{_zz__zz_decode_IS_RS2_SIGNED_17,{_zz__zz_decode_IS_RS2_SIGNED_20,_zz__zz_decode_IS_RS2_SIGNED_28}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_6 = 32'h10403050; + assign _zz__zz_decode_IS_RS2_SIGNED_8 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz__zz_decode_IS_RS2_SIGNED_9 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz__zz_decode_IS_RS2_SIGNED_11 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_12 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_13) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_14 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_15) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_16 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_17 = ({_zz__zz_decode_IS_RS2_SIGNED_18,_zz__zz_decode_IS_RS2_SIGNED_19} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_20 = ({_zz__zz_decode_IS_RS2_SIGNED_21,_zz__zz_decode_IS_RS2_SIGNED_23} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_28 = {(_zz__zz_decode_IS_RS2_SIGNED_29 != _zz__zz_decode_IS_RS2_SIGNED_31),{_zz__zz_decode_IS_RS2_SIGNED_32,{_zz__zz_decode_IS_RS2_SIGNED_35,_zz__zz_decode_IS_RS2_SIGNED_37}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_13 = 32'h0000001c; + assign _zz__zz_decode_IS_RS2_SIGNED_15 = 32'h00000058; + assign _zz__zz_decode_IS_RS2_SIGNED_18 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz__zz_decode_IS_RS2_SIGNED_19 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz__zz_decode_IS_RS2_SIGNED_21 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_22) == 32'h40001010); + assign _zz__zz_decode_IS_RS2_SIGNED_23 = {(_zz__zz_decode_IS_RS2_SIGNED_24 == _zz__zz_decode_IS_RS2_SIGNED_25),(_zz__zz_decode_IS_RS2_SIGNED_26 == _zz__zz_decode_IS_RS2_SIGNED_27)}; + assign _zz__zz_decode_IS_RS2_SIGNED_29 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_30) == 32'h00000024); + assign _zz__zz_decode_IS_RS2_SIGNED_31 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_32 = ((_zz__zz_decode_IS_RS2_SIGNED_33 == _zz__zz_decode_IS_RS2_SIGNED_34) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_35 = (_zz__zz_decode_IS_RS2_SIGNED_36 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_37 = {(_zz__zz_decode_IS_RS2_SIGNED_38 != _zz__zz_decode_IS_RS2_SIGNED_43),{_zz__zz_decode_IS_RS2_SIGNED_44,{_zz__zz_decode_IS_RS2_SIGNED_47,_zz__zz_decode_IS_RS2_SIGNED_52}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_22 = 32'h40003054; + assign _zz__zz_decode_IS_RS2_SIGNED_24 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_RS2_SIGNED_25 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_26 = (decode_INSTRUCTION & 32'h02007054); + assign _zz__zz_decode_IS_RS2_SIGNED_27 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_30 = 32'h00000064; + assign _zz__zz_decode_IS_RS2_SIGNED_33 = (decode_INSTRUCTION & 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_34 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_36 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_38 = {(_zz__zz_decode_IS_RS2_SIGNED_39 == _zz__zz_decode_IS_RS2_SIGNED_40),(_zz__zz_decode_IS_RS2_SIGNED_41 == _zz__zz_decode_IS_RS2_SIGNED_42)}; + assign _zz__zz_decode_IS_RS2_SIGNED_43 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_44 = ((_zz__zz_decode_IS_RS2_SIGNED_45 == _zz__zz_decode_IS_RS2_SIGNED_46) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_47 = ({_zz__zz_decode_IS_RS2_SIGNED_48,_zz__zz_decode_IS_RS2_SIGNED_50} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_52 = {(_zz__zz_decode_IS_RS2_SIGNED_53 != _zz__zz_decode_IS_RS2_SIGNED_60),{_zz__zz_decode_IS_RS2_SIGNED_61,{_zz__zz_decode_IS_RS2_SIGNED_64,_zz__zz_decode_IS_RS2_SIGNED_77}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_39 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_40 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_41 = (decode_INSTRUCTION & 32'h00005000); + assign _zz__zz_decode_IS_RS2_SIGNED_42 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_45 = (decode_INSTRUCTION & 32'h00004048); + assign _zz__zz_decode_IS_RS2_SIGNED_46 = 32'h00004008; + assign _zz__zz_decode_IS_RS2_SIGNED_48 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_49) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_50 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_51) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_53 = {(_zz__zz_decode_IS_RS2_SIGNED_54 == _zz__zz_decode_IS_RS2_SIGNED_55),{_zz__zz_decode_IS_RS2_SIGNED_56,_zz__zz_decode_IS_RS2_SIGNED_58}}; + assign _zz__zz_decode_IS_RS2_SIGNED_60 = 3'b000; + assign _zz__zz_decode_IS_RS2_SIGNED_61 = ((_zz__zz_decode_IS_RS2_SIGNED_62 == _zz__zz_decode_IS_RS2_SIGNED_63) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_64 = ({_zz__zz_decode_IS_RS2_SIGNED_65,_zz__zz_decode_IS_RS2_SIGNED_68} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_77 = {(_zz__zz_decode_IS_RS2_SIGNED_78 != _zz__zz_decode_IS_RS2_SIGNED_91),{_zz__zz_decode_IS_RS2_SIGNED_92,{_zz__zz_decode_IS_RS2_SIGNED_109,_zz__zz_decode_IS_RS2_SIGNED_114}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_49 = 32'h00000034; + assign _zz__zz_decode_IS_RS2_SIGNED_51 = 32'h00000064; + assign _zz__zz_decode_IS_RS2_SIGNED_54 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_55 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_56 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_57) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_58 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_59) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_62 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_63 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_65 = (_zz__zz_decode_IS_RS2_SIGNED_66 == _zz__zz_decode_IS_RS2_SIGNED_67); + assign _zz__zz_decode_IS_RS2_SIGNED_68 = {_zz_decode_IS_RS2_SIGNED_2,{_zz__zz_decode_IS_RS2_SIGNED_69,_zz__zz_decode_IS_RS2_SIGNED_72}}; + assign _zz__zz_decode_IS_RS2_SIGNED_78 = {_zz_decode_IS_RS2_SIGNED_2,{_zz__zz_decode_IS_RS2_SIGNED_79,_zz__zz_decode_IS_RS2_SIGNED_82}}; + assign _zz__zz_decode_IS_RS2_SIGNED_91 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_92 = ({_zz__zz_decode_IS_RS2_SIGNED_93,_zz__zz_decode_IS_RS2_SIGNED_94} != 6'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_109 = (_zz__zz_decode_IS_RS2_SIGNED_110 != _zz__zz_decode_IS_RS2_SIGNED_113); + assign _zz__zz_decode_IS_RS2_SIGNED_114 = {_zz__zz_decode_IS_RS2_SIGNED_115,{_zz__zz_decode_IS_RS2_SIGNED_120,_zz__zz_decode_IS_RS2_SIGNED_125}}; + assign _zz__zz_decode_IS_RS2_SIGNED_57 = 32'h00000038; + assign _zz__zz_decode_IS_RS2_SIGNED_59 = 32'h00403040; + assign _zz__zz_decode_IS_RS2_SIGNED_66 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_67 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_69 = (_zz__zz_decode_IS_RS2_SIGNED_70 == _zz__zz_decode_IS_RS2_SIGNED_71); + assign _zz__zz_decode_IS_RS2_SIGNED_72 = {_zz__zz_decode_IS_RS2_SIGNED_73,_zz__zz_decode_IS_RS2_SIGNED_75}; + assign _zz__zz_decode_IS_RS2_SIGNED_79 = (_zz__zz_decode_IS_RS2_SIGNED_80 == _zz__zz_decode_IS_RS2_SIGNED_81); + assign _zz__zz_decode_IS_RS2_SIGNED_82 = {_zz__zz_decode_IS_RS2_SIGNED_83,{_zz__zz_decode_IS_RS2_SIGNED_85,_zz__zz_decode_IS_RS2_SIGNED_88}}; + assign _zz__zz_decode_IS_RS2_SIGNED_93 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_94 = {_zz__zz_decode_IS_RS2_SIGNED_95,{_zz__zz_decode_IS_RS2_SIGNED_97,_zz__zz_decode_IS_RS2_SIGNED_100}}; + assign _zz__zz_decode_IS_RS2_SIGNED_110 = {_zz_decode_IS_RS2_SIGNED_2,_zz__zz_decode_IS_RS2_SIGNED_111}; + assign _zz__zz_decode_IS_RS2_SIGNED_113 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_115 = ({_zz__zz_decode_IS_RS2_SIGNED_116,_zz__zz_decode_IS_RS2_SIGNED_117} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_120 = (_zz__zz_decode_IS_RS2_SIGNED_121 != _zz__zz_decode_IS_RS2_SIGNED_124); + assign _zz__zz_decode_IS_RS2_SIGNED_125 = {_zz__zz_decode_IS_RS2_SIGNED_126,{_zz__zz_decode_IS_RS2_SIGNED_129,_zz__zz_decode_IS_RS2_SIGNED_140}}; + assign _zz__zz_decode_IS_RS2_SIGNED_70 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_IS_RS2_SIGNED_71 = 32'h00004020; + assign _zz__zz_decode_IS_RS2_SIGNED_73 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_74) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_75 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_76) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_80 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_IS_RS2_SIGNED_81 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_83 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_84) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_85 = (_zz__zz_decode_IS_RS2_SIGNED_86 == _zz__zz_decode_IS_RS2_SIGNED_87); + assign _zz__zz_decode_IS_RS2_SIGNED_88 = (_zz__zz_decode_IS_RS2_SIGNED_89 == _zz__zz_decode_IS_RS2_SIGNED_90); + assign _zz__zz_decode_IS_RS2_SIGNED_95 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_96) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_97 = (_zz__zz_decode_IS_RS2_SIGNED_98 == _zz__zz_decode_IS_RS2_SIGNED_99); + assign _zz__zz_decode_IS_RS2_SIGNED_100 = {_zz__zz_decode_IS_RS2_SIGNED_101,{_zz__zz_decode_IS_RS2_SIGNED_103,_zz__zz_decode_IS_RS2_SIGNED_106}}; + assign _zz__zz_decode_IS_RS2_SIGNED_111 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_112) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_116 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_117 = (_zz__zz_decode_IS_RS2_SIGNED_118 == _zz__zz_decode_IS_RS2_SIGNED_119); + assign _zz__zz_decode_IS_RS2_SIGNED_121 = (_zz__zz_decode_IS_RS2_SIGNED_122 == _zz__zz_decode_IS_RS2_SIGNED_123); + assign _zz__zz_decode_IS_RS2_SIGNED_124 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_126 = (_zz__zz_decode_IS_RS2_SIGNED_127 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_129 = (_zz__zz_decode_IS_RS2_SIGNED_130 != _zz__zz_decode_IS_RS2_SIGNED_139); + assign _zz__zz_decode_IS_RS2_SIGNED_140 = {_zz__zz_decode_IS_RS2_SIGNED_141,{_zz__zz_decode_IS_RS2_SIGNED_143,_zz__zz_decode_IS_RS2_SIGNED_150}}; + assign _zz__zz_decode_IS_RS2_SIGNED_74 = 32'h00000030; + assign _zz__zz_decode_IS_RS2_SIGNED_76 = 32'h02000020; + assign _zz__zz_decode_IS_RS2_SIGNED_84 = 32'h00001030; + assign _zz__zz_decode_IS_RS2_SIGNED_86 = (decode_INSTRUCTION & 32'h02002060); + assign _zz__zz_decode_IS_RS2_SIGNED_87 = 32'h00002020; + assign _zz__zz_decode_IS_RS2_SIGNED_89 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_IS_RS2_SIGNED_90 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_96 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_98 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_99 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_101 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_102) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_103 = (_zz__zz_decode_IS_RS2_SIGNED_104 == _zz__zz_decode_IS_RS2_SIGNED_105); + assign _zz__zz_decode_IS_RS2_SIGNED_106 = (_zz__zz_decode_IS_RS2_SIGNED_107 == _zz__zz_decode_IS_RS2_SIGNED_108); + assign _zz__zz_decode_IS_RS2_SIGNED_112 = 32'h00000070; + assign _zz__zz_decode_IS_RS2_SIGNED_118 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_119 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_122 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_IS_RS2_SIGNED_123 = 32'h00004010; + assign _zz__zz_decode_IS_RS2_SIGNED_127 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_128) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_130 = {_zz__zz_decode_IS_RS2_SIGNED_131,{_zz__zz_decode_IS_RS2_SIGNED_132,_zz__zz_decode_IS_RS2_SIGNED_134}}; + assign _zz__zz_decode_IS_RS2_SIGNED_139 = 4'b0000; + assign _zz__zz_decode_IS_RS2_SIGNED_141 = (_zz__zz_decode_IS_RS2_SIGNED_142 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_143 = (_zz__zz_decode_IS_RS2_SIGNED_144 != _zz__zz_decode_IS_RS2_SIGNED_149); + assign _zz__zz_decode_IS_RS2_SIGNED_150 = {_zz__zz_decode_IS_RS2_SIGNED_151,{_zz__zz_decode_IS_RS2_SIGNED_153,_zz__zz_decode_IS_RS2_SIGNED_156}}; + assign _zz__zz_decode_IS_RS2_SIGNED_102 = 32'h00000050; + assign _zz__zz_decode_IS_RS2_SIGNED_104 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz__zz_decode_IS_RS2_SIGNED_105 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_107 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_RS2_SIGNED_108 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_128 = 32'h00006014; + assign _zz__zz_decode_IS_RS2_SIGNED_131 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_132 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_133) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_134 = {(_zz__zz_decode_IS_RS2_SIGNED_135 == _zz__zz_decode_IS_RS2_SIGNED_136),(_zz__zz_decode_IS_RS2_SIGNED_137 == _zz__zz_decode_IS_RS2_SIGNED_138)}; + assign _zz__zz_decode_IS_RS2_SIGNED_142 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_144 = {(_zz__zz_decode_IS_RS2_SIGNED_145 == _zz__zz_decode_IS_RS2_SIGNED_146),{_zz__zz_decode_IS_RS2_SIGNED_147,_zz__zz_decode_IS_RS2_SIGNED_148}}; + assign _zz__zz_decode_IS_RS2_SIGNED_149 = 3'b000; + assign _zz__zz_decode_IS_RS2_SIGNED_151 = ({_zz__zz_decode_IS_RS2_SIGNED_152,_zz_decode_IS_RS2_SIGNED_1} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_153 = ({_zz__zz_decode_IS_RS2_SIGNED_154,_zz__zz_decode_IS_RS2_SIGNED_155} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_156 = (_zz__zz_decode_IS_RS2_SIGNED_157 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_133 = 32'h00000018; + assign _zz__zz_decode_IS_RS2_SIGNED_135 = (decode_INSTRUCTION & 32'h00006004); + assign _zz__zz_decode_IS_RS2_SIGNED_136 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_137 = (decode_INSTRUCTION & 32'h00005004); + assign _zz__zz_decode_IS_RS2_SIGNED_138 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_145 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_RS2_SIGNED_146 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_147 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_148 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz__zz_decode_IS_RS2_SIGNED_152 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_154 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_155 = _zz_decode_IS_RS2_SIGNED_1; + assign _zz__zz_decode_IS_RS2_SIGNED_157 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_165 ), //i - .io_cpu_prefetch_isValid (_zz_166 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_167 ), //i - .io_cpu_fetch_isStuck (_zz_168 ), //i - .io_cpu_fetch_isRemoved (_zz_169 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_170 ), //i - .io_cpu_decode_isStuck (_zz_171 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_172 ), //i - .io_cpu_fill_valid (_zz_173 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_174 ), //i - .io_cpu_execute_address (_zz_175[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_81[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_176 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_177[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_178 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_179 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_180 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_181[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_182 ), //i - .io_cpu_writeBack_fence_SR (_zz_183 ), //i - .io_cpu_writeBack_fence_SO (_zz_184 ), //i - .io_cpu_writeBack_fence_SI (_zz_185 ), //i - .io_cpu_writeBack_fence_PW (_zz_186 ), //i - .io_cpu_writeBack_fence_PR (_zz_187 ), //i - .io_cpu_writeBack_fence_PO (_zz_188 ), //i - .io_cpu_writeBack_fence_PI (_zz_189 ), //i - .io_cpu_writeBack_fence_FM (_zz_190[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_191 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_192 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_325) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) 2'b00 : begin - _zz_195 = DBusCachedPlugin_redoBranch_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_195 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_195 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + end + 2'b01 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + end + 2'b10 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; end default : begin - _zz_195 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_30) - `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; - default : _zz_30_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_33) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; - default : _zz_33_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_34) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; - default : _zz_34_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_36) - `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; - default : _zz_36_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_37) - `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; - default : _zz_37_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_38) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; - default : _zz_38_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_39) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; - default : _zz_39_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_43) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; - default : _zz_43_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; - default : _zz_44_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_45) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; - default : _zz_45_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_46) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; - default : _zz_46_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_47) - `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; - default : _zz_47_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_48) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; - default : _zz_48_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_49) - `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; - default : _zz_49_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_91) - `Src1CtrlEnum_defaultEncoding_RS : _zz_91_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_91_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_91_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_91_string = "URS1 "; - default : _zz_91_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_92) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_92_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_92_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_92_string = "BITWISE "; - default : _zz_92_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_93) - `Src2CtrlEnum_defaultEncoding_RS : _zz_93_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_93_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_93_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_93_string = "PC "; - default : _zz_93_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_94) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_94_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_94_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_94_string = "AND_1"; - default : _zz_94_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_95) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_95_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_95_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_95_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_95_string = "SRA_1 "; - default : _zz_95_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_96) - `BranchCtrlEnum_defaultEncoding_INC : _zz_96_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_96_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_96_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_96_string = "JALR"; - default : _zz_96_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_97) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_97_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_97_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_97_string = "ECALL"; - default : _zz_97_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_231) + $signed(_zz_239)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2356,44 +2448,44 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_241; - assign execute_REGFILE_WRITE_DATA = _zz_99; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_175[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_243[0]; - assign decode_IS_RS1_SIGNED = _zz_244[0]; - assign decode_IS_DIV = _zz_245[0]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_RS2_SIGNED[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_RS2_SIGNED[30]; + assign decode_IS_DIV = _zz_decode_IS_RS2_SIGNED[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_246[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_247[0]; - assign _zz_8 = _zz_9; - assign _zz_10 = _zz_11; - assign decode_SHIFT_CTRL = _zz_12; - assign _zz_13 = _zz_14; - assign decode_ALU_BITWISE_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_248[0]; - assign decode_MEMORY_MANAGMENT = _zz_249[0]; + assign decode_IS_MUL = _zz_decode_IS_RS2_SIGNED[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_RS2_SIGNED[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_RS2_SIGNED[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_RS2_SIGNED[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_250[0]; + assign decode_MEMORY_WR = _zz_decode_IS_RS2_SIGNED[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_251[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_252[0]; - assign decode_SRC2_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_ALU_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_SRC1_CTRL = _zz_24; - assign _zz_25 = _zz_26; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_RS2_SIGNED[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_RS2_SIGNED[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; @@ -2413,22 +2505,22 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27; - assign execute_ENV_CTRL = _zz_28; - assign writeBack_ENV_CTRL = _zz_29; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_121; - assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_253[0]; - assign decode_RS1_USE = _zz_254[0]; - always @ (*) begin - _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_196)begin - _zz_31 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_RS2_SIGNED[15]; + assign decode_RS1_USE = _zz_decode_IS_RS2_SIGNED[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2438,139 +2530,139 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_110)begin - if((_zz_111 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_112; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_197)begin - if(_zz_198)begin - if(_zz_114)begin - decode_RS2 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_199)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_116)begin - decode_RS2 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_200)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_118)begin - decode_RS2 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_110)begin - if((_zz_111 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_112; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_197)begin - if(_zz_198)begin - if(_zz_113)begin - decode_RS1 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_199)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_115)begin - decode_RS1 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_200)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_117)begin - decode_RS1 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_32 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_32 = _zz_107; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_32 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_201)begin - _zz_32 = memory_DivPlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_33; - assign execute_SHIFT_CTRL = _zz_34; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_35 = execute_PC; - assign execute_SRC2_CTRL = _zz_36; - assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_255[0]; - assign decode_SRC_ADD_ZERO = _zz_256[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_RS2_SIGNED[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_RS2_SIGNED[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_38; - assign execute_SRC2 = _zz_105; - assign execute_SRC1 = _zz_100; - assign execute_ALU_BITWISE_CTRL = _zz_39; - assign _zz_40 = writeBack_INSTRUCTION; - assign _zz_41 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_42 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_42 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_257[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_RS2_SIGNED[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_326) == 32'h00001073),{(_zz_327 == _zz_328),{_zz_329,{_zz_330,_zz_331}}}}}}} != 21'h0); - always @ (*) begin - _zz_50 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_50 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 21'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_230) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_50 = _zz_299; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_50 = _zz_300; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2582,201 +2674,201 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_258[0]; - assign decode_FLUSH_ALL = _zz_259[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_IS_RS2_SIGNED[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_RS2_SIGNED[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_202)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_203)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_204)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_205)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_51; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_52 = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_52 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_53 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_108 || _zz_109)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_206)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_206)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_191 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_196)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_201)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_207)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_208)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2785,45 +2877,47 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_207)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_208)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; assign CsrPlugin_inWfi = 1'b0; assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_207)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_208)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_207)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_208)begin - case(_zz_209) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2836,59 +2930,65 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_54 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_55 = (_zz_54 & (~ _zz_260)); - assign _zz_56 = _zz_55[3]; - assign _zz_57 = (_zz_55[1] || _zz_56); - assign _zz_58 = (_zz_55[2] || _zz_56); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_195; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_262); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -2896,265 +2996,286 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_59 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_59); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_59); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_60); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_60); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_61); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_61); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_62; - assign _zz_62 = ((1'b0 && (! _zz_63)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_63 = _zz_64; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_63; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_65)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_65 = _zz_66; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_65; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_67; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_68 = _zz_263[11]; - always @ (*) begin - _zz_69[18] = _zz_68; - _zz_69[17] = _zz_68; - _zz_69[16] = _zz_68; - _zz_69[15] = _zz_68; - _zz_69[14] = _zz_68; - _zz_69[13] = _zz_68; - _zz_69[12] = _zz_68; - _zz_69[11] = _zz_68; - _zz_69[10] = _zz_68; - _zz_69[9] = _zz_68; - _zz_69[8] = _zz_68; - _zz_69[7] = _zz_68; - _zz_69[6] = _zz_68; - _zz_69[5] = _zz_68; - _zz_69[4] = _zz_68; - _zz_69[3] = _zz_68; - _zz_69[2] = _zz_68; - _zz_69[1] = _zz_68; - _zz_69[0] = _zz_68; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_264[31])); - if(_zz_74)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_70 = _zz_265[19]; - always @ (*) begin - _zz_71[10] = _zz_70; - _zz_71[9] = _zz_70; - _zz_71[8] = _zz_70; - _zz_71[7] = _zz_70; - _zz_71[6] = _zz_70; - _zz_71[5] = _zz_70; - _zz_71[4] = _zz_70; - _zz_71[3] = _zz_70; - _zz_71[2] = _zz_70; - _zz_71[1] = _zz_70; - _zz_71[0] = _zz_70; - end - - assign _zz_72 = _zz_266[11]; - always @ (*) begin - _zz_73[18] = _zz_72; - _zz_73[17] = _zz_72; - _zz_73[16] = _zz_72; - _zz_73[15] = _zz_72; - _zz_73[14] = _zz_72; - _zz_73[13] = _zz_72; - _zz_73[12] = _zz_72; - _zz_73[11] = _zz_72; - _zz_73[10] = _zz_72; - _zz_73[9] = _zz_72; - _zz_73[8] = _zz_72; - _zz_73[7] = _zz_72; - _zz_73[6] = _zz_72; - _zz_73[5] = _zz_72; - _zz_73[4] = _zz_72; - _zz_73[3] = _zz_72; - _zz_73[2] = _zz_72; - _zz_73[1] = _zz_72; - _zz_73[0] = _zz_72; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_74 = _zz_267[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_74 = _zz_268[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_75 = _zz_269[19]; - always @ (*) begin - _zz_76[10] = _zz_75; - _zz_76[9] = _zz_75; - _zz_76[8] = _zz_75; - _zz_76[7] = _zz_75; - _zz_76[6] = _zz_75; - _zz_76[5] = _zz_75; - _zz_76[4] = _zz_75; - _zz_76[3] = _zz_75; - _zz_76[2] = _zz_75; - _zz_76[1] = _zz_75; - _zz_76[0] = _zz_75; - end - - assign _zz_77 = _zz_270[11]; - always @ (*) begin - _zz_78[18] = _zz_77; - _zz_78[17] = _zz_77; - _zz_78[16] = _zz_77; - _zz_78[15] = _zz_77; - _zz_78[14] = _zz_77; - _zz_78[13] = _zz_77; - _zz_78[12] = _zz_77; - _zz_78[11] = _zz_77; - _zz_78[10] = _zz_77; - _zz_78[9] = _zz_77; - _zz_78[8] = _zz_77; - _zz_78[7] = _zz_77; - _zz_78[6] = _zz_77; - _zz_78[5] = _zz_77; - _zz_78[4] = _zz_77; - _zz_78[3] = _zz_77; - _zz_78[2] = _zz_77; - _zz_78[1] = _zz_77; - _zz_78[0] = _zz_77; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_76,{{{_zz_344,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_78,{{{_zz_345,_zz_346},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_166 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_167 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_168 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_167; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_170 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_171 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_172 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_205)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_203)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_173 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_203)begin - _zz_173 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_204)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_202)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_204)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_202)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_165 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_192 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3162,168 +3283,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_174 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_175 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_81 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_81 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_81 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_191 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_176 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_177 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_176; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_177; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_178 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_178 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_179 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_180 = (CsrPlugin_privilege == 2'b00); - assign _zz_181 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_210)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_210)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_210)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_271}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_272}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; end - assign _zz_82 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_83[31] = _zz_82; - _zz_83[30] = _zz_82; - _zz_83[29] = _zz_82; - _zz_83[28] = _zz_82; - _zz_83[27] = _zz_82; - _zz_83[26] = _zz_82; - _zz_83[25] = _zz_82; - _zz_83[24] = _zz_82; - _zz_83[23] = _zz_82; - _zz_83[22] = _zz_82; - _zz_83[21] = _zz_82; - _zz_83[20] = _zz_82; - _zz_83[19] = _zz_82; - _zz_83[18] = _zz_82; - _zz_83[17] = _zz_82; - _zz_83[16] = _zz_82; - _zz_83[15] = _zz_82; - _zz_83[14] = _zz_82; - _zz_83[13] = _zz_82; - _zz_83[12] = _zz_82; - _zz_83[11] = _zz_82; - _zz_83[10] = _zz_82; - _zz_83[9] = _zz_82; - _zz_83[8] = _zz_82; - _zz_83[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_84 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_85[31] = _zz_84; - _zz_85[30] = _zz_84; - _zz_85[29] = _zz_84; - _zz_85[28] = _zz_84; - _zz_85[27] = _zz_84; - _zz_85[26] = _zz_84; - _zz_85[25] = _zz_84; - _zz_85[24] = _zz_84; - _zz_85[23] = _zz_84; - _zz_85[22] = _zz_84; - _zz_85[21] = _zz_84; - _zz_85[20] = _zz_84; - _zz_85[19] = _zz_84; - _zz_85[18] = _zz_84; - _zz_85[17] = _zz_84; - _zz_85[16] = _zz_84; - _zz_85[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_228) + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_83; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_85; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3342,59 +3474,60 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_87 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_88 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_89 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_90 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_86 = {(_zz_90 != 1'b0),{(_zz_90 != 1'b0),{((_zz_347 == _zz_348) != 1'b0),{(_zz_349 != 1'b0),{(_zz_350 != _zz_351),{_zz_352,{_zz_353,_zz_354}}}}}}}; - assign _zz_91 = _zz_86[2 : 1]; - assign _zz_49 = _zz_91; - assign _zz_92 = _zz_86[7 : 6]; - assign _zz_48 = _zz_92; - assign _zz_93 = _zz_86[9 : 8]; - assign _zz_47 = _zz_93; - assign _zz_94 = _zz_86[19 : 18]; - assign _zz_46 = _zz_94; - assign _zz_95 = _zz_86[22 : 21]; - assign _zz_45 = _zz_95; - assign _zz_96 = _zz_86[24 : 23]; - assign _zz_44 = _zz_96; - assign _zz_97 = _zz_86[27 : 26]; - assign _zz_43 = _zz_97; + assign _zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_RS2_SIGNED_4 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_IS_RS2_SIGNED = {(_zz_decode_IS_RS2_SIGNED_4 != 1'b0),{(_zz_decode_IS_RS2_SIGNED_4 != 1'b0),{((_zz__zz_decode_IS_RS2_SIGNED == _zz__zz_decode_IS_RS2_SIGNED_1) != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_2 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_3 != _zz__zz_decode_IS_RS2_SIGNED_4),{_zz__zz_decode_IS_RS2_SIGNED_5,{_zz__zz_decode_IS_RS2_SIGNED_7,_zz__zz_decode_IS_RS2_SIGNED_10}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_RS2_SIGNED[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_RS2_SIGNED[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_RS2_SIGNED[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_RS2_SIGNED[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_RS2_SIGNED[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_RS2_SIGNED[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_RS2_SIGNED[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_193; - assign decode_RegFilePlugin_rs2Data = _zz_194; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); - if(_zz_98)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; - if(_zz_98)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_50; - if(_zz_98)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3403,355 +3536,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_99 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_99 = {31'd0, _zz_273}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_99 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_100 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_100 = {29'd0, _zz_274}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_100 = {27'd0, _zz_275}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_101 = _zz_276[11]; - always @ (*) begin - _zz_102[19] = _zz_101; - _zz_102[18] = _zz_101; - _zz_102[17] = _zz_101; - _zz_102[16] = _zz_101; - _zz_102[15] = _zz_101; - _zz_102[14] = _zz_101; - _zz_102[13] = _zz_101; - _zz_102[12] = _zz_101; - _zz_102[11] = _zz_101; - _zz_102[10] = _zz_101; - _zz_102[9] = _zz_101; - _zz_102[8] = _zz_101; - _zz_102[7] = _zz_101; - _zz_102[6] = _zz_101; - _zz_102[5] = _zz_101; - _zz_102[4] = _zz_101; - _zz_102[3] = _zz_101; - _zz_102[2] = _zz_101; - _zz_102[1] = _zz_101; - _zz_102[0] = _zz_101; - end - - assign _zz_103 = _zz_277[11]; - always @ (*) begin - _zz_104[19] = _zz_103; - _zz_104[18] = _zz_103; - _zz_104[17] = _zz_103; - _zz_104[16] = _zz_103; - _zz_104[15] = _zz_103; - _zz_104[14] = _zz_103; - _zz_104[13] = _zz_103; - _zz_104[12] = _zz_103; - _zz_104[11] = _zz_103; - _zz_104[10] = _zz_103; - _zz_104[9] = _zz_103; - _zz_104[8] = _zz_103; - _zz_104[7] = _zz_103; - _zz_104[6] = _zz_103; - _zz_104[5] = _zz_103; - _zz_104[4] = _zz_103; - _zz_104[3] = _zz_103; - _zz_104[2] = _zz_103; - _zz_104[1] = _zz_103; - _zz_104[0] = _zz_103; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_105 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_105 = {_zz_104,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_105 = _zz_35; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_278; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_106[0] = execute_SRC1[31]; - _zz_106[1] = execute_SRC1[30]; - _zz_106[2] = execute_SRC1[29]; - _zz_106[3] = execute_SRC1[28]; - _zz_106[4] = execute_SRC1[27]; - _zz_106[5] = execute_SRC1[26]; - _zz_106[6] = execute_SRC1[25]; - _zz_106[7] = execute_SRC1[24]; - _zz_106[8] = execute_SRC1[23]; - _zz_106[9] = execute_SRC1[22]; - _zz_106[10] = execute_SRC1[21]; - _zz_106[11] = execute_SRC1[20]; - _zz_106[12] = execute_SRC1[19]; - _zz_106[13] = execute_SRC1[18]; - _zz_106[14] = execute_SRC1[17]; - _zz_106[15] = execute_SRC1[16]; - _zz_106[16] = execute_SRC1[15]; - _zz_106[17] = execute_SRC1[14]; - _zz_106[18] = execute_SRC1[13]; - _zz_106[19] = execute_SRC1[12]; - _zz_106[20] = execute_SRC1[11]; - _zz_106[21] = execute_SRC1[10]; - _zz_106[22] = execute_SRC1[9]; - _zz_106[23] = execute_SRC1[8]; - _zz_106[24] = execute_SRC1[7]; - _zz_106[25] = execute_SRC1[6]; - _zz_106[26] = execute_SRC1[5]; - _zz_106[27] = execute_SRC1[4]; - _zz_106[28] = execute_SRC1[3]; - _zz_106[29] = execute_SRC1[2]; - _zz_106[30] = execute_SRC1[1]; - _zz_106[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_106 : execute_SRC1); - always @ (*) begin - _zz_107[0] = memory_SHIFT_RIGHT[31]; - _zz_107[1] = memory_SHIFT_RIGHT[30]; - _zz_107[2] = memory_SHIFT_RIGHT[29]; - _zz_107[3] = memory_SHIFT_RIGHT[28]; - _zz_107[4] = memory_SHIFT_RIGHT[27]; - _zz_107[5] = memory_SHIFT_RIGHT[26]; - _zz_107[6] = memory_SHIFT_RIGHT[25]; - _zz_107[7] = memory_SHIFT_RIGHT[24]; - _zz_107[8] = memory_SHIFT_RIGHT[23]; - _zz_107[9] = memory_SHIFT_RIGHT[22]; - _zz_107[10] = memory_SHIFT_RIGHT[21]; - _zz_107[11] = memory_SHIFT_RIGHT[20]; - _zz_107[12] = memory_SHIFT_RIGHT[19]; - _zz_107[13] = memory_SHIFT_RIGHT[18]; - _zz_107[14] = memory_SHIFT_RIGHT[17]; - _zz_107[15] = memory_SHIFT_RIGHT[16]; - _zz_107[16] = memory_SHIFT_RIGHT[15]; - _zz_107[17] = memory_SHIFT_RIGHT[14]; - _zz_107[18] = memory_SHIFT_RIGHT[13]; - _zz_107[19] = memory_SHIFT_RIGHT[12]; - _zz_107[20] = memory_SHIFT_RIGHT[11]; - _zz_107[21] = memory_SHIFT_RIGHT[10]; - _zz_107[22] = memory_SHIFT_RIGHT[9]; - _zz_107[23] = memory_SHIFT_RIGHT[8]; - _zz_107[24] = memory_SHIFT_RIGHT[7]; - _zz_107[25] = memory_SHIFT_RIGHT[6]; - _zz_107[26] = memory_SHIFT_RIGHT[5]; - _zz_107[27] = memory_SHIFT_RIGHT[4]; - _zz_107[28] = memory_SHIFT_RIGHT[3]; - _zz_107[29] = memory_SHIFT_RIGHT[2]; - _zz_107[30] = memory_SHIFT_RIGHT[1]; - _zz_107[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_108 = 1'b0; - if(_zz_211)begin - if(_zz_212)begin - if(_zz_113)begin - _zz_108 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_213)begin - if(_zz_214)begin - if(_zz_115)begin - _zz_108 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_215)begin - if(_zz_216)begin - if(_zz_117)begin - _zz_108 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_108 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_109 = 1'b0; - if(_zz_211)begin - if(_zz_212)begin - if(_zz_114)begin - _zz_109 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_213)begin - if(_zz_214)begin - if(_zz_116)begin - _zz_109 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_215)begin - if(_zz_216)begin - if(_zz_118)begin - _zz_109 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_109 = 1'b0; - end - end - - assign _zz_113 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_114 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_115 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_116 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_117 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_118 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_119 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_119 == 3'b000)) begin - _zz_120 = execute_BranchPlugin_eq; - end else if((_zz_119 == 3'b001)) begin - _zz_120 = (! execute_BranchPlugin_eq); - end else if((((_zz_119 & 3'b101) == 3'b101))) begin - _zz_120 = (! execute_SRC_LESS); - end else begin - _zz_120 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_121 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_121 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_121 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_121 = _zz_120; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_122 = _zz_285[11]; - always @ (*) begin - _zz_123[19] = _zz_122; - _zz_123[18] = _zz_122; - _zz_123[17] = _zz_122; - _zz_123[16] = _zz_122; - _zz_123[15] = _zz_122; - _zz_123[14] = _zz_122; - _zz_123[13] = _zz_122; - _zz_123[12] = _zz_122; - _zz_123[11] = _zz_122; - _zz_123[10] = _zz_122; - _zz_123[9] = _zz_122; - _zz_123[8] = _zz_122; - _zz_123[7] = _zz_122; - _zz_123[6] = _zz_122; - _zz_123[5] = _zz_122; - _zz_123[4] = _zz_122; - _zz_123[3] = _zz_122; - _zz_123[2] = _zz_122; - _zz_123[1] = _zz_122; - _zz_123[0] = _zz_122; - end - - assign _zz_124 = _zz_286[19]; - always @ (*) begin - _zz_125[10] = _zz_124; - _zz_125[9] = _zz_124; - _zz_125[8] = _zz_124; - _zz_125[7] = _zz_124; - _zz_125[6] = _zz_124; - _zz_125[5] = _zz_124; - _zz_125[4] = _zz_124; - _zz_125[3] = _zz_124; - _zz_125[2] = _zz_124; - _zz_125[1] = _zz_124; - _zz_125[0] = _zz_124; - end - - assign _zz_126 = _zz_287[11]; - always @ (*) begin - _zz_127[18] = _zz_126; - _zz_127[17] = _zz_126; - _zz_127[16] = _zz_126; - _zz_127[15] = _zz_126; - _zz_127[14] = _zz_126; - _zz_127[13] = _zz_126; - _zz_127[12] = _zz_126; - _zz_127[11] = _zz_126; - _zz_127[10] = _zz_126; - _zz_127[9] = _zz_126; - _zz_127[8] = _zz_126; - _zz_127[7] = _zz_126; - _zz_127[6] = _zz_126; - _zz_127[5] = _zz_126; - _zz_127[4] = _zz_126; - _zz_127[3] = _zz_126; - _zz_127[2] = _zz_126; - _zz_127[1] = _zz_126; - _zz_127[0] = _zz_126; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_128 = (_zz_288[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_128 = _zz_289[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_128 = _zz_290[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_128); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -3760,80 +3916,80 @@ module VexRiscv ( endcase end - assign _zz_129 = _zz_291[11]; - always @ (*) begin - _zz_130[19] = _zz_129; - _zz_130[18] = _zz_129; - _zz_130[17] = _zz_129; - _zz_130[16] = _zz_129; - _zz_130[15] = _zz_129; - _zz_130[14] = _zz_129; - _zz_130[13] = _zz_129; - _zz_130[12] = _zz_129; - _zz_130[11] = _zz_129; - _zz_130[10] = _zz_129; - _zz_130[9] = _zz_129; - _zz_130[8] = _zz_129; - _zz_130[7] = _zz_129; - _zz_130[6] = _zz_129; - _zz_130[5] = _zz_129; - _zz_130[4] = _zz_129; - _zz_130[3] = _zz_129; - _zz_130[2] = _zz_129; - _zz_130[1] = _zz_129; - _zz_130[0] = _zz_129; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_130,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_132,{{{_zz_505,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_134,{{{_zz_506,_zz_507},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_294}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_131 = _zz_292[19]; - always @ (*) begin - _zz_132[10] = _zz_131; - _zz_132[9] = _zz_131; - _zz_132[8] = _zz_131; - _zz_132[7] = _zz_131; - _zz_132[6] = _zz_131; - _zz_132[5] = _zz_131; - _zz_132[4] = _zz_131; - _zz_132[3] = _zz_131; - _zz_132[2] = _zz_131; - _zz_132[1] = _zz_131; - _zz_132[0] = _zz_131; - end - - assign _zz_133 = _zz_293[11]; - always @ (*) begin - _zz_134[18] = _zz_133; - _zz_134[17] = _zz_133; - _zz_134[16] = _zz_133; - _zz_134[15] = _zz_133; - _zz_134[14] = _zz_133; - _zz_134[13] = _zz_133; - _zz_134[12] = _zz_133; - _zz_134[11] = _zz_133; - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -3843,95 +3999,109 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_135 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_136 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_137 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_138 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_139 = _zz_295[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_206)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -3942,8 +4112,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3953,77 +4123,84 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_217)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_218)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_218)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4036,39 +4213,48 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_217)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_217)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_229) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_219) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4081,8 +4267,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_219) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4101,79 +4287,150 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_297) + $signed(_zz_298)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_201)begin - if(_zz_220)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_221)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_302); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_140 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_140[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_303); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_304 : _zz_305); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_306[31:0]; - assign _zz_141 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_142 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_143 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_144[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_144[31 : 0] = execute_RS1; - end - - assign _zz_146 = (_zz_145 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_146 != 32'h0); - assign _zz_26 = decode_SRC1_CTRL; - assign _zz_24 = _zz_49; - assign _zz_37 = decode_to_execute_SRC1_CTRL; - assign _zz_23 = decode_ALU_CTRL; - assign _zz_21 = _zz_48; - assign _zz_38 = decode_to_execute_ALU_CTRL; - assign _zz_20 = decode_SRC2_CTRL; - assign _zz_18 = _zz_47; - assign _zz_36 = decode_to_execute_SRC2_CTRL; - assign _zz_17 = decode_ALU_BITWISE_CTRL; - assign _zz_15 = _zz_46; - assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_14 = decode_SHIFT_CTRL; - assign _zz_11 = execute_SHIFT_CTRL; - assign _zz_12 = _zz_45; - assign _zz_34 = decode_to_execute_SHIFT_CTRL; - assign _zz_33 = execute_to_memory_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_51 = _zz_44; - assign _zz_30 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_43; - assign _zz_28 = decode_to_execute_ENV_CTRL; - assign _zz_27 = execute_to_memory_ENV_CTRL; - assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4194,140 +4451,159 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_147 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_147[12 : 0] = 13'h1000; - _zz_147[25 : 20] = 6'h20; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_148 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_148[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_148[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_148[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_149 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_149[11 : 11] = CsrPlugin_mip_MEIP; - _zz_149[7 : 7] = CsrPlugin_mip_MTIP; - _zz_149[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_150 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_150[11 : 11] = CsrPlugin_mie_MEIE; - _zz_150[7 : 7] = CsrPlugin_mie_MTIE; - _zz_150[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_151 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_151[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_152 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_152[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_152[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_153 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_153[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_154 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_154[31 : 0] = _zz_145; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_155 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_155[31 : 0] = _zz_146; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = ((((_zz_147 | _zz_148) | (_zz_149 | _zz_150)) | ((_zz_151 | _zz_152) | (_zz_153 | _zz_154))) | _zz_155); - assign iBusWishbone_ADR = {_zz_322,_zz_156}; - assign iBusWishbone_CTI = ((_zz_156 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = ((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))) | _zz_CsrPlugin_csrMapping_readDataInit_10); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_222)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_222)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_157; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_163 = (dBus_cmd_payload_length != 3'b000); - assign _zz_159 = dBus_cmd_valid; - assign _zz_161 = dBus_cmd_payload_wr; - assign _zz_162 = (_zz_158 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_160 && (_zz_161 || _zz_162)); - assign dBusWishbone_ADR = ((_zz_163 ? {{dBus_cmd_payload_address[31 : 5],_zz_158},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_163 ? (_zz_162 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_161 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_161; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_160 = (_zz_159 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_159; - assign dBusWishbone_STB = _zz_159; - assign dBus_rsp_valid = _zz_164; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_64 <= 1'b0; - _zz_66 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_79; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_80; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_98 <= 1'b1; - _zz_110 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -4345,158 +4621,158 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_145 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_156 <= 3'b000; - _zz_157 <= 1'b0; - _zz_158 <= 3'b000; - _zz_164 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_64 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_62)begin - _zz_64 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_66 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_66 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_223)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_98 <= 1'b0; - _zz_110 <= (_zz_41 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_224)begin - if(_zz_225)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_226)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_227)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_207)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4507,8 +4783,8 @@ module VexRiscv ( end endcase end - if(_zz_208)begin - case(_zz_209) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4518,135 +4794,135 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_137,{_zz_136,_zz_135}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_316[0]; - CsrPlugin_mstatus_MIE <= _zz_317[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_319[0]; - CsrPlugin_mie_MTIE <= _zz_320[0]; - CsrPlugin_mie_MSIE <= _zz_321[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_145 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_222)begin - if(iBusWishbone_ACK)begin - _zz_156 <= (_zz_156 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_157 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_159 && _zz_160))begin - _zz_158 <= (_zz_158 + 3'b001); - if(_zz_162)begin - _zz_158 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_164 <= ((_zz_159 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_67 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_223)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_111 <= _zz_40[11 : 7]; - _zz_112 <= _zz_50; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_206)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_139 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_139 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_224)begin - if(_zz_225)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_226)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_227)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_207)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -4654,258 +4930,258 @@ module VexRiscv ( end endcase end - if((memory_DivPlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_DivPlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_201)begin - if(_zz_220)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_307[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; end end end - if(_zz_221)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_143 ? (~ _zz_144) : _zz_144) + _zz_313); - memory_DivPlugin_rs2 <= ((_zz_142 ? (~ execute_RS2) : execute_RS2) + _zz_315); - memory_DivPlugin_div_needRevert <= ((_zz_143 ^ (_zz_142 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_35; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_7) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_25; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_22; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_19; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_10; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_49) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_50) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + if(when_Pipeline_l124_51) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + if(when_Pipeline_l124_52) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_53) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_54) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_318[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -4918,9 +5194,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -4942,6 +5217,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -4957,9 +5233,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -4967,7 +5244,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -4976,24 +5253,15 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -5018,40 +5286,48 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5061,23 +5337,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -5085,10 +5371,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -5100,59 +5394,54 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -5167,274 +5456,293 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -5442,89 +5750,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_16)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -5532,12 +5824,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -5548,20 +5840,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -5569,45 +5881,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -5618,46 +5932,37 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; @@ -5665,50 +5970,51 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -5758,13 +6064,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [21:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [21:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -5773,8 +6075,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -5788,22 +6095,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -5813,82 +6123,85 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - assign _zz_11 = (! lineLoader_flushCounter[7]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -5904,30 +6217,35 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -5935,51 +6253,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 8'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -5990,10 +6308,10 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v index 21879f2..27d99db 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v @@ -1,46 +1,46 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b10 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -81,37 +81,37 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_168; - wire _zz_169; - wire _zz_170; - wire _zz_171; - wire _zz_172; - wire _zz_173; - wire _zz_174; - wire _zz_175; - reg _zz_176; - wire _zz_177; - wire [31:0] _zz_178; - wire _zz_179; - wire [31:0] _zz_180; - reg _zz_181; - wire _zz_182; - wire _zz_183; - wire [31:0] _zz_184; - wire _zz_185; - wire _zz_186; - wire _zz_187; - wire _zz_188; - wire _zz_189; - wire _zz_190; - wire _zz_191; - wire _zz_192; - wire [3:0] _zz_193; - wire _zz_194; - wire _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -134,6 +134,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -142,325 +143,267 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - wire _zz_204; - wire _zz_205; - wire _zz_206; - wire _zz_207; - wire _zz_208; - wire _zz_209; - wire _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire [1:0] _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - wire _zz_219; - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - wire [1:0] _zz_225; - wire _zz_226; - wire _zz_227; - wire [5:0] _zz_228; - wire _zz_229; - wire _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire [1:0] _zz_235; - wire _zz_236; - wire [1:0] _zz_237; - wire [51:0] _zz_238; - wire [51:0] _zz_239; - wire [51:0] _zz_240; - wire [32:0] _zz_241; - wire [51:0] _zz_242; - wire [49:0] _zz_243; - wire [51:0] _zz_244; - wire [49:0] _zz_245; - wire [51:0] _zz_246; - wire [32:0] _zz_247; - wire [31:0] _zz_248; - wire [32:0] _zz_249; - wire [0:0] _zz_250; - wire [0:0] _zz_251; - wire [0:0] _zz_252; - wire [0:0] _zz_253; - wire [0:0] _zz_254; - wire [0:0] _zz_255; - wire [0:0] _zz_256; - wire [0:0] _zz_257; - wire [0:0] _zz_258; - wire [0:0] _zz_259; - wire [0:0] _zz_260; - wire [0:0] _zz_261; - wire [0:0] _zz_262; - wire [0:0] _zz_263; - wire [0:0] _zz_264; - wire [0:0] _zz_265; - wire [0:0] _zz_266; - wire [0:0] _zz_267; - wire [3:0] _zz_268; - wire [2:0] _zz_269; - wire [31:0] _zz_270; - wire [11:0] _zz_271; - wire [31:0] _zz_272; - wire [19:0] _zz_273; - wire [11:0] _zz_274; - wire [31:0] _zz_275; - wire [31:0] _zz_276; - wire [19:0] _zz_277; - wire [11:0] _zz_278; - wire [2:0] _zz_279; - wire [2:0] _zz_280; - wire [0:0] _zz_281; - wire [2:0] _zz_282; - wire [4:0] _zz_283; - wire [11:0] _zz_284; - wire [11:0] _zz_285; - wire [31:0] _zz_286; - wire [31:0] _zz_287; - wire [31:0] _zz_288; - wire [31:0] _zz_289; - wire [31:0] _zz_290; - wire [31:0] _zz_291; - wire [31:0] _zz_292; - wire [11:0] _zz_293; - wire [19:0] _zz_294; - wire [11:0] _zz_295; - wire [31:0] _zz_296; - wire [31:0] _zz_297; - wire [31:0] _zz_298; - wire [11:0] _zz_299; - wire [19:0] _zz_300; - wire [11:0] _zz_301; - wire [2:0] _zz_302; - wire [1:0] _zz_303; - wire [1:0] _zz_304; - wire [65:0] _zz_305; - wire [65:0] _zz_306; - wire [31:0] _zz_307; - wire [31:0] _zz_308; - wire [0:0] _zz_309; - wire [5:0] _zz_310; - wire [32:0] _zz_311; - wire [31:0] _zz_312; - wire [31:0] _zz_313; - wire [32:0] _zz_314; - wire [32:0] _zz_315; - wire [32:0] _zz_316; - wire [32:0] _zz_317; - wire [0:0] _zz_318; - wire [32:0] _zz_319; - wire [0:0] _zz_320; - wire [32:0] _zz_321; - wire [0:0] _zz_322; - wire [31:0] _zz_323; - wire [0:0] _zz_324; - wire [0:0] _zz_325; - wire [0:0] _zz_326; - wire [0:0] _zz_327; - wire [0:0] _zz_328; - wire [0:0] _zz_329; - wire [26:0] _zz_330; - wire _zz_331; - wire _zz_332; - wire [1:0] _zz_333; - wire [31:0] _zz_334; - wire [31:0] _zz_335; - wire [31:0] _zz_336; - wire _zz_337; - wire [0:0] _zz_338; - wire [13:0] _zz_339; - wire [31:0] _zz_340; - wire [31:0] _zz_341; - wire [31:0] _zz_342; - wire _zz_343; - wire [0:0] _zz_344; - wire [7:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; - wire _zz_349; - wire [0:0] _zz_350; - wire [1:0] _zz_351; - wire _zz_352; - wire _zz_353; - wire _zz_354; - wire [31:0] _zz_355; - wire [0:0] _zz_356; - wire [0:0] _zz_357; - wire _zz_358; - wire [0:0] _zz_359; - wire [26:0] _zz_360; - wire [31:0] _zz_361; - wire [31:0] _zz_362; - wire [31:0] _zz_363; - wire _zz_364; - wire [1:0] _zz_365; - wire [1:0] _zz_366; - wire _zz_367; - wire [0:0] _zz_368; - wire [22:0] _zz_369; - wire [31:0] _zz_370; - wire [31:0] _zz_371; - wire [31:0] _zz_372; - wire [31:0] _zz_373; - wire _zz_374; - wire _zz_375; - wire [1:0] _zz_376; - wire [1:0] _zz_377; - wire _zz_378; - wire [0:0] _zz_379; - wire [19:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire [31:0] _zz_384; - wire _zz_385; - wire [0:0] _zz_386; - wire [0:0] _zz_387; - wire _zz_388; - wire [0:0] _zz_389; - wire [0:0] _zz_390; - wire _zz_391; - wire [0:0] _zz_392; - wire [16:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire [0:0] _zz_399; - wire [0:0] _zz_400; - wire [0:0] _zz_401; - wire [0:0] _zz_402; - wire _zz_403; - wire [0:0] _zz_404; - wire [13:0] _zz_405; - wire [31:0] _zz_406; - wire [31:0] _zz_407; - wire [31:0] _zz_408; - wire _zz_409; - wire _zz_410; - wire [0:0] _zz_411; - wire [1:0] _zz_412; - wire [0:0] _zz_413; - wire [0:0] _zz_414; - wire _zz_415; - wire [0:0] _zz_416; - wire [10:0] _zz_417; - wire [31:0] _zz_418; - wire [31:0] _zz_419; - wire [31:0] _zz_420; - wire [31:0] _zz_421; - wire [31:0] _zz_422; - wire [31:0] _zz_423; - wire _zz_424; - wire [0:0] _zz_425; - wire [2:0] _zz_426; - wire [0:0] _zz_427; - wire [3:0] _zz_428; - wire [5:0] _zz_429; - wire [5:0] _zz_430; - wire _zz_431; - wire [0:0] _zz_432; - wire [7:0] _zz_433; - wire [31:0] _zz_434; - wire _zz_435; - wire [0:0] _zz_436; - wire [0:0] _zz_437; - wire _zz_438; - wire [0:0] _zz_439; - wire [1:0] _zz_440; - wire [0:0] _zz_441; - wire [3:0] _zz_442; - wire [0:0] _zz_443; - wire [0:0] _zz_444; - wire [1:0] _zz_445; - wire [1:0] _zz_446; - wire _zz_447; - wire [0:0] _zz_448; - wire [5:0] _zz_449; - wire [31:0] _zz_450; - wire [31:0] _zz_451; - wire [31:0] _zz_452; - wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [31:0] _zz_456; - wire [31:0] _zz_457; - wire _zz_458; - wire _zz_459; - wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire _zz_462; - wire [0:0] _zz_463; - wire [1:0] _zz_464; - wire [31:0] _zz_465; - wire [31:0] _zz_466; - wire _zz_467; - wire _zz_468; - wire [0:0] _zz_469; - wire [0:0] _zz_470; - wire _zz_471; - wire [0:0] _zz_472; - wire [3:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; - wire _zz_479; - wire _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire [0:0] _zz_485; - wire [2:0] _zz_486; - wire [0:0] _zz_487; - wire [0:0] _zz_488; - wire _zz_489; - wire [0:0] _zz_490; - wire [1:0] _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire _zz_495; - wire _zz_496; - wire [31:0] _zz_497; - wire _zz_498; - wire [0:0] _zz_499; - wire [0:0] _zz_500; - wire [0:0] _zz_501; - wire [0:0] _zz_502; - wire [1:0] _zz_503; - wire [1:0] _zz_504; - wire [0:0] _zz_505; - wire [0:0] _zz_506; - wire [31:0] _zz_507; - wire [31:0] _zz_508; - wire [31:0] _zz_509; - wire [31:0] _zz_510; - wire [31:0] _zz_511; - wire [31:0] _zz_512; - wire _zz_513; - wire _zz_514; - wire _zz_515; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_1; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_2; + wire _zz__zz_decode_IS_RS2_SIGNED_3; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_4; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_5; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_6; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_7; + wire [26:0] _zz__zz_decode_IS_RS2_SIGNED_8; + wire _zz__zz_decode_IS_RS2_SIGNED_9; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_10; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_11; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_12; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_13; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_14; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_15; + wire _zz__zz_decode_IS_RS2_SIGNED_16; + wire _zz__zz_decode_IS_RS2_SIGNED_17; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_18; + wire _zz__zz_decode_IS_RS2_SIGNED_19; + wire [22:0] _zz__zz_decode_IS_RS2_SIGNED_20; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_21; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_22; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_23; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_24; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_25; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_26; + wire _zz__zz_decode_IS_RS2_SIGNED_27; + wire _zz__zz_decode_IS_RS2_SIGNED_28; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_29; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_30; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_31; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_32; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_33; + wire _zz__zz_decode_IS_RS2_SIGNED_34; + wire [19:0] _zz__zz_decode_IS_RS2_SIGNED_35; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_36; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_37; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_38; + wire _zz__zz_decode_IS_RS2_SIGNED_39; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_40; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_41; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_42; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_43; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_44; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_45; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_46; + wire [16:0] _zz__zz_decode_IS_RS2_SIGNED_47; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_48; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_49; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_50; + wire _zz__zz_decode_IS_RS2_SIGNED_51; + wire _zz__zz_decode_IS_RS2_SIGNED_52; + wire _zz__zz_decode_IS_RS2_SIGNED_53; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_54; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_55; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_56; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_57; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_58; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_59; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_60; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_61; + wire [13:0] _zz__zz_decode_IS_RS2_SIGNED_62; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_63; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_64; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_65; + wire _zz__zz_decode_IS_RS2_SIGNED_66; + wire _zz__zz_decode_IS_RS2_SIGNED_67; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_68; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_69; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_70; + wire _zz__zz_decode_IS_RS2_SIGNED_71; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_72; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_73; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_74; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_75; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_76; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_77; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_78; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_79; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_80; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_81; + wire _zz__zz_decode_IS_RS2_SIGNED_82; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_83; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_84; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_85; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_86; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_87; + wire _zz__zz_decode_IS_RS2_SIGNED_88; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_89; + wire _zz__zz_decode_IS_RS2_SIGNED_90; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_91; + wire [10:0] _zz__zz_decode_IS_RS2_SIGNED_92; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_93; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_94; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_95; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_96; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_97; + wire _zz__zz_decode_IS_RS2_SIGNED_98; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_99; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_100; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_101; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_102; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_103; + wire _zz__zz_decode_IS_RS2_SIGNED_104; + wire _zz__zz_decode_IS_RS2_SIGNED_105; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_106; + wire _zz__zz_decode_IS_RS2_SIGNED_107; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_108; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_109; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_110; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_111; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_112; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_113; + wire _zz__zz_decode_IS_RS2_SIGNED_114; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_115; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_116; + wire [7:0] _zz__zz_decode_IS_RS2_SIGNED_117; + wire _zz__zz_decode_IS_RS2_SIGNED_118; + wire _zz__zz_decode_IS_RS2_SIGNED_119; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_120; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_121; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_122; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_123; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_124; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_125; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_126; + wire _zz__zz_decode_IS_RS2_SIGNED_127; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_128; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_129; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_130; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_131; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_132; + wire _zz__zz_decode_IS_RS2_SIGNED_133; + wire _zz__zz_decode_IS_RS2_SIGNED_134; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_135; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_136; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_137; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_138; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_139; + wire _zz__zz_decode_IS_RS2_SIGNED_140; + wire _zz__zz_decode_IS_RS2_SIGNED_141; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_142; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_143; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_144; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_145; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_146; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_147; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_148; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_149; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_150; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_151; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_152; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_153; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_154; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_155; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_156; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_157; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -471,8 +414,8 @@ module VexRiscv ( wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_DO_EBREAK; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; @@ -484,27 +427,27 @@ module VexRiscv ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -512,18 +455,18 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; @@ -545,23 +488,23 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_31; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -571,45 +514,45 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_32; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_35; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_36; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; - wire [31:0] _zz_40; - wire _zz_41; - reg _zz_42; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_43; - wire `BranchCtrlEnum_defaultEncoding_type _zz_44; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; - wire `Src2CtrlEnum_defaultEncoding_type _zz_47; - wire `AluCtrlEnum_defaultEncoding_type _zz_48; - wire `Src1CtrlEnum_defaultEncoding_type _zz_49; - reg [31:0] _zz_50; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -627,11 +570,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_52; - reg [31:0] _zz_53; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -718,7 +661,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -744,7 +687,7 @@ module VexRiscv ( reg DBusCachedPlugin_exceptionBus_valid; reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_54; + reg _zz_when_DBusCachedPlugin_l386; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -753,6 +696,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; wire CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -770,31 +718,37 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; reg CsrPlugin_allowInterrupts; reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; reg IBusCachedPlugin_injectionPort_valid; reg IBusCachedPlugin_injectionPort_ready; wire [31:0] IBusCachedPlugin_injectionPort_payload; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_55; - wire [3:0] _zz_56; - wire _zz_57; - wire _zz_58; - wire _zz_59; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -817,16 +771,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_60; - wire _zz_61; - wire _zz_62; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_63; - wire _zz_64; - reg _zz_65; - wire _zz_66; - reg _zz_67; - reg [31:0] _zz_68; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -834,22 +790,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_69; - reg [18:0] _zz_70; - wire _zz_71; - reg [10:0] _zz_72; - wire _zz_73; - reg [18:0] _zz_74; - reg _zz_75; - wire _zz_76; - reg [10:0] _zz_77; - wire _zz_78; - reg [18:0] _zz_79; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -857,7 +820,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_80; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -865,23 +828,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -889,38 +857,54 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_81; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_82; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_83; - reg [31:0] _zz_84; - wire _zz_85; - reg [31:0] _zz_86; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [32:0] _zz_87; - wire _zz_88; - wire _zz_89; - wire _zz_90; - wire _zz_91; - wire `Src1CtrlEnum_defaultEncoding_type _zz_92; - wire `AluCtrlEnum_defaultEncoding_type _zz_93; - wire `Src2CtrlEnum_defaultEncoding_type _zz_94; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_95; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_96; - wire `BranchCtrlEnum_defaultEncoding_type _zz_97; - wire `EnvCtrlEnum_defaultEncoding_type _zz_98; + wire when_DBusCachedPlugin_l484; + wire [32:0] _zz_decode_IS_RS2_SIGNED; + wire _zz_decode_IS_RS2_SIGNED_1; + wire _zz_decode_IS_RS2_SIGNED_2; + wire _zz_decode_IS_RS2_SIGNED_3; + wire _zz_decode_IS_RS2_SIGNED_4; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -928,52 +912,70 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_99; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_100; - reg [31:0] _zz_101; - wire _zz_102; - reg [19:0] _zz_103; - wire _zz_104; - reg [19:0] _zz_105; - reg [31:0] _zz_106; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_107; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_108; - reg _zz_109; - reg _zz_110; - reg _zz_111; - reg [4:0] _zz_112; - reg [31:0] _zz_113; - wire _zz_114; - wire _zz_115; - wire _zz_116; - wire _zz_117; - wire _zz_118; - wire _zz_119; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_120; - reg _zz_121; - reg _zz_122; - wire _zz_123; - reg [19:0] _zz_124; - wire _zz_125; - reg [10:0] _zz_126; - wire _zz_127; - reg [18:0] _zz_128; - reg _zz_129; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_130; - reg [19:0] _zz_131; - wire _zz_132; - reg [10:0] _zz_133; - wire _zz_134; - reg [18:0] _zz_135; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; @@ -994,9 +996,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_136; - wire _zz_137; - wire _zz_138; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1009,40 +1011,64 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_139; - wire _zz_140; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1050,6 +1076,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1062,19 +1090,26 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_141; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_142; - wire _zz_143; - wire _zz_144; - reg [32:0] _zz_145; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_146; - wire [31:0] _zz_147; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1082,174 +1117,274 @@ module VexRiscv ( reg DebugPlugin_stepIt; reg DebugPlugin_isPipBusy; reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_148; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_44; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_45; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_46; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_47; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_48; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_49; reg decode_to_execute_DO_EBREAK; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_50; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_51; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_52; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_53; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_54; reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_55; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_57; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_60; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_61; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_62; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_149; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l378; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_150; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [2:0] _zz_159; - reg _zz_160; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_161; - wire _zz_162; - wire _zz_163; - wire _zz_164; - wire _zz_165; - wire _zz_166; - reg _zz_167; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; - reg [39:0] _zz_17_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; - reg [23:0] _zz_20_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; - reg [63:0] _zz_23_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; - reg [95:0] _zz_26_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_30_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_33_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_34_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_36_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_37_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_38_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_39_string; - reg [39:0] _zz_43_string; - reg [31:0] _zz_44_string; - reg [71:0] _zz_45_string; - reg [39:0] _zz_46_string; - reg [23:0] _zz_47_string; - reg [63:0] _zz_48_string; - reg [95:0] _zz_49_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_51_string; - reg [95:0] _zz_92_string; - reg [63:0] _zz_93_string; - reg [23:0] _zz_94_string; - reg [39:0] _zz_95_string; - reg [71:0] _zz_96_string; - reg [31:0] _zz_97_string; - reg [39:0] _zz_98_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1264,1132 +1399,1098 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_199 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_200 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_201 = 1'b1; - assign _zz_202 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_203 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_204 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_205 = ((_zz_173 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_206 = ((_zz_173 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_207 = ((_zz_173 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_208 = ((_zz_173 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_209 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_210 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_211 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_212 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_213 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_214 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_215 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_216 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_217 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_218 = (1'b0 || (! 1'b1)); - assign _zz_219 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_220 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_221 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_222 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_223 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_224 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_225 = execute_INSTRUCTION[13 : 12]; - assign _zz_226 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_227 = (! memory_arbitration_isStuck); - assign _zz_228 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_229 = (iBus_cmd_valid || (_zz_159 != 3'b000)); - assign _zz_230 = (_zz_195 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_231 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_232 = ((_zz_136 && 1'b1) && (! 1'b0)); - assign _zz_233 = ((_zz_137 && 1'b1) && (! 1'b0)); - assign _zz_234 = ((_zz_138 && 1'b1) && (! 1'b0)); - assign _zz_235 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_236 = execute_INSTRUCTION[13]; - assign _zz_237 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_238 = ($signed(_zz_239) + $signed(_zz_244)); - assign _zz_239 = ($signed(_zz_240) + $signed(_zz_242)); - assign _zz_240 = 52'h0; - assign _zz_241 = {1'b0,memory_MUL_LL}; - assign _zz_242 = {{19{_zz_241[32]}}, _zz_241}; - assign _zz_243 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_244 = {{2{_zz_243[49]}}, _zz_243}; - assign _zz_245 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_246 = {{2{_zz_245[49]}}, _zz_245}; - assign _zz_247 = ($signed(_zz_249) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_248 = _zz_247[31 : 0]; - assign _zz_249 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_250 = _zz_87[31 : 31]; - assign _zz_251 = _zz_87[30 : 30]; - assign _zz_252 = _zz_87[29 : 29]; - assign _zz_253 = _zz_87[28 : 28]; - assign _zz_254 = _zz_87[25 : 25]; - assign _zz_255 = _zz_87[17 : 17]; - assign _zz_256 = _zz_87[16 : 16]; - assign _zz_257 = _zz_87[13 : 13]; - assign _zz_258 = _zz_87[12 : 12]; - assign _zz_259 = _zz_87[11 : 11]; - assign _zz_260 = _zz_87[32 : 32]; - assign _zz_261 = _zz_87[15 : 15]; - assign _zz_262 = _zz_87[5 : 5]; - assign _zz_263 = _zz_87[3 : 3]; - assign _zz_264 = _zz_87[20 : 20]; - assign _zz_265 = _zz_87[10 : 10]; - assign _zz_266 = _zz_87[4 : 4]; - assign _zz_267 = _zz_87[0 : 0]; - assign _zz_268 = (_zz_55 - 4'b0001); - assign _zz_269 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_270 = {29'd0, _zz_269}; - assign _zz_271 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_272 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_273 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_274 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_275 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_276 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_277 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_278 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_279 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_280 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_281 = execute_SRC_LESS; - assign _zz_282 = 3'b100; - assign _zz_283 = execute_INSTRUCTION[19 : 15]; - assign _zz_284 = execute_INSTRUCTION[31 : 20]; - assign _zz_285 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_286 = ($signed(_zz_287) + $signed(_zz_290)); - assign _zz_287 = ($signed(_zz_288) + $signed(_zz_289)); - assign _zz_288 = execute_SRC1; - assign _zz_289 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_290 = (execute_SRC_USE_SUB_LESS ? _zz_291 : _zz_292); - assign _zz_291 = 32'h00000001; - assign _zz_292 = 32'h0; - assign _zz_293 = execute_INSTRUCTION[31 : 20]; - assign _zz_294 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_295 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_296 = {_zz_124,execute_INSTRUCTION[31 : 20]}; - assign _zz_297 = {{_zz_126,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_298 = {{_zz_128,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_299 = execute_INSTRUCTION[31 : 20]; - assign _zz_300 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_301 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_302 = 3'b100; - assign _zz_303 = (_zz_139 & (~ _zz_304)); - assign _zz_304 = (_zz_139 - 2'b01); - assign _zz_305 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_306 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_307 = writeBack_MUL_LOW[31 : 0]; - assign _zz_308 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_309 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_310 = {5'd0, _zz_309}; - assign _zz_311 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_312 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_313 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_314 = {_zz_141,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_315 = _zz_316; - assign _zz_316 = _zz_317; - assign _zz_317 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_142) : _zz_142)} + _zz_319); - assign _zz_318 = memory_DivPlugin_div_needRevert; - assign _zz_319 = {32'd0, _zz_318}; - assign _zz_320 = _zz_144; - assign _zz_321 = {32'd0, _zz_320}; - assign _zz_322 = _zz_143; - assign _zz_323 = {31'd0, _zz_322}; - assign _zz_324 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_325 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_326 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_327 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_328 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_329 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_330 = (iBus_cmd_payload_address >>> 5); - assign _zz_331 = 1'b1; - assign _zz_332 = 1'b1; - assign _zz_333 = {_zz_59,_zz_58}; - assign _zz_334 = 32'h0000107f; - assign _zz_335 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_336 = 32'h00002073; - assign _zz_337 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_338 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_339 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_340) == 32'h00000003),{(_zz_341 == _zz_342),{_zz_343,{_zz_344,_zz_345}}}}}}; - assign _zz_340 = 32'h0000505f; - assign _zz_341 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_342 = 32'h00000063; - assign _zz_343 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_344 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_345 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_346) == 32'h00001013),{(_zz_347 == _zz_348),{_zz_349,{_zz_350,_zz_351}}}}}}; - assign _zz_346 = 32'hfc00307f; - assign _zz_347 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_348 = 32'h00005033; - assign _zz_349 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_350 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_351 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz_352 = decode_INSTRUCTION[31]; - assign _zz_353 = decode_INSTRUCTION[31]; - assign _zz_354 = decode_INSTRUCTION[7]; - assign _zz_355 = 32'h10103050; - assign _zz_356 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_357 = 1'b0; - assign _zz_358 = (((decode_INSTRUCTION & _zz_361) == 32'h02000030) != 1'b0); - assign _zz_359 = ((_zz_362 == _zz_363) != 1'b0); - assign _zz_360 = {(_zz_364 != 1'b0),{(_zz_365 != _zz_366),{_zz_367,{_zz_368,_zz_369}}}}; - assign _zz_361 = 32'h02004074; - assign _zz_362 = (decode_INSTRUCTION & 32'h10103050); - assign _zz_363 = 32'h00000050; - assign _zz_364 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); - assign _zz_365 = {(_zz_370 == _zz_371),(_zz_372 == _zz_373)}; - assign _zz_366 = 2'b00; - assign _zz_367 = ({_zz_90,_zz_374} != 2'b00); - assign _zz_368 = (_zz_375 != 1'b0); - assign _zz_369 = {(_zz_376 != _zz_377),{_zz_378,{_zz_379,_zz_380}}}; - assign _zz_370 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_371 = 32'h00001050; - assign _zz_372 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_373 = 32'h00002050; - assign _zz_374 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_375 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_376 = {(_zz_381 == _zz_382),(_zz_383 == _zz_384)}; - assign _zz_377 = 2'b00; - assign _zz_378 = ({_zz_385,{_zz_386,_zz_387}} != 3'b000); - assign _zz_379 = (_zz_388 != 1'b0); - assign _zz_380 = {(_zz_389 != _zz_390),{_zz_391,{_zz_392,_zz_393}}}; - assign _zz_381 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_382 = 32'h00005010; - assign _zz_383 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_384 = 32'h00005020; - assign _zz_385 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_386 = ((decode_INSTRUCTION & _zz_394) == 32'h00001010); - assign _zz_387 = ((decode_INSTRUCTION & _zz_395) == 32'h00001010); - assign _zz_388 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_389 = ((decode_INSTRUCTION & _zz_396) == 32'h00001000); - assign _zz_390 = 1'b0; - assign _zz_391 = ((_zz_397 == _zz_398) != 1'b0); - assign _zz_392 = ({_zz_399,_zz_400} != 2'b00); - assign _zz_393 = {(_zz_401 != _zz_402),{_zz_403,{_zz_404,_zz_405}}}; - assign _zz_394 = 32'h00007034; - assign _zz_395 = 32'h02007054; - assign _zz_396 = 32'h00001000; - assign _zz_397 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_398 = 32'h00002000; - assign _zz_399 = ((decode_INSTRUCTION & _zz_406) == 32'h00002000); - assign _zz_400 = ((decode_INSTRUCTION & _zz_407) == 32'h00001000); - assign _zz_401 = ((decode_INSTRUCTION & _zz_408) == 32'h00004008); - assign _zz_402 = 1'b0; - assign _zz_403 = ({_zz_409,_zz_410} != 2'b00); - assign _zz_404 = ({_zz_411,_zz_412} != 3'b000); - assign _zz_405 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; - assign _zz_406 = 32'h00002010; - assign _zz_407 = 32'h00005000; - assign _zz_408 = 32'h00004048; - assign _zz_409 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); - assign _zz_410 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_411 = ((decode_INSTRUCTION & _zz_418) == 32'h00000040); - assign _zz_412 = {(_zz_419 == _zz_420),(_zz_421 == _zz_422)}; - assign _zz_413 = ((decode_INSTRUCTION & _zz_423) == 32'h00000020); - assign _zz_414 = 1'b0; - assign _zz_415 = ({_zz_424,{_zz_425,_zz_426}} != 5'h0); - assign _zz_416 = ({_zz_427,_zz_428} != 5'h0); - assign _zz_417 = {(_zz_429 != _zz_430),{_zz_431,{_zz_432,_zz_433}}}; - assign _zz_418 = 32'h00000050; - assign _zz_419 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_420 = 32'h0; - assign _zz_421 = (decode_INSTRUCTION & 32'h00103040); - assign _zz_422 = 32'h00000040; - assign _zz_423 = 32'h00000020; - assign _zz_424 = ((decode_INSTRUCTION & _zz_434) == 32'h00000040); - assign _zz_425 = _zz_89; - assign _zz_426 = {_zz_435,{_zz_436,_zz_437}}; - assign _zz_427 = _zz_89; - assign _zz_428 = {_zz_438,{_zz_439,_zz_440}}; - assign _zz_429 = {_zz_90,{_zz_441,_zz_442}}; - assign _zz_430 = 6'h0; - assign _zz_431 = ({_zz_443,_zz_444} != 2'b00); - assign _zz_432 = (_zz_445 != _zz_446); - assign _zz_433 = {_zz_447,{_zz_448,_zz_449}}; - assign _zz_434 = 32'h00000040; - assign _zz_435 = ((decode_INSTRUCTION & _zz_450) == 32'h00004020); - assign _zz_436 = (_zz_451 == _zz_452); - assign _zz_437 = (_zz_453 == _zz_454); - assign _zz_438 = ((decode_INSTRUCTION & _zz_455) == 32'h00002010); - assign _zz_439 = (_zz_456 == _zz_457); - assign _zz_440 = {_zz_458,_zz_459}; - assign _zz_441 = (_zz_460 == _zz_461); - assign _zz_442 = {_zz_462,{_zz_463,_zz_464}}; - assign _zz_443 = _zz_89; - assign _zz_444 = (_zz_465 == _zz_466); - assign _zz_445 = {_zz_89,_zz_467}; - assign _zz_446 = 2'b00; - assign _zz_447 = (_zz_468 != 1'b0); - assign _zz_448 = (_zz_469 != _zz_470); - assign _zz_449 = {_zz_471,{_zz_472,_zz_473}}; - assign _zz_450 = 32'h00004020; - assign _zz_451 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_452 = 32'h00000010; - assign _zz_453 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_454 = 32'h00000020; - assign _zz_455 = 32'h00002030; - assign _zz_456 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_457 = 32'h00000010; - assign _zz_458 = ((decode_INSTRUCTION & _zz_474) == 32'h00002020); - assign _zz_459 = ((decode_INSTRUCTION & _zz_475) == 32'h00000020); - assign _zz_460 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_461 = 32'h00001010; - assign _zz_462 = ((decode_INSTRUCTION & _zz_476) == 32'h00002010); - assign _zz_463 = (_zz_477 == _zz_478); - assign _zz_464 = {_zz_479,_zz_480}; - assign _zz_465 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_466 = 32'h00000020; - assign _zz_467 = ((decode_INSTRUCTION & _zz_481) == 32'h0); - assign _zz_468 = ((decode_INSTRUCTION & _zz_482) == 32'h00004010); - assign _zz_469 = (_zz_483 == _zz_484); - assign _zz_470 = 1'b0; - assign _zz_471 = ({_zz_485,_zz_486} != 4'b0000); - assign _zz_472 = (_zz_487 != _zz_488); - assign _zz_473 = {_zz_489,{_zz_490,_zz_491}}; - assign _zz_474 = 32'h02002060; - assign _zz_475 = 32'h02003020; - assign _zz_476 = 32'h00002010; - assign _zz_477 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_478 = 32'h00000010; - assign _zz_479 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_480 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); - assign _zz_481 = 32'h00000020; - assign _zz_482 = 32'h00004014; - assign _zz_483 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_484 = 32'h00002010; - assign _zz_485 = ((decode_INSTRUCTION & _zz_492) == 32'h0); - assign _zz_486 = {(_zz_493 == _zz_494),{_zz_495,_zz_496}}; - assign _zz_487 = ((decode_INSTRUCTION & _zz_497) == 32'h0); - assign _zz_488 = 1'b0; - assign _zz_489 = ({_zz_498,{_zz_499,_zz_500}} != 3'b000); - assign _zz_490 = ({_zz_501,_zz_502} != 2'b00); - assign _zz_491 = {(_zz_503 != _zz_504),(_zz_505 != _zz_506)}; - assign _zz_492 = 32'h00000044; - assign _zz_493 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_494 = 32'h0; - assign _zz_495 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_496 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_497 = 32'h00000058; - assign _zz_498 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_499 = ((decode_INSTRUCTION & _zz_507) == 32'h00002010); - assign _zz_500 = ((decode_INSTRUCTION & _zz_508) == 32'h40000030); - assign _zz_501 = ((decode_INSTRUCTION & _zz_509) == 32'h00000004); - assign _zz_502 = _zz_88; - assign _zz_503 = {(_zz_510 == _zz_511),_zz_88}; - assign _zz_504 = 2'b00; - assign _zz_505 = ((decode_INSTRUCTION & _zz_512) == 32'h00001008); - assign _zz_506 = 1'b0; - assign _zz_507 = 32'h00002014; - assign _zz_508 = 32'h40000034; - assign _zz_509 = 32'h00000014; - assign _zz_510 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_511 = 32'h00000004; - assign _zz_512 = 32'h00005048; - assign _zz_513 = execute_INSTRUCTION[31]; - assign _zz_514 = execute_INSTRUCTION[31]; - assign _zz_515 = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_331) begin - _zz_196 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_332) begin - _zz_197 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_42) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_IS_RS2_SIGNED = 32'h10103050; + assign _zz__zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz__zz_decode_IS_RS2_SIGNED_2 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_3 = (((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_4) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_5 = ((_zz__zz_decode_IS_RS2_SIGNED_6 == _zz__zz_decode_IS_RS2_SIGNED_7) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_8 = {(_zz__zz_decode_IS_RS2_SIGNED_9 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_10 != _zz__zz_decode_IS_RS2_SIGNED_15),{_zz__zz_decode_IS_RS2_SIGNED_16,{_zz__zz_decode_IS_RS2_SIGNED_18,_zz__zz_decode_IS_RS2_SIGNED_20}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_4 = 32'h02004074; + assign _zz__zz_decode_IS_RS2_SIGNED_6 = (decode_INSTRUCTION & 32'h10103050); + assign _zz__zz_decode_IS_RS2_SIGNED_7 = 32'h00000050; + assign _zz__zz_decode_IS_RS2_SIGNED_9 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz__zz_decode_IS_RS2_SIGNED_10 = {(_zz__zz_decode_IS_RS2_SIGNED_11 == _zz__zz_decode_IS_RS2_SIGNED_12),(_zz__zz_decode_IS_RS2_SIGNED_13 == _zz__zz_decode_IS_RS2_SIGNED_14)}; + assign _zz__zz_decode_IS_RS2_SIGNED_15 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_16 = ({_zz_decode_IS_RS2_SIGNED_3,_zz__zz_decode_IS_RS2_SIGNED_17} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_18 = (_zz__zz_decode_IS_RS2_SIGNED_19 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_20 = {(_zz__zz_decode_IS_RS2_SIGNED_21 != _zz__zz_decode_IS_RS2_SIGNED_26),{_zz__zz_decode_IS_RS2_SIGNED_27,{_zz__zz_decode_IS_RS2_SIGNED_33,_zz__zz_decode_IS_RS2_SIGNED_35}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_11 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_IS_RS2_SIGNED_12 = 32'h00001050; + assign _zz__zz_decode_IS_RS2_SIGNED_13 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_IS_RS2_SIGNED_14 = 32'h00002050; + assign _zz__zz_decode_IS_RS2_SIGNED_17 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_19 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_21 = {(_zz__zz_decode_IS_RS2_SIGNED_22 == _zz__zz_decode_IS_RS2_SIGNED_23),(_zz__zz_decode_IS_RS2_SIGNED_24 == _zz__zz_decode_IS_RS2_SIGNED_25)}; + assign _zz__zz_decode_IS_RS2_SIGNED_26 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_27 = ({_zz__zz_decode_IS_RS2_SIGNED_28,{_zz__zz_decode_IS_RS2_SIGNED_29,_zz__zz_decode_IS_RS2_SIGNED_31}} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_33 = (_zz__zz_decode_IS_RS2_SIGNED_34 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_35 = {(_zz__zz_decode_IS_RS2_SIGNED_36 != _zz__zz_decode_IS_RS2_SIGNED_38),{_zz__zz_decode_IS_RS2_SIGNED_39,{_zz__zz_decode_IS_RS2_SIGNED_42,_zz__zz_decode_IS_RS2_SIGNED_47}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_22 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_RS2_SIGNED_23 = 32'h00005010; + assign _zz__zz_decode_IS_RS2_SIGNED_24 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_IS_RS2_SIGNED_25 = 32'h00005020; + assign _zz__zz_decode_IS_RS2_SIGNED_28 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_IS_RS2_SIGNED_29 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_30) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_31 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_32) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_34 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_IS_RS2_SIGNED_36 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_37) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_38 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_39 = ((_zz__zz_decode_IS_RS2_SIGNED_40 == _zz__zz_decode_IS_RS2_SIGNED_41) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_42 = ({_zz__zz_decode_IS_RS2_SIGNED_43,_zz__zz_decode_IS_RS2_SIGNED_45} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_47 = {(_zz__zz_decode_IS_RS2_SIGNED_48 != _zz__zz_decode_IS_RS2_SIGNED_50),{_zz__zz_decode_IS_RS2_SIGNED_51,{_zz__zz_decode_IS_RS2_SIGNED_54,_zz__zz_decode_IS_RS2_SIGNED_62}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_30 = 32'h00007034; + assign _zz__zz_decode_IS_RS2_SIGNED_32 = 32'h02007054; + assign _zz__zz_decode_IS_RS2_SIGNED_37 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_40 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_IS_RS2_SIGNED_41 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_43 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_44) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_45 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_46) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_48 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_49) == 32'h00004008); + assign _zz__zz_decode_IS_RS2_SIGNED_50 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_51 = ({_zz__zz_decode_IS_RS2_SIGNED_52,_zz__zz_decode_IS_RS2_SIGNED_53} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_54 = ({_zz__zz_decode_IS_RS2_SIGNED_55,_zz__zz_decode_IS_RS2_SIGNED_57} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_62 = {(_zz__zz_decode_IS_RS2_SIGNED_63 != _zz__zz_decode_IS_RS2_SIGNED_65),{_zz__zz_decode_IS_RS2_SIGNED_66,{_zz__zz_decode_IS_RS2_SIGNED_79,_zz__zz_decode_IS_RS2_SIGNED_92}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_44 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_46 = 32'h00005000; + assign _zz__zz_decode_IS_RS2_SIGNED_49 = 32'h00004048; + assign _zz__zz_decode_IS_RS2_SIGNED_52 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_53 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_55 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_56) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_57 = {(_zz__zz_decode_IS_RS2_SIGNED_58 == _zz__zz_decode_IS_RS2_SIGNED_59),(_zz__zz_decode_IS_RS2_SIGNED_60 == _zz__zz_decode_IS_RS2_SIGNED_61)}; + assign _zz__zz_decode_IS_RS2_SIGNED_63 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_64) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_65 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_66 = ({_zz__zz_decode_IS_RS2_SIGNED_67,{_zz__zz_decode_IS_RS2_SIGNED_69,_zz__zz_decode_IS_RS2_SIGNED_70}} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_79 = ({_zz__zz_decode_IS_RS2_SIGNED_80,_zz__zz_decode_IS_RS2_SIGNED_81} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_92 = {(_zz__zz_decode_IS_RS2_SIGNED_93 != _zz__zz_decode_IS_RS2_SIGNED_106),{_zz__zz_decode_IS_RS2_SIGNED_107,{_zz__zz_decode_IS_RS2_SIGNED_112,_zz__zz_decode_IS_RS2_SIGNED_117}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_56 = 32'h00000050; + assign _zz__zz_decode_IS_RS2_SIGNED_58 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_IS_RS2_SIGNED_59 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_60 = (decode_INSTRUCTION & 32'h00103040); + assign _zz__zz_decode_IS_RS2_SIGNED_61 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_64 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_67 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_68) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_69 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_70 = {_zz__zz_decode_IS_RS2_SIGNED_71,{_zz__zz_decode_IS_RS2_SIGNED_73,_zz__zz_decode_IS_RS2_SIGNED_76}}; + assign _zz__zz_decode_IS_RS2_SIGNED_80 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_81 = {_zz__zz_decode_IS_RS2_SIGNED_82,{_zz__zz_decode_IS_RS2_SIGNED_84,_zz__zz_decode_IS_RS2_SIGNED_87}}; + assign _zz__zz_decode_IS_RS2_SIGNED_93 = {_zz_decode_IS_RS2_SIGNED_3,{_zz__zz_decode_IS_RS2_SIGNED_94,_zz__zz_decode_IS_RS2_SIGNED_97}}; + assign _zz__zz_decode_IS_RS2_SIGNED_106 = 6'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_107 = ({_zz__zz_decode_IS_RS2_SIGNED_108,_zz__zz_decode_IS_RS2_SIGNED_109} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_112 = (_zz__zz_decode_IS_RS2_SIGNED_113 != _zz__zz_decode_IS_RS2_SIGNED_116); + assign _zz__zz_decode_IS_RS2_SIGNED_117 = {_zz__zz_decode_IS_RS2_SIGNED_118,{_zz__zz_decode_IS_RS2_SIGNED_121,_zz__zz_decode_IS_RS2_SIGNED_126}}; + assign _zz__zz_decode_IS_RS2_SIGNED_68 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_71 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_72) == 32'h00004020); + assign _zz__zz_decode_IS_RS2_SIGNED_73 = (_zz__zz_decode_IS_RS2_SIGNED_74 == _zz__zz_decode_IS_RS2_SIGNED_75); + assign _zz__zz_decode_IS_RS2_SIGNED_76 = (_zz__zz_decode_IS_RS2_SIGNED_77 == _zz__zz_decode_IS_RS2_SIGNED_78); + assign _zz__zz_decode_IS_RS2_SIGNED_82 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_83) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_84 = (_zz__zz_decode_IS_RS2_SIGNED_85 == _zz__zz_decode_IS_RS2_SIGNED_86); + assign _zz__zz_decode_IS_RS2_SIGNED_87 = {_zz__zz_decode_IS_RS2_SIGNED_88,_zz__zz_decode_IS_RS2_SIGNED_90}; + assign _zz__zz_decode_IS_RS2_SIGNED_94 = (_zz__zz_decode_IS_RS2_SIGNED_95 == _zz__zz_decode_IS_RS2_SIGNED_96); + assign _zz__zz_decode_IS_RS2_SIGNED_97 = {_zz__zz_decode_IS_RS2_SIGNED_98,{_zz__zz_decode_IS_RS2_SIGNED_100,_zz__zz_decode_IS_RS2_SIGNED_103}}; + assign _zz__zz_decode_IS_RS2_SIGNED_108 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_109 = (_zz__zz_decode_IS_RS2_SIGNED_110 == _zz__zz_decode_IS_RS2_SIGNED_111); + assign _zz__zz_decode_IS_RS2_SIGNED_113 = {_zz_decode_IS_RS2_SIGNED_2,_zz__zz_decode_IS_RS2_SIGNED_114}; + assign _zz__zz_decode_IS_RS2_SIGNED_116 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_118 = (_zz__zz_decode_IS_RS2_SIGNED_119 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_121 = (_zz__zz_decode_IS_RS2_SIGNED_122 != _zz__zz_decode_IS_RS2_SIGNED_125); + assign _zz__zz_decode_IS_RS2_SIGNED_126 = {_zz__zz_decode_IS_RS2_SIGNED_127,{_zz__zz_decode_IS_RS2_SIGNED_135,_zz__zz_decode_IS_RS2_SIGNED_139}}; + assign _zz__zz_decode_IS_RS2_SIGNED_72 = 32'h00004020; + assign _zz__zz_decode_IS_RS2_SIGNED_74 = (decode_INSTRUCTION & 32'h00000030); + assign _zz__zz_decode_IS_RS2_SIGNED_75 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_77 = (decode_INSTRUCTION & 32'h02000020); + assign _zz__zz_decode_IS_RS2_SIGNED_78 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_83 = 32'h00002030; + assign _zz__zz_decode_IS_RS2_SIGNED_85 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_IS_RS2_SIGNED_86 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_88 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_89) == 32'h00002020); + assign _zz__zz_decode_IS_RS2_SIGNED_90 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_91) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_95 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_96 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_98 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_99) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_100 = (_zz__zz_decode_IS_RS2_SIGNED_101 == _zz__zz_decode_IS_RS2_SIGNED_102); + assign _zz__zz_decode_IS_RS2_SIGNED_103 = {_zz__zz_decode_IS_RS2_SIGNED_104,_zz__zz_decode_IS_RS2_SIGNED_105}; + assign _zz__zz_decode_IS_RS2_SIGNED_110 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_IS_RS2_SIGNED_111 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_114 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_115) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_119 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_120) == 32'h00004010); + assign _zz__zz_decode_IS_RS2_SIGNED_122 = (_zz__zz_decode_IS_RS2_SIGNED_123 == _zz__zz_decode_IS_RS2_SIGNED_124); + assign _zz__zz_decode_IS_RS2_SIGNED_125 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_127 = ({_zz__zz_decode_IS_RS2_SIGNED_128,_zz__zz_decode_IS_RS2_SIGNED_130} != 4'b0000); + assign _zz__zz_decode_IS_RS2_SIGNED_135 = (_zz__zz_decode_IS_RS2_SIGNED_136 != _zz__zz_decode_IS_RS2_SIGNED_138); + assign _zz__zz_decode_IS_RS2_SIGNED_139 = {_zz__zz_decode_IS_RS2_SIGNED_140,{_zz__zz_decode_IS_RS2_SIGNED_146,_zz__zz_decode_IS_RS2_SIGNED_150}}; + assign _zz__zz_decode_IS_RS2_SIGNED_89 = 32'h02002060; + assign _zz__zz_decode_IS_RS2_SIGNED_91 = 32'h02003020; + assign _zz__zz_decode_IS_RS2_SIGNED_99 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_101 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_102 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_104 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_105 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_115 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_120 = 32'h00004014; + assign _zz__zz_decode_IS_RS2_SIGNED_123 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_IS_RS2_SIGNED_124 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_128 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_129) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_130 = {(_zz__zz_decode_IS_RS2_SIGNED_131 == _zz__zz_decode_IS_RS2_SIGNED_132),{_zz__zz_decode_IS_RS2_SIGNED_133,_zz__zz_decode_IS_RS2_SIGNED_134}}; + assign _zz__zz_decode_IS_RS2_SIGNED_136 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_137) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_138 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_140 = ({_zz__zz_decode_IS_RS2_SIGNED_141,{_zz__zz_decode_IS_RS2_SIGNED_142,_zz__zz_decode_IS_RS2_SIGNED_144}} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_146 = ({_zz__zz_decode_IS_RS2_SIGNED_147,_zz__zz_decode_IS_RS2_SIGNED_149} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_150 = {(_zz__zz_decode_IS_RS2_SIGNED_151 != _zz__zz_decode_IS_RS2_SIGNED_154),(_zz__zz_decode_IS_RS2_SIGNED_155 != _zz__zz_decode_IS_RS2_SIGNED_157)}; + assign _zz__zz_decode_IS_RS2_SIGNED_129 = 32'h00000044; + assign _zz__zz_decode_IS_RS2_SIGNED_131 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_IS_RS2_SIGNED_132 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_133 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_134 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_137 = 32'h00000058; + assign _zz__zz_decode_IS_RS2_SIGNED_141 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_142 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_143) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_144 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_145) == 32'h40000030); + assign _zz__zz_decode_IS_RS2_SIGNED_147 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_148) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_149 = _zz_decode_IS_RS2_SIGNED_1; + assign _zz__zz_decode_IS_RS2_SIGNED_151 = {(_zz__zz_decode_IS_RS2_SIGNED_152 == _zz__zz_decode_IS_RS2_SIGNED_153),_zz_decode_IS_RS2_SIGNED_1}; + assign _zz__zz_decode_IS_RS2_SIGNED_154 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_155 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_156) == 32'h00001008); + assign _zz__zz_decode_IS_RS2_SIGNED_157 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_143 = 32'h00002014; + assign _zz__zz_decode_IS_RS2_SIGNED_145 = 32'h40000034; + assign _zz__zz_decode_IS_RS2_SIGNED_148 = 32'h00000014; + assign _zz__zz_decode_IS_RS2_SIGNED_152 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_RS2_SIGNED_153 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_156 = 32'h00005048; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_168 ), //i - .io_cpu_prefetch_isValid (_zz_169 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_170 ), //i - .io_cpu_fetch_isStuck (_zz_171 ), //i - .io_cpu_fetch_isRemoved (_zz_172 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_173 ), //i - .io_cpu_decode_isStuck (_zz_174 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_175 ), //i - .io_cpu_fill_valid (_zz_176 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_149[2:0] ), //i - ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i + ._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_177 ), //i - .io_cpu_execute_address (_zz_178[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_82[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_179 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_180[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_181 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_182 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_183 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_184[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_185 ), //i - .io_cpu_writeBack_fence_SR (_zz_186 ), //i - .io_cpu_writeBack_fence_SO (_zz_187 ), //i - .io_cpu_writeBack_fence_SI (_zz_188 ), //i - .io_cpu_writeBack_fence_PW (_zz_189 ), //i - .io_cpu_writeBack_fence_PR (_zz_190 ), //i - .io_cpu_writeBack_fence_PO (_zz_191 ), //i - .io_cpu_writeBack_fence_PI (_zz_192 ), //i - .io_cpu_writeBack_fence_FM (_zz_193[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_194 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_195 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_333) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) + 2'b00 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) 2'b00 : begin - _zz_198 = DBusCachedPlugin_redoBranch_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; end 2'b01 : begin - _zz_198 = CsrPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; end 2'b10 : begin - _zz_198 = BranchPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; end default : begin - _zz_198 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_30) - `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; - default : _zz_30_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_33) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; - default : _zz_33_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_34) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; - default : _zz_34_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_36) - `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; - default : _zz_36_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_37) - `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; - default : _zz_37_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_38) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; - default : _zz_38_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_39) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; - default : _zz_39_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_43) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; - default : _zz_43_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; - default : _zz_44_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_45) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; - default : _zz_45_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_46) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; - default : _zz_46_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_47) - `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; - default : _zz_47_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_48) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; - default : _zz_48_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_49) - `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; - default : _zz_49_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_92) - `Src1CtrlEnum_defaultEncoding_RS : _zz_92_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_92_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_92_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_92_string = "URS1 "; - default : _zz_92_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_93) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_93_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_93_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_93_string = "BITWISE "; - default : _zz_93_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_94) - `Src2CtrlEnum_defaultEncoding_RS : _zz_94_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_94_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_94_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_94_string = "PC "; - default : _zz_94_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_95) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_95_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_95_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_95_string = "AND_1"; - default : _zz_95_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_96) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_96_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_96_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_96_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_96_string = "SRA_1 "; - default : _zz_96_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_97) - `BranchCtrlEnum_defaultEncoding_INC : _zz_97_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_97_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_97_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_97_string = "JALR"; - default : _zz_97_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_98) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_98_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_98_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_98_string = "ECALL"; - default : _zz_98_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_238) + $signed(_zz_246)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2397,45 +2498,45 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_248; - assign execute_REGFILE_WRITE_DATA = _zz_100; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_178[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_250[0]; - assign decode_IS_RS1_SIGNED = _zz_251[0]; - assign decode_IS_DIV = _zz_252[0]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_RS2_SIGNED[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_RS2_SIGNED[30]; + assign decode_IS_DIV = _zz_decode_IS_RS2_SIGNED[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_253[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_254[0]; - assign _zz_8 = _zz_9; - assign _zz_10 = _zz_11; - assign decode_SHIFT_CTRL = _zz_12; - assign _zz_13 = _zz_14; - assign decode_ALU_BITWISE_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_255[0]; - assign decode_MEMORY_MANAGMENT = _zz_256[0]; + assign decode_IS_MUL = _zz_decode_IS_RS2_SIGNED[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_RS2_SIGNED[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_RS2_SIGNED[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_RS2_SIGNED[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_257[0]; + assign decode_MEMORY_WR = _zz_decode_IS_RS2_SIGNED[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_258[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_259[0]; - assign decode_SRC2_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_ALU_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_SRC1_CTRL = _zz_24; - assign _zz_25 = _zz_26; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_RS2_SIGNED[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_RS2_SIGNED[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; @@ -2443,7 +2544,7 @@ module VexRiscv ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_260[0]; + assign decode_IS_EBREAK = _zz_decode_IS_RS2_SIGNED[32]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2457,22 +2558,22 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27; - assign execute_ENV_CTRL = _zz_28; - assign writeBack_ENV_CTRL = _zz_29; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_122; - assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_261[0]; - assign decode_RS1_USE = _zz_262[0]; - always @ (*) begin - _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_199)begin - _zz_31 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_RS2_SIGNED[15]; + assign decode_RS1_USE = _zz_decode_IS_RS2_SIGNED[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2482,139 +2583,139 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_111)begin - if((_zz_112 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_113; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_200)begin - if(_zz_201)begin - if(_zz_115)begin - decode_RS2 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_202)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_117)begin - decode_RS2 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_203)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_119)begin - decode_RS2 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_111)begin - if((_zz_112 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_113; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_200)begin - if(_zz_201)begin - if(_zz_114)begin - decode_RS1 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_202)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_116)begin - decode_RS1 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_203)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_118)begin - decode_RS1 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_32 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_32 = _zz_108; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_32 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_204)begin - _zz_32 = memory_DivPlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_33; - assign execute_SHIFT_CTRL = _zz_34; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_35 = execute_PC; - assign execute_SRC2_CTRL = _zz_36; - assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_263[0]; - assign decode_SRC_ADD_ZERO = _zz_264[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_RS2_SIGNED[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_RS2_SIGNED[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_38; - assign execute_SRC2 = _zz_106; - assign execute_SRC1 = _zz_101; - assign execute_ALU_BITWISE_CTRL = _zz_39; - assign _zz_40 = writeBack_INSTRUCTION; - assign _zz_41 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_42 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_42 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_265[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_RS2_SIGNED[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_334) == 32'h00001073),{(_zz_335 == _zz_336),{_zz_337,{_zz_338,_zz_339}}}}}}} != 21'h0); - always @ (*) begin - _zz_50 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_50 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 21'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_237) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_50 = _zz_307; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_50 = _zz_308; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2626,61 +2727,61 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_266[0]; - assign decode_FLUSH_ALL = _zz_267[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_IS_RS2_SIGNED[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_RS2_SIGNED[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_205)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_206)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_207)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_208)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_51; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_52 = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_52 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_53 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end - case(_zz_149) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2689,161 +2790,161 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_109 || _zz_110)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_209)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_209)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_194 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_199)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_210)begin + if(when_DebugPlugin_l284) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_210)begin - if(_zz_211)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushIt = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_210)begin - if(_zz_211)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushNext = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_204)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_212)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_213)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2852,69 +2953,71 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_212)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_213)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_210)begin - if(_zz_211)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_214)begin + if(when_DebugPlugin_l300) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin - _zz_54 = 1'b0; - if(DebugPlugin_godmode)begin - _zz_54 = 1'b1; + always @(*) begin + _zz_when_DBusCachedPlugin_l386 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l386 = 1'b1; end end + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; assign CsrPlugin_inWfi = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin CsrPlugin_thirdPartyWake = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_212)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_213)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_212)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_213)begin - case(_zz_215) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2924,80 +3027,92 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_forceMachineWire = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + if(when_DebugPlugin_l316) begin CsrPlugin_allowInterrupts = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_allowException = 1'b0; end end + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_55 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_56 = (_zz_55 & (~ _zz_268)); - assign _zz_57 = _zz_56[3]; - assign _zz_58 = (_zz_56[1] || _zz_57); - assign _zz_59 = (_zz_56[2] || _zz_57); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_198; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_270); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3005,66 +3120,75 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_60); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_60); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_61); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_61); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_62 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_62); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_62); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_63; - assign _zz_63 = ((1'b0 && (! _zz_64)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_64 = _zz_65; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_64; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_66)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_66 = _zz_67; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_66; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_68; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); - always @ (*) begin + always @(*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_149) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3076,207 +3200,219 @@ module VexRiscv ( endcase end - assign _zz_69 = _zz_271[11]; - always @ (*) begin - _zz_70[18] = _zz_69; - _zz_70[17] = _zz_69; - _zz_70[16] = _zz_69; - _zz_70[15] = _zz_69; - _zz_70[14] = _zz_69; - _zz_70[13] = _zz_69; - _zz_70[12] = _zz_69; - _zz_70[11] = _zz_69; - _zz_70[10] = _zz_69; - _zz_70[9] = _zz_69; - _zz_70[8] = _zz_69; - _zz_70[7] = _zz_69; - _zz_70[6] = _zz_69; - _zz_70[5] = _zz_69; - _zz_70[4] = _zz_69; - _zz_70[3] = _zz_69; - _zz_70[2] = _zz_69; - _zz_70[1] = _zz_69; - _zz_70[0] = _zz_69; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_272[31])); - if(_zz_75)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_71 = _zz_273[19]; - always @ (*) begin - _zz_72[10] = _zz_71; - _zz_72[9] = _zz_71; - _zz_72[8] = _zz_71; - _zz_72[7] = _zz_71; - _zz_72[6] = _zz_71; - _zz_72[5] = _zz_71; - _zz_72[4] = _zz_71; - _zz_72[3] = _zz_71; - _zz_72[2] = _zz_71; - _zz_72[1] = _zz_71; - _zz_72[0] = _zz_71; - end - - assign _zz_73 = _zz_274[11]; - always @ (*) begin - _zz_74[18] = _zz_73; - _zz_74[17] = _zz_73; - _zz_74[16] = _zz_73; - _zz_74[15] = _zz_73; - _zz_74[14] = _zz_73; - _zz_74[13] = _zz_73; - _zz_74[12] = _zz_73; - _zz_74[11] = _zz_73; - _zz_74[10] = _zz_73; - _zz_74[9] = _zz_73; - _zz_74[8] = _zz_73; - _zz_74[7] = _zz_73; - _zz_74[6] = _zz_73; - _zz_74[5] = _zz_73; - _zz_74[4] = _zz_73; - _zz_74[3] = _zz_73; - _zz_74[2] = _zz_73; - _zz_74[1] = _zz_73; - _zz_74[0] = _zz_73; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_75 = _zz_275[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_75 = _zz_276[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_76 = _zz_277[19]; - always @ (*) begin - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7] = _zz_76; - _zz_77[6] = _zz_76; - _zz_77[5] = _zz_76; - _zz_77[4] = _zz_76; - _zz_77[3] = _zz_76; - _zz_77[2] = _zz_76; - _zz_77[1] = _zz_76; - _zz_77[0] = _zz_76; - end - - assign _zz_78 = _zz_278[11]; - always @ (*) begin - _zz_79[18] = _zz_78; - _zz_79[17] = _zz_78; - _zz_79[16] = _zz_78; - _zz_79[15] = _zz_78; - _zz_79[14] = _zz_78; - _zz_79[13] = _zz_78; - _zz_79[12] = _zz_78; - _zz_79[11] = _zz_78; - _zz_79[10] = _zz_78; - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7] = _zz_78; - _zz_79[6] = _zz_78; - _zz_79[5] = _zz_78; - _zz_79[4] = _zz_78; - _zz_79[3] = _zz_78; - _zz_79[2] = _zz_78; - _zz_79[1] = _zz_78; - _zz_79[0] = _zz_78; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_77,{{{_zz_352,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_79,{{{_zz_353,_zz_354},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_169 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_170 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_171 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_170; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_173 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_174 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_175 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_208)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_206)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_176 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_206)begin - _zz_176 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_207)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_205)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_207)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_205)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_168 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_195 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3284,168 +3420,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_177 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_178 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_82 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_82 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_82 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_194 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_179 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_180 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_179; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_180; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_181 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_54 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_181 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_182 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_183 = (CsrPlugin_privilege == 2'b00); - assign _zz_184 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_216)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_216)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_216)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_279}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_280}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; end - assign _zz_83 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_84[31] = _zz_83; - _zz_84[30] = _zz_83; - _zz_84[29] = _zz_83; - _zz_84[28] = _zz_83; - _zz_84[27] = _zz_83; - _zz_84[26] = _zz_83; - _zz_84[25] = _zz_83; - _zz_84[24] = _zz_83; - _zz_84[23] = _zz_83; - _zz_84[22] = _zz_83; - _zz_84[21] = _zz_83; - _zz_84[20] = _zz_83; - _zz_84[19] = _zz_83; - _zz_84[18] = _zz_83; - _zz_84[17] = _zz_83; - _zz_84[16] = _zz_83; - _zz_84[15] = _zz_83; - _zz_84[14] = _zz_83; - _zz_84[13] = _zz_83; - _zz_84[12] = _zz_83; - _zz_84[11] = _zz_83; - _zz_84[10] = _zz_83; - _zz_84[9] = _zz_83; - _zz_84[8] = _zz_83; - _zz_84[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_85 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_86[31] = _zz_85; - _zz_86[30] = _zz_85; - _zz_86[29] = _zz_85; - _zz_86[28] = _zz_85; - _zz_86[27] = _zz_85; - _zz_86[26] = _zz_85; - _zz_86[25] = _zz_85; - _zz_86[24] = _zz_85; - _zz_86[23] = _zz_85; - _zz_86[22] = _zz_85; - _zz_86[21] = _zz_85; - _zz_86[20] = _zz_85; - _zz_86[19] = _zz_85; - _zz_86[18] = _zz_85; - _zz_86[17] = _zz_85; - _zz_86[16] = _zz_85; - _zz_86[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_235) + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_84; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_86; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3464,59 +3611,60 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_88 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_89 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_90 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_91 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_87 = {(((decode_INSTRUCTION & _zz_355) == 32'h00100050) != 1'b0),{(_zz_91 != 1'b0),{(_zz_91 != 1'b0),{(_zz_356 != _zz_357),{_zz_358,{_zz_359,_zz_360}}}}}}; - assign _zz_92 = _zz_87[2 : 1]; - assign _zz_49 = _zz_92; - assign _zz_93 = _zz_87[7 : 6]; - assign _zz_48 = _zz_93; - assign _zz_94 = _zz_87[9 : 8]; - assign _zz_47 = _zz_94; - assign _zz_95 = _zz_87[19 : 18]; - assign _zz_46 = _zz_95; - assign _zz_96 = _zz_87[22 : 21]; - assign _zz_45 = _zz_96; - assign _zz_97 = _zz_87[24 : 23]; - assign _zz_44 = _zz_97; - assign _zz_98 = _zz_87[27 : 26]; - assign _zz_43 = _zz_98; + assign _zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_RS2_SIGNED_4 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_IS_RS2_SIGNED = {(((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED) == 32'h00100050) != 1'b0),{(_zz_decode_IS_RS2_SIGNED_4 != 1'b0),{(_zz_decode_IS_RS2_SIGNED_4 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_1 != _zz__zz_decode_IS_RS2_SIGNED_2),{_zz__zz_decode_IS_RS2_SIGNED_3,{_zz__zz_decode_IS_RS2_SIGNED_5,_zz__zz_decode_IS_RS2_SIGNED_8}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_RS2_SIGNED[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_RS2_SIGNED[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_RS2_SIGNED[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_RS2_SIGNED[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_RS2_SIGNED[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_RS2_SIGNED[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_RS2_SIGNED[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_196; - assign decode_RegFilePlugin_rs2Data = _zz_197; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); - if(_zz_99)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; - if(_zz_99)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_50; - if(_zz_99)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3525,355 +3673,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_100 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_100 = {31'd0, _zz_281}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_100 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_101 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_101 = {29'd0, _zz_282}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_101 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_101 = {27'd0, _zz_283}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_102 = _zz_284[11]; - always @ (*) begin - _zz_103[19] = _zz_102; - _zz_103[18] = _zz_102; - _zz_103[17] = _zz_102; - _zz_103[16] = _zz_102; - _zz_103[15] = _zz_102; - _zz_103[14] = _zz_102; - _zz_103[13] = _zz_102; - _zz_103[12] = _zz_102; - _zz_103[11] = _zz_102; - _zz_103[10] = _zz_102; - _zz_103[9] = _zz_102; - _zz_103[8] = _zz_102; - _zz_103[7] = _zz_102; - _zz_103[6] = _zz_102; - _zz_103[5] = _zz_102; - _zz_103[4] = _zz_102; - _zz_103[3] = _zz_102; - _zz_103[2] = _zz_102; - _zz_103[1] = _zz_102; - _zz_103[0] = _zz_102; - end - - assign _zz_104 = _zz_285[11]; - always @ (*) begin - _zz_105[19] = _zz_104; - _zz_105[18] = _zz_104; - _zz_105[17] = _zz_104; - _zz_105[16] = _zz_104; - _zz_105[15] = _zz_104; - _zz_105[14] = _zz_104; - _zz_105[13] = _zz_104; - _zz_105[12] = _zz_104; - _zz_105[11] = _zz_104; - _zz_105[10] = _zz_104; - _zz_105[9] = _zz_104; - _zz_105[8] = _zz_104; - _zz_105[7] = _zz_104; - _zz_105[6] = _zz_104; - _zz_105[5] = _zz_104; - _zz_105[4] = _zz_104; - _zz_105[3] = _zz_104; - _zz_105[2] = _zz_104; - _zz_105[1] = _zz_104; - _zz_105[0] = _zz_104; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_106 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_106 = {_zz_103,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_106 = {_zz_105,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_106 = _zz_35; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_286; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_107[0] = execute_SRC1[31]; - _zz_107[1] = execute_SRC1[30]; - _zz_107[2] = execute_SRC1[29]; - _zz_107[3] = execute_SRC1[28]; - _zz_107[4] = execute_SRC1[27]; - _zz_107[5] = execute_SRC1[26]; - _zz_107[6] = execute_SRC1[25]; - _zz_107[7] = execute_SRC1[24]; - _zz_107[8] = execute_SRC1[23]; - _zz_107[9] = execute_SRC1[22]; - _zz_107[10] = execute_SRC1[21]; - _zz_107[11] = execute_SRC1[20]; - _zz_107[12] = execute_SRC1[19]; - _zz_107[13] = execute_SRC1[18]; - _zz_107[14] = execute_SRC1[17]; - _zz_107[15] = execute_SRC1[16]; - _zz_107[16] = execute_SRC1[15]; - _zz_107[17] = execute_SRC1[14]; - _zz_107[18] = execute_SRC1[13]; - _zz_107[19] = execute_SRC1[12]; - _zz_107[20] = execute_SRC1[11]; - _zz_107[21] = execute_SRC1[10]; - _zz_107[22] = execute_SRC1[9]; - _zz_107[23] = execute_SRC1[8]; - _zz_107[24] = execute_SRC1[7]; - _zz_107[25] = execute_SRC1[6]; - _zz_107[26] = execute_SRC1[5]; - _zz_107[27] = execute_SRC1[4]; - _zz_107[28] = execute_SRC1[3]; - _zz_107[29] = execute_SRC1[2]; - _zz_107[30] = execute_SRC1[1]; - _zz_107[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_107 : execute_SRC1); - always @ (*) begin - _zz_108[0] = memory_SHIFT_RIGHT[31]; - _zz_108[1] = memory_SHIFT_RIGHT[30]; - _zz_108[2] = memory_SHIFT_RIGHT[29]; - _zz_108[3] = memory_SHIFT_RIGHT[28]; - _zz_108[4] = memory_SHIFT_RIGHT[27]; - _zz_108[5] = memory_SHIFT_RIGHT[26]; - _zz_108[6] = memory_SHIFT_RIGHT[25]; - _zz_108[7] = memory_SHIFT_RIGHT[24]; - _zz_108[8] = memory_SHIFT_RIGHT[23]; - _zz_108[9] = memory_SHIFT_RIGHT[22]; - _zz_108[10] = memory_SHIFT_RIGHT[21]; - _zz_108[11] = memory_SHIFT_RIGHT[20]; - _zz_108[12] = memory_SHIFT_RIGHT[19]; - _zz_108[13] = memory_SHIFT_RIGHT[18]; - _zz_108[14] = memory_SHIFT_RIGHT[17]; - _zz_108[15] = memory_SHIFT_RIGHT[16]; - _zz_108[16] = memory_SHIFT_RIGHT[15]; - _zz_108[17] = memory_SHIFT_RIGHT[14]; - _zz_108[18] = memory_SHIFT_RIGHT[13]; - _zz_108[19] = memory_SHIFT_RIGHT[12]; - _zz_108[20] = memory_SHIFT_RIGHT[11]; - _zz_108[21] = memory_SHIFT_RIGHT[10]; - _zz_108[22] = memory_SHIFT_RIGHT[9]; - _zz_108[23] = memory_SHIFT_RIGHT[8]; - _zz_108[24] = memory_SHIFT_RIGHT[7]; - _zz_108[25] = memory_SHIFT_RIGHT[6]; - _zz_108[26] = memory_SHIFT_RIGHT[5]; - _zz_108[27] = memory_SHIFT_RIGHT[4]; - _zz_108[28] = memory_SHIFT_RIGHT[3]; - _zz_108[29] = memory_SHIFT_RIGHT[2]; - _zz_108[30] = memory_SHIFT_RIGHT[1]; - _zz_108[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_109 = 1'b0; - if(_zz_217)begin - if(_zz_218)begin - if(_zz_114)begin - _zz_109 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_219)begin - if(_zz_220)begin - if(_zz_116)begin - _zz_109 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_221)begin - if(_zz_222)begin - if(_zz_118)begin - _zz_109 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_109 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_110 = 1'b0; - if(_zz_217)begin - if(_zz_218)begin - if(_zz_115)begin - _zz_110 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_219)begin - if(_zz_220)begin - if(_zz_117)begin - _zz_110 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_221)begin - if(_zz_222)begin - if(_zz_119)begin - _zz_110 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_110 = 1'b0; - end - end - - assign _zz_114 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_115 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_116 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_117 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_118 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_119 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_120 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_120 == 3'b000)) begin - _zz_121 = execute_BranchPlugin_eq; - end else if((_zz_120 == 3'b001)) begin - _zz_121 = (! execute_BranchPlugin_eq); - end else if((((_zz_120 & 3'b101) == 3'b101))) begin - _zz_121 = (! execute_SRC_LESS); - end else begin - _zz_121 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_122 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_122 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_122 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_122 = _zz_121; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_123 = _zz_293[11]; - always @ (*) begin - _zz_124[19] = _zz_123; - _zz_124[18] = _zz_123; - _zz_124[17] = _zz_123; - _zz_124[16] = _zz_123; - _zz_124[15] = _zz_123; - _zz_124[14] = _zz_123; - _zz_124[13] = _zz_123; - _zz_124[12] = _zz_123; - _zz_124[11] = _zz_123; - _zz_124[10] = _zz_123; - _zz_124[9] = _zz_123; - _zz_124[8] = _zz_123; - _zz_124[7] = _zz_123; - _zz_124[6] = _zz_123; - _zz_124[5] = _zz_123; - _zz_124[4] = _zz_123; - _zz_124[3] = _zz_123; - _zz_124[2] = _zz_123; - _zz_124[1] = _zz_123; - _zz_124[0] = _zz_123; - end - - assign _zz_125 = _zz_294[19]; - always @ (*) begin - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; - end - - assign _zz_127 = _zz_295[11]; - always @ (*) begin - _zz_128[18] = _zz_127; - _zz_128[17] = _zz_127; - _zz_128[16] = _zz_127; - _zz_128[15] = _zz_127; - _zz_128[14] = _zz_127; - _zz_128[13] = _zz_127; - _zz_128[12] = _zz_127; - _zz_128[11] = _zz_127; - _zz_128[10] = _zz_127; - _zz_128[9] = _zz_127; - _zz_128[8] = _zz_127; - _zz_128[7] = _zz_127; - _zz_128[6] = _zz_127; - _zz_128[5] = _zz_127; - _zz_128[4] = _zz_127; - _zz_128[3] = _zz_127; - _zz_128[2] = _zz_127; - _zz_128[1] = _zz_127; - _zz_128[0] = _zz_127; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_129 = (_zz_296[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_129 = _zz_297[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_129 = _zz_298[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_129); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -3882,80 +4053,80 @@ module VexRiscv ( endcase end - assign _zz_130 = _zz_299[11]; - always @ (*) begin - _zz_131[19] = _zz_130; - _zz_131[18] = _zz_130; - _zz_131[17] = _zz_130; - _zz_131[16] = _zz_130; - _zz_131[15] = _zz_130; - _zz_131[14] = _zz_130; - _zz_131[13] = _zz_130; - _zz_131[12] = _zz_130; - _zz_131[11] = _zz_130; - _zz_131[10] = _zz_130; - _zz_131[9] = _zz_130; - _zz_131[8] = _zz_130; - _zz_131[7] = _zz_130; - _zz_131[6] = _zz_130; - _zz_131[5] = _zz_130; - _zz_131[4] = _zz_130; - _zz_131[3] = _zz_130; - _zz_131[2] = _zz_130; - _zz_131[1] = _zz_130; - _zz_131[0] = _zz_130; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_131,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_133,{{{_zz_513,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_135,{{{_zz_514,_zz_515},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_302}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_132 = _zz_300[19]; - always @ (*) begin - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; - end - - assign _zz_134 = _zz_301[11]; - always @ (*) begin - _zz_135[18] = _zz_134; - _zz_135[17] = _zz_134; - _zz_135[16] = _zz_134; - _zz_135[15] = _zz_134; - _zz_135[14] = _zz_134; - _zz_135[13] = _zz_134; - _zz_135[12] = _zz_134; - _zz_135[11] = _zz_134; - _zz_135[10] = _zz_134; - _zz_135[9] = _zz_134; - _zz_135[8] = _zz_134; - _zz_135[7] = _zz_134; - _zz_135[6] = _zz_134; - _zz_135[5] = _zz_134; - _zz_135[4] = _zz_134; - _zz_135[3] = _zz_134; - _zz_135[2] = _zz_134; - _zz_135[1] = _zz_134; - _zz_135[0] = _zz_134; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -3965,95 +4136,109 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_136 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_137 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_138 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_139 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_140 = _zz_303[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_209)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4064,8 +4249,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4075,77 +4260,84 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_223)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_224)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_224)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4158,39 +4350,48 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_223)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_223)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_236) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_225) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4203,8 +4404,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_225) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4223,58 +4424,69 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_305) + $signed(_zz_306)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_204)begin - if(_zz_226)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_227)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_310); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_141 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_141[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_311); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_312 : _zz_313); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_314[31:0]; - assign _zz_142 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_143 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_144 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_145[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_145[31 : 0] = execute_RS1; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; end - assign _zz_147 = (_zz_146 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_147 != 32'h0); - always @ (*) begin + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_228) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end end @@ -4284,9 +4496,9 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_148))begin + if(when_DebugPlugin_l244) begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4295,12 +4507,13 @@ module VexRiscv ( end end - always @ (*) begin + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_228) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin IBusCachedPlugin_injectionPort_valid = 1'b1; end end @@ -4311,35 +4524,110 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_26 = decode_SRC1_CTRL; - assign _zz_24 = _zz_49; - assign _zz_37 = decode_to_execute_SRC1_CTRL; - assign _zz_23 = decode_ALU_CTRL; - assign _zz_21 = _zz_48; - assign _zz_38 = decode_to_execute_ALU_CTRL; - assign _zz_20 = decode_SRC2_CTRL; - assign _zz_18 = _zz_47; - assign _zz_36 = decode_to_execute_SRC2_CTRL; - assign _zz_17 = decode_ALU_BITWISE_CTRL; - assign _zz_15 = _zz_46; - assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_14 = decode_SHIFT_CTRL; - assign _zz_11 = execute_SHIFT_CTRL; - assign _zz_12 = _zz_45; - assign _zz_34 = decode_to_execute_SHIFT_CTRL; - assign _zz_33 = execute_to_memory_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_51 = _zz_44; - assign _zz_30 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_43; - assign _zz_28 = decode_to_execute_ENV_CTRL; - assign _zz_27 = execute_to_memory_ENV_CTRL; - assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4360,9 +4648,15 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_149) + case(switch_Fetcher_l362) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4371,140 +4665,154 @@ module VexRiscv ( endcase end - always @ (*) begin - _zz_150 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_150[12 : 0] = 13'h1000; - _zz_150[25 : 20] = 6'h20; + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_151 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_151[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_151[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_151[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_152 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_152[11 : 11] = CsrPlugin_mip_MEIP; - _zz_152[7 : 7] = CsrPlugin_mip_MTIP; - _zz_152[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_153 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_153[11 : 11] = CsrPlugin_mie_MEIE; - _zz_153[7 : 7] = CsrPlugin_mie_MTIE; - _zz_153[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_154 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_154[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_155 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_155[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_155[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_156 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_156[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_157 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_157[31 : 0] = _zz_146; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_158 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_158[31 : 0] = _zz_147; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = ((((_zz_150 | _zz_151) | (_zz_152 | _zz_153)) | ((_zz_154 | _zz_155) | (_zz_156 | _zz_157))) | _zz_158); - assign iBusWishbone_ADR = {_zz_330,_zz_159}; - assign iBusWishbone_CTI = ((_zz_159 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = ((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))) | _zz_CsrPlugin_csrMapping_readDataInit_10); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_229)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_229)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_160; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_166 = (dBus_cmd_payload_length != 3'b000); - assign _zz_162 = dBus_cmd_valid; - assign _zz_164 = dBus_cmd_payload_wr; - assign _zz_165 = (_zz_161 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_163 && (_zz_164 || _zz_165)); - assign dBusWishbone_ADR = ((_zz_166 ? {{dBus_cmd_payload_address[31 : 5],_zz_161},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_166 ? (_zz_165 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_164 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_164; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_163 = (_zz_162 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_162; - assign dBusWishbone_STB = _zz_162; - assign dBus_rsp_valid = _zz_167; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_65 <= 1'b0; - _zz_67 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_80; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_81; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_99 <= 1'b1; - _zz_111 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -4522,159 +4830,159 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_146 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_149 <= 3'b000; - _zz_159 <= 3'b000; - _zz_160 <= 1'b0; - _zz_161 <= 3'b000; - _zz_167 <= 1'b0; + switch_Fetcher_l362 <= 3'b000; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_65 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_63)begin - _zz_65 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_67 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_67 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_230)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_99 <= 1'b0; - _zz_111 <= (_zz_41 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_231)begin - if(_zz_232)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_233)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_234)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_212)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4685,8 +4993,8 @@ module VexRiscv ( end endcase end - if(_zz_213)begin - case(_zz_215) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4696,158 +5004,158 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_138,{_zz_137,_zz_136}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_149) + case(switch_Fetcher_l362) 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_149 <= 3'b001; + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; end end 3'b001 : begin - _zz_149 <= 3'b010; + switch_Fetcher_l362 <= 3'b010; end 3'b010 : begin - _zz_149 <= 3'b011; + switch_Fetcher_l362 <= 3'b011; end 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_149 <= 3'b100; + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; end end 3'b100 : begin - _zz_149 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; end default : begin end endcase - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_324[0]; - CsrPlugin_mstatus_MIE <= _zz_325[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_327[0]; - CsrPlugin_mie_MTIE <= _zz_328[0]; - CsrPlugin_mie_MSIE <= _zz_329[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_229)begin - if(iBusWishbone_ACK)begin - _zz_159 <= (_zz_159 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_160 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_162 && _zz_163))begin - _zz_161 <= (_zz_161 + 3'b001); - if(_zz_165)begin - _zz_161 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_167 <= ((_zz_162 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_68 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_230)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_112 <= _zz_40[11 : 7]; - _zz_113 <= _zz_50; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_209)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_140 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_140 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_231)begin - if(_zz_232)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_233)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_234)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_212)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -4855,332 +5163,343 @@ module VexRiscv ( end endcase end - if((memory_DivPlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_DivPlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_204)begin - if(_zz_226)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_315[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; end end end - if(_zz_227)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_144 ? (~ _zz_145) : _zz_145) + _zz_321); - memory_DivPlugin_rs2 <= ((_zz_143 ? (~ execute_RS2) : execute_RS2) + _zz_323); - memory_DivPlugin_div_needRevert <= ((_zz_144 ^ (_zz_143 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_35; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_7) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_25; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_22; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_19; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_10; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_50) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_51) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + if(when_Pipeline_l124_52) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + if(when_Pipeline_l124_53) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_54) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_62) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_326[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end - always @ (posedge clk) begin + always @(posedge clk) begin DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin + if(debug_bus_cmd_ready) begin DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_50; + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; end - _zz_148 <= debug_bus_cmd_payload_address[2]; - if(_zz_210)begin + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin + always @(posedge clk) begin if(debugReset) begin DebugPlugin_resetIt <= 1'b0; DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + if(when_DebugPlugin_l225) begin DebugPlugin_godmode <= 1'b1; end - if(debug_bus_cmd_valid)begin - case(_zz_228) + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin + if(when_DebugPlugin_l260) begin DebugPlugin_resetIt <= 1'b1; end - if(debug_bus_cmd_payload_data[24])begin + if(when_DebugPlugin_l260_1) begin DebugPlugin_resetIt <= 1'b0; end - if(debug_bus_cmd_payload_data[17])begin + if(when_DebugPlugin_l261) begin DebugPlugin_haltIt <= 1'b1; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l261_1) begin DebugPlugin_haltIt <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l262) begin DebugPlugin_haltedByBreak <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l263) begin DebugPlugin_godmode <= 1'b0; end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end end end default : begin end endcase end - if(_zz_210)begin - if(_zz_211)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_214)begin - if(decode_arbitration_isValid)begin + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin DebugPlugin_haltIt <= 1'b1; end end @@ -5193,9 +5512,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -5217,6 +5535,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -5232,9 +5551,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -5242,7 +5562,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -5251,24 +5571,15 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -5293,40 +5604,48 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5336,23 +5655,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -5360,10 +5689,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -5375,59 +5712,54 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -5442,274 +5774,293 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -5717,89 +6068,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_16)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -5807,12 +6142,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -5823,20 +6158,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -5844,45 +6199,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -5893,46 +6250,37 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; @@ -5940,50 +6288,51 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6030,18 +6379,14 @@ module InstructionCache ( input io_mem_rsp_valid, input [31:0] io_mem_rsp_payload_data, input io_mem_rsp_payload_error, - input [2:0] _zz_9, - input [31:0] _zz_10, + input [2:0] _zz_when_Fetcher_l398, + input [31:0] _zz_io_cpu_fetch_data_regNextWhen, input clk, input reset ); - reg [31:0] _zz_11; - reg [21:0] _zz_12; - wire _zz_13; - wire _zz_14; - wire [0:0] _zz_15; - wire [0:0] _zz_16; - wire [21:0] _zz_17; + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6050,8 +6395,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -6065,22 +6415,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -6090,82 +6443,86 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; + wire when_Fetcher_l398; (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - assign _zz_13 = (! lineLoader_flushCounter[7]); - assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_15 = _zz_8[0 : 0]; - assign _zz_16 = _zz_8[1 : 1]; - assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_11 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_12 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_13)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -6181,30 +6538,36 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_12; - assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000); + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -6212,51 +6575,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_14)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_13)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_14)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 8'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -6267,14 +6630,14 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end - if((_zz_9 != 3'b000))begin - io_cpu_fetch_data_regNextWhen <= _zz_10; + if(when_Fetcher_l398) begin + io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v index a3a8c57..e637b47 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Fomu.v @@ -1,46 +1,46 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : d8ec2d84c3160c3a9131beef2db359dce7a2e4a4 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b10 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -73,18 +73,17 @@ module VexRiscv ( input clk, input reset ); - wire _zz_128; - wire _zz_129; - wire _zz_130; - wire _zz_131; - wire _zz_132; - wire _zz_133; - wire _zz_134; - wire _zz_135; - reg _zz_136; - reg [31:0] _zz_137; - reg [31:0] _zz_138; - reg [31:0] _zz_139; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -97,245 +96,201 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_140; - wire _zz_141; - wire _zz_142; - wire _zz_143; - wire _zz_144; - wire [1:0] _zz_145; - wire _zz_146; - wire _zz_147; - wire _zz_148; - wire _zz_149; - wire _zz_150; - wire _zz_151; - wire _zz_152; - wire _zz_153; - wire _zz_154; - wire [1:0] _zz_155; - wire _zz_156; - wire _zz_157; - wire _zz_158; - wire _zz_159; - wire _zz_160; - wire _zz_161; - wire [1:0] _zz_162; - wire _zz_163; - wire [1:0] _zz_164; - wire [51:0] _zz_165; - wire [51:0] _zz_166; - wire [51:0] _zz_167; - wire [32:0] _zz_168; - wire [51:0] _zz_169; - wire [49:0] _zz_170; - wire [51:0] _zz_171; - wire [49:0] _zz_172; - wire [51:0] _zz_173; - wire [32:0] _zz_174; - wire [31:0] _zz_175; - wire [32:0] _zz_176; - wire [0:0] _zz_177; - wire [0:0] _zz_178; - wire [0:0] _zz_179; - wire [0:0] _zz_180; - wire [0:0] _zz_181; - wire [0:0] _zz_182; - wire [0:0] _zz_183; - wire [0:0] _zz_184; - wire [0:0] _zz_185; - wire [0:0] _zz_186; - wire [0:0] _zz_187; - wire [0:0] _zz_188; - wire [0:0] _zz_189; - wire [2:0] _zz_190; - wire [2:0] _zz_191; - wire [31:0] _zz_192; - wire [0:0] _zz_193; - wire [2:0] _zz_194; - wire [4:0] _zz_195; - wire [11:0] _zz_196; - wire [11:0] _zz_197; - wire [31:0] _zz_198; - wire [31:0] _zz_199; - wire [31:0] _zz_200; - wire [31:0] _zz_201; - wire [31:0] _zz_202; - wire [31:0] _zz_203; - wire [31:0] _zz_204; - wire [19:0] _zz_205; - wire [11:0] _zz_206; - wire [11:0] _zz_207; - wire [65:0] _zz_208; - wire [65:0] _zz_209; - wire [31:0] _zz_210; - wire [31:0] _zz_211; - wire [0:0] _zz_212; - wire [0:0] _zz_213; - wire [0:0] _zz_214; - wire [0:0] _zz_215; - wire [0:0] _zz_216; - wire [0:0] _zz_217; - wire [26:0] _zz_218; - wire _zz_219; - wire _zz_220; - wire [1:0] _zz_221; - wire [31:0] _zz_222; - wire [31:0] _zz_223; - wire [31:0] _zz_224; - wire _zz_225; - wire [0:0] _zz_226; - wire [13:0] _zz_227; - wire [31:0] _zz_228; - wire [31:0] _zz_229; - wire [31:0] _zz_230; - wire _zz_231; - wire [0:0] _zz_232; - wire [7:0] _zz_233; - wire [31:0] _zz_234; - wire [31:0] _zz_235; - wire [31:0] _zz_236; - wire _zz_237; - wire [0:0] _zz_238; - wire [1:0] _zz_239; - wire [31:0] _zz_240; - wire [31:0] _zz_241; - wire [31:0] _zz_242; - wire _zz_243; - wire [1:0] _zz_244; - wire [1:0] _zz_245; - wire _zz_246; - wire [0:0] _zz_247; - wire [21:0] _zz_248; - wire [31:0] _zz_249; - wire [31:0] _zz_250; - wire [31:0] _zz_251; - wire [31:0] _zz_252; - wire _zz_253; - wire _zz_254; - wire [1:0] _zz_255; - wire [1:0] _zz_256; - wire _zz_257; - wire [0:0] _zz_258; - wire [18:0] _zz_259; - wire [31:0] _zz_260; - wire [31:0] _zz_261; - wire [31:0] _zz_262; - wire [31:0] _zz_263; - wire [31:0] _zz_264; - wire [31:0] _zz_265; - wire [0:0] _zz_266; - wire [1:0] _zz_267; - wire [0:0] _zz_268; - wire [0:0] _zz_269; - wire _zz_270; - wire [0:0] _zz_271; - wire [15:0] _zz_272; - wire [31:0] _zz_273; - wire [31:0] _zz_274; - wire [31:0] _zz_275; - wire [31:0] _zz_276; - wire [31:0] _zz_277; - wire [31:0] _zz_278; - wire [31:0] _zz_279; - wire [31:0] _zz_280; - wire _zz_281; - wire [1:0] _zz_282; - wire [1:0] _zz_283; - wire _zz_284; - wire [0:0] _zz_285; - wire [12:0] _zz_286; - wire [31:0] _zz_287; - wire [31:0] _zz_288; - wire [31:0] _zz_289; - wire [31:0] _zz_290; - wire [31:0] _zz_291; - wire [31:0] _zz_292; - wire [1:0] _zz_293; - wire [1:0] _zz_294; - wire _zz_295; - wire [0:0] _zz_296; - wire [9:0] _zz_297; - wire [31:0] _zz_298; - wire [31:0] _zz_299; - wire [31:0] _zz_300; - wire _zz_301; - wire [0:0] _zz_302; - wire [1:0] _zz_303; - wire [0:0] _zz_304; - wire [3:0] _zz_305; - wire [5:0] _zz_306; - wire [5:0] _zz_307; - wire _zz_308; - wire [0:0] _zz_309; - wire [5:0] _zz_310; - wire [31:0] _zz_311; - wire [31:0] _zz_312; - wire [31:0] _zz_313; - wire [31:0] _zz_314; - wire [31:0] _zz_315; - wire [31:0] _zz_316; - wire _zz_317; - wire [0:0] _zz_318; - wire [0:0] _zz_319; - wire _zz_320; - wire [0:0] _zz_321; - wire [2:0] _zz_322; - wire _zz_323; - wire [0:0] _zz_324; - wire [0:0] _zz_325; - wire [3:0] _zz_326; - wire [3:0] _zz_327; - wire _zz_328; - wire [0:0] _zz_329; - wire [2:0] _zz_330; - wire [31:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [31:0] _zz_334; - wire [31:0] _zz_335; - wire [31:0] _zz_336; - wire [31:0] _zz_337; - wire [31:0] _zz_338; - wire _zz_339; - wire [0:0] _zz_340; - wire [0:0] _zz_341; - wire [31:0] _zz_342; - wire [31:0] _zz_343; - wire [31:0] _zz_344; - wire _zz_345; - wire [0:0] _zz_346; - wire [1:0] _zz_347; - wire _zz_348; - wire [2:0] _zz_349; - wire [2:0] _zz_350; - wire _zz_351; - wire [0:0] _zz_352; - wire [0:0] _zz_353; - wire [31:0] _zz_354; - wire [31:0] _zz_355; - wire [31:0] _zz_356; - wire [31:0] _zz_357; - wire [31:0] _zz_358; - wire [31:0] _zz_359; - wire [31:0] _zz_360; - wire [31:0] _zz_361; - wire _zz_362; - wire [31:0] _zz_363; - wire _zz_364; - wire [0:0] _zz_365; - wire [0:0] _zz_366; - wire [0:0] _zz_367; - wire [0:0] _zz_368; - wire [1:0] _zz_369; - wire [1:0] _zz_370; - wire [0:0] _zz_371; - wire [0:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire [31:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire [31:0] _zz_378; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [31:0] _zz__zz_decode_IS_MUL; + wire [31:0] _zz__zz_decode_IS_MUL_1; + wire [31:0] _zz__zz_decode_IS_MUL_2; + wire _zz__zz_decode_IS_MUL_3; + wire [1:0] _zz__zz_decode_IS_MUL_4; + wire [31:0] _zz__zz_decode_IS_MUL_5; + wire [31:0] _zz__zz_decode_IS_MUL_6; + wire [31:0] _zz__zz_decode_IS_MUL_7; + wire [31:0] _zz__zz_decode_IS_MUL_8; + wire [1:0] _zz__zz_decode_IS_MUL_9; + wire _zz__zz_decode_IS_MUL_10; + wire _zz__zz_decode_IS_MUL_11; + wire [0:0] _zz__zz_decode_IS_MUL_12; + wire _zz__zz_decode_IS_MUL_13; + wire [21:0] _zz__zz_decode_IS_MUL_14; + wire [1:0] _zz__zz_decode_IS_MUL_15; + wire [31:0] _zz__zz_decode_IS_MUL_16; + wire [31:0] _zz__zz_decode_IS_MUL_17; + wire [31:0] _zz__zz_decode_IS_MUL_18; + wire [31:0] _zz__zz_decode_IS_MUL_19; + wire [1:0] _zz__zz_decode_IS_MUL_20; + wire _zz__zz_decode_IS_MUL_21; + wire [31:0] _zz__zz_decode_IS_MUL_22; + wire [31:0] _zz__zz_decode_IS_MUL_23; + wire [0:0] _zz__zz_decode_IS_MUL_24; + wire [0:0] _zz__zz_decode_IS_MUL_25; + wire [31:0] _zz__zz_decode_IS_MUL_26; + wire [1:0] _zz__zz_decode_IS_MUL_27; + wire [31:0] _zz__zz_decode_IS_MUL_28; + wire [31:0] _zz__zz_decode_IS_MUL_29; + wire [31:0] _zz__zz_decode_IS_MUL_30; + wire [31:0] _zz__zz_decode_IS_MUL_31; + wire [18:0] _zz__zz_decode_IS_MUL_32; + wire [0:0] _zz__zz_decode_IS_MUL_33; + wire [31:0] _zz__zz_decode_IS_MUL_34; + wire [0:0] _zz__zz_decode_IS_MUL_35; + wire _zz__zz_decode_IS_MUL_36; + wire [31:0] _zz__zz_decode_IS_MUL_37; + wire [31:0] _zz__zz_decode_IS_MUL_38; + wire [0:0] _zz__zz_decode_IS_MUL_39; + wire _zz__zz_decode_IS_MUL_40; + wire [15:0] _zz__zz_decode_IS_MUL_41; + wire [1:0] _zz__zz_decode_IS_MUL_42; + wire [31:0] _zz__zz_decode_IS_MUL_43; + wire [31:0] _zz__zz_decode_IS_MUL_44; + wire [31:0] _zz__zz_decode_IS_MUL_45; + wire [31:0] _zz__zz_decode_IS_MUL_46; + wire [1:0] _zz__zz_decode_IS_MUL_47; + wire _zz__zz_decode_IS_MUL_48; + wire [31:0] _zz__zz_decode_IS_MUL_49; + wire [31:0] _zz__zz_decode_IS_MUL_50; + wire [0:0] _zz__zz_decode_IS_MUL_51; + wire [12:0] _zz__zz_decode_IS_MUL_52; + wire [1:0] _zz__zz_decode_IS_MUL_53; + wire [31:0] _zz__zz_decode_IS_MUL_54; + wire [31:0] _zz__zz_decode_IS_MUL_55; + wire [1:0] _zz__zz_decode_IS_MUL_56; + wire _zz__zz_decode_IS_MUL_57; + wire [31:0] _zz__zz_decode_IS_MUL_58; + wire [0:0] _zz__zz_decode_IS_MUL_59; + wire _zz__zz_decode_IS_MUL_60; + wire [0:0] _zz__zz_decode_IS_MUL_61; + wire [1:0] _zz__zz_decode_IS_MUL_62; + wire [31:0] _zz__zz_decode_IS_MUL_63; + wire [31:0] _zz__zz_decode_IS_MUL_64; + wire [31:0] _zz__zz_decode_IS_MUL_65; + wire [31:0] _zz__zz_decode_IS_MUL_66; + wire [9:0] _zz__zz_decode_IS_MUL_67; + wire [0:0] _zz__zz_decode_IS_MUL_68; + wire [3:0] _zz__zz_decode_IS_MUL_69; + wire [31:0] _zz__zz_decode_IS_MUL_70; + wire [31:0] _zz__zz_decode_IS_MUL_71; + wire _zz__zz_decode_IS_MUL_72; + wire [31:0] _zz__zz_decode_IS_MUL_73; + wire [0:0] _zz__zz_decode_IS_MUL_74; + wire [31:0] _zz__zz_decode_IS_MUL_75; + wire [31:0] _zz__zz_decode_IS_MUL_76; + wire [0:0] _zz__zz_decode_IS_MUL_77; + wire [31:0] _zz__zz_decode_IS_MUL_78; + wire [31:0] _zz__zz_decode_IS_MUL_79; + wire [5:0] _zz__zz_decode_IS_MUL_80; + wire _zz__zz_decode_IS_MUL_81; + wire [31:0] _zz__zz_decode_IS_MUL_82; + wire [0:0] _zz__zz_decode_IS_MUL_83; + wire [31:0] _zz__zz_decode_IS_MUL_84; + wire [31:0] _zz__zz_decode_IS_MUL_85; + wire [2:0] _zz__zz_decode_IS_MUL_86; + wire _zz__zz_decode_IS_MUL_87; + wire [31:0] _zz__zz_decode_IS_MUL_88; + wire [0:0] _zz__zz_decode_IS_MUL_89; + wire [31:0] _zz__zz_decode_IS_MUL_90; + wire [31:0] _zz__zz_decode_IS_MUL_91; + wire [0:0] _zz__zz_decode_IS_MUL_92; + wire [31:0] _zz__zz_decode_IS_MUL_93; + wire [31:0] _zz__zz_decode_IS_MUL_94; + wire [5:0] _zz__zz_decode_IS_MUL_95; + wire _zz__zz_decode_IS_MUL_96; + wire _zz__zz_decode_IS_MUL_97; + wire [31:0] _zz__zz_decode_IS_MUL_98; + wire [0:0] _zz__zz_decode_IS_MUL_99; + wire [0:0] _zz__zz_decode_IS_MUL_100; + wire [0:0] _zz__zz_decode_IS_MUL_101; + wire [31:0] _zz__zz_decode_IS_MUL_102; + wire [31:0] _zz__zz_decode_IS_MUL_103; + wire [5:0] _zz__zz_decode_IS_MUL_104; + wire [3:0] _zz__zz_decode_IS_MUL_105; + wire _zz__zz_decode_IS_MUL_106; + wire [31:0] _zz__zz_decode_IS_MUL_107; + wire [0:0] _zz__zz_decode_IS_MUL_108; + wire [31:0] _zz__zz_decode_IS_MUL_109; + wire [31:0] _zz__zz_decode_IS_MUL_110; + wire [1:0] _zz__zz_decode_IS_MUL_111; + wire _zz__zz_decode_IS_MUL_112; + wire [3:0] _zz__zz_decode_IS_MUL_113; + wire _zz__zz_decode_IS_MUL_114; + wire _zz__zz_decode_IS_MUL_115; + wire [31:0] _zz__zz_decode_IS_MUL_116; + wire [0:0] _zz__zz_decode_IS_MUL_117; + wire [2:0] _zz__zz_decode_IS_MUL_118; + wire _zz__zz_decode_IS_MUL_119; + wire [0:0] _zz__zz_decode_IS_MUL_120; + wire [31:0] _zz__zz_decode_IS_MUL_121; + wire [0:0] _zz__zz_decode_IS_MUL_122; + wire [31:0] _zz__zz_decode_IS_MUL_123; + wire [2:0] _zz__zz_decode_IS_MUL_124; + wire [2:0] _zz__zz_decode_IS_MUL_125; + wire _zz__zz_decode_IS_MUL_126; + wire [0:0] _zz__zz_decode_IS_MUL_127; + wire [31:0] _zz__zz_decode_IS_MUL_128; + wire [0:0] _zz__zz_decode_IS_MUL_129; + wire [0:0] _zz__zz_decode_IS_MUL_130; + wire [1:0] _zz__zz_decode_IS_MUL_131; + wire [31:0] _zz__zz_decode_IS_MUL_132; + wire [31:0] _zz__zz_decode_IS_MUL_133; + wire [1:0] _zz__zz_decode_IS_MUL_134; + wire [0:0] _zz__zz_decode_IS_MUL_135; + wire [0:0] _zz__zz_decode_IS_MUL_136; + wire [31:0] _zz__zz_decode_IS_MUL_137; + wire [0:0] _zz__zz_decode_IS_MUL_138; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_lastStageRegFileWrite_payload_data; + wire [31:0] _zz__zz_lastStageRegFileWrite_payload_data_1; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire [31:0] memory_MEMORY_READ_DATA; wire [33:0] memory_MUL_HH; @@ -347,6 +302,7 @@ module VexRiscv ( wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] memory_REGFILE_WRITE_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; wire [1:0] memory_MEMORY_ADDRESS_LOW; wire [1:0] execute_MEMORY_ADDRESS_LOW; @@ -358,72 +314,74 @@ module VexRiscv ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `BranchCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_19; - wire `AluCtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `Src2CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire decode_MEMORY_ENABLE; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; wire writeBack_IS_MUL; wire [33:0] writeBack_MUL_HH; wire [51:0] writeBack_MUL_LOW; wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; - reg [31:0] _zz_28; + reg [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_30; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_31; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_32; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; @@ -433,87 +391,64 @@ module VexRiscv ( wire memory_BYPASSABLE_MEMORY_STAGE; wire writeBack_REGFILE_WRITE_VALID; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_33; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_35; + reg [31:0] _zz_memory_to_writeBack_REGFILE_WRITE_DATA; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_36; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_37; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_38; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_39; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_40; - wire [31:0] _zz_41; - wire _zz_42; - reg _zz_43; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_44; - wire `BranchCtrlEnum_defaultEncoding_type _zz_45; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_46; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47; - wire `AluCtrlEnum_defaultEncoding_type _zz_48; - wire `Src2CtrlEnum_defaultEncoding_type _zz_49; - wire `Src1CtrlEnum_defaultEncoding_type _zz_50; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; wire writeBack_MEMORY_STORE; - reg [31:0] _zz_51; + reg [31:0] _zz_lastStageRegFileWrite_payload_data; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP2_physicalAddress; - wire memory_MMU_RSP2_isIoAccess; - wire memory_MMU_RSP2_isPaging; - wire memory_MMU_RSP2_allowRead; - wire memory_MMU_RSP2_allowWrite; - wire memory_MMU_RSP2_allowExecute; - wire memory_MMU_RSP2_exception; - wire memory_MMU_RSP2_refilling; - wire memory_MMU_RSP2_bypassTranslation; - wire [31:0] memory_PC; - wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP2_physicalAddress; - wire execute_MMU_RSP2_isIoAccess; - wire execute_MMU_RSP2_isPaging; - wire execute_MMU_RSP2_allowRead; - wire execute_MMU_RSP2_allowWrite; - wire execute_MMU_RSP2_allowExecute; - wire execute_MMU_RSP2_exception; - wire execute_MMU_RSP2_refilling; - wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; - wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_52; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; + wire decode_arbitration_haltItself; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; wire decode_arbitration_flushIt; @@ -538,7 +473,7 @@ module VexRiscv ( reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; + wire memory_arbitration_flushIt; reg memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; @@ -582,31 +517,16 @@ module VexRiscv ( wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; wire IBusCachedPlugin_mmuBus_end; wire IBusCachedPlugin_mmuBus_busy; - reg DBusSimplePlugin_memoryExceptionPort_valid; - reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; - wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_0_isValid; - wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_isPaging; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; wire CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -624,27 +544,30 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_53; - wire [2:0] _zz_54; - wire _zz_55; - wire _zz_56; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -667,16 +590,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_57; - wire _zz_58; - wire _zz_59; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_60; - wire _zz_61; - reg _zz_62; - wire _zz_63; - reg _zz_64; - reg [31:0] _zz_65; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -684,11 +609,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l329_4; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -696,7 +628,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_66; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -704,6 +636,9 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l267; wire dBus_cmd_valid; wire dBus_cmd_ready; wire dBus_cmd_payload_wr; @@ -713,29 +648,34 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - wire _zz_67; + wire _zz_dBus_cmd_valid; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_68; - reg [3:0] _zz_69; + reg [31:0] _zz_dBus_cmd_payload_data; + wire when_DBusSimplePlugin_l426; + reg [3:0] _zz_execute_DBusSimplePlugin_formalMask; wire [3:0] execute_DBusSimplePlugin_formalMask; + wire when_DBusSimplePlugin_l479; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_70; - reg [31:0] _zz_71; - wire _zz_72; - reg [31:0] _zz_73; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusSimplePlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1; + wire _zz_writeBack_DBusSimplePlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3; reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [27:0] _zz_74; - wire _zz_75; - wire _zz_76; - wire _zz_77; - wire _zz_78; - wire `Src1CtrlEnum_defaultEncoding_type _zz_79; - wire `Src2CtrlEnum_defaultEncoding_type _zz_80; - wire `AluCtrlEnum_defaultEncoding_type _zz_81; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_82; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_83; - wire `BranchCtrlEnum_defaultEncoding_type _zz_84; - wire `EnvCtrlEnum_defaultEncoding_type _zz_85; + wire when_DBusSimplePlugin_l558; + wire [27:0] _zz_decode_IS_MUL; + wire _zz_decode_IS_MUL_1; + wire _zz_decode_IS_MUL_2; + wire _zz_decode_IS_MUL_3; + wire _zz_decode_IS_MUL_4; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -743,37 +683,58 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_86; + reg _zz_2; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_87; - reg [31:0] _zz_88; - wire _zz_89; - reg [19:0] _zz_90; - wire _zz_91; - reg [19:0] _zz_92; - reg [31:0] _zz_93; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_94; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_95; - reg _zz_96; - reg _zz_97; - reg _zz_98; - reg [4:0] _zz_99; + reg [31:0] _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l59; + wire when_HazardSimplePlugin_l62; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l59_1; + wire when_HazardSimplePlugin_l62_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l59_2; + wire when_HazardSimplePlugin_l62_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_100; - reg _zz_101; - reg _zz_102; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_DO; + reg _zz_execute_BRANCH_DO_1; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_103; - reg [10:0] _zz_104; - wire _zz_105; - reg [19:0] _zz_106; - wire _zz_107; - reg [18:0] _zz_108; - reg [31:0] _zz_109; + wire _zz_execute_BranchPlugin_branch_src2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -795,9 +756,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_110; - wire _zz_111; - wire _zz_112; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -810,38 +771,62 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -849,98 +834,166 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_113; - wire [31:0] _zz_114; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_9; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg memory_to_writeBack_MEMORY_ENABLE; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_14; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_16; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_19; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_20; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_MEMORY_STORE; + wire when_Pipeline_l124_22; reg execute_to_memory_MEMORY_STORE; + wire when_Pipeline_l124_23; reg memory_to_writeBack_MEMORY_STORE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_24; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_25; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_26; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_27; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_28; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_29; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_30; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_31; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_32; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_34; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_35; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_36; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_37; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_38; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_39; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_40; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_41; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_42; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_43; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_MMU_FAULT; - reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; - reg execute_to_memory_MMU_RSP2_isIoAccess; - reg execute_to_memory_MMU_RSP2_isPaging; - reg execute_to_memory_MMU_RSP2_allowRead; - reg execute_to_memory_MMU_RSP2_allowWrite; - reg execute_to_memory_MMU_RSP2_allowExecute; - reg execute_to_memory_MMU_RSP2_exception; - reg execute_to_memory_MMU_RSP2_refilling; - reg execute_to_memory_MMU_RSP2_bypassTranslation; + wire when_Pipeline_l124_44; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_45; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_46; reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_47; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_48; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_49; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_50; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_51; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_52; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_53; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_54; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + wire when_Pipeline_l124_55; reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_115; - reg [31:0] _zz_116; - reg [31:0] _zz_117; - reg [31:0] _zz_118; - reg [31:0] _zz_119; - reg [31:0] _zz_120; - reg [31:0] _zz_121; - reg [31:0] _zz_122; - reg [31:0] _zz_123; - reg [31:0] _zz_124; - reg [2:0] _zz_125; - reg _zz_126; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -948,82 +1001,83 @@ module VexRiscv ( wire [31:0] dBus_cmd_halfPipe_payload_address; wire [31:0] dBus_cmd_halfPipe_payload_data; wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_127; + reg dBus_cmd_rValid; + wire dBus_cmd_halfPipe_fire; + reg dBus_cmd_rData_wr; + reg [31:0] dBus_cmd_rData_address; + reg [31:0] dBus_cmd_rData_data; + reg [1:0] dBus_cmd_rData_size; + reg [3:0] _zz_dBusWishbone_SEL; + wire when_DBusSimplePlugin_l189; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [31:0] _zz_10_string; - reg [71:0] _zz_11_string; - reg [71:0] _zz_12_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; - reg [71:0] _zz_15_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_16_string; - reg [39:0] _zz_17_string; - reg [39:0] _zz_18_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_19_string; - reg [63:0] _zz_20_string; - reg [63:0] _zz_21_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_22_string; - reg [23:0] _zz_23_string; - reg [23:0] _zz_24_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_25_string; - reg [95:0] _zz_26_string; - reg [95:0] _zz_27_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_30_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_31_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_32_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_34_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_35_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_37_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_38_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_39_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_40_string; - reg [39:0] _zz_44_string; - reg [31:0] _zz_45_string; - reg [71:0] _zz_46_string; - reg [39:0] _zz_47_string; - reg [63:0] _zz_48_string; - reg [23:0] _zz_49_string; - reg [95:0] _zz_50_string; - reg [95:0] _zz_79_string; - reg [23:0] _zz_80_string; - reg [63:0] _zz_81_string; - reg [39:0] _zz_82_string; - reg [71:0] _zz_83_string; - reg [31:0] _zz_84_string; - reg [39:0] _zz_85_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; @@ -1038,988 +1092,928 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_140 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_141 = ((_zz_133 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_142 = ((_zz_133 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_143 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_144 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_145 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_146 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_147 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_148 = (1'b1 || (! 1'b1)); - assign _zz_149 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_150 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_151 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_152 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_153 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_154 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_155 = execute_INSTRUCTION[13 : 12]; - assign _zz_156 = (iBus_cmd_valid || (_zz_125 != 3'b000)); - assign _zz_157 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_158 = ((_zz_110 && 1'b1) && (! 1'b0)); - assign _zz_159 = ((_zz_111 && 1'b1) && (! 1'b0)); - assign _zz_160 = ((_zz_112 && 1'b1) && (! 1'b0)); - assign _zz_161 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_162 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_163 = execute_INSTRUCTION[13]; - assign _zz_164 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_165 = ($signed(_zz_166) + $signed(_zz_171)); - assign _zz_166 = ($signed(_zz_167) + $signed(_zz_169)); - assign _zz_167 = 52'h0; - assign _zz_168 = {1'b0,memory_MUL_LL}; - assign _zz_169 = {{19{_zz_168[32]}}, _zz_168}; - assign _zz_170 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_171 = {{2{_zz_170[49]}}, _zz_170}; - assign _zz_172 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_173 = {{2{_zz_172[49]}}, _zz_172}; - assign _zz_174 = ($signed(_zz_176) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_175 = _zz_174[31 : 0]; - assign _zz_176 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_177 = _zz_74[27 : 27]; - assign _zz_178 = _zz_74[24 : 24]; - assign _zz_179 = _zz_74[15 : 15]; - assign _zz_180 = _zz_74[11 : 11]; - assign _zz_181 = _zz_74[10 : 10]; - assign _zz_182 = _zz_74[9 : 9]; - assign _zz_183 = _zz_74[12 : 12]; - assign _zz_184 = _zz_74[5 : 5]; - assign _zz_185 = _zz_74[3 : 3]; - assign _zz_186 = _zz_74[18 : 18]; - assign _zz_187 = _zz_74[8 : 8]; - assign _zz_188 = _zz_74[4 : 4]; - assign _zz_189 = _zz_74[0 : 0]; - assign _zz_190 = (_zz_53 - 3'b001); - assign _zz_191 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_192 = {29'd0, _zz_191}; - assign _zz_193 = execute_SRC_LESS; - assign _zz_194 = 3'b100; - assign _zz_195 = execute_INSTRUCTION[19 : 15]; - assign _zz_196 = execute_INSTRUCTION[31 : 20]; - assign _zz_197 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_198 = ($signed(_zz_199) + $signed(_zz_202)); - assign _zz_199 = ($signed(_zz_200) + $signed(_zz_201)); - assign _zz_200 = execute_SRC1; - assign _zz_201 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_202 = (execute_SRC_USE_SUB_LESS ? _zz_203 : _zz_204); - assign _zz_203 = 32'h00000001; - assign _zz_204 = 32'h0; - assign _zz_205 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_206 = execute_INSTRUCTION[31 : 20]; - assign _zz_207 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_208 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_209 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_210 = writeBack_MUL_LOW[31 : 0]; - assign _zz_211 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_212 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_213 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_214 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_215 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_216 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_217 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_218 = (iBus_cmd_payload_address >>> 5); - assign _zz_219 = 1'b1; - assign _zz_220 = 1'b1; - assign _zz_221 = {_zz_56,_zz_55}; - assign _zz_222 = 32'h0000107f; - assign _zz_223 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_224 = 32'h00002073; - assign _zz_225 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_226 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_227 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_228) == 32'h00000003),{(_zz_229 == _zz_230),{_zz_231,{_zz_232,_zz_233}}}}}}; - assign _zz_228 = 32'h0000505f; - assign _zz_229 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_230 = 32'h00000063; - assign _zz_231 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_232 = ((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033); - assign _zz_233 = {((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_234) == 32'h00001013),{(_zz_235 == _zz_236),{_zz_237,{_zz_238,_zz_239}}}}}}; - assign _zz_234 = 32'hfc00307f; - assign _zz_235 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_236 = 32'h00005033; - assign _zz_237 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_238 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_239 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; - assign _zz_240 = 32'h02000074; - assign _zz_241 = (decode_INSTRUCTION & 32'h10003050); - assign _zz_242 = 32'h00000050; - assign _zz_243 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); - assign _zz_244 = {(_zz_249 == _zz_250),(_zz_251 == _zz_252)}; - assign _zz_245 = 2'b00; - assign _zz_246 = ({_zz_78,_zz_253} != 2'b00); - assign _zz_247 = (_zz_254 != 1'b0); - assign _zz_248 = {(_zz_255 != _zz_256),{_zz_257,{_zz_258,_zz_259}}}; - assign _zz_249 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_250 = 32'h00001050; - assign _zz_251 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_252 = 32'h00002050; - assign _zz_253 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_254 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_255 = {(_zz_260 == _zz_261),(_zz_262 == _zz_263)}; - assign _zz_256 = 2'b00; - assign _zz_257 = ((_zz_264 == _zz_265) != 1'b0); - assign _zz_258 = ({_zz_266,_zz_267} != 3'b000); - assign _zz_259 = {(_zz_268 != _zz_269),{_zz_270,{_zz_271,_zz_272}}}; - assign _zz_260 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_261 = 32'h00000040; - assign _zz_262 = (decode_INSTRUCTION & 32'h00403040); - assign _zz_263 = 32'h00000040; - assign _zz_264 = (decode_INSTRUCTION & 32'h00007054); - assign _zz_265 = 32'h00005010; - assign _zz_266 = ((decode_INSTRUCTION & _zz_273) == 32'h40001010); - assign _zz_267 = {(_zz_274 == _zz_275),(_zz_276 == _zz_277)}; - assign _zz_268 = ((decode_INSTRUCTION & _zz_278) == 32'h00000024); - assign _zz_269 = 1'b0; - assign _zz_270 = ((_zz_279 == _zz_280) != 1'b0); - assign _zz_271 = (_zz_281 != 1'b0); - assign _zz_272 = {(_zz_282 != _zz_283),{_zz_284,{_zz_285,_zz_286}}}; - assign _zz_273 = 32'h40003054; - assign _zz_274 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_275 = 32'h00001010; - assign _zz_276 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_277 = 32'h00001010; - assign _zz_278 = 32'h00000064; - assign _zz_279 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_280 = 32'h00001000; - assign _zz_281 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_282 = {(_zz_287 == _zz_288),(_zz_289 == _zz_290)}; - assign _zz_283 = 2'b00; - assign _zz_284 = ((_zz_291 == _zz_292) != 1'b0); - assign _zz_285 = (_zz_76 != 1'b0); - assign _zz_286 = {(_zz_293 != _zz_294),{_zz_295,{_zz_296,_zz_297}}}; - assign _zz_287 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_288 = 32'h00002000; - assign _zz_289 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_290 = 32'h00001000; - assign _zz_291 = (decode_INSTRUCTION & 32'h00004004); - assign _zz_292 = 32'h00004000; - assign _zz_293 = {((decode_INSTRUCTION & _zz_298) == 32'h00000020),((decode_INSTRUCTION & _zz_299) == 32'h00000020)}; - assign _zz_294 = 2'b00; - assign _zz_295 = (((decode_INSTRUCTION & _zz_300) == 32'h00000020) != 1'b0); - assign _zz_296 = ({_zz_301,{_zz_302,_zz_303}} != 4'b0000); - assign _zz_297 = {({_zz_304,_zz_305} != 5'h0),{(_zz_306 != _zz_307),{_zz_308,{_zz_309,_zz_310}}}}; - assign _zz_298 = 32'h00000034; - assign _zz_299 = 32'h00000064; - assign _zz_300 = 32'h00000020; - assign _zz_301 = ((decode_INSTRUCTION & 32'h00000040) == 32'h00000040); - assign _zz_302 = _zz_77; - assign _zz_303 = {(_zz_311 == _zz_312),(_zz_313 == _zz_314)}; - assign _zz_304 = _zz_77; - assign _zz_305 = {(_zz_315 == _zz_316),{_zz_317,{_zz_318,_zz_319}}}; - assign _zz_306 = {_zz_78,{_zz_320,{_zz_321,_zz_322}}}; - assign _zz_307 = 6'h0; - assign _zz_308 = ({_zz_77,_zz_323} != 2'b00); - assign _zz_309 = ({_zz_324,_zz_325} != 2'b00); - assign _zz_310 = {(_zz_326 != _zz_327),{_zz_328,{_zz_329,_zz_330}}}; - assign _zz_311 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_312 = 32'h00000010; - assign _zz_313 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_314 = 32'h00000020; - assign _zz_315 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_316 = 32'h00002010; - assign _zz_317 = ((decode_INSTRUCTION & _zz_331) == 32'h00000010); - assign _zz_318 = (_zz_332 == _zz_333); - assign _zz_319 = (_zz_334 == _zz_335); - assign _zz_320 = ((decode_INSTRUCTION & _zz_336) == 32'h00001010); - assign _zz_321 = (_zz_337 == _zz_338); - assign _zz_322 = {_zz_339,{_zz_340,_zz_341}}; - assign _zz_323 = ((decode_INSTRUCTION & _zz_342) == 32'h00000020); - assign _zz_324 = _zz_77; - assign _zz_325 = (_zz_343 == _zz_344); - assign _zz_326 = {_zz_345,{_zz_346,_zz_347}}; - assign _zz_327 = 4'b0000; - assign _zz_328 = (_zz_348 != 1'b0); - assign _zz_329 = (_zz_349 != _zz_350); - assign _zz_330 = {_zz_351,{_zz_352,_zz_353}}; - assign _zz_331 = 32'h00001030; - assign _zz_332 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_333 = 32'h00002020; - assign _zz_334 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_335 = 32'h00000020; - assign _zz_336 = 32'h00001010; - assign _zz_337 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_338 = 32'h00002010; - assign _zz_339 = ((decode_INSTRUCTION & _zz_354) == 32'h00000010); - assign _zz_340 = (_zz_355 == _zz_356); - assign _zz_341 = (_zz_357 == _zz_358); - assign _zz_342 = 32'h00000070; - assign _zz_343 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_344 = 32'h0; - assign _zz_345 = ((decode_INSTRUCTION & _zz_359) == 32'h0); - assign _zz_346 = (_zz_360 == _zz_361); - assign _zz_347 = {_zz_76,_zz_362}; - assign _zz_348 = ((decode_INSTRUCTION & _zz_363) == 32'h0); - assign _zz_349 = {_zz_364,{_zz_365,_zz_366}}; - assign _zz_350 = 3'b000; - assign _zz_351 = ({_zz_367,_zz_368} != 2'b00); - assign _zz_352 = (_zz_369 != _zz_370); - assign _zz_353 = (_zz_371 != _zz_372); - assign _zz_354 = 32'h00000050; - assign _zz_355 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_356 = 32'h00000004; - assign _zz_357 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_358 = 32'h0; - assign _zz_359 = 32'h00000044; - assign _zz_360 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_361 = 32'h0; - assign _zz_362 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_363 = 32'h00000058; - assign _zz_364 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_365 = ((decode_INSTRUCTION & _zz_373) == 32'h00002010); - assign _zz_366 = ((decode_INSTRUCTION & _zz_374) == 32'h40000030); - assign _zz_367 = ((decode_INSTRUCTION & _zz_375) == 32'h00000004); - assign _zz_368 = _zz_75; - assign _zz_369 = {(_zz_376 == _zz_377),_zz_75}; - assign _zz_370 = 2'b00; - assign _zz_371 = ((decode_INSTRUCTION & _zz_378) == 32'h00001008); - assign _zz_372 = 1'b0; - assign _zz_373 = 32'h00002014; - assign _zz_374 = 32'h40000034; - assign _zz_375 = 32'h00000014; - assign _zz_376 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_377 = 32'h00000004; - assign _zz_378 = 32'h00001048; - always @ (posedge clk) begin - if(_zz_219) begin - _zz_137 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_220) begin - _zz_138 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_43) begin + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz_IBusCachedPlugin_jump_pcLoad_payload_2)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 2'b01); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_lastStageRegFileWrite_payload_data = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_lastStageRegFileWrite_payload_data_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz__zz_decode_IS_MUL = 32'h02000074; + assign _zz__zz_decode_IS_MUL_1 = (decode_INSTRUCTION & 32'h10003050); + assign _zz__zz_decode_IS_MUL_2 = 32'h00000050; + assign _zz__zz_decode_IS_MUL_3 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz__zz_decode_IS_MUL_4 = {(_zz__zz_decode_IS_MUL_5 == _zz__zz_decode_IS_MUL_6),(_zz__zz_decode_IS_MUL_7 == _zz__zz_decode_IS_MUL_8)}; + assign _zz__zz_decode_IS_MUL_9 = 2'b00; + assign _zz__zz_decode_IS_MUL_10 = ({_zz_decode_IS_MUL_4,_zz__zz_decode_IS_MUL_11} != 2'b00); + assign _zz__zz_decode_IS_MUL_12 = (_zz__zz_decode_IS_MUL_13 != 1'b0); + assign _zz__zz_decode_IS_MUL_14 = {(_zz__zz_decode_IS_MUL_15 != _zz__zz_decode_IS_MUL_20),{_zz__zz_decode_IS_MUL_21,{_zz__zz_decode_IS_MUL_24,_zz__zz_decode_IS_MUL_32}}}; + assign _zz__zz_decode_IS_MUL_5 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_IS_MUL_6 = 32'h00001050; + assign _zz__zz_decode_IS_MUL_7 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_IS_MUL_8 = 32'h00002050; + assign _zz__zz_decode_IS_MUL_11 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_IS_MUL_13 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_IS_MUL_15 = {(_zz__zz_decode_IS_MUL_16 == _zz__zz_decode_IS_MUL_17),(_zz__zz_decode_IS_MUL_18 == _zz__zz_decode_IS_MUL_19)}; + assign _zz__zz_decode_IS_MUL_20 = 2'b00; + assign _zz__zz_decode_IS_MUL_21 = ((_zz__zz_decode_IS_MUL_22 == _zz__zz_decode_IS_MUL_23) != 1'b0); + assign _zz__zz_decode_IS_MUL_24 = ({_zz__zz_decode_IS_MUL_25,_zz__zz_decode_IS_MUL_27} != 3'b000); + assign _zz__zz_decode_IS_MUL_32 = {(_zz__zz_decode_IS_MUL_33 != _zz__zz_decode_IS_MUL_35),{_zz__zz_decode_IS_MUL_36,{_zz__zz_decode_IS_MUL_39,_zz__zz_decode_IS_MUL_41}}}; + assign _zz__zz_decode_IS_MUL_16 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_MUL_17 = 32'h00000040; + assign _zz__zz_decode_IS_MUL_18 = (decode_INSTRUCTION & 32'h00403040); + assign _zz__zz_decode_IS_MUL_19 = 32'h00000040; + assign _zz__zz_decode_IS_MUL_22 = (decode_INSTRUCTION & 32'h00007054); + assign _zz__zz_decode_IS_MUL_23 = 32'h00005010; + assign _zz__zz_decode_IS_MUL_25 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_26) == 32'h40001010); + assign _zz__zz_decode_IS_MUL_27 = {(_zz__zz_decode_IS_MUL_28 == _zz__zz_decode_IS_MUL_29),(_zz__zz_decode_IS_MUL_30 == _zz__zz_decode_IS_MUL_31)}; + assign _zz__zz_decode_IS_MUL_33 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_34) == 32'h00000024); + assign _zz__zz_decode_IS_MUL_35 = 1'b0; + assign _zz__zz_decode_IS_MUL_36 = ((_zz__zz_decode_IS_MUL_37 == _zz__zz_decode_IS_MUL_38) != 1'b0); + assign _zz__zz_decode_IS_MUL_39 = (_zz__zz_decode_IS_MUL_40 != 1'b0); + assign _zz__zz_decode_IS_MUL_41 = {(_zz__zz_decode_IS_MUL_42 != _zz__zz_decode_IS_MUL_47),{_zz__zz_decode_IS_MUL_48,{_zz__zz_decode_IS_MUL_51,_zz__zz_decode_IS_MUL_52}}}; + assign _zz__zz_decode_IS_MUL_26 = 32'h40003054; + assign _zz__zz_decode_IS_MUL_28 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_MUL_29 = 32'h00001010; + assign _zz__zz_decode_IS_MUL_30 = (decode_INSTRUCTION & 32'h02007054); + assign _zz__zz_decode_IS_MUL_31 = 32'h00001010; + assign _zz__zz_decode_IS_MUL_34 = 32'h00000064; + assign _zz__zz_decode_IS_MUL_37 = (decode_INSTRUCTION & 32'h00001000); + assign _zz__zz_decode_IS_MUL_38 = 32'h00001000; + assign _zz__zz_decode_IS_MUL_40 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz__zz_decode_IS_MUL_42 = {(_zz__zz_decode_IS_MUL_43 == _zz__zz_decode_IS_MUL_44),(_zz__zz_decode_IS_MUL_45 == _zz__zz_decode_IS_MUL_46)}; + assign _zz__zz_decode_IS_MUL_47 = 2'b00; + assign _zz__zz_decode_IS_MUL_48 = ((_zz__zz_decode_IS_MUL_49 == _zz__zz_decode_IS_MUL_50) != 1'b0); + assign _zz__zz_decode_IS_MUL_51 = (_zz_decode_IS_MUL_2 != 1'b0); + assign _zz__zz_decode_IS_MUL_52 = {(_zz__zz_decode_IS_MUL_53 != _zz__zz_decode_IS_MUL_56),{_zz__zz_decode_IS_MUL_57,{_zz__zz_decode_IS_MUL_59,_zz__zz_decode_IS_MUL_67}}}; + assign _zz__zz_decode_IS_MUL_43 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_MUL_44 = 32'h00002000; + assign _zz__zz_decode_IS_MUL_45 = (decode_INSTRUCTION & 32'h00005000); + assign _zz__zz_decode_IS_MUL_46 = 32'h00001000; + assign _zz__zz_decode_IS_MUL_49 = (decode_INSTRUCTION & 32'h00004004); + assign _zz__zz_decode_IS_MUL_50 = 32'h00004000; + assign _zz__zz_decode_IS_MUL_53 = {((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_54) == 32'h00000020),((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_55) == 32'h00000020)}; + assign _zz__zz_decode_IS_MUL_56 = 2'b00; + assign _zz__zz_decode_IS_MUL_57 = (((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_58) == 32'h00000020) != 1'b0); + assign _zz__zz_decode_IS_MUL_59 = ({_zz__zz_decode_IS_MUL_60,{_zz__zz_decode_IS_MUL_61,_zz__zz_decode_IS_MUL_62}} != 4'b0000); + assign _zz__zz_decode_IS_MUL_67 = {({_zz__zz_decode_IS_MUL_68,_zz__zz_decode_IS_MUL_69} != 5'h0),{(_zz__zz_decode_IS_MUL_80 != _zz__zz_decode_IS_MUL_95),{_zz__zz_decode_IS_MUL_96,{_zz__zz_decode_IS_MUL_99,_zz__zz_decode_IS_MUL_104}}}}; + assign _zz__zz_decode_IS_MUL_54 = 32'h00000034; + assign _zz__zz_decode_IS_MUL_55 = 32'h00000064; + assign _zz__zz_decode_IS_MUL_58 = 32'h00000020; + assign _zz__zz_decode_IS_MUL_60 = ((decode_INSTRUCTION & 32'h00000040) == 32'h00000040); + assign _zz__zz_decode_IS_MUL_61 = _zz_decode_IS_MUL_3; + assign _zz__zz_decode_IS_MUL_62 = {(_zz__zz_decode_IS_MUL_63 == _zz__zz_decode_IS_MUL_64),(_zz__zz_decode_IS_MUL_65 == _zz__zz_decode_IS_MUL_66)}; + assign _zz__zz_decode_IS_MUL_68 = _zz_decode_IS_MUL_3; + assign _zz__zz_decode_IS_MUL_69 = {(_zz__zz_decode_IS_MUL_70 == _zz__zz_decode_IS_MUL_71),{_zz__zz_decode_IS_MUL_72,{_zz__zz_decode_IS_MUL_74,_zz__zz_decode_IS_MUL_77}}}; + assign _zz__zz_decode_IS_MUL_80 = {_zz_decode_IS_MUL_4,{_zz__zz_decode_IS_MUL_81,{_zz__zz_decode_IS_MUL_83,_zz__zz_decode_IS_MUL_86}}}; + assign _zz__zz_decode_IS_MUL_95 = 6'h0; + assign _zz__zz_decode_IS_MUL_96 = ({_zz_decode_IS_MUL_3,_zz__zz_decode_IS_MUL_97} != 2'b00); + assign _zz__zz_decode_IS_MUL_99 = ({_zz__zz_decode_IS_MUL_100,_zz__zz_decode_IS_MUL_101} != 2'b00); + assign _zz__zz_decode_IS_MUL_104 = {(_zz__zz_decode_IS_MUL_105 != _zz__zz_decode_IS_MUL_113),{_zz__zz_decode_IS_MUL_114,{_zz__zz_decode_IS_MUL_117,_zz__zz_decode_IS_MUL_125}}}; + assign _zz__zz_decode_IS_MUL_63 = (decode_INSTRUCTION & 32'h00000030); + assign _zz__zz_decode_IS_MUL_64 = 32'h00000010; + assign _zz__zz_decode_IS_MUL_65 = (decode_INSTRUCTION & 32'h02000020); + assign _zz__zz_decode_IS_MUL_66 = 32'h00000020; + assign _zz__zz_decode_IS_MUL_70 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_IS_MUL_71 = 32'h00002010; + assign _zz__zz_decode_IS_MUL_72 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_73) == 32'h00000010); + assign _zz__zz_decode_IS_MUL_74 = (_zz__zz_decode_IS_MUL_75 == _zz__zz_decode_IS_MUL_76); + assign _zz__zz_decode_IS_MUL_77 = (_zz__zz_decode_IS_MUL_78 == _zz__zz_decode_IS_MUL_79); + assign _zz__zz_decode_IS_MUL_81 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_82) == 32'h00001010); + assign _zz__zz_decode_IS_MUL_83 = (_zz__zz_decode_IS_MUL_84 == _zz__zz_decode_IS_MUL_85); + assign _zz__zz_decode_IS_MUL_86 = {_zz__zz_decode_IS_MUL_87,{_zz__zz_decode_IS_MUL_89,_zz__zz_decode_IS_MUL_92}}; + assign _zz__zz_decode_IS_MUL_97 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_98) == 32'h00000020); + assign _zz__zz_decode_IS_MUL_100 = _zz_decode_IS_MUL_3; + assign _zz__zz_decode_IS_MUL_101 = (_zz__zz_decode_IS_MUL_102 == _zz__zz_decode_IS_MUL_103); + assign _zz__zz_decode_IS_MUL_105 = {_zz__zz_decode_IS_MUL_106,{_zz__zz_decode_IS_MUL_108,_zz__zz_decode_IS_MUL_111}}; + assign _zz__zz_decode_IS_MUL_113 = 4'b0000; + assign _zz__zz_decode_IS_MUL_114 = (_zz__zz_decode_IS_MUL_115 != 1'b0); + assign _zz__zz_decode_IS_MUL_117 = (_zz__zz_decode_IS_MUL_118 != _zz__zz_decode_IS_MUL_124); + assign _zz__zz_decode_IS_MUL_125 = {_zz__zz_decode_IS_MUL_126,{_zz__zz_decode_IS_MUL_130,_zz__zz_decode_IS_MUL_135}}; + assign _zz__zz_decode_IS_MUL_73 = 32'h00001030; + assign _zz__zz_decode_IS_MUL_75 = (decode_INSTRUCTION & 32'h02002060); + assign _zz__zz_decode_IS_MUL_76 = 32'h00002020; + assign _zz__zz_decode_IS_MUL_78 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_IS_MUL_79 = 32'h00000020; + assign _zz__zz_decode_IS_MUL_82 = 32'h00001010; + assign _zz__zz_decode_IS_MUL_84 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_MUL_85 = 32'h00002010; + assign _zz__zz_decode_IS_MUL_87 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_88) == 32'h00000010); + assign _zz__zz_decode_IS_MUL_89 = (_zz__zz_decode_IS_MUL_90 == _zz__zz_decode_IS_MUL_91); + assign _zz__zz_decode_IS_MUL_92 = (_zz__zz_decode_IS_MUL_93 == _zz__zz_decode_IS_MUL_94); + assign _zz__zz_decode_IS_MUL_98 = 32'h00000070; + assign _zz__zz_decode_IS_MUL_102 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_MUL_103 = 32'h0; + assign _zz__zz_decode_IS_MUL_106 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_107) == 32'h0); + assign _zz__zz_decode_IS_MUL_108 = (_zz__zz_decode_IS_MUL_109 == _zz__zz_decode_IS_MUL_110); + assign _zz__zz_decode_IS_MUL_111 = {_zz_decode_IS_MUL_2,_zz__zz_decode_IS_MUL_112}; + assign _zz__zz_decode_IS_MUL_115 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_116) == 32'h0); + assign _zz__zz_decode_IS_MUL_118 = {_zz__zz_decode_IS_MUL_119,{_zz__zz_decode_IS_MUL_120,_zz__zz_decode_IS_MUL_122}}; + assign _zz__zz_decode_IS_MUL_124 = 3'b000; + assign _zz__zz_decode_IS_MUL_126 = ({_zz__zz_decode_IS_MUL_127,_zz__zz_decode_IS_MUL_129} != 2'b00); + assign _zz__zz_decode_IS_MUL_130 = (_zz__zz_decode_IS_MUL_131 != _zz__zz_decode_IS_MUL_134); + assign _zz__zz_decode_IS_MUL_135 = (_zz__zz_decode_IS_MUL_136 != _zz__zz_decode_IS_MUL_138); + assign _zz__zz_decode_IS_MUL_88 = 32'h00000050; + assign _zz__zz_decode_IS_MUL_90 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz__zz_decode_IS_MUL_91 = 32'h00000004; + assign _zz__zz_decode_IS_MUL_93 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_MUL_94 = 32'h0; + assign _zz__zz_decode_IS_MUL_107 = 32'h00000044; + assign _zz__zz_decode_IS_MUL_109 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_IS_MUL_110 = 32'h0; + assign _zz__zz_decode_IS_MUL_112 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_IS_MUL_116 = 32'h00000058; + assign _zz__zz_decode_IS_MUL_119 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_IS_MUL_120 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_121) == 32'h00002010); + assign _zz__zz_decode_IS_MUL_122 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_123) == 32'h40000030); + assign _zz__zz_decode_IS_MUL_127 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_128) == 32'h00000004); + assign _zz__zz_decode_IS_MUL_129 = _zz_decode_IS_MUL_1; + assign _zz__zz_decode_IS_MUL_131 = {(_zz__zz_decode_IS_MUL_132 == _zz__zz_decode_IS_MUL_133),_zz_decode_IS_MUL_1}; + assign _zz__zz_decode_IS_MUL_134 = 2'b00; + assign _zz__zz_decode_IS_MUL_136 = ((decode_INSTRUCTION & _zz__zz_decode_IS_MUL_137) == 32'h00001008); + assign _zz__zz_decode_IS_MUL_138 = 1'b0; + assign _zz__zz_decode_IS_MUL_121 = 32'h00002014; + assign _zz__zz_decode_IS_MUL_123 = 32'h40000034; + assign _zz__zz_decode_IS_MUL_128 = 32'h00000014; + assign _zz__zz_decode_IS_MUL_132 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_MUL_133 = 32'h00000004; + assign _zz__zz_decode_IS_MUL_137 = 32'h00001048; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_128 ), //i - .io_cpu_prefetch_isValid (_zz_129 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_130 ), //i - .io_cpu_fetch_isStuck (_zz_131 ), //i - .io_cpu_fetch_isRemoved (_zz_132 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_133 ), //i - .io_cpu_decode_isStuck (_zz_134 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_135 ), //i - .io_cpu_fill_valid (_zz_136 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); - always @(*) begin - case(_zz_221) - 2'b00 : begin - _zz_139 = CsrPlugin_jumpInterface_payload; - end - 2'b01 : begin - _zz_139 = DBusSimplePlugin_redoBranch_payload; - end - default : begin - _zz_139 = BranchPlugin_jumpInterface_payload; - end - endcase - end - `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_10) - `BranchCtrlEnum_defaultEncoding_INC : _zz_10_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_10_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_10_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_10_string = "JALR"; - default : _zz_10_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_19) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19_string = "BITWISE "; - default : _zz_19_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_20) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; - default : _zz_20_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_24) - `Src2CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_24_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_24_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_24_string = "PC "; - default : _zz_24_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_30) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_30_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_30_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30_string = "ECALL"; - default : _zz_30_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_31) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_31_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_31_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_31_string = "ECALL"; - default : _zz_31_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_32) - `BranchCtrlEnum_defaultEncoding_INC : _zz_32_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_32_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_32_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_32_string = "JALR"; - default : _zz_32_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_34) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; - default : _zz_34_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_35) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35_string = "SRA_1 "; - default : _zz_35_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_37) - `Src2CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_37_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_37_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_37_string = "PC "; - default : _zz_37_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_38) - `Src1CtrlEnum_defaultEncoding_RS : _zz_38_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_38_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_38_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_38_string = "URS1 "; - default : _zz_38_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_39) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_39_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_39_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_39_string = "BITWISE "; - default : _zz_39_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_40) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_40_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_40_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_40_string = "AND_1"; - default : _zz_40_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_44_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_44_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_44_string = "ECALL"; - default : _zz_44_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_45) - `BranchCtrlEnum_defaultEncoding_INC : _zz_45_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_45_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_45_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_45_string = "JALR"; - default : _zz_45_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_46) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46_string = "SRA_1 "; - default : _zz_46_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_47) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47_string = "AND_1"; - default : _zz_47_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_48) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; - default : _zz_48_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_49) - `Src2CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_49_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_49_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_49_string = "PC "; - default : _zz_49_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_50) - `Src1CtrlEnum_defaultEncoding_RS : _zz_50_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_50_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_50_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_50_string = "URS1 "; - default : _zz_50_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin - case(_zz_79) - `Src1CtrlEnum_defaultEncoding_RS : _zz_79_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_79_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_79_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_79_string = "URS1 "; - default : _zz_79_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_80) - `Src2CtrlEnum_defaultEncoding_RS : _zz_80_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_80_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_80_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_80_string = "PC "; - default : _zz_80_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_81) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_81_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_81_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_81_string = "BITWISE "; - default : _zz_81_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_82) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_82_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_82_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_82_string = "AND_1"; - default : _zz_82_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_83) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_83_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_83_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_83_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_83_string = "SRA_1 "; - default : _zz_83_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_84) - `BranchCtrlEnum_defaultEncoding_INC : _zz_84_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_84_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_84_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_84_string = "JALR"; - default : _zz_84_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_85) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_85_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_85_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_85_string = "ECALL"; - default : _zz_85_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_165) + $signed(_zz_173)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); assign memory_MEMORY_READ_DATA = dBus_rsp_data; assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); @@ -2027,10 +2021,11 @@ module VexRiscv ( assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_102; - assign execute_SHIFT_RIGHT = _zz_175; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_87; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); @@ -2040,60 +2035,62 @@ module VexRiscv ( assign decode_RS1 = decode_RegFilePlugin_rs1Data; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_177[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_178[0]; - assign decode_BRANCH_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign _zz_11 = _zz_12; - assign decode_SHIFT_CTRL = _zz_13; - assign _zz_14 = _zz_15; - assign decode_ALU_BITWISE_CTRL = _zz_16; - assign _zz_17 = _zz_18; - assign decode_SRC_LESS_UNSIGNED = _zz_179[0]; - assign decode_ALU_CTRL = _zz_19; - assign _zz_20 = _zz_21; - assign decode_MEMORY_STORE = _zz_180[0]; + assign decode_IS_MUL = _zz_decode_IS_MUL[27]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_MUL[24]; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_MUL[15]; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_STORE = _zz_decode_IS_MUL[11]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_181[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_182[0]; - assign decode_SRC2_CTRL = _zz_22; - assign _zz_23 = _zz_24; - assign decode_SRC1_CTRL = _zz_25; - assign _zz_26 = _zz_27; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_MUL[10]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_MUL[9]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_MEMORY_ENABLE = _zz_decode_IS_MUL[4]; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; - always @ (*) begin - _zz_28 = execute_REGFILE_WRITE_DATA; - if(_zz_140)begin - _zz_28 = execute_CsrPlugin_readData; + always @(*) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = CsrPlugin_csrMapping_readDataSignal; end end assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_29; - assign execute_ENV_CTRL = _zz_30; - assign writeBack_ENV_CTRL = _zz_31; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_32; - assign decode_RS2_USE = _zz_183[0]; - assign decode_RS1_USE = _zz_184[0]; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_MUL[12]; + assign decode_RS1_USE = _zz_decode_IS_MUL[5]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; @@ -2101,15 +2098,15 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_33 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_memory_to_writeBack_REGFILE_WRITE_DATA = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_33 = _zz_95; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_memory_to_writeBack_REGFILE_WRITE_DATA = _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_33 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_memory_to_writeBack_REGFILE_WRITE_DATA = memory_SHIFT_RIGHT; end default : begin end @@ -2117,53 +2114,53 @@ module VexRiscv ( end end - assign memory_SHIFT_CTRL = _zz_34; - assign execute_SHIFT_CTRL = _zz_35; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_36 = execute_PC; - assign execute_SRC2_CTRL = _zz_37; - assign execute_SRC1_CTRL = _zz_38; - assign decode_SRC_USE_SUB_LESS = _zz_185[0]; - assign decode_SRC_ADD_ZERO = _zz_186[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_MUL[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_MUL[18]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_39; - assign execute_SRC2 = _zz_93; - assign execute_SRC1 = _zz_88; - assign execute_ALU_BITWISE_CTRL = _zz_40; - assign _zz_41 = writeBack_INSTRUCTION; - assign _zz_42 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_43 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_43 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_187[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_MUL[8]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_222) == 32'h00001073),{(_zz_223 == _zz_224),{_zz_225,{_zz_226,_zz_227}}}}}}} != 21'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 21'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; - always @ (*) begin - _zz_51 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_51 = writeBack_DBusSimplePlugin_rspFormated; + always @(*) begin + _zz_lastStageRegFileWrite_payload_data = writeBack_REGFILE_WRITE_DATA; + if(when_DBusSimplePlugin_l558) begin + _zz_lastStageRegFileWrite_payload_data = writeBack_DBusSimplePlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_164) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_51 = _zz_210; + _zz_lastStageRegFileWrite_payload_data = _zz__zz_lastStageRegFileWrite_payload_data; end default : begin - _zz_51 = _zz_211; + _zz_lastStageRegFileWrite_payload_data = _zz__zz_lastStageRegFileWrite_payload_data_1; end endcase end @@ -2172,189 +2169,142 @@ module VexRiscv ( assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; - assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; - assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; - assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; - assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; - assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; - assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; - assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; - assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; - assign memory_PC = execute_to_memory_PC; - assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); - assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; - assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; - assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; - assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = 1'b0; - assign decode_MEMORY_ENABLE = _zz_188[0]; - assign decode_FLUSH_ALL = _zz_189[0]; - always @ (*) begin + assign decode_FLUSH_ALL = _zz_decode_IS_MUL[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_141)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_142)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_52 = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_52 = DBusSimplePlugin_redoBranch_payload; - end - if(BranchPlugin_jumpInterface_valid)begin - _zz_52 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin - decode_arbitration_haltItself = 1'b0; - if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin - decode_arbitration_haltItself = 1'b1; - end - end - - always @ (*) begin + assign decode_arbitration_haltItself = 1'b0; + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_96 || _zz_97)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_67)))begin + if(when_DBusSimplePlugin_l426) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_140)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end assign execute_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + if(when_DBusSimplePlugin_l479) begin memory_arbitration_haltItself = 1'b1; end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(DBusSimplePlugin_memoryExceptionPort_valid)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end - always @ (*) begin - memory_arbitration_flushIt = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_jumpInterface_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(DBusSimplePlugin_memoryExceptionPort_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end end assign writeBack_arbitration_haltItself = 1'b0; assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end assign writeBack_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_143)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_144)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2363,45 +2313,47 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_143)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_144)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; assign CsrPlugin_inWfi = 1'b0; assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_143)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_144)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_143)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_144)begin - case(_zz_145) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2414,58 +2366,61 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); - assign _zz_53 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_54 = (_zz_53 & (~ _zz_190)); - assign _zz_55 = _zz_54[1]; - assign _zz_56 = _zz_54[2]; - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_139; - always @ (*) begin + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid} != 2'b00); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}; + assign IBusCachedPlugin_jump_pcLoad_payload = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[0] ? CsrPlugin_jumpInterface_payload : BranchPlugin_jumpInterface_payload); + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_192); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -2473,58 +2428,67 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_57 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_57); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_57); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_58 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_58); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_58); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_2 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_59 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_59); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_59); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_60; - assign _zz_60 = ((1'b0 && (! _zz_61)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_61 = _zz_62; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_61; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_63)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_63 = _zz_64; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_63; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_65; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; @@ -2532,134 +2496,96 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_129 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_130 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_131 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_130; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_133 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_134 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_135 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_142)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_141)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_136 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_141)begin - _zz_136 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_2 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_128 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign _zz_67 = 1'b0; - always @ (*) begin + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_dBus_cmd_valid = 1'b0; + always @(*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; - if(execute_ALIGNEMENT_FAULT)begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin + if(execute_ALIGNEMENT_FAULT) begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_67)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_68 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_dBus_cmd_payload_data = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_68 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_dBus_cmd_payload_data = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_68 = execute_RS2[31 : 0]; + _zz_dBus_cmd_payload_data = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_68; - always @ (*) begin + assign dBus_cmd_payload_data = _zz_dBus_cmd_payload_data; + assign when_DBusSimplePlugin_l426 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_69 = 4'b0001; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0001; end 2'b01 : begin - _zz_69 = 4'b0011; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0011; end default : begin - _zz_69 = 4'b1111; + _zz_execute_DBusSimplePlugin_formalMask = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_69 <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; - assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end else begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - end - if(_zz_146)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end - end - - always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(! memory_MMU_RSP2_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); - end - end - end - - assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; - always @ (*) begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_redoBranch_valid = 1'b1; - end - if(_zz_146)begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - end - end - - assign DBusSimplePlugin_redoBranch_payload = memory_PC; - always @ (*) begin + assign execute_DBusSimplePlugin_formalMask = (_zz_execute_DBusSimplePlugin_formalMask <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign when_DBusSimplePlugin_l479 = (((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)); + always @(*) begin writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin @@ -2676,63 +2602,64 @@ module VexRiscv ( endcase end - assign _zz_70 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_71[31] = _zz_70; - _zz_71[30] = _zz_70; - _zz_71[29] = _zz_70; - _zz_71[28] = _zz_70; - _zz_71[27] = _zz_70; - _zz_71[26] = _zz_70; - _zz_71[25] = _zz_70; - _zz_71[24] = _zz_70; - _zz_71[23] = _zz_70; - _zz_71[22] = _zz_70; - _zz_71[21] = _zz_70; - _zz_71[20] = _zz_70; - _zz_71[19] = _zz_70; - _zz_71[18] = _zz_70; - _zz_71[17] = _zz_70; - _zz_71[16] = _zz_70; - _zz_71[15] = _zz_70; - _zz_71[14] = _zz_70; - _zz_71[13] = _zz_70; - _zz_71[12] = _zz_70; - _zz_71[11] = _zz_70; - _zz_71[10] = _zz_70; - _zz_71[9] = _zz_70; - _zz_71[8] = _zz_70; - _zz_71[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_72 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_73[31] = _zz_72; - _zz_73[30] = _zz_72; - _zz_73[29] = _zz_72; - _zz_73[28] = _zz_72; - _zz_73[27] = _zz_72; - _zz_73[26] = _zz_72; - _zz_73[25] = _zz_72; - _zz_73[24] = _zz_72; - _zz_73[23] = _zz_72; - _zz_73[22] = _zz_72; - _zz_73[21] = _zz_72; - _zz_73[20] = _zz_72; - _zz_73[19] = _zz_72; - _zz_73[18] = _zz_72; - _zz_73[17] = _zz_72; - _zz_73[16] = _zz_72; - _zz_73[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_162) + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusSimplePlugin_rspFormated = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_1[31] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[30] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[29] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[28] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[27] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[26] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[25] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[24] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[23] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[22] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[21] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[20] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[19] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[18] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[17] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[16] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[15] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[14] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[13] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[12] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[11] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[10] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[9] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[8] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_writeBack_DBusSimplePlugin_rspFormated_2 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_3[31] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[30] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[29] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[28] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[27] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[26] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[25] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[24] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[23] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[22] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[21] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[20] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[19] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[18] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[17] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[16] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_71; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_73; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_3; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -2740,6 +2667,7 @@ module VexRiscv ( endcase end + assign when_DBusSimplePlugin_l558 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -2749,68 +2677,60 @@ module VexRiscv ( assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_75 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_76 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_77 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_78 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_74 = {(((decode_INSTRUCTION & _zz_240) == 32'h02000030) != 1'b0),{((_zz_241 == _zz_242) != 1'b0),{(_zz_243 != 1'b0),{(_zz_244 != _zz_245),{_zz_246,{_zz_247,_zz_248}}}}}}; - assign _zz_79 = _zz_74[2 : 1]; - assign _zz_50 = _zz_79; - assign _zz_80 = _zz_74[7 : 6]; - assign _zz_49 = _zz_80; - assign _zz_81 = _zz_74[14 : 13]; - assign _zz_48 = _zz_81; - assign _zz_82 = _zz_74[17 : 16]; - assign _zz_47 = _zz_82; - assign _zz_83 = _zz_74[20 : 19]; - assign _zz_46 = _zz_83; - assign _zz_84 = _zz_74[23 : 22]; - assign _zz_45 = _zz_84; - assign _zz_85 = _zz_74[26 : 25]; - assign _zz_44 = _zz_85; + assign _zz_decode_IS_MUL_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_MUL_2 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_decode_IS_MUL_3 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_MUL_4 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_MUL = {(((decode_INSTRUCTION & _zz__zz_decode_IS_MUL) == 32'h02000030) != 1'b0),{((_zz__zz_decode_IS_MUL_1 == _zz__zz_decode_IS_MUL_2) != 1'b0),{(_zz__zz_decode_IS_MUL_3 != 1'b0),{(_zz__zz_decode_IS_MUL_4 != _zz__zz_decode_IS_MUL_9),{_zz__zz_decode_IS_MUL_10,{_zz__zz_decode_IS_MUL_12,_zz__zz_decode_IS_MUL_14}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_MUL[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_MUL[7 : 6]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_MUL[14 : 13]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_MUL[17 : 16]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_MUL[20 : 19]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_MUL[23 : 22]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_MUL[26 : 25]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_137; - assign decode_RegFilePlugin_rs2Data = _zz_138; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_42 && writeBack_arbitration_isFiring); - if(_zz_86)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_41[11 : 7]; - if(_zz_86)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_51; - if(_zz_86)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_lastStageRegFileWrite_payload_data; + if(_zz_2) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -2819,444 +2739,480 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_87 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_87 = {31'd0, _zz_193}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_87 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_88 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_88 = {29'd0, _zz_194}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_88 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_88 = {27'd0, _zz_195}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_89 = _zz_196[11]; - always @ (*) begin - _zz_90[19] = _zz_89; - _zz_90[18] = _zz_89; - _zz_90[17] = _zz_89; - _zz_90[16] = _zz_89; - _zz_90[15] = _zz_89; - _zz_90[14] = _zz_89; - _zz_90[13] = _zz_89; - _zz_90[12] = _zz_89; - _zz_90[11] = _zz_89; - _zz_90[10] = _zz_89; - _zz_90[9] = _zz_89; - _zz_90[8] = _zz_89; - _zz_90[7] = _zz_89; - _zz_90[6] = _zz_89; - _zz_90[5] = _zz_89; - _zz_90[4] = _zz_89; - _zz_90[3] = _zz_89; - _zz_90[2] = _zz_89; - _zz_90[1] = _zz_89; - _zz_90[0] = _zz_89; - end - - assign _zz_91 = _zz_197[11]; - always @ (*) begin - _zz_92[19] = _zz_91; - _zz_92[18] = _zz_91; - _zz_92[17] = _zz_91; - _zz_92[16] = _zz_91; - _zz_92[15] = _zz_91; - _zz_92[14] = _zz_91; - _zz_92[13] = _zz_91; - _zz_92[12] = _zz_91; - _zz_92[11] = _zz_91; - _zz_92[10] = _zz_91; - _zz_92[9] = _zz_91; - _zz_92[8] = _zz_91; - _zz_92[7] = _zz_91; - _zz_92[6] = _zz_91; - _zz_92[5] = _zz_91; - _zz_92[4] = _zz_91; - _zz_92[3] = _zz_91; - _zz_92[2] = _zz_91; - _zz_92[1] = _zz_91; - _zz_92[0] = _zz_91; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_93 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_93 = {_zz_90,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_93 = {_zz_92,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_93 = _zz_36; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_198; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_94[0] = execute_SRC1[31]; - _zz_94[1] = execute_SRC1[30]; - _zz_94[2] = execute_SRC1[29]; - _zz_94[3] = execute_SRC1[28]; - _zz_94[4] = execute_SRC1[27]; - _zz_94[5] = execute_SRC1[26]; - _zz_94[6] = execute_SRC1[25]; - _zz_94[7] = execute_SRC1[24]; - _zz_94[8] = execute_SRC1[23]; - _zz_94[9] = execute_SRC1[22]; - _zz_94[10] = execute_SRC1[21]; - _zz_94[11] = execute_SRC1[20]; - _zz_94[12] = execute_SRC1[19]; - _zz_94[13] = execute_SRC1[18]; - _zz_94[14] = execute_SRC1[17]; - _zz_94[15] = execute_SRC1[16]; - _zz_94[16] = execute_SRC1[15]; - _zz_94[17] = execute_SRC1[14]; - _zz_94[18] = execute_SRC1[13]; - _zz_94[19] = execute_SRC1[12]; - _zz_94[20] = execute_SRC1[11]; - _zz_94[21] = execute_SRC1[10]; - _zz_94[22] = execute_SRC1[9]; - _zz_94[23] = execute_SRC1[8]; - _zz_94[24] = execute_SRC1[7]; - _zz_94[25] = execute_SRC1[6]; - _zz_94[26] = execute_SRC1[5]; - _zz_94[27] = execute_SRC1[4]; - _zz_94[28] = execute_SRC1[3]; - _zz_94[29] = execute_SRC1[2]; - _zz_94[30] = execute_SRC1[1]; - _zz_94[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_94 : execute_SRC1); - always @ (*) begin - _zz_95[0] = memory_SHIFT_RIGHT[31]; - _zz_95[1] = memory_SHIFT_RIGHT[30]; - _zz_95[2] = memory_SHIFT_RIGHT[29]; - _zz_95[3] = memory_SHIFT_RIGHT[28]; - _zz_95[4] = memory_SHIFT_RIGHT[27]; - _zz_95[5] = memory_SHIFT_RIGHT[26]; - _zz_95[6] = memory_SHIFT_RIGHT[25]; - _zz_95[7] = memory_SHIFT_RIGHT[24]; - _zz_95[8] = memory_SHIFT_RIGHT[23]; - _zz_95[9] = memory_SHIFT_RIGHT[22]; - _zz_95[10] = memory_SHIFT_RIGHT[21]; - _zz_95[11] = memory_SHIFT_RIGHT[20]; - _zz_95[12] = memory_SHIFT_RIGHT[19]; - _zz_95[13] = memory_SHIFT_RIGHT[18]; - _zz_95[14] = memory_SHIFT_RIGHT[17]; - _zz_95[15] = memory_SHIFT_RIGHT[16]; - _zz_95[16] = memory_SHIFT_RIGHT[15]; - _zz_95[17] = memory_SHIFT_RIGHT[14]; - _zz_95[18] = memory_SHIFT_RIGHT[13]; - _zz_95[19] = memory_SHIFT_RIGHT[12]; - _zz_95[20] = memory_SHIFT_RIGHT[11]; - _zz_95[21] = memory_SHIFT_RIGHT[10]; - _zz_95[22] = memory_SHIFT_RIGHT[9]; - _zz_95[23] = memory_SHIFT_RIGHT[8]; - _zz_95[24] = memory_SHIFT_RIGHT[7]; - _zz_95[25] = memory_SHIFT_RIGHT[6]; - _zz_95[26] = memory_SHIFT_RIGHT[5]; - _zz_95[27] = memory_SHIFT_RIGHT[4]; - _zz_95[28] = memory_SHIFT_RIGHT[3]; - _zz_95[29] = memory_SHIFT_RIGHT[2]; - _zz_95[30] = memory_SHIFT_RIGHT[1]; - _zz_95[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_96 = 1'b0; - if(_zz_98)begin - if((_zz_99 == decode_INSTRUCTION[19 : 15]))begin - _zz_96 = 1'b1; - end - end - if(_zz_147)begin - if(_zz_148)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_96 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[0] = memory_SHIFT_RIGHT[31]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[1] = memory_SHIFT_RIGHT[30]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[2] = memory_SHIFT_RIGHT[29]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[3] = memory_SHIFT_RIGHT[28]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[4] = memory_SHIFT_RIGHT[27]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[5] = memory_SHIFT_RIGHT[26]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[6] = memory_SHIFT_RIGHT[25]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[7] = memory_SHIFT_RIGHT[24]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[8] = memory_SHIFT_RIGHT[23]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[9] = memory_SHIFT_RIGHT[22]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[10] = memory_SHIFT_RIGHT[21]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[11] = memory_SHIFT_RIGHT[20]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[12] = memory_SHIFT_RIGHT[19]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[13] = memory_SHIFT_RIGHT[18]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[14] = memory_SHIFT_RIGHT[17]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[15] = memory_SHIFT_RIGHT[16]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[16] = memory_SHIFT_RIGHT[15]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[17] = memory_SHIFT_RIGHT[14]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[18] = memory_SHIFT_RIGHT[13]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[19] = memory_SHIFT_RIGHT[12]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[20] = memory_SHIFT_RIGHT[11]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[21] = memory_SHIFT_RIGHT[10]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[22] = memory_SHIFT_RIGHT[9]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[23] = memory_SHIFT_RIGHT[8]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[24] = memory_SHIFT_RIGHT[7]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[25] = memory_SHIFT_RIGHT[6]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[26] = memory_SHIFT_RIGHT[5]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[27] = memory_SHIFT_RIGHT[4]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[28] = memory_SHIFT_RIGHT[3]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[29] = memory_SHIFT_RIGHT[2]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[30] = memory_SHIFT_RIGHT[1]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l59) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_149)begin - if(_zz_150)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_96 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l59_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_151)begin - if(_zz_152)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_96 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l59_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_96 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_97 = 1'b0; - if(_zz_98)begin - if((_zz_99 == decode_INSTRUCTION[24 : 20]))begin - _zz_97 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end - if(_zz_147)begin - if(_zz_148)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_97 = 1'b1; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l62) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_149)begin - if(_zz_150)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_97 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l62_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_151)begin - if(_zz_152)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_97 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l62_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_97 = 1'b0; - end - end - + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_lastStageRegFileWrite_payload_data; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l59 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b1 || (! 1'b1)); + assign when_HazardSimplePlugin_l59_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l59_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_100 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_100 == 3'b000)) begin - _zz_101 = execute_BranchPlugin_eq; - end else if((_zz_100 == 3'b001)) begin - _zz_101 = (! execute_BranchPlugin_eq); - end else if((((_zz_100 & 3'b101) == 3'b101))) begin - _zz_101 = (! execute_SRC_LESS); - end else begin - _zz_101 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_DO = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_102 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_DO_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_102 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_DO_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_102 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_DO_1 = 1'b1; end default : begin - _zz_102 = _zz_101; + _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; end endcase end - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_103 = _zz_205[19]; - always @ (*) begin - _zz_104[10] = _zz_103; - _zz_104[9] = _zz_103; - _zz_104[8] = _zz_103; - _zz_104[7] = _zz_103; - _zz_104[6] = _zz_103; - _zz_104[5] = _zz_103; - _zz_104[4] = _zz_103; - _zz_104[3] = _zz_103; - _zz_104[2] = _zz_103; - _zz_104[1] = _zz_103; - _zz_104[0] = _zz_103; - end - - assign _zz_105 = _zz_206[11]; - always @ (*) begin - _zz_106[19] = _zz_105; - _zz_106[18] = _zz_105; - _zz_106[17] = _zz_105; - _zz_106[16] = _zz_105; - _zz_106[15] = _zz_105; - _zz_106[14] = _zz_105; - _zz_106[13] = _zz_105; - _zz_106[12] = _zz_105; - _zz_106[11] = _zz_105; - _zz_106[10] = _zz_105; - _zz_106[9] = _zz_105; - _zz_106[8] = _zz_105; - _zz_106[7] = _zz_105; - _zz_106[6] = _zz_105; - _zz_106[5] = _zz_105; - _zz_106[4] = _zz_105; - _zz_106[3] = _zz_105; - _zz_106[2] = _zz_105; - _zz_106[1] = _zz_105; - _zz_106[0] = _zz_105; - end - - assign _zz_107 = _zz_207[11]; - always @ (*) begin - _zz_108[18] = _zz_107; - _zz_108[17] = _zz_107; - _zz_108[16] = _zz_107; - _zz_108[15] = _zz_107; - _zz_108[14] = _zz_107; - _zz_108[13] = _zz_107; - _zz_108[12] = _zz_107; - _zz_108[11] = _zz_107; - _zz_108[10] = _zz_107; - _zz_108[9] = _zz_107; - _zz_108[8] = _zz_107; - _zz_108[7] = _zz_107; - _zz_108[6] = _zz_107; - _zz_108[5] = _zz_107; - _zz_108[4] = _zz_107; - _zz_108[3] = _zz_107; - _zz_108[2] = _zz_107; - _zz_108[1] = _zz_107; - _zz_108[0] = _zz_107; - end - - always @ (*) begin + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JALR) ? execute_RS1 : execute_PC); + assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_109 = {{_zz_104,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_109 = {_zz_106,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_109 = {{_zz_108,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_109; + assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_110 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_111 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_112 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(DBusSimplePlugin_memoryExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -3267,8 +3223,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3278,82 +3234,89 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_2816) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_2944) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_153)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_154)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_154)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3366,39 +3329,48 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_153)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_153)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_163) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_155) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -3411,8 +3383,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_155) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -3431,36 +3403,94 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_208) + $signed(_zz_209)); - assign _zz_114 = (_zz_113 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_114 != 32'h0); - assign _zz_27 = decode_SRC1_CTRL; - assign _zz_25 = _zz_50; - assign _zz_38 = decode_to_execute_SRC1_CTRL; - assign _zz_24 = decode_SRC2_CTRL; - assign _zz_22 = _zz_49; - assign _zz_37 = decode_to_execute_SRC2_CTRL; - assign _zz_21 = decode_ALU_CTRL; - assign _zz_19 = _zz_48; - assign _zz_39 = decode_to_execute_ALU_CTRL; - assign _zz_18 = decode_ALU_BITWISE_CTRL; - assign _zz_16 = _zz_47; - assign _zz_40 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_15 = decode_SHIFT_CTRL; - assign _zz_12 = execute_SHIFT_CTRL; - assign _zz_13 = _zz_46; - assign _zz_35 = decode_to_execute_SHIFT_CTRL; - assign _zz_34 = execute_to_memory_SHIFT_CTRL; - assign _zz_10 = decode_BRANCH_CTRL; - assign _zz_8 = _zz_45; - assign _zz_32 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_44; - assign _zz_30 = decode_to_execute_ENV_CTRL; - assign _zz_29 = execute_to_memory_ENV_CTRL; - assign _zz_31 = memory_to_writeBack_ENV_CTRL; + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_32 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_33 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -3481,138 +3511,160 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_115 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_115[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_115[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_115[3 : 3] = CsrPlugin_mstatus_MIE; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_116 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_116[11 : 11] = CsrPlugin_mip_MEIP; - _zz_116[7 : 7] = CsrPlugin_mip_MTIP; - _zz_116[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_117 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_117[11 : 11] = CsrPlugin_mie_MEIE; - _zz_117[7 : 7] = CsrPlugin_mie_MTIE; - _zz_117[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_118 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_118[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_119 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_119[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_119[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_120 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_120[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_121 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_121[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_122 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_122[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_123 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_123[31 : 0] = _zz_113; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_124 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_124[31 : 0] = _zz_114; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = ((((_zz_115 | _zz_116) | (_zz_117 | _zz_118)) | ((_zz_119 | _zz_120) | (_zz_121 | _zz_122))) | (_zz_123 | _zz_124)); - assign iBusWishbone_ADR = {_zz_218,_zz_125}; - assign iBusWishbone_CTI = ((_zz_125 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = ((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))) | (_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11)); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_156)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_156)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_126; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; - assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; - assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; - assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; - assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; - assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBus_cmd_halfPipe_fire = (dBus_cmd_halfPipe_valid && dBus_cmd_halfPipe_ready); + assign dBus_cmd_ready = (! dBus_cmd_rValid); + assign dBus_cmd_halfPipe_valid = dBus_cmd_rValid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_rData_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_rData_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_rData_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_rData_size; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); assign dBusWishbone_CTI = 3'b000; assign dBusWishbone_BTE = 2'b00; - always @ (*) begin + always @(*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_127 = 4'b0001; + _zz_dBusWishbone_SEL = 4'b0001; end 2'b01 : begin - _zz_127 = 4'b0011; + _zz_dBusWishbone_SEL = 4'b0011; end default : begin - _zz_127 = 4'b1111; + _zz_dBusWishbone_SEL = 4'b1111; end endcase end - always @ (*) begin - dBusWishbone_SEL = (_zz_127 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - if((! dBus_cmd_halfPipe_payload_wr))begin + always @(*) begin + dBusWishbone_SEL = (_zz_dBusWishbone_SEL <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + if(when_DBusSimplePlugin_l189) begin dBusWishbone_SEL = 4'b1111; end end + assign when_DBusSimplePlugin_l189 = (! dBus_cmd_halfPipe_payload_wr); assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); @@ -3621,23 +3673,23 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_62 <= 1'b0; - _zz_64 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_66; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; - _zz_86 <= 1'b1; - _zz_98 <= 1'b0; + _zz_2 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3654,89 +3706,88 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - _zz_113 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_125 <= 3'b000; - _zz_126 <= 1'b0; - dBus_cmd_halfPipe_regs_valid <= 1'b0; - dBus_cmd_halfPipe_regs_ready <= 1'b1; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + dBus_cmd_rValid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_62 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_60)begin - _zz_62 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_64 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_64 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end `ifndef SYNTHESIS @@ -3759,61 +3810,61 @@ module VexRiscv ( end `endif `endif - _zz_86 <= 1'b0; - _zz_98 <= (_zz_42 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_2 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_157)begin - if(_zz_158)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_159)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_160)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_143)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3824,8 +3875,8 @@ module VexRiscv ( end endcase end - if(_zz_144)begin - case(_zz_145) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3835,111 +3886,107 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_112,{_zz_111,_zz_110}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_212[0]; - CsrPlugin_mstatus_MIE <= _zz_213[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_215[0]; - CsrPlugin_mie_MTIE <= _zz_216[0]; - CsrPlugin_mie_MSIE <= _zz_217[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_113 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_156)begin - if(iBusWishbone_ACK)begin - _zz_125 <= (_zz_125 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_126 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_161)begin - dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; - dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); - end else begin - dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); - dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(dBus_cmd_valid) begin + dBus_cmd_rValid <= 1'b1; + end + if(dBus_cmd_halfPipe_fire) begin + dBus_cmd_rValid <= 1'b0; end end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_65 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - _zz_99 <= _zz_41[11 : 7]; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= decodeExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= decodeExceptionPort_payload_badAddr; end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(DBusSimplePlugin_memoryExceptionPort_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusSimplePlugin_memoryExceptionPort_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - end - if(_zz_157)begin - if(_zz_158)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_159)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_160)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_143)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -3948,243 +3995,229 @@ module VexRiscv ( endcase end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_36; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_6) begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_7) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_26; + if(when_Pipeline_l124_9) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_10) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_23; + if(when_Pipeline_l124_14) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_15) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_16) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_20; + if(when_Pipeline_l124_24) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_17; + if(when_Pipeline_l124_26) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_14; + if(when_Pipeline_l124_27) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_11; + if(when_Pipeline_l124_28) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_9; + if(when_Pipeline_l124_29) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_30) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_31) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_32) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_33) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_34) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_35) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; - execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; - execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; - execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; - execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; - execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; - execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; - execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; - execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_28; + if(when_Pipeline_l124_44) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_execute_to_memory_REGFILE_WRITE_DATA; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_33; + if(when_Pipeline_l124_45) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_memory_to_writeBack_REGFILE_WRITE_DATA; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_52) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_53) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_54) begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_214[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_161)begin - dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; - dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; - dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; - dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + if(dBus_cmd_ready) begin + dBus_cmd_rData_wr <= dBus_cmd_payload_wr; + dBus_cmd_rData_address <= dBus_cmd_payload_address; + dBus_cmd_rData_data <= dBus_cmd_payload_data; + dBus_cmd_rData_size <= dBus_cmd_payload_size; end end @@ -4233,13 +4266,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [22:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [22:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [22:0] _zz_ways_0_tags_port1; + wire [22:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -4248,8 +4277,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [6:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -4263,22 +4297,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [8:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_6; - wire _zz_7; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8; + wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -4288,82 +4325,85 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_11 = (! lineLoader_flushCounter[6]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -4379,30 +4419,35 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -4410,51 +4455,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[6]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 7'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -4465,10 +4510,10 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v index 1371328..ac7ffb6 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FomuCfu.v @@ -1,56 +1,57 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : d8ec2d84c3160c3a9131beef2db359dce7a2e4a4 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a -`define Input2Kind_defaultEncoding_type [0:0] -`define Input2Kind_defaultEncoding_RS 1'b0 -`define Input2Kind_defaultEncoding_IMM_I 1'b1 +`define Input2Kind_binary_sequential_type [0:0] +`define Input2Kind_binary_sequential_RS 1'b0 +`define Input2Kind_binary_sequential_IMM_I 1'b1 -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b10 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, + input [31:0] externalInterruptArray, output CfuPlugin_bus_cmd_valid, input CfuPlugin_bus_cmd_ready, output [9:0] CfuPlugin_bus_cmd_payload_function_id, @@ -58,9 +59,7 @@ module VexRiscv ( output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, input CfuPlugin_bus_rsp_valid, output CfuPlugin_bus_rsp_ready, - input CfuPlugin_bus_rsp_payload_response_ok, input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, - input [31:0] externalInterruptArray, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, input iBusWishbone_ACK, @@ -86,18 +85,17 @@ module VexRiscv ( input clk, input reset ); - wire _zz_143; - wire _zz_144; - wire _zz_145; - wire _zz_146; - wire _zz_147; - wire _zz_148; - wire _zz_149; - wire _zz_150; - reg _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -110,269 +108,222 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_155; - wire _zz_156; - wire _zz_157; - wire _zz_158; - wire _zz_159; - wire _zz_160; - wire [1:0] _zz_161; - wire _zz_162; - wire _zz_163; - wire _zz_164; - wire _zz_165; - wire _zz_166; - wire _zz_167; - wire _zz_168; - wire _zz_169; - wire _zz_170; - wire [1:0] _zz_171; - wire _zz_172; - wire _zz_173; - wire _zz_174; - wire _zz_175; - wire _zz_176; - wire _zz_177; - wire _zz_178; - wire [1:0] _zz_179; - wire _zz_180; - wire [1:0] _zz_181; - wire [51:0] _zz_182; - wire [51:0] _zz_183; - wire [51:0] _zz_184; - wire [32:0] _zz_185; - wire [51:0] _zz_186; - wire [49:0] _zz_187; - wire [51:0] _zz_188; - wire [49:0] _zz_189; - wire [51:0] _zz_190; - wire [32:0] _zz_191; - wire [31:0] _zz_192; - wire [32:0] _zz_193; - wire [0:0] _zz_194; - wire [0:0] _zz_195; - wire [0:0] _zz_196; - wire [0:0] _zz_197; - wire [0:0] _zz_198; - wire [0:0] _zz_199; - wire [0:0] _zz_200; - wire [0:0] _zz_201; - wire [0:0] _zz_202; - wire [0:0] _zz_203; - wire [0:0] _zz_204; - wire [0:0] _zz_205; - wire [0:0] _zz_206; - wire [0:0] _zz_207; - wire [2:0] _zz_208; - wire [2:0] _zz_209; - wire [31:0] _zz_210; - wire [0:0] _zz_211; - wire [2:0] _zz_212; - wire [4:0] _zz_213; - wire [11:0] _zz_214; - wire [11:0] _zz_215; - wire [31:0] _zz_216; - wire [31:0] _zz_217; - wire [31:0] _zz_218; - wire [31:0] _zz_219; - wire [31:0] _zz_220; - wire [31:0] _zz_221; - wire [31:0] _zz_222; - wire [19:0] _zz_223; - wire [11:0] _zz_224; - wire [11:0] _zz_225; - wire [1:0] _zz_226; - wire [1:0] _zz_227; - wire [9:0] _zz_228; - wire [7:0] _zz_229; - wire [65:0] _zz_230; - wire [65:0] _zz_231; - wire [31:0] _zz_232; - wire [31:0] _zz_233; - wire [0:0] _zz_234; - wire [0:0] _zz_235; - wire [0:0] _zz_236; - wire [0:0] _zz_237; - wire [0:0] _zz_238; - wire [0:0] _zz_239; - wire [26:0] _zz_240; - wire _zz_241; - wire _zz_242; - wire [1:0] _zz_243; - wire [31:0] _zz_244; - wire [31:0] _zz_245; - wire [31:0] _zz_246; - wire _zz_247; - wire [0:0] _zz_248; - wire [14:0] _zz_249; - wire [31:0] _zz_250; - wire [31:0] _zz_251; - wire [31:0] _zz_252; - wire _zz_253; - wire [0:0] _zz_254; - wire [8:0] _zz_255; - wire [31:0] _zz_256; - wire [31:0] _zz_257; - wire [31:0] _zz_258; - wire _zz_259; - wire [0:0] _zz_260; - wire [2:0] _zz_261; - wire _zz_262; - wire [0:0] _zz_263; - wire [0:0] _zz_264; - wire _zz_265; - wire [0:0] _zz_266; - wire [22:0] _zz_267; - wire [31:0] _zz_268; - wire [31:0] _zz_269; - wire [31:0] _zz_270; - wire [31:0] _zz_271; - wire _zz_272; - wire _zz_273; - wire [1:0] _zz_274; - wire [1:0] _zz_275; - wire _zz_276; - wire [0:0] _zz_277; - wire [18:0] _zz_278; - wire [31:0] _zz_279; - wire [31:0] _zz_280; - wire [31:0] _zz_281; - wire [31:0] _zz_282; - wire [31:0] _zz_283; - wire [31:0] _zz_284; - wire [0:0] _zz_285; - wire [1:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; - wire _zz_289; - wire [0:0] _zz_290; - wire [15:0] _zz_291; - wire [31:0] _zz_292; - wire [31:0] _zz_293; - wire [31:0] _zz_294; - wire [31:0] _zz_295; - wire [31:0] _zz_296; - wire [31:0] _zz_297; - wire [31:0] _zz_298; - wire [31:0] _zz_299; - wire _zz_300; - wire [1:0] _zz_301; - wire [1:0] _zz_302; - wire _zz_303; - wire [0:0] _zz_304; - wire [12:0] _zz_305; - wire [31:0] _zz_306; - wire [31:0] _zz_307; - wire [31:0] _zz_308; - wire [31:0] _zz_309; - wire [31:0] _zz_310; - wire [31:0] _zz_311; - wire [2:0] _zz_312; - wire [2:0] _zz_313; - wire _zz_314; - wire [0:0] _zz_315; - wire [9:0] _zz_316; - wire [31:0] _zz_317; - wire [31:0] _zz_318; - wire [31:0] _zz_319; - wire [31:0] _zz_320; - wire [31:0] _zz_321; - wire _zz_322; - wire [0:0] _zz_323; - wire [2:0] _zz_324; - wire [0:0] _zz_325; - wire [3:0] _zz_326; - wire [5:0] _zz_327; - wire [5:0] _zz_328; - wire _zz_329; - wire [0:0] _zz_330; - wire [5:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [31:0] _zz_334; - wire [0:0] _zz_335; - wire [0:0] _zz_336; - wire _zz_337; - wire [0:0] _zz_338; - wire [1:0] _zz_339; - wire [0:0] _zz_340; - wire [3:0] _zz_341; - wire [0:0] _zz_342; - wire [0:0] _zz_343; - wire [1:0] _zz_344; - wire [1:0] _zz_345; - wire _zz_346; - wire [0:0] _zz_347; - wire [3:0] _zz_348; - wire [31:0] _zz_349; - wire [31:0] _zz_350; - wire [31:0] _zz_351; - wire [31:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire [31:0] _zz_355; - wire _zz_356; - wire _zz_357; - wire [31:0] _zz_358; - wire [31:0] _zz_359; - wire _zz_360; - wire [0:0] _zz_361; - wire [1:0] _zz_362; - wire [31:0] _zz_363; - wire [31:0] _zz_364; - wire _zz_365; - wire [0:0] _zz_366; - wire [2:0] _zz_367; - wire [0:0] _zz_368; - wire [0:0] _zz_369; - wire _zz_370; - wire [0:0] _zz_371; - wire [1:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire [31:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire _zz_378; - wire _zz_379; - wire [31:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; - wire _zz_383; - wire [0:0] _zz_384; - wire [0:0] _zz_385; - wire [31:0] _zz_386; - wire [31:0] _zz_387; - wire [0:0] _zz_388; - wire [1:0] _zz_389; - wire [1:0] _zz_390; - wire [1:0] _zz_391; - wire _zz_392; - wire _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire [31:0] _zz_399; - wire [31:0] _zz_400; - wire _zz_401; - wire _zz_402; - wire _zz_403; - wire [0:0] _zz_404; - wire [0:0] _zz_405; - wire _zz_406; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11; + wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30; + wire [18:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39; + wire [15:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50; + wire [12:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72; + wire [9:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_lastStageRegFileWrite_payload_data; + wire [31:0] _zz__zz_lastStageRegFileWrite_payload_data_1; + wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire [31:0] memory_MEMORY_READ_DATA; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; - wire writeBack_CfuPlugin_CFU_IN_FLIGHT; - wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire [31:0] memory_REGFILE_WRITE_DATA; wire [31:0] execute_REGFILE_WRITE_DATA; wire [1:0] memory_MEMORY_ADDRESS_LOW; wire [1:0] execute_MEMORY_ADDRESS_LOW; @@ -381,86 +332,88 @@ module VexRiscv ( wire decode_SRC2_FORCE_ZERO; wire [31:0] decode_RS2; wire [31:0] decode_RS1; + wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + wire decode_CfuPlugin_CFU_ENABLE; wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_1; - wire `Input2Kind_defaultEncoding_type _zz_2; - wire `Input2Kind_defaultEncoding_type _zz_3; - wire decode_CfuPlugin_CFU_ENABLE; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12; - wire `BranchCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_18; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_21; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_25; - wire `Src2CtrlEnum_defaultEncoding_type _zz_26; - wire `Src2CtrlEnum_defaultEncoding_type _zz_27; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_28; - wire `Src1CtrlEnum_defaultEncoding_type _zz_29; - wire `Src1CtrlEnum_defaultEncoding_type _zz_30; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire decode_MEMORY_ENABLE; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire execute_CfuPlugin_CFU_ENABLE; wire writeBack_IS_MUL; wire [33:0] writeBack_MUL_HH; wire [51:0] writeBack_MUL_LOW; wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; - reg _zz_31; - reg _zz_32; - wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_33; - wire execute_CfuPlugin_CFU_ENABLE; - reg [31:0] _zz_34; + reg [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_36; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_37; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_PC; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_38; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; @@ -470,89 +423,65 @@ module VexRiscv ( wire memory_BYPASSABLE_MEMORY_STAGE; wire writeBack_REGFILE_WRITE_VALID; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_39; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_41; + reg [31:0] _zz_memory_to_writeBack_REGFILE_WRITE_DATA; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_42; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_43; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_44; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_45; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; - wire [31:0] _zz_47; - wire _zz_48; - reg _zz_49; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_50; - wire `EnvCtrlEnum_defaultEncoding_type _zz_51; - wire `BranchCtrlEnum_defaultEncoding_type _zz_52; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_53; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_54; - wire `AluCtrlEnum_defaultEncoding_type _zz_55; - wire `Src2CtrlEnum_defaultEncoding_type _zz_56; - wire `Src1CtrlEnum_defaultEncoding_type _zz_57; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; wire writeBack_MEMORY_STORE; - reg [31:0] _zz_58; + reg [31:0] _zz_lastStageRegFileWrite_payload_data; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP2_physicalAddress; - wire memory_MMU_RSP2_isIoAccess; - wire memory_MMU_RSP2_isPaging; - wire memory_MMU_RSP2_allowRead; - wire memory_MMU_RSP2_allowWrite; - wire memory_MMU_RSP2_allowExecute; - wire memory_MMU_RSP2_exception; - wire memory_MMU_RSP2_refilling; - wire memory_MMU_RSP2_bypassTranslation; - wire [31:0] memory_PC; - wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP2_physicalAddress; - wire execute_MMU_RSP2_isIoAccess; - wire execute_MMU_RSP2_isPaging; - wire execute_MMU_RSP2_allowRead; - wire execute_MMU_RSP2_allowWrite; - wire execute_MMU_RSP2_allowExecute; - wire execute_MMU_RSP2_exception; - wire execute_MMU_RSP2_refilling; - wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; - wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_59; - reg [31:0] _zz_60; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; + wire decode_arbitration_haltItself; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; wire decode_arbitration_flushIt; @@ -577,8 +506,8 @@ module VexRiscv ( reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; - reg memory_arbitration_flushNext; + wire memory_arbitration_flushIt; + wire memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; @@ -621,31 +550,16 @@ module VexRiscv ( wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; wire IBusCachedPlugin_mmuBus_end; wire IBusCachedPlugin_mmuBus_busy; - reg DBusSimplePlugin_memoryExceptionPort_valid; - reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; - wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_0_isValid; - wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_isPaging; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; wire CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -663,30 +577,30 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; - reg CfuPlugin_joinException_valid; - wire [3:0] CfuPlugin_joinException_payload_code; - wire [31:0] CfuPlugin_joinException_payload_badAddr; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [2:0] _zz_61; - wire [2:0] _zz_62; - wire _zz_63; - wire _zz_64; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -709,16 +623,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_65; - wire _zz_66; - wire _zz_67; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_68; - wire _zz_69; - reg _zz_70; - wire _zz_71; - reg _zz_72; - reg [31:0] _zz_73; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -726,11 +642,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l329_4; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -738,7 +661,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_74; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -746,6 +669,9 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l267; wire dBus_cmd_valid; wire dBus_cmd_ready; wire dBus_cmd_payload_wr; @@ -755,31 +681,36 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - wire _zz_75; + wire _zz_dBus_cmd_valid; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_76; - reg [3:0] _zz_77; + reg [31:0] _zz_dBus_cmd_payload_data; + wire when_DBusSimplePlugin_l426; + reg [3:0] _zz_execute_DBusSimplePlugin_formalMask; wire [3:0] execute_DBusSimplePlugin_formalMask; + wire when_DBusSimplePlugin_l479; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_78; - reg [31:0] _zz_79; - wire _zz_80; - reg [31:0] _zz_81; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusSimplePlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1; + wire _zz_writeBack_DBusSimplePlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3; reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [29:0] _zz_82; - wire _zz_83; - wire _zz_84; - wire _zz_85; - wire _zz_86; - wire _zz_87; - wire `Src1CtrlEnum_defaultEncoding_type _zz_88; - wire `Src2CtrlEnum_defaultEncoding_type _zz_89; - wire `AluCtrlEnum_defaultEncoding_type _zz_90; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_91; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_92; - wire `BranchCtrlEnum_defaultEncoding_type _zz_93; - wire `EnvCtrlEnum_defaultEncoding_type _zz_94; - wire `Input2Kind_defaultEncoding_type _zz_95; + wire when_DBusSimplePlugin_l558; + wire [29:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -787,37 +718,58 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_96; + reg _zz_2; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_97; - reg [31:0] _zz_98; - wire _zz_99; - reg [19:0] _zz_100; - wire _zz_101; - reg [19:0] _zz_102; - reg [31:0] _zz_103; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_104; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_105; - reg _zz_106; - reg _zz_107; - reg _zz_108; - reg [4:0] _zz_109; + reg [31:0] _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l59; + wire when_HazardSimplePlugin_l62; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l59_1; + wire when_HazardSimplePlugin_l62_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l59_2; + wire when_HazardSimplePlugin_l62_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_110; - reg _zz_111; - reg _zz_112; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_DO; + reg _zz_execute_BRANCH_DO_1; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_113; - reg [10:0] _zz_114; - wire _zz_115; - reg [19:0] _zz_116; - wire _zz_117; - reg [18:0] _zz_118; - reg [31:0] _zz_119; + wire _zz_execute_BranchPlugin_branch_src2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -839,9 +791,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_120; - wire _zz_121; - wire _zz_122; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -854,54 +806,62 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_123; - wire _zz_124; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; - wire execute_CfuPlugin_schedule; - reg execute_CfuPlugin_hold; - reg execute_CfuPlugin_fired; - wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_125; - reg [23:0] _zz_126; - reg [31:0] _zz_127; - wire memory_CfuPlugin_rsp_valid; - reg memory_CfuPlugin_rsp_ready; - wire memory_CfuPlugin_rsp_payload_response_ok; - wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_s2mPipe_rValid; - reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -909,100 +869,186 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_128; - wire [31:0] _zz_129; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire CfuPlugin_bus_cmd_fire; + wire when_CfuPlugin_l171; + wire when_CfuPlugin_l175; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_CfuPlugin_bus_cmd_payload_inputs_1; + reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1; + reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + wire CfuPlugin_bus_rsp_rsp_valid; + reg CfuPlugin_bus_rsp_rsp_ready; + wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_rValid; + reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; + wire when_CfuPlugin_l208; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_9; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg memory_to_writeBack_MEMORY_ENABLE; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_14; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_16; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_19; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_20; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_MEMORY_STORE; + wire when_Pipeline_l124_22; reg execute_to_memory_MEMORY_STORE; + wire when_Pipeline_l124_23; reg memory_to_writeBack_MEMORY_STORE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_24; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_25; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_26; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_27; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_28; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_29; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_30; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_31; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_32; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_34; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_35; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_36; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_37; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + wire when_Pipeline_l124_38; + reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_39; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_40; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_41; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_42; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_43; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_44; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_45; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_MMU_FAULT; - reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; - reg execute_to_memory_MMU_RSP2_isIoAccess; - reg execute_to_memory_MMU_RSP2_isPaging; - reg execute_to_memory_MMU_RSP2_allowRead; - reg execute_to_memory_MMU_RSP2_allowWrite; - reg execute_to_memory_MMU_RSP2_allowExecute; - reg execute_to_memory_MMU_RSP2_exception; - reg execute_to_memory_MMU_RSP2_refilling; - reg execute_to_memory_MMU_RSP2_bypassTranslation; + wire when_Pipeline_l124_46; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_47; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_48; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_49; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_50; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_51; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_52; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_53; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_54; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_55; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_56; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + wire when_Pipeline_l124_57; reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_130; - reg [31:0] _zz_131; - reg [31:0] _zz_132; - reg [31:0] _zz_133; - reg [31:0] _zz_134; - reg [31:0] _zz_135; - reg [31:0] _zz_136; - reg [31:0] _zz_137; - reg [31:0] _zz_138; - reg [31:0] _zz_139; - reg [2:0] _zz_140; - reg _zz_141; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -1010,90 +1056,91 @@ module VexRiscv ( wire [31:0] dBus_cmd_halfPipe_payload_address; wire [31:0] dBus_cmd_halfPipe_payload_data; wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_142; + reg dBus_cmd_rValid; + wire dBus_cmd_halfPipe_fire; + reg dBus_cmd_rData_wr; + reg [31:0] dBus_cmd_rData_address; + reg [31:0] dBus_cmd_rData_data; + reg [1:0] dBus_cmd_rData_size; + reg [3:0] _zz_dBusWishbone_SEL; + wire when_DBusSimplePlugin_l189; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8_string; - reg [39:0] _zz_9_string; - reg [39:0] _zz_10_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_11_string; - reg [31:0] _zz_12_string; - reg [31:0] _zz_13_string; - reg [71:0] _zz_14_string; - reg [71:0] _zz_15_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_16_string; - reg [71:0] _zz_17_string; - reg [71:0] _zz_18_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_19_string; - reg [39:0] _zz_20_string; - reg [39:0] _zz_21_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_22_string; - reg [63:0] _zz_23_string; - reg [63:0] _zz_24_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_25_string; - reg [23:0] _zz_26_string; - reg [23:0] _zz_27_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_28_string; - reg [95:0] _zz_29_string; - reg [95:0] _zz_30_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_36_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_37_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_38_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_40_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_41_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_43_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_44_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_45_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_46_string; - reg [39:0] _zz_50_string; - reg [39:0] _zz_51_string; - reg [31:0] _zz_52_string; - reg [71:0] _zz_53_string; - reg [39:0] _zz_54_string; - reg [63:0] _zz_55_string; - reg [23:0] _zz_56_string; - reg [95:0] _zz_57_string; - reg [95:0] _zz_88_string; - reg [23:0] _zz_89_string; - reg [63:0] _zz_90_string; - reg [39:0] _zz_91_string; - reg [71:0] _zz_92_string; - reg [31:0] _zz_93_string; - reg [39:0] _zz_94_string; - reg [39:0] _zz_95_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; @@ -1109,1075 +1156,1012 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_155 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_156 = ((_zz_148 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_157 = ((_zz_148 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_158 = ({CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_159 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_160 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_161 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_162 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_163 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_164 = (1'b1 || (! 1'b1)); - assign _zz_165 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_166 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_167 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_168 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_169 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_170 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_171 = execute_INSTRUCTION[13 : 12]; - assign _zz_172 = (iBus_cmd_valid || (_zz_140 != 3'b000)); - assign _zz_173 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_174 = ((_zz_120 && 1'b1) && (! 1'b0)); - assign _zz_175 = ((_zz_121 && 1'b1) && (! 1'b0)); - assign _zz_176 = ((_zz_122 && 1'b1) && (! 1'b0)); - assign _zz_177 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_178 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_179 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_180 = execute_INSTRUCTION[13]; - assign _zz_181 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_182 = ($signed(_zz_183) + $signed(_zz_188)); - assign _zz_183 = ($signed(_zz_184) + $signed(_zz_186)); - assign _zz_184 = 52'h0; - assign _zz_185 = {1'b0,memory_MUL_LL}; - assign _zz_186 = {{19{_zz_185[32]}}, _zz_185}; - assign _zz_187 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_188 = {{2{_zz_187[49]}}, _zz_187}; - assign _zz_189 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_190 = {{2{_zz_189[49]}}, _zz_189}; - assign _zz_191 = ($signed(_zz_193) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_192 = _zz_191[31 : 0]; - assign _zz_193 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_194 = _zz_82[29 : 29]; - assign _zz_195 = _zz_82[27 : 27]; - assign _zz_196 = _zz_82[24 : 24]; - assign _zz_197 = _zz_82[15 : 15]; - assign _zz_198 = _zz_82[11 : 11]; - assign _zz_199 = _zz_82[10 : 10]; - assign _zz_200 = _zz_82[9 : 9]; - assign _zz_201 = _zz_82[12 : 12]; - assign _zz_202 = _zz_82[5 : 5]; - assign _zz_203 = _zz_82[3 : 3]; - assign _zz_204 = _zz_82[18 : 18]; - assign _zz_205 = _zz_82[8 : 8]; - assign _zz_206 = _zz_82[4 : 4]; - assign _zz_207 = _zz_82[0 : 0]; - assign _zz_208 = (_zz_61 - 3'b001); - assign _zz_209 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_210 = {29'd0, _zz_209}; - assign _zz_211 = execute_SRC_LESS; - assign _zz_212 = 3'b100; - assign _zz_213 = execute_INSTRUCTION[19 : 15]; - assign _zz_214 = execute_INSTRUCTION[31 : 20]; - assign _zz_215 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_216 = ($signed(_zz_217) + $signed(_zz_220)); - assign _zz_217 = ($signed(_zz_218) + $signed(_zz_219)); - assign _zz_218 = execute_SRC1; - assign _zz_219 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_220 = (execute_SRC_USE_SUB_LESS ? _zz_221 : _zz_222); - assign _zz_221 = 32'h00000001; - assign _zz_222 = 32'h0; - assign _zz_223 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_224 = execute_INSTRUCTION[31 : 20]; - assign _zz_225 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_226 = (_zz_123 & (~ _zz_227)); - assign _zz_227 = (_zz_123 - 2'b01); - assign _zz_228 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_229 = execute_INSTRUCTION[31 : 24]; - assign _zz_230 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_231 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_232 = writeBack_MUL_LOW[31 : 0]; - assign _zz_233 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_234 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_235 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_236 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_237 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_238 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_239 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_240 = (iBus_cmd_payload_address >>> 5); - assign _zz_241 = 1'b1; - assign _zz_242 = 1'b1; - assign _zz_243 = {_zz_64,_zz_63}; - assign _zz_244 = 32'h0000106f; - assign _zz_245 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_246 = 32'h00001073; - assign _zz_247 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_248 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_249 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_250) == 32'h00000003),{(_zz_251 == _zz_252),{_zz_253,{_zz_254,_zz_255}}}}}}; - assign _zz_250 = 32'h0000207f; - assign _zz_251 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_252 = 32'h00000003; - assign _zz_253 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_254 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_255 = {((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033),{((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_256) == 32'h00005013),{(_zz_257 == _zz_258),{_zz_259,{_zz_260,_zz_261}}}}}}; - assign _zz_256 = 32'hbc00707f; - assign _zz_257 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_258 = 32'h00001013; - assign _zz_259 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_260 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_261 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_262 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); - assign _zz_263 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); - assign _zz_264 = 1'b0; - assign _zz_265 = ({(_zz_268 == _zz_269),(_zz_270 == _zz_271)} != 2'b00); - assign _zz_266 = ({_zz_86,_zz_272} != 2'b00); - assign _zz_267 = {(_zz_273 != 1'b0),{(_zz_274 != _zz_275),{_zz_276,{_zz_277,_zz_278}}}}; - assign _zz_268 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_269 = 32'h00001050; - assign _zz_270 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_271 = 32'h00002050; - assign _zz_272 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_273 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_274 = {(_zz_279 == _zz_280),(_zz_281 == _zz_282)}; - assign _zz_275 = 2'b00; - assign _zz_276 = ((_zz_283 == _zz_284) != 1'b0); - assign _zz_277 = ({_zz_285,_zz_286} != 3'b000); - assign _zz_278 = {(_zz_287 != _zz_288),{_zz_289,{_zz_290,_zz_291}}}; - assign _zz_279 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_280 = 32'h00000040; - assign _zz_281 = (decode_INSTRUCTION & 32'h00403040); - assign _zz_282 = 32'h00000040; - assign _zz_283 = (decode_INSTRUCTION & 32'h00007054); - assign _zz_284 = 32'h00005010; - assign _zz_285 = ((decode_INSTRUCTION & _zz_292) == 32'h40001010); - assign _zz_286 = {(_zz_293 == _zz_294),(_zz_295 == _zz_296)}; - assign _zz_287 = ((decode_INSTRUCTION & _zz_297) == 32'h00000024); - assign _zz_288 = 1'b0; - assign _zz_289 = ((_zz_298 == _zz_299) != 1'b0); - assign _zz_290 = (_zz_300 != 1'b0); - assign _zz_291 = {(_zz_301 != _zz_302),{_zz_303,{_zz_304,_zz_305}}}; - assign _zz_292 = 32'h40003054; - assign _zz_293 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_294 = 32'h00001010; - assign _zz_295 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_296 = 32'h00001010; - assign _zz_297 = 32'h00000064; - assign _zz_298 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_299 = 32'h00001000; - assign _zz_300 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_301 = {(_zz_306 == _zz_307),(_zz_308 == _zz_309)}; - assign _zz_302 = 2'b00; - assign _zz_303 = ((_zz_310 == _zz_311) != 1'b0); - assign _zz_304 = (_zz_84 != 1'b0); - assign _zz_305 = {(_zz_312 != _zz_313),{_zz_314,{_zz_315,_zz_316}}}; - assign _zz_306 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_307 = 32'h00002000; - assign _zz_308 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_309 = 32'h00001000; - assign _zz_310 = (decode_INSTRUCTION & 32'h00004004); - assign _zz_311 = 32'h00004000; - assign _zz_312 = {_zz_87,{(_zz_317 == _zz_318),(_zz_319 == _zz_320)}}; - assign _zz_313 = 3'b000; - assign _zz_314 = (((decode_INSTRUCTION & _zz_321) == 32'h00000020) != 1'b0); - assign _zz_315 = ({_zz_322,{_zz_323,_zz_324}} != 5'h0); - assign _zz_316 = {({_zz_325,_zz_326} != 5'h0),{(_zz_327 != _zz_328),{_zz_329,{_zz_330,_zz_331}}}}; - assign _zz_317 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_318 = 32'h00000020; - assign _zz_319 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_320 = 32'h00000020; - assign _zz_321 = 32'h00000020; - assign _zz_322 = ((decode_INSTRUCTION & _zz_332) == 32'h00000008); - assign _zz_323 = (_zz_333 == _zz_334); - assign _zz_324 = {_zz_85,{_zz_335,_zz_336}}; - assign _zz_325 = _zz_85; - assign _zz_326 = {_zz_337,{_zz_338,_zz_339}}; - assign _zz_327 = {_zz_86,{_zz_340,_zz_341}}; - assign _zz_328 = 6'h0; - assign _zz_329 = ({_zz_342,_zz_343} != 2'b00); - assign _zz_330 = (_zz_344 != _zz_345); - assign _zz_331 = {_zz_346,{_zz_347,_zz_348}}; - assign _zz_332 = 32'h00000008; - assign _zz_333 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_334 = 32'h00000040; - assign _zz_335 = (_zz_349 == _zz_350); - assign _zz_336 = (_zz_351 == _zz_352); - assign _zz_337 = ((decode_INSTRUCTION & _zz_353) == 32'h00002010); - assign _zz_338 = (_zz_354 == _zz_355); - assign _zz_339 = {_zz_356,_zz_357}; - assign _zz_340 = (_zz_358 == _zz_359); - assign _zz_341 = {_zz_360,{_zz_361,_zz_362}}; - assign _zz_342 = _zz_85; - assign _zz_343 = (_zz_363 == _zz_364); - assign _zz_344 = {_zz_85,_zz_365}; - assign _zz_345 = 2'b00; - assign _zz_346 = ({_zz_366,_zz_367} != 4'b0000); - assign _zz_347 = (_zz_368 != _zz_369); - assign _zz_348 = {_zz_370,{_zz_371,_zz_372}}; - assign _zz_349 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_350 = 32'h00000010; - assign _zz_351 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_352 = 32'h00000020; - assign _zz_353 = 32'h00002030; - assign _zz_354 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_355 = 32'h00000010; - assign _zz_356 = ((decode_INSTRUCTION & _zz_373) == 32'h00002020); - assign _zz_357 = ((decode_INSTRUCTION & _zz_374) == 32'h00000020); - assign _zz_358 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_359 = 32'h00001010; - assign _zz_360 = ((decode_INSTRUCTION & _zz_375) == 32'h00002010); - assign _zz_361 = (_zz_376 == _zz_377); - assign _zz_362 = {_zz_378,_zz_379}; - assign _zz_363 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_364 = 32'h00000020; - assign _zz_365 = ((decode_INSTRUCTION & _zz_380) == 32'h0); - assign _zz_366 = (_zz_381 == _zz_382); - assign _zz_367 = {_zz_383,{_zz_384,_zz_385}}; - assign _zz_368 = (_zz_386 == _zz_387); - assign _zz_369 = 1'b0; - assign _zz_370 = ({_zz_388,_zz_389} != 3'b000); - assign _zz_371 = (_zz_390 != _zz_391); - assign _zz_372 = {_zz_392,_zz_393}; - assign _zz_373 = 32'h02002060; - assign _zz_374 = 32'h02003020; - assign _zz_375 = 32'h00002010; - assign _zz_376 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_377 = 32'h00000010; - assign _zz_378 = ((decode_INSTRUCTION & _zz_394) == 32'h00000004); - assign _zz_379 = ((decode_INSTRUCTION & _zz_395) == 32'h0); - assign _zz_380 = 32'h00000020; - assign _zz_381 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_382 = 32'h0; - assign _zz_383 = ((decode_INSTRUCTION & _zz_396) == 32'h0); - assign _zz_384 = _zz_84; - assign _zz_385 = (_zz_397 == _zz_398); - assign _zz_386 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_387 = 32'h0; - assign _zz_388 = (_zz_399 == _zz_400); - assign _zz_389 = {_zz_401,_zz_402}; - assign _zz_390 = {_zz_403,_zz_83}; - assign _zz_391 = 2'b00; - assign _zz_392 = ({_zz_404,_zz_405} != 2'b00); - assign _zz_393 = (_zz_406 != 1'b0); - assign _zz_394 = 32'h0000000c; - assign _zz_395 = 32'h00000024; - assign _zz_396 = 32'h00000018; - assign _zz_397 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_398 = 32'h00001000; - assign _zz_399 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_400 = 32'h00000040; - assign _zz_401 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_402 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_403 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_404 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_405 = _zz_83; - assign _zz_406 = ((decode_INSTRUCTION & 32'h00001054) == 32'h00001004); - always @ (posedge clk) begin - if(_zz_241) begin - _zz_152 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_242) begin - _zz_153 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_49) begin + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz_IBusCachedPlugin_jump_pcLoad_payload_2)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 2'b01); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_lastStageRegFileWrite_payload_data = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_lastStageRegFileWrite_payload_data_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00407f) == 32'h00000033),{((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = (decode_INSTRUCTION & 32'h02000074); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 32'h02000030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = ((decode_INSTRUCTION & 32'h10003050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = ({(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9)} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31}}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = 32'h00001050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = 32'h00002050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (decode_INSTRUCTION & 32'h00403040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007054); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25) == 32'h40001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33) == 32'h00000024); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 32'h40003054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = (decode_INSTRUCTION & 32'h02007054); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = 32'h00000064; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = (decode_INSTRUCTION & 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = (_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = (decode_INSTRUCTION & 32'h00005000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = (decode_INSTRUCTION & 32'h00004004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 32'h00004000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7,{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56)}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 3'b000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59) == 32'h00000020) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66}} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = {({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75} != 5'h0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112}}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = (decode_INSTRUCTION & 32'h00000034); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62) == 32'h00000008); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = 6'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000008; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117} != 4'b0000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = (decode_INSTRUCTION & 32'h00000030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = (decode_INSTRUCTION & 32'h02000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = 32'h00002030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83) == 32'h00002020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = 32'h02002060; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = 32'h02003020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139,_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = 32'h0000000c; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h00000024; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = 32'h00000018; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = (decode_INSTRUCTION & 32'h00005004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = ((decode_INSTRUCTION & 32'h00001054) == 32'h00001004); + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_143 ), //i - .io_cpu_prefetch_isValid (_zz_144 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_145 ), //i - .io_cpu_fetch_isStuck (_zz_146 ), //i - .io_cpu_fetch_isRemoved (_zz_147 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_148 ), //i - .io_cpu_decode_isStuck (_zz_149 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_150 ), //i - .io_cpu_fill_valid (_zz_151 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); - always @(*) begin - case(_zz_243) - 2'b00 : begin - _zz_154 = CsrPlugin_jumpInterface_payload; - end - 2'b01 : begin - _zz_154 = DBusSimplePlugin_redoBranch_payload; - end - default : begin - _zz_154 = BranchPlugin_jumpInterface_payload; - end - endcase - end - `ifndef SYNTHESIS always @(*) begin case(decode_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_1) - `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; - default : _zz_1_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; - default : _zz_2_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; - default : _zz_3_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; - default : _zz_8_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_9) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; - default : _zz_9_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_10) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; - default : _zz_10_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_11) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; - default : _zz_11_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_12) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; - default : _zz_12_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_13) - `BranchCtrlEnum_defaultEncoding_INC : _zz_13_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_13_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_13_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_13_string = "JALR"; - default : _zz_13_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_16) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; - default : _zz_16_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_17) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; - default : _zz_17_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_18) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_18_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_18_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_18_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_18_string = "SRA_1 "; - default : _zz_18_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_19) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; - default : _zz_19_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_20) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; - default : _zz_20_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_21) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_21_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_21_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_21_string = "AND_1"; - default : _zz_21_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_25) - `Src2CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_25_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_25_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_25_string = "PC "; - default : _zz_25_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_26) - `Src2CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_26_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_26_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_26_string = "PC "; - default : _zz_26_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_27) - `Src2CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_27_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_27_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_27_string = "PC "; - default : _zz_27_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_28) - `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; - default : _zz_28_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_29) - `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; - default : _zz_29_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_30) - `Src1CtrlEnum_defaultEncoding_RS : _zz_30_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_30_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_30_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_30_string = "URS1 "; - default : _zz_30_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_33) - `Input2Kind_defaultEncoding_RS : _zz_33_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_33_string = "IMM_I"; - default : _zz_33_string = "?????"; + case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_36) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_36_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_36_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_36_string = "ECALL"; - default : _zz_36_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_37) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_37_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_37_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_37_string = "ECALL"; - default : _zz_37_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_38) - `BranchCtrlEnum_defaultEncoding_INC : _zz_38_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_38_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_38_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_38_string = "JALR"; - default : _zz_38_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_40) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; - default : _zz_40_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_41) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_41_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_41_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_41_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_41_string = "SRA_1 "; - default : _zz_41_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_43) - `Src2CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_43_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_43_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_43_string = "PC "; - default : _zz_43_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_44) - `Src1CtrlEnum_defaultEncoding_RS : _zz_44_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_44_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_44_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_44_string = "URS1 "; - default : _zz_44_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_45) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; - default : _zz_45_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_46) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; - default : _zz_46_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_50) - `Input2Kind_defaultEncoding_RS : _zz_50_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_50_string = "IMM_I"; - default : _zz_50_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_51) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_51_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_51_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_51_string = "ECALL"; - default : _zz_51_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_52) - `BranchCtrlEnum_defaultEncoding_INC : _zz_52_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_52_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_52_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_52_string = "JALR"; - default : _zz_52_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_53) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_53_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_53_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_53_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_53_string = "SRA_1 "; - default : _zz_53_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_54) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_54_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_54_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_54_string = "AND_1"; - default : _zz_54_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_55) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; - default : _zz_55_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_56) - `Src2CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_56_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_56_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_56_string = "PC "; - default : _zz_56_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_57) - `Src1CtrlEnum_defaultEncoding_RS : _zz_57_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_57_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_57_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_57_string = "URS1 "; - default : _zz_57_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin - case(_zz_88) - `Src1CtrlEnum_defaultEncoding_RS : _zz_88_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_88_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_88_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_88_string = "URS1 "; - default : _zz_88_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_89) - `Src2CtrlEnum_defaultEncoding_RS : _zz_89_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_89_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_89_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_89_string = "PC "; - default : _zz_89_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_90) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_90_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_90_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_90_string = "BITWISE "; - default : _zz_90_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_91) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_91_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_91_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_91_string = "AND_1"; - default : _zz_91_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_92) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_92_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_92_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_92_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_92_string = "SRA_1 "; - default : _zz_92_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_93) - `BranchCtrlEnum_defaultEncoding_INC : _zz_93_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_93_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_93_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_93_string = "JALR"; - default : _zz_93_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_94) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_94_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_94_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_94_string = "ECALL"; - default : _zz_94_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_95) - `Input2Kind_defaultEncoding_RS : _zz_95_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_95_string = "IMM_I"; - default : _zz_95_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_182) + $signed(_zz_190)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); assign memory_MEMORY_READ_DATA = dBus_rsp_data; + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_192; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_97; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); @@ -2185,82 +2169,84 @@ module VexRiscv ( assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_194[0]; - assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; - assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_195[0]; - assign _zz_4 = _zz_5; - assign _zz_6 = _zz_7; - assign decode_ENV_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_196[0]; - assign decode_BRANCH_CTRL = _zz_11; - assign _zz_12 = _zz_13; - assign _zz_14 = _zz_15; - assign decode_SHIFT_CTRL = _zz_16; - assign _zz_17 = _zz_18; - assign decode_ALU_BITWISE_CTRL = _zz_19; - assign _zz_20 = _zz_21; - assign decode_SRC_LESS_UNSIGNED = _zz_197[0]; - assign decode_ALU_CTRL = _zz_22; - assign _zz_23 = _zz_24; - assign decode_MEMORY_STORE = _zz_198[0]; + assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24]; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15]; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_STORE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_199[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_200[0]; - assign decode_SRC2_CTRL = _zz_25; - assign _zz_26 = _zz_27; - assign decode_SRC1_CTRL = _zz_28; - assign _zz_29 = _zz_30; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4]; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); - assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; - assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; - assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; - assign memory_MUL_HL = execute_to_memory_MUL_HL; - assign memory_MUL_LH = execute_to_memory_MUL_LH; - assign memory_MUL_LL = execute_to_memory_MUL_LL; - always @ (*) begin - _zz_31 = memory_CfuPlugin_CFU_IN_FLIGHT; - if(memory_arbitration_isStuck)begin - _zz_31 = 1'b0; + assign memory_PC = execute_to_memory_PC; + always @(*) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0; end end - always @ (*) begin - _zz_32 = execute_CfuPlugin_CFU_IN_FLIGHT; - if(execute_arbitration_isStuck)begin - _zz_32 = 1'b0; + always @(*) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0; end end assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_33; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; - always @ (*) begin - _zz_34 = execute_REGFILE_WRITE_DATA; - if(_zz_155)begin - _zz_34 = execute_CsrPlugin_readData; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + always @(*) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = CsrPlugin_csrMapping_readDataSignal; end end assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_35; - assign execute_ENV_CTRL = _zz_36; - assign writeBack_ENV_CTRL = _zz_37; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_112; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_38; - assign decode_RS2_USE = _zz_201[0]; - assign decode_RS1_USE = _zz_202[0]; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12]; + assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; @@ -2268,72 +2254,72 @@ module VexRiscv ( assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_39 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_memory_to_writeBack_REGFILE_WRITE_DATA = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_39 = _zz_105; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_memory_to_writeBack_REGFILE_WRITE_DATA = _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_39 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_memory_to_writeBack_REGFILE_WRITE_DATA = memory_SHIFT_RIGHT; end default : begin end endcase end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_39 = memory_CfuPlugin_rsp_payload_outputs_0; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + _zz_memory_to_writeBack_REGFILE_WRITE_DATA = CfuPlugin_bus_rsp_rsp_payload_outputs_0; end end - assign memory_SHIFT_CTRL = _zz_40; - assign execute_SHIFT_CTRL = _zz_41; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_42 = execute_PC; - assign execute_SRC2_CTRL = _zz_43; - assign execute_SRC1_CTRL = _zz_44; - assign decode_SRC_USE_SUB_LESS = _zz_203[0]; - assign decode_SRC_ADD_ZERO = _zz_204[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[18]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_45; - assign execute_SRC2 = _zz_103; - assign execute_SRC1 = _zz_98; - assign execute_ALU_BITWISE_CTRL = _zz_46; - assign _zz_47 = writeBack_INSTRUCTION; - assign _zz_48 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_49 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_49 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_205[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[8]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_244) == 32'h00000003),{(_zz_245 == _zz_246),{_zz_247,{_zz_248,_zz_249}}}}}}} != 22'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; - always @ (*) begin - _zz_58 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_58 = writeBack_DBusSimplePlugin_rspFormated; + always @(*) begin + _zz_lastStageRegFileWrite_payload_data = writeBack_REGFILE_WRITE_DATA; + if(when_DBusSimplePlugin_l558) begin + _zz_lastStageRegFileWrite_payload_data = writeBack_DBusSimplePlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_181) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_58 = _zz_232; + _zz_lastStageRegFileWrite_payload_data = _zz__zz_lastStageRegFileWrite_payload_data; end default : begin - _zz_58 = _zz_233; + _zz_lastStageRegFileWrite_payload_data = _zz__zz_lastStageRegFileWrite_payload_data_1; end endcase end @@ -2342,201 +2328,147 @@ module VexRiscv ( assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; - assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; - assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; - assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; - assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; - assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; - assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; - assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; - assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; - assign memory_PC = execute_to_memory_PC; - assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); - assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; - assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; - assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; - assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = 1'b0; - assign decode_MEMORY_ENABLE = _zz_206[0]; - assign decode_FLUSH_ALL = _zz_207[0]; - always @ (*) begin + assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_156)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_157)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_59 = execute_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_59 = BranchPlugin_jumpInterface_payload; - end - end - - always @ (*) begin - _zz_60 = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_60 = DBusSimplePlugin_redoBranch_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin - decode_arbitration_haltItself = 1'b0; - if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin - decode_arbitration_haltItself = 1'b1; - end - end - - always @ (*) begin + assign decode_arbitration_haltItself = 1'b0; + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_106 || _zz_107)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_75)))begin + if(when_DBusSimplePlugin_l426) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_155)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end - if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + if(when_CfuPlugin_l175) begin execute_arbitration_haltItself = 1'b1; end end assign execute_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin execute_arbitration_flushNext = 1'b1; end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + if(when_DBusSimplePlugin_l479) begin memory_arbitration_haltItself = 1'b1; end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if((! memory_CfuPlugin_rsp_valid))begin + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + if(when_CfuPlugin_l208) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_158)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin - memory_arbitration_removeIt = 1'b1; - end - end - - always @ (*) begin - memory_arbitration_flushIt = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; - end - end - - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(_zz_158)begin - memory_arbitration_flushNext = 1'b1; - end end + assign memory_arbitration_flushIt = 1'b0; + assign memory_arbitration_flushNext = 1'b0; assign writeBack_arbitration_haltItself = 1'b0; assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end assign writeBack_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_159)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_160)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2545,45 +2477,47 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_159)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_160)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; assign CsrPlugin_inWfi = 1'b0; assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_159)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_160)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_159)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_160)begin - case(_zz_161) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2596,58 +2530,61 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); - assign _zz_61 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_62 = (_zz_61 & (~ _zz_208)); - assign _zz_63 = _zz_62[1]; - assign _zz_64 = _zz_62[2]; - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_154; - always @ (*) begin + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid} != 2'b00); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}; + assign IBusCachedPlugin_jump_pcLoad_payload = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[0] ? CsrPlugin_jumpInterface_payload : BranchPlugin_jumpInterface_payload); + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_210); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -2655,58 +2592,67 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_65 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_65); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_65); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_66); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_66); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_2 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_67); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_68; - assign _zz_68 = ((1'b0 && (! _zz_69)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_69 = _zz_70; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_69; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_71 = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_71; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_73; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; @@ -2714,134 +2660,96 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_144 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_145 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_146 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_145; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_148 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_149 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_150 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_157)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_156)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_151 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_156)begin - _zz_151 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_2 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_143 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign _zz_75 = 1'b0; - always @ (*) begin + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_dBus_cmd_valid = 1'b0; + always @(*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; - if(execute_ALIGNEMENT_FAULT)begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin + if(execute_ALIGNEMENT_FAULT) begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_75)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_76 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_dBus_cmd_payload_data = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_76 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_dBus_cmd_payload_data = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_76 = execute_RS2[31 : 0]; + _zz_dBus_cmd_payload_data = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_76; - always @ (*) begin + assign dBus_cmd_payload_data = _zz_dBus_cmd_payload_data; + assign when_DBusSimplePlugin_l426 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_77 = 4'b0001; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0001; end 2'b01 : begin - _zz_77 = 4'b0011; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0011; end default : begin - _zz_77 = 4'b1111; + _zz_execute_DBusSimplePlugin_formalMask = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_77 <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; - assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end else begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - end - if(_zz_162)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end - end - - always @ (*) begin - DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(! memory_MMU_RSP2_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); - end - end - end - - assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; - always @ (*) begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_redoBranch_valid = 1'b1; - end - if(_zz_162)begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - end - end - - assign DBusSimplePlugin_redoBranch_payload = memory_PC; - always @ (*) begin + assign execute_DBusSimplePlugin_formalMask = (_zz_execute_DBusSimplePlugin_formalMask <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign when_DBusSimplePlugin_l479 = (((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)); + always @(*) begin writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin @@ -2858,63 +2766,64 @@ module VexRiscv ( endcase end - assign _zz_78 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_79[31] = _zz_78; - _zz_79[30] = _zz_78; - _zz_79[29] = _zz_78; - _zz_79[28] = _zz_78; - _zz_79[27] = _zz_78; - _zz_79[26] = _zz_78; - _zz_79[25] = _zz_78; - _zz_79[24] = _zz_78; - _zz_79[23] = _zz_78; - _zz_79[22] = _zz_78; - _zz_79[21] = _zz_78; - _zz_79[20] = _zz_78; - _zz_79[19] = _zz_78; - _zz_79[18] = _zz_78; - _zz_79[17] = _zz_78; - _zz_79[16] = _zz_78; - _zz_79[15] = _zz_78; - _zz_79[14] = _zz_78; - _zz_79[13] = _zz_78; - _zz_79[12] = _zz_78; - _zz_79[11] = _zz_78; - _zz_79[10] = _zz_78; - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_80 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_81[31] = _zz_80; - _zz_81[30] = _zz_80; - _zz_81[29] = _zz_80; - _zz_81[28] = _zz_80; - _zz_81[27] = _zz_80; - _zz_81[26] = _zz_80; - _zz_81[25] = _zz_80; - _zz_81[24] = _zz_80; - _zz_81[23] = _zz_80; - _zz_81[22] = _zz_80; - _zz_81[21] = _zz_80; - _zz_81[20] = _zz_80; - _zz_81[19] = _zz_80; - _zz_81[18] = _zz_80; - _zz_81[17] = _zz_80; - _zz_81[16] = _zz_80; - _zz_81[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_179) + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusSimplePlugin_rspFormated = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_1[31] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[30] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[29] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[28] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[27] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[26] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[25] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[24] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[23] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[22] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[21] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[20] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[19] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[18] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[17] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[16] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[15] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[14] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[13] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[12] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[11] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[10] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[9] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[8] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_writeBack_DBusSimplePlugin_rspFormated_2 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_3[31] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[30] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[29] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[28] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[27] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[26] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[25] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[24] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[23] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[22] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[21] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[20] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[19] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[18] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[17] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[16] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_79; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_81; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_3; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -2922,6 +2831,7 @@ module VexRiscv ( endcase end + assign when_DBusSimplePlugin_l558 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -2931,71 +2841,63 @@ module VexRiscv ( assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_83 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_84 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_85 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_86 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_87 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_82 = {(((decode_INSTRUCTION & 32'h02000074) == 32'h02000030) != 1'b0),{1'b0,{(_zz_87 != 1'b0),{(_zz_262 != 1'b0),{(_zz_263 != _zz_264),{_zz_265,{_zz_266,_zz_267}}}}}}}; - assign _zz_88 = _zz_82[2 : 1]; - assign _zz_57 = _zz_88; - assign _zz_89 = _zz_82[7 : 6]; - assign _zz_56 = _zz_89; - assign _zz_90 = _zz_82[14 : 13]; - assign _zz_55 = _zz_90; - assign _zz_91 = _zz_82[17 : 16]; - assign _zz_54 = _zz_91; - assign _zz_92 = _zz_82[20 : 19]; - assign _zz_53 = _zz_92; - assign _zz_93 = _zz_82[23 : 22]; - assign _zz_52 = _zz_93; - assign _zz_94 = _zz_82[26 : 25]; - assign _zz_51 = _zz_94; - assign _zz_95 = _zz_82[28 : 28]; - assign _zz_50 = _zz_95; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1) != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[14 : 13]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17 : 16]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20 : 19]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[23 : 22]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[26 : 25]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29 : 29]; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_152; - assign decode_RegFilePlugin_rs2Data = _zz_153; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_48 && writeBack_arbitration_isFiring); - if(_zz_96)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_47[11 : 7]; - if(_zz_96)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_58; - if(_zz_96)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_lastStageRegFileWrite_payload_data; + if(_zz_2) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3004,446 +2906,480 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_97 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_97 = {31'd0, _zz_211}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_97 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_98 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_98 = {29'd0, _zz_212}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_98 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_98 = {27'd0, _zz_213}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_99 = _zz_214[11]; - always @ (*) begin - _zz_100[19] = _zz_99; - _zz_100[18] = _zz_99; - _zz_100[17] = _zz_99; - _zz_100[16] = _zz_99; - _zz_100[15] = _zz_99; - _zz_100[14] = _zz_99; - _zz_100[13] = _zz_99; - _zz_100[12] = _zz_99; - _zz_100[11] = _zz_99; - _zz_100[10] = _zz_99; - _zz_100[9] = _zz_99; - _zz_100[8] = _zz_99; - _zz_100[7] = _zz_99; - _zz_100[6] = _zz_99; - _zz_100[5] = _zz_99; - _zz_100[4] = _zz_99; - _zz_100[3] = _zz_99; - _zz_100[2] = _zz_99; - _zz_100[1] = _zz_99; - _zz_100[0] = _zz_99; - end - - assign _zz_101 = _zz_215[11]; - always @ (*) begin - _zz_102[19] = _zz_101; - _zz_102[18] = _zz_101; - _zz_102[17] = _zz_101; - _zz_102[16] = _zz_101; - _zz_102[15] = _zz_101; - _zz_102[14] = _zz_101; - _zz_102[13] = _zz_101; - _zz_102[12] = _zz_101; - _zz_102[11] = _zz_101; - _zz_102[10] = _zz_101; - _zz_102[9] = _zz_101; - _zz_102[8] = _zz_101; - _zz_102[7] = _zz_101; - _zz_102[6] = _zz_101; - _zz_102[5] = _zz_101; - _zz_102[4] = _zz_101; - _zz_102[3] = _zz_101; - _zz_102[2] = _zz_101; - _zz_102[1] = _zz_101; - _zz_102[0] = _zz_101; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_103 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_103 = {_zz_100,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_103 = {_zz_102,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_103 = _zz_42; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_216; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_104[0] = execute_SRC1[31]; - _zz_104[1] = execute_SRC1[30]; - _zz_104[2] = execute_SRC1[29]; - _zz_104[3] = execute_SRC1[28]; - _zz_104[4] = execute_SRC1[27]; - _zz_104[5] = execute_SRC1[26]; - _zz_104[6] = execute_SRC1[25]; - _zz_104[7] = execute_SRC1[24]; - _zz_104[8] = execute_SRC1[23]; - _zz_104[9] = execute_SRC1[22]; - _zz_104[10] = execute_SRC1[21]; - _zz_104[11] = execute_SRC1[20]; - _zz_104[12] = execute_SRC1[19]; - _zz_104[13] = execute_SRC1[18]; - _zz_104[14] = execute_SRC1[17]; - _zz_104[15] = execute_SRC1[16]; - _zz_104[16] = execute_SRC1[15]; - _zz_104[17] = execute_SRC1[14]; - _zz_104[18] = execute_SRC1[13]; - _zz_104[19] = execute_SRC1[12]; - _zz_104[20] = execute_SRC1[11]; - _zz_104[21] = execute_SRC1[10]; - _zz_104[22] = execute_SRC1[9]; - _zz_104[23] = execute_SRC1[8]; - _zz_104[24] = execute_SRC1[7]; - _zz_104[25] = execute_SRC1[6]; - _zz_104[26] = execute_SRC1[5]; - _zz_104[27] = execute_SRC1[4]; - _zz_104[28] = execute_SRC1[3]; - _zz_104[29] = execute_SRC1[2]; - _zz_104[30] = execute_SRC1[1]; - _zz_104[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_104 : execute_SRC1); - always @ (*) begin - _zz_105[0] = memory_SHIFT_RIGHT[31]; - _zz_105[1] = memory_SHIFT_RIGHT[30]; - _zz_105[2] = memory_SHIFT_RIGHT[29]; - _zz_105[3] = memory_SHIFT_RIGHT[28]; - _zz_105[4] = memory_SHIFT_RIGHT[27]; - _zz_105[5] = memory_SHIFT_RIGHT[26]; - _zz_105[6] = memory_SHIFT_RIGHT[25]; - _zz_105[7] = memory_SHIFT_RIGHT[24]; - _zz_105[8] = memory_SHIFT_RIGHT[23]; - _zz_105[9] = memory_SHIFT_RIGHT[22]; - _zz_105[10] = memory_SHIFT_RIGHT[21]; - _zz_105[11] = memory_SHIFT_RIGHT[20]; - _zz_105[12] = memory_SHIFT_RIGHT[19]; - _zz_105[13] = memory_SHIFT_RIGHT[18]; - _zz_105[14] = memory_SHIFT_RIGHT[17]; - _zz_105[15] = memory_SHIFT_RIGHT[16]; - _zz_105[16] = memory_SHIFT_RIGHT[15]; - _zz_105[17] = memory_SHIFT_RIGHT[14]; - _zz_105[18] = memory_SHIFT_RIGHT[13]; - _zz_105[19] = memory_SHIFT_RIGHT[12]; - _zz_105[20] = memory_SHIFT_RIGHT[11]; - _zz_105[21] = memory_SHIFT_RIGHT[10]; - _zz_105[22] = memory_SHIFT_RIGHT[9]; - _zz_105[23] = memory_SHIFT_RIGHT[8]; - _zz_105[24] = memory_SHIFT_RIGHT[7]; - _zz_105[25] = memory_SHIFT_RIGHT[6]; - _zz_105[26] = memory_SHIFT_RIGHT[5]; - _zz_105[27] = memory_SHIFT_RIGHT[4]; - _zz_105[28] = memory_SHIFT_RIGHT[3]; - _zz_105[29] = memory_SHIFT_RIGHT[2]; - _zz_105[30] = memory_SHIFT_RIGHT[1]; - _zz_105[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_106 = 1'b0; - if(_zz_108)begin - if((_zz_109 == decode_INSTRUCTION[19 : 15]))begin - _zz_106 = 1'b1; - end - end - if(_zz_163)begin - if(_zz_164)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_106 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[0] = memory_SHIFT_RIGHT[31]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[1] = memory_SHIFT_RIGHT[30]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[2] = memory_SHIFT_RIGHT[29]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[3] = memory_SHIFT_RIGHT[28]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[4] = memory_SHIFT_RIGHT[27]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[5] = memory_SHIFT_RIGHT[26]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[6] = memory_SHIFT_RIGHT[25]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[7] = memory_SHIFT_RIGHT[24]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[8] = memory_SHIFT_RIGHT[23]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[9] = memory_SHIFT_RIGHT[22]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[10] = memory_SHIFT_RIGHT[21]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[11] = memory_SHIFT_RIGHT[20]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[12] = memory_SHIFT_RIGHT[19]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[13] = memory_SHIFT_RIGHT[18]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[14] = memory_SHIFT_RIGHT[17]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[15] = memory_SHIFT_RIGHT[16]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[16] = memory_SHIFT_RIGHT[15]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[17] = memory_SHIFT_RIGHT[14]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[18] = memory_SHIFT_RIGHT[13]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[19] = memory_SHIFT_RIGHT[12]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[20] = memory_SHIFT_RIGHT[11]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[21] = memory_SHIFT_RIGHT[10]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[22] = memory_SHIFT_RIGHT[9]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[23] = memory_SHIFT_RIGHT[8]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[24] = memory_SHIFT_RIGHT[7]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[25] = memory_SHIFT_RIGHT[6]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[26] = memory_SHIFT_RIGHT[5]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[27] = memory_SHIFT_RIGHT[4]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[28] = memory_SHIFT_RIGHT[3]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[29] = memory_SHIFT_RIGHT[2]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[30] = memory_SHIFT_RIGHT[1]; + _zz_memory_to_writeBack_REGFILE_WRITE_DATA_1[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l59) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_165)begin - if(_zz_166)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_106 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l59_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_167)begin - if(_zz_168)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_106 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l59_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_106 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_107 = 1'b0; - if(_zz_108)begin - if((_zz_109 == decode_INSTRUCTION[24 : 20]))begin - _zz_107 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end - if(_zz_163)begin - if(_zz_164)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_107 = 1'b1; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l62) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_165)begin - if(_zz_166)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_107 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l62_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_167)begin - if(_zz_168)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_107 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l62_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_107 = 1'b0; - end - end - + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_lastStageRegFileWrite_payload_data; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l59 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b1 || (! 1'b1)); + assign when_HazardSimplePlugin_l59_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l59_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_110 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_110 == 3'b000)) begin - _zz_111 = execute_BranchPlugin_eq; - end else if((_zz_110 == 3'b001)) begin - _zz_111 = (! execute_BranchPlugin_eq); - end else if((((_zz_110 & 3'b101) == 3'b101))) begin - _zz_111 = (! execute_SRC_LESS); - end else begin - _zz_111 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_DO = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_112 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_DO_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_112 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_DO_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_112 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_DO_1 = 1'b1; end default : begin - _zz_112 = _zz_111; + _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; end endcase end - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_113 = _zz_223[19]; - always @ (*) begin - _zz_114[10] = _zz_113; - _zz_114[9] = _zz_113; - _zz_114[8] = _zz_113; - _zz_114[7] = _zz_113; - _zz_114[6] = _zz_113; - _zz_114[5] = _zz_113; - _zz_114[4] = _zz_113; - _zz_114[3] = _zz_113; - _zz_114[2] = _zz_113; - _zz_114[1] = _zz_113; - _zz_114[0] = _zz_113; - end - - assign _zz_115 = _zz_224[11]; - always @ (*) begin - _zz_116[19] = _zz_115; - _zz_116[18] = _zz_115; - _zz_116[17] = _zz_115; - _zz_116[16] = _zz_115; - _zz_116[15] = _zz_115; - _zz_116[14] = _zz_115; - _zz_116[13] = _zz_115; - _zz_116[12] = _zz_115; - _zz_116[11] = _zz_115; - _zz_116[10] = _zz_115; - _zz_116[9] = _zz_115; - _zz_116[8] = _zz_115; - _zz_116[7] = _zz_115; - _zz_116[6] = _zz_115; - _zz_116[5] = _zz_115; - _zz_116[4] = _zz_115; - _zz_116[3] = _zz_115; - _zz_116[2] = _zz_115; - _zz_116[1] = _zz_115; - _zz_116[0] = _zz_115; - end - - assign _zz_117 = _zz_225[11]; - always @ (*) begin - _zz_118[18] = _zz_117; - _zz_118[17] = _zz_117; - _zz_118[16] = _zz_117; - _zz_118[15] = _zz_117; - _zz_118[14] = _zz_117; - _zz_118[13] = _zz_117; - _zz_118[12] = _zz_117; - _zz_118[11] = _zz_117; - _zz_118[10] = _zz_117; - _zz_118[9] = _zz_117; - _zz_118[8] = _zz_117; - _zz_118[7] = _zz_117; - _zz_118[6] = _zz_117; - _zz_118[5] = _zz_117; - _zz_118[4] = _zz_117; - _zz_118[3] = _zz_117; - _zz_118[2] = _zz_117; - _zz_118[1] = _zz_117; - _zz_118[0] = _zz_117; - end - - always @ (*) begin + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JALR) ? execute_RS1 : execute_PC); + assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_119 = {{_zz_114,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_119 = {_zz_116,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_119 = {{_zz_118,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_119; + assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_120 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_121 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_122 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_123 = {CfuPlugin_joinException_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_124 = _zz_226[0]; - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_158)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -3454,8 +3390,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3465,82 +3401,89 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_2816) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_2944) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_169)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_170)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_170)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3553,106 +3496,48 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_169)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_169)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_180) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); - assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_228; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; - assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_125 = _zz_229[7]; - always @ (*) begin - _zz_126[23] = _zz_125; - _zz_126[22] = _zz_125; - _zz_126[21] = _zz_125; - _zz_126[20] = _zz_125; - _zz_126[19] = _zz_125; - _zz_126[18] = _zz_125; - _zz_126[17] = _zz_125; - _zz_126[16] = _zz_125; - _zz_126[15] = _zz_125; - _zz_126[14] = _zz_125; - _zz_126[13] = _zz_125; - _zz_126[12] = _zz_125; - _zz_126[11] = _zz_125; - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : begin - _zz_127 = execute_RS2; - end - default : begin - _zz_127 = {_zz_126,execute_INSTRUCTION[31 : 24]}; - end - endcase - end - - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_127; - assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); - assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); - assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); - assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); - always @ (*) begin - CfuPlugin_joinException_valid = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if(memory_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); - end - end - end - - assign CfuPlugin_joinException_payload_code = 4'b1111; - assign CfuPlugin_joinException_payload_badAddr = 32'h0; - always @ (*) begin - memory_CfuPlugin_rsp_ready = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); - end - end - assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_171) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -3665,8 +3550,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_171) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -3685,39 +3570,158 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_230) + $signed(_zz_231)); - assign _zz_129 = (_zz_128 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_129 != 32'h0); - assign _zz_30 = decode_SRC1_CTRL; - assign _zz_28 = _zz_57; - assign _zz_44 = decode_to_execute_SRC1_CTRL; - assign _zz_27 = decode_SRC2_CTRL; - assign _zz_25 = _zz_56; - assign _zz_43 = decode_to_execute_SRC2_CTRL; - assign _zz_24 = decode_ALU_CTRL; - assign _zz_22 = _zz_55; - assign _zz_45 = decode_to_execute_ALU_CTRL; - assign _zz_21 = decode_ALU_BITWISE_CTRL; - assign _zz_19 = _zz_54; - assign _zz_46 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_18 = decode_SHIFT_CTRL; - assign _zz_15 = execute_SHIFT_CTRL; - assign _zz_16 = _zz_53; - assign _zz_41 = decode_to_execute_SHIFT_CTRL; - assign _zz_40 = execute_to_memory_SHIFT_CTRL; - assign _zz_13 = decode_BRANCH_CTRL; - assign _zz_11 = _zz_52; - assign _zz_38 = decode_to_execute_BRANCH_CTRL; - assign _zz_10 = decode_ENV_CTRL; - assign _zz_7 = execute_ENV_CTRL; - assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_51; - assign _zz_36 = decode_to_execute_ENV_CTRL; - assign _zz_35 = execute_to_memory_ENV_CTRL; - assign _zz_37 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_50; - assign _zz_33 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready); + assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)); + assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + end + + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2; + end + default : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @(*) begin + CfuPlugin_bus_rsp_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_16 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_32 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_33 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + assign when_Pipeline_l124_38 = (! execute_arbitration_isStuck); + assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -3738,138 +3742,160 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_130 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_130[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_130[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_130[3 : 3] = CsrPlugin_mstatus_MIE; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_131 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_131[11 : 11] = CsrPlugin_mip_MEIP; - _zz_131[7 : 7] = CsrPlugin_mip_MTIP; - _zz_131[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_132 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_132[11 : 11] = CsrPlugin_mie_MEIE; - _zz_132[7 : 7] = CsrPlugin_mie_MTIE; - _zz_132[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_133 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_133[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_134 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_134[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_134[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_135 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_135[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_136 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_136[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_137 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_137[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_138 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_138[31 : 0] = _zz_128; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_139 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_139[31 : 0] = _zz_129; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = ((((_zz_130 | _zz_131) | (_zz_132 | _zz_133)) | ((_zz_134 | _zz_135) | (_zz_136 | _zz_137))) | (_zz_138 | _zz_139)); - assign iBusWishbone_ADR = {_zz_240,_zz_140}; - assign iBusWishbone_CTI = ((_zz_140 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = ((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))) | (_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11)); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_172)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_172)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_141; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; - assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; - assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; - assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; - assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; - assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBus_cmd_halfPipe_fire = (dBus_cmd_halfPipe_valid && dBus_cmd_halfPipe_ready); + assign dBus_cmd_ready = (! dBus_cmd_rValid); + assign dBus_cmd_halfPipe_valid = dBus_cmd_rValid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_rData_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_rData_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_rData_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_rData_size; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); assign dBusWishbone_CTI = 3'b000; assign dBusWishbone_BTE = 2'b00; - always @ (*) begin + always @(*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_142 = 4'b0001; + _zz_dBusWishbone_SEL = 4'b0001; end 2'b01 : begin - _zz_142 = 4'b0011; + _zz_dBusWishbone_SEL = 4'b0011; end default : begin - _zz_142 = 4'b1111; + _zz_dBusWishbone_SEL = 4'b1111; end endcase end - always @ (*) begin - dBusWishbone_SEL = (_zz_142 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - if((! dBus_cmd_halfPipe_payload_wr))begin + always @(*) begin + dBusWishbone_SEL = (_zz_dBusWishbone_SEL <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + if(when_DBusSimplePlugin_l189) begin dBusWishbone_SEL = 4'b1111; end end + assign when_DBusSimplePlugin_l189 = (! dBus_cmd_halfPipe_payload_wr); assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); @@ -3878,23 +3904,23 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_70 <= 1'b0; - _zz_72 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_74; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; - _zz_96 <= 1'b1; - _zz_108 <= 1'b0; + _zz_2 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3911,93 +3937,92 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - _zz_128 <= 32'h0; + CfuPlugin_bus_rsp_rValid <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_140 <= 3'b000; - _zz_141 <= 1'b0; - dBus_cmd_halfPipe_regs_valid <= 1'b0; - dBus_cmd_halfPipe_regs_ready <= 1'b1; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + dBus_cmd_rValid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_70 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_68)begin - _zz_70 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_72 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end `ifndef SYNTHESIS @@ -4020,61 +4045,61 @@ module VexRiscv ( end `endif `endif - _zz_96 <= 1'b0; - _zz_108 <= (_zz_48 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_2 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_173)begin - if(_zz_174)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_175)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_176)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_159)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4085,8 +4110,8 @@ module VexRiscv ( end endcase end - if(_zz_160)begin - case(_zz_161) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4096,132 +4121,128 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_122,{_zz_121,_zz_120}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(execute_CfuPlugin_schedule)begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(execute_CfuPlugin_schedule) begin execute_CfuPlugin_hold <= 1'b1; end - if(CfuPlugin_bus_cmd_ready)begin + if(CfuPlugin_bus_cmd_ready) begin execute_CfuPlugin_hold <= 1'b0; end - if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + if(CfuPlugin_bus_cmd_fire) begin execute_CfuPlugin_fired <= 1'b1; end - if((! execute_arbitration_isStuckByOthers))begin + if(when_CfuPlugin_l171) begin execute_CfuPlugin_fired <= 1'b0; end - if(memory_CfuPlugin_rsp_ready)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + if(CfuPlugin_bus_rsp_valid) begin + CfuPlugin_bus_rsp_rValid <= 1'b1; end - if(_zz_177)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + if(CfuPlugin_bus_rsp_rsp_ready) begin + CfuPlugin_bus_rsp_rValid <= 1'b0; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_32; + if(when_Pipeline_l124_54) begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_234[0]; - CsrPlugin_mstatus_MIE <= _zz_235[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_237[0]; - CsrPlugin_mie_MTIE <= _zz_238[0]; - CsrPlugin_mie_MSIE <= _zz_239[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_128 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_172)begin - if(iBusWishbone_ACK)begin - _zz_140 <= (_zz_140 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_141 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_178)begin - dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; - dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); - end else begin - dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); - dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(dBus_cmd_valid) begin + dBus_cmd_rValid <= 1'b1; + end + if(dBus_cmd_halfPipe_fire) begin + dBus_cmd_rValid <= 1'b0; end end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_73 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - _zz_109 <= _zz_47[11 : 7]; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(decodeExceptionPort_valid)begin + if(decodeExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= decodeExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= decodeExceptionPort_payload_badAddr; end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_158)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_124 ? DBusSimplePlugin_memoryExceptionPort_payload_code : CfuPlugin_joinException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_124 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : CfuPlugin_joinException_payload_badAddr); - end - if(_zz_173)begin - if(_zz_174)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_175)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_176)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_159)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -4229,251 +4250,236 @@ module VexRiscv ( end endcase end - if(_zz_177)begin - CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; - end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(CfuPlugin_bus_rsp_ready) begin + CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_42; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_6) begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_60; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_29; + if(when_Pipeline_l124_9) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_10) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_26; + if(when_Pipeline_l124_14) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_15) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_16) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_23; + if(when_Pipeline_l124_24) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_20; + if(when_Pipeline_l124_26) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_17; + if(when_Pipeline_l124_27) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_14; + if(when_Pipeline_l124_28) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_12; + if(when_Pipeline_l124_29) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_30) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_31) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + if(when_Pipeline_l124_32) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + if(when_Pipeline_l124_33) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_34) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_35) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if(when_Pipeline_l124_38) begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + end + if(when_Pipeline_l124_39) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; - execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; - execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; - execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; - execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; - execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; - execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; - execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; - execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + if(when_Pipeline_l124_46) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_execute_to_memory_REGFILE_WRITE_DATA; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_34; + if(when_Pipeline_l124_47) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_memory_to_writeBack_REGFILE_WRITE_DATA; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_39; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_52) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_53) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + end + if(when_Pipeline_l124_56) begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_236[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_178)begin - dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; - dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; - dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; - dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + if(dBus_cmd_ready) begin + dBus_cmd_rData_wr <= dBus_cmd_payload_wr; + dBus_cmd_rData_address <= dBus_cmd_payload_address; + dBus_cmd_rData_data <= dBus_cmd_payload_data; + dBus_cmd_rData_size <= dBus_cmd_payload_size; end end @@ -4522,13 +4528,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [22:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [22:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [22:0] _zz_ways_0_tags_port1; + wire [22:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -4537,8 +4539,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [6:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -4552,22 +4559,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [8:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_6; - wire _zz_7; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8; + wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -4577,82 +4587,85 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_11 = (! lineLoader_flushCounter[6]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -4668,30 +4681,35 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -4699,51 +4717,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[6]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 7'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -4754,10 +4772,10 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v index 6d43c55..ca6283f 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v @@ -1,47 +1,47 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 - - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -74,37 +74,37 @@ module VexRiscv ( input clk, input reset ); - wire _zz_179; - wire _zz_180; - wire _zz_181; - wire _zz_182; - wire _zz_183; - wire _zz_184; - wire _zz_185; - wire _zz_186; - reg _zz_187; - wire _zz_188; - wire [31:0] _zz_189; - wire _zz_190; - wire [31:0] _zz_191; - reg _zz_192; - wire _zz_193; - wire _zz_194; - wire [31:0] _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - wire [3:0] _zz_204; - wire _zz_205; - wire _zz_206; - reg [31:0] _zz_207; - reg [31:0] _zz_208; - reg [31:0] _zz_209; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -127,6 +127,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -135,330 +136,274 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - wire _zz_219; - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire [1:0] _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - wire _zz_228; - wire _zz_229; - wire _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire [1:0] _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire [1:0] _zz_244; - wire _zz_245; - wire [1:0] _zz_246; - wire [51:0] _zz_247; - wire [51:0] _zz_248; - wire [51:0] _zz_249; - wire [32:0] _zz_250; - wire [51:0] _zz_251; - wire [49:0] _zz_252; - wire [51:0] _zz_253; - wire [49:0] _zz_254; - wire [51:0] _zz_255; - wire [32:0] _zz_256; - wire [31:0] _zz_257; - wire [32:0] _zz_258; - wire [0:0] _zz_259; - wire [0:0] _zz_260; - wire [0:0] _zz_261; - wire [0:0] _zz_262; - wire [0:0] _zz_263; - wire [0:0] _zz_264; - wire [0:0] _zz_265; - wire [0:0] _zz_266; - wire [0:0] _zz_267; - wire [0:0] _zz_268; - wire [0:0] _zz_269; - wire [0:0] _zz_270; - wire [0:0] _zz_271; - wire [0:0] _zz_272; - wire [0:0] _zz_273; - wire [0:0] _zz_274; - wire [0:0] _zz_275; - wire [3:0] _zz_276; - wire [2:0] _zz_277; - wire [31:0] _zz_278; - wire [11:0] _zz_279; - wire [31:0] _zz_280; - wire [19:0] _zz_281; - wire [11:0] _zz_282; - wire [31:0] _zz_283; - wire [31:0] _zz_284; - wire [19:0] _zz_285; - wire [11:0] _zz_286; - wire [2:0] _zz_287; - wire [2:0] _zz_288; - wire [0:0] _zz_289; - wire [2:0] _zz_290; - wire [4:0] _zz_291; - wire [11:0] _zz_292; - wire [11:0] _zz_293; - wire [31:0] _zz_294; - wire [31:0] _zz_295; - wire [31:0] _zz_296; - wire [31:0] _zz_297; - wire [31:0] _zz_298; - wire [31:0] _zz_299; - wire [31:0] _zz_300; - wire [11:0] _zz_301; - wire [19:0] _zz_302; - wire [11:0] _zz_303; - wire [31:0] _zz_304; - wire [31:0] _zz_305; - wire [31:0] _zz_306; - wire [11:0] _zz_307; - wire [19:0] _zz_308; - wire [11:0] _zz_309; - wire [2:0] _zz_310; - wire [1:0] _zz_311; - wire [1:0] _zz_312; - wire [65:0] _zz_313; - wire [65:0] _zz_314; - wire [31:0] _zz_315; - wire [31:0] _zz_316; - wire [0:0] _zz_317; - wire [5:0] _zz_318; - wire [32:0] _zz_319; - wire [31:0] _zz_320; - wire [31:0] _zz_321; - wire [32:0] _zz_322; - wire [32:0] _zz_323; - wire [32:0] _zz_324; - wire [32:0] _zz_325; - wire [0:0] _zz_326; - wire [32:0] _zz_327; - wire [0:0] _zz_328; - wire [32:0] _zz_329; - wire [0:0] _zz_330; - wire [31:0] _zz_331; - wire [0:0] _zz_332; - wire [0:0] _zz_333; - wire [0:0] _zz_334; - wire [0:0] _zz_335; - wire [0:0] _zz_336; - wire [0:0] _zz_337; - wire [0:0] _zz_338; - wire [26:0] _zz_339; - wire _zz_340; - wire _zz_341; - wire [1:0] _zz_342; - wire [31:0] _zz_343; - wire [31:0] _zz_344; - wire [31:0] _zz_345; - wire _zz_346; - wire [0:0] _zz_347; - wire [13:0] _zz_348; - wire [31:0] _zz_349; - wire [31:0] _zz_350; - wire [31:0] _zz_351; - wire _zz_352; - wire [0:0] _zz_353; - wire [7:0] _zz_354; - wire [31:0] _zz_355; - wire [31:0] _zz_356; - wire [31:0] _zz_357; - wire _zz_358; - wire [0:0] _zz_359; - wire [1:0] _zz_360; - wire _zz_361; - wire _zz_362; - wire _zz_363; - wire [31:0] _zz_364; - wire [31:0] _zz_365; - wire _zz_366; - wire [0:0] _zz_367; - wire [0:0] _zz_368; - wire _zz_369; - wire [0:0] _zz_370; - wire [24:0] _zz_371; - wire [31:0] _zz_372; - wire _zz_373; - wire _zz_374; - wire [0:0] _zz_375; - wire [0:0] _zz_376; - wire [0:0] _zz_377; - wire [0:0] _zz_378; - wire _zz_379; - wire [0:0] _zz_380; - wire [20:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire _zz_384; - wire _zz_385; - wire [0:0] _zz_386; - wire [1:0] _zz_387; - wire [0:0] _zz_388; - wire [0:0] _zz_389; - wire _zz_390; - wire [0:0] _zz_391; - wire [17:0] _zz_392; - wire [31:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire [31:0] _zz_399; - wire [31:0] _zz_400; - wire _zz_401; - wire [1:0] _zz_402; - wire [1:0] _zz_403; - wire _zz_404; - wire [0:0] _zz_405; - wire [14:0] _zz_406; - wire [31:0] _zz_407; - wire [31:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire [31:0] _zz_411; - wire [31:0] _zz_412; - wire [0:0] _zz_413; - wire [0:0] _zz_414; - wire [4:0] _zz_415; - wire [4:0] _zz_416; - wire _zz_417; - wire [0:0] _zz_418; - wire [11:0] _zz_419; - wire [31:0] _zz_420; - wire [31:0] _zz_421; - wire [31:0] _zz_422; - wire [31:0] _zz_423; - wire _zz_424; - wire [0:0] _zz_425; - wire [1:0] _zz_426; - wire [31:0] _zz_427; - wire [31:0] _zz_428; - wire [0:0] _zz_429; - wire [3:0] _zz_430; - wire [4:0] _zz_431; - wire [4:0] _zz_432; - wire _zz_433; - wire [0:0] _zz_434; - wire [8:0] _zz_435; - wire [31:0] _zz_436; - wire [31:0] _zz_437; - wire [31:0] _zz_438; - wire _zz_439; - wire _zz_440; - wire [31:0] _zz_441; - wire [31:0] _zz_442; - wire [0:0] _zz_443; - wire [1:0] _zz_444; - wire [0:0] _zz_445; - wire [2:0] _zz_446; - wire [0:0] _zz_447; - wire [4:0] _zz_448; - wire [1:0] _zz_449; - wire [1:0] _zz_450; - wire _zz_451; - wire [0:0] _zz_452; - wire [6:0] _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [31:0] _zz_456; - wire [31:0] _zz_457; - wire _zz_458; - wire _zz_459; - wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire _zz_462; - wire [0:0] _zz_463; - wire [0:0] _zz_464; - wire _zz_465; - wire [0:0] _zz_466; - wire [2:0] _zz_467; - wire _zz_468; - wire [0:0] _zz_469; - wire [0:0] _zz_470; - wire [0:0] _zz_471; - wire [0:0] _zz_472; - wire _zz_473; - wire [0:0] _zz_474; - wire [4:0] _zz_475; - wire [31:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; - wire [31:0] _zz_479; - wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire [31:0] _zz_485; - wire _zz_486; - wire [0:0] _zz_487; - wire [0:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; - wire [31:0] _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire _zz_494; - wire [3:0] _zz_495; - wire [3:0] _zz_496; - wire _zz_497; - wire [0:0] _zz_498; - wire [2:0] _zz_499; - wire [31:0] _zz_500; - wire [31:0] _zz_501; - wire [31:0] _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire [31:0] _zz_505; - wire _zz_506; - wire [0:0] _zz_507; - wire [1:0] _zz_508; - wire _zz_509; - wire [2:0] _zz_510; - wire [2:0] _zz_511; - wire _zz_512; - wire [0:0] _zz_513; - wire [0:0] _zz_514; - wire [31:0] _zz_515; - wire [31:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire [31:0] _zz_520; - wire [31:0] _zz_521; - wire _zz_522; - wire _zz_523; - wire _zz_524; - wire [0:0] _zz_525; - wire [0:0] _zz_526; - wire _zz_527; - wire _zz_528; - wire _zz_529; - wire _zz_530; - wire [31:0] _zz_531; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_1; + wire _zz__zz_decode_IS_RS2_SIGNED_2; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_3; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_4; + wire _zz__zz_decode_IS_RS2_SIGNED_5; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_6; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_7; + wire _zz__zz_decode_IS_RS2_SIGNED_8; + wire _zz__zz_decode_IS_RS2_SIGNED_9; + wire [24:0] _zz__zz_decode_IS_RS2_SIGNED_10; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_11; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_12; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_13; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_14; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_15; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_16; + wire _zz__zz_decode_IS_RS2_SIGNED_17; + wire _zz__zz_decode_IS_RS2_SIGNED_18; + wire _zz__zz_decode_IS_RS2_SIGNED_19; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_20; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_21; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_22; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_23; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_24; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_25; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_26; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_27; + wire [20:0] _zz__zz_decode_IS_RS2_SIGNED_28; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_29; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_30; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_31; + wire _zz__zz_decode_IS_RS2_SIGNED_32; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_33; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_34; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_35; + wire _zz__zz_decode_IS_RS2_SIGNED_36; + wire [17:0] _zz__zz_decode_IS_RS2_SIGNED_37; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_38; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_39; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_40; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_41; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_42; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_43; + wire _zz__zz_decode_IS_RS2_SIGNED_44; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_45; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_46; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_47; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_48; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_49; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_50; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_51; + wire [14:0] _zz__zz_decode_IS_RS2_SIGNED_52; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_53; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_54; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_55; + wire _zz__zz_decode_IS_RS2_SIGNED_56; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_57; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_58; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_59; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_60; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_61; + wire _zz__zz_decode_IS_RS2_SIGNED_62; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_63; + wire _zz__zz_decode_IS_RS2_SIGNED_64; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_65; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_66; + wire _zz__zz_decode_IS_RS2_SIGNED_67; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_68; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_69; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_70; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_71; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_72; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_73; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_74; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_75; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_76; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_77; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_78; + wire _zz__zz_decode_IS_RS2_SIGNED_79; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_80; + wire _zz__zz_decode_IS_RS2_SIGNED_81; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_82; + wire [11:0] _zz__zz_decode_IS_RS2_SIGNED_83; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_84; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_85; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_86; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_87; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_88; + wire _zz__zz_decode_IS_RS2_SIGNED_89; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_90; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_91; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_92; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_93; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_94; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_95; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_96; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_97; + wire _zz__zz_decode_IS_RS2_SIGNED_98; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_99; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_100; + wire _zz__zz_decode_IS_RS2_SIGNED_101; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_102; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_103; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_104; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_105; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_106; + wire _zz__zz_decode_IS_RS2_SIGNED_107; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_108; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_109; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_110; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_111; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_112; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_113; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_114; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_115; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_116; + wire _zz__zz_decode_IS_RS2_SIGNED_117; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_118; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_119; + wire [8:0] _zz__zz_decode_IS_RS2_SIGNED_120; + wire _zz__zz_decode_IS_RS2_SIGNED_121; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_122; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_123; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_124; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_125; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_126; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_127; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_128; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_129; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_130; + wire [6:0] _zz__zz_decode_IS_RS2_SIGNED_131; + wire _zz__zz_decode_IS_RS2_SIGNED_132; + wire _zz__zz_decode_IS_RS2_SIGNED_133; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_134; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_135; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_136; + wire _zz__zz_decode_IS_RS2_SIGNED_137; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_138; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_139; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_140; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_141; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_142; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_143; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_144; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_145; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_146; + wire _zz__zz_decode_IS_RS2_SIGNED_147; + wire _zz__zz_decode_IS_RS2_SIGNED_148; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_149; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_150; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_151; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_152; + wire _zz__zz_decode_IS_RS2_SIGNED_153; + wire _zz__zz_decode_IS_RS2_SIGNED_154; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_155; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_156; + wire _zz__zz_decode_IS_RS2_SIGNED_157; + wire _zz__zz_decode_IS_RS2_SIGNED_158; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_159; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_160; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_161; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_162; + wire _zz__zz_decode_IS_RS2_SIGNED_163; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -469,8 +414,8 @@ module VexRiscv ( wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; @@ -481,27 +426,27 @@ module VexRiscv ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -509,18 +454,18 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; @@ -540,23 +485,23 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_31; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -566,45 +511,45 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_32; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_35; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_36; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; - wire [31:0] _zz_40; - wire _zz_41; - reg _zz_42; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_43; - wire `BranchCtrlEnum_defaultEncoding_type _zz_44; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; - wire `Src2CtrlEnum_defaultEncoding_type _zz_47; - wire `AluCtrlEnum_defaultEncoding_type _zz_48; - wire `Src1CtrlEnum_defaultEncoding_type _zz_49; - reg [31:0] _zz_50; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -622,11 +567,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_52; - reg [31:0] _zz_53; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -713,7 +658,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -747,6 +692,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -764,28 +714,34 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_54; - wire [3:0] _zz_55; - wire _zz_56; - wire _zz_57; - wire _zz_58; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -808,16 +764,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_59; - wire _zz_60; - wire _zz_61; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_62; - wire _zz_63; - reg _zz_64; - wire _zz_65; - reg _zz_66; - reg [31:0] _zz_67; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -825,22 +783,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_68; - reg [18:0] _zz_69; - wire _zz_70; - reg [10:0] _zz_71; - wire _zz_72; - reg [18:0] _zz_73; - reg _zz_74; - wire _zz_75; - reg [10:0] _zz_76; - wire _zz_77; - reg [18:0] _zz_78; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -848,7 +813,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_79; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -856,23 +821,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -880,38 +850,54 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_80; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_81; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_82; - reg [31:0] _zz_83; - wire _zz_84; - reg [31:0] _zz_85; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [31:0] _zz_86; - wire _zz_87; - wire _zz_88; - wire _zz_89; - wire _zz_90; - wire `Src1CtrlEnum_defaultEncoding_type _zz_91; - wire `AluCtrlEnum_defaultEncoding_type _zz_92; - wire `Src2CtrlEnum_defaultEncoding_type _zz_93; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_94; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_95; - wire `BranchCtrlEnum_defaultEncoding_type _zz_96; - wire `EnvCtrlEnum_defaultEncoding_type _zz_97; + wire when_DBusCachedPlugin_l484; + wire [31:0] _zz_decode_IS_RS2_SIGNED; + wire _zz_decode_IS_RS2_SIGNED_1; + wire _zz_decode_IS_RS2_SIGNED_2; + wire _zz_decode_IS_RS2_SIGNED_3; + wire _zz_decode_IS_RS2_SIGNED_4; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -919,52 +905,70 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_98; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_99; - reg [31:0] _zz_100; - wire _zz_101; - reg [19:0] _zz_102; - wire _zz_103; - reg [19:0] _zz_104; - reg [31:0] _zz_105; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_106; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_107; - reg _zz_108; - reg _zz_109; - reg _zz_110; - reg [4:0] _zz_111; - reg [31:0] _zz_112; - wire _zz_113; - wire _zz_114; - wire _zz_115; - wire _zz_116; - wire _zz_117; - wire _zz_118; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_119; - reg _zz_120; - reg _zz_121; - wire _zz_122; - reg [19:0] _zz_123; - wire _zz_124; - reg [10:0] _zz_125; - wire _zz_126; - reg [18:0] _zz_127; - reg _zz_128; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_129; - reg [19:0] _zz_130; - wire _zz_131; - reg [10:0] _zz_132; - wire _zz_133; - reg [18:0] _zz_134; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -986,9 +990,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_135; - wire _zz_136; - wire _zz_137; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1001,40 +1005,67 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_138; - wire _zz_139; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1042,6 +1073,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1054,208 +1087,310 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_140; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_141; - wire _zz_142; - wire _zz_143; - reg [32:0] _zz_144; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_145; - wire [31:0] _zz_146; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_44; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_45; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_46; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_47; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_48; reg decode_to_execute_CSR_READ_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_49; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_50; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_51; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_52; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_53; reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_54; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_55; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_57; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_60; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_61; reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_147; - reg [31:0] _zz_148; - reg [31:0] _zz_149; - reg [31:0] _zz_150; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [2:0] _zz_170; - reg _zz_171; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_172; - wire _zz_173; - wire _zz_174; - wire _zz_175; - wire _zz_176; - wire _zz_177; - reg _zz_178; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; - reg [39:0] _zz_17_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; - reg [23:0] _zz_20_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; - reg [63:0] _zz_23_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; - reg [95:0] _zz_26_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_30_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_33_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_34_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_36_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_37_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_38_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_39_string; - reg [39:0] _zz_43_string; - reg [31:0] _zz_44_string; - reg [71:0] _zz_45_string; - reg [39:0] _zz_46_string; - reg [23:0] _zz_47_string; - reg [63:0] _zz_48_string; - reg [95:0] _zz_49_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_51_string; - reg [95:0] _zz_91_string; - reg [63:0] _zz_92_string; - reg [23:0] _zz_93_string; - reg [39:0] _zz_94_string; - reg [71:0] _zz_95_string; - reg [31:0] _zz_96_string; - reg [39:0] _zz_97_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1270,1154 +1405,1122 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_210 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_211 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_212 = 1'b1; - assign _zz_213 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_214 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_215 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_216 = ((_zz_184 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_217 = ((_zz_184 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_218 = ((_zz_184 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_219 = ((_zz_184 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_220 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_221 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_222 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_223 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_224 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_225 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_226 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_227 = (1'b0 || (! 1'b1)); - assign _zz_228 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_229 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_230 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_231 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_232 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_233 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_234 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_235 = execute_INSTRUCTION[13 : 12]; - assign _zz_236 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_237 = (! memory_arbitration_isStuck); - assign _zz_238 = (iBus_cmd_valid || (_zz_170 != 3'b000)); - assign _zz_239 = (_zz_206 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_240 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_241 = ((_zz_135 && 1'b1) && (! 1'b0)); - assign _zz_242 = ((_zz_136 && 1'b1) && (! 1'b0)); - assign _zz_243 = ((_zz_137 && 1'b1) && (! 1'b0)); - assign _zz_244 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_245 = execute_INSTRUCTION[13]; - assign _zz_246 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_247 = ($signed(_zz_248) + $signed(_zz_253)); - assign _zz_248 = ($signed(_zz_249) + $signed(_zz_251)); - assign _zz_249 = 52'h0; - assign _zz_250 = {1'b0,memory_MUL_LL}; - assign _zz_251 = {{19{_zz_250[32]}}, _zz_250}; - assign _zz_252 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_253 = {{2{_zz_252[49]}}, _zz_252}; - assign _zz_254 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_255 = {{2{_zz_254[49]}}, _zz_254}; - assign _zz_256 = ($signed(_zz_258) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_257 = _zz_256[31 : 0]; - assign _zz_258 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_259 = _zz_86[31 : 31]; - assign _zz_260 = _zz_86[30 : 30]; - assign _zz_261 = _zz_86[29 : 29]; - assign _zz_262 = _zz_86[28 : 28]; - assign _zz_263 = _zz_86[25 : 25]; - assign _zz_264 = _zz_86[17 : 17]; - assign _zz_265 = _zz_86[16 : 16]; - assign _zz_266 = _zz_86[13 : 13]; - assign _zz_267 = _zz_86[12 : 12]; - assign _zz_268 = _zz_86[11 : 11]; - assign _zz_269 = _zz_86[15 : 15]; - assign _zz_270 = _zz_86[5 : 5]; - assign _zz_271 = _zz_86[3 : 3]; - assign _zz_272 = _zz_86[20 : 20]; - assign _zz_273 = _zz_86[10 : 10]; - assign _zz_274 = _zz_86[4 : 4]; - assign _zz_275 = _zz_86[0 : 0]; - assign _zz_276 = (_zz_54 - 4'b0001); - assign _zz_277 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_278 = {29'd0, _zz_277}; - assign _zz_279 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_280 = {{_zz_69,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_281 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_282 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_283 = {{_zz_71,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_284 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_285 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_286 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_287 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_288 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_289 = execute_SRC_LESS; - assign _zz_290 = 3'b100; - assign _zz_291 = execute_INSTRUCTION[19 : 15]; - assign _zz_292 = execute_INSTRUCTION[31 : 20]; - assign _zz_293 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_294 = ($signed(_zz_295) + $signed(_zz_298)); - assign _zz_295 = ($signed(_zz_296) + $signed(_zz_297)); - assign _zz_296 = execute_SRC1; - assign _zz_297 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_298 = (execute_SRC_USE_SUB_LESS ? _zz_299 : _zz_300); - assign _zz_299 = 32'h00000001; - assign _zz_300 = 32'h0; - assign _zz_301 = execute_INSTRUCTION[31 : 20]; - assign _zz_302 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_303 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_304 = {_zz_123,execute_INSTRUCTION[31 : 20]}; - assign _zz_305 = {{_zz_125,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_306 = {{_zz_127,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_307 = execute_INSTRUCTION[31 : 20]; - assign _zz_308 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_309 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_310 = 3'b100; - assign _zz_311 = (_zz_138 & (~ _zz_312)); - assign _zz_312 = (_zz_138 - 2'b01); - assign _zz_313 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_314 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_315 = writeBack_MUL_LOW[31 : 0]; - assign _zz_316 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_317 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_318 = {5'd0, _zz_317}; - assign _zz_319 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_320 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_321 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_322 = {_zz_140,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_323 = _zz_324; - assign _zz_324 = _zz_325; - assign _zz_325 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_141) : _zz_141)} + _zz_327); - assign _zz_326 = memory_DivPlugin_div_needRevert; - assign _zz_327 = {32'd0, _zz_326}; - assign _zz_328 = _zz_143; - assign _zz_329 = {32'd0, _zz_328}; - assign _zz_330 = _zz_142; - assign _zz_331 = {31'd0, _zz_330}; - assign _zz_332 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_333 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_334 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_335 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_336 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_337 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_338 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_339 = (iBus_cmd_payload_address >>> 5); - assign _zz_340 = 1'b1; - assign _zz_341 = 1'b1; - assign _zz_342 = {_zz_58,_zz_57}; - assign _zz_343 = 32'h0000107f; - assign _zz_344 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_345 = 32'h00002073; - assign _zz_346 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_347 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_348 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_349) == 32'h00000003),{(_zz_350 == _zz_351),{_zz_352,{_zz_353,_zz_354}}}}}}; - assign _zz_349 = 32'h0000505f; - assign _zz_350 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_351 = 32'h00000063; - assign _zz_352 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_353 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_354 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_355) == 32'h00001013),{(_zz_356 == _zz_357),{_zz_358,{_zz_359,_zz_360}}}}}}; - assign _zz_355 = 32'hfc00307f; - assign _zz_356 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_357 = 32'h00005033; - assign _zz_358 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_359 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_360 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; - assign _zz_361 = decode_INSTRUCTION[31]; - assign _zz_362 = decode_INSTRUCTION[31]; - assign _zz_363 = decode_INSTRUCTION[7]; - assign _zz_364 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_365 = 32'h02004020; - assign _zz_366 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_367 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); - assign _zz_368 = 1'b0; - assign _zz_369 = (((decode_INSTRUCTION & _zz_372) == 32'h00000050) != 1'b0); - assign _zz_370 = ({_zz_373,_zz_374} != 2'b00); - assign _zz_371 = {({_zz_375,_zz_376} != 2'b00),{(_zz_377 != _zz_378),{_zz_379,{_zz_380,_zz_381}}}}; - assign _zz_372 = 32'h00403050; - assign _zz_373 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_374 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_375 = _zz_89; - assign _zz_376 = ((decode_INSTRUCTION & _zz_382) == 32'h00000004); - assign _zz_377 = ((decode_INSTRUCTION & _zz_383) == 32'h00000040); - assign _zz_378 = 1'b0; - assign _zz_379 = ({_zz_384,_zz_385} != 2'b00); - assign _zz_380 = ({_zz_386,_zz_387} != 3'b000); - assign _zz_381 = {(_zz_388 != _zz_389),{_zz_390,{_zz_391,_zz_392}}}; - assign _zz_382 = 32'h0000001c; - assign _zz_383 = 32'h00000058; - assign _zz_384 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_385 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_386 = ((decode_INSTRUCTION & _zz_393) == 32'h40001010); - assign _zz_387 = {(_zz_394 == _zz_395),(_zz_396 == _zz_397)}; - assign _zz_388 = ((decode_INSTRUCTION & _zz_398) == 32'h00000024); - assign _zz_389 = 1'b0; - assign _zz_390 = ((_zz_399 == _zz_400) != 1'b0); - assign _zz_391 = (_zz_401 != 1'b0); - assign _zz_392 = {(_zz_402 != _zz_403),{_zz_404,{_zz_405,_zz_406}}}; - assign _zz_393 = 32'h40003054; - assign _zz_394 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_395 = 32'h00001010; - assign _zz_396 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_397 = 32'h00001010; - assign _zz_398 = 32'h00000064; - assign _zz_399 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_400 = 32'h00001000; - assign _zz_401 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_402 = {(_zz_407 == _zz_408),(_zz_409 == _zz_410)}; - assign _zz_403 = 2'b00; - assign _zz_404 = ((_zz_411 == _zz_412) != 1'b0); - assign _zz_405 = ({_zz_413,_zz_414} != 2'b00); - assign _zz_406 = {(_zz_415 != _zz_416),{_zz_417,{_zz_418,_zz_419}}}; - assign _zz_407 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_408 = 32'h00002000; - assign _zz_409 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_410 = 32'h00001000; - assign _zz_411 = (decode_INSTRUCTION & 32'h00004048); - assign _zz_412 = 32'h00004008; - assign _zz_413 = ((decode_INSTRUCTION & _zz_420) == 32'h00000020); - assign _zz_414 = ((decode_INSTRUCTION & _zz_421) == 32'h00000020); - assign _zz_415 = {(_zz_422 == _zz_423),{_zz_424,{_zz_425,_zz_426}}}; - assign _zz_416 = 5'h0; - assign _zz_417 = ((_zz_427 == _zz_428) != 1'b0); - assign _zz_418 = ({_zz_429,_zz_430} != 5'h0); - assign _zz_419 = {(_zz_431 != _zz_432),{_zz_433,{_zz_434,_zz_435}}}; - assign _zz_420 = 32'h00000034; - assign _zz_421 = 32'h00000064; - assign _zz_422 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_423 = 32'h00002040; - assign _zz_424 = ((decode_INSTRUCTION & _zz_436) == 32'h00001040); - assign _zz_425 = (_zz_437 == _zz_438); - assign _zz_426 = {_zz_439,_zz_440}; - assign _zz_427 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_428 = 32'h00000020; - assign _zz_429 = (_zz_441 == _zz_442); - assign _zz_430 = {_zz_88,{_zz_443,_zz_444}}; - assign _zz_431 = {_zz_88,{_zz_445,_zz_446}}; - assign _zz_432 = 5'h0; - assign _zz_433 = ({_zz_447,_zz_448} != 6'h0); - assign _zz_434 = (_zz_449 != _zz_450); - assign _zz_435 = {_zz_451,{_zz_452,_zz_453}}; - assign _zz_436 = 32'h00001040; - assign _zz_437 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_438 = 32'h00000040; - assign _zz_439 = ((decode_INSTRUCTION & _zz_454) == 32'h00000040); - assign _zz_440 = ((decode_INSTRUCTION & _zz_455) == 32'h0); - assign _zz_441 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_442 = 32'h00000040; - assign _zz_443 = (_zz_456 == _zz_457); - assign _zz_444 = {_zz_458,_zz_459}; - assign _zz_445 = (_zz_460 == _zz_461); - assign _zz_446 = {_zz_462,{_zz_463,_zz_464}}; - assign _zz_447 = _zz_89; - assign _zz_448 = {_zz_465,{_zz_466,_zz_467}}; - assign _zz_449 = {_zz_88,_zz_468}; - assign _zz_450 = 2'b00; - assign _zz_451 = ({_zz_469,_zz_470} != 2'b00); - assign _zz_452 = (_zz_471 != _zz_472); - assign _zz_453 = {_zz_473,{_zz_474,_zz_475}}; - assign _zz_454 = 32'h00400040; - assign _zz_455 = 32'h00000038; - assign _zz_456 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_457 = 32'h00004020; - assign _zz_458 = ((decode_INSTRUCTION & _zz_476) == 32'h00000010); - assign _zz_459 = ((decode_INSTRUCTION & _zz_477) == 32'h00000020); - assign _zz_460 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_461 = 32'h00002010; - assign _zz_462 = ((decode_INSTRUCTION & _zz_478) == 32'h00000010); - assign _zz_463 = (_zz_479 == _zz_480); - assign _zz_464 = (_zz_481 == _zz_482); - assign _zz_465 = ((decode_INSTRUCTION & _zz_483) == 32'h00001010); - assign _zz_466 = (_zz_484 == _zz_485); - assign _zz_467 = {_zz_486,{_zz_487,_zz_488}}; - assign _zz_468 = ((decode_INSTRUCTION & _zz_489) == 32'h00000020); - assign _zz_469 = _zz_88; - assign _zz_470 = (_zz_490 == _zz_491); - assign _zz_471 = (_zz_492 == _zz_493); - assign _zz_472 = 1'b0; - assign _zz_473 = (_zz_494 != 1'b0); - assign _zz_474 = (_zz_495 != _zz_496); - assign _zz_475 = {_zz_497,{_zz_498,_zz_499}}; - assign _zz_476 = 32'h00000030; - assign _zz_477 = 32'h02000020; - assign _zz_478 = 32'h00001030; - assign _zz_479 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_480 = 32'h00002020; - assign _zz_481 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_482 = 32'h00000020; - assign _zz_483 = 32'h00001010; - assign _zz_484 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_485 = 32'h00002010; - assign _zz_486 = ((decode_INSTRUCTION & _zz_500) == 32'h00000010); - assign _zz_487 = (_zz_501 == _zz_502); - assign _zz_488 = (_zz_503 == _zz_504); - assign _zz_489 = 32'h00000070; - assign _zz_490 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_491 = 32'h0; - assign _zz_492 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_493 = 32'h00004010; - assign _zz_494 = ((decode_INSTRUCTION & _zz_505) == 32'h00002010); - assign _zz_495 = {_zz_506,{_zz_507,_zz_508}}; - assign _zz_496 = 4'b0000; - assign _zz_497 = (_zz_509 != 1'b0); - assign _zz_498 = (_zz_510 != _zz_511); - assign _zz_499 = {_zz_512,{_zz_513,_zz_514}}; - assign _zz_500 = 32'h00000050; - assign _zz_501 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_502 = 32'h00000004; - assign _zz_503 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_504 = 32'h0; - assign _zz_505 = 32'h00006014; - assign _zz_506 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_507 = ((decode_INSTRUCTION & _zz_515) == 32'h0); - assign _zz_508 = {(_zz_516 == _zz_517),(_zz_518 == _zz_519)}; - assign _zz_509 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_510 = {(_zz_520 == _zz_521),{_zz_522,_zz_523}}; - assign _zz_511 = 3'b000; - assign _zz_512 = ({_zz_524,_zz_87} != 2'b00); - assign _zz_513 = ({_zz_525,_zz_526} != 2'b00); - assign _zz_514 = (_zz_527 != 1'b0); - assign _zz_515 = 32'h00000018; - assign _zz_516 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_517 = 32'h00002000; - assign _zz_518 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_519 = 32'h00001000; - assign _zz_520 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_521 = 32'h00000040; - assign _zz_522 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_523 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_524 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_525 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_526 = _zz_87; - assign _zz_527 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); - assign _zz_528 = execute_INSTRUCTION[31]; - assign _zz_529 = execute_INSTRUCTION[31]; - assign _zz_530 = execute_INSTRUCTION[7]; - assign _zz_531 = 32'h0; - always @ (posedge clk) begin - if(_zz_340) begin - _zz_207 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_341) begin - _zz_208 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_42) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_IS_RS2_SIGNED = (decode_INSTRUCTION & 32'h02004064); + assign _zz__zz_decode_IS_RS2_SIGNED_1 = 32'h02004020; + assign _zz__zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz__zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_4 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_5 = (((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_6) == 32'h00000050) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_7 = ({_zz__zz_decode_IS_RS2_SIGNED_8,_zz__zz_decode_IS_RS2_SIGNED_9} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_10 = {({_zz__zz_decode_IS_RS2_SIGNED_11,_zz__zz_decode_IS_RS2_SIGNED_12} != 2'b00),{(_zz__zz_decode_IS_RS2_SIGNED_14 != _zz__zz_decode_IS_RS2_SIGNED_16),{_zz__zz_decode_IS_RS2_SIGNED_17,{_zz__zz_decode_IS_RS2_SIGNED_20,_zz__zz_decode_IS_RS2_SIGNED_28}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_6 = 32'h00403050; + assign _zz__zz_decode_IS_RS2_SIGNED_8 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz__zz_decode_IS_RS2_SIGNED_9 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz__zz_decode_IS_RS2_SIGNED_11 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_12 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_13) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_14 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_15) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_16 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_17 = ({_zz__zz_decode_IS_RS2_SIGNED_18,_zz__zz_decode_IS_RS2_SIGNED_19} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_20 = ({_zz__zz_decode_IS_RS2_SIGNED_21,_zz__zz_decode_IS_RS2_SIGNED_23} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_28 = {(_zz__zz_decode_IS_RS2_SIGNED_29 != _zz__zz_decode_IS_RS2_SIGNED_31),{_zz__zz_decode_IS_RS2_SIGNED_32,{_zz__zz_decode_IS_RS2_SIGNED_35,_zz__zz_decode_IS_RS2_SIGNED_37}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_13 = 32'h0000001c; + assign _zz__zz_decode_IS_RS2_SIGNED_15 = 32'h00000058; + assign _zz__zz_decode_IS_RS2_SIGNED_18 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz__zz_decode_IS_RS2_SIGNED_19 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz__zz_decode_IS_RS2_SIGNED_21 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_22) == 32'h40001010); + assign _zz__zz_decode_IS_RS2_SIGNED_23 = {(_zz__zz_decode_IS_RS2_SIGNED_24 == _zz__zz_decode_IS_RS2_SIGNED_25),(_zz__zz_decode_IS_RS2_SIGNED_26 == _zz__zz_decode_IS_RS2_SIGNED_27)}; + assign _zz__zz_decode_IS_RS2_SIGNED_29 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_30) == 32'h00000024); + assign _zz__zz_decode_IS_RS2_SIGNED_31 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_32 = ((_zz__zz_decode_IS_RS2_SIGNED_33 == _zz__zz_decode_IS_RS2_SIGNED_34) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_35 = (_zz__zz_decode_IS_RS2_SIGNED_36 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_37 = {(_zz__zz_decode_IS_RS2_SIGNED_38 != _zz__zz_decode_IS_RS2_SIGNED_43),{_zz__zz_decode_IS_RS2_SIGNED_44,{_zz__zz_decode_IS_RS2_SIGNED_47,_zz__zz_decode_IS_RS2_SIGNED_52}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_22 = 32'h40003054; + assign _zz__zz_decode_IS_RS2_SIGNED_24 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_RS2_SIGNED_25 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_26 = (decode_INSTRUCTION & 32'h02007054); + assign _zz__zz_decode_IS_RS2_SIGNED_27 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_30 = 32'h00000064; + assign _zz__zz_decode_IS_RS2_SIGNED_33 = (decode_INSTRUCTION & 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_34 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_36 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_38 = {(_zz__zz_decode_IS_RS2_SIGNED_39 == _zz__zz_decode_IS_RS2_SIGNED_40),(_zz__zz_decode_IS_RS2_SIGNED_41 == _zz__zz_decode_IS_RS2_SIGNED_42)}; + assign _zz__zz_decode_IS_RS2_SIGNED_43 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_44 = ((_zz__zz_decode_IS_RS2_SIGNED_45 == _zz__zz_decode_IS_RS2_SIGNED_46) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_47 = ({_zz__zz_decode_IS_RS2_SIGNED_48,_zz__zz_decode_IS_RS2_SIGNED_50} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_52 = {(_zz__zz_decode_IS_RS2_SIGNED_53 != _zz__zz_decode_IS_RS2_SIGNED_66),{_zz__zz_decode_IS_RS2_SIGNED_67,{_zz__zz_decode_IS_RS2_SIGNED_70,_zz__zz_decode_IS_RS2_SIGNED_83}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_39 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_40 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_41 = (decode_INSTRUCTION & 32'h00005000); + assign _zz__zz_decode_IS_RS2_SIGNED_42 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_45 = (decode_INSTRUCTION & 32'h00004048); + assign _zz__zz_decode_IS_RS2_SIGNED_46 = 32'h00004008; + assign _zz__zz_decode_IS_RS2_SIGNED_48 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_49) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_50 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_51) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_53 = {(_zz__zz_decode_IS_RS2_SIGNED_54 == _zz__zz_decode_IS_RS2_SIGNED_55),{_zz__zz_decode_IS_RS2_SIGNED_56,{_zz__zz_decode_IS_RS2_SIGNED_58,_zz__zz_decode_IS_RS2_SIGNED_61}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_66 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_67 = ((_zz__zz_decode_IS_RS2_SIGNED_68 == _zz__zz_decode_IS_RS2_SIGNED_69) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_70 = ({_zz__zz_decode_IS_RS2_SIGNED_71,_zz__zz_decode_IS_RS2_SIGNED_74} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_83 = {(_zz__zz_decode_IS_RS2_SIGNED_84 != _zz__zz_decode_IS_RS2_SIGNED_97),{_zz__zz_decode_IS_RS2_SIGNED_98,{_zz__zz_decode_IS_RS2_SIGNED_115,_zz__zz_decode_IS_RS2_SIGNED_120}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_49 = 32'h00000034; + assign _zz__zz_decode_IS_RS2_SIGNED_51 = 32'h00000064; + assign _zz__zz_decode_IS_RS2_SIGNED_54 = (decode_INSTRUCTION & 32'h00002040); + assign _zz__zz_decode_IS_RS2_SIGNED_55 = 32'h00002040; + assign _zz__zz_decode_IS_RS2_SIGNED_56 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_57) == 32'h00001040); + assign _zz__zz_decode_IS_RS2_SIGNED_58 = (_zz__zz_decode_IS_RS2_SIGNED_59 == _zz__zz_decode_IS_RS2_SIGNED_60); + assign _zz__zz_decode_IS_RS2_SIGNED_61 = {_zz__zz_decode_IS_RS2_SIGNED_62,_zz__zz_decode_IS_RS2_SIGNED_64}; + assign _zz__zz_decode_IS_RS2_SIGNED_68 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_69 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_71 = (_zz__zz_decode_IS_RS2_SIGNED_72 == _zz__zz_decode_IS_RS2_SIGNED_73); + assign _zz__zz_decode_IS_RS2_SIGNED_74 = {_zz_decode_IS_RS2_SIGNED_2,{_zz__zz_decode_IS_RS2_SIGNED_75,_zz__zz_decode_IS_RS2_SIGNED_78}}; + assign _zz__zz_decode_IS_RS2_SIGNED_84 = {_zz_decode_IS_RS2_SIGNED_2,{_zz__zz_decode_IS_RS2_SIGNED_85,_zz__zz_decode_IS_RS2_SIGNED_88}}; + assign _zz__zz_decode_IS_RS2_SIGNED_97 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_98 = ({_zz__zz_decode_IS_RS2_SIGNED_99,_zz__zz_decode_IS_RS2_SIGNED_100} != 6'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_115 = (_zz__zz_decode_IS_RS2_SIGNED_116 != _zz__zz_decode_IS_RS2_SIGNED_119); + assign _zz__zz_decode_IS_RS2_SIGNED_120 = {_zz__zz_decode_IS_RS2_SIGNED_121,{_zz__zz_decode_IS_RS2_SIGNED_126,_zz__zz_decode_IS_RS2_SIGNED_131}}; + assign _zz__zz_decode_IS_RS2_SIGNED_57 = 32'h00001040; + assign _zz__zz_decode_IS_RS2_SIGNED_59 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_60 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_62 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_63) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_64 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_65) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_72 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_73 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_75 = (_zz__zz_decode_IS_RS2_SIGNED_76 == _zz__zz_decode_IS_RS2_SIGNED_77); + assign _zz__zz_decode_IS_RS2_SIGNED_78 = {_zz__zz_decode_IS_RS2_SIGNED_79,_zz__zz_decode_IS_RS2_SIGNED_81}; + assign _zz__zz_decode_IS_RS2_SIGNED_85 = (_zz__zz_decode_IS_RS2_SIGNED_86 == _zz__zz_decode_IS_RS2_SIGNED_87); + assign _zz__zz_decode_IS_RS2_SIGNED_88 = {_zz__zz_decode_IS_RS2_SIGNED_89,{_zz__zz_decode_IS_RS2_SIGNED_91,_zz__zz_decode_IS_RS2_SIGNED_94}}; + assign _zz__zz_decode_IS_RS2_SIGNED_99 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_100 = {_zz__zz_decode_IS_RS2_SIGNED_101,{_zz__zz_decode_IS_RS2_SIGNED_103,_zz__zz_decode_IS_RS2_SIGNED_106}}; + assign _zz__zz_decode_IS_RS2_SIGNED_116 = {_zz_decode_IS_RS2_SIGNED_2,_zz__zz_decode_IS_RS2_SIGNED_117}; + assign _zz__zz_decode_IS_RS2_SIGNED_119 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_121 = ({_zz__zz_decode_IS_RS2_SIGNED_122,_zz__zz_decode_IS_RS2_SIGNED_123} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_126 = (_zz__zz_decode_IS_RS2_SIGNED_127 != _zz__zz_decode_IS_RS2_SIGNED_130); + assign _zz__zz_decode_IS_RS2_SIGNED_131 = {_zz__zz_decode_IS_RS2_SIGNED_132,{_zz__zz_decode_IS_RS2_SIGNED_135,_zz__zz_decode_IS_RS2_SIGNED_146}}; + assign _zz__zz_decode_IS_RS2_SIGNED_63 = 32'h00400040; + assign _zz__zz_decode_IS_RS2_SIGNED_65 = 32'h00000038; + assign _zz__zz_decode_IS_RS2_SIGNED_76 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_IS_RS2_SIGNED_77 = 32'h00004020; + assign _zz__zz_decode_IS_RS2_SIGNED_79 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_80) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_81 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_82) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_86 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_IS_RS2_SIGNED_87 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_89 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_90) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_91 = (_zz__zz_decode_IS_RS2_SIGNED_92 == _zz__zz_decode_IS_RS2_SIGNED_93); + assign _zz__zz_decode_IS_RS2_SIGNED_94 = (_zz__zz_decode_IS_RS2_SIGNED_95 == _zz__zz_decode_IS_RS2_SIGNED_96); + assign _zz__zz_decode_IS_RS2_SIGNED_101 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_102) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_103 = (_zz__zz_decode_IS_RS2_SIGNED_104 == _zz__zz_decode_IS_RS2_SIGNED_105); + assign _zz__zz_decode_IS_RS2_SIGNED_106 = {_zz__zz_decode_IS_RS2_SIGNED_107,{_zz__zz_decode_IS_RS2_SIGNED_109,_zz__zz_decode_IS_RS2_SIGNED_112}}; + assign _zz__zz_decode_IS_RS2_SIGNED_117 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_118) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_122 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_123 = (_zz__zz_decode_IS_RS2_SIGNED_124 == _zz__zz_decode_IS_RS2_SIGNED_125); + assign _zz__zz_decode_IS_RS2_SIGNED_127 = (_zz__zz_decode_IS_RS2_SIGNED_128 == _zz__zz_decode_IS_RS2_SIGNED_129); + assign _zz__zz_decode_IS_RS2_SIGNED_130 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_132 = (_zz__zz_decode_IS_RS2_SIGNED_133 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_135 = (_zz__zz_decode_IS_RS2_SIGNED_136 != _zz__zz_decode_IS_RS2_SIGNED_145); + assign _zz__zz_decode_IS_RS2_SIGNED_146 = {_zz__zz_decode_IS_RS2_SIGNED_147,{_zz__zz_decode_IS_RS2_SIGNED_149,_zz__zz_decode_IS_RS2_SIGNED_156}}; + assign _zz__zz_decode_IS_RS2_SIGNED_80 = 32'h00000030; + assign _zz__zz_decode_IS_RS2_SIGNED_82 = 32'h02000020; + assign _zz__zz_decode_IS_RS2_SIGNED_90 = 32'h00001030; + assign _zz__zz_decode_IS_RS2_SIGNED_92 = (decode_INSTRUCTION & 32'h02002060); + assign _zz__zz_decode_IS_RS2_SIGNED_93 = 32'h00002020; + assign _zz__zz_decode_IS_RS2_SIGNED_95 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_IS_RS2_SIGNED_96 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_102 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_104 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_105 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_107 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_108) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_109 = (_zz__zz_decode_IS_RS2_SIGNED_110 == _zz__zz_decode_IS_RS2_SIGNED_111); + assign _zz__zz_decode_IS_RS2_SIGNED_112 = (_zz__zz_decode_IS_RS2_SIGNED_113 == _zz__zz_decode_IS_RS2_SIGNED_114); + assign _zz__zz_decode_IS_RS2_SIGNED_118 = 32'h00000070; + assign _zz__zz_decode_IS_RS2_SIGNED_124 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_125 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_128 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_IS_RS2_SIGNED_129 = 32'h00004010; + assign _zz__zz_decode_IS_RS2_SIGNED_133 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_134) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_136 = {_zz__zz_decode_IS_RS2_SIGNED_137,{_zz__zz_decode_IS_RS2_SIGNED_138,_zz__zz_decode_IS_RS2_SIGNED_140}}; + assign _zz__zz_decode_IS_RS2_SIGNED_145 = 4'b0000; + assign _zz__zz_decode_IS_RS2_SIGNED_147 = (_zz__zz_decode_IS_RS2_SIGNED_148 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_149 = (_zz__zz_decode_IS_RS2_SIGNED_150 != _zz__zz_decode_IS_RS2_SIGNED_155); + assign _zz__zz_decode_IS_RS2_SIGNED_156 = {_zz__zz_decode_IS_RS2_SIGNED_157,{_zz__zz_decode_IS_RS2_SIGNED_159,_zz__zz_decode_IS_RS2_SIGNED_162}}; + assign _zz__zz_decode_IS_RS2_SIGNED_108 = 32'h00000050; + assign _zz__zz_decode_IS_RS2_SIGNED_110 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz__zz_decode_IS_RS2_SIGNED_111 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_113 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_RS2_SIGNED_114 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_134 = 32'h00006014; + assign _zz__zz_decode_IS_RS2_SIGNED_137 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_138 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_139) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_140 = {(_zz__zz_decode_IS_RS2_SIGNED_141 == _zz__zz_decode_IS_RS2_SIGNED_142),(_zz__zz_decode_IS_RS2_SIGNED_143 == _zz__zz_decode_IS_RS2_SIGNED_144)}; + assign _zz__zz_decode_IS_RS2_SIGNED_148 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_150 = {(_zz__zz_decode_IS_RS2_SIGNED_151 == _zz__zz_decode_IS_RS2_SIGNED_152),{_zz__zz_decode_IS_RS2_SIGNED_153,_zz__zz_decode_IS_RS2_SIGNED_154}}; + assign _zz__zz_decode_IS_RS2_SIGNED_155 = 3'b000; + assign _zz__zz_decode_IS_RS2_SIGNED_157 = ({_zz__zz_decode_IS_RS2_SIGNED_158,_zz_decode_IS_RS2_SIGNED_1} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_159 = ({_zz__zz_decode_IS_RS2_SIGNED_160,_zz__zz_decode_IS_RS2_SIGNED_161} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_162 = (_zz__zz_decode_IS_RS2_SIGNED_163 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_139 = 32'h00000018; + assign _zz__zz_decode_IS_RS2_SIGNED_141 = (decode_INSTRUCTION & 32'h00006004); + assign _zz__zz_decode_IS_RS2_SIGNED_142 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_143 = (decode_INSTRUCTION & 32'h00005004); + assign _zz__zz_decode_IS_RS2_SIGNED_144 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_151 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_RS2_SIGNED_152 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_153 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_154 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz__zz_decode_IS_RS2_SIGNED_158 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_160 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_161 = _zz_decode_IS_RS2_SIGNED_1; + assign _zz__zz_decode_IS_RS2_SIGNED_163 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_179 ), //i - .io_cpu_prefetch_isValid (_zz_180 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_181 ), //i - .io_cpu_fetch_isStuck (_zz_182 ), //i - .io_cpu_fetch_isRemoved (_zz_183 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_184 ), //i - .io_cpu_decode_isStuck (_zz_185 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_186 ), //i - .io_cpu_fill_valid (_zz_187 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_188 ), //i - .io_cpu_execute_address (_zz_189[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_81[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_190 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_191[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_192 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_193 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_194 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_195[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_196 ), //i - .io_cpu_writeBack_fence_SR (_zz_197 ), //i - .io_cpu_writeBack_fence_SO (_zz_198 ), //i - .io_cpu_writeBack_fence_SI (_zz_199 ), //i - .io_cpu_writeBack_fence_PW (_zz_200 ), //i - .io_cpu_writeBack_fence_PR (_zz_201 ), //i - .io_cpu_writeBack_fence_PO (_zz_202 ), //i - .io_cpu_writeBack_fence_PI (_zz_203 ), //i - .io_cpu_writeBack_fence_FM (_zz_204[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_205 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_206 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_342) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) 2'b00 : begin - _zz_209 = DBusCachedPlugin_redoBranch_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_209 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_209 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_209 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + end + 2'b01 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + end + 2'b10 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_30) - `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; - default : _zz_30_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_33) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; - default : _zz_33_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_34) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; - default : _zz_34_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_36) - `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; - default : _zz_36_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_37) - `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; - default : _zz_37_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_38) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; - default : _zz_38_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_39) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; - default : _zz_39_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_43) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; - default : _zz_43_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; - default : _zz_44_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_45) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; - default : _zz_45_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_46) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; - default : _zz_46_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_47) - `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; - default : _zz_47_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_48) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; - default : _zz_48_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_49) - `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; - default : _zz_49_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_91) - `Src1CtrlEnum_defaultEncoding_RS : _zz_91_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_91_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_91_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_91_string = "URS1 "; - default : _zz_91_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_92) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_92_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_92_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_92_string = "BITWISE "; - default : _zz_92_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_93) - `Src2CtrlEnum_defaultEncoding_RS : _zz_93_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_93_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_93_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_93_string = "PC "; - default : _zz_93_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_94) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_94_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_94_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_94_string = "AND_1"; - default : _zz_94_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_95) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_95_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_95_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_95_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_95_string = "SRA_1 "; - default : _zz_95_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_96) - `BranchCtrlEnum_defaultEncoding_INC : _zz_96_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_96_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_96_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_96_string = "JALR"; - default : _zz_96_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_97) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_97_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_97_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_97_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_97_string = "ECALL"; - default : _zz_97_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_247) + $signed(_zz_255)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2425,44 +2528,44 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_257; - assign execute_REGFILE_WRITE_DATA = _zz_99; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_189[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_259[0]; - assign decode_IS_RS1_SIGNED = _zz_260[0]; - assign decode_IS_DIV = _zz_261[0]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_RS2_SIGNED[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_RS2_SIGNED[30]; + assign decode_IS_DIV = _zz_decode_IS_RS2_SIGNED[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_262[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_263[0]; - assign _zz_8 = _zz_9; - assign _zz_10 = _zz_11; - assign decode_SHIFT_CTRL = _zz_12; - assign _zz_13 = _zz_14; - assign decode_ALU_BITWISE_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_264[0]; - assign decode_MEMORY_MANAGMENT = _zz_265[0]; + assign decode_IS_MUL = _zz_decode_IS_RS2_SIGNED[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_RS2_SIGNED[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_RS2_SIGNED[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_RS2_SIGNED[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_266[0]; + assign decode_MEMORY_WR = _zz_decode_IS_RS2_SIGNED[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_267[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_268[0]; - assign decode_SRC2_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_ALU_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_SRC1_CTRL = _zz_24; - assign _zz_25 = _zz_26; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_RS2_SIGNED[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_RS2_SIGNED[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; @@ -2482,22 +2585,22 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27; - assign execute_ENV_CTRL = _zz_28; - assign writeBack_ENV_CTRL = _zz_29; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_121; - assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_269[0]; - assign decode_RS1_USE = _zz_270[0]; - always @ (*) begin - _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_210)begin - _zz_31 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_RS2_SIGNED[15]; + assign decode_RS1_USE = _zz_decode_IS_RS2_SIGNED[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2507,139 +2610,139 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_110)begin - if((_zz_111 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_112; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_211)begin - if(_zz_212)begin - if(_zz_114)begin - decode_RS2 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_213)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_116)begin - decode_RS2 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_214)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_118)begin - decode_RS2 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_110)begin - if((_zz_111 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_112; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_211)begin - if(_zz_212)begin - if(_zz_113)begin - decode_RS1 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_213)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_115)begin - decode_RS1 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_214)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_117)begin - decode_RS1 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_32 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_32 = _zz_107; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_32 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_215)begin - _zz_32 = memory_DivPlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_33; - assign execute_SHIFT_CTRL = _zz_34; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_35 = execute_PC; - assign execute_SRC2_CTRL = _zz_36; - assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_271[0]; - assign decode_SRC_ADD_ZERO = _zz_272[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_RS2_SIGNED[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_RS2_SIGNED[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_38; - assign execute_SRC2 = _zz_105; - assign execute_SRC1 = _zz_100; - assign execute_ALU_BITWISE_CTRL = _zz_39; - assign _zz_40 = writeBack_INSTRUCTION; - assign _zz_41 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_42 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_42 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_273[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_RS2_SIGNED[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_343) == 32'h00001073),{(_zz_344 == _zz_345),{_zz_346,{_zz_347,_zz_348}}}}}}} != 21'h0); - always @ (*) begin - _zz_50 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_50 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 21'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_246) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_50 = _zz_315; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_50 = _zz_316; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2651,206 +2754,206 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_274[0]; - assign decode_FLUSH_ALL = _zz_275[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_IS_RS2_SIGNED[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_RS2_SIGNED[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_216)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_217)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_218)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_219)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_51; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_52 = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_52 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_53 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_108 || _zz_109)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_220)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_220)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_205 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_221)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_210)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_215)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_222)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_223)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2859,51 +2962,53 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_222)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_223)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_221)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_222)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_223)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_222)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_223)begin - case(_zz_224) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2916,59 +3021,65 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_54 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_55 = (_zz_54 & (~ _zz_276)); - assign _zz_56 = _zz_55[3]; - assign _zz_57 = (_zz_55[1] || _zz_56); - assign _zz_58 = (_zz_55[2] || _zz_56); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_209; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_278); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -2976,265 +3087,286 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_59 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_59); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_59); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_60); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_60); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_61); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_61); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_62; - assign _zz_62 = ((1'b0 && (! _zz_63)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_63 = _zz_64; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_63; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_65)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_65 = _zz_66; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_65; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_67; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_68 = _zz_279[11]; - always @ (*) begin - _zz_69[18] = _zz_68; - _zz_69[17] = _zz_68; - _zz_69[16] = _zz_68; - _zz_69[15] = _zz_68; - _zz_69[14] = _zz_68; - _zz_69[13] = _zz_68; - _zz_69[12] = _zz_68; - _zz_69[11] = _zz_68; - _zz_69[10] = _zz_68; - _zz_69[9] = _zz_68; - _zz_69[8] = _zz_68; - _zz_69[7] = _zz_68; - _zz_69[6] = _zz_68; - _zz_69[5] = _zz_68; - _zz_69[4] = _zz_68; - _zz_69[3] = _zz_68; - _zz_69[2] = _zz_68; - _zz_69[1] = _zz_68; - _zz_69[0] = _zz_68; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_280[31])); - if(_zz_74)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_70 = _zz_281[19]; - always @ (*) begin - _zz_71[10] = _zz_70; - _zz_71[9] = _zz_70; - _zz_71[8] = _zz_70; - _zz_71[7] = _zz_70; - _zz_71[6] = _zz_70; - _zz_71[5] = _zz_70; - _zz_71[4] = _zz_70; - _zz_71[3] = _zz_70; - _zz_71[2] = _zz_70; - _zz_71[1] = _zz_70; - _zz_71[0] = _zz_70; - end - - assign _zz_72 = _zz_282[11]; - always @ (*) begin - _zz_73[18] = _zz_72; - _zz_73[17] = _zz_72; - _zz_73[16] = _zz_72; - _zz_73[15] = _zz_72; - _zz_73[14] = _zz_72; - _zz_73[13] = _zz_72; - _zz_73[12] = _zz_72; - _zz_73[11] = _zz_72; - _zz_73[10] = _zz_72; - _zz_73[9] = _zz_72; - _zz_73[8] = _zz_72; - _zz_73[7] = _zz_72; - _zz_73[6] = _zz_72; - _zz_73[5] = _zz_72; - _zz_73[4] = _zz_72; - _zz_73[3] = _zz_72; - _zz_73[2] = _zz_72; - _zz_73[1] = _zz_72; - _zz_73[0] = _zz_72; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_74 = _zz_283[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_74 = _zz_284[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_75 = _zz_285[19]; - always @ (*) begin - _zz_76[10] = _zz_75; - _zz_76[9] = _zz_75; - _zz_76[8] = _zz_75; - _zz_76[7] = _zz_75; - _zz_76[6] = _zz_75; - _zz_76[5] = _zz_75; - _zz_76[4] = _zz_75; - _zz_76[3] = _zz_75; - _zz_76[2] = _zz_75; - _zz_76[1] = _zz_75; - _zz_76[0] = _zz_75; - end - - assign _zz_77 = _zz_286[11]; - always @ (*) begin - _zz_78[18] = _zz_77; - _zz_78[17] = _zz_77; - _zz_78[16] = _zz_77; - _zz_78[15] = _zz_77; - _zz_78[14] = _zz_77; - _zz_78[13] = _zz_77; - _zz_78[12] = _zz_77; - _zz_78[11] = _zz_77; - _zz_78[10] = _zz_77; - _zz_78[9] = _zz_77; - _zz_78[8] = _zz_77; - _zz_78[7] = _zz_77; - _zz_78[6] = _zz_77; - _zz_78[5] = _zz_77; - _zz_78[4] = _zz_77; - _zz_78[3] = _zz_77; - _zz_78[2] = _zz_77; - _zz_78[1] = _zz_77; - _zz_78[0] = _zz_77; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_76,{{{_zz_361,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_78,{{{_zz_362,_zz_363},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_180 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_181 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_182 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_181; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_184 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_185 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_186 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_219)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_217)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_187 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_217)begin - _zz_187 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_218)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_216)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_218)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_216)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_179 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_206 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3242,168 +3374,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_188 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_189 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_81 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_81 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_81 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_205 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_190 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_191 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_190; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_191; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_192 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_192 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; end end - assign _zz_193 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_194 = (CsrPlugin_privilege == 2'b00); - assign _zz_195 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_225)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_225)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_225)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_287}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_288}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; end - assign _zz_82 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_83[31] = _zz_82; - _zz_83[30] = _zz_82; - _zz_83[29] = _zz_82; - _zz_83[28] = _zz_82; - _zz_83[27] = _zz_82; - _zz_83[26] = _zz_82; - _zz_83[25] = _zz_82; - _zz_83[24] = _zz_82; - _zz_83[23] = _zz_82; - _zz_83[22] = _zz_82; - _zz_83[21] = _zz_82; - _zz_83[20] = _zz_82; - _zz_83[19] = _zz_82; - _zz_83[18] = _zz_82; - _zz_83[17] = _zz_82; - _zz_83[16] = _zz_82; - _zz_83[15] = _zz_82; - _zz_83[14] = _zz_82; - _zz_83[13] = _zz_82; - _zz_83[12] = _zz_82; - _zz_83[11] = _zz_82; - _zz_83[10] = _zz_82; - _zz_83[9] = _zz_82; - _zz_83[8] = _zz_82; - _zz_83[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_84 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_85[31] = _zz_84; - _zz_85[30] = _zz_84; - _zz_85[29] = _zz_84; - _zz_85[28] = _zz_84; - _zz_85[27] = _zz_84; - _zz_85[26] = _zz_84; - _zz_85[25] = _zz_84; - _zz_85[24] = _zz_84; - _zz_85[23] = _zz_84; - _zz_85[22] = _zz_84; - _zz_85[21] = _zz_84; - _zz_85[20] = _zz_84; - _zz_85[19] = _zz_84; - _zz_85[18] = _zz_84; - _zz_85[17] = _zz_84; - _zz_85[16] = _zz_84; - _zz_85[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_244) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_83; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_85; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3422,59 +3565,60 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_87 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_88 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_89 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_90 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_86 = {(_zz_90 != 1'b0),{(_zz_90 != 1'b0),{((_zz_364 == _zz_365) != 1'b0),{(_zz_366 != 1'b0),{(_zz_367 != _zz_368),{_zz_369,{_zz_370,_zz_371}}}}}}}; - assign _zz_91 = _zz_86[2 : 1]; - assign _zz_49 = _zz_91; - assign _zz_92 = _zz_86[7 : 6]; - assign _zz_48 = _zz_92; - assign _zz_93 = _zz_86[9 : 8]; - assign _zz_47 = _zz_93; - assign _zz_94 = _zz_86[19 : 18]; - assign _zz_46 = _zz_94; - assign _zz_95 = _zz_86[22 : 21]; - assign _zz_45 = _zz_95; - assign _zz_96 = _zz_86[24 : 23]; - assign _zz_44 = _zz_96; - assign _zz_97 = _zz_86[27 : 26]; - assign _zz_43 = _zz_97; + assign _zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_RS2_SIGNED_4 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_IS_RS2_SIGNED = {(_zz_decode_IS_RS2_SIGNED_4 != 1'b0),{(_zz_decode_IS_RS2_SIGNED_4 != 1'b0),{((_zz__zz_decode_IS_RS2_SIGNED == _zz__zz_decode_IS_RS2_SIGNED_1) != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_2 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_3 != _zz__zz_decode_IS_RS2_SIGNED_4),{_zz__zz_decode_IS_RS2_SIGNED_5,{_zz__zz_decode_IS_RS2_SIGNED_7,_zz__zz_decode_IS_RS2_SIGNED_10}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_RS2_SIGNED[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_RS2_SIGNED[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_RS2_SIGNED[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_RS2_SIGNED[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_RS2_SIGNED[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_RS2_SIGNED[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_RS2_SIGNED[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_207; - assign decode_RegFilePlugin_rs2Data = _zz_208; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); - if(_zz_98)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; - if(_zz_98)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_50; - if(_zz_98)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3483,355 +3627,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_99 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_99 = {31'd0, _zz_289}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_99 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_100 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_100 = {29'd0, _zz_290}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_100 = {27'd0, _zz_291}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_101 = _zz_292[11]; - always @ (*) begin - _zz_102[19] = _zz_101; - _zz_102[18] = _zz_101; - _zz_102[17] = _zz_101; - _zz_102[16] = _zz_101; - _zz_102[15] = _zz_101; - _zz_102[14] = _zz_101; - _zz_102[13] = _zz_101; - _zz_102[12] = _zz_101; - _zz_102[11] = _zz_101; - _zz_102[10] = _zz_101; - _zz_102[9] = _zz_101; - _zz_102[8] = _zz_101; - _zz_102[7] = _zz_101; - _zz_102[6] = _zz_101; - _zz_102[5] = _zz_101; - _zz_102[4] = _zz_101; - _zz_102[3] = _zz_101; - _zz_102[2] = _zz_101; - _zz_102[1] = _zz_101; - _zz_102[0] = _zz_101; - end - - assign _zz_103 = _zz_293[11]; - always @ (*) begin - _zz_104[19] = _zz_103; - _zz_104[18] = _zz_103; - _zz_104[17] = _zz_103; - _zz_104[16] = _zz_103; - _zz_104[15] = _zz_103; - _zz_104[14] = _zz_103; - _zz_104[13] = _zz_103; - _zz_104[12] = _zz_103; - _zz_104[11] = _zz_103; - _zz_104[10] = _zz_103; - _zz_104[9] = _zz_103; - _zz_104[8] = _zz_103; - _zz_104[7] = _zz_103; - _zz_104[6] = _zz_103; - _zz_104[5] = _zz_103; - _zz_104[4] = _zz_103; - _zz_104[3] = _zz_103; - _zz_104[2] = _zz_103; - _zz_104[1] = _zz_103; - _zz_104[0] = _zz_103; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_105 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_105 = {_zz_104,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_105 = _zz_35; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_294; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_106[0] = execute_SRC1[31]; - _zz_106[1] = execute_SRC1[30]; - _zz_106[2] = execute_SRC1[29]; - _zz_106[3] = execute_SRC1[28]; - _zz_106[4] = execute_SRC1[27]; - _zz_106[5] = execute_SRC1[26]; - _zz_106[6] = execute_SRC1[25]; - _zz_106[7] = execute_SRC1[24]; - _zz_106[8] = execute_SRC1[23]; - _zz_106[9] = execute_SRC1[22]; - _zz_106[10] = execute_SRC1[21]; - _zz_106[11] = execute_SRC1[20]; - _zz_106[12] = execute_SRC1[19]; - _zz_106[13] = execute_SRC1[18]; - _zz_106[14] = execute_SRC1[17]; - _zz_106[15] = execute_SRC1[16]; - _zz_106[16] = execute_SRC1[15]; - _zz_106[17] = execute_SRC1[14]; - _zz_106[18] = execute_SRC1[13]; - _zz_106[19] = execute_SRC1[12]; - _zz_106[20] = execute_SRC1[11]; - _zz_106[21] = execute_SRC1[10]; - _zz_106[22] = execute_SRC1[9]; - _zz_106[23] = execute_SRC1[8]; - _zz_106[24] = execute_SRC1[7]; - _zz_106[25] = execute_SRC1[6]; - _zz_106[26] = execute_SRC1[5]; - _zz_106[27] = execute_SRC1[4]; - _zz_106[28] = execute_SRC1[3]; - _zz_106[29] = execute_SRC1[2]; - _zz_106[30] = execute_SRC1[1]; - _zz_106[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_106 : execute_SRC1); - always @ (*) begin - _zz_107[0] = memory_SHIFT_RIGHT[31]; - _zz_107[1] = memory_SHIFT_RIGHT[30]; - _zz_107[2] = memory_SHIFT_RIGHT[29]; - _zz_107[3] = memory_SHIFT_RIGHT[28]; - _zz_107[4] = memory_SHIFT_RIGHT[27]; - _zz_107[5] = memory_SHIFT_RIGHT[26]; - _zz_107[6] = memory_SHIFT_RIGHT[25]; - _zz_107[7] = memory_SHIFT_RIGHT[24]; - _zz_107[8] = memory_SHIFT_RIGHT[23]; - _zz_107[9] = memory_SHIFT_RIGHT[22]; - _zz_107[10] = memory_SHIFT_RIGHT[21]; - _zz_107[11] = memory_SHIFT_RIGHT[20]; - _zz_107[12] = memory_SHIFT_RIGHT[19]; - _zz_107[13] = memory_SHIFT_RIGHT[18]; - _zz_107[14] = memory_SHIFT_RIGHT[17]; - _zz_107[15] = memory_SHIFT_RIGHT[16]; - _zz_107[16] = memory_SHIFT_RIGHT[15]; - _zz_107[17] = memory_SHIFT_RIGHT[14]; - _zz_107[18] = memory_SHIFT_RIGHT[13]; - _zz_107[19] = memory_SHIFT_RIGHT[12]; - _zz_107[20] = memory_SHIFT_RIGHT[11]; - _zz_107[21] = memory_SHIFT_RIGHT[10]; - _zz_107[22] = memory_SHIFT_RIGHT[9]; - _zz_107[23] = memory_SHIFT_RIGHT[8]; - _zz_107[24] = memory_SHIFT_RIGHT[7]; - _zz_107[25] = memory_SHIFT_RIGHT[6]; - _zz_107[26] = memory_SHIFT_RIGHT[5]; - _zz_107[27] = memory_SHIFT_RIGHT[4]; - _zz_107[28] = memory_SHIFT_RIGHT[3]; - _zz_107[29] = memory_SHIFT_RIGHT[2]; - _zz_107[30] = memory_SHIFT_RIGHT[1]; - _zz_107[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_108 = 1'b0; - if(_zz_226)begin - if(_zz_227)begin - if(_zz_113)begin - _zz_108 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_228)begin - if(_zz_229)begin - if(_zz_115)begin - _zz_108 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_230)begin - if(_zz_231)begin - if(_zz_117)begin - _zz_108 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_108 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_109 = 1'b0; - if(_zz_226)begin - if(_zz_227)begin - if(_zz_114)begin - _zz_109 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_228)begin - if(_zz_229)begin - if(_zz_116)begin - _zz_109 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_230)begin - if(_zz_231)begin - if(_zz_118)begin - _zz_109 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_109 = 1'b0; - end - end - - assign _zz_113 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_114 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_115 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_116 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_117 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_118 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_119 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_119 == 3'b000)) begin - _zz_120 = execute_BranchPlugin_eq; - end else if((_zz_119 == 3'b001)) begin - _zz_120 = (! execute_BranchPlugin_eq); - end else if((((_zz_119 & 3'b101) == 3'b101))) begin - _zz_120 = (! execute_SRC_LESS); - end else begin - _zz_120 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_121 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_121 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_121 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_121 = _zz_120; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_122 = _zz_301[11]; - always @ (*) begin - _zz_123[19] = _zz_122; - _zz_123[18] = _zz_122; - _zz_123[17] = _zz_122; - _zz_123[16] = _zz_122; - _zz_123[15] = _zz_122; - _zz_123[14] = _zz_122; - _zz_123[13] = _zz_122; - _zz_123[12] = _zz_122; - _zz_123[11] = _zz_122; - _zz_123[10] = _zz_122; - _zz_123[9] = _zz_122; - _zz_123[8] = _zz_122; - _zz_123[7] = _zz_122; - _zz_123[6] = _zz_122; - _zz_123[5] = _zz_122; - _zz_123[4] = _zz_122; - _zz_123[3] = _zz_122; - _zz_123[2] = _zz_122; - _zz_123[1] = _zz_122; - _zz_123[0] = _zz_122; - end - - assign _zz_124 = _zz_302[19]; - always @ (*) begin - _zz_125[10] = _zz_124; - _zz_125[9] = _zz_124; - _zz_125[8] = _zz_124; - _zz_125[7] = _zz_124; - _zz_125[6] = _zz_124; - _zz_125[5] = _zz_124; - _zz_125[4] = _zz_124; - _zz_125[3] = _zz_124; - _zz_125[2] = _zz_124; - _zz_125[1] = _zz_124; - _zz_125[0] = _zz_124; - end - - assign _zz_126 = _zz_303[11]; - always @ (*) begin - _zz_127[18] = _zz_126; - _zz_127[17] = _zz_126; - _zz_127[16] = _zz_126; - _zz_127[15] = _zz_126; - _zz_127[14] = _zz_126; - _zz_127[13] = _zz_126; - _zz_127[12] = _zz_126; - _zz_127[11] = _zz_126; - _zz_127[10] = _zz_126; - _zz_127[9] = _zz_126; - _zz_127[8] = _zz_126; - _zz_127[7] = _zz_126; - _zz_127[6] = _zz_126; - _zz_127[5] = _zz_126; - _zz_127[4] = _zz_126; - _zz_127[3] = _zz_126; - _zz_127[2] = _zz_126; - _zz_127[1] = _zz_126; - _zz_127[0] = _zz_126; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_128 = (_zz_304[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_128 = _zz_305[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_128 = _zz_306[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_128); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -3840,80 +4007,80 @@ module VexRiscv ( endcase end - assign _zz_129 = _zz_307[11]; - always @ (*) begin - _zz_130[19] = _zz_129; - _zz_130[18] = _zz_129; - _zz_130[17] = _zz_129; - _zz_130[16] = _zz_129; - _zz_130[15] = _zz_129; - _zz_130[14] = _zz_129; - _zz_130[13] = _zz_129; - _zz_130[12] = _zz_129; - _zz_130[11] = _zz_129; - _zz_130[10] = _zz_129; - _zz_130[9] = _zz_129; - _zz_130[8] = _zz_129; - _zz_130[7] = _zz_129; - _zz_130[6] = _zz_129; - _zz_130[5] = _zz_129; - _zz_130[4] = _zz_129; - _zz_130[3] = _zz_129; - _zz_130[2] = _zz_129; - _zz_130[1] = _zz_129; - _zz_130[0] = _zz_129; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_130,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_132,{{{_zz_528,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_134,{{{_zz_529,_zz_530},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_310}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_131 = _zz_308[19]; - always @ (*) begin - _zz_132[10] = _zz_131; - _zz_132[9] = _zz_131; - _zz_132[8] = _zz_131; - _zz_132[7] = _zz_131; - _zz_132[6] = _zz_131; - _zz_132[5] = _zz_131; - _zz_132[4] = _zz_131; - _zz_132[3] = _zz_131; - _zz_132[2] = _zz_131; - _zz_132[1] = _zz_131; - _zz_132[0] = _zz_131; - end - - assign _zz_133 = _zz_309[11]; - always @ (*) begin - _zz_134[18] = _zz_133; - _zz_134[17] = _zz_133; - _zz_134[16] = _zz_133; - _zz_134[15] = _zz_133; - _zz_134[14] = _zz_133; - _zz_134[13] = _zz_133; - _zz_134[12] = _zz_133; - _zz_134[11] = _zz_133; - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -3923,92 +4090,106 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_135 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_136 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_137 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_138 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_139 = _zz_311[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_220)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4019,8 +4200,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4030,135 +4211,144 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_232)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_233)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_234)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_233)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_234)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4171,39 +4361,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_232)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_232)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_245) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_235) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4216,8 +4416,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_235) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4236,79 +4436,150 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_313) + $signed(_zz_314)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_215)begin - if(_zz_236)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_237)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_318); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_140 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_140[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_319); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_320 : _zz_321); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_322[31:0]; - assign _zz_141 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_142 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_143 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_144[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_144[31 : 0] = execute_RS1; - end - - assign _zz_146 = (_zz_145 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_146 != 32'h0); - assign _zz_26 = decode_SRC1_CTRL; - assign _zz_24 = _zz_49; - assign _zz_37 = decode_to_execute_SRC1_CTRL; - assign _zz_23 = decode_ALU_CTRL; - assign _zz_21 = _zz_48; - assign _zz_38 = decode_to_execute_ALU_CTRL; - assign _zz_20 = decode_SRC2_CTRL; - assign _zz_18 = _zz_47; - assign _zz_36 = decode_to_execute_SRC2_CTRL; - assign _zz_17 = decode_ALU_BITWISE_CTRL; - assign _zz_15 = _zz_46; - assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_14 = decode_SHIFT_CTRL; - assign _zz_11 = execute_SHIFT_CTRL; - assign _zz_12 = _zz_45; - assign _zz_34 = decode_to_execute_SHIFT_CTRL; - assign _zz_33 = execute_to_memory_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_51 = _zz_44; - assign _zz_30 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_43; - assign _zz_28 = decode_to_execute_ENV_CTRL; - assign _zz_27 = execute_to_memory_ENV_CTRL; - assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4329,240 +4600,273 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_147 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_147[12 : 0] = 13'h1000; - _zz_147[25 : 20] = 6'h20; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_148 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_148[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_149 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_149[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_150 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_150[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_151 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_151[31 : 30] = CsrPlugin_misa_base; - _zz_151[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_152 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_152[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_152[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_152[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_153 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_153[11 : 11] = CsrPlugin_mip_MEIP; - _zz_153[7 : 7] = CsrPlugin_mip_MTIP; - _zz_153[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_154 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_154[11 : 11] = CsrPlugin_mie_MEIE; - _zz_154[7 : 7] = CsrPlugin_mie_MTIE; - _zz_154[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_155 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_155[31 : 2] = CsrPlugin_mtvec_base; - _zz_155[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_156 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_156[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_157 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_157[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_158 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_158[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_158[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_159 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_159[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_160 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_160[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_161 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_161[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_162 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_162[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_163 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_163[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_164 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_164[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_165 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_165[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_166 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_166[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_167 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_167[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_168 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_168[31 : 0] = _zz_145; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_169 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_169[31 : 0] = _zz_146; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = (((((_zz_147 | _zz_148) | (_zz_149 | _zz_150)) | ((_zz_531 | _zz_151) | (_zz_152 | _zz_153))) | (((_zz_154 | _zz_155) | (_zz_156 | _zz_157)) | ((_zz_158 | _zz_159) | (_zz_160 | _zz_161)))) | (((_zz_162 | _zz_163) | (_zz_164 | _zz_165)) | ((_zz_166 | _zz_167) | (_zz_168 | _zz_169)))); - assign iBusWishbone_ADR = {_zz_339,_zz_170}; - assign iBusWishbone_CTI = ((_zz_170 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_238)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_238)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_171; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_177 = (dBus_cmd_payload_length != 3'b000); - assign _zz_173 = dBus_cmd_valid; - assign _zz_175 = dBus_cmd_payload_wr; - assign _zz_176 = (_zz_172 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_174 && (_zz_175 || _zz_176)); - assign dBusWishbone_ADR = ((_zz_177 ? {{dBus_cmd_payload_address[31 : 5],_zz_172},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_177 ? (_zz_176 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_175 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_175; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_174 = (_zz_173 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_173; - assign dBusWishbone_STB = _zz_173; - assign dBus_rsp_valid = _zz_178; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_64 <= 1'b0; - _zz_66 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_79; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_80; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_98 <= 1'b1; - _zz_110 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4583,159 +4887,159 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_145 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_170 <= 3'b000; - _zz_171 <= 1'b0; - _zz_172 <= 3'b000; - _zz_178 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_64 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_62)begin - _zz_64 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_66 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_66 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_239)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_98 <= 1'b0; - _zz_110 <= (_zz_41 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_240)begin - if(_zz_241)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_242)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_243)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_222)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4746,8 +5050,8 @@ module VexRiscv ( end endcase end - if(_zz_223)begin - case(_zz_224) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4757,141 +5061,141 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_137,{_zz_136,_zz_135}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_332[0]; - CsrPlugin_mstatus_MIE <= _zz_333[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_335[0]; - CsrPlugin_mie_MTIE <= _zz_336[0]; - CsrPlugin_mie_MSIE <= _zz_337[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_145 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_238)begin - if(iBusWishbone_ACK)begin - _zz_170 <= (_zz_170 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_171 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_173 && _zz_174))begin - _zz_172 <= (_zz_172 + 3'b001); - if(_zz_176)begin - _zz_172 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_178 <= ((_zz_173 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_67 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_239)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_111 <= _zz_40[11 : 7]; - _zz_112 <= _zz_50; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_220)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_139 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_139 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_240)begin - if(_zz_241)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_242)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_243)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_222)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -4899,336 +5203,336 @@ module VexRiscv ( end endcase end - if((memory_DivPlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_DivPlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_215)begin - if(_zz_236)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_323[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; end end end - if(_zz_237)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_143 ? (~ _zz_144) : _zz_144) + _zz_329); - memory_DivPlugin_rs2 <= ((_zz_142 ? (~ execute_RS2) : execute_RS2) + _zz_331); - memory_DivPlugin_div_needRevert <= ((_zz_143 ^ (_zz_142 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_35; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_7) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_25; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_22; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_19; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_10; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_49) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_50) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + if(when_Pipeline_l124_51) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + if(when_Pipeline_l124_52) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_53) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_54) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_334[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_338[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -5241,9 +5545,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -5265,6 +5568,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -5280,9 +5584,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -5290,7 +5595,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -5299,24 +5604,15 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -5341,40 +5637,48 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5384,23 +5688,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -5408,10 +5722,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -5423,59 +5745,54 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -5490,274 +5807,293 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -5765,89 +6101,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_16)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -5855,12 +6175,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -5871,20 +6191,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -5892,45 +6232,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -5941,46 +6283,37 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; @@ -5988,50 +6321,51 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6081,13 +6415,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [21:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [21:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6096,8 +6426,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -6111,22 +6446,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -6136,82 +6474,85 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - assign _zz_11 = (! lineLoader_flushCounter[7]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -6227,30 +6568,35 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -6258,51 +6604,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 8'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -6313,10 +6659,10 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index c5eea43..11834d9 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,57 +1,58 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 5bb91146a62643cf606443d5366c69720906549c - - -`define Input2Kind_defaultEncoding_type [0:0] -`define Input2Kind_defaultEncoding_RS 1'b0 -`define Input2Kind_defaultEncoding_IMM_I 1'b1 - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define Input2Kind_binary_sequential_type [0:0] +`define Input2Kind_binary_sequential_RS 1'b0 +`define Input2Kind_binary_sequential_IMM_I 1'b1 + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, + input [31:0] externalInterruptArray, output CfuPlugin_bus_cmd_valid, input CfuPlugin_bus_cmd_ready, output [9:0] CfuPlugin_bus_cmd_payload_function_id, @@ -59,9 +60,7 @@ module VexRiscv ( output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, input CfuPlugin_bus_rsp_valid, output CfuPlugin_bus_rsp_ready, - input CfuPlugin_bus_rsp_payload_response_ok, input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, - input [31:0] externalInterruptArray, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, input iBusWishbone_ACK, @@ -87,37 +86,37 @@ module VexRiscv ( input clk, input reset ); - wire _zz_217; - wire _zz_218; - wire _zz_219; - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - reg _zz_225; - wire _zz_226; - wire [31:0] _zz_227; - wire _zz_228; - wire [31:0] _zz_229; - reg _zz_230; - wire _zz_231; - wire _zz_232; - wire [31:0] _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire [3:0] _zz_242; - wire _zz_243; - wire _zz_244; - reg [31:0] _zz_245; - reg [31:0] _zz_246; - reg [31:0] _zz_247; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -140,6 +139,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -148,389 +148,329 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_248; - wire _zz_249; - wire _zz_250; - wire _zz_251; - wire _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire _zz_256; - wire _zz_257; - wire _zz_258; - wire _zz_259; - wire _zz_260; - wire _zz_261; - wire _zz_262; - wire [1:0] _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire _zz_267; - wire _zz_268; - wire _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire [1:0] _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire _zz_279; - wire _zz_280; - wire _zz_281; - wire _zz_282; - wire _zz_283; - wire [1:0] _zz_284; - wire _zz_285; - wire [1:0] _zz_286; - wire [51:0] _zz_287; - wire [51:0] _zz_288; - wire [51:0] _zz_289; - wire [32:0] _zz_290; - wire [51:0] _zz_291; - wire [49:0] _zz_292; - wire [51:0] _zz_293; - wire [49:0] _zz_294; - wire [51:0] _zz_295; - wire [32:0] _zz_296; - wire [31:0] _zz_297; - wire [32:0] _zz_298; - wire [0:0] _zz_299; - wire [0:0] _zz_300; - wire [0:0] _zz_301; - wire [0:0] _zz_302; - wire [0:0] _zz_303; - wire [0:0] _zz_304; - wire [0:0] _zz_305; - wire [0:0] _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire [0:0] _zz_312; - wire [0:0] _zz_313; - wire [0:0] _zz_314; - wire [0:0] _zz_315; - wire [0:0] _zz_316; - wire [3:0] _zz_317; - wire [2:0] _zz_318; - wire [31:0] _zz_319; - wire [11:0] _zz_320; - wire [31:0] _zz_321; - wire [19:0] _zz_322; - wire [11:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [19:0] _zz_326; - wire [11:0] _zz_327; - wire [2:0] _zz_328; - wire [2:0] _zz_329; - wire [0:0] _zz_330; - wire [2:0] _zz_331; - wire [4:0] _zz_332; - wire [11:0] _zz_333; - wire [11:0] _zz_334; - wire [31:0] _zz_335; - wire [31:0] _zz_336; - wire [31:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire [31:0] _zz_340; - wire [31:0] _zz_341; - wire [11:0] _zz_342; - wire [19:0] _zz_343; - wire [11:0] _zz_344; - wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [11:0] _zz_348; - wire [19:0] _zz_349; - wire [11:0] _zz_350; - wire [2:0] _zz_351; - wire [1:0] _zz_352; - wire [1:0] _zz_353; - wire [1:0] _zz_354; - wire [1:0] _zz_355; - wire [9:0] _zz_356; - wire [7:0] _zz_357; - wire [65:0] _zz_358; - wire [65:0] _zz_359; - wire [31:0] _zz_360; - wire [31:0] _zz_361; - wire [0:0] _zz_362; - wire [5:0] _zz_363; - wire [32:0] _zz_364; - wire [31:0] _zz_365; - wire [31:0] _zz_366; - wire [32:0] _zz_367; - wire [32:0] _zz_368; - wire [32:0] _zz_369; - wire [32:0] _zz_370; - wire [0:0] _zz_371; - wire [32:0] _zz_372; - wire [0:0] _zz_373; - wire [32:0] _zz_374; - wire [0:0] _zz_375; - wire [31:0] _zz_376; - wire [0:0] _zz_377; - wire [0:0] _zz_378; - wire [0:0] _zz_379; - wire [0:0] _zz_380; - wire [0:0] _zz_381; - wire [0:0] _zz_382; - wire [0:0] _zz_383; - wire [26:0] _zz_384; - wire _zz_385; - wire _zz_386; - wire [1:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire _zz_391; - wire [0:0] _zz_392; - wire [14:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire _zz_397; - wire [0:0] _zz_398; - wire [8:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire [31:0] _zz_402; - wire _zz_403; - wire [0:0] _zz_404; - wire [2:0] _zz_405; - wire _zz_406; - wire _zz_407; - wire _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire _zz_411; - wire _zz_412; - wire [0:0] _zz_413; - wire [26:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire [1:0] _zz_420; - wire [1:0] _zz_421; - wire _zz_422; - wire [0:0] _zz_423; - wire [21:0] _zz_424; - wire [31:0] _zz_425; - wire [31:0] _zz_426; - wire [31:0] _zz_427; - wire [31:0] _zz_428; - wire [31:0] _zz_429; - wire [31:0] _zz_430; - wire [0:0] _zz_431; - wire [0:0] _zz_432; - wire [2:0] _zz_433; - wire [2:0] _zz_434; - wire _zz_435; - wire [0:0] _zz_436; - wire [18:0] _zz_437; - wire [31:0] _zz_438; - wire [31:0] _zz_439; - wire [31:0] _zz_440; - wire [31:0] _zz_441; - wire _zz_442; - wire _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire _zz_446; - wire [0:0] _zz_447; - wire [0:0] _zz_448; - wire _zz_449; - wire [0:0] _zz_450; - wire [15:0] _zz_451; - wire [31:0] _zz_452; - wire _zz_453; - wire _zz_454; - wire _zz_455; - wire [2:0] _zz_456; - wire [2:0] _zz_457; - wire _zz_458; - wire [0:0] _zz_459; - wire [12:0] _zz_460; - wire _zz_461; - wire _zz_462; - wire _zz_463; - wire [0:0] _zz_464; - wire [2:0] _zz_465; - wire _zz_466; - wire [5:0] _zz_467; - wire [5:0] _zz_468; - wire _zz_469; - wire [0:0] _zz_470; - wire [9:0] _zz_471; - wire [31:0] _zz_472; - wire [31:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [0:0] _zz_479; - wire [31:0] _zz_480; - wire _zz_481; - wire [0:0] _zz_482; - wire [3:0] _zz_483; - wire [0:0] _zz_484; - wire [3:0] _zz_485; - wire [5:0] _zz_486; - wire [5:0] _zz_487; - wire _zz_488; - wire [0:0] _zz_489; - wire [7:0] _zz_490; - wire [31:0] _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; - wire [31:0] _zz_496; - wire [31:0] _zz_497; - wire [31:0] _zz_498; - wire [0:0] _zz_499; - wire [1:0] _zz_500; - wire _zz_501; - wire [0:0] _zz_502; - wire [1:0] _zz_503; - wire [0:0] _zz_504; - wire [3:0] _zz_505; - wire [0:0] _zz_506; - wire [0:0] _zz_507; - wire [1:0] _zz_508; - wire [1:0] _zz_509; - wire _zz_510; - wire [0:0] _zz_511; - wire [5:0] _zz_512; - wire [31:0] _zz_513; - wire [31:0] _zz_514; - wire _zz_515; - wire _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire _zz_520; - wire _zz_521; - wire [31:0] _zz_522; - wire [31:0] _zz_523; - wire _zz_524; - wire [0:0] _zz_525; - wire [1:0] _zz_526; - wire [31:0] _zz_527; - wire [31:0] _zz_528; - wire _zz_529; - wire _zz_530; - wire [0:0] _zz_531; - wire [0:0] _zz_532; - wire _zz_533; - wire [0:0] _zz_534; - wire [3:0] _zz_535; - wire [31:0] _zz_536; - wire [31:0] _zz_537; - wire [31:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire [31:0] _zz_541; - wire [31:0] _zz_542; - wire _zz_543; - wire _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire [0:0] _zz_549; - wire [2:0] _zz_550; - wire [0:0] _zz_551; - wire [0:0] _zz_552; - wire _zz_553; - wire [0:0] _zz_554; - wire [1:0] _zz_555; - wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire _zz_559; - wire _zz_560; - wire [31:0] _zz_561; - wire _zz_562; - wire [0:0] _zz_563; - wire [0:0] _zz_564; - wire [0:0] _zz_565; - wire [0:0] _zz_566; - wire [1:0] _zz_567; - wire [1:0] _zz_568; - wire [0:0] _zz_569; - wire [0:0] _zz_570; - wire [31:0] _zz_571; - wire [31:0] _zz_572; - wire [31:0] _zz_573; - wire [31:0] _zz_574; - wire [31:0] _zz_575; - wire [31:0] _zz_576; - wire _zz_577; - wire _zz_578; - wire _zz_579; - wire [31:0] _zz_580; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6; + wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18; + wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33; + wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45; + wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68; + wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100; + wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125; + wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1; + wire _zz_when; + wire _zz_when_1; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_41; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; - wire writeBack_CfuPlugin_CFU_IN_FLIGHT; - wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; wire decode_SRC2_FORCE_ZERO; + wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + wire decode_CfuPlugin_CFU_ENABLE; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_DIV; wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_1; - wire `Input2Kind_defaultEncoding_type _zz_2; - wire `Input2Kind_defaultEncoding_type _zz_3; - wire decode_CfuPlugin_CFU_ENABLE; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -538,24 +478,30 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; - wire `AluCtrlEnum_defaultEncoding_type _zz_25; - wire `AluCtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; - wire `Src1CtrlEnum_defaultEncoding_type _zz_28; - wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] memory_PC; + reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire execute_CfuPlugin_CFU_ENABLE; wire execute_IS_RS1_SIGNED; wire execute_IS_DIV; wire execute_IS_RS2_SIGNED; @@ -566,32 +512,26 @@ module VexRiscv ( wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; - reg _zz_30; - reg _zz_31; - wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_32; - wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_37; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -601,46 +541,46 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_38; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_41; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_42; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; - wire [31:0] _zz_46; - wire _zz_47; - reg _zz_48; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_49; - wire `EnvCtrlEnum_defaultEncoding_type _zz_50; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; - wire `Src2CtrlEnum_defaultEncoding_type _zz_54; - wire `AluCtrlEnum_defaultEncoding_type _zz_55; - wire `Src1CtrlEnum_defaultEncoding_type _zz_56; - reg [31:0] _zz_57; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -658,11 +598,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_59; - reg [31:0] _zz_60; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -692,7 +632,7 @@ module VexRiscv ( wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; + wire memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; @@ -749,7 +689,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -783,6 +723,11 @@ module VexRiscv ( reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -800,31 +745,34 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; - reg CfuPlugin_joinException_valid; - wire [3:0] CfuPlugin_joinException_payload_code; - wire [31:0] CfuPlugin_joinException_payload_badAddr; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_61; - wire [3:0] _zz_62; - wire _zz_63; - wire _zz_64; - wire _zz_65; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -847,16 +795,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_66; - wire _zz_67; - wire _zz_68; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_69; - wire _zz_70; - reg _zz_71; - wire _zz_72; - reg _zz_73; - reg [31:0] _zz_74; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -864,22 +814,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_75; - reg [18:0] _zz_76; - wire _zz_77; - reg [10:0] _zz_78; - wire _zz_79; - reg [18:0] _zz_80; - reg _zz_81; - wire _zz_82; - reg [10:0] _zz_83; - wire _zz_84; - reg [18:0] _zz_85; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -887,7 +844,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_86; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -895,23 +852,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -919,40 +881,56 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_87; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_88; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_89; - reg [31:0] _zz_90; - wire _zz_91; - reg [31:0] _zz_92; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [33:0] _zz_93; - wire _zz_94; - wire _zz_95; - wire _zz_96; - wire _zz_97; - wire _zz_98; - wire `Src1CtrlEnum_defaultEncoding_type _zz_99; - wire `AluCtrlEnum_defaultEncoding_type _zz_100; - wire `Src2CtrlEnum_defaultEncoding_type _zz_101; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_102; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_103; - wire `BranchCtrlEnum_defaultEncoding_type _zz_104; - wire `EnvCtrlEnum_defaultEncoding_type _zz_105; - wire `Input2Kind_defaultEncoding_type _zz_106; + wire when_DBusCachedPlugin_l484; + wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -960,53 +938,72 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_107; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_108; - reg [31:0] _zz_109; - wire _zz_110; - reg [19:0] _zz_111; - wire _zz_112; - reg [19:0] _zz_113; - reg [31:0] _zz_114; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_115; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_116; - reg _zz_117; - reg _zz_118; - reg _zz_119; - reg [4:0] _zz_120; - reg [31:0] _zz_121; - wire _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; - wire _zz_126; - wire _zz_127; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_128; - reg _zz_129; - reg _zz_130; - wire _zz_131; - reg [19:0] _zz_132; - wire _zz_133; - reg [10:0] _zz_134; - wire _zz_135; - reg [18:0] _zz_136; - reg _zz_137; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_138; - reg [19:0] _zz_139; - wire _zz_140; - reg [10:0] _zz_141; - wire _zz_142; - reg [18:0] _zz_143; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; + wire when_BranchPlugin_l296; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1027,9 +1024,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_144; - wire _zz_145; - wire _zz_146; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1042,72 +1039,69 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_147; - wire _zz_148; - wire [1:0] _zz_149; - wire _zz_150; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - wire execute_CfuPlugin_schedule; - reg execute_CfuPlugin_hold; - reg execute_CfuPlugin_fired; - wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_167; - reg [23:0] _zz_168; - reg [31:0] _zz_169; - wire memory_CfuPlugin_rsp_valid; - reg memory_CfuPlugin_rsp_ready; - wire memory_CfuPlugin_rsp_payload_response_ok; - wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_s2mPipe_rValid; - reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1115,6 +1109,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1127,242 +1123,402 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_170; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_171; - wire _zz_172; - wire _zz_173; - reg [32:0] _zz_174; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_175; - wire [31:0] _zz_176; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire CfuPlugin_bus_cmd_fire; + wire when_CfuPlugin_l171; + wire when_CfuPlugin_l175; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_CfuPlugin_bus_cmd_payload_inputs_1; + reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1; + reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + wire CfuPlugin_bus_rsp_rsp_valid; + reg CfuPlugin_bus_rsp_rsp_ready; + wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_rValid; + reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; + wire when_CfuPlugin_l208; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_when_GenCoreDefault_l367; + wire when_GenCoreDefault_l367; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_when_GenCoreDefault_l367_1; + wire when_GenCoreDefault_l367_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_when_GenCoreDefault_l367_2; + wire when_GenCoreDefault_l367_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_when_GenCoreDefault_l367_3; + wire when_GenCoreDefault_l367_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_when_GenCoreDefault_l367_4; + wire when_GenCoreDefault_l367_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_when_GenCoreDefault_l367_5; + wire when_GenCoreDefault_l367_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_when_GenCoreDefault_l367_6; + wire when_GenCoreDefault_l367_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_when_GenCoreDefault_l367_7; + wire when_GenCoreDefault_l367_7; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + wire when_Pipeline_l124_44; + reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_45; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_46; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_47; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_48; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_49; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_50; reg decode_to_execute_CSR_READ_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_51; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_52; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_53; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_54; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_55; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_57; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_60; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_61; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_62; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_63; reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; + reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; + reg execute_CsrPlugin_csr_4032; + wire when_CsrPlugin_l1264_24; reg execute_CsrPlugin_csr_2820; + wire when_CsrPlugin_l1264_25; reg execute_CsrPlugin_csr_2821; + wire when_CsrPlugin_l1264_26; reg execute_CsrPlugin_csr_2822; + wire when_CsrPlugin_l1264_27; reg execute_CsrPlugin_csr_2823; + wire when_CsrPlugin_l1264_28; reg execute_CsrPlugin_csr_2824; + wire when_CsrPlugin_l1264_29; reg execute_CsrPlugin_csr_2825; + wire when_CsrPlugin_l1264_30; reg execute_CsrPlugin_csr_2826; + wire when_CsrPlugin_l1264_31; reg execute_CsrPlugin_csr_2827; + wire when_CsrPlugin_l1264_32; reg execute_CsrPlugin_csr_2828; + wire when_CsrPlugin_l1264_33; reg execute_CsrPlugin_csr_2829; + wire when_CsrPlugin_l1264_34; reg execute_CsrPlugin_csr_2830; + wire when_CsrPlugin_l1264_35; reg execute_CsrPlugin_csr_2831; + wire when_CsrPlugin_l1264_36; reg execute_CsrPlugin_csr_2832; + wire when_CsrPlugin_l1264_37; reg execute_CsrPlugin_csr_2833; + wire when_CsrPlugin_l1264_38; reg execute_CsrPlugin_csr_2834; + wire when_CsrPlugin_l1264_39; reg execute_CsrPlugin_csr_2835; - reg execute_CsrPlugin_csr_3008; - reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [31:0] _zz_199; - reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; - reg [2:0] _zz_208; - reg _zz_209; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_29; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_30; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_31; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_32; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_33; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_34; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_35; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_36; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_37; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_38; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_39; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_40; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - reg _zz_216; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8_string; - reg [39:0] _zz_9_string; - reg [39:0] _zz_10_string; - reg [31:0] _zz_11_string; - reg [31:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_15_string; - reg [71:0] _zz_16_string; - reg [71:0] _zz_17_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_18_string; - reg [39:0] _zz_19_string; - reg [39:0] _zz_20_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_21_string; - reg [23:0] _zz_22_string; - reg [23:0] _zz_23_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_24_string; - reg [63:0] _zz_25_string; - reg [63:0] _zz_26_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_27_string; - reg [95:0] _zz_28_string; - reg [95:0] _zz_29_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_32_string; + reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_36_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_39_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_40_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_42_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_43_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_44_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_45_string; - reg [39:0] _zz_49_string; - reg [39:0] _zz_50_string; - reg [31:0] _zz_51_string; - reg [71:0] _zz_52_string; - reg [39:0] _zz_53_string; - reg [23:0] _zz_54_string; - reg [63:0] _zz_55_string; - reg [95:0] _zz_56_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_58_string; - reg [95:0] _zz_99_string; - reg [63:0] _zz_100_string; - reg [23:0] _zz_101_string; - reg [39:0] _zz_102_string; - reg [71:0] _zz_103_string; - reg [31:0] _zz_104_string; - reg [39:0] _zz_105_string; - reg [39:0] _zz_106_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1378,473 +1534,437 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_248 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_249 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_250 = 1'b1; - assign _zz_251 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_252 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_254 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_255 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_256 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_257 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_260 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_264 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_265 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_266 = (1'b0 || (! 1'b1)); - assign _zz_267 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_268 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_270 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_271 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_272 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_273 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_274 = execute_INSTRUCTION[13 : 12]; - assign _zz_275 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_276 = (! memory_arbitration_isStuck); - assign _zz_277 = (iBus_cmd_valid || (_zz_208 != 3'b000)); - assign _zz_278 = (_zz_244 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_280 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_281 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_282 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_285 = execute_INSTRUCTION[13]; - assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); - assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); - assign _zz_289 = 52'h0; - assign _zz_290 = {1'b0,memory_MUL_LL}; - assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; - assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; - assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; - assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_297 = _zz_296[31 : 0]; - assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_299 = _zz_93[33 : 33]; - assign _zz_300 = _zz_93[32 : 32]; - assign _zz_301 = _zz_93[31 : 31]; - assign _zz_302 = _zz_93[30 : 30]; - assign _zz_303 = _zz_93[28 : 28]; - assign _zz_304 = _zz_93[25 : 25]; - assign _zz_305 = _zz_93[17 : 17]; - assign _zz_306 = _zz_93[16 : 16]; - assign _zz_307 = _zz_93[13 : 13]; - assign _zz_308 = _zz_93[12 : 12]; - assign _zz_309 = _zz_93[11 : 11]; - assign _zz_310 = _zz_93[15 : 15]; - assign _zz_311 = _zz_93[5 : 5]; - assign _zz_312 = _zz_93[3 : 3]; - assign _zz_313 = _zz_93[20 : 20]; - assign _zz_314 = _zz_93[10 : 10]; - assign _zz_315 = _zz_93[4 : 4]; - assign _zz_316 = _zz_93[0 : 0]; - assign _zz_317 = (_zz_61 - 4'b0001); - assign _zz_318 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_319 = {29'd0, _zz_318}; - assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_321 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_324 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_325 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_326 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_328 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_329 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_330 = execute_SRC_LESS; - assign _zz_331 = 3'b100; - assign _zz_332 = execute_INSTRUCTION[19 : 15]; - assign _zz_333 = execute_INSTRUCTION[31 : 20]; - assign _zz_334 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_335 = ($signed(_zz_336) + $signed(_zz_339)); - assign _zz_336 = ($signed(_zz_337) + $signed(_zz_338)); - assign _zz_337 = execute_SRC1; - assign _zz_338 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_339 = (execute_SRC_USE_SUB_LESS ? _zz_340 : _zz_341); - assign _zz_340 = 32'h00000001; - assign _zz_341 = 32'h0; - assign _zz_342 = execute_INSTRUCTION[31 : 20]; - assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_345 = {_zz_132,execute_INSTRUCTION[31 : 20]}; - assign _zz_346 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_347 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_348 = execute_INSTRUCTION[31 : 20]; - assign _zz_349 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_351 = 3'b100; - assign _zz_352 = (_zz_147 & (~ _zz_353)); - assign _zz_353 = (_zz_147 - 2'b01); - assign _zz_354 = (_zz_149 & (~ _zz_355)); - assign _zz_355 = (_zz_149 - 2'b01); - assign _zz_356 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_357 = execute_INSTRUCTION[31 : 24]; - assign _zz_358 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_359 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_360 = writeBack_MUL_LOW[31 : 0]; - assign _zz_361 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_362 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_363 = {5'd0, _zz_362}; - assign _zz_364 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_365 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_366 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_367 = {_zz_170,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_368 = _zz_369; - assign _zz_369 = _zz_370; - assign _zz_370 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_171) : _zz_171)} + _zz_372); - assign _zz_371 = memory_DivPlugin_div_needRevert; - assign _zz_372 = {32'd0, _zz_371}; - assign _zz_373 = _zz_173; - assign _zz_374 = {32'd0, _zz_373}; - assign _zz_375 = _zz_172; - assign _zz_376 = {31'd0, _zz_375}; - assign _zz_377 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_378 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_380 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_381 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_382 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_383 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_384 = (iBus_cmd_payload_address >>> 5); - assign _zz_385 = 1'b1; - assign _zz_386 = 1'b1; - assign _zz_387 = {_zz_65,_zz_64}; - assign _zz_388 = 32'h0000106f; - assign _zz_389 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_390 = 32'h00001073; - assign _zz_391 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_392 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_393 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_394) == 32'h00000003),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; - assign _zz_394 = 32'h0000207f; - assign _zz_395 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_396 = 32'h00000003; - assign _zz_397 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_398 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_399 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_400) == 32'h00005013),{(_zz_401 == _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; - assign _zz_400 = 32'hbc00707f; - assign _zz_401 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_402 = 32'h00001013; - assign _zz_403 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_405 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_406 = decode_INSTRUCTION[31]; - assign _zz_407 = decode_INSTRUCTION[31]; - assign _zz_408 = decode_INSTRUCTION[7]; - assign _zz_409 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_410 = 32'h02004020; - assign _zz_411 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_412 = (_zz_97 != 1'b0); - assign _zz_413 = (((decode_INSTRUCTION & _zz_415) == 32'h00000050) != 1'b0); - assign _zz_414 = {((_zz_416 == _zz_417) != 1'b0),{({_zz_418,_zz_419} != 2'b00),{(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}}}; - assign _zz_415 = 32'h00203050; - assign _zz_416 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_417 = 32'h00000050; - assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00001050); - assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00002050); - assign _zz_420 = {_zz_96,(_zz_427 == _zz_428)}; - assign _zz_421 = 2'b00; - assign _zz_422 = ((_zz_429 == _zz_430) != 1'b0); - assign _zz_423 = ({_zz_431,_zz_432} != 2'b00); - assign _zz_424 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; - assign _zz_425 = 32'h00001050; - assign _zz_426 = 32'h00002050; - assign _zz_427 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_428 = 32'h00000004; - assign _zz_429 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_430 = 32'h00000040; - assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h00005010); - assign _zz_432 = ((decode_INSTRUCTION & _zz_439) == 32'h00005020); - assign _zz_433 = {(_zz_440 == _zz_441),{_zz_442,_zz_443}}; - assign _zz_434 = 3'b000; - assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); - assign _zz_436 = (_zz_446 != 1'b0); - assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; - assign _zz_438 = 32'h00007034; - assign _zz_439 = 32'h02007064; - assign _zz_440 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_441 = 32'h40001010; - assign _zz_442 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_443 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_445 = 32'h00000024; - assign _zz_446 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_447 = ((decode_INSTRUCTION & _zz_452) == 32'h00002000); - assign _zz_448 = 1'b0; - assign _zz_449 = ({_zz_453,_zz_454} != 2'b00); - assign _zz_450 = (_zz_455 != 1'b0); - assign _zz_451 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; - assign _zz_452 = 32'h00003000; - assign _zz_453 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_454 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_455 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_456 = {_zz_97,{_zz_461,_zz_462}}; - assign _zz_457 = 3'b000; - assign _zz_458 = ({_zz_463,{_zz_464,_zz_465}} != 5'h0); - assign _zz_459 = (_zz_466 != 1'b0); - assign _zz_460 = {(_zz_467 != _zz_468),{_zz_469,{_zz_470,_zz_471}}}; - assign _zz_461 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); - assign _zz_462 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); - assign _zz_463 = ((decode_INSTRUCTION & _zz_474) == 32'h00002040); - assign _zz_464 = (_zz_475 == _zz_476); - assign _zz_465 = {_zz_477,{_zz_478,_zz_479}}; - assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000020); - assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; - assign _zz_468 = 6'h0; - assign _zz_469 = ({_zz_484,_zz_485} != 5'h0); - assign _zz_470 = (_zz_486 != _zz_487); - assign _zz_471 = {_zz_488,{_zz_489,_zz_490}}; - assign _zz_472 = 32'h00000034; - assign _zz_473 = 32'h00000064; - assign _zz_474 = 32'h00002040; - assign _zz_475 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_476 = 32'h00001040; - assign _zz_477 = ((decode_INSTRUCTION & _zz_491) == 32'h00000040); - assign _zz_478 = (_zz_492 == _zz_493); - assign _zz_479 = (_zz_494 == _zz_495); - assign _zz_480 = 32'h00000020; - assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00000008); - assign _zz_482 = (_zz_497 == _zz_498); - assign _zz_483 = {_zz_95,{_zz_499,_zz_500}}; - assign _zz_484 = _zz_95; - assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; - assign _zz_486 = {_zz_96,{_zz_504,_zz_505}}; - assign _zz_487 = 6'h0; - assign _zz_488 = ({_zz_506,_zz_507} != 2'b00); - assign _zz_489 = (_zz_508 != _zz_509); - assign _zz_490 = {_zz_510,{_zz_511,_zz_512}}; - assign _zz_491 = 32'h00000050; - assign _zz_492 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_493 = 32'h00000040; - assign _zz_494 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_495 = 32'h0; - assign _zz_496 = 32'h00000008; - assign _zz_497 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_498 = 32'h00000040; - assign _zz_499 = (_zz_513 == _zz_514); - assign _zz_500 = {_zz_515,_zz_516}; - assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00002010); - assign _zz_502 = (_zz_518 == _zz_519); - assign _zz_503 = {_zz_520,_zz_521}; - assign _zz_504 = (_zz_522 == _zz_523); - assign _zz_505 = {_zz_524,{_zz_525,_zz_526}}; - assign _zz_506 = _zz_95; - assign _zz_507 = (_zz_527 == _zz_528); - assign _zz_508 = {_zz_95,_zz_529}; - assign _zz_509 = 2'b00; - assign _zz_510 = (_zz_530 != 1'b0); - assign _zz_511 = (_zz_531 != _zz_532); - assign _zz_512 = {_zz_533,{_zz_534,_zz_535}}; - assign _zz_513 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_514 = 32'h00004020; - assign _zz_515 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); - assign _zz_516 = ((decode_INSTRUCTION & _zz_537) == 32'h00000020); - assign _zz_517 = 32'h00002030; - assign _zz_518 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_519 = 32'h00000010; - assign _zz_520 = ((decode_INSTRUCTION & _zz_538) == 32'h00002020); - assign _zz_521 = ((decode_INSTRUCTION & _zz_539) == 32'h00000020); - assign _zz_522 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_523 = 32'h00001010; - assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00002010); - assign _zz_525 = (_zz_541 == _zz_542); - assign _zz_526 = {_zz_543,_zz_544}; - assign _zz_527 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_528 = 32'h00000020; - assign _zz_529 = ((decode_INSTRUCTION & _zz_545) == 32'h0); - assign _zz_530 = ((decode_INSTRUCTION & _zz_546) == 32'h00004010); - assign _zz_531 = (_zz_547 == _zz_548); - assign _zz_532 = 1'b0; - assign _zz_533 = ({_zz_549,_zz_550} != 4'b0000); - assign _zz_534 = (_zz_551 != _zz_552); - assign _zz_535 = {_zz_553,{_zz_554,_zz_555}}; - assign _zz_536 = 32'h00000030; - assign _zz_537 = 32'h02000020; - assign _zz_538 = 32'h02002060; - assign _zz_539 = 32'h02003020; - assign _zz_540 = 32'h00002010; - assign _zz_541 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_542 = 32'h00000010; - assign _zz_543 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_544 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_545 = 32'h00000020; - assign _zz_546 = 32'h00004014; - assign _zz_547 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_548 = 32'h00002010; - assign _zz_549 = ((decode_INSTRUCTION & _zz_556) == 32'h0); - assign _zz_550 = {(_zz_557 == _zz_558),{_zz_559,_zz_560}}; - assign _zz_551 = ((decode_INSTRUCTION & _zz_561) == 32'h0); - assign _zz_552 = 1'b0; - assign _zz_553 = ({_zz_562,{_zz_563,_zz_564}} != 3'b000); - assign _zz_554 = ({_zz_565,_zz_566} != 2'b00); - assign _zz_555 = {(_zz_567 != _zz_568),(_zz_569 != _zz_570)}; - assign _zz_556 = 32'h00000044; - assign _zz_557 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_558 = 32'h0; - assign _zz_559 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_560 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_561 = 32'h00000058; - assign _zz_562 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_563 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); - assign _zz_564 = ((decode_INSTRUCTION & _zz_572) == 32'h40000030); - assign _zz_565 = ((decode_INSTRUCTION & _zz_573) == 32'h00000004); - assign _zz_566 = _zz_94; - assign _zz_567 = {(_zz_574 == _zz_575),_zz_94}; - assign _zz_568 = 2'b00; - assign _zz_569 = ((decode_INSTRUCTION & _zz_576) == 32'h00001004); - assign _zz_570 = 1'b0; - assign _zz_571 = 32'h00002014; - assign _zz_572 = 32'h40000034; - assign _zz_573 = 32'h00000014; - assign _zz_574 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_575 = 32'h00000004; - assign _zz_576 = 32'h00005054; - assign _zz_577 = execute_INSTRUCTION[31]; - assign _zz_578 = execute_INSTRUCTION[31]; - assign _zz_579 = execute_INSTRUCTION[7]; - assign _zz_580 = 32'h0; - always @ (posedge clk) begin - if(_zz_385) begin - _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_386) begin - _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_48) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h00203050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00002040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79}} != 6'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00002040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h00001040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75) == 32'h00000008); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = 6'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = (decode_INSTRUCTION & 32'h00400040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = 32'h00000008; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = 32'h00004020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85) == 32'h00000010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h00002030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98) == 32'h00002020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129) == 32'h00004010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139} != 4'b0000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = 32'h00000030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h02000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = 32'h02002060; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02003020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = 32'h00004014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = 32'h00000044; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00000058; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h40000030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165) == 32'h00001004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = 32'h00002014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h40000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 32'h00000014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = 32'h00000004; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 32'h00005054; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_41 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_217 ), //i - .io_cpu_prefetch_isValid (_zz_218 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_219 ), //i - .io_cpu_fetch_isStuck (_zz_220 ), //i - .io_cpu_fetch_isRemoved (_zz_221 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_222 ), //i - .io_cpu_decode_isStuck (_zz_223 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_224 ), //i - .io_cpu_fill_valid (_zz_225 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_226 ), //i - .io_cpu_execute_address (_zz_227[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_88[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_228 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_229[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_230 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_231 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_232 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_233[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_234 ), //i - .io_cpu_writeBack_fence_SR (_zz_235 ), //i - .io_cpu_writeBack_fence_SO (_zz_236 ), //i - .io_cpu_writeBack_fence_SI (_zz_237 ), //i - .io_cpu_writeBack_fence_PW (_zz_238 ), //i - .io_cpu_writeBack_fence_PR (_zz_239 ), //i - .io_cpu_writeBack_fence_PO (_zz_240 ), //i - .io_cpu_writeBack_fence_PI (_zz_241 ), //i - .io_cpu_writeBack_fence_FM (_zz_242[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_243 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_244 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_387) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) 2'b00 : begin - _zz_247 = DBusCachedPlugin_redoBranch_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_247 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_247 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + end + 2'b01 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + end + 2'b10 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; end default : begin - _zz_247 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end @@ -1852,808 +1972,825 @@ module VexRiscv ( `ifndef SYNTHESIS always @(*) begin case(decode_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_1) - `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; - default : _zz_1_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; - default : _zz_2_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; - default : _zz_3_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; - default : _zz_8_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_9) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; - default : _zz_9_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_10) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; - default : _zz_10_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_11) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; - default : _zz_11_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_12) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; - default : _zz_12_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_16) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; - default : _zz_16_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_17) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; - default : _zz_17_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_19) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; - default : _zz_19_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_20) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; - default : _zz_20_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_25) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; - default : _zz_25_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_26) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; - default : _zz_26_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_28) - `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; - default : _zz_28_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_29) - `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; - default : _zz_29_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_32) - `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; - default : _zz_32_string = "?????"; + case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_36) - `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; - default : _zz_36_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_39) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; - default : _zz_39_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_40) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; - default : _zz_40_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_42) - `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; - default : _zz_42_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_43) - `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; - default : _zz_43_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_44) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; - default : _zz_44_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_45) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; - default : _zz_45_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_49) - `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; - default : _zz_49_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_50) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; - default : _zz_50_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_52) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; - default : _zz_52_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_53) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; - default : _zz_53_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_54) - `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; - default : _zz_54_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_55) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; - default : _zz_55_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_56) - `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; - default : _zz_56_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_58) - `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; - default : _zz_58_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_99) - `Src1CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_99_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99_string = "URS1 "; - default : _zz_99_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_100) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_100_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_100_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_100_string = "BITWISE "; - default : _zz_100_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_101) - `Src2CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_101_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_101_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_101_string = "PC "; - default : _zz_101_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_102) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_102_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_102_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_102_string = "AND_1"; - default : _zz_102_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_103) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_103_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_103_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_103_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_103_string = "SRA_1 "; - default : _zz_103_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_104) - `BranchCtrlEnum_defaultEncoding_INC : _zz_104_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_104_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_104_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_104_string = "JALR"; - default : _zz_104_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_105) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_105_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_105_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_105_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_105_string = "ECALL"; - default : _zz_105_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_106) - `Input2Kind_defaultEncoding_RS : _zz_106_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_106_string = "IMM_I"; - default : _zz_106_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_297; - assign execute_REGFILE_WRITE_DATA = _zz_108; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_227[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_299[0]; - assign decode_IS_RS1_SIGNED = _zz_300[0]; - assign decode_IS_DIV = _zz_301[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32]; + assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30]; + assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_302[0]; - assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; - assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; - assign _zz_4 = _zz_5; - assign _zz_6 = _zz_7; - assign decode_ENV_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_304[0]; - assign _zz_11 = _zz_12; - assign _zz_13 = _zz_14; - assign decode_SHIFT_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_ALU_BITWISE_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; - assign decode_MEMORY_MANAGMENT = _zz_306[0]; + assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_307[0]; + assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; - assign decode_SRC2_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_ALU_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_SRC1_CTRL = _zz_27; - assign _zz_28 = _zz_29; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; + always @(*) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + always @(*) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2664,42 +2801,25 @@ module VexRiscv ( assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; - always @ (*) begin - _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; - if(memory_arbitration_isStuck)begin - _zz_30 = 1'b0; - end - end - - always @ (*) begin - _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; - if(execute_arbitration_isStuck)begin - _zz_31 = 1'b0; - end - end - - assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33; - assign execute_ENV_CTRL = _zz_34; - assign writeBack_ENV_CTRL = _zz_35; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_130; - assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_310[0]; - assign decode_RS1_USE = _zz_311[0]; - always @ (*) begin - _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_248)begin - _zz_37 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15]; + assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2709,142 +2829,142 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_119)begin - if((_zz_120 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_121; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_123)begin - decode_RS2 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_251)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin - decode_RS2 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_252)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin - decode_RS2 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_119)begin - if((_zz_120 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_121; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_122)begin - decode_RS1 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_251)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_124)begin - decode_RS1 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_252)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_126)begin - decode_RS1 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_38 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_116; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_38 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end - if(_zz_253)begin - _zz_38 = memory_DivPlugin_div_result; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + _zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0; end end - assign memory_SHIFT_CTRL = _zz_39; - assign execute_SHIFT_CTRL = _zz_40; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_41 = execute_PC; - assign execute_SRC2_CTRL = _zz_42; - assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_312[0]; - assign decode_SRC_ADD_ZERO = _zz_313[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_114; - assign execute_SRC1 = _zz_109; - assign execute_ALU_BITWISE_CTRL = _zz_45; - assign _zz_46 = writeBack_INSTRUCTION; - assign _zz_47 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_48 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_48 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_314[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}} != 22'h0); - always @ (*) begin - _zz_57 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_286) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_57 = _zz_360; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_57 = _zz_361; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2856,214 +2976,205 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_315[0]; - assign decode_FLUSH_ALL = _zz_316[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4]; + assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_254)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_255)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_256)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_257)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_58; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_59 = execute_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_59 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_60 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_117 || _zz_118)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_258)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_258)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_243 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_259)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_248)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end - if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + if(when_CfuPlugin_l175) begin execute_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_260)begin + if(_zz_when_1) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_260)begin + if(_zz_when_1) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if((! memory_CfuPlugin_rsp_valid))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_253)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + if(when_CfuPlugin_l208) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushNext = 1'b0; + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_262)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3072,51 +3183,53 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_262)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_259)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_262)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_261)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_262)begin - case(_zz_263) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3129,59 +3242,65 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_62 = (_zz_61 & (~ _zz_317)); - assign _zz_63 = _zz_62[3]; - assign _zz_64 = (_zz_62[1] || _zz_63); - assign _zz_65 = (_zz_62[2] || _zz_63); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_319); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3189,265 +3308,286 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_66); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_66); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_67); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_68); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_68); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_69; - assign _zz_69 = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_70 = _zz_71; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_72)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_72 = _zz_73; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_74; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_75 = _zz_320[11]; - always @ (*) begin - _zz_76[18] = _zz_75; - _zz_76[17] = _zz_75; - _zz_76[16] = _zz_75; - _zz_76[15] = _zz_75; - _zz_76[14] = _zz_75; - _zz_76[13] = _zz_75; - _zz_76[12] = _zz_75; - _zz_76[11] = _zz_75; - _zz_76[10] = _zz_75; - _zz_76[9] = _zz_75; - _zz_76[8] = _zz_75; - _zz_76[7] = _zz_75; - _zz_76[6] = _zz_75; - _zz_76[5] = _zz_75; - _zz_76[4] = _zz_75; - _zz_76[3] = _zz_75; - _zz_76[2] = _zz_75; - _zz_76[1] = _zz_75; - _zz_76[0] = _zz_75; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_321[31])); - if(_zz_81)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_77 = _zz_322[19]; - always @ (*) begin - _zz_78[10] = _zz_77; - _zz_78[9] = _zz_77; - _zz_78[8] = _zz_77; - _zz_78[7] = _zz_77; - _zz_78[6] = _zz_77; - _zz_78[5] = _zz_77; - _zz_78[4] = _zz_77; - _zz_78[3] = _zz_77; - _zz_78[2] = _zz_77; - _zz_78[1] = _zz_77; - _zz_78[0] = _zz_77; - end - - assign _zz_79 = _zz_323[11]; - always @ (*) begin - _zz_80[18] = _zz_79; - _zz_80[17] = _zz_79; - _zz_80[16] = _zz_79; - _zz_80[15] = _zz_79; - _zz_80[14] = _zz_79; - _zz_80[13] = _zz_79; - _zz_80[12] = _zz_79; - _zz_80[11] = _zz_79; - _zz_80[10] = _zz_79; - _zz_80[9] = _zz_79; - _zz_80[8] = _zz_79; - _zz_80[7] = _zz_79; - _zz_80[6] = _zz_79; - _zz_80[5] = _zz_79; - _zz_80[4] = _zz_79; - _zz_80[3] = _zz_79; - _zz_80[2] = _zz_79; - _zz_80[1] = _zz_79; - _zz_80[0] = _zz_79; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_81 = _zz_324[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_81 = _zz_325[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_82 = _zz_326[19]; - always @ (*) begin - _zz_83[10] = _zz_82; - _zz_83[9] = _zz_82; - _zz_83[8] = _zz_82; - _zz_83[7] = _zz_82; - _zz_83[6] = _zz_82; - _zz_83[5] = _zz_82; - _zz_83[4] = _zz_82; - _zz_83[3] = _zz_82; - _zz_83[2] = _zz_82; - _zz_83[1] = _zz_82; - _zz_83[0] = _zz_82; - end - - assign _zz_84 = _zz_327[11]; - always @ (*) begin - _zz_85[18] = _zz_84; - _zz_85[17] = _zz_84; - _zz_85[16] = _zz_84; - _zz_85[15] = _zz_84; - _zz_85[14] = _zz_84; - _zz_85[13] = _zz_84; - _zz_85[12] = _zz_84; - _zz_85[11] = _zz_84; - _zz_85[10] = _zz_84; - _zz_85[9] = _zz_84; - _zz_85[8] = _zz_84; - _zz_85[7] = _zz_84; - _zz_85[6] = _zz_84; - _zz_85[5] = _zz_84; - _zz_85[4] = _zz_84; - _zz_85[3] = _zz_84; - _zz_85[2] = _zz_84; - _zz_85[1] = _zz_84; - _zz_85[0] = _zz_84; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_406,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_407,_zz_408},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_219; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_224 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_257)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_255)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_225 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_255)begin - _zz_225 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_256)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_254)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_256)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_254)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_217 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_244 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3455,168 +3595,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_227 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_88 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_88 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_88 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_243 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_228 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_229 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_228; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_229; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_230 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_230 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_232 = (CsrPlugin_privilege == 2'b00); - assign _zz_233 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_264)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_264)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_264)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; end - assign _zz_89 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_90[31] = _zz_89; - _zz_90[30] = _zz_89; - _zz_90[29] = _zz_89; - _zz_90[28] = _zz_89; - _zz_90[27] = _zz_89; - _zz_90[26] = _zz_89; - _zz_90[25] = _zz_89; - _zz_90[24] = _zz_89; - _zz_90[23] = _zz_89; - _zz_90[22] = _zz_89; - _zz_90[21] = _zz_89; - _zz_90[20] = _zz_89; - _zz_90[19] = _zz_89; - _zz_90[18] = _zz_89; - _zz_90[17] = _zz_89; - _zz_90[16] = _zz_89; - _zz_90[15] = _zz_89; - _zz_90[14] = _zz_89; - _zz_90[13] = _zz_89; - _zz_90[12] = _zz_89; - _zz_90[11] = _zz_89; - _zz_90[10] = _zz_89; - _zz_90[9] = _zz_89; - _zz_90[8] = _zz_89; - _zz_90[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_91 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_92[31] = _zz_91; - _zz_92[30] = _zz_91; - _zz_92[29] = _zz_91; - _zz_92[28] = _zz_91; - _zz_92[27] = _zz_91; - _zz_92[26] = _zz_91; - _zz_92[25] = _zz_91; - _zz_92[24] = _zz_91; - _zz_92[23] = _zz_91; - _zz_92[22] = _zz_91; - _zz_92[21] = _zz_91; - _zz_92[20] = _zz_91; - _zz_92[19] = _zz_91; - _zz_92[18] = _zz_91; - _zz_92[17] = _zz_91; - _zz_92[16] = _zz_91; - _zz_92[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_284) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_90; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_92; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3635,62 +3786,63 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_94 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_95 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_409 == _zz_410) != 1'b0),{(_zz_411 != 1'b0),{1'b0,{_zz_412,{_zz_413,_zz_414}}}}}}}; - assign _zz_99 = _zz_93[2 : 1]; - assign _zz_56 = _zz_99; - assign _zz_100 = _zz_93[7 : 6]; - assign _zz_55 = _zz_100; - assign _zz_101 = _zz_93[9 : 8]; - assign _zz_54 = _zz_101; - assign _zz_102 = _zz_93[19 : 18]; - assign _zz_53 = _zz_102; - assign _zz_103 = _zz_93[22 : 21]; - assign _zz_52 = _zz_103; - assign _zz_104 = _zz_93[24 : 23]; - assign _zz_51 = _zz_104; - assign _zz_105 = _zz_93[27 : 26]; - assign _zz_50 = _zz_105; - assign _zz_106 = _zz_93[29 : 29]; - assign _zz_49 = _zz_106; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33]; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_245; - assign decode_RegFilePlugin_rs2Data = _zz_246; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_107)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_107)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_107)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3699,355 +3851,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_108 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_108 = {31'd0, _zz_330}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_108 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_109 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_109 = {29'd0, _zz_331}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_109 = {27'd0, _zz_332}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_110 = _zz_333[11]; - always @ (*) begin - _zz_111[19] = _zz_110; - _zz_111[18] = _zz_110; - _zz_111[17] = _zz_110; - _zz_111[16] = _zz_110; - _zz_111[15] = _zz_110; - _zz_111[14] = _zz_110; - _zz_111[13] = _zz_110; - _zz_111[12] = _zz_110; - _zz_111[11] = _zz_110; - _zz_111[10] = _zz_110; - _zz_111[9] = _zz_110; - _zz_111[8] = _zz_110; - _zz_111[7] = _zz_110; - _zz_111[6] = _zz_110; - _zz_111[5] = _zz_110; - _zz_111[4] = _zz_110; - _zz_111[3] = _zz_110; - _zz_111[2] = _zz_110; - _zz_111[1] = _zz_110; - _zz_111[0] = _zz_110; - end - - assign _zz_112 = _zz_334[11]; - always @ (*) begin - _zz_113[19] = _zz_112; - _zz_113[18] = _zz_112; - _zz_113[17] = _zz_112; - _zz_113[16] = _zz_112; - _zz_113[15] = _zz_112; - _zz_113[14] = _zz_112; - _zz_113[13] = _zz_112; - _zz_113[12] = _zz_112; - _zz_113[11] = _zz_112; - _zz_113[10] = _zz_112; - _zz_113[9] = _zz_112; - _zz_113[8] = _zz_112; - _zz_113[7] = _zz_112; - _zz_113[6] = _zz_112; - _zz_113[5] = _zz_112; - _zz_113[4] = _zz_112; - _zz_113[3] = _zz_112; - _zz_113[2] = _zz_112; - _zz_113[1] = _zz_112; - _zz_113[0] = _zz_112; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_114 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_114 = {_zz_111,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_114 = {_zz_113,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_114 = _zz_41; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_335; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_115[0] = execute_SRC1[31]; - _zz_115[1] = execute_SRC1[30]; - _zz_115[2] = execute_SRC1[29]; - _zz_115[3] = execute_SRC1[28]; - _zz_115[4] = execute_SRC1[27]; - _zz_115[5] = execute_SRC1[26]; - _zz_115[6] = execute_SRC1[25]; - _zz_115[7] = execute_SRC1[24]; - _zz_115[8] = execute_SRC1[23]; - _zz_115[9] = execute_SRC1[22]; - _zz_115[10] = execute_SRC1[21]; - _zz_115[11] = execute_SRC1[20]; - _zz_115[12] = execute_SRC1[19]; - _zz_115[13] = execute_SRC1[18]; - _zz_115[14] = execute_SRC1[17]; - _zz_115[15] = execute_SRC1[16]; - _zz_115[16] = execute_SRC1[15]; - _zz_115[17] = execute_SRC1[14]; - _zz_115[18] = execute_SRC1[13]; - _zz_115[19] = execute_SRC1[12]; - _zz_115[20] = execute_SRC1[11]; - _zz_115[21] = execute_SRC1[10]; - _zz_115[22] = execute_SRC1[9]; - _zz_115[23] = execute_SRC1[8]; - _zz_115[24] = execute_SRC1[7]; - _zz_115[25] = execute_SRC1[6]; - _zz_115[26] = execute_SRC1[5]; - _zz_115[27] = execute_SRC1[4]; - _zz_115[28] = execute_SRC1[3]; - _zz_115[29] = execute_SRC1[2]; - _zz_115[30] = execute_SRC1[1]; - _zz_115[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_115 : execute_SRC1); - always @ (*) begin - _zz_116[0] = memory_SHIFT_RIGHT[31]; - _zz_116[1] = memory_SHIFT_RIGHT[30]; - _zz_116[2] = memory_SHIFT_RIGHT[29]; - _zz_116[3] = memory_SHIFT_RIGHT[28]; - _zz_116[4] = memory_SHIFT_RIGHT[27]; - _zz_116[5] = memory_SHIFT_RIGHT[26]; - _zz_116[6] = memory_SHIFT_RIGHT[25]; - _zz_116[7] = memory_SHIFT_RIGHT[24]; - _zz_116[8] = memory_SHIFT_RIGHT[23]; - _zz_116[9] = memory_SHIFT_RIGHT[22]; - _zz_116[10] = memory_SHIFT_RIGHT[21]; - _zz_116[11] = memory_SHIFT_RIGHT[20]; - _zz_116[12] = memory_SHIFT_RIGHT[19]; - _zz_116[13] = memory_SHIFT_RIGHT[18]; - _zz_116[14] = memory_SHIFT_RIGHT[17]; - _zz_116[15] = memory_SHIFT_RIGHT[16]; - _zz_116[16] = memory_SHIFT_RIGHT[15]; - _zz_116[17] = memory_SHIFT_RIGHT[14]; - _zz_116[18] = memory_SHIFT_RIGHT[13]; - _zz_116[19] = memory_SHIFT_RIGHT[12]; - _zz_116[20] = memory_SHIFT_RIGHT[11]; - _zz_116[21] = memory_SHIFT_RIGHT[10]; - _zz_116[22] = memory_SHIFT_RIGHT[9]; - _zz_116[23] = memory_SHIFT_RIGHT[8]; - _zz_116[24] = memory_SHIFT_RIGHT[7]; - _zz_116[25] = memory_SHIFT_RIGHT[6]; - _zz_116[26] = memory_SHIFT_RIGHT[5]; - _zz_116[27] = memory_SHIFT_RIGHT[4]; - _zz_116[28] = memory_SHIFT_RIGHT[3]; - _zz_116[29] = memory_SHIFT_RIGHT[2]; - _zz_116[30] = memory_SHIFT_RIGHT[1]; - _zz_116[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_117 = 1'b0; - if(_zz_265)begin - if(_zz_266)begin - if(_zz_122)begin - _zz_117 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_267)begin - if(_zz_268)begin - if(_zz_124)begin - _zz_117 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_269)begin - if(_zz_270)begin - if(_zz_126)begin - _zz_117 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_117 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_118 = 1'b0; - if(_zz_265)begin - if(_zz_266)begin - if(_zz_123)begin - _zz_118 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_267)begin - if(_zz_268)begin - if(_zz_125)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_269)begin - if(_zz_270)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_118 = 1'b0; - end - end - - assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_128 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_128 == 3'b000)) begin - _zz_129 = execute_BranchPlugin_eq; - end else if((_zz_128 == 3'b001)) begin - _zz_129 = (! execute_BranchPlugin_eq); - end else if((((_zz_128 & 3'b101) == 3'b101))) begin - _zz_129 = (! execute_SRC_LESS); - end else begin - _zz_129 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_130 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_130 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_130 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_130 = _zz_129; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_131 = _zz_342[11]; - always @ (*) begin - _zz_132[19] = _zz_131; - _zz_132[18] = _zz_131; - _zz_132[17] = _zz_131; - _zz_132[16] = _zz_131; - _zz_132[15] = _zz_131; - _zz_132[14] = _zz_131; - _zz_132[13] = _zz_131; - _zz_132[12] = _zz_131; - _zz_132[11] = _zz_131; - _zz_132[10] = _zz_131; - _zz_132[9] = _zz_131; - _zz_132[8] = _zz_131; - _zz_132[7] = _zz_131; - _zz_132[6] = _zz_131; - _zz_132[5] = _zz_131; - _zz_132[4] = _zz_131; - _zz_132[3] = _zz_131; - _zz_132[2] = _zz_131; - _zz_132[1] = _zz_131; - _zz_132[0] = _zz_131; - end - - assign _zz_133 = _zz_343[19]; - always @ (*) begin - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; - end - - assign _zz_135 = _zz_344[11]; - always @ (*) begin - _zz_136[18] = _zz_135; - _zz_136[17] = _zz_135; - _zz_136[16] = _zz_135; - _zz_136[15] = _zz_135; - _zz_136[14] = _zz_135; - _zz_136[13] = _zz_135; - _zz_136[12] = _zz_135; - _zz_136[11] = _zz_135; - _zz_136[10] = _zz_135; - _zz_136[9] = _zz_135; - _zz_136[8] = _zz_135; - _zz_136[7] = _zz_135; - _zz_136[6] = _zz_135; - _zz_136[5] = _zz_135; - _zz_136[4] = _zz_135; - _zz_136[3] = _zz_135; - _zz_136[2] = _zz_135; - _zz_136[1] = _zz_135; - _zz_136[0] = _zz_135; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_137 = (_zz_345[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_137 = _zz_346[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_137 = _zz_347[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_137); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -4056,183 +4231,195 @@ module VexRiscv ( endcase end - assign _zz_138 = _zz_348[11]; - always @ (*) begin - _zz_139[19] = _zz_138; - _zz_139[18] = _zz_138; - _zz_139[17] = _zz_138; - _zz_139[16] = _zz_138; - _zz_139[15] = _zz_138; - _zz_139[14] = _zz_138; - _zz_139[13] = _zz_138; - _zz_139[12] = _zz_138; - _zz_139[11] = _zz_138; - _zz_139[10] = _zz_138; - _zz_139[9] = _zz_138; - _zz_139[8] = _zz_138; - _zz_139[7] = _zz_138; - _zz_139[6] = _zz_138; - _zz_139[5] = _zz_138; - _zz_139[4] = _zz_138; - _zz_139[3] = _zz_138; - _zz_139[2] = _zz_138; - _zz_139[1] = _zz_138; - _zz_139[0] = _zz_138; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_577,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_578,_zz_579},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_351}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_140 = _zz_349[19]; - always @ (*) begin - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; - end - - assign _zz_142 = _zz_350[11]; - always @ (*) begin - _zz_143[18] = _zz_142; - _zz_143[17] = _zz_142; - _zz_143[16] = _zz_142; - _zz_143[15] = _zz_142; - _zz_143[14] = _zz_142; - _zz_143[13] = _zz_142; - _zz_143[12] = _zz_142; - _zz_143[11] = _zz_142; - _zz_143[10] = _zz_142; - _zz_143[9] = _zz_142; - _zz_143[8] = _zz_142; - _zz_143[7] = _zz_142; - _zz_143[6] = _zz_142; - _zz_143[5] = _zz_142; - _zz_143[4] = _zz_142; - _zz_143[3] = _zz_142; - _zz_143[2] = _zz_142; - _zz_143[1] = _zz_142; - _zz_143[0] = _zz_142; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; - always @ (*) begin + always @(*) begin BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); - if(1'b0)begin + if(when_BranchPlugin_l296) begin BranchPlugin_branchExceptionPort_valid = 1'b0; end end assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign when_BranchPlugin_l296 = 1'b0; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_144 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_145 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_146 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_148 = _zz_352[0]; - assign _zz_149 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_150 = _zz_354[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_258)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_260)begin + if(_zz_when_1) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4243,8 +4430,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4254,199 +4441,208 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_csr_2820) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2821) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_csr_2822) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2823) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_csr_2824) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2825) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_csr_2826) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2827) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_csr_2828) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2829) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_csr_2830) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2831) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_csr_2832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2833) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_2834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_2835) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_271)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_272)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_273)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_272)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_273)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4459,106 +4655,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_271)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_271)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_285) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); - assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_356; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; - assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_167 = _zz_357[7]; - always @ (*) begin - _zz_168[23] = _zz_167; - _zz_168[22] = _zz_167; - _zz_168[21] = _zz_167; - _zz_168[20] = _zz_167; - _zz_168[19] = _zz_167; - _zz_168[18] = _zz_167; - _zz_168[17] = _zz_167; - _zz_168[16] = _zz_167; - _zz_168[15] = _zz_167; - _zz_168[14] = _zz_167; - _zz_168[13] = _zz_167; - _zz_168[12] = _zz_167; - _zz_168[11] = _zz_167; - _zz_168[10] = _zz_167; - _zz_168[9] = _zz_167; - _zz_168[8] = _zz_167; - _zz_168[7] = _zz_167; - _zz_168[6] = _zz_167; - _zz_168[5] = _zz_167; - _zz_168[4] = _zz_167; - _zz_168[3] = _zz_167; - _zz_168[2] = _zz_167; - _zz_168[1] = _zz_167; - _zz_168[0] = _zz_167; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : begin - _zz_169 = execute_RS2; - end - default : begin - _zz_169 = {_zz_168,execute_INSTRUCTION[31 : 24]}; - end - endcase - end - - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_169; - assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); - assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); - assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); - assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); - always @ (*) begin - CfuPlugin_joinException_valid = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if(memory_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); - end - end - end - - assign CfuPlugin_joinException_payload_code = 4'b1111; - assign CfuPlugin_joinException_payload_badAddr = 32'h0; - always @ (*) begin - memory_CfuPlugin_rsp_ready = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); - end - end - assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_274) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4571,8 +4710,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_274) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4591,82 +4730,222 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_358) + $signed(_zz_359)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_253)begin - if(_zz_275)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_276)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_363); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_170 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_170[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_364); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_365 : _zz_366); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_367[31:0]; - assign _zz_171 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_172 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_173 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_174[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_174[31 : 0] = execute_RS1; - end - - assign _zz_176 = (_zz_175 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_176 != 32'h0); - assign _zz_29 = decode_SRC1_CTRL; - assign _zz_27 = _zz_56; - assign _zz_43 = decode_to_execute_SRC1_CTRL; - assign _zz_26 = decode_ALU_CTRL; - assign _zz_24 = _zz_55; - assign _zz_44 = decode_to_execute_ALU_CTRL; - assign _zz_23 = decode_SRC2_CTRL; - assign _zz_21 = _zz_54; - assign _zz_42 = decode_to_execute_SRC2_CTRL; - assign _zz_20 = decode_ALU_BITWISE_CTRL; - assign _zz_18 = _zz_53; - assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_17 = decode_SHIFT_CTRL; - assign _zz_14 = execute_SHIFT_CTRL; - assign _zz_15 = _zz_52; - assign _zz_40 = decode_to_execute_SHIFT_CTRL; - assign _zz_39 = execute_to_memory_SHIFT_CTRL; - assign _zz_12 = decode_BRANCH_CTRL; - assign _zz_58 = _zz_51; - assign _zz_36 = decode_to_execute_BRANCH_CTRL; - assign _zz_10 = decode_ENV_CTRL; - assign _zz_7 = execute_ENV_CTRL; - assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_50; - assign _zz_34 = decode_to_execute_ENV_CTRL; - assign _zz_33 = execute_to_memory_ENV_CTRL; - assign _zz_35 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_49; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready); + assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)); + assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + end + + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2; + end + default : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @(*) begin + CfuPlugin_bus_rsp_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); + assign when_GenCoreDefault_l367 = _zz_when_GenCoreDefault_l367[0]; + assign when_GenCoreDefault_l367_1 = _zz_when_GenCoreDefault_l367_1[0]; + assign when_GenCoreDefault_l367_2 = _zz_when_GenCoreDefault_l367_2[0]; + assign when_GenCoreDefault_l367_3 = _zz_when_GenCoreDefault_l367_3[0]; + assign when_GenCoreDefault_l367_4 = _zz_when_GenCoreDefault_l367_4[0]; + assign when_GenCoreDefault_l367_5 = _zz_when_GenCoreDefault_l367_5[0]; + assign when_GenCoreDefault_l367_6 = _zz_when_GenCoreDefault_l367_6[0]; + assign when_GenCoreDefault_l367_7 = _zz_when_GenCoreDefault_l367_7[0]; + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4687,296 +4966,345 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_177 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_177[12 : 0] = 13'h1000; - _zz_177[25 : 20] = 6'h20; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_28 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_29 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_30 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_31 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_32 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_33 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_34 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_35 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_36 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_37 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_38 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_39 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[13 : 0] = 14'h2000; + _zz_CsrPlugin_csrMapping_readDataInit_10[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_178 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_178[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_179 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_179[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_180[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_181[31 : 30] = CsrPlugin_misa_base; - _zz_181[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_14[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_182[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_182[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_182[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_15[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_183[11 : 11] = CsrPlugin_mip_MEIP; - _zz_183[7 : 7] = CsrPlugin_mip_MTIP; - _zz_183[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_184[11 : 11] = CsrPlugin_mie_MEIE; - _zz_184[7 : 7] = CsrPlugin_mie_MTIE; - _zz_184[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_185[31 : 2] = CsrPlugin_mtvec_base; - _zz_185[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_186 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_186[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_187 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_187[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_188 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_188[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_188[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_21[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_189 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_189[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_190 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_191 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_192 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_193 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_194 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_195 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_28[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_196 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_29 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_29[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_197 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_30 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_30[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_198 = 32'h0; - if(execute_CsrPlugin_csr_2820)begin - _zz_198[31 : 0] = _zz_151; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_31 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_31[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_199 = 32'h0; - if(execute_CsrPlugin_csr_2822)begin - _zz_199[31 : 0] = _zz_153; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_32 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_32[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - always @ (*) begin - _zz_200 = 32'h0; - if(execute_CsrPlugin_csr_2824)begin - _zz_200[31 : 0] = _zz_155; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_33 = 32'h0; + if(execute_CsrPlugin_csr_2820) begin + _zz_CsrPlugin_csrMapping_readDataInit_33[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; end end - always @ (*) begin - _zz_201 = 32'h0; - if(execute_CsrPlugin_csr_2826)begin - _zz_201[31 : 0] = _zz_157; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_34 = 32'h0; + if(execute_CsrPlugin_csr_2822) begin + _zz_CsrPlugin_csrMapping_readDataInit_34[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; end end - always @ (*) begin - _zz_202 = 32'h0; - if(execute_CsrPlugin_csr_2828)begin - _zz_202[31 : 0] = _zz_159; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_35 = 32'h0; + if(execute_CsrPlugin_csr_2824) begin + _zz_CsrPlugin_csrMapping_readDataInit_35[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_4; end end - always @ (*) begin - _zz_203 = 32'h0; - if(execute_CsrPlugin_csr_2830)begin - _zz_203[31 : 0] = _zz_161; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_36 = 32'h0; + if(execute_CsrPlugin_csr_2826) begin + _zz_CsrPlugin_csrMapping_readDataInit_36[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_5; end end - always @ (*) begin - _zz_204 = 32'h0; - if(execute_CsrPlugin_csr_2832)begin - _zz_204[31 : 0] = _zz_163; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_37 = 32'h0; + if(execute_CsrPlugin_csr_2828) begin + _zz_CsrPlugin_csrMapping_readDataInit_37[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_6; end end - always @ (*) begin - _zz_205 = 32'h0; - if(execute_CsrPlugin_csr_2834)begin - _zz_205[31 : 0] = _zz_165; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_38 = 32'h0; + if(execute_CsrPlugin_csr_2830) begin + _zz_CsrPlugin_csrMapping_readDataInit_38[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_7; end end - always @ (*) begin - _zz_206 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_206[31 : 0] = _zz_175; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_39 = 32'h0; + if(execute_CsrPlugin_csr_2832) begin + _zz_CsrPlugin_csrMapping_readDataInit_39[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_8; end end - always @ (*) begin - _zz_207 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_207[31 : 0] = _zz_176; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_40 = 32'h0; + if(execute_CsrPlugin_csr_2834) begin + _zz_CsrPlugin_csrMapping_readDataInit_40[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_9; end end - assign execute_CsrPlugin_readData = (((((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_580 | _zz_181) | (_zz_182 | _zz_183))) | (((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191)))) | ((((_zz_192 | _zz_193) | (_zz_194 | _zz_195)) | ((_zz_196 | _zz_197) | (_zz_198 | _zz_199))) | (((_zz_200 | _zz_201) | (_zz_202 | _zz_203)) | ((_zz_204 | _zz_205) | (_zz_206 | _zz_207))))); - assign iBusWishbone_ADR = {_zz_384,_zz_208}; - assign iBusWishbone_CTI = ((_zz_208 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | (_zz_CsrPlugin_csrMapping_readDataInit_12 | _zz_CsrPlugin_csrMapping_readDataInit_13)) | ((_zz_CsrPlugin_csrMapping_readDataInit_41 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26) | (_zz_CsrPlugin_csrMapping_readDataInit_27 | _zz_CsrPlugin_csrMapping_readDataInit_28)) | ((_zz_CsrPlugin_csrMapping_readDataInit_29 | _zz_CsrPlugin_csrMapping_readDataInit_30) | (_zz_CsrPlugin_csrMapping_readDataInit_31 | _zz_CsrPlugin_csrMapping_readDataInit_32))) | (((_zz_CsrPlugin_csrMapping_readDataInit_33 | _zz_CsrPlugin_csrMapping_readDataInit_34) | (_zz_CsrPlugin_csrMapping_readDataInit_35 | _zz_CsrPlugin_csrMapping_readDataInit_36)) | ((_zz_CsrPlugin_csrMapping_readDataInit_37 | _zz_CsrPlugin_csrMapping_readDataInit_38) | (_zz_CsrPlugin_csrMapping_readDataInit_39 | _zz_CsrPlugin_csrMapping_readDataInit_40))))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_277)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_277)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_209; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_215 = (dBus_cmd_payload_length != 3'b000); - assign _zz_211 = dBus_cmd_valid; - assign _zz_213 = dBus_cmd_payload_wr; - assign _zz_214 = (_zz_210 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_212 && (_zz_213 || _zz_214)); - assign dBusWishbone_ADR = ((_zz_215 ? {{dBus_cmd_payload_address[31 : 5],_zz_210},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_215 ? (_zz_214 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_213 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_213; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_212 = (_zz_211 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_211; - assign dBusWishbone_STB = _zz_211; - assign dBus_rsp_valid = _zz_216; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_71 <= 1'b0; - _zz_73 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_86; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_87; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_107 <= 1'b1; - _zz_119 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4996,164 +5324,164 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - memory_DivPlugin_div_counter_value <= 6'h0; - _zz_175 <= 32'h0; + CfuPlugin_bus_rsp_rValid <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_208 <= 3'b000; - _zz_209 <= 1'b0; - _zz_210 <= 3'b000; - _zz_216 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_71 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_69)begin - _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_73 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_73 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_278)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_107 <= 1'b0; - _zz_119 <= (_zz_47 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_279)begin - if(_zz_280)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_281)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_282)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5164,8 +5492,8 @@ module VexRiscv ( end endcase end - if(_zz_262)begin - case(_zz_263) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5175,162 +5503,158 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_146,{_zz_145,_zz_144}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(execute_CfuPlugin_schedule)begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(execute_CfuPlugin_schedule) begin execute_CfuPlugin_hold <= 1'b1; end - if(CfuPlugin_bus_cmd_ready)begin + if(CfuPlugin_bus_cmd_ready) begin execute_CfuPlugin_hold <= 1'b0; end - if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + if(CfuPlugin_bus_cmd_fire) begin execute_CfuPlugin_fired <= 1'b1; end - if((! execute_arbitration_isStuckByOthers))begin + if(when_CfuPlugin_l171) begin execute_CfuPlugin_fired <= 1'b0; end - if(memory_CfuPlugin_rsp_ready)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + if(CfuPlugin_bus_rsp_valid) begin + CfuPlugin_bus_rsp_rValid <= 1'b1; end - if(_zz_283)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + if(CfuPlugin_bus_rsp_rsp_ready) begin + CfuPlugin_bus_rsp_rValid <= 1'b0; end - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + if(when_Pipeline_l124_61) begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_377[0]; - CsrPlugin_mstatus_MIE <= _zz_378[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_380[0]; - CsrPlugin_mie_MTIE <= _zz_381[0]; - CsrPlugin_mie_MSIE <= _zz_382[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_175 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_277)begin - if(iBusWishbone_ACK)begin - _zz_208 <= (_zz_208 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_209 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_211 && _zz_212))begin - _zz_210 <= (_zz_210 + 3'b001); - if(_zz_214)begin - _zz_210 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_216 <= ((_zz_211 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_74 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_278)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_120 <= _zz_46[11 : 7]; - _zz_121 <= _zz_57; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_258)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(_zz_260)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; + if(_zz_when_1) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_279)begin - if(_zz_280)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_281)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_282)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5338,495 +5662,494 @@ module VexRiscv ( end endcase end - if(_zz_152[0])begin - _zz_151 <= (_zz_151 + 32'h00000001); + if(when_MulDivIterativePlugin_l126) begin + memory_DivPlugin_div_done <= 1'b1; end - if(_zz_154[0])begin - _zz_153 <= (_zz_153 + 32'h00000001); + if(when_MulDivIterativePlugin_l126_1) begin + memory_DivPlugin_div_done <= 1'b0; end - if(_zz_156[0])begin - _zz_155 <= (_zz_155 + 32'h00000001); + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; + end + end end - if(_zz_158[0])begin - _zz_157 <= (_zz_157 + 32'h00000001); + if(when_MulDivIterativePlugin_l162) begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end - if(_zz_160[0])begin - _zz_159 <= (_zz_159 + 32'h00000001); + externalInterruptArray_regNext <= externalInterruptArray; + if(CfuPlugin_bus_rsp_ready) begin + CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end - if(_zz_162[0])begin - _zz_161 <= (_zz_161 + 32'h00000001); + if(when_GenCoreDefault_l367) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= (_zz_CsrPlugin_csrMapping_readDataInit_2 + 32'h00000001); end - if(_zz_164[0])begin - _zz_163 <= (_zz_163 + 32'h00000001); + if(when_GenCoreDefault_l367_1) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= (_zz_CsrPlugin_csrMapping_readDataInit_3 + 32'h00000001); end - if(_zz_166[0])begin - _zz_165 <= (_zz_165 + 32'h00000001); + if(when_GenCoreDefault_l367_2) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= (_zz_CsrPlugin_csrMapping_readDataInit_4 + 32'h00000001); end - if(_zz_283)begin - CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + if(when_GenCoreDefault_l367_3) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= (_zz_CsrPlugin_csrMapping_readDataInit_5 + 32'h00000001); end - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_done <= 1'b1; + if(when_GenCoreDefault_l367_4) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= (_zz_CsrPlugin_csrMapping_readDataInit_6 + 32'h00000001); end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + if(when_GenCoreDefault_l367_5) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= (_zz_CsrPlugin_csrMapping_readDataInit_7 + 32'h00000001); end - if(_zz_253)begin - if(_zz_275)begin - memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; - memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_368[31:0]; - end - end + if(when_GenCoreDefault_l367_6) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= (_zz_CsrPlugin_csrMapping_readDataInit_8 + 32'h00000001); end - if(_zz_276)begin - memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_173 ? (~ _zz_174) : _zz_174) + _zz_374); - memory_DivPlugin_rs2 <= ((_zz_172 ? (~ execute_RS2) : execute_RS2) + _zz_376); - memory_DivPlugin_div_needRevert <= ((_zz_173 ^ (_zz_172 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(when_GenCoreDefault_l367_7) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= (_zz_CsrPlugin_csrMapping_readDataInit_9 + 32'h00000001); end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_41; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_8) begin memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_28; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_25; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_22; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_16; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_11; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + end + if(when_Pipeline_l124_45) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_51) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_52) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + if(when_Pipeline_l124_53) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + if(when_Pipeline_l124_54) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_62) begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + end + if(when_Pipeline_l124_63) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if(when_CsrPlugin_l1264_23) begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(when_CsrPlugin_l1264_24) begin execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_25) begin execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_26) begin execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_27) begin execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_28) begin execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_29) begin execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_30) begin execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_31) begin execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_32) begin execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_33) begin execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_34) begin execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_35) begin execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_36) begin execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_37) begin execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_38) begin execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_39) begin execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); - end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_379[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_383[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2820)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2820) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2821) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2822)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2822) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2823) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_1 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2824)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2824) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2825) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2826)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2826) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2827) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2828)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2828) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2829) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2830)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2830) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2831) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2832)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2832) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2833) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2834)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2834) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2835) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -5839,9 +6162,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -5863,6 +6185,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -5878,9 +6201,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -5888,7 +6212,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -5897,99 +6221,81 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_19; - reg [31:0] _zz_20; - reg [21:0] _zz_21; - reg [31:0] _zz_22; - wire _zz_23; - wire _zz_24; - wire _zz_25; - wire _zz_26; - wire _zz_27; - wire _zz_28; - wire _zz_29; - wire [0:0] _zz_30; - wire [0:0] _zz_31; - wire [0:0] _zz_32; - wire [0:0] _zz_33; - wire [0:0] _zz_34; - wire [0:0] _zz_35; - wire [2:0] _zz_36; - wire [2:0] _zz_37; - wire [21:0] _zz_38; - wire [21:0] _zz_39; + reg [20:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [20:0] _zz_ways_0_tags_port; + wire [10:0] _zz_stage0_dataColisions; + wire [10:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; - reg _zz_3; - reg _zz_4; wire haltCpu; reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; + reg [7:0] tagsReadCmd_payload; reg tagsWriteCmd_valid; - reg [1:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; + reg [0:0] tagsWriteCmd_payload_way; + reg [7:0] tagsWriteCmd_payload_address; reg tagsWriteCmd_payload_data_valid; reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; + reg [18:0] tagsWriteCmd_payload_data_address; reg tagsWriteLastCmd_valid; - reg [1:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [7:0] tagsWriteLastCmd_payload_address; reg tagsWriteLastCmd_payload_data_valid; reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; + reg [18:0] tagsWriteLastCmd_payload_data_address; reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; + reg [10:0] dataReadCmd_payload; reg dataWriteCmd_valid; - reg [1:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; + reg [0:0] dataWriteCmd_payload_way; + reg [10:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_5; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_6; - wire _zz_7; + wire [18:0] ways_0_tagsReadRsp_address; + wire [20:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; - wire _zz_8; - wire ways_1_tagsReadRsp_valid; - wire ways_1_tagsReadRsp_error; - wire [19:0] ways_1_tagsReadRsp_address; - wire [21:0] _zz_9; - wire _zz_10; - wire [31:0] ways_1_dataReadRspMem; - wire [31:0] ways_1_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_11; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; - reg [1:0] stage0_dataColisions; - wire [9:0] _zz_12; - wire [3:0] _zz_13; - wire [1:0] stage0_wayInvalidate; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; - wire [1:0] stageA_wayHits; - reg [1:0] _zz_14; - reg [1:0] stageA_wayInvalidate; - reg [1:0] stage0_dataColisions_regNextWhen; - reg [1:0] _zz_15; - wire [9:0] _zz_16; - wire [3:0] _zz_17; - wire [1:0] stageA_dataColisions; + wire [0:0] stageA_wayHits; + wire when_DataCache_l763_2; + reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_stageA_dataColisions; + wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5999,27 +6305,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg stageB_tagsReadRsp_1_valid; - reg stageB_tagsReadRsp_1_error; - reg [19:0] stageB_tagsReadRsp_1_address; + reg [18:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; - reg [31:0] stageB_dataReadRsp_1; - reg [1:0] stageB_wayInvalidate; + wire when_DataCache_l812; + reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; - reg [1:0] stageB_dataColisions; + wire when_DataCache_l812_1; + reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; - reg [1:0] stageB_waysHitsBeforeInvalidate; - wire [1:0] stageB_waysHits; + wire when_DataCache_l812_3; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [8:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -6027,10 +6339,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - reg [1:0] _zz_18; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -6038,432 +6358,359 @@ module DataCache ( reg [2:0] loader_counter_value; wire loader_counter_willOverflowIfInc; wire loader_counter_willOverflow; - reg [1:0] loader_waysAllocator; + reg [0:0] loader_waysAllocator; reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_40; - reg [7:0] _zz_41; - reg [7:0] _zz_42; - reg [7:0] _zz_43; - (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol3 [0:1023]; - reg [7:0] _zz_44; - reg [7:0] _zz_45; - reg [7:0] _zz_46; - reg [7:0] _zz_47; - - assign _zz_23 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_24 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_25 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_26 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_27 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_28 = (! stageB_flusher_hold); - assign _zz_29 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_30 = _zz_6[0 : 0]; - assign _zz_31 = _zz_6[1 : 1]; - assign _zz_32 = _zz_9[0 : 0]; - assign _zz_33 = _zz_9[1 : 1]; - assign _zz_34 = 1'b1; - assign _zz_35 = loader_counter_willIncrement; - assign _zz_36 = {2'd0, _zz_35}; - assign _zz_37 = {loader_waysAllocator,loader_waysAllocator[1]}; - assign _zz_38 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - assign _zz_39 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_5) begin - _zz_19 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin - if(_zz_4) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_38; - end - end - - always @ (*) begin - _zz_20 = {_zz_43, _zz_42, _zz_41, _zz_40}; - end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_40 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_41 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_42 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_43 <= ways_0_data_symbol3[dataReadCmd_payload]; - end - end - - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_3) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_3) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_3) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_3) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end - end - - always @ (posedge clk) begin - if(_zz_8) begin - _zz_21 <= ways_1_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + wire when_DataCache_l1107; + wire when_DataCache_l1110; + (* ram_style = "block" *) reg [20:0] ways_0_tags [0:255]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:2047]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[12 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[12 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_1_tags[tagsWriteCmd_payload_address] <= _zz_39; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_22 = {_zz_47, _zz_46, _zz_45, _zz_44}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_10) begin - _zz_44 <= ways_1_data_symbol0[dataReadCmd_payload]; - _zz_45 <= ways_1_data_symbol1[dataReadCmd_payload]; - _zz_46 <= ways_1_data_symbol2[dataReadCmd_payload]; - _zz_47 <= ways_1_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin - ways_1_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end if(dataWriteCmd_payload_mask[1] && _zz_1) begin - ways_1_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end if(dataWriteCmd_payload_mask[2] && _zz_1) begin - ways_1_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end if(dataWriteCmd_payload_mask[3] && _zz_1) begin - ways_1_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[1]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[1]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end - always @ (*) begin - _zz_3 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_3 = 1'b1; - end - end - - always @ (*) begin - _zz_4 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_4 = 1'b1; - end - end - assign haltCpu = 1'b0; - assign _zz_5 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_6 = _zz_19; - assign ways_0_tagsReadRsp_valid = _zz_30[0]; - assign ways_0_tagsReadRsp_error = _zz_31[0]; - assign ways_0_tagsReadRsp_address = _zz_6[21 : 2]; - assign _zz_7 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_20; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[20 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - assign _zz_8 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_9 = _zz_21; - assign ways_1_tagsReadRsp_valid = _zz_32[0]; - assign ways_1_tagsReadRsp_error = _zz_33[0]; - assign ways_1_tagsReadRsp_address = _zz_9[21 : 2]; - assign _zz_10 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_1_dataReadRspMem = _zz_22; - assign ways_1_dataReadRsp = ways_1_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_23)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_23)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + always @(*) begin + tagsReadCmd_payload = 8'bxxxxxxxx; + if(when_DataCache_l656) begin + tagsReadCmd_payload = io_cpu_execute_address[12 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_23)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_23)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + always @(*) begin + dataReadCmd_payload = 11'bxxxxxxxxxxx; + if(when_DataCache_l656) begin + dataReadCmd_payload = io_cpu_execute_address[12 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_24)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin - tagsWriteCmd_payload_way = 2'bxx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = 2'b11; + always @(*) begin + tagsWriteCmd_payload_way = 1'bx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 8'bxxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[7:0]; end - if(loader_done)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + if(loader_done) begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[12 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + always @(*) begin + tagsWriteCmd_payload_data_address = 19'bxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 13]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_24)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin - dataWriteCmd_payload_way = 2'bxx; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + always @(*) begin + dataWriteCmd_payload_address = 11'bxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[12 : 2]; end - if(_zz_25)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + if(when_DataCache_l1075) begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[12 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_34[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_11 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_11 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_11 = 4'b1111; end endcase end - assign stage0_mask = (_zz_11 <<< io_cpu_execute_address[1 : 0]); - assign _zz_12 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_13 = dataWriteCmd_payload_mask[3 : 0]; - always @ (*) begin - stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); - stage0_dataColisions[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); - end - - assign stage0_wayInvalidate = 2'b00; + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - always @ (*) begin - _zz_14[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - _zz_14[1] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_1_tagsReadRsp_address) && ways_1_tagsReadRsp_valid); - end - - assign stageA_wayHits = _zz_14; - assign _zz_16 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_17 = dataWriteCmd_payload_mask[3 : 0]; - always @ (*) begin - _zz_15[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); - _zz_15[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); - end - - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_15); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 13] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); - assign stageB_waysHit = (stageB_waysHits != 2'b00); - assign stageB_dataMux = (stageB_waysHits[0] ? stageB_dataReadRsp_0 : stageB_dataReadRsp_1); - always @ (*) begin + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(! _zz_27) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_26)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_27)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[8]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[8]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -6471,89 +6718,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 2'b00)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_18) != 2'b00) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_26)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_27)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6561,12 +6792,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(! _zz_27) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6577,24 +6808,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - always @ (*) begin - _zz_18[0] = stageB_tagsReadRsp_0_error; - _zz_18[1] = stageB_tagsReadRsp_1_error; - end - - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_25)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6602,45 +6849,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_36); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6651,105 +6900,89 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_1_valid <= ways_1_tagsReadRsp_valid; - stageB_tagsReadRsp_1_error <= ways_1_tagsReadRsp_error; - stageB_tagsReadRsp_1_address <= ways_1_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_1 <= ways_1_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_28)begin - if(_zz_29)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 9'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; - loader_waysAllocator <= 2'b01; + loader_waysAllocator <= 1'b1; loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_28)begin - if(! _zz_29) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 9'h001); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 9'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_25)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_37[1:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6799,83 +7032,56 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_16; - reg [31:0] _zz_17; - reg [21:0] _zz_18; - reg [21:0] _zz_19; - reg _zz_20; - reg [31:0] _zz_21; - wire _zz_22; - wire _zz_23; - wire [0:0] _zz_24; - wire [0:0] _zz_25; - wire [0:0] _zz_26; - wire [0:0] _zz_27; - wire [21:0] _zz_28; - wire [21:0] _zz_29; + reg [31:0] _zz_banks_0_port1; + reg [20:0] _zz_ways_0_tags_port1; + wire [20:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; - reg _zz_3; - reg _zz_4; reg lineLoader_fire; reg lineLoader_valid; (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_5; + reg [8:0] lineLoader_flushCounter; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; - reg [0:0] lineLoader_wayToAllocate_valueNext; - reg [0:0] lineLoader_wayToAllocate_value; wire lineLoader_wayToAllocate_willOverflowIfInc; wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; + wire [7:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_tag_1_valid; - wire [6:0] lineLoader_write_tag_1_payload_address; - wire lineLoader_write_tag_1_payload_data_valid; - wire lineLoader_write_tag_1_payload_data_error; - wire [19:0] lineLoader_write_tag_1_payload_data_address; + wire [18:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; + wire [10:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire lineLoader_write_data_1_valid; - wire [9:0] lineLoader_write_data_1_payload_address; - wire [31:0] lineLoader_write_data_1_payload_data; - wire [9:0] _zz_6; - wire _zz_7; + wire when_InstructionCache_l401; + wire [10:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [9:0] _zz_8; - wire _zz_9; - wire [31:0] fetchStage_read_banksValue_1_dataMem; - wire [31:0] fetchStage_read_banksValue_1_data; - wire [6:0] _zz_10; - wire _zz_11; + wire [7:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_12; - wire [6:0] _zz_13; - wire _zz_14; - wire fetchStage_read_waysValues_1_tag_valid; - wire fetchStage_read_waysValues_1_tag_error; - wire [19:0] fetchStage_read_waysValues_1_tag_address; - wire [21:0] _zz_15; + wire [18:0] fetchStage_read_waysValues_0_tag_address; + wire [20:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; - wire fetchStage_hit_hits_1; wire fetchStage_hit_valid; - wire [0:0] fetchStage_hit_wayId; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -6885,258 +7091,181 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; - (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; - (* ram_style = "block" *) reg [31:0] banks_1 [0:1023]; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; - - assign _zz_22 = (! lineLoader_flushCounter[7]); - assign _zz_23 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_24 = _zz_12[0 : 0]; - assign _zz_25 = _zz_12[1 : 1]; - assign _zz_26 = _zz_15[0 : 0]; - assign _zz_27 = _zz_15[1 : 1]; - assign _zz_28 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - assign _zz_29 = {lineLoader_write_tag_1_payload_data_address,{lineLoader_write_tag_1_payload_data_error,lineLoader_write_tag_1_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2) begin - banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end + (* ram_style = "block" *) reg [31:0] banks_0 [0:2047]; + (* ram_style = "block" *) reg [20:0] ways_0_tags [0:255]; - always @ (posedge clk) begin - if(_zz_7) begin - _zz_16 <= banks_0[_zz_6]; - end - end - - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin - banks_1[lineLoader_write_data_1_payload_address] <= lineLoader_write_data_1_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_9) begin - _zz_17 <= banks_1[_zz_8]; - end - end - - always @ (posedge clk) begin - if(_zz_4) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_28; + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_11) begin - _zz_18 <= ways_0_tags[_zz_10]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin - if(_zz_3) begin - ways_1_tags[lineLoader_write_tag_1_payload_address] <= _zz_29; + always @(posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_14) begin - _zz_19 <= ways_1_tags[_zz_13]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end always @(*) begin - case(fetchStage_hit_wayId) - 1'b0 : begin - _zz_20 = fetchStage_read_waysValues_0_tag_error; - _zz_21 = fetchStage_read_banksValue_0_data; - end - default : begin - _zz_20 = fetchStage_read_waysValues_1_tag_error; - _zz_21 = fetchStage_read_banksValue_1_data; - end - endcase - end - - always @ (*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_1_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin - _zz_3 = 1'b0; - if(lineLoader_write_tag_1_valid)begin - _zz_3 = 1'b1; - end - end - - always @ (*) begin - _zz_4 = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_4 = 1'b1; - end - end - - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_22)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_5))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[8]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = (lineLoader_wayToAllocate_value == 1'b1); + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - always @ (*) begin - lineLoader_wayToAllocate_valueNext = (lineLoader_wayToAllocate_value + lineLoader_wayToAllocate_willIncrement); - if(lineLoader_wayToAllocate_willClear)begin - lineLoader_wayToAllocate_valueNext = 1'b0; - end - end - - assign lineLoader_write_tag_0_valid = (((lineLoader_wayToAllocate_value == 1'b0) && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[8])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[8] ? lineLoader_address[12 : 5] : lineLoader_flushCounter[7 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[8]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_tag_1_valid = (((lineLoader_wayToAllocate_value == 1'b1) && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_1_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_1_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_1_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_1_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b0)); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 13]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[12 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign lineLoader_write_data_1_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b1)); - assign lineLoader_write_data_1_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_1_payload_data = io_mem_rsp_payload_data; - assign _zz_6 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_16; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[12 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_8 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_1_dataMem = _zz_17; - assign fetchStage_read_banksValue_1_data = fetchStage_read_banksValue_1_dataMem[31 : 0]; - assign _zz_10 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_11 = (! io_cpu_fetch_isStuck); - assign _zz_12 = _zz_18; - assign fetchStage_read_waysValues_0_tag_valid = _zz_24[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_25[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_12[21 : 2]; - assign _zz_13 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_14 = (! io_cpu_fetch_isStuck); - assign _zz_15 = _zz_19; - assign fetchStage_read_waysValues_1_tag_valid = _zz_26[0]; - assign fetchStage_read_waysValues_1_tag_error = _zz_27[0]; - assign fetchStage_read_waysValues_1_tag_address = _zz_15[21 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_hits_1 = (fetchStage_read_waysValues_1_tag_valid && (fetchStage_read_waysValues_1_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = ({fetchStage_hit_hits_1,fetchStage_hit_hits_0} != 2'b00); - assign fetchStage_hit_wayId = fetchStage_hit_hits_1; - assign fetchStage_hit_error = _zz_20; - assign fetchStage_hit_data = _zz_21; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[12 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[20 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 13])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; lineLoader_flushPending <= 1'b1; lineLoader_cmdSent <= 1'b0; - lineLoader_wayToAllocate_value <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_23)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - lineLoader_wayToAllocate_value <= lineLoader_wayToAllocate_valueNext; - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_22)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + if(when_InstructionCache_l338) begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 9'h001); end - _zz_5 <= lineLoader_flushCounter[7]; - if(_zz_23)begin - lineLoader_flushCounter <= 8'h0; + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[8]; + if(when_InstructionCache_l351) begin + lineLoader_flushCounter <= 9'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -7147,10 +7276,10 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index 6613f83..5a78830 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,66 +1,57 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 5bb91146a62643cf606443d5366c69720906549c - - -`define Input2Kind_defaultEncoding_type [0:0] -`define Input2Kind_defaultEncoding_RS 1'b0 -`define Input2Kind_defaultEncoding_IMM_I 1'b1 - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define Input2Kind_binary_sequential_type [0:0] +`define Input2Kind_binary_sequential_RS 1'b0 +`define Input2Kind_binary_sequential_IMM_I 1'b1 + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, - output CfuPlugin_bus_cmd_valid, - input CfuPlugin_bus_cmd_ready, - output [9:0] CfuPlugin_bus_cmd_payload_function_id, - output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, - output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, - input CfuPlugin_bus_rsp_valid, - output CfuPlugin_bus_rsp_ready, - input CfuPlugin_bus_rsp_payload_response_ok, - input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, input [31:0] externalInterruptArray, input debug_bus_cmd_valid, output reg debug_bus_cmd_ready, @@ -69,6 +60,14 @@ module VexRiscv ( input [31:0] debug_bus_cmd_payload_data, output reg [31:0] debug_bus_rsp_data, output debug_resetOut, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, input iBusWishbone_ACK, @@ -95,37 +94,37 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - reg _zz_228; - wire _zz_229; - wire [31:0] _zz_230; - wire _zz_231; - wire [31:0] _zz_232; - reg _zz_233; - wire _zz_234; - wire _zz_235; - wire [31:0] _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire [3:0] _zz_245; - wire _zz_246; - wire _zz_247; - reg [31:0] _zz_248; - reg [31:0] _zz_249; - reg [31:0] _zz_250; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -148,6 +147,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -156,404 +156,332 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_251; - wire _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire _zz_256; - wire _zz_257; - wire _zz_258; - wire _zz_259; - wire _zz_260; - wire _zz_261; - wire _zz_262; - wire _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire _zz_267; - wire _zz_268; - wire [1:0] _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire _zz_279; - wire [1:0] _zz_280; - wire _zz_281; - wire _zz_282; - wire [5:0] _zz_283; - wire _zz_284; - wire _zz_285; - wire _zz_286; - wire _zz_287; - wire _zz_288; - wire _zz_289; - wire _zz_290; - wire [1:0] _zz_291; - wire _zz_292; - wire [1:0] _zz_293; - wire [51:0] _zz_294; - wire [51:0] _zz_295; - wire [51:0] _zz_296; - wire [32:0] _zz_297; - wire [51:0] _zz_298; - wire [49:0] _zz_299; - wire [51:0] _zz_300; - wire [49:0] _zz_301; - wire [51:0] _zz_302; - wire [32:0] _zz_303; - wire [31:0] _zz_304; - wire [32:0] _zz_305; - wire [0:0] _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire [0:0] _zz_312; - wire [0:0] _zz_313; - wire [0:0] _zz_314; - wire [0:0] _zz_315; - wire [0:0] _zz_316; - wire [0:0] _zz_317; - wire [0:0] _zz_318; - wire [0:0] _zz_319; - wire [0:0] _zz_320; - wire [0:0] _zz_321; - wire [0:0] _zz_322; - wire [0:0] _zz_323; - wire [0:0] _zz_324; - wire [3:0] _zz_325; - wire [2:0] _zz_326; - wire [31:0] _zz_327; - wire [11:0] _zz_328; - wire [31:0] _zz_329; - wire [19:0] _zz_330; - wire [11:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [19:0] _zz_334; - wire [11:0] _zz_335; - wire [2:0] _zz_336; - wire [2:0] _zz_337; - wire [0:0] _zz_338; - wire [2:0] _zz_339; - wire [4:0] _zz_340; - wire [11:0] _zz_341; - wire [11:0] _zz_342; - wire [31:0] _zz_343; - wire [31:0] _zz_344; - wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; - wire [31:0] _zz_349; - wire [11:0] _zz_350; - wire [19:0] _zz_351; - wire [11:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire [31:0] _zz_355; - wire [11:0] _zz_356; - wire [19:0] _zz_357; - wire [11:0] _zz_358; - wire [2:0] _zz_359; - wire [1:0] _zz_360; - wire [1:0] _zz_361; - wire [1:0] _zz_362; - wire [1:0] _zz_363; - wire [9:0] _zz_364; - wire [7:0] _zz_365; - wire [65:0] _zz_366; - wire [65:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; - wire [0:0] _zz_370; - wire [5:0] _zz_371; - wire [32:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire [32:0] _zz_375; - wire [32:0] _zz_376; - wire [32:0] _zz_377; - wire [32:0] _zz_378; - wire [0:0] _zz_379; - wire [32:0] _zz_380; - wire [0:0] _zz_381; - wire [32:0] _zz_382; - wire [0:0] _zz_383; - wire [31:0] _zz_384; - wire [0:0] _zz_385; - wire [0:0] _zz_386; - wire [0:0] _zz_387; - wire [0:0] _zz_388; - wire [0:0] _zz_389; - wire [0:0] _zz_390; - wire [0:0] _zz_391; - wire [26:0] _zz_392; - wire _zz_393; - wire _zz_394; - wire [1:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire _zz_399; - wire [0:0] _zz_400; - wire [14:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [8:0] _zz_407; - wire [31:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire _zz_411; - wire [0:0] _zz_412; - wire [2:0] _zz_413; - wire _zz_414; - wire _zz_415; - wire _zz_416; - wire [31:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire _zz_420; - wire [0:0] _zz_421; - wire [28:0] _zz_422; - wire [0:0] _zz_423; - wire [0:0] _zz_424; - wire [0:0] _zz_425; - wire [0:0] _zz_426; - wire _zz_427; - wire [0:0] _zz_428; - wire [23:0] _zz_429; - wire [31:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire _zz_433; - wire _zz_434; - wire [0:0] _zz_435; - wire [0:0] _zz_436; - wire [0:0] _zz_437; - wire [0:0] _zz_438; - wire _zz_439; - wire [0:0] _zz_440; - wire [20:0] _zz_441; - wire [31:0] _zz_442; - wire [31:0] _zz_443; - wire _zz_444; - wire _zz_445; - wire [0:0] _zz_446; - wire [1:0] _zz_447; - wire [0:0] _zz_448; - wire [0:0] _zz_449; - wire _zz_450; - wire [0:0] _zz_451; - wire [17:0] _zz_452; - wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [31:0] _zz_456; - wire [31:0] _zz_457; - wire [31:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire _zz_461; - wire [1:0] _zz_462; - wire [1:0] _zz_463; - wire _zz_464; - wire [0:0] _zz_465; - wire [14:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire [31:0] _zz_471; - wire [31:0] _zz_472; - wire [0:0] _zz_473; - wire [1:0] _zz_474; - wire [4:0] _zz_475; - wire [4:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [11:0] _zz_479; - wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire [31:0] _zz_485; - wire _zz_486; - wire [0:0] _zz_487; - wire [1:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; - wire [0:0] _zz_491; - wire [4:0] _zz_492; - wire [4:0] _zz_493; - wire [4:0] _zz_494; - wire _zz_495; - wire [0:0] _zz_496; - wire [8:0] _zz_497; - wire [31:0] _zz_498; - wire [31:0] _zz_499; - wire [31:0] _zz_500; - wire _zz_501; - wire _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire _zz_505; - wire [0:0] _zz_506; - wire [2:0] _zz_507; - wire [0:0] _zz_508; - wire [2:0] _zz_509; - wire [0:0] _zz_510; - wire [4:0] _zz_511; - wire [1:0] _zz_512; - wire [1:0] _zz_513; - wire _zz_514; - wire [0:0] _zz_515; - wire [6:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire _zz_520; - wire [0:0] _zz_521; - wire [0:0] _zz_522; - wire [31:0] _zz_523; - wire [31:0] _zz_524; - wire _zz_525; - wire [0:0] _zz_526; - wire [0:0] _zz_527; - wire _zz_528; - wire [0:0] _zz_529; - wire [2:0] _zz_530; - wire _zz_531; - wire [0:0] _zz_532; - wire [0:0] _zz_533; - wire [0:0] _zz_534; - wire [0:0] _zz_535; - wire _zz_536; - wire [0:0] _zz_537; - wire [4:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire [31:0] _zz_541; - wire [31:0] _zz_542; - wire [31:0] _zz_543; - wire [31:0] _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire [31:0] _zz_549; - wire [31:0] _zz_550; - wire [31:0] _zz_551; - wire _zz_552; - wire [0:0] _zz_553; - wire [0:0] _zz_554; - wire [31:0] _zz_555; - wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire [31:0] _zz_559; - wire _zz_560; - wire [3:0] _zz_561; - wire [3:0] _zz_562; - wire _zz_563; - wire [0:0] _zz_564; - wire [2:0] _zz_565; - wire [31:0] _zz_566; - wire [31:0] _zz_567; - wire [31:0] _zz_568; - wire [31:0] _zz_569; - wire [31:0] _zz_570; - wire [31:0] _zz_571; - wire _zz_572; - wire [0:0] _zz_573; - wire [1:0] _zz_574; - wire _zz_575; - wire [2:0] _zz_576; - wire [2:0] _zz_577; - wire _zz_578; - wire [0:0] _zz_579; - wire [0:0] _zz_580; - wire [31:0] _zz_581; - wire [31:0] _zz_582; - wire [31:0] _zz_583; - wire [31:0] _zz_584; - wire [31:0] _zz_585; - wire [31:0] _zz_586; - wire [31:0] _zz_587; - wire _zz_588; - wire _zz_589; - wire _zz_590; - wire [0:0] _zz_591; - wire [0:0] _zz_592; - wire _zz_593; - wire _zz_594; - wire _zz_595; - wire _zz_596; - wire [31:0] _zz_597; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6; + wire [27:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20; + wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35; + wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47; + wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70; + wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102; + wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127; + wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1; + wire _zz_when; + wire _zz_when_1; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_41; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; - wire writeBack_CfuPlugin_CFU_IN_FLIGHT; - wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_DO_EBREAK; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; wire decode_SRC2_FORCE_ZERO; + wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + wire decode_CfuPlugin_CFU_ENABLE; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_DIV; wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_1; - wire `Input2Kind_defaultEncoding_type _zz_2; - wire `Input2Kind_defaultEncoding_type _zz_3; - wire decode_CfuPlugin_CFU_ENABLE; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -561,24 +489,30 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; - wire `AluCtrlEnum_defaultEncoding_type _zz_25; - wire `AluCtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; - wire `Src1CtrlEnum_defaultEncoding_type _zz_28; - wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] memory_PC; + reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire execute_CfuPlugin_CFU_ENABLE; wire execute_DO_EBREAK; wire decode_IS_EBREAK; wire execute_IS_RS1_SIGNED; @@ -591,32 +525,26 @@ module VexRiscv ( wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; - reg _zz_30; - reg _zz_31; - wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_32; - wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_37; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -626,46 +554,46 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_38; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_41; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_42; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; - wire [31:0] _zz_46; - wire _zz_47; - reg _zz_48; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_49; - wire `EnvCtrlEnum_defaultEncoding_type _zz_50; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; - wire `Src2CtrlEnum_defaultEncoding_type _zz_54; - wire `AluCtrlEnum_defaultEncoding_type _zz_55; - wire `Src1CtrlEnum_defaultEncoding_type _zz_56; - reg [31:0] _zz_57; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -683,11 +611,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_59; - reg [31:0] _zz_60; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -717,7 +645,7 @@ module VexRiscv ( wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; + wire memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; @@ -774,7 +702,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -800,7 +728,7 @@ module VexRiscv ( reg DBusCachedPlugin_exceptionBus_valid; reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_61; + reg _zz_when_DBusCachedPlugin_l386; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -809,6 +737,11 @@ module VexRiscv ( reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -826,34 +759,37 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; reg CsrPlugin_allowInterrupts; reg CsrPlugin_allowException; - reg CfuPlugin_joinException_valid; - wire [3:0] CfuPlugin_joinException_payload_code; - wire [31:0] CfuPlugin_joinException_payload_badAddr; + reg CsrPlugin_allowEbreakException; reg IBusCachedPlugin_injectionPort_valid; reg IBusCachedPlugin_injectionPort_ready; wire [31:0] IBusCachedPlugin_injectionPort_payload; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_62; - wire [3:0] _zz_63; - wire _zz_64; - wire _zz_65; - wire _zz_66; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -876,16 +812,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_67; - wire _zz_68; - wire _zz_69; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_70; - wire _zz_71; - reg _zz_72; - wire _zz_73; - reg _zz_74; - reg [31:0] _zz_75; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -893,22 +831,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_76; - reg [18:0] _zz_77; - wire _zz_78; - reg [10:0] _zz_79; - wire _zz_80; - reg [18:0] _zz_81; - reg _zz_82; - wire _zz_83; - reg [10:0] _zz_84; - wire _zz_85; - reg [18:0] _zz_86; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -916,7 +861,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_87; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -924,23 +869,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -948,40 +898,56 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_88; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_89; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_90; - reg [31:0] _zz_91; - wire _zz_92; - reg [31:0] _zz_93; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [34:0] _zz_94; - wire _zz_95; - wire _zz_96; - wire _zz_97; - wire _zz_98; - wire _zz_99; - wire `Src1CtrlEnum_defaultEncoding_type _zz_100; - wire `AluCtrlEnum_defaultEncoding_type _zz_101; - wire `Src2CtrlEnum_defaultEncoding_type _zz_102; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; - wire `BranchCtrlEnum_defaultEncoding_type _zz_105; - wire `EnvCtrlEnum_defaultEncoding_type _zz_106; - wire `Input2Kind_defaultEncoding_type _zz_107; + wire when_DBusCachedPlugin_l484; + wire [34:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -989,53 +955,72 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_108; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_109; - reg [31:0] _zz_110; - wire _zz_111; - reg [19:0] _zz_112; - wire _zz_113; - reg [19:0] _zz_114; - reg [31:0] _zz_115; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_116; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_117; - reg _zz_118; - reg _zz_119; - reg _zz_120; - reg [4:0] _zz_121; - reg [31:0] _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; - wire _zz_126; - wire _zz_127; - wire _zz_128; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_129; - reg _zz_130; - reg _zz_131; - wire _zz_132; - reg [19:0] _zz_133; - wire _zz_134; - reg [10:0] _zz_135; - wire _zz_136; - reg [18:0] _zz_137; - reg _zz_138; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_139; - reg [19:0] _zz_140; - wire _zz_141; - reg [10:0] _zz_142; - wire _zz_143; - reg [18:0] _zz_144; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; + wire when_BranchPlugin_l296; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1056,9 +1041,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_145; - wire _zz_146; - wire _zz_147; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1071,72 +1056,69 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_148; - wire _zz_149; - wire [1:0] _zz_150; - wire _zz_151; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - wire execute_CfuPlugin_schedule; - reg execute_CfuPlugin_hold; - reg execute_CfuPlugin_fired; - wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_168; - reg [23:0] _zz_169; - reg [31:0] _zz_170; - wire memory_CfuPlugin_rsp_valid; - reg memory_CfuPlugin_rsp_ready; - wire memory_CfuPlugin_rsp_payload_response_ok; - wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_s2mPipe_rValid; - reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1144,6 +1126,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1156,19 +1140,26 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_171; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_172; - wire _zz_173; - wire _zz_174; - reg [32:0] _zz_175; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_176; - wire [31:0] _zz_177; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1176,236 +1167,408 @@ module VexRiscv ( reg DebugPlugin_stepIt; reg DebugPlugin_isPipBusy; reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_178; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire CfuPlugin_bus_cmd_fire; + wire when_CfuPlugin_l171; + wire when_CfuPlugin_l175; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_CfuPlugin_bus_cmd_payload_inputs_1; + reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1; + reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + wire CfuPlugin_bus_rsp_rsp_valid; + reg CfuPlugin_bus_rsp_rsp_ready; + wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_rValid; + reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; + wire when_CfuPlugin_l208; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_when_GenCoreDefault_l367; + wire when_GenCoreDefault_l367; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_when_GenCoreDefault_l367_1; + wire when_GenCoreDefault_l367_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_when_GenCoreDefault_l367_2; + wire when_GenCoreDefault_l367_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_when_GenCoreDefault_l367_3; + wire when_GenCoreDefault_l367_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_when_GenCoreDefault_l367_4; + wire when_GenCoreDefault_l367_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_when_GenCoreDefault_l367_5; + wire when_GenCoreDefault_l367_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_when_GenCoreDefault_l367_6; + wire when_GenCoreDefault_l367_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_when_GenCoreDefault_l367_7; + wire when_GenCoreDefault_l367_7; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + wire when_Pipeline_l124_44; + reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_45; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_46; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_47; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_48; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_49; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_50; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_51; reg decode_to_execute_DO_EBREAK; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_52; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_53; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_54; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_55; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_57; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_60; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_61; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_62; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_63; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_64; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_179; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l378; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; + reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; + reg execute_CsrPlugin_csr_4032; + wire when_CsrPlugin_l1264_24; reg execute_CsrPlugin_csr_2820; + wire when_CsrPlugin_l1264_25; reg execute_CsrPlugin_csr_2821; + wire when_CsrPlugin_l1264_26; reg execute_CsrPlugin_csr_2822; + wire when_CsrPlugin_l1264_27; reg execute_CsrPlugin_csr_2823; + wire when_CsrPlugin_l1264_28; reg execute_CsrPlugin_csr_2824; + wire when_CsrPlugin_l1264_29; reg execute_CsrPlugin_csr_2825; + wire when_CsrPlugin_l1264_30; reg execute_CsrPlugin_csr_2826; + wire when_CsrPlugin_l1264_31; reg execute_CsrPlugin_csr_2827; + wire when_CsrPlugin_l1264_32; reg execute_CsrPlugin_csr_2828; + wire when_CsrPlugin_l1264_33; reg execute_CsrPlugin_csr_2829; + wire when_CsrPlugin_l1264_34; reg execute_CsrPlugin_csr_2830; + wire when_CsrPlugin_l1264_35; reg execute_CsrPlugin_csr_2831; + wire when_CsrPlugin_l1264_36; reg execute_CsrPlugin_csr_2832; + wire when_CsrPlugin_l1264_37; reg execute_CsrPlugin_csr_2833; + wire when_CsrPlugin_l1264_38; reg execute_CsrPlugin_csr_2834; + wire when_CsrPlugin_l1264_39; reg execute_CsrPlugin_csr_2835; - reg execute_CsrPlugin_csr_3008; - reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [31:0] _zz_199; - reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; - reg [31:0] _zz_208; - reg [31:0] _zz_209; - reg [31:0] _zz_210; - reg [2:0] _zz_211; - reg _zz_212; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_29; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_30; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_31; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_32; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_33; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_34; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_35; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_36; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_37; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_38; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_39; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_40; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - reg _zz_219; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8_string; - reg [39:0] _zz_9_string; - reg [39:0] _zz_10_string; - reg [31:0] _zz_11_string; - reg [31:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_15_string; - reg [71:0] _zz_16_string; - reg [71:0] _zz_17_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_18_string; - reg [39:0] _zz_19_string; - reg [39:0] _zz_20_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_21_string; - reg [23:0] _zz_22_string; - reg [23:0] _zz_23_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_24_string; - reg [63:0] _zz_25_string; - reg [63:0] _zz_26_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_27_string; - reg [95:0] _zz_28_string; - reg [95:0] _zz_29_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_32_string; + reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_36_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_39_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_40_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_42_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_43_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_44_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_45_string; - reg [39:0] _zz_49_string; - reg [39:0] _zz_50_string; - reg [31:0] _zz_51_string; - reg [71:0] _zz_52_string; - reg [39:0] _zz_53_string; - reg [23:0] _zz_54_string; - reg [63:0] _zz_55_string; - reg [95:0] _zz_56_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_58_string; - reg [95:0] _zz_100_string; - reg [63:0] _zz_101_string; - reg [23:0] _zz_102_string; - reg [39:0] _zz_103_string; - reg [71:0] _zz_104_string; - reg [31:0] _zz_105_string; - reg [39:0] _zz_106_string; - reg [39:0] _zz_107_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1421,489 +1584,441 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_251 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_253 = 1'b1; - assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_256 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_257 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_258 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_259 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_260 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_261 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_262 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_263 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_264 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_265 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_268 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_269 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_270 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_271 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_272 = (1'b0 || (! 1'b1)); - assign _zz_273 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_274 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_275 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_276 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_277 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_278 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_280 = execute_INSTRUCTION[13 : 12]; - assign _zz_281 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_282 = (! memory_arbitration_isStuck); - assign _zz_283 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_284 = (iBus_cmd_valid || (_zz_211 != 3'b000)); - assign _zz_285 = (_zz_247 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_286 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_287 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_288 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_289 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_290 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_291 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_292 = execute_INSTRUCTION[13]; - assign _zz_293 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_294 = ($signed(_zz_295) + $signed(_zz_300)); - assign _zz_295 = ($signed(_zz_296) + $signed(_zz_298)); - assign _zz_296 = 52'h0; - assign _zz_297 = {1'b0,memory_MUL_LL}; - assign _zz_298 = {{19{_zz_297[32]}}, _zz_297}; - assign _zz_299 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; - assign _zz_301 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_302 = {{2{_zz_301[49]}}, _zz_301}; - assign _zz_303 = ($signed(_zz_305) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_304 = _zz_303[31 : 0]; - assign _zz_305 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_306 = _zz_94[33 : 33]; - assign _zz_307 = _zz_94[32 : 32]; - assign _zz_308 = _zz_94[31 : 31]; - assign _zz_309 = _zz_94[30 : 30]; - assign _zz_310 = _zz_94[28 : 28]; - assign _zz_311 = _zz_94[25 : 25]; - assign _zz_312 = _zz_94[17 : 17]; - assign _zz_313 = _zz_94[16 : 16]; - assign _zz_314 = _zz_94[13 : 13]; - assign _zz_315 = _zz_94[12 : 12]; - assign _zz_316 = _zz_94[11 : 11]; - assign _zz_317 = _zz_94[34 : 34]; - assign _zz_318 = _zz_94[15 : 15]; - assign _zz_319 = _zz_94[5 : 5]; - assign _zz_320 = _zz_94[3 : 3]; - assign _zz_321 = _zz_94[20 : 20]; - assign _zz_322 = _zz_94[10 : 10]; - assign _zz_323 = _zz_94[4 : 4]; - assign _zz_324 = _zz_94[0 : 0]; - assign _zz_325 = (_zz_62 - 4'b0001); - assign _zz_326 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_327 = {29'd0, _zz_326}; - assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_329 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_331 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_332 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_333 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_334 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_335 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_338 = execute_SRC_LESS; - assign _zz_339 = 3'b100; - assign _zz_340 = execute_INSTRUCTION[19 : 15]; - assign _zz_341 = execute_INSTRUCTION[31 : 20]; - assign _zz_342 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_343 = ($signed(_zz_344) + $signed(_zz_347)); - assign _zz_344 = ($signed(_zz_345) + $signed(_zz_346)); - assign _zz_345 = execute_SRC1; - assign _zz_346 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_347 = (execute_SRC_USE_SUB_LESS ? _zz_348 : _zz_349); - assign _zz_348 = 32'h00000001; - assign _zz_349 = 32'h0; - assign _zz_350 = execute_INSTRUCTION[31 : 20]; - assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_353 = {_zz_133,execute_INSTRUCTION[31 : 20]}; - assign _zz_354 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_355 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_356 = execute_INSTRUCTION[31 : 20]; - assign _zz_357 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_359 = 3'b100; - assign _zz_360 = (_zz_148 & (~ _zz_361)); - assign _zz_361 = (_zz_148 - 2'b01); - assign _zz_362 = (_zz_150 & (~ _zz_363)); - assign _zz_363 = (_zz_150 - 2'b01); - assign _zz_364 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_365 = execute_INSTRUCTION[31 : 24]; - assign _zz_366 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_367 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_368 = writeBack_MUL_LOW[31 : 0]; - assign _zz_369 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_370 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_371 = {5'd0, _zz_370}; - assign _zz_372 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_373 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_374 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_375 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_376 = _zz_377; - assign _zz_377 = _zz_378; - assign _zz_378 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_380); - assign _zz_379 = memory_DivPlugin_div_needRevert; - assign _zz_380 = {32'd0, _zz_379}; - assign _zz_381 = _zz_174; - assign _zz_382 = {32'd0, _zz_381}; - assign _zz_383 = _zz_173; - assign _zz_384 = {31'd0, _zz_383}; - assign _zz_385 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_386 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_387 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_388 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_391 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_392 = (iBus_cmd_payload_address >>> 5); - assign _zz_393 = 1'b1; - assign _zz_394 = 1'b1; - assign _zz_395 = {_zz_66,_zz_65}; - assign _zz_396 = 32'h0000106f; - assign _zz_397 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_398 = 32'h00001073; - assign _zz_399 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_400 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_401 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_402) == 32'h00000003),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; - assign _zz_402 = 32'h0000207f; - assign _zz_403 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_404 = 32'h00000003; - assign _zz_405 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_406 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_407 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_408) == 32'h00005013),{(_zz_409 == _zz_410),{_zz_411,{_zz_412,_zz_413}}}}}}; - assign _zz_408 = 32'hbc00707f; - assign _zz_409 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_410 = 32'h00001013; - assign _zz_411 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_412 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_413 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; - assign _zz_414 = decode_INSTRUCTION[31]; - assign _zz_415 = decode_INSTRUCTION[31]; - assign _zz_416 = decode_INSTRUCTION[7]; - assign _zz_417 = 32'h10103050; - assign _zz_418 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_419 = 1'b0; - assign _zz_420 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_421 = 1'b0; - assign _zz_422 = {(_zz_98 != 1'b0),{({_zz_423,_zz_424} != 2'b00),{(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}}}; - assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h10000050); - assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00000050); - assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00000050); - assign _zz_426 = 1'b0; - assign _zz_427 = ({_zz_433,_zz_434} != 2'b00); - assign _zz_428 = ({_zz_435,_zz_436} != 2'b00); - assign _zz_429 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; - assign _zz_430 = 32'h10203050; - assign _zz_431 = 32'h10103050; - assign _zz_432 = 32'h00103050; - assign _zz_433 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_434 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_435 = _zz_97; - assign _zz_436 = ((decode_INSTRUCTION & _zz_442) == 32'h00000004); - assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000040); - assign _zz_438 = 1'b0; - assign _zz_439 = ({_zz_444,_zz_445} != 2'b00); - assign _zz_440 = ({_zz_446,_zz_447} != 3'b000); - assign _zz_441 = {(_zz_448 != _zz_449),{_zz_450,{_zz_451,_zz_452}}}; - assign _zz_442 = 32'h0000001c; - assign _zz_443 = 32'h00000058; - assign _zz_444 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_445 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h40001010); - assign _zz_447 = {(_zz_454 == _zz_455),(_zz_456 == _zz_457)}; - assign _zz_448 = ((decode_INSTRUCTION & _zz_458) == 32'h00000024); - assign _zz_449 = 1'b0; - assign _zz_450 = ((_zz_459 == _zz_460) != 1'b0); - assign _zz_451 = (_zz_461 != 1'b0); - assign _zz_452 = {(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}; - assign _zz_453 = 32'h40003054; - assign _zz_454 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_455 = 32'h00001010; - assign _zz_456 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_457 = 32'h00001010; - assign _zz_458 = 32'h00000064; - assign _zz_459 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_460 = 32'h00001000; - assign _zz_461 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_462 = {(_zz_467 == _zz_468),(_zz_469 == _zz_470)}; - assign _zz_463 = 2'b00; - assign _zz_464 = ((_zz_471 == _zz_472) != 1'b0); - assign _zz_465 = ({_zz_473,_zz_474} != 3'b000); - assign _zz_466 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; - assign _zz_467 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_468 = 32'h00002000; - assign _zz_469 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_470 = 32'h00001000; - assign _zz_471 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_472 = 32'h00004004; - assign _zz_473 = _zz_98; - assign _zz_474 = {(_zz_480 == _zz_481),(_zz_482 == _zz_483)}; - assign _zz_475 = {(_zz_484 == _zz_485),{_zz_486,{_zz_487,_zz_488}}}; - assign _zz_476 = 5'h0; - assign _zz_477 = ((_zz_489 == _zz_490) != 1'b0); - assign _zz_478 = ({_zz_491,_zz_492} != 6'h0); - assign _zz_479 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; - assign _zz_480 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_481 = 32'h00000020; - assign _zz_482 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_483 = 32'h00000020; - assign _zz_484 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_485 = 32'h00002040; - assign _zz_486 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); - assign _zz_487 = (_zz_499 == _zz_500); - assign _zz_488 = {_zz_501,_zz_502}; - assign _zz_489 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_490 = 32'h00000020; - assign _zz_491 = (_zz_503 == _zz_504); - assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; - assign _zz_493 = {_zz_96,{_zz_508,_zz_509}}; - assign _zz_494 = 5'h0; - assign _zz_495 = ({_zz_510,_zz_511} != 6'h0); - assign _zz_496 = (_zz_512 != _zz_513); - assign _zz_497 = {_zz_514,{_zz_515,_zz_516}}; - assign _zz_498 = 32'h00001040; - assign _zz_499 = (decode_INSTRUCTION & 32'h00100040); - assign _zz_500 = 32'h00000040; - assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00000040); - assign _zz_502 = ((decode_INSTRUCTION & _zz_518) == 32'h0); - assign _zz_503 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_504 = 32'h00000008; - assign _zz_505 = ((decode_INSTRUCTION & _zz_519) == 32'h00000040); - assign _zz_506 = _zz_96; - assign _zz_507 = {_zz_520,{_zz_521,_zz_522}}; - assign _zz_508 = (_zz_523 == _zz_524); - assign _zz_509 = {_zz_525,{_zz_526,_zz_527}}; - assign _zz_510 = _zz_97; - assign _zz_511 = {_zz_528,{_zz_529,_zz_530}}; - assign _zz_512 = {_zz_96,_zz_531}; - assign _zz_513 = 2'b00; - assign _zz_514 = ({_zz_532,_zz_533} != 2'b00); - assign _zz_515 = (_zz_534 != _zz_535); - assign _zz_516 = {_zz_536,{_zz_537,_zz_538}}; - assign _zz_517 = 32'h00000050; - assign _zz_518 = 32'h00000038; - assign _zz_519 = 32'h00000040; - assign _zz_520 = ((decode_INSTRUCTION & _zz_539) == 32'h00004020); - assign _zz_521 = (_zz_540 == _zz_541); - assign _zz_522 = (_zz_542 == _zz_543); - assign _zz_523 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_524 = 32'h00002010; - assign _zz_525 = ((decode_INSTRUCTION & _zz_544) == 32'h00000010); - assign _zz_526 = (_zz_545 == _zz_546); - assign _zz_527 = (_zz_547 == _zz_548); - assign _zz_528 = ((decode_INSTRUCTION & _zz_549) == 32'h00001010); - assign _zz_529 = (_zz_550 == _zz_551); - assign _zz_530 = {_zz_552,{_zz_553,_zz_554}}; - assign _zz_531 = ((decode_INSTRUCTION & _zz_555) == 32'h00000020); - assign _zz_532 = _zz_96; - assign _zz_533 = (_zz_556 == _zz_557); - assign _zz_534 = (_zz_558 == _zz_559); - assign _zz_535 = 1'b0; - assign _zz_536 = (_zz_560 != 1'b0); - assign _zz_537 = (_zz_561 != _zz_562); - assign _zz_538 = {_zz_563,{_zz_564,_zz_565}}; - assign _zz_539 = 32'h00004020; - assign _zz_540 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_541 = 32'h00000010; - assign _zz_542 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_543 = 32'h00000020; - assign _zz_544 = 32'h00001030; - assign _zz_545 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_546 = 32'h00002020; - assign _zz_547 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_548 = 32'h00000020; - assign _zz_549 = 32'h00001010; - assign _zz_550 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_551 = 32'h00002010; - assign _zz_552 = ((decode_INSTRUCTION & _zz_566) == 32'h00000010); - assign _zz_553 = (_zz_567 == _zz_568); - assign _zz_554 = (_zz_569 == _zz_570); - assign _zz_555 = 32'h00000070; - assign _zz_556 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_557 = 32'h0; - assign _zz_558 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_559 = 32'h00004010; - assign _zz_560 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); - assign _zz_561 = {_zz_572,{_zz_573,_zz_574}}; - assign _zz_562 = 4'b0000; - assign _zz_563 = (_zz_575 != 1'b0); - assign _zz_564 = (_zz_576 != _zz_577); - assign _zz_565 = {_zz_578,{_zz_579,_zz_580}}; - assign _zz_566 = 32'h00000050; - assign _zz_567 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_568 = 32'h00000004; - assign _zz_569 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_570 = 32'h0; - assign _zz_571 = 32'h00006014; - assign _zz_572 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_573 = ((decode_INSTRUCTION & _zz_581) == 32'h0); - assign _zz_574 = {(_zz_582 == _zz_583),(_zz_584 == _zz_585)}; - assign _zz_575 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_576 = {(_zz_586 == _zz_587),{_zz_588,_zz_589}}; - assign _zz_577 = 3'b000; - assign _zz_578 = ({_zz_590,_zz_95} != 2'b00); - assign _zz_579 = ({_zz_591,_zz_592} != 2'b00); - assign _zz_580 = (_zz_593 != 1'b0); - assign _zz_581 = 32'h00000018; - assign _zz_582 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_583 = 32'h00002000; - assign _zz_584 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_585 = 32'h00001000; - assign _zz_586 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_587 = 32'h00000040; - assign _zz_588 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_589 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_590 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_591 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_592 = _zz_95; - assign _zz_593 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); - assign _zz_594 = execute_INSTRUCTION[31]; - assign _zz_595 = execute_INSTRUCTION[31]; - assign _zz_596 = execute_INSTRUCTION[7]; - assign _zz_597 = 32'h0; - always @ (posedge clk) begin - if(_zz_393) begin - _zz_248 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_394) begin - _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_48) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = (decode_INSTRUCTION & 32'h10103050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 32'h00100050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = (((decode_INSTRUCTION & 32'h02004064) == 32'h02004020) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9} != 2'b00),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21}}}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h02004074; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00001050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = 32'h00002050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = 32'h00005020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h00007034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = 32'h02007054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = 32'h00002000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50) == 32'h00004004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = 32'h00005000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = 32'h00004054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59) == 32'h00002040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81}} != 6'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = 32'h00000064; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = 32'h00002040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00001040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77) == 32'h00000008); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = 6'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = 32'h00100040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = 32'h00000008; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = 32'h00004020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = 32'h00002030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00002020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131) == 32'h00004010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141} != 4'b0000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h00000030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = 32'h02000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02002060; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = 32'h02003020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = 32'h00004014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = 32'h00000044; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = 32'h00000058; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156) == 32'h40000030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167) == 32'h00001004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h00002014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = 32'h40000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = 32'h00000014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = 32'h00000004; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167 = 32'h00005054; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_41 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_220 ), //i - .io_cpu_prefetch_isValid (_zz_221 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_222 ), //i - .io_cpu_fetch_isStuck (_zz_223 ), //i - .io_cpu_fetch_isRemoved (_zz_224 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_225 ), //i - .io_cpu_decode_isStuck (_zz_226 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_227 ), //i - .io_cpu_fill_valid (_zz_228 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_16 (_zz_179[2:0] ), //i - ._zz_17 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i + ._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_229 ), //i - .io_cpu_execute_address (_zz_230[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_89[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_231 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_232[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_233 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_234 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_235 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_236[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_237 ), //i - .io_cpu_writeBack_fence_SR (_zz_238 ), //i - .io_cpu_writeBack_fence_SO (_zz_239 ), //i - .io_cpu_writeBack_fence_SI (_zz_240 ), //i - .io_cpu_writeBack_fence_PW (_zz_241 ), //i - .io_cpu_writeBack_fence_PR (_zz_242 ), //i - .io_cpu_writeBack_fence_PO (_zz_243 ), //i - .io_cpu_writeBack_fence_PI (_zz_244 ), //i - .io_cpu_writeBack_fence_FM (_zz_245[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_246 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_247 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_395) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) + 2'b00 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) 2'b00 : begin - _zz_250 = DBusCachedPlugin_redoBranch_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; end 2'b01 : begin - _zz_250 = CsrPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; end 2'b10 : begin - _zz_250 = BranchPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; end default : begin - _zz_250 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end @@ -1911,811 +2026,828 @@ module VexRiscv ( `ifndef SYNTHESIS always @(*) begin case(decode_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_1) - `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; - default : _zz_1_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; - default : _zz_2_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; - default : _zz_3_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; - default : _zz_8_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_9) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; - default : _zz_9_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_10) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; - default : _zz_10_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_11) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; - default : _zz_11_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_12) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; - default : _zz_12_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_16) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; - default : _zz_16_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_17) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; - default : _zz_17_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_19) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; - default : _zz_19_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_20) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; - default : _zz_20_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_25) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; - default : _zz_25_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_26) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; - default : _zz_26_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_28) - `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; - default : _zz_28_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_29) - `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; - default : _zz_29_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_32) - `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; - default : _zz_32_string = "?????"; + case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_36) - `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; - default : _zz_36_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_39) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; - default : _zz_39_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_40) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; - default : _zz_40_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_42) - `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; - default : _zz_42_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_43) - `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; - default : _zz_43_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_44) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; - default : _zz_44_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_45) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; - default : _zz_45_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_49) - `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; - default : _zz_49_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_50) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; - default : _zz_50_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_52) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; - default : _zz_52_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_53) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; - default : _zz_53_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_54) - `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; - default : _zz_54_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_55) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; - default : _zz_55_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_56) - `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; - default : _zz_56_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_58) - `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; - default : _zz_58_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_100) - `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; - default : _zz_100_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_101) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; - default : _zz_101_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_102) - `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; - default : _zz_102_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_103) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; - default : _zz_103_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_104) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; - default : _zz_104_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_105) - `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; - default : _zz_105_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_106) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; - default : _zz_106_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_107) - `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; - default : _zz_107_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_294) + $signed(_zz_302)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_304; - assign execute_REGFILE_WRITE_DATA = _zz_109; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_230[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_306[0]; - assign decode_IS_RS1_SIGNED = _zz_307[0]; - assign decode_IS_DIV = _zz_308[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33]; + assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30]; + assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_309[0]; - assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; - assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_310[0]; - assign _zz_4 = _zz_5; - assign _zz_6 = _zz_7; - assign decode_ENV_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_311[0]; - assign _zz_11 = _zz_12; - assign _zz_13 = _zz_14; - assign decode_SHIFT_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_ALU_BITWISE_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_312[0]; - assign decode_MEMORY_MANAGMENT = _zz_313[0]; + assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_314[0]; + assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_315[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_316[0]; - assign decode_SRC2_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_ALU_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_SRC1_CTRL = _zz_27; - assign _zz_28 = _zz_29; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; + always @(*) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + always @(*) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_317[0]; + assign decode_IS_EBREAK = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2726,42 +2858,25 @@ module VexRiscv ( assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; - always @ (*) begin - _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; - if(memory_arbitration_isStuck)begin - _zz_30 = 1'b0; - end - end - - always @ (*) begin - _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; - if(execute_arbitration_isStuck)begin - _zz_31 = 1'b0; - end - end - - assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33; - assign execute_ENV_CTRL = _zz_34; - assign writeBack_ENV_CTRL = _zz_35; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_131; - assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_318[0]; - assign decode_RS1_USE = _zz_319[0]; - always @ (*) begin - _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_251)begin - _zz_37 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15]; + assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2771,142 +2886,142 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_122; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_252)begin - if(_zz_253)begin - if(_zz_124)begin - decode_RS2 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_254)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_126)begin - decode_RS2 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_255)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_128)begin - decode_RS2 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_122; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_252)begin - if(_zz_253)begin - if(_zz_123)begin - decode_RS1 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_254)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin - decode_RS1 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_255)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin - decode_RS1 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_38 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_117; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_38 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end - if(_zz_256)begin - _zz_38 = memory_DivPlugin_div_result; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + _zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0; end end - assign memory_SHIFT_CTRL = _zz_39; - assign execute_SHIFT_CTRL = _zz_40; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_41 = execute_PC; - assign execute_SRC2_CTRL = _zz_42; - assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_320[0]; - assign decode_SRC_ADD_ZERO = _zz_321[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_115; - assign execute_SRC1 = _zz_110; - assign execute_ALU_BITWISE_CTRL = _zz_45; - assign _zz_46 = writeBack_INSTRUCTION; - assign _zz_47 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_48 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_48 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_322[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}} != 22'h0); - always @ (*) begin - _zz_57 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_293) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_57 = _zz_368; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_57 = _zz_369; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2918,61 +3033,61 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_323[0]; - assign decode_FLUSH_ALL = _zz_324[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4]; + assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_257)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_258)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_259)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_260)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_58; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_59 = execute_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_59 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_60 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end - case(_zz_179) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2981,174 +3096,165 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_261)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_246 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_262)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_251)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end - if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + if(when_CfuPlugin_l175) begin execute_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_263)begin + if(when_DebugPlugin_l284) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_264)begin + if(_zz_when_1) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushIt = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_264)begin + if(_zz_when_1) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushNext = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if((! memory_CfuPlugin_rsp_valid))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_256)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + if(when_CfuPlugin_l208) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushNext = 1'b0; + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3157,75 +3263,77 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_268)begin + if(when_DebugPlugin_l300) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin - _zz_61 = 1'b0; - if(DebugPlugin_godmode)begin - _zz_61 = 1'b1; + always @(*) begin + _zz_when_DBusCachedPlugin_l386 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l386 = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_262)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin CsrPlugin_thirdPartyWake = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_266)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_267)begin - case(_zz_269) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3235,80 +3343,92 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_forceMachineWire = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + if(when_DebugPlugin_l316) begin CsrPlugin_allowInterrupts = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_allowException = 1'b0; end end + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_63 = (_zz_62 & (~ _zz_325)); - assign _zz_64 = _zz_63[3]; - assign _zz_65 = (_zz_63[1] || _zz_64); - assign _zz_66 = (_zz_63[2] || _zz_64); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_250; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_327); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3316,66 +3436,75 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_67); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_68); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_68); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_69 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_69); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_69); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_70; - assign _zz_70 = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_71 = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_73)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_73 = _zz_74; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_73; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_75; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); - always @ (*) begin + always @(*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_179) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3387,207 +3516,219 @@ module VexRiscv ( endcase end - assign _zz_76 = _zz_328[11]; - always @ (*) begin - _zz_77[18] = _zz_76; - _zz_77[17] = _zz_76; - _zz_77[16] = _zz_76; - _zz_77[15] = _zz_76; - _zz_77[14] = _zz_76; - _zz_77[13] = _zz_76; - _zz_77[12] = _zz_76; - _zz_77[11] = _zz_76; - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7] = _zz_76; - _zz_77[6] = _zz_76; - _zz_77[5] = _zz_76; - _zz_77[4] = _zz_76; - _zz_77[3] = _zz_76; - _zz_77[2] = _zz_76; - _zz_77[1] = _zz_76; - _zz_77[0] = _zz_76; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_329[31])); - if(_zz_82)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_78 = _zz_330[19]; - always @ (*) begin - _zz_79[10] = _zz_78; - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7] = _zz_78; - _zz_79[6] = _zz_78; - _zz_79[5] = _zz_78; - _zz_79[4] = _zz_78; - _zz_79[3] = _zz_78; - _zz_79[2] = _zz_78; - _zz_79[1] = _zz_78; - _zz_79[0] = _zz_78; - end - - assign _zz_80 = _zz_331[11]; - always @ (*) begin - _zz_81[18] = _zz_80; - _zz_81[17] = _zz_80; - _zz_81[16] = _zz_80; - _zz_81[15] = _zz_80; - _zz_81[14] = _zz_80; - _zz_81[13] = _zz_80; - _zz_81[12] = _zz_80; - _zz_81[11] = _zz_80; - _zz_81[10] = _zz_80; - _zz_81[9] = _zz_80; - _zz_81[8] = _zz_80; - _zz_81[7] = _zz_80; - _zz_81[6] = _zz_80; - _zz_81[5] = _zz_80; - _zz_81[4] = _zz_80; - _zz_81[3] = _zz_80; - _zz_81[2] = _zz_80; - _zz_81[1] = _zz_80; - _zz_81[0] = _zz_80; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_82 = _zz_332[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_82 = _zz_333[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_83 = _zz_334[19]; - always @ (*) begin - _zz_84[10] = _zz_83; - _zz_84[9] = _zz_83; - _zz_84[8] = _zz_83; - _zz_84[7] = _zz_83; - _zz_84[6] = _zz_83; - _zz_84[5] = _zz_83; - _zz_84[4] = _zz_83; - _zz_84[3] = _zz_83; - _zz_84[2] = _zz_83; - _zz_84[1] = _zz_83; - _zz_84[0] = _zz_83; - end - - assign _zz_85 = _zz_335[11]; - always @ (*) begin - _zz_86[18] = _zz_85; - _zz_86[17] = _zz_85; - _zz_86[16] = _zz_85; - _zz_86[15] = _zz_85; - _zz_86[14] = _zz_85; - _zz_86[13] = _zz_85; - _zz_86[12] = _zz_85; - _zz_86[11] = _zz_85; - _zz_86[10] = _zz_85; - _zz_86[9] = _zz_85; - _zz_86[8] = _zz_85; - _zz_86[7] = _zz_85; - _zz_86[6] = _zz_85; - _zz_86[5] = _zz_85; - _zz_86[4] = _zz_85; - _zz_86[3] = _zz_85; - _zz_86[2] = _zz_85; - _zz_86[1] = _zz_85; - _zz_86[0] = _zz_85; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_414,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_415,_zz_416},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_222; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_225 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_226 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_227 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_260)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_258)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_228 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_258)begin - _zz_228 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_259)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_257)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_259)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_257)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_220 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_247 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3595,168 +3736,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_229 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_230 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_89 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_89 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_246 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_231 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_232 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_231; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_232; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_233 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_233 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_234 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_235 = (CsrPlugin_privilege == 2'b00); - assign _zz_236 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_270)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_270)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_270)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; end - assign _zz_90 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_91[31] = _zz_90; - _zz_91[30] = _zz_90; - _zz_91[29] = _zz_90; - _zz_91[28] = _zz_90; - _zz_91[27] = _zz_90; - _zz_91[26] = _zz_90; - _zz_91[25] = _zz_90; - _zz_91[24] = _zz_90; - _zz_91[23] = _zz_90; - _zz_91[22] = _zz_90; - _zz_91[21] = _zz_90; - _zz_91[20] = _zz_90; - _zz_91[19] = _zz_90; - _zz_91[18] = _zz_90; - _zz_91[17] = _zz_90; - _zz_91[16] = _zz_90; - _zz_91[15] = _zz_90; - _zz_91[14] = _zz_90; - _zz_91[13] = _zz_90; - _zz_91[12] = _zz_90; - _zz_91[11] = _zz_90; - _zz_91[10] = _zz_90; - _zz_91[9] = _zz_90; - _zz_91[8] = _zz_90; - _zz_91[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_92 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_93[31] = _zz_92; - _zz_93[30] = _zz_92; - _zz_93[29] = _zz_92; - _zz_93[28] = _zz_92; - _zz_93[27] = _zz_92; - _zz_93[26] = _zz_92; - _zz_93[25] = _zz_92; - _zz_93[24] = _zz_92; - _zz_93[23] = _zz_92; - _zz_93[22] = _zz_92; - _zz_93[21] = _zz_92; - _zz_93[20] = _zz_92; - _zz_93[19] = _zz_92; - _zz_93[18] = _zz_92; - _zz_93[17] = _zz_92; - _zz_93[16] = _zz_92; - _zz_93[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_291) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_91; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_93; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3775,62 +3927,63 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_94 = {(((decode_INSTRUCTION & _zz_417) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}; - assign _zz_100 = _zz_94[2 : 1]; - assign _zz_56 = _zz_100; - assign _zz_101 = _zz_94[7 : 6]; - assign _zz_55 = _zz_101; - assign _zz_102 = _zz_94[9 : 8]; - assign _zz_54 = _zz_102; - assign _zz_103 = _zz_94[19 : 18]; - assign _zz_53 = _zz_103; - assign _zz_104 = _zz_94[22 : 21]; - assign _zz_52 = _zz_104; - assign _zz_105 = _zz_94[24 : 23]; - assign _zz_51 = _zz_105; - assign _zz_106 = _zz_94[27 : 26]; - assign _zz_50 = _zz_106; - assign _zz_107 = _zz_94[29 : 29]; - assign _zz_49 = _zz_107; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1) != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[34 : 34]; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_248; - assign decode_RegFilePlugin_rs2Data = _zz_249; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_108)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_108)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_108)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3839,355 +3992,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_109 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_109 = {31'd0, _zz_338}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_109 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_110 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_110 = {29'd0, _zz_339}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_110 = {27'd0, _zz_340}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_111 = _zz_341[11]; - always @ (*) begin - _zz_112[19] = _zz_111; - _zz_112[18] = _zz_111; - _zz_112[17] = _zz_111; - _zz_112[16] = _zz_111; - _zz_112[15] = _zz_111; - _zz_112[14] = _zz_111; - _zz_112[13] = _zz_111; - _zz_112[12] = _zz_111; - _zz_112[11] = _zz_111; - _zz_112[10] = _zz_111; - _zz_112[9] = _zz_111; - _zz_112[8] = _zz_111; - _zz_112[7] = _zz_111; - _zz_112[6] = _zz_111; - _zz_112[5] = _zz_111; - _zz_112[4] = _zz_111; - _zz_112[3] = _zz_111; - _zz_112[2] = _zz_111; - _zz_112[1] = _zz_111; - _zz_112[0] = _zz_111; - end - - assign _zz_113 = _zz_342[11]; - always @ (*) begin - _zz_114[19] = _zz_113; - _zz_114[18] = _zz_113; - _zz_114[17] = _zz_113; - _zz_114[16] = _zz_113; - _zz_114[15] = _zz_113; - _zz_114[14] = _zz_113; - _zz_114[13] = _zz_113; - _zz_114[12] = _zz_113; - _zz_114[11] = _zz_113; - _zz_114[10] = _zz_113; - _zz_114[9] = _zz_113; - _zz_114[8] = _zz_113; - _zz_114[7] = _zz_113; - _zz_114[6] = _zz_113; - _zz_114[5] = _zz_113; - _zz_114[4] = _zz_113; - _zz_114[3] = _zz_113; - _zz_114[2] = _zz_113; - _zz_114[1] = _zz_113; - _zz_114[0] = _zz_113; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_115 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_115 = _zz_41; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_343; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_116[0] = execute_SRC1[31]; - _zz_116[1] = execute_SRC1[30]; - _zz_116[2] = execute_SRC1[29]; - _zz_116[3] = execute_SRC1[28]; - _zz_116[4] = execute_SRC1[27]; - _zz_116[5] = execute_SRC1[26]; - _zz_116[6] = execute_SRC1[25]; - _zz_116[7] = execute_SRC1[24]; - _zz_116[8] = execute_SRC1[23]; - _zz_116[9] = execute_SRC1[22]; - _zz_116[10] = execute_SRC1[21]; - _zz_116[11] = execute_SRC1[20]; - _zz_116[12] = execute_SRC1[19]; - _zz_116[13] = execute_SRC1[18]; - _zz_116[14] = execute_SRC1[17]; - _zz_116[15] = execute_SRC1[16]; - _zz_116[16] = execute_SRC1[15]; - _zz_116[17] = execute_SRC1[14]; - _zz_116[18] = execute_SRC1[13]; - _zz_116[19] = execute_SRC1[12]; - _zz_116[20] = execute_SRC1[11]; - _zz_116[21] = execute_SRC1[10]; - _zz_116[22] = execute_SRC1[9]; - _zz_116[23] = execute_SRC1[8]; - _zz_116[24] = execute_SRC1[7]; - _zz_116[25] = execute_SRC1[6]; - _zz_116[26] = execute_SRC1[5]; - _zz_116[27] = execute_SRC1[4]; - _zz_116[28] = execute_SRC1[3]; - _zz_116[29] = execute_SRC1[2]; - _zz_116[30] = execute_SRC1[1]; - _zz_116[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); - always @ (*) begin - _zz_117[0] = memory_SHIFT_RIGHT[31]; - _zz_117[1] = memory_SHIFT_RIGHT[30]; - _zz_117[2] = memory_SHIFT_RIGHT[29]; - _zz_117[3] = memory_SHIFT_RIGHT[28]; - _zz_117[4] = memory_SHIFT_RIGHT[27]; - _zz_117[5] = memory_SHIFT_RIGHT[26]; - _zz_117[6] = memory_SHIFT_RIGHT[25]; - _zz_117[7] = memory_SHIFT_RIGHT[24]; - _zz_117[8] = memory_SHIFT_RIGHT[23]; - _zz_117[9] = memory_SHIFT_RIGHT[22]; - _zz_117[10] = memory_SHIFT_RIGHT[21]; - _zz_117[11] = memory_SHIFT_RIGHT[20]; - _zz_117[12] = memory_SHIFT_RIGHT[19]; - _zz_117[13] = memory_SHIFT_RIGHT[18]; - _zz_117[14] = memory_SHIFT_RIGHT[17]; - _zz_117[15] = memory_SHIFT_RIGHT[16]; - _zz_117[16] = memory_SHIFT_RIGHT[15]; - _zz_117[17] = memory_SHIFT_RIGHT[14]; - _zz_117[18] = memory_SHIFT_RIGHT[13]; - _zz_117[19] = memory_SHIFT_RIGHT[12]; - _zz_117[20] = memory_SHIFT_RIGHT[11]; - _zz_117[21] = memory_SHIFT_RIGHT[10]; - _zz_117[22] = memory_SHIFT_RIGHT[9]; - _zz_117[23] = memory_SHIFT_RIGHT[8]; - _zz_117[24] = memory_SHIFT_RIGHT[7]; - _zz_117[25] = memory_SHIFT_RIGHT[6]; - _zz_117[26] = memory_SHIFT_RIGHT[5]; - _zz_117[27] = memory_SHIFT_RIGHT[4]; - _zz_117[28] = memory_SHIFT_RIGHT[3]; - _zz_117[29] = memory_SHIFT_RIGHT[2]; - _zz_117[30] = memory_SHIFT_RIGHT[1]; - _zz_117[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_118 = 1'b0; - if(_zz_271)begin - if(_zz_272)begin - if(_zz_123)begin - _zz_118 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_273)begin - if(_zz_274)begin - if(_zz_125)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_275)begin - if(_zz_276)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_118 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_119 = 1'b0; - if(_zz_271)begin - if(_zz_272)begin - if(_zz_124)begin - _zz_119 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_273)begin - if(_zz_274)begin - if(_zz_126)begin - _zz_119 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_275)begin - if(_zz_276)begin - if(_zz_128)begin - _zz_119 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_119 = 1'b0; - end - end - - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_129 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_129 == 3'b000)) begin - _zz_130 = execute_BranchPlugin_eq; - end else if((_zz_129 == 3'b001)) begin - _zz_130 = (! execute_BranchPlugin_eq); - end else if((((_zz_129 & 3'b101) == 3'b101))) begin - _zz_130 = (! execute_SRC_LESS); - end else begin - _zz_130 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_131 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_131 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_131 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_131 = _zz_130; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_132 = _zz_350[11]; - always @ (*) begin - _zz_133[19] = _zz_132; - _zz_133[18] = _zz_132; - _zz_133[17] = _zz_132; - _zz_133[16] = _zz_132; - _zz_133[15] = _zz_132; - _zz_133[14] = _zz_132; - _zz_133[13] = _zz_132; - _zz_133[12] = _zz_132; - _zz_133[11] = _zz_132; - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; - end - - assign _zz_134 = _zz_351[19]; - always @ (*) begin - _zz_135[10] = _zz_134; - _zz_135[9] = _zz_134; - _zz_135[8] = _zz_134; - _zz_135[7] = _zz_134; - _zz_135[6] = _zz_134; - _zz_135[5] = _zz_134; - _zz_135[4] = _zz_134; - _zz_135[3] = _zz_134; - _zz_135[2] = _zz_134; - _zz_135[1] = _zz_134; - _zz_135[0] = _zz_134; - end - - assign _zz_136 = _zz_352[11]; - always @ (*) begin - _zz_137[18] = _zz_136; - _zz_137[17] = _zz_136; - _zz_137[16] = _zz_136; - _zz_137[15] = _zz_136; - _zz_137[14] = _zz_136; - _zz_137[13] = _zz_136; - _zz_137[12] = _zz_136; - _zz_137[11] = _zz_136; - _zz_137[10] = _zz_136; - _zz_137[9] = _zz_136; - _zz_137[8] = _zz_136; - _zz_137[7] = _zz_136; - _zz_137[6] = _zz_136; - _zz_137[5] = _zz_136; - _zz_137[4] = _zz_136; - _zz_137[3] = _zz_136; - _zz_137[2] = _zz_136; - _zz_137[1] = _zz_136; - _zz_137[0] = _zz_136; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_138 = (_zz_353[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_138 = _zz_354[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_138 = _zz_355[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -4196,183 +4372,195 @@ module VexRiscv ( endcase end - assign _zz_139 = _zz_356[11]; - always @ (*) begin - _zz_140[19] = _zz_139; - _zz_140[18] = _zz_139; - _zz_140[17] = _zz_139; - _zz_140[16] = _zz_139; - _zz_140[15] = _zz_139; - _zz_140[14] = _zz_139; - _zz_140[13] = _zz_139; - _zz_140[12] = _zz_139; - _zz_140[11] = _zz_139; - _zz_140[10] = _zz_139; - _zz_140[9] = _zz_139; - _zz_140[8] = _zz_139; - _zz_140[7] = _zz_139; - _zz_140[6] = _zz_139; - _zz_140[5] = _zz_139; - _zz_140[4] = _zz_139; - _zz_140[3] = _zz_139; - _zz_140[2] = _zz_139; - _zz_140[1] = _zz_139; - _zz_140[0] = _zz_139; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_594,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_595,_zz_596},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_359}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_141 = _zz_357[19]; - always @ (*) begin - _zz_142[10] = _zz_141; - _zz_142[9] = _zz_141; - _zz_142[8] = _zz_141; - _zz_142[7] = _zz_141; - _zz_142[6] = _zz_141; - _zz_142[5] = _zz_141; - _zz_142[4] = _zz_141; - _zz_142[3] = _zz_141; - _zz_142[2] = _zz_141; - _zz_142[1] = _zz_141; - _zz_142[0] = _zz_141; - end - - assign _zz_143 = _zz_358[11]; - always @ (*) begin - _zz_144[18] = _zz_143; - _zz_144[17] = _zz_143; - _zz_144[16] = _zz_143; - _zz_144[15] = _zz_143; - _zz_144[14] = _zz_143; - _zz_144[13] = _zz_143; - _zz_144[12] = _zz_143; - _zz_144[11] = _zz_143; - _zz_144[10] = _zz_143; - _zz_144[9] = _zz_143; - _zz_144[8] = _zz_143; - _zz_144[7] = _zz_143; - _zz_144[6] = _zz_143; - _zz_144[5] = _zz_143; - _zz_144[4] = _zz_143; - _zz_144[3] = _zz_143; - _zz_144[2] = _zz_143; - _zz_144[1] = _zz_143; - _zz_144[0] = _zz_143; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; - always @ (*) begin + always @(*) begin BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); - if(1'b0)begin + if(when_BranchPlugin_l296) begin BranchPlugin_branchExceptionPort_valid = 1'b0; end end assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign when_BranchPlugin_l296 = 1'b0; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_149 = _zz_360[0]; - assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_151 = _zz_362[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_261)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_264)begin + if(_zz_when_1) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4383,8 +4571,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4394,199 +4582,208 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_csr_2820) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2821) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_csr_2822) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2823) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_csr_2824) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2825) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_csr_2826) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2827) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_csr_2828) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2829) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_csr_2830) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2831) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_csr_2832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2833) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_2834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_2835) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_277)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_278)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_279)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_278)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_279)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4599,106 +4796,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_277)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_277)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_292) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); - assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_364; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; - assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_168 = _zz_365[7]; - always @ (*) begin - _zz_169[23] = _zz_168; - _zz_169[22] = _zz_168; - _zz_169[21] = _zz_168; - _zz_169[20] = _zz_168; - _zz_169[19] = _zz_168; - _zz_169[18] = _zz_168; - _zz_169[17] = _zz_168; - _zz_169[16] = _zz_168; - _zz_169[15] = _zz_168; - _zz_169[14] = _zz_168; - _zz_169[13] = _zz_168; - _zz_169[12] = _zz_168; - _zz_169[11] = _zz_168; - _zz_169[10] = _zz_168; - _zz_169[9] = _zz_168; - _zz_169[8] = _zz_168; - _zz_169[7] = _zz_168; - _zz_169[6] = _zz_168; - _zz_169[5] = _zz_168; - _zz_169[4] = _zz_168; - _zz_169[3] = _zz_168; - _zz_169[2] = _zz_168; - _zz_169[1] = _zz_168; - _zz_169[0] = _zz_168; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : begin - _zz_170 = execute_RS2; - end - default : begin - _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 24]}; - end - endcase - end - - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; - assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); - assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); - assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); - assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); - always @ (*) begin - CfuPlugin_joinException_valid = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if(memory_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); - end - end - end - - assign CfuPlugin_joinException_payload_code = 4'b1111; - assign CfuPlugin_joinException_payload_badAddr = 32'h0; - always @ (*) begin - memory_CfuPlugin_rsp_ready = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); - end - end - assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_280) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4711,8 +4851,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_280) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4731,58 +4871,69 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_366) + $signed(_zz_367)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_256)begin - if(_zz_281)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_282)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_372); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_373 : _zz_374); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_375[31:0]; - assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_175[31 : 0] = execute_RS1; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; end - assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_177 != 32'h0); - always @ (*) begin + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_283) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end end @@ -4792,9 +4943,9 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_178))begin + if(when_DebugPlugin_l244) begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4803,12 +4954,13 @@ module VexRiscv ( end end - always @ (*) begin + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_283) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin IBusCachedPlugin_injectionPort_valid = 1'b1; end end @@ -4819,38 +4971,182 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_29 = decode_SRC1_CTRL; - assign _zz_27 = _zz_56; - assign _zz_43 = decode_to_execute_SRC1_CTRL; - assign _zz_26 = decode_ALU_CTRL; - assign _zz_24 = _zz_55; - assign _zz_44 = decode_to_execute_ALU_CTRL; - assign _zz_23 = decode_SRC2_CTRL; - assign _zz_21 = _zz_54; - assign _zz_42 = decode_to_execute_SRC2_CTRL; - assign _zz_20 = decode_ALU_BITWISE_CTRL; - assign _zz_18 = _zz_53; - assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_17 = decode_SHIFT_CTRL; - assign _zz_14 = execute_SHIFT_CTRL; - assign _zz_15 = _zz_52; - assign _zz_40 = decode_to_execute_SHIFT_CTRL; - assign _zz_39 = execute_to_memory_SHIFT_CTRL; - assign _zz_12 = decode_BRANCH_CTRL; - assign _zz_58 = _zz_51; - assign _zz_36 = decode_to_execute_BRANCH_CTRL; - assign _zz_10 = decode_ENV_CTRL; - assign _zz_7 = execute_ENV_CTRL; - assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_50; - assign _zz_34 = decode_to_execute_ENV_CTRL; - assign _zz_33 = execute_to_memory_ENV_CTRL; - assign _zz_35 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_49; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready); + assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)); + assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + end + + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2; + end + default : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @(*) begin + CfuPlugin_bus_rsp_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); + assign when_GenCoreDefault_l367 = _zz_when_GenCoreDefault_l367[0]; + assign when_GenCoreDefault_l367_1 = _zz_when_GenCoreDefault_l367_1[0]; + assign when_GenCoreDefault_l367_2 = _zz_when_GenCoreDefault_l367_2[0]; + assign when_GenCoreDefault_l367_3 = _zz_when_GenCoreDefault_l367_3[0]; + assign when_GenCoreDefault_l367_4 = _zz_when_GenCoreDefault_l367_4[0]; + assign when_GenCoreDefault_l367_5 = _zz_when_GenCoreDefault_l367_5[0]; + assign when_GenCoreDefault_l367_6 = _zz_when_GenCoreDefault_l367_6[0]; + assign when_GenCoreDefault_l367_7 = _zz_when_GenCoreDefault_l367_7[0]; + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_64 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4871,9 +5167,15 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_179) + case(switch_Fetcher_l362) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4882,296 +5184,340 @@ module VexRiscv ( endcase end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_180[12 : 0] = 13'h1000; - _zz_180[25 : 20] = 6'h20; + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_28 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_29 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_30 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_31 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_32 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_33 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_34 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_35 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_36 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_37 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_38 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_39 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[13 : 0] = 14'h2000; + _zz_CsrPlugin_csrMapping_readDataInit_10[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_181[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_182[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_183[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_184[31 : 30] = CsrPlugin_misa_base; - _zz_184[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_14[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_15[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_186 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_186[11 : 11] = CsrPlugin_mip_MEIP; - _zz_186[7 : 7] = CsrPlugin_mip_MTIP; - _zz_186[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_187 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_187[11 : 11] = CsrPlugin_mie_MEIE; - _zz_187[7 : 7] = CsrPlugin_mie_MTIE; - _zz_187[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_188 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_188[31 : 2] = CsrPlugin_mtvec_base; - _zz_188[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_189 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_189[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_190 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_190[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_191 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_21[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_192 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_192[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_193 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_194 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_195 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_196 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_197 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_198 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_28[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_199 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_29 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_29[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_200 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_30 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_30[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_201 = 32'h0; - if(execute_CsrPlugin_csr_2820)begin - _zz_201[31 : 0] = _zz_152; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_31 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_31[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_202 = 32'h0; - if(execute_CsrPlugin_csr_2822)begin - _zz_202[31 : 0] = _zz_154; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_32 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_32[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - always @ (*) begin - _zz_203 = 32'h0; - if(execute_CsrPlugin_csr_2824)begin - _zz_203[31 : 0] = _zz_156; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_33 = 32'h0; + if(execute_CsrPlugin_csr_2820) begin + _zz_CsrPlugin_csrMapping_readDataInit_33[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; end end - always @ (*) begin - _zz_204 = 32'h0; - if(execute_CsrPlugin_csr_2826)begin - _zz_204[31 : 0] = _zz_158; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_34 = 32'h0; + if(execute_CsrPlugin_csr_2822) begin + _zz_CsrPlugin_csrMapping_readDataInit_34[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; end end - always @ (*) begin - _zz_205 = 32'h0; - if(execute_CsrPlugin_csr_2828)begin - _zz_205[31 : 0] = _zz_160; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_35 = 32'h0; + if(execute_CsrPlugin_csr_2824) begin + _zz_CsrPlugin_csrMapping_readDataInit_35[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_4; end end - always @ (*) begin - _zz_206 = 32'h0; - if(execute_CsrPlugin_csr_2830)begin - _zz_206[31 : 0] = _zz_162; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_36 = 32'h0; + if(execute_CsrPlugin_csr_2826) begin + _zz_CsrPlugin_csrMapping_readDataInit_36[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_5; end end - always @ (*) begin - _zz_207 = 32'h0; - if(execute_CsrPlugin_csr_2832)begin - _zz_207[31 : 0] = _zz_164; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_37 = 32'h0; + if(execute_CsrPlugin_csr_2828) begin + _zz_CsrPlugin_csrMapping_readDataInit_37[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_6; end end - always @ (*) begin - _zz_208 = 32'h0; - if(execute_CsrPlugin_csr_2834)begin - _zz_208[31 : 0] = _zz_166; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_38 = 32'h0; + if(execute_CsrPlugin_csr_2830) begin + _zz_CsrPlugin_csrMapping_readDataInit_38[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_7; end end - always @ (*) begin - _zz_209 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_209[31 : 0] = _zz_176; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_39 = 32'h0; + if(execute_CsrPlugin_csr_2832) begin + _zz_CsrPlugin_csrMapping_readDataInit_39[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_8; end end - always @ (*) begin - _zz_210 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_210[31 : 0] = _zz_177; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_40 = 32'h0; + if(execute_CsrPlugin_csr_2834) begin + _zz_CsrPlugin_csrMapping_readDataInit_40[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_9; end end - assign execute_CsrPlugin_readData = (((((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_597 | _zz_184) | (_zz_185 | _zz_186))) | (((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194)))) | ((((_zz_195 | _zz_196) | (_zz_197 | _zz_198)) | ((_zz_199 | _zz_200) | (_zz_201 | _zz_202))) | (((_zz_203 | _zz_204) | (_zz_205 | _zz_206)) | ((_zz_207 | _zz_208) | (_zz_209 | _zz_210))))); - assign iBusWishbone_ADR = {_zz_392,_zz_211}; - assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | (_zz_CsrPlugin_csrMapping_readDataInit_12 | _zz_CsrPlugin_csrMapping_readDataInit_13)) | ((_zz_CsrPlugin_csrMapping_readDataInit_41 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26) | (_zz_CsrPlugin_csrMapping_readDataInit_27 | _zz_CsrPlugin_csrMapping_readDataInit_28)) | ((_zz_CsrPlugin_csrMapping_readDataInit_29 | _zz_CsrPlugin_csrMapping_readDataInit_30) | (_zz_CsrPlugin_csrMapping_readDataInit_31 | _zz_CsrPlugin_csrMapping_readDataInit_32))) | (((_zz_CsrPlugin_csrMapping_readDataInit_33 | _zz_CsrPlugin_csrMapping_readDataInit_34) | (_zz_CsrPlugin_csrMapping_readDataInit_35 | _zz_CsrPlugin_csrMapping_readDataInit_36)) | ((_zz_CsrPlugin_csrMapping_readDataInit_37 | _zz_CsrPlugin_csrMapping_readDataInit_38) | (_zz_CsrPlugin_csrMapping_readDataInit_39 | _zz_CsrPlugin_csrMapping_readDataInit_40))))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_284)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_284)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_212; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_218 = (dBus_cmd_payload_length != 3'b000); - assign _zz_214 = dBus_cmd_valid; - assign _zz_216 = dBus_cmd_payload_wr; - assign _zz_217 = (_zz_213 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_215 && (_zz_216 || _zz_217)); - assign dBusWishbone_ADR = ((_zz_218 ? {{dBus_cmd_payload_address[31 : 5],_zz_213},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_218 ? (_zz_217 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_216 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_216; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_215 = (_zz_214 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_214; - assign dBusWishbone_STB = _zz_214; - assign dBus_rsp_valid = _zz_219; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_72 <= 1'b0; - _zz_74 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_87; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_88; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_108 <= 1'b1; - _zz_120 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -5191,165 +5537,165 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - memory_DivPlugin_div_counter_value <= 6'h0; - _zz_176 <= 32'h0; + CfuPlugin_bus_rsp_rValid <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_179 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_211 <= 3'b000; - _zz_212 <= 1'b0; - _zz_213 <= 3'b000; - _zz_219 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_72 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_70)begin - _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_74 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_74 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_285)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_108 <= 1'b0; - _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_286)begin - if(_zz_287)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_288)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_289)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5360,8 +5706,8 @@ module VexRiscv ( end endcase end - if(_zz_267)begin - case(_zz_269) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5371,185 +5717,181 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(execute_CfuPlugin_schedule)begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(execute_CfuPlugin_schedule) begin execute_CfuPlugin_hold <= 1'b1; end - if(CfuPlugin_bus_cmd_ready)begin + if(CfuPlugin_bus_cmd_ready) begin execute_CfuPlugin_hold <= 1'b0; end - if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + if(CfuPlugin_bus_cmd_fire) begin execute_CfuPlugin_fired <= 1'b1; end - if((! execute_arbitration_isStuckByOthers))begin + if(when_CfuPlugin_l171) begin execute_CfuPlugin_fired <= 1'b0; end - if(memory_CfuPlugin_rsp_ready)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + if(CfuPlugin_bus_rsp_valid) begin + CfuPlugin_bus_rsp_rValid <= 1'b1; end - if(_zz_290)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + if(CfuPlugin_bus_rsp_rsp_ready) begin + CfuPlugin_bus_rsp_rValid <= 1'b0; end - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + if(when_Pipeline_l124_62) begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_179) + case(switch_Fetcher_l362) 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_179 <= 3'b001; + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; end end 3'b001 : begin - _zz_179 <= 3'b010; + switch_Fetcher_l362 <= 3'b010; end 3'b010 : begin - _zz_179 <= 3'b011; + switch_Fetcher_l362 <= 3'b011; end 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_179 <= 3'b100; + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; end end 3'b100 : begin - _zz_179 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; end default : begin end endcase - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_385[0]; - CsrPlugin_mstatus_MIE <= _zz_386[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_388[0]; - CsrPlugin_mie_MTIE <= _zz_389[0]; - CsrPlugin_mie_MSIE <= _zz_390[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_284)begin - if(iBusWishbone_ACK)begin - _zz_211 <= (_zz_211 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_214 && _zz_215))begin - _zz_213 <= (_zz_213 + 3'b001); - if(_zz_217)begin - _zz_213 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_219 <= ((_zz_214 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_75 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_285)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_121 <= _zz_46[11 : 7]; - _zz_122 <= _zz_57; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_261)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(_zz_264)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_when_1) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; - end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_286)begin - if(_zz_287)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_288)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_289)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5557,569 +5899,579 @@ module VexRiscv ( end endcase end - if(_zz_153[0])begin - _zz_152 <= (_zz_152 + 32'h00000001); + if(when_MulDivIterativePlugin_l126) begin + memory_DivPlugin_div_done <= 1'b1; end - if(_zz_155[0])begin - _zz_154 <= (_zz_154 + 32'h00000001); + if(when_MulDivIterativePlugin_l126_1) begin + memory_DivPlugin_div_done <= 1'b0; end - if(_zz_157[0])begin - _zz_156 <= (_zz_156 + 32'h00000001); + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; + end + end end - if(_zz_159[0])begin - _zz_158 <= (_zz_158 + 32'h00000001); + if(when_MulDivIterativePlugin_l162) begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end - if(_zz_161[0])begin - _zz_160 <= (_zz_160 + 32'h00000001); + externalInterruptArray_regNext <= externalInterruptArray; + if(CfuPlugin_bus_rsp_ready) begin + CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end - if(_zz_163[0])begin - _zz_162 <= (_zz_162 + 32'h00000001); + if(when_GenCoreDefault_l367) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= (_zz_CsrPlugin_csrMapping_readDataInit_2 + 32'h00000001); end - if(_zz_165[0])begin - _zz_164 <= (_zz_164 + 32'h00000001); + if(when_GenCoreDefault_l367_1) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= (_zz_CsrPlugin_csrMapping_readDataInit_3 + 32'h00000001); end - if(_zz_167[0])begin - _zz_166 <= (_zz_166 + 32'h00000001); + if(when_GenCoreDefault_l367_2) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= (_zz_CsrPlugin_csrMapping_readDataInit_4 + 32'h00000001); end - if(_zz_290)begin - CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + if(when_GenCoreDefault_l367_3) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= (_zz_CsrPlugin_csrMapping_readDataInit_5 + 32'h00000001); end - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_done <= 1'b1; + if(when_GenCoreDefault_l367_4) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= (_zz_CsrPlugin_csrMapping_readDataInit_6 + 32'h00000001); end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + if(when_GenCoreDefault_l367_5) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= (_zz_CsrPlugin_csrMapping_readDataInit_7 + 32'h00000001); end - if(_zz_256)begin - if(_zz_281)begin - memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; - memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_376[31:0]; - end - end + if(when_GenCoreDefault_l367_6) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= (_zz_CsrPlugin_csrMapping_readDataInit_8 + 32'h00000001); end - if(_zz_282)begin - memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_382); - memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_384); - memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(when_GenCoreDefault_l367_7) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= (_zz_CsrPlugin_csrMapping_readDataInit_9 + 32'h00000001); end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_41; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_8) begin memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_28; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_25; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_22; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_16; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_11; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + end + if(when_Pipeline_l124_45) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_52) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_53) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + if(when_Pipeline_l124_54) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + if(when_Pipeline_l124_55) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_63) begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + end + if(when_Pipeline_l124_64) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if(when_CsrPlugin_l1264_23) begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(when_CsrPlugin_l1264_24) begin execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_25) begin execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_26) begin execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_27) begin execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_28) begin execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_29) begin execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_30) begin execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_31) begin execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_32) begin execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_33) begin execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_34) begin execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_35) begin execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_36) begin execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_37) begin execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_38) begin execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_39) begin execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); - end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_387[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_391[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2820)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2820) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2821) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2822)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2822) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2823) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_1 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2824)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2824) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2825) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2826)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2826) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2827) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2828)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2828) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2829) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2830)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2830) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2831) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2832)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2832) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2833) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2834)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2834) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2835) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end - always @ (posedge clk) begin + always @(posedge clk) begin DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin + if(debug_bus_cmd_ready) begin DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_57; + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; end - _zz_178 <= debug_bus_cmd_payload_address[2]; - if(_zz_263)begin + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin + always @(posedge clk) begin if(debugReset) begin DebugPlugin_resetIt <= 1'b0; DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + if(when_DebugPlugin_l225) begin DebugPlugin_godmode <= 1'b1; end - if(debug_bus_cmd_valid)begin - case(_zz_283) + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin + if(when_DebugPlugin_l260) begin DebugPlugin_resetIt <= 1'b1; end - if(debug_bus_cmd_payload_data[24])begin + if(when_DebugPlugin_l260_1) begin DebugPlugin_resetIt <= 1'b0; end - if(debug_bus_cmd_payload_data[17])begin + if(when_DebugPlugin_l261) begin DebugPlugin_haltIt <= 1'b1; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l261_1) begin DebugPlugin_haltIt <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l262) begin DebugPlugin_haltedByBreak <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l263) begin DebugPlugin_godmode <= 1'b0; end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end end end default : begin end endcase end - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_268)begin - if(decode_arbitration_isValid)begin + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin DebugPlugin_haltIt <= 1'b1; end end @@ -6132,9 +6484,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -6156,6 +6507,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -6171,9 +6523,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -6181,7 +6534,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -6190,99 +6543,81 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_19; - reg [31:0] _zz_20; - reg [21:0] _zz_21; - reg [31:0] _zz_22; - wire _zz_23; - wire _zz_24; - wire _zz_25; - wire _zz_26; - wire _zz_27; - wire _zz_28; - wire _zz_29; - wire [0:0] _zz_30; - wire [0:0] _zz_31; - wire [0:0] _zz_32; - wire [0:0] _zz_33; - wire [0:0] _zz_34; - wire [0:0] _zz_35; - wire [2:0] _zz_36; - wire [2:0] _zz_37; - wire [21:0] _zz_38; - wire [21:0] _zz_39; + reg [20:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [20:0] _zz_ways_0_tags_port; + wire [10:0] _zz_stage0_dataColisions; + wire [10:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; - reg _zz_3; - reg _zz_4; wire haltCpu; reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; + reg [7:0] tagsReadCmd_payload; reg tagsWriteCmd_valid; - reg [1:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; + reg [0:0] tagsWriteCmd_payload_way; + reg [7:0] tagsWriteCmd_payload_address; reg tagsWriteCmd_payload_data_valid; reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; + reg [18:0] tagsWriteCmd_payload_data_address; reg tagsWriteLastCmd_valid; - reg [1:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [7:0] tagsWriteLastCmd_payload_address; reg tagsWriteLastCmd_payload_data_valid; reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; + reg [18:0] tagsWriteLastCmd_payload_data_address; reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; + reg [10:0] dataReadCmd_payload; reg dataWriteCmd_valid; - reg [1:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; + reg [0:0] dataWriteCmd_payload_way; + reg [10:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_5; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_6; - wire _zz_7; + wire [18:0] ways_0_tagsReadRsp_address; + wire [20:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; - wire _zz_8; - wire ways_1_tagsReadRsp_valid; - wire ways_1_tagsReadRsp_error; - wire [19:0] ways_1_tagsReadRsp_address; - wire [21:0] _zz_9; - wire _zz_10; - wire [31:0] ways_1_dataReadRspMem; - wire [31:0] ways_1_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_11; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; - reg [1:0] stage0_dataColisions; - wire [9:0] _zz_12; - wire [3:0] _zz_13; - wire [1:0] stage0_wayInvalidate; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; - wire [1:0] stageA_wayHits; - reg [1:0] _zz_14; - reg [1:0] stageA_wayInvalidate; - reg [1:0] stage0_dataColisions_regNextWhen; - reg [1:0] _zz_15; - wire [9:0] _zz_16; - wire [3:0] _zz_17; - wire [1:0] stageA_dataColisions; + wire [0:0] stageA_wayHits; + wire when_DataCache_l763_2; + reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_stageA_dataColisions; + wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -6292,27 +6627,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg stageB_tagsReadRsp_1_valid; - reg stageB_tagsReadRsp_1_error; - reg [19:0] stageB_tagsReadRsp_1_address; + reg [18:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; - reg [31:0] stageB_dataReadRsp_1; - reg [1:0] stageB_wayInvalidate; + wire when_DataCache_l812; + reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; - reg [1:0] stageB_dataColisions; + wire when_DataCache_l812_1; + reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; - reg [1:0] stageB_waysHitsBeforeInvalidate; - wire [1:0] stageB_waysHits; + wire when_DataCache_l812_3; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [8:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -6320,10 +6661,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - reg [1:0] _zz_18; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -6331,432 +6680,359 @@ module DataCache ( reg [2:0] loader_counter_value; wire loader_counter_willOverflowIfInc; wire loader_counter_willOverflow; - reg [1:0] loader_waysAllocator; + reg [0:0] loader_waysAllocator; reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_40; - reg [7:0] _zz_41; - reg [7:0] _zz_42; - reg [7:0] _zz_43; - (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol3 [0:1023]; - reg [7:0] _zz_44; - reg [7:0] _zz_45; - reg [7:0] _zz_46; - reg [7:0] _zz_47; - - assign _zz_23 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_24 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_25 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_26 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_27 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_28 = (! stageB_flusher_hold); - assign _zz_29 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_30 = _zz_6[0 : 0]; - assign _zz_31 = _zz_6[1 : 1]; - assign _zz_32 = _zz_9[0 : 0]; - assign _zz_33 = _zz_9[1 : 1]; - assign _zz_34 = 1'b1; - assign _zz_35 = loader_counter_willIncrement; - assign _zz_36 = {2'd0, _zz_35}; - assign _zz_37 = {loader_waysAllocator,loader_waysAllocator[1]}; - assign _zz_38 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - assign _zz_39 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_5) begin - _zz_19 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin - if(_zz_4) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_38; - end - end - - always @ (*) begin - _zz_20 = {_zz_43, _zz_42, _zz_41, _zz_40}; - end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_40 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_41 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_42 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_43 <= ways_0_data_symbol3[dataReadCmd_payload]; - end - end - - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_3) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_3) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_3) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_3) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end - end - - always @ (posedge clk) begin - if(_zz_8) begin - _zz_21 <= ways_1_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + wire when_DataCache_l1107; + wire when_DataCache_l1110; + (* ram_style = "block" *) reg [20:0] ways_0_tags [0:255]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:2047]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[12 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[12 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_1_tags[tagsWriteCmd_payload_address] <= _zz_39; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_22 = {_zz_47, _zz_46, _zz_45, _zz_44}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_10) begin - _zz_44 <= ways_1_data_symbol0[dataReadCmd_payload]; - _zz_45 <= ways_1_data_symbol1[dataReadCmd_payload]; - _zz_46 <= ways_1_data_symbol2[dataReadCmd_payload]; - _zz_47 <= ways_1_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin - ways_1_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end if(dataWriteCmd_payload_mask[1] && _zz_1) begin - ways_1_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end if(dataWriteCmd_payload_mask[2] && _zz_1) begin - ways_1_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end if(dataWriteCmd_payload_mask[3] && _zz_1) begin - ways_1_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[1]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[1]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end - always @ (*) begin - _zz_3 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_3 = 1'b1; - end - end - - always @ (*) begin - _zz_4 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_4 = 1'b1; - end - end - assign haltCpu = 1'b0; - assign _zz_5 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_6 = _zz_19; - assign ways_0_tagsReadRsp_valid = _zz_30[0]; - assign ways_0_tagsReadRsp_error = _zz_31[0]; - assign ways_0_tagsReadRsp_address = _zz_6[21 : 2]; - assign _zz_7 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_20; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[20 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - assign _zz_8 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_9 = _zz_21; - assign ways_1_tagsReadRsp_valid = _zz_32[0]; - assign ways_1_tagsReadRsp_error = _zz_33[0]; - assign ways_1_tagsReadRsp_address = _zz_9[21 : 2]; - assign _zz_10 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_1_dataReadRspMem = _zz_22; - assign ways_1_dataReadRsp = ways_1_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_23)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_23)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + always @(*) begin + tagsReadCmd_payload = 8'bxxxxxxxx; + if(when_DataCache_l656) begin + tagsReadCmd_payload = io_cpu_execute_address[12 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_23)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_23)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + always @(*) begin + dataReadCmd_payload = 11'bxxxxxxxxxxx; + if(when_DataCache_l656) begin + dataReadCmd_payload = io_cpu_execute_address[12 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_24)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin - tagsWriteCmd_payload_way = 2'bxx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = 2'b11; + always @(*) begin + tagsWriteCmd_payload_way = 1'bx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 8'bxxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[7:0]; end - if(loader_done)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + if(loader_done) begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[12 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + always @(*) begin + tagsWriteCmd_payload_data_address = 19'bxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 13]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_24)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin - dataWriteCmd_payload_way = 2'bxx; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + always @(*) begin + dataWriteCmd_payload_address = 11'bxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[12 : 2]; end - if(_zz_25)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + if(when_DataCache_l1075) begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[12 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_34[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_11 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_11 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_11 = 4'b1111; end endcase end - assign stage0_mask = (_zz_11 <<< io_cpu_execute_address[1 : 0]); - assign _zz_12 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_13 = dataWriteCmd_payload_mask[3 : 0]; - always @ (*) begin - stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); - stage0_dataColisions[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); - end - - assign stage0_wayInvalidate = 2'b00; + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - always @ (*) begin - _zz_14[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - _zz_14[1] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_1_tagsReadRsp_address) && ways_1_tagsReadRsp_valid); - end - - assign stageA_wayHits = _zz_14; - assign _zz_16 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_17 = dataWriteCmd_payload_mask[3 : 0]; - always @ (*) begin - _zz_15[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); - _zz_15[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); - end - - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_15); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 13] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); - assign stageB_waysHit = (stageB_waysHits != 2'b00); - assign stageB_dataMux = (stageB_waysHits[0] ? stageB_dataReadRsp_0 : stageB_dataReadRsp_1); - always @ (*) begin + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(! _zz_27) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_26)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_27)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[8]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[8]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -6764,89 +7040,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 2'b00)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_18) != 2'b00) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_26)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_27)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6854,12 +7114,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(! _zz_27) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6870,24 +7130,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - always @ (*) begin - _zz_18[0] = stageB_tagsReadRsp_0_error; - _zz_18[1] = stageB_tagsReadRsp_1_error; - end - - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_25)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6895,45 +7171,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_36); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6944,105 +7222,89 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_1_valid <= ways_1_tagsReadRsp_valid; - stageB_tagsReadRsp_1_error <= ways_1_tagsReadRsp_error; - stageB_tagsReadRsp_1_address <= ways_1_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_1 <= ways_1_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_28)begin - if(_zz_29)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 9'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; - loader_waysAllocator <= 2'b01; + loader_waysAllocator <= 1'b1; loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_28)begin - if(! _zz_29) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 9'h001); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 9'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_25)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_37[1:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -7089,88 +7351,61 @@ module InstructionCache ( input io_mem_rsp_valid, input [31:0] io_mem_rsp_payload_data, input io_mem_rsp_payload_error, - input [2:0] _zz_16, - input [31:0] _zz_17, + input [2:0] _zz_when_Fetcher_l398, + input [31:0] _zz_io_cpu_fetch_data_regNextWhen, input clk, input reset ); - reg [31:0] _zz_18; - reg [31:0] _zz_19; - reg [21:0] _zz_20; - reg [21:0] _zz_21; - reg _zz_22; - reg [31:0] _zz_23; - wire _zz_24; - wire _zz_25; - wire [0:0] _zz_26; - wire [0:0] _zz_27; - wire [0:0] _zz_28; - wire [0:0] _zz_29; - wire [21:0] _zz_30; - wire [21:0] _zz_31; + reg [31:0] _zz_banks_0_port1; + reg [20:0] _zz_ways_0_tags_port1; + wire [20:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; - reg _zz_3; - reg _zz_4; reg lineLoader_fire; reg lineLoader_valid; (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_5; + reg [8:0] lineLoader_flushCounter; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; - reg [0:0] lineLoader_wayToAllocate_valueNext; - reg [0:0] lineLoader_wayToAllocate_value; wire lineLoader_wayToAllocate_willOverflowIfInc; wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; + wire [7:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_tag_1_valid; - wire [6:0] lineLoader_write_tag_1_payload_address; - wire lineLoader_write_tag_1_payload_data_valid; - wire lineLoader_write_tag_1_payload_data_error; - wire [19:0] lineLoader_write_tag_1_payload_data_address; + wire [18:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; + wire [10:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire lineLoader_write_data_1_valid; - wire [9:0] lineLoader_write_data_1_payload_address; - wire [31:0] lineLoader_write_data_1_payload_data; - wire [9:0] _zz_6; - wire _zz_7; + wire when_InstructionCache_l401; + wire [10:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [9:0] _zz_8; - wire _zz_9; - wire [31:0] fetchStage_read_banksValue_1_dataMem; - wire [31:0] fetchStage_read_banksValue_1_data; - wire [6:0] _zz_10; - wire _zz_11; + wire [7:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_12; - wire [6:0] _zz_13; - wire _zz_14; - wire fetchStage_read_waysValues_1_tag_valid; - wire fetchStage_read_waysValues_1_tag_error; - wire [19:0] fetchStage_read_waysValues_1_tag_address; - wire [21:0] _zz_15; + wire [18:0] fetchStage_read_waysValues_0_tag_address; + wire [20:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; - wire fetchStage_hit_hits_1; wire fetchStage_hit_valid; - wire [0:0] fetchStage_hit_wayId; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -7180,258 +7415,183 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; - (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; - (* ram_style = "block" *) reg [31:0] banks_1 [0:1023]; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; - - assign _zz_24 = (! lineLoader_flushCounter[7]); - assign _zz_25 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_26 = _zz_12[0 : 0]; - assign _zz_27 = _zz_12[1 : 1]; - assign _zz_28 = _zz_15[0 : 0]; - assign _zz_29 = _zz_15[1 : 1]; - assign _zz_30 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - assign _zz_31 = {lineLoader_write_tag_1_payload_data_address,{lineLoader_write_tag_1_payload_data_error,lineLoader_write_tag_1_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2) begin - banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_7) begin - _zz_18 <= banks_0[_zz_6]; - end - end + wire when_Fetcher_l398; + (* ram_style = "block" *) reg [31:0] banks_0 [0:2047]; + (* ram_style = "block" *) reg [20:0] ways_0_tags [0:255]; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin - banks_1[lineLoader_write_data_1_payload_address] <= lineLoader_write_data_1_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_9) begin - _zz_19 <= banks_1[_zz_8]; - end - end - - always @ (posedge clk) begin - if(_zz_4) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_30; + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_11) begin - _zz_20 <= ways_0_tags[_zz_10]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin - if(_zz_3) begin - ways_1_tags[lineLoader_write_tag_1_payload_address] <= _zz_31; + always @(posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_14) begin - _zz_21 <= ways_1_tags[_zz_13]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end always @(*) begin - case(fetchStage_hit_wayId) - 1'b0 : begin - _zz_22 = fetchStage_read_waysValues_0_tag_error; - _zz_23 = fetchStage_read_banksValue_0_data; - end - default : begin - _zz_22 = fetchStage_read_waysValues_1_tag_error; - _zz_23 = fetchStage_read_banksValue_1_data; - end - endcase - end - - always @ (*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_1_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin - _zz_3 = 1'b0; - if(lineLoader_write_tag_1_valid)begin - _zz_3 = 1'b1; - end - end - - always @ (*) begin - _zz_4 = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_4 = 1'b1; - end - end - - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_24)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_5))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[8]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = (lineLoader_wayToAllocate_value == 1'b1); + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - always @ (*) begin - lineLoader_wayToAllocate_valueNext = (lineLoader_wayToAllocate_value + lineLoader_wayToAllocate_willIncrement); - if(lineLoader_wayToAllocate_willClear)begin - lineLoader_wayToAllocate_valueNext = 1'b0; - end - end - - assign lineLoader_write_tag_0_valid = (((lineLoader_wayToAllocate_value == 1'b0) && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[8])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[8] ? lineLoader_address[12 : 5] : lineLoader_flushCounter[7 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[8]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_tag_1_valid = (((lineLoader_wayToAllocate_value == 1'b1) && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_1_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_1_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_1_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_1_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b0)); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 13]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[12 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign lineLoader_write_data_1_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b1)); - assign lineLoader_write_data_1_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_1_payload_data = io_mem_rsp_payload_data; - assign _zz_6 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_18; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[12 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_8 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_1_dataMem = _zz_19; - assign fetchStage_read_banksValue_1_data = fetchStage_read_banksValue_1_dataMem[31 : 0]; - assign _zz_10 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_11 = (! io_cpu_fetch_isStuck); - assign _zz_12 = _zz_20; - assign fetchStage_read_waysValues_0_tag_valid = _zz_26[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_27[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_12[21 : 2]; - assign _zz_13 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_14 = (! io_cpu_fetch_isStuck); - assign _zz_15 = _zz_21; - assign fetchStage_read_waysValues_1_tag_valid = _zz_28[0]; - assign fetchStage_read_waysValues_1_tag_error = _zz_29[0]; - assign fetchStage_read_waysValues_1_tag_address = _zz_15[21 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_hits_1 = (fetchStage_read_waysValues_1_tag_valid && (fetchStage_read_waysValues_1_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = ({fetchStage_hit_hits_1,fetchStage_hit_hits_0} != 2'b00); - assign fetchStage_hit_wayId = fetchStage_hit_hits_1; - assign fetchStage_hit_error = _zz_22; - assign fetchStage_hit_data = _zz_23; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[12 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[20 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 13])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000); + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; lineLoader_flushPending <= 1'b1; lineLoader_cmdSent <= 1'b0; - lineLoader_wayToAllocate_value <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_25)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - lineLoader_wayToAllocate_value <= lineLoader_wayToAllocate_valueNext; - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_24)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + if(when_InstructionCache_l338) begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 9'h001); end - _zz_5 <= lineLoader_flushCounter[7]; - if(_zz_25)begin - lineLoader_flushCounter <= 8'h0; + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[8]; + if(when_InstructionCache_l351) begin + lineLoader_flushCounter <= 9'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -7442,14 +7602,14 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end - if((_zz_16 != 3'b000))begin - io_cpu_fetch_data_regNextWhen <= _zz_17; + if(when_Fetcher_l398) begin + io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v index 4d3116e..af090b8 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v @@ -1,47 +1,47 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 - - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -82,37 +82,37 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_182; - wire _zz_183; - wire _zz_184; - wire _zz_185; - wire _zz_186; - wire _zz_187; - wire _zz_188; - wire _zz_189; - reg _zz_190; - wire _zz_191; - wire [31:0] _zz_192; - wire _zz_193; - wire [31:0] _zz_194; - reg _zz_195; - wire _zz_196; - wire _zz_197; - wire [31:0] _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - wire _zz_204; - wire _zz_205; - wire _zz_206; - wire [3:0] _zz_207; - wire _zz_208; - wire _zz_209; - reg [31:0] _zz_210; - reg [31:0] _zz_211; - reg [31:0] _zz_212; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -135,6 +135,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -143,335 +144,274 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - wire _zz_219; - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - wire _zz_228; - wire _zz_229; - wire [1:0] _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire [1:0] _zz_241; - wire _zz_242; - wire _zz_243; - wire [5:0] _zz_244; - wire _zz_245; - wire _zz_246; - wire _zz_247; - wire _zz_248; - wire _zz_249; - wire _zz_250; - wire [1:0] _zz_251; - wire _zz_252; - wire [1:0] _zz_253; - wire [51:0] _zz_254; - wire [51:0] _zz_255; - wire [51:0] _zz_256; - wire [32:0] _zz_257; - wire [51:0] _zz_258; - wire [49:0] _zz_259; - wire [51:0] _zz_260; - wire [49:0] _zz_261; - wire [51:0] _zz_262; - wire [32:0] _zz_263; - wire [31:0] _zz_264; - wire [32:0] _zz_265; - wire [0:0] _zz_266; - wire [0:0] _zz_267; - wire [0:0] _zz_268; - wire [0:0] _zz_269; - wire [0:0] _zz_270; - wire [0:0] _zz_271; - wire [0:0] _zz_272; - wire [0:0] _zz_273; - wire [0:0] _zz_274; - wire [0:0] _zz_275; - wire [0:0] _zz_276; - wire [0:0] _zz_277; - wire [0:0] _zz_278; - wire [0:0] _zz_279; - wire [0:0] _zz_280; - wire [0:0] _zz_281; - wire [0:0] _zz_282; - wire [0:0] _zz_283; - wire [3:0] _zz_284; - wire [2:0] _zz_285; - wire [31:0] _zz_286; - wire [11:0] _zz_287; - wire [31:0] _zz_288; - wire [19:0] _zz_289; - wire [11:0] _zz_290; - wire [31:0] _zz_291; - wire [31:0] _zz_292; - wire [19:0] _zz_293; - wire [11:0] _zz_294; - wire [2:0] _zz_295; - wire [2:0] _zz_296; - wire [0:0] _zz_297; - wire [2:0] _zz_298; - wire [4:0] _zz_299; - wire [11:0] _zz_300; - wire [11:0] _zz_301; - wire [31:0] _zz_302; - wire [31:0] _zz_303; - wire [31:0] _zz_304; - wire [31:0] _zz_305; - wire [31:0] _zz_306; - wire [31:0] _zz_307; - wire [31:0] _zz_308; - wire [11:0] _zz_309; - wire [19:0] _zz_310; - wire [11:0] _zz_311; - wire [31:0] _zz_312; - wire [31:0] _zz_313; - wire [31:0] _zz_314; - wire [11:0] _zz_315; - wire [19:0] _zz_316; - wire [11:0] _zz_317; - wire [2:0] _zz_318; - wire [1:0] _zz_319; - wire [1:0] _zz_320; - wire [65:0] _zz_321; - wire [65:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [0:0] _zz_325; - wire [5:0] _zz_326; - wire [32:0] _zz_327; - wire [31:0] _zz_328; - wire [31:0] _zz_329; - wire [32:0] _zz_330; - wire [32:0] _zz_331; - wire [32:0] _zz_332; - wire [32:0] _zz_333; - wire [0:0] _zz_334; - wire [32:0] _zz_335; - wire [0:0] _zz_336; - wire [32:0] _zz_337; - wire [0:0] _zz_338; - wire [31:0] _zz_339; - wire [0:0] _zz_340; - wire [0:0] _zz_341; - wire [0:0] _zz_342; - wire [0:0] _zz_343; - wire [0:0] _zz_344; - wire [0:0] _zz_345; - wire [0:0] _zz_346; - wire [26:0] _zz_347; - wire _zz_348; - wire _zz_349; - wire [1:0] _zz_350; - wire [31:0] _zz_351; - wire [31:0] _zz_352; - wire [31:0] _zz_353; - wire _zz_354; - wire [0:0] _zz_355; - wire [13:0] _zz_356; - wire [31:0] _zz_357; - wire [31:0] _zz_358; - wire [31:0] _zz_359; - wire _zz_360; - wire [0:0] _zz_361; - wire [7:0] _zz_362; - wire [31:0] _zz_363; - wire [31:0] _zz_364; - wire [31:0] _zz_365; - wire _zz_366; - wire [0:0] _zz_367; - wire [1:0] _zz_368; - wire _zz_369; - wire _zz_370; - wire _zz_371; - wire [31:0] _zz_372; - wire [0:0] _zz_373; - wire [0:0] _zz_374; - wire _zz_375; - wire [0:0] _zz_376; - wire [26:0] _zz_377; - wire [31:0] _zz_378; - wire _zz_379; - wire _zz_380; - wire _zz_381; - wire [1:0] _zz_382; - wire [1:0] _zz_383; - wire _zz_384; - wire [0:0] _zz_385; - wire [22:0] _zz_386; - wire [31:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire _zz_391; - wire _zz_392; - wire [1:0] _zz_393; - wire [1:0] _zz_394; - wire _zz_395; - wire [0:0] _zz_396; - wire [19:0] _zz_397; - wire [31:0] _zz_398; - wire [31:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire _zz_402; - wire [0:0] _zz_403; - wire [0:0] _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [0:0] _zz_407; - wire _zz_408; - wire [0:0] _zz_409; - wire [16:0] _zz_410; - wire [31:0] _zz_411; - wire [31:0] _zz_412; - wire [31:0] _zz_413; - wire [31:0] _zz_414; - wire [31:0] _zz_415; - wire [0:0] _zz_416; - wire [0:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire _zz_420; - wire [0:0] _zz_421; - wire [13:0] _zz_422; - wire [31:0] _zz_423; - wire [31:0] _zz_424; - wire [31:0] _zz_425; - wire _zz_426; - wire _zz_427; - wire [0:0] _zz_428; - wire [3:0] _zz_429; - wire [0:0] _zz_430; - wire [0:0] _zz_431; - wire _zz_432; - wire [0:0] _zz_433; - wire [10:0] _zz_434; - wire [31:0] _zz_435; - wire [31:0] _zz_436; - wire [31:0] _zz_437; - wire _zz_438; - wire [0:0] _zz_439; - wire [0:0] _zz_440; - wire [31:0] _zz_441; - wire _zz_442; - wire [0:0] _zz_443; - wire [2:0] _zz_444; - wire [0:0] _zz_445; - wire [3:0] _zz_446; - wire [5:0] _zz_447; - wire [5:0] _zz_448; - wire _zz_449; - wire [0:0] _zz_450; - wire [7:0] _zz_451; - wire [31:0] _zz_452; - wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [31:0] _zz_456; - wire [31:0] _zz_457; - wire _zz_458; - wire [0:0] _zz_459; - wire [0:0] _zz_460; - wire _zz_461; - wire [0:0] _zz_462; - wire [1:0] _zz_463; - wire [0:0] _zz_464; - wire [3:0] _zz_465; - wire [0:0] _zz_466; - wire [0:0] _zz_467; - wire [1:0] _zz_468; - wire [1:0] _zz_469; - wire _zz_470; - wire [0:0] _zz_471; - wire [5:0] _zz_472; - wire [31:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; - wire [31:0] _zz_477; - wire [31:0] _zz_478; - wire [31:0] _zz_479; - wire [31:0] _zz_480; - wire _zz_481; - wire _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire _zz_485; - wire [0:0] _zz_486; - wire [1:0] _zz_487; - wire [31:0] _zz_488; - wire [31:0] _zz_489; - wire _zz_490; - wire _zz_491; - wire [0:0] _zz_492; - wire [0:0] _zz_493; - wire _zz_494; - wire [0:0] _zz_495; - wire [3:0] _zz_496; - wire [31:0] _zz_497; - wire [31:0] _zz_498; - wire [31:0] _zz_499; - wire [31:0] _zz_500; - wire [31:0] _zz_501; - wire _zz_502; - wire _zz_503; - wire [31:0] _zz_504; - wire [31:0] _zz_505; - wire [31:0] _zz_506; - wire [31:0] _zz_507; - wire [0:0] _zz_508; - wire [2:0] _zz_509; - wire [0:0] _zz_510; - wire [0:0] _zz_511; - wire _zz_512; - wire [0:0] _zz_513; - wire [1:0] _zz_514; - wire [31:0] _zz_515; - wire [31:0] _zz_516; - wire [31:0] _zz_517; - wire _zz_518; - wire _zz_519; - wire [31:0] _zz_520; - wire _zz_521; - wire [0:0] _zz_522; - wire [0:0] _zz_523; - wire [0:0] _zz_524; - wire [0:0] _zz_525; - wire [1:0] _zz_526; - wire [1:0] _zz_527; - wire [0:0] _zz_528; - wire [0:0] _zz_529; - wire [31:0] _zz_530; - wire [31:0] _zz_531; - wire [31:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire [31:0] _zz_535; - wire _zz_536; - wire _zz_537; - wire _zz_538; - wire [31:0] _zz_539; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_1; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_2; + wire _zz__zz_decode_IS_RS2_SIGNED_3; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_4; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_5; + wire _zz__zz_decode_IS_RS2_SIGNED_6; + wire _zz__zz_decode_IS_RS2_SIGNED_7; + wire [26:0] _zz__zz_decode_IS_RS2_SIGNED_8; + wire _zz__zz_decode_IS_RS2_SIGNED_9; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_10; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_11; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_12; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_13; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_14; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_15; + wire _zz__zz_decode_IS_RS2_SIGNED_16; + wire _zz__zz_decode_IS_RS2_SIGNED_17; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_18; + wire _zz__zz_decode_IS_RS2_SIGNED_19; + wire [22:0] _zz__zz_decode_IS_RS2_SIGNED_20; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_21; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_22; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_23; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_24; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_25; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_26; + wire _zz__zz_decode_IS_RS2_SIGNED_27; + wire _zz__zz_decode_IS_RS2_SIGNED_28; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_29; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_30; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_31; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_32; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_33; + wire _zz__zz_decode_IS_RS2_SIGNED_34; + wire [19:0] _zz__zz_decode_IS_RS2_SIGNED_35; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_36; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_37; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_38; + wire _zz__zz_decode_IS_RS2_SIGNED_39; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_40; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_41; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_42; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_43; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_44; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_45; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_46; + wire [16:0] _zz__zz_decode_IS_RS2_SIGNED_47; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_48; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_49; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_50; + wire _zz__zz_decode_IS_RS2_SIGNED_51; + wire _zz__zz_decode_IS_RS2_SIGNED_52; + wire _zz__zz_decode_IS_RS2_SIGNED_53; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_54; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_55; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_56; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_57; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_58; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_59; + wire _zz__zz_decode_IS_RS2_SIGNED_60; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_61; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_62; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_63; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_64; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_65; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_66; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_67; + wire [13:0] _zz__zz_decode_IS_RS2_SIGNED_68; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_69; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_70; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_71; + wire _zz__zz_decode_IS_RS2_SIGNED_72; + wire _zz__zz_decode_IS_RS2_SIGNED_73; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_74; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_75; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_76; + wire _zz__zz_decode_IS_RS2_SIGNED_77; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_78; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_79; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_80; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_81; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_82; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_83; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_84; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_85; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_86; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_87; + wire _zz__zz_decode_IS_RS2_SIGNED_88; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_89; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_90; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_91; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_92; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_93; + wire _zz__zz_decode_IS_RS2_SIGNED_94; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_95; + wire _zz__zz_decode_IS_RS2_SIGNED_96; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_97; + wire [10:0] _zz__zz_decode_IS_RS2_SIGNED_98; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_99; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_100; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_101; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_102; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_103; + wire _zz__zz_decode_IS_RS2_SIGNED_104; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_105; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_106; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_107; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_108; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_109; + wire _zz__zz_decode_IS_RS2_SIGNED_110; + wire _zz__zz_decode_IS_RS2_SIGNED_111; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_112; + wire _zz__zz_decode_IS_RS2_SIGNED_113; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_114; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_115; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_116; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_117; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_118; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_119; + wire _zz__zz_decode_IS_RS2_SIGNED_120; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_121; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_122; + wire [7:0] _zz__zz_decode_IS_RS2_SIGNED_123; + wire _zz__zz_decode_IS_RS2_SIGNED_124; + wire _zz__zz_decode_IS_RS2_SIGNED_125; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_126; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_127; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_128; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_129; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_130; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_131; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_132; + wire _zz__zz_decode_IS_RS2_SIGNED_133; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_134; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_135; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_136; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_137; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_138; + wire _zz__zz_decode_IS_RS2_SIGNED_139; + wire _zz__zz_decode_IS_RS2_SIGNED_140; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_141; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_142; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_143; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_144; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_145; + wire _zz__zz_decode_IS_RS2_SIGNED_146; + wire _zz__zz_decode_IS_RS2_SIGNED_147; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_148; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_149; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_150; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_151; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_152; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_153; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_154; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_155; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_156; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_157; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_158; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_159; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_160; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_161; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_162; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_163; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -482,8 +422,8 @@ module VexRiscv ( wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_DO_EBREAK; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; @@ -495,27 +435,27 @@ module VexRiscv ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -523,18 +463,18 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; @@ -556,23 +496,23 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_31; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -582,45 +522,45 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_32; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_35; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_36; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; - wire [31:0] _zz_40; - wire _zz_41; - reg _zz_42; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_43; - wire `BranchCtrlEnum_defaultEncoding_type _zz_44; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; - wire `Src2CtrlEnum_defaultEncoding_type _zz_47; - wire `AluCtrlEnum_defaultEncoding_type _zz_48; - wire `Src1CtrlEnum_defaultEncoding_type _zz_49; - reg [31:0] _zz_50; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -638,11 +578,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_52; - reg [31:0] _zz_53; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -729,7 +669,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -755,7 +695,7 @@ module VexRiscv ( reg DBusCachedPlugin_exceptionBus_valid; reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_54; + reg _zz_when_DBusCachedPlugin_l386; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -764,6 +704,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -781,31 +726,37 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; reg CsrPlugin_allowInterrupts; reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; reg IBusCachedPlugin_injectionPort_valid; reg IBusCachedPlugin_injectionPort_ready; wire [31:0] IBusCachedPlugin_injectionPort_payload; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_55; - wire [3:0] _zz_56; - wire _zz_57; - wire _zz_58; - wire _zz_59; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -828,16 +779,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_60; - wire _zz_61; - wire _zz_62; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_63; - wire _zz_64; - reg _zz_65; - wire _zz_66; - reg _zz_67; - reg [31:0] _zz_68; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -845,22 +798,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_69; - reg [18:0] _zz_70; - wire _zz_71; - reg [10:0] _zz_72; - wire _zz_73; - reg [18:0] _zz_74; - reg _zz_75; - wire _zz_76; - reg [10:0] _zz_77; - wire _zz_78; - reg [18:0] _zz_79; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -868,7 +828,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_80; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -876,23 +836,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -900,38 +865,54 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_81; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_82; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_83; - reg [31:0] _zz_84; - wire _zz_85; - reg [31:0] _zz_86; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [32:0] _zz_87; - wire _zz_88; - wire _zz_89; - wire _zz_90; - wire _zz_91; - wire `Src1CtrlEnum_defaultEncoding_type _zz_92; - wire `AluCtrlEnum_defaultEncoding_type _zz_93; - wire `Src2CtrlEnum_defaultEncoding_type _zz_94; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_95; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_96; - wire `BranchCtrlEnum_defaultEncoding_type _zz_97; - wire `EnvCtrlEnum_defaultEncoding_type _zz_98; + wire when_DBusCachedPlugin_l484; + wire [32:0] _zz_decode_IS_RS2_SIGNED; + wire _zz_decode_IS_RS2_SIGNED_1; + wire _zz_decode_IS_RS2_SIGNED_2; + wire _zz_decode_IS_RS2_SIGNED_3; + wire _zz_decode_IS_RS2_SIGNED_4; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -939,52 +920,70 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_99; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_100; - reg [31:0] _zz_101; - wire _zz_102; - reg [19:0] _zz_103; - wire _zz_104; - reg [19:0] _zz_105; - reg [31:0] _zz_106; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_107; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_108; - reg _zz_109; - reg _zz_110; - reg _zz_111; - reg [4:0] _zz_112; - reg [31:0] _zz_113; - wire _zz_114; - wire _zz_115; - wire _zz_116; - wire _zz_117; - wire _zz_118; - wire _zz_119; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_120; - reg _zz_121; - reg _zz_122; - wire _zz_123; - reg [19:0] _zz_124; - wire _zz_125; - reg [10:0] _zz_126; - wire _zz_127; - reg [18:0] _zz_128; - reg _zz_129; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_130; - reg [19:0] _zz_131; - wire _zz_132; - reg [10:0] _zz_133; - wire _zz_134; - reg [18:0] _zz_135; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1006,9 +1005,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_136; - wire _zz_137; - wire _zz_138; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1021,40 +1020,67 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_139; - wire _zz_140; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1062,6 +1088,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1074,19 +1102,26 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_141; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_142; - wire _zz_143; - wire _zz_144; - reg [32:0] _zz_145; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_146; - wire [31:0] _zz_147; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1094,202 +1129,316 @@ module VexRiscv ( reg DebugPlugin_stepIt; reg DebugPlugin_isPipBusy; reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_148; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_44; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_45; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_46; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_47; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_48; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_49; reg decode_to_execute_DO_EBREAK; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_50; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_51; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_52; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_53; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_54; reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_55; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_57; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_60; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_61; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_62; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_149; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l378; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_150; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [2:0] _zz_173; - reg _zz_174; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_175; - wire _zz_176; - wire _zz_177; - wire _zz_178; - wire _zz_179; - wire _zz_180; - reg _zz_181; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; - reg [39:0] _zz_17_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; - reg [23:0] _zz_20_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; - reg [63:0] _zz_23_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; - reg [95:0] _zz_26_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_30_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_33_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_34_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_36_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_37_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_38_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_39_string; - reg [39:0] _zz_43_string; - reg [31:0] _zz_44_string; - reg [71:0] _zz_45_string; - reg [39:0] _zz_46_string; - reg [23:0] _zz_47_string; - reg [63:0] _zz_48_string; - reg [95:0] _zz_49_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_51_string; - reg [95:0] _zz_92_string; - reg [63:0] _zz_93_string; - reg [23:0] _zz_94_string; - reg [39:0] _zz_95_string; - reg [71:0] _zz_96_string; - reg [31:0] _zz_97_string; - reg [39:0] _zz_98_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1304,1161 +1453,1124 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_213 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_214 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_215 = 1'b1; - assign _zz_216 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_217 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_218 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_219 = ((_zz_187 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_220 = ((_zz_187 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_221 = ((_zz_187 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_222 = ((_zz_187 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_223 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_224 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_225 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_226 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_227 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_228 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_229 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_230 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_232 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_233 = (1'b0 || (! 1'b1)); - assign _zz_234 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_235 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_236 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_237 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_238 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_239 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_240 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_241 = execute_INSTRUCTION[13 : 12]; - assign _zz_242 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_243 = (! memory_arbitration_isStuck); - assign _zz_244 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_245 = (iBus_cmd_valid || (_zz_173 != 3'b000)); - assign _zz_246 = (_zz_209 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_247 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_248 = ((_zz_136 && 1'b1) && (! 1'b0)); - assign _zz_249 = ((_zz_137 && 1'b1) && (! 1'b0)); - assign _zz_250 = ((_zz_138 && 1'b1) && (! 1'b0)); - assign _zz_251 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_252 = execute_INSTRUCTION[13]; - assign _zz_253 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_254 = ($signed(_zz_255) + $signed(_zz_260)); - assign _zz_255 = ($signed(_zz_256) + $signed(_zz_258)); - assign _zz_256 = 52'h0; - assign _zz_257 = {1'b0,memory_MUL_LL}; - assign _zz_258 = {{19{_zz_257[32]}}, _zz_257}; - assign _zz_259 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_260 = {{2{_zz_259[49]}}, _zz_259}; - assign _zz_261 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_262 = {{2{_zz_261[49]}}, _zz_261}; - assign _zz_263 = ($signed(_zz_265) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_264 = _zz_263[31 : 0]; - assign _zz_265 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_266 = _zz_87[31 : 31]; - assign _zz_267 = _zz_87[30 : 30]; - assign _zz_268 = _zz_87[29 : 29]; - assign _zz_269 = _zz_87[28 : 28]; - assign _zz_270 = _zz_87[25 : 25]; - assign _zz_271 = _zz_87[17 : 17]; - assign _zz_272 = _zz_87[16 : 16]; - assign _zz_273 = _zz_87[13 : 13]; - assign _zz_274 = _zz_87[12 : 12]; - assign _zz_275 = _zz_87[11 : 11]; - assign _zz_276 = _zz_87[32 : 32]; - assign _zz_277 = _zz_87[15 : 15]; - assign _zz_278 = _zz_87[5 : 5]; - assign _zz_279 = _zz_87[3 : 3]; - assign _zz_280 = _zz_87[20 : 20]; - assign _zz_281 = _zz_87[10 : 10]; - assign _zz_282 = _zz_87[4 : 4]; - assign _zz_283 = _zz_87[0 : 0]; - assign _zz_284 = (_zz_55 - 4'b0001); - assign _zz_285 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_286 = {29'd0, _zz_285}; - assign _zz_287 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_288 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_289 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_290 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_291 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_292 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_293 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_294 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_295 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_296 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_297 = execute_SRC_LESS; - assign _zz_298 = 3'b100; - assign _zz_299 = execute_INSTRUCTION[19 : 15]; - assign _zz_300 = execute_INSTRUCTION[31 : 20]; - assign _zz_301 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_302 = ($signed(_zz_303) + $signed(_zz_306)); - assign _zz_303 = ($signed(_zz_304) + $signed(_zz_305)); - assign _zz_304 = execute_SRC1; - assign _zz_305 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_306 = (execute_SRC_USE_SUB_LESS ? _zz_307 : _zz_308); - assign _zz_307 = 32'h00000001; - assign _zz_308 = 32'h0; - assign _zz_309 = execute_INSTRUCTION[31 : 20]; - assign _zz_310 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_311 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_312 = {_zz_124,execute_INSTRUCTION[31 : 20]}; - assign _zz_313 = {{_zz_126,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_314 = {{_zz_128,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_315 = execute_INSTRUCTION[31 : 20]; - assign _zz_316 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_317 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_318 = 3'b100; - assign _zz_319 = (_zz_139 & (~ _zz_320)); - assign _zz_320 = (_zz_139 - 2'b01); - assign _zz_321 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_322 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_323 = writeBack_MUL_LOW[31 : 0]; - assign _zz_324 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_325 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_326 = {5'd0, _zz_325}; - assign _zz_327 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_328 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_329 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_330 = {_zz_141,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_331 = _zz_332; - assign _zz_332 = _zz_333; - assign _zz_333 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_142) : _zz_142)} + _zz_335); - assign _zz_334 = memory_DivPlugin_div_needRevert; - assign _zz_335 = {32'd0, _zz_334}; - assign _zz_336 = _zz_144; - assign _zz_337 = {32'd0, _zz_336}; - assign _zz_338 = _zz_143; - assign _zz_339 = {31'd0, _zz_338}; - assign _zz_340 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_341 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_342 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_343 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_344 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_345 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_346 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_347 = (iBus_cmd_payload_address >>> 5); - assign _zz_348 = 1'b1; - assign _zz_349 = 1'b1; - assign _zz_350 = {_zz_59,_zz_58}; - assign _zz_351 = 32'h0000107f; - assign _zz_352 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_353 = 32'h00002073; - assign _zz_354 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_355 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_356 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_357) == 32'h00000003),{(_zz_358 == _zz_359),{_zz_360,{_zz_361,_zz_362}}}}}}; - assign _zz_357 = 32'h0000505f; - assign _zz_358 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_359 = 32'h00000063; - assign _zz_360 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_361 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_362 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_363) == 32'h00001013),{(_zz_364 == _zz_365),{_zz_366,{_zz_367,_zz_368}}}}}}; - assign _zz_363 = 32'hfc00307f; - assign _zz_364 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_365 = 32'h00005033; - assign _zz_366 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_367 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_368 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz_369 = decode_INSTRUCTION[31]; - assign _zz_370 = decode_INSTRUCTION[31]; - assign _zz_371 = decode_INSTRUCTION[7]; - assign _zz_372 = 32'h10103050; - assign _zz_373 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_374 = 1'b0; - assign _zz_375 = (((decode_INSTRUCTION & _zz_378) == 32'h02000030) != 1'b0); - assign _zz_376 = ({_zz_379,_zz_380} != 2'b00); - assign _zz_377 = {(_zz_381 != 1'b0),{(_zz_382 != _zz_383),{_zz_384,{_zz_385,_zz_386}}}}; - assign _zz_378 = 32'h02004074; - assign _zz_379 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); - assign _zz_380 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); - assign _zz_381 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); - assign _zz_382 = {(_zz_387 == _zz_388),(_zz_389 == _zz_390)}; - assign _zz_383 = 2'b00; - assign _zz_384 = ({_zz_90,_zz_391} != 2'b00); - assign _zz_385 = (_zz_392 != 1'b0); - assign _zz_386 = {(_zz_393 != _zz_394),{_zz_395,{_zz_396,_zz_397}}}; - assign _zz_387 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_388 = 32'h00001050; - assign _zz_389 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_390 = 32'h00002050; - assign _zz_391 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_392 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_393 = {(_zz_398 == _zz_399),(_zz_400 == _zz_401)}; - assign _zz_394 = 2'b00; - assign _zz_395 = ({_zz_402,{_zz_403,_zz_404}} != 3'b000); - assign _zz_396 = (_zz_405 != 1'b0); - assign _zz_397 = {(_zz_406 != _zz_407),{_zz_408,{_zz_409,_zz_410}}}; - assign _zz_398 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_399 = 32'h00005010; - assign _zz_400 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_401 = 32'h00005020; - assign _zz_402 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_403 = ((decode_INSTRUCTION & _zz_411) == 32'h00001010); - assign _zz_404 = ((decode_INSTRUCTION & _zz_412) == 32'h00001010); - assign _zz_405 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_406 = ((decode_INSTRUCTION & _zz_413) == 32'h00001000); - assign _zz_407 = 1'b0; - assign _zz_408 = ((_zz_414 == _zz_415) != 1'b0); - assign _zz_409 = ({_zz_416,_zz_417} != 2'b00); - assign _zz_410 = {(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}; - assign _zz_411 = 32'h00007034; - assign _zz_412 = 32'h02007054; - assign _zz_413 = 32'h00001000; - assign _zz_414 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_415 = 32'h00002000; - assign _zz_416 = ((decode_INSTRUCTION & _zz_423) == 32'h00002000); - assign _zz_417 = ((decode_INSTRUCTION & _zz_424) == 32'h00001000); - assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00004008); - assign _zz_419 = 1'b0; - assign _zz_420 = ({_zz_426,_zz_427} != 2'b00); - assign _zz_421 = ({_zz_428,_zz_429} != 5'h0); - assign _zz_422 = {(_zz_430 != _zz_431),{_zz_432,{_zz_433,_zz_434}}}; - assign _zz_423 = 32'h00002010; - assign _zz_424 = 32'h00005000; - assign _zz_425 = 32'h00004048; - assign _zz_426 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); - assign _zz_427 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_428 = ((decode_INSTRUCTION & _zz_435) == 32'h00002040); - assign _zz_429 = {(_zz_436 == _zz_437),{_zz_438,{_zz_439,_zz_440}}}; - assign _zz_430 = ((decode_INSTRUCTION & _zz_441) == 32'h00000020); - assign _zz_431 = 1'b0; - assign _zz_432 = ({_zz_442,{_zz_443,_zz_444}} != 5'h0); - assign _zz_433 = ({_zz_445,_zz_446} != 5'h0); - assign _zz_434 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; - assign _zz_435 = 32'h00002040; - assign _zz_436 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_437 = 32'h00001040; - assign _zz_438 = ((decode_INSTRUCTION & _zz_452) == 32'h00000040); - assign _zz_439 = (_zz_453 == _zz_454); - assign _zz_440 = (_zz_455 == _zz_456); - assign _zz_441 = 32'h00000020; - assign _zz_442 = ((decode_INSTRUCTION & _zz_457) == 32'h00000040); - assign _zz_443 = _zz_89; - assign _zz_444 = {_zz_458,{_zz_459,_zz_460}}; - assign _zz_445 = _zz_89; - assign _zz_446 = {_zz_461,{_zz_462,_zz_463}}; - assign _zz_447 = {_zz_90,{_zz_464,_zz_465}}; - assign _zz_448 = 6'h0; - assign _zz_449 = ({_zz_466,_zz_467} != 2'b00); - assign _zz_450 = (_zz_468 != _zz_469); - assign _zz_451 = {_zz_470,{_zz_471,_zz_472}}; - assign _zz_452 = 32'h00100040; - assign _zz_453 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_454 = 32'h00000040; - assign _zz_455 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_456 = 32'h0; - assign _zz_457 = 32'h00000040; - assign _zz_458 = ((decode_INSTRUCTION & _zz_473) == 32'h00004020); - assign _zz_459 = (_zz_474 == _zz_475); - assign _zz_460 = (_zz_476 == _zz_477); - assign _zz_461 = ((decode_INSTRUCTION & _zz_478) == 32'h00002010); - assign _zz_462 = (_zz_479 == _zz_480); - assign _zz_463 = {_zz_481,_zz_482}; - assign _zz_464 = (_zz_483 == _zz_484); - assign _zz_465 = {_zz_485,{_zz_486,_zz_487}}; - assign _zz_466 = _zz_89; - assign _zz_467 = (_zz_488 == _zz_489); - assign _zz_468 = {_zz_89,_zz_490}; - assign _zz_469 = 2'b00; - assign _zz_470 = (_zz_491 != 1'b0); - assign _zz_471 = (_zz_492 != _zz_493); - assign _zz_472 = {_zz_494,{_zz_495,_zz_496}}; - assign _zz_473 = 32'h00004020; - assign _zz_474 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_475 = 32'h00000010; - assign _zz_476 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_477 = 32'h00000020; - assign _zz_478 = 32'h00002030; - assign _zz_479 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_480 = 32'h00000010; - assign _zz_481 = ((decode_INSTRUCTION & _zz_497) == 32'h00002020); - assign _zz_482 = ((decode_INSTRUCTION & _zz_498) == 32'h00000020); - assign _zz_483 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_484 = 32'h00001010; - assign _zz_485 = ((decode_INSTRUCTION & _zz_499) == 32'h00002010); - assign _zz_486 = (_zz_500 == _zz_501); - assign _zz_487 = {_zz_502,_zz_503}; - assign _zz_488 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_489 = 32'h00000020; - assign _zz_490 = ((decode_INSTRUCTION & _zz_504) == 32'h0); - assign _zz_491 = ((decode_INSTRUCTION & _zz_505) == 32'h00004010); - assign _zz_492 = (_zz_506 == _zz_507); - assign _zz_493 = 1'b0; - assign _zz_494 = ({_zz_508,_zz_509} != 4'b0000); - assign _zz_495 = (_zz_510 != _zz_511); - assign _zz_496 = {_zz_512,{_zz_513,_zz_514}}; - assign _zz_497 = 32'h02002060; - assign _zz_498 = 32'h02003020; - assign _zz_499 = 32'h00002010; - assign _zz_500 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_501 = 32'h00000010; - assign _zz_502 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_503 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); - assign _zz_504 = 32'h00000020; - assign _zz_505 = 32'h00004014; - assign _zz_506 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_507 = 32'h00002010; - assign _zz_508 = ((decode_INSTRUCTION & _zz_515) == 32'h0); - assign _zz_509 = {(_zz_516 == _zz_517),{_zz_518,_zz_519}}; - assign _zz_510 = ((decode_INSTRUCTION & _zz_520) == 32'h0); - assign _zz_511 = 1'b0; - assign _zz_512 = ({_zz_521,{_zz_522,_zz_523}} != 3'b000); - assign _zz_513 = ({_zz_524,_zz_525} != 2'b00); - assign _zz_514 = {(_zz_526 != _zz_527),(_zz_528 != _zz_529)}; - assign _zz_515 = 32'h00000044; - assign _zz_516 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_517 = 32'h0; - assign _zz_518 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_519 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_520 = 32'h00000058; - assign _zz_521 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_522 = ((decode_INSTRUCTION & _zz_530) == 32'h00002010); - assign _zz_523 = ((decode_INSTRUCTION & _zz_531) == 32'h40000030); - assign _zz_524 = ((decode_INSTRUCTION & _zz_532) == 32'h00000004); - assign _zz_525 = _zz_88; - assign _zz_526 = {(_zz_533 == _zz_534),_zz_88}; - assign _zz_527 = 2'b00; - assign _zz_528 = ((decode_INSTRUCTION & _zz_535) == 32'h00001008); - assign _zz_529 = 1'b0; - assign _zz_530 = 32'h00002014; - assign _zz_531 = 32'h40000034; - assign _zz_532 = 32'h00000014; - assign _zz_533 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_534 = 32'h00000004; - assign _zz_535 = 32'h00005048; - assign _zz_536 = execute_INSTRUCTION[31]; - assign _zz_537 = execute_INSTRUCTION[31]; - assign _zz_538 = execute_INSTRUCTION[7]; - assign _zz_539 = 32'h0; - always @ (posedge clk) begin - if(_zz_348) begin - _zz_210 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_349) begin - _zz_211 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_42) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_IS_RS2_SIGNED = 32'h10103050; + assign _zz__zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz__zz_decode_IS_RS2_SIGNED_2 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_3 = (((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_4) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_5 = ({_zz__zz_decode_IS_RS2_SIGNED_6,_zz__zz_decode_IS_RS2_SIGNED_7} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_8 = {(_zz__zz_decode_IS_RS2_SIGNED_9 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_10 != _zz__zz_decode_IS_RS2_SIGNED_15),{_zz__zz_decode_IS_RS2_SIGNED_16,{_zz__zz_decode_IS_RS2_SIGNED_18,_zz__zz_decode_IS_RS2_SIGNED_20}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_4 = 32'h02004074; + assign _zz__zz_decode_IS_RS2_SIGNED_6 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); + assign _zz__zz_decode_IS_RS2_SIGNED_7 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_9 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_10 = {(_zz__zz_decode_IS_RS2_SIGNED_11 == _zz__zz_decode_IS_RS2_SIGNED_12),(_zz__zz_decode_IS_RS2_SIGNED_13 == _zz__zz_decode_IS_RS2_SIGNED_14)}; + assign _zz__zz_decode_IS_RS2_SIGNED_15 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_16 = ({_zz_decode_IS_RS2_SIGNED_3,_zz__zz_decode_IS_RS2_SIGNED_17} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_18 = (_zz__zz_decode_IS_RS2_SIGNED_19 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_20 = {(_zz__zz_decode_IS_RS2_SIGNED_21 != _zz__zz_decode_IS_RS2_SIGNED_26),{_zz__zz_decode_IS_RS2_SIGNED_27,{_zz__zz_decode_IS_RS2_SIGNED_33,_zz__zz_decode_IS_RS2_SIGNED_35}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_11 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_IS_RS2_SIGNED_12 = 32'h00001050; + assign _zz__zz_decode_IS_RS2_SIGNED_13 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_IS_RS2_SIGNED_14 = 32'h00002050; + assign _zz__zz_decode_IS_RS2_SIGNED_17 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_19 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_21 = {(_zz__zz_decode_IS_RS2_SIGNED_22 == _zz__zz_decode_IS_RS2_SIGNED_23),(_zz__zz_decode_IS_RS2_SIGNED_24 == _zz__zz_decode_IS_RS2_SIGNED_25)}; + assign _zz__zz_decode_IS_RS2_SIGNED_26 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_27 = ({_zz__zz_decode_IS_RS2_SIGNED_28,{_zz__zz_decode_IS_RS2_SIGNED_29,_zz__zz_decode_IS_RS2_SIGNED_31}} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_33 = (_zz__zz_decode_IS_RS2_SIGNED_34 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_35 = {(_zz__zz_decode_IS_RS2_SIGNED_36 != _zz__zz_decode_IS_RS2_SIGNED_38),{_zz__zz_decode_IS_RS2_SIGNED_39,{_zz__zz_decode_IS_RS2_SIGNED_42,_zz__zz_decode_IS_RS2_SIGNED_47}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_22 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_RS2_SIGNED_23 = 32'h00005010; + assign _zz__zz_decode_IS_RS2_SIGNED_24 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_IS_RS2_SIGNED_25 = 32'h00005020; + assign _zz__zz_decode_IS_RS2_SIGNED_28 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_IS_RS2_SIGNED_29 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_30) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_31 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_32) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_34 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_IS_RS2_SIGNED_36 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_37) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_38 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_39 = ((_zz__zz_decode_IS_RS2_SIGNED_40 == _zz__zz_decode_IS_RS2_SIGNED_41) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_42 = ({_zz__zz_decode_IS_RS2_SIGNED_43,_zz__zz_decode_IS_RS2_SIGNED_45} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_47 = {(_zz__zz_decode_IS_RS2_SIGNED_48 != _zz__zz_decode_IS_RS2_SIGNED_50),{_zz__zz_decode_IS_RS2_SIGNED_51,{_zz__zz_decode_IS_RS2_SIGNED_54,_zz__zz_decode_IS_RS2_SIGNED_68}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_30 = 32'h00007034; + assign _zz__zz_decode_IS_RS2_SIGNED_32 = 32'h02007054; + assign _zz__zz_decode_IS_RS2_SIGNED_37 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_40 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_IS_RS2_SIGNED_41 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_43 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_44) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_45 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_46) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_48 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_49) == 32'h00004008); + assign _zz__zz_decode_IS_RS2_SIGNED_50 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_51 = ({_zz__zz_decode_IS_RS2_SIGNED_52,_zz__zz_decode_IS_RS2_SIGNED_53} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_54 = ({_zz__zz_decode_IS_RS2_SIGNED_55,_zz__zz_decode_IS_RS2_SIGNED_57} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_68 = {(_zz__zz_decode_IS_RS2_SIGNED_69 != _zz__zz_decode_IS_RS2_SIGNED_71),{_zz__zz_decode_IS_RS2_SIGNED_72,{_zz__zz_decode_IS_RS2_SIGNED_85,_zz__zz_decode_IS_RS2_SIGNED_98}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_44 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_46 = 32'h00005000; + assign _zz__zz_decode_IS_RS2_SIGNED_49 = 32'h00004048; + assign _zz__zz_decode_IS_RS2_SIGNED_52 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_53 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_55 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_56) == 32'h00002040); + assign _zz__zz_decode_IS_RS2_SIGNED_57 = {(_zz__zz_decode_IS_RS2_SIGNED_58 == _zz__zz_decode_IS_RS2_SIGNED_59),{_zz__zz_decode_IS_RS2_SIGNED_60,{_zz__zz_decode_IS_RS2_SIGNED_62,_zz__zz_decode_IS_RS2_SIGNED_65}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_69 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_70) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_71 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_72 = ({_zz__zz_decode_IS_RS2_SIGNED_73,{_zz__zz_decode_IS_RS2_SIGNED_75,_zz__zz_decode_IS_RS2_SIGNED_76}} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_85 = ({_zz__zz_decode_IS_RS2_SIGNED_86,_zz__zz_decode_IS_RS2_SIGNED_87} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_98 = {(_zz__zz_decode_IS_RS2_SIGNED_99 != _zz__zz_decode_IS_RS2_SIGNED_112),{_zz__zz_decode_IS_RS2_SIGNED_113,{_zz__zz_decode_IS_RS2_SIGNED_118,_zz__zz_decode_IS_RS2_SIGNED_123}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_56 = 32'h00002040; + assign _zz__zz_decode_IS_RS2_SIGNED_58 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_IS_RS2_SIGNED_59 = 32'h00001040; + assign _zz__zz_decode_IS_RS2_SIGNED_60 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_61) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_62 = (_zz__zz_decode_IS_RS2_SIGNED_63 == _zz__zz_decode_IS_RS2_SIGNED_64); + assign _zz__zz_decode_IS_RS2_SIGNED_65 = (_zz__zz_decode_IS_RS2_SIGNED_66 == _zz__zz_decode_IS_RS2_SIGNED_67); + assign _zz__zz_decode_IS_RS2_SIGNED_70 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_73 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_74) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_75 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_76 = {_zz__zz_decode_IS_RS2_SIGNED_77,{_zz__zz_decode_IS_RS2_SIGNED_79,_zz__zz_decode_IS_RS2_SIGNED_82}}; + assign _zz__zz_decode_IS_RS2_SIGNED_86 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_87 = {_zz__zz_decode_IS_RS2_SIGNED_88,{_zz__zz_decode_IS_RS2_SIGNED_90,_zz__zz_decode_IS_RS2_SIGNED_93}}; + assign _zz__zz_decode_IS_RS2_SIGNED_99 = {_zz_decode_IS_RS2_SIGNED_3,{_zz__zz_decode_IS_RS2_SIGNED_100,_zz__zz_decode_IS_RS2_SIGNED_103}}; + assign _zz__zz_decode_IS_RS2_SIGNED_112 = 6'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_113 = ({_zz__zz_decode_IS_RS2_SIGNED_114,_zz__zz_decode_IS_RS2_SIGNED_115} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_118 = (_zz__zz_decode_IS_RS2_SIGNED_119 != _zz__zz_decode_IS_RS2_SIGNED_122); + assign _zz__zz_decode_IS_RS2_SIGNED_123 = {_zz__zz_decode_IS_RS2_SIGNED_124,{_zz__zz_decode_IS_RS2_SIGNED_127,_zz__zz_decode_IS_RS2_SIGNED_132}}; + assign _zz__zz_decode_IS_RS2_SIGNED_61 = 32'h00100040; + assign _zz__zz_decode_IS_RS2_SIGNED_63 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_64 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_66 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_IS_RS2_SIGNED_67 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_74 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_77 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_78) == 32'h00004020); + assign _zz__zz_decode_IS_RS2_SIGNED_79 = (_zz__zz_decode_IS_RS2_SIGNED_80 == _zz__zz_decode_IS_RS2_SIGNED_81); + assign _zz__zz_decode_IS_RS2_SIGNED_82 = (_zz__zz_decode_IS_RS2_SIGNED_83 == _zz__zz_decode_IS_RS2_SIGNED_84); + assign _zz__zz_decode_IS_RS2_SIGNED_88 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_89) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_90 = (_zz__zz_decode_IS_RS2_SIGNED_91 == _zz__zz_decode_IS_RS2_SIGNED_92); + assign _zz__zz_decode_IS_RS2_SIGNED_93 = {_zz__zz_decode_IS_RS2_SIGNED_94,_zz__zz_decode_IS_RS2_SIGNED_96}; + assign _zz__zz_decode_IS_RS2_SIGNED_100 = (_zz__zz_decode_IS_RS2_SIGNED_101 == _zz__zz_decode_IS_RS2_SIGNED_102); + assign _zz__zz_decode_IS_RS2_SIGNED_103 = {_zz__zz_decode_IS_RS2_SIGNED_104,{_zz__zz_decode_IS_RS2_SIGNED_106,_zz__zz_decode_IS_RS2_SIGNED_109}}; + assign _zz__zz_decode_IS_RS2_SIGNED_114 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_115 = (_zz__zz_decode_IS_RS2_SIGNED_116 == _zz__zz_decode_IS_RS2_SIGNED_117); + assign _zz__zz_decode_IS_RS2_SIGNED_119 = {_zz_decode_IS_RS2_SIGNED_2,_zz__zz_decode_IS_RS2_SIGNED_120}; + assign _zz__zz_decode_IS_RS2_SIGNED_122 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_124 = (_zz__zz_decode_IS_RS2_SIGNED_125 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_127 = (_zz__zz_decode_IS_RS2_SIGNED_128 != _zz__zz_decode_IS_RS2_SIGNED_131); + assign _zz__zz_decode_IS_RS2_SIGNED_132 = {_zz__zz_decode_IS_RS2_SIGNED_133,{_zz__zz_decode_IS_RS2_SIGNED_141,_zz__zz_decode_IS_RS2_SIGNED_145}}; + assign _zz__zz_decode_IS_RS2_SIGNED_78 = 32'h00004020; + assign _zz__zz_decode_IS_RS2_SIGNED_80 = (decode_INSTRUCTION & 32'h00000030); + assign _zz__zz_decode_IS_RS2_SIGNED_81 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_83 = (decode_INSTRUCTION & 32'h02000020); + assign _zz__zz_decode_IS_RS2_SIGNED_84 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_89 = 32'h00002030; + assign _zz__zz_decode_IS_RS2_SIGNED_91 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_IS_RS2_SIGNED_92 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_94 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_95) == 32'h00002020); + assign _zz__zz_decode_IS_RS2_SIGNED_96 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_97) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_101 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_102 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_104 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_105) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_106 = (_zz__zz_decode_IS_RS2_SIGNED_107 == _zz__zz_decode_IS_RS2_SIGNED_108); + assign _zz__zz_decode_IS_RS2_SIGNED_109 = {_zz__zz_decode_IS_RS2_SIGNED_110,_zz__zz_decode_IS_RS2_SIGNED_111}; + assign _zz__zz_decode_IS_RS2_SIGNED_116 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_IS_RS2_SIGNED_117 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_120 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_121) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_125 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_126) == 32'h00004010); + assign _zz__zz_decode_IS_RS2_SIGNED_128 = (_zz__zz_decode_IS_RS2_SIGNED_129 == _zz__zz_decode_IS_RS2_SIGNED_130); + assign _zz__zz_decode_IS_RS2_SIGNED_131 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_133 = ({_zz__zz_decode_IS_RS2_SIGNED_134,_zz__zz_decode_IS_RS2_SIGNED_136} != 4'b0000); + assign _zz__zz_decode_IS_RS2_SIGNED_141 = (_zz__zz_decode_IS_RS2_SIGNED_142 != _zz__zz_decode_IS_RS2_SIGNED_144); + assign _zz__zz_decode_IS_RS2_SIGNED_145 = {_zz__zz_decode_IS_RS2_SIGNED_146,{_zz__zz_decode_IS_RS2_SIGNED_152,_zz__zz_decode_IS_RS2_SIGNED_156}}; + assign _zz__zz_decode_IS_RS2_SIGNED_95 = 32'h02002060; + assign _zz__zz_decode_IS_RS2_SIGNED_97 = 32'h02003020; + assign _zz__zz_decode_IS_RS2_SIGNED_105 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_107 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_108 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_110 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_111 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_121 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_126 = 32'h00004014; + assign _zz__zz_decode_IS_RS2_SIGNED_129 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_IS_RS2_SIGNED_130 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_134 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_135) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_136 = {(_zz__zz_decode_IS_RS2_SIGNED_137 == _zz__zz_decode_IS_RS2_SIGNED_138),{_zz__zz_decode_IS_RS2_SIGNED_139,_zz__zz_decode_IS_RS2_SIGNED_140}}; + assign _zz__zz_decode_IS_RS2_SIGNED_142 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_143) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_144 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_146 = ({_zz__zz_decode_IS_RS2_SIGNED_147,{_zz__zz_decode_IS_RS2_SIGNED_148,_zz__zz_decode_IS_RS2_SIGNED_150}} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_152 = ({_zz__zz_decode_IS_RS2_SIGNED_153,_zz__zz_decode_IS_RS2_SIGNED_155} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_156 = {(_zz__zz_decode_IS_RS2_SIGNED_157 != _zz__zz_decode_IS_RS2_SIGNED_160),(_zz__zz_decode_IS_RS2_SIGNED_161 != _zz__zz_decode_IS_RS2_SIGNED_163)}; + assign _zz__zz_decode_IS_RS2_SIGNED_135 = 32'h00000044; + assign _zz__zz_decode_IS_RS2_SIGNED_137 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_IS_RS2_SIGNED_138 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_139 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_140 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_143 = 32'h00000058; + assign _zz__zz_decode_IS_RS2_SIGNED_147 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_148 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_149) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_150 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_151) == 32'h40000030); + assign _zz__zz_decode_IS_RS2_SIGNED_153 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_154) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_155 = _zz_decode_IS_RS2_SIGNED_1; + assign _zz__zz_decode_IS_RS2_SIGNED_157 = {(_zz__zz_decode_IS_RS2_SIGNED_158 == _zz__zz_decode_IS_RS2_SIGNED_159),_zz_decode_IS_RS2_SIGNED_1}; + assign _zz__zz_decode_IS_RS2_SIGNED_160 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_161 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_162) == 32'h00001008); + assign _zz__zz_decode_IS_RS2_SIGNED_163 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_149 = 32'h00002014; + assign _zz__zz_decode_IS_RS2_SIGNED_151 = 32'h40000034; + assign _zz__zz_decode_IS_RS2_SIGNED_154 = 32'h00000014; + assign _zz__zz_decode_IS_RS2_SIGNED_158 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_RS2_SIGNED_159 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_162 = 32'h00005048; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_182 ), //i - .io_cpu_prefetch_isValid (_zz_183 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_184 ), //i - .io_cpu_fetch_isStuck (_zz_185 ), //i - .io_cpu_fetch_isRemoved (_zz_186 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_187 ), //i - .io_cpu_decode_isStuck (_zz_188 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_189 ), //i - .io_cpu_fill_valid (_zz_190 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_149[2:0] ), //i - ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i + ._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_191 ), //i - .io_cpu_execute_address (_zz_192[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_82[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_193 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_194[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_195 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_196 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_197 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_198[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_199 ), //i - .io_cpu_writeBack_fence_SR (_zz_200 ), //i - .io_cpu_writeBack_fence_SO (_zz_201 ), //i - .io_cpu_writeBack_fence_SI (_zz_202 ), //i - .io_cpu_writeBack_fence_PW (_zz_203 ), //i - .io_cpu_writeBack_fence_PR (_zz_204 ), //i - .io_cpu_writeBack_fence_PO (_zz_205 ), //i - .io_cpu_writeBack_fence_PI (_zz_206 ), //i - .io_cpu_writeBack_fence_FM (_zz_207[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_208 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_209 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_350) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) + 2'b00 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) 2'b00 : begin - _zz_212 = DBusCachedPlugin_redoBranch_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; end 2'b01 : begin - _zz_212 = CsrPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; end 2'b10 : begin - _zz_212 = BranchPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; end default : begin - _zz_212 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_30) - `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; - default : _zz_30_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_33) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; - default : _zz_33_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_34) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; - default : _zz_34_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_36) - `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; - default : _zz_36_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_37) - `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; - default : _zz_37_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_38) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; - default : _zz_38_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_39) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; - default : _zz_39_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_43) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; - default : _zz_43_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; - default : _zz_44_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_45) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; - default : _zz_45_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_46) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; - default : _zz_46_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_47) - `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; - default : _zz_47_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_48) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; - default : _zz_48_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_49) - `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; - default : _zz_49_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_92) - `Src1CtrlEnum_defaultEncoding_RS : _zz_92_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_92_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_92_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_92_string = "URS1 "; - default : _zz_92_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_93) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_93_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_93_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_93_string = "BITWISE "; - default : _zz_93_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_94) - `Src2CtrlEnum_defaultEncoding_RS : _zz_94_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_94_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_94_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_94_string = "PC "; - default : _zz_94_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_95) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_95_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_95_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_95_string = "AND_1"; - default : _zz_95_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_96) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_96_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_96_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_96_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_96_string = "SRA_1 "; - default : _zz_96_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_97) - `BranchCtrlEnum_defaultEncoding_INC : _zz_97_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_97_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_97_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_97_string = "JALR"; - default : _zz_97_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_98) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_98_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_98_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_98_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_98_string = "ECALL"; - default : _zz_98_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_254) + $signed(_zz_262)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2466,45 +2578,45 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_264; - assign execute_REGFILE_WRITE_DATA = _zz_100; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_192[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_266[0]; - assign decode_IS_RS1_SIGNED = _zz_267[0]; - assign decode_IS_DIV = _zz_268[0]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_RS2_SIGNED[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_RS2_SIGNED[30]; + assign decode_IS_DIV = _zz_decode_IS_RS2_SIGNED[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_269[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_270[0]; - assign _zz_8 = _zz_9; - assign _zz_10 = _zz_11; - assign decode_SHIFT_CTRL = _zz_12; - assign _zz_13 = _zz_14; - assign decode_ALU_BITWISE_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_271[0]; - assign decode_MEMORY_MANAGMENT = _zz_272[0]; + assign decode_IS_MUL = _zz_decode_IS_RS2_SIGNED[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_RS2_SIGNED[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_RS2_SIGNED[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_RS2_SIGNED[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_273[0]; + assign decode_MEMORY_WR = _zz_decode_IS_RS2_SIGNED[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_274[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_275[0]; - assign decode_SRC2_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_ALU_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_SRC1_CTRL = _zz_24; - assign _zz_25 = _zz_26; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_RS2_SIGNED[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_RS2_SIGNED[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; @@ -2512,7 +2624,7 @@ module VexRiscv ( assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_276[0]; + assign decode_IS_EBREAK = _zz_decode_IS_RS2_SIGNED[32]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2526,22 +2638,22 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27; - assign execute_ENV_CTRL = _zz_28; - assign writeBack_ENV_CTRL = _zz_29; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_122; - assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_277[0]; - assign decode_RS1_USE = _zz_278[0]; - always @ (*) begin - _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_213)begin - _zz_31 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_RS2_SIGNED[15]; + assign decode_RS1_USE = _zz_decode_IS_RS2_SIGNED[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2551,139 +2663,139 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_111)begin - if((_zz_112 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_113; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_214)begin - if(_zz_215)begin - if(_zz_115)begin - decode_RS2 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_216)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_117)begin - decode_RS2 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_217)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_119)begin - decode_RS2 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_111)begin - if((_zz_112 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_113; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_214)begin - if(_zz_215)begin - if(_zz_114)begin - decode_RS1 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_216)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_116)begin - decode_RS1 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_217)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_118)begin - decode_RS1 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_32 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_32 = _zz_108; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_32 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_218)begin - _zz_32 = memory_DivPlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_33; - assign execute_SHIFT_CTRL = _zz_34; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_35 = execute_PC; - assign execute_SRC2_CTRL = _zz_36; - assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_279[0]; - assign decode_SRC_ADD_ZERO = _zz_280[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_RS2_SIGNED[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_RS2_SIGNED[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_38; - assign execute_SRC2 = _zz_106; - assign execute_SRC1 = _zz_101; - assign execute_ALU_BITWISE_CTRL = _zz_39; - assign _zz_40 = writeBack_INSTRUCTION; - assign _zz_41 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_42 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_42 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_281[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_RS2_SIGNED[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_351) == 32'h00001073),{(_zz_352 == _zz_353),{_zz_354,{_zz_355,_zz_356}}}}}}} != 21'h0); - always @ (*) begin - _zz_50 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_50 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 21'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_253) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_50 = _zz_323; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_50 = _zz_324; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2695,61 +2807,61 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_282[0]; - assign decode_FLUSH_ALL = _zz_283[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_IS_RS2_SIGNED[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_RS2_SIGNED[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_219)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_220)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_221)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_222)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_51; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_52 = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_52 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_53 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end - case(_zz_149) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2758,166 +2870,166 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_109 || _zz_110)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_223)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_223)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_208 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_224)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_213)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_225)begin + if(when_DebugPlugin_l284) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_225)begin - if(_zz_226)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushIt = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_225)begin - if(_zz_226)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushNext = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_218)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_227)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_228)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2926,75 +3038,77 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_227)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_228)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_225)begin - if(_zz_226)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_229)begin + if(when_DebugPlugin_l300) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin - _zz_54 = 1'b0; - if(DebugPlugin_godmode)begin - _zz_54 = 1'b1; + always @(*) begin + _zz_when_DBusCachedPlugin_l386 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l386 = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_224)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin CsrPlugin_thirdPartyWake = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_227)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_228)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_227)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_228)begin - case(_zz_230) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3004,80 +3118,92 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_forceMachineWire = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + if(when_DebugPlugin_l316) begin CsrPlugin_allowInterrupts = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_allowException = 1'b0; end end + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_55 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_56 = (_zz_55 & (~ _zz_284)); - assign _zz_57 = _zz_56[3]; - assign _zz_58 = (_zz_56[1] || _zz_57); - assign _zz_59 = (_zz_56[2] || _zz_57); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_212; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_286); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3085,66 +3211,75 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_60); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_60); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_61); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_61); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_62 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_62); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_62); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_63; - assign _zz_63 = ((1'b0 && (! _zz_64)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_64 = _zz_65; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_64; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_66)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_66 = _zz_67; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_66; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_68; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); - always @ (*) begin + always @(*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_149) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3156,207 +3291,219 @@ module VexRiscv ( endcase end - assign _zz_69 = _zz_287[11]; - always @ (*) begin - _zz_70[18] = _zz_69; - _zz_70[17] = _zz_69; - _zz_70[16] = _zz_69; - _zz_70[15] = _zz_69; - _zz_70[14] = _zz_69; - _zz_70[13] = _zz_69; - _zz_70[12] = _zz_69; - _zz_70[11] = _zz_69; - _zz_70[10] = _zz_69; - _zz_70[9] = _zz_69; - _zz_70[8] = _zz_69; - _zz_70[7] = _zz_69; - _zz_70[6] = _zz_69; - _zz_70[5] = _zz_69; - _zz_70[4] = _zz_69; - _zz_70[3] = _zz_69; - _zz_70[2] = _zz_69; - _zz_70[1] = _zz_69; - _zz_70[0] = _zz_69; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_288[31])); - if(_zz_75)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_71 = _zz_289[19]; - always @ (*) begin - _zz_72[10] = _zz_71; - _zz_72[9] = _zz_71; - _zz_72[8] = _zz_71; - _zz_72[7] = _zz_71; - _zz_72[6] = _zz_71; - _zz_72[5] = _zz_71; - _zz_72[4] = _zz_71; - _zz_72[3] = _zz_71; - _zz_72[2] = _zz_71; - _zz_72[1] = _zz_71; - _zz_72[0] = _zz_71; - end - - assign _zz_73 = _zz_290[11]; - always @ (*) begin - _zz_74[18] = _zz_73; - _zz_74[17] = _zz_73; - _zz_74[16] = _zz_73; - _zz_74[15] = _zz_73; - _zz_74[14] = _zz_73; - _zz_74[13] = _zz_73; - _zz_74[12] = _zz_73; - _zz_74[11] = _zz_73; - _zz_74[10] = _zz_73; - _zz_74[9] = _zz_73; - _zz_74[8] = _zz_73; - _zz_74[7] = _zz_73; - _zz_74[6] = _zz_73; - _zz_74[5] = _zz_73; - _zz_74[4] = _zz_73; - _zz_74[3] = _zz_73; - _zz_74[2] = _zz_73; - _zz_74[1] = _zz_73; - _zz_74[0] = _zz_73; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_75 = _zz_291[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_75 = _zz_292[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_76 = _zz_293[19]; - always @ (*) begin - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7] = _zz_76; - _zz_77[6] = _zz_76; - _zz_77[5] = _zz_76; - _zz_77[4] = _zz_76; - _zz_77[3] = _zz_76; - _zz_77[2] = _zz_76; - _zz_77[1] = _zz_76; - _zz_77[0] = _zz_76; - end - - assign _zz_78 = _zz_294[11]; - always @ (*) begin - _zz_79[18] = _zz_78; - _zz_79[17] = _zz_78; - _zz_79[16] = _zz_78; - _zz_79[15] = _zz_78; - _zz_79[14] = _zz_78; - _zz_79[13] = _zz_78; - _zz_79[12] = _zz_78; - _zz_79[11] = _zz_78; - _zz_79[10] = _zz_78; - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7] = _zz_78; - _zz_79[6] = _zz_78; - _zz_79[5] = _zz_78; - _zz_79[4] = _zz_78; - _zz_79[3] = _zz_78; - _zz_79[2] = _zz_78; - _zz_79[1] = _zz_78; - _zz_79[0] = _zz_78; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_77,{{{_zz_369,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_79,{{{_zz_370,_zz_371},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_183 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_184 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_185 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_184; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_187 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_188 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_189 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_222)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_220)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_190 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_220)begin - _zz_190 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_221)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_219)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_221)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_219)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_182 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_209 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3364,168 +3511,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_191 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_192 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_82 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_82 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_82 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_208 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_193 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_194 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_193; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_194; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_195 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_54 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_195 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_196 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_197 = (CsrPlugin_privilege == 2'b00); - assign _zz_198 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_231)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_231)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_231)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_295}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_296}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; end - assign _zz_83 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_84[31] = _zz_83; - _zz_84[30] = _zz_83; - _zz_84[29] = _zz_83; - _zz_84[28] = _zz_83; - _zz_84[27] = _zz_83; - _zz_84[26] = _zz_83; - _zz_84[25] = _zz_83; - _zz_84[24] = _zz_83; - _zz_84[23] = _zz_83; - _zz_84[22] = _zz_83; - _zz_84[21] = _zz_83; - _zz_84[20] = _zz_83; - _zz_84[19] = _zz_83; - _zz_84[18] = _zz_83; - _zz_84[17] = _zz_83; - _zz_84[16] = _zz_83; - _zz_84[15] = _zz_83; - _zz_84[14] = _zz_83; - _zz_84[13] = _zz_83; - _zz_84[12] = _zz_83; - _zz_84[11] = _zz_83; - _zz_84[10] = _zz_83; - _zz_84[9] = _zz_83; - _zz_84[8] = _zz_83; - _zz_84[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_85 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_86[31] = _zz_85; - _zz_86[30] = _zz_85; - _zz_86[29] = _zz_85; - _zz_86[28] = _zz_85; - _zz_86[27] = _zz_85; - _zz_86[26] = _zz_85; - _zz_86[25] = _zz_85; - _zz_86[24] = _zz_85; - _zz_86[23] = _zz_85; - _zz_86[22] = _zz_85; - _zz_86[21] = _zz_85; - _zz_86[20] = _zz_85; - _zz_86[19] = _zz_85; - _zz_86[18] = _zz_85; - _zz_86[17] = _zz_85; - _zz_86[16] = _zz_85; - _zz_86[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_251) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_84; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_86; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3544,59 +3702,60 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_88 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_89 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_90 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_91 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_87 = {(((decode_INSTRUCTION & _zz_372) == 32'h00100050) != 1'b0),{(_zz_91 != 1'b0),{(_zz_91 != 1'b0),{(_zz_373 != _zz_374),{_zz_375,{_zz_376,_zz_377}}}}}}; - assign _zz_92 = _zz_87[2 : 1]; - assign _zz_49 = _zz_92; - assign _zz_93 = _zz_87[7 : 6]; - assign _zz_48 = _zz_93; - assign _zz_94 = _zz_87[9 : 8]; - assign _zz_47 = _zz_94; - assign _zz_95 = _zz_87[19 : 18]; - assign _zz_46 = _zz_95; - assign _zz_96 = _zz_87[22 : 21]; - assign _zz_45 = _zz_96; - assign _zz_97 = _zz_87[24 : 23]; - assign _zz_44 = _zz_97; - assign _zz_98 = _zz_87[27 : 26]; - assign _zz_43 = _zz_98; + assign _zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_RS2_SIGNED_4 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_IS_RS2_SIGNED = {(((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED) == 32'h00100050) != 1'b0),{(_zz_decode_IS_RS2_SIGNED_4 != 1'b0),{(_zz_decode_IS_RS2_SIGNED_4 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_1 != _zz__zz_decode_IS_RS2_SIGNED_2),{_zz__zz_decode_IS_RS2_SIGNED_3,{_zz__zz_decode_IS_RS2_SIGNED_5,_zz__zz_decode_IS_RS2_SIGNED_8}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_RS2_SIGNED[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_RS2_SIGNED[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_RS2_SIGNED[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_RS2_SIGNED[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_RS2_SIGNED[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_RS2_SIGNED[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_RS2_SIGNED[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_210; - assign decode_RegFilePlugin_rs2Data = _zz_211; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); - if(_zz_99)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; - if(_zz_99)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_50; - if(_zz_99)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3605,355 +3764,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_100 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_100 = {31'd0, _zz_297}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_100 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_101 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_101 = {29'd0, _zz_298}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_101 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_101 = {27'd0, _zz_299}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_102 = _zz_300[11]; - always @ (*) begin - _zz_103[19] = _zz_102; - _zz_103[18] = _zz_102; - _zz_103[17] = _zz_102; - _zz_103[16] = _zz_102; - _zz_103[15] = _zz_102; - _zz_103[14] = _zz_102; - _zz_103[13] = _zz_102; - _zz_103[12] = _zz_102; - _zz_103[11] = _zz_102; - _zz_103[10] = _zz_102; - _zz_103[9] = _zz_102; - _zz_103[8] = _zz_102; - _zz_103[7] = _zz_102; - _zz_103[6] = _zz_102; - _zz_103[5] = _zz_102; - _zz_103[4] = _zz_102; - _zz_103[3] = _zz_102; - _zz_103[2] = _zz_102; - _zz_103[1] = _zz_102; - _zz_103[0] = _zz_102; - end - - assign _zz_104 = _zz_301[11]; - always @ (*) begin - _zz_105[19] = _zz_104; - _zz_105[18] = _zz_104; - _zz_105[17] = _zz_104; - _zz_105[16] = _zz_104; - _zz_105[15] = _zz_104; - _zz_105[14] = _zz_104; - _zz_105[13] = _zz_104; - _zz_105[12] = _zz_104; - _zz_105[11] = _zz_104; - _zz_105[10] = _zz_104; - _zz_105[9] = _zz_104; - _zz_105[8] = _zz_104; - _zz_105[7] = _zz_104; - _zz_105[6] = _zz_104; - _zz_105[5] = _zz_104; - _zz_105[4] = _zz_104; - _zz_105[3] = _zz_104; - _zz_105[2] = _zz_104; - _zz_105[1] = _zz_104; - _zz_105[0] = _zz_104; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_106 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_106 = {_zz_103,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_106 = {_zz_105,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_106 = _zz_35; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_302; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_107[0] = execute_SRC1[31]; - _zz_107[1] = execute_SRC1[30]; - _zz_107[2] = execute_SRC1[29]; - _zz_107[3] = execute_SRC1[28]; - _zz_107[4] = execute_SRC1[27]; - _zz_107[5] = execute_SRC1[26]; - _zz_107[6] = execute_SRC1[25]; - _zz_107[7] = execute_SRC1[24]; - _zz_107[8] = execute_SRC1[23]; - _zz_107[9] = execute_SRC1[22]; - _zz_107[10] = execute_SRC1[21]; - _zz_107[11] = execute_SRC1[20]; - _zz_107[12] = execute_SRC1[19]; - _zz_107[13] = execute_SRC1[18]; - _zz_107[14] = execute_SRC1[17]; - _zz_107[15] = execute_SRC1[16]; - _zz_107[16] = execute_SRC1[15]; - _zz_107[17] = execute_SRC1[14]; - _zz_107[18] = execute_SRC1[13]; - _zz_107[19] = execute_SRC1[12]; - _zz_107[20] = execute_SRC1[11]; - _zz_107[21] = execute_SRC1[10]; - _zz_107[22] = execute_SRC1[9]; - _zz_107[23] = execute_SRC1[8]; - _zz_107[24] = execute_SRC1[7]; - _zz_107[25] = execute_SRC1[6]; - _zz_107[26] = execute_SRC1[5]; - _zz_107[27] = execute_SRC1[4]; - _zz_107[28] = execute_SRC1[3]; - _zz_107[29] = execute_SRC1[2]; - _zz_107[30] = execute_SRC1[1]; - _zz_107[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_107 : execute_SRC1); - always @ (*) begin - _zz_108[0] = memory_SHIFT_RIGHT[31]; - _zz_108[1] = memory_SHIFT_RIGHT[30]; - _zz_108[2] = memory_SHIFT_RIGHT[29]; - _zz_108[3] = memory_SHIFT_RIGHT[28]; - _zz_108[4] = memory_SHIFT_RIGHT[27]; - _zz_108[5] = memory_SHIFT_RIGHT[26]; - _zz_108[6] = memory_SHIFT_RIGHT[25]; - _zz_108[7] = memory_SHIFT_RIGHT[24]; - _zz_108[8] = memory_SHIFT_RIGHT[23]; - _zz_108[9] = memory_SHIFT_RIGHT[22]; - _zz_108[10] = memory_SHIFT_RIGHT[21]; - _zz_108[11] = memory_SHIFT_RIGHT[20]; - _zz_108[12] = memory_SHIFT_RIGHT[19]; - _zz_108[13] = memory_SHIFT_RIGHT[18]; - _zz_108[14] = memory_SHIFT_RIGHT[17]; - _zz_108[15] = memory_SHIFT_RIGHT[16]; - _zz_108[16] = memory_SHIFT_RIGHT[15]; - _zz_108[17] = memory_SHIFT_RIGHT[14]; - _zz_108[18] = memory_SHIFT_RIGHT[13]; - _zz_108[19] = memory_SHIFT_RIGHT[12]; - _zz_108[20] = memory_SHIFT_RIGHT[11]; - _zz_108[21] = memory_SHIFT_RIGHT[10]; - _zz_108[22] = memory_SHIFT_RIGHT[9]; - _zz_108[23] = memory_SHIFT_RIGHT[8]; - _zz_108[24] = memory_SHIFT_RIGHT[7]; - _zz_108[25] = memory_SHIFT_RIGHT[6]; - _zz_108[26] = memory_SHIFT_RIGHT[5]; - _zz_108[27] = memory_SHIFT_RIGHT[4]; - _zz_108[28] = memory_SHIFT_RIGHT[3]; - _zz_108[29] = memory_SHIFT_RIGHT[2]; - _zz_108[30] = memory_SHIFT_RIGHT[1]; - _zz_108[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_109 = 1'b0; - if(_zz_232)begin - if(_zz_233)begin - if(_zz_114)begin - _zz_109 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_234)begin - if(_zz_235)begin - if(_zz_116)begin - _zz_109 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_236)begin - if(_zz_237)begin - if(_zz_118)begin - _zz_109 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_109 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_110 = 1'b0; - if(_zz_232)begin - if(_zz_233)begin - if(_zz_115)begin - _zz_110 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_234)begin - if(_zz_235)begin - if(_zz_117)begin - _zz_110 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_236)begin - if(_zz_237)begin - if(_zz_119)begin - _zz_110 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_110 = 1'b0; - end - end - - assign _zz_114 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_115 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_116 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_117 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_118 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_119 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_120 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_120 == 3'b000)) begin - _zz_121 = execute_BranchPlugin_eq; - end else if((_zz_120 == 3'b001)) begin - _zz_121 = (! execute_BranchPlugin_eq); - end else if((((_zz_120 & 3'b101) == 3'b101))) begin - _zz_121 = (! execute_SRC_LESS); - end else begin - _zz_121 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_122 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_122 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_122 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_122 = _zz_121; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_123 = _zz_309[11]; - always @ (*) begin - _zz_124[19] = _zz_123; - _zz_124[18] = _zz_123; - _zz_124[17] = _zz_123; - _zz_124[16] = _zz_123; - _zz_124[15] = _zz_123; - _zz_124[14] = _zz_123; - _zz_124[13] = _zz_123; - _zz_124[12] = _zz_123; - _zz_124[11] = _zz_123; - _zz_124[10] = _zz_123; - _zz_124[9] = _zz_123; - _zz_124[8] = _zz_123; - _zz_124[7] = _zz_123; - _zz_124[6] = _zz_123; - _zz_124[5] = _zz_123; - _zz_124[4] = _zz_123; - _zz_124[3] = _zz_123; - _zz_124[2] = _zz_123; - _zz_124[1] = _zz_123; - _zz_124[0] = _zz_123; - end - - assign _zz_125 = _zz_310[19]; - always @ (*) begin - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; - end - - assign _zz_127 = _zz_311[11]; - always @ (*) begin - _zz_128[18] = _zz_127; - _zz_128[17] = _zz_127; - _zz_128[16] = _zz_127; - _zz_128[15] = _zz_127; - _zz_128[14] = _zz_127; - _zz_128[13] = _zz_127; - _zz_128[12] = _zz_127; - _zz_128[11] = _zz_127; - _zz_128[10] = _zz_127; - _zz_128[9] = _zz_127; - _zz_128[8] = _zz_127; - _zz_128[7] = _zz_127; - _zz_128[6] = _zz_127; - _zz_128[5] = _zz_127; - _zz_128[4] = _zz_127; - _zz_128[3] = _zz_127; - _zz_128[2] = _zz_127; - _zz_128[1] = _zz_127; - _zz_128[0] = _zz_127; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_129 = (_zz_312[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_129 = _zz_313[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_129 = _zz_314[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_129); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -3962,80 +4144,80 @@ module VexRiscv ( endcase end - assign _zz_130 = _zz_315[11]; - always @ (*) begin - _zz_131[19] = _zz_130; - _zz_131[18] = _zz_130; - _zz_131[17] = _zz_130; - _zz_131[16] = _zz_130; - _zz_131[15] = _zz_130; - _zz_131[14] = _zz_130; - _zz_131[13] = _zz_130; - _zz_131[12] = _zz_130; - _zz_131[11] = _zz_130; - _zz_131[10] = _zz_130; - _zz_131[9] = _zz_130; - _zz_131[8] = _zz_130; - _zz_131[7] = _zz_130; - _zz_131[6] = _zz_130; - _zz_131[5] = _zz_130; - _zz_131[4] = _zz_130; - _zz_131[3] = _zz_130; - _zz_131[2] = _zz_130; - _zz_131[1] = _zz_130; - _zz_131[0] = _zz_130; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_131,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_133,{{{_zz_536,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_135,{{{_zz_537,_zz_538},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_318}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_132 = _zz_316[19]; - always @ (*) begin - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; - end - - assign _zz_134 = _zz_317[11]; - always @ (*) begin - _zz_135[18] = _zz_134; - _zz_135[17] = _zz_134; - _zz_135[16] = _zz_134; - _zz_135[15] = _zz_134; - _zz_135[14] = _zz_134; - _zz_135[13] = _zz_134; - _zz_135[12] = _zz_134; - _zz_135[11] = _zz_134; - _zz_135[10] = _zz_134; - _zz_135[9] = _zz_134; - _zz_135[8] = _zz_134; - _zz_135[7] = _zz_134; - _zz_135[6] = _zz_134; - _zz_135[5] = _zz_134; - _zz_135[4] = _zz_134; - _zz_135[3] = _zz_134; - _zz_135[2] = _zz_134; - _zz_135[1] = _zz_134; - _zz_135[0] = _zz_134; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -4045,92 +4227,106 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_136 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_137 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_138 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_139 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_140 = _zz_319[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_223)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4141,8 +4337,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4152,135 +4348,144 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_238)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_239)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_240)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_239)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_240)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4293,39 +4498,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_238)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_238)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_252) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_241) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4338,8 +4553,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_241) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4358,58 +4573,69 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_321) + $signed(_zz_322)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_218)begin - if(_zz_242)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_243)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_326); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_141 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_141[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_327); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_328 : _zz_329); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_330[31:0]; - assign _zz_142 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_143 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_144 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_145[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_145[31 : 0] = execute_RS1; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; end - assign _zz_147 = (_zz_146 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_147 != 32'h0); - always @ (*) begin + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_244) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end end @@ -4419,9 +4645,9 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_148))begin + if(when_DebugPlugin_l244) begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4430,12 +4656,13 @@ module VexRiscv ( end end - always @ (*) begin + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_244) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin IBusCachedPlugin_injectionPort_valid = 1'b1; end end @@ -4446,35 +4673,110 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_26 = decode_SRC1_CTRL; - assign _zz_24 = _zz_49; - assign _zz_37 = decode_to_execute_SRC1_CTRL; - assign _zz_23 = decode_ALU_CTRL; - assign _zz_21 = _zz_48; - assign _zz_38 = decode_to_execute_ALU_CTRL; - assign _zz_20 = decode_SRC2_CTRL; - assign _zz_18 = _zz_47; - assign _zz_36 = decode_to_execute_SRC2_CTRL; - assign _zz_17 = decode_ALU_BITWISE_CTRL; - assign _zz_15 = _zz_46; - assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_14 = decode_SHIFT_CTRL; - assign _zz_11 = execute_SHIFT_CTRL; - assign _zz_12 = _zz_45; - assign _zz_34 = decode_to_execute_SHIFT_CTRL; - assign _zz_33 = execute_to_memory_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_51 = _zz_44; - assign _zz_30 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_43; - assign _zz_28 = decode_to_execute_ENV_CTRL; - assign _zz_27 = execute_to_memory_ENV_CTRL; - assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4495,9 +4797,15 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_149) + case(switch_Fetcher_l362) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4506,240 +4814,268 @@ module VexRiscv ( endcase end - always @ (*) begin - _zz_150 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_150[12 : 0] = 13'h1000; - _zz_150[25 : 20] = 6'h20; + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_151 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_151[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_152 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_152[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_153 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_153[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_154 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_154[31 : 30] = CsrPlugin_misa_base; - _zz_154[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_155 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_155[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_155[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_155[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_156 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_156[11 : 11] = CsrPlugin_mip_MEIP; - _zz_156[7 : 7] = CsrPlugin_mip_MTIP; - _zz_156[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_157 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_157[11 : 11] = CsrPlugin_mie_MEIE; - _zz_157[7 : 7] = CsrPlugin_mie_MTIE; - _zz_157[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_158 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_158[31 : 2] = CsrPlugin_mtvec_base; - _zz_158[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_159 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_159[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_160 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_160[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_161 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_161[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_161[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_162 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_162[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_163 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_163[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_164 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_164[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_165 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_165[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_166 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_166[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_167 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_167[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_168 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_168[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_169 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_169[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_170 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_170[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_171 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_171[31 : 0] = _zz_146; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_172 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_172[31 : 0] = _zz_147; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = (((((_zz_150 | _zz_151) | (_zz_152 | _zz_153)) | ((_zz_539 | _zz_154) | (_zz_155 | _zz_156))) | (((_zz_157 | _zz_158) | (_zz_159 | _zz_160)) | ((_zz_161 | _zz_162) | (_zz_163 | _zz_164)))) | (((_zz_165 | _zz_166) | (_zz_167 | _zz_168)) | ((_zz_169 | _zz_170) | (_zz_171 | _zz_172)))); - assign iBusWishbone_ADR = {_zz_347,_zz_173}; - assign iBusWishbone_CTI = ((_zz_173 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_245)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_245)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_174; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_180 = (dBus_cmd_payload_length != 3'b000); - assign _zz_176 = dBus_cmd_valid; - assign _zz_178 = dBus_cmd_payload_wr; - assign _zz_179 = (_zz_175 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_177 && (_zz_178 || _zz_179)); - assign dBusWishbone_ADR = ((_zz_180 ? {{dBus_cmd_payload_address[31 : 5],_zz_175},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_180 ? (_zz_179 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_178 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_178; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_177 = (_zz_176 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_176; - assign dBusWishbone_STB = _zz_176; - assign dBus_rsp_valid = _zz_181; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_65 <= 1'b0; - _zz_67 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_80; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_81; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_99 <= 1'b1; - _zz_111 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4760,160 +5096,160 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_146 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_149 <= 3'b000; - _zz_173 <= 3'b000; - _zz_174 <= 1'b0; - _zz_175 <= 3'b000; - _zz_181 <= 1'b0; + switch_Fetcher_l362 <= 3'b000; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_65 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_63)begin - _zz_65 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_67 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_67 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_246)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_99 <= 1'b0; - _zz_111 <= (_zz_41 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_247)begin - if(_zz_248)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_249)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_250)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_227)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4924,8 +5260,8 @@ module VexRiscv ( end endcase end - if(_zz_228)begin - case(_zz_230) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4935,164 +5271,164 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_138,{_zz_137,_zz_136}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_149) + case(switch_Fetcher_l362) 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_149 <= 3'b001; + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; end end 3'b001 : begin - _zz_149 <= 3'b010; + switch_Fetcher_l362 <= 3'b010; end 3'b010 : begin - _zz_149 <= 3'b011; + switch_Fetcher_l362 <= 3'b011; end 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_149 <= 3'b100; + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; end end 3'b100 : begin - _zz_149 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; end default : begin end endcase - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_340[0]; - CsrPlugin_mstatus_MIE <= _zz_341[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_343[0]; - CsrPlugin_mie_MTIE <= _zz_344[0]; - CsrPlugin_mie_MSIE <= _zz_345[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_245)begin - if(iBusWishbone_ACK)begin - _zz_173 <= (_zz_173 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_174 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_176 && _zz_177))begin - _zz_175 <= (_zz_175 + 3'b001); - if(_zz_179)begin - _zz_175 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_181 <= ((_zz_176 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_68 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_246)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_112 <= _zz_40[11 : 7]; - _zz_113 <= _zz_50; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_223)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_140 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_140 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_247)begin - if(_zz_248)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_249)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_250)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_227)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5100,410 +5436,421 @@ module VexRiscv ( end endcase end - if((memory_DivPlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_DivPlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_218)begin - if(_zz_242)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_331[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; end end end - if(_zz_243)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_144 ? (~ _zz_145) : _zz_145) + _zz_337); - memory_DivPlugin_rs2 <= ((_zz_143 ? (~ execute_RS2) : execute_RS2) + _zz_339); - memory_DivPlugin_div_needRevert <= ((_zz_144 ^ (_zz_143 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_35; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_7) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_25; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_22; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_19; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_10; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_50) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_51) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + if(when_Pipeline_l124_52) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + if(when_Pipeline_l124_53) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_54) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_62) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_342[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_346[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end - always @ (posedge clk) begin + always @(posedge clk) begin DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin + if(debug_bus_cmd_ready) begin DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_50; + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; end - _zz_148 <= debug_bus_cmd_payload_address[2]; - if(_zz_225)begin + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin + always @(posedge clk) begin if(debugReset) begin DebugPlugin_resetIt <= 1'b0; DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + if(when_DebugPlugin_l225) begin DebugPlugin_godmode <= 1'b1; end - if(debug_bus_cmd_valid)begin - case(_zz_244) + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin + if(when_DebugPlugin_l260) begin DebugPlugin_resetIt <= 1'b1; end - if(debug_bus_cmd_payload_data[24])begin + if(when_DebugPlugin_l260_1) begin DebugPlugin_resetIt <= 1'b0; end - if(debug_bus_cmd_payload_data[17])begin + if(when_DebugPlugin_l261) begin DebugPlugin_haltIt <= 1'b1; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l261_1) begin DebugPlugin_haltIt <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l262) begin DebugPlugin_haltedByBreak <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l263) begin DebugPlugin_godmode <= 1'b0; end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end end end default : begin end endcase end - if(_zz_225)begin - if(_zz_226)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_229)begin - if(decode_arbitration_isValid)begin + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin DebugPlugin_haltIt <= 1'b1; end end @@ -5516,9 +5863,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -5540,6 +5886,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -5555,9 +5902,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -5565,7 +5913,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -5574,24 +5922,15 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -5616,40 +5955,48 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5659,23 +6006,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -5683,10 +6040,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -5698,59 +6063,54 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -5765,274 +6125,293 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -6040,89 +6419,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_16)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6130,12 +6493,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6146,20 +6509,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6167,45 +6550,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6216,46 +6601,37 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; @@ -6263,50 +6639,51 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6353,18 +6730,14 @@ module InstructionCache ( input io_mem_rsp_valid, input [31:0] io_mem_rsp_payload_data, input io_mem_rsp_payload_error, - input [2:0] _zz_9, - input [31:0] _zz_10, + input [2:0] _zz_when_Fetcher_l398, + input [31:0] _zz_io_cpu_fetch_data_regNextWhen, input clk, input reset ); - reg [31:0] _zz_11; - reg [21:0] _zz_12; - wire _zz_13; - wire _zz_14; - wire [0:0] _zz_15; - wire [0:0] _zz_16; - wire [21:0] _zz_17; + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6373,8 +6746,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -6388,22 +6766,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -6413,82 +6794,86 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; + wire when_Fetcher_l398; (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - assign _zz_13 = (! lineLoader_flushCounter[7]); - assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_15 = _zz_8[0 : 0]; - assign _zz_16 = _zz_8[1 : 1]; - assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_11 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_12 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_13)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -6504,30 +6889,36 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_12; - assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000); + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -6535,51 +6926,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_14)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_13)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_14)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 8'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -6590,14 +6981,14 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end - if((_zz_9 != 3'b000))begin - io_cpu_fetch_data_regNextWhen <= _zz_10; + if(when_Fetcher_l398) begin + io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v index 7ca7550..330be8a 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v @@ -1,47 +1,47 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 - - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -74,38 +74,39 @@ module VexRiscv ( input clk, input reset ); - wire _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire [31:0] _zz_203; - reg _zz_204; - wire _zz_205; - wire [31:0] _zz_206; - wire _zz_207; - wire [31:0] _zz_208; - reg _zz_209; - wire _zz_210; - wire _zz_211; - wire [31:0] _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - wire _zz_219; - wire _zz_220; - wire [3:0] _zz_221; - wire _zz_222; - wire _zz_223; - reg [31:0] _zz_224; - reg [31:0] _zz_225; - reg [31:0] _zz_226; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_fetch_isUser; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_pc; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + reg dataCache_1_io_cpu_execute_args_isLrsc; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire IBusCachedPlugin_cache_io_cpu_fetch_error; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; @@ -128,6 +129,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -136,340 +138,304 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_227; - wire _zz_228; - wire _zz_229; - wire _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire [1:0] _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire _zz_245; - wire _zz_246; - wire _zz_247; - wire _zz_248; - wire _zz_249; - wire _zz_250; - wire _zz_251; - wire _zz_252; - wire [1:0] _zz_253; - wire _zz_254; - wire _zz_255; - wire _zz_256; - wire _zz_257; - wire _zz_258; - wire _zz_259; - wire _zz_260; - wire _zz_261; - wire _zz_262; - wire [4:0] _zz_263; - wire [1:0] _zz_264; - wire [1:0] _zz_265; - wire [1:0] _zz_266; - wire _zz_267; - wire [1:0] _zz_268; - wire [51:0] _zz_269; - wire [51:0] _zz_270; - wire [51:0] _zz_271; - wire [32:0] _zz_272; - wire [51:0] _zz_273; - wire [49:0] _zz_274; - wire [51:0] _zz_275; - wire [49:0] _zz_276; - wire [51:0] _zz_277; - wire [32:0] _zz_278; - wire [31:0] _zz_279; - wire [32:0] _zz_280; - wire [0:0] _zz_281; - wire [0:0] _zz_282; - wire [0:0] _zz_283; - wire [0:0] _zz_284; - wire [0:0] _zz_285; - wire [0:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; - wire [0:0] _zz_289; - wire [0:0] _zz_290; - wire [2:0] _zz_291; - wire [31:0] _zz_292; - wire [0:0] _zz_293; - wire [0:0] _zz_294; - wire [0:0] _zz_295; - wire [0:0] _zz_296; - wire [0:0] _zz_297; - wire [0:0] _zz_298; - wire [0:0] _zz_299; - wire [3:0] _zz_300; - wire [2:0] _zz_301; - wire [31:0] _zz_302; - wire [2:0] _zz_303; - wire [31:0] _zz_304; - wire [31:0] _zz_305; - wire [11:0] _zz_306; - wire [11:0] _zz_307; - wire [11:0] _zz_308; - wire [31:0] _zz_309; - wire [19:0] _zz_310; - wire [11:0] _zz_311; - wire [2:0] _zz_312; - wire [2:0] _zz_313; - wire [0:0] _zz_314; - wire [2:0] _zz_315; - wire [4:0] _zz_316; - wire [11:0] _zz_317; - wire [11:0] _zz_318; - wire [31:0] _zz_319; - wire [31:0] _zz_320; - wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [11:0] _zz_326; - wire [19:0] _zz_327; - wire [11:0] _zz_328; - wire [2:0] _zz_329; - wire [1:0] _zz_330; - wire [1:0] _zz_331; - wire [65:0] _zz_332; - wire [65:0] _zz_333; - wire [31:0] _zz_334; - wire [31:0] _zz_335; - wire [0:0] _zz_336; - wire [5:0] _zz_337; - wire [32:0] _zz_338; - wire [31:0] _zz_339; - wire [31:0] _zz_340; - wire [32:0] _zz_341; - wire [32:0] _zz_342; - wire [32:0] _zz_343; - wire [32:0] _zz_344; - wire [0:0] _zz_345; - wire [32:0] _zz_346; - wire [0:0] _zz_347; - wire [32:0] _zz_348; - wire [0:0] _zz_349; - wire [31:0] _zz_350; - wire [0:0] _zz_351; - wire [0:0] _zz_352; - wire [0:0] _zz_353; - wire [0:0] _zz_354; - wire [0:0] _zz_355; - wire [0:0] _zz_356; - wire [0:0] _zz_357; - wire [26:0] _zz_358; - wire _zz_359; - wire _zz_360; - wire [1:0] _zz_361; - wire [31:0] _zz_362; - wire [31:0] _zz_363; - wire [31:0] _zz_364; - wire _zz_365; - wire [0:0] _zz_366; - wire [13:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; - wire [31:0] _zz_370; - wire _zz_371; - wire [0:0] _zz_372; - wire [7:0] _zz_373; - wire [31:0] _zz_374; - wire [31:0] _zz_375; - wire [31:0] _zz_376; - wire _zz_377; - wire [0:0] _zz_378; - wire [1:0] _zz_379; - wire _zz_380; - wire _zz_381; - wire [6:0] _zz_382; - wire [4:0] _zz_383; - wire _zz_384; - wire [4:0] _zz_385; - wire [0:0] _zz_386; - wire [7:0] _zz_387; - wire _zz_388; - wire [0:0] _zz_389; - wire [0:0] _zz_390; - wire [31:0] _zz_391; - wire [31:0] _zz_392; - wire _zz_393; - wire [0:0] _zz_394; - wire [0:0] _zz_395; - wire _zz_396; - wire [0:0] _zz_397; - wire [24:0] _zz_398; - wire [31:0] _zz_399; - wire _zz_400; - wire _zz_401; - wire [0:0] _zz_402; - wire [0:0] _zz_403; - wire [0:0] _zz_404; - wire [0:0] _zz_405; - wire _zz_406; - wire [0:0] _zz_407; - wire [20:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire _zz_411; - wire _zz_412; - wire [0:0] _zz_413; - wire [1:0] _zz_414; - wire [0:0] _zz_415; - wire [0:0] _zz_416; - wire _zz_417; - wire [0:0] _zz_418; - wire [17:0] _zz_419; - wire [31:0] _zz_420; - wire [31:0] _zz_421; - wire [31:0] _zz_422; - wire [31:0] _zz_423; - wire [31:0] _zz_424; - wire [31:0] _zz_425; - wire [31:0] _zz_426; - wire [31:0] _zz_427; - wire _zz_428; - wire [1:0] _zz_429; - wire [1:0] _zz_430; - wire _zz_431; - wire [0:0] _zz_432; - wire [14:0] _zz_433; - wire [31:0] _zz_434; - wire [31:0] _zz_435; - wire [31:0] _zz_436; - wire [31:0] _zz_437; - wire [31:0] _zz_438; - wire [31:0] _zz_439; - wire [0:0] _zz_440; - wire [0:0] _zz_441; - wire [4:0] _zz_442; - wire [4:0] _zz_443; - wire _zz_444; - wire [0:0] _zz_445; - wire [11:0] _zz_446; - wire [31:0] _zz_447; - wire [31:0] _zz_448; - wire [31:0] _zz_449; - wire [31:0] _zz_450; - wire _zz_451; - wire [0:0] _zz_452; - wire [1:0] _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [0:0] _zz_456; - wire [3:0] _zz_457; - wire [4:0] _zz_458; - wire [4:0] _zz_459; - wire _zz_460; - wire [0:0] _zz_461; - wire [8:0] _zz_462; - wire [31:0] _zz_463; - wire [31:0] _zz_464; - wire [31:0] _zz_465; - wire _zz_466; - wire _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [0:0] _zz_470; - wire [1:0] _zz_471; - wire [0:0] _zz_472; - wire [2:0] _zz_473; - wire [0:0] _zz_474; - wire [4:0] _zz_475; - wire [1:0] _zz_476; - wire [1:0] _zz_477; - wire _zz_478; - wire [0:0] _zz_479; - wire [6:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire _zz_485; - wire _zz_486; - wire [31:0] _zz_487; - wire [31:0] _zz_488; - wire _zz_489; - wire [0:0] _zz_490; - wire [0:0] _zz_491; - wire _zz_492; - wire [0:0] _zz_493; - wire [2:0] _zz_494; - wire _zz_495; - wire [0:0] _zz_496; - wire [0:0] _zz_497; - wire [0:0] _zz_498; - wire [0:0] _zz_499; - wire _zz_500; - wire [0:0] _zz_501; - wire [4:0] _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire [31:0] _zz_505; - wire [31:0] _zz_506; - wire [31:0] _zz_507; - wire [31:0] _zz_508; - wire [31:0] _zz_509; - wire [31:0] _zz_510; - wire [31:0] _zz_511; - wire [31:0] _zz_512; - wire _zz_513; - wire [0:0] _zz_514; - wire [0:0] _zz_515; - wire [31:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire [31:0] _zz_520; - wire _zz_521; - wire [3:0] _zz_522; - wire [3:0] _zz_523; - wire _zz_524; - wire [0:0] _zz_525; - wire [2:0] _zz_526; - wire [31:0] _zz_527; - wire [31:0] _zz_528; - wire [31:0] _zz_529; - wire [31:0] _zz_530; - wire [31:0] _zz_531; - wire [31:0] _zz_532; - wire _zz_533; - wire [0:0] _zz_534; - wire [1:0] _zz_535; - wire _zz_536; - wire [2:0] _zz_537; - wire [2:0] _zz_538; - wire _zz_539; - wire [0:0] _zz_540; - wire [0:0] _zz_541; - wire [31:0] _zz_542; - wire [31:0] _zz_543; - wire [31:0] _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire _zz_549; - wire _zz_550; - wire _zz_551; - wire [0:0] _zz_552; - wire [0:0] _zz_553; - wire _zz_554; - wire _zz_555; - wire _zz_556; - wire _zz_557; - wire [31:0] _zz_558; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_FORMAL_PC_NEXT; + wire [2:0] _zz_decode_FORMAL_PC_NEXT_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [15:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [9:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [3:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [31:0] _zz_IBusCachedPlugin_decodePc_pcPlus; + wire [2:0] _zz_IBusCachedPlugin_decodePc_pcPlus_1; + wire [31:0] _zz_IBusCachedPlugin_decompressor_decompressed_27; + wire _zz_IBusCachedPlugin_decompressor_decompressed_28; + wire _zz_IBusCachedPlugin_decompressor_decompressed_29; + wire [6:0] _zz_IBusCachedPlugin_decompressor_decompressed_30; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_31; + wire _zz_IBusCachedPlugin_decompressor_decompressed_32; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_33; + wire [11:0] _zz_IBusCachedPlugin_decompressor_decompressed_34; + wire [11:0] _zz_IBusCachedPlugin_decompressor_decompressed_35; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire [0:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire [7:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [0:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_7; + wire [0:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_8; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspRf; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_1; + wire _zz__zz_decode_IS_RS2_SIGNED_2; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_3; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_4; + wire _zz__zz_decode_IS_RS2_SIGNED_5; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_6; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_7; + wire _zz__zz_decode_IS_RS2_SIGNED_8; + wire _zz__zz_decode_IS_RS2_SIGNED_9; + wire [25:0] _zz__zz_decode_IS_RS2_SIGNED_10; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_11; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_12; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_13; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_14; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_15; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_16; + wire _zz__zz_decode_IS_RS2_SIGNED_17; + wire _zz__zz_decode_IS_RS2_SIGNED_18; + wire _zz__zz_decode_IS_RS2_SIGNED_19; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_20; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_21; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_22; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_23; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_24; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_25; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_26; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_27; + wire [21:0] _zz__zz_decode_IS_RS2_SIGNED_28; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_29; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_30; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_31; + wire _zz__zz_decode_IS_RS2_SIGNED_32; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_33; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_34; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_35; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_36; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_37; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_38; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_39; + wire [18:0] _zz__zz_decode_IS_RS2_SIGNED_40; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_41; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_42; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_43; + wire _zz__zz_decode_IS_RS2_SIGNED_44; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_45; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_46; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_47; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_48; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_49; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_50; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_51; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_52; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_53; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_54; + wire [15:0] _zz__zz_decode_IS_RS2_SIGNED_55; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_56; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_57; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_58; + wire _zz__zz_decode_IS_RS2_SIGNED_59; + wire _zz__zz_decode_IS_RS2_SIGNED_60; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_61; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_62; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_63; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_64; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_65; + wire _zz__zz_decode_IS_RS2_SIGNED_66; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_67; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_68; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_69; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_70; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_71; + wire _zz__zz_decode_IS_RS2_SIGNED_72; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_73; + wire _zz__zz_decode_IS_RS2_SIGNED_74; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_75; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_76; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_77; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_78; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_79; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_80; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_81; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_82; + wire [12:0] _zz__zz_decode_IS_RS2_SIGNED_83; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_84; + wire _zz__zz_decode_IS_RS2_SIGNED_85; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_86; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_87; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_88; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_89; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_90; + wire _zz__zz_decode_IS_RS2_SIGNED_91; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_92; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_93; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_94; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_95; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_96; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_97; + wire _zz__zz_decode_IS_RS2_SIGNED_98; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_99; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_100; + wire _zz__zz_decode_IS_RS2_SIGNED_101; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_102; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_103; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_104; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_105; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_106; + wire _zz__zz_decode_IS_RS2_SIGNED_107; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_108; + wire _zz__zz_decode_IS_RS2_SIGNED_109; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_110; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_111; + wire [6:0] _zz__zz_decode_IS_RS2_SIGNED_112; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_113; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_114; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_115; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_116; + wire _zz__zz_decode_IS_RS2_SIGNED_117; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_118; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_119; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_120; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_121; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_122; + wire _zz__zz_decode_IS_RS2_SIGNED_123; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_124; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_125; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_126; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_127; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_128; + wire [6:0] _zz__zz_decode_IS_RS2_SIGNED_129; + wire [9:0] _zz__zz_decode_IS_RS2_SIGNED_130; + wire _zz__zz_decode_IS_RS2_SIGNED_131; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_132; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_133; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_134; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_135; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_136; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_137; + wire _zz__zz_decode_IS_RS2_SIGNED_138; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_139; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_140; + wire [7:0] _zz__zz_decode_IS_RS2_SIGNED_141; + wire _zz__zz_decode_IS_RS2_SIGNED_142; + wire _zz__zz_decode_IS_RS2_SIGNED_143; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_144; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_145; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_146; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_147; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_148; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_149; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_150; + wire _zz__zz_decode_IS_RS2_SIGNED_151; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_152; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_153; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_154; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_155; + wire _zz__zz_decode_IS_RS2_SIGNED_156; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_157; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_158; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_159; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_160; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_161; + wire _zz__zz_decode_IS_RS2_SIGNED_162; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_163; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_164; + wire _zz__zz_decode_IS_RS2_SIGNED_165; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_166; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_167; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_168; + wire _zz__zz_decode_IS_RS2_SIGNED_169; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_170; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_171; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_172; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_173; + wire _zz__zz_decode_IS_RS2_SIGNED_174; + wire _zz__zz_decode_IS_RS2_SIGNED_175; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_176; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_177; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_178; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_179; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_180; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_181; + wire _zz__zz_decode_IS_RS2_SIGNED_182; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_183; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_184; + wire _zz__zz_decode_IS_RS2_SIGNED_185; + wire _zz__zz_decode_IS_RS2_SIGNED_186; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -480,8 +446,8 @@ module VexRiscv ( wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; @@ -492,46 +458,47 @@ module VexRiscv ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_LRSC; wire memory_MEMORY_WR; wire decode_MEMORY_WR; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; @@ -551,23 +518,23 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; wire execute_PREDICTION_HAD_BRANCHED2; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_31; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -577,50 +544,52 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_32; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_35; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_36; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; wire execute_IS_RVC; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; - wire [31:0] _zz_40; - wire _zz_41; - reg _zz_42; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_43; - wire `BranchCtrlEnum_defaultEncoding_type _zz_44; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; - wire `Src2CtrlEnum_defaultEncoding_type _zz_47; - wire `AluCtrlEnum_defaultEncoding_type _zz_48; - wire `Src1CtrlEnum_defaultEncoding_type _zz_49; - reg [31:0] _zz_50; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_LRSC; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_ENABLE; + wire execute_MEMORY_LRSC; wire execute_MEMORY_FORCE_CONSTISTENCY; wire execute_MEMORY_MANAGMENT; (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; @@ -628,16 +597,18 @@ module VexRiscv ( wire [31:0] execute_SRC_ADD; wire execute_MEMORY_ENABLE; wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_LRSC; + reg _zz_decode_MEMORY_FORCE_CONSTISTENCY; wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_4; reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; - reg [31:0] _zz_52; - reg [31:0] _zz_53; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] decode_INSTRUCTION; wire decode_IS_RVC; @@ -726,7 +697,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -757,6 +728,11 @@ module VexRiscv ( wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -774,32 +750,40 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_54; - wire [3:0] _zz_55; - wire _zz_56; - wire _zz_57; - wire _zz_58; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; reg [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_decodePc_flushed; reg [31:0] IBusCachedPlugin_decodePc_pcReg /* verilator public */ ; wire [31:0] IBusCachedPlugin_decodePc_pcPlus; wire IBusCachedPlugin_decodePc_injectedDecode; + wire when_Fetcher_l180; + wire when_Fetcher_l192; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -815,12 +799,12 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire _zz_59; - wire _zz_60; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_61; - wire _zz_62; - reg _zz_63; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -849,59 +833,74 @@ module VexRiscv ( reg IBusCachedPlugin_decompressor_throw2BytesReg; wire IBusCachedPlugin_decompressor_throw2Bytes; wire IBusCachedPlugin_decompressor_unaligned; + reg IBusCachedPlugin_decompressor_bufferValidLatch; + reg IBusCachedPlugin_decompressor_throw2BytesLatch; + wire IBusCachedPlugin_decompressor_bufferValidPatched; + wire IBusCachedPlugin_decompressor_throw2BytesPatched; wire [31:0] IBusCachedPlugin_decompressor_raw; wire IBusCachedPlugin_decompressor_isRvc; - wire [15:0] _zz_64; + wire [15:0] _zz_IBusCachedPlugin_decompressor_decompressed; reg [31:0] IBusCachedPlugin_decompressor_decompressed; - wire [4:0] _zz_65; - wire [4:0] _zz_66; - wire [11:0] _zz_67; - wire _zz_68; - reg [11:0] _zz_69; - wire _zz_70; - reg [9:0] _zz_71; - wire [20:0] _zz_72; - wire _zz_73; - reg [14:0] _zz_74; - wire _zz_75; - reg [2:0] _zz_76; - wire _zz_77; - reg [9:0] _zz_78; - wire [20:0] _zz_79; - wire _zz_80; - reg [4:0] _zz_81; - wire [12:0] _zz_82; - wire [4:0] _zz_83; - wire [4:0] _zz_84; - wire [4:0] _zz_85; - wire _zz_86; - reg [2:0] _zz_87; - reg [2:0] _zz_88; - wire _zz_89; - reg [6:0] _zz_90; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_1; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_2; + wire [11:0] _zz_IBusCachedPlugin_decompressor_decompressed_3; + wire _zz_IBusCachedPlugin_decompressor_decompressed_4; + reg [11:0] _zz_IBusCachedPlugin_decompressor_decompressed_5; + wire _zz_IBusCachedPlugin_decompressor_decompressed_6; + reg [9:0] _zz_IBusCachedPlugin_decompressor_decompressed_7; + wire [20:0] _zz_IBusCachedPlugin_decompressor_decompressed_8; + wire _zz_IBusCachedPlugin_decompressor_decompressed_9; + reg [14:0] _zz_IBusCachedPlugin_decompressor_decompressed_10; + wire _zz_IBusCachedPlugin_decompressor_decompressed_11; + reg [2:0] _zz_IBusCachedPlugin_decompressor_decompressed_12; + wire _zz_IBusCachedPlugin_decompressor_decompressed_13; + reg [9:0] _zz_IBusCachedPlugin_decompressor_decompressed_14; + wire [20:0] _zz_IBusCachedPlugin_decompressor_decompressed_15; + wire _zz_IBusCachedPlugin_decompressor_decompressed_16; + reg [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_17; + wire [12:0] _zz_IBusCachedPlugin_decompressor_decompressed_18; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_19; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_20; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_21; + wire [4:0] switch_Misc_l44; + wire _zz_IBusCachedPlugin_decompressor_decompressed_22; + wire [1:0] switch_Misc_l200; + wire [1:0] switch_Misc_l200_1; + reg [2:0] _zz_IBusCachedPlugin_decompressor_decompressed_23; + reg [2:0] _zz_IBusCachedPlugin_decompressor_decompressed_24; + wire _zz_IBusCachedPlugin_decompressor_decompressed_25; + reg [6:0] _zz_IBusCachedPlugin_decompressor_decompressed_26; + wire IBusCachedPlugin_decompressor_output_fire; wire IBusCachedPlugin_decompressor_bufferFill; + wire when_Fetcher_l283; + wire when_Fetcher_l286; + wire when_Fetcher_l291; wire IBusCachedPlugin_injector_decodeInput_valid; wire IBusCachedPlugin_injector_decodeInput_ready; wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; - reg _zz_91; - reg [31:0] _zz_92; - reg _zz_93; - reg [31:0] _zz_94; - reg _zz_95; + reg _zz_IBusCachedPlugin_injector_decodeInput_valid; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; - wire _zz_96; - reg [18:0] _zz_97; - wire _zz_98; - reg [10:0] _zz_99; - wire _zz_100; - reg [18:0] _zz_101; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -909,30 +908,35 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_102; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -940,38 +944,58 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_103; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; + wire when_DBusCachedPlugin_l311; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_104; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_105; - reg [31:0] _zz_106; - wire _zz_107; - reg [31:0] _zz_108; + reg [31:0] writeBack_DBusCachedPlugin_rspRf; + wire when_DBusCachedPlugin_l474; + wire [1:0] switch_Misc_l200_2; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [31:0] _zz_109; - wire _zz_110; - wire _zz_111; - wire _zz_112; - wire _zz_113; - wire `Src1CtrlEnum_defaultEncoding_type _zz_114; - wire `AluCtrlEnum_defaultEncoding_type _zz_115; - wire `Src2CtrlEnum_defaultEncoding_type _zz_116; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_117; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_118; - wire `BranchCtrlEnum_defaultEncoding_type _zz_119; - wire `EnvCtrlEnum_defaultEncoding_type _zz_120; + wire when_DBusCachedPlugin_l484; + wire [32:0] _zz_decode_IS_RS2_SIGNED; + wire _zz_decode_IS_RS2_SIGNED_1; + wire _zz_decode_IS_RS2_SIGNED_2; + wire _zz_decode_IS_RS2_SIGNED_3; + wire _zz_decode_IS_RS2_SIGNED_4; + wire _zz_decode_IS_RS2_SIGNED_5; + wire _zz_decode_IS_RS2_SIGNED_6; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -979,45 +1003,63 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_121; + reg _zz_2; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_122; - reg [31:0] _zz_123; - wire _zz_124; - reg [19:0] _zz_125; - wire _zz_126; - reg [19:0] _zz_127; - reg [31:0] _zz_128; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_129; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_130; - reg _zz_131; - reg _zz_132; - reg _zz_133; - reg [4:0] _zz_134; - reg [31:0] _zz_135; - wire _zz_136; - wire _zz_137; - wire _zz_138; - wire _zz_139; - wire _zz_140; - wire _zz_141; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_142; - reg _zz_143; - reg _zz_144; + wire [2:0] switch_Misc_l200_3; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_145; - reg [19:0] _zz_146; - wire _zz_147; - reg [10:0] _zz_148; - wire _zz_149; - reg [18:0] _zz_150; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1039,9 +1081,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_151; - wire _zz_152; - wire _zz_153; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1054,40 +1096,67 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_154; - wire _zz_155; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_4; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1095,6 +1164,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1107,209 +1178,318 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_156; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_157; - wire _zz_158; - wire _zz_159; - reg [32:0] _zz_160; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_161; - wire [31:0] _zz_162; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg decode_to_execute_IS_RVC; + wire when_Pipeline_l124_7; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_10; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_12; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_13; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_15; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_16; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_17; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_18; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_22; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_24; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_25; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_26; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_27; + reg decode_to_execute_MEMORY_LRSC; + wire when_Pipeline_l124_28; + reg execute_to_memory_MEMORY_LRSC; + wire when_Pipeline_l124_29; + reg memory_to_writeBack_MEMORY_LRSC; + wire when_Pipeline_l124_30; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_31; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_33; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_34; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_35; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_37; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_38; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_39; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_40; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_41; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_42; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_43; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_44; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_45; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_46; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_47; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_48; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_49; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_50; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_51; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_52; reg decode_to_execute_CSR_READ_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_53; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_54; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_55; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_56; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_57; reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_58; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_59; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_60; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_61; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_62; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_63; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_64; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_65; reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [2:0] _zz_186; - reg _zz_187; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_188; - wire _zz_189; - wire _zz_190; - wire _zz_191; - wire _zz_192; - wire _zz_193; - reg _zz_194; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; - reg [39:0] _zz_17_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; - reg [23:0] _zz_20_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; - reg [63:0] _zz_23_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; - reg [95:0] _zz_26_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_30_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_33_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_34_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_36_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_37_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_38_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_39_string; - reg [39:0] _zz_43_string; - reg [31:0] _zz_44_string; - reg [71:0] _zz_45_string; - reg [39:0] _zz_46_string; - reg [23:0] _zz_47_string; - reg [63:0] _zz_48_string; - reg [95:0] _zz_49_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_51_string; - reg [95:0] _zz_114_string; - reg [63:0] _zz_115_string; - reg [23:0] _zz_116_string; - reg [39:0] _zz_117_string; - reg [71:0] _zz_118_string; - reg [31:0] _zz_119_string; - reg [39:0] _zz_120_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1324,1164 +1504,1153 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_227 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_228 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_229 = 1'b1; - assign _zz_230 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_231 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_232 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_233 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_234 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_235 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_236 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_237 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_238 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_239 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_240 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_241 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_242 = (IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); - assign _zz_243 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_244 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_245 = (1'b0 || (! 1'b1)); - assign _zz_246 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_247 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_248 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_249 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_250 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_251 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_252 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_253 = execute_INSTRUCTION[13 : 12]; - assign _zz_254 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_255 = (! memory_arbitration_isStuck); - assign _zz_256 = (iBus_cmd_valid || (_zz_186 != 3'b000)); - assign _zz_257 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); - assign _zz_258 = (_zz_223 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_259 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_260 = ((_zz_151 && 1'b1) && (! 1'b0)); - assign _zz_261 = ((_zz_152 && 1'b1) && (! 1'b0)); - assign _zz_262 = ((_zz_153 && 1'b1) && (! 1'b0)); - assign _zz_263 = {_zz_64[1 : 0],_zz_64[15 : 13]}; - assign _zz_264 = _zz_64[6 : 5]; - assign _zz_265 = _zz_64[11 : 10]; - assign _zz_266 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_267 = execute_INSTRUCTION[13]; - assign _zz_268 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_269 = ($signed(_zz_270) + $signed(_zz_275)); - assign _zz_270 = ($signed(_zz_271) + $signed(_zz_273)); - assign _zz_271 = 52'h0; - assign _zz_272 = {1'b0,memory_MUL_LL}; - assign _zz_273 = {{19{_zz_272[32]}}, _zz_272}; - assign _zz_274 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_275 = {{2{_zz_274[49]}}, _zz_274}; - assign _zz_276 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_277 = {{2{_zz_276[49]}}, _zz_276}; - assign _zz_278 = ($signed(_zz_280) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_279 = _zz_278[31 : 0]; - assign _zz_280 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_281 = _zz_109[31 : 31]; - assign _zz_282 = _zz_109[30 : 30]; - assign _zz_283 = _zz_109[29 : 29]; - assign _zz_284 = _zz_109[28 : 28]; - assign _zz_285 = _zz_109[25 : 25]; - assign _zz_286 = _zz_109[17 : 17]; - assign _zz_287 = _zz_109[16 : 16]; - assign _zz_288 = _zz_109[13 : 13]; - assign _zz_289 = _zz_109[12 : 12]; - assign _zz_290 = _zz_109[11 : 11]; - assign _zz_291 = (decode_IS_RVC ? 3'b010 : 3'b100); - assign _zz_292 = {29'd0, _zz_291}; - assign _zz_293 = _zz_109[15 : 15]; - assign _zz_294 = _zz_109[5 : 5]; - assign _zz_295 = _zz_109[3 : 3]; - assign _zz_296 = _zz_109[20 : 20]; - assign _zz_297 = _zz_109[10 : 10]; - assign _zz_298 = _zz_109[4 : 4]; - assign _zz_299 = _zz_109[0 : 0]; - assign _zz_300 = (_zz_54 - 4'b0001); - assign _zz_301 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_302 = {29'd0, _zz_301}; - assign _zz_303 = (decode_IS_RVC ? 3'b010 : 3'b100); - assign _zz_304 = {29'd0, _zz_303}; - assign _zz_305 = {{_zz_74,_zz_64[6 : 2]},12'h0}; - assign _zz_306 = {{{4'b0000,_zz_64[8 : 7]},_zz_64[12 : 9]},2'b00}; - assign _zz_307 = {{{4'b0000,_zz_64[8 : 7]},_zz_64[12 : 9]},2'b00}; - assign _zz_308 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_309 = {{_zz_97,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_310 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_311 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_312 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_313 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_314 = execute_SRC_LESS; - assign _zz_315 = (execute_IS_RVC ? 3'b010 : 3'b100); - assign _zz_316 = execute_INSTRUCTION[19 : 15]; - assign _zz_317 = execute_INSTRUCTION[31 : 20]; - assign _zz_318 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_319 = ($signed(_zz_320) + $signed(_zz_323)); - assign _zz_320 = ($signed(_zz_321) + $signed(_zz_322)); - assign _zz_321 = execute_SRC1; - assign _zz_322 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_323 = (execute_SRC_USE_SUB_LESS ? _zz_324 : _zz_325); - assign _zz_324 = 32'h00000001; - assign _zz_325 = 32'h0; - assign _zz_326 = execute_INSTRUCTION[31 : 20]; - assign _zz_327 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_329 = (execute_IS_RVC ? 3'b010 : 3'b100); - assign _zz_330 = (_zz_154 & (~ _zz_331)); - assign _zz_331 = (_zz_154 - 2'b01); - assign _zz_332 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_333 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_334 = writeBack_MUL_LOW[31 : 0]; - assign _zz_335 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_336 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_337 = {5'd0, _zz_336}; - assign _zz_338 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_339 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_340 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_341 = {_zz_156,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_342 = _zz_343; - assign _zz_343 = _zz_344; - assign _zz_344 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_157) : _zz_157)} + _zz_346); - assign _zz_345 = memory_DivPlugin_div_needRevert; - assign _zz_346 = {32'd0, _zz_345}; - assign _zz_347 = _zz_159; - assign _zz_348 = {32'd0, _zz_347}; - assign _zz_349 = _zz_158; - assign _zz_350 = {31'd0, _zz_349}; - assign _zz_351 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_352 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_353 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_354 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_355 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_356 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_357 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_358 = (iBus_cmd_payload_address >>> 5); - assign _zz_359 = 1'b1; - assign _zz_360 = 1'b1; - assign _zz_361 = {_zz_58,_zz_57}; - assign _zz_362 = 32'h0000107f; - assign _zz_363 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_364 = 32'h00002073; - assign _zz_365 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_366 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_367 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_368) == 32'h00000003),{(_zz_369 == _zz_370),{_zz_371,{_zz_372,_zz_373}}}}}}; - assign _zz_368 = 32'h0000505f; - assign _zz_369 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_370 = 32'h00000063; - assign _zz_371 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_372 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_373 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_374) == 32'h00001013),{(_zz_375 == _zz_376),{_zz_377,{_zz_378,_zz_379}}}}}}; - assign _zz_374 = 32'hfc00307f; - assign _zz_375 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_376 = 32'h00005033; - assign _zz_377 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_378 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_379 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; - assign _zz_380 = (_zz_64[11 : 10] == 2'b01); - assign _zz_381 = ((_zz_64[11 : 10] == 2'b11) && (_zz_64[6 : 5] == 2'b00)); - assign _zz_382 = 7'h0; - assign _zz_383 = _zz_64[6 : 2]; - assign _zz_384 = _zz_64[12]; - assign _zz_385 = _zz_64[11 : 7]; - assign _zz_386 = decode_INSTRUCTION[31]; - assign _zz_387 = decode_INSTRUCTION[19 : 12]; - assign _zz_388 = decode_INSTRUCTION[20]; - assign _zz_389 = decode_INSTRUCTION[31]; - assign _zz_390 = decode_INSTRUCTION[7]; - assign _zz_391 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_392 = 32'h02004020; - assign _zz_393 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_394 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); - assign _zz_395 = 1'b0; - assign _zz_396 = (((decode_INSTRUCTION & _zz_399) == 32'h00000050) != 1'b0); - assign _zz_397 = ({_zz_400,_zz_401} != 2'b00); - assign _zz_398 = {({_zz_402,_zz_403} != 2'b00),{(_zz_404 != _zz_405),{_zz_406,{_zz_407,_zz_408}}}}; - assign _zz_399 = 32'h00403050; - assign _zz_400 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_401 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_402 = _zz_112; - assign _zz_403 = ((decode_INSTRUCTION & _zz_409) == 32'h00000004); - assign _zz_404 = ((decode_INSTRUCTION & _zz_410) == 32'h00000040); - assign _zz_405 = 1'b0; - assign _zz_406 = ({_zz_411,_zz_412} != 2'b00); - assign _zz_407 = ({_zz_413,_zz_414} != 3'b000); - assign _zz_408 = {(_zz_415 != _zz_416),{_zz_417,{_zz_418,_zz_419}}}; - assign _zz_409 = 32'h0000001c; - assign _zz_410 = 32'h00000058; - assign _zz_411 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_412 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_413 = ((decode_INSTRUCTION & _zz_420) == 32'h40001010); - assign _zz_414 = {(_zz_421 == _zz_422),(_zz_423 == _zz_424)}; - assign _zz_415 = ((decode_INSTRUCTION & _zz_425) == 32'h00000024); - assign _zz_416 = 1'b0; - assign _zz_417 = ((_zz_426 == _zz_427) != 1'b0); - assign _zz_418 = (_zz_428 != 1'b0); - assign _zz_419 = {(_zz_429 != _zz_430),{_zz_431,{_zz_432,_zz_433}}}; - assign _zz_420 = 32'h40003054; - assign _zz_421 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_422 = 32'h00001010; - assign _zz_423 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_424 = 32'h00001010; - assign _zz_425 = 32'h00000064; - assign _zz_426 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_427 = 32'h00001000; - assign _zz_428 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_429 = {(_zz_434 == _zz_435),(_zz_436 == _zz_437)}; - assign _zz_430 = 2'b00; - assign _zz_431 = ((_zz_438 == _zz_439) != 1'b0); - assign _zz_432 = ({_zz_440,_zz_441} != 2'b00); - assign _zz_433 = {(_zz_442 != _zz_443),{_zz_444,{_zz_445,_zz_446}}}; - assign _zz_434 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_435 = 32'h00002000; - assign _zz_436 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_437 = 32'h00001000; - assign _zz_438 = (decode_INSTRUCTION & 32'h00004048); - assign _zz_439 = 32'h00004008; - assign _zz_440 = ((decode_INSTRUCTION & _zz_447) == 32'h00000020); - assign _zz_441 = ((decode_INSTRUCTION & _zz_448) == 32'h00000020); - assign _zz_442 = {(_zz_449 == _zz_450),{_zz_451,{_zz_452,_zz_453}}}; - assign _zz_443 = 5'h0; - assign _zz_444 = ((_zz_454 == _zz_455) != 1'b0); - assign _zz_445 = ({_zz_456,_zz_457} != 5'h0); - assign _zz_446 = {(_zz_458 != _zz_459),{_zz_460,{_zz_461,_zz_462}}}; - assign _zz_447 = 32'h00000034; - assign _zz_448 = 32'h00000064; - assign _zz_449 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_450 = 32'h00002040; - assign _zz_451 = ((decode_INSTRUCTION & _zz_463) == 32'h00001040); - assign _zz_452 = (_zz_464 == _zz_465); - assign _zz_453 = {_zz_466,_zz_467}; - assign _zz_454 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_455 = 32'h00000020; - assign _zz_456 = (_zz_468 == _zz_469); - assign _zz_457 = {_zz_111,{_zz_470,_zz_471}}; - assign _zz_458 = {_zz_111,{_zz_472,_zz_473}}; - assign _zz_459 = 5'h0; - assign _zz_460 = ({_zz_474,_zz_475} != 6'h0); - assign _zz_461 = (_zz_476 != _zz_477); - assign _zz_462 = {_zz_478,{_zz_479,_zz_480}}; - assign _zz_463 = 32'h00001040; - assign _zz_464 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_465 = 32'h00000040; - assign _zz_466 = ((decode_INSTRUCTION & _zz_481) == 32'h00000040); - assign _zz_467 = ((decode_INSTRUCTION & _zz_482) == 32'h0); - assign _zz_468 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_469 = 32'h00000040; - assign _zz_470 = (_zz_483 == _zz_484); - assign _zz_471 = {_zz_485,_zz_486}; - assign _zz_472 = (_zz_487 == _zz_488); - assign _zz_473 = {_zz_489,{_zz_490,_zz_491}}; - assign _zz_474 = _zz_112; - assign _zz_475 = {_zz_492,{_zz_493,_zz_494}}; - assign _zz_476 = {_zz_111,_zz_495}; - assign _zz_477 = 2'b00; - assign _zz_478 = ({_zz_496,_zz_497} != 2'b00); - assign _zz_479 = (_zz_498 != _zz_499); - assign _zz_480 = {_zz_500,{_zz_501,_zz_502}}; - assign _zz_481 = 32'h00400040; - assign _zz_482 = 32'h00000038; - assign _zz_483 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_484 = 32'h00004020; - assign _zz_485 = ((decode_INSTRUCTION & _zz_503) == 32'h00000010); - assign _zz_486 = ((decode_INSTRUCTION & _zz_504) == 32'h00000020); - assign _zz_487 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_488 = 32'h00002010; - assign _zz_489 = ((decode_INSTRUCTION & _zz_505) == 32'h00000010); - assign _zz_490 = (_zz_506 == _zz_507); - assign _zz_491 = (_zz_508 == _zz_509); - assign _zz_492 = ((decode_INSTRUCTION & _zz_510) == 32'h00001010); - assign _zz_493 = (_zz_511 == _zz_512); - assign _zz_494 = {_zz_513,{_zz_514,_zz_515}}; - assign _zz_495 = ((decode_INSTRUCTION & _zz_516) == 32'h00000020); - assign _zz_496 = _zz_111; - assign _zz_497 = (_zz_517 == _zz_518); - assign _zz_498 = (_zz_519 == _zz_520); - assign _zz_499 = 1'b0; - assign _zz_500 = (_zz_521 != 1'b0); - assign _zz_501 = (_zz_522 != _zz_523); - assign _zz_502 = {_zz_524,{_zz_525,_zz_526}}; - assign _zz_503 = 32'h00000030; - assign _zz_504 = 32'h02000020; - assign _zz_505 = 32'h00001030; - assign _zz_506 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_507 = 32'h00002020; - assign _zz_508 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_509 = 32'h00000020; - assign _zz_510 = 32'h00001010; - assign _zz_511 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_512 = 32'h00002010; - assign _zz_513 = ((decode_INSTRUCTION & _zz_527) == 32'h00000010); - assign _zz_514 = (_zz_528 == _zz_529); - assign _zz_515 = (_zz_530 == _zz_531); - assign _zz_516 = 32'h00000070; - assign _zz_517 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_518 = 32'h0; - assign _zz_519 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_520 = 32'h00004010; - assign _zz_521 = ((decode_INSTRUCTION & _zz_532) == 32'h00002010); - assign _zz_522 = {_zz_533,{_zz_534,_zz_535}}; - assign _zz_523 = 4'b0000; - assign _zz_524 = (_zz_536 != 1'b0); - assign _zz_525 = (_zz_537 != _zz_538); - assign _zz_526 = {_zz_539,{_zz_540,_zz_541}}; - assign _zz_527 = 32'h00000050; - assign _zz_528 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_529 = 32'h00000004; - assign _zz_530 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_531 = 32'h0; - assign _zz_532 = 32'h00006014; - assign _zz_533 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_534 = ((decode_INSTRUCTION & _zz_542) == 32'h0); - assign _zz_535 = {(_zz_543 == _zz_544),(_zz_545 == _zz_546)}; - assign _zz_536 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_537 = {(_zz_547 == _zz_548),{_zz_549,_zz_550}}; - assign _zz_538 = 3'b000; - assign _zz_539 = ({_zz_551,_zz_110} != 2'b00); - assign _zz_540 = ({_zz_552,_zz_553} != 2'b00); - assign _zz_541 = (_zz_554 != 1'b0); - assign _zz_542 = 32'h00000018; - assign _zz_543 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_544 = 32'h00002000; - assign _zz_545 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_546 = 32'h00001000; - assign _zz_547 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_548 = 32'h00000040; - assign _zz_549 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_550 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_551 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_552 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_553 = _zz_110; - assign _zz_554 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); - assign _zz_555 = execute_INSTRUCTION[31]; - assign _zz_556 = execute_INSTRUCTION[31]; - assign _zz_557 = execute_INSTRUCTION[7]; - assign _zz_558 = 32'h0; - always @ (posedge clk) begin - if(_zz_359) begin - _zz_224 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_360) begin - _zz_225 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_42) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_decode_FORMAL_PC_NEXT_1 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_decode_FORMAL_PC_NEXT = {29'd0, _zz_decode_FORMAL_PC_NEXT_1}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz_IBusCachedPlugin_decodePc_pcPlus_1 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_IBusCachedPlugin_decodePc_pcPlus = {29'd0, _zz_IBusCachedPlugin_decodePc_pcPlus_1}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_27 = {{_zz_IBusCachedPlugin_decompressor_decompressed_10,_zz_IBusCachedPlugin_decompressor_decompressed[6 : 2]},12'h0}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_34 = {{{4'b0000,_zz_IBusCachedPlugin_decompressor_decompressed[8 : 7]},_zz_IBusCachedPlugin_decompressor_decompressed[12 : 9]},2'b00}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_35 = {{{4'b0000,_zz_IBusCachedPlugin_decompressor_decompressed[8 : 7]},_zz_IBusCachedPlugin_decompressor_decompressed[12 : 9]},2'b00}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_writeBack_DBusCachedPlugin_rspRf = (! dataCache_1_io_cpu_writeBack_exclusiveOk); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hf800707f) == 32'h1800202f),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_28 = (_zz_IBusCachedPlugin_decompressor_decompressed[11 : 10] == 2'b01); + assign _zz_IBusCachedPlugin_decompressor_decompressed_29 = ((_zz_IBusCachedPlugin_decompressor_decompressed[11 : 10] == 2'b11) && (_zz_IBusCachedPlugin_decompressor_decompressed[6 : 5] == 2'b00)); + assign _zz_IBusCachedPlugin_decompressor_decompressed_30 = 7'h0; + assign _zz_IBusCachedPlugin_decompressor_decompressed_31 = _zz_IBusCachedPlugin_decompressor_decompressed[6 : 2]; + assign _zz_IBusCachedPlugin_decompressor_decompressed_32 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + assign _zz_IBusCachedPlugin_decompressor_decompressed_33 = _zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[19 : 12]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[20]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_7 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_8 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_IS_RS2_SIGNED = (decode_INSTRUCTION & 32'h02004064); + assign _zz__zz_decode_IS_RS2_SIGNED_1 = 32'h02004020; + assign _zz__zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz__zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_4 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_5 = (((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_6) == 32'h00000050) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_7 = ({_zz__zz_decode_IS_RS2_SIGNED_8,_zz__zz_decode_IS_RS2_SIGNED_9} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_10 = {({_zz__zz_decode_IS_RS2_SIGNED_11,_zz__zz_decode_IS_RS2_SIGNED_12} != 2'b00),{(_zz__zz_decode_IS_RS2_SIGNED_14 != _zz__zz_decode_IS_RS2_SIGNED_16),{_zz__zz_decode_IS_RS2_SIGNED_17,{_zz__zz_decode_IS_RS2_SIGNED_20,_zz__zz_decode_IS_RS2_SIGNED_28}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_6 = 32'h00403050; + assign _zz__zz_decode_IS_RS2_SIGNED_8 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz__zz_decode_IS_RS2_SIGNED_9 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz__zz_decode_IS_RS2_SIGNED_11 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_12 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_13) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_14 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_15) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_16 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_17 = ({_zz__zz_decode_IS_RS2_SIGNED_18,_zz__zz_decode_IS_RS2_SIGNED_19} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_20 = ({_zz__zz_decode_IS_RS2_SIGNED_21,_zz__zz_decode_IS_RS2_SIGNED_23} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_28 = {(_zz__zz_decode_IS_RS2_SIGNED_29 != _zz__zz_decode_IS_RS2_SIGNED_31),{_zz__zz_decode_IS_RS2_SIGNED_32,{_zz__zz_decode_IS_RS2_SIGNED_35,_zz__zz_decode_IS_RS2_SIGNED_40}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_13 = 32'h0000001c; + assign _zz__zz_decode_IS_RS2_SIGNED_15 = 32'h00000058; + assign _zz__zz_decode_IS_RS2_SIGNED_18 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz__zz_decode_IS_RS2_SIGNED_19 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz__zz_decode_IS_RS2_SIGNED_21 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_22) == 32'h40001010); + assign _zz__zz_decode_IS_RS2_SIGNED_23 = {(_zz__zz_decode_IS_RS2_SIGNED_24 == _zz__zz_decode_IS_RS2_SIGNED_25),(_zz__zz_decode_IS_RS2_SIGNED_26 == _zz__zz_decode_IS_RS2_SIGNED_27)}; + assign _zz__zz_decode_IS_RS2_SIGNED_29 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_30) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_31 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_32 = ((_zz__zz_decode_IS_RS2_SIGNED_33 == _zz__zz_decode_IS_RS2_SIGNED_34) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_35 = ({_zz__zz_decode_IS_RS2_SIGNED_36,_zz__zz_decode_IS_RS2_SIGNED_38} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_40 = {(_zz__zz_decode_IS_RS2_SIGNED_41 != _zz__zz_decode_IS_RS2_SIGNED_43),{_zz__zz_decode_IS_RS2_SIGNED_44,{_zz__zz_decode_IS_RS2_SIGNED_47,_zz__zz_decode_IS_RS2_SIGNED_55}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_22 = 32'h40003054; + assign _zz__zz_decode_IS_RS2_SIGNED_24 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_RS2_SIGNED_25 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_26 = (decode_INSTRUCTION & 32'h02007054); + assign _zz__zz_decode_IS_RS2_SIGNED_27 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_30 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_33 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_IS_RS2_SIGNED_34 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_36 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_37) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_38 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_39) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_41 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_42) == 32'h00004008); + assign _zz__zz_decode_IS_RS2_SIGNED_43 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_44 = ((_zz__zz_decode_IS_RS2_SIGNED_45 == _zz__zz_decode_IS_RS2_SIGNED_46) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_47 = ({_zz__zz_decode_IS_RS2_SIGNED_48,_zz__zz_decode_IS_RS2_SIGNED_50} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_55 = {(_zz__zz_decode_IS_RS2_SIGNED_56 != _zz__zz_decode_IS_RS2_SIGNED_58),{_zz__zz_decode_IS_RS2_SIGNED_59,{_zz__zz_decode_IS_RS2_SIGNED_76,_zz__zz_decode_IS_RS2_SIGNED_83}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_37 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_39 = 32'h00005000; + assign _zz__zz_decode_IS_RS2_SIGNED_42 = 32'h00004048; + assign _zz__zz_decode_IS_RS2_SIGNED_45 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_IS_RS2_SIGNED_46 = 32'h00000024; + assign _zz__zz_decode_IS_RS2_SIGNED_48 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_49) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_50 = {(_zz__zz_decode_IS_RS2_SIGNED_51 == _zz__zz_decode_IS_RS2_SIGNED_52),(_zz__zz_decode_IS_RS2_SIGNED_53 == _zz__zz_decode_IS_RS2_SIGNED_54)}; + assign _zz__zz_decode_IS_RS2_SIGNED_56 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_57) == 32'h00000008); + assign _zz__zz_decode_IS_RS2_SIGNED_58 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_59 = ({_zz__zz_decode_IS_RS2_SIGNED_60,{_zz__zz_decode_IS_RS2_SIGNED_62,_zz__zz_decode_IS_RS2_SIGNED_65}} != 6'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_76 = ({_zz__zz_decode_IS_RS2_SIGNED_77,_zz__zz_decode_IS_RS2_SIGNED_80} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_83 = {(_zz__zz_decode_IS_RS2_SIGNED_84 != _zz__zz_decode_IS_RS2_SIGNED_97),{_zz__zz_decode_IS_RS2_SIGNED_98,{_zz__zz_decode_IS_RS2_SIGNED_111,_zz__zz_decode_IS_RS2_SIGNED_130}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_49 = 32'h00000034; + assign _zz__zz_decode_IS_RS2_SIGNED_51 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_IS_RS2_SIGNED_52 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_53 = (decode_INSTRUCTION & 32'h08000070); + assign _zz__zz_decode_IS_RS2_SIGNED_54 = 32'h08000020; + assign _zz__zz_decode_IS_RS2_SIGNED_57 = 32'h00000008; + assign _zz__zz_decode_IS_RS2_SIGNED_60 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_61) == 32'h00002040); + assign _zz__zz_decode_IS_RS2_SIGNED_62 = (_zz__zz_decode_IS_RS2_SIGNED_63 == _zz__zz_decode_IS_RS2_SIGNED_64); + assign _zz__zz_decode_IS_RS2_SIGNED_65 = {_zz__zz_decode_IS_RS2_SIGNED_66,{_zz__zz_decode_IS_RS2_SIGNED_68,_zz__zz_decode_IS_RS2_SIGNED_71}}; + assign _zz__zz_decode_IS_RS2_SIGNED_77 = (_zz__zz_decode_IS_RS2_SIGNED_78 == _zz__zz_decode_IS_RS2_SIGNED_79); + assign _zz__zz_decode_IS_RS2_SIGNED_80 = (_zz__zz_decode_IS_RS2_SIGNED_81 == _zz__zz_decode_IS_RS2_SIGNED_82); + assign _zz__zz_decode_IS_RS2_SIGNED_84 = {_zz__zz_decode_IS_RS2_SIGNED_85,{_zz__zz_decode_IS_RS2_SIGNED_87,_zz__zz_decode_IS_RS2_SIGNED_90}}; + assign _zz__zz_decode_IS_RS2_SIGNED_97 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_98 = ({_zz__zz_decode_IS_RS2_SIGNED_99,_zz__zz_decode_IS_RS2_SIGNED_100} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_111 = (_zz__zz_decode_IS_RS2_SIGNED_112 != _zz__zz_decode_IS_RS2_SIGNED_129); + assign _zz__zz_decode_IS_RS2_SIGNED_130 = {_zz__zz_decode_IS_RS2_SIGNED_131,{_zz__zz_decode_IS_RS2_SIGNED_136,_zz__zz_decode_IS_RS2_SIGNED_141}}; + assign _zz__zz_decode_IS_RS2_SIGNED_61 = 32'h00002040; + assign _zz__zz_decode_IS_RS2_SIGNED_63 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_IS_RS2_SIGNED_64 = 32'h00001040; + assign _zz__zz_decode_IS_RS2_SIGNED_66 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_67) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_68 = (_zz__zz_decode_IS_RS2_SIGNED_69 == _zz__zz_decode_IS_RS2_SIGNED_70); + assign _zz__zz_decode_IS_RS2_SIGNED_71 = {_zz__zz_decode_IS_RS2_SIGNED_72,_zz__zz_decode_IS_RS2_SIGNED_74}; + assign _zz__zz_decode_IS_RS2_SIGNED_78 = (decode_INSTRUCTION & 32'h08000020); + assign _zz__zz_decode_IS_RS2_SIGNED_79 = 32'h08000020; + assign _zz__zz_decode_IS_RS2_SIGNED_81 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_RS2_SIGNED_82 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_85 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_86) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_87 = (_zz__zz_decode_IS_RS2_SIGNED_88 == _zz__zz_decode_IS_RS2_SIGNED_89); + assign _zz__zz_decode_IS_RS2_SIGNED_90 = {_zz__zz_decode_IS_RS2_SIGNED_91,{_zz__zz_decode_IS_RS2_SIGNED_93,_zz__zz_decode_IS_RS2_SIGNED_94}}; + assign _zz__zz_decode_IS_RS2_SIGNED_99 = _zz_decode_IS_RS2_SIGNED_5; + assign _zz__zz_decode_IS_RS2_SIGNED_100 = {_zz__zz_decode_IS_RS2_SIGNED_101,{_zz__zz_decode_IS_RS2_SIGNED_103,_zz__zz_decode_IS_RS2_SIGNED_106}}; + assign _zz__zz_decode_IS_RS2_SIGNED_112 = {_zz_decode_IS_RS2_SIGNED_2,{_zz__zz_decode_IS_RS2_SIGNED_113,_zz__zz_decode_IS_RS2_SIGNED_116}}; + assign _zz__zz_decode_IS_RS2_SIGNED_129 = 7'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_131 = ({_zz__zz_decode_IS_RS2_SIGNED_132,_zz__zz_decode_IS_RS2_SIGNED_133} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_136 = (_zz__zz_decode_IS_RS2_SIGNED_137 != _zz__zz_decode_IS_RS2_SIGNED_140); + assign _zz__zz_decode_IS_RS2_SIGNED_141 = {_zz__zz_decode_IS_RS2_SIGNED_142,{_zz__zz_decode_IS_RS2_SIGNED_145,_zz__zz_decode_IS_RS2_SIGNED_150}}; + assign _zz__zz_decode_IS_RS2_SIGNED_67 = 32'h00000050; + assign _zz__zz_decode_IS_RS2_SIGNED_69 = (decode_INSTRUCTION & 32'h00400040); + assign _zz__zz_decode_IS_RS2_SIGNED_70 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_72 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_73) == 32'h00002008); + assign _zz__zz_decode_IS_RS2_SIGNED_74 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_75) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_86 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_88 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_IS_RS2_SIGNED_89 = 32'h00004020; + assign _zz__zz_decode_IS_RS2_SIGNED_91 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_92) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_93 = _zz_decode_IS_RS2_SIGNED_5; + assign _zz__zz_decode_IS_RS2_SIGNED_94 = (_zz__zz_decode_IS_RS2_SIGNED_95 == _zz__zz_decode_IS_RS2_SIGNED_96); + assign _zz__zz_decode_IS_RS2_SIGNED_101 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_102) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_103 = (_zz__zz_decode_IS_RS2_SIGNED_104 == _zz__zz_decode_IS_RS2_SIGNED_105); + assign _zz__zz_decode_IS_RS2_SIGNED_106 = {_zz__zz_decode_IS_RS2_SIGNED_107,_zz__zz_decode_IS_RS2_SIGNED_109}; + assign _zz__zz_decode_IS_RS2_SIGNED_113 = (_zz__zz_decode_IS_RS2_SIGNED_114 == _zz__zz_decode_IS_RS2_SIGNED_115); + assign _zz__zz_decode_IS_RS2_SIGNED_116 = {_zz__zz_decode_IS_RS2_SIGNED_117,{_zz__zz_decode_IS_RS2_SIGNED_119,_zz__zz_decode_IS_RS2_SIGNED_122}}; + assign _zz__zz_decode_IS_RS2_SIGNED_132 = _zz_decode_IS_RS2_SIGNED_4; + assign _zz__zz_decode_IS_RS2_SIGNED_133 = (_zz__zz_decode_IS_RS2_SIGNED_134 == _zz__zz_decode_IS_RS2_SIGNED_135); + assign _zz__zz_decode_IS_RS2_SIGNED_137 = {_zz_decode_IS_RS2_SIGNED_4,_zz__zz_decode_IS_RS2_SIGNED_138}; + assign _zz__zz_decode_IS_RS2_SIGNED_140 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_142 = (_zz__zz_decode_IS_RS2_SIGNED_143 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_145 = (_zz__zz_decode_IS_RS2_SIGNED_146 != _zz__zz_decode_IS_RS2_SIGNED_149); + assign _zz__zz_decode_IS_RS2_SIGNED_150 = {_zz__zz_decode_IS_RS2_SIGNED_151,{_zz__zz_decode_IS_RS2_SIGNED_163,_zz__zz_decode_IS_RS2_SIGNED_168}}; + assign _zz__zz_decode_IS_RS2_SIGNED_73 = 32'h08002008; + assign _zz__zz_decode_IS_RS2_SIGNED_75 = 32'h00000038; + assign _zz__zz_decode_IS_RS2_SIGNED_92 = 32'h00000030; + assign _zz__zz_decode_IS_RS2_SIGNED_95 = (decode_INSTRUCTION & 32'h12000020); + assign _zz__zz_decode_IS_RS2_SIGNED_96 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_102 = 32'h00002030; + assign _zz__zz_decode_IS_RS2_SIGNED_104 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_IS_RS2_SIGNED_105 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_107 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_108) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_109 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_110) == 32'h00002020); + assign _zz__zz_decode_IS_RS2_SIGNED_114 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_115 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_117 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_118) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_119 = (_zz__zz_decode_IS_RS2_SIGNED_120 == _zz__zz_decode_IS_RS2_SIGNED_121); + assign _zz__zz_decode_IS_RS2_SIGNED_122 = {_zz__zz_decode_IS_RS2_SIGNED_123,{_zz__zz_decode_IS_RS2_SIGNED_125,_zz__zz_decode_IS_RS2_SIGNED_126}}; + assign _zz__zz_decode_IS_RS2_SIGNED_134 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_IS_RS2_SIGNED_135 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_138 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_139) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_143 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_144) == 32'h00004010); + assign _zz__zz_decode_IS_RS2_SIGNED_146 = (_zz__zz_decode_IS_RS2_SIGNED_147 == _zz__zz_decode_IS_RS2_SIGNED_148); + assign _zz__zz_decode_IS_RS2_SIGNED_149 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_151 = ({_zz__zz_decode_IS_RS2_SIGNED_152,_zz__zz_decode_IS_RS2_SIGNED_155} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_163 = (_zz__zz_decode_IS_RS2_SIGNED_164 != _zz__zz_decode_IS_RS2_SIGNED_167); + assign _zz__zz_decode_IS_RS2_SIGNED_168 = {_zz__zz_decode_IS_RS2_SIGNED_169,{_zz__zz_decode_IS_RS2_SIGNED_176,_zz__zz_decode_IS_RS2_SIGNED_181}}; + assign _zz__zz_decode_IS_RS2_SIGNED_108 = 32'h02003020; + assign _zz__zz_decode_IS_RS2_SIGNED_110 = 32'h12002060; + assign _zz__zz_decode_IS_RS2_SIGNED_118 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_120 = (decode_INSTRUCTION & 32'h00002008); + assign _zz__zz_decode_IS_RS2_SIGNED_121 = 32'h00002008; + assign _zz__zz_decode_IS_RS2_SIGNED_123 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_124) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_125 = _zz_decode_IS_RS2_SIGNED_5; + assign _zz__zz_decode_IS_RS2_SIGNED_126 = (_zz__zz_decode_IS_RS2_SIGNED_127 == _zz__zz_decode_IS_RS2_SIGNED_128); + assign _zz__zz_decode_IS_RS2_SIGNED_139 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_144 = 32'h00004014; + assign _zz__zz_decode_IS_RS2_SIGNED_147 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_IS_RS2_SIGNED_148 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_152 = (_zz__zz_decode_IS_RS2_SIGNED_153 == _zz__zz_decode_IS_RS2_SIGNED_154); + assign _zz__zz_decode_IS_RS2_SIGNED_155 = {_zz__zz_decode_IS_RS2_SIGNED_156,{_zz__zz_decode_IS_RS2_SIGNED_158,_zz__zz_decode_IS_RS2_SIGNED_161}}; + assign _zz__zz_decode_IS_RS2_SIGNED_164 = {_zz_decode_IS_RS2_SIGNED_3,_zz__zz_decode_IS_RS2_SIGNED_165}; + assign _zz__zz_decode_IS_RS2_SIGNED_167 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_169 = ({_zz__zz_decode_IS_RS2_SIGNED_170,_zz__zz_decode_IS_RS2_SIGNED_173} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_176 = (_zz__zz_decode_IS_RS2_SIGNED_177 != _zz__zz_decode_IS_RS2_SIGNED_180); + assign _zz__zz_decode_IS_RS2_SIGNED_181 = {_zz__zz_decode_IS_RS2_SIGNED_182,_zz__zz_decode_IS_RS2_SIGNED_185}; + assign _zz__zz_decode_IS_RS2_SIGNED_124 = 32'h00000050; + assign _zz__zz_decode_IS_RS2_SIGNED_127 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_RS2_SIGNED_128 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_153 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_RS2_SIGNED_154 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_156 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_157) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_158 = (_zz__zz_decode_IS_RS2_SIGNED_159 == _zz__zz_decode_IS_RS2_SIGNED_160); + assign _zz__zz_decode_IS_RS2_SIGNED_161 = {_zz__zz_decode_IS_RS2_SIGNED_162,_zz_decode_IS_RS2_SIGNED_3}; + assign _zz__zz_decode_IS_RS2_SIGNED_165 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_166) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_170 = (_zz__zz_decode_IS_RS2_SIGNED_171 == _zz__zz_decode_IS_RS2_SIGNED_172); + assign _zz__zz_decode_IS_RS2_SIGNED_173 = {_zz__zz_decode_IS_RS2_SIGNED_174,_zz__zz_decode_IS_RS2_SIGNED_175}; + assign _zz__zz_decode_IS_RS2_SIGNED_177 = {_zz_decode_IS_RS2_SIGNED_2,{_zz__zz_decode_IS_RS2_SIGNED_178,_zz__zz_decode_IS_RS2_SIGNED_179}}; + assign _zz__zz_decode_IS_RS2_SIGNED_180 = 3'b000; + assign _zz__zz_decode_IS_RS2_SIGNED_182 = ({_zz__zz_decode_IS_RS2_SIGNED_183,_zz__zz_decode_IS_RS2_SIGNED_184} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_185 = (_zz__zz_decode_IS_RS2_SIGNED_186 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_157 = 32'h00000018; + assign _zz__zz_decode_IS_RS2_SIGNED_159 = (decode_INSTRUCTION & 32'h00006004); + assign _zz__zz_decode_IS_RS2_SIGNED_160 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_162 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_166 = 32'h00000058; + assign _zz__zz_decode_IS_RS2_SIGNED_171 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_RS2_SIGNED_172 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_174 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_175 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz__zz_decode_IS_RS2_SIGNED_178 = _zz_decode_IS_RS2_SIGNED_1; + assign _zz__zz_decode_IS_RS2_SIGNED_179 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_183 = _zz_decode_IS_RS2_SIGNED_1; + assign _zz__zz_decode_IS_RS2_SIGNED_184 = ((decode_INSTRUCTION & 32'h0000004c) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_186 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_195 ), //i - .io_cpu_prefetch_isValid (_zz_196 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_197 ), //i - .io_cpu_fetch_isStuck (_zz_198 ), //i - .io_cpu_fetch_isRemoved (_zz_199 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_fetch_cacheMiss (IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss ), //o - .io_cpu_fetch_error (IBusCachedPlugin_cache_io_cpu_fetch_error ), //o - .io_cpu_fetch_mmuRefilling (IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling ), //o - .io_cpu_fetch_mmuException (IBusCachedPlugin_cache_io_cpu_fetch_mmuException ), //o - .io_cpu_fetch_isUser (_zz_200 ), //i - .io_cpu_decode_isValid (_zz_201 ), //i - .io_cpu_decode_isStuck (_zz_202 ), //i - .io_cpu_decode_pc (_zz_203[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_fill_valid (_zz_204 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_fetch_cacheMiss (IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss ), //o + .io_cpu_fetch_error (IBusCachedPlugin_cache_io_cpu_fetch_error ), //o + .io_cpu_fetch_mmuRefilling (IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling ), //o + .io_cpu_fetch_mmuException (IBusCachedPlugin_cache_io_cpu_fetch_mmuException ), //o + .io_cpu_fetch_isUser (IBusCachedPlugin_cache_io_cpu_fetch_isUser ), //i + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_cache_io_cpu_decode_pc ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_205 ), //i - .io_cpu_execute_address (_zz_206[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_104[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_207 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_208[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_209 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_210 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_211 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_212[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_213 ), //i - .io_cpu_writeBack_fence_SR (_zz_214 ), //i - .io_cpu_writeBack_fence_SO (_zz_215 ), //i - .io_cpu_writeBack_fence_SI (_zz_216 ), //i - .io_cpu_writeBack_fence_PW (_zz_217 ), //i - .io_cpu_writeBack_fence_PR (_zz_218 ), //i - .io_cpu_writeBack_fence_PO (_zz_219 ), //i - .io_cpu_writeBack_fence_PI (_zz_220 ), //i - .io_cpu_writeBack_fence_FM (_zz_221[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_222 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_223 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_isLrsc (dataCache_1_io_cpu_execute_args_isLrsc ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_361) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) 2'b00 : begin - _zz_226 = DBusCachedPlugin_redoBranch_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_226 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_226 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_226 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + end + 2'b01 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + end + 2'b10 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_30) - `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; - default : _zz_30_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_33) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; - default : _zz_33_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_34) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; - default : _zz_34_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_36) - `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; - default : _zz_36_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_37) - `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; - default : _zz_37_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_38) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; - default : _zz_38_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_39) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; - default : _zz_39_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_43) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; - default : _zz_43_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; - default : _zz_44_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_45) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; - default : _zz_45_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_46) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; - default : _zz_46_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_47) - `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; - default : _zz_47_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_48) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; - default : _zz_48_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_49) - `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; - default : _zz_49_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_114) - `Src1CtrlEnum_defaultEncoding_RS : _zz_114_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_114_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_114_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_114_string = "URS1 "; - default : _zz_114_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_115) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_115_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_115_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_115_string = "BITWISE "; - default : _zz_115_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_116) - `Src2CtrlEnum_defaultEncoding_RS : _zz_116_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_116_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_116_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_116_string = "PC "; - default : _zz_116_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_117) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_117_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_117_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_117_string = "AND_1"; - default : _zz_117_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_118) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_118_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_118_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_118_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_118_string = "SRA_1 "; - default : _zz_118_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_119) - `BranchCtrlEnum_defaultEncoding_INC : _zz_119_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_119_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_119_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_119_string = "JALR"; - default : _zz_119_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_120) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_120_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_120_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_120_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_120_string = "ECALL"; - default : _zz_120_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_269) + $signed(_zz_277)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2489,49 +2658,50 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_279; - assign execute_REGFILE_WRITE_DATA = _zz_122; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_206[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_281[0]; - assign decode_IS_RS1_SIGNED = _zz_282[0]; - assign decode_IS_DIV = _zz_283[0]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_RS2_SIGNED[32]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_RS2_SIGNED[31]; + assign decode_IS_DIV = _zz_decode_IS_RS2_SIGNED[30]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_284[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_285[0]; - assign _zz_8 = _zz_9; - assign _zz_10 = _zz_11; - assign decode_SHIFT_CTRL = _zz_12; - assign _zz_13 = _zz_14; - assign decode_ALU_BITWISE_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_286[0]; - assign decode_MEMORY_MANAGMENT = _zz_287[0]; + assign decode_IS_MUL = _zz_decode_IS_RS2_SIGNED[29]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_RS2_SIGNED[26]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_RS2_SIGNED[19]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_RS2_SIGNED[18]; + assign memory_MEMORY_LRSC = execute_to_memory_MEMORY_LRSC; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_288[0]; + assign decode_MEMORY_WR = _zz_decode_IS_RS2_SIGNED[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_289[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_290[0]; - assign decode_SRC2_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_ALU_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_SRC1_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_RS2_SIGNED[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_RS2_SIGNED[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_decode_MEMORY_FORCE_CONSTISTENCY; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_292); + assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_decode_FORMAL_PC_NEXT); assign memory_PC = execute_to_memory_PC; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; @@ -2546,22 +2716,22 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27; - assign execute_ENV_CTRL = _zz_28; - assign writeBack_ENV_CTRL = _zz_29; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_144; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; - assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_293[0]; - assign decode_RS1_USE = _zz_294[0]; - always @ (*) begin - _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_227)begin - _zz_31 = execute_CsrPlugin_readData; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_RS2_SIGNED[16]; + assign decode_RS1_USE = _zz_decode_IS_RS2_SIGNED[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2571,144 +2741,146 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_133)begin - if((_zz_134 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_135; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_228)begin - if(_zz_229)begin - if(_zz_137)begin - decode_RS2 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_230)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_139)begin - decode_RS2 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_231)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_141)begin - decode_RS2 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_133)begin - if((_zz_134 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_135; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_228)begin - if(_zz_229)begin - if(_zz_136)begin - decode_RS1 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_230)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_138)begin - decode_RS1 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_231)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_140)begin - decode_RS1 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_32 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_32 = _zz_130; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_32 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_232)begin - _zz_32 = memory_DivPlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_33; - assign execute_SHIFT_CTRL = _zz_34; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_35 = execute_PC; - assign execute_SRC2_CTRL = _zz_36; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; assign execute_IS_RVC = decode_to_execute_IS_RVC; - assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_295[0]; - assign decode_SRC_ADD_ZERO = _zz_296[0]; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_RS2_SIGNED[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_RS2_SIGNED[17]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_38; - assign execute_SRC2 = _zz_128; - assign execute_SRC1 = _zz_123; - assign execute_ALU_BITWISE_CTRL = _zz_39; - assign _zz_40 = writeBack_INSTRUCTION; - assign _zz_41 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_42 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_42 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_decompressor_output_payload_rsp_inst); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_297[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_RS2_SIGNED[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_362) == 32'h00001073),{(_zz_363 == _zz_364),{_zz_365,{_zz_366,_zz_367}}}}}}} != 21'h0); - always @ (*) begin - _zz_50 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_50 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 23'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_268) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_50 = _zz_334; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_50 = _zz_335; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_LRSC = memory_to_writeBack_MEMORY_LRSC; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; @@ -2716,48 +2888,49 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_298[0]; - assign decode_FLUSH_ALL = _zz_299[0]; - always @ (*) begin + assign decode_MEMORY_LRSC = _zz_decode_IS_RS2_SIGNED[15]; + assign decode_MEMORY_ENABLE = _zz_decode_IS_RS2_SIGNED[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_RS2_SIGNED[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_233)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_234)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_235)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_236)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_51; - always @ (*) begin - _zz_52 = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_52 = BranchPlugin_jumpInterface_payload; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_53 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end @@ -2766,151 +2939,151 @@ module VexRiscv ( assign decode_IS_RVC = IBusCachedPlugin_injector_decodeInput_payload_isRvc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_131 || _zz_132)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_237)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_237)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_222 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_238)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_227)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_232)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_239)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_240)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2919,54 +3092,56 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_239)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_240)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_valid)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_valid) begin IBusCachedPlugin_incomingInstruction = 1'b1; end - if(IBusCachedPlugin_injector_decodeInput_valid)begin + if(IBusCachedPlugin_injector_decodeInput_valid) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_238)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_239)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_240)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_239)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_240)begin - case(_zz_241) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2979,70 +3154,78 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_54 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_55 = (_zz_54 & (~ _zz_300)); - assign _zz_56 = _zz_55[3]; - assign _zz_57 = (_zz_55[1] || _zz_56); - assign _zz_58 = (_zz_55[2] || _zz_56); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_226; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_302); - if(IBusCachedPlugin_fetchPc_inc)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_inc) begin IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodePc_flushed = 1'b0; - if(_zz_242)begin + if(when_Fetcher_l192) begin IBusCachedPlugin_decodePc_flushed = 1'b1; end end - assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_304); + assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_IBusCachedPlugin_decodePc_pcPlus); assign IBusCachedPlugin_decodePc_injectedDecode = 1'b0; - always @ (*) begin + assign when_Fetcher_l180 = (decode_arbitration_isFiring && (! IBusCachedPlugin_decodePc_injectedDecode)); + assign when_Fetcher_l192 = (IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3050,48 +3233,48 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_59 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_59); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_59); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_60); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_60); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - if(IBusCachedPlugin_decompressor_throw2BytesReg)begin + if(IBusCachedPlugin_decompressor_throw2BytesReg) begin IBusCachedPlugin_fetchPc_redo_payload[1] = 1'b1; end end assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_61; - assign _zz_61 = ((1'b0 && (! _zz_62)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_62 = _zz_63; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_62; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if(IBusCachedPlugin_injector_decodeInput_valid)begin + if(IBusCachedPlugin_injector_decodeInput_valid) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end @@ -3108,190 +3291,195 @@ module VexRiscv ( assign IBusCachedPlugin_decompressor_isInputHighRvc = (IBusCachedPlugin_decompressor_input_payload_rsp_inst[17 : 16] != 2'b11); assign IBusCachedPlugin_decompressor_throw2Bytes = (IBusCachedPlugin_decompressor_throw2BytesReg || IBusCachedPlugin_decompressor_input_payload_pc[1]); assign IBusCachedPlugin_decompressor_unaligned = (IBusCachedPlugin_decompressor_throw2Bytes || IBusCachedPlugin_decompressor_bufferValid); - assign IBusCachedPlugin_decompressor_raw = (IBusCachedPlugin_decompressor_bufferValid ? {IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0],IBusCachedPlugin_decompressor_bufferData} : {IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16],(IBusCachedPlugin_decompressor_throw2Bytes ? IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16] : IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0])}); + assign IBusCachedPlugin_decompressor_bufferValidPatched = (IBusCachedPlugin_decompressor_input_valid ? IBusCachedPlugin_decompressor_bufferValid : IBusCachedPlugin_decompressor_bufferValidLatch); + assign IBusCachedPlugin_decompressor_throw2BytesPatched = (IBusCachedPlugin_decompressor_input_valid ? IBusCachedPlugin_decompressor_throw2Bytes : IBusCachedPlugin_decompressor_throw2BytesLatch); + assign IBusCachedPlugin_decompressor_raw = (IBusCachedPlugin_decompressor_bufferValidPatched ? {IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0],IBusCachedPlugin_decompressor_bufferData} : {IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16],(IBusCachedPlugin_decompressor_throw2BytesPatched ? IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16] : IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0])}); assign IBusCachedPlugin_decompressor_isRvc = (IBusCachedPlugin_decompressor_raw[1 : 0] != 2'b11); - assign _zz_64 = IBusCachedPlugin_decompressor_raw[15 : 0]; - always @ (*) begin - IBusCachedPlugin_decompressor_decompressed = 32'h0; - case(_zz_263) + assign _zz_IBusCachedPlugin_decompressor_decompressed = IBusCachedPlugin_decompressor_raw[15 : 0]; + always @(*) begin + IBusCachedPlugin_decompressor_decompressed = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(switch_Misc_l44) 5'h0 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{{{2'b00,_zz_64[10 : 7]},_zz_64[12 : 11]},_zz_64[5]},_zz_64[6]},2'b00},5'h02},3'b000},_zz_66},7'h13}; + IBusCachedPlugin_decompressor_decompressed = {{{{{{{{{2'b00,_zz_IBusCachedPlugin_decompressor_decompressed[10 : 7]},_zz_IBusCachedPlugin_decompressor_decompressed[12 : 11]},_zz_IBusCachedPlugin_decompressor_decompressed[5]},_zz_IBusCachedPlugin_decompressor_decompressed[6]},2'b00},5'h02},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed_2},7'h13}; end 5'h02 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_67,_zz_65},3'b010},_zz_66},7'h03}; + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_IBusCachedPlugin_decompressor_decompressed_3,_zz_IBusCachedPlugin_decompressor_decompressed_1},3'b010},_zz_IBusCachedPlugin_decompressor_decompressed_2},7'h03}; end 5'h06 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_67[11 : 5],_zz_66},_zz_65},3'b010},_zz_67[4 : 0]},7'h23}; + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_3[11 : 5],_zz_IBusCachedPlugin_decompressor_decompressed_2},_zz_IBusCachedPlugin_decompressor_decompressed_1},3'b010},_zz_IBusCachedPlugin_decompressor_decompressed_3[4 : 0]},7'h23}; end 5'h08 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_69,_zz_64[11 : 7]},3'b000},_zz_64[11 : 7]},7'h13}; + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_IBusCachedPlugin_decompressor_decompressed_5,_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h13}; end 5'h09 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_72[20],_zz_72[10 : 1]},_zz_72[11]},_zz_72[19 : 12]},_zz_84},7'h6f}; + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_8[20],_zz_IBusCachedPlugin_decompressor_decompressed_8[10 : 1]},_zz_IBusCachedPlugin_decompressor_decompressed_8[11]},_zz_IBusCachedPlugin_decompressor_decompressed_8[19 : 12]},_zz_IBusCachedPlugin_decompressor_decompressed_20},7'h6f}; end 5'h0a : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_69,5'h0},3'b000},_zz_64[11 : 7]},7'h13}; + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_IBusCachedPlugin_decompressor_decompressed_5,5'h0},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h13}; end 5'h0b : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_64[11 : 7] == 5'h02) ? {{{{{{{{{_zz_76,_zz_64[4 : 3]},_zz_64[5]},_zz_64[2]},_zz_64[6]},4'b0000},_zz_64[11 : 7]},3'b000},_zz_64[11 : 7]},7'h13} : {{_zz_305[31 : 12],_zz_64[11 : 7]},7'h37}); + IBusCachedPlugin_decompressor_decompressed = ((_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7] == 5'h02) ? {{{{{{{{{_zz_IBusCachedPlugin_decompressor_decompressed_12,_zz_IBusCachedPlugin_decompressor_decompressed[4 : 3]},_zz_IBusCachedPlugin_decompressor_decompressed[5]},_zz_IBusCachedPlugin_decompressor_decompressed[2]},_zz_IBusCachedPlugin_decompressor_decompressed[6]},4'b0000},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h13} : {{_zz_IBusCachedPlugin_decompressor_decompressed_27[31 : 12],_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h37}); end 5'h0c : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_64[11 : 10] == 2'b10) ? _zz_90 : {{1'b0,(_zz_380 || _zz_381)},5'h0}),(((! _zz_64[11]) || _zz_86) ? _zz_64[6 : 2] : _zz_66)},_zz_65},_zz_88},_zz_65},(_zz_86 ? 7'h13 : 7'h33)}; + IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_IBusCachedPlugin_decompressor_decompressed[11 : 10] == 2'b10) ? _zz_IBusCachedPlugin_decompressor_decompressed_26 : {{1'b0,(_zz_IBusCachedPlugin_decompressor_decompressed_28 || _zz_IBusCachedPlugin_decompressor_decompressed_29)},5'h0}),(((! _zz_IBusCachedPlugin_decompressor_decompressed[11]) || _zz_IBusCachedPlugin_decompressor_decompressed_22) ? _zz_IBusCachedPlugin_decompressor_decompressed[6 : 2] : _zz_IBusCachedPlugin_decompressor_decompressed_2)},_zz_IBusCachedPlugin_decompressor_decompressed_1},_zz_IBusCachedPlugin_decompressor_decompressed_24},_zz_IBusCachedPlugin_decompressor_decompressed_1},(_zz_IBusCachedPlugin_decompressor_decompressed_22 ? 7'h13 : 7'h33)}; end 5'h0d : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_79[20],_zz_79[10 : 1]},_zz_79[11]},_zz_79[19 : 12]},_zz_83},7'h6f}; + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_15[20],_zz_IBusCachedPlugin_decompressor_decompressed_15[10 : 1]},_zz_IBusCachedPlugin_decompressor_decompressed_15[11]},_zz_IBusCachedPlugin_decompressor_decompressed_15[19 : 12]},_zz_IBusCachedPlugin_decompressor_decompressed_19},7'h6f}; end 5'h0e : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_82[12],_zz_82[10 : 5]},_zz_83},_zz_65},3'b000},_zz_82[4 : 1]},_zz_82[11]},7'h63}; + IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_IBusCachedPlugin_decompressor_decompressed_18[12],_zz_IBusCachedPlugin_decompressor_decompressed_18[10 : 5]},_zz_IBusCachedPlugin_decompressor_decompressed_19},_zz_IBusCachedPlugin_decompressor_decompressed_1},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed_18[4 : 1]},_zz_IBusCachedPlugin_decompressor_decompressed_18[11]},7'h63}; end 5'h0f : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_82[12],_zz_82[10 : 5]},_zz_83},_zz_65},3'b001},_zz_82[4 : 1]},_zz_82[11]},7'h63}; + IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_IBusCachedPlugin_decompressor_decompressed_18[12],_zz_IBusCachedPlugin_decompressor_decompressed_18[10 : 5]},_zz_IBusCachedPlugin_decompressor_decompressed_19},_zz_IBusCachedPlugin_decompressor_decompressed_1},3'b001},_zz_IBusCachedPlugin_decompressor_decompressed_18[4 : 1]},_zz_IBusCachedPlugin_decompressor_decompressed_18[11]},7'h63}; end 5'h10 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{7'h0,_zz_64[6 : 2]},_zz_64[11 : 7]},3'b001},_zz_64[11 : 7]},7'h13}; + IBusCachedPlugin_decompressor_decompressed = {{{{{7'h0,_zz_IBusCachedPlugin_decompressor_decompressed[6 : 2]},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},3'b001},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h13}; end 5'h12 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{{4'b0000,_zz_64[3 : 2]},_zz_64[12]},_zz_64[6 : 4]},2'b00},_zz_85},3'b010},_zz_64[11 : 7]},7'h03}; + IBusCachedPlugin_decompressor_decompressed = {{{{{{{{4'b0000,_zz_IBusCachedPlugin_decompressor_decompressed[3 : 2]},_zz_IBusCachedPlugin_decompressor_decompressed[12]},_zz_IBusCachedPlugin_decompressor_decompressed[6 : 4]},2'b00},_zz_IBusCachedPlugin_decompressor_decompressed_21},3'b010},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h03}; end 5'h14 : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_64[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_64[6 : 2] == 5'h0) ? {{{{12'h0,_zz_64[11 : 7]},3'b000},(_zz_64[12] ? _zz_84 : _zz_83)},7'h67} : {{{{{_zz_382,_zz_383},(_zz_384 ? _zz_385 : _zz_83)},3'b000},_zz_64[11 : 7]},7'h33})); + IBusCachedPlugin_decompressor_decompressed = ((_zz_IBusCachedPlugin_decompressor_decompressed[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_IBusCachedPlugin_decompressor_decompressed[6 : 2] == 5'h0) ? {{{{12'h0,_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},3'b000},(_zz_IBusCachedPlugin_decompressor_decompressed[12] ? _zz_IBusCachedPlugin_decompressor_decompressed_20 : _zz_IBusCachedPlugin_decompressor_decompressed_19)},7'h67} : {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_30,_zz_IBusCachedPlugin_decompressor_decompressed_31},(_zz_IBusCachedPlugin_decompressor_decompressed_32 ? _zz_IBusCachedPlugin_decompressor_decompressed_33 : _zz_IBusCachedPlugin_decompressor_decompressed_19)},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h33})); end 5'h16 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_306[11 : 5],_zz_64[6 : 2]},_zz_85},3'b010},_zz_307[4 : 0]},7'h23}; + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_34[11 : 5],_zz_IBusCachedPlugin_decompressor_decompressed[6 : 2]},_zz_IBusCachedPlugin_decompressor_decompressed_21},3'b010},_zz_IBusCachedPlugin_decompressor_decompressed_35[4 : 0]},7'h23}; end default : begin end endcase end - assign _zz_65 = {2'b01,_zz_64[9 : 7]}; - assign _zz_66 = {2'b01,_zz_64[4 : 2]}; - assign _zz_67 = {{{{5'h0,_zz_64[5]},_zz_64[12 : 10]},_zz_64[6]},2'b00}; - assign _zz_68 = _zz_64[12]; - always @ (*) begin - _zz_69[11] = _zz_68; - _zz_69[10] = _zz_68; - _zz_69[9] = _zz_68; - _zz_69[8] = _zz_68; - _zz_69[7] = _zz_68; - _zz_69[6] = _zz_68; - _zz_69[5] = _zz_68; - _zz_69[4 : 0] = _zz_64[6 : 2]; - end - - assign _zz_70 = _zz_64[12]; - always @ (*) begin - _zz_71[9] = _zz_70; - _zz_71[8] = _zz_70; - _zz_71[7] = _zz_70; - _zz_71[6] = _zz_70; - _zz_71[5] = _zz_70; - _zz_71[4] = _zz_70; - _zz_71[3] = _zz_70; - _zz_71[2] = _zz_70; - _zz_71[1] = _zz_70; - _zz_71[0] = _zz_70; - end - - assign _zz_72 = {{{{{{{{_zz_71,_zz_64[8]},_zz_64[10 : 9]},_zz_64[6]},_zz_64[7]},_zz_64[2]},_zz_64[11]},_zz_64[5 : 3]},1'b0}; - assign _zz_73 = _zz_64[12]; - always @ (*) begin - _zz_74[14] = _zz_73; - _zz_74[13] = _zz_73; - _zz_74[12] = _zz_73; - _zz_74[11] = _zz_73; - _zz_74[10] = _zz_73; - _zz_74[9] = _zz_73; - _zz_74[8] = _zz_73; - _zz_74[7] = _zz_73; - _zz_74[6] = _zz_73; - _zz_74[5] = _zz_73; - _zz_74[4] = _zz_73; - _zz_74[3] = _zz_73; - _zz_74[2] = _zz_73; - _zz_74[1] = _zz_73; - _zz_74[0] = _zz_73; - end - - assign _zz_75 = _zz_64[12]; - always @ (*) begin - _zz_76[2] = _zz_75; - _zz_76[1] = _zz_75; - _zz_76[0] = _zz_75; - end - - assign _zz_77 = _zz_64[12]; - always @ (*) begin - _zz_78[9] = _zz_77; - _zz_78[8] = _zz_77; - _zz_78[7] = _zz_77; - _zz_78[6] = _zz_77; - _zz_78[5] = _zz_77; - _zz_78[4] = _zz_77; - _zz_78[3] = _zz_77; - _zz_78[2] = _zz_77; - _zz_78[1] = _zz_77; - _zz_78[0] = _zz_77; - end - - assign _zz_79 = {{{{{{{{_zz_78,_zz_64[8]},_zz_64[10 : 9]},_zz_64[6]},_zz_64[7]},_zz_64[2]},_zz_64[11]},_zz_64[5 : 3]},1'b0}; - assign _zz_80 = _zz_64[12]; - always @ (*) begin - _zz_81[4] = _zz_80; - _zz_81[3] = _zz_80; - _zz_81[2] = _zz_80; - _zz_81[1] = _zz_80; - _zz_81[0] = _zz_80; - end - - assign _zz_82 = {{{{{_zz_81,_zz_64[6 : 5]},_zz_64[2]},_zz_64[11 : 10]},_zz_64[4 : 3]},1'b0}; - assign _zz_83 = 5'h0; - assign _zz_84 = 5'h01; - assign _zz_85 = 5'h02; - assign _zz_86 = (_zz_64[11 : 10] != 2'b11); - always @ (*) begin - case(_zz_264) + assign _zz_IBusCachedPlugin_decompressor_decompressed_1 = {2'b01,_zz_IBusCachedPlugin_decompressor_decompressed[9 : 7]}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_2 = {2'b01,_zz_IBusCachedPlugin_decompressor_decompressed[4 : 2]}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_3 = {{{{5'h0,_zz_IBusCachedPlugin_decompressor_decompressed[5]},_zz_IBusCachedPlugin_decompressor_decompressed[12 : 10]},_zz_IBusCachedPlugin_decompressor_decompressed[6]},2'b00}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_4 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_5[11] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[10] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[9] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[8] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[7] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[6] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[5] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[4 : 0] = _zz_IBusCachedPlugin_decompressor_decompressed[6 : 2]; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_6 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_7[9] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[8] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[7] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[6] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[5] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[4] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[3] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[2] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[1] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[0] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_8 = {{{{{{{{_zz_IBusCachedPlugin_decompressor_decompressed_7,_zz_IBusCachedPlugin_decompressor_decompressed[8]},_zz_IBusCachedPlugin_decompressor_decompressed[10 : 9]},_zz_IBusCachedPlugin_decompressor_decompressed[6]},_zz_IBusCachedPlugin_decompressor_decompressed[7]},_zz_IBusCachedPlugin_decompressor_decompressed[2]},_zz_IBusCachedPlugin_decompressor_decompressed[11]},_zz_IBusCachedPlugin_decompressor_decompressed[5 : 3]},1'b0}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_9 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_10[14] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[13] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[12] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[11] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[10] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[9] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[8] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[7] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[6] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[5] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[4] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[3] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[2] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[1] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[0] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_11 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_12[2] = _zz_IBusCachedPlugin_decompressor_decompressed_11; + _zz_IBusCachedPlugin_decompressor_decompressed_12[1] = _zz_IBusCachedPlugin_decompressor_decompressed_11; + _zz_IBusCachedPlugin_decompressor_decompressed_12[0] = _zz_IBusCachedPlugin_decompressor_decompressed_11; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_13 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_14[9] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[8] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[7] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[6] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[5] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[4] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[3] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[2] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[1] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[0] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_15 = {{{{{{{{_zz_IBusCachedPlugin_decompressor_decompressed_14,_zz_IBusCachedPlugin_decompressor_decompressed[8]},_zz_IBusCachedPlugin_decompressor_decompressed[10 : 9]},_zz_IBusCachedPlugin_decompressor_decompressed[6]},_zz_IBusCachedPlugin_decompressor_decompressed[7]},_zz_IBusCachedPlugin_decompressor_decompressed[2]},_zz_IBusCachedPlugin_decompressor_decompressed[11]},_zz_IBusCachedPlugin_decompressor_decompressed[5 : 3]},1'b0}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_16 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_17[4] = _zz_IBusCachedPlugin_decompressor_decompressed_16; + _zz_IBusCachedPlugin_decompressor_decompressed_17[3] = _zz_IBusCachedPlugin_decompressor_decompressed_16; + _zz_IBusCachedPlugin_decompressor_decompressed_17[2] = _zz_IBusCachedPlugin_decompressor_decompressed_16; + _zz_IBusCachedPlugin_decompressor_decompressed_17[1] = _zz_IBusCachedPlugin_decompressor_decompressed_16; + _zz_IBusCachedPlugin_decompressor_decompressed_17[0] = _zz_IBusCachedPlugin_decompressor_decompressed_16; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_18 = {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_17,_zz_IBusCachedPlugin_decompressor_decompressed[6 : 5]},_zz_IBusCachedPlugin_decompressor_decompressed[2]},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 10]},_zz_IBusCachedPlugin_decompressor_decompressed[4 : 3]},1'b0}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_19 = 5'h0; + assign _zz_IBusCachedPlugin_decompressor_decompressed_20 = 5'h01; + assign _zz_IBusCachedPlugin_decompressor_decompressed_21 = 5'h02; + assign switch_Misc_l44 = {_zz_IBusCachedPlugin_decompressor_decompressed[1 : 0],_zz_IBusCachedPlugin_decompressor_decompressed[15 : 13]}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_22 = (_zz_IBusCachedPlugin_decompressor_decompressed[11 : 10] != 2'b11); + assign switch_Misc_l200 = _zz_IBusCachedPlugin_decompressor_decompressed[11 : 10]; + assign switch_Misc_l200_1 = _zz_IBusCachedPlugin_decompressor_decompressed[6 : 5]; + always @(*) begin + case(switch_Misc_l200_1) 2'b00 : begin - _zz_87 = 3'b000; + _zz_IBusCachedPlugin_decompressor_decompressed_23 = 3'b000; end 2'b01 : begin - _zz_87 = 3'b100; + _zz_IBusCachedPlugin_decompressor_decompressed_23 = 3'b100; end 2'b10 : begin - _zz_87 = 3'b110; + _zz_IBusCachedPlugin_decompressor_decompressed_23 = 3'b110; end default : begin - _zz_87 = 3'b111; + _zz_IBusCachedPlugin_decompressor_decompressed_23 = 3'b111; end endcase end - always @ (*) begin - case(_zz_265) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - _zz_88 = 3'b101; + _zz_IBusCachedPlugin_decompressor_decompressed_24 = 3'b101; end 2'b01 : begin - _zz_88 = 3'b101; + _zz_IBusCachedPlugin_decompressor_decompressed_24 = 3'b101; end 2'b10 : begin - _zz_88 = 3'b111; + _zz_IBusCachedPlugin_decompressor_decompressed_24 = 3'b111; end default : begin - _zz_88 = _zz_87; + _zz_IBusCachedPlugin_decompressor_decompressed_24 = _zz_IBusCachedPlugin_decompressor_decompressed_23; end endcase end - assign _zz_89 = _zz_64[12]; - always @ (*) begin - _zz_90[6] = _zz_89; - _zz_90[5] = _zz_89; - _zz_90[4] = _zz_89; - _zz_90[3] = _zz_89; - _zz_90[2] = _zz_89; - _zz_90[1] = _zz_89; - _zz_90[0] = _zz_89; + assign _zz_IBusCachedPlugin_decompressor_decompressed_25 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_26[6] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[5] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[4] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[3] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[2] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[1] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[0] = _zz_IBusCachedPlugin_decompressor_decompressed_25; end assign IBusCachedPlugin_decompressor_output_valid = (IBusCachedPlugin_decompressor_input_valid && (! ((IBusCachedPlugin_decompressor_throw2Bytes && (! IBusCachedPlugin_decompressor_bufferValid)) && (! IBusCachedPlugin_decompressor_isInputHighRvc)))); @@ -3299,163 +3487,183 @@ module VexRiscv ( assign IBusCachedPlugin_decompressor_output_payload_isRvc = IBusCachedPlugin_decompressor_isRvc; assign IBusCachedPlugin_decompressor_output_payload_rsp_inst = (IBusCachedPlugin_decompressor_isRvc ? IBusCachedPlugin_decompressor_decompressed : IBusCachedPlugin_decompressor_raw); assign IBusCachedPlugin_decompressor_input_ready = (IBusCachedPlugin_decompressor_output_ready && (((! IBusCachedPlugin_iBusRsp_stages_1_input_valid) || IBusCachedPlugin_decompressor_flushNext) || ((! (IBusCachedPlugin_decompressor_bufferValid && IBusCachedPlugin_decompressor_isInputHighRvc)) && (! (((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && IBusCachedPlugin_decompressor_isInputHighRvc))))); + assign IBusCachedPlugin_decompressor_output_fire = (IBusCachedPlugin_decompressor_output_valid && IBusCachedPlugin_decompressor_output_ready); assign IBusCachedPlugin_decompressor_bufferFill = (((((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && (! IBusCachedPlugin_decompressor_isInputHighRvc)) || (IBusCachedPlugin_decompressor_bufferValid && (! IBusCachedPlugin_decompressor_isInputHighRvc))) || ((IBusCachedPlugin_decompressor_throw2Bytes && (! IBusCachedPlugin_decompressor_isRvc)) && (! IBusCachedPlugin_decompressor_isInputHighRvc))); + assign when_Fetcher_l283 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); + assign when_Fetcher_l286 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); + assign when_Fetcher_l291 = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_decompressor_consumeCurrent); assign IBusCachedPlugin_decompressor_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); - assign IBusCachedPlugin_injector_decodeInput_valid = _zz_91; - assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_92; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_93; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_94; - assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_95; + assign IBusCachedPlugin_injector_decodeInput_valid = _zz_IBusCachedPlugin_injector_decodeInput_valid; + assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; + assign when_Fetcher_l329 = (! 1'b0); + assign when_Fetcher_l329_1 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_2 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; - assign _zz_96 = _zz_308[11]; - always @ (*) begin - _zz_97[18] = _zz_96; - _zz_97[17] = _zz_96; - _zz_97[16] = _zz_96; - _zz_97[15] = _zz_96; - _zz_97[14] = _zz_96; - _zz_97[13] = _zz_96; - _zz_97[12] = _zz_96; - _zz_97[11] = _zz_96; - _zz_97[10] = _zz_96; - _zz_97[9] = _zz_96; - _zz_97[8] = _zz_96; - _zz_97[7] = _zz_96; - _zz_97[6] = _zz_96; - _zz_97[5] = _zz_96; - _zz_97[4] = _zz_96; - _zz_97[3] = _zz_96; - _zz_97[2] = _zz_96; - _zz_97[1] = _zz_96; - _zz_97[0] = _zz_96; - end - - assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_309[31])); + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_98 = _zz_310[19]; - always @ (*) begin - _zz_99[10] = _zz_98; - _zz_99[9] = _zz_98; - _zz_99[8] = _zz_98; - _zz_99[7] = _zz_98; - _zz_99[6] = _zz_98; - _zz_99[5] = _zz_98; - _zz_99[4] = _zz_98; - _zz_99[3] = _zz_98; - _zz_99[2] = _zz_98; - _zz_99[1] = _zz_98; - _zz_99[0] = _zz_98; - end - - assign _zz_100 = _zz_311[11]; - always @ (*) begin - _zz_101[18] = _zz_100; - _zz_101[17] = _zz_100; - _zz_101[16] = _zz_100; - _zz_101[15] = _zz_100; - _zz_101[14] = _zz_100; - _zz_101[13] = _zz_100; - _zz_101[12] = _zz_100; - _zz_101[11] = _zz_100; - _zz_101[10] = _zz_100; - _zz_101[9] = _zz_100; - _zz_101[8] = _zz_100; - _zz_101[7] = _zz_100; - _zz_101[6] = _zz_100; - _zz_101[5] = _zz_100; - _zz_101[4] = _zz_100; - _zz_101[3] = _zz_100; - _zz_101[2] = _zz_100; - _zz_101[1] = _zz_100; - _zz_101[0] = _zz_100; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_99,{{{_zz_386,_zz_387},_zz_388},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_101,{{{_zz_389,_zz_390},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,_zz_IBusCachedPlugin_predictionJumpInterface_payload_5},_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_7,_zz_IBusCachedPlugin_predictionJumpInterface_payload_8},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_196 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_197 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_198 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_197; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_200 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_fetch_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_236)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_234)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_204 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); - if(_zz_234)begin - _zz_204 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_235)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_233)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_235)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_233)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_1_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_fetch_isValid && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_fetch_isValid && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_fetch_isValid && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_fetch_isValid && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_1_output_valid; assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_1_output_payload; - assign _zz_195 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_223 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3463,168 +3671,203 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + always @(*) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + if(when_DBusCachedPlugin_l311) begin + if(decode_MEMORY_LRSC) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b1; + end + end + end + + assign when_DBusCachedPlugin_l311 = decode_INSTRUCTION[25]; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_205 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_206 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_104 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_104 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_104 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_222 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_207 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_208 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_207; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + always @(*) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b0; + if(execute_MEMORY_LRSC) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b1; + end + end + + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_208; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_209 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_209 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_210 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_211 = (CsrPlugin_privilege == 2'b00); - assign _zz_212 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_243)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_243)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_243)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_312}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_313}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + always @(*) begin + writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + if(when_DBusCachedPlugin_l474) begin + writeBack_DBusCachedPlugin_rspRf = {31'd0, _zz_writeBack_DBusCachedPlugin_rspRf}; + end + end + + assign when_DBusCachedPlugin_l474 = (writeBack_MEMORY_LRSC && writeBack_MEMORY_WR); + assign switch_Misc_l200_2 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; end - assign _zz_105 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_106[31] = _zz_105; - _zz_106[30] = _zz_105; - _zz_106[29] = _zz_105; - _zz_106[28] = _zz_105; - _zz_106[27] = _zz_105; - _zz_106[26] = _zz_105; - _zz_106[25] = _zz_105; - _zz_106[24] = _zz_105; - _zz_106[23] = _zz_105; - _zz_106[22] = _zz_105; - _zz_106[21] = _zz_105; - _zz_106[20] = _zz_105; - _zz_106[19] = _zz_105; - _zz_106[18] = _zz_105; - _zz_106[17] = _zz_105; - _zz_106[16] = _zz_105; - _zz_106[15] = _zz_105; - _zz_106[14] = _zz_105; - _zz_106[13] = _zz_105; - _zz_106[12] = _zz_105; - _zz_106[11] = _zz_105; - _zz_106[10] = _zz_105; - _zz_106[9] = _zz_105; - _zz_106[8] = _zz_105; - _zz_106[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_107 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_108[31] = _zz_107; - _zz_108[30] = _zz_107; - _zz_108[29] = _zz_107; - _zz_108[28] = _zz_107; - _zz_108[27] = _zz_107; - _zz_108[26] = _zz_107; - _zz_108[25] = _zz_107; - _zz_108[24] = _zz_107; - _zz_108[23] = _zz_107; - _zz_108[22] = _zz_107; - _zz_108[21] = _zz_107; - _zz_108[20] = _zz_107; - _zz_108[19] = _zz_107; - _zz_108[18] = _zz_107; - _zz_108[17] = _zz_107; - _zz_108[16] = _zz_107; - _zz_108[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_266) + always @(*) begin + case(switch_Misc_l200_2) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_106; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_108; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3643,59 +3886,62 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_110 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_111 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_112 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_113 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_109 = {(_zz_113 != 1'b0),{(_zz_113 != 1'b0),{((_zz_391 == _zz_392) != 1'b0),{(_zz_393 != 1'b0),{(_zz_394 != _zz_395),{_zz_396,{_zz_397,_zz_398}}}}}}}; - assign _zz_114 = _zz_109[2 : 1]; - assign _zz_49 = _zz_114; - assign _zz_115 = _zz_109[7 : 6]; - assign _zz_48 = _zz_115; - assign _zz_116 = _zz_109[9 : 8]; - assign _zz_47 = _zz_116; - assign _zz_117 = _zz_109[19 : 18]; - assign _zz_46 = _zz_117; - assign _zz_118 = _zz_109[22 : 21]; - assign _zz_45 = _zz_118; - assign _zz_119 = _zz_109[24 : 23]; - assign _zz_44 = _zz_119; - assign _zz_120 = _zz_109[27 : 26]; - assign _zz_43 = _zz_120; + assign _zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); + assign _zz_decode_IS_RS2_SIGNED_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_5 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_6 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_IS_RS2_SIGNED = {(_zz_decode_IS_RS2_SIGNED_6 != 1'b0),{(_zz_decode_IS_RS2_SIGNED_6 != 1'b0),{((_zz__zz_decode_IS_RS2_SIGNED == _zz__zz_decode_IS_RS2_SIGNED_1) != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_2 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_3 != _zz__zz_decode_IS_RS2_SIGNED_4),{_zz__zz_decode_IS_RS2_SIGNED_5,{_zz__zz_decode_IS_RS2_SIGNED_7,_zz__zz_decode_IS_RS2_SIGNED_10}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_RS2_SIGNED[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_RS2_SIGNED[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_RS2_SIGNED[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_RS2_SIGNED[21 : 20]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_RS2_SIGNED[23 : 22]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_RS2_SIGNED[25 : 24]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_RS2_SIGNED[28 : 27]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_224; - assign decode_RegFilePlugin_rs2Data = _zz_225; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); - if(_zz_121)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; - if(_zz_121)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_50; - if(_zz_121)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_2) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3704,279 +3950,302 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_122 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_122 = {31'd0, _zz_314}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_122 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_123 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_123 = {29'd0, _zz_315}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_123 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_123 = {27'd0, _zz_316}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_124 = _zz_317[11]; - always @ (*) begin - _zz_125[19] = _zz_124; - _zz_125[18] = _zz_124; - _zz_125[17] = _zz_124; - _zz_125[16] = _zz_124; - _zz_125[15] = _zz_124; - _zz_125[14] = _zz_124; - _zz_125[13] = _zz_124; - _zz_125[12] = _zz_124; - _zz_125[11] = _zz_124; - _zz_125[10] = _zz_124; - _zz_125[9] = _zz_124; - _zz_125[8] = _zz_124; - _zz_125[7] = _zz_124; - _zz_125[6] = _zz_124; - _zz_125[5] = _zz_124; - _zz_125[4] = _zz_124; - _zz_125[3] = _zz_124; - _zz_125[2] = _zz_124; - _zz_125[1] = _zz_124; - _zz_125[0] = _zz_124; - end - - assign _zz_126 = _zz_318[11]; - always @ (*) begin - _zz_127[19] = _zz_126; - _zz_127[18] = _zz_126; - _zz_127[17] = _zz_126; - _zz_127[16] = _zz_126; - _zz_127[15] = _zz_126; - _zz_127[14] = _zz_126; - _zz_127[13] = _zz_126; - _zz_127[12] = _zz_126; - _zz_127[11] = _zz_126; - _zz_127[10] = _zz_126; - _zz_127[9] = _zz_126; - _zz_127[8] = _zz_126; - _zz_127[7] = _zz_126; - _zz_127[6] = _zz_126; - _zz_127[5] = _zz_126; - _zz_127[4] = _zz_126; - _zz_127[3] = _zz_126; - _zz_127[2] = _zz_126; - _zz_127[1] = _zz_126; - _zz_127[0] = _zz_126; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_128 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_128 = {_zz_125,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_128 = {_zz_127,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_128 = _zz_35; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_319; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_129[0] = execute_SRC1[31]; - _zz_129[1] = execute_SRC1[30]; - _zz_129[2] = execute_SRC1[29]; - _zz_129[3] = execute_SRC1[28]; - _zz_129[4] = execute_SRC1[27]; - _zz_129[5] = execute_SRC1[26]; - _zz_129[6] = execute_SRC1[25]; - _zz_129[7] = execute_SRC1[24]; - _zz_129[8] = execute_SRC1[23]; - _zz_129[9] = execute_SRC1[22]; - _zz_129[10] = execute_SRC1[21]; - _zz_129[11] = execute_SRC1[20]; - _zz_129[12] = execute_SRC1[19]; - _zz_129[13] = execute_SRC1[18]; - _zz_129[14] = execute_SRC1[17]; - _zz_129[15] = execute_SRC1[16]; - _zz_129[16] = execute_SRC1[15]; - _zz_129[17] = execute_SRC1[14]; - _zz_129[18] = execute_SRC1[13]; - _zz_129[19] = execute_SRC1[12]; - _zz_129[20] = execute_SRC1[11]; - _zz_129[21] = execute_SRC1[10]; - _zz_129[22] = execute_SRC1[9]; - _zz_129[23] = execute_SRC1[8]; - _zz_129[24] = execute_SRC1[7]; - _zz_129[25] = execute_SRC1[6]; - _zz_129[26] = execute_SRC1[5]; - _zz_129[27] = execute_SRC1[4]; - _zz_129[28] = execute_SRC1[3]; - _zz_129[29] = execute_SRC1[2]; - _zz_129[30] = execute_SRC1[1]; - _zz_129[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_129 : execute_SRC1); - always @ (*) begin - _zz_130[0] = memory_SHIFT_RIGHT[31]; - _zz_130[1] = memory_SHIFT_RIGHT[30]; - _zz_130[2] = memory_SHIFT_RIGHT[29]; - _zz_130[3] = memory_SHIFT_RIGHT[28]; - _zz_130[4] = memory_SHIFT_RIGHT[27]; - _zz_130[5] = memory_SHIFT_RIGHT[26]; - _zz_130[6] = memory_SHIFT_RIGHT[25]; - _zz_130[7] = memory_SHIFT_RIGHT[24]; - _zz_130[8] = memory_SHIFT_RIGHT[23]; - _zz_130[9] = memory_SHIFT_RIGHT[22]; - _zz_130[10] = memory_SHIFT_RIGHT[21]; - _zz_130[11] = memory_SHIFT_RIGHT[20]; - _zz_130[12] = memory_SHIFT_RIGHT[19]; - _zz_130[13] = memory_SHIFT_RIGHT[18]; - _zz_130[14] = memory_SHIFT_RIGHT[17]; - _zz_130[15] = memory_SHIFT_RIGHT[16]; - _zz_130[16] = memory_SHIFT_RIGHT[15]; - _zz_130[17] = memory_SHIFT_RIGHT[14]; - _zz_130[18] = memory_SHIFT_RIGHT[13]; - _zz_130[19] = memory_SHIFT_RIGHT[12]; - _zz_130[20] = memory_SHIFT_RIGHT[11]; - _zz_130[21] = memory_SHIFT_RIGHT[10]; - _zz_130[22] = memory_SHIFT_RIGHT[9]; - _zz_130[23] = memory_SHIFT_RIGHT[8]; - _zz_130[24] = memory_SHIFT_RIGHT[7]; - _zz_130[25] = memory_SHIFT_RIGHT[6]; - _zz_130[26] = memory_SHIFT_RIGHT[5]; - _zz_130[27] = memory_SHIFT_RIGHT[4]; - _zz_130[28] = memory_SHIFT_RIGHT[3]; - _zz_130[29] = memory_SHIFT_RIGHT[2]; - _zz_130[30] = memory_SHIFT_RIGHT[1]; - _zz_130[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_131 = 1'b0; - if(_zz_244)begin - if(_zz_245)begin - if(_zz_136)begin - _zz_131 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_246)begin - if(_zz_247)begin - if(_zz_138)begin - _zz_131 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_248)begin - if(_zz_249)begin - if(_zz_140)begin - _zz_131 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_131 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_132 = 1'b0; - if(_zz_244)begin - if(_zz_245)begin - if(_zz_137)begin - _zz_132 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_246)begin - if(_zz_247)begin - if(_zz_139)begin - _zz_132 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_248)begin - if(_zz_249)begin - if(_zz_141)begin - _zz_132 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_132 = 1'b0; - end - end - - assign _zz_136 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_137 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_138 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_139 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_140 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_141 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_142 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_142 == 3'b000)) begin - _zz_143 = execute_BranchPlugin_eq; - end else if((_zz_142 == 3'b001)) begin - _zz_143 = (! execute_BranchPlugin_eq); - end else if((((_zz_142 & 3'b101) == 3'b101))) begin - _zz_143 = (! execute_SRC_LESS); - end else begin - _zz_143 = execute_SRC_LESS; - end + assign switch_Misc_l200_3 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_3) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_144 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_144 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_144 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_144 = _zz_143; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end assign execute_BranchPlugin_missAlignedTarget = 1'b0; - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -3985,169 +4254,183 @@ module VexRiscv ( endcase end - assign _zz_145 = _zz_326[11]; - always @ (*) begin - _zz_146[19] = _zz_145; - _zz_146[18] = _zz_145; - _zz_146[17] = _zz_145; - _zz_146[16] = _zz_145; - _zz_146[15] = _zz_145; - _zz_146[14] = _zz_145; - _zz_146[13] = _zz_145; - _zz_146[12] = _zz_145; - _zz_146[11] = _zz_145; - _zz_146[10] = _zz_145; - _zz_146[9] = _zz_145; - _zz_146[8] = _zz_145; - _zz_146[7] = _zz_145; - _zz_146[6] = _zz_145; - _zz_146[5] = _zz_145; - _zz_146[4] = _zz_145; - _zz_146[3] = _zz_145; - _zz_146[2] = _zz_145; - _zz_146[1] = _zz_145; - _zz_146[0] = _zz_145; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_146,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_148,{{{_zz_555,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_150,{{{_zz_556,_zz_557},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_329}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_147 = _zz_327[19]; - always @ (*) begin - _zz_148[10] = _zz_147; - _zz_148[9] = _zz_147; - _zz_148[8] = _zz_147; - _zz_148[7] = _zz_147; - _zz_148[6] = _zz_147; - _zz_148[5] = _zz_147; - _zz_148[4] = _zz_147; - _zz_148[3] = _zz_147; - _zz_148[2] = _zz_147; - _zz_148[1] = _zz_147; - _zz_148[0] = _zz_147; - end - - assign _zz_149 = _zz_328[11]; - always @ (*) begin - _zz_150[18] = _zz_149; - _zz_150[17] = _zz_149; - _zz_150[16] = _zz_149; - _zz_150[15] = _zz_149; - _zz_150[14] = _zz_149; - _zz_150[13] = _zz_149; - _zz_150[12] = _zz_149; - _zz_150[11] = _zz_149; - _zz_150[10] = _zz_149; - _zz_150[9] = _zz_149; - _zz_150[8] = _zz_149; - _zz_150[7] = _zz_149; - _zz_150[6] = _zz_149; - _zz_150[5] = _zz_149; - _zz_150[4] = _zz_149; - _zz_150[3] = _zz_149; - _zz_150[2] = _zz_149; - _zz_150[1] = _zz_149; - _zz_150[0] = _zz_149; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_151 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_152 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_153 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_154 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_155 = _zz_330[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_237)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4158,8 +4441,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4169,135 +4452,144 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_250)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_251)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_252)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_251)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_252)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4310,39 +4602,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_250)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_250)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_267) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_4 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_4) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_253) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4355,8 +4657,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_253) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4375,79 +4677,154 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_332) + $signed(_zz_333)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_232)begin - if(_zz_254)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_255)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_337); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_156 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_156[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_338); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_339 : _zz_340); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_341[31:0]; - assign _zz_157 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_158 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_159 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_160[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_160[31 : 0] = execute_RS1; - end - - assign _zz_162 = (_zz_161 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_162 != 32'h0); - assign _zz_26 = decode_SRC1_CTRL; - assign _zz_24 = _zz_49; - assign _zz_37 = decode_to_execute_SRC1_CTRL; - assign _zz_23 = decode_ALU_CTRL; - assign _zz_21 = _zz_48; - assign _zz_38 = decode_to_execute_ALU_CTRL; - assign _zz_20 = decode_SRC2_CTRL; - assign _zz_18 = _zz_47; - assign _zz_36 = decode_to_execute_SRC2_CTRL; - assign _zz_17 = decode_ALU_BITWISE_CTRL; - assign _zz_15 = _zz_46; - assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_14 = decode_SHIFT_CTRL; - assign _zz_11 = execute_SHIFT_CTRL; - assign _zz_12 = _zz_45; - assign _zz_34 = decode_to_execute_SHIFT_CTRL; - assign _zz_33 = execute_to_memory_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_51 = _zz_44; - assign _zz_30 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_43; - assign _zz_28 = decode_to_execute_ENV_CTRL; - assign _zz_27 = execute_to_memory_ENV_CTRL; - assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_15 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_29 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_64 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_65 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4468,242 +4845,275 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_163 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_163[12 : 0] = 13'h1000; - _zz_163[25 : 20] = 6'h20; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_164 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_164[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_165 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_165[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_166 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_166[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_167 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_167[31 : 30] = CsrPlugin_misa_base; - _zz_167[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_168 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_168[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_168[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_168[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_169 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_169[11 : 11] = CsrPlugin_mip_MEIP; - _zz_169[7 : 7] = CsrPlugin_mip_MTIP; - _zz_169[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_170 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_170[11 : 11] = CsrPlugin_mie_MEIE; - _zz_170[7 : 7] = CsrPlugin_mie_MTIE; - _zz_170[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_171 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_171[31 : 2] = CsrPlugin_mtvec_base; - _zz_171[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_172 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_172[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_173 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_173[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_174 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_174[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_174[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_175 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_175[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_176 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_176[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_177 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_177[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_178 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_178[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_179 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_179[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_180[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_181[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_182[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_183[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_184[31 : 0] = _zz_161; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_185[31 : 0] = _zz_162; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = (((((_zz_163 | _zz_164) | (_zz_165 | _zz_166)) | ((_zz_558 | _zz_167) | (_zz_168 | _zz_169))) | (((_zz_170 | _zz_171) | (_zz_172 | _zz_173)) | ((_zz_174 | _zz_175) | (_zz_176 | _zz_177)))) | (((_zz_178 | _zz_179) | (_zz_180 | _zz_181)) | ((_zz_182 | _zz_183) | (_zz_184 | _zz_185)))); - assign iBusWishbone_ADR = {_zz_358,_zz_186}; - assign iBusWishbone_CTI = ((_zz_186 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_256)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_256)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_187; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_193 = (dBus_cmd_payload_length != 3'b000); - assign _zz_189 = dBus_cmd_valid; - assign _zz_191 = dBus_cmd_payload_wr; - assign _zz_192 = (_zz_188 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_190 && (_zz_191 || _zz_192)); - assign dBusWishbone_ADR = ((_zz_193 ? {{dBus_cmd_payload_address[31 : 5],_zz_188},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_193 ? (_zz_192 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_191 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_191; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_190 = (_zz_189 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_189; - assign dBusWishbone_STB = _zz_189; - assign dBus_rsp_valid = _zz_194; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; IBusCachedPlugin_decodePc_pcReg <= externalResetVector; - _zz_63 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; IBusCachedPlugin_decompressor_bufferValid <= 1'b0; IBusCachedPlugin_decompressor_throw2BytesReg <= 1'b0; - _zz_91 <= 1'b0; + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_102; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_103; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_121 <= 1'b1; - _zz_133 <= 1'b0; + _zz_2 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4724,162 +5134,162 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_161 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_186 <= 3'b000; - _zz_187 <= 1'b0; - _zz_188 <= 3'b000; - _zz_194 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if((decode_arbitration_isFiring && (! IBusCachedPlugin_decodePc_injectedDecode)))begin + if(when_Fetcher_l180) begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_decodePc_pcPlus; end - if(_zz_242)begin + if(when_Fetcher_l192) begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_jump_pcLoad_payload; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_63 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_61)begin - _zz_63 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if((IBusCachedPlugin_decompressor_output_valid && IBusCachedPlugin_decompressor_output_ready))begin + if(IBusCachedPlugin_decompressor_output_fire) begin IBusCachedPlugin_decompressor_throw2BytesReg <= ((((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && IBusCachedPlugin_decompressor_isInputHighRvc) || (IBusCachedPlugin_decompressor_bufferValid && IBusCachedPlugin_decompressor_isInputHighRvc)); end - if((IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid))begin + if(when_Fetcher_l283) begin IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end - if(_zz_257)begin - if(IBusCachedPlugin_decompressor_bufferFill)begin + if(when_Fetcher_l286) begin + if(IBusCachedPlugin_decompressor_bufferFill) begin IBusCachedPlugin_decompressor_bufferValid <= 1'b1; end end - if((IBusCachedPlugin_externalFlush || IBusCachedPlugin_decompressor_consumeCurrent))begin + if(when_Fetcher_l291) begin IBusCachedPlugin_decompressor_throw2BytesReg <= 1'b0; IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end - if(decode_arbitration_removeIt)begin - _zz_91 <= 1'b0; + if(decode_arbitration_removeIt) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; end - if(IBusCachedPlugin_decompressor_output_ready)begin - _zz_91 <= (IBusCachedPlugin_decompressor_output_valid && (! IBusCachedPlugin_externalFlush)); + if(IBusCachedPlugin_decompressor_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= (IBusCachedPlugin_decompressor_output_valid && (! IBusCachedPlugin_externalFlush)); end - if((! 1'b0))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_decodePc_flushed)begin + if(IBusCachedPlugin_decodePc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_decodePc_flushed)begin + if(IBusCachedPlugin_decodePc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_decodePc_flushed)begin + if(IBusCachedPlugin_decodePc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_decodePc_flushed)begin + if(IBusCachedPlugin_decodePc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_258)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_121 <= 1'b0; - _zz_133 <= (_zz_41 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_2 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_259)begin - if(_zz_260)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_261)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_262)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_239)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4890,8 +5300,8 @@ module VexRiscv ( end endcase end - if(_zz_240)begin - case(_zz_241) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4901,143 +5311,149 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_153,{_zz_152,_zz_151}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_351[0]; - CsrPlugin_mstatus_MIE <= _zz_352[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_354[0]; - CsrPlugin_mie_MTIE <= _zz_355[0]; - CsrPlugin_mie_MSIE <= _zz_356[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_256)begin - if(iBusWishbone_ACK)begin - _zz_186 <= (_zz_186 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_187 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_189 && _zz_190))begin - _zz_188 <= (_zz_188 + 3'b001); - if(_zz_192)begin - _zz_188 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_194 <= ((_zz_189 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(_zz_257)begin + always @(posedge clk) begin + if(IBusCachedPlugin_decompressor_input_valid) begin + IBusCachedPlugin_decompressor_bufferValidLatch <= IBusCachedPlugin_decompressor_bufferValid; + end + if(IBusCachedPlugin_decompressor_input_valid) begin + IBusCachedPlugin_decompressor_throw2BytesLatch <= IBusCachedPlugin_decompressor_throw2Bytes; + end + if(when_Fetcher_l286) begin IBusCachedPlugin_decompressor_bufferData <= IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16]; end - if(IBusCachedPlugin_decompressor_output_ready)begin - _zz_92 <= IBusCachedPlugin_decompressor_output_payload_pc; - _zz_93 <= IBusCachedPlugin_decompressor_output_payload_rsp_error; - _zz_94 <= IBusCachedPlugin_decompressor_output_payload_rsp_inst; - _zz_95 <= IBusCachedPlugin_decompressor_output_payload_isRvc; + if(IBusCachedPlugin_decompressor_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_pc <= IBusCachedPlugin_decompressor_output_payload_pc; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error <= IBusCachedPlugin_decompressor_output_payload_rsp_error; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_decompressor_output_payload_rsp_inst; + _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc <= IBusCachedPlugin_decompressor_output_payload_isRvc; end - if(IBusCachedPlugin_injector_decodeInput_ready)begin + if(IBusCachedPlugin_injector_decodeInput_ready) begin IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_decompressor_raw; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(_zz_258)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_134 <= _zz_40[11 : 7]; - _zz_135 <= _zz_50; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_237)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_155 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_155 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_259)begin - if(_zz_260)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_261)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_262)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_239)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5045,339 +5461,348 @@ module VexRiscv ( end endcase end - if((memory_DivPlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_DivPlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_232)begin - if(_zz_254)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_342[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; end end end - if(_zz_255)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_159 ? (~ _zz_160) : _zz_160) + _zz_348); - memory_DivPlugin_rs2 <= ((_zz_158 ? (~ execute_RS2) : execute_RS2) + _zz_350); - memory_DivPlugin_div_needRevert <= ((_zz_159 ^ (_zz_158 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_35; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_6) begin decode_to_execute_IS_RVC <= decode_IS_RVC; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + if(when_Pipeline_l124_7) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_8) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + if(when_Pipeline_l124_9) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_10) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_25; + if(when_Pipeline_l124_11) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_15) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_22; + if(when_Pipeline_l124_16) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_19; + if(when_Pipeline_l124_17) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin + decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; + end + if(when_Pipeline_l124_28) begin + execute_to_memory_MEMORY_LRSC <= execute_MEMORY_LRSC; + end + if(when_Pipeline_l124_29) begin + memory_to_writeBack_MEMORY_LRSC <= memory_MEMORY_LRSC; + end + if(when_Pipeline_l124_30) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_31) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + if(when_Pipeline_l124_32) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_33) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_10; + if(when_Pipeline_l124_34) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + if(when_Pipeline_l124_35) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_37) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_38) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_39) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_52) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_53) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_54) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + if(when_Pipeline_l124_55) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + if(when_Pipeline_l124_56) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_62) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_63) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_64) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_65) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_353[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_357[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -5390,10 +5815,10 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_isLrsc, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, input io_cpu_memory_isValid, @@ -5414,6 +5839,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -5429,9 +5855,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -5439,7 +5866,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -5448,24 +5875,15 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -5490,40 +5908,50 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; + reg stageA_request_isLrsc; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; + reg stageB_request_isLrsc; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5533,34 +5961,56 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; + reg stageB_lrSc_reserved; + wire when_DataCache_l866; wire stageB_isAmo; wire stageB_isAmoCached; wire stageB_isExternalLsrc; wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l984; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1010; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -5572,59 +6022,54 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -5639,274 +6084,311 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1010) begin + dataWriteCmd_valid = 1'b0; + end + end + end + end + end + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(when_DataCache_l984) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(when_DataCache_l1010) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); + assign when_DataCache_l866 = ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -5914,89 +6396,79 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); + if(when_DataCache_l984) begin + io_mem_cmd_valid = 1'b0; + end end else begin - if(_zz_16)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end + if(when_DataCache_l1010) begin + io_mem_cmd_valid = 1'b0; + end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6004,12 +6476,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6020,20 +6492,43 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l984 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1010 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign io_cpu_writeBack_exclusiveOk = stageB_lrSc_reserved; + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6041,45 +6536,49 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; + stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; + stageB_request_isLrsc <= stageA_request_isLrsc; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6090,97 +6589,96 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; + stageB_lrSc_reserved <= 1'b0; loader_valid <= 1'b0; loader_counter_value <= 3'b000; loader_waysAllocator <= 1'b1; loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; + end + if(when_DataCache_l866) begin + stageB_lrSc_reserved <= (! stageB_request_wr); + end + if(when_DataCache_l1051) begin + stageB_lrSc_reserved <= stageB_lrSc_reserved; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6230,13 +6728,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [21:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [21:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6245,8 +6739,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -6260,16 +6759,17 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; @@ -6278,77 +6778,78 @@ module InstructionCache ( (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - assign _zz_11 = (! lineLoader_flushCounter[7]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -6364,16 +6865,17 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; @@ -6385,7 +6887,7 @@ module InstructionCache ( assign io_cpu_fetch_error = (fetchStage_hit_error || ((! io_cpu_fetch_mmuRsp_isPaging) && (io_cpu_fetch_mmuRsp_exception || (! io_cpu_fetch_mmuRsp_allowExecute)))); assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuRsp_refilling; assign io_cpu_fetch_mmuException = (((! io_cpu_fetch_mmuRsp_refilling) && io_cpu_fetch_mmuRsp_isPaging) && (io_cpu_fetch_mmuRsp_exception || (! io_cpu_fetch_mmuRsp_allowExecute))); - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -6393,45 +6895,45 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 8'h0; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v index c0e4bb3..04c18ce 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v @@ -1,47 +1,47 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 - - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -82,38 +82,39 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - wire _zz_204; - wire _zz_205; - wire _zz_206; - wire [31:0] _zz_207; - reg _zz_208; - wire _zz_209; - wire [31:0] _zz_210; - wire _zz_211; - wire [31:0] _zz_212; - reg _zz_213; - wire _zz_214; - wire _zz_215; - wire [31:0] _zz_216; - wire _zz_217; - wire _zz_218; - wire _zz_219; - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - wire [3:0] _zz_225; - wire _zz_226; - wire _zz_227; - reg [31:0] _zz_228; - reg [31:0] _zz_229; - reg [31:0] _zz_230; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_fetch_isUser; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_pc; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + reg dataCache_1_io_cpu_execute_args_isLrsc; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire IBusCachedPlugin_cache_io_cpu_fetch_error; wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; @@ -136,6 +137,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -144,345 +146,304 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire _zz_245; - wire _zz_246; - wire _zz_247; - wire [1:0] _zz_248; - wire _zz_249; - wire _zz_250; - wire _zz_251; - wire _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire _zz_256; - wire _zz_257; - wire _zz_258; - wire _zz_259; - wire [1:0] _zz_260; - wire _zz_261; - wire _zz_262; - wire [5:0] _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire _zz_267; - wire _zz_268; - wire _zz_269; - wire _zz_270; - wire [4:0] _zz_271; - wire [1:0] _zz_272; - wire [1:0] _zz_273; - wire [1:0] _zz_274; - wire _zz_275; - wire [1:0] _zz_276; - wire [51:0] _zz_277; - wire [51:0] _zz_278; - wire [51:0] _zz_279; - wire [32:0] _zz_280; - wire [51:0] _zz_281; - wire [49:0] _zz_282; - wire [51:0] _zz_283; - wire [49:0] _zz_284; - wire [51:0] _zz_285; - wire [32:0] _zz_286; - wire [31:0] _zz_287; - wire [32:0] _zz_288; - wire [0:0] _zz_289; - wire [0:0] _zz_290; - wire [0:0] _zz_291; - wire [0:0] _zz_292; - wire [0:0] _zz_293; - wire [0:0] _zz_294; - wire [0:0] _zz_295; - wire [0:0] _zz_296; - wire [0:0] _zz_297; - wire [0:0] _zz_298; - wire [2:0] _zz_299; - wire [31:0] _zz_300; - wire [0:0] _zz_301; - wire [0:0] _zz_302; - wire [0:0] _zz_303; - wire [0:0] _zz_304; - wire [0:0] _zz_305; - wire [0:0] _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire [3:0] _zz_309; - wire [2:0] _zz_310; - wire [31:0] _zz_311; - wire [2:0] _zz_312; - wire [31:0] _zz_313; - wire [31:0] _zz_314; - wire [11:0] _zz_315; - wire [11:0] _zz_316; - wire [11:0] _zz_317; - wire [31:0] _zz_318; - wire [19:0] _zz_319; - wire [11:0] _zz_320; - wire [2:0] _zz_321; - wire [2:0] _zz_322; - wire [0:0] _zz_323; - wire [2:0] _zz_324; - wire [4:0] _zz_325; - wire [11:0] _zz_326; - wire [11:0] _zz_327; - wire [31:0] _zz_328; - wire [31:0] _zz_329; - wire [31:0] _zz_330; - wire [31:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [31:0] _zz_334; - wire [11:0] _zz_335; - wire [19:0] _zz_336; - wire [11:0] _zz_337; - wire [2:0] _zz_338; - wire [1:0] _zz_339; - wire [1:0] _zz_340; - wire [65:0] _zz_341; - wire [65:0] _zz_342; - wire [31:0] _zz_343; - wire [31:0] _zz_344; - wire [0:0] _zz_345; - wire [5:0] _zz_346; - wire [32:0] _zz_347; - wire [31:0] _zz_348; - wire [31:0] _zz_349; - wire [32:0] _zz_350; - wire [32:0] _zz_351; - wire [32:0] _zz_352; - wire [32:0] _zz_353; - wire [0:0] _zz_354; - wire [32:0] _zz_355; - wire [0:0] _zz_356; - wire [32:0] _zz_357; - wire [0:0] _zz_358; - wire [31:0] _zz_359; - wire [0:0] _zz_360; - wire [0:0] _zz_361; - wire [0:0] _zz_362; - wire [0:0] _zz_363; - wire [0:0] _zz_364; - wire [0:0] _zz_365; - wire [0:0] _zz_366; - wire [26:0] _zz_367; - wire _zz_368; - wire _zz_369; - wire [1:0] _zz_370; - wire [31:0] _zz_371; - wire [31:0] _zz_372; - wire [31:0] _zz_373; - wire _zz_374; - wire [0:0] _zz_375; - wire [13:0] _zz_376; - wire [31:0] _zz_377; - wire [31:0] _zz_378; - wire [31:0] _zz_379; - wire _zz_380; - wire [0:0] _zz_381; - wire [7:0] _zz_382; - wire [31:0] _zz_383; - wire [31:0] _zz_384; - wire [31:0] _zz_385; - wire _zz_386; - wire [0:0] _zz_387; - wire [1:0] _zz_388; - wire _zz_389; - wire _zz_390; - wire [6:0] _zz_391; - wire [4:0] _zz_392; - wire _zz_393; - wire [4:0] _zz_394; - wire [0:0] _zz_395; - wire [7:0] _zz_396; - wire _zz_397; - wire [0:0] _zz_398; - wire [0:0] _zz_399; - wire [31:0] _zz_400; - wire [0:0] _zz_401; - wire [0:0] _zz_402; - wire _zz_403; - wire [0:0] _zz_404; - wire [26:0] _zz_405; - wire [31:0] _zz_406; - wire _zz_407; - wire _zz_408; - wire _zz_409; - wire [1:0] _zz_410; - wire [1:0] _zz_411; - wire _zz_412; - wire [0:0] _zz_413; - wire [22:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; - wire [31:0] _zz_418; - wire _zz_419; - wire _zz_420; - wire [1:0] _zz_421; - wire [1:0] _zz_422; - wire _zz_423; - wire [0:0] _zz_424; - wire [19:0] _zz_425; - wire [31:0] _zz_426; - wire [31:0] _zz_427; - wire [31:0] _zz_428; - wire [31:0] _zz_429; - wire _zz_430; - wire [0:0] _zz_431; - wire [0:0] _zz_432; - wire _zz_433; - wire [0:0] _zz_434; - wire [0:0] _zz_435; - wire _zz_436; - wire [0:0] _zz_437; - wire [16:0] _zz_438; - wire [31:0] _zz_439; - wire [31:0] _zz_440; - wire [31:0] _zz_441; - wire [31:0] _zz_442; - wire [31:0] _zz_443; - wire [0:0] _zz_444; - wire [0:0] _zz_445; - wire [0:0] _zz_446; - wire [0:0] _zz_447; - wire _zz_448; - wire [0:0] _zz_449; - wire [13:0] _zz_450; - wire [31:0] _zz_451; - wire [31:0] _zz_452; - wire [31:0] _zz_453; - wire _zz_454; - wire _zz_455; - wire [0:0] _zz_456; - wire [3:0] _zz_457; - wire [0:0] _zz_458; - wire [0:0] _zz_459; - wire _zz_460; - wire [0:0] _zz_461; - wire [10:0] _zz_462; - wire [31:0] _zz_463; - wire [31:0] _zz_464; - wire [31:0] _zz_465; - wire _zz_466; - wire [0:0] _zz_467; - wire [0:0] _zz_468; - wire [31:0] _zz_469; - wire _zz_470; - wire [0:0] _zz_471; - wire [2:0] _zz_472; - wire [0:0] _zz_473; - wire [3:0] _zz_474; - wire [5:0] _zz_475; - wire [5:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [7:0] _zz_479; - wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire [31:0] _zz_485; - wire _zz_486; - wire [0:0] _zz_487; - wire [0:0] _zz_488; - wire _zz_489; - wire [0:0] _zz_490; - wire [1:0] _zz_491; - wire [0:0] _zz_492; - wire [3:0] _zz_493; - wire [0:0] _zz_494; - wire [0:0] _zz_495; - wire [1:0] _zz_496; - wire [1:0] _zz_497; - wire _zz_498; - wire [0:0] _zz_499; - wire [5:0] _zz_500; - wire [31:0] _zz_501; - wire [31:0] _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire [31:0] _zz_505; - wire [31:0] _zz_506; - wire [31:0] _zz_507; - wire [31:0] _zz_508; - wire _zz_509; - wire _zz_510; - wire [31:0] _zz_511; - wire [31:0] _zz_512; - wire _zz_513; - wire [0:0] _zz_514; - wire [1:0] _zz_515; - wire [31:0] _zz_516; - wire [31:0] _zz_517; - wire _zz_518; - wire _zz_519; - wire [0:0] _zz_520; - wire [0:0] _zz_521; - wire _zz_522; - wire [0:0] _zz_523; - wire [3:0] _zz_524; - wire [31:0] _zz_525; - wire [31:0] _zz_526; - wire [31:0] _zz_527; - wire [31:0] _zz_528; - wire [31:0] _zz_529; - wire _zz_530; - wire _zz_531; - wire [31:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire [31:0] _zz_535; - wire [0:0] _zz_536; - wire [2:0] _zz_537; - wire [0:0] _zz_538; - wire [0:0] _zz_539; - wire _zz_540; - wire [0:0] _zz_541; - wire [1:0] _zz_542; - wire [31:0] _zz_543; - wire [31:0] _zz_544; - wire [31:0] _zz_545; - wire _zz_546; - wire _zz_547; - wire [31:0] _zz_548; - wire _zz_549; - wire [0:0] _zz_550; - wire [0:0] _zz_551; - wire [0:0] _zz_552; - wire [0:0] _zz_553; - wire [1:0] _zz_554; - wire [1:0] _zz_555; - wire [0:0] _zz_556; - wire [0:0] _zz_557; - wire [31:0] _zz_558; - wire [31:0] _zz_559; - wire [31:0] _zz_560; - wire [31:0] _zz_561; - wire [31:0] _zz_562; - wire [31:0] _zz_563; - wire _zz_564; - wire _zz_565; - wire _zz_566; - wire [31:0] _zz_567; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_FORMAL_PC_NEXT; + wire [2:0] _zz_decode_FORMAL_PC_NEXT_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [15:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [9:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [3:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [31:0] _zz_IBusCachedPlugin_decodePc_pcPlus; + wire [2:0] _zz_IBusCachedPlugin_decodePc_pcPlus_1; + wire [31:0] _zz_IBusCachedPlugin_decompressor_decompressed_27; + wire _zz_IBusCachedPlugin_decompressor_decompressed_28; + wire _zz_IBusCachedPlugin_decompressor_decompressed_29; + wire [6:0] _zz_IBusCachedPlugin_decompressor_decompressed_30; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_31; + wire _zz_IBusCachedPlugin_decompressor_decompressed_32; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_33; + wire [11:0] _zz_IBusCachedPlugin_decompressor_decompressed_34; + wire [11:0] _zz_IBusCachedPlugin_decompressor_decompressed_35; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire [0:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire [7:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [0:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_7; + wire [0:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_8; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspRf; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_1; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_2; + wire _zz__zz_decode_IS_RS2_SIGNED_3; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_4; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_5; + wire _zz__zz_decode_IS_RS2_SIGNED_6; + wire _zz__zz_decode_IS_RS2_SIGNED_7; + wire [27:0] _zz__zz_decode_IS_RS2_SIGNED_8; + wire _zz__zz_decode_IS_RS2_SIGNED_9; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_10; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_11; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_12; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_13; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_14; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_15; + wire _zz__zz_decode_IS_RS2_SIGNED_16; + wire _zz__zz_decode_IS_RS2_SIGNED_17; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_18; + wire _zz__zz_decode_IS_RS2_SIGNED_19; + wire [23:0] _zz__zz_decode_IS_RS2_SIGNED_20; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_21; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_22; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_23; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_24; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_25; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_26; + wire _zz__zz_decode_IS_RS2_SIGNED_27; + wire _zz__zz_decode_IS_RS2_SIGNED_28; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_29; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_30; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_31; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_32; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_33; + wire _zz__zz_decode_IS_RS2_SIGNED_34; + wire [20:0] _zz__zz_decode_IS_RS2_SIGNED_35; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_36; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_37; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_38; + wire _zz__zz_decode_IS_RS2_SIGNED_39; + wire _zz__zz_decode_IS_RS2_SIGNED_40; + wire _zz__zz_decode_IS_RS2_SIGNED_41; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_42; + wire _zz__zz_decode_IS_RS2_SIGNED_43; + wire [17:0] _zz__zz_decode_IS_RS2_SIGNED_44; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_45; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_46; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_47; + wire _zz__zz_decode_IS_RS2_SIGNED_48; + wire _zz__zz_decode_IS_RS2_SIGNED_49; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_50; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_51; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_52; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_53; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_54; + wire _zz__zz_decode_IS_RS2_SIGNED_55; + wire [14:0] _zz__zz_decode_IS_RS2_SIGNED_56; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_57; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_58; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_59; + wire _zz__zz_decode_IS_RS2_SIGNED_60; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_61; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_62; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_63; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_64; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_65; + wire _zz__zz_decode_IS_RS2_SIGNED_66; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_67; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_68; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_69; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_70; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_71; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_72; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_73; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_74; + wire _zz__zz_decode_IS_RS2_SIGNED_75; + wire _zz__zz_decode_IS_RS2_SIGNED_76; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_77; + wire _zz__zz_decode_IS_RS2_SIGNED_78; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_79; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_80; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_81; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_82; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_83; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_84; + wire _zz__zz_decode_IS_RS2_SIGNED_85; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_86; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_87; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_88; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_89; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_90; + wire _zz__zz_decode_IS_RS2_SIGNED_91; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_92; + wire [11:0] _zz__zz_decode_IS_RS2_SIGNED_93; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_94; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_95; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_96; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_97; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_98; + wire _zz__zz_decode_IS_RS2_SIGNED_99; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_100; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_101; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_102; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_103; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_104; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_105; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_106; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_107; + wire _zz__zz_decode_IS_RS2_SIGNED_108; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_109; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_110; + wire _zz__zz_decode_IS_RS2_SIGNED_111; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_112; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_113; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_114; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_115; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_116; + wire _zz__zz_decode_IS_RS2_SIGNED_117; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_118; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_119; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_120; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_121; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_122; + wire _zz__zz_decode_IS_RS2_SIGNED_123; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_124; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_125; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_126; + wire _zz__zz_decode_IS_RS2_SIGNED_127; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_128; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_129; + wire [8:0] _zz__zz_decode_IS_RS2_SIGNED_130; + wire _zz__zz_decode_IS_RS2_SIGNED_131; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_132; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_133; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_134; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_135; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_136; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_137; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_138; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_139; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_140; + wire [6:0] _zz__zz_decode_IS_RS2_SIGNED_141; + wire _zz__zz_decode_IS_RS2_SIGNED_142; + wire _zz__zz_decode_IS_RS2_SIGNED_143; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_144; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_145; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_146; + wire _zz__zz_decode_IS_RS2_SIGNED_147; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_148; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_149; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_150; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_151; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_152; + wire _zz__zz_decode_IS_RS2_SIGNED_153; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_154; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_155; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_156; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_157; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_158; + wire _zz__zz_decode_IS_RS2_SIGNED_159; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_160; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_161; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_162; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_163; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_164; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_165; + wire _zz__zz_decode_IS_RS2_SIGNED_166; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_167; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_168; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_169; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_170; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_171; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_172; + wire _zz__zz_decode_IS_RS2_SIGNED_173; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_174; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_175; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_176; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_177; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_178; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_179; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_180; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_181; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_182; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_183; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_184; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_185; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_186; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -493,8 +454,8 @@ module VexRiscv ( wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_DO_EBREAK; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; @@ -506,46 +467,47 @@ module VexRiscv ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_LRSC; wire memory_MEMORY_WR; wire decode_MEMORY_WR; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; @@ -567,23 +529,23 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; wire execute_PREDICTION_HAD_BRANCHED2; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_31; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -593,50 +555,52 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_32; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_35; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_36; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; wire execute_IS_RVC; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; - wire [31:0] _zz_40; - wire _zz_41; - reg _zz_42; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_43; - wire `BranchCtrlEnum_defaultEncoding_type _zz_44; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; - wire `Src2CtrlEnum_defaultEncoding_type _zz_47; - wire `AluCtrlEnum_defaultEncoding_type _zz_48; - wire `Src1CtrlEnum_defaultEncoding_type _zz_49; - reg [31:0] _zz_50; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_LRSC; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_ENABLE; + wire execute_MEMORY_LRSC; wire execute_MEMORY_FORCE_CONSTISTENCY; wire execute_MEMORY_MANAGMENT; (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; @@ -644,16 +608,18 @@ module VexRiscv ( wire [31:0] execute_SRC_ADD; wire execute_MEMORY_ENABLE; wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_LRSC; + reg _zz_decode_MEMORY_FORCE_CONSTISTENCY; wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_4; reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; - reg [31:0] _zz_52; - reg [31:0] _zz_53; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] decode_INSTRUCTION; wire decode_IS_RVC; @@ -742,7 +708,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -768,12 +734,17 @@ module VexRiscv ( reg DBusCachedPlugin_exceptionBus_valid; reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_54; + reg _zz_when_DBusCachedPlugin_l386; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; wire BranchPlugin_jumpInterface_valid; wire [31:0] BranchPlugin_jumpInterface_payload; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -791,35 +762,43 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; reg CsrPlugin_allowInterrupts; reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; reg IBusCachedPlugin_injectionPort_valid; reg IBusCachedPlugin_injectionPort_ready; wire [31:0] IBusCachedPlugin_injectionPort_payload; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_55; - wire [3:0] _zz_56; - wire _zz_57; - wire _zz_58; - wire _zz_59; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; reg [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_decodePc_flushed; reg [31:0] IBusCachedPlugin_decodePc_pcReg /* verilator public */ ; wire [31:0] IBusCachedPlugin_decodePc_pcPlus; reg IBusCachedPlugin_decodePc_injectedDecode; + wire when_Fetcher_l180; + wire when_Fetcher_l192; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -835,12 +814,12 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; reg IBusCachedPlugin_iBusRsp_stages_1_halt; - wire _zz_60; - wire _zz_61; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_62; - wire _zz_63; - reg _zz_64; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -869,59 +848,74 @@ module VexRiscv ( reg IBusCachedPlugin_decompressor_throw2BytesReg; wire IBusCachedPlugin_decompressor_throw2Bytes; wire IBusCachedPlugin_decompressor_unaligned; + reg IBusCachedPlugin_decompressor_bufferValidLatch; + reg IBusCachedPlugin_decompressor_throw2BytesLatch; + wire IBusCachedPlugin_decompressor_bufferValidPatched; + wire IBusCachedPlugin_decompressor_throw2BytesPatched; wire [31:0] IBusCachedPlugin_decompressor_raw; wire IBusCachedPlugin_decompressor_isRvc; - wire [15:0] _zz_65; + wire [15:0] _zz_IBusCachedPlugin_decompressor_decompressed; reg [31:0] IBusCachedPlugin_decompressor_decompressed; - wire [4:0] _zz_66; - wire [4:0] _zz_67; - wire [11:0] _zz_68; - wire _zz_69; - reg [11:0] _zz_70; - wire _zz_71; - reg [9:0] _zz_72; - wire [20:0] _zz_73; - wire _zz_74; - reg [14:0] _zz_75; - wire _zz_76; - reg [2:0] _zz_77; - wire _zz_78; - reg [9:0] _zz_79; - wire [20:0] _zz_80; - wire _zz_81; - reg [4:0] _zz_82; - wire [12:0] _zz_83; - wire [4:0] _zz_84; - wire [4:0] _zz_85; - wire [4:0] _zz_86; - wire _zz_87; - reg [2:0] _zz_88; - reg [2:0] _zz_89; - wire _zz_90; - reg [6:0] _zz_91; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_1; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_2; + wire [11:0] _zz_IBusCachedPlugin_decompressor_decompressed_3; + wire _zz_IBusCachedPlugin_decompressor_decompressed_4; + reg [11:0] _zz_IBusCachedPlugin_decompressor_decompressed_5; + wire _zz_IBusCachedPlugin_decompressor_decompressed_6; + reg [9:0] _zz_IBusCachedPlugin_decompressor_decompressed_7; + wire [20:0] _zz_IBusCachedPlugin_decompressor_decompressed_8; + wire _zz_IBusCachedPlugin_decompressor_decompressed_9; + reg [14:0] _zz_IBusCachedPlugin_decompressor_decompressed_10; + wire _zz_IBusCachedPlugin_decompressor_decompressed_11; + reg [2:0] _zz_IBusCachedPlugin_decompressor_decompressed_12; + wire _zz_IBusCachedPlugin_decompressor_decompressed_13; + reg [9:0] _zz_IBusCachedPlugin_decompressor_decompressed_14; + wire [20:0] _zz_IBusCachedPlugin_decompressor_decompressed_15; + wire _zz_IBusCachedPlugin_decompressor_decompressed_16; + reg [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_17; + wire [12:0] _zz_IBusCachedPlugin_decompressor_decompressed_18; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_19; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_20; + wire [4:0] _zz_IBusCachedPlugin_decompressor_decompressed_21; + wire [4:0] switch_Misc_l44; + wire _zz_IBusCachedPlugin_decompressor_decompressed_22; + wire [1:0] switch_Misc_l200; + wire [1:0] switch_Misc_l200_1; + reg [2:0] _zz_IBusCachedPlugin_decompressor_decompressed_23; + reg [2:0] _zz_IBusCachedPlugin_decompressor_decompressed_24; + wire _zz_IBusCachedPlugin_decompressor_decompressed_25; + reg [6:0] _zz_IBusCachedPlugin_decompressor_decompressed_26; + wire IBusCachedPlugin_decompressor_output_fire; wire IBusCachedPlugin_decompressor_bufferFill; + wire when_Fetcher_l283; + wire when_Fetcher_l286; + wire when_Fetcher_l291; wire IBusCachedPlugin_injector_decodeInput_valid; wire IBusCachedPlugin_injector_decodeInput_ready; wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_pc; wire IBusCachedPlugin_injector_decodeInput_payload_rsp_error; wire [31:0] IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; wire IBusCachedPlugin_injector_decodeInput_payload_isRvc; - reg _zz_92; - reg [31:0] _zz_93; - reg _zz_94; - reg [31:0] _zz_95; - reg _zz_96; + reg _zz_IBusCachedPlugin_injector_decodeInput_valid; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + reg [31:0] _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + reg _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg [31:0] IBusCachedPlugin_injector_formal_rawInDecode; - wire _zz_97; - reg [18:0] _zz_98; - wire _zz_99; - reg [10:0] _zz_100; - wire _zz_101; - reg [18:0] _zz_102; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -929,30 +923,35 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_103; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -960,38 +959,58 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_104; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; + wire when_DBusCachedPlugin_l311; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_105; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_106; - reg [31:0] _zz_107; - wire _zz_108; - reg [31:0] _zz_109; + reg [31:0] writeBack_DBusCachedPlugin_rspRf; + wire when_DBusCachedPlugin_l474; + wire [1:0] switch_Misc_l200_2; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [32:0] _zz_110; - wire _zz_111; - wire _zz_112; - wire _zz_113; - wire _zz_114; - wire `Src1CtrlEnum_defaultEncoding_type _zz_115; - wire `AluCtrlEnum_defaultEncoding_type _zz_116; - wire `Src2CtrlEnum_defaultEncoding_type _zz_117; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_118; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_119; - wire `BranchCtrlEnum_defaultEncoding_type _zz_120; - wire `EnvCtrlEnum_defaultEncoding_type _zz_121; + wire when_DBusCachedPlugin_l484; + wire [33:0] _zz_decode_IS_RS2_SIGNED; + wire _zz_decode_IS_RS2_SIGNED_1; + wire _zz_decode_IS_RS2_SIGNED_2; + wire _zz_decode_IS_RS2_SIGNED_3; + wire _zz_decode_IS_RS2_SIGNED_4; + wire _zz_decode_IS_RS2_SIGNED_5; + wire _zz_decode_IS_RS2_SIGNED_6; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -999,45 +1018,63 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_122; + reg _zz_2; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_123; - reg [31:0] _zz_124; - wire _zz_125; - reg [19:0] _zz_126; - wire _zz_127; - reg [19:0] _zz_128; - reg [31:0] _zz_129; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_130; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_131; - reg _zz_132; - reg _zz_133; - reg _zz_134; - reg [4:0] _zz_135; - reg [31:0] _zz_136; - wire _zz_137; - wire _zz_138; - wire _zz_139; - wire _zz_140; - wire _zz_141; - wire _zz_142; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_143; - reg _zz_144; - reg _zz_145; + wire [2:0] switch_Misc_l200_3; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_146; - reg [19:0] _zz_147; - wire _zz_148; - reg [10:0] _zz_149; - wire _zz_150; - reg [18:0] _zz_151; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; @@ -1059,9 +1096,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_152; - wire _zz_153; - wire _zz_154; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1074,40 +1111,67 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_155; - wire _zz_156; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_4; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1115,6 +1179,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1127,19 +1193,26 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_157; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_158; - wire _zz_159; - wire _zz_160; - reg [32:0] _zz_161; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_162; - wire [31:0] _zz_163; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1147,204 +1220,327 @@ module VexRiscv ( reg DebugPlugin_stepIt; reg DebugPlugin_isPipBusy; reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_164; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; wire DebugPlugin_allowEBreak; - reg _zz_165; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; + reg _zz_3; reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg decode_to_execute_IS_RVC; + wire when_Pipeline_l124_7; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_10; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_12; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_13; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_15; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_16; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_17; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_18; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_22; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_24; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_25; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_26; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_27; + reg decode_to_execute_MEMORY_LRSC; + wire when_Pipeline_l124_28; + reg execute_to_memory_MEMORY_LRSC; + wire when_Pipeline_l124_29; + reg memory_to_writeBack_MEMORY_LRSC; + wire when_Pipeline_l124_30; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_31; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_33; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_34; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_35; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_37; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_38; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_39; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_40; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_41; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_42; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_43; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_44; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_45; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_46; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_47; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_48; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_49; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_50; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_51; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_52; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_53; reg decode_to_execute_DO_EBREAK; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_54; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_55; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_57; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_58; reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_59; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_60; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_61; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_62; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_63; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_64; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_65; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_66; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_166; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l360; + wire when_Fetcher_l378; + wire when_Fetcher_l398; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [2:0] _zz_190; - reg _zz_191; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_192; - wire _zz_193; - wire _zz_194; - wire _zz_195; - wire _zz_196; - wire _zz_197; - reg _zz_198; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; - reg [39:0] _zz_17_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; - reg [23:0] _zz_20_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; - reg [63:0] _zz_23_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; - reg [95:0] _zz_26_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_30_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_33_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_34_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_36_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_37_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_38_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_39_string; - reg [39:0] _zz_43_string; - reg [31:0] _zz_44_string; - reg [71:0] _zz_45_string; - reg [39:0] _zz_46_string; - reg [23:0] _zz_47_string; - reg [63:0] _zz_48_string; - reg [95:0] _zz_49_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_51_string; - reg [95:0] _zz_115_string; - reg [63:0] _zz_116_string; - reg [23:0] _zz_117_string; - reg [39:0] _zz_118_string; - reg [71:0] _zz_119_string; - reg [31:0] _zz_120_string; - reg [39:0] _zz_121_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1359,1169 +1555,1153 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_231 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_232 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_233 = 1'b1; - assign _zz_234 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_235 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_236 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_237 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_238 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_239 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_240 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_241 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_242 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_243 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_244 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_245 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_246 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_247 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_248 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_249 = (IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); - assign _zz_250 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_251 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_252 = (1'b0 || (! 1'b1)); - assign _zz_253 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_254 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_256 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_257 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_258 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_260 = execute_INSTRUCTION[13 : 12]; - assign _zz_261 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_262 = (! memory_arbitration_isStuck); - assign _zz_263 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_264 = (iBus_cmd_valid || (_zz_190 != 3'b000)); - assign _zz_265 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); - assign _zz_266 = (_zz_227 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_267 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_268 = ((_zz_152 && 1'b1) && (! 1'b0)); - assign _zz_269 = ((_zz_153 && 1'b1) && (! 1'b0)); - assign _zz_270 = ((_zz_154 && 1'b1) && (! 1'b0)); - assign _zz_271 = {_zz_65[1 : 0],_zz_65[15 : 13]}; - assign _zz_272 = _zz_65[6 : 5]; - assign _zz_273 = _zz_65[11 : 10]; - assign _zz_274 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_275 = execute_INSTRUCTION[13]; - assign _zz_276 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_277 = ($signed(_zz_278) + $signed(_zz_283)); - assign _zz_278 = ($signed(_zz_279) + $signed(_zz_281)); - assign _zz_279 = 52'h0; - assign _zz_280 = {1'b0,memory_MUL_LL}; - assign _zz_281 = {{19{_zz_280[32]}}, _zz_280}; - assign _zz_282 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_283 = {{2{_zz_282[49]}}, _zz_282}; - assign _zz_284 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_285 = {{2{_zz_284[49]}}, _zz_284}; - assign _zz_286 = ($signed(_zz_288) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_287 = _zz_286[31 : 0]; - assign _zz_288 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_289 = _zz_110[31 : 31]; - assign _zz_290 = _zz_110[30 : 30]; - assign _zz_291 = _zz_110[29 : 29]; - assign _zz_292 = _zz_110[28 : 28]; - assign _zz_293 = _zz_110[25 : 25]; - assign _zz_294 = _zz_110[17 : 17]; - assign _zz_295 = _zz_110[16 : 16]; - assign _zz_296 = _zz_110[13 : 13]; - assign _zz_297 = _zz_110[12 : 12]; - assign _zz_298 = _zz_110[11 : 11]; - assign _zz_299 = (decode_IS_RVC ? 3'b010 : 3'b100); - assign _zz_300 = {29'd0, _zz_299}; - assign _zz_301 = _zz_110[32 : 32]; - assign _zz_302 = _zz_110[15 : 15]; - assign _zz_303 = _zz_110[5 : 5]; - assign _zz_304 = _zz_110[3 : 3]; - assign _zz_305 = _zz_110[20 : 20]; - assign _zz_306 = _zz_110[10 : 10]; - assign _zz_307 = _zz_110[4 : 4]; - assign _zz_308 = _zz_110[0 : 0]; - assign _zz_309 = (_zz_55 - 4'b0001); - assign _zz_310 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_311 = {29'd0, _zz_310}; - assign _zz_312 = (decode_IS_RVC ? 3'b010 : 3'b100); - assign _zz_313 = {29'd0, _zz_312}; - assign _zz_314 = {{_zz_75,_zz_65[6 : 2]},12'h0}; - assign _zz_315 = {{{4'b0000,_zz_65[8 : 7]},_zz_65[12 : 9]},2'b00}; - assign _zz_316 = {{{4'b0000,_zz_65[8 : 7]},_zz_65[12 : 9]},2'b00}; - assign _zz_317 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_318 = {{_zz_98,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_319 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_321 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_322 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_323 = execute_SRC_LESS; - assign _zz_324 = (execute_IS_RVC ? 3'b010 : 3'b100); - assign _zz_325 = execute_INSTRUCTION[19 : 15]; - assign _zz_326 = execute_INSTRUCTION[31 : 20]; - assign _zz_327 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_328 = ($signed(_zz_329) + $signed(_zz_332)); - assign _zz_329 = ($signed(_zz_330) + $signed(_zz_331)); - assign _zz_330 = execute_SRC1; - assign _zz_331 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_332 = (execute_SRC_USE_SUB_LESS ? _zz_333 : _zz_334); - assign _zz_333 = 32'h00000001; - assign _zz_334 = 32'h0; - assign _zz_335 = execute_INSTRUCTION[31 : 20]; - assign _zz_336 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_337 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_338 = (execute_IS_RVC ? 3'b010 : 3'b100); - assign _zz_339 = (_zz_155 & (~ _zz_340)); - assign _zz_340 = (_zz_155 - 2'b01); - assign _zz_341 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_342 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_343 = writeBack_MUL_LOW[31 : 0]; - assign _zz_344 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_345 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_346 = {5'd0, _zz_345}; - assign _zz_347 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_348 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_349 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_350 = {_zz_157,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_351 = _zz_352; - assign _zz_352 = _zz_353; - assign _zz_353 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_158) : _zz_158)} + _zz_355); - assign _zz_354 = memory_DivPlugin_div_needRevert; - assign _zz_355 = {32'd0, _zz_354}; - assign _zz_356 = _zz_160; - assign _zz_357 = {32'd0, _zz_356}; - assign _zz_358 = _zz_159; - assign _zz_359 = {31'd0, _zz_358}; - assign _zz_360 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_361 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_362 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_363 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_364 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_365 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_366 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_367 = (iBus_cmd_payload_address >>> 5); - assign _zz_368 = 1'b1; - assign _zz_369 = 1'b1; - assign _zz_370 = {_zz_59,_zz_58}; - assign _zz_371 = 32'h0000107f; - assign _zz_372 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_373 = 32'h00002073; - assign _zz_374 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_375 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_376 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_377) == 32'h00000003),{(_zz_378 == _zz_379),{_zz_380,{_zz_381,_zz_382}}}}}}; - assign _zz_377 = 32'h0000505f; - assign _zz_378 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_379 = 32'h00000063; - assign _zz_380 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_381 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_382 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_383) == 32'h00001013),{(_zz_384 == _zz_385),{_zz_386,{_zz_387,_zz_388}}}}}}; - assign _zz_383 = 32'hfc00307f; - assign _zz_384 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_385 = 32'h00005033; - assign _zz_386 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_387 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_388 = {((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}; - assign _zz_389 = (_zz_65[11 : 10] == 2'b01); - assign _zz_390 = ((_zz_65[11 : 10] == 2'b11) && (_zz_65[6 : 5] == 2'b00)); - assign _zz_391 = 7'h0; - assign _zz_392 = _zz_65[6 : 2]; - assign _zz_393 = _zz_65[12]; - assign _zz_394 = _zz_65[11 : 7]; - assign _zz_395 = decode_INSTRUCTION[31]; - assign _zz_396 = decode_INSTRUCTION[19 : 12]; - assign _zz_397 = decode_INSTRUCTION[20]; - assign _zz_398 = decode_INSTRUCTION[31]; - assign _zz_399 = decode_INSTRUCTION[7]; - assign _zz_400 = 32'h10103050; - assign _zz_401 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_402 = 1'b0; - assign _zz_403 = (((decode_INSTRUCTION & _zz_406) == 32'h02000030) != 1'b0); - assign _zz_404 = ({_zz_407,_zz_408} != 2'b00); - assign _zz_405 = {(_zz_409 != 1'b0),{(_zz_410 != _zz_411),{_zz_412,{_zz_413,_zz_414}}}}; - assign _zz_406 = 32'h02004074; - assign _zz_407 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); - assign _zz_408 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); - assign _zz_409 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); - assign _zz_410 = {(_zz_415 == _zz_416),(_zz_417 == _zz_418)}; - assign _zz_411 = 2'b00; - assign _zz_412 = ({_zz_113,_zz_419} != 2'b00); - assign _zz_413 = (_zz_420 != 1'b0); - assign _zz_414 = {(_zz_421 != _zz_422),{_zz_423,{_zz_424,_zz_425}}}; - assign _zz_415 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_416 = 32'h00001050; - assign _zz_417 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_418 = 32'h00002050; - assign _zz_419 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_420 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_421 = {(_zz_426 == _zz_427),(_zz_428 == _zz_429)}; - assign _zz_422 = 2'b00; - assign _zz_423 = ({_zz_430,{_zz_431,_zz_432}} != 3'b000); - assign _zz_424 = (_zz_433 != 1'b0); - assign _zz_425 = {(_zz_434 != _zz_435),{_zz_436,{_zz_437,_zz_438}}}; - assign _zz_426 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_427 = 32'h00005010; - assign _zz_428 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_429 = 32'h00005020; - assign _zz_430 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_431 = ((decode_INSTRUCTION & _zz_439) == 32'h00001010); - assign _zz_432 = ((decode_INSTRUCTION & _zz_440) == 32'h00001010); - assign _zz_433 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_434 = ((decode_INSTRUCTION & _zz_441) == 32'h00001000); - assign _zz_435 = 1'b0; - assign _zz_436 = ((_zz_442 == _zz_443) != 1'b0); - assign _zz_437 = ({_zz_444,_zz_445} != 2'b00); - assign _zz_438 = {(_zz_446 != _zz_447),{_zz_448,{_zz_449,_zz_450}}}; - assign _zz_439 = 32'h00007034; - assign _zz_440 = 32'h02007054; - assign _zz_441 = 32'h00001000; - assign _zz_442 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_443 = 32'h00002000; - assign _zz_444 = ((decode_INSTRUCTION & _zz_451) == 32'h00002000); - assign _zz_445 = ((decode_INSTRUCTION & _zz_452) == 32'h00001000); - assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h00004008); - assign _zz_447 = 1'b0; - assign _zz_448 = ({_zz_454,_zz_455} != 2'b00); - assign _zz_449 = ({_zz_456,_zz_457} != 5'h0); - assign _zz_450 = {(_zz_458 != _zz_459),{_zz_460,{_zz_461,_zz_462}}}; - assign _zz_451 = 32'h00002010; - assign _zz_452 = 32'h00005000; - assign _zz_453 = 32'h00004048; - assign _zz_454 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); - assign _zz_455 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_456 = ((decode_INSTRUCTION & _zz_463) == 32'h00002040); - assign _zz_457 = {(_zz_464 == _zz_465),{_zz_466,{_zz_467,_zz_468}}}; - assign _zz_458 = ((decode_INSTRUCTION & _zz_469) == 32'h00000020); - assign _zz_459 = 1'b0; - assign _zz_460 = ({_zz_470,{_zz_471,_zz_472}} != 5'h0); - assign _zz_461 = ({_zz_473,_zz_474} != 5'h0); - assign _zz_462 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; - assign _zz_463 = 32'h00002040; - assign _zz_464 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_465 = 32'h00001040; - assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000040); - assign _zz_467 = (_zz_481 == _zz_482); - assign _zz_468 = (_zz_483 == _zz_484); - assign _zz_469 = 32'h00000020; - assign _zz_470 = ((decode_INSTRUCTION & _zz_485) == 32'h00000040); - assign _zz_471 = _zz_112; - assign _zz_472 = {_zz_486,{_zz_487,_zz_488}}; - assign _zz_473 = _zz_112; - assign _zz_474 = {_zz_489,{_zz_490,_zz_491}}; - assign _zz_475 = {_zz_113,{_zz_492,_zz_493}}; - assign _zz_476 = 6'h0; - assign _zz_477 = ({_zz_494,_zz_495} != 2'b00); - assign _zz_478 = (_zz_496 != _zz_497); - assign _zz_479 = {_zz_498,{_zz_499,_zz_500}}; - assign _zz_480 = 32'h00100040; - assign _zz_481 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_482 = 32'h00000040; - assign _zz_483 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_484 = 32'h0; - assign _zz_485 = 32'h00000040; - assign _zz_486 = ((decode_INSTRUCTION & _zz_501) == 32'h00004020); - assign _zz_487 = (_zz_502 == _zz_503); - assign _zz_488 = (_zz_504 == _zz_505); - assign _zz_489 = ((decode_INSTRUCTION & _zz_506) == 32'h00002010); - assign _zz_490 = (_zz_507 == _zz_508); - assign _zz_491 = {_zz_509,_zz_510}; - assign _zz_492 = (_zz_511 == _zz_512); - assign _zz_493 = {_zz_513,{_zz_514,_zz_515}}; - assign _zz_494 = _zz_112; - assign _zz_495 = (_zz_516 == _zz_517); - assign _zz_496 = {_zz_112,_zz_518}; - assign _zz_497 = 2'b00; - assign _zz_498 = (_zz_519 != 1'b0); - assign _zz_499 = (_zz_520 != _zz_521); - assign _zz_500 = {_zz_522,{_zz_523,_zz_524}}; - assign _zz_501 = 32'h00004020; - assign _zz_502 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_503 = 32'h00000010; - assign _zz_504 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_505 = 32'h00000020; - assign _zz_506 = 32'h00002030; - assign _zz_507 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_508 = 32'h00000010; - assign _zz_509 = ((decode_INSTRUCTION & _zz_525) == 32'h00002020); - assign _zz_510 = ((decode_INSTRUCTION & _zz_526) == 32'h00000020); - assign _zz_511 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_512 = 32'h00001010; - assign _zz_513 = ((decode_INSTRUCTION & _zz_527) == 32'h00002010); - assign _zz_514 = (_zz_528 == _zz_529); - assign _zz_515 = {_zz_530,_zz_531}; - assign _zz_516 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_517 = 32'h00000020; - assign _zz_518 = ((decode_INSTRUCTION & _zz_532) == 32'h0); - assign _zz_519 = ((decode_INSTRUCTION & _zz_533) == 32'h00004010); - assign _zz_520 = (_zz_534 == _zz_535); - assign _zz_521 = 1'b0; - assign _zz_522 = ({_zz_536,_zz_537} != 4'b0000); - assign _zz_523 = (_zz_538 != _zz_539); - assign _zz_524 = {_zz_540,{_zz_541,_zz_542}}; - assign _zz_525 = 32'h02002060; - assign _zz_526 = 32'h02003020; - assign _zz_527 = 32'h00002010; - assign _zz_528 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_529 = 32'h00000010; - assign _zz_530 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_531 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); - assign _zz_532 = 32'h00000020; - assign _zz_533 = 32'h00004014; - assign _zz_534 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_535 = 32'h00002010; - assign _zz_536 = ((decode_INSTRUCTION & _zz_543) == 32'h0); - assign _zz_537 = {(_zz_544 == _zz_545),{_zz_546,_zz_547}}; - assign _zz_538 = ((decode_INSTRUCTION & _zz_548) == 32'h0); - assign _zz_539 = 1'b0; - assign _zz_540 = ({_zz_549,{_zz_550,_zz_551}} != 3'b000); - assign _zz_541 = ({_zz_552,_zz_553} != 2'b00); - assign _zz_542 = {(_zz_554 != _zz_555),(_zz_556 != _zz_557)}; - assign _zz_543 = 32'h00000044; - assign _zz_544 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_545 = 32'h0; - assign _zz_546 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_547 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_548 = 32'h00000058; - assign _zz_549 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_550 = ((decode_INSTRUCTION & _zz_558) == 32'h00002010); - assign _zz_551 = ((decode_INSTRUCTION & _zz_559) == 32'h40000030); - assign _zz_552 = ((decode_INSTRUCTION & _zz_560) == 32'h00000004); - assign _zz_553 = _zz_111; - assign _zz_554 = {(_zz_561 == _zz_562),_zz_111}; - assign _zz_555 = 2'b00; - assign _zz_556 = ((decode_INSTRUCTION & _zz_563) == 32'h00001008); - assign _zz_557 = 1'b0; - assign _zz_558 = 32'h00002014; - assign _zz_559 = 32'h40000034; - assign _zz_560 = 32'h00000014; - assign _zz_561 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_562 = 32'h00000004; - assign _zz_563 = 32'h00005048; - assign _zz_564 = execute_INSTRUCTION[31]; - assign _zz_565 = execute_INSTRUCTION[31]; - assign _zz_566 = execute_INSTRUCTION[7]; - assign _zz_567 = 32'h0; - always @ (posedge clk) begin - if(_zz_368) begin - _zz_228 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_369) begin - _zz_229 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_42) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz_decode_FORMAL_PC_NEXT_1 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_decode_FORMAL_PC_NEXT = {29'd0, _zz_decode_FORMAL_PC_NEXT_1}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz_IBusCachedPlugin_decodePc_pcPlus_1 = (decode_IS_RVC ? 3'b010 : 3'b100); + assign _zz_IBusCachedPlugin_decodePc_pcPlus = {29'd0, _zz_IBusCachedPlugin_decodePc_pcPlus_1}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_27 = {{_zz_IBusCachedPlugin_decompressor_decompressed_10,_zz_IBusCachedPlugin_decompressor_decompressed[6 : 2]},12'h0}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_34 = {{{4'b0000,_zz_IBusCachedPlugin_decompressor_decompressed[8 : 7]},_zz_IBusCachedPlugin_decompressor_decompressed[12 : 9]},2'b00}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_35 = {{{4'b0000,_zz_IBusCachedPlugin_decompressor_decompressed[8 : 7]},_zz_IBusCachedPlugin_decompressor_decompressed[12 : 9]},2'b00}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_writeBack_DBusCachedPlugin_rspRf = (! dataCache_1_io_cpu_writeBack_exclusiveOk); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = (execute_IS_RVC ? 3'b010 : 3'b100); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hf800707f) == 32'h1800202f),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_28 = (_zz_IBusCachedPlugin_decompressor_decompressed[11 : 10] == 2'b01); + assign _zz_IBusCachedPlugin_decompressor_decompressed_29 = ((_zz_IBusCachedPlugin_decompressor_decompressed[11 : 10] == 2'b11) && (_zz_IBusCachedPlugin_decompressor_decompressed[6 : 5] == 2'b00)); + assign _zz_IBusCachedPlugin_decompressor_decompressed_30 = 7'h0; + assign _zz_IBusCachedPlugin_decompressor_decompressed_31 = _zz_IBusCachedPlugin_decompressor_decompressed[6 : 2]; + assign _zz_IBusCachedPlugin_decompressor_decompressed_32 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + assign _zz_IBusCachedPlugin_decompressor_decompressed_33 = _zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[19 : 12]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[20]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_7 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_8 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_IS_RS2_SIGNED = 32'h10103050; + assign _zz__zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz__zz_decode_IS_RS2_SIGNED_2 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_3 = (((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_4) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_5 = ({_zz__zz_decode_IS_RS2_SIGNED_6,_zz__zz_decode_IS_RS2_SIGNED_7} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_8 = {(_zz__zz_decode_IS_RS2_SIGNED_9 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_10 != _zz__zz_decode_IS_RS2_SIGNED_15),{_zz__zz_decode_IS_RS2_SIGNED_16,{_zz__zz_decode_IS_RS2_SIGNED_18,_zz__zz_decode_IS_RS2_SIGNED_20}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_4 = 32'h02004074; + assign _zz__zz_decode_IS_RS2_SIGNED_6 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); + assign _zz__zz_decode_IS_RS2_SIGNED_7 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_9 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_10 = {(_zz__zz_decode_IS_RS2_SIGNED_11 == _zz__zz_decode_IS_RS2_SIGNED_12),(_zz__zz_decode_IS_RS2_SIGNED_13 == _zz__zz_decode_IS_RS2_SIGNED_14)}; + assign _zz__zz_decode_IS_RS2_SIGNED_15 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_16 = ({_zz_decode_IS_RS2_SIGNED_2,_zz__zz_decode_IS_RS2_SIGNED_17} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_18 = (_zz__zz_decode_IS_RS2_SIGNED_19 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_20 = {(_zz__zz_decode_IS_RS2_SIGNED_21 != _zz__zz_decode_IS_RS2_SIGNED_26),{_zz__zz_decode_IS_RS2_SIGNED_27,{_zz__zz_decode_IS_RS2_SIGNED_33,_zz__zz_decode_IS_RS2_SIGNED_35}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_11 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_IS_RS2_SIGNED_12 = 32'h00001050; + assign _zz__zz_decode_IS_RS2_SIGNED_13 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_IS_RS2_SIGNED_14 = 32'h00002050; + assign _zz__zz_decode_IS_RS2_SIGNED_17 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_19 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_21 = {(_zz__zz_decode_IS_RS2_SIGNED_22 == _zz__zz_decode_IS_RS2_SIGNED_23),(_zz__zz_decode_IS_RS2_SIGNED_24 == _zz__zz_decode_IS_RS2_SIGNED_25)}; + assign _zz__zz_decode_IS_RS2_SIGNED_26 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_27 = ({_zz__zz_decode_IS_RS2_SIGNED_28,{_zz__zz_decode_IS_RS2_SIGNED_29,_zz__zz_decode_IS_RS2_SIGNED_31}} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_33 = (_zz__zz_decode_IS_RS2_SIGNED_34 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_35 = {(_zz__zz_decode_IS_RS2_SIGNED_36 != _zz__zz_decode_IS_RS2_SIGNED_38),{_zz__zz_decode_IS_RS2_SIGNED_39,{_zz__zz_decode_IS_RS2_SIGNED_42,_zz__zz_decode_IS_RS2_SIGNED_44}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_22 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_RS2_SIGNED_23 = 32'h00005010; + assign _zz__zz_decode_IS_RS2_SIGNED_24 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_IS_RS2_SIGNED_25 = 32'h00005020; + assign _zz__zz_decode_IS_RS2_SIGNED_28 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_IS_RS2_SIGNED_29 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_30) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_31 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_32) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_34 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_36 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_37) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_38 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_39 = ({_zz__zz_decode_IS_RS2_SIGNED_40,_zz__zz_decode_IS_RS2_SIGNED_41} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_42 = (_zz__zz_decode_IS_RS2_SIGNED_43 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_44 = {(_zz__zz_decode_IS_RS2_SIGNED_45 != _zz__zz_decode_IS_RS2_SIGNED_47),{_zz__zz_decode_IS_RS2_SIGNED_48,{_zz__zz_decode_IS_RS2_SIGNED_54,_zz__zz_decode_IS_RS2_SIGNED_56}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_30 = 32'h00007034; + assign _zz__zz_decode_IS_RS2_SIGNED_32 = 32'h02007054; + assign _zz__zz_decode_IS_RS2_SIGNED_37 = 32'h00003000; + assign _zz__zz_decode_IS_RS2_SIGNED_40 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_41 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_43 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz__zz_decode_IS_RS2_SIGNED_45 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_46) == 32'h00000024); + assign _zz__zz_decode_IS_RS2_SIGNED_47 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_48 = ({_zz__zz_decode_IS_RS2_SIGNED_49,{_zz__zz_decode_IS_RS2_SIGNED_50,_zz__zz_decode_IS_RS2_SIGNED_52}} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_54 = (_zz__zz_decode_IS_RS2_SIGNED_55 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_56 = {(_zz__zz_decode_IS_RS2_SIGNED_57 != _zz__zz_decode_IS_RS2_SIGNED_74),{_zz__zz_decode_IS_RS2_SIGNED_75,{_zz__zz_decode_IS_RS2_SIGNED_80,_zz__zz_decode_IS_RS2_SIGNED_93}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_46 = 32'h00000064; + assign _zz__zz_decode_IS_RS2_SIGNED_49 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_50 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_51) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_52 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_53) == 32'h08000020); + assign _zz__zz_decode_IS_RS2_SIGNED_55 = ((decode_INSTRUCTION & 32'h00000008) == 32'h00000008); + assign _zz__zz_decode_IS_RS2_SIGNED_57 = {(_zz__zz_decode_IS_RS2_SIGNED_58 == _zz__zz_decode_IS_RS2_SIGNED_59),{_zz__zz_decode_IS_RS2_SIGNED_60,{_zz__zz_decode_IS_RS2_SIGNED_62,_zz__zz_decode_IS_RS2_SIGNED_65}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_74 = 6'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_75 = ({_zz__zz_decode_IS_RS2_SIGNED_76,_zz__zz_decode_IS_RS2_SIGNED_78} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_80 = ({_zz__zz_decode_IS_RS2_SIGNED_81,_zz__zz_decode_IS_RS2_SIGNED_84} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_93 = {(_zz__zz_decode_IS_RS2_SIGNED_94 != _zz__zz_decode_IS_RS2_SIGNED_107),{_zz__zz_decode_IS_RS2_SIGNED_108,{_zz__zz_decode_IS_RS2_SIGNED_125,_zz__zz_decode_IS_RS2_SIGNED_130}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_51 = 32'h00000064; + assign _zz__zz_decode_IS_RS2_SIGNED_53 = 32'h08000070; + assign _zz__zz_decode_IS_RS2_SIGNED_58 = (decode_INSTRUCTION & 32'h00002040); + assign _zz__zz_decode_IS_RS2_SIGNED_59 = 32'h00002040; + assign _zz__zz_decode_IS_RS2_SIGNED_60 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_61) == 32'h00001040); + assign _zz__zz_decode_IS_RS2_SIGNED_62 = (_zz__zz_decode_IS_RS2_SIGNED_63 == _zz__zz_decode_IS_RS2_SIGNED_64); + assign _zz__zz_decode_IS_RS2_SIGNED_65 = {_zz__zz_decode_IS_RS2_SIGNED_66,{_zz__zz_decode_IS_RS2_SIGNED_68,_zz__zz_decode_IS_RS2_SIGNED_71}}; + assign _zz__zz_decode_IS_RS2_SIGNED_76 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_77) == 32'h08000020); + assign _zz__zz_decode_IS_RS2_SIGNED_78 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_79) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_81 = (_zz__zz_decode_IS_RS2_SIGNED_82 == _zz__zz_decode_IS_RS2_SIGNED_83); + assign _zz__zz_decode_IS_RS2_SIGNED_84 = {_zz__zz_decode_IS_RS2_SIGNED_85,{_zz__zz_decode_IS_RS2_SIGNED_87,_zz__zz_decode_IS_RS2_SIGNED_90}}; + assign _zz__zz_decode_IS_RS2_SIGNED_94 = {_zz_decode_IS_RS2_SIGNED_5,{_zz__zz_decode_IS_RS2_SIGNED_95,_zz__zz_decode_IS_RS2_SIGNED_98}}; + assign _zz__zz_decode_IS_RS2_SIGNED_107 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_108 = ({_zz__zz_decode_IS_RS2_SIGNED_109,_zz__zz_decode_IS_RS2_SIGNED_110} != 7'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_125 = (_zz__zz_decode_IS_RS2_SIGNED_126 != _zz__zz_decode_IS_RS2_SIGNED_129); + assign _zz__zz_decode_IS_RS2_SIGNED_130 = {_zz__zz_decode_IS_RS2_SIGNED_131,{_zz__zz_decode_IS_RS2_SIGNED_136,_zz__zz_decode_IS_RS2_SIGNED_141}}; + assign _zz__zz_decode_IS_RS2_SIGNED_61 = 32'h00001040; + assign _zz__zz_decode_IS_RS2_SIGNED_63 = (decode_INSTRUCTION & 32'h00100040); + assign _zz__zz_decode_IS_RS2_SIGNED_64 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_66 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_67) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_68 = (_zz__zz_decode_IS_RS2_SIGNED_69 == _zz__zz_decode_IS_RS2_SIGNED_70); + assign _zz__zz_decode_IS_RS2_SIGNED_71 = (_zz__zz_decode_IS_RS2_SIGNED_72 == _zz__zz_decode_IS_RS2_SIGNED_73); + assign _zz__zz_decode_IS_RS2_SIGNED_77 = 32'h08000020; + assign _zz__zz_decode_IS_RS2_SIGNED_79 = 32'h00000028; + assign _zz__zz_decode_IS_RS2_SIGNED_82 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_83 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_85 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_86) == 32'h00004020); + assign _zz__zz_decode_IS_RS2_SIGNED_87 = (_zz__zz_decode_IS_RS2_SIGNED_88 == _zz__zz_decode_IS_RS2_SIGNED_89); + assign _zz__zz_decode_IS_RS2_SIGNED_90 = {_zz_decode_IS_RS2_SIGNED_5,_zz__zz_decode_IS_RS2_SIGNED_91}; + assign _zz__zz_decode_IS_RS2_SIGNED_95 = (_zz__zz_decode_IS_RS2_SIGNED_96 == _zz__zz_decode_IS_RS2_SIGNED_97); + assign _zz__zz_decode_IS_RS2_SIGNED_98 = {_zz__zz_decode_IS_RS2_SIGNED_99,{_zz__zz_decode_IS_RS2_SIGNED_101,_zz__zz_decode_IS_RS2_SIGNED_104}}; + assign _zz__zz_decode_IS_RS2_SIGNED_109 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_110 = {_zz__zz_decode_IS_RS2_SIGNED_111,{_zz__zz_decode_IS_RS2_SIGNED_113,_zz__zz_decode_IS_RS2_SIGNED_116}}; + assign _zz__zz_decode_IS_RS2_SIGNED_126 = {_zz_decode_IS_RS2_SIGNED_4,_zz__zz_decode_IS_RS2_SIGNED_127}; + assign _zz__zz_decode_IS_RS2_SIGNED_129 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_131 = ({_zz__zz_decode_IS_RS2_SIGNED_132,_zz__zz_decode_IS_RS2_SIGNED_133} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_136 = (_zz__zz_decode_IS_RS2_SIGNED_137 != _zz__zz_decode_IS_RS2_SIGNED_140); + assign _zz__zz_decode_IS_RS2_SIGNED_141 = {_zz__zz_decode_IS_RS2_SIGNED_142,{_zz__zz_decode_IS_RS2_SIGNED_145,_zz__zz_decode_IS_RS2_SIGNED_158}}; + assign _zz__zz_decode_IS_RS2_SIGNED_67 = 32'h00000050; + assign _zz__zz_decode_IS_RS2_SIGNED_69 = (decode_INSTRUCTION & 32'h08002008); + assign _zz__zz_decode_IS_RS2_SIGNED_70 = 32'h00002008; + assign _zz__zz_decode_IS_RS2_SIGNED_72 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_IS_RS2_SIGNED_73 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_86 = 32'h00004020; + assign _zz__zz_decode_IS_RS2_SIGNED_88 = (decode_INSTRUCTION & 32'h00000030); + assign _zz__zz_decode_IS_RS2_SIGNED_89 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_91 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_92) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_96 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_IS_RS2_SIGNED_97 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_99 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_100) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_101 = (_zz__zz_decode_IS_RS2_SIGNED_102 == _zz__zz_decode_IS_RS2_SIGNED_103); + assign _zz__zz_decode_IS_RS2_SIGNED_104 = (_zz__zz_decode_IS_RS2_SIGNED_105 == _zz__zz_decode_IS_RS2_SIGNED_106); + assign _zz__zz_decode_IS_RS2_SIGNED_111 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_112) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_113 = (_zz__zz_decode_IS_RS2_SIGNED_114 == _zz__zz_decode_IS_RS2_SIGNED_115); + assign _zz__zz_decode_IS_RS2_SIGNED_116 = {_zz__zz_decode_IS_RS2_SIGNED_117,{_zz__zz_decode_IS_RS2_SIGNED_119,_zz__zz_decode_IS_RS2_SIGNED_122}}; + assign _zz__zz_decode_IS_RS2_SIGNED_127 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_128) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_132 = _zz_decode_IS_RS2_SIGNED_4; + assign _zz__zz_decode_IS_RS2_SIGNED_133 = (_zz__zz_decode_IS_RS2_SIGNED_134 == _zz__zz_decode_IS_RS2_SIGNED_135); + assign _zz__zz_decode_IS_RS2_SIGNED_137 = (_zz__zz_decode_IS_RS2_SIGNED_138 == _zz__zz_decode_IS_RS2_SIGNED_139); + assign _zz__zz_decode_IS_RS2_SIGNED_140 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_142 = (_zz__zz_decode_IS_RS2_SIGNED_143 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_145 = (_zz__zz_decode_IS_RS2_SIGNED_146 != _zz__zz_decode_IS_RS2_SIGNED_157); + assign _zz__zz_decode_IS_RS2_SIGNED_158 = {_zz__zz_decode_IS_RS2_SIGNED_159,{_zz__zz_decode_IS_RS2_SIGNED_164,_zz__zz_decode_IS_RS2_SIGNED_172}}; + assign _zz__zz_decode_IS_RS2_SIGNED_92 = 32'h12000020; + assign _zz__zz_decode_IS_RS2_SIGNED_100 = 32'h00001030; + assign _zz__zz_decode_IS_RS2_SIGNED_102 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_IS_RS2_SIGNED_103 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_105 = (decode_INSTRUCTION & 32'h12002060); + assign _zz__zz_decode_IS_RS2_SIGNED_106 = 32'h00002020; + assign _zz__zz_decode_IS_RS2_SIGNED_112 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_114 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_115 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_117 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_118) == 32'h00002008); + assign _zz__zz_decode_IS_RS2_SIGNED_119 = (_zz__zz_decode_IS_RS2_SIGNED_120 == _zz__zz_decode_IS_RS2_SIGNED_121); + assign _zz__zz_decode_IS_RS2_SIGNED_122 = {_zz_decode_IS_RS2_SIGNED_5,_zz__zz_decode_IS_RS2_SIGNED_123}; + assign _zz__zz_decode_IS_RS2_SIGNED_128 = 32'h00000070; + assign _zz__zz_decode_IS_RS2_SIGNED_134 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_135 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_138 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_IS_RS2_SIGNED_139 = 32'h00004010; + assign _zz__zz_decode_IS_RS2_SIGNED_143 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_144) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_146 = {_zz__zz_decode_IS_RS2_SIGNED_147,{_zz__zz_decode_IS_RS2_SIGNED_149,_zz__zz_decode_IS_RS2_SIGNED_152}}; + assign _zz__zz_decode_IS_RS2_SIGNED_157 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_159 = ({_zz__zz_decode_IS_RS2_SIGNED_160,_zz__zz_decode_IS_RS2_SIGNED_161} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_164 = (_zz__zz_decode_IS_RS2_SIGNED_165 != _zz__zz_decode_IS_RS2_SIGNED_171); + assign _zz__zz_decode_IS_RS2_SIGNED_172 = {_zz__zz_decode_IS_RS2_SIGNED_173,{_zz__zz_decode_IS_RS2_SIGNED_178,_zz__zz_decode_IS_RS2_SIGNED_183}}; + assign _zz__zz_decode_IS_RS2_SIGNED_118 = 32'h00002008; + assign _zz__zz_decode_IS_RS2_SIGNED_120 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_121 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_123 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_124) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_144 = 32'h00006014; + assign _zz__zz_decode_IS_RS2_SIGNED_147 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_148) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_149 = (_zz__zz_decode_IS_RS2_SIGNED_150 == _zz__zz_decode_IS_RS2_SIGNED_151); + assign _zz__zz_decode_IS_RS2_SIGNED_152 = {_zz__zz_decode_IS_RS2_SIGNED_153,{_zz__zz_decode_IS_RS2_SIGNED_154,_zz__zz_decode_IS_RS2_SIGNED_156}}; + assign _zz__zz_decode_IS_RS2_SIGNED_160 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_161 = (_zz__zz_decode_IS_RS2_SIGNED_162 == _zz__zz_decode_IS_RS2_SIGNED_163); + assign _zz__zz_decode_IS_RS2_SIGNED_165 = {_zz__zz_decode_IS_RS2_SIGNED_166,{_zz__zz_decode_IS_RS2_SIGNED_167,_zz__zz_decode_IS_RS2_SIGNED_169}}; + assign _zz__zz_decode_IS_RS2_SIGNED_171 = 3'b000; + assign _zz__zz_decode_IS_RS2_SIGNED_173 = ({_zz__zz_decode_IS_RS2_SIGNED_174,_zz__zz_decode_IS_RS2_SIGNED_175} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_178 = (_zz__zz_decode_IS_RS2_SIGNED_179 != _zz__zz_decode_IS_RS2_SIGNED_182); + assign _zz__zz_decode_IS_RS2_SIGNED_183 = (_zz__zz_decode_IS_RS2_SIGNED_184 != _zz__zz_decode_IS_RS2_SIGNED_186); + assign _zz__zz_decode_IS_RS2_SIGNED_124 = 32'h00000028; + assign _zz__zz_decode_IS_RS2_SIGNED_148 = 32'h00000044; + assign _zz__zz_decode_IS_RS2_SIGNED_150 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_IS_RS2_SIGNED_151 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_153 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_154 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_155) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_156 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_162 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_IS_RS2_SIGNED_163 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_166 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_167 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_168) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_169 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_170) == 32'h40000030); + assign _zz__zz_decode_IS_RS2_SIGNED_174 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_175 = {_zz_decode_IS_RS2_SIGNED_1,(_zz__zz_decode_IS_RS2_SIGNED_176 == _zz__zz_decode_IS_RS2_SIGNED_177)}; + assign _zz__zz_decode_IS_RS2_SIGNED_179 = {_zz_decode_IS_RS2_SIGNED_1,(_zz__zz_decode_IS_RS2_SIGNED_180 == _zz__zz_decode_IS_RS2_SIGNED_181)}; + assign _zz__zz_decode_IS_RS2_SIGNED_182 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_184 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_185) == 32'h00001008); + assign _zz__zz_decode_IS_RS2_SIGNED_186 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_155 = 32'h00005004; + assign _zz__zz_decode_IS_RS2_SIGNED_168 = 32'h00002014; + assign _zz__zz_decode_IS_RS2_SIGNED_170 = 32'h40000034; + assign _zz__zz_decode_IS_RS2_SIGNED_176 = (decode_INSTRUCTION & 32'h00002014); + assign _zz__zz_decode_IS_RS2_SIGNED_177 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_180 = (decode_INSTRUCTION & 32'h0000004c); + assign _zz__zz_decode_IS_RS2_SIGNED_181 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_185 = 32'h00005048; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_199 ), //i - .io_cpu_prefetch_isValid (_zz_200 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_201 ), //i - .io_cpu_fetch_isStuck (_zz_202 ), //i - .io_cpu_fetch_isRemoved (_zz_203 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_fetch_cacheMiss (IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss ), //o - .io_cpu_fetch_error (IBusCachedPlugin_cache_io_cpu_fetch_error ), //o - .io_cpu_fetch_mmuRefilling (IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling ), //o - .io_cpu_fetch_mmuException (IBusCachedPlugin_cache_io_cpu_fetch_mmuException ), //o - .io_cpu_fetch_isUser (_zz_204 ), //i - .io_cpu_decode_isValid (_zz_205 ), //i - .io_cpu_decode_isStuck (_zz_206 ), //i - .io_cpu_decode_pc (_zz_207[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_fill_valid (_zz_208 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_fetch_cacheMiss (IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss ), //o + .io_cpu_fetch_error (IBusCachedPlugin_cache_io_cpu_fetch_error ), //o + .io_cpu_fetch_mmuRefilling (IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling ), //o + .io_cpu_fetch_mmuException (IBusCachedPlugin_cache_io_cpu_fetch_mmuException ), //o + .io_cpu_fetch_isUser (IBusCachedPlugin_cache_io_cpu_fetch_isUser ), //i + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_cache_io_cpu_decode_pc ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_209 ), //i - .io_cpu_execute_address (_zz_210[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_105[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_211 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_212[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_213 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_214 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_215 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_216[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_217 ), //i - .io_cpu_writeBack_fence_SR (_zz_218 ), //i - .io_cpu_writeBack_fence_SO (_zz_219 ), //i - .io_cpu_writeBack_fence_SI (_zz_220 ), //i - .io_cpu_writeBack_fence_PW (_zz_221 ), //i - .io_cpu_writeBack_fence_PR (_zz_222 ), //i - .io_cpu_writeBack_fence_PO (_zz_223 ), //i - .io_cpu_writeBack_fence_PI (_zz_224 ), //i - .io_cpu_writeBack_fence_FM (_zz_225[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_226 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_227 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_isLrsc (dataCache_1_io_cpu_execute_args_isLrsc ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_370) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) + 2'b00 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) 2'b00 : begin - _zz_230 = DBusCachedPlugin_redoBranch_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; end 2'b01 : begin - _zz_230 = CsrPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; end 2'b10 : begin - _zz_230 = BranchPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; end default : begin - _zz_230 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_30) - `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; - default : _zz_30_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_33) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; - default : _zz_33_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_34) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; - default : _zz_34_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_36) - `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; - default : _zz_36_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_37) - `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; - default : _zz_37_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_38) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; - default : _zz_38_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_39) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; - default : _zz_39_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_43) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; - default : _zz_43_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; - default : _zz_44_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_45) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; - default : _zz_45_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_46) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; - default : _zz_46_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_47) - `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; - default : _zz_47_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_48) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; - default : _zz_48_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_49) - `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; - default : _zz_49_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_115) - `Src1CtrlEnum_defaultEncoding_RS : _zz_115_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_115_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_115_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_115_string = "URS1 "; - default : _zz_115_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_116) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_116_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_116_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_116_string = "BITWISE "; - default : _zz_116_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_117) - `Src2CtrlEnum_defaultEncoding_RS : _zz_117_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_117_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_117_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_117_string = "PC "; - default : _zz_117_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_118) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_118_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_118_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_118_string = "AND_1"; - default : _zz_118_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_119) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_119_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_119_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_119_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_119_string = "SRA_1 "; - default : _zz_119_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_120) - `BranchCtrlEnum_defaultEncoding_INC : _zz_120_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_120_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_120_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_120_string = "JALR"; - default : _zz_120_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_121) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_121_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_121_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_121_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_121_string = "ECALL"; - default : _zz_121_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_277) + $signed(_zz_285)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -2529,53 +2709,54 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_287; - assign execute_REGFILE_WRITE_DATA = _zz_123; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_210[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_289[0]; - assign decode_IS_RS1_SIGNED = _zz_290[0]; - assign decode_IS_DIV = _zz_291[0]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_RS2_SIGNED[32]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_RS2_SIGNED[31]; + assign decode_IS_DIV = _zz_decode_IS_RS2_SIGNED[30]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_292[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_293[0]; - assign _zz_8 = _zz_9; - assign _zz_10 = _zz_11; - assign decode_SHIFT_CTRL = _zz_12; - assign _zz_13 = _zz_14; - assign decode_ALU_BITWISE_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_294[0]; - assign decode_MEMORY_MANAGMENT = _zz_295[0]; + assign decode_IS_MUL = _zz_decode_IS_RS2_SIGNED[29]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_RS2_SIGNED[26]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_RS2_SIGNED[19]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_RS2_SIGNED[18]; + assign memory_MEMORY_LRSC = execute_to_memory_MEMORY_LRSC; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_296[0]; + assign decode_MEMORY_WR = _zz_decode_IS_RS2_SIGNED[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_297[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_298[0]; - assign decode_SRC2_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_ALU_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_SRC1_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_RS2_SIGNED[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_RS2_SIGNED[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_decode_MEMORY_FORCE_CONSTISTENCY; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; - assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_300); + assign decode_FORMAL_PC_NEXT = (decode_PC + _zz_decode_FORMAL_PC_NEXT); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_301[0]; + assign decode_IS_EBREAK = _zz_decode_IS_RS2_SIGNED[33]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2589,22 +2770,22 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27; - assign execute_ENV_CTRL = _zz_28; - assign writeBack_ENV_CTRL = _zz_29; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_145; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; - assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_302[0]; - assign decode_RS1_USE = _zz_303[0]; - always @ (*) begin - _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_231)begin - _zz_31 = execute_CsrPlugin_readData; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_RS2_SIGNED[16]; + assign decode_RS1_USE = _zz_decode_IS_RS2_SIGNED[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2614,144 +2795,146 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_134)begin - if((_zz_135 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_136; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_232)begin - if(_zz_233)begin - if(_zz_138)begin - decode_RS2 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_234)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_140)begin - decode_RS2 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_235)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_142)begin - decode_RS2 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_134)begin - if((_zz_135 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_136; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_232)begin - if(_zz_233)begin - if(_zz_137)begin - decode_RS1 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_234)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_139)begin - decode_RS1 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_235)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_141)begin - decode_RS1 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_32 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_32 = _zz_131; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_32 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_236)begin - _zz_32 = memory_DivPlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_33; - assign execute_SHIFT_CTRL = _zz_34; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_35 = execute_PC; - assign execute_SRC2_CTRL = _zz_36; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; assign execute_IS_RVC = decode_to_execute_IS_RVC; - assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_304[0]; - assign decode_SRC_ADD_ZERO = _zz_305[0]; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_RS2_SIGNED[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_RS2_SIGNED[17]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_38; - assign execute_SRC2 = _zz_129; - assign execute_SRC1 = _zz_124; - assign execute_ALU_BITWISE_CTRL = _zz_39; - assign _zz_40 = writeBack_INSTRUCTION; - assign _zz_41 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_42 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_42 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_decompressor_output_payload_rsp_inst); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_306[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_RS2_SIGNED[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_371) == 32'h00001073),{(_zz_372 == _zz_373),{_zz_374,{_zz_375,_zz_376}}}}}}} != 21'h0); - always @ (*) begin - _zz_50 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_50 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 23'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_276) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_50 = _zz_343; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_50 = _zz_344; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_LRSC = memory_to_writeBack_MEMORY_LRSC; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; @@ -2759,48 +2942,49 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_307[0]; - assign decode_FLUSH_ALL = _zz_308[0]; - always @ (*) begin + assign decode_MEMORY_LRSC = _zz_decode_IS_RS2_SIGNED[15]; + assign decode_MEMORY_ENABLE = _zz_decode_IS_RS2_SIGNED[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_RS2_SIGNED[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_237)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_238)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_239)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_240)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_51; - always @ (*) begin - _zz_52 = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_52 = BranchPlugin_jumpInterface_payload; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_53 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_53 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end @@ -2809,12 +2993,12 @@ module VexRiscv ( assign decode_IS_RVC = IBusCachedPlugin_injector_decodeInput_payload_isRvc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end - case(_zz_166) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2823,163 +3007,163 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_132 || _zz_133)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_241)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_241)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_226 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_242)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_231)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_243)begin + if(when_DebugPlugin_l284) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_243)begin - if(_zz_244)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushIt = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_243)begin - if(_zz_244)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushNext = 1'b1; end end - if(_zz_165)begin + if(_zz_3) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_236)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_245)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_246)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2988,78 +3172,80 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_245)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_246)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_243)begin - if(_zz_244)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_247)begin + if(when_DebugPlugin_l300) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_valid)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_valid) begin IBusCachedPlugin_incomingInstruction = 1'b1; end - if(IBusCachedPlugin_injector_decodeInput_valid)begin + if(IBusCachedPlugin_injector_decodeInput_valid) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin - _zz_54 = 1'b0; - if(DebugPlugin_godmode)begin - _zz_54 = 1'b1; + always @(*) begin + _zz_when_DBusCachedPlugin_l386 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l386 = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_242)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin CsrPlugin_thirdPartyWake = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_245)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_246)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_245)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_246)begin - case(_zz_248) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3069,97 +3255,111 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_forceMachineWire = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + if(when_DebugPlugin_l316) begin CsrPlugin_allowInterrupts = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_allowException = 1'b0; end end + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_55 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_56 = (_zz_55 & (~ _zz_309)); - assign _zz_57 = _zz_56[3]; - assign _zz_58 = (_zz_56[1] || _zz_57); - assign _zz_59 = (_zz_56[2] || _zz_57); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_230; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_311); - if(IBusCachedPlugin_fetchPc_inc)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_inc) begin IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodePc_flushed = 1'b0; - if(_zz_249)begin + if(when_Fetcher_l192) begin IBusCachedPlugin_decodePc_flushed = 1'b1; end end - assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_313); - always @ (*) begin + assign IBusCachedPlugin_decodePc_pcPlus = (IBusCachedPlugin_decodePc_pcReg + _zz_IBusCachedPlugin_decodePc_pcPlus); + always @(*) begin IBusCachedPlugin_decodePc_injectedDecode = 1'b0; - if((_zz_166 != 3'b000))begin + if(when_Fetcher_l360) begin IBusCachedPlugin_decodePc_injectedDecode = 1'b1; end end - always @ (*) begin + assign when_Fetcher_l180 = (decode_arbitration_isFiring && (! IBusCachedPlugin_decodePc_injectedDecode)); + assign when_Fetcher_l192 = (IBusCachedPlugin_jump_pcLoad_valid && ((! decode_arbitration_isStuck) || decode_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3167,48 +3367,48 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_60); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_60); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_61); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_61); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - if(IBusCachedPlugin_decompressor_throw2BytesReg)begin + if(IBusCachedPlugin_decompressor_throw2BytesReg) begin IBusCachedPlugin_fetchPc_redo_payload[1] = 1'b1; end end assign IBusCachedPlugin_iBusRsp_flush = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_62; - assign _zz_62 = ((1'b0 && (! _zz_63)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_63 = _zz_64; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_63; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if(IBusCachedPlugin_injector_decodeInput_valid)begin + if(IBusCachedPlugin_injector_decodeInput_valid) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end @@ -3225,190 +3425,195 @@ module VexRiscv ( assign IBusCachedPlugin_decompressor_isInputHighRvc = (IBusCachedPlugin_decompressor_input_payload_rsp_inst[17 : 16] != 2'b11); assign IBusCachedPlugin_decompressor_throw2Bytes = (IBusCachedPlugin_decompressor_throw2BytesReg || IBusCachedPlugin_decompressor_input_payload_pc[1]); assign IBusCachedPlugin_decompressor_unaligned = (IBusCachedPlugin_decompressor_throw2Bytes || IBusCachedPlugin_decompressor_bufferValid); - assign IBusCachedPlugin_decompressor_raw = (IBusCachedPlugin_decompressor_bufferValid ? {IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0],IBusCachedPlugin_decompressor_bufferData} : {IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16],(IBusCachedPlugin_decompressor_throw2Bytes ? IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16] : IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0])}); + assign IBusCachedPlugin_decompressor_bufferValidPatched = (IBusCachedPlugin_decompressor_input_valid ? IBusCachedPlugin_decompressor_bufferValid : IBusCachedPlugin_decompressor_bufferValidLatch); + assign IBusCachedPlugin_decompressor_throw2BytesPatched = (IBusCachedPlugin_decompressor_input_valid ? IBusCachedPlugin_decompressor_throw2Bytes : IBusCachedPlugin_decompressor_throw2BytesLatch); + assign IBusCachedPlugin_decompressor_raw = (IBusCachedPlugin_decompressor_bufferValidPatched ? {IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0],IBusCachedPlugin_decompressor_bufferData} : {IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16],(IBusCachedPlugin_decompressor_throw2BytesPatched ? IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16] : IBusCachedPlugin_decompressor_input_payload_rsp_inst[15 : 0])}); assign IBusCachedPlugin_decompressor_isRvc = (IBusCachedPlugin_decompressor_raw[1 : 0] != 2'b11); - assign _zz_65 = IBusCachedPlugin_decompressor_raw[15 : 0]; - always @ (*) begin - IBusCachedPlugin_decompressor_decompressed = 32'h0; - case(_zz_271) + assign _zz_IBusCachedPlugin_decompressor_decompressed = IBusCachedPlugin_decompressor_raw[15 : 0]; + always @(*) begin + IBusCachedPlugin_decompressor_decompressed = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(switch_Misc_l44) 5'h0 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{{{2'b00,_zz_65[10 : 7]},_zz_65[12 : 11]},_zz_65[5]},_zz_65[6]},2'b00},5'h02},3'b000},_zz_67},7'h13}; + IBusCachedPlugin_decompressor_decompressed = {{{{{{{{{2'b00,_zz_IBusCachedPlugin_decompressor_decompressed[10 : 7]},_zz_IBusCachedPlugin_decompressor_decompressed[12 : 11]},_zz_IBusCachedPlugin_decompressor_decompressed[5]},_zz_IBusCachedPlugin_decompressor_decompressed[6]},2'b00},5'h02},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed_2},7'h13}; end 5'h02 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_68,_zz_66},3'b010},_zz_67},7'h03}; + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_IBusCachedPlugin_decompressor_decompressed_3,_zz_IBusCachedPlugin_decompressor_decompressed_1},3'b010},_zz_IBusCachedPlugin_decompressor_decompressed_2},7'h03}; end 5'h06 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_68[11 : 5],_zz_67},_zz_66},3'b010},_zz_68[4 : 0]},7'h23}; + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_3[11 : 5],_zz_IBusCachedPlugin_decompressor_decompressed_2},_zz_IBusCachedPlugin_decompressor_decompressed_1},3'b010},_zz_IBusCachedPlugin_decompressor_decompressed_3[4 : 0]},7'h23}; end 5'h08 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_70,_zz_65[11 : 7]},3'b000},_zz_65[11 : 7]},7'h13}; + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_IBusCachedPlugin_decompressor_decompressed_5,_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h13}; end 5'h09 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_73[20],_zz_73[10 : 1]},_zz_73[11]},_zz_73[19 : 12]},_zz_85},7'h6f}; + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_8[20],_zz_IBusCachedPlugin_decompressor_decompressed_8[10 : 1]},_zz_IBusCachedPlugin_decompressor_decompressed_8[11]},_zz_IBusCachedPlugin_decompressor_decompressed_8[19 : 12]},_zz_IBusCachedPlugin_decompressor_decompressed_20},7'h6f}; end 5'h0a : begin - IBusCachedPlugin_decompressor_decompressed = {{{{_zz_70,5'h0},3'b000},_zz_65[11 : 7]},7'h13}; + IBusCachedPlugin_decompressor_decompressed = {{{{_zz_IBusCachedPlugin_decompressor_decompressed_5,5'h0},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h13}; end 5'h0b : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_65[11 : 7] == 5'h02) ? {{{{{{{{{_zz_77,_zz_65[4 : 3]},_zz_65[5]},_zz_65[2]},_zz_65[6]},4'b0000},_zz_65[11 : 7]},3'b000},_zz_65[11 : 7]},7'h13} : {{_zz_314[31 : 12],_zz_65[11 : 7]},7'h37}); + IBusCachedPlugin_decompressor_decompressed = ((_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7] == 5'h02) ? {{{{{{{{{_zz_IBusCachedPlugin_decompressor_decompressed_12,_zz_IBusCachedPlugin_decompressor_decompressed[4 : 3]},_zz_IBusCachedPlugin_decompressor_decompressed[5]},_zz_IBusCachedPlugin_decompressor_decompressed[2]},_zz_IBusCachedPlugin_decompressor_decompressed[6]},4'b0000},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h13} : {{_zz_IBusCachedPlugin_decompressor_decompressed_27[31 : 12],_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h37}); end 5'h0c : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_65[11 : 10] == 2'b10) ? _zz_91 : {{1'b0,(_zz_389 || _zz_390)},5'h0}),(((! _zz_65[11]) || _zz_87) ? _zz_65[6 : 2] : _zz_67)},_zz_66},_zz_89},_zz_66},(_zz_87 ? 7'h13 : 7'h33)}; + IBusCachedPlugin_decompressor_decompressed = {{{{{((_zz_IBusCachedPlugin_decompressor_decompressed[11 : 10] == 2'b10) ? _zz_IBusCachedPlugin_decompressor_decompressed_26 : {{1'b0,(_zz_IBusCachedPlugin_decompressor_decompressed_28 || _zz_IBusCachedPlugin_decompressor_decompressed_29)},5'h0}),(((! _zz_IBusCachedPlugin_decompressor_decompressed[11]) || _zz_IBusCachedPlugin_decompressor_decompressed_22) ? _zz_IBusCachedPlugin_decompressor_decompressed[6 : 2] : _zz_IBusCachedPlugin_decompressor_decompressed_2)},_zz_IBusCachedPlugin_decompressor_decompressed_1},_zz_IBusCachedPlugin_decompressor_decompressed_24},_zz_IBusCachedPlugin_decompressor_decompressed_1},(_zz_IBusCachedPlugin_decompressor_decompressed_22 ? 7'h13 : 7'h33)}; end 5'h0d : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_80[20],_zz_80[10 : 1]},_zz_80[11]},_zz_80[19 : 12]},_zz_84},7'h6f}; + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_15[20],_zz_IBusCachedPlugin_decompressor_decompressed_15[10 : 1]},_zz_IBusCachedPlugin_decompressor_decompressed_15[11]},_zz_IBusCachedPlugin_decompressor_decompressed_15[19 : 12]},_zz_IBusCachedPlugin_decompressor_decompressed_19},7'h6f}; end 5'h0e : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_83[12],_zz_83[10 : 5]},_zz_84},_zz_66},3'b000},_zz_83[4 : 1]},_zz_83[11]},7'h63}; + IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_IBusCachedPlugin_decompressor_decompressed_18[12],_zz_IBusCachedPlugin_decompressor_decompressed_18[10 : 5]},_zz_IBusCachedPlugin_decompressor_decompressed_19},_zz_IBusCachedPlugin_decompressor_decompressed_1},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed_18[4 : 1]},_zz_IBusCachedPlugin_decompressor_decompressed_18[11]},7'h63}; end 5'h0f : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_83[12],_zz_83[10 : 5]},_zz_84},_zz_66},3'b001},_zz_83[4 : 1]},_zz_83[11]},7'h63}; + IBusCachedPlugin_decompressor_decompressed = {{{{{{{_zz_IBusCachedPlugin_decompressor_decompressed_18[12],_zz_IBusCachedPlugin_decompressor_decompressed_18[10 : 5]},_zz_IBusCachedPlugin_decompressor_decompressed_19},_zz_IBusCachedPlugin_decompressor_decompressed_1},3'b001},_zz_IBusCachedPlugin_decompressor_decompressed_18[4 : 1]},_zz_IBusCachedPlugin_decompressor_decompressed_18[11]},7'h63}; end 5'h10 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{7'h0,_zz_65[6 : 2]},_zz_65[11 : 7]},3'b001},_zz_65[11 : 7]},7'h13}; + IBusCachedPlugin_decompressor_decompressed = {{{{{7'h0,_zz_IBusCachedPlugin_decompressor_decompressed[6 : 2]},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},3'b001},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h13}; end 5'h12 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{{{{4'b0000,_zz_65[3 : 2]},_zz_65[12]},_zz_65[6 : 4]},2'b00},_zz_86},3'b010},_zz_65[11 : 7]},7'h03}; + IBusCachedPlugin_decompressor_decompressed = {{{{{{{{4'b0000,_zz_IBusCachedPlugin_decompressor_decompressed[3 : 2]},_zz_IBusCachedPlugin_decompressor_decompressed[12]},_zz_IBusCachedPlugin_decompressor_decompressed[6 : 4]},2'b00},_zz_IBusCachedPlugin_decompressor_decompressed_21},3'b010},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h03}; end 5'h14 : begin - IBusCachedPlugin_decompressor_decompressed = ((_zz_65[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_65[6 : 2] == 5'h0) ? {{{{12'h0,_zz_65[11 : 7]},3'b000},(_zz_65[12] ? _zz_85 : _zz_84)},7'h67} : {{{{{_zz_391,_zz_392},(_zz_393 ? _zz_394 : _zz_84)},3'b000},_zz_65[11 : 7]},7'h33})); + IBusCachedPlugin_decompressor_decompressed = ((_zz_IBusCachedPlugin_decompressor_decompressed[12 : 2] == 11'h400) ? 32'h00100073 : ((_zz_IBusCachedPlugin_decompressor_decompressed[6 : 2] == 5'h0) ? {{{{12'h0,_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},3'b000},(_zz_IBusCachedPlugin_decompressor_decompressed[12] ? _zz_IBusCachedPlugin_decompressor_decompressed_20 : _zz_IBusCachedPlugin_decompressor_decompressed_19)},7'h67} : {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_30,_zz_IBusCachedPlugin_decompressor_decompressed_31},(_zz_IBusCachedPlugin_decompressor_decompressed_32 ? _zz_IBusCachedPlugin_decompressor_decompressed_33 : _zz_IBusCachedPlugin_decompressor_decompressed_19)},3'b000},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 7]},7'h33})); end 5'h16 : begin - IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_315[11 : 5],_zz_65[6 : 2]},_zz_86},3'b010},_zz_316[4 : 0]},7'h23}; + IBusCachedPlugin_decompressor_decompressed = {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_34[11 : 5],_zz_IBusCachedPlugin_decompressor_decompressed[6 : 2]},_zz_IBusCachedPlugin_decompressor_decompressed_21},3'b010},_zz_IBusCachedPlugin_decompressor_decompressed_35[4 : 0]},7'h23}; end default : begin end endcase end - assign _zz_66 = {2'b01,_zz_65[9 : 7]}; - assign _zz_67 = {2'b01,_zz_65[4 : 2]}; - assign _zz_68 = {{{{5'h0,_zz_65[5]},_zz_65[12 : 10]},_zz_65[6]},2'b00}; - assign _zz_69 = _zz_65[12]; - always @ (*) begin - _zz_70[11] = _zz_69; - _zz_70[10] = _zz_69; - _zz_70[9] = _zz_69; - _zz_70[8] = _zz_69; - _zz_70[7] = _zz_69; - _zz_70[6] = _zz_69; - _zz_70[5] = _zz_69; - _zz_70[4 : 0] = _zz_65[6 : 2]; - end - - assign _zz_71 = _zz_65[12]; - always @ (*) begin - _zz_72[9] = _zz_71; - _zz_72[8] = _zz_71; - _zz_72[7] = _zz_71; - _zz_72[6] = _zz_71; - _zz_72[5] = _zz_71; - _zz_72[4] = _zz_71; - _zz_72[3] = _zz_71; - _zz_72[2] = _zz_71; - _zz_72[1] = _zz_71; - _zz_72[0] = _zz_71; - end - - assign _zz_73 = {{{{{{{{_zz_72,_zz_65[8]},_zz_65[10 : 9]},_zz_65[6]},_zz_65[7]},_zz_65[2]},_zz_65[11]},_zz_65[5 : 3]},1'b0}; - assign _zz_74 = _zz_65[12]; - always @ (*) begin - _zz_75[14] = _zz_74; - _zz_75[13] = _zz_74; - _zz_75[12] = _zz_74; - _zz_75[11] = _zz_74; - _zz_75[10] = _zz_74; - _zz_75[9] = _zz_74; - _zz_75[8] = _zz_74; - _zz_75[7] = _zz_74; - _zz_75[6] = _zz_74; - _zz_75[5] = _zz_74; - _zz_75[4] = _zz_74; - _zz_75[3] = _zz_74; - _zz_75[2] = _zz_74; - _zz_75[1] = _zz_74; - _zz_75[0] = _zz_74; - end - - assign _zz_76 = _zz_65[12]; - always @ (*) begin - _zz_77[2] = _zz_76; - _zz_77[1] = _zz_76; - _zz_77[0] = _zz_76; - end - - assign _zz_78 = _zz_65[12]; - always @ (*) begin - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7] = _zz_78; - _zz_79[6] = _zz_78; - _zz_79[5] = _zz_78; - _zz_79[4] = _zz_78; - _zz_79[3] = _zz_78; - _zz_79[2] = _zz_78; - _zz_79[1] = _zz_78; - _zz_79[0] = _zz_78; - end - - assign _zz_80 = {{{{{{{{_zz_79,_zz_65[8]},_zz_65[10 : 9]},_zz_65[6]},_zz_65[7]},_zz_65[2]},_zz_65[11]},_zz_65[5 : 3]},1'b0}; - assign _zz_81 = _zz_65[12]; - always @ (*) begin - _zz_82[4] = _zz_81; - _zz_82[3] = _zz_81; - _zz_82[2] = _zz_81; - _zz_82[1] = _zz_81; - _zz_82[0] = _zz_81; - end - - assign _zz_83 = {{{{{_zz_82,_zz_65[6 : 5]},_zz_65[2]},_zz_65[11 : 10]},_zz_65[4 : 3]},1'b0}; - assign _zz_84 = 5'h0; - assign _zz_85 = 5'h01; - assign _zz_86 = 5'h02; - assign _zz_87 = (_zz_65[11 : 10] != 2'b11); - always @ (*) begin - case(_zz_272) + assign _zz_IBusCachedPlugin_decompressor_decompressed_1 = {2'b01,_zz_IBusCachedPlugin_decompressor_decompressed[9 : 7]}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_2 = {2'b01,_zz_IBusCachedPlugin_decompressor_decompressed[4 : 2]}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_3 = {{{{5'h0,_zz_IBusCachedPlugin_decompressor_decompressed[5]},_zz_IBusCachedPlugin_decompressor_decompressed[12 : 10]},_zz_IBusCachedPlugin_decompressor_decompressed[6]},2'b00}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_4 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_5[11] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[10] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[9] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[8] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[7] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[6] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[5] = _zz_IBusCachedPlugin_decompressor_decompressed_4; + _zz_IBusCachedPlugin_decompressor_decompressed_5[4 : 0] = _zz_IBusCachedPlugin_decompressor_decompressed[6 : 2]; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_6 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_7[9] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[8] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[7] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[6] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[5] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[4] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[3] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[2] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[1] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + _zz_IBusCachedPlugin_decompressor_decompressed_7[0] = _zz_IBusCachedPlugin_decompressor_decompressed_6; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_8 = {{{{{{{{_zz_IBusCachedPlugin_decompressor_decompressed_7,_zz_IBusCachedPlugin_decompressor_decompressed[8]},_zz_IBusCachedPlugin_decompressor_decompressed[10 : 9]},_zz_IBusCachedPlugin_decompressor_decompressed[6]},_zz_IBusCachedPlugin_decompressor_decompressed[7]},_zz_IBusCachedPlugin_decompressor_decompressed[2]},_zz_IBusCachedPlugin_decompressor_decompressed[11]},_zz_IBusCachedPlugin_decompressor_decompressed[5 : 3]},1'b0}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_9 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_10[14] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[13] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[12] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[11] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[10] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[9] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[8] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[7] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[6] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[5] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[4] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[3] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[2] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[1] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + _zz_IBusCachedPlugin_decompressor_decompressed_10[0] = _zz_IBusCachedPlugin_decompressor_decompressed_9; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_11 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_12[2] = _zz_IBusCachedPlugin_decompressor_decompressed_11; + _zz_IBusCachedPlugin_decompressor_decompressed_12[1] = _zz_IBusCachedPlugin_decompressor_decompressed_11; + _zz_IBusCachedPlugin_decompressor_decompressed_12[0] = _zz_IBusCachedPlugin_decompressor_decompressed_11; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_13 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_14[9] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[8] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[7] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[6] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[5] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[4] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[3] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[2] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[1] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + _zz_IBusCachedPlugin_decompressor_decompressed_14[0] = _zz_IBusCachedPlugin_decompressor_decompressed_13; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_15 = {{{{{{{{_zz_IBusCachedPlugin_decompressor_decompressed_14,_zz_IBusCachedPlugin_decompressor_decompressed[8]},_zz_IBusCachedPlugin_decompressor_decompressed[10 : 9]},_zz_IBusCachedPlugin_decompressor_decompressed[6]},_zz_IBusCachedPlugin_decompressor_decompressed[7]},_zz_IBusCachedPlugin_decompressor_decompressed[2]},_zz_IBusCachedPlugin_decompressor_decompressed[11]},_zz_IBusCachedPlugin_decompressor_decompressed[5 : 3]},1'b0}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_16 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_17[4] = _zz_IBusCachedPlugin_decompressor_decompressed_16; + _zz_IBusCachedPlugin_decompressor_decompressed_17[3] = _zz_IBusCachedPlugin_decompressor_decompressed_16; + _zz_IBusCachedPlugin_decompressor_decompressed_17[2] = _zz_IBusCachedPlugin_decompressor_decompressed_16; + _zz_IBusCachedPlugin_decompressor_decompressed_17[1] = _zz_IBusCachedPlugin_decompressor_decompressed_16; + _zz_IBusCachedPlugin_decompressor_decompressed_17[0] = _zz_IBusCachedPlugin_decompressor_decompressed_16; + end + + assign _zz_IBusCachedPlugin_decompressor_decompressed_18 = {{{{{_zz_IBusCachedPlugin_decompressor_decompressed_17,_zz_IBusCachedPlugin_decompressor_decompressed[6 : 5]},_zz_IBusCachedPlugin_decompressor_decompressed[2]},_zz_IBusCachedPlugin_decompressor_decompressed[11 : 10]},_zz_IBusCachedPlugin_decompressor_decompressed[4 : 3]},1'b0}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_19 = 5'h0; + assign _zz_IBusCachedPlugin_decompressor_decompressed_20 = 5'h01; + assign _zz_IBusCachedPlugin_decompressor_decompressed_21 = 5'h02; + assign switch_Misc_l44 = {_zz_IBusCachedPlugin_decompressor_decompressed[1 : 0],_zz_IBusCachedPlugin_decompressor_decompressed[15 : 13]}; + assign _zz_IBusCachedPlugin_decompressor_decompressed_22 = (_zz_IBusCachedPlugin_decompressor_decompressed[11 : 10] != 2'b11); + assign switch_Misc_l200 = _zz_IBusCachedPlugin_decompressor_decompressed[11 : 10]; + assign switch_Misc_l200_1 = _zz_IBusCachedPlugin_decompressor_decompressed[6 : 5]; + always @(*) begin + case(switch_Misc_l200_1) 2'b00 : begin - _zz_88 = 3'b000; + _zz_IBusCachedPlugin_decompressor_decompressed_23 = 3'b000; end 2'b01 : begin - _zz_88 = 3'b100; + _zz_IBusCachedPlugin_decompressor_decompressed_23 = 3'b100; end 2'b10 : begin - _zz_88 = 3'b110; + _zz_IBusCachedPlugin_decompressor_decompressed_23 = 3'b110; end default : begin - _zz_88 = 3'b111; + _zz_IBusCachedPlugin_decompressor_decompressed_23 = 3'b111; end endcase end - always @ (*) begin - case(_zz_273) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - _zz_89 = 3'b101; + _zz_IBusCachedPlugin_decompressor_decompressed_24 = 3'b101; end 2'b01 : begin - _zz_89 = 3'b101; + _zz_IBusCachedPlugin_decompressor_decompressed_24 = 3'b101; end 2'b10 : begin - _zz_89 = 3'b111; + _zz_IBusCachedPlugin_decompressor_decompressed_24 = 3'b111; end default : begin - _zz_89 = _zz_88; + _zz_IBusCachedPlugin_decompressor_decompressed_24 = _zz_IBusCachedPlugin_decompressor_decompressed_23; end endcase end - assign _zz_90 = _zz_65[12]; - always @ (*) begin - _zz_91[6] = _zz_90; - _zz_91[5] = _zz_90; - _zz_91[4] = _zz_90; - _zz_91[3] = _zz_90; - _zz_91[2] = _zz_90; - _zz_91[1] = _zz_90; - _zz_91[0] = _zz_90; + assign _zz_IBusCachedPlugin_decompressor_decompressed_25 = _zz_IBusCachedPlugin_decompressor_decompressed[12]; + always @(*) begin + _zz_IBusCachedPlugin_decompressor_decompressed_26[6] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[5] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[4] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[3] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[2] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[1] = _zz_IBusCachedPlugin_decompressor_decompressed_25; + _zz_IBusCachedPlugin_decompressor_decompressed_26[0] = _zz_IBusCachedPlugin_decompressor_decompressed_25; end assign IBusCachedPlugin_decompressor_output_valid = (IBusCachedPlugin_decompressor_input_valid && (! ((IBusCachedPlugin_decompressor_throw2Bytes && (! IBusCachedPlugin_decompressor_bufferValid)) && (! IBusCachedPlugin_decompressor_isInputHighRvc)))); @@ -3416,21 +3621,29 @@ module VexRiscv ( assign IBusCachedPlugin_decompressor_output_payload_isRvc = IBusCachedPlugin_decompressor_isRvc; assign IBusCachedPlugin_decompressor_output_payload_rsp_inst = (IBusCachedPlugin_decompressor_isRvc ? IBusCachedPlugin_decompressor_decompressed : IBusCachedPlugin_decompressor_raw); assign IBusCachedPlugin_decompressor_input_ready = (IBusCachedPlugin_decompressor_output_ready && (((! IBusCachedPlugin_iBusRsp_stages_1_input_valid) || IBusCachedPlugin_decompressor_flushNext) || ((! (IBusCachedPlugin_decompressor_bufferValid && IBusCachedPlugin_decompressor_isInputHighRvc)) && (! (((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && IBusCachedPlugin_decompressor_isInputHighRvc))))); + assign IBusCachedPlugin_decompressor_output_fire = (IBusCachedPlugin_decompressor_output_valid && IBusCachedPlugin_decompressor_output_ready); assign IBusCachedPlugin_decompressor_bufferFill = (((((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && (! IBusCachedPlugin_decompressor_isInputHighRvc)) || (IBusCachedPlugin_decompressor_bufferValid && (! IBusCachedPlugin_decompressor_isInputHighRvc))) || ((IBusCachedPlugin_decompressor_throw2Bytes && (! IBusCachedPlugin_decompressor_isRvc)) && (! IBusCachedPlugin_decompressor_isInputHighRvc))); + assign when_Fetcher_l283 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); + assign when_Fetcher_l286 = (IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid); + assign when_Fetcher_l291 = (IBusCachedPlugin_externalFlush || IBusCachedPlugin_decompressor_consumeCurrent); assign IBusCachedPlugin_decompressor_output_ready = ((1'b0 && (! IBusCachedPlugin_injector_decodeInput_valid)) || IBusCachedPlugin_injector_decodeInput_ready); - assign IBusCachedPlugin_injector_decodeInput_valid = _zz_92; - assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_93; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_94; - assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_95; - assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_96; + assign IBusCachedPlugin_injector_decodeInput_valid = _zz_IBusCachedPlugin_injector_decodeInput_valid; + assign IBusCachedPlugin_injector_decodeInput_payload_pc = _zz_IBusCachedPlugin_injector_decodeInput_payload_pc; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_error = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error; + assign IBusCachedPlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst; + assign IBusCachedPlugin_injector_decodeInput_payload_isRvc = _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc; + assign when_Fetcher_l329 = (! 1'b0); + assign when_Fetcher_l329_1 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_2 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - always @ (*) begin + always @(*) begin decode_arbitration_isValid = IBusCachedPlugin_injector_decodeInput_valid; - case(_zz_166) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3442,150 +3655,162 @@ module VexRiscv ( endcase end - assign _zz_97 = _zz_317[11]; - always @ (*) begin - _zz_98[18] = _zz_97; - _zz_98[17] = _zz_97; - _zz_98[16] = _zz_97; - _zz_98[15] = _zz_97; - _zz_98[14] = _zz_97; - _zz_98[13] = _zz_97; - _zz_98[12] = _zz_97; - _zz_98[11] = _zz_97; - _zz_98[10] = _zz_97; - _zz_98[9] = _zz_97; - _zz_98[8] = _zz_97; - _zz_98[7] = _zz_97; - _zz_98[6] = _zz_97; - _zz_98[5] = _zz_97; - _zz_98[4] = _zz_97; - _zz_98[3] = _zz_97; - _zz_98[2] = _zz_97; - _zz_98[1] = _zz_97; - _zz_98[0] = _zz_97; - end - - assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_318[31])); + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + assign IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_99 = _zz_319[19]; - always @ (*) begin - _zz_100[10] = _zz_99; - _zz_100[9] = _zz_99; - _zz_100[8] = _zz_99; - _zz_100[7] = _zz_99; - _zz_100[6] = _zz_99; - _zz_100[5] = _zz_99; - _zz_100[4] = _zz_99; - _zz_100[3] = _zz_99; - _zz_100[2] = _zz_99; - _zz_100[1] = _zz_99; - _zz_100[0] = _zz_99; - end - - assign _zz_101 = _zz_320[11]; - always @ (*) begin - _zz_102[18] = _zz_101; - _zz_102[17] = _zz_101; - _zz_102[16] = _zz_101; - _zz_102[15] = _zz_101; - _zz_102[14] = _zz_101; - _zz_102[13] = _zz_101; - _zz_102[12] = _zz_101; - _zz_102[11] = _zz_101; - _zz_102[10] = _zz_101; - _zz_102[9] = _zz_101; - _zz_102[8] = _zz_101; - _zz_102[7] = _zz_101; - _zz_102[6] = _zz_101; - _zz_102[5] = _zz_101; - _zz_102[4] = _zz_101; - _zz_102[3] = _zz_101; - _zz_102[2] = _zz_101; - _zz_102[1] = _zz_101; - _zz_102[0] = _zz_101; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_100,{{{_zz_395,_zz_396},_zz_397},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_102,{{{_zz_398,_zz_399},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,_zz_IBusCachedPlugin_predictionJumpInterface_payload_5},_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_7,_zz_IBusCachedPlugin_predictionJumpInterface_payload_8},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_200 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_201 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_202 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_201; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_204 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_fetch_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_240)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_238)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_208 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); - if(_zz_238)begin - _zz_208 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_239)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_237)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_239)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_237)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_1_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_fetch_isValid && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_fetch_isValid && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_fetch_isValid && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_fetch_isValid && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_1_output_valid; assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_1_output_payload; - assign _zz_199 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_227 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3593,168 +3818,203 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + always @(*) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + if(when_DBusCachedPlugin_l311) begin + if(decode_MEMORY_LRSC) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b1; + end + end + end + + assign when_DBusCachedPlugin_l311 = decode_INSTRUCTION[25]; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_209 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_210 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_105 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_105 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_105 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_211 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_212 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_211; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + always @(*) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b0; + if(execute_MEMORY_LRSC) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b1; + end + end + + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_212; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_213 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_54 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_213 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; end end - assign _zz_214 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_215 = (CsrPlugin_privilege == 2'b00); - assign _zz_216 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_250)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_250)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_250)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_321}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_322}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; end - assign _zz_106 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_107[31] = _zz_106; - _zz_107[30] = _zz_106; - _zz_107[29] = _zz_106; - _zz_107[28] = _zz_106; - _zz_107[27] = _zz_106; - _zz_107[26] = _zz_106; - _zz_107[25] = _zz_106; - _zz_107[24] = _zz_106; - _zz_107[23] = _zz_106; - _zz_107[22] = _zz_106; - _zz_107[21] = _zz_106; - _zz_107[20] = _zz_106; - _zz_107[19] = _zz_106; - _zz_107[18] = _zz_106; - _zz_107[17] = _zz_106; - _zz_107[16] = _zz_106; - _zz_107[15] = _zz_106; - _zz_107[14] = _zz_106; - _zz_107[13] = _zz_106; - _zz_107[12] = _zz_106; - _zz_107[11] = _zz_106; - _zz_107[10] = _zz_106; - _zz_107[9] = _zz_106; - _zz_107[8] = _zz_106; - _zz_107[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_108 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_109[31] = _zz_108; - _zz_109[30] = _zz_108; - _zz_109[29] = _zz_108; - _zz_109[28] = _zz_108; - _zz_109[27] = _zz_108; - _zz_109[26] = _zz_108; - _zz_109[25] = _zz_108; - _zz_109[24] = _zz_108; - _zz_109[23] = _zz_108; - _zz_109[22] = _zz_108; - _zz_109[21] = _zz_108; - _zz_109[20] = _zz_108; - _zz_109[19] = _zz_108; - _zz_109[18] = _zz_108; - _zz_109[17] = _zz_108; - _zz_109[16] = _zz_108; - _zz_109[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_274) + always @(*) begin + writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + if(when_DBusCachedPlugin_l474) begin + writeBack_DBusCachedPlugin_rspRf = {31'd0, _zz_writeBack_DBusCachedPlugin_rspRf}; + end + end + + assign when_DBusCachedPlugin_l474 = (writeBack_MEMORY_LRSC && writeBack_MEMORY_WR); + assign switch_Misc_l200_2 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200_2) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_107; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_109; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3773,59 +4033,62 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_111 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_112 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_113 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_114 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_110 = {(((decode_INSTRUCTION & _zz_400) == 32'h00100050) != 1'b0),{(_zz_114 != 1'b0),{(_zz_114 != 1'b0),{(_zz_401 != _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; - assign _zz_115 = _zz_110[2 : 1]; - assign _zz_49 = _zz_115; - assign _zz_116 = _zz_110[7 : 6]; - assign _zz_48 = _zz_116; - assign _zz_117 = _zz_110[9 : 8]; - assign _zz_47 = _zz_117; - assign _zz_118 = _zz_110[19 : 18]; - assign _zz_46 = _zz_118; - assign _zz_119 = _zz_110[22 : 21]; - assign _zz_45 = _zz_119; - assign _zz_120 = _zz_110[24 : 23]; - assign _zz_44 = _zz_120; - assign _zz_121 = _zz_110[27 : 26]; - assign _zz_43 = _zz_121; + assign _zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); + assign _zz_decode_IS_RS2_SIGNED_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_5 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_6 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_IS_RS2_SIGNED = {(((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED) == 32'h00100050) != 1'b0),{(_zz_decode_IS_RS2_SIGNED_6 != 1'b0),{(_zz_decode_IS_RS2_SIGNED_6 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_1 != _zz__zz_decode_IS_RS2_SIGNED_2),{_zz__zz_decode_IS_RS2_SIGNED_3,{_zz__zz_decode_IS_RS2_SIGNED_5,_zz__zz_decode_IS_RS2_SIGNED_8}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_RS2_SIGNED[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_RS2_SIGNED[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_RS2_SIGNED[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_RS2_SIGNED[21 : 20]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_RS2_SIGNED[23 : 22]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_RS2_SIGNED[25 : 24]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_RS2_SIGNED[28 : 27]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_228; - assign decode_RegFilePlugin_rs2Data = _zz_229; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); - if(_zz_122)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; - if(_zz_122)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_50; - if(_zz_122)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_2) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3834,279 +4097,302 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_123 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_123 = {31'd0, _zz_323}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_123 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_124 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_124 = {29'd0, _zz_324}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_124 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_124 = {27'd0, _zz_325}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_125 = _zz_326[11]; - always @ (*) begin - _zz_126[19] = _zz_125; - _zz_126[18] = _zz_125; - _zz_126[17] = _zz_125; - _zz_126[16] = _zz_125; - _zz_126[15] = _zz_125; - _zz_126[14] = _zz_125; - _zz_126[13] = _zz_125; - _zz_126[12] = _zz_125; - _zz_126[11] = _zz_125; - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; - end - - assign _zz_127 = _zz_327[11]; - always @ (*) begin - _zz_128[19] = _zz_127; - _zz_128[18] = _zz_127; - _zz_128[17] = _zz_127; - _zz_128[16] = _zz_127; - _zz_128[15] = _zz_127; - _zz_128[14] = _zz_127; - _zz_128[13] = _zz_127; - _zz_128[12] = _zz_127; - _zz_128[11] = _zz_127; - _zz_128[10] = _zz_127; - _zz_128[9] = _zz_127; - _zz_128[8] = _zz_127; - _zz_128[7] = _zz_127; - _zz_128[6] = _zz_127; - _zz_128[5] = _zz_127; - _zz_128[4] = _zz_127; - _zz_128[3] = _zz_127; - _zz_128[2] = _zz_127; - _zz_128[1] = _zz_127; - _zz_128[0] = _zz_127; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_129 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_129 = {_zz_126,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_129 = {_zz_128,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_129 = _zz_35; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_328; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_130[0] = execute_SRC1[31]; - _zz_130[1] = execute_SRC1[30]; - _zz_130[2] = execute_SRC1[29]; - _zz_130[3] = execute_SRC1[28]; - _zz_130[4] = execute_SRC1[27]; - _zz_130[5] = execute_SRC1[26]; - _zz_130[6] = execute_SRC1[25]; - _zz_130[7] = execute_SRC1[24]; - _zz_130[8] = execute_SRC1[23]; - _zz_130[9] = execute_SRC1[22]; - _zz_130[10] = execute_SRC1[21]; - _zz_130[11] = execute_SRC1[20]; - _zz_130[12] = execute_SRC1[19]; - _zz_130[13] = execute_SRC1[18]; - _zz_130[14] = execute_SRC1[17]; - _zz_130[15] = execute_SRC1[16]; - _zz_130[16] = execute_SRC1[15]; - _zz_130[17] = execute_SRC1[14]; - _zz_130[18] = execute_SRC1[13]; - _zz_130[19] = execute_SRC1[12]; - _zz_130[20] = execute_SRC1[11]; - _zz_130[21] = execute_SRC1[10]; - _zz_130[22] = execute_SRC1[9]; - _zz_130[23] = execute_SRC1[8]; - _zz_130[24] = execute_SRC1[7]; - _zz_130[25] = execute_SRC1[6]; - _zz_130[26] = execute_SRC1[5]; - _zz_130[27] = execute_SRC1[4]; - _zz_130[28] = execute_SRC1[3]; - _zz_130[29] = execute_SRC1[2]; - _zz_130[30] = execute_SRC1[1]; - _zz_130[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_130 : execute_SRC1); - always @ (*) begin - _zz_131[0] = memory_SHIFT_RIGHT[31]; - _zz_131[1] = memory_SHIFT_RIGHT[30]; - _zz_131[2] = memory_SHIFT_RIGHT[29]; - _zz_131[3] = memory_SHIFT_RIGHT[28]; - _zz_131[4] = memory_SHIFT_RIGHT[27]; - _zz_131[5] = memory_SHIFT_RIGHT[26]; - _zz_131[6] = memory_SHIFT_RIGHT[25]; - _zz_131[7] = memory_SHIFT_RIGHT[24]; - _zz_131[8] = memory_SHIFT_RIGHT[23]; - _zz_131[9] = memory_SHIFT_RIGHT[22]; - _zz_131[10] = memory_SHIFT_RIGHT[21]; - _zz_131[11] = memory_SHIFT_RIGHT[20]; - _zz_131[12] = memory_SHIFT_RIGHT[19]; - _zz_131[13] = memory_SHIFT_RIGHT[18]; - _zz_131[14] = memory_SHIFT_RIGHT[17]; - _zz_131[15] = memory_SHIFT_RIGHT[16]; - _zz_131[16] = memory_SHIFT_RIGHT[15]; - _zz_131[17] = memory_SHIFT_RIGHT[14]; - _zz_131[18] = memory_SHIFT_RIGHT[13]; - _zz_131[19] = memory_SHIFT_RIGHT[12]; - _zz_131[20] = memory_SHIFT_RIGHT[11]; - _zz_131[21] = memory_SHIFT_RIGHT[10]; - _zz_131[22] = memory_SHIFT_RIGHT[9]; - _zz_131[23] = memory_SHIFT_RIGHT[8]; - _zz_131[24] = memory_SHIFT_RIGHT[7]; - _zz_131[25] = memory_SHIFT_RIGHT[6]; - _zz_131[26] = memory_SHIFT_RIGHT[5]; - _zz_131[27] = memory_SHIFT_RIGHT[4]; - _zz_131[28] = memory_SHIFT_RIGHT[3]; - _zz_131[29] = memory_SHIFT_RIGHT[2]; - _zz_131[30] = memory_SHIFT_RIGHT[1]; - _zz_131[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_132 = 1'b0; - if(_zz_251)begin - if(_zz_252)begin - if(_zz_137)begin - _zz_132 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_253)begin - if(_zz_254)begin - if(_zz_139)begin - _zz_132 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_255)begin - if(_zz_256)begin - if(_zz_141)begin - _zz_132 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_132 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_133 = 1'b0; - if(_zz_251)begin - if(_zz_252)begin - if(_zz_138)begin - _zz_133 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_253)begin - if(_zz_254)begin - if(_zz_140)begin - _zz_133 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_255)begin - if(_zz_256)begin - if(_zz_142)begin - _zz_133 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_133 = 1'b0; - end - end - - assign _zz_137 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_138 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_139 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_140 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_141 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_142 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_143 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_143 == 3'b000)) begin - _zz_144 = execute_BranchPlugin_eq; - end else if((_zz_143 == 3'b001)) begin - _zz_144 = (! execute_BranchPlugin_eq); - end else if((((_zz_143 & 3'b101) == 3'b101))) begin - _zz_144 = (! execute_SRC_LESS); - end else begin - _zz_144 = execute_SRC_LESS; - end + assign switch_Misc_l200_3 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_3) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_145 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_145 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_145 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_145 = _zz_144; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end assign execute_BranchPlugin_missAlignedTarget = 1'b0; - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -4115,169 +4401,183 @@ module VexRiscv ( endcase end - assign _zz_146 = _zz_335[11]; - always @ (*) begin - _zz_147[19] = _zz_146; - _zz_147[18] = _zz_146; - _zz_147[17] = _zz_146; - _zz_147[16] = _zz_146; - _zz_147[15] = _zz_146; - _zz_147[14] = _zz_146; - _zz_147[13] = _zz_146; - _zz_147[12] = _zz_146; - _zz_147[11] = _zz_146; - _zz_147[10] = _zz_146; - _zz_147[9] = _zz_146; - _zz_147[8] = _zz_146; - _zz_147[7] = _zz_146; - _zz_147[6] = _zz_146; - _zz_147[5] = _zz_146; - _zz_147[4] = _zz_146; - _zz_147[3] = _zz_146; - _zz_147[2] = _zz_146; - _zz_147[1] = _zz_146; - _zz_147[0] = _zz_146; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_147,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_149,{{{_zz_564,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_151,{{{_zz_565,_zz_566},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_338}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_148 = _zz_336[19]; - always @ (*) begin - _zz_149[10] = _zz_148; - _zz_149[9] = _zz_148; - _zz_149[8] = _zz_148; - _zz_149[7] = _zz_148; - _zz_149[6] = _zz_148; - _zz_149[5] = _zz_148; - _zz_149[4] = _zz_148; - _zz_149[3] = _zz_148; - _zz_149[2] = _zz_148; - _zz_149[1] = _zz_148; - _zz_149[0] = _zz_148; - end - - assign _zz_150 = _zz_337[11]; - always @ (*) begin - _zz_151[18] = _zz_150; - _zz_151[17] = _zz_150; - _zz_151[16] = _zz_150; - _zz_151[15] = _zz_150; - _zz_151[14] = _zz_150; - _zz_151[13] = _zz_150; - _zz_151[12] = _zz_150; - _zz_151[11] = _zz_150; - _zz_151[10] = _zz_150; - _zz_151[9] = _zz_150; - _zz_151[8] = _zz_150; - _zz_151[7] = _zz_150; - _zz_151[6] = _zz_150; - _zz_151[5] = _zz_150; - _zz_151[4] = _zz_150; - _zz_151[3] = _zz_150; - _zz_151[2] = _zz_150; - _zz_151[1] = _zz_150; - _zz_151[0] = _zz_150; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_152 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_153 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_154 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_155 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_156 = _zz_339[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_241)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4288,8 +4588,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4299,135 +4599,144 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_257)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_258)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_259)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_258)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_259)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4440,39 +4749,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_257)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_257)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_275) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_4 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_4) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_260) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4485,8 +4804,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_260) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4505,58 +4824,69 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_341) + $signed(_zz_342)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_236)begin - if(_zz_261)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_262)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_346); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_157 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_157[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_347); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_348 : _zz_349); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_350[31:0]; - assign _zz_158 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_159 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_160 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_161[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_161[31 : 0] = execute_RS1; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; end - assign _zz_163 = (_zz_162 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_163 != 32'h0); - always @ (*) begin + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_263) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end end @@ -4566,9 +4896,9 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_164))begin + if(when_DebugPlugin_l244) begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4577,12 +4907,13 @@ module VexRiscv ( end end - always @ (*) begin + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_263) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin IBusCachedPlugin_injectionPort_valid = 1'b1; end end @@ -4593,35 +4924,114 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_26 = decode_SRC1_CTRL; - assign _zz_24 = _zz_49; - assign _zz_37 = decode_to_execute_SRC1_CTRL; - assign _zz_23 = decode_ALU_CTRL; - assign _zz_21 = _zz_48; - assign _zz_38 = decode_to_execute_ALU_CTRL; - assign _zz_20 = decode_SRC2_CTRL; - assign _zz_18 = _zz_47; - assign _zz_36 = decode_to_execute_SRC2_CTRL; - assign _zz_17 = decode_ALU_BITWISE_CTRL; - assign _zz_15 = _zz_46; - assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_14 = decode_SHIFT_CTRL; - assign _zz_11 = execute_SHIFT_CTRL; - assign _zz_12 = _zz_45; - assign _zz_34 = decode_to_execute_SHIFT_CTRL; - assign _zz_33 = execute_to_memory_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_51 = _zz_44; - assign _zz_30 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_43; - assign _zz_28 = decode_to_execute_ENV_CTRL; - assign _zz_27 = execute_to_memory_ENV_CTRL; - assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_15 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_18 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_28 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_29 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_39 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_64 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_65 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_66 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4642,9 +5052,15 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_166) + case(switch_Fetcher_l362) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4653,242 +5069,272 @@ module VexRiscv ( endcase end - always @ (*) begin - _zz_167 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_167[12 : 0] = 13'h1000; - _zz_167[25 : 20] = 6'h20; + assign when_Fetcher_l360 = (switch_Fetcher_l362 != 3'b000); + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_Fetcher_l398 = (switch_Fetcher_l362 != 3'b000); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_168 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_168[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_169 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_169[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_170 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_170[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_171 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_171[31 : 30] = CsrPlugin_misa_base; - _zz_171[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_172 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_172[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_172[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_172[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_173 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_173[11 : 11] = CsrPlugin_mip_MEIP; - _zz_173[7 : 7] = CsrPlugin_mip_MTIP; - _zz_173[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_174 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_174[11 : 11] = CsrPlugin_mie_MEIE; - _zz_174[7 : 7] = CsrPlugin_mie_MTIE; - _zz_174[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_175 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_175[31 : 2] = CsrPlugin_mtvec_base; - _zz_175[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_176 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_176[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_177 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_177[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_178 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_178[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_178[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_179 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_179[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_180[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_181[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_182[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_183[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_184[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_185[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_186 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_186[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_187 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_187[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_188 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_188[31 : 0] = _zz_162; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_189 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_189[31 : 0] = _zz_163; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = (((((_zz_167 | _zz_168) | (_zz_169 | _zz_170)) | ((_zz_567 | _zz_171) | (_zz_172 | _zz_173))) | (((_zz_174 | _zz_175) | (_zz_176 | _zz_177)) | ((_zz_178 | _zz_179) | (_zz_180 | _zz_181)))) | (((_zz_182 | _zz_183) | (_zz_184 | _zz_185)) | ((_zz_186 | _zz_187) | (_zz_188 | _zz_189)))); - assign iBusWishbone_ADR = {_zz_367,_zz_190}; - assign iBusWishbone_CTI = ((_zz_190 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_264)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_264)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_191; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_197 = (dBus_cmd_payload_length != 3'b000); - assign _zz_193 = dBus_cmd_valid; - assign _zz_195 = dBus_cmd_payload_wr; - assign _zz_196 = (_zz_192 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_194 && (_zz_195 || _zz_196)); - assign dBusWishbone_ADR = ((_zz_197 ? {{dBus_cmd_payload_address[31 : 5],_zz_192},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_197 ? (_zz_196 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_195 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_195; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_194 = (_zz_193 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_193; - assign dBusWishbone_STB = _zz_193; - assign dBus_rsp_valid = _zz_198; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; IBusCachedPlugin_decodePc_pcReg <= externalResetVector; - _zz_64 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; IBusCachedPlugin_decompressor_bufferValid <= 1'b0; IBusCachedPlugin_decompressor_throw2BytesReg <= 1'b0; - _zz_92 <= 1'b0; + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_103; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_104; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_122 <= 1'b1; - _zz_134 <= 1'b0; + _zz_2 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4909,163 +5355,163 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_162 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_166 <= 3'b000; - _zz_190 <= 3'b000; - _zz_191 <= 1'b0; - _zz_192 <= 3'b000; - _zz_198 <= 1'b0; + switch_Fetcher_l362 <= 3'b000; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if((decode_arbitration_isFiring && (! IBusCachedPlugin_decodePc_injectedDecode)))begin + if(when_Fetcher_l180) begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_decodePc_pcPlus; end - if(_zz_249)begin + if(when_Fetcher_l192) begin IBusCachedPlugin_decodePc_pcReg <= IBusCachedPlugin_jump_pcLoad_payload; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_64 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_62)begin - _zz_64 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if((IBusCachedPlugin_decompressor_output_valid && IBusCachedPlugin_decompressor_output_ready))begin + if(IBusCachedPlugin_decompressor_output_fire) begin IBusCachedPlugin_decompressor_throw2BytesReg <= ((((! IBusCachedPlugin_decompressor_unaligned) && IBusCachedPlugin_decompressor_isInputLowRvc) && IBusCachedPlugin_decompressor_isInputHighRvc) || (IBusCachedPlugin_decompressor_bufferValid && IBusCachedPlugin_decompressor_isInputHighRvc)); end - if((IBusCachedPlugin_decompressor_output_ready && IBusCachedPlugin_decompressor_input_valid))begin + if(when_Fetcher_l283) begin IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end - if(_zz_265)begin - if(IBusCachedPlugin_decompressor_bufferFill)begin + if(when_Fetcher_l286) begin + if(IBusCachedPlugin_decompressor_bufferFill) begin IBusCachedPlugin_decompressor_bufferValid <= 1'b1; end end - if((IBusCachedPlugin_externalFlush || IBusCachedPlugin_decompressor_consumeCurrent))begin + if(when_Fetcher_l291) begin IBusCachedPlugin_decompressor_throw2BytesReg <= 1'b0; IBusCachedPlugin_decompressor_bufferValid <= 1'b0; end - if(decode_arbitration_removeIt)begin - _zz_92 <= 1'b0; + if(decode_arbitration_removeIt) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= 1'b0; end - if(IBusCachedPlugin_decompressor_output_ready)begin - _zz_92 <= (IBusCachedPlugin_decompressor_output_valid && (! IBusCachedPlugin_externalFlush)); + if(IBusCachedPlugin_decompressor_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_valid <= (IBusCachedPlugin_decompressor_output_valid && (! IBusCachedPlugin_externalFlush)); end - if((! 1'b0))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_decodePc_flushed)begin + if(IBusCachedPlugin_decodePc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_decodePc_flushed)begin + if(IBusCachedPlugin_decodePc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_decodePc_flushed)begin + if(IBusCachedPlugin_decodePc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_decodePc_flushed)begin + if(IBusCachedPlugin_decodePc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_266)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_122 <= 1'b0; - _zz_134 <= (_zz_41 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_2 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_267)begin - if(_zz_268)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_269)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_270)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_245)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5076,8 +5522,8 @@ module VexRiscv ( end endcase end - if(_zz_246)begin - case(_zz_248) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5087,166 +5533,172 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_154,{_zz_153,_zz_152}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_166) + case(switch_Fetcher_l362) 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_166 <= 3'b001; + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; end end 3'b001 : begin - _zz_166 <= 3'b010; + switch_Fetcher_l362 <= 3'b010; end 3'b010 : begin - _zz_166 <= 3'b011; + switch_Fetcher_l362 <= 3'b011; end 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_166 <= 3'b100; + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; end end 3'b100 : begin - _zz_166 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; end default : begin end endcase - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_360[0]; - CsrPlugin_mstatus_MIE <= _zz_361[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_363[0]; - CsrPlugin_mie_MTIE <= _zz_364[0]; - CsrPlugin_mie_MSIE <= _zz_365[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_264)begin - if(iBusWishbone_ACK)begin - _zz_190 <= (_zz_190 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_191 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_193 && _zz_194))begin - _zz_192 <= (_zz_192 + 3'b001); - if(_zz_196)begin - _zz_192 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_198 <= ((_zz_193 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(_zz_265)begin + always @(posedge clk) begin + if(IBusCachedPlugin_decompressor_input_valid) begin + IBusCachedPlugin_decompressor_bufferValidLatch <= IBusCachedPlugin_decompressor_bufferValid; + end + if(IBusCachedPlugin_decompressor_input_valid) begin + IBusCachedPlugin_decompressor_throw2BytesLatch <= IBusCachedPlugin_decompressor_throw2Bytes; + end + if(when_Fetcher_l286) begin IBusCachedPlugin_decompressor_bufferData <= IBusCachedPlugin_decompressor_input_payload_rsp_inst[31 : 16]; end - if(IBusCachedPlugin_decompressor_output_ready)begin - _zz_93 <= IBusCachedPlugin_decompressor_output_payload_pc; - _zz_94 <= IBusCachedPlugin_decompressor_output_payload_rsp_error; - _zz_95 <= IBusCachedPlugin_decompressor_output_payload_rsp_inst; - _zz_96 <= IBusCachedPlugin_decompressor_output_payload_isRvc; + if(IBusCachedPlugin_decompressor_output_ready) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_pc <= IBusCachedPlugin_decompressor_output_payload_pc; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_error <= IBusCachedPlugin_decompressor_output_payload_rsp_error; + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_decompressor_output_payload_rsp_inst; + _zz_IBusCachedPlugin_injector_decodeInput_payload_isRvc <= IBusCachedPlugin_decompressor_output_payload_isRvc; end - if(IBusCachedPlugin_injector_decodeInput_ready)begin + if(IBusCachedPlugin_injector_decodeInput_ready) begin IBusCachedPlugin_injector_formal_rawInDecode <= IBusCachedPlugin_decompressor_raw; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(_zz_266)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_135 <= _zz_40[11 : 7]; - _zz_136 <= _zz_50; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_241)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_156 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_156 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_267)begin - if(_zz_268)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_269)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_270)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_245)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5254,421 +5706,441 @@ module VexRiscv ( end endcase end - if((memory_DivPlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_DivPlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_236)begin - if(_zz_261)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_351[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; end end end - if(_zz_262)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_160 ? (~ _zz_161) : _zz_161) + _zz_357); - memory_DivPlugin_rs2 <= ((_zz_159 ? (~ execute_RS2) : execute_RS2) + _zz_359); - memory_DivPlugin_div_needRevert <= ((_zz_160 ^ (_zz_159 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_35; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_6) begin decode_to_execute_IS_RVC <= decode_IS_RVC; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_53; + if(when_Pipeline_l124_7) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_8) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_52; + if(when_Pipeline_l124_9) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_10) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_25; + if(when_Pipeline_l124_11) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_15) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_22; + if(when_Pipeline_l124_16) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_19; + if(when_Pipeline_l124_17) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin + decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; + end + if(when_Pipeline_l124_28) begin + execute_to_memory_MEMORY_LRSC <= execute_MEMORY_LRSC; + end + if(when_Pipeline_l124_29) begin + memory_to_writeBack_MEMORY_LRSC <= memory_MEMORY_LRSC; + end + if(when_Pipeline_l124_30) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_31) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + if(when_Pipeline_l124_32) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_33) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_10; + if(when_Pipeline_l124_34) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + if(when_Pipeline_l124_35) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_37) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_38) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_39) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_52) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_53) begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_54) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_55) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + if(when_Pipeline_l124_56) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + if(when_Pipeline_l124_57) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_62) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_63) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_64) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_65) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_66) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((_zz_166 != 3'b000))begin - _zz_95 <= IBusCachedPlugin_injectionPort_payload; + if(when_Fetcher_l398) begin + _zz_IBusCachedPlugin_injector_decodeInput_payload_rsp_inst <= IBusCachedPlugin_injectionPort_payload; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_362[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_366[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end - always @ (posedge clk) begin + always @(posedge clk) begin DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin + if(debug_bus_cmd_ready) begin DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_50; + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; end - _zz_164 <= debug_bus_cmd_payload_address[2]; - if(_zz_243)begin + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin + always @(posedge clk) begin if(debugReset) begin DebugPlugin_resetIt <= 1'b0; DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; - _zz_165 <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; + _zz_3 <= 1'b0; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + if(when_DebugPlugin_l225) begin DebugPlugin_godmode <= 1'b1; end - if(debug_bus_cmd_valid)begin - case(_zz_263) + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin + if(when_DebugPlugin_l260) begin DebugPlugin_resetIt <= 1'b1; end - if(debug_bus_cmd_payload_data[24])begin + if(when_DebugPlugin_l260_1) begin DebugPlugin_resetIt <= 1'b0; end - if(debug_bus_cmd_payload_data[17])begin + if(when_DebugPlugin_l261) begin DebugPlugin_haltIt <= 1'b1; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l261_1) begin DebugPlugin_haltIt <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l262) begin DebugPlugin_haltedByBreak <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l263) begin DebugPlugin_godmode <= 1'b0; end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end end end default : begin end endcase end - if(_zz_243)begin - if(_zz_244)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_247)begin - if(decode_arbitration_isValid)begin + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin DebugPlugin_haltIt <= 1'b1; end end - _zz_165 <= (DebugPlugin_stepIt && decode_arbitration_isFiring); + _zz_3 <= (DebugPlugin_stepIt && decode_arbitration_isFiring); end end @@ -5678,10 +6150,10 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_isLrsc, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, input io_cpu_memory_isValid, @@ -5702,6 +6174,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -5717,9 +6190,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -5727,7 +6201,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -5736,24 +6210,15 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -5778,40 +6243,50 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; + reg stageA_request_isLrsc; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; + reg stageB_request_isLrsc; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5821,34 +6296,56 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; + reg stageB_lrSc_reserved; + wire when_DataCache_l866; wire stageB_isAmo; wire stageB_isAmoCached; wire stageB_isExternalLsrc; wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l984; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1010; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -5860,59 +6357,54 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -5927,274 +6419,311 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1010) begin + dataWriteCmd_valid = 1'b0; + end + end + end + end + end + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(when_DataCache_l984) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin + io_cpu_writeBack_haltIt = 1'b0; + end + if(when_DataCache_l1010) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); + assign when_DataCache_l866 = ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -6202,89 +6731,79 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); + if(when_DataCache_l984) begin + io_mem_cmd_valid = 1'b0; + end end else begin - if(_zz_16)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end + if(when_DataCache_l1010) begin + io_mem_cmd_valid = 1'b0; + end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6292,12 +6811,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6308,20 +6827,43 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l984 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1010 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign io_cpu_writeBack_exclusiveOk = stageB_lrSc_reserved; + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6329,45 +6871,49 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; + stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; + stageB_request_isLrsc <= stageA_request_isLrsc; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6378,97 +6924,96 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; + stageB_lrSc_reserved <= 1'b0; loader_valid <= 1'b0; loader_counter_value <= 3'b000; loader_waysAllocator <= 1'b1; loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; + end + if(when_DataCache_l866) begin + stageB_lrSc_reserved <= (! stageB_request_wr); + end + if(when_DataCache_l1051) begin + stageB_lrSc_reserved <= stageB_lrSc_reserved; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6518,13 +7063,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [21:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [21:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6533,8 +7074,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -6548,16 +7094,17 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; @@ -6566,77 +7113,78 @@ module InstructionCache ( (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - assign _zz_11 = (! lineLoader_flushCounter[7]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -6652,16 +7200,17 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; @@ -6673,7 +7222,7 @@ module InstructionCache ( assign io_cpu_fetch_error = (fetchStage_hit_error || ((! io_cpu_fetch_mmuRsp_isPaging) && (io_cpu_fetch_mmuRsp_exception || (! io_cpu_fetch_mmuRsp_allowExecute)))); assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuRsp_refilling; assign io_cpu_fetch_mmuException = (((! io_cpu_fetch_mmuRsp_refilling) && io_cpu_fetch_mmuRsp_isPaging) && (io_cpu_fetch_mmuRsp_exception || (! io_cpu_fetch_mmuRsp_allowExecute))); - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -6681,45 +7230,45 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 8'h0; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v index 3ebd2f1..e7ea0a9 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v @@ -1,54 +1,54 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 - - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - -`define MmuPlugin_shared_State_defaultEncoding_type [2:0] -`define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000 -`define MmuPlugin_shared_State_defaultEncoding_L1_CMD 3'b001 -`define MmuPlugin_shared_State_defaultEncoding_L1_RSP 3'b010 -`define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011 -`define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 + +`define MmuPlugin_shared_State_binary_sequential_type [2:0] +`define MmuPlugin_shared_State_binary_sequential_IDLE 3'b000 +`define MmuPlugin_shared_State_binary_sequential_L1_CMD 3'b001 +`define MmuPlugin_shared_State_binary_sequential_L1_RSP 3'b010 +`define MmuPlugin_shared_State_binary_sequential_L0_CMD 3'b011 +`define MmuPlugin_shared_State_binary_sequential_L0_RSP 3'b100 module VexRiscv ( @@ -81,66 +81,42 @@ module VexRiscv ( input clk, input reset ); - wire _zz_205; - wire _zz_206; - wire _zz_207; - wire _zz_208; - wire _zz_209; - wire _zz_210; - wire _zz_211; - wire _zz_212; - reg _zz_213; - reg _zz_214; - reg [31:0] _zz_215; - reg _zz_216; - reg [31:0] _zz_217; - reg [1:0] _zz_218; - reg _zz_219; - reg _zz_220; - wire _zz_221; - wire [2:0] _zz_222; - reg _zz_223; - wire [31:0] _zz_224; - reg _zz_225; - reg _zz_226; - wire _zz_227; - wire [31:0] _zz_228; - wire _zz_229; - wire _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire [3:0] _zz_237; - wire _zz_238; - wire _zz_239; - reg [31:0] _zz_240; - reg [31:0] _zz_241; - reg [31:0] _zz_242; - reg _zz_243; - reg _zz_244; - reg _zz_245; - reg [9:0] _zz_246; - reg [9:0] _zz_247; - reg [9:0] _zz_248; - reg [9:0] _zz_249; - reg _zz_250; - reg _zz_251; - reg _zz_252; - reg _zz_253; - reg _zz_254; - reg _zz_255; - reg _zz_256; - reg [9:0] _zz_257; - reg [9:0] _zz_258; - reg [9:0] _zz_259; - reg [9:0] _zz_260; - reg _zz_261; - reg _zz_262; - reg _zz_263; - reg _zz_264; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + reg dataCache_1_io_cpu_execute_isValid; + reg [31:0] dataCache_1_io_cpu_execute_address; + reg dataCache_1_io_cpu_execute_args_wr; + reg [1:0] dataCache_1_io_cpu_execute_args_size; + reg dataCache_1_io_cpu_execute_args_isLrsc; + wire dataCache_1_io_cpu_execute_args_amoCtrl_swap; + wire [2:0] dataCache_1_io_cpu_execute_args_amoCtrl_alu; + reg dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -163,6 +139,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -171,445 +148,351 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_265; - wire _zz_266; - wire _zz_267; - wire _zz_268; - wire _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire [1:0] _zz_279; - wire _zz_280; - wire _zz_281; - wire _zz_282; - wire _zz_283; - wire _zz_284; - wire _zz_285; - wire _zz_286; - wire _zz_287; - wire _zz_288; - wire _zz_289; - wire _zz_290; - wire _zz_291; - wire _zz_292; - wire _zz_293; - wire _zz_294; - wire [1:0] _zz_295; - wire _zz_296; - wire _zz_297; - wire _zz_298; - wire _zz_299; - wire _zz_300; - wire _zz_301; - wire _zz_302; - wire _zz_303; - wire _zz_304; - wire _zz_305; - wire _zz_306; - wire _zz_307; - wire _zz_308; - wire _zz_309; - wire _zz_310; - wire _zz_311; - wire _zz_312; - wire _zz_313; - wire _zz_314; - wire _zz_315; - wire _zz_316; - wire _zz_317; - wire _zz_318; - wire _zz_319; - wire [1:0] _zz_320; - wire _zz_321; - wire [1:0] _zz_322; - wire [51:0] _zz_323; - wire [51:0] _zz_324; - wire [51:0] _zz_325; - wire [32:0] _zz_326; - wire [51:0] _zz_327; - wire [49:0] _zz_328; - wire [51:0] _zz_329; - wire [49:0] _zz_330; - wire [51:0] _zz_331; - wire [32:0] _zz_332; - wire [31:0] _zz_333; - wire [32:0] _zz_334; - wire [0:0] _zz_335; - wire [0:0] _zz_336; - wire [0:0] _zz_337; - wire [0:0] _zz_338; - wire [0:0] _zz_339; - wire [0:0] _zz_340; - wire [0:0] _zz_341; - wire [0:0] _zz_342; - wire [0:0] _zz_343; - wire [0:0] _zz_344; - wire [0:0] _zz_345; - wire [0:0] _zz_346; - wire [0:0] _zz_347; - wire [0:0] _zz_348; - wire [0:0] _zz_349; - wire [0:0] _zz_350; - wire [0:0] _zz_351; - wire [0:0] _zz_352; - wire [0:0] _zz_353; - wire [0:0] _zz_354; - wire [4:0] _zz_355; - wire [2:0] _zz_356; - wire [31:0] _zz_357; - wire [11:0] _zz_358; - wire [31:0] _zz_359; - wire [19:0] _zz_360; - wire [11:0] _zz_361; - wire [31:0] _zz_362; - wire [31:0] _zz_363; - wire [19:0] _zz_364; - wire [11:0] _zz_365; - wire [2:0] _zz_366; - wire [2:0] _zz_367; - wire [0:0] _zz_368; - wire [1:0] _zz_369; - wire [0:0] _zz_370; - wire [1:0] _zz_371; - wire [0:0] _zz_372; - wire [0:0] _zz_373; - wire [0:0] _zz_374; - wire [0:0] _zz_375; - wire [0:0] _zz_376; - wire [0:0] _zz_377; - wire [0:0] _zz_378; - wire [0:0] _zz_379; - wire [1:0] _zz_380; - wire [0:0] _zz_381; - wire [2:0] _zz_382; - wire [4:0] _zz_383; - wire [11:0] _zz_384; - wire [11:0] _zz_385; - wire [31:0] _zz_386; - wire [31:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire [31:0] _zz_391; - wire [31:0] _zz_392; - wire [11:0] _zz_393; - wire [19:0] _zz_394; - wire [11:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire [11:0] _zz_399; - wire [19:0] _zz_400; - wire [11:0] _zz_401; - wire [2:0] _zz_402; - wire [1:0] _zz_403; - wire [1:0] _zz_404; - wire [65:0] _zz_405; - wire [65:0] _zz_406; - wire [31:0] _zz_407; - wire [31:0] _zz_408; - wire [0:0] _zz_409; - wire [5:0] _zz_410; - wire [32:0] _zz_411; - wire [31:0] _zz_412; - wire [31:0] _zz_413; - wire [32:0] _zz_414; - wire [32:0] _zz_415; - wire [32:0] _zz_416; - wire [32:0] _zz_417; - wire [0:0] _zz_418; - wire [32:0] _zz_419; - wire [0:0] _zz_420; - wire [32:0] _zz_421; - wire [0:0] _zz_422; - wire [31:0] _zz_423; - wire [0:0] _zz_424; - wire [0:0] _zz_425; - wire [0:0] _zz_426; - wire [0:0] _zz_427; - wire [0:0] _zz_428; - wire [0:0] _zz_429; - wire [0:0] _zz_430; - wire [0:0] _zz_431; - wire [0:0] _zz_432; - wire [0:0] _zz_433; - wire [0:0] _zz_434; - wire [0:0] _zz_435; - wire [0:0] _zz_436; - wire [0:0] _zz_437; - wire [0:0] _zz_438; - wire [0:0] _zz_439; - wire [0:0] _zz_440; - wire [0:0] _zz_441; - wire [0:0] _zz_442; - wire [0:0] _zz_443; - wire [0:0] _zz_444; - wire [0:0] _zz_445; - wire [0:0] _zz_446; - wire [0:0] _zz_447; - wire [0:0] _zz_448; - wire [0:0] _zz_449; - wire [0:0] _zz_450; - wire [0:0] _zz_451; - wire [0:0] _zz_452; - wire [0:0] _zz_453; - wire [0:0] _zz_454; - wire [0:0] _zz_455; - wire [0:0] _zz_456; - wire [0:0] _zz_457; - wire [0:0] _zz_458; - wire [0:0] _zz_459; - wire [0:0] _zz_460; - wire [0:0] _zz_461; - wire [0:0] _zz_462; - wire [0:0] _zz_463; - wire [0:0] _zz_464; - wire [0:0] _zz_465; - wire [0:0] _zz_466; - wire [0:0] _zz_467; - wire [0:0] _zz_468; - wire [26:0] _zz_469; - wire _zz_470; - wire _zz_471; - wire [2:0] _zz_472; - wire [31:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire _zz_476; - wire [0:0] _zz_477; - wire [17:0] _zz_478; - wire [31:0] _zz_479; - wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire _zz_482; - wire [0:0] _zz_483; - wire [11:0] _zz_484; - wire [31:0] _zz_485; - wire [31:0] _zz_486; - wire [31:0] _zz_487; - wire _zz_488; - wire [0:0] _zz_489; - wire [5:0] _zz_490; - wire [31:0] _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire _zz_494; - wire _zz_495; - wire _zz_496; - wire _zz_497; - wire _zz_498; - wire [31:0] _zz_499; - wire [31:0] _zz_500; - wire _zz_501; - wire [0:0] _zz_502; - wire [0:0] _zz_503; - wire _zz_504; - wire [0:0] _zz_505; - wire [27:0] _zz_506; - wire [31:0] _zz_507; - wire _zz_508; - wire _zz_509; - wire [0:0] _zz_510; - wire [0:0] _zz_511; - wire [0:0] _zz_512; - wire [0:0] _zz_513; - wire _zz_514; - wire [0:0] _zz_515; - wire [23:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire _zz_519; - wire _zz_520; - wire [0:0] _zz_521; - wire [1:0] _zz_522; - wire [0:0] _zz_523; - wire [0:0] _zz_524; - wire _zz_525; - wire [0:0] _zz_526; - wire [20:0] _zz_527; - wire [31:0] _zz_528; - wire [31:0] _zz_529; - wire [31:0] _zz_530; - wire [31:0] _zz_531; - wire [31:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire [31:0] _zz_535; - wire [0:0] _zz_536; - wire [0:0] _zz_537; - wire [0:0] _zz_538; - wire [0:0] _zz_539; - wire _zz_540; - wire [0:0] _zz_541; - wire [17:0] _zz_542; - wire [31:0] _zz_543; - wire [31:0] _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire _zz_548; - wire [3:0] _zz_549; - wire [3:0] _zz_550; - wire _zz_551; - wire [0:0] _zz_552; - wire [14:0] _zz_553; - wire [31:0] _zz_554; - wire [31:0] _zz_555; - wire _zz_556; - wire [0:0] _zz_557; - wire [0:0] _zz_558; - wire [31:0] _zz_559; - wire [31:0] _zz_560; - wire _zz_561; - wire [5:0] _zz_562; - wire [5:0] _zz_563; - wire _zz_564; - wire [0:0] _zz_565; - wire [11:0] _zz_566; - wire [31:0] _zz_567; - wire [31:0] _zz_568; - wire [31:0] _zz_569; - wire [31:0] _zz_570; - wire _zz_571; - wire [0:0] _zz_572; - wire [2:0] _zz_573; - wire _zz_574; - wire [0:0] _zz_575; - wire [0:0] _zz_576; - wire [0:0] _zz_577; - wire [3:0] _zz_578; - wire [4:0] _zz_579; - wire [4:0] _zz_580; - wire _zz_581; - wire [0:0] _zz_582; - wire [8:0] _zz_583; - wire [31:0] _zz_584; - wire [31:0] _zz_585; - wire [31:0] _zz_586; - wire _zz_587; - wire [0:0] _zz_588; - wire [0:0] _zz_589; - wire [31:0] _zz_590; - wire [31:0] _zz_591; - wire [31:0] _zz_592; - wire [31:0] _zz_593; - wire [31:0] _zz_594; - wire [31:0] _zz_595; - wire [31:0] _zz_596; - wire _zz_597; - wire [0:0] _zz_598; - wire [1:0] _zz_599; - wire [0:0] _zz_600; - wire [2:0] _zz_601; - wire [0:0] _zz_602; - wire [5:0] _zz_603; - wire [1:0] _zz_604; - wire [1:0] _zz_605; - wire _zz_606; - wire [0:0] _zz_607; - wire [6:0] _zz_608; - wire [31:0] _zz_609; - wire [31:0] _zz_610; - wire [31:0] _zz_611; - wire [31:0] _zz_612; - wire [31:0] _zz_613; - wire [31:0] _zz_614; - wire [31:0] _zz_615; - wire [31:0] _zz_616; - wire _zz_617; - wire [31:0] _zz_618; - wire [31:0] _zz_619; - wire _zz_620; - wire [0:0] _zz_621; - wire [0:0] _zz_622; - wire _zz_623; - wire [0:0] _zz_624; - wire [3:0] _zz_625; - wire _zz_626; - wire [0:0] _zz_627; - wire [0:0] _zz_628; - wire [0:0] _zz_629; - wire [0:0] _zz_630; - wire _zz_631; - wire [0:0] _zz_632; - wire [4:0] _zz_633; - wire [31:0] _zz_634; - wire [31:0] _zz_635; - wire [31:0] _zz_636; - wire [31:0] _zz_637; - wire [31:0] _zz_638; - wire [31:0] _zz_639; - wire [31:0] _zz_640; - wire [31:0] _zz_641; - wire [31:0] _zz_642; - wire _zz_643; - wire [0:0] _zz_644; - wire [1:0] _zz_645; - wire [31:0] _zz_646; - wire [31:0] _zz_647; - wire [31:0] _zz_648; - wire [31:0] _zz_649; - wire [31:0] _zz_650; - wire _zz_651; - wire [4:0] _zz_652; - wire [4:0] _zz_653; - wire _zz_654; - wire [0:0] _zz_655; - wire [2:0] _zz_656; - wire [31:0] _zz_657; - wire [31:0] _zz_658; - wire [31:0] _zz_659; - wire _zz_660; - wire [31:0] _zz_661; - wire _zz_662; - wire [0:0] _zz_663; - wire [2:0] _zz_664; - wire [0:0] _zz_665; - wire [0:0] _zz_666; - wire [2:0] _zz_667; - wire [2:0] _zz_668; - wire _zz_669; - wire [0:0] _zz_670; - wire [0:0] _zz_671; - wire [31:0] _zz_672; - wire [31:0] _zz_673; - wire [31:0] _zz_674; - wire [31:0] _zz_675; - wire _zz_676; - wire [0:0] _zz_677; - wire [0:0] _zz_678; - wire [31:0] _zz_679; - wire [31:0] _zz_680; - wire _zz_681; - wire [0:0] _zz_682; - wire [0:0] _zz_683; - wire [0:0] _zz_684; - wire [1:0] _zz_685; - wire [1:0] _zz_686; - wire [1:0] _zz_687; - wire [0:0] _zz_688; - wire [0:0] _zz_689; - wire [31:0] _zz_690; - wire [31:0] _zz_691; - wire [31:0] _zz_692; - wire [31:0] _zz_693; - wire [31:0] _zz_694; - wire [31:0] _zz_695; - wire [31:0] _zz_696; - wire [31:0] _zz_697; - wire _zz_698; - wire _zz_699; - wire _zz_700; - wire [31:0] _zz_701; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [17:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [11:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [5:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_18; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_19; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_20; + wire _zz_decode_LEGAL_INSTRUCTION_21; + wire _zz_decode_LEGAL_INSTRUCTION_22; + wire [4:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_7; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspRf; + wire [9:0] _zz_MmuPlugin_ports_0_cacheHitsCalc; + wire [9:0] _zz_MmuPlugin_ports_0_cacheHitsCalc_1; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_2; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_3; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_4; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_5; + reg _zz_MmuPlugin_ports_0_cacheLine_valid_4; + reg _zz_MmuPlugin_ports_0_cacheLine_exception; + reg _zz_MmuPlugin_ports_0_cacheLine_superPage; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1; + reg _zz_MmuPlugin_ports_0_cacheLine_allowRead; + reg _zz_MmuPlugin_ports_0_cacheLine_allowWrite; + reg _zz_MmuPlugin_ports_0_cacheLine_allowExecute; + reg _zz_MmuPlugin_ports_0_cacheLine_allowUser; + wire [1:0] _zz_MmuPlugin_ports_0_entryToReplace_valueNext; + wire [0:0] _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1; + wire [9:0] _zz_MmuPlugin_ports_1_cacheHitsCalc; + wire [9:0] _zz_MmuPlugin_ports_1_cacheHitsCalc_1; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_2; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_3; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_4; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_5; + reg _zz_MmuPlugin_ports_1_cacheLine_valid_4; + reg _zz_MmuPlugin_ports_1_cacheLine_exception; + reg _zz_MmuPlugin_ports_1_cacheLine_superPage; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1; + reg _zz_MmuPlugin_ports_1_cacheLine_allowRead; + reg _zz_MmuPlugin_ports_1_cacheLine_allowWrite; + reg _zz_MmuPlugin_ports_1_cacheLine_allowExecute; + reg _zz_MmuPlugin_ports_1_cacheLine_allowUser; + wire [1:0] _zz_MmuPlugin_ports_1_entryToReplace_valueNext; + wire [0:0] _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1; + wire [1:0] _zz__zz_MmuPlugin_shared_refills_2; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_1; + wire _zz__zz_decode_IS_RS2_SIGNED_2; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_3; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_4; + wire _zz__zz_decode_IS_RS2_SIGNED_5; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_6; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_7; + wire _zz__zz_decode_IS_RS2_SIGNED_8; + wire _zz__zz_decode_IS_RS2_SIGNED_9; + wire [28:0] _zz__zz_decode_IS_RS2_SIGNED_10; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_11; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_12; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_13; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_14; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_15; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_16; + wire _zz__zz_decode_IS_RS2_SIGNED_17; + wire _zz__zz_decode_IS_RS2_SIGNED_18; + wire _zz__zz_decode_IS_RS2_SIGNED_19; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_20; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_21; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_22; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_23; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_24; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_25; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_26; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_27; + wire [24:0] _zz__zz_decode_IS_RS2_SIGNED_28; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_29; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_30; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_31; + wire _zz__zz_decode_IS_RS2_SIGNED_32; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_33; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_34; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_35; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_36; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_37; + wire [21:0] _zz__zz_decode_IS_RS2_SIGNED_38; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_39; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_40; + wire _zz__zz_decode_IS_RS2_SIGNED_41; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_42; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_43; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_44; + wire [18:0] _zz__zz_decode_IS_RS2_SIGNED_45; + wire _zz__zz_decode_IS_RS2_SIGNED_46; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_47; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_48; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_49; + wire _zz__zz_decode_IS_RS2_SIGNED_50; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_51; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_52; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_53; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_54; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_55; + wire _zz__zz_decode_IS_RS2_SIGNED_56; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_57; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_58; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_59; + wire _zz__zz_decode_IS_RS2_SIGNED_60; + wire [14:0] _zz__zz_decode_IS_RS2_SIGNED_61; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_62; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_63; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_64; + wire _zz__zz_decode_IS_RS2_SIGNED_65; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_66; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_67; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_68; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_69; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_70; + wire _zz__zz_decode_IS_RS2_SIGNED_71; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_72; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_73; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_74; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_75; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_76; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_77; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_78; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_79; + wire _zz__zz_decode_IS_RS2_SIGNED_80; + wire _zz__zz_decode_IS_RS2_SIGNED_81; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_82; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_83; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_84; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_85; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_86; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_87; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_88; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_89; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_90; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_91; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_92; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_93; + wire _zz__zz_decode_IS_RS2_SIGNED_94; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_95; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_96; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_97; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_98; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_99; + wire _zz__zz_decode_IS_RS2_SIGNED_100; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_101; + wire [11:0] _zz__zz_decode_IS_RS2_SIGNED_102; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_103; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_104; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_105; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_106; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_107; + wire _zz__zz_decode_IS_RS2_SIGNED_108; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_109; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_110; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_111; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_112; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_113; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_114; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_115; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_116; + wire _zz__zz_decode_IS_RS2_SIGNED_117; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_118; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_119; + wire _zz__zz_decode_IS_RS2_SIGNED_120; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_121; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_122; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_123; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_124; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_125; + wire _zz__zz_decode_IS_RS2_SIGNED_126; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_127; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_128; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_129; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_130; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_131; + wire _zz__zz_decode_IS_RS2_SIGNED_132; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_133; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_134; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_135; + wire _zz__zz_decode_IS_RS2_SIGNED_136; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_137; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_138; + wire [8:0] _zz__zz_decode_IS_RS2_SIGNED_139; + wire _zz__zz_decode_IS_RS2_SIGNED_140; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_141; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_142; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_143; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_144; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_145; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_146; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_147; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_148; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_149; + wire [6:0] _zz__zz_decode_IS_RS2_SIGNED_150; + wire _zz__zz_decode_IS_RS2_SIGNED_151; + wire _zz__zz_decode_IS_RS2_SIGNED_152; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_153; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_154; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_155; + wire _zz__zz_decode_IS_RS2_SIGNED_156; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_157; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_158; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_159; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_160; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_161; + wire _zz__zz_decode_IS_RS2_SIGNED_162; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_163; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_164; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_165; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_166; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_167; + wire _zz__zz_decode_IS_RS2_SIGNED_168; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_169; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_170; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_171; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_172; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_173; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_174; + wire _zz__zz_decode_IS_RS2_SIGNED_175; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_176; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_177; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_178; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_179; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_180; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_181; + wire _zz__zz_decode_IS_RS2_SIGNED_182; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_183; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_184; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_185; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_186; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_187; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_188; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_189; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_190; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_191; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_192; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_193; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_194; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_195; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -621,8 +504,8 @@ module VexRiscv ( wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; wire execute_IS_DBUS_SHARING; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; @@ -633,49 +516,49 @@ module VexRiscv ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; - wire memory_IS_SFENCE_VMA; - wire execute_IS_SFENCE_VMA; wire decode_IS_SFENCE_VMA; + wire decode_IS_SFENCE_VMA2; wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_LRSC; wire memory_MEMORY_WR; wire decode_MEMORY_WR; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; @@ -695,23 +578,24 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; + wire execute_IS_SFENCE_VMA; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_31; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -721,54 +605,55 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_32; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_35; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_36; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; - wire [31:0] _zz_40; - wire _zz_41; - reg _zz_42; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_43; - wire `BranchCtrlEnum_defaultEncoding_type _zz_44; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; - wire `Src2CtrlEnum_defaultEncoding_type _zz_47; - wire `AluCtrlEnum_defaultEncoding_type _zz_48; - wire `Src1CtrlEnum_defaultEncoding_type _zz_49; - wire writeBack_IS_SFENCE_VMA; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + wire execute_IS_SFENCE_VMA2; wire writeBack_IS_DBUS_SHARING; wire memory_IS_DBUS_SHARING; - reg [31:0] _zz_50; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_LRSC; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_ENABLE; - wire execute_MEMORY_AMO; - wire execute_MEMORY_LRSC; + reg execute_MEMORY_AMO; + reg execute_MEMORY_LRSC; wire execute_MEMORY_FORCE_CONSTISTENCY; wire execute_MEMORY_MANAGMENT; (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; @@ -778,19 +663,19 @@ module VexRiscv ( wire [31:0] execute_INSTRUCTION; wire decode_MEMORY_AMO; wire decode_MEMORY_LRSC; - reg _zz_51; + reg _zz_decode_MEMORY_FORCE_CONSTISTENCY; wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_4; reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_52; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_53; - reg [31:0] _zz_54; - reg [31:0] _zz_55; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -885,7 +770,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -938,6 +823,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -958,29 +848,35 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_56; - wire [4:0] _zz_57; - wire _zz_58; - wire _zz_59; - wire _zz_60; - wire _zz_61; + wire [4:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_5; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -1003,16 +899,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_62; - wire _zz_63; - wire _zz_64; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_65; - wire _zz_66; - reg _zz_67; - wire _zz_68; - reg _zz_69; - reg [31:0] _zz_70; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -1020,22 +918,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_71; - reg [18:0] _zz_72; - wire _zz_73; - reg [10:0] _zz_74; - wire _zz_75; - reg [18:0] _zz_76; - reg _zz_77; - wire _zz_78; - reg [10:0] _zz_79; - wire _zz_80; - reg [18:0] _zz_81; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -1043,7 +948,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_82; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -1051,23 +956,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -1075,27 +985,47 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_83; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; + wire when_DBusCachedPlugin_l311; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_84; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_85; - reg [31:0] _zz_86; - wire _zz_87; - reg [31:0] _zz_88; + reg [31:0] writeBack_DBusCachedPlugin_rspRf; + wire when_DBusCachedPlugin_l474; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire when_DBusCachedPlugin_l484; reg DBusCachedPlugin_forceDatapath; + wire when_DBusCachedPlugin_l498; + wire when_DBusCachedPlugin_l499; + wire MmuPlugin_dBusAccess_cmd_fire; reg MmuPlugin_status_sum; reg MmuPlugin_status_mxr; reg MmuPlugin_status_mprv; @@ -1148,12 +1078,14 @@ module VexRiscv ( reg MmuPlugin_ports_0_cache_3_allowUser; wire MmuPlugin_ports_0_dirty; reg MmuPlugin_ports_0_requireMmuLockupCalc; - reg [3:0] MmuPlugin_ports_0_cacheHitsCalc; + wire when_MmuPlugin_l125; + wire when_MmuPlugin_l126; + wire [3:0] MmuPlugin_ports_0_cacheHitsCalc; wire MmuPlugin_ports_0_cacheHit; - wire _zz_89; - wire _zz_90; - wire _zz_91; - wire [1:0] _zz_92; + wire _zz_MmuPlugin_ports_0_cacheLine_valid; + wire _zz_MmuPlugin_ports_0_cacheLine_valid_1; + wire _zz_MmuPlugin_ports_0_cacheLine_valid_2; + wire [1:0] _zz_MmuPlugin_ports_0_cacheLine_valid_3; wire MmuPlugin_ports_0_cacheLine_valid; wire MmuPlugin_ports_0_cacheLine_exception; wire MmuPlugin_ports_0_cacheLine_superPage; @@ -1217,12 +1149,15 @@ module VexRiscv ( reg MmuPlugin_ports_1_cache_3_allowUser; wire MmuPlugin_ports_1_dirty; reg MmuPlugin_ports_1_requireMmuLockupCalc; - reg [3:0] MmuPlugin_ports_1_cacheHitsCalc; + wire when_MmuPlugin_l125_1; + wire when_MmuPlugin_l126_1; + wire when_MmuPlugin_l128; + wire [3:0] MmuPlugin_ports_1_cacheHitsCalc; wire MmuPlugin_ports_1_cacheHit; - wire _zz_93; - wire _zz_94; - wire _zz_95; - wire [1:0] _zz_96; + wire _zz_MmuPlugin_ports_1_cacheLine_valid; + wire _zz_MmuPlugin_ports_1_cacheLine_valid_1; + wire _zz_MmuPlugin_ports_1_cacheLine_valid_2; + wire [1:0] _zz_MmuPlugin_ports_1_cacheLine_valid_3; wire MmuPlugin_ports_1_cacheLine_valid; wire MmuPlugin_ports_1_cacheLine_exception; wire MmuPlugin_ports_1_cacheLine_superPage; @@ -1240,7 +1175,7 @@ module VexRiscv ( reg [1:0] MmuPlugin_ports_1_entryToReplace_value; wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; wire MmuPlugin_ports_1_entryToReplace_willOverflow; - reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1; + reg `MmuPlugin_shared_State_binary_sequential_type MmuPlugin_shared_state_1; reg [9:0] MmuPlugin_shared_vpn_0; reg [9:0] MmuPlugin_shared_vpn_1; reg [1:0] MmuPlugin_shared_portSortedOh; @@ -1261,6 +1196,7 @@ module VexRiscv ( wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; wire MmuPlugin_shared_dBusRsp_exception; wire MmuPlugin_shared_dBusRsp_leaf; + wire when_MmuPlugin_l205; reg MmuPlugin_shared_pteBuffer_V; reg MmuPlugin_shared_pteBuffer_R; reg MmuPlugin_shared_pteBuffer_W; @@ -1272,27 +1208,42 @@ module VexRiscv ( reg [1:0] MmuPlugin_shared_pteBuffer_RSW; reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; - reg [1:0] _zz_97; - wire [1:0] _zz_98; - reg [1:0] _zz_99; + wire [1:0] _zz_MmuPlugin_shared_refills; + reg [1:0] _zz_MmuPlugin_shared_refills_1; wire [1:0] MmuPlugin_shared_refills; - wire [1:0] _zz_100; - reg [1:0] _zz_101; - wire [31:0] _zz_102; - wire [34:0] _zz_103; - wire _zz_104; - wire _zz_105; - wire _zz_106; - wire _zz_107; - wire _zz_108; - wire _zz_109; - wire `Src1CtrlEnum_defaultEncoding_type _zz_110; - wire `AluCtrlEnum_defaultEncoding_type _zz_111; - wire `Src2CtrlEnum_defaultEncoding_type _zz_112; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_113; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_114; - wire `BranchCtrlEnum_defaultEncoding_type _zz_115; - wire `EnvCtrlEnum_defaultEncoding_type _zz_116; + wire [1:0] _zz_MmuPlugin_shared_refills_2; + reg [1:0] _zz_MmuPlugin_shared_refills_3; + wire when_MmuPlugin_l217; + wire [31:0] _zz_MmuPlugin_shared_vpn_0; + wire when_MmuPlugin_l243; + wire when_MmuPlugin_l272; + wire when_MmuPlugin_l274; + wire when_MmuPlugin_l280; + wire when_MmuPlugin_l280_1; + wire when_MmuPlugin_l280_2; + wire when_MmuPlugin_l280_3; + wire when_MmuPlugin_l274_1; + wire when_MmuPlugin_l280_4; + wire when_MmuPlugin_l280_5; + wire when_MmuPlugin_l280_6; + wire when_MmuPlugin_l280_7; + wire when_MmuPlugin_l304; + wire [35:0] _zz_decode_IS_RS2_SIGNED; + wire _zz_decode_IS_RS2_SIGNED_1; + wire _zz_decode_IS_RS2_SIGNED_2; + wire _zz_decode_IS_RS2_SIGNED_3; + wire _zz_decode_IS_RS2_SIGNED_4; + wire _zz_decode_IS_RS2_SIGNED_5; + wire _zz_decode_IS_RS2_SIGNED_6; + wire _zz_decode_IS_RS2_SIGNED_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -1300,54 +1251,72 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_117; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_118; - reg [31:0] _zz_119; - wire _zz_120; - reg [19:0] _zz_121; - wire _zz_122; - reg [19:0] _zz_123; - reg [31:0] _zz_124; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_125; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_126; - reg _zz_127; - reg _zz_128; - reg _zz_129; - reg [4:0] _zz_130; - reg [31:0] _zz_131; - wire _zz_132; - wire _zz_133; - wire _zz_134; - wire _zz_135; - wire _zz_136; - wire _zz_137; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_138; - reg _zz_139; - reg _zz_140; - wire _zz_141; - reg [19:0] _zz_142; - wire _zz_143; - reg [10:0] _zz_144; - wire _zz_145; - reg [18:0] _zz_146; - reg _zz_147; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_148; - reg [19:0] _zz_149; - wire _zz_150; - reg [10:0] _zz_151; - wire _zz_152; - reg [18:0] _zz_153; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] _zz_154; + reg [1:0] _zz_CsrPlugin_privilege; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1404,12 +1373,14 @@ module VexRiscv ( reg [21:0] CsrPlugin_satp_PPN; reg [8:0] CsrPlugin_satp_ASID; reg [0:0] CsrPlugin_satp_MODE; - wire _zz_155; - wire _zz_156; - wire _zz_157; - wire _zz_158; - wire _zz_159; - wire _zz_160; + reg CsrPlugin_rescheduleLogic_rescheduleNext; + wire when_CsrPlugin_l803; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; + wire _zz_when_CsrPlugin_l952_3; + wire _zz_when_CsrPlugin_l952_4; + wire _zz_when_CsrPlugin_l952_5; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1421,41 +1392,87 @@ module VexRiscv ( reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire when_CsrPlugin_l866; + wire when_CsrPlugin_l866_1; + wire when_CsrPlugin_l866_2; + wire when_CsrPlugin_l866_3; + wire when_CsrPlugin_l866_4; + wire when_CsrPlugin_l866_5; + wire when_CsrPlugin_l866_6; + wire when_CsrPlugin_l866_7; + wire when_CsrPlugin_l866_8; + wire when_CsrPlugin_l866_9; + wire when_CsrPlugin_l866_10; + wire when_CsrPlugin_l866_11; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_161; - wire _zz_162; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l946_1; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; + wire when_CsrPlugin_l952_3; + wire when_CsrPlugin_l952_4; + wire when_CsrPlugin_l952_5; + wire when_CsrPlugin_l952_6; + wire when_CsrPlugin_l952_7; + wire when_CsrPlugin_l952_8; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; reg [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1463,6 +1480,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1475,223 +1494,338 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_163; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_164; - wire _zz_165; - wire _zz_166; - reg [32:0] _zz_167; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_168; - wire [31:0] _zz_169; - reg [31:0] _zz_170; - wire [31:0] _zz_171; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_LRSC; + wire when_Pipeline_l124_27; + reg execute_to_memory_MEMORY_LRSC; + wire when_Pipeline_l124_28; + reg memory_to_writeBack_MEMORY_LRSC; + wire when_Pipeline_l124_29; reg decode_to_execute_MEMORY_AMO; + wire when_Pipeline_l124_30; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_31; + reg decode_to_execute_IS_SFENCE_VMA2; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_SFENCE_VMA; - reg execute_to_memory_IS_SFENCE_VMA; - reg memory_to_writeBack_IS_SFENCE_VMA; + wire when_Pipeline_l124_33; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_34; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_35; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_36; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_37; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_38; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_39; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_40; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_41; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_43; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_44; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_45; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_46; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_47; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_48; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_49; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_50; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_51; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_52; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_53; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_54; reg decode_to_execute_CSR_READ_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_55; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_56; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_57; reg execute_to_memory_IS_DBUS_SHARING; + wire when_Pipeline_l124_58; reg memory_to_writeBack_IS_DBUS_SHARING; + wire when_Pipeline_l124_59; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_60; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_61; reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_62; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_63; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_64; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_65; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_66; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_67; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_68; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_69; reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_256; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_384; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_770; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_771; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_324; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_260; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_261; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_321; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_320; + wire when_CsrPlugin_l1264_22; reg execute_CsrPlugin_csr_322; + wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_323; + wire when_CsrPlugin_l1264_24; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_25; reg execute_CsrPlugin_csr_4032; + wire when_CsrPlugin_l1264_26; reg execute_CsrPlugin_csr_2496; + wire when_CsrPlugin_l1264_27; reg execute_CsrPlugin_csr_3520; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [2:0] _zz_196; - reg _zz_197; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - reg _zz_204; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; - reg [39:0] _zz_17_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; - reg [23:0] _zz_20_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; - reg [63:0] _zz_23_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; - reg [95:0] _zz_26_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_30_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_33_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_34_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_36_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_37_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_38_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_39_string; - reg [39:0] _zz_43_string; - reg [31:0] _zz_44_string; - reg [71:0] _zz_45_string; - reg [39:0] _zz_46_string; - reg [23:0] _zz_47_string; - reg [63:0] _zz_48_string; - reg [95:0] _zz_49_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_52_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; reg [47:0] MmuPlugin_shared_state_1_string; - reg [95:0] _zz_110_string; - reg [63:0] _zz_111_string; - reg [23:0] _zz_112_string; - reg [39:0] _zz_113_string; - reg [71:0] _zz_114_string; - reg [31:0] _zz_115_string; - reg [39:0] _zz_116_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1706,1416 +1840,1324 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_265 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_266 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_267 = 1'b1; - assign _zz_268 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_270 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_271 = ((_zz_210 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_272 = ((_zz_210 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_273 = ((_zz_210 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_274 = ((_zz_210 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_275 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_276 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_277 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_278 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_279 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_280 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); - assign _zz_281 = (! dataCache_1_io_cpu_execute_refilling); - assign _zz_282 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_283 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); - assign _zz_284 = MmuPlugin_shared_portSortedOh[0]; - assign _zz_285 = MmuPlugin_shared_portSortedOh[1]; - assign _zz_286 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_287 = (1'b0 || (! 1'b1)); - assign _zz_288 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_289 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_290 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_291 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_292 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_293 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_294 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_295 = execute_INSTRUCTION[13 : 12]; - assign _zz_296 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_297 = (! memory_arbitration_isStuck); - assign _zz_298 = (iBus_cmd_valid || (_zz_196 != 3'b000)); - assign _zz_299 = (_zz_239 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_300 = (MmuPlugin_shared_refills != 2'b00); - assign _zz_301 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); - assign _zz_302 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); - assign _zz_303 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); - assign _zz_304 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); - assign _zz_305 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); - assign _zz_306 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); - assign _zz_307 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); - assign _zz_308 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); - assign _zz_309 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); - assign _zz_310 = ((_zz_155 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); - assign _zz_311 = ((_zz_156 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); - assign _zz_312 = ((_zz_157 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); - assign _zz_313 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_314 = ((_zz_155 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); - assign _zz_315 = ((_zz_156 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); - assign _zz_316 = ((_zz_157 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); - assign _zz_317 = ((_zz_158 && 1'b1) && (! 1'b0)); - assign _zz_318 = ((_zz_159 && 1'b1) && (! 1'b0)); - assign _zz_319 = ((_zz_160 && 1'b1) && (! 1'b0)); - assign _zz_320 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_321 = execute_INSTRUCTION[13]; - assign _zz_322 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_323 = ($signed(_zz_324) + $signed(_zz_329)); - assign _zz_324 = ($signed(_zz_325) + $signed(_zz_327)); - assign _zz_325 = 52'h0; - assign _zz_326 = {1'b0,memory_MUL_LL}; - assign _zz_327 = {{19{_zz_326[32]}}, _zz_326}; - assign _zz_328 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_329 = {{2{_zz_328[49]}}, _zz_328}; - assign _zz_330 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_331 = {{2{_zz_330[49]}}, _zz_330}; - assign _zz_332 = ($signed(_zz_334) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_333 = _zz_332[31 : 0]; - assign _zz_334 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_335 = _zz_103[34 : 34]; - assign _zz_336 = _zz_103[33 : 33]; - assign _zz_337 = _zz_103[32 : 32]; - assign _zz_338 = _zz_103[31 : 31]; - assign _zz_339 = _zz_103[28 : 28]; - assign _zz_340 = _zz_103[21 : 21]; - assign _zz_341 = _zz_103[20 : 20]; - assign _zz_342 = _zz_103[19 : 19]; - assign _zz_343 = _zz_103[13 : 13]; - assign _zz_344 = _zz_103[12 : 12]; - assign _zz_345 = _zz_103[11 : 11]; - assign _zz_346 = _zz_103[17 : 17]; - assign _zz_347 = _zz_103[5 : 5]; - assign _zz_348 = _zz_103[3 : 3]; - assign _zz_349 = _zz_103[18 : 18]; - assign _zz_350 = _zz_103[10 : 10]; - assign _zz_351 = _zz_103[16 : 16]; - assign _zz_352 = _zz_103[15 : 15]; - assign _zz_353 = _zz_103[4 : 4]; - assign _zz_354 = _zz_103[0 : 0]; - assign _zz_355 = (_zz_56 - 5'h01); - assign _zz_356 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_357 = {29'd0, _zz_356}; - assign _zz_358 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_359 = {{_zz_72,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_360 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_361 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_362 = {{_zz_74,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_363 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_364 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_365 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_366 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_367 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_368 = MmuPlugin_ports_0_entryToReplace_willIncrement; - assign _zz_369 = {1'd0, _zz_368}; - assign _zz_370 = MmuPlugin_ports_1_entryToReplace_willIncrement; - assign _zz_371 = {1'd0, _zz_370}; - assign _zz_372 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; - assign _zz_373 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; - assign _zz_374 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; - assign _zz_375 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; - assign _zz_376 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; - assign _zz_377 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; - assign _zz_378 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; - assign _zz_379 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; - assign _zz_380 = (_zz_99 - 2'b01); - assign _zz_381 = execute_SRC_LESS; - assign _zz_382 = 3'b100; - assign _zz_383 = execute_INSTRUCTION[19 : 15]; - assign _zz_384 = execute_INSTRUCTION[31 : 20]; - assign _zz_385 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_386 = ($signed(_zz_387) + $signed(_zz_390)); - assign _zz_387 = ($signed(_zz_388) + $signed(_zz_389)); - assign _zz_388 = execute_SRC1; - assign _zz_389 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_390 = (execute_SRC_USE_SUB_LESS ? _zz_391 : _zz_392); - assign _zz_391 = 32'h00000001; - assign _zz_392 = 32'h0; - assign _zz_393 = execute_INSTRUCTION[31 : 20]; - assign _zz_394 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_395 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_396 = {_zz_142,execute_INSTRUCTION[31 : 20]}; - assign _zz_397 = {{_zz_144,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_398 = {{_zz_146,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_399 = execute_INSTRUCTION[31 : 20]; - assign _zz_400 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_401 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_402 = 3'b100; - assign _zz_403 = (_zz_161 & (~ _zz_404)); - assign _zz_404 = (_zz_161 - 2'b01); - assign _zz_405 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_406 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_407 = writeBack_MUL_LOW[31 : 0]; - assign _zz_408 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_409 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_410 = {5'd0, _zz_409}; - assign _zz_411 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_412 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_413 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_414 = {_zz_163,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_415 = _zz_416; - assign _zz_416 = _zz_417; - assign _zz_417 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_164) : _zz_164)} + _zz_419); - assign _zz_418 = memory_DivPlugin_div_needRevert; - assign _zz_419 = {32'd0, _zz_418}; - assign _zz_420 = _zz_166; - assign _zz_421 = {32'd0, _zz_420}; - assign _zz_422 = _zz_165; - assign _zz_423 = {31'd0, _zz_422}; - assign _zz_424 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_425 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_426 = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_427 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_428 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_429 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_430 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_431 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_432 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_433 = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_434 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_435 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_436 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_437 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_438 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_439 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_440 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_441 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_442 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_443 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_444 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_445 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_446 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_447 = execute_CsrPlugin_writeData[0 : 0]; - assign _zz_448 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_449 = execute_CsrPlugin_writeData[2 : 2]; - assign _zz_450 = execute_CsrPlugin_writeData[4 : 4]; - assign _zz_451 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_452 = execute_CsrPlugin_writeData[6 : 6]; - assign _zz_453 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_454 = execute_CsrPlugin_writeData[8 : 8]; - assign _zz_455 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_456 = execute_CsrPlugin_writeData[12 : 12]; - assign _zz_457 = execute_CsrPlugin_writeData[13 : 13]; - assign _zz_458 = execute_CsrPlugin_writeData[15 : 15]; - assign _zz_459 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_460 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_461 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_462 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_463 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_464 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_465 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_466 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_467 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_468 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_469 = (iBus_cmd_payload_address >>> 5); - assign _zz_470 = 1'b1; - assign _zz_471 = 1'b1; - assign _zz_472 = {_zz_59,{_zz_61,_zz_60}}; - assign _zz_473 = 32'h0000107f; - assign _zz_474 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_475 = 32'h00002073; - assign _zz_476 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_477 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_478 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_479) == 32'h00000003),{(_zz_480 == _zz_481),{_zz_482,{_zz_483,_zz_484}}}}}}; - assign _zz_479 = 32'h0000505f; - assign _zz_480 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_481 = 32'h00000063; - assign _zz_482 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_483 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); - assign _zz_484 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_485) == 32'h0000500f),{(_zz_486 == _zz_487),{_zz_488,{_zz_489,_zz_490}}}}}}; - assign _zz_485 = 32'h01f0707f; - assign _zz_486 = (decode_INSTRUCTION & 32'hbc00707f); - assign _zz_487 = 32'h00005013; - assign _zz_488 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); - assign _zz_489 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_490 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_491) == 32'h12000073),{(_zz_492 == _zz_493),{_zz_494,_zz_495}}}}}; - assign _zz_491 = 32'hfe007fff; - assign _zz_492 = (decode_INSTRUCTION & 32'hdfffffff); - assign _zz_493 = 32'h10200073; - assign _zz_494 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_495 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); - assign _zz_496 = decode_INSTRUCTION[31]; - assign _zz_497 = decode_INSTRUCTION[31]; - assign _zz_498 = decode_INSTRUCTION[7]; - assign _zz_499 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_500 = 32'h02004020; - assign _zz_501 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_502 = ((decode_INSTRUCTION & 32'h02203050) == 32'h00000050); - assign _zz_503 = 1'b0; - assign _zz_504 = (((decode_INSTRUCTION & _zz_507) == 32'h00000050) != 1'b0); - assign _zz_505 = ({_zz_508,_zz_509} != 2'b00); - assign _zz_506 = {({_zz_510,_zz_511} != 2'b00),{(_zz_512 != _zz_513),{_zz_514,{_zz_515,_zz_516}}}}; - assign _zz_507 = 32'h02403050; - assign _zz_508 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_509 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_510 = _zz_105; - assign _zz_511 = ((decode_INSTRUCTION & _zz_517) == 32'h00000004); - assign _zz_512 = ((decode_INSTRUCTION & _zz_518) == 32'h00000040); - assign _zz_513 = 1'b0; - assign _zz_514 = ({_zz_519,_zz_520} != 2'b00); - assign _zz_515 = ({_zz_521,_zz_522} != 3'b000); - assign _zz_516 = {(_zz_523 != _zz_524),{_zz_525,{_zz_526,_zz_527}}}; - assign _zz_517 = 32'h0000001c; - assign _zz_518 = 32'h00000058; - assign _zz_519 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_520 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_521 = ((decode_INSTRUCTION & _zz_528) == 32'h40001010); - assign _zz_522 = {(_zz_529 == _zz_530),(_zz_531 == _zz_532)}; - assign _zz_523 = ((decode_INSTRUCTION & _zz_533) == 32'h00001000); - assign _zz_524 = 1'b0; - assign _zz_525 = ((_zz_534 == _zz_535) != 1'b0); - assign _zz_526 = ({_zz_536,_zz_537} != 2'b00); - assign _zz_527 = {(_zz_538 != _zz_539),{_zz_540,{_zz_541,_zz_542}}}; - assign _zz_528 = 32'h40003054; - assign _zz_529 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_530 = 32'h00001010; - assign _zz_531 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_532 = 32'h00001010; - assign _zz_533 = 32'h00001000; - assign _zz_534 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_535 = 32'h00002000; - assign _zz_536 = ((decode_INSTRUCTION & _zz_543) == 32'h00002000); - assign _zz_537 = ((decode_INSTRUCTION & _zz_544) == 32'h00001000); - assign _zz_538 = ((decode_INSTRUCTION & _zz_545) == 32'h02000050); - assign _zz_539 = 1'b0; - assign _zz_540 = ((_zz_546 == _zz_547) != 1'b0); - assign _zz_541 = (_zz_548 != 1'b0); - assign _zz_542 = {(_zz_549 != _zz_550),{_zz_551,{_zz_552,_zz_553}}}; - assign _zz_543 = 32'h00002010; - assign _zz_544 = 32'h00005000; - assign _zz_545 = 32'h02003050; - assign _zz_546 = (decode_INSTRUCTION & 32'h00004048); - assign _zz_547 = 32'h00004008; - assign _zz_548 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_549 = {(_zz_554 == _zz_555),{_zz_556,{_zz_557,_zz_558}}}; - assign _zz_550 = 4'b0000; - assign _zz_551 = ((_zz_559 == _zz_560) != 1'b0); - assign _zz_552 = (_zz_561 != 1'b0); - assign _zz_553 = {(_zz_562 != _zz_563),{_zz_564,{_zz_565,_zz_566}}}; - assign _zz_554 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_555 = 32'h00000020; - assign _zz_556 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_557 = ((decode_INSTRUCTION & _zz_567) == 32'h08000020); - assign _zz_558 = ((decode_INSTRUCTION & _zz_568) == 32'h00000020); - assign _zz_559 = (decode_INSTRUCTION & 32'h10000008); - assign _zz_560 = 32'h00000008; - assign _zz_561 = ((decode_INSTRUCTION & 32'h10000008) == 32'h10000008); - assign _zz_562 = {(_zz_569 == _zz_570),{_zz_571,{_zz_572,_zz_573}}}; - assign _zz_563 = 6'h0; - assign _zz_564 = ({_zz_574,{_zz_575,_zz_576}} != 3'b000); - assign _zz_565 = ({_zz_577,_zz_578} != 5'h0); - assign _zz_566 = {(_zz_579 != _zz_580),{_zz_581,{_zz_582,_zz_583}}}; - assign _zz_567 = 32'h08000070; - assign _zz_568 = 32'h10000070; - assign _zz_569 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_570 = 32'h00002040; - assign _zz_571 = ((decode_INSTRUCTION & _zz_584) == 32'h00001040); - assign _zz_572 = (_zz_585 == _zz_586); - assign _zz_573 = {_zz_587,{_zz_588,_zz_589}}; - assign _zz_574 = ((decode_INSTRUCTION & _zz_590) == 32'h08000020); - assign _zz_575 = (_zz_591 == _zz_592); - assign _zz_576 = (_zz_593 == _zz_594); - assign _zz_577 = (_zz_595 == _zz_596); - assign _zz_578 = {_zz_597,{_zz_598,_zz_599}}; - assign _zz_579 = {_zz_108,{_zz_600,_zz_601}}; - assign _zz_580 = 5'h0; - assign _zz_581 = ({_zz_602,_zz_603} != 7'h0); - assign _zz_582 = (_zz_604 != _zz_605); - assign _zz_583 = {_zz_606,{_zz_607,_zz_608}}; - assign _zz_584 = 32'h00001040; - assign _zz_585 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_586 = 32'h00000040; - assign _zz_587 = ((decode_INSTRUCTION & _zz_609) == 32'h00000040); - assign _zz_588 = (_zz_610 == _zz_611); - assign _zz_589 = (_zz_612 == _zz_613); - assign _zz_590 = 32'h08000020; - assign _zz_591 = (decode_INSTRUCTION & 32'h10000020); - assign _zz_592 = 32'h00000020; - assign _zz_593 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_594 = 32'h00000020; - assign _zz_595 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_596 = 32'h00000040; - assign _zz_597 = ((decode_INSTRUCTION & _zz_614) == 32'h00004020); - assign _zz_598 = (_zz_615 == _zz_616); - assign _zz_599 = {_zz_108,_zz_617}; - assign _zz_600 = (_zz_618 == _zz_619); - assign _zz_601 = {_zz_620,{_zz_621,_zz_622}}; - assign _zz_602 = _zz_105; - assign _zz_603 = {_zz_623,{_zz_624,_zz_625}}; - assign _zz_604 = {_zz_107,_zz_626}; - assign _zz_605 = 2'b00; - assign _zz_606 = ({_zz_627,_zz_628} != 2'b00); - assign _zz_607 = (_zz_629 != _zz_630); - assign _zz_608 = {_zz_631,{_zz_632,_zz_633}}; - assign _zz_609 = 32'h02400040; - assign _zz_610 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_611 = 32'h0; - assign _zz_612 = (decode_INSTRUCTION & 32'h18002008); - assign _zz_613 = 32'h10002008; - assign _zz_614 = 32'h00004020; - assign _zz_615 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_616 = 32'h00000010; - assign _zz_617 = ((decode_INSTRUCTION & _zz_634) == 32'h00000020); - assign _zz_618 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_619 = 32'h00002010; - assign _zz_620 = ((decode_INSTRUCTION & _zz_635) == 32'h00000010); - assign _zz_621 = (_zz_636 == _zz_637); - assign _zz_622 = (_zz_638 == _zz_639); - assign _zz_623 = ((decode_INSTRUCTION & _zz_640) == 32'h00001010); - assign _zz_624 = (_zz_641 == _zz_642); - assign _zz_625 = {_zz_643,{_zz_644,_zz_645}}; - assign _zz_626 = ((decode_INSTRUCTION & _zz_646) == 32'h00000020); - assign _zz_627 = _zz_107; - assign _zz_628 = (_zz_647 == _zz_648); - assign _zz_629 = (_zz_649 == _zz_650); - assign _zz_630 = 1'b0; - assign _zz_631 = (_zz_651 != 1'b0); - assign _zz_632 = (_zz_652 != _zz_653); - assign _zz_633 = {_zz_654,{_zz_655,_zz_656}}; - assign _zz_634 = 32'h02000028; - assign _zz_635 = 32'h00001030; - assign _zz_636 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_637 = 32'h00000020; - assign _zz_638 = (decode_INSTRUCTION & 32'h02002068); - assign _zz_639 = 32'h00002020; - assign _zz_640 = 32'h00001010; - assign _zz_641 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_642 = 32'h00002010; - assign _zz_643 = ((decode_INSTRUCTION & _zz_657) == 32'h00002008); - assign _zz_644 = (_zz_658 == _zz_659); - assign _zz_645 = {_zz_108,_zz_660}; - assign _zz_646 = 32'h00000070; - assign _zz_647 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_648 = 32'h0; - assign _zz_649 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_650 = 32'h00004010; - assign _zz_651 = ((decode_INSTRUCTION & _zz_661) == 32'h00002010); - assign _zz_652 = {_zz_662,{_zz_663,_zz_664}}; - assign _zz_653 = 5'h0; - assign _zz_654 = ({_zz_665,_zz_666} != 2'b00); - assign _zz_655 = (_zz_667 != _zz_668); - assign _zz_656 = {_zz_669,{_zz_670,_zz_671}}; - assign _zz_657 = 32'h00002008; - assign _zz_658 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_659 = 32'h00000010; - assign _zz_660 = ((decode_INSTRUCTION & _zz_672) == 32'h0); - assign _zz_661 = 32'h00006014; - assign _zz_662 = ((decode_INSTRUCTION & _zz_673) == 32'h0); - assign _zz_663 = (_zz_674 == _zz_675); - assign _zz_664 = {_zz_676,{_zz_677,_zz_678}}; - assign _zz_665 = _zz_106; - assign _zz_666 = (_zz_679 == _zz_680); - assign _zz_667 = {_zz_681,{_zz_682,_zz_683}}; - assign _zz_668 = 3'b000; - assign _zz_669 = ({_zz_684,_zz_685} != 3'b000); - assign _zz_670 = (_zz_686 != _zz_687); - assign _zz_671 = (_zz_688 != _zz_689); - assign _zz_672 = 32'h00000028; - assign _zz_673 = 32'h00000044; - assign _zz_674 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_675 = 32'h0; - assign _zz_676 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_677 = ((decode_INSTRUCTION & _zz_690) == 32'h00001000); - assign _zz_678 = _zz_106; - assign _zz_679 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_680 = 32'h0; - assign _zz_681 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_682 = ((decode_INSTRUCTION & _zz_691) == 32'h00002010); - assign _zz_683 = ((decode_INSTRUCTION & _zz_692) == 32'h40000030); - assign _zz_684 = _zz_105; - assign _zz_685 = {_zz_104,(_zz_693 == _zz_694)}; - assign _zz_686 = {_zz_104,(_zz_695 == _zz_696)}; - assign _zz_687 = 2'b00; - assign _zz_688 = ((decode_INSTRUCTION & _zz_697) == 32'h00001008); - assign _zz_689 = 1'b0; - assign _zz_690 = 32'h00005004; - assign _zz_691 = 32'h00002014; - assign _zz_692 = 32'h40000034; - assign _zz_693 = (decode_INSTRUCTION & 32'h00002014); - assign _zz_694 = 32'h00000004; - assign _zz_695 = (decode_INSTRUCTION & 32'h0000004c); - assign _zz_696 = 32'h00000004; - assign _zz_697 = 32'h00005048; - assign _zz_698 = execute_INSTRUCTION[31]; - assign _zz_699 = execute_INSTRUCTION[31]; - assign _zz_700 = execute_INSTRUCTION[7]; - assign _zz_701 = 32'h0; - always @ (posedge clk) begin - if(_zz_470) begin - _zz_240 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_471) begin - _zz_241 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_42) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 5'h01); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_writeBack_DBusCachedPlugin_rspRf = (! dataCache_1_io_cpu_writeBack_exclusiveOk); + assign _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_MmuPlugin_ports_0_entryToReplace_valueNext = {1'd0, _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1}; + assign _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_MmuPlugin_ports_1_entryToReplace_valueNext = {1'd0, _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1}; + assign _zz__zz_MmuPlugin_shared_refills_2 = (_zz_MmuPlugin_shared_refills_1 - 2'b01); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_7 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,{_zz_IBusCachedPlugin_jump_pcLoad_payload_5,_zz_IBusCachedPlugin_jump_pcLoad_payload_4}}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h0000500f),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'h01f0707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbc00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_18) == 32'h12000073),{(_zz_decode_LEGAL_INSTRUCTION_19 == _zz_decode_LEGAL_INSTRUCTION_20),{_zz_decode_LEGAL_INSTRUCTION_21,_zz_decode_LEGAL_INSTRUCTION_22}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_18 = 32'hfe007fff; + assign _zz_decode_LEGAL_INSTRUCTION_19 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_decode_LEGAL_INSTRUCTION_20 = 32'h10200073; + assign _zz_decode_LEGAL_INSTRUCTION_21 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_decode_LEGAL_INSTRUCTION_22 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_1 = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_2 = (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_3 = (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_4 = (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_5 = (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]; + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_1 = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]; + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_2 = (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_3 = (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_4 = (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_5 = (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz__zz_decode_IS_RS2_SIGNED = (decode_INSTRUCTION & 32'h02004064); + assign _zz__zz_decode_IS_RS2_SIGNED_1 = 32'h02004020; + assign _zz__zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz__zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h02203050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_4 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_5 = (((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_6) == 32'h00000050) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_7 = ({_zz__zz_decode_IS_RS2_SIGNED_8,_zz__zz_decode_IS_RS2_SIGNED_9} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_10 = {({_zz__zz_decode_IS_RS2_SIGNED_11,_zz__zz_decode_IS_RS2_SIGNED_12} != 2'b00),{(_zz__zz_decode_IS_RS2_SIGNED_14 != _zz__zz_decode_IS_RS2_SIGNED_16),{_zz__zz_decode_IS_RS2_SIGNED_17,{_zz__zz_decode_IS_RS2_SIGNED_20,_zz__zz_decode_IS_RS2_SIGNED_28}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_6 = 32'h02403050; + assign _zz__zz_decode_IS_RS2_SIGNED_8 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz__zz_decode_IS_RS2_SIGNED_9 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz__zz_decode_IS_RS2_SIGNED_11 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_12 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_13) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_14 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_15) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_16 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_17 = ({_zz__zz_decode_IS_RS2_SIGNED_18,_zz__zz_decode_IS_RS2_SIGNED_19} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_20 = ({_zz__zz_decode_IS_RS2_SIGNED_21,_zz__zz_decode_IS_RS2_SIGNED_23} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_28 = {(_zz__zz_decode_IS_RS2_SIGNED_29 != _zz__zz_decode_IS_RS2_SIGNED_31),{_zz__zz_decode_IS_RS2_SIGNED_32,{_zz__zz_decode_IS_RS2_SIGNED_35,_zz__zz_decode_IS_RS2_SIGNED_38}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_13 = 32'h0000001c; + assign _zz__zz_decode_IS_RS2_SIGNED_15 = 32'h00000058; + assign _zz__zz_decode_IS_RS2_SIGNED_18 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz__zz_decode_IS_RS2_SIGNED_19 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz__zz_decode_IS_RS2_SIGNED_21 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_22) == 32'h40001010); + assign _zz__zz_decode_IS_RS2_SIGNED_23 = {(_zz__zz_decode_IS_RS2_SIGNED_24 == _zz__zz_decode_IS_RS2_SIGNED_25),(_zz__zz_decode_IS_RS2_SIGNED_26 == _zz__zz_decode_IS_RS2_SIGNED_27)}; + assign _zz__zz_decode_IS_RS2_SIGNED_29 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_30) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_31 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_32 = ((_zz__zz_decode_IS_RS2_SIGNED_33 == _zz__zz_decode_IS_RS2_SIGNED_34) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_35 = ({_zz__zz_decode_IS_RS2_SIGNED_36,_zz__zz_decode_IS_RS2_SIGNED_37} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_38 = {(_zz__zz_decode_IS_RS2_SIGNED_39 != _zz__zz_decode_IS_RS2_SIGNED_40),{_zz__zz_decode_IS_RS2_SIGNED_41,{_zz__zz_decode_IS_RS2_SIGNED_42,_zz__zz_decode_IS_RS2_SIGNED_45}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_22 = 32'h40003054; + assign _zz__zz_decode_IS_RS2_SIGNED_24 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_RS2_SIGNED_25 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_26 = (decode_INSTRUCTION & 32'h02007054); + assign _zz__zz_decode_IS_RS2_SIGNED_27 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_30 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_33 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_IS_RS2_SIGNED_34 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_36 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_37 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_39 = _zz_decode_IS_RS2_SIGNED_6; + assign _zz__zz_decode_IS_RS2_SIGNED_40 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_41 = (_zz_decode_IS_RS2_SIGNED_6 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_42 = ((_zz__zz_decode_IS_RS2_SIGNED_43 == _zz__zz_decode_IS_RS2_SIGNED_44) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_45 = {(_zz__zz_decode_IS_RS2_SIGNED_46 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_47 != _zz__zz_decode_IS_RS2_SIGNED_55),{_zz__zz_decode_IS_RS2_SIGNED_56,{_zz__zz_decode_IS_RS2_SIGNED_59,_zz__zz_decode_IS_RS2_SIGNED_61}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_43 = (decode_INSTRUCTION & 32'h00004048); + assign _zz__zz_decode_IS_RS2_SIGNED_44 = 32'h00004008; + assign _zz__zz_decode_IS_RS2_SIGNED_46 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_IS_RS2_SIGNED_47 = {(_zz__zz_decode_IS_RS2_SIGNED_48 == _zz__zz_decode_IS_RS2_SIGNED_49),{_zz__zz_decode_IS_RS2_SIGNED_50,{_zz__zz_decode_IS_RS2_SIGNED_51,_zz__zz_decode_IS_RS2_SIGNED_53}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_55 = 4'b0000; + assign _zz__zz_decode_IS_RS2_SIGNED_56 = ((_zz__zz_decode_IS_RS2_SIGNED_57 == _zz__zz_decode_IS_RS2_SIGNED_58) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_59 = (_zz__zz_decode_IS_RS2_SIGNED_60 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_61 = {(_zz__zz_decode_IS_RS2_SIGNED_62 != _zz__zz_decode_IS_RS2_SIGNED_79),{_zz__zz_decode_IS_RS2_SIGNED_80,{_zz__zz_decode_IS_RS2_SIGNED_89,_zz__zz_decode_IS_RS2_SIGNED_102}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_48 = (decode_INSTRUCTION & 32'h00000034); + assign _zz__zz_decode_IS_RS2_SIGNED_49 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_50 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_51 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_52) == 32'h08000020); + assign _zz__zz_decode_IS_RS2_SIGNED_53 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_54) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_57 = (decode_INSTRUCTION & 32'h10000008); + assign _zz__zz_decode_IS_RS2_SIGNED_58 = 32'h00000008; + assign _zz__zz_decode_IS_RS2_SIGNED_60 = ((decode_INSTRUCTION & 32'h10000008) == 32'h10000008); + assign _zz__zz_decode_IS_RS2_SIGNED_62 = {(_zz__zz_decode_IS_RS2_SIGNED_63 == _zz__zz_decode_IS_RS2_SIGNED_64),{_zz__zz_decode_IS_RS2_SIGNED_65,{_zz__zz_decode_IS_RS2_SIGNED_67,_zz__zz_decode_IS_RS2_SIGNED_70}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_79 = 6'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_80 = ({_zz__zz_decode_IS_RS2_SIGNED_81,{_zz__zz_decode_IS_RS2_SIGNED_83,_zz__zz_decode_IS_RS2_SIGNED_86}} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_89 = ({_zz__zz_decode_IS_RS2_SIGNED_90,_zz__zz_decode_IS_RS2_SIGNED_93} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_102 = {(_zz__zz_decode_IS_RS2_SIGNED_103 != _zz__zz_decode_IS_RS2_SIGNED_116),{_zz__zz_decode_IS_RS2_SIGNED_117,{_zz__zz_decode_IS_RS2_SIGNED_134,_zz__zz_decode_IS_RS2_SIGNED_139}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_52 = 32'h08000070; + assign _zz__zz_decode_IS_RS2_SIGNED_54 = 32'h10000070; + assign _zz__zz_decode_IS_RS2_SIGNED_63 = (decode_INSTRUCTION & 32'h00002040); + assign _zz__zz_decode_IS_RS2_SIGNED_64 = 32'h00002040; + assign _zz__zz_decode_IS_RS2_SIGNED_65 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_66) == 32'h00001040); + assign _zz__zz_decode_IS_RS2_SIGNED_67 = (_zz__zz_decode_IS_RS2_SIGNED_68 == _zz__zz_decode_IS_RS2_SIGNED_69); + assign _zz__zz_decode_IS_RS2_SIGNED_70 = {_zz__zz_decode_IS_RS2_SIGNED_71,{_zz__zz_decode_IS_RS2_SIGNED_73,_zz__zz_decode_IS_RS2_SIGNED_76}}; + assign _zz__zz_decode_IS_RS2_SIGNED_81 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_82) == 32'h08000020); + assign _zz__zz_decode_IS_RS2_SIGNED_83 = (_zz__zz_decode_IS_RS2_SIGNED_84 == _zz__zz_decode_IS_RS2_SIGNED_85); + assign _zz__zz_decode_IS_RS2_SIGNED_86 = (_zz__zz_decode_IS_RS2_SIGNED_87 == _zz__zz_decode_IS_RS2_SIGNED_88); + assign _zz__zz_decode_IS_RS2_SIGNED_90 = (_zz__zz_decode_IS_RS2_SIGNED_91 == _zz__zz_decode_IS_RS2_SIGNED_92); + assign _zz__zz_decode_IS_RS2_SIGNED_93 = {_zz__zz_decode_IS_RS2_SIGNED_94,{_zz__zz_decode_IS_RS2_SIGNED_96,_zz__zz_decode_IS_RS2_SIGNED_99}}; + assign _zz__zz_decode_IS_RS2_SIGNED_103 = {_zz_decode_IS_RS2_SIGNED_5,{_zz__zz_decode_IS_RS2_SIGNED_104,_zz__zz_decode_IS_RS2_SIGNED_107}}; + assign _zz__zz_decode_IS_RS2_SIGNED_116 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_117 = ({_zz__zz_decode_IS_RS2_SIGNED_118,_zz__zz_decode_IS_RS2_SIGNED_119} != 7'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_134 = (_zz__zz_decode_IS_RS2_SIGNED_135 != _zz__zz_decode_IS_RS2_SIGNED_138); + assign _zz__zz_decode_IS_RS2_SIGNED_139 = {_zz__zz_decode_IS_RS2_SIGNED_140,{_zz__zz_decode_IS_RS2_SIGNED_145,_zz__zz_decode_IS_RS2_SIGNED_150}}; + assign _zz__zz_decode_IS_RS2_SIGNED_66 = 32'h00001040; + assign _zz__zz_decode_IS_RS2_SIGNED_68 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_69 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_71 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_72) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_73 = (_zz__zz_decode_IS_RS2_SIGNED_74 == _zz__zz_decode_IS_RS2_SIGNED_75); + assign _zz__zz_decode_IS_RS2_SIGNED_76 = (_zz__zz_decode_IS_RS2_SIGNED_77 == _zz__zz_decode_IS_RS2_SIGNED_78); + assign _zz__zz_decode_IS_RS2_SIGNED_82 = 32'h08000020; + assign _zz__zz_decode_IS_RS2_SIGNED_84 = (decode_INSTRUCTION & 32'h10000020); + assign _zz__zz_decode_IS_RS2_SIGNED_85 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_87 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_RS2_SIGNED_88 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_91 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_92 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_94 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_95) == 32'h00004020); + assign _zz__zz_decode_IS_RS2_SIGNED_96 = (_zz__zz_decode_IS_RS2_SIGNED_97 == _zz__zz_decode_IS_RS2_SIGNED_98); + assign _zz__zz_decode_IS_RS2_SIGNED_99 = {_zz_decode_IS_RS2_SIGNED_5,_zz__zz_decode_IS_RS2_SIGNED_100}; + assign _zz__zz_decode_IS_RS2_SIGNED_104 = (_zz__zz_decode_IS_RS2_SIGNED_105 == _zz__zz_decode_IS_RS2_SIGNED_106); + assign _zz__zz_decode_IS_RS2_SIGNED_107 = {_zz__zz_decode_IS_RS2_SIGNED_108,{_zz__zz_decode_IS_RS2_SIGNED_110,_zz__zz_decode_IS_RS2_SIGNED_113}}; + assign _zz__zz_decode_IS_RS2_SIGNED_118 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_119 = {_zz__zz_decode_IS_RS2_SIGNED_120,{_zz__zz_decode_IS_RS2_SIGNED_122,_zz__zz_decode_IS_RS2_SIGNED_125}}; + assign _zz__zz_decode_IS_RS2_SIGNED_135 = {_zz_decode_IS_RS2_SIGNED_4,_zz__zz_decode_IS_RS2_SIGNED_136}; + assign _zz__zz_decode_IS_RS2_SIGNED_138 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_140 = ({_zz__zz_decode_IS_RS2_SIGNED_141,_zz__zz_decode_IS_RS2_SIGNED_142} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_145 = (_zz__zz_decode_IS_RS2_SIGNED_146 != _zz__zz_decode_IS_RS2_SIGNED_149); + assign _zz__zz_decode_IS_RS2_SIGNED_150 = {_zz__zz_decode_IS_RS2_SIGNED_151,{_zz__zz_decode_IS_RS2_SIGNED_154,_zz__zz_decode_IS_RS2_SIGNED_167}}; + assign _zz__zz_decode_IS_RS2_SIGNED_72 = 32'h02400040; + assign _zz__zz_decode_IS_RS2_SIGNED_74 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_IS_RS2_SIGNED_75 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_77 = (decode_INSTRUCTION & 32'h18002008); + assign _zz__zz_decode_IS_RS2_SIGNED_78 = 32'h10002008; + assign _zz__zz_decode_IS_RS2_SIGNED_95 = 32'h00004020; + assign _zz__zz_decode_IS_RS2_SIGNED_97 = (decode_INSTRUCTION & 32'h00000030); + assign _zz__zz_decode_IS_RS2_SIGNED_98 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_100 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_101) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_105 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_IS_RS2_SIGNED_106 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_108 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_109) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_110 = (_zz__zz_decode_IS_RS2_SIGNED_111 == _zz__zz_decode_IS_RS2_SIGNED_112); + assign _zz__zz_decode_IS_RS2_SIGNED_113 = (_zz__zz_decode_IS_RS2_SIGNED_114 == _zz__zz_decode_IS_RS2_SIGNED_115); + assign _zz__zz_decode_IS_RS2_SIGNED_120 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_121) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_122 = (_zz__zz_decode_IS_RS2_SIGNED_123 == _zz__zz_decode_IS_RS2_SIGNED_124); + assign _zz__zz_decode_IS_RS2_SIGNED_125 = {_zz__zz_decode_IS_RS2_SIGNED_126,{_zz__zz_decode_IS_RS2_SIGNED_128,_zz__zz_decode_IS_RS2_SIGNED_131}}; + assign _zz__zz_decode_IS_RS2_SIGNED_136 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_137) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_141 = _zz_decode_IS_RS2_SIGNED_4; + assign _zz__zz_decode_IS_RS2_SIGNED_142 = (_zz__zz_decode_IS_RS2_SIGNED_143 == _zz__zz_decode_IS_RS2_SIGNED_144); + assign _zz__zz_decode_IS_RS2_SIGNED_146 = (_zz__zz_decode_IS_RS2_SIGNED_147 == _zz__zz_decode_IS_RS2_SIGNED_148); + assign _zz__zz_decode_IS_RS2_SIGNED_149 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_151 = (_zz__zz_decode_IS_RS2_SIGNED_152 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_154 = (_zz__zz_decode_IS_RS2_SIGNED_155 != _zz__zz_decode_IS_RS2_SIGNED_166); + assign _zz__zz_decode_IS_RS2_SIGNED_167 = {_zz__zz_decode_IS_RS2_SIGNED_168,{_zz__zz_decode_IS_RS2_SIGNED_173,_zz__zz_decode_IS_RS2_SIGNED_181}}; + assign _zz__zz_decode_IS_RS2_SIGNED_101 = 32'h02000028; + assign _zz__zz_decode_IS_RS2_SIGNED_109 = 32'h00001030; + assign _zz__zz_decode_IS_RS2_SIGNED_111 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_IS_RS2_SIGNED_112 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_114 = (decode_INSTRUCTION & 32'h02002068); + assign _zz__zz_decode_IS_RS2_SIGNED_115 = 32'h00002020; + assign _zz__zz_decode_IS_RS2_SIGNED_121 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_123 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_124 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_126 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_127) == 32'h00002008); + assign _zz__zz_decode_IS_RS2_SIGNED_128 = (_zz__zz_decode_IS_RS2_SIGNED_129 == _zz__zz_decode_IS_RS2_SIGNED_130); + assign _zz__zz_decode_IS_RS2_SIGNED_131 = {_zz_decode_IS_RS2_SIGNED_5,_zz__zz_decode_IS_RS2_SIGNED_132}; + assign _zz__zz_decode_IS_RS2_SIGNED_137 = 32'h00000070; + assign _zz__zz_decode_IS_RS2_SIGNED_143 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_144 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_147 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_IS_RS2_SIGNED_148 = 32'h00004010; + assign _zz__zz_decode_IS_RS2_SIGNED_152 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_153) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_155 = {_zz__zz_decode_IS_RS2_SIGNED_156,{_zz__zz_decode_IS_RS2_SIGNED_158,_zz__zz_decode_IS_RS2_SIGNED_161}}; + assign _zz__zz_decode_IS_RS2_SIGNED_166 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_168 = ({_zz__zz_decode_IS_RS2_SIGNED_169,_zz__zz_decode_IS_RS2_SIGNED_170} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_173 = (_zz__zz_decode_IS_RS2_SIGNED_174 != _zz__zz_decode_IS_RS2_SIGNED_180); + assign _zz__zz_decode_IS_RS2_SIGNED_181 = {_zz__zz_decode_IS_RS2_SIGNED_182,{_zz__zz_decode_IS_RS2_SIGNED_187,_zz__zz_decode_IS_RS2_SIGNED_192}}; + assign _zz__zz_decode_IS_RS2_SIGNED_127 = 32'h00002008; + assign _zz__zz_decode_IS_RS2_SIGNED_129 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_130 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_132 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_133) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_153 = 32'h00006014; + assign _zz__zz_decode_IS_RS2_SIGNED_156 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_157) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_158 = (_zz__zz_decode_IS_RS2_SIGNED_159 == _zz__zz_decode_IS_RS2_SIGNED_160); + assign _zz__zz_decode_IS_RS2_SIGNED_161 = {_zz__zz_decode_IS_RS2_SIGNED_162,{_zz__zz_decode_IS_RS2_SIGNED_163,_zz__zz_decode_IS_RS2_SIGNED_165}}; + assign _zz__zz_decode_IS_RS2_SIGNED_169 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_170 = (_zz__zz_decode_IS_RS2_SIGNED_171 == _zz__zz_decode_IS_RS2_SIGNED_172); + assign _zz__zz_decode_IS_RS2_SIGNED_174 = {_zz__zz_decode_IS_RS2_SIGNED_175,{_zz__zz_decode_IS_RS2_SIGNED_176,_zz__zz_decode_IS_RS2_SIGNED_178}}; + assign _zz__zz_decode_IS_RS2_SIGNED_180 = 3'b000; + assign _zz__zz_decode_IS_RS2_SIGNED_182 = ({_zz__zz_decode_IS_RS2_SIGNED_183,_zz__zz_decode_IS_RS2_SIGNED_184} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_187 = (_zz__zz_decode_IS_RS2_SIGNED_188 != _zz__zz_decode_IS_RS2_SIGNED_191); + assign _zz__zz_decode_IS_RS2_SIGNED_192 = (_zz__zz_decode_IS_RS2_SIGNED_193 != _zz__zz_decode_IS_RS2_SIGNED_195); + assign _zz__zz_decode_IS_RS2_SIGNED_133 = 32'h00000028; + assign _zz__zz_decode_IS_RS2_SIGNED_157 = 32'h00000044; + assign _zz__zz_decode_IS_RS2_SIGNED_159 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_IS_RS2_SIGNED_160 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_162 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_163 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_164) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_165 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_171 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_IS_RS2_SIGNED_172 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_175 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_176 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_177) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_178 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_179) == 32'h40000030); + assign _zz__zz_decode_IS_RS2_SIGNED_183 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_184 = {_zz_decode_IS_RS2_SIGNED_1,(_zz__zz_decode_IS_RS2_SIGNED_185 == _zz__zz_decode_IS_RS2_SIGNED_186)}; + assign _zz__zz_decode_IS_RS2_SIGNED_188 = {_zz_decode_IS_RS2_SIGNED_1,(_zz__zz_decode_IS_RS2_SIGNED_189 == _zz__zz_decode_IS_RS2_SIGNED_190)}; + assign _zz__zz_decode_IS_RS2_SIGNED_191 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_193 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_194) == 32'h00001008); + assign _zz__zz_decode_IS_RS2_SIGNED_195 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_164 = 32'h00005004; + assign _zz__zz_decode_IS_RS2_SIGNED_177 = 32'h00002014; + assign _zz__zz_decode_IS_RS2_SIGNED_179 = 32'h40000034; + assign _zz__zz_decode_IS_RS2_SIGNED_185 = (decode_INSTRUCTION & 32'h00002014); + assign _zz__zz_decode_IS_RS2_SIGNED_186 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_189 = (decode_INSTRUCTION & 32'h0000004c); + assign _zz__zz_decode_IS_RS2_SIGNED_190 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_194 = 32'h00005048; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_205 ), //i - .io_cpu_prefetch_isValid (_zz_206 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_207 ), //i - .io_cpu_fetch_isStuck (_zz_208 ), //i - .io_cpu_fetch_isRemoved (_zz_209 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i - .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i - .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i - .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i - .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i - .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i - .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i - .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_210 ), //i - .io_cpu_decode_isStuck (_zz_211 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_212 ), //i - .io_cpu_fill_valid (_zz_213 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical ), //i + .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical ), //i + .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical ), //i + .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_214 ), //i - .io_cpu_execute_address (_zz_215[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (_zz_216 ), //i - .io_cpu_execute_args_data (_zz_217[31:0] ), //i - .io_cpu_execute_args_size (_zz_218[1:0] ), //i - .io_cpu_execute_args_isLrsc (_zz_219 ), //i - .io_cpu_execute_args_isAmo (_zz_220 ), //i - .io_cpu_execute_args_amoCtrl_swap (_zz_221 ), //i - .io_cpu_execute_args_amoCtrl_alu (_zz_222[2:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_223 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_224[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_225 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i - .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i - .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i - .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i - .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i - .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i - .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i - .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i - .io_cpu_writeBack_isValid (_zz_226 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_227 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_228[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_229 ), //i - .io_cpu_writeBack_fence_SR (_zz_230 ), //i - .io_cpu_writeBack_fence_SO (_zz_231 ), //i - .io_cpu_writeBack_fence_SI (_zz_232 ), //i - .io_cpu_writeBack_fence_PW (_zz_233 ), //i - .io_cpu_writeBack_fence_PR (_zz_234 ), //i - .io_cpu_writeBack_fence_PO (_zz_235 ), //i - .io_cpu_writeBack_fence_PI (_zz_236 ), //i - .io_cpu_writeBack_fence_FM (_zz_237[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_238 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_239 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (dataCache_1_io_cpu_execute_args_wr ), //i + .io_cpu_execute_args_size (dataCache_1_io_cpu_execute_args_size ), //i + .io_cpu_execute_args_isLrsc (dataCache_1_io_cpu_execute_args_isLrsc ), //i + .io_cpu_execute_args_isAmo (execute_MEMORY_AMO ), //i + .io_cpu_execute_args_amoCtrl_swap (dataCache_1_io_cpu_execute_args_amoCtrl_swap ), //i + .io_cpu_execute_args_amoCtrl_alu (dataCache_1_io_cpu_execute_args_amoCtrl_alu ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical ), //i + .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical ), //i + .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical ), //i + .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_472) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_7) 3'b000 : begin - _zz_242 = DBusCachedPlugin_redoBranch_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = DBusCachedPlugin_redoBranch_payload; end 3'b001 : begin - _zz_242 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = CsrPlugin_jumpInterface_payload; end 3'b010 : begin - _zz_242 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = BranchPlugin_jumpInterface_payload; end 3'b011 : begin - _zz_242 = CsrPlugin_redoInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = CsrPlugin_redoInterface_payload; end default : begin - _zz_242 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end always @(*) begin - case(_zz_92) + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) 2'b00 : begin - _zz_243 = MmuPlugin_ports_0_cache_0_valid; - _zz_244 = MmuPlugin_ports_0_cache_0_exception; - _zz_245 = MmuPlugin_ports_0_cache_0_superPage; - _zz_246 = MmuPlugin_ports_0_cache_0_virtualAddress_0; - _zz_247 = MmuPlugin_ports_0_cache_0_virtualAddress_1; - _zz_248 = MmuPlugin_ports_0_cache_0_physicalAddress_0; - _zz_249 = MmuPlugin_ports_0_cache_0_physicalAddress_1; - _zz_250 = MmuPlugin_ports_0_cache_0_allowRead; - _zz_251 = MmuPlugin_ports_0_cache_0_allowWrite; - _zz_252 = MmuPlugin_ports_0_cache_0_allowExecute; - _zz_253 = MmuPlugin_ports_0_cache_0_allowUser; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; end 2'b01 : begin - _zz_243 = MmuPlugin_ports_0_cache_1_valid; - _zz_244 = MmuPlugin_ports_0_cache_1_exception; - _zz_245 = MmuPlugin_ports_0_cache_1_superPage; - _zz_246 = MmuPlugin_ports_0_cache_1_virtualAddress_0; - _zz_247 = MmuPlugin_ports_0_cache_1_virtualAddress_1; - _zz_248 = MmuPlugin_ports_0_cache_1_physicalAddress_0; - _zz_249 = MmuPlugin_ports_0_cache_1_physicalAddress_1; - _zz_250 = MmuPlugin_ports_0_cache_1_allowRead; - _zz_251 = MmuPlugin_ports_0_cache_1_allowWrite; - _zz_252 = MmuPlugin_ports_0_cache_1_allowExecute; - _zz_253 = MmuPlugin_ports_0_cache_1_allowUser; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; end 2'b10 : begin - _zz_243 = MmuPlugin_ports_0_cache_2_valid; - _zz_244 = MmuPlugin_ports_0_cache_2_exception; - _zz_245 = MmuPlugin_ports_0_cache_2_superPage; - _zz_246 = MmuPlugin_ports_0_cache_2_virtualAddress_0; - _zz_247 = MmuPlugin_ports_0_cache_2_virtualAddress_1; - _zz_248 = MmuPlugin_ports_0_cache_2_physicalAddress_0; - _zz_249 = MmuPlugin_ports_0_cache_2_physicalAddress_1; - _zz_250 = MmuPlugin_ports_0_cache_2_allowRead; - _zz_251 = MmuPlugin_ports_0_cache_2_allowWrite; - _zz_252 = MmuPlugin_ports_0_cache_2_allowExecute; - _zz_253 = MmuPlugin_ports_0_cache_2_allowUser; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; end default : begin - _zz_243 = MmuPlugin_ports_0_cache_3_valid; - _zz_244 = MmuPlugin_ports_0_cache_3_exception; - _zz_245 = MmuPlugin_ports_0_cache_3_superPage; - _zz_246 = MmuPlugin_ports_0_cache_3_virtualAddress_0; - _zz_247 = MmuPlugin_ports_0_cache_3_virtualAddress_1; - _zz_248 = MmuPlugin_ports_0_cache_3_physicalAddress_0; - _zz_249 = MmuPlugin_ports_0_cache_3_physicalAddress_1; - _zz_250 = MmuPlugin_ports_0_cache_3_allowRead; - _zz_251 = MmuPlugin_ports_0_cache_3_allowWrite; - _zz_252 = MmuPlugin_ports_0_cache_3_allowExecute; - _zz_253 = MmuPlugin_ports_0_cache_3_allowUser; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end always @(*) begin - case(_zz_96) + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_MmuPlugin_ports_0_cacheLine_valid_3) + 2'b00 : begin + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_0_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_0_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_0_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_0_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_0_allowUser; + end + 2'b01 : begin + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_1_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_1_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_1_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_1_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_1_allowUser; + end + 2'b10 : begin + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_2_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_2_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_2_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_2_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_2_allowUser; + end + default : begin + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_3_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_3_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_3_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_3_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_3_allowUser; + end + endcase + end + + always @(*) begin + case(_zz_MmuPlugin_ports_1_cacheLine_valid_3) 2'b00 : begin - _zz_254 = MmuPlugin_ports_1_cache_0_valid; - _zz_255 = MmuPlugin_ports_1_cache_0_exception; - _zz_256 = MmuPlugin_ports_1_cache_0_superPage; - _zz_257 = MmuPlugin_ports_1_cache_0_virtualAddress_0; - _zz_258 = MmuPlugin_ports_1_cache_0_virtualAddress_1; - _zz_259 = MmuPlugin_ports_1_cache_0_physicalAddress_0; - _zz_260 = MmuPlugin_ports_1_cache_0_physicalAddress_1; - _zz_261 = MmuPlugin_ports_1_cache_0_allowRead; - _zz_262 = MmuPlugin_ports_1_cache_0_allowWrite; - _zz_263 = MmuPlugin_ports_1_cache_0_allowExecute; - _zz_264 = MmuPlugin_ports_1_cache_0_allowUser; + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_0_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_0_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_0_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_0_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_0_allowUser; end 2'b01 : begin - _zz_254 = MmuPlugin_ports_1_cache_1_valid; - _zz_255 = MmuPlugin_ports_1_cache_1_exception; - _zz_256 = MmuPlugin_ports_1_cache_1_superPage; - _zz_257 = MmuPlugin_ports_1_cache_1_virtualAddress_0; - _zz_258 = MmuPlugin_ports_1_cache_1_virtualAddress_1; - _zz_259 = MmuPlugin_ports_1_cache_1_physicalAddress_0; - _zz_260 = MmuPlugin_ports_1_cache_1_physicalAddress_1; - _zz_261 = MmuPlugin_ports_1_cache_1_allowRead; - _zz_262 = MmuPlugin_ports_1_cache_1_allowWrite; - _zz_263 = MmuPlugin_ports_1_cache_1_allowExecute; - _zz_264 = MmuPlugin_ports_1_cache_1_allowUser; + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_1_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_1_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_1_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_1_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_1_allowUser; end 2'b10 : begin - _zz_254 = MmuPlugin_ports_1_cache_2_valid; - _zz_255 = MmuPlugin_ports_1_cache_2_exception; - _zz_256 = MmuPlugin_ports_1_cache_2_superPage; - _zz_257 = MmuPlugin_ports_1_cache_2_virtualAddress_0; - _zz_258 = MmuPlugin_ports_1_cache_2_virtualAddress_1; - _zz_259 = MmuPlugin_ports_1_cache_2_physicalAddress_0; - _zz_260 = MmuPlugin_ports_1_cache_2_physicalAddress_1; - _zz_261 = MmuPlugin_ports_1_cache_2_allowRead; - _zz_262 = MmuPlugin_ports_1_cache_2_allowWrite; - _zz_263 = MmuPlugin_ports_1_cache_2_allowExecute; - _zz_264 = MmuPlugin_ports_1_cache_2_allowUser; + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_2_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_2_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_2_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_2_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_2_allowUser; end default : begin - _zz_254 = MmuPlugin_ports_1_cache_3_valid; - _zz_255 = MmuPlugin_ports_1_cache_3_exception; - _zz_256 = MmuPlugin_ports_1_cache_3_superPage; - _zz_257 = MmuPlugin_ports_1_cache_3_virtualAddress_0; - _zz_258 = MmuPlugin_ports_1_cache_3_virtualAddress_1; - _zz_259 = MmuPlugin_ports_1_cache_3_physicalAddress_0; - _zz_260 = MmuPlugin_ports_1_cache_3_physicalAddress_1; - _zz_261 = MmuPlugin_ports_1_cache_3_allowRead; - _zz_262 = MmuPlugin_ports_1_cache_3_allowWrite; - _zz_263 = MmuPlugin_ports_1_cache_3_allowExecute; - _zz_264 = MmuPlugin_ports_1_cache_3_allowUser; + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_3_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_3_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_3_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_3_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_3_allowUser; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_30) - `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; - default : _zz_30_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_33) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; - default : _zz_33_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_34) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; - default : _zz_34_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_36) - `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; - default : _zz_36_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_37) - `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; - default : _zz_37_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_38) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; - default : _zz_38_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_39) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; - default : _zz_39_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_43) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; - default : _zz_43_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; - default : _zz_44_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_45) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; - default : _zz_45_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_46) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; - default : _zz_46_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_47) - `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; - default : _zz_47_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_48) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; - default : _zz_48_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_49) - `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; - default : _zz_49_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_52) - `BranchCtrlEnum_defaultEncoding_INC : _zz_52_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_52_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_52_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_52_string = "JALR"; - default : _zz_52_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; + `MmuPlugin_shared_State_binary_sequential_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; + `MmuPlugin_shared_State_binary_sequential_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; + `MmuPlugin_shared_State_binary_sequential_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; + `MmuPlugin_shared_State_binary_sequential_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; + `MmuPlugin_shared_State_binary_sequential_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; default : MmuPlugin_shared_state_1_string = "??????"; endcase end always @(*) begin - case(_zz_110) - `Src1CtrlEnum_defaultEncoding_RS : _zz_110_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_110_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_110_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_110_string = "URS1 "; - default : _zz_110_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_111) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_111_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_111_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_111_string = "BITWISE "; - default : _zz_111_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_112) - `Src2CtrlEnum_defaultEncoding_RS : _zz_112_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_112_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_112_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_112_string = "PC "; - default : _zz_112_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_113) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_113_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_113_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_113_string = "AND_1"; - default : _zz_113_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_114) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_114_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_114_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_114_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_114_string = "SRA_1 "; - default : _zz_114_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_115) - `BranchCtrlEnum_defaultEncoding_INC : _zz_115_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_115_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_115_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_115_string = "JALR"; - default : _zz_115_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_116) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_116_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_116_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_116_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_116_string = "ECALL"; - default : _zz_116_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_323) + $signed(_zz_331)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -3123,49 +3165,49 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_333; - assign execute_REGFILE_WRITE_DATA = _zz_118; - assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_215[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign execute_IS_DBUS_SHARING = MmuPlugin_dBusAccess_cmd_fire; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_335[0]; - assign decode_IS_RS1_SIGNED = _zz_336[0]; - assign decode_IS_DIV = _zz_337[0]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_RS2_SIGNED[35]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_RS2_SIGNED[34]; + assign decode_IS_DIV = _zz_decode_IS_RS2_SIGNED[33]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_338[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_339[0]; - assign _zz_8 = _zz_9; - assign _zz_10 = _zz_11; - assign decode_SHIFT_CTRL = _zz_12; - assign _zz_13 = _zz_14; - assign decode_ALU_BITWISE_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_340[0]; - assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; - assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; - assign decode_IS_SFENCE_VMA = _zz_341[0]; - assign decode_MEMORY_MANAGMENT = _zz_342[0]; + assign decode_IS_MUL = _zz_decode_IS_RS2_SIGNED[32]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_RS2_SIGNED[29]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_RS2_SIGNED[22]; + assign decode_IS_SFENCE_VMA = _zz_decode_IS_RS2_SIGNED[21]; + assign decode_IS_SFENCE_VMA2 = _zz_decode_IS_RS2_SIGNED[20]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_RS2_SIGNED[19]; + assign memory_MEMORY_LRSC = execute_to_memory_MEMORY_LRSC; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_343[0]; + assign decode_MEMORY_WR = _zz_decode_IS_RS2_SIGNED[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_344[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_345[0]; - assign decode_SRC2_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_ALU_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_SRC1_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_51; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_RS2_SIGNED[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_RS2_SIGNED[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_decode_MEMORY_FORCE_CONSTISTENCY; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; @@ -3184,25 +3226,26 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27; - assign execute_ENV_CTRL = _zz_28; - assign writeBack_ENV_CTRL = _zz_29; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; + assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_140; - assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_346[0]; - assign decode_RS1_USE = _zz_347[0]; - always @ (*) begin - _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_265)begin - _zz_31 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_RS2_SIGNED[17]; + assign decode_RS1_USE = _zz_decode_IS_RS2_SIGNED[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end - if(DBusCachedPlugin_forceDatapath)begin - _zz_31 = MmuPlugin_dBusAccess_cmd_payload_address; + if(DBusCachedPlugin_forceDatapath) begin + _zz_decode_RS2 = MmuPlugin_dBusAccess_cmd_payload_address; end end @@ -3212,148 +3255,165 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_129)begin - if((_zz_130 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_131; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_266)begin - if(_zz_267)begin - if(_zz_133)begin - decode_RS2 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_268)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_135)begin - decode_RS2 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_269)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_137)begin - decode_RS2 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_129)begin - if((_zz_130 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_131; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_266)begin - if(_zz_267)begin - if(_zz_132)begin - decode_RS1 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_268)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_134)begin - decode_RS1 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_269)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_136)begin - decode_RS1 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_32 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_32 = _zz_126; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_32 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_270)begin - _zz_32 = memory_DivPlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_33; - assign execute_SHIFT_CTRL = _zz_34; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_35 = execute_PC; - assign execute_SRC2_CTRL = _zz_36; - assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_348[0]; - assign decode_SRC_ADD_ZERO = _zz_349[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_RS2_SIGNED[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_RS2_SIGNED[18]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_38; - assign execute_SRC2 = _zz_124; - assign execute_SRC1 = _zz_119; - assign execute_ALU_BITWISE_CTRL = _zz_39; - assign _zz_40 = writeBack_INSTRUCTION; - assign _zz_41 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_42 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_42 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_350[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_RS2_SIGNED[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_473) == 32'h00001073),{(_zz_474 == _zz_475),{_zz_476,{_zz_477,_zz_478}}}}}}} != 25'h0); - assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 25'h0); + assign execute_IS_SFENCE_VMA2 = decode_to_execute_IS_SFENCE_VMA2; assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; - always @ (*) begin - _zz_50 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_50 = writeBack_DBusCachedPlugin_rspFormated; + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_322) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_50 = _zz_407; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_50 = _zz_408; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_LRSC = memory_to_writeBack_MEMORY_LRSC; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; - assign execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + always @(*) begin + execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + execute_MEMORY_AMO = 1'b0; + end + end + end + + always @(*) begin + execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + execute_MEMORY_LRSC = 1'b0; + end + end + end + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; @@ -3361,223 +3421,224 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_AMO = _zz_351[0]; - assign decode_MEMORY_LRSC = _zz_352[0]; - assign decode_MEMORY_ENABLE = _zz_353[0]; - assign decode_FLUSH_ALL = _zz_354[0]; - always @ (*) begin + assign decode_MEMORY_AMO = _zz_decode_IS_RS2_SIGNED[16]; + assign decode_MEMORY_LRSC = _zz_decode_IS_RS2_SIGNED[15]; + assign decode_MEMORY_ENABLE = _zz_decode_IS_RS2_SIGNED[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_RS2_SIGNED[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_271)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_272)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_273)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_274)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_52; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_53 = execute_FORMAL_PC_NEXT; - if(CsrPlugin_redoInterface_valid)begin - _zz_53 = CsrPlugin_redoInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(CsrPlugin_redoInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = CsrPlugin_redoInterface_payload; end end - always @ (*) begin - _zz_54 = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_54 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_55 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_55 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if(MmuPlugin_dBusAccess_cmd_valid)begin + if(MmuPlugin_dBusAccess_cmd_valid) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if((decode_arbitration_isValid && (_zz_127 || _zz_128)))begin + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_275)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_275)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_238 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_276)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_265)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin execute_arbitration_flushNext = 1'b1; end - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeInstruction)begin - execute_arbitration_flushNext = 1'b1; - end + if(CsrPlugin_selfException_valid) begin + execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_270)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_277)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_278)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3586,51 +3647,53 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_277)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_278)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_276)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_277)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_278)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_277)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_278)begin - case(_zz_279) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3646,60 +3709,66 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != 5'h0); - assign _zz_56 = {IBusCachedPlugin_predictionJumpInterface_valid,{CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_57 = (_zz_56 & (~ _zz_355)); - assign _zz_58 = _zz_57[3]; - assign _zz_59 = _zz_57[4]; - assign _zz_60 = (_zz_57[1] || _zz_58); - assign _zz_61 = (_zz_57[2] || _zz_58); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_242; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[4]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_357); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3707,265 +3776,286 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_62 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_62); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_62); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_63 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_63); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_63); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_64 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_64); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_64); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_65; - assign _zz_65 = ((1'b0 && (! _zz_66)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_66 = _zz_67; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_66; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_68)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_68 = _zz_69; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_68; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_70; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_71 = _zz_358[11]; - always @ (*) begin - _zz_72[18] = _zz_71; - _zz_72[17] = _zz_71; - _zz_72[16] = _zz_71; - _zz_72[15] = _zz_71; - _zz_72[14] = _zz_71; - _zz_72[13] = _zz_71; - _zz_72[12] = _zz_71; - _zz_72[11] = _zz_71; - _zz_72[10] = _zz_71; - _zz_72[9] = _zz_71; - _zz_72[8] = _zz_71; - _zz_72[7] = _zz_71; - _zz_72[6] = _zz_71; - _zz_72[5] = _zz_71; - _zz_72[4] = _zz_71; - _zz_72[3] = _zz_71; - _zz_72[2] = _zz_71; - _zz_72[1] = _zz_71; - _zz_72[0] = _zz_71; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_359[31])); - if(_zz_77)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_73 = _zz_360[19]; - always @ (*) begin - _zz_74[10] = _zz_73; - _zz_74[9] = _zz_73; - _zz_74[8] = _zz_73; - _zz_74[7] = _zz_73; - _zz_74[6] = _zz_73; - _zz_74[5] = _zz_73; - _zz_74[4] = _zz_73; - _zz_74[3] = _zz_73; - _zz_74[2] = _zz_73; - _zz_74[1] = _zz_73; - _zz_74[0] = _zz_73; - end - - assign _zz_75 = _zz_361[11]; - always @ (*) begin - _zz_76[18] = _zz_75; - _zz_76[17] = _zz_75; - _zz_76[16] = _zz_75; - _zz_76[15] = _zz_75; - _zz_76[14] = _zz_75; - _zz_76[13] = _zz_75; - _zz_76[12] = _zz_75; - _zz_76[11] = _zz_75; - _zz_76[10] = _zz_75; - _zz_76[9] = _zz_75; - _zz_76[8] = _zz_75; - _zz_76[7] = _zz_75; - _zz_76[6] = _zz_75; - _zz_76[5] = _zz_75; - _zz_76[4] = _zz_75; - _zz_76[3] = _zz_75; - _zz_76[2] = _zz_75; - _zz_76[1] = _zz_75; - _zz_76[0] = _zz_75; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_77 = _zz_362[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_77 = _zz_363[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_78 = _zz_364[19]; - always @ (*) begin - _zz_79[10] = _zz_78; - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7] = _zz_78; - _zz_79[6] = _zz_78; - _zz_79[5] = _zz_78; - _zz_79[4] = _zz_78; - _zz_79[3] = _zz_78; - _zz_79[2] = _zz_78; - _zz_79[1] = _zz_78; - _zz_79[0] = _zz_78; - end - - assign _zz_80 = _zz_365[11]; - always @ (*) begin - _zz_81[18] = _zz_80; - _zz_81[17] = _zz_80; - _zz_81[16] = _zz_80; - _zz_81[15] = _zz_80; - _zz_81[14] = _zz_80; - _zz_81[13] = _zz_80; - _zz_81[12] = _zz_80; - _zz_81[11] = _zz_80; - _zz_81[10] = _zz_80; - _zz_81[9] = _zz_80; - _zz_81[8] = _zz_80; - _zz_81[7] = _zz_80; - _zz_81[6] = _zz_80; - _zz_81[5] = _zz_80; - _zz_81[4] = _zz_80; - _zz_81[3] = _zz_80; - _zz_81[2] = _zz_80; - _zz_81[1] = _zz_80; - _zz_81[0] = _zz_80; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_79,{{{_zz_496,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_81,{{{_zz_497,_zz_498},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_206 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_207 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_208 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_207; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_210 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_211 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_212 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_274)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_272)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_213 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_272)begin - _zz_213 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_273)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_271)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_273)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_271)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_205 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_239 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3973,328 +4063,320 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - always @ (*) begin - _zz_51 = 1'b0; - if(decode_INSTRUCTION[25])begin - if(decode_MEMORY_LRSC)begin - _zz_51 = 1'b1; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + always @(*) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + if(when_DBusCachedPlugin_l311) begin + if(decode_MEMORY_LRSC) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b1; end - if(decode_MEMORY_AMO)begin - _zz_51 = 1'b1; + if(decode_MEMORY_AMO) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b1; end end end + assign when_DBusCachedPlugin_l311 = decode_INSTRUCTION[25]; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin - _zz_214 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_280)begin - if(_zz_281)begin - _zz_214 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + if(when_DBusCachedPlugin_l499) begin + dataCache_1_io_cpu_execute_isValid = 1'b1; end end end end - always @ (*) begin - _zz_215 = execute_SRC_ADD; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_280)begin - _zz_215 = MmuPlugin_dBusAccess_cmd_payload_address; + always @(*) begin + dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_address = MmuPlugin_dBusAccess_cmd_payload_address; end end end - always @ (*) begin - _zz_216 = execute_MEMORY_WR; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_280)begin - _zz_216 = MmuPlugin_dBusAccess_cmd_payload_write; + always @(*) begin + dataCache_1_io_cpu_execute_args_wr = execute_MEMORY_WR; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_args_wr = 1'b0; end end end - always @ (*) begin + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_84 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_84 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_84 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - always @ (*) begin - _zz_217 = _zz_84; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_280)begin - _zz_217 = MmuPlugin_dBusAccess_cmd_payload_data; - end - end - end - - always @ (*) begin - _zz_218 = execute_DBusCachedPlugin_size; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_280)begin - _zz_218 = MmuPlugin_dBusAccess_cmd_payload_size; - end - end - end - - assign _zz_238 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - always @ (*) begin - _zz_219 = 1'b0; - if(execute_MEMORY_LRSC)begin - _zz_219 = 1'b1; - end - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_280)begin - _zz_219 = 1'b0; + always @(*) begin + dataCache_1_io_cpu_execute_args_size = execute_DBusCachedPlugin_size; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_args_size = MmuPlugin_dBusAccess_cmd_payload_size; end end end - always @ (*) begin - _zz_220 = execute_MEMORY_AMO; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_280)begin - _zz_220 = 1'b0; - end + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + always @(*) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b0; + if(execute_MEMORY_LRSC) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b1; end end - assign _zz_222 = execute_INSTRUCTION[31 : 29]; - assign _zz_221 = execute_INSTRUCTION[27]; - always @ (*) begin - _zz_223 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - if(memory_IS_DBUS_SHARING)begin - _zz_223 = 1'b1; + assign dataCache_1_io_cpu_execute_args_amoCtrl_alu = execute_INSTRUCTION[31 : 29]; + assign dataCache_1_io_cpu_execute_args_amoCtrl_swap = execute_INSTRUCTION[27]; + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + always @(*) begin + dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + if(memory_IS_DBUS_SHARING) begin + dataCache_1_io_cpu_memory_isValid = 1'b1; end end - assign _zz_224 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_223; + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_224; - always @ (*) begin + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; + always @(*) begin DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - if(memory_IS_DBUS_SHARING)begin + if(memory_IS_DBUS_SHARING) begin DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; end end assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_225 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_225 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; end end - always @ (*) begin - _zz_226 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - if(writeBack_IS_DBUS_SHARING)begin - _zz_226 = 1'b1; + assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_IS_DBUS_SHARING) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b1; + end + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_227 = (CsrPlugin_privilege == 2'b00); - assign _zz_228 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_282)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_282)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_282)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_366}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_367}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + always @(*) begin + writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + if(when_DBusCachedPlugin_l474) begin + writeBack_DBusCachedPlugin_rspRf = {31'd0, _zz_writeBack_DBusCachedPlugin_rspRf}; + end + end + + assign when_DBusCachedPlugin_l474 = (writeBack_MEMORY_LRSC && writeBack_MEMORY_WR); + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; end - assign _zz_85 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_86[31] = _zz_85; - _zz_86[30] = _zz_85; - _zz_86[29] = _zz_85; - _zz_86[28] = _zz_85; - _zz_86[27] = _zz_85; - _zz_86[26] = _zz_85; - _zz_86[25] = _zz_85; - _zz_86[24] = _zz_85; - _zz_86[23] = _zz_85; - _zz_86[22] = _zz_85; - _zz_86[21] = _zz_85; - _zz_86[20] = _zz_85; - _zz_86[19] = _zz_85; - _zz_86[18] = _zz_85; - _zz_86[17] = _zz_85; - _zz_86[16] = _zz_85; - _zz_86[15] = _zz_85; - _zz_86[14] = _zz_85; - _zz_86[13] = _zz_85; - _zz_86[12] = _zz_85; - _zz_86[11] = _zz_85; - _zz_86[10] = _zz_85; - _zz_86[9] = _zz_85; - _zz_86[8] = _zz_85; - _zz_86[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_87 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_88[31] = _zz_87; - _zz_88[30] = _zz_87; - _zz_88[29] = _zz_87; - _zz_88[28] = _zz_87; - _zz_88[27] = _zz_87; - _zz_88[26] = _zz_87; - _zz_88[25] = _zz_87; - _zz_88[24] = _zz_87; - _zz_88[23] = _zz_87; - _zz_88[22] = _zz_87; - _zz_88[21] = _zz_87; - _zz_88[20] = _zz_87; - _zz_88[19] = _zz_87; - _zz_88[18] = _zz_87; - _zz_88[17] = _zz_87; - _zz_88[16] = _zz_87; - _zz_88[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_320) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_86; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_88; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end - always @ (*) begin + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + always @(*) begin MmuPlugin_dBusAccess_cmd_ready = 1'b0; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_280)begin - if(_zz_281)begin + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + if(when_DBusCachedPlugin_l499) begin MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); end end end end - always @ (*) begin + always @(*) begin DBusCachedPlugin_forceDatapath = 1'b0; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_280)begin + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin DBusCachedPlugin_forceDatapath = 1'b1; end end end + assign when_DBusCachedPlugin_l498 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign when_DBusCachedPlugin_l499 = (! dataCache_1_io_cpu_execute_refilling); + assign MmuPlugin_dBusAccess_cmd_fire = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); - assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1_io_cpu_writeBack_data; + assign MmuPlugin_dBusAccess_rsp_payload_data = writeBack_DBusCachedPlugin_rspRf; assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; assign MmuPlugin_ports_0_dirty = 1'b0; - always @ (*) begin + always @(*) begin MmuPlugin_ports_0_requireMmuLockupCalc = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + if(when_MmuPlugin_l125) begin MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; end - if((CsrPlugin_privilege == 2'b11))begin + if(when_MmuPlugin_l126) begin MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; end end - always @ (*) begin - MmuPlugin_ports_0_cacheHitsCalc[0] = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_0_cacheHitsCalc[1] = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_0_cacheHitsCalc[2] = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_0_cacheHitsCalc[3] = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - end - + assign when_MmuPlugin_l125 = ((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)); + assign when_MmuPlugin_l126 = (CsrPlugin_privilege == 2'b11); + assign MmuPlugin_ports_0_cacheHitsCalc = {((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))),{((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == _zz_MmuPlugin_ports_0_cacheHitsCalc)) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == _zz_MmuPlugin_ports_0_cacheHitsCalc_1))),{((MmuPlugin_ports_0_cache_1_valid && _zz_MmuPlugin_ports_0_cacheHitsCalc_2) && (MmuPlugin_ports_0_cache_1_superPage || _zz_MmuPlugin_ports_0_cacheHitsCalc_3)),((MmuPlugin_ports_0_cache_0_valid && _zz_MmuPlugin_ports_0_cacheHitsCalc_4) && (MmuPlugin_ports_0_cache_0_superPage || _zz_MmuPlugin_ports_0_cacheHitsCalc_5))}}}; assign MmuPlugin_ports_0_cacheHit = (MmuPlugin_ports_0_cacheHitsCalc != 4'b0000); - assign _zz_89 = MmuPlugin_ports_0_cacheHitsCalc[3]; - assign _zz_90 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_89); - assign _zz_91 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_89); - assign _zz_92 = {_zz_91,_zz_90}; - assign MmuPlugin_ports_0_cacheLine_valid = _zz_243; - assign MmuPlugin_ports_0_cacheLine_exception = _zz_244; - assign MmuPlugin_ports_0_cacheLine_superPage = _zz_245; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_246; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_247; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_248; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_249; - assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_250; - assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_251; - assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_252; - assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_253; - always @ (*) begin + assign _zz_MmuPlugin_ports_0_cacheLine_valid = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign _zz_MmuPlugin_ports_0_cacheLine_valid_1 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_MmuPlugin_ports_0_cacheLine_valid); + assign _zz_MmuPlugin_ports_0_cacheLine_valid_2 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_MmuPlugin_ports_0_cacheLine_valid); + assign _zz_MmuPlugin_ports_0_cacheLine_valid_3 = {_zz_MmuPlugin_ports_0_cacheLine_valid_2,_zz_MmuPlugin_ports_0_cacheLine_valid_1}; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_MmuPlugin_ports_0_cacheLine_valid_4; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_MmuPlugin_ports_0_cacheLine_exception; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_MmuPlugin_ports_0_cacheLine_superPage; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_MmuPlugin_ports_0_cacheLine_allowRead; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_MmuPlugin_ports_0_cacheLine_allowWrite; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_MmuPlugin_ports_0_cacheLine_allowExecute; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_MmuPlugin_ports_0_cacheLine_allowUser; + always @(*) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; - if(_zz_283)begin - if(_zz_284)begin + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; end end @@ -4303,63 +4385,63 @@ module VexRiscv ( assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); - always @ (*) begin - MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_369); - if(MmuPlugin_ports_0_entryToReplace_willClear)begin + always @(*) begin + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_MmuPlugin_ports_0_entryToReplace_valueNext); + if(MmuPlugin_ports_0_entryToReplace_willClear) begin MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; end else begin IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); end else begin IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; end else begin IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; end else begin IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); end else begin IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; @@ -4377,45 +4459,42 @@ module VexRiscv ( assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; assign MmuPlugin_ports_1_dirty = 1'b0; - always @ (*) begin + always @(*) begin MmuPlugin_ports_1_requireMmuLockupCalc = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + if(when_MmuPlugin_l125_1) begin MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; end - if((CsrPlugin_privilege == 2'b11))begin - if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)))begin + if(when_MmuPlugin_l126_1) begin + if(when_MmuPlugin_l128) begin MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; end end end - always @ (*) begin - MmuPlugin_ports_1_cacheHitsCalc[0] = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_1_cacheHitsCalc[1] = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_1_cacheHitsCalc[2] = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_1_cacheHitsCalc[3] = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - end - + assign when_MmuPlugin_l125_1 = ((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)); + assign when_MmuPlugin_l126_1 = (CsrPlugin_privilege == 2'b11); + assign when_MmuPlugin_l128 = ((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)); + assign MmuPlugin_ports_1_cacheHitsCalc = {((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))),{((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == _zz_MmuPlugin_ports_1_cacheHitsCalc)) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == _zz_MmuPlugin_ports_1_cacheHitsCalc_1))),{((MmuPlugin_ports_1_cache_1_valid && _zz_MmuPlugin_ports_1_cacheHitsCalc_2) && (MmuPlugin_ports_1_cache_1_superPage || _zz_MmuPlugin_ports_1_cacheHitsCalc_3)),((MmuPlugin_ports_1_cache_0_valid && _zz_MmuPlugin_ports_1_cacheHitsCalc_4) && (MmuPlugin_ports_1_cache_0_superPage || _zz_MmuPlugin_ports_1_cacheHitsCalc_5))}}}; assign MmuPlugin_ports_1_cacheHit = (MmuPlugin_ports_1_cacheHitsCalc != 4'b0000); - assign _zz_93 = MmuPlugin_ports_1_cacheHitsCalc[3]; - assign _zz_94 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_93); - assign _zz_95 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_93); - assign _zz_96 = {_zz_95,_zz_94}; - assign MmuPlugin_ports_1_cacheLine_valid = _zz_254; - assign MmuPlugin_ports_1_cacheLine_exception = _zz_255; - assign MmuPlugin_ports_1_cacheLine_superPage = _zz_256; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_257; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_258; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_259; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_260; - assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_261; - assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_262; - assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_263; - assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_264; - always @ (*) begin + assign _zz_MmuPlugin_ports_1_cacheLine_valid = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign _zz_MmuPlugin_ports_1_cacheLine_valid_1 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_MmuPlugin_ports_1_cacheLine_valid); + assign _zz_MmuPlugin_ports_1_cacheLine_valid_2 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_MmuPlugin_ports_1_cacheLine_valid); + assign _zz_MmuPlugin_ports_1_cacheLine_valid_3 = {_zz_MmuPlugin_ports_1_cacheLine_valid_2,_zz_MmuPlugin_ports_1_cacheLine_valid_1}; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_MmuPlugin_ports_1_cacheLine_valid_4; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_MmuPlugin_ports_1_cacheLine_exception; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_MmuPlugin_ports_1_cacheLine_superPage; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_MmuPlugin_ports_1_cacheLine_allowRead; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_MmuPlugin_ports_1_cacheLine_allowWrite; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_MmuPlugin_ports_1_cacheLine_allowExecute; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_MmuPlugin_ports_1_cacheLine_allowUser; + always @(*) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; - if(_zz_283)begin - if(_zz_285)begin + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274_1) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; end end @@ -4424,63 +4503,63 @@ module VexRiscv ( assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); - always @ (*) begin - MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_371); - if(MmuPlugin_ports_1_entryToReplace_willClear)begin + always @(*) begin + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_MmuPlugin_ports_1_entryToReplace_valueNext); + if(MmuPlugin_ports_1_entryToReplace_willClear) begin MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; end else begin DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); end else begin DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; end else begin DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; end else begin DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); end else begin DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; @@ -4497,30 +4576,31 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; - assign MmuPlugin_shared_dBusRsp_pte_V = _zz_372[0]; - assign MmuPlugin_shared_dBusRsp_pte_R = _zz_373[0]; - assign MmuPlugin_shared_dBusRsp_pte_W = _zz_374[0]; - assign MmuPlugin_shared_dBusRsp_pte_X = _zz_375[0]; - assign MmuPlugin_shared_dBusRsp_pte_U = _zz_376[0]; - assign MmuPlugin_shared_dBusRsp_pte_G = _zz_377[0]; - assign MmuPlugin_shared_dBusRsp_pte_A = _zz_378[0]; - assign MmuPlugin_shared_dBusRsp_pte_D = _zz_379[0]; + assign MmuPlugin_shared_dBusRsp_pte_V = MmuPlugin_shared_dBusRspStaged_payload_data[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = MmuPlugin_shared_dBusRspStaged_payload_data[1]; + assign MmuPlugin_shared_dBusRsp_pte_W = MmuPlugin_shared_dBusRspStaged_payload_data[2]; + assign MmuPlugin_shared_dBusRsp_pte_X = MmuPlugin_shared_dBusRspStaged_payload_data[3]; + assign MmuPlugin_shared_dBusRsp_pte_U = MmuPlugin_shared_dBusRspStaged_payload_data[4]; + assign MmuPlugin_shared_dBusRsp_pte_G = MmuPlugin_shared_dBusRspStaged_payload_data[5]; + assign MmuPlugin_shared_dBusRsp_pte_A = MmuPlugin_shared_dBusRspStaged_payload_data[6]; + assign MmuPlugin_shared_dBusRsp_pte_D = MmuPlugin_shared_dBusRspStaged_payload_data[7]; assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); - always @ (*) begin + assign when_MmuPlugin_l205 = (MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)); + always @(*) begin MmuPlugin_dBusAccess_cmd_valid = 1'b0; case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + `MmuPlugin_shared_State_binary_sequential_IDLE : begin end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin MmuPlugin_dBusAccess_cmd_valid = 1'b1; end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin MmuPlugin_dBusAccess_cmd_valid = 1'b1; end default : begin @@ -4530,17 +4610,17 @@ module VexRiscv ( assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; - always @ (*) begin - MmuPlugin_dBusAccess_cmd_payload_address = 32'h0; + always @(*) begin + MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + `MmuPlugin_shared_State_binary_sequential_IDLE : begin end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; end default : begin @@ -4548,84 +4628,95 @@ module VexRiscv ( endcase end - assign MmuPlugin_dBusAccess_cmd_payload_data = 32'h0; + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; - always @ (*) begin - _zz_97[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); - _zz_97[1] = (((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)); - end - - assign _zz_98 = _zz_97; - always @ (*) begin - _zz_99[0] = _zz_98[1]; - _zz_99[1] = _zz_98[0]; - end - - assign _zz_100 = (_zz_99 & (~ _zz_380)); - always @ (*) begin - _zz_101[0] = _zz_100[1]; - _zz_101[1] = _zz_100[0]; - end - - assign MmuPlugin_shared_refills = _zz_101; - assign _zz_102 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); - assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[0]); - assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[1]); - assign _zz_104 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_105 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_106 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); - assign _zz_107 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_108 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_109 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_103 = {(_zz_109 != 1'b0),{(_zz_109 != 1'b0),{((_zz_499 == _zz_500) != 1'b0),{(_zz_501 != 1'b0),{(_zz_502 != _zz_503),{_zz_504,{_zz_505,_zz_506}}}}}}}; - assign _zz_110 = _zz_103[2 : 1]; - assign _zz_49 = _zz_110; - assign _zz_111 = _zz_103[7 : 6]; - assign _zz_48 = _zz_111; - assign _zz_112 = _zz_103[9 : 8]; - assign _zz_47 = _zz_112; - assign _zz_113 = _zz_103[23 : 22]; - assign _zz_46 = _zz_113; - assign _zz_114 = _zz_103[25 : 24]; - assign _zz_45 = _zz_114; - assign _zz_115 = _zz_103[27 : 26]; - assign _zz_44 = _zz_115; - assign _zz_116 = _zz_103[30 : 29]; - assign _zz_43 = _zz_116; + assign _zz_MmuPlugin_shared_refills = {(((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)),(((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit))}; + always @(*) begin + _zz_MmuPlugin_shared_refills_1[0] = _zz_MmuPlugin_shared_refills[1]; + _zz_MmuPlugin_shared_refills_1[1] = _zz_MmuPlugin_shared_refills[0]; + end + + assign _zz_MmuPlugin_shared_refills_2 = (_zz_MmuPlugin_shared_refills_1 & (~ _zz__zz_MmuPlugin_shared_refills_2)); + always @(*) begin + _zz_MmuPlugin_shared_refills_3[0] = _zz_MmuPlugin_shared_refills_2[1]; + _zz_MmuPlugin_shared_refills_3[1] = _zz_MmuPlugin_shared_refills_2[0]; + end + + assign MmuPlugin_shared_refills = _zz_MmuPlugin_shared_refills_3; + assign when_MmuPlugin_l217 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_MmuPlugin_shared_vpn_0 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); + assign when_MmuPlugin_l243 = (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception); + assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_binary_sequential_IDLE) && MmuPlugin_shared_portSortedOh[0]); + assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_binary_sequential_IDLE) && MmuPlugin_shared_portSortedOh[1]); + assign when_MmuPlugin_l272 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign when_MmuPlugin_l274 = MmuPlugin_shared_portSortedOh[0]; + assign when_MmuPlugin_l280 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign when_MmuPlugin_l280_1 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign when_MmuPlugin_l280_2 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign when_MmuPlugin_l280_3 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign when_MmuPlugin_l274_1 = MmuPlugin_shared_portSortedOh[1]; + assign when_MmuPlugin_l280_4 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign when_MmuPlugin_l280_5 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign when_MmuPlugin_l280_6 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign when_MmuPlugin_l280_7 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign when_MmuPlugin_l304 = ((execute_arbitration_isValid && execute_arbitration_isFiring) && execute_IS_SFENCE_VMA2); + assign _zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); + assign _zz_decode_IS_RS2_SIGNED_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_5 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_6 = ((decode_INSTRUCTION & 32'h02003050) == 32'h02000050); + assign _zz_decode_IS_RS2_SIGNED_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_IS_RS2_SIGNED = {(_zz_decode_IS_RS2_SIGNED_7 != 1'b0),{(_zz_decode_IS_RS2_SIGNED_7 != 1'b0),{((_zz__zz_decode_IS_RS2_SIGNED == _zz__zz_decode_IS_RS2_SIGNED_1) != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_2 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_3 != _zz__zz_decode_IS_RS2_SIGNED_4),{_zz__zz_decode_IS_RS2_SIGNED_5,{_zz__zz_decode_IS_RS2_SIGNED_7,_zz__zz_decode_IS_RS2_SIGNED_10}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_RS2_SIGNED[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_RS2_SIGNED[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_RS2_SIGNED[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_RS2_SIGNED[24 : 23]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_RS2_SIGNED[26 : 25]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_RS2_SIGNED[28 : 27]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_RS2_SIGNED[31 : 30]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_240; - assign decode_RegFilePlugin_rs2Data = _zz_241; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); - if(_zz_117)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; - if(_zz_117)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_50; - if(_zz_117)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -4634,355 +4725,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_118 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_118 = {31'd0, _zz_381}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_118 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_119 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_119 = {29'd0, _zz_382}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_119 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_119 = {27'd0, _zz_383}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_120 = _zz_384[11]; - always @ (*) begin - _zz_121[19] = _zz_120; - _zz_121[18] = _zz_120; - _zz_121[17] = _zz_120; - _zz_121[16] = _zz_120; - _zz_121[15] = _zz_120; - _zz_121[14] = _zz_120; - _zz_121[13] = _zz_120; - _zz_121[12] = _zz_120; - _zz_121[11] = _zz_120; - _zz_121[10] = _zz_120; - _zz_121[9] = _zz_120; - _zz_121[8] = _zz_120; - _zz_121[7] = _zz_120; - _zz_121[6] = _zz_120; - _zz_121[5] = _zz_120; - _zz_121[4] = _zz_120; - _zz_121[3] = _zz_120; - _zz_121[2] = _zz_120; - _zz_121[1] = _zz_120; - _zz_121[0] = _zz_120; - end - - assign _zz_122 = _zz_385[11]; - always @ (*) begin - _zz_123[19] = _zz_122; - _zz_123[18] = _zz_122; - _zz_123[17] = _zz_122; - _zz_123[16] = _zz_122; - _zz_123[15] = _zz_122; - _zz_123[14] = _zz_122; - _zz_123[13] = _zz_122; - _zz_123[12] = _zz_122; - _zz_123[11] = _zz_122; - _zz_123[10] = _zz_122; - _zz_123[9] = _zz_122; - _zz_123[8] = _zz_122; - _zz_123[7] = _zz_122; - _zz_123[6] = _zz_122; - _zz_123[5] = _zz_122; - _zz_123[4] = _zz_122; - _zz_123[3] = _zz_122; - _zz_123[2] = _zz_122; - _zz_123[1] = _zz_122; - _zz_123[0] = _zz_122; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_124 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_124 = {_zz_121,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_124 = {_zz_123,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_124 = _zz_35; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_386; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_125[0] = execute_SRC1[31]; - _zz_125[1] = execute_SRC1[30]; - _zz_125[2] = execute_SRC1[29]; - _zz_125[3] = execute_SRC1[28]; - _zz_125[4] = execute_SRC1[27]; - _zz_125[5] = execute_SRC1[26]; - _zz_125[6] = execute_SRC1[25]; - _zz_125[7] = execute_SRC1[24]; - _zz_125[8] = execute_SRC1[23]; - _zz_125[9] = execute_SRC1[22]; - _zz_125[10] = execute_SRC1[21]; - _zz_125[11] = execute_SRC1[20]; - _zz_125[12] = execute_SRC1[19]; - _zz_125[13] = execute_SRC1[18]; - _zz_125[14] = execute_SRC1[17]; - _zz_125[15] = execute_SRC1[16]; - _zz_125[16] = execute_SRC1[15]; - _zz_125[17] = execute_SRC1[14]; - _zz_125[18] = execute_SRC1[13]; - _zz_125[19] = execute_SRC1[12]; - _zz_125[20] = execute_SRC1[11]; - _zz_125[21] = execute_SRC1[10]; - _zz_125[22] = execute_SRC1[9]; - _zz_125[23] = execute_SRC1[8]; - _zz_125[24] = execute_SRC1[7]; - _zz_125[25] = execute_SRC1[6]; - _zz_125[26] = execute_SRC1[5]; - _zz_125[27] = execute_SRC1[4]; - _zz_125[28] = execute_SRC1[3]; - _zz_125[29] = execute_SRC1[2]; - _zz_125[30] = execute_SRC1[1]; - _zz_125[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_125 : execute_SRC1); - always @ (*) begin - _zz_126[0] = memory_SHIFT_RIGHT[31]; - _zz_126[1] = memory_SHIFT_RIGHT[30]; - _zz_126[2] = memory_SHIFT_RIGHT[29]; - _zz_126[3] = memory_SHIFT_RIGHT[28]; - _zz_126[4] = memory_SHIFT_RIGHT[27]; - _zz_126[5] = memory_SHIFT_RIGHT[26]; - _zz_126[6] = memory_SHIFT_RIGHT[25]; - _zz_126[7] = memory_SHIFT_RIGHT[24]; - _zz_126[8] = memory_SHIFT_RIGHT[23]; - _zz_126[9] = memory_SHIFT_RIGHT[22]; - _zz_126[10] = memory_SHIFT_RIGHT[21]; - _zz_126[11] = memory_SHIFT_RIGHT[20]; - _zz_126[12] = memory_SHIFT_RIGHT[19]; - _zz_126[13] = memory_SHIFT_RIGHT[18]; - _zz_126[14] = memory_SHIFT_RIGHT[17]; - _zz_126[15] = memory_SHIFT_RIGHT[16]; - _zz_126[16] = memory_SHIFT_RIGHT[15]; - _zz_126[17] = memory_SHIFT_RIGHT[14]; - _zz_126[18] = memory_SHIFT_RIGHT[13]; - _zz_126[19] = memory_SHIFT_RIGHT[12]; - _zz_126[20] = memory_SHIFT_RIGHT[11]; - _zz_126[21] = memory_SHIFT_RIGHT[10]; - _zz_126[22] = memory_SHIFT_RIGHT[9]; - _zz_126[23] = memory_SHIFT_RIGHT[8]; - _zz_126[24] = memory_SHIFT_RIGHT[7]; - _zz_126[25] = memory_SHIFT_RIGHT[6]; - _zz_126[26] = memory_SHIFT_RIGHT[5]; - _zz_126[27] = memory_SHIFT_RIGHT[4]; - _zz_126[28] = memory_SHIFT_RIGHT[3]; - _zz_126[29] = memory_SHIFT_RIGHT[2]; - _zz_126[30] = memory_SHIFT_RIGHT[1]; - _zz_126[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_127 = 1'b0; - if(_zz_286)begin - if(_zz_287)begin - if(_zz_132)begin - _zz_127 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_288)begin - if(_zz_289)begin - if(_zz_134)begin - _zz_127 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_290)begin - if(_zz_291)begin - if(_zz_136)begin - _zz_127 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_127 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_128 = 1'b0; - if(_zz_286)begin - if(_zz_287)begin - if(_zz_133)begin - _zz_128 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_288)begin - if(_zz_289)begin - if(_zz_135)begin - _zz_128 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_290)begin - if(_zz_291)begin - if(_zz_137)begin - _zz_128 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_128 = 1'b0; - end - end - - assign _zz_132 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_133 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_134 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_135 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_136 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_137 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_138 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_138 == 3'b000)) begin - _zz_139 = execute_BranchPlugin_eq; - end else if((_zz_138 == 3'b001)) begin - _zz_139 = (! execute_BranchPlugin_eq); - end else if((((_zz_138 & 3'b101) == 3'b101))) begin - _zz_139 = (! execute_SRC_LESS); - end else begin - _zz_139 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_140 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_140 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_140 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_140 = _zz_139; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_141 = _zz_393[11]; - always @ (*) begin - _zz_142[19] = _zz_141; - _zz_142[18] = _zz_141; - _zz_142[17] = _zz_141; - _zz_142[16] = _zz_141; - _zz_142[15] = _zz_141; - _zz_142[14] = _zz_141; - _zz_142[13] = _zz_141; - _zz_142[12] = _zz_141; - _zz_142[11] = _zz_141; - _zz_142[10] = _zz_141; - _zz_142[9] = _zz_141; - _zz_142[8] = _zz_141; - _zz_142[7] = _zz_141; - _zz_142[6] = _zz_141; - _zz_142[5] = _zz_141; - _zz_142[4] = _zz_141; - _zz_142[3] = _zz_141; - _zz_142[2] = _zz_141; - _zz_142[1] = _zz_141; - _zz_142[0] = _zz_141; - end - - assign _zz_143 = _zz_394[19]; - always @ (*) begin - _zz_144[10] = _zz_143; - _zz_144[9] = _zz_143; - _zz_144[8] = _zz_143; - _zz_144[7] = _zz_143; - _zz_144[6] = _zz_143; - _zz_144[5] = _zz_143; - _zz_144[4] = _zz_143; - _zz_144[3] = _zz_143; - _zz_144[2] = _zz_143; - _zz_144[1] = _zz_143; - _zz_144[0] = _zz_143; - end - - assign _zz_145 = _zz_395[11]; - always @ (*) begin - _zz_146[18] = _zz_145; - _zz_146[17] = _zz_145; - _zz_146[16] = _zz_145; - _zz_146[15] = _zz_145; - _zz_146[14] = _zz_145; - _zz_146[13] = _zz_145; - _zz_146[12] = _zz_145; - _zz_146[11] = _zz_145; - _zz_146[10] = _zz_145; - _zz_146[9] = _zz_145; - _zz_146[8] = _zz_145; - _zz_146[7] = _zz_145; - _zz_146[6] = _zz_145; - _zz_146[5] = _zz_145; - _zz_146[4] = _zz_145; - _zz_146[3] = _zz_145; - _zz_146[2] = _zz_145; - _zz_146[1] = _zz_145; - _zz_146[0] = _zz_145; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_147 = (_zz_396[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_147 = _zz_397[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_147 = _zz_398[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_147); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -4991,80 +5105,80 @@ module VexRiscv ( endcase end - assign _zz_148 = _zz_399[11]; - always @ (*) begin - _zz_149[19] = _zz_148; - _zz_149[18] = _zz_148; - _zz_149[17] = _zz_148; - _zz_149[16] = _zz_148; - _zz_149[15] = _zz_148; - _zz_149[14] = _zz_148; - _zz_149[13] = _zz_148; - _zz_149[12] = _zz_148; - _zz_149[11] = _zz_148; - _zz_149[10] = _zz_148; - _zz_149[9] = _zz_148; - _zz_149[8] = _zz_148; - _zz_149[7] = _zz_148; - _zz_149[6] = _zz_148; - _zz_149[5] = _zz_148; - _zz_149[4] = _zz_148; - _zz_149[3] = _zz_148; - _zz_149[2] = _zz_148; - _zz_149[1] = _zz_148; - _zz_149[0] = _zz_148; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_149,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_151,{{{_zz_698,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_153,{{{_zz_699,_zz_700},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_402}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_150 = _zz_400[19]; - always @ (*) begin - _zz_151[10] = _zz_150; - _zz_151[9] = _zz_150; - _zz_151[8] = _zz_150; - _zz_151[7] = _zz_150; - _zz_151[6] = _zz_150; - _zz_151[5] = _zz_150; - _zz_151[4] = _zz_150; - _zz_151[3] = _zz_150; - _zz_151[2] = _zz_150; - _zz_151[1] = _zz_150; - _zz_151[0] = _zz_150; - end - - assign _zz_152 = _zz_401[11]; - always @ (*) begin - _zz_153[18] = _zz_152; - _zz_153[17] = _zz_152; - _zz_153[16] = _zz_152; - _zz_153[15] = _zz_152; - _zz_153[14] = _zz_152; - _zz_153[13] = _zz_152; - _zz_153[12] = _zz_152; - _zz_153[11] = _zz_152; - _zz_153[10] = _zz_152; - _zz_153[9] = _zz_152; - _zz_153[8] = _zz_152; - _zz_153[7] = _zz_152; - _zz_153[6] = _zz_152; - _zz_153[5] = _zz_152; - _zz_153[4] = _zz_152; - _zz_153[3] = _zz_152; - _zz_153[2] = _zz_152; - _zz_153[1] = _zz_152; - _zz_153[0] = _zz_152; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -5074,9 +5188,9 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin - CsrPlugin_privilege = _zz_154; - if(CsrPlugin_forceMachineWire)begin + always @(*) begin + CsrPlugin_privilege = _zz_CsrPlugin_privilege; + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end @@ -5084,82 +5198,93 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0; assign CsrPlugin_sip_SEIP_OR = (CsrPlugin_sip_SEIP_SOFT || CsrPlugin_sip_SEIP_INPUT); - always @ (*) begin + always @(*) begin CsrPlugin_redoInterface_valid = 1'b0; - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeInstruction)begin - CsrPlugin_redoInterface_valid = 1'b1; - end + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin + CsrPlugin_redoInterface_valid = 1'b1; end end assign CsrPlugin_redoInterface_payload = decode_PC; - assign _zz_155 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); - assign _zz_156 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); - assign _zz_157 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); - assign _zz_158 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_159 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_160 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - always @ (*) begin + always @(*) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b0; + if(when_CsrPlugin_l803) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b1; + end + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeInstruction) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b1; + end + end + end + + assign when_CsrPlugin_l803 = (execute_arbitration_isValid && execute_IS_SFENCE_VMA); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_when_CsrPlugin_l952_3 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_4 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_5 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) 4'b0000 : begin - if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin + if(when_CsrPlugin_l866) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0001 : begin - if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_1) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0010 : begin - if(((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)))begin + if(when_CsrPlugin_l866_2) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0100 : begin - if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin + if(when_CsrPlugin_l866_3) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0101 : begin - if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_4) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0110 : begin - if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin + if(when_CsrPlugin_l866_5) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0111 : begin - if(((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_6) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1000 : begin - if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin + if(when_CsrPlugin_l866_7) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1001 : begin - if(((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)))begin + if(when_CsrPlugin_l866_8) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1100 : begin - if(((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_9) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1101 : begin - if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_10) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1111 : begin - if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_11) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end @@ -5168,81 +5293,114 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l866 = ((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)); + assign when_CsrPlugin_l866_1 = ((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)); + assign when_CsrPlugin_l866_2 = ((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)); + assign when_CsrPlugin_l866_3 = ((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)); + assign when_CsrPlugin_l866_4 = ((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)); + assign when_CsrPlugin_l866_5 = ((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)); + assign when_CsrPlugin_l866_6 = ((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)); + assign when_CsrPlugin_l866_7 = ((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)); + assign when_CsrPlugin_l866_8 = ((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)); + assign when_CsrPlugin_l866_9 = ((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)); + assign when_CsrPlugin_l866_10 = ((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)); + assign when_CsrPlugin_l866_11 = ((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_161 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_162 = _zz_403[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_275)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign when_CsrPlugin_l946_1 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign when_CsrPlugin_l952_3 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign when_CsrPlugin_l952_4 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign when_CsrPlugin_l952_5 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign when_CsrPlugin_l952_6 = ((_zz_when_CsrPlugin_l952_3 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_7 = ((_zz_when_CsrPlugin_l952_4 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_8 = ((_zz_when_CsrPlugin_l952_5 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin @@ -5256,8 +5414,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_base = CsrPlugin_stvec_base; @@ -5270,151 +5428,160 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_256)begin + if(execute_CsrPlugin_csr_256) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_csr_384) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_770)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_770) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_771)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_771) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_324)begin + if(execute_CsrPlugin_csr_324) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_260)begin + if(execute_CsrPlugin_csr_260) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_261)begin + if(execute_CsrPlugin_csr_261) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_321)begin + if(execute_CsrPlugin_csr_321) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_320)begin + if(execute_CsrPlugin_csr_320) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_322)begin + if(execute_CsrPlugin_csr_322) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_323)begin + if(execute_CsrPlugin_csr_323) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2496)begin + if(execute_CsrPlugin_csr_2496) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3520)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3520) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_292)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_293)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_294)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_293)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_294)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -5430,48 +5597,58 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_292)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_292)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - always @ (*) begin - execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - if(execute_CsrPlugin_csr_836)begin + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + always @(*) begin + execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; end - if(execute_CsrPlugin_csr_324)begin + if(execute_CsrPlugin_csr_324) begin execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; end end - always @ (*) begin - case(_zz_321) + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || execute_IS_SFENCE_VMA)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_295) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -5484,8 +5661,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_295) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -5504,81 +5681,160 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_405) + $signed(_zz_406)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_270)begin - if(_zz_296)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_297)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_410); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_163 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_163[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_411); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_412 : _zz_413); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_414[31:0]; - assign _zz_164 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_165 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_166 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_167[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_167[31 : 0] = execute_RS1; - end - - assign _zz_169 = (_zz_168 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_169 != 32'h0); - assign _zz_171 = (_zz_170 & externalInterruptArray_regNext); - assign externalInterruptS = (_zz_171 != 32'h0); - assign _zz_26 = decode_SRC1_CTRL; - assign _zz_24 = _zz_49; - assign _zz_37 = decode_to_execute_SRC1_CTRL; - assign _zz_23 = decode_ALU_CTRL; - assign _zz_21 = _zz_48; - assign _zz_38 = decode_to_execute_ALU_CTRL; - assign _zz_20 = decode_SRC2_CTRL; - assign _zz_18 = _zz_47; - assign _zz_36 = decode_to_execute_SRC2_CTRL; - assign _zz_17 = decode_ALU_BITWISE_CTRL; - assign _zz_15 = _zz_46; - assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_14 = decode_SHIFT_CTRL; - assign _zz_11 = execute_SHIFT_CTRL; - assign _zz_12 = _zz_45; - assign _zz_34 = decode_to_execute_SHIFT_CTRL; - assign _zz_33 = execute_to_memory_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_52 = _zz_44; - assign _zz_30 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_43; - assign _zz_28 = decode_to_execute_ENV_CTRL; - assign _zz_27 = execute_to_memory_ENV_CTRL; - assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign _zz_CsrPlugin_csrMapping_readDataInit_3 = (_zz_CsrPlugin_csrMapping_readDataInit_2 & externalInterruptArray_regNext); + assign externalInterruptS = (_zz_CsrPlugin_csrMapping_readDataInit_3 != 32'h0); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_28 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_36 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_38 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_41 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_64 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_65 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_66 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_67 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_68 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_69 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -5599,267 +5855,304 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_172 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_172[12 : 0] = 13'h1000; - _zz_172[25 : 20] = 6'h20; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_4[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_173 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_173[19 : 19] = MmuPlugin_status_mxr; - _zz_173[18 : 18] = MmuPlugin_status_sum; - _zz_173[17 : 17] = MmuPlugin_status_mprv; - _zz_173[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_173[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_173[3 : 3] = CsrPlugin_mstatus_MIE; - _zz_173[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_173[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_173[1 : 1] = CsrPlugin_sstatus_SIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[19 : 19] = MmuPlugin_status_mxr; + _zz_CsrPlugin_csrMapping_readDataInit_5[18 : 18] = MmuPlugin_status_sum; + _zz_CsrPlugin_csrMapping_readDataInit_5[17 : 17] = MmuPlugin_status_mprv; + _zz_CsrPlugin_csrMapping_readDataInit_5[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_5[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[1 : 1] = CsrPlugin_sstatus_SIE; end end - always @ (*) begin - _zz_174 = 32'h0; - if(execute_CsrPlugin_csr_256)begin - _zz_174[19 : 19] = MmuPlugin_status_mxr; - _zz_174[18 : 18] = MmuPlugin_status_sum; - _zz_174[17 : 17] = MmuPlugin_status_mprv; - _zz_174[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_174[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_174[1 : 1] = CsrPlugin_sstatus_SIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_256) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[19 : 19] = MmuPlugin_status_mxr; + _zz_CsrPlugin_csrMapping_readDataInit_6[18 : 18] = MmuPlugin_status_sum; + _zz_CsrPlugin_csrMapping_readDataInit_6[17 : 17] = MmuPlugin_status_mprv; + _zz_CsrPlugin_csrMapping_readDataInit_6[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_CsrPlugin_csrMapping_readDataInit_6[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_CsrPlugin_csrMapping_readDataInit_6[1 : 1] = CsrPlugin_sstatus_SIE; end end - always @ (*) begin - _zz_175 = 32'h0; - if(execute_CsrPlugin_csr_384)begin - _zz_175[31 : 31] = MmuPlugin_satp_mode; - _zz_175[30 : 22] = MmuPlugin_satp_asid; - _zz_175[19 : 0] = MmuPlugin_satp_ppn; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_384) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 31] = MmuPlugin_satp_mode; + _zz_CsrPlugin_csrMapping_readDataInit_7[30 : 22] = MmuPlugin_satp_asid; + _zz_CsrPlugin_csrMapping_readDataInit_7[19 : 0] = MmuPlugin_satp_ppn; end end - always @ (*) begin - _zz_176 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_176[0 : 0] = 1'b1; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[0 : 0] = 1'b1; end end - always @ (*) begin - _zz_177 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_177[1 : 0] = 2'b10; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[1 : 0] = 2'b10; end end - always @ (*) begin - _zz_178 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_178[1 : 0] = 2'b11; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = 2'b11; end end - always @ (*) begin - _zz_179 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_179[11 : 11] = CsrPlugin_mip_MEIP; - _zz_179[7 : 7] = CsrPlugin_mip_MTIP; - _zz_179[3 : 3] = CsrPlugin_mip_MSIP; - _zz_179[5 : 5] = CsrPlugin_sip_STIP; - _zz_179[1 : 1] = CsrPlugin_sip_SSIP; - _zz_179[9 : 9] = CsrPlugin_sip_SEIP_OR; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 3] = CsrPlugin_mip_MSIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[5 : 5] = CsrPlugin_sip_STIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[1 : 1] = CsrPlugin_sip_SSIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[9 : 9] = CsrPlugin_sip_SEIP_OR; end end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_180[11 : 11] = CsrPlugin_mie_MEIE; - _zz_180[7 : 7] = CsrPlugin_mie_MTIE; - _zz_180[3 : 3] = CsrPlugin_mie_MSIE; - _zz_180[9 : 9] = CsrPlugin_sie_SEIE; - _zz_180[5 : 5] = CsrPlugin_sie_STIE; - _zz_180[1 : 1] = CsrPlugin_sie_SSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[3 : 3] = CsrPlugin_mie_MSIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[9 : 9] = CsrPlugin_sie_SEIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[5 : 5] = CsrPlugin_sie_STIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[1 : 1] = CsrPlugin_sie_SSIE; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_181[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_182[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_183[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_183[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_184[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_324)begin - _zz_185[5 : 5] = CsrPlugin_sip_STIP; - _zz_185[1 : 1] = CsrPlugin_sip_SSIP; - _zz_185[9 : 9] = CsrPlugin_sip_SEIP_OR; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_324) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[5 : 5] = CsrPlugin_sip_STIP; + _zz_CsrPlugin_csrMapping_readDataInit_17[1 : 1] = CsrPlugin_sip_SSIP; + _zz_CsrPlugin_csrMapping_readDataInit_17[9 : 9] = CsrPlugin_sip_SEIP_OR; end end - always @ (*) begin - _zz_186 = 32'h0; - if(execute_CsrPlugin_csr_260)begin - _zz_186[9 : 9] = CsrPlugin_sie_SEIE; - _zz_186[5 : 5] = CsrPlugin_sie_STIE; - _zz_186[1 : 1] = CsrPlugin_sie_SSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_260) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[9 : 9] = CsrPlugin_sie_SEIE; + _zz_CsrPlugin_csrMapping_readDataInit_18[5 : 5] = CsrPlugin_sie_STIE; + _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 1] = CsrPlugin_sie_SSIE; end end - always @ (*) begin - _zz_187 = 32'h0; - if(execute_CsrPlugin_csr_261)begin - _zz_187[31 : 2] = CsrPlugin_stvec_base; - _zz_187[1 : 0] = CsrPlugin_stvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_261) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 2] = CsrPlugin_stvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_19[1 : 0] = CsrPlugin_stvec_mode; end end - always @ (*) begin - _zz_188 = 32'h0; - if(execute_CsrPlugin_csr_321)begin - _zz_188[31 : 0] = CsrPlugin_sepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_321) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_sepc; end end - always @ (*) begin - _zz_189 = 32'h0; - if(execute_CsrPlugin_csr_320)begin - _zz_189[31 : 0] = CsrPlugin_sscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_320) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_sscratch; end end - always @ (*) begin - _zz_190 = 32'h0; - if(execute_CsrPlugin_csr_322)begin - _zz_190[31 : 31] = CsrPlugin_scause_interrupt; - _zz_190[3 : 0] = CsrPlugin_scause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_322) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 31] = CsrPlugin_scause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_22[3 : 0] = CsrPlugin_scause_exceptionCode; end end - always @ (*) begin - _zz_191 = 32'h0; - if(execute_CsrPlugin_csr_323)begin - _zz_191[31 : 0] = CsrPlugin_stval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_323) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_stval; end end - always @ (*) begin - _zz_192 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_192[31 : 0] = _zz_168; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_193 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_193[31 : 0] = _zz_169; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - always @ (*) begin - _zz_194 = 32'h0; - if(execute_CsrPlugin_csr_2496)begin - _zz_194[31 : 0] = _zz_170; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + if(execute_CsrPlugin_csr_2496) begin + _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; end end - always @ (*) begin - _zz_195 = 32'h0; - if(execute_CsrPlugin_csr_3520)begin - _zz_195[31 : 0] = _zz_171; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + if(execute_CsrPlugin_csr_3520) begin + _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; end end - assign execute_CsrPlugin_readData = (((((_zz_172 | _zz_173) | (_zz_174 | _zz_175)) | ((_zz_176 | _zz_177) | (_zz_178 | _zz_701))) | (((_zz_179 | _zz_180) | (_zz_181 | _zz_182)) | ((_zz_183 | _zz_184) | (_zz_185 | _zz_186)))) | ((((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194))) | _zz_195)); - assign iBusWishbone_ADR = {_zz_469,_zz_196}; - assign iBusWishbone_CTI = ((_zz_196 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5) | (_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7)) | ((_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9) | (_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_28))) | (((_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12) | (_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14)) | ((_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16) | (_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20) | (_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22)) | ((_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24) | (_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26))) | _zz_CsrPlugin_csrMapping_readDataInit_27)); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_298)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_298)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_197; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_203 = (dBus_cmd_payload_length != 3'b000); - assign _zz_199 = dBus_cmd_valid; - assign _zz_201 = dBus_cmd_payload_wr; - assign _zz_202 = (_zz_198 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_200 && (_zz_201 || _zz_202)); - assign dBusWishbone_ADR = ((_zz_203 ? {{dBus_cmd_payload_address[31 : 5],_zz_198},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_203 ? (_zz_202 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_201 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_201; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_200 = (_zz_199 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_199; - assign dBusWishbone_STB = _zz_199; - assign dBus_rsp_valid = _zz_204; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_67 <= 1'b0; - _zz_69 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_82; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_83; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; MmuPlugin_status_sum <= 1'b0; MmuPlugin_status_mxr <= 1'b0; @@ -5875,11 +6168,11 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; MmuPlugin_ports_1_entryToReplace_value <= 2'b00; - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_IDLE; MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; - _zz_117 <= 1'b1; - _zz_129 <= 1'b0; - _zz_154 <= 2'b11; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_CsrPlugin_privilege <= 2'b11; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -5922,204 +6215,204 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_168 <= 32'h0; - _zz_170 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_2 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_IS_DBUS_SHARING <= 1'b0; memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; - _zz_196 <= 3'b000; - _zz_197 <= 1'b0; - _zz_198 <= 3'b000; - _zz_204 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_67 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_65)begin - _zz_67 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_69 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_69 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_299)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; - if(contextSwitching)begin - if(MmuPlugin_ports_0_cache_0_exception)begin + if(contextSwitching) begin + if(MmuPlugin_ports_0_cache_0_exception) begin MmuPlugin_ports_0_cache_0_valid <= 1'b0; end - if(MmuPlugin_ports_0_cache_1_exception)begin + if(MmuPlugin_ports_0_cache_1_exception) begin MmuPlugin_ports_0_cache_1_valid <= 1'b0; end - if(MmuPlugin_ports_0_cache_2_exception)begin + if(MmuPlugin_ports_0_cache_2_exception) begin MmuPlugin_ports_0_cache_2_valid <= 1'b0; end - if(MmuPlugin_ports_0_cache_3_exception)begin + if(MmuPlugin_ports_0_cache_3_exception) begin MmuPlugin_ports_0_cache_3_valid <= 1'b0; end end MmuPlugin_ports_1_entryToReplace_value <= MmuPlugin_ports_1_entryToReplace_valueNext; - if(contextSwitching)begin - if(MmuPlugin_ports_1_cache_0_exception)begin + if(contextSwitching) begin + if(MmuPlugin_ports_1_cache_0_exception) begin MmuPlugin_ports_1_cache_0_valid <= 1'b0; end - if(MmuPlugin_ports_1_cache_1_exception)begin + if(MmuPlugin_ports_1_cache_1_exception) begin MmuPlugin_ports_1_cache_1_valid <= 1'b0; end - if(MmuPlugin_ports_1_cache_2_exception)begin + if(MmuPlugin_ports_1_cache_2_exception) begin MmuPlugin_ports_1_cache_2_valid <= 1'b0; end - if(MmuPlugin_ports_1_cache_3_exception)begin + if(MmuPlugin_ports_1_cache_3_exception) begin MmuPlugin_ports_1_cache_3_valid <= 1'b0; end end MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_300)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + `MmuPlugin_shared_State_binary_sequential_IDLE : begin + if(when_MmuPlugin_l217) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L1_CMD; end end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin - if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L1_RSP; end end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin - if(MmuPlugin_shared_dBusRspStaged_valid)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; - if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin + if(MmuPlugin_shared_dBusRspStaged_valid) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L0_CMD; + if(when_MmuPlugin_l243) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_IDLE; end - if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + if(MmuPlugin_shared_dBusRspStaged_payload_redo) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L1_CMD; end end end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin - if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L0_RSP; end end default : begin - if(MmuPlugin_shared_dBusRspStaged_valid)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; - if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if(MmuPlugin_shared_dBusRspStaged_valid) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_IDLE; + if(MmuPlugin_shared_dBusRspStaged_payload_redo) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L0_CMD; end end end endcase - if(_zz_283)begin - if(_zz_284)begin - if(_zz_301)begin + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin + if(when_MmuPlugin_l280) begin MmuPlugin_ports_0_cache_0_valid <= 1'b1; end - if(_zz_302)begin + if(when_MmuPlugin_l280_1) begin MmuPlugin_ports_0_cache_1_valid <= 1'b1; end - if(_zz_303)begin + if(when_MmuPlugin_l280_2) begin MmuPlugin_ports_0_cache_2_valid <= 1'b1; end - if(_zz_304)begin + if(when_MmuPlugin_l280_3) begin MmuPlugin_ports_0_cache_3_valid <= 1'b1; end end - if(_zz_285)begin - if(_zz_305)begin + if(when_MmuPlugin_l274_1) begin + if(when_MmuPlugin_l280_4) begin MmuPlugin_ports_1_cache_0_valid <= 1'b1; end - if(_zz_306)begin + if(when_MmuPlugin_l280_5) begin MmuPlugin_ports_1_cache_1_valid <= 1'b1; end - if(_zz_307)begin + if(when_MmuPlugin_l280_6) begin MmuPlugin_ports_1_cache_2_valid <= 1'b1; end - if(_zz_308)begin + if(when_MmuPlugin_l280_7) begin MmuPlugin_ports_1_cache_3_valid <= 1'b1; end end end - if((writeBack_arbitration_isValid && writeBack_IS_SFENCE_VMA))begin + if(when_MmuPlugin_l304) begin MmuPlugin_ports_0_cache_0_valid <= 1'b0; MmuPlugin_ports_0_cache_1_valid <= 1'b0; MmuPlugin_ports_0_cache_2_valid <= 1'b0; @@ -6129,83 +6422,83 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - _zz_117 <= 1'b0; - _zz_129 <= (_zz_41 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_309)begin - if(_zz_310)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_311)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_312)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(_zz_313)begin - if(_zz_314)begin + if(when_CsrPlugin_l946_1) begin + if(when_CsrPlugin_l952_3) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_315)begin + if(when_CsrPlugin_l952_4) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_316)begin + if(when_CsrPlugin_l952_5) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_317)begin + if(when_CsrPlugin_l952_6) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_318)begin + if(when_CsrPlugin_l952_7) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_319)begin + if(when_CsrPlugin_l952_8) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_277)begin - _zz_154 <= CsrPlugin_targetPrivilege; + if(when_CsrPlugin_l1019) begin + _zz_CsrPlugin_privilege <= CsrPlugin_targetPrivilege; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_sstatus_SIE <= 1'b0; @@ -6221,78 +6514,82 @@ module VexRiscv ( end endcase end - if(_zz_278)begin - case(_zz_279) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; - _zz_154 <= CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_privilege <= CsrPlugin_mstatus_MPP; end 2'b01 : begin CsrPlugin_sstatus_SPP <= 1'b0; CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; CsrPlugin_sstatus_SPIE <= 1'b1; - _zz_154 <= {1'b0,CsrPlugin_sstatus_SPP}; + _zz_CsrPlugin_privilege <= {1'b0,CsrPlugin_sstatus_SPP}; end default : begin end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_160,{_zz_159,{_zz_158,{_zz_157,{_zz_156,_zz_155}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_5,{_zz_when_CsrPlugin_l952_4,{_zz_when_CsrPlugin_l952_3,{_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(MmuPlugin_dBusAccess_rsp_valid)begin + if(MmuPlugin_dBusAccess_rsp_valid) begin + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end + if(MmuPlugin_dBusAccess_rsp_valid) begin memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_424[0]; - MmuPlugin_status_sum <= _zz_425[0]; - MmuPlugin_status_mprv <= _zz_426[0]; - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_427[0]; - CsrPlugin_mstatus_MIE <= _zz_428[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_429[0]; - CsrPlugin_sstatus_SIE <= _zz_430[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_status_mxr <= CsrPlugin_csrMapping_writeDataSignal[19]; + MmuPlugin_status_sum <= CsrPlugin_csrMapping_writeDataSignal[18]; + MmuPlugin_status_mprv <= CsrPlugin_csrMapping_writeDataSignal[17]; + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + CsrPlugin_sstatus_SPP <= CsrPlugin_csrMapping_writeDataSignal[8 : 8]; + CsrPlugin_sstatus_SPIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sstatus_SIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_256)begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_431[0]; - MmuPlugin_status_sum <= _zz_432[0]; - MmuPlugin_status_mprv <= _zz_433[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_434[0]; - CsrPlugin_sstatus_SIE <= _zz_435[0]; + if(execute_CsrPlugin_csr_256) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_status_mxr <= CsrPlugin_csrMapping_writeDataSignal[19]; + MmuPlugin_status_sum <= CsrPlugin_csrMapping_writeDataSignal[18]; + MmuPlugin_status_mprv <= CsrPlugin_csrMapping_writeDataSignal[17]; + CsrPlugin_sstatus_SPP <= CsrPlugin_csrMapping_writeDataSignal[8 : 8]; + CsrPlugin_sstatus_SPIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sstatus_SIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeInstruction)begin + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_satp_mode <= CsrPlugin_csrMapping_writeDataSignal[31]; MmuPlugin_ports_0_cache_0_valid <= 1'b0; MmuPlugin_ports_0_cache_1_valid <= 1'b0; MmuPlugin_ports_0_cache_2_valid <= 1'b0; @@ -6302,122 +6599,119 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_mode <= _zz_436[0]; - end end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_438[0]; - CsrPlugin_sip_SSIP <= _zz_439[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_440[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sip_STIP <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sip_SSIP <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_sip_SEIP_SOFT <= CsrPlugin_csrMapping_writeDataSignal[9]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_441[0]; - CsrPlugin_mie_MTIE <= _zz_442[0]; - CsrPlugin_mie_MSIE <= _zz_443[0]; - CsrPlugin_sie_SEIE <= _zz_444[0]; - CsrPlugin_sie_STIE <= _zz_445[0]; - CsrPlugin_sie_SSIE <= _zz_446[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + CsrPlugin_sie_SEIE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_sie_STIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sie_SSIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_770)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_medeleg_IAM <= _zz_447[0]; - CsrPlugin_medeleg_IAF <= _zz_448[0]; - CsrPlugin_medeleg_II <= _zz_449[0]; - CsrPlugin_medeleg_LAM <= _zz_450[0]; - CsrPlugin_medeleg_LAF <= _zz_451[0]; - CsrPlugin_medeleg_SAM <= _zz_452[0]; - CsrPlugin_medeleg_SAF <= _zz_453[0]; - CsrPlugin_medeleg_EU <= _zz_454[0]; - CsrPlugin_medeleg_ES <= _zz_455[0]; - CsrPlugin_medeleg_IPF <= _zz_456[0]; - CsrPlugin_medeleg_LPF <= _zz_457[0]; - CsrPlugin_medeleg_SPF <= _zz_458[0]; + if(execute_CsrPlugin_csr_770) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_medeleg_IAM <= CsrPlugin_csrMapping_writeDataSignal[0]; + CsrPlugin_medeleg_IAF <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_medeleg_II <= CsrPlugin_csrMapping_writeDataSignal[2]; + CsrPlugin_medeleg_LAM <= CsrPlugin_csrMapping_writeDataSignal[4]; + CsrPlugin_medeleg_LAF <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_medeleg_SAM <= CsrPlugin_csrMapping_writeDataSignal[6]; + CsrPlugin_medeleg_SAF <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_medeleg_EU <= CsrPlugin_csrMapping_writeDataSignal[8]; + CsrPlugin_medeleg_ES <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_medeleg_IPF <= CsrPlugin_csrMapping_writeDataSignal[12]; + CsrPlugin_medeleg_LPF <= CsrPlugin_csrMapping_writeDataSignal[13]; + CsrPlugin_medeleg_SPF <= CsrPlugin_csrMapping_writeDataSignal[15]; end end - if(execute_CsrPlugin_csr_771)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mideleg_SE <= _zz_459[0]; - CsrPlugin_mideleg_ST <= _zz_460[0]; - CsrPlugin_mideleg_SS <= _zz_461[0]; + if(execute_CsrPlugin_csr_771) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mideleg_SE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_mideleg_ST <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_mideleg_SS <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_324)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_462[0]; - CsrPlugin_sip_SSIP <= _zz_463[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_464[0]; + if(execute_CsrPlugin_csr_324) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sip_STIP <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sip_SSIP <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_sip_SEIP_SOFT <= CsrPlugin_csrMapping_writeDataSignal[9]; end end - if(execute_CsrPlugin_csr_260)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sie_SEIE <= _zz_465[0]; - CsrPlugin_sie_STIE <= _zz_466[0]; - CsrPlugin_sie_SSIE <= _zz_467[0]; + if(execute_CsrPlugin_csr_260) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sie_SEIE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_sie_STIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sie_SSIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_168 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2496)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_170 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2496) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_298)begin - if(iBusWishbone_ACK)begin - _zz_196 <= (_zz_196 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_197 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_199 && _zz_200))begin - _zz_198 <= (_zz_198 + 3'b001); - if(_zz_202)begin - _zz_198 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_204 <= ((_zz_199 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_70 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_299)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; - if((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)))begin + if(when_MmuPlugin_l205) begin MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; @@ -6431,26 +6725,26 @@ module VexRiscv ( MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; end case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_300)begin + `MmuPlugin_shared_State_binary_sequential_IDLE : begin + if(when_MmuPlugin_l217) begin MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; - MmuPlugin_shared_vpn_1 <= _zz_102[31 : 22]; - MmuPlugin_shared_vpn_0 <= _zz_102[21 : 12]; + MmuPlugin_shared_vpn_1 <= _zz_MmuPlugin_shared_vpn_0[31 : 22]; + MmuPlugin_shared_vpn_0 <= _zz_MmuPlugin_shared_vpn_0[21 : 12]; end end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin end default : begin end endcase - if(_zz_283)begin - if(_zz_284)begin - if(_zz_301)begin - MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin + if(when_MmuPlugin_l280) begin + MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6459,10 +6753,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_302)begin - MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_1) begin + MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6471,10 +6765,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_303)begin - MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_2) begin + MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6483,10 +6777,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_304)begin - MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_3) begin + MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6495,12 +6789,12 @@ module VexRiscv ( MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end end - if(_zz_285)begin - if(_zz_305)begin - MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l274_1) begin + if(when_MmuPlugin_l280_4) begin + MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6509,10 +6803,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_306)begin - MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_5) begin + MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6521,10 +6815,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_307)begin - MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_6) begin + MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6533,10 +6827,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_308)begin - MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_7) begin + MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6545,83 +6839,83 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end end end - _zz_130 <= _zz_40[11 : 7]; - _zz_131 <= _zz_50; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_sip_SEIP_INPUT <= externalInterruptS; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_275)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_162 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_162 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_309)begin - if(_zz_310)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_311)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_312)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end end - if(_zz_313)begin - if(_zz_314)begin + if(when_CsrPlugin_l946_1) begin + if(when_CsrPlugin_l952_3) begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_315)begin + if(when_CsrPlugin_l952_4) begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_316)begin + if(when_CsrPlugin_l952_5) begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_317)begin + if(when_CsrPlugin_l952_6) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_318)begin + if(when_CsrPlugin_l952_7) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_319)begin + if(when_CsrPlugin_l952_8) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_277)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_sepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -6629,7 +6923,7 @@ module VexRiscv ( CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -6637,365 +6931,368 @@ module VexRiscv ( end endcase end - if((memory_DivPlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_DivPlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_270)begin - if(_zz_296)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_415[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; end end end - if(_zz_297)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_166 ? (~ _zz_167) : _zz_167) + _zz_421); - memory_DivPlugin_rs2 <= ((_zz_165 ? (~ execute_RS2) : execute_RS2) + _zz_423); - memory_DivPlugin_div_needRevert <= ((_zz_166 ^ (_zz_165 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_35; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_55; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_53; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_54; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_25; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_22; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_19; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin + execute_to_memory_MEMORY_LRSC <= execute_MEMORY_LRSC; + end + if(when_Pipeline_l124_28) begin + memory_to_writeBack_MEMORY_LRSC <= memory_MEMORY_LRSC; + end + if(when_Pipeline_l124_29) begin decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_30) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + if(when_Pipeline_l124_31) begin + decode_to_execute_IS_SFENCE_VMA2 <= decode_IS_SFENCE_VMA2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + if(when_Pipeline_l124_32) begin + decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_33) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + if(when_Pipeline_l124_34) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_35) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_10; + if(when_Pipeline_l124_36) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + if(when_Pipeline_l124_37) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_39) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_40) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_41) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_52) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_53) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_54) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_55) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_56) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + if(when_Pipeline_l124_59) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + if(when_Pipeline_l124_60) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_62) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_63) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_64) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_65) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_66) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_67) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_68) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_69) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_770 <= (decode_INSTRUCTION[31 : 20] == 12'h302); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_771 <= (decode_INSTRUCTION[31 : 20] == 12'h303); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_324 <= (decode_INSTRUCTION[31 : 20] == 12'h144); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_260 <= (decode_INSTRUCTION[31 : 20] == 12'h104); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_261 <= (decode_INSTRUCTION[31 : 20] == 12'h105); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_321 <= (decode_INSTRUCTION[31 : 20] == 12'h141); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_320 <= (decode_INSTRUCTION[31 : 20] == 12'h140); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin execute_CsrPlugin_csr_322 <= (decode_INSTRUCTION[31 : 20] == 12'h142); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_323 <= (decode_INSTRUCTION[31 : 20] == 12'h143); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_24) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_25) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_26) begin execute_CsrPlugin_csr_2496 <= (decode_INSTRUCTION[31 : 20] == 12'h9c0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_27) begin execute_CsrPlugin_csr_3520 <= (decode_INSTRUCTION[31 : 20] == 12'hdc0); end - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_asid <= execute_CsrPlugin_writeData[30 : 22]; - MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_satp_asid <= CsrPlugin_csrMapping_writeDataSignal[30 : 22]; + MmuPlugin_satp_ppn <= CsrPlugin_csrMapping_writeDataSignal[19 : 0]; end end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_437[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_261)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_261) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_stvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_stvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_321)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_321) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_320)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_320) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_322)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_scause_interrupt <= _zz_468[0]; - CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_322) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_scause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_scause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_323)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_323) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_stval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -7008,9 +7305,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_isLrsc, input io_cpu_execute_args_isAmo, @@ -7044,6 +7340,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -7059,9 +7356,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -7069,7 +7367,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -7078,38 +7376,23 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire _zz_19; - wire _zz_20; - wire _zz_21; - wire _zz_22; - wire [2:0] _zz_23; - wire [0:0] _zz_24; - wire [0:0] _zz_25; - wire [9:0] _zz_26; - wire [9:0] _zz_27; - wire [31:0] _zz_28; - wire [31:0] _zz_29; - wire [31:0] _zz_30; - wire [31:0] _zz_31; - wire [1:0] _zz_32; - wire [31:0] _zz_33; - wire [1:0] _zz_34; - wire [1:0] _zz_35; - wire [0:0] _zz_36; - wire [0:0] _zz_37; - wire [0:0] _zz_38; - wire [2:0] _zz_39; - wire [1:0] _zz_40; - wire [21:0] _zz_41; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [31:0] _zz_stageB_amo_addSub; + wire [31:0] _zz_stageB_amo_addSub_1; + wire [31:0] _zz_stageB_amo_addSub_2; + wire [31:0] _zz_stageB_amo_addSub_3; + wire [31:0] _zz_stageB_amo_addSub_4; + wire [1:0] _zz_stageB_amo_addSub_5; + wire [1:0] _zz_stageB_amo_addSub_6; + wire [1:0] _zz_stageB_amo_addSub_7; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -7134,38 +7417,45 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_isLrsc; reg stageA_request_isAmo; reg stageA_request_amoCtrl_swap; reg [2:0] stageA_request_amoCtrl_alu; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_isLrsc; reg stageB_request_isAmo; @@ -7173,6 +7463,7 @@ module DataCache ( reg [2:0] stageB_request_amoCtrl_alu; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -7190,25 +7481,36 @@ module DataCache ( reg [31:0] stageB_mmuRsp_ways_2_physical; reg stageB_mmuRsp_ways_3_sel; reg [31:0] stageB_mmuRsp_ways_3_physical; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; reg stageB_lrSc_reserved; + wire when_DataCache_l866; wire stageB_isExternalLsrc; wire stageB_isExternalAmo; reg [31:0] stageB_requestDataBypass; @@ -7217,14 +7519,26 @@ module DataCache ( wire [31:0] stageB_amo_addSub; wire stageB_amo_less; wire stageB_amo_selectRf; + wire [2:0] switch_Misc_l200; reg [31:0] stageB_amo_result; reg [31:0] stageB_amo_resultReg; reg stageB_amo_internal_resultRegValid; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l984; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l997; + wire when_DataCache_l1005; + wire when_DataCache_l1010; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -7236,73 +7550,62 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_42; - reg [7:0] _zz_43; - reg [7:0] _zz_44; - reg [7:0] _zz_45; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_15 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); - assign _zz_16 = (! stageB_amo_internal_resultRegValid); - assign _zz_17 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); - assign _zz_18 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_19 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); - assign _zz_20 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); - assign _zz_21 = (! stageB_flusher_hold); - assign _zz_22 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_23 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); - assign _zz_24 = _zz_4[0 : 0]; - assign _zz_25 = _zz_4[1 : 1]; - assign _zz_26 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_27 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_28 = ($signed(_zz_29) + $signed(_zz_33)); - assign _zz_29 = ($signed(_zz_30) + $signed(_zz_31)); - assign _zz_30 = stageB_request_data; - assign _zz_31 = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux); - assign _zz_32 = (stageB_amo_compare ? _zz_34 : _zz_35); - assign _zz_33 = {{30{_zz_32[1]}}, _zz_32}; - assign _zz_34 = 2'b01; - assign _zz_35 = 2'b00; - assign _zz_36 = 1'b1; - assign _zz_37 = (! stageB_lrSc_reserved); - assign _zz_38 = loader_counter_willIncrement; - assign _zz_39 = {2'd0, _zz_38}; - assign _zz_40 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_41 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_stageB_amo_addSub = ($signed(_zz_stageB_amo_addSub_1) + $signed(_zz_stageB_amo_addSub_4)); + assign _zz_stageB_amo_addSub_1 = ($signed(_zz_stageB_amo_addSub_2) + $signed(_zz_stageB_amo_addSub_3)); + assign _zz_stageB_amo_addSub_2 = io_cpu_writeBack_storeData[31 : 0]; + assign _zz_stageB_amo_addSub_3 = (stageB_amo_compare ? (~ stageB_dataMux[31 : 0]) : stageB_dataMux[31 : 0]); + assign _zz_stageB_amo_addSub_5 = (stageB_amo_compare ? _zz_stageB_amo_addSub_6 : _zz_stageB_amo_addSub_7); + assign _zz_stageB_amo_addSub_4 = {{30{_zz_stageB_amo_addSub_5[1]}}, _zz_stageB_amo_addSub_5}; + assign _zz_stageB_amo_addSub_6 = 2'b01; + assign _zz_stageB_amo_addSub_7 = 2'b00; + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_41; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_45, _zz_44, _zz_43, _zz_42}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_42 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_43 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_44 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_45 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -7317,327 +7620,348 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_24[0]; - assign ways_0_tagsReadRsp_error = _zz_25[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - if(stageB_request_isAmo)begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin dataWriteCmd_valid = 1'b0; end end - if(_zz_17)begin + if(when_DataCache_l1010) begin dataWriteCmd_valid = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_36[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_26)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_27)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(! _zz_15) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_14)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end - if(_zz_19)begin + if(when_DataCache_l984) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_15)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end - if(stageB_request_isAmo)begin - if(_zz_16)begin + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin io_cpu_writeBack_haltIt = 1'b1; end end - if(_zz_17)begin + if(when_DataCache_l1010) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); + assign when_DataCache_l866 = ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc); assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - always @ (*) begin - stageB_requestDataBypass = stageB_request_data; - if(stageB_request_isAmo)begin - stageB_requestDataBypass = stageB_amo_resultReg; + always @(*) begin + stageB_requestDataBypass = io_cpu_writeBack_storeData; + if(stageB_request_isAmo) begin + stageB_requestDataBypass[31 : 0] = stageB_amo_resultReg; end end assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == 2'b11); - assign stageB_amo_addSub = _zz_28; - assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31])); + assign stageB_amo_addSub = _zz_stageB_amo_addSub; + assign stageB_amo_less = ((io_cpu_writeBack_storeData[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : io_cpu_writeBack_storeData[31])); assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); - always @ (*) begin - case(_zz_23) + assign switch_Misc_l200 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); + always @(*) begin + case(switch_Misc_l200) 3'b000 : begin stageB_amo_result = stageB_amo_addSub; end 3'b001 : begin - stageB_amo_result = (stageB_request_data ^ stageB_dataMux); + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] ^ stageB_dataMux[31 : 0]); end 3'b010 : begin - stageB_amo_result = (stageB_request_data | stageB_dataMux); + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] | stageB_dataMux[31 : 0]); end 3'b011 : begin - stageB_amo_result = (stageB_request_data & stageB_dataMux); + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] & stageB_dataMux[31 : 0]); end default : begin - stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux); + stageB_amo_result = (stageB_amo_selectRf ? io_cpu_writeBack_storeData[31 : 0] : stageB_dataMux[31 : 0]); end endcase end - always @ (*) begin + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -7645,103 +7969,87 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_request_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - if(_zz_20)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_14)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); - if(_zz_19)begin + if(when_DataCache_l984) begin io_mem_cmd_valid = 1'b0; end end else begin - if(_zz_15)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end - if(stageB_request_isAmo)begin - if(_zz_16)begin + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin io_mem_cmd_valid = 1'b0; end end - if(_zz_20)begin + if(when_DataCache_l1005) begin io_mem_cmd_valid = 1'b0; end - if(_zz_17)begin + if(when_DataCache_l1010) begin io_mem_cmd_valid = 1'b0; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -7749,12 +8057,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(! _zz_15) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -7765,23 +8073,44 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l984 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l997 = (! stageB_amo_internal_resultRegValid); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1010 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end - if((stageB_request_isLrsc && stageB_request_wr))begin - io_cpu_writeBack_data = {31'd0, _zz_37}; - end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign io_cpu_writeBack_exclusiveOk = stageB_lrSc_reserved; + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_18)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -7789,26 +8118,29 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_39); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; stageA_request_isAmo <= io_cpu_execute_args_isAmo; @@ -7816,18 +8148,17 @@ module DataCache ( stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_isLrsc <= stageA_request_isLrsc; stageB_request_isAmo <= stageA_request_isAmo; @@ -7835,7 +8166,7 @@ module DataCache ( stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -7854,48 +8185,39 @@ module DataCache ( stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_21)begin - if(_zz_22)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end stageB_amo_internal_resultRegValid <= io_cpu_writeBack_isStuck; stageB_amo_resultReg <= stageB_amo_result; loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; stageB_lrSc_reserved <= 1'b0; loader_valid <= 1'b0; @@ -7904,27 +8226,29 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_21)begin - if(! _zz_22) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end - if(((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc))begin + if(when_DataCache_l866) begin stageB_lrSc_reserved <= (! stageB_request_wr); end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_lrSc_reserved <= stageB_lrSc_reserved; end `ifndef SYNTHESIS @@ -7932,28 +8256,27 @@ module DataCache ( assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_18)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_40[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -8011,13 +8334,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [21:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [21:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -8026,8 +8345,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -8041,22 +8365,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -8074,82 +8401,85 @@ module InstructionCache ( reg [31:0] decodeStage_mmuRsp_ways_2_physical; reg decodeStage_mmuRsp_ways_3_sel; reg [31:0] decodeStage_mmuRsp_ways_3_physical; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - assign _zz_11 = (! lineLoader_flushCounter[7]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -8165,30 +8495,35 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -8196,51 +8531,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 8'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -8259,10 +8594,10 @@ module InstructionCache ( decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v index 6330d5a..9699b01 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v @@ -1,54 +1,54 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 - - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - -`define MmuPlugin_shared_State_defaultEncoding_type [2:0] -`define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000 -`define MmuPlugin_shared_State_defaultEncoding_L1_CMD 3'b001 -`define MmuPlugin_shared_State_defaultEncoding_L1_RSP 3'b010 -`define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011 -`define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 + +`define MmuPlugin_shared_State_binary_sequential_type [2:0] +`define MmuPlugin_shared_State_binary_sequential_IDLE 3'b000 +`define MmuPlugin_shared_State_binary_sequential_L1_CMD 3'b001 +`define MmuPlugin_shared_State_binary_sequential_L1_RSP 3'b010 +`define MmuPlugin_shared_State_binary_sequential_L0_CMD 3'b011 +`define MmuPlugin_shared_State_binary_sequential_L0_RSP 3'b100 module VexRiscv ( @@ -89,66 +89,42 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_208; - wire _zz_209; - wire _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - reg _zz_216; - reg _zz_217; - reg [31:0] _zz_218; - reg _zz_219; - reg [31:0] _zz_220; - reg [1:0] _zz_221; - reg _zz_222; - reg _zz_223; - wire _zz_224; - wire [2:0] _zz_225; - reg _zz_226; - wire [31:0] _zz_227; - reg _zz_228; - reg _zz_229; - wire _zz_230; - wire [31:0] _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire [3:0] _zz_240; - wire _zz_241; - wire _zz_242; - reg [31:0] _zz_243; - reg [31:0] _zz_244; - reg [31:0] _zz_245; - reg _zz_246; - reg _zz_247; - reg _zz_248; - reg [9:0] _zz_249; - reg [9:0] _zz_250; - reg [9:0] _zz_251; - reg [9:0] _zz_252; - reg _zz_253; - reg _zz_254; - reg _zz_255; - reg _zz_256; - reg _zz_257; - reg _zz_258; - reg _zz_259; - reg [9:0] _zz_260; - reg [9:0] _zz_261; - reg [9:0] _zz_262; - reg [9:0] _zz_263; - reg _zz_264; - reg _zz_265; - reg _zz_266; - reg _zz_267; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + reg dataCache_1_io_cpu_execute_isValid; + reg [31:0] dataCache_1_io_cpu_execute_address; + reg dataCache_1_io_cpu_execute_args_wr; + reg [1:0] dataCache_1_io_cpu_execute_args_size; + reg dataCache_1_io_cpu_execute_args_isLrsc; + wire dataCache_1_io_cpu_execute_args_amoCtrl_swap; + wire [2:0] dataCache_1_io_cpu_execute_args_amoCtrl_alu; + reg dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -171,6 +147,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -179,457 +156,360 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_268; - wire _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire _zz_279; - wire _zz_280; - wire _zz_281; - wire _zz_282; - wire _zz_283; - wire _zz_284; - wire [1:0] _zz_285; - wire _zz_286; - wire _zz_287; - wire _zz_288; - wire _zz_289; - wire _zz_290; - wire _zz_291; - wire _zz_292; - wire _zz_293; - wire _zz_294; - wire _zz_295; - wire _zz_296; - wire _zz_297; - wire _zz_298; - wire _zz_299; - wire _zz_300; - wire [1:0] _zz_301; - wire _zz_302; - wire _zz_303; - wire [5:0] _zz_304; - wire _zz_305; - wire _zz_306; - wire _zz_307; - wire _zz_308; - wire _zz_309; - wire _zz_310; - wire _zz_311; - wire _zz_312; - wire _zz_313; - wire _zz_314; - wire _zz_315; - wire _zz_316; - wire _zz_317; - wire _zz_318; - wire _zz_319; - wire _zz_320; - wire _zz_321; - wire _zz_322; - wire _zz_323; - wire _zz_324; - wire _zz_325; - wire _zz_326; - wire [1:0] _zz_327; - wire _zz_328; - wire [1:0] _zz_329; - wire [51:0] _zz_330; - wire [51:0] _zz_331; - wire [51:0] _zz_332; - wire [32:0] _zz_333; - wire [51:0] _zz_334; - wire [49:0] _zz_335; - wire [51:0] _zz_336; - wire [49:0] _zz_337; - wire [51:0] _zz_338; - wire [32:0] _zz_339; - wire [31:0] _zz_340; - wire [32:0] _zz_341; - wire [0:0] _zz_342; - wire [0:0] _zz_343; - wire [0:0] _zz_344; - wire [0:0] _zz_345; - wire [0:0] _zz_346; - wire [0:0] _zz_347; - wire [0:0] _zz_348; - wire [0:0] _zz_349; - wire [0:0] _zz_350; - wire [0:0] _zz_351; - wire [0:0] _zz_352; - wire [0:0] _zz_353; - wire [0:0] _zz_354; - wire [0:0] _zz_355; - wire [0:0] _zz_356; - wire [0:0] _zz_357; - wire [0:0] _zz_358; - wire [0:0] _zz_359; - wire [0:0] _zz_360; - wire [0:0] _zz_361; - wire [0:0] _zz_362; - wire [4:0] _zz_363; - wire [2:0] _zz_364; - wire [31:0] _zz_365; - wire [11:0] _zz_366; - wire [31:0] _zz_367; - wire [19:0] _zz_368; - wire [11:0] _zz_369; - wire [31:0] _zz_370; - wire [31:0] _zz_371; - wire [19:0] _zz_372; - wire [11:0] _zz_373; - wire [2:0] _zz_374; - wire [2:0] _zz_375; - wire [0:0] _zz_376; - wire [1:0] _zz_377; - wire [0:0] _zz_378; - wire [1:0] _zz_379; - wire [0:0] _zz_380; - wire [0:0] _zz_381; - wire [0:0] _zz_382; - wire [0:0] _zz_383; - wire [0:0] _zz_384; - wire [0:0] _zz_385; - wire [0:0] _zz_386; - wire [0:0] _zz_387; - wire [1:0] _zz_388; - wire [0:0] _zz_389; - wire [2:0] _zz_390; - wire [4:0] _zz_391; - wire [11:0] _zz_392; - wire [11:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire [31:0] _zz_399; - wire [31:0] _zz_400; - wire [11:0] _zz_401; - wire [19:0] _zz_402; - wire [11:0] _zz_403; - wire [31:0] _zz_404; - wire [31:0] _zz_405; - wire [31:0] _zz_406; - wire [11:0] _zz_407; - wire [19:0] _zz_408; - wire [11:0] _zz_409; - wire [2:0] _zz_410; - wire [1:0] _zz_411; - wire [1:0] _zz_412; - wire [65:0] _zz_413; - wire [65:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [0:0] _zz_417; - wire [5:0] _zz_418; - wire [32:0] _zz_419; - wire [31:0] _zz_420; - wire [31:0] _zz_421; - wire [32:0] _zz_422; - wire [32:0] _zz_423; - wire [32:0] _zz_424; - wire [32:0] _zz_425; - wire [0:0] _zz_426; - wire [32:0] _zz_427; - wire [0:0] _zz_428; - wire [32:0] _zz_429; - wire [0:0] _zz_430; - wire [31:0] _zz_431; - wire [0:0] _zz_432; - wire [0:0] _zz_433; - wire [0:0] _zz_434; - wire [0:0] _zz_435; - wire [0:0] _zz_436; - wire [0:0] _zz_437; - wire [0:0] _zz_438; - wire [0:0] _zz_439; - wire [0:0] _zz_440; - wire [0:0] _zz_441; - wire [0:0] _zz_442; - wire [0:0] _zz_443; - wire [0:0] _zz_444; - wire [0:0] _zz_445; - wire [0:0] _zz_446; - wire [0:0] _zz_447; - wire [0:0] _zz_448; - wire [0:0] _zz_449; - wire [0:0] _zz_450; - wire [0:0] _zz_451; - wire [0:0] _zz_452; - wire [0:0] _zz_453; - wire [0:0] _zz_454; - wire [0:0] _zz_455; - wire [0:0] _zz_456; - wire [0:0] _zz_457; - wire [0:0] _zz_458; - wire [0:0] _zz_459; - wire [0:0] _zz_460; - wire [0:0] _zz_461; - wire [0:0] _zz_462; - wire [0:0] _zz_463; - wire [0:0] _zz_464; - wire [0:0] _zz_465; - wire [0:0] _zz_466; - wire [0:0] _zz_467; - wire [0:0] _zz_468; - wire [0:0] _zz_469; - wire [0:0] _zz_470; - wire [0:0] _zz_471; - wire [0:0] _zz_472; - wire [0:0] _zz_473; - wire [0:0] _zz_474; - wire [0:0] _zz_475; - wire [0:0] _zz_476; - wire [26:0] _zz_477; - wire _zz_478; - wire _zz_479; - wire [2:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire _zz_484; - wire [0:0] _zz_485; - wire [17:0] _zz_486; - wire [31:0] _zz_487; - wire [31:0] _zz_488; - wire [31:0] _zz_489; - wire _zz_490; - wire [0:0] _zz_491; - wire [11:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; - wire _zz_496; - wire [0:0] _zz_497; - wire [5:0] _zz_498; - wire [31:0] _zz_499; - wire [31:0] _zz_500; - wire [31:0] _zz_501; - wire _zz_502; - wire _zz_503; - wire _zz_504; - wire _zz_505; - wire _zz_506; - wire [31:0] _zz_507; - wire [0:0] _zz_508; - wire [0:0] _zz_509; - wire _zz_510; - wire [0:0] _zz_511; - wire [29:0] _zz_512; - wire [31:0] _zz_513; - wire _zz_514; - wire _zz_515; - wire _zz_516; - wire [1:0] _zz_517; - wire [1:0] _zz_518; - wire _zz_519; - wire [0:0] _zz_520; - wire [25:0] _zz_521; - wire [31:0] _zz_522; - wire [31:0] _zz_523; - wire [31:0] _zz_524; - wire [31:0] _zz_525; - wire _zz_526; - wire _zz_527; - wire [1:0] _zz_528; - wire [1:0] _zz_529; - wire _zz_530; - wire [0:0] _zz_531; - wire [22:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire [31:0] _zz_535; - wire [31:0] _zz_536; - wire _zz_537; - wire [0:0] _zz_538; - wire [0:0] _zz_539; - wire _zz_540; - wire [0:0] _zz_541; - wire [0:0] _zz_542; - wire _zz_543; - wire [0:0] _zz_544; - wire [19:0] _zz_545; - wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire _zz_549; - wire _zz_550; - wire _zz_551; - wire [0:0] _zz_552; - wire [0:0] _zz_553; - wire _zz_554; - wire [0:0] _zz_555; - wire [16:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire [31:0] _zz_559; - wire [0:0] _zz_560; - wire [2:0] _zz_561; - wire [0:0] _zz_562; - wire [0:0] _zz_563; - wire _zz_564; - wire [0:0] _zz_565; - wire [13:0] _zz_566; - wire [31:0] _zz_567; - wire [31:0] _zz_568; - wire [31:0] _zz_569; - wire _zz_570; - wire _zz_571; - wire [31:0] _zz_572; - wire [31:0] _zz_573; - wire [31:0] _zz_574; - wire [0:0] _zz_575; - wire [4:0] _zz_576; - wire [2:0] _zz_577; - wire [2:0] _zz_578; - wire _zz_579; - wire [0:0] _zz_580; - wire [10:0] _zz_581; - wire [31:0] _zz_582; - wire [31:0] _zz_583; - wire [31:0] _zz_584; - wire [31:0] _zz_585; - wire _zz_586; - wire [0:0] _zz_587; - wire [2:0] _zz_588; - wire _zz_589; - wire [0:0] _zz_590; - wire [0:0] _zz_591; - wire [0:0] _zz_592; - wire [3:0] _zz_593; - wire [4:0] _zz_594; - wire [4:0] _zz_595; - wire _zz_596; - wire [0:0] _zz_597; - wire [8:0] _zz_598; - wire [31:0] _zz_599; - wire [31:0] _zz_600; - wire [31:0] _zz_601; - wire _zz_602; - wire [0:0] _zz_603; - wire [0:0] _zz_604; - wire [31:0] _zz_605; - wire [31:0] _zz_606; - wire [31:0] _zz_607; - wire [31:0] _zz_608; - wire [31:0] _zz_609; - wire [31:0] _zz_610; - wire [31:0] _zz_611; - wire _zz_612; - wire [0:0] _zz_613; - wire [1:0] _zz_614; - wire [0:0] _zz_615; - wire [2:0] _zz_616; - wire [0:0] _zz_617; - wire [5:0] _zz_618; - wire [1:0] _zz_619; - wire [1:0] _zz_620; - wire _zz_621; - wire [0:0] _zz_622; - wire [6:0] _zz_623; - wire [31:0] _zz_624; - wire [31:0] _zz_625; - wire [31:0] _zz_626; - wire [31:0] _zz_627; - wire [31:0] _zz_628; - wire [31:0] _zz_629; - wire [31:0] _zz_630; - wire [31:0] _zz_631; - wire _zz_632; - wire [31:0] _zz_633; - wire [31:0] _zz_634; - wire _zz_635; - wire [0:0] _zz_636; - wire [0:0] _zz_637; - wire _zz_638; - wire [0:0] _zz_639; - wire [3:0] _zz_640; - wire _zz_641; - wire [0:0] _zz_642; - wire [0:0] _zz_643; - wire [0:0] _zz_644; - wire [0:0] _zz_645; - wire _zz_646; - wire [0:0] _zz_647; - wire [4:0] _zz_648; - wire [31:0] _zz_649; - wire [31:0] _zz_650; - wire [31:0] _zz_651; - wire [31:0] _zz_652; - wire [31:0] _zz_653; - wire [31:0] _zz_654; - wire [31:0] _zz_655; - wire [31:0] _zz_656; - wire [31:0] _zz_657; - wire _zz_658; - wire [0:0] _zz_659; - wire [1:0] _zz_660; - wire [31:0] _zz_661; - wire [31:0] _zz_662; - wire [31:0] _zz_663; - wire [31:0] _zz_664; - wire [31:0] _zz_665; - wire _zz_666; - wire [4:0] _zz_667; - wire [4:0] _zz_668; - wire _zz_669; - wire [0:0] _zz_670; - wire [2:0] _zz_671; - wire [31:0] _zz_672; - wire [31:0] _zz_673; - wire [31:0] _zz_674; - wire _zz_675; - wire [31:0] _zz_676; - wire _zz_677; - wire [0:0] _zz_678; - wire [2:0] _zz_679; - wire [0:0] _zz_680; - wire [0:0] _zz_681; - wire [2:0] _zz_682; - wire [2:0] _zz_683; - wire _zz_684; - wire [0:0] _zz_685; - wire [0:0] _zz_686; - wire [31:0] _zz_687; - wire [31:0] _zz_688; - wire [31:0] _zz_689; - wire [31:0] _zz_690; - wire _zz_691; - wire [0:0] _zz_692; - wire [0:0] _zz_693; - wire [31:0] _zz_694; - wire [31:0] _zz_695; - wire _zz_696; - wire [0:0] _zz_697; - wire [0:0] _zz_698; - wire [0:0] _zz_699; - wire [1:0] _zz_700; - wire [1:0] _zz_701; - wire [1:0] _zz_702; - wire [0:0] _zz_703; - wire [0:0] _zz_704; - wire [31:0] _zz_705; - wire [31:0] _zz_706; - wire [31:0] _zz_707; - wire [31:0] _zz_708; - wire [31:0] _zz_709; - wire [31:0] _zz_710; - wire [31:0] _zz_711; - wire [31:0] _zz_712; - wire _zz_713; - wire _zz_714; - wire _zz_715; - wire [31:0] _zz_716; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [17:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [11:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [5:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_18; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_19; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_20; + wire _zz_decode_LEGAL_INSTRUCTION_21; + wire _zz_decode_LEGAL_INSTRUCTION_22; + wire [4:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_7; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspRf; + wire [9:0] _zz_MmuPlugin_ports_0_cacheHitsCalc; + wire [9:0] _zz_MmuPlugin_ports_0_cacheHitsCalc_1; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_2; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_3; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_4; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_5; + reg _zz_MmuPlugin_ports_0_cacheLine_valid_4; + reg _zz_MmuPlugin_ports_0_cacheLine_exception; + reg _zz_MmuPlugin_ports_0_cacheLine_superPage; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1; + reg _zz_MmuPlugin_ports_0_cacheLine_allowRead; + reg _zz_MmuPlugin_ports_0_cacheLine_allowWrite; + reg _zz_MmuPlugin_ports_0_cacheLine_allowExecute; + reg _zz_MmuPlugin_ports_0_cacheLine_allowUser; + wire [1:0] _zz_MmuPlugin_ports_0_entryToReplace_valueNext; + wire [0:0] _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1; + wire [9:0] _zz_MmuPlugin_ports_1_cacheHitsCalc; + wire [9:0] _zz_MmuPlugin_ports_1_cacheHitsCalc_1; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_2; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_3; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_4; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_5; + reg _zz_MmuPlugin_ports_1_cacheLine_valid_4; + reg _zz_MmuPlugin_ports_1_cacheLine_exception; + reg _zz_MmuPlugin_ports_1_cacheLine_superPage; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1; + reg _zz_MmuPlugin_ports_1_cacheLine_allowRead; + reg _zz_MmuPlugin_ports_1_cacheLine_allowWrite; + reg _zz_MmuPlugin_ports_1_cacheLine_allowExecute; + reg _zz_MmuPlugin_ports_1_cacheLine_allowUser; + wire [1:0] _zz_MmuPlugin_ports_1_entryToReplace_valueNext; + wire [0:0] _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1; + wire [1:0] _zz__zz_MmuPlugin_shared_refills_2; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_1; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_2; + wire _zz__zz_decode_IS_RS2_SIGNED_3; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_4; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_5; + wire _zz__zz_decode_IS_RS2_SIGNED_6; + wire _zz__zz_decode_IS_RS2_SIGNED_7; + wire [30:0] _zz__zz_decode_IS_RS2_SIGNED_8; + wire _zz__zz_decode_IS_RS2_SIGNED_9; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_10; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_11; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_12; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_13; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_14; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_15; + wire _zz__zz_decode_IS_RS2_SIGNED_16; + wire _zz__zz_decode_IS_RS2_SIGNED_17; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_18; + wire _zz__zz_decode_IS_RS2_SIGNED_19; + wire [26:0] _zz__zz_decode_IS_RS2_SIGNED_20; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_21; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_22; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_23; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_24; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_25; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_26; + wire _zz__zz_decode_IS_RS2_SIGNED_27; + wire _zz__zz_decode_IS_RS2_SIGNED_28; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_29; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_30; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_31; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_32; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_33; + wire _zz__zz_decode_IS_RS2_SIGNED_34; + wire [23:0] _zz__zz_decode_IS_RS2_SIGNED_35; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_36; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_37; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_38; + wire _zz__zz_decode_IS_RS2_SIGNED_39; + wire _zz__zz_decode_IS_RS2_SIGNED_40; + wire _zz__zz_decode_IS_RS2_SIGNED_41; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_42; + wire [20:0] _zz__zz_decode_IS_RS2_SIGNED_43; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_44; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_45; + wire _zz__zz_decode_IS_RS2_SIGNED_46; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_47; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_48; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_49; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_50; + wire [17:0] _zz__zz_decode_IS_RS2_SIGNED_51; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_52; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_53; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_54; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_55; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_56; + wire _zz__zz_decode_IS_RS2_SIGNED_57; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_58; + wire _zz__zz_decode_IS_RS2_SIGNED_59; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_60; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_61; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_62; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_63; + wire _zz__zz_decode_IS_RS2_SIGNED_64; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_65; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_66; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_67; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_68; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_69; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_70; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_71; + wire _zz__zz_decode_IS_RS2_SIGNED_72; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_73; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_74; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_75; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_76; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_77; + wire _zz__zz_decode_IS_RS2_SIGNED_78; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_79; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_80; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_81; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_82; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_83; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_84; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_85; + wire [13:0] _zz__zz_decode_IS_RS2_SIGNED_86; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_87; + wire _zz__zz_decode_IS_RS2_SIGNED_88; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_89; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_90; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_91; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_92; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_93; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_94; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_95; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_96; + wire _zz__zz_decode_IS_RS2_SIGNED_97; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_98; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_99; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_100; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_101; + wire _zz__zz_decode_IS_RS2_SIGNED_102; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_103; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_104; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_105; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_106; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_107; + wire _zz__zz_decode_IS_RS2_SIGNED_108; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_109; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_110; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_111; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_112; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_113; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_114; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_115; + wire _zz__zz_decode_IS_RS2_SIGNED_116; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_117; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_118; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_119; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_120; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_121; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_122; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_123; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_124; + wire [10:0] _zz__zz_decode_IS_RS2_SIGNED_125; + wire _zz__zz_decode_IS_RS2_SIGNED_126; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_127; + wire [5:0] _zz__zz_decode_IS_RS2_SIGNED_128; + wire _zz__zz_decode_IS_RS2_SIGNED_129; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_130; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_131; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_132; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_133; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_134; + wire _zz__zz_decode_IS_RS2_SIGNED_135; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_136; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_137; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_138; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_139; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_140; + wire _zz__zz_decode_IS_RS2_SIGNED_141; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_142; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_143; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_144; + wire _zz__zz_decode_IS_RS2_SIGNED_145; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_146; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_147; + wire [8:0] _zz__zz_decode_IS_RS2_SIGNED_148; + wire _zz__zz_decode_IS_RS2_SIGNED_149; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_150; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_151; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_152; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_153; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_154; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_155; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_156; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_157; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_158; + wire [6:0] _zz__zz_decode_IS_RS2_SIGNED_159; + wire _zz__zz_decode_IS_RS2_SIGNED_160; + wire _zz__zz_decode_IS_RS2_SIGNED_161; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_162; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_163; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_164; + wire _zz__zz_decode_IS_RS2_SIGNED_165; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_166; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_167; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_168; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_169; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_170; + wire _zz__zz_decode_IS_RS2_SIGNED_171; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_172; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_173; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_174; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_175; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_176; + wire _zz__zz_decode_IS_RS2_SIGNED_177; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_178; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_179; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_180; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_181; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_182; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_183; + wire _zz__zz_decode_IS_RS2_SIGNED_184; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_185; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_186; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_187; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_188; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_189; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_190; + wire _zz__zz_decode_IS_RS2_SIGNED_191; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_192; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_193; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_194; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_195; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_196; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_197; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_198; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_199; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_200; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_201; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_202; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_203; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_204; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; @@ -641,8 +521,8 @@ module VexRiscv ( wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; wire execute_IS_DBUS_SHARING; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_DO_EBREAK; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; @@ -654,49 +534,49 @@ module VexRiscv ( wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; - wire memory_IS_SFENCE_VMA; - wire execute_IS_SFENCE_VMA; wire decode_IS_SFENCE_VMA; + wire decode_IS_SFENCE_VMA2; wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_LRSC; wire memory_MEMORY_WR; wire decode_MEMORY_WR; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; @@ -718,23 +598,24 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; + wire execute_IS_SFENCE_VMA; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_30; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_31; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -744,54 +625,55 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_32; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_33; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_35; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_36; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_37; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_38; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39; - wire [31:0] _zz_40; - wire _zz_41; - reg _zz_42; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_43; - wire `BranchCtrlEnum_defaultEncoding_type _zz_44; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_45; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_46; - wire `Src2CtrlEnum_defaultEncoding_type _zz_47; - wire `AluCtrlEnum_defaultEncoding_type _zz_48; - wire `Src1CtrlEnum_defaultEncoding_type _zz_49; - wire writeBack_IS_SFENCE_VMA; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + wire execute_IS_SFENCE_VMA2; wire writeBack_IS_DBUS_SHARING; wire memory_IS_DBUS_SHARING; - reg [31:0] _zz_50; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_LRSC; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_ENABLE; - wire execute_MEMORY_AMO; - wire execute_MEMORY_LRSC; + reg execute_MEMORY_AMO; + reg execute_MEMORY_LRSC; wire execute_MEMORY_FORCE_CONSTISTENCY; wire execute_MEMORY_MANAGMENT; (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; @@ -801,19 +683,19 @@ module VexRiscv ( wire [31:0] execute_INSTRUCTION; wire decode_MEMORY_AMO; wire decode_MEMORY_LRSC; - reg _zz_51; + reg _zz_decode_MEMORY_FORCE_CONSTISTENCY; wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_4; reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_52; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_53; - reg [31:0] _zz_54; - reg [31:0] _zz_55; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -908,7 +790,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -942,7 +824,7 @@ module VexRiscv ( reg DBusCachedPlugin_exceptionBus_valid; reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_56; + reg _zz_when_DBusCachedPlugin_l386; reg MmuPlugin_dBusAccess_cmd_valid; reg MmuPlugin_dBusAccess_cmd_ready; reg [31:0] MmuPlugin_dBusAccess_cmd_payload_address; @@ -962,6 +844,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -982,32 +869,38 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; reg CsrPlugin_allowInterrupts; reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; reg IBusCachedPlugin_injectionPort_valid; reg IBusCachedPlugin_injectionPort_ready; wire [31:0] IBusCachedPlugin_injectionPort_payload; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [4:0] _zz_57; - wire [4:0] _zz_58; - wire _zz_59; - wire _zz_60; - wire _zz_61; - wire _zz_62; + wire [4:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [4:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_5; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -1030,16 +923,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_63; - wire _zz_64; - wire _zz_65; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_66; - wire _zz_67; - reg _zz_68; - wire _zz_69; - reg _zz_70; - reg [31:0] _zz_71; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -1047,22 +942,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_72; - reg [18:0] _zz_73; - wire _zz_74; - reg [10:0] _zz_75; - wire _zz_76; - reg [18:0] _zz_77; - reg _zz_78; - wire _zz_79; - reg [10:0] _zz_80; - wire _zz_81; - reg [18:0] _zz_82; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -1070,7 +972,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_83; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -1078,23 +980,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -1102,27 +1009,47 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_84; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; + wire when_DBusCachedPlugin_l311; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_85; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_86; - reg [31:0] _zz_87; - wire _zz_88; - reg [31:0] _zz_89; + reg [31:0] writeBack_DBusCachedPlugin_rspRf; + wire when_DBusCachedPlugin_l474; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire when_DBusCachedPlugin_l484; reg DBusCachedPlugin_forceDatapath; + wire when_DBusCachedPlugin_l498; + wire when_DBusCachedPlugin_l499; + wire MmuPlugin_dBusAccess_cmd_fire; reg MmuPlugin_status_sum; reg MmuPlugin_status_mxr; reg MmuPlugin_status_mprv; @@ -1175,12 +1102,14 @@ module VexRiscv ( reg MmuPlugin_ports_0_cache_3_allowUser; wire MmuPlugin_ports_0_dirty; reg MmuPlugin_ports_0_requireMmuLockupCalc; - reg [3:0] MmuPlugin_ports_0_cacheHitsCalc; + wire when_MmuPlugin_l125; + wire when_MmuPlugin_l126; + wire [3:0] MmuPlugin_ports_0_cacheHitsCalc; wire MmuPlugin_ports_0_cacheHit; - wire _zz_90; - wire _zz_91; - wire _zz_92; - wire [1:0] _zz_93; + wire _zz_MmuPlugin_ports_0_cacheLine_valid; + wire _zz_MmuPlugin_ports_0_cacheLine_valid_1; + wire _zz_MmuPlugin_ports_0_cacheLine_valid_2; + wire [1:0] _zz_MmuPlugin_ports_0_cacheLine_valid_3; wire MmuPlugin_ports_0_cacheLine_valid; wire MmuPlugin_ports_0_cacheLine_exception; wire MmuPlugin_ports_0_cacheLine_superPage; @@ -1244,12 +1173,15 @@ module VexRiscv ( reg MmuPlugin_ports_1_cache_3_allowUser; wire MmuPlugin_ports_1_dirty; reg MmuPlugin_ports_1_requireMmuLockupCalc; - reg [3:0] MmuPlugin_ports_1_cacheHitsCalc; + wire when_MmuPlugin_l125_1; + wire when_MmuPlugin_l126_1; + wire when_MmuPlugin_l128; + wire [3:0] MmuPlugin_ports_1_cacheHitsCalc; wire MmuPlugin_ports_1_cacheHit; - wire _zz_94; - wire _zz_95; - wire _zz_96; - wire [1:0] _zz_97; + wire _zz_MmuPlugin_ports_1_cacheLine_valid; + wire _zz_MmuPlugin_ports_1_cacheLine_valid_1; + wire _zz_MmuPlugin_ports_1_cacheLine_valid_2; + wire [1:0] _zz_MmuPlugin_ports_1_cacheLine_valid_3; wire MmuPlugin_ports_1_cacheLine_valid; wire MmuPlugin_ports_1_cacheLine_exception; wire MmuPlugin_ports_1_cacheLine_superPage; @@ -1267,7 +1199,7 @@ module VexRiscv ( reg [1:0] MmuPlugin_ports_1_entryToReplace_value; wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; wire MmuPlugin_ports_1_entryToReplace_willOverflow; - reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1; + reg `MmuPlugin_shared_State_binary_sequential_type MmuPlugin_shared_state_1; reg [9:0] MmuPlugin_shared_vpn_0; reg [9:0] MmuPlugin_shared_vpn_1; reg [1:0] MmuPlugin_shared_portSortedOh; @@ -1288,6 +1220,7 @@ module VexRiscv ( wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; wire MmuPlugin_shared_dBusRsp_exception; wire MmuPlugin_shared_dBusRsp_leaf; + wire when_MmuPlugin_l205; reg MmuPlugin_shared_pteBuffer_V; reg MmuPlugin_shared_pteBuffer_R; reg MmuPlugin_shared_pteBuffer_W; @@ -1299,27 +1232,42 @@ module VexRiscv ( reg [1:0] MmuPlugin_shared_pteBuffer_RSW; reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; - reg [1:0] _zz_98; - wire [1:0] _zz_99; - reg [1:0] _zz_100; + wire [1:0] _zz_MmuPlugin_shared_refills; + reg [1:0] _zz_MmuPlugin_shared_refills_1; wire [1:0] MmuPlugin_shared_refills; - wire [1:0] _zz_101; - reg [1:0] _zz_102; - wire [31:0] _zz_103; - wire [35:0] _zz_104; - wire _zz_105; - wire _zz_106; - wire _zz_107; - wire _zz_108; - wire _zz_109; - wire _zz_110; - wire `Src1CtrlEnum_defaultEncoding_type _zz_111; - wire `AluCtrlEnum_defaultEncoding_type _zz_112; - wire `Src2CtrlEnum_defaultEncoding_type _zz_113; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_114; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_115; - wire `BranchCtrlEnum_defaultEncoding_type _zz_116; - wire `EnvCtrlEnum_defaultEncoding_type _zz_117; + wire [1:0] _zz_MmuPlugin_shared_refills_2; + reg [1:0] _zz_MmuPlugin_shared_refills_3; + wire when_MmuPlugin_l217; + wire [31:0] _zz_MmuPlugin_shared_vpn_0; + wire when_MmuPlugin_l243; + wire when_MmuPlugin_l272; + wire when_MmuPlugin_l274; + wire when_MmuPlugin_l280; + wire when_MmuPlugin_l280_1; + wire when_MmuPlugin_l280_2; + wire when_MmuPlugin_l280_3; + wire when_MmuPlugin_l274_1; + wire when_MmuPlugin_l280_4; + wire when_MmuPlugin_l280_5; + wire when_MmuPlugin_l280_6; + wire when_MmuPlugin_l280_7; + wire when_MmuPlugin_l304; + wire [36:0] _zz_decode_IS_RS2_SIGNED; + wire _zz_decode_IS_RS2_SIGNED_1; + wire _zz_decode_IS_RS2_SIGNED_2; + wire _zz_decode_IS_RS2_SIGNED_3; + wire _zz_decode_IS_RS2_SIGNED_4; + wire _zz_decode_IS_RS2_SIGNED_5; + wire _zz_decode_IS_RS2_SIGNED_6; + wire _zz_decode_IS_RS2_SIGNED_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -1327,54 +1275,72 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_118; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_119; - reg [31:0] _zz_120; - wire _zz_121; - reg [19:0] _zz_122; - wire _zz_123; - reg [19:0] _zz_124; - reg [31:0] _zz_125; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_126; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_127; - reg _zz_128; - reg _zz_129; - reg _zz_130; - reg [4:0] _zz_131; - reg [31:0] _zz_132; - wire _zz_133; - wire _zz_134; - wire _zz_135; - wire _zz_136; - wire _zz_137; - wire _zz_138; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_139; - reg _zz_140; - reg _zz_141; - wire _zz_142; - reg [19:0] _zz_143; - wire _zz_144; - reg [10:0] _zz_145; - wire _zz_146; - reg [18:0] _zz_147; - reg _zz_148; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_149; - reg [19:0] _zz_150; - wire _zz_151; - reg [10:0] _zz_152; - wire _zz_153; - reg [18:0] _zz_154; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] _zz_155; + reg [1:0] _zz_CsrPlugin_privilege; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1431,12 +1397,14 @@ module VexRiscv ( reg [21:0] CsrPlugin_satp_PPN; reg [8:0] CsrPlugin_satp_ASID; reg [0:0] CsrPlugin_satp_MODE; - wire _zz_156; - wire _zz_157; - wire _zz_158; - wire _zz_159; - wire _zz_160; - wire _zz_161; + reg CsrPlugin_rescheduleLogic_rescheduleNext; + wire when_CsrPlugin_l803; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; + wire _zz_when_CsrPlugin_l952_3; + wire _zz_when_CsrPlugin_l952_4; + wire _zz_when_CsrPlugin_l952_5; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1448,41 +1416,87 @@ module VexRiscv ( reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire when_CsrPlugin_l866; + wire when_CsrPlugin_l866_1; + wire when_CsrPlugin_l866_2; + wire when_CsrPlugin_l866_3; + wire when_CsrPlugin_l866_4; + wire when_CsrPlugin_l866_5; + wire when_CsrPlugin_l866_6; + wire when_CsrPlugin_l866_7; + wire when_CsrPlugin_l866_8; + wire when_CsrPlugin_l866_9; + wire when_CsrPlugin_l866_10; + wire when_CsrPlugin_l866_11; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_162; - wire _zz_163; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l946_1; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; + wire when_CsrPlugin_l952_3; + wire when_CsrPlugin_l952_4; + wire when_CsrPlugin_l952_5; + wire when_CsrPlugin_l952_6; + wire when_CsrPlugin_l952_7; + wire when_CsrPlugin_l952_8; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; reg [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1490,6 +1504,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1502,21 +1518,28 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_164; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_165; - wire _zz_166; - wire _zz_167; - reg [32:0] _zz_168; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_169; - wire [31:0] _zz_170; - reg [31:0] _zz_171; - wire [31:0] _zz_172; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1524,215 +1547,342 @@ module VexRiscv ( reg DebugPlugin_stepIt; reg DebugPlugin_isPipBusy; reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_173; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_LRSC; + wire when_Pipeline_l124_27; + reg execute_to_memory_MEMORY_LRSC; + wire when_Pipeline_l124_28; + reg memory_to_writeBack_MEMORY_LRSC; + wire when_Pipeline_l124_29; reg decode_to_execute_MEMORY_AMO; + wire when_Pipeline_l124_30; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_31; + reg decode_to_execute_IS_SFENCE_VMA2; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_SFENCE_VMA; - reg execute_to_memory_IS_SFENCE_VMA; - reg memory_to_writeBack_IS_SFENCE_VMA; + wire when_Pipeline_l124_33; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_34; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_35; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_36; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_37; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_38; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_39; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_40; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_41; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_43; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_44; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_45; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_46; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_47; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_48; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_49; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_50; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_51; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_52; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_53; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_54; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_55; reg decode_to_execute_DO_EBREAK; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_56; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_57; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_58; reg execute_to_memory_IS_DBUS_SHARING; + wire when_Pipeline_l124_59; reg memory_to_writeBack_IS_DBUS_SHARING; + wire when_Pipeline_l124_60; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_61; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_62; reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_63; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_64; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_65; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_66; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_67; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_68; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_69; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_70; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_174; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l378; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_256; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_384; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_770; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_771; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_324; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_260; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_261; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_321; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_320; + wire when_CsrPlugin_l1264_22; reg execute_CsrPlugin_csr_322; + wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_323; + wire when_CsrPlugin_l1264_24; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_25; reg execute_CsrPlugin_csr_4032; + wire when_CsrPlugin_l1264_26; reg execute_CsrPlugin_csr_2496; + wire when_CsrPlugin_l1264_27; reg execute_CsrPlugin_csr_3520; - reg [31:0] _zz_175; - reg [31:0] _zz_176; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [2:0] _zz_199; - reg _zz_200; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_201; - wire _zz_202; - wire _zz_203; - wire _zz_204; - wire _zz_205; - wire _zz_206; - reg _zz_207; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; - reg [39:0] _zz_17_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; - reg [23:0] _zz_20_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; - reg [63:0] _zz_23_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; - reg [95:0] _zz_26_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_30_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_33_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_34_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_36_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_37_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_38_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_39_string; - reg [39:0] _zz_43_string; - reg [31:0] _zz_44_string; - reg [71:0] _zz_45_string; - reg [39:0] _zz_46_string; - reg [23:0] _zz_47_string; - reg [63:0] _zz_48_string; - reg [95:0] _zz_49_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_52_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; reg [47:0] MmuPlugin_shared_state_1_string; - reg [95:0] _zz_111_string; - reg [63:0] _zz_112_string; - reg [23:0] _zz_113_string; - reg [39:0] _zz_114_string; - reg [71:0] _zz_115_string; - reg [31:0] _zz_116_string; - reg [39:0] _zz_117_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1747,1430 +1897,1335 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_268 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_269 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_270 = 1'b1; - assign _zz_271 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_272 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_273 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_274 = ((_zz_213 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_275 = ((_zz_213 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_276 = ((_zz_213 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_277 = ((_zz_213 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_278 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_280 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_281 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_282 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_283 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_284 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_285 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_286 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); - assign _zz_287 = (! dataCache_1_io_cpu_execute_refilling); - assign _zz_288 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_289 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); - assign _zz_290 = MmuPlugin_shared_portSortedOh[0]; - assign _zz_291 = MmuPlugin_shared_portSortedOh[1]; - assign _zz_292 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_293 = (1'b0 || (! 1'b1)); - assign _zz_294 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_295 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_296 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_297 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_298 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_299 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_300 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_301 = execute_INSTRUCTION[13 : 12]; - assign _zz_302 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_303 = (! memory_arbitration_isStuck); - assign _zz_304 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_305 = (iBus_cmd_valid || (_zz_199 != 3'b000)); - assign _zz_306 = (_zz_242 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_307 = (MmuPlugin_shared_refills != 2'b00); - assign _zz_308 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); - assign _zz_309 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); - assign _zz_310 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); - assign _zz_311 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); - assign _zz_312 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); - assign _zz_313 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); - assign _zz_314 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); - assign _zz_315 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); - assign _zz_316 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); - assign _zz_317 = ((_zz_156 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); - assign _zz_318 = ((_zz_157 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); - assign _zz_319 = ((_zz_158 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); - assign _zz_320 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_321 = ((_zz_156 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); - assign _zz_322 = ((_zz_157 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); - assign _zz_323 = ((_zz_158 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); - assign _zz_324 = ((_zz_159 && 1'b1) && (! 1'b0)); - assign _zz_325 = ((_zz_160 && 1'b1) && (! 1'b0)); - assign _zz_326 = ((_zz_161 && 1'b1) && (! 1'b0)); - assign _zz_327 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_328 = execute_INSTRUCTION[13]; - assign _zz_329 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_330 = ($signed(_zz_331) + $signed(_zz_336)); - assign _zz_331 = ($signed(_zz_332) + $signed(_zz_334)); - assign _zz_332 = 52'h0; - assign _zz_333 = {1'b0,memory_MUL_LL}; - assign _zz_334 = {{19{_zz_333[32]}}, _zz_333}; - assign _zz_335 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_336 = {{2{_zz_335[49]}}, _zz_335}; - assign _zz_337 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_338 = {{2{_zz_337[49]}}, _zz_337}; - assign _zz_339 = ($signed(_zz_341) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_340 = _zz_339[31 : 0]; - assign _zz_341 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_342 = _zz_104[34 : 34]; - assign _zz_343 = _zz_104[33 : 33]; - assign _zz_344 = _zz_104[32 : 32]; - assign _zz_345 = _zz_104[31 : 31]; - assign _zz_346 = _zz_104[28 : 28]; - assign _zz_347 = _zz_104[21 : 21]; - assign _zz_348 = _zz_104[20 : 20]; - assign _zz_349 = _zz_104[19 : 19]; - assign _zz_350 = _zz_104[13 : 13]; - assign _zz_351 = _zz_104[12 : 12]; - assign _zz_352 = _zz_104[11 : 11]; - assign _zz_353 = _zz_104[35 : 35]; - assign _zz_354 = _zz_104[17 : 17]; - assign _zz_355 = _zz_104[5 : 5]; - assign _zz_356 = _zz_104[3 : 3]; - assign _zz_357 = _zz_104[18 : 18]; - assign _zz_358 = _zz_104[10 : 10]; - assign _zz_359 = _zz_104[16 : 16]; - assign _zz_360 = _zz_104[15 : 15]; - assign _zz_361 = _zz_104[4 : 4]; - assign _zz_362 = _zz_104[0 : 0]; - assign _zz_363 = (_zz_57 - 5'h01); - assign _zz_364 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_365 = {29'd0, _zz_364}; - assign _zz_366 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_367 = {{_zz_73,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_368 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_369 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_370 = {{_zz_75,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_371 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_372 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_373 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_374 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_375 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_376 = MmuPlugin_ports_0_entryToReplace_willIncrement; - assign _zz_377 = {1'd0, _zz_376}; - assign _zz_378 = MmuPlugin_ports_1_entryToReplace_willIncrement; - assign _zz_379 = {1'd0, _zz_378}; - assign _zz_380 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; - assign _zz_381 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; - assign _zz_382 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; - assign _zz_383 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; - assign _zz_384 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; - assign _zz_385 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; - assign _zz_386 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; - assign _zz_387 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; - assign _zz_388 = (_zz_100 - 2'b01); - assign _zz_389 = execute_SRC_LESS; - assign _zz_390 = 3'b100; - assign _zz_391 = execute_INSTRUCTION[19 : 15]; - assign _zz_392 = execute_INSTRUCTION[31 : 20]; - assign _zz_393 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_394 = ($signed(_zz_395) + $signed(_zz_398)); - assign _zz_395 = ($signed(_zz_396) + $signed(_zz_397)); - assign _zz_396 = execute_SRC1; - assign _zz_397 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_398 = (execute_SRC_USE_SUB_LESS ? _zz_399 : _zz_400); - assign _zz_399 = 32'h00000001; - assign _zz_400 = 32'h0; - assign _zz_401 = execute_INSTRUCTION[31 : 20]; - assign _zz_402 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_403 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_404 = {_zz_143,execute_INSTRUCTION[31 : 20]}; - assign _zz_405 = {{_zz_145,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_406 = {{_zz_147,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_407 = execute_INSTRUCTION[31 : 20]; - assign _zz_408 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_409 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_410 = 3'b100; - assign _zz_411 = (_zz_162 & (~ _zz_412)); - assign _zz_412 = (_zz_162 - 2'b01); - assign _zz_413 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_414 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_415 = writeBack_MUL_LOW[31 : 0]; - assign _zz_416 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_417 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_418 = {5'd0, _zz_417}; - assign _zz_419 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_420 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_421 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_422 = {_zz_164,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_423 = _zz_424; - assign _zz_424 = _zz_425; - assign _zz_425 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_165) : _zz_165)} + _zz_427); - assign _zz_426 = memory_DivPlugin_div_needRevert; - assign _zz_427 = {32'd0, _zz_426}; - assign _zz_428 = _zz_167; - assign _zz_429 = {32'd0, _zz_428}; - assign _zz_430 = _zz_166; - assign _zz_431 = {31'd0, _zz_430}; - assign _zz_432 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_433 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_434 = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_435 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_436 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_437 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_438 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_439 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_440 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_441 = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_442 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_443 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_444 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_445 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_446 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_447 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_448 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_449 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_450 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_451 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_452 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_453 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_454 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_455 = execute_CsrPlugin_writeData[0 : 0]; - assign _zz_456 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_457 = execute_CsrPlugin_writeData[2 : 2]; - assign _zz_458 = execute_CsrPlugin_writeData[4 : 4]; - assign _zz_459 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_460 = execute_CsrPlugin_writeData[6 : 6]; - assign _zz_461 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_462 = execute_CsrPlugin_writeData[8 : 8]; - assign _zz_463 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_464 = execute_CsrPlugin_writeData[12 : 12]; - assign _zz_465 = execute_CsrPlugin_writeData[13 : 13]; - assign _zz_466 = execute_CsrPlugin_writeData[15 : 15]; - assign _zz_467 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_468 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_469 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_470 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_471 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_472 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_473 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_474 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_475 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_476 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_477 = (iBus_cmd_payload_address >>> 5); - assign _zz_478 = 1'b1; - assign _zz_479 = 1'b1; - assign _zz_480 = {_zz_60,{_zz_62,_zz_61}}; - assign _zz_481 = 32'h0000107f; - assign _zz_482 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_483 = 32'h00002073; - assign _zz_484 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_485 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_486 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_487) == 32'h00000003),{(_zz_488 == _zz_489),{_zz_490,{_zz_491,_zz_492}}}}}}; - assign _zz_487 = 32'h0000505f; - assign _zz_488 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_489 = 32'h00000063; - assign _zz_490 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_491 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); - assign _zz_492 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_493) == 32'h0000500f),{(_zz_494 == _zz_495),{_zz_496,{_zz_497,_zz_498}}}}}}; - assign _zz_493 = 32'h01f0707f; - assign _zz_494 = (decode_INSTRUCTION & 32'hbc00707f); - assign _zz_495 = 32'h00005013; - assign _zz_496 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); - assign _zz_497 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_498 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_499) == 32'h12000073),{(_zz_500 == _zz_501),{_zz_502,_zz_503}}}}}; - assign _zz_499 = 32'hfe007fff; - assign _zz_500 = (decode_INSTRUCTION & 32'hdfffffff); - assign _zz_501 = 32'h10200073; - assign _zz_502 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); - assign _zz_503 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_504 = decode_INSTRUCTION[31]; - assign _zz_505 = decode_INSTRUCTION[31]; - assign _zz_506 = decode_INSTRUCTION[7]; - assign _zz_507 = 32'h10103050; - assign _zz_508 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_509 = 1'b0; - assign _zz_510 = (((decode_INSTRUCTION & _zz_513) == 32'h02000030) != 1'b0); - assign _zz_511 = ({_zz_514,_zz_515} != 2'b00); - assign _zz_512 = {(_zz_516 != 1'b0),{(_zz_517 != _zz_518),{_zz_519,{_zz_520,_zz_521}}}}; - assign _zz_513 = 32'h02004074; - assign _zz_514 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); - assign _zz_515 = ((decode_INSTRUCTION & 32'h12203050) == 32'h10000050); - assign _zz_516 = ((decode_INSTRUCTION & 32'h02103050) == 32'h00000050); - assign _zz_517 = {(_zz_522 == _zz_523),(_zz_524 == _zz_525)}; - assign _zz_518 = 2'b00; - assign _zz_519 = ({_zz_106,_zz_526} != 2'b00); - assign _zz_520 = (_zz_527 != 1'b0); - assign _zz_521 = {(_zz_528 != _zz_529),{_zz_530,{_zz_531,_zz_532}}}; - assign _zz_522 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_523 = 32'h00001050; - assign _zz_524 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_525 = 32'h00002050; - assign _zz_526 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_527 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_528 = {(_zz_533 == _zz_534),(_zz_535 == _zz_536)}; - assign _zz_529 = 2'b00; - assign _zz_530 = ({_zz_537,{_zz_538,_zz_539}} != 3'b000); - assign _zz_531 = (_zz_540 != 1'b0); - assign _zz_532 = {(_zz_541 != _zz_542),{_zz_543,{_zz_544,_zz_545}}}; - assign _zz_533 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_534 = 32'h00005010; - assign _zz_535 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_536 = 32'h00005020; - assign _zz_537 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_538 = ((decode_INSTRUCTION & _zz_546) == 32'h00001010); - assign _zz_539 = ((decode_INSTRUCTION & _zz_547) == 32'h00001010); - assign _zz_540 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_541 = ((decode_INSTRUCTION & _zz_548) == 32'h00002000); - assign _zz_542 = 1'b0; - assign _zz_543 = ({_zz_549,_zz_550} != 2'b00); - assign _zz_544 = (_zz_551 != 1'b0); - assign _zz_545 = {(_zz_552 != _zz_553),{_zz_554,{_zz_555,_zz_556}}}; - assign _zz_546 = 32'h00007034; - assign _zz_547 = 32'h02007054; - assign _zz_548 = 32'h00003000; - assign _zz_549 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_550 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_551 = ((decode_INSTRUCTION & 32'h02003050) == 32'h02000050); - assign _zz_552 = ((decode_INSTRUCTION & _zz_557) == 32'h00004008); - assign _zz_553 = 1'b0; - assign _zz_554 = ((_zz_558 == _zz_559) != 1'b0); - assign _zz_555 = ({_zz_560,_zz_561} != 4'b0000); - assign _zz_556 = {(_zz_562 != _zz_563),{_zz_564,{_zz_565,_zz_566}}}; - assign _zz_557 = 32'h00004048; - assign _zz_558 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_559 = 32'h00000024; - assign _zz_560 = ((decode_INSTRUCTION & _zz_567) == 32'h00000020); - assign _zz_561 = {(_zz_568 == _zz_569),{_zz_570,_zz_571}}; - assign _zz_562 = ((decode_INSTRUCTION & _zz_572) == 32'h00000008); - assign _zz_563 = 1'b0; - assign _zz_564 = ((_zz_573 == _zz_574) != 1'b0); - assign _zz_565 = ({_zz_575,_zz_576} != 6'h0); - assign _zz_566 = {(_zz_577 != _zz_578),{_zz_579,{_zz_580,_zz_581}}}; - assign _zz_567 = 32'h00000034; - assign _zz_568 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_569 = 32'h00000020; - assign _zz_570 = ((decode_INSTRUCTION & _zz_582) == 32'h08000020); - assign _zz_571 = ((decode_INSTRUCTION & _zz_583) == 32'h00000020); - assign _zz_572 = 32'h10000008; - assign _zz_573 = (decode_INSTRUCTION & 32'h10000008); - assign _zz_574 = 32'h10000008; - assign _zz_575 = (_zz_584 == _zz_585); - assign _zz_576 = {_zz_586,{_zz_587,_zz_588}}; - assign _zz_577 = {_zz_589,{_zz_590,_zz_591}}; - assign _zz_578 = 3'b000; - assign _zz_579 = ({_zz_592,_zz_593} != 5'h0); - assign _zz_580 = (_zz_594 != _zz_595); - assign _zz_581 = {_zz_596,{_zz_597,_zz_598}}; - assign _zz_582 = 32'h08000070; - assign _zz_583 = 32'h10000070; - assign _zz_584 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_585 = 32'h00002040; - assign _zz_586 = ((decode_INSTRUCTION & _zz_599) == 32'h00001040); - assign _zz_587 = (_zz_600 == _zz_601); - assign _zz_588 = {_zz_602,{_zz_603,_zz_604}}; - assign _zz_589 = ((decode_INSTRUCTION & _zz_605) == 32'h08000020); - assign _zz_590 = (_zz_606 == _zz_607); - assign _zz_591 = (_zz_608 == _zz_609); - assign _zz_592 = (_zz_610 == _zz_611); - assign _zz_593 = {_zz_612,{_zz_613,_zz_614}}; - assign _zz_594 = {_zz_109,{_zz_615,_zz_616}}; - assign _zz_595 = 5'h0; - assign _zz_596 = ({_zz_617,_zz_618} != 7'h0); - assign _zz_597 = (_zz_619 != _zz_620); - assign _zz_598 = {_zz_621,{_zz_622,_zz_623}}; - assign _zz_599 = 32'h00001040; - assign _zz_600 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_601 = 32'h00000040; - assign _zz_602 = ((decode_INSTRUCTION & _zz_624) == 32'h00000040); - assign _zz_603 = (_zz_625 == _zz_626); - assign _zz_604 = (_zz_627 == _zz_628); - assign _zz_605 = 32'h08000020; - assign _zz_606 = (decode_INSTRUCTION & 32'h10000020); - assign _zz_607 = 32'h00000020; - assign _zz_608 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_609 = 32'h00000020; - assign _zz_610 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_611 = 32'h00000040; - assign _zz_612 = ((decode_INSTRUCTION & _zz_629) == 32'h00004020); - assign _zz_613 = (_zz_630 == _zz_631); - assign _zz_614 = {_zz_109,_zz_632}; - assign _zz_615 = (_zz_633 == _zz_634); - assign _zz_616 = {_zz_635,{_zz_636,_zz_637}}; - assign _zz_617 = _zz_106; - assign _zz_618 = {_zz_638,{_zz_639,_zz_640}}; - assign _zz_619 = {_zz_108,_zz_641}; - assign _zz_620 = 2'b00; - assign _zz_621 = ({_zz_642,_zz_643} != 2'b00); - assign _zz_622 = (_zz_644 != _zz_645); - assign _zz_623 = {_zz_646,{_zz_647,_zz_648}}; - assign _zz_624 = 32'h02100040; - assign _zz_625 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_626 = 32'h0; - assign _zz_627 = (decode_INSTRUCTION & 32'h18002008); - assign _zz_628 = 32'h10002008; - assign _zz_629 = 32'h00004020; - assign _zz_630 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_631 = 32'h00000010; - assign _zz_632 = ((decode_INSTRUCTION & _zz_649) == 32'h00000020); - assign _zz_633 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_634 = 32'h00002010; - assign _zz_635 = ((decode_INSTRUCTION & _zz_650) == 32'h00000010); - assign _zz_636 = (_zz_651 == _zz_652); - assign _zz_637 = (_zz_653 == _zz_654); - assign _zz_638 = ((decode_INSTRUCTION & _zz_655) == 32'h00001010); - assign _zz_639 = (_zz_656 == _zz_657); - assign _zz_640 = {_zz_658,{_zz_659,_zz_660}}; - assign _zz_641 = ((decode_INSTRUCTION & _zz_661) == 32'h00000020); - assign _zz_642 = _zz_108; - assign _zz_643 = (_zz_662 == _zz_663); - assign _zz_644 = (_zz_664 == _zz_665); - assign _zz_645 = 1'b0; - assign _zz_646 = (_zz_666 != 1'b0); - assign _zz_647 = (_zz_667 != _zz_668); - assign _zz_648 = {_zz_669,{_zz_670,_zz_671}}; - assign _zz_649 = 32'h02000028; - assign _zz_650 = 32'h00001030; - assign _zz_651 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_652 = 32'h00000020; - assign _zz_653 = (decode_INSTRUCTION & 32'h02002068); - assign _zz_654 = 32'h00002020; - assign _zz_655 = 32'h00001010; - assign _zz_656 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_657 = 32'h00002010; - assign _zz_658 = ((decode_INSTRUCTION & _zz_672) == 32'h00002008); - assign _zz_659 = (_zz_673 == _zz_674); - assign _zz_660 = {_zz_109,_zz_675}; - assign _zz_661 = 32'h00000070; - assign _zz_662 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_663 = 32'h0; - assign _zz_664 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_665 = 32'h00004010; - assign _zz_666 = ((decode_INSTRUCTION & _zz_676) == 32'h00002010); - assign _zz_667 = {_zz_677,{_zz_678,_zz_679}}; - assign _zz_668 = 5'h0; - assign _zz_669 = ({_zz_680,_zz_681} != 2'b00); - assign _zz_670 = (_zz_682 != _zz_683); - assign _zz_671 = {_zz_684,{_zz_685,_zz_686}}; - assign _zz_672 = 32'h00002008; - assign _zz_673 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_674 = 32'h00000010; - assign _zz_675 = ((decode_INSTRUCTION & _zz_687) == 32'h0); - assign _zz_676 = 32'h00006014; - assign _zz_677 = ((decode_INSTRUCTION & _zz_688) == 32'h0); - assign _zz_678 = (_zz_689 == _zz_690); - assign _zz_679 = {_zz_691,{_zz_692,_zz_693}}; - assign _zz_680 = _zz_107; - assign _zz_681 = (_zz_694 == _zz_695); - assign _zz_682 = {_zz_696,{_zz_697,_zz_698}}; - assign _zz_683 = 3'b000; - assign _zz_684 = ({_zz_699,_zz_700} != 3'b000); - assign _zz_685 = (_zz_701 != _zz_702); - assign _zz_686 = (_zz_703 != _zz_704); - assign _zz_687 = 32'h00000028; - assign _zz_688 = 32'h00000044; - assign _zz_689 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_690 = 32'h0; - assign _zz_691 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_692 = ((decode_INSTRUCTION & _zz_705) == 32'h00001000); - assign _zz_693 = _zz_107; - assign _zz_694 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_695 = 32'h0; - assign _zz_696 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_697 = ((decode_INSTRUCTION & _zz_706) == 32'h00002010); - assign _zz_698 = ((decode_INSTRUCTION & _zz_707) == 32'h40000030); - assign _zz_699 = _zz_106; - assign _zz_700 = {_zz_105,(_zz_708 == _zz_709)}; - assign _zz_701 = {_zz_105,(_zz_710 == _zz_711)}; - assign _zz_702 = 2'b00; - assign _zz_703 = ((decode_INSTRUCTION & _zz_712) == 32'h00001008); - assign _zz_704 = 1'b0; - assign _zz_705 = 32'h00005004; - assign _zz_706 = 32'h00002014; - assign _zz_707 = 32'h40000034; - assign _zz_708 = (decode_INSTRUCTION & 32'h00002014); - assign _zz_709 = 32'h00000004; - assign _zz_710 = (decode_INSTRUCTION & 32'h0000004c); - assign _zz_711 = 32'h00000004; - assign _zz_712 = 32'h00005048; - assign _zz_713 = execute_INSTRUCTION[31]; - assign _zz_714 = execute_INSTRUCTION[31]; - assign _zz_715 = execute_INSTRUCTION[7]; - assign _zz_716 = 32'h0; - always @ (posedge clk) begin - if(_zz_478) begin - _zz_243 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_479) begin - _zz_244 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_42) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 5'h01); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_writeBack_DBusCachedPlugin_rspRf = (! dataCache_1_io_cpu_writeBack_exclusiveOk); + assign _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_MmuPlugin_ports_0_entryToReplace_valueNext = {1'd0, _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1}; + assign _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_MmuPlugin_ports_1_entryToReplace_valueNext = {1'd0, _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1}; + assign _zz__zz_MmuPlugin_shared_refills_2 = (_zz_MmuPlugin_shared_refills_1 - 2'b01); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_7 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,{_zz_IBusCachedPlugin_jump_pcLoad_payload_5,_zz_IBusCachedPlugin_jump_pcLoad_payload_4}}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h0000500f),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'h01f0707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbc00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_18) == 32'h12000073),{(_zz_decode_LEGAL_INSTRUCTION_19 == _zz_decode_LEGAL_INSTRUCTION_20),{_zz_decode_LEGAL_INSTRUCTION_21,_zz_decode_LEGAL_INSTRUCTION_22}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_18 = 32'hfe007fff; + assign _zz_decode_LEGAL_INSTRUCTION_19 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_decode_LEGAL_INSTRUCTION_20 = 32'h10200073; + assign _zz_decode_LEGAL_INSTRUCTION_21 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_decode_LEGAL_INSTRUCTION_22 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_1 = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_2 = (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_3 = (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_4 = (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_5 = (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]; + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_1 = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]; + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_2 = (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_3 = (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_4 = (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_5 = (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz__zz_decode_IS_RS2_SIGNED = 32'h10103050; + assign _zz__zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz__zz_decode_IS_RS2_SIGNED_2 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_3 = (((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_4) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_5 = ({_zz__zz_decode_IS_RS2_SIGNED_6,_zz__zz_decode_IS_RS2_SIGNED_7} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_8 = {(_zz__zz_decode_IS_RS2_SIGNED_9 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_10 != _zz__zz_decode_IS_RS2_SIGNED_15),{_zz__zz_decode_IS_RS2_SIGNED_16,{_zz__zz_decode_IS_RS2_SIGNED_18,_zz__zz_decode_IS_RS2_SIGNED_20}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_4 = 32'h02004074; + assign _zz__zz_decode_IS_RS2_SIGNED_6 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_7 = ((decode_INSTRUCTION & 32'h12203050) == 32'h10000050); + assign _zz__zz_decode_IS_RS2_SIGNED_9 = ((decode_INSTRUCTION & 32'h02103050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_10 = {(_zz__zz_decode_IS_RS2_SIGNED_11 == _zz__zz_decode_IS_RS2_SIGNED_12),(_zz__zz_decode_IS_RS2_SIGNED_13 == _zz__zz_decode_IS_RS2_SIGNED_14)}; + assign _zz__zz_decode_IS_RS2_SIGNED_15 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_16 = ({_zz_decode_IS_RS2_SIGNED_2,_zz__zz_decode_IS_RS2_SIGNED_17} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_18 = (_zz__zz_decode_IS_RS2_SIGNED_19 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_20 = {(_zz__zz_decode_IS_RS2_SIGNED_21 != _zz__zz_decode_IS_RS2_SIGNED_26),{_zz__zz_decode_IS_RS2_SIGNED_27,{_zz__zz_decode_IS_RS2_SIGNED_33,_zz__zz_decode_IS_RS2_SIGNED_35}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_11 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_IS_RS2_SIGNED_12 = 32'h00001050; + assign _zz__zz_decode_IS_RS2_SIGNED_13 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_IS_RS2_SIGNED_14 = 32'h00002050; + assign _zz__zz_decode_IS_RS2_SIGNED_17 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_19 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_21 = {(_zz__zz_decode_IS_RS2_SIGNED_22 == _zz__zz_decode_IS_RS2_SIGNED_23),(_zz__zz_decode_IS_RS2_SIGNED_24 == _zz__zz_decode_IS_RS2_SIGNED_25)}; + assign _zz__zz_decode_IS_RS2_SIGNED_26 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_27 = ({_zz__zz_decode_IS_RS2_SIGNED_28,{_zz__zz_decode_IS_RS2_SIGNED_29,_zz__zz_decode_IS_RS2_SIGNED_31}} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_33 = (_zz__zz_decode_IS_RS2_SIGNED_34 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_35 = {(_zz__zz_decode_IS_RS2_SIGNED_36 != _zz__zz_decode_IS_RS2_SIGNED_38),{_zz__zz_decode_IS_RS2_SIGNED_39,{_zz__zz_decode_IS_RS2_SIGNED_42,_zz__zz_decode_IS_RS2_SIGNED_43}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_22 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_RS2_SIGNED_23 = 32'h00005010; + assign _zz__zz_decode_IS_RS2_SIGNED_24 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_IS_RS2_SIGNED_25 = 32'h00005020; + assign _zz__zz_decode_IS_RS2_SIGNED_28 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_IS_RS2_SIGNED_29 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_30) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_31 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_32) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_34 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_36 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_37) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_38 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_39 = ({_zz__zz_decode_IS_RS2_SIGNED_40,_zz__zz_decode_IS_RS2_SIGNED_41} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_42 = (_zz_decode_IS_RS2_SIGNED_6 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_43 = {(_zz__zz_decode_IS_RS2_SIGNED_44 != _zz__zz_decode_IS_RS2_SIGNED_45),{_zz__zz_decode_IS_RS2_SIGNED_46,{_zz__zz_decode_IS_RS2_SIGNED_48,_zz__zz_decode_IS_RS2_SIGNED_51}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_30 = 32'h00007034; + assign _zz__zz_decode_IS_RS2_SIGNED_32 = 32'h02007054; + assign _zz__zz_decode_IS_RS2_SIGNED_37 = 32'h00003000; + assign _zz__zz_decode_IS_RS2_SIGNED_40 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_41 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_44 = _zz_decode_IS_RS2_SIGNED_6; + assign _zz__zz_decode_IS_RS2_SIGNED_45 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_46 = (((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_47) == 32'h00004008) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_48 = ((_zz__zz_decode_IS_RS2_SIGNED_49 == _zz__zz_decode_IS_RS2_SIGNED_50) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_51 = {({_zz__zz_decode_IS_RS2_SIGNED_52,_zz__zz_decode_IS_RS2_SIGNED_54} != 4'b0000),{(_zz__zz_decode_IS_RS2_SIGNED_61 != _zz__zz_decode_IS_RS2_SIGNED_63),{_zz__zz_decode_IS_RS2_SIGNED_64,{_zz__zz_decode_IS_RS2_SIGNED_67,_zz__zz_decode_IS_RS2_SIGNED_86}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_47 = 32'h00004048; + assign _zz__zz_decode_IS_RS2_SIGNED_49 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_IS_RS2_SIGNED_50 = 32'h00000024; + assign _zz__zz_decode_IS_RS2_SIGNED_52 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_53) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_54 = {(_zz__zz_decode_IS_RS2_SIGNED_55 == _zz__zz_decode_IS_RS2_SIGNED_56),{_zz__zz_decode_IS_RS2_SIGNED_57,_zz__zz_decode_IS_RS2_SIGNED_59}}; + assign _zz__zz_decode_IS_RS2_SIGNED_61 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_62) == 32'h00000008); + assign _zz__zz_decode_IS_RS2_SIGNED_63 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_64 = ((_zz__zz_decode_IS_RS2_SIGNED_65 == _zz__zz_decode_IS_RS2_SIGNED_66) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_67 = ({_zz__zz_decode_IS_RS2_SIGNED_68,_zz__zz_decode_IS_RS2_SIGNED_71} != 6'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_86 = {(_zz__zz_decode_IS_RS2_SIGNED_87 != _zz__zz_decode_IS_RS2_SIGNED_96),{_zz__zz_decode_IS_RS2_SIGNED_97,{_zz__zz_decode_IS_RS2_SIGNED_110,_zz__zz_decode_IS_RS2_SIGNED_125}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_53 = 32'h00000034; + assign _zz__zz_decode_IS_RS2_SIGNED_55 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_IS_RS2_SIGNED_56 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_57 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_58) == 32'h08000020); + assign _zz__zz_decode_IS_RS2_SIGNED_59 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_60) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_62 = 32'h10000008; + assign _zz__zz_decode_IS_RS2_SIGNED_65 = (decode_INSTRUCTION & 32'h10000008); + assign _zz__zz_decode_IS_RS2_SIGNED_66 = 32'h10000008; + assign _zz__zz_decode_IS_RS2_SIGNED_68 = (_zz__zz_decode_IS_RS2_SIGNED_69 == _zz__zz_decode_IS_RS2_SIGNED_70); + assign _zz__zz_decode_IS_RS2_SIGNED_71 = {_zz__zz_decode_IS_RS2_SIGNED_72,{_zz__zz_decode_IS_RS2_SIGNED_74,_zz__zz_decode_IS_RS2_SIGNED_77}}; + assign _zz__zz_decode_IS_RS2_SIGNED_87 = {_zz__zz_decode_IS_RS2_SIGNED_88,{_zz__zz_decode_IS_RS2_SIGNED_90,_zz__zz_decode_IS_RS2_SIGNED_93}}; + assign _zz__zz_decode_IS_RS2_SIGNED_96 = 3'b000; + assign _zz__zz_decode_IS_RS2_SIGNED_97 = ({_zz__zz_decode_IS_RS2_SIGNED_98,_zz__zz_decode_IS_RS2_SIGNED_101} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_110 = (_zz__zz_decode_IS_RS2_SIGNED_111 != _zz__zz_decode_IS_RS2_SIGNED_124); + assign _zz__zz_decode_IS_RS2_SIGNED_125 = {_zz__zz_decode_IS_RS2_SIGNED_126,{_zz__zz_decode_IS_RS2_SIGNED_143,_zz__zz_decode_IS_RS2_SIGNED_148}}; + assign _zz__zz_decode_IS_RS2_SIGNED_58 = 32'h08000070; + assign _zz__zz_decode_IS_RS2_SIGNED_60 = 32'h10000070; + assign _zz__zz_decode_IS_RS2_SIGNED_69 = (decode_INSTRUCTION & 32'h00002040); + assign _zz__zz_decode_IS_RS2_SIGNED_70 = 32'h00002040; + assign _zz__zz_decode_IS_RS2_SIGNED_72 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_73) == 32'h00001040); + assign _zz__zz_decode_IS_RS2_SIGNED_74 = (_zz__zz_decode_IS_RS2_SIGNED_75 == _zz__zz_decode_IS_RS2_SIGNED_76); + assign _zz__zz_decode_IS_RS2_SIGNED_77 = {_zz__zz_decode_IS_RS2_SIGNED_78,{_zz__zz_decode_IS_RS2_SIGNED_80,_zz__zz_decode_IS_RS2_SIGNED_83}}; + assign _zz__zz_decode_IS_RS2_SIGNED_88 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_89) == 32'h08000020); + assign _zz__zz_decode_IS_RS2_SIGNED_90 = (_zz__zz_decode_IS_RS2_SIGNED_91 == _zz__zz_decode_IS_RS2_SIGNED_92); + assign _zz__zz_decode_IS_RS2_SIGNED_93 = (_zz__zz_decode_IS_RS2_SIGNED_94 == _zz__zz_decode_IS_RS2_SIGNED_95); + assign _zz__zz_decode_IS_RS2_SIGNED_98 = (_zz__zz_decode_IS_RS2_SIGNED_99 == _zz__zz_decode_IS_RS2_SIGNED_100); + assign _zz__zz_decode_IS_RS2_SIGNED_101 = {_zz__zz_decode_IS_RS2_SIGNED_102,{_zz__zz_decode_IS_RS2_SIGNED_104,_zz__zz_decode_IS_RS2_SIGNED_107}}; + assign _zz__zz_decode_IS_RS2_SIGNED_111 = {_zz_decode_IS_RS2_SIGNED_5,{_zz__zz_decode_IS_RS2_SIGNED_112,_zz__zz_decode_IS_RS2_SIGNED_115}}; + assign _zz__zz_decode_IS_RS2_SIGNED_124 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_126 = ({_zz__zz_decode_IS_RS2_SIGNED_127,_zz__zz_decode_IS_RS2_SIGNED_128} != 7'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_143 = (_zz__zz_decode_IS_RS2_SIGNED_144 != _zz__zz_decode_IS_RS2_SIGNED_147); + assign _zz__zz_decode_IS_RS2_SIGNED_148 = {_zz__zz_decode_IS_RS2_SIGNED_149,{_zz__zz_decode_IS_RS2_SIGNED_154,_zz__zz_decode_IS_RS2_SIGNED_159}}; + assign _zz__zz_decode_IS_RS2_SIGNED_73 = 32'h00001040; + assign _zz__zz_decode_IS_RS2_SIGNED_75 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_76 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_78 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_79) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_80 = (_zz__zz_decode_IS_RS2_SIGNED_81 == _zz__zz_decode_IS_RS2_SIGNED_82); + assign _zz__zz_decode_IS_RS2_SIGNED_83 = (_zz__zz_decode_IS_RS2_SIGNED_84 == _zz__zz_decode_IS_RS2_SIGNED_85); + assign _zz__zz_decode_IS_RS2_SIGNED_89 = 32'h08000020; + assign _zz__zz_decode_IS_RS2_SIGNED_91 = (decode_INSTRUCTION & 32'h10000020); + assign _zz__zz_decode_IS_RS2_SIGNED_92 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_94 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_RS2_SIGNED_95 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_99 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_100 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_102 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_103) == 32'h00004020); + assign _zz__zz_decode_IS_RS2_SIGNED_104 = (_zz__zz_decode_IS_RS2_SIGNED_105 == _zz__zz_decode_IS_RS2_SIGNED_106); + assign _zz__zz_decode_IS_RS2_SIGNED_107 = {_zz_decode_IS_RS2_SIGNED_5,_zz__zz_decode_IS_RS2_SIGNED_108}; + assign _zz__zz_decode_IS_RS2_SIGNED_112 = (_zz__zz_decode_IS_RS2_SIGNED_113 == _zz__zz_decode_IS_RS2_SIGNED_114); + assign _zz__zz_decode_IS_RS2_SIGNED_115 = {_zz__zz_decode_IS_RS2_SIGNED_116,{_zz__zz_decode_IS_RS2_SIGNED_118,_zz__zz_decode_IS_RS2_SIGNED_121}}; + assign _zz__zz_decode_IS_RS2_SIGNED_127 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_128 = {_zz__zz_decode_IS_RS2_SIGNED_129,{_zz__zz_decode_IS_RS2_SIGNED_131,_zz__zz_decode_IS_RS2_SIGNED_134}}; + assign _zz__zz_decode_IS_RS2_SIGNED_144 = {_zz_decode_IS_RS2_SIGNED_4,_zz__zz_decode_IS_RS2_SIGNED_145}; + assign _zz__zz_decode_IS_RS2_SIGNED_147 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_149 = ({_zz__zz_decode_IS_RS2_SIGNED_150,_zz__zz_decode_IS_RS2_SIGNED_151} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_154 = (_zz__zz_decode_IS_RS2_SIGNED_155 != _zz__zz_decode_IS_RS2_SIGNED_158); + assign _zz__zz_decode_IS_RS2_SIGNED_159 = {_zz__zz_decode_IS_RS2_SIGNED_160,{_zz__zz_decode_IS_RS2_SIGNED_163,_zz__zz_decode_IS_RS2_SIGNED_176}}; + assign _zz__zz_decode_IS_RS2_SIGNED_79 = 32'h02100040; + assign _zz__zz_decode_IS_RS2_SIGNED_81 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_IS_RS2_SIGNED_82 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_84 = (decode_INSTRUCTION & 32'h18002008); + assign _zz__zz_decode_IS_RS2_SIGNED_85 = 32'h10002008; + assign _zz__zz_decode_IS_RS2_SIGNED_103 = 32'h00004020; + assign _zz__zz_decode_IS_RS2_SIGNED_105 = (decode_INSTRUCTION & 32'h00000030); + assign _zz__zz_decode_IS_RS2_SIGNED_106 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_108 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_109) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_113 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_IS_RS2_SIGNED_114 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_116 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_117) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_118 = (_zz__zz_decode_IS_RS2_SIGNED_119 == _zz__zz_decode_IS_RS2_SIGNED_120); + assign _zz__zz_decode_IS_RS2_SIGNED_121 = (_zz__zz_decode_IS_RS2_SIGNED_122 == _zz__zz_decode_IS_RS2_SIGNED_123); + assign _zz__zz_decode_IS_RS2_SIGNED_129 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_130) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_131 = (_zz__zz_decode_IS_RS2_SIGNED_132 == _zz__zz_decode_IS_RS2_SIGNED_133); + assign _zz__zz_decode_IS_RS2_SIGNED_134 = {_zz__zz_decode_IS_RS2_SIGNED_135,{_zz__zz_decode_IS_RS2_SIGNED_137,_zz__zz_decode_IS_RS2_SIGNED_140}}; + assign _zz__zz_decode_IS_RS2_SIGNED_145 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_146) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_150 = _zz_decode_IS_RS2_SIGNED_4; + assign _zz__zz_decode_IS_RS2_SIGNED_151 = (_zz__zz_decode_IS_RS2_SIGNED_152 == _zz__zz_decode_IS_RS2_SIGNED_153); + assign _zz__zz_decode_IS_RS2_SIGNED_155 = (_zz__zz_decode_IS_RS2_SIGNED_156 == _zz__zz_decode_IS_RS2_SIGNED_157); + assign _zz__zz_decode_IS_RS2_SIGNED_158 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_160 = (_zz__zz_decode_IS_RS2_SIGNED_161 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_163 = (_zz__zz_decode_IS_RS2_SIGNED_164 != _zz__zz_decode_IS_RS2_SIGNED_175); + assign _zz__zz_decode_IS_RS2_SIGNED_176 = {_zz__zz_decode_IS_RS2_SIGNED_177,{_zz__zz_decode_IS_RS2_SIGNED_182,_zz__zz_decode_IS_RS2_SIGNED_190}}; + assign _zz__zz_decode_IS_RS2_SIGNED_109 = 32'h02000028; + assign _zz__zz_decode_IS_RS2_SIGNED_117 = 32'h00001030; + assign _zz__zz_decode_IS_RS2_SIGNED_119 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_IS_RS2_SIGNED_120 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_122 = (decode_INSTRUCTION & 32'h02002068); + assign _zz__zz_decode_IS_RS2_SIGNED_123 = 32'h00002020; + assign _zz__zz_decode_IS_RS2_SIGNED_130 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_132 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_133 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_135 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_136) == 32'h00002008); + assign _zz__zz_decode_IS_RS2_SIGNED_137 = (_zz__zz_decode_IS_RS2_SIGNED_138 == _zz__zz_decode_IS_RS2_SIGNED_139); + assign _zz__zz_decode_IS_RS2_SIGNED_140 = {_zz_decode_IS_RS2_SIGNED_5,_zz__zz_decode_IS_RS2_SIGNED_141}; + assign _zz__zz_decode_IS_RS2_SIGNED_146 = 32'h00000070; + assign _zz__zz_decode_IS_RS2_SIGNED_152 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_153 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_156 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_IS_RS2_SIGNED_157 = 32'h00004010; + assign _zz__zz_decode_IS_RS2_SIGNED_161 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_162) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_164 = {_zz__zz_decode_IS_RS2_SIGNED_165,{_zz__zz_decode_IS_RS2_SIGNED_167,_zz__zz_decode_IS_RS2_SIGNED_170}}; + assign _zz__zz_decode_IS_RS2_SIGNED_175 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_177 = ({_zz__zz_decode_IS_RS2_SIGNED_178,_zz__zz_decode_IS_RS2_SIGNED_179} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_182 = (_zz__zz_decode_IS_RS2_SIGNED_183 != _zz__zz_decode_IS_RS2_SIGNED_189); + assign _zz__zz_decode_IS_RS2_SIGNED_190 = {_zz__zz_decode_IS_RS2_SIGNED_191,{_zz__zz_decode_IS_RS2_SIGNED_196,_zz__zz_decode_IS_RS2_SIGNED_201}}; + assign _zz__zz_decode_IS_RS2_SIGNED_136 = 32'h00002008; + assign _zz__zz_decode_IS_RS2_SIGNED_138 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_139 = 32'h00000010; + assign _zz__zz_decode_IS_RS2_SIGNED_141 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_142) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_162 = 32'h00006014; + assign _zz__zz_decode_IS_RS2_SIGNED_165 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_166) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_167 = (_zz__zz_decode_IS_RS2_SIGNED_168 == _zz__zz_decode_IS_RS2_SIGNED_169); + assign _zz__zz_decode_IS_RS2_SIGNED_170 = {_zz__zz_decode_IS_RS2_SIGNED_171,{_zz__zz_decode_IS_RS2_SIGNED_172,_zz__zz_decode_IS_RS2_SIGNED_174}}; + assign _zz__zz_decode_IS_RS2_SIGNED_178 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_179 = (_zz__zz_decode_IS_RS2_SIGNED_180 == _zz__zz_decode_IS_RS2_SIGNED_181); + assign _zz__zz_decode_IS_RS2_SIGNED_183 = {_zz__zz_decode_IS_RS2_SIGNED_184,{_zz__zz_decode_IS_RS2_SIGNED_185,_zz__zz_decode_IS_RS2_SIGNED_187}}; + assign _zz__zz_decode_IS_RS2_SIGNED_189 = 3'b000; + assign _zz__zz_decode_IS_RS2_SIGNED_191 = ({_zz__zz_decode_IS_RS2_SIGNED_192,_zz__zz_decode_IS_RS2_SIGNED_193} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_196 = (_zz__zz_decode_IS_RS2_SIGNED_197 != _zz__zz_decode_IS_RS2_SIGNED_200); + assign _zz__zz_decode_IS_RS2_SIGNED_201 = (_zz__zz_decode_IS_RS2_SIGNED_202 != _zz__zz_decode_IS_RS2_SIGNED_204); + assign _zz__zz_decode_IS_RS2_SIGNED_142 = 32'h00000028; + assign _zz__zz_decode_IS_RS2_SIGNED_166 = 32'h00000044; + assign _zz__zz_decode_IS_RS2_SIGNED_168 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_IS_RS2_SIGNED_169 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_171 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_172 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_173) == 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_174 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_180 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_IS_RS2_SIGNED_181 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_184 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_185 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_186) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_187 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_188) == 32'h40000030); + assign _zz__zz_decode_IS_RS2_SIGNED_192 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_193 = {_zz_decode_IS_RS2_SIGNED_1,(_zz__zz_decode_IS_RS2_SIGNED_194 == _zz__zz_decode_IS_RS2_SIGNED_195)}; + assign _zz__zz_decode_IS_RS2_SIGNED_197 = {_zz_decode_IS_RS2_SIGNED_1,(_zz__zz_decode_IS_RS2_SIGNED_198 == _zz__zz_decode_IS_RS2_SIGNED_199)}; + assign _zz__zz_decode_IS_RS2_SIGNED_200 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_202 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_203) == 32'h00001008); + assign _zz__zz_decode_IS_RS2_SIGNED_204 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_173 = 32'h00005004; + assign _zz__zz_decode_IS_RS2_SIGNED_186 = 32'h00002014; + assign _zz__zz_decode_IS_RS2_SIGNED_188 = 32'h40000034; + assign _zz__zz_decode_IS_RS2_SIGNED_194 = (decode_INSTRUCTION & 32'h00002014); + assign _zz__zz_decode_IS_RS2_SIGNED_195 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_198 = (decode_INSTRUCTION & 32'h0000004c); + assign _zz__zz_decode_IS_RS2_SIGNED_199 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_203 = 32'h00005048; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_208 ), //i - .io_cpu_prefetch_isValid (_zz_209 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_210 ), //i - .io_cpu_fetch_isStuck (_zz_211 ), //i - .io_cpu_fetch_isRemoved (_zz_212 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i - .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i - .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i - .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i - .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i - .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i - .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i - .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_213 ), //i - .io_cpu_decode_isStuck (_zz_214 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_215 ), //i - .io_cpu_fill_valid (_zz_216 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_174[2:0] ), //i - ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical ), //i + .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical ), //i + .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical ), //i + .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i + ._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_217 ), //i - .io_cpu_execute_address (_zz_218[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (_zz_219 ), //i - .io_cpu_execute_args_data (_zz_220[31:0] ), //i - .io_cpu_execute_args_size (_zz_221[1:0] ), //i - .io_cpu_execute_args_isLrsc (_zz_222 ), //i - .io_cpu_execute_args_isAmo (_zz_223 ), //i - .io_cpu_execute_args_amoCtrl_swap (_zz_224 ), //i - .io_cpu_execute_args_amoCtrl_alu (_zz_225[2:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_226 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_227[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_228 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i - .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i - .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i - .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i - .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i - .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i - .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i - .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i - .io_cpu_writeBack_isValid (_zz_229 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_230 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_231[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_232 ), //i - .io_cpu_writeBack_fence_SR (_zz_233 ), //i - .io_cpu_writeBack_fence_SO (_zz_234 ), //i - .io_cpu_writeBack_fence_SI (_zz_235 ), //i - .io_cpu_writeBack_fence_PW (_zz_236 ), //i - .io_cpu_writeBack_fence_PR (_zz_237 ), //i - .io_cpu_writeBack_fence_PO (_zz_238 ), //i - .io_cpu_writeBack_fence_PI (_zz_239 ), //i - .io_cpu_writeBack_fence_FM (_zz_240[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_241 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_242 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (dataCache_1_io_cpu_execute_args_wr ), //i + .io_cpu_execute_args_size (dataCache_1_io_cpu_execute_args_size ), //i + .io_cpu_execute_args_isLrsc (dataCache_1_io_cpu_execute_args_isLrsc ), //i + .io_cpu_execute_args_isAmo (execute_MEMORY_AMO ), //i + .io_cpu_execute_args_amoCtrl_swap (dataCache_1_io_cpu_execute_args_amoCtrl_swap ), //i + .io_cpu_execute_args_amoCtrl_alu (dataCache_1_io_cpu_execute_args_amoCtrl_alu ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical ), //i + .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical ), //i + .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical ), //i + .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_480) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_7) 3'b000 : begin - _zz_245 = DBusCachedPlugin_redoBranch_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = DBusCachedPlugin_redoBranch_payload; end 3'b001 : begin - _zz_245 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = CsrPlugin_jumpInterface_payload; end 3'b010 : begin - _zz_245 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = BranchPlugin_jumpInterface_payload; end 3'b011 : begin - _zz_245 = CsrPlugin_redoInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = CsrPlugin_redoInterface_payload; end default : begin - _zz_245 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end always @(*) begin - case(_zz_93) + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) 2'b00 : begin - _zz_246 = MmuPlugin_ports_0_cache_0_valid; - _zz_247 = MmuPlugin_ports_0_cache_0_exception; - _zz_248 = MmuPlugin_ports_0_cache_0_superPage; - _zz_249 = MmuPlugin_ports_0_cache_0_virtualAddress_0; - _zz_250 = MmuPlugin_ports_0_cache_0_virtualAddress_1; - _zz_251 = MmuPlugin_ports_0_cache_0_physicalAddress_0; - _zz_252 = MmuPlugin_ports_0_cache_0_physicalAddress_1; - _zz_253 = MmuPlugin_ports_0_cache_0_allowRead; - _zz_254 = MmuPlugin_ports_0_cache_0_allowWrite; - _zz_255 = MmuPlugin_ports_0_cache_0_allowExecute; - _zz_256 = MmuPlugin_ports_0_cache_0_allowUser; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; end 2'b01 : begin - _zz_246 = MmuPlugin_ports_0_cache_1_valid; - _zz_247 = MmuPlugin_ports_0_cache_1_exception; - _zz_248 = MmuPlugin_ports_0_cache_1_superPage; - _zz_249 = MmuPlugin_ports_0_cache_1_virtualAddress_0; - _zz_250 = MmuPlugin_ports_0_cache_1_virtualAddress_1; - _zz_251 = MmuPlugin_ports_0_cache_1_physicalAddress_0; - _zz_252 = MmuPlugin_ports_0_cache_1_physicalAddress_1; - _zz_253 = MmuPlugin_ports_0_cache_1_allowRead; - _zz_254 = MmuPlugin_ports_0_cache_1_allowWrite; - _zz_255 = MmuPlugin_ports_0_cache_1_allowExecute; - _zz_256 = MmuPlugin_ports_0_cache_1_allowUser; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; end 2'b10 : begin - _zz_246 = MmuPlugin_ports_0_cache_2_valid; - _zz_247 = MmuPlugin_ports_0_cache_2_exception; - _zz_248 = MmuPlugin_ports_0_cache_2_superPage; - _zz_249 = MmuPlugin_ports_0_cache_2_virtualAddress_0; - _zz_250 = MmuPlugin_ports_0_cache_2_virtualAddress_1; - _zz_251 = MmuPlugin_ports_0_cache_2_physicalAddress_0; - _zz_252 = MmuPlugin_ports_0_cache_2_physicalAddress_1; - _zz_253 = MmuPlugin_ports_0_cache_2_allowRead; - _zz_254 = MmuPlugin_ports_0_cache_2_allowWrite; - _zz_255 = MmuPlugin_ports_0_cache_2_allowExecute; - _zz_256 = MmuPlugin_ports_0_cache_2_allowUser; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; end default : begin - _zz_246 = MmuPlugin_ports_0_cache_3_valid; - _zz_247 = MmuPlugin_ports_0_cache_3_exception; - _zz_248 = MmuPlugin_ports_0_cache_3_superPage; - _zz_249 = MmuPlugin_ports_0_cache_3_virtualAddress_0; - _zz_250 = MmuPlugin_ports_0_cache_3_virtualAddress_1; - _zz_251 = MmuPlugin_ports_0_cache_3_physicalAddress_0; - _zz_252 = MmuPlugin_ports_0_cache_3_physicalAddress_1; - _zz_253 = MmuPlugin_ports_0_cache_3_allowRead; - _zz_254 = MmuPlugin_ports_0_cache_3_allowWrite; - _zz_255 = MmuPlugin_ports_0_cache_3_allowExecute; - _zz_256 = MmuPlugin_ports_0_cache_3_allowUser; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end always @(*) begin - case(_zz_97) + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_MmuPlugin_ports_0_cacheLine_valid_3) 2'b00 : begin - _zz_257 = MmuPlugin_ports_1_cache_0_valid; - _zz_258 = MmuPlugin_ports_1_cache_0_exception; - _zz_259 = MmuPlugin_ports_1_cache_0_superPage; - _zz_260 = MmuPlugin_ports_1_cache_0_virtualAddress_0; - _zz_261 = MmuPlugin_ports_1_cache_0_virtualAddress_1; - _zz_262 = MmuPlugin_ports_1_cache_0_physicalAddress_0; - _zz_263 = MmuPlugin_ports_1_cache_0_physicalAddress_1; - _zz_264 = MmuPlugin_ports_1_cache_0_allowRead; - _zz_265 = MmuPlugin_ports_1_cache_0_allowWrite; - _zz_266 = MmuPlugin_ports_1_cache_0_allowExecute; - _zz_267 = MmuPlugin_ports_1_cache_0_allowUser; + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_0_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_0_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_0_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_0_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_0_allowUser; end 2'b01 : begin - _zz_257 = MmuPlugin_ports_1_cache_1_valid; - _zz_258 = MmuPlugin_ports_1_cache_1_exception; - _zz_259 = MmuPlugin_ports_1_cache_1_superPage; - _zz_260 = MmuPlugin_ports_1_cache_1_virtualAddress_0; - _zz_261 = MmuPlugin_ports_1_cache_1_virtualAddress_1; - _zz_262 = MmuPlugin_ports_1_cache_1_physicalAddress_0; - _zz_263 = MmuPlugin_ports_1_cache_1_physicalAddress_1; - _zz_264 = MmuPlugin_ports_1_cache_1_allowRead; - _zz_265 = MmuPlugin_ports_1_cache_1_allowWrite; - _zz_266 = MmuPlugin_ports_1_cache_1_allowExecute; - _zz_267 = MmuPlugin_ports_1_cache_1_allowUser; + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_1_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_1_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_1_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_1_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_1_allowUser; end 2'b10 : begin - _zz_257 = MmuPlugin_ports_1_cache_2_valid; - _zz_258 = MmuPlugin_ports_1_cache_2_exception; - _zz_259 = MmuPlugin_ports_1_cache_2_superPage; - _zz_260 = MmuPlugin_ports_1_cache_2_virtualAddress_0; - _zz_261 = MmuPlugin_ports_1_cache_2_virtualAddress_1; - _zz_262 = MmuPlugin_ports_1_cache_2_physicalAddress_0; - _zz_263 = MmuPlugin_ports_1_cache_2_physicalAddress_1; - _zz_264 = MmuPlugin_ports_1_cache_2_allowRead; - _zz_265 = MmuPlugin_ports_1_cache_2_allowWrite; - _zz_266 = MmuPlugin_ports_1_cache_2_allowExecute; - _zz_267 = MmuPlugin_ports_1_cache_2_allowUser; + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_2_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_2_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_2_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_2_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_2_allowUser; end default : begin - _zz_257 = MmuPlugin_ports_1_cache_3_valid; - _zz_258 = MmuPlugin_ports_1_cache_3_exception; - _zz_259 = MmuPlugin_ports_1_cache_3_superPage; - _zz_260 = MmuPlugin_ports_1_cache_3_virtualAddress_0; - _zz_261 = MmuPlugin_ports_1_cache_3_virtualAddress_1; - _zz_262 = MmuPlugin_ports_1_cache_3_physicalAddress_0; - _zz_263 = MmuPlugin_ports_1_cache_3_physicalAddress_1; - _zz_264 = MmuPlugin_ports_1_cache_3_allowRead; - _zz_265 = MmuPlugin_ports_1_cache_3_allowWrite; - _zz_266 = MmuPlugin_ports_1_cache_3_allowExecute; - _zz_267 = MmuPlugin_ports_1_cache_3_allowUser; + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_3_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_3_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_3_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_3_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_3_allowUser; + end + endcase + end + + always @(*) begin + case(_zz_MmuPlugin_ports_1_cacheLine_valid_3) + 2'b00 : begin + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_0_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_0_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_0_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_0_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_0_allowUser; + end + 2'b01 : begin + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_1_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_1_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_1_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_1_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_1_allowUser; + end + 2'b10 : begin + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_2_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_2_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_2_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_2_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_2_allowUser; + end + default : begin + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_3_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_3_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_3_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_3_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_3_allowUser; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_27_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_30) - `BranchCtrlEnum_defaultEncoding_INC : _zz_30_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_30_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_30_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_30_string = "JALR"; - default : _zz_30_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_33) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_33_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_33_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_33_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_33_string = "SRA_1 "; - default : _zz_33_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_34) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; - default : _zz_34_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_36) - `Src2CtrlEnum_defaultEncoding_RS : _zz_36_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_36_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_36_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_36_string = "PC "; - default : _zz_36_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_37) - `Src1CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_37_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_37_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_37_string = "URS1 "; - default : _zz_37_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_38) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_38_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_38_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_38_string = "BITWISE "; - default : _zz_38_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_39) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39_string = "AND_1"; - default : _zz_39_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_43) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_43_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_43_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_43_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_43_string = "ECALL"; - default : _zz_43_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `BranchCtrlEnum_defaultEncoding_INC : _zz_44_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_44_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_44_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_44_string = "JALR"; - default : _zz_44_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_45) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_45_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_45_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_45_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_45_string = "SRA_1 "; - default : _zz_45_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_46) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_46_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_46_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_46_string = "AND_1"; - default : _zz_46_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_47) - `Src2CtrlEnum_defaultEncoding_RS : _zz_47_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_47_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_47_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_47_string = "PC "; - default : _zz_47_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_48) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_48_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_48_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_48_string = "BITWISE "; - default : _zz_48_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_49) - `Src1CtrlEnum_defaultEncoding_RS : _zz_49_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_49_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_49_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_49_string = "URS1 "; - default : _zz_49_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_52) - `BranchCtrlEnum_defaultEncoding_INC : _zz_52_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_52_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_52_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_52_string = "JALR"; - default : _zz_52_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; + `MmuPlugin_shared_State_binary_sequential_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; + `MmuPlugin_shared_State_binary_sequential_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; + `MmuPlugin_shared_State_binary_sequential_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; + `MmuPlugin_shared_State_binary_sequential_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; + `MmuPlugin_shared_State_binary_sequential_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; default : MmuPlugin_shared_state_1_string = "??????"; endcase end always @(*) begin - case(_zz_111) - `Src1CtrlEnum_defaultEncoding_RS : _zz_111_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_111_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_111_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_111_string = "URS1 "; - default : _zz_111_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_112) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_112_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_112_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_112_string = "BITWISE "; - default : _zz_112_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_113) - `Src2CtrlEnum_defaultEncoding_RS : _zz_113_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_113_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_113_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_113_string = "PC "; - default : _zz_113_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_114) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_114_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_114_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_114_string = "AND_1"; - default : _zz_114_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_115) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_115_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_115_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_115_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_115_string = "SRA_1 "; - default : _zz_115_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_116) - `BranchCtrlEnum_defaultEncoding_INC : _zz_116_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_116_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_116_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_116_string = "JALR"; - default : _zz_116_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_117) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_117_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_117_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_117_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_117_string = "ECALL"; - default : _zz_117_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_330) + $signed(_zz_338)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); @@ -3178,57 +3233,57 @@ module VexRiscv ( assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); - assign execute_SHIFT_RIGHT = _zz_340; - assign execute_REGFILE_WRITE_DATA = _zz_119; - assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_218[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign execute_IS_DBUS_SHARING = MmuPlugin_dBusAccess_cmd_fire; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_342[0]; - assign decode_IS_RS1_SIGNED = _zz_343[0]; - assign decode_IS_DIV = _zz_344[0]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_RS2_SIGNED[35]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_RS2_SIGNED[34]; + assign decode_IS_DIV = _zz_decode_IS_RS2_SIGNED[33]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_345[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_346[0]; - assign _zz_8 = _zz_9; - assign _zz_10 = _zz_11; - assign decode_SHIFT_CTRL = _zz_12; - assign _zz_13 = _zz_14; - assign decode_ALU_BITWISE_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_SRC_LESS_UNSIGNED = _zz_347[0]; - assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; - assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; - assign decode_IS_SFENCE_VMA = _zz_348[0]; - assign decode_MEMORY_MANAGMENT = _zz_349[0]; + assign decode_IS_MUL = _zz_decode_IS_RS2_SIGNED[32]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_RS2_SIGNED[29]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_RS2_SIGNED[22]; + assign decode_IS_SFENCE_VMA = _zz_decode_IS_RS2_SIGNED[21]; + assign decode_IS_SFENCE_VMA2 = _zz_decode_IS_RS2_SIGNED[20]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_RS2_SIGNED[19]; + assign memory_MEMORY_LRSC = execute_to_memory_MEMORY_LRSC; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_350[0]; + assign decode_MEMORY_WR = _zz_decode_IS_RS2_SIGNED[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_351[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_352[0]; - assign decode_SRC2_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_ALU_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_SRC1_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_51; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_RS2_SIGNED[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_RS2_SIGNED[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_decode_MEMORY_FORCE_CONSTISTENCY; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_353[0]; + assign decode_IS_EBREAK = _zz_decode_IS_RS2_SIGNED[36]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -3242,25 +3297,26 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_27; - assign execute_ENV_CTRL = _zz_28; - assign writeBack_ENV_CTRL = _zz_29; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; + assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_141; - assign execute_BRANCH_CTRL = _zz_30; - assign decode_RS2_USE = _zz_354[0]; - assign decode_RS1_USE = _zz_355[0]; - always @ (*) begin - _zz_31 = execute_REGFILE_WRITE_DATA; - if(_zz_268)begin - _zz_31 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_RS2_SIGNED[17]; + assign decode_RS1_USE = _zz_decode_IS_RS2_SIGNED[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end - if(DBusCachedPlugin_forceDatapath)begin - _zz_31 = MmuPlugin_dBusAccess_cmd_payload_address; + if(DBusCachedPlugin_forceDatapath) begin + _zz_decode_RS2 = MmuPlugin_dBusAccess_cmd_payload_address; end end @@ -3270,148 +3326,165 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_130)begin - if((_zz_131 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_132; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_269)begin - if(_zz_270)begin - if(_zz_134)begin - decode_RS2 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_271)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_136)begin - decode_RS2 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_272)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_138)begin - decode_RS2 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_130)begin - if((_zz_131 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_132; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_269)begin - if(_zz_270)begin - if(_zz_133)begin - decode_RS1 = _zz_50; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_271)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_135)begin - decode_RS1 = _zz_32; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_272)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_137)begin - decode_RS1 = _zz_31; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_32 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_32 = _zz_127; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_32 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_273)begin - _zz_32 = memory_DivPlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_33; - assign execute_SHIFT_CTRL = _zz_34; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_35 = execute_PC; - assign execute_SRC2_CTRL = _zz_36; - assign execute_SRC1_CTRL = _zz_37; - assign decode_SRC_USE_SUB_LESS = _zz_356[0]; - assign decode_SRC_ADD_ZERO = _zz_357[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_RS2_SIGNED[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_RS2_SIGNED[18]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_38; - assign execute_SRC2 = _zz_125; - assign execute_SRC1 = _zz_120; - assign execute_ALU_BITWISE_CTRL = _zz_39; - assign _zz_40 = writeBack_INSTRUCTION; - assign _zz_41 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_42 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_42 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_358[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_RS2_SIGNED[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_481) == 32'h00001073),{(_zz_482 == _zz_483),{_zz_484,{_zz_485,_zz_486}}}}}}} != 25'h0); - assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 25'h0); + assign execute_IS_SFENCE_VMA2 = decode_to_execute_IS_SFENCE_VMA2; assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; - always @ (*) begin - _zz_50 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_50 = writeBack_DBusCachedPlugin_rspFormated; + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_329) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_50 = _zz_415; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_50 = _zz_416; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_LRSC = memory_to_writeBack_MEMORY_LRSC; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; - assign execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + always @(*) begin + execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + execute_MEMORY_AMO = 1'b0; + end + end + end + + always @(*) begin + execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + execute_MEMORY_LRSC = 1'b0; + end + end + end + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; @@ -3419,70 +3492,70 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_AMO = _zz_359[0]; - assign decode_MEMORY_LRSC = _zz_360[0]; - assign decode_MEMORY_ENABLE = _zz_361[0]; - assign decode_FLUSH_ALL = _zz_362[0]; - always @ (*) begin + assign decode_MEMORY_AMO = _zz_decode_IS_RS2_SIGNED[16]; + assign decode_MEMORY_LRSC = _zz_decode_IS_RS2_SIGNED[15]; + assign decode_MEMORY_ENABLE = _zz_decode_IS_RS2_SIGNED[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_RS2_SIGNED[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_274)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_275)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_276)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_277)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_52; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_53 = execute_FORMAL_PC_NEXT; - if(CsrPlugin_redoInterface_valid)begin - _zz_53 = CsrPlugin_redoInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(CsrPlugin_redoInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = CsrPlugin_redoInterface_payload; end end - always @ (*) begin - _zz_54 = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_54 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_55 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_55 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end - case(_zz_174) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -3491,174 +3564,175 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if(MmuPlugin_dBusAccess_cmd_valid)begin + if(MmuPlugin_dBusAccess_cmd_valid) begin decode_arbitration_haltByOther = 1'b1; end - if((decode_arbitration_isValid && (_zz_128 || _zz_129)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(CsrPlugin_pipelineLiberator_active) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_278)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_278)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_241 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_279)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_268)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_280)begin + if(when_DebugPlugin_l284) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_280)begin - if(_zz_281)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushIt = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_280)begin - if(_zz_281)begin - execute_arbitration_flushNext = 1'b1; - end + if(CsrPlugin_selfException_valid) begin + execute_arbitration_flushNext = 1'b1; end - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeInstruction)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushNext = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_273)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_282)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_283)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3667,75 +3741,77 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_282)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_283)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_280)begin - if(_zz_281)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_284)begin + if(when_DebugPlugin_l300) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin - _zz_56 = 1'b0; - if(DebugPlugin_godmode)begin - _zz_56 = 1'b1; + always @(*) begin + _zz_when_DBusCachedPlugin_l386 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l386 = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_279)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin CsrPlugin_thirdPartyWake = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_282)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_283)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_282)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_283)begin - case(_zz_285) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3748,81 +3824,93 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_forceMachineWire = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + if(when_DebugPlugin_l316) begin CsrPlugin_allowInterrupts = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_allowException = 1'b0; end end + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}}} != 5'h0); - assign _zz_57 = {IBusCachedPlugin_predictionJumpInterface_valid,{CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; - assign _zz_58 = (_zz_57 & (~ _zz_363)); - assign _zz_59 = _zz_58[3]; - assign _zz_60 = _zz_58[4]; - assign _zz_61 = (_zz_58[1] || _zz_59); - assign _zz_62 = (_zz_58[2] || _zz_59); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_245; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[4]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_365); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3830,66 +3918,75 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_63 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_63); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_63); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_64 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_64); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_64); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_65 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_65); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_65); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_66; - assign _zz_66 = ((1'b0 && (! _zz_67)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_67 = _zz_68; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_67; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_69)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_69 = _zz_70; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_69; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_71; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); - always @ (*) begin + always @(*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_174) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3901,207 +3998,219 @@ module VexRiscv ( endcase end - assign _zz_72 = _zz_366[11]; - always @ (*) begin - _zz_73[18] = _zz_72; - _zz_73[17] = _zz_72; - _zz_73[16] = _zz_72; - _zz_73[15] = _zz_72; - _zz_73[14] = _zz_72; - _zz_73[13] = _zz_72; - _zz_73[12] = _zz_72; - _zz_73[11] = _zz_72; - _zz_73[10] = _zz_72; - _zz_73[9] = _zz_72; - _zz_73[8] = _zz_72; - _zz_73[7] = _zz_72; - _zz_73[6] = _zz_72; - _zz_73[5] = _zz_72; - _zz_73[4] = _zz_72; - _zz_73[3] = _zz_72; - _zz_73[2] = _zz_72; - _zz_73[1] = _zz_72; - _zz_73[0] = _zz_72; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_367[31])); - if(_zz_78)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_74 = _zz_368[19]; - always @ (*) begin - _zz_75[10] = _zz_74; - _zz_75[9] = _zz_74; - _zz_75[8] = _zz_74; - _zz_75[7] = _zz_74; - _zz_75[6] = _zz_74; - _zz_75[5] = _zz_74; - _zz_75[4] = _zz_74; - _zz_75[3] = _zz_74; - _zz_75[2] = _zz_74; - _zz_75[1] = _zz_74; - _zz_75[0] = _zz_74; - end - - assign _zz_76 = _zz_369[11]; - always @ (*) begin - _zz_77[18] = _zz_76; - _zz_77[17] = _zz_76; - _zz_77[16] = _zz_76; - _zz_77[15] = _zz_76; - _zz_77[14] = _zz_76; - _zz_77[13] = _zz_76; - _zz_77[12] = _zz_76; - _zz_77[11] = _zz_76; - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7] = _zz_76; - _zz_77[6] = _zz_76; - _zz_77[5] = _zz_76; - _zz_77[4] = _zz_76; - _zz_77[3] = _zz_76; - _zz_77[2] = _zz_76; - _zz_77[1] = _zz_76; - _zz_77[0] = _zz_76; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_78 = _zz_370[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_78 = _zz_371[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_79 = _zz_372[19]; - always @ (*) begin - _zz_80[10] = _zz_79; - _zz_80[9] = _zz_79; - _zz_80[8] = _zz_79; - _zz_80[7] = _zz_79; - _zz_80[6] = _zz_79; - _zz_80[5] = _zz_79; - _zz_80[4] = _zz_79; - _zz_80[3] = _zz_79; - _zz_80[2] = _zz_79; - _zz_80[1] = _zz_79; - _zz_80[0] = _zz_79; - end - - assign _zz_81 = _zz_373[11]; - always @ (*) begin - _zz_82[18] = _zz_81; - _zz_82[17] = _zz_81; - _zz_82[16] = _zz_81; - _zz_82[15] = _zz_81; - _zz_82[14] = _zz_81; - _zz_82[13] = _zz_81; - _zz_82[12] = _zz_81; - _zz_82[11] = _zz_81; - _zz_82[10] = _zz_81; - _zz_82[9] = _zz_81; - _zz_82[8] = _zz_81; - _zz_82[7] = _zz_81; - _zz_82[6] = _zz_81; - _zz_82[5] = _zz_81; - _zz_82[4] = _zz_81; - _zz_82[3] = _zz_81; - _zz_82[2] = _zz_81; - _zz_82[1] = _zz_81; - _zz_82[0] = _zz_81; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_80,{{{_zz_504,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_82,{{{_zz_505,_zz_506},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_209 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_210 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_211 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_210; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_213 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_214 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_215 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_277)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_275)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_216 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_275)begin - _zz_216 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_276)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_274)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_276)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_274)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_208 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_242 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -4109,328 +4218,320 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - always @ (*) begin - _zz_51 = 1'b0; - if(decode_INSTRUCTION[25])begin - if(decode_MEMORY_LRSC)begin - _zz_51 = 1'b1; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + always @(*) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + if(when_DBusCachedPlugin_l311) begin + if(decode_MEMORY_LRSC) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b1; end - if(decode_MEMORY_AMO)begin - _zz_51 = 1'b1; + if(decode_MEMORY_AMO) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b1; end end end + assign when_DBusCachedPlugin_l311 = decode_INSTRUCTION[25]; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin - _zz_217 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_286)begin - if(_zz_287)begin - _zz_217 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + if(when_DBusCachedPlugin_l499) begin + dataCache_1_io_cpu_execute_isValid = 1'b1; end end end end - always @ (*) begin - _zz_218 = execute_SRC_ADD; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_286)begin - _zz_218 = MmuPlugin_dBusAccess_cmd_payload_address; + always @(*) begin + dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_address = MmuPlugin_dBusAccess_cmd_payload_address; end end end - always @ (*) begin - _zz_219 = execute_MEMORY_WR; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_286)begin - _zz_219 = MmuPlugin_dBusAccess_cmd_payload_write; + always @(*) begin + dataCache_1_io_cpu_execute_args_wr = execute_MEMORY_WR; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_args_wr = 1'b0; end end end - always @ (*) begin + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_85 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_85 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_85 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - always @ (*) begin - _zz_220 = _zz_85; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_286)begin - _zz_220 = MmuPlugin_dBusAccess_cmd_payload_data; - end - end - end - - always @ (*) begin - _zz_221 = execute_DBusCachedPlugin_size; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_286)begin - _zz_221 = MmuPlugin_dBusAccess_cmd_payload_size; - end - end - end - - assign _zz_241 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - always @ (*) begin - _zz_222 = 1'b0; - if(execute_MEMORY_LRSC)begin - _zz_222 = 1'b1; - end - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_286)begin - _zz_222 = 1'b0; + always @(*) begin + dataCache_1_io_cpu_execute_args_size = execute_DBusCachedPlugin_size; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_args_size = MmuPlugin_dBusAccess_cmd_payload_size; end end end - always @ (*) begin - _zz_223 = execute_MEMORY_AMO; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_286)begin - _zz_223 = 1'b0; - end + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + always @(*) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b0; + if(execute_MEMORY_LRSC) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b1; end end - assign _zz_225 = execute_INSTRUCTION[31 : 29]; - assign _zz_224 = execute_INSTRUCTION[27]; - always @ (*) begin - _zz_226 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - if(memory_IS_DBUS_SHARING)begin - _zz_226 = 1'b1; + assign dataCache_1_io_cpu_execute_args_amoCtrl_alu = execute_INSTRUCTION[31 : 29]; + assign dataCache_1_io_cpu_execute_args_amoCtrl_swap = execute_INSTRUCTION[27]; + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + always @(*) begin + dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + if(memory_IS_DBUS_SHARING) begin + dataCache_1_io_cpu_memory_isValid = 1'b1; end end - assign _zz_227 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_226; + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_227; - always @ (*) begin + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; + always @(*) begin DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - if(memory_IS_DBUS_SHARING)begin + if(memory_IS_DBUS_SHARING) begin DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; end end assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_228 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_56 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_228 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; end end - always @ (*) begin - _zz_229 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - if(writeBack_IS_DBUS_SHARING)begin - _zz_229 = 1'b1; + assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_IS_DBUS_SHARING) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b1; + end + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_230 = (CsrPlugin_privilege == 2'b00); - assign _zz_231 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_288)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_288)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_288)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_374}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_375}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + always @(*) begin + writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + if(when_DBusCachedPlugin_l474) begin + writeBack_DBusCachedPlugin_rspRf = {31'd0, _zz_writeBack_DBusCachedPlugin_rspRf}; + end end - assign _zz_86 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_87[31] = _zz_86; - _zz_87[30] = _zz_86; - _zz_87[29] = _zz_86; - _zz_87[28] = _zz_86; - _zz_87[27] = _zz_86; - _zz_87[26] = _zz_86; - _zz_87[25] = _zz_86; - _zz_87[24] = _zz_86; - _zz_87[23] = _zz_86; - _zz_87[22] = _zz_86; - _zz_87[21] = _zz_86; - _zz_87[20] = _zz_86; - _zz_87[19] = _zz_86; - _zz_87[18] = _zz_86; - _zz_87[17] = _zz_86; - _zz_87[16] = _zz_86; - _zz_87[15] = _zz_86; - _zz_87[14] = _zz_86; - _zz_87[13] = _zz_86; - _zz_87[12] = _zz_86; - _zz_87[11] = _zz_86; - _zz_87[10] = _zz_86; - _zz_87[9] = _zz_86; - _zz_87[8] = _zz_86; - _zz_87[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_88 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_89[31] = _zz_88; - _zz_89[30] = _zz_88; - _zz_89[29] = _zz_88; - _zz_89[28] = _zz_88; - _zz_89[27] = _zz_88; - _zz_89[26] = _zz_88; - _zz_89[25] = _zz_88; - _zz_89[24] = _zz_88; - _zz_89[23] = _zz_88; - _zz_89[22] = _zz_88; - _zz_89[21] = _zz_88; - _zz_89[20] = _zz_88; - _zz_89[19] = _zz_88; - _zz_89[18] = _zz_88; - _zz_89[17] = _zz_88; - _zz_89[16] = _zz_88; - _zz_89[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_327) + assign when_DBusCachedPlugin_l474 = (writeBack_MEMORY_LRSC && writeBack_MEMORY_WR); + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_87; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_89; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end - always @ (*) begin + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + always @(*) begin MmuPlugin_dBusAccess_cmd_ready = 1'b0; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_286)begin - if(_zz_287)begin + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + if(when_DBusCachedPlugin_l499) begin MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); end end end end - always @ (*) begin + always @(*) begin DBusCachedPlugin_forceDatapath = 1'b0; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_286)begin + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin DBusCachedPlugin_forceDatapath = 1'b1; end end end + assign when_DBusCachedPlugin_l498 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign when_DBusCachedPlugin_l499 = (! dataCache_1_io_cpu_execute_refilling); + assign MmuPlugin_dBusAccess_cmd_fire = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); - assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1_io_cpu_writeBack_data; + assign MmuPlugin_dBusAccess_rsp_payload_data = writeBack_DBusCachedPlugin_rspRf; assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; assign MmuPlugin_ports_0_dirty = 1'b0; - always @ (*) begin + always @(*) begin MmuPlugin_ports_0_requireMmuLockupCalc = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + if(when_MmuPlugin_l125) begin MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; end - if((CsrPlugin_privilege == 2'b11))begin + if(when_MmuPlugin_l126) begin MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; end end - always @ (*) begin - MmuPlugin_ports_0_cacheHitsCalc[0] = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_0_cacheHitsCalc[1] = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_0_cacheHitsCalc[2] = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_0_cacheHitsCalc[3] = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - end - + assign when_MmuPlugin_l125 = ((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)); + assign when_MmuPlugin_l126 = (CsrPlugin_privilege == 2'b11); + assign MmuPlugin_ports_0_cacheHitsCalc = {((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))),{((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == _zz_MmuPlugin_ports_0_cacheHitsCalc)) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == _zz_MmuPlugin_ports_0_cacheHitsCalc_1))),{((MmuPlugin_ports_0_cache_1_valid && _zz_MmuPlugin_ports_0_cacheHitsCalc_2) && (MmuPlugin_ports_0_cache_1_superPage || _zz_MmuPlugin_ports_0_cacheHitsCalc_3)),((MmuPlugin_ports_0_cache_0_valid && _zz_MmuPlugin_ports_0_cacheHitsCalc_4) && (MmuPlugin_ports_0_cache_0_superPage || _zz_MmuPlugin_ports_0_cacheHitsCalc_5))}}}; assign MmuPlugin_ports_0_cacheHit = (MmuPlugin_ports_0_cacheHitsCalc != 4'b0000); - assign _zz_90 = MmuPlugin_ports_0_cacheHitsCalc[3]; - assign _zz_91 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_90); - assign _zz_92 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_90); - assign _zz_93 = {_zz_92,_zz_91}; - assign MmuPlugin_ports_0_cacheLine_valid = _zz_246; - assign MmuPlugin_ports_0_cacheLine_exception = _zz_247; - assign MmuPlugin_ports_0_cacheLine_superPage = _zz_248; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_249; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_250; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_251; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_252; - assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_253; - assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_254; - assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_255; - assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_256; - always @ (*) begin + assign _zz_MmuPlugin_ports_0_cacheLine_valid = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign _zz_MmuPlugin_ports_0_cacheLine_valid_1 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_MmuPlugin_ports_0_cacheLine_valid); + assign _zz_MmuPlugin_ports_0_cacheLine_valid_2 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_MmuPlugin_ports_0_cacheLine_valid); + assign _zz_MmuPlugin_ports_0_cacheLine_valid_3 = {_zz_MmuPlugin_ports_0_cacheLine_valid_2,_zz_MmuPlugin_ports_0_cacheLine_valid_1}; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_MmuPlugin_ports_0_cacheLine_valid_4; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_MmuPlugin_ports_0_cacheLine_exception; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_MmuPlugin_ports_0_cacheLine_superPage; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_MmuPlugin_ports_0_cacheLine_allowRead; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_MmuPlugin_ports_0_cacheLine_allowWrite; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_MmuPlugin_ports_0_cacheLine_allowExecute; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_MmuPlugin_ports_0_cacheLine_allowUser; + always @(*) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; - if(_zz_289)begin - if(_zz_290)begin + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; end end @@ -4439,63 +4540,63 @@ module VexRiscv ( assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); - always @ (*) begin - MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_377); - if(MmuPlugin_ports_0_entryToReplace_willClear)begin + always @(*) begin + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_MmuPlugin_ports_0_entryToReplace_valueNext); + if(MmuPlugin_ports_0_entryToReplace_willClear) begin MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; end else begin IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); end else begin IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; end else begin IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; end else begin IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); end else begin IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; @@ -4513,45 +4614,42 @@ module VexRiscv ( assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; assign MmuPlugin_ports_1_dirty = 1'b0; - always @ (*) begin + always @(*) begin MmuPlugin_ports_1_requireMmuLockupCalc = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + if(when_MmuPlugin_l125_1) begin MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; end - if((CsrPlugin_privilege == 2'b11))begin - if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)))begin + if(when_MmuPlugin_l126_1) begin + if(when_MmuPlugin_l128) begin MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; end end end - always @ (*) begin - MmuPlugin_ports_1_cacheHitsCalc[0] = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_1_cacheHitsCalc[1] = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_1_cacheHitsCalc[2] = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_1_cacheHitsCalc[3] = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - end - + assign when_MmuPlugin_l125_1 = ((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)); + assign when_MmuPlugin_l126_1 = (CsrPlugin_privilege == 2'b11); + assign when_MmuPlugin_l128 = ((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)); + assign MmuPlugin_ports_1_cacheHitsCalc = {((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))),{((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == _zz_MmuPlugin_ports_1_cacheHitsCalc)) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == _zz_MmuPlugin_ports_1_cacheHitsCalc_1))),{((MmuPlugin_ports_1_cache_1_valid && _zz_MmuPlugin_ports_1_cacheHitsCalc_2) && (MmuPlugin_ports_1_cache_1_superPage || _zz_MmuPlugin_ports_1_cacheHitsCalc_3)),((MmuPlugin_ports_1_cache_0_valid && _zz_MmuPlugin_ports_1_cacheHitsCalc_4) && (MmuPlugin_ports_1_cache_0_superPage || _zz_MmuPlugin_ports_1_cacheHitsCalc_5))}}}; assign MmuPlugin_ports_1_cacheHit = (MmuPlugin_ports_1_cacheHitsCalc != 4'b0000); - assign _zz_94 = MmuPlugin_ports_1_cacheHitsCalc[3]; - assign _zz_95 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_94); - assign _zz_96 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_94); - assign _zz_97 = {_zz_96,_zz_95}; - assign MmuPlugin_ports_1_cacheLine_valid = _zz_257; - assign MmuPlugin_ports_1_cacheLine_exception = _zz_258; - assign MmuPlugin_ports_1_cacheLine_superPage = _zz_259; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_260; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_261; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_262; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_263; - assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_264; - assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_265; - assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_266; - assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_267; - always @ (*) begin + assign _zz_MmuPlugin_ports_1_cacheLine_valid = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign _zz_MmuPlugin_ports_1_cacheLine_valid_1 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_MmuPlugin_ports_1_cacheLine_valid); + assign _zz_MmuPlugin_ports_1_cacheLine_valid_2 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_MmuPlugin_ports_1_cacheLine_valid); + assign _zz_MmuPlugin_ports_1_cacheLine_valid_3 = {_zz_MmuPlugin_ports_1_cacheLine_valid_2,_zz_MmuPlugin_ports_1_cacheLine_valid_1}; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_MmuPlugin_ports_1_cacheLine_valid_4; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_MmuPlugin_ports_1_cacheLine_exception; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_MmuPlugin_ports_1_cacheLine_superPage; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_MmuPlugin_ports_1_cacheLine_allowRead; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_MmuPlugin_ports_1_cacheLine_allowWrite; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_MmuPlugin_ports_1_cacheLine_allowExecute; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_MmuPlugin_ports_1_cacheLine_allowUser; + always @(*) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; - if(_zz_289)begin - if(_zz_291)begin + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274_1) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; end end @@ -4560,63 +4658,63 @@ module VexRiscv ( assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); - always @ (*) begin - MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_379); - if(MmuPlugin_ports_1_entryToReplace_willClear)begin + always @(*) begin + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_MmuPlugin_ports_1_entryToReplace_valueNext); + if(MmuPlugin_ports_1_entryToReplace_willClear) begin MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; end else begin DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); end else begin DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; end else begin DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; end else begin DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); end else begin DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; @@ -4633,30 +4731,31 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; - assign MmuPlugin_shared_dBusRsp_pte_V = _zz_380[0]; - assign MmuPlugin_shared_dBusRsp_pte_R = _zz_381[0]; - assign MmuPlugin_shared_dBusRsp_pte_W = _zz_382[0]; - assign MmuPlugin_shared_dBusRsp_pte_X = _zz_383[0]; - assign MmuPlugin_shared_dBusRsp_pte_U = _zz_384[0]; - assign MmuPlugin_shared_dBusRsp_pte_G = _zz_385[0]; - assign MmuPlugin_shared_dBusRsp_pte_A = _zz_386[0]; - assign MmuPlugin_shared_dBusRsp_pte_D = _zz_387[0]; + assign MmuPlugin_shared_dBusRsp_pte_V = MmuPlugin_shared_dBusRspStaged_payload_data[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = MmuPlugin_shared_dBusRspStaged_payload_data[1]; + assign MmuPlugin_shared_dBusRsp_pte_W = MmuPlugin_shared_dBusRspStaged_payload_data[2]; + assign MmuPlugin_shared_dBusRsp_pte_X = MmuPlugin_shared_dBusRspStaged_payload_data[3]; + assign MmuPlugin_shared_dBusRsp_pte_U = MmuPlugin_shared_dBusRspStaged_payload_data[4]; + assign MmuPlugin_shared_dBusRsp_pte_G = MmuPlugin_shared_dBusRspStaged_payload_data[5]; + assign MmuPlugin_shared_dBusRsp_pte_A = MmuPlugin_shared_dBusRspStaged_payload_data[6]; + assign MmuPlugin_shared_dBusRsp_pte_D = MmuPlugin_shared_dBusRspStaged_payload_data[7]; assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); - always @ (*) begin + assign when_MmuPlugin_l205 = (MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)); + always @(*) begin MmuPlugin_dBusAccess_cmd_valid = 1'b0; case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + `MmuPlugin_shared_State_binary_sequential_IDLE : begin end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin MmuPlugin_dBusAccess_cmd_valid = 1'b1; end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin MmuPlugin_dBusAccess_cmd_valid = 1'b1; end default : begin @@ -4666,17 +4765,17 @@ module VexRiscv ( assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; - always @ (*) begin - MmuPlugin_dBusAccess_cmd_payload_address = 32'h0; + always @(*) begin + MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + `MmuPlugin_shared_State_binary_sequential_IDLE : begin end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; end default : begin @@ -4684,84 +4783,95 @@ module VexRiscv ( endcase end - assign MmuPlugin_dBusAccess_cmd_payload_data = 32'h0; + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; - always @ (*) begin - _zz_98[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); - _zz_98[1] = (((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)); - end - - assign _zz_99 = _zz_98; - always @ (*) begin - _zz_100[0] = _zz_99[1]; - _zz_100[1] = _zz_99[0]; - end - - assign _zz_101 = (_zz_100 & (~ _zz_388)); - always @ (*) begin - _zz_102[0] = _zz_101[1]; - _zz_102[1] = _zz_101[0]; - end - - assign MmuPlugin_shared_refills = _zz_102; - assign _zz_103 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); - assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[0]); - assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[1]); - assign _zz_105 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_106 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_107 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); - assign _zz_108 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_109 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_110 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_104 = {(((decode_INSTRUCTION & _zz_507) == 32'h00100050) != 1'b0),{(_zz_110 != 1'b0),{(_zz_110 != 1'b0),{(_zz_508 != _zz_509),{_zz_510,{_zz_511,_zz_512}}}}}}; - assign _zz_111 = _zz_104[2 : 1]; - assign _zz_49 = _zz_111; - assign _zz_112 = _zz_104[7 : 6]; - assign _zz_48 = _zz_112; - assign _zz_113 = _zz_104[9 : 8]; - assign _zz_47 = _zz_113; - assign _zz_114 = _zz_104[23 : 22]; - assign _zz_46 = _zz_114; - assign _zz_115 = _zz_104[25 : 24]; - assign _zz_45 = _zz_115; - assign _zz_116 = _zz_104[27 : 26]; - assign _zz_44 = _zz_116; - assign _zz_117 = _zz_104[30 : 29]; - assign _zz_43 = _zz_117; + assign _zz_MmuPlugin_shared_refills = {(((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)),(((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit))}; + always @(*) begin + _zz_MmuPlugin_shared_refills_1[0] = _zz_MmuPlugin_shared_refills[1]; + _zz_MmuPlugin_shared_refills_1[1] = _zz_MmuPlugin_shared_refills[0]; + end + + assign _zz_MmuPlugin_shared_refills_2 = (_zz_MmuPlugin_shared_refills_1 & (~ _zz__zz_MmuPlugin_shared_refills_2)); + always @(*) begin + _zz_MmuPlugin_shared_refills_3[0] = _zz_MmuPlugin_shared_refills_2[1]; + _zz_MmuPlugin_shared_refills_3[1] = _zz_MmuPlugin_shared_refills_2[0]; + end + + assign MmuPlugin_shared_refills = _zz_MmuPlugin_shared_refills_3; + assign when_MmuPlugin_l217 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_MmuPlugin_shared_vpn_0 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); + assign when_MmuPlugin_l243 = (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception); + assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_binary_sequential_IDLE) && MmuPlugin_shared_portSortedOh[0]); + assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_binary_sequential_IDLE) && MmuPlugin_shared_portSortedOh[1]); + assign when_MmuPlugin_l272 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign when_MmuPlugin_l274 = MmuPlugin_shared_portSortedOh[0]; + assign when_MmuPlugin_l280 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign when_MmuPlugin_l280_1 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign when_MmuPlugin_l280_2 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign when_MmuPlugin_l280_3 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign when_MmuPlugin_l274_1 = MmuPlugin_shared_portSortedOh[1]; + assign when_MmuPlugin_l280_4 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign when_MmuPlugin_l280_5 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign when_MmuPlugin_l280_6 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign when_MmuPlugin_l280_7 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign when_MmuPlugin_l304 = ((execute_arbitration_isValid && execute_arbitration_isFiring) && execute_IS_SFENCE_VMA2); + assign _zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); + assign _zz_decode_IS_RS2_SIGNED_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_5 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_6 = ((decode_INSTRUCTION & 32'h02003050) == 32'h02000050); + assign _zz_decode_IS_RS2_SIGNED_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_IS_RS2_SIGNED = {(((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED) == 32'h00100050) != 1'b0),{(_zz_decode_IS_RS2_SIGNED_7 != 1'b0),{(_zz_decode_IS_RS2_SIGNED_7 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_1 != _zz__zz_decode_IS_RS2_SIGNED_2),{_zz__zz_decode_IS_RS2_SIGNED_3,{_zz__zz_decode_IS_RS2_SIGNED_5,_zz__zz_decode_IS_RS2_SIGNED_8}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_RS2_SIGNED[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_RS2_SIGNED[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_RS2_SIGNED[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_RS2_SIGNED[24 : 23]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_RS2_SIGNED[26 : 25]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_RS2_SIGNED[28 : 27]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_RS2_SIGNED[31 : 30]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_243; - assign decode_RegFilePlugin_rs2Data = _zz_244; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_41 && writeBack_arbitration_isFiring); - if(_zz_118)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_40[11 : 7]; - if(_zz_118)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_50; - if(_zz_118)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -4770,355 +4880,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_119 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_119 = {31'd0, _zz_389}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_119 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_120 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_120 = {29'd0, _zz_390}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_120 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_120 = {27'd0, _zz_391}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_121 = _zz_392[11]; - always @ (*) begin - _zz_122[19] = _zz_121; - _zz_122[18] = _zz_121; - _zz_122[17] = _zz_121; - _zz_122[16] = _zz_121; - _zz_122[15] = _zz_121; - _zz_122[14] = _zz_121; - _zz_122[13] = _zz_121; - _zz_122[12] = _zz_121; - _zz_122[11] = _zz_121; - _zz_122[10] = _zz_121; - _zz_122[9] = _zz_121; - _zz_122[8] = _zz_121; - _zz_122[7] = _zz_121; - _zz_122[6] = _zz_121; - _zz_122[5] = _zz_121; - _zz_122[4] = _zz_121; - _zz_122[3] = _zz_121; - _zz_122[2] = _zz_121; - _zz_122[1] = _zz_121; - _zz_122[0] = _zz_121; - end - - assign _zz_123 = _zz_393[11]; - always @ (*) begin - _zz_124[19] = _zz_123; - _zz_124[18] = _zz_123; - _zz_124[17] = _zz_123; - _zz_124[16] = _zz_123; - _zz_124[15] = _zz_123; - _zz_124[14] = _zz_123; - _zz_124[13] = _zz_123; - _zz_124[12] = _zz_123; - _zz_124[11] = _zz_123; - _zz_124[10] = _zz_123; - _zz_124[9] = _zz_123; - _zz_124[8] = _zz_123; - _zz_124[7] = _zz_123; - _zz_124[6] = _zz_123; - _zz_124[5] = _zz_123; - _zz_124[4] = _zz_123; - _zz_124[3] = _zz_123; - _zz_124[2] = _zz_123; - _zz_124[1] = _zz_123; - _zz_124[0] = _zz_123; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_125 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_125 = {_zz_122,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_125 = {_zz_124,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_125 = _zz_35; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_394; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_126[0] = execute_SRC1[31]; - _zz_126[1] = execute_SRC1[30]; - _zz_126[2] = execute_SRC1[29]; - _zz_126[3] = execute_SRC1[28]; - _zz_126[4] = execute_SRC1[27]; - _zz_126[5] = execute_SRC1[26]; - _zz_126[6] = execute_SRC1[25]; - _zz_126[7] = execute_SRC1[24]; - _zz_126[8] = execute_SRC1[23]; - _zz_126[9] = execute_SRC1[22]; - _zz_126[10] = execute_SRC1[21]; - _zz_126[11] = execute_SRC1[20]; - _zz_126[12] = execute_SRC1[19]; - _zz_126[13] = execute_SRC1[18]; - _zz_126[14] = execute_SRC1[17]; - _zz_126[15] = execute_SRC1[16]; - _zz_126[16] = execute_SRC1[15]; - _zz_126[17] = execute_SRC1[14]; - _zz_126[18] = execute_SRC1[13]; - _zz_126[19] = execute_SRC1[12]; - _zz_126[20] = execute_SRC1[11]; - _zz_126[21] = execute_SRC1[10]; - _zz_126[22] = execute_SRC1[9]; - _zz_126[23] = execute_SRC1[8]; - _zz_126[24] = execute_SRC1[7]; - _zz_126[25] = execute_SRC1[6]; - _zz_126[26] = execute_SRC1[5]; - _zz_126[27] = execute_SRC1[4]; - _zz_126[28] = execute_SRC1[3]; - _zz_126[29] = execute_SRC1[2]; - _zz_126[30] = execute_SRC1[1]; - _zz_126[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_126 : execute_SRC1); - always @ (*) begin - _zz_127[0] = memory_SHIFT_RIGHT[31]; - _zz_127[1] = memory_SHIFT_RIGHT[30]; - _zz_127[2] = memory_SHIFT_RIGHT[29]; - _zz_127[3] = memory_SHIFT_RIGHT[28]; - _zz_127[4] = memory_SHIFT_RIGHT[27]; - _zz_127[5] = memory_SHIFT_RIGHT[26]; - _zz_127[6] = memory_SHIFT_RIGHT[25]; - _zz_127[7] = memory_SHIFT_RIGHT[24]; - _zz_127[8] = memory_SHIFT_RIGHT[23]; - _zz_127[9] = memory_SHIFT_RIGHT[22]; - _zz_127[10] = memory_SHIFT_RIGHT[21]; - _zz_127[11] = memory_SHIFT_RIGHT[20]; - _zz_127[12] = memory_SHIFT_RIGHT[19]; - _zz_127[13] = memory_SHIFT_RIGHT[18]; - _zz_127[14] = memory_SHIFT_RIGHT[17]; - _zz_127[15] = memory_SHIFT_RIGHT[16]; - _zz_127[16] = memory_SHIFT_RIGHT[15]; - _zz_127[17] = memory_SHIFT_RIGHT[14]; - _zz_127[18] = memory_SHIFT_RIGHT[13]; - _zz_127[19] = memory_SHIFT_RIGHT[12]; - _zz_127[20] = memory_SHIFT_RIGHT[11]; - _zz_127[21] = memory_SHIFT_RIGHT[10]; - _zz_127[22] = memory_SHIFT_RIGHT[9]; - _zz_127[23] = memory_SHIFT_RIGHT[8]; - _zz_127[24] = memory_SHIFT_RIGHT[7]; - _zz_127[25] = memory_SHIFT_RIGHT[6]; - _zz_127[26] = memory_SHIFT_RIGHT[5]; - _zz_127[27] = memory_SHIFT_RIGHT[4]; - _zz_127[28] = memory_SHIFT_RIGHT[3]; - _zz_127[29] = memory_SHIFT_RIGHT[2]; - _zz_127[30] = memory_SHIFT_RIGHT[1]; - _zz_127[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_128 = 1'b0; - if(_zz_292)begin - if(_zz_293)begin - if(_zz_133)begin - _zz_128 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_294)begin - if(_zz_295)begin - if(_zz_135)begin - _zz_128 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_296)begin - if(_zz_297)begin - if(_zz_137)begin - _zz_128 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_128 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_129 = 1'b0; - if(_zz_292)begin - if(_zz_293)begin - if(_zz_134)begin - _zz_129 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_294)begin - if(_zz_295)begin - if(_zz_136)begin - _zz_129 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_296)begin - if(_zz_297)begin - if(_zz_138)begin - _zz_129 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_129 = 1'b0; - end - end - - assign _zz_133 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_134 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_135 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_136 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_137 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_138 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_139 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_139 == 3'b000)) begin - _zz_140 = execute_BranchPlugin_eq; - end else if((_zz_139 == 3'b001)) begin - _zz_140 = (! execute_BranchPlugin_eq); - end else if((((_zz_139 & 3'b101) == 3'b101))) begin - _zz_140 = (! execute_SRC_LESS); - end else begin - _zz_140 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_141 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_141 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_141 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_141 = _zz_140; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_142 = _zz_401[11]; - always @ (*) begin - _zz_143[19] = _zz_142; - _zz_143[18] = _zz_142; - _zz_143[17] = _zz_142; - _zz_143[16] = _zz_142; - _zz_143[15] = _zz_142; - _zz_143[14] = _zz_142; - _zz_143[13] = _zz_142; - _zz_143[12] = _zz_142; - _zz_143[11] = _zz_142; - _zz_143[10] = _zz_142; - _zz_143[9] = _zz_142; - _zz_143[8] = _zz_142; - _zz_143[7] = _zz_142; - _zz_143[6] = _zz_142; - _zz_143[5] = _zz_142; - _zz_143[4] = _zz_142; - _zz_143[3] = _zz_142; - _zz_143[2] = _zz_142; - _zz_143[1] = _zz_142; - _zz_143[0] = _zz_142; - end - - assign _zz_144 = _zz_402[19]; - always @ (*) begin - _zz_145[10] = _zz_144; - _zz_145[9] = _zz_144; - _zz_145[8] = _zz_144; - _zz_145[7] = _zz_144; - _zz_145[6] = _zz_144; - _zz_145[5] = _zz_144; - _zz_145[4] = _zz_144; - _zz_145[3] = _zz_144; - _zz_145[2] = _zz_144; - _zz_145[1] = _zz_144; - _zz_145[0] = _zz_144; - end - - assign _zz_146 = _zz_403[11]; - always @ (*) begin - _zz_147[18] = _zz_146; - _zz_147[17] = _zz_146; - _zz_147[16] = _zz_146; - _zz_147[15] = _zz_146; - _zz_147[14] = _zz_146; - _zz_147[13] = _zz_146; - _zz_147[12] = _zz_146; - _zz_147[11] = _zz_146; - _zz_147[10] = _zz_146; - _zz_147[9] = _zz_146; - _zz_147[8] = _zz_146; - _zz_147[7] = _zz_146; - _zz_147[6] = _zz_146; - _zz_147[5] = _zz_146; - _zz_147[4] = _zz_146; - _zz_147[3] = _zz_146; - _zz_147[2] = _zz_146; - _zz_147[1] = _zz_146; - _zz_147[0] = _zz_146; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_148 = (_zz_404[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_148 = _zz_405[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_148 = _zz_406[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_148); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -5127,80 +5260,80 @@ module VexRiscv ( endcase end - assign _zz_149 = _zz_407[11]; - always @ (*) begin - _zz_150[19] = _zz_149; - _zz_150[18] = _zz_149; - _zz_150[17] = _zz_149; - _zz_150[16] = _zz_149; - _zz_150[15] = _zz_149; - _zz_150[14] = _zz_149; - _zz_150[13] = _zz_149; - _zz_150[12] = _zz_149; - _zz_150[11] = _zz_149; - _zz_150[10] = _zz_149; - _zz_150[9] = _zz_149; - _zz_150[8] = _zz_149; - _zz_150[7] = _zz_149; - _zz_150[6] = _zz_149; - _zz_150[5] = _zz_149; - _zz_150[4] = _zz_149; - _zz_150[3] = _zz_149; - _zz_150[2] = _zz_149; - _zz_150[1] = _zz_149; - _zz_150[0] = _zz_149; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_150,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_152,{{{_zz_713,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_154,{{{_zz_714,_zz_715},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_410}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_151 = _zz_408[19]; - always @ (*) begin - _zz_152[10] = _zz_151; - _zz_152[9] = _zz_151; - _zz_152[8] = _zz_151; - _zz_152[7] = _zz_151; - _zz_152[6] = _zz_151; - _zz_152[5] = _zz_151; - _zz_152[4] = _zz_151; - _zz_152[3] = _zz_151; - _zz_152[2] = _zz_151; - _zz_152[1] = _zz_151; - _zz_152[0] = _zz_151; - end - - assign _zz_153 = _zz_409[11]; - always @ (*) begin - _zz_154[18] = _zz_153; - _zz_154[17] = _zz_153; - _zz_154[16] = _zz_153; - _zz_154[15] = _zz_153; - _zz_154[14] = _zz_153; - _zz_154[13] = _zz_153; - _zz_154[12] = _zz_153; - _zz_154[11] = _zz_153; - _zz_154[10] = _zz_153; - _zz_154[9] = _zz_153; - _zz_154[8] = _zz_153; - _zz_154[7] = _zz_153; - _zz_154[6] = _zz_153; - _zz_154[5] = _zz_153; - _zz_154[4] = _zz_153; - _zz_154[3] = _zz_153; - _zz_154[2] = _zz_153; - _zz_154[1] = _zz_153; - _zz_154[0] = _zz_153; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -5210,9 +5343,9 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin - CsrPlugin_privilege = _zz_155; - if(CsrPlugin_forceMachineWire)begin + always @(*) begin + CsrPlugin_privilege = _zz_CsrPlugin_privilege; + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end @@ -5220,82 +5353,93 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0; assign CsrPlugin_sip_SEIP_OR = (CsrPlugin_sip_SEIP_SOFT || CsrPlugin_sip_SEIP_INPUT); - always @ (*) begin + always @(*) begin CsrPlugin_redoInterface_valid = 1'b0; - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeInstruction)begin - CsrPlugin_redoInterface_valid = 1'b1; - end + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin + CsrPlugin_redoInterface_valid = 1'b1; end end assign CsrPlugin_redoInterface_payload = decode_PC; - assign _zz_156 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); - assign _zz_157 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); - assign _zz_158 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); - assign _zz_159 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_160 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_161 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - always @ (*) begin + always @(*) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b0; + if(when_CsrPlugin_l803) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b1; + end + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeInstruction) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b1; + end + end + end + + assign when_CsrPlugin_l803 = (execute_arbitration_isValid && execute_IS_SFENCE_VMA); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_when_CsrPlugin_l952_3 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_4 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_5 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) 4'b0000 : begin - if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin + if(when_CsrPlugin_l866) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0001 : begin - if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_1) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0010 : begin - if(((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)))begin + if(when_CsrPlugin_l866_2) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0100 : begin - if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin + if(when_CsrPlugin_l866_3) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0101 : begin - if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_4) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0110 : begin - if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin + if(when_CsrPlugin_l866_5) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0111 : begin - if(((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_6) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1000 : begin - if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin + if(when_CsrPlugin_l866_7) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1001 : begin - if(((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)))begin + if(when_CsrPlugin_l866_8) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1100 : begin - if(((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_9) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1101 : begin - if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_10) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1111 : begin - if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_11) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end @@ -5304,81 +5448,114 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l866 = ((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)); + assign when_CsrPlugin_l866_1 = ((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)); + assign when_CsrPlugin_l866_2 = ((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)); + assign when_CsrPlugin_l866_3 = ((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)); + assign when_CsrPlugin_l866_4 = ((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)); + assign when_CsrPlugin_l866_5 = ((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)); + assign when_CsrPlugin_l866_6 = ((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)); + assign when_CsrPlugin_l866_7 = ((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)); + assign when_CsrPlugin_l866_8 = ((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)); + assign when_CsrPlugin_l866_9 = ((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)); + assign when_CsrPlugin_l866_10 = ((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)); + assign when_CsrPlugin_l866_11 = ((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_162 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_163 = _zz_411[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_278)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign when_CsrPlugin_l946_1 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign when_CsrPlugin_l952_3 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign when_CsrPlugin_l952_4 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign when_CsrPlugin_l952_5 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign when_CsrPlugin_l952_6 = ((_zz_when_CsrPlugin_l952_3 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_7 = ((_zz_when_CsrPlugin_l952_4 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_8 = ((_zz_when_CsrPlugin_l952_5 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin @@ -5392,8 +5569,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_base = CsrPlugin_stvec_base; @@ -5406,151 +5583,160 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_256)begin + if(execute_CsrPlugin_csr_256) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_csr_384) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_770)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_770) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_771)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_771) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_324)begin + if(execute_CsrPlugin_csr_324) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_260)begin + if(execute_CsrPlugin_csr_260) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_261)begin + if(execute_CsrPlugin_csr_261) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_321)begin + if(execute_CsrPlugin_csr_321) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_320)begin + if(execute_CsrPlugin_csr_320) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_322)begin + if(execute_CsrPlugin_csr_322) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_323)begin + if(execute_CsrPlugin_csr_323) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2496)begin + if(execute_CsrPlugin_csr_2496) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3520)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3520) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_298)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_299)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_300)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_299)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_300)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -5566,48 +5752,58 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_298)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_298)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - always @ (*) begin - execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - if(execute_CsrPlugin_csr_836)begin + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + always @(*) begin + execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; end - if(execute_CsrPlugin_csr_324)begin + if(execute_CsrPlugin_csr_324) begin execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; end end - always @ (*) begin - case(_zz_328) + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || execute_IS_SFENCE_VMA)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_301) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -5620,8 +5816,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_301) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -5640,60 +5836,71 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_413) + $signed(_zz_414)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_273)begin - if(_zz_302)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_303)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_418); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_164 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_164[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_419); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_420 : _zz_421); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_422[31:0]; - assign _zz_165 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_166 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_167 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_168[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_168[31 : 0] = execute_RS1; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; end - assign _zz_170 = (_zz_169 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_170 != 32'h0); - assign _zz_172 = (_zz_171 & externalInterruptArray_regNext); - assign externalInterruptS = (_zz_172 != 32'h0); - always @ (*) begin + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign _zz_CsrPlugin_csrMapping_readDataInit_3 = (_zz_CsrPlugin_csrMapping_readDataInit_2 & externalInterruptArray_regNext); + assign externalInterruptS = (_zz_CsrPlugin_csrMapping_readDataInit_3 != 32'h0); + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_304) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end end @@ -5703,9 +5910,9 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_173))begin + if(when_DebugPlugin_l244) begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -5714,12 +5921,13 @@ module VexRiscv ( end end - always @ (*) begin + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_304) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin IBusCachedPlugin_injectionPort_valid = 1'b1; end end @@ -5730,35 +5938,118 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_26 = decode_SRC1_CTRL; - assign _zz_24 = _zz_49; - assign _zz_37 = decode_to_execute_SRC1_CTRL; - assign _zz_23 = decode_ALU_CTRL; - assign _zz_21 = _zz_48; - assign _zz_38 = decode_to_execute_ALU_CTRL; - assign _zz_20 = decode_SRC2_CTRL; - assign _zz_18 = _zz_47; - assign _zz_36 = decode_to_execute_SRC2_CTRL; - assign _zz_17 = decode_ALU_BITWISE_CTRL; - assign _zz_15 = _zz_46; - assign _zz_39 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_14 = decode_SHIFT_CTRL; - assign _zz_11 = execute_SHIFT_CTRL; - assign _zz_12 = _zz_45; - assign _zz_34 = decode_to_execute_SHIFT_CTRL; - assign _zz_33 = execute_to_memory_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_52 = _zz_44; - assign _zz_30 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_43; - assign _zz_28 = decode_to_execute_ENV_CTRL; - assign _zz_27 = execute_to_memory_ENV_CTRL; - assign _zz_29 = memory_to_writeBack_ENV_CTRL; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_28 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_36 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_38 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_41 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_64 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_65 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_66 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_67 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_68 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_69 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_70 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -5779,9 +6070,15 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_174) + case(switch_Fetcher_l362) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -5790,267 +6087,299 @@ module VexRiscv ( endcase end - always @ (*) begin - _zz_175 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_175[12 : 0] = 13'h1000; - _zz_175[25 : 20] = 6'h20; + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_4[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_176 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_176[19 : 19] = MmuPlugin_status_mxr; - _zz_176[18 : 18] = MmuPlugin_status_sum; - _zz_176[17 : 17] = MmuPlugin_status_mprv; - _zz_176[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_176[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_176[3 : 3] = CsrPlugin_mstatus_MIE; - _zz_176[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_176[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_176[1 : 1] = CsrPlugin_sstatus_SIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[19 : 19] = MmuPlugin_status_mxr; + _zz_CsrPlugin_csrMapping_readDataInit_5[18 : 18] = MmuPlugin_status_sum; + _zz_CsrPlugin_csrMapping_readDataInit_5[17 : 17] = MmuPlugin_status_mprv; + _zz_CsrPlugin_csrMapping_readDataInit_5[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_5[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[1 : 1] = CsrPlugin_sstatus_SIE; end end - always @ (*) begin - _zz_177 = 32'h0; - if(execute_CsrPlugin_csr_256)begin - _zz_177[19 : 19] = MmuPlugin_status_mxr; - _zz_177[18 : 18] = MmuPlugin_status_sum; - _zz_177[17 : 17] = MmuPlugin_status_mprv; - _zz_177[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_177[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_177[1 : 1] = CsrPlugin_sstatus_SIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_256) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[19 : 19] = MmuPlugin_status_mxr; + _zz_CsrPlugin_csrMapping_readDataInit_6[18 : 18] = MmuPlugin_status_sum; + _zz_CsrPlugin_csrMapping_readDataInit_6[17 : 17] = MmuPlugin_status_mprv; + _zz_CsrPlugin_csrMapping_readDataInit_6[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_CsrPlugin_csrMapping_readDataInit_6[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_CsrPlugin_csrMapping_readDataInit_6[1 : 1] = CsrPlugin_sstatus_SIE; end end - always @ (*) begin - _zz_178 = 32'h0; - if(execute_CsrPlugin_csr_384)begin - _zz_178[31 : 31] = MmuPlugin_satp_mode; - _zz_178[30 : 22] = MmuPlugin_satp_asid; - _zz_178[19 : 0] = MmuPlugin_satp_ppn; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_384) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 31] = MmuPlugin_satp_mode; + _zz_CsrPlugin_csrMapping_readDataInit_7[30 : 22] = MmuPlugin_satp_asid; + _zz_CsrPlugin_csrMapping_readDataInit_7[19 : 0] = MmuPlugin_satp_ppn; end end - always @ (*) begin - _zz_179 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_179[0 : 0] = 1'b1; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[0 : 0] = 1'b1; end end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_180[1 : 0] = 2'b10; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[1 : 0] = 2'b10; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_181[1 : 0] = 2'b11; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = 2'b11; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_182[11 : 11] = CsrPlugin_mip_MEIP; - _zz_182[7 : 7] = CsrPlugin_mip_MTIP; - _zz_182[3 : 3] = CsrPlugin_mip_MSIP; - _zz_182[5 : 5] = CsrPlugin_sip_STIP; - _zz_182[1 : 1] = CsrPlugin_sip_SSIP; - _zz_182[9 : 9] = CsrPlugin_sip_SEIP_OR; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 3] = CsrPlugin_mip_MSIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[5 : 5] = CsrPlugin_sip_STIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[1 : 1] = CsrPlugin_sip_SSIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[9 : 9] = CsrPlugin_sip_SEIP_OR; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_183[11 : 11] = CsrPlugin_mie_MEIE; - _zz_183[7 : 7] = CsrPlugin_mie_MTIE; - _zz_183[3 : 3] = CsrPlugin_mie_MSIE; - _zz_183[9 : 9] = CsrPlugin_sie_SEIE; - _zz_183[5 : 5] = CsrPlugin_sie_STIE; - _zz_183[1 : 1] = CsrPlugin_sie_SSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[3 : 3] = CsrPlugin_mie_MSIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[9 : 9] = CsrPlugin_sie_SEIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[5 : 5] = CsrPlugin_sie_STIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[1 : 1] = CsrPlugin_sie_SSIE; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_184[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_185[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_186 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_186[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_186[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_187 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_187[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_188 = 32'h0; - if(execute_CsrPlugin_csr_324)begin - _zz_188[5 : 5] = CsrPlugin_sip_STIP; - _zz_188[1 : 1] = CsrPlugin_sip_SSIP; - _zz_188[9 : 9] = CsrPlugin_sip_SEIP_OR; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_324) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[5 : 5] = CsrPlugin_sip_STIP; + _zz_CsrPlugin_csrMapping_readDataInit_17[1 : 1] = CsrPlugin_sip_SSIP; + _zz_CsrPlugin_csrMapping_readDataInit_17[9 : 9] = CsrPlugin_sip_SEIP_OR; end end - always @ (*) begin - _zz_189 = 32'h0; - if(execute_CsrPlugin_csr_260)begin - _zz_189[9 : 9] = CsrPlugin_sie_SEIE; - _zz_189[5 : 5] = CsrPlugin_sie_STIE; - _zz_189[1 : 1] = CsrPlugin_sie_SSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_260) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[9 : 9] = CsrPlugin_sie_SEIE; + _zz_CsrPlugin_csrMapping_readDataInit_18[5 : 5] = CsrPlugin_sie_STIE; + _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 1] = CsrPlugin_sie_SSIE; end end - always @ (*) begin - _zz_190 = 32'h0; - if(execute_CsrPlugin_csr_261)begin - _zz_190[31 : 2] = CsrPlugin_stvec_base; - _zz_190[1 : 0] = CsrPlugin_stvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_261) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 2] = CsrPlugin_stvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_19[1 : 0] = CsrPlugin_stvec_mode; end end - always @ (*) begin - _zz_191 = 32'h0; - if(execute_CsrPlugin_csr_321)begin - _zz_191[31 : 0] = CsrPlugin_sepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_321) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_sepc; end end - always @ (*) begin - _zz_192 = 32'h0; - if(execute_CsrPlugin_csr_320)begin - _zz_192[31 : 0] = CsrPlugin_sscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_320) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_sscratch; end end - always @ (*) begin - _zz_193 = 32'h0; - if(execute_CsrPlugin_csr_322)begin - _zz_193[31 : 31] = CsrPlugin_scause_interrupt; - _zz_193[3 : 0] = CsrPlugin_scause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_322) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 31] = CsrPlugin_scause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_22[3 : 0] = CsrPlugin_scause_exceptionCode; end end - always @ (*) begin - _zz_194 = 32'h0; - if(execute_CsrPlugin_csr_323)begin - _zz_194[31 : 0] = CsrPlugin_stval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_323) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_stval; end end - always @ (*) begin - _zz_195 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_195[31 : 0] = _zz_169; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_196 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_196[31 : 0] = _zz_170; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - always @ (*) begin - _zz_197 = 32'h0; - if(execute_CsrPlugin_csr_2496)begin - _zz_197[31 : 0] = _zz_171; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + if(execute_CsrPlugin_csr_2496) begin + _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; end end - always @ (*) begin - _zz_198 = 32'h0; - if(execute_CsrPlugin_csr_3520)begin - _zz_198[31 : 0] = _zz_172; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + if(execute_CsrPlugin_csr_3520) begin + _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; end end - assign execute_CsrPlugin_readData = (((((_zz_175 | _zz_176) | (_zz_177 | _zz_178)) | ((_zz_179 | _zz_180) | (_zz_181 | _zz_716))) | (((_zz_182 | _zz_183) | (_zz_184 | _zz_185)) | ((_zz_186 | _zz_187) | (_zz_188 | _zz_189)))) | ((((_zz_190 | _zz_191) | (_zz_192 | _zz_193)) | ((_zz_194 | _zz_195) | (_zz_196 | _zz_197))) | _zz_198)); - assign iBusWishbone_ADR = {_zz_477,_zz_199}; - assign iBusWishbone_CTI = ((_zz_199 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5) | (_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7)) | ((_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9) | (_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_28))) | (((_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12) | (_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14)) | ((_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16) | (_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20) | (_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22)) | ((_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24) | (_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26))) | _zz_CsrPlugin_csrMapping_readDataInit_27)); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_305)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_305)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_200; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_206 = (dBus_cmd_payload_length != 3'b000); - assign _zz_202 = dBus_cmd_valid; - assign _zz_204 = dBus_cmd_payload_wr; - assign _zz_205 = (_zz_201 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_203 && (_zz_204 || _zz_205)); - assign dBusWishbone_ADR = ((_zz_206 ? {{dBus_cmd_payload_address[31 : 5],_zz_201},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_206 ? (_zz_205 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_204 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_204; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_203 = (_zz_202 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_202; - assign dBusWishbone_STB = _zz_202; - assign dBus_rsp_valid = _zz_207; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_68 <= 1'b0; - _zz_70 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_83; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_84; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; MmuPlugin_status_sum <= 1'b0; MmuPlugin_status_mxr <= 1'b0; @@ -6066,11 +6395,11 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; MmuPlugin_ports_1_entryToReplace_value <= 2'b00; - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_IDLE; MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; - _zz_118 <= 1'b1; - _zz_130 <= 1'b0; - _zz_155 <= 2'b11; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_CsrPlugin_privilege <= 2'b11; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -6113,205 +6442,205 @@ module VexRiscv ( CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; memory_DivPlugin_div_counter_value <= 6'h0; - _zz_169 <= 32'h0; - _zz_171 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_2 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_174 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; execute_to_memory_IS_DBUS_SHARING <= 1'b0; memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; - _zz_199 <= 3'b000; - _zz_200 <= 1'b0; - _zz_201 <= 3'b000; - _zz_207 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_68 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_66)begin - _zz_68 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_70 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_70 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_306)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; - if(contextSwitching)begin - if(MmuPlugin_ports_0_cache_0_exception)begin + if(contextSwitching) begin + if(MmuPlugin_ports_0_cache_0_exception) begin MmuPlugin_ports_0_cache_0_valid <= 1'b0; end - if(MmuPlugin_ports_0_cache_1_exception)begin + if(MmuPlugin_ports_0_cache_1_exception) begin MmuPlugin_ports_0_cache_1_valid <= 1'b0; end - if(MmuPlugin_ports_0_cache_2_exception)begin + if(MmuPlugin_ports_0_cache_2_exception) begin MmuPlugin_ports_0_cache_2_valid <= 1'b0; end - if(MmuPlugin_ports_0_cache_3_exception)begin + if(MmuPlugin_ports_0_cache_3_exception) begin MmuPlugin_ports_0_cache_3_valid <= 1'b0; end end MmuPlugin_ports_1_entryToReplace_value <= MmuPlugin_ports_1_entryToReplace_valueNext; - if(contextSwitching)begin - if(MmuPlugin_ports_1_cache_0_exception)begin + if(contextSwitching) begin + if(MmuPlugin_ports_1_cache_0_exception) begin MmuPlugin_ports_1_cache_0_valid <= 1'b0; end - if(MmuPlugin_ports_1_cache_1_exception)begin + if(MmuPlugin_ports_1_cache_1_exception) begin MmuPlugin_ports_1_cache_1_valid <= 1'b0; end - if(MmuPlugin_ports_1_cache_2_exception)begin + if(MmuPlugin_ports_1_cache_2_exception) begin MmuPlugin_ports_1_cache_2_valid <= 1'b0; end - if(MmuPlugin_ports_1_cache_3_exception)begin + if(MmuPlugin_ports_1_cache_3_exception) begin MmuPlugin_ports_1_cache_3_valid <= 1'b0; end end MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_307)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + `MmuPlugin_shared_State_binary_sequential_IDLE : begin + if(when_MmuPlugin_l217) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L1_CMD; end end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin - if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L1_RSP; end end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin - if(MmuPlugin_shared_dBusRspStaged_valid)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; - if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin + if(MmuPlugin_shared_dBusRspStaged_valid) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L0_CMD; + if(when_MmuPlugin_l243) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_IDLE; end - if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + if(MmuPlugin_shared_dBusRspStaged_payload_redo) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L1_CMD; end end end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin - if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L0_RSP; end end default : begin - if(MmuPlugin_shared_dBusRspStaged_valid)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; - if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if(MmuPlugin_shared_dBusRspStaged_valid) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_IDLE; + if(MmuPlugin_shared_dBusRspStaged_payload_redo) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L0_CMD; end end end endcase - if(_zz_289)begin - if(_zz_290)begin - if(_zz_308)begin + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin + if(when_MmuPlugin_l280) begin MmuPlugin_ports_0_cache_0_valid <= 1'b1; end - if(_zz_309)begin + if(when_MmuPlugin_l280_1) begin MmuPlugin_ports_0_cache_1_valid <= 1'b1; end - if(_zz_310)begin + if(when_MmuPlugin_l280_2) begin MmuPlugin_ports_0_cache_2_valid <= 1'b1; end - if(_zz_311)begin + if(when_MmuPlugin_l280_3) begin MmuPlugin_ports_0_cache_3_valid <= 1'b1; end end - if(_zz_291)begin - if(_zz_312)begin + if(when_MmuPlugin_l274_1) begin + if(when_MmuPlugin_l280_4) begin MmuPlugin_ports_1_cache_0_valid <= 1'b1; end - if(_zz_313)begin + if(when_MmuPlugin_l280_5) begin MmuPlugin_ports_1_cache_1_valid <= 1'b1; end - if(_zz_314)begin + if(when_MmuPlugin_l280_6) begin MmuPlugin_ports_1_cache_2_valid <= 1'b1; end - if(_zz_315)begin + if(when_MmuPlugin_l280_7) begin MmuPlugin_ports_1_cache_3_valid <= 1'b1; end end end - if((writeBack_arbitration_isValid && writeBack_IS_SFENCE_VMA))begin + if(when_MmuPlugin_l304) begin MmuPlugin_ports_0_cache_0_valid <= 1'b0; MmuPlugin_ports_0_cache_1_valid <= 1'b0; MmuPlugin_ports_0_cache_2_valid <= 1'b0; @@ -6321,83 +6650,83 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - _zz_118 <= 1'b0; - _zz_130 <= (_zz_41 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_316)begin - if(_zz_317)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_318)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_319)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(_zz_320)begin - if(_zz_321)begin + if(when_CsrPlugin_l946_1) begin + if(when_CsrPlugin_l952_3) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_322)begin + if(when_CsrPlugin_l952_4) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_323)begin + if(when_CsrPlugin_l952_5) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_324)begin + if(when_CsrPlugin_l952_6) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_325)begin + if(when_CsrPlugin_l952_7) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_326)begin + if(when_CsrPlugin_l952_8) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_282)begin - _zz_155 <= CsrPlugin_targetPrivilege; + if(when_CsrPlugin_l1019) begin + _zz_CsrPlugin_privilege <= CsrPlugin_targetPrivilege; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_sstatus_SIE <= 1'b0; @@ -6413,101 +6742,105 @@ module VexRiscv ( end endcase end - if(_zz_283)begin - case(_zz_285) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; - _zz_155 <= CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_privilege <= CsrPlugin_mstatus_MPP; end 2'b01 : begin CsrPlugin_sstatus_SPP <= 1'b0; CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; CsrPlugin_sstatus_SPIE <= 1'b1; - _zz_155 <= {1'b0,CsrPlugin_sstatus_SPP}; + _zz_CsrPlugin_privilege <= {1'b0,CsrPlugin_sstatus_SPP}; end default : begin end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_161,{_zz_160,{_zz_159,{_zz_158,{_zz_157,_zz_156}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_5,{_zz_when_CsrPlugin_l952_4,{_zz_when_CsrPlugin_l952_3,{_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_174) + case(switch_Fetcher_l362) 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_174 <= 3'b001; + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; end end 3'b001 : begin - _zz_174 <= 3'b010; + switch_Fetcher_l362 <= 3'b010; end 3'b010 : begin - _zz_174 <= 3'b011; + switch_Fetcher_l362 <= 3'b011; end 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_174 <= 3'b100; + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; end end 3'b100 : begin - _zz_174 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; end default : begin end endcase - if(MmuPlugin_dBusAccess_rsp_valid)begin + if(MmuPlugin_dBusAccess_rsp_valid) begin + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end + if(MmuPlugin_dBusAccess_rsp_valid) begin memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_432[0]; - MmuPlugin_status_sum <= _zz_433[0]; - MmuPlugin_status_mprv <= _zz_434[0]; - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_435[0]; - CsrPlugin_mstatus_MIE <= _zz_436[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_437[0]; - CsrPlugin_sstatus_SIE <= _zz_438[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_status_mxr <= CsrPlugin_csrMapping_writeDataSignal[19]; + MmuPlugin_status_sum <= CsrPlugin_csrMapping_writeDataSignal[18]; + MmuPlugin_status_mprv <= CsrPlugin_csrMapping_writeDataSignal[17]; + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + CsrPlugin_sstatus_SPP <= CsrPlugin_csrMapping_writeDataSignal[8 : 8]; + CsrPlugin_sstatus_SPIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sstatus_SIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_256)begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_439[0]; - MmuPlugin_status_sum <= _zz_440[0]; - MmuPlugin_status_mprv <= _zz_441[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_442[0]; - CsrPlugin_sstatus_SIE <= _zz_443[0]; + if(execute_CsrPlugin_csr_256) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_status_mxr <= CsrPlugin_csrMapping_writeDataSignal[19]; + MmuPlugin_status_sum <= CsrPlugin_csrMapping_writeDataSignal[18]; + MmuPlugin_status_mprv <= CsrPlugin_csrMapping_writeDataSignal[17]; + CsrPlugin_sstatus_SPP <= CsrPlugin_csrMapping_writeDataSignal[8 : 8]; + CsrPlugin_sstatus_SPIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sstatus_SIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeInstruction)begin + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_satp_mode <= CsrPlugin_csrMapping_writeDataSignal[31]; MmuPlugin_ports_0_cache_0_valid <= 1'b0; MmuPlugin_ports_0_cache_1_valid <= 1'b0; MmuPlugin_ports_0_cache_2_valid <= 1'b0; @@ -6517,122 +6850,119 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_mode <= _zz_444[0]; - end end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_446[0]; - CsrPlugin_sip_SSIP <= _zz_447[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_448[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sip_STIP <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sip_SSIP <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_sip_SEIP_SOFT <= CsrPlugin_csrMapping_writeDataSignal[9]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_449[0]; - CsrPlugin_mie_MTIE <= _zz_450[0]; - CsrPlugin_mie_MSIE <= _zz_451[0]; - CsrPlugin_sie_SEIE <= _zz_452[0]; - CsrPlugin_sie_STIE <= _zz_453[0]; - CsrPlugin_sie_SSIE <= _zz_454[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + CsrPlugin_sie_SEIE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_sie_STIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sie_SSIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_770)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_medeleg_IAM <= _zz_455[0]; - CsrPlugin_medeleg_IAF <= _zz_456[0]; - CsrPlugin_medeleg_II <= _zz_457[0]; - CsrPlugin_medeleg_LAM <= _zz_458[0]; - CsrPlugin_medeleg_LAF <= _zz_459[0]; - CsrPlugin_medeleg_SAM <= _zz_460[0]; - CsrPlugin_medeleg_SAF <= _zz_461[0]; - CsrPlugin_medeleg_EU <= _zz_462[0]; - CsrPlugin_medeleg_ES <= _zz_463[0]; - CsrPlugin_medeleg_IPF <= _zz_464[0]; - CsrPlugin_medeleg_LPF <= _zz_465[0]; - CsrPlugin_medeleg_SPF <= _zz_466[0]; + if(execute_CsrPlugin_csr_770) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_medeleg_IAM <= CsrPlugin_csrMapping_writeDataSignal[0]; + CsrPlugin_medeleg_IAF <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_medeleg_II <= CsrPlugin_csrMapping_writeDataSignal[2]; + CsrPlugin_medeleg_LAM <= CsrPlugin_csrMapping_writeDataSignal[4]; + CsrPlugin_medeleg_LAF <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_medeleg_SAM <= CsrPlugin_csrMapping_writeDataSignal[6]; + CsrPlugin_medeleg_SAF <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_medeleg_EU <= CsrPlugin_csrMapping_writeDataSignal[8]; + CsrPlugin_medeleg_ES <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_medeleg_IPF <= CsrPlugin_csrMapping_writeDataSignal[12]; + CsrPlugin_medeleg_LPF <= CsrPlugin_csrMapping_writeDataSignal[13]; + CsrPlugin_medeleg_SPF <= CsrPlugin_csrMapping_writeDataSignal[15]; end end - if(execute_CsrPlugin_csr_771)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mideleg_SE <= _zz_467[0]; - CsrPlugin_mideleg_ST <= _zz_468[0]; - CsrPlugin_mideleg_SS <= _zz_469[0]; + if(execute_CsrPlugin_csr_771) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mideleg_SE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_mideleg_ST <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_mideleg_SS <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_324)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_470[0]; - CsrPlugin_sip_SSIP <= _zz_471[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_472[0]; + if(execute_CsrPlugin_csr_324) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sip_STIP <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sip_SSIP <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_sip_SEIP_SOFT <= CsrPlugin_csrMapping_writeDataSignal[9]; end end - if(execute_CsrPlugin_csr_260)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sie_SEIE <= _zz_473[0]; - CsrPlugin_sie_STIE <= _zz_474[0]; - CsrPlugin_sie_SSIE <= _zz_475[0]; + if(execute_CsrPlugin_csr_260) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sie_SEIE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_sie_STIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sie_SSIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_169 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2496)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_171 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2496) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_305)begin - if(iBusWishbone_ACK)begin - _zz_199 <= (_zz_199 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_200 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_202 && _zz_203))begin - _zz_201 <= (_zz_201 + 3'b001); - if(_zz_205)begin - _zz_201 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_207 <= ((_zz_202 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_71 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_306)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; - if((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)))begin + if(when_MmuPlugin_l205) begin MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; @@ -6646,26 +6976,26 @@ module VexRiscv ( MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; end case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_307)begin + `MmuPlugin_shared_State_binary_sequential_IDLE : begin + if(when_MmuPlugin_l217) begin MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; - MmuPlugin_shared_vpn_1 <= _zz_103[31 : 22]; - MmuPlugin_shared_vpn_0 <= _zz_103[21 : 12]; + MmuPlugin_shared_vpn_1 <= _zz_MmuPlugin_shared_vpn_0[31 : 22]; + MmuPlugin_shared_vpn_0 <= _zz_MmuPlugin_shared_vpn_0[21 : 12]; end end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin end default : begin end endcase - if(_zz_289)begin - if(_zz_290)begin - if(_zz_308)begin - MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin + if(when_MmuPlugin_l280) begin + MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6674,10 +7004,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_309)begin - MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_1) begin + MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6686,10 +7016,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_310)begin - MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_2) begin + MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6698,10 +7028,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_311)begin - MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_3) begin + MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6710,12 +7040,12 @@ module VexRiscv ( MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end end - if(_zz_291)begin - if(_zz_312)begin - MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l274_1) begin + if(when_MmuPlugin_l280_4) begin + MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6724,10 +7054,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_313)begin - MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_5) begin + MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6736,10 +7066,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_314)begin - MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_6) begin + MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6748,10 +7078,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_315)begin - MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_7) begin + MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6760,83 +7090,83 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end end end - _zz_131 <= _zz_40[11 : 7]; - _zz_132 <= _zz_50; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_sip_SEIP_INPUT <= externalInterruptS; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_278)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_163 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_163 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_316)begin - if(_zz_317)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_318)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_319)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end end - if(_zz_320)begin - if(_zz_321)begin + if(when_CsrPlugin_l946_1) begin + if(when_CsrPlugin_l952_3) begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_322)begin + if(when_CsrPlugin_l952_4) begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_323)begin + if(when_CsrPlugin_l952_5) begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_324)begin + if(when_CsrPlugin_l952_6) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_325)begin + if(when_CsrPlugin_l952_7) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_326)begin + if(when_CsrPlugin_l952_8) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_282)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_sepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -6844,7 +7174,7 @@ module VexRiscv ( CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -6852,439 +7182,453 @@ module VexRiscv ( end endcase end - if((memory_DivPlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_DivPlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_273)begin - if(_zz_302)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_423[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; end end end - if(_zz_303)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_167 ? (~ _zz_168) : _zz_168) + _zz_429); - memory_DivPlugin_rs2 <= ((_zz_166 ? (~ execute_RS2) : execute_RS2) + _zz_431); - memory_DivPlugin_div_needRevert <= ((_zz_167 ^ (_zz_166 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_35; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_55; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_53; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_54; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_25; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_22; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_19; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin + execute_to_memory_MEMORY_LRSC <= execute_MEMORY_LRSC; + end + if(when_Pipeline_l124_28) begin + memory_to_writeBack_MEMORY_LRSC <= memory_MEMORY_LRSC; + end + if(when_Pipeline_l124_29) begin decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_30) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; + if(when_Pipeline_l124_31) begin + decode_to_execute_IS_SFENCE_VMA2 <= decode_IS_SFENCE_VMA2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + if(when_Pipeline_l124_32) begin + decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_33) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_16; + if(when_Pipeline_l124_34) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_35) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_10; + if(when_Pipeline_l124_36) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + if(when_Pipeline_l124_37) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_39) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_40) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_41) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_52) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_53) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_54) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_56) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_57) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_31; + if(when_Pipeline_l124_60) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_32; + if(when_Pipeline_l124_61) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_62) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_63) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_64) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_65) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_66) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_67) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_68) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_69) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_70) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_770 <= (decode_INSTRUCTION[31 : 20] == 12'h302); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_771 <= (decode_INSTRUCTION[31 : 20] == 12'h303); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_324 <= (decode_INSTRUCTION[31 : 20] == 12'h144); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_260 <= (decode_INSTRUCTION[31 : 20] == 12'h104); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_261 <= (decode_INSTRUCTION[31 : 20] == 12'h105); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_321 <= (decode_INSTRUCTION[31 : 20] == 12'h141); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_320 <= (decode_INSTRUCTION[31 : 20] == 12'h140); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin execute_CsrPlugin_csr_322 <= (decode_INSTRUCTION[31 : 20] == 12'h142); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_323 <= (decode_INSTRUCTION[31 : 20] == 12'h143); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_24) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_25) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_26) begin execute_CsrPlugin_csr_2496 <= (decode_INSTRUCTION[31 : 20] == 12'h9c0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_27) begin execute_CsrPlugin_csr_3520 <= (decode_INSTRUCTION[31 : 20] == 12'hdc0); end - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_asid <= execute_CsrPlugin_writeData[30 : 22]; - MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_satp_asid <= CsrPlugin_csrMapping_writeDataSignal[30 : 22]; + MmuPlugin_satp_ppn <= CsrPlugin_csrMapping_writeDataSignal[19 : 0]; end end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_445[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_261)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_261) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_stvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_stvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_321)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_321) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_320)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_320) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_322)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_scause_interrupt <= _zz_476[0]; - CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_322) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_scause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_scause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_323)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_323) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_stval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end - always @ (posedge clk) begin + always @(posedge clk) begin DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin + if(debug_bus_cmd_ready) begin DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_50; + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; end - _zz_173 <= debug_bus_cmd_payload_address[2]; - if(_zz_280)begin + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin + always @(posedge clk) begin if(debugReset) begin DebugPlugin_resetIt <= 1'b0; DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + if(when_DebugPlugin_l225) begin DebugPlugin_godmode <= 1'b1; end - if(debug_bus_cmd_valid)begin - case(_zz_304) + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin + if(when_DebugPlugin_l260) begin DebugPlugin_resetIt <= 1'b1; end - if(debug_bus_cmd_payload_data[24])begin + if(when_DebugPlugin_l260_1) begin DebugPlugin_resetIt <= 1'b0; end - if(debug_bus_cmd_payload_data[17])begin + if(when_DebugPlugin_l261) begin DebugPlugin_haltIt <= 1'b1; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l261_1) begin DebugPlugin_haltIt <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l262) begin DebugPlugin_haltedByBreak <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l263) begin DebugPlugin_godmode <= 1'b0; end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end end end default : begin end endcase end - if(_zz_280)begin - if(_zz_281)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_284)begin - if(decode_arbitration_isValid)begin + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin DebugPlugin_haltIt <= 1'b1; end end @@ -7297,9 +7641,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_isLrsc, input io_cpu_execute_args_isAmo, @@ -7333,6 +7676,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -7348,9 +7692,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -7358,7 +7703,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -7367,38 +7712,23 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire _zz_19; - wire _zz_20; - wire _zz_21; - wire _zz_22; - wire [2:0] _zz_23; - wire [0:0] _zz_24; - wire [0:0] _zz_25; - wire [9:0] _zz_26; - wire [9:0] _zz_27; - wire [31:0] _zz_28; - wire [31:0] _zz_29; - wire [31:0] _zz_30; - wire [31:0] _zz_31; - wire [1:0] _zz_32; - wire [31:0] _zz_33; - wire [1:0] _zz_34; - wire [1:0] _zz_35; - wire [0:0] _zz_36; - wire [0:0] _zz_37; - wire [0:0] _zz_38; - wire [2:0] _zz_39; - wire [1:0] _zz_40; - wire [21:0] _zz_41; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [31:0] _zz_stageB_amo_addSub; + wire [31:0] _zz_stageB_amo_addSub_1; + wire [31:0] _zz_stageB_amo_addSub_2; + wire [31:0] _zz_stageB_amo_addSub_3; + wire [31:0] _zz_stageB_amo_addSub_4; + wire [1:0] _zz_stageB_amo_addSub_5; + wire [1:0] _zz_stageB_amo_addSub_6; + wire [1:0] _zz_stageB_amo_addSub_7; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -7423,38 +7753,45 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_isLrsc; reg stageA_request_isAmo; reg stageA_request_amoCtrl_swap; reg [2:0] stageA_request_amoCtrl_alu; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_isLrsc; reg stageB_request_isAmo; @@ -7462,6 +7799,7 @@ module DataCache ( reg [2:0] stageB_request_amoCtrl_alu; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -7479,25 +7817,36 @@ module DataCache ( reg [31:0] stageB_mmuRsp_ways_2_physical; reg stageB_mmuRsp_ways_3_sel; reg [31:0] stageB_mmuRsp_ways_3_physical; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; reg stageB_lrSc_reserved; + wire when_DataCache_l866; wire stageB_isExternalLsrc; wire stageB_isExternalAmo; reg [31:0] stageB_requestDataBypass; @@ -7506,14 +7855,26 @@ module DataCache ( wire [31:0] stageB_amo_addSub; wire stageB_amo_less; wire stageB_amo_selectRf; + wire [2:0] switch_Misc_l200; reg [31:0] stageB_amo_result; reg [31:0] stageB_amo_resultReg; reg stageB_amo_internal_resultRegValid; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l984; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l997; + wire when_DataCache_l1005; + wire when_DataCache_l1010; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -7525,73 +7886,62 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_42; - reg [7:0] _zz_43; - reg [7:0] _zz_44; - reg [7:0] _zz_45; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_15 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); - assign _zz_16 = (! stageB_amo_internal_resultRegValid); - assign _zz_17 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); - assign _zz_18 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_19 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); - assign _zz_20 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); - assign _zz_21 = (! stageB_flusher_hold); - assign _zz_22 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_23 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); - assign _zz_24 = _zz_4[0 : 0]; - assign _zz_25 = _zz_4[1 : 1]; - assign _zz_26 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_27 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_28 = ($signed(_zz_29) + $signed(_zz_33)); - assign _zz_29 = ($signed(_zz_30) + $signed(_zz_31)); - assign _zz_30 = stageB_request_data; - assign _zz_31 = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux); - assign _zz_32 = (stageB_amo_compare ? _zz_34 : _zz_35); - assign _zz_33 = {{30{_zz_32[1]}}, _zz_32}; - assign _zz_34 = 2'b01; - assign _zz_35 = 2'b00; - assign _zz_36 = 1'b1; - assign _zz_37 = (! stageB_lrSc_reserved); - assign _zz_38 = loader_counter_willIncrement; - assign _zz_39 = {2'd0, _zz_38}; - assign _zz_40 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_41 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_stageB_amo_addSub = ($signed(_zz_stageB_amo_addSub_1) + $signed(_zz_stageB_amo_addSub_4)); + assign _zz_stageB_amo_addSub_1 = ($signed(_zz_stageB_amo_addSub_2) + $signed(_zz_stageB_amo_addSub_3)); + assign _zz_stageB_amo_addSub_2 = io_cpu_writeBack_storeData[31 : 0]; + assign _zz_stageB_amo_addSub_3 = (stageB_amo_compare ? (~ stageB_dataMux[31 : 0]) : stageB_dataMux[31 : 0]); + assign _zz_stageB_amo_addSub_5 = (stageB_amo_compare ? _zz_stageB_amo_addSub_6 : _zz_stageB_amo_addSub_7); + assign _zz_stageB_amo_addSub_4 = {{30{_zz_stageB_amo_addSub_5[1]}}, _zz_stageB_amo_addSub_5}; + assign _zz_stageB_amo_addSub_6 = 2'b01; + assign _zz_stageB_amo_addSub_7 = 2'b00; + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_41; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_45, _zz_44, _zz_43, _zz_42}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_42 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_43 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_44 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_45 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -7606,327 +7956,348 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_24[0]; - assign ways_0_tagsReadRsp_error = _zz_25[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - if(stageB_request_isAmo)begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin dataWriteCmd_valid = 1'b0; end end - if(_zz_17)begin + if(when_DataCache_l1010) begin dataWriteCmd_valid = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_36[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_26)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_27)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(! _zz_15) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_14)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end - if(_zz_19)begin + if(when_DataCache_l984) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_15)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end - if(stageB_request_isAmo)begin - if(_zz_16)begin + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin io_cpu_writeBack_haltIt = 1'b1; end end - if(_zz_17)begin + if(when_DataCache_l1010) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); + assign when_DataCache_l866 = ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc); assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - always @ (*) begin - stageB_requestDataBypass = stageB_request_data; - if(stageB_request_isAmo)begin - stageB_requestDataBypass = stageB_amo_resultReg; + always @(*) begin + stageB_requestDataBypass = io_cpu_writeBack_storeData; + if(stageB_request_isAmo) begin + stageB_requestDataBypass[31 : 0] = stageB_amo_resultReg; end end assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == 2'b11); - assign stageB_amo_addSub = _zz_28; - assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31])); + assign stageB_amo_addSub = _zz_stageB_amo_addSub; + assign stageB_amo_less = ((io_cpu_writeBack_storeData[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : io_cpu_writeBack_storeData[31])); assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); - always @ (*) begin - case(_zz_23) + assign switch_Misc_l200 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); + always @(*) begin + case(switch_Misc_l200) 3'b000 : begin stageB_amo_result = stageB_amo_addSub; end 3'b001 : begin - stageB_amo_result = (stageB_request_data ^ stageB_dataMux); + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] ^ stageB_dataMux[31 : 0]); end 3'b010 : begin - stageB_amo_result = (stageB_request_data | stageB_dataMux); + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] | stageB_dataMux[31 : 0]); end 3'b011 : begin - stageB_amo_result = (stageB_request_data & stageB_dataMux); + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] & stageB_dataMux[31 : 0]); end default : begin - stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux); + stageB_amo_result = (stageB_amo_selectRf ? io_cpu_writeBack_storeData[31 : 0] : stageB_dataMux[31 : 0]); end endcase end - always @ (*) begin + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -7934,103 +8305,87 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_request_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - if(_zz_20)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_14)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); - if(_zz_19)begin + if(when_DataCache_l984) begin io_mem_cmd_valid = 1'b0; end end else begin - if(_zz_15)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end - if(stageB_request_isAmo)begin - if(_zz_16)begin + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin io_mem_cmd_valid = 1'b0; end end - if(_zz_20)begin + if(when_DataCache_l1005) begin io_mem_cmd_valid = 1'b0; end - if(_zz_17)begin + if(when_DataCache_l1010) begin io_mem_cmd_valid = 1'b0; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -8038,12 +8393,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(! _zz_15) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -8054,23 +8409,44 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l984 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l997 = (! stageB_amo_internal_resultRegValid); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1010 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end - if((stageB_request_isLrsc && stageB_request_wr))begin - io_cpu_writeBack_data = {31'd0, _zz_37}; - end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign io_cpu_writeBack_exclusiveOk = stageB_lrSc_reserved; + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_18)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -8078,26 +8454,29 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_39); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; stageA_request_isAmo <= io_cpu_execute_args_isAmo; @@ -8105,18 +8484,17 @@ module DataCache ( stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_isLrsc <= stageA_request_isLrsc; stageB_request_isAmo <= stageA_request_isAmo; @@ -8124,7 +8502,7 @@ module DataCache ( stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -8143,48 +8521,39 @@ module DataCache ( stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_21)begin - if(_zz_22)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end stageB_amo_internal_resultRegValid <= io_cpu_writeBack_isStuck; stageB_amo_resultReg <= stageB_amo_result; loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; stageB_lrSc_reserved <= 1'b0; loader_valid <= 1'b0; @@ -8193,27 +8562,29 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_21)begin - if(! _zz_22) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end - if(((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc))begin + if(when_DataCache_l866) begin stageB_lrSc_reserved <= (! stageB_request_wr); end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_lrSc_reserved <= stageB_lrSc_reserved; end `ifndef SYNTHESIS @@ -8221,28 +8592,27 @@ module DataCache ( assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_18)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_40[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -8297,18 +8667,14 @@ module InstructionCache ( input io_mem_rsp_valid, input [31:0] io_mem_rsp_payload_data, input io_mem_rsp_payload_error, - input [2:0] _zz_9, - input [31:0] _zz_10, + input [2:0] _zz_when_Fetcher_l398, + input [31:0] _zz_io_cpu_fetch_data_regNextWhen, input clk, input reset ); - reg [31:0] _zz_11; - reg [21:0] _zz_12; - wire _zz_13; - wire _zz_14; - wire [0:0] _zz_15; - wire [0:0] _zz_16; - wire [21:0] _zz_17; + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -8317,8 +8683,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -8332,22 +8703,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -8365,82 +8739,86 @@ module InstructionCache ( reg [31:0] decodeStage_mmuRsp_ways_2_physical; reg decodeStage_mmuRsp_ways_3_sel; reg [31:0] decodeStage_mmuRsp_ways_3_physical; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; + wire when_Fetcher_l398; (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - assign _zz_13 = (! lineLoader_flushCounter[7]); - assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_15 = _zz_8[0 : 0]; - assign _zz_16 = _zz_8[1 : 1]; - assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_11 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_12 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_13)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -8456,30 +8834,36 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_12; - assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000); + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -8487,51 +8871,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_14)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_13)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_14)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 8'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -8550,14 +8934,14 @@ module InstructionCache ( decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end - if((_zz_9 != 3'b000))begin - io_cpu_fetch_data_regNextWhen <= _zz_10; + if(when_Fetcher_l398) begin + io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v index dd57d2f..cc8e971 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v @@ -1,54 +1,54 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 - - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 - -`define MmuPlugin_shared_State_defaultEncoding_type [2:0] -`define MmuPlugin_shared_State_defaultEncoding_IDLE 3'b000 -`define MmuPlugin_shared_State_defaultEncoding_L1_CMD 3'b001 -`define MmuPlugin_shared_State_defaultEncoding_L1_RSP 3'b010 -`define MmuPlugin_shared_State_defaultEncoding_L0_CMD 3'b011 -`define MmuPlugin_shared_State_defaultEncoding_L0_RSP 3'b100 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 + +`define MmuPlugin_shared_State_binary_sequential_type [2:0] +`define MmuPlugin_shared_State_binary_sequential_IDLE 3'b000 +`define MmuPlugin_shared_State_binary_sequential_L1_CMD 3'b001 +`define MmuPlugin_shared_State_binary_sequential_L1_RSP 3'b010 +`define MmuPlugin_shared_State_binary_sequential_L0_CMD 3'b011 +`define MmuPlugin_shared_State_binary_sequential_L0_RSP 3'b100 module VexRiscv ( @@ -81,66 +81,42 @@ module VexRiscv ( input clk, input reset ); - wire _zz_192; - wire _zz_193; - wire _zz_194; - wire _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - reg _zz_200; - reg _zz_201; - reg [31:0] _zz_202; - reg _zz_203; - reg [31:0] _zz_204; - reg [1:0] _zz_205; - reg _zz_206; - reg _zz_207; - wire _zz_208; - wire [2:0] _zz_209; - reg _zz_210; - wire [31:0] _zz_211; - reg _zz_212; - reg _zz_213; - wire _zz_214; - wire [31:0] _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - wire _zz_219; - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire [3:0] _zz_224; - wire _zz_225; - wire _zz_226; - reg [31:0] _zz_227; - reg [31:0] _zz_228; - reg [31:0] _zz_229; - reg _zz_230; - reg _zz_231; - reg _zz_232; - reg [9:0] _zz_233; - reg [9:0] _zz_234; - reg [9:0] _zz_235; - reg [9:0] _zz_236; - reg _zz_237; - reg _zz_238; - reg _zz_239; - reg _zz_240; - reg _zz_241; - reg _zz_242; - reg _zz_243; - reg [9:0] _zz_244; - reg [9:0] _zz_245; - reg [9:0] _zz_246; - reg [9:0] _zz_247; - reg _zz_248; - reg _zz_249; - reg _zz_250; - reg _zz_251; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + reg dataCache_1_io_cpu_execute_isValid; + reg [31:0] dataCache_1_io_cpu_execute_address; + reg dataCache_1_io_cpu_execute_args_wr; + reg [1:0] dataCache_1_io_cpu_execute_args_size; + reg dataCache_1_io_cpu_execute_args_isLrsc; + wire dataCache_1_io_cpu_execute_args_amoCtrl_swap; + wire [2:0] dataCache_1_io_cpu_execute_args_amoCtrl_alu; + reg dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -163,6 +139,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -171,417 +148,323 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire _zz_256; - wire _zz_257; - wire _zz_258; - wire _zz_259; - wire _zz_260; - wire _zz_261; - wire _zz_262; - wire _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire _zz_267; - wire [1:0] _zz_268; - wire _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire _zz_279; - wire _zz_280; - wire _zz_281; - wire _zz_282; - wire _zz_283; - wire _zz_284; - wire _zz_285; - wire _zz_286; - wire _zz_287; - wire _zz_288; - wire _zz_289; - wire _zz_290; - wire _zz_291; - wire _zz_292; - wire _zz_293; - wire _zz_294; - wire _zz_295; - wire _zz_296; - wire _zz_297; - wire _zz_298; - wire _zz_299; - wire _zz_300; - wire _zz_301; - wire _zz_302; - wire _zz_303; - wire _zz_304; - wire _zz_305; - wire _zz_306; - wire _zz_307; - wire [1:0] _zz_308; - wire _zz_309; - wire [32:0] _zz_310; - wire [31:0] _zz_311; - wire [32:0] _zz_312; - wire [0:0] _zz_313; - wire [0:0] _zz_314; - wire [0:0] _zz_315; - wire [0:0] _zz_316; - wire [0:0] _zz_317; - wire [0:0] _zz_318; - wire [0:0] _zz_319; - wire [0:0] _zz_320; - wire [0:0] _zz_321; - wire [0:0] _zz_322; - wire [0:0] _zz_323; - wire [0:0] _zz_324; - wire [0:0] _zz_325; - wire [0:0] _zz_326; - wire [0:0] _zz_327; - wire [0:0] _zz_328; - wire [0:0] _zz_329; - wire [0:0] _zz_330; - wire [0:0] _zz_331; - wire [0:0] _zz_332; - wire [3:0] _zz_333; - wire [2:0] _zz_334; - wire [31:0] _zz_335; - wire [2:0] _zz_336; - wire [2:0] _zz_337; - wire [0:0] _zz_338; - wire [1:0] _zz_339; - wire [0:0] _zz_340; - wire [1:0] _zz_341; - wire [0:0] _zz_342; - wire [0:0] _zz_343; - wire [0:0] _zz_344; - wire [0:0] _zz_345; - wire [0:0] _zz_346; - wire [0:0] _zz_347; - wire [0:0] _zz_348; - wire [0:0] _zz_349; - wire [1:0] _zz_350; - wire [0:0] _zz_351; - wire [2:0] _zz_352; - wire [4:0] _zz_353; - wire [11:0] _zz_354; - wire [11:0] _zz_355; - wire [31:0] _zz_356; - wire [31:0] _zz_357; - wire [31:0] _zz_358; - wire [31:0] _zz_359; - wire [31:0] _zz_360; - wire [31:0] _zz_361; - wire [31:0] _zz_362; - wire [19:0] _zz_363; - wire [11:0] _zz_364; - wire [11:0] _zz_365; - wire [1:0] _zz_366; - wire [1:0] _zz_367; - wire [0:0] _zz_368; - wire [5:0] _zz_369; - wire [33:0] _zz_370; - wire [32:0] _zz_371; - wire [33:0] _zz_372; - wire [32:0] _zz_373; - wire [33:0] _zz_374; - wire [32:0] _zz_375; - wire [0:0] _zz_376; - wire [5:0] _zz_377; - wire [32:0] _zz_378; - wire [31:0] _zz_379; - wire [31:0] _zz_380; - wire [32:0] _zz_381; - wire [32:0] _zz_382; - wire [32:0] _zz_383; - wire [32:0] _zz_384; - wire [0:0] _zz_385; - wire [32:0] _zz_386; - wire [0:0] _zz_387; - wire [32:0] _zz_388; - wire [0:0] _zz_389; - wire [31:0] _zz_390; - wire [0:0] _zz_391; - wire [0:0] _zz_392; - wire [0:0] _zz_393; - wire [0:0] _zz_394; - wire [0:0] _zz_395; - wire [0:0] _zz_396; - wire [0:0] _zz_397; - wire [0:0] _zz_398; - wire [0:0] _zz_399; - wire [0:0] _zz_400; - wire [0:0] _zz_401; - wire [0:0] _zz_402; - wire [0:0] _zz_403; - wire [0:0] _zz_404; - wire [0:0] _zz_405; - wire [0:0] _zz_406; - wire [0:0] _zz_407; - wire [0:0] _zz_408; - wire [0:0] _zz_409; - wire [0:0] _zz_410; - wire [0:0] _zz_411; - wire [0:0] _zz_412; - wire [0:0] _zz_413; - wire [0:0] _zz_414; - wire [0:0] _zz_415; - wire [0:0] _zz_416; - wire [0:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire [0:0] _zz_420; - wire [0:0] _zz_421; - wire [0:0] _zz_422; - wire [0:0] _zz_423; - wire [0:0] _zz_424; - wire [0:0] _zz_425; - wire [0:0] _zz_426; - wire [0:0] _zz_427; - wire [0:0] _zz_428; - wire [0:0] _zz_429; - wire [0:0] _zz_430; - wire [0:0] _zz_431; - wire [0:0] _zz_432; - wire [0:0] _zz_433; - wire [0:0] _zz_434; - wire [0:0] _zz_435; - wire [26:0] _zz_436; - wire _zz_437; - wire _zz_438; - wire [1:0] _zz_439; - wire [31:0] _zz_440; - wire [31:0] _zz_441; - wire [31:0] _zz_442; - wire _zz_443; - wire [0:0] _zz_444; - wire [17:0] _zz_445; - wire [31:0] _zz_446; - wire [31:0] _zz_447; - wire [31:0] _zz_448; - wire _zz_449; - wire [0:0] _zz_450; - wire [11:0] _zz_451; - wire [31:0] _zz_452; - wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire _zz_455; - wire [0:0] _zz_456; - wire [5:0] _zz_457; - wire [31:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire _zz_461; - wire _zz_462; - wire [31:0] _zz_463; - wire [0:0] _zz_464; - wire [1:0] _zz_465; - wire [0:0] _zz_466; - wire [0:0] _zz_467; - wire _zz_468; - wire [0:0] _zz_469; - wire [28:0] _zz_470; - wire [31:0] _zz_471; - wire [31:0] _zz_472; - wire [31:0] _zz_473; - wire [0:0] _zz_474; - wire [0:0] _zz_475; - wire [1:0] _zz_476; - wire [1:0] _zz_477; - wire _zz_478; - wire [0:0] _zz_479; - wire [24:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire [31:0] _zz_485; - wire [31:0] _zz_486; - wire [0:0] _zz_487; - wire [0:0] _zz_488; - wire [2:0] _zz_489; - wire [2:0] _zz_490; - wire _zz_491; - wire [0:0] _zz_492; - wire [21:0] _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; - wire [31:0] _zz_496; - wire [31:0] _zz_497; - wire _zz_498; - wire _zz_499; - wire [31:0] _zz_500; - wire [31:0] _zz_501; - wire [1:0] _zz_502; - wire [1:0] _zz_503; - wire _zz_504; - wire [0:0] _zz_505; - wire [18:0] _zz_506; - wire [31:0] _zz_507; - wire [31:0] _zz_508; - wire [31:0] _zz_509; - wire [31:0] _zz_510; - wire [31:0] _zz_511; - wire [31:0] _zz_512; - wire _zz_513; - wire [0:0] _zz_514; - wire [0:0] _zz_515; - wire _zz_516; - wire [0:0] _zz_517; - wire [15:0] _zz_518; - wire [31:0] _zz_519; - wire [31:0] _zz_520; - wire _zz_521; - wire [0:0] _zz_522; - wire [0:0] _zz_523; - wire [31:0] _zz_524; - wire [31:0] _zz_525; - wire _zz_526; - wire [5:0] _zz_527; - wire [5:0] _zz_528; - wire _zz_529; - wire [0:0] _zz_530; - wire [11:0] _zz_531; - wire [31:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire [31:0] _zz_535; - wire _zz_536; - wire [0:0] _zz_537; - wire [2:0] _zz_538; - wire _zz_539; - wire [0:0] _zz_540; - wire [0:0] _zz_541; - wire _zz_542; - wire [4:0] _zz_543; - wire [4:0] _zz_544; - wire _zz_545; - wire [0:0] _zz_546; - wire [8:0] _zz_547; - wire [31:0] _zz_548; - wire [31:0] _zz_549; - wire [31:0] _zz_550; - wire _zz_551; - wire [0:0] _zz_552; - wire [0:0] _zz_553; - wire [31:0] _zz_554; - wire [31:0] _zz_555; - wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire [31:0] _zz_559; - wire [0:0] _zz_560; - wire [2:0] _zz_561; - wire [0:0] _zz_562; - wire [5:0] _zz_563; - wire [1:0] _zz_564; - wire [1:0] _zz_565; - wire _zz_566; - wire [0:0] _zz_567; - wire [6:0] _zz_568; - wire [31:0] _zz_569; - wire [31:0] _zz_570; - wire [31:0] _zz_571; - wire [31:0] _zz_572; - wire [31:0] _zz_573; - wire [31:0] _zz_574; - wire [31:0] _zz_575; - wire _zz_576; - wire [0:0] _zz_577; - wire [0:0] _zz_578; - wire _zz_579; - wire [0:0] _zz_580; - wire [3:0] _zz_581; - wire _zz_582; - wire [0:0] _zz_583; - wire [0:0] _zz_584; - wire [0:0] _zz_585; - wire [0:0] _zz_586; - wire _zz_587; - wire [0:0] _zz_588; - wire [4:0] _zz_589; - wire [31:0] _zz_590; - wire [31:0] _zz_591; - wire [31:0] _zz_592; - wire [31:0] _zz_593; - wire [31:0] _zz_594; - wire [31:0] _zz_595; - wire [31:0] _zz_596; - wire [31:0] _zz_597; - wire _zz_598; - wire [0:0] _zz_599; - wire [1:0] _zz_600; - wire [31:0] _zz_601; - wire [31:0] _zz_602; - wire [31:0] _zz_603; - wire [31:0] _zz_604; - wire [31:0] _zz_605; - wire _zz_606; - wire [4:0] _zz_607; - wire [4:0] _zz_608; - wire _zz_609; - wire [0:0] _zz_610; - wire [2:0] _zz_611; - wire [31:0] _zz_612; - wire [31:0] _zz_613; - wire [31:0] _zz_614; - wire _zz_615; - wire [31:0] _zz_616; - wire _zz_617; - wire [0:0] _zz_618; - wire [2:0] _zz_619; - wire [0:0] _zz_620; - wire [0:0] _zz_621; - wire [2:0] _zz_622; - wire [2:0] _zz_623; - wire _zz_624; - wire [0:0] _zz_625; - wire [0:0] _zz_626; - wire [31:0] _zz_627; - wire [31:0] _zz_628; - wire [31:0] _zz_629; - wire [31:0] _zz_630; - wire _zz_631; - wire [0:0] _zz_632; - wire [0:0] _zz_633; - wire [31:0] _zz_634; - wire [31:0] _zz_635; - wire _zz_636; - wire [0:0] _zz_637; - wire [0:0] _zz_638; - wire [0:0] _zz_639; - wire [1:0] _zz_640; - wire [1:0] _zz_641; - wire [1:0] _zz_642; - wire [0:0] _zz_643; - wire [0:0] _zz_644; - wire [31:0] _zz_645; - wire [31:0] _zz_646; - wire [31:0] _zz_647; - wire [31:0] _zz_648; - wire [31:0] _zz_649; - wire [31:0] _zz_650; - wire [31:0] _zz_651; - wire [31:0] _zz_652; - wire [31:0] _zz_653; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [17:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [11:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [5:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_18; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_19; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_20; + wire _zz_decode_LEGAL_INSTRUCTION_21; + wire _zz_decode_LEGAL_INSTRUCTION_22; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspRf; + wire [9:0] _zz_MmuPlugin_ports_0_cacheHitsCalc; + wire [9:0] _zz_MmuPlugin_ports_0_cacheHitsCalc_1; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_2; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_3; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_4; + wire _zz_MmuPlugin_ports_0_cacheHitsCalc_5; + reg _zz_MmuPlugin_ports_0_cacheLine_valid_4; + reg _zz_MmuPlugin_ports_0_cacheLine_exception; + reg _zz_MmuPlugin_ports_0_cacheLine_superPage; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0; + reg [9:0] _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1; + reg _zz_MmuPlugin_ports_0_cacheLine_allowRead; + reg _zz_MmuPlugin_ports_0_cacheLine_allowWrite; + reg _zz_MmuPlugin_ports_0_cacheLine_allowExecute; + reg _zz_MmuPlugin_ports_0_cacheLine_allowUser; + wire [1:0] _zz_MmuPlugin_ports_0_entryToReplace_valueNext; + wire [0:0] _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1; + wire [9:0] _zz_MmuPlugin_ports_1_cacheHitsCalc; + wire [9:0] _zz_MmuPlugin_ports_1_cacheHitsCalc_1; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_2; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_3; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_4; + wire _zz_MmuPlugin_ports_1_cacheHitsCalc_5; + reg _zz_MmuPlugin_ports_1_cacheLine_valid_4; + reg _zz_MmuPlugin_ports_1_cacheLine_exception; + reg _zz_MmuPlugin_ports_1_cacheLine_superPage; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0; + reg [9:0] _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1; + reg _zz_MmuPlugin_ports_1_cacheLine_allowRead; + reg _zz_MmuPlugin_ports_1_cacheLine_allowWrite; + reg _zz_MmuPlugin_ports_1_cacheLine_allowExecute; + reg _zz_MmuPlugin_ports_1_cacheLine_allowUser; + wire [1:0] _zz_MmuPlugin_ports_1_entryToReplace_valueNext; + wire [0:0] _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1; + wire [1:0] _zz__zz_MmuPlugin_shared_refills_2; + wire [31:0] _zz__zz_decode_IS_DIV; + wire [0:0] _zz__zz_decode_IS_DIV_1; + wire [1:0] _zz__zz_decode_IS_DIV_2; + wire [0:0] _zz__zz_decode_IS_DIV_3; + wire [0:0] _zz__zz_decode_IS_DIV_4; + wire _zz__zz_decode_IS_DIV_5; + wire [31:0] _zz__zz_decode_IS_DIV_6; + wire [0:0] _zz__zz_decode_IS_DIV_7; + wire [31:0] _zz__zz_decode_IS_DIV_8; + wire [31:0] _zz__zz_decode_IS_DIV_9; + wire [29:0] _zz__zz_decode_IS_DIV_10; + wire [0:0] _zz__zz_decode_IS_DIV_11; + wire [31:0] _zz__zz_decode_IS_DIV_12; + wire [0:0] _zz__zz_decode_IS_DIV_13; + wire [31:0] _zz__zz_decode_IS_DIV_14; + wire [1:0] _zz__zz_decode_IS_DIV_15; + wire [31:0] _zz__zz_decode_IS_DIV_16; + wire [31:0] _zz__zz_decode_IS_DIV_17; + wire [1:0] _zz__zz_decode_IS_DIV_18; + wire _zz__zz_decode_IS_DIV_19; + wire [31:0] _zz__zz_decode_IS_DIV_20; + wire [31:0] _zz__zz_decode_IS_DIV_21; + wire [0:0] _zz__zz_decode_IS_DIV_22; + wire [0:0] _zz__zz_decode_IS_DIV_23; + wire [31:0] _zz__zz_decode_IS_DIV_24; + wire [0:0] _zz__zz_decode_IS_DIV_25; + wire [31:0] _zz__zz_decode_IS_DIV_26; + wire [25:0] _zz__zz_decode_IS_DIV_27; + wire [2:0] _zz__zz_decode_IS_DIV_28; + wire [31:0] _zz__zz_decode_IS_DIV_29; + wire [31:0] _zz__zz_decode_IS_DIV_30; + wire _zz__zz_decode_IS_DIV_31; + wire _zz__zz_decode_IS_DIV_32; + wire [2:0] _zz__zz_decode_IS_DIV_33; + wire _zz__zz_decode_IS_DIV_34; + wire [31:0] _zz__zz_decode_IS_DIV_35; + wire [31:0] _zz__zz_decode_IS_DIV_36; + wire [0:0] _zz__zz_decode_IS_DIV_37; + wire [22:0] _zz__zz_decode_IS_DIV_38; + wire [1:0] _zz__zz_decode_IS_DIV_39; + wire [31:0] _zz__zz_decode_IS_DIV_40; + wire [31:0] _zz__zz_decode_IS_DIV_41; + wire [31:0] _zz__zz_decode_IS_DIV_42; + wire [31:0] _zz__zz_decode_IS_DIV_43; + wire [1:0] _zz__zz_decode_IS_DIV_44; + wire _zz__zz_decode_IS_DIV_45; + wire [0:0] _zz__zz_decode_IS_DIV_46; + wire [19:0] _zz__zz_decode_IS_DIV_47; + wire [0:0] _zz__zz_decode_IS_DIV_48; + wire [0:0] _zz__zz_decode_IS_DIV_49; + wire _zz__zz_decode_IS_DIV_50; + wire [31:0] _zz__zz_decode_IS_DIV_51; + wire [0:0] _zz__zz_decode_IS_DIV_52; + wire _zz__zz_decode_IS_DIV_53; + wire [0:0] _zz__zz_decode_IS_DIV_54; + wire [31:0] _zz__zz_decode_IS_DIV_55; + wire [1:0] _zz__zz_decode_IS_DIV_56; + wire [31:0] _zz__zz_decode_IS_DIV_57; + wire [31:0] _zz__zz_decode_IS_DIV_58; + wire [31:0] _zz__zz_decode_IS_DIV_59; + wire [31:0] _zz__zz_decode_IS_DIV_60; + wire [16:0] _zz__zz_decode_IS_DIV_61; + wire _zz__zz_decode_IS_DIV_62; + wire [0:0] _zz__zz_decode_IS_DIV_63; + wire [31:0] _zz__zz_decode_IS_DIV_64; + wire [0:0] _zz__zz_decode_IS_DIV_65; + wire _zz__zz_decode_IS_DIV_66; + wire _zz__zz_decode_IS_DIV_67; + wire [31:0] _zz__zz_decode_IS_DIV_68; + wire [0:0] _zz__zz_decode_IS_DIV_69; + wire [31:0] _zz__zz_decode_IS_DIV_70; + wire [31:0] _zz__zz_decode_IS_DIV_71; + wire [3:0] _zz__zz_decode_IS_DIV_72; + wire _zz__zz_decode_IS_DIV_73; + wire [31:0] _zz__zz_decode_IS_DIV_74; + wire [0:0] _zz__zz_decode_IS_DIV_75; + wire [31:0] _zz__zz_decode_IS_DIV_76; + wire [31:0] _zz__zz_decode_IS_DIV_77; + wire [1:0] _zz__zz_decode_IS_DIV_78; + wire _zz__zz_decode_IS_DIV_79; + wire [31:0] _zz__zz_decode_IS_DIV_80; + wire _zz__zz_decode_IS_DIV_81; + wire [31:0] _zz__zz_decode_IS_DIV_82; + wire [0:0] _zz__zz_decode_IS_DIV_83; + wire [0:0] _zz__zz_decode_IS_DIV_84; + wire [31:0] _zz__zz_decode_IS_DIV_85; + wire [31:0] _zz__zz_decode_IS_DIV_86; + wire [1:0] _zz__zz_decode_IS_DIV_87; + wire _zz__zz_decode_IS_DIV_88; + wire [31:0] _zz__zz_decode_IS_DIV_89; + wire _zz__zz_decode_IS_DIV_90; + wire [31:0] _zz__zz_decode_IS_DIV_91; + wire [12:0] _zz__zz_decode_IS_DIV_92; + wire [0:0] _zz__zz_decode_IS_DIV_93; + wire [31:0] _zz__zz_decode_IS_DIV_94; + wire [31:0] _zz__zz_decode_IS_DIV_95; + wire [0:0] _zz__zz_decode_IS_DIV_96; + wire _zz__zz_decode_IS_DIV_97; + wire [0:0] _zz__zz_decode_IS_DIV_98; + wire [3:0] _zz__zz_decode_IS_DIV_99; + wire _zz__zz_decode_IS_DIV_100; + wire [31:0] _zz__zz_decode_IS_DIV_101; + wire [0:0] _zz__zz_decode_IS_DIV_102; + wire [31:0] _zz__zz_decode_IS_DIV_103; + wire [31:0] _zz__zz_decode_IS_DIV_104; + wire [1:0] _zz__zz_decode_IS_DIV_105; + wire _zz__zz_decode_IS_DIV_106; + wire [31:0] _zz__zz_decode_IS_DIV_107; + wire _zz__zz_decode_IS_DIV_108; + wire [31:0] _zz__zz_decode_IS_DIV_109; + wire [0:0] _zz__zz_decode_IS_DIV_110; + wire [6:0] _zz__zz_decode_IS_DIV_111; + wire [0:0] _zz__zz_decode_IS_DIV_112; + wire [31:0] _zz__zz_decode_IS_DIV_113; + wire [31:0] _zz__zz_decode_IS_DIV_114; + wire [4:0] _zz__zz_decode_IS_DIV_115; + wire _zz__zz_decode_IS_DIV_116; + wire [31:0] _zz__zz_decode_IS_DIV_117; + wire [0:0] _zz__zz_decode_IS_DIV_118; + wire [31:0] _zz__zz_decode_IS_DIV_119; + wire [31:0] _zz__zz_decode_IS_DIV_120; + wire [2:0] _zz__zz_decode_IS_DIV_121; + wire _zz__zz_decode_IS_DIV_122; + wire [31:0] _zz__zz_decode_IS_DIV_123; + wire [0:0] _zz__zz_decode_IS_DIV_124; + wire [0:0] _zz__zz_decode_IS_DIV_125; + wire [31:0] _zz__zz_decode_IS_DIV_126; + wire [31:0] _zz__zz_decode_IS_DIV_127; + wire [6:0] _zz__zz_decode_IS_DIV_128; + wire [9:0] _zz__zz_decode_IS_DIV_129; + wire _zz__zz_decode_IS_DIV_130; + wire [0:0] _zz__zz_decode_IS_DIV_131; + wire [0:0] _zz__zz_decode_IS_DIV_132; + wire [31:0] _zz__zz_decode_IS_DIV_133; + wire [31:0] _zz__zz_decode_IS_DIV_134; + wire [0:0] _zz__zz_decode_IS_DIV_135; + wire [1:0] _zz__zz_decode_IS_DIV_136; + wire _zz__zz_decode_IS_DIV_137; + wire [31:0] _zz__zz_decode_IS_DIV_138; + wire [1:0] _zz__zz_decode_IS_DIV_139; + wire [7:0] _zz__zz_decode_IS_DIV_140; + wire _zz__zz_decode_IS_DIV_141; + wire _zz__zz_decode_IS_DIV_142; + wire [31:0] _zz__zz_decode_IS_DIV_143; + wire [0:0] _zz__zz_decode_IS_DIV_144; + wire [0:0] _zz__zz_decode_IS_DIV_145; + wire [31:0] _zz__zz_decode_IS_DIV_146; + wire [31:0] _zz__zz_decode_IS_DIV_147; + wire [0:0] _zz__zz_decode_IS_DIV_148; + wire [5:0] _zz__zz_decode_IS_DIV_149; + wire _zz__zz_decode_IS_DIV_150; + wire [0:0] _zz__zz_decode_IS_DIV_151; + wire [31:0] _zz__zz_decode_IS_DIV_152; + wire [31:0] _zz__zz_decode_IS_DIV_153; + wire [3:0] _zz__zz_decode_IS_DIV_154; + wire _zz__zz_decode_IS_DIV_155; + wire [31:0] _zz__zz_decode_IS_DIV_156; + wire [0:0] _zz__zz_decode_IS_DIV_157; + wire [31:0] _zz__zz_decode_IS_DIV_158; + wire [31:0] _zz__zz_decode_IS_DIV_159; + wire [1:0] _zz__zz_decode_IS_DIV_160; + wire _zz__zz_decode_IS_DIV_161; + wire [0:0] _zz__zz_decode_IS_DIV_162; + wire [1:0] _zz__zz_decode_IS_DIV_163; + wire _zz__zz_decode_IS_DIV_164; + wire [31:0] _zz__zz_decode_IS_DIV_165; + wire [1:0] _zz__zz_decode_IS_DIV_166; + wire [3:0] _zz__zz_decode_IS_DIV_167; + wire _zz__zz_decode_IS_DIV_168; + wire [0:0] _zz__zz_decode_IS_DIV_169; + wire [31:0] _zz__zz_decode_IS_DIV_170; + wire [31:0] _zz__zz_decode_IS_DIV_171; + wire [1:0] _zz__zz_decode_IS_DIV_172; + wire _zz__zz_decode_IS_DIV_173; + wire _zz__zz_decode_IS_DIV_174; + wire [0:0] _zz__zz_decode_IS_DIV_175; + wire [2:0] _zz__zz_decode_IS_DIV_176; + wire [0:0] _zz__zz_decode_IS_DIV_177; + wire [0:0] _zz__zz_decode_IS_DIV_178; + wire [2:0] _zz__zz_decode_IS_DIV_179; + wire [1:0] _zz__zz_decode_IS_DIV_180; + wire _zz__zz_decode_IS_DIV_181; + wire [0:0] _zz__zz_decode_IS_DIV_182; + wire [0:0] _zz__zz_decode_IS_DIV_183; + wire _zz__zz_decode_IS_DIV_184; + wire _zz__zz_decode_IS_DIV_185; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [5:0] _zz_memory_MulDivIterativePlugin_mul_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_mul_counter_valueNext_1; + wire [33:0] _zz_memory_MulDivIterativePlugin_accumulator; + wire [33:0] _zz_memory_MulDivIterativePlugin_accumulator_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_accumulator_2; + wire [33:0] _zz_memory_MulDivIterativePlugin_accumulator_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_accumulator_4; + wire [32:0] _zz_memory_MulDivIterativePlugin_accumulator_5; + wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; + wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_3; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_4; + wire [31:0] _zz_memory_MulDivIterativePlugin_rs2; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_1; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; wire execute_IS_DBUS_SHARING; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_SRC2_FORCE_ZERO; @@ -589,51 +472,51 @@ module VexRiscv ( wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `BranchCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; - wire memory_IS_SFENCE_VMA; - wire execute_IS_SFENCE_VMA; wire decode_IS_SFENCE_VMA; + wire decode_IS_SFENCE_VMA2; wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_LRSC; wire memory_MEMORY_WR; wire decode_MEMORY_WR; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `Src2CtrlEnum_defaultEncoding_type _zz_20; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `AluCtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; - wire `Src1CtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; @@ -649,21 +532,22 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_29; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_30; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; + wire execute_IS_SFENCE_VMA; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire [31:0] execute_RS1; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_31; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_32; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -673,54 +557,55 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_33; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_34; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_35; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_36; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_37; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_38; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_39; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_40; - wire [31:0] _zz_41; - wire _zz_42; - reg _zz_43; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_44; - wire `BranchCtrlEnum_defaultEncoding_type _zz_45; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_46; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_47; - wire `Src2CtrlEnum_defaultEncoding_type _zz_48; - wire `AluCtrlEnum_defaultEncoding_type _zz_49; - wire `Src1CtrlEnum_defaultEncoding_type _zz_50; - wire writeBack_IS_SFENCE_VMA; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + wire execute_IS_SFENCE_VMA2; wire writeBack_IS_DBUS_SHARING; wire memory_IS_DBUS_SHARING; - reg [31:0] _zz_51; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_LRSC; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_ENABLE; - wire execute_MEMORY_AMO; - wire execute_MEMORY_LRSC; + reg execute_MEMORY_AMO; + reg execute_MEMORY_LRSC; wire execute_MEMORY_FORCE_CONSTISTENCY; wire execute_MEMORY_MANAGMENT; wire [31:0] execute_RS2; @@ -730,7 +615,7 @@ module VexRiscv ( wire [31:0] execute_INSTRUCTION; wire decode_MEMORY_AMO; wire decode_MEMORY_LRSC; - reg _zz_52; + reg _zz_decode_MEMORY_FORCE_CONSTISTENCY; wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_4; @@ -738,8 +623,8 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_53; - reg [31:0] _zz_54; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -830,7 +715,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -883,6 +768,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -903,28 +793,34 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_55; - wire [3:0] _zz_56; - wire _zz_57; - wire _zz_58; - wire _zz_59; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -954,20 +850,24 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_3_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_3_output_payload; reg IBusCachedPlugin_iBusRsp_stages_3_halt; - wire _zz_60; - wire _zz_61; - wire _zz_62; - wire _zz_63; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_3_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_64; - wire _zz_65; - reg _zz_66; - wire _zz_67; - reg _zz_68; - reg [31:0] _zz_69; - wire _zz_70; - reg _zz_71; - reg [31:0] _zz_72; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -975,12 +875,20 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l329_4; reg IBusCachedPlugin_injector_nextPcCalc_valids_5; + wire when_Fetcher_l329_5; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -988,7 +896,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_73; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -996,23 +904,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -1020,27 +933,47 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_74; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; + wire when_DBusCachedPlugin_l311; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_75; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_76; - reg [31:0] _zz_77; - wire _zz_78; - reg [31:0] _zz_79; + reg [31:0] writeBack_DBusCachedPlugin_rspRf; + wire when_DBusCachedPlugin_l474; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire when_DBusCachedPlugin_l484; reg DBusCachedPlugin_forceDatapath; + wire when_DBusCachedPlugin_l498; + wire when_DBusCachedPlugin_l499; + wire MmuPlugin_dBusAccess_cmd_fire; reg MmuPlugin_status_sum; reg MmuPlugin_status_mxr; reg MmuPlugin_status_mprv; @@ -1093,12 +1026,14 @@ module VexRiscv ( reg MmuPlugin_ports_0_cache_3_allowUser; wire MmuPlugin_ports_0_dirty; reg MmuPlugin_ports_0_requireMmuLockupCalc; - reg [3:0] MmuPlugin_ports_0_cacheHitsCalc; + wire when_MmuPlugin_l125; + wire when_MmuPlugin_l126; + wire [3:0] MmuPlugin_ports_0_cacheHitsCalc; wire MmuPlugin_ports_0_cacheHit; - wire _zz_80; - wire _zz_81; - wire _zz_82; - wire [1:0] _zz_83; + wire _zz_MmuPlugin_ports_0_cacheLine_valid; + wire _zz_MmuPlugin_ports_0_cacheLine_valid_1; + wire _zz_MmuPlugin_ports_0_cacheLine_valid_2; + wire [1:0] _zz_MmuPlugin_ports_0_cacheLine_valid_3; wire MmuPlugin_ports_0_cacheLine_valid; wire MmuPlugin_ports_0_cacheLine_exception; wire MmuPlugin_ports_0_cacheLine_superPage; @@ -1162,12 +1097,15 @@ module VexRiscv ( reg MmuPlugin_ports_1_cache_3_allowUser; wire MmuPlugin_ports_1_dirty; reg MmuPlugin_ports_1_requireMmuLockupCalc; - reg [3:0] MmuPlugin_ports_1_cacheHitsCalc; + wire when_MmuPlugin_l125_1; + wire when_MmuPlugin_l126_1; + wire when_MmuPlugin_l128; + wire [3:0] MmuPlugin_ports_1_cacheHitsCalc; wire MmuPlugin_ports_1_cacheHit; - wire _zz_84; - wire _zz_85; - wire _zz_86; - wire [1:0] _zz_87; + wire _zz_MmuPlugin_ports_1_cacheLine_valid; + wire _zz_MmuPlugin_ports_1_cacheLine_valid_1; + wire _zz_MmuPlugin_ports_1_cacheLine_valid_2; + wire [1:0] _zz_MmuPlugin_ports_1_cacheLine_valid_3; wire MmuPlugin_ports_1_cacheLine_valid; wire MmuPlugin_ports_1_cacheLine_exception; wire MmuPlugin_ports_1_cacheLine_superPage; @@ -1185,7 +1123,7 @@ module VexRiscv ( reg [1:0] MmuPlugin_ports_1_entryToReplace_value; wire MmuPlugin_ports_1_entryToReplace_willOverflowIfInc; wire MmuPlugin_ports_1_entryToReplace_willOverflow; - reg `MmuPlugin_shared_State_defaultEncoding_type MmuPlugin_shared_state_1; + reg `MmuPlugin_shared_State_binary_sequential_type MmuPlugin_shared_state_1; reg [9:0] MmuPlugin_shared_vpn_0; reg [9:0] MmuPlugin_shared_vpn_1; reg [1:0] MmuPlugin_shared_portSortedOh; @@ -1206,6 +1144,7 @@ module VexRiscv ( wire [11:0] MmuPlugin_shared_dBusRsp_pte_PPN1; wire MmuPlugin_shared_dBusRsp_exception; wire MmuPlugin_shared_dBusRsp_leaf; + wire when_MmuPlugin_l205; reg MmuPlugin_shared_pteBuffer_V; reg MmuPlugin_shared_pteBuffer_R; reg MmuPlugin_shared_pteBuffer_W; @@ -1217,29 +1156,44 @@ module VexRiscv ( reg [1:0] MmuPlugin_shared_pteBuffer_RSW; reg [9:0] MmuPlugin_shared_pteBuffer_PPN0; reg [11:0] MmuPlugin_shared_pteBuffer_PPN1; - reg [1:0] _zz_88; - wire [1:0] _zz_89; - reg [1:0] _zz_90; + wire [1:0] _zz_MmuPlugin_shared_refills; + reg [1:0] _zz_MmuPlugin_shared_refills_1; wire [1:0] MmuPlugin_shared_refills; - wire [1:0] _zz_91; - reg [1:0] _zz_92; - wire [31:0] _zz_93; - wire [34:0] _zz_94; - wire _zz_95; - wire _zz_96; - wire _zz_97; - wire _zz_98; - wire _zz_99; - wire _zz_100; - wire _zz_101; - wire _zz_102; - wire `Src1CtrlEnum_defaultEncoding_type _zz_103; - wire `AluCtrlEnum_defaultEncoding_type _zz_104; - wire `Src2CtrlEnum_defaultEncoding_type _zz_105; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_106; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_107; - wire `BranchCtrlEnum_defaultEncoding_type _zz_108; - wire `EnvCtrlEnum_defaultEncoding_type _zz_109; + wire [1:0] _zz_MmuPlugin_shared_refills_2; + reg [1:0] _zz_MmuPlugin_shared_refills_3; + wire when_MmuPlugin_l217; + wire [31:0] _zz_MmuPlugin_shared_vpn_0; + wire when_MmuPlugin_l243; + wire when_MmuPlugin_l272; + wire when_MmuPlugin_l274; + wire when_MmuPlugin_l280; + wire when_MmuPlugin_l280_1; + wire when_MmuPlugin_l280_2; + wire when_MmuPlugin_l280_3; + wire when_MmuPlugin_l274_1; + wire when_MmuPlugin_l280_4; + wire when_MmuPlugin_l280_5; + wire when_MmuPlugin_l280_6; + wire when_MmuPlugin_l280_7; + wire when_MmuPlugin_l304; + wire [35:0] _zz_decode_IS_DIV; + wire _zz_decode_IS_DIV_1; + wire _zz_decode_IS_DIV_2; + wire _zz_decode_IS_DIV_3; + wire _zz_decode_IS_DIV_4; + wire _zz_decode_IS_DIV_5; + wire _zz_decode_IS_DIV_6; + wire _zz_decode_IS_DIV_7; + wire _zz_decode_IS_DIV_8; + wire _zz_decode_IS_DIV_9; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -1247,47 +1201,65 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_110; + reg _zz_2; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_111; - reg [31:0] _zz_112; - wire _zz_113; - reg [19:0] _zz_114; - wire _zz_115; - reg [19:0] _zz_116; - reg [31:0] _zz_117; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_118; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_119; - reg _zz_120; - reg _zz_121; - reg _zz_122; - reg [4:0] _zz_123; - reg [31:0] _zz_124; - wire _zz_125; - wire _zz_126; - wire _zz_127; - wire _zz_128; - wire _zz_129; - wire _zz_130; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_131; - reg _zz_132; - reg _zz_133; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_DO; + reg _zz_execute_BRANCH_DO_1; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_134; - reg [10:0] _zz_135; - wire _zz_136; - reg [19:0] _zz_137; - wire _zz_138; - reg [18:0] _zz_139; - reg [31:0] _zz_140; + wire _zz_execute_BranchPlugin_branch_src2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; - reg [1:0] _zz_141; + reg [1:0] _zz_CsrPlugin_privilege; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1344,12 +1316,14 @@ module VexRiscv ( reg [21:0] CsrPlugin_satp_PPN; reg [8:0] CsrPlugin_satp_ASID; reg [0:0] CsrPlugin_satp_MODE; - wire _zz_142; - wire _zz_143; - wire _zz_144; - wire _zz_145; - wire _zz_146; - wire _zz_147; + reg CsrPlugin_rescheduleLogic_rescheduleNext; + wire when_CsrPlugin_l803; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; + wire _zz_when_CsrPlugin_l952_3; + wire _zz_when_CsrPlugin_l952_4; + wire _zz_when_CsrPlugin_l952_5; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1361,36 +1335,81 @@ module VexRiscv ( reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; reg [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire when_CsrPlugin_l866; + wire when_CsrPlugin_l866_1; + wire when_CsrPlugin_l866_2; + wire when_CsrPlugin_l866_3; + wire when_CsrPlugin_l866_4; + wire when_CsrPlugin_l866_5; + wire when_CsrPlugin_l866_6; + wire when_CsrPlugin_l866_7; + wire when_CsrPlugin_l866_8; + wire when_CsrPlugin_l866_9; + wire when_CsrPlugin_l866_10; + wire when_CsrPlugin_l866_11; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_148; - wire _zz_149; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l946_1; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; + wire when_CsrPlugin_l952_3; + wire when_CsrPlugin_l952_4; + wire when_CsrPlugin_l952_5; + wire when_CsrPlugin_l952_6; + wire when_CsrPlugin_l952_7; + wire when_CsrPlugin_l952_8; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; reg [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg [32:0] memory_MulDivIterativePlugin_rs1; reg [31:0] memory_MulDivIterativePlugin_rs2; @@ -1402,6 +1421,10 @@ module VexRiscv ( reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + wire when_MulDivIterativePlugin_l96; + wire when_MulDivIterativePlugin_l97; + wire when_MulDivIterativePlugin_l100; + wire when_MulDivIterativePlugin_l110; reg memory_MulDivIterativePlugin_div_needRevert; reg memory_MulDivIterativePlugin_div_counter_willIncrement; reg memory_MulDivIterativePlugin_div_counter_willClear; @@ -1410,215 +1433,322 @@ module VexRiscv ( wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; wire memory_MulDivIterativePlugin_div_counter_willOverflow; reg memory_MulDivIterativePlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_150; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [31:0] _zz_151; - wire _zz_152; - wire _zz_153; - reg [32:0] _zz_154; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_MulDivIterativePlugin_rs1; + wire _zz_memory_MulDivIterativePlugin_rs1_1; + reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_155; - wire [31:0] _zz_156; - reg [31:0] _zz_157; - wire [31:0] _zz_158; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_LRSC; + wire when_Pipeline_l124_27; + reg execute_to_memory_MEMORY_LRSC; + wire when_Pipeline_l124_28; + reg memory_to_writeBack_MEMORY_LRSC; + wire when_Pipeline_l124_29; reg decode_to_execute_MEMORY_AMO; + wire when_Pipeline_l124_30; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_31; + reg decode_to_execute_IS_SFENCE_VMA2; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_SFENCE_VMA; - reg execute_to_memory_IS_SFENCE_VMA; - reg memory_to_writeBack_IS_SFENCE_VMA; + wire when_Pipeline_l124_33; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_34; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_35; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_36; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_37; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_38; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_39; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_40; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_41; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_43; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_44; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_45; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_46; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_47; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_48; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_49; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_50; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_51; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_52; reg decode_to_execute_CSR_READ_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_53; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_54; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_55; reg execute_to_memory_IS_DBUS_SHARING; + wire when_Pipeline_l124_56; reg memory_to_writeBack_IS_DBUS_SHARING; + wire when_Pipeline_l124_57; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_58; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_59; reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_60; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_61; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_256; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_384; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_770; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_771; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_324; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_260; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_261; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_321; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_320; + wire when_CsrPlugin_l1264_22; reg execute_CsrPlugin_csr_322; + wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_323; + wire when_CsrPlugin_l1264_24; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_25; reg execute_CsrPlugin_csr_4032; + wire when_CsrPlugin_l1264_26; reg execute_CsrPlugin_csr_2496; + wire when_CsrPlugin_l1264_27; reg execute_CsrPlugin_csr_3520; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [2:0] _zz_183; - reg _zz_184; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_185; - wire _zz_186; - wire _zz_187; - wire _zz_188; - wire _zz_189; - wire _zz_190; - reg _zz_191; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [31:0] _zz_10_string; - reg [71:0] _zz_11_string; - reg [71:0] _zz_12_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; - reg [71:0] _zz_15_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_16_string; - reg [39:0] _zz_17_string; - reg [39:0] _zz_18_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_19_string; - reg [23:0] _zz_20_string; - reg [23:0] _zz_21_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_22_string; - reg [63:0] _zz_23_string; - reg [63:0] _zz_24_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_25_string; - reg [95:0] _zz_26_string; - reg [95:0] _zz_27_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_29_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_30_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_31_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_34_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_35_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_37_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_38_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_39_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_40_string; - reg [39:0] _zz_44_string; - reg [31:0] _zz_45_string; - reg [71:0] _zz_46_string; - reg [39:0] _zz_47_string; - reg [23:0] _zz_48_string; - reg [63:0] _zz_49_string; - reg [95:0] _zz_50_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [47:0] MmuPlugin_shared_state_1_string; - reg [95:0] _zz_103_string; - reg [63:0] _zz_104_string; - reg [23:0] _zz_105_string; - reg [39:0] _zz_106_string; - reg [71:0] _zz_107_string; - reg [31:0] _zz_108_string; - reg [39:0] _zz_109_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1633,1420 +1763,1328 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_252 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_253 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_254 = 1'b1; - assign _zz_255 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_256 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_257 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_258 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_259 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_260 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_261 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_262 = ((_zz_197 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_263 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_264 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_265 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_268 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_269 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); - assign _zz_270 = (! dataCache_1_io_cpu_execute_refilling); - assign _zz_271 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_272 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); - assign _zz_273 = MmuPlugin_shared_portSortedOh[0]; - assign _zz_274 = MmuPlugin_shared_portSortedOh[1]; - assign _zz_275 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_276 = (1'b0 || (! 1'b1)); - assign _zz_277 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_278 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_279 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_280 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_281 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_282 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_283 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_284 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_285 = (! memory_arbitration_isStuck); - assign _zz_286 = (iBus_cmd_valid || (_zz_183 != 3'b000)); - assign _zz_287 = (_zz_226 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_288 = (MmuPlugin_shared_refills != 2'b00); - assign _zz_289 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); - assign _zz_290 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); - assign _zz_291 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); - assign _zz_292 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); - assign _zz_293 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); - assign _zz_294 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); - assign _zz_295 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); - assign _zz_296 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); - assign _zz_297 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); - assign _zz_298 = ((_zz_142 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); - assign _zz_299 = ((_zz_143 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); - assign _zz_300 = ((_zz_144 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); - assign _zz_301 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_302 = ((_zz_142 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); - assign _zz_303 = ((_zz_143 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); - assign _zz_304 = ((_zz_144 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); - assign _zz_305 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_306 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_307 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_308 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_309 = execute_INSTRUCTION[13]; - assign _zz_310 = ($signed(_zz_312) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_311 = _zz_310[31 : 0]; - assign _zz_312 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_313 = _zz_94[34 : 34]; - assign _zz_314 = _zz_94[33 : 33]; - assign _zz_315 = _zz_94[32 : 32]; - assign _zz_316 = _zz_94[31 : 31]; - assign _zz_317 = _zz_94[28 : 28]; - assign _zz_318 = _zz_94[21 : 21]; - assign _zz_319 = _zz_94[20 : 20]; - assign _zz_320 = _zz_94[19 : 19]; - assign _zz_321 = _zz_94[13 : 13]; - assign _zz_322 = _zz_94[12 : 12]; - assign _zz_323 = _zz_94[11 : 11]; - assign _zz_324 = _zz_94[17 : 17]; - assign _zz_325 = _zz_94[5 : 5]; - assign _zz_326 = _zz_94[3 : 3]; - assign _zz_327 = _zz_94[18 : 18]; - assign _zz_328 = _zz_94[10 : 10]; - assign _zz_329 = _zz_94[16 : 16]; - assign _zz_330 = _zz_94[15 : 15]; - assign _zz_331 = _zz_94[4 : 4]; - assign _zz_332 = _zz_94[0 : 0]; - assign _zz_333 = (_zz_55 - 4'b0001); - assign _zz_334 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_335 = {29'd0, _zz_334}; - assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_338 = MmuPlugin_ports_0_entryToReplace_willIncrement; - assign _zz_339 = {1'd0, _zz_338}; - assign _zz_340 = MmuPlugin_ports_1_entryToReplace_willIncrement; - assign _zz_341 = {1'd0, _zz_340}; - assign _zz_342 = MmuPlugin_shared_dBusRspStaged_payload_data[0 : 0]; - assign _zz_343 = MmuPlugin_shared_dBusRspStaged_payload_data[1 : 1]; - assign _zz_344 = MmuPlugin_shared_dBusRspStaged_payload_data[2 : 2]; - assign _zz_345 = MmuPlugin_shared_dBusRspStaged_payload_data[3 : 3]; - assign _zz_346 = MmuPlugin_shared_dBusRspStaged_payload_data[4 : 4]; - assign _zz_347 = MmuPlugin_shared_dBusRspStaged_payload_data[5 : 5]; - assign _zz_348 = MmuPlugin_shared_dBusRspStaged_payload_data[6 : 6]; - assign _zz_349 = MmuPlugin_shared_dBusRspStaged_payload_data[7 : 7]; - assign _zz_350 = (_zz_90 - 2'b01); - assign _zz_351 = execute_SRC_LESS; - assign _zz_352 = 3'b100; - assign _zz_353 = execute_INSTRUCTION[19 : 15]; - assign _zz_354 = execute_INSTRUCTION[31 : 20]; - assign _zz_355 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_356 = ($signed(_zz_357) + $signed(_zz_360)); - assign _zz_357 = ($signed(_zz_358) + $signed(_zz_359)); - assign _zz_358 = execute_SRC1; - assign _zz_359 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_360 = (execute_SRC_USE_SUB_LESS ? _zz_361 : _zz_362); - assign _zz_361 = 32'h00000001; - assign _zz_362 = 32'h0; - assign _zz_363 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_364 = execute_INSTRUCTION[31 : 20]; - assign _zz_365 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_366 = (_zz_148 & (~ _zz_367)); - assign _zz_367 = (_zz_148 - 2'b01); - assign _zz_368 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_369 = {5'd0, _zz_368}; - assign _zz_370 = (_zz_372 + _zz_374); - assign _zz_371 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_372 = {{1{_zz_371[32]}}, _zz_371}; - assign _zz_373 = _zz_375; - assign _zz_374 = {{1{_zz_373[32]}}, _zz_373}; - assign _zz_375 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_376 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_377 = {5'd0, _zz_376}; - assign _zz_378 = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_379 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_380 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_381 = {_zz_150,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_382 = _zz_383; - assign _zz_383 = _zz_384; - assign _zz_384 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_151) : _zz_151)} + _zz_386); - assign _zz_385 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_386 = {32'd0, _zz_385}; - assign _zz_387 = _zz_153; - assign _zz_388 = {32'd0, _zz_387}; - assign _zz_389 = _zz_152; - assign _zz_390 = {31'd0, _zz_389}; - assign _zz_391 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_392 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_393 = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_394 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_395 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_396 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_397 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_398 = execute_CsrPlugin_writeData[19 : 19]; - assign _zz_399 = execute_CsrPlugin_writeData[18 : 18]; - assign _zz_400 = execute_CsrPlugin_writeData[17 : 17]; - assign _zz_401 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_402 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_403 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_404 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_405 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_406 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_407 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_408 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_409 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_410 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_411 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_412 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_413 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_414 = execute_CsrPlugin_writeData[0 : 0]; - assign _zz_415 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_416 = execute_CsrPlugin_writeData[2 : 2]; - assign _zz_417 = execute_CsrPlugin_writeData[4 : 4]; - assign _zz_418 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_419 = execute_CsrPlugin_writeData[6 : 6]; - assign _zz_420 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_421 = execute_CsrPlugin_writeData[8 : 8]; - assign _zz_422 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_423 = execute_CsrPlugin_writeData[12 : 12]; - assign _zz_424 = execute_CsrPlugin_writeData[13 : 13]; - assign _zz_425 = execute_CsrPlugin_writeData[15 : 15]; - assign _zz_426 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_427 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_428 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_429 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_430 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_431 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_432 = execute_CsrPlugin_writeData[9 : 9]; - assign _zz_433 = execute_CsrPlugin_writeData[5 : 5]; - assign _zz_434 = execute_CsrPlugin_writeData[1 : 1]; - assign _zz_435 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_436 = (iBus_cmd_payload_address >>> 5); - assign _zz_437 = 1'b1; - assign _zz_438 = 1'b1; - assign _zz_439 = {_zz_59,_zz_58}; - assign _zz_440 = 32'h0000107f; - assign _zz_441 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_442 = 32'h00002073; - assign _zz_443 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_444 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_445 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_446) == 32'h00000003),{(_zz_447 == _zz_448),{_zz_449,{_zz_450,_zz_451}}}}}}; - assign _zz_446 = 32'h0000505f; - assign _zz_447 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_448 = 32'h00000063; - assign _zz_449 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_450 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); - assign _zz_451 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_452) == 32'h00001013),{(_zz_453 == _zz_454),{_zz_455,{_zz_456,_zz_457}}}}}}; - assign _zz_452 = 32'hfc00305f; - assign _zz_453 = (decode_INSTRUCTION & 32'h01f0707f); - assign _zz_454 = 32'h0000500f; - assign _zz_455 = ((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013); - assign _zz_456 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_457 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_458) == 32'h12000073),{(_zz_459 == _zz_460),{_zz_461,_zz_462}}}}}; - assign _zz_458 = 32'hfe007fff; - assign _zz_459 = (decode_INSTRUCTION & 32'hdfffffff); - assign _zz_460 = 32'h10200073; - assign _zz_461 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_462 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); - assign _zz_463 = 32'h02004064; - assign _zz_464 = _zz_102; - assign _zz_465 = {_zz_100,_zz_101}; - assign _zz_466 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_467 = 1'b0; - assign _zz_468 = (((decode_INSTRUCTION & _zz_471) == 32'h00000050) != 1'b0); - assign _zz_469 = ((_zz_472 == _zz_473) != 1'b0); - assign _zz_470 = {({_zz_474,_zz_475} != 2'b00),{(_zz_476 != _zz_477),{_zz_478,{_zz_479,_zz_480}}}}; - assign _zz_471 = 32'h02203050; - assign _zz_472 = (decode_INSTRUCTION & 32'h02403050); - assign _zz_473 = 32'h00000050; - assign _zz_474 = ((decode_INSTRUCTION & _zz_481) == 32'h00001050); - assign _zz_475 = ((decode_INSTRUCTION & _zz_482) == 32'h00002050); - assign _zz_476 = {_zz_96,(_zz_483 == _zz_484)}; - assign _zz_477 = 2'b00; - assign _zz_478 = ((_zz_485 == _zz_486) != 1'b0); - assign _zz_479 = ({_zz_487,_zz_488} != 2'b00); - assign _zz_480 = {(_zz_489 != _zz_490),{_zz_491,{_zz_492,_zz_493}}}; - assign _zz_481 = 32'h00001050; - assign _zz_482 = 32'h00002050; - assign _zz_483 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_484 = 32'h00000004; - assign _zz_485 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_486 = 32'h00000040; - assign _zz_487 = ((decode_INSTRUCTION & _zz_494) == 32'h00005010); - assign _zz_488 = ((decode_INSTRUCTION & _zz_495) == 32'h00005020); - assign _zz_489 = {(_zz_496 == _zz_497),{_zz_498,_zz_499}}; - assign _zz_490 = 3'b000; - assign _zz_491 = ((_zz_500 == _zz_501) != 1'b0); - assign _zz_492 = (_zz_100 != 1'b0); - assign _zz_493 = {(_zz_502 != _zz_503),{_zz_504,{_zz_505,_zz_506}}}; - assign _zz_494 = 32'h00007034; - assign _zz_495 = 32'h02007064; - assign _zz_496 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_497 = 32'h40001010; - assign _zz_498 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_499 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_500 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_501 = 32'h00001000; - assign _zz_502 = {(_zz_507 == _zz_508),(_zz_509 == _zz_510)}; - assign _zz_503 = 2'b00; - assign _zz_504 = ((_zz_511 == _zz_512) != 1'b0); - assign _zz_505 = (_zz_513 != 1'b0); - assign _zz_506 = {(_zz_514 != _zz_515),{_zz_516,{_zz_517,_zz_518}}}; - assign _zz_507 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_508 = 32'h00002000; - assign _zz_509 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_510 = 32'h00001000; - assign _zz_511 = (decode_INSTRUCTION & 32'h02003050); - assign _zz_512 = 32'h02000050; - assign _zz_513 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); - assign _zz_514 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_515 = 1'b0; - assign _zz_516 = ({(_zz_519 == _zz_520),{_zz_521,{_zz_522,_zz_523}}} != 4'b0000); - assign _zz_517 = ((_zz_524 == _zz_525) != 1'b0); - assign _zz_518 = {(_zz_526 != 1'b0),{(_zz_527 != _zz_528),{_zz_529,{_zz_530,_zz_531}}}}; - assign _zz_519 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_520 = 32'h00000020; - assign _zz_521 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_522 = ((decode_INSTRUCTION & _zz_532) == 32'h08000020); - assign _zz_523 = ((decode_INSTRUCTION & _zz_533) == 32'h00000020); - assign _zz_524 = (decode_INSTRUCTION & 32'h10000008); - assign _zz_525 = 32'h00000008; - assign _zz_526 = ((decode_INSTRUCTION & 32'h10000008) == 32'h10000008); - assign _zz_527 = {(_zz_534 == _zz_535),{_zz_536,{_zz_537,_zz_538}}}; - assign _zz_528 = 6'h0; - assign _zz_529 = ({_zz_539,{_zz_540,_zz_541}} != 3'b000); - assign _zz_530 = (_zz_542 != 1'b0); - assign _zz_531 = {(_zz_543 != _zz_544),{_zz_545,{_zz_546,_zz_547}}}; - assign _zz_532 = 32'h08000070; - assign _zz_533 = 32'h10000070; - assign _zz_534 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_535 = 32'h00002040; - assign _zz_536 = ((decode_INSTRUCTION & _zz_548) == 32'h00001040); - assign _zz_537 = (_zz_549 == _zz_550); - assign _zz_538 = {_zz_551,{_zz_552,_zz_553}}; - assign _zz_539 = ((decode_INSTRUCTION & _zz_554) == 32'h08000020); - assign _zz_540 = (_zz_555 == _zz_556); - assign _zz_541 = (_zz_557 == _zz_558); - assign _zz_542 = ((decode_INSTRUCTION & _zz_559) == 32'h00000010); - assign _zz_543 = {_zz_99,{_zz_560,_zz_561}}; - assign _zz_544 = 5'h0; - assign _zz_545 = ({_zz_562,_zz_563} != 7'h0); - assign _zz_546 = (_zz_564 != _zz_565); - assign _zz_547 = {_zz_566,{_zz_567,_zz_568}}; - assign _zz_548 = 32'h00001040; - assign _zz_549 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_550 = 32'h00000040; - assign _zz_551 = ((decode_INSTRUCTION & _zz_569) == 32'h00000040); - assign _zz_552 = (_zz_570 == _zz_571); - assign _zz_553 = (_zz_572 == _zz_573); - assign _zz_554 = 32'h08000020; - assign _zz_555 = (decode_INSTRUCTION & 32'h10000020); - assign _zz_556 = 32'h00000020; - assign _zz_557 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_558 = 32'h00000020; - assign _zz_559 = 32'h00000010; - assign _zz_560 = (_zz_574 == _zz_575); - assign _zz_561 = {_zz_576,{_zz_577,_zz_578}}; - assign _zz_562 = _zz_96; - assign _zz_563 = {_zz_579,{_zz_580,_zz_581}}; - assign _zz_564 = {_zz_98,_zz_582}; - assign _zz_565 = 2'b00; - assign _zz_566 = ({_zz_583,_zz_584} != 2'b00); - assign _zz_567 = (_zz_585 != _zz_586); - assign _zz_568 = {_zz_587,{_zz_588,_zz_589}}; - assign _zz_569 = 32'h02400040; - assign _zz_570 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_571 = 32'h0; - assign _zz_572 = (decode_INSTRUCTION & 32'h18002008); - assign _zz_573 = 32'h10002008; - assign _zz_574 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_575 = 32'h00002010; - assign _zz_576 = ((decode_INSTRUCTION & _zz_590) == 32'h00000010); - assign _zz_577 = (_zz_591 == _zz_592); - assign _zz_578 = (_zz_593 == _zz_594); - assign _zz_579 = ((decode_INSTRUCTION & _zz_595) == 32'h00001010); - assign _zz_580 = (_zz_596 == _zz_597); - assign _zz_581 = {_zz_598,{_zz_599,_zz_600}}; - assign _zz_582 = ((decode_INSTRUCTION & _zz_601) == 32'h00000020); - assign _zz_583 = _zz_98; - assign _zz_584 = (_zz_602 == _zz_603); - assign _zz_585 = (_zz_604 == _zz_605); - assign _zz_586 = 1'b0; - assign _zz_587 = (_zz_606 != 1'b0); - assign _zz_588 = (_zz_607 != _zz_608); - assign _zz_589 = {_zz_609,{_zz_610,_zz_611}}; - assign _zz_590 = 32'h00001030; - assign _zz_591 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_592 = 32'h00000020; - assign _zz_593 = (decode_INSTRUCTION & 32'h02002068); - assign _zz_594 = 32'h00002020; - assign _zz_595 = 32'h00001010; - assign _zz_596 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_597 = 32'h00002010; - assign _zz_598 = ((decode_INSTRUCTION & _zz_612) == 32'h00002008); - assign _zz_599 = (_zz_613 == _zz_614); - assign _zz_600 = {_zz_99,_zz_615}; - assign _zz_601 = 32'h00000070; - assign _zz_602 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_603 = 32'h0; - assign _zz_604 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_605 = 32'h00004010; - assign _zz_606 = ((decode_INSTRUCTION & _zz_616) == 32'h00002010); - assign _zz_607 = {_zz_617,{_zz_618,_zz_619}}; - assign _zz_608 = 5'h0; - assign _zz_609 = ({_zz_620,_zz_621} != 2'b00); - assign _zz_610 = (_zz_622 != _zz_623); - assign _zz_611 = {_zz_624,{_zz_625,_zz_626}}; - assign _zz_612 = 32'h00002008; - assign _zz_613 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_614 = 32'h00000010; - assign _zz_615 = ((decode_INSTRUCTION & _zz_627) == 32'h0); - assign _zz_616 = 32'h00006014; - assign _zz_617 = ((decode_INSTRUCTION & _zz_628) == 32'h0); - assign _zz_618 = (_zz_629 == _zz_630); - assign _zz_619 = {_zz_631,{_zz_632,_zz_633}}; - assign _zz_620 = _zz_97; - assign _zz_621 = (_zz_634 == _zz_635); - assign _zz_622 = {_zz_636,{_zz_637,_zz_638}}; - assign _zz_623 = 3'b000; - assign _zz_624 = ({_zz_639,_zz_640} != 3'b000); - assign _zz_625 = (_zz_641 != _zz_642); - assign _zz_626 = (_zz_643 != _zz_644); - assign _zz_627 = 32'h00000028; - assign _zz_628 = 32'h00000044; - assign _zz_629 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_630 = 32'h0; - assign _zz_631 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_632 = ((decode_INSTRUCTION & _zz_645) == 32'h00001000); - assign _zz_633 = _zz_97; - assign _zz_634 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_635 = 32'h0; - assign _zz_636 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_637 = ((decode_INSTRUCTION & _zz_646) == 32'h00002010); - assign _zz_638 = ((decode_INSTRUCTION & _zz_647) == 32'h40000030); - assign _zz_639 = _zz_96; - assign _zz_640 = {_zz_95,(_zz_648 == _zz_649)}; - assign _zz_641 = {_zz_95,(_zz_650 == _zz_651)}; - assign _zz_642 = 2'b00; - assign _zz_643 = ((decode_INSTRUCTION & _zz_652) == 32'h00001008); - assign _zz_644 = 1'b0; - assign _zz_645 = 32'h00005004; - assign _zz_646 = 32'h00002014; - assign _zz_647 = 32'h40000034; - assign _zz_648 = (decode_INSTRUCTION & 32'h00002014); - assign _zz_649 = 32'h00000004; - assign _zz_650 = (decode_INSTRUCTION & 32'h0000004c); - assign _zz_651 = 32'h00000004; - assign _zz_652 = 32'h00005048; - assign _zz_653 = 32'h0; - always @ (posedge clk) begin - if(_zz_437) begin - _zz_227 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_438) begin - _zz_228 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_43) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz_writeBack_DBusCachedPlugin_rspRf = (! dataCache_1_io_cpu_writeBack_exclusiveOk); + assign _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1 = MmuPlugin_ports_0_entryToReplace_willIncrement; + assign _zz_MmuPlugin_ports_0_entryToReplace_valueNext = {1'd0, _zz_MmuPlugin_ports_0_entryToReplace_valueNext_1}; + assign _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1 = MmuPlugin_ports_1_entryToReplace_willIncrement; + assign _zz_MmuPlugin_ports_1_entryToReplace_valueNext = {1'd0, _zz_MmuPlugin_ports_1_entryToReplace_valueNext_1}; + assign _zz__zz_MmuPlugin_shared_refills_2 = (_zz_MmuPlugin_shared_refills_1 - 2'b01); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_memory_MulDivIterativePlugin_mul_counter_valueNext_1 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_mul_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_mul_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_accumulator = (_zz_memory_MulDivIterativePlugin_accumulator_1 + _zz_memory_MulDivIterativePlugin_accumulator_3); + assign _zz_memory_MulDivIterativePlugin_accumulator_2 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_memory_MulDivIterativePlugin_accumulator_1 = {{1{_zz_memory_MulDivIterativePlugin_accumulator_2[32]}}, _zz_memory_MulDivIterativePlugin_accumulator_2}; + assign _zz_memory_MulDivIterativePlugin_accumulator_4 = _zz_memory_MulDivIterativePlugin_accumulator_5; + assign _zz_memory_MulDivIterativePlugin_accumulator_3 = {{1{_zz_memory_MulDivIterativePlugin_accumulator_4[32]}}, _zz_memory_MulDivIterativePlugin_accumulator_4}; + assign _zz_memory_MulDivIterativePlugin_accumulator_5 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; + assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; + assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); + assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; + assign _zz_memory_MulDivIterativePlugin_rs1_4 = _zz_memory_MulDivIterativePlugin_rs1_1; + assign _zz_memory_MulDivIterativePlugin_rs1_3 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_4}; + assign _zz_memory_MulDivIterativePlugin_rs2_1 = _zz_memory_MulDivIterativePlugin_rs1; + assign _zz_memory_MulDivIterativePlugin_rs2 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_1}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h1800707f) == 32'h0000202f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'he800707f) == 32'h0800202f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00305f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'h01f0707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h0000500f; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033),{((decode_INSTRUCTION & 32'hf9f0707f) == 32'h1000202f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_18) == 32'h12000073),{(_zz_decode_LEGAL_INSTRUCTION_19 == _zz_decode_LEGAL_INSTRUCTION_20),{_zz_decode_LEGAL_INSTRUCTION_21,_zz_decode_LEGAL_INSTRUCTION_22}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_18 = 32'hfe007fff; + assign _zz_decode_LEGAL_INSTRUCTION_19 = (decode_INSTRUCTION & 32'hdfffffff); + assign _zz_decode_LEGAL_INSTRUCTION_20 = 32'h10200073; + assign _zz_decode_LEGAL_INSTRUCTION_21 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_decode_LEGAL_INSTRUCTION_22 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_1 = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]; + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_2 = (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_3 = (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_4 = (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_0_cacheHitsCalc_5 = (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]; + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_1 = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]; + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_2 = (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_3 = (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_4 = (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22]); + assign _zz_MmuPlugin_ports_1_cacheHitsCalc_5 = (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]); + assign _zz__zz_decode_IS_DIV = 32'h02004064; + assign _zz__zz_decode_IS_DIV_1 = _zz_decode_IS_DIV_9; + assign _zz__zz_decode_IS_DIV_2 = {_zz_decode_IS_DIV_7,_zz_decode_IS_DIV_8}; + assign _zz__zz_decode_IS_DIV_3 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz__zz_decode_IS_DIV_4 = 1'b0; + assign _zz__zz_decode_IS_DIV_5 = (((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_6) == 32'h00000050) != 1'b0); + assign _zz__zz_decode_IS_DIV_7 = ((_zz__zz_decode_IS_DIV_8 == _zz__zz_decode_IS_DIV_9) != 1'b0); + assign _zz__zz_decode_IS_DIV_10 = {({_zz__zz_decode_IS_DIV_11,_zz__zz_decode_IS_DIV_13} != 2'b00),{(_zz__zz_decode_IS_DIV_15 != _zz__zz_decode_IS_DIV_18),{_zz__zz_decode_IS_DIV_19,{_zz__zz_decode_IS_DIV_22,_zz__zz_decode_IS_DIV_27}}}}; + assign _zz__zz_decode_IS_DIV_6 = 32'h02203050; + assign _zz__zz_decode_IS_DIV_8 = (decode_INSTRUCTION & 32'h02403050); + assign _zz__zz_decode_IS_DIV_9 = 32'h00000050; + assign _zz__zz_decode_IS_DIV_11 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_12) == 32'h00001050); + assign _zz__zz_decode_IS_DIV_13 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_14) == 32'h00002050); + assign _zz__zz_decode_IS_DIV_15 = {_zz_decode_IS_DIV_2,(_zz__zz_decode_IS_DIV_16 == _zz__zz_decode_IS_DIV_17)}; + assign _zz__zz_decode_IS_DIV_18 = 2'b00; + assign _zz__zz_decode_IS_DIV_19 = ((_zz__zz_decode_IS_DIV_20 == _zz__zz_decode_IS_DIV_21) != 1'b0); + assign _zz__zz_decode_IS_DIV_22 = ({_zz__zz_decode_IS_DIV_23,_zz__zz_decode_IS_DIV_25} != 2'b00); + assign _zz__zz_decode_IS_DIV_27 = {(_zz__zz_decode_IS_DIV_28 != _zz__zz_decode_IS_DIV_33),{_zz__zz_decode_IS_DIV_34,{_zz__zz_decode_IS_DIV_37,_zz__zz_decode_IS_DIV_38}}}; + assign _zz__zz_decode_IS_DIV_12 = 32'h00001050; + assign _zz__zz_decode_IS_DIV_14 = 32'h00002050; + assign _zz__zz_decode_IS_DIV_16 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz__zz_decode_IS_DIV_17 = 32'h00000004; + assign _zz__zz_decode_IS_DIV_20 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_IS_DIV_21 = 32'h00000040; + assign _zz__zz_decode_IS_DIV_23 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_24) == 32'h00005010); + assign _zz__zz_decode_IS_DIV_25 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_26) == 32'h00005020); + assign _zz__zz_decode_IS_DIV_28 = {(_zz__zz_decode_IS_DIV_29 == _zz__zz_decode_IS_DIV_30),{_zz__zz_decode_IS_DIV_31,_zz__zz_decode_IS_DIV_32}}; + assign _zz__zz_decode_IS_DIV_33 = 3'b000; + assign _zz__zz_decode_IS_DIV_34 = ((_zz__zz_decode_IS_DIV_35 == _zz__zz_decode_IS_DIV_36) != 1'b0); + assign _zz__zz_decode_IS_DIV_37 = (_zz_decode_IS_DIV_7 != 1'b0); + assign _zz__zz_decode_IS_DIV_38 = {(_zz__zz_decode_IS_DIV_39 != _zz__zz_decode_IS_DIV_44),{_zz__zz_decode_IS_DIV_45,{_zz__zz_decode_IS_DIV_46,_zz__zz_decode_IS_DIV_47}}}; + assign _zz__zz_decode_IS_DIV_24 = 32'h00007034; + assign _zz__zz_decode_IS_DIV_26 = 32'h02007064; + assign _zz__zz_decode_IS_DIV_29 = (decode_INSTRUCTION & 32'h40003054); + assign _zz__zz_decode_IS_DIV_30 = 32'h40001010; + assign _zz__zz_decode_IS_DIV_31 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); + assign _zz__zz_decode_IS_DIV_32 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); + assign _zz__zz_decode_IS_DIV_35 = (decode_INSTRUCTION & 32'h00001000); + assign _zz__zz_decode_IS_DIV_36 = 32'h00001000; + assign _zz__zz_decode_IS_DIV_39 = {(_zz__zz_decode_IS_DIV_40 == _zz__zz_decode_IS_DIV_41),(_zz__zz_decode_IS_DIV_42 == _zz__zz_decode_IS_DIV_43)}; + assign _zz__zz_decode_IS_DIV_44 = 2'b00; + assign _zz__zz_decode_IS_DIV_45 = (_zz_decode_IS_DIV_6 != 1'b0); + assign _zz__zz_decode_IS_DIV_46 = (_zz_decode_IS_DIV_6 != 1'b0); + assign _zz__zz_decode_IS_DIV_47 = {(_zz__zz_decode_IS_DIV_48 != _zz__zz_decode_IS_DIV_49),{_zz__zz_decode_IS_DIV_50,{_zz__zz_decode_IS_DIV_52,_zz__zz_decode_IS_DIV_61}}}; + assign _zz__zz_decode_IS_DIV_40 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_DIV_41 = 32'h00002000; + assign _zz__zz_decode_IS_DIV_42 = (decode_INSTRUCTION & 32'h00005000); + assign _zz__zz_decode_IS_DIV_43 = 32'h00001000; + assign _zz__zz_decode_IS_DIV_48 = ((decode_INSTRUCTION & 32'h00004048) == 32'h00004008); + assign _zz__zz_decode_IS_DIV_49 = 1'b0; + assign _zz__zz_decode_IS_DIV_50 = (((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_51) == 32'h00000024) != 1'b0); + assign _zz__zz_decode_IS_DIV_52 = ({_zz__zz_decode_IS_DIV_53,{_zz__zz_decode_IS_DIV_54,_zz__zz_decode_IS_DIV_56}} != 4'b0000); + assign _zz__zz_decode_IS_DIV_61 = {(_zz__zz_decode_IS_DIV_62 != 1'b0),{(_zz__zz_decode_IS_DIV_63 != _zz__zz_decode_IS_DIV_65),{_zz__zz_decode_IS_DIV_66,{_zz__zz_decode_IS_DIV_83,_zz__zz_decode_IS_DIV_92}}}}; + assign _zz__zz_decode_IS_DIV_51 = 32'h00000064; + assign _zz__zz_decode_IS_DIV_53 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_54 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_55) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_56 = {(_zz__zz_decode_IS_DIV_57 == _zz__zz_decode_IS_DIV_58),(_zz__zz_decode_IS_DIV_59 == _zz__zz_decode_IS_DIV_60)}; + assign _zz__zz_decode_IS_DIV_62 = ((decode_INSTRUCTION & 32'h10000008) == 32'h00000008); + assign _zz__zz_decode_IS_DIV_63 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_64) == 32'h10000008); + assign _zz__zz_decode_IS_DIV_65 = 1'b0; + assign _zz__zz_decode_IS_DIV_66 = ({_zz__zz_decode_IS_DIV_67,{_zz__zz_decode_IS_DIV_69,_zz__zz_decode_IS_DIV_72}} != 6'h0); + assign _zz__zz_decode_IS_DIV_83 = ({_zz__zz_decode_IS_DIV_84,_zz__zz_decode_IS_DIV_87} != 3'b000); + assign _zz__zz_decode_IS_DIV_92 = {(_zz__zz_decode_IS_DIV_93 != _zz__zz_decode_IS_DIV_96),{_zz__zz_decode_IS_DIV_97,{_zz__zz_decode_IS_DIV_110,_zz__zz_decode_IS_DIV_129}}}; + assign _zz__zz_decode_IS_DIV_55 = 32'h00000064; + assign _zz__zz_decode_IS_DIV_57 = (decode_INSTRUCTION & 32'h08000070); + assign _zz__zz_decode_IS_DIV_58 = 32'h08000020; + assign _zz__zz_decode_IS_DIV_59 = (decode_INSTRUCTION & 32'h10000070); + assign _zz__zz_decode_IS_DIV_60 = 32'h00000020; + assign _zz__zz_decode_IS_DIV_64 = 32'h10000008; + assign _zz__zz_decode_IS_DIV_67 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_68) == 32'h00002040); + assign _zz__zz_decode_IS_DIV_69 = (_zz__zz_decode_IS_DIV_70 == _zz__zz_decode_IS_DIV_71); + assign _zz__zz_decode_IS_DIV_72 = {_zz__zz_decode_IS_DIV_73,{_zz__zz_decode_IS_DIV_75,_zz__zz_decode_IS_DIV_78}}; + assign _zz__zz_decode_IS_DIV_84 = (_zz__zz_decode_IS_DIV_85 == _zz__zz_decode_IS_DIV_86); + assign _zz__zz_decode_IS_DIV_87 = {_zz__zz_decode_IS_DIV_88,_zz__zz_decode_IS_DIV_90}; + assign _zz__zz_decode_IS_DIV_93 = (_zz__zz_decode_IS_DIV_94 == _zz__zz_decode_IS_DIV_95); + assign _zz__zz_decode_IS_DIV_96 = 1'b0; + assign _zz__zz_decode_IS_DIV_97 = ({_zz__zz_decode_IS_DIV_98,_zz__zz_decode_IS_DIV_99} != 5'h0); + assign _zz__zz_decode_IS_DIV_110 = (_zz__zz_decode_IS_DIV_111 != _zz__zz_decode_IS_DIV_128); + assign _zz__zz_decode_IS_DIV_129 = {_zz__zz_decode_IS_DIV_130,{_zz__zz_decode_IS_DIV_135,_zz__zz_decode_IS_DIV_140}}; + assign _zz__zz_decode_IS_DIV_68 = 32'h00002040; + assign _zz__zz_decode_IS_DIV_70 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_IS_DIV_71 = 32'h00001040; + assign _zz__zz_decode_IS_DIV_73 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_74) == 32'h00000040); + assign _zz__zz_decode_IS_DIV_75 = (_zz__zz_decode_IS_DIV_76 == _zz__zz_decode_IS_DIV_77); + assign _zz__zz_decode_IS_DIV_78 = {_zz__zz_decode_IS_DIV_79,_zz__zz_decode_IS_DIV_81}; + assign _zz__zz_decode_IS_DIV_85 = (decode_INSTRUCTION & 32'h08000020); + assign _zz__zz_decode_IS_DIV_86 = 32'h08000020; + assign _zz__zz_decode_IS_DIV_88 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_89) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_90 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_91) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_94 = (decode_INSTRUCTION & 32'h00000010); + assign _zz__zz_decode_IS_DIV_95 = 32'h00000010; + assign _zz__zz_decode_IS_DIV_98 = _zz_decode_IS_DIV_5; + assign _zz__zz_decode_IS_DIV_99 = {_zz__zz_decode_IS_DIV_100,{_zz__zz_decode_IS_DIV_102,_zz__zz_decode_IS_DIV_105}}; + assign _zz__zz_decode_IS_DIV_111 = {_zz_decode_IS_DIV_2,{_zz__zz_decode_IS_DIV_112,_zz__zz_decode_IS_DIV_115}}; + assign _zz__zz_decode_IS_DIV_128 = 7'h0; + assign _zz__zz_decode_IS_DIV_130 = ({_zz__zz_decode_IS_DIV_131,_zz__zz_decode_IS_DIV_132} != 2'b00); + assign _zz__zz_decode_IS_DIV_135 = (_zz__zz_decode_IS_DIV_136 != _zz__zz_decode_IS_DIV_139); + assign _zz__zz_decode_IS_DIV_140 = {_zz__zz_decode_IS_DIV_141,{_zz__zz_decode_IS_DIV_144,_zz__zz_decode_IS_DIV_149}}; + assign _zz__zz_decode_IS_DIV_74 = 32'h00000050; + assign _zz__zz_decode_IS_DIV_76 = (decode_INSTRUCTION & 32'h02400040); + assign _zz__zz_decode_IS_DIV_77 = 32'h00000040; + assign _zz__zz_decode_IS_DIV_79 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_80) == 32'h0); + assign _zz__zz_decode_IS_DIV_81 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_82) == 32'h10002008); + assign _zz__zz_decode_IS_DIV_89 = 32'h10000020; + assign _zz__zz_decode_IS_DIV_91 = 32'h00000028; + assign _zz__zz_decode_IS_DIV_100 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_101) == 32'h00002010); + assign _zz__zz_decode_IS_DIV_102 = (_zz__zz_decode_IS_DIV_103 == _zz__zz_decode_IS_DIV_104); + assign _zz__zz_decode_IS_DIV_105 = {_zz__zz_decode_IS_DIV_106,_zz__zz_decode_IS_DIV_108}; + assign _zz__zz_decode_IS_DIV_112 = (_zz__zz_decode_IS_DIV_113 == _zz__zz_decode_IS_DIV_114); + assign _zz__zz_decode_IS_DIV_115 = {_zz__zz_decode_IS_DIV_116,{_zz__zz_decode_IS_DIV_118,_zz__zz_decode_IS_DIV_121}}; + assign _zz__zz_decode_IS_DIV_131 = _zz_decode_IS_DIV_4; + assign _zz__zz_decode_IS_DIV_132 = (_zz__zz_decode_IS_DIV_133 == _zz__zz_decode_IS_DIV_134); + assign _zz__zz_decode_IS_DIV_136 = {_zz_decode_IS_DIV_4,_zz__zz_decode_IS_DIV_137}; + assign _zz__zz_decode_IS_DIV_139 = 2'b00; + assign _zz__zz_decode_IS_DIV_141 = (_zz__zz_decode_IS_DIV_142 != 1'b0); + assign _zz__zz_decode_IS_DIV_144 = (_zz__zz_decode_IS_DIV_145 != _zz__zz_decode_IS_DIV_148); + assign _zz__zz_decode_IS_DIV_149 = {_zz__zz_decode_IS_DIV_150,{_zz__zz_decode_IS_DIV_162,_zz__zz_decode_IS_DIV_167}}; + assign _zz__zz_decode_IS_DIV_80 = 32'h00000038; + assign _zz__zz_decode_IS_DIV_82 = 32'h18002008; + assign _zz__zz_decode_IS_DIV_101 = 32'h00002030; + assign _zz__zz_decode_IS_DIV_103 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_IS_DIV_104 = 32'h00000010; + assign _zz__zz_decode_IS_DIV_106 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_107) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_108 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_109) == 32'h00002020); + assign _zz__zz_decode_IS_DIV_113 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_IS_DIV_114 = 32'h00001010; + assign _zz__zz_decode_IS_DIV_116 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_117) == 32'h00002010); + assign _zz__zz_decode_IS_DIV_118 = (_zz__zz_decode_IS_DIV_119 == _zz__zz_decode_IS_DIV_120); + assign _zz__zz_decode_IS_DIV_121 = {_zz__zz_decode_IS_DIV_122,{_zz__zz_decode_IS_DIV_124,_zz__zz_decode_IS_DIV_125}}; + assign _zz__zz_decode_IS_DIV_133 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_IS_DIV_134 = 32'h00000020; + assign _zz__zz_decode_IS_DIV_137 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_138) == 32'h0); + assign _zz__zz_decode_IS_DIV_142 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_143) == 32'h00004010); + assign _zz__zz_decode_IS_DIV_145 = (_zz__zz_decode_IS_DIV_146 == _zz__zz_decode_IS_DIV_147); + assign _zz__zz_decode_IS_DIV_148 = 1'b0; + assign _zz__zz_decode_IS_DIV_150 = ({_zz__zz_decode_IS_DIV_151,_zz__zz_decode_IS_DIV_154} != 5'h0); + assign _zz__zz_decode_IS_DIV_162 = (_zz__zz_decode_IS_DIV_163 != _zz__zz_decode_IS_DIV_166); + assign _zz__zz_decode_IS_DIV_167 = {_zz__zz_decode_IS_DIV_168,{_zz__zz_decode_IS_DIV_175,_zz__zz_decode_IS_DIV_180}}; + assign _zz__zz_decode_IS_DIV_107 = 32'h02003020; + assign _zz__zz_decode_IS_DIV_109 = 32'h02002068; + assign _zz__zz_decode_IS_DIV_117 = 32'h00002010; + assign _zz__zz_decode_IS_DIV_119 = (decode_INSTRUCTION & 32'h00002008); + assign _zz__zz_decode_IS_DIV_120 = 32'h00002008; + assign _zz__zz_decode_IS_DIV_122 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_123) == 32'h00000010); + assign _zz__zz_decode_IS_DIV_124 = _zz_decode_IS_DIV_5; + assign _zz__zz_decode_IS_DIV_125 = (_zz__zz_decode_IS_DIV_126 == _zz__zz_decode_IS_DIV_127); + assign _zz__zz_decode_IS_DIV_138 = 32'h00000020; + assign _zz__zz_decode_IS_DIV_143 = 32'h00004014; + assign _zz__zz_decode_IS_DIV_146 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_IS_DIV_147 = 32'h00002010; + assign _zz__zz_decode_IS_DIV_151 = (_zz__zz_decode_IS_DIV_152 == _zz__zz_decode_IS_DIV_153); + assign _zz__zz_decode_IS_DIV_154 = {_zz__zz_decode_IS_DIV_155,{_zz__zz_decode_IS_DIV_157,_zz__zz_decode_IS_DIV_160}}; + assign _zz__zz_decode_IS_DIV_163 = {_zz_decode_IS_DIV_3,_zz__zz_decode_IS_DIV_164}; + assign _zz__zz_decode_IS_DIV_166 = 2'b00; + assign _zz__zz_decode_IS_DIV_168 = ({_zz__zz_decode_IS_DIV_169,_zz__zz_decode_IS_DIV_172} != 3'b000); + assign _zz__zz_decode_IS_DIV_175 = (_zz__zz_decode_IS_DIV_176 != _zz__zz_decode_IS_DIV_179); + assign _zz__zz_decode_IS_DIV_180 = {_zz__zz_decode_IS_DIV_181,_zz__zz_decode_IS_DIV_184}; + assign _zz__zz_decode_IS_DIV_123 = 32'h00000050; + assign _zz__zz_decode_IS_DIV_126 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_DIV_127 = 32'h0; + assign _zz__zz_decode_IS_DIV_152 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_DIV_153 = 32'h0; + assign _zz__zz_decode_IS_DIV_155 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_156) == 32'h0); + assign _zz__zz_decode_IS_DIV_157 = (_zz__zz_decode_IS_DIV_158 == _zz__zz_decode_IS_DIV_159); + assign _zz__zz_decode_IS_DIV_160 = {_zz__zz_decode_IS_DIV_161,_zz_decode_IS_DIV_3}; + assign _zz__zz_decode_IS_DIV_164 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_165) == 32'h0); + assign _zz__zz_decode_IS_DIV_169 = (_zz__zz_decode_IS_DIV_170 == _zz__zz_decode_IS_DIV_171); + assign _zz__zz_decode_IS_DIV_172 = {_zz__zz_decode_IS_DIV_173,_zz__zz_decode_IS_DIV_174}; + assign _zz__zz_decode_IS_DIV_176 = {_zz_decode_IS_DIV_2,{_zz__zz_decode_IS_DIV_177,_zz__zz_decode_IS_DIV_178}}; + assign _zz__zz_decode_IS_DIV_179 = 3'b000; + assign _zz__zz_decode_IS_DIV_181 = ({_zz__zz_decode_IS_DIV_182,_zz__zz_decode_IS_DIV_183} != 2'b00); + assign _zz__zz_decode_IS_DIV_184 = (_zz__zz_decode_IS_DIV_185 != 1'b0); + assign _zz__zz_decode_IS_DIV_156 = 32'h00000018; + assign _zz__zz_decode_IS_DIV_158 = (decode_INSTRUCTION & 32'h00006004); + assign _zz__zz_decode_IS_DIV_159 = 32'h00002000; + assign _zz__zz_decode_IS_DIV_161 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_IS_DIV_165 = 32'h00000058; + assign _zz__zz_decode_IS_DIV_170 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_DIV_171 = 32'h00000040; + assign _zz__zz_decode_IS_DIV_173 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_IS_DIV_174 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz__zz_decode_IS_DIV_177 = _zz_decode_IS_DIV_1; + assign _zz__zz_decode_IS_DIV_178 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00000004); + assign _zz__zz_decode_IS_DIV_182 = _zz_decode_IS_DIV_1; + assign _zz__zz_decode_IS_DIV_183 = ((decode_INSTRUCTION & 32'h0000004c) == 32'h00000004); + assign _zz__zz_decode_IS_DIV_185 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_192 ), //i - .io_cpu_prefetch_isValid (_zz_193 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_194 ), //i - .io_cpu_fetch_isStuck (_zz_195 ), //i - .io_cpu_fetch_isRemoved (_zz_196 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i - .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i - .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i - .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i - .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i - .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i - .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i - .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_197 ), //i - .io_cpu_decode_isStuck (_zz_198 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_3_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_199 ), //i - .io_cpu_fill_valid (_zz_200 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_mmuRsp_ways_0_sel (IBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_fetch_mmuRsp_ways_0_physical (IBusCachedPlugin_mmuBus_rsp_ways_0_physical ), //i + .io_cpu_fetch_mmuRsp_ways_1_sel (IBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_fetch_mmuRsp_ways_1_physical (IBusCachedPlugin_mmuBus_rsp_ways_1_physical ), //i + .io_cpu_fetch_mmuRsp_ways_2_sel (IBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_fetch_mmuRsp_ways_2_physical (IBusCachedPlugin_mmuBus_rsp_ways_2_physical ), //i + .io_cpu_fetch_mmuRsp_ways_3_sel (IBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_fetch_mmuRsp_ways_3_physical (IBusCachedPlugin_mmuBus_rsp_ways_3_physical ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_3_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_201 ), //i - .io_cpu_execute_address (_zz_202[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (_zz_203 ), //i - .io_cpu_execute_args_data (_zz_204[31:0] ), //i - .io_cpu_execute_args_size (_zz_205[1:0] ), //i - .io_cpu_execute_args_isLrsc (_zz_206 ), //i - .io_cpu_execute_args_isAmo (_zz_207 ), //i - .io_cpu_execute_args_amoCtrl_swap (_zz_208 ), //i - .io_cpu_execute_args_amoCtrl_alu (_zz_209[2:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_210 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_211[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_212 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i - .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical[31:0] ), //i - .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i - .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical[31:0] ), //i - .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i - .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical[31:0] ), //i - .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i - .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical[31:0] ), //i - .io_cpu_writeBack_isValid (_zz_213 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_214 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_215[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_216 ), //i - .io_cpu_writeBack_fence_SR (_zz_217 ), //i - .io_cpu_writeBack_fence_SO (_zz_218 ), //i - .io_cpu_writeBack_fence_SI (_zz_219 ), //i - .io_cpu_writeBack_fence_PW (_zz_220 ), //i - .io_cpu_writeBack_fence_PR (_zz_221 ), //i - .io_cpu_writeBack_fence_PO (_zz_222 ), //i - .io_cpu_writeBack_fence_PI (_zz_223 ), //i - .io_cpu_writeBack_fence_FM (_zz_224[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_225 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_226 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (dataCache_1_io_cpu_execute_args_wr ), //i + .io_cpu_execute_args_size (dataCache_1_io_cpu_execute_args_size ), //i + .io_cpu_execute_args_isLrsc (dataCache_1_io_cpu_execute_args_isLrsc ), //i + .io_cpu_execute_args_isAmo (execute_MEMORY_AMO ), //i + .io_cpu_execute_args_amoCtrl_swap (dataCache_1_io_cpu_execute_args_amoCtrl_swap ), //i + .io_cpu_execute_args_amoCtrl_alu (dataCache_1_io_cpu_execute_args_amoCtrl_alu ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_memory_mmuRsp_ways_0_sel (DBusCachedPlugin_mmuBus_rsp_ways_0_sel ), //i + .io_cpu_memory_mmuRsp_ways_0_physical (DBusCachedPlugin_mmuBus_rsp_ways_0_physical ), //i + .io_cpu_memory_mmuRsp_ways_1_sel (DBusCachedPlugin_mmuBus_rsp_ways_1_sel ), //i + .io_cpu_memory_mmuRsp_ways_1_physical (DBusCachedPlugin_mmuBus_rsp_ways_1_physical ), //i + .io_cpu_memory_mmuRsp_ways_2_sel (DBusCachedPlugin_mmuBus_rsp_ways_2_sel ), //i + .io_cpu_memory_mmuRsp_ways_2_physical (DBusCachedPlugin_mmuBus_rsp_ways_2_physical ), //i + .io_cpu_memory_mmuRsp_ways_3_sel (DBusCachedPlugin_mmuBus_rsp_ways_3_sel ), //i + .io_cpu_memory_mmuRsp_ways_3_physical (DBusCachedPlugin_mmuBus_rsp_ways_3_physical ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_439) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) + 2'b00 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_redoInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) 2'b00 : begin - _zz_229 = DBusCachedPlugin_redoBranch_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; end 2'b01 : begin - _zz_229 = CsrPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; end 2'b10 : begin - _zz_229 = BranchPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; end default : begin - _zz_229 = CsrPlugin_redoInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end always @(*) begin - case(_zz_83) + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_MmuPlugin_ports_0_cacheLine_valid_3) 2'b00 : begin - _zz_230 = MmuPlugin_ports_0_cache_0_valid; - _zz_231 = MmuPlugin_ports_0_cache_0_exception; - _zz_232 = MmuPlugin_ports_0_cache_0_superPage; - _zz_233 = MmuPlugin_ports_0_cache_0_virtualAddress_0; - _zz_234 = MmuPlugin_ports_0_cache_0_virtualAddress_1; - _zz_235 = MmuPlugin_ports_0_cache_0_physicalAddress_0; - _zz_236 = MmuPlugin_ports_0_cache_0_physicalAddress_1; - _zz_237 = MmuPlugin_ports_0_cache_0_allowRead; - _zz_238 = MmuPlugin_ports_0_cache_0_allowWrite; - _zz_239 = MmuPlugin_ports_0_cache_0_allowExecute; - _zz_240 = MmuPlugin_ports_0_cache_0_allowUser; + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_0_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_0_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_0_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_0_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_0_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_0_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_0_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_0_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_0_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_0_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_0_allowUser; end 2'b01 : begin - _zz_230 = MmuPlugin_ports_0_cache_1_valid; - _zz_231 = MmuPlugin_ports_0_cache_1_exception; - _zz_232 = MmuPlugin_ports_0_cache_1_superPage; - _zz_233 = MmuPlugin_ports_0_cache_1_virtualAddress_0; - _zz_234 = MmuPlugin_ports_0_cache_1_virtualAddress_1; - _zz_235 = MmuPlugin_ports_0_cache_1_physicalAddress_0; - _zz_236 = MmuPlugin_ports_0_cache_1_physicalAddress_1; - _zz_237 = MmuPlugin_ports_0_cache_1_allowRead; - _zz_238 = MmuPlugin_ports_0_cache_1_allowWrite; - _zz_239 = MmuPlugin_ports_0_cache_1_allowExecute; - _zz_240 = MmuPlugin_ports_0_cache_1_allowUser; + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_1_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_1_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_1_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_1_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_1_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_1_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_1_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_1_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_1_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_1_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_1_allowUser; end 2'b10 : begin - _zz_230 = MmuPlugin_ports_0_cache_2_valid; - _zz_231 = MmuPlugin_ports_0_cache_2_exception; - _zz_232 = MmuPlugin_ports_0_cache_2_superPage; - _zz_233 = MmuPlugin_ports_0_cache_2_virtualAddress_0; - _zz_234 = MmuPlugin_ports_0_cache_2_virtualAddress_1; - _zz_235 = MmuPlugin_ports_0_cache_2_physicalAddress_0; - _zz_236 = MmuPlugin_ports_0_cache_2_physicalAddress_1; - _zz_237 = MmuPlugin_ports_0_cache_2_allowRead; - _zz_238 = MmuPlugin_ports_0_cache_2_allowWrite; - _zz_239 = MmuPlugin_ports_0_cache_2_allowExecute; - _zz_240 = MmuPlugin_ports_0_cache_2_allowUser; + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_2_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_2_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_2_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_2_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_2_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_2_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_2_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_2_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_2_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_2_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_2_allowUser; end default : begin - _zz_230 = MmuPlugin_ports_0_cache_3_valid; - _zz_231 = MmuPlugin_ports_0_cache_3_exception; - _zz_232 = MmuPlugin_ports_0_cache_3_superPage; - _zz_233 = MmuPlugin_ports_0_cache_3_virtualAddress_0; - _zz_234 = MmuPlugin_ports_0_cache_3_virtualAddress_1; - _zz_235 = MmuPlugin_ports_0_cache_3_physicalAddress_0; - _zz_236 = MmuPlugin_ports_0_cache_3_physicalAddress_1; - _zz_237 = MmuPlugin_ports_0_cache_3_allowRead; - _zz_238 = MmuPlugin_ports_0_cache_3_allowWrite; - _zz_239 = MmuPlugin_ports_0_cache_3_allowExecute; - _zz_240 = MmuPlugin_ports_0_cache_3_allowUser; + _zz_MmuPlugin_ports_0_cacheLine_valid_4 = MmuPlugin_ports_0_cache_3_valid; + _zz_MmuPlugin_ports_0_cacheLine_exception = MmuPlugin_ports_0_cache_3_exception; + _zz_MmuPlugin_ports_0_cacheLine_superPage = MmuPlugin_ports_0_cache_3_superPage; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0 = MmuPlugin_ports_0_cache_3_virtualAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1 = MmuPlugin_ports_0_cache_3_virtualAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0 = MmuPlugin_ports_0_cache_3_physicalAddress_0; + _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1 = MmuPlugin_ports_0_cache_3_physicalAddress_1; + _zz_MmuPlugin_ports_0_cacheLine_allowRead = MmuPlugin_ports_0_cache_3_allowRead; + _zz_MmuPlugin_ports_0_cacheLine_allowWrite = MmuPlugin_ports_0_cache_3_allowWrite; + _zz_MmuPlugin_ports_0_cacheLine_allowExecute = MmuPlugin_ports_0_cache_3_allowExecute; + _zz_MmuPlugin_ports_0_cacheLine_allowUser = MmuPlugin_ports_0_cache_3_allowUser; end endcase end always @(*) begin - case(_zz_87) + case(_zz_MmuPlugin_ports_1_cacheLine_valid_3) 2'b00 : begin - _zz_241 = MmuPlugin_ports_1_cache_0_valid; - _zz_242 = MmuPlugin_ports_1_cache_0_exception; - _zz_243 = MmuPlugin_ports_1_cache_0_superPage; - _zz_244 = MmuPlugin_ports_1_cache_0_virtualAddress_0; - _zz_245 = MmuPlugin_ports_1_cache_0_virtualAddress_1; - _zz_246 = MmuPlugin_ports_1_cache_0_physicalAddress_0; - _zz_247 = MmuPlugin_ports_1_cache_0_physicalAddress_1; - _zz_248 = MmuPlugin_ports_1_cache_0_allowRead; - _zz_249 = MmuPlugin_ports_1_cache_0_allowWrite; - _zz_250 = MmuPlugin_ports_1_cache_0_allowExecute; - _zz_251 = MmuPlugin_ports_1_cache_0_allowUser; + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_0_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_0_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_0_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_0_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_0_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_0_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_0_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_0_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_0_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_0_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_0_allowUser; end 2'b01 : begin - _zz_241 = MmuPlugin_ports_1_cache_1_valid; - _zz_242 = MmuPlugin_ports_1_cache_1_exception; - _zz_243 = MmuPlugin_ports_1_cache_1_superPage; - _zz_244 = MmuPlugin_ports_1_cache_1_virtualAddress_0; - _zz_245 = MmuPlugin_ports_1_cache_1_virtualAddress_1; - _zz_246 = MmuPlugin_ports_1_cache_1_physicalAddress_0; - _zz_247 = MmuPlugin_ports_1_cache_1_physicalAddress_1; - _zz_248 = MmuPlugin_ports_1_cache_1_allowRead; - _zz_249 = MmuPlugin_ports_1_cache_1_allowWrite; - _zz_250 = MmuPlugin_ports_1_cache_1_allowExecute; - _zz_251 = MmuPlugin_ports_1_cache_1_allowUser; + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_1_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_1_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_1_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_1_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_1_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_1_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_1_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_1_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_1_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_1_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_1_allowUser; end 2'b10 : begin - _zz_241 = MmuPlugin_ports_1_cache_2_valid; - _zz_242 = MmuPlugin_ports_1_cache_2_exception; - _zz_243 = MmuPlugin_ports_1_cache_2_superPage; - _zz_244 = MmuPlugin_ports_1_cache_2_virtualAddress_0; - _zz_245 = MmuPlugin_ports_1_cache_2_virtualAddress_1; - _zz_246 = MmuPlugin_ports_1_cache_2_physicalAddress_0; - _zz_247 = MmuPlugin_ports_1_cache_2_physicalAddress_1; - _zz_248 = MmuPlugin_ports_1_cache_2_allowRead; - _zz_249 = MmuPlugin_ports_1_cache_2_allowWrite; - _zz_250 = MmuPlugin_ports_1_cache_2_allowExecute; - _zz_251 = MmuPlugin_ports_1_cache_2_allowUser; + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_2_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_2_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_2_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_2_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_2_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_2_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_2_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_2_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_2_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_2_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_2_allowUser; end default : begin - _zz_241 = MmuPlugin_ports_1_cache_3_valid; - _zz_242 = MmuPlugin_ports_1_cache_3_exception; - _zz_243 = MmuPlugin_ports_1_cache_3_superPage; - _zz_244 = MmuPlugin_ports_1_cache_3_virtualAddress_0; - _zz_245 = MmuPlugin_ports_1_cache_3_virtualAddress_1; - _zz_246 = MmuPlugin_ports_1_cache_3_physicalAddress_0; - _zz_247 = MmuPlugin_ports_1_cache_3_physicalAddress_1; - _zz_248 = MmuPlugin_ports_1_cache_3_allowRead; - _zz_249 = MmuPlugin_ports_1_cache_3_allowWrite; - _zz_250 = MmuPlugin_ports_1_cache_3_allowExecute; - _zz_251 = MmuPlugin_ports_1_cache_3_allowUser; + _zz_MmuPlugin_ports_1_cacheLine_valid_4 = MmuPlugin_ports_1_cache_3_valid; + _zz_MmuPlugin_ports_1_cacheLine_exception = MmuPlugin_ports_1_cache_3_exception; + _zz_MmuPlugin_ports_1_cacheLine_superPage = MmuPlugin_ports_1_cache_3_superPage; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0 = MmuPlugin_ports_1_cache_3_virtualAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1 = MmuPlugin_ports_1_cache_3_virtualAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0 = MmuPlugin_ports_1_cache_3_physicalAddress_0; + _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1 = MmuPlugin_ports_1_cache_3_physicalAddress_1; + _zz_MmuPlugin_ports_1_cacheLine_allowRead = MmuPlugin_ports_1_cache_3_allowRead; + _zz_MmuPlugin_ports_1_cacheLine_allowWrite = MmuPlugin_ports_1_cache_3_allowWrite; + _zz_MmuPlugin_ports_1_cacheLine_allowExecute = MmuPlugin_ports_1_cache_3_allowExecute; + _zz_MmuPlugin_ports_1_cacheLine_allowUser = MmuPlugin_ports_1_cache_3_allowUser; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_1_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_2_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_3_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_10) - `BranchCtrlEnum_defaultEncoding_INC : _zz_10_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_10_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_10_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_10_string = "JALR"; - default : _zz_10_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_17) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_17_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_17_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_17_string = "AND_1"; - default : _zz_17_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_20) - `Src2CtrlEnum_defaultEncoding_RS : _zz_20_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_20_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_20_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_20_string = "PC "; - default : _zz_20_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_23) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_23_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_23_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_23_string = "BITWISE "; - default : _zz_23_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_26) - `Src1CtrlEnum_defaultEncoding_RS : _zz_26_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_26_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_26_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_26_string = "URS1 "; - default : _zz_26_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_28_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_29) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_29_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_29_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_29_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_29_string = "ECALL"; - default : _zz_29_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_30) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_30_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_30_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_30_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_30_string = "ECALL"; - default : _zz_30_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_31) - `BranchCtrlEnum_defaultEncoding_INC : _zz_31_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_31_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_31_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_31_string = "JALR"; - default : _zz_31_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_34) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_34_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_34_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_34_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_34_string = "SRA_1 "; - default : _zz_34_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_35) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_35_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_35_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_35_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_35_string = "SRA_1 "; - default : _zz_35_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_37) - `Src2CtrlEnum_defaultEncoding_RS : _zz_37_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_37_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_37_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_37_string = "PC "; - default : _zz_37_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_38) - `Src1CtrlEnum_defaultEncoding_RS : _zz_38_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_38_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_38_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_38_string = "URS1 "; - default : _zz_38_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_39) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_39_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_39_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_39_string = "BITWISE "; - default : _zz_39_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_40) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_40_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_40_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_40_string = "AND_1"; - default : _zz_40_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_44_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_44_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_44_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_44_string = "ECALL"; - default : _zz_44_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_45) - `BranchCtrlEnum_defaultEncoding_INC : _zz_45_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_45_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_45_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_45_string = "JALR"; - default : _zz_45_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_46) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_46_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_46_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_46_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_46_string = "SRA_1 "; - default : _zz_46_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_47) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_47_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_47_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_47_string = "AND_1"; - default : _zz_47_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_48) - `Src2CtrlEnum_defaultEncoding_RS : _zz_48_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_48_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_48_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_48_string = "PC "; - default : _zz_48_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_49) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_49_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_49_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_49_string = "BITWISE "; - default : _zz_49_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_50) - `Src1CtrlEnum_defaultEncoding_RS : _zz_50_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_50_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_50_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_50_string = "URS1 "; - default : _zz_50_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; - `MmuPlugin_shared_State_defaultEncoding_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; + `MmuPlugin_shared_State_binary_sequential_IDLE : MmuPlugin_shared_state_1_string = "IDLE "; + `MmuPlugin_shared_State_binary_sequential_L1_CMD : MmuPlugin_shared_state_1_string = "L1_CMD"; + `MmuPlugin_shared_State_binary_sequential_L1_RSP : MmuPlugin_shared_state_1_string = "L1_RSP"; + `MmuPlugin_shared_State_binary_sequential_L0_CMD : MmuPlugin_shared_state_1_string = "L0_CMD"; + `MmuPlugin_shared_State_binary_sequential_L0_RSP : MmuPlugin_shared_state_1_string = "L0_RSP"; default : MmuPlugin_shared_state_1_string = "??????"; endcase end always @(*) begin - case(_zz_103) - `Src1CtrlEnum_defaultEncoding_RS : _zz_103_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_103_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_103_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_103_string = "URS1 "; - default : _zz_103_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_104) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_104_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_104_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_104_string = "BITWISE "; - default : _zz_104_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_105) - `Src2CtrlEnum_defaultEncoding_RS : _zz_105_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_105_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_105_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_105_string = "PC "; - default : _zz_105_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_106) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_106_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_106_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_106_string = "AND_1"; - default : _zz_106_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_107) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_107_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_107_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_107_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_107_string = "SRA_1 "; - default : _zz_107_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_108) - `BranchCtrlEnum_defaultEncoding_INC : _zz_108_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_108_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_108_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_108_string = "JALR"; - default : _zz_108_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_109) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_109_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_109_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_109_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_109_string = "ECALL"; - default : _zz_109_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end `endif assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_133; - assign execute_SHIFT_RIGHT = _zz_311; - assign execute_REGFILE_WRITE_DATA = _zz_111; - assign execute_IS_DBUS_SHARING = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_202[1 : 0]; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign execute_IS_DBUS_SHARING = MmuPlugin_dBusAccess_cmd_fire; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_DIV = _zz_313[0]; - assign decode_IS_RS2_SIGNED = _zz_314[0]; - assign decode_IS_RS1_SIGNED = _zz_315[0]; - assign decode_IS_MUL = _zz_316[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_317[0]; - assign decode_BRANCH_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign _zz_11 = _zz_12; - assign decode_SHIFT_CTRL = _zz_13; - assign _zz_14 = _zz_15; - assign decode_ALU_BITWISE_CTRL = _zz_16; - assign _zz_17 = _zz_18; - assign decode_SRC_LESS_UNSIGNED = _zz_318[0]; - assign memory_IS_SFENCE_VMA = execute_to_memory_IS_SFENCE_VMA; - assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; - assign decode_IS_SFENCE_VMA = _zz_319[0]; - assign decode_MEMORY_MANAGMENT = _zz_320[0]; + assign decode_IS_DIV = _zz_decode_IS_DIV[35]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_DIV[34]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_DIV[33]; + assign decode_IS_MUL = _zz_decode_IS_DIV[32]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_DIV[29]; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_DIV[22]; + assign decode_IS_SFENCE_VMA = _zz_decode_IS_DIV[21]; + assign decode_IS_SFENCE_VMA2 = _zz_decode_IS_DIV[20]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_DIV[19]; + assign memory_MEMORY_LRSC = execute_to_memory_MEMORY_LRSC; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_321[0]; + assign decode_MEMORY_WR = _zz_decode_IS_DIV[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_322[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_323[0]; - assign decode_SRC2_CTRL = _zz_19; - assign _zz_20 = _zz_21; - assign decode_ALU_CTRL = _zz_22; - assign _zz_23 = _zz_24; - assign decode_SRC1_CTRL = _zz_25; - assign _zz_26 = _zz_27; - assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_52; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_DIV[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_DIV[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = _zz_decode_MEMORY_FORCE_CONSTISTENCY; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; @@ -3061,23 +3099,24 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_28; - assign execute_ENV_CTRL = _zz_29; - assign writeBack_ENV_CTRL = _zz_30; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; + assign execute_IS_SFENCE_VMA = decode_to_execute_IS_SFENCE_VMA; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_31; - assign decode_RS2_USE = _zz_324[0]; - assign decode_RS1_USE = _zz_325[0]; - always @ (*) begin - _zz_32 = execute_REGFILE_WRITE_DATA; - if(_zz_252)begin - _zz_32 = execute_CsrPlugin_readData; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_DIV[17]; + assign decode_RS1_USE = _zz_decode_IS_DIV[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end - if(DBusCachedPlugin_forceDatapath)begin - _zz_32 = MmuPlugin_dBusAccess_cmd_payload_address; + if(DBusCachedPlugin_forceDatapath) begin + _zz_decode_RS2 = MmuPlugin_dBusAccess_cmd_payload_address; end end @@ -3087,141 +3126,158 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_122)begin - if((_zz_123 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_124; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_253)begin - if(_zz_254)begin - if(_zz_126)begin - decode_RS2 = _zz_51; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_255)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_128)begin - decode_RS2 = _zz_33; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_256)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_130)begin - decode_RS2 = _zz_32; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_122)begin - if((_zz_123 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_124; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_253)begin - if(_zz_254)begin - if(_zz_125)begin - decode_RS1 = _zz_51; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_255)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_127)begin - decode_RS1 = _zz_33; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_256)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_129)begin - decode_RS1 = _zz_32; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_33 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_33 = _zz_119; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_33 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(_zz_257)begin - _zz_33 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + if(when_MulDivIterativePlugin_l96) begin + _zz_decode_RS2_1 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_258)begin - _zz_33 = memory_MulDivIterativePlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_MulDivIterativePlugin_div_result; end end - assign memory_SHIFT_CTRL = _zz_34; - assign execute_SHIFT_CTRL = _zz_35; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_36 = execute_PC; - assign execute_SRC2_CTRL = _zz_37; - assign execute_SRC1_CTRL = _zz_38; - assign decode_SRC_USE_SUB_LESS = _zz_326[0]; - assign decode_SRC_ADD_ZERO = _zz_327[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_DIV[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_DIV[18]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_39; - assign execute_SRC2 = _zz_117; - assign execute_SRC1 = _zz_112; - assign execute_ALU_BITWISE_CTRL = _zz_40; - assign _zz_41 = writeBack_INSTRUCTION; - assign _zz_42 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_43 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_43 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_328[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_DIV[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_440) == 32'h00001073),{(_zz_441 == _zz_442),{_zz_443,{_zz_444,_zz_445}}}}}}} != 25'h0); - assign writeBack_IS_SFENCE_VMA = memory_to_writeBack_IS_SFENCE_VMA; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 25'h0); + assign execute_IS_SFENCE_VMA2 = decode_to_execute_IS_SFENCE_VMA2; assign writeBack_IS_DBUS_SHARING = memory_to_writeBack_IS_DBUS_SHARING; assign memory_IS_DBUS_SHARING = execute_to_memory_IS_DBUS_SHARING; - always @ (*) begin - _zz_51 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_51 = writeBack_DBusCachedPlugin_rspFormated; + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_LRSC = memory_to_writeBack_MEMORY_LRSC; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; - assign execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + always @(*) begin + execute_MEMORY_AMO = decode_to_execute_MEMORY_AMO; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + execute_MEMORY_AMO = 1'b0; + end + end + end + + always @(*) begin + execute_MEMORY_LRSC = decode_to_execute_MEMORY_LRSC; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + execute_MEMORY_LRSC = 1'b0; + end + end + end + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; assign execute_RS2 = decode_to_execute_RS2; @@ -3229,220 +3285,221 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_AMO = _zz_329[0]; - assign decode_MEMORY_LRSC = _zz_330[0]; - assign decode_MEMORY_ENABLE = _zz_331[0]; - assign decode_FLUSH_ALL = _zz_332[0]; - always @ (*) begin + assign decode_MEMORY_AMO = _zz_decode_IS_DIV[16]; + assign decode_MEMORY_LRSC = _zz_decode_IS_DIV[15]; + assign decode_MEMORY_ENABLE = _zz_decode_IS_DIV[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_DIV[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_259)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_260)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_261)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_262)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_53 = execute_FORMAL_PC_NEXT; - if(CsrPlugin_redoInterface_valid)begin - _zz_53 = CsrPlugin_redoInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(CsrPlugin_redoInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = CsrPlugin_redoInterface_payload; end end - always @ (*) begin - _zz_54 = memory_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_54 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if(MmuPlugin_dBusAccess_cmd_valid)begin + if(MmuPlugin_dBusAccess_cmd_valid) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if((decode_arbitration_isValid && (_zz_120 || _zz_121)))begin + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_263)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(_zz_263)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_225 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_264)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_252)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin execute_arbitration_flushNext = 1'b1; end - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeInstruction)begin - execute_arbitration_flushNext = 1'b1; - end + if(CsrPlugin_selfException_valid) begin + execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(_zz_257)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + if(when_MulDivIterativePlugin_l96) begin + if(when_MulDivIterativePlugin_l97) begin memory_arbitration_haltItself = 1'b1; end - if(_zz_265)begin + if(when_MulDivIterativePlugin_l100) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_258)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin memory_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3451,51 +3508,53 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if(((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid) || IBusCachedPlugin_iBusRsp_stages_3_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_264)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_266)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_267)begin - case(_zz_268) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3511,59 +3570,65 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_redoInterface_valid,{CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}} != 4'b0000); - assign _zz_55 = {CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_56 = (_zz_55 & (~ _zz_333)); - assign _zz_57 = _zz_56[3]; - assign _zz_58 = (_zz_56[1] || _zz_57); - assign _zz_59 = (_zz_56[2] || _zz_57); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_229; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {CsrPlugin_redoInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_335); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3572,66 +3637,78 @@ module VexRiscv ( assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; assign IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - assign _zz_60 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_60); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_60); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_61 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_61); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_61); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_62 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_62); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_62); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_3_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_3_halt = 1'b1; end end - assign _zz_63 = (! IBusCachedPlugin_iBusRsp_stages_3_halt); - assign IBusCachedPlugin_iBusRsp_stages_3_input_ready = (IBusCachedPlugin_iBusRsp_stages_3_output_ready && _zz_63); - assign IBusCachedPlugin_iBusRsp_stages_3_output_valid = (IBusCachedPlugin_iBusRsp_stages_3_input_valid && _zz_63); + assign _zz_IBusCachedPlugin_iBusRsp_stages_3_input_ready = (! IBusCachedPlugin_iBusRsp_stages_3_halt); + assign IBusCachedPlugin_iBusRsp_stages_3_input_ready = (IBusCachedPlugin_iBusRsp_stages_3_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_3_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_3_output_valid = (IBusCachedPlugin_iBusRsp_stages_3_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_3_input_ready); assign IBusCachedPlugin_iBusRsp_stages_3_output_payload = IBusCachedPlugin_iBusRsp_stages_3_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_3_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_64; - assign _zz_64 = ((1'b0 && (! _zz_65)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_65 = _zz_66; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_65; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_67)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_67 = _zz_68; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_67; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_69; - assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_3_input_ready); - assign _zz_70 = _zz_71; - assign IBusCachedPlugin_iBusRsp_stages_3_input_valid = _zz_70; - assign IBusCachedPlugin_iBusRsp_stages_3_input_payload = _zz_72; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_3_input_valid = IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_3_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_3_input_payload = IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = ((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid) || IBusCachedPlugin_iBusRsp_stages_3_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! (! IBusCachedPlugin_iBusRsp_stages_3_input_ready)); + assign when_Fetcher_l329_3 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_5 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_4; @@ -3639,87 +3716,99 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_193 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_194 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_195 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_194; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_2_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_197 = (IBusCachedPlugin_iBusRsp_stages_3_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_198 = (! IBusCachedPlugin_iBusRsp_stages_3_input_ready); - assign _zz_199 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_3_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_3_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_262)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_260)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_200 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_260)begin - _zz_200 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_261)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_259)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_261)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_259)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_3_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_3_output_valid; assign IBusCachedPlugin_iBusRsp_stages_3_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_3_output_payload; - assign _zz_192 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_226 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3727,328 +3816,320 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - always @ (*) begin - _zz_52 = 1'b0; - if(decode_INSTRUCTION[25])begin - if(decode_MEMORY_LRSC)begin - _zz_52 = 1'b1; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + always @(*) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + if(when_DBusCachedPlugin_l311) begin + if(decode_MEMORY_LRSC) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b1; end - if(decode_MEMORY_AMO)begin - _zz_52 = 1'b1; + if(decode_MEMORY_AMO) begin + _zz_decode_MEMORY_FORCE_CONSTISTENCY = 1'b1; end end end + assign when_DBusCachedPlugin_l311 = decode_INSTRUCTION[25]; assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin - _zz_201 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_269)begin - if(_zz_270)begin - _zz_201 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + if(when_DBusCachedPlugin_l499) begin + dataCache_1_io_cpu_execute_isValid = 1'b1; end end end end - always @ (*) begin - _zz_202 = execute_SRC_ADD; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_269)begin - _zz_202 = MmuPlugin_dBusAccess_cmd_payload_address; + always @(*) begin + dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_address = MmuPlugin_dBusAccess_cmd_payload_address; end end end - always @ (*) begin - _zz_203 = execute_MEMORY_WR; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_269)begin - _zz_203 = MmuPlugin_dBusAccess_cmd_payload_write; + always @(*) begin + dataCache_1_io_cpu_execute_args_wr = execute_MEMORY_WR; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_args_wr = 1'b0; end end end - always @ (*) begin + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_75 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_75 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_75 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - always @ (*) begin - _zz_204 = _zz_75; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_269)begin - _zz_204 = MmuPlugin_dBusAccess_cmd_payload_data; - end - end - end - - always @ (*) begin - _zz_205 = execute_DBusCachedPlugin_size; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_269)begin - _zz_205 = MmuPlugin_dBusAccess_cmd_payload_size; - end - end - end - - assign _zz_225 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - always @ (*) begin - _zz_206 = 1'b0; - if(execute_MEMORY_LRSC)begin - _zz_206 = 1'b1; - end - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_269)begin - _zz_206 = 1'b0; + always @(*) begin + dataCache_1_io_cpu_execute_args_size = execute_DBusCachedPlugin_size; + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + dataCache_1_io_cpu_execute_args_size = MmuPlugin_dBusAccess_cmd_payload_size; end end end - always @ (*) begin - _zz_207 = execute_MEMORY_AMO; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_269)begin - _zz_207 = 1'b0; - end + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + always @(*) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b0; + if(execute_MEMORY_LRSC) begin + dataCache_1_io_cpu_execute_args_isLrsc = 1'b1; end end - assign _zz_209 = execute_INSTRUCTION[31 : 29]; - assign _zz_208 = execute_INSTRUCTION[27]; - always @ (*) begin - _zz_210 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - if(memory_IS_DBUS_SHARING)begin - _zz_210 = 1'b1; + assign dataCache_1_io_cpu_execute_args_amoCtrl_alu = execute_INSTRUCTION[31 : 29]; + assign dataCache_1_io_cpu_execute_args_amoCtrl_swap = execute_INSTRUCTION[27]; + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + always @(*) begin + dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + if(memory_IS_DBUS_SHARING) begin + dataCache_1_io_cpu_memory_isValid = 1'b1; end end - assign _zz_211 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_210; + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_211; - always @ (*) begin + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; + always @(*) begin DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - if(memory_IS_DBUS_SHARING)begin + if(memory_IS_DBUS_SHARING) begin DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b1; end end assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_212 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_212 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; end end - always @ (*) begin - _zz_213 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - if(writeBack_IS_DBUS_SHARING)begin - _zz_213 = 1'b1; + assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_IS_DBUS_SHARING) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b1; + end + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_214 = (CsrPlugin_privilege == 2'b00); - assign _zz_215 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_271)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_271)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_271)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + always @(*) begin + writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + if(when_DBusCachedPlugin_l474) begin + writeBack_DBusCachedPlugin_rspRf = {31'd0, _zz_writeBack_DBusCachedPlugin_rspRf}; + end end - assign _zz_76 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_77[31] = _zz_76; - _zz_77[30] = _zz_76; - _zz_77[29] = _zz_76; - _zz_77[28] = _zz_76; - _zz_77[27] = _zz_76; - _zz_77[26] = _zz_76; - _zz_77[25] = _zz_76; - _zz_77[24] = _zz_76; - _zz_77[23] = _zz_76; - _zz_77[22] = _zz_76; - _zz_77[21] = _zz_76; - _zz_77[20] = _zz_76; - _zz_77[19] = _zz_76; - _zz_77[18] = _zz_76; - _zz_77[17] = _zz_76; - _zz_77[16] = _zz_76; - _zz_77[15] = _zz_76; - _zz_77[14] = _zz_76; - _zz_77[13] = _zz_76; - _zz_77[12] = _zz_76; - _zz_77[11] = _zz_76; - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_78 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_79[31] = _zz_78; - _zz_79[30] = _zz_78; - _zz_79[29] = _zz_78; - _zz_79[28] = _zz_78; - _zz_79[27] = _zz_78; - _zz_79[26] = _zz_78; - _zz_79[25] = _zz_78; - _zz_79[24] = _zz_78; - _zz_79[23] = _zz_78; - _zz_79[22] = _zz_78; - _zz_79[21] = _zz_78; - _zz_79[20] = _zz_78; - _zz_79[19] = _zz_78; - _zz_79[18] = _zz_78; - _zz_79[17] = _zz_78; - _zz_79[16] = _zz_78; - _zz_79[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_308) + assign when_DBusCachedPlugin_l474 = (writeBack_MEMORY_LRSC && writeBack_MEMORY_WR); + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_77; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_79; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end - always @ (*) begin + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + always @(*) begin MmuPlugin_dBusAccess_cmd_ready = 1'b0; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_269)begin - if(_zz_270)begin + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin + if(when_DBusCachedPlugin_l499) begin MmuPlugin_dBusAccess_cmd_ready = (! execute_arbitration_isStuck); end end end end - always @ (*) begin + always @(*) begin DBusCachedPlugin_forceDatapath = 1'b0; - if(MmuPlugin_dBusAccess_cmd_valid)begin - if(_zz_269)begin + if(MmuPlugin_dBusAccess_cmd_valid) begin + if(when_DBusCachedPlugin_l498) begin DBusCachedPlugin_forceDatapath = 1'b1; end end end + assign when_DBusCachedPlugin_l498 = (! ({(writeBack_arbitration_isValid || CsrPlugin_exceptionPendings_3),{(memory_arbitration_isValid || CsrPlugin_exceptionPendings_2),(execute_arbitration_isValid || CsrPlugin_exceptionPendings_1)}} != 3'b000)); + assign when_DBusCachedPlugin_l499 = (! dataCache_1_io_cpu_execute_refilling); + assign MmuPlugin_dBusAccess_cmd_fire = (MmuPlugin_dBusAccess_cmd_valid && MmuPlugin_dBusAccess_cmd_ready); assign MmuPlugin_dBusAccess_rsp_valid = ((writeBack_IS_DBUS_SHARING && (! dataCache_1_io_cpu_writeBack_isWrite)) && (dataCache_1_io_cpu_redo || (! dataCache_1_io_cpu_writeBack_haltIt))); - assign MmuPlugin_dBusAccess_rsp_payload_data = dataCache_1_io_cpu_writeBack_data; + assign MmuPlugin_dBusAccess_rsp_payload_data = writeBack_DBusCachedPlugin_rspRf; assign MmuPlugin_dBusAccess_rsp_payload_error = (dataCache_1_io_cpu_writeBack_unalignedAccess || dataCache_1_io_cpu_writeBack_accessError); assign MmuPlugin_dBusAccess_rsp_payload_redo = dataCache_1_io_cpu_redo; assign MmuPlugin_ports_0_dirty = 1'b0; - always @ (*) begin + always @(*) begin MmuPlugin_ports_0_requireMmuLockupCalc = ((1'b1 && (! IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + if(when_MmuPlugin_l125) begin MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; end - if((CsrPlugin_privilege == 2'b11))begin + if(when_MmuPlugin_l126) begin MmuPlugin_ports_0_requireMmuLockupCalc = 1'b0; end end - always @ (*) begin - MmuPlugin_ports_0_cacheHitsCalc[0] = ((MmuPlugin_ports_0_cache_0_valid && (MmuPlugin_ports_0_cache_0_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_0_superPage || (MmuPlugin_ports_0_cache_0_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_0_cacheHitsCalc[1] = ((MmuPlugin_ports_0_cache_1_valid && (MmuPlugin_ports_0_cache_1_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_1_superPage || (MmuPlugin_ports_0_cache_1_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_0_cacheHitsCalc[2] = ((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_0_cacheHitsCalc[3] = ((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - end - + assign when_MmuPlugin_l125 = ((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)); + assign when_MmuPlugin_l126 = (CsrPlugin_privilege == 2'b11); + assign MmuPlugin_ports_0_cacheHitsCalc = {((MmuPlugin_ports_0_cache_3_valid && (MmuPlugin_ports_0_cache_3_virtualAddress_1 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_0_cache_3_superPage || (MmuPlugin_ports_0_cache_3_virtualAddress_0 == IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))),{((MmuPlugin_ports_0_cache_2_valid && (MmuPlugin_ports_0_cache_2_virtualAddress_1 == _zz_MmuPlugin_ports_0_cacheHitsCalc)) && (MmuPlugin_ports_0_cache_2_superPage || (MmuPlugin_ports_0_cache_2_virtualAddress_0 == _zz_MmuPlugin_ports_0_cacheHitsCalc_1))),{((MmuPlugin_ports_0_cache_1_valid && _zz_MmuPlugin_ports_0_cacheHitsCalc_2) && (MmuPlugin_ports_0_cache_1_superPage || _zz_MmuPlugin_ports_0_cacheHitsCalc_3)),((MmuPlugin_ports_0_cache_0_valid && _zz_MmuPlugin_ports_0_cacheHitsCalc_4) && (MmuPlugin_ports_0_cache_0_superPage || _zz_MmuPlugin_ports_0_cacheHitsCalc_5))}}}; assign MmuPlugin_ports_0_cacheHit = (MmuPlugin_ports_0_cacheHitsCalc != 4'b0000); - assign _zz_80 = MmuPlugin_ports_0_cacheHitsCalc[3]; - assign _zz_81 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_80); - assign _zz_82 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_80); - assign _zz_83 = {_zz_82,_zz_81}; - assign MmuPlugin_ports_0_cacheLine_valid = _zz_230; - assign MmuPlugin_ports_0_cacheLine_exception = _zz_231; - assign MmuPlugin_ports_0_cacheLine_superPage = _zz_232; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_233; - assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_234; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_235; - assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_236; - assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_237; - assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_238; - assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_239; - assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_240; - always @ (*) begin + assign _zz_MmuPlugin_ports_0_cacheLine_valid = MmuPlugin_ports_0_cacheHitsCalc[3]; + assign _zz_MmuPlugin_ports_0_cacheLine_valid_1 = (MmuPlugin_ports_0_cacheHitsCalc[1] || _zz_MmuPlugin_ports_0_cacheLine_valid); + assign _zz_MmuPlugin_ports_0_cacheLine_valid_2 = (MmuPlugin_ports_0_cacheHitsCalc[2] || _zz_MmuPlugin_ports_0_cacheLine_valid); + assign _zz_MmuPlugin_ports_0_cacheLine_valid_3 = {_zz_MmuPlugin_ports_0_cacheLine_valid_2,_zz_MmuPlugin_ports_0_cacheLine_valid_1}; + assign MmuPlugin_ports_0_cacheLine_valid = _zz_MmuPlugin_ports_0_cacheLine_valid_4; + assign MmuPlugin_ports_0_cacheLine_exception = _zz_MmuPlugin_ports_0_cacheLine_exception; + assign MmuPlugin_ports_0_cacheLine_superPage = _zz_MmuPlugin_ports_0_cacheLine_superPage; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_0 = _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_0; + assign MmuPlugin_ports_0_cacheLine_virtualAddress_1 = _zz_MmuPlugin_ports_0_cacheLine_virtualAddress_1; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_0 = _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_0; + assign MmuPlugin_ports_0_cacheLine_physicalAddress_1 = _zz_MmuPlugin_ports_0_cacheLine_physicalAddress_1; + assign MmuPlugin_ports_0_cacheLine_allowRead = _zz_MmuPlugin_ports_0_cacheLine_allowRead; + assign MmuPlugin_ports_0_cacheLine_allowWrite = _zz_MmuPlugin_ports_0_cacheLine_allowWrite; + assign MmuPlugin_ports_0_cacheLine_allowExecute = _zz_MmuPlugin_ports_0_cacheLine_allowExecute; + assign MmuPlugin_ports_0_cacheLine_allowUser = _zz_MmuPlugin_ports_0_cacheLine_allowUser; + always @(*) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b0; - if(_zz_272)begin - if(_zz_273)begin + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin MmuPlugin_ports_0_entryToReplace_willIncrement = 1'b1; end end @@ -4057,63 +4138,63 @@ module VexRiscv ( assign MmuPlugin_ports_0_entryToReplace_willClear = 1'b0; assign MmuPlugin_ports_0_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); assign MmuPlugin_ports_0_entryToReplace_willOverflow = (MmuPlugin_ports_0_entryToReplace_willOverflowIfInc && MmuPlugin_ports_0_entryToReplace_willIncrement); - always @ (*) begin - MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_339); - if(MmuPlugin_ports_0_entryToReplace_willClear)begin + always @(*) begin + MmuPlugin_ports_0_entryToReplace_valueNext = (MmuPlugin_ports_0_entryToReplace_value + _zz_MmuPlugin_ports_0_entryToReplace_valueNext); + if(MmuPlugin_ports_0_entryToReplace_willClear) begin MmuPlugin_ports_0_entryToReplace_valueNext = 2'b00; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_0_cacheLine_physicalAddress_1,(MmuPlugin_ports_0_cacheLine_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cacheLine_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; end else begin IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_0_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_0_cacheLine_allowExecute)); end else begin IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_0_cacheLine_allowWrite; end else begin IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_0_cacheLine_allowExecute; end else begin IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_0_dirty) && MmuPlugin_ports_0_cacheHit) && ((MmuPlugin_ports_0_cacheLine_exception || ((MmuPlugin_ports_0_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_0_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_0_dirty || (! MmuPlugin_ports_0_cacheHit)); end else begin IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_0_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_0_requireMmuLockupCalc) begin IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; @@ -4131,45 +4212,42 @@ module VexRiscv ( assign IBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_0_cacheHitsCalc[3]; assign IBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_0_cache_3_physicalAddress_1,(MmuPlugin_ports_0_cache_3_superPage ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_0_cache_3_physicalAddress_0)},IBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; assign MmuPlugin_ports_1_dirty = 1'b0; - always @ (*) begin + always @(*) begin MmuPlugin_ports_1_requireMmuLockupCalc = ((1'b1 && (! DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation)) && MmuPlugin_satp_mode); - if(((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)))begin + if(when_MmuPlugin_l125_1) begin MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; end - if((CsrPlugin_privilege == 2'b11))begin - if(((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)))begin + if(when_MmuPlugin_l126_1) begin + if(when_MmuPlugin_l128) begin MmuPlugin_ports_1_requireMmuLockupCalc = 1'b0; end end end - always @ (*) begin - MmuPlugin_ports_1_cacheHitsCalc[0] = ((MmuPlugin_ports_1_cache_0_valid && (MmuPlugin_ports_1_cache_0_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_0_superPage || (MmuPlugin_ports_1_cache_0_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_1_cacheHitsCalc[1] = ((MmuPlugin_ports_1_cache_1_valid && (MmuPlugin_ports_1_cache_1_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_1_superPage || (MmuPlugin_ports_1_cache_1_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_1_cacheHitsCalc[2] = ((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - MmuPlugin_ports_1_cacheHitsCalc[3] = ((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))); - end - + assign when_MmuPlugin_l125_1 = ((! MmuPlugin_status_mprv) && (CsrPlugin_privilege == 2'b11)); + assign when_MmuPlugin_l126_1 = (CsrPlugin_privilege == 2'b11); + assign when_MmuPlugin_l128 = ((! MmuPlugin_status_mprv) || (CsrPlugin_mstatus_MPP == 2'b11)); + assign MmuPlugin_ports_1_cacheHitsCalc = {((MmuPlugin_ports_1_cache_3_valid && (MmuPlugin_ports_1_cache_3_virtualAddress_1 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[31 : 22])) && (MmuPlugin_ports_1_cache_3_superPage || (MmuPlugin_ports_1_cache_3_virtualAddress_0 == DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12]))),{((MmuPlugin_ports_1_cache_2_valid && (MmuPlugin_ports_1_cache_2_virtualAddress_1 == _zz_MmuPlugin_ports_1_cacheHitsCalc)) && (MmuPlugin_ports_1_cache_2_superPage || (MmuPlugin_ports_1_cache_2_virtualAddress_0 == _zz_MmuPlugin_ports_1_cacheHitsCalc_1))),{((MmuPlugin_ports_1_cache_1_valid && _zz_MmuPlugin_ports_1_cacheHitsCalc_2) && (MmuPlugin_ports_1_cache_1_superPage || _zz_MmuPlugin_ports_1_cacheHitsCalc_3)),((MmuPlugin_ports_1_cache_0_valid && _zz_MmuPlugin_ports_1_cacheHitsCalc_4) && (MmuPlugin_ports_1_cache_0_superPage || _zz_MmuPlugin_ports_1_cacheHitsCalc_5))}}}; assign MmuPlugin_ports_1_cacheHit = (MmuPlugin_ports_1_cacheHitsCalc != 4'b0000); - assign _zz_84 = MmuPlugin_ports_1_cacheHitsCalc[3]; - assign _zz_85 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_84); - assign _zz_86 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_84); - assign _zz_87 = {_zz_86,_zz_85}; - assign MmuPlugin_ports_1_cacheLine_valid = _zz_241; - assign MmuPlugin_ports_1_cacheLine_exception = _zz_242; - assign MmuPlugin_ports_1_cacheLine_superPage = _zz_243; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_244; - assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_245; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_246; - assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_247; - assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_248; - assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_249; - assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_250; - assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_251; - always @ (*) begin + assign _zz_MmuPlugin_ports_1_cacheLine_valid = MmuPlugin_ports_1_cacheHitsCalc[3]; + assign _zz_MmuPlugin_ports_1_cacheLine_valid_1 = (MmuPlugin_ports_1_cacheHitsCalc[1] || _zz_MmuPlugin_ports_1_cacheLine_valid); + assign _zz_MmuPlugin_ports_1_cacheLine_valid_2 = (MmuPlugin_ports_1_cacheHitsCalc[2] || _zz_MmuPlugin_ports_1_cacheLine_valid); + assign _zz_MmuPlugin_ports_1_cacheLine_valid_3 = {_zz_MmuPlugin_ports_1_cacheLine_valid_2,_zz_MmuPlugin_ports_1_cacheLine_valid_1}; + assign MmuPlugin_ports_1_cacheLine_valid = _zz_MmuPlugin_ports_1_cacheLine_valid_4; + assign MmuPlugin_ports_1_cacheLine_exception = _zz_MmuPlugin_ports_1_cacheLine_exception; + assign MmuPlugin_ports_1_cacheLine_superPage = _zz_MmuPlugin_ports_1_cacheLine_superPage; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_0 = _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_0; + assign MmuPlugin_ports_1_cacheLine_virtualAddress_1 = _zz_MmuPlugin_ports_1_cacheLine_virtualAddress_1; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_0 = _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_0; + assign MmuPlugin_ports_1_cacheLine_physicalAddress_1 = _zz_MmuPlugin_ports_1_cacheLine_physicalAddress_1; + assign MmuPlugin_ports_1_cacheLine_allowRead = _zz_MmuPlugin_ports_1_cacheLine_allowRead; + assign MmuPlugin_ports_1_cacheLine_allowWrite = _zz_MmuPlugin_ports_1_cacheLine_allowWrite; + assign MmuPlugin_ports_1_cacheLine_allowExecute = _zz_MmuPlugin_ports_1_cacheLine_allowExecute; + assign MmuPlugin_ports_1_cacheLine_allowUser = _zz_MmuPlugin_ports_1_cacheLine_allowUser; + always @(*) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b0; - if(_zz_272)begin - if(_zz_274)begin + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274_1) begin MmuPlugin_ports_1_entryToReplace_willIncrement = 1'b1; end end @@ -4178,63 +4256,63 @@ module VexRiscv ( assign MmuPlugin_ports_1_entryToReplace_willClear = 1'b0; assign MmuPlugin_ports_1_entryToReplace_willOverflowIfInc = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); assign MmuPlugin_ports_1_entryToReplace_willOverflow = (MmuPlugin_ports_1_entryToReplace_willOverflowIfInc && MmuPlugin_ports_1_entryToReplace_willIncrement); - always @ (*) begin - MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_341); - if(MmuPlugin_ports_1_entryToReplace_willClear)begin + always @(*) begin + MmuPlugin_ports_1_entryToReplace_valueNext = (MmuPlugin_ports_1_entryToReplace_value + _zz_MmuPlugin_ports_1_entryToReplace_valueNext); + if(MmuPlugin_ports_1_entryToReplace_willClear) begin MmuPlugin_ports_1_entryToReplace_valueNext = 2'b00; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_physicalAddress = {{MmuPlugin_ports_1_cacheLine_physicalAddress_1,(MmuPlugin_ports_1_cacheLine_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cacheLine_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; end else begin DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_allowRead = (MmuPlugin_ports_1_cacheLine_allowRead || (MmuPlugin_status_mxr && MmuPlugin_ports_1_cacheLine_allowExecute)); end else begin DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_allowWrite = MmuPlugin_ports_1_cacheLine_allowWrite; end else begin DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_allowExecute = MmuPlugin_ports_1_cacheLine_allowExecute; end else begin DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_exception = (((! MmuPlugin_ports_1_dirty) && MmuPlugin_ports_1_cacheHit) && ((MmuPlugin_ports_1_cacheLine_exception || ((MmuPlugin_ports_1_cacheLine_allowUser && (CsrPlugin_privilege == 2'b01)) && (! MmuPlugin_status_sum))) || ((! MmuPlugin_ports_1_cacheLine_allowUser) && (CsrPlugin_privilege == 2'b00)))); end else begin DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_refilling = (MmuPlugin_ports_1_dirty || (! MmuPlugin_ports_1_cacheHit)); end else begin DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; end end - always @ (*) begin - if(MmuPlugin_ports_1_requireMmuLockupCalc)begin + always @(*) begin + if(MmuPlugin_ports_1_requireMmuLockupCalc) begin DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b1; end else begin DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; @@ -4251,30 +4329,31 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_ways_2_physical = {{MmuPlugin_ports_1_cache_2_physicalAddress_1,(MmuPlugin_ports_1_cache_2_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_2_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; assign DBusCachedPlugin_mmuBus_rsp_ways_3_sel = MmuPlugin_ports_1_cacheHitsCalc[3]; assign DBusCachedPlugin_mmuBus_rsp_ways_3_physical = {{MmuPlugin_ports_1_cache_3_physicalAddress_1,(MmuPlugin_ports_1_cache_3_superPage ? DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[21 : 12] : MmuPlugin_ports_1_cache_3_physicalAddress_0)},DBusCachedPlugin_mmuBus_cmd_0_virtualAddress[11 : 0]}; - assign MmuPlugin_shared_dBusRsp_pte_V = _zz_342[0]; - assign MmuPlugin_shared_dBusRsp_pte_R = _zz_343[0]; - assign MmuPlugin_shared_dBusRsp_pte_W = _zz_344[0]; - assign MmuPlugin_shared_dBusRsp_pte_X = _zz_345[0]; - assign MmuPlugin_shared_dBusRsp_pte_U = _zz_346[0]; - assign MmuPlugin_shared_dBusRsp_pte_G = _zz_347[0]; - assign MmuPlugin_shared_dBusRsp_pte_A = _zz_348[0]; - assign MmuPlugin_shared_dBusRsp_pte_D = _zz_349[0]; + assign MmuPlugin_shared_dBusRsp_pte_V = MmuPlugin_shared_dBusRspStaged_payload_data[0]; + assign MmuPlugin_shared_dBusRsp_pte_R = MmuPlugin_shared_dBusRspStaged_payload_data[1]; + assign MmuPlugin_shared_dBusRsp_pte_W = MmuPlugin_shared_dBusRspStaged_payload_data[2]; + assign MmuPlugin_shared_dBusRsp_pte_X = MmuPlugin_shared_dBusRspStaged_payload_data[3]; + assign MmuPlugin_shared_dBusRsp_pte_U = MmuPlugin_shared_dBusRspStaged_payload_data[4]; + assign MmuPlugin_shared_dBusRsp_pte_G = MmuPlugin_shared_dBusRspStaged_payload_data[5]; + assign MmuPlugin_shared_dBusRsp_pte_A = MmuPlugin_shared_dBusRspStaged_payload_data[6]; + assign MmuPlugin_shared_dBusRsp_pte_D = MmuPlugin_shared_dBusRspStaged_payload_data[7]; assign MmuPlugin_shared_dBusRsp_pte_RSW = MmuPlugin_shared_dBusRspStaged_payload_data[9 : 8]; assign MmuPlugin_shared_dBusRsp_pte_PPN0 = MmuPlugin_shared_dBusRspStaged_payload_data[19 : 10]; assign MmuPlugin_shared_dBusRsp_pte_PPN1 = MmuPlugin_shared_dBusRspStaged_payload_data[31 : 20]; assign MmuPlugin_shared_dBusRsp_exception = (((! MmuPlugin_shared_dBusRsp_pte_V) || ((! MmuPlugin_shared_dBusRsp_pte_R) && MmuPlugin_shared_dBusRsp_pte_W)) || MmuPlugin_shared_dBusRspStaged_payload_error); assign MmuPlugin_shared_dBusRsp_leaf = (MmuPlugin_shared_dBusRsp_pte_R || MmuPlugin_shared_dBusRsp_pte_X); - always @ (*) begin + assign when_MmuPlugin_l205 = (MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)); + always @(*) begin MmuPlugin_dBusAccess_cmd_valid = 1'b0; case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + `MmuPlugin_shared_State_binary_sequential_IDLE : begin end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin MmuPlugin_dBusAccess_cmd_valid = 1'b1; end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin MmuPlugin_dBusAccess_cmd_valid = 1'b1; end default : begin @@ -4284,17 +4363,17 @@ module VexRiscv ( assign MmuPlugin_dBusAccess_cmd_payload_write = 1'b0; assign MmuPlugin_dBusAccess_cmd_payload_size = 2'b10; - always @ (*) begin - MmuPlugin_dBusAccess_cmd_payload_address = 32'h0; + always @(*) begin + MmuPlugin_dBusAccess_cmd_payload_address = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin + `MmuPlugin_shared_State_binary_sequential_IDLE : begin end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin MmuPlugin_dBusAccess_cmd_payload_address = {{MmuPlugin_satp_ppn,MmuPlugin_shared_vpn_1},2'b00}; end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin MmuPlugin_dBusAccess_cmd_payload_address = {{{MmuPlugin_shared_pteBuffer_PPN1[9 : 0],MmuPlugin_shared_pteBuffer_PPN0},MmuPlugin_shared_vpn_0},2'b00}; end default : begin @@ -4302,86 +4381,97 @@ module VexRiscv ( endcase end - assign MmuPlugin_dBusAccess_cmd_payload_data = 32'h0; + assign MmuPlugin_dBusAccess_cmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign MmuPlugin_dBusAccess_cmd_payload_writeMask = 4'bxxxx; - always @ (*) begin - _zz_88[0] = (((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit)); - _zz_88[1] = (((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)); - end - - assign _zz_89 = _zz_88; - always @ (*) begin - _zz_90[0] = _zz_89[1]; - _zz_90[1] = _zz_89[0]; - end - - assign _zz_91 = (_zz_90 & (~ _zz_350)); - always @ (*) begin - _zz_92[0] = _zz_91[1]; - _zz_92[1] = _zz_91[0]; - end - - assign MmuPlugin_shared_refills = _zz_92; - assign _zz_93 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); - assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[0]); - assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_defaultEncoding_IDLE) && MmuPlugin_shared_portSortedOh[1]); - assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_97 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); - assign _zz_98 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_99 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_100 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_101 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); - assign _zz_102 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); - assign _zz_94 = {(((decode_INSTRUCTION & _zz_463) == 32'h02004020) != 1'b0),{({_zz_102,_zz_101} != 2'b00),{({_zz_464,_zz_465} != 3'b000),{(_zz_466 != _zz_467),{_zz_468,{_zz_469,_zz_470}}}}}}; - assign _zz_103 = _zz_94[2 : 1]; - assign _zz_50 = _zz_103; - assign _zz_104 = _zz_94[7 : 6]; - assign _zz_49 = _zz_104; - assign _zz_105 = _zz_94[9 : 8]; - assign _zz_48 = _zz_105; - assign _zz_106 = _zz_94[23 : 22]; - assign _zz_47 = _zz_106; - assign _zz_107 = _zz_94[25 : 24]; - assign _zz_46 = _zz_107; - assign _zz_108 = _zz_94[27 : 26]; - assign _zz_45 = _zz_108; - assign _zz_109 = _zz_94[30 : 29]; - assign _zz_44 = _zz_109; + assign _zz_MmuPlugin_shared_refills = {(((DBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_1_requireMmuLockupCalc) && (! MmuPlugin_ports_1_dirty)) && (! MmuPlugin_ports_1_cacheHit)),(((IBusCachedPlugin_mmuBus_cmd_0_isValid && MmuPlugin_ports_0_requireMmuLockupCalc) && (! MmuPlugin_ports_0_dirty)) && (! MmuPlugin_ports_0_cacheHit))}; + always @(*) begin + _zz_MmuPlugin_shared_refills_1[0] = _zz_MmuPlugin_shared_refills[1]; + _zz_MmuPlugin_shared_refills_1[1] = _zz_MmuPlugin_shared_refills[0]; + end + + assign _zz_MmuPlugin_shared_refills_2 = (_zz_MmuPlugin_shared_refills_1 & (~ _zz__zz_MmuPlugin_shared_refills_2)); + always @(*) begin + _zz_MmuPlugin_shared_refills_3[0] = _zz_MmuPlugin_shared_refills_2[1]; + _zz_MmuPlugin_shared_refills_3[1] = _zz_MmuPlugin_shared_refills_2[0]; + end + + assign MmuPlugin_shared_refills = _zz_MmuPlugin_shared_refills_3; + assign when_MmuPlugin_l217 = (MmuPlugin_shared_refills != 2'b00); + assign _zz_MmuPlugin_shared_vpn_0 = (MmuPlugin_shared_refills[0] ? IBusCachedPlugin_mmuBus_cmd_0_virtualAddress : DBusCachedPlugin_mmuBus_cmd_0_virtualAddress); + assign when_MmuPlugin_l243 = (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception); + assign IBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_binary_sequential_IDLE) && MmuPlugin_shared_portSortedOh[0]); + assign DBusCachedPlugin_mmuBus_busy = ((MmuPlugin_shared_state_1 != `MmuPlugin_shared_State_binary_sequential_IDLE) && MmuPlugin_shared_portSortedOh[1]); + assign when_MmuPlugin_l272 = ((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)) && (MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception)); + assign when_MmuPlugin_l274 = MmuPlugin_shared_portSortedOh[0]; + assign when_MmuPlugin_l280 = (MmuPlugin_ports_0_entryToReplace_value == 2'b00); + assign when_MmuPlugin_l280_1 = (MmuPlugin_ports_0_entryToReplace_value == 2'b01); + assign when_MmuPlugin_l280_2 = (MmuPlugin_ports_0_entryToReplace_value == 2'b10); + assign when_MmuPlugin_l280_3 = (MmuPlugin_ports_0_entryToReplace_value == 2'b11); + assign when_MmuPlugin_l274_1 = MmuPlugin_shared_portSortedOh[1]; + assign when_MmuPlugin_l280_4 = (MmuPlugin_ports_1_entryToReplace_value == 2'b00); + assign when_MmuPlugin_l280_5 = (MmuPlugin_ports_1_entryToReplace_value == 2'b01); + assign when_MmuPlugin_l280_6 = (MmuPlugin_ports_1_entryToReplace_value == 2'b10); + assign when_MmuPlugin_l280_7 = (MmuPlugin_ports_1_entryToReplace_value == 2'b11); + assign when_MmuPlugin_l304 = ((execute_arbitration_isValid && execute_arbitration_isFiring) && execute_IS_SFENCE_VMA2); + assign _zz_decode_IS_DIV_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_DIV_2 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_DIV_3 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002000); + assign _zz_decode_IS_DIV_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_DIV_5 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz_decode_IS_DIV_6 = ((decode_INSTRUCTION & 32'h02003050) == 32'h02000050); + assign _zz_decode_IS_DIV_7 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_decode_IS_DIV_8 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); + assign _zz_decode_IS_DIV_9 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); + assign _zz_decode_IS_DIV = {(((decode_INSTRUCTION & _zz__zz_decode_IS_DIV) == 32'h02004020) != 1'b0),{({_zz_decode_IS_DIV_9,_zz_decode_IS_DIV_8} != 2'b00),{({_zz__zz_decode_IS_DIV_1,_zz__zz_decode_IS_DIV_2} != 3'b000),{(_zz__zz_decode_IS_DIV_3 != _zz__zz_decode_IS_DIV_4),{_zz__zz_decode_IS_DIV_5,{_zz__zz_decode_IS_DIV_7,_zz__zz_decode_IS_DIV_10}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_DIV[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_DIV[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_DIV[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_DIV[24 : 23]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_DIV[26 : 25]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_DIV[28 : 27]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_DIV[31 : 30]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_227; - assign decode_RegFilePlugin_rs2Data = _zz_228; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_42 && writeBack_arbitration_isFiring); - if(_zz_110)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_41[11 : 7]; - if(_zz_110)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_51; - if(_zz_110)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_2) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -4390,362 +4480,385 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_111 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_111 = {31'd0, _zz_351}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_111 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_112 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_112 = {29'd0, _zz_352}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_112 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_112 = {27'd0, _zz_353}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_113 = _zz_354[11]; - always @ (*) begin - _zz_114[19] = _zz_113; - _zz_114[18] = _zz_113; - _zz_114[17] = _zz_113; - _zz_114[16] = _zz_113; - _zz_114[15] = _zz_113; - _zz_114[14] = _zz_113; - _zz_114[13] = _zz_113; - _zz_114[12] = _zz_113; - _zz_114[11] = _zz_113; - _zz_114[10] = _zz_113; - _zz_114[9] = _zz_113; - _zz_114[8] = _zz_113; - _zz_114[7] = _zz_113; - _zz_114[6] = _zz_113; - _zz_114[5] = _zz_113; - _zz_114[4] = _zz_113; - _zz_114[3] = _zz_113; - _zz_114[2] = _zz_113; - _zz_114[1] = _zz_113; - _zz_114[0] = _zz_113; - end - - assign _zz_115 = _zz_355[11]; - always @ (*) begin - _zz_116[19] = _zz_115; - _zz_116[18] = _zz_115; - _zz_116[17] = _zz_115; - _zz_116[16] = _zz_115; - _zz_116[15] = _zz_115; - _zz_116[14] = _zz_115; - _zz_116[13] = _zz_115; - _zz_116[12] = _zz_115; - _zz_116[11] = _zz_115; - _zz_116[10] = _zz_115; - _zz_116[9] = _zz_115; - _zz_116[8] = _zz_115; - _zz_116[7] = _zz_115; - _zz_116[6] = _zz_115; - _zz_116[5] = _zz_115; - _zz_116[4] = _zz_115; - _zz_116[3] = _zz_115; - _zz_116[2] = _zz_115; - _zz_116[1] = _zz_115; - _zz_116[0] = _zz_115; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_117 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_117 = {_zz_114,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_117 = {_zz_116,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_117 = _zz_36; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_356; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_118[0] = execute_SRC1[31]; - _zz_118[1] = execute_SRC1[30]; - _zz_118[2] = execute_SRC1[29]; - _zz_118[3] = execute_SRC1[28]; - _zz_118[4] = execute_SRC1[27]; - _zz_118[5] = execute_SRC1[26]; - _zz_118[6] = execute_SRC1[25]; - _zz_118[7] = execute_SRC1[24]; - _zz_118[8] = execute_SRC1[23]; - _zz_118[9] = execute_SRC1[22]; - _zz_118[10] = execute_SRC1[21]; - _zz_118[11] = execute_SRC1[20]; - _zz_118[12] = execute_SRC1[19]; - _zz_118[13] = execute_SRC1[18]; - _zz_118[14] = execute_SRC1[17]; - _zz_118[15] = execute_SRC1[16]; - _zz_118[16] = execute_SRC1[15]; - _zz_118[17] = execute_SRC1[14]; - _zz_118[18] = execute_SRC1[13]; - _zz_118[19] = execute_SRC1[12]; - _zz_118[20] = execute_SRC1[11]; - _zz_118[21] = execute_SRC1[10]; - _zz_118[22] = execute_SRC1[9]; - _zz_118[23] = execute_SRC1[8]; - _zz_118[24] = execute_SRC1[7]; - _zz_118[25] = execute_SRC1[6]; - _zz_118[26] = execute_SRC1[5]; - _zz_118[27] = execute_SRC1[4]; - _zz_118[28] = execute_SRC1[3]; - _zz_118[29] = execute_SRC1[2]; - _zz_118[30] = execute_SRC1[1]; - _zz_118[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_118 : execute_SRC1); - always @ (*) begin - _zz_119[0] = memory_SHIFT_RIGHT[31]; - _zz_119[1] = memory_SHIFT_RIGHT[30]; - _zz_119[2] = memory_SHIFT_RIGHT[29]; - _zz_119[3] = memory_SHIFT_RIGHT[28]; - _zz_119[4] = memory_SHIFT_RIGHT[27]; - _zz_119[5] = memory_SHIFT_RIGHT[26]; - _zz_119[6] = memory_SHIFT_RIGHT[25]; - _zz_119[7] = memory_SHIFT_RIGHT[24]; - _zz_119[8] = memory_SHIFT_RIGHT[23]; - _zz_119[9] = memory_SHIFT_RIGHT[22]; - _zz_119[10] = memory_SHIFT_RIGHT[21]; - _zz_119[11] = memory_SHIFT_RIGHT[20]; - _zz_119[12] = memory_SHIFT_RIGHT[19]; - _zz_119[13] = memory_SHIFT_RIGHT[18]; - _zz_119[14] = memory_SHIFT_RIGHT[17]; - _zz_119[15] = memory_SHIFT_RIGHT[16]; - _zz_119[16] = memory_SHIFT_RIGHT[15]; - _zz_119[17] = memory_SHIFT_RIGHT[14]; - _zz_119[18] = memory_SHIFT_RIGHT[13]; - _zz_119[19] = memory_SHIFT_RIGHT[12]; - _zz_119[20] = memory_SHIFT_RIGHT[11]; - _zz_119[21] = memory_SHIFT_RIGHT[10]; - _zz_119[22] = memory_SHIFT_RIGHT[9]; - _zz_119[23] = memory_SHIFT_RIGHT[8]; - _zz_119[24] = memory_SHIFT_RIGHT[7]; - _zz_119[25] = memory_SHIFT_RIGHT[6]; - _zz_119[26] = memory_SHIFT_RIGHT[5]; - _zz_119[27] = memory_SHIFT_RIGHT[4]; - _zz_119[28] = memory_SHIFT_RIGHT[3]; - _zz_119[29] = memory_SHIFT_RIGHT[2]; - _zz_119[30] = memory_SHIFT_RIGHT[1]; - _zz_119[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_120 = 1'b0; - if(_zz_275)begin - if(_zz_276)begin - if(_zz_125)begin - _zz_120 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_277)begin - if(_zz_278)begin - if(_zz_127)begin - _zz_120 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_279)begin - if(_zz_280)begin - if(_zz_129)begin - _zz_120 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_120 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_121 = 1'b0; - if(_zz_275)begin - if(_zz_276)begin - if(_zz_126)begin - _zz_121 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_277)begin - if(_zz_278)begin - if(_zz_128)begin - _zz_121 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_279)begin - if(_zz_280)begin - if(_zz_130)begin - _zz_121 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_121 = 1'b0; - end - end - - assign _zz_125 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_126 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_127 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_128 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_129 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_130 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_131 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_131 == 3'b000)) begin - _zz_132 = execute_BranchPlugin_eq; - end else if((_zz_131 == 3'b001)) begin - _zz_132 = (! execute_BranchPlugin_eq); - end else if((((_zz_131 & 3'b101) == 3'b101))) begin - _zz_132 = (! execute_SRC_LESS); - end else begin - _zz_132 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_DO = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_133 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_DO_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_133 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_DO_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_133 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_DO_1 = 1'b1; end default : begin - _zz_133 = _zz_132; + _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; end endcase end - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_134 = _zz_363[19]; - always @ (*) begin - _zz_135[10] = _zz_134; - _zz_135[9] = _zz_134; - _zz_135[8] = _zz_134; - _zz_135[7] = _zz_134; - _zz_135[6] = _zz_134; - _zz_135[5] = _zz_134; - _zz_135[4] = _zz_134; - _zz_135[3] = _zz_134; - _zz_135[2] = _zz_134; - _zz_135[1] = _zz_134; - _zz_135[0] = _zz_134; - end - - assign _zz_136 = _zz_364[11]; - always @ (*) begin - _zz_137[19] = _zz_136; - _zz_137[18] = _zz_136; - _zz_137[17] = _zz_136; - _zz_137[16] = _zz_136; - _zz_137[15] = _zz_136; - _zz_137[14] = _zz_136; - _zz_137[13] = _zz_136; - _zz_137[12] = _zz_136; - _zz_137[11] = _zz_136; - _zz_137[10] = _zz_136; - _zz_137[9] = _zz_136; - _zz_137[8] = _zz_136; - _zz_137[7] = _zz_136; - _zz_137[6] = _zz_136; - _zz_137[5] = _zz_136; - _zz_137[4] = _zz_136; - _zz_137[3] = _zz_136; - _zz_137[2] = _zz_136; - _zz_137[1] = _zz_136; - _zz_137[0] = _zz_136; - end - - assign _zz_138 = _zz_365[11]; - always @ (*) begin - _zz_139[18] = _zz_138; - _zz_139[17] = _zz_138; - _zz_139[16] = _zz_138; - _zz_139[15] = _zz_138; - _zz_139[14] = _zz_138; - _zz_139[13] = _zz_138; - _zz_139[12] = _zz_138; - _zz_139[11] = _zz_138; - _zz_139[10] = _zz_138; - _zz_139[9] = _zz_138; - _zz_139[8] = _zz_138; - _zz_139[7] = _zz_138; - _zz_139[6] = _zz_138; - _zz_139[5] = _zz_138; - _zz_139[4] = _zz_138; - _zz_139[3] = _zz_138; - _zz_139[2] = _zz_138; - _zz_139[1] = _zz_138; - _zz_139[0] = _zz_138; - end - - always @ (*) begin + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JALR) ? execute_RS1 : execute_PC); + assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_140 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_140 = {_zz_137,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_140 = {{_zz_139,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_140; + assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; - always @ (*) begin - CsrPlugin_privilege = _zz_141; - if(CsrPlugin_forceMachineWire)begin + always @(*) begin + CsrPlugin_privilege = _zz_CsrPlugin_privilege; + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end @@ -4753,82 +4866,93 @@ module VexRiscv ( assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0; assign CsrPlugin_sip_SEIP_OR = (CsrPlugin_sip_SEIP_SOFT || CsrPlugin_sip_SEIP_INPUT); - always @ (*) begin + always @(*) begin CsrPlugin_redoInterface_valid = 1'b0; - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeInstruction)begin - CsrPlugin_redoInterface_valid = 1'b1; - end + if(CsrPlugin_rescheduleLogic_rescheduleNext) begin + CsrPlugin_redoInterface_valid = 1'b1; end end assign CsrPlugin_redoInterface_payload = decode_PC; - assign _zz_142 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); - assign _zz_143 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); - assign _zz_144 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); - assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); - always @ (*) begin + always @(*) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b0; + if(when_CsrPlugin_l803) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b1; + end + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeInstruction) begin + CsrPlugin_rescheduleLogic_rescheduleNext = 1'b1; + end + end + end + + assign when_CsrPlugin_l803 = (execute_arbitration_isValid && execute_IS_SFENCE_VMA); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_sip_STIP && CsrPlugin_sie_STIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_sip_SSIP && CsrPlugin_sie_SSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_sip_SEIP_OR && CsrPlugin_sie_SEIE); + assign _zz_when_CsrPlugin_l952_3 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_4 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_5 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; case(CsrPlugin_exceptionPortCtrl_exceptionContext_code) 4'b0000 : begin - if(((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)))begin + if(when_CsrPlugin_l866) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0001 : begin - if(((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_1) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0010 : begin - if(((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)))begin + if(when_CsrPlugin_l866_2) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0100 : begin - if(((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)))begin + if(when_CsrPlugin_l866_3) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0101 : begin - if(((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_4) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0110 : begin - if(((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)))begin + if(when_CsrPlugin_l866_5) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b0111 : begin - if(((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_6) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1000 : begin - if(((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)))begin + if(when_CsrPlugin_l866_7) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1001 : begin - if(((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)))begin + if(when_CsrPlugin_l866_8) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1100 : begin - if(((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_9) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1101 : begin - if(((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_10) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end 4'b1111 : begin - if(((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)))begin + if(when_CsrPlugin_l866_11) begin CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b01; end end @@ -4837,81 +4961,114 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l866 = ((1'b1 && CsrPlugin_medeleg_IAM) && (! 1'b0)); + assign when_CsrPlugin_l866_1 = ((1'b1 && CsrPlugin_medeleg_IAF) && (! 1'b0)); + assign when_CsrPlugin_l866_2 = ((1'b1 && CsrPlugin_medeleg_II) && (! 1'b0)); + assign when_CsrPlugin_l866_3 = ((1'b1 && CsrPlugin_medeleg_LAM) && (! 1'b0)); + assign when_CsrPlugin_l866_4 = ((1'b1 && CsrPlugin_medeleg_LAF) && (! 1'b0)); + assign when_CsrPlugin_l866_5 = ((1'b1 && CsrPlugin_medeleg_SAM) && (! 1'b0)); + assign when_CsrPlugin_l866_6 = ((1'b1 && CsrPlugin_medeleg_SAF) && (! 1'b0)); + assign when_CsrPlugin_l866_7 = ((1'b1 && CsrPlugin_medeleg_EU) && (! 1'b0)); + assign when_CsrPlugin_l866_8 = ((1'b1 && CsrPlugin_medeleg_ES) && (! 1'b0)); + assign when_CsrPlugin_l866_9 = ((1'b1 && CsrPlugin_medeleg_IPF) && (! 1'b0)); + assign when_CsrPlugin_l866_10 = ((1'b1 && CsrPlugin_medeleg_LPF) && (! 1'b0)); + assign when_CsrPlugin_l866_11 = ((1'b1 && CsrPlugin_medeleg_SPF) && (! 1'b0)); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_149 = _zz_366[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_263)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = ((CsrPlugin_sstatus_SIE && (CsrPlugin_privilege == 2'b01)) || (CsrPlugin_privilege < 2'b01)); + assign when_CsrPlugin_l946_1 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && (1'b1 && CsrPlugin_mideleg_ST)) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && (1'b1 && CsrPlugin_mideleg_SS)) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && (1'b1 && CsrPlugin_mideleg_SE)) && (! 1'b0)); + assign when_CsrPlugin_l952_3 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! (CsrPlugin_mideleg_ST != 1'b0))); + assign when_CsrPlugin_l952_4 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! (CsrPlugin_mideleg_SS != 1'b0))); + assign when_CsrPlugin_l952_5 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! (CsrPlugin_mideleg_SE != 1'b0))); + assign when_CsrPlugin_l952_6 = ((_zz_when_CsrPlugin_l952_3 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_7 = ((_zz_when_CsrPlugin_l952_4 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_8 = ((_zz_when_CsrPlugin_l952_5 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin @@ -4925,8 +5082,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_xtvec_base = CsrPlugin_stvec_base; @@ -4939,151 +5096,160 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_256)begin + if(execute_CsrPlugin_csr_256) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_384)begin + if(execute_CsrPlugin_csr_384) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_770)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_770) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_771)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_771) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_324)begin + if(execute_CsrPlugin_csr_324) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_260)begin + if(execute_CsrPlugin_csr_260) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_261)begin + if(execute_CsrPlugin_csr_261) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_321)begin + if(execute_CsrPlugin_csr_321) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_320)begin + if(execute_CsrPlugin_csr_320) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_322)begin + if(execute_CsrPlugin_csr_322) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_323)begin + if(execute_CsrPlugin_csr_323) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2496)begin + if(execute_CsrPlugin_csr_2496) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3520)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3520) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_281)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_282)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_283)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_282)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_283)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -5099,147 +5265,229 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_281)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_281)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - always @ (*) begin - execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - if(execute_CsrPlugin_csr_836)begin + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + always @(*) begin + execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; end - if(execute_CsrPlugin_csr_324)begin + if(execute_CsrPlugin_csr_324) begin execute_CsrPlugin_readToWriteData[9 : 9] = CsrPlugin_sip_SEIP_SOFT; end end - always @ (*) begin - case(_zz_309) + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || execute_IS_SFENCE_VMA)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign memory_MulDivIterativePlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_257)begin - if(_zz_265)begin + if(when_MulDivIterativePlugin_l96) begin + if(when_MulDivIterativePlugin_l100) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l110) begin memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; end end assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); - always @ (*) begin - if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin + always @(*) begin + if(memory_MulDivIterativePlugin_mul_counter_willOverflow) begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_369); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_memory_MulDivIterativePlugin_mul_counter_valueNext); end - if(memory_MulDivIterativePlugin_mul_counter_willClear)begin + if(memory_MulDivIterativePlugin_mul_counter_willClear) begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end end - always @ (*) begin + assign when_MulDivIterativePlugin_l96 = (memory_arbitration_isValid && memory_IS_MUL); + assign when_MulDivIterativePlugin_l97 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign when_MulDivIterativePlugin_l100 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign when_MulDivIterativePlugin_l110 = (! memory_arbitration_isStuck); + always @(*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_258)begin - if(_zz_284)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_285)begin + if(when_MulDivIterativePlugin_l162) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_377); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); end - if(memory_MulDivIterativePlugin_div_counter_willClear)begin + if(memory_MulDivIterativePlugin_div_counter_willClear) begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end end - assign _zz_150 = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_150[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_378); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_379 : _zz_380); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_381[31:0]; - assign _zz_151 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_152 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_153 = ((execute_IS_MUL && _zz_152) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_154[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_154[31 : 0] = execute_RS1; - end - - assign _zz_156 = (_zz_155 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_156 != 32'h0); - assign _zz_158 = (_zz_157 & externalInterruptArray_regNext); - assign externalInterruptS = (_zz_158 != 32'h0); - assign _zz_27 = decode_SRC1_CTRL; - assign _zz_25 = _zz_50; - assign _zz_38 = decode_to_execute_SRC1_CTRL; - assign _zz_24 = decode_ALU_CTRL; - assign _zz_22 = _zz_49; - assign _zz_39 = decode_to_execute_ALU_CTRL; - assign _zz_21 = decode_SRC2_CTRL; - assign _zz_19 = _zz_48; - assign _zz_37 = decode_to_execute_SRC2_CTRL; - assign _zz_18 = decode_ALU_BITWISE_CTRL; - assign _zz_16 = _zz_47; - assign _zz_40 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_15 = decode_SHIFT_CTRL; - assign _zz_12 = execute_SHIFT_CTRL; - assign _zz_13 = _zz_46; - assign _zz_35 = decode_to_execute_SHIFT_CTRL; - assign _zz_34 = execute_to_memory_SHIFT_CTRL; - assign _zz_10 = decode_BRANCH_CTRL; - assign _zz_8 = _zz_45; - assign _zz_31 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_44; - assign _zz_29 = decode_to_execute_ENV_CTRL; - assign _zz_28 = execute_to_memory_ENV_CTRL; - assign _zz_30 = memory_to_writeBack_ENV_CTRL; + assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_MulDivIterativePlugin_rs1 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_MulDivIterativePlugin_rs1_1 = ((execute_IS_MUL && _zz_memory_MulDivIterativePlugin_rs1) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_MulDivIterativePlugin_rs1_2[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_MulDivIterativePlugin_rs1_2[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign _zz_CsrPlugin_csrMapping_readDataInit_3 = (_zz_CsrPlugin_csrMapping_readDataInit_2 & externalInterruptArray_regNext); + assign externalInterruptS = (_zz_CsrPlugin_csrMapping_readDataInit_3 != 32'h0); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_28 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_36 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_38 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_41 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -5260,269 +5508,306 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_159 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_159[12 : 0] = 13'h1000; - _zz_159[25 : 20] = 6'h20; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_4[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_160 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_160[19 : 19] = MmuPlugin_status_mxr; - _zz_160[18 : 18] = MmuPlugin_status_sum; - _zz_160[17 : 17] = MmuPlugin_status_mprv; - _zz_160[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_160[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_160[3 : 3] = CsrPlugin_mstatus_MIE; - _zz_160[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_160[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_160[1 : 1] = CsrPlugin_sstatus_SIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[19 : 19] = MmuPlugin_status_mxr; + _zz_CsrPlugin_csrMapping_readDataInit_5[18 : 18] = MmuPlugin_status_sum; + _zz_CsrPlugin_csrMapping_readDataInit_5[17 : 17] = MmuPlugin_status_mprv; + _zz_CsrPlugin_csrMapping_readDataInit_5[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_5[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_CsrPlugin_csrMapping_readDataInit_5[1 : 1] = CsrPlugin_sstatus_SIE; end end - always @ (*) begin - _zz_161 = 32'h0; - if(execute_CsrPlugin_csr_256)begin - _zz_161[19 : 19] = MmuPlugin_status_mxr; - _zz_161[18 : 18] = MmuPlugin_status_sum; - _zz_161[17 : 17] = MmuPlugin_status_mprv; - _zz_161[8 : 8] = CsrPlugin_sstatus_SPP; - _zz_161[5 : 5] = CsrPlugin_sstatus_SPIE; - _zz_161[1 : 1] = CsrPlugin_sstatus_SIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_256) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[19 : 19] = MmuPlugin_status_mxr; + _zz_CsrPlugin_csrMapping_readDataInit_6[18 : 18] = MmuPlugin_status_sum; + _zz_CsrPlugin_csrMapping_readDataInit_6[17 : 17] = MmuPlugin_status_mprv; + _zz_CsrPlugin_csrMapping_readDataInit_6[8 : 8] = CsrPlugin_sstatus_SPP; + _zz_CsrPlugin_csrMapping_readDataInit_6[5 : 5] = CsrPlugin_sstatus_SPIE; + _zz_CsrPlugin_csrMapping_readDataInit_6[1 : 1] = CsrPlugin_sstatus_SIE; end end - always @ (*) begin - _zz_162 = 32'h0; - if(execute_CsrPlugin_csr_384)begin - _zz_162[31 : 31] = MmuPlugin_satp_mode; - _zz_162[30 : 22] = MmuPlugin_satp_asid; - _zz_162[19 : 0] = MmuPlugin_satp_ppn; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_384) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 31] = MmuPlugin_satp_mode; + _zz_CsrPlugin_csrMapping_readDataInit_7[30 : 22] = MmuPlugin_satp_asid; + _zz_CsrPlugin_csrMapping_readDataInit_7[19 : 0] = MmuPlugin_satp_ppn; end end - always @ (*) begin - _zz_163 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_163[0 : 0] = 1'b1; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[0 : 0] = 1'b1; end end - always @ (*) begin - _zz_164 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_164[1 : 0] = 2'b10; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[1 : 0] = 2'b10; end end - always @ (*) begin - _zz_165 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_165[1 : 0] = 2'b11; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = 2'b11; end end - always @ (*) begin - _zz_166 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_166[11 : 11] = CsrPlugin_mip_MEIP; - _zz_166[7 : 7] = CsrPlugin_mip_MTIP; - _zz_166[3 : 3] = CsrPlugin_mip_MSIP; - _zz_166[5 : 5] = CsrPlugin_sip_STIP; - _zz_166[1 : 1] = CsrPlugin_sip_SSIP; - _zz_166[9 : 9] = CsrPlugin_sip_SEIP_OR; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 3] = CsrPlugin_mip_MSIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[5 : 5] = CsrPlugin_sip_STIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[1 : 1] = CsrPlugin_sip_SSIP; + _zz_CsrPlugin_csrMapping_readDataInit_11[9 : 9] = CsrPlugin_sip_SEIP_OR; end end - always @ (*) begin - _zz_167 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_167[11 : 11] = CsrPlugin_mie_MEIE; - _zz_167[7 : 7] = CsrPlugin_mie_MTIE; - _zz_167[3 : 3] = CsrPlugin_mie_MSIE; - _zz_167[9 : 9] = CsrPlugin_sie_SEIE; - _zz_167[5 : 5] = CsrPlugin_sie_STIE; - _zz_167[1 : 1] = CsrPlugin_sie_SSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[3 : 3] = CsrPlugin_mie_MSIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[9 : 9] = CsrPlugin_sie_SEIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[5 : 5] = CsrPlugin_sie_STIE; + _zz_CsrPlugin_csrMapping_readDataInit_12[1 : 1] = CsrPlugin_sie_SSIE; end end - always @ (*) begin - _zz_168 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_168[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_169 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_169[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_170 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_170[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_170[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_171 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_171[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_172 = 32'h0; - if(execute_CsrPlugin_csr_324)begin - _zz_172[5 : 5] = CsrPlugin_sip_STIP; - _zz_172[1 : 1] = CsrPlugin_sip_SSIP; - _zz_172[9 : 9] = CsrPlugin_sip_SEIP_OR; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_324) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[5 : 5] = CsrPlugin_sip_STIP; + _zz_CsrPlugin_csrMapping_readDataInit_17[1 : 1] = CsrPlugin_sip_SSIP; + _zz_CsrPlugin_csrMapping_readDataInit_17[9 : 9] = CsrPlugin_sip_SEIP_OR; end end - always @ (*) begin - _zz_173 = 32'h0; - if(execute_CsrPlugin_csr_260)begin - _zz_173[9 : 9] = CsrPlugin_sie_SEIE; - _zz_173[5 : 5] = CsrPlugin_sie_STIE; - _zz_173[1 : 1] = CsrPlugin_sie_SSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_260) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[9 : 9] = CsrPlugin_sie_SEIE; + _zz_CsrPlugin_csrMapping_readDataInit_18[5 : 5] = CsrPlugin_sie_STIE; + _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 1] = CsrPlugin_sie_SSIE; end end - always @ (*) begin - _zz_174 = 32'h0; - if(execute_CsrPlugin_csr_261)begin - _zz_174[31 : 2] = CsrPlugin_stvec_base; - _zz_174[1 : 0] = CsrPlugin_stvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_261) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 2] = CsrPlugin_stvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_19[1 : 0] = CsrPlugin_stvec_mode; end end - always @ (*) begin - _zz_175 = 32'h0; - if(execute_CsrPlugin_csr_321)begin - _zz_175[31 : 0] = CsrPlugin_sepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_321) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_sepc; end end - always @ (*) begin - _zz_176 = 32'h0; - if(execute_CsrPlugin_csr_320)begin - _zz_176[31 : 0] = CsrPlugin_sscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_320) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_sscratch; end end - always @ (*) begin - _zz_177 = 32'h0; - if(execute_CsrPlugin_csr_322)begin - _zz_177[31 : 31] = CsrPlugin_scause_interrupt; - _zz_177[3 : 0] = CsrPlugin_scause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_322) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 31] = CsrPlugin_scause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_22[3 : 0] = CsrPlugin_scause_exceptionCode; end end - always @ (*) begin - _zz_178 = 32'h0; - if(execute_CsrPlugin_csr_323)begin - _zz_178[31 : 0] = CsrPlugin_stval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_323) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_stval; end end - always @ (*) begin - _zz_179 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_179[31 : 0] = _zz_155; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_180[31 : 0] = _zz_156; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_2496)begin - _zz_181[31 : 0] = _zz_157; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + if(execute_CsrPlugin_csr_2496) begin + _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_3520)begin - _zz_182[31 : 0] = _zz_158; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + if(execute_CsrPlugin_csr_3520) begin + _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; end end - assign execute_CsrPlugin_readData = (((((_zz_159 | _zz_160) | (_zz_161 | _zz_162)) | ((_zz_163 | _zz_164) | (_zz_165 | _zz_653))) | (((_zz_166 | _zz_167) | (_zz_168 | _zz_169)) | ((_zz_170 | _zz_171) | (_zz_172 | _zz_173)))) | ((((_zz_174 | _zz_175) | (_zz_176 | _zz_177)) | ((_zz_178 | _zz_179) | (_zz_180 | _zz_181))) | _zz_182)); - assign iBusWishbone_ADR = {_zz_436,_zz_183}; - assign iBusWishbone_CTI = ((_zz_183 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5) | (_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7)) | ((_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9) | (_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_28))) | (((_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12) | (_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14)) | ((_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16) | (_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20) | (_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22)) | ((_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24) | (_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26))) | _zz_CsrPlugin_csrMapping_readDataInit_27)); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_286)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_286)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_184; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_190 = (dBus_cmd_payload_length != 3'b000); - assign _zz_186 = dBus_cmd_valid; - assign _zz_188 = dBus_cmd_payload_wr; - assign _zz_189 = (_zz_185 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_187 && (_zz_188 || _zz_189)); - assign dBusWishbone_ADR = ((_zz_190 ? {{dBus_cmd_payload_address[31 : 5],_zz_185},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_190 ? (_zz_189 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_188 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_188; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_187 = (_zz_186 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_186; - assign dBusWishbone_STB = _zz_186; - assign dBus_rsp_valid = _zz_191; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_66 <= 1'b0; - _zz_68 <= 1'b0; - _zz_71 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_73; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_74; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; MmuPlugin_status_sum <= 1'b0; MmuPlugin_status_mxr <= 1'b0; @@ -5538,11 +5823,11 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; MmuPlugin_ports_1_entryToReplace_value <= 2'b00; - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_IDLE; MmuPlugin_shared_dBusRspStaged_valid <= 1'b0; - _zz_110 <= 1'b1; - _zz_122 <= 1'b0; - _zz_141 <= 2'b11; + _zz_2 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + _zz_CsrPlugin_privilege <= 2'b11; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -5586,219 +5871,219 @@ module VexRiscv ( execute_CsrPlugin_wfiWake <= 1'b0; memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - _zz_155 <= 32'h0; - _zz_157 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_2 <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_IS_DBUS_SHARING <= 1'b0; memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; - _zz_183 <= 3'b000; - _zz_184 <= 1'b0; - _zz_185 <= 3'b000; - _zz_191 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_66 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_64)begin - _zz_66 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_68 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_68 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_71 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_2_output_ready)begin - _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_2_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_2_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_2_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_3_input_ready)))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_5) begin IBusCachedPlugin_injector_nextPcCalc_valids_5 <= IBusCachedPlugin_injector_nextPcCalc_valids_4; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_5 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_287)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end MmuPlugin_ports_0_entryToReplace_value <= MmuPlugin_ports_0_entryToReplace_valueNext; - if(contextSwitching)begin - if(MmuPlugin_ports_0_cache_0_exception)begin + if(contextSwitching) begin + if(MmuPlugin_ports_0_cache_0_exception) begin MmuPlugin_ports_0_cache_0_valid <= 1'b0; end - if(MmuPlugin_ports_0_cache_1_exception)begin + if(MmuPlugin_ports_0_cache_1_exception) begin MmuPlugin_ports_0_cache_1_valid <= 1'b0; end - if(MmuPlugin_ports_0_cache_2_exception)begin + if(MmuPlugin_ports_0_cache_2_exception) begin MmuPlugin_ports_0_cache_2_valid <= 1'b0; end - if(MmuPlugin_ports_0_cache_3_exception)begin + if(MmuPlugin_ports_0_cache_3_exception) begin MmuPlugin_ports_0_cache_3_valid <= 1'b0; end end MmuPlugin_ports_1_entryToReplace_value <= MmuPlugin_ports_1_entryToReplace_valueNext; - if(contextSwitching)begin - if(MmuPlugin_ports_1_cache_0_exception)begin + if(contextSwitching) begin + if(MmuPlugin_ports_1_cache_0_exception) begin MmuPlugin_ports_1_cache_0_valid <= 1'b0; end - if(MmuPlugin_ports_1_cache_1_exception)begin + if(MmuPlugin_ports_1_cache_1_exception) begin MmuPlugin_ports_1_cache_1_valid <= 1'b0; end - if(MmuPlugin_ports_1_cache_2_exception)begin + if(MmuPlugin_ports_1_cache_2_exception) begin MmuPlugin_ports_1_cache_2_valid <= 1'b0; end - if(MmuPlugin_ports_1_cache_3_exception)begin + if(MmuPlugin_ports_1_cache_3_exception) begin MmuPlugin_ports_1_cache_3_valid <= 1'b0; end end MmuPlugin_shared_dBusRspStaged_valid <= MmuPlugin_dBusAccess_rsp_valid; case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_288)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + `MmuPlugin_shared_State_binary_sequential_IDLE : begin + if(when_MmuPlugin_l217) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L1_CMD; end end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin - if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_RSP; + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L1_RSP; end end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin - if(MmuPlugin_shared_dBusRspStaged_valid)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; - if((MmuPlugin_shared_dBusRsp_leaf || MmuPlugin_shared_dBusRsp_exception))begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin + if(MmuPlugin_shared_dBusRspStaged_valid) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L0_CMD; + if(when_MmuPlugin_l243) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_IDLE; end - if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L1_CMD; + if(MmuPlugin_shared_dBusRspStaged_payload_redo) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L1_CMD; end end end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin - if(MmuPlugin_dBusAccess_cmd_ready)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_RSP; + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin + if(MmuPlugin_dBusAccess_cmd_ready) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L0_RSP; end end default : begin - if(MmuPlugin_shared_dBusRspStaged_valid)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_IDLE; - if(MmuPlugin_shared_dBusRspStaged_payload_redo)begin - MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_defaultEncoding_L0_CMD; + if(MmuPlugin_shared_dBusRspStaged_valid) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_IDLE; + if(MmuPlugin_shared_dBusRspStaged_payload_redo) begin + MmuPlugin_shared_state_1 <= `MmuPlugin_shared_State_binary_sequential_L0_CMD; end end end endcase - if(_zz_272)begin - if(_zz_273)begin - if(_zz_289)begin + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin + if(when_MmuPlugin_l280) begin MmuPlugin_ports_0_cache_0_valid <= 1'b1; end - if(_zz_290)begin + if(when_MmuPlugin_l280_1) begin MmuPlugin_ports_0_cache_1_valid <= 1'b1; end - if(_zz_291)begin + if(when_MmuPlugin_l280_2) begin MmuPlugin_ports_0_cache_2_valid <= 1'b1; end - if(_zz_292)begin + if(when_MmuPlugin_l280_3) begin MmuPlugin_ports_0_cache_3_valid <= 1'b1; end end - if(_zz_274)begin - if(_zz_293)begin + if(when_MmuPlugin_l274_1) begin + if(when_MmuPlugin_l280_4) begin MmuPlugin_ports_1_cache_0_valid <= 1'b1; end - if(_zz_294)begin + if(when_MmuPlugin_l280_5) begin MmuPlugin_ports_1_cache_1_valid <= 1'b1; end - if(_zz_295)begin + if(when_MmuPlugin_l280_6) begin MmuPlugin_ports_1_cache_2_valid <= 1'b1; end - if(_zz_296)begin + if(when_MmuPlugin_l280_7) begin MmuPlugin_ports_1_cache_3_valid <= 1'b1; end end end - if((writeBack_arbitration_isValid && writeBack_IS_SFENCE_VMA))begin + if(when_MmuPlugin_l304) begin MmuPlugin_ports_0_cache_0_valid <= 1'b0; MmuPlugin_ports_0_cache_1_valid <= 1'b0; MmuPlugin_ports_0_cache_2_valid <= 1'b0; @@ -5808,83 +6093,83 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - _zz_110 <= 1'b0; - _zz_122 <= (_zz_42 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_2 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_297)begin - if(_zz_298)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_299)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_300)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(_zz_301)begin - if(_zz_302)begin + if(when_CsrPlugin_l946_1) begin + if(when_CsrPlugin_l952_3) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_303)begin + if(when_CsrPlugin_l952_4) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_304)begin + if(when_CsrPlugin_l952_5) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_305)begin + if(when_CsrPlugin_l952_6) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_306)begin + if(when_CsrPlugin_l952_7) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_307)begin + if(when_CsrPlugin_l952_8) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_266)begin - _zz_141 <= CsrPlugin_targetPrivilege; + if(when_CsrPlugin_l1019) begin + _zz_CsrPlugin_privilege <= CsrPlugin_targetPrivilege; case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_sstatus_SIE <= 1'b0; @@ -5900,79 +6185,83 @@ module VexRiscv ( end endcase end - if(_zz_267)begin - case(_zz_268) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; CsrPlugin_mstatus_MPIE <= 1'b1; - _zz_141 <= CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_privilege <= CsrPlugin_mstatus_MPP; end 2'b01 : begin CsrPlugin_sstatus_SPP <= 1'b0; CsrPlugin_sstatus_SIE <= CsrPlugin_sstatus_SPIE; CsrPlugin_sstatus_SPIE <= 1'b1; - _zz_141 <= {1'b0,CsrPlugin_sstatus_SPP}; + _zz_CsrPlugin_privilege <= {1'b0,CsrPlugin_sstatus_SPP}; end default : begin end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,{_zz_145,{_zz_144,{_zz_143,_zz_142}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_5,{_zz_when_CsrPlugin_l952_4,{_zz_when_CsrPlugin_l952_3,{_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}}}}} != 6'h0) || CsrPlugin_thirdPartyWake); memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin execute_to_memory_IS_DBUS_SHARING <= execute_IS_DBUS_SHARING; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin memory_to_writeBack_IS_DBUS_SHARING <= memory_IS_DBUS_SHARING; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(MmuPlugin_dBusAccess_rsp_valid)begin + if(MmuPlugin_dBusAccess_rsp_valid) begin memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_391[0]; - MmuPlugin_status_sum <= _zz_392[0]; - MmuPlugin_status_mprv <= _zz_393[0]; - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_394[0]; - CsrPlugin_mstatus_MIE <= _zz_395[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_396[0]; - CsrPlugin_sstatus_SIE <= _zz_397[0]; + if(MmuPlugin_dBusAccess_rsp_valid) begin + memory_to_writeBack_IS_DBUS_SHARING <= 1'b0; + end + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_status_mxr <= CsrPlugin_csrMapping_writeDataSignal[19]; + MmuPlugin_status_sum <= CsrPlugin_csrMapping_writeDataSignal[18]; + MmuPlugin_status_mprv <= CsrPlugin_csrMapping_writeDataSignal[17]; + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + CsrPlugin_sstatus_SPP <= CsrPlugin_csrMapping_writeDataSignal[8 : 8]; + CsrPlugin_sstatus_SPIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sstatus_SIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_256)begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_status_mxr <= _zz_398[0]; - MmuPlugin_status_sum <= _zz_399[0]; - MmuPlugin_status_mprv <= _zz_400[0]; - CsrPlugin_sstatus_SPP <= execute_CsrPlugin_writeData[8 : 8]; - CsrPlugin_sstatus_SPIE <= _zz_401[0]; - CsrPlugin_sstatus_SIE <= _zz_402[0]; + if(execute_CsrPlugin_csr_256) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_status_mxr <= CsrPlugin_csrMapping_writeDataSignal[19]; + MmuPlugin_status_sum <= CsrPlugin_csrMapping_writeDataSignal[18]; + MmuPlugin_status_mprv <= CsrPlugin_csrMapping_writeDataSignal[17]; + CsrPlugin_sstatus_SPP <= CsrPlugin_csrMapping_writeDataSignal[8 : 8]; + CsrPlugin_sstatus_SPIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sstatus_SIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeInstruction)begin + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_satp_mode <= CsrPlugin_csrMapping_writeDataSignal[31]; MmuPlugin_ports_0_cache_0_valid <= 1'b0; MmuPlugin_ports_0_cache_1_valid <= 1'b0; MmuPlugin_ports_0_cache_2_valid <= 1'b0; @@ -5982,125 +6271,122 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_valid <= 1'b0; MmuPlugin_ports_1_cache_3_valid <= 1'b0; end - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_mode <= _zz_403[0]; - end end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_405[0]; - CsrPlugin_sip_SSIP <= _zz_406[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_407[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sip_STIP <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sip_SSIP <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_sip_SEIP_SOFT <= CsrPlugin_csrMapping_writeDataSignal[9]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_408[0]; - CsrPlugin_mie_MTIE <= _zz_409[0]; - CsrPlugin_mie_MSIE <= _zz_410[0]; - CsrPlugin_sie_SEIE <= _zz_411[0]; - CsrPlugin_sie_STIE <= _zz_412[0]; - CsrPlugin_sie_SSIE <= _zz_413[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + CsrPlugin_sie_SEIE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_sie_STIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sie_SSIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_770)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_medeleg_IAM <= _zz_414[0]; - CsrPlugin_medeleg_IAF <= _zz_415[0]; - CsrPlugin_medeleg_II <= _zz_416[0]; - CsrPlugin_medeleg_LAM <= _zz_417[0]; - CsrPlugin_medeleg_LAF <= _zz_418[0]; - CsrPlugin_medeleg_SAM <= _zz_419[0]; - CsrPlugin_medeleg_SAF <= _zz_420[0]; - CsrPlugin_medeleg_EU <= _zz_421[0]; - CsrPlugin_medeleg_ES <= _zz_422[0]; - CsrPlugin_medeleg_IPF <= _zz_423[0]; - CsrPlugin_medeleg_LPF <= _zz_424[0]; - CsrPlugin_medeleg_SPF <= _zz_425[0]; + if(execute_CsrPlugin_csr_770) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_medeleg_IAM <= CsrPlugin_csrMapping_writeDataSignal[0]; + CsrPlugin_medeleg_IAF <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_medeleg_II <= CsrPlugin_csrMapping_writeDataSignal[2]; + CsrPlugin_medeleg_LAM <= CsrPlugin_csrMapping_writeDataSignal[4]; + CsrPlugin_medeleg_LAF <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_medeleg_SAM <= CsrPlugin_csrMapping_writeDataSignal[6]; + CsrPlugin_medeleg_SAF <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_medeleg_EU <= CsrPlugin_csrMapping_writeDataSignal[8]; + CsrPlugin_medeleg_ES <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_medeleg_IPF <= CsrPlugin_csrMapping_writeDataSignal[12]; + CsrPlugin_medeleg_LPF <= CsrPlugin_csrMapping_writeDataSignal[13]; + CsrPlugin_medeleg_SPF <= CsrPlugin_csrMapping_writeDataSignal[15]; end end - if(execute_CsrPlugin_csr_771)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mideleg_SE <= _zz_426[0]; - CsrPlugin_mideleg_ST <= _zz_427[0]; - CsrPlugin_mideleg_SS <= _zz_428[0]; + if(execute_CsrPlugin_csr_771) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mideleg_SE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_mideleg_ST <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_mideleg_SS <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_324)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sip_STIP <= _zz_429[0]; - CsrPlugin_sip_SSIP <= _zz_430[0]; - CsrPlugin_sip_SEIP_SOFT <= _zz_431[0]; + if(execute_CsrPlugin_csr_324) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sip_STIP <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sip_SSIP <= CsrPlugin_csrMapping_writeDataSignal[1]; + CsrPlugin_sip_SEIP_SOFT <= CsrPlugin_csrMapping_writeDataSignal[9]; end end - if(execute_CsrPlugin_csr_260)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sie_SEIE <= _zz_432[0]; - CsrPlugin_sie_STIE <= _zz_433[0]; - CsrPlugin_sie_SSIE <= _zz_434[0]; + if(execute_CsrPlugin_csr_260) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sie_SEIE <= CsrPlugin_csrMapping_writeDataSignal[9]; + CsrPlugin_sie_STIE <= CsrPlugin_csrMapping_writeDataSignal[5]; + CsrPlugin_sie_SSIE <= CsrPlugin_csrMapping_writeDataSignal[1]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2496)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2496) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_286)begin - if(iBusWishbone_ACK)begin - _zz_183 <= (_zz_183 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_184 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_186 && _zz_187))begin - _zz_185 <= (_zz_185 + 3'b001); - if(_zz_189)begin - _zz_185 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_191 <= ((_zz_186 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_69 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_2_output_ready)begin - _zz_72 <= IBusCachedPlugin_iBusRsp_stages_2_output_payload; + if(IBusCachedPlugin_iBusRsp_stages_2_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_2_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_2_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_3_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_3_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_287)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; end MmuPlugin_shared_dBusRspStaged_payload_data <= MmuPlugin_dBusAccess_rsp_payload_data; MmuPlugin_shared_dBusRspStaged_payload_error <= MmuPlugin_dBusAccess_rsp_payload_error; MmuPlugin_shared_dBusRspStaged_payload_redo <= MmuPlugin_dBusAccess_rsp_payload_redo; - if((MmuPlugin_shared_dBusRspStaged_valid && (! MmuPlugin_shared_dBusRspStaged_payload_redo)))begin + if(when_MmuPlugin_l205) begin MmuPlugin_shared_pteBuffer_V <= MmuPlugin_shared_dBusRsp_pte_V; MmuPlugin_shared_pteBuffer_R <= MmuPlugin_shared_dBusRsp_pte_R; MmuPlugin_shared_pteBuffer_W <= MmuPlugin_shared_dBusRsp_pte_W; @@ -6114,26 +6400,26 @@ module VexRiscv ( MmuPlugin_shared_pteBuffer_PPN1 <= MmuPlugin_shared_dBusRsp_pte_PPN1; end case(MmuPlugin_shared_state_1) - `MmuPlugin_shared_State_defaultEncoding_IDLE : begin - if(_zz_288)begin + `MmuPlugin_shared_State_binary_sequential_IDLE : begin + if(when_MmuPlugin_l217) begin MmuPlugin_shared_portSortedOh <= MmuPlugin_shared_refills; - MmuPlugin_shared_vpn_1 <= _zz_93[31 : 22]; - MmuPlugin_shared_vpn_0 <= _zz_93[21 : 12]; + MmuPlugin_shared_vpn_1 <= _zz_MmuPlugin_shared_vpn_0[31 : 22]; + MmuPlugin_shared_vpn_0 <= _zz_MmuPlugin_shared_vpn_0[21 : 12]; end end - `MmuPlugin_shared_State_defaultEncoding_L1_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L1_CMD : begin end - `MmuPlugin_shared_State_defaultEncoding_L1_RSP : begin + `MmuPlugin_shared_State_binary_sequential_L1_RSP : begin end - `MmuPlugin_shared_State_defaultEncoding_L0_CMD : begin + `MmuPlugin_shared_State_binary_sequential_L0_CMD : begin end default : begin end endcase - if(_zz_272)begin - if(_zz_273)begin - if(_zz_289)begin - MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l272) begin + if(when_MmuPlugin_l274) begin + if(when_MmuPlugin_l280) begin + MmuPlugin_ports_0_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6142,10 +6428,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_290)begin - MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_1) begin + MmuPlugin_ports_0_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6154,10 +6440,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_291)begin - MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_2) begin + MmuPlugin_ports_0_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6166,10 +6452,10 @@ module VexRiscv ( MmuPlugin_ports_0_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_292)begin - MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_3) begin + MmuPlugin_ports_0_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_0_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_0_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_0_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6178,12 +6464,12 @@ module VexRiscv ( MmuPlugin_ports_0_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_0_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_0_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_0_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end end - if(_zz_274)begin - if(_zz_293)begin - MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l274_1) begin + if(when_MmuPlugin_l280_4) begin + MmuPlugin_ports_1_cache_0_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_0_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_0_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_0_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6192,10 +6478,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_0_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_0_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_0_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_0_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_294)begin - MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_5) begin + MmuPlugin_ports_1_cache_1_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_1_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_1_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_1_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6204,10 +6490,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_1_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_1_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_1_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_1_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_295)begin - MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_6) begin + MmuPlugin_ports_1_cache_2_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_2_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_2_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_2_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6216,10 +6502,10 @@ module VexRiscv ( MmuPlugin_ports_1_cache_2_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_2_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_2_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_2_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end - if(_zz_296)begin - MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); + if(when_MmuPlugin_l280_7) begin + MmuPlugin_ports_1_cache_3_exception <= (MmuPlugin_shared_dBusRsp_exception || ((MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP) && (MmuPlugin_shared_dBusRsp_pte_PPN0 != 10'h0))); MmuPlugin_ports_1_cache_3_virtualAddress_0 <= MmuPlugin_shared_vpn_0; MmuPlugin_ports_1_cache_3_virtualAddress_1 <= MmuPlugin_shared_vpn_1; MmuPlugin_ports_1_cache_3_physicalAddress_0 <= MmuPlugin_shared_dBusRsp_pte_PPN0; @@ -6228,83 +6514,83 @@ module VexRiscv ( MmuPlugin_ports_1_cache_3_allowWrite <= MmuPlugin_shared_dBusRsp_pte_W; MmuPlugin_ports_1_cache_3_allowExecute <= MmuPlugin_shared_dBusRsp_pte_X; MmuPlugin_ports_1_cache_3_allowUser <= MmuPlugin_shared_dBusRsp_pte_U; - MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_defaultEncoding_L1_RSP); + MmuPlugin_ports_1_cache_3_superPage <= (MmuPlugin_shared_state_1 == `MmuPlugin_shared_State_binary_sequential_L1_RSP); end end end - _zz_123 <= _zz_41[11 : 7]; - _zz_124 <= _zz_51; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_sip_SEIP_INPUT <= externalInterruptS; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_263)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(BranchPlugin_branchExceptionPort_valid)begin + if(BranchPlugin_branchExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_297)begin - if(_zz_298)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_299)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end - if(_zz_300)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b01; end end - if(_zz_301)begin - if(_zz_302)begin + if(when_CsrPlugin_l946_1) begin + if(when_CsrPlugin_l952_3) begin CsrPlugin_interrupt_code <= 4'b0101; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_303)begin + if(when_CsrPlugin_l952_4) begin CsrPlugin_interrupt_code <= 4'b0001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_304)begin + if(when_CsrPlugin_l952_5) begin CsrPlugin_interrupt_code <= 4'b1001; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_305)begin + if(when_CsrPlugin_l952_6) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_306)begin + if(when_CsrPlugin_l952_7) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_307)begin + if(when_CsrPlugin_l952_8) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b01 : begin CsrPlugin_scause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_scause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_sepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_stval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -6312,7 +6598,7 @@ module VexRiscv ( CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -6320,347 +6606,350 @@ module VexRiscv ( end endcase end - if(_zz_257)begin - if(_zz_265)begin + if(when_MulDivIterativePlugin_l96) begin + if(when_MulDivIterativePlugin_l100) begin memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_370,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_memory_MulDivIterativePlugin_accumulator,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end - if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_MulDivIterativePlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_MulDivIterativePlugin_div_done <= 1'b0; end - if(_zz_258)begin - if(_zz_284)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; - if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_result <= _zz_382[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; end end end - if(_zz_285)begin + if(when_MulDivIterativePlugin_l162) begin memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_153 ? (~ _zz_154) : _zz_154) + _zz_388); - memory_MulDivIterativePlugin_rs2 <= ((_zz_152 ? (~ execute_RS2) : execute_RS2) + _zz_390); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_153 ^ (_zz_152 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1_1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_2) : _zz_memory_MulDivIterativePlugin_rs1_2) + _zz_memory_MulDivIterativePlugin_rs1_3); + memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1_1 ^ (_zz_memory_MulDivIterativePlugin_rs1 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_36; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_6) begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_53; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_54; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_26; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_23; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_20; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_LRSC <= decode_MEMORY_LRSC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin + execute_to_memory_MEMORY_LRSC <= execute_MEMORY_LRSC; + end + if(when_Pipeline_l124_28) begin + memory_to_writeBack_MEMORY_LRSC <= memory_MEMORY_LRSC; + end + if(when_Pipeline_l124_29) begin decode_to_execute_MEMORY_AMO <= decode_MEMORY_AMO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_30) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; + if(when_Pipeline_l124_31) begin + decode_to_execute_IS_SFENCE_VMA2 <= decode_IS_SFENCE_VMA2; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_IS_SFENCE_VMA <= execute_IS_SFENCE_VMA; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_IS_SFENCE_VMA <= memory_IS_SFENCE_VMA; + if(when_Pipeline_l124_32) begin + decode_to_execute_IS_SFENCE_VMA <= decode_IS_SFENCE_VMA; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_33) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_17; + if(when_Pipeline_l124_34) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_14; + if(when_Pipeline_l124_35) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_11; + if(when_Pipeline_l124_36) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_9; + if(when_Pipeline_l124_37) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_39) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_40) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_41) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_52) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_53) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_54) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_32; + if(when_Pipeline_l124_57) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_33; + if(when_Pipeline_l124_58) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_256 <= (decode_INSTRUCTION[31 : 20] == 12'h100); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_384 <= (decode_INSTRUCTION[31 : 20] == 12'h180); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_770 <= (decode_INSTRUCTION[31 : 20] == 12'h302); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_771 <= (decode_INSTRUCTION[31 : 20] == 12'h303); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_324 <= (decode_INSTRUCTION[31 : 20] == 12'h144); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_260 <= (decode_INSTRUCTION[31 : 20] == 12'h104); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_261 <= (decode_INSTRUCTION[31 : 20] == 12'h105); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_321 <= (decode_INSTRUCTION[31 : 20] == 12'h141); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_320 <= (decode_INSTRUCTION[31 : 20] == 12'h140); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin execute_CsrPlugin_csr_322 <= (decode_INSTRUCTION[31 : 20] == 12'h142); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_323 <= (decode_INSTRUCTION[31 : 20] == 12'h143); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_24) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_25) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_26) begin execute_CsrPlugin_csr_2496 <= (decode_INSTRUCTION[31 : 20] == 12'h9c0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_27) begin execute_CsrPlugin_csr_3520 <= (decode_INSTRUCTION[31 : 20] == 12'hdc0); end - if(execute_CsrPlugin_csr_384)begin - if(execute_CsrPlugin_writeEnable)begin - MmuPlugin_satp_asid <= execute_CsrPlugin_writeData[30 : 22]; - MmuPlugin_satp_ppn <= execute_CsrPlugin_writeData[19 : 0]; + if(execute_CsrPlugin_csr_384) begin + if(execute_CsrPlugin_writeEnable) begin + MmuPlugin_satp_asid <= CsrPlugin_csrMapping_writeDataSignal[30 : 22]; + MmuPlugin_satp_ppn <= CsrPlugin_csrMapping_writeDataSignal[19 : 0]; end end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_404[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_261)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_stvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_261) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_stvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_stvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_321)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_321) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_320)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_sscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_320) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_sscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_322)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_scause_interrupt <= _zz_435[0]; - CsrPlugin_scause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_322) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_scause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_scause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_323)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_stval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_323) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_stval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -6673,9 +6962,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_isLrsc, input io_cpu_execute_args_isAmo, @@ -6709,6 +6997,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -6724,9 +7013,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -6734,7 +7024,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -6743,38 +7033,23 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire _zz_19; - wire _zz_20; - wire _zz_21; - wire _zz_22; - wire [2:0] _zz_23; - wire [0:0] _zz_24; - wire [0:0] _zz_25; - wire [9:0] _zz_26; - wire [9:0] _zz_27; - wire [31:0] _zz_28; - wire [31:0] _zz_29; - wire [31:0] _zz_30; - wire [31:0] _zz_31; - wire [1:0] _zz_32; - wire [31:0] _zz_33; - wire [1:0] _zz_34; - wire [1:0] _zz_35; - wire [0:0] _zz_36; - wire [0:0] _zz_37; - wire [0:0] _zz_38; - wire [2:0] _zz_39; - wire [1:0] _zz_40; - wire [21:0] _zz_41; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [31:0] _zz_stageB_amo_addSub; + wire [31:0] _zz_stageB_amo_addSub_1; + wire [31:0] _zz_stageB_amo_addSub_2; + wire [31:0] _zz_stageB_amo_addSub_3; + wire [31:0] _zz_stageB_amo_addSub_4; + wire [1:0] _zz_stageB_amo_addSub_5; + wire [1:0] _zz_stageB_amo_addSub_6; + wire [1:0] _zz_stageB_amo_addSub_7; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -6799,38 +7074,45 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_isLrsc; reg stageA_request_isAmo; reg stageA_request_amoCtrl_swap; reg [2:0] stageA_request_amoCtrl_alu; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_isLrsc; reg stageB_request_isAmo; @@ -6838,6 +7120,7 @@ module DataCache ( reg [2:0] stageB_request_amoCtrl_alu; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -6855,25 +7138,36 @@ module DataCache ( reg [31:0] stageB_mmuRsp_ways_2_physical; reg stageB_mmuRsp_ways_3_sel; reg [31:0] stageB_mmuRsp_ways_3_physical; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; reg stageB_lrSc_reserved; + wire when_DataCache_l866; wire stageB_isExternalLsrc; wire stageB_isExternalAmo; reg [31:0] stageB_requestDataBypass; @@ -6882,14 +7176,26 @@ module DataCache ( wire [31:0] stageB_amo_addSub; wire stageB_amo_less; wire stageB_amo_selectRf; + wire [2:0] switch_Misc_l200; reg [31:0] stageB_amo_result; reg [31:0] stageB_amo_resultReg; reg stageB_amo_internal_resultRegValid; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l984; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l997; + wire when_DataCache_l1005; + wire when_DataCache_l1010; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -6901,73 +7207,62 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_42; - reg [7:0] _zz_43; - reg [7:0] _zz_44; - reg [7:0] _zz_45; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_15 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); - assign _zz_16 = (! stageB_amo_internal_resultRegValid); - assign _zz_17 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); - assign _zz_18 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_19 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); - assign _zz_20 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); - assign _zz_21 = (! stageB_flusher_hold); - assign _zz_22 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_23 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); - assign _zz_24 = _zz_4[0 : 0]; - assign _zz_25 = _zz_4[1 : 1]; - assign _zz_26 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_27 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_28 = ($signed(_zz_29) + $signed(_zz_33)); - assign _zz_29 = ($signed(_zz_30) + $signed(_zz_31)); - assign _zz_30 = stageB_request_data; - assign _zz_31 = (stageB_amo_compare ? (~ stageB_dataMux) : stageB_dataMux); - assign _zz_32 = (stageB_amo_compare ? _zz_34 : _zz_35); - assign _zz_33 = {{30{_zz_32[1]}}, _zz_32}; - assign _zz_34 = 2'b01; - assign _zz_35 = 2'b00; - assign _zz_36 = 1'b1; - assign _zz_37 = (! stageB_lrSc_reserved); - assign _zz_38 = loader_counter_willIncrement; - assign _zz_39 = {2'd0, _zz_38}; - assign _zz_40 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_41 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_stageB_amo_addSub = ($signed(_zz_stageB_amo_addSub_1) + $signed(_zz_stageB_amo_addSub_4)); + assign _zz_stageB_amo_addSub_1 = ($signed(_zz_stageB_amo_addSub_2) + $signed(_zz_stageB_amo_addSub_3)); + assign _zz_stageB_amo_addSub_2 = io_cpu_writeBack_storeData[31 : 0]; + assign _zz_stageB_amo_addSub_3 = (stageB_amo_compare ? (~ stageB_dataMux[31 : 0]) : stageB_dataMux[31 : 0]); + assign _zz_stageB_amo_addSub_5 = (stageB_amo_compare ? _zz_stageB_amo_addSub_6 : _zz_stageB_amo_addSub_7); + assign _zz_stageB_amo_addSub_4 = {{30{_zz_stageB_amo_addSub_5[1]}}, _zz_stageB_amo_addSub_5}; + assign _zz_stageB_amo_addSub_6 = 2'b01; + assign _zz_stageB_amo_addSub_7 = 2'b00; + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_41; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_45, _zz_44, _zz_43, _zz_42}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_42 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_43 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_44 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_45 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -6982,327 +7277,348 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_24[0]; - assign ways_0_tagsReadRsp_error = _zz_25[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - if(stageB_request_isAmo)begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin dataWriteCmd_valid = 1'b0; end end - if(_zz_17)begin + if(when_DataCache_l1010) begin dataWriteCmd_valid = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_36[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_18)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_26)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_27)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(! _zz_15) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_14)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end - if(_zz_19)begin + if(when_DataCache_l984) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_15)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end - if(stageB_request_isAmo)begin - if(_zz_16)begin + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin io_cpu_writeBack_haltIt = 1'b1; end end - if(_zz_17)begin + if(when_DataCache_l1010) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); + assign when_DataCache_l866 = ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc); assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - always @ (*) begin - stageB_requestDataBypass = stageB_request_data; - if(stageB_request_isAmo)begin - stageB_requestDataBypass = stageB_amo_resultReg; + always @(*) begin + stageB_requestDataBypass = io_cpu_writeBack_storeData; + if(stageB_request_isAmo) begin + stageB_requestDataBypass[31 : 0] = stageB_amo_resultReg; end end assign stageB_amo_compare = stageB_request_amoCtrl_alu[2]; assign stageB_amo_unsigned = (stageB_request_amoCtrl_alu[2 : 1] == 2'b11); - assign stageB_amo_addSub = _zz_28; - assign stageB_amo_less = ((stageB_request_data[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : stageB_request_data[31])); + assign stageB_amo_addSub = _zz_stageB_amo_addSub; + assign stageB_amo_less = ((io_cpu_writeBack_storeData[31] == stageB_dataMux[31]) ? stageB_amo_addSub[31] : (stageB_amo_unsigned ? stageB_dataMux[31] : io_cpu_writeBack_storeData[31])); assign stageB_amo_selectRf = (stageB_request_amoCtrl_swap ? 1'b1 : (stageB_request_amoCtrl_alu[0] ^ stageB_amo_less)); - always @ (*) begin - case(_zz_23) + assign switch_Misc_l200 = (stageB_request_amoCtrl_alu | {stageB_request_amoCtrl_swap,2'b00}); + always @(*) begin + case(switch_Misc_l200) 3'b000 : begin stageB_amo_result = stageB_amo_addSub; end 3'b001 : begin - stageB_amo_result = (stageB_request_data ^ stageB_dataMux); + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] ^ stageB_dataMux[31 : 0]); end 3'b010 : begin - stageB_amo_result = (stageB_request_data | stageB_dataMux); + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] | stageB_dataMux[31 : 0]); end 3'b011 : begin - stageB_amo_result = (stageB_request_data & stageB_dataMux); + stageB_amo_result = (io_cpu_writeBack_storeData[31 : 0] & stageB_dataMux[31 : 0]); end default : begin - stageB_amo_result = (stageB_amo_selectRf ? stageB_request_data : stageB_dataMux); + stageB_amo_result = (stageB_amo_selectRf ? io_cpu_writeBack_storeData[31 : 0] : stageB_dataMux[31 : 0]); end endcase end - always @ (*) begin + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -7310,103 +7626,87 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_request_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - if(_zz_20)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_14)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); - if(_zz_19)begin + if(when_DataCache_l984) begin io_mem_cmd_valid = 1'b0; end end else begin - if(_zz_15)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end - if(stageB_request_isAmo)begin - if(_zz_16)begin + if(stageB_request_isAmo) begin + if(when_DataCache_l997) begin io_mem_cmd_valid = 1'b0; end end - if(_zz_20)begin + if(when_DataCache_l1005) begin io_mem_cmd_valid = 1'b0; end - if(_zz_17)begin + if(when_DataCache_l1010) begin io_mem_cmd_valid = 1'b0; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(_zz_15)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -7414,12 +7714,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_14) begin - if(! _zz_15) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -7430,23 +7730,44 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l984 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_request_isAmo))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l997 = (! stageB_amo_internal_resultRegValid); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_request_isAmo) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1010 = (stageB_request_isLrsc && (! stageB_lrSc_reserved)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end - if((stageB_request_isLrsc && stageB_request_wr))begin - io_cpu_writeBack_data = {31'd0, _zz_37}; - end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign io_cpu_writeBack_exclusiveOk = stageB_lrSc_reserved; + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_18)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -7454,26 +7775,29 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_39); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_isLrsc <= io_cpu_execute_args_isLrsc; stageA_request_isAmo <= io_cpu_execute_args_isAmo; @@ -7481,18 +7805,17 @@ module DataCache ( stageA_request_amoCtrl_alu <= io_cpu_execute_args_amoCtrl_alu; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_isLrsc <= stageA_request_isLrsc; stageB_request_isAmo <= stageA_request_isAmo; @@ -7500,7 +7823,7 @@ module DataCache ( stageB_request_amoCtrl_alu <= stageA_request_amoCtrl_alu; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -7519,48 +7842,39 @@ module DataCache ( stageB_mmuRsp_ways_3_sel <= io_cpu_memory_mmuRsp_ways_3_sel; stageB_mmuRsp_ways_3_physical <= io_cpu_memory_mmuRsp_ways_3_physical; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_21)begin - if(_zz_22)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end stageB_amo_internal_resultRegValid <= io_cpu_writeBack_isStuck; stageB_amo_resultReg <= stageB_amo_result; loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; stageB_lrSc_reserved <= 1'b0; loader_valid <= 1'b0; @@ -7569,27 +7883,29 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_21)begin - if(! _zz_22) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end - if(((io_cpu_writeBack_isValid && (! io_cpu_writeBack_isStuck)) && stageB_request_isLrsc))begin + if(when_DataCache_l866) begin stageB_lrSc_reserved <= (! stageB_request_wr); end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_lrSc_reserved <= stageB_lrSc_reserved; end `ifndef SYNTHESIS @@ -7597,28 +7913,27 @@ module DataCache ( assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_18)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_40[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -7676,13 +7991,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [21:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [21:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [21:0] _zz_ways_0_tags_port1; + wire [21:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -7691,8 +8002,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [7:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -7706,22 +8022,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [9:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [9:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [9:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [6:0] _zz_6; - wire _zz_7; + wire [6:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_8; + wire [21:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -7739,82 +8058,85 @@ module InstructionCache ( reg [31:0] decodeStage_mmuRsp_ways_2_physical; reg decodeStage_mmuRsp_ways_3_sel; reg [31:0] decodeStage_mmuRsp_ways_3_physical; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - assign _zz_11 = (! lineLoader_flushCounter[7]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[7]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -7830,30 +8152,35 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[11 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[21 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[11 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[21 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -7861,51 +8188,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); end - _zz_3 <= lineLoader_flushCounter[7]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[7]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 8'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -7924,10 +8251,10 @@ module InstructionCache ( decodeStage_mmuRsp_ways_3_sel <= io_cpu_fetch_mmuRsp_ways_3_sel; decodeStage_mmuRsp_ways_3_physical <= io_cpu_fetch_mmuRsp_ways_3_physical; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v index 4dd8855..01e1f6d 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v @@ -1,46 +1,46 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b10 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -73,18 +73,17 @@ module VexRiscv ( input clk, input reset ); - wire _zz_159; - wire _zz_160; - wire _zz_161; - wire _zz_162; - wire _zz_163; - wire _zz_164; - wire _zz_165; - wire _zz_166; - reg _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -97,309 +96,250 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_171; - wire _zz_172; - wire _zz_173; - wire _zz_174; - wire _zz_175; - wire _zz_176; - wire _zz_177; - wire _zz_178; - wire _zz_179; - wire _zz_180; - wire _zz_181; - wire _zz_182; - wire _zz_183; - wire _zz_184; - wire _zz_185; - wire _zz_186; - wire _zz_187; - wire [1:0] _zz_188; - wire _zz_189; - wire _zz_190; - wire _zz_191; - wire _zz_192; - wire _zz_193; - wire _zz_194; - wire _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - wire _zz_204; - wire _zz_205; - wire _zz_206; - wire _zz_207; - wire [1:0] _zz_208; - wire _zz_209; - wire [0:0] _zz_210; - wire [0:0] _zz_211; - wire [0:0] _zz_212; - wire [0:0] _zz_213; - wire [0:0] _zz_214; - wire [0:0] _zz_215; - wire [0:0] _zz_216; - wire [0:0] _zz_217; - wire [0:0] _zz_218; - wire [0:0] _zz_219; - wire [0:0] _zz_220; - wire [0:0] _zz_221; - wire [0:0] _zz_222; - wire [0:0] _zz_223; - wire [0:0] _zz_224; - wire [0:0] _zz_225; - wire [3:0] _zz_226; - wire [2:0] _zz_227; - wire [31:0] _zz_228; - wire [11:0] _zz_229; - wire [31:0] _zz_230; - wire [19:0] _zz_231; - wire [11:0] _zz_232; - wire [31:0] _zz_233; - wire [31:0] _zz_234; - wire [19:0] _zz_235; - wire [11:0] _zz_236; - wire [2:0] _zz_237; - wire [0:0] _zz_238; - wire [2:0] _zz_239; - wire [4:0] _zz_240; - wire [11:0] _zz_241; - wire [11:0] _zz_242; - wire [31:0] _zz_243; - wire [31:0] _zz_244; - wire [31:0] _zz_245; - wire [31:0] _zz_246; - wire [31:0] _zz_247; - wire [31:0] _zz_248; - wire [31:0] _zz_249; - wire [31:0] _zz_250; - wire [32:0] _zz_251; - wire [11:0] _zz_252; - wire [19:0] _zz_253; - wire [11:0] _zz_254; - wire [31:0] _zz_255; - wire [31:0] _zz_256; - wire [31:0] _zz_257; - wire [11:0] _zz_258; - wire [19:0] _zz_259; - wire [11:0] _zz_260; - wire [2:0] _zz_261; - wire [1:0] _zz_262; - wire [1:0] _zz_263; - wire [1:0] _zz_264; - wire [1:0] _zz_265; - wire [0:0] _zz_266; - wire [5:0] _zz_267; - wire [33:0] _zz_268; - wire [32:0] _zz_269; - wire [33:0] _zz_270; - wire [32:0] _zz_271; - wire [33:0] _zz_272; - wire [32:0] _zz_273; - wire [0:0] _zz_274; - wire [5:0] _zz_275; - wire [32:0] _zz_276; - wire [31:0] _zz_277; - wire [31:0] _zz_278; - wire [32:0] _zz_279; - wire [32:0] _zz_280; - wire [32:0] _zz_281; - wire [32:0] _zz_282; - wire [0:0] _zz_283; - wire [32:0] _zz_284; - wire [0:0] _zz_285; - wire [32:0] _zz_286; - wire [0:0] _zz_287; - wire [31:0] _zz_288; - wire [0:0] _zz_289; - wire [0:0] _zz_290; - wire [0:0] _zz_291; - wire [0:0] _zz_292; - wire [0:0] _zz_293; - wire [0:0] _zz_294; - wire [26:0] _zz_295; - wire _zz_296; - wire _zz_297; - wire [1:0] _zz_298; - wire [31:0] _zz_299; - wire [31:0] _zz_300; - wire [31:0] _zz_301; - wire _zz_302; - wire [0:0] _zz_303; - wire [12:0] _zz_304; - wire [31:0] _zz_305; - wire [31:0] _zz_306; - wire [31:0] _zz_307; - wire _zz_308; - wire [0:0] _zz_309; - wire [6:0] _zz_310; - wire [31:0] _zz_311; - wire [31:0] _zz_312; - wire [31:0] _zz_313; - wire _zz_314; - wire [0:0] _zz_315; - wire [0:0] _zz_316; - wire _zz_317; - wire _zz_318; - wire _zz_319; - wire [31:0] _zz_320; - wire [0:0] _zz_321; - wire [1:0] _zz_322; - wire [0:0] _zz_323; - wire [0:0] _zz_324; - wire _zz_325; - wire [0:0] _zz_326; - wire [24:0] _zz_327; - wire [31:0] _zz_328; - wire [31:0] _zz_329; - wire [31:0] _zz_330; - wire [0:0] _zz_331; - wire [0:0] _zz_332; - wire [1:0] _zz_333; - wire [1:0] _zz_334; - wire _zz_335; - wire [0:0] _zz_336; - wire [20:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire [31:0] _zz_340; - wire [31:0] _zz_341; - wire [31:0] _zz_342; - wire [31:0] _zz_343; - wire [0:0] _zz_344; - wire [0:0] _zz_345; - wire [2:0] _zz_346; - wire [2:0] _zz_347; - wire _zz_348; - wire [0:0] _zz_349; - wire [17:0] _zz_350; - wire [31:0] _zz_351; - wire [31:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire _zz_355; - wire _zz_356; - wire _zz_357; - wire [0:0] _zz_358; - wire [0:0] _zz_359; - wire _zz_360; - wire [0:0] _zz_361; - wire [0:0] _zz_362; - wire _zz_363; - wire [0:0] _zz_364; - wire [14:0] _zz_365; - wire [31:0] _zz_366; - wire [31:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; - wire [31:0] _zz_370; - wire [31:0] _zz_371; - wire [31:0] _zz_372; - wire [31:0] _zz_373; - wire [0:0] _zz_374; - wire [0:0] _zz_375; - wire [1:0] _zz_376; - wire [1:0] _zz_377; - wire _zz_378; - wire [0:0] _zz_379; - wire [12:0] _zz_380; - wire [31:0] _zz_381; - wire [31:0] _zz_382; - wire [31:0] _zz_383; - wire [31:0] _zz_384; - wire [31:0] _zz_385; - wire [31:0] _zz_386; - wire _zz_387; - wire [0:0] _zz_388; - wire [0:0] _zz_389; - wire _zz_390; - wire [0:0] _zz_391; - wire [0:0] _zz_392; - wire _zz_393; - wire [0:0] _zz_394; - wire [9:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire [0:0] _zz_399; - wire [0:0] _zz_400; - wire [0:0] _zz_401; - wire [4:0] _zz_402; - wire [1:0] _zz_403; - wire [1:0] _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [6:0] _zz_407; - wire [31:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire [31:0] _zz_411; - wire _zz_412; - wire [0:0] _zz_413; - wire [1:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire [0:0] _zz_420; - wire [0:0] _zz_421; - wire _zz_422; - wire [0:0] _zz_423; - wire [3:0] _zz_424; - wire [31:0] _zz_425; - wire [31:0] _zz_426; - wire [31:0] _zz_427; - wire _zz_428; - wire _zz_429; - wire [31:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire [31:0] _zz_433; - wire [31:0] _zz_434; - wire [31:0] _zz_435; - wire [31:0] _zz_436; - wire [0:0] _zz_437; - wire [2:0] _zz_438; - wire [0:0] _zz_439; - wire [0:0] _zz_440; - wire _zz_441; - wire [0:0] _zz_442; - wire [1:0] _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire [31:0] _zz_446; - wire [31:0] _zz_447; - wire _zz_448; - wire [0:0] _zz_449; - wire [0:0] _zz_450; - wire [31:0] _zz_451; - wire [31:0] _zz_452; - wire [0:0] _zz_453; - wire [1:0] _zz_454; - wire [1:0] _zz_455; - wire [1:0] _zz_456; - wire _zz_457; - wire _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire [31:0] _zz_462; - wire [31:0] _zz_463; - wire [31:0] _zz_464; - wire [31:0] _zz_465; - wire [31:0] _zz_466; - wire [31:0] _zz_467; - wire _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire _zz_471; - wire _zz_472; - wire _zz_473; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [12:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [6:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] _zz__zz_decode_IS_DIV; + wire [0:0] _zz__zz_decode_IS_DIV_1; + wire [1:0] _zz__zz_decode_IS_DIV_2; + wire [0:0] _zz__zz_decode_IS_DIV_3; + wire [0:0] _zz__zz_decode_IS_DIV_4; + wire _zz__zz_decode_IS_DIV_5; + wire [31:0] _zz__zz_decode_IS_DIV_6; + wire [0:0] _zz__zz_decode_IS_DIV_7; + wire [31:0] _zz__zz_decode_IS_DIV_8; + wire [31:0] _zz__zz_decode_IS_DIV_9; + wire [24:0] _zz__zz_decode_IS_DIV_10; + wire [0:0] _zz__zz_decode_IS_DIV_11; + wire [31:0] _zz__zz_decode_IS_DIV_12; + wire [0:0] _zz__zz_decode_IS_DIV_13; + wire [31:0] _zz__zz_decode_IS_DIV_14; + wire [1:0] _zz__zz_decode_IS_DIV_15; + wire [31:0] _zz__zz_decode_IS_DIV_16; + wire [31:0] _zz__zz_decode_IS_DIV_17; + wire [1:0] _zz__zz_decode_IS_DIV_18; + wire _zz__zz_decode_IS_DIV_19; + wire [31:0] _zz__zz_decode_IS_DIV_20; + wire [31:0] _zz__zz_decode_IS_DIV_21; + wire [0:0] _zz__zz_decode_IS_DIV_22; + wire [0:0] _zz__zz_decode_IS_DIV_23; + wire [31:0] _zz__zz_decode_IS_DIV_24; + wire [0:0] _zz__zz_decode_IS_DIV_25; + wire [31:0] _zz__zz_decode_IS_DIV_26; + wire [20:0] _zz__zz_decode_IS_DIV_27; + wire [2:0] _zz__zz_decode_IS_DIV_28; + wire [31:0] _zz__zz_decode_IS_DIV_29; + wire [31:0] _zz__zz_decode_IS_DIV_30; + wire _zz__zz_decode_IS_DIV_31; + wire [31:0] _zz__zz_decode_IS_DIV_32; + wire _zz__zz_decode_IS_DIV_33; + wire [31:0] _zz__zz_decode_IS_DIV_34; + wire [2:0] _zz__zz_decode_IS_DIV_35; + wire _zz__zz_decode_IS_DIV_36; + wire _zz__zz_decode_IS_DIV_37; + wire [31:0] _zz__zz_decode_IS_DIV_38; + wire [0:0] _zz__zz_decode_IS_DIV_39; + wire [31:0] _zz__zz_decode_IS_DIV_40; + wire [31:0] _zz__zz_decode_IS_DIV_41; + wire [0:0] _zz__zz_decode_IS_DIV_42; + wire [31:0] _zz__zz_decode_IS_DIV_43; + wire [31:0] _zz__zz_decode_IS_DIV_44; + wire [0:0] _zz__zz_decode_IS_DIV_45; + wire _zz__zz_decode_IS_DIV_46; + wire [31:0] _zz__zz_decode_IS_DIV_47; + wire [17:0] _zz__zz_decode_IS_DIV_48; + wire [0:0] _zz__zz_decode_IS_DIV_49; + wire [0:0] _zz__zz_decode_IS_DIV_50; + wire _zz__zz_decode_IS_DIV_51; + wire [0:0] _zz__zz_decode_IS_DIV_52; + wire [31:0] _zz__zz_decode_IS_DIV_53; + wire [0:0] _zz__zz_decode_IS_DIV_54; + wire [31:0] _zz__zz_decode_IS_DIV_55; + wire [0:0] _zz__zz_decode_IS_DIV_56; + wire [1:0] _zz__zz_decode_IS_DIV_57; + wire [31:0] _zz__zz_decode_IS_DIV_58; + wire [31:0] _zz__zz_decode_IS_DIV_59; + wire [31:0] _zz__zz_decode_IS_DIV_60; + wire [31:0] _zz__zz_decode_IS_DIV_61; + wire [1:0] _zz__zz_decode_IS_DIV_62; + wire [14:0] _zz__zz_decode_IS_DIV_63; + wire _zz__zz_decode_IS_DIV_64; + wire _zz__zz_decode_IS_DIV_65; + wire [0:0] _zz__zz_decode_IS_DIV_66; + wire [31:0] _zz__zz_decode_IS_DIV_67; + wire [0:0] _zz__zz_decode_IS_DIV_68; + wire [31:0] _zz__zz_decode_IS_DIV_69; + wire [0:0] _zz__zz_decode_IS_DIV_70; + wire _zz__zz_decode_IS_DIV_71; + wire [12:0] _zz__zz_decode_IS_DIV_72; + wire [0:0] _zz__zz_decode_IS_DIV_73; + wire [31:0] _zz__zz_decode_IS_DIV_74; + wire [0:0] _zz__zz_decode_IS_DIV_75; + wire _zz__zz_decode_IS_DIV_76; + wire [0:0] _zz__zz_decode_IS_DIV_77; + wire [31:0] _zz__zz_decode_IS_DIV_78; + wire [0:0] _zz__zz_decode_IS_DIV_79; + wire [31:0] _zz__zz_decode_IS_DIV_80; + wire [0:0] _zz__zz_decode_IS_DIV_81; + wire [0:0] _zz__zz_decode_IS_DIV_82; + wire [4:0] _zz__zz_decode_IS_DIV_83; + wire [31:0] _zz__zz_decode_IS_DIV_84; + wire [31:0] _zz__zz_decode_IS_DIV_85; + wire _zz__zz_decode_IS_DIV_86; + wire [31:0] _zz__zz_decode_IS_DIV_87; + wire [0:0] _zz__zz_decode_IS_DIV_88; + wire [31:0] _zz__zz_decode_IS_DIV_89; + wire [31:0] _zz__zz_decode_IS_DIV_90; + wire [1:0] _zz__zz_decode_IS_DIV_91; + wire _zz__zz_decode_IS_DIV_92; + wire [31:0] _zz__zz_decode_IS_DIV_93; + wire _zz__zz_decode_IS_DIV_94; + wire [31:0] _zz__zz_decode_IS_DIV_95; + wire [9:0] _zz__zz_decode_IS_DIV_96; + wire [1:0] _zz__zz_decode_IS_DIV_97; + wire [31:0] _zz__zz_decode_IS_DIV_98; + wire [31:0] _zz__zz_decode_IS_DIV_99; + wire [1:0] _zz__zz_decode_IS_DIV_100; + wire _zz__zz_decode_IS_DIV_101; + wire _zz__zz_decode_IS_DIV_102; + wire [31:0] _zz__zz_decode_IS_DIV_103; + wire [0:0] _zz__zz_decode_IS_DIV_104; + wire [0:0] _zz__zz_decode_IS_DIV_105; + wire [31:0] _zz__zz_decode_IS_DIV_106; + wire [31:0] _zz__zz_decode_IS_DIV_107; + wire [0:0] _zz__zz_decode_IS_DIV_108; + wire [31:0] _zz__zz_decode_IS_DIV_109; + wire [31:0] _zz__zz_decode_IS_DIV_110; + wire [6:0] _zz__zz_decode_IS_DIV_111; + wire [0:0] _zz__zz_decode_IS_DIV_112; + wire [31:0] _zz__zz_decode_IS_DIV_113; + wire [31:0] _zz__zz_decode_IS_DIV_114; + wire [0:0] _zz__zz_decode_IS_DIV_115; + wire _zz__zz_decode_IS_DIV_116; + wire [0:0] _zz__zz_decode_IS_DIV_117; + wire [31:0] _zz__zz_decode_IS_DIV_118; + wire [31:0] _zz__zz_decode_IS_DIV_119; + wire [2:0] _zz__zz_decode_IS_DIV_120; + wire _zz__zz_decode_IS_DIV_121; + wire [0:0] _zz__zz_decode_IS_DIV_122; + wire [31:0] _zz__zz_decode_IS_DIV_123; + wire [0:0] _zz__zz_decode_IS_DIV_124; + wire [31:0] _zz__zz_decode_IS_DIV_125; + wire [0:0] _zz__zz_decode_IS_DIV_126; + wire [0:0] _zz__zz_decode_IS_DIV_127; + wire [31:0] _zz__zz_decode_IS_DIV_128; + wire [31:0] _zz__zz_decode_IS_DIV_129; + wire [0:0] _zz__zz_decode_IS_DIV_130; + wire [3:0] _zz__zz_decode_IS_DIV_131; + wire _zz__zz_decode_IS_DIV_132; + wire [0:0] _zz__zz_decode_IS_DIV_133; + wire [31:0] _zz__zz_decode_IS_DIV_134; + wire [1:0] _zz__zz_decode_IS_DIV_135; + wire [31:0] _zz__zz_decode_IS_DIV_136; + wire [31:0] _zz__zz_decode_IS_DIV_137; + wire [31:0] _zz__zz_decode_IS_DIV_138; + wire [31:0] _zz__zz_decode_IS_DIV_139; + wire [0:0] _zz__zz_decode_IS_DIV_140; + wire [1:0] _zz__zz_decode_IS_DIV_141; + wire [31:0] _zz__zz_decode_IS_DIV_142; + wire [31:0] _zz__zz_decode_IS_DIV_143; + wire [1:0] _zz__zz_decode_IS_DIV_144; + wire [1:0] _zz__zz_decode_IS_DIV_145; + wire _zz__zz_decode_IS_DIV_146; + wire _zz__zz_decode_IS_DIV_147; + wire _zz__zz_decode_IS_DIV_148; + wire [31:0] _zz__zz_decode_IS_DIV_149; + wire [31:0] _zz__zz_decode_IS_DIV_150; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [31:0] _zz__zz_decode_RS2_3; + wire [32:0] _zz__zz_decode_RS2_3_1; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1; + wire _zz_when; + wire _zz_when_1; + wire [5:0] _zz_memory_MulDivIterativePlugin_mul_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_mul_counter_valueNext_1; + wire [33:0] _zz_memory_MulDivIterativePlugin_accumulator; + wire [33:0] _zz_memory_MulDivIterativePlugin_accumulator_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_accumulator_2; + wire [33:0] _zz_memory_MulDivIterativePlugin_accumulator_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_accumulator_4; + wire [32:0] _zz_memory_MulDivIterativePlugin_accumulator_5; + wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; + wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_3; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_4; + wire [31:0] _zz_memory_MulDivIterativePlugin_rs2; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_1; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -415,46 +355,48 @@ module VexRiscv ( wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_13; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_16; - wire `Src2CtrlEnum_defaultEncoding_type _zz_17; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_19; - wire `AluCtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_22; - wire `Src1CtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire decode_MEMORY_ENABLE; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; wire execute_IS_RS1_SIGNED; wire execute_IS_DIV; wire execute_IS_MUL; @@ -464,116 +406,94 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_25; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; wire [31:0] execute_RS1; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_28; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; - reg [31:0] _zz_29; + reg [31:0] _zz_decode_RS2; wire memory_REGFILE_WRITE_VALID; wire [31:0] memory_INSTRUCTION; wire memory_BYPASSABLE_MEMORY_STAGE; wire writeBack_REGFILE_WRITE_VALID; reg [31:0] decode_RS2; reg [31:0] decode_RS1; - reg [31:0] _zz_30; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_31; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_32; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_33; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_34; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_35; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_36; - wire [31:0] _zz_37; - wire _zz_38; - reg _zz_39; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_40; - wire `BranchCtrlEnum_defaultEncoding_type _zz_41; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_42; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; - wire `Src2CtrlEnum_defaultEncoding_type _zz_44; - wire `AluCtrlEnum_defaultEncoding_type _zz_45; - wire `Src1CtrlEnum_defaultEncoding_type _zz_46; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; wire writeBack_MEMORY_STORE; - reg [31:0] _zz_47; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP2_physicalAddress; - wire memory_MMU_RSP2_isIoAccess; - wire memory_MMU_RSP2_isPaging; - wire memory_MMU_RSP2_allowRead; - wire memory_MMU_RSP2_allowWrite; - wire memory_MMU_RSP2_allowExecute; - wire memory_MMU_RSP2_exception; - wire memory_MMU_RSP2_refilling; - wire memory_MMU_RSP2_bypassTranslation; - wire [31:0] memory_PC; wire memory_ALIGNEMENT_FAULT; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP2_physicalAddress; - wire execute_MMU_RSP2_isIoAccess; - wire execute_MMU_RSP2_isPaging; - wire execute_MMU_RSP2_allowRead; - wire execute_MMU_RSP2_allowWrite; - wire execute_MMU_RSP2_allowExecute; - wire execute_MMU_RSP2_exception; - wire execute_MMU_RSP2_refilling; - wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; wire [31:0] execute_RS2; wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; - wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_4; reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_48; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_49; - reg [31:0] _zz_50; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; + wire decode_arbitration_haltItself; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; wire decode_arbitration_flushIt; @@ -598,7 +518,7 @@ module VexRiscv ( reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; + wire memory_arbitration_flushIt; reg memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; @@ -652,23 +572,6 @@ module VexRiscv ( reg DBusSimplePlugin_memoryExceptionPort_valid; reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_0_isValid; - wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_isPaging; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -677,6 +580,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; wire CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -694,28 +602,33 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_51; - wire [3:0] _zz_52; - wire _zz_53; - wire _zz_54; - wire _zz_55; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -738,16 +651,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_56; - wire _zz_57; - wire _zz_58; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_59; - wire _zz_60; - reg _zz_61; - wire _zz_62; - reg _zz_63; - reg [31:0] _zz_64; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -755,22 +670,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_65; - reg [18:0] _zz_66; - wire _zz_67; - reg [10:0] _zz_68; - wire _zz_69; - reg [18:0] _zz_70; - reg _zz_71; - wire _zz_72; - reg [10:0] _zz_73; - wire _zz_74; - reg [18:0] _zz_75; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -778,7 +700,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_76; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -786,6 +708,11 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dBus_cmd_valid; wire dBus_cmd_ready; wire dBus_cmd_payload_wr; @@ -795,31 +722,38 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - wire _zz_77; + wire _zz_dBus_cmd_valid; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_78; - reg [3:0] _zz_79; + reg [31:0] _zz_dBus_cmd_payload_data; + wire when_DBusSimplePlugin_l426; + reg [3:0] _zz_execute_DBusSimplePlugin_formalMask; wire [3:0] execute_DBusSimplePlugin_formalMask; + wire when_DBusSimplePlugin_l479; + wire when_DBusSimplePlugin_l486; + wire when_DBusSimplePlugin_l512; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_80; - reg [31:0] _zz_81; - wire _zz_82; - reg [31:0] _zz_83; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusSimplePlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1; + wire _zz_writeBack_DBusSimplePlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3; reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [30:0] _zz_84; - wire _zz_85; - wire _zz_86; - wire _zz_87; - wire _zz_88; - wire _zz_89; - wire _zz_90; - wire `Src1CtrlEnum_defaultEncoding_type _zz_91; - wire `AluCtrlEnum_defaultEncoding_type _zz_92; - wire `Src2CtrlEnum_defaultEncoding_type _zz_93; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_94; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_95; - wire `BranchCtrlEnum_defaultEncoding_type _zz_96; - wire `EnvCtrlEnum_defaultEncoding_type _zz_97; + wire when_DBusSimplePlugin_l558; + wire [30:0] _zz_decode_IS_DIV; + wire _zz_decode_IS_DIV_1; + wire _zz_decode_IS_DIV_2; + wire _zz_decode_IS_DIV_3; + wire _zz_decode_IS_DIV_4; + wire _zz_decode_IS_DIV_5; + wire _zz_decode_IS_DIV_6; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -827,15 +761,15 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_98; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_99; - reg [31:0] _zz_100; - wire _zz_101; - reg [19:0] _zz_102; - wire _zz_103; - reg [19:0] _zz_104; - reg [31:0] _zz_105; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; @@ -844,38 +778,59 @@ module VexRiscv ( wire [4:0] execute_LightShifterPlugin_amplitude; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_106; - reg _zz_107; - reg _zz_108; - reg _zz_109; - reg [4:0] _zz_110; - reg [31:0] _zz_111; - wire _zz_112; - wire _zz_113; - wire _zz_114; - wire _zz_115; - wire _zz_116; - wire _zz_117; + wire when_ShiftPlugins_l169; + reg [31:0] _zz_decode_RS2_3; + wire when_ShiftPlugins_l175; + wire when_ShiftPlugins_l184; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_118; - reg _zz_119; - reg _zz_120; - wire _zz_121; - reg [19:0] _zz_122; - wire _zz_123; - reg [10:0] _zz_124; - wire _zz_125; - reg [18:0] _zz_126; - reg _zz_127; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_128; - reg [19:0] _zz_129; - wire _zz_130; - reg [10:0] _zz_131; - wire _zz_132; - reg [18:0] _zz_133; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; @@ -896,9 +851,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_134; - wire _zz_135; - wire _zz_136; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -911,37 +866,60 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_137; - wire _zz_138; - wire [1:0] _zz_139; - wire _zz_140; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg [32:0] memory_MulDivIterativePlugin_rs1; reg [31:0] memory_MulDivIterativePlugin_rs2; @@ -953,6 +931,10 @@ module VexRiscv ( reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + wire when_MulDivIterativePlugin_l96; + wire when_MulDivIterativePlugin_l97; + wire when_MulDivIterativePlugin_l100; + wire when_MulDivIterativePlugin_l110; reg memory_MulDivIterativePlugin_div_needRevert; reg memory_MulDivIterativePlugin_div_counter_willIncrement; reg memory_MulDivIterativePlugin_div_counter_willClear; @@ -961,101 +943,169 @@ module VexRiscv ( wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; wire memory_MulDivIterativePlugin_div_counter_willOverflow; reg memory_MulDivIterativePlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_141; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [31:0] _zz_142; - wire _zz_143; - wire _zz_144; - reg [32:0] _zz_145; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_MulDivIterativePlugin_rs1; + wire _zz_memory_MulDivIterativePlugin_rs1_1; + reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_146; - wire [31:0] _zz_147; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_9; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_14; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_15; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_16; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg decode_to_execute_MEMORY_STORE; + wire when_Pipeline_l124_23; reg execute_to_memory_MEMORY_STORE; + wire when_Pipeline_l124_24; reg memory_to_writeBack_MEMORY_STORE; + wire when_Pipeline_l124_25; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_26; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_27; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_28; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_29; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_30; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_31; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_32; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_33; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_34; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_35; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_37; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_38; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_39; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_40; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_41; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_42; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_43; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_44; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_45; reg execute_to_memory_ALIGNEMENT_FAULT; + wire when_Pipeline_l124_46; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_47; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_MMU_FAULT; - reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; - reg execute_to_memory_MMU_RSP2_isIoAccess; - reg execute_to_memory_MMU_RSP2_isPaging; - reg execute_to_memory_MMU_RSP2_allowRead; - reg execute_to_memory_MMU_RSP2_allowWrite; - reg execute_to_memory_MMU_RSP2_allowExecute; - reg execute_to_memory_MMU_RSP2_exception; - reg execute_to_memory_MMU_RSP2_refilling; - reg execute_to_memory_MMU_RSP2_bypassTranslation; + wire when_Pipeline_l124_48; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_49; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_50; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_51; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_52; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_148; - reg [31:0] _zz_149; - reg [31:0] _zz_150; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [2:0] _zz_156; - reg _zz_157; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -1063,78 +1113,79 @@ module VexRiscv ( wire [31:0] dBus_cmd_halfPipe_payload_address; wire [31:0] dBus_cmd_halfPipe_payload_data; wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_158; + reg dBus_cmd_rValid; + wire dBus_cmd_halfPipe_fire; + reg dBus_cmd_rData_wr; + reg [31:0] dBus_cmd_rData_address; + reg [31:0] dBus_cmd_rData_data; + reg [1:0] dBus_cmd_rData_size; + reg [3:0] _zz_dBusWishbone_SEL; + wire when_DBusSimplePlugin_l189; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; - reg [71:0] _zz_12_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_13_string; - reg [39:0] _zz_14_string; - reg [39:0] _zz_15_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_16_string; - reg [23:0] _zz_17_string; - reg [23:0] _zz_18_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_19_string; - reg [63:0] _zz_20_string; - reg [63:0] _zz_21_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_22_string; - reg [95:0] _zz_23_string; - reg [95:0] _zz_24_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_25_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_26_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_28_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_31_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_33_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_34_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_35_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_36_string; - reg [39:0] _zz_40_string; - reg [31:0] _zz_41_string; - reg [71:0] _zz_42_string; - reg [39:0] _zz_43_string; - reg [23:0] _zz_44_string; - reg [63:0] _zz_45_string; - reg [95:0] _zz_46_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_48_string; - reg [95:0] _zz_91_string; - reg [63:0] _zz_92_string; - reg [23:0] _zz_93_string; - reg [39:0] _zz_94_string; - reg [71:0] _zz_95_string; - reg [31:0] _zz_96_string; - reg [39:0] _zz_97_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1148,1004 +1199,939 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_171 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_172 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_173 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_174 = 1'b1; - assign _zz_175 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_176 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_177 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_178 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_179 = ((_zz_164 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_180 = ((_zz_164 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_181 = ((_zz_164 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_182 = ((_zz_164 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_183 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_184 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_185 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_186 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_187 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_188 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_189 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_190 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_191 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_192 = (1'b0 || (! 1'b1)); - assign _zz_193 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_194 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_195 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_196 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_197 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_198 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_199 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_200 = (! memory_arbitration_isStuck); - assign _zz_201 = (iBus_cmd_valid || (_zz_156 != 3'b000)); - assign _zz_202 = (! execute_arbitration_isStuckByOthers); - assign _zz_203 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_204 = ((_zz_134 && 1'b1) && (! 1'b0)); - assign _zz_205 = ((_zz_135 && 1'b1) && (! 1'b0)); - assign _zz_206 = ((_zz_136 && 1'b1) && (! 1'b0)); - assign _zz_207 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_208 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_209 = execute_INSTRUCTION[13]; - assign _zz_210 = _zz_84[30 : 30]; - assign _zz_211 = _zz_84[29 : 29]; - assign _zz_212 = _zz_84[28 : 28]; - assign _zz_213 = _zz_84[27 : 27]; - assign _zz_214 = _zz_84[24 : 24]; - assign _zz_215 = _zz_84[16 : 16]; - assign _zz_216 = _zz_84[13 : 13]; - assign _zz_217 = _zz_84[12 : 12]; - assign _zz_218 = _zz_84[11 : 11]; - assign _zz_219 = _zz_84[15 : 15]; - assign _zz_220 = _zz_84[5 : 5]; - assign _zz_221 = _zz_84[3 : 3]; - assign _zz_222 = _zz_84[19 : 19]; - assign _zz_223 = _zz_84[10 : 10]; - assign _zz_224 = _zz_84[4 : 4]; - assign _zz_225 = _zz_84[0 : 0]; - assign _zz_226 = (_zz_51 - 4'b0001); - assign _zz_227 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_228 = {29'd0, _zz_227}; - assign _zz_229 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_230 = {{_zz_66,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_231 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_232 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_233 = {{_zz_68,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_234 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_235 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_236 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_237 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_238 = execute_SRC_LESS; - assign _zz_239 = 3'b100; - assign _zz_240 = execute_INSTRUCTION[19 : 15]; - assign _zz_241 = execute_INSTRUCTION[31 : 20]; - assign _zz_242 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_243 = ($signed(_zz_244) + $signed(_zz_247)); - assign _zz_244 = ($signed(_zz_245) + $signed(_zz_246)); - assign _zz_245 = execute_SRC1; - assign _zz_246 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_247 = (execute_SRC_USE_SUB_LESS ? _zz_248 : _zz_249); - assign _zz_248 = 32'h00000001; - assign _zz_249 = 32'h0; - assign _zz_250 = (_zz_251 >>> 1); - assign _zz_251 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_252 = execute_INSTRUCTION[31 : 20]; - assign _zz_253 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_254 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_255 = {_zz_122,execute_INSTRUCTION[31 : 20]}; - assign _zz_256 = {{_zz_124,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_257 = {{_zz_126,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_258 = execute_INSTRUCTION[31 : 20]; - assign _zz_259 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_260 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_261 = 3'b100; - assign _zz_262 = (_zz_137 & (~ _zz_263)); - assign _zz_263 = (_zz_137 - 2'b01); - assign _zz_264 = (_zz_139 & (~ _zz_265)); - assign _zz_265 = (_zz_139 - 2'b01); - assign _zz_266 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_267 = {5'd0, _zz_266}; - assign _zz_268 = (_zz_270 + _zz_272); - assign _zz_269 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_270 = {{1{_zz_269[32]}}, _zz_269}; - assign _zz_271 = _zz_273; - assign _zz_272 = {{1{_zz_271[32]}}, _zz_271}; - assign _zz_273 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_274 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_275 = {5'd0, _zz_274}; - assign _zz_276 = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_277 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_278 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_279 = {_zz_141,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_280 = _zz_281; - assign _zz_281 = _zz_282; - assign _zz_282 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_142) : _zz_142)} + _zz_284); - assign _zz_283 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_284 = {32'd0, _zz_283}; - assign _zz_285 = _zz_144; - assign _zz_286 = {32'd0, _zz_285}; - assign _zz_287 = _zz_143; - assign _zz_288 = {31'd0, _zz_287}; - assign _zz_289 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_290 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_291 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_292 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_293 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_294 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_295 = (iBus_cmd_payload_address >>> 5); - assign _zz_296 = 1'b1; - assign _zz_297 = 1'b1; - assign _zz_298 = {_zz_55,_zz_54}; - assign _zz_299 = 32'h0000107f; - assign _zz_300 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_301 = 32'h00002073; - assign _zz_302 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_303 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_304 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_305) == 32'h00000003),{(_zz_306 == _zz_307),{_zz_308,{_zz_309,_zz_310}}}}}}; - assign _zz_305 = 32'h0000505f; - assign _zz_306 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_307 = 32'h00000063; - assign _zz_308 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_309 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_310 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_311) == 32'h00005033),{(_zz_312 == _zz_313),{_zz_314,{_zz_315,_zz_316}}}}}}; - assign _zz_311 = 32'hbe00707f; - assign _zz_312 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_313 = 32'h00000033; - assign _zz_314 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_315 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_316 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); - assign _zz_317 = decode_INSTRUCTION[31]; - assign _zz_318 = decode_INSTRUCTION[31]; - assign _zz_319 = decode_INSTRUCTION[7]; - assign _zz_320 = 32'h02004064; - assign _zz_321 = _zz_90; - assign _zz_322 = {_zz_88,_zz_89}; - assign _zz_323 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_324 = 1'b0; - assign _zz_325 = (((decode_INSTRUCTION & _zz_328) == 32'h00000050) != 1'b0); - assign _zz_326 = ((_zz_329 == _zz_330) != 1'b0); - assign _zz_327 = {({_zz_331,_zz_332} != 2'b00),{(_zz_333 != _zz_334),{_zz_335,{_zz_336,_zz_337}}}}; - assign _zz_328 = 32'h10003050; - assign _zz_329 = (decode_INSTRUCTION & 32'h10403050); - assign _zz_330 = 32'h10000050; - assign _zz_331 = ((decode_INSTRUCTION & _zz_338) == 32'h00001050); - assign _zz_332 = ((decode_INSTRUCTION & _zz_339) == 32'h00002050); - assign _zz_333 = {_zz_87,(_zz_340 == _zz_341)}; - assign _zz_334 = 2'b00; - assign _zz_335 = ((_zz_342 == _zz_343) != 1'b0); - assign _zz_336 = ({_zz_344,_zz_345} != 2'b00); - assign _zz_337 = {(_zz_346 != _zz_347),{_zz_348,{_zz_349,_zz_350}}}; - assign _zz_338 = 32'h00001050; - assign _zz_339 = 32'h00002050; - assign _zz_340 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_341 = 32'h00000004; - assign _zz_342 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_343 = 32'h00000040; - assign _zz_344 = ((decode_INSTRUCTION & _zz_351) == 32'h00005010); - assign _zz_345 = ((decode_INSTRUCTION & _zz_352) == 32'h00005020); - assign _zz_346 = {(_zz_353 == _zz_354),{_zz_355,_zz_356}}; - assign _zz_347 = 3'b000; - assign _zz_348 = ({_zz_357,{_zz_358,_zz_359}} != 3'b000); - assign _zz_349 = (_zz_360 != 1'b0); - assign _zz_350 = {(_zz_361 != _zz_362),{_zz_363,{_zz_364,_zz_365}}}; - assign _zz_351 = 32'h00007034; - assign _zz_352 = 32'h02007064; - assign _zz_353 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_354 = 32'h40001010; - assign _zz_355 = ((decode_INSTRUCTION & _zz_366) == 32'h00001010); - assign _zz_356 = ((decode_INSTRUCTION & _zz_367) == 32'h00001010); - assign _zz_357 = ((decode_INSTRUCTION & _zz_368) == 32'h00000024); - assign _zz_358 = (_zz_369 == _zz_370); - assign _zz_359 = (_zz_371 == _zz_372); - assign _zz_360 = ((decode_INSTRUCTION & _zz_373) == 32'h00001000); - assign _zz_361 = _zz_88; - assign _zz_362 = 1'b0; - assign _zz_363 = ({_zz_374,_zz_375} != 2'b00); - assign _zz_364 = (_zz_376 != _zz_377); - assign _zz_365 = {_zz_378,{_zz_379,_zz_380}}; - assign _zz_366 = 32'h00007034; - assign _zz_367 = 32'h02007054; - assign _zz_368 = 32'h00000064; - assign _zz_369 = (decode_INSTRUCTION & 32'h00003034); - assign _zz_370 = 32'h00001010; - assign _zz_371 = (decode_INSTRUCTION & 32'h02003054); - assign _zz_372 = 32'h00001010; - assign _zz_373 = 32'h00001000; - assign _zz_374 = ((decode_INSTRUCTION & _zz_381) == 32'h00002000); - assign _zz_375 = ((decode_INSTRUCTION & _zz_382) == 32'h00001000); - assign _zz_376 = {(_zz_383 == _zz_384),(_zz_385 == _zz_386)}; - assign _zz_377 = 2'b00; - assign _zz_378 = ({_zz_387,{_zz_388,_zz_389}} != 3'b000); - assign _zz_379 = (_zz_390 != 1'b0); - assign _zz_380 = {(_zz_391 != _zz_392),{_zz_393,{_zz_394,_zz_395}}}; - assign _zz_381 = 32'h00002010; - assign _zz_382 = 32'h00005000; - assign _zz_383 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_384 = 32'h00000020; - assign _zz_385 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_386 = 32'h00000020; - assign _zz_387 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); - assign _zz_388 = ((decode_INSTRUCTION & _zz_396) == 32'h0); - assign _zz_389 = ((decode_INSTRUCTION & _zz_397) == 32'h00000040); - assign _zz_390 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz_391 = ((decode_INSTRUCTION & _zz_398) == 32'h00000010); - assign _zz_392 = 1'b0; - assign _zz_393 = ({_zz_86,{_zz_399,_zz_400}} != 3'b000); - assign _zz_394 = ({_zz_401,_zz_402} != 6'h0); - assign _zz_395 = {(_zz_403 != _zz_404),{_zz_405,{_zz_406,_zz_407}}}; - assign _zz_396 = 32'h00000038; - assign _zz_397 = 32'h00403040; - assign _zz_398 = 32'h00000010; - assign _zz_399 = ((decode_INSTRUCTION & _zz_408) == 32'h00000010); - assign _zz_400 = ((decode_INSTRUCTION & _zz_409) == 32'h00000020); - assign _zz_401 = _zz_87; - assign _zz_402 = {(_zz_410 == _zz_411),{_zz_412,{_zz_413,_zz_414}}}; - assign _zz_403 = {_zz_86,(_zz_415 == _zz_416)}; - assign _zz_404 = 2'b00; - assign _zz_405 = ({_zz_86,_zz_417} != 2'b00); - assign _zz_406 = ({_zz_418,_zz_419} != 2'b00); - assign _zz_407 = {(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}; - assign _zz_408 = 32'h00000030; - assign _zz_409 = 32'h02000060; - assign _zz_410 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_411 = 32'h00001010; - assign _zz_412 = ((decode_INSTRUCTION & _zz_425) == 32'h00002010); - assign _zz_413 = (_zz_426 == _zz_427); - assign _zz_414 = {_zz_428,_zz_429}; - assign _zz_415 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_416 = 32'h00000020; - assign _zz_417 = ((decode_INSTRUCTION & _zz_430) == 32'h0); - assign _zz_418 = (_zz_431 == _zz_432); - assign _zz_419 = (_zz_433 == _zz_434); - assign _zz_420 = (_zz_435 == _zz_436); - assign _zz_421 = 1'b0; - assign _zz_422 = ({_zz_437,_zz_438} != 4'b0000); - assign _zz_423 = (_zz_439 != _zz_440); - assign _zz_424 = {_zz_441,{_zz_442,_zz_443}}; - assign _zz_425 = 32'h00002010; - assign _zz_426 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_427 = 32'h00000010; - assign _zz_428 = ((decode_INSTRUCTION & _zz_444) == 32'h00000004); - assign _zz_429 = ((decode_INSTRUCTION & _zz_445) == 32'h0); - assign _zz_430 = 32'h00000020; - assign _zz_431 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_432 = 32'h00006010; - assign _zz_433 = (decode_INSTRUCTION & 32'h00005014); - assign _zz_434 = 32'h00004010; - assign _zz_435 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_436 = 32'h00002010; - assign _zz_437 = (_zz_446 == _zz_447); - assign _zz_438 = {_zz_448,{_zz_449,_zz_450}}; - assign _zz_439 = (_zz_451 == _zz_452); - assign _zz_440 = 1'b0; - assign _zz_441 = ({_zz_453,_zz_454} != 3'b000); - assign _zz_442 = (_zz_455 != _zz_456); - assign _zz_443 = {_zz_457,_zz_458}; - assign _zz_444 = 32'h0000000c; - assign _zz_445 = 32'h00000028; - assign _zz_446 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_447 = 32'h0; - assign _zz_448 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); - assign _zz_449 = ((decode_INSTRUCTION & _zz_459) == 32'h00002000); - assign _zz_450 = ((decode_INSTRUCTION & _zz_460) == 32'h00001000); - assign _zz_451 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_452 = 32'h0; - assign _zz_453 = ((decode_INSTRUCTION & _zz_461) == 32'h00000040); - assign _zz_454 = {(_zz_462 == _zz_463),(_zz_464 == _zz_465)}; - assign _zz_455 = {(_zz_466 == _zz_467),_zz_85}; - assign _zz_456 = 2'b00; - assign _zz_457 = ({_zz_468,_zz_85} != 2'b00); - assign _zz_458 = ((_zz_469 == _zz_470) != 1'b0); - assign _zz_459 = 32'h00006004; - assign _zz_460 = 32'h00005004; - assign _zz_461 = 32'h00000044; - assign _zz_462 = (decode_INSTRUCTION & 32'h00002014); - assign _zz_463 = 32'h00002010; - assign _zz_464 = (decode_INSTRUCTION & 32'h40004034); - assign _zz_465 = 32'h40000030; - assign _zz_466 = (decode_INSTRUCTION & 32'h00000014); - assign _zz_467 = 32'h00000004; - assign _zz_468 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_469 = (decode_INSTRUCTION & 32'h00001048); - assign _zz_470 = 32'h00001008; - assign _zz_471 = execute_INSTRUCTION[31]; - assign _zz_472 = execute_INSTRUCTION[31]; - assign _zz_473 = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_296) begin - _zz_168 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_297) begin - _zz_169 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_39) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_when_1 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_decode_RS2_3 = (_zz__zz_decode_RS2_3_1 >>> 1); + assign _zz__zz_decode_RS2_3_1 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01); + assign _zz_memory_MulDivIterativePlugin_mul_counter_valueNext_1 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_mul_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_mul_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_accumulator = (_zz_memory_MulDivIterativePlugin_accumulator_1 + _zz_memory_MulDivIterativePlugin_accumulator_3); + assign _zz_memory_MulDivIterativePlugin_accumulator_2 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_memory_MulDivIterativePlugin_accumulator_1 = {{1{_zz_memory_MulDivIterativePlugin_accumulator_2[32]}}, _zz_memory_MulDivIterativePlugin_accumulator_2}; + assign _zz_memory_MulDivIterativePlugin_accumulator_4 = _zz_memory_MulDivIterativePlugin_accumulator_5; + assign _zz_memory_MulDivIterativePlugin_accumulator_3 = {{1{_zz_memory_MulDivIterativePlugin_accumulator_4[32]}}, _zz_memory_MulDivIterativePlugin_accumulator_4}; + assign _zz_memory_MulDivIterativePlugin_accumulator_5 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; + assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; + assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); + assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; + assign _zz_memory_MulDivIterativePlugin_rs1_4 = _zz_memory_MulDivIterativePlugin_rs1_1; + assign _zz_memory_MulDivIterativePlugin_rs1_3 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_4}; + assign _zz_memory_MulDivIterativePlugin_rs2_1 = _zz_memory_MulDivIterativePlugin_rs1; + assign _zz_memory_MulDivIterativePlugin_rs2 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_1}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005033),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbe00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00000033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_IS_DIV = 32'h02004064; + assign _zz__zz_decode_IS_DIV_1 = _zz_decode_IS_DIV_6; + assign _zz__zz_decode_IS_DIV_2 = {_zz_decode_IS_DIV_4,_zz_decode_IS_DIV_5}; + assign _zz__zz_decode_IS_DIV_3 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz__zz_decode_IS_DIV_4 = 1'b0; + assign _zz__zz_decode_IS_DIV_5 = (((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_6) == 32'h00000050) != 1'b0); + assign _zz__zz_decode_IS_DIV_7 = ((_zz__zz_decode_IS_DIV_8 == _zz__zz_decode_IS_DIV_9) != 1'b0); + assign _zz__zz_decode_IS_DIV_10 = {({_zz__zz_decode_IS_DIV_11,_zz__zz_decode_IS_DIV_13} != 2'b00),{(_zz__zz_decode_IS_DIV_15 != _zz__zz_decode_IS_DIV_18),{_zz__zz_decode_IS_DIV_19,{_zz__zz_decode_IS_DIV_22,_zz__zz_decode_IS_DIV_27}}}}; + assign _zz__zz_decode_IS_DIV_6 = 32'h10003050; + assign _zz__zz_decode_IS_DIV_8 = (decode_INSTRUCTION & 32'h10403050); + assign _zz__zz_decode_IS_DIV_9 = 32'h10000050; + assign _zz__zz_decode_IS_DIV_11 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_12) == 32'h00001050); + assign _zz__zz_decode_IS_DIV_13 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_14) == 32'h00002050); + assign _zz__zz_decode_IS_DIV_15 = {_zz_decode_IS_DIV_3,(_zz__zz_decode_IS_DIV_16 == _zz__zz_decode_IS_DIV_17)}; + assign _zz__zz_decode_IS_DIV_18 = 2'b00; + assign _zz__zz_decode_IS_DIV_19 = ((_zz__zz_decode_IS_DIV_20 == _zz__zz_decode_IS_DIV_21) != 1'b0); + assign _zz__zz_decode_IS_DIV_22 = ({_zz__zz_decode_IS_DIV_23,_zz__zz_decode_IS_DIV_25} != 2'b00); + assign _zz__zz_decode_IS_DIV_27 = {(_zz__zz_decode_IS_DIV_28 != _zz__zz_decode_IS_DIV_35),{_zz__zz_decode_IS_DIV_36,{_zz__zz_decode_IS_DIV_45,_zz__zz_decode_IS_DIV_48}}}; + assign _zz__zz_decode_IS_DIV_12 = 32'h00001050; + assign _zz__zz_decode_IS_DIV_14 = 32'h00002050; + assign _zz__zz_decode_IS_DIV_16 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz__zz_decode_IS_DIV_17 = 32'h00000004; + assign _zz__zz_decode_IS_DIV_20 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_IS_DIV_21 = 32'h00000040; + assign _zz__zz_decode_IS_DIV_23 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_24) == 32'h00005010); + assign _zz__zz_decode_IS_DIV_25 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_26) == 32'h00005020); + assign _zz__zz_decode_IS_DIV_28 = {(_zz__zz_decode_IS_DIV_29 == _zz__zz_decode_IS_DIV_30),{_zz__zz_decode_IS_DIV_31,_zz__zz_decode_IS_DIV_33}}; + assign _zz__zz_decode_IS_DIV_35 = 3'b000; + assign _zz__zz_decode_IS_DIV_36 = ({_zz__zz_decode_IS_DIV_37,{_zz__zz_decode_IS_DIV_39,_zz__zz_decode_IS_DIV_42}} != 3'b000); + assign _zz__zz_decode_IS_DIV_45 = (_zz__zz_decode_IS_DIV_46 != 1'b0); + assign _zz__zz_decode_IS_DIV_48 = {(_zz__zz_decode_IS_DIV_49 != _zz__zz_decode_IS_DIV_50),{_zz__zz_decode_IS_DIV_51,{_zz__zz_decode_IS_DIV_56,_zz__zz_decode_IS_DIV_63}}}; + assign _zz__zz_decode_IS_DIV_24 = 32'h00007034; + assign _zz__zz_decode_IS_DIV_26 = 32'h02007064; + assign _zz__zz_decode_IS_DIV_29 = (decode_INSTRUCTION & 32'h40003054); + assign _zz__zz_decode_IS_DIV_30 = 32'h40001010; + assign _zz__zz_decode_IS_DIV_31 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_32) == 32'h00001010); + assign _zz__zz_decode_IS_DIV_33 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_34) == 32'h00001010); + assign _zz__zz_decode_IS_DIV_37 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_38) == 32'h00000024); + assign _zz__zz_decode_IS_DIV_39 = (_zz__zz_decode_IS_DIV_40 == _zz__zz_decode_IS_DIV_41); + assign _zz__zz_decode_IS_DIV_42 = (_zz__zz_decode_IS_DIV_43 == _zz__zz_decode_IS_DIV_44); + assign _zz__zz_decode_IS_DIV_46 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_47) == 32'h00001000); + assign _zz__zz_decode_IS_DIV_49 = _zz_decode_IS_DIV_4; + assign _zz__zz_decode_IS_DIV_50 = 1'b0; + assign _zz__zz_decode_IS_DIV_51 = ({_zz__zz_decode_IS_DIV_52,_zz__zz_decode_IS_DIV_54} != 2'b00); + assign _zz__zz_decode_IS_DIV_56 = (_zz__zz_decode_IS_DIV_57 != _zz__zz_decode_IS_DIV_62); + assign _zz__zz_decode_IS_DIV_63 = {_zz__zz_decode_IS_DIV_64,{_zz__zz_decode_IS_DIV_70,_zz__zz_decode_IS_DIV_72}}; + assign _zz__zz_decode_IS_DIV_32 = 32'h00007034; + assign _zz__zz_decode_IS_DIV_34 = 32'h02007054; + assign _zz__zz_decode_IS_DIV_38 = 32'h00000064; + assign _zz__zz_decode_IS_DIV_40 = (decode_INSTRUCTION & 32'h00003034); + assign _zz__zz_decode_IS_DIV_41 = 32'h00001010; + assign _zz__zz_decode_IS_DIV_43 = (decode_INSTRUCTION & 32'h02003054); + assign _zz__zz_decode_IS_DIV_44 = 32'h00001010; + assign _zz__zz_decode_IS_DIV_47 = 32'h00001000; + assign _zz__zz_decode_IS_DIV_52 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_53) == 32'h00002000); + assign _zz__zz_decode_IS_DIV_54 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_55) == 32'h00001000); + assign _zz__zz_decode_IS_DIV_57 = {(_zz__zz_decode_IS_DIV_58 == _zz__zz_decode_IS_DIV_59),(_zz__zz_decode_IS_DIV_60 == _zz__zz_decode_IS_DIV_61)}; + assign _zz__zz_decode_IS_DIV_62 = 2'b00; + assign _zz__zz_decode_IS_DIV_64 = ({_zz__zz_decode_IS_DIV_65,{_zz__zz_decode_IS_DIV_66,_zz__zz_decode_IS_DIV_68}} != 3'b000); + assign _zz__zz_decode_IS_DIV_70 = (_zz__zz_decode_IS_DIV_71 != 1'b0); + assign _zz__zz_decode_IS_DIV_72 = {(_zz__zz_decode_IS_DIV_73 != _zz__zz_decode_IS_DIV_75),{_zz__zz_decode_IS_DIV_76,{_zz__zz_decode_IS_DIV_81,_zz__zz_decode_IS_DIV_96}}}; + assign _zz__zz_decode_IS_DIV_53 = 32'h00002010; + assign _zz__zz_decode_IS_DIV_55 = 32'h00005000; + assign _zz__zz_decode_IS_DIV_58 = (decode_INSTRUCTION & 32'h00000034); + assign _zz__zz_decode_IS_DIV_59 = 32'h00000020; + assign _zz__zz_decode_IS_DIV_60 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_IS_DIV_61 = 32'h00000020; + assign _zz__zz_decode_IS_DIV_65 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz__zz_decode_IS_DIV_66 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_67) == 32'h0); + assign _zz__zz_decode_IS_DIV_68 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_69) == 32'h00000040); + assign _zz__zz_decode_IS_DIV_71 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_73 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_74) == 32'h00000010); + assign _zz__zz_decode_IS_DIV_75 = 1'b0; + assign _zz__zz_decode_IS_DIV_76 = ({_zz_decode_IS_DIV_2,{_zz__zz_decode_IS_DIV_77,_zz__zz_decode_IS_DIV_79}} != 3'b000); + assign _zz__zz_decode_IS_DIV_81 = ({_zz__zz_decode_IS_DIV_82,_zz__zz_decode_IS_DIV_83} != 6'h0); + assign _zz__zz_decode_IS_DIV_96 = {(_zz__zz_decode_IS_DIV_97 != _zz__zz_decode_IS_DIV_100),{_zz__zz_decode_IS_DIV_101,{_zz__zz_decode_IS_DIV_104,_zz__zz_decode_IS_DIV_111}}}; + assign _zz__zz_decode_IS_DIV_67 = 32'h00000038; + assign _zz__zz_decode_IS_DIV_69 = 32'h00403040; + assign _zz__zz_decode_IS_DIV_74 = 32'h00000010; + assign _zz__zz_decode_IS_DIV_77 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_78) == 32'h00000010); + assign _zz__zz_decode_IS_DIV_79 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_80) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_82 = _zz_decode_IS_DIV_3; + assign _zz__zz_decode_IS_DIV_83 = {(_zz__zz_decode_IS_DIV_84 == _zz__zz_decode_IS_DIV_85),{_zz__zz_decode_IS_DIV_86,{_zz__zz_decode_IS_DIV_88,_zz__zz_decode_IS_DIV_91}}}; + assign _zz__zz_decode_IS_DIV_97 = {_zz_decode_IS_DIV_2,(_zz__zz_decode_IS_DIV_98 == _zz__zz_decode_IS_DIV_99)}; + assign _zz__zz_decode_IS_DIV_100 = 2'b00; + assign _zz__zz_decode_IS_DIV_101 = ({_zz_decode_IS_DIV_2,_zz__zz_decode_IS_DIV_102} != 2'b00); + assign _zz__zz_decode_IS_DIV_104 = ({_zz__zz_decode_IS_DIV_105,_zz__zz_decode_IS_DIV_108} != 2'b00); + assign _zz__zz_decode_IS_DIV_111 = {(_zz__zz_decode_IS_DIV_112 != _zz__zz_decode_IS_DIV_115),{_zz__zz_decode_IS_DIV_116,{_zz__zz_decode_IS_DIV_126,_zz__zz_decode_IS_DIV_131}}}; + assign _zz__zz_decode_IS_DIV_78 = 32'h00000030; + assign _zz__zz_decode_IS_DIV_80 = 32'h02000060; + assign _zz__zz_decode_IS_DIV_84 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_IS_DIV_85 = 32'h00001010; + assign _zz__zz_decode_IS_DIV_86 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_87) == 32'h00002010); + assign _zz__zz_decode_IS_DIV_88 = (_zz__zz_decode_IS_DIV_89 == _zz__zz_decode_IS_DIV_90); + assign _zz__zz_decode_IS_DIV_91 = {_zz__zz_decode_IS_DIV_92,_zz__zz_decode_IS_DIV_94}; + assign _zz__zz_decode_IS_DIV_98 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_IS_DIV_99 = 32'h00000020; + assign _zz__zz_decode_IS_DIV_102 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_103) == 32'h0); + assign _zz__zz_decode_IS_DIV_105 = (_zz__zz_decode_IS_DIV_106 == _zz__zz_decode_IS_DIV_107); + assign _zz__zz_decode_IS_DIV_108 = (_zz__zz_decode_IS_DIV_109 == _zz__zz_decode_IS_DIV_110); + assign _zz__zz_decode_IS_DIV_112 = (_zz__zz_decode_IS_DIV_113 == _zz__zz_decode_IS_DIV_114); + assign _zz__zz_decode_IS_DIV_115 = 1'b0; + assign _zz__zz_decode_IS_DIV_116 = ({_zz__zz_decode_IS_DIV_117,_zz__zz_decode_IS_DIV_120} != 4'b0000); + assign _zz__zz_decode_IS_DIV_126 = (_zz__zz_decode_IS_DIV_127 != _zz__zz_decode_IS_DIV_130); + assign _zz__zz_decode_IS_DIV_131 = {_zz__zz_decode_IS_DIV_132,{_zz__zz_decode_IS_DIV_140,_zz__zz_decode_IS_DIV_145}}; + assign _zz__zz_decode_IS_DIV_87 = 32'h00002010; + assign _zz__zz_decode_IS_DIV_89 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_DIV_90 = 32'h00000010; + assign _zz__zz_decode_IS_DIV_92 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_93) == 32'h00000004); + assign _zz__zz_decode_IS_DIV_94 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_95) == 32'h0); + assign _zz__zz_decode_IS_DIV_103 = 32'h00000020; + assign _zz__zz_decode_IS_DIV_106 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_IS_DIV_107 = 32'h00006010; + assign _zz__zz_decode_IS_DIV_109 = (decode_INSTRUCTION & 32'h00005014); + assign _zz__zz_decode_IS_DIV_110 = 32'h00004010; + assign _zz__zz_decode_IS_DIV_113 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_IS_DIV_114 = 32'h00002010; + assign _zz__zz_decode_IS_DIV_117 = (_zz__zz_decode_IS_DIV_118 == _zz__zz_decode_IS_DIV_119); + assign _zz__zz_decode_IS_DIV_120 = {_zz__zz_decode_IS_DIV_121,{_zz__zz_decode_IS_DIV_122,_zz__zz_decode_IS_DIV_124}}; + assign _zz__zz_decode_IS_DIV_127 = (_zz__zz_decode_IS_DIV_128 == _zz__zz_decode_IS_DIV_129); + assign _zz__zz_decode_IS_DIV_130 = 1'b0; + assign _zz__zz_decode_IS_DIV_132 = ({_zz__zz_decode_IS_DIV_133,_zz__zz_decode_IS_DIV_135} != 3'b000); + assign _zz__zz_decode_IS_DIV_140 = (_zz__zz_decode_IS_DIV_141 != _zz__zz_decode_IS_DIV_144); + assign _zz__zz_decode_IS_DIV_145 = {_zz__zz_decode_IS_DIV_146,_zz__zz_decode_IS_DIV_148}; + assign _zz__zz_decode_IS_DIV_93 = 32'h0000000c; + assign _zz__zz_decode_IS_DIV_95 = 32'h00000028; + assign _zz__zz_decode_IS_DIV_118 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_DIV_119 = 32'h0; + assign _zz__zz_decode_IS_DIV_121 = ((decode_INSTRUCTION & 32'h00000018) == 32'h0); + assign _zz__zz_decode_IS_DIV_122 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_123) == 32'h00002000); + assign _zz__zz_decode_IS_DIV_124 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_125) == 32'h00001000); + assign _zz__zz_decode_IS_DIV_128 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_IS_DIV_129 = 32'h0; + assign _zz__zz_decode_IS_DIV_133 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_134) == 32'h00000040); + assign _zz__zz_decode_IS_DIV_135 = {(_zz__zz_decode_IS_DIV_136 == _zz__zz_decode_IS_DIV_137),(_zz__zz_decode_IS_DIV_138 == _zz__zz_decode_IS_DIV_139)}; + assign _zz__zz_decode_IS_DIV_141 = {(_zz__zz_decode_IS_DIV_142 == _zz__zz_decode_IS_DIV_143),_zz_decode_IS_DIV_1}; + assign _zz__zz_decode_IS_DIV_144 = 2'b00; + assign _zz__zz_decode_IS_DIV_146 = ({_zz__zz_decode_IS_DIV_147,_zz_decode_IS_DIV_1} != 2'b00); + assign _zz__zz_decode_IS_DIV_148 = ((_zz__zz_decode_IS_DIV_149 == _zz__zz_decode_IS_DIV_150) != 1'b0); + assign _zz__zz_decode_IS_DIV_123 = 32'h00006004; + assign _zz__zz_decode_IS_DIV_125 = 32'h00005004; + assign _zz__zz_decode_IS_DIV_134 = 32'h00000044; + assign _zz__zz_decode_IS_DIV_136 = (decode_INSTRUCTION & 32'h00002014); + assign _zz__zz_decode_IS_DIV_137 = 32'h00002010; + assign _zz__zz_decode_IS_DIV_138 = (decode_INSTRUCTION & 32'h40004034); + assign _zz__zz_decode_IS_DIV_139 = 32'h40000030; + assign _zz__zz_decode_IS_DIV_142 = (decode_INSTRUCTION & 32'h00000014); + assign _zz__zz_decode_IS_DIV_143 = 32'h00000004; + assign _zz__zz_decode_IS_DIV_147 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_IS_DIV_149 = (decode_INSTRUCTION & 32'h00001048); + assign _zz__zz_decode_IS_DIV_150 = 32'h00001008; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_159 ), //i - .io_cpu_prefetch_isValid (_zz_160 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_161 ), //i - .io_cpu_fetch_isStuck (_zz_162 ), //i - .io_cpu_fetch_isRemoved (_zz_163 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_164 ), //i - .io_cpu_decode_isStuck (_zz_165 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_166 ), //i - .io_cpu_fill_valid (_zz_167 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_298) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) 2'b00 : begin - _zz_170 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_170 = DBusSimplePlugin_redoBranch_payload; - end - 2'b10 : begin - _zz_170 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_170 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_13) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_13_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_13_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_13_string = "AND_1"; - default : _zz_13_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_14) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; - default : _zz_14_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_16) - `Src2CtrlEnum_defaultEncoding_RS : _zz_16_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_16_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_16_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_16_string = "PC "; - default : _zz_16_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_17) - `Src2CtrlEnum_defaultEncoding_RS : _zz_17_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_17_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_17_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_17_string = "PC "; - default : _zz_17_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_19) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19_string = "BITWISE "; - default : _zz_19_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_20) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; - default : _zz_20_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_22) - `Src1CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_22_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_22_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_22_string = "URS1 "; - default : _zz_22_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_23) - `Src1CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_23_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_23_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_23_string = "URS1 "; - default : _zz_23_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_25) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_25_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_25_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25_string = "ECALL"; - default : _zz_25_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_26) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26_string = "ECALL"; - default : _zz_26_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_28) - `BranchCtrlEnum_defaultEncoding_INC : _zz_28_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_28_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_28_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_28_string = "JALR"; - default : _zz_28_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_31) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_31_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_31_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_31_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_31_string = "SRA_1 "; - default : _zz_31_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_33) - `Src2CtrlEnum_defaultEncoding_RS : _zz_33_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_33_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_33_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_33_string = "PC "; - default : _zz_33_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_34) - `Src1CtrlEnum_defaultEncoding_RS : _zz_34_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_34_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34_string = "URS1 "; - default : _zz_34_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_35) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_35_string = "BITWISE "; - default : _zz_35_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_36) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_36_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_36_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_36_string = "AND_1"; - default : _zz_36_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_40) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_40_string = "ECALL"; - default : _zz_40_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_41) - `BranchCtrlEnum_defaultEncoding_INC : _zz_41_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_41_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_41_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_41_string = "JALR"; - default : _zz_41_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_42) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_42_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_42_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_42_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_42_string = "SRA_1 "; - default : _zz_42_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_43) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; - default : _zz_43_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `Src2CtrlEnum_defaultEncoding_RS : _zz_44_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_44_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_44_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_44_string = "PC "; - default : _zz_44_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_45) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; - default : _zz_45_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_46) - `Src1CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_46_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_46_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_46_string = "URS1 "; - default : _zz_46_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_48) - `BranchCtrlEnum_defaultEncoding_INC : _zz_48_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_48_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_48_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_48_string = "JALR"; - default : _zz_48_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_91) - `Src1CtrlEnum_defaultEncoding_RS : _zz_91_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_91_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_91_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_91_string = "URS1 "; - default : _zz_91_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_92) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_92_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_92_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_92_string = "BITWISE "; - default : _zz_92_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_93) - `Src2CtrlEnum_defaultEncoding_RS : _zz_93_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_93_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_93_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_93_string = "PC "; - default : _zz_93_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_94) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_94_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_94_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_94_string = "AND_1"; - default : _zz_94_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_95) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_95_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_95_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_95_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_95_string = "SRA_1 "; - default : _zz_95_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_96) - `BranchCtrlEnum_defaultEncoding_INC : _zz_96_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_96_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_96_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_96_string = "JALR"; - default : _zz_96_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_97) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_97_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_97_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_97_string = "ECALL"; - default : _zz_97_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end @@ -2155,42 +2141,44 @@ module VexRiscv ( assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_99; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_DIV = _zz_210[0]; - assign decode_IS_RS2_SIGNED = _zz_211[0]; - assign decode_IS_RS1_SIGNED = _zz_212[0]; - assign decode_IS_MUL = _zz_213[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_214[0]; - assign _zz_8 = _zz_9; - assign decode_SHIFT_CTRL = _zz_10; - assign _zz_11 = _zz_12; - assign decode_ALU_BITWISE_CTRL = _zz_13; - assign _zz_14 = _zz_15; - assign decode_SRC_LESS_UNSIGNED = _zz_215[0]; - assign decode_MEMORY_STORE = _zz_216[0]; + assign decode_IS_DIV = _zz_decode_IS_DIV[30]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_DIV[29]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_DIV[28]; + assign decode_IS_MUL = _zz_decode_IS_DIV[27]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_DIV[24]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_DIV[16]; + assign decode_MEMORY_STORE = _zz_decode_IS_DIV[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_217[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_218[0]; - assign decode_SRC2_CTRL = _zz_16; - assign _zz_17 = _zz_18; - assign decode_ALU_CTRL = _zz_19; - assign _zz_20 = _zz_21; - assign decode_SRC1_CTRL = _zz_22; - assign _zz_23 = _zz_24; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_DIV[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_DIV[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_ENABLE = _zz_decode_IS_DIV[4]; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_MUL = decode_to_execute_IS_MUL; @@ -2200,27 +2188,27 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_25; - assign execute_ENV_CTRL = _zz_26; - assign writeBack_ENV_CTRL = _zz_27; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_120; - assign execute_BRANCH_CTRL = _zz_28; - assign decode_RS2_USE = _zz_219[0]; - assign decode_RS1_USE = _zz_220[0]; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_DIV[15]; + assign decode_RS1_USE = _zz_decode_IS_DIV[5]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - always @ (*) begin - _zz_29 = memory_REGFILE_WRITE_DATA; - if(_zz_171)begin - _zz_29 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + always @(*) begin + _zz_decode_RS2 = memory_REGFILE_WRITE_DATA; + if(when_MulDivIterativePlugin_l96) begin + _zz_decode_RS2 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_172)begin - _zz_29 = memory_MulDivIterativePlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2 = memory_MulDivIterativePlugin_div_result; end end @@ -2228,347 +2216,307 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_109)begin - if((_zz_110 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_111; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_173)begin - if(_zz_174)begin - if(_zz_113)begin - decode_RS2 = _zz_47; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_175)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_115)begin - decode_RS2 = _zz_29; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2; end end end - if(_zz_176)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_117)begin - decode_RS2 = _zz_30; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2_1; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_109)begin - if((_zz_110 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_111; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_173)begin - if(_zz_174)begin - if(_zz_112)begin - decode_RS1 = _zz_47; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_175)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_114)begin - decode_RS1 = _zz_29; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2; end end end - if(_zz_176)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_116)begin - decode_RS1 = _zz_30; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2_1; end end end end - always @ (*) begin - _zz_30 = execute_REGFILE_WRITE_DATA; - if(_zz_177)begin - _zz_30 = _zz_106; + always @(*) begin + _zz_decode_RS2_1 = execute_REGFILE_WRITE_DATA; + if(when_ShiftPlugins_l169) begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - if(_zz_178)begin - _zz_30 = execute_CsrPlugin_readData; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2_1 = CsrPlugin_csrMapping_readDataSignal; end end - assign execute_SHIFT_CTRL = _zz_31; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_32 = execute_PC; - assign execute_SRC2_CTRL = _zz_33; - assign execute_SRC1_CTRL = _zz_34; - assign decode_SRC_USE_SUB_LESS = _zz_221[0]; - assign decode_SRC_ADD_ZERO = _zz_222[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_DIV[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_DIV[19]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_35; - assign execute_SRC2 = _zz_105; - assign execute_SRC1 = _zz_100; - assign execute_ALU_BITWISE_CTRL = _zz_36; - assign _zz_37 = writeBack_INSTRUCTION; - assign _zz_38 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_39 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_39 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_223[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_DIV[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_299) == 32'h00001073),{(_zz_300 == _zz_301),{_zz_302,{_zz_303,_zz_304}}}}}}} != 20'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; - always @ (*) begin - _zz_47 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_47 = writeBack_DBusSimplePlugin_rspFormated; + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusSimplePlugin_l558) begin + _zz_decode_RS2_2 = writeBack_DBusSimplePlugin_rspFormated; end end assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; - assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; - assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; - assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; - assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; - assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; - assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; - assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; - assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; - assign memory_PC = execute_to_memory_PC; assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); - assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; - assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; - assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; - assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_224[0]; - assign decode_FLUSH_ALL = _zz_225[0]; - always @ (*) begin + assign decode_FLUSH_ALL = _zz_decode_IS_DIV[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_179)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_180)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_181)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_182)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_48; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_49 = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_49 = DBusSimplePlugin_redoBranch_payload; - end - if(BranchPlugin_jumpInterface_valid)begin - _zz_49 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_50 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_50 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin - decode_arbitration_haltItself = 1'b0; - if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin - decode_arbitration_haltItself = 1'b1; - end - end - - always @ (*) begin + assign decode_arbitration_haltItself = 1'b0; + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_107 || _zz_108)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_183)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_183)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_77)))begin + if(when_DBusSimplePlugin_l426) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_177)begin - if((! execute_LightShifterPlugin_done))begin + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l184) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_178)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end assign execute_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + if(when_DBusSimplePlugin_l479) begin memory_arbitration_haltItself = 1'b1; end - if(_zz_171)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + if(when_MulDivIterativePlugin_l96) begin + if(when_MulDivIterativePlugin_l97) begin memory_arbitration_haltItself = 1'b1; end - if(_zz_184)begin + if(when_MulDivIterativePlugin_l100) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_172)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_185)begin + if(_zz_when_1) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end - always @ (*) begin - memory_arbitration_flushIt = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(_zz_185)begin + if(_zz_when_1) begin memory_arbitration_flushNext = 1'b1; end end assign writeBack_arbitration_haltItself = 1'b0; assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end assign writeBack_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_186)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_187)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2577,45 +2525,47 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_186)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_187)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; assign CsrPlugin_inWfi = 1'b0; assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_186)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_187)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_186)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_187)begin - case(_zz_188) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2628,59 +2578,64 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_51 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; - assign _zz_52 = (_zz_51 & (~ _zz_226)); - assign _zz_53 = _zz_52[3]; - assign _zz_54 = (_zz_52[1] || _zz_53); - assign _zz_55 = (_zz_52[2] || _zz_53); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_170; - always @ (*) begin + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,IBusCachedPlugin_predictionJumpInterface_valid}} != 3'b000); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_228); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -2688,345 +2643,332 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_56 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_56); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_56); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_57 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_57); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_57); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_58 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_58); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_58); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_59; - assign _zz_59 = ((1'b0 && (! _zz_60)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_60 = _zz_61; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_60; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_62)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_62 = _zz_63; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_62; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_64; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_65 = _zz_229[11]; - always @ (*) begin - _zz_66[18] = _zz_65; - _zz_66[17] = _zz_65; - _zz_66[16] = _zz_65; - _zz_66[15] = _zz_65; - _zz_66[14] = _zz_65; - _zz_66[13] = _zz_65; - _zz_66[12] = _zz_65; - _zz_66[11] = _zz_65; - _zz_66[10] = _zz_65; - _zz_66[9] = _zz_65; - _zz_66[8] = _zz_65; - _zz_66[7] = _zz_65; - _zz_66[6] = _zz_65; - _zz_66[5] = _zz_65; - _zz_66[4] = _zz_65; - _zz_66[3] = _zz_65; - _zz_66[2] = _zz_65; - _zz_66[1] = _zz_65; - _zz_66[0] = _zz_65; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_230[31])); - if(_zz_71)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_67 = _zz_231[19]; - always @ (*) begin - _zz_68[10] = _zz_67; - _zz_68[9] = _zz_67; - _zz_68[8] = _zz_67; - _zz_68[7] = _zz_67; - _zz_68[6] = _zz_67; - _zz_68[5] = _zz_67; - _zz_68[4] = _zz_67; - _zz_68[3] = _zz_67; - _zz_68[2] = _zz_67; - _zz_68[1] = _zz_67; - _zz_68[0] = _zz_67; - end - - assign _zz_69 = _zz_232[11]; - always @ (*) begin - _zz_70[18] = _zz_69; - _zz_70[17] = _zz_69; - _zz_70[16] = _zz_69; - _zz_70[15] = _zz_69; - _zz_70[14] = _zz_69; - _zz_70[13] = _zz_69; - _zz_70[12] = _zz_69; - _zz_70[11] = _zz_69; - _zz_70[10] = _zz_69; - _zz_70[9] = _zz_69; - _zz_70[8] = _zz_69; - _zz_70[7] = _zz_69; - _zz_70[6] = _zz_69; - _zz_70[5] = _zz_69; - _zz_70[4] = _zz_69; - _zz_70[3] = _zz_69; - _zz_70[2] = _zz_69; - _zz_70[1] = _zz_69; - _zz_70[0] = _zz_69; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_71 = _zz_233[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_71 = _zz_234[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_72 = _zz_235[19]; - always @ (*) begin - _zz_73[10] = _zz_72; - _zz_73[9] = _zz_72; - _zz_73[8] = _zz_72; - _zz_73[7] = _zz_72; - _zz_73[6] = _zz_72; - _zz_73[5] = _zz_72; - _zz_73[4] = _zz_72; - _zz_73[3] = _zz_72; - _zz_73[2] = _zz_72; - _zz_73[1] = _zz_72; - _zz_73[0] = _zz_72; - end - - assign _zz_74 = _zz_236[11]; - always @ (*) begin - _zz_75[18] = _zz_74; - _zz_75[17] = _zz_74; - _zz_75[16] = _zz_74; - _zz_75[15] = _zz_74; - _zz_75[14] = _zz_74; - _zz_75[13] = _zz_74; - _zz_75[12] = _zz_74; - _zz_75[11] = _zz_74; - _zz_75[10] = _zz_74; - _zz_75[9] = _zz_74; - _zz_75[8] = _zz_74; - _zz_75[7] = _zz_74; - _zz_75[6] = _zz_74; - _zz_75[5] = _zz_74; - _zz_75[4] = _zz_74; - _zz_75[3] = _zz_74; - _zz_75[2] = _zz_74; - _zz_75[1] = _zz_74; - _zz_75[0] = _zz_74; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_73,{{{_zz_317,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_75,{{{_zz_318,_zz_319},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_160 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_161 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_162 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_161; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_164 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_165 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_166 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_182)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_180)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_167 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_180)begin - _zz_167 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_181)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_179)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_181)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_179)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_159 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign _zz_77 = 1'b0; - always @ (*) begin + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_dBus_cmd_valid = 1'b0; + always @(*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; - if(execute_ALIGNEMENT_FAULT)begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin + if(execute_ALIGNEMENT_FAULT) begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_77)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_78 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_dBus_cmd_payload_data = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_78 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_dBus_cmd_payload_data = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_78 = execute_RS2[31 : 0]; + _zz_dBus_cmd_payload_data = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_78; - always @ (*) begin + assign dBus_cmd_payload_data = _zz_dBus_cmd_payload_data; + assign when_DBusSimplePlugin_l426 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_79 = 4'b0001; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0001; end 2'b01 : begin - _zz_79 = 4'b0011; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0011; end default : begin - _zz_79 = 4'b1111; + _zz_execute_DBusSimplePlugin_formalMask = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_79 <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; - assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - always @ (*) begin + assign execute_DBusSimplePlugin_formalMask = (_zz_execute_DBusSimplePlugin_formalMask <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign when_DBusSimplePlugin_l479 = (((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)); + always @(*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_189)begin + if(when_DBusSimplePlugin_l486) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_ALIGNEMENT_FAULT)begin + if(memory_ALIGNEMENT_FAULT) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end else begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - end - if(_zz_190)begin + if(when_DBusSimplePlugin_l512) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end - always @ (*) begin + always @(*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_189)begin + if(when_DBusSimplePlugin_l486) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_237}; - end - if(! memory_MMU_RSP2_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); - end + if(memory_ALIGNEMENT_FAULT) begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_DBusSimplePlugin_memoryExceptionPort_payload_code}; end end assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; - always @ (*) begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_redoBranch_valid = 1'b1; - end - if(_zz_190)begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - end - end - - assign DBusSimplePlugin_redoBranch_payload = memory_PC; - always @ (*) begin + assign when_DBusSimplePlugin_l486 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign when_DBusSimplePlugin_l512 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + always @(*) begin writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin @@ -3043,63 +2985,64 @@ module VexRiscv ( endcase end - assign _zz_80 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_81[31] = _zz_80; - _zz_81[30] = _zz_80; - _zz_81[29] = _zz_80; - _zz_81[28] = _zz_80; - _zz_81[27] = _zz_80; - _zz_81[26] = _zz_80; - _zz_81[25] = _zz_80; - _zz_81[24] = _zz_80; - _zz_81[23] = _zz_80; - _zz_81[22] = _zz_80; - _zz_81[21] = _zz_80; - _zz_81[20] = _zz_80; - _zz_81[19] = _zz_80; - _zz_81[18] = _zz_80; - _zz_81[17] = _zz_80; - _zz_81[16] = _zz_80; - _zz_81[15] = _zz_80; - _zz_81[14] = _zz_80; - _zz_81[13] = _zz_80; - _zz_81[12] = _zz_80; - _zz_81[11] = _zz_80; - _zz_81[10] = _zz_80; - _zz_81[9] = _zz_80; - _zz_81[8] = _zz_80; - _zz_81[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_82 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_83[31] = _zz_82; - _zz_83[30] = _zz_82; - _zz_83[29] = _zz_82; - _zz_83[28] = _zz_82; - _zz_83[27] = _zz_82; - _zz_83[26] = _zz_82; - _zz_83[25] = _zz_82; - _zz_83[24] = _zz_82; - _zz_83[23] = _zz_82; - _zz_83[22] = _zz_82; - _zz_83[21] = _zz_82; - _zz_83[20] = _zz_82; - _zz_83[19] = _zz_82; - _zz_83[18] = _zz_82; - _zz_83[17] = _zz_82; - _zz_83[16] = _zz_82; - _zz_83[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_208) + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusSimplePlugin_rspFormated = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_1[31] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[30] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[29] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[28] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[27] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[26] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[25] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[24] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[23] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[22] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[21] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[20] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[19] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[18] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[17] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[16] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[15] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[14] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[13] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[12] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[11] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[10] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[9] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[8] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_writeBack_DBusSimplePlugin_rspFormated_2 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_3[31] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[30] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[29] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[28] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[27] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[26] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[25] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[24] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[23] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[22] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[21] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[20] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[19] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[18] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[17] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[16] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_81; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_83; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_3; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -3107,6 +3050,7 @@ module VexRiscv ( endcase end + assign when_DBusSimplePlugin_l558 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3116,70 +3060,62 @@ module VexRiscv ( assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_85 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_86 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_87 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_88 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_89 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); - assign _zz_90 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); - assign _zz_84 = {(((decode_INSTRUCTION & _zz_320) == 32'h02004020) != 1'b0),{({_zz_90,_zz_89} != 2'b00),{({_zz_321,_zz_322} != 3'b000),{(_zz_323 != _zz_324),{_zz_325,{_zz_326,_zz_327}}}}}}; - assign _zz_91 = _zz_84[2 : 1]; - assign _zz_46 = _zz_91; - assign _zz_92 = _zz_84[7 : 6]; - assign _zz_45 = _zz_92; - assign _zz_93 = _zz_84[9 : 8]; - assign _zz_44 = _zz_93; - assign _zz_94 = _zz_84[18 : 17]; - assign _zz_43 = _zz_94; - assign _zz_95 = _zz_84[21 : 20]; - assign _zz_42 = _zz_95; - assign _zz_96 = _zz_84[23 : 22]; - assign _zz_41 = _zz_96; - assign _zz_97 = _zz_84[26 : 25]; - assign _zz_40 = _zz_97; + assign _zz_decode_IS_DIV_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_DIV_2 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_DIV_3 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_DIV_4 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_decode_IS_DIV_5 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); + assign _zz_decode_IS_DIV_6 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); + assign _zz_decode_IS_DIV = {(((decode_INSTRUCTION & _zz__zz_decode_IS_DIV) == 32'h02004020) != 1'b0),{({_zz_decode_IS_DIV_6,_zz_decode_IS_DIV_5} != 2'b00),{({_zz__zz_decode_IS_DIV_1,_zz__zz_decode_IS_DIV_2} != 3'b000),{(_zz__zz_decode_IS_DIV_3 != _zz__zz_decode_IS_DIV_4),{_zz__zz_decode_IS_DIV_5,{_zz__zz_decode_IS_DIV_7,_zz__zz_decode_IS_DIV_10}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_DIV[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_DIV[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_DIV[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_DIV[18 : 17]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_DIV[21 : 20]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_DIV[23 : 22]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_DIV[26 : 25]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_168; - assign decode_RegFilePlugin_rs2Data = _zz_169; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); - if(_zz_98)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_37[11 : 7]; - if(_zz_98)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_47; - if(_zz_98)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3188,298 +3124,324 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_99 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_99 = {31'd0, _zz_238}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_99 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_100 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_100 = {29'd0, _zz_239}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_100 = {27'd0, _zz_240}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_101 = _zz_241[11]; - always @ (*) begin - _zz_102[19] = _zz_101; - _zz_102[18] = _zz_101; - _zz_102[17] = _zz_101; - _zz_102[16] = _zz_101; - _zz_102[15] = _zz_101; - _zz_102[14] = _zz_101; - _zz_102[13] = _zz_101; - _zz_102[12] = _zz_101; - _zz_102[11] = _zz_101; - _zz_102[10] = _zz_101; - _zz_102[9] = _zz_101; - _zz_102[8] = _zz_101; - _zz_102[7] = _zz_101; - _zz_102[6] = _zz_101; - _zz_102[5] = _zz_101; - _zz_102[4] = _zz_101; - _zz_102[3] = _zz_101; - _zz_102[2] = _zz_101; - _zz_102[1] = _zz_101; - _zz_102[0] = _zz_101; - end - - assign _zz_103 = _zz_242[11]; - always @ (*) begin - _zz_104[19] = _zz_103; - _zz_104[18] = _zz_103; - _zz_104[17] = _zz_103; - _zz_104[16] = _zz_103; - _zz_104[15] = _zz_103; - _zz_104[14] = _zz_103; - _zz_104[13] = _zz_103; - _zz_104[12] = _zz_103; - _zz_104[11] = _zz_103; - _zz_104[10] = _zz_103; - _zz_104[9] = _zz_103; - _zz_104[8] = _zz_103; - _zz_104[7] = _zz_103; - _zz_104[6] = _zz_103; - _zz_104[5] = _zz_103; - _zz_104[4] = _zz_103; - _zz_104[3] = _zz_103; - _zz_104[2] = _zz_103; - _zz_104[1] = _zz_103; - _zz_104[0] = _zz_103; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_105 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_105 = {_zz_104,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_105 = _zz_32; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_243; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_binary_sequential_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); - always @ (*) begin + assign when_ShiftPlugins_l169 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_106 = (execute_LightShifterPlugin_shiftInput <<< 1); + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_3 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_106 = _zz_250; + _zz_decode_RS2_3 = _zz__zz_decode_RS2_3; end endcase end - always @ (*) begin - _zz_107 = 1'b0; - if(_zz_191)begin - if(_zz_192)begin - if(_zz_112)begin - _zz_107 = 1'b1; + assign when_ShiftPlugins_l175 = (! execute_arbitration_isStuckByOthers); + assign when_ShiftPlugins_l184 = (! execute_LightShifterPlugin_done); + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_193)begin - if(_zz_194)begin - if(_zz_114)begin - _zz_107 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_195)begin - if(_zz_196)begin - if(_zz_116)begin - _zz_107 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_107 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_108 = 1'b0; - if(_zz_191)begin - if(_zz_192)begin - if(_zz_113)begin - _zz_108 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_193)begin - if(_zz_194)begin - if(_zz_115)begin - _zz_108 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_195)begin - if(_zz_196)begin - if(_zz_117)begin - _zz_108 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_108 = 1'b0; - end - end - - assign _zz_112 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_113 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_114 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_115 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_116 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_117 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_118 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_118 == 3'b000)) begin - _zz_119 = execute_BranchPlugin_eq; - end else if((_zz_118 == 3'b001)) begin - _zz_119 = (! execute_BranchPlugin_eq); - end else if((((_zz_118 & 3'b101) == 3'b101))) begin - _zz_119 = (! execute_SRC_LESS); - end else begin - _zz_119 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_120 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_120 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_120 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_120 = _zz_119; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_121 = _zz_252[11]; - always @ (*) begin - _zz_122[19] = _zz_121; - _zz_122[18] = _zz_121; - _zz_122[17] = _zz_121; - _zz_122[16] = _zz_121; - _zz_122[15] = _zz_121; - _zz_122[14] = _zz_121; - _zz_122[13] = _zz_121; - _zz_122[12] = _zz_121; - _zz_122[11] = _zz_121; - _zz_122[10] = _zz_121; - _zz_122[9] = _zz_121; - _zz_122[8] = _zz_121; - _zz_122[7] = _zz_121; - _zz_122[6] = _zz_121; - _zz_122[5] = _zz_121; - _zz_122[4] = _zz_121; - _zz_122[3] = _zz_121; - _zz_122[2] = _zz_121; - _zz_122[1] = _zz_121; - _zz_122[0] = _zz_121; - end - - assign _zz_123 = _zz_253[19]; - always @ (*) begin - _zz_124[10] = _zz_123; - _zz_124[9] = _zz_123; - _zz_124[8] = _zz_123; - _zz_124[7] = _zz_123; - _zz_124[6] = _zz_123; - _zz_124[5] = _zz_123; - _zz_124[4] = _zz_123; - _zz_124[3] = _zz_123; - _zz_124[2] = _zz_123; - _zz_124[1] = _zz_123; - _zz_124[0] = _zz_123; - end - - assign _zz_125 = _zz_254[11]; - always @ (*) begin - _zz_126[18] = _zz_125; - _zz_126[17] = _zz_125; - _zz_126[16] = _zz_125; - _zz_126[15] = _zz_125; - _zz_126[14] = _zz_125; - _zz_126[13] = _zz_125; - _zz_126[12] = _zz_125; - _zz_126[11] = _zz_125; - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_127 = (_zz_255[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_127 = _zz_256[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_127 = _zz_257[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_127); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -3488,80 +3450,80 @@ module VexRiscv ( endcase end - assign _zz_128 = _zz_258[11]; - always @ (*) begin - _zz_129[19] = _zz_128; - _zz_129[18] = _zz_128; - _zz_129[17] = _zz_128; - _zz_129[16] = _zz_128; - _zz_129[15] = _zz_128; - _zz_129[14] = _zz_128; - _zz_129[13] = _zz_128; - _zz_129[12] = _zz_128; - _zz_129[11] = _zz_128; - _zz_129[10] = _zz_128; - _zz_129[9] = _zz_128; - _zz_129[8] = _zz_128; - _zz_129[7] = _zz_128; - _zz_129[6] = _zz_128; - _zz_129[5] = _zz_128; - _zz_129[4] = _zz_128; - _zz_129[3] = _zz_128; - _zz_129[2] = _zz_128; - _zz_129[1] = _zz_128; - _zz_129[0] = _zz_128; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_129,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_131,{{{_zz_471,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_133,{{{_zz_472,_zz_473},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_261}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_130 = _zz_259[19]; - always @ (*) begin - _zz_131[10] = _zz_130; - _zz_131[9] = _zz_130; - _zz_131[8] = _zz_130; - _zz_131[7] = _zz_130; - _zz_131[6] = _zz_130; - _zz_131[5] = _zz_130; - _zz_131[4] = _zz_130; - _zz_131[3] = _zz_130; - _zz_131[2] = _zz_130; - _zz_131[1] = _zz_130; - _zz_131[0] = _zz_130; - end - - assign _zz_132 = _zz_260[11]; - always @ (*) begin - _zz_133[18] = _zz_132; - _zz_133[17] = _zz_132; - _zz_133[16] = _zz_132; - _zz_133[15] = _zz_132; - _zz_133[14] = _zz_132; - _zz_133[13] = _zz_132; - _zz_133[12] = _zz_132; - _zz_133[11] = _zz_132; - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -3571,94 +3533,108 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_134 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_135 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_136 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_137 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_138 = _zz_262[0]; - assign _zz_139 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_140 = _zz_264[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_183)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_185)begin + if(_zz_when_1) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -3669,8 +3645,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3680,72 +3656,79 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_197)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_198)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_198)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3758,134 +3741,206 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_197)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_197)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_209) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign memory_MulDivIterativePlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_171)begin - if(_zz_184)begin + if(when_MulDivIterativePlugin_l96) begin + if(when_MulDivIterativePlugin_l100) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l110) begin memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; end end assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); - always @ (*) begin - if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin + always @(*) begin + if(memory_MulDivIterativePlugin_mul_counter_willOverflow) begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_267); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_memory_MulDivIterativePlugin_mul_counter_valueNext); end - if(memory_MulDivIterativePlugin_mul_counter_willClear)begin + if(memory_MulDivIterativePlugin_mul_counter_willClear) begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end end - always @ (*) begin + assign when_MulDivIterativePlugin_l96 = (memory_arbitration_isValid && memory_IS_MUL); + assign when_MulDivIterativePlugin_l97 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign when_MulDivIterativePlugin_l100 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign when_MulDivIterativePlugin_l110 = (! memory_arbitration_isStuck); + always @(*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_172)begin - if(_zz_199)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_200)begin + if(when_MulDivIterativePlugin_l162) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_275); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); end - if(memory_MulDivIterativePlugin_div_counter_willClear)begin + if(memory_MulDivIterativePlugin_div_counter_willClear) begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end end - assign _zz_141 = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_141[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_276); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_277 : _zz_278); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_279[31:0]; - assign _zz_142 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_143 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_144 = ((execute_IS_MUL && _zz_143) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_145[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_145[31 : 0] = execute_RS1; - end - - assign _zz_147 = (_zz_146 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_147 != 32'h0); - assign _zz_24 = decode_SRC1_CTRL; - assign _zz_22 = _zz_46; - assign _zz_34 = decode_to_execute_SRC1_CTRL; - assign _zz_21 = decode_ALU_CTRL; - assign _zz_19 = _zz_45; - assign _zz_35 = decode_to_execute_ALU_CTRL; - assign _zz_18 = decode_SRC2_CTRL; - assign _zz_16 = _zz_44; - assign _zz_33 = decode_to_execute_SRC2_CTRL; - assign _zz_15 = decode_ALU_BITWISE_CTRL; - assign _zz_13 = _zz_43; - assign _zz_36 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_12 = decode_SHIFT_CTRL; - assign _zz_10 = _zz_42; - assign _zz_31 = decode_to_execute_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_48 = _zz_41; - assign _zz_28 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_40; - assign _zz_26 = decode_to_execute_ENV_CTRL; - assign _zz_25 = execute_to_memory_ENV_CTRL; - assign _zz_27 = memory_to_writeBack_ENV_CTRL; + assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_MulDivIterativePlugin_rs1 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_MulDivIterativePlugin_rs1_1 = ((execute_IS_MUL && _zz_memory_MulDivIterativePlugin_rs1) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_MulDivIterativePlugin_rs1_2[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_MulDivIterativePlugin_rs1_2[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_31 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_32 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_48 = ((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)); + assign when_Pipeline_l124_49 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -3906,124 +3961,144 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_148 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_148[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_148[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_148[3 : 3] = CsrPlugin_mstatus_MIE; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_149 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_149[11 : 11] = CsrPlugin_mip_MEIP; - _zz_149[7 : 7] = CsrPlugin_mip_MTIP; - _zz_149[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_150 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_150[11 : 11] = CsrPlugin_mie_MEIE; - _zz_150[7 : 7] = CsrPlugin_mie_MTIE; - _zz_150[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_151 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_151[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_152 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_152[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_152[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_153 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_153[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_154 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_154[31 : 0] = _zz_146; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_155 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_155[31 : 0] = _zz_147; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = (((_zz_148 | _zz_149) | (_zz_150 | _zz_151)) | ((_zz_152 | _zz_153) | (_zz_154 | _zz_155))); - assign iBusWishbone_ADR = {_zz_295,_zz_156}; - assign iBusWishbone_CTI = ((_zz_156 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_201)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_201)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_157; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; - assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; - assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; - assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; - assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; - assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBus_cmd_halfPipe_fire = (dBus_cmd_halfPipe_valid && dBus_cmd_halfPipe_ready); + assign dBus_cmd_ready = (! dBus_cmd_rValid); + assign dBus_cmd_halfPipe_valid = dBus_cmd_rValid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_rData_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_rData_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_rData_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_rData_size; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); assign dBusWishbone_CTI = 3'b000; assign dBusWishbone_BTE = 2'b00; - always @ (*) begin + always @(*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_158 = 4'b0001; + _zz_dBusWishbone_SEL = 4'b0001; end 2'b01 : begin - _zz_158 = 4'b0011; + _zz_dBusWishbone_SEL = 4'b0011; end default : begin - _zz_158 = 4'b1111; + _zz_dBusWishbone_SEL = 4'b1111; end endcase end - always @ (*) begin - dBusWishbone_SEL = (_zz_158 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - if((! dBus_cmd_halfPipe_payload_wr))begin + always @(*) begin + dBusWishbone_SEL = (_zz_dBusWishbone_SEL <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + if(when_DBusSimplePlugin_l189) begin dBusWishbone_SEL = 4'b1111; end end + assign when_DBusSimplePlugin_l189 = (! dBus_cmd_halfPipe_payload_wr); assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); @@ -4032,24 +4107,24 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_61 <= 1'b0; - _zz_63 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_76; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; - _zz_98 <= 1'b1; + _zz_7 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_109 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -4068,89 +4143,88 @@ module VexRiscv ( execute_CsrPlugin_wfiWake <= 1'b0; memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - _zz_146 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_156 <= 3'b000; - _zz_157 <= 1'b0; - dBus_cmd_halfPipe_regs_valid <= 1'b0; - dBus_cmd_halfPipe_regs_ready <= 1'b1; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + dBus_cmd_rValid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_61 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_59)begin - _zz_61 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_63 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_63 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end `ifndef SYNTHESIS @@ -4173,72 +4247,72 @@ module VexRiscv ( end `endif `endif - _zz_98 <= 1'b0; - if(_zz_177)begin - if(_zz_202)begin + _zz_7 <= 1'b0; + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l175) begin execute_LightShifterPlugin_isActive <= 1'b1; - if(execute_LightShifterPlugin_done)begin + if(execute_LightShifterPlugin_done) begin execute_LightShifterPlugin_isActive <= 1'b0; end end end - if(execute_arbitration_removeIt)begin + if(execute_arbitration_removeIt) begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_109 <= (_zz_38 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_203)begin - if(_zz_204)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_205)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_206)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_186)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4249,8 +4323,8 @@ module VexRiscv ( end endcase end - if(_zz_187)begin - case(_zz_188) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4260,119 +4334,118 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_136,{_zz_135,_zz_134}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_289[0]; - CsrPlugin_mstatus_MIE <= _zz_290[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_292[0]; - CsrPlugin_mie_MTIE <= _zz_293[0]; - CsrPlugin_mie_MSIE <= _zz_294[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_201)begin - if(iBusWishbone_ACK)begin - _zz_156 <= (_zz_156 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_157 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_207)begin - dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; - dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); - end else begin - dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); - dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(dBus_cmd_valid) begin + dBus_cmd_rValid <= 1'b1; + end + if(dBus_cmd_halfPipe_fire) begin + dBus_cmd_rValid <= 1'b0; end end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_64 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_177)begin - if(_zz_202)begin + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l175) begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - _zz_110 <= _zz_37[11 : 7]; - _zz_111 <= _zz_47; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_183)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_138 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_138 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_185)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_140 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_140 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_when_1) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_203)begin - if(_zz_204)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_205)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_206)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_186)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -4380,256 +4453,242 @@ module VexRiscv ( end endcase end - if(_zz_171)begin - if(_zz_184)begin + if(when_MulDivIterativePlugin_l96) begin + if(when_MulDivIterativePlugin_l100) begin memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_268,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_memory_MulDivIterativePlugin_accumulator,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end - if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_MulDivIterativePlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_MulDivIterativePlugin_div_done <= 1'b0; end - if(_zz_172)begin - if(_zz_199)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; - if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_result <= _zz_280[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; end end end - if(_zz_200)begin + if(when_MulDivIterativePlugin_l162) begin memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_144 ? (~ _zz_145) : _zz_145) + _zz_286); - memory_MulDivIterativePlugin_rs2 <= ((_zz_143 ? (~ execute_RS2) : execute_RS2) + _zz_288); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_144 ^ (_zz_143 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1_1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_2) : _zz_memory_MulDivIterativePlugin_rs1_2) + _zz_memory_MulDivIterativePlugin_rs1_3); + memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1_1 ^ (_zz_memory_MulDivIterativePlugin_rs1 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_32; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_50; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_7) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_49; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_23; + if(when_Pipeline_l124_9) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_10) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_20; + if(when_Pipeline_l124_14) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_17; + if(when_Pipeline_l124_15) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_16) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_14; + if(when_Pipeline_l124_26) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_11; + if(when_Pipeline_l124_27) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + if(when_Pipeline_l124_28) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_29) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_30) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_31) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_32) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_33) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_34) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_35) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; + if(when_Pipeline_l124_48) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; - execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; - execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; - execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; - execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; - execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; - execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; - execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; - execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + if(when_Pipeline_l124_49) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_30; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_29; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_52) begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_291[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_207)begin - dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; - dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; - dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; - dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + if(dBus_cmd_ready) begin + dBus_cmd_rData_wr <= dBus_cmd_payload_wr; + dBus_cmd_rData_address <= dBus_cmd_payload_address; + dBus_cmd_rData_data <= dBus_cmd_payload_data; + dBus_cmd_rData_size <= dBus_cmd_payload_size; end end @@ -4678,13 +4737,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [22:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [22:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [22:0] _zz_ways_0_tags_port1; + wire [22:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -4693,8 +4748,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [6:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -4708,22 +4768,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [8:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_6; - wire _zz_7; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8; + wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -4733,82 +4796,85 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_11 = (! lineLoader_flushCounter[6]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -4824,30 +4890,35 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -4855,51 +4926,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[6]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 7'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -4910,10 +4981,10 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v index 92696e4..b13e65a 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v @@ -1,46 +1,46 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b10 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -81,18 +81,17 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_161; - wire _zz_162; - wire _zz_163; - wire _zz_164; - wire _zz_165; - wire _zz_166; - wire _zz_167; - wire _zz_168; - reg _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -105,313 +104,249 @@ module VexRiscv ( wire IBusCachedPlugin_cache_io_mem_cmd_valid; wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; - wire _zz_173; - wire _zz_174; - wire _zz_175; - wire _zz_176; - wire _zz_177; - wire _zz_178; - wire _zz_179; - wire _zz_180; - wire _zz_181; - wire _zz_182; - wire _zz_183; - wire _zz_184; - wire _zz_185; - wire _zz_186; - wire _zz_187; - wire _zz_188; - wire _zz_189; - wire _zz_190; - wire _zz_191; - wire _zz_192; - wire [1:0] _zz_193; - wire _zz_194; - wire _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - wire _zz_204; - wire _zz_205; - wire [5:0] _zz_206; - wire _zz_207; - wire _zz_208; - wire _zz_209; - wire _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire [1:0] _zz_214; - wire _zz_215; - wire [0:0] _zz_216; - wire [0:0] _zz_217; - wire [0:0] _zz_218; - wire [0:0] _zz_219; - wire [0:0] _zz_220; - wire [0:0] _zz_221; - wire [0:0] _zz_222; - wire [0:0] _zz_223; - wire [0:0] _zz_224; - wire [0:0] _zz_225; - wire [0:0] _zz_226; - wire [0:0] _zz_227; - wire [0:0] _zz_228; - wire [0:0] _zz_229; - wire [0:0] _zz_230; - wire [0:0] _zz_231; - wire [0:0] _zz_232; - wire [3:0] _zz_233; - wire [2:0] _zz_234; - wire [31:0] _zz_235; - wire [11:0] _zz_236; - wire [31:0] _zz_237; - wire [19:0] _zz_238; - wire [11:0] _zz_239; - wire [31:0] _zz_240; - wire [31:0] _zz_241; - wire [19:0] _zz_242; - wire [11:0] _zz_243; - wire [2:0] _zz_244; - wire [0:0] _zz_245; - wire [2:0] _zz_246; - wire [4:0] _zz_247; - wire [11:0] _zz_248; - wire [11:0] _zz_249; - wire [31:0] _zz_250; - wire [31:0] _zz_251; - wire [31:0] _zz_252; - wire [31:0] _zz_253; - wire [31:0] _zz_254; - wire [31:0] _zz_255; - wire [31:0] _zz_256; - wire [31:0] _zz_257; - wire [32:0] _zz_258; - wire [11:0] _zz_259; - wire [19:0] _zz_260; - wire [11:0] _zz_261; - wire [31:0] _zz_262; - wire [31:0] _zz_263; - wire [31:0] _zz_264; - wire [11:0] _zz_265; - wire [19:0] _zz_266; - wire [11:0] _zz_267; - wire [2:0] _zz_268; - wire [1:0] _zz_269; - wire [1:0] _zz_270; - wire [1:0] _zz_271; - wire [1:0] _zz_272; - wire [0:0] _zz_273; - wire [5:0] _zz_274; - wire [33:0] _zz_275; - wire [32:0] _zz_276; - wire [33:0] _zz_277; - wire [32:0] _zz_278; - wire [33:0] _zz_279; - wire [32:0] _zz_280; - wire [0:0] _zz_281; - wire [5:0] _zz_282; - wire [32:0] _zz_283; - wire [31:0] _zz_284; - wire [31:0] _zz_285; - wire [32:0] _zz_286; - wire [32:0] _zz_287; - wire [32:0] _zz_288; - wire [32:0] _zz_289; - wire [0:0] _zz_290; - wire [32:0] _zz_291; - wire [0:0] _zz_292; - wire [32:0] _zz_293; - wire [0:0] _zz_294; - wire [31:0] _zz_295; - wire [0:0] _zz_296; - wire [0:0] _zz_297; - wire [0:0] _zz_298; - wire [0:0] _zz_299; - wire [0:0] _zz_300; - wire [0:0] _zz_301; - wire [26:0] _zz_302; - wire _zz_303; - wire _zz_304; - wire [1:0] _zz_305; - wire [31:0] _zz_306; - wire [31:0] _zz_307; - wire [31:0] _zz_308; - wire _zz_309; - wire [0:0] _zz_310; - wire [12:0] _zz_311; - wire [31:0] _zz_312; - wire [31:0] _zz_313; - wire [31:0] _zz_314; - wire _zz_315; - wire [0:0] _zz_316; - wire [6:0] _zz_317; - wire [31:0] _zz_318; - wire [31:0] _zz_319; - wire [31:0] _zz_320; - wire _zz_321; - wire [0:0] _zz_322; - wire [0:0] _zz_323; - wire _zz_324; - wire _zz_325; - wire _zz_326; - wire [31:0] _zz_327; - wire [31:0] _zz_328; - wire [31:0] _zz_329; - wire [0:0] _zz_330; - wire [0:0] _zz_331; - wire [2:0] _zz_332; - wire [2:0] _zz_333; - wire _zz_334; - wire [0:0] _zz_335; - wire [25:0] _zz_336; - wire [31:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire _zz_340; - wire [1:0] _zz_341; - wire [1:0] _zz_342; - wire _zz_343; - wire [0:0] _zz_344; - wire [21:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; - wire [31:0] _zz_349; - wire _zz_350; - wire _zz_351; - wire [1:0] _zz_352; - wire [1:0] _zz_353; - wire _zz_354; - wire [0:0] _zz_355; - wire [18:0] _zz_356; - wire [31:0] _zz_357; - wire [31:0] _zz_358; - wire [31:0] _zz_359; - wire [31:0] _zz_360; - wire _zz_361; - wire [0:0] _zz_362; - wire [0:0] _zz_363; - wire [0:0] _zz_364; - wire [1:0] _zz_365; - wire [0:0] _zz_366; - wire [0:0] _zz_367; - wire _zz_368; - wire [0:0] _zz_369; - wire [15:0] _zz_370; - wire [31:0] _zz_371; - wire [31:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire [31:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire _zz_378; - wire _zz_379; - wire [31:0] _zz_380; - wire [31:0] _zz_381; - wire [1:0] _zz_382; - wire [1:0] _zz_383; - wire _zz_384; - wire [0:0] _zz_385; - wire [13:0] _zz_386; - wire [31:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire _zz_391; - wire _zz_392; - wire [0:0] _zz_393; - wire [1:0] _zz_394; - wire [0:0] _zz_395; - wire [0:0] _zz_396; - wire _zz_397; - wire [0:0] _zz_398; - wire [10:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire [31:0] _zz_405; - wire [31:0] _zz_406; - wire [31:0] _zz_407; - wire [0:0] _zz_408; - wire [1:0] _zz_409; - wire [5:0] _zz_410; - wire [5:0] _zz_411; - wire _zz_412; - wire [0:0] _zz_413; - wire [7:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; - wire [31:0] _zz_418; - wire _zz_419; - wire [0:0] _zz_420; - wire [2:0] _zz_421; - wire _zz_422; - wire [0:0] _zz_423; - wire [0:0] _zz_424; - wire [1:0] _zz_425; - wire [1:0] _zz_426; - wire _zz_427; - wire [0:0] _zz_428; - wire [4:0] _zz_429; - wire [31:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire _zz_433; - wire [0:0] _zz_434; - wire [0:0] _zz_435; - wire [31:0] _zz_436; - wire [31:0] _zz_437; - wire [31:0] _zz_438; - wire _zz_439; - wire _zz_440; - wire _zz_441; - wire [3:0] _zz_442; - wire [3:0] _zz_443; - wire _zz_444; - wire [0:0] _zz_445; - wire [2:0] _zz_446; - wire [31:0] _zz_447; - wire [31:0] _zz_448; - wire [31:0] _zz_449; - wire [31:0] _zz_450; - wire [31:0] _zz_451; - wire [31:0] _zz_452; - wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire _zz_455; - wire [0:0] _zz_456; - wire [1:0] _zz_457; - wire _zz_458; - wire [2:0] _zz_459; - wire [2:0] _zz_460; - wire _zz_461; - wire [0:0] _zz_462; - wire [0:0] _zz_463; - wire [31:0] _zz_464; - wire [31:0] _zz_465; - wire [31:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire _zz_471; - wire _zz_472; - wire _zz_473; - wire [0:0] _zz_474; - wire [0:0] _zz_475; - wire _zz_476; - wire _zz_477; - wire _zz_478; - wire _zz_479; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [12:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [6:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [2:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] _zz__zz_decode_IS_DIV; + wire [31:0] _zz__zz_decode_IS_DIV_1; + wire [31:0] _zz__zz_decode_IS_DIV_2; + wire [0:0] _zz__zz_decode_IS_DIV_3; + wire [0:0] _zz__zz_decode_IS_DIV_4; + wire [2:0] _zz__zz_decode_IS_DIV_5; + wire [2:0] _zz__zz_decode_IS_DIV_6; + wire _zz__zz_decode_IS_DIV_7; + wire [31:0] _zz__zz_decode_IS_DIV_8; + wire [0:0] _zz__zz_decode_IS_DIV_9; + wire [31:0] _zz__zz_decode_IS_DIV_10; + wire [31:0] _zz__zz_decode_IS_DIV_11; + wire [25:0] _zz__zz_decode_IS_DIV_12; + wire _zz__zz_decode_IS_DIV_13; + wire [1:0] _zz__zz_decode_IS_DIV_14; + wire [31:0] _zz__zz_decode_IS_DIV_15; + wire [31:0] _zz__zz_decode_IS_DIV_16; + wire [31:0] _zz__zz_decode_IS_DIV_17; + wire [31:0] _zz__zz_decode_IS_DIV_18; + wire [1:0] _zz__zz_decode_IS_DIV_19; + wire _zz__zz_decode_IS_DIV_20; + wire _zz__zz_decode_IS_DIV_21; + wire [0:0] _zz__zz_decode_IS_DIV_22; + wire _zz__zz_decode_IS_DIV_23; + wire [21:0] _zz__zz_decode_IS_DIV_24; + wire [1:0] _zz__zz_decode_IS_DIV_25; + wire [31:0] _zz__zz_decode_IS_DIV_26; + wire [31:0] _zz__zz_decode_IS_DIV_27; + wire [31:0] _zz__zz_decode_IS_DIV_28; + wire [31:0] _zz__zz_decode_IS_DIV_29; + wire [1:0] _zz__zz_decode_IS_DIV_30; + wire _zz__zz_decode_IS_DIV_31; + wire _zz__zz_decode_IS_DIV_32; + wire [31:0] _zz__zz_decode_IS_DIV_33; + wire [0:0] _zz__zz_decode_IS_DIV_34; + wire [31:0] _zz__zz_decode_IS_DIV_35; + wire [31:0] _zz__zz_decode_IS_DIV_36; + wire [0:0] _zz__zz_decode_IS_DIV_37; + wire [31:0] _zz__zz_decode_IS_DIV_38; + wire [31:0] _zz__zz_decode_IS_DIV_39; + wire [0:0] _zz__zz_decode_IS_DIV_40; + wire [0:0] _zz__zz_decode_IS_DIV_41; + wire [31:0] _zz__zz_decode_IS_DIV_42; + wire [31:0] _zz__zz_decode_IS_DIV_43; + wire [1:0] _zz__zz_decode_IS_DIV_44; + wire _zz__zz_decode_IS_DIV_45; + wire _zz__zz_decode_IS_DIV_46; + wire [18:0] _zz__zz_decode_IS_DIV_47; + wire [0:0] _zz__zz_decode_IS_DIV_48; + wire [31:0] _zz__zz_decode_IS_DIV_49; + wire [31:0] _zz__zz_decode_IS_DIV_50; + wire [0:0] _zz__zz_decode_IS_DIV_51; + wire _zz__zz_decode_IS_DIV_52; + wire [0:0] _zz__zz_decode_IS_DIV_53; + wire [1:0] _zz__zz_decode_IS_DIV_54; + wire [31:0] _zz__zz_decode_IS_DIV_55; + wire [31:0] _zz__zz_decode_IS_DIV_56; + wire [31:0] _zz__zz_decode_IS_DIV_57; + wire [31:0] _zz__zz_decode_IS_DIV_58; + wire [1:0] _zz__zz_decode_IS_DIV_59; + wire [15:0] _zz__zz_decode_IS_DIV_60; + wire _zz__zz_decode_IS_DIV_61; + wire _zz__zz_decode_IS_DIV_62; + wire _zz__zz_decode_IS_DIV_63; + wire [0:0] _zz__zz_decode_IS_DIV_64; + wire [0:0] _zz__zz_decode_IS_DIV_65; + wire [31:0] _zz__zz_decode_IS_DIV_66; + wire [1:0] _zz__zz_decode_IS_DIV_67; + wire [31:0] _zz__zz_decode_IS_DIV_68; + wire [31:0] _zz__zz_decode_IS_DIV_69; + wire [31:0] _zz__zz_decode_IS_DIV_70; + wire [31:0] _zz__zz_decode_IS_DIV_71; + wire [13:0] _zz__zz_decode_IS_DIV_72; + wire [0:0] _zz__zz_decode_IS_DIV_73; + wire [31:0] _zz__zz_decode_IS_DIV_74; + wire [0:0] _zz__zz_decode_IS_DIV_75; + wire _zz__zz_decode_IS_DIV_76; + wire [31:0] _zz__zz_decode_IS_DIV_77; + wire [31:0] _zz__zz_decode_IS_DIV_78; + wire [0:0] _zz__zz_decode_IS_DIV_79; + wire [0:0] _zz__zz_decode_IS_DIV_80; + wire [1:0] _zz__zz_decode_IS_DIV_81; + wire [31:0] _zz__zz_decode_IS_DIV_82; + wire [31:0] _zz__zz_decode_IS_DIV_83; + wire [31:0] _zz__zz_decode_IS_DIV_84; + wire [31:0] _zz__zz_decode_IS_DIV_85; + wire [10:0] _zz__zz_decode_IS_DIV_86; + wire [5:0] _zz__zz_decode_IS_DIV_87; + wire _zz__zz_decode_IS_DIV_88; + wire [31:0] _zz__zz_decode_IS_DIV_89; + wire [0:0] _zz__zz_decode_IS_DIV_90; + wire [31:0] _zz__zz_decode_IS_DIV_91; + wire [31:0] _zz__zz_decode_IS_DIV_92; + wire [2:0] _zz__zz_decode_IS_DIV_93; + wire _zz__zz_decode_IS_DIV_94; + wire [31:0] _zz__zz_decode_IS_DIV_95; + wire [0:0] _zz__zz_decode_IS_DIV_96; + wire [31:0] _zz__zz_decode_IS_DIV_97; + wire [31:0] _zz__zz_decode_IS_DIV_98; + wire [0:0] _zz__zz_decode_IS_DIV_99; + wire [31:0] _zz__zz_decode_IS_DIV_100; + wire [31:0] _zz__zz_decode_IS_DIV_101; + wire [5:0] _zz__zz_decode_IS_DIV_102; + wire _zz__zz_decode_IS_DIV_103; + wire _zz__zz_decode_IS_DIV_104; + wire [31:0] _zz__zz_decode_IS_DIV_105; + wire [0:0] _zz__zz_decode_IS_DIV_106; + wire [0:0] _zz__zz_decode_IS_DIV_107; + wire [0:0] _zz__zz_decode_IS_DIV_108; + wire [31:0] _zz__zz_decode_IS_DIV_109; + wire [31:0] _zz__zz_decode_IS_DIV_110; + wire [7:0] _zz__zz_decode_IS_DIV_111; + wire [1:0] _zz__zz_decode_IS_DIV_112; + wire _zz__zz_decode_IS_DIV_113; + wire [31:0] _zz__zz_decode_IS_DIV_114; + wire _zz__zz_decode_IS_DIV_115; + wire [31:0] _zz__zz_decode_IS_DIV_116; + wire [1:0] _zz__zz_decode_IS_DIV_117; + wire _zz__zz_decode_IS_DIV_118; + wire _zz__zz_decode_IS_DIV_119; + wire [31:0] _zz__zz_decode_IS_DIV_120; + wire [0:0] _zz__zz_decode_IS_DIV_121; + wire [3:0] _zz__zz_decode_IS_DIV_122; + wire _zz__zz_decode_IS_DIV_123; + wire [0:0] _zz__zz_decode_IS_DIV_124; + wire [31:0] _zz__zz_decode_IS_DIV_125; + wire [1:0] _zz__zz_decode_IS_DIV_126; + wire [31:0] _zz__zz_decode_IS_DIV_127; + wire [31:0] _zz__zz_decode_IS_DIV_128; + wire [31:0] _zz__zz_decode_IS_DIV_129; + wire [31:0] _zz__zz_decode_IS_DIV_130; + wire [3:0] _zz__zz_decode_IS_DIV_131; + wire [4:0] _zz__zz_decode_IS_DIV_132; + wire _zz__zz_decode_IS_DIV_133; + wire _zz__zz_decode_IS_DIV_134; + wire [0:0] _zz__zz_decode_IS_DIV_135; + wire [2:0] _zz__zz_decode_IS_DIV_136; + wire [31:0] _zz__zz_decode_IS_DIV_137; + wire [31:0] _zz__zz_decode_IS_DIV_138; + wire _zz__zz_decode_IS_DIV_139; + wire _zz__zz_decode_IS_DIV_140; + wire [2:0] _zz__zz_decode_IS_DIV_141; + wire [2:0] _zz__zz_decode_IS_DIV_142; + wire _zz__zz_decode_IS_DIV_143; + wire _zz__zz_decode_IS_DIV_144; + wire [0:0] _zz__zz_decode_IS_DIV_145; + wire [0:0] _zz__zz_decode_IS_DIV_146; + wire [0:0] _zz__zz_decode_IS_DIV_147; + wire [0:0] _zz__zz_decode_IS_DIV_148; + wire _zz__zz_decode_IS_DIV_149; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [31:0] _zz__zz_decode_RS2_3; + wire [32:0] _zz__zz_decode_RS2_3_1; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1; + wire _zz_when; + wire _zz_when_1; + wire [5:0] _zz_memory_MulDivIterativePlugin_mul_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_mul_counter_valueNext_1; + wire [33:0] _zz_memory_MulDivIterativePlugin_accumulator; + wire [33:0] _zz_memory_MulDivIterativePlugin_accumulator_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_accumulator_2; + wire [33:0] _zz_memory_MulDivIterativePlugin_accumulator_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_accumulator_4; + wire [32:0] _zz_memory_MulDivIterativePlugin_accumulator_5; + wire [5:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_1; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_2; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_3; + wire [32:0] _zz_memory_MulDivIterativePlugin_div_result_4; + wire [0:0] _zz_memory_MulDivIterativePlugin_div_result_5; + wire [32:0] _zz_memory_MulDivIterativePlugin_rs1_3; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs1_4; + wire [31:0] _zz_memory_MulDivIterativePlugin_rs2; + wire [0:0] _zz_memory_MulDivIterativePlugin_rs2_1; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -428,46 +363,48 @@ module VexRiscv ( wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_MUL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_13; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_16; - wire `Src2CtrlEnum_defaultEncoding_type _zz_17; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_19; - wire `AluCtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_22; - wire `Src1CtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire decode_MEMORY_ENABLE; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; wire execute_DO_EBREAK; wire decode_IS_EBREAK; wire execute_IS_RS1_SIGNED; @@ -479,112 +416,90 @@ module VexRiscv ( wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_25; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; wire [31:0] execute_RS1; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_28; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; - reg [31:0] _zz_29; + reg [31:0] _zz_decode_RS2; wire memory_REGFILE_WRITE_VALID; wire [31:0] memory_INSTRUCTION; wire memory_BYPASSABLE_MEMORY_STAGE; wire writeBack_REGFILE_WRITE_VALID; reg [31:0] decode_RS2; reg [31:0] decode_RS1; - reg [31:0] _zz_30; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_31; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_32; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_33; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_34; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_35; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_36; - wire [31:0] _zz_37; - wire _zz_38; - reg _zz_39; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_40; - wire `BranchCtrlEnum_defaultEncoding_type _zz_41; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_42; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; - wire `Src2CtrlEnum_defaultEncoding_type _zz_44; - wire `AluCtrlEnum_defaultEncoding_type _zz_45; - wire `Src1CtrlEnum_defaultEncoding_type _zz_46; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; wire writeBack_MEMORY_STORE; - reg [31:0] _zz_47; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP2_physicalAddress; - wire memory_MMU_RSP2_isIoAccess; - wire memory_MMU_RSP2_isPaging; - wire memory_MMU_RSP2_allowRead; - wire memory_MMU_RSP2_allowWrite; - wire memory_MMU_RSP2_allowExecute; - wire memory_MMU_RSP2_exception; - wire memory_MMU_RSP2_refilling; - wire memory_MMU_RSP2_bypassTranslation; - wire [31:0] memory_PC; wire memory_ALIGNEMENT_FAULT; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP2_physicalAddress; - wire execute_MMU_RSP2_isIoAccess; - wire execute_MMU_RSP2_isPaging; - wire execute_MMU_RSP2_allowRead; - wire execute_MMU_RSP2_allowWrite; - wire execute_MMU_RSP2_allowExecute; - wire execute_MMU_RSP2_exception; - wire execute_MMU_RSP2_refilling; - wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; wire [31:0] execute_RS2; wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; - wire decode_MEMORY_ENABLE; wire decode_FLUSH_ALL; reg IBusCachedPlugin_rsp_issueDetected_4; reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_48; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_49; - reg [31:0] _zz_50; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -613,7 +528,7 @@ module VexRiscv ( reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; + wire memory_arbitration_flushIt; reg memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; @@ -667,23 +582,6 @@ module VexRiscv ( reg DBusSimplePlugin_memoryExceptionPort_valid; reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_0_isValid; - wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_isPaging; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -692,6 +590,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; wire CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -709,31 +612,36 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; reg CsrPlugin_allowInterrupts; reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; reg IBusCachedPlugin_injectionPort_valid; reg IBusCachedPlugin_injectionPort_ready; wire [31:0] IBusCachedPlugin_injectionPort_payload; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_51; - wire [3:0] _zz_52; - wire _zz_53; - wire _zz_54; - wire _zz_55; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -756,16 +664,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_56; - wire _zz_57; - wire _zz_58; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_59; - wire _zz_60; - reg _zz_61; - wire _zz_62; - reg _zz_63; - reg [31:0] _zz_64; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -773,22 +683,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_65; - reg [18:0] _zz_66; - wire _zz_67; - reg [10:0] _zz_68; - wire _zz_69; - reg [18:0] _zz_70; - reg _zz_71; - wire _zz_72; - reg [10:0] _zz_73; - wire _zz_74; - reg [18:0] _zz_75; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -796,7 +713,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_76; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -804,6 +721,11 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dBus_cmd_valid; wire dBus_cmd_ready; wire dBus_cmd_payload_wr; @@ -813,31 +735,38 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - wire _zz_77; + wire _zz_dBus_cmd_valid; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_78; - reg [3:0] _zz_79; + reg [31:0] _zz_dBus_cmd_payload_data; + wire when_DBusSimplePlugin_l426; + reg [3:0] _zz_execute_DBusSimplePlugin_formalMask; wire [3:0] execute_DBusSimplePlugin_formalMask; + wire when_DBusSimplePlugin_l479; + wire when_DBusSimplePlugin_l486; + wire when_DBusSimplePlugin_l512; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_80; - reg [31:0] _zz_81; - wire _zz_82; - reg [31:0] _zz_83; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusSimplePlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1; + wire _zz_writeBack_DBusSimplePlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3; reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [31:0] _zz_84; - wire _zz_85; - wire _zz_86; - wire _zz_87; - wire _zz_88; - wire _zz_89; - wire _zz_90; - wire `Src1CtrlEnum_defaultEncoding_type _zz_91; - wire `AluCtrlEnum_defaultEncoding_type _zz_92; - wire `Src2CtrlEnum_defaultEncoding_type _zz_93; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_94; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_95; - wire `BranchCtrlEnum_defaultEncoding_type _zz_96; - wire `EnvCtrlEnum_defaultEncoding_type _zz_97; + wire when_DBusSimplePlugin_l558; + wire [31:0] _zz_decode_IS_DIV; + wire _zz_decode_IS_DIV_1; + wire _zz_decode_IS_DIV_2; + wire _zz_decode_IS_DIV_3; + wire _zz_decode_IS_DIV_4; + wire _zz_decode_IS_DIV_5; + wire _zz_decode_IS_DIV_6; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -845,15 +774,15 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_98; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_99; - reg [31:0] _zz_100; - wire _zz_101; - reg [19:0] _zz_102; - wire _zz_103; - reg [19:0] _zz_104; - reg [31:0] _zz_105; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; @@ -862,38 +791,59 @@ module VexRiscv ( wire [4:0] execute_LightShifterPlugin_amplitude; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_106; - reg _zz_107; - reg _zz_108; - reg _zz_109; - reg [4:0] _zz_110; - reg [31:0] _zz_111; - wire _zz_112; - wire _zz_113; - wire _zz_114; - wire _zz_115; - wire _zz_116; - wire _zz_117; + wire when_ShiftPlugins_l169; + reg [31:0] _zz_decode_RS2_3; + wire when_ShiftPlugins_l175; + wire when_ShiftPlugins_l184; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_118; - reg _zz_119; - reg _zz_120; - wire _zz_121; - reg [19:0] _zz_122; - wire _zz_123; - reg [10:0] _zz_124; - wire _zz_125; - reg [18:0] _zz_126; - reg _zz_127; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_128; - reg [19:0] _zz_129; - wire _zz_130; - reg [10:0] _zz_131; - wire _zz_132; - reg [18:0] _zz_133; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; wire [25:0] CsrPlugin_misa_extensions; @@ -914,9 +864,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_134; - wire _zz_135; - wire _zz_136; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -929,37 +879,60 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_137; - wire _zz_138; - wire [1:0] _zz_139; - wire _zz_140; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg [32:0] memory_MulDivIterativePlugin_rs1; reg [31:0] memory_MulDivIterativePlugin_rs2; @@ -971,6 +944,10 @@ module VexRiscv ( reg [5:0] memory_MulDivIterativePlugin_mul_counter_value; wire memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc; wire memory_MulDivIterativePlugin_mul_counter_willOverflow; + wire when_MulDivIterativePlugin_l96; + wire when_MulDivIterativePlugin_l97; + wire when_MulDivIterativePlugin_l100; + wire when_MulDivIterativePlugin_l110; reg memory_MulDivIterativePlugin_div_needRevert; reg memory_MulDivIterativePlugin_div_counter_willIncrement; reg memory_MulDivIterativePlugin_div_counter_willClear; @@ -979,19 +956,26 @@ module VexRiscv ( wire memory_MulDivIterativePlugin_div_counter_willOverflowIfInc; wire memory_MulDivIterativePlugin_div_counter_willOverflow; reg memory_MulDivIterativePlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_MulDivIterativePlugin_div_result; - wire [31:0] _zz_141; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderShifted; wire [32:0] memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outRemainder; wire [31:0] memory_MulDivIterativePlugin_div_stage_0_outNumerator; - wire [31:0] _zz_142; - wire _zz_143; - wire _zz_144; - reg [32:0] _zz_145; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_MulDivIterativePlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_MulDivIterativePlugin_rs1; + wire _zz_memory_MulDivIterativePlugin_rs1_1; + reg [32:0] _zz_memory_MulDivIterativePlugin_rs1_2; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_146; - wire [31:0] _zz_147; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -999,95 +983,175 @@ module VexRiscv ( reg DebugPlugin_stepIt; reg DebugPlugin_isPipBusy; reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_148; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_9; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_14; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_15; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_16; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg decode_to_execute_MEMORY_STORE; + wire when_Pipeline_l124_23; reg execute_to_memory_MEMORY_STORE; + wire when_Pipeline_l124_24; reg memory_to_writeBack_MEMORY_STORE; + wire when_Pipeline_l124_25; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_26; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_27; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_28; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_29; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_30; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_31; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_32; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_33; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_34; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_35; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_37; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_38; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_39; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_40; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_41; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_42; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_43; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_44; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_45; reg decode_to_execute_DO_EBREAK; + wire when_Pipeline_l124_46; reg execute_to_memory_ALIGNEMENT_FAULT; + wire when_Pipeline_l124_47; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_48; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_MMU_FAULT; - reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; - reg execute_to_memory_MMU_RSP2_isIoAccess; - reg execute_to_memory_MMU_RSP2_isPaging; - reg execute_to_memory_MMU_RSP2_allowRead; - reg execute_to_memory_MMU_RSP2_allowWrite; - reg execute_to_memory_MMU_RSP2_allowExecute; - reg execute_to_memory_MMU_RSP2_exception; - reg execute_to_memory_MMU_RSP2_refilling; - reg execute_to_memory_MMU_RSP2_bypassTranslation; + wire when_Pipeline_l124_49; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_50; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_51; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_52; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_53; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg [2:0] _zz_149; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l378; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_150; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [2:0] _zz_158; - reg _zz_159; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; @@ -1095,78 +1159,79 @@ module VexRiscv ( wire [31:0] dBus_cmd_halfPipe_payload_address; wire [31:0] dBus_cmd_halfPipe_payload_data; wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_160; + reg dBus_cmd_rValid; + wire dBus_cmd_halfPipe_fire; + reg dBus_cmd_rData_wr; + reg [31:0] dBus_cmd_rData_address; + reg [31:0] dBus_cmd_rData_data; + reg [1:0] dBus_cmd_rData_size; + reg [3:0] _zz_dBusWishbone_SEL; + wire when_DBusSimplePlugin_l189; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_10_string; - reg [71:0] _zz_11_string; - reg [71:0] _zz_12_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_13_string; - reg [39:0] _zz_14_string; - reg [39:0] _zz_15_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_16_string; - reg [23:0] _zz_17_string; - reg [23:0] _zz_18_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_19_string; - reg [63:0] _zz_20_string; - reg [63:0] _zz_21_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_22_string; - reg [95:0] _zz_23_string; - reg [95:0] _zz_24_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_25_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_26_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_28_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_31_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_33_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_34_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_35_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_36_string; - reg [39:0] _zz_40_string; - reg [31:0] _zz_41_string; - reg [71:0] _zz_42_string; - reg [39:0] _zz_43_string; - reg [23:0] _zz_44_string; - reg [63:0] _zz_45_string; - reg [95:0] _zz_46_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_48_string; - reg [95:0] _zz_91_string; - reg [63:0] _zz_92_string; - reg [23:0] _zz_93_string; - reg [39:0] _zz_94_string; - reg [71:0] _zz_95_string; - reg [31:0] _zz_96_string; - reg [39:0] _zz_97_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1180,1010 +1245,940 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_173 = (memory_arbitration_isValid && memory_IS_MUL); - assign _zz_174 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_175 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_176 = 1'b1; - assign _zz_177 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_178 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_179 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_180 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_181 = ((_zz_166 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_182 = ((_zz_166 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_183 = ((_zz_166 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_184 = ((_zz_166 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_185 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_186 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_187 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_188 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); - assign _zz_189 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_190 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_191 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_192 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_193 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_194 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_195 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_196 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_197 = (1'b0 || (! 1'b1)); - assign _zz_198 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_199 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_200 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_201 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_202 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_203 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_204 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); - assign _zz_205 = (! memory_arbitration_isStuck); - assign _zz_206 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_207 = (iBus_cmd_valid || (_zz_158 != 3'b000)); - assign _zz_208 = (! execute_arbitration_isStuckByOthers); - assign _zz_209 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_210 = ((_zz_134 && 1'b1) && (! 1'b0)); - assign _zz_211 = ((_zz_135 && 1'b1) && (! 1'b0)); - assign _zz_212 = ((_zz_136 && 1'b1) && (! 1'b0)); - assign _zz_213 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_214 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_215 = execute_INSTRUCTION[13]; - assign _zz_216 = _zz_84[30 : 30]; - assign _zz_217 = _zz_84[29 : 29]; - assign _zz_218 = _zz_84[28 : 28]; - assign _zz_219 = _zz_84[27 : 27]; - assign _zz_220 = _zz_84[24 : 24]; - assign _zz_221 = _zz_84[16 : 16]; - assign _zz_222 = _zz_84[13 : 13]; - assign _zz_223 = _zz_84[12 : 12]; - assign _zz_224 = _zz_84[11 : 11]; - assign _zz_225 = _zz_84[31 : 31]; - assign _zz_226 = _zz_84[15 : 15]; - assign _zz_227 = _zz_84[5 : 5]; - assign _zz_228 = _zz_84[3 : 3]; - assign _zz_229 = _zz_84[19 : 19]; - assign _zz_230 = _zz_84[10 : 10]; - assign _zz_231 = _zz_84[4 : 4]; - assign _zz_232 = _zz_84[0 : 0]; - assign _zz_233 = (_zz_51 - 4'b0001); - assign _zz_234 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_235 = {29'd0, _zz_234}; - assign _zz_236 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_237 = {{_zz_66,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_238 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_239 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_240 = {{_zz_68,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_241 = {{_zz_70,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_242 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_243 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_244 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_245 = execute_SRC_LESS; - assign _zz_246 = 3'b100; - assign _zz_247 = execute_INSTRUCTION[19 : 15]; - assign _zz_248 = execute_INSTRUCTION[31 : 20]; - assign _zz_249 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_250 = ($signed(_zz_251) + $signed(_zz_254)); - assign _zz_251 = ($signed(_zz_252) + $signed(_zz_253)); - assign _zz_252 = execute_SRC1; - assign _zz_253 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_254 = (execute_SRC_USE_SUB_LESS ? _zz_255 : _zz_256); - assign _zz_255 = 32'h00000001; - assign _zz_256 = 32'h0; - assign _zz_257 = (_zz_258 >>> 1); - assign _zz_258 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_259 = execute_INSTRUCTION[31 : 20]; - assign _zz_260 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_261 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_262 = {_zz_122,execute_INSTRUCTION[31 : 20]}; - assign _zz_263 = {{_zz_124,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_264 = {{_zz_126,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_265 = execute_INSTRUCTION[31 : 20]; - assign _zz_266 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_267 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_268 = 3'b100; - assign _zz_269 = (_zz_137 & (~ _zz_270)); - assign _zz_270 = (_zz_137 - 2'b01); - assign _zz_271 = (_zz_139 & (~ _zz_272)); - assign _zz_272 = (_zz_139 - 2'b01); - assign _zz_273 = memory_MulDivIterativePlugin_mul_counter_willIncrement; - assign _zz_274 = {5'd0, _zz_273}; - assign _zz_275 = (_zz_277 + _zz_279); - assign _zz_276 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); - assign _zz_277 = {{1{_zz_276[32]}}, _zz_276}; - assign _zz_278 = _zz_280; - assign _zz_279 = {{1{_zz_278[32]}}, _zz_278}; - assign _zz_280 = (memory_MulDivIterativePlugin_accumulator >>> 32); - assign _zz_281 = memory_MulDivIterativePlugin_div_counter_willIncrement; - assign _zz_282 = {5'd0, _zz_281}; - assign _zz_283 = {1'd0, memory_MulDivIterativePlugin_rs2}; - assign _zz_284 = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_285 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_286 = {_zz_141,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_287 = _zz_288; - assign _zz_288 = _zz_289; - assign _zz_289 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_142) : _zz_142)} + _zz_291); - assign _zz_290 = memory_MulDivIterativePlugin_div_needRevert; - assign _zz_291 = {32'd0, _zz_290}; - assign _zz_292 = _zz_144; - assign _zz_293 = {32'd0, _zz_292}; - assign _zz_294 = _zz_143; - assign _zz_295 = {31'd0, _zz_294}; - assign _zz_296 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_297 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_298 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_299 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_300 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_301 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_302 = (iBus_cmd_payload_address >>> 5); - assign _zz_303 = 1'b1; - assign _zz_304 = 1'b1; - assign _zz_305 = {_zz_55,_zz_54}; - assign _zz_306 = 32'h0000107f; - assign _zz_307 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_308 = 32'h00002073; - assign _zz_309 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_310 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_311 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_312) == 32'h00000003),{(_zz_313 == _zz_314),{_zz_315,{_zz_316,_zz_317}}}}}}; - assign _zz_312 = 32'h0000505f; - assign _zz_313 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_314 = 32'h00000063; - assign _zz_315 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_316 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); - assign _zz_317 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_318) == 32'h00005033),{(_zz_319 == _zz_320),{_zz_321,{_zz_322,_zz_323}}}}}}; - assign _zz_318 = 32'hbe00707f; - assign _zz_319 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_320 = 32'h00000033; - assign _zz_321 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_322 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); - assign _zz_323 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_324 = decode_INSTRUCTION[31]; - assign _zz_325 = decode_INSTRUCTION[31]; - assign _zz_326 = decode_INSTRUCTION[7]; - assign _zz_327 = 32'h10103050; - assign _zz_328 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_329 = 32'h02004020; - assign _zz_330 = _zz_90; - assign _zz_331 = _zz_89; - assign _zz_332 = {_zz_90,{_zz_88,_zz_89}}; - assign _zz_333 = 3'b000; - assign _zz_334 = (((decode_INSTRUCTION & _zz_337) == 32'h02000030) != 1'b0); - assign _zz_335 = ((_zz_338 == _zz_339) != 1'b0); - assign _zz_336 = {(_zz_340 != 1'b0),{(_zz_341 != _zz_342),{_zz_343,{_zz_344,_zz_345}}}}; - assign _zz_337 = 32'h02004074; - assign _zz_338 = (decode_INSTRUCTION & 32'h10103050); - assign _zz_339 = 32'h00000050; - assign _zz_340 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); - assign _zz_341 = {(_zz_346 == _zz_347),(_zz_348 == _zz_349)}; - assign _zz_342 = 2'b00; - assign _zz_343 = ({_zz_87,_zz_350} != 2'b00); - assign _zz_344 = (_zz_351 != 1'b0); - assign _zz_345 = {(_zz_352 != _zz_353),{_zz_354,{_zz_355,_zz_356}}}; - assign _zz_346 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_347 = 32'h00001050; - assign _zz_348 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_349 = 32'h00002050; - assign _zz_350 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_351 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_352 = {(_zz_357 == _zz_358),(_zz_359 == _zz_360)}; - assign _zz_353 = 2'b00; - assign _zz_354 = ({_zz_361,{_zz_362,_zz_363}} != 3'b000); - assign _zz_355 = ({_zz_364,_zz_365} != 3'b000); - assign _zz_356 = {(_zz_366 != _zz_367),{_zz_368,{_zz_369,_zz_370}}}; - assign _zz_357 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_358 = 32'h00005010; - assign _zz_359 = (decode_INSTRUCTION & 32'h02007064); - assign _zz_360 = 32'h00005020; - assign _zz_361 = ((decode_INSTRUCTION & _zz_371) == 32'h40001010); - assign _zz_362 = (_zz_372 == _zz_373); - assign _zz_363 = (_zz_374 == _zz_375); - assign _zz_364 = (_zz_376 == _zz_377); - assign _zz_365 = {_zz_378,_zz_379}; - assign _zz_366 = (_zz_380 == _zz_381); - assign _zz_367 = 1'b0; - assign _zz_368 = (_zz_88 != 1'b0); - assign _zz_369 = (_zz_382 != _zz_383); - assign _zz_370 = {_zz_384,{_zz_385,_zz_386}}; - assign _zz_371 = 32'h40003054; - assign _zz_372 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_373 = 32'h00001010; - assign _zz_374 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_375 = 32'h00001010; - assign _zz_376 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_377 = 32'h00000024; - assign _zz_378 = ((decode_INSTRUCTION & 32'h00003034) == 32'h00001010); - assign _zz_379 = ((decode_INSTRUCTION & 32'h02003054) == 32'h00001010); - assign _zz_380 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_381 = 32'h00001000; - assign _zz_382 = {(_zz_387 == _zz_388),(_zz_389 == _zz_390)}; - assign _zz_383 = 2'b00; - assign _zz_384 = ({_zz_391,_zz_392} != 2'b00); - assign _zz_385 = ({_zz_393,_zz_394} != 3'b000); - assign _zz_386 = {(_zz_395 != _zz_396),{_zz_397,{_zz_398,_zz_399}}}; - assign _zz_387 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_388 = 32'h00002000; - assign _zz_389 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_390 = 32'h00001000; - assign _zz_391 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); - assign _zz_392 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); - assign _zz_393 = ((decode_INSTRUCTION & _zz_400) == 32'h00000040); - assign _zz_394 = {(_zz_401 == _zz_402),(_zz_403 == _zz_404)}; - assign _zz_395 = ((decode_INSTRUCTION & _zz_405) == 32'h00000020); - assign _zz_396 = 1'b0; - assign _zz_397 = ((_zz_406 == _zz_407) != 1'b0); - assign _zz_398 = ({_zz_408,_zz_409} != 3'b000); - assign _zz_399 = {(_zz_410 != _zz_411),{_zz_412,{_zz_413,_zz_414}}}; - assign _zz_400 = 32'h00000050; - assign _zz_401 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_402 = 32'h0; - assign _zz_403 = (decode_INSTRUCTION & 32'h00103040); - assign _zz_404 = 32'h00000040; - assign _zz_405 = 32'h00000020; - assign _zz_406 = (decode_INSTRUCTION & 32'h00000010); - assign _zz_407 = 32'h00000010; - assign _zz_408 = _zz_86; - assign _zz_409 = {(_zz_415 == _zz_416),(_zz_417 == _zz_418)}; - assign _zz_410 = {_zz_87,{_zz_419,{_zz_420,_zz_421}}}; - assign _zz_411 = 6'h0; - assign _zz_412 = ({_zz_86,_zz_422} != 2'b00); - assign _zz_413 = ({_zz_423,_zz_424} != 2'b00); - assign _zz_414 = {(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}; - assign _zz_415 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_416 = 32'h00000010; - assign _zz_417 = (decode_INSTRUCTION & 32'h02000060); - assign _zz_418 = 32'h00000020; - assign _zz_419 = ((decode_INSTRUCTION & _zz_430) == 32'h00001010); - assign _zz_420 = (_zz_431 == _zz_432); - assign _zz_421 = {_zz_433,{_zz_434,_zz_435}}; - assign _zz_422 = ((decode_INSTRUCTION & _zz_436) == 32'h00000020); - assign _zz_423 = _zz_86; - assign _zz_424 = (_zz_437 == _zz_438); - assign _zz_425 = {_zz_439,_zz_440}; - assign _zz_426 = 2'b00; - assign _zz_427 = (_zz_441 != 1'b0); - assign _zz_428 = (_zz_442 != _zz_443); - assign _zz_429 = {_zz_444,{_zz_445,_zz_446}}; - assign _zz_430 = 32'h00001010; - assign _zz_431 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_432 = 32'h00002010; - assign _zz_433 = ((decode_INSTRUCTION & _zz_447) == 32'h00000010); - assign _zz_434 = (_zz_448 == _zz_449); - assign _zz_435 = (_zz_450 == _zz_451); - assign _zz_436 = 32'h00000070; - assign _zz_437 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_438 = 32'h0; - assign _zz_439 = ((decode_INSTRUCTION & _zz_452) == 32'h00006010); - assign _zz_440 = ((decode_INSTRUCTION & _zz_453) == 32'h00004010); - assign _zz_441 = ((decode_INSTRUCTION & _zz_454) == 32'h00002010); - assign _zz_442 = {_zz_455,{_zz_456,_zz_457}}; - assign _zz_443 = 4'b0000; - assign _zz_444 = (_zz_458 != 1'b0); - assign _zz_445 = (_zz_459 != _zz_460); - assign _zz_446 = {_zz_461,{_zz_462,_zz_463}}; - assign _zz_447 = 32'h00000050; - assign _zz_448 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_449 = 32'h00000004; - assign _zz_450 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_451 = 32'h0; - assign _zz_452 = 32'h00006014; - assign _zz_453 = 32'h00005014; - assign _zz_454 = 32'h00006014; - assign _zz_455 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_456 = ((decode_INSTRUCTION & _zz_464) == 32'h0); - assign _zz_457 = {(_zz_465 == _zz_466),(_zz_467 == _zz_468)}; - assign _zz_458 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_459 = {(_zz_469 == _zz_470),{_zz_471,_zz_472}}; - assign _zz_460 = 3'b000; - assign _zz_461 = ({_zz_473,_zz_85} != 2'b00); - assign _zz_462 = ({_zz_474,_zz_475} != 2'b00); - assign _zz_463 = (_zz_476 != 1'b0); - assign _zz_464 = 32'h00000018; - assign _zz_465 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_466 = 32'h00002000; - assign _zz_467 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_468 = 32'h00001000; - assign _zz_469 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_470 = 32'h00000040; - assign _zz_471 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_472 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz_473 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_474 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_475 = _zz_85; - assign _zz_476 = ((decode_INSTRUCTION & 32'h00001048) == 32'h00001008); - assign _zz_477 = execute_INSTRUCTION[31]; - assign _zz_478 = execute_INSTRUCTION[31]; - assign _zz_479 = execute_INSTRUCTION[7]; - always @ (posedge clk) begin - if(_zz_303) begin - _zz_170 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_304) begin - _zz_171 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_39) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_when_1 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 3'b001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_decode_RS2_3 = (_zz__zz_decode_RS2_3_1 >>> 1); + assign _zz__zz_decode_RS2_3_1 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01); + assign _zz_memory_MulDivIterativePlugin_mul_counter_valueNext_1 = memory_MulDivIterativePlugin_mul_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_mul_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_mul_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_accumulator = (_zz_memory_MulDivIterativePlugin_accumulator_1 + _zz_memory_MulDivIterativePlugin_accumulator_3); + assign _zz_memory_MulDivIterativePlugin_accumulator_2 = (memory_MulDivIterativePlugin_rs2[0] ? memory_MulDivIterativePlugin_rs1 : 33'h0); + assign _zz_memory_MulDivIterativePlugin_accumulator_1 = {{1{_zz_memory_MulDivIterativePlugin_accumulator_2[32]}}, _zz_memory_MulDivIterativePlugin_accumulator_2}; + assign _zz_memory_MulDivIterativePlugin_accumulator_4 = _zz_memory_MulDivIterativePlugin_accumulator_5; + assign _zz_memory_MulDivIterativePlugin_accumulator_3 = {{1{_zz_memory_MulDivIterativePlugin_accumulator_4[32]}}, _zz_memory_MulDivIterativePlugin_accumulator_4}; + assign _zz_memory_MulDivIterativePlugin_accumulator_5 = (memory_MulDivIterativePlugin_accumulator >>> 32); + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1 = memory_MulDivIterativePlugin_div_counter_willIncrement; + assign _zz_memory_MulDivIterativePlugin_div_counter_valueNext = {5'd0, _zz_memory_MulDivIterativePlugin_div_counter_valueNext_1}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_MulDivIterativePlugin_rs2}; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder = memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1 = memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator = {_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted,(! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_MulDivIterativePlugin_div_result_1 = _zz_memory_MulDivIterativePlugin_div_result_2; + assign _zz_memory_MulDivIterativePlugin_div_result_2 = _zz_memory_MulDivIterativePlugin_div_result_3; + assign _zz_memory_MulDivIterativePlugin_div_result_3 = ({memory_MulDivIterativePlugin_div_needRevert,(memory_MulDivIterativePlugin_div_needRevert ? (~ _zz_memory_MulDivIterativePlugin_div_result) : _zz_memory_MulDivIterativePlugin_div_result)} + _zz_memory_MulDivIterativePlugin_div_result_4); + assign _zz_memory_MulDivIterativePlugin_div_result_5 = memory_MulDivIterativePlugin_div_needRevert; + assign _zz_memory_MulDivIterativePlugin_div_result_4 = {32'd0, _zz_memory_MulDivIterativePlugin_div_result_5}; + assign _zz_memory_MulDivIterativePlugin_rs1_4 = _zz_memory_MulDivIterativePlugin_rs1_1; + assign _zz_memory_MulDivIterativePlugin_rs1_3 = {32'd0, _zz_memory_MulDivIterativePlugin_rs1_4}; + assign _zz_memory_MulDivIterativePlugin_rs2_1 = _zz_memory_MulDivIterativePlugin_rs1; + assign _zz_memory_MulDivIterativePlugin_rs2 = {31'd0, _zz_memory_MulDivIterativePlugin_rs2_1}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_3,_zz_IBusCachedPlugin_jump_pcLoad_payload_2}; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00305f) == 32'h00001013),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005033),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbe00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00000033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_IS_DIV = 32'h10103050; + assign _zz__zz_decode_IS_DIV_1 = (decode_INSTRUCTION & 32'h02004064); + assign _zz__zz_decode_IS_DIV_2 = 32'h02004020; + assign _zz__zz_decode_IS_DIV_3 = _zz_decode_IS_DIV_6; + assign _zz__zz_decode_IS_DIV_4 = _zz_decode_IS_DIV_5; + assign _zz__zz_decode_IS_DIV_5 = {_zz_decode_IS_DIV_6,{_zz_decode_IS_DIV_4,_zz_decode_IS_DIV_5}}; + assign _zz__zz_decode_IS_DIV_6 = 3'b000; + assign _zz__zz_decode_IS_DIV_7 = (((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_8) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_IS_DIV_9 = ((_zz__zz_decode_IS_DIV_10 == _zz__zz_decode_IS_DIV_11) != 1'b0); + assign _zz__zz_decode_IS_DIV_12 = {(_zz__zz_decode_IS_DIV_13 != 1'b0),{(_zz__zz_decode_IS_DIV_14 != _zz__zz_decode_IS_DIV_19),{_zz__zz_decode_IS_DIV_20,{_zz__zz_decode_IS_DIV_22,_zz__zz_decode_IS_DIV_24}}}}; + assign _zz__zz_decode_IS_DIV_8 = 32'h02004074; + assign _zz__zz_decode_IS_DIV_10 = (decode_INSTRUCTION & 32'h10103050); + assign _zz__zz_decode_IS_DIV_11 = 32'h00000050; + assign _zz__zz_decode_IS_DIV_13 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz__zz_decode_IS_DIV_14 = {(_zz__zz_decode_IS_DIV_15 == _zz__zz_decode_IS_DIV_16),(_zz__zz_decode_IS_DIV_17 == _zz__zz_decode_IS_DIV_18)}; + assign _zz__zz_decode_IS_DIV_19 = 2'b00; + assign _zz__zz_decode_IS_DIV_20 = ({_zz_decode_IS_DIV_3,_zz__zz_decode_IS_DIV_21} != 2'b00); + assign _zz__zz_decode_IS_DIV_22 = (_zz__zz_decode_IS_DIV_23 != 1'b0); + assign _zz__zz_decode_IS_DIV_24 = {(_zz__zz_decode_IS_DIV_25 != _zz__zz_decode_IS_DIV_30),{_zz__zz_decode_IS_DIV_31,{_zz__zz_decode_IS_DIV_40,_zz__zz_decode_IS_DIV_47}}}; + assign _zz__zz_decode_IS_DIV_15 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_IS_DIV_16 = 32'h00001050; + assign _zz__zz_decode_IS_DIV_17 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_IS_DIV_18 = 32'h00002050; + assign _zz__zz_decode_IS_DIV_21 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_IS_DIV_23 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_IS_DIV_25 = {(_zz__zz_decode_IS_DIV_26 == _zz__zz_decode_IS_DIV_27),(_zz__zz_decode_IS_DIV_28 == _zz__zz_decode_IS_DIV_29)}; + assign _zz__zz_decode_IS_DIV_30 = 2'b00; + assign _zz__zz_decode_IS_DIV_31 = ({_zz__zz_decode_IS_DIV_32,{_zz__zz_decode_IS_DIV_34,_zz__zz_decode_IS_DIV_37}} != 3'b000); + assign _zz__zz_decode_IS_DIV_40 = ({_zz__zz_decode_IS_DIV_41,_zz__zz_decode_IS_DIV_44} != 3'b000); + assign _zz__zz_decode_IS_DIV_47 = {(_zz__zz_decode_IS_DIV_48 != _zz__zz_decode_IS_DIV_51),{_zz__zz_decode_IS_DIV_52,{_zz__zz_decode_IS_DIV_53,_zz__zz_decode_IS_DIV_60}}}; + assign _zz__zz_decode_IS_DIV_26 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_DIV_27 = 32'h00005010; + assign _zz__zz_decode_IS_DIV_28 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_IS_DIV_29 = 32'h00005020; + assign _zz__zz_decode_IS_DIV_32 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_33) == 32'h40001010); + assign _zz__zz_decode_IS_DIV_34 = (_zz__zz_decode_IS_DIV_35 == _zz__zz_decode_IS_DIV_36); + assign _zz__zz_decode_IS_DIV_37 = (_zz__zz_decode_IS_DIV_38 == _zz__zz_decode_IS_DIV_39); + assign _zz__zz_decode_IS_DIV_41 = (_zz__zz_decode_IS_DIV_42 == _zz__zz_decode_IS_DIV_43); + assign _zz__zz_decode_IS_DIV_44 = {_zz__zz_decode_IS_DIV_45,_zz__zz_decode_IS_DIV_46}; + assign _zz__zz_decode_IS_DIV_48 = (_zz__zz_decode_IS_DIV_49 == _zz__zz_decode_IS_DIV_50); + assign _zz__zz_decode_IS_DIV_51 = 1'b0; + assign _zz__zz_decode_IS_DIV_52 = (_zz_decode_IS_DIV_4 != 1'b0); + assign _zz__zz_decode_IS_DIV_53 = (_zz__zz_decode_IS_DIV_54 != _zz__zz_decode_IS_DIV_59); + assign _zz__zz_decode_IS_DIV_60 = {_zz__zz_decode_IS_DIV_61,{_zz__zz_decode_IS_DIV_64,_zz__zz_decode_IS_DIV_72}}; + assign _zz__zz_decode_IS_DIV_33 = 32'h40003054; + assign _zz__zz_decode_IS_DIV_35 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_DIV_36 = 32'h00001010; + assign _zz__zz_decode_IS_DIV_38 = (decode_INSTRUCTION & 32'h02007054); + assign _zz__zz_decode_IS_DIV_39 = 32'h00001010; + assign _zz__zz_decode_IS_DIV_42 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_IS_DIV_43 = 32'h00000024; + assign _zz__zz_decode_IS_DIV_45 = ((decode_INSTRUCTION & 32'h00003034) == 32'h00001010); + assign _zz__zz_decode_IS_DIV_46 = ((decode_INSTRUCTION & 32'h02003054) == 32'h00001010); + assign _zz__zz_decode_IS_DIV_49 = (decode_INSTRUCTION & 32'h00001000); + assign _zz__zz_decode_IS_DIV_50 = 32'h00001000; + assign _zz__zz_decode_IS_DIV_54 = {(_zz__zz_decode_IS_DIV_55 == _zz__zz_decode_IS_DIV_56),(_zz__zz_decode_IS_DIV_57 == _zz__zz_decode_IS_DIV_58)}; + assign _zz__zz_decode_IS_DIV_59 = 2'b00; + assign _zz__zz_decode_IS_DIV_61 = ({_zz__zz_decode_IS_DIV_62,_zz__zz_decode_IS_DIV_63} != 2'b00); + assign _zz__zz_decode_IS_DIV_64 = ({_zz__zz_decode_IS_DIV_65,_zz__zz_decode_IS_DIV_67} != 3'b000); + assign _zz__zz_decode_IS_DIV_72 = {(_zz__zz_decode_IS_DIV_73 != _zz__zz_decode_IS_DIV_75),{_zz__zz_decode_IS_DIV_76,{_zz__zz_decode_IS_DIV_79,_zz__zz_decode_IS_DIV_86}}}; + assign _zz__zz_decode_IS_DIV_55 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_DIV_56 = 32'h00002000; + assign _zz__zz_decode_IS_DIV_57 = (decode_INSTRUCTION & 32'h00005000); + assign _zz__zz_decode_IS_DIV_58 = 32'h00001000; + assign _zz__zz_decode_IS_DIV_62 = ((decode_INSTRUCTION & 32'h00000034) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_63 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_65 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_66) == 32'h00000040); + assign _zz__zz_decode_IS_DIV_67 = {(_zz__zz_decode_IS_DIV_68 == _zz__zz_decode_IS_DIV_69),(_zz__zz_decode_IS_DIV_70 == _zz__zz_decode_IS_DIV_71)}; + assign _zz__zz_decode_IS_DIV_73 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_74) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_75 = 1'b0; + assign _zz__zz_decode_IS_DIV_76 = ((_zz__zz_decode_IS_DIV_77 == _zz__zz_decode_IS_DIV_78) != 1'b0); + assign _zz__zz_decode_IS_DIV_79 = ({_zz__zz_decode_IS_DIV_80,_zz__zz_decode_IS_DIV_81} != 3'b000); + assign _zz__zz_decode_IS_DIV_86 = {(_zz__zz_decode_IS_DIV_87 != _zz__zz_decode_IS_DIV_102),{_zz__zz_decode_IS_DIV_103,{_zz__zz_decode_IS_DIV_106,_zz__zz_decode_IS_DIV_111}}}; + assign _zz__zz_decode_IS_DIV_66 = 32'h00000050; + assign _zz__zz_decode_IS_DIV_68 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_IS_DIV_69 = 32'h0; + assign _zz__zz_decode_IS_DIV_70 = (decode_INSTRUCTION & 32'h00103040); + assign _zz__zz_decode_IS_DIV_71 = 32'h00000040; + assign _zz__zz_decode_IS_DIV_74 = 32'h00000020; + assign _zz__zz_decode_IS_DIV_77 = (decode_INSTRUCTION & 32'h00000010); + assign _zz__zz_decode_IS_DIV_78 = 32'h00000010; + assign _zz__zz_decode_IS_DIV_80 = _zz_decode_IS_DIV_2; + assign _zz__zz_decode_IS_DIV_81 = {(_zz__zz_decode_IS_DIV_82 == _zz__zz_decode_IS_DIV_83),(_zz__zz_decode_IS_DIV_84 == _zz__zz_decode_IS_DIV_85)}; + assign _zz__zz_decode_IS_DIV_87 = {_zz_decode_IS_DIV_3,{_zz__zz_decode_IS_DIV_88,{_zz__zz_decode_IS_DIV_90,_zz__zz_decode_IS_DIV_93}}}; + assign _zz__zz_decode_IS_DIV_102 = 6'h0; + assign _zz__zz_decode_IS_DIV_103 = ({_zz_decode_IS_DIV_2,_zz__zz_decode_IS_DIV_104} != 2'b00); + assign _zz__zz_decode_IS_DIV_106 = ({_zz__zz_decode_IS_DIV_107,_zz__zz_decode_IS_DIV_108} != 2'b00); + assign _zz__zz_decode_IS_DIV_111 = {(_zz__zz_decode_IS_DIV_112 != _zz__zz_decode_IS_DIV_117),{_zz__zz_decode_IS_DIV_118,{_zz__zz_decode_IS_DIV_121,_zz__zz_decode_IS_DIV_132}}}; + assign _zz__zz_decode_IS_DIV_82 = (decode_INSTRUCTION & 32'h00000030); + assign _zz__zz_decode_IS_DIV_83 = 32'h00000010; + assign _zz__zz_decode_IS_DIV_84 = (decode_INSTRUCTION & 32'h02000060); + assign _zz__zz_decode_IS_DIV_85 = 32'h00000020; + assign _zz__zz_decode_IS_DIV_88 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_89) == 32'h00001010); + assign _zz__zz_decode_IS_DIV_90 = (_zz__zz_decode_IS_DIV_91 == _zz__zz_decode_IS_DIV_92); + assign _zz__zz_decode_IS_DIV_93 = {_zz__zz_decode_IS_DIV_94,{_zz__zz_decode_IS_DIV_96,_zz__zz_decode_IS_DIV_99}}; + assign _zz__zz_decode_IS_DIV_104 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_105) == 32'h00000020); + assign _zz__zz_decode_IS_DIV_107 = _zz_decode_IS_DIV_2; + assign _zz__zz_decode_IS_DIV_108 = (_zz__zz_decode_IS_DIV_109 == _zz__zz_decode_IS_DIV_110); + assign _zz__zz_decode_IS_DIV_112 = {_zz__zz_decode_IS_DIV_113,_zz__zz_decode_IS_DIV_115}; + assign _zz__zz_decode_IS_DIV_117 = 2'b00; + assign _zz__zz_decode_IS_DIV_118 = (_zz__zz_decode_IS_DIV_119 != 1'b0); + assign _zz__zz_decode_IS_DIV_121 = (_zz__zz_decode_IS_DIV_122 != _zz__zz_decode_IS_DIV_131); + assign _zz__zz_decode_IS_DIV_132 = {_zz__zz_decode_IS_DIV_133,{_zz__zz_decode_IS_DIV_135,_zz__zz_decode_IS_DIV_142}}; + assign _zz__zz_decode_IS_DIV_89 = 32'h00001010; + assign _zz__zz_decode_IS_DIV_91 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_DIV_92 = 32'h00002010; + assign _zz__zz_decode_IS_DIV_94 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_95) == 32'h00000010); + assign _zz__zz_decode_IS_DIV_96 = (_zz__zz_decode_IS_DIV_97 == _zz__zz_decode_IS_DIV_98); + assign _zz__zz_decode_IS_DIV_99 = (_zz__zz_decode_IS_DIV_100 == _zz__zz_decode_IS_DIV_101); + assign _zz__zz_decode_IS_DIV_105 = 32'h00000070; + assign _zz__zz_decode_IS_DIV_109 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_DIV_110 = 32'h0; + assign _zz__zz_decode_IS_DIV_113 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_114) == 32'h00006010); + assign _zz__zz_decode_IS_DIV_115 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_116) == 32'h00004010); + assign _zz__zz_decode_IS_DIV_119 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_120) == 32'h00002010); + assign _zz__zz_decode_IS_DIV_122 = {_zz__zz_decode_IS_DIV_123,{_zz__zz_decode_IS_DIV_124,_zz__zz_decode_IS_DIV_126}}; + assign _zz__zz_decode_IS_DIV_131 = 4'b0000; + assign _zz__zz_decode_IS_DIV_133 = (_zz__zz_decode_IS_DIV_134 != 1'b0); + assign _zz__zz_decode_IS_DIV_135 = (_zz__zz_decode_IS_DIV_136 != _zz__zz_decode_IS_DIV_141); + assign _zz__zz_decode_IS_DIV_142 = {_zz__zz_decode_IS_DIV_143,{_zz__zz_decode_IS_DIV_145,_zz__zz_decode_IS_DIV_148}}; + assign _zz__zz_decode_IS_DIV_95 = 32'h00000050; + assign _zz__zz_decode_IS_DIV_97 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz__zz_decode_IS_DIV_98 = 32'h00000004; + assign _zz__zz_decode_IS_DIV_100 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_DIV_101 = 32'h0; + assign _zz__zz_decode_IS_DIV_114 = 32'h00006014; + assign _zz__zz_decode_IS_DIV_116 = 32'h00005014; + assign _zz__zz_decode_IS_DIV_120 = 32'h00006014; + assign _zz__zz_decode_IS_DIV_123 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz__zz_decode_IS_DIV_124 = ((decode_INSTRUCTION & _zz__zz_decode_IS_DIV_125) == 32'h0); + assign _zz__zz_decode_IS_DIV_126 = {(_zz__zz_decode_IS_DIV_127 == _zz__zz_decode_IS_DIV_128),(_zz__zz_decode_IS_DIV_129 == _zz__zz_decode_IS_DIV_130)}; + assign _zz__zz_decode_IS_DIV_134 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz__zz_decode_IS_DIV_136 = {(_zz__zz_decode_IS_DIV_137 == _zz__zz_decode_IS_DIV_138),{_zz__zz_decode_IS_DIV_139,_zz__zz_decode_IS_DIV_140}}; + assign _zz__zz_decode_IS_DIV_141 = 3'b000; + assign _zz__zz_decode_IS_DIV_143 = ({_zz__zz_decode_IS_DIV_144,_zz_decode_IS_DIV_1} != 2'b00); + assign _zz__zz_decode_IS_DIV_145 = ({_zz__zz_decode_IS_DIV_146,_zz__zz_decode_IS_DIV_147} != 2'b00); + assign _zz__zz_decode_IS_DIV_148 = (_zz__zz_decode_IS_DIV_149 != 1'b0); + assign _zz__zz_decode_IS_DIV_125 = 32'h00000018; + assign _zz__zz_decode_IS_DIV_127 = (decode_INSTRUCTION & 32'h00006004); + assign _zz__zz_decode_IS_DIV_128 = 32'h00002000; + assign _zz__zz_decode_IS_DIV_129 = (decode_INSTRUCTION & 32'h00005004); + assign _zz__zz_decode_IS_DIV_130 = 32'h00001000; + assign _zz__zz_decode_IS_DIV_137 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_DIV_138 = 32'h00000040; + assign _zz__zz_decode_IS_DIV_139 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_IS_DIV_140 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz__zz_decode_IS_DIV_144 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz__zz_decode_IS_DIV_146 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_IS_DIV_147 = _zz_decode_IS_DIV_1; + assign _zz__zz_decode_IS_DIV_149 = ((decode_INSTRUCTION & 32'h00001048) == 32'h00001008); + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_161 ), //i - .io_cpu_prefetch_isValid (_zz_162 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_163 ), //i - .io_cpu_fetch_isStuck (_zz_164 ), //i - .io_cpu_fetch_isRemoved (_zz_165 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_166 ), //i - .io_cpu_decode_isStuck (_zz_167 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_168 ), //i - .io_cpu_fill_valid (_zz_169 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_149[2:0] ), //i - ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i + ._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_305) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_5) 2'b00 : begin - _zz_172 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = CsrPlugin_jumpInterface_payload; end 2'b01 : begin - _zz_172 = DBusSimplePlugin_redoBranch_payload; - end - 2'b10 : begin - _zz_172 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_172 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = IBusCachedPlugin_predictionJumpInterface_payload; end endcase end `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_10) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_10_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_10_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_10_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_10_string = "SRA_1 "; - default : _zz_10_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_13) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_13_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_13_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_13_string = "AND_1"; - default : _zz_13_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_14) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; - default : _zz_14_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_16) - `Src2CtrlEnum_defaultEncoding_RS : _zz_16_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_16_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_16_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_16_string = "PC "; - default : _zz_16_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_17) - `Src2CtrlEnum_defaultEncoding_RS : _zz_17_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_17_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_17_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_17_string = "PC "; - default : _zz_17_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_19) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_19_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_19_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_19_string = "BITWISE "; - default : _zz_19_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_20) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; - default : _zz_20_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_22) - `Src1CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_22_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_22_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_22_string = "URS1 "; - default : _zz_22_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_23) - `Src1CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_23_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_23_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_23_string = "URS1 "; - default : _zz_23_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_25) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_25_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_25_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_25_string = "ECALL"; - default : _zz_25_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_26) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26_string = "ECALL"; - default : _zz_26_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_28) - `BranchCtrlEnum_defaultEncoding_INC : _zz_28_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_28_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_28_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_28_string = "JALR"; - default : _zz_28_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_31) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_31_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_31_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_31_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_31_string = "SRA_1 "; - default : _zz_31_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_33) - `Src2CtrlEnum_defaultEncoding_RS : _zz_33_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_33_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_33_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_33_string = "PC "; - default : _zz_33_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_34) - `Src1CtrlEnum_defaultEncoding_RS : _zz_34_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_34_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34_string = "URS1 "; - default : _zz_34_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_35) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_35_string = "BITWISE "; - default : _zz_35_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_36) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_36_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_36_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_36_string = "AND_1"; - default : _zz_36_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_40) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_40_string = "ECALL"; - default : _zz_40_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_41) - `BranchCtrlEnum_defaultEncoding_INC : _zz_41_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_41_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_41_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_41_string = "JALR"; - default : _zz_41_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_42) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_42_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_42_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_42_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_42_string = "SRA_1 "; - default : _zz_42_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_43) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; - default : _zz_43_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `Src2CtrlEnum_defaultEncoding_RS : _zz_44_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_44_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_44_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_44_string = "PC "; - default : _zz_44_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_45) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; - default : _zz_45_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_46) - `Src1CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_46_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_46_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_46_string = "URS1 "; - default : _zz_46_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_48) - `BranchCtrlEnum_defaultEncoding_INC : _zz_48_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_48_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_48_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_48_string = "JALR"; - default : _zz_48_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_91) - `Src1CtrlEnum_defaultEncoding_RS : _zz_91_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_91_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_91_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_91_string = "URS1 "; - default : _zz_91_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_92) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_92_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_92_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_92_string = "BITWISE "; - default : _zz_92_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_93) - `Src2CtrlEnum_defaultEncoding_RS : _zz_93_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_93_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_93_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_93_string = "PC "; - default : _zz_93_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_94) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_94_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_94_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_94_string = "AND_1"; - default : _zz_94_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_95) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_95_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_95_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_95_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_95_string = "SRA_1 "; - default : _zz_95_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_96) - `BranchCtrlEnum_defaultEncoding_INC : _zz_96_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_96_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_96_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_96_string = "JALR"; - default : _zz_96_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_97) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_97_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_97_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_97_string = "ECALL"; - default : _zz_97_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end @@ -2193,7 +2188,7 @@ module VexRiscv ( assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_99; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); @@ -2201,37 +2196,39 @@ module VexRiscv ( assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_DIV = _zz_216[0]; - assign decode_IS_RS2_SIGNED = _zz_217[0]; - assign decode_IS_RS1_SIGNED = _zz_218[0]; - assign decode_IS_MUL = _zz_219[0]; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_220[0]; - assign _zz_8 = _zz_9; - assign decode_SHIFT_CTRL = _zz_10; - assign _zz_11 = _zz_12; - assign decode_ALU_BITWISE_CTRL = _zz_13; - assign _zz_14 = _zz_15; - assign decode_SRC_LESS_UNSIGNED = _zz_221[0]; - assign decode_MEMORY_STORE = _zz_222[0]; + assign decode_IS_DIV = _zz_decode_IS_DIV[30]; + assign decode_IS_RS2_SIGNED = _zz_decode_IS_DIV[29]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_DIV[28]; + assign decode_IS_MUL = _zz_decode_IS_DIV[27]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_DIV[24]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_DIV[16]; + assign decode_MEMORY_STORE = _zz_decode_IS_DIV[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_223[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_224[0]; - assign decode_SRC2_CTRL = _zz_16; - assign _zz_17 = _zz_18; - assign decode_ALU_CTRL = _zz_19; - assign _zz_20 = _zz_21; - assign decode_SRC1_CTRL = _zz_22; - assign _zz_23 = _zz_24; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_DIV[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_DIV[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_ENABLE = _zz_decode_IS_DIV[4]; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_225[0]; + assign decode_IS_EBREAK = _zz_decode_IS_DIV[31]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_MUL = decode_to_execute_IS_MUL; @@ -2241,27 +2238,27 @@ module VexRiscv ( assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_25; - assign execute_ENV_CTRL = _zz_26; - assign writeBack_ENV_CTRL = _zz_27; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_120; - assign execute_BRANCH_CTRL = _zz_28; - assign decode_RS2_USE = _zz_226[0]; - assign decode_RS1_USE = _zz_227[0]; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_DIV[15]; + assign decode_RS1_USE = _zz_decode_IS_DIV[5]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; - always @ (*) begin - _zz_29 = memory_REGFILE_WRITE_DATA; - if(_zz_173)begin - _zz_29 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); + always @(*) begin + _zz_decode_RS2 = memory_REGFILE_WRITE_DATA; + if(when_MulDivIterativePlugin_l96) begin + _zz_decode_RS2 = ((memory_INSTRUCTION[13 : 12] == 2'b00) ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_accumulator[63 : 32]); end - if(_zz_174)begin - _zz_29 = memory_MulDivIterativePlugin_div_result; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2 = memory_MulDivIterativePlugin_div_result; end end @@ -2269,209 +2266,181 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_109)begin - if((_zz_110 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_111; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_175)begin - if(_zz_176)begin - if(_zz_113)begin - decode_RS2 = _zz_47; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_177)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_115)begin - decode_RS2 = _zz_29; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2; end end end - if(_zz_178)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_117)begin - decode_RS2 = _zz_30; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2_1; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_109)begin - if((_zz_110 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_111; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_175)begin - if(_zz_176)begin - if(_zz_112)begin - decode_RS1 = _zz_47; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_177)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_114)begin - decode_RS1 = _zz_29; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2; end end end - if(_zz_178)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_116)begin - decode_RS1 = _zz_30; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2_1; end end end end - always @ (*) begin - _zz_30 = execute_REGFILE_WRITE_DATA; - if(_zz_179)begin - _zz_30 = _zz_106; + always @(*) begin + _zz_decode_RS2_1 = execute_REGFILE_WRITE_DATA; + if(when_ShiftPlugins_l169) begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - if(_zz_180)begin - _zz_30 = execute_CsrPlugin_readData; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2_1 = CsrPlugin_csrMapping_readDataSignal; end end - assign execute_SHIFT_CTRL = _zz_31; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_32 = execute_PC; - assign execute_SRC2_CTRL = _zz_33; - assign execute_SRC1_CTRL = _zz_34; - assign decode_SRC_USE_SUB_LESS = _zz_228[0]; - assign decode_SRC_ADD_ZERO = _zz_229[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_DIV[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_DIV[19]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_35; - assign execute_SRC2 = _zz_105; - assign execute_SRC1 = _zz_100; - assign execute_ALU_BITWISE_CTRL = _zz_36; - assign _zz_37 = writeBack_INSTRUCTION; - assign _zz_38 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_39 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_39 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_230[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_DIV[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_306) == 32'h00001073),{(_zz_307 == _zz_308),{_zz_309,{_zz_310,_zz_311}}}}}}} != 20'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; - always @ (*) begin - _zz_47 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_47 = writeBack_DBusSimplePlugin_rspFormated; + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusSimplePlugin_l558) begin + _zz_decode_RS2_2 = writeBack_DBusSimplePlugin_rspFormated; end end assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; - assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; - assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; - assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; - assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; - assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; - assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; - assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; - assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; - assign memory_PC = execute_to_memory_PC; assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); - assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; - assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; - assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; - assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_231[0]; - assign decode_FLUSH_ALL = _zz_232[0]; - always @ (*) begin + assign decode_FLUSH_ALL = _zz_decode_IS_DIV[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_181)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_182)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_183)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_184)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_48; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_49 = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_49 = DBusSimplePlugin_redoBranch_payload; - end - if(BranchPlugin_jumpInterface_valid)begin - _zz_49 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_50 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_50 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin - decode_arbitration_haltItself = 1'b1; - end - case(_zz_149) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2480,162 +2449,153 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_107 || _zz_108)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_185)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_185)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_77)))begin + if(when_DBusSimplePlugin_l426) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_179)begin - if((! execute_LightShifterPlugin_done))begin + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l184) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_180)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_186)begin + if(when_DebugPlugin_l284) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_186)begin - if(_zz_187)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushIt = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_186)begin - if(_zz_187)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushNext = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + if(when_DBusSimplePlugin_l479) begin memory_arbitration_haltItself = 1'b1; end - if(_zz_173)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)))begin + if(when_MulDivIterativePlugin_l96) begin + if(when_MulDivIterativePlugin_l97) begin memory_arbitration_haltItself = 1'b1; end - if(_zz_188)begin + if(when_MulDivIterativePlugin_l100) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_174)begin - if(((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_189)begin + if(_zz_when_1) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end - always @ (*) begin - memory_arbitration_flushIt = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(_zz_189)begin + if(_zz_when_1) begin memory_arbitration_flushNext = 1'b1; end end assign writeBack_arbitration_haltItself = 1'b0; assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end assign writeBack_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_190)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_191)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2644,62 +2604,64 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_190)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_191)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_186)begin - if(_zz_187)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_192)begin + if(when_DebugPlugin_l300) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; assign CsrPlugin_inWfi = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin CsrPlugin_thirdPartyWake = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_190)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_191)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_190)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_191)begin - case(_zz_193) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2709,80 +2671,91 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_forceMachineWire = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + if(when_DebugPlugin_l316) begin CsrPlugin_allowInterrupts = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_allowException = 1'b0; end end + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_51 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}}; - assign _zz_52 = (_zz_51 & (~ _zz_233)); - assign _zz_53 = _zz_52[3]; - assign _zz_54 = (_zz_52[1] || _zz_53); - assign _zz_55 = (_zz_52[2] || _zz_53); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_172; - always @ (*) begin + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,IBusCachedPlugin_predictionJumpInterface_valid}} != 3'b000); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[1]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_235); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -2790,66 +2763,75 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_56 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_56); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_56); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_57 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_57); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_57); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_58 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_58); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_58); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_59; - assign _zz_59 = ((1'b0 && (! _zz_60)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_60 = _zz_61; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_60; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_62)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_62 = _zz_63; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_62; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_64; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); - always @ (*) begin + always @(*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_149) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -2861,287 +2843,265 @@ module VexRiscv ( endcase end - assign _zz_65 = _zz_236[11]; - always @ (*) begin - _zz_66[18] = _zz_65; - _zz_66[17] = _zz_65; - _zz_66[16] = _zz_65; - _zz_66[15] = _zz_65; - _zz_66[14] = _zz_65; - _zz_66[13] = _zz_65; - _zz_66[12] = _zz_65; - _zz_66[11] = _zz_65; - _zz_66[10] = _zz_65; - _zz_66[9] = _zz_65; - _zz_66[8] = _zz_65; - _zz_66[7] = _zz_65; - _zz_66[6] = _zz_65; - _zz_66[5] = _zz_65; - _zz_66[4] = _zz_65; - _zz_66[3] = _zz_65; - _zz_66[2] = _zz_65; - _zz_66[1] = _zz_65; - _zz_66[0] = _zz_65; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_237[31])); - if(_zz_71)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_67 = _zz_238[19]; - always @ (*) begin - _zz_68[10] = _zz_67; - _zz_68[9] = _zz_67; - _zz_68[8] = _zz_67; - _zz_68[7] = _zz_67; - _zz_68[6] = _zz_67; - _zz_68[5] = _zz_67; - _zz_68[4] = _zz_67; - _zz_68[3] = _zz_67; - _zz_68[2] = _zz_67; - _zz_68[1] = _zz_67; - _zz_68[0] = _zz_67; - end - - assign _zz_69 = _zz_239[11]; - always @ (*) begin - _zz_70[18] = _zz_69; - _zz_70[17] = _zz_69; - _zz_70[16] = _zz_69; - _zz_70[15] = _zz_69; - _zz_70[14] = _zz_69; - _zz_70[13] = _zz_69; - _zz_70[12] = _zz_69; - _zz_70[11] = _zz_69; - _zz_70[10] = _zz_69; - _zz_70[9] = _zz_69; - _zz_70[8] = _zz_69; - _zz_70[7] = _zz_69; - _zz_70[6] = _zz_69; - _zz_70[5] = _zz_69; - _zz_70[4] = _zz_69; - _zz_70[3] = _zz_69; - _zz_70[2] = _zz_69; - _zz_70[1] = _zz_69; - _zz_70[0] = _zz_69; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_71 = _zz_240[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_71 = _zz_241[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_72 = _zz_242[19]; - always @ (*) begin - _zz_73[10] = _zz_72; - _zz_73[9] = _zz_72; - _zz_73[8] = _zz_72; - _zz_73[7] = _zz_72; - _zz_73[6] = _zz_72; - _zz_73[5] = _zz_72; - _zz_73[4] = _zz_72; - _zz_73[3] = _zz_72; - _zz_73[2] = _zz_72; - _zz_73[1] = _zz_72; - _zz_73[0] = _zz_72; - end - - assign _zz_74 = _zz_243[11]; - always @ (*) begin - _zz_75[18] = _zz_74; - _zz_75[17] = _zz_74; - _zz_75[16] = _zz_74; - _zz_75[15] = _zz_74; - _zz_75[14] = _zz_74; - _zz_75[13] = _zz_74; - _zz_75[12] = _zz_74; - _zz_75[11] = _zz_74; - _zz_75[10] = _zz_74; - _zz_75[9] = _zz_74; - _zz_75[8] = _zz_74; - _zz_75[7] = _zz_74; - _zz_75[6] = _zz_74; - _zz_75[5] = _zz_74; - _zz_75[4] = _zz_74; - _zz_75[3] = _zz_74; - _zz_75[2] = _zz_74; - _zz_75[1] = _zz_74; - _zz_75[0] = _zz_74; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_73,{{{_zz_324,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_75,{{{_zz_325,_zz_326},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_162 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_163 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_164 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_163; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_166 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_167 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_168 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_184)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_182)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_169 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_182)begin - _zz_169 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_183)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_181)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_183)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_181)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_161 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign _zz_77 = 1'b0; - always @ (*) begin + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_dBus_cmd_valid = 1'b0; + always @(*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; - if(execute_ALIGNEMENT_FAULT)begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin + if(execute_ALIGNEMENT_FAULT) begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_77)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_78 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_dBus_cmd_payload_data = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_78 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_dBus_cmd_payload_data = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_78 = execute_RS2[31 : 0]; + _zz_dBus_cmd_payload_data = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_78; - always @ (*) begin + assign dBus_cmd_payload_data = _zz_dBus_cmd_payload_data; + assign when_DBusSimplePlugin_l426 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_79 = 4'b0001; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0001; end 2'b01 : begin - _zz_79 = 4'b0011; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0011; end default : begin - _zz_79 = 4'b1111; + _zz_execute_DBusSimplePlugin_formalMask = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_79 <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; - assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - always @ (*) begin + assign execute_DBusSimplePlugin_formalMask = (_zz_execute_DBusSimplePlugin_formalMask <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign when_DBusSimplePlugin_l479 = (((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)); + always @(*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_194)begin + if(when_DBusSimplePlugin_l486) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_ALIGNEMENT_FAULT)begin + if(memory_ALIGNEMENT_FAULT) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end else begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - end - if(_zz_195)begin + if(when_DBusSimplePlugin_l512) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end - always @ (*) begin + always @(*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_194)begin + if(when_DBusSimplePlugin_l486) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_244}; - end - if(! memory_MMU_RSP2_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); - end + if(memory_ALIGNEMENT_FAULT) begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_DBusSimplePlugin_memoryExceptionPort_payload_code}; end end assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; - always @ (*) begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_redoBranch_valid = 1'b1; - end - if(_zz_195)begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - end - end - - assign DBusSimplePlugin_redoBranch_payload = memory_PC; - always @ (*) begin + assign when_DBusSimplePlugin_l486 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign when_DBusSimplePlugin_l512 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + always @(*) begin writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin @@ -3158,63 +3118,64 @@ module VexRiscv ( endcase end - assign _zz_80 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_81[31] = _zz_80; - _zz_81[30] = _zz_80; - _zz_81[29] = _zz_80; - _zz_81[28] = _zz_80; - _zz_81[27] = _zz_80; - _zz_81[26] = _zz_80; - _zz_81[25] = _zz_80; - _zz_81[24] = _zz_80; - _zz_81[23] = _zz_80; - _zz_81[22] = _zz_80; - _zz_81[21] = _zz_80; - _zz_81[20] = _zz_80; - _zz_81[19] = _zz_80; - _zz_81[18] = _zz_80; - _zz_81[17] = _zz_80; - _zz_81[16] = _zz_80; - _zz_81[15] = _zz_80; - _zz_81[14] = _zz_80; - _zz_81[13] = _zz_80; - _zz_81[12] = _zz_80; - _zz_81[11] = _zz_80; - _zz_81[10] = _zz_80; - _zz_81[9] = _zz_80; - _zz_81[8] = _zz_80; - _zz_81[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_82 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_83[31] = _zz_82; - _zz_83[30] = _zz_82; - _zz_83[29] = _zz_82; - _zz_83[28] = _zz_82; - _zz_83[27] = _zz_82; - _zz_83[26] = _zz_82; - _zz_83[25] = _zz_82; - _zz_83[24] = _zz_82; - _zz_83[23] = _zz_82; - _zz_83[22] = _zz_82; - _zz_83[21] = _zz_82; - _zz_83[20] = _zz_82; - _zz_83[19] = _zz_82; - _zz_83[18] = _zz_82; - _zz_83[17] = _zz_82; - _zz_83[16] = _zz_82; - _zz_83[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_214) + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusSimplePlugin_rspFormated = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_1[31] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[30] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[29] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[28] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[27] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[26] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[25] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[24] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[23] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[22] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[21] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[20] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[19] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[18] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[17] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[16] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[15] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[14] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[13] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[12] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[11] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[10] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[9] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[8] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_writeBack_DBusSimplePlugin_rspFormated_2 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_3[31] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[30] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[29] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[28] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[27] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[26] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[25] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[24] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[23] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[22] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[21] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[20] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[19] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[18] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[17] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[16] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_81; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_83; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_3; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -3222,6 +3183,7 @@ module VexRiscv ( endcase end + assign when_DBusSimplePlugin_l558 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3231,70 +3193,62 @@ module VexRiscv ( assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign IBusCachedPlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_85 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_86 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_87 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_88 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_89 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); - assign _zz_90 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); - assign _zz_84 = {(((decode_INSTRUCTION & _zz_327) == 32'h00100050) != 1'b0),{((_zz_328 == _zz_329) != 1'b0),{({_zz_330,_zz_331} != 2'b00),{(_zz_332 != _zz_333),{_zz_334,{_zz_335,_zz_336}}}}}}; - assign _zz_91 = _zz_84[2 : 1]; - assign _zz_46 = _zz_91; - assign _zz_92 = _zz_84[7 : 6]; - assign _zz_45 = _zz_92; - assign _zz_93 = _zz_84[9 : 8]; - assign _zz_44 = _zz_93; - assign _zz_94 = _zz_84[18 : 17]; - assign _zz_43 = _zz_94; - assign _zz_95 = _zz_84[21 : 20]; - assign _zz_42 = _zz_95; - assign _zz_96 = _zz_84[23 : 22]; - assign _zz_41 = _zz_96; - assign _zz_97 = _zz_84[26 : 25]; - assign _zz_40 = _zz_97; + assign _zz_decode_IS_DIV_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_DIV_2 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_DIV_3 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_DIV_4 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz_decode_IS_DIV_5 = ((decode_INSTRUCTION & 32'h00007000) == 32'h00001000); + assign _zz_decode_IS_DIV_6 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00004000); + assign _zz_decode_IS_DIV = {(((decode_INSTRUCTION & _zz__zz_decode_IS_DIV) == 32'h00100050) != 1'b0),{((_zz__zz_decode_IS_DIV_1 == _zz__zz_decode_IS_DIV_2) != 1'b0),{({_zz__zz_decode_IS_DIV_3,_zz__zz_decode_IS_DIV_4} != 2'b00),{(_zz__zz_decode_IS_DIV_5 != _zz__zz_decode_IS_DIV_6),{_zz__zz_decode_IS_DIV_7,{_zz__zz_decode_IS_DIV_9,_zz__zz_decode_IS_DIV_12}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_DIV[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_DIV[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_DIV[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_DIV[18 : 17]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_DIV[21 : 20]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_DIV[23 : 22]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_DIV[26 : 25]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_170; - assign decode_RegFilePlugin_rs2Data = _zz_171; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); - if(_zz_98)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_37[11 : 7]; - if(_zz_98)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_47; - if(_zz_98)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3303,298 +3257,324 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_99 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_99 = {31'd0, _zz_245}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_99 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_100 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_100 = {29'd0, _zz_246}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_100 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_100 = {27'd0, _zz_247}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_101 = _zz_248[11]; - always @ (*) begin - _zz_102[19] = _zz_101; - _zz_102[18] = _zz_101; - _zz_102[17] = _zz_101; - _zz_102[16] = _zz_101; - _zz_102[15] = _zz_101; - _zz_102[14] = _zz_101; - _zz_102[13] = _zz_101; - _zz_102[12] = _zz_101; - _zz_102[11] = _zz_101; - _zz_102[10] = _zz_101; - _zz_102[9] = _zz_101; - _zz_102[8] = _zz_101; - _zz_102[7] = _zz_101; - _zz_102[6] = _zz_101; - _zz_102[5] = _zz_101; - _zz_102[4] = _zz_101; - _zz_102[3] = _zz_101; - _zz_102[2] = _zz_101; - _zz_102[1] = _zz_101; - _zz_102[0] = _zz_101; - end - - assign _zz_103 = _zz_249[11]; - always @ (*) begin - _zz_104[19] = _zz_103; - _zz_104[18] = _zz_103; - _zz_104[17] = _zz_103; - _zz_104[16] = _zz_103; - _zz_104[15] = _zz_103; - _zz_104[14] = _zz_103; - _zz_104[13] = _zz_103; - _zz_104[12] = _zz_103; - _zz_104[11] = _zz_103; - _zz_104[10] = _zz_103; - _zz_104[9] = _zz_103; - _zz_104[8] = _zz_103; - _zz_104[7] = _zz_103; - _zz_104[6] = _zz_103; - _zz_104[5] = _zz_103; - _zz_104[4] = _zz_103; - _zz_104[3] = _zz_103; - _zz_104[2] = _zz_103; - _zz_104[1] = _zz_103; - _zz_104[0] = _zz_103; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_105 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_105 = {_zz_104,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_105 = _zz_32; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_250; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_binary_sequential_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); - always @ (*) begin + assign when_ShiftPlugins_l169 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_106 = (execute_LightShifterPlugin_shiftInput <<< 1); + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_3 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_106 = _zz_257; + _zz_decode_RS2_3 = _zz__zz_decode_RS2_3; end endcase end - always @ (*) begin - _zz_107 = 1'b0; - if(_zz_196)begin - if(_zz_197)begin - if(_zz_112)begin - _zz_107 = 1'b1; + assign when_ShiftPlugins_l175 = (! execute_arbitration_isStuckByOthers); + assign when_ShiftPlugins_l184 = (! execute_LightShifterPlugin_done); + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_198)begin - if(_zz_199)begin - if(_zz_114)begin - _zz_107 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_200)begin - if(_zz_201)begin - if(_zz_116)begin - _zz_107 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_107 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_108 = 1'b0; - if(_zz_196)begin - if(_zz_197)begin - if(_zz_113)begin - _zz_108 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_198)begin - if(_zz_199)begin - if(_zz_115)begin - _zz_108 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_200)begin - if(_zz_201)begin - if(_zz_117)begin - _zz_108 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_108 = 1'b0; - end - end - - assign _zz_112 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_113 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_114 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_115 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_116 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_117 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_118 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_118 == 3'b000)) begin - _zz_119 = execute_BranchPlugin_eq; - end else if((_zz_118 == 3'b001)) begin - _zz_119 = (! execute_BranchPlugin_eq); - end else if((((_zz_118 & 3'b101) == 3'b101))) begin - _zz_119 = (! execute_SRC_LESS); - end else begin - _zz_119 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_120 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_120 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_120 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_120 = _zz_119; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_121 = _zz_259[11]; - always @ (*) begin - _zz_122[19] = _zz_121; - _zz_122[18] = _zz_121; - _zz_122[17] = _zz_121; - _zz_122[16] = _zz_121; - _zz_122[15] = _zz_121; - _zz_122[14] = _zz_121; - _zz_122[13] = _zz_121; - _zz_122[12] = _zz_121; - _zz_122[11] = _zz_121; - _zz_122[10] = _zz_121; - _zz_122[9] = _zz_121; - _zz_122[8] = _zz_121; - _zz_122[7] = _zz_121; - _zz_122[6] = _zz_121; - _zz_122[5] = _zz_121; - _zz_122[4] = _zz_121; - _zz_122[3] = _zz_121; - _zz_122[2] = _zz_121; - _zz_122[1] = _zz_121; - _zz_122[0] = _zz_121; - end - - assign _zz_123 = _zz_260[19]; - always @ (*) begin - _zz_124[10] = _zz_123; - _zz_124[9] = _zz_123; - _zz_124[8] = _zz_123; - _zz_124[7] = _zz_123; - _zz_124[6] = _zz_123; - _zz_124[5] = _zz_123; - _zz_124[4] = _zz_123; - _zz_124[3] = _zz_123; - _zz_124[2] = _zz_123; - _zz_124[1] = _zz_123; - _zz_124[0] = _zz_123; - end - - assign _zz_125 = _zz_261[11]; - always @ (*) begin - _zz_126[18] = _zz_125; - _zz_126[17] = _zz_125; - _zz_126[16] = _zz_125; - _zz_126[15] = _zz_125; - _zz_126[14] = _zz_125; - _zz_126[13] = _zz_125; - _zz_126[12] = _zz_125; - _zz_126[11] = _zz_125; - _zz_126[10] = _zz_125; - _zz_126[9] = _zz_125; - _zz_126[8] = _zz_125; - _zz_126[7] = _zz_125; - _zz_126[6] = _zz_125; - _zz_126[5] = _zz_125; - _zz_126[4] = _zz_125; - _zz_126[3] = _zz_125; - _zz_126[2] = _zz_125; - _zz_126[1] = _zz_125; - _zz_126[0] = _zz_125; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_127 = (_zz_262[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_127 = _zz_263[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_127 = _zz_264[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_127); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -3603,80 +3583,80 @@ module VexRiscv ( endcase end - assign _zz_128 = _zz_265[11]; - always @ (*) begin - _zz_129[19] = _zz_128; - _zz_129[18] = _zz_128; - _zz_129[17] = _zz_128; - _zz_129[16] = _zz_128; - _zz_129[15] = _zz_128; - _zz_129[14] = _zz_128; - _zz_129[13] = _zz_128; - _zz_129[12] = _zz_128; - _zz_129[11] = _zz_128; - _zz_129[10] = _zz_128; - _zz_129[9] = _zz_128; - _zz_129[8] = _zz_128; - _zz_129[7] = _zz_128; - _zz_129[6] = _zz_128; - _zz_129[5] = _zz_128; - _zz_129[4] = _zz_128; - _zz_129[3] = _zz_128; - _zz_129[2] = _zz_128; - _zz_129[1] = _zz_128; - _zz_129[0] = _zz_128; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_129,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_131,{{{_zz_477,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_133,{{{_zz_478,_zz_479},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_268}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_130 = _zz_266[19]; - always @ (*) begin - _zz_131[10] = _zz_130; - _zz_131[9] = _zz_130; - _zz_131[8] = _zz_130; - _zz_131[7] = _zz_130; - _zz_131[6] = _zz_130; - _zz_131[5] = _zz_130; - _zz_131[4] = _zz_130; - _zz_131[3] = _zz_130; - _zz_131[2] = _zz_130; - _zz_131[1] = _zz_130; - _zz_131[0] = _zz_130; - end - - assign _zz_132 = _zz_267[11]; - always @ (*) begin - _zz_133[18] = _zz_132; - _zz_133[17] = _zz_132; - _zz_133[16] = _zz_132; - _zz_133[15] = _zz_132; - _zz_133[14] = _zz_132; - _zz_133[13] = _zz_132; - _zz_133[12] = _zz_132; - _zz_133[11] = _zz_132; - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); @@ -3686,94 +3666,108 @@ module VexRiscv ( assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_134 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_135 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_136 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_137 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_138 = _zz_269[0]; - assign _zz_139 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_140 = _zz_271[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_185)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_189)begin + if(_zz_when_1) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -3784,8 +3778,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3795,72 +3789,79 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_202)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_203)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_203)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3873,115 +3874,136 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_202)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_202)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_215) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; assign memory_MulDivIterativePlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b0; - if(_zz_173)begin - if(_zz_188)begin + if(when_MulDivIterativePlugin_l96) begin + if(when_MulDivIterativePlugin_l100) begin memory_MulDivIterativePlugin_mul_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_MulDivIterativePlugin_mul_counter_willClear = 1'b0; - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l110) begin memory_MulDivIterativePlugin_mul_counter_willClear = 1'b1; end end assign memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_mul_counter_value == 6'h20); assign memory_MulDivIterativePlugin_mul_counter_willOverflow = (memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc && memory_MulDivIterativePlugin_mul_counter_willIncrement); - always @ (*) begin - if(memory_MulDivIterativePlugin_mul_counter_willOverflow)begin + always @(*) begin + if(memory_MulDivIterativePlugin_mul_counter_willOverflow) begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_274); + memory_MulDivIterativePlugin_mul_counter_valueNext = (memory_MulDivIterativePlugin_mul_counter_value + _zz_memory_MulDivIterativePlugin_mul_counter_valueNext); end - if(memory_MulDivIterativePlugin_mul_counter_willClear)begin + if(memory_MulDivIterativePlugin_mul_counter_willClear) begin memory_MulDivIterativePlugin_mul_counter_valueNext = 6'h0; end end - always @ (*) begin + assign when_MulDivIterativePlugin_l96 = (memory_arbitration_isValid && memory_IS_MUL); + assign when_MulDivIterativePlugin_l97 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign when_MulDivIterativePlugin_l100 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_mul_counter_willOverflowIfInc)); + assign when_MulDivIterativePlugin_l110 = (! memory_arbitration_isStuck); + always @(*) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b0; - if(_zz_174)begin - if(_zz_204)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_MulDivIterativePlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b0; - if(_zz_205)begin + if(when_MulDivIterativePlugin_l162) begin memory_MulDivIterativePlugin_div_counter_willClear = 1'b1; end end assign memory_MulDivIterativePlugin_div_counter_willOverflowIfInc = (memory_MulDivIterativePlugin_div_counter_value == 6'h21); assign memory_MulDivIterativePlugin_div_counter_willOverflow = (memory_MulDivIterativePlugin_div_counter_willOverflowIfInc && memory_MulDivIterativePlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_MulDivIterativePlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_MulDivIterativePlugin_div_counter_willOverflow) begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end else begin - memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_282); + memory_MulDivIterativePlugin_div_counter_valueNext = (memory_MulDivIterativePlugin_div_counter_value + _zz_memory_MulDivIterativePlugin_div_counter_valueNext); end - if(memory_MulDivIterativePlugin_div_counter_willClear)begin + if(memory_MulDivIterativePlugin_div_counter_willClear) begin memory_MulDivIterativePlugin_div_counter_valueNext = 6'h0; end end - assign _zz_141 = memory_MulDivIterativePlugin_rs1[31 : 0]; - assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_141[31]}; - assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_283); - assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_284 : _zz_285); - assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_286[31:0]; - assign _zz_142 = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); - assign _zz_143 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_144 = ((execute_IS_MUL && _zz_143) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_145[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_145[31 : 0] = execute_RS1; + assign when_MulDivIterativePlugin_l126 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_MulDivIterativePlugin_frontendOk) || (! memory_MulDivIterativePlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_MulDivIterativePlugin_frontendOk && (! memory_MulDivIterativePlugin_div_done)); + assign _zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted = memory_MulDivIterativePlugin_rs1[31 : 0]; + assign memory_MulDivIterativePlugin_div_stage_0_remainderShifted = {memory_MulDivIterativePlugin_accumulator[31 : 0],_zz_memory_MulDivIterativePlugin_div_stage_0_remainderShifted[31]}; + assign memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator = (memory_MulDivIterativePlugin_div_stage_0_remainderShifted - _zz_memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator); + assign memory_MulDivIterativePlugin_div_stage_0_outRemainder = ((! memory_MulDivIterativePlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder : _zz_memory_MulDivIterativePlugin_div_stage_0_outRemainder_1); + assign memory_MulDivIterativePlugin_div_stage_0_outNumerator = _zz_memory_MulDivIterativePlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_MulDivIterativePlugin_div_counter_value == 6'h20); + assign _zz_memory_MulDivIterativePlugin_div_result = (memory_INSTRUCTION[13] ? memory_MulDivIterativePlugin_accumulator[31 : 0] : memory_MulDivIterativePlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_MulDivIterativePlugin_rs1 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_MulDivIterativePlugin_rs1_1 = ((execute_IS_MUL && _zz_memory_MulDivIterativePlugin_rs1) || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_MulDivIterativePlugin_rs1_2[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_MulDivIterativePlugin_rs1_2[31 : 0] = execute_RS1; end - assign _zz_147 = (_zz_146 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_147 != 32'h0); - always @ (*) begin + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_206) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end end @@ -3991,9 +4013,9 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_148))begin + if(when_DebugPlugin_l244) begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4002,12 +4024,13 @@ module VexRiscv ( end end - always @ (*) begin + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_206) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin IBusCachedPlugin_injectionPort_valid = 1'b1; end end @@ -4018,33 +4041,99 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_24 = decode_SRC1_CTRL; - assign _zz_22 = _zz_46; - assign _zz_34 = decode_to_execute_SRC1_CTRL; - assign _zz_21 = decode_ALU_CTRL; - assign _zz_19 = _zz_45; - assign _zz_35 = decode_to_execute_ALU_CTRL; - assign _zz_18 = decode_SRC2_CTRL; - assign _zz_16 = _zz_44; - assign _zz_33 = decode_to_execute_SRC2_CTRL; - assign _zz_15 = decode_ALU_BITWISE_CTRL; - assign _zz_13 = _zz_43; - assign _zz_36 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_12 = decode_SHIFT_CTRL; - assign _zz_10 = _zz_42; - assign _zz_31 = decode_to_execute_SHIFT_CTRL; - assign _zz_9 = decode_BRANCH_CTRL; - assign _zz_48 = _zz_41; - assign _zz_28 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_40; - assign _zz_26 = decode_to_execute_ENV_CTRL; - assign _zz_25 = execute_to_memory_ENV_CTRL; - assign _zz_27 = memory_to_writeBack_ENV_CTRL; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_31 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_32 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_49 = ((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)); + assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4065,9 +4154,15 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_149) + case(switch_Fetcher_l362) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4076,124 +4171,139 @@ module VexRiscv ( endcase end - always @ (*) begin - _zz_150 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_150[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_150[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_150[3 : 3] = CsrPlugin_mstatus_MIE; + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_151 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_151[11 : 11] = CsrPlugin_mip_MEIP; - _zz_151[7 : 7] = CsrPlugin_mip_MTIP; - _zz_151[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_152 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_152[11 : 11] = CsrPlugin_mie_MEIE; - _zz_152[7 : 7] = CsrPlugin_mie_MTIE; - _zz_152[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_153 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_153[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_154 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_154[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_154[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_155 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_155[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_156 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_156[31 : 0] = _zz_146; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_157 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_157[31 : 0] = _zz_147; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = (((_zz_150 | _zz_151) | (_zz_152 | _zz_153)) | ((_zz_154 | _zz_155) | (_zz_156 | _zz_157))); - assign iBusWishbone_ADR = {_zz_302,_zz_158}; - assign iBusWishbone_CTI = ((_zz_158 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_207)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_207)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_159; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; - assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; - assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; - assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; - assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; - assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBus_cmd_halfPipe_fire = (dBus_cmd_halfPipe_valid && dBus_cmd_halfPipe_ready); + assign dBus_cmd_ready = (! dBus_cmd_rValid); + assign dBus_cmd_halfPipe_valid = dBus_cmd_rValid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_rData_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_rData_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_rData_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_rData_size; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); assign dBusWishbone_CTI = 3'b000; assign dBusWishbone_BTE = 2'b00; - always @ (*) begin + always @(*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_160 = 4'b0001; + _zz_dBusWishbone_SEL = 4'b0001; end 2'b01 : begin - _zz_160 = 4'b0011; + _zz_dBusWishbone_SEL = 4'b0011; end default : begin - _zz_160 = 4'b1111; + _zz_dBusWishbone_SEL = 4'b1111; end endcase end - always @ (*) begin - dBusWishbone_SEL = (_zz_160 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - if((! dBus_cmd_halfPipe_payload_wr))begin + always @(*) begin + dBusWishbone_SEL = (_zz_dBusWishbone_SEL <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + if(when_DBusSimplePlugin_l189) begin dBusWishbone_SEL = 4'b1111; end end + assign when_DBusSimplePlugin_l189 = (! dBus_cmd_halfPipe_payload_wr); assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); @@ -4202,24 +4312,24 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_61 <= 1'b0; - _zz_63 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_76; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; - _zz_98 <= 1'b1; + _zz_7 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_109 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -4238,90 +4348,89 @@ module VexRiscv ( execute_CsrPlugin_wfiWake <= 1'b0; memory_MulDivIterativePlugin_mul_counter_value <= 6'h0; memory_MulDivIterativePlugin_div_counter_value <= 6'h0; - _zz_146 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_149 <= 3'b000; - _zz_158 <= 3'b000; - _zz_159 <= 1'b0; - dBus_cmd_halfPipe_regs_valid <= 1'b0; - dBus_cmd_halfPipe_regs_ready <= 1'b1; + switch_Fetcher_l362 <= 3'b000; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + dBus_cmd_rValid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_61 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_59)begin - _zz_61 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_63 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_63 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end `ifndef SYNTHESIS @@ -4344,72 +4453,72 @@ module VexRiscv ( end `endif `endif - _zz_98 <= 1'b0; - if(_zz_179)begin - if(_zz_208)begin + _zz_7 <= 1'b0; + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l175) begin execute_LightShifterPlugin_isActive <= 1'b1; - if(execute_LightShifterPlugin_done)begin + if(execute_LightShifterPlugin_done) begin execute_LightShifterPlugin_isActive <= 1'b0; end end end - if(execute_arbitration_removeIt)begin + if(execute_arbitration_removeIt) begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_109 <= (_zz_38 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_209)begin - if(_zz_210)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_211)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_212)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_190)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -4420,8 +4529,8 @@ module VexRiscv ( end endcase end - if(_zz_191)begin - case(_zz_193) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -4431,142 +4540,141 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_136,{_zz_135,_zz_134}} != 3'b000) || CsrPlugin_thirdPartyWake); + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); memory_MulDivIterativePlugin_mul_counter_value <= memory_MulDivIterativePlugin_mul_counter_valueNext; memory_MulDivIterativePlugin_div_counter_value <= memory_MulDivIterativePlugin_div_counter_valueNext; - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_149) + case(switch_Fetcher_l362) 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_149 <= 3'b001; + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; end end 3'b001 : begin - _zz_149 <= 3'b010; + switch_Fetcher_l362 <= 3'b010; end 3'b010 : begin - _zz_149 <= 3'b011; + switch_Fetcher_l362 <= 3'b011; end 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_149 <= 3'b100; + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; end end 3'b100 : begin - _zz_149 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; end default : begin end endcase - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_296[0]; - CsrPlugin_mstatus_MIE <= _zz_297[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_299[0]; - CsrPlugin_mie_MTIE <= _zz_300[0]; - CsrPlugin_mie_MSIE <= _zz_301[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_146 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_207)begin - if(iBusWishbone_ACK)begin - _zz_158 <= (_zz_158 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_159 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if(_zz_213)begin - dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; - dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); - end else begin - dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); - dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(dBus_cmd_valid) begin + dBus_cmd_rValid <= 1'b1; + end + if(dBus_cmd_halfPipe_fire) begin + dBus_cmd_rValid <= 1'b0; end end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_64 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_179)begin - if(_zz_208)begin + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l175) begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - _zz_110 <= _zz_37[11 : 7]; - _zz_111 <= _zz_47; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_185)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_138 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_138 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_189)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_140 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_140 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_when_1) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_209)begin - if(_zz_210)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_211)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_212)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_190)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -4574,327 +4682,324 @@ module VexRiscv ( end endcase end - if(_zz_173)begin - if(_zz_188)begin + if(when_MulDivIterativePlugin_l96) begin + if(when_MulDivIterativePlugin_l100) begin memory_MulDivIterativePlugin_rs2 <= (memory_MulDivIterativePlugin_rs2 >>> 1); - memory_MulDivIterativePlugin_accumulator <= ({_zz_275,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); + memory_MulDivIterativePlugin_accumulator <= ({_zz_memory_MulDivIterativePlugin_accumulator,memory_MulDivIterativePlugin_accumulator[31 : 0]} >>> 1); end end - if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_MulDivIterativePlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_MulDivIterativePlugin_div_done <= 1'b0; end - if(_zz_174)begin - if(_zz_204)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_MulDivIterativePlugin_rs1[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outNumerator; memory_MulDivIterativePlugin_accumulator[31 : 0] <= memory_MulDivIterativePlugin_div_stage_0_outRemainder; - if((memory_MulDivIterativePlugin_div_counter_value == 6'h20))begin - memory_MulDivIterativePlugin_div_result <= _zz_287[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_MulDivIterativePlugin_div_result <= _zz_memory_MulDivIterativePlugin_div_result_1[31:0]; end end end - if(_zz_205)begin + if(when_MulDivIterativePlugin_l162) begin memory_MulDivIterativePlugin_accumulator <= 65'h0; - memory_MulDivIterativePlugin_rs1 <= ((_zz_144 ? (~ _zz_145) : _zz_145) + _zz_293); - memory_MulDivIterativePlugin_rs2 <= ((_zz_143 ? (~ execute_RS2) : execute_RS2) + _zz_295); - memory_MulDivIterativePlugin_div_needRevert <= ((_zz_144 ^ (_zz_143 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_MulDivIterativePlugin_rs1 <= ((_zz_memory_MulDivIterativePlugin_rs1_1 ? (~ _zz_memory_MulDivIterativePlugin_rs1_2) : _zz_memory_MulDivIterativePlugin_rs1_2) + _zz_memory_MulDivIterativePlugin_rs1_3); + memory_MulDivIterativePlugin_rs2 <= ((_zz_memory_MulDivIterativePlugin_rs1 ? (~ execute_RS2) : execute_RS2) + _zz_memory_MulDivIterativePlugin_rs2); + memory_MulDivIterativePlugin_div_needRevert <= ((_zz_memory_MulDivIterativePlugin_rs1_1 ^ (_zz_memory_MulDivIterativePlugin_rs1 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_32; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_50; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_7) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_49; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_23; + if(when_Pipeline_l124_9) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_10) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_20; + if(when_Pipeline_l124_14) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_17; + if(when_Pipeline_l124_15) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_16) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_14; + if(when_Pipeline_l124_26) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_11; + if(when_Pipeline_l124_27) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_8; + if(when_Pipeline_l124_28) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_29) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_30) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_31) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_32) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_33) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_34) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_35) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; - execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; - execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; - execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; - execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; - execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; - execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; - execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; - execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; - end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_30; + if(when_Pipeline_l124_49) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_29; + if(when_Pipeline_l124_50) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_52) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_53) begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_298[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; - if(_zz_213)begin - dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; - dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; - dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; - dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + if(dBus_cmd_ready) begin + dBus_cmd_rData_wr <= dBus_cmd_payload_wr; + dBus_cmd_rData_address <= dBus_cmd_payload_address; + dBus_cmd_rData_data <= dBus_cmd_payload_data; + dBus_cmd_rData_size <= dBus_cmd_payload_size; end end - always @ (posedge clk) begin + always @(posedge clk) begin DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin + if(debug_bus_cmd_ready) begin DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_47; + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; end - _zz_148 <= debug_bus_cmd_payload_address[2]; - if(_zz_186)begin + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin + always @(posedge clk) begin if(debugReset) begin DebugPlugin_resetIt <= 1'b0; DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + if(when_DebugPlugin_l225) begin DebugPlugin_godmode <= 1'b1; end - if(debug_bus_cmd_valid)begin - case(_zz_206) + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin + if(when_DebugPlugin_l260) begin DebugPlugin_resetIt <= 1'b1; end - if(debug_bus_cmd_payload_data[24])begin + if(when_DebugPlugin_l260_1) begin DebugPlugin_resetIt <= 1'b0; end - if(debug_bus_cmd_payload_data[17])begin + if(when_DebugPlugin_l261) begin DebugPlugin_haltIt <= 1'b1; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l261_1) begin DebugPlugin_haltIt <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l262) begin DebugPlugin_haltedByBreak <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l263) begin DebugPlugin_godmode <= 1'b0; end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end end end default : begin end endcase end - if(_zz_186)begin - if(_zz_187)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_192)begin - if(decode_arbitration_isValid)begin + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin DebugPlugin_haltIt <= 1'b1; end end @@ -4943,18 +5048,14 @@ module InstructionCache ( input io_mem_rsp_valid, input [31:0] io_mem_rsp_payload_data, input io_mem_rsp_payload_error, - input [2:0] _zz_9, - input [31:0] _zz_10, + input [2:0] _zz_when_Fetcher_l398, + input [31:0] _zz_io_cpu_fetch_data_regNextWhen, input clk, input reset ); - reg [31:0] _zz_11; - reg [22:0] _zz_12; - wire _zz_13; - wire _zz_14; - wire [0:0] _zz_15; - wire [0:0] _zz_16; - wire [22:0] _zz_17; + reg [31:0] _zz_banks_0_port1; + reg [22:0] _zz_ways_0_tags_port1; + wire [22:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -4963,8 +5064,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [6:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -4978,22 +5084,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [8:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_6; - wire _zz_7; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8; + wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -5003,82 +5112,86 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; + wire when_Fetcher_l398; (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_13 = (! lineLoader_flushCounter[6]); - assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_15 = _zz_8[0 : 0]; - assign _zz_16 = _zz_8[1 : 1]; - assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_11 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_12 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_13)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -5094,30 +5207,36 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_12; - assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000); + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -5125,51 +5244,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_14)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_13)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[6]; - if(_zz_14)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 7'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -5180,14 +5299,14 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end - if((_zz_9 != 3'b000))begin - io_cpu_fetch_data_regNextWhen <= _zz_10; + if(when_Fetcher_l398) begin + io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v index ea879f1..02bc40f 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v @@ -1,46 +1,46 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b10 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -73,223 +73,177 @@ module VexRiscv ( input clk, input reset ); - wire _zz_124; - wire _zz_125; - reg [31:0] _zz_126; - reg [31:0] _zz_127; - reg [31:0] _zz_128; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; - wire _zz_129; - wire _zz_130; - wire _zz_131; - wire _zz_132; - wire _zz_133; - wire _zz_134; - wire [1:0] _zz_135; - wire _zz_136; - wire _zz_137; - wire _zz_138; - wire _zz_139; - wire _zz_140; - wire _zz_141; - wire _zz_142; - wire _zz_143; - wire _zz_144; - wire _zz_145; - wire _zz_146; - wire _zz_147; - wire _zz_148; - wire _zz_149; - wire _zz_150; - wire _zz_151; - wire _zz_152; - wire [1:0] _zz_153; - wire _zz_154; - wire [0:0] _zz_155; - wire [0:0] _zz_156; - wire [0:0] _zz_157; - wire [0:0] _zz_158; - wire [0:0] _zz_159; - wire [0:0] _zz_160; - wire [0:0] _zz_161; - wire [0:0] _zz_162; - wire [0:0] _zz_163; - wire [0:0] _zz_164; - wire [0:0] _zz_165; - wire [2:0] _zz_166; - wire [2:0] _zz_167; - wire [31:0] _zz_168; - wire [2:0] _zz_169; - wire [0:0] _zz_170; - wire [2:0] _zz_171; - wire [0:0] _zz_172; - wire [2:0] _zz_173; - wire [0:0] _zz_174; - wire [2:0] _zz_175; - wire [0:0] _zz_176; - wire [2:0] _zz_177; - wire [2:0] _zz_178; - wire [0:0] _zz_179; - wire [2:0] _zz_180; - wire [4:0] _zz_181; - wire [11:0] _zz_182; - wire [11:0] _zz_183; - wire [31:0] _zz_184; - wire [31:0] _zz_185; - wire [31:0] _zz_186; - wire [31:0] _zz_187; - wire [31:0] _zz_188; - wire [31:0] _zz_189; - wire [31:0] _zz_190; - wire [31:0] _zz_191; - wire [32:0] _zz_192; - wire [19:0] _zz_193; - wire [11:0] _zz_194; - wire [11:0] _zz_195; - wire [1:0] _zz_196; - wire [1:0] _zz_197; - wire [1:0] _zz_198; - wire [1:0] _zz_199; - wire [0:0] _zz_200; - wire [0:0] _zz_201; - wire [0:0] _zz_202; - wire [0:0] _zz_203; - wire [0:0] _zz_204; - wire [0:0] _zz_205; - wire _zz_206; - wire _zz_207; - wire [1:0] _zz_208; - wire [31:0] _zz_209; - wire [31:0] _zz_210; - wire [31:0] _zz_211; - wire _zz_212; - wire [0:0] _zz_213; - wire [12:0] _zz_214; - wire [31:0] _zz_215; - wire [31:0] _zz_216; - wire [31:0] _zz_217; - wire _zz_218; - wire [0:0] _zz_219; - wire [6:0] _zz_220; - wire [31:0] _zz_221; - wire [31:0] _zz_222; - wire [31:0] _zz_223; - wire _zz_224; - wire [0:0] _zz_225; - wire [0:0] _zz_226; - wire [31:0] _zz_227; - wire [31:0] _zz_228; - wire [31:0] _zz_229; - wire [0:0] _zz_230; - wire [0:0] _zz_231; - wire [1:0] _zz_232; - wire [1:0] _zz_233; - wire _zz_234; - wire [0:0] _zz_235; - wire [19:0] _zz_236; - wire [31:0] _zz_237; - wire [31:0] _zz_238; - wire [31:0] _zz_239; - wire [31:0] _zz_240; - wire [31:0] _zz_241; - wire [31:0] _zz_242; - wire _zz_243; - wire [1:0] _zz_244; - wire [1:0] _zz_245; - wire _zz_246; - wire [0:0] _zz_247; - wire [16:0] _zz_248; - wire [31:0] _zz_249; - wire [31:0] _zz_250; - wire [31:0] _zz_251; - wire [31:0] _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire [0:0] _zz_256; - wire [0:0] _zz_257; - wire _zz_258; - wire [0:0] _zz_259; - wire [13:0] _zz_260; - wire [31:0] _zz_261; - wire _zz_262; - wire _zz_263; - wire [0:0] _zz_264; - wire [0:0] _zz_265; - wire [2:0] _zz_266; - wire [2:0] _zz_267; - wire _zz_268; - wire [0:0] _zz_269; - wire [10:0] _zz_270; - wire [31:0] _zz_271; - wire [31:0] _zz_272; - wire [31:0] _zz_273; - wire [31:0] _zz_274; - wire _zz_275; - wire _zz_276; - wire [31:0] _zz_277; - wire [31:0] _zz_278; - wire _zz_279; - wire [0:0] _zz_280; - wire [0:0] _zz_281; - wire _zz_282; - wire [0:0] _zz_283; - wire [7:0] _zz_284; - wire [0:0] _zz_285; - wire [3:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; - wire [1:0] _zz_289; - wire [1:0] _zz_290; - wire _zz_291; - wire [0:0] _zz_292; - wire [4:0] _zz_293; - wire [31:0] _zz_294; - wire [31:0] _zz_295; - wire [31:0] _zz_296; - wire [0:0] _zz_297; - wire [0:0] _zz_298; - wire [31:0] _zz_299; - wire [31:0] _zz_300; - wire [31:0] _zz_301; - wire _zz_302; - wire _zz_303; - wire _zz_304; - wire [3:0] _zz_305; - wire [3:0] _zz_306; - wire _zz_307; - wire [0:0] _zz_308; - wire [1:0] _zz_309; - wire [31:0] _zz_310; - wire [31:0] _zz_311; - wire [31:0] _zz_312; - wire [31:0] _zz_313; - wire [31:0] _zz_314; - wire [31:0] _zz_315; - wire [31:0] _zz_316; - wire _zz_317; - wire [0:0] _zz_318; - wire [1:0] _zz_319; - wire _zz_320; - wire [2:0] _zz_321; - wire [2:0] _zz_322; - wire _zz_323; - wire _zz_324; - wire [31:0] _zz_325; - wire [31:0] _zz_326; - wire [31:0] _zz_327; - wire [31:0] _zz_328; - wire [31:0] _zz_329; - wire [31:0] _zz_330; - wire [31:0] _zz_331; - wire _zz_332; - wire _zz_333; - wire _zz_334; - wire _zz_335; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [12:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [6:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload_1; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload_2; + wire [31:0] _zz_IBusSimplePlugin_fetchPc_pc; + wire [2:0] _zz_IBusSimplePlugin_fetchPc_pc_1; + wire [2:0] _zz_IBusSimplePlugin_pending_next; + wire [2:0] _zz_IBusSimplePlugin_pending_next_1; + wire [0:0] _zz_IBusSimplePlugin_pending_next_2; + wire [2:0] _zz_IBusSimplePlugin_pending_next_3; + wire [0:0] _zz_IBusSimplePlugin_pending_next_4; + wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire [0:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1; + wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2; + wire [0:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3; + wire [2:0] _zz_DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] _zz__zz_decode_ENV_CTRL_2; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_1; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_2; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_3; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_4; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_5; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_6; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_7; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_8; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_9; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_10; + wire _zz__zz_decode_ENV_CTRL_2_11; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_12; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_13; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_14; + wire _zz__zz_decode_ENV_CTRL_2_15; + wire [19:0] _zz__zz_decode_ENV_CTRL_2_16; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_17; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_18; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_19; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_20; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_21; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_22; + wire _zz__zz_decode_ENV_CTRL_2_23; + wire _zz__zz_decode_ENV_CTRL_2_24; + wire _zz__zz_decode_ENV_CTRL_2_25; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_26; + wire _zz__zz_decode_ENV_CTRL_2_27; + wire [16:0] _zz__zz_decode_ENV_CTRL_2_28; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_29; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_30; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_31; + wire _zz__zz_decode_ENV_CTRL_2_32; + wire _zz__zz_decode_ENV_CTRL_2_33; + wire _zz__zz_decode_ENV_CTRL_2_34; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_35; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_36; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_37; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_38; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_39; + wire [13:0] _zz__zz_decode_ENV_CTRL_2_40; + wire [2:0] _zz__zz_decode_ENV_CTRL_2_41; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_42; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_43; + wire _zz__zz_decode_ENV_CTRL_2_44; + wire _zz__zz_decode_ENV_CTRL_2_45; + wire [2:0] _zz__zz_decode_ENV_CTRL_2_46; + wire _zz__zz_decode_ENV_CTRL_2_47; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_48; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_49; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_50; + wire _zz__zz_decode_ENV_CTRL_2_51; + wire [10:0] _zz__zz_decode_ENV_CTRL_2_52; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_53; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_54; + wire _zz__zz_decode_ENV_CTRL_2_55; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_56; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_57; + wire [3:0] _zz__zz_decode_ENV_CTRL_2_58; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_59; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_60; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_61; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_62; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_63; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_64; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_65; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_66; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_67; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_68; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_69; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_70; + wire [7:0] _zz__zz_decode_ENV_CTRL_2_71; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_72; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_73; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_74; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_75; + wire _zz__zz_decode_ENV_CTRL_2_76; + wire _zz__zz_decode_ENV_CTRL_2_77; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_78; + wire _zz__zz_decode_ENV_CTRL_2_79; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_80; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_81; + wire _zz__zz_decode_ENV_CTRL_2_82; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_83; + wire [4:0] _zz__zz_decode_ENV_CTRL_2_84; + wire [3:0] _zz__zz_decode_ENV_CTRL_2_85; + wire _zz__zz_decode_ENV_CTRL_2_86; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_87; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_88; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_89; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_90; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_91; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_92; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_93; + wire [3:0] _zz__zz_decode_ENV_CTRL_2_94; + wire _zz__zz_decode_ENV_CTRL_2_95; + wire _zz__zz_decode_ENV_CTRL_2_96; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_97; + wire [2:0] _zz__zz_decode_ENV_CTRL_2_98; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_99; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_100; + wire _zz__zz_decode_ENV_CTRL_2_101; + wire _zz__zz_decode_ENV_CTRL_2_102; + wire [2:0] _zz__zz_decode_ENV_CTRL_2_103; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_104; + wire _zz__zz_decode_ENV_CTRL_2_105; + wire _zz__zz_decode_ENV_CTRL_2_106; + wire _zz__zz_decode_ENV_CTRL_2_107; + wire _zz__zz_decode_ENV_CTRL_2_108; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [31:0] _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1; + wire [32:0] _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -302,63 +256,65 @@ module VexRiscv ( wire decode_SRC2_FORCE_ZERO; wire [31:0] decode_RS2; wire [31:0] decode_RS1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `BranchCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_17; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire decode_MEMORY_ENABLE; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire [31:0] execute_RS1; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_29; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; @@ -367,83 +323,61 @@ module VexRiscv ( wire [31:0] memory_INSTRUCTION; wire memory_BYPASSABLE_MEMORY_STAGE; wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] _zz_30; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_31; + reg [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_32; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_33; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_34; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_35; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_36; - wire [31:0] _zz_37; - wire _zz_38; - reg _zz_39; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_40; - wire `BranchCtrlEnum_defaultEncoding_type _zz_41; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_42; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; - wire `Src2CtrlEnum_defaultEncoding_type _zz_44; - wire `AluCtrlEnum_defaultEncoding_type _zz_45; - wire `Src1CtrlEnum_defaultEncoding_type _zz_46; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; wire writeBack_MEMORY_STORE; - reg [31:0] _zz_47; + reg [31:0] _zz_lastStageRegFileWrite_payload_data; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP2_physicalAddress; - wire memory_MMU_RSP2_isIoAccess; - wire memory_MMU_RSP2_isPaging; - wire memory_MMU_RSP2_allowRead; - wire memory_MMU_RSP2_allowWrite; - wire memory_MMU_RSP2_allowExecute; - wire memory_MMU_RSP2_exception; - wire memory_MMU_RSP2_refilling; - wire memory_MMU_RSP2_bypassTranslation; - wire [31:0] memory_PC; wire memory_ALIGNEMENT_FAULT; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP2_physicalAddress; - wire execute_MMU_RSP2_isIoAccess; - wire execute_MMU_RSP2_isPaging; - wire execute_MMU_RSP2_allowRead; - wire execute_MMU_RSP2_allowWrite; - wire execute_MMU_RSP2_allowExecute; - wire execute_MMU_RSP2_exception; - wire execute_MMU_RSP2_refilling; - wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; wire [31:0] execute_RS2; wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; - wire decode_MEMORY_ENABLE; - reg [31:0] _zz_48; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] decode_INSTRUCTION; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; - reg decode_arbitration_haltItself; + wire decode_arbitration_haltItself; reg decode_arbitration_haltByOther; reg decode_arbitration_removeIt; wire decode_arbitration_flushIt; @@ -468,7 +402,7 @@ module VexRiscv ( reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; + wire memory_arbitration_flushIt; reg memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; @@ -498,49 +432,14 @@ module VexRiscv ( wire IBusSimplePlugin_pcValids_2; wire IBusSimplePlugin_pcValids_3; wire iBus_cmd_valid; - wire iBus_cmd_ready; + reg iBus_cmd_ready; wire [31:0] iBus_cmd_payload_pc; wire iBus_rsp_valid; wire iBus_rsp_payload_error; wire [31:0] iBus_rsp_payload_inst; - wire IBusSimplePlugin_decodeExceptionPort_valid; - reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; - wire IBusSimplePlugin_mmuBus_cmd_0_isValid; - wire IBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire IBusSimplePlugin_mmuBus_rsp_isPaging; - wire IBusSimplePlugin_mmuBus_rsp_allowRead; - wire IBusSimplePlugin_mmuBus_rsp_allowWrite; - wire IBusSimplePlugin_mmuBus_rsp_allowExecute; - wire IBusSimplePlugin_mmuBus_rsp_exception; - wire IBusSimplePlugin_mmuBus_rsp_refilling; - wire IBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire IBusSimplePlugin_mmuBus_end; - wire IBusSimplePlugin_mmuBus_busy; reg DBusSimplePlugin_memoryExceptionPort_valid; reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_0_isValid; - wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_isPaging; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -549,6 +448,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; wire CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -566,28 +470,29 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; + wire CsrPlugin_allowEbreakException; wire IBusSimplePlugin_externalFlush; wire IBusSimplePlugin_jump_pcLoad_valid; wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; - wire [2:0] _zz_49; - wire [2:0] _zz_50; - wire _zz_51; - wire _zz_52; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload; wire IBusSimplePlugin_fetchPc_output_valid; wire IBusSimplePlugin_fetchPc_output_ready; wire [31:0] IBusSimplePlugin_fetchPc_output_payload; reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; reg IBusSimplePlugin_fetchPc_correction; reg IBusSimplePlugin_fetchPc_correctionReg; + wire IBusSimplePlugin_fetchPc_output_fire; wire IBusSimplePlugin_fetchPc_corrected; reg IBusSimplePlugin_fetchPc_pcRegPropagate; reg IBusSimplePlugin_fetchPc_booted; reg IBusSimplePlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusSimplePlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusSimplePlugin_fetchPc_pc; - wire IBusSimplePlugin_fetchPc_redo_valid; - wire [31:0] IBusSimplePlugin_fetchPc_redo_payload; reg IBusSimplePlugin_fetchPc_flushed; - reg IBusSimplePlugin_iBusRsp_redoFetch; + wire when_Fetcher_l158; + wire IBusSimplePlugin_iBusRsp_redoFetch; wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; @@ -602,12 +507,12 @@ module VexRiscv ( wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; wire IBusSimplePlugin_iBusRsp_stages_1_halt; - wire _zz_53; - wire _zz_54; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready; wire IBusSimplePlugin_iBusRsp_flush; - wire _zz_55; - wire _zz_56; - reg _zz_57; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2; reg IBusSimplePlugin_iBusRsp_readyForError; wire IBusSimplePlugin_iBusRsp_output_valid; wire IBusSimplePlugin_iBusRsp_output_ready; @@ -621,18 +526,24 @@ module VexRiscv ( wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; - reg _zz_58; - reg [31:0] _zz_59; - reg _zz_60; - reg [31:0] _zz_61; - reg _zz_62; + reg _zz_IBusSimplePlugin_injector_decodeInput_valid; + reg [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_pc; + reg _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + reg [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + reg _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc; + wire when_Fetcher_l320; reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l329_4; reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; - reg IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_valid; wire IBusSimplePlugin_cmd_ready; wire [31:0] IBusSimplePlugin_cmd_payload_pc; wire IBusSimplePlugin_pending_inc; @@ -640,33 +551,30 @@ module VexRiscv ( reg [2:0] IBusSimplePlugin_pending_value; wire [2:0] IBusSimplePlugin_pending_next; wire IBusSimplePlugin_cmdFork_canEmit; - reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; - reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; - reg IBusSimplePlugin_mmu_joinCtx_isPaging; - reg IBusSimplePlugin_mmu_joinCtx_allowRead; - reg IBusSimplePlugin_mmu_joinCtx_allowWrite; - reg IBusSimplePlugin_mmu_joinCtx_allowExecute; - reg IBusSimplePlugin_mmu_joinCtx_exception; - reg IBusSimplePlugin_mmu_joinCtx_refilling; - reg IBusSimplePlugin_mmu_joinCtx_bypassTranslation; + wire when_IBusSimplePlugin_l304; + wire IBusSimplePlugin_cmd_fire; wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire when_IBusSimplePlugin_l375; wire IBusSimplePlugin_rspJoin_join_valid; wire IBusSimplePlugin_rspJoin_join_ready; wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; wire IBusSimplePlugin_rspJoin_join_payload_isRvc; - reg IBusSimplePlugin_rspJoin_exceptionDetected; - wire _zz_63; + wire IBusSimplePlugin_rspJoin_exceptionDetected; + wire IBusSimplePlugin_rspJoin_join_fire; + wire IBusSimplePlugin_rspJoin_join_fire_1; + wire _zz_IBusSimplePlugin_iBusRsp_output_valid; wire dBus_cmd_valid; wire dBus_cmd_ready; wire dBus_cmd_payload_wr; @@ -676,29 +584,36 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - wire _zz_64; + wire _zz_dBus_cmd_valid; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_65; - reg [3:0] _zz_66; + reg [31:0] _zz_dBus_cmd_payload_data; + wire when_DBusSimplePlugin_l426; + reg [3:0] _zz_execute_DBusSimplePlugin_formalMask; wire [3:0] execute_DBusSimplePlugin_formalMask; + wire when_DBusSimplePlugin_l479; + wire when_DBusSimplePlugin_l486; + wire when_DBusSimplePlugin_l512; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_67; - reg [31:0] _zz_68; - wire _zz_69; - reg [31:0] _zz_70; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusSimplePlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1; + wire _zz_writeBack_DBusSimplePlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3; reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [25:0] _zz_71; - wire _zz_72; - wire _zz_73; - wire _zz_74; - wire _zz_75; - wire `Src1CtrlEnum_defaultEncoding_type _zz_76; - wire `AluCtrlEnum_defaultEncoding_type _zz_77; - wire `Src2CtrlEnum_defaultEncoding_type _zz_78; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_79; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_80; - wire `BranchCtrlEnum_defaultEncoding_type _zz_81; - wire `EnvCtrlEnum_defaultEncoding_type _zz_82; + wire when_DBusSimplePlugin_l558; + wire [25:0] _zz_decode_ENV_CTRL_2; + wire _zz_decode_ENV_CTRL_3; + wire _zz_decode_ENV_CTRL_4; + wire _zz_decode_ENV_CTRL_5; + wire _zz_decode_ENV_CTRL_6; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_7; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -706,15 +621,15 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_83; + reg _zz_2; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_84; - reg [31:0] _zz_85; - wire _zz_86; - reg [19:0] _zz_87; - wire _zz_88; - reg [19:0] _zz_89; - reg [31:0] _zz_90; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; @@ -723,23 +638,47 @@ module VexRiscv ( wire [4:0] execute_LightShifterPlugin_amplitude; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_91; - reg _zz_92; - reg _zz_93; - reg _zz_94; - reg [4:0] _zz_95; + wire when_ShiftPlugins_l169; + reg [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA_1; + wire when_ShiftPlugins_l175; + wire when_ShiftPlugins_l184; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l59; + wire when_HazardSimplePlugin_l62; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l59_1; + wire when_HazardSimplePlugin_l62_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l59_2; + wire when_HazardSimplePlugin_l62_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_96; - reg _zz_97; - reg _zz_98; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_DO; + reg _zz_execute_BRANCH_DO_1; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_99; - reg [10:0] _zz_100; - wire _zz_101; - reg [19:0] _zz_102; - wire _zz_103; - reg [18:0] _zz_104; - reg [31:0] _zz_105; + wire _zz_execute_BranchPlugin_branch_src2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -761,9 +700,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_106; - wire _zz_107; - wire _zz_108; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -776,197 +715,273 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_109; - wire _zz_110; - wire [1:0] _zz_111; - wire _zz_112; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_113; - wire [31:0] _zz_114; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_9; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_14; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_15; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_16; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg decode_to_execute_MEMORY_STORE; + wire when_Pipeline_l124_23; reg execute_to_memory_MEMORY_STORE; + wire when_Pipeline_l124_24; reg memory_to_writeBack_MEMORY_STORE; + wire when_Pipeline_l124_25; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_26; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_27; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_28; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_29; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_30; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_31; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_32; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_33; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_34; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_35; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_36; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_37; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_38; reg execute_to_memory_ALIGNEMENT_FAULT; + wire when_Pipeline_l124_39; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_40; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_MMU_FAULT; - reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; - reg execute_to_memory_MMU_RSP2_isIoAccess; - reg execute_to_memory_MMU_RSP2_isPaging; - reg execute_to_memory_MMU_RSP2_allowRead; - reg execute_to_memory_MMU_RSP2_allowWrite; - reg execute_to_memory_MMU_RSP2_allowExecute; - reg execute_to_memory_MMU_RSP2_exception; - reg execute_to_memory_MMU_RSP2_refilling; - reg execute_to_memory_MMU_RSP2_bypassTranslation; + wire when_Pipeline_l124_41; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_42; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_43; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_44; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_45; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_115; - reg [31:0] _zz_116; - reg [31:0] _zz_117; - reg [31:0] _zz_118; - reg [31:0] _zz_119; - reg [31:0] _zz_120; - reg [31:0] _zz_121; - reg [31:0] _zz_122; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; wire iBus_cmd_m2sPipe_valid; wire iBus_cmd_m2sPipe_ready; wire [31:0] iBus_cmd_m2sPipe_payload_pc; - reg iBus_cmd_m2sPipe_rValid; - reg [31:0] iBus_cmd_m2sPipe_rData_pc; + reg iBus_cmd_rValid; + reg [31:0] iBus_cmd_rData_pc; + wire when_Stream_l342; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; wire dBus_cmd_halfPipe_payload_wr; wire [31:0] dBus_cmd_halfPipe_payload_address; wire [31:0] dBus_cmd_halfPipe_payload_data; wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_123; + reg dBus_cmd_rValid; + wire dBus_cmd_halfPipe_fire; + reg dBus_cmd_rData_wr; + reg [31:0] dBus_cmd_rData_address; + reg [31:0] dBus_cmd_rData_data; + reg [1:0] dBus_cmd_rData_size; + reg [3:0] _zz_dBusWishbone_SEL; + wire when_DBusSimplePlugin_l189; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [31:0] _zz_10_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_11_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_14_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_17_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_20_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_23_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_26_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_29_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_31_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_33_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_34_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_35_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_36_string; - reg [39:0] _zz_40_string; - reg [31:0] _zz_41_string; - reg [71:0] _zz_42_string; - reg [39:0] _zz_43_string; - reg [23:0] _zz_44_string; - reg [63:0] _zz_45_string; - reg [95:0] _zz_46_string; - reg [95:0] _zz_76_string; - reg [63:0] _zz_77_string; - reg [23:0] _zz_78_string; - reg [39:0] _zz_79_string; - reg [71:0] _zz_80_string; - reg [31:0] _zz_81_string; - reg [39:0] _zz_82_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_7_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -980,877 +995,817 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_129 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_130 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_131 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_132 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_133 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_134 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_135 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_136 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_137 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_138 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_139 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_140 = (1'b1 || (! 1'b1)); - assign _zz_141 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_142 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_143 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_144 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_145 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_146 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_147 = (! execute_arbitration_isStuckByOthers); - assign _zz_148 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_149 = ((_zz_106 && 1'b1) && (! 1'b0)); - assign _zz_150 = ((_zz_107 && 1'b1) && (! 1'b0)); - assign _zz_151 = ((_zz_108 && 1'b1) && (! 1'b0)); - assign _zz_152 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_153 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_154 = execute_INSTRUCTION[13]; - assign _zz_155 = _zz_71[23 : 23]; - assign _zz_156 = _zz_71[15 : 15]; - assign _zz_157 = _zz_71[12 : 12]; - assign _zz_158 = _zz_71[11 : 11]; - assign _zz_159 = _zz_71[10 : 10]; - assign _zz_160 = _zz_71[14 : 14]; - assign _zz_161 = _zz_71[4 : 4]; - assign _zz_162 = _zz_71[2 : 2]; - assign _zz_163 = _zz_71[18 : 18]; - assign _zz_164 = _zz_71[9 : 9]; - assign _zz_165 = _zz_71[3 : 3]; - assign _zz_166 = (_zz_49 - 3'b001); - assign _zz_167 = {IBusSimplePlugin_fetchPc_inc,2'b00}; - assign _zz_168 = {29'd0, _zz_167}; - assign _zz_169 = (IBusSimplePlugin_pending_value + _zz_171); - assign _zz_170 = IBusSimplePlugin_pending_inc; - assign _zz_171 = {2'd0, _zz_170}; - assign _zz_172 = IBusSimplePlugin_pending_dec; - assign _zz_173 = {2'd0, _zz_172}; - assign _zz_174 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); - assign _zz_175 = {2'd0, _zz_174}; - assign _zz_176 = IBusSimplePlugin_pending_dec; - assign _zz_177 = {2'd0, _zz_176}; - assign _zz_178 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_179 = execute_SRC_LESS; - assign _zz_180 = 3'b100; - assign _zz_181 = execute_INSTRUCTION[19 : 15]; - assign _zz_182 = execute_INSTRUCTION[31 : 20]; - assign _zz_183 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_184 = ($signed(_zz_185) + $signed(_zz_188)); - assign _zz_185 = ($signed(_zz_186) + $signed(_zz_187)); - assign _zz_186 = execute_SRC1; - assign _zz_187 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_188 = (execute_SRC_USE_SUB_LESS ? _zz_189 : _zz_190); - assign _zz_189 = 32'h00000001; - assign _zz_190 = 32'h0; - assign _zz_191 = (_zz_192 >>> 1); - assign _zz_192 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_193 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_194 = execute_INSTRUCTION[31 : 20]; - assign _zz_195 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_196 = (_zz_109 & (~ _zz_197)); - assign _zz_197 = (_zz_109 - 2'b01); - assign _zz_198 = (_zz_111 & (~ _zz_199)); - assign _zz_199 = (_zz_111 - 2'b01); - assign _zz_200 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_201 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_202 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_203 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_204 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_205 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_206 = 1'b1; - assign _zz_207 = 1'b1; - assign _zz_208 = {_zz_52,_zz_51}; - assign _zz_209 = 32'h0000107f; - assign _zz_210 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_211 = 32'h00002073; - assign _zz_212 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_213 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_214 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_215) == 32'h00000003),{(_zz_216 == _zz_217),{_zz_218,{_zz_219,_zz_220}}}}}}; - assign _zz_215 = 32'h0000505f; - assign _zz_216 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_217 = 32'h00000063; - assign _zz_218 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_219 = ((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033); - assign _zz_220 = {((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013),{((decode_INSTRUCTION & _zz_221) == 32'h00005033),{(_zz_222 == _zz_223),{_zz_224,{_zz_225,_zz_226}}}}}}; - assign _zz_221 = 32'hbe00707f; - assign _zz_222 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_223 = 32'h00000033; - assign _zz_224 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_225 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_226 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); - assign _zz_227 = 32'h10003050; - assign _zz_228 = (decode_INSTRUCTION & 32'h10403050); - assign _zz_229 = 32'h10000050; - assign _zz_230 = ((decode_INSTRUCTION & _zz_237) == 32'h00001050); - assign _zz_231 = ((decode_INSTRUCTION & _zz_238) == 32'h00002050); - assign _zz_232 = {_zz_75,(_zz_239 == _zz_240)}; - assign _zz_233 = 2'b00; - assign _zz_234 = ((_zz_241 == _zz_242) != 1'b0); - assign _zz_235 = (_zz_243 != 1'b0); - assign _zz_236 = {(_zz_244 != _zz_245),{_zz_246,{_zz_247,_zz_248}}}; - assign _zz_237 = 32'h00001050; - assign _zz_238 = 32'h00002050; - assign _zz_239 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_240 = 32'h00000004; - assign _zz_241 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_242 = 32'h00000040; - assign _zz_243 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); - assign _zz_244 = {(_zz_249 == _zz_250),(_zz_251 == _zz_252)}; - assign _zz_245 = 2'b00; - assign _zz_246 = ({_zz_253,_zz_254} != 2'b00); - assign _zz_247 = (_zz_255 != 1'b0); - assign _zz_248 = {(_zz_256 != _zz_257),{_zz_258,{_zz_259,_zz_260}}}; - assign _zz_249 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_250 = 32'h40001010; - assign _zz_251 = (decode_INSTRUCTION & 32'h00007054); - assign _zz_252 = 32'h00001010; - assign _zz_253 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); - assign _zz_254 = ((decode_INSTRUCTION & 32'h00003054) == 32'h00001010); - assign _zz_255 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_256 = ((decode_INSTRUCTION & _zz_261) == 32'h00002000); - assign _zz_257 = 1'b0; - assign _zz_258 = ({_zz_262,_zz_263} != 2'b00); - assign _zz_259 = ({_zz_264,_zz_265} != 2'b00); - assign _zz_260 = {(_zz_266 != _zz_267),{_zz_268,{_zz_269,_zz_270}}}; - assign _zz_261 = 32'h00003000; - assign _zz_262 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_263 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_264 = ((decode_INSTRUCTION & _zz_271) == 32'h00000020); - assign _zz_265 = ((decode_INSTRUCTION & _zz_272) == 32'h00000020); - assign _zz_266 = {(_zz_273 == _zz_274),{_zz_275,_zz_276}}; - assign _zz_267 = 3'b000; - assign _zz_268 = ((_zz_277 == _zz_278) != 1'b0); - assign _zz_269 = (_zz_279 != 1'b0); - assign _zz_270 = {(_zz_280 != _zz_281),{_zz_282,{_zz_283,_zz_284}}}; - assign _zz_271 = 32'h00000034; - assign _zz_272 = 32'h00000064; - assign _zz_273 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_274 = 32'h00000040; - assign _zz_275 = ((decode_INSTRUCTION & 32'h00000038) == 32'h0); - assign _zz_276 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); - assign _zz_277 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_278 = 32'h00000020; - assign _zz_279 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); - assign _zz_280 = _zz_74; - assign _zz_281 = 1'b0; - assign _zz_282 = ({_zz_75,{_zz_285,_zz_286}} != 6'h0); - assign _zz_283 = ({_zz_287,_zz_288} != 2'b00); - assign _zz_284 = {(_zz_289 != _zz_290),{_zz_291,{_zz_292,_zz_293}}}; - assign _zz_285 = ((decode_INSTRUCTION & _zz_294) == 32'h00001010); - assign _zz_286 = {(_zz_295 == _zz_296),{_zz_74,{_zz_297,_zz_298}}}; - assign _zz_287 = _zz_73; - assign _zz_288 = ((decode_INSTRUCTION & _zz_299) == 32'h00000020); - assign _zz_289 = {_zz_73,(_zz_300 == _zz_301)}; - assign _zz_290 = 2'b00; - assign _zz_291 = ({_zz_302,_zz_303} != 2'b00); - assign _zz_292 = (_zz_304 != 1'b0); - assign _zz_293 = {(_zz_305 != _zz_306),{_zz_307,{_zz_308,_zz_309}}}; - assign _zz_294 = 32'h00001010; - assign _zz_295 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_296 = 32'h00002010; - assign _zz_297 = (_zz_310 == _zz_311); - assign _zz_298 = (_zz_312 == _zz_313); - assign _zz_299 = 32'h00000070; - assign _zz_300 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_301 = 32'h0; - assign _zz_302 = ((decode_INSTRUCTION & _zz_314) == 32'h00006010); - assign _zz_303 = ((decode_INSTRUCTION & _zz_315) == 32'h00004010); - assign _zz_304 = ((decode_INSTRUCTION & _zz_316) == 32'h00002010); - assign _zz_305 = {_zz_317,{_zz_318,_zz_319}}; - assign _zz_306 = 4'b0000; - assign _zz_307 = (_zz_320 != 1'b0); - assign _zz_308 = (_zz_321 != _zz_322); - assign _zz_309 = {_zz_323,_zz_324}; - assign _zz_310 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_311 = 32'h00000004; - assign _zz_312 = (decode_INSTRUCTION & 32'h00000028); - assign _zz_313 = 32'h0; - assign _zz_314 = 32'h00006014; - assign _zz_315 = 32'h00005014; - assign _zz_316 = 32'h00006014; - assign _zz_317 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_318 = ((decode_INSTRUCTION & _zz_325) == 32'h0); - assign _zz_319 = {(_zz_326 == _zz_327),(_zz_328 == _zz_329)}; - assign _zz_320 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_321 = {(_zz_330 == _zz_331),{_zz_332,_zz_333}}; - assign _zz_322 = 3'b000; - assign _zz_323 = ({_zz_334,_zz_72} != 2'b00); - assign _zz_324 = ({_zz_335,_zz_72} != 2'b00); - assign _zz_325 = 32'h00000018; - assign _zz_326 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_327 = 32'h00002000; - assign _zz_328 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_329 = 32'h00001000; - assign _zz_330 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_331 = 32'h00000040; - assign _zz_332 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_333 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz_334 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_335 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - always @ (posedge clk) begin - if(_zz_206) begin - _zz_126 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_207) begin - _zz_127 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_39) begin + assign _zz_when = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_IBusSimplePlugin_jump_pcLoad_payload_1 = (_zz_IBusSimplePlugin_jump_pcLoad_payload & (~ _zz_IBusSimplePlugin_jump_pcLoad_payload_2)); + assign _zz_IBusSimplePlugin_jump_pcLoad_payload_2 = (_zz_IBusSimplePlugin_jump_pcLoad_payload - 2'b01); + assign _zz_IBusSimplePlugin_fetchPc_pc_1 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_IBusSimplePlugin_fetchPc_pc = {29'd0, _zz_IBusSimplePlugin_fetchPc_pc_1}; + assign _zz_IBusSimplePlugin_pending_next = (IBusSimplePlugin_pending_value + _zz_IBusSimplePlugin_pending_next_1); + assign _zz_IBusSimplePlugin_pending_next_2 = IBusSimplePlugin_pending_inc; + assign _zz_IBusSimplePlugin_pending_next_1 = {2'd0, _zz_IBusSimplePlugin_pending_next_2}; + assign _zz_IBusSimplePlugin_pending_next_4 = IBusSimplePlugin_pending_dec; + assign _zz_IBusSimplePlugin_pending_next_3 = {2'd0, _zz_IBusSimplePlugin_pending_next_4}; + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1}; + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3 = IBusSimplePlugin_pending_dec; + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2 = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3}; + assign _zz_DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1 = (_zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1 >>> 1); + assign _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005033),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbe00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00000033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073); + assign _zz__zz_decode_ENV_CTRL_2 = 32'h10003050; + assign _zz__zz_decode_ENV_CTRL_2_1 = (decode_INSTRUCTION & 32'h10403050); + assign _zz__zz_decode_ENV_CTRL_2_2 = 32'h10000050; + assign _zz__zz_decode_ENV_CTRL_2_3 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_4) == 32'h00001050); + assign _zz__zz_decode_ENV_CTRL_2_5 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_6) == 32'h00002050); + assign _zz__zz_decode_ENV_CTRL_2_7 = {_zz_decode_ENV_CTRL_6,(_zz__zz_decode_ENV_CTRL_2_8 == _zz__zz_decode_ENV_CTRL_2_9)}; + assign _zz__zz_decode_ENV_CTRL_2_10 = 2'b00; + assign _zz__zz_decode_ENV_CTRL_2_11 = ((_zz__zz_decode_ENV_CTRL_2_12 == _zz__zz_decode_ENV_CTRL_2_13) != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_14 = (_zz__zz_decode_ENV_CTRL_2_15 != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_16 = {(_zz__zz_decode_ENV_CTRL_2_17 != _zz__zz_decode_ENV_CTRL_2_22),{_zz__zz_decode_ENV_CTRL_2_23,{_zz__zz_decode_ENV_CTRL_2_26,_zz__zz_decode_ENV_CTRL_2_28}}}; + assign _zz__zz_decode_ENV_CTRL_2_4 = 32'h00001050; + assign _zz__zz_decode_ENV_CTRL_2_6 = 32'h00002050; + assign _zz__zz_decode_ENV_CTRL_2_8 = (decode_INSTRUCTION & 32'h0000001c); + assign _zz__zz_decode_ENV_CTRL_2_9 = 32'h00000004; + assign _zz__zz_decode_ENV_CTRL_2_12 = (decode_INSTRUCTION & 32'h00000058); + assign _zz__zz_decode_ENV_CTRL_2_13 = 32'h00000040; + assign _zz__zz_decode_ENV_CTRL_2_15 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00005010); + assign _zz__zz_decode_ENV_CTRL_2_17 = {(_zz__zz_decode_ENV_CTRL_2_18 == _zz__zz_decode_ENV_CTRL_2_19),(_zz__zz_decode_ENV_CTRL_2_20 == _zz__zz_decode_ENV_CTRL_2_21)}; + assign _zz__zz_decode_ENV_CTRL_2_22 = 2'b00; + assign _zz__zz_decode_ENV_CTRL_2_23 = ({_zz__zz_decode_ENV_CTRL_2_24,_zz__zz_decode_ENV_CTRL_2_25} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_26 = (_zz__zz_decode_ENV_CTRL_2_27 != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_28 = {(_zz__zz_decode_ENV_CTRL_2_29 != _zz__zz_decode_ENV_CTRL_2_31),{_zz__zz_decode_ENV_CTRL_2_32,{_zz__zz_decode_ENV_CTRL_2_35,_zz__zz_decode_ENV_CTRL_2_40}}}; + assign _zz__zz_decode_ENV_CTRL_2_18 = (decode_INSTRUCTION & 32'h40003054); + assign _zz__zz_decode_ENV_CTRL_2_19 = 32'h40001010; + assign _zz__zz_decode_ENV_CTRL_2_20 = (decode_INSTRUCTION & 32'h00007054); + assign _zz__zz_decode_ENV_CTRL_2_21 = 32'h00001010; + assign _zz__zz_decode_ENV_CTRL_2_24 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_ENV_CTRL_2_25 = ((decode_INSTRUCTION & 32'h00003054) == 32'h00001010); + assign _zz__zz_decode_ENV_CTRL_2_27 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); + assign _zz__zz_decode_ENV_CTRL_2_29 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_30) == 32'h00002000); + assign _zz__zz_decode_ENV_CTRL_2_31 = 1'b0; + assign _zz__zz_decode_ENV_CTRL_2_32 = ({_zz__zz_decode_ENV_CTRL_2_33,_zz__zz_decode_ENV_CTRL_2_34} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_35 = ({_zz__zz_decode_ENV_CTRL_2_36,_zz__zz_decode_ENV_CTRL_2_38} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_40 = {(_zz__zz_decode_ENV_CTRL_2_41 != _zz__zz_decode_ENV_CTRL_2_46),{_zz__zz_decode_ENV_CTRL_2_47,{_zz__zz_decode_ENV_CTRL_2_50,_zz__zz_decode_ENV_CTRL_2_52}}}; + assign _zz__zz_decode_ENV_CTRL_2_30 = 32'h00003000; + assign _zz__zz_decode_ENV_CTRL_2_33 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); + assign _zz__zz_decode_ENV_CTRL_2_34 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); + assign _zz__zz_decode_ENV_CTRL_2_36 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_37) == 32'h00000020); + assign _zz__zz_decode_ENV_CTRL_2_38 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_39) == 32'h00000020); + assign _zz__zz_decode_ENV_CTRL_2_41 = {(_zz__zz_decode_ENV_CTRL_2_42 == _zz__zz_decode_ENV_CTRL_2_43),{_zz__zz_decode_ENV_CTRL_2_44,_zz__zz_decode_ENV_CTRL_2_45}}; + assign _zz__zz_decode_ENV_CTRL_2_46 = 3'b000; + assign _zz__zz_decode_ENV_CTRL_2_47 = ((_zz__zz_decode_ENV_CTRL_2_48 == _zz__zz_decode_ENV_CTRL_2_49) != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_50 = (_zz__zz_decode_ENV_CTRL_2_51 != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_52 = {(_zz__zz_decode_ENV_CTRL_2_53 != _zz__zz_decode_ENV_CTRL_2_54),{_zz__zz_decode_ENV_CTRL_2_55,{_zz__zz_decode_ENV_CTRL_2_67,_zz__zz_decode_ENV_CTRL_2_71}}}; + assign _zz__zz_decode_ENV_CTRL_2_37 = 32'h00000034; + assign _zz__zz_decode_ENV_CTRL_2_39 = 32'h00000064; + assign _zz__zz_decode_ENV_CTRL_2_42 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_ENV_CTRL_2_43 = 32'h00000040; + assign _zz__zz_decode_ENV_CTRL_2_44 = ((decode_INSTRUCTION & 32'h00000038) == 32'h0); + assign _zz__zz_decode_ENV_CTRL_2_45 = ((decode_INSTRUCTION & 32'h00403040) == 32'h00000040); + assign _zz__zz_decode_ENV_CTRL_2_48 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_ENV_CTRL_2_49 = 32'h00000020; + assign _zz__zz_decode_ENV_CTRL_2_51 = ((decode_INSTRUCTION & 32'h00000010) == 32'h00000010); + assign _zz__zz_decode_ENV_CTRL_2_53 = _zz_decode_ENV_CTRL_5; + assign _zz__zz_decode_ENV_CTRL_2_54 = 1'b0; + assign _zz__zz_decode_ENV_CTRL_2_55 = ({_zz_decode_ENV_CTRL_6,{_zz__zz_decode_ENV_CTRL_2_56,_zz__zz_decode_ENV_CTRL_2_58}} != 6'h0); + assign _zz__zz_decode_ENV_CTRL_2_67 = ({_zz__zz_decode_ENV_CTRL_2_68,_zz__zz_decode_ENV_CTRL_2_69} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_71 = {(_zz__zz_decode_ENV_CTRL_2_72 != _zz__zz_decode_ENV_CTRL_2_75),{_zz__zz_decode_ENV_CTRL_2_76,{_zz__zz_decode_ENV_CTRL_2_81,_zz__zz_decode_ENV_CTRL_2_84}}}; + assign _zz__zz_decode_ENV_CTRL_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_57) == 32'h00001010); + assign _zz__zz_decode_ENV_CTRL_2_58 = {(_zz__zz_decode_ENV_CTRL_2_59 == _zz__zz_decode_ENV_CTRL_2_60),{_zz_decode_ENV_CTRL_5,{_zz__zz_decode_ENV_CTRL_2_61,_zz__zz_decode_ENV_CTRL_2_64}}}; + assign _zz__zz_decode_ENV_CTRL_2_68 = _zz_decode_ENV_CTRL_4; + assign _zz__zz_decode_ENV_CTRL_2_69 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_70) == 32'h00000020); + assign _zz__zz_decode_ENV_CTRL_2_72 = {_zz_decode_ENV_CTRL_4,(_zz__zz_decode_ENV_CTRL_2_73 == _zz__zz_decode_ENV_CTRL_2_74)}; + assign _zz__zz_decode_ENV_CTRL_2_75 = 2'b00; + assign _zz__zz_decode_ENV_CTRL_2_76 = ({_zz__zz_decode_ENV_CTRL_2_77,_zz__zz_decode_ENV_CTRL_2_79} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_81 = (_zz__zz_decode_ENV_CTRL_2_82 != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_84 = {(_zz__zz_decode_ENV_CTRL_2_85 != _zz__zz_decode_ENV_CTRL_2_94),{_zz__zz_decode_ENV_CTRL_2_95,{_zz__zz_decode_ENV_CTRL_2_97,_zz__zz_decode_ENV_CTRL_2_104}}}; + assign _zz__zz_decode_ENV_CTRL_2_57 = 32'h00001010; + assign _zz__zz_decode_ENV_CTRL_2_59 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_ENV_CTRL_2_60 = 32'h00002010; + assign _zz__zz_decode_ENV_CTRL_2_61 = (_zz__zz_decode_ENV_CTRL_2_62 == _zz__zz_decode_ENV_CTRL_2_63); + assign _zz__zz_decode_ENV_CTRL_2_64 = (_zz__zz_decode_ENV_CTRL_2_65 == _zz__zz_decode_ENV_CTRL_2_66); + assign _zz__zz_decode_ENV_CTRL_2_70 = 32'h00000070; + assign _zz__zz_decode_ENV_CTRL_2_73 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_ENV_CTRL_2_74 = 32'h0; + assign _zz__zz_decode_ENV_CTRL_2_77 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_78) == 32'h00006010); + assign _zz__zz_decode_ENV_CTRL_2_79 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_80) == 32'h00004010); + assign _zz__zz_decode_ENV_CTRL_2_82 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_83) == 32'h00002010); + assign _zz__zz_decode_ENV_CTRL_2_85 = {_zz__zz_decode_ENV_CTRL_2_86,{_zz__zz_decode_ENV_CTRL_2_87,_zz__zz_decode_ENV_CTRL_2_89}}; + assign _zz__zz_decode_ENV_CTRL_2_94 = 4'b0000; + assign _zz__zz_decode_ENV_CTRL_2_95 = (_zz__zz_decode_ENV_CTRL_2_96 != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_97 = (_zz__zz_decode_ENV_CTRL_2_98 != _zz__zz_decode_ENV_CTRL_2_103); + assign _zz__zz_decode_ENV_CTRL_2_104 = {_zz__zz_decode_ENV_CTRL_2_105,_zz__zz_decode_ENV_CTRL_2_107}; + assign _zz__zz_decode_ENV_CTRL_2_62 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz__zz_decode_ENV_CTRL_2_63 = 32'h00000004; + assign _zz__zz_decode_ENV_CTRL_2_65 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_ENV_CTRL_2_66 = 32'h0; + assign _zz__zz_decode_ENV_CTRL_2_78 = 32'h00006014; + assign _zz__zz_decode_ENV_CTRL_2_80 = 32'h00005014; + assign _zz__zz_decode_ENV_CTRL_2_83 = 32'h00006014; + assign _zz__zz_decode_ENV_CTRL_2_86 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz__zz_decode_ENV_CTRL_2_87 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_88) == 32'h0); + assign _zz__zz_decode_ENV_CTRL_2_89 = {(_zz__zz_decode_ENV_CTRL_2_90 == _zz__zz_decode_ENV_CTRL_2_91),(_zz__zz_decode_ENV_CTRL_2_92 == _zz__zz_decode_ENV_CTRL_2_93)}; + assign _zz__zz_decode_ENV_CTRL_2_96 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz__zz_decode_ENV_CTRL_2_98 = {(_zz__zz_decode_ENV_CTRL_2_99 == _zz__zz_decode_ENV_CTRL_2_100),{_zz__zz_decode_ENV_CTRL_2_101,_zz__zz_decode_ENV_CTRL_2_102}}; + assign _zz__zz_decode_ENV_CTRL_2_103 = 3'b000; + assign _zz__zz_decode_ENV_CTRL_2_105 = ({_zz__zz_decode_ENV_CTRL_2_106,_zz_decode_ENV_CTRL_3} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_107 = ({_zz__zz_decode_ENV_CTRL_2_108,_zz_decode_ENV_CTRL_3} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_88 = 32'h00000018; + assign _zz__zz_decode_ENV_CTRL_2_90 = (decode_INSTRUCTION & 32'h00006004); + assign _zz__zz_decode_ENV_CTRL_2_91 = 32'h00002000; + assign _zz__zz_decode_ENV_CTRL_2_92 = (decode_INSTRUCTION & 32'h00005004); + assign _zz__zz_decode_ENV_CTRL_2_93 = 32'h00001000; + assign _zz__zz_decode_ENV_CTRL_2_99 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_ENV_CTRL_2_100 = 32'h00000040; + assign _zz__zz_decode_ENV_CTRL_2_101 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_ENV_CTRL_2_102 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz__zz_decode_ENV_CTRL_2_106 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz__zz_decode_ENV_CTRL_2_108 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( - .io_push_valid (iBus_rsp_valid ), //i - .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o - .io_push_payload_error (iBus_rsp_payload_error ), //i - .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i - .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o - .io_pop_ready (_zz_124 ), //i - .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o - .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o - .io_flush (_zz_125 ), //i - .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o - .clk (clk ), //i - .reset (reset ) //i + .io_push_valid (iBus_rsp_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_payload_error ), //i + .io_push_payload_inst (iBus_rsp_payload_inst ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst ), //o + .io_flush (1'b0 ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .clk (clk ), //i + .reset (reset ) //i ); - always @(*) begin - case(_zz_208) - 2'b00 : begin - _zz_128 = CsrPlugin_jumpInterface_payload; - end - 2'b01 : begin - _zz_128 = DBusSimplePlugin_redoBranch_payload; - end - default : begin - _zz_128 = BranchPlugin_jumpInterface_payload; - end - endcase - end - `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_10) - `BranchCtrlEnum_defaultEncoding_INC : _zz_10_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_10_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_10_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_10_string = "JALR"; - default : _zz_10_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_14) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; - default : _zz_14_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_17) - `Src2CtrlEnum_defaultEncoding_RS : _zz_17_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_17_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_17_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_17_string = "PC "; - default : _zz_17_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_20) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; - default : _zz_20_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_23) - `Src1CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_23_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_23_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_23_string = "URS1 "; - default : _zz_23_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_26) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26_string = "ECALL"; - default : _zz_26_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_29) - `BranchCtrlEnum_defaultEncoding_INC : _zz_29_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_29_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_29_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_29_string = "JALR"; - default : _zz_29_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_31) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_31_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_31_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_31_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_31_string = "SRA_1 "; - default : _zz_31_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_33) - `Src2CtrlEnum_defaultEncoding_RS : _zz_33_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_33_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_33_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_33_string = "PC "; - default : _zz_33_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_34) - `Src1CtrlEnum_defaultEncoding_RS : _zz_34_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_34_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34_string = "URS1 "; - default : _zz_34_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_35) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_35_string = "BITWISE "; - default : _zz_35_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_36) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_36_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_36_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_36_string = "AND_1"; - default : _zz_36_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_40) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_40_string = "ECALL"; - default : _zz_40_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_41) - `BranchCtrlEnum_defaultEncoding_INC : _zz_41_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_41_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_41_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_41_string = "JALR"; - default : _zz_41_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_42) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_42_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_42_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_42_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_42_string = "SRA_1 "; - default : _zz_42_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_43) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; - default : _zz_43_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `Src2CtrlEnum_defaultEncoding_RS : _zz_44_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_44_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_44_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_44_string = "PC "; - default : _zz_44_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_45) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; - default : _zz_45_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_46) - `Src1CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_46_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_46_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_46_string = "URS1 "; - default : _zz_46_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin - case(_zz_76) - `Src1CtrlEnum_defaultEncoding_RS : _zz_76_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_76_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_76_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_76_string = "URS1 "; - default : _zz_76_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_77) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_77_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_77_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_77_string = "BITWISE "; - default : _zz_77_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_78) - `Src2CtrlEnum_defaultEncoding_RS : _zz_78_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_78_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_78_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_78_string = "PC "; - default : _zz_78_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_79) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_79_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_79_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_79_string = "AND_1"; - default : _zz_79_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_80) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_80_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_80_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_80_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_80_string = "SRA_1 "; - default : _zz_80_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_81) - `BranchCtrlEnum_defaultEncoding_INC : _zz_81_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_81_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_81_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_81_string = "JALR"; - default : _zz_81_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_82) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_82_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_82_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_82_string = "ECALL"; - default : _zz_82_string = "?????"; + case(_zz_decode_ENV_CTRL_7) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_7_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_7_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_7_string = "ECALL"; + default : _zz_decode_ENV_CTRL_7_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end @@ -1858,9 +1813,9 @@ module VexRiscv ( assign memory_MEMORY_READ_DATA = dBus_rsp_data; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_98; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_84; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); @@ -1868,144 +1823,121 @@ module VexRiscv ( assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_155[0]; - assign decode_BRANCH_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_SHIFT_CTRL = _zz_11; - assign _zz_12 = _zz_13; - assign decode_ALU_BITWISE_CTRL = _zz_14; - assign _zz_15 = _zz_16; - assign decode_SRC_LESS_UNSIGNED = _zz_156[0]; - assign decode_MEMORY_STORE = _zz_157[0]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_ENV_CTRL_2[23]; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_ENV_CTRL_2[15]; + assign decode_MEMORY_STORE = _zz_decode_ENV_CTRL_2[12]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_158[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_159[0]; - assign decode_SRC2_CTRL = _zz_17; - assign _zz_18 = _zz_19; - assign decode_ALU_CTRL = _zz_20; - assign _zz_21 = _zz_22; - assign decode_SRC1_CTRL = _zz_23; - assign _zz_24 = _zz_25; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_ENV_CTRL_2[11]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_ENV_CTRL_2[10]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_ENABLE = _zz_decode_ENV_CTRL_2[3]; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_26; - assign execute_ENV_CTRL = _zz_27; - assign writeBack_ENV_CTRL = _zz_28; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_29; - assign decode_RS2_USE = _zz_160[0]; - assign decode_RS1_USE = _zz_161[0]; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_ENV_CTRL_2[14]; + assign decode_RS1_USE = _zz_decode_ENV_CTRL_2[4]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_30 = execute_REGFILE_WRITE_DATA; - if(_zz_129)begin - _zz_30 = _zz_91; + always @(*) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = execute_REGFILE_WRITE_DATA; + if(when_ShiftPlugins_l169) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = _zz_execute_to_memory_REGFILE_WRITE_DATA_1; end - if(_zz_130)begin - _zz_30 = execute_CsrPlugin_readData; + if(when_CsrPlugin_l1176) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = CsrPlugin_csrMapping_readDataSignal; end end - assign execute_SHIFT_CTRL = _zz_31; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_32 = execute_PC; - assign execute_SRC2_CTRL = _zz_33; - assign execute_SRC1_CTRL = _zz_34; - assign decode_SRC_USE_SUB_LESS = _zz_162[0]; - assign decode_SRC_ADD_ZERO = _zz_163[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_ENV_CTRL_2[2]; + assign decode_SRC_ADD_ZERO = _zz_decode_ENV_CTRL_2[18]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_35; - assign execute_SRC2 = _zz_90; - assign execute_SRC1 = _zz_85; - assign execute_ALU_BITWISE_CTRL = _zz_36; - assign _zz_37 = writeBack_INSTRUCTION; - assign _zz_38 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_39 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_39 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_164[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_ENV_CTRL_2[9]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_209) == 32'h00001073),{(_zz_210 == _zz_211),{_zz_212,{_zz_213,_zz_214}}}}}}} != 20'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; - always @ (*) begin - _zz_47 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_47 = writeBack_DBusSimplePlugin_rspFormated; + always @(*) begin + _zz_lastStageRegFileWrite_payload_data = writeBack_REGFILE_WRITE_DATA; + if(when_DBusSimplePlugin_l558) begin + _zz_lastStageRegFileWrite_payload_data = writeBack_DBusSimplePlugin_rspFormated; end end assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; - assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; - assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; - assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; - assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; - assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; - assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; - assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; - assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; - assign memory_PC = execute_to_memory_PC; assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); - assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; - assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; - assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; - assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_165[0]; - always @ (*) begin - _zz_48 = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_48 = DBusSimplePlugin_redoBranch_payload; - end - if(BranchPlugin_jumpInterface_valid)begin - _zz_48 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end @@ -2013,134 +1945,119 @@ module VexRiscv ( assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin - decode_arbitration_haltItself = 1'b0; - if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin - decode_arbitration_haltItself = 1'b1; - end - end - - always @ (*) begin + assign decode_arbitration_haltItself = 1'b0; + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_92 || _zz_93)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_131)begin + if(decodeExceptionPort_valid) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(_zz_131)begin + if(decodeExceptionPort_valid) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)))begin + if(when_DBusSimplePlugin_l426) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_129)begin - if((! execute_LightShifterPlugin_done))begin + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l184) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_130)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end assign execute_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + if(when_DBusSimplePlugin_l479) begin memory_arbitration_haltItself = 1'b1; end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_132)begin + if(_zz_when) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end - always @ (*) begin - memory_arbitration_flushIt = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(BranchPlugin_jumpInterface_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(_zz_132)begin + if(_zz_when) begin memory_arbitration_flushNext = 1'b1; end end assign writeBack_arbitration_haltItself = 1'b0; assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end assign writeBack_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_133)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_134)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2149,48 +2066,50 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusSimplePlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_133)begin + if(when_CsrPlugin_l1019) begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_134)begin + if(when_CsrPlugin_l1064) begin IBusSimplePlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusSimplePlugin_incomingInstruction = 1'b0; - if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin + if(IBusSimplePlugin_iBusRsp_stages_1_input_valid) begin IBusSimplePlugin_incomingInstruction = 1'b1; end - if(IBusSimplePlugin_injector_decodeInput_valid)begin + if(IBusSimplePlugin_injector_decodeInput_valid) begin IBusSimplePlugin_incomingInstruction = 1'b1; end end + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; assign CsrPlugin_inWfi = 1'b0; assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_133)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_134)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_133)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_134)begin - case(_zz_135) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2203,113 +2122,97 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); - assign _zz_49 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_50 = (_zz_49 & (~ _zz_166)); - assign _zz_51 = _zz_50[1]; - assign _zz_52 = _zz_50[2]; - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_128; - always @ (*) begin + assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid} != 2'b00); + assign _zz_IBusSimplePlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}; + assign IBusSimplePlugin_jump_pcLoad_payload = (_zz_IBusSimplePlugin_jump_pcLoad_payload_1[0] ? CsrPlugin_jumpInterface_payload : BranchPlugin_jumpInterface_payload); + always @(*) begin IBusSimplePlugin_fetchPc_correction = 1'b0; - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_correction = 1'b1; - end - if(IBusSimplePlugin_jump_pcLoad_valid)begin + if(IBusSimplePlugin_jump_pcLoad_valid) begin IBusSimplePlugin_fetchPc_correction = 1'b1; end end + assign IBusSimplePlugin_fetchPc_output_fire = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready); assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin + if(IBusSimplePlugin_iBusRsp_stages_1_input_ready) begin IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_168); - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; - end - if(IBusSimplePlugin_jump_pcLoad_valid)begin + assign when_Fetcher_l131 = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate); + assign IBusSimplePlugin_fetchPc_output_fire_1 = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready); + always @(*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_IBusSimplePlugin_fetchPc_pc); + if(IBusSimplePlugin_jump_pcLoad_valid) begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; end IBusSimplePlugin_fetchPc_pc[0] = 1'b0; IBusSimplePlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusSimplePlugin_fetchPc_flushed = 1'b0; - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_flushed = 1'b1; - end - if(IBusSimplePlugin_jump_pcLoad_valid)begin + if(IBusSimplePlugin_jump_pcLoad_valid) begin IBusSimplePlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)); assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; - always @ (*) begin - IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin - IBusSimplePlugin_iBusRsp_redoFetch = 1'b1; - end - end - + assign IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin + if(when_IBusSimplePlugin_l304) begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; end - if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin - if(IBusSimplePlugin_mmuBus_rsp_refilling)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; - end - if(IBusSimplePlugin_mmuBus_rsp_exception)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - end - end end - assign _zz_53 = (! IBusSimplePlugin_iBusRsp_stages_0_halt); - assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_53); - assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_53); + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; - assign _zz_54 = (! IBusSimplePlugin_iBusRsp_stages_1_halt); - assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_54); - assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_54); + assign _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; - assign IBusSimplePlugin_fetchPc_redo_valid = IBusSimplePlugin_iBusRsp_redoFetch; - assign IBusSimplePlugin_fetchPc_redo_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); - assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_55; - assign _zz_55 = ((1'b0 && (! _zz_56)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); - assign _zz_56 = _zz_57; - assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_56; + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1; assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; - always @ (*) begin + always @(*) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b1; - if(IBusSimplePlugin_injector_decodeInput_valid)begin + if(IBusSimplePlugin_injector_decodeInput_valid) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b0; end - if((! IBusSimplePlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b0; end end assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); - assign IBusSimplePlugin_injector_decodeInput_valid = _zz_58; - assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_59; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_60; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_61; - assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_62; + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_IBusSimplePlugin_injector_decodeInput_valid; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_IBusSimplePlugin_injector_decodeInput_payload_pc; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc; + assign when_Fetcher_l320 = (! IBusSimplePlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusSimplePlugin_injector_decodeInput_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; @@ -2319,169 +2222,118 @@ module VexRiscv ( assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pending_next = (_zz_169 - _zz_173); + assign IBusSimplePlugin_pending_next = (_zz_IBusSimplePlugin_pending_next - _zz_IBusSimplePlugin_pending_next_3); assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); - always @ (*) begin - IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); - if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin - if(IBusSimplePlugin_mmuBus_rsp_refilling)begin - IBusSimplePlugin_cmd_valid = 1'b0; - end - if(IBusSimplePlugin_mmuBus_rsp_exception)begin - IBusSimplePlugin_cmd_valid = 1'b0; - end - end - end - - assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); - assign IBusSimplePlugin_mmuBus_cmd_0_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; - assign IBusSimplePlugin_mmuBus_cmd_0_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; - assign IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_externalFlush); - assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],2'b00}; + assign when_IBusSimplePlugin_l304 = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))); + assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); + assign IBusSimplePlugin_cmd_fire = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_pending_inc = IBusSimplePlugin_cmd_fire; + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_0_input_payload[31 : 2],2'b00}; assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - assign _zz_124 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); - assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_124); + assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready); + assign IBusSimplePlugin_pending_dec = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; - always @ (*) begin + always @(*) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; - if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin + if(when_IBusSimplePlugin_l375) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; end end assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; - always @ (*) begin - IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_136)begin - IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; - end - end - + assign when_IBusSimplePlugin_l375 = (! IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; - assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); - assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); - assign _zz_63 = (! IBusSimplePlugin_rspJoin_exceptionDetected); - assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_63); - assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_63); + assign IBusSimplePlugin_rspJoin_join_fire = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? IBusSimplePlugin_rspJoin_join_fire : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_join_fire_1 = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = IBusSimplePlugin_rspJoin_join_fire_1; + assign _zz_IBusSimplePlugin_iBusRsp_output_valid = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_IBusSimplePlugin_iBusRsp_output_valid); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_IBusSimplePlugin_iBusRsp_output_valid); assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; - always @ (*) begin - IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_136)begin - IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; - end - end - - assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],2'b00}; - assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError); - assign _zz_64 = 1'b0; - always @ (*) begin + assign _zz_dBus_cmd_valid = 1'b0; + always @(*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; - if(execute_ALIGNEMENT_FAULT)begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin + if(execute_ALIGNEMENT_FAULT) begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_65 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_dBus_cmd_payload_data = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_65 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_dBus_cmd_payload_data = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_65 = execute_RS2[31 : 0]; + _zz_dBus_cmd_payload_data = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_65; - always @ (*) begin + assign dBus_cmd_payload_data = _zz_dBus_cmd_payload_data; + assign when_DBusSimplePlugin_l426 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_66 = 4'b0001; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0001; end 2'b01 : begin - _zz_66 = 4'b0011; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0011; end default : begin - _zz_66 = 4'b1111; + _zz_execute_DBusSimplePlugin_formalMask = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_66 <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; - assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - always @ (*) begin + assign execute_DBusSimplePlugin_formalMask = (_zz_execute_DBusSimplePlugin_formalMask <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign when_DBusSimplePlugin_l479 = (((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)); + always @(*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_137)begin + if(when_DBusSimplePlugin_l486) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_ALIGNEMENT_FAULT)begin + if(memory_ALIGNEMENT_FAULT) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end else begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - end - if(_zz_138)begin + if(when_DBusSimplePlugin_l512) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end - always @ (*) begin + always @(*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_137)begin + if(when_DBusSimplePlugin_l486) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_178}; - end - if(! memory_MMU_RSP2_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); - end + if(memory_ALIGNEMENT_FAULT) begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_DBusSimplePlugin_memoryExceptionPort_payload_code}; end end assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; - always @ (*) begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_redoBranch_valid = 1'b1; - end - if(_zz_138)begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - end - end - - assign DBusSimplePlugin_redoBranch_payload = memory_PC; - always @ (*) begin + assign when_DBusSimplePlugin_l486 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign when_DBusSimplePlugin_l512 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + always @(*) begin writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin @@ -2498,63 +2350,64 @@ module VexRiscv ( endcase end - assign _zz_67 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_68[31] = _zz_67; - _zz_68[30] = _zz_67; - _zz_68[29] = _zz_67; - _zz_68[28] = _zz_67; - _zz_68[27] = _zz_67; - _zz_68[26] = _zz_67; - _zz_68[25] = _zz_67; - _zz_68[24] = _zz_67; - _zz_68[23] = _zz_67; - _zz_68[22] = _zz_67; - _zz_68[21] = _zz_67; - _zz_68[20] = _zz_67; - _zz_68[19] = _zz_67; - _zz_68[18] = _zz_67; - _zz_68[17] = _zz_67; - _zz_68[16] = _zz_67; - _zz_68[15] = _zz_67; - _zz_68[14] = _zz_67; - _zz_68[13] = _zz_67; - _zz_68[12] = _zz_67; - _zz_68[11] = _zz_67; - _zz_68[10] = _zz_67; - _zz_68[9] = _zz_67; - _zz_68[8] = _zz_67; - _zz_68[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_69 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_70[31] = _zz_69; - _zz_70[30] = _zz_69; - _zz_70[29] = _zz_69; - _zz_70[28] = _zz_69; - _zz_70[27] = _zz_69; - _zz_70[26] = _zz_69; - _zz_70[25] = _zz_69; - _zz_70[24] = _zz_69; - _zz_70[23] = _zz_69; - _zz_70[22] = _zz_69; - _zz_70[21] = _zz_69; - _zz_70[20] = _zz_69; - _zz_70[19] = _zz_69; - _zz_70[18] = _zz_69; - _zz_70[17] = _zz_69; - _zz_70[16] = _zz_69; - _zz_70[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_153) + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusSimplePlugin_rspFormated = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_1[31] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[30] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[29] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[28] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[27] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[26] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[25] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[24] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[23] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[22] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[21] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[20] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[19] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[18] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[17] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[16] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[15] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[14] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[13] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[12] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[11] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[10] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[9] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[8] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_writeBack_DBusSimplePlugin_rspFormated_2 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_3[31] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[30] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[29] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[28] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[27] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[26] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[25] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[24] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[23] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[22] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[21] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[20] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[19] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[18] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[17] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[16] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_68; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_70; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_3; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -2562,77 +2415,61 @@ module VexRiscv ( endcase end - assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign IBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign IBusSimplePlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_72 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_73 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_74 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); - assign _zz_75 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_71 = {(((decode_INSTRUCTION & _zz_227) == 32'h00000050) != 1'b0),{((_zz_228 == _zz_229) != 1'b0),{({_zz_230,_zz_231} != 2'b00),{(_zz_232 != _zz_233),{_zz_234,{_zz_235,_zz_236}}}}}}; - assign _zz_76 = _zz_71[1 : 0]; - assign _zz_46 = _zz_76; - assign _zz_77 = _zz_71[6 : 5]; - assign _zz_45 = _zz_77; - assign _zz_78 = _zz_71[8 : 7]; - assign _zz_44 = _zz_78; - assign _zz_79 = _zz_71[17 : 16]; - assign _zz_43 = _zz_79; - assign _zz_80 = _zz_71[20 : 19]; - assign _zz_42 = _zz_80; - assign _zz_81 = _zz_71[22 : 21]; - assign _zz_41 = _zz_81; - assign _zz_82 = _zz_71[25 : 24]; - assign _zz_40 = _zz_82; + assign when_DBusSimplePlugin_l558 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_decode_ENV_CTRL_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_ENV_CTRL_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_ENV_CTRL_5 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz_decode_ENV_CTRL_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_ENV_CTRL_2 = {(((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2) == 32'h00000050) != 1'b0),{((_zz__zz_decode_ENV_CTRL_2_1 == _zz__zz_decode_ENV_CTRL_2_2) != 1'b0),{({_zz__zz_decode_ENV_CTRL_2_3,_zz__zz_decode_ENV_CTRL_2_5} != 2'b00),{(_zz__zz_decode_ENV_CTRL_2_7 != _zz__zz_decode_ENV_CTRL_2_10),{_zz__zz_decode_ENV_CTRL_2_11,{_zz__zz_decode_ENV_CTRL_2_14,_zz__zz_decode_ENV_CTRL_2_16}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_ENV_CTRL_2[1 : 0]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_ENV_CTRL_2[6 : 5]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_ENV_CTRL_2[8 : 7]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_ENV_CTRL_2[17 : 16]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_ENV_CTRL_2[20 : 19]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_ENV_CTRL_2[22 : 21]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_7 = _zz_decode_ENV_CTRL_2[25 : 24]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_7; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_126; - assign decode_RegFilePlugin_rs2Data = _zz_127; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); - if(_zz_83)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_37[11 : 7]; - if(_zz_83)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_47; - if(_zz_83)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_lastStageRegFileWrite_payload_data; + if(_zz_2) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -2641,394 +2478,434 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_84 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_84 = {31'd0, _zz_179}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_84 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_85 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_85 = {29'd0, _zz_180}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_85 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_85 = {27'd0, _zz_181}; - end - endcase - end - - assign _zz_86 = _zz_182[11]; - always @ (*) begin - _zz_87[19] = _zz_86; - _zz_87[18] = _zz_86; - _zz_87[17] = _zz_86; - _zz_87[16] = _zz_86; - _zz_87[15] = _zz_86; - _zz_87[14] = _zz_86; - _zz_87[13] = _zz_86; - _zz_87[12] = _zz_86; - _zz_87[11] = _zz_86; - _zz_87[10] = _zz_86; - _zz_87[9] = _zz_86; - _zz_87[8] = _zz_86; - _zz_87[7] = _zz_86; - _zz_87[6] = _zz_86; - _zz_87[5] = _zz_86; - _zz_87[4] = _zz_86; - _zz_87[3] = _zz_86; - _zz_87[2] = _zz_86; - _zz_87[1] = _zz_86; - _zz_87[0] = _zz_86; - end - - assign _zz_88 = _zz_183[11]; - always @ (*) begin - _zz_89[19] = _zz_88; - _zz_89[18] = _zz_88; - _zz_89[17] = _zz_88; - _zz_89[16] = _zz_88; - _zz_89[15] = _zz_88; - _zz_89[14] = _zz_88; - _zz_89[13] = _zz_88; - _zz_89[12] = _zz_88; - _zz_89[11] = _zz_88; - _zz_89[10] = _zz_88; - _zz_89[9] = _zz_88; - _zz_89[8] = _zz_88; - _zz_89[7] = _zz_88; - _zz_89[6] = _zz_88; - _zz_89[5] = _zz_88; - _zz_89[4] = _zz_88; - _zz_89[3] = _zz_88; - _zz_89[2] = _zz_88; - _zz_89[1] = _zz_88; - _zz_89[0] = _zz_88; - end - - always @ (*) begin + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; + end + endcase + end + + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_90 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_90 = {_zz_87,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_90 = {_zz_89,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_90 = _zz_32; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_184; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_binary_sequential_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); - always @ (*) begin + assign when_ShiftPlugins_l169 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_91 = (execute_LightShifterPlugin_shiftInput <<< 1); + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_execute_to_memory_REGFILE_WRITE_DATA_1 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_91 = _zz_191; + _zz_execute_to_memory_REGFILE_WRITE_DATA_1 = _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1; end endcase end - always @ (*) begin - _zz_92 = 1'b0; - if(_zz_94)begin - if((_zz_95 == decode_INSTRUCTION[19 : 15]))begin - _zz_92 = 1'b1; + assign when_ShiftPlugins_l175 = (! execute_arbitration_isStuckByOthers); + assign when_ShiftPlugins_l184 = (! execute_LightShifterPlugin_done); + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end - if(_zz_139)begin - if(_zz_140)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_92 = 1'b1; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l59) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_141)begin - if(_zz_142)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_92 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l59_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_143)begin - if(_zz_144)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_92 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l59_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_92 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_93 = 1'b0; - if(_zz_94)begin - if((_zz_95 == decode_INSTRUCTION[24 : 20]))begin - _zz_93 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end - if(_zz_139)begin - if(_zz_140)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_93 = 1'b1; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l62) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_141)begin - if(_zz_142)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_93 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l62_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_143)begin - if(_zz_144)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_93 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l62_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_93 = 1'b0; - end - end - + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_lastStageRegFileWrite_payload_data; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l59 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b1 || (! 1'b1)); + assign when_HazardSimplePlugin_l59_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l59_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_96 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_96 == 3'b000)) begin - _zz_97 = execute_BranchPlugin_eq; - end else if((_zz_96 == 3'b001)) begin - _zz_97 = (! execute_BranchPlugin_eq); - end else if((((_zz_96 & 3'b101) == 3'b101))) begin - _zz_97 = (! execute_SRC_LESS); - end else begin - _zz_97 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_DO = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_98 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_DO_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_98 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_DO_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_98 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_DO_1 = 1'b1; end default : begin - _zz_98 = _zz_97; - end - endcase - end - - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_99 = _zz_193[19]; - always @ (*) begin - _zz_100[10] = _zz_99; - _zz_100[9] = _zz_99; - _zz_100[8] = _zz_99; - _zz_100[7] = _zz_99; - _zz_100[6] = _zz_99; - _zz_100[5] = _zz_99; - _zz_100[4] = _zz_99; - _zz_100[3] = _zz_99; - _zz_100[2] = _zz_99; - _zz_100[1] = _zz_99; - _zz_100[0] = _zz_99; - end - - assign _zz_101 = _zz_194[11]; - always @ (*) begin - _zz_102[19] = _zz_101; - _zz_102[18] = _zz_101; - _zz_102[17] = _zz_101; - _zz_102[16] = _zz_101; - _zz_102[15] = _zz_101; - _zz_102[14] = _zz_101; - _zz_102[13] = _zz_101; - _zz_102[12] = _zz_101; - _zz_102[11] = _zz_101; - _zz_102[10] = _zz_101; - _zz_102[9] = _zz_101; - _zz_102[8] = _zz_101; - _zz_102[7] = _zz_101; - _zz_102[6] = _zz_101; - _zz_102[5] = _zz_101; - _zz_102[4] = _zz_101; - _zz_102[3] = _zz_101; - _zz_102[2] = _zz_101; - _zz_102[1] = _zz_101; - _zz_102[0] = _zz_101; - end - - assign _zz_103 = _zz_195[11]; - always @ (*) begin - _zz_104[18] = _zz_103; - _zz_104[17] = _zz_103; - _zz_104[16] = _zz_103; - _zz_104[15] = _zz_103; - _zz_104[14] = _zz_103; - _zz_104[13] = _zz_103; - _zz_104[12] = _zz_103; - _zz_104[11] = _zz_103; - _zz_104[10] = _zz_103; - _zz_104[9] = _zz_103; - _zz_104[8] = _zz_103; - _zz_104[7] = _zz_103; - _zz_104[6] = _zz_103; - _zz_104[5] = _zz_103; - _zz_104[4] = _zz_103; - _zz_104[3] = _zz_103; - _zz_104[2] = _zz_103; - _zz_104[1] = _zz_103; - _zz_104[0] = _zz_103; - end - - always @ (*) begin + _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; + end + endcase + end + + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JALR) ? execute_RS1 : execute_PC); + assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_105 = {{_zz_100,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_105 = {{_zz_104,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_105; + assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_106 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_107 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_108 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_109 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; - assign _zz_110 = _zz_196[0]; - assign _zz_111 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_112 = _zz_198[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_131)begin + if(decodeExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_132)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -3039,8 +2916,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3050,72 +2927,79 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_145)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_146)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_146)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3128,62 +3012,116 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_145)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_145)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_154) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign _zz_114 = (_zz_113 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_114 != 32'h0); - assign _zz_25 = decode_SRC1_CTRL; - assign _zz_23 = _zz_46; - assign _zz_34 = decode_to_execute_SRC1_CTRL; - assign _zz_22 = decode_ALU_CTRL; - assign _zz_20 = _zz_45; - assign _zz_35 = decode_to_execute_ALU_CTRL; - assign _zz_19 = decode_SRC2_CTRL; - assign _zz_17 = _zz_44; - assign _zz_33 = decode_to_execute_SRC2_CTRL; - assign _zz_16 = decode_ALU_BITWISE_CTRL; - assign _zz_14 = _zz_43; - assign _zz_36 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_13 = decode_SHIFT_CTRL; - assign _zz_11 = _zz_42; - assign _zz_31 = decode_to_execute_SHIFT_CTRL; - assign _zz_10 = decode_BRANCH_CTRL; - assign _zz_8 = _zz_41; - assign _zz_29 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_40; - assign _zz_27 = decode_to_execute_ENV_CTRL; - assign _zz_26 = execute_to_memory_ENV_CTRL; - assign _zz_28 = memory_to_writeBack_ENV_CTRL; + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_31 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_32 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_41 = ((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)); + assign when_Pipeline_l124_42 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -3204,115 +3142,141 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_115 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_115[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_115[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_115[3 : 3] = CsrPlugin_mstatus_MIE; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_116 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_116[11 : 11] = CsrPlugin_mip_MEIP; - _zz_116[7 : 7] = CsrPlugin_mip_MTIP; - _zz_116[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_117 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_117[11 : 11] = CsrPlugin_mie_MEIE; - _zz_117[7 : 7] = CsrPlugin_mie_MTIE; - _zz_117[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_118 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_118[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_119 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_119[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_119[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_120 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_120[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_121 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_121[31 : 0] = _zz_113; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_122 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_122[31 : 0] = _zz_114; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = (((_zz_115 | _zz_116) | (_zz_117 | _zz_118)) | ((_zz_119 | _zz_120) | (_zz_121 | _zz_122))); - assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); - assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; - assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; + assign CsrPlugin_csrMapping_readDataInit = (((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + always @(*) begin + iBus_cmd_ready = iBus_cmd_m2sPipe_ready; + if(when_Stream_l342) begin + iBus_cmd_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! iBus_cmd_m2sPipe_valid); + assign iBus_cmd_m2sPipe_valid = iBus_cmd_rValid; + assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_rData_pc; assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); assign iBusWishbone_CTI = 3'b000; assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK); assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO; assign iBus_rsp_payload_error = 1'b0; - assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; - assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; - assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; - assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; - assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; - assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBus_cmd_halfPipe_fire = (dBus_cmd_halfPipe_valid && dBus_cmd_halfPipe_ready); + assign dBus_cmd_ready = (! dBus_cmd_rValid); + assign dBus_cmd_halfPipe_valid = dBus_cmd_rValid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_rData_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_rData_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_rData_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_rData_size; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); assign dBusWishbone_CTI = 3'b000; assign dBusWishbone_BTE = 2'b00; - always @ (*) begin + always @(*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_123 = 4'b0001; + _zz_dBusWishbone_SEL = 4'b0001; end 2'b01 : begin - _zz_123 = 4'b0011; + _zz_dBusWishbone_SEL = 4'b0011; end default : begin - _zz_123 = 4'b1111; + _zz_dBusWishbone_SEL = 4'b1111; end endcase end - always @ (*) begin - dBusWishbone_SEL = (_zz_123 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - if((! dBus_cmd_halfPipe_payload_wr))begin + always @(*) begin + dBusWishbone_SEL = (_zz_dBusWishbone_SEL <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + if(when_DBusSimplePlugin_l189) begin dBusWishbone_SEL = 4'b1111; end end + assign when_DBusSimplePlugin_l189 = (! dBus_cmd_halfPipe_payload_wr); assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); @@ -3321,15 +3285,14 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - assign _zz_125 = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; IBusSimplePlugin_fetchPc_booted <= 1'b0; IBusSimplePlugin_fetchPc_inc <= 1'b0; - _zz_57 <= 1'b0; - _zz_58 <= 1'b0; + _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; @@ -3337,9 +3300,9 @@ module VexRiscv ( IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; IBusSimplePlugin_pending_value <= 3'b000; IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; - _zz_83 <= 1'b1; + _zz_2 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_94 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3356,91 +3319,90 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - _zz_113 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - iBus_cmd_m2sPipe_rValid <= 1'b0; - dBus_cmd_halfPipe_regs_valid <= 1'b0; - dBus_cmd_halfPipe_regs_ready <= 1'b1; + iBus_cmd_rValid <= 1'b0; + dBus_cmd_rValid <= 1'b0; end else begin - if(IBusSimplePlugin_fetchPc_correction)begin + if(IBusSimplePlugin_fetchPc_correction) begin IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + if(IBusSimplePlugin_fetchPc_output_fire) begin IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; end IBusSimplePlugin_fetchPc_booted <= 1'b1; - if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end - if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + if(IBusSimplePlugin_fetchPc_output_fire_1) begin IBusSimplePlugin_fetchPc_inc <= 1'b1; end - if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end - if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; end - if(IBusSimplePlugin_iBusRsp_flush)begin - _zz_57 <= 1'b0; + if(IBusSimplePlugin_iBusRsp_flush) begin + _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_55)begin - _zz_57 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(decode_arbitration_removeIt)begin - _zz_58 <= 1'b0; + if(decode_arbitration_removeIt) begin + _zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0; end - if(IBusSimplePlugin_iBusRsp_output_ready)begin - _zz_58 <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + if(IBusSimplePlugin_iBusRsp_output_ready) begin + _zz_IBusSimplePlugin_injector_decodeInput_valid <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin + if(when_Fetcher_l329_1) begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_175); - if(IBusSimplePlugin_iBusRsp_flush)begin - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_177); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter); + if(IBusSimplePlugin_iBusRsp_flush) begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2); end `ifndef SYNTHESIS `ifdef FORMAL @@ -3462,72 +3424,72 @@ module VexRiscv ( end `endif `endif - _zz_83 <= 1'b0; - if(_zz_129)begin - if(_zz_147)begin + _zz_2 <= 1'b0; + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l175) begin execute_LightShifterPlugin_isActive <= 1'b1; - if(execute_LightShifterPlugin_done)begin + if(execute_LightShifterPlugin_done) begin execute_LightShifterPlugin_isActive <= 1'b0; end end end - if(execute_arbitration_removeIt)begin + if(execute_arbitration_removeIt) begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_94 <= (_zz_38 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_148)begin - if(_zz_149)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_150)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_151)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_133)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3538,8 +3500,8 @@ module VexRiscv ( end endcase end - if(_zz_134)begin - case(_zz_135) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3549,124 +3511,113 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_108,{_zz_107,_zz_106}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_200[0]; - CsrPlugin_mstatus_MIE <= _zz_201[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_203[0]; - CsrPlugin_mie_MTIE <= _zz_204[0]; - CsrPlugin_mie_MSIE <= _zz_205[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_113 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(iBus_cmd_ready)begin - iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; + if(iBus_cmd_ready) begin + iBus_cmd_rValid <= iBus_cmd_valid; end - if(_zz_152)begin - dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; - dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); - end else begin - dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); - dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + if(dBus_cmd_valid) begin + dBus_cmd_rValid <= 1'b1; + end + if(dBus_cmd_halfPipe_fire) begin + dBus_cmd_rValid <= 1'b0; end end end - always @ (posedge clk) begin - if(IBusSimplePlugin_iBusRsp_output_ready)begin - _zz_59 <= IBusSimplePlugin_iBusRsp_output_payload_pc; - _zz_60 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; - _zz_61 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; - _zz_62 <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; + always @(posedge clk) begin + if(IBusSimplePlugin_iBusRsp_output_ready) begin + _zz_IBusSimplePlugin_injector_decodeInput_payload_pc <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; end - if(IBusSimplePlugin_injector_decodeInput_ready)begin + if(IBusSimplePlugin_injector_decodeInput_ready) begin IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; end - if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin - IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; - IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; - IBusSimplePlugin_mmu_joinCtx_isPaging <= IBusSimplePlugin_mmuBus_rsp_isPaging; - IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; - IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; - IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; - IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; - IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; - IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; - end - if(_zz_129)begin - if(_zz_147)begin + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l175) begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - _zz_95 <= _zz_37[11 : 7]; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_131)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_110 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_110 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(decodeExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= decodeExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= decodeExceptionPort_payload_badAddr; end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_132)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_112 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_112 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_148)begin - if(_zz_149)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_150)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_151)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_133)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -3675,209 +3626,195 @@ module VexRiscv ( endcase end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_32; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_6) begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_7) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_48; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_24; + if(when_Pipeline_l124_9) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_10) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_21; + if(when_Pipeline_l124_14) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_18; + if(when_Pipeline_l124_15) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_16) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_15; + if(when_Pipeline_l124_26) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_12; + if(when_Pipeline_l124_27) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_9; + if(when_Pipeline_l124_28) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_29) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_30) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_31) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_32) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_33) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_34) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_35) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; - execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; - execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; - execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; - execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; - execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; - execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; - execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; - execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + if(when_Pipeline_l124_41) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_execute_to_memory_REGFILE_WRITE_DATA; end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_30; - end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_202[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(iBus_cmd_ready)begin - iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; + if(iBus_cmd_ready) begin + iBus_cmd_rData_pc <= iBus_cmd_payload_pc; end - if(_zz_152)begin - dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; - dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; - dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; - dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + if(dBus_cmd_ready) begin + dBus_cmd_rData_wr <= dBus_cmd_payload_wr; + dBus_cmd_rData_address <= dBus_cmd_payload_address; + dBus_cmd_rData_data <= dBus_cmd_payload_data; + dBus_cmd_rData_size <= dBus_cmd_payload_size; end end @@ -3898,9 +3835,7 @@ module StreamFifoLowLatency ( input clk, input reset ); - wire _zz_4; - wire [0:0] _zz_5; - reg _zz_1; + reg when_Phase_l623; reg pushPtr_willIncrement; reg pushPtr_willClear; wire pushPtr_willOverflowIfInc; @@ -3915,44 +3850,44 @@ module StreamFifoLowLatency ( wire full; wire pushing; wire popping; - wire [32:0] _zz_2; - reg [32:0] _zz_3; + wire when_Stream_l995; + wire [32:0] _zz_io_pop_payload_error; + wire when_Stream_l1008; + reg [32:0] _zz_io_pop_payload_error_1; - assign _zz_4 = (! empty); - assign _zz_5 = _zz_2[0 : 0]; - always @ (*) begin - _zz_1 = 1'b0; - if(pushing)begin - _zz_1 = 1'b1; + always @(*) begin + when_Phase_l623 = 1'b0; + if(pushing) begin + when_Phase_l623 = 1'b1; end end - always @ (*) begin + always @(*) begin pushPtr_willIncrement = 1'b0; - if(pushing)begin + if(pushing) begin pushPtr_willIncrement = 1'b1; end end - always @ (*) begin + always @(*) begin pushPtr_willClear = 1'b0; - if(io_flush)begin + if(io_flush) begin pushPtr_willClear = 1'b1; end end assign pushPtr_willOverflowIfInc = 1'b1; assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); - always @ (*) begin + always @(*) begin popPtr_willIncrement = 1'b0; - if(popping)begin + if(popping) begin popPtr_willIncrement = 1'b1; end end - always @ (*) begin + always @(*) begin popPtr_willClear = 1'b0; - if(io_flush)begin + if(io_flush) begin popPtr_willClear = 1'b1; end end @@ -3965,48 +3900,50 @@ module StreamFifoLowLatency ( assign pushing = (io_push_valid && io_push_ready); assign popping = (io_pop_valid && io_pop_ready); assign io_push_ready = (! full); - always @ (*) begin - if(_zz_4)begin + assign when_Stream_l995 = (! empty); + always @(*) begin + if(when_Stream_l995) begin io_pop_valid = 1'b1; end else begin io_pop_valid = io_push_valid; end end - assign _zz_2 = _zz_3; - always @ (*) begin - if(_zz_4)begin - io_pop_payload_error = _zz_5[0]; + assign _zz_io_pop_payload_error = _zz_io_pop_payload_error_1; + always @(*) begin + if(when_Stream_l995) begin + io_pop_payload_error = _zz_io_pop_payload_error[0]; end else begin io_pop_payload_error = io_push_payload_error; end end - always @ (*) begin - if(_zz_4)begin - io_pop_payload_inst = _zz_2[32 : 1]; + always @(*) begin + if(when_Stream_l995) begin + io_pop_payload_inst = _zz_io_pop_payload_error[32 : 1]; end else begin io_pop_payload_inst = io_push_payload_inst; end end + assign when_Stream_l1008 = (pushing != popping); assign io_occupancy = (risingOccupancy && ptrMatch); - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin risingOccupancy <= 1'b0; end else begin - if((pushing != popping))begin + if(when_Stream_l1008) begin risingOccupancy <= pushing; end - if(io_flush)begin + if(io_flush) begin risingOccupancy <= 1'b0; end end end - always @ (posedge clk) begin - if(_zz_1)begin - _zz_3 <= {io_push_payload_inst,io_push_payload_error}; + always @(posedge clk) begin + if(when_Phase_l623) begin + _zz_io_pop_payload_error_1 <= {io_push_payload_inst,io_push_payload_error}; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v index a777070..8f08a8e 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v @@ -1,46 +1,46 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : e78ff1c6772b33f1f3adf05557c1928a170ed641 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b10 -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( @@ -81,231 +81,180 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_126; - wire _zz_127; - reg [31:0] _zz_128; - reg [31:0] _zz_129; - reg [31:0] _zz_130; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid; wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; wire [0:0] IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy; - wire _zz_131; - wire _zz_132; - wire _zz_133; - wire _zz_134; - wire _zz_135; - wire _zz_136; - wire _zz_137; - wire _zz_138; - wire _zz_139; - wire [1:0] _zz_140; - wire _zz_141; - wire _zz_142; - wire _zz_143; - wire _zz_144; - wire _zz_145; - wire _zz_146; - wire _zz_147; - wire _zz_148; - wire _zz_149; - wire _zz_150; - wire _zz_151; - wire [5:0] _zz_152; - wire _zz_153; - wire _zz_154; - wire _zz_155; - wire _zz_156; - wire _zz_157; - wire _zz_158; - wire [1:0] _zz_159; - wire _zz_160; - wire [0:0] _zz_161; - wire [0:0] _zz_162; - wire [0:0] _zz_163; - wire [0:0] _zz_164; - wire [0:0] _zz_165; - wire [0:0] _zz_166; - wire [0:0] _zz_167; - wire [0:0] _zz_168; - wire [0:0] _zz_169; - wire [0:0] _zz_170; - wire [0:0] _zz_171; - wire [0:0] _zz_172; - wire [2:0] _zz_173; - wire [2:0] _zz_174; - wire [31:0] _zz_175; - wire [2:0] _zz_176; - wire [0:0] _zz_177; - wire [2:0] _zz_178; - wire [0:0] _zz_179; - wire [2:0] _zz_180; - wire [0:0] _zz_181; - wire [2:0] _zz_182; - wire [0:0] _zz_183; - wire [2:0] _zz_184; - wire [2:0] _zz_185; - wire [0:0] _zz_186; - wire [2:0] _zz_187; - wire [4:0] _zz_188; - wire [11:0] _zz_189; - wire [11:0] _zz_190; - wire [31:0] _zz_191; - wire [31:0] _zz_192; - wire [31:0] _zz_193; - wire [31:0] _zz_194; - wire [31:0] _zz_195; - wire [31:0] _zz_196; - wire [31:0] _zz_197; - wire [31:0] _zz_198; - wire [32:0] _zz_199; - wire [19:0] _zz_200; - wire [11:0] _zz_201; - wire [11:0] _zz_202; - wire [1:0] _zz_203; - wire [1:0] _zz_204; - wire [1:0] _zz_205; - wire [1:0] _zz_206; - wire [0:0] _zz_207; - wire [0:0] _zz_208; - wire [0:0] _zz_209; - wire [0:0] _zz_210; - wire [0:0] _zz_211; - wire [0:0] _zz_212; - wire _zz_213; - wire _zz_214; - wire [1:0] _zz_215; - wire [31:0] _zz_216; - wire [31:0] _zz_217; - wire [31:0] _zz_218; - wire _zz_219; - wire [0:0] _zz_220; - wire [12:0] _zz_221; - wire [31:0] _zz_222; - wire [31:0] _zz_223; - wire [31:0] _zz_224; - wire _zz_225; - wire [0:0] _zz_226; - wire [6:0] _zz_227; - wire [31:0] _zz_228; - wire [31:0] _zz_229; - wire [31:0] _zz_230; - wire _zz_231; - wire [0:0] _zz_232; - wire [0:0] _zz_233; - wire [31:0] _zz_234; - wire [31:0] _zz_235; - wire [31:0] _zz_236; - wire _zz_237; - wire [1:0] _zz_238; - wire [1:0] _zz_239; - wire _zz_240; - wire [0:0] _zz_241; - wire [20:0] _zz_242; - wire [31:0] _zz_243; - wire [31:0] _zz_244; - wire [31:0] _zz_245; - wire [31:0] _zz_246; - wire _zz_247; - wire _zz_248; - wire [0:0] _zz_249; - wire [0:0] _zz_250; - wire _zz_251; - wire [0:0] _zz_252; - wire [17:0] _zz_253; - wire [31:0] _zz_254; - wire _zz_255; - wire _zz_256; - wire [0:0] _zz_257; - wire [0:0] _zz_258; - wire [0:0] _zz_259; - wire [0:0] _zz_260; - wire _zz_261; - wire [0:0] _zz_262; - wire [14:0] _zz_263; - wire [31:0] _zz_264; - wire [31:0] _zz_265; - wire [31:0] _zz_266; - wire [31:0] _zz_267; - wire [31:0] _zz_268; - wire [0:0] _zz_269; - wire [0:0] _zz_270; - wire [1:0] _zz_271; - wire [1:0] _zz_272; - wire _zz_273; - wire [0:0] _zz_274; - wire [11:0] _zz_275; - wire [31:0] _zz_276; - wire [31:0] _zz_277; - wire [31:0] _zz_278; - wire [31:0] _zz_279; - wire [31:0] _zz_280; - wire [31:0] _zz_281; - wire _zz_282; - wire [0:0] _zz_283; - wire [0:0] _zz_284; - wire _zz_285; - wire [0:0] _zz_286; - wire [0:0] _zz_287; - wire _zz_288; - wire [0:0] _zz_289; - wire [8:0] _zz_290; - wire [31:0] _zz_291; - wire [31:0] _zz_292; - wire [31:0] _zz_293; - wire [0:0] _zz_294; - wire [4:0] _zz_295; - wire [1:0] _zz_296; - wire [1:0] _zz_297; - wire _zz_298; - wire [0:0] _zz_299; - wire [5:0] _zz_300; - wire [31:0] _zz_301; - wire [31:0] _zz_302; - wire _zz_303; - wire [0:0] _zz_304; - wire [1:0] _zz_305; - wire [31:0] _zz_306; - wire [31:0] _zz_307; - wire _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire [0:0] _zz_312; - wire _zz_313; - wire [0:0] _zz_314; - wire [2:0] _zz_315; - wire [31:0] _zz_316; - wire _zz_317; - wire _zz_318; - wire [31:0] _zz_319; - wire [31:0] _zz_320; - wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [0:0] _zz_326; - wire [2:0] _zz_327; - wire [0:0] _zz_328; - wire [0:0] _zz_329; - wire _zz_330; - wire [0:0] _zz_331; - wire [0:0] _zz_332; - wire [31:0] _zz_333; - wire [31:0] _zz_334; - wire [31:0] _zz_335; - wire _zz_336; - wire _zz_337; - wire [31:0] _zz_338; - wire _zz_339; - wire [0:0] _zz_340; - wire [0:0] _zz_341; - wire [0:0] _zz_342; - wire [0:0] _zz_343; - wire [0:0] _zz_344; - wire [0:0] _zz_345; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [12:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [6:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload_1; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload_2; + wire [31:0] _zz_IBusSimplePlugin_fetchPc_pc; + wire [2:0] _zz_IBusSimplePlugin_fetchPc_pc_1; + wire [2:0] _zz_IBusSimplePlugin_pending_next; + wire [2:0] _zz_IBusSimplePlugin_pending_next_1; + wire [0:0] _zz_IBusSimplePlugin_pending_next_2; + wire [2:0] _zz_IBusSimplePlugin_pending_next_3; + wire [0:0] _zz_IBusSimplePlugin_pending_next_4; + wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; + wire [0:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1; + wire [2:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2; + wire [0:0] _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3; + wire [2:0] _zz_DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] _zz__zz_decode_ENV_CTRL_2; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_1; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_2; + wire _zz__zz_decode_ENV_CTRL_2_3; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_4; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_5; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_6; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_7; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_8; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_9; + wire _zz__zz_decode_ENV_CTRL_2_10; + wire _zz__zz_decode_ENV_CTRL_2_11; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_12; + wire _zz__zz_decode_ENV_CTRL_2_13; + wire [20:0] _zz__zz_decode_ENV_CTRL_2_14; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_15; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_16; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_17; + wire _zz__zz_decode_ENV_CTRL_2_18; + wire _zz__zz_decode_ENV_CTRL_2_19; + wire _zz__zz_decode_ENV_CTRL_2_20; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_21; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_22; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_23; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_24; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_25; + wire [17:0] _zz__zz_decode_ENV_CTRL_2_26; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_27; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_28; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_29; + wire _zz__zz_decode_ENV_CTRL_2_30; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_31; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_32; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_33; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_34; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_35; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_36; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_37; + wire [14:0] _zz__zz_decode_ENV_CTRL_2_38; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_39; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_40; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_41; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_42; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_43; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_44; + wire _zz__zz_decode_ENV_CTRL_2_45; + wire _zz__zz_decode_ENV_CTRL_2_46; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_47; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_48; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_49; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_50; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_51; + wire _zz__zz_decode_ENV_CTRL_2_52; + wire [11:0] _zz__zz_decode_ENV_CTRL_2_53; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_54; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_55; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_56; + wire _zz__zz_decode_ENV_CTRL_2_57; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_58; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_59; + wire [4:0] _zz__zz_decode_ENV_CTRL_2_60; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_61; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_62; + wire _zz__zz_decode_ENV_CTRL_2_63; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_64; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_65; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_66; + wire _zz__zz_decode_ENV_CTRL_2_67; + wire _zz__zz_decode_ENV_CTRL_2_68; + wire [8:0] _zz__zz_decode_ENV_CTRL_2_69; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_70; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_71; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_72; + wire [1:0] _zz__zz_decode_ENV_CTRL_2_73; + wire _zz__zz_decode_ENV_CTRL_2_74; + wire _zz__zz_decode_ENV_CTRL_2_75; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_76; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_77; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_78; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_79; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_80; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_81; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_82; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_83; + wire [5:0] _zz__zz_decode_ENV_CTRL_2_84; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_85; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_86; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_87; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_88; + wire _zz__zz_decode_ENV_CTRL_2_89; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_90; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_91; + wire [2:0] _zz__zz_decode_ENV_CTRL_2_92; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_93; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_94; + wire _zz__zz_decode_ENV_CTRL_2_95; + wire _zz__zz_decode_ENV_CTRL_2_96; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_97; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_98; + wire [31:0] _zz__zz_decode_ENV_CTRL_2_99; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_100; + wire [2:0] _zz__zz_decode_ENV_CTRL_2_101; + wire _zz__zz_decode_ENV_CTRL_2_102; + wire _zz__zz_decode_ENV_CTRL_2_103; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_104; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_105; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_106; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_107; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_108; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_109; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_110; + wire [0:0] _zz__zz_decode_ENV_CTRL_2_111; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [31:0] _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1; + wire [32:0] _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; wire [31:0] memory_MEMORY_READ_DATA; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; @@ -319,65 +268,67 @@ module VexRiscv ( wire decode_SRC2_FORCE_ZERO; wire [31:0] decode_RS2; wire [31:0] decode_RS1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_1; - wire `EnvCtrlEnum_defaultEncoding_type _zz_2; - wire `EnvCtrlEnum_defaultEncoding_type _zz_3; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_8; - wire `BranchCtrlEnum_defaultEncoding_type _zz_9; - wire `BranchCtrlEnum_defaultEncoding_type _zz_10; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_11; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_14; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_15; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_16; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_STORE; wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_17; - wire `Src2CtrlEnum_defaultEncoding_type _zz_18; - wire `Src2CtrlEnum_defaultEncoding_type _zz_19; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_20; - wire `AluCtrlEnum_defaultEncoding_type _zz_21; - wire `AluCtrlEnum_defaultEncoding_type _zz_22; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_23; - wire `Src1CtrlEnum_defaultEncoding_type _zz_24; - wire `Src1CtrlEnum_defaultEncoding_type _zz_25; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire decode_MEMORY_ENABLE; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; wire execute_DO_EBREAK; wire decode_IS_EBREAK; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_26; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_27; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_28; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] memory_BRANCH_CALC; wire memory_BRANCH_DO; wire [31:0] execute_PC; wire [31:0] execute_RS1; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_29; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; wire execute_REGFILE_WRITE_VALID; @@ -386,78 +337,56 @@ module VexRiscv ( wire [31:0] memory_INSTRUCTION; wire memory_BYPASSABLE_MEMORY_STAGE; wire writeBack_REGFILE_WRITE_VALID; - reg [31:0] _zz_30; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_31; + reg [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_32; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_33; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_34; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_35; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_36; - wire [31:0] _zz_37; - wire _zz_38; - reg _zz_39; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `EnvCtrlEnum_defaultEncoding_type _zz_40; - wire `BranchCtrlEnum_defaultEncoding_type _zz_41; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_42; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_43; - wire `Src2CtrlEnum_defaultEncoding_type _zz_44; - wire `AluCtrlEnum_defaultEncoding_type _zz_45; - wire `Src1CtrlEnum_defaultEncoding_type _zz_46; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; wire writeBack_MEMORY_STORE; - reg [31:0] _zz_47; + reg [31:0] _zz_lastStageRegFileWrite_payload_data; wire writeBack_MEMORY_ENABLE; wire [1:0] writeBack_MEMORY_ADDRESS_LOW; wire [31:0] writeBack_MEMORY_READ_DATA; - wire memory_MMU_FAULT; - wire [31:0] memory_MMU_RSP2_physicalAddress; - wire memory_MMU_RSP2_isIoAccess; - wire memory_MMU_RSP2_isPaging; - wire memory_MMU_RSP2_allowRead; - wire memory_MMU_RSP2_allowWrite; - wire memory_MMU_RSP2_allowExecute; - wire memory_MMU_RSP2_exception; - wire memory_MMU_RSP2_refilling; - wire memory_MMU_RSP2_bypassTranslation; - wire [31:0] memory_PC; wire memory_ALIGNEMENT_FAULT; wire [31:0] memory_REGFILE_WRITE_DATA; wire memory_MEMORY_STORE; wire memory_MEMORY_ENABLE; - wire execute_MMU_FAULT; - wire [31:0] execute_MMU_RSP2_physicalAddress; - wire execute_MMU_RSP2_isIoAccess; - wire execute_MMU_RSP2_isPaging; - wire execute_MMU_RSP2_allowRead; - wire execute_MMU_RSP2_allowWrite; - wire execute_MMU_RSP2_allowExecute; - wire execute_MMU_RSP2_exception; - wire execute_MMU_RSP2_refilling; - wire execute_MMU_RSP2_bypassTranslation; wire [31:0] execute_SRC_ADD; wire [31:0] execute_RS2; wire [31:0] execute_INSTRUCTION; wire execute_MEMORY_STORE; wire execute_MEMORY_ENABLE; wire execute_ALIGNEMENT_FAULT; - wire decode_MEMORY_ENABLE; - reg [31:0] _zz_48; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] decode_INSTRUCTION; wire [31:0] writeBack_PC; @@ -487,7 +416,7 @@ module VexRiscv ( reg memory_arbitration_haltItself; wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; - reg memory_arbitration_flushIt; + wire memory_arbitration_flushIt; reg memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; @@ -517,49 +446,14 @@ module VexRiscv ( wire IBusSimplePlugin_pcValids_2; wire IBusSimplePlugin_pcValids_3; wire iBus_cmd_valid; - wire iBus_cmd_ready; + reg iBus_cmd_ready; wire [31:0] iBus_cmd_payload_pc; wire iBus_rsp_valid; wire iBus_rsp_payload_error; wire [31:0] iBus_rsp_payload_inst; - wire IBusSimplePlugin_decodeExceptionPort_valid; - reg [3:0] IBusSimplePlugin_decodeExceptionPort_payload_code; - wire [31:0] IBusSimplePlugin_decodeExceptionPort_payload_badAddr; - wire IBusSimplePlugin_mmuBus_cmd_0_isValid; - wire IBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] IBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire IBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire IBusSimplePlugin_mmuBus_rsp_isPaging; - wire IBusSimplePlugin_mmuBus_rsp_allowRead; - wire IBusSimplePlugin_mmuBus_rsp_allowWrite; - wire IBusSimplePlugin_mmuBus_rsp_allowExecute; - wire IBusSimplePlugin_mmuBus_rsp_exception; - wire IBusSimplePlugin_mmuBus_rsp_refilling; - wire IBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire IBusSimplePlugin_mmuBus_end; - wire IBusSimplePlugin_mmuBus_busy; reg DBusSimplePlugin_memoryExceptionPort_valid; reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; - wire DBusSimplePlugin_mmuBus_cmd_0_isValid; - wire DBusSimplePlugin_mmuBus_cmd_0_isStuck; - wire [31:0] DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - wire DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation; - wire [31:0] DBusSimplePlugin_mmuBus_rsp_physicalAddress; - wire DBusSimplePlugin_mmuBus_rsp_isIoAccess; - wire DBusSimplePlugin_mmuBus_rsp_isPaging; - wire DBusSimplePlugin_mmuBus_rsp_allowRead; - wire DBusSimplePlugin_mmuBus_rsp_allowWrite; - wire DBusSimplePlugin_mmuBus_rsp_allowExecute; - wire DBusSimplePlugin_mmuBus_rsp_exception; - wire DBusSimplePlugin_mmuBus_rsp_refilling; - wire DBusSimplePlugin_mmuBus_rsp_bypassTranslation; - wire DBusSimplePlugin_mmuBus_end; - wire DBusSimplePlugin_mmuBus_busy; - reg DBusSimplePlugin_redoBranch_valid; - wire [31:0] DBusSimplePlugin_redoBranch_payload; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -568,6 +462,11 @@ module VexRiscv ( wire BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; wire CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -585,31 +484,32 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; reg CsrPlugin_allowInterrupts; reg CsrPlugin_allowException; + reg CsrPlugin_allowEbreakException; reg IBusSimplePlugin_injectionPort_valid; reg IBusSimplePlugin_injectionPort_ready; wire [31:0] IBusSimplePlugin_injectionPort_payload; wire IBusSimplePlugin_externalFlush; wire IBusSimplePlugin_jump_pcLoad_valid; wire [31:0] IBusSimplePlugin_jump_pcLoad_payload; - wire [2:0] _zz_49; - wire [2:0] _zz_50; - wire _zz_51; - wire _zz_52; + wire [1:0] _zz_IBusSimplePlugin_jump_pcLoad_payload; wire IBusSimplePlugin_fetchPc_output_valid; wire IBusSimplePlugin_fetchPc_output_ready; wire [31:0] IBusSimplePlugin_fetchPc_output_payload; reg [31:0] IBusSimplePlugin_fetchPc_pcReg /* verilator public */ ; reg IBusSimplePlugin_fetchPc_correction; reg IBusSimplePlugin_fetchPc_correctionReg; + wire IBusSimplePlugin_fetchPc_output_fire; wire IBusSimplePlugin_fetchPc_corrected; reg IBusSimplePlugin_fetchPc_pcRegPropagate; reg IBusSimplePlugin_fetchPc_booted; reg IBusSimplePlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusSimplePlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusSimplePlugin_fetchPc_pc; - wire IBusSimplePlugin_fetchPc_redo_valid; - wire [31:0] IBusSimplePlugin_fetchPc_redo_payload; reg IBusSimplePlugin_fetchPc_flushed; - reg IBusSimplePlugin_iBusRsp_redoFetch; + wire when_Fetcher_l158; + wire IBusSimplePlugin_iBusRsp_redoFetch; wire IBusSimplePlugin_iBusRsp_stages_0_input_valid; wire IBusSimplePlugin_iBusRsp_stages_0_input_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_0_input_payload; @@ -624,12 +524,12 @@ module VexRiscv ( wire IBusSimplePlugin_iBusRsp_stages_1_output_ready; wire [31:0] IBusSimplePlugin_iBusRsp_stages_1_output_payload; wire IBusSimplePlugin_iBusRsp_stages_1_halt; - wire _zz_53; - wire _zz_54; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready; wire IBusSimplePlugin_iBusRsp_flush; - wire _zz_55; - wire _zz_56; - reg _zz_57; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2; reg IBusSimplePlugin_iBusRsp_readyForError; wire IBusSimplePlugin_iBusRsp_output_valid; wire IBusSimplePlugin_iBusRsp_output_ready; @@ -643,18 +543,24 @@ module VexRiscv ( wire IBusSimplePlugin_injector_decodeInput_payload_rsp_error; wire [31:0] IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; wire IBusSimplePlugin_injector_decodeInput_payload_isRvc; - reg _zz_58; - reg [31:0] _zz_59; - reg _zz_60; - reg [31:0] _zz_61; - reg _zz_62; + reg _zz_IBusSimplePlugin_injector_decodeInput_valid; + reg [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_pc; + reg _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + reg [31:0] _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + reg _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc; + wire when_Fetcher_l320; reg IBusSimplePlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusSimplePlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusSimplePlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusSimplePlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusSimplePlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l329_4; reg [31:0] IBusSimplePlugin_injector_formal_rawInDecode; - reg IBusSimplePlugin_cmd_valid; + wire IBusSimplePlugin_cmd_valid; wire IBusSimplePlugin_cmd_ready; wire [31:0] IBusSimplePlugin_cmd_payload_pc; wire IBusSimplePlugin_pending_inc; @@ -662,33 +568,30 @@ module VexRiscv ( reg [2:0] IBusSimplePlugin_pending_value; wire [2:0] IBusSimplePlugin_pending_next; wire IBusSimplePlugin_cmdFork_canEmit; - reg [31:0] IBusSimplePlugin_mmu_joinCtx_physicalAddress; - reg IBusSimplePlugin_mmu_joinCtx_isIoAccess; - reg IBusSimplePlugin_mmu_joinCtx_isPaging; - reg IBusSimplePlugin_mmu_joinCtx_allowRead; - reg IBusSimplePlugin_mmu_joinCtx_allowWrite; - reg IBusSimplePlugin_mmu_joinCtx_allowExecute; - reg IBusSimplePlugin_mmu_joinCtx_exception; - reg IBusSimplePlugin_mmu_joinCtx_refilling; - reg IBusSimplePlugin_mmu_joinCtx_bypassTranslation; + wire when_IBusSimplePlugin_l304; + wire IBusSimplePlugin_cmd_fire; wire IBusSimplePlugin_rspJoin_rspBuffer_output_valid; wire IBusSimplePlugin_rspJoin_rspBuffer_output_ready; wire IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; wire [31:0] IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; reg [2:0] IBusSimplePlugin_rspJoin_rspBuffer_discardCounter; wire IBusSimplePlugin_rspJoin_rspBuffer_flush; + wire IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_pc; reg IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; wire [31:0] IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; wire IBusSimplePlugin_rspJoin_fetchRsp_isRvc; + wire when_IBusSimplePlugin_l375; wire IBusSimplePlugin_rspJoin_join_valid; wire IBusSimplePlugin_rspJoin_join_ready; wire [31:0] IBusSimplePlugin_rspJoin_join_payload_pc; wire IBusSimplePlugin_rspJoin_join_payload_rsp_error; wire [31:0] IBusSimplePlugin_rspJoin_join_payload_rsp_inst; wire IBusSimplePlugin_rspJoin_join_payload_isRvc; - reg IBusSimplePlugin_rspJoin_exceptionDetected; - wire _zz_63; + wire IBusSimplePlugin_rspJoin_exceptionDetected; + wire IBusSimplePlugin_rspJoin_join_fire; + wire IBusSimplePlugin_rspJoin_join_fire_1; + wire _zz_IBusSimplePlugin_iBusRsp_output_valid; wire dBus_cmd_valid; wire dBus_cmd_ready; wire dBus_cmd_payload_wr; @@ -698,29 +601,36 @@ module VexRiscv ( wire dBus_rsp_ready; wire dBus_rsp_error; wire [31:0] dBus_rsp_data; - wire _zz_64; + wire _zz_dBus_cmd_valid; reg execute_DBusSimplePlugin_skipCmd; - reg [31:0] _zz_65; - reg [3:0] _zz_66; + reg [31:0] _zz_dBus_cmd_payload_data; + wire when_DBusSimplePlugin_l426; + reg [3:0] _zz_execute_DBusSimplePlugin_formalMask; wire [3:0] execute_DBusSimplePlugin_formalMask; + wire when_DBusSimplePlugin_l479; + wire when_DBusSimplePlugin_l486; + wire when_DBusSimplePlugin_l512; reg [31:0] writeBack_DBusSimplePlugin_rspShifted; - wire _zz_67; - reg [31:0] _zz_68; - wire _zz_69; - reg [31:0] _zz_70; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusSimplePlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_1; + wire _zz_writeBack_DBusSimplePlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusSimplePlugin_rspFormated_3; reg [31:0] writeBack_DBusSimplePlugin_rspFormated; - wire [26:0] _zz_71; - wire _zz_72; - wire _zz_73; - wire _zz_74; - wire _zz_75; - wire `Src1CtrlEnum_defaultEncoding_type _zz_76; - wire `AluCtrlEnum_defaultEncoding_type _zz_77; - wire `Src2CtrlEnum_defaultEncoding_type _zz_78; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_79; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_80; - wire `BranchCtrlEnum_defaultEncoding_type _zz_81; - wire `EnvCtrlEnum_defaultEncoding_type _zz_82; + wire when_DBusSimplePlugin_l558; + wire [26:0] _zz_decode_ENV_CTRL_2; + wire _zz_decode_ENV_CTRL_3; + wire _zz_decode_ENV_CTRL_4; + wire _zz_decode_ENV_CTRL_5; + wire _zz_decode_ENV_CTRL_6; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_7; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -728,15 +638,15 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_83; + reg _zz_2; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_84; - reg [31:0] _zz_85; - wire _zz_86; - reg [19:0] _zz_87; - wire _zz_88; - reg [19:0] _zz_89; - reg [31:0] _zz_90; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; reg execute_LightShifterPlugin_isActive; @@ -745,23 +655,47 @@ module VexRiscv ( wire [4:0] execute_LightShifterPlugin_amplitude; wire [31:0] execute_LightShifterPlugin_shiftInput; wire execute_LightShifterPlugin_done; - reg [31:0] _zz_91; - reg _zz_92; - reg _zz_93; - reg _zz_94; - reg [4:0] _zz_95; + wire when_ShiftPlugins_l169; + reg [31:0] _zz_execute_to_memory_REGFILE_WRITE_DATA_1; + wire when_ShiftPlugins_l175; + wire when_ShiftPlugins_l184; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l59; + wire when_HazardSimplePlugin_l62; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l59_1; + wire when_HazardSimplePlugin_l62_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l59_2; + wire when_HazardSimplePlugin_l62_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_96; - reg _zz_97; - reg _zz_98; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_DO; + reg _zz_execute_BRANCH_DO_1; wire [31:0] execute_BranchPlugin_branch_src1; - wire _zz_99; - reg [10:0] _zz_100; - wire _zz_101; - reg [19:0] _zz_102; - wire _zz_103; - reg [18:0] _zz_104; - reg [31:0] _zz_105; + wire _zz_execute_BranchPlugin_branch_src2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + reg [31:0] _zz_execute_BranchPlugin_branch_src2_6; wire [31:0] execute_BranchPlugin_branch_src2; wire [31:0] execute_BranchPlugin_branchAdder; wire [1:0] CsrPlugin_misa_base; @@ -783,9 +717,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_106; - wire _zz_107; - wire _zz_108; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -798,41 +732,62 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_109; - wire _zz_110; - wire [1:0] _zz_111; - wire _zz_112; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; wire CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_113; - wire [31:0] _zz_114; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -840,169 +795,244 @@ module VexRiscv ( reg DebugPlugin_stepIt; reg DebugPlugin_isPipBusy; reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_115; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_9; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_11; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_12; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_14; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_15; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_16; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_17; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_21; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg decode_to_execute_MEMORY_STORE; + wire when_Pipeline_l124_23; reg execute_to_memory_MEMORY_STORE; + wire when_Pipeline_l124_24; reg memory_to_writeBack_MEMORY_STORE; + wire when_Pipeline_l124_25; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_26; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_27; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_28; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_29; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_30; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_31; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_32; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_33; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_34; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_35; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_36; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_37; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_38; reg decode_to_execute_DO_EBREAK; + wire when_Pipeline_l124_39; reg execute_to_memory_ALIGNEMENT_FAULT; + wire when_Pipeline_l124_40; reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_41; reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; - reg execute_to_memory_MMU_FAULT; - reg [31:0] execute_to_memory_MMU_RSP2_physicalAddress; - reg execute_to_memory_MMU_RSP2_isIoAccess; - reg execute_to_memory_MMU_RSP2_isPaging; - reg execute_to_memory_MMU_RSP2_allowRead; - reg execute_to_memory_MMU_RSP2_allowWrite; - reg execute_to_memory_MMU_RSP2_allowExecute; - reg execute_to_memory_MMU_RSP2_exception; - reg execute_to_memory_MMU_RSP2_refilling; - reg execute_to_memory_MMU_RSP2_bypassTranslation; + wire when_Pipeline_l124_42; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_43; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_44; reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_45; reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_46; reg [31:0] memory_to_writeBack_MEMORY_READ_DATA; - reg [2:0] _zz_116; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l378; + wire when_Fetcher_l398; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_117; - reg [31:0] _zz_118; - reg [31:0] _zz_119; - reg [31:0] _zz_120; - reg [31:0] _zz_121; - reg [31:0] _zz_122; - reg [31:0] _zz_123; - reg [31:0] _zz_124; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; wire iBus_cmd_m2sPipe_valid; wire iBus_cmd_m2sPipe_ready; wire [31:0] iBus_cmd_m2sPipe_payload_pc; - reg iBus_cmd_m2sPipe_rValid; - reg [31:0] iBus_cmd_m2sPipe_rData_pc; + reg iBus_cmd_rValid; + reg [31:0] iBus_cmd_rData_pc; + wire when_Stream_l342; wire dBus_cmd_halfPipe_valid; wire dBus_cmd_halfPipe_ready; wire dBus_cmd_halfPipe_payload_wr; wire [31:0] dBus_cmd_halfPipe_payload_address; wire [31:0] dBus_cmd_halfPipe_payload_data; wire [1:0] dBus_cmd_halfPipe_payload_size; - reg dBus_cmd_halfPipe_regs_valid; - reg dBus_cmd_halfPipe_regs_ready; - reg dBus_cmd_halfPipe_regs_payload_wr; - reg [31:0] dBus_cmd_halfPipe_regs_payload_address; - reg [31:0] dBus_cmd_halfPipe_regs_payload_data; - reg [1:0] dBus_cmd_halfPipe_regs_payload_size; - reg [3:0] _zz_125; + reg dBus_cmd_rValid; + wire dBus_cmd_halfPipe_fire; + reg dBus_cmd_rData_wr; + reg [31:0] dBus_cmd_rData_address; + reg [31:0] dBus_cmd_rData_data; + reg [1:0] dBus_cmd_rData_size; + reg [3:0] _zz_dBusWishbone_SEL; + wire when_DBusSimplePlugin_l189; `ifndef SYNTHESIS - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_8_string; - reg [31:0] _zz_9_string; - reg [31:0] _zz_10_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_11_string; - reg [71:0] _zz_12_string; - reg [71:0] _zz_13_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_14_string; - reg [39:0] _zz_15_string; - reg [39:0] _zz_16_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_17_string; - reg [23:0] _zz_18_string; - reg [23:0] _zz_19_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_20_string; - reg [63:0] _zz_21_string; - reg [63:0] _zz_22_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_23_string; - reg [95:0] _zz_24_string; - reg [95:0] _zz_25_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_26_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_27_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_28_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_29_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_31_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_33_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_34_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_35_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_36_string; - reg [39:0] _zz_40_string; - reg [31:0] _zz_41_string; - reg [71:0] _zz_42_string; - reg [39:0] _zz_43_string; - reg [23:0] _zz_44_string; - reg [63:0] _zz_45_string; - reg [95:0] _zz_46_string; - reg [95:0] _zz_76_string; - reg [63:0] _zz_77_string; - reg [23:0] _zz_78_string; - reg [39:0] _zz_79_string; - reg [71:0] _zz_80_string; - reg [31:0] _zz_81_string; - reg [39:0] _zz_82_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_7_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1016,885 +1046,820 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_131 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); - assign _zz_132 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_133 = ({decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_134 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_135 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_136 = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); - assign _zz_137 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_138 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_139 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); - assign _zz_140 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_141 = ((IBusSimplePlugin_iBusRsp_stages_1_input_valid && (! IBusSimplePlugin_mmu_joinCtx_refilling)) && (IBusSimplePlugin_mmu_joinCtx_exception || (! IBusSimplePlugin_mmu_joinCtx_allowExecute))); - assign _zz_142 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); - assign _zz_143 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); - assign _zz_144 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_145 = (1'b1 || (! 1'b1)); - assign _zz_146 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_147 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_148 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_149 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_150 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_151 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_152 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_153 = (! execute_arbitration_isStuckByOthers); - assign _zz_154 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_155 = ((_zz_106 && 1'b1) && (! 1'b0)); - assign _zz_156 = ((_zz_107 && 1'b1) && (! 1'b0)); - assign _zz_157 = ((_zz_108 && 1'b1) && (! 1'b0)); - assign _zz_158 = (! dBus_cmd_halfPipe_regs_valid); - assign _zz_159 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_160 = execute_INSTRUCTION[13]; - assign _zz_161 = _zz_71[23 : 23]; - assign _zz_162 = _zz_71[15 : 15]; - assign _zz_163 = _zz_71[12 : 12]; - assign _zz_164 = _zz_71[11 : 11]; - assign _zz_165 = _zz_71[10 : 10]; - assign _zz_166 = _zz_71[26 : 26]; - assign _zz_167 = _zz_71[14 : 14]; - assign _zz_168 = _zz_71[4 : 4]; - assign _zz_169 = _zz_71[2 : 2]; - assign _zz_170 = _zz_71[18 : 18]; - assign _zz_171 = _zz_71[9 : 9]; - assign _zz_172 = _zz_71[3 : 3]; - assign _zz_173 = (_zz_49 - 3'b001); - assign _zz_174 = {IBusSimplePlugin_fetchPc_inc,2'b00}; - assign _zz_175 = {29'd0, _zz_174}; - assign _zz_176 = (IBusSimplePlugin_pending_value + _zz_178); - assign _zz_177 = IBusSimplePlugin_pending_inc; - assign _zz_178 = {2'd0, _zz_177}; - assign _zz_179 = IBusSimplePlugin_pending_dec; - assign _zz_180 = {2'd0, _zz_179}; - assign _zz_181 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); - assign _zz_182 = {2'd0, _zz_181}; - assign _zz_183 = IBusSimplePlugin_pending_dec; - assign _zz_184 = {2'd0, _zz_183}; - assign _zz_185 = (memory_MEMORY_STORE ? 3'b110 : 3'b100); - assign _zz_186 = execute_SRC_LESS; - assign _zz_187 = 3'b100; - assign _zz_188 = execute_INSTRUCTION[19 : 15]; - assign _zz_189 = execute_INSTRUCTION[31 : 20]; - assign _zz_190 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_191 = ($signed(_zz_192) + $signed(_zz_195)); - assign _zz_192 = ($signed(_zz_193) + $signed(_zz_194)); - assign _zz_193 = execute_SRC1; - assign _zz_194 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_195 = (execute_SRC_USE_SUB_LESS ? _zz_196 : _zz_197); - assign _zz_196 = 32'h00000001; - assign _zz_197 = 32'h0; - assign _zz_198 = (_zz_199 >>> 1); - assign _zz_199 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; - assign _zz_200 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_201 = execute_INSTRUCTION[31 : 20]; - assign _zz_202 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_203 = (_zz_109 & (~ _zz_204)); - assign _zz_204 = (_zz_109 - 2'b01); - assign _zz_205 = (_zz_111 & (~ _zz_206)); - assign _zz_206 = (_zz_111 - 2'b01); - assign _zz_207 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_208 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_209 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_210 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_211 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_212 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_213 = 1'b1; - assign _zz_214 = 1'b1; - assign _zz_215 = {_zz_52,_zz_51}; - assign _zz_216 = 32'h0000107f; - assign _zz_217 = (decode_INSTRUCTION & 32'h0000207f); - assign _zz_218 = 32'h00002073; - assign _zz_219 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_220 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); - assign _zz_221 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_222) == 32'h00000003),{(_zz_223 == _zz_224),{_zz_225,{_zz_226,_zz_227}}}}}}; - assign _zz_222 = 32'h0000505f; - assign _zz_223 = (decode_INSTRUCTION & 32'h0000707b); - assign _zz_224 = 32'h00000063; - assign _zz_225 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_226 = ((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033); - assign _zz_227 = {((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013),{((decode_INSTRUCTION & _zz_228) == 32'h00005033),{(_zz_229 == _zz_230),{_zz_231,{_zz_232,_zz_233}}}}}}; - assign _zz_228 = 32'hbe00707f; - assign _zz_229 = (decode_INSTRUCTION & 32'hbe00707f); - assign _zz_230 = 32'h00000033; - assign _zz_231 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); - assign _zz_232 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); - assign _zz_233 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); - assign _zz_234 = 32'h10103050; - assign _zz_235 = (decode_INSTRUCTION & 32'h10103050); - assign _zz_236 = 32'h00000050; - assign _zz_237 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); - assign _zz_238 = {(_zz_243 == _zz_244),(_zz_245 == _zz_246)}; - assign _zz_239 = 2'b00; - assign _zz_240 = ({_zz_75,_zz_247} != 2'b00); - assign _zz_241 = (_zz_248 != 1'b0); - assign _zz_242 = {(_zz_249 != _zz_250),{_zz_251,{_zz_252,_zz_253}}}; - assign _zz_243 = (decode_INSTRUCTION & 32'h00001050); - assign _zz_244 = 32'h00001050; - assign _zz_245 = (decode_INSTRUCTION & 32'h00002050); - assign _zz_246 = 32'h00002050; - assign _zz_247 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); - assign _zz_248 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); - assign _zz_249 = ((decode_INSTRUCTION & _zz_254) == 32'h00005010); - assign _zz_250 = 1'b0; - assign _zz_251 = ({_zz_255,_zz_256} != 2'b00); - assign _zz_252 = ({_zz_257,_zz_258} != 2'b00); - assign _zz_253 = {(_zz_259 != _zz_260),{_zz_261,{_zz_262,_zz_263}}}; - assign _zz_254 = 32'h00007054; - assign _zz_255 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); - assign _zz_256 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00001010); - assign _zz_257 = ((decode_INSTRUCTION & _zz_264) == 32'h00000024); - assign _zz_258 = ((decode_INSTRUCTION & _zz_265) == 32'h00001010); - assign _zz_259 = ((decode_INSTRUCTION & _zz_266) == 32'h00001000); - assign _zz_260 = 1'b0; - assign _zz_261 = ((_zz_267 == _zz_268) != 1'b0); - assign _zz_262 = ({_zz_269,_zz_270} != 2'b00); - assign _zz_263 = {(_zz_271 != _zz_272),{_zz_273,{_zz_274,_zz_275}}}; - assign _zz_264 = 32'h00000064; - assign _zz_265 = 32'h00003054; - assign _zz_266 = 32'h00001000; - assign _zz_267 = (decode_INSTRUCTION & 32'h00003000); - assign _zz_268 = 32'h00002000; - assign _zz_269 = ((decode_INSTRUCTION & _zz_276) == 32'h00002000); - assign _zz_270 = ((decode_INSTRUCTION & _zz_277) == 32'h00001000); - assign _zz_271 = {(_zz_278 == _zz_279),(_zz_280 == _zz_281)}; - assign _zz_272 = 2'b00; - assign _zz_273 = ({_zz_282,{_zz_283,_zz_284}} != 3'b000); - assign _zz_274 = (_zz_285 != 1'b0); - assign _zz_275 = {(_zz_286 != _zz_287),{_zz_288,{_zz_289,_zz_290}}}; - assign _zz_276 = 32'h00002010; - assign _zz_277 = 32'h00005000; - assign _zz_278 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_279 = 32'h00000020; - assign _zz_280 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_281 = 32'h00000020; - assign _zz_282 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); - assign _zz_283 = ((decode_INSTRUCTION & _zz_291) == 32'h0); - assign _zz_284 = ((decode_INSTRUCTION & _zz_292) == 32'h00000040); - assign _zz_285 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); - assign _zz_286 = ((decode_INSTRUCTION & _zz_293) == 32'h00000010); - assign _zz_287 = 1'b0; - assign _zz_288 = (_zz_74 != 1'b0); - assign _zz_289 = ({_zz_294,_zz_295} != 6'h0); - assign _zz_290 = {(_zz_296 != _zz_297),{_zz_298,{_zz_299,_zz_300}}}; - assign _zz_291 = 32'h00000038; - assign _zz_292 = 32'h00103040; - assign _zz_293 = 32'h00000010; - assign _zz_294 = _zz_75; - assign _zz_295 = {(_zz_301 == _zz_302),{_zz_303,{_zz_304,_zz_305}}}; - assign _zz_296 = {_zz_73,(_zz_306 == _zz_307)}; - assign _zz_297 = 2'b00; - assign _zz_298 = ({_zz_73,_zz_308} != 2'b00); - assign _zz_299 = ({_zz_309,_zz_310} != 2'b00); - assign _zz_300 = {(_zz_311 != _zz_312),{_zz_313,{_zz_314,_zz_315}}}; - assign _zz_301 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_302 = 32'h00001010; - assign _zz_303 = ((decode_INSTRUCTION & _zz_316) == 32'h00002010); - assign _zz_304 = _zz_74; - assign _zz_305 = {_zz_317,_zz_318}; - assign _zz_306 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_307 = 32'h00000020; - assign _zz_308 = ((decode_INSTRUCTION & _zz_319) == 32'h0); - assign _zz_309 = (_zz_320 == _zz_321); - assign _zz_310 = (_zz_322 == _zz_323); - assign _zz_311 = (_zz_324 == _zz_325); - assign _zz_312 = 1'b0; - assign _zz_313 = ({_zz_326,_zz_327} != 4'b0000); - assign _zz_314 = (_zz_328 != _zz_329); - assign _zz_315 = {_zz_330,{_zz_331,_zz_332}}; - assign _zz_316 = 32'h00002010; - assign _zz_317 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_318 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); - assign _zz_319 = 32'h00000020; - assign _zz_320 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_321 = 32'h00006010; - assign _zz_322 = (decode_INSTRUCTION & 32'h00005014); - assign _zz_323 = 32'h00004010; - assign _zz_324 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_325 = 32'h00002010; - assign _zz_326 = ((decode_INSTRUCTION & _zz_333) == 32'h0); - assign _zz_327 = {(_zz_334 == _zz_335),{_zz_336,_zz_337}}; - assign _zz_328 = ((decode_INSTRUCTION & _zz_338) == 32'h0); - assign _zz_329 = 1'b0; - assign _zz_330 = ({_zz_339,{_zz_340,_zz_341}} != 3'b000); - assign _zz_331 = ({_zz_342,_zz_343} != 2'b00); - assign _zz_332 = ({_zz_344,_zz_345} != 2'b00); - assign _zz_333 = 32'h00000044; - assign _zz_334 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_335 = 32'h0; - assign _zz_336 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_337 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_338 = 32'h00000058; - assign _zz_339 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_340 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_341 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); - assign _zz_342 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_343 = _zz_72; - assign _zz_344 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_345 = _zz_72; - always @ (posedge clk) begin - if(_zz_213) begin - _zz_128 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_214) begin - _zz_129 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_39) begin + assign _zz_when = ({BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid} != 2'b00); + assign _zz_IBusSimplePlugin_jump_pcLoad_payload_1 = (_zz_IBusSimplePlugin_jump_pcLoad_payload & (~ _zz_IBusSimplePlugin_jump_pcLoad_payload_2)); + assign _zz_IBusSimplePlugin_jump_pcLoad_payload_2 = (_zz_IBusSimplePlugin_jump_pcLoad_payload - 2'b01); + assign _zz_IBusSimplePlugin_fetchPc_pc_1 = {IBusSimplePlugin_fetchPc_inc,2'b00}; + assign _zz_IBusSimplePlugin_fetchPc_pc = {29'd0, _zz_IBusSimplePlugin_fetchPc_pc_1}; + assign _zz_IBusSimplePlugin_pending_next = (IBusSimplePlugin_pending_value + _zz_IBusSimplePlugin_pending_next_1); + assign _zz_IBusSimplePlugin_pending_next_2 = IBusSimplePlugin_pending_inc; + assign _zz_IBusSimplePlugin_pending_next_1 = {2'd0, _zz_IBusSimplePlugin_pending_next_2}; + assign _zz_IBusSimplePlugin_pending_next_4 = IBusSimplePlugin_pending_dec; + assign _zz_IBusSimplePlugin_pending_next_3 = {2'd0, _zz_IBusSimplePlugin_pending_next_4}; + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1 = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000)); + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_1}; + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3 = IBusSimplePlugin_pending_dec; + assign _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2 = {2'd0, _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_3}; + assign _zz_DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1 = (_zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1 >>> 1); + assign _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1_1 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz__zz_execute_BranchPlugin_branch_src2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfe00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & 32'hfc00307f) == 32'h00001013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005033),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbe00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00000033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = ((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073); + assign _zz__zz_decode_ENV_CTRL_2 = 32'h10103050; + assign _zz__zz_decode_ENV_CTRL_2_1 = (decode_INSTRUCTION & 32'h10103050); + assign _zz__zz_decode_ENV_CTRL_2_2 = 32'h00000050; + assign _zz__zz_decode_ENV_CTRL_2_3 = ((decode_INSTRUCTION & 32'h10403050) == 32'h10000050); + assign _zz__zz_decode_ENV_CTRL_2_4 = {(_zz__zz_decode_ENV_CTRL_2_5 == _zz__zz_decode_ENV_CTRL_2_6),(_zz__zz_decode_ENV_CTRL_2_7 == _zz__zz_decode_ENV_CTRL_2_8)}; + assign _zz__zz_decode_ENV_CTRL_2_9 = 2'b00; + assign _zz__zz_decode_ENV_CTRL_2_10 = ({_zz_decode_ENV_CTRL_6,_zz__zz_decode_ENV_CTRL_2_11} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_12 = (_zz__zz_decode_ENV_CTRL_2_13 != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_14 = {(_zz__zz_decode_ENV_CTRL_2_15 != _zz__zz_decode_ENV_CTRL_2_17),{_zz__zz_decode_ENV_CTRL_2_18,{_zz__zz_decode_ENV_CTRL_2_21,_zz__zz_decode_ENV_CTRL_2_26}}}; + assign _zz__zz_decode_ENV_CTRL_2_5 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_ENV_CTRL_2_6 = 32'h00001050; + assign _zz__zz_decode_ENV_CTRL_2_7 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_ENV_CTRL_2_8 = 32'h00002050; + assign _zz__zz_decode_ENV_CTRL_2_11 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_ENV_CTRL_2_13 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_ENV_CTRL_2_15 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_16) == 32'h00005010); + assign _zz__zz_decode_ENV_CTRL_2_17 = 1'b0; + assign _zz__zz_decode_ENV_CTRL_2_18 = ({_zz__zz_decode_ENV_CTRL_2_19,_zz__zz_decode_ENV_CTRL_2_20} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_21 = ({_zz__zz_decode_ENV_CTRL_2_22,_zz__zz_decode_ENV_CTRL_2_24} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_26 = {(_zz__zz_decode_ENV_CTRL_2_27 != _zz__zz_decode_ENV_CTRL_2_29),{_zz__zz_decode_ENV_CTRL_2_30,{_zz__zz_decode_ENV_CTRL_2_33,_zz__zz_decode_ENV_CTRL_2_38}}}; + assign _zz__zz_decode_ENV_CTRL_2_16 = 32'h00007054; + assign _zz__zz_decode_ENV_CTRL_2_19 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_ENV_CTRL_2_20 = ((decode_INSTRUCTION & 32'h00007054) == 32'h00001010); + assign _zz__zz_decode_ENV_CTRL_2_22 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_23) == 32'h00000024); + assign _zz__zz_decode_ENV_CTRL_2_24 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_25) == 32'h00001010); + assign _zz__zz_decode_ENV_CTRL_2_27 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_28) == 32'h00001000); + assign _zz__zz_decode_ENV_CTRL_2_29 = 1'b0; + assign _zz__zz_decode_ENV_CTRL_2_30 = ((_zz__zz_decode_ENV_CTRL_2_31 == _zz__zz_decode_ENV_CTRL_2_32) != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_33 = ({_zz__zz_decode_ENV_CTRL_2_34,_zz__zz_decode_ENV_CTRL_2_36} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_38 = {(_zz__zz_decode_ENV_CTRL_2_39 != _zz__zz_decode_ENV_CTRL_2_44),{_zz__zz_decode_ENV_CTRL_2_45,{_zz__zz_decode_ENV_CTRL_2_51,_zz__zz_decode_ENV_CTRL_2_53}}}; + assign _zz__zz_decode_ENV_CTRL_2_23 = 32'h00000064; + assign _zz__zz_decode_ENV_CTRL_2_25 = 32'h00003054; + assign _zz__zz_decode_ENV_CTRL_2_28 = 32'h00001000; + assign _zz__zz_decode_ENV_CTRL_2_31 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_ENV_CTRL_2_32 = 32'h00002000; + assign _zz__zz_decode_ENV_CTRL_2_34 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_35) == 32'h00002000); + assign _zz__zz_decode_ENV_CTRL_2_36 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_37) == 32'h00001000); + assign _zz__zz_decode_ENV_CTRL_2_39 = {(_zz__zz_decode_ENV_CTRL_2_40 == _zz__zz_decode_ENV_CTRL_2_41),(_zz__zz_decode_ENV_CTRL_2_42 == _zz__zz_decode_ENV_CTRL_2_43)}; + assign _zz__zz_decode_ENV_CTRL_2_44 = 2'b00; + assign _zz__zz_decode_ENV_CTRL_2_45 = ({_zz__zz_decode_ENV_CTRL_2_46,{_zz__zz_decode_ENV_CTRL_2_47,_zz__zz_decode_ENV_CTRL_2_49}} != 3'b000); + assign _zz__zz_decode_ENV_CTRL_2_51 = (_zz__zz_decode_ENV_CTRL_2_52 != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_53 = {(_zz__zz_decode_ENV_CTRL_2_54 != _zz__zz_decode_ENV_CTRL_2_56),{_zz__zz_decode_ENV_CTRL_2_57,{_zz__zz_decode_ENV_CTRL_2_58,_zz__zz_decode_ENV_CTRL_2_69}}}; + assign _zz__zz_decode_ENV_CTRL_2_35 = 32'h00002010; + assign _zz__zz_decode_ENV_CTRL_2_37 = 32'h00005000; + assign _zz__zz_decode_ENV_CTRL_2_40 = (decode_INSTRUCTION & 32'h00000034); + assign _zz__zz_decode_ENV_CTRL_2_41 = 32'h00000020; + assign _zz__zz_decode_ENV_CTRL_2_42 = (decode_INSTRUCTION & 32'h00000064); + assign _zz__zz_decode_ENV_CTRL_2_43 = 32'h00000020; + assign _zz__zz_decode_ENV_CTRL_2_46 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000040); + assign _zz__zz_decode_ENV_CTRL_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_48) == 32'h0); + assign _zz__zz_decode_ENV_CTRL_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_50) == 32'h00000040); + assign _zz__zz_decode_ENV_CTRL_2_52 = ((decode_INSTRUCTION & 32'h00000020) == 32'h00000020); + assign _zz__zz_decode_ENV_CTRL_2_54 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_55) == 32'h00000010); + assign _zz__zz_decode_ENV_CTRL_2_56 = 1'b0; + assign _zz__zz_decode_ENV_CTRL_2_57 = (_zz_decode_ENV_CTRL_5 != 1'b0); + assign _zz__zz_decode_ENV_CTRL_2_58 = ({_zz__zz_decode_ENV_CTRL_2_59,_zz__zz_decode_ENV_CTRL_2_60} != 6'h0); + assign _zz__zz_decode_ENV_CTRL_2_69 = {(_zz__zz_decode_ENV_CTRL_2_70 != _zz__zz_decode_ENV_CTRL_2_73),{_zz__zz_decode_ENV_CTRL_2_74,{_zz__zz_decode_ENV_CTRL_2_77,_zz__zz_decode_ENV_CTRL_2_84}}}; + assign _zz__zz_decode_ENV_CTRL_2_48 = 32'h00000038; + assign _zz__zz_decode_ENV_CTRL_2_50 = 32'h00103040; + assign _zz__zz_decode_ENV_CTRL_2_55 = 32'h00000010; + assign _zz__zz_decode_ENV_CTRL_2_59 = _zz_decode_ENV_CTRL_6; + assign _zz__zz_decode_ENV_CTRL_2_60 = {(_zz__zz_decode_ENV_CTRL_2_61 == _zz__zz_decode_ENV_CTRL_2_62),{_zz__zz_decode_ENV_CTRL_2_63,{_zz__zz_decode_ENV_CTRL_2_65,_zz__zz_decode_ENV_CTRL_2_66}}}; + assign _zz__zz_decode_ENV_CTRL_2_70 = {_zz_decode_ENV_CTRL_4,(_zz__zz_decode_ENV_CTRL_2_71 == _zz__zz_decode_ENV_CTRL_2_72)}; + assign _zz__zz_decode_ENV_CTRL_2_73 = 2'b00; + assign _zz__zz_decode_ENV_CTRL_2_74 = ({_zz_decode_ENV_CTRL_4,_zz__zz_decode_ENV_CTRL_2_75} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_77 = ({_zz__zz_decode_ENV_CTRL_2_78,_zz__zz_decode_ENV_CTRL_2_81} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_84 = {(_zz__zz_decode_ENV_CTRL_2_85 != _zz__zz_decode_ENV_CTRL_2_88),{_zz__zz_decode_ENV_CTRL_2_89,{_zz__zz_decode_ENV_CTRL_2_97,_zz__zz_decode_ENV_CTRL_2_101}}}; + assign _zz__zz_decode_ENV_CTRL_2_61 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_ENV_CTRL_2_62 = 32'h00001010; + assign _zz__zz_decode_ENV_CTRL_2_63 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_64) == 32'h00002010); + assign _zz__zz_decode_ENV_CTRL_2_65 = _zz_decode_ENV_CTRL_5; + assign _zz__zz_decode_ENV_CTRL_2_66 = {_zz__zz_decode_ENV_CTRL_2_67,_zz__zz_decode_ENV_CTRL_2_68}; + assign _zz__zz_decode_ENV_CTRL_2_71 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_ENV_CTRL_2_72 = 32'h00000020; + assign _zz__zz_decode_ENV_CTRL_2_75 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_76) == 32'h0); + assign _zz__zz_decode_ENV_CTRL_2_78 = (_zz__zz_decode_ENV_CTRL_2_79 == _zz__zz_decode_ENV_CTRL_2_80); + assign _zz__zz_decode_ENV_CTRL_2_81 = (_zz__zz_decode_ENV_CTRL_2_82 == _zz__zz_decode_ENV_CTRL_2_83); + assign _zz__zz_decode_ENV_CTRL_2_85 = (_zz__zz_decode_ENV_CTRL_2_86 == _zz__zz_decode_ENV_CTRL_2_87); + assign _zz__zz_decode_ENV_CTRL_2_88 = 1'b0; + assign _zz__zz_decode_ENV_CTRL_2_89 = ({_zz__zz_decode_ENV_CTRL_2_90,_zz__zz_decode_ENV_CTRL_2_92} != 4'b0000); + assign _zz__zz_decode_ENV_CTRL_2_97 = (_zz__zz_decode_ENV_CTRL_2_98 != _zz__zz_decode_ENV_CTRL_2_100); + assign _zz__zz_decode_ENV_CTRL_2_101 = {_zz__zz_decode_ENV_CTRL_2_102,{_zz__zz_decode_ENV_CTRL_2_106,_zz__zz_decode_ENV_CTRL_2_109}}; + assign _zz__zz_decode_ENV_CTRL_2_64 = 32'h00002010; + assign _zz__zz_decode_ENV_CTRL_2_67 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_ENV_CTRL_2_68 = ((decode_INSTRUCTION & 32'h00000028) == 32'h0); + assign _zz__zz_decode_ENV_CTRL_2_76 = 32'h00000020; + assign _zz__zz_decode_ENV_CTRL_2_79 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_ENV_CTRL_2_80 = 32'h00006010; + assign _zz__zz_decode_ENV_CTRL_2_82 = (decode_INSTRUCTION & 32'h00005014); + assign _zz__zz_decode_ENV_CTRL_2_83 = 32'h00004010; + assign _zz__zz_decode_ENV_CTRL_2_86 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_ENV_CTRL_2_87 = 32'h00002010; + assign _zz__zz_decode_ENV_CTRL_2_90 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_91) == 32'h0); + assign _zz__zz_decode_ENV_CTRL_2_92 = {(_zz__zz_decode_ENV_CTRL_2_93 == _zz__zz_decode_ENV_CTRL_2_94),{_zz__zz_decode_ENV_CTRL_2_95,_zz__zz_decode_ENV_CTRL_2_96}}; + assign _zz__zz_decode_ENV_CTRL_2_98 = ((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2_99) == 32'h0); + assign _zz__zz_decode_ENV_CTRL_2_100 = 1'b0; + assign _zz__zz_decode_ENV_CTRL_2_102 = ({_zz__zz_decode_ENV_CTRL_2_103,{_zz__zz_decode_ENV_CTRL_2_104,_zz__zz_decode_ENV_CTRL_2_105}} != 3'b000); + assign _zz__zz_decode_ENV_CTRL_2_106 = ({_zz__zz_decode_ENV_CTRL_2_107,_zz__zz_decode_ENV_CTRL_2_108} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_109 = ({_zz__zz_decode_ENV_CTRL_2_110,_zz__zz_decode_ENV_CTRL_2_111} != 2'b00); + assign _zz__zz_decode_ENV_CTRL_2_91 = 32'h00000044; + assign _zz__zz_decode_ENV_CTRL_2_93 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_ENV_CTRL_2_94 = 32'h0; + assign _zz__zz_decode_ENV_CTRL_2_95 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_ENV_CTRL_2_96 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_ENV_CTRL_2_99 = 32'h00000058; + assign _zz__zz_decode_ENV_CTRL_2_103 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_ENV_CTRL_2_104 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_ENV_CTRL_2_105 = ((decode_INSTRUCTION & 32'h40004034) == 32'h40000030); + assign _zz__zz_decode_ENV_CTRL_2_107 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz__zz_decode_ENV_CTRL_2_108 = _zz_decode_ENV_CTRL_3; + assign _zz__zz_decode_ENV_CTRL_2_110 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_ENV_CTRL_2_111 = _zz_decode_ENV_CTRL_3; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end StreamFifoLowLatency IBusSimplePlugin_rspJoin_rspBuffer_c ( - .io_push_valid (iBus_rsp_valid ), //i - .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o - .io_push_payload_error (iBus_rsp_payload_error ), //i - .io_push_payload_inst (iBus_rsp_payload_inst[31:0] ), //i - .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o - .io_pop_ready (_zz_126 ), //i - .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o - .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst[31:0] ), //o - .io_flush (_zz_127 ), //i - .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o - .clk (clk ), //i - .reset (reset ) //i + .io_push_valid (iBus_rsp_valid ), //i + .io_push_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_push_ready ), //o + .io_push_payload_error (iBus_rsp_payload_error ), //i + .io_push_payload_inst (iBus_rsp_payload_inst ), //i + .io_pop_valid (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid ), //o + .io_pop_ready (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready ), //i + .io_pop_payload_error (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error ), //o + .io_pop_payload_inst (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst ), //o + .io_flush (1'b0 ), //i + .io_occupancy (IBusSimplePlugin_rspJoin_rspBuffer_c_io_occupancy ), //o + .clk (clk ), //i + .reset (reset ) //i ); - always @(*) begin - case(_zz_215) - 2'b00 : begin - _zz_130 = CsrPlugin_jumpInterface_payload; - end - 2'b01 : begin - _zz_130 = DBusSimplePlugin_redoBranch_payload; - end - default : begin - _zz_130 = BranchPlugin_jumpInterface_payload; - end - endcase - end - `ifndef SYNTHESIS always @(*) begin - case(_zz_1) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_1_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_1_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1_string = "ECALL"; - default : _zz_1_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_2_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_2_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2_string = "ECALL"; - default : _zz_2_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_3_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_3_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3_string = "ECALL"; - default : _zz_3_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_8) - `BranchCtrlEnum_defaultEncoding_INC : _zz_8_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_8_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_8_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_8_string = "JALR"; - default : _zz_8_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_9) - `BranchCtrlEnum_defaultEncoding_INC : _zz_9_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_9_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_9_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_9_string = "JALR"; - default : _zz_9_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_10) - `BranchCtrlEnum_defaultEncoding_INC : _zz_10_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_10_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_10_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_10_string = "JALR"; - default : _zz_10_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_11) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_11_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_11_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_11_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_11_string = "SRA_1 "; - default : _zz_11_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_12) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_12_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_12_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_12_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_12_string = "SRA_1 "; - default : _zz_12_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_14) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_14_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_14_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_14_string = "AND_1"; - default : _zz_14_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_15) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_15_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_15_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_15_string = "AND_1"; - default : _zz_15_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_16) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_16_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_16_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_16_string = "AND_1"; - default : _zz_16_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_17) - `Src2CtrlEnum_defaultEncoding_RS : _zz_17_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_17_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_17_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_17_string = "PC "; - default : _zz_17_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_18) - `Src2CtrlEnum_defaultEncoding_RS : _zz_18_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_18_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_18_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_18_string = "PC "; - default : _zz_18_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_19) - `Src2CtrlEnum_defaultEncoding_RS : _zz_19_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_19_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_19_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_19_string = "PC "; - default : _zz_19_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_20) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_20_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_20_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_20_string = "BITWISE "; - default : _zz_20_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_21) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_21_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_21_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_21_string = "BITWISE "; - default : _zz_21_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_22) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_22_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_22_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_22_string = "BITWISE "; - default : _zz_22_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_23) - `Src1CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_23_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_23_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_23_string = "URS1 "; - default : _zz_23_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_24) - `Src1CtrlEnum_defaultEncoding_RS : _zz_24_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_24_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_24_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_24_string = "URS1 "; - default : _zz_24_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_25) - `Src1CtrlEnum_defaultEncoding_RS : _zz_25_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_25_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_25_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_25_string = "URS1 "; - default : _zz_25_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_26) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_26_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_26_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_26_string = "ECALL"; - default : _zz_26_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_27) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_27_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_27_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_27_string = "ECALL"; - default : _zz_27_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_28) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_28_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_28_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_28_string = "ECALL"; - default : _zz_28_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_29) - `BranchCtrlEnum_defaultEncoding_INC : _zz_29_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_29_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_29_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_29_string = "JALR"; - default : _zz_29_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_31) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_31_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_31_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_31_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_31_string = "SRA_1 "; - default : _zz_31_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_33) - `Src2CtrlEnum_defaultEncoding_RS : _zz_33_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_33_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_33_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_33_string = "PC "; - default : _zz_33_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_34) - `Src1CtrlEnum_defaultEncoding_RS : _zz_34_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_34_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34_string = "URS1 "; - default : _zz_34_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_35) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_35_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_35_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_35_string = "BITWISE "; - default : _zz_35_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_36) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_36_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_36_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_36_string = "AND_1"; - default : _zz_36_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_40) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_40_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_40_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_40_string = "ECALL"; - default : _zz_40_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_41) - `BranchCtrlEnum_defaultEncoding_INC : _zz_41_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_41_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_41_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_41_string = "JALR"; - default : _zz_41_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_42) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_42_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_42_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_42_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_42_string = "SRA_1 "; - default : _zz_42_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_43) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_43_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_43_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_43_string = "AND_1"; - default : _zz_43_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_44) - `Src2CtrlEnum_defaultEncoding_RS : _zz_44_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_44_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_44_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_44_string = "PC "; - default : _zz_44_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_45) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_45_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_45_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_45_string = "BITWISE "; - default : _zz_45_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_46) - `Src1CtrlEnum_defaultEncoding_RS : _zz_46_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_46_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_46_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_46_string = "URS1 "; - default : _zz_46_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin - case(_zz_76) - `Src1CtrlEnum_defaultEncoding_RS : _zz_76_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_76_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_76_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_76_string = "URS1 "; - default : _zz_76_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_77) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_77_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_77_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_77_string = "BITWISE "; - default : _zz_77_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_78) - `Src2CtrlEnum_defaultEncoding_RS : _zz_78_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_78_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_78_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_78_string = "PC "; - default : _zz_78_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_79) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_79_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_79_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_79_string = "AND_1"; - default : _zz_79_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_80) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_80_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_80_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_80_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_80_string = "SRA_1 "; - default : _zz_80_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_81) - `BranchCtrlEnum_defaultEncoding_INC : _zz_81_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_81_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_81_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_81_string = "JALR"; - default : _zz_81_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_82) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_82_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_82_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_82_string = "ECALL"; - default : _zz_82_string = "?????"; + case(_zz_decode_ENV_CTRL_7) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_7_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_7_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_7_string = "ECALL"; + default : _zz_decode_ENV_CTRL_7_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end @@ -1902,9 +1867,9 @@ module VexRiscv ( assign memory_MEMORY_READ_DATA = dBus_rsp_data; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; - assign execute_BRANCH_DO = _zz_98; + assign execute_BRANCH_DO = _zz_execute_BRANCH_DO_1; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; - assign execute_REGFILE_WRITE_DATA = _zz_84; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; assign execute_MEMORY_ADDRESS_LOW = dBus_cmd_payload_address[1 : 0]; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); @@ -1913,146 +1878,123 @@ module VexRiscv ( assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); assign decode_RS2 = decode_RegFilePlugin_rs2Data; assign decode_RS1 = decode_RegFilePlugin_rs1Data; - assign _zz_1 = _zz_2; - assign _zz_3 = _zz_4; - assign decode_ENV_CTRL = _zz_5; - assign _zz_6 = _zz_7; - assign decode_IS_CSR = _zz_161[0]; - assign decode_BRANCH_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_SHIFT_CTRL = _zz_11; - assign _zz_12 = _zz_13; - assign decode_ALU_BITWISE_CTRL = _zz_14; - assign _zz_15 = _zz_16; - assign decode_SRC_LESS_UNSIGNED = _zz_162[0]; - assign decode_MEMORY_STORE = _zz_163[0]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_ENV_CTRL_2[23]; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_ENV_CTRL_2[15]; + assign decode_MEMORY_STORE = _zz_decode_ENV_CTRL_2[12]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_164[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_165[0]; - assign decode_SRC2_CTRL = _zz_17; - assign _zz_18 = _zz_19; - assign decode_ALU_CTRL = _zz_20; - assign _zz_21 = _zz_22; - assign decode_SRC1_CTRL = _zz_23; - assign _zz_24 = _zz_25; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_ENV_CTRL_2[11]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_ENV_CTRL_2[10]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_MEMORY_ENABLE = _zz_decode_ENV_CTRL_2[3]; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_166[0]; + assign decode_IS_EBREAK = _zz_decode_ENV_CTRL_2[26]; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_26; - assign execute_ENV_CTRL = _zz_27; - assign writeBack_ENV_CTRL = _zz_28; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; assign execute_PC = decode_to_execute_PC; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_CTRL = _zz_29; - assign decode_RS2_USE = _zz_167[0]; - assign decode_RS1_USE = _zz_168[0]; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_ENV_CTRL_2[14]; + assign decode_RS1_USE = _zz_decode_ENV_CTRL_2[4]; assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_30 = execute_REGFILE_WRITE_DATA; - if(_zz_131)begin - _zz_30 = _zz_91; + always @(*) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = execute_REGFILE_WRITE_DATA; + if(when_ShiftPlugins_l169) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = _zz_execute_to_memory_REGFILE_WRITE_DATA_1; end - if(_zz_132)begin - _zz_30 = execute_CsrPlugin_readData; + if(when_CsrPlugin_l1176) begin + _zz_execute_to_memory_REGFILE_WRITE_DATA = CsrPlugin_csrMapping_readDataSignal; end end - assign execute_SHIFT_CTRL = _zz_31; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_32 = execute_PC; - assign execute_SRC2_CTRL = _zz_33; - assign execute_SRC1_CTRL = _zz_34; - assign decode_SRC_USE_SUB_LESS = _zz_169[0]; - assign decode_SRC_ADD_ZERO = _zz_170[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_ENV_CTRL_2[2]; + assign decode_SRC_ADD_ZERO = _zz_decode_ENV_CTRL_2[18]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_35; - assign execute_SRC2 = _zz_90; - assign execute_SRC1 = _zz_85; - assign execute_ALU_BITWISE_CTRL = _zz_36; - assign _zz_37 = writeBack_INSTRUCTION; - assign _zz_38 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_39 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_39 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusSimplePlugin_iBusRsp_output_payload_rsp_inst); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_171[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_ENV_CTRL_2[9]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_216) == 32'h00001073),{(_zz_217 == _zz_218),{_zz_219,{_zz_220,_zz_221}}}}}}} != 20'h0); + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 20'h0); assign writeBack_MEMORY_STORE = memory_to_writeBack_MEMORY_STORE; - always @ (*) begin - _zz_47 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_47 = writeBack_DBusSimplePlugin_rspFormated; + always @(*) begin + _zz_lastStageRegFileWrite_payload_data = writeBack_REGFILE_WRITE_DATA; + if(when_DBusSimplePlugin_l558) begin + _zz_lastStageRegFileWrite_payload_data = writeBack_DBusSimplePlugin_rspFormated; end end assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_READ_DATA = memory_to_writeBack_MEMORY_READ_DATA; - assign memory_MMU_FAULT = execute_to_memory_MMU_FAULT; - assign memory_MMU_RSP2_physicalAddress = execute_to_memory_MMU_RSP2_physicalAddress; - assign memory_MMU_RSP2_isIoAccess = execute_to_memory_MMU_RSP2_isIoAccess; - assign memory_MMU_RSP2_isPaging = execute_to_memory_MMU_RSP2_isPaging; - assign memory_MMU_RSP2_allowRead = execute_to_memory_MMU_RSP2_allowRead; - assign memory_MMU_RSP2_allowWrite = execute_to_memory_MMU_RSP2_allowWrite; - assign memory_MMU_RSP2_allowExecute = execute_to_memory_MMU_RSP2_allowExecute; - assign memory_MMU_RSP2_exception = execute_to_memory_MMU_RSP2_exception; - assign memory_MMU_RSP2_refilling = execute_to_memory_MMU_RSP2_refilling; - assign memory_MMU_RSP2_bypassTranslation = execute_to_memory_MMU_RSP2_bypassTranslation; - assign memory_PC = execute_to_memory_PC; assign memory_ALIGNEMENT_FAULT = execute_to_memory_ALIGNEMENT_FAULT; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; assign memory_MEMORY_STORE = execute_to_memory_MEMORY_STORE; assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; - assign execute_MMU_FAULT = ((execute_MMU_RSP2_exception || ((! execute_MMU_RSP2_allowWrite) && execute_MEMORY_STORE)) || ((! execute_MMU_RSP2_allowRead) && (! execute_MEMORY_STORE))); - assign execute_MMU_RSP2_physicalAddress = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - assign execute_MMU_RSP2_isIoAccess = DBusSimplePlugin_mmuBus_rsp_isIoAccess; - assign execute_MMU_RSP2_isPaging = DBusSimplePlugin_mmuBus_rsp_isPaging; - assign execute_MMU_RSP2_allowRead = DBusSimplePlugin_mmuBus_rsp_allowRead; - assign execute_MMU_RSP2_allowWrite = DBusSimplePlugin_mmuBus_rsp_allowWrite; - assign execute_MMU_RSP2_allowExecute = DBusSimplePlugin_mmuBus_rsp_allowExecute; - assign execute_MMU_RSP2_exception = DBusSimplePlugin_mmuBus_rsp_exception; - assign execute_MMU_RSP2_refilling = DBusSimplePlugin_mmuBus_rsp_refilling; - assign execute_MMU_RSP2_bypassTranslation = DBusSimplePlugin_mmuBus_rsp_bypassTranslation; assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_RS2 = decode_to_execute_RS2; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_ALIGNEMENT_FAULT = (((dBus_cmd_payload_size == 2'b10) && (dBus_cmd_payload_address[1 : 0] != 2'b00)) || ((dBus_cmd_payload_size == 2'b01) && (dBus_cmd_payload_address[0 : 0] != 1'b0))); - assign decode_MEMORY_ENABLE = _zz_172[0]; - always @ (*) begin - _zz_48 = memory_FORMAL_PC_NEXT; - if(DBusSimplePlugin_redoBranch_valid)begin - _zz_48 = DBusSimplePlugin_redoBranch_payload; - end - if(BranchPlugin_jumpInterface_valid)begin - _zz_48 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end @@ -2060,12 +2002,9 @@ module VexRiscv ( assign decode_INSTRUCTION = IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusSimplePlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin - decode_arbitration_haltItself = 1'b1; - end - case(_zz_116) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2074,146 +2013,137 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_92 || _zz_93)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_133)begin + if(decodeExceptionPort_valid) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(_zz_133)begin + if(decodeExceptionPort_valid) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)))begin + if(when_DBusSimplePlugin_l426) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_131)begin - if((! execute_LightShifterPlugin_done))begin + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l184) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_132)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if(_zz_134)begin + if(when_DebugPlugin_l284) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_134)begin - if(_zz_135)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushIt = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_134)begin - if(_zz_135)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushNext = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)))begin + if(when_DBusSimplePlugin_l479) begin memory_arbitration_haltItself = 1'b1; end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(_zz_136)begin + if(_zz_when) begin memory_arbitration_removeIt = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end - always @ (*) begin - memory_arbitration_flushIt = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushIt = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin memory_arbitration_flushNext = 1'b0; - if(DBusSimplePlugin_redoBranch_valid)begin - memory_arbitration_flushNext = 1'b1; - end - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin memory_arbitration_flushNext = 1'b1; end - if(_zz_136)begin + if(_zz_when) begin memory_arbitration_flushNext = 1'b1; end end assign writeBack_arbitration_haltItself = 1'b0; assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end assign writeBack_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(_zz_137)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_138)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -2222,65 +2152,67 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusSimplePlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_137)begin + if(when_CsrPlugin_l1019) begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_138)begin + if(when_CsrPlugin_l1064) begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_134)begin - if(_zz_135)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin IBusSimplePlugin_fetcherHalt = 1'b1; end end - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin IBusSimplePlugin_fetcherHalt = 1'b1; end - if(_zz_139)begin + if(when_DebugPlugin_l300) begin IBusSimplePlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusSimplePlugin_incomingInstruction = 1'b0; - if(IBusSimplePlugin_iBusRsp_stages_1_input_valid)begin + if(IBusSimplePlugin_iBusRsp_stages_1_input_valid) begin IBusSimplePlugin_incomingInstruction = 1'b1; end - if(IBusSimplePlugin_injector_decodeInput_valid)begin + if(IBusSimplePlugin_injector_decodeInput_valid) begin IBusSimplePlugin_incomingInstruction = 1'b1; end end + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; assign CsrPlugin_inWfi = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin CsrPlugin_thirdPartyWake = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_137)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_138)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_137)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_138)begin - case(_zz_140) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -2290,142 +2222,132 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_forceMachineWire = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + if(when_DebugPlugin_l316) begin CsrPlugin_allowInterrupts = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_allowException = 1'b0; end end + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + assign IBusSimplePlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); - assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusSimplePlugin_redoBranch_valid}} != 3'b000); - assign _zz_49 = {BranchPlugin_jumpInterface_valid,{DBusSimplePlugin_redoBranch_valid,CsrPlugin_jumpInterface_valid}}; - assign _zz_50 = (_zz_49 & (~ _zz_173)); - assign _zz_51 = _zz_50[1]; - assign _zz_52 = _zz_50[2]; - assign IBusSimplePlugin_jump_pcLoad_payload = _zz_130; - always @ (*) begin + assign IBusSimplePlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid} != 2'b00); + assign _zz_IBusSimplePlugin_jump_pcLoad_payload = {BranchPlugin_jumpInterface_valid,CsrPlugin_jumpInterface_valid}; + assign IBusSimplePlugin_jump_pcLoad_payload = (_zz_IBusSimplePlugin_jump_pcLoad_payload_1[0] ? CsrPlugin_jumpInterface_payload : BranchPlugin_jumpInterface_payload); + always @(*) begin IBusSimplePlugin_fetchPc_correction = 1'b0; - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_correction = 1'b1; - end - if(IBusSimplePlugin_jump_pcLoad_valid)begin + if(IBusSimplePlugin_jump_pcLoad_valid) begin IBusSimplePlugin_fetchPc_correction = 1'b1; end end + assign IBusSimplePlugin_fetchPc_output_fire = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready); assign IBusSimplePlugin_fetchPc_corrected = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusSimplePlugin_iBusRsp_stages_1_input_ready)begin + if(IBusSimplePlugin_iBusRsp_stages_1_input_ready) begin IBusSimplePlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_175); - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_fetchPc_redo_payload; - end - if(IBusSimplePlugin_jump_pcLoad_valid)begin + assign when_Fetcher_l131 = (IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate); + assign IBusSimplePlugin_fetchPc_output_fire_1 = (IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready); + always @(*) begin + IBusSimplePlugin_fetchPc_pc = (IBusSimplePlugin_fetchPc_pcReg + _zz_IBusSimplePlugin_fetchPc_pc); + if(IBusSimplePlugin_jump_pcLoad_valid) begin IBusSimplePlugin_fetchPc_pc = IBusSimplePlugin_jump_pcLoad_payload; end IBusSimplePlugin_fetchPc_pc[0] = 1'b0; IBusSimplePlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusSimplePlugin_fetchPc_flushed = 1'b0; - if(IBusSimplePlugin_fetchPc_redo_valid)begin - IBusSimplePlugin_fetchPc_flushed = 1'b1; - end - if(IBusSimplePlugin_jump_pcLoad_valid)begin + if(IBusSimplePlugin_jump_pcLoad_valid) begin IBusSimplePlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)); assign IBusSimplePlugin_fetchPc_output_valid = ((! IBusSimplePlugin_fetcherHalt) && IBusSimplePlugin_fetchPc_booted); assign IBusSimplePlugin_fetchPc_output_payload = IBusSimplePlugin_fetchPc_pc; - always @ (*) begin - IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_1_input_valid && IBusSimplePlugin_mmu_joinCtx_refilling))begin - IBusSimplePlugin_iBusRsp_redoFetch = 1'b1; - end - end - + assign IBusSimplePlugin_iBusRsp_redoFetch = 1'b0; assign IBusSimplePlugin_iBusRsp_stages_0_input_valid = IBusSimplePlugin_fetchPc_output_valid; assign IBusSimplePlugin_fetchPc_output_ready = IBusSimplePlugin_iBusRsp_stages_0_input_ready; assign IBusSimplePlugin_iBusRsp_stages_0_input_payload = IBusSimplePlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - if((IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))))begin + if(when_IBusSimplePlugin_l304) begin IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; end - if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin - if(IBusSimplePlugin_mmuBus_rsp_refilling)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b1; - end - if(IBusSimplePlugin_mmuBus_rsp_exception)begin - IBusSimplePlugin_iBusRsp_stages_0_halt = 1'b0; - end - end end - assign _zz_53 = (! IBusSimplePlugin_iBusRsp_stages_0_halt); - assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_53); - assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_53); + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready = (! IBusSimplePlugin_iBusRsp_stages_0_halt); + assign IBusSimplePlugin_iBusRsp_stages_0_input_ready = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); + assign IBusSimplePlugin_iBusRsp_stages_0_output_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_0_input_ready); assign IBusSimplePlugin_iBusRsp_stages_0_output_payload = IBusSimplePlugin_iBusRsp_stages_0_input_payload; assign IBusSimplePlugin_iBusRsp_stages_1_halt = 1'b0; - assign _zz_54 = (! IBusSimplePlugin_iBusRsp_stages_1_halt); - assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_54); - assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_54); + assign _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready = (! IBusSimplePlugin_iBusRsp_stages_1_halt); + assign IBusSimplePlugin_iBusRsp_stages_1_input_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_ready && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign IBusSimplePlugin_iBusRsp_stages_1_output_valid = (IBusSimplePlugin_iBusRsp_stages_1_input_valid && _zz_IBusSimplePlugin_iBusRsp_stages_1_input_ready); assign IBusSimplePlugin_iBusRsp_stages_1_output_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; - assign IBusSimplePlugin_fetchPc_redo_valid = IBusSimplePlugin_iBusRsp_redoFetch; - assign IBusSimplePlugin_fetchPc_redo_payload = IBusSimplePlugin_iBusRsp_stages_1_input_payload; assign IBusSimplePlugin_iBusRsp_flush = (IBusSimplePlugin_externalFlush || IBusSimplePlugin_iBusRsp_redoFetch); - assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_55; - assign _zz_55 = ((1'b0 && (! _zz_56)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); - assign _zz_56 = _zz_57; - assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_56; + assign IBusSimplePlugin_iBusRsp_stages_0_output_ready = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1)) || IBusSimplePlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2; + assign IBusSimplePlugin_iBusRsp_stages_1_input_valid = _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_1; assign IBusSimplePlugin_iBusRsp_stages_1_input_payload = IBusSimplePlugin_fetchPc_pcReg; - always @ (*) begin + always @(*) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b1; - if(IBusSimplePlugin_injector_decodeInput_valid)begin + if(IBusSimplePlugin_injector_decodeInput_valid) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b0; end - if((! IBusSimplePlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusSimplePlugin_iBusRsp_readyForError = 1'b0; end end assign IBusSimplePlugin_iBusRsp_output_ready = ((1'b0 && (! IBusSimplePlugin_injector_decodeInput_valid)) || IBusSimplePlugin_injector_decodeInput_ready); - assign IBusSimplePlugin_injector_decodeInput_valid = _zz_58; - assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_59; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_60; - assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_61; - assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_62; + assign IBusSimplePlugin_injector_decodeInput_valid = _zz_IBusSimplePlugin_injector_decodeInput_valid; + assign IBusSimplePlugin_injector_decodeInput_payload_pc = _zz_IBusSimplePlugin_injector_decodeInput_payload_pc; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_error = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error; + assign IBusSimplePlugin_injector_decodeInput_payload_rsp_inst = _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst; + assign IBusSimplePlugin_injector_decodeInput_payload_isRvc = _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc; + assign when_Fetcher_l320 = (! IBusSimplePlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusSimplePlugin_injector_decodeInput_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusSimplePlugin_pcValids_0 = IBusSimplePlugin_injector_nextPcCalc_valids_1; assign IBusSimplePlugin_pcValids_1 = IBusSimplePlugin_injector_nextPcCalc_valids_2; assign IBusSimplePlugin_pcValids_2 = IBusSimplePlugin_injector_nextPcCalc_valids_3; assign IBusSimplePlugin_pcValids_3 = IBusSimplePlugin_injector_nextPcCalc_valids_4; assign IBusSimplePlugin_injector_decodeInput_ready = (! decode_arbitration_isStuck); - always @ (*) begin + always @(*) begin decode_arbitration_isValid = IBusSimplePlugin_injector_decodeInput_valid; - case(_zz_116) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -2440,169 +2362,118 @@ module VexRiscv ( assign iBus_cmd_valid = IBusSimplePlugin_cmd_valid; assign IBusSimplePlugin_cmd_ready = iBus_cmd_ready; assign iBus_cmd_payload_pc = IBusSimplePlugin_cmd_payload_pc; - assign IBusSimplePlugin_pending_next = (_zz_176 - _zz_180); + assign IBusSimplePlugin_pending_next = (_zz_IBusSimplePlugin_pending_next - _zz_IBusSimplePlugin_pending_next_3); assign IBusSimplePlugin_cmdFork_canEmit = (IBusSimplePlugin_iBusRsp_stages_0_output_ready && (IBusSimplePlugin_pending_value != 3'b111)); - always @ (*) begin - IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); - if(IBusSimplePlugin_iBusRsp_stages_0_input_valid)begin - if(IBusSimplePlugin_mmuBus_rsp_refilling)begin - IBusSimplePlugin_cmd_valid = 1'b0; - end - if(IBusSimplePlugin_mmuBus_rsp_exception)begin - IBusSimplePlugin_cmd_valid = 1'b0; - end - end - end - - assign IBusSimplePlugin_pending_inc = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); - assign IBusSimplePlugin_mmuBus_cmd_0_isValid = IBusSimplePlugin_iBusRsp_stages_0_input_valid; - assign IBusSimplePlugin_mmuBus_cmd_0_virtualAddress = IBusSimplePlugin_iBusRsp_stages_0_input_payload; - assign IBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign IBusSimplePlugin_mmuBus_end = ((IBusSimplePlugin_iBusRsp_stages_0_output_valid && IBusSimplePlugin_iBusRsp_stages_0_output_ready) || IBusSimplePlugin_externalFlush); - assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_mmuBus_rsp_physicalAddress[31 : 2],2'b00}; + assign when_IBusSimplePlugin_l304 = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && ((! IBusSimplePlugin_cmdFork_canEmit) || (! IBusSimplePlugin_cmd_ready))); + assign IBusSimplePlugin_cmd_valid = (IBusSimplePlugin_iBusRsp_stages_0_input_valid && IBusSimplePlugin_cmdFork_canEmit); + assign IBusSimplePlugin_cmd_fire = (IBusSimplePlugin_cmd_valid && IBusSimplePlugin_cmd_ready); + assign IBusSimplePlugin_pending_inc = IBusSimplePlugin_cmd_fire; + assign IBusSimplePlugin_cmd_payload_pc = {IBusSimplePlugin_iBusRsp_stages_0_input_payload[31 : 2],2'b00}; assign IBusSimplePlugin_rspJoin_rspBuffer_flush = ((IBusSimplePlugin_rspJoin_rspBuffer_discardCounter != 3'b000) || IBusSimplePlugin_iBusRsp_flush); assign IBusSimplePlugin_rspJoin_rspBuffer_output_valid = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter == 3'b000)); assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_error; assign IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_payload_inst; - assign _zz_126 = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); - assign IBusSimplePlugin_pending_dec = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && _zz_126); + assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready = (IBusSimplePlugin_rspJoin_rspBuffer_output_ready || IBusSimplePlugin_rspJoin_rspBuffer_flush); + assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire = (IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_valid && IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_ready); + assign IBusSimplePlugin_pending_dec = IBusSimplePlugin_rspJoin_rspBuffer_c_io_pop_fire; assign IBusSimplePlugin_rspJoin_fetchRsp_pc = IBusSimplePlugin_iBusRsp_stages_1_output_payload; - always @ (*) begin + always @(*) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_error; - if((! IBusSimplePlugin_rspJoin_rspBuffer_output_valid))begin + if(when_IBusSimplePlugin_l375) begin IBusSimplePlugin_rspJoin_fetchRsp_rsp_error = 1'b0; end end assign IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst = IBusSimplePlugin_rspJoin_rspBuffer_output_payload_inst; - always @ (*) begin - IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; - if(_zz_141)begin - IBusSimplePlugin_rspJoin_exceptionDetected = 1'b1; - end - end - + assign when_IBusSimplePlugin_l375 = (! IBusSimplePlugin_rspJoin_rspBuffer_output_valid); + assign IBusSimplePlugin_rspJoin_exceptionDetected = 1'b0; assign IBusSimplePlugin_rspJoin_join_valid = (IBusSimplePlugin_iBusRsp_stages_1_output_valid && IBusSimplePlugin_rspJoin_rspBuffer_output_valid); assign IBusSimplePlugin_rspJoin_join_payload_pc = IBusSimplePlugin_rspJoin_fetchRsp_pc; assign IBusSimplePlugin_rspJoin_join_payload_rsp_error = IBusSimplePlugin_rspJoin_fetchRsp_rsp_error; assign IBusSimplePlugin_rspJoin_join_payload_rsp_inst = IBusSimplePlugin_rspJoin_fetchRsp_rsp_inst; assign IBusSimplePlugin_rspJoin_join_payload_isRvc = IBusSimplePlugin_rspJoin_fetchRsp_isRvc; - assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready) : IBusSimplePlugin_rspJoin_join_ready); - assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); - assign _zz_63 = (! IBusSimplePlugin_rspJoin_exceptionDetected); - assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_63); - assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_63); + assign IBusSimplePlugin_rspJoin_join_fire = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_iBusRsp_stages_1_output_ready = (IBusSimplePlugin_iBusRsp_stages_1_output_valid ? IBusSimplePlugin_rspJoin_join_fire : IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_join_fire_1 = (IBusSimplePlugin_rspJoin_join_valid && IBusSimplePlugin_rspJoin_join_ready); + assign IBusSimplePlugin_rspJoin_rspBuffer_output_ready = IBusSimplePlugin_rspJoin_join_fire_1; + assign _zz_IBusSimplePlugin_iBusRsp_output_valid = (! IBusSimplePlugin_rspJoin_exceptionDetected); + assign IBusSimplePlugin_rspJoin_join_ready = (IBusSimplePlugin_iBusRsp_output_ready && _zz_IBusSimplePlugin_iBusRsp_output_valid); + assign IBusSimplePlugin_iBusRsp_output_valid = (IBusSimplePlugin_rspJoin_join_valid && _zz_IBusSimplePlugin_iBusRsp_output_valid); assign IBusSimplePlugin_iBusRsp_output_payload_pc = IBusSimplePlugin_rspJoin_join_payload_pc; assign IBusSimplePlugin_iBusRsp_output_payload_rsp_error = IBusSimplePlugin_rspJoin_join_payload_rsp_error; assign IBusSimplePlugin_iBusRsp_output_payload_rsp_inst = IBusSimplePlugin_rspJoin_join_payload_rsp_inst; assign IBusSimplePlugin_iBusRsp_output_payload_isRvc = IBusSimplePlugin_rspJoin_join_payload_isRvc; - always @ (*) begin - IBusSimplePlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_141)begin - IBusSimplePlugin_decodeExceptionPort_payload_code = 4'b1100; - end - end - - assign IBusSimplePlugin_decodeExceptionPort_payload_badAddr = {IBusSimplePlugin_rspJoin_join_payload_pc[31 : 2],2'b00}; - assign IBusSimplePlugin_decodeExceptionPort_valid = (IBusSimplePlugin_rspJoin_exceptionDetected && IBusSimplePlugin_iBusRsp_readyForError); - assign _zz_64 = 1'b0; - always @ (*) begin + assign _zz_dBus_cmd_valid = 1'b0; + always @(*) begin execute_DBusSimplePlugin_skipCmd = 1'b0; - if(execute_ALIGNEMENT_FAULT)begin - execute_DBusSimplePlugin_skipCmd = 1'b1; - end - if((execute_MMU_FAULT || execute_MMU_RSP2_refilling))begin + if(execute_ALIGNEMENT_FAULT) begin execute_DBusSimplePlugin_skipCmd = 1'b1; end end - assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_64)); + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); assign dBus_cmd_payload_wr = execute_MEMORY_STORE; assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; - always @ (*) begin + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_65 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_dBus_cmd_payload_data = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_65 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_dBus_cmd_payload_data = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_65 = execute_RS2[31 : 0]; + _zz_dBus_cmd_payload_data = execute_RS2[31 : 0]; end endcase end - assign dBus_cmd_payload_data = _zz_65; - always @ (*) begin + assign dBus_cmd_payload_data = _zz_dBus_cmd_payload_data; + assign when_DBusSimplePlugin_l426 = ((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! _zz_dBus_cmd_valid)); + always @(*) begin case(dBus_cmd_payload_size) 2'b00 : begin - _zz_66 = 4'b0001; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0001; end 2'b01 : begin - _zz_66 = 4'b0011; + _zz_execute_DBusSimplePlugin_formalMask = 4'b0011; end default : begin - _zz_66 = 4'b1111; + _zz_execute_DBusSimplePlugin_formalMask = 4'b1111; end endcase end - assign execute_DBusSimplePlugin_formalMask = (_zz_66 <<< dBus_cmd_payload_address[1 : 0]); - assign DBusSimplePlugin_mmuBus_cmd_0_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign DBusSimplePlugin_mmuBus_cmd_0_isStuck = execute_arbitration_isStuck; - assign DBusSimplePlugin_mmuBus_cmd_0_virtualAddress = execute_SRC_ADD; - assign DBusSimplePlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; - assign DBusSimplePlugin_mmuBus_end = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); - assign dBus_cmd_payload_address = DBusSimplePlugin_mmuBus_rsp_physicalAddress; - always @ (*) begin + assign execute_DBusSimplePlugin_formalMask = (_zz_execute_DBusSimplePlugin_formalMask <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign when_DBusSimplePlugin_l479 = (((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! memory_MEMORY_STORE)) && ((! dBus_rsp_ready) || 1'b0)); + always @(*) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - if(_zz_142)begin + if(when_DBusSimplePlugin_l486) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_ALIGNEMENT_FAULT)begin + if(memory_ALIGNEMENT_FAULT) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; end - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; - end else begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; - end - end - if(_zz_143)begin + if(when_DBusSimplePlugin_l512) begin DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; end end - always @ (*) begin + always @(*) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'bxxxx; - if(_zz_142)begin + if(when_DBusSimplePlugin_l486) begin DBusSimplePlugin_memoryExceptionPort_payload_code = 4'b0101; end - if(memory_ALIGNEMENT_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_185}; - end - if(! memory_MMU_RSP2_refilling) begin - if(memory_MMU_FAULT)begin - DBusSimplePlugin_memoryExceptionPort_payload_code = (memory_MEMORY_STORE ? 4'b1111 : 4'b1101); - end + if(memory_ALIGNEMENT_FAULT) begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_DBusSimplePlugin_memoryExceptionPort_payload_code}; end end assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = memory_REGFILE_WRITE_DATA; - always @ (*) begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - if(memory_MMU_RSP2_refilling)begin - DBusSimplePlugin_redoBranch_valid = 1'b1; - end - if(_zz_143)begin - DBusSimplePlugin_redoBranch_valid = 1'b0; - end - end - - assign DBusSimplePlugin_redoBranch_payload = memory_PC; - always @ (*) begin + assign when_DBusSimplePlugin_l486 = ((dBus_rsp_ready && dBus_rsp_error) && (! memory_MEMORY_STORE)); + assign when_DBusSimplePlugin_l512 = (! ((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (1'b1 || (! memory_arbitration_isStuckByOthers)))); + always @(*) begin writeBack_DBusSimplePlugin_rspShifted = writeBack_MEMORY_READ_DATA; case(writeBack_MEMORY_ADDRESS_LOW) 2'b01 : begin @@ -2619,63 +2490,64 @@ module VexRiscv ( endcase end - assign _zz_67 = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_68[31] = _zz_67; - _zz_68[30] = _zz_67; - _zz_68[29] = _zz_67; - _zz_68[28] = _zz_67; - _zz_68[27] = _zz_67; - _zz_68[26] = _zz_67; - _zz_68[25] = _zz_67; - _zz_68[24] = _zz_67; - _zz_68[23] = _zz_67; - _zz_68[22] = _zz_67; - _zz_68[21] = _zz_67; - _zz_68[20] = _zz_67; - _zz_68[19] = _zz_67; - _zz_68[18] = _zz_67; - _zz_68[17] = _zz_67; - _zz_68[16] = _zz_67; - _zz_68[15] = _zz_67; - _zz_68[14] = _zz_67; - _zz_68[13] = _zz_67; - _zz_68[12] = _zz_67; - _zz_68[11] = _zz_67; - _zz_68[10] = _zz_67; - _zz_68[9] = _zz_67; - _zz_68[8] = _zz_67; - _zz_68[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; - end - - assign _zz_69 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_70[31] = _zz_69; - _zz_70[30] = _zz_69; - _zz_70[29] = _zz_69; - _zz_70[28] = _zz_69; - _zz_70[27] = _zz_69; - _zz_70[26] = _zz_69; - _zz_70[25] = _zz_69; - _zz_70[24] = _zz_69; - _zz_70[23] = _zz_69; - _zz_70[22] = _zz_69; - _zz_70[21] = _zz_69; - _zz_70[20] = _zz_69; - _zz_70[19] = _zz_69; - _zz_70[18] = _zz_69; - _zz_70[17] = _zz_69; - _zz_70[16] = _zz_69; - _zz_70[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_159) + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusSimplePlugin_rspFormated = (writeBack_DBusSimplePlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_1[31] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[30] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[29] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[28] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[27] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[26] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[25] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[24] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[23] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[22] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[21] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[20] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[19] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[18] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[17] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[16] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[15] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[14] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[13] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[12] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[11] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[10] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[9] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[8] = _zz_writeBack_DBusSimplePlugin_rspFormated; + _zz_writeBack_DBusSimplePlugin_rspFormated_1[7 : 0] = writeBack_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_writeBack_DBusSimplePlugin_rspFormated_2 = (writeBack_DBusSimplePlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusSimplePlugin_rspFormated_3[31] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[30] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[29] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[28] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[27] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[26] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[25] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[24] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[23] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[22] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[21] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[20] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[19] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[18] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[17] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[16] = _zz_writeBack_DBusSimplePlugin_rspFormated_2; + _zz_writeBack_DBusSimplePlugin_rspFormated_3[15 : 0] = writeBack_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_68; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusSimplePlugin_rspFormated = _zz_70; + writeBack_DBusSimplePlugin_rspFormated = _zz_writeBack_DBusSimplePlugin_rspFormated_3; end default : begin writeBack_DBusSimplePlugin_rspFormated = writeBack_DBusSimplePlugin_rspShifted; @@ -2683,77 +2555,61 @@ module VexRiscv ( endcase end - assign IBusSimplePlugin_mmuBus_rsp_physicalAddress = IBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign IBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign IBusSimplePlugin_mmuBus_rsp_isIoAccess = IBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign IBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign IBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign IBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign IBusSimplePlugin_mmuBus_busy = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_physicalAddress = DBusSimplePlugin_mmuBus_cmd_0_virtualAddress; - assign DBusSimplePlugin_mmuBus_rsp_allowRead = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowWrite = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_allowExecute = 1'b1; - assign DBusSimplePlugin_mmuBus_rsp_isIoAccess = DBusSimplePlugin_mmuBus_rsp_physicalAddress[31]; - assign DBusSimplePlugin_mmuBus_rsp_isPaging = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_exception = 1'b0; - assign DBusSimplePlugin_mmuBus_rsp_refilling = 1'b0; - assign DBusSimplePlugin_mmuBus_busy = 1'b0; - assign _zz_72 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_73 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_74 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); - assign _zz_75 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_71 = {(((decode_INSTRUCTION & _zz_234) == 32'h00100050) != 1'b0),{((_zz_235 == _zz_236) != 1'b0),{(_zz_237 != 1'b0),{(_zz_238 != _zz_239),{_zz_240,{_zz_241,_zz_242}}}}}}; - assign _zz_76 = _zz_71[1 : 0]; - assign _zz_46 = _zz_76; - assign _zz_77 = _zz_71[6 : 5]; - assign _zz_45 = _zz_77; - assign _zz_78 = _zz_71[8 : 7]; - assign _zz_44 = _zz_78; - assign _zz_79 = _zz_71[17 : 16]; - assign _zz_43 = _zz_79; - assign _zz_80 = _zz_71[20 : 19]; - assign _zz_42 = _zz_80; - assign _zz_81 = _zz_71[22 : 21]; - assign _zz_41 = _zz_81; - assign _zz_82 = _zz_71[25 : 24]; - assign _zz_40 = _zz_82; + assign when_DBusSimplePlugin_l558 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_decode_ENV_CTRL_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_ENV_CTRL_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_ENV_CTRL_5 = ((decode_INSTRUCTION & 32'h00000050) == 32'h00000010); + assign _zz_decode_ENV_CTRL_6 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_ENV_CTRL_2 = {(((decode_INSTRUCTION & _zz__zz_decode_ENV_CTRL_2) == 32'h00100050) != 1'b0),{((_zz__zz_decode_ENV_CTRL_2_1 == _zz__zz_decode_ENV_CTRL_2_2) != 1'b0),{(_zz__zz_decode_ENV_CTRL_2_3 != 1'b0),{(_zz__zz_decode_ENV_CTRL_2_4 != _zz__zz_decode_ENV_CTRL_2_9),{_zz__zz_decode_ENV_CTRL_2_10,{_zz__zz_decode_ENV_CTRL_2_12,_zz__zz_decode_ENV_CTRL_2_14}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_ENV_CTRL_2[1 : 0]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_ENV_CTRL_2[6 : 5]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_ENV_CTRL_2[8 : 7]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_ENV_CTRL_2[17 : 16]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_ENV_CTRL_2[20 : 19]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_ENV_CTRL_2[22 : 21]; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_7 = _zz_decode_ENV_CTRL_2[25 : 24]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_7; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_128; - assign decode_RegFilePlugin_rs2Data = _zz_129; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_38 && writeBack_arbitration_isFiring); - if(_zz_83)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_2) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_37[11 : 7]; - if(_zz_83)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_2) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_47; - if(_zz_83)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_lastStageRegFileWrite_payload_data; + if(_zz_2) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -2762,394 +2618,434 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_84 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_84 = {31'd0, _zz_186}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_84 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_85 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_85 = {29'd0, _zz_187}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_85 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_85 = {27'd0, _zz_188}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_86 = _zz_189[11]; - always @ (*) begin - _zz_87[19] = _zz_86; - _zz_87[18] = _zz_86; - _zz_87[17] = _zz_86; - _zz_87[16] = _zz_86; - _zz_87[15] = _zz_86; - _zz_87[14] = _zz_86; - _zz_87[13] = _zz_86; - _zz_87[12] = _zz_86; - _zz_87[11] = _zz_86; - _zz_87[10] = _zz_86; - _zz_87[9] = _zz_86; - _zz_87[8] = _zz_86; - _zz_87[7] = _zz_86; - _zz_87[6] = _zz_86; - _zz_87[5] = _zz_86; - _zz_87[4] = _zz_86; - _zz_87[3] = _zz_86; - _zz_87[2] = _zz_86; - _zz_87[1] = _zz_86; - _zz_87[0] = _zz_86; - end - - assign _zz_88 = _zz_190[11]; - always @ (*) begin - _zz_89[19] = _zz_88; - _zz_89[18] = _zz_88; - _zz_89[17] = _zz_88; - _zz_89[16] = _zz_88; - _zz_89[15] = _zz_88; - _zz_89[14] = _zz_88; - _zz_89[13] = _zz_88; - _zz_89[12] = _zz_88; - _zz_89[11] = _zz_88; - _zz_89[10] = _zz_88; - _zz_89[9] = _zz_88; - _zz_89[8] = _zz_88; - _zz_89[7] = _zz_88; - _zz_89[6] = _zz_88; - _zz_89[5] = _zz_88; - _zz_89[4] = _zz_88; - _zz_89[3] = _zz_88; - _zz_89[2] = _zz_88; - _zz_89[1] = _zz_88; - _zz_89[0] = _zz_88; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_90 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_90 = {_zz_87,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_90 = {_zz_89,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_90 = _zz_32; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_191; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); - assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_binary_sequential_DISABLE_1); assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? memory_REGFILE_WRITE_DATA : execute_SRC1); assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == 4'b0000); - always @ (*) begin + assign when_ShiftPlugins_l169 = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != 5'h0)); + always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_91 = (execute_LightShifterPlugin_shiftInput <<< 1); + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_execute_to_memory_REGFILE_WRITE_DATA_1 = (execute_LightShifterPlugin_shiftInput <<< 1); end default : begin - _zz_91 = _zz_198; + _zz_execute_to_memory_REGFILE_WRITE_DATA_1 = _zz__zz_execute_to_memory_REGFILE_WRITE_DATA_1; end endcase end - always @ (*) begin - _zz_92 = 1'b0; - if(_zz_94)begin - if((_zz_95 == decode_INSTRUCTION[19 : 15]))begin - _zz_92 = 1'b1; + assign when_ShiftPlugins_l175 = (! execute_arbitration_isStuckByOthers); + assign when_ShiftPlugins_l184 = (! execute_LightShifterPlugin_done); + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end - if(_zz_144)begin - if(_zz_145)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_92 = 1'b1; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l59) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_146)begin - if(_zz_147)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_92 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l59_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_148)begin - if(_zz_149)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]))begin - _zz_92 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l59_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_92 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_93 = 1'b0; - if(_zz_94)begin - if((_zz_95 == decode_INSTRUCTION[24 : 20]))begin - _zz_93 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end - if(_zz_144)begin - if(_zz_145)begin - if((writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_93 = 1'b1; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l62) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_146)begin - if(_zz_147)begin - if((memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_93 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l62_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_148)begin - if(_zz_149)begin - if((execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]))begin - _zz_93 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l62_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_93 = 1'b0; - end - end - + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_lastStageRegFileWrite_payload_data; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l59 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b1 || (! 1'b1)); + assign when_HazardSimplePlugin_l59_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b1 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l59_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l62_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b1 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_96 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_96 == 3'b000)) begin - _zz_97 = execute_BranchPlugin_eq; - end else if((_zz_96 == 3'b001)) begin - _zz_97 = (! execute_BranchPlugin_eq); - end else if((((_zz_96 & 3'b101) == 3'b101))) begin - _zz_97 = (! execute_SRC_LESS); - end else begin - _zz_97 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_DO = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_DO = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_DO = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_DO = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_98 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_DO_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_98 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_DO_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_98 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_DO_1 = 1'b1; end default : begin - _zz_98 = _zz_97; + _zz_execute_BRANCH_DO_1 = _zz_execute_BRANCH_DO; end endcase end - assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); - assign _zz_99 = _zz_200[19]; - always @ (*) begin - _zz_100[10] = _zz_99; - _zz_100[9] = _zz_99; - _zz_100[8] = _zz_99; - _zz_100[7] = _zz_99; - _zz_100[6] = _zz_99; - _zz_100[5] = _zz_99; - _zz_100[4] = _zz_99; - _zz_100[3] = _zz_99; - _zz_100[2] = _zz_99; - _zz_100[1] = _zz_99; - _zz_100[0] = _zz_99; - end - - assign _zz_101 = _zz_201[11]; - always @ (*) begin - _zz_102[19] = _zz_101; - _zz_102[18] = _zz_101; - _zz_102[17] = _zz_101; - _zz_102[16] = _zz_101; - _zz_102[15] = _zz_101; - _zz_102[14] = _zz_101; - _zz_102[13] = _zz_101; - _zz_102[12] = _zz_101; - _zz_102[11] = _zz_101; - _zz_102[10] = _zz_101; - _zz_102[9] = _zz_101; - _zz_102[8] = _zz_101; - _zz_102[7] = _zz_101; - _zz_102[6] = _zz_101; - _zz_102[5] = _zz_101; - _zz_102[4] = _zz_101; - _zz_102[3] = _zz_101; - _zz_102[2] = _zz_101; - _zz_102[1] = _zz_101; - _zz_102[0] = _zz_101; - end - - assign _zz_103 = _zz_202[11]; - always @ (*) begin - _zz_104[18] = _zz_103; - _zz_104[17] = _zz_103; - _zz_104[16] = _zz_103; - _zz_104[15] = _zz_103; - _zz_104[14] = _zz_103; - _zz_104[13] = _zz_103; - _zz_104[12] = _zz_103; - _zz_104[11] = _zz_103; - _zz_104[10] = _zz_103; - _zz_104[9] = _zz_103; - _zz_104[8] = _zz_103; - _zz_104[7] = _zz_103; - _zz_104[6] = _zz_103; - _zz_104[5] = _zz_103; - _zz_104[4] = _zz_103; - _zz_104[3] = _zz_103; - _zz_104[2] = _zz_103; - _zz_104[1] = _zz_103; - _zz_104[0] = _zz_103; - end - - always @ (*) begin + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JALR) ? execute_RS1 : execute_PC); + assign _zz_execute_BranchPlugin_branch_src2 = _zz__zz_execute_BranchPlugin_branch_src2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[19] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[18] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[17] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[16] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[15] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[14] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[13] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[12] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[11] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_105 = {{_zz_100,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_1,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_105 = {_zz_102,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_branch_src2_6 = {_zz_execute_BranchPlugin_branch_src2_3,execute_INSTRUCTION[31 : 20]}; end default : begin - _zz_105 = {{_zz_104,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + _zz_execute_BranchPlugin_branch_src2_6 = {{_zz_execute_BranchPlugin_branch_src2_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; end endcase end - assign execute_BranchPlugin_branch_src2 = _zz_105; + assign execute_BranchPlugin_branch_src2 = _zz_execute_BranchPlugin_branch_src2_6; assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end assign CsrPlugin_misa_base = 2'b01; assign CsrPlugin_misa_extensions = 26'h0000042; - assign _zz_106 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_107 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_108 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_109 = {decodeExceptionPort_valid,IBusSimplePlugin_decodeExceptionPort_valid}; - assign _zz_110 = _zz_203[0]; - assign _zz_111 = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; - assign _zz_112 = _zz_205[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_133)begin + if(decodeExceptionPort_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(_zz_136)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_lastStageWasWfi = 1'b0; assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -3160,8 +3056,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -3171,72 +3067,79 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_773) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_834) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_835) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_150)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_151)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_151)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -3249,43 +3152,53 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_150)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_150)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_160) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign _zz_114 = (_zz_113 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_114 != 32'h0); - always @ (*) begin + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_152) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin debug_bus_cmd_ready = IBusSimplePlugin_injectionPort_ready; end end @@ -3295,9 +3208,9 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_115))begin + if(when_DebugPlugin_l244) begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -3306,12 +3219,13 @@ module VexRiscv ( end end - always @ (*) begin + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin IBusSimplePlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_152) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin IBusSimplePlugin_injectionPort_valid = 1'b1; end end @@ -3322,33 +3236,92 @@ module VexRiscv ( end assign IBusSimplePlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusSimplePlugin_incomingInstruction); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_25 = decode_SRC1_CTRL; - assign _zz_23 = _zz_46; - assign _zz_34 = decode_to_execute_SRC1_CTRL; - assign _zz_22 = decode_ALU_CTRL; - assign _zz_20 = _zz_45; - assign _zz_35 = decode_to_execute_ALU_CTRL; - assign _zz_19 = decode_SRC2_CTRL; - assign _zz_17 = _zz_44; - assign _zz_33 = decode_to_execute_SRC2_CTRL; - assign _zz_16 = decode_ALU_BITWISE_CTRL; - assign _zz_14 = _zz_43; - assign _zz_36 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_13 = decode_SHIFT_CTRL; - assign _zz_11 = _zz_42; - assign _zz_31 = decode_to_execute_SHIFT_CTRL; - assign _zz_10 = decode_BRANCH_CTRL; - assign _zz_8 = _zz_41; - assign _zz_29 = decode_to_execute_BRANCH_CTRL; - assign _zz_7 = decode_ENV_CTRL; - assign _zz_4 = execute_ENV_CTRL; - assign _zz_2 = memory_ENV_CTRL; - assign _zz_5 = _zz_40; - assign _zz_27 = decode_to_execute_ENV_CTRL; - assign _zz_26 = execute_to_memory_ENV_CTRL; - assign _zz_28 = memory_to_writeBack_ENV_CTRL; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_14 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_17 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_30 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_31 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_32 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_34 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_35 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_42 = ((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)); + assign when_Pipeline_l124_43 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -3369,9 +3342,15 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin IBusSimplePlugin_injectionPort_ready = 1'b0; - case(_zz_116) + case(switch_Fetcher_l362) 3'b100 : begin IBusSimplePlugin_injectionPort_ready = 1'b1; end @@ -3380,115 +3359,137 @@ module VexRiscv ( endcase end - always @ (*) begin - _zz_117 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_117[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_117[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_117[3 : 3] = CsrPlugin_mstatus_MIE; + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_Fetcher_l398 = (switch_Fetcher_l362 != 3'b000); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_2[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_2[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_118 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_118[11 : 11] = CsrPlugin_mip_MEIP; - _zz_118[7 : 7] = CsrPlugin_mip_MTIP; - _zz_118[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_4[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_119 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_119[11 : 11] = CsrPlugin_mie_MEIE; - _zz_119[7 : 7] = CsrPlugin_mie_MTIE; - _zz_119[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_120 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_120[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_6[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_121 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_121[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_121[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_122 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_122[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_123 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_123[31 : 0] = _zz_113; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - always @ (*) begin - _zz_124 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_124[31 : 0] = _zz_114; + assign CsrPlugin_csrMapping_readDataInit = (((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_6 | _zz_CsrPlugin_csrMapping_readDataInit_7) | (_zz_CsrPlugin_csrMapping_readDataInit_8 | _zz_CsrPlugin_csrMapping_readDataInit_9))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + always @(*) begin + iBus_cmd_ready = iBus_cmd_m2sPipe_ready; + if(when_Stream_l342) begin + iBus_cmd_ready = 1'b1; end end - assign execute_CsrPlugin_readData = (((_zz_117 | _zz_118) | (_zz_119 | _zz_120)) | ((_zz_121 | _zz_122) | (_zz_123 | _zz_124))); - assign iBus_cmd_ready = ((1'b1 && (! iBus_cmd_m2sPipe_valid)) || iBus_cmd_m2sPipe_ready); - assign iBus_cmd_m2sPipe_valid = iBus_cmd_m2sPipe_rValid; - assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_m2sPipe_rData_pc; + assign when_Stream_l342 = (! iBus_cmd_m2sPipe_valid); + assign iBus_cmd_m2sPipe_valid = iBus_cmd_rValid; + assign iBus_cmd_m2sPipe_payload_pc = iBus_cmd_rData_pc; assign iBusWishbone_ADR = (iBus_cmd_m2sPipe_payload_pc >>> 2); assign iBusWishbone_CTI = 3'b000; assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; assign iBusWishbone_CYC = iBus_cmd_m2sPipe_valid; assign iBusWishbone_STB = iBus_cmd_m2sPipe_valid; assign iBus_cmd_m2sPipe_ready = (iBus_cmd_m2sPipe_valid && iBusWishbone_ACK); assign iBus_rsp_valid = (iBusWishbone_CYC && iBusWishbone_ACK); assign iBus_rsp_payload_inst = iBusWishbone_DAT_MISO; assign iBus_rsp_payload_error = 1'b0; - assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; - assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; - assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; - assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; - assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; - assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBus_cmd_halfPipe_fire = (dBus_cmd_halfPipe_valid && dBus_cmd_halfPipe_ready); + assign dBus_cmd_ready = (! dBus_cmd_rValid); + assign dBus_cmd_halfPipe_valid = dBus_cmd_rValid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_rData_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_rData_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_rData_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_rData_size; assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); assign dBusWishbone_CTI = 3'b000; assign dBusWishbone_BTE = 2'b00; - always @ (*) begin + always @(*) begin case(dBus_cmd_halfPipe_payload_size) 2'b00 : begin - _zz_125 = 4'b0001; + _zz_dBusWishbone_SEL = 4'b0001; end 2'b01 : begin - _zz_125 = 4'b0011; + _zz_dBusWishbone_SEL = 4'b0011; end default : begin - _zz_125 = 4'b1111; + _zz_dBusWishbone_SEL = 4'b1111; end endcase end - always @ (*) begin - dBusWishbone_SEL = (_zz_125 <<< dBus_cmd_halfPipe_payload_address[1 : 0]); - if((! dBus_cmd_halfPipe_payload_wr))begin + always @(*) begin + dBusWishbone_SEL = (_zz_dBusWishbone_SEL <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + if(when_DBusSimplePlugin_l189) begin dBusWishbone_SEL = 4'b1111; end end + assign when_DBusSimplePlugin_l189 = (! dBus_cmd_halfPipe_payload_wr); assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); @@ -3497,15 +3498,14 @@ module VexRiscv ( assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); assign dBus_rsp_data = dBusWishbone_DAT_MISO; assign dBus_rsp_error = 1'b0; - assign _zz_127 = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusSimplePlugin_fetchPc_pcReg <= externalResetVector; IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; IBusSimplePlugin_fetchPc_booted <= 1'b0; IBusSimplePlugin_fetchPc_inc <= 1'b0; - _zz_57 <= 1'b0; - _zz_58 <= 1'b0; + _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; @@ -3513,9 +3513,9 @@ module VexRiscv ( IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; IBusSimplePlugin_pending_value <= 3'b000; IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= 3'b000; - _zz_83 <= 1'b1; + _zz_2 <= 1'b1; execute_LightShifterPlugin_isActive <= 1'b0; - _zz_94 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_mstatus_MIE <= 1'b0; CsrPlugin_mstatus_MPIE <= 1'b0; CsrPlugin_mstatus_MPP <= 2'b11; @@ -3532,92 +3532,91 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; - _zz_113 <= 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_116 <= 3'b000; - iBus_cmd_m2sPipe_rValid <= 1'b0; - dBus_cmd_halfPipe_regs_valid <= 1'b0; - dBus_cmd_halfPipe_regs_ready <= 1'b1; + switch_Fetcher_l362 <= 3'b000; + iBus_cmd_rValid <= 1'b0; + dBus_cmd_rValid <= 1'b0; end else begin - if(IBusSimplePlugin_fetchPc_correction)begin + if(IBusSimplePlugin_fetchPc_correction) begin IBusSimplePlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + if(IBusSimplePlugin_fetchPc_output_fire) begin IBusSimplePlugin_fetchPc_correctionReg <= 1'b0; end IBusSimplePlugin_fetchPc_booted <= 1'b1; - if((IBusSimplePlugin_fetchPc_correction || IBusSimplePlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end - if((IBusSimplePlugin_fetchPc_output_valid && IBusSimplePlugin_fetchPc_output_ready))begin + if(IBusSimplePlugin_fetchPc_output_fire_1) begin IBusSimplePlugin_fetchPc_inc <= 1'b1; end - if(((! IBusSimplePlugin_fetchPc_output_valid) && IBusSimplePlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusSimplePlugin_fetchPc_inc <= 1'b0; end - if((IBusSimplePlugin_fetchPc_booted && ((IBusSimplePlugin_fetchPc_output_ready || IBusSimplePlugin_fetchPc_correction) || IBusSimplePlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusSimplePlugin_fetchPc_pcReg <= IBusSimplePlugin_fetchPc_pc; end - if(IBusSimplePlugin_iBusRsp_flush)begin - _zz_57 <= 1'b0; + if(IBusSimplePlugin_iBusRsp_flush) begin + _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_55)begin - _zz_57 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusSimplePlugin_iBusRsp_stages_0_output_ready_2 <= (IBusSimplePlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(decode_arbitration_removeIt)begin - _zz_58 <= 1'b0; + if(decode_arbitration_removeIt) begin + _zz_IBusSimplePlugin_injector_decodeInput_valid <= 1'b0; end - if(IBusSimplePlugin_iBusRsp_output_ready)begin - _zz_58 <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); + if(IBusSimplePlugin_iBusRsp_output_ready) begin + _zz_IBusSimplePlugin_injector_decodeInput_valid <= (IBusSimplePlugin_iBusRsp_output_valid && (! IBusSimplePlugin_externalFlush)); end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusSimplePlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusSimplePlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusSimplePlugin_injector_decodeInput_ready)))begin + if(when_Fetcher_l329_1) begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= IBusSimplePlugin_injector_nextPcCalc_valids_0; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= IBusSimplePlugin_injector_nextPcCalc_valids_1; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= IBusSimplePlugin_injector_nextPcCalc_valids_2; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= IBusSimplePlugin_injector_nextPcCalc_valids_3; end - if(IBusSimplePlugin_fetchPc_flushed)begin + if(IBusSimplePlugin_fetchPc_flushed) begin IBusSimplePlugin_injector_nextPcCalc_valids_4 <= 1'b0; end IBusSimplePlugin_pending_value <= IBusSimplePlugin_pending_next; - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_182); - if(IBusSimplePlugin_iBusRsp_flush)begin - IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_184); + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_rspJoin_rspBuffer_discardCounter - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter); + if(IBusSimplePlugin_iBusRsp_flush) begin + IBusSimplePlugin_rspJoin_rspBuffer_discardCounter <= (IBusSimplePlugin_pending_value - _zz_IBusSimplePlugin_rspJoin_rspBuffer_discardCounter_2); end `ifndef SYNTHESIS `ifdef FORMAL @@ -3639,72 +3638,72 @@ module VexRiscv ( end `endif `endif - _zz_83 <= 1'b0; - if(_zz_131)begin - if(_zz_153)begin + _zz_2 <= 1'b0; + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l175) begin execute_LightShifterPlugin_isActive <= 1'b1; - if(execute_LightShifterPlugin_done)begin + if(execute_LightShifterPlugin_done) begin execute_LightShifterPlugin_isActive <= 1'b0; end end end - if(execute_arbitration_removeIt)begin + if(execute_arbitration_removeIt) begin execute_LightShifterPlugin_isActive <= 1'b0; end - _zz_94 <= (_zz_38 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_154)begin - if(_zz_155)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_156)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_157)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_137)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -3715,8 +3714,8 @@ module VexRiscv ( end endcase end - if(_zz_138)begin - case(_zz_140) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -3726,147 +3725,136 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_108,{_zz_107,_zz_106}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_116) + case(switch_Fetcher_l362) 3'b000 : begin - if(IBusSimplePlugin_injectionPort_valid)begin - _zz_116 <= 3'b001; + if(IBusSimplePlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; end end 3'b001 : begin - _zz_116 <= 3'b010; + switch_Fetcher_l362 <= 3'b010; end 3'b010 : begin - _zz_116 <= 3'b011; + switch_Fetcher_l362 <= 3'b011; end 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_116 <= 3'b100; + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; end end 3'b100 : begin - _zz_116 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; end default : begin end endcase - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_207[0]; - CsrPlugin_mstatus_MIE <= _zz_208[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_210[0]; - CsrPlugin_mie_MTIE <= _zz_211[0]; - CsrPlugin_mie_MSIE <= _zz_212[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_113 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(iBus_cmd_ready)begin - iBus_cmd_m2sPipe_rValid <= iBus_cmd_valid; + if(iBus_cmd_ready) begin + iBus_cmd_rValid <= iBus_cmd_valid; end - if(_zz_158)begin - dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; - dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); - end else begin - dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); - dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + if(dBus_cmd_valid) begin + dBus_cmd_rValid <= 1'b1; + end + if(dBus_cmd_halfPipe_fire) begin + dBus_cmd_rValid <= 1'b0; end end end - always @ (posedge clk) begin - if(IBusSimplePlugin_iBusRsp_output_ready)begin - _zz_59 <= IBusSimplePlugin_iBusRsp_output_payload_pc; - _zz_60 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; - _zz_61 <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; - _zz_62 <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; + always @(posedge clk) begin + if(IBusSimplePlugin_iBusRsp_output_ready) begin + _zz_IBusSimplePlugin_injector_decodeInput_payload_pc <= IBusSimplePlugin_iBusRsp_output_payload_pc; + _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_error <= IBusSimplePlugin_iBusRsp_output_payload_rsp_error; + _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; + _zz_IBusSimplePlugin_injector_decodeInput_payload_isRvc <= IBusSimplePlugin_iBusRsp_output_payload_isRvc; end - if(IBusSimplePlugin_injector_decodeInput_ready)begin + if(IBusSimplePlugin_injector_decodeInput_ready) begin IBusSimplePlugin_injector_formal_rawInDecode <= IBusSimplePlugin_iBusRsp_output_payload_rsp_inst; end - if(IBusSimplePlugin_iBusRsp_stages_1_output_ready)begin - IBusSimplePlugin_mmu_joinCtx_physicalAddress <= IBusSimplePlugin_mmuBus_rsp_physicalAddress; - IBusSimplePlugin_mmu_joinCtx_isIoAccess <= IBusSimplePlugin_mmuBus_rsp_isIoAccess; - IBusSimplePlugin_mmu_joinCtx_isPaging <= IBusSimplePlugin_mmuBus_rsp_isPaging; - IBusSimplePlugin_mmu_joinCtx_allowRead <= IBusSimplePlugin_mmuBus_rsp_allowRead; - IBusSimplePlugin_mmu_joinCtx_allowWrite <= IBusSimplePlugin_mmuBus_rsp_allowWrite; - IBusSimplePlugin_mmu_joinCtx_allowExecute <= IBusSimplePlugin_mmuBus_rsp_allowExecute; - IBusSimplePlugin_mmu_joinCtx_exception <= IBusSimplePlugin_mmuBus_rsp_exception; - IBusSimplePlugin_mmu_joinCtx_refilling <= IBusSimplePlugin_mmuBus_rsp_refilling; - IBusSimplePlugin_mmu_joinCtx_bypassTranslation <= IBusSimplePlugin_mmuBus_rsp_bypassTranslation; - end - if(_zz_131)begin - if(_zz_153)begin + if(when_ShiftPlugins_l169) begin + if(when_ShiftPlugins_l175) begin execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - 5'h01); end end - _zz_95 <= _zz_37[11 : 7]; + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_133)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_110 ? IBusSimplePlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_110 ? IBusSimplePlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(decodeExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= decodeExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= decodeExceptionPort_payload_badAddr; end - if(CsrPlugin_selfException_valid)begin + if(CsrPlugin_selfException_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; end - if(_zz_136)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_112 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_112 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? DBusSimplePlugin_memoryExceptionPort_payload_code : BranchPlugin_branchExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? DBusSimplePlugin_memoryExceptionPort_payload_badAddr : BranchPlugin_branchExceptionPort_payload_badAddr); end - if(_zz_154)begin - if(_zz_155)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_156)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_157)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_137)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -3875,283 +3863,280 @@ module VexRiscv ( endcase end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_32; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_6) begin decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_7) begin execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_FORMAL_PC_NEXT <= _zz_48; + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_24; + if(when_Pipeline_l124_9) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_10) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_21; + if(when_Pipeline_l124_14) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_18; + if(when_Pipeline_l124_15) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_16) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin execute_to_memory_MEMORY_STORE <= execute_MEMORY_STORE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin memory_to_writeBack_MEMORY_STORE <= memory_MEMORY_STORE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_15; + if(when_Pipeline_l124_26) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_12; + if(when_Pipeline_l124_27) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_9; + if(when_Pipeline_l124_28) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_29) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_30) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_3; + if(when_Pipeline_l124_31) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_1; + if(when_Pipeline_l124_32) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_33) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_34) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_35) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin execute_to_memory_ALIGNEMENT_FAULT <= execute_ALIGNEMENT_FAULT; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_FAULT <= execute_MMU_FAULT; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MMU_RSP2_physicalAddress <= execute_MMU_RSP2_physicalAddress; - execute_to_memory_MMU_RSP2_isIoAccess <= execute_MMU_RSP2_isIoAccess; - execute_to_memory_MMU_RSP2_isPaging <= execute_MMU_RSP2_isPaging; - execute_to_memory_MMU_RSP2_allowRead <= execute_MMU_RSP2_allowRead; - execute_to_memory_MMU_RSP2_allowWrite <= execute_MMU_RSP2_allowWrite; - execute_to_memory_MMU_RSP2_allowExecute <= execute_MMU_RSP2_allowExecute; - execute_to_memory_MMU_RSP2_exception <= execute_MMU_RSP2_exception; - execute_to_memory_MMU_RSP2_refilling <= execute_MMU_RSP2_refilling; - execute_to_memory_MMU_RSP2_bypassTranslation <= execute_MMU_RSP2_bypassTranslation; + if(when_Pipeline_l124_42) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_execute_to_memory_REGFILE_WRITE_DATA; end - if(((! memory_arbitration_isStuck) && (! execute_arbitration_isStuckByOthers)))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_30; - end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin memory_to_writeBack_REGFILE_WRITE_DATA <= memory_REGFILE_WRITE_DATA; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_44) begin execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_45) begin execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin memory_to_writeBack_MEMORY_READ_DATA <= memory_MEMORY_READ_DATA; end - if((_zz_116 != 3'b000))begin - _zz_61 <= IBusSimplePlugin_injectionPort_payload; + if(when_Fetcher_l398) begin + _zz_IBusSimplePlugin_injector_decodeInput_payload_rsp_inst <= IBusSimplePlugin_injectionPort_payload; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_209[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(iBus_cmd_ready)begin - iBus_cmd_m2sPipe_rData_pc <= iBus_cmd_payload_pc; + if(iBus_cmd_ready) begin + iBus_cmd_rData_pc <= iBus_cmd_payload_pc; end - if(_zz_158)begin - dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; - dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; - dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; - dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + if(dBus_cmd_ready) begin + dBus_cmd_rData_wr <= dBus_cmd_payload_wr; + dBus_cmd_rData_address <= dBus_cmd_payload_address; + dBus_cmd_rData_data <= dBus_cmd_payload_data; + dBus_cmd_rData_size <= dBus_cmd_payload_size; end end - always @ (posedge clk) begin + always @(posedge clk) begin DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin + if(debug_bus_cmd_ready) begin DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusSimplePlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_47; + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_lastStageRegFileWrite_payload_data; end - _zz_115 <= debug_bus_cmd_payload_address[2]; - if(_zz_134)begin + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin + always @(posedge clk) begin if(debugReset) begin DebugPlugin_resetIt <= 1'b0; DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + if(when_DebugPlugin_l225) begin DebugPlugin_godmode <= 1'b1; end - if(debug_bus_cmd_valid)begin - case(_zz_152) + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin + if(when_DebugPlugin_l260) begin DebugPlugin_resetIt <= 1'b1; end - if(debug_bus_cmd_payload_data[24])begin + if(when_DebugPlugin_l260_1) begin DebugPlugin_resetIt <= 1'b0; end - if(debug_bus_cmd_payload_data[17])begin + if(when_DebugPlugin_l261) begin DebugPlugin_haltIt <= 1'b1; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l261_1) begin DebugPlugin_haltIt <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l262) begin DebugPlugin_haltedByBreak <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l263) begin DebugPlugin_godmode <= 1'b0; end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end end end default : begin end endcase end - if(_zz_134)begin - if(_zz_135)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_139)begin - if(decode_arbitration_isValid)begin + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin DebugPlugin_haltIt <= 1'b1; end end @@ -4175,9 +4160,7 @@ module StreamFifoLowLatency ( input clk, input reset ); - wire _zz_4; - wire [0:0] _zz_5; - reg _zz_1; + reg when_Phase_l623; reg pushPtr_willIncrement; reg pushPtr_willClear; wire pushPtr_willOverflowIfInc; @@ -4192,44 +4175,44 @@ module StreamFifoLowLatency ( wire full; wire pushing; wire popping; - wire [32:0] _zz_2; - reg [32:0] _zz_3; + wire when_Stream_l995; + wire [32:0] _zz_io_pop_payload_error; + wire when_Stream_l1008; + reg [32:0] _zz_io_pop_payload_error_1; - assign _zz_4 = (! empty); - assign _zz_5 = _zz_2[0 : 0]; - always @ (*) begin - _zz_1 = 1'b0; - if(pushing)begin - _zz_1 = 1'b1; + always @(*) begin + when_Phase_l623 = 1'b0; + if(pushing) begin + when_Phase_l623 = 1'b1; end end - always @ (*) begin + always @(*) begin pushPtr_willIncrement = 1'b0; - if(pushing)begin + if(pushing) begin pushPtr_willIncrement = 1'b1; end end - always @ (*) begin + always @(*) begin pushPtr_willClear = 1'b0; - if(io_flush)begin + if(io_flush) begin pushPtr_willClear = 1'b1; end end assign pushPtr_willOverflowIfInc = 1'b1; assign pushPtr_willOverflow = (pushPtr_willOverflowIfInc && pushPtr_willIncrement); - always @ (*) begin + always @(*) begin popPtr_willIncrement = 1'b0; - if(popping)begin + if(popping) begin popPtr_willIncrement = 1'b1; end end - always @ (*) begin + always @(*) begin popPtr_willClear = 1'b0; - if(io_flush)begin + if(io_flush) begin popPtr_willClear = 1'b1; end end @@ -4242,48 +4225,50 @@ module StreamFifoLowLatency ( assign pushing = (io_push_valid && io_push_ready); assign popping = (io_pop_valid && io_pop_ready); assign io_push_ready = (! full); - always @ (*) begin - if(_zz_4)begin + assign when_Stream_l995 = (! empty); + always @(*) begin + if(when_Stream_l995) begin io_pop_valid = 1'b1; end else begin io_pop_valid = io_push_valid; end end - assign _zz_2 = _zz_3; - always @ (*) begin - if(_zz_4)begin - io_pop_payload_error = _zz_5[0]; + assign _zz_io_pop_payload_error = _zz_io_pop_payload_error_1; + always @(*) begin + if(when_Stream_l995) begin + io_pop_payload_error = _zz_io_pop_payload_error[0]; end else begin io_pop_payload_error = io_push_payload_error; end end - always @ (*) begin - if(_zz_4)begin - io_pop_payload_inst = _zz_2[32 : 1]; + always @(*) begin + if(when_Stream_l995) begin + io_pop_payload_inst = _zz_io_pop_payload_error[32 : 1]; end else begin io_pop_payload_inst = io_push_payload_inst; end end + assign when_Stream_l1008 = (pushing != popping); assign io_occupancy = (risingOccupancy && ptrMatch); - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin risingOccupancy <= 1'b0; end else begin - if((pushing != popping))begin + if(when_Stream_l1008) begin risingOccupancy <= pushing; end - if(io_flush)begin + if(io_flush) begin risingOccupancy <= 1'b0; end end end - always @ (posedge clk) begin - if(_zz_1)begin - _zz_3 <= {io_push_payload_inst,io_push_payload_error}; + always @(posedge clk) begin + if(when_Phase_l623) begin + _zz_io_pop_payload_error_1 <= {io_push_payload_inst,io_push_payload_error}; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v index c5eea43..11834d9 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfu.v @@ -1,57 +1,58 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 5bb91146a62643cf606443d5366c69720906549c - - -`define Input2Kind_defaultEncoding_type [0:0] -`define Input2Kind_defaultEncoding_RS 1'b0 -`define Input2Kind_defaultEncoding_IMM_I 1'b1 - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define Input2Kind_binary_sequential_type [0:0] +`define Input2Kind_binary_sequential_RS 1'b0 +`define Input2Kind_binary_sequential_IMM_I 1'b1 + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, + input [31:0] externalInterruptArray, output CfuPlugin_bus_cmd_valid, input CfuPlugin_bus_cmd_ready, output [9:0] CfuPlugin_bus_cmd_payload_function_id, @@ -59,9 +60,7 @@ module VexRiscv ( output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, input CfuPlugin_bus_rsp_valid, output CfuPlugin_bus_rsp_ready, - input CfuPlugin_bus_rsp_payload_response_ok, input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, - input [31:0] externalInterruptArray, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, input iBusWishbone_ACK, @@ -87,37 +86,37 @@ module VexRiscv ( input clk, input reset ); - wire _zz_217; - wire _zz_218; - wire _zz_219; - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - reg _zz_225; - wire _zz_226; - wire [31:0] _zz_227; - wire _zz_228; - wire [31:0] _zz_229; - reg _zz_230; - wire _zz_231; - wire _zz_232; - wire [31:0] _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire [3:0] _zz_242; - wire _zz_243; - wire _zz_244; - reg [31:0] _zz_245; - reg [31:0] _zz_246; - reg [31:0] _zz_247; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -140,6 +139,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -148,389 +148,329 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_248; - wire _zz_249; - wire _zz_250; - wire _zz_251; - wire _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire _zz_256; - wire _zz_257; - wire _zz_258; - wire _zz_259; - wire _zz_260; - wire _zz_261; - wire _zz_262; - wire [1:0] _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire _zz_267; - wire _zz_268; - wire _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire [1:0] _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire _zz_279; - wire _zz_280; - wire _zz_281; - wire _zz_282; - wire _zz_283; - wire [1:0] _zz_284; - wire _zz_285; - wire [1:0] _zz_286; - wire [51:0] _zz_287; - wire [51:0] _zz_288; - wire [51:0] _zz_289; - wire [32:0] _zz_290; - wire [51:0] _zz_291; - wire [49:0] _zz_292; - wire [51:0] _zz_293; - wire [49:0] _zz_294; - wire [51:0] _zz_295; - wire [32:0] _zz_296; - wire [31:0] _zz_297; - wire [32:0] _zz_298; - wire [0:0] _zz_299; - wire [0:0] _zz_300; - wire [0:0] _zz_301; - wire [0:0] _zz_302; - wire [0:0] _zz_303; - wire [0:0] _zz_304; - wire [0:0] _zz_305; - wire [0:0] _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire [0:0] _zz_312; - wire [0:0] _zz_313; - wire [0:0] _zz_314; - wire [0:0] _zz_315; - wire [0:0] _zz_316; - wire [3:0] _zz_317; - wire [2:0] _zz_318; - wire [31:0] _zz_319; - wire [11:0] _zz_320; - wire [31:0] _zz_321; - wire [19:0] _zz_322; - wire [11:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [19:0] _zz_326; - wire [11:0] _zz_327; - wire [2:0] _zz_328; - wire [2:0] _zz_329; - wire [0:0] _zz_330; - wire [2:0] _zz_331; - wire [4:0] _zz_332; - wire [11:0] _zz_333; - wire [11:0] _zz_334; - wire [31:0] _zz_335; - wire [31:0] _zz_336; - wire [31:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire [31:0] _zz_340; - wire [31:0] _zz_341; - wire [11:0] _zz_342; - wire [19:0] _zz_343; - wire [11:0] _zz_344; - wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [11:0] _zz_348; - wire [19:0] _zz_349; - wire [11:0] _zz_350; - wire [2:0] _zz_351; - wire [1:0] _zz_352; - wire [1:0] _zz_353; - wire [1:0] _zz_354; - wire [1:0] _zz_355; - wire [9:0] _zz_356; - wire [7:0] _zz_357; - wire [65:0] _zz_358; - wire [65:0] _zz_359; - wire [31:0] _zz_360; - wire [31:0] _zz_361; - wire [0:0] _zz_362; - wire [5:0] _zz_363; - wire [32:0] _zz_364; - wire [31:0] _zz_365; - wire [31:0] _zz_366; - wire [32:0] _zz_367; - wire [32:0] _zz_368; - wire [32:0] _zz_369; - wire [32:0] _zz_370; - wire [0:0] _zz_371; - wire [32:0] _zz_372; - wire [0:0] _zz_373; - wire [32:0] _zz_374; - wire [0:0] _zz_375; - wire [31:0] _zz_376; - wire [0:0] _zz_377; - wire [0:0] _zz_378; - wire [0:0] _zz_379; - wire [0:0] _zz_380; - wire [0:0] _zz_381; - wire [0:0] _zz_382; - wire [0:0] _zz_383; - wire [26:0] _zz_384; - wire _zz_385; - wire _zz_386; - wire [1:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire _zz_391; - wire [0:0] _zz_392; - wire [14:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire _zz_397; - wire [0:0] _zz_398; - wire [8:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire [31:0] _zz_402; - wire _zz_403; - wire [0:0] _zz_404; - wire [2:0] _zz_405; - wire _zz_406; - wire _zz_407; - wire _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire _zz_411; - wire _zz_412; - wire [0:0] _zz_413; - wire [26:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire [1:0] _zz_420; - wire [1:0] _zz_421; - wire _zz_422; - wire [0:0] _zz_423; - wire [21:0] _zz_424; - wire [31:0] _zz_425; - wire [31:0] _zz_426; - wire [31:0] _zz_427; - wire [31:0] _zz_428; - wire [31:0] _zz_429; - wire [31:0] _zz_430; - wire [0:0] _zz_431; - wire [0:0] _zz_432; - wire [2:0] _zz_433; - wire [2:0] _zz_434; - wire _zz_435; - wire [0:0] _zz_436; - wire [18:0] _zz_437; - wire [31:0] _zz_438; - wire [31:0] _zz_439; - wire [31:0] _zz_440; - wire [31:0] _zz_441; - wire _zz_442; - wire _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire _zz_446; - wire [0:0] _zz_447; - wire [0:0] _zz_448; - wire _zz_449; - wire [0:0] _zz_450; - wire [15:0] _zz_451; - wire [31:0] _zz_452; - wire _zz_453; - wire _zz_454; - wire _zz_455; - wire [2:0] _zz_456; - wire [2:0] _zz_457; - wire _zz_458; - wire [0:0] _zz_459; - wire [12:0] _zz_460; - wire _zz_461; - wire _zz_462; - wire _zz_463; - wire [0:0] _zz_464; - wire [2:0] _zz_465; - wire _zz_466; - wire [5:0] _zz_467; - wire [5:0] _zz_468; - wire _zz_469; - wire [0:0] _zz_470; - wire [9:0] _zz_471; - wire [31:0] _zz_472; - wire [31:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [0:0] _zz_479; - wire [31:0] _zz_480; - wire _zz_481; - wire [0:0] _zz_482; - wire [3:0] _zz_483; - wire [0:0] _zz_484; - wire [3:0] _zz_485; - wire [5:0] _zz_486; - wire [5:0] _zz_487; - wire _zz_488; - wire [0:0] _zz_489; - wire [7:0] _zz_490; - wire [31:0] _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; - wire [31:0] _zz_496; - wire [31:0] _zz_497; - wire [31:0] _zz_498; - wire [0:0] _zz_499; - wire [1:0] _zz_500; - wire _zz_501; - wire [0:0] _zz_502; - wire [1:0] _zz_503; - wire [0:0] _zz_504; - wire [3:0] _zz_505; - wire [0:0] _zz_506; - wire [0:0] _zz_507; - wire [1:0] _zz_508; - wire [1:0] _zz_509; - wire _zz_510; - wire [0:0] _zz_511; - wire [5:0] _zz_512; - wire [31:0] _zz_513; - wire [31:0] _zz_514; - wire _zz_515; - wire _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire _zz_520; - wire _zz_521; - wire [31:0] _zz_522; - wire [31:0] _zz_523; - wire _zz_524; - wire [0:0] _zz_525; - wire [1:0] _zz_526; - wire [31:0] _zz_527; - wire [31:0] _zz_528; - wire _zz_529; - wire _zz_530; - wire [0:0] _zz_531; - wire [0:0] _zz_532; - wire _zz_533; - wire [0:0] _zz_534; - wire [3:0] _zz_535; - wire [31:0] _zz_536; - wire [31:0] _zz_537; - wire [31:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire [31:0] _zz_541; - wire [31:0] _zz_542; - wire _zz_543; - wire _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire [0:0] _zz_549; - wire [2:0] _zz_550; - wire [0:0] _zz_551; - wire [0:0] _zz_552; - wire _zz_553; - wire [0:0] _zz_554; - wire [1:0] _zz_555; - wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire _zz_559; - wire _zz_560; - wire [31:0] _zz_561; - wire _zz_562; - wire [0:0] _zz_563; - wire [0:0] _zz_564; - wire [0:0] _zz_565; - wire [0:0] _zz_566; - wire [1:0] _zz_567; - wire [1:0] _zz_568; - wire [0:0] _zz_569; - wire [0:0] _zz_570; - wire [31:0] _zz_571; - wire [31:0] _zz_572; - wire [31:0] _zz_573; - wire [31:0] _zz_574; - wire [31:0] _zz_575; - wire [31:0] _zz_576; - wire _zz_577; - wire _zz_578; - wire _zz_579; - wire [31:0] _zz_580; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6; + wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18; + wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33; + wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45; + wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68; + wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100; + wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125; + wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1; + wire _zz_when; + wire _zz_when_1; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_41; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; - wire writeBack_CfuPlugin_CFU_IN_FLIGHT; - wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; wire decode_SRC2_FORCE_ZERO; + wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + wire decode_CfuPlugin_CFU_ENABLE; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_DIV; wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_1; - wire `Input2Kind_defaultEncoding_type _zz_2; - wire `Input2Kind_defaultEncoding_type _zz_3; - wire decode_CfuPlugin_CFU_ENABLE; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -538,24 +478,30 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; - wire `AluCtrlEnum_defaultEncoding_type _zz_25; - wire `AluCtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; - wire `Src1CtrlEnum_defaultEncoding_type _zz_28; - wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] memory_PC; + reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire execute_CfuPlugin_CFU_ENABLE; wire execute_IS_RS1_SIGNED; wire execute_IS_DIV; wire execute_IS_RS2_SIGNED; @@ -566,32 +512,26 @@ module VexRiscv ( wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; - reg _zz_30; - reg _zz_31; - wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_32; - wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_37; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -601,46 +541,46 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_38; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_41; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_42; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; - wire [31:0] _zz_46; - wire _zz_47; - reg _zz_48; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_49; - wire `EnvCtrlEnum_defaultEncoding_type _zz_50; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; - wire `Src2CtrlEnum_defaultEncoding_type _zz_54; - wire `AluCtrlEnum_defaultEncoding_type _zz_55; - wire `Src1CtrlEnum_defaultEncoding_type _zz_56; - reg [31:0] _zz_57; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -658,11 +598,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_59; - reg [31:0] _zz_60; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -692,7 +632,7 @@ module VexRiscv ( wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; + wire memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; @@ -749,7 +689,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -783,6 +723,11 @@ module VexRiscv ( reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -800,31 +745,34 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; - reg CfuPlugin_joinException_valid; - wire [3:0] CfuPlugin_joinException_payload_code; - wire [31:0] CfuPlugin_joinException_payload_badAddr; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_61; - wire [3:0] _zz_62; - wire _zz_63; - wire _zz_64; - wire _zz_65; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -847,16 +795,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_66; - wire _zz_67; - wire _zz_68; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_69; - wire _zz_70; - reg _zz_71; - wire _zz_72; - reg _zz_73; - reg [31:0] _zz_74; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -864,22 +814,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_75; - reg [18:0] _zz_76; - wire _zz_77; - reg [10:0] _zz_78; - wire _zz_79; - reg [18:0] _zz_80; - reg _zz_81; - wire _zz_82; - reg [10:0] _zz_83; - wire _zz_84; - reg [18:0] _zz_85; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -887,7 +844,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_86; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -895,23 +852,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -919,40 +881,56 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_87; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_88; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_89; - reg [31:0] _zz_90; - wire _zz_91; - reg [31:0] _zz_92; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [33:0] _zz_93; - wire _zz_94; - wire _zz_95; - wire _zz_96; - wire _zz_97; - wire _zz_98; - wire `Src1CtrlEnum_defaultEncoding_type _zz_99; - wire `AluCtrlEnum_defaultEncoding_type _zz_100; - wire `Src2CtrlEnum_defaultEncoding_type _zz_101; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_102; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_103; - wire `BranchCtrlEnum_defaultEncoding_type _zz_104; - wire `EnvCtrlEnum_defaultEncoding_type _zz_105; - wire `Input2Kind_defaultEncoding_type _zz_106; + wire when_DBusCachedPlugin_l484; + wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -960,53 +938,72 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_107; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_108; - reg [31:0] _zz_109; - wire _zz_110; - reg [19:0] _zz_111; - wire _zz_112; - reg [19:0] _zz_113; - reg [31:0] _zz_114; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_115; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_116; - reg _zz_117; - reg _zz_118; - reg _zz_119; - reg [4:0] _zz_120; - reg [31:0] _zz_121; - wire _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; - wire _zz_126; - wire _zz_127; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_128; - reg _zz_129; - reg _zz_130; - wire _zz_131; - reg [19:0] _zz_132; - wire _zz_133; - reg [10:0] _zz_134; - wire _zz_135; - reg [18:0] _zz_136; - reg _zz_137; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_138; - reg [19:0] _zz_139; - wire _zz_140; - reg [10:0] _zz_141; - wire _zz_142; - reg [18:0] _zz_143; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; + wire when_BranchPlugin_l296; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1027,9 +1024,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_144; - wire _zz_145; - wire _zz_146; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1042,72 +1039,69 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_147; - wire _zz_148; - wire [1:0] _zz_149; - wire _zz_150; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - wire execute_CfuPlugin_schedule; - reg execute_CfuPlugin_hold; - reg execute_CfuPlugin_fired; - wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_167; - reg [23:0] _zz_168; - reg [31:0] _zz_169; - wire memory_CfuPlugin_rsp_valid; - reg memory_CfuPlugin_rsp_ready; - wire memory_CfuPlugin_rsp_payload_response_ok; - wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_s2mPipe_rValid; - reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1115,6 +1109,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1127,242 +1123,402 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_170; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_171; - wire _zz_172; - wire _zz_173; - reg [32:0] _zz_174; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_175; - wire [31:0] _zz_176; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire CfuPlugin_bus_cmd_fire; + wire when_CfuPlugin_l171; + wire when_CfuPlugin_l175; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_CfuPlugin_bus_cmd_payload_inputs_1; + reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1; + reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + wire CfuPlugin_bus_rsp_rsp_valid; + reg CfuPlugin_bus_rsp_rsp_ready; + wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_rValid; + reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; + wire when_CfuPlugin_l208; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_when_GenCoreDefault_l367; + wire when_GenCoreDefault_l367; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_when_GenCoreDefault_l367_1; + wire when_GenCoreDefault_l367_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_when_GenCoreDefault_l367_2; + wire when_GenCoreDefault_l367_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_when_GenCoreDefault_l367_3; + wire when_GenCoreDefault_l367_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_when_GenCoreDefault_l367_4; + wire when_GenCoreDefault_l367_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_when_GenCoreDefault_l367_5; + wire when_GenCoreDefault_l367_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_when_GenCoreDefault_l367_6; + wire when_GenCoreDefault_l367_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_when_GenCoreDefault_l367_7; + wire when_GenCoreDefault_l367_7; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + wire when_Pipeline_l124_44; + reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_45; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_46; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_47; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_48; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_49; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_50; reg decode_to_execute_CSR_READ_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_51; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_52; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_53; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_54; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_55; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_57; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_60; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_61; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_62; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_63; reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; + reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; + reg execute_CsrPlugin_csr_4032; + wire when_CsrPlugin_l1264_24; reg execute_CsrPlugin_csr_2820; + wire when_CsrPlugin_l1264_25; reg execute_CsrPlugin_csr_2821; + wire when_CsrPlugin_l1264_26; reg execute_CsrPlugin_csr_2822; + wire when_CsrPlugin_l1264_27; reg execute_CsrPlugin_csr_2823; + wire when_CsrPlugin_l1264_28; reg execute_CsrPlugin_csr_2824; + wire when_CsrPlugin_l1264_29; reg execute_CsrPlugin_csr_2825; + wire when_CsrPlugin_l1264_30; reg execute_CsrPlugin_csr_2826; + wire when_CsrPlugin_l1264_31; reg execute_CsrPlugin_csr_2827; + wire when_CsrPlugin_l1264_32; reg execute_CsrPlugin_csr_2828; + wire when_CsrPlugin_l1264_33; reg execute_CsrPlugin_csr_2829; + wire when_CsrPlugin_l1264_34; reg execute_CsrPlugin_csr_2830; + wire when_CsrPlugin_l1264_35; reg execute_CsrPlugin_csr_2831; + wire when_CsrPlugin_l1264_36; reg execute_CsrPlugin_csr_2832; + wire when_CsrPlugin_l1264_37; reg execute_CsrPlugin_csr_2833; + wire when_CsrPlugin_l1264_38; reg execute_CsrPlugin_csr_2834; + wire when_CsrPlugin_l1264_39; reg execute_CsrPlugin_csr_2835; - reg execute_CsrPlugin_csr_3008; - reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [31:0] _zz_199; - reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; - reg [2:0] _zz_208; - reg _zz_209; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_29; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_30; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_31; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_32; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_33; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_34; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_35; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_36; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_37; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_38; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_39; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_40; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - reg _zz_216; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8_string; - reg [39:0] _zz_9_string; - reg [39:0] _zz_10_string; - reg [31:0] _zz_11_string; - reg [31:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_15_string; - reg [71:0] _zz_16_string; - reg [71:0] _zz_17_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_18_string; - reg [39:0] _zz_19_string; - reg [39:0] _zz_20_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_21_string; - reg [23:0] _zz_22_string; - reg [23:0] _zz_23_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_24_string; - reg [63:0] _zz_25_string; - reg [63:0] _zz_26_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_27_string; - reg [95:0] _zz_28_string; - reg [95:0] _zz_29_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_32_string; + reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_36_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_39_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_40_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_42_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_43_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_44_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_45_string; - reg [39:0] _zz_49_string; - reg [39:0] _zz_50_string; - reg [31:0] _zz_51_string; - reg [71:0] _zz_52_string; - reg [39:0] _zz_53_string; - reg [23:0] _zz_54_string; - reg [63:0] _zz_55_string; - reg [95:0] _zz_56_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_58_string; - reg [95:0] _zz_99_string; - reg [63:0] _zz_100_string; - reg [23:0] _zz_101_string; - reg [39:0] _zz_102_string; - reg [71:0] _zz_103_string; - reg [31:0] _zz_104_string; - reg [39:0] _zz_105_string; - reg [39:0] _zz_106_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1378,473 +1534,437 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_248 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_249 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_250 = 1'b1; - assign _zz_251 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_252 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_254 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_255 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_256 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_257 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_260 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_264 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_265 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_266 = (1'b0 || (! 1'b1)); - assign _zz_267 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_268 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_270 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_271 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_272 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_273 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_274 = execute_INSTRUCTION[13 : 12]; - assign _zz_275 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_276 = (! memory_arbitration_isStuck); - assign _zz_277 = (iBus_cmd_valid || (_zz_208 != 3'b000)); - assign _zz_278 = (_zz_244 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_280 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_281 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_282 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_285 = execute_INSTRUCTION[13]; - assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); - assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); - assign _zz_289 = 52'h0; - assign _zz_290 = {1'b0,memory_MUL_LL}; - assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; - assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; - assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; - assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_297 = _zz_296[31 : 0]; - assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_299 = _zz_93[33 : 33]; - assign _zz_300 = _zz_93[32 : 32]; - assign _zz_301 = _zz_93[31 : 31]; - assign _zz_302 = _zz_93[30 : 30]; - assign _zz_303 = _zz_93[28 : 28]; - assign _zz_304 = _zz_93[25 : 25]; - assign _zz_305 = _zz_93[17 : 17]; - assign _zz_306 = _zz_93[16 : 16]; - assign _zz_307 = _zz_93[13 : 13]; - assign _zz_308 = _zz_93[12 : 12]; - assign _zz_309 = _zz_93[11 : 11]; - assign _zz_310 = _zz_93[15 : 15]; - assign _zz_311 = _zz_93[5 : 5]; - assign _zz_312 = _zz_93[3 : 3]; - assign _zz_313 = _zz_93[20 : 20]; - assign _zz_314 = _zz_93[10 : 10]; - assign _zz_315 = _zz_93[4 : 4]; - assign _zz_316 = _zz_93[0 : 0]; - assign _zz_317 = (_zz_61 - 4'b0001); - assign _zz_318 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_319 = {29'd0, _zz_318}; - assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_321 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_324 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_325 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_326 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_328 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_329 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_330 = execute_SRC_LESS; - assign _zz_331 = 3'b100; - assign _zz_332 = execute_INSTRUCTION[19 : 15]; - assign _zz_333 = execute_INSTRUCTION[31 : 20]; - assign _zz_334 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_335 = ($signed(_zz_336) + $signed(_zz_339)); - assign _zz_336 = ($signed(_zz_337) + $signed(_zz_338)); - assign _zz_337 = execute_SRC1; - assign _zz_338 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_339 = (execute_SRC_USE_SUB_LESS ? _zz_340 : _zz_341); - assign _zz_340 = 32'h00000001; - assign _zz_341 = 32'h0; - assign _zz_342 = execute_INSTRUCTION[31 : 20]; - assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_345 = {_zz_132,execute_INSTRUCTION[31 : 20]}; - assign _zz_346 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_347 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_348 = execute_INSTRUCTION[31 : 20]; - assign _zz_349 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_351 = 3'b100; - assign _zz_352 = (_zz_147 & (~ _zz_353)); - assign _zz_353 = (_zz_147 - 2'b01); - assign _zz_354 = (_zz_149 & (~ _zz_355)); - assign _zz_355 = (_zz_149 - 2'b01); - assign _zz_356 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_357 = execute_INSTRUCTION[31 : 24]; - assign _zz_358 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_359 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_360 = writeBack_MUL_LOW[31 : 0]; - assign _zz_361 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_362 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_363 = {5'd0, _zz_362}; - assign _zz_364 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_365 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_366 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_367 = {_zz_170,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_368 = _zz_369; - assign _zz_369 = _zz_370; - assign _zz_370 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_171) : _zz_171)} + _zz_372); - assign _zz_371 = memory_DivPlugin_div_needRevert; - assign _zz_372 = {32'd0, _zz_371}; - assign _zz_373 = _zz_173; - assign _zz_374 = {32'd0, _zz_373}; - assign _zz_375 = _zz_172; - assign _zz_376 = {31'd0, _zz_375}; - assign _zz_377 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_378 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_380 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_381 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_382 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_383 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_384 = (iBus_cmd_payload_address >>> 5); - assign _zz_385 = 1'b1; - assign _zz_386 = 1'b1; - assign _zz_387 = {_zz_65,_zz_64}; - assign _zz_388 = 32'h0000106f; - assign _zz_389 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_390 = 32'h00001073; - assign _zz_391 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_392 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_393 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_394) == 32'h00000003),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; - assign _zz_394 = 32'h0000207f; - assign _zz_395 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_396 = 32'h00000003; - assign _zz_397 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_398 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_399 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_400) == 32'h00005013),{(_zz_401 == _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; - assign _zz_400 = 32'hbc00707f; - assign _zz_401 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_402 = 32'h00001013; - assign _zz_403 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_405 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_406 = decode_INSTRUCTION[31]; - assign _zz_407 = decode_INSTRUCTION[31]; - assign _zz_408 = decode_INSTRUCTION[7]; - assign _zz_409 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_410 = 32'h02004020; - assign _zz_411 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_412 = (_zz_97 != 1'b0); - assign _zz_413 = (((decode_INSTRUCTION & _zz_415) == 32'h00000050) != 1'b0); - assign _zz_414 = {((_zz_416 == _zz_417) != 1'b0),{({_zz_418,_zz_419} != 2'b00),{(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}}}; - assign _zz_415 = 32'h00203050; - assign _zz_416 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_417 = 32'h00000050; - assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00001050); - assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00002050); - assign _zz_420 = {_zz_96,(_zz_427 == _zz_428)}; - assign _zz_421 = 2'b00; - assign _zz_422 = ((_zz_429 == _zz_430) != 1'b0); - assign _zz_423 = ({_zz_431,_zz_432} != 2'b00); - assign _zz_424 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; - assign _zz_425 = 32'h00001050; - assign _zz_426 = 32'h00002050; - assign _zz_427 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_428 = 32'h00000004; - assign _zz_429 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_430 = 32'h00000040; - assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h00005010); - assign _zz_432 = ((decode_INSTRUCTION & _zz_439) == 32'h00005020); - assign _zz_433 = {(_zz_440 == _zz_441),{_zz_442,_zz_443}}; - assign _zz_434 = 3'b000; - assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); - assign _zz_436 = (_zz_446 != 1'b0); - assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; - assign _zz_438 = 32'h00007034; - assign _zz_439 = 32'h02007064; - assign _zz_440 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_441 = 32'h40001010; - assign _zz_442 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_443 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_445 = 32'h00000024; - assign _zz_446 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_447 = ((decode_INSTRUCTION & _zz_452) == 32'h00002000); - assign _zz_448 = 1'b0; - assign _zz_449 = ({_zz_453,_zz_454} != 2'b00); - assign _zz_450 = (_zz_455 != 1'b0); - assign _zz_451 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; - assign _zz_452 = 32'h00003000; - assign _zz_453 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_454 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_455 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_456 = {_zz_97,{_zz_461,_zz_462}}; - assign _zz_457 = 3'b000; - assign _zz_458 = ({_zz_463,{_zz_464,_zz_465}} != 5'h0); - assign _zz_459 = (_zz_466 != 1'b0); - assign _zz_460 = {(_zz_467 != _zz_468),{_zz_469,{_zz_470,_zz_471}}}; - assign _zz_461 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); - assign _zz_462 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); - assign _zz_463 = ((decode_INSTRUCTION & _zz_474) == 32'h00002040); - assign _zz_464 = (_zz_475 == _zz_476); - assign _zz_465 = {_zz_477,{_zz_478,_zz_479}}; - assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000020); - assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; - assign _zz_468 = 6'h0; - assign _zz_469 = ({_zz_484,_zz_485} != 5'h0); - assign _zz_470 = (_zz_486 != _zz_487); - assign _zz_471 = {_zz_488,{_zz_489,_zz_490}}; - assign _zz_472 = 32'h00000034; - assign _zz_473 = 32'h00000064; - assign _zz_474 = 32'h00002040; - assign _zz_475 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_476 = 32'h00001040; - assign _zz_477 = ((decode_INSTRUCTION & _zz_491) == 32'h00000040); - assign _zz_478 = (_zz_492 == _zz_493); - assign _zz_479 = (_zz_494 == _zz_495); - assign _zz_480 = 32'h00000020; - assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00000008); - assign _zz_482 = (_zz_497 == _zz_498); - assign _zz_483 = {_zz_95,{_zz_499,_zz_500}}; - assign _zz_484 = _zz_95; - assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; - assign _zz_486 = {_zz_96,{_zz_504,_zz_505}}; - assign _zz_487 = 6'h0; - assign _zz_488 = ({_zz_506,_zz_507} != 2'b00); - assign _zz_489 = (_zz_508 != _zz_509); - assign _zz_490 = {_zz_510,{_zz_511,_zz_512}}; - assign _zz_491 = 32'h00000050; - assign _zz_492 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_493 = 32'h00000040; - assign _zz_494 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_495 = 32'h0; - assign _zz_496 = 32'h00000008; - assign _zz_497 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_498 = 32'h00000040; - assign _zz_499 = (_zz_513 == _zz_514); - assign _zz_500 = {_zz_515,_zz_516}; - assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00002010); - assign _zz_502 = (_zz_518 == _zz_519); - assign _zz_503 = {_zz_520,_zz_521}; - assign _zz_504 = (_zz_522 == _zz_523); - assign _zz_505 = {_zz_524,{_zz_525,_zz_526}}; - assign _zz_506 = _zz_95; - assign _zz_507 = (_zz_527 == _zz_528); - assign _zz_508 = {_zz_95,_zz_529}; - assign _zz_509 = 2'b00; - assign _zz_510 = (_zz_530 != 1'b0); - assign _zz_511 = (_zz_531 != _zz_532); - assign _zz_512 = {_zz_533,{_zz_534,_zz_535}}; - assign _zz_513 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_514 = 32'h00004020; - assign _zz_515 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); - assign _zz_516 = ((decode_INSTRUCTION & _zz_537) == 32'h00000020); - assign _zz_517 = 32'h00002030; - assign _zz_518 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_519 = 32'h00000010; - assign _zz_520 = ((decode_INSTRUCTION & _zz_538) == 32'h00002020); - assign _zz_521 = ((decode_INSTRUCTION & _zz_539) == 32'h00000020); - assign _zz_522 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_523 = 32'h00001010; - assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00002010); - assign _zz_525 = (_zz_541 == _zz_542); - assign _zz_526 = {_zz_543,_zz_544}; - assign _zz_527 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_528 = 32'h00000020; - assign _zz_529 = ((decode_INSTRUCTION & _zz_545) == 32'h0); - assign _zz_530 = ((decode_INSTRUCTION & _zz_546) == 32'h00004010); - assign _zz_531 = (_zz_547 == _zz_548); - assign _zz_532 = 1'b0; - assign _zz_533 = ({_zz_549,_zz_550} != 4'b0000); - assign _zz_534 = (_zz_551 != _zz_552); - assign _zz_535 = {_zz_553,{_zz_554,_zz_555}}; - assign _zz_536 = 32'h00000030; - assign _zz_537 = 32'h02000020; - assign _zz_538 = 32'h02002060; - assign _zz_539 = 32'h02003020; - assign _zz_540 = 32'h00002010; - assign _zz_541 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_542 = 32'h00000010; - assign _zz_543 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_544 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_545 = 32'h00000020; - assign _zz_546 = 32'h00004014; - assign _zz_547 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_548 = 32'h00002010; - assign _zz_549 = ((decode_INSTRUCTION & _zz_556) == 32'h0); - assign _zz_550 = {(_zz_557 == _zz_558),{_zz_559,_zz_560}}; - assign _zz_551 = ((decode_INSTRUCTION & _zz_561) == 32'h0); - assign _zz_552 = 1'b0; - assign _zz_553 = ({_zz_562,{_zz_563,_zz_564}} != 3'b000); - assign _zz_554 = ({_zz_565,_zz_566} != 2'b00); - assign _zz_555 = {(_zz_567 != _zz_568),(_zz_569 != _zz_570)}; - assign _zz_556 = 32'h00000044; - assign _zz_557 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_558 = 32'h0; - assign _zz_559 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_560 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_561 = 32'h00000058; - assign _zz_562 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_563 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); - assign _zz_564 = ((decode_INSTRUCTION & _zz_572) == 32'h40000030); - assign _zz_565 = ((decode_INSTRUCTION & _zz_573) == 32'h00000004); - assign _zz_566 = _zz_94; - assign _zz_567 = {(_zz_574 == _zz_575),_zz_94}; - assign _zz_568 = 2'b00; - assign _zz_569 = ((decode_INSTRUCTION & _zz_576) == 32'h00001004); - assign _zz_570 = 1'b0; - assign _zz_571 = 32'h00002014; - assign _zz_572 = 32'h40000034; - assign _zz_573 = 32'h00000014; - assign _zz_574 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_575 = 32'h00000004; - assign _zz_576 = 32'h00005054; - assign _zz_577 = execute_INSTRUCTION[31]; - assign _zz_578 = execute_INSTRUCTION[31]; - assign _zz_579 = execute_INSTRUCTION[7]; - assign _zz_580 = 32'h0; - always @ (posedge clk) begin - if(_zz_385) begin - _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_386) begin - _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_48) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h00203050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00002040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79}} != 6'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00002040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h00001040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75) == 32'h00000008); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = 6'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = (decode_INSTRUCTION & 32'h00400040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = 32'h00000008; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = 32'h00004020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85) == 32'h00000010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h00002030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98) == 32'h00002020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129) == 32'h00004010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139} != 4'b0000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = 32'h00000030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h02000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = 32'h02002060; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02003020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = 32'h00004014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = 32'h00000044; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00000058; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h40000030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165) == 32'h00001004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = 32'h00002014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h40000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 32'h00000014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = 32'h00000004; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 32'h00005054; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_41 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_217 ), //i - .io_cpu_prefetch_isValid (_zz_218 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_219 ), //i - .io_cpu_fetch_isStuck (_zz_220 ), //i - .io_cpu_fetch_isRemoved (_zz_221 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_222 ), //i - .io_cpu_decode_isStuck (_zz_223 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_224 ), //i - .io_cpu_fill_valid (_zz_225 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_226 ), //i - .io_cpu_execute_address (_zz_227[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_88[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_228 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_229[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_230 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_231 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_232 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_233[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_234 ), //i - .io_cpu_writeBack_fence_SR (_zz_235 ), //i - .io_cpu_writeBack_fence_SO (_zz_236 ), //i - .io_cpu_writeBack_fence_SI (_zz_237 ), //i - .io_cpu_writeBack_fence_PW (_zz_238 ), //i - .io_cpu_writeBack_fence_PR (_zz_239 ), //i - .io_cpu_writeBack_fence_PO (_zz_240 ), //i - .io_cpu_writeBack_fence_PI (_zz_241 ), //i - .io_cpu_writeBack_fence_FM (_zz_242[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_243 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_244 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_387) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) 2'b00 : begin - _zz_247 = DBusCachedPlugin_redoBranch_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_247 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_247 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + end + 2'b01 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + end + 2'b10 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; end default : begin - _zz_247 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end @@ -1852,808 +1972,825 @@ module VexRiscv ( `ifndef SYNTHESIS always @(*) begin case(decode_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_1) - `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; - default : _zz_1_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; - default : _zz_2_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; - default : _zz_3_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; - default : _zz_8_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_9) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; - default : _zz_9_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_10) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; - default : _zz_10_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_11) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; - default : _zz_11_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_12) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; - default : _zz_12_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_16) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; - default : _zz_16_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_17) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; - default : _zz_17_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_19) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; - default : _zz_19_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_20) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; - default : _zz_20_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_25) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; - default : _zz_25_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_26) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; - default : _zz_26_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_28) - `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; - default : _zz_28_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_29) - `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; - default : _zz_29_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_32) - `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; - default : _zz_32_string = "?????"; + case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_36) - `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; - default : _zz_36_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_39) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; - default : _zz_39_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_40) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; - default : _zz_40_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_42) - `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; - default : _zz_42_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_43) - `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; - default : _zz_43_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_44) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; - default : _zz_44_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_45) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; - default : _zz_45_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_49) - `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; - default : _zz_49_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_50) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; - default : _zz_50_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_52) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; - default : _zz_52_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_53) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; - default : _zz_53_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_54) - `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; - default : _zz_54_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_55) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; - default : _zz_55_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_56) - `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; - default : _zz_56_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_58) - `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; - default : _zz_58_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_99) - `Src1CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_99_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99_string = "URS1 "; - default : _zz_99_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_100) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_100_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_100_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_100_string = "BITWISE "; - default : _zz_100_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_101) - `Src2CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_101_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_101_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_101_string = "PC "; - default : _zz_101_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_102) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_102_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_102_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_102_string = "AND_1"; - default : _zz_102_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_103) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_103_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_103_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_103_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_103_string = "SRA_1 "; - default : _zz_103_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_104) - `BranchCtrlEnum_defaultEncoding_INC : _zz_104_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_104_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_104_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_104_string = "JALR"; - default : _zz_104_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_105) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_105_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_105_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_105_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_105_string = "ECALL"; - default : _zz_105_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_106) - `Input2Kind_defaultEncoding_RS : _zz_106_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_106_string = "IMM_I"; - default : _zz_106_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_297; - assign execute_REGFILE_WRITE_DATA = _zz_108; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_227[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_299[0]; - assign decode_IS_RS1_SIGNED = _zz_300[0]; - assign decode_IS_DIV = _zz_301[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32]; + assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30]; + assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_302[0]; - assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; - assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; - assign _zz_4 = _zz_5; - assign _zz_6 = _zz_7; - assign decode_ENV_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_304[0]; - assign _zz_11 = _zz_12; - assign _zz_13 = _zz_14; - assign decode_SHIFT_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_ALU_BITWISE_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; - assign decode_MEMORY_MANAGMENT = _zz_306[0]; + assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_307[0]; + assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; - assign decode_SRC2_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_ALU_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_SRC1_CTRL = _zz_27; - assign _zz_28 = _zz_29; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; + always @(*) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + always @(*) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2664,42 +2801,25 @@ module VexRiscv ( assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; - always @ (*) begin - _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; - if(memory_arbitration_isStuck)begin - _zz_30 = 1'b0; - end - end - - always @ (*) begin - _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; - if(execute_arbitration_isStuck)begin - _zz_31 = 1'b0; - end - end - - assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33; - assign execute_ENV_CTRL = _zz_34; - assign writeBack_ENV_CTRL = _zz_35; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_130; - assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_310[0]; - assign decode_RS1_USE = _zz_311[0]; - always @ (*) begin - _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_248)begin - _zz_37 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15]; + assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2709,142 +2829,142 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_119)begin - if((_zz_120 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_121; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_123)begin - decode_RS2 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_251)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin - decode_RS2 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_252)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin - decode_RS2 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_119)begin - if((_zz_120 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_121; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_122)begin - decode_RS1 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_251)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_124)begin - decode_RS1 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_252)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_126)begin - decode_RS1 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_38 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_116; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_38 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end - if(_zz_253)begin - _zz_38 = memory_DivPlugin_div_result; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + _zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0; end end - assign memory_SHIFT_CTRL = _zz_39; - assign execute_SHIFT_CTRL = _zz_40; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_41 = execute_PC; - assign execute_SRC2_CTRL = _zz_42; - assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_312[0]; - assign decode_SRC_ADD_ZERO = _zz_313[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_114; - assign execute_SRC1 = _zz_109; - assign execute_ALU_BITWISE_CTRL = _zz_45; - assign _zz_46 = writeBack_INSTRUCTION; - assign _zz_47 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_48 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_48 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_314[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}} != 22'h0); - always @ (*) begin - _zz_57 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_286) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_57 = _zz_360; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_57 = _zz_361; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2856,214 +2976,205 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_315[0]; - assign decode_FLUSH_ALL = _zz_316[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4]; + assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_254)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_255)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_256)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_257)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_58; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_59 = execute_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_59 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_60 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_117 || _zz_118)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_258)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_258)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_243 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_259)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_248)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end - if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + if(when_CfuPlugin_l175) begin execute_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_260)begin + if(_zz_when_1) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_260)begin + if(_zz_when_1) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if((! memory_CfuPlugin_rsp_valid))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_253)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + if(when_CfuPlugin_l208) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushNext = 1'b0; + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_262)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3072,51 +3183,53 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_262)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_259)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_262)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_261)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_262)begin - case(_zz_263) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3129,59 +3242,65 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_62 = (_zz_61 & (~ _zz_317)); - assign _zz_63 = _zz_62[3]; - assign _zz_64 = (_zz_62[1] || _zz_63); - assign _zz_65 = (_zz_62[2] || _zz_63); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_319); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3189,265 +3308,286 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_66); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_66); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_67); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_68); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_68); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_69; - assign _zz_69 = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_70 = _zz_71; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_72)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_72 = _zz_73; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_74; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_75 = _zz_320[11]; - always @ (*) begin - _zz_76[18] = _zz_75; - _zz_76[17] = _zz_75; - _zz_76[16] = _zz_75; - _zz_76[15] = _zz_75; - _zz_76[14] = _zz_75; - _zz_76[13] = _zz_75; - _zz_76[12] = _zz_75; - _zz_76[11] = _zz_75; - _zz_76[10] = _zz_75; - _zz_76[9] = _zz_75; - _zz_76[8] = _zz_75; - _zz_76[7] = _zz_75; - _zz_76[6] = _zz_75; - _zz_76[5] = _zz_75; - _zz_76[4] = _zz_75; - _zz_76[3] = _zz_75; - _zz_76[2] = _zz_75; - _zz_76[1] = _zz_75; - _zz_76[0] = _zz_75; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_321[31])); - if(_zz_81)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_77 = _zz_322[19]; - always @ (*) begin - _zz_78[10] = _zz_77; - _zz_78[9] = _zz_77; - _zz_78[8] = _zz_77; - _zz_78[7] = _zz_77; - _zz_78[6] = _zz_77; - _zz_78[5] = _zz_77; - _zz_78[4] = _zz_77; - _zz_78[3] = _zz_77; - _zz_78[2] = _zz_77; - _zz_78[1] = _zz_77; - _zz_78[0] = _zz_77; - end - - assign _zz_79 = _zz_323[11]; - always @ (*) begin - _zz_80[18] = _zz_79; - _zz_80[17] = _zz_79; - _zz_80[16] = _zz_79; - _zz_80[15] = _zz_79; - _zz_80[14] = _zz_79; - _zz_80[13] = _zz_79; - _zz_80[12] = _zz_79; - _zz_80[11] = _zz_79; - _zz_80[10] = _zz_79; - _zz_80[9] = _zz_79; - _zz_80[8] = _zz_79; - _zz_80[7] = _zz_79; - _zz_80[6] = _zz_79; - _zz_80[5] = _zz_79; - _zz_80[4] = _zz_79; - _zz_80[3] = _zz_79; - _zz_80[2] = _zz_79; - _zz_80[1] = _zz_79; - _zz_80[0] = _zz_79; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_81 = _zz_324[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_81 = _zz_325[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_82 = _zz_326[19]; - always @ (*) begin - _zz_83[10] = _zz_82; - _zz_83[9] = _zz_82; - _zz_83[8] = _zz_82; - _zz_83[7] = _zz_82; - _zz_83[6] = _zz_82; - _zz_83[5] = _zz_82; - _zz_83[4] = _zz_82; - _zz_83[3] = _zz_82; - _zz_83[2] = _zz_82; - _zz_83[1] = _zz_82; - _zz_83[0] = _zz_82; - end - - assign _zz_84 = _zz_327[11]; - always @ (*) begin - _zz_85[18] = _zz_84; - _zz_85[17] = _zz_84; - _zz_85[16] = _zz_84; - _zz_85[15] = _zz_84; - _zz_85[14] = _zz_84; - _zz_85[13] = _zz_84; - _zz_85[12] = _zz_84; - _zz_85[11] = _zz_84; - _zz_85[10] = _zz_84; - _zz_85[9] = _zz_84; - _zz_85[8] = _zz_84; - _zz_85[7] = _zz_84; - _zz_85[6] = _zz_84; - _zz_85[5] = _zz_84; - _zz_85[4] = _zz_84; - _zz_85[3] = _zz_84; - _zz_85[2] = _zz_84; - _zz_85[1] = _zz_84; - _zz_85[0] = _zz_84; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_406,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_407,_zz_408},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_219; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_224 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_257)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_255)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_225 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_255)begin - _zz_225 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_256)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_254)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_256)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_254)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_217 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_244 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3455,168 +3595,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_227 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_88 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_88 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_88 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_243 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_228 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_229 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_228; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_229; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_230 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_230 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_232 = (CsrPlugin_privilege == 2'b00); - assign _zz_233 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_264)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_264)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_264)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; end - assign _zz_89 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_90[31] = _zz_89; - _zz_90[30] = _zz_89; - _zz_90[29] = _zz_89; - _zz_90[28] = _zz_89; - _zz_90[27] = _zz_89; - _zz_90[26] = _zz_89; - _zz_90[25] = _zz_89; - _zz_90[24] = _zz_89; - _zz_90[23] = _zz_89; - _zz_90[22] = _zz_89; - _zz_90[21] = _zz_89; - _zz_90[20] = _zz_89; - _zz_90[19] = _zz_89; - _zz_90[18] = _zz_89; - _zz_90[17] = _zz_89; - _zz_90[16] = _zz_89; - _zz_90[15] = _zz_89; - _zz_90[14] = _zz_89; - _zz_90[13] = _zz_89; - _zz_90[12] = _zz_89; - _zz_90[11] = _zz_89; - _zz_90[10] = _zz_89; - _zz_90[9] = _zz_89; - _zz_90[8] = _zz_89; - _zz_90[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_91 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_92[31] = _zz_91; - _zz_92[30] = _zz_91; - _zz_92[29] = _zz_91; - _zz_92[28] = _zz_91; - _zz_92[27] = _zz_91; - _zz_92[26] = _zz_91; - _zz_92[25] = _zz_91; - _zz_92[24] = _zz_91; - _zz_92[23] = _zz_91; - _zz_92[22] = _zz_91; - _zz_92[21] = _zz_91; - _zz_92[20] = _zz_91; - _zz_92[19] = _zz_91; - _zz_92[18] = _zz_91; - _zz_92[17] = _zz_91; - _zz_92[16] = _zz_91; - _zz_92[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_284) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_90; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_92; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3635,62 +3786,63 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_94 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_95 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_409 == _zz_410) != 1'b0),{(_zz_411 != 1'b0),{1'b0,{_zz_412,{_zz_413,_zz_414}}}}}}}; - assign _zz_99 = _zz_93[2 : 1]; - assign _zz_56 = _zz_99; - assign _zz_100 = _zz_93[7 : 6]; - assign _zz_55 = _zz_100; - assign _zz_101 = _zz_93[9 : 8]; - assign _zz_54 = _zz_101; - assign _zz_102 = _zz_93[19 : 18]; - assign _zz_53 = _zz_102; - assign _zz_103 = _zz_93[22 : 21]; - assign _zz_52 = _zz_103; - assign _zz_104 = _zz_93[24 : 23]; - assign _zz_51 = _zz_104; - assign _zz_105 = _zz_93[27 : 26]; - assign _zz_50 = _zz_105; - assign _zz_106 = _zz_93[29 : 29]; - assign _zz_49 = _zz_106; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33]; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_245; - assign decode_RegFilePlugin_rs2Data = _zz_246; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_107)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_107)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_107)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3699,355 +3851,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_108 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_108 = {31'd0, _zz_330}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_108 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_109 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_109 = {29'd0, _zz_331}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_109 = {27'd0, _zz_332}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_110 = _zz_333[11]; - always @ (*) begin - _zz_111[19] = _zz_110; - _zz_111[18] = _zz_110; - _zz_111[17] = _zz_110; - _zz_111[16] = _zz_110; - _zz_111[15] = _zz_110; - _zz_111[14] = _zz_110; - _zz_111[13] = _zz_110; - _zz_111[12] = _zz_110; - _zz_111[11] = _zz_110; - _zz_111[10] = _zz_110; - _zz_111[9] = _zz_110; - _zz_111[8] = _zz_110; - _zz_111[7] = _zz_110; - _zz_111[6] = _zz_110; - _zz_111[5] = _zz_110; - _zz_111[4] = _zz_110; - _zz_111[3] = _zz_110; - _zz_111[2] = _zz_110; - _zz_111[1] = _zz_110; - _zz_111[0] = _zz_110; - end - - assign _zz_112 = _zz_334[11]; - always @ (*) begin - _zz_113[19] = _zz_112; - _zz_113[18] = _zz_112; - _zz_113[17] = _zz_112; - _zz_113[16] = _zz_112; - _zz_113[15] = _zz_112; - _zz_113[14] = _zz_112; - _zz_113[13] = _zz_112; - _zz_113[12] = _zz_112; - _zz_113[11] = _zz_112; - _zz_113[10] = _zz_112; - _zz_113[9] = _zz_112; - _zz_113[8] = _zz_112; - _zz_113[7] = _zz_112; - _zz_113[6] = _zz_112; - _zz_113[5] = _zz_112; - _zz_113[4] = _zz_112; - _zz_113[3] = _zz_112; - _zz_113[2] = _zz_112; - _zz_113[1] = _zz_112; - _zz_113[0] = _zz_112; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_114 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_114 = {_zz_111,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_114 = {_zz_113,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_114 = _zz_41; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_335; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_115[0] = execute_SRC1[31]; - _zz_115[1] = execute_SRC1[30]; - _zz_115[2] = execute_SRC1[29]; - _zz_115[3] = execute_SRC1[28]; - _zz_115[4] = execute_SRC1[27]; - _zz_115[5] = execute_SRC1[26]; - _zz_115[6] = execute_SRC1[25]; - _zz_115[7] = execute_SRC1[24]; - _zz_115[8] = execute_SRC1[23]; - _zz_115[9] = execute_SRC1[22]; - _zz_115[10] = execute_SRC1[21]; - _zz_115[11] = execute_SRC1[20]; - _zz_115[12] = execute_SRC1[19]; - _zz_115[13] = execute_SRC1[18]; - _zz_115[14] = execute_SRC1[17]; - _zz_115[15] = execute_SRC1[16]; - _zz_115[16] = execute_SRC1[15]; - _zz_115[17] = execute_SRC1[14]; - _zz_115[18] = execute_SRC1[13]; - _zz_115[19] = execute_SRC1[12]; - _zz_115[20] = execute_SRC1[11]; - _zz_115[21] = execute_SRC1[10]; - _zz_115[22] = execute_SRC1[9]; - _zz_115[23] = execute_SRC1[8]; - _zz_115[24] = execute_SRC1[7]; - _zz_115[25] = execute_SRC1[6]; - _zz_115[26] = execute_SRC1[5]; - _zz_115[27] = execute_SRC1[4]; - _zz_115[28] = execute_SRC1[3]; - _zz_115[29] = execute_SRC1[2]; - _zz_115[30] = execute_SRC1[1]; - _zz_115[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_115 : execute_SRC1); - always @ (*) begin - _zz_116[0] = memory_SHIFT_RIGHT[31]; - _zz_116[1] = memory_SHIFT_RIGHT[30]; - _zz_116[2] = memory_SHIFT_RIGHT[29]; - _zz_116[3] = memory_SHIFT_RIGHT[28]; - _zz_116[4] = memory_SHIFT_RIGHT[27]; - _zz_116[5] = memory_SHIFT_RIGHT[26]; - _zz_116[6] = memory_SHIFT_RIGHT[25]; - _zz_116[7] = memory_SHIFT_RIGHT[24]; - _zz_116[8] = memory_SHIFT_RIGHT[23]; - _zz_116[9] = memory_SHIFT_RIGHT[22]; - _zz_116[10] = memory_SHIFT_RIGHT[21]; - _zz_116[11] = memory_SHIFT_RIGHT[20]; - _zz_116[12] = memory_SHIFT_RIGHT[19]; - _zz_116[13] = memory_SHIFT_RIGHT[18]; - _zz_116[14] = memory_SHIFT_RIGHT[17]; - _zz_116[15] = memory_SHIFT_RIGHT[16]; - _zz_116[16] = memory_SHIFT_RIGHT[15]; - _zz_116[17] = memory_SHIFT_RIGHT[14]; - _zz_116[18] = memory_SHIFT_RIGHT[13]; - _zz_116[19] = memory_SHIFT_RIGHT[12]; - _zz_116[20] = memory_SHIFT_RIGHT[11]; - _zz_116[21] = memory_SHIFT_RIGHT[10]; - _zz_116[22] = memory_SHIFT_RIGHT[9]; - _zz_116[23] = memory_SHIFT_RIGHT[8]; - _zz_116[24] = memory_SHIFT_RIGHT[7]; - _zz_116[25] = memory_SHIFT_RIGHT[6]; - _zz_116[26] = memory_SHIFT_RIGHT[5]; - _zz_116[27] = memory_SHIFT_RIGHT[4]; - _zz_116[28] = memory_SHIFT_RIGHT[3]; - _zz_116[29] = memory_SHIFT_RIGHT[2]; - _zz_116[30] = memory_SHIFT_RIGHT[1]; - _zz_116[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_117 = 1'b0; - if(_zz_265)begin - if(_zz_266)begin - if(_zz_122)begin - _zz_117 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_267)begin - if(_zz_268)begin - if(_zz_124)begin - _zz_117 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_269)begin - if(_zz_270)begin - if(_zz_126)begin - _zz_117 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_117 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_118 = 1'b0; - if(_zz_265)begin - if(_zz_266)begin - if(_zz_123)begin - _zz_118 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_267)begin - if(_zz_268)begin - if(_zz_125)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_269)begin - if(_zz_270)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_118 = 1'b0; - end - end - - assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_128 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_128 == 3'b000)) begin - _zz_129 = execute_BranchPlugin_eq; - end else if((_zz_128 == 3'b001)) begin - _zz_129 = (! execute_BranchPlugin_eq); - end else if((((_zz_128 & 3'b101) == 3'b101))) begin - _zz_129 = (! execute_SRC_LESS); - end else begin - _zz_129 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_130 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_130 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_130 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_130 = _zz_129; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_131 = _zz_342[11]; - always @ (*) begin - _zz_132[19] = _zz_131; - _zz_132[18] = _zz_131; - _zz_132[17] = _zz_131; - _zz_132[16] = _zz_131; - _zz_132[15] = _zz_131; - _zz_132[14] = _zz_131; - _zz_132[13] = _zz_131; - _zz_132[12] = _zz_131; - _zz_132[11] = _zz_131; - _zz_132[10] = _zz_131; - _zz_132[9] = _zz_131; - _zz_132[8] = _zz_131; - _zz_132[7] = _zz_131; - _zz_132[6] = _zz_131; - _zz_132[5] = _zz_131; - _zz_132[4] = _zz_131; - _zz_132[3] = _zz_131; - _zz_132[2] = _zz_131; - _zz_132[1] = _zz_131; - _zz_132[0] = _zz_131; - end - - assign _zz_133 = _zz_343[19]; - always @ (*) begin - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; - end - - assign _zz_135 = _zz_344[11]; - always @ (*) begin - _zz_136[18] = _zz_135; - _zz_136[17] = _zz_135; - _zz_136[16] = _zz_135; - _zz_136[15] = _zz_135; - _zz_136[14] = _zz_135; - _zz_136[13] = _zz_135; - _zz_136[12] = _zz_135; - _zz_136[11] = _zz_135; - _zz_136[10] = _zz_135; - _zz_136[9] = _zz_135; - _zz_136[8] = _zz_135; - _zz_136[7] = _zz_135; - _zz_136[6] = _zz_135; - _zz_136[5] = _zz_135; - _zz_136[4] = _zz_135; - _zz_136[3] = _zz_135; - _zz_136[2] = _zz_135; - _zz_136[1] = _zz_135; - _zz_136[0] = _zz_135; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_137 = (_zz_345[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_137 = _zz_346[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_137 = _zz_347[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_137); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -4056,183 +4231,195 @@ module VexRiscv ( endcase end - assign _zz_138 = _zz_348[11]; - always @ (*) begin - _zz_139[19] = _zz_138; - _zz_139[18] = _zz_138; - _zz_139[17] = _zz_138; - _zz_139[16] = _zz_138; - _zz_139[15] = _zz_138; - _zz_139[14] = _zz_138; - _zz_139[13] = _zz_138; - _zz_139[12] = _zz_138; - _zz_139[11] = _zz_138; - _zz_139[10] = _zz_138; - _zz_139[9] = _zz_138; - _zz_139[8] = _zz_138; - _zz_139[7] = _zz_138; - _zz_139[6] = _zz_138; - _zz_139[5] = _zz_138; - _zz_139[4] = _zz_138; - _zz_139[3] = _zz_138; - _zz_139[2] = _zz_138; - _zz_139[1] = _zz_138; - _zz_139[0] = _zz_138; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_577,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_578,_zz_579},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_351}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_140 = _zz_349[19]; - always @ (*) begin - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; - end - - assign _zz_142 = _zz_350[11]; - always @ (*) begin - _zz_143[18] = _zz_142; - _zz_143[17] = _zz_142; - _zz_143[16] = _zz_142; - _zz_143[15] = _zz_142; - _zz_143[14] = _zz_142; - _zz_143[13] = _zz_142; - _zz_143[12] = _zz_142; - _zz_143[11] = _zz_142; - _zz_143[10] = _zz_142; - _zz_143[9] = _zz_142; - _zz_143[8] = _zz_142; - _zz_143[7] = _zz_142; - _zz_143[6] = _zz_142; - _zz_143[5] = _zz_142; - _zz_143[4] = _zz_142; - _zz_143[3] = _zz_142; - _zz_143[2] = _zz_142; - _zz_143[1] = _zz_142; - _zz_143[0] = _zz_142; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; - always @ (*) begin + always @(*) begin BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); - if(1'b0)begin + if(when_BranchPlugin_l296) begin BranchPlugin_branchExceptionPort_valid = 1'b0; end end assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign when_BranchPlugin_l296 = 1'b0; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_144 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_145 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_146 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_148 = _zz_352[0]; - assign _zz_149 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_150 = _zz_354[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_258)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_260)begin + if(_zz_when_1) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4243,8 +4430,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4254,199 +4441,208 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_csr_2820) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2821) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_csr_2822) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2823) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_csr_2824) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2825) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_csr_2826) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2827) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_csr_2828) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2829) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_csr_2830) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2831) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_csr_2832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2833) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_2834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_2835) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_271)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_272)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_273)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_272)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_273)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4459,106 +4655,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_271)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_271)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_285) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); - assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_356; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; - assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_167 = _zz_357[7]; - always @ (*) begin - _zz_168[23] = _zz_167; - _zz_168[22] = _zz_167; - _zz_168[21] = _zz_167; - _zz_168[20] = _zz_167; - _zz_168[19] = _zz_167; - _zz_168[18] = _zz_167; - _zz_168[17] = _zz_167; - _zz_168[16] = _zz_167; - _zz_168[15] = _zz_167; - _zz_168[14] = _zz_167; - _zz_168[13] = _zz_167; - _zz_168[12] = _zz_167; - _zz_168[11] = _zz_167; - _zz_168[10] = _zz_167; - _zz_168[9] = _zz_167; - _zz_168[8] = _zz_167; - _zz_168[7] = _zz_167; - _zz_168[6] = _zz_167; - _zz_168[5] = _zz_167; - _zz_168[4] = _zz_167; - _zz_168[3] = _zz_167; - _zz_168[2] = _zz_167; - _zz_168[1] = _zz_167; - _zz_168[0] = _zz_167; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : begin - _zz_169 = execute_RS2; - end - default : begin - _zz_169 = {_zz_168,execute_INSTRUCTION[31 : 24]}; - end - endcase - end - - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_169; - assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); - assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); - assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); - assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); - always @ (*) begin - CfuPlugin_joinException_valid = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if(memory_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); - end - end - end - - assign CfuPlugin_joinException_payload_code = 4'b1111; - assign CfuPlugin_joinException_payload_badAddr = 32'h0; - always @ (*) begin - memory_CfuPlugin_rsp_ready = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); - end - end - assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_274) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4571,8 +4710,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_274) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4591,82 +4730,222 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_358) + $signed(_zz_359)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_253)begin - if(_zz_275)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_276)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_363); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_170 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_170[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_364); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_365 : _zz_366); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_367[31:0]; - assign _zz_171 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_172 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_173 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_174[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_174[31 : 0] = execute_RS1; - end - - assign _zz_176 = (_zz_175 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_176 != 32'h0); - assign _zz_29 = decode_SRC1_CTRL; - assign _zz_27 = _zz_56; - assign _zz_43 = decode_to_execute_SRC1_CTRL; - assign _zz_26 = decode_ALU_CTRL; - assign _zz_24 = _zz_55; - assign _zz_44 = decode_to_execute_ALU_CTRL; - assign _zz_23 = decode_SRC2_CTRL; - assign _zz_21 = _zz_54; - assign _zz_42 = decode_to_execute_SRC2_CTRL; - assign _zz_20 = decode_ALU_BITWISE_CTRL; - assign _zz_18 = _zz_53; - assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_17 = decode_SHIFT_CTRL; - assign _zz_14 = execute_SHIFT_CTRL; - assign _zz_15 = _zz_52; - assign _zz_40 = decode_to_execute_SHIFT_CTRL; - assign _zz_39 = execute_to_memory_SHIFT_CTRL; - assign _zz_12 = decode_BRANCH_CTRL; - assign _zz_58 = _zz_51; - assign _zz_36 = decode_to_execute_BRANCH_CTRL; - assign _zz_10 = decode_ENV_CTRL; - assign _zz_7 = execute_ENV_CTRL; - assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_50; - assign _zz_34 = decode_to_execute_ENV_CTRL; - assign _zz_33 = execute_to_memory_ENV_CTRL; - assign _zz_35 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_49; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready); + assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)); + assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + end + + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2; + end + default : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @(*) begin + CfuPlugin_bus_rsp_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); + assign when_GenCoreDefault_l367 = _zz_when_GenCoreDefault_l367[0]; + assign when_GenCoreDefault_l367_1 = _zz_when_GenCoreDefault_l367_1[0]; + assign when_GenCoreDefault_l367_2 = _zz_when_GenCoreDefault_l367_2[0]; + assign when_GenCoreDefault_l367_3 = _zz_when_GenCoreDefault_l367_3[0]; + assign when_GenCoreDefault_l367_4 = _zz_when_GenCoreDefault_l367_4[0]; + assign when_GenCoreDefault_l367_5 = _zz_when_GenCoreDefault_l367_5[0]; + assign when_GenCoreDefault_l367_6 = _zz_when_GenCoreDefault_l367_6[0]; + assign when_GenCoreDefault_l367_7 = _zz_when_GenCoreDefault_l367_7[0]; + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4687,296 +4966,345 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_177 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_177[12 : 0] = 13'h1000; - _zz_177[25 : 20] = 6'h20; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_28 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_29 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_30 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_31 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_32 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_33 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_34 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_35 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_36 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_37 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_38 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_39 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[13 : 0] = 14'h2000; + _zz_CsrPlugin_csrMapping_readDataInit_10[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_178 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_178[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_179 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_179[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_180[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_181[31 : 30] = CsrPlugin_misa_base; - _zz_181[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_14[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_182[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_182[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_182[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_15[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_183[11 : 11] = CsrPlugin_mip_MEIP; - _zz_183[7 : 7] = CsrPlugin_mip_MTIP; - _zz_183[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_184[11 : 11] = CsrPlugin_mie_MEIE; - _zz_184[7 : 7] = CsrPlugin_mie_MTIE; - _zz_184[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_185[31 : 2] = CsrPlugin_mtvec_base; - _zz_185[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_186 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_186[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_187 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_187[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_188 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_188[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_188[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_21[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_189 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_189[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_190 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_191 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_192 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_193 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_194 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_195 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_28[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_196 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_29 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_29[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_197 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_30 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_30[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_198 = 32'h0; - if(execute_CsrPlugin_csr_2820)begin - _zz_198[31 : 0] = _zz_151; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_31 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_31[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_199 = 32'h0; - if(execute_CsrPlugin_csr_2822)begin - _zz_199[31 : 0] = _zz_153; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_32 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_32[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - always @ (*) begin - _zz_200 = 32'h0; - if(execute_CsrPlugin_csr_2824)begin - _zz_200[31 : 0] = _zz_155; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_33 = 32'h0; + if(execute_CsrPlugin_csr_2820) begin + _zz_CsrPlugin_csrMapping_readDataInit_33[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; end end - always @ (*) begin - _zz_201 = 32'h0; - if(execute_CsrPlugin_csr_2826)begin - _zz_201[31 : 0] = _zz_157; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_34 = 32'h0; + if(execute_CsrPlugin_csr_2822) begin + _zz_CsrPlugin_csrMapping_readDataInit_34[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; end end - always @ (*) begin - _zz_202 = 32'h0; - if(execute_CsrPlugin_csr_2828)begin - _zz_202[31 : 0] = _zz_159; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_35 = 32'h0; + if(execute_CsrPlugin_csr_2824) begin + _zz_CsrPlugin_csrMapping_readDataInit_35[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_4; end end - always @ (*) begin - _zz_203 = 32'h0; - if(execute_CsrPlugin_csr_2830)begin - _zz_203[31 : 0] = _zz_161; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_36 = 32'h0; + if(execute_CsrPlugin_csr_2826) begin + _zz_CsrPlugin_csrMapping_readDataInit_36[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_5; end end - always @ (*) begin - _zz_204 = 32'h0; - if(execute_CsrPlugin_csr_2832)begin - _zz_204[31 : 0] = _zz_163; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_37 = 32'h0; + if(execute_CsrPlugin_csr_2828) begin + _zz_CsrPlugin_csrMapping_readDataInit_37[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_6; end end - always @ (*) begin - _zz_205 = 32'h0; - if(execute_CsrPlugin_csr_2834)begin - _zz_205[31 : 0] = _zz_165; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_38 = 32'h0; + if(execute_CsrPlugin_csr_2830) begin + _zz_CsrPlugin_csrMapping_readDataInit_38[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_7; end end - always @ (*) begin - _zz_206 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_206[31 : 0] = _zz_175; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_39 = 32'h0; + if(execute_CsrPlugin_csr_2832) begin + _zz_CsrPlugin_csrMapping_readDataInit_39[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_8; end end - always @ (*) begin - _zz_207 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_207[31 : 0] = _zz_176; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_40 = 32'h0; + if(execute_CsrPlugin_csr_2834) begin + _zz_CsrPlugin_csrMapping_readDataInit_40[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_9; end end - assign execute_CsrPlugin_readData = (((((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_580 | _zz_181) | (_zz_182 | _zz_183))) | (((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191)))) | ((((_zz_192 | _zz_193) | (_zz_194 | _zz_195)) | ((_zz_196 | _zz_197) | (_zz_198 | _zz_199))) | (((_zz_200 | _zz_201) | (_zz_202 | _zz_203)) | ((_zz_204 | _zz_205) | (_zz_206 | _zz_207))))); - assign iBusWishbone_ADR = {_zz_384,_zz_208}; - assign iBusWishbone_CTI = ((_zz_208 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | (_zz_CsrPlugin_csrMapping_readDataInit_12 | _zz_CsrPlugin_csrMapping_readDataInit_13)) | ((_zz_CsrPlugin_csrMapping_readDataInit_41 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26) | (_zz_CsrPlugin_csrMapping_readDataInit_27 | _zz_CsrPlugin_csrMapping_readDataInit_28)) | ((_zz_CsrPlugin_csrMapping_readDataInit_29 | _zz_CsrPlugin_csrMapping_readDataInit_30) | (_zz_CsrPlugin_csrMapping_readDataInit_31 | _zz_CsrPlugin_csrMapping_readDataInit_32))) | (((_zz_CsrPlugin_csrMapping_readDataInit_33 | _zz_CsrPlugin_csrMapping_readDataInit_34) | (_zz_CsrPlugin_csrMapping_readDataInit_35 | _zz_CsrPlugin_csrMapping_readDataInit_36)) | ((_zz_CsrPlugin_csrMapping_readDataInit_37 | _zz_CsrPlugin_csrMapping_readDataInit_38) | (_zz_CsrPlugin_csrMapping_readDataInit_39 | _zz_CsrPlugin_csrMapping_readDataInit_40))))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_277)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_277)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_209; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_215 = (dBus_cmd_payload_length != 3'b000); - assign _zz_211 = dBus_cmd_valid; - assign _zz_213 = dBus_cmd_payload_wr; - assign _zz_214 = (_zz_210 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_212 && (_zz_213 || _zz_214)); - assign dBusWishbone_ADR = ((_zz_215 ? {{dBus_cmd_payload_address[31 : 5],_zz_210},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_215 ? (_zz_214 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_213 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_213; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_212 = (_zz_211 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_211; - assign dBusWishbone_STB = _zz_211; - assign dBus_rsp_valid = _zz_216; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_71 <= 1'b0; - _zz_73 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_86; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_87; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_107 <= 1'b1; - _zz_119 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4996,164 +5324,164 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - memory_DivPlugin_div_counter_value <= 6'h0; - _zz_175 <= 32'h0; + CfuPlugin_bus_rsp_rValid <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_208 <= 3'b000; - _zz_209 <= 1'b0; - _zz_210 <= 3'b000; - _zz_216 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_71 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_69)begin - _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_73 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_73 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_278)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_107 <= 1'b0; - _zz_119 <= (_zz_47 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_279)begin - if(_zz_280)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_281)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_282)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5164,8 +5492,8 @@ module VexRiscv ( end endcase end - if(_zz_262)begin - case(_zz_263) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5175,162 +5503,158 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_146,{_zz_145,_zz_144}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(execute_CfuPlugin_schedule)begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(execute_CfuPlugin_schedule) begin execute_CfuPlugin_hold <= 1'b1; end - if(CfuPlugin_bus_cmd_ready)begin + if(CfuPlugin_bus_cmd_ready) begin execute_CfuPlugin_hold <= 1'b0; end - if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + if(CfuPlugin_bus_cmd_fire) begin execute_CfuPlugin_fired <= 1'b1; end - if((! execute_arbitration_isStuckByOthers))begin + if(when_CfuPlugin_l171) begin execute_CfuPlugin_fired <= 1'b0; end - if(memory_CfuPlugin_rsp_ready)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + if(CfuPlugin_bus_rsp_valid) begin + CfuPlugin_bus_rsp_rValid <= 1'b1; end - if(_zz_283)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + if(CfuPlugin_bus_rsp_rsp_ready) begin + CfuPlugin_bus_rsp_rValid <= 1'b0; end - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + if(when_Pipeline_l124_61) begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_377[0]; - CsrPlugin_mstatus_MIE <= _zz_378[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_380[0]; - CsrPlugin_mie_MTIE <= _zz_381[0]; - CsrPlugin_mie_MSIE <= _zz_382[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_175 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_277)begin - if(iBusWishbone_ACK)begin - _zz_208 <= (_zz_208 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_209 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_211 && _zz_212))begin - _zz_210 <= (_zz_210 + 3'b001); - if(_zz_214)begin - _zz_210 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_216 <= ((_zz_211 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_74 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_278)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_120 <= _zz_46[11 : 7]; - _zz_121 <= _zz_57; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_258)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(_zz_260)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; + if(_zz_when_1) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_279)begin - if(_zz_280)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_281)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_282)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5338,495 +5662,494 @@ module VexRiscv ( end endcase end - if(_zz_152[0])begin - _zz_151 <= (_zz_151 + 32'h00000001); + if(when_MulDivIterativePlugin_l126) begin + memory_DivPlugin_div_done <= 1'b1; end - if(_zz_154[0])begin - _zz_153 <= (_zz_153 + 32'h00000001); + if(when_MulDivIterativePlugin_l126_1) begin + memory_DivPlugin_div_done <= 1'b0; end - if(_zz_156[0])begin - _zz_155 <= (_zz_155 + 32'h00000001); + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; + end + end end - if(_zz_158[0])begin - _zz_157 <= (_zz_157 + 32'h00000001); + if(when_MulDivIterativePlugin_l162) begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end - if(_zz_160[0])begin - _zz_159 <= (_zz_159 + 32'h00000001); + externalInterruptArray_regNext <= externalInterruptArray; + if(CfuPlugin_bus_rsp_ready) begin + CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end - if(_zz_162[0])begin - _zz_161 <= (_zz_161 + 32'h00000001); + if(when_GenCoreDefault_l367) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= (_zz_CsrPlugin_csrMapping_readDataInit_2 + 32'h00000001); end - if(_zz_164[0])begin - _zz_163 <= (_zz_163 + 32'h00000001); + if(when_GenCoreDefault_l367_1) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= (_zz_CsrPlugin_csrMapping_readDataInit_3 + 32'h00000001); end - if(_zz_166[0])begin - _zz_165 <= (_zz_165 + 32'h00000001); + if(when_GenCoreDefault_l367_2) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= (_zz_CsrPlugin_csrMapping_readDataInit_4 + 32'h00000001); end - if(_zz_283)begin - CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + if(when_GenCoreDefault_l367_3) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= (_zz_CsrPlugin_csrMapping_readDataInit_5 + 32'h00000001); end - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_done <= 1'b1; + if(when_GenCoreDefault_l367_4) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= (_zz_CsrPlugin_csrMapping_readDataInit_6 + 32'h00000001); end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + if(when_GenCoreDefault_l367_5) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= (_zz_CsrPlugin_csrMapping_readDataInit_7 + 32'h00000001); end - if(_zz_253)begin - if(_zz_275)begin - memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; - memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_368[31:0]; - end - end + if(when_GenCoreDefault_l367_6) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= (_zz_CsrPlugin_csrMapping_readDataInit_8 + 32'h00000001); end - if(_zz_276)begin - memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_173 ? (~ _zz_174) : _zz_174) + _zz_374); - memory_DivPlugin_rs2 <= ((_zz_172 ? (~ execute_RS2) : execute_RS2) + _zz_376); - memory_DivPlugin_div_needRevert <= ((_zz_173 ^ (_zz_172 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(when_GenCoreDefault_l367_7) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= (_zz_CsrPlugin_csrMapping_readDataInit_9 + 32'h00000001); end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_41; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_8) begin memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_28; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_25; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_22; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_16; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_11; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + end + if(when_Pipeline_l124_45) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_51) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_52) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + if(when_Pipeline_l124_53) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + if(when_Pipeline_l124_54) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_62) begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + end + if(when_Pipeline_l124_63) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if(when_CsrPlugin_l1264_23) begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(when_CsrPlugin_l1264_24) begin execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_25) begin execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_26) begin execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_27) begin execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_28) begin execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_29) begin execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_30) begin execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_31) begin execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_32) begin execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_33) begin execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_34) begin execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_35) begin execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_36) begin execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_37) begin execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_38) begin execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_39) begin execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); - end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_379[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_383[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2820)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2820) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2821) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2822)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2822) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2823) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_1 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2824)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2824) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2825) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2826)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2826) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2827) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2828)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2828) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2829) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2830)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2830) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2831) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2832)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2832) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2833) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2834)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2834) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2835) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -5839,9 +6162,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -5863,6 +6185,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -5878,9 +6201,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -5888,7 +6212,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -5897,99 +6221,81 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_19; - reg [31:0] _zz_20; - reg [21:0] _zz_21; - reg [31:0] _zz_22; - wire _zz_23; - wire _zz_24; - wire _zz_25; - wire _zz_26; - wire _zz_27; - wire _zz_28; - wire _zz_29; - wire [0:0] _zz_30; - wire [0:0] _zz_31; - wire [0:0] _zz_32; - wire [0:0] _zz_33; - wire [0:0] _zz_34; - wire [0:0] _zz_35; - wire [2:0] _zz_36; - wire [2:0] _zz_37; - wire [21:0] _zz_38; - wire [21:0] _zz_39; + reg [20:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [20:0] _zz_ways_0_tags_port; + wire [10:0] _zz_stage0_dataColisions; + wire [10:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; - reg _zz_3; - reg _zz_4; wire haltCpu; reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; + reg [7:0] tagsReadCmd_payload; reg tagsWriteCmd_valid; - reg [1:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; + reg [0:0] tagsWriteCmd_payload_way; + reg [7:0] tagsWriteCmd_payload_address; reg tagsWriteCmd_payload_data_valid; reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; + reg [18:0] tagsWriteCmd_payload_data_address; reg tagsWriteLastCmd_valid; - reg [1:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [7:0] tagsWriteLastCmd_payload_address; reg tagsWriteLastCmd_payload_data_valid; reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; + reg [18:0] tagsWriteLastCmd_payload_data_address; reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; + reg [10:0] dataReadCmd_payload; reg dataWriteCmd_valid; - reg [1:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; + reg [0:0] dataWriteCmd_payload_way; + reg [10:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_5; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_6; - wire _zz_7; + wire [18:0] ways_0_tagsReadRsp_address; + wire [20:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; - wire _zz_8; - wire ways_1_tagsReadRsp_valid; - wire ways_1_tagsReadRsp_error; - wire [19:0] ways_1_tagsReadRsp_address; - wire [21:0] _zz_9; - wire _zz_10; - wire [31:0] ways_1_dataReadRspMem; - wire [31:0] ways_1_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_11; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; - reg [1:0] stage0_dataColisions; - wire [9:0] _zz_12; - wire [3:0] _zz_13; - wire [1:0] stage0_wayInvalidate; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; - wire [1:0] stageA_wayHits; - reg [1:0] _zz_14; - reg [1:0] stageA_wayInvalidate; - reg [1:0] stage0_dataColisions_regNextWhen; - reg [1:0] _zz_15; - wire [9:0] _zz_16; - wire [3:0] _zz_17; - wire [1:0] stageA_dataColisions; + wire [0:0] stageA_wayHits; + wire when_DataCache_l763_2; + reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_stageA_dataColisions; + wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5999,27 +6305,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg stageB_tagsReadRsp_1_valid; - reg stageB_tagsReadRsp_1_error; - reg [19:0] stageB_tagsReadRsp_1_address; + reg [18:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; - reg [31:0] stageB_dataReadRsp_1; - reg [1:0] stageB_wayInvalidate; + wire when_DataCache_l812; + reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; - reg [1:0] stageB_dataColisions; + wire when_DataCache_l812_1; + reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; - reg [1:0] stageB_waysHitsBeforeInvalidate; - wire [1:0] stageB_waysHits; + wire when_DataCache_l812_3; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [8:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -6027,10 +6339,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - reg [1:0] _zz_18; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -6038,432 +6358,359 @@ module DataCache ( reg [2:0] loader_counter_value; wire loader_counter_willOverflowIfInc; wire loader_counter_willOverflow; - reg [1:0] loader_waysAllocator; + reg [0:0] loader_waysAllocator; reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_40; - reg [7:0] _zz_41; - reg [7:0] _zz_42; - reg [7:0] _zz_43; - (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol3 [0:1023]; - reg [7:0] _zz_44; - reg [7:0] _zz_45; - reg [7:0] _zz_46; - reg [7:0] _zz_47; - - assign _zz_23 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_24 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_25 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_26 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_27 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_28 = (! stageB_flusher_hold); - assign _zz_29 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_30 = _zz_6[0 : 0]; - assign _zz_31 = _zz_6[1 : 1]; - assign _zz_32 = _zz_9[0 : 0]; - assign _zz_33 = _zz_9[1 : 1]; - assign _zz_34 = 1'b1; - assign _zz_35 = loader_counter_willIncrement; - assign _zz_36 = {2'd0, _zz_35}; - assign _zz_37 = {loader_waysAllocator,loader_waysAllocator[1]}; - assign _zz_38 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - assign _zz_39 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_5) begin - _zz_19 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin - if(_zz_4) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_38; - end - end - - always @ (*) begin - _zz_20 = {_zz_43, _zz_42, _zz_41, _zz_40}; - end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_40 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_41 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_42 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_43 <= ways_0_data_symbol3[dataReadCmd_payload]; - end - end - - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_3) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_3) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_3) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_3) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end - end - - always @ (posedge clk) begin - if(_zz_8) begin - _zz_21 <= ways_1_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + wire when_DataCache_l1107; + wire when_DataCache_l1110; + (* ram_style = "block" *) reg [20:0] ways_0_tags [0:255]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:2047]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[12 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[12 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_1_tags[tagsWriteCmd_payload_address] <= _zz_39; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_22 = {_zz_47, _zz_46, _zz_45, _zz_44}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_10) begin - _zz_44 <= ways_1_data_symbol0[dataReadCmd_payload]; - _zz_45 <= ways_1_data_symbol1[dataReadCmd_payload]; - _zz_46 <= ways_1_data_symbol2[dataReadCmd_payload]; - _zz_47 <= ways_1_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin - ways_1_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end if(dataWriteCmd_payload_mask[1] && _zz_1) begin - ways_1_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end if(dataWriteCmd_payload_mask[2] && _zz_1) begin - ways_1_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end if(dataWriteCmd_payload_mask[3] && _zz_1) begin - ways_1_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[1]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[1]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end - always @ (*) begin - _zz_3 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_3 = 1'b1; - end - end - - always @ (*) begin - _zz_4 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_4 = 1'b1; - end - end - assign haltCpu = 1'b0; - assign _zz_5 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_6 = _zz_19; - assign ways_0_tagsReadRsp_valid = _zz_30[0]; - assign ways_0_tagsReadRsp_error = _zz_31[0]; - assign ways_0_tagsReadRsp_address = _zz_6[21 : 2]; - assign _zz_7 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_20; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[20 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - assign _zz_8 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_9 = _zz_21; - assign ways_1_tagsReadRsp_valid = _zz_32[0]; - assign ways_1_tagsReadRsp_error = _zz_33[0]; - assign ways_1_tagsReadRsp_address = _zz_9[21 : 2]; - assign _zz_10 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_1_dataReadRspMem = _zz_22; - assign ways_1_dataReadRsp = ways_1_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_23)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_23)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + always @(*) begin + tagsReadCmd_payload = 8'bxxxxxxxx; + if(when_DataCache_l656) begin + tagsReadCmd_payload = io_cpu_execute_address[12 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_23)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_23)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + always @(*) begin + dataReadCmd_payload = 11'bxxxxxxxxxxx; + if(when_DataCache_l656) begin + dataReadCmd_payload = io_cpu_execute_address[12 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_24)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin - tagsWriteCmd_payload_way = 2'bxx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = 2'b11; + always @(*) begin + tagsWriteCmd_payload_way = 1'bx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 8'bxxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[7:0]; end - if(loader_done)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + if(loader_done) begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[12 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + always @(*) begin + tagsWriteCmd_payload_data_address = 19'bxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 13]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_24)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin - dataWriteCmd_payload_way = 2'bxx; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + always @(*) begin + dataWriteCmd_payload_address = 11'bxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[12 : 2]; end - if(_zz_25)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + if(when_DataCache_l1075) begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[12 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_34[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_11 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_11 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_11 = 4'b1111; end endcase end - assign stage0_mask = (_zz_11 <<< io_cpu_execute_address[1 : 0]); - assign _zz_12 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_13 = dataWriteCmd_payload_mask[3 : 0]; - always @ (*) begin - stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); - stage0_dataColisions[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); - end - - assign stage0_wayInvalidate = 2'b00; + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - always @ (*) begin - _zz_14[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - _zz_14[1] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_1_tagsReadRsp_address) && ways_1_tagsReadRsp_valid); - end - - assign stageA_wayHits = _zz_14; - assign _zz_16 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_17 = dataWriteCmd_payload_mask[3 : 0]; - always @ (*) begin - _zz_15[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); - _zz_15[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); - end - - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_15); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 13] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); - assign stageB_waysHit = (stageB_waysHits != 2'b00); - assign stageB_dataMux = (stageB_waysHits[0] ? stageB_dataReadRsp_0 : stageB_dataReadRsp_1); - always @ (*) begin + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(! _zz_27) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_26)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_27)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[8]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[8]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -6471,89 +6718,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 2'b00)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_18) != 2'b00) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_26)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_27)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6561,12 +6792,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(! _zz_27) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6577,24 +6808,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - always @ (*) begin - _zz_18[0] = stageB_tagsReadRsp_0_error; - _zz_18[1] = stageB_tagsReadRsp_1_error; - end - - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_25)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6602,45 +6849,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_36); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6651,105 +6900,89 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_1_valid <= ways_1_tagsReadRsp_valid; - stageB_tagsReadRsp_1_error <= ways_1_tagsReadRsp_error; - stageB_tagsReadRsp_1_address <= ways_1_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_1 <= ways_1_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_28)begin - if(_zz_29)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 9'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; - loader_waysAllocator <= 2'b01; + loader_waysAllocator <= 1'b1; loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_28)begin - if(! _zz_29) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 9'h001); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 9'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_25)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_37[1:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6799,83 +7032,56 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_16; - reg [31:0] _zz_17; - reg [21:0] _zz_18; - reg [21:0] _zz_19; - reg _zz_20; - reg [31:0] _zz_21; - wire _zz_22; - wire _zz_23; - wire [0:0] _zz_24; - wire [0:0] _zz_25; - wire [0:0] _zz_26; - wire [0:0] _zz_27; - wire [21:0] _zz_28; - wire [21:0] _zz_29; + reg [31:0] _zz_banks_0_port1; + reg [20:0] _zz_ways_0_tags_port1; + wire [20:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; - reg _zz_3; - reg _zz_4; reg lineLoader_fire; reg lineLoader_valid; (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_5; + reg [8:0] lineLoader_flushCounter; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; - reg [0:0] lineLoader_wayToAllocate_valueNext; - reg [0:0] lineLoader_wayToAllocate_value; wire lineLoader_wayToAllocate_willOverflowIfInc; wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; + wire [7:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_tag_1_valid; - wire [6:0] lineLoader_write_tag_1_payload_address; - wire lineLoader_write_tag_1_payload_data_valid; - wire lineLoader_write_tag_1_payload_data_error; - wire [19:0] lineLoader_write_tag_1_payload_data_address; + wire [18:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; + wire [10:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire lineLoader_write_data_1_valid; - wire [9:0] lineLoader_write_data_1_payload_address; - wire [31:0] lineLoader_write_data_1_payload_data; - wire [9:0] _zz_6; - wire _zz_7; + wire when_InstructionCache_l401; + wire [10:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [9:0] _zz_8; - wire _zz_9; - wire [31:0] fetchStage_read_banksValue_1_dataMem; - wire [31:0] fetchStage_read_banksValue_1_data; - wire [6:0] _zz_10; - wire _zz_11; + wire [7:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_12; - wire [6:0] _zz_13; - wire _zz_14; - wire fetchStage_read_waysValues_1_tag_valid; - wire fetchStage_read_waysValues_1_tag_error; - wire [19:0] fetchStage_read_waysValues_1_tag_address; - wire [21:0] _zz_15; + wire [18:0] fetchStage_read_waysValues_0_tag_address; + wire [20:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; - wire fetchStage_hit_hits_1; wire fetchStage_hit_valid; - wire [0:0] fetchStage_hit_wayId; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -6885,258 +7091,181 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; - (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; - (* ram_style = "block" *) reg [31:0] banks_1 [0:1023]; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; - - assign _zz_22 = (! lineLoader_flushCounter[7]); - assign _zz_23 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_24 = _zz_12[0 : 0]; - assign _zz_25 = _zz_12[1 : 1]; - assign _zz_26 = _zz_15[0 : 0]; - assign _zz_27 = _zz_15[1 : 1]; - assign _zz_28 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - assign _zz_29 = {lineLoader_write_tag_1_payload_data_address,{lineLoader_write_tag_1_payload_data_error,lineLoader_write_tag_1_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2) begin - banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end + (* ram_style = "block" *) reg [31:0] banks_0 [0:2047]; + (* ram_style = "block" *) reg [20:0] ways_0_tags [0:255]; - always @ (posedge clk) begin - if(_zz_7) begin - _zz_16 <= banks_0[_zz_6]; - end - end - - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin - banks_1[lineLoader_write_data_1_payload_address] <= lineLoader_write_data_1_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_9) begin - _zz_17 <= banks_1[_zz_8]; - end - end - - always @ (posedge clk) begin - if(_zz_4) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_28; + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_11) begin - _zz_18 <= ways_0_tags[_zz_10]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin - if(_zz_3) begin - ways_1_tags[lineLoader_write_tag_1_payload_address] <= _zz_29; + always @(posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_14) begin - _zz_19 <= ways_1_tags[_zz_13]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end always @(*) begin - case(fetchStage_hit_wayId) - 1'b0 : begin - _zz_20 = fetchStage_read_waysValues_0_tag_error; - _zz_21 = fetchStage_read_banksValue_0_data; - end - default : begin - _zz_20 = fetchStage_read_waysValues_1_tag_error; - _zz_21 = fetchStage_read_banksValue_1_data; - end - endcase - end - - always @ (*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_1_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin - _zz_3 = 1'b0; - if(lineLoader_write_tag_1_valid)begin - _zz_3 = 1'b1; - end - end - - always @ (*) begin - _zz_4 = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_4 = 1'b1; - end - end - - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_22)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_5))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[8]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = (lineLoader_wayToAllocate_value == 1'b1); + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - always @ (*) begin - lineLoader_wayToAllocate_valueNext = (lineLoader_wayToAllocate_value + lineLoader_wayToAllocate_willIncrement); - if(lineLoader_wayToAllocate_willClear)begin - lineLoader_wayToAllocate_valueNext = 1'b0; - end - end - - assign lineLoader_write_tag_0_valid = (((lineLoader_wayToAllocate_value == 1'b0) && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[8])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[8] ? lineLoader_address[12 : 5] : lineLoader_flushCounter[7 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[8]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_tag_1_valid = (((lineLoader_wayToAllocate_value == 1'b1) && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_1_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_1_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_1_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_1_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b0)); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 13]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[12 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign lineLoader_write_data_1_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b1)); - assign lineLoader_write_data_1_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_1_payload_data = io_mem_rsp_payload_data; - assign _zz_6 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_16; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[12 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_8 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_1_dataMem = _zz_17; - assign fetchStage_read_banksValue_1_data = fetchStage_read_banksValue_1_dataMem[31 : 0]; - assign _zz_10 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_11 = (! io_cpu_fetch_isStuck); - assign _zz_12 = _zz_18; - assign fetchStage_read_waysValues_0_tag_valid = _zz_24[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_25[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_12[21 : 2]; - assign _zz_13 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_14 = (! io_cpu_fetch_isStuck); - assign _zz_15 = _zz_19; - assign fetchStage_read_waysValues_1_tag_valid = _zz_26[0]; - assign fetchStage_read_waysValues_1_tag_error = _zz_27[0]; - assign fetchStage_read_waysValues_1_tag_address = _zz_15[21 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_hits_1 = (fetchStage_read_waysValues_1_tag_valid && (fetchStage_read_waysValues_1_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = ({fetchStage_hit_hits_1,fetchStage_hit_hits_0} != 2'b00); - assign fetchStage_hit_wayId = fetchStage_hit_hits_1; - assign fetchStage_hit_error = _zz_20; - assign fetchStage_hit_data = _zz_21; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[12 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[20 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 13])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; lineLoader_flushPending <= 1'b1; lineLoader_cmdSent <= 1'b0; - lineLoader_wayToAllocate_value <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_23)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - lineLoader_wayToAllocate_value <= lineLoader_wayToAllocate_valueNext; - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_22)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + if(when_InstructionCache_l338) begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 9'h001); end - _zz_5 <= lineLoader_flushCounter[7]; - if(_zz_23)begin - lineLoader_flushCounter <= 8'h0; + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[8]; + if(when_InstructionCache_l351) begin + lineLoader_flushCounter <= 9'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -7147,10 +7276,10 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v index 6613f83..5a78830 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_PerfCfuDebug.v @@ -1,66 +1,57 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 5bb91146a62643cf606443d5366c69720906549c - - -`define Input2Kind_defaultEncoding_type [0:0] -`define Input2Kind_defaultEncoding_RS 1'b0 -`define Input2Kind_defaultEncoding_IMM_I 1'b1 - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define Input2Kind_binary_sequential_type [0:0] +`define Input2Kind_binary_sequential_RS 1'b0 +`define Input2Kind_binary_sequential_IMM_I 1'b1 + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, - output CfuPlugin_bus_cmd_valid, - input CfuPlugin_bus_cmd_ready, - output [9:0] CfuPlugin_bus_cmd_payload_function_id, - output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, - output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, - input CfuPlugin_bus_rsp_valid, - output CfuPlugin_bus_rsp_ready, - input CfuPlugin_bus_rsp_payload_response_ok, - input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, input [31:0] externalInterruptArray, input debug_bus_cmd_valid, output reg debug_bus_cmd_ready, @@ -69,6 +60,14 @@ module VexRiscv ( input [31:0] debug_bus_cmd_payload_data, output reg [31:0] debug_bus_rsp_data, output debug_resetOut, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, input iBusWishbone_ACK, @@ -95,37 +94,37 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - reg _zz_228; - wire _zz_229; - wire [31:0] _zz_230; - wire _zz_231; - wire [31:0] _zz_232; - reg _zz_233; - wire _zz_234; - wire _zz_235; - wire [31:0] _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire [3:0] _zz_245; - wire _zz_246; - wire _zz_247; - reg [31:0] _zz_248; - reg [31:0] _zz_249; - reg [31:0] _zz_250; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -148,6 +147,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -156,404 +156,332 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_251; - wire _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire _zz_256; - wire _zz_257; - wire _zz_258; - wire _zz_259; - wire _zz_260; - wire _zz_261; - wire _zz_262; - wire _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire _zz_267; - wire _zz_268; - wire [1:0] _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire _zz_279; - wire [1:0] _zz_280; - wire _zz_281; - wire _zz_282; - wire [5:0] _zz_283; - wire _zz_284; - wire _zz_285; - wire _zz_286; - wire _zz_287; - wire _zz_288; - wire _zz_289; - wire _zz_290; - wire [1:0] _zz_291; - wire _zz_292; - wire [1:0] _zz_293; - wire [51:0] _zz_294; - wire [51:0] _zz_295; - wire [51:0] _zz_296; - wire [32:0] _zz_297; - wire [51:0] _zz_298; - wire [49:0] _zz_299; - wire [51:0] _zz_300; - wire [49:0] _zz_301; - wire [51:0] _zz_302; - wire [32:0] _zz_303; - wire [31:0] _zz_304; - wire [32:0] _zz_305; - wire [0:0] _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire [0:0] _zz_312; - wire [0:0] _zz_313; - wire [0:0] _zz_314; - wire [0:0] _zz_315; - wire [0:0] _zz_316; - wire [0:0] _zz_317; - wire [0:0] _zz_318; - wire [0:0] _zz_319; - wire [0:0] _zz_320; - wire [0:0] _zz_321; - wire [0:0] _zz_322; - wire [0:0] _zz_323; - wire [0:0] _zz_324; - wire [3:0] _zz_325; - wire [2:0] _zz_326; - wire [31:0] _zz_327; - wire [11:0] _zz_328; - wire [31:0] _zz_329; - wire [19:0] _zz_330; - wire [11:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [19:0] _zz_334; - wire [11:0] _zz_335; - wire [2:0] _zz_336; - wire [2:0] _zz_337; - wire [0:0] _zz_338; - wire [2:0] _zz_339; - wire [4:0] _zz_340; - wire [11:0] _zz_341; - wire [11:0] _zz_342; - wire [31:0] _zz_343; - wire [31:0] _zz_344; - wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; - wire [31:0] _zz_349; - wire [11:0] _zz_350; - wire [19:0] _zz_351; - wire [11:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire [31:0] _zz_355; - wire [11:0] _zz_356; - wire [19:0] _zz_357; - wire [11:0] _zz_358; - wire [2:0] _zz_359; - wire [1:0] _zz_360; - wire [1:0] _zz_361; - wire [1:0] _zz_362; - wire [1:0] _zz_363; - wire [9:0] _zz_364; - wire [7:0] _zz_365; - wire [65:0] _zz_366; - wire [65:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; - wire [0:0] _zz_370; - wire [5:0] _zz_371; - wire [32:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire [32:0] _zz_375; - wire [32:0] _zz_376; - wire [32:0] _zz_377; - wire [32:0] _zz_378; - wire [0:0] _zz_379; - wire [32:0] _zz_380; - wire [0:0] _zz_381; - wire [32:0] _zz_382; - wire [0:0] _zz_383; - wire [31:0] _zz_384; - wire [0:0] _zz_385; - wire [0:0] _zz_386; - wire [0:0] _zz_387; - wire [0:0] _zz_388; - wire [0:0] _zz_389; - wire [0:0] _zz_390; - wire [0:0] _zz_391; - wire [26:0] _zz_392; - wire _zz_393; - wire _zz_394; - wire [1:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire _zz_399; - wire [0:0] _zz_400; - wire [14:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [8:0] _zz_407; - wire [31:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire _zz_411; - wire [0:0] _zz_412; - wire [2:0] _zz_413; - wire _zz_414; - wire _zz_415; - wire _zz_416; - wire [31:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire _zz_420; - wire [0:0] _zz_421; - wire [28:0] _zz_422; - wire [0:0] _zz_423; - wire [0:0] _zz_424; - wire [0:0] _zz_425; - wire [0:0] _zz_426; - wire _zz_427; - wire [0:0] _zz_428; - wire [23:0] _zz_429; - wire [31:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire _zz_433; - wire _zz_434; - wire [0:0] _zz_435; - wire [0:0] _zz_436; - wire [0:0] _zz_437; - wire [0:0] _zz_438; - wire _zz_439; - wire [0:0] _zz_440; - wire [20:0] _zz_441; - wire [31:0] _zz_442; - wire [31:0] _zz_443; - wire _zz_444; - wire _zz_445; - wire [0:0] _zz_446; - wire [1:0] _zz_447; - wire [0:0] _zz_448; - wire [0:0] _zz_449; - wire _zz_450; - wire [0:0] _zz_451; - wire [17:0] _zz_452; - wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [31:0] _zz_456; - wire [31:0] _zz_457; - wire [31:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire _zz_461; - wire [1:0] _zz_462; - wire [1:0] _zz_463; - wire _zz_464; - wire [0:0] _zz_465; - wire [14:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire [31:0] _zz_471; - wire [31:0] _zz_472; - wire [0:0] _zz_473; - wire [1:0] _zz_474; - wire [4:0] _zz_475; - wire [4:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [11:0] _zz_479; - wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire [31:0] _zz_485; - wire _zz_486; - wire [0:0] _zz_487; - wire [1:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; - wire [0:0] _zz_491; - wire [4:0] _zz_492; - wire [4:0] _zz_493; - wire [4:0] _zz_494; - wire _zz_495; - wire [0:0] _zz_496; - wire [8:0] _zz_497; - wire [31:0] _zz_498; - wire [31:0] _zz_499; - wire [31:0] _zz_500; - wire _zz_501; - wire _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire _zz_505; - wire [0:0] _zz_506; - wire [2:0] _zz_507; - wire [0:0] _zz_508; - wire [2:0] _zz_509; - wire [0:0] _zz_510; - wire [4:0] _zz_511; - wire [1:0] _zz_512; - wire [1:0] _zz_513; - wire _zz_514; - wire [0:0] _zz_515; - wire [6:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire _zz_520; - wire [0:0] _zz_521; - wire [0:0] _zz_522; - wire [31:0] _zz_523; - wire [31:0] _zz_524; - wire _zz_525; - wire [0:0] _zz_526; - wire [0:0] _zz_527; - wire _zz_528; - wire [0:0] _zz_529; - wire [2:0] _zz_530; - wire _zz_531; - wire [0:0] _zz_532; - wire [0:0] _zz_533; - wire [0:0] _zz_534; - wire [0:0] _zz_535; - wire _zz_536; - wire [0:0] _zz_537; - wire [4:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire [31:0] _zz_541; - wire [31:0] _zz_542; - wire [31:0] _zz_543; - wire [31:0] _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire [31:0] _zz_549; - wire [31:0] _zz_550; - wire [31:0] _zz_551; - wire _zz_552; - wire [0:0] _zz_553; - wire [0:0] _zz_554; - wire [31:0] _zz_555; - wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire [31:0] _zz_559; - wire _zz_560; - wire [3:0] _zz_561; - wire [3:0] _zz_562; - wire _zz_563; - wire [0:0] _zz_564; - wire [2:0] _zz_565; - wire [31:0] _zz_566; - wire [31:0] _zz_567; - wire [31:0] _zz_568; - wire [31:0] _zz_569; - wire [31:0] _zz_570; - wire [31:0] _zz_571; - wire _zz_572; - wire [0:0] _zz_573; - wire [1:0] _zz_574; - wire _zz_575; - wire [2:0] _zz_576; - wire [2:0] _zz_577; - wire _zz_578; - wire [0:0] _zz_579; - wire [0:0] _zz_580; - wire [31:0] _zz_581; - wire [31:0] _zz_582; - wire [31:0] _zz_583; - wire [31:0] _zz_584; - wire [31:0] _zz_585; - wire [31:0] _zz_586; - wire [31:0] _zz_587; - wire _zz_588; - wire _zz_589; - wire _zz_590; - wire [0:0] _zz_591; - wire [0:0] _zz_592; - wire _zz_593; - wire _zz_594; - wire _zz_595; - wire _zz_596; - wire [31:0] _zz_597; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6; + wire [27:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20; + wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35; + wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47; + wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70; + wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102; + wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127; + wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1; + wire _zz_when; + wire _zz_when_1; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_41; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; - wire writeBack_CfuPlugin_CFU_IN_FLIGHT; - wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_DO_EBREAK; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; wire decode_SRC2_FORCE_ZERO; + wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + wire decode_CfuPlugin_CFU_ENABLE; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_DIV; wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_1; - wire `Input2Kind_defaultEncoding_type _zz_2; - wire `Input2Kind_defaultEncoding_type _zz_3; - wire decode_CfuPlugin_CFU_ENABLE; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -561,24 +489,30 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; - wire `AluCtrlEnum_defaultEncoding_type _zz_25; - wire `AluCtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; - wire `Src1CtrlEnum_defaultEncoding_type _zz_28; - wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] memory_PC; + reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire execute_CfuPlugin_CFU_ENABLE; wire execute_DO_EBREAK; wire decode_IS_EBREAK; wire execute_IS_RS1_SIGNED; @@ -591,32 +525,26 @@ module VexRiscv ( wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; - reg _zz_30; - reg _zz_31; - wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_32; - wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_37; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -626,46 +554,46 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_38; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_41; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_42; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; - wire [31:0] _zz_46; - wire _zz_47; - reg _zz_48; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_49; - wire `EnvCtrlEnum_defaultEncoding_type _zz_50; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; - wire `Src2CtrlEnum_defaultEncoding_type _zz_54; - wire `AluCtrlEnum_defaultEncoding_type _zz_55; - wire `Src1CtrlEnum_defaultEncoding_type _zz_56; - reg [31:0] _zz_57; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -683,11 +611,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_59; - reg [31:0] _zz_60; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -717,7 +645,7 @@ module VexRiscv ( wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; + wire memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; @@ -774,7 +702,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -800,7 +728,7 @@ module VexRiscv ( reg DBusCachedPlugin_exceptionBus_valid; reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_61; + reg _zz_when_DBusCachedPlugin_l386; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -809,6 +737,11 @@ module VexRiscv ( reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -826,34 +759,37 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; reg CsrPlugin_allowInterrupts; reg CsrPlugin_allowException; - reg CfuPlugin_joinException_valid; - wire [3:0] CfuPlugin_joinException_payload_code; - wire [31:0] CfuPlugin_joinException_payload_badAddr; + reg CsrPlugin_allowEbreakException; reg IBusCachedPlugin_injectionPort_valid; reg IBusCachedPlugin_injectionPort_ready; wire [31:0] IBusCachedPlugin_injectionPort_payload; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_62; - wire [3:0] _zz_63; - wire _zz_64; - wire _zz_65; - wire _zz_66; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -876,16 +812,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_67; - wire _zz_68; - wire _zz_69; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_70; - wire _zz_71; - reg _zz_72; - wire _zz_73; - reg _zz_74; - reg [31:0] _zz_75; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -893,22 +831,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_76; - reg [18:0] _zz_77; - wire _zz_78; - reg [10:0] _zz_79; - wire _zz_80; - reg [18:0] _zz_81; - reg _zz_82; - wire _zz_83; - reg [10:0] _zz_84; - wire _zz_85; - reg [18:0] _zz_86; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -916,7 +861,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_87; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -924,23 +869,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -948,40 +898,56 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_88; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_89; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_90; - reg [31:0] _zz_91; - wire _zz_92; - reg [31:0] _zz_93; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [34:0] _zz_94; - wire _zz_95; - wire _zz_96; - wire _zz_97; - wire _zz_98; - wire _zz_99; - wire `Src1CtrlEnum_defaultEncoding_type _zz_100; - wire `AluCtrlEnum_defaultEncoding_type _zz_101; - wire `Src2CtrlEnum_defaultEncoding_type _zz_102; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; - wire `BranchCtrlEnum_defaultEncoding_type _zz_105; - wire `EnvCtrlEnum_defaultEncoding_type _zz_106; - wire `Input2Kind_defaultEncoding_type _zz_107; + wire when_DBusCachedPlugin_l484; + wire [34:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -989,53 +955,72 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_108; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_109; - reg [31:0] _zz_110; - wire _zz_111; - reg [19:0] _zz_112; - wire _zz_113; - reg [19:0] _zz_114; - reg [31:0] _zz_115; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_116; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_117; - reg _zz_118; - reg _zz_119; - reg _zz_120; - reg [4:0] _zz_121; - reg [31:0] _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; - wire _zz_126; - wire _zz_127; - wire _zz_128; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_129; - reg _zz_130; - reg _zz_131; - wire _zz_132; - reg [19:0] _zz_133; - wire _zz_134; - reg [10:0] _zz_135; - wire _zz_136; - reg [18:0] _zz_137; - reg _zz_138; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_139; - reg [19:0] _zz_140; - wire _zz_141; - reg [10:0] _zz_142; - wire _zz_143; - reg [18:0] _zz_144; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; + wire when_BranchPlugin_l296; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1056,9 +1041,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_145; - wire _zz_146; - wire _zz_147; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1071,72 +1056,69 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_148; - wire _zz_149; - wire [1:0] _zz_150; - wire _zz_151; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - wire execute_CfuPlugin_schedule; - reg execute_CfuPlugin_hold; - reg execute_CfuPlugin_fired; - wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_168; - reg [23:0] _zz_169; - reg [31:0] _zz_170; - wire memory_CfuPlugin_rsp_valid; - reg memory_CfuPlugin_rsp_ready; - wire memory_CfuPlugin_rsp_payload_response_ok; - wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_s2mPipe_rValid; - reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1144,6 +1126,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1156,19 +1140,26 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_171; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_172; - wire _zz_173; - wire _zz_174; - reg [32:0] _zz_175; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_176; - wire [31:0] _zz_177; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1176,236 +1167,408 @@ module VexRiscv ( reg DebugPlugin_stepIt; reg DebugPlugin_isPipBusy; reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_178; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire CfuPlugin_bus_cmd_fire; + wire when_CfuPlugin_l171; + wire when_CfuPlugin_l175; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_CfuPlugin_bus_cmd_payload_inputs_1; + reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1; + reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + wire CfuPlugin_bus_rsp_rsp_valid; + reg CfuPlugin_bus_rsp_rsp_ready; + wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_rValid; + reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; + wire when_CfuPlugin_l208; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_when_GenCoreDefault_l367; + wire when_GenCoreDefault_l367; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_when_GenCoreDefault_l367_1; + wire when_GenCoreDefault_l367_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_when_GenCoreDefault_l367_2; + wire when_GenCoreDefault_l367_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_when_GenCoreDefault_l367_3; + wire when_GenCoreDefault_l367_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_when_GenCoreDefault_l367_4; + wire when_GenCoreDefault_l367_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_when_GenCoreDefault_l367_5; + wire when_GenCoreDefault_l367_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_when_GenCoreDefault_l367_6; + wire when_GenCoreDefault_l367_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_when_GenCoreDefault_l367_7; + wire when_GenCoreDefault_l367_7; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + wire when_Pipeline_l124_44; + reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_45; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_46; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_47; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_48; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_49; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_50; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_51; reg decode_to_execute_DO_EBREAK; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_52; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_53; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_54; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_55; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_57; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_60; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_61; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_62; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_63; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_64; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_179; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l378; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; + reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; + reg execute_CsrPlugin_csr_4032; + wire when_CsrPlugin_l1264_24; reg execute_CsrPlugin_csr_2820; + wire when_CsrPlugin_l1264_25; reg execute_CsrPlugin_csr_2821; + wire when_CsrPlugin_l1264_26; reg execute_CsrPlugin_csr_2822; + wire when_CsrPlugin_l1264_27; reg execute_CsrPlugin_csr_2823; + wire when_CsrPlugin_l1264_28; reg execute_CsrPlugin_csr_2824; + wire when_CsrPlugin_l1264_29; reg execute_CsrPlugin_csr_2825; + wire when_CsrPlugin_l1264_30; reg execute_CsrPlugin_csr_2826; + wire when_CsrPlugin_l1264_31; reg execute_CsrPlugin_csr_2827; + wire when_CsrPlugin_l1264_32; reg execute_CsrPlugin_csr_2828; + wire when_CsrPlugin_l1264_33; reg execute_CsrPlugin_csr_2829; + wire when_CsrPlugin_l1264_34; reg execute_CsrPlugin_csr_2830; + wire when_CsrPlugin_l1264_35; reg execute_CsrPlugin_csr_2831; + wire when_CsrPlugin_l1264_36; reg execute_CsrPlugin_csr_2832; + wire when_CsrPlugin_l1264_37; reg execute_CsrPlugin_csr_2833; + wire when_CsrPlugin_l1264_38; reg execute_CsrPlugin_csr_2834; + wire when_CsrPlugin_l1264_39; reg execute_CsrPlugin_csr_2835; - reg execute_CsrPlugin_csr_3008; - reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [31:0] _zz_199; - reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; - reg [31:0] _zz_208; - reg [31:0] _zz_209; - reg [31:0] _zz_210; - reg [2:0] _zz_211; - reg _zz_212; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_29; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_30; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_31; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_32; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_33; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_34; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_35; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_36; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_37; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_38; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_39; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_40; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - reg _zz_219; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8_string; - reg [39:0] _zz_9_string; - reg [39:0] _zz_10_string; - reg [31:0] _zz_11_string; - reg [31:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_15_string; - reg [71:0] _zz_16_string; - reg [71:0] _zz_17_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_18_string; - reg [39:0] _zz_19_string; - reg [39:0] _zz_20_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_21_string; - reg [23:0] _zz_22_string; - reg [23:0] _zz_23_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_24_string; - reg [63:0] _zz_25_string; - reg [63:0] _zz_26_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_27_string; - reg [95:0] _zz_28_string; - reg [95:0] _zz_29_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_32_string; + reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_36_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_39_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_40_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_42_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_43_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_44_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_45_string; - reg [39:0] _zz_49_string; - reg [39:0] _zz_50_string; - reg [31:0] _zz_51_string; - reg [71:0] _zz_52_string; - reg [39:0] _zz_53_string; - reg [23:0] _zz_54_string; - reg [63:0] _zz_55_string; - reg [95:0] _zz_56_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_58_string; - reg [95:0] _zz_100_string; - reg [63:0] _zz_101_string; - reg [23:0] _zz_102_string; - reg [39:0] _zz_103_string; - reg [71:0] _zz_104_string; - reg [31:0] _zz_105_string; - reg [39:0] _zz_106_string; - reg [39:0] _zz_107_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1421,489 +1584,441 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_251 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_253 = 1'b1; - assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_256 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_257 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_258 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_259 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_260 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_261 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_262 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_263 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_264 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_265 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_268 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_269 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_270 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_271 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_272 = (1'b0 || (! 1'b1)); - assign _zz_273 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_274 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_275 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_276 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_277 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_278 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_280 = execute_INSTRUCTION[13 : 12]; - assign _zz_281 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_282 = (! memory_arbitration_isStuck); - assign _zz_283 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_284 = (iBus_cmd_valid || (_zz_211 != 3'b000)); - assign _zz_285 = (_zz_247 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_286 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_287 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_288 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_289 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_290 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_291 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_292 = execute_INSTRUCTION[13]; - assign _zz_293 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_294 = ($signed(_zz_295) + $signed(_zz_300)); - assign _zz_295 = ($signed(_zz_296) + $signed(_zz_298)); - assign _zz_296 = 52'h0; - assign _zz_297 = {1'b0,memory_MUL_LL}; - assign _zz_298 = {{19{_zz_297[32]}}, _zz_297}; - assign _zz_299 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; - assign _zz_301 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_302 = {{2{_zz_301[49]}}, _zz_301}; - assign _zz_303 = ($signed(_zz_305) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_304 = _zz_303[31 : 0]; - assign _zz_305 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_306 = _zz_94[33 : 33]; - assign _zz_307 = _zz_94[32 : 32]; - assign _zz_308 = _zz_94[31 : 31]; - assign _zz_309 = _zz_94[30 : 30]; - assign _zz_310 = _zz_94[28 : 28]; - assign _zz_311 = _zz_94[25 : 25]; - assign _zz_312 = _zz_94[17 : 17]; - assign _zz_313 = _zz_94[16 : 16]; - assign _zz_314 = _zz_94[13 : 13]; - assign _zz_315 = _zz_94[12 : 12]; - assign _zz_316 = _zz_94[11 : 11]; - assign _zz_317 = _zz_94[34 : 34]; - assign _zz_318 = _zz_94[15 : 15]; - assign _zz_319 = _zz_94[5 : 5]; - assign _zz_320 = _zz_94[3 : 3]; - assign _zz_321 = _zz_94[20 : 20]; - assign _zz_322 = _zz_94[10 : 10]; - assign _zz_323 = _zz_94[4 : 4]; - assign _zz_324 = _zz_94[0 : 0]; - assign _zz_325 = (_zz_62 - 4'b0001); - assign _zz_326 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_327 = {29'd0, _zz_326}; - assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_329 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_331 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_332 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_333 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_334 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_335 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_338 = execute_SRC_LESS; - assign _zz_339 = 3'b100; - assign _zz_340 = execute_INSTRUCTION[19 : 15]; - assign _zz_341 = execute_INSTRUCTION[31 : 20]; - assign _zz_342 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_343 = ($signed(_zz_344) + $signed(_zz_347)); - assign _zz_344 = ($signed(_zz_345) + $signed(_zz_346)); - assign _zz_345 = execute_SRC1; - assign _zz_346 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_347 = (execute_SRC_USE_SUB_LESS ? _zz_348 : _zz_349); - assign _zz_348 = 32'h00000001; - assign _zz_349 = 32'h0; - assign _zz_350 = execute_INSTRUCTION[31 : 20]; - assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_353 = {_zz_133,execute_INSTRUCTION[31 : 20]}; - assign _zz_354 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_355 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_356 = execute_INSTRUCTION[31 : 20]; - assign _zz_357 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_359 = 3'b100; - assign _zz_360 = (_zz_148 & (~ _zz_361)); - assign _zz_361 = (_zz_148 - 2'b01); - assign _zz_362 = (_zz_150 & (~ _zz_363)); - assign _zz_363 = (_zz_150 - 2'b01); - assign _zz_364 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_365 = execute_INSTRUCTION[31 : 24]; - assign _zz_366 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_367 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_368 = writeBack_MUL_LOW[31 : 0]; - assign _zz_369 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_370 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_371 = {5'd0, _zz_370}; - assign _zz_372 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_373 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_374 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_375 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_376 = _zz_377; - assign _zz_377 = _zz_378; - assign _zz_378 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_380); - assign _zz_379 = memory_DivPlugin_div_needRevert; - assign _zz_380 = {32'd0, _zz_379}; - assign _zz_381 = _zz_174; - assign _zz_382 = {32'd0, _zz_381}; - assign _zz_383 = _zz_173; - assign _zz_384 = {31'd0, _zz_383}; - assign _zz_385 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_386 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_387 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_388 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_391 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_392 = (iBus_cmd_payload_address >>> 5); - assign _zz_393 = 1'b1; - assign _zz_394 = 1'b1; - assign _zz_395 = {_zz_66,_zz_65}; - assign _zz_396 = 32'h0000106f; - assign _zz_397 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_398 = 32'h00001073; - assign _zz_399 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_400 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_401 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_402) == 32'h00000003),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; - assign _zz_402 = 32'h0000207f; - assign _zz_403 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_404 = 32'h00000003; - assign _zz_405 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_406 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_407 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_408) == 32'h00005013),{(_zz_409 == _zz_410),{_zz_411,{_zz_412,_zz_413}}}}}}; - assign _zz_408 = 32'hbc00707f; - assign _zz_409 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_410 = 32'h00001013; - assign _zz_411 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_412 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_413 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; - assign _zz_414 = decode_INSTRUCTION[31]; - assign _zz_415 = decode_INSTRUCTION[31]; - assign _zz_416 = decode_INSTRUCTION[7]; - assign _zz_417 = 32'h10103050; - assign _zz_418 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_419 = 1'b0; - assign _zz_420 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_421 = 1'b0; - assign _zz_422 = {(_zz_98 != 1'b0),{({_zz_423,_zz_424} != 2'b00),{(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}}}; - assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h10000050); - assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00000050); - assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00000050); - assign _zz_426 = 1'b0; - assign _zz_427 = ({_zz_433,_zz_434} != 2'b00); - assign _zz_428 = ({_zz_435,_zz_436} != 2'b00); - assign _zz_429 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; - assign _zz_430 = 32'h10203050; - assign _zz_431 = 32'h10103050; - assign _zz_432 = 32'h00103050; - assign _zz_433 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_434 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_435 = _zz_97; - assign _zz_436 = ((decode_INSTRUCTION & _zz_442) == 32'h00000004); - assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000040); - assign _zz_438 = 1'b0; - assign _zz_439 = ({_zz_444,_zz_445} != 2'b00); - assign _zz_440 = ({_zz_446,_zz_447} != 3'b000); - assign _zz_441 = {(_zz_448 != _zz_449),{_zz_450,{_zz_451,_zz_452}}}; - assign _zz_442 = 32'h0000001c; - assign _zz_443 = 32'h00000058; - assign _zz_444 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_445 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h40001010); - assign _zz_447 = {(_zz_454 == _zz_455),(_zz_456 == _zz_457)}; - assign _zz_448 = ((decode_INSTRUCTION & _zz_458) == 32'h00000024); - assign _zz_449 = 1'b0; - assign _zz_450 = ((_zz_459 == _zz_460) != 1'b0); - assign _zz_451 = (_zz_461 != 1'b0); - assign _zz_452 = {(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}; - assign _zz_453 = 32'h40003054; - assign _zz_454 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_455 = 32'h00001010; - assign _zz_456 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_457 = 32'h00001010; - assign _zz_458 = 32'h00000064; - assign _zz_459 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_460 = 32'h00001000; - assign _zz_461 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_462 = {(_zz_467 == _zz_468),(_zz_469 == _zz_470)}; - assign _zz_463 = 2'b00; - assign _zz_464 = ((_zz_471 == _zz_472) != 1'b0); - assign _zz_465 = ({_zz_473,_zz_474} != 3'b000); - assign _zz_466 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; - assign _zz_467 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_468 = 32'h00002000; - assign _zz_469 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_470 = 32'h00001000; - assign _zz_471 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_472 = 32'h00004004; - assign _zz_473 = _zz_98; - assign _zz_474 = {(_zz_480 == _zz_481),(_zz_482 == _zz_483)}; - assign _zz_475 = {(_zz_484 == _zz_485),{_zz_486,{_zz_487,_zz_488}}}; - assign _zz_476 = 5'h0; - assign _zz_477 = ((_zz_489 == _zz_490) != 1'b0); - assign _zz_478 = ({_zz_491,_zz_492} != 6'h0); - assign _zz_479 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; - assign _zz_480 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_481 = 32'h00000020; - assign _zz_482 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_483 = 32'h00000020; - assign _zz_484 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_485 = 32'h00002040; - assign _zz_486 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); - assign _zz_487 = (_zz_499 == _zz_500); - assign _zz_488 = {_zz_501,_zz_502}; - assign _zz_489 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_490 = 32'h00000020; - assign _zz_491 = (_zz_503 == _zz_504); - assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; - assign _zz_493 = {_zz_96,{_zz_508,_zz_509}}; - assign _zz_494 = 5'h0; - assign _zz_495 = ({_zz_510,_zz_511} != 6'h0); - assign _zz_496 = (_zz_512 != _zz_513); - assign _zz_497 = {_zz_514,{_zz_515,_zz_516}}; - assign _zz_498 = 32'h00001040; - assign _zz_499 = (decode_INSTRUCTION & 32'h00100040); - assign _zz_500 = 32'h00000040; - assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00000040); - assign _zz_502 = ((decode_INSTRUCTION & _zz_518) == 32'h0); - assign _zz_503 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_504 = 32'h00000008; - assign _zz_505 = ((decode_INSTRUCTION & _zz_519) == 32'h00000040); - assign _zz_506 = _zz_96; - assign _zz_507 = {_zz_520,{_zz_521,_zz_522}}; - assign _zz_508 = (_zz_523 == _zz_524); - assign _zz_509 = {_zz_525,{_zz_526,_zz_527}}; - assign _zz_510 = _zz_97; - assign _zz_511 = {_zz_528,{_zz_529,_zz_530}}; - assign _zz_512 = {_zz_96,_zz_531}; - assign _zz_513 = 2'b00; - assign _zz_514 = ({_zz_532,_zz_533} != 2'b00); - assign _zz_515 = (_zz_534 != _zz_535); - assign _zz_516 = {_zz_536,{_zz_537,_zz_538}}; - assign _zz_517 = 32'h00000050; - assign _zz_518 = 32'h00000038; - assign _zz_519 = 32'h00000040; - assign _zz_520 = ((decode_INSTRUCTION & _zz_539) == 32'h00004020); - assign _zz_521 = (_zz_540 == _zz_541); - assign _zz_522 = (_zz_542 == _zz_543); - assign _zz_523 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_524 = 32'h00002010; - assign _zz_525 = ((decode_INSTRUCTION & _zz_544) == 32'h00000010); - assign _zz_526 = (_zz_545 == _zz_546); - assign _zz_527 = (_zz_547 == _zz_548); - assign _zz_528 = ((decode_INSTRUCTION & _zz_549) == 32'h00001010); - assign _zz_529 = (_zz_550 == _zz_551); - assign _zz_530 = {_zz_552,{_zz_553,_zz_554}}; - assign _zz_531 = ((decode_INSTRUCTION & _zz_555) == 32'h00000020); - assign _zz_532 = _zz_96; - assign _zz_533 = (_zz_556 == _zz_557); - assign _zz_534 = (_zz_558 == _zz_559); - assign _zz_535 = 1'b0; - assign _zz_536 = (_zz_560 != 1'b0); - assign _zz_537 = (_zz_561 != _zz_562); - assign _zz_538 = {_zz_563,{_zz_564,_zz_565}}; - assign _zz_539 = 32'h00004020; - assign _zz_540 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_541 = 32'h00000010; - assign _zz_542 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_543 = 32'h00000020; - assign _zz_544 = 32'h00001030; - assign _zz_545 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_546 = 32'h00002020; - assign _zz_547 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_548 = 32'h00000020; - assign _zz_549 = 32'h00001010; - assign _zz_550 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_551 = 32'h00002010; - assign _zz_552 = ((decode_INSTRUCTION & _zz_566) == 32'h00000010); - assign _zz_553 = (_zz_567 == _zz_568); - assign _zz_554 = (_zz_569 == _zz_570); - assign _zz_555 = 32'h00000070; - assign _zz_556 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_557 = 32'h0; - assign _zz_558 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_559 = 32'h00004010; - assign _zz_560 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); - assign _zz_561 = {_zz_572,{_zz_573,_zz_574}}; - assign _zz_562 = 4'b0000; - assign _zz_563 = (_zz_575 != 1'b0); - assign _zz_564 = (_zz_576 != _zz_577); - assign _zz_565 = {_zz_578,{_zz_579,_zz_580}}; - assign _zz_566 = 32'h00000050; - assign _zz_567 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_568 = 32'h00000004; - assign _zz_569 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_570 = 32'h0; - assign _zz_571 = 32'h00006014; - assign _zz_572 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_573 = ((decode_INSTRUCTION & _zz_581) == 32'h0); - assign _zz_574 = {(_zz_582 == _zz_583),(_zz_584 == _zz_585)}; - assign _zz_575 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_576 = {(_zz_586 == _zz_587),{_zz_588,_zz_589}}; - assign _zz_577 = 3'b000; - assign _zz_578 = ({_zz_590,_zz_95} != 2'b00); - assign _zz_579 = ({_zz_591,_zz_592} != 2'b00); - assign _zz_580 = (_zz_593 != 1'b0); - assign _zz_581 = 32'h00000018; - assign _zz_582 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_583 = 32'h00002000; - assign _zz_584 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_585 = 32'h00001000; - assign _zz_586 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_587 = 32'h00000040; - assign _zz_588 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_589 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_590 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_591 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_592 = _zz_95; - assign _zz_593 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); - assign _zz_594 = execute_INSTRUCTION[31]; - assign _zz_595 = execute_INSTRUCTION[31]; - assign _zz_596 = execute_INSTRUCTION[7]; - assign _zz_597 = 32'h0; - always @ (posedge clk) begin - if(_zz_393) begin - _zz_248 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_394) begin - _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_48) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = (decode_INSTRUCTION & 32'h10103050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 32'h00100050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = (((decode_INSTRUCTION & 32'h02004064) == 32'h02004020) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9} != 2'b00),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21}}}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h02004074; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00001050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = 32'h00002050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = 32'h00005020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h00007034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = 32'h02007054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = 32'h00002000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50) == 32'h00004004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = 32'h00005000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = 32'h00004054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59) == 32'h00002040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81}} != 6'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = 32'h00000064; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = 32'h00002040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00001040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77) == 32'h00000008); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = 6'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = 32'h00100040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = 32'h00000008; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = 32'h00004020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = 32'h00002030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00002020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131) == 32'h00004010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141} != 4'b0000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h00000030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = 32'h02000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02002060; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = 32'h02003020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = 32'h00004014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = 32'h00000044; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = 32'h00000058; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156) == 32'h40000030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167) == 32'h00001004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h00002014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = 32'h40000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = 32'h00000014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = 32'h00000004; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167 = 32'h00005054; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_41 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_220 ), //i - .io_cpu_prefetch_isValid (_zz_221 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_222 ), //i - .io_cpu_fetch_isStuck (_zz_223 ), //i - .io_cpu_fetch_isRemoved (_zz_224 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_225 ), //i - .io_cpu_decode_isStuck (_zz_226 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_227 ), //i - .io_cpu_fill_valid (_zz_228 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_16 (_zz_179[2:0] ), //i - ._zz_17 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i + ._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_229 ), //i - .io_cpu_execute_address (_zz_230[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_89[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_231 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_232[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_233 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_234 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_235 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_236[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_237 ), //i - .io_cpu_writeBack_fence_SR (_zz_238 ), //i - .io_cpu_writeBack_fence_SO (_zz_239 ), //i - .io_cpu_writeBack_fence_SI (_zz_240 ), //i - .io_cpu_writeBack_fence_PW (_zz_241 ), //i - .io_cpu_writeBack_fence_PR (_zz_242 ), //i - .io_cpu_writeBack_fence_PO (_zz_243 ), //i - .io_cpu_writeBack_fence_PI (_zz_244 ), //i - .io_cpu_writeBack_fence_FM (_zz_245[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_246 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_247 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_395) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) + 2'b00 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) 2'b00 : begin - _zz_250 = DBusCachedPlugin_redoBranch_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; end 2'b01 : begin - _zz_250 = CsrPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; end 2'b10 : begin - _zz_250 = BranchPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; end default : begin - _zz_250 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end @@ -1911,811 +2026,828 @@ module VexRiscv ( `ifndef SYNTHESIS always @(*) begin case(decode_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_1) - `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; - default : _zz_1_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; - default : _zz_2_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; - default : _zz_3_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; - default : _zz_8_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_9) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; - default : _zz_9_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_10) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; - default : _zz_10_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_11) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; - default : _zz_11_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_12) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; - default : _zz_12_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_16) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; - default : _zz_16_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_17) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; - default : _zz_17_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_19) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; - default : _zz_19_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_20) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; - default : _zz_20_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_25) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; - default : _zz_25_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_26) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; - default : _zz_26_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_28) - `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; - default : _zz_28_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_29) - `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; - default : _zz_29_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_32) - `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; - default : _zz_32_string = "?????"; + case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_36) - `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; - default : _zz_36_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_39) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; - default : _zz_39_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_40) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; - default : _zz_40_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_42) - `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; - default : _zz_42_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_43) - `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; - default : _zz_43_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_44) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; - default : _zz_44_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_45) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; - default : _zz_45_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_49) - `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; - default : _zz_49_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_50) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; - default : _zz_50_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_52) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; - default : _zz_52_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_53) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; - default : _zz_53_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_54) - `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; - default : _zz_54_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_55) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; - default : _zz_55_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_56) - `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; - default : _zz_56_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_58) - `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; - default : _zz_58_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_100) - `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; - default : _zz_100_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_101) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; - default : _zz_101_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_102) - `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; - default : _zz_102_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_103) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; - default : _zz_103_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_104) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; - default : _zz_104_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_105) - `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; - default : _zz_105_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_106) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; - default : _zz_106_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_107) - `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; - default : _zz_107_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_294) + $signed(_zz_302)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_304; - assign execute_REGFILE_WRITE_DATA = _zz_109; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_230[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_306[0]; - assign decode_IS_RS1_SIGNED = _zz_307[0]; - assign decode_IS_DIV = _zz_308[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33]; + assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30]; + assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_309[0]; - assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; - assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_310[0]; - assign _zz_4 = _zz_5; - assign _zz_6 = _zz_7; - assign decode_ENV_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_311[0]; - assign _zz_11 = _zz_12; - assign _zz_13 = _zz_14; - assign decode_SHIFT_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_ALU_BITWISE_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_312[0]; - assign decode_MEMORY_MANAGMENT = _zz_313[0]; + assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_314[0]; + assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_315[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_316[0]; - assign decode_SRC2_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_ALU_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_SRC1_CTRL = _zz_27; - assign _zz_28 = _zz_29; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; + always @(*) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + always @(*) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_317[0]; + assign decode_IS_EBREAK = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2726,42 +2858,25 @@ module VexRiscv ( assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; - always @ (*) begin - _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; - if(memory_arbitration_isStuck)begin - _zz_30 = 1'b0; - end - end - - always @ (*) begin - _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; - if(execute_arbitration_isStuck)begin - _zz_31 = 1'b0; - end - end - - assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33; - assign execute_ENV_CTRL = _zz_34; - assign writeBack_ENV_CTRL = _zz_35; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_131; - assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_318[0]; - assign decode_RS1_USE = _zz_319[0]; - always @ (*) begin - _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_251)begin - _zz_37 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15]; + assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2771,142 +2886,142 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_122; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_252)begin - if(_zz_253)begin - if(_zz_124)begin - decode_RS2 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_254)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_126)begin - decode_RS2 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_255)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_128)begin - decode_RS2 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_122; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_252)begin - if(_zz_253)begin - if(_zz_123)begin - decode_RS1 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_254)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin - decode_RS1 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_255)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin - decode_RS1 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_38 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_117; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_38 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end - if(_zz_256)begin - _zz_38 = memory_DivPlugin_div_result; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + _zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0; end end - assign memory_SHIFT_CTRL = _zz_39; - assign execute_SHIFT_CTRL = _zz_40; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_41 = execute_PC; - assign execute_SRC2_CTRL = _zz_42; - assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_320[0]; - assign decode_SRC_ADD_ZERO = _zz_321[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_115; - assign execute_SRC1 = _zz_110; - assign execute_ALU_BITWISE_CTRL = _zz_45; - assign _zz_46 = writeBack_INSTRUCTION; - assign _zz_47 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_48 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_48 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_322[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}} != 22'h0); - always @ (*) begin - _zz_57 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_293) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_57 = _zz_368; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_57 = _zz_369; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2918,61 +3033,61 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_323[0]; - assign decode_FLUSH_ALL = _zz_324[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4]; + assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_257)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_258)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_259)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_260)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_58; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_59 = execute_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_59 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_60 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end - case(_zz_179) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2981,174 +3096,165 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_261)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_246 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_262)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_251)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end - if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + if(when_CfuPlugin_l175) begin execute_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_263)begin + if(when_DebugPlugin_l284) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_264)begin + if(_zz_when_1) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushIt = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_264)begin + if(_zz_when_1) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushNext = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if((! memory_CfuPlugin_rsp_valid))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_256)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + if(when_CfuPlugin_l208) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushNext = 1'b0; + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3157,75 +3263,77 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_268)begin + if(when_DebugPlugin_l300) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin - _zz_61 = 1'b0; - if(DebugPlugin_godmode)begin - _zz_61 = 1'b1; + always @(*) begin + _zz_when_DBusCachedPlugin_l386 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l386 = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_262)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin CsrPlugin_thirdPartyWake = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_266)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_267)begin - case(_zz_269) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3235,80 +3343,92 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_forceMachineWire = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + if(when_DebugPlugin_l316) begin CsrPlugin_allowInterrupts = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_allowException = 1'b0; end end + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_63 = (_zz_62 & (~ _zz_325)); - assign _zz_64 = _zz_63[3]; - assign _zz_65 = (_zz_63[1] || _zz_64); - assign _zz_66 = (_zz_63[2] || _zz_64); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_250; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_327); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3316,66 +3436,75 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_67); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_68); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_68); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_69 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_69); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_69); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_70; - assign _zz_70 = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_71 = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_73)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_73 = _zz_74; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_73; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_75; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); - always @ (*) begin + always @(*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_179) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3387,207 +3516,219 @@ module VexRiscv ( endcase end - assign _zz_76 = _zz_328[11]; - always @ (*) begin - _zz_77[18] = _zz_76; - _zz_77[17] = _zz_76; - _zz_77[16] = _zz_76; - _zz_77[15] = _zz_76; - _zz_77[14] = _zz_76; - _zz_77[13] = _zz_76; - _zz_77[12] = _zz_76; - _zz_77[11] = _zz_76; - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7] = _zz_76; - _zz_77[6] = _zz_76; - _zz_77[5] = _zz_76; - _zz_77[4] = _zz_76; - _zz_77[3] = _zz_76; - _zz_77[2] = _zz_76; - _zz_77[1] = _zz_76; - _zz_77[0] = _zz_76; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_329[31])); - if(_zz_82)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_78 = _zz_330[19]; - always @ (*) begin - _zz_79[10] = _zz_78; - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7] = _zz_78; - _zz_79[6] = _zz_78; - _zz_79[5] = _zz_78; - _zz_79[4] = _zz_78; - _zz_79[3] = _zz_78; - _zz_79[2] = _zz_78; - _zz_79[1] = _zz_78; - _zz_79[0] = _zz_78; - end - - assign _zz_80 = _zz_331[11]; - always @ (*) begin - _zz_81[18] = _zz_80; - _zz_81[17] = _zz_80; - _zz_81[16] = _zz_80; - _zz_81[15] = _zz_80; - _zz_81[14] = _zz_80; - _zz_81[13] = _zz_80; - _zz_81[12] = _zz_80; - _zz_81[11] = _zz_80; - _zz_81[10] = _zz_80; - _zz_81[9] = _zz_80; - _zz_81[8] = _zz_80; - _zz_81[7] = _zz_80; - _zz_81[6] = _zz_80; - _zz_81[5] = _zz_80; - _zz_81[4] = _zz_80; - _zz_81[3] = _zz_80; - _zz_81[2] = _zz_80; - _zz_81[1] = _zz_80; - _zz_81[0] = _zz_80; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_82 = _zz_332[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_82 = _zz_333[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_83 = _zz_334[19]; - always @ (*) begin - _zz_84[10] = _zz_83; - _zz_84[9] = _zz_83; - _zz_84[8] = _zz_83; - _zz_84[7] = _zz_83; - _zz_84[6] = _zz_83; - _zz_84[5] = _zz_83; - _zz_84[4] = _zz_83; - _zz_84[3] = _zz_83; - _zz_84[2] = _zz_83; - _zz_84[1] = _zz_83; - _zz_84[0] = _zz_83; - end - - assign _zz_85 = _zz_335[11]; - always @ (*) begin - _zz_86[18] = _zz_85; - _zz_86[17] = _zz_85; - _zz_86[16] = _zz_85; - _zz_86[15] = _zz_85; - _zz_86[14] = _zz_85; - _zz_86[13] = _zz_85; - _zz_86[12] = _zz_85; - _zz_86[11] = _zz_85; - _zz_86[10] = _zz_85; - _zz_86[9] = _zz_85; - _zz_86[8] = _zz_85; - _zz_86[7] = _zz_85; - _zz_86[6] = _zz_85; - _zz_86[5] = _zz_85; - _zz_86[4] = _zz_85; - _zz_86[3] = _zz_85; - _zz_86[2] = _zz_85; - _zz_86[1] = _zz_85; - _zz_86[0] = _zz_85; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_414,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_415,_zz_416},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_222; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_225 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_226 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_227 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_260)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_258)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_228 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_258)begin - _zz_228 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_259)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_257)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_259)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_257)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_220 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_247 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3595,168 +3736,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_229 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_230 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_89 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_89 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_246 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_231 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_232 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_231; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_232; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_233 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_233 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_234 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_235 = (CsrPlugin_privilege == 2'b00); - assign _zz_236 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_270)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_270)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_270)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; end - assign _zz_90 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_91[31] = _zz_90; - _zz_91[30] = _zz_90; - _zz_91[29] = _zz_90; - _zz_91[28] = _zz_90; - _zz_91[27] = _zz_90; - _zz_91[26] = _zz_90; - _zz_91[25] = _zz_90; - _zz_91[24] = _zz_90; - _zz_91[23] = _zz_90; - _zz_91[22] = _zz_90; - _zz_91[21] = _zz_90; - _zz_91[20] = _zz_90; - _zz_91[19] = _zz_90; - _zz_91[18] = _zz_90; - _zz_91[17] = _zz_90; - _zz_91[16] = _zz_90; - _zz_91[15] = _zz_90; - _zz_91[14] = _zz_90; - _zz_91[13] = _zz_90; - _zz_91[12] = _zz_90; - _zz_91[11] = _zz_90; - _zz_91[10] = _zz_90; - _zz_91[9] = _zz_90; - _zz_91[8] = _zz_90; - _zz_91[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_92 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_93[31] = _zz_92; - _zz_93[30] = _zz_92; - _zz_93[29] = _zz_92; - _zz_93[28] = _zz_92; - _zz_93[27] = _zz_92; - _zz_93[26] = _zz_92; - _zz_93[25] = _zz_92; - _zz_93[24] = _zz_92; - _zz_93[23] = _zz_92; - _zz_93[22] = _zz_92; - _zz_93[21] = _zz_92; - _zz_93[20] = _zz_92; - _zz_93[19] = _zz_92; - _zz_93[18] = _zz_92; - _zz_93[17] = _zz_92; - _zz_93[16] = _zz_92; - _zz_93[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_291) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_91; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_93; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3775,62 +3927,63 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_94 = {(((decode_INSTRUCTION & _zz_417) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}; - assign _zz_100 = _zz_94[2 : 1]; - assign _zz_56 = _zz_100; - assign _zz_101 = _zz_94[7 : 6]; - assign _zz_55 = _zz_101; - assign _zz_102 = _zz_94[9 : 8]; - assign _zz_54 = _zz_102; - assign _zz_103 = _zz_94[19 : 18]; - assign _zz_53 = _zz_103; - assign _zz_104 = _zz_94[22 : 21]; - assign _zz_52 = _zz_104; - assign _zz_105 = _zz_94[24 : 23]; - assign _zz_51 = _zz_105; - assign _zz_106 = _zz_94[27 : 26]; - assign _zz_50 = _zz_106; - assign _zz_107 = _zz_94[29 : 29]; - assign _zz_49 = _zz_107; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1) != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[34 : 34]; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_248; - assign decode_RegFilePlugin_rs2Data = _zz_249; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_108)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_108)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_108)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3839,355 +3992,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_109 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_109 = {31'd0, _zz_338}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_109 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_110 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_110 = {29'd0, _zz_339}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_110 = {27'd0, _zz_340}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_111 = _zz_341[11]; - always @ (*) begin - _zz_112[19] = _zz_111; - _zz_112[18] = _zz_111; - _zz_112[17] = _zz_111; - _zz_112[16] = _zz_111; - _zz_112[15] = _zz_111; - _zz_112[14] = _zz_111; - _zz_112[13] = _zz_111; - _zz_112[12] = _zz_111; - _zz_112[11] = _zz_111; - _zz_112[10] = _zz_111; - _zz_112[9] = _zz_111; - _zz_112[8] = _zz_111; - _zz_112[7] = _zz_111; - _zz_112[6] = _zz_111; - _zz_112[5] = _zz_111; - _zz_112[4] = _zz_111; - _zz_112[3] = _zz_111; - _zz_112[2] = _zz_111; - _zz_112[1] = _zz_111; - _zz_112[0] = _zz_111; - end - - assign _zz_113 = _zz_342[11]; - always @ (*) begin - _zz_114[19] = _zz_113; - _zz_114[18] = _zz_113; - _zz_114[17] = _zz_113; - _zz_114[16] = _zz_113; - _zz_114[15] = _zz_113; - _zz_114[14] = _zz_113; - _zz_114[13] = _zz_113; - _zz_114[12] = _zz_113; - _zz_114[11] = _zz_113; - _zz_114[10] = _zz_113; - _zz_114[9] = _zz_113; - _zz_114[8] = _zz_113; - _zz_114[7] = _zz_113; - _zz_114[6] = _zz_113; - _zz_114[5] = _zz_113; - _zz_114[4] = _zz_113; - _zz_114[3] = _zz_113; - _zz_114[2] = _zz_113; - _zz_114[1] = _zz_113; - _zz_114[0] = _zz_113; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_115 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_115 = _zz_41; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_343; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_116[0] = execute_SRC1[31]; - _zz_116[1] = execute_SRC1[30]; - _zz_116[2] = execute_SRC1[29]; - _zz_116[3] = execute_SRC1[28]; - _zz_116[4] = execute_SRC1[27]; - _zz_116[5] = execute_SRC1[26]; - _zz_116[6] = execute_SRC1[25]; - _zz_116[7] = execute_SRC1[24]; - _zz_116[8] = execute_SRC1[23]; - _zz_116[9] = execute_SRC1[22]; - _zz_116[10] = execute_SRC1[21]; - _zz_116[11] = execute_SRC1[20]; - _zz_116[12] = execute_SRC1[19]; - _zz_116[13] = execute_SRC1[18]; - _zz_116[14] = execute_SRC1[17]; - _zz_116[15] = execute_SRC1[16]; - _zz_116[16] = execute_SRC1[15]; - _zz_116[17] = execute_SRC1[14]; - _zz_116[18] = execute_SRC1[13]; - _zz_116[19] = execute_SRC1[12]; - _zz_116[20] = execute_SRC1[11]; - _zz_116[21] = execute_SRC1[10]; - _zz_116[22] = execute_SRC1[9]; - _zz_116[23] = execute_SRC1[8]; - _zz_116[24] = execute_SRC1[7]; - _zz_116[25] = execute_SRC1[6]; - _zz_116[26] = execute_SRC1[5]; - _zz_116[27] = execute_SRC1[4]; - _zz_116[28] = execute_SRC1[3]; - _zz_116[29] = execute_SRC1[2]; - _zz_116[30] = execute_SRC1[1]; - _zz_116[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); - always @ (*) begin - _zz_117[0] = memory_SHIFT_RIGHT[31]; - _zz_117[1] = memory_SHIFT_RIGHT[30]; - _zz_117[2] = memory_SHIFT_RIGHT[29]; - _zz_117[3] = memory_SHIFT_RIGHT[28]; - _zz_117[4] = memory_SHIFT_RIGHT[27]; - _zz_117[5] = memory_SHIFT_RIGHT[26]; - _zz_117[6] = memory_SHIFT_RIGHT[25]; - _zz_117[7] = memory_SHIFT_RIGHT[24]; - _zz_117[8] = memory_SHIFT_RIGHT[23]; - _zz_117[9] = memory_SHIFT_RIGHT[22]; - _zz_117[10] = memory_SHIFT_RIGHT[21]; - _zz_117[11] = memory_SHIFT_RIGHT[20]; - _zz_117[12] = memory_SHIFT_RIGHT[19]; - _zz_117[13] = memory_SHIFT_RIGHT[18]; - _zz_117[14] = memory_SHIFT_RIGHT[17]; - _zz_117[15] = memory_SHIFT_RIGHT[16]; - _zz_117[16] = memory_SHIFT_RIGHT[15]; - _zz_117[17] = memory_SHIFT_RIGHT[14]; - _zz_117[18] = memory_SHIFT_RIGHT[13]; - _zz_117[19] = memory_SHIFT_RIGHT[12]; - _zz_117[20] = memory_SHIFT_RIGHT[11]; - _zz_117[21] = memory_SHIFT_RIGHT[10]; - _zz_117[22] = memory_SHIFT_RIGHT[9]; - _zz_117[23] = memory_SHIFT_RIGHT[8]; - _zz_117[24] = memory_SHIFT_RIGHT[7]; - _zz_117[25] = memory_SHIFT_RIGHT[6]; - _zz_117[26] = memory_SHIFT_RIGHT[5]; - _zz_117[27] = memory_SHIFT_RIGHT[4]; - _zz_117[28] = memory_SHIFT_RIGHT[3]; - _zz_117[29] = memory_SHIFT_RIGHT[2]; - _zz_117[30] = memory_SHIFT_RIGHT[1]; - _zz_117[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_118 = 1'b0; - if(_zz_271)begin - if(_zz_272)begin - if(_zz_123)begin - _zz_118 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_273)begin - if(_zz_274)begin - if(_zz_125)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_275)begin - if(_zz_276)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_118 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_119 = 1'b0; - if(_zz_271)begin - if(_zz_272)begin - if(_zz_124)begin - _zz_119 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_273)begin - if(_zz_274)begin - if(_zz_126)begin - _zz_119 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_275)begin - if(_zz_276)begin - if(_zz_128)begin - _zz_119 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_119 = 1'b0; - end - end - - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_129 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_129 == 3'b000)) begin - _zz_130 = execute_BranchPlugin_eq; - end else if((_zz_129 == 3'b001)) begin - _zz_130 = (! execute_BranchPlugin_eq); - end else if((((_zz_129 & 3'b101) == 3'b101))) begin - _zz_130 = (! execute_SRC_LESS); - end else begin - _zz_130 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_131 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_131 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_131 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_131 = _zz_130; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_132 = _zz_350[11]; - always @ (*) begin - _zz_133[19] = _zz_132; - _zz_133[18] = _zz_132; - _zz_133[17] = _zz_132; - _zz_133[16] = _zz_132; - _zz_133[15] = _zz_132; - _zz_133[14] = _zz_132; - _zz_133[13] = _zz_132; - _zz_133[12] = _zz_132; - _zz_133[11] = _zz_132; - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; - end - - assign _zz_134 = _zz_351[19]; - always @ (*) begin - _zz_135[10] = _zz_134; - _zz_135[9] = _zz_134; - _zz_135[8] = _zz_134; - _zz_135[7] = _zz_134; - _zz_135[6] = _zz_134; - _zz_135[5] = _zz_134; - _zz_135[4] = _zz_134; - _zz_135[3] = _zz_134; - _zz_135[2] = _zz_134; - _zz_135[1] = _zz_134; - _zz_135[0] = _zz_134; - end - - assign _zz_136 = _zz_352[11]; - always @ (*) begin - _zz_137[18] = _zz_136; - _zz_137[17] = _zz_136; - _zz_137[16] = _zz_136; - _zz_137[15] = _zz_136; - _zz_137[14] = _zz_136; - _zz_137[13] = _zz_136; - _zz_137[12] = _zz_136; - _zz_137[11] = _zz_136; - _zz_137[10] = _zz_136; - _zz_137[9] = _zz_136; - _zz_137[8] = _zz_136; - _zz_137[7] = _zz_136; - _zz_137[6] = _zz_136; - _zz_137[5] = _zz_136; - _zz_137[4] = _zz_136; - _zz_137[3] = _zz_136; - _zz_137[2] = _zz_136; - _zz_137[1] = _zz_136; - _zz_137[0] = _zz_136; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_138 = (_zz_353[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_138 = _zz_354[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_138 = _zz_355[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -4196,183 +4372,195 @@ module VexRiscv ( endcase end - assign _zz_139 = _zz_356[11]; - always @ (*) begin - _zz_140[19] = _zz_139; - _zz_140[18] = _zz_139; - _zz_140[17] = _zz_139; - _zz_140[16] = _zz_139; - _zz_140[15] = _zz_139; - _zz_140[14] = _zz_139; - _zz_140[13] = _zz_139; - _zz_140[12] = _zz_139; - _zz_140[11] = _zz_139; - _zz_140[10] = _zz_139; - _zz_140[9] = _zz_139; - _zz_140[8] = _zz_139; - _zz_140[7] = _zz_139; - _zz_140[6] = _zz_139; - _zz_140[5] = _zz_139; - _zz_140[4] = _zz_139; - _zz_140[3] = _zz_139; - _zz_140[2] = _zz_139; - _zz_140[1] = _zz_139; - _zz_140[0] = _zz_139; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_594,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_595,_zz_596},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_359}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_141 = _zz_357[19]; - always @ (*) begin - _zz_142[10] = _zz_141; - _zz_142[9] = _zz_141; - _zz_142[8] = _zz_141; - _zz_142[7] = _zz_141; - _zz_142[6] = _zz_141; - _zz_142[5] = _zz_141; - _zz_142[4] = _zz_141; - _zz_142[3] = _zz_141; - _zz_142[2] = _zz_141; - _zz_142[1] = _zz_141; - _zz_142[0] = _zz_141; - end - - assign _zz_143 = _zz_358[11]; - always @ (*) begin - _zz_144[18] = _zz_143; - _zz_144[17] = _zz_143; - _zz_144[16] = _zz_143; - _zz_144[15] = _zz_143; - _zz_144[14] = _zz_143; - _zz_144[13] = _zz_143; - _zz_144[12] = _zz_143; - _zz_144[11] = _zz_143; - _zz_144[10] = _zz_143; - _zz_144[9] = _zz_143; - _zz_144[8] = _zz_143; - _zz_144[7] = _zz_143; - _zz_144[6] = _zz_143; - _zz_144[5] = _zz_143; - _zz_144[4] = _zz_143; - _zz_144[3] = _zz_143; - _zz_144[2] = _zz_143; - _zz_144[1] = _zz_143; - _zz_144[0] = _zz_143; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; - always @ (*) begin + always @(*) begin BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); - if(1'b0)begin + if(when_BranchPlugin_l296) begin BranchPlugin_branchExceptionPort_valid = 1'b0; end end assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign when_BranchPlugin_l296 = 1'b0; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_149 = _zz_360[0]; - assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_151 = _zz_362[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_261)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_264)begin + if(_zz_when_1) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4383,8 +4571,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4394,199 +4582,208 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_csr_2820) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2821) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_csr_2822) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2823) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_csr_2824) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2825) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_csr_2826) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2827) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_csr_2828) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2829) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_csr_2830) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2831) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_csr_2832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2833) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_2834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_2835) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_277)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_278)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_279)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_278)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_279)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4599,106 +4796,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_277)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_277)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_292) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); - assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_364; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; - assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_168 = _zz_365[7]; - always @ (*) begin - _zz_169[23] = _zz_168; - _zz_169[22] = _zz_168; - _zz_169[21] = _zz_168; - _zz_169[20] = _zz_168; - _zz_169[19] = _zz_168; - _zz_169[18] = _zz_168; - _zz_169[17] = _zz_168; - _zz_169[16] = _zz_168; - _zz_169[15] = _zz_168; - _zz_169[14] = _zz_168; - _zz_169[13] = _zz_168; - _zz_169[12] = _zz_168; - _zz_169[11] = _zz_168; - _zz_169[10] = _zz_168; - _zz_169[9] = _zz_168; - _zz_169[8] = _zz_168; - _zz_169[7] = _zz_168; - _zz_169[6] = _zz_168; - _zz_169[5] = _zz_168; - _zz_169[4] = _zz_168; - _zz_169[3] = _zz_168; - _zz_169[2] = _zz_168; - _zz_169[1] = _zz_168; - _zz_169[0] = _zz_168; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : begin - _zz_170 = execute_RS2; - end - default : begin - _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 24]}; - end - endcase - end - - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; - assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); - assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); - assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); - assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); - always @ (*) begin - CfuPlugin_joinException_valid = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if(memory_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); - end - end - end - - assign CfuPlugin_joinException_payload_code = 4'b1111; - assign CfuPlugin_joinException_payload_badAddr = 32'h0; - always @ (*) begin - memory_CfuPlugin_rsp_ready = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); - end - end - assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_280) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4711,8 +4851,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_280) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4731,58 +4871,69 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_366) + $signed(_zz_367)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_256)begin - if(_zz_281)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_282)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_372); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_373 : _zz_374); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_375[31:0]; - assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_175[31 : 0] = execute_RS1; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; end - assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_177 != 32'h0); - always @ (*) begin + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_283) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end end @@ -4792,9 +4943,9 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_178))begin + if(when_DebugPlugin_l244) begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4803,12 +4954,13 @@ module VexRiscv ( end end - always @ (*) begin + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_283) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin IBusCachedPlugin_injectionPort_valid = 1'b1; end end @@ -4819,38 +4971,182 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_29 = decode_SRC1_CTRL; - assign _zz_27 = _zz_56; - assign _zz_43 = decode_to_execute_SRC1_CTRL; - assign _zz_26 = decode_ALU_CTRL; - assign _zz_24 = _zz_55; - assign _zz_44 = decode_to_execute_ALU_CTRL; - assign _zz_23 = decode_SRC2_CTRL; - assign _zz_21 = _zz_54; - assign _zz_42 = decode_to_execute_SRC2_CTRL; - assign _zz_20 = decode_ALU_BITWISE_CTRL; - assign _zz_18 = _zz_53; - assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_17 = decode_SHIFT_CTRL; - assign _zz_14 = execute_SHIFT_CTRL; - assign _zz_15 = _zz_52; - assign _zz_40 = decode_to_execute_SHIFT_CTRL; - assign _zz_39 = execute_to_memory_SHIFT_CTRL; - assign _zz_12 = decode_BRANCH_CTRL; - assign _zz_58 = _zz_51; - assign _zz_36 = decode_to_execute_BRANCH_CTRL; - assign _zz_10 = decode_ENV_CTRL; - assign _zz_7 = execute_ENV_CTRL; - assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_50; - assign _zz_34 = decode_to_execute_ENV_CTRL; - assign _zz_33 = execute_to_memory_ENV_CTRL; - assign _zz_35 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_49; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready); + assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)); + assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + end + + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2; + end + default : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @(*) begin + CfuPlugin_bus_rsp_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); + assign when_GenCoreDefault_l367 = _zz_when_GenCoreDefault_l367[0]; + assign when_GenCoreDefault_l367_1 = _zz_when_GenCoreDefault_l367_1[0]; + assign when_GenCoreDefault_l367_2 = _zz_when_GenCoreDefault_l367_2[0]; + assign when_GenCoreDefault_l367_3 = _zz_when_GenCoreDefault_l367_3[0]; + assign when_GenCoreDefault_l367_4 = _zz_when_GenCoreDefault_l367_4[0]; + assign when_GenCoreDefault_l367_5 = _zz_when_GenCoreDefault_l367_5[0]; + assign when_GenCoreDefault_l367_6 = _zz_when_GenCoreDefault_l367_6[0]; + assign when_GenCoreDefault_l367_7 = _zz_when_GenCoreDefault_l367_7[0]; + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_64 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4871,9 +5167,15 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_179) + case(switch_Fetcher_l362) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4882,296 +5184,340 @@ module VexRiscv ( endcase end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_180[12 : 0] = 13'h1000; - _zz_180[25 : 20] = 6'h20; + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_28 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_29 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_30 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_31 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_32 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_33 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_34 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_35 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_36 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_37 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_38 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_39 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[13 : 0] = 14'h2000; + _zz_CsrPlugin_csrMapping_readDataInit_10[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_181[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_182[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_183[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_184[31 : 30] = CsrPlugin_misa_base; - _zz_184[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_14[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_15[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_186 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_186[11 : 11] = CsrPlugin_mip_MEIP; - _zz_186[7 : 7] = CsrPlugin_mip_MTIP; - _zz_186[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_187 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_187[11 : 11] = CsrPlugin_mie_MEIE; - _zz_187[7 : 7] = CsrPlugin_mie_MTIE; - _zz_187[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_188 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_188[31 : 2] = CsrPlugin_mtvec_base; - _zz_188[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_189 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_189[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_190 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_190[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_191 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_21[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_192 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_192[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_193 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_194 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_195 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_196 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_197 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_198 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_28[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_199 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_29 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_29[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_200 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_30 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_30[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_201 = 32'h0; - if(execute_CsrPlugin_csr_2820)begin - _zz_201[31 : 0] = _zz_152; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_31 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_31[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_202 = 32'h0; - if(execute_CsrPlugin_csr_2822)begin - _zz_202[31 : 0] = _zz_154; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_32 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_32[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - always @ (*) begin - _zz_203 = 32'h0; - if(execute_CsrPlugin_csr_2824)begin - _zz_203[31 : 0] = _zz_156; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_33 = 32'h0; + if(execute_CsrPlugin_csr_2820) begin + _zz_CsrPlugin_csrMapping_readDataInit_33[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; end end - always @ (*) begin - _zz_204 = 32'h0; - if(execute_CsrPlugin_csr_2826)begin - _zz_204[31 : 0] = _zz_158; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_34 = 32'h0; + if(execute_CsrPlugin_csr_2822) begin + _zz_CsrPlugin_csrMapping_readDataInit_34[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; end end - always @ (*) begin - _zz_205 = 32'h0; - if(execute_CsrPlugin_csr_2828)begin - _zz_205[31 : 0] = _zz_160; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_35 = 32'h0; + if(execute_CsrPlugin_csr_2824) begin + _zz_CsrPlugin_csrMapping_readDataInit_35[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_4; end end - always @ (*) begin - _zz_206 = 32'h0; - if(execute_CsrPlugin_csr_2830)begin - _zz_206[31 : 0] = _zz_162; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_36 = 32'h0; + if(execute_CsrPlugin_csr_2826) begin + _zz_CsrPlugin_csrMapping_readDataInit_36[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_5; end end - always @ (*) begin - _zz_207 = 32'h0; - if(execute_CsrPlugin_csr_2832)begin - _zz_207[31 : 0] = _zz_164; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_37 = 32'h0; + if(execute_CsrPlugin_csr_2828) begin + _zz_CsrPlugin_csrMapping_readDataInit_37[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_6; end end - always @ (*) begin - _zz_208 = 32'h0; - if(execute_CsrPlugin_csr_2834)begin - _zz_208[31 : 0] = _zz_166; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_38 = 32'h0; + if(execute_CsrPlugin_csr_2830) begin + _zz_CsrPlugin_csrMapping_readDataInit_38[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_7; end end - always @ (*) begin - _zz_209 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_209[31 : 0] = _zz_176; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_39 = 32'h0; + if(execute_CsrPlugin_csr_2832) begin + _zz_CsrPlugin_csrMapping_readDataInit_39[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_8; end end - always @ (*) begin - _zz_210 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_210[31 : 0] = _zz_177; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_40 = 32'h0; + if(execute_CsrPlugin_csr_2834) begin + _zz_CsrPlugin_csrMapping_readDataInit_40[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_9; end end - assign execute_CsrPlugin_readData = (((((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_597 | _zz_184) | (_zz_185 | _zz_186))) | (((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194)))) | ((((_zz_195 | _zz_196) | (_zz_197 | _zz_198)) | ((_zz_199 | _zz_200) | (_zz_201 | _zz_202))) | (((_zz_203 | _zz_204) | (_zz_205 | _zz_206)) | ((_zz_207 | _zz_208) | (_zz_209 | _zz_210))))); - assign iBusWishbone_ADR = {_zz_392,_zz_211}; - assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | (_zz_CsrPlugin_csrMapping_readDataInit_12 | _zz_CsrPlugin_csrMapping_readDataInit_13)) | ((_zz_CsrPlugin_csrMapping_readDataInit_41 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26) | (_zz_CsrPlugin_csrMapping_readDataInit_27 | _zz_CsrPlugin_csrMapping_readDataInit_28)) | ((_zz_CsrPlugin_csrMapping_readDataInit_29 | _zz_CsrPlugin_csrMapping_readDataInit_30) | (_zz_CsrPlugin_csrMapping_readDataInit_31 | _zz_CsrPlugin_csrMapping_readDataInit_32))) | (((_zz_CsrPlugin_csrMapping_readDataInit_33 | _zz_CsrPlugin_csrMapping_readDataInit_34) | (_zz_CsrPlugin_csrMapping_readDataInit_35 | _zz_CsrPlugin_csrMapping_readDataInit_36)) | ((_zz_CsrPlugin_csrMapping_readDataInit_37 | _zz_CsrPlugin_csrMapping_readDataInit_38) | (_zz_CsrPlugin_csrMapping_readDataInit_39 | _zz_CsrPlugin_csrMapping_readDataInit_40))))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_284)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_284)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_212; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_218 = (dBus_cmd_payload_length != 3'b000); - assign _zz_214 = dBus_cmd_valid; - assign _zz_216 = dBus_cmd_payload_wr; - assign _zz_217 = (_zz_213 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_215 && (_zz_216 || _zz_217)); - assign dBusWishbone_ADR = ((_zz_218 ? {{dBus_cmd_payload_address[31 : 5],_zz_213},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_218 ? (_zz_217 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_216 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_216; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_215 = (_zz_214 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_214; - assign dBusWishbone_STB = _zz_214; - assign dBus_rsp_valid = _zz_219; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_72 <= 1'b0; - _zz_74 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_87; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_88; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_108 <= 1'b1; - _zz_120 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -5191,165 +5537,165 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - memory_DivPlugin_div_counter_value <= 6'h0; - _zz_176 <= 32'h0; + CfuPlugin_bus_rsp_rValid <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_179 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_211 <= 3'b000; - _zz_212 <= 1'b0; - _zz_213 <= 3'b000; - _zz_219 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_72 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_70)begin - _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_74 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_74 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_285)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_108 <= 1'b0; - _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_286)begin - if(_zz_287)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_288)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_289)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5360,8 +5706,8 @@ module VexRiscv ( end endcase end - if(_zz_267)begin - case(_zz_269) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5371,185 +5717,181 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(execute_CfuPlugin_schedule)begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(execute_CfuPlugin_schedule) begin execute_CfuPlugin_hold <= 1'b1; end - if(CfuPlugin_bus_cmd_ready)begin + if(CfuPlugin_bus_cmd_ready) begin execute_CfuPlugin_hold <= 1'b0; end - if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + if(CfuPlugin_bus_cmd_fire) begin execute_CfuPlugin_fired <= 1'b1; end - if((! execute_arbitration_isStuckByOthers))begin + if(when_CfuPlugin_l171) begin execute_CfuPlugin_fired <= 1'b0; end - if(memory_CfuPlugin_rsp_ready)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + if(CfuPlugin_bus_rsp_valid) begin + CfuPlugin_bus_rsp_rValid <= 1'b1; end - if(_zz_290)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + if(CfuPlugin_bus_rsp_rsp_ready) begin + CfuPlugin_bus_rsp_rValid <= 1'b0; end - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + if(when_Pipeline_l124_62) begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_179) + case(switch_Fetcher_l362) 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_179 <= 3'b001; + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; end end 3'b001 : begin - _zz_179 <= 3'b010; + switch_Fetcher_l362 <= 3'b010; end 3'b010 : begin - _zz_179 <= 3'b011; + switch_Fetcher_l362 <= 3'b011; end 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_179 <= 3'b100; + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; end end 3'b100 : begin - _zz_179 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; end default : begin end endcase - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_385[0]; - CsrPlugin_mstatus_MIE <= _zz_386[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_388[0]; - CsrPlugin_mie_MTIE <= _zz_389[0]; - CsrPlugin_mie_MSIE <= _zz_390[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_284)begin - if(iBusWishbone_ACK)begin - _zz_211 <= (_zz_211 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_214 && _zz_215))begin - _zz_213 <= (_zz_213 + 3'b001); - if(_zz_217)begin - _zz_213 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_219 <= ((_zz_214 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_75 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_285)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_121 <= _zz_46[11 : 7]; - _zz_122 <= _zz_57; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_261)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(_zz_264)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_when_1) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; - end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_286)begin - if(_zz_287)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_288)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_289)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5557,569 +5899,579 @@ module VexRiscv ( end endcase end - if(_zz_153[0])begin - _zz_152 <= (_zz_152 + 32'h00000001); + if(when_MulDivIterativePlugin_l126) begin + memory_DivPlugin_div_done <= 1'b1; end - if(_zz_155[0])begin - _zz_154 <= (_zz_154 + 32'h00000001); + if(when_MulDivIterativePlugin_l126_1) begin + memory_DivPlugin_div_done <= 1'b0; end - if(_zz_157[0])begin - _zz_156 <= (_zz_156 + 32'h00000001); + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; + end + end end - if(_zz_159[0])begin - _zz_158 <= (_zz_158 + 32'h00000001); + if(when_MulDivIterativePlugin_l162) begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end - if(_zz_161[0])begin - _zz_160 <= (_zz_160 + 32'h00000001); + externalInterruptArray_regNext <= externalInterruptArray; + if(CfuPlugin_bus_rsp_ready) begin + CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end - if(_zz_163[0])begin - _zz_162 <= (_zz_162 + 32'h00000001); + if(when_GenCoreDefault_l367) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= (_zz_CsrPlugin_csrMapping_readDataInit_2 + 32'h00000001); end - if(_zz_165[0])begin - _zz_164 <= (_zz_164 + 32'h00000001); + if(when_GenCoreDefault_l367_1) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= (_zz_CsrPlugin_csrMapping_readDataInit_3 + 32'h00000001); end - if(_zz_167[0])begin - _zz_166 <= (_zz_166 + 32'h00000001); + if(when_GenCoreDefault_l367_2) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= (_zz_CsrPlugin_csrMapping_readDataInit_4 + 32'h00000001); end - if(_zz_290)begin - CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + if(when_GenCoreDefault_l367_3) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= (_zz_CsrPlugin_csrMapping_readDataInit_5 + 32'h00000001); end - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_done <= 1'b1; + if(when_GenCoreDefault_l367_4) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= (_zz_CsrPlugin_csrMapping_readDataInit_6 + 32'h00000001); end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + if(when_GenCoreDefault_l367_5) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= (_zz_CsrPlugin_csrMapping_readDataInit_7 + 32'h00000001); end - if(_zz_256)begin - if(_zz_281)begin - memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; - memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_376[31:0]; - end - end + if(when_GenCoreDefault_l367_6) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= (_zz_CsrPlugin_csrMapping_readDataInit_8 + 32'h00000001); end - if(_zz_282)begin - memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_382); - memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_384); - memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(when_GenCoreDefault_l367_7) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= (_zz_CsrPlugin_csrMapping_readDataInit_9 + 32'h00000001); end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_41; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_8) begin memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_28; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_25; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_22; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_16; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_11; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6; - end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + end + if(when_Pipeline_l124_45) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_52) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_53) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + if(when_Pipeline_l124_54) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + if(when_Pipeline_l124_55) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_63) begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + end + if(when_Pipeline_l124_64) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if(when_CsrPlugin_l1264_23) begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(when_CsrPlugin_l1264_24) begin execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_25) begin execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_26) begin execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_27) begin execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_28) begin execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_29) begin execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_30) begin execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_31) begin execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_32) begin execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_33) begin execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_34) begin execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_35) begin execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_36) begin execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_37) begin execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_38) begin execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_39) begin execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); - end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_387[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_391[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2820)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2820) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2821) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2822)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2822) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2823) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_1 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2824)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2824) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2825) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2826)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2826) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2827) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2828)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2828) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2829) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2830)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2830) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2831) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2832)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2832) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2833) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2834)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2834) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2835) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end - always @ (posedge clk) begin + always @(posedge clk) begin DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin + if(debug_bus_cmd_ready) begin DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_57; + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; end - _zz_178 <= debug_bus_cmd_payload_address[2]; - if(_zz_263)begin + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin + always @(posedge clk) begin if(debugReset) begin DebugPlugin_resetIt <= 1'b0; DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + if(when_DebugPlugin_l225) begin DebugPlugin_godmode <= 1'b1; end - if(debug_bus_cmd_valid)begin - case(_zz_283) + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin + if(when_DebugPlugin_l260) begin DebugPlugin_resetIt <= 1'b1; end - if(debug_bus_cmd_payload_data[24])begin + if(when_DebugPlugin_l260_1) begin DebugPlugin_resetIt <= 1'b0; end - if(debug_bus_cmd_payload_data[17])begin + if(when_DebugPlugin_l261) begin DebugPlugin_haltIt <= 1'b1; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l261_1) begin DebugPlugin_haltIt <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l262) begin DebugPlugin_haltedByBreak <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l263) begin DebugPlugin_godmode <= 1'b0; end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end end end default : begin end endcase end - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_268)begin - if(decode_arbitration_isValid)begin + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin DebugPlugin_haltIt <= 1'b1; end end @@ -6132,9 +6484,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -6156,6 +6507,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -6171,9 +6523,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -6181,7 +6534,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -6190,99 +6543,81 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_19; - reg [31:0] _zz_20; - reg [21:0] _zz_21; - reg [31:0] _zz_22; - wire _zz_23; - wire _zz_24; - wire _zz_25; - wire _zz_26; - wire _zz_27; - wire _zz_28; - wire _zz_29; - wire [0:0] _zz_30; - wire [0:0] _zz_31; - wire [0:0] _zz_32; - wire [0:0] _zz_33; - wire [0:0] _zz_34; - wire [0:0] _zz_35; - wire [2:0] _zz_36; - wire [2:0] _zz_37; - wire [21:0] _zz_38; - wire [21:0] _zz_39; + reg [20:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [20:0] _zz_ways_0_tags_port; + wire [10:0] _zz_stage0_dataColisions; + wire [10:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; - reg _zz_3; - reg _zz_4; wire haltCpu; reg tagsReadCmd_valid; - reg [6:0] tagsReadCmd_payload; + reg [7:0] tagsReadCmd_payload; reg tagsWriteCmd_valid; - reg [1:0] tagsWriteCmd_payload_way; - reg [6:0] tagsWriteCmd_payload_address; + reg [0:0] tagsWriteCmd_payload_way; + reg [7:0] tagsWriteCmd_payload_address; reg tagsWriteCmd_payload_data_valid; reg tagsWriteCmd_payload_data_error; - reg [19:0] tagsWriteCmd_payload_data_address; + reg [18:0] tagsWriteCmd_payload_data_address; reg tagsWriteLastCmd_valid; - reg [1:0] tagsWriteLastCmd_payload_way; - reg [6:0] tagsWriteLastCmd_payload_address; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [7:0] tagsWriteLastCmd_payload_address; reg tagsWriteLastCmd_payload_data_valid; reg tagsWriteLastCmd_payload_data_error; - reg [19:0] tagsWriteLastCmd_payload_data_address; + reg [18:0] tagsWriteLastCmd_payload_data_address; reg dataReadCmd_valid; - reg [9:0] dataReadCmd_payload; + reg [10:0] dataReadCmd_payload; reg dataWriteCmd_valid; - reg [1:0] dataWriteCmd_payload_way; - reg [9:0] dataWriteCmd_payload_address; + reg [0:0] dataWriteCmd_payload_way; + reg [10:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_5; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; - wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_6; - wire _zz_7; + wire [18:0] ways_0_tagsReadRsp_address; + wire [20:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; - wire _zz_8; - wire ways_1_tagsReadRsp_valid; - wire ways_1_tagsReadRsp_error; - wire [19:0] ways_1_tagsReadRsp_address; - wire [21:0] _zz_9; - wire _zz_10; - wire [31:0] ways_1_dataReadRspMem; - wire [31:0] ways_1_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_11; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; - reg [1:0] stage0_dataColisions; - wire [9:0] _zz_12; - wire [3:0] _zz_13; - wire [1:0] stage0_wayInvalidate; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; - wire [1:0] stageA_wayHits; - reg [1:0] _zz_14; - reg [1:0] stageA_wayInvalidate; - reg [1:0] stage0_dataColisions_regNextWhen; - reg [1:0] _zz_15; - wire [9:0] _zz_16; - wire [3:0] _zz_17; - wire [1:0] stageA_dataColisions; + wire [0:0] stageA_wayHits; + wire when_DataCache_l763_2; + reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_stageA_dataColisions; + wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -6292,27 +6627,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; - reg [19:0] stageB_tagsReadRsp_0_address; - reg stageB_tagsReadRsp_1_valid; - reg stageB_tagsReadRsp_1_error; - reg [19:0] stageB_tagsReadRsp_1_address; + reg [18:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; - reg [31:0] stageB_dataReadRsp_1; - reg [1:0] stageB_wayInvalidate; + wire when_DataCache_l812; + reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; - reg [1:0] stageB_dataColisions; + wire when_DataCache_l812_1; + reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; - reg [1:0] stageB_waysHitsBeforeInvalidate; - wire [1:0] stageB_waysHits; + wire when_DataCache_l812_3; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [8:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -6320,10 +6661,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - reg [1:0] _zz_18; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -6331,432 +6680,359 @@ module DataCache ( reg [2:0] loader_counter_value; wire loader_counter_willOverflowIfInc; wire loader_counter_willOverflow; - reg [1:0] loader_waysAllocator; + reg [0:0] loader_waysAllocator; reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_40; - reg [7:0] _zz_41; - reg [7:0] _zz_42; - reg [7:0] _zz_43; - (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol0 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol1 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol2 [0:1023]; - (* ram_style = "block" *) reg [7:0] ways_1_data_symbol3 [0:1023]; - reg [7:0] _zz_44; - reg [7:0] _zz_45; - reg [7:0] _zz_46; - reg [7:0] _zz_47; - - assign _zz_23 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_24 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_25 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_26 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_27 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_28 = (! stageB_flusher_hold); - assign _zz_29 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_30 = _zz_6[0 : 0]; - assign _zz_31 = _zz_6[1 : 1]; - assign _zz_32 = _zz_9[0 : 0]; - assign _zz_33 = _zz_9[1 : 1]; - assign _zz_34 = 1'b1; - assign _zz_35 = loader_counter_willIncrement; - assign _zz_36 = {2'd0, _zz_35}; - assign _zz_37 = {loader_waysAllocator,loader_waysAllocator[1]}; - assign _zz_38 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - assign _zz_39 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_5) begin - _zz_19 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin - if(_zz_4) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_38; - end - end - - always @ (*) begin - _zz_20 = {_zz_43, _zz_42, _zz_41, _zz_40}; - end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_40 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_41 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_42 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_43 <= ways_0_data_symbol3[dataReadCmd_payload]; - end - end - - always @ (posedge clk) begin - if(dataWriteCmd_payload_mask[0] && _zz_3) begin - ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; - end - if(dataWriteCmd_payload_mask[1] && _zz_3) begin - ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; - end - if(dataWriteCmd_payload_mask[2] && _zz_3) begin - ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; - end - if(dataWriteCmd_payload_mask[3] && _zz_3) begin - ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; - end - end - - always @ (posedge clk) begin - if(_zz_8) begin - _zz_21 <= ways_1_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + wire when_DataCache_l1107; + wire when_DataCache_l1110; + (* ram_style = "block" *) reg [20:0] ways_0_tags [0:255]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:2047]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:2047]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[12 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[12 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_1_tags[tagsWriteCmd_payload_address] <= _zz_39; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_22 = {_zz_47, _zz_46, _zz_45, _zz_44}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_10) begin - _zz_44 <= ways_1_data_symbol0[dataReadCmd_payload]; - _zz_45 <= ways_1_data_symbol1[dataReadCmd_payload]; - _zz_46 <= ways_1_data_symbol2[dataReadCmd_payload]; - _zz_47 <= ways_1_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin - ways_1_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end if(dataWriteCmd_payload_mask[1] && _zz_1) begin - ways_1_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; end if(dataWriteCmd_payload_mask[2] && _zz_1) begin - ways_1_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; end if(dataWriteCmd_payload_mask[3] && _zz_1) begin - ways_1_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[1]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[1]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end - always @ (*) begin - _zz_3 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin - _zz_3 = 1'b1; - end - end - - always @ (*) begin - _zz_4 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin - _zz_4 = 1'b1; - end - end - assign haltCpu = 1'b0; - assign _zz_5 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_6 = _zz_19; - assign ways_0_tagsReadRsp_valid = _zz_30[0]; - assign ways_0_tagsReadRsp_error = _zz_31[0]; - assign ways_0_tagsReadRsp_address = _zz_6[21 : 2]; - assign _zz_7 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_20; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[20 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - assign _zz_8 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_9 = _zz_21; - assign ways_1_tagsReadRsp_valid = _zz_32[0]; - assign ways_1_tagsReadRsp_error = _zz_33[0]; - assign ways_1_tagsReadRsp_address = _zz_9[21 : 2]; - assign _zz_10 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_1_dataReadRspMem = _zz_22; - assign ways_1_dataReadRsp = ways_1_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_23)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_23)begin - tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + always @(*) begin + tagsReadCmd_payload = 8'bxxxxxxxx; + if(when_DataCache_l656) begin + tagsReadCmd_payload = io_cpu_execute_address[12 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_23)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_23)begin - dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + always @(*) begin + dataReadCmd_payload = 11'bxxxxxxxxxxx; + if(when_DataCache_l656) begin + dataReadCmd_payload = io_cpu_execute_address[12 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_24)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin - tagsWriteCmd_payload_way = 2'bxx; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_way = 2'b11; + always @(*) begin + tagsWriteCmd_payload_way = 1'bx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 8'bxxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[7:0]; end - if(loader_done)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + if(loader_done) begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[12 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin - tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + always @(*) begin + tagsWriteCmd_payload_data_address = 19'bxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 13]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_24)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin - dataWriteCmd_payload_way = 2'bxx; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin - dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + always @(*) begin + dataWriteCmd_payload_address = 11'bxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[12 : 2]; end - if(_zz_25)begin - dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + if(when_DataCache_l1075) begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[12 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_34[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_25)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_11 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_11 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_11 = 4'b1111; end endcase end - assign stage0_mask = (_zz_11 <<< io_cpu_execute_address[1 : 0]); - assign _zz_12 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_13 = dataWriteCmd_payload_mask[3 : 0]; - always @ (*) begin - stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); - stage0_dataColisions[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_12)) && ((stage0_mask & _zz_13) != 4'b0000)); - end - - assign stage0_wayInvalidate = 2'b00; + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - always @ (*) begin - _zz_14[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - _zz_14[1] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_1_tagsReadRsp_address) && ways_1_tagsReadRsp_valid); - end - - assign stageA_wayHits = _zz_14; - assign _zz_16 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_17 = dataWriteCmd_payload_mask[3 : 0]; - always @ (*) begin - _zz_15[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); - _zz_15[1] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[1]) && (dataWriteCmd_payload_address == _zz_16)) && ((stageA_mask & _zz_17) != 4'b0000)); - end - - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_15); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 13] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); - assign stageB_waysHit = (stageB_waysHits != 2'b00); - assign stageB_dataMux = (stageB_waysHits[0] ? stageB_dataReadRsp_0 : stageB_dataReadRsp_1); - always @ (*) begin + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(! _zz_27) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_26)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_27)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[8]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[8]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -6764,89 +7040,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 2'b00)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_18) != 2'b00) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_26)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_27)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_24)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(_zz_27)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6854,12 +7114,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_26) begin - if(! _zz_27) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6870,24 +7130,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - always @ (*) begin - _zz_18[0] = stageB_tagsReadRsp_0_error; - _zz_18[1] = stageB_tagsReadRsp_1_error; - end - - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_25)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6895,45 +7171,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_36); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6944,105 +7222,89 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin - stageB_tagsReadRsp_1_valid <= ways_1_tagsReadRsp_valid; - stageB_tagsReadRsp_1_error <= ways_1_tagsReadRsp_error; - stageB_tagsReadRsp_1_address <= ways_1_tagsReadRsp_address; - end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin - stageB_dataReadRsp_1 <= ways_1_dataReadRsp; - end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_28)begin - if(_zz_29)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 9'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; - loader_waysAllocator <= 2'b01; + loader_waysAllocator <= 1'b1; loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_28)begin - if(! _zz_29) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 9'h001); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 9'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_25)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_37[1:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -7089,88 +7351,61 @@ module InstructionCache ( input io_mem_rsp_valid, input [31:0] io_mem_rsp_payload_data, input io_mem_rsp_payload_error, - input [2:0] _zz_16, - input [31:0] _zz_17, + input [2:0] _zz_when_Fetcher_l398, + input [31:0] _zz_io_cpu_fetch_data_regNextWhen, input clk, input reset ); - reg [31:0] _zz_18; - reg [31:0] _zz_19; - reg [21:0] _zz_20; - reg [21:0] _zz_21; - reg _zz_22; - reg [31:0] _zz_23; - wire _zz_24; - wire _zz_25; - wire [0:0] _zz_26; - wire [0:0] _zz_27; - wire [0:0] _zz_28; - wire [0:0] _zz_29; - wire [21:0] _zz_30; - wire [21:0] _zz_31; + reg [31:0] _zz_banks_0_port1; + reg [20:0] _zz_ways_0_tags_port1; + wire [20:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; - reg _zz_3; - reg _zz_4; reg lineLoader_fire; reg lineLoader_valid; (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; reg lineLoader_hadError; reg lineLoader_flushPending; - reg [7:0] lineLoader_flushCounter; - reg _zz_5; + reg [8:0] lineLoader_flushCounter; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; - reg [0:0] lineLoader_wayToAllocate_valueNext; - reg [0:0] lineLoader_wayToAllocate_value; wire lineLoader_wayToAllocate_willOverflowIfInc; wire lineLoader_wayToAllocate_willOverflow; (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; wire lineLoader_write_tag_0_valid; - wire [6:0] lineLoader_write_tag_0_payload_address; + wire [7:0] lineLoader_write_tag_0_payload_address; wire lineLoader_write_tag_0_payload_data_valid; wire lineLoader_write_tag_0_payload_data_error; - wire [19:0] lineLoader_write_tag_0_payload_data_address; - wire lineLoader_write_tag_1_valid; - wire [6:0] lineLoader_write_tag_1_payload_address; - wire lineLoader_write_tag_1_payload_data_valid; - wire lineLoader_write_tag_1_payload_data_error; - wire [19:0] lineLoader_write_tag_1_payload_data_address; + wire [18:0] lineLoader_write_tag_0_payload_data_address; wire lineLoader_write_data_0_valid; - wire [9:0] lineLoader_write_data_0_payload_address; + wire [10:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire lineLoader_write_data_1_valid; - wire [9:0] lineLoader_write_data_1_payload_address; - wire [31:0] lineLoader_write_data_1_payload_data; - wire [9:0] _zz_6; - wire _zz_7; + wire when_InstructionCache_l401; + wire [10:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [9:0] _zz_8; - wire _zz_9; - wire [31:0] fetchStage_read_banksValue_1_dataMem; - wire [31:0] fetchStage_read_banksValue_1_data; - wire [6:0] _zz_10; - wire _zz_11; + wire [7:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; - wire [19:0] fetchStage_read_waysValues_0_tag_address; - wire [21:0] _zz_12; - wire [6:0] _zz_13; - wire _zz_14; - wire fetchStage_read_waysValues_1_tag_valid; - wire fetchStage_read_waysValues_1_tag_error; - wire [19:0] fetchStage_read_waysValues_1_tag_address; - wire [21:0] _zz_15; + wire [18:0] fetchStage_read_waysValues_0_tag_address; + wire [20:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; - wire fetchStage_hit_hits_1; wire fetchStage_hit_valid; - wire [0:0] fetchStage_hit_wayId; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -7180,258 +7415,183 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; - (* ram_style = "block" *) reg [31:0] banks_0 [0:1023]; - (* ram_style = "block" *) reg [31:0] banks_1 [0:1023]; - (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; - (* ram_style = "block" *) reg [21:0] ways_1_tags [0:127]; - - assign _zz_24 = (! lineLoader_flushCounter[7]); - assign _zz_25 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_26 = _zz_12[0 : 0]; - assign _zz_27 = _zz_12[1 : 1]; - assign _zz_28 = _zz_15[0 : 0]; - assign _zz_29 = _zz_15[1 : 1]; - assign _zz_30 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - assign _zz_31 = {lineLoader_write_tag_1_payload_data_address,{lineLoader_write_tag_1_payload_data_error,lineLoader_write_tag_1_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_2) begin - banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_7) begin - _zz_18 <= banks_0[_zz_6]; - end - end + wire when_Fetcher_l398; + (* ram_style = "block" *) reg [31:0] banks_0 [0:2047]; + (* ram_style = "block" *) reg [20:0] ways_0_tags [0:255]; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin - banks_1[lineLoader_write_data_1_payload_address] <= lineLoader_write_data_1_payload_data; - end - end - - always @ (posedge clk) begin - if(_zz_9) begin - _zz_19 <= banks_1[_zz_8]; - end - end - - always @ (posedge clk) begin - if(_zz_4) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_30; + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_11) begin - _zz_20 <= ways_0_tags[_zz_10]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin - if(_zz_3) begin - ways_1_tags[lineLoader_write_tag_1_payload_address] <= _zz_31; + always @(posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_14) begin - _zz_21 <= ways_1_tags[_zz_13]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end always @(*) begin - case(fetchStage_hit_wayId) - 1'b0 : begin - _zz_22 = fetchStage_read_waysValues_0_tag_error; - _zz_23 = fetchStage_read_banksValue_0_data; - end - default : begin - _zz_22 = fetchStage_read_waysValues_1_tag_error; - _zz_23 = fetchStage_read_banksValue_1_data; - end - endcase - end - - always @ (*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_1_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin - _zz_3 = 1'b0; - if(lineLoader_write_tag_1_valid)begin - _zz_3 = 1'b1; - end - end - - always @ (*) begin - _zz_4 = 1'b0; - if(lineLoader_write_tag_0_valid)begin - _zz_4 = 1'b1; - end - end - - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_24)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_5))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[8]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end assign lineLoader_wayToAllocate_willClear = 1'b0; - assign lineLoader_wayToAllocate_willOverflowIfInc = (lineLoader_wayToAllocate_value == 1'b1); + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); - always @ (*) begin - lineLoader_wayToAllocate_valueNext = (lineLoader_wayToAllocate_value + lineLoader_wayToAllocate_willIncrement); - if(lineLoader_wayToAllocate_willClear)begin - lineLoader_wayToAllocate_valueNext = 1'b0; - end - end - - assign lineLoader_write_tag_0_valid = (((lineLoader_wayToAllocate_value == 1'b0) && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[8])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[8] ? lineLoader_address[12 : 5] : lineLoader_flushCounter[7 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[8]; assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_tag_1_valid = (((lineLoader_wayToAllocate_value == 1'b1) && lineLoader_fire) || (! lineLoader_flushCounter[7])); - assign lineLoader_write_tag_1_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); - assign lineLoader_write_tag_1_payload_data_valid = lineLoader_flushCounter[7]; - assign lineLoader_write_tag_1_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); - assign lineLoader_write_tag_1_payload_data_address = lineLoader_address[31 : 12]; - assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b0)); - assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 13]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[12 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign lineLoader_write_data_1_valid = (io_mem_rsp_valid && (lineLoader_wayToAllocate_value == 1'b1)); - assign lineLoader_write_data_1_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; - assign lineLoader_write_data_1_payload_data = io_mem_rsp_payload_data; - assign _zz_6 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_18; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[12 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_8 = io_cpu_prefetch_pc[11 : 2]; - assign _zz_9 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_1_dataMem = _zz_19; - assign fetchStage_read_banksValue_1_data = fetchStage_read_banksValue_1_dataMem[31 : 0]; - assign _zz_10 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_11 = (! io_cpu_fetch_isStuck); - assign _zz_12 = _zz_20; - assign fetchStage_read_waysValues_0_tag_valid = _zz_26[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_27[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_12[21 : 2]; - assign _zz_13 = io_cpu_prefetch_pc[11 : 5]; - assign _zz_14 = (! io_cpu_fetch_isStuck); - assign _zz_15 = _zz_21; - assign fetchStage_read_waysValues_1_tag_valid = _zz_28[0]; - assign fetchStage_read_waysValues_1_tag_error = _zz_29[0]; - assign fetchStage_read_waysValues_1_tag_address = _zz_15[21 : 2]; - assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_hits_1 = (fetchStage_read_waysValues_1_tag_valid && (fetchStage_read_waysValues_1_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 12])); - assign fetchStage_hit_valid = ({fetchStage_hit_hits_1,fetchStage_hit_hits_0} != 2'b00); - assign fetchStage_hit_wayId = fetchStage_hit_hits_1; - assign fetchStage_hit_error = _zz_22; - assign fetchStage_hit_data = _zz_23; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[12 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[20 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 13])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000); + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; lineLoader_flushPending <= 1'b1; lineLoader_cmdSent <= 1'b0; - lineLoader_wayToAllocate_value <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_25)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - lineLoader_wayToAllocate_value <= lineLoader_wayToAllocate_valueNext; - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_24)begin - lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + if(when_InstructionCache_l338) begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 9'h001); end - _zz_5 <= lineLoader_flushCounter[7]; - if(_zz_25)begin - lineLoader_flushCounter <= 8'h0; + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[8]; + if(when_InstructionCache_l351) begin + lineLoader_flushCounter <= 9'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -7442,14 +7602,14 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end - if((_zz_16 != 3'b000))begin - io_cpu_fetch_data_regNextWhen <= _zz_17; + if(when_Fetcher_l398) begin + io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v index 5ea51b3..d829aa8 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 6276bf628be9d0a58c0284dca83137b71ef29098 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a `define EnvCtrlEnum_binary_sequential_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v index 8325088..9c1d990 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 6276bf628be9d0a58c0284dca83137b71ef29098 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a `define EnvCtrlEnum_binary_sequential_type [1:0] diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v index b12ad4a..76f3ba0 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfu.v @@ -1,57 +1,58 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 5bb91146a62643cf606443d5366c69720906549c - - -`define Input2Kind_defaultEncoding_type [0:0] -`define Input2Kind_defaultEncoding_RS 1'b0 -`define Input2Kind_defaultEncoding_IMM_I 1'b1 - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define Input2Kind_binary_sequential_type [0:0] +`define Input2Kind_binary_sequential_RS 1'b0 +`define Input2Kind_binary_sequential_IMM_I 1'b1 + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, + input [31:0] externalInterruptArray, output CfuPlugin_bus_cmd_valid, input CfuPlugin_bus_cmd_ready, output [9:0] CfuPlugin_bus_cmd_payload_function_id, @@ -59,9 +60,7 @@ module VexRiscv ( output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, input CfuPlugin_bus_rsp_valid, output CfuPlugin_bus_rsp_ready, - input CfuPlugin_bus_rsp_payload_response_ok, input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, - input [31:0] externalInterruptArray, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, input iBusWishbone_ACK, @@ -87,37 +86,37 @@ module VexRiscv ( input clk, input reset ); - wire _zz_193; - wire _zz_194; - wire _zz_195; - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - reg _zz_201; - wire _zz_202; - wire [31:0] _zz_203; - wire _zz_204; - wire [31:0] _zz_205; - reg _zz_206; - wire _zz_207; - wire _zz_208; - wire [31:0] _zz_209; - wire _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire [3:0] _zz_218; - wire _zz_219; - wire _zz_220; - reg [31:0] _zz_221; - reg [31:0] _zz_222; - reg [31:0] _zz_223; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -140,6 +139,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -148,389 +148,329 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - wire _zz_228; - wire _zz_229; - wire _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire [1:0] _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire _zz_245; - wire _zz_246; - wire _zz_247; - wire _zz_248; - wire _zz_249; - wire [1:0] _zz_250; - wire _zz_251; - wire _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire _zz_256; - wire _zz_257; - wire _zz_258; - wire _zz_259; - wire [1:0] _zz_260; - wire _zz_261; - wire [1:0] _zz_262; - wire [51:0] _zz_263; - wire [51:0] _zz_264; - wire [51:0] _zz_265; - wire [32:0] _zz_266; - wire [51:0] _zz_267; - wire [49:0] _zz_268; - wire [51:0] _zz_269; - wire [49:0] _zz_270; - wire [51:0] _zz_271; - wire [32:0] _zz_272; - wire [31:0] _zz_273; - wire [32:0] _zz_274; - wire [0:0] _zz_275; - wire [0:0] _zz_276; - wire [0:0] _zz_277; - wire [0:0] _zz_278; - wire [0:0] _zz_279; - wire [0:0] _zz_280; - wire [0:0] _zz_281; - wire [0:0] _zz_282; - wire [0:0] _zz_283; - wire [0:0] _zz_284; - wire [0:0] _zz_285; - wire [0:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; - wire [0:0] _zz_289; - wire [0:0] _zz_290; - wire [0:0] _zz_291; - wire [0:0] _zz_292; - wire [3:0] _zz_293; - wire [2:0] _zz_294; - wire [31:0] _zz_295; - wire [11:0] _zz_296; - wire [31:0] _zz_297; - wire [19:0] _zz_298; - wire [11:0] _zz_299; - wire [31:0] _zz_300; - wire [31:0] _zz_301; - wire [19:0] _zz_302; - wire [11:0] _zz_303; - wire [2:0] _zz_304; - wire [2:0] _zz_305; - wire [0:0] _zz_306; - wire [2:0] _zz_307; - wire [4:0] _zz_308; - wire [11:0] _zz_309; - wire [11:0] _zz_310; - wire [31:0] _zz_311; - wire [31:0] _zz_312; - wire [31:0] _zz_313; - wire [31:0] _zz_314; - wire [31:0] _zz_315; - wire [31:0] _zz_316; - wire [31:0] _zz_317; - wire [11:0] _zz_318; - wire [19:0] _zz_319; - wire [11:0] _zz_320; - wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [11:0] _zz_324; - wire [19:0] _zz_325; - wire [11:0] _zz_326; - wire [2:0] _zz_327; - wire [1:0] _zz_328; - wire [1:0] _zz_329; - wire [1:0] _zz_330; - wire [1:0] _zz_331; - wire [9:0] _zz_332; - wire [7:0] _zz_333; - wire [65:0] _zz_334; - wire [65:0] _zz_335; - wire [31:0] _zz_336; - wire [31:0] _zz_337; - wire [0:0] _zz_338; - wire [5:0] _zz_339; - wire [32:0] _zz_340; - wire [31:0] _zz_341; - wire [31:0] _zz_342; - wire [32:0] _zz_343; - wire [32:0] _zz_344; - wire [32:0] _zz_345; - wire [32:0] _zz_346; - wire [0:0] _zz_347; - wire [32:0] _zz_348; - wire [0:0] _zz_349; - wire [32:0] _zz_350; - wire [0:0] _zz_351; - wire [31:0] _zz_352; - wire [0:0] _zz_353; - wire [0:0] _zz_354; - wire [0:0] _zz_355; - wire [0:0] _zz_356; - wire [0:0] _zz_357; - wire [0:0] _zz_358; - wire [0:0] _zz_359; - wire [26:0] _zz_360; - wire _zz_361; - wire _zz_362; - wire [1:0] _zz_363; - wire [31:0] _zz_364; - wire [31:0] _zz_365; - wire [31:0] _zz_366; - wire _zz_367; - wire [0:0] _zz_368; - wire [14:0] _zz_369; - wire [31:0] _zz_370; - wire [31:0] _zz_371; - wire [31:0] _zz_372; - wire _zz_373; - wire [0:0] _zz_374; - wire [8:0] _zz_375; - wire [31:0] _zz_376; - wire [31:0] _zz_377; - wire [31:0] _zz_378; - wire _zz_379; - wire [0:0] _zz_380; - wire [2:0] _zz_381; - wire _zz_382; - wire _zz_383; - wire _zz_384; - wire [31:0] _zz_385; - wire [31:0] _zz_386; - wire _zz_387; - wire _zz_388; - wire [0:0] _zz_389; - wire [26:0] _zz_390; - wire [31:0] _zz_391; - wire [31:0] _zz_392; - wire [31:0] _zz_393; - wire [0:0] _zz_394; - wire [0:0] _zz_395; - wire [1:0] _zz_396; - wire [1:0] _zz_397; - wire _zz_398; - wire [0:0] _zz_399; - wire [21:0] _zz_400; - wire [31:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire [31:0] _zz_405; - wire [31:0] _zz_406; - wire [0:0] _zz_407; - wire [0:0] _zz_408; - wire [2:0] _zz_409; - wire [2:0] _zz_410; - wire _zz_411; - wire [0:0] _zz_412; - wire [18:0] _zz_413; - wire [31:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; - wire _zz_418; - wire _zz_419; - wire [31:0] _zz_420; - wire [31:0] _zz_421; - wire _zz_422; - wire [0:0] _zz_423; - wire [0:0] _zz_424; - wire _zz_425; - wire [0:0] _zz_426; - wire [15:0] _zz_427; - wire [31:0] _zz_428; - wire _zz_429; - wire _zz_430; - wire _zz_431; - wire [2:0] _zz_432; - wire [2:0] _zz_433; - wire _zz_434; - wire [0:0] _zz_435; - wire [12:0] _zz_436; - wire _zz_437; - wire _zz_438; - wire _zz_439; - wire [0:0] _zz_440; - wire [2:0] _zz_441; - wire _zz_442; - wire [5:0] _zz_443; - wire [5:0] _zz_444; - wire _zz_445; - wire [0:0] _zz_446; - wire [9:0] _zz_447; - wire [31:0] _zz_448; - wire [31:0] _zz_449; - wire [31:0] _zz_450; - wire [31:0] _zz_451; - wire [31:0] _zz_452; - wire _zz_453; - wire [0:0] _zz_454; - wire [0:0] _zz_455; - wire [31:0] _zz_456; - wire _zz_457; - wire [0:0] _zz_458; - wire [3:0] _zz_459; - wire [0:0] _zz_460; - wire [3:0] _zz_461; - wire [5:0] _zz_462; - wire [5:0] _zz_463; - wire _zz_464; - wire [0:0] _zz_465; - wire [7:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire [31:0] _zz_471; - wire [31:0] _zz_472; - wire [31:0] _zz_473; - wire [31:0] _zz_474; - wire [0:0] _zz_475; - wire [1:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [1:0] _zz_479; - wire [0:0] _zz_480; - wire [3:0] _zz_481; - wire [0:0] _zz_482; - wire [0:0] _zz_483; - wire [1:0] _zz_484; - wire [1:0] _zz_485; - wire _zz_486; - wire [0:0] _zz_487; - wire [5:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; - wire _zz_491; - wire _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; - wire _zz_496; - wire _zz_497; - wire [31:0] _zz_498; - wire [31:0] _zz_499; - wire _zz_500; - wire [0:0] _zz_501; - wire [1:0] _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire _zz_505; - wire _zz_506; - wire [0:0] _zz_507; - wire [0:0] _zz_508; - wire _zz_509; - wire [0:0] _zz_510; - wire [3:0] _zz_511; - wire [31:0] _zz_512; - wire [31:0] _zz_513; - wire [31:0] _zz_514; - wire [31:0] _zz_515; - wire [31:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire _zz_519; - wire _zz_520; - wire [31:0] _zz_521; - wire [31:0] _zz_522; - wire [31:0] _zz_523; - wire [31:0] _zz_524; - wire [0:0] _zz_525; - wire [2:0] _zz_526; - wire [0:0] _zz_527; - wire [0:0] _zz_528; - wire _zz_529; - wire [0:0] _zz_530; - wire [1:0] _zz_531; - wire [31:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire _zz_535; - wire _zz_536; - wire [31:0] _zz_537; - wire _zz_538; - wire [0:0] _zz_539; - wire [0:0] _zz_540; - wire [0:0] _zz_541; - wire [0:0] _zz_542; - wire [1:0] _zz_543; - wire [1:0] _zz_544; - wire [0:0] _zz_545; - wire [0:0] _zz_546; - wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire [31:0] _zz_549; - wire [31:0] _zz_550; - wire [31:0] _zz_551; - wire [31:0] _zz_552; - wire _zz_553; - wire _zz_554; - wire _zz_555; - wire [31:0] _zz_556; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6; + wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18; + wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33; + wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45; + wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68; + wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100; + wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125; + wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1; + wire _zz_when; + wire _zz_when_1; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; - wire writeBack_CfuPlugin_CFU_IN_FLIGHT; - wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; wire decode_SRC2_FORCE_ZERO; + wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + wire decode_CfuPlugin_CFU_ENABLE; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_DIV; wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_1; - wire `Input2Kind_defaultEncoding_type _zz_2; - wire `Input2Kind_defaultEncoding_type _zz_3; - wire decode_CfuPlugin_CFU_ENABLE; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -538,24 +478,30 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; - wire `AluCtrlEnum_defaultEncoding_type _zz_25; - wire `AluCtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; - wire `Src1CtrlEnum_defaultEncoding_type _zz_28; - wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] memory_PC; + reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire execute_CfuPlugin_CFU_ENABLE; wire execute_IS_RS1_SIGNED; wire execute_IS_DIV; wire execute_IS_RS2_SIGNED; @@ -566,32 +512,26 @@ module VexRiscv ( wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; - reg _zz_30; - reg _zz_31; - wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_32; - wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_37; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -601,46 +541,46 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_38; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_41; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_42; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; - wire [31:0] _zz_46; - wire _zz_47; - reg _zz_48; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_49; - wire `EnvCtrlEnum_defaultEncoding_type _zz_50; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; - wire `Src2CtrlEnum_defaultEncoding_type _zz_54; - wire `AluCtrlEnum_defaultEncoding_type _zz_55; - wire `Src1CtrlEnum_defaultEncoding_type _zz_56; - reg [31:0] _zz_57; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -658,11 +598,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_59; - reg [31:0] _zz_60; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -692,7 +632,7 @@ module VexRiscv ( wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; + wire memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; @@ -749,7 +689,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -783,6 +723,11 @@ module VexRiscv ( reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -800,31 +745,34 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; - reg CfuPlugin_joinException_valid; - wire [3:0] CfuPlugin_joinException_payload_code; - wire [31:0] CfuPlugin_joinException_payload_badAddr; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_61; - wire [3:0] _zz_62; - wire _zz_63; - wire _zz_64; - wire _zz_65; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -847,16 +795,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_66; - wire _zz_67; - wire _zz_68; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_69; - wire _zz_70; - reg _zz_71; - wire _zz_72; - reg _zz_73; - reg [31:0] _zz_74; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -864,22 +814,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_75; - reg [18:0] _zz_76; - wire _zz_77; - reg [10:0] _zz_78; - wire _zz_79; - reg [18:0] _zz_80; - reg _zz_81; - wire _zz_82; - reg [10:0] _zz_83; - wire _zz_84; - reg [18:0] _zz_85; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -887,7 +844,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_86; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -895,23 +852,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -919,40 +881,56 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_87; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_88; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_89; - reg [31:0] _zz_90; - wire _zz_91; - reg [31:0] _zz_92; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [33:0] _zz_93; - wire _zz_94; - wire _zz_95; - wire _zz_96; - wire _zz_97; - wire _zz_98; - wire `Src1CtrlEnum_defaultEncoding_type _zz_99; - wire `AluCtrlEnum_defaultEncoding_type _zz_100; - wire `Src2CtrlEnum_defaultEncoding_type _zz_101; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_102; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_103; - wire `BranchCtrlEnum_defaultEncoding_type _zz_104; - wire `EnvCtrlEnum_defaultEncoding_type _zz_105; - wire `Input2Kind_defaultEncoding_type _zz_106; + wire when_DBusCachedPlugin_l484; + wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -960,53 +938,72 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_107; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_108; - reg [31:0] _zz_109; - wire _zz_110; - reg [19:0] _zz_111; - wire _zz_112; - reg [19:0] _zz_113; - reg [31:0] _zz_114; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_115; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_116; - reg _zz_117; - reg _zz_118; - reg _zz_119; - reg [4:0] _zz_120; - reg [31:0] _zz_121; - wire _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; - wire _zz_126; - wire _zz_127; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_128; - reg _zz_129; - reg _zz_130; - wire _zz_131; - reg [19:0] _zz_132; - wire _zz_133; - reg [10:0] _zz_134; - wire _zz_135; - reg [18:0] _zz_136; - reg _zz_137; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_138; - reg [19:0] _zz_139; - wire _zz_140; - reg [10:0] _zz_141; - wire _zz_142; - reg [18:0] _zz_143; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; + wire when_BranchPlugin_l296; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1027,9 +1024,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_144; - wire _zz_145; - wire _zz_146; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1042,56 +1039,69 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_147; - wire _zz_148; - wire [1:0] _zz_149; - wire _zz_150; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; - wire execute_CfuPlugin_schedule; - reg execute_CfuPlugin_hold; - reg execute_CfuPlugin_fired; - wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_151; - reg [23:0] _zz_152; - reg [31:0] _zz_153; - wire memory_CfuPlugin_rsp_valid; - reg memory_CfuPlugin_rsp_ready; - wire memory_CfuPlugin_rsp_payload_response_ok; - wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_s2mPipe_rValid; - reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1099,6 +1109,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1111,218 +1123,338 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_154; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_155; - wire _zz_156; - wire _zz_157; - reg [32:0] _zz_158; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_159; - wire [31:0] _zz_160; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire CfuPlugin_bus_cmd_fire; + wire when_CfuPlugin_l171; + wire when_CfuPlugin_l175; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_CfuPlugin_bus_cmd_payload_inputs_1; + reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1; + reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + wire CfuPlugin_bus_rsp_rsp_valid; + reg CfuPlugin_bus_rsp_rsp_ready; + wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_rValid; + reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; + wire when_CfuPlugin_l208; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + wire when_Pipeline_l124_44; + reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_45; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_46; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_47; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_48; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_49; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_50; reg decode_to_execute_CSR_READ_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_51; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_52; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_53; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_54; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_55; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_57; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_60; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_61; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_62; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_63; reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [2:0] _zz_184; - reg _zz_185; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_186; - wire _zz_187; - wire _zz_188; - wire _zz_189; - wire _zz_190; - wire _zz_191; - reg _zz_192; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8_string; - reg [39:0] _zz_9_string; - reg [39:0] _zz_10_string; - reg [31:0] _zz_11_string; - reg [31:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_15_string; - reg [71:0] _zz_16_string; - reg [71:0] _zz_17_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_18_string; - reg [39:0] _zz_19_string; - reg [39:0] _zz_20_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_21_string; - reg [23:0] _zz_22_string; - reg [23:0] _zz_23_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_24_string; - reg [63:0] _zz_25_string; - reg [63:0] _zz_26_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_27_string; - reg [95:0] _zz_28_string; - reg [95:0] _zz_29_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_32_string; + reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_36_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_39_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_40_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_42_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_43_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_44_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_45_string; - reg [39:0] _zz_49_string; - reg [39:0] _zz_50_string; - reg [31:0] _zz_51_string; - reg [71:0] _zz_52_string; - reg [39:0] _zz_53_string; - reg [23:0] _zz_54_string; - reg [63:0] _zz_55_string; - reg [95:0] _zz_56_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_58_string; - reg [95:0] _zz_99_string; - reg [63:0] _zz_100_string; - reg [23:0] _zz_101_string; - reg [39:0] _zz_102_string; - reg [71:0] _zz_103_string; - reg [31:0] _zz_104_string; - reg [39:0] _zz_105_string; - reg [39:0] _zz_106_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1338,473 +1470,437 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_224 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_225 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_226 = 1'b1; - assign _zz_227 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_228 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_229 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_230 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_231 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_232 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_233 = ((_zz_198 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_234 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_235 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_236 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_237 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_238 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_239 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_240 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_241 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_242 = (1'b0 || (! 1'b1)); - assign _zz_243 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_244 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_245 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_246 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_247 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_248 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_249 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_250 = execute_INSTRUCTION[13 : 12]; - assign _zz_251 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_252 = (! memory_arbitration_isStuck); - assign _zz_253 = (iBus_cmd_valid || (_zz_184 != 3'b000)); - assign _zz_254 = (_zz_220 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_255 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_256 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_257 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_258 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_259 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_260 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_261 = execute_INSTRUCTION[13]; - assign _zz_262 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_263 = ($signed(_zz_264) + $signed(_zz_269)); - assign _zz_264 = ($signed(_zz_265) + $signed(_zz_267)); - assign _zz_265 = 52'h0; - assign _zz_266 = {1'b0,memory_MUL_LL}; - assign _zz_267 = {{19{_zz_266[32]}}, _zz_266}; - assign _zz_268 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_269 = {{2{_zz_268[49]}}, _zz_268}; - assign _zz_270 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_271 = {{2{_zz_270[49]}}, _zz_270}; - assign _zz_272 = ($signed(_zz_274) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_273 = _zz_272[31 : 0]; - assign _zz_274 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_275 = _zz_93[33 : 33]; - assign _zz_276 = _zz_93[32 : 32]; - assign _zz_277 = _zz_93[31 : 31]; - assign _zz_278 = _zz_93[30 : 30]; - assign _zz_279 = _zz_93[28 : 28]; - assign _zz_280 = _zz_93[25 : 25]; - assign _zz_281 = _zz_93[17 : 17]; - assign _zz_282 = _zz_93[16 : 16]; - assign _zz_283 = _zz_93[13 : 13]; - assign _zz_284 = _zz_93[12 : 12]; - assign _zz_285 = _zz_93[11 : 11]; - assign _zz_286 = _zz_93[15 : 15]; - assign _zz_287 = _zz_93[5 : 5]; - assign _zz_288 = _zz_93[3 : 3]; - assign _zz_289 = _zz_93[20 : 20]; - assign _zz_290 = _zz_93[10 : 10]; - assign _zz_291 = _zz_93[4 : 4]; - assign _zz_292 = _zz_93[0 : 0]; - assign _zz_293 = (_zz_61 - 4'b0001); - assign _zz_294 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_295 = {29'd0, _zz_294}; - assign _zz_296 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_297 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_298 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_299 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_300 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_301 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_302 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_303 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_304 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_305 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_306 = execute_SRC_LESS; - assign _zz_307 = 3'b100; - assign _zz_308 = execute_INSTRUCTION[19 : 15]; - assign _zz_309 = execute_INSTRUCTION[31 : 20]; - assign _zz_310 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_311 = ($signed(_zz_312) + $signed(_zz_315)); - assign _zz_312 = ($signed(_zz_313) + $signed(_zz_314)); - assign _zz_313 = execute_SRC1; - assign _zz_314 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_315 = (execute_SRC_USE_SUB_LESS ? _zz_316 : _zz_317); - assign _zz_316 = 32'h00000001; - assign _zz_317 = 32'h0; - assign _zz_318 = execute_INSTRUCTION[31 : 20]; - assign _zz_319 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_320 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_321 = {_zz_132,execute_INSTRUCTION[31 : 20]}; - assign _zz_322 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_323 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_324 = execute_INSTRUCTION[31 : 20]; - assign _zz_325 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_326 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_327 = 3'b100; - assign _zz_328 = (_zz_147 & (~ _zz_329)); - assign _zz_329 = (_zz_147 - 2'b01); - assign _zz_330 = (_zz_149 & (~ _zz_331)); - assign _zz_331 = (_zz_149 - 2'b01); - assign _zz_332 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_333 = execute_INSTRUCTION[31 : 24]; - assign _zz_334 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_335 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_336 = writeBack_MUL_LOW[31 : 0]; - assign _zz_337 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_338 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_339 = {5'd0, _zz_338}; - assign _zz_340 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_341 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_342 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_343 = {_zz_154,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_344 = _zz_345; - assign _zz_345 = _zz_346; - assign _zz_346 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_155) : _zz_155)} + _zz_348); - assign _zz_347 = memory_DivPlugin_div_needRevert; - assign _zz_348 = {32'd0, _zz_347}; - assign _zz_349 = _zz_157; - assign _zz_350 = {32'd0, _zz_349}; - assign _zz_351 = _zz_156; - assign _zz_352 = {31'd0, _zz_351}; - assign _zz_353 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_354 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_355 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_356 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_357 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_358 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_359 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_360 = (iBus_cmd_payload_address >>> 5); - assign _zz_361 = 1'b1; - assign _zz_362 = 1'b1; - assign _zz_363 = {_zz_65,_zz_64}; - assign _zz_364 = 32'h0000106f; - assign _zz_365 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_366 = 32'h00001073; - assign _zz_367 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_368 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_369 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_370) == 32'h00000003),{(_zz_371 == _zz_372),{_zz_373,{_zz_374,_zz_375}}}}}}; - assign _zz_370 = 32'h0000207f; - assign _zz_371 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_372 = 32'h00000003; - assign _zz_373 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_374 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_375 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_376) == 32'h00005013),{(_zz_377 == _zz_378),{_zz_379,{_zz_380,_zz_381}}}}}}; - assign _zz_376 = 32'hbc00707f; - assign _zz_377 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_378 = 32'h00001013; - assign _zz_379 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_380 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_381 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_382 = decode_INSTRUCTION[31]; - assign _zz_383 = decode_INSTRUCTION[31]; - assign _zz_384 = decode_INSTRUCTION[7]; - assign _zz_385 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_386 = 32'h02004020; - assign _zz_387 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_388 = (_zz_97 != 1'b0); - assign _zz_389 = (((decode_INSTRUCTION & _zz_391) == 32'h00000050) != 1'b0); - assign _zz_390 = {((_zz_392 == _zz_393) != 1'b0),{({_zz_394,_zz_395} != 2'b00),{(_zz_396 != _zz_397),{_zz_398,{_zz_399,_zz_400}}}}}; - assign _zz_391 = 32'h00203050; - assign _zz_392 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_393 = 32'h00000050; - assign _zz_394 = ((decode_INSTRUCTION & _zz_401) == 32'h00001050); - assign _zz_395 = ((decode_INSTRUCTION & _zz_402) == 32'h00002050); - assign _zz_396 = {_zz_96,(_zz_403 == _zz_404)}; - assign _zz_397 = 2'b00; - assign _zz_398 = ((_zz_405 == _zz_406) != 1'b0); - assign _zz_399 = ({_zz_407,_zz_408} != 2'b00); - assign _zz_400 = {(_zz_409 != _zz_410),{_zz_411,{_zz_412,_zz_413}}}; - assign _zz_401 = 32'h00001050; - assign _zz_402 = 32'h00002050; - assign _zz_403 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_404 = 32'h00000004; - assign _zz_405 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_406 = 32'h00000040; - assign _zz_407 = ((decode_INSTRUCTION & _zz_414) == 32'h00005010); - assign _zz_408 = ((decode_INSTRUCTION & _zz_415) == 32'h00005020); - assign _zz_409 = {(_zz_416 == _zz_417),{_zz_418,_zz_419}}; - assign _zz_410 = 3'b000; - assign _zz_411 = ((_zz_420 == _zz_421) != 1'b0); - assign _zz_412 = (_zz_422 != 1'b0); - assign _zz_413 = {(_zz_423 != _zz_424),{_zz_425,{_zz_426,_zz_427}}}; - assign _zz_414 = 32'h00007034; - assign _zz_415 = 32'h02007064; - assign _zz_416 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_417 = 32'h40001010; - assign _zz_418 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_419 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_420 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_421 = 32'h00000024; - assign _zz_422 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_423 = ((decode_INSTRUCTION & _zz_428) == 32'h00002000); - assign _zz_424 = 1'b0; - assign _zz_425 = ({_zz_429,_zz_430} != 2'b00); - assign _zz_426 = (_zz_431 != 1'b0); - assign _zz_427 = {(_zz_432 != _zz_433),{_zz_434,{_zz_435,_zz_436}}}; - assign _zz_428 = 32'h00003000; - assign _zz_429 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_430 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_431 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_432 = {_zz_97,{_zz_437,_zz_438}}; - assign _zz_433 = 3'b000; - assign _zz_434 = ({_zz_439,{_zz_440,_zz_441}} != 5'h0); - assign _zz_435 = (_zz_442 != 1'b0); - assign _zz_436 = {(_zz_443 != _zz_444),{_zz_445,{_zz_446,_zz_447}}}; - assign _zz_437 = ((decode_INSTRUCTION & _zz_448) == 32'h00000020); - assign _zz_438 = ((decode_INSTRUCTION & _zz_449) == 32'h00000020); - assign _zz_439 = ((decode_INSTRUCTION & _zz_450) == 32'h00002040); - assign _zz_440 = (_zz_451 == _zz_452); - assign _zz_441 = {_zz_453,{_zz_454,_zz_455}}; - assign _zz_442 = ((decode_INSTRUCTION & _zz_456) == 32'h00000020); - assign _zz_443 = {_zz_457,{_zz_458,_zz_459}}; - assign _zz_444 = 6'h0; - assign _zz_445 = ({_zz_460,_zz_461} != 5'h0); - assign _zz_446 = (_zz_462 != _zz_463); - assign _zz_447 = {_zz_464,{_zz_465,_zz_466}}; - assign _zz_448 = 32'h00000034; - assign _zz_449 = 32'h00000064; - assign _zz_450 = 32'h00002040; - assign _zz_451 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_452 = 32'h00001040; - assign _zz_453 = ((decode_INSTRUCTION & _zz_467) == 32'h00000040); - assign _zz_454 = (_zz_468 == _zz_469); - assign _zz_455 = (_zz_470 == _zz_471); - assign _zz_456 = 32'h00000020; - assign _zz_457 = ((decode_INSTRUCTION & _zz_472) == 32'h00000008); - assign _zz_458 = (_zz_473 == _zz_474); - assign _zz_459 = {_zz_95,{_zz_475,_zz_476}}; - assign _zz_460 = _zz_95; - assign _zz_461 = {_zz_477,{_zz_478,_zz_479}}; - assign _zz_462 = {_zz_96,{_zz_480,_zz_481}}; - assign _zz_463 = 6'h0; - assign _zz_464 = ({_zz_482,_zz_483} != 2'b00); - assign _zz_465 = (_zz_484 != _zz_485); - assign _zz_466 = {_zz_486,{_zz_487,_zz_488}}; - assign _zz_467 = 32'h00000050; - assign _zz_468 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_469 = 32'h00000040; - assign _zz_470 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_471 = 32'h0; - assign _zz_472 = 32'h00000008; - assign _zz_473 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_474 = 32'h00000040; - assign _zz_475 = (_zz_489 == _zz_490); - assign _zz_476 = {_zz_491,_zz_492}; - assign _zz_477 = ((decode_INSTRUCTION & _zz_493) == 32'h00002010); - assign _zz_478 = (_zz_494 == _zz_495); - assign _zz_479 = {_zz_496,_zz_497}; - assign _zz_480 = (_zz_498 == _zz_499); - assign _zz_481 = {_zz_500,{_zz_501,_zz_502}}; - assign _zz_482 = _zz_95; - assign _zz_483 = (_zz_503 == _zz_504); - assign _zz_484 = {_zz_95,_zz_505}; - assign _zz_485 = 2'b00; - assign _zz_486 = (_zz_506 != 1'b0); - assign _zz_487 = (_zz_507 != _zz_508); - assign _zz_488 = {_zz_509,{_zz_510,_zz_511}}; - assign _zz_489 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_490 = 32'h00004020; - assign _zz_491 = ((decode_INSTRUCTION & _zz_512) == 32'h00000010); - assign _zz_492 = ((decode_INSTRUCTION & _zz_513) == 32'h00000020); - assign _zz_493 = 32'h00002030; - assign _zz_494 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_495 = 32'h00000010; - assign _zz_496 = ((decode_INSTRUCTION & _zz_514) == 32'h00002020); - assign _zz_497 = ((decode_INSTRUCTION & _zz_515) == 32'h00000020); - assign _zz_498 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_499 = 32'h00001010; - assign _zz_500 = ((decode_INSTRUCTION & _zz_516) == 32'h00002010); - assign _zz_501 = (_zz_517 == _zz_518); - assign _zz_502 = {_zz_519,_zz_520}; - assign _zz_503 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_504 = 32'h00000020; - assign _zz_505 = ((decode_INSTRUCTION & _zz_521) == 32'h0); - assign _zz_506 = ((decode_INSTRUCTION & _zz_522) == 32'h00004010); - assign _zz_507 = (_zz_523 == _zz_524); - assign _zz_508 = 1'b0; - assign _zz_509 = ({_zz_525,_zz_526} != 4'b0000); - assign _zz_510 = (_zz_527 != _zz_528); - assign _zz_511 = {_zz_529,{_zz_530,_zz_531}}; - assign _zz_512 = 32'h00000030; - assign _zz_513 = 32'h02000020; - assign _zz_514 = 32'h02002060; - assign _zz_515 = 32'h02003020; - assign _zz_516 = 32'h00002010; - assign _zz_517 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_518 = 32'h00000010; - assign _zz_519 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_520 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_521 = 32'h00000020; - assign _zz_522 = 32'h00004014; - assign _zz_523 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_524 = 32'h00002010; - assign _zz_525 = ((decode_INSTRUCTION & _zz_532) == 32'h0); - assign _zz_526 = {(_zz_533 == _zz_534),{_zz_535,_zz_536}}; - assign _zz_527 = ((decode_INSTRUCTION & _zz_537) == 32'h0); - assign _zz_528 = 1'b0; - assign _zz_529 = ({_zz_538,{_zz_539,_zz_540}} != 3'b000); - assign _zz_530 = ({_zz_541,_zz_542} != 2'b00); - assign _zz_531 = {(_zz_543 != _zz_544),(_zz_545 != _zz_546)}; - assign _zz_532 = 32'h00000044; - assign _zz_533 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_534 = 32'h0; - assign _zz_535 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_536 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_537 = 32'h00000058; - assign _zz_538 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_539 = ((decode_INSTRUCTION & _zz_547) == 32'h00002010); - assign _zz_540 = ((decode_INSTRUCTION & _zz_548) == 32'h40000030); - assign _zz_541 = ((decode_INSTRUCTION & _zz_549) == 32'h00000004); - assign _zz_542 = _zz_94; - assign _zz_543 = {(_zz_550 == _zz_551),_zz_94}; - assign _zz_544 = 2'b00; - assign _zz_545 = ((decode_INSTRUCTION & _zz_552) == 32'h00001004); - assign _zz_546 = 1'b0; - assign _zz_547 = 32'h00002014; - assign _zz_548 = 32'h40000034; - assign _zz_549 = 32'h00000014; - assign _zz_550 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_551 = 32'h00000004; - assign _zz_552 = 32'h00005054; - assign _zz_553 = execute_INSTRUCTION[31]; - assign _zz_554 = execute_INSTRUCTION[31]; - assign _zz_555 = execute_INSTRUCTION[7]; - assign _zz_556 = 32'h0; - always @ (posedge clk) begin - if(_zz_361) begin - _zz_221 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_362) begin - _zz_222 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_48) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h00203050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00002040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79}} != 6'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00002040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h00001040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75) == 32'h00000008); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = 6'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = (decode_INSTRUCTION & 32'h00400040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = 32'h00000008; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = 32'h00004020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85) == 32'h00000010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h00002030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98) == 32'h00002020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129) == 32'h00004010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139} != 4'b0000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = 32'h00000030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h02000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = 32'h02002060; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02003020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = 32'h00004014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = 32'h00000044; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00000058; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h40000030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165) == 32'h00001004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = 32'h00002014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h40000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 32'h00000014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = 32'h00000004; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 32'h00005054; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_193 ), //i - .io_cpu_prefetch_isValid (_zz_194 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_195 ), //i - .io_cpu_fetch_isStuck (_zz_196 ), //i - .io_cpu_fetch_isRemoved (_zz_197 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_198 ), //i - .io_cpu_decode_isStuck (_zz_199 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_200 ), //i - .io_cpu_fill_valid (_zz_201 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_202 ), //i - .io_cpu_execute_address (_zz_203[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_88[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_204 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_205[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_206 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_207 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_208 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_209[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_210 ), //i - .io_cpu_writeBack_fence_SR (_zz_211 ), //i - .io_cpu_writeBack_fence_SO (_zz_212 ), //i - .io_cpu_writeBack_fence_SI (_zz_213 ), //i - .io_cpu_writeBack_fence_PW (_zz_214 ), //i - .io_cpu_writeBack_fence_PR (_zz_215 ), //i - .io_cpu_writeBack_fence_PO (_zz_216 ), //i - .io_cpu_writeBack_fence_PI (_zz_217 ), //i - .io_cpu_writeBack_fence_FM (_zz_218[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_219 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_220 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_363) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) + 2'b00 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) 2'b00 : begin - _zz_223 = DBusCachedPlugin_redoBranch_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; end 2'b01 : begin - _zz_223 = CsrPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; end 2'b10 : begin - _zz_223 = BranchPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; end default : begin - _zz_223 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end @@ -1812,808 +1908,825 @@ module VexRiscv ( `ifndef SYNTHESIS always @(*) begin case(decode_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_1) - `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; - default : _zz_1_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; - default : _zz_2_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; - default : _zz_3_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; - default : _zz_8_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_9) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; - default : _zz_9_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_10) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; - default : _zz_10_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_11) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; - default : _zz_11_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_12) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; - default : _zz_12_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_16) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; - default : _zz_16_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_17) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; - default : _zz_17_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_19) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; - default : _zz_19_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_20) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; - default : _zz_20_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_25) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; - default : _zz_25_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_26) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; - default : _zz_26_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_28) - `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; - default : _zz_28_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_29) - `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; - default : _zz_29_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_32) - `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; - default : _zz_32_string = "?????"; + case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_36) - `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; - default : _zz_36_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_39) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; - default : _zz_39_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_40) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; - default : _zz_40_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_42) - `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; - default : _zz_42_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_43) - `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; - default : _zz_43_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_44) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; - default : _zz_44_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_45) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; - default : _zz_45_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_49) - `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; - default : _zz_49_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_50) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; - default : _zz_50_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_52) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; - default : _zz_52_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_53) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; - default : _zz_53_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_54) - `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; - default : _zz_54_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_55) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; - default : _zz_55_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_56) - `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; - default : _zz_56_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_58) - `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; - default : _zz_58_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_99) - `Src1CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_99_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99_string = "URS1 "; - default : _zz_99_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_100) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_100_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_100_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_100_string = "BITWISE "; - default : _zz_100_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_101) - `Src2CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_101_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_101_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_101_string = "PC "; - default : _zz_101_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_102) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_102_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_102_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_102_string = "AND_1"; - default : _zz_102_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_103) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_103_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_103_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_103_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_103_string = "SRA_1 "; - default : _zz_103_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_104) - `BranchCtrlEnum_defaultEncoding_INC : _zz_104_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_104_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_104_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_104_string = "JALR"; - default : _zz_104_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_105) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_105_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_105_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_105_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_105_string = "ECALL"; - default : _zz_105_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_106) - `Input2Kind_defaultEncoding_RS : _zz_106_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_106_string = "IMM_I"; - default : _zz_106_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_263) + $signed(_zz_271)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_273; - assign execute_REGFILE_WRITE_DATA = _zz_108; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_203[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_275[0]; - assign decode_IS_RS1_SIGNED = _zz_276[0]; - assign decode_IS_DIV = _zz_277[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32]; + assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30]; + assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_278[0]; - assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; - assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_279[0]; - assign _zz_4 = _zz_5; - assign _zz_6 = _zz_7; - assign decode_ENV_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_280[0]; - assign _zz_11 = _zz_12; - assign _zz_13 = _zz_14; - assign decode_SHIFT_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_ALU_BITWISE_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_281[0]; - assign decode_MEMORY_MANAGMENT = _zz_282[0]; + assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_283[0]; + assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_284[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_285[0]; - assign decode_SRC2_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_ALU_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_SRC1_CTRL = _zz_27; - assign _zz_28 = _zz_29; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; + always @(*) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + always @(*) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2624,42 +2737,25 @@ module VexRiscv ( assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; - always @ (*) begin - _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; - if(memory_arbitration_isStuck)begin - _zz_30 = 1'b0; - end - end - - always @ (*) begin - _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; - if(execute_arbitration_isStuck)begin - _zz_31 = 1'b0; - end - end - - assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33; - assign execute_ENV_CTRL = _zz_34; - assign writeBack_ENV_CTRL = _zz_35; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_130; - assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_286[0]; - assign decode_RS1_USE = _zz_287[0]; - always @ (*) begin - _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_224)begin - _zz_37 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15]; + assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2669,142 +2765,142 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_119)begin - if((_zz_120 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_121; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_225)begin - if(_zz_226)begin - if(_zz_123)begin - decode_RS2 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_227)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin - decode_RS2 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_228)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin - decode_RS2 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_119)begin - if((_zz_120 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_121; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_225)begin - if(_zz_226)begin - if(_zz_122)begin - decode_RS1 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_227)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_124)begin - decode_RS1 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_228)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_126)begin - decode_RS1 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_38 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_116; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_38 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end - if(_zz_229)begin - _zz_38 = memory_DivPlugin_div_result; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + _zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0; end end - assign memory_SHIFT_CTRL = _zz_39; - assign execute_SHIFT_CTRL = _zz_40; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_41 = execute_PC; - assign execute_SRC2_CTRL = _zz_42; - assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_288[0]; - assign decode_SRC_ADD_ZERO = _zz_289[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_114; - assign execute_SRC1 = _zz_109; - assign execute_ALU_BITWISE_CTRL = _zz_45; - assign _zz_46 = writeBack_INSTRUCTION; - assign _zz_47 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_48 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_48 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_290[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_364) == 32'h00000003),{(_zz_365 == _zz_366),{_zz_367,{_zz_368,_zz_369}}}}}}} != 22'h0); - always @ (*) begin - _zz_57 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_262) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_57 = _zz_336; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_57 = _zz_337; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2816,214 +2912,205 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_291[0]; - assign decode_FLUSH_ALL = _zz_292[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4]; + assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_230)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_231)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_232)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_233)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_58; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_59 = execute_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_59 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_60 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_117 || _zz_118)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_234)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_234)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_219 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_235)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_224)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end - if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + if(when_CfuPlugin_l175) begin execute_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_236)begin + if(_zz_when_1) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_236)begin + if(_zz_when_1) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if((! memory_CfuPlugin_rsp_valid))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_229)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + if(when_CfuPlugin_l208) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushNext = 1'b0; + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_237)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_238)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3032,51 +3119,53 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_237)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_238)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_235)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_237)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_238)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_237)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_238)begin - case(_zz_239) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3089,59 +3178,65 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_62 = (_zz_61 & (~ _zz_293)); - assign _zz_63 = _zz_62[3]; - assign _zz_64 = (_zz_62[1] || _zz_63); - assign _zz_65 = (_zz_62[2] || _zz_63); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_223; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_295); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3149,265 +3244,286 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_66); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_66); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_67); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_68); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_68); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_69; - assign _zz_69 = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_70 = _zz_71; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_72)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_72 = _zz_73; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_74; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_75 = _zz_296[11]; - always @ (*) begin - _zz_76[18] = _zz_75; - _zz_76[17] = _zz_75; - _zz_76[16] = _zz_75; - _zz_76[15] = _zz_75; - _zz_76[14] = _zz_75; - _zz_76[13] = _zz_75; - _zz_76[12] = _zz_75; - _zz_76[11] = _zz_75; - _zz_76[10] = _zz_75; - _zz_76[9] = _zz_75; - _zz_76[8] = _zz_75; - _zz_76[7] = _zz_75; - _zz_76[6] = _zz_75; - _zz_76[5] = _zz_75; - _zz_76[4] = _zz_75; - _zz_76[3] = _zz_75; - _zz_76[2] = _zz_75; - _zz_76[1] = _zz_75; - _zz_76[0] = _zz_75; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_297[31])); - if(_zz_81)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_77 = _zz_298[19]; - always @ (*) begin - _zz_78[10] = _zz_77; - _zz_78[9] = _zz_77; - _zz_78[8] = _zz_77; - _zz_78[7] = _zz_77; - _zz_78[6] = _zz_77; - _zz_78[5] = _zz_77; - _zz_78[4] = _zz_77; - _zz_78[3] = _zz_77; - _zz_78[2] = _zz_77; - _zz_78[1] = _zz_77; - _zz_78[0] = _zz_77; - end - - assign _zz_79 = _zz_299[11]; - always @ (*) begin - _zz_80[18] = _zz_79; - _zz_80[17] = _zz_79; - _zz_80[16] = _zz_79; - _zz_80[15] = _zz_79; - _zz_80[14] = _zz_79; - _zz_80[13] = _zz_79; - _zz_80[12] = _zz_79; - _zz_80[11] = _zz_79; - _zz_80[10] = _zz_79; - _zz_80[9] = _zz_79; - _zz_80[8] = _zz_79; - _zz_80[7] = _zz_79; - _zz_80[6] = _zz_79; - _zz_80[5] = _zz_79; - _zz_80[4] = _zz_79; - _zz_80[3] = _zz_79; - _zz_80[2] = _zz_79; - _zz_80[1] = _zz_79; - _zz_80[0] = _zz_79; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_81 = _zz_300[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_81 = _zz_301[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_82 = _zz_302[19]; - always @ (*) begin - _zz_83[10] = _zz_82; - _zz_83[9] = _zz_82; - _zz_83[8] = _zz_82; - _zz_83[7] = _zz_82; - _zz_83[6] = _zz_82; - _zz_83[5] = _zz_82; - _zz_83[4] = _zz_82; - _zz_83[3] = _zz_82; - _zz_83[2] = _zz_82; - _zz_83[1] = _zz_82; - _zz_83[0] = _zz_82; - end - - assign _zz_84 = _zz_303[11]; - always @ (*) begin - _zz_85[18] = _zz_84; - _zz_85[17] = _zz_84; - _zz_85[16] = _zz_84; - _zz_85[15] = _zz_84; - _zz_85[14] = _zz_84; - _zz_85[13] = _zz_84; - _zz_85[12] = _zz_84; - _zz_85[11] = _zz_84; - _zz_85[10] = _zz_84; - _zz_85[9] = _zz_84; - _zz_85[8] = _zz_84; - _zz_85[7] = _zz_84; - _zz_85[6] = _zz_84; - _zz_85[5] = _zz_84; - _zz_85[4] = _zz_84; - _zz_85[3] = _zz_84; - _zz_85[2] = _zz_84; - _zz_85[1] = _zz_84; - _zz_85[0] = _zz_84; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_382,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_383,_zz_384},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_194 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_195 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_196 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_195; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_198 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_199 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_200 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_233)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_231)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_201 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_231)begin - _zz_201 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_232)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_230)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_232)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_230)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_193 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_220 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3415,168 +3531,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_202 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_203 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_88 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_88 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_88 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_219 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_204 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_205 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_204; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_205; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_206 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_206 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; end end - assign _zz_207 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_208 = (CsrPlugin_privilege == 2'b00); - assign _zz_209 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_240)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_240)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_240)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_304}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_305}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; end - assign _zz_89 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_90[31] = _zz_89; - _zz_90[30] = _zz_89; - _zz_90[29] = _zz_89; - _zz_90[28] = _zz_89; - _zz_90[27] = _zz_89; - _zz_90[26] = _zz_89; - _zz_90[25] = _zz_89; - _zz_90[24] = _zz_89; - _zz_90[23] = _zz_89; - _zz_90[22] = _zz_89; - _zz_90[21] = _zz_89; - _zz_90[20] = _zz_89; - _zz_90[19] = _zz_89; - _zz_90[18] = _zz_89; - _zz_90[17] = _zz_89; - _zz_90[16] = _zz_89; - _zz_90[15] = _zz_89; - _zz_90[14] = _zz_89; - _zz_90[13] = _zz_89; - _zz_90[12] = _zz_89; - _zz_90[11] = _zz_89; - _zz_90[10] = _zz_89; - _zz_90[9] = _zz_89; - _zz_90[8] = _zz_89; - _zz_90[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_91 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_92[31] = _zz_91; - _zz_92[30] = _zz_91; - _zz_92[29] = _zz_91; - _zz_92[28] = _zz_91; - _zz_92[27] = _zz_91; - _zz_92[26] = _zz_91; - _zz_92[25] = _zz_91; - _zz_92[24] = _zz_91; - _zz_92[23] = _zz_91; - _zz_92[22] = _zz_91; - _zz_92[21] = _zz_91; - _zz_92[20] = _zz_91; - _zz_92[19] = _zz_91; - _zz_92[18] = _zz_91; - _zz_92[17] = _zz_91; - _zz_92[16] = _zz_91; - _zz_92[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_260) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_90; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_92; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3595,62 +3722,63 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_94 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_95 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_385 == _zz_386) != 1'b0),{(_zz_387 != 1'b0),{1'b0,{_zz_388,{_zz_389,_zz_390}}}}}}}; - assign _zz_99 = _zz_93[2 : 1]; - assign _zz_56 = _zz_99; - assign _zz_100 = _zz_93[7 : 6]; - assign _zz_55 = _zz_100; - assign _zz_101 = _zz_93[9 : 8]; - assign _zz_54 = _zz_101; - assign _zz_102 = _zz_93[19 : 18]; - assign _zz_53 = _zz_102; - assign _zz_103 = _zz_93[22 : 21]; - assign _zz_52 = _zz_103; - assign _zz_104 = _zz_93[24 : 23]; - assign _zz_51 = _zz_104; - assign _zz_105 = _zz_93[27 : 26]; - assign _zz_50 = _zz_105; - assign _zz_106 = _zz_93[29 : 29]; - assign _zz_49 = _zz_106; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33]; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_221; - assign decode_RegFilePlugin_rs2Data = _zz_222; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_107)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_107)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_107)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3659,355 +3787,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_108 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_108 = {31'd0, _zz_306}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_108 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_109 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_109 = {29'd0, _zz_307}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_109 = {27'd0, _zz_308}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_110 = _zz_309[11]; - always @ (*) begin - _zz_111[19] = _zz_110; - _zz_111[18] = _zz_110; - _zz_111[17] = _zz_110; - _zz_111[16] = _zz_110; - _zz_111[15] = _zz_110; - _zz_111[14] = _zz_110; - _zz_111[13] = _zz_110; - _zz_111[12] = _zz_110; - _zz_111[11] = _zz_110; - _zz_111[10] = _zz_110; - _zz_111[9] = _zz_110; - _zz_111[8] = _zz_110; - _zz_111[7] = _zz_110; - _zz_111[6] = _zz_110; - _zz_111[5] = _zz_110; - _zz_111[4] = _zz_110; - _zz_111[3] = _zz_110; - _zz_111[2] = _zz_110; - _zz_111[1] = _zz_110; - _zz_111[0] = _zz_110; - end - - assign _zz_112 = _zz_310[11]; - always @ (*) begin - _zz_113[19] = _zz_112; - _zz_113[18] = _zz_112; - _zz_113[17] = _zz_112; - _zz_113[16] = _zz_112; - _zz_113[15] = _zz_112; - _zz_113[14] = _zz_112; - _zz_113[13] = _zz_112; - _zz_113[12] = _zz_112; - _zz_113[11] = _zz_112; - _zz_113[10] = _zz_112; - _zz_113[9] = _zz_112; - _zz_113[8] = _zz_112; - _zz_113[7] = _zz_112; - _zz_113[6] = _zz_112; - _zz_113[5] = _zz_112; - _zz_113[4] = _zz_112; - _zz_113[3] = _zz_112; - _zz_113[2] = _zz_112; - _zz_113[1] = _zz_112; - _zz_113[0] = _zz_112; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_114 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_114 = {_zz_111,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_114 = {_zz_113,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_114 = _zz_41; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_311; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_115[0] = execute_SRC1[31]; - _zz_115[1] = execute_SRC1[30]; - _zz_115[2] = execute_SRC1[29]; - _zz_115[3] = execute_SRC1[28]; - _zz_115[4] = execute_SRC1[27]; - _zz_115[5] = execute_SRC1[26]; - _zz_115[6] = execute_SRC1[25]; - _zz_115[7] = execute_SRC1[24]; - _zz_115[8] = execute_SRC1[23]; - _zz_115[9] = execute_SRC1[22]; - _zz_115[10] = execute_SRC1[21]; - _zz_115[11] = execute_SRC1[20]; - _zz_115[12] = execute_SRC1[19]; - _zz_115[13] = execute_SRC1[18]; - _zz_115[14] = execute_SRC1[17]; - _zz_115[15] = execute_SRC1[16]; - _zz_115[16] = execute_SRC1[15]; - _zz_115[17] = execute_SRC1[14]; - _zz_115[18] = execute_SRC1[13]; - _zz_115[19] = execute_SRC1[12]; - _zz_115[20] = execute_SRC1[11]; - _zz_115[21] = execute_SRC1[10]; - _zz_115[22] = execute_SRC1[9]; - _zz_115[23] = execute_SRC1[8]; - _zz_115[24] = execute_SRC1[7]; - _zz_115[25] = execute_SRC1[6]; - _zz_115[26] = execute_SRC1[5]; - _zz_115[27] = execute_SRC1[4]; - _zz_115[28] = execute_SRC1[3]; - _zz_115[29] = execute_SRC1[2]; - _zz_115[30] = execute_SRC1[1]; - _zz_115[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_115 : execute_SRC1); - always @ (*) begin - _zz_116[0] = memory_SHIFT_RIGHT[31]; - _zz_116[1] = memory_SHIFT_RIGHT[30]; - _zz_116[2] = memory_SHIFT_RIGHT[29]; - _zz_116[3] = memory_SHIFT_RIGHT[28]; - _zz_116[4] = memory_SHIFT_RIGHT[27]; - _zz_116[5] = memory_SHIFT_RIGHT[26]; - _zz_116[6] = memory_SHIFT_RIGHT[25]; - _zz_116[7] = memory_SHIFT_RIGHT[24]; - _zz_116[8] = memory_SHIFT_RIGHT[23]; - _zz_116[9] = memory_SHIFT_RIGHT[22]; - _zz_116[10] = memory_SHIFT_RIGHT[21]; - _zz_116[11] = memory_SHIFT_RIGHT[20]; - _zz_116[12] = memory_SHIFT_RIGHT[19]; - _zz_116[13] = memory_SHIFT_RIGHT[18]; - _zz_116[14] = memory_SHIFT_RIGHT[17]; - _zz_116[15] = memory_SHIFT_RIGHT[16]; - _zz_116[16] = memory_SHIFT_RIGHT[15]; - _zz_116[17] = memory_SHIFT_RIGHT[14]; - _zz_116[18] = memory_SHIFT_RIGHT[13]; - _zz_116[19] = memory_SHIFT_RIGHT[12]; - _zz_116[20] = memory_SHIFT_RIGHT[11]; - _zz_116[21] = memory_SHIFT_RIGHT[10]; - _zz_116[22] = memory_SHIFT_RIGHT[9]; - _zz_116[23] = memory_SHIFT_RIGHT[8]; - _zz_116[24] = memory_SHIFT_RIGHT[7]; - _zz_116[25] = memory_SHIFT_RIGHT[6]; - _zz_116[26] = memory_SHIFT_RIGHT[5]; - _zz_116[27] = memory_SHIFT_RIGHT[4]; - _zz_116[28] = memory_SHIFT_RIGHT[3]; - _zz_116[29] = memory_SHIFT_RIGHT[2]; - _zz_116[30] = memory_SHIFT_RIGHT[1]; - _zz_116[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_117 = 1'b0; - if(_zz_241)begin - if(_zz_242)begin - if(_zz_122)begin - _zz_117 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_243)begin - if(_zz_244)begin - if(_zz_124)begin - _zz_117 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_245)begin - if(_zz_246)begin - if(_zz_126)begin - _zz_117 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_117 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_118 = 1'b0; - if(_zz_241)begin - if(_zz_242)begin - if(_zz_123)begin - _zz_118 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_243)begin - if(_zz_244)begin - if(_zz_125)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_245)begin - if(_zz_246)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_118 = 1'b0; - end - end - - assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_128 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_128 == 3'b000)) begin - _zz_129 = execute_BranchPlugin_eq; - end else if((_zz_128 == 3'b001)) begin - _zz_129 = (! execute_BranchPlugin_eq); - end else if((((_zz_128 & 3'b101) == 3'b101))) begin - _zz_129 = (! execute_SRC_LESS); - end else begin - _zz_129 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_130 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_130 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_130 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_130 = _zz_129; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_131 = _zz_318[11]; - always @ (*) begin - _zz_132[19] = _zz_131; - _zz_132[18] = _zz_131; - _zz_132[17] = _zz_131; - _zz_132[16] = _zz_131; - _zz_132[15] = _zz_131; - _zz_132[14] = _zz_131; - _zz_132[13] = _zz_131; - _zz_132[12] = _zz_131; - _zz_132[11] = _zz_131; - _zz_132[10] = _zz_131; - _zz_132[9] = _zz_131; - _zz_132[8] = _zz_131; - _zz_132[7] = _zz_131; - _zz_132[6] = _zz_131; - _zz_132[5] = _zz_131; - _zz_132[4] = _zz_131; - _zz_132[3] = _zz_131; - _zz_132[2] = _zz_131; - _zz_132[1] = _zz_131; - _zz_132[0] = _zz_131; - end - - assign _zz_133 = _zz_319[19]; - always @ (*) begin - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; - end - - assign _zz_135 = _zz_320[11]; - always @ (*) begin - _zz_136[18] = _zz_135; - _zz_136[17] = _zz_135; - _zz_136[16] = _zz_135; - _zz_136[15] = _zz_135; - _zz_136[14] = _zz_135; - _zz_136[13] = _zz_135; - _zz_136[12] = _zz_135; - _zz_136[11] = _zz_135; - _zz_136[10] = _zz_135; - _zz_136[9] = _zz_135; - _zz_136[8] = _zz_135; - _zz_136[7] = _zz_135; - _zz_136[6] = _zz_135; - _zz_136[5] = _zz_135; - _zz_136[4] = _zz_135; - _zz_136[3] = _zz_135; - _zz_136[2] = _zz_135; - _zz_136[1] = _zz_135; - _zz_136[0] = _zz_135; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_137 = (_zz_321[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_137 = _zz_322[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_137 = _zz_323[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_137); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -4016,183 +4167,195 @@ module VexRiscv ( endcase end - assign _zz_138 = _zz_324[11]; - always @ (*) begin - _zz_139[19] = _zz_138; - _zz_139[18] = _zz_138; - _zz_139[17] = _zz_138; - _zz_139[16] = _zz_138; - _zz_139[15] = _zz_138; - _zz_139[14] = _zz_138; - _zz_139[13] = _zz_138; - _zz_139[12] = _zz_138; - _zz_139[11] = _zz_138; - _zz_139[10] = _zz_138; - _zz_139[9] = _zz_138; - _zz_139[8] = _zz_138; - _zz_139[7] = _zz_138; - _zz_139[6] = _zz_138; - _zz_139[5] = _zz_138; - _zz_139[4] = _zz_138; - _zz_139[3] = _zz_138; - _zz_139[2] = _zz_138; - _zz_139[1] = _zz_138; - _zz_139[0] = _zz_138; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_553,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_554,_zz_555},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_327}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_140 = _zz_325[19]; - always @ (*) begin - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; - end - - assign _zz_142 = _zz_326[11]; - always @ (*) begin - _zz_143[18] = _zz_142; - _zz_143[17] = _zz_142; - _zz_143[16] = _zz_142; - _zz_143[15] = _zz_142; - _zz_143[14] = _zz_142; - _zz_143[13] = _zz_142; - _zz_143[12] = _zz_142; - _zz_143[11] = _zz_142; - _zz_143[10] = _zz_142; - _zz_143[9] = _zz_142; - _zz_143[8] = _zz_142; - _zz_143[7] = _zz_142; - _zz_143[6] = _zz_142; - _zz_143[5] = _zz_142; - _zz_143[4] = _zz_142; - _zz_143[3] = _zz_142; - _zz_143[2] = _zz_142; - _zz_143[1] = _zz_142; - _zz_143[0] = _zz_142; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; - always @ (*) begin + always @(*) begin BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); - if(1'b0)begin + if(when_BranchPlugin_l296) begin BranchPlugin_branchExceptionPort_valid = 1'b0; end end assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign when_BranchPlugin_l296 = 1'b0; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_144 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_145 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_146 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_148 = _zz_328[0]; - assign _zz_149 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_150 = _zz_330[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_234)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_236)begin + if(_zz_when_1) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4203,8 +4366,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4214,135 +4377,144 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_247)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_248)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_249)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_248)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_249)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4355,106 +4527,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_247)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_247)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_261) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); - assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_332; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; - assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_151 = _zz_333[7]; - always @ (*) begin - _zz_152[23] = _zz_151; - _zz_152[22] = _zz_151; - _zz_152[21] = _zz_151; - _zz_152[20] = _zz_151; - _zz_152[19] = _zz_151; - _zz_152[18] = _zz_151; - _zz_152[17] = _zz_151; - _zz_152[16] = _zz_151; - _zz_152[15] = _zz_151; - _zz_152[14] = _zz_151; - _zz_152[13] = _zz_151; - _zz_152[12] = _zz_151; - _zz_152[11] = _zz_151; - _zz_152[10] = _zz_151; - _zz_152[9] = _zz_151; - _zz_152[8] = _zz_151; - _zz_152[7] = _zz_151; - _zz_152[6] = _zz_151; - _zz_152[5] = _zz_151; - _zz_152[4] = _zz_151; - _zz_152[3] = _zz_151; - _zz_152[2] = _zz_151; - _zz_152[1] = _zz_151; - _zz_152[0] = _zz_151; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : begin - _zz_153 = execute_RS2; - end - default : begin - _zz_153 = {_zz_152,execute_INSTRUCTION[31 : 24]}; - end - endcase - end - - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_153; - assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); - assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); - assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); - assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); - always @ (*) begin - CfuPlugin_joinException_valid = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if(memory_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); - end - end - end - - assign CfuPlugin_joinException_payload_code = 4'b1111; - assign CfuPlugin_joinException_payload_badAddr = 32'h0; - always @ (*) begin - memory_CfuPlugin_rsp_ready = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); - end - end - assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_250) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4467,8 +4582,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_250) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4487,82 +4602,214 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_334) + $signed(_zz_335)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_229)begin - if(_zz_251)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_252)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_339); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_154 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_154[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_340); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_341 : _zz_342); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_343[31:0]; - assign _zz_155 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_156 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_157 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_158[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_158[31 : 0] = execute_RS1; - end - - assign _zz_160 = (_zz_159 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_160 != 32'h0); - assign _zz_29 = decode_SRC1_CTRL; - assign _zz_27 = _zz_56; - assign _zz_43 = decode_to_execute_SRC1_CTRL; - assign _zz_26 = decode_ALU_CTRL; - assign _zz_24 = _zz_55; - assign _zz_44 = decode_to_execute_ALU_CTRL; - assign _zz_23 = decode_SRC2_CTRL; - assign _zz_21 = _zz_54; - assign _zz_42 = decode_to_execute_SRC2_CTRL; - assign _zz_20 = decode_ALU_BITWISE_CTRL; - assign _zz_18 = _zz_53; - assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_17 = decode_SHIFT_CTRL; - assign _zz_14 = execute_SHIFT_CTRL; - assign _zz_15 = _zz_52; - assign _zz_40 = decode_to_execute_SHIFT_CTRL; - assign _zz_39 = execute_to_memory_SHIFT_CTRL; - assign _zz_12 = decode_BRANCH_CTRL; - assign _zz_58 = _zz_51; - assign _zz_36 = decode_to_execute_BRANCH_CTRL; - assign _zz_10 = decode_ENV_CTRL; - assign _zz_7 = execute_ENV_CTRL; - assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_50; - assign _zz_34 = decode_to_execute_ENV_CTRL; - assign _zz_33 = execute_to_memory_ENV_CTRL; - assign _zz_35 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_49; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready); + assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)); + assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + end + + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2; + end + default : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @(*) begin + CfuPlugin_bus_rsp_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4583,240 +4830,273 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_161 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_161[12 : 0] = 13'h1000; - _zz_161[25 : 20] = 6'h20; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_162 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_162[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_163 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_163[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_164 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_164[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_165 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_165[31 : 30] = CsrPlugin_misa_base; - _zz_165[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_166 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_166[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_166[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_166[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_167 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_167[11 : 11] = CsrPlugin_mip_MEIP; - _zz_167[7 : 7] = CsrPlugin_mip_MTIP; - _zz_167[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_168 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_168[11 : 11] = CsrPlugin_mie_MEIE; - _zz_168[7 : 7] = CsrPlugin_mie_MTIE; - _zz_168[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_169 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_169[31 : 2] = CsrPlugin_mtvec_base; - _zz_169[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_170 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_170[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_171 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_171[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_172 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_172[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_172[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_173 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_173[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_174 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_174[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_175 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_175[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_176 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_176[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_177 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_177[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_178 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_178[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_179 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_179[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_180[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_181[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_182[31 : 0] = _zz_159; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_183[31 : 0] = _zz_160; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = (((((_zz_161 | _zz_162) | (_zz_163 | _zz_164)) | ((_zz_556 | _zz_165) | (_zz_166 | _zz_167))) | (((_zz_168 | _zz_169) | (_zz_170 | _zz_171)) | ((_zz_172 | _zz_173) | (_zz_174 | _zz_175)))) | (((_zz_176 | _zz_177) | (_zz_178 | _zz_179)) | ((_zz_180 | _zz_181) | (_zz_182 | _zz_183)))); - assign iBusWishbone_ADR = {_zz_360,_zz_184}; - assign iBusWishbone_CTI = ((_zz_184 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_253)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_253)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_185; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_191 = (dBus_cmd_payload_length != 3'b000); - assign _zz_187 = dBus_cmd_valid; - assign _zz_189 = dBus_cmd_payload_wr; - assign _zz_190 = (_zz_186 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_188 && (_zz_189 || _zz_190)); - assign dBusWishbone_ADR = ((_zz_191 ? {{dBus_cmd_payload_address[31 : 5],_zz_186},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_191 ? (_zz_190 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_189 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_189; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_188 = (_zz_187 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_187; - assign dBusWishbone_STB = _zz_187; - assign dBus_rsp_valid = _zz_192; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_71 <= 1'b0; - _zz_73 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_86; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_87; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_107 <= 1'b1; - _zz_119 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4836,164 +5116,164 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - memory_DivPlugin_div_counter_value <= 6'h0; - _zz_159 <= 32'h0; + CfuPlugin_bus_rsp_rValid <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_184 <= 3'b000; - _zz_185 <= 1'b0; - _zz_186 <= 3'b000; - _zz_192 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_71 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_69)begin - _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_73 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_73 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_254)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_107 <= 1'b0; - _zz_119 <= (_zz_47 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_255)begin - if(_zz_256)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_257)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_258)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_237)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5004,8 +5284,8 @@ module VexRiscv ( end endcase end - if(_zz_238)begin - case(_zz_239) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5015,162 +5295,158 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_146,{_zz_145,_zz_144}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(execute_CfuPlugin_schedule)begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(execute_CfuPlugin_schedule) begin execute_CfuPlugin_hold <= 1'b1; end - if(CfuPlugin_bus_cmd_ready)begin + if(CfuPlugin_bus_cmd_ready) begin execute_CfuPlugin_hold <= 1'b0; end - if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + if(CfuPlugin_bus_cmd_fire) begin execute_CfuPlugin_fired <= 1'b1; end - if((! execute_arbitration_isStuckByOthers))begin + if(when_CfuPlugin_l171) begin execute_CfuPlugin_fired <= 1'b0; end - if(memory_CfuPlugin_rsp_ready)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + if(CfuPlugin_bus_rsp_valid) begin + CfuPlugin_bus_rsp_rValid <= 1'b1; end - if(_zz_259)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + if(CfuPlugin_bus_rsp_rsp_ready) begin + CfuPlugin_bus_rsp_rValid <= 1'b0; end - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + if(when_Pipeline_l124_61) begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_353[0]; - CsrPlugin_mstatus_MIE <= _zz_354[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_356[0]; - CsrPlugin_mie_MTIE <= _zz_357[0]; - CsrPlugin_mie_MSIE <= _zz_358[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_253)begin - if(iBusWishbone_ACK)begin - _zz_184 <= (_zz_184 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_185 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_187 && _zz_188))begin - _zz_186 <= (_zz_186 + 3'b001); - if(_zz_190)begin - _zz_186 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_192 <= ((_zz_187 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_74 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_254)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_120 <= _zz_46[11 : 7]; - _zz_121 <= _zz_57; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_234)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(_zz_236)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; + if(_zz_when_1) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_255)begin - if(_zz_256)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_257)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_258)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_237)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5178,343 +5454,342 @@ module VexRiscv ( end endcase end - if(_zz_259)begin - CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; - end - if((memory_DivPlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_DivPlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_229)begin - if(_zz_251)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_344[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; end end end - if(_zz_252)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_157 ? (~ _zz_158) : _zz_158) + _zz_350); - memory_DivPlugin_rs2 <= ((_zz_156 ? (~ execute_RS2) : execute_RS2) + _zz_352); - memory_DivPlugin_div_needRevert <= ((_zz_157 ^ (_zz_156 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(CfuPlugin_bus_rsp_ready) begin + CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_41; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_8) begin memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_28; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_25; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_22; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_16; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_11; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + end + if(when_Pipeline_l124_45) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_51) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_52) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + if(when_Pipeline_l124_53) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + if(when_Pipeline_l124_54) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_62) begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + end + if(when_Pipeline_l124_63) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_355[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_359[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -5527,9 +5802,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -5551,6 +5825,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -5566,9 +5841,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -5576,7 +5852,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -5585,24 +5861,15 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -5627,40 +5894,48 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5670,23 +5945,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -5694,10 +5979,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -5709,59 +6002,54 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -5776,274 +6064,293 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -6051,89 +6358,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_16)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6141,12 +6432,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6157,20 +6448,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6178,45 +6489,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6227,46 +6540,37 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; @@ -6274,50 +6578,51 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6367,13 +6672,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [22:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [22:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [22:0] _zz_ways_0_tags_port1; + wire [22:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6382,8 +6683,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [6:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -6397,22 +6703,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [8:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_6; - wire _zz_7; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8; + wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -6422,82 +6731,85 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_11 = (! lineLoader_flushCounter[6]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -6513,30 +6825,35 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -6544,51 +6861,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[6]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 7'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -6599,10 +6916,10 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v index cf5ad7e..bab2f8d 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimCfuDebug.v @@ -1,66 +1,57 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 5bb91146a62643cf606443d5366c69720906549c - - -`define Input2Kind_defaultEncoding_type [0:0] -`define Input2Kind_defaultEncoding_RS 1'b0 -`define Input2Kind_defaultEncoding_IMM_I 1'b1 - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define Input2Kind_binary_sequential_type [0:0] +`define Input2Kind_binary_sequential_RS 1'b0 +`define Input2Kind_binary_sequential_IMM_I 1'b1 + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, - output CfuPlugin_bus_cmd_valid, - input CfuPlugin_bus_cmd_ready, - output [9:0] CfuPlugin_bus_cmd_payload_function_id, - output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, - output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, - input CfuPlugin_bus_rsp_valid, - output CfuPlugin_bus_rsp_ready, - input CfuPlugin_bus_rsp_payload_response_ok, - input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, input [31:0] externalInterruptArray, input debug_bus_cmd_valid, output reg debug_bus_cmd_ready, @@ -69,6 +60,14 @@ module VexRiscv ( input [31:0] debug_bus_cmd_payload_data, output reg [31:0] debug_bus_rsp_data, output debug_resetOut, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, input iBusWishbone_ACK, @@ -95,37 +94,37 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_196; - wire _zz_197; - wire _zz_198; - wire _zz_199; - wire _zz_200; - wire _zz_201; - wire _zz_202; - wire _zz_203; - reg _zz_204; - wire _zz_205; - wire [31:0] _zz_206; - wire _zz_207; - wire [31:0] _zz_208; - reg _zz_209; - wire _zz_210; - wire _zz_211; - wire [31:0] _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - wire _zz_219; - wire _zz_220; - wire [3:0] _zz_221; - wire _zz_222; - wire _zz_223; - reg [31:0] _zz_224; - reg [31:0] _zz_225; - reg [31:0] _zz_226; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -148,6 +147,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -156,404 +156,332 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_227; - wire _zz_228; - wire _zz_229; - wire _zz_230; - wire _zz_231; - wire _zz_232; - wire _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire [1:0] _zz_245; - wire _zz_246; - wire _zz_247; - wire _zz_248; - wire _zz_249; - wire _zz_250; - wire _zz_251; - wire _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire [1:0] _zz_256; - wire _zz_257; - wire _zz_258; - wire [5:0] _zz_259; - wire _zz_260; - wire _zz_261; - wire _zz_262; - wire _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire [1:0] _zz_267; - wire _zz_268; - wire [1:0] _zz_269; - wire [51:0] _zz_270; - wire [51:0] _zz_271; - wire [51:0] _zz_272; - wire [32:0] _zz_273; - wire [51:0] _zz_274; - wire [49:0] _zz_275; - wire [51:0] _zz_276; - wire [49:0] _zz_277; - wire [51:0] _zz_278; - wire [32:0] _zz_279; - wire [31:0] _zz_280; - wire [32:0] _zz_281; - wire [0:0] _zz_282; - wire [0:0] _zz_283; - wire [0:0] _zz_284; - wire [0:0] _zz_285; - wire [0:0] _zz_286; - wire [0:0] _zz_287; - wire [0:0] _zz_288; - wire [0:0] _zz_289; - wire [0:0] _zz_290; - wire [0:0] _zz_291; - wire [0:0] _zz_292; - wire [0:0] _zz_293; - wire [0:0] _zz_294; - wire [0:0] _zz_295; - wire [0:0] _zz_296; - wire [0:0] _zz_297; - wire [0:0] _zz_298; - wire [0:0] _zz_299; - wire [0:0] _zz_300; - wire [3:0] _zz_301; - wire [2:0] _zz_302; - wire [31:0] _zz_303; - wire [11:0] _zz_304; - wire [31:0] _zz_305; - wire [19:0] _zz_306; - wire [11:0] _zz_307; - wire [31:0] _zz_308; - wire [31:0] _zz_309; - wire [19:0] _zz_310; - wire [11:0] _zz_311; - wire [2:0] _zz_312; - wire [2:0] _zz_313; - wire [0:0] _zz_314; - wire [2:0] _zz_315; - wire [4:0] _zz_316; - wire [11:0] _zz_317; - wire [11:0] _zz_318; - wire [31:0] _zz_319; - wire [31:0] _zz_320; - wire [31:0] _zz_321; - wire [31:0] _zz_322; - wire [31:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [11:0] _zz_326; - wire [19:0] _zz_327; - wire [11:0] _zz_328; - wire [31:0] _zz_329; - wire [31:0] _zz_330; - wire [31:0] _zz_331; - wire [11:0] _zz_332; - wire [19:0] _zz_333; - wire [11:0] _zz_334; - wire [2:0] _zz_335; - wire [1:0] _zz_336; - wire [1:0] _zz_337; - wire [1:0] _zz_338; - wire [1:0] _zz_339; - wire [9:0] _zz_340; - wire [7:0] _zz_341; - wire [65:0] _zz_342; - wire [65:0] _zz_343; - wire [31:0] _zz_344; - wire [31:0] _zz_345; - wire [0:0] _zz_346; - wire [5:0] _zz_347; - wire [32:0] _zz_348; - wire [31:0] _zz_349; - wire [31:0] _zz_350; - wire [32:0] _zz_351; - wire [32:0] _zz_352; - wire [32:0] _zz_353; - wire [32:0] _zz_354; - wire [0:0] _zz_355; - wire [32:0] _zz_356; - wire [0:0] _zz_357; - wire [32:0] _zz_358; - wire [0:0] _zz_359; - wire [31:0] _zz_360; - wire [0:0] _zz_361; - wire [0:0] _zz_362; - wire [0:0] _zz_363; - wire [0:0] _zz_364; - wire [0:0] _zz_365; - wire [0:0] _zz_366; - wire [0:0] _zz_367; - wire [26:0] _zz_368; - wire _zz_369; - wire _zz_370; - wire [1:0] _zz_371; - wire [31:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire _zz_375; - wire [0:0] _zz_376; - wire [14:0] _zz_377; - wire [31:0] _zz_378; - wire [31:0] _zz_379; - wire [31:0] _zz_380; - wire _zz_381; - wire [0:0] _zz_382; - wire [8:0] _zz_383; - wire [31:0] _zz_384; - wire [31:0] _zz_385; - wire [31:0] _zz_386; - wire _zz_387; - wire [0:0] _zz_388; - wire [2:0] _zz_389; - wire _zz_390; - wire _zz_391; - wire _zz_392; - wire [31:0] _zz_393; - wire [0:0] _zz_394; - wire [0:0] _zz_395; - wire _zz_396; - wire [0:0] _zz_397; - wire [28:0] _zz_398; - wire [0:0] _zz_399; - wire [0:0] _zz_400; - wire [0:0] _zz_401; - wire [0:0] _zz_402; - wire _zz_403; - wire [0:0] _zz_404; - wire [23:0] _zz_405; - wire [31:0] _zz_406; - wire [31:0] _zz_407; - wire [31:0] _zz_408; - wire _zz_409; - wire _zz_410; - wire [0:0] _zz_411; - wire [0:0] _zz_412; - wire [0:0] _zz_413; - wire [0:0] _zz_414; - wire _zz_415; - wire [0:0] _zz_416; - wire [20:0] _zz_417; - wire [31:0] _zz_418; - wire [31:0] _zz_419; - wire _zz_420; - wire _zz_421; - wire [0:0] _zz_422; - wire [1:0] _zz_423; - wire [0:0] _zz_424; - wire [0:0] _zz_425; - wire _zz_426; - wire [0:0] _zz_427; - wire [17:0] _zz_428; - wire [31:0] _zz_429; - wire [31:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire [31:0] _zz_433; - wire [31:0] _zz_434; - wire [31:0] _zz_435; - wire [31:0] _zz_436; - wire _zz_437; - wire [1:0] _zz_438; - wire [1:0] _zz_439; - wire _zz_440; - wire [0:0] _zz_441; - wire [14:0] _zz_442; - wire [31:0] _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire [31:0] _zz_446; - wire [31:0] _zz_447; - wire [31:0] _zz_448; - wire [0:0] _zz_449; - wire [1:0] _zz_450; - wire [4:0] _zz_451; - wire [4:0] _zz_452; - wire _zz_453; - wire [0:0] _zz_454; - wire [11:0] _zz_455; - wire [31:0] _zz_456; - wire [31:0] _zz_457; - wire [31:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire [31:0] _zz_461; - wire _zz_462; - wire [0:0] _zz_463; - wire [1:0] _zz_464; - wire [31:0] _zz_465; - wire [31:0] _zz_466; - wire [0:0] _zz_467; - wire [4:0] _zz_468; - wire [4:0] _zz_469; - wire [4:0] _zz_470; - wire _zz_471; - wire [0:0] _zz_472; - wire [8:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; - wire _zz_477; - wire _zz_478; - wire [31:0] _zz_479; - wire [31:0] _zz_480; - wire _zz_481; - wire [0:0] _zz_482; - wire [2:0] _zz_483; - wire [0:0] _zz_484; - wire [2:0] _zz_485; - wire [0:0] _zz_486; - wire [4:0] _zz_487; - wire [1:0] _zz_488; - wire [1:0] _zz_489; - wire _zz_490; - wire [0:0] _zz_491; - wire [6:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; - wire _zz_496; - wire [0:0] _zz_497; - wire [0:0] _zz_498; - wire [31:0] _zz_499; - wire [31:0] _zz_500; - wire _zz_501; - wire [0:0] _zz_502; - wire [0:0] _zz_503; - wire _zz_504; - wire [0:0] _zz_505; - wire [2:0] _zz_506; - wire _zz_507; - wire [0:0] _zz_508; - wire [0:0] _zz_509; - wire [0:0] _zz_510; - wire [0:0] _zz_511; - wire _zz_512; - wire [0:0] _zz_513; - wire [4:0] _zz_514; - wire [31:0] _zz_515; - wire [31:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire [31:0] _zz_520; - wire [31:0] _zz_521; - wire [31:0] _zz_522; - wire [31:0] _zz_523; - wire [31:0] _zz_524; - wire [31:0] _zz_525; - wire [31:0] _zz_526; - wire [31:0] _zz_527; - wire _zz_528; - wire [0:0] _zz_529; - wire [0:0] _zz_530; - wire [31:0] _zz_531; - wire [31:0] _zz_532; - wire [31:0] _zz_533; - wire [31:0] _zz_534; - wire [31:0] _zz_535; - wire _zz_536; - wire [3:0] _zz_537; - wire [3:0] _zz_538; - wire _zz_539; - wire [0:0] _zz_540; - wire [2:0] _zz_541; - wire [31:0] _zz_542; - wire [31:0] _zz_543; - wire [31:0] _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire _zz_548; - wire [0:0] _zz_549; - wire [1:0] _zz_550; - wire _zz_551; - wire [2:0] _zz_552; - wire [2:0] _zz_553; - wire _zz_554; - wire [0:0] _zz_555; - wire [0:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire [31:0] _zz_559; - wire [31:0] _zz_560; - wire [31:0] _zz_561; - wire [31:0] _zz_562; - wire [31:0] _zz_563; - wire _zz_564; - wire _zz_565; - wire _zz_566; - wire [0:0] _zz_567; - wire [0:0] _zz_568; - wire _zz_569; - wire _zz_570; - wire _zz_571; - wire _zz_572; - wire [31:0] _zz_573; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6; + wire [27:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20; + wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35; + wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47; + wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70; + wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102; + wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127; + wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1; + wire _zz_when; + wire _zz_when_1; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; - wire writeBack_CfuPlugin_CFU_IN_FLIGHT; - wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_DO_EBREAK; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; wire decode_SRC2_FORCE_ZERO; + wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + wire decode_CfuPlugin_CFU_ENABLE; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_DIV; wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_1; - wire `Input2Kind_defaultEncoding_type _zz_2; - wire `Input2Kind_defaultEncoding_type _zz_3; - wire decode_CfuPlugin_CFU_ENABLE; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -561,24 +489,30 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; - wire `AluCtrlEnum_defaultEncoding_type _zz_25; - wire `AluCtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; - wire `Src1CtrlEnum_defaultEncoding_type _zz_28; - wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] memory_PC; + reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire execute_CfuPlugin_CFU_ENABLE; wire execute_DO_EBREAK; wire decode_IS_EBREAK; wire execute_IS_RS1_SIGNED; @@ -591,32 +525,26 @@ module VexRiscv ( wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; - reg _zz_30; - reg _zz_31; - wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_32; - wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_37; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -626,46 +554,46 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_38; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_41; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_42; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; - wire [31:0] _zz_46; - wire _zz_47; - reg _zz_48; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_49; - wire `EnvCtrlEnum_defaultEncoding_type _zz_50; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; - wire `Src2CtrlEnum_defaultEncoding_type _zz_54; - wire `AluCtrlEnum_defaultEncoding_type _zz_55; - wire `Src1CtrlEnum_defaultEncoding_type _zz_56; - reg [31:0] _zz_57; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -683,11 +611,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_59; - reg [31:0] _zz_60; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -717,7 +645,7 @@ module VexRiscv ( wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; + wire memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; @@ -774,7 +702,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -800,7 +728,7 @@ module VexRiscv ( reg DBusCachedPlugin_exceptionBus_valid; reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_61; + reg _zz_when_DBusCachedPlugin_l386; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -809,6 +737,11 @@ module VexRiscv ( reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -826,34 +759,37 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; reg CsrPlugin_allowInterrupts; reg CsrPlugin_allowException; - reg CfuPlugin_joinException_valid; - wire [3:0] CfuPlugin_joinException_payload_code; - wire [31:0] CfuPlugin_joinException_payload_badAddr; + reg CsrPlugin_allowEbreakException; reg IBusCachedPlugin_injectionPort_valid; reg IBusCachedPlugin_injectionPort_ready; wire [31:0] IBusCachedPlugin_injectionPort_payload; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_62; - wire [3:0] _zz_63; - wire _zz_64; - wire _zz_65; - wire _zz_66; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -876,16 +812,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_67; - wire _zz_68; - wire _zz_69; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_70; - wire _zz_71; - reg _zz_72; - wire _zz_73; - reg _zz_74; - reg [31:0] _zz_75; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -893,22 +831,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_76; - reg [18:0] _zz_77; - wire _zz_78; - reg [10:0] _zz_79; - wire _zz_80; - reg [18:0] _zz_81; - reg _zz_82; - wire _zz_83; - reg [10:0] _zz_84; - wire _zz_85; - reg [18:0] _zz_86; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -916,7 +861,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_87; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -924,23 +869,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -948,40 +898,56 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_88; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_89; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_90; - reg [31:0] _zz_91; - wire _zz_92; - reg [31:0] _zz_93; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [34:0] _zz_94; - wire _zz_95; - wire _zz_96; - wire _zz_97; - wire _zz_98; - wire _zz_99; - wire `Src1CtrlEnum_defaultEncoding_type _zz_100; - wire `AluCtrlEnum_defaultEncoding_type _zz_101; - wire `Src2CtrlEnum_defaultEncoding_type _zz_102; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; - wire `BranchCtrlEnum_defaultEncoding_type _zz_105; - wire `EnvCtrlEnum_defaultEncoding_type _zz_106; - wire `Input2Kind_defaultEncoding_type _zz_107; + wire when_DBusCachedPlugin_l484; + wire [34:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -989,53 +955,72 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_108; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_109; - reg [31:0] _zz_110; - wire _zz_111; - reg [19:0] _zz_112; - wire _zz_113; - reg [19:0] _zz_114; - reg [31:0] _zz_115; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_116; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_117; - reg _zz_118; - reg _zz_119; - reg _zz_120; - reg [4:0] _zz_121; - reg [31:0] _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; - wire _zz_126; - wire _zz_127; - wire _zz_128; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_129; - reg _zz_130; - reg _zz_131; - wire _zz_132; - reg [19:0] _zz_133; - wire _zz_134; - reg [10:0] _zz_135; - wire _zz_136; - reg [18:0] _zz_137; - reg _zz_138; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_139; - reg [19:0] _zz_140; - wire _zz_141; - reg [10:0] _zz_142; - wire _zz_143; - reg [18:0] _zz_144; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; + wire when_BranchPlugin_l296; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1056,9 +1041,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_145; - wire _zz_146; - wire _zz_147; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1071,56 +1056,69 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_148; - wire _zz_149; - wire [1:0] _zz_150; - wire _zz_151; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; - wire execute_CfuPlugin_schedule; - reg execute_CfuPlugin_hold; - reg execute_CfuPlugin_fired; - wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_152; - reg [23:0] _zz_153; - reg [31:0] _zz_154; - wire memory_CfuPlugin_rsp_valid; - reg memory_CfuPlugin_rsp_ready; - wire memory_CfuPlugin_rsp_payload_response_ok; - wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_s2mPipe_rValid; - reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1128,6 +1126,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1140,19 +1140,26 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_155; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_156; - wire _zz_157; - wire _zz_158; - reg [32:0] _zz_159; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_160; - wire [31:0] _zz_161; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1160,212 +1167,344 @@ module VexRiscv ( reg DebugPlugin_stepIt; reg DebugPlugin_isPipBusy; reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_162; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire CfuPlugin_bus_cmd_fire; + wire when_CfuPlugin_l171; + wire when_CfuPlugin_l175; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_CfuPlugin_bus_cmd_payload_inputs_1; + reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1; + reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + wire CfuPlugin_bus_rsp_rsp_valid; + reg CfuPlugin_bus_rsp_rsp_ready; + wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_rValid; + reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; + wire when_CfuPlugin_l208; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + wire when_Pipeline_l124_44; + reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_45; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_46; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_47; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_48; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_49; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_50; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_51; reg decode_to_execute_DO_EBREAK; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_52; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_53; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_54; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_55; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_57; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_60; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_61; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_62; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_63; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_64; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_163; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l378; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - reg [31:0] _zz_168; - reg [31:0] _zz_169; - reg [31:0] _zz_170; - reg [31:0] _zz_171; - reg [31:0] _zz_172; - reg [31:0] _zz_173; - reg [31:0] _zz_174; - reg [31:0] _zz_175; - reg [31:0] _zz_176; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [2:0] _zz_187; - reg _zz_188; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_189; - wire _zz_190; - wire _zz_191; - wire _zz_192; - wire _zz_193; - wire _zz_194; - reg _zz_195; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8_string; - reg [39:0] _zz_9_string; - reg [39:0] _zz_10_string; - reg [31:0] _zz_11_string; - reg [31:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_15_string; - reg [71:0] _zz_16_string; - reg [71:0] _zz_17_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_18_string; - reg [39:0] _zz_19_string; - reg [39:0] _zz_20_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_21_string; - reg [23:0] _zz_22_string; - reg [23:0] _zz_23_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_24_string; - reg [63:0] _zz_25_string; - reg [63:0] _zz_26_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_27_string; - reg [95:0] _zz_28_string; - reg [95:0] _zz_29_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_32_string; + reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_36_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_39_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_40_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_42_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_43_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_44_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_45_string; - reg [39:0] _zz_49_string; - reg [39:0] _zz_50_string; - reg [31:0] _zz_51_string; - reg [71:0] _zz_52_string; - reg [39:0] _zz_53_string; - reg [23:0] _zz_54_string; - reg [63:0] _zz_55_string; - reg [95:0] _zz_56_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_58_string; - reg [95:0] _zz_100_string; - reg [63:0] _zz_101_string; - reg [23:0] _zz_102_string; - reg [39:0] _zz_103_string; - reg [71:0] _zz_104_string; - reg [31:0] _zz_105_string; - reg [39:0] _zz_106_string; - reg [39:0] _zz_107_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1381,489 +1520,441 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_227 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_228 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_229 = 1'b1; - assign _zz_230 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_231 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_232 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_233 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_234 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_235 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_236 = ((_zz_201 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_237 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_238 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_239 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_240 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_241 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_242 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_243 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_244 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_245 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_246 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_247 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_248 = (1'b0 || (! 1'b1)); - assign _zz_249 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_250 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_251 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_252 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_253 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_254 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_255 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_256 = execute_INSTRUCTION[13 : 12]; - assign _zz_257 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_258 = (! memory_arbitration_isStuck); - assign _zz_259 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_260 = (iBus_cmd_valid || (_zz_187 != 3'b000)); - assign _zz_261 = (_zz_223 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_262 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_263 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_264 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_265 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_266 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_267 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_268 = execute_INSTRUCTION[13]; - assign _zz_269 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_270 = ($signed(_zz_271) + $signed(_zz_276)); - assign _zz_271 = ($signed(_zz_272) + $signed(_zz_274)); - assign _zz_272 = 52'h0; - assign _zz_273 = {1'b0,memory_MUL_LL}; - assign _zz_274 = {{19{_zz_273[32]}}, _zz_273}; - assign _zz_275 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_276 = {{2{_zz_275[49]}}, _zz_275}; - assign _zz_277 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_278 = {{2{_zz_277[49]}}, _zz_277}; - assign _zz_279 = ($signed(_zz_281) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_280 = _zz_279[31 : 0]; - assign _zz_281 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_282 = _zz_94[33 : 33]; - assign _zz_283 = _zz_94[32 : 32]; - assign _zz_284 = _zz_94[31 : 31]; - assign _zz_285 = _zz_94[30 : 30]; - assign _zz_286 = _zz_94[28 : 28]; - assign _zz_287 = _zz_94[25 : 25]; - assign _zz_288 = _zz_94[17 : 17]; - assign _zz_289 = _zz_94[16 : 16]; - assign _zz_290 = _zz_94[13 : 13]; - assign _zz_291 = _zz_94[12 : 12]; - assign _zz_292 = _zz_94[11 : 11]; - assign _zz_293 = _zz_94[34 : 34]; - assign _zz_294 = _zz_94[15 : 15]; - assign _zz_295 = _zz_94[5 : 5]; - assign _zz_296 = _zz_94[3 : 3]; - assign _zz_297 = _zz_94[20 : 20]; - assign _zz_298 = _zz_94[10 : 10]; - assign _zz_299 = _zz_94[4 : 4]; - assign _zz_300 = _zz_94[0 : 0]; - assign _zz_301 = (_zz_62 - 4'b0001); - assign _zz_302 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_303 = {29'd0, _zz_302}; - assign _zz_304 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_305 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_306 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_307 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_308 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_309 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_310 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_311 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_312 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_313 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_314 = execute_SRC_LESS; - assign _zz_315 = 3'b100; - assign _zz_316 = execute_INSTRUCTION[19 : 15]; - assign _zz_317 = execute_INSTRUCTION[31 : 20]; - assign _zz_318 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_319 = ($signed(_zz_320) + $signed(_zz_323)); - assign _zz_320 = ($signed(_zz_321) + $signed(_zz_322)); - assign _zz_321 = execute_SRC1; - assign _zz_322 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_323 = (execute_SRC_USE_SUB_LESS ? _zz_324 : _zz_325); - assign _zz_324 = 32'h00000001; - assign _zz_325 = 32'h0; - assign _zz_326 = execute_INSTRUCTION[31 : 20]; - assign _zz_327 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_328 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_329 = {_zz_133,execute_INSTRUCTION[31 : 20]}; - assign _zz_330 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_331 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_332 = execute_INSTRUCTION[31 : 20]; - assign _zz_333 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_334 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_335 = 3'b100; - assign _zz_336 = (_zz_148 & (~ _zz_337)); - assign _zz_337 = (_zz_148 - 2'b01); - assign _zz_338 = (_zz_150 & (~ _zz_339)); - assign _zz_339 = (_zz_150 - 2'b01); - assign _zz_340 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_341 = execute_INSTRUCTION[31 : 24]; - assign _zz_342 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_343 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_344 = writeBack_MUL_LOW[31 : 0]; - assign _zz_345 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_346 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_347 = {5'd0, _zz_346}; - assign _zz_348 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_349 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_350 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_351 = {_zz_155,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_352 = _zz_353; - assign _zz_353 = _zz_354; - assign _zz_354 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_156) : _zz_156)} + _zz_356); - assign _zz_355 = memory_DivPlugin_div_needRevert; - assign _zz_356 = {32'd0, _zz_355}; - assign _zz_357 = _zz_158; - assign _zz_358 = {32'd0, _zz_357}; - assign _zz_359 = _zz_157; - assign _zz_360 = {31'd0, _zz_359}; - assign _zz_361 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_362 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_363 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_364 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_365 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_366 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_367 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_368 = (iBus_cmd_payload_address >>> 5); - assign _zz_369 = 1'b1; - assign _zz_370 = 1'b1; - assign _zz_371 = {_zz_66,_zz_65}; - assign _zz_372 = 32'h0000106f; - assign _zz_373 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_374 = 32'h00001073; - assign _zz_375 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_376 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_377 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_378) == 32'h00000003),{(_zz_379 == _zz_380),{_zz_381,{_zz_382,_zz_383}}}}}}; - assign _zz_378 = 32'h0000207f; - assign _zz_379 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_380 = 32'h00000003; - assign _zz_381 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_382 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_383 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_384) == 32'h00005013),{(_zz_385 == _zz_386),{_zz_387,{_zz_388,_zz_389}}}}}}; - assign _zz_384 = 32'hbc00707f; - assign _zz_385 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_386 = 32'h00001013; - assign _zz_387 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_388 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_389 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; - assign _zz_390 = decode_INSTRUCTION[31]; - assign _zz_391 = decode_INSTRUCTION[31]; - assign _zz_392 = decode_INSTRUCTION[7]; - assign _zz_393 = 32'h10103050; - assign _zz_394 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_395 = 1'b0; - assign _zz_396 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_397 = 1'b0; - assign _zz_398 = {(_zz_98 != 1'b0),{({_zz_399,_zz_400} != 2'b00),{(_zz_401 != _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}; - assign _zz_399 = ((decode_INSTRUCTION & _zz_406) == 32'h10000050); - assign _zz_400 = ((decode_INSTRUCTION & _zz_407) == 32'h00000050); - assign _zz_401 = ((decode_INSTRUCTION & _zz_408) == 32'h00000050); - assign _zz_402 = 1'b0; - assign _zz_403 = ({_zz_409,_zz_410} != 2'b00); - assign _zz_404 = ({_zz_411,_zz_412} != 2'b00); - assign _zz_405 = {(_zz_413 != _zz_414),{_zz_415,{_zz_416,_zz_417}}}; - assign _zz_406 = 32'h10203050; - assign _zz_407 = 32'h10103050; - assign _zz_408 = 32'h00103050; - assign _zz_409 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_410 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_411 = _zz_97; - assign _zz_412 = ((decode_INSTRUCTION & _zz_418) == 32'h00000004); - assign _zz_413 = ((decode_INSTRUCTION & _zz_419) == 32'h00000040); - assign _zz_414 = 1'b0; - assign _zz_415 = ({_zz_420,_zz_421} != 2'b00); - assign _zz_416 = ({_zz_422,_zz_423} != 3'b000); - assign _zz_417 = {(_zz_424 != _zz_425),{_zz_426,{_zz_427,_zz_428}}}; - assign _zz_418 = 32'h0000001c; - assign _zz_419 = 32'h00000058; - assign _zz_420 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_421 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_422 = ((decode_INSTRUCTION & _zz_429) == 32'h40001010); - assign _zz_423 = {(_zz_430 == _zz_431),(_zz_432 == _zz_433)}; - assign _zz_424 = ((decode_INSTRUCTION & _zz_434) == 32'h00000024); - assign _zz_425 = 1'b0; - assign _zz_426 = ((_zz_435 == _zz_436) != 1'b0); - assign _zz_427 = (_zz_437 != 1'b0); - assign _zz_428 = {(_zz_438 != _zz_439),{_zz_440,{_zz_441,_zz_442}}}; - assign _zz_429 = 32'h40003054; - assign _zz_430 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_431 = 32'h00001010; - assign _zz_432 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_433 = 32'h00001010; - assign _zz_434 = 32'h00000064; - assign _zz_435 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_436 = 32'h00001000; - assign _zz_437 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_438 = {(_zz_443 == _zz_444),(_zz_445 == _zz_446)}; - assign _zz_439 = 2'b00; - assign _zz_440 = ((_zz_447 == _zz_448) != 1'b0); - assign _zz_441 = ({_zz_449,_zz_450} != 3'b000); - assign _zz_442 = {(_zz_451 != _zz_452),{_zz_453,{_zz_454,_zz_455}}}; - assign _zz_443 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_444 = 32'h00002000; - assign _zz_445 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_446 = 32'h00001000; - assign _zz_447 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_448 = 32'h00004004; - assign _zz_449 = _zz_98; - assign _zz_450 = {(_zz_456 == _zz_457),(_zz_458 == _zz_459)}; - assign _zz_451 = {(_zz_460 == _zz_461),{_zz_462,{_zz_463,_zz_464}}}; - assign _zz_452 = 5'h0; - assign _zz_453 = ((_zz_465 == _zz_466) != 1'b0); - assign _zz_454 = ({_zz_467,_zz_468} != 6'h0); - assign _zz_455 = {(_zz_469 != _zz_470),{_zz_471,{_zz_472,_zz_473}}}; - assign _zz_456 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_457 = 32'h00000020; - assign _zz_458 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_459 = 32'h00000020; - assign _zz_460 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_461 = 32'h00002040; - assign _zz_462 = ((decode_INSTRUCTION & _zz_474) == 32'h00001040); - assign _zz_463 = (_zz_475 == _zz_476); - assign _zz_464 = {_zz_477,_zz_478}; - assign _zz_465 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_466 = 32'h00000020; - assign _zz_467 = (_zz_479 == _zz_480); - assign _zz_468 = {_zz_481,{_zz_482,_zz_483}}; - assign _zz_469 = {_zz_96,{_zz_484,_zz_485}}; - assign _zz_470 = 5'h0; - assign _zz_471 = ({_zz_486,_zz_487} != 6'h0); - assign _zz_472 = (_zz_488 != _zz_489); - assign _zz_473 = {_zz_490,{_zz_491,_zz_492}}; - assign _zz_474 = 32'h00001040; - assign _zz_475 = (decode_INSTRUCTION & 32'h00100040); - assign _zz_476 = 32'h00000040; - assign _zz_477 = ((decode_INSTRUCTION & _zz_493) == 32'h00000040); - assign _zz_478 = ((decode_INSTRUCTION & _zz_494) == 32'h0); - assign _zz_479 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_480 = 32'h00000008; - assign _zz_481 = ((decode_INSTRUCTION & _zz_495) == 32'h00000040); - assign _zz_482 = _zz_96; - assign _zz_483 = {_zz_496,{_zz_497,_zz_498}}; - assign _zz_484 = (_zz_499 == _zz_500); - assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; - assign _zz_486 = _zz_97; - assign _zz_487 = {_zz_504,{_zz_505,_zz_506}}; - assign _zz_488 = {_zz_96,_zz_507}; - assign _zz_489 = 2'b00; - assign _zz_490 = ({_zz_508,_zz_509} != 2'b00); - assign _zz_491 = (_zz_510 != _zz_511); - assign _zz_492 = {_zz_512,{_zz_513,_zz_514}}; - assign _zz_493 = 32'h00000050; - assign _zz_494 = 32'h00000038; - assign _zz_495 = 32'h00000040; - assign _zz_496 = ((decode_INSTRUCTION & _zz_515) == 32'h00004020); - assign _zz_497 = (_zz_516 == _zz_517); - assign _zz_498 = (_zz_518 == _zz_519); - assign _zz_499 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_500 = 32'h00002010; - assign _zz_501 = ((decode_INSTRUCTION & _zz_520) == 32'h00000010); - assign _zz_502 = (_zz_521 == _zz_522); - assign _zz_503 = (_zz_523 == _zz_524); - assign _zz_504 = ((decode_INSTRUCTION & _zz_525) == 32'h00001010); - assign _zz_505 = (_zz_526 == _zz_527); - assign _zz_506 = {_zz_528,{_zz_529,_zz_530}}; - assign _zz_507 = ((decode_INSTRUCTION & _zz_531) == 32'h00000020); - assign _zz_508 = _zz_96; - assign _zz_509 = (_zz_532 == _zz_533); - assign _zz_510 = (_zz_534 == _zz_535); - assign _zz_511 = 1'b0; - assign _zz_512 = (_zz_536 != 1'b0); - assign _zz_513 = (_zz_537 != _zz_538); - assign _zz_514 = {_zz_539,{_zz_540,_zz_541}}; - assign _zz_515 = 32'h00004020; - assign _zz_516 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_517 = 32'h00000010; - assign _zz_518 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_519 = 32'h00000020; - assign _zz_520 = 32'h00001030; - assign _zz_521 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_522 = 32'h00002020; - assign _zz_523 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_524 = 32'h00000020; - assign _zz_525 = 32'h00001010; - assign _zz_526 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_527 = 32'h00002010; - assign _zz_528 = ((decode_INSTRUCTION & _zz_542) == 32'h00000010); - assign _zz_529 = (_zz_543 == _zz_544); - assign _zz_530 = (_zz_545 == _zz_546); - assign _zz_531 = 32'h00000070; - assign _zz_532 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_533 = 32'h0; - assign _zz_534 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_535 = 32'h00004010; - assign _zz_536 = ((decode_INSTRUCTION & _zz_547) == 32'h00002010); - assign _zz_537 = {_zz_548,{_zz_549,_zz_550}}; - assign _zz_538 = 4'b0000; - assign _zz_539 = (_zz_551 != 1'b0); - assign _zz_540 = (_zz_552 != _zz_553); - assign _zz_541 = {_zz_554,{_zz_555,_zz_556}}; - assign _zz_542 = 32'h00000050; - assign _zz_543 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_544 = 32'h00000004; - assign _zz_545 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_546 = 32'h0; - assign _zz_547 = 32'h00006014; - assign _zz_548 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_549 = ((decode_INSTRUCTION & _zz_557) == 32'h0); - assign _zz_550 = {(_zz_558 == _zz_559),(_zz_560 == _zz_561)}; - assign _zz_551 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_552 = {(_zz_562 == _zz_563),{_zz_564,_zz_565}}; - assign _zz_553 = 3'b000; - assign _zz_554 = ({_zz_566,_zz_95} != 2'b00); - assign _zz_555 = ({_zz_567,_zz_568} != 2'b00); - assign _zz_556 = (_zz_569 != 1'b0); - assign _zz_557 = 32'h00000018; - assign _zz_558 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_559 = 32'h00002000; - assign _zz_560 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_561 = 32'h00001000; - assign _zz_562 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_563 = 32'h00000040; - assign _zz_564 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_565 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_566 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_567 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_568 = _zz_95; - assign _zz_569 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); - assign _zz_570 = execute_INSTRUCTION[31]; - assign _zz_571 = execute_INSTRUCTION[31]; - assign _zz_572 = execute_INSTRUCTION[7]; - assign _zz_573 = 32'h0; - always @ (posedge clk) begin - if(_zz_369) begin - _zz_224 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_370) begin - _zz_225 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_48) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = (decode_INSTRUCTION & 32'h10103050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 32'h00100050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = (((decode_INSTRUCTION & 32'h02004064) == 32'h02004020) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9} != 2'b00),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21}}}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h02004074; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00001050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = 32'h00002050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = 32'h00005020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h00007034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = 32'h02007054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = 32'h00002000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50) == 32'h00004004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = 32'h00005000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = 32'h00004054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59) == 32'h00002040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81}} != 6'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = 32'h00000064; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = 32'h00002040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00001040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77) == 32'h00000008); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = 6'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = 32'h00100040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = 32'h00000008; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = 32'h00004020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = 32'h00002030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00002020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131) == 32'h00004010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141} != 4'b0000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h00000030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = 32'h02000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02002060; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = 32'h02003020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = 32'h00004014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = 32'h00000044; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = 32'h00000058; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156) == 32'h40000030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167) == 32'h00001004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h00002014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = 32'h40000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = 32'h00000014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = 32'h00000004; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167 = 32'h00005054; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_196 ), //i - .io_cpu_prefetch_isValid (_zz_197 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_198 ), //i - .io_cpu_fetch_isStuck (_zz_199 ), //i - .io_cpu_fetch_isRemoved (_zz_200 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_201 ), //i - .io_cpu_decode_isStuck (_zz_202 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_203 ), //i - .io_cpu_fill_valid (_zz_204 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_163[2:0] ), //i - ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i + ._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_205 ), //i - .io_cpu_execute_address (_zz_206[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_89[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_207 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_208[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_209 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_210 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_211 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_212[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_213 ), //i - .io_cpu_writeBack_fence_SR (_zz_214 ), //i - .io_cpu_writeBack_fence_SO (_zz_215 ), //i - .io_cpu_writeBack_fence_SI (_zz_216 ), //i - .io_cpu_writeBack_fence_PW (_zz_217 ), //i - .io_cpu_writeBack_fence_PR (_zz_218 ), //i - .io_cpu_writeBack_fence_PO (_zz_219 ), //i - .io_cpu_writeBack_fence_PI (_zz_220 ), //i - .io_cpu_writeBack_fence_FM (_zz_221[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_222 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_223 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_371) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) 2'b00 : begin - _zz_226 = DBusCachedPlugin_redoBranch_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_226 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_226 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_226 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + end + 2'b01 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + end + 2'b10 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end @@ -1871,811 +1962,828 @@ module VexRiscv ( `ifndef SYNTHESIS always @(*) begin case(decode_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_1) - `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; - default : _zz_1_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; - default : _zz_2_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; - default : _zz_3_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; - default : _zz_8_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_9) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; - default : _zz_9_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_10) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; - default : _zz_10_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_11) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; - default : _zz_11_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_12) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; - default : _zz_12_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_16) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; - default : _zz_16_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_17) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; - default : _zz_17_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_19) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; - default : _zz_19_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_20) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; - default : _zz_20_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_25) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; - default : _zz_25_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_26) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; - default : _zz_26_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_28) - `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; - default : _zz_28_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_29) - `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; - default : _zz_29_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_32) - `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; - default : _zz_32_string = "?????"; + case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_36) - `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; - default : _zz_36_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_39) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; - default : _zz_39_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_40) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; - default : _zz_40_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_42) - `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; - default : _zz_42_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_43) - `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; - default : _zz_43_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_44) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; - default : _zz_44_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_45) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; - default : _zz_45_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_49) - `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; - default : _zz_49_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_50) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; - default : _zz_50_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_52) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; - default : _zz_52_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_53) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; - default : _zz_53_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_54) - `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; - default : _zz_54_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_55) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; - default : _zz_55_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_56) - `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; - default : _zz_56_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_58) - `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; - default : _zz_58_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_100) - `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; - default : _zz_100_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_101) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; - default : _zz_101_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_102) - `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; - default : _zz_102_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_103) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; - default : _zz_103_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_104) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; - default : _zz_104_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_105) - `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; - default : _zz_105_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_106) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; - default : _zz_106_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_107) - `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; - default : _zz_107_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_270) + $signed(_zz_278)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_280; - assign execute_REGFILE_WRITE_DATA = _zz_109; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_206[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_282[0]; - assign decode_IS_RS1_SIGNED = _zz_283[0]; - assign decode_IS_DIV = _zz_284[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33]; + assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30]; + assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_285[0]; - assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; - assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_286[0]; - assign _zz_4 = _zz_5; - assign _zz_6 = _zz_7; - assign decode_ENV_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_287[0]; - assign _zz_11 = _zz_12; - assign _zz_13 = _zz_14; - assign decode_SHIFT_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_ALU_BITWISE_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_288[0]; - assign decode_MEMORY_MANAGMENT = _zz_289[0]; + assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_290[0]; + assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_291[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_292[0]; - assign decode_SRC2_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_ALU_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_SRC1_CTRL = _zz_27; - assign _zz_28 = _zz_29; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; + always @(*) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + always @(*) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_293[0]; + assign decode_IS_EBREAK = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2686,42 +2794,25 @@ module VexRiscv ( assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; - always @ (*) begin - _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; - if(memory_arbitration_isStuck)begin - _zz_30 = 1'b0; - end - end - - always @ (*) begin - _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; - if(execute_arbitration_isStuck)begin - _zz_31 = 1'b0; - end - end - - assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33; - assign execute_ENV_CTRL = _zz_34; - assign writeBack_ENV_CTRL = _zz_35; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_131; - assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_294[0]; - assign decode_RS1_USE = _zz_295[0]; - always @ (*) begin - _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_227)begin - _zz_37 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15]; + assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2731,142 +2822,142 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_122; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_228)begin - if(_zz_229)begin - if(_zz_124)begin - decode_RS2 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_230)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_126)begin - decode_RS2 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_231)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_128)begin - decode_RS2 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_122; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_228)begin - if(_zz_229)begin - if(_zz_123)begin - decode_RS1 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_230)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin - decode_RS1 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_231)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin - decode_RS1 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_38 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_117; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_38 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end - if(_zz_232)begin - _zz_38 = memory_DivPlugin_div_result; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + _zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0; end end - assign memory_SHIFT_CTRL = _zz_39; - assign execute_SHIFT_CTRL = _zz_40; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_41 = execute_PC; - assign execute_SRC2_CTRL = _zz_42; - assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_296[0]; - assign decode_SRC_ADD_ZERO = _zz_297[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_115; - assign execute_SRC1 = _zz_110; - assign execute_ALU_BITWISE_CTRL = _zz_45; - assign _zz_46 = writeBack_INSTRUCTION; - assign _zz_47 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_48 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_48 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_298[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_372) == 32'h00000003),{(_zz_373 == _zz_374),{_zz_375,{_zz_376,_zz_377}}}}}}} != 22'h0); - always @ (*) begin - _zz_57 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_269) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_57 = _zz_344; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_57 = _zz_345; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2878,61 +2969,61 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_299[0]; - assign decode_FLUSH_ALL = _zz_300[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4]; + assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_233)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_234)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_235)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_236)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_58; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_59 = execute_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_59 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_60 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end - case(_zz_163) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2941,174 +3032,165 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_237)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_237)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_222 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_238)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_227)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end - if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + if(when_CfuPlugin_l175) begin execute_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_239)begin + if(when_DebugPlugin_l284) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_240)begin + if(_zz_when_1) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_239)begin - if(_zz_241)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushIt = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_240)begin + if(_zz_when_1) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_239)begin - if(_zz_241)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushNext = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if((! memory_CfuPlugin_rsp_valid))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_232)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + if(when_CfuPlugin_l208) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushNext = 1'b0; + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_242)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_243)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3117,75 +3199,77 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_242)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_243)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_239)begin - if(_zz_241)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_244)begin + if(when_DebugPlugin_l300) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin - _zz_61 = 1'b0; - if(DebugPlugin_godmode)begin - _zz_61 = 1'b1; + always @(*) begin + _zz_when_DBusCachedPlugin_l386 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l386 = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_238)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin CsrPlugin_thirdPartyWake = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_242)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_243)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_242)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_243)begin - case(_zz_245) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3195,80 +3279,92 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_forceMachineWire = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + if(when_DebugPlugin_l316) begin CsrPlugin_allowInterrupts = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_allowException = 1'b0; end end + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_63 = (_zz_62 & (~ _zz_301)); - assign _zz_64 = _zz_63[3]; - assign _zz_65 = (_zz_63[1] || _zz_64); - assign _zz_66 = (_zz_63[2] || _zz_64); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_226; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_303); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3276,66 +3372,75 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_67); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_68); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_68); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_69 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_69); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_69); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_70; - assign _zz_70 = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_71 = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_73)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_73 = _zz_74; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_73; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_75; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); - always @ (*) begin + always @(*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_163) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3347,207 +3452,219 @@ module VexRiscv ( endcase end - assign _zz_76 = _zz_304[11]; - always @ (*) begin - _zz_77[18] = _zz_76; - _zz_77[17] = _zz_76; - _zz_77[16] = _zz_76; - _zz_77[15] = _zz_76; - _zz_77[14] = _zz_76; - _zz_77[13] = _zz_76; - _zz_77[12] = _zz_76; - _zz_77[11] = _zz_76; - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7] = _zz_76; - _zz_77[6] = _zz_76; - _zz_77[5] = _zz_76; - _zz_77[4] = _zz_76; - _zz_77[3] = _zz_76; - _zz_77[2] = _zz_76; - _zz_77[1] = _zz_76; - _zz_77[0] = _zz_76; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_305[31])); - if(_zz_82)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_78 = _zz_306[19]; - always @ (*) begin - _zz_79[10] = _zz_78; - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7] = _zz_78; - _zz_79[6] = _zz_78; - _zz_79[5] = _zz_78; - _zz_79[4] = _zz_78; - _zz_79[3] = _zz_78; - _zz_79[2] = _zz_78; - _zz_79[1] = _zz_78; - _zz_79[0] = _zz_78; - end - - assign _zz_80 = _zz_307[11]; - always @ (*) begin - _zz_81[18] = _zz_80; - _zz_81[17] = _zz_80; - _zz_81[16] = _zz_80; - _zz_81[15] = _zz_80; - _zz_81[14] = _zz_80; - _zz_81[13] = _zz_80; - _zz_81[12] = _zz_80; - _zz_81[11] = _zz_80; - _zz_81[10] = _zz_80; - _zz_81[9] = _zz_80; - _zz_81[8] = _zz_80; - _zz_81[7] = _zz_80; - _zz_81[6] = _zz_80; - _zz_81[5] = _zz_80; - _zz_81[4] = _zz_80; - _zz_81[3] = _zz_80; - _zz_81[2] = _zz_80; - _zz_81[1] = _zz_80; - _zz_81[0] = _zz_80; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_82 = _zz_308[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_82 = _zz_309[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_83 = _zz_310[19]; - always @ (*) begin - _zz_84[10] = _zz_83; - _zz_84[9] = _zz_83; - _zz_84[8] = _zz_83; - _zz_84[7] = _zz_83; - _zz_84[6] = _zz_83; - _zz_84[5] = _zz_83; - _zz_84[4] = _zz_83; - _zz_84[3] = _zz_83; - _zz_84[2] = _zz_83; - _zz_84[1] = _zz_83; - _zz_84[0] = _zz_83; - end - - assign _zz_85 = _zz_311[11]; - always @ (*) begin - _zz_86[18] = _zz_85; - _zz_86[17] = _zz_85; - _zz_86[16] = _zz_85; - _zz_86[15] = _zz_85; - _zz_86[14] = _zz_85; - _zz_86[13] = _zz_85; - _zz_86[12] = _zz_85; - _zz_86[11] = _zz_85; - _zz_86[10] = _zz_85; - _zz_86[9] = _zz_85; - _zz_86[8] = _zz_85; - _zz_86[7] = _zz_85; - _zz_86[6] = _zz_85; - _zz_86[5] = _zz_85; - _zz_86[4] = _zz_85; - _zz_86[3] = _zz_85; - _zz_86[2] = _zz_85; - _zz_86[1] = _zz_85; - _zz_86[0] = _zz_85; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_390,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_391,_zz_392},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_197 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_198 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_199 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_198; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_201 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_202 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_203 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_236)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_234)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_204 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_234)begin - _zz_204 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_235)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_233)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_235)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_233)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_196 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_223 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3555,168 +3672,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_205 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_206 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_89 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_89 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_222 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_207 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_208 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_207; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_208; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_209 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_209 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; end end - assign _zz_210 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_211 = (CsrPlugin_privilege == 2'b00); - assign _zz_212 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_246)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_246)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_246)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_312}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_313}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; end - assign _zz_90 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_91[31] = _zz_90; - _zz_91[30] = _zz_90; - _zz_91[29] = _zz_90; - _zz_91[28] = _zz_90; - _zz_91[27] = _zz_90; - _zz_91[26] = _zz_90; - _zz_91[25] = _zz_90; - _zz_91[24] = _zz_90; - _zz_91[23] = _zz_90; - _zz_91[22] = _zz_90; - _zz_91[21] = _zz_90; - _zz_91[20] = _zz_90; - _zz_91[19] = _zz_90; - _zz_91[18] = _zz_90; - _zz_91[17] = _zz_90; - _zz_91[16] = _zz_90; - _zz_91[15] = _zz_90; - _zz_91[14] = _zz_90; - _zz_91[13] = _zz_90; - _zz_91[12] = _zz_90; - _zz_91[11] = _zz_90; - _zz_91[10] = _zz_90; - _zz_91[9] = _zz_90; - _zz_91[8] = _zz_90; - _zz_91[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_92 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_93[31] = _zz_92; - _zz_93[30] = _zz_92; - _zz_93[29] = _zz_92; - _zz_93[28] = _zz_92; - _zz_93[27] = _zz_92; - _zz_93[26] = _zz_92; - _zz_93[25] = _zz_92; - _zz_93[24] = _zz_92; - _zz_93[23] = _zz_92; - _zz_93[22] = _zz_92; - _zz_93[21] = _zz_92; - _zz_93[20] = _zz_92; - _zz_93[19] = _zz_92; - _zz_93[18] = _zz_92; - _zz_93[17] = _zz_92; - _zz_93[16] = _zz_92; - _zz_93[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_267) + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_91; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_93; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3735,62 +3863,63 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_94 = {(((decode_INSTRUCTION & _zz_393) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_394 != _zz_395),{_zz_396,{_zz_397,_zz_398}}}}}}; - assign _zz_100 = _zz_94[2 : 1]; - assign _zz_56 = _zz_100; - assign _zz_101 = _zz_94[7 : 6]; - assign _zz_55 = _zz_101; - assign _zz_102 = _zz_94[9 : 8]; - assign _zz_54 = _zz_102; - assign _zz_103 = _zz_94[19 : 18]; - assign _zz_53 = _zz_103; - assign _zz_104 = _zz_94[22 : 21]; - assign _zz_52 = _zz_104; - assign _zz_105 = _zz_94[24 : 23]; - assign _zz_51 = _zz_105; - assign _zz_106 = _zz_94[27 : 26]; - assign _zz_50 = _zz_106; - assign _zz_107 = _zz_94[29 : 29]; - assign _zz_49 = _zz_107; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1) != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[34 : 34]; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_224; - assign decode_RegFilePlugin_rs2Data = _zz_225; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_108)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_108)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_108)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3799,355 +3928,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_109 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_109 = {31'd0, _zz_314}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_109 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_110 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_110 = {29'd0, _zz_315}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_110 = {27'd0, _zz_316}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_111 = _zz_317[11]; - always @ (*) begin - _zz_112[19] = _zz_111; - _zz_112[18] = _zz_111; - _zz_112[17] = _zz_111; - _zz_112[16] = _zz_111; - _zz_112[15] = _zz_111; - _zz_112[14] = _zz_111; - _zz_112[13] = _zz_111; - _zz_112[12] = _zz_111; - _zz_112[11] = _zz_111; - _zz_112[10] = _zz_111; - _zz_112[9] = _zz_111; - _zz_112[8] = _zz_111; - _zz_112[7] = _zz_111; - _zz_112[6] = _zz_111; - _zz_112[5] = _zz_111; - _zz_112[4] = _zz_111; - _zz_112[3] = _zz_111; - _zz_112[2] = _zz_111; - _zz_112[1] = _zz_111; - _zz_112[0] = _zz_111; - end - - assign _zz_113 = _zz_318[11]; - always @ (*) begin - _zz_114[19] = _zz_113; - _zz_114[18] = _zz_113; - _zz_114[17] = _zz_113; - _zz_114[16] = _zz_113; - _zz_114[15] = _zz_113; - _zz_114[14] = _zz_113; - _zz_114[13] = _zz_113; - _zz_114[12] = _zz_113; - _zz_114[11] = _zz_113; - _zz_114[10] = _zz_113; - _zz_114[9] = _zz_113; - _zz_114[8] = _zz_113; - _zz_114[7] = _zz_113; - _zz_114[6] = _zz_113; - _zz_114[5] = _zz_113; - _zz_114[4] = _zz_113; - _zz_114[3] = _zz_113; - _zz_114[2] = _zz_113; - _zz_114[1] = _zz_113; - _zz_114[0] = _zz_113; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_115 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_115 = _zz_41; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_319; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_116[0] = execute_SRC1[31]; - _zz_116[1] = execute_SRC1[30]; - _zz_116[2] = execute_SRC1[29]; - _zz_116[3] = execute_SRC1[28]; - _zz_116[4] = execute_SRC1[27]; - _zz_116[5] = execute_SRC1[26]; - _zz_116[6] = execute_SRC1[25]; - _zz_116[7] = execute_SRC1[24]; - _zz_116[8] = execute_SRC1[23]; - _zz_116[9] = execute_SRC1[22]; - _zz_116[10] = execute_SRC1[21]; - _zz_116[11] = execute_SRC1[20]; - _zz_116[12] = execute_SRC1[19]; - _zz_116[13] = execute_SRC1[18]; - _zz_116[14] = execute_SRC1[17]; - _zz_116[15] = execute_SRC1[16]; - _zz_116[16] = execute_SRC1[15]; - _zz_116[17] = execute_SRC1[14]; - _zz_116[18] = execute_SRC1[13]; - _zz_116[19] = execute_SRC1[12]; - _zz_116[20] = execute_SRC1[11]; - _zz_116[21] = execute_SRC1[10]; - _zz_116[22] = execute_SRC1[9]; - _zz_116[23] = execute_SRC1[8]; - _zz_116[24] = execute_SRC1[7]; - _zz_116[25] = execute_SRC1[6]; - _zz_116[26] = execute_SRC1[5]; - _zz_116[27] = execute_SRC1[4]; - _zz_116[28] = execute_SRC1[3]; - _zz_116[29] = execute_SRC1[2]; - _zz_116[30] = execute_SRC1[1]; - _zz_116[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); - always @ (*) begin - _zz_117[0] = memory_SHIFT_RIGHT[31]; - _zz_117[1] = memory_SHIFT_RIGHT[30]; - _zz_117[2] = memory_SHIFT_RIGHT[29]; - _zz_117[3] = memory_SHIFT_RIGHT[28]; - _zz_117[4] = memory_SHIFT_RIGHT[27]; - _zz_117[5] = memory_SHIFT_RIGHT[26]; - _zz_117[6] = memory_SHIFT_RIGHT[25]; - _zz_117[7] = memory_SHIFT_RIGHT[24]; - _zz_117[8] = memory_SHIFT_RIGHT[23]; - _zz_117[9] = memory_SHIFT_RIGHT[22]; - _zz_117[10] = memory_SHIFT_RIGHT[21]; - _zz_117[11] = memory_SHIFT_RIGHT[20]; - _zz_117[12] = memory_SHIFT_RIGHT[19]; - _zz_117[13] = memory_SHIFT_RIGHT[18]; - _zz_117[14] = memory_SHIFT_RIGHT[17]; - _zz_117[15] = memory_SHIFT_RIGHT[16]; - _zz_117[16] = memory_SHIFT_RIGHT[15]; - _zz_117[17] = memory_SHIFT_RIGHT[14]; - _zz_117[18] = memory_SHIFT_RIGHT[13]; - _zz_117[19] = memory_SHIFT_RIGHT[12]; - _zz_117[20] = memory_SHIFT_RIGHT[11]; - _zz_117[21] = memory_SHIFT_RIGHT[10]; - _zz_117[22] = memory_SHIFT_RIGHT[9]; - _zz_117[23] = memory_SHIFT_RIGHT[8]; - _zz_117[24] = memory_SHIFT_RIGHT[7]; - _zz_117[25] = memory_SHIFT_RIGHT[6]; - _zz_117[26] = memory_SHIFT_RIGHT[5]; - _zz_117[27] = memory_SHIFT_RIGHT[4]; - _zz_117[28] = memory_SHIFT_RIGHT[3]; - _zz_117[29] = memory_SHIFT_RIGHT[2]; - _zz_117[30] = memory_SHIFT_RIGHT[1]; - _zz_117[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_118 = 1'b0; - if(_zz_247)begin - if(_zz_248)begin - if(_zz_123)begin - _zz_118 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_125)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_251)begin - if(_zz_252)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_118 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_119 = 1'b0; - if(_zz_247)begin - if(_zz_248)begin - if(_zz_124)begin - _zz_119 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_126)begin - _zz_119 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_251)begin - if(_zz_252)begin - if(_zz_128)begin - _zz_119 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_119 = 1'b0; - end - end - - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_129 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_129 == 3'b000)) begin - _zz_130 = execute_BranchPlugin_eq; - end else if((_zz_129 == 3'b001)) begin - _zz_130 = (! execute_BranchPlugin_eq); - end else if((((_zz_129 & 3'b101) == 3'b101))) begin - _zz_130 = (! execute_SRC_LESS); - end else begin - _zz_130 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_131 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_131 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_131 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_131 = _zz_130; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_132 = _zz_326[11]; - always @ (*) begin - _zz_133[19] = _zz_132; - _zz_133[18] = _zz_132; - _zz_133[17] = _zz_132; - _zz_133[16] = _zz_132; - _zz_133[15] = _zz_132; - _zz_133[14] = _zz_132; - _zz_133[13] = _zz_132; - _zz_133[12] = _zz_132; - _zz_133[11] = _zz_132; - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; - end - - assign _zz_134 = _zz_327[19]; - always @ (*) begin - _zz_135[10] = _zz_134; - _zz_135[9] = _zz_134; - _zz_135[8] = _zz_134; - _zz_135[7] = _zz_134; - _zz_135[6] = _zz_134; - _zz_135[5] = _zz_134; - _zz_135[4] = _zz_134; - _zz_135[3] = _zz_134; - _zz_135[2] = _zz_134; - _zz_135[1] = _zz_134; - _zz_135[0] = _zz_134; - end - - assign _zz_136 = _zz_328[11]; - always @ (*) begin - _zz_137[18] = _zz_136; - _zz_137[17] = _zz_136; - _zz_137[16] = _zz_136; - _zz_137[15] = _zz_136; - _zz_137[14] = _zz_136; - _zz_137[13] = _zz_136; - _zz_137[12] = _zz_136; - _zz_137[11] = _zz_136; - _zz_137[10] = _zz_136; - _zz_137[9] = _zz_136; - _zz_137[8] = _zz_136; - _zz_137[7] = _zz_136; - _zz_137[6] = _zz_136; - _zz_137[5] = _zz_136; - _zz_137[4] = _zz_136; - _zz_137[3] = _zz_136; - _zz_137[2] = _zz_136; - _zz_137[1] = _zz_136; - _zz_137[0] = _zz_136; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_138 = (_zz_329[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_138 = _zz_330[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_138 = _zz_331[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -4156,183 +4308,195 @@ module VexRiscv ( endcase end - assign _zz_139 = _zz_332[11]; - always @ (*) begin - _zz_140[19] = _zz_139; - _zz_140[18] = _zz_139; - _zz_140[17] = _zz_139; - _zz_140[16] = _zz_139; - _zz_140[15] = _zz_139; - _zz_140[14] = _zz_139; - _zz_140[13] = _zz_139; - _zz_140[12] = _zz_139; - _zz_140[11] = _zz_139; - _zz_140[10] = _zz_139; - _zz_140[9] = _zz_139; - _zz_140[8] = _zz_139; - _zz_140[7] = _zz_139; - _zz_140[6] = _zz_139; - _zz_140[5] = _zz_139; - _zz_140[4] = _zz_139; - _zz_140[3] = _zz_139; - _zz_140[2] = _zz_139; - _zz_140[1] = _zz_139; - _zz_140[0] = _zz_139; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_570,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_571,_zz_572},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_335}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_141 = _zz_333[19]; - always @ (*) begin - _zz_142[10] = _zz_141; - _zz_142[9] = _zz_141; - _zz_142[8] = _zz_141; - _zz_142[7] = _zz_141; - _zz_142[6] = _zz_141; - _zz_142[5] = _zz_141; - _zz_142[4] = _zz_141; - _zz_142[3] = _zz_141; - _zz_142[2] = _zz_141; - _zz_142[1] = _zz_141; - _zz_142[0] = _zz_141; - end - - assign _zz_143 = _zz_334[11]; - always @ (*) begin - _zz_144[18] = _zz_143; - _zz_144[17] = _zz_143; - _zz_144[16] = _zz_143; - _zz_144[15] = _zz_143; - _zz_144[14] = _zz_143; - _zz_144[13] = _zz_143; - _zz_144[12] = _zz_143; - _zz_144[11] = _zz_143; - _zz_144[10] = _zz_143; - _zz_144[9] = _zz_143; - _zz_144[8] = _zz_143; - _zz_144[7] = _zz_143; - _zz_144[6] = _zz_143; - _zz_144[5] = _zz_143; - _zz_144[4] = _zz_143; - _zz_144[3] = _zz_143; - _zz_144[2] = _zz_143; - _zz_144[1] = _zz_143; - _zz_144[0] = _zz_143; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; - always @ (*) begin + always @(*) begin BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); - if(1'b0)begin + if(when_BranchPlugin_l296) begin BranchPlugin_branchExceptionPort_valid = 1'b0; end end assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign when_BranchPlugin_l296 = 1'b0; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_149 = _zz_336[0]; - assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_151 = _zz_338[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_237)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_240)begin + if(_zz_when_1) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4343,8 +4507,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4354,135 +4518,144 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_253)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_254)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_255)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_254)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_255)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4495,106 +4668,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_253)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_253)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_268) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); - assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_340; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; - assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_152 = _zz_341[7]; - always @ (*) begin - _zz_153[23] = _zz_152; - _zz_153[22] = _zz_152; - _zz_153[21] = _zz_152; - _zz_153[20] = _zz_152; - _zz_153[19] = _zz_152; - _zz_153[18] = _zz_152; - _zz_153[17] = _zz_152; - _zz_153[16] = _zz_152; - _zz_153[15] = _zz_152; - _zz_153[14] = _zz_152; - _zz_153[13] = _zz_152; - _zz_153[12] = _zz_152; - _zz_153[11] = _zz_152; - _zz_153[10] = _zz_152; - _zz_153[9] = _zz_152; - _zz_153[8] = _zz_152; - _zz_153[7] = _zz_152; - _zz_153[6] = _zz_152; - _zz_153[5] = _zz_152; - _zz_153[4] = _zz_152; - _zz_153[3] = _zz_152; - _zz_153[2] = _zz_152; - _zz_153[1] = _zz_152; - _zz_153[0] = _zz_152; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : begin - _zz_154 = execute_RS2; - end - default : begin - _zz_154 = {_zz_153,execute_INSTRUCTION[31 : 24]}; - end - endcase - end - - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_154; - assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); - assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); - assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); - assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); - always @ (*) begin - CfuPlugin_joinException_valid = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if(memory_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); - end - end - end - - assign CfuPlugin_joinException_payload_code = 4'b1111; - assign CfuPlugin_joinException_payload_badAddr = 32'h0; - always @ (*) begin - memory_CfuPlugin_rsp_ready = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); - end - end - assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_256) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4607,8 +4723,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_256) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4627,58 +4743,69 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_342) + $signed(_zz_343)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_232)begin - if(_zz_257)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_258)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_347); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_155 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_155[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_348); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_349 : _zz_350); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_351[31:0]; - assign _zz_156 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_157 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_158 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_159[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_159[31 : 0] = execute_RS1; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; end - assign _zz_161 = (_zz_160 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_161 != 32'h0); - always @ (*) begin + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_259) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end end @@ -4688,9 +4815,9 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_162))begin + if(when_DebugPlugin_l244) begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4699,12 +4826,13 @@ module VexRiscv ( end end - always @ (*) begin + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_259) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin IBusCachedPlugin_injectionPort_valid = 1'b1; end end @@ -4715,38 +4843,174 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_29 = decode_SRC1_CTRL; - assign _zz_27 = _zz_56; - assign _zz_43 = decode_to_execute_SRC1_CTRL; - assign _zz_26 = decode_ALU_CTRL; - assign _zz_24 = _zz_55; - assign _zz_44 = decode_to_execute_ALU_CTRL; - assign _zz_23 = decode_SRC2_CTRL; - assign _zz_21 = _zz_54; - assign _zz_42 = decode_to_execute_SRC2_CTRL; - assign _zz_20 = decode_ALU_BITWISE_CTRL; - assign _zz_18 = _zz_53; - assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_17 = decode_SHIFT_CTRL; - assign _zz_14 = execute_SHIFT_CTRL; - assign _zz_15 = _zz_52; - assign _zz_40 = decode_to_execute_SHIFT_CTRL; - assign _zz_39 = execute_to_memory_SHIFT_CTRL; - assign _zz_12 = decode_BRANCH_CTRL; - assign _zz_58 = _zz_51; - assign _zz_36 = decode_to_execute_BRANCH_CTRL; - assign _zz_10 = decode_ENV_CTRL; - assign _zz_7 = execute_ENV_CTRL; - assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_50; - assign _zz_34 = decode_to_execute_ENV_CTRL; - assign _zz_33 = execute_to_memory_ENV_CTRL; - assign _zz_35 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_49; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready); + assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)); + assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + end + + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2; + end + default : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @(*) begin + CfuPlugin_bus_rsp_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_64 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4767,9 +5031,15 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_163) + case(switch_Fetcher_l362) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4778,240 +5048,268 @@ module VexRiscv ( endcase end - always @ (*) begin - _zz_164 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_164[12 : 0] = 13'h1000; - _zz_164[25 : 20] = 6'h20; + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_165 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_165[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_166 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_166[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_167 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_167[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_168 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_168[31 : 30] = CsrPlugin_misa_base; - _zz_168[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_169 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_169[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_169[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_169[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_170 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_170[11 : 11] = CsrPlugin_mip_MEIP; - _zz_170[7 : 7] = CsrPlugin_mip_MTIP; - _zz_170[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_171 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_171[11 : 11] = CsrPlugin_mie_MEIE; - _zz_171[7 : 7] = CsrPlugin_mie_MTIE; - _zz_171[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_172 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_172[31 : 2] = CsrPlugin_mtvec_base; - _zz_172[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_173 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_173[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_174 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_174[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_175 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_175[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_175[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_176 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_176[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_177 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_177[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_178 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_178[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_179 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_179[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_180[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_181[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_182[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_183[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_184[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_185[31 : 0] = _zz_160; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_186 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_186[31 : 0] = _zz_161; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign execute_CsrPlugin_readData = (((((_zz_164 | _zz_165) | (_zz_166 | _zz_167)) | ((_zz_573 | _zz_168) | (_zz_169 | _zz_170))) | (((_zz_171 | _zz_172) | (_zz_173 | _zz_174)) | ((_zz_175 | _zz_176) | (_zz_177 | _zz_178)))) | (((_zz_179 | _zz_180) | (_zz_181 | _zz_182)) | ((_zz_183 | _zz_184) | (_zz_185 | _zz_186)))); - assign iBusWishbone_ADR = {_zz_368,_zz_187}; - assign iBusWishbone_CTI = ((_zz_187 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_260)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_260)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_188; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_194 = (dBus_cmd_payload_length != 3'b000); - assign _zz_190 = dBus_cmd_valid; - assign _zz_192 = dBus_cmd_payload_wr; - assign _zz_193 = (_zz_189 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_191 && (_zz_192 || _zz_193)); - assign dBusWishbone_ADR = ((_zz_194 ? {{dBus_cmd_payload_address[31 : 5],_zz_189},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_194 ? (_zz_193 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_192 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_192; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_191 = (_zz_190 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_190; - assign dBusWishbone_STB = _zz_190; - assign dBus_rsp_valid = _zz_195; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_72 <= 1'b0; - _zz_74 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_87; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_88; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_108 <= 1'b1; - _zz_120 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -5031,165 +5329,165 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - memory_DivPlugin_div_counter_value <= 6'h0; - _zz_160 <= 32'h0; + CfuPlugin_bus_rsp_rValid <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_163 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_187 <= 3'b000; - _zz_188 <= 1'b0; - _zz_189 <= 3'b000; - _zz_195 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_72 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_70)begin - _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_74 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_74 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_261)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_108 <= 1'b0; - _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_262)begin - if(_zz_263)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_264)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_265)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_242)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5200,8 +5498,8 @@ module VexRiscv ( end endcase end - if(_zz_243)begin - case(_zz_245) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5211,185 +5509,181 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(execute_CfuPlugin_schedule)begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(execute_CfuPlugin_schedule) begin execute_CfuPlugin_hold <= 1'b1; end - if(CfuPlugin_bus_cmd_ready)begin + if(CfuPlugin_bus_cmd_ready) begin execute_CfuPlugin_hold <= 1'b0; end - if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + if(CfuPlugin_bus_cmd_fire) begin execute_CfuPlugin_fired <= 1'b1; end - if((! execute_arbitration_isStuckByOthers))begin + if(when_CfuPlugin_l171) begin execute_CfuPlugin_fired <= 1'b0; end - if(memory_CfuPlugin_rsp_ready)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + if(CfuPlugin_bus_rsp_valid) begin + CfuPlugin_bus_rsp_rValid <= 1'b1; end - if(_zz_266)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + if(CfuPlugin_bus_rsp_rsp_ready) begin + CfuPlugin_bus_rsp_rValid <= 1'b0; end - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + if(when_Pipeline_l124_62) begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_163) + case(switch_Fetcher_l362) 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_163 <= 3'b001; + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; end end 3'b001 : begin - _zz_163 <= 3'b010; + switch_Fetcher_l362 <= 3'b010; end 3'b010 : begin - _zz_163 <= 3'b011; + switch_Fetcher_l362 <= 3'b011; end 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_163 <= 3'b100; + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; end end 3'b100 : begin - _zz_163 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; end default : begin end endcase - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_361[0]; - CsrPlugin_mstatus_MIE <= _zz_362[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_364[0]; - CsrPlugin_mie_MTIE <= _zz_365[0]; - CsrPlugin_mie_MSIE <= _zz_366[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_260)begin - if(iBusWishbone_ACK)begin - _zz_187 <= (_zz_187 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_188 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_190 && _zz_191))begin - _zz_189 <= (_zz_189 + 3'b001); - if(_zz_193)begin - _zz_189 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_195 <= ((_zz_190 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_75 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_261)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_121 <= _zz_46[11 : 7]; - _zz_122 <= _zz_57; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_237)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(_zz_240)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; + if(_zz_when_1) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_262)begin - if(_zz_263)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_264)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_265)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_242)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5397,417 +5691,427 @@ module VexRiscv ( end endcase end - if(_zz_266)begin - CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; - end - if((memory_DivPlugin_div_counter_value == 6'h20))begin + if(when_MulDivIterativePlugin_l126) begin memory_DivPlugin_div_done <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_MulDivIterativePlugin_l126_1) begin memory_DivPlugin_div_done <= 1'b0; end - if(_zz_232)begin - if(_zz_257)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_352[31:0]; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; end end end - if(_zz_258)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_158 ? (~ _zz_159) : _zz_159) + _zz_358); - memory_DivPlugin_rs2 <= ((_zz_157 ? (~ execute_RS2) : execute_RS2) + _zz_360); - memory_DivPlugin_div_needRevert <= ((_zz_158 ^ (_zz_157 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(CfuPlugin_bus_rsp_ready) begin + CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + end + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_41; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_8) begin memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_28; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_25; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_22; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_16; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_11; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + end + if(when_Pipeline_l124_45) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_52) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_53) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + if(when_Pipeline_l124_54) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + if(when_Pipeline_l124_55) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_63) begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + end + if(when_Pipeline_l124_64) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_363[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_367[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end - always @ (posedge clk) begin + always @(posedge clk) begin DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin + if(debug_bus_cmd_ready) begin DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_57; + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; end - _zz_162 <= debug_bus_cmd_payload_address[2]; - if(_zz_239)begin + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin + always @(posedge clk) begin if(debugReset) begin DebugPlugin_resetIt <= 1'b0; DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + if(when_DebugPlugin_l225) begin DebugPlugin_godmode <= 1'b1; end - if(debug_bus_cmd_valid)begin - case(_zz_259) + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin + if(when_DebugPlugin_l260) begin DebugPlugin_resetIt <= 1'b1; end - if(debug_bus_cmd_payload_data[24])begin + if(when_DebugPlugin_l260_1) begin DebugPlugin_resetIt <= 1'b0; end - if(debug_bus_cmd_payload_data[17])begin + if(when_DebugPlugin_l261) begin DebugPlugin_haltIt <= 1'b1; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l261_1) begin DebugPlugin_haltIt <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l262) begin DebugPlugin_haltedByBreak <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l263) begin DebugPlugin_godmode <= 1'b0; end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end end end default : begin end endcase end - if(_zz_239)begin - if(_zz_241)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_244)begin - if(decode_arbitration_isValid)begin + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin DebugPlugin_haltIt <= 1'b1; end end @@ -5820,9 +6124,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -5844,6 +6147,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -5859,9 +6163,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -5869,7 +6174,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -5878,24 +6183,15 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -5920,40 +6216,48 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5963,23 +6267,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -5987,10 +6301,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -6002,59 +6324,54 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -6069,274 +6386,293 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -6344,89 +6680,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_16)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6434,12 +6754,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6450,20 +6770,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6471,45 +6811,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6520,46 +6862,37 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; @@ -6567,50 +6900,51 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6657,18 +6991,14 @@ module InstructionCache ( input io_mem_rsp_valid, input [31:0] io_mem_rsp_payload_data, input io_mem_rsp_payload_error, - input [2:0] _zz_9, - input [31:0] _zz_10, + input [2:0] _zz_when_Fetcher_l398, + input [31:0] _zz_io_cpu_fetch_data_regNextWhen, input clk, input reset ); - reg [31:0] _zz_11; - reg [22:0] _zz_12; - wire _zz_13; - wire _zz_14; - wire [0:0] _zz_15; - wire [0:0] _zz_16; - wire [22:0] _zz_17; + reg [31:0] _zz_banks_0_port1; + reg [22:0] _zz_ways_0_tags_port1; + wire [22:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6677,8 +7007,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [6:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -6692,22 +7027,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [8:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_6; - wire _zz_7; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8; + wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -6717,82 +7055,86 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; + wire when_Fetcher_l398; (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_13 = (! lineLoader_flushCounter[6]); - assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_15 = _zz_8[0 : 0]; - assign _zz_16 = _zz_8[1 : 1]; - assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_11 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_12 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_13)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -6808,30 +7150,36 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_12; - assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000); + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -6839,51 +7187,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_14)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_13)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[6]; - if(_zz_14)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 7'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -6894,14 +7242,14 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end - if((_zz_9 != 3'b000))begin - io_cpu_fetch_data_regNextWhen <= _zz_10; + if(when_Fetcher_l398) begin + io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.v index a049b7e..726e688 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfu.v @@ -1,57 +1,58 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : cbb04d34fec970ebb660147932da0bb4bb5adce0 - - -`define Input2Kind_defaultEncoding_type [0:0] -`define Input2Kind_defaultEncoding_RS 1'b0 -`define Input2Kind_defaultEncoding_IMM_I 1'b1 - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define Input2Kind_binary_sequential_type [0:0] +`define Input2Kind_binary_sequential_RS 1'b0 +`define Input2Kind_binary_sequential_IMM_I 1'b1 + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, + input [31:0] externalInterruptArray, output CfuPlugin_bus_cmd_valid, input CfuPlugin_bus_cmd_ready, output [9:0] CfuPlugin_bus_cmd_payload_function_id, @@ -59,9 +60,7 @@ module VexRiscv ( output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, input CfuPlugin_bus_rsp_valid, output CfuPlugin_bus_rsp_ready, - input CfuPlugin_bus_rsp_payload_response_ok, input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, - input [31:0] externalInterruptArray, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, input iBusWishbone_ACK, @@ -87,37 +86,37 @@ module VexRiscv ( input clk, input reset ); - wire _zz_217; - wire _zz_218; - wire _zz_219; - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - reg _zz_225; - wire _zz_226; - wire [31:0] _zz_227; - wire _zz_228; - wire [31:0] _zz_229; - reg _zz_230; - wire _zz_231; - wire _zz_232; - wire [31:0] _zz_233; - wire _zz_234; - wire _zz_235; - wire _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire [3:0] _zz_242; - wire _zz_243; - wire _zz_244; - reg [31:0] _zz_245; - reg [31:0] _zz_246; - reg [31:0] _zz_247; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -140,6 +139,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -148,389 +148,329 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_248; - wire _zz_249; - wire _zz_250; - wire _zz_251; - wire _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire _zz_256; - wire _zz_257; - wire _zz_258; - wire _zz_259; - wire _zz_260; - wire _zz_261; - wire _zz_262; - wire [1:0] _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire _zz_267; - wire _zz_268; - wire _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire [1:0] _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire _zz_279; - wire _zz_280; - wire _zz_281; - wire _zz_282; - wire _zz_283; - wire [1:0] _zz_284; - wire _zz_285; - wire [1:0] _zz_286; - wire [51:0] _zz_287; - wire [51:0] _zz_288; - wire [51:0] _zz_289; - wire [32:0] _zz_290; - wire [51:0] _zz_291; - wire [49:0] _zz_292; - wire [51:0] _zz_293; - wire [49:0] _zz_294; - wire [51:0] _zz_295; - wire [32:0] _zz_296; - wire [31:0] _zz_297; - wire [32:0] _zz_298; - wire [0:0] _zz_299; - wire [0:0] _zz_300; - wire [0:0] _zz_301; - wire [0:0] _zz_302; - wire [0:0] _zz_303; - wire [0:0] _zz_304; - wire [0:0] _zz_305; - wire [0:0] _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire [0:0] _zz_312; - wire [0:0] _zz_313; - wire [0:0] _zz_314; - wire [0:0] _zz_315; - wire [0:0] _zz_316; - wire [3:0] _zz_317; - wire [2:0] _zz_318; - wire [31:0] _zz_319; - wire [11:0] _zz_320; - wire [31:0] _zz_321; - wire [19:0] _zz_322; - wire [11:0] _zz_323; - wire [31:0] _zz_324; - wire [31:0] _zz_325; - wire [19:0] _zz_326; - wire [11:0] _zz_327; - wire [2:0] _zz_328; - wire [2:0] _zz_329; - wire [0:0] _zz_330; - wire [2:0] _zz_331; - wire [4:0] _zz_332; - wire [11:0] _zz_333; - wire [11:0] _zz_334; - wire [31:0] _zz_335; - wire [31:0] _zz_336; - wire [31:0] _zz_337; - wire [31:0] _zz_338; - wire [31:0] _zz_339; - wire [31:0] _zz_340; - wire [31:0] _zz_341; - wire [11:0] _zz_342; - wire [19:0] _zz_343; - wire [11:0] _zz_344; - wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [11:0] _zz_348; - wire [19:0] _zz_349; - wire [11:0] _zz_350; - wire [2:0] _zz_351; - wire [1:0] _zz_352; - wire [1:0] _zz_353; - wire [1:0] _zz_354; - wire [1:0] _zz_355; - wire [9:0] _zz_356; - wire [7:0] _zz_357; - wire [65:0] _zz_358; - wire [65:0] _zz_359; - wire [31:0] _zz_360; - wire [31:0] _zz_361; - wire [0:0] _zz_362; - wire [5:0] _zz_363; - wire [32:0] _zz_364; - wire [31:0] _zz_365; - wire [31:0] _zz_366; - wire [32:0] _zz_367; - wire [32:0] _zz_368; - wire [32:0] _zz_369; - wire [32:0] _zz_370; - wire [0:0] _zz_371; - wire [32:0] _zz_372; - wire [0:0] _zz_373; - wire [32:0] _zz_374; - wire [0:0] _zz_375; - wire [31:0] _zz_376; - wire [0:0] _zz_377; - wire [0:0] _zz_378; - wire [0:0] _zz_379; - wire [0:0] _zz_380; - wire [0:0] _zz_381; - wire [0:0] _zz_382; - wire [0:0] _zz_383; - wire [26:0] _zz_384; - wire _zz_385; - wire _zz_386; - wire [1:0] _zz_387; - wire [31:0] _zz_388; - wire [31:0] _zz_389; - wire [31:0] _zz_390; - wire _zz_391; - wire [0:0] _zz_392; - wire [14:0] _zz_393; - wire [31:0] _zz_394; - wire [31:0] _zz_395; - wire [31:0] _zz_396; - wire _zz_397; - wire [0:0] _zz_398; - wire [8:0] _zz_399; - wire [31:0] _zz_400; - wire [31:0] _zz_401; - wire [31:0] _zz_402; - wire _zz_403; - wire [0:0] _zz_404; - wire [2:0] _zz_405; - wire _zz_406; - wire _zz_407; - wire _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire _zz_411; - wire _zz_412; - wire [0:0] _zz_413; - wire [26:0] _zz_414; - wire [31:0] _zz_415; - wire [31:0] _zz_416; - wire [31:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire [1:0] _zz_420; - wire [1:0] _zz_421; - wire _zz_422; - wire [0:0] _zz_423; - wire [21:0] _zz_424; - wire [31:0] _zz_425; - wire [31:0] _zz_426; - wire [31:0] _zz_427; - wire [31:0] _zz_428; - wire [31:0] _zz_429; - wire [31:0] _zz_430; - wire [0:0] _zz_431; - wire [0:0] _zz_432; - wire [2:0] _zz_433; - wire [2:0] _zz_434; - wire _zz_435; - wire [0:0] _zz_436; - wire [18:0] _zz_437; - wire [31:0] _zz_438; - wire [31:0] _zz_439; - wire [31:0] _zz_440; - wire [31:0] _zz_441; - wire _zz_442; - wire _zz_443; - wire [31:0] _zz_444; - wire [31:0] _zz_445; - wire _zz_446; - wire [0:0] _zz_447; - wire [0:0] _zz_448; - wire _zz_449; - wire [0:0] _zz_450; - wire [15:0] _zz_451; - wire [31:0] _zz_452; - wire _zz_453; - wire _zz_454; - wire _zz_455; - wire [2:0] _zz_456; - wire [2:0] _zz_457; - wire _zz_458; - wire [0:0] _zz_459; - wire [12:0] _zz_460; - wire _zz_461; - wire _zz_462; - wire _zz_463; - wire [0:0] _zz_464; - wire [2:0] _zz_465; - wire _zz_466; - wire [5:0] _zz_467; - wire [5:0] _zz_468; - wire _zz_469; - wire [0:0] _zz_470; - wire [9:0] _zz_471; - wire [31:0] _zz_472; - wire [31:0] _zz_473; - wire [31:0] _zz_474; - wire [31:0] _zz_475; - wire [31:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [0:0] _zz_479; - wire [31:0] _zz_480; - wire _zz_481; - wire [0:0] _zz_482; - wire [3:0] _zz_483; - wire [0:0] _zz_484; - wire [3:0] _zz_485; - wire [5:0] _zz_486; - wire [5:0] _zz_487; - wire _zz_488; - wire [0:0] _zz_489; - wire [7:0] _zz_490; - wire [31:0] _zz_491; - wire [31:0] _zz_492; - wire [31:0] _zz_493; - wire [31:0] _zz_494; - wire [31:0] _zz_495; - wire [31:0] _zz_496; - wire [31:0] _zz_497; - wire [31:0] _zz_498; - wire [0:0] _zz_499; - wire [1:0] _zz_500; - wire _zz_501; - wire [0:0] _zz_502; - wire [1:0] _zz_503; - wire [0:0] _zz_504; - wire [3:0] _zz_505; - wire [0:0] _zz_506; - wire [0:0] _zz_507; - wire [1:0] _zz_508; - wire [1:0] _zz_509; - wire _zz_510; - wire [0:0] _zz_511; - wire [5:0] _zz_512; - wire [31:0] _zz_513; - wire [31:0] _zz_514; - wire _zz_515; - wire _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire _zz_520; - wire _zz_521; - wire [31:0] _zz_522; - wire [31:0] _zz_523; - wire _zz_524; - wire [0:0] _zz_525; - wire [1:0] _zz_526; - wire [31:0] _zz_527; - wire [31:0] _zz_528; - wire _zz_529; - wire _zz_530; - wire [0:0] _zz_531; - wire [0:0] _zz_532; - wire _zz_533; - wire [0:0] _zz_534; - wire [3:0] _zz_535; - wire [31:0] _zz_536; - wire [31:0] _zz_537; - wire [31:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire [31:0] _zz_541; - wire [31:0] _zz_542; - wire _zz_543; - wire _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire [0:0] _zz_549; - wire [2:0] _zz_550; - wire [0:0] _zz_551; - wire [0:0] _zz_552; - wire _zz_553; - wire [0:0] _zz_554; - wire [1:0] _zz_555; - wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire _zz_559; - wire _zz_560; - wire [31:0] _zz_561; - wire _zz_562; - wire [0:0] _zz_563; - wire [0:0] _zz_564; - wire [0:0] _zz_565; - wire [0:0] _zz_566; - wire [1:0] _zz_567; - wire [1:0] _zz_568; - wire [0:0] _zz_569; - wire [0:0] _zz_570; - wire [31:0] _zz_571; - wire [31:0] _zz_572; - wire [31:0] _zz_573; - wire [31:0] _zz_574; - wire [31:0] _zz_575; - wire [31:0] _zz_576; - wire _zz_577; - wire _zz_578; - wire _zz_579; - wire [31:0] _zz_580; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6; + wire [26:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18; + wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33; + wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45; + wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68; + wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100; + wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125; + wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1; + wire _zz_when; + wire _zz_when_1; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_41; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; - wire writeBack_CfuPlugin_CFU_IN_FLIGHT; - wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; wire decode_SRC2_FORCE_ZERO; + wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + wire decode_CfuPlugin_CFU_ENABLE; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_DIV; wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_1; - wire `Input2Kind_defaultEncoding_type _zz_2; - wire `Input2Kind_defaultEncoding_type _zz_3; - wire decode_CfuPlugin_CFU_ENABLE; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -538,24 +478,30 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; - wire `AluCtrlEnum_defaultEncoding_type _zz_25; - wire `AluCtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; - wire `Src1CtrlEnum_defaultEncoding_type _zz_28; - wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] memory_PC; + reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire execute_CfuPlugin_CFU_ENABLE; wire execute_IS_RS1_SIGNED; wire execute_IS_DIV; wire execute_IS_RS2_SIGNED; @@ -566,32 +512,26 @@ module VexRiscv ( wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; - reg _zz_30; - reg _zz_31; - wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_32; - wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_37; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -601,46 +541,46 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_38; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_41; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_42; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; - wire [31:0] _zz_46; - wire _zz_47; - reg _zz_48; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_49; - wire `EnvCtrlEnum_defaultEncoding_type _zz_50; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; - wire `Src2CtrlEnum_defaultEncoding_type _zz_54; - wire `AluCtrlEnum_defaultEncoding_type _zz_55; - wire `Src1CtrlEnum_defaultEncoding_type _zz_56; - reg [31:0] _zz_57; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -658,11 +598,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_59; - reg [31:0] _zz_60; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -692,7 +632,7 @@ module VexRiscv ( wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; + wire memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; @@ -749,7 +689,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -783,6 +723,11 @@ module VexRiscv ( reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; wire CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -800,31 +745,34 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; wire CsrPlugin_allowInterrupts; wire CsrPlugin_allowException; - reg CfuPlugin_joinException_valid; - wire [3:0] CfuPlugin_joinException_payload_code; - wire [31:0] CfuPlugin_joinException_payload_badAddr; + wire CsrPlugin_allowEbreakException; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_61; - wire [3:0] _zz_62; - wire _zz_63; - wire _zz_64; - wire _zz_65; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -847,16 +795,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_66; - wire _zz_67; - wire _zz_68; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_69; - wire _zz_70; - reg _zz_71; - wire _zz_72; - reg _zz_73; - reg [31:0] _zz_74; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -864,22 +814,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_75; - reg [18:0] _zz_76; - wire _zz_77; - reg [10:0] _zz_78; - wire _zz_79; - reg [18:0] _zz_80; - reg _zz_81; - wire _zz_82; - reg [10:0] _zz_83; - wire _zz_84; - reg [18:0] _zz_85; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -887,7 +844,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_86; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -895,23 +852,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -919,40 +881,56 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_87; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_88; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_89; - reg [31:0] _zz_90; - wire _zz_91; - reg [31:0] _zz_92; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [33:0] _zz_93; - wire _zz_94; - wire _zz_95; - wire _zz_96; - wire _zz_97; - wire _zz_98; - wire `Src1CtrlEnum_defaultEncoding_type _zz_99; - wire `AluCtrlEnum_defaultEncoding_type _zz_100; - wire `Src2CtrlEnum_defaultEncoding_type _zz_101; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_102; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_103; - wire `BranchCtrlEnum_defaultEncoding_type _zz_104; - wire `EnvCtrlEnum_defaultEncoding_type _zz_105; - wire `Input2Kind_defaultEncoding_type _zz_106; + wire when_DBusCachedPlugin_l484; + wire [33:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -960,53 +938,72 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_107; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_108; - reg [31:0] _zz_109; - wire _zz_110; - reg [19:0] _zz_111; - wire _zz_112; - reg [19:0] _zz_113; - reg [31:0] _zz_114; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_115; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_116; - reg _zz_117; - reg _zz_118; - reg _zz_119; - reg [4:0] _zz_120; - reg [31:0] _zz_121; - wire _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; - wire _zz_126; - wire _zz_127; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_128; - reg _zz_129; - reg _zz_130; - wire _zz_131; - reg [19:0] _zz_132; - wire _zz_133; - reg [10:0] _zz_134; - wire _zz_135; - reg [18:0] _zz_136; - reg _zz_137; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_138; - reg [19:0] _zz_139; - wire _zz_140; - reg [10:0] _zz_141; - wire _zz_142; - reg [18:0] _zz_143; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; + wire when_BranchPlugin_l296; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1027,9 +1024,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_144; - wire _zz_145; - wire _zz_146; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1042,72 +1039,69 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_147; - wire _zz_148; - wire [1:0] _zz_149; - wire _zz_150; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_151; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - wire execute_CfuPlugin_schedule; - reg execute_CfuPlugin_hold; - reg execute_CfuPlugin_fired; - wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_167; - reg [23:0] _zz_168; - reg [31:0] _zz_169; - wire memory_CfuPlugin_rsp_valid; - reg memory_CfuPlugin_rsp_ready; - wire memory_CfuPlugin_rsp_payload_response_ok; - wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_s2mPipe_rValid; - reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1115,6 +1109,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1127,242 +1123,402 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_170; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_171; - wire _zz_172; - wire _zz_173; - reg [32:0] _zz_174; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_175; - wire [31:0] _zz_176; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire CfuPlugin_bus_cmd_fire; + wire when_CfuPlugin_l171; + wire when_CfuPlugin_l175; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_CfuPlugin_bus_cmd_payload_inputs_1; + reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1; + reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + wire CfuPlugin_bus_rsp_rsp_valid; + reg CfuPlugin_bus_rsp_rsp_ready; + wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_rValid; + reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; + wire when_CfuPlugin_l208; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_when_GenCoreDefault_l367; + wire when_GenCoreDefault_l367; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_when_GenCoreDefault_l367_1; + wire when_GenCoreDefault_l367_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_when_GenCoreDefault_l367_2; + wire when_GenCoreDefault_l367_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_when_GenCoreDefault_l367_3; + wire when_GenCoreDefault_l367_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_when_GenCoreDefault_l367_4; + wire when_GenCoreDefault_l367_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_when_GenCoreDefault_l367_5; + wire when_GenCoreDefault_l367_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_when_GenCoreDefault_l367_6; + wire when_GenCoreDefault_l367_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_when_GenCoreDefault_l367_7; + wire when_GenCoreDefault_l367_7; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + wire when_Pipeline_l124_44; + reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_45; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_46; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_47; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_48; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_49; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_50; reg decode_to_execute_CSR_READ_OPCODE; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_51; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_52; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_53; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_54; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_55; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_57; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_60; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_61; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_62; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_63; reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; + reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; + reg execute_CsrPlugin_csr_4032; + wire when_CsrPlugin_l1264_24; reg execute_CsrPlugin_csr_2820; + wire when_CsrPlugin_l1264_25; reg execute_CsrPlugin_csr_2821; + wire when_CsrPlugin_l1264_26; reg execute_CsrPlugin_csr_2822; + wire when_CsrPlugin_l1264_27; reg execute_CsrPlugin_csr_2823; + wire when_CsrPlugin_l1264_28; reg execute_CsrPlugin_csr_2824; + wire when_CsrPlugin_l1264_29; reg execute_CsrPlugin_csr_2825; + wire when_CsrPlugin_l1264_30; reg execute_CsrPlugin_csr_2826; + wire when_CsrPlugin_l1264_31; reg execute_CsrPlugin_csr_2827; + wire when_CsrPlugin_l1264_32; reg execute_CsrPlugin_csr_2828; + wire when_CsrPlugin_l1264_33; reg execute_CsrPlugin_csr_2829; + wire when_CsrPlugin_l1264_34; reg execute_CsrPlugin_csr_2830; + wire when_CsrPlugin_l1264_35; reg execute_CsrPlugin_csr_2831; + wire when_CsrPlugin_l1264_36; reg execute_CsrPlugin_csr_2832; + wire when_CsrPlugin_l1264_37; reg execute_CsrPlugin_csr_2833; + wire when_CsrPlugin_l1264_38; reg execute_CsrPlugin_csr_2834; + wire when_CsrPlugin_l1264_39; reg execute_CsrPlugin_csr_2835; - reg execute_CsrPlugin_csr_3008; - reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_177; - reg [31:0] _zz_178; - reg [31:0] _zz_179; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [31:0] _zz_199; - reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; - reg [2:0] _zz_208; - reg _zz_209; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_29; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_30; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_31; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_32; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_33; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_34; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_35; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_36; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_37; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_38; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_39; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_40; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_210; - wire _zz_211; - wire _zz_212; - wire _zz_213; - wire _zz_214; - wire _zz_215; - reg _zz_216; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8_string; - reg [39:0] _zz_9_string; - reg [39:0] _zz_10_string; - reg [31:0] _zz_11_string; - reg [31:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_15_string; - reg [71:0] _zz_16_string; - reg [71:0] _zz_17_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_18_string; - reg [39:0] _zz_19_string; - reg [39:0] _zz_20_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_21_string; - reg [23:0] _zz_22_string; - reg [23:0] _zz_23_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_24_string; - reg [63:0] _zz_25_string; - reg [63:0] _zz_26_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_27_string; - reg [95:0] _zz_28_string; - reg [95:0] _zz_29_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_32_string; + reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_36_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_39_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_40_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_42_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_43_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_44_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_45_string; - reg [39:0] _zz_49_string; - reg [39:0] _zz_50_string; - reg [31:0] _zz_51_string; - reg [71:0] _zz_52_string; - reg [39:0] _zz_53_string; - reg [23:0] _zz_54_string; - reg [63:0] _zz_55_string; - reg [95:0] _zz_56_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_58_string; - reg [95:0] _zz_99_string; - reg [63:0] _zz_100_string; - reg [23:0] _zz_101_string; - reg [39:0] _zz_102_string; - reg [71:0] _zz_103_string; - reg [31:0] _zz_104_string; - reg [39:0] _zz_105_string; - reg [39:0] _zz_106_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1378,473 +1534,437 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_248 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_249 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_250 = 1'b1; - assign _zz_251 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_252 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_253 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_254 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_255 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_256 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_257 = ((_zz_222 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_258 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_259 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_260 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_261 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_262 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_263 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_264 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_265 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_266 = (1'b0 || (! 1'b1)); - assign _zz_267 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_268 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_269 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_270 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_271 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_272 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_273 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_274 = execute_INSTRUCTION[13 : 12]; - assign _zz_275 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_276 = (! memory_arbitration_isStuck); - assign _zz_277 = (iBus_cmd_valid || (_zz_208 != 3'b000)); - assign _zz_278 = (_zz_244 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_279 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_280 = ((_zz_144 && 1'b1) && (! 1'b0)); - assign _zz_281 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_282 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_283 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_284 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_285 = execute_INSTRUCTION[13]; - assign _zz_286 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_287 = ($signed(_zz_288) + $signed(_zz_293)); - assign _zz_288 = ($signed(_zz_289) + $signed(_zz_291)); - assign _zz_289 = 52'h0; - assign _zz_290 = {1'b0,memory_MUL_LL}; - assign _zz_291 = {{19{_zz_290[32]}}, _zz_290}; - assign _zz_292 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_293 = {{2{_zz_292[49]}}, _zz_292}; - assign _zz_294 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_295 = {{2{_zz_294[49]}}, _zz_294}; - assign _zz_296 = ($signed(_zz_298) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_297 = _zz_296[31 : 0]; - assign _zz_298 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_299 = _zz_93[33 : 33]; - assign _zz_300 = _zz_93[32 : 32]; - assign _zz_301 = _zz_93[31 : 31]; - assign _zz_302 = _zz_93[30 : 30]; - assign _zz_303 = _zz_93[28 : 28]; - assign _zz_304 = _zz_93[25 : 25]; - assign _zz_305 = _zz_93[17 : 17]; - assign _zz_306 = _zz_93[16 : 16]; - assign _zz_307 = _zz_93[13 : 13]; - assign _zz_308 = _zz_93[12 : 12]; - assign _zz_309 = _zz_93[11 : 11]; - assign _zz_310 = _zz_93[15 : 15]; - assign _zz_311 = _zz_93[5 : 5]; - assign _zz_312 = _zz_93[3 : 3]; - assign _zz_313 = _zz_93[20 : 20]; - assign _zz_314 = _zz_93[10 : 10]; - assign _zz_315 = _zz_93[4 : 4]; - assign _zz_316 = _zz_93[0 : 0]; - assign _zz_317 = (_zz_61 - 4'b0001); - assign _zz_318 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_319 = {29'd0, _zz_318}; - assign _zz_320 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_321 = {{_zz_76,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_322 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_323 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_324 = {{_zz_78,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_325 = {{_zz_80,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_326 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_327 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_328 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_329 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_330 = execute_SRC_LESS; - assign _zz_331 = 3'b100; - assign _zz_332 = execute_INSTRUCTION[19 : 15]; - assign _zz_333 = execute_INSTRUCTION[31 : 20]; - assign _zz_334 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_335 = ($signed(_zz_336) + $signed(_zz_339)); - assign _zz_336 = ($signed(_zz_337) + $signed(_zz_338)); - assign _zz_337 = execute_SRC1; - assign _zz_338 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_339 = (execute_SRC_USE_SUB_LESS ? _zz_340 : _zz_341); - assign _zz_340 = 32'h00000001; - assign _zz_341 = 32'h0; - assign _zz_342 = execute_INSTRUCTION[31 : 20]; - assign _zz_343 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_344 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_345 = {_zz_132,execute_INSTRUCTION[31 : 20]}; - assign _zz_346 = {{_zz_134,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_347 = {{_zz_136,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_348 = execute_INSTRUCTION[31 : 20]; - assign _zz_349 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_350 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_351 = 3'b100; - assign _zz_352 = (_zz_147 & (~ _zz_353)); - assign _zz_353 = (_zz_147 - 2'b01); - assign _zz_354 = (_zz_149 & (~ _zz_355)); - assign _zz_355 = (_zz_149 - 2'b01); - assign _zz_356 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_357 = execute_INSTRUCTION[31 : 24]; - assign _zz_358 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_359 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_360 = writeBack_MUL_LOW[31 : 0]; - assign _zz_361 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_362 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_363 = {5'd0, _zz_362}; - assign _zz_364 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_365 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_366 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_367 = {_zz_170,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_368 = _zz_369; - assign _zz_369 = _zz_370; - assign _zz_370 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_171) : _zz_171)} + _zz_372); - assign _zz_371 = memory_DivPlugin_div_needRevert; - assign _zz_372 = {32'd0, _zz_371}; - assign _zz_373 = _zz_173; - assign _zz_374 = {32'd0, _zz_373}; - assign _zz_375 = _zz_172; - assign _zz_376 = {31'd0, _zz_375}; - assign _zz_377 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_378 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_379 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_380 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_381 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_382 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_383 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_384 = (iBus_cmd_payload_address >>> 5); - assign _zz_385 = 1'b1; - assign _zz_386 = 1'b1; - assign _zz_387 = {_zz_65,_zz_64}; - assign _zz_388 = 32'h0000106f; - assign _zz_389 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_390 = 32'h00001073; - assign _zz_391 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_392 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_393 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_394) == 32'h00000003),{(_zz_395 == _zz_396),{_zz_397,{_zz_398,_zz_399}}}}}}; - assign _zz_394 = 32'h0000207f; - assign _zz_395 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_396 = 32'h00000003; - assign _zz_397 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_398 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_399 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_400) == 32'h00005013),{(_zz_401 == _zz_402),{_zz_403,{_zz_404,_zz_405}}}}}}; - assign _zz_400 = 32'hbc00707f; - assign _zz_401 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_402 = 32'h00001013; - assign _zz_403 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_404 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_405 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; - assign _zz_406 = decode_INSTRUCTION[31]; - assign _zz_407 = decode_INSTRUCTION[31]; - assign _zz_408 = decode_INSTRUCTION[7]; - assign _zz_409 = (decode_INSTRUCTION & 32'h02004064); - assign _zz_410 = 32'h02004020; - assign _zz_411 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); - assign _zz_412 = (_zz_97 != 1'b0); - assign _zz_413 = (((decode_INSTRUCTION & _zz_415) == 32'h00000050) != 1'b0); - assign _zz_414 = {((_zz_416 == _zz_417) != 1'b0),{({_zz_418,_zz_419} != 2'b00),{(_zz_420 != _zz_421),{_zz_422,{_zz_423,_zz_424}}}}}; - assign _zz_415 = 32'h00203050; - assign _zz_416 = (decode_INSTRUCTION & 32'h00403050); - assign _zz_417 = 32'h00000050; - assign _zz_418 = ((decode_INSTRUCTION & _zz_425) == 32'h00001050); - assign _zz_419 = ((decode_INSTRUCTION & _zz_426) == 32'h00002050); - assign _zz_420 = {_zz_96,(_zz_427 == _zz_428)}; - assign _zz_421 = 2'b00; - assign _zz_422 = ((_zz_429 == _zz_430) != 1'b0); - assign _zz_423 = ({_zz_431,_zz_432} != 2'b00); - assign _zz_424 = {(_zz_433 != _zz_434),{_zz_435,{_zz_436,_zz_437}}}; - assign _zz_425 = 32'h00001050; - assign _zz_426 = 32'h00002050; - assign _zz_427 = (decode_INSTRUCTION & 32'h0000001c); - assign _zz_428 = 32'h00000004; - assign _zz_429 = (decode_INSTRUCTION & 32'h00000058); - assign _zz_430 = 32'h00000040; - assign _zz_431 = ((decode_INSTRUCTION & _zz_438) == 32'h00005010); - assign _zz_432 = ((decode_INSTRUCTION & _zz_439) == 32'h00005020); - assign _zz_433 = {(_zz_440 == _zz_441),{_zz_442,_zz_443}}; - assign _zz_434 = 3'b000; - assign _zz_435 = ((_zz_444 == _zz_445) != 1'b0); - assign _zz_436 = (_zz_446 != 1'b0); - assign _zz_437 = {(_zz_447 != _zz_448),{_zz_449,{_zz_450,_zz_451}}}; - assign _zz_438 = 32'h00007034; - assign _zz_439 = 32'h02007064; - assign _zz_440 = (decode_INSTRUCTION & 32'h40003054); - assign _zz_441 = 32'h40001010; - assign _zz_442 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00001010); - assign _zz_443 = ((decode_INSTRUCTION & 32'h02007054) == 32'h00001010); - assign _zz_444 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_445 = 32'h00000024; - assign _zz_446 = ((decode_INSTRUCTION & 32'h00001000) == 32'h00001000); - assign _zz_447 = ((decode_INSTRUCTION & _zz_452) == 32'h00002000); - assign _zz_448 = 1'b0; - assign _zz_449 = ({_zz_453,_zz_454} != 2'b00); - assign _zz_450 = (_zz_455 != 1'b0); - assign _zz_451 = {(_zz_456 != _zz_457),{_zz_458,{_zz_459,_zz_460}}}; - assign _zz_452 = 32'h00003000; - assign _zz_453 = ((decode_INSTRUCTION & 32'h00002010) == 32'h00002000); - assign _zz_454 = ((decode_INSTRUCTION & 32'h00005000) == 32'h00001000); - assign _zz_455 = ((decode_INSTRUCTION & 32'h00004054) == 32'h00004004); - assign _zz_456 = {_zz_97,{_zz_461,_zz_462}}; - assign _zz_457 = 3'b000; - assign _zz_458 = ({_zz_463,{_zz_464,_zz_465}} != 5'h0); - assign _zz_459 = (_zz_466 != 1'b0); - assign _zz_460 = {(_zz_467 != _zz_468),{_zz_469,{_zz_470,_zz_471}}}; - assign _zz_461 = ((decode_INSTRUCTION & _zz_472) == 32'h00000020); - assign _zz_462 = ((decode_INSTRUCTION & _zz_473) == 32'h00000020); - assign _zz_463 = ((decode_INSTRUCTION & _zz_474) == 32'h00002040); - assign _zz_464 = (_zz_475 == _zz_476); - assign _zz_465 = {_zz_477,{_zz_478,_zz_479}}; - assign _zz_466 = ((decode_INSTRUCTION & _zz_480) == 32'h00000020); - assign _zz_467 = {_zz_481,{_zz_482,_zz_483}}; - assign _zz_468 = 6'h0; - assign _zz_469 = ({_zz_484,_zz_485} != 5'h0); - assign _zz_470 = (_zz_486 != _zz_487); - assign _zz_471 = {_zz_488,{_zz_489,_zz_490}}; - assign _zz_472 = 32'h00000034; - assign _zz_473 = 32'h00000064; - assign _zz_474 = 32'h00002040; - assign _zz_475 = (decode_INSTRUCTION & 32'h00001040); - assign _zz_476 = 32'h00001040; - assign _zz_477 = ((decode_INSTRUCTION & _zz_491) == 32'h00000040); - assign _zz_478 = (_zz_492 == _zz_493); - assign _zz_479 = (_zz_494 == _zz_495); - assign _zz_480 = 32'h00000020; - assign _zz_481 = ((decode_INSTRUCTION & _zz_496) == 32'h00000008); - assign _zz_482 = (_zz_497 == _zz_498); - assign _zz_483 = {_zz_95,{_zz_499,_zz_500}}; - assign _zz_484 = _zz_95; - assign _zz_485 = {_zz_501,{_zz_502,_zz_503}}; - assign _zz_486 = {_zz_96,{_zz_504,_zz_505}}; - assign _zz_487 = 6'h0; - assign _zz_488 = ({_zz_506,_zz_507} != 2'b00); - assign _zz_489 = (_zz_508 != _zz_509); - assign _zz_490 = {_zz_510,{_zz_511,_zz_512}}; - assign _zz_491 = 32'h00000050; - assign _zz_492 = (decode_INSTRUCTION & 32'h00400040); - assign _zz_493 = 32'h00000040; - assign _zz_494 = (decode_INSTRUCTION & 32'h00000038); - assign _zz_495 = 32'h0; - assign _zz_496 = 32'h00000008; - assign _zz_497 = (decode_INSTRUCTION & 32'h00000040); - assign _zz_498 = 32'h00000040; - assign _zz_499 = (_zz_513 == _zz_514); - assign _zz_500 = {_zz_515,_zz_516}; - assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00002010); - assign _zz_502 = (_zz_518 == _zz_519); - assign _zz_503 = {_zz_520,_zz_521}; - assign _zz_504 = (_zz_522 == _zz_523); - assign _zz_505 = {_zz_524,{_zz_525,_zz_526}}; - assign _zz_506 = _zz_95; - assign _zz_507 = (_zz_527 == _zz_528); - assign _zz_508 = {_zz_95,_zz_529}; - assign _zz_509 = 2'b00; - assign _zz_510 = (_zz_530 != 1'b0); - assign _zz_511 = (_zz_531 != _zz_532); - assign _zz_512 = {_zz_533,{_zz_534,_zz_535}}; - assign _zz_513 = (decode_INSTRUCTION & 32'h00004020); - assign _zz_514 = 32'h00004020; - assign _zz_515 = ((decode_INSTRUCTION & _zz_536) == 32'h00000010); - assign _zz_516 = ((decode_INSTRUCTION & _zz_537) == 32'h00000020); - assign _zz_517 = 32'h00002030; - assign _zz_518 = (decode_INSTRUCTION & 32'h00001030); - assign _zz_519 = 32'h00000010; - assign _zz_520 = ((decode_INSTRUCTION & _zz_538) == 32'h00002020); - assign _zz_521 = ((decode_INSTRUCTION & _zz_539) == 32'h00000020); - assign _zz_522 = (decode_INSTRUCTION & 32'h00001010); - assign _zz_523 = 32'h00001010; - assign _zz_524 = ((decode_INSTRUCTION & _zz_540) == 32'h00002010); - assign _zz_525 = (_zz_541 == _zz_542); - assign _zz_526 = {_zz_543,_zz_544}; - assign _zz_527 = (decode_INSTRUCTION & 32'h00000070); - assign _zz_528 = 32'h00000020; - assign _zz_529 = ((decode_INSTRUCTION & _zz_545) == 32'h0); - assign _zz_530 = ((decode_INSTRUCTION & _zz_546) == 32'h00004010); - assign _zz_531 = (_zz_547 == _zz_548); - assign _zz_532 = 1'b0; - assign _zz_533 = ({_zz_549,_zz_550} != 4'b0000); - assign _zz_534 = (_zz_551 != _zz_552); - assign _zz_535 = {_zz_553,{_zz_554,_zz_555}}; - assign _zz_536 = 32'h00000030; - assign _zz_537 = 32'h02000020; - assign _zz_538 = 32'h02002060; - assign _zz_539 = 32'h02003020; - assign _zz_540 = 32'h00002010; - assign _zz_541 = (decode_INSTRUCTION & 32'h00000050); - assign _zz_542 = 32'h00000010; - assign _zz_543 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); - assign _zz_544 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); - assign _zz_545 = 32'h00000020; - assign _zz_546 = 32'h00004014; - assign _zz_547 = (decode_INSTRUCTION & 32'h00006014); - assign _zz_548 = 32'h00002010; - assign _zz_549 = ((decode_INSTRUCTION & _zz_556) == 32'h0); - assign _zz_550 = {(_zz_557 == _zz_558),{_zz_559,_zz_560}}; - assign _zz_551 = ((decode_INSTRUCTION & _zz_561) == 32'h0); - assign _zz_552 = 1'b0; - assign _zz_553 = ({_zz_562,{_zz_563,_zz_564}} != 3'b000); - assign _zz_554 = ({_zz_565,_zz_566} != 2'b00); - assign _zz_555 = {(_zz_567 != _zz_568),(_zz_569 != _zz_570)}; - assign _zz_556 = 32'h00000044; - assign _zz_557 = (decode_INSTRUCTION & 32'h00000018); - assign _zz_558 = 32'h0; - assign _zz_559 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); - assign _zz_560 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); - assign _zz_561 = 32'h00000058; - assign _zz_562 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); - assign _zz_563 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); - assign _zz_564 = ((decode_INSTRUCTION & _zz_572) == 32'h40000030); - assign _zz_565 = ((decode_INSTRUCTION & _zz_573) == 32'h00000004); - assign _zz_566 = _zz_94; - assign _zz_567 = {(_zz_574 == _zz_575),_zz_94}; - assign _zz_568 = 2'b00; - assign _zz_569 = ((decode_INSTRUCTION & _zz_576) == 32'h00001004); - assign _zz_570 = 1'b0; - assign _zz_571 = 32'h00002014; - assign _zz_572 = 32'h40000034; - assign _zz_573 = 32'h00000014; - assign _zz_574 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_575 = 32'h00000004; - assign _zz_576 = 32'h00005054; - assign _zz_577 = execute_INSTRUCTION[31]; - assign _zz_578 = execute_INSTRUCTION[31]; - assign _zz_579 = execute_INSTRUCTION[7]; - assign _zz_580 = 32'h0; - always @ (posedge clk) begin - if(_zz_385) begin - _zz_245 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_386) begin - _zz_246 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_48) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19}}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 32'h02004074; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (decode_INSTRUCTION & 32'h00203050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h00000050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h00403050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = 32'h00001050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00002050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = 32'h00005010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = 32'h00007034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h02007054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = 32'h00002000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48) == 32'h00004004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00005000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = 32'h00004054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57) == 32'h00002040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79}} != 6'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = 32'h00000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000064; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = 32'h00002040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = 32'h00001040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75) == 32'h00000008); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = 6'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00000050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = (decode_INSTRUCTION & 32'h00400040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = 32'h00000008; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = 32'h00004020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85) == 32'h00000010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = 32'h00002030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98) == 32'h00002020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129) == 32'h00004010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139} != 4'b0000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = 32'h00000030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h02000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = 32'h02002060; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02003020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = 32'h00004014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = 32'h00000044; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = 32'h00000058; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h40000030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165) == 32'h00001004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = 32'h00002014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h40000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = 32'h00000014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = 32'h00000004; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 32'h00005054; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_41 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_217 ), //i - .io_cpu_prefetch_isValid (_zz_218 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_219 ), //i - .io_cpu_fetch_isStuck (_zz_220 ), //i - .io_cpu_fetch_isRemoved (_zz_221 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_222 ), //i - .io_cpu_decode_isStuck (_zz_223 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_224 ), //i - .io_cpu_fill_valid (_zz_225 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_226 ), //i - .io_cpu_execute_address (_zz_227[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_88[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_228 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_229[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_230 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_231 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_232 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_233[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_234 ), //i - .io_cpu_writeBack_fence_SR (_zz_235 ), //i - .io_cpu_writeBack_fence_SO (_zz_236 ), //i - .io_cpu_writeBack_fence_SI (_zz_237 ), //i - .io_cpu_writeBack_fence_PW (_zz_238 ), //i - .io_cpu_writeBack_fence_PR (_zz_239 ), //i - .io_cpu_writeBack_fence_PO (_zz_240 ), //i - .io_cpu_writeBack_fence_PI (_zz_241 ), //i - .io_cpu_writeBack_fence_FM (_zz_242[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_243 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_244 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_387) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) 2'b00 : begin - _zz_247 = DBusCachedPlugin_redoBranch_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; end 2'b01 : begin - _zz_247 = CsrPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; end 2'b10 : begin - _zz_247 = BranchPlugin_jumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; end default : begin - _zz_247 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + end + 2'b01 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + end + 2'b10 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end @@ -1852,808 +1972,825 @@ module VexRiscv ( `ifndef SYNTHESIS always @(*) begin case(decode_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_1) - `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; - default : _zz_1_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; - default : _zz_2_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; - default : _zz_3_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; - default : _zz_8_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_9) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; - default : _zz_9_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_10) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; - default : _zz_10_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_11) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; - default : _zz_11_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_12) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; - default : _zz_12_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_16) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; - default : _zz_16_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_17) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; - default : _zz_17_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_19) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; - default : _zz_19_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_20) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; - default : _zz_20_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_25) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; - default : _zz_25_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_26) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; - default : _zz_26_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_28) - `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; - default : _zz_28_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_29) - `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; - default : _zz_29_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_32) - `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; - default : _zz_32_string = "?????"; + case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_36) - `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; - default : _zz_36_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_39) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; - default : _zz_39_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_40) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; - default : _zz_40_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_42) - `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; - default : _zz_42_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_43) - `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; - default : _zz_43_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_44) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; - default : _zz_44_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_45) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; - default : _zz_45_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_49) - `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; - default : _zz_49_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_50) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; - default : _zz_50_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_52) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; - default : _zz_52_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_53) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; - default : _zz_53_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_54) - `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; - default : _zz_54_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_55) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; - default : _zz_55_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_56) - `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; - default : _zz_56_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_58) - `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; - default : _zz_58_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_99) - `Src1CtrlEnum_defaultEncoding_RS : _zz_99_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_99_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_99_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_99_string = "URS1 "; - default : _zz_99_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_100) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_100_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_100_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_100_string = "BITWISE "; - default : _zz_100_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_101) - `Src2CtrlEnum_defaultEncoding_RS : _zz_101_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_101_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_101_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_101_string = "PC "; - default : _zz_101_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_102) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_102_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_102_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_102_string = "AND_1"; - default : _zz_102_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_103) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_103_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_103_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_103_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_103_string = "SRA_1 "; - default : _zz_103_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_104) - `BranchCtrlEnum_defaultEncoding_INC : _zz_104_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_104_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_104_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_104_string = "JALR"; - default : _zz_104_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_105) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_105_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_105_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_105_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_105_string = "ECALL"; - default : _zz_105_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_106) - `Input2Kind_defaultEncoding_RS : _zz_106_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_106_string = "IMM_I"; - default : _zz_106_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_287) + $signed(_zz_295)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_297; - assign execute_REGFILE_WRITE_DATA = _zz_108; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_227[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_299[0]; - assign decode_IS_RS1_SIGNED = _zz_300[0]; - assign decode_IS_DIV = _zz_301[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32]; + assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30]; + assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_302[0]; - assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; - assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_303[0]; - assign _zz_4 = _zz_5; - assign _zz_6 = _zz_7; - assign decode_ENV_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_304[0]; - assign _zz_11 = _zz_12; - assign _zz_13 = _zz_14; - assign decode_SHIFT_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_ALU_BITWISE_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_305[0]; - assign decode_MEMORY_MANAGMENT = _zz_306[0]; + assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_307[0]; + assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_308[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_309[0]; - assign decode_SRC2_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_ALU_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_SRC1_CTRL = _zz_27; - assign _zz_28 = _zz_29; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; + always @(*) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + always @(*) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2664,42 +2801,25 @@ module VexRiscv ( assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; - always @ (*) begin - _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; - if(memory_arbitration_isStuck)begin - _zz_30 = 1'b0; - end - end - - always @ (*) begin - _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; - if(execute_arbitration_isStuck)begin - _zz_31 = 1'b0; - end - end - - assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33; - assign execute_ENV_CTRL = _zz_34; - assign writeBack_ENV_CTRL = _zz_35; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_130; - assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_310[0]; - assign decode_RS1_USE = _zz_311[0]; - always @ (*) begin - _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_248)begin - _zz_37 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15]; + assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2709,142 +2829,142 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_119)begin - if((_zz_120 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_121; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_123)begin - decode_RS2 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_251)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin - decode_RS2 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_252)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin - decode_RS2 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_119)begin - if((_zz_120 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_121; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_249)begin - if(_zz_250)begin - if(_zz_122)begin - decode_RS1 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_251)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_124)begin - decode_RS1 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_252)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_126)begin - decode_RS1 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_38 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_116; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_38 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end - if(_zz_253)begin - _zz_38 = memory_DivPlugin_div_result; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + _zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0; end end - assign memory_SHIFT_CTRL = _zz_39; - assign execute_SHIFT_CTRL = _zz_40; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_41 = execute_PC; - assign execute_SRC2_CTRL = _zz_42; - assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_312[0]; - assign decode_SRC_ADD_ZERO = _zz_313[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_114; - assign execute_SRC1 = _zz_109; - assign execute_ALU_BITWISE_CTRL = _zz_45; - assign _zz_46 = writeBack_INSTRUCTION; - assign _zz_47 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_48 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_48 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_314[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_388) == 32'h00000003),{(_zz_389 == _zz_390),{_zz_391,{_zz_392,_zz_393}}}}}}} != 22'h0); - always @ (*) begin - _zz_57 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_286) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_57 = _zz_360; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_57 = _zz_361; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2856,214 +2976,205 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_315[0]; - assign decode_FLUSH_ALL = _zz_316[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4]; + assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_254)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_255)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_256)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_257)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_58; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_59 = execute_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_59 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_60 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_117 || _zz_118)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_258)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_258)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_243 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_259)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_248)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end - if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + if(when_CfuPlugin_l175) begin execute_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_260)begin + if(_zz_when_1) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end assign execute_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_260)begin + if(_zz_when_1) begin execute_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if((! memory_CfuPlugin_rsp_valid))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_253)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + if(when_CfuPlugin_l208) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushNext = 1'b0; + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_262)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3072,51 +3183,53 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_262)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_259)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end assign CsrPlugin_thirdPartyWake = 1'b0; - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_262)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_261)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_262)begin - case(_zz_263) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3129,59 +3242,65 @@ module VexRiscv ( assign CsrPlugin_forceMachineWire = 1'b0; assign CsrPlugin_allowInterrupts = 1'b1; assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_61 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_62 = (_zz_61 & (~ _zz_317)); - assign _zz_63 = _zz_62[3]; - assign _zz_64 = (_zz_62[1] || _zz_63); - assign _zz_65 = (_zz_62[2] || _zz_63); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_247; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_319); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3189,265 +3308,286 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_66 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_66); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_66); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_67); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_68); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_68); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_69; - assign _zz_69 = ((1'b0 && (! _zz_70)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_70 = _zz_71; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_70; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_72)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_72 = _zz_73; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_74; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - assign _zz_75 = _zz_320[11]; - always @ (*) begin - _zz_76[18] = _zz_75; - _zz_76[17] = _zz_75; - _zz_76[16] = _zz_75; - _zz_76[15] = _zz_75; - _zz_76[14] = _zz_75; - _zz_76[13] = _zz_75; - _zz_76[12] = _zz_75; - _zz_76[11] = _zz_75; - _zz_76[10] = _zz_75; - _zz_76[9] = _zz_75; - _zz_76[8] = _zz_75; - _zz_76[7] = _zz_75; - _zz_76[6] = _zz_75; - _zz_76[5] = _zz_75; - _zz_76[4] = _zz_75; - _zz_76[3] = _zz_75; - _zz_76[2] = _zz_75; - _zz_76[1] = _zz_75; - _zz_76[0] = _zz_75; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_321[31])); - if(_zz_81)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_77 = _zz_322[19]; - always @ (*) begin - _zz_78[10] = _zz_77; - _zz_78[9] = _zz_77; - _zz_78[8] = _zz_77; - _zz_78[7] = _zz_77; - _zz_78[6] = _zz_77; - _zz_78[5] = _zz_77; - _zz_78[4] = _zz_77; - _zz_78[3] = _zz_77; - _zz_78[2] = _zz_77; - _zz_78[1] = _zz_77; - _zz_78[0] = _zz_77; - end - - assign _zz_79 = _zz_323[11]; - always @ (*) begin - _zz_80[18] = _zz_79; - _zz_80[17] = _zz_79; - _zz_80[16] = _zz_79; - _zz_80[15] = _zz_79; - _zz_80[14] = _zz_79; - _zz_80[13] = _zz_79; - _zz_80[12] = _zz_79; - _zz_80[11] = _zz_79; - _zz_80[10] = _zz_79; - _zz_80[9] = _zz_79; - _zz_80[8] = _zz_79; - _zz_80[7] = _zz_79; - _zz_80[6] = _zz_79; - _zz_80[5] = _zz_79; - _zz_80[4] = _zz_79; - _zz_80[3] = _zz_79; - _zz_80[2] = _zz_79; - _zz_80[1] = _zz_79; - _zz_80[0] = _zz_79; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_81 = _zz_324[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_81 = _zz_325[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_82 = _zz_326[19]; - always @ (*) begin - _zz_83[10] = _zz_82; - _zz_83[9] = _zz_82; - _zz_83[8] = _zz_82; - _zz_83[7] = _zz_82; - _zz_83[6] = _zz_82; - _zz_83[5] = _zz_82; - _zz_83[4] = _zz_82; - _zz_83[3] = _zz_82; - _zz_83[2] = _zz_82; - _zz_83[1] = _zz_82; - _zz_83[0] = _zz_82; - end - - assign _zz_84 = _zz_327[11]; - always @ (*) begin - _zz_85[18] = _zz_84; - _zz_85[17] = _zz_84; - _zz_85[16] = _zz_84; - _zz_85[15] = _zz_84; - _zz_85[14] = _zz_84; - _zz_85[13] = _zz_84; - _zz_85[12] = _zz_84; - _zz_85[11] = _zz_84; - _zz_85[10] = _zz_84; - _zz_85[9] = _zz_84; - _zz_85[8] = _zz_84; - _zz_85[7] = _zz_84; - _zz_85[6] = _zz_84; - _zz_85[5] = _zz_84; - _zz_85[4] = _zz_84; - _zz_85[3] = _zz_84; - _zz_85[2] = _zz_84; - _zz_85[1] = _zz_84; - _zz_85[0] = _zz_84; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_83,{{{_zz_406,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_85,{{{_zz_407,_zz_408},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_218 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_219 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_220 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_219; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_224 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_257)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_255)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_225 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_255)begin - _zz_225 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_256)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_254)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_256)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_254)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_217 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_244 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3455,168 +3595,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_226 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_227 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_88 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_88 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_88 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_243 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_228 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_229 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_228; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_229; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_230 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((1'b0 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_230 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; end end - assign _zz_231 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_232 = (CsrPlugin_privilege == 2'b00); - assign _zz_233 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_264)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_264)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_264)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_328}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_329}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; end - assign _zz_89 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_90[31] = _zz_89; - _zz_90[30] = _zz_89; - _zz_90[29] = _zz_89; - _zz_90[28] = _zz_89; - _zz_90[27] = _zz_89; - _zz_90[26] = _zz_89; - _zz_90[25] = _zz_89; - _zz_90[24] = _zz_89; - _zz_90[23] = _zz_89; - _zz_90[22] = _zz_89; - _zz_90[21] = _zz_89; - _zz_90[20] = _zz_89; - _zz_90[19] = _zz_89; - _zz_90[18] = _zz_89; - _zz_90[17] = _zz_89; - _zz_90[16] = _zz_89; - _zz_90[15] = _zz_89; - _zz_90[14] = _zz_89; - _zz_90[13] = _zz_89; - _zz_90[12] = _zz_89; - _zz_90[11] = _zz_89; - _zz_90[10] = _zz_89; - _zz_90[9] = _zz_89; - _zz_90[8] = _zz_89; - _zz_90[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_91 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_92[31] = _zz_91; - _zz_92[30] = _zz_91; - _zz_92[29] = _zz_91; - _zz_92[28] = _zz_91; - _zz_92[27] = _zz_91; - _zz_92[26] = _zz_91; - _zz_92[25] = _zz_91; - _zz_92[24] = _zz_91; - _zz_92[23] = _zz_91; - _zz_92[22] = _zz_91; - _zz_92[21] = _zz_91; - _zz_92[20] = _zz_91; - _zz_92[19] = _zz_91; - _zz_92[18] = _zz_91; - _zz_92[17] = _zz_91; - _zz_92[16] = _zz_91; - _zz_92[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_284) + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_90; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_92; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3635,62 +3786,63 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_94 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_95 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_97 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_98 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_93 = {(_zz_98 != 1'b0),{(_zz_98 != 1'b0),{((_zz_409 == _zz_410) != 1'b0),{(_zz_411 != 1'b0),{1'b0,{_zz_412,{_zz_413,_zz_414}}}}}}}; - assign _zz_99 = _zz_93[2 : 1]; - assign _zz_56 = _zz_99; - assign _zz_100 = _zz_93[7 : 6]; - assign _zz_55 = _zz_100; - assign _zz_101 = _zz_93[9 : 8]; - assign _zz_54 = _zz_101; - assign _zz_102 = _zz_93[19 : 18]; - assign _zz_53 = _zz_102; - assign _zz_103 = _zz_93[22 : 21]; - assign _zz_52 = _zz_103; - assign _zz_104 = _zz_93[24 : 23]; - assign _zz_51 = _zz_104; - assign _zz_105 = _zz_93[27 : 26]; - assign _zz_50 = _zz_105; - assign _zz_106 = _zz_93[29 : 29]; - assign _zz_49 = _zz_106; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33 : 33]; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_245; - assign decode_RegFilePlugin_rs2Data = _zz_246; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_107)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_107)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_107)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3699,355 +3851,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_108 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_108 = {31'd0, _zz_330}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_108 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_109 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_109 = {29'd0, _zz_331}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_109 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_109 = {27'd0, _zz_332}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_110 = _zz_333[11]; - always @ (*) begin - _zz_111[19] = _zz_110; - _zz_111[18] = _zz_110; - _zz_111[17] = _zz_110; - _zz_111[16] = _zz_110; - _zz_111[15] = _zz_110; - _zz_111[14] = _zz_110; - _zz_111[13] = _zz_110; - _zz_111[12] = _zz_110; - _zz_111[11] = _zz_110; - _zz_111[10] = _zz_110; - _zz_111[9] = _zz_110; - _zz_111[8] = _zz_110; - _zz_111[7] = _zz_110; - _zz_111[6] = _zz_110; - _zz_111[5] = _zz_110; - _zz_111[4] = _zz_110; - _zz_111[3] = _zz_110; - _zz_111[2] = _zz_110; - _zz_111[1] = _zz_110; - _zz_111[0] = _zz_110; - end - - assign _zz_112 = _zz_334[11]; - always @ (*) begin - _zz_113[19] = _zz_112; - _zz_113[18] = _zz_112; - _zz_113[17] = _zz_112; - _zz_113[16] = _zz_112; - _zz_113[15] = _zz_112; - _zz_113[14] = _zz_112; - _zz_113[13] = _zz_112; - _zz_113[12] = _zz_112; - _zz_113[11] = _zz_112; - _zz_113[10] = _zz_112; - _zz_113[9] = _zz_112; - _zz_113[8] = _zz_112; - _zz_113[7] = _zz_112; - _zz_113[6] = _zz_112; - _zz_113[5] = _zz_112; - _zz_113[4] = _zz_112; - _zz_113[3] = _zz_112; - _zz_113[2] = _zz_112; - _zz_113[1] = _zz_112; - _zz_113[0] = _zz_112; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_114 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_114 = {_zz_111,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_114 = {_zz_113,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_114 = _zz_41; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_335; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_115[0] = execute_SRC1[31]; - _zz_115[1] = execute_SRC1[30]; - _zz_115[2] = execute_SRC1[29]; - _zz_115[3] = execute_SRC1[28]; - _zz_115[4] = execute_SRC1[27]; - _zz_115[5] = execute_SRC1[26]; - _zz_115[6] = execute_SRC1[25]; - _zz_115[7] = execute_SRC1[24]; - _zz_115[8] = execute_SRC1[23]; - _zz_115[9] = execute_SRC1[22]; - _zz_115[10] = execute_SRC1[21]; - _zz_115[11] = execute_SRC1[20]; - _zz_115[12] = execute_SRC1[19]; - _zz_115[13] = execute_SRC1[18]; - _zz_115[14] = execute_SRC1[17]; - _zz_115[15] = execute_SRC1[16]; - _zz_115[16] = execute_SRC1[15]; - _zz_115[17] = execute_SRC1[14]; - _zz_115[18] = execute_SRC1[13]; - _zz_115[19] = execute_SRC1[12]; - _zz_115[20] = execute_SRC1[11]; - _zz_115[21] = execute_SRC1[10]; - _zz_115[22] = execute_SRC1[9]; - _zz_115[23] = execute_SRC1[8]; - _zz_115[24] = execute_SRC1[7]; - _zz_115[25] = execute_SRC1[6]; - _zz_115[26] = execute_SRC1[5]; - _zz_115[27] = execute_SRC1[4]; - _zz_115[28] = execute_SRC1[3]; - _zz_115[29] = execute_SRC1[2]; - _zz_115[30] = execute_SRC1[1]; - _zz_115[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_115 : execute_SRC1); - always @ (*) begin - _zz_116[0] = memory_SHIFT_RIGHT[31]; - _zz_116[1] = memory_SHIFT_RIGHT[30]; - _zz_116[2] = memory_SHIFT_RIGHT[29]; - _zz_116[3] = memory_SHIFT_RIGHT[28]; - _zz_116[4] = memory_SHIFT_RIGHT[27]; - _zz_116[5] = memory_SHIFT_RIGHT[26]; - _zz_116[6] = memory_SHIFT_RIGHT[25]; - _zz_116[7] = memory_SHIFT_RIGHT[24]; - _zz_116[8] = memory_SHIFT_RIGHT[23]; - _zz_116[9] = memory_SHIFT_RIGHT[22]; - _zz_116[10] = memory_SHIFT_RIGHT[21]; - _zz_116[11] = memory_SHIFT_RIGHT[20]; - _zz_116[12] = memory_SHIFT_RIGHT[19]; - _zz_116[13] = memory_SHIFT_RIGHT[18]; - _zz_116[14] = memory_SHIFT_RIGHT[17]; - _zz_116[15] = memory_SHIFT_RIGHT[16]; - _zz_116[16] = memory_SHIFT_RIGHT[15]; - _zz_116[17] = memory_SHIFT_RIGHT[14]; - _zz_116[18] = memory_SHIFT_RIGHT[13]; - _zz_116[19] = memory_SHIFT_RIGHT[12]; - _zz_116[20] = memory_SHIFT_RIGHT[11]; - _zz_116[21] = memory_SHIFT_RIGHT[10]; - _zz_116[22] = memory_SHIFT_RIGHT[9]; - _zz_116[23] = memory_SHIFT_RIGHT[8]; - _zz_116[24] = memory_SHIFT_RIGHT[7]; - _zz_116[25] = memory_SHIFT_RIGHT[6]; - _zz_116[26] = memory_SHIFT_RIGHT[5]; - _zz_116[27] = memory_SHIFT_RIGHT[4]; - _zz_116[28] = memory_SHIFT_RIGHT[3]; - _zz_116[29] = memory_SHIFT_RIGHT[2]; - _zz_116[30] = memory_SHIFT_RIGHT[1]; - _zz_116[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_117 = 1'b0; - if(_zz_265)begin - if(_zz_266)begin - if(_zz_122)begin - _zz_117 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_267)begin - if(_zz_268)begin - if(_zz_124)begin - _zz_117 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_269)begin - if(_zz_270)begin - if(_zz_126)begin - _zz_117 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_117 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_118 = 1'b0; - if(_zz_265)begin - if(_zz_266)begin - if(_zz_123)begin - _zz_118 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_267)begin - if(_zz_268)begin - if(_zz_125)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_269)begin - if(_zz_270)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_118 = 1'b0; - end - end - - assign _zz_122 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_124 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_126 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_128 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_128 == 3'b000)) begin - _zz_129 = execute_BranchPlugin_eq; - end else if((_zz_128 == 3'b001)) begin - _zz_129 = (! execute_BranchPlugin_eq); - end else if((((_zz_128 & 3'b101) == 3'b101))) begin - _zz_129 = (! execute_SRC_LESS); - end else begin - _zz_129 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_130 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_130 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_130 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_130 = _zz_129; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_131 = _zz_342[11]; - always @ (*) begin - _zz_132[19] = _zz_131; - _zz_132[18] = _zz_131; - _zz_132[17] = _zz_131; - _zz_132[16] = _zz_131; - _zz_132[15] = _zz_131; - _zz_132[14] = _zz_131; - _zz_132[13] = _zz_131; - _zz_132[12] = _zz_131; - _zz_132[11] = _zz_131; - _zz_132[10] = _zz_131; - _zz_132[9] = _zz_131; - _zz_132[8] = _zz_131; - _zz_132[7] = _zz_131; - _zz_132[6] = _zz_131; - _zz_132[5] = _zz_131; - _zz_132[4] = _zz_131; - _zz_132[3] = _zz_131; - _zz_132[2] = _zz_131; - _zz_132[1] = _zz_131; - _zz_132[0] = _zz_131; - end - - assign _zz_133 = _zz_343[19]; - always @ (*) begin - _zz_134[10] = _zz_133; - _zz_134[9] = _zz_133; - _zz_134[8] = _zz_133; - _zz_134[7] = _zz_133; - _zz_134[6] = _zz_133; - _zz_134[5] = _zz_133; - _zz_134[4] = _zz_133; - _zz_134[3] = _zz_133; - _zz_134[2] = _zz_133; - _zz_134[1] = _zz_133; - _zz_134[0] = _zz_133; - end - - assign _zz_135 = _zz_344[11]; - always @ (*) begin - _zz_136[18] = _zz_135; - _zz_136[17] = _zz_135; - _zz_136[16] = _zz_135; - _zz_136[15] = _zz_135; - _zz_136[14] = _zz_135; - _zz_136[13] = _zz_135; - _zz_136[12] = _zz_135; - _zz_136[11] = _zz_135; - _zz_136[10] = _zz_135; - _zz_136[9] = _zz_135; - _zz_136[8] = _zz_135; - _zz_136[7] = _zz_135; - _zz_136[6] = _zz_135; - _zz_136[5] = _zz_135; - _zz_136[4] = _zz_135; - _zz_136[3] = _zz_135; - _zz_136[2] = _zz_135; - _zz_136[1] = _zz_135; - _zz_136[0] = _zz_135; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_137 = (_zz_345[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_137 = _zz_346[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_137 = _zz_347[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_137); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -4056,183 +4231,195 @@ module VexRiscv ( endcase end - assign _zz_138 = _zz_348[11]; - always @ (*) begin - _zz_139[19] = _zz_138; - _zz_139[18] = _zz_138; - _zz_139[17] = _zz_138; - _zz_139[16] = _zz_138; - _zz_139[15] = _zz_138; - _zz_139[14] = _zz_138; - _zz_139[13] = _zz_138; - _zz_139[12] = _zz_138; - _zz_139[11] = _zz_138; - _zz_139[10] = _zz_138; - _zz_139[9] = _zz_138; - _zz_139[8] = _zz_138; - _zz_139[7] = _zz_138; - _zz_139[6] = _zz_138; - _zz_139[5] = _zz_138; - _zz_139[4] = _zz_138; - _zz_139[3] = _zz_138; - _zz_139[2] = _zz_138; - _zz_139[1] = _zz_138; - _zz_139[0] = _zz_138; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_139,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_141,{{{_zz_577,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_143,{{{_zz_578,_zz_579},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_351}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_140 = _zz_349[19]; - always @ (*) begin - _zz_141[10] = _zz_140; - _zz_141[9] = _zz_140; - _zz_141[8] = _zz_140; - _zz_141[7] = _zz_140; - _zz_141[6] = _zz_140; - _zz_141[5] = _zz_140; - _zz_141[4] = _zz_140; - _zz_141[3] = _zz_140; - _zz_141[2] = _zz_140; - _zz_141[1] = _zz_140; - _zz_141[0] = _zz_140; - end - - assign _zz_142 = _zz_350[11]; - always @ (*) begin - _zz_143[18] = _zz_142; - _zz_143[17] = _zz_142; - _zz_143[16] = _zz_142; - _zz_143[15] = _zz_142; - _zz_143[14] = _zz_142; - _zz_143[13] = _zz_142; - _zz_143[12] = _zz_142; - _zz_143[11] = _zz_142; - _zz_143[10] = _zz_142; - _zz_143[9] = _zz_142; - _zz_143[8] = _zz_142; - _zz_143[7] = _zz_142; - _zz_143[6] = _zz_142; - _zz_143[5] = _zz_142; - _zz_143[4] = _zz_142; - _zz_143[3] = _zz_142; - _zz_143[2] = _zz_142; - _zz_143[1] = _zz_142; - _zz_143[0] = _zz_142; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; - always @ (*) begin + always @(*) begin BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); - if(1'b0)begin + if(when_BranchPlugin_l296) begin BranchPlugin_branchExceptionPort_valid = 1'b0; end end assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign when_BranchPlugin_l296 = 1'b0; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_144 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_145 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_146 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_147 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_148 = _zz_352[0]; - assign _zz_149 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_150 = _zz_354[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_258)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_260)begin + if(_zz_when_1) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4243,8 +4430,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4254,199 +4441,208 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_csr_2820) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2821) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_csr_2822) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2823) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_csr_2824) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2825) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_csr_2826) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2827) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_csr_2828) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2829) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_csr_2830) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2831) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_csr_2832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2833) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_2834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_2835) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_271)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_272)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_273)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_272)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_273)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4459,106 +4655,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_271)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_271)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_285) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); - assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_356; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; - assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_167 = _zz_357[7]; - always @ (*) begin - _zz_168[23] = _zz_167; - _zz_168[22] = _zz_167; - _zz_168[21] = _zz_167; - _zz_168[20] = _zz_167; - _zz_168[19] = _zz_167; - _zz_168[18] = _zz_167; - _zz_168[17] = _zz_167; - _zz_168[16] = _zz_167; - _zz_168[15] = _zz_167; - _zz_168[14] = _zz_167; - _zz_168[13] = _zz_167; - _zz_168[12] = _zz_167; - _zz_168[11] = _zz_167; - _zz_168[10] = _zz_167; - _zz_168[9] = _zz_167; - _zz_168[8] = _zz_167; - _zz_168[7] = _zz_167; - _zz_168[6] = _zz_167; - _zz_168[5] = _zz_167; - _zz_168[4] = _zz_167; - _zz_168[3] = _zz_167; - _zz_168[2] = _zz_167; - _zz_168[1] = _zz_167; - _zz_168[0] = _zz_167; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : begin - _zz_169 = execute_RS2; - end - default : begin - _zz_169 = {_zz_168,execute_INSTRUCTION[31 : 24]}; - end - endcase - end - - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_169; - assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); - assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); - assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); - assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); - always @ (*) begin - CfuPlugin_joinException_valid = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if(memory_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); - end - end - end - - assign CfuPlugin_joinException_payload_code = 4'b1111; - assign CfuPlugin_joinException_payload_badAddr = 32'h0; - always @ (*) begin - memory_CfuPlugin_rsp_ready = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); - end - end - assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_274) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4571,8 +4710,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_274) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4591,82 +4730,222 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_358) + $signed(_zz_359)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_253)begin - if(_zz_275)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_276)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_363); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_170 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_170[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_364); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_365 : _zz_366); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_367[31:0]; - assign _zz_171 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_172 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_173 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_174[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_174[31 : 0] = execute_RS1; - end - - assign _zz_176 = (_zz_175 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_176 != 32'h0); - assign _zz_29 = decode_SRC1_CTRL; - assign _zz_27 = _zz_56; - assign _zz_43 = decode_to_execute_SRC1_CTRL; - assign _zz_26 = decode_ALU_CTRL; - assign _zz_24 = _zz_55; - assign _zz_44 = decode_to_execute_ALU_CTRL; - assign _zz_23 = decode_SRC2_CTRL; - assign _zz_21 = _zz_54; - assign _zz_42 = decode_to_execute_SRC2_CTRL; - assign _zz_20 = decode_ALU_BITWISE_CTRL; - assign _zz_18 = _zz_53; - assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_17 = decode_SHIFT_CTRL; - assign _zz_14 = execute_SHIFT_CTRL; - assign _zz_15 = _zz_52; - assign _zz_40 = decode_to_execute_SHIFT_CTRL; - assign _zz_39 = execute_to_memory_SHIFT_CTRL; - assign _zz_12 = decode_BRANCH_CTRL; - assign _zz_58 = _zz_51; - assign _zz_36 = decode_to_execute_BRANCH_CTRL; - assign _zz_10 = decode_ENV_CTRL; - assign _zz_7 = execute_ENV_CTRL; - assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_50; - assign _zz_34 = decode_to_execute_ENV_CTRL; - assign _zz_33 = execute_to_memory_ENV_CTRL; - assign _zz_35 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_49; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready); + assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)); + assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + end + + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2; + end + default : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @(*) begin + CfuPlugin_bus_rsp_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); + assign when_GenCoreDefault_l367 = _zz_when_GenCoreDefault_l367[0]; + assign when_GenCoreDefault_l367_1 = _zz_when_GenCoreDefault_l367_1[0]; + assign when_GenCoreDefault_l367_2 = _zz_when_GenCoreDefault_l367_2[0]; + assign when_GenCoreDefault_l367_3 = _zz_when_GenCoreDefault_l367_3[0]; + assign when_GenCoreDefault_l367_4 = _zz_when_GenCoreDefault_l367_4[0]; + assign when_GenCoreDefault_l367_5 = _zz_when_GenCoreDefault_l367_5[0]; + assign when_GenCoreDefault_l367_6 = _zz_when_GenCoreDefault_l367_6[0]; + assign when_GenCoreDefault_l367_7 = _zz_when_GenCoreDefault_l367_7[0]; + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4687,296 +4966,345 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin - _zz_177 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_177[12 : 0] = 13'h1000; - _zz_177[25 : 20] = 6'h20; + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_28 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_29 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_30 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_31 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_32 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_33 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_34 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_35 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_36 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_37 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_38 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_39 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_10[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_178 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_178[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_179 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_179[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_180[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_181[31 : 30] = CsrPlugin_misa_base; - _zz_181[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_14[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_182[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_182[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_182[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_15[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_183[11 : 11] = CsrPlugin_mip_MEIP; - _zz_183[7 : 7] = CsrPlugin_mip_MTIP; - _zz_183[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_184[11 : 11] = CsrPlugin_mie_MEIE; - _zz_184[7 : 7] = CsrPlugin_mie_MTIE; - _zz_184[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_185[31 : 2] = CsrPlugin_mtvec_base; - _zz_185[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_186 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_186[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_187 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_187[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_188 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_188[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_188[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_21[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_189 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_189[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_190 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_190[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_191 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_191[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_192 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_192[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_193 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_193[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_194 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_195 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_195[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_28[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_196 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_196[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_29 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_29[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_197 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_197[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_30 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_30[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_198 = 32'h0; - if(execute_CsrPlugin_csr_2820)begin - _zz_198[31 : 0] = _zz_151; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_31 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_31[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_199 = 32'h0; - if(execute_CsrPlugin_csr_2822)begin - _zz_199[31 : 0] = _zz_153; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_32 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_32[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - always @ (*) begin - _zz_200 = 32'h0; - if(execute_CsrPlugin_csr_2824)begin - _zz_200[31 : 0] = _zz_155; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_33 = 32'h0; + if(execute_CsrPlugin_csr_2820) begin + _zz_CsrPlugin_csrMapping_readDataInit_33[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; end end - always @ (*) begin - _zz_201 = 32'h0; - if(execute_CsrPlugin_csr_2826)begin - _zz_201[31 : 0] = _zz_157; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_34 = 32'h0; + if(execute_CsrPlugin_csr_2822) begin + _zz_CsrPlugin_csrMapping_readDataInit_34[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; end end - always @ (*) begin - _zz_202 = 32'h0; - if(execute_CsrPlugin_csr_2828)begin - _zz_202[31 : 0] = _zz_159; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_35 = 32'h0; + if(execute_CsrPlugin_csr_2824) begin + _zz_CsrPlugin_csrMapping_readDataInit_35[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_4; end end - always @ (*) begin - _zz_203 = 32'h0; - if(execute_CsrPlugin_csr_2830)begin - _zz_203[31 : 0] = _zz_161; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_36 = 32'h0; + if(execute_CsrPlugin_csr_2826) begin + _zz_CsrPlugin_csrMapping_readDataInit_36[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_5; end end - always @ (*) begin - _zz_204 = 32'h0; - if(execute_CsrPlugin_csr_2832)begin - _zz_204[31 : 0] = _zz_163; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_37 = 32'h0; + if(execute_CsrPlugin_csr_2828) begin + _zz_CsrPlugin_csrMapping_readDataInit_37[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_6; end end - always @ (*) begin - _zz_205 = 32'h0; - if(execute_CsrPlugin_csr_2834)begin - _zz_205[31 : 0] = _zz_165; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_38 = 32'h0; + if(execute_CsrPlugin_csr_2830) begin + _zz_CsrPlugin_csrMapping_readDataInit_38[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_7; end end - always @ (*) begin - _zz_206 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_206[31 : 0] = _zz_175; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_39 = 32'h0; + if(execute_CsrPlugin_csr_2832) begin + _zz_CsrPlugin_csrMapping_readDataInit_39[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_8; end end - always @ (*) begin - _zz_207 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_207[31 : 0] = _zz_176; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_40 = 32'h0; + if(execute_CsrPlugin_csr_2834) begin + _zz_CsrPlugin_csrMapping_readDataInit_40[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_9; end end - assign execute_CsrPlugin_readData = (((((_zz_177 | _zz_178) | (_zz_179 | _zz_180)) | ((_zz_580 | _zz_181) | (_zz_182 | _zz_183))) | (((_zz_184 | _zz_185) | (_zz_186 | _zz_187)) | ((_zz_188 | _zz_189) | (_zz_190 | _zz_191)))) | ((((_zz_192 | _zz_193) | (_zz_194 | _zz_195)) | ((_zz_196 | _zz_197) | (_zz_198 | _zz_199))) | (((_zz_200 | _zz_201) | (_zz_202 | _zz_203)) | ((_zz_204 | _zz_205) | (_zz_206 | _zz_207))))); - assign iBusWishbone_ADR = {_zz_384,_zz_208}; - assign iBusWishbone_CTI = ((_zz_208 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | (_zz_CsrPlugin_csrMapping_readDataInit_12 | _zz_CsrPlugin_csrMapping_readDataInit_13)) | ((_zz_CsrPlugin_csrMapping_readDataInit_41 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26) | (_zz_CsrPlugin_csrMapping_readDataInit_27 | _zz_CsrPlugin_csrMapping_readDataInit_28)) | ((_zz_CsrPlugin_csrMapping_readDataInit_29 | _zz_CsrPlugin_csrMapping_readDataInit_30) | (_zz_CsrPlugin_csrMapping_readDataInit_31 | _zz_CsrPlugin_csrMapping_readDataInit_32))) | (((_zz_CsrPlugin_csrMapping_readDataInit_33 | _zz_CsrPlugin_csrMapping_readDataInit_34) | (_zz_CsrPlugin_csrMapping_readDataInit_35 | _zz_CsrPlugin_csrMapping_readDataInit_36)) | ((_zz_CsrPlugin_csrMapping_readDataInit_37 | _zz_CsrPlugin_csrMapping_readDataInit_38) | (_zz_CsrPlugin_csrMapping_readDataInit_39 | _zz_CsrPlugin_csrMapping_readDataInit_40))))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_277)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_277)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_209; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_215 = (dBus_cmd_payload_length != 3'b000); - assign _zz_211 = dBus_cmd_valid; - assign _zz_213 = dBus_cmd_payload_wr; - assign _zz_214 = (_zz_210 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_212 && (_zz_213 || _zz_214)); - assign dBusWishbone_ADR = ((_zz_215 ? {{dBus_cmd_payload_address[31 : 5],_zz_210},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_215 ? (_zz_214 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_213 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_213; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_212 = (_zz_211 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_211; - assign dBusWishbone_STB = _zz_211; - assign dBus_rsp_valid = _zz_216; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_71 <= 1'b0; - _zz_73 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_86; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_87; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_107 <= 1'b1; - _zz_119 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -4996,164 +5324,164 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - memory_DivPlugin_div_counter_value <= 6'h0; - _zz_175 <= 32'h0; + CfuPlugin_bus_rsp_rValid <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_208 <= 3'b000; - _zz_209 <= 1'b0; - _zz_210 <= 3'b000; - _zz_216 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_71 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_69)begin - _zz_71 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_73 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_73 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_278)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_107 <= 1'b0; - _zz_119 <= (_zz_47 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_279)begin - if(_zz_280)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_281)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_282)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5164,8 +5492,8 @@ module VexRiscv ( end endcase end - if(_zz_262)begin - case(_zz_263) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5175,162 +5503,158 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_146,{_zz_145,_zz_144}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(execute_CfuPlugin_schedule)begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(execute_CfuPlugin_schedule) begin execute_CfuPlugin_hold <= 1'b1; end - if(CfuPlugin_bus_cmd_ready)begin + if(CfuPlugin_bus_cmd_ready) begin execute_CfuPlugin_hold <= 1'b0; end - if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + if(CfuPlugin_bus_cmd_fire) begin execute_CfuPlugin_fired <= 1'b1; end - if((! execute_arbitration_isStuckByOthers))begin + if(when_CfuPlugin_l171) begin execute_CfuPlugin_fired <= 1'b0; end - if(memory_CfuPlugin_rsp_ready)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + if(CfuPlugin_bus_rsp_valid) begin + CfuPlugin_bus_rsp_rValid <= 1'b1; end - if(_zz_283)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + if(CfuPlugin_bus_rsp_rsp_ready) begin + CfuPlugin_bus_rsp_rValid <= 1'b0; end - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + if(when_Pipeline_l124_61) begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_377[0]; - CsrPlugin_mstatus_MIE <= _zz_378[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_380[0]; - CsrPlugin_mie_MTIE <= _zz_381[0]; - CsrPlugin_mie_MSIE <= _zz_382[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_175 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_277)begin - if(iBusWishbone_ACK)begin - _zz_208 <= (_zz_208 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_209 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_211 && _zz_212))begin - _zz_210 <= (_zz_210 + 3'b001); - if(_zz_214)begin - _zz_210 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_216 <= ((_zz_211 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_74 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_278)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_120 <= _zz_46[11 : 7]; - _zz_121 <= _zz_57; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_258)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_148 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(_zz_260)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_150 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_when_1) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; - end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_279)begin - if(_zz_280)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_281)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_282)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_261)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5338,495 +5662,494 @@ module VexRiscv ( end endcase end - if(_zz_152[0])begin - _zz_151 <= (_zz_151 + 32'h00000001); + if(when_MulDivIterativePlugin_l126) begin + memory_DivPlugin_div_done <= 1'b1; end - if(_zz_154[0])begin - _zz_153 <= (_zz_153 + 32'h00000001); + if(when_MulDivIterativePlugin_l126_1) begin + memory_DivPlugin_div_done <= 1'b0; end - if(_zz_156[0])begin - _zz_155 <= (_zz_155 + 32'h00000001); + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; + end + end end - if(_zz_158[0])begin - _zz_157 <= (_zz_157 + 32'h00000001); + if(when_MulDivIterativePlugin_l162) begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end - if(_zz_160[0])begin - _zz_159 <= (_zz_159 + 32'h00000001); + externalInterruptArray_regNext <= externalInterruptArray; + if(CfuPlugin_bus_rsp_ready) begin + CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end - if(_zz_162[0])begin - _zz_161 <= (_zz_161 + 32'h00000001); + if(when_GenCoreDefault_l367) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= (_zz_CsrPlugin_csrMapping_readDataInit_2 + 32'h00000001); end - if(_zz_164[0])begin - _zz_163 <= (_zz_163 + 32'h00000001); + if(when_GenCoreDefault_l367_1) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= (_zz_CsrPlugin_csrMapping_readDataInit_3 + 32'h00000001); end - if(_zz_166[0])begin - _zz_165 <= (_zz_165 + 32'h00000001); + if(when_GenCoreDefault_l367_2) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= (_zz_CsrPlugin_csrMapping_readDataInit_4 + 32'h00000001); end - if(_zz_283)begin - CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + if(when_GenCoreDefault_l367_3) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= (_zz_CsrPlugin_csrMapping_readDataInit_5 + 32'h00000001); end - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_done <= 1'b1; + if(when_GenCoreDefault_l367_4) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= (_zz_CsrPlugin_csrMapping_readDataInit_6 + 32'h00000001); end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + if(when_GenCoreDefault_l367_5) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= (_zz_CsrPlugin_csrMapping_readDataInit_7 + 32'h00000001); end - if(_zz_253)begin - if(_zz_275)begin - memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; - memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_368[31:0]; - end - end + if(when_GenCoreDefault_l367_6) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= (_zz_CsrPlugin_csrMapping_readDataInit_8 + 32'h00000001); end - if(_zz_276)begin - memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_173 ? (~ _zz_174) : _zz_174) + _zz_374); - memory_DivPlugin_rs2 <= ((_zz_172 ? (~ execute_RS2) : execute_RS2) + _zz_376); - memory_DivPlugin_div_needRevert <= ((_zz_173 ^ (_zz_172 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(when_GenCoreDefault_l367_7) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= (_zz_CsrPlugin_csrMapping_readDataInit_9 + 32'h00000001); end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_41; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_8) begin memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_28; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_25; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_22; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_16; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_11; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9; - end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; - end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + end + if(when_Pipeline_l124_45) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_51) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_52) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + if(when_Pipeline_l124_53) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + if(when_Pipeline_l124_54) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_55) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_62) begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + end + if(when_Pipeline_l124_63) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if(when_CsrPlugin_l1264_23) begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(when_CsrPlugin_l1264_24) begin execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_25) begin execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_26) begin execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_27) begin execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_28) begin execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_29) begin execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_30) begin execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_31) begin execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_32) begin execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_33) begin execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_34) begin execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_35) begin execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_36) begin execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_37) begin execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_38) begin execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_39) begin execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); - end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_379[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_383[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2820)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_151 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2820) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2821) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2822)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2822) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2823) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_1 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2824)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2824) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2825) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2826)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2826) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2827) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2828)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2828) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2829) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2830)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2830) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2831) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2832)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2832) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2833) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2834)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2834) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2835) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; @@ -5839,9 +6162,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -5863,6 +6185,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -5878,9 +6201,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -5888,7 +6212,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -5897,24 +6221,15 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -5939,40 +6254,48 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -5982,23 +6305,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -6006,10 +6339,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -6021,59 +6362,54 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -6088,274 +6424,293 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -6363,89 +6718,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_16)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6453,12 +6792,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6469,20 +6808,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6490,45 +6849,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6539,46 +6900,37 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; @@ -6586,50 +6938,51 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6679,13 +7032,9 @@ module InstructionCache ( input clk, input reset ); - reg [31:0] _zz_9; - reg [22:0] _zz_10; - wire _zz_11; - wire _zz_12; - wire [0:0] _zz_13; - wire [0:0] _zz_14; - wire [22:0] _zz_15; + reg [31:0] _zz_banks_0_port1; + reg [22:0] _zz_ways_0_tags_port1; + wire [22:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6694,8 +7043,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [6:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -6709,22 +7063,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [8:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_6; - wire _zz_7; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8; + wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -6734,82 +7091,85 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_11 = (! lineLoader_flushCounter[6]); - assign _zz_12 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_13 = _zz_8[0 : 0]; - assign _zz_14 = _zz_8[1 : 1]; - assign _zz_15 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_9 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_15; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_10 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_11)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -6825,30 +7185,35 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_9; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_10; - assign fetchStage_read_waysValues_0_tag_valid = _zz_13[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_14[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -6856,51 +7221,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_12)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_11)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[6]; - if(_zz_12)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 7'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -6911,10 +7276,10 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.v index 81f1a5b..1f7837a 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_SlimPerfCfuDebug.v @@ -1,66 +1,57 @@ -// Generator : SpinalHDL v1.4.3 git head : adf552d8f500e7419fff395b7049228e4bc5de26 +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : cbb04d34fec970ebb660147932da0bb4bb5adce0 - - -`define Input2Kind_defaultEncoding_type [0:0] -`define Input2Kind_defaultEncoding_RS 1'b0 -`define Input2Kind_defaultEncoding_IMM_I 1'b1 - -`define EnvCtrlEnum_defaultEncoding_type [1:0] -`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 -`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 -`define EnvCtrlEnum_defaultEncoding_WFI 2'b10 -`define EnvCtrlEnum_defaultEncoding_ECALL 2'b11 - -`define BranchCtrlEnum_defaultEncoding_type [1:0] -`define BranchCtrlEnum_defaultEncoding_INC 2'b00 -`define BranchCtrlEnum_defaultEncoding_B 2'b01 -`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 -`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 - -`define ShiftCtrlEnum_defaultEncoding_type [1:0] -`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 -`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 -`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 -`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 - -`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] -`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 -`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 -`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 - -`define Src2CtrlEnum_defaultEncoding_type [1:0] -`define Src2CtrlEnum_defaultEncoding_RS 2'b00 -`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 -`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 -`define Src2CtrlEnum_defaultEncoding_PC 2'b11 - -`define AluCtrlEnum_defaultEncoding_type [1:0] -`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 -`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 -`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 - -`define Src1CtrlEnum_defaultEncoding_type [1:0] -`define Src1CtrlEnum_defaultEncoding_RS 2'b00 -`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 -`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 -`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 +// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a + + +`define Input2Kind_binary_sequential_type [0:0] +`define Input2Kind_binary_sequential_RS 1'b0 +`define Input2Kind_binary_sequential_IMM_I 1'b1 + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 module VexRiscv ( input [31:0] externalResetVector, input timerInterrupt, input softwareInterrupt, - output CfuPlugin_bus_cmd_valid, - input CfuPlugin_bus_cmd_ready, - output [9:0] CfuPlugin_bus_cmd_payload_function_id, - output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, - output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, - input CfuPlugin_bus_rsp_valid, - output CfuPlugin_bus_rsp_ready, - input CfuPlugin_bus_rsp_payload_response_ok, - input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, input [31:0] externalInterruptArray, input debug_bus_cmd_valid, output reg debug_bus_cmd_ready, @@ -69,6 +60,14 @@ module VexRiscv ( input [31:0] debug_bus_cmd_payload_data, output reg [31:0] debug_bus_rsp_data, output debug_resetOut, + output CfuPlugin_bus_cmd_valid, + input CfuPlugin_bus_cmd_ready, + output [9:0] CfuPlugin_bus_cmd_payload_function_id, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_0, + output [31:0] CfuPlugin_bus_cmd_payload_inputs_1, + input CfuPlugin_bus_rsp_valid, + output CfuPlugin_bus_rsp_ready, + input [31:0] CfuPlugin_bus_rsp_payload_outputs_0, output reg iBusWishbone_CYC, output reg iBusWishbone_STB, input iBusWishbone_ACK, @@ -95,37 +94,37 @@ module VexRiscv ( input reset, input debugReset ); - wire _zz_220; - wire _zz_221; - wire _zz_222; - wire _zz_223; - wire _zz_224; - wire _zz_225; - wire _zz_226; - wire _zz_227; - reg _zz_228; - wire _zz_229; - wire [31:0] _zz_230; - wire _zz_231; - wire [31:0] _zz_232; - reg _zz_233; - wire _zz_234; - wire _zz_235; - wire [31:0] _zz_236; - wire _zz_237; - wire _zz_238; - wire _zz_239; - wire _zz_240; - wire _zz_241; - wire _zz_242; - wire _zz_243; - wire _zz_244; - wire [3:0] _zz_245; - wire _zz_246; - wire _zz_247; - reg [31:0] _zz_248; - reg [31:0] _zz_249; - reg [31:0] _zz_250; + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; @@ -148,6 +147,7 @@ module VexRiscv ( wire dataCache_1_io_cpu_writeBack_accessError; wire dataCache_1_io_cpu_writeBack_isWrite; wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; wire dataCache_1_io_cpu_flush_ready; wire dataCache_1_io_cpu_redo; wire dataCache_1_io_mem_cmd_valid; @@ -156,404 +156,332 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_payload_address; wire [31:0] dataCache_1_io_mem_cmd_payload_data; wire [3:0] dataCache_1_io_mem_cmd_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; wire dataCache_1_io_mem_cmd_payload_last; - wire _zz_251; - wire _zz_252; - wire _zz_253; - wire _zz_254; - wire _zz_255; - wire _zz_256; - wire _zz_257; - wire _zz_258; - wire _zz_259; - wire _zz_260; - wire _zz_261; - wire _zz_262; - wire _zz_263; - wire _zz_264; - wire _zz_265; - wire _zz_266; - wire _zz_267; - wire _zz_268; - wire [1:0] _zz_269; - wire _zz_270; - wire _zz_271; - wire _zz_272; - wire _zz_273; - wire _zz_274; - wire _zz_275; - wire _zz_276; - wire _zz_277; - wire _zz_278; - wire _zz_279; - wire [1:0] _zz_280; - wire _zz_281; - wire _zz_282; - wire [5:0] _zz_283; - wire _zz_284; - wire _zz_285; - wire _zz_286; - wire _zz_287; - wire _zz_288; - wire _zz_289; - wire _zz_290; - wire [1:0] _zz_291; - wire _zz_292; - wire [1:0] _zz_293; - wire [51:0] _zz_294; - wire [51:0] _zz_295; - wire [51:0] _zz_296; - wire [32:0] _zz_297; - wire [51:0] _zz_298; - wire [49:0] _zz_299; - wire [51:0] _zz_300; - wire [49:0] _zz_301; - wire [51:0] _zz_302; - wire [32:0] _zz_303; - wire [31:0] _zz_304; - wire [32:0] _zz_305; - wire [0:0] _zz_306; - wire [0:0] _zz_307; - wire [0:0] _zz_308; - wire [0:0] _zz_309; - wire [0:0] _zz_310; - wire [0:0] _zz_311; - wire [0:0] _zz_312; - wire [0:0] _zz_313; - wire [0:0] _zz_314; - wire [0:0] _zz_315; - wire [0:0] _zz_316; - wire [0:0] _zz_317; - wire [0:0] _zz_318; - wire [0:0] _zz_319; - wire [0:0] _zz_320; - wire [0:0] _zz_321; - wire [0:0] _zz_322; - wire [0:0] _zz_323; - wire [0:0] _zz_324; - wire [3:0] _zz_325; - wire [2:0] _zz_326; - wire [31:0] _zz_327; - wire [11:0] _zz_328; - wire [31:0] _zz_329; - wire [19:0] _zz_330; - wire [11:0] _zz_331; - wire [31:0] _zz_332; - wire [31:0] _zz_333; - wire [19:0] _zz_334; - wire [11:0] _zz_335; - wire [2:0] _zz_336; - wire [2:0] _zz_337; - wire [0:0] _zz_338; - wire [2:0] _zz_339; - wire [4:0] _zz_340; - wire [11:0] _zz_341; - wire [11:0] _zz_342; - wire [31:0] _zz_343; - wire [31:0] _zz_344; - wire [31:0] _zz_345; - wire [31:0] _zz_346; - wire [31:0] _zz_347; - wire [31:0] _zz_348; - wire [31:0] _zz_349; - wire [11:0] _zz_350; - wire [19:0] _zz_351; - wire [11:0] _zz_352; - wire [31:0] _zz_353; - wire [31:0] _zz_354; - wire [31:0] _zz_355; - wire [11:0] _zz_356; - wire [19:0] _zz_357; - wire [11:0] _zz_358; - wire [2:0] _zz_359; - wire [1:0] _zz_360; - wire [1:0] _zz_361; - wire [1:0] _zz_362; - wire [1:0] _zz_363; - wire [9:0] _zz_364; - wire [7:0] _zz_365; - wire [65:0] _zz_366; - wire [65:0] _zz_367; - wire [31:0] _zz_368; - wire [31:0] _zz_369; - wire [0:0] _zz_370; - wire [5:0] _zz_371; - wire [32:0] _zz_372; - wire [31:0] _zz_373; - wire [31:0] _zz_374; - wire [32:0] _zz_375; - wire [32:0] _zz_376; - wire [32:0] _zz_377; - wire [32:0] _zz_378; - wire [0:0] _zz_379; - wire [32:0] _zz_380; - wire [0:0] _zz_381; - wire [32:0] _zz_382; - wire [0:0] _zz_383; - wire [31:0] _zz_384; - wire [0:0] _zz_385; - wire [0:0] _zz_386; - wire [0:0] _zz_387; - wire [0:0] _zz_388; - wire [0:0] _zz_389; - wire [0:0] _zz_390; - wire [0:0] _zz_391; - wire [26:0] _zz_392; - wire _zz_393; - wire _zz_394; - wire [1:0] _zz_395; - wire [31:0] _zz_396; - wire [31:0] _zz_397; - wire [31:0] _zz_398; - wire _zz_399; - wire [0:0] _zz_400; - wire [14:0] _zz_401; - wire [31:0] _zz_402; - wire [31:0] _zz_403; - wire [31:0] _zz_404; - wire _zz_405; - wire [0:0] _zz_406; - wire [8:0] _zz_407; - wire [31:0] _zz_408; - wire [31:0] _zz_409; - wire [31:0] _zz_410; - wire _zz_411; - wire [0:0] _zz_412; - wire [2:0] _zz_413; - wire _zz_414; - wire _zz_415; - wire _zz_416; - wire [31:0] _zz_417; - wire [0:0] _zz_418; - wire [0:0] _zz_419; - wire _zz_420; - wire [0:0] _zz_421; - wire [28:0] _zz_422; - wire [0:0] _zz_423; - wire [0:0] _zz_424; - wire [0:0] _zz_425; - wire [0:0] _zz_426; - wire _zz_427; - wire [0:0] _zz_428; - wire [23:0] _zz_429; - wire [31:0] _zz_430; - wire [31:0] _zz_431; - wire [31:0] _zz_432; - wire _zz_433; - wire _zz_434; - wire [0:0] _zz_435; - wire [0:0] _zz_436; - wire [0:0] _zz_437; - wire [0:0] _zz_438; - wire _zz_439; - wire [0:0] _zz_440; - wire [20:0] _zz_441; - wire [31:0] _zz_442; - wire [31:0] _zz_443; - wire _zz_444; - wire _zz_445; - wire [0:0] _zz_446; - wire [1:0] _zz_447; - wire [0:0] _zz_448; - wire [0:0] _zz_449; - wire _zz_450; - wire [0:0] _zz_451; - wire [17:0] _zz_452; - wire [31:0] _zz_453; - wire [31:0] _zz_454; - wire [31:0] _zz_455; - wire [31:0] _zz_456; - wire [31:0] _zz_457; - wire [31:0] _zz_458; - wire [31:0] _zz_459; - wire [31:0] _zz_460; - wire _zz_461; - wire [1:0] _zz_462; - wire [1:0] _zz_463; - wire _zz_464; - wire [0:0] _zz_465; - wire [14:0] _zz_466; - wire [31:0] _zz_467; - wire [31:0] _zz_468; - wire [31:0] _zz_469; - wire [31:0] _zz_470; - wire [31:0] _zz_471; - wire [31:0] _zz_472; - wire [0:0] _zz_473; - wire [1:0] _zz_474; - wire [4:0] _zz_475; - wire [4:0] _zz_476; - wire _zz_477; - wire [0:0] _zz_478; - wire [11:0] _zz_479; - wire [31:0] _zz_480; - wire [31:0] _zz_481; - wire [31:0] _zz_482; - wire [31:0] _zz_483; - wire [31:0] _zz_484; - wire [31:0] _zz_485; - wire _zz_486; - wire [0:0] _zz_487; - wire [1:0] _zz_488; - wire [31:0] _zz_489; - wire [31:0] _zz_490; - wire [0:0] _zz_491; - wire [4:0] _zz_492; - wire [4:0] _zz_493; - wire [4:0] _zz_494; - wire _zz_495; - wire [0:0] _zz_496; - wire [8:0] _zz_497; - wire [31:0] _zz_498; - wire [31:0] _zz_499; - wire [31:0] _zz_500; - wire _zz_501; - wire _zz_502; - wire [31:0] _zz_503; - wire [31:0] _zz_504; - wire _zz_505; - wire [0:0] _zz_506; - wire [2:0] _zz_507; - wire [0:0] _zz_508; - wire [2:0] _zz_509; - wire [0:0] _zz_510; - wire [4:0] _zz_511; - wire [1:0] _zz_512; - wire [1:0] _zz_513; - wire _zz_514; - wire [0:0] _zz_515; - wire [6:0] _zz_516; - wire [31:0] _zz_517; - wire [31:0] _zz_518; - wire [31:0] _zz_519; - wire _zz_520; - wire [0:0] _zz_521; - wire [0:0] _zz_522; - wire [31:0] _zz_523; - wire [31:0] _zz_524; - wire _zz_525; - wire [0:0] _zz_526; - wire [0:0] _zz_527; - wire _zz_528; - wire [0:0] _zz_529; - wire [2:0] _zz_530; - wire _zz_531; - wire [0:0] _zz_532; - wire [0:0] _zz_533; - wire [0:0] _zz_534; - wire [0:0] _zz_535; - wire _zz_536; - wire [0:0] _zz_537; - wire [4:0] _zz_538; - wire [31:0] _zz_539; - wire [31:0] _zz_540; - wire [31:0] _zz_541; - wire [31:0] _zz_542; - wire [31:0] _zz_543; - wire [31:0] _zz_544; - wire [31:0] _zz_545; - wire [31:0] _zz_546; - wire [31:0] _zz_547; - wire [31:0] _zz_548; - wire [31:0] _zz_549; - wire [31:0] _zz_550; - wire [31:0] _zz_551; - wire _zz_552; - wire [0:0] _zz_553; - wire [0:0] _zz_554; - wire [31:0] _zz_555; - wire [31:0] _zz_556; - wire [31:0] _zz_557; - wire [31:0] _zz_558; - wire [31:0] _zz_559; - wire _zz_560; - wire [3:0] _zz_561; - wire [3:0] _zz_562; - wire _zz_563; - wire [0:0] _zz_564; - wire [2:0] _zz_565; - wire [31:0] _zz_566; - wire [31:0] _zz_567; - wire [31:0] _zz_568; - wire [31:0] _zz_569; - wire [31:0] _zz_570; - wire [31:0] _zz_571; - wire _zz_572; - wire [0:0] _zz_573; - wire [1:0] _zz_574; - wire _zz_575; - wire [2:0] _zz_576; - wire [2:0] _zz_577; - wire _zz_578; - wire [0:0] _zz_579; - wire [0:0] _zz_580; - wire [31:0] _zz_581; - wire [31:0] _zz_582; - wire [31:0] _zz_583; - wire [31:0] _zz_584; - wire [31:0] _zz_585; - wire [31:0] _zz_586; - wire [31:0] _zz_587; - wire _zz_588; - wire _zz_589; - wire _zz_590; - wire [0:0] _zz_591; - wire [0:0] _zz_592; - wire _zz_593; - wire _zz_594; - wire _zz_595; - wire _zz_596; - wire [31:0] _zz_597; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [14:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [8:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [2:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6; + wire [27:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20; + wire [22:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35; + wire [19:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47; + wire [16:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70; + wire [13:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102; + wire [10:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127; + wire [7:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136; + wire [5:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140; + wire [2:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149; + wire [3:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151; + wire _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164; + wire [1:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166; + wire [31:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167; + wire [0:0] _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1; + wire _zz_when; + wire _zz_when_1; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_41; + wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; + wire writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [33:0] memory_MUL_HH; wire [33:0] execute_MUL_HH; wire [33:0] execute_MUL_HL; wire [33:0] execute_MUL_LH; wire [31:0] execute_MUL_LL; - wire writeBack_CfuPlugin_CFU_IN_FLIGHT; - wire execute_CfuPlugin_CFU_IN_FLIGHT; wire [31:0] execute_SHIFT_RIGHT; wire [31:0] execute_REGFILE_WRITE_DATA; - wire [1:0] memory_MEMORY_ADDRESS_LOW; - wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; wire decode_DO_EBREAK; wire decode_CSR_READ_OPCODE; wire decode_CSR_WRITE_OPCODE; wire decode_PREDICTION_HAD_BRANCHED2; wire decode_SRC2_FORCE_ZERO; + wire `Input2Kind_binary_sequential_type decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + wire decode_CfuPlugin_CFU_ENABLE; wire decode_IS_RS2_SIGNED; wire decode_IS_RS1_SIGNED; wire decode_IS_DIV; wire memory_IS_MUL; wire execute_IS_MUL; wire decode_IS_MUL; - wire `Input2Kind_defaultEncoding_type decode_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_1; - wire `Input2Kind_defaultEncoding_type _zz_2; - wire `Input2Kind_defaultEncoding_type _zz_3; - wire decode_CfuPlugin_CFU_ENABLE; - wire `EnvCtrlEnum_defaultEncoding_type _zz_4; - wire `EnvCtrlEnum_defaultEncoding_type _zz_5; - wire `EnvCtrlEnum_defaultEncoding_type _zz_6; - wire `EnvCtrlEnum_defaultEncoding_type _zz_7; - wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_8; - wire `EnvCtrlEnum_defaultEncoding_type _zz_9; - wire `EnvCtrlEnum_defaultEncoding_type _zz_10; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; wire decode_IS_CSR; - wire `BranchCtrlEnum_defaultEncoding_type _zz_11; - wire `BranchCtrlEnum_defaultEncoding_type _zz_12; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_13; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_14; - wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_15; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_16; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_17; - wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_18; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; wire decode_SRC_LESS_UNSIGNED; wire decode_MEMORY_MANAGMENT; wire memory_MEMORY_WR; @@ -561,24 +489,30 @@ module VexRiscv ( wire execute_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_MEMORY_STAGE; wire decode_BYPASSABLE_EXECUTE_STAGE; - wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_21; - wire `Src2CtrlEnum_defaultEncoding_type _zz_22; - wire `Src2CtrlEnum_defaultEncoding_type _zz_23; - wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_24; - wire `AluCtrlEnum_defaultEncoding_type _zz_25; - wire `AluCtrlEnum_defaultEncoding_type _zz_26; - wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_27; - wire `Src1CtrlEnum_defaultEncoding_type _zz_28; - wire `Src1CtrlEnum_defaultEncoding_type _zz_29; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; wire decode_MEMORY_FORCE_CONSTISTENCY; wire [31:0] writeBack_FORMAL_PC_NEXT; wire [31:0] memory_FORMAL_PC_NEXT; wire [31:0] execute_FORMAL_PC_NEXT; wire [31:0] decode_FORMAL_PC_NEXT; wire [31:0] memory_PC; + reg _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + reg _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire memory_CfuPlugin_CFU_IN_FLIGHT; + wire `Input2Kind_binary_sequential_type execute_CfuPlugin_CFU_INPUT_2_KIND; + wire `Input2Kind_binary_sequential_type _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire execute_CfuPlugin_CFU_ENABLE; wire execute_DO_EBREAK; wire decode_IS_EBREAK; wire execute_IS_RS1_SIGNED; @@ -591,32 +525,26 @@ module VexRiscv ( wire [33:0] memory_MUL_HL; wire [33:0] memory_MUL_LH; wire [31:0] memory_MUL_LL; - reg _zz_30; - reg _zz_31; - wire memory_CfuPlugin_CFU_IN_FLIGHT; - wire `Input2Kind_defaultEncoding_type execute_CfuPlugin_CFU_INPUT_2_KIND; - wire `Input2Kind_defaultEncoding_type _zz_32; - wire execute_CfuPlugin_CFU_ENABLE; wire execute_CSR_READ_OPCODE; wire execute_CSR_WRITE_OPCODE; wire execute_IS_CSR; - wire `EnvCtrlEnum_defaultEncoding_type memory_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_33; - wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_34; - wire `EnvCtrlEnum_defaultEncoding_type writeBack_ENV_CTRL; - wire `EnvCtrlEnum_defaultEncoding_type _zz_35; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; wire [31:0] execute_BRANCH_CALC; wire execute_BRANCH_DO; wire [31:0] execute_PC; wire execute_PREDICTION_HAD_BRANCHED2; (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; wire execute_BRANCH_COND_RESULT; - wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_36; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; wire decode_RS2_USE; wire decode_RS1_USE; - reg [31:0] _zz_37; + reg [31:0] _zz_decode_RS2; wire execute_REGFILE_WRITE_VALID; wire execute_BYPASSABLE_EXECUTE_STAGE; wire memory_REGFILE_WRITE_VALID; @@ -626,46 +554,46 @@ module VexRiscv ( reg [31:0] decode_RS2; reg [31:0] decode_RS1; wire [31:0] memory_SHIFT_RIGHT; - reg [31:0] _zz_38; - wire `ShiftCtrlEnum_defaultEncoding_type memory_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_39; - wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_40; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; wire execute_SRC_LESS_UNSIGNED; wire execute_SRC2_FORCE_ZERO; wire execute_SRC_USE_SUB_LESS; - wire [31:0] _zz_41; - wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; - wire `Src2CtrlEnum_defaultEncoding_type _zz_42; - wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; - wire `Src1CtrlEnum_defaultEncoding_type _zz_43; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; wire decode_SRC_USE_SUB_LESS; wire decode_SRC_ADD_ZERO; wire [31:0] execute_SRC_ADD_SUB; wire execute_SRC_LESS; - wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; - wire `AluCtrlEnum_defaultEncoding_type _zz_44; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; wire [31:0] execute_SRC2; wire [31:0] execute_SRC1; - wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45; - wire [31:0] _zz_46; - wire _zz_47; - reg _zz_48; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; wire [31:0] decode_INSTRUCTION_ANTICIPATED; reg decode_REGFILE_WRITE_VALID; wire decode_LEGAL_INSTRUCTION; - wire `Input2Kind_defaultEncoding_type _zz_49; - wire `EnvCtrlEnum_defaultEncoding_type _zz_50; - wire `BranchCtrlEnum_defaultEncoding_type _zz_51; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_52; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_53; - wire `Src2CtrlEnum_defaultEncoding_type _zz_54; - wire `AluCtrlEnum_defaultEncoding_type _zz_55; - wire `Src1CtrlEnum_defaultEncoding_type _zz_56; - reg [31:0] _zz_57; - wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; wire [31:0] writeBack_REGFILE_WRITE_DATA; wire writeBack_MEMORY_ENABLE; wire [31:0] memory_REGFILE_WRITE_DATA; @@ -683,11 +611,11 @@ module VexRiscv ( reg IBusCachedPlugin_rsp_issueDetected_3; reg IBusCachedPlugin_rsp_issueDetected_2; reg IBusCachedPlugin_rsp_issueDetected_1; - wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; - wire `BranchCtrlEnum_defaultEncoding_type _zz_58; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; wire [31:0] decode_INSTRUCTION; - reg [31:0] _zz_59; - reg [31:0] _zz_60; + reg [31:0] _zz_execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; wire [31:0] decode_PC; wire [31:0] writeBack_PC; wire [31:0] writeBack_INSTRUCTION; @@ -717,7 +645,7 @@ module VexRiscv ( wire memory_arbitration_haltByOther; reg memory_arbitration_removeIt; wire memory_arbitration_flushIt; - reg memory_arbitration_flushNext; + wire memory_arbitration_flushNext; reg memory_arbitration_isValid; wire memory_arbitration_isStuck; wire memory_arbitration_isStuckByOthers; @@ -774,7 +702,7 @@ module VexRiscv ( wire [31:0] dBus_cmd_payload_address; wire [31:0] dBus_cmd_payload_data; wire [3:0] dBus_cmd_payload_mask; - wire [2:0] dBus_cmd_payload_length; + wire [2:0] dBus_cmd_payload_size; wire dBus_cmd_payload_last; wire dBus_rsp_valid; wire dBus_rsp_payload_last; @@ -800,7 +728,7 @@ module VexRiscv ( reg DBusCachedPlugin_exceptionBus_valid; reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; - reg _zz_61; + reg _zz_when_DBusCachedPlugin_l386; wire decodeExceptionPort_valid; wire [3:0] decodeExceptionPort_payload_code; wire [31:0] decodeExceptionPort_payload_badAddr; @@ -809,6 +737,11 @@ module VexRiscv ( reg BranchPlugin_branchExceptionPort_valid; wire [3:0] BranchPlugin_branchExceptionPort_payload_code; wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; reg CsrPlugin_inWfi /* verilator public */ ; reg CsrPlugin_thirdPartyWake; reg CsrPlugin_jumpInterface_valid; @@ -826,34 +759,37 @@ module VexRiscv ( wire [31:0] CsrPlugin_selfException_payload_badAddr; reg CsrPlugin_allowInterrupts; reg CsrPlugin_allowException; - reg CfuPlugin_joinException_valid; - wire [3:0] CfuPlugin_joinException_payload_code; - wire [31:0] CfuPlugin_joinException_payload_badAddr; + reg CsrPlugin_allowEbreakException; reg IBusCachedPlugin_injectionPort_valid; reg IBusCachedPlugin_injectionPort_ready; wire [31:0] IBusCachedPlugin_injectionPort_payload; wire IBusCachedPlugin_externalFlush; wire IBusCachedPlugin_jump_pcLoad_valid; wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; - wire [3:0] _zz_62; - wire [3:0] _zz_63; - wire _zz_64; - wire _zz_65; - wire _zz_66; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; wire IBusCachedPlugin_fetchPc_output_valid; wire IBusCachedPlugin_fetchPc_output_ready; wire [31:0] IBusCachedPlugin_fetchPc_output_payload; reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; reg IBusCachedPlugin_fetchPc_correction; reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; wire IBusCachedPlugin_fetchPc_corrected; reg IBusCachedPlugin_fetchPc_pcRegPropagate; reg IBusCachedPlugin_fetchPc_booted; reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; reg [31:0] IBusCachedPlugin_fetchPc_pc; wire IBusCachedPlugin_fetchPc_redo_valid; wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; reg IBusCachedPlugin_iBusRsp_redoFetch; wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; @@ -876,16 +812,18 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; reg IBusCachedPlugin_iBusRsp_stages_2_halt; - wire _zz_67; - wire _zz_68; - wire _zz_69; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; wire IBusCachedPlugin_iBusRsp_flush; - wire _zz_70; - wire _zz_71; - reg _zz_72; - wire _zz_73; - reg _zz_74; - reg [31:0] _zz_75; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; reg IBusCachedPlugin_iBusRsp_readyForError; wire IBusCachedPlugin_iBusRsp_output_valid; wire IBusCachedPlugin_iBusRsp_output_ready; @@ -893,22 +831,29 @@ module VexRiscv ( wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; reg IBusCachedPlugin_injector_nextPcCalc_valids_4; - wire _zz_76; - reg [18:0] _zz_77; - wire _zz_78; - reg [10:0] _zz_79; - wire _zz_80; - reg [18:0] _zz_81; - reg _zz_82; - wire _zz_83; - reg [10:0] _zz_84; - wire _zz_85; - reg [18:0] _zz_86; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; wire iBus_cmd_valid; wire iBus_cmd_ready; reg [31:0] iBus_cmd_payload_address; @@ -916,7 +861,7 @@ module VexRiscv ( wire iBus_rsp_valid; wire [31:0] iBus_rsp_payload_data; wire iBus_rsp_payload_error; - wire [31:0] _zz_87; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; reg [31:0] IBusCachedPlugin_rspCounter; wire IBusCachedPlugin_s0_tightlyCoupledHit; reg IBusCachedPlugin_s1_tightlyCoupledHit; @@ -924,23 +869,28 @@ module VexRiscv ( wire IBusCachedPlugin_rsp_iBusRspOutputHalt; wire IBusCachedPlugin_rsp_issueDetected; reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; wire dataCache_1_io_mem_cmd_s2mPipe_valid; - wire dataCache_1_io_mem_cmd_s2mPipe_ready; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -948,40 +898,56 @@ module VexRiscv ( wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - reg dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; - wire [31:0] _zz_88; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; wire [1:0] execute_DBusCachedPlugin_size; - reg [31:0] _zz_89; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; reg [31:0] writeBack_DBusCachedPlugin_rspShifted; - wire _zz_90; - reg [31:0] _zz_91; - wire _zz_92; - reg [31:0] _zz_93; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; reg [31:0] writeBack_DBusCachedPlugin_rspFormated; - wire [34:0] _zz_94; - wire _zz_95; - wire _zz_96; - wire _zz_97; - wire _zz_98; - wire _zz_99; - wire `Src1CtrlEnum_defaultEncoding_type _zz_100; - wire `AluCtrlEnum_defaultEncoding_type _zz_101; - wire `Src2CtrlEnum_defaultEncoding_type _zz_102; - wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_103; - wire `ShiftCtrlEnum_defaultEncoding_type _zz_104; - wire `BranchCtrlEnum_defaultEncoding_type _zz_105; - wire `EnvCtrlEnum_defaultEncoding_type _zz_106; - wire `Input2Kind_defaultEncoding_type _zz_107; + wire when_DBusCachedPlugin_l484; + wire [34:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6; + wire _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire `Input2Kind_binary_sequential_type _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; + wire when_RegFilePlugin_l63; wire [4:0] decode_RegFilePlugin_regFileReadAddress1; wire [4:0] decode_RegFilePlugin_regFileReadAddress2; wire [31:0] decode_RegFilePlugin_rs1Data; @@ -989,53 +955,72 @@ module VexRiscv ( reg lastStageRegFileWrite_valid /* verilator public */ ; reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; - reg _zz_108; + reg _zz_7; reg [31:0] execute_IntAluPlugin_bitwise; - reg [31:0] _zz_109; - reg [31:0] _zz_110; - wire _zz_111; - reg [19:0] _zz_112; - wire _zz_113; - reg [19:0] _zz_114; - reg [31:0] _zz_115; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; reg [31:0] execute_SrcPlugin_addSub; wire execute_SrcPlugin_less; wire [4:0] execute_FullBarrelShifterPlugin_amplitude; - reg [31:0] _zz_116; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; wire [31:0] execute_FullBarrelShifterPlugin_reversed; - reg [31:0] _zz_117; - reg _zz_118; - reg _zz_119; - reg _zz_120; - reg [4:0] _zz_121; - reg [31:0] _zz_122; - wire _zz_123; - wire _zz_124; - wire _zz_125; - wire _zz_126; - wire _zz_127; - wire _zz_128; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; wire execute_BranchPlugin_eq; - wire [2:0] _zz_129; - reg _zz_130; - reg _zz_131; - wire _zz_132; - reg [19:0] _zz_133; - wire _zz_134; - reg [10:0] _zz_135; - wire _zz_136; - reg [18:0] _zz_137; - reg _zz_138; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; wire execute_BranchPlugin_missAlignedTarget; reg [31:0] execute_BranchPlugin_branch_src1; reg [31:0] execute_BranchPlugin_branch_src2; - wire _zz_139; - reg [19:0] _zz_140; - wire _zz_141; - reg [10:0] _zz_142; - wire _zz_143; - reg [18:0] _zz_144; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; wire [31:0] execute_BranchPlugin_branchAdder; + wire when_BranchPlugin_l296; reg [1:0] CsrPlugin_misa_base; reg [25:0] CsrPlugin_misa_extensions; reg [1:0] CsrPlugin_mtvec_mode; @@ -1056,9 +1041,9 @@ module VexRiscv ( reg [31:0] CsrPlugin_mtval; reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; - wire _zz_145; - wire _zz_146; - wire _zz_147; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; @@ -1071,72 +1056,69 @@ module VexRiscv ( reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; - wire [1:0] _zz_148; - wire _zz_149; - wire [1:0] _zz_150; - wire _zz_151; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; reg CsrPlugin_interrupt_valid; reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; wire CsrPlugin_exception; reg CsrPlugin_lastStageWasWfi; reg CsrPlugin_pipelineLiberator_pcValids_0; reg CsrPlugin_pipelineLiberator_pcValids_1; reg CsrPlugin_pipelineLiberator_pcValids_2; wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; wire CsrPlugin_interruptJump /* verilator public */ ; reg CsrPlugin_hadException /* verilator public */ ; reg [1:0] CsrPlugin_targetPrivilege; reg [3:0] CsrPlugin_trapCause; reg [1:0] CsrPlugin_xtvec_mode; reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; wire execute_CsrPlugin_blockedBySideEffects; reg execute_CsrPlugin_illegalAccess; reg execute_CsrPlugin_illegalInstruction; - wire [31:0] execute_CsrPlugin_readData; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; reg execute_CsrPlugin_writeInstruction; reg execute_CsrPlugin_readInstruction; wire execute_CsrPlugin_writeEnable; wire execute_CsrPlugin_readEnable; wire [31:0] execute_CsrPlugin_readToWriteData; - reg [31:0] execute_CsrPlugin_writeData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; wire [11:0] execute_CsrPlugin_csrAddress; - reg [31:0] _zz_152; - reg [31:0] _zz_153; - reg [31:0] _zz_154; - reg [31:0] _zz_155; - reg [31:0] _zz_156; - reg [31:0] _zz_157; - reg [31:0] _zz_158; - reg [31:0] _zz_159; - reg [31:0] _zz_160; - reg [31:0] _zz_161; - reg [31:0] _zz_162; - reg [31:0] _zz_163; - reg [31:0] _zz_164; - reg [31:0] _zz_165; - reg [31:0] _zz_166; - reg [31:0] _zz_167; - wire execute_CfuPlugin_schedule; - reg execute_CfuPlugin_hold; - reg execute_CfuPlugin_fired; - wire [9:0] execute_CfuPlugin_functionsIds_0; - wire _zz_168; - reg [23:0] _zz_169; - reg [31:0] _zz_170; - wire memory_CfuPlugin_rsp_valid; - reg memory_CfuPlugin_rsp_ready; - wire memory_CfuPlugin_rsp_payload_response_ok; - wire [31:0] memory_CfuPlugin_rsp_payload_outputs_0; - reg CfuPlugin_bus_rsp_s2mPipe_rValid; - reg CfuPlugin_bus_rsp_s2mPipe_rData_response_ok; - reg [31:0] CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0; reg execute_MulPlugin_aSigned; reg execute_MulPlugin_bSigned; wire [31:0] execute_MulPlugin_a; wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; wire [15:0] execute_MulPlugin_aULow; wire [15:0] execute_MulPlugin_bULow; wire [16:0] execute_MulPlugin_aSLow; @@ -1144,6 +1126,8 @@ module VexRiscv ( wire [16:0] execute_MulPlugin_aHigh; wire [16:0] execute_MulPlugin_bHigh; wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; reg [32:0] memory_DivPlugin_rs1; reg [31:0] memory_DivPlugin_rs2; reg [64:0] memory_DivPlugin_accumulator; @@ -1156,19 +1140,26 @@ module VexRiscv ( wire memory_DivPlugin_div_counter_willOverflowIfInc; wire memory_DivPlugin_div_counter_willOverflow; reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; reg [31:0] memory_DivPlugin_div_result; - wire [31:0] _zz_171; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; - wire [31:0] _zz_172; - wire _zz_173; - wire _zz_174; - reg [32:0] _zz_175; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; reg [31:0] externalInterruptArray_regNext; - reg [31:0] _zz_176; - wire [31:0] _zz_177; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; reg DebugPlugin_firstCycle; reg DebugPlugin_secondCycle; reg DebugPlugin_resetIt; @@ -1176,236 +1167,408 @@ module VexRiscv ( reg DebugPlugin_stepIt; reg DebugPlugin_isPipBusy; reg DebugPlugin_godmode; + wire when_DebugPlugin_l225; reg DebugPlugin_haltedByBreak; - reg [31:0] DebugPlugin_busReadDataReg; - reg _zz_178; + reg DebugPlugin_debugUsed /* verilator public */ ; + reg DebugPlugin_disableEbreak; wire DebugPlugin_allowEBreak; + reg [31:0] DebugPlugin_busReadDataReg; + reg _zz_when_DebugPlugin_l244; + wire when_DebugPlugin_l244; + wire [5:0] switch_DebugPlugin_l256; + wire when_DebugPlugin_l260; + wire when_DebugPlugin_l260_1; + wire when_DebugPlugin_l261; + wire when_DebugPlugin_l261_1; + wire when_DebugPlugin_l262; + wire when_DebugPlugin_l263; + wire when_DebugPlugin_l264; + wire when_DebugPlugin_l264_1; + wire when_DebugPlugin_l284; + wire when_DebugPlugin_l287; + wire when_DebugPlugin_l300; reg DebugPlugin_resetIt_regNext; + wire when_DebugPlugin_l316; + wire execute_CfuPlugin_schedule; + reg execute_CfuPlugin_hold; + reg execute_CfuPlugin_fired; + wire CfuPlugin_bus_cmd_fire; + wire when_CfuPlugin_l171; + wire when_CfuPlugin_l175; + wire [9:0] execute_CfuPlugin_functionsIds_0; + wire _zz_CfuPlugin_bus_cmd_payload_inputs_1; + reg [23:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_1; + reg [31:0] _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + wire CfuPlugin_bus_rsp_rsp_valid; + reg CfuPlugin_bus_rsp_rsp_ready; + wire [31:0] CfuPlugin_bus_rsp_rsp_payload_outputs_0; + reg CfuPlugin_bus_rsp_rValid; + reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; + wire when_CfuPlugin_l208; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_when_GenCoreDefault_l367; + wire when_GenCoreDefault_l367; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_when_GenCoreDefault_l367_1; + wire when_GenCoreDefault_l367_1; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_when_GenCoreDefault_l367_2; + wire when_GenCoreDefault_l367_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_when_GenCoreDefault_l367_3; + wire when_GenCoreDefault_l367_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_when_GenCoreDefault_l367_4; + wire when_GenCoreDefault_l367_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_when_GenCoreDefault_l367_5; + wire when_GenCoreDefault_l367_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_when_GenCoreDefault_l367_6; + wire when_GenCoreDefault_l367_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_when_GenCoreDefault_l367_7; + wire when_GenCoreDefault_l367_7; + wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; - reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; reg memory_to_writeBack_MEMORY_ENABLE; - reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; - reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; reg decode_to_execute_SRC_LESS_UNSIGNED; - reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; - reg `ShiftCtrlEnum_defaultEncoding_type execute_to_memory_SHIFT_CTRL; - reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; reg decode_to_execute_IS_CSR; - reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_ENV_CTRL; - reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_ENV_CTRL; - reg decode_to_execute_CfuPlugin_CFU_ENABLE; - reg `Input2Kind_defaultEncoding_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; + reg decode_to_execute_CfuPlugin_CFU_ENABLE; + wire when_Pipeline_l124_44; + reg `Input2Kind_binary_sequential_type decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + wire when_Pipeline_l124_45; reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_46; reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_47; reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_48; reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_49; reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_50; reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_51; reg decode_to_execute_DO_EBREAK; - reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; - reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + wire when_Pipeline_l124_52; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_53; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_54; reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_55; reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_56; reg [31:0] execute_to_memory_SHIFT_RIGHT; - reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_57; reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_58; reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_59; reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_60; reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_61; reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_62; + reg execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_63; + reg memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + wire when_Pipeline_l124_64; reg [51:0] memory_to_writeBack_MUL_LOW; - reg [2:0] _zz_179; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + reg [2:0] switch_Fetcher_l362; + wire when_Fetcher_l378; + wire when_CsrPlugin_l1264; reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; + reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; + reg execute_CsrPlugin_csr_4032; + wire when_CsrPlugin_l1264_24; reg execute_CsrPlugin_csr_2820; + wire when_CsrPlugin_l1264_25; reg execute_CsrPlugin_csr_2821; + wire when_CsrPlugin_l1264_26; reg execute_CsrPlugin_csr_2822; + wire when_CsrPlugin_l1264_27; reg execute_CsrPlugin_csr_2823; + wire when_CsrPlugin_l1264_28; reg execute_CsrPlugin_csr_2824; + wire when_CsrPlugin_l1264_29; reg execute_CsrPlugin_csr_2825; + wire when_CsrPlugin_l1264_30; reg execute_CsrPlugin_csr_2826; + wire when_CsrPlugin_l1264_31; reg execute_CsrPlugin_csr_2827; + wire when_CsrPlugin_l1264_32; reg execute_CsrPlugin_csr_2828; + wire when_CsrPlugin_l1264_33; reg execute_CsrPlugin_csr_2829; + wire when_CsrPlugin_l1264_34; reg execute_CsrPlugin_csr_2830; + wire when_CsrPlugin_l1264_35; reg execute_CsrPlugin_csr_2831; + wire when_CsrPlugin_l1264_36; reg execute_CsrPlugin_csr_2832; + wire when_CsrPlugin_l1264_37; reg execute_CsrPlugin_csr_2833; + wire when_CsrPlugin_l1264_38; reg execute_CsrPlugin_csr_2834; + wire when_CsrPlugin_l1264_39; reg execute_CsrPlugin_csr_2835; - reg execute_CsrPlugin_csr_3008; - reg execute_CsrPlugin_csr_4032; - reg [31:0] _zz_180; - reg [31:0] _zz_181; - reg [31:0] _zz_182; - reg [31:0] _zz_183; - reg [31:0] _zz_184; - reg [31:0] _zz_185; - reg [31:0] _zz_186; - reg [31:0] _zz_187; - reg [31:0] _zz_188; - reg [31:0] _zz_189; - reg [31:0] _zz_190; - reg [31:0] _zz_191; - reg [31:0] _zz_192; - reg [31:0] _zz_193; - reg [31:0] _zz_194; - reg [31:0] _zz_195; - reg [31:0] _zz_196; - reg [31:0] _zz_197; - reg [31:0] _zz_198; - reg [31:0] _zz_199; - reg [31:0] _zz_200; - reg [31:0] _zz_201; - reg [31:0] _zz_202; - reg [31:0] _zz_203; - reg [31:0] _zz_204; - reg [31:0] _zz_205; - reg [31:0] _zz_206; - reg [31:0] _zz_207; - reg [31:0] _zz_208; - reg [31:0] _zz_209; - reg [31:0] _zz_210; - reg [2:0] _zz_211; - reg _zz_212; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_29; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_30; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_31; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_32; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_33; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_34; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_35; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_36; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_37; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_38; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_39; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_40; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; reg [31:0] iBusWishbone_DAT_MISO_regNext; - reg [2:0] _zz_213; - wire _zz_214; - wire _zz_215; - wire _zz_216; - wire _zz_217; - wire _zz_218; - reg _zz_219; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; reg [31:0] dBusWishbone_DAT_MISO_regNext; `ifndef SYNTHESIS reg [39:0] decode_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_1_string; - reg [39:0] _zz_2_string; - reg [39:0] _zz_3_string; - reg [39:0] _zz_4_string; - reg [39:0] _zz_5_string; - reg [39:0] _zz_6_string; - reg [39:0] _zz_7_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string; + reg [39:0] _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; reg [39:0] decode_ENV_CTRL_string; - reg [39:0] _zz_8_string; - reg [39:0] _zz_9_string; - reg [39:0] _zz_10_string; - reg [31:0] _zz_11_string; - reg [31:0] _zz_12_string; - reg [71:0] _zz_13_string; - reg [71:0] _zz_14_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; reg [71:0] decode_SHIFT_CTRL_string; - reg [71:0] _zz_15_string; - reg [71:0] _zz_16_string; - reg [71:0] _zz_17_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; reg [39:0] decode_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_18_string; - reg [39:0] _zz_19_string; - reg [39:0] _zz_20_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; reg [23:0] decode_SRC2_CTRL_string; - reg [23:0] _zz_21_string; - reg [23:0] _zz_22_string; - reg [23:0] _zz_23_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; reg [63:0] decode_ALU_CTRL_string; - reg [63:0] _zz_24_string; - reg [63:0] _zz_25_string; - reg [63:0] _zz_26_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; reg [95:0] decode_SRC1_CTRL_string; - reg [95:0] _zz_27_string; - reg [95:0] _zz_28_string; - reg [95:0] _zz_29_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; reg [39:0] execute_CfuPlugin_CFU_INPUT_2_KIND_string; - reg [39:0] _zz_32_string; + reg [39:0] _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string; reg [39:0] memory_ENV_CTRL_string; - reg [39:0] _zz_33_string; + reg [39:0] _zz_memory_ENV_CTRL_string; reg [39:0] execute_ENV_CTRL_string; - reg [39:0] _zz_34_string; + reg [39:0] _zz_execute_ENV_CTRL_string; reg [39:0] writeBack_ENV_CTRL_string; - reg [39:0] _zz_35_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; reg [31:0] execute_BRANCH_CTRL_string; - reg [31:0] _zz_36_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; reg [71:0] memory_SHIFT_CTRL_string; - reg [71:0] _zz_39_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; reg [71:0] execute_SHIFT_CTRL_string; - reg [71:0] _zz_40_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; reg [23:0] execute_SRC2_CTRL_string; - reg [23:0] _zz_42_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; reg [95:0] execute_SRC1_CTRL_string; - reg [95:0] _zz_43_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; reg [63:0] execute_ALU_CTRL_string; - reg [63:0] _zz_44_string; + reg [63:0] _zz_execute_ALU_CTRL_string; reg [39:0] execute_ALU_BITWISE_CTRL_string; - reg [39:0] _zz_45_string; - reg [39:0] _zz_49_string; - reg [39:0] _zz_50_string; - reg [31:0] _zz_51_string; - reg [71:0] _zz_52_string; - reg [39:0] _zz_53_string; - reg [23:0] _zz_54_string; - reg [63:0] _zz_55_string; - reg [95:0] _zz_56_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; reg [31:0] decode_BRANCH_CTRL_string; - reg [31:0] _zz_58_string; - reg [95:0] _zz_100_string; - reg [63:0] _zz_101_string; - reg [23:0] _zz_102_string; - reg [39:0] _zz_103_string; - reg [71:0] _zz_104_string; - reg [31:0] _zz_105_string; - reg [39:0] _zz_106_string; - reg [39:0] _zz_107_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [39:0] _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string; reg [95:0] decode_to_execute_SRC1_CTRL_string; reg [63:0] decode_to_execute_ALU_CTRL_string; reg [23:0] decode_to_execute_SRC2_CTRL_string; @@ -1421,489 +1584,441 @@ module VexRiscv ( (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; - assign _zz_251 = (execute_arbitration_isValid && execute_IS_CSR); - assign _zz_252 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_253 = 1'b1; - assign _zz_254 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_255 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_256 = (memory_arbitration_isValid && memory_IS_DIV); - assign _zz_257 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); - assign _zz_258 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); - assign _zz_259 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); - assign _zz_260 = ((_zz_225 && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); - assign _zz_261 = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); - assign _zz_262 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - assign _zz_263 = (execute_arbitration_isValid && execute_DO_EBREAK); - assign _zz_264 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); - assign _zz_265 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); - assign _zz_266 = (CsrPlugin_hadException || CsrPlugin_interruptJump); - assign _zz_267 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); - assign _zz_268 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); - assign _zz_269 = writeBack_INSTRUCTION[29 : 28]; - assign _zz_270 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_271 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); - assign _zz_272 = (1'b0 || (! 1'b1)); - assign _zz_273 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); - assign _zz_274 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); - assign _zz_275 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); - assign _zz_276 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); - assign _zz_277 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); - assign _zz_278 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); - assign _zz_279 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)); - assign _zz_280 = execute_INSTRUCTION[13 : 12]; - assign _zz_281 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); - assign _zz_282 = (! memory_arbitration_isStuck); - assign _zz_283 = debug_bus_cmd_payload_address[7 : 2]; - assign _zz_284 = (iBus_cmd_valid || (_zz_211 != 3'b000)); - assign _zz_285 = (_zz_247 && (! dataCache_1_io_mem_cmd_s2mPipe_ready)); - assign _zz_286 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); - assign _zz_287 = ((_zz_145 && 1'b1) && (! 1'b0)); - assign _zz_288 = ((_zz_146 && 1'b1) && (! 1'b0)); - assign _zz_289 = ((_zz_147 && 1'b1) && (! 1'b0)); - assign _zz_290 = (CfuPlugin_bus_rsp_ready && (! memory_CfuPlugin_rsp_ready)); - assign _zz_291 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_292 = execute_INSTRUCTION[13]; - assign _zz_293 = writeBack_INSTRUCTION[13 : 12]; - assign _zz_294 = ($signed(_zz_295) + $signed(_zz_300)); - assign _zz_295 = ($signed(_zz_296) + $signed(_zz_298)); - assign _zz_296 = 52'h0; - assign _zz_297 = {1'b0,memory_MUL_LL}; - assign _zz_298 = {{19{_zz_297[32]}}, _zz_297}; - assign _zz_299 = ({16'd0,memory_MUL_LH} <<< 16); - assign _zz_300 = {{2{_zz_299[49]}}, _zz_299}; - assign _zz_301 = ({16'd0,memory_MUL_HL} <<< 16); - assign _zz_302 = {{2{_zz_301[49]}}, _zz_301}; - assign _zz_303 = ($signed(_zz_305) >>> execute_FullBarrelShifterPlugin_amplitude); - assign _zz_304 = _zz_303[31 : 0]; - assign _zz_305 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; - assign _zz_306 = _zz_94[33 : 33]; - assign _zz_307 = _zz_94[32 : 32]; - assign _zz_308 = _zz_94[31 : 31]; - assign _zz_309 = _zz_94[30 : 30]; - assign _zz_310 = _zz_94[28 : 28]; - assign _zz_311 = _zz_94[25 : 25]; - assign _zz_312 = _zz_94[17 : 17]; - assign _zz_313 = _zz_94[16 : 16]; - assign _zz_314 = _zz_94[13 : 13]; - assign _zz_315 = _zz_94[12 : 12]; - assign _zz_316 = _zz_94[11 : 11]; - assign _zz_317 = _zz_94[34 : 34]; - assign _zz_318 = _zz_94[15 : 15]; - assign _zz_319 = _zz_94[5 : 5]; - assign _zz_320 = _zz_94[3 : 3]; - assign _zz_321 = _zz_94[20 : 20]; - assign _zz_322 = _zz_94[10 : 10]; - assign _zz_323 = _zz_94[4 : 4]; - assign _zz_324 = _zz_94[0 : 0]; - assign _zz_325 = (_zz_62 - 4'b0001); - assign _zz_326 = {IBusCachedPlugin_fetchPc_inc,2'b00}; - assign _zz_327 = {29'd0, _zz_326}; - assign _zz_328 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_329 = {{_zz_77,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_330 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_331 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_332 = {{_zz_79,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_333 = {{_zz_81,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_334 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; - assign _zz_335 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; - assign _zz_336 = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); - assign _zz_337 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); - assign _zz_338 = execute_SRC_LESS; - assign _zz_339 = 3'b100; - assign _zz_340 = execute_INSTRUCTION[19 : 15]; - assign _zz_341 = execute_INSTRUCTION[31 : 20]; - assign _zz_342 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; - assign _zz_343 = ($signed(_zz_344) + $signed(_zz_347)); - assign _zz_344 = ($signed(_zz_345) + $signed(_zz_346)); - assign _zz_345 = execute_SRC1; - assign _zz_346 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); - assign _zz_347 = (execute_SRC_USE_SUB_LESS ? _zz_348 : _zz_349); - assign _zz_348 = 32'h00000001; - assign _zz_349 = 32'h0; - assign _zz_350 = execute_INSTRUCTION[31 : 20]; - assign _zz_351 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_352 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_353 = {_zz_133,execute_INSTRUCTION[31 : 20]}; - assign _zz_354 = {{_zz_135,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; - assign _zz_355 = {{_zz_137,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; - assign _zz_356 = execute_INSTRUCTION[31 : 20]; - assign _zz_357 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; - assign _zz_358 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; - assign _zz_359 = 3'b100; - assign _zz_360 = (_zz_148 & (~ _zz_361)); - assign _zz_361 = (_zz_148 - 2'b01); - assign _zz_362 = (_zz_150 & (~ _zz_363)); - assign _zz_363 = (_zz_150 - 2'b01); - assign _zz_364 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; - assign _zz_365 = execute_INSTRUCTION[31 : 24]; - assign _zz_366 = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; - assign _zz_367 = ({32'd0,writeBack_MUL_HH} <<< 32); - assign _zz_368 = writeBack_MUL_LOW[31 : 0]; - assign _zz_369 = writeBack_MulPlugin_result[63 : 32]; - assign _zz_370 = memory_DivPlugin_div_counter_willIncrement; - assign _zz_371 = {5'd0, _zz_370}; - assign _zz_372 = {1'd0, memory_DivPlugin_rs2}; - assign _zz_373 = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; - assign _zz_374 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; - assign _zz_375 = {_zz_171,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; - assign _zz_376 = _zz_377; - assign _zz_377 = _zz_378; - assign _zz_378 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_172) : _zz_172)} + _zz_380); - assign _zz_379 = memory_DivPlugin_div_needRevert; - assign _zz_380 = {32'd0, _zz_379}; - assign _zz_381 = _zz_174; - assign _zz_382 = {32'd0, _zz_381}; - assign _zz_383 = _zz_173; - assign _zz_384 = {31'd0, _zz_383}; - assign _zz_385 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_386 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_387 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_388 = execute_CsrPlugin_writeData[11 : 11]; - assign _zz_389 = execute_CsrPlugin_writeData[7 : 7]; - assign _zz_390 = execute_CsrPlugin_writeData[3 : 3]; - assign _zz_391 = execute_CsrPlugin_writeData[31 : 31]; - assign _zz_392 = (iBus_cmd_payload_address >>> 5); - assign _zz_393 = 1'b1; - assign _zz_394 = 1'b1; - assign _zz_395 = {_zz_66,_zz_65}; - assign _zz_396 = 32'h0000106f; - assign _zz_397 = (decode_INSTRUCTION & 32'h0000107f); - assign _zz_398 = 32'h00001073; - assign _zz_399 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); - assign _zz_400 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); - assign _zz_401 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_402) == 32'h00000003),{(_zz_403 == _zz_404),{_zz_405,{_zz_406,_zz_407}}}}}}; - assign _zz_402 = 32'h0000207f; - assign _zz_403 = (decode_INSTRUCTION & 32'h0000505f); - assign _zz_404 = 32'h00000003; - assign _zz_405 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); - assign _zz_406 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); - assign _zz_407 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_408) == 32'h00005013),{(_zz_409 == _zz_410),{_zz_411,{_zz_412,_zz_413}}}}}}; - assign _zz_408 = 32'hbc00707f; - assign _zz_409 = (decode_INSTRUCTION & 32'hfc00307f); - assign _zz_410 = 32'h00001013; - assign _zz_411 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); - assign _zz_412 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); - assign _zz_413 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; - assign _zz_414 = decode_INSTRUCTION[31]; - assign _zz_415 = decode_INSTRUCTION[31]; - assign _zz_416 = decode_INSTRUCTION[7]; - assign _zz_417 = 32'h10103050; - assign _zz_418 = ((decode_INSTRUCTION & 32'h02004064) == 32'h02004020); - assign _zz_419 = 1'b0; - assign _zz_420 = (((decode_INSTRUCTION & 32'h02004074) == 32'h02000030) != 1'b0); - assign _zz_421 = 1'b0; - assign _zz_422 = {(_zz_98 != 1'b0),{({_zz_423,_zz_424} != 2'b00),{(_zz_425 != _zz_426),{_zz_427,{_zz_428,_zz_429}}}}}; - assign _zz_423 = ((decode_INSTRUCTION & _zz_430) == 32'h10000050); - assign _zz_424 = ((decode_INSTRUCTION & _zz_431) == 32'h00000050); - assign _zz_425 = ((decode_INSTRUCTION & _zz_432) == 32'h00000050); - assign _zz_426 = 1'b0; - assign _zz_427 = ({_zz_433,_zz_434} != 2'b00); - assign _zz_428 = ({_zz_435,_zz_436} != 2'b00); - assign _zz_429 = {(_zz_437 != _zz_438),{_zz_439,{_zz_440,_zz_441}}}; - assign _zz_430 = 32'h10203050; - assign _zz_431 = 32'h10103050; - assign _zz_432 = 32'h00103050; - assign _zz_433 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); - assign _zz_434 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); - assign _zz_435 = _zz_97; - assign _zz_436 = ((decode_INSTRUCTION & _zz_442) == 32'h00000004); - assign _zz_437 = ((decode_INSTRUCTION & _zz_443) == 32'h00000040); - assign _zz_438 = 1'b0; - assign _zz_439 = ({_zz_444,_zz_445} != 2'b00); - assign _zz_440 = ({_zz_446,_zz_447} != 3'b000); - assign _zz_441 = {(_zz_448 != _zz_449),{_zz_450,{_zz_451,_zz_452}}}; - assign _zz_442 = 32'h0000001c; - assign _zz_443 = 32'h00000058; - assign _zz_444 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); - assign _zz_445 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); - assign _zz_446 = ((decode_INSTRUCTION & _zz_453) == 32'h40001010); - assign _zz_447 = {(_zz_454 == _zz_455),(_zz_456 == _zz_457)}; - assign _zz_448 = ((decode_INSTRUCTION & _zz_458) == 32'h00000024); - assign _zz_449 = 1'b0; - assign _zz_450 = ((_zz_459 == _zz_460) != 1'b0); - assign _zz_451 = (_zz_461 != 1'b0); - assign _zz_452 = {(_zz_462 != _zz_463),{_zz_464,{_zz_465,_zz_466}}}; - assign _zz_453 = 32'h40003054; - assign _zz_454 = (decode_INSTRUCTION & 32'h00007034); - assign _zz_455 = 32'h00001010; - assign _zz_456 = (decode_INSTRUCTION & 32'h02007054); - assign _zz_457 = 32'h00001010; - assign _zz_458 = 32'h00000064; - assign _zz_459 = (decode_INSTRUCTION & 32'h00001000); - assign _zz_460 = 32'h00001000; - assign _zz_461 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); - assign _zz_462 = {(_zz_467 == _zz_468),(_zz_469 == _zz_470)}; - assign _zz_463 = 2'b00; - assign _zz_464 = ((_zz_471 == _zz_472) != 1'b0); - assign _zz_465 = ({_zz_473,_zz_474} != 3'b000); - assign _zz_466 = {(_zz_475 != _zz_476),{_zz_477,{_zz_478,_zz_479}}}; - assign _zz_467 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_468 = 32'h00002000; - assign _zz_469 = (decode_INSTRUCTION & 32'h00005000); - assign _zz_470 = 32'h00001000; - assign _zz_471 = (decode_INSTRUCTION & 32'h00004054); - assign _zz_472 = 32'h00004004; - assign _zz_473 = _zz_98; - assign _zz_474 = {(_zz_480 == _zz_481),(_zz_482 == _zz_483)}; - assign _zz_475 = {(_zz_484 == _zz_485),{_zz_486,{_zz_487,_zz_488}}}; - assign _zz_476 = 5'h0; - assign _zz_477 = ((_zz_489 == _zz_490) != 1'b0); - assign _zz_478 = ({_zz_491,_zz_492} != 6'h0); - assign _zz_479 = {(_zz_493 != _zz_494),{_zz_495,{_zz_496,_zz_497}}}; - assign _zz_480 = (decode_INSTRUCTION & 32'h00000034); - assign _zz_481 = 32'h00000020; - assign _zz_482 = (decode_INSTRUCTION & 32'h00000064); - assign _zz_483 = 32'h00000020; - assign _zz_484 = (decode_INSTRUCTION & 32'h00002040); - assign _zz_485 = 32'h00002040; - assign _zz_486 = ((decode_INSTRUCTION & _zz_498) == 32'h00001040); - assign _zz_487 = (_zz_499 == _zz_500); - assign _zz_488 = {_zz_501,_zz_502}; - assign _zz_489 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_490 = 32'h00000020; - assign _zz_491 = (_zz_503 == _zz_504); - assign _zz_492 = {_zz_505,{_zz_506,_zz_507}}; - assign _zz_493 = {_zz_96,{_zz_508,_zz_509}}; - assign _zz_494 = 5'h0; - assign _zz_495 = ({_zz_510,_zz_511} != 6'h0); - assign _zz_496 = (_zz_512 != _zz_513); - assign _zz_497 = {_zz_514,{_zz_515,_zz_516}}; - assign _zz_498 = 32'h00001040; - assign _zz_499 = (decode_INSTRUCTION & 32'h00100040); - assign _zz_500 = 32'h00000040; - assign _zz_501 = ((decode_INSTRUCTION & _zz_517) == 32'h00000040); - assign _zz_502 = ((decode_INSTRUCTION & _zz_518) == 32'h0); - assign _zz_503 = (decode_INSTRUCTION & 32'h00000008); - assign _zz_504 = 32'h00000008; - assign _zz_505 = ((decode_INSTRUCTION & _zz_519) == 32'h00000040); - assign _zz_506 = _zz_96; - assign _zz_507 = {_zz_520,{_zz_521,_zz_522}}; - assign _zz_508 = (_zz_523 == _zz_524); - assign _zz_509 = {_zz_525,{_zz_526,_zz_527}}; - assign _zz_510 = _zz_97; - assign _zz_511 = {_zz_528,{_zz_529,_zz_530}}; - assign _zz_512 = {_zz_96,_zz_531}; - assign _zz_513 = 2'b00; - assign _zz_514 = ({_zz_532,_zz_533} != 2'b00); - assign _zz_515 = (_zz_534 != _zz_535); - assign _zz_516 = {_zz_536,{_zz_537,_zz_538}}; - assign _zz_517 = 32'h00000050; - assign _zz_518 = 32'h00000038; - assign _zz_519 = 32'h00000040; - assign _zz_520 = ((decode_INSTRUCTION & _zz_539) == 32'h00004020); - assign _zz_521 = (_zz_540 == _zz_541); - assign _zz_522 = (_zz_542 == _zz_543); - assign _zz_523 = (decode_INSTRUCTION & 32'h00002030); - assign _zz_524 = 32'h00002010; - assign _zz_525 = ((decode_INSTRUCTION & _zz_544) == 32'h00000010); - assign _zz_526 = (_zz_545 == _zz_546); - assign _zz_527 = (_zz_547 == _zz_548); - assign _zz_528 = ((decode_INSTRUCTION & _zz_549) == 32'h00001010); - assign _zz_529 = (_zz_550 == _zz_551); - assign _zz_530 = {_zz_552,{_zz_553,_zz_554}}; - assign _zz_531 = ((decode_INSTRUCTION & _zz_555) == 32'h00000020); - assign _zz_532 = _zz_96; - assign _zz_533 = (_zz_556 == _zz_557); - assign _zz_534 = (_zz_558 == _zz_559); - assign _zz_535 = 1'b0; - assign _zz_536 = (_zz_560 != 1'b0); - assign _zz_537 = (_zz_561 != _zz_562); - assign _zz_538 = {_zz_563,{_zz_564,_zz_565}}; - assign _zz_539 = 32'h00004020; - assign _zz_540 = (decode_INSTRUCTION & 32'h00000030); - assign _zz_541 = 32'h00000010; - assign _zz_542 = (decode_INSTRUCTION & 32'h02000020); - assign _zz_543 = 32'h00000020; - assign _zz_544 = 32'h00001030; - assign _zz_545 = (decode_INSTRUCTION & 32'h02002060); - assign _zz_546 = 32'h00002020; - assign _zz_547 = (decode_INSTRUCTION & 32'h02003020); - assign _zz_548 = 32'h00000020; - assign _zz_549 = 32'h00001010; - assign _zz_550 = (decode_INSTRUCTION & 32'h00002010); - assign _zz_551 = 32'h00002010; - assign _zz_552 = ((decode_INSTRUCTION & _zz_566) == 32'h00000010); - assign _zz_553 = (_zz_567 == _zz_568); - assign _zz_554 = (_zz_569 == _zz_570); - assign _zz_555 = 32'h00000070; - assign _zz_556 = (decode_INSTRUCTION & 32'h00000020); - assign _zz_557 = 32'h0; - assign _zz_558 = (decode_INSTRUCTION & 32'h00004014); - assign _zz_559 = 32'h00004010; - assign _zz_560 = ((decode_INSTRUCTION & _zz_571) == 32'h00002010); - assign _zz_561 = {_zz_572,{_zz_573,_zz_574}}; - assign _zz_562 = 4'b0000; - assign _zz_563 = (_zz_575 != 1'b0); - assign _zz_564 = (_zz_576 != _zz_577); - assign _zz_565 = {_zz_578,{_zz_579,_zz_580}}; - assign _zz_566 = 32'h00000050; - assign _zz_567 = (decode_INSTRUCTION & 32'h0000000c); - assign _zz_568 = 32'h00000004; - assign _zz_569 = (decode_INSTRUCTION & 32'h00000024); - assign _zz_570 = 32'h0; - assign _zz_571 = 32'h00006014; - assign _zz_572 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); - assign _zz_573 = ((decode_INSTRUCTION & _zz_581) == 32'h0); - assign _zz_574 = {(_zz_582 == _zz_583),(_zz_584 == _zz_585)}; - assign _zz_575 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); - assign _zz_576 = {(_zz_586 == _zz_587),{_zz_588,_zz_589}}; - assign _zz_577 = 3'b000; - assign _zz_578 = ({_zz_590,_zz_95} != 2'b00); - assign _zz_579 = ({_zz_591,_zz_592} != 2'b00); - assign _zz_580 = (_zz_593 != 1'b0); - assign _zz_581 = 32'h00000018; - assign _zz_582 = (decode_INSTRUCTION & 32'h00006004); - assign _zz_583 = 32'h00002000; - assign _zz_584 = (decode_INSTRUCTION & 32'h00005004); - assign _zz_585 = 32'h00001000; - assign _zz_586 = (decode_INSTRUCTION & 32'h00000044); - assign _zz_587 = 32'h00000040; - assign _zz_588 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); - assign _zz_589 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); - assign _zz_590 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); - assign _zz_591 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); - assign _zz_592 = _zz_95; - assign _zz_593 = ((decode_INSTRUCTION & 32'h00005054) == 32'h00001004); - assign _zz_594 = execute_INSTRUCTION[31]; - assign _zz_595 = execute_INSTRUCTION[31]; - assign _zz_596 = execute_INSTRUCTION[7]; - assign _zz_597 = 32'h0; - always @ (posedge clk) begin - if(_zz_393) begin - _zz_248 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; - end - end - - always @ (posedge clk) begin - if(_zz_394) begin - _zz_249 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; - end - end - - always @ (posedge clk) begin - if(_zz_48) begin + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_when_1 = ({CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_execute_CfuPlugin_functionsIds_0 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[14 : 12]}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000106f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000107f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00001073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002073); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013),{((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000207f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000505f); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000003; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000707b) == 32'h00000063); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033),{((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00005013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hbc00707f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hfc00307f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00001013; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00005033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073),{((decode_INSTRUCTION & 32'hffefffff) == 32'h00000073),((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073)}}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = (decode_INSTRUCTION & 32'h10103050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1 = 32'h00100050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4 = (((decode_INSTRUCTION & 32'h02004064) == 32'h02004020) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5 = (((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6) == 32'h02000030) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7 = {({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9} != 2'b00),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21}}}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_6 = 32'h02004074; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_8 = ((decode_INSTRUCTION & 32'h10203050) == 32'h10000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_9 = ((decode_INSTRUCTION & 32'h10103050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_10 = ((decode_INSTRUCTION & 32'h00103050) == 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_11 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_16 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_17 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_19 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_21 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_12 = (decode_INSTRUCTION & 32'h00001050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_13 = 32'h00001050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_14 = (decode_INSTRUCTION & 32'h00002050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_15 = 32'h00002050; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_18 = ((decode_INSTRUCTION & 32'h0000001c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_20 = ((decode_INSTRUCTION & 32'h00000058) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_22 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_27 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_28 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_34 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_36 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_23 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_24 = 32'h00005010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_25 = (decode_INSTRUCTION & 32'h02007064); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_26 = 32'h00005020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_29 = ((decode_INSTRUCTION & 32'h40003054) == 32'h40001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_30 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_32 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33) == 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_35 = ((decode_INSTRUCTION & 32'h00000064) == 32'h00000024); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_37 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_39 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_40 = ((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42) != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_43 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_48 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_31 = 32'h00007034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_33 = 32'h02007054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_38 = 32'h00001000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_41 = (decode_INSTRUCTION & 32'h00003000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_42 = 32'h00002000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_44 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_46 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_49 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50) == 32'h00004004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_51 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_52 = ({_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_57 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_71 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_45 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_47 = 32'h00005000; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_50 = 32'h00004054; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_53 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_55 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_58 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59) == 32'h00002040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_60 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_72 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_74 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_75 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81}} != 6'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_90 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92} != 5'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_103 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128}}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_54 = 32'h00000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_56 = 32'h00000064; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_59 = 32'h00002040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_61 = (decode_INSTRUCTION & 32'h00001040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_62 = 32'h00001040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_63 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_65 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_68 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_73 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_76 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77) == 32'h00000008); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_78 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_81 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_91 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_92 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_104 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_117 = 6'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_118 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_123 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_128 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_64 = 32'h00100040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_66 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_67 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_69 = (decode_INSTRUCTION & 32'h00000038); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_70 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_77 = 32'h00000008; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_79 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_80 = 32'h00000040; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_82 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_85 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_93 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_95 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_98 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_105 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_108 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_119 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_120 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_124 = {_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_127 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_129 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 != 1'b0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_132 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_137 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_83 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_84 = 32'h00004020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_86 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87) == 32'h00000010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_88 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_94 = 32'h00002030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_96 = (decode_INSTRUCTION & 32'h00001030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_97 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_99 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100) == 32'h00002020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_101 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102) == 32'h00000020); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_106 = (decode_INSTRUCTION & 32'h00001010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_107 = 32'h00001010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_109 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_111 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_114 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_121 = (decode_INSTRUCTION & 32'h00000070); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_122 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_125 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_130 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131) == 32'h00004010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_133 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_136 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_138 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141} != 4'b0000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_146 = (_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_150 = {_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_87 = 32'h00000030; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_89 = 32'h02000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_100 = 32'h02002060; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_102 = 32'h02003020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_110 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_112 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_113 = 32'h00000010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_115 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_116 = ((decode_INSTRUCTION & 32'h00000024) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_126 = 32'h00000020; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_131 = 32'h00004014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_134 = (decode_INSTRUCTION & 32'h00006014); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_135 = 32'h00002010; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_139 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_141 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145}}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_147 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148) == 32'h0); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_149 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_151 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155}} != 3'b000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_157 = ({_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160} != 2'b00); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_161 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165),(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168)}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_140 = 32'h00000044; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_142 = (decode_INSTRUCTION & 32'h00000018); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_143 = 32'h0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_144 = ((decode_INSTRUCTION & 32'h00006004) == 32'h00002000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_145 = ((decode_INSTRUCTION & 32'h00005004) == 32'h00001000); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_148 = 32'h00000058; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_152 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000040); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_153 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154) == 32'h00002010); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_155 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156) == 32'h40000030); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_158 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159) == 32'h00000004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_160 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_162 = {(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164),_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3}; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_165 = 2'b00; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_166 = ((decode_INSTRUCTION & _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167) == 32'h00001004); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_168 = 1'b0; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_154 = 32'h00002014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_156 = 32'h40000034; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_159 = 32'h00000014; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_163 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_164 = 32'h00000004; + assign _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_167 = 32'h00005054; + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_41 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; end end InstructionCache IBusCachedPlugin_cache ( - .io_flush (_zz_220 ), //i - .io_cpu_prefetch_isValid (_zz_221 ), //i - .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o - .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i - .io_cpu_fetch_isValid (_zz_222 ), //i - .io_cpu_fetch_isStuck (_zz_223 ), //i - .io_cpu_fetch_isRemoved (_zz_224 ), //i - .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i - .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o - .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i - .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o - .io_cpu_decode_isValid (_zz_225 ), //i - .io_cpu_decode_isStuck (_zz_226 ), //i - .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i - .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o - .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o - .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o - .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o - .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o - .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o - .io_cpu_decode_isUser (_zz_227 ), //i - .io_cpu_fill_valid (_zz_228 ), //i - .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i - .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (iBus_cmd_ready ), //i - .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o - .io_mem_rsp_valid (iBus_rsp_valid ), //i - .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i - ._zz_9 (_zz_179[2:0] ), //i - ._zz_10 (IBusCachedPlugin_injectionPort_payload[31:0] ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + ._zz_when_Fetcher_l398 (switch_Fetcher_l362 ), //i + ._zz_io_cpu_fetch_data_regNextWhen (IBusCachedPlugin_injectionPort_payload ), //i + .clk (clk ), //i + .reset (reset ) //i ); DataCache dataCache_1 ( - .io_cpu_execute_isValid (_zz_229 ), //i - .io_cpu_execute_address (_zz_230[31:0] ), //i - .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o - .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i - .io_cpu_execute_args_data (_zz_89[31:0] ), //i - .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i - .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i - .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o - .io_cpu_memory_isValid (_zz_231 ), //i - .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i - .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o - .io_cpu_memory_address (_zz_232[31:0] ), //i - .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i - .io_cpu_memory_mmuRsp_isIoAccess (_zz_233 ), //i - .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i - .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i - .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i - .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i - .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i - .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i - .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i - .io_cpu_writeBack_isValid (_zz_234 ), //i - .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i - .io_cpu_writeBack_isUser (_zz_235 ), //i - .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o - .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o - .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data[31:0] ), //o - .io_cpu_writeBack_address (_zz_236[31:0] ), //i - .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o - .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o - .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o - .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o - .io_cpu_writeBack_fence_SW (_zz_237 ), //i - .io_cpu_writeBack_fence_SR (_zz_238 ), //i - .io_cpu_writeBack_fence_SO (_zz_239 ), //i - .io_cpu_writeBack_fence_SI (_zz_240 ), //i - .io_cpu_writeBack_fence_PW (_zz_241 ), //i - .io_cpu_writeBack_fence_PR (_zz_242 ), //i - .io_cpu_writeBack_fence_PO (_zz_243 ), //i - .io_cpu_writeBack_fence_PI (_zz_244 ), //i - .io_cpu_writeBack_fence_FM (_zz_245[3:0] ), //i - .io_cpu_redo (dataCache_1_io_cpu_redo ), //o - .io_cpu_flush_valid (_zz_246 ), //i - .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o - .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o - .io_mem_cmd_ready (_zz_247 ), //i - .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o - .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o - .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address[31:0] ), //o - .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data[31:0] ), //o - .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask[3:0] ), //o - .io_mem_cmd_payload_length (dataCache_1_io_mem_cmd_payload_length[2:0] ), //o - .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o - .io_mem_rsp_valid (dBus_rsp_valid ), //i - .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i - .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i - .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i - .clk (clk ), //i - .reset (reset ) //i + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i ); always @(*) begin - case(_zz_395) + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) + 2'b00 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) 2'b00 : begin - _zz_250 = DBusCachedPlugin_redoBranch_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; end 2'b01 : begin - _zz_250 = CsrPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; end 2'b10 : begin - _zz_250 = BranchPlugin_jumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; end default : begin - _zz_250 = IBusCachedPlugin_predictionJumpInterface_payload; + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; end endcase end @@ -1911,811 +2026,828 @@ module VexRiscv ( `ifndef SYNTHESIS always @(*) begin case(decode_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_1) - `Input2Kind_defaultEncoding_RS : _zz_1_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_1_string = "IMM_I"; - default : _zz_1_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_2) - `Input2Kind_defaultEncoding_RS : _zz_2_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_2_string = "IMM_I"; - default : _zz_2_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_3) - `Input2Kind_defaultEncoding_RS : _zz_3_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_3_string = "IMM_I"; - default : _zz_3_string = "?????"; + case(_zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_4) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_4_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_4_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_4_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_4_string = "ECALL"; - default : _zz_4_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_5) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_5_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_5_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_5_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_5_string = "ECALL"; - default : _zz_5_string = "?????"; + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_6) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_6_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_6_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_6_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_6_string = "ECALL"; - default : _zz_6_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_7) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_7_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_7_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_7_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_7_string = "ECALL"; - default : _zz_7_string = "?????"; + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; default : decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_8) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_8_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_8_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_8_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_8_string = "ECALL"; - default : _zz_8_string = "?????"; + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_9) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_9_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_9_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_9_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_9_string = "ECALL"; - default : _zz_9_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_10) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_10_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_10_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_10_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_10_string = "ECALL"; - default : _zz_10_string = "?????"; + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_11) - `BranchCtrlEnum_defaultEncoding_INC : _zz_11_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_11_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_11_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_11_string = "JALR"; - default : _zz_11_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_12) - `BranchCtrlEnum_defaultEncoding_INC : _zz_12_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_12_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_12_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_12_string = "JALR"; - default : _zz_12_string = "????"; + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_13) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_13_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_13_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_13_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_13_string = "SRA_1 "; - default : _zz_13_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_14) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_14_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_14_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_14_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_14_string = "SRA_1 "; - default : _zz_14_string = "?????????"; + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; default : decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_15) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_15_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_15_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_15_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_15_string = "SRA_1 "; - default : _zz_15_string = "?????????"; + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_16) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16_string = "SRA_1 "; - default : _zz_16_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_17) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17_string = "SRA_1 "; - default : _zz_17_string = "?????????"; + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin case(decode_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_18) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_18_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_18_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_18_string = "AND_1"; - default : _zz_18_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_19) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19_string = "AND_1"; - default : _zz_19_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_20) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20_string = "AND_1"; - default : _zz_20_string = "?????"; + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin case(decode_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; default : decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_21) - `Src2CtrlEnum_defaultEncoding_RS : _zz_21_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_21_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_21_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_21_string = "PC "; - default : _zz_21_string = "???"; + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_22) - `Src2CtrlEnum_defaultEncoding_RS : _zz_22_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_22_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_22_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_22_string = "PC "; - default : _zz_22_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_23) - `Src2CtrlEnum_defaultEncoding_RS : _zz_23_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_23_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_23_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_23_string = "PC "; - default : _zz_23_string = "???"; + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin case(decode_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; default : decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_24) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_24_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_24_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_24_string = "BITWISE "; - default : _zz_24_string = "????????"; + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_25) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_25_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_25_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_25_string = "BITWISE "; - default : _zz_25_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_26) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_26_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_26_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_26_string = "BITWISE "; - default : _zz_26_string = "????????"; + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin case(decode_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; default : decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_27) - `Src1CtrlEnum_defaultEncoding_RS : _zz_27_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_27_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_27_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_27_string = "URS1 "; - default : _zz_27_string = "????????????"; + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_28) - `Src1CtrlEnum_defaultEncoding_RS : _zz_28_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_28_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_28_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_28_string = "URS1 "; - default : _zz_28_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_29) - `Src1CtrlEnum_defaultEncoding_RS : _zz_29_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_29_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_29_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_29_string = "URS1 "; - default : _zz_29_string = "????????????"; + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin - case(_zz_32) - `Input2Kind_defaultEncoding_RS : _zz_32_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_32_string = "IMM_I"; - default : _zz_32_string = "?????"; + case(_zz_execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + default : _zz_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end always @(*) begin case(memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; default : memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_33) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_33_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_33_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_33_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_33_string = "ECALL"; - default : _zz_33_string = "?????"; + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; default : execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_34) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_34_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_34_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_34_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_34_string = "ECALL"; - default : _zz_34_string = "?????"; + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; default : writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_35) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_35_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_35_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_35_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_35_string = "ECALL"; - default : _zz_35_string = "?????"; + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; default : execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_36) - `BranchCtrlEnum_defaultEncoding_INC : _zz_36_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_36_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_36_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_36_string = "JALR"; - default : _zz_36_string = "????"; + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; default : memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_39) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_39_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_39_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_39_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_39_string = "SRA_1 "; - default : _zz_39_string = "?????????"; + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; default : execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin - case(_zz_40) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_40_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_40_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_40_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_40_string = "SRA_1 "; - default : _zz_40_string = "?????????"; + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; default : execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin - case(_zz_42) - `Src2CtrlEnum_defaultEncoding_RS : _zz_42_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_42_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_42_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_42_string = "PC "; - default : _zz_42_string = "???"; + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; default : execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin - case(_zz_43) - `Src1CtrlEnum_defaultEncoding_RS : _zz_43_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_43_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_43_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_43_string = "URS1 "; - default : _zz_43_string = "????????????"; + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; default : execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin - case(_zz_44) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_44_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_44_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_44_string = "BITWISE "; - default : _zz_44_string = "????????"; + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; default : execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_45) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45_string = "AND_1"; - default : _zz_45_string = "?????"; + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin - case(_zz_49) - `Input2Kind_defaultEncoding_RS : _zz_49_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_49_string = "IMM_I"; - default : _zz_49_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1_string = "?????"; endcase end always @(*) begin - case(_zz_50) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_50_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_50_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_50_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_50_string = "ECALL"; - default : _zz_50_string = "?????"; + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_51) - `BranchCtrlEnum_defaultEncoding_INC : _zz_51_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_51_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_51_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_51_string = "JALR"; - default : _zz_51_string = "????"; + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_52) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_52_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_52_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_52_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_52_string = "SRA_1 "; - default : _zz_52_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; endcase end always @(*) begin - case(_zz_53) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_53_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_53_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_53_string = "AND_1"; - default : _zz_53_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; endcase end always @(*) begin - case(_zz_54) - `Src2CtrlEnum_defaultEncoding_RS : _zz_54_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_54_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_54_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_54_string = "PC "; - default : _zz_54_string = "???"; + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; endcase end always @(*) begin - case(_zz_55) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_55_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_55_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_55_string = "BITWISE "; - default : _zz_55_string = "????????"; + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; endcase end always @(*) begin - case(_zz_56) - `Src1CtrlEnum_defaultEncoding_RS : _zz_56_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_56_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_56_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_56_string = "URS1 "; - default : _zz_56_string = "????????????"; + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; endcase end always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; default : decode_BRANCH_CTRL_string = "????"; endcase end always @(*) begin - case(_zz_58) - `BranchCtrlEnum_defaultEncoding_INC : _zz_58_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_58_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_58_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_58_string = "JALR"; - default : _zz_58_string = "????"; + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; endcase end always @(*) begin - case(_zz_100) - `Src1CtrlEnum_defaultEncoding_RS : _zz_100_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : _zz_100_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_100_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : _zz_100_string = "URS1 "; - default : _zz_100_string = "????????????"; + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; endcase end always @(*) begin - case(_zz_101) - `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_101_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_101_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : _zz_101_string = "BITWISE "; - default : _zz_101_string = "????????"; + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; endcase end always @(*) begin - case(_zz_102) - `Src2CtrlEnum_defaultEncoding_RS : _zz_102_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : _zz_102_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : _zz_102_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : _zz_102_string = "PC "; - default : _zz_102_string = "???"; + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; endcase end always @(*) begin - case(_zz_103) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_103_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_103_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_103_string = "AND_1"; - default : _zz_103_string = "?????"; + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_104) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_104_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_104_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_104_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_104_string = "SRA_1 "; - default : _zz_104_string = "?????????"; + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; endcase end always @(*) begin - case(_zz_105) - `BranchCtrlEnum_defaultEncoding_INC : _zz_105_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : _zz_105_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : _zz_105_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : _zz_105_string = "JALR"; - default : _zz_105_string = "????"; + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; endcase end always @(*) begin - case(_zz_106) - `EnvCtrlEnum_defaultEncoding_NONE : _zz_106_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : _zz_106_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : _zz_106_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : _zz_106_string = "ECALL"; - default : _zz_106_string = "?????"; + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; endcase end always @(*) begin - case(_zz_107) - `Input2Kind_defaultEncoding_RS : _zz_107_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : _zz_107_string = "IMM_I"; - default : _zz_107_string = "?????"; + case(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8) + `Input2Kind_binary_sequential_RS : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "IMM_I"; + default : _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; - `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; - `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; default : decode_to_execute_SRC1_CTRL_string = "????????????"; endcase end always @(*) begin case(decode_to_execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; - `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; - `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; default : decode_to_execute_ALU_CTRL_string = "????????"; endcase end always @(*) begin case(decode_to_execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; - `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; - `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; - `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; default : decode_to_execute_SRC2_CTRL_string = "???"; endcase end always @(*) begin case(decode_to_execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; default : decode_to_execute_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(execute_to_memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; - `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; - `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; default : execute_to_memory_SHIFT_CTRL_string = "?????????"; endcase end always @(*) begin case(decode_to_execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; - `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; - `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; - `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; default : decode_to_execute_BRANCH_CTRL_string = "????"; endcase end always @(*) begin case(decode_to_execute_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; default : decode_to_execute_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(execute_to_memory_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; default : execute_to_memory_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(memory_to_writeBack_ENV_CTRL) - `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; - `EnvCtrlEnum_defaultEncoding_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; - `EnvCtrlEnum_defaultEncoding_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; - `EnvCtrlEnum_defaultEncoding_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; default : memory_to_writeBack_ENV_CTRL_string = "?????"; endcase end always @(*) begin case(decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; - `Input2Kind_defaultEncoding_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; + `Input2Kind_binary_sequential_RS : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "RS "; + `Input2Kind_binary_sequential_IMM_I : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "IMM_I"; default : decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_string = "?????"; endcase end `endif - assign memory_MUL_LOW = ($signed(_zz_294) + $signed(_zz_302)); + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); assign memory_MUL_HH = execute_to_memory_MUL_HH; assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); - assign writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_IN_FLIGHT = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) || execute_CfuPlugin_fired); - assign execute_SHIFT_RIGHT = _zz_304; - assign execute_REGFILE_WRITE_DATA = _zz_109; - assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; - assign execute_MEMORY_ADDRESS_LOW = _zz_230[1 : 0]; + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; assign decode_DO_EBREAK = (((! DebugPlugin_haltIt) && (decode_IS_EBREAK || 1'b0)) && DebugPlugin_allowEBreak); assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); - assign decode_IS_RS2_SIGNED = _zz_306[0]; - assign decode_IS_RS1_SIGNED = _zz_307[0]; - assign decode_IS_DIV = _zz_308[0]; + assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1; + assign decode_CfuPlugin_CFU_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[33]; + assign decode_IS_RS2_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[30]; + assign decode_IS_DIV = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[29]; assign memory_IS_MUL = execute_to_memory_IS_MUL; assign execute_IS_MUL = decode_to_execute_IS_MUL; - assign decode_IS_MUL = _zz_309[0]; - assign decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_1; - assign _zz_2 = _zz_3; - assign decode_CfuPlugin_CFU_ENABLE = _zz_310[0]; - assign _zz_4 = _zz_5; - assign _zz_6 = _zz_7; - assign decode_ENV_CTRL = _zz_8; - assign _zz_9 = _zz_10; - assign decode_IS_CSR = _zz_311[0]; - assign _zz_11 = _zz_12; - assign _zz_13 = _zz_14; - assign decode_SHIFT_CTRL = _zz_15; - assign _zz_16 = _zz_17; - assign decode_ALU_BITWISE_CTRL = _zz_18; - assign _zz_19 = _zz_20; - assign decode_SRC_LESS_UNSIGNED = _zz_312[0]; - assign decode_MEMORY_MANAGMENT = _zz_313[0]; + assign decode_IS_MUL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[16]; assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; - assign decode_MEMORY_WR = _zz_314[0]; + assign decode_MEMORY_WR = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[13]; assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; - assign decode_BYPASSABLE_MEMORY_STAGE = _zz_315[0]; - assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_316[0]; - assign decode_SRC2_CTRL = _zz_21; - assign _zz_22 = _zz_23; - assign decode_ALU_CTRL = _zz_24; - assign _zz_25 = _zz_26; - assign decode_SRC1_CTRL = _zz_27; - assign _zz_28 = _zz_29; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); assign memory_PC = execute_to_memory_PC; + always @(*) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = memory_CfuPlugin_CFU_IN_FLIGHT; + if(memory_arbitration_isStuck) begin + _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + always @(*) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = execute_CfuPlugin_CFU_IN_FLIGHT; + if(execute_arbitration_isStuck) begin + _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT = 1'b0; + end + end + + assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; + assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_DO_EBREAK = decode_to_execute_DO_EBREAK; - assign decode_IS_EBREAK = _zz_317[0]; + assign decode_IS_EBREAK = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[32]; assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; assign execute_IS_DIV = decode_to_execute_IS_DIV; assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; @@ -2726,42 +2858,25 @@ module VexRiscv ( assign memory_MUL_HL = execute_to_memory_MUL_HL; assign memory_MUL_LH = execute_to_memory_MUL_LH; assign memory_MUL_LL = execute_to_memory_MUL_LL; - always @ (*) begin - _zz_30 = memory_CfuPlugin_CFU_IN_FLIGHT; - if(memory_arbitration_isStuck)begin - _zz_30 = 1'b0; - end - end - - always @ (*) begin - _zz_31 = execute_CfuPlugin_CFU_IN_FLIGHT; - if(execute_arbitration_isStuck)begin - _zz_31 = 1'b0; - end - end - - assign memory_CfuPlugin_CFU_IN_FLIGHT = execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; - assign execute_CfuPlugin_CFU_INPUT_2_KIND = _zz_32; - assign execute_CfuPlugin_CFU_ENABLE = decode_to_execute_CfuPlugin_CFU_ENABLE; assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; assign execute_IS_CSR = decode_to_execute_IS_CSR; - assign memory_ENV_CTRL = _zz_33; - assign execute_ENV_CTRL = _zz_34; - assign writeBack_ENV_CTRL = _zz_35; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); assign execute_PC = decode_to_execute_PC; assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; assign execute_RS1 = decode_to_execute_RS1; - assign execute_BRANCH_COND_RESULT = _zz_131; - assign execute_BRANCH_CTRL = _zz_36; - assign decode_RS2_USE = _zz_318[0]; - assign decode_RS1_USE = _zz_319[0]; - always @ (*) begin - _zz_37 = execute_REGFILE_WRITE_DATA; - if(_zz_251)begin - _zz_37 = execute_CsrPlugin_readData; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[15]; + assign decode_RS1_USE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; end end @@ -2771,142 +2886,142 @@ module VexRiscv ( assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; - always @ (*) begin + always @(*) begin decode_RS2 = decode_RegFilePlugin_rs2Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[24 : 20]))begin - decode_RS2 = _zz_122; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_252)begin - if(_zz_253)begin - if(_zz_124)begin - decode_RS2 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; end end end - if(_zz_254)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_126)begin - decode_RS2 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; end end end - if(_zz_255)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_128)begin - decode_RS2 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; end end end end - always @ (*) begin + always @(*) begin decode_RS1 = decode_RegFilePlugin_rs1Data; - if(_zz_120)begin - if((_zz_121 == decode_INSTRUCTION[19 : 15]))begin - decode_RS1 = _zz_122; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; end end - if(_zz_252)begin - if(_zz_253)begin - if(_zz_123)begin - decode_RS1 = _zz_57; + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; end end end - if(_zz_254)begin - if(memory_BYPASSABLE_MEMORY_STAGE)begin - if(_zz_125)begin - decode_RS1 = _zz_38; + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; end end end - if(_zz_255)begin - if(execute_BYPASSABLE_EXECUTE_STAGE)begin - if(_zz_127)begin - decode_RS1 = _zz_37; + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; end end end end assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; - always @ (*) begin - _zz_38 = memory_REGFILE_WRITE_DATA; - if(memory_arbitration_isValid)begin + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin case(memory_SHIFT_CTRL) - `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin - _zz_38 = _zz_117; + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; end - `ShiftCtrlEnum_defaultEncoding_SRL_1, `ShiftCtrlEnum_defaultEncoding_SRA_1 : begin - _zz_38 = memory_SHIFT_RIGHT; + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; end default : begin end endcase end - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - _zz_38 = memory_CfuPlugin_rsp_payload_outputs_0; + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; end - if(_zz_256)begin - _zz_38 = memory_DivPlugin_div_result; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + _zz_decode_RS2_1 = CfuPlugin_bus_rsp_rsp_payload_outputs_0; end end - assign memory_SHIFT_CTRL = _zz_39; - assign execute_SHIFT_CTRL = _zz_40; + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; - assign _zz_41 = execute_PC; - assign execute_SRC2_CTRL = _zz_42; - assign execute_SRC1_CTRL = _zz_43; - assign decode_SRC_USE_SUB_LESS = _zz_320[0]; - assign decode_SRC_ADD_ZERO = _zz_321[0]; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[20]; assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; assign execute_SRC_LESS = execute_SrcPlugin_less; - assign execute_ALU_CTRL = _zz_44; - assign execute_SRC2 = _zz_115; - assign execute_SRC1 = _zz_110; - assign execute_ALU_BITWISE_CTRL = _zz_45; - assign _zz_46 = writeBack_INSTRUCTION; - assign _zz_47 = writeBack_REGFILE_WRITE_VALID; - always @ (*) begin - _zz_48 = 1'b0; - if(lastStageRegFileWrite_valid)begin - _zz_48 = 1'b1; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; end end assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); - always @ (*) begin - decode_REGFILE_WRITE_VALID = _zz_322[0]; - if((decode_INSTRUCTION[11 : 7] == 5'h0))begin + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[10]; + if(when_RegFilePlugin_l63) begin decode_REGFILE_WRITE_VALID = 1'b0; end end - assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_396) == 32'h00000003),{(_zz_397 == _zz_398),{_zz_399,{_zz_400,_zz_401}}}}}}} != 22'h0); - always @ (*) begin - _zz_57 = writeBack_REGFILE_WRITE_DATA; - if((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE))begin - _zz_57 = writeBack_DBusCachedPlugin_rspFormated; + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000000b),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 22'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; end - if((writeBack_arbitration_isValid && writeBack_IS_MUL))begin - case(_zz_293) + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) 2'b00 : begin - _zz_57 = _zz_368; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; end default : begin - _zz_57 = _zz_369; + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; end endcase end end - assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; @@ -2918,61 +3033,61 @@ module VexRiscv ( assign execute_SRC_ADD = execute_SrcPlugin_addSub; assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; - assign decode_MEMORY_ENABLE = _zz_323[0]; - assign decode_FLUSH_ALL = _zz_324[0]; - always @ (*) begin + assign decode_MEMORY_ENABLE = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[4]; + assign decode_FLUSH_ALL = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[0]; + always @(*) begin IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; - if(_zz_257)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; - if(_zz_258)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; - if(_zz_259)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; - if(_zz_260)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; end end - assign decode_BRANCH_CTRL = _zz_58; + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; - always @ (*) begin - _zz_59 = execute_FORMAL_PC_NEXT; - if(BranchPlugin_jumpInterface_valid)begin - _zz_59 = BranchPlugin_jumpInterface_payload; + always @(*) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = execute_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_execute_to_memory_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; end end - always @ (*) begin - _zz_60 = decode_FORMAL_PC_NEXT; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin - _zz_60 = IBusCachedPlugin_predictionJumpInterface_payload; + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; end end assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; assign writeBack_PC = memory_to_writeBack_PC; assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; - always @ (*) begin + always @(*) begin decode_arbitration_haltItself = 1'b0; - if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + if(when_DBusCachedPlugin_l303) begin decode_arbitration_haltItself = 1'b1; end - case(_zz_179) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_haltItself = 1'b1; end @@ -2981,174 +3096,165 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin decode_arbitration_haltByOther = 1'b0; - if((decode_arbitration_isValid && (_zz_118 || _zz_119)))begin + if(when_HazardSimplePlugin_l113) begin decode_arbitration_haltByOther = 1'b1; end - if(CsrPlugin_pipelineLiberator_active)begin + if(CsrPlugin_pipelineLiberator_active) begin decode_arbitration_haltByOther = 1'b1; end - if(({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET))}} != 3'b000))begin + if(when_CsrPlugin_l1116) begin decode_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin decode_arbitration_removeIt = 1'b0; - if(_zz_261)begin + if(_zz_when) begin decode_arbitration_removeIt = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin decode_arbitration_removeIt = 1'b1; end end assign decode_arbitration_flushIt = 1'b0; - always @ (*) begin + always @(*) begin decode_arbitration_flushNext = 1'b0; - if(IBusCachedPlugin_predictionJumpInterface_valid)begin + if(IBusCachedPlugin_predictionJumpInterface_valid) begin decode_arbitration_flushNext = 1'b1; end - if(_zz_261)begin + if(_zz_when) begin decode_arbitration_flushNext = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltItself = 1'b0; - if(((_zz_246 && (! dataCache_1_io_cpu_flush_ready)) || dataCache_1_io_cpu_execute_haltIt))begin + if(when_DBusCachedPlugin_l343) begin execute_arbitration_haltItself = 1'b1; end - if(_zz_262)begin - if((! execute_CsrPlugin_wfiWake))begin + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin execute_arbitration_haltItself = 1'b1; end end - if(_zz_251)begin - if(execute_CsrPlugin_blockedBySideEffects)begin + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin execute_arbitration_haltItself = 1'b1; end end - if((CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)))begin + if(when_CfuPlugin_l175) begin execute_arbitration_haltItself = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_haltByOther = 1'b0; - if((dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid))begin + if(when_DBusCachedPlugin_l359) begin execute_arbitration_haltByOther = 1'b1; end - if(_zz_263)begin + if(when_DebugPlugin_l284) begin execute_arbitration_haltByOther = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_removeIt = 1'b0; - if(_zz_264)begin + if(_zz_when_1) begin execute_arbitration_removeIt = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin execute_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin execute_arbitration_flushIt = 1'b0; - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushIt = 1'b1; end end end - always @ (*) begin + always @(*) begin execute_arbitration_flushNext = 1'b0; - if(BranchPlugin_jumpInterface_valid)begin + if(BranchPlugin_jumpInterface_valid) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_264)begin + if(_zz_when_1) begin execute_arbitration_flushNext = 1'b1; end - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin execute_arbitration_flushNext = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_arbitration_haltItself = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if((! memory_CfuPlugin_rsp_valid))begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin memory_arbitration_haltItself = 1'b1; end end - if(_zz_256)begin - if(((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)))begin + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + if(when_CfuPlugin_l208) begin memory_arbitration_haltItself = 1'b1; end end end assign memory_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin memory_arbitration_removeIt = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_removeIt = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin memory_arbitration_removeIt = 1'b1; end end assign memory_arbitration_flushIt = 1'b0; - always @ (*) begin - memory_arbitration_flushNext = 1'b0; - if(CfuPlugin_joinException_valid)begin - memory_arbitration_flushNext = 1'b1; - end - end - - always @ (*) begin + assign memory_arbitration_flushNext = 1'b0; + always @(*) begin writeBack_arbitration_haltItself = 1'b0; - if(dataCache_1_io_cpu_writeBack_haltIt)begin + if(when_DBusCachedPlugin_l458) begin writeBack_arbitration_haltItself = 1'b1; end end assign writeBack_arbitration_haltByOther = 1'b0; - always @ (*) begin + always @(*) begin writeBack_arbitration_removeIt = 1'b0; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_removeIt = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin writeBack_arbitration_removeIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushIt = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushIt = 1'b1; end end - always @ (*) begin + always @(*) begin writeBack_arbitration_flushNext = 1'b0; - if(DBusCachedPlugin_redoBranch_valid)begin + if(DBusCachedPlugin_redoBranch_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin writeBack_arbitration_flushNext = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin writeBack_arbitration_flushNext = 1'b1; end end @@ -3157,75 +3263,77 @@ module VexRiscv ( assign lastStagePc = writeBack_PC; assign lastStageIsValid = writeBack_arbitration_isValid; assign lastStageIsFiring = writeBack_arbitration_isFiring; - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetcherHalt = 1'b0; - if(({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000))begin + if(when_CsrPlugin_l922) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin IBusCachedPlugin_fetcherHalt = 1'b1; end - if(_zz_268)begin + if(when_DebugPlugin_l300) begin IBusCachedPlugin_fetcherHalt = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_incomingInstruction = 1'b0; - if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + if(when_Fetcher_l240) begin IBusCachedPlugin_incomingInstruction = 1'b1; end end - always @ (*) begin - _zz_61 = 1'b0; - if(DebugPlugin_godmode)begin - _zz_61 = 1'b1; + always @(*) begin + _zz_when_DBusCachedPlugin_l386 = 1'b0; + if(DebugPlugin_godmode) begin + _zz_when_DBusCachedPlugin_l386 = 1'b1; end end - always @ (*) begin + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin CsrPlugin_inWfi = 1'b0; - if(_zz_262)begin + if(when_CsrPlugin_l1108) begin CsrPlugin_inWfi = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_thirdPartyWake = 1'b0; - if(DebugPlugin_haltIt)begin + if(DebugPlugin_haltIt) begin CsrPlugin_thirdPartyWake = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_jumpInterface_valid = 1'b0; - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_valid = 1'b1; end - if(_zz_267)begin + if(when_CsrPlugin_l1064) begin CsrPlugin_jumpInterface_valid = 1'b1; end end - always @ (*) begin - CsrPlugin_jumpInterface_payload = 32'h0; - if(_zz_266)begin + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; end - if(_zz_267)begin - case(_zz_269) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; end @@ -3235,80 +3343,92 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin CsrPlugin_forceMachineWire = 1'b0; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_forceMachineWire = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowInterrupts = 1'b1; - if((DebugPlugin_haltIt || DebugPlugin_stepIt))begin + if(when_DebugPlugin_l316) begin CsrPlugin_allowInterrupts = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_allowException = 1'b1; - if(DebugPlugin_godmode)begin + if(DebugPlugin_godmode) begin CsrPlugin_allowException = 1'b0; end end + always @(*) begin + CsrPlugin_allowEbreakException = 1'b1; + if(DebugPlugin_allowEBreak) begin + CsrPlugin_allowEbreakException = 1'b0; + end + end + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); - assign _zz_62 = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; - assign _zz_63 = (_zz_62 & (~ _zz_325)); - assign _zz_64 = _zz_63[3]; - assign _zz_65 = (_zz_63[1] || _zz_64); - assign _zz_66 = (_zz_63[2] || _zz_64); - assign IBusCachedPlugin_jump_pcLoad_payload = _zz_250; - always @ (*) begin + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin IBusCachedPlugin_fetchPc_correction = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_correction = 1'b1; end end + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; end end - always @ (*) begin - IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_327); - if(IBusCachedPlugin_fetchPc_redo_valid)begin + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; end IBusCachedPlugin_fetchPc_pc[0] = 1'b0; IBusCachedPlugin_fetchPc_pc[1] = 1'b0; end - always @ (*) begin + always @(*) begin IBusCachedPlugin_fetchPc_flushed = 1'b0; - if(IBusCachedPlugin_fetchPc_redo_valid)begin + if(IBusCachedPlugin_fetchPc_redo_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end - if(IBusCachedPlugin_jump_pcLoad_valid)begin + if(IBusCachedPlugin_jump_pcLoad_valid) begin IBusCachedPlugin_fetchPc_flushed = 1'b1; end end + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; - if(IBusCachedPlugin_rsp_redoFetch)begin + if(IBusCachedPlugin_rsp_redoFetch) begin IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; end end @@ -3316,66 +3436,75 @@ module VexRiscv ( assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; - if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; end end - assign _zz_67 = (! IBusCachedPlugin_iBusRsp_stages_0_halt); - assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_67); - assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_67); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; - if(IBusCachedPlugin_mmuBus_busy)begin + if(IBusCachedPlugin_mmuBus_busy) begin IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; end end - assign _zz_68 = (! IBusCachedPlugin_iBusRsp_stages_1_halt); - assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_68); - assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_68); + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; - always @ (*) begin + always @(*) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; - if((IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + if(when_IBusCachedPlugin_l267) begin IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; end end - assign _zz_69 = (! IBusCachedPlugin_iBusRsp_stages_2_halt); - assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_69); - assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_69); + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); - assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_70; - assign _zz_70 = ((1'b0 && (! _zz_71)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign _zz_71 = _zz_72; - assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_71; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; - assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_73)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_73 = _zz_74; - assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_73; - assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_75; - always @ (*) begin + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b1; - if((! IBusCachedPlugin_pcValids_0))begin + if(when_Fetcher_l320) begin IBusCachedPlugin_iBusRsp_readyForError = 1'b0; end end + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); - always @ (*) begin + always @(*) begin decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; - case(_zz_179) + case(switch_Fetcher_l362) 3'b010 : begin decode_arbitration_isValid = 1'b1; end @@ -3387,207 +3516,219 @@ module VexRiscv ( endcase end - assign _zz_76 = _zz_328[11]; - always @ (*) begin - _zz_77[18] = _zz_76; - _zz_77[17] = _zz_76; - _zz_77[16] = _zz_76; - _zz_77[15] = _zz_76; - _zz_77[14] = _zz_76; - _zz_77[13] = _zz_76; - _zz_77[12] = _zz_76; - _zz_77[11] = _zz_76; - _zz_77[10] = _zz_76; - _zz_77[9] = _zz_76; - _zz_77[8] = _zz_76; - _zz_77[7] = _zz_76; - _zz_77[6] = _zz_76; - _zz_77[5] = _zz_76; - _zz_77[4] = _zz_76; - _zz_77[3] = _zz_76; - _zz_77[2] = _zz_76; - _zz_77[1] = _zz_76; - _zz_77[0] = _zz_76; - end - - always @ (*) begin - IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_B) && _zz_329[31])); - if(_zz_82)begin + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; end end - assign _zz_78 = _zz_330[19]; - always @ (*) begin - _zz_79[10] = _zz_78; - _zz_79[9] = _zz_78; - _zz_79[8] = _zz_78; - _zz_79[7] = _zz_78; - _zz_79[6] = _zz_78; - _zz_79[5] = _zz_78; - _zz_79[4] = _zz_78; - _zz_79[3] = _zz_78; - _zz_79[2] = _zz_78; - _zz_79[1] = _zz_78; - _zz_79[0] = _zz_78; - end - - assign _zz_80 = _zz_331[11]; - always @ (*) begin - _zz_81[18] = _zz_80; - _zz_81[17] = _zz_80; - _zz_81[16] = _zz_80; - _zz_81[15] = _zz_80; - _zz_81[14] = _zz_80; - _zz_81[13] = _zz_80; - _zz_81[12] = _zz_80; - _zz_81[11] = _zz_80; - _zz_81[10] = _zz_80; - _zz_81[9] = _zz_80; - _zz_81[8] = _zz_80; - _zz_81[7] = _zz_80; - _zz_81[6] = _zz_80; - _zz_81[5] = _zz_80; - _zz_81[4] = _zz_80; - _zz_81[3] = _zz_80; - _zz_81[2] = _zz_80; - _zz_81[1] = _zz_80; - _zz_81[0] = _zz_80; - end - - always @ (*) begin + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin case(decode_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_82 = _zz_332[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; end default : begin - _zz_82 = _zz_333[1]; + _zz_6 = _zz__zz_6_1[1]; end endcase end assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); - assign _zz_83 = _zz_334[19]; - always @ (*) begin - _zz_84[10] = _zz_83; - _zz_84[9] = _zz_83; - _zz_84[8] = _zz_83; - _zz_84[7] = _zz_83; - _zz_84[6] = _zz_83; - _zz_84[5] = _zz_83; - _zz_84[4] = _zz_83; - _zz_84[3] = _zz_83; - _zz_84[2] = _zz_83; - _zz_84[1] = _zz_83; - _zz_84[0] = _zz_83; - end - - assign _zz_85 = _zz_335[11]; - always @ (*) begin - _zz_86[18] = _zz_85; - _zz_86[17] = _zz_85; - _zz_86[16] = _zz_85; - _zz_86[15] = _zz_85; - _zz_86[14] = _zz_85; - _zz_86[13] = _zz_85; - _zz_86[12] = _zz_85; - _zz_86[11] = _zz_85; - _zz_86[10] = _zz_85; - _zz_86[9] = _zz_85; - _zz_86[8] = _zz_85; - _zz_86[7] = _zz_85; - _zz_86[6] = _zz_85; - _zz_86[5] = _zz_85; - _zz_86[4] = _zz_85; - _zz_86[3] = _zz_85; - _zz_86[2] = _zz_85; - _zz_86[1] = _zz_85; - _zz_86[0] = _zz_85; - end - - assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_84,{{{_zz_414,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_86,{{{_zz_415,_zz_416},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; - always @ (*) begin + always @(*) begin iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; end assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; - assign _zz_221 = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); - assign _zz_222 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); - assign _zz_223 = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); - assign IBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_222; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); - assign _zz_225 = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); - assign _zz_226 = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); - assign _zz_227 = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; assign IBusCachedPlugin_rsp_issueDetected = 1'b0; - always @ (*) begin + always @(*) begin IBusCachedPlugin_rsp_redoFetch = 1'b0; - if(_zz_260)begin + if(when_IBusCachedPlugin_l239) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end - if(_zz_258)begin + if(when_IBusCachedPlugin_l250) begin IBusCachedPlugin_rsp_redoFetch = 1'b1; end end - always @ (*) begin - _zz_228 = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); - if(_zz_258)begin - _zz_228 = 1'b1; + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; - if(_zz_259)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end - if(_zz_257)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; end end - always @ (*) begin + always @(*) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; - if(_zz_259)begin + if(when_IBusCachedPlugin_l244) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; end - if(_zz_257)begin + if(when_IBusCachedPlugin_l256) begin IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; end end assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; - assign _zz_220 = (decode_arbitration_isValid && decode_FLUSH_ALL); - assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign _zz_247 = (! dataCache_1_io_mem_cmd_s2mPipe_rValid); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_wr : dataCache_1_io_mem_cmd_payload_wr); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_address : dataCache_1_io_mem_cmd_payload_address); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_data : dataCache_1_io_mem_cmd_payload_data); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_mask : dataCache_1_io_mem_cmd_payload_mask); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_length = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_length : dataCache_1_io_mem_cmd_payload_length); - assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_s2mPipe_rValid ? dataCache_1_io_mem_cmd_s2mPipe_rData_last : dataCache_1_io_mem_cmd_payload_last); - assign dataCache_1_io_mem_cmd_s2mPipe_ready = ((1'b1 && (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid)) || dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready); - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length; - assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; @@ -3595,168 +3736,179 @@ module VexRiscv ( assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; - assign dBus_cmd_payload_length = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_length; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; - assign _zz_229 = (execute_arbitration_isValid && execute_MEMORY_ENABLE); - assign _zz_230 = execute_SRC_ADD; - always @ (*) begin + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin case(execute_DBusCachedPlugin_size) 2'b00 : begin - _zz_89 = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; end 2'b01 : begin - _zz_89 = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; end default : begin - _zz_89 = execute_RS2[31 : 0]; + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; end endcase end - assign _zz_246 = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); - assign _zz_231 = (memory_arbitration_isValid && memory_MEMORY_ENABLE); - assign _zz_232 = memory_REGFILE_WRITE_DATA; - assign DBusCachedPlugin_mmuBus_cmd_0_isValid = _zz_231; + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; - assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = _zz_232; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); - always @ (*) begin - _zz_233 = DBusCachedPlugin_mmuBus_rsp_isIoAccess; - if((_zz_61 && (! dataCache_1_io_cpu_memory_isWrite)))begin - _zz_233 = 1'b1; + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; end end - assign _zz_234 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); - assign _zz_235 = (CsrPlugin_privilege == 2'b00); - assign _zz_236 = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + assign when_DBusCachedPlugin_l386 = (_zz_when_DBusCachedPlugin_l386 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin DBusCachedPlugin_redoBranch_valid = 1'b0; - if(_zz_270)begin - if(dataCache_1_io_cpu_redo)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_redoBranch_valid = 1'b1; end end end assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; - if(_zz_270)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin DBusCachedPlugin_exceptionBus_valid = 1'b1; end - if(dataCache_1_io_cpu_redo)begin + if(dataCache_1_io_cpu_redo) begin DBusCachedPlugin_exceptionBus_valid = 1'b0; end end end assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; - always @ (*) begin + always @(*) begin DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; - if(_zz_270)begin - if(dataCache_1_io_cpu_writeBack_accessError)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_336}; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; end - if(dataCache_1_io_cpu_writeBack_mmuException)begin + if(dataCache_1_io_cpu_writeBack_mmuException) begin DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); end - if(dataCache_1_io_cpu_writeBack_unalignedAccess)begin - DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_337}; + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; end end end - always @ (*) begin - writeBack_DBusCachedPlugin_rspShifted = dataCache_1_io_cpu_writeBack_data; - case(writeBack_MEMORY_ADDRESS_LOW) - 2'b01 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[15 : 8]; - end - 2'b10 : begin - writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 16]; - end - 2'b11 : begin - writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1_io_cpu_writeBack_data[31 : 24]; - end - default : begin - end - endcase + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; end - assign _zz_90 = (writeBack_DBusCachedPlugin_rspShifted[7] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_91[31] = _zz_90; - _zz_91[30] = _zz_90; - _zz_91[29] = _zz_90; - _zz_91[28] = _zz_90; - _zz_91[27] = _zz_90; - _zz_91[26] = _zz_90; - _zz_91[25] = _zz_90; - _zz_91[24] = _zz_90; - _zz_91[23] = _zz_90; - _zz_91[22] = _zz_90; - _zz_91[21] = _zz_90; - _zz_91[20] = _zz_90; - _zz_91[19] = _zz_90; - _zz_91[18] = _zz_90; - _zz_91[17] = _zz_90; - _zz_91[16] = _zz_90; - _zz_91[15] = _zz_90; - _zz_91[14] = _zz_90; - _zz_91[13] = _zz_90; - _zz_91[12] = _zz_90; - _zz_91[11] = _zz_90; - _zz_91[10] = _zz_90; - _zz_91[9] = _zz_90; - _zz_91[8] = _zz_90; - _zz_91[7 : 0] = writeBack_DBusCachedPlugin_rspShifted[7 : 0]; - end - - assign _zz_92 = (writeBack_DBusCachedPlugin_rspShifted[15] && (! writeBack_INSTRUCTION[14])); - always @ (*) begin - _zz_93[31] = _zz_92; - _zz_93[30] = _zz_92; - _zz_93[29] = _zz_92; - _zz_93[28] = _zz_92; - _zz_93[27] = _zz_92; - _zz_93[26] = _zz_92; - _zz_93[25] = _zz_92; - _zz_93[24] = _zz_92; - _zz_93[23] = _zz_92; - _zz_93[22] = _zz_92; - _zz_93[21] = _zz_92; - _zz_93[20] = _zz_92; - _zz_93[19] = _zz_92; - _zz_93[18] = _zz_92; - _zz_93[17] = _zz_92; - _zz_93[16] = _zz_92; - _zz_93[15 : 0] = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; - end - - always @ (*) begin - case(_zz_291) + always @(*) begin + case(switch_Misc_l200) 2'b00 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_91; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; end 2'b01 : begin - writeBack_DBusCachedPlugin_rspFormated = _zz_93; + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; end default : begin - writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; end endcase end + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; @@ -3775,62 +3927,63 @@ module VexRiscv ( assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; assign DBusCachedPlugin_mmuBus_busy = 1'b0; - assign _zz_95 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); - assign _zz_96 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); - assign _zz_97 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); - assign _zz_98 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); - assign _zz_99 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); - assign _zz_94 = {(((decode_INSTRUCTION & _zz_417) == 32'h00100050) != 1'b0),{(_zz_99 != 1'b0),{(_zz_99 != 1'b0),{(_zz_418 != _zz_419),{_zz_420,{_zz_421,_zz_422}}}}}}; - assign _zz_100 = _zz_94[2 : 1]; - assign _zz_56 = _zz_100; - assign _zz_101 = _zz_94[7 : 6]; - assign _zz_55 = _zz_101; - assign _zz_102 = _zz_94[9 : 8]; - assign _zz_54 = _zz_102; - assign _zz_103 = _zz_94[19 : 18]; - assign _zz_53 = _zz_103; - assign _zz_104 = _zz_94[22 : 21]; - assign _zz_52 = _zz_104; - assign _zz_105 = _zz_94[24 : 23]; - assign _zz_51 = _zz_105; - assign _zz_106 = _zz_94[27 : 26]; - assign _zz_50 = _zz_106; - assign _zz_107 = _zz_94[29 : 29]; - assign _zz_49 = _zz_107; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_3 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_4 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_5 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 = ((decode_INSTRUCTION & 32'h0000000c) == 32'h00000008); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 = {1'b0,{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_6 != 1'b0),{((_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2 == _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_1) != 1'b0),{(_zz_decode_CfuPlugin_CFU_INPUT_2_KIND_7 != 1'b0),{(_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_2 != _zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_3),{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_4,{_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_5,_zz__zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2_7}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_2[34 : 34]; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1 = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_8; assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); assign decodeExceptionPort_payload_code = 4'b0010; assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; - assign decode_RegFilePlugin_rs1Data = _zz_248; - assign decode_RegFilePlugin_rs2Data = _zz_249; - always @ (*) begin - lastStageRegFileWrite_valid = (_zz_47 && writeBack_arbitration_isFiring); - if(_zz_108)begin + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin lastStageRegFileWrite_valid = 1'b1; end end - always @ (*) begin - lastStageRegFileWrite_payload_address = _zz_46[11 : 7]; - if(_zz_108)begin + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin lastStageRegFileWrite_payload_address = 5'h0; end end - always @ (*) begin - lastStageRegFileWrite_payload_data = _zz_57; - if(_zz_108)begin + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin lastStageRegFileWrite_payload_data = 32'h0; end end - always @ (*) begin + always @(*) begin case(execute_ALU_BITWISE_CTRL) - `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); end - `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); end default : begin @@ -3839,355 +3992,378 @@ module VexRiscv ( endcase end - always @ (*) begin + always @(*) begin case(execute_ALU_CTRL) - `AluCtrlEnum_defaultEncoding_BITWISE : begin - _zz_109 = execute_IntAluPlugin_bitwise; + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; end - `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin - _zz_109 = {31'd0, _zz_338}; + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; end default : begin - _zz_109 = execute_SRC_ADD_SUB; + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; end endcase end - always @ (*) begin + always @(*) begin case(execute_SRC1_CTRL) - `Src1CtrlEnum_defaultEncoding_RS : begin - _zz_110 = execute_RS1; + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; end - `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin - _zz_110 = {29'd0, _zz_339}; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; end - `Src1CtrlEnum_defaultEncoding_IMU : begin - _zz_110 = {execute_INSTRUCTION[31 : 12],12'h0}; + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; end default : begin - _zz_110 = {27'd0, _zz_340}; + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; end endcase end - assign _zz_111 = _zz_341[11]; - always @ (*) begin - _zz_112[19] = _zz_111; - _zz_112[18] = _zz_111; - _zz_112[17] = _zz_111; - _zz_112[16] = _zz_111; - _zz_112[15] = _zz_111; - _zz_112[14] = _zz_111; - _zz_112[13] = _zz_111; - _zz_112[12] = _zz_111; - _zz_112[11] = _zz_111; - _zz_112[10] = _zz_111; - _zz_112[9] = _zz_111; - _zz_112[8] = _zz_111; - _zz_112[7] = _zz_111; - _zz_112[6] = _zz_111; - _zz_112[5] = _zz_111; - _zz_112[4] = _zz_111; - _zz_112[3] = _zz_111; - _zz_112[2] = _zz_111; - _zz_112[1] = _zz_111; - _zz_112[0] = _zz_111; - end - - assign _zz_113 = _zz_342[11]; - always @ (*) begin - _zz_114[19] = _zz_113; - _zz_114[18] = _zz_113; - _zz_114[17] = _zz_113; - _zz_114[16] = _zz_113; - _zz_114[15] = _zz_113; - _zz_114[14] = _zz_113; - _zz_114[13] = _zz_113; - _zz_114[12] = _zz_113; - _zz_114[11] = _zz_113; - _zz_114[10] = _zz_113; - _zz_114[9] = _zz_113; - _zz_114[8] = _zz_113; - _zz_114[7] = _zz_113; - _zz_114[6] = _zz_113; - _zz_114[5] = _zz_113; - _zz_114[4] = _zz_113; - _zz_114[3] = _zz_113; - _zz_114[2] = _zz_113; - _zz_114[1] = _zz_113; - _zz_114[0] = _zz_113; - end - - always @ (*) begin + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin case(execute_SRC2_CTRL) - `Src2CtrlEnum_defaultEncoding_RS : begin - _zz_115 = execute_RS2; + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; end - `Src2CtrlEnum_defaultEncoding_IMI : begin - _zz_115 = {_zz_112,execute_INSTRUCTION[31 : 20]}; + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; end - `Src2CtrlEnum_defaultEncoding_IMS : begin - _zz_115 = {_zz_114,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; end default : begin - _zz_115 = _zz_41; + _zz_execute_SRC2_5 = _zz_execute_SRC2; end endcase end - always @ (*) begin - execute_SrcPlugin_addSub = _zz_343; - if(execute_SRC2_FORCE_ZERO)begin + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin execute_SrcPlugin_addSub = execute_SRC1; end end assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; - always @ (*) begin - _zz_116[0] = execute_SRC1[31]; - _zz_116[1] = execute_SRC1[30]; - _zz_116[2] = execute_SRC1[29]; - _zz_116[3] = execute_SRC1[28]; - _zz_116[4] = execute_SRC1[27]; - _zz_116[5] = execute_SRC1[26]; - _zz_116[6] = execute_SRC1[25]; - _zz_116[7] = execute_SRC1[24]; - _zz_116[8] = execute_SRC1[23]; - _zz_116[9] = execute_SRC1[22]; - _zz_116[10] = execute_SRC1[21]; - _zz_116[11] = execute_SRC1[20]; - _zz_116[12] = execute_SRC1[19]; - _zz_116[13] = execute_SRC1[18]; - _zz_116[14] = execute_SRC1[17]; - _zz_116[15] = execute_SRC1[16]; - _zz_116[16] = execute_SRC1[15]; - _zz_116[17] = execute_SRC1[14]; - _zz_116[18] = execute_SRC1[13]; - _zz_116[19] = execute_SRC1[12]; - _zz_116[20] = execute_SRC1[11]; - _zz_116[21] = execute_SRC1[10]; - _zz_116[22] = execute_SRC1[9]; - _zz_116[23] = execute_SRC1[8]; - _zz_116[24] = execute_SRC1[7]; - _zz_116[25] = execute_SRC1[6]; - _zz_116[26] = execute_SRC1[5]; - _zz_116[27] = execute_SRC1[4]; - _zz_116[28] = execute_SRC1[3]; - _zz_116[29] = execute_SRC1[2]; - _zz_116[30] = execute_SRC1[1]; - _zz_116[31] = execute_SRC1[0]; - end - - assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SLL_1) ? _zz_116 : execute_SRC1); - always @ (*) begin - _zz_117[0] = memory_SHIFT_RIGHT[31]; - _zz_117[1] = memory_SHIFT_RIGHT[30]; - _zz_117[2] = memory_SHIFT_RIGHT[29]; - _zz_117[3] = memory_SHIFT_RIGHT[28]; - _zz_117[4] = memory_SHIFT_RIGHT[27]; - _zz_117[5] = memory_SHIFT_RIGHT[26]; - _zz_117[6] = memory_SHIFT_RIGHT[25]; - _zz_117[7] = memory_SHIFT_RIGHT[24]; - _zz_117[8] = memory_SHIFT_RIGHT[23]; - _zz_117[9] = memory_SHIFT_RIGHT[22]; - _zz_117[10] = memory_SHIFT_RIGHT[21]; - _zz_117[11] = memory_SHIFT_RIGHT[20]; - _zz_117[12] = memory_SHIFT_RIGHT[19]; - _zz_117[13] = memory_SHIFT_RIGHT[18]; - _zz_117[14] = memory_SHIFT_RIGHT[17]; - _zz_117[15] = memory_SHIFT_RIGHT[16]; - _zz_117[16] = memory_SHIFT_RIGHT[15]; - _zz_117[17] = memory_SHIFT_RIGHT[14]; - _zz_117[18] = memory_SHIFT_RIGHT[13]; - _zz_117[19] = memory_SHIFT_RIGHT[12]; - _zz_117[20] = memory_SHIFT_RIGHT[11]; - _zz_117[21] = memory_SHIFT_RIGHT[10]; - _zz_117[22] = memory_SHIFT_RIGHT[9]; - _zz_117[23] = memory_SHIFT_RIGHT[8]; - _zz_117[24] = memory_SHIFT_RIGHT[7]; - _zz_117[25] = memory_SHIFT_RIGHT[6]; - _zz_117[26] = memory_SHIFT_RIGHT[5]; - _zz_117[27] = memory_SHIFT_RIGHT[4]; - _zz_117[28] = memory_SHIFT_RIGHT[3]; - _zz_117[29] = memory_SHIFT_RIGHT[2]; - _zz_117[30] = memory_SHIFT_RIGHT[1]; - _zz_117[31] = memory_SHIFT_RIGHT[0]; - end - - always @ (*) begin - _zz_118 = 1'b0; - if(_zz_271)begin - if(_zz_272)begin - if(_zz_123)begin - _zz_118 = 1'b1; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_273)begin - if(_zz_274)begin - if(_zz_125)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if(_zz_275)begin - if(_zz_276)begin - if(_zz_127)begin - _zz_118 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; end end end - if((! decode_RS1_USE))begin - _zz_118 = 1'b0; + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; end end - always @ (*) begin - _zz_119 = 1'b0; - if(_zz_271)begin - if(_zz_272)begin - if(_zz_124)begin - _zz_119 = 1'b1; + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_273)begin - if(_zz_274)begin - if(_zz_126)begin - _zz_119 = 1'b1; + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if(_zz_275)begin - if(_zz_276)begin - if(_zz_128)begin - _zz_119 = 1'b1; + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; end end end - if((! decode_RS2_USE))begin - _zz_119 = 1'b0; - end - end - - assign _zz_123 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_124 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_125 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_126 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); - assign _zz_127 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); - assign _zz_128 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); - assign _zz_129 = execute_INSTRUCTION[14 : 12]; - always @ (*) begin - if((_zz_129 == 3'b000)) begin - _zz_130 = execute_BranchPlugin_eq; - end else if((_zz_129 == 3'b001)) begin - _zz_130 = (! execute_BranchPlugin_eq); - end else if((((_zz_129 & 3'b101) == 3'b101))) begin - _zz_130 = (! execute_SRC_LESS); - end else begin - _zz_130 = execute_SRC_LESS; - end + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase end - always @ (*) begin + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_INC : begin - _zz_131 = 1'b0; + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_131 = 1'b1; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_131 = 1'b1; + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; end default : begin - _zz_131 = _zz_130; + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; end endcase end - assign _zz_132 = _zz_350[11]; - always @ (*) begin - _zz_133[19] = _zz_132; - _zz_133[18] = _zz_132; - _zz_133[17] = _zz_132; - _zz_133[16] = _zz_132; - _zz_133[15] = _zz_132; - _zz_133[14] = _zz_132; - _zz_133[13] = _zz_132; - _zz_133[12] = _zz_132; - _zz_133[11] = _zz_132; - _zz_133[10] = _zz_132; - _zz_133[9] = _zz_132; - _zz_133[8] = _zz_132; - _zz_133[7] = _zz_132; - _zz_133[6] = _zz_132; - _zz_133[5] = _zz_132; - _zz_133[4] = _zz_132; - _zz_133[3] = _zz_132; - _zz_133[2] = _zz_132; - _zz_133[1] = _zz_132; - _zz_133[0] = _zz_132; - end - - assign _zz_134 = _zz_351[19]; - always @ (*) begin - _zz_135[10] = _zz_134; - _zz_135[9] = _zz_134; - _zz_135[8] = _zz_134; - _zz_135[7] = _zz_134; - _zz_135[6] = _zz_134; - _zz_135[5] = _zz_134; - _zz_135[4] = _zz_134; - _zz_135[3] = _zz_134; - _zz_135[2] = _zz_134; - _zz_135[1] = _zz_134; - _zz_135[0] = _zz_134; - end - - assign _zz_136 = _zz_352[11]; - always @ (*) begin - _zz_137[18] = _zz_136; - _zz_137[17] = _zz_136; - _zz_137[16] = _zz_136; - _zz_137[15] = _zz_136; - _zz_137[14] = _zz_136; - _zz_137[13] = _zz_136; - _zz_137[12] = _zz_136; - _zz_137[11] = _zz_136; - _zz_137[10] = _zz_136; - _zz_137[9] = _zz_136; - _zz_137[8] = _zz_136; - _zz_137[7] = _zz_136; - _zz_137[6] = _zz_136; - _zz_137[5] = _zz_136; - _zz_137[4] = _zz_136; - _zz_137[3] = _zz_136; - _zz_137[2] = _zz_136; - _zz_137[1] = _zz_136; - _zz_137[0] = _zz_136; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - _zz_138 = (_zz_353[1] ^ execute_RS1[1]); + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); end - `BranchCtrlEnum_defaultEncoding_JAL : begin - _zz_138 = _zz_354[1]; + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; end default : begin - _zz_138 = _zz_355[1]; + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; end endcase end - assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_138); - always @ (*) begin + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin + `BranchCtrlEnum_binary_sequential_JALR : begin execute_BranchPlugin_branch_src1 = execute_RS1; end default : begin @@ -4196,183 +4372,195 @@ module VexRiscv ( endcase end - assign _zz_139 = _zz_356[11]; - always @ (*) begin - _zz_140[19] = _zz_139; - _zz_140[18] = _zz_139; - _zz_140[17] = _zz_139; - _zz_140[16] = _zz_139; - _zz_140[15] = _zz_139; - _zz_140[14] = _zz_139; - _zz_140[13] = _zz_139; - _zz_140[12] = _zz_139; - _zz_140[11] = _zz_139; - _zz_140[10] = _zz_139; - _zz_140[9] = _zz_139; - _zz_140[8] = _zz_139; - _zz_140[7] = _zz_139; - _zz_140[6] = _zz_139; - _zz_140[5] = _zz_139; - _zz_140[4] = _zz_139; - _zz_140[3] = _zz_139; - _zz_140[2] = _zz_139; - _zz_140[1] = _zz_139; - _zz_140[0] = _zz_139; - end - - always @ (*) begin + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin case(execute_BRANCH_CTRL) - `BranchCtrlEnum_defaultEncoding_JALR : begin - execute_BranchPlugin_branch_src2 = {_zz_140,execute_INSTRUCTION[31 : 20]}; + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; end default : begin - execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JAL) ? {{_zz_142,{{{_zz_594,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_144,{{{_zz_595,_zz_596},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); - if(execute_PREDICTION_HAD_BRANCHED2)begin - execute_BranchPlugin_branch_src2 = {29'd0, _zz_359}; + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; end end endcase end - assign _zz_141 = _zz_357[19]; - always @ (*) begin - _zz_142[10] = _zz_141; - _zz_142[9] = _zz_141; - _zz_142[8] = _zz_141; - _zz_142[7] = _zz_141; - _zz_142[6] = _zz_141; - _zz_142[5] = _zz_141; - _zz_142[4] = _zz_141; - _zz_142[3] = _zz_141; - _zz_142[2] = _zz_141; - _zz_142[1] = _zz_141; - _zz_142[0] = _zz_141; - end - - assign _zz_143 = _zz_358[11]; - always @ (*) begin - _zz_144[18] = _zz_143; - _zz_144[17] = _zz_143; - _zz_144[16] = _zz_143; - _zz_144[15] = _zz_143; - _zz_144[14] = _zz_143; - _zz_144[13] = _zz_143; - _zz_144[12] = _zz_143; - _zz_144[11] = _zz_143; - _zz_144[10] = _zz_143; - _zz_144[9] = _zz_143; - _zz_144[8] = _zz_143; - _zz_144[7] = _zz_143; - _zz_144[6] = _zz_143; - _zz_144[5] = _zz_143; - _zz_144[4] = _zz_143; - _zz_144[3] = _zz_143; - _zz_144[2] = _zz_143; - _zz_144[1] = _zz_143; - _zz_144[0] = _zz_143; + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; end assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && (! 1'b0)); assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; - always @ (*) begin + always @(*) begin BranchPlugin_branchExceptionPort_valid = (execute_arbitration_isValid && (execute_BRANCH_DO && execute_BRANCH_CALC[1])); - if(1'b0)begin + if(when_BranchPlugin_l296) begin BranchPlugin_branchExceptionPort_valid = 1'b0; end end assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; assign BranchPlugin_branchExceptionPort_payload_badAddr = execute_BRANCH_CALC; + assign when_BranchPlugin_l296 = 1'b0; assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; - always @ (*) begin + always @(*) begin CsrPlugin_privilege = 2'b11; - if(CsrPlugin_forceMachineWire)begin + if(CsrPlugin_forceMachineWire) begin CsrPlugin_privilege = 2'b11; end end - assign _zz_145 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); - assign _zz_146 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); - assign _zz_147 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); - assign _zz_148 = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; - assign _zz_149 = _zz_360[0]; - assign _zz_150 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; - assign _zz_151 = _zz_362[0]; - always @ (*) begin + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_2 = {CsrPlugin_selfException_valid,BranchPlugin_branchExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3[0]; + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; - if(_zz_261)begin + if(_zz_when) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; end - if(decode_arbitration_isFlushed)begin + if(decode_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; - if(_zz_264)begin + if(_zz_when_1) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; end - if(execute_arbitration_isFlushed)begin + if(execute_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; - end - if(memory_arbitration_isFlushed)begin + if(memory_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; end end - always @ (*) begin + always @(*) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; end - if(writeBack_arbitration_isFlushed)begin + if(writeBack_arbitration_isFlushed) begin CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; end end + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); - always @ (*) begin + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; - if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000))begin + if(when_CsrPlugin_l991) begin CsrPlugin_pipelineLiberator_done = 1'b0; end - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_pipelineLiberator_done = 1'b0; end end + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); - always @ (*) begin + always @(*) begin CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; end end - always @ (*) begin + always @(*) begin CsrPlugin_trapCause = CsrPlugin_interrupt_code; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; end end - always @ (*) begin + always @(*) begin CsrPlugin_xtvec_mode = 2'bxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin @@ -4383,8 +4571,8 @@ module VexRiscv ( endcase end - always @ (*) begin - CsrPlugin_xtvec_base = 30'h0; + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; @@ -4394,199 +4582,208 @@ module VexRiscv ( endcase end + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalAccess = 1'b1; - if(execute_CsrPlugin_csr_3264)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3857)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3858)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3859)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3860)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_769)begin + if(execute_CsrPlugin_csr_769) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_768)begin + if(execute_CsrPlugin_csr_768) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_836)begin + if(execute_CsrPlugin_csr_836) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_772)begin + if(execute_CsrPlugin_csr_772) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_773)begin + if(execute_CsrPlugin_csr_773) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_833)begin + if(execute_CsrPlugin_csr_833) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_832)begin + if(execute_CsrPlugin_csr_832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_834)begin + if(execute_CsrPlugin_csr_834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_835)begin + if(execute_CsrPlugin_csr_835) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2816)begin + if(execute_CsrPlugin_csr_2816) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2944)begin + if(execute_CsrPlugin_csr_2944) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2818)begin + if(execute_CsrPlugin_csr_2818) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2946)begin + if(execute_CsrPlugin_csr_2946) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_3072)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3200)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3074)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3202)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820)begin + if(execute_CsrPlugin_csr_3008) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2822)begin + if(execute_CsrPlugin_csr_2820) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2821) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2824)begin + if(execute_CsrPlugin_csr_2822) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2823) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2826)begin + if(execute_CsrPlugin_csr_2824) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2825) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2828)begin + if(execute_CsrPlugin_csr_2826) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2827) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2830)begin + if(execute_CsrPlugin_csr_2828) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2829) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2832)begin + if(execute_CsrPlugin_csr_2830) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2831) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2834)begin + if(execute_CsrPlugin_csr_2832) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CSR_WRITE_OPCODE)begin + if(execute_CsrPlugin_csr_2833) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_3008)begin + if(execute_CsrPlugin_csr_2834) begin execute_CsrPlugin_illegalAccess = 1'b0; end - if(execute_CsrPlugin_csr_4032)begin - if(execute_CSR_READ_OPCODE)begin + if(execute_CsrPlugin_csr_2835) begin + if(execute_CSR_WRITE_OPCODE) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - if(_zz_277)begin + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_illegalAccess = 1'b1; end - if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + if(when_CsrPlugin_l1302) begin execute_CsrPlugin_illegalAccess = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_illegalInstruction = 1'b0; - if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin - if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin execute_CsrPlugin_illegalInstruction = 1'b1; end end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_valid = 1'b0; - if(_zz_278)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_valid = 1'b1; end - if(_zz_279)begin + if(when_CsrPlugin_l1144) begin CsrPlugin_selfException_valid = 1'b1; end end - always @ (*) begin + always @(*) begin CsrPlugin_selfException_payload_code = 4'bxxxx; - if(_zz_278)begin + if(when_CsrPlugin_l1129) begin CsrPlugin_selfException_payload_code = 4'b0010; end - if(_zz_279)begin + if(when_CsrPlugin_l1144) begin case(CsrPlugin_privilege) 2'b00 : begin CsrPlugin_selfException_payload_code = 4'b1000; @@ -4599,106 +4796,49 @@ module VexRiscv ( end assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; - always @ (*) begin + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); - if(_zz_277)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_writeInstruction = 1'b0; end end - always @ (*) begin + always @(*) begin execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); - if(_zz_277)begin + if(when_CsrPlugin_l1297) begin execute_CsrPlugin_readInstruction = 1'b0; end end assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); - assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; - always @ (*) begin - case(_zz_292) + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) 1'b0 : begin - execute_CsrPlugin_writeData = execute_SRC1; + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; end default : begin - execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); end endcase end + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; - assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); - assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); - assign execute_CfuPlugin_functionsIds_0 = _zz_364; - assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; - assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; - assign _zz_168 = _zz_365[7]; - always @ (*) begin - _zz_169[23] = _zz_168; - _zz_169[22] = _zz_168; - _zz_169[21] = _zz_168; - _zz_169[20] = _zz_168; - _zz_169[19] = _zz_168; - _zz_169[18] = _zz_168; - _zz_169[17] = _zz_168; - _zz_169[16] = _zz_168; - _zz_169[15] = _zz_168; - _zz_169[14] = _zz_168; - _zz_169[13] = _zz_168; - _zz_169[12] = _zz_168; - _zz_169[11] = _zz_168; - _zz_169[10] = _zz_168; - _zz_169[9] = _zz_168; - _zz_169[8] = _zz_168; - _zz_169[7] = _zz_168; - _zz_169[6] = _zz_168; - _zz_169[5] = _zz_168; - _zz_169[4] = _zz_168; - _zz_169[3] = _zz_168; - _zz_169[2] = _zz_168; - _zz_169[1] = _zz_168; - _zz_169[0] = _zz_168; - end - - always @ (*) begin - case(execute_CfuPlugin_CFU_INPUT_2_KIND) - `Input2Kind_defaultEncoding_RS : begin - _zz_170 = execute_RS2; - end - default : begin - _zz_170 = {_zz_169,execute_INSTRUCTION[31 : 24]}; - end - endcase - end - - assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_170; - assign memory_CfuPlugin_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_s2mPipe_rValid); - assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_s2mPipe_rValid); - assign memory_CfuPlugin_rsp_payload_response_ok = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_response_ok : CfuPlugin_bus_rsp_payload_response_ok); - assign memory_CfuPlugin_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_s2mPipe_rValid ? CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); - always @ (*) begin - CfuPlugin_joinException_valid = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - if(memory_arbitration_isValid)begin - CfuPlugin_joinException_valid = (! memory_CfuPlugin_rsp_payload_response_ok); - end - end - end - - assign CfuPlugin_joinException_payload_code = 4'b1111; - assign CfuPlugin_joinException_payload_badAddr = 32'h0; - always @ (*) begin - memory_CfuPlugin_rsp_ready = 1'b0; - if(memory_CfuPlugin_CFU_IN_FLIGHT)begin - memory_CfuPlugin_rsp_ready = (! memory_arbitration_isStuckByOthers); - end - end - assign execute_MulPlugin_a = execute_RS1; assign execute_MulPlugin_b = execute_RS2; - always @ (*) begin - case(_zz_280) + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_aSigned = 1'b1; end @@ -4711,8 +4851,8 @@ module VexRiscv ( endcase end - always @ (*) begin - case(_zz_280) + always @(*) begin + case(switch_MulPlugin_l87) 2'b01 : begin execute_MulPlugin_bSigned = 1'b1; end @@ -4731,58 +4871,69 @@ module VexRiscv ( assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; - assign writeBack_MulPlugin_result = ($signed(_zz_366) + $signed(_zz_367)); + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; assign memory_DivPlugin_frontendOk = 1'b1; - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willIncrement = 1'b0; - if(_zz_256)begin - if(_zz_281)begin + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin memory_DivPlugin_div_counter_willIncrement = 1'b1; end end end - always @ (*) begin + always @(*) begin memory_DivPlugin_div_counter_willClear = 1'b0; - if(_zz_282)begin + if(when_MulDivIterativePlugin_l162) begin memory_DivPlugin_div_counter_willClear = 1'b1; end end assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); - always @ (*) begin - if(memory_DivPlugin_div_counter_willOverflow)begin + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end else begin - memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_371); + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); end - if(memory_DivPlugin_div_counter_willClear)begin + if(memory_DivPlugin_div_counter_willClear) begin memory_DivPlugin_div_counter_valueNext = 6'h0; end end - assign _zz_171 = memory_DivPlugin_rs1[31 : 0]; - assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_171[31]}; - assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_372); - assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_373 : _zz_374); - assign memory_DivPlugin_div_stage_0_outNumerator = _zz_375[31:0]; - assign _zz_172 = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); - assign _zz_173 = (execute_RS2[31] && execute_IS_RS2_SIGNED); - assign _zz_174 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); - always @ (*) begin - _zz_175[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); - _zz_175[31 : 0] = execute_RS1; + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; end - assign _zz_177 = (_zz_176 & externalInterruptArray_regNext); - assign externalInterrupt = (_zz_177 != 32'h0); - always @ (*) begin + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_DebugPlugin_l225 = (DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)); + assign DebugPlugin_allowEBreak = (DebugPlugin_debugUsed && (! DebugPlugin_disableEbreak)); + always @(*) begin debug_bus_cmd_ready = 1'b1; - if(debug_bus_cmd_valid)begin - case(_zz_283) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin debug_bus_cmd_ready = IBusCachedPlugin_injectionPort_ready; end end @@ -4792,9 +4943,9 @@ module VexRiscv ( end end - always @ (*) begin + always @(*) begin debug_bus_rsp_data = DebugPlugin_busReadDataReg; - if((! _zz_178))begin + if(when_DebugPlugin_l244) begin debug_bus_rsp_data[0] = DebugPlugin_resetIt; debug_bus_rsp_data[1] = DebugPlugin_haltIt; debug_bus_rsp_data[2] = DebugPlugin_isPipBusy; @@ -4803,12 +4954,13 @@ module VexRiscv ( end end - always @ (*) begin + assign when_DebugPlugin_l244 = (! _zz_when_DebugPlugin_l244); + always @(*) begin IBusCachedPlugin_injectionPort_valid = 1'b0; - if(debug_bus_cmd_valid)begin - case(_zz_283) + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h01 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin IBusCachedPlugin_injectionPort_valid = 1'b1; end end @@ -4819,38 +4971,182 @@ module VexRiscv ( end assign IBusCachedPlugin_injectionPort_payload = debug_bus_cmd_payload_data; - assign DebugPlugin_allowEBreak = (CsrPlugin_privilege == 2'b11); + assign switch_DebugPlugin_l256 = debug_bus_cmd_payload_address[7 : 2]; + assign when_DebugPlugin_l260 = debug_bus_cmd_payload_data[16]; + assign when_DebugPlugin_l260_1 = debug_bus_cmd_payload_data[24]; + assign when_DebugPlugin_l261 = debug_bus_cmd_payload_data[17]; + assign when_DebugPlugin_l261_1 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l262 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l263 = debug_bus_cmd_payload_data[25]; + assign when_DebugPlugin_l264 = debug_bus_cmd_payload_data[18]; + assign when_DebugPlugin_l264_1 = debug_bus_cmd_payload_data[26]; + assign when_DebugPlugin_l284 = (execute_arbitration_isValid && execute_DO_EBREAK); + assign when_DebugPlugin_l287 = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) == 1'b0); + assign when_DebugPlugin_l300 = (DebugPlugin_stepIt && IBusCachedPlugin_incomingInstruction); assign debug_resetOut = DebugPlugin_resetIt_regNext; - assign _zz_29 = decode_SRC1_CTRL; - assign _zz_27 = _zz_56; - assign _zz_43 = decode_to_execute_SRC1_CTRL; - assign _zz_26 = decode_ALU_CTRL; - assign _zz_24 = _zz_55; - assign _zz_44 = decode_to_execute_ALU_CTRL; - assign _zz_23 = decode_SRC2_CTRL; - assign _zz_21 = _zz_54; - assign _zz_42 = decode_to_execute_SRC2_CTRL; - assign _zz_20 = decode_ALU_BITWISE_CTRL; - assign _zz_18 = _zz_53; - assign _zz_45 = decode_to_execute_ALU_BITWISE_CTRL; - assign _zz_17 = decode_SHIFT_CTRL; - assign _zz_14 = execute_SHIFT_CTRL; - assign _zz_15 = _zz_52; - assign _zz_40 = decode_to_execute_SHIFT_CTRL; - assign _zz_39 = execute_to_memory_SHIFT_CTRL; - assign _zz_12 = decode_BRANCH_CTRL; - assign _zz_58 = _zz_51; - assign _zz_36 = decode_to_execute_BRANCH_CTRL; - assign _zz_10 = decode_ENV_CTRL; - assign _zz_7 = execute_ENV_CTRL; - assign _zz_5 = memory_ENV_CTRL; - assign _zz_8 = _zz_50; - assign _zz_34 = decode_to_execute_ENV_CTRL; - assign _zz_33 = execute_to_memory_ENV_CTRL; - assign _zz_35 = memory_to_writeBack_ENV_CTRL; - assign _zz_3 = decode_CfuPlugin_CFU_INPUT_2_KIND; - assign _zz_1 = _zz_49; - assign _zz_32 = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_DebugPlugin_l316 = (DebugPlugin_haltIt || DebugPlugin_stepIt); + assign execute_CfuPlugin_schedule = (execute_arbitration_isValid && execute_CfuPlugin_CFU_ENABLE); + assign CfuPlugin_bus_cmd_fire = (CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready); + assign when_CfuPlugin_l171 = (! execute_arbitration_isStuckByOthers); + assign CfuPlugin_bus_cmd_valid = ((execute_CfuPlugin_schedule || execute_CfuPlugin_hold) && (! execute_CfuPlugin_fired)); + assign when_CfuPlugin_l175 = (CfuPlugin_bus_cmd_valid && (! CfuPlugin_bus_cmd_ready)); + assign execute_CfuPlugin_functionsIds_0 = _zz_execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_function_id = execute_CfuPlugin_functionsIds_0; + assign CfuPlugin_bus_cmd_payload_inputs_0 = execute_RS1; + assign _zz_CfuPlugin_bus_cmd_payload_inputs_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[23] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[22] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[21] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[20] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[19] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[18] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[17] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[16] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[15] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[14] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[13] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[12] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[11] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[10] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[9] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[8] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[7] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[6] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[5] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[4] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[3] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[2] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[1] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + _zz_CfuPlugin_bus_cmd_payload_inputs_1_1[0] = _zz_CfuPlugin_bus_cmd_payload_inputs_1; + end + + always @(*) begin + case(execute_CfuPlugin_CFU_INPUT_2_KIND) + `Input2Kind_binary_sequential_RS : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = execute_RS2; + end + default : begin + _zz_CfuPlugin_bus_cmd_payload_inputs_1_2 = {_zz_CfuPlugin_bus_cmd_payload_inputs_1_1,execute_INSTRUCTION[31 : 24]}; + end + endcase + end + + assign CfuPlugin_bus_cmd_payload_inputs_1 = _zz_CfuPlugin_bus_cmd_payload_inputs_1_2; + assign CfuPlugin_bus_rsp_ready = (! CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_valid = (CfuPlugin_bus_rsp_valid || CfuPlugin_bus_rsp_rValid); + assign CfuPlugin_bus_rsp_rsp_payload_outputs_0 = (CfuPlugin_bus_rsp_rValid ? CfuPlugin_bus_rsp_rData_outputs_0 : CfuPlugin_bus_rsp_payload_outputs_0); + always @(*) begin + CfuPlugin_bus_rsp_rsp_ready = 1'b0; + if(memory_CfuPlugin_CFU_IN_FLIGHT) begin + CfuPlugin_bus_rsp_rsp_ready = (! memory_arbitration_isStuckByOthers); + end + end + + assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); + assign when_GenCoreDefault_l367 = _zz_when_GenCoreDefault_l367[0]; + assign when_GenCoreDefault_l367_1 = _zz_when_GenCoreDefault_l367_1[0]; + assign when_GenCoreDefault_l367_2 = _zz_when_GenCoreDefault_l367_2[0]; + assign when_GenCoreDefault_l367_3 = _zz_when_GenCoreDefault_l367_3[0]; + assign when_GenCoreDefault_l367_4 = _zz_when_GenCoreDefault_l367_4[0]; + assign when_GenCoreDefault_l367_5 = _zz_when_GenCoreDefault_l367_5[0]; + assign when_GenCoreDefault_l367_6 = _zz_when_GenCoreDefault_l367_6[0]; + assign when_GenCoreDefault_l367_7 = _zz_when_GenCoreDefault_l367_7[0]; + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND_1 = decode_CfuPlugin_CFU_INPUT_2_KIND; + assign _zz_decode_CfuPlugin_CFU_INPUT_2_KIND = _zz_decode_CfuPlugin_CFU_INPUT_2_KIND_1; + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign _zz_execute_CfuPlugin_CFU_INPUT_2_KIND = decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_62 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_63 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_64 = (! writeBack_arbitration_isStuck); assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); @@ -4871,9 +5167,15 @@ module VexRiscv ( assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); - always @ (*) begin + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + always @(*) begin IBusCachedPlugin_injectionPort_ready = 1'b0; - case(_zz_179) + case(switch_Fetcher_l362) 3'b100 : begin IBusCachedPlugin_injectionPort_ready = 1'b1; end @@ -4882,296 +5184,340 @@ module VexRiscv ( endcase end - always @ (*) begin - _zz_180 = 32'h0; - if(execute_CsrPlugin_csr_3264)begin - _zz_180[12 : 0] = 13'h1000; - _zz_180[25 : 20] = 6'h20; + assign when_Fetcher_l378 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_28 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_29 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_30 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_31 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_32 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_33 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_34 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_35 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_36 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_37 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_38 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_39 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_10[25 : 20] = 6'h20; end end - always @ (*) begin - _zz_181 = 32'h0; - if(execute_CsrPlugin_csr_3857)begin - _zz_181[3 : 0] = 4'b1011; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 0] = 4'b1011; end end - always @ (*) begin - _zz_182 = 32'h0; - if(execute_CsrPlugin_csr_3858)begin - _zz_182[4 : 0] = 5'h16; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[4 : 0] = 5'h16; end end - always @ (*) begin - _zz_183 = 32'h0; - if(execute_CsrPlugin_csr_3859)begin - _zz_183[5 : 0] = 6'h21; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[5 : 0] = 6'h21; end end - always @ (*) begin - _zz_184 = 32'h0; - if(execute_CsrPlugin_csr_769)begin - _zz_184[31 : 30] = CsrPlugin_misa_base; - _zz_184[25 : 0] = CsrPlugin_misa_extensions; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_14[25 : 0] = CsrPlugin_misa_extensions; end end - always @ (*) begin - _zz_185 = 32'h0; - if(execute_CsrPlugin_csr_768)begin - _zz_185[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_185[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_185[3 : 3] = CsrPlugin_mstatus_MIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_15[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 3] = CsrPlugin_mstatus_MIE; end end - always @ (*) begin - _zz_186 = 32'h0; - if(execute_CsrPlugin_csr_836)begin - _zz_186[11 : 11] = CsrPlugin_mip_MEIP; - _zz_186[7 : 7] = CsrPlugin_mip_MTIP; - _zz_186[3 : 3] = CsrPlugin_mip_MSIP; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_16[3 : 3] = CsrPlugin_mip_MSIP; end end - always @ (*) begin - _zz_187 = 32'h0; - if(execute_CsrPlugin_csr_772)begin - _zz_187[11 : 11] = CsrPlugin_mie_MEIE; - _zz_187[7 : 7] = CsrPlugin_mie_MTIE; - _zz_187[3 : 3] = CsrPlugin_mie_MSIE; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_17[3 : 3] = CsrPlugin_mie_MSIE; end end - always @ (*) begin - _zz_188 = 32'h0; - if(execute_CsrPlugin_csr_773)begin - _zz_188[31 : 2] = CsrPlugin_mtvec_base; - _zz_188[1 : 0] = CsrPlugin_mtvec_mode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 0] = CsrPlugin_mtvec_mode; end end - always @ (*) begin - _zz_189 = 32'h0; - if(execute_CsrPlugin_csr_833)begin - _zz_189[31 : 0] = CsrPlugin_mepc; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mepc; end end - always @ (*) begin - _zz_190 = 32'h0; - if(execute_CsrPlugin_csr_832)begin - _zz_190[31 : 0] = CsrPlugin_mscratch; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mscratch; end end - always @ (*) begin - _zz_191 = 32'h0; - if(execute_CsrPlugin_csr_834)begin - _zz_191[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_191[3 : 0] = CsrPlugin_mcause_exceptionCode; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_21[3 : 0] = CsrPlugin_mcause_exceptionCode; end end - always @ (*) begin - _zz_192 = 32'h0; - if(execute_CsrPlugin_csr_835)begin - _zz_192[31 : 0] = CsrPlugin_mtval; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_mtval; end end - always @ (*) begin - _zz_193 = 32'h0; - if(execute_CsrPlugin_csr_2816)begin - _zz_193[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_194 = 32'h0; - if(execute_CsrPlugin_csr_2944)begin - _zz_194[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_195 = 32'h0; - if(execute_CsrPlugin_csr_2818)begin - _zz_195[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_196 = 32'h0; - if(execute_CsrPlugin_csr_2946)begin - _zz_196[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_197 = 32'h0; - if(execute_CsrPlugin_csr_3072)begin - _zz_197[31 : 0] = CsrPlugin_mcycle[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end - always @ (*) begin - _zz_198 = 32'h0; - if(execute_CsrPlugin_csr_3200)begin - _zz_198[31 : 0] = CsrPlugin_mcycle[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_28[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end - always @ (*) begin - _zz_199 = 32'h0; - if(execute_CsrPlugin_csr_3074)begin - _zz_199[31 : 0] = CsrPlugin_minstret[31 : 0]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_29 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_29[31 : 0] = CsrPlugin_minstret[31 : 0]; end end - always @ (*) begin - _zz_200 = 32'h0; - if(execute_CsrPlugin_csr_3202)begin - _zz_200[31 : 0] = CsrPlugin_minstret[63 : 32]; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_30 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_30[31 : 0] = CsrPlugin_minstret[63 : 32]; end end - always @ (*) begin - _zz_201 = 32'h0; - if(execute_CsrPlugin_csr_2820)begin - _zz_201[31 : 0] = _zz_152; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_31 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_31[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end - always @ (*) begin - _zz_202 = 32'h0; - if(execute_CsrPlugin_csr_2822)begin - _zz_202[31 : 0] = _zz_154; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_32 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_32[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - always @ (*) begin - _zz_203 = 32'h0; - if(execute_CsrPlugin_csr_2824)begin - _zz_203[31 : 0] = _zz_156; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_33 = 32'h0; + if(execute_CsrPlugin_csr_2820) begin + _zz_CsrPlugin_csrMapping_readDataInit_33[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; end end - always @ (*) begin - _zz_204 = 32'h0; - if(execute_CsrPlugin_csr_2826)begin - _zz_204[31 : 0] = _zz_158; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_34 = 32'h0; + if(execute_CsrPlugin_csr_2822) begin + _zz_CsrPlugin_csrMapping_readDataInit_34[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; end end - always @ (*) begin - _zz_205 = 32'h0; - if(execute_CsrPlugin_csr_2828)begin - _zz_205[31 : 0] = _zz_160; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_35 = 32'h0; + if(execute_CsrPlugin_csr_2824) begin + _zz_CsrPlugin_csrMapping_readDataInit_35[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_4; end end - always @ (*) begin - _zz_206 = 32'h0; - if(execute_CsrPlugin_csr_2830)begin - _zz_206[31 : 0] = _zz_162; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_36 = 32'h0; + if(execute_CsrPlugin_csr_2826) begin + _zz_CsrPlugin_csrMapping_readDataInit_36[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_5; end end - always @ (*) begin - _zz_207 = 32'h0; - if(execute_CsrPlugin_csr_2832)begin - _zz_207[31 : 0] = _zz_164; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_37 = 32'h0; + if(execute_CsrPlugin_csr_2828) begin + _zz_CsrPlugin_csrMapping_readDataInit_37[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_6; end end - always @ (*) begin - _zz_208 = 32'h0; - if(execute_CsrPlugin_csr_2834)begin - _zz_208[31 : 0] = _zz_166; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_38 = 32'h0; + if(execute_CsrPlugin_csr_2830) begin + _zz_CsrPlugin_csrMapping_readDataInit_38[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_7; end end - always @ (*) begin - _zz_209 = 32'h0; - if(execute_CsrPlugin_csr_3008)begin - _zz_209[31 : 0] = _zz_176; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_39 = 32'h0; + if(execute_CsrPlugin_csr_2832) begin + _zz_CsrPlugin_csrMapping_readDataInit_39[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_8; end end - always @ (*) begin - _zz_210 = 32'h0; - if(execute_CsrPlugin_csr_4032)begin - _zz_210[31 : 0] = _zz_177; + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_40 = 32'h0; + if(execute_CsrPlugin_csr_2834) begin + _zz_CsrPlugin_csrMapping_readDataInit_40[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_9; end end - assign execute_CsrPlugin_readData = (((((_zz_180 | _zz_181) | (_zz_182 | _zz_183)) | ((_zz_597 | _zz_184) | (_zz_185 | _zz_186))) | (((_zz_187 | _zz_188) | (_zz_189 | _zz_190)) | ((_zz_191 | _zz_192) | (_zz_193 | _zz_194)))) | ((((_zz_195 | _zz_196) | (_zz_197 | _zz_198)) | ((_zz_199 | _zz_200) | (_zz_201 | _zz_202))) | (((_zz_203 | _zz_204) | (_zz_205 | _zz_206)) | ((_zz_207 | _zz_208) | (_zz_209 | _zz_210))))); - assign iBusWishbone_ADR = {_zz_392,_zz_211}; - assign iBusWishbone_CTI = ((_zz_211 == 3'b111) ? 3'b111 : 3'b010); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | (_zz_CsrPlugin_csrMapping_readDataInit_12 | _zz_CsrPlugin_csrMapping_readDataInit_13)) | ((_zz_CsrPlugin_csrMapping_readDataInit_41 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26) | (_zz_CsrPlugin_csrMapping_readDataInit_27 | _zz_CsrPlugin_csrMapping_readDataInit_28)) | ((_zz_CsrPlugin_csrMapping_readDataInit_29 | _zz_CsrPlugin_csrMapping_readDataInit_30) | (_zz_CsrPlugin_csrMapping_readDataInit_31 | _zz_CsrPlugin_csrMapping_readDataInit_32))) | (((_zz_CsrPlugin_csrMapping_readDataInit_33 | _zz_CsrPlugin_csrMapping_readDataInit_34) | (_zz_CsrPlugin_csrMapping_readDataInit_35 | _zz_CsrPlugin_csrMapping_readDataInit_36)) | ((_zz_CsrPlugin_csrMapping_readDataInit_37 | _zz_CsrPlugin_csrMapping_readDataInit_38) | (_zz_CsrPlugin_csrMapping_readDataInit_39 | _zz_CsrPlugin_csrMapping_readDataInit_40))))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); assign iBusWishbone_BTE = 2'b00; assign iBusWishbone_SEL = 4'b1111; assign iBusWishbone_WE = 1'b0; - assign iBusWishbone_DAT_MOSI = 32'h0; - always @ (*) begin + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin iBusWishbone_CYC = 1'b0; - if(_zz_284)begin + if(when_InstructionCache_l239) begin iBusWishbone_CYC = 1'b1; end end - always @ (*) begin + always @(*) begin iBusWishbone_STB = 1'b0; - if(_zz_284)begin + if(when_InstructionCache_l239) begin iBusWishbone_STB = 1'b1; end end + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); - assign iBus_rsp_valid = _zz_212; + assign iBus_rsp_valid = _zz_iBus_rsp_valid; assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; assign iBus_rsp_payload_error = 1'b0; - assign _zz_218 = (dBus_cmd_payload_length != 3'b000); - assign _zz_214 = dBus_cmd_valid; - assign _zz_216 = dBus_cmd_payload_wr; - assign _zz_217 = (_zz_213 == dBus_cmd_payload_length); - assign dBus_cmd_ready = (_zz_215 && (_zz_216 || _zz_217)); - assign dBusWishbone_ADR = ((_zz_218 ? {{dBus_cmd_payload_address[31 : 5],_zz_213},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); - assign dBusWishbone_CTI = (_zz_218 ? (_zz_217 ? 3'b111 : 3'b010) : 3'b000); + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); assign dBusWishbone_BTE = 2'b00; - assign dBusWishbone_SEL = (_zz_216 ? dBus_cmd_payload_mask : 4'b1111); - assign dBusWishbone_WE = _zz_216; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; - assign _zz_215 = (_zz_214 && dBusWishbone_ACK); - assign dBusWishbone_CYC = _zz_214; - assign dBusWishbone_STB = _zz_214; - assign dBus_rsp_valid = _zz_219; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; assign dBus_rsp_payload_error = 1'b0; - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; IBusCachedPlugin_fetchPc_booted <= 1'b0; IBusCachedPlugin_fetchPc_inc <= 1'b0; - _zz_72 <= 1'b0; - _zz_74 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; - IBusCachedPlugin_rspCounter <= _zz_87; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= 1'b0; - DBusCachedPlugin_rspCounter <= _zz_88; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; DBusCachedPlugin_rspCounter <= 32'h0; - _zz_108 <= 1'b1; - _zz_120 <= 1'b0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; CsrPlugin_misa_base <= 2'b01; CsrPlugin_misa_extensions <= 26'h0000042; CsrPlugin_mstatus_MIE <= 1'b0; @@ -5191,165 +5537,165 @@ module VexRiscv ( CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; CsrPlugin_hadException <= 1'b0; execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; execute_CfuPlugin_hold <= 1'b0; execute_CfuPlugin_fired <= 1'b0; - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; - memory_DivPlugin_div_counter_value <= 6'h0; - _zz_176 <= 32'h0; + CfuPlugin_bus_rsp_rValid <= 1'b0; execute_arbitration_isValid <= 1'b0; memory_arbitration_isValid <= 1'b0; writeBack_arbitration_isValid <= 1'b0; - _zz_179 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= 1'b0; - _zz_211 <= 3'b000; - _zz_212 <= 1'b0; - _zz_213 <= 3'b000; - _zz_219 <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; end else begin - if(IBusCachedPlugin_fetchPc_correction)begin + if(IBusCachedPlugin_fetchPc_correction) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire) begin IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; end IBusCachedPlugin_fetchPc_booted <= 1'b1; - if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + if(when_Fetcher_l131) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + if(IBusCachedPlugin_fetchPc_output_fire_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b1; end - if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + if(when_Fetcher_l131_1) begin IBusCachedPlugin_fetchPc_inc <= 1'b0; end - if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + if(when_Fetcher_l158) begin IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_72 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; end - if(_zz_70)begin - _zz_72 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); end - if(IBusCachedPlugin_iBusRsp_flush)begin - _zz_74 <= 1'b0; + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; end - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_74 <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + if(when_Fetcher_l329) begin IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + if(when_Fetcher_l329_1) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if((! execute_arbitration_isStuck))begin + if(when_Fetcher_l329_2) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if((! memory_arbitration_isStuck))begin + if(when_Fetcher_l329_3) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if((! writeBack_arbitration_isStuck))begin + if(when_Fetcher_l329_4) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; end - if(IBusCachedPlugin_fetchPc_flushed)begin + if(IBusCachedPlugin_fetchPc_flushed) begin IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; end - if(iBus_rsp_valid)begin + if(iBus_rsp_valid) begin IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; end - if(_zz_285)begin - dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; end - if(dBus_rsp_valid)begin + if(dBus_rsp_valid) begin DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); end - _zz_108 <= 1'b0; - _zz_120 <= (_zz_47 && writeBack_arbitration_isFiring); - if((! decode_arbitration_isStuck))begin + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l909_1) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l909_2) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l909_3) begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); end else begin CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; end CsrPlugin_interrupt_valid <= 1'b0; - if(_zz_286)begin - if(_zz_287)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_288)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_valid <= 1'b1; end - if(_zz_289)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_valid <= 1'b1; end end - CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_WFI)); - if(CsrPlugin_pipelineLiberator_active)begin - if((! execute_arbitration_isStuck))begin + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; end - if((! memory_arbitration_isStuck))begin + if(when_CsrPlugin_l980_1) begin CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; end - if((! writeBack_arbitration_isStuck))begin + if(when_CsrPlugin_l980_2) begin CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; end end - if(((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + if(when_CsrPlugin_l985) begin CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; end - if(CsrPlugin_interruptJump)begin + if(CsrPlugin_interruptJump) begin CsrPlugin_interrupt_valid <= 1'b0; end CsrPlugin_hadException <= CsrPlugin_exception; - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mstatus_MIE <= 1'b0; @@ -5360,8 +5706,8 @@ module VexRiscv ( end endcase end - if(_zz_267)begin - case(_zz_269) + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) 2'b11 : begin CsrPlugin_mstatus_MPP <= 2'b00; CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; @@ -5371,185 +5717,181 @@ module VexRiscv ( end endcase end - execute_CsrPlugin_wfiWake <= (({_zz_147,{_zz_146,_zz_145}} != 3'b000) || CsrPlugin_thirdPartyWake); - if(execute_CfuPlugin_schedule)begin + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(execute_CfuPlugin_schedule) begin execute_CfuPlugin_hold <= 1'b1; end - if(CfuPlugin_bus_cmd_ready)begin + if(CfuPlugin_bus_cmd_ready) begin execute_CfuPlugin_hold <= 1'b0; end - if((CfuPlugin_bus_cmd_valid && CfuPlugin_bus_cmd_ready))begin + if(CfuPlugin_bus_cmd_fire) begin execute_CfuPlugin_fired <= 1'b1; end - if((! execute_arbitration_isStuckByOthers))begin + if(when_CfuPlugin_l171) begin execute_CfuPlugin_fired <= 1'b0; end - if(memory_CfuPlugin_rsp_ready)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= 1'b0; + if(CfuPlugin_bus_rsp_valid) begin + CfuPlugin_bus_rsp_rValid <= 1'b1; end - if(_zz_290)begin - CfuPlugin_bus_rsp_s2mPipe_rValid <= CfuPlugin_bus_rsp_valid; + if(CfuPlugin_bus_rsp_rsp_ready) begin + CfuPlugin_bus_rsp_rValid <= 1'b0; end - memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; - if((! memory_arbitration_isStuck))begin - execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_31; + if(when_Pipeline_l124_62) begin + execute_to_memory_CfuPlugin_CFU_IN_FLIGHT <= _zz_execute_to_memory_CfuPlugin_CFU_IN_FLIGHT; end - if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + if(when_Pipeline_l151) begin execute_arbitration_isValid <= 1'b0; end - if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + if(when_Pipeline_l154) begin execute_arbitration_isValid <= decode_arbitration_isValid; end - if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + if(when_Pipeline_l151_1) begin memory_arbitration_isValid <= 1'b0; end - if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + if(when_Pipeline_l154_1) begin memory_arbitration_isValid <= execute_arbitration_isValid; end - if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + if(when_Pipeline_l151_2) begin writeBack_arbitration_isValid <= 1'b0; end - if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + if(when_Pipeline_l154_2) begin writeBack_arbitration_isValid <= memory_arbitration_isValid; end - case(_zz_179) + case(switch_Fetcher_l362) 3'b000 : begin - if(IBusCachedPlugin_injectionPort_valid)begin - _zz_179 <= 3'b001; + if(IBusCachedPlugin_injectionPort_valid) begin + switch_Fetcher_l362 <= 3'b001; end end 3'b001 : begin - _zz_179 <= 3'b010; + switch_Fetcher_l362 <= 3'b010; end 3'b010 : begin - _zz_179 <= 3'b011; + switch_Fetcher_l362 <= 3'b011; end 3'b011 : begin - if((! decode_arbitration_isStuck))begin - _zz_179 <= 3'b100; + if(when_Fetcher_l378) begin + switch_Fetcher_l362 <= 3'b100; end end 3'b100 : begin - _zz_179 <= 3'b000; + switch_Fetcher_l362 <= 3'b000; end default : begin end endcase - if(execute_CsrPlugin_csr_769)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_misa_base <= execute_CsrPlugin_writeData[31 : 30]; - CsrPlugin_misa_extensions <= execute_CsrPlugin_writeData[25 : 0]; + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; end end - if(execute_CsrPlugin_csr_768)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; - CsrPlugin_mstatus_MPIE <= _zz_385[0]; - CsrPlugin_mstatus_MIE <= _zz_386[0]; + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_772)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mie_MEIE <= _zz_388[0]; - CsrPlugin_mie_MTIE <= _zz_389[0]; - CsrPlugin_mie_MSIE <= _zz_390[0]; + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_3008)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_176 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(_zz_284)begin - if(iBusWishbone_ACK)begin - _zz_211 <= (_zz_211 + 3'b001); + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); end end - _zz_212 <= (iBusWishbone_CYC && iBusWishbone_ACK); - if((_zz_214 && _zz_215))begin - _zz_213 <= (_zz_213 + 3'b001); - if(_zz_217)begin - _zz_213 <= 3'b000; + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; end end - _zz_219 <= ((_zz_214 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); end end - always @ (posedge clk) begin - if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin - _zz_75 <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; end - if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; end - if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; end - if(_zz_285)begin - dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_rData_length <= dataCache_1_io_mem_cmd_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_payload_last; - end - if(dataCache_1_io_mem_cmd_s2mPipe_ready)begin - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_length <= dataCache_1_io_mem_cmd_s2mPipe_payload_length; - dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; - end - _zz_121 <= _zz_46[11 : 7]; - _zz_122 <= _zz_57; + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; CsrPlugin_mip_MEIP <= externalInterrupt; CsrPlugin_mip_MTIP <= timerInterrupt; CsrPlugin_mip_MSIP <= softwareInterrupt; CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); - if(writeBack_arbitration_isFiring)begin + if(writeBack_arbitration_isFiring) begin CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); end - if(_zz_261)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_149 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); - end - if(_zz_264)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_151 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); end - if(CfuPlugin_joinException_valid)begin - CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CfuPlugin_joinException_payload_code; - CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CfuPlugin_joinException_payload_badAddr; + if(_zz_when_1) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_code : CsrPlugin_selfException_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_3 ? BranchPlugin_branchExceptionPort_payload_badAddr : CsrPlugin_selfException_payload_badAddr); end - if(DBusCachedPlugin_exceptionBus_valid)begin + if(DBusCachedPlugin_exceptionBus_valid) begin CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; end - if(_zz_286)begin - if(_zz_287)begin + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin CsrPlugin_interrupt_code <= 4'b0111; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_288)begin + if(when_CsrPlugin_l952_1) begin CsrPlugin_interrupt_code <= 4'b0011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end - if(_zz_289)begin + if(when_CsrPlugin_l952_2) begin CsrPlugin_interrupt_code <= 4'b1011; CsrPlugin_interrupt_targetPrivilege <= 2'b11; end end - if(_zz_266)begin + if(when_CsrPlugin_l1019) begin case(CsrPlugin_targetPrivilege) 2'b11 : begin CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; CsrPlugin_mepc <= writeBack_PC; - if(CsrPlugin_hadException)begin + if(CsrPlugin_hadException) begin CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; end end @@ -5557,569 +5899,579 @@ module VexRiscv ( end endcase end - if(_zz_153[0])begin - _zz_152 <= (_zz_152 + 32'h00000001); + if(when_MulDivIterativePlugin_l126) begin + memory_DivPlugin_div_done <= 1'b1; end - if(_zz_155[0])begin - _zz_154 <= (_zz_154 + 32'h00000001); + if(when_MulDivIterativePlugin_l126_1) begin + memory_DivPlugin_div_done <= 1'b0; end - if(_zz_157[0])begin - _zz_156 <= (_zz_156 + 32'h00000001); + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; + end + end end - if(_zz_159[0])begin - _zz_158 <= (_zz_158 + 32'h00000001); + if(when_MulDivIterativePlugin_l162) begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); end - if(_zz_161[0])begin - _zz_160 <= (_zz_160 + 32'h00000001); + externalInterruptArray_regNext <= externalInterruptArray; + if(CfuPlugin_bus_rsp_ready) begin + CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end - if(_zz_163[0])begin - _zz_162 <= (_zz_162 + 32'h00000001); + if(when_GenCoreDefault_l367) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= (_zz_CsrPlugin_csrMapping_readDataInit_2 + 32'h00000001); end - if(_zz_165[0])begin - _zz_164 <= (_zz_164 + 32'h00000001); + if(when_GenCoreDefault_l367_1) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= (_zz_CsrPlugin_csrMapping_readDataInit_3 + 32'h00000001); end - if(_zz_167[0])begin - _zz_166 <= (_zz_166 + 32'h00000001); + if(when_GenCoreDefault_l367_2) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= (_zz_CsrPlugin_csrMapping_readDataInit_4 + 32'h00000001); end - if(_zz_290)begin - CfuPlugin_bus_rsp_s2mPipe_rData_response_ok <= CfuPlugin_bus_rsp_payload_response_ok; - CfuPlugin_bus_rsp_s2mPipe_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; + if(when_GenCoreDefault_l367_3) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= (_zz_CsrPlugin_csrMapping_readDataInit_5 + 32'h00000001); end - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_done <= 1'b1; + if(when_GenCoreDefault_l367_4) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= (_zz_CsrPlugin_csrMapping_readDataInit_6 + 32'h00000001); end - if((! memory_arbitration_isStuck))begin - memory_DivPlugin_div_done <= 1'b0; + if(when_GenCoreDefault_l367_5) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= (_zz_CsrPlugin_csrMapping_readDataInit_7 + 32'h00000001); end - if(_zz_256)begin - if(_zz_281)begin - memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; - memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; - if((memory_DivPlugin_div_counter_value == 6'h20))begin - memory_DivPlugin_div_result <= _zz_376[31:0]; - end - end + if(when_GenCoreDefault_l367_6) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= (_zz_CsrPlugin_csrMapping_readDataInit_8 + 32'h00000001); end - if(_zz_282)begin - memory_DivPlugin_accumulator <= 65'h0; - memory_DivPlugin_rs1 <= ((_zz_174 ? (~ _zz_175) : _zz_175) + _zz_382); - memory_DivPlugin_rs2 <= ((_zz_173 ? (~ execute_RS2) : execute_RS2) + _zz_384); - memory_DivPlugin_div_needRevert <= ((_zz_174 ^ (_zz_173 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + if(when_GenCoreDefault_l367_7) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= (_zz_CsrPlugin_csrMapping_readDataInit_9 + 32'h00000001); end - externalInterruptArray_regNext <= externalInterruptArray; - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_PC <= _zz_41; + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; end - if(((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + if(when_Pipeline_l124_2) begin memory_to_writeBack_PC <= memory_PC; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_3) begin decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_4) begin execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_5) begin memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_FORMAL_PC_NEXT <= _zz_60; + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_FORMAL_PC_NEXT <= _zz_59; + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= _zz_execute_to_memory_FORMAL_PC_NEXT; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_8) begin memory_to_writeBack_FORMAL_PC_NEXT <= memory_FORMAL_PC_NEXT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_9) begin decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC1_CTRL <= _zz_28; + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_11) begin decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_12) begin decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_13) begin execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_14) begin memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_CTRL <= _zz_25; + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SRC2_CTRL <= _zz_22; + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_17) begin decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_18) begin execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_19) begin memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_20) begin decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_21) begin decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_22) begin execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_23) begin decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_24) begin execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_25) begin memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_26) begin decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_27) begin decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ALU_BITWISE_CTRL <= _zz_19; + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_SHIFT_CTRL <= _zz_16; + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_SHIFT_CTRL <= _zz_13; + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_BRANCH_CTRL <= _zz_11; + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_32) begin decode_to_execute_IS_CSR <= decode_IS_CSR; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_ENV_CTRL <= _zz_9; + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_ENV_CTRL <= _zz_6; + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_ENV_CTRL <= _zz_4; - end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; end - if((! execute_arbitration_isStuck))begin - decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_2; - end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_36) begin decode_to_execute_IS_MUL <= decode_IS_MUL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_37) begin execute_to_memory_IS_MUL <= execute_IS_MUL; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_38) begin memory_to_writeBack_IS_MUL <= memory_IS_MUL; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_39) begin decode_to_execute_IS_DIV <= decode_IS_DIV; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_40) begin execute_to_memory_IS_DIV <= execute_IS_DIV; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_41) begin decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_42) begin decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_43) begin + decode_to_execute_CfuPlugin_CFU_ENABLE <= decode_CfuPlugin_CFU_ENABLE; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND <= _zz_decode_to_execute_CfuPlugin_CFU_INPUT_2_KIND; + end + if(when_Pipeline_l124_45) begin decode_to_execute_RS1 <= decode_RS1; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_46) begin decode_to_execute_RS2 <= decode_RS2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_47) begin decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_48) begin decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_49) begin decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_50) begin decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; end - if((! execute_arbitration_isStuck))begin + if(when_Pipeline_l124_51) begin decode_to_execute_DO_EBREAK <= decode_DO_EBREAK; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_52) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + if(when_Pipeline_l124_53) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; end - if((! memory_arbitration_isStuck))begin - execute_to_memory_REGFILE_WRITE_DATA <= _zz_37; + if(when_Pipeline_l124_54) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_38; + if(when_Pipeline_l124_55) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_56) begin execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; end - if((! writeBack_arbitration_isStuck))begin - memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_30; - end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_57) begin execute_to_memory_MUL_LL <= execute_MUL_LL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_58) begin execute_to_memory_MUL_LH <= execute_MUL_LH; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_59) begin execute_to_memory_MUL_HL <= execute_MUL_HL; end - if((! memory_arbitration_isStuck))begin + if(when_Pipeline_l124_60) begin execute_to_memory_MUL_HH <= execute_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_61) begin memory_to_writeBack_MUL_HH <= memory_MUL_HH; end - if((! writeBack_arbitration_isStuck))begin + if(when_Pipeline_l124_63) begin + memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT <= _zz_memory_to_writeBack_CfuPlugin_CFU_IN_FLIGHT; + end + if(when_Pipeline_l124_64) begin memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264) begin execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_1) begin execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_2) begin execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_3) begin execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_4) begin execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_5) begin execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_6) begin execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_7) begin execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_8) begin execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_9) begin execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_10) begin execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_11) begin execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_12) begin execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_13) begin execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_14) begin execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_15) begin execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_16) begin execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_17) begin execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_18) begin execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_19) begin execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_20) begin execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_21) begin execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_22) begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if(when_CsrPlugin_l1264_23) begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(when_CsrPlugin_l1264_24) begin execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_25) begin execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_26) begin execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_27) begin execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_28) begin execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_29) begin execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_30) begin execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_31) begin execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_32) begin execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_33) begin execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_34) begin execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_35) begin execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_36) begin execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_37) begin execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_38) begin execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); end - if((! execute_arbitration_isStuck))begin + if(when_CsrPlugin_l1264_39) begin execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); - end - if((! execute_arbitration_isStuck))begin - execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); - end - if(execute_CsrPlugin_csr_836)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mip_MSIP <= _zz_387[0]; + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; end end - if(execute_CsrPlugin_csr_773)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; - CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; end end - if(execute_CsrPlugin_csr_833)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_832)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_834)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcause_interrupt <= _zz_391[0]; - CsrPlugin_mcause_exceptionCode <= execute_CsrPlugin_writeData[3 : 0]; + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; end end - if(execute_CsrPlugin_csr_835)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mtval <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2816)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2944)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_mcycle[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2818)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[31 : 0] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2946)begin - if(execute_CsrPlugin_writeEnable)begin - CsrPlugin_minstret[63 : 32] <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2820)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_152 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2820) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2821)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_153 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2821) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2822)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_154 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2822) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2823)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_155 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2823) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_1 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2824)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_156 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2824) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2825)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_157 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2825) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2826)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_158 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2826) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2827)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_159 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2827) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2828)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_160 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2828) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2829)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_161 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2829) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2830)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_162 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2830) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2831)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_163 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2831) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2832)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_164 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2832) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2833)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_165 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2833) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2834)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_166 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2834) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2835)begin - if(execute_CsrPlugin_writeEnable)begin - _zz_167 <= execute_CsrPlugin_writeData[31 : 0]; + if(execute_CsrPlugin_csr_2835) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_when_GenCoreDefault_l367_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end - always @ (posedge clk) begin + always @(posedge clk) begin DebugPlugin_firstCycle <= 1'b0; - if(debug_bus_cmd_ready)begin + if(debug_bus_cmd_ready) begin DebugPlugin_firstCycle <= 1'b1; end DebugPlugin_secondCycle <= DebugPlugin_firstCycle; DebugPlugin_isPipBusy <= (({writeBack_arbitration_isValid,{memory_arbitration_isValid,{execute_arbitration_isValid,decode_arbitration_isValid}}} != 4'b0000) || IBusCachedPlugin_incomingInstruction); - if(writeBack_arbitration_isValid)begin - DebugPlugin_busReadDataReg <= _zz_57; + if(writeBack_arbitration_isValid) begin + DebugPlugin_busReadDataReg <= _zz_decode_RS2_2; end - _zz_178 <= debug_bus_cmd_payload_address[2]; - if(_zz_263)begin + _zz_when_DebugPlugin_l244 <= debug_bus_cmd_payload_address[2]; + if(when_DebugPlugin_l284) begin DebugPlugin_busReadDataReg <= execute_PC; end DebugPlugin_resetIt_regNext <= DebugPlugin_resetIt; end - always @ (posedge clk) begin + always @(posedge clk) begin if(debugReset) begin DebugPlugin_resetIt <= 1'b0; DebugPlugin_haltIt <= 1'b0; DebugPlugin_stepIt <= 1'b0; DebugPlugin_godmode <= 1'b0; DebugPlugin_haltedByBreak <= 1'b0; + DebugPlugin_debugUsed <= 1'b0; + DebugPlugin_disableEbreak <= 1'b0; end else begin - if((DebugPlugin_haltIt && (! DebugPlugin_isPipBusy)))begin + if(when_DebugPlugin_l225) begin DebugPlugin_godmode <= 1'b1; end - if(debug_bus_cmd_valid)begin - case(_zz_283) + if(debug_bus_cmd_valid) begin + DebugPlugin_debugUsed <= 1'b1; + end + if(debug_bus_cmd_valid) begin + case(switch_DebugPlugin_l256) 6'h0 : begin - if(debug_bus_cmd_payload_wr)begin + if(debug_bus_cmd_payload_wr) begin DebugPlugin_stepIt <= debug_bus_cmd_payload_data[4]; - if(debug_bus_cmd_payload_data[16])begin + if(when_DebugPlugin_l260) begin DebugPlugin_resetIt <= 1'b1; end - if(debug_bus_cmd_payload_data[24])begin + if(when_DebugPlugin_l260_1) begin DebugPlugin_resetIt <= 1'b0; end - if(debug_bus_cmd_payload_data[17])begin + if(when_DebugPlugin_l261) begin DebugPlugin_haltIt <= 1'b1; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l261_1) begin DebugPlugin_haltIt <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l262) begin DebugPlugin_haltedByBreak <= 1'b0; end - if(debug_bus_cmd_payload_data[25])begin + if(when_DebugPlugin_l263) begin DebugPlugin_godmode <= 1'b0; end + if(when_DebugPlugin_l264) begin + DebugPlugin_disableEbreak <= 1'b1; + end + if(when_DebugPlugin_l264_1) begin + DebugPlugin_disableEbreak <= 1'b0; + end end end default : begin end endcase end - if(_zz_263)begin - if(_zz_265)begin + if(when_DebugPlugin_l284) begin + if(when_DebugPlugin_l287) begin DebugPlugin_haltIt <= 1'b1; DebugPlugin_haltedByBreak <= 1'b1; end end - if(_zz_268)begin - if(decode_arbitration_isValid)begin + if(when_DebugPlugin_l300) begin + if(decode_arbitration_isValid) begin DebugPlugin_haltIt <= 1'b1; end end @@ -6132,9 +6484,8 @@ endmodule module DataCache ( input io_cpu_execute_isValid, input [31:0] io_cpu_execute_address, - output io_cpu_execute_haltIt, + output reg io_cpu_execute_haltIt, input io_cpu_execute_args_wr, - input [31:0] io_cpu_execute_args_data, input [1:0] io_cpu_execute_args_size, input io_cpu_execute_args_totalyConsistent, output io_cpu_execute_refilling, @@ -6156,6 +6507,7 @@ module DataCache ( input io_cpu_writeBack_isUser, output reg io_cpu_writeBack_haltIt, output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, output reg [31:0] io_cpu_writeBack_data, input [31:0] io_cpu_writeBack_address, output io_cpu_writeBack_mmuException, @@ -6171,9 +6523,10 @@ module DataCache ( input io_cpu_writeBack_fence_PO, input io_cpu_writeBack_fence_PI, input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, output reg io_cpu_redo, input io_cpu_flush_valid, - output reg io_cpu_flush_ready, + output io_cpu_flush_ready, output reg io_mem_cmd_valid, input io_mem_cmd_ready, output reg io_mem_cmd_payload_wr, @@ -6181,7 +6534,7 @@ module DataCache ( output reg [31:0] io_mem_cmd_payload_address, output [31:0] io_mem_cmd_payload_data, output [3:0] io_mem_cmd_payload_mask, - output reg [2:0] io_mem_cmd_payload_length, + output reg [2:0] io_mem_cmd_payload_size, output io_mem_cmd_payload_last, input io_mem_rsp_valid, input io_mem_rsp_payload_last, @@ -6190,24 +6543,15 @@ module DataCache ( input clk, input reset ); - reg [21:0] _zz_10; - reg [31:0] _zz_11; - wire _zz_12; - wire _zz_13; - wire _zz_14; - wire _zz_15; - wire _zz_16; - wire _zz_17; - wire _zz_18; - wire [0:0] _zz_19; - wire [0:0] _zz_20; - wire [9:0] _zz_21; - wire [9:0] _zz_22; - wire [0:0] _zz_23; - wire [0:0] _zz_24; - wire [2:0] _zz_25; - wire [1:0] _zz_26; - wire [21:0] _zz_27; + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; reg _zz_1; reg _zz_2; wire haltCpu; @@ -6232,40 +6576,48 @@ module DataCache ( reg [9:0] dataWriteCmd_payload_address; reg [31:0] dataWriteCmd_payload_data; reg [3:0] dataWriteCmd_payload_mask; - wire _zz_3; + wire _zz_ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_valid; wire ways_0_tagsReadRsp_error; wire [19:0] ways_0_tagsReadRsp_address; - wire [21:0] _zz_4; - wire _zz_5; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRspMem; wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; wire rspSync; wire rspLast; reg memCmdSent; - reg [3:0] _zz_6; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; wire [3:0] stage0_mask; wire [0:0] stage0_dataColisions; wire [0:0] stage0_wayInvalidate; wire stage0_isAmo; + wire when_DataCache_l763; reg stageA_request_wr; - reg [31:0] stageA_request_data; reg [1:0] stageA_request_size; reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; reg [3:0] stageA_mask; wire stageA_isAmo; wire stageA_isLrsc; wire [0:0] stageA_wayHits; - wire [0:0] _zz_7; + wire when_DataCache_l763_2; reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; reg [0:0] stage0_dataColisions_regNextWhen; - wire [0:0] _zz_8; + wire [0:0] _zz_stageA_dataColisions; wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; reg stageB_request_wr; - reg [31:0] stageB_request_data; reg [1:0] stageB_request_size; reg stageB_request_totalyConsistent; reg stageB_mmuRspFreeze; + wire when_DataCache_l816; reg [31:0] stageB_mmuRsp_physicalAddress; reg stageB_mmuRsp_isIoAccess; reg stageB_mmuRsp_isPaging; @@ -6275,23 +6627,33 @@ module DataCache ( reg stageB_mmuRsp_exception; reg stageB_mmuRsp_refilling; reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; reg stageB_tagsReadRsp_0_valid; reg stageB_tagsReadRsp_0_error; reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; reg [0:0] stageB_wayInvalidate; wire stageB_consistancyHazard; + wire when_DataCache_l812_1; reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; reg stageB_unaligned; + wire when_DataCache_l812_3; reg [0:0] stageB_waysHitsBeforeInvalidate; wire [0:0] stageB_waysHits; wire stageB_waysHit; wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; reg [3:0] stageB_mask; reg stageB_loaderValid; wire [31:0] stageB_ioMemRspMuxed; - reg stageB_flusher_valid; + reg stageB_flusher_waitDone; wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; reg stageB_flusher_start; wire stageB_isAmo; wire stageB_isAmoCached; @@ -6299,10 +6661,18 @@ module DataCache ( wire stageB_isExternalAmo; wire [31:0] stageB_requestDataBypass; reg stageB_cpuWriteToCache; + wire when_DataCache_l911; wire stageB_badPermissions; wire stageB_loadStoreFault; wire stageB_bypassCache; - wire [0:0] _zz_9; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; reg loader_valid; reg loader_counter_willIncrement; wire loader_counter_willClear; @@ -6314,59 +6684,54 @@ module DataCache ( reg loader_error; wire loader_kill; reg loader_killReg; + wire when_DataCache_l1075; wire loader_done; + wire when_DataCache_l1103; reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; - reg [7:0] _zz_28; - reg [7:0] _zz_29; - reg [7:0] _zz_30; - reg [7:0] _zz_31; - - assign _zz_12 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); - assign _zz_13 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); - assign _zz_14 = ((loader_valid && io_mem_rsp_valid) && rspLast); - assign _zz_15 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); - assign _zz_16 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); - assign _zz_17 = (! stageB_flusher_hold); - assign _zz_18 = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); - assign _zz_19 = _zz_4[0 : 0]; - assign _zz_20 = _zz_4[1 : 1]; - assign _zz_21 = (io_cpu_execute_address[11 : 2] >>> 0); - assign _zz_22 = (io_cpu_memory_address[11 : 2] >>> 0); - assign _zz_23 = 1'b1; - assign _zz_24 = loader_counter_willIncrement; - assign _zz_25 = {2'd0, _zz_24}; - assign _zz_26 = {loader_waysAllocator,loader_waysAllocator[0]}; - assign _zz_27 = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; - always @ (posedge clk) begin - if(_zz_3) begin - _zz_10 <= ways_0_tags[tagsReadCmd_payload]; - end - end - - always @ (posedge clk) begin + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[tagsWriteCmd_payload_address] <= _zz_27; + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; end end - always @ (*) begin - _zz_11 = {_zz_31, _zz_30, _zz_29, _zz_28}; + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_28 <= ways_0_data_symbol0[dataReadCmd_payload]; - _zz_29 <= ways_0_data_symbol1[dataReadCmd_payload]; - _zz_30 <= ways_0_data_symbol2[dataReadCmd_payload]; - _zz_31 <= ways_0_data_symbol3[dataReadCmd_payload]; + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(dataWriteCmd_payload_mask[0] && _zz_1) begin ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; end @@ -6381,274 +6746,293 @@ module DataCache ( end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + if(when_DataCache_l637) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + if(when_DataCache_l634) begin _zz_2 = 1'b1; end end assign haltCpu = 1'b0; - assign _zz_3 = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); - assign _zz_4 = _zz_10; - assign ways_0_tagsReadRsp_valid = _zz_19[0]; - assign ways_0_tagsReadRsp_error = _zz_20[0]; - assign ways_0_tagsReadRsp_address = _zz_4[21 : 2]; - assign _zz_5 = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); - assign ways_0_dataReadRspMem = _zz_11; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; - always @ (*) begin + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin tagsReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin tagsReadCmd_valid = 1'b1; end end - always @ (*) begin - tagsReadCmd_payload = 7'h0; - if(_zz_12)begin + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; end end - always @ (*) begin + always @(*) begin dataReadCmd_valid = 1'b0; - if(_zz_12)begin + if(when_DataCache_l656) begin dataReadCmd_valid = 1'b1; end end - always @ (*) begin - dataReadCmd_payload = 10'h0; - if(_zz_12)begin + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin dataReadCmd_payload = io_cpu_execute_address[11 : 2]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_valid = 1'b0; - if(stageB_flusher_valid)begin - tagsWriteCmd_valid = stageB_flusher_valid; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; end - if(_zz_13)begin + if(when_DataCache_l1051) begin tagsWriteCmd_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_way = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_way = 1'b1; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - tagsWriteCmd_payload_address = 7'h0; - if(stageB_flusher_valid)begin - tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_valid = 1'bx; - if(stageB_flusher_valid)begin + if(when_DataCache_l842) begin tagsWriteCmd_payload_data_valid = 1'b0; end - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); end end - always @ (*) begin + always @(*) begin tagsWriteCmd_payload_data_error = 1'bx; - if(loader_done)begin + if(loader_done) begin tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); end end - always @ (*) begin - tagsWriteCmd_payload_data_address = 20'h0; - if(loader_done)begin + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; end end - always @ (*) begin + always @(*) begin dataWriteCmd_valid = 1'b0; - if(stageB_cpuWriteToCache)begin - if((stageB_request_wr && stageB_waysHit))begin + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin dataWriteCmd_valid = 1'b1; end end - if(_zz_13)begin + if(when_DataCache_l1051) begin dataWriteCmd_valid = 1'b0; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_valid = 1'b1; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_way = 1'bx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_way = stageB_waysHits; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_way = loader_waysAllocator; end end - always @ (*) begin - dataWriteCmd_payload_address = 10'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; end end - always @ (*) begin - dataWriteCmd_payload_data = 32'h0; - if(stageB_cpuWriteToCache)begin + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_data = io_mem_rsp_payload_data; end end - always @ (*) begin + always @(*) begin dataWriteCmd_payload_mask = 4'bxxxx; - if(stageB_cpuWriteToCache)begin + if(stageB_cpuWriteToCache) begin dataWriteCmd_payload_mask = 4'b0000; - if(_zz_23[0])begin + if(_zz_when[0]) begin dataWriteCmd_payload_mask[3 : 0] = stageB_mask; end end - if(_zz_14)begin + if(when_DataCache_l1075) begin dataWriteCmd_payload_mask = 4'b1111; end end - assign io_cpu_execute_haltIt = 1'b0; + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + assign rspSync = 1'b1; assign rspLast = 1'b1; - always @ (*) begin + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; case(io_cpu_execute_args_size) 2'b00 : begin - _zz_6 = 4'b0001; + _zz_stage0_mask = 4'b0001; end 2'b01 : begin - _zz_6 = 4'b0011; + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; end default : begin - _zz_6 = 4'b1111; end endcase end - assign stage0_mask = (_zz_6 <<< io_cpu_execute_address[1 : 0]); - assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_21)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); assign stage0_wayInvalidate = 1'b0; assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); assign io_cpu_memory_isWrite = stageA_request_wr; assign stageA_isAmo = 1'b0; assign stageA_isLrsc = 1'b0; - assign _zz_7[0] = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); - assign stageA_wayHits = _zz_7; - assign _zz_8[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_22)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); - assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_8); - always @ (*) begin + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_mmuRspFreeze = 1'b0; - if((stageB_loaderValid || loader_valid))begin + if(when_DataCache_l1110) begin stageB_mmuRspFreeze = 1'b1; end end + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); assign stageB_waysHit = (stageB_waysHits != 1'b0); assign stageB_dataMux = stageB_dataReadRsp_0; - always @ (*) begin + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin stageB_loaderValid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin - if(io_mem_cmd_ready)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin stageB_loaderValid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin stageB_loaderValid = 1'b0; end end assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; - always @ (*) begin - io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; - if(stageB_flusher_valid)begin - io_cpu_writeBack_haltIt = 1'b1; - end - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin - if(((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready))begin + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin io_cpu_writeBack_haltIt = 1'b0; end end else begin - if(_zz_16)begin - if(((! stageB_request_wr) || io_mem_cmd_ready))begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin io_cpu_writeBack_haltIt = 1'b0; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_cpu_writeBack_haltIt = 1'b0; end end assign stageB_flusher_hold = 1'b0; - always @ (*) begin - io_cpu_flush_ready = 1'b0; - if(stageB_flusher_start)begin - io_cpu_flush_ready = 1'b1; - end - end - + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); assign stageB_isAmo = 1'b0; assign stageB_isAmoCached = 1'b0; assign stageB_isExternalLsrc = 1'b0; assign stageB_isExternalAmo = 1'b0; - assign stageB_requestDataBypass = stageB_request_data; - always @ (*) begin + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin stageB_cpuWriteToCache = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin stageB_cpuWriteToCache = 1'b1; end end @@ -6656,89 +7040,73 @@ module DataCache ( end end + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); - always @ (*) begin + always @(*) begin io_cpu_redo = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - if((((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)))begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin io_cpu_redo = 1'b1; end end end end end - if((io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)))begin + if(when_DataCache_l1060) begin io_cpu_redo = 1'b1; end - if((loader_valid && (! loader_valid_regNext)))begin + if(when_DataCache_l1107) begin io_cpu_redo = 1'b1; end end - always @ (*) begin + always @(*) begin io_cpu_writeBack_accessError = 1'b0; - if(stageB_bypassCache)begin + if(stageB_bypassCache) begin io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); end else begin - io_cpu_writeBack_accessError = (((stageB_waysHits & _zz_9) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); end end assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); assign io_cpu_writeBack_isWrite = stageB_request_wr; - always @ (*) begin + always @(*) begin io_mem_cmd_valid = 1'b0; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(_zz_15)begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin io_mem_cmd_valid = (! memCmdSent); end else begin - if(_zz_16)begin - if(stageB_request_wr)begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin io_mem_cmd_valid = 1'b1; end end else begin - if((! memCmdSent))begin + if(when_DataCache_l1017) begin io_mem_cmd_valid = 1'b1; end end end end end - if(_zz_13)begin + if(when_DataCache_l1051) begin io_mem_cmd_valid = 1'b0; end end - always @ (*) begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],2'b00}; - end else begin - io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; - end - end - end - end - end - - always @ (*) begin - io_mem_cmd_payload_length = 3'b000; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(_zz_16)begin - io_mem_cmd_payload_length = 3'b000; - end else begin - io_mem_cmd_payload_length = 3'b111; + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; end end end @@ -6746,12 +7114,12 @@ module DataCache ( end assign io_mem_cmd_payload_last = 1'b1; - always @ (*) begin + always @(*) begin io_mem_cmd_payload_wr = stageB_request_wr; - if(io_cpu_writeBack_isValid)begin - if(! stageB_isExternalAmo) begin - if(! _zz_15) begin - if(! _zz_16) begin + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin io_mem_cmd_payload_wr = 1'b0; end end @@ -6762,20 +7130,40 @@ module DataCache ( assign io_mem_cmd_payload_mask = stageB_mask; assign io_mem_cmd_payload_data = stageB_requestDataBypass; assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); assign io_cpu_writeBack_keepMemRspData = 1'b0; - always @ (*) begin - if(stageB_bypassCache)begin + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin io_cpu_writeBack_data = stageB_ioMemRspMuxed; end else begin io_cpu_writeBack_data = stageB_dataMux; end end - assign _zz_9[0] = stageB_tagsReadRsp_0_error; - always @ (*) begin + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin loader_counter_willIncrement = 1'b0; - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_counter_willIncrement = 1'b1; end end @@ -6783,45 +7171,47 @@ module DataCache ( assign loader_counter_willClear = 1'b0; assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); - always @ (*) begin - loader_counter_valueNext = (loader_counter_value + _zz_25); - if(loader_counter_willClear)begin + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin loader_counter_valueNext = 3'b000; end end assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); assign io_cpu_execute_refilling = loader_valid; - always @ (posedge clk) begin + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin tagsWriteLastCmd_valid <= tagsWriteCmd_valid; tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763) begin stageA_request_wr <= io_cpu_execute_args_wr; - stageA_request_data <= io_cpu_execute_args_data; stageA_request_size <= io_cpu_execute_args_size; stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_1) begin stageA_mask <= stage0_mask; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_2) begin stageA_wayInvalidate <= stage0_wayInvalidate; end - if((! io_cpu_memory_isStuck))begin + if(when_DataCache_l763_3) begin stage0_dataColisions_regNextWhen <= stage0_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l814) begin stageB_request_wr <= stageA_request_wr; - stageB_request_data <= stageA_request_data; stageB_request_size <= stageA_request_size; stageB_request_totalyConsistent <= stageA_request_totalyConsistent; end - if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + if(when_DataCache_l816) begin stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; @@ -6832,46 +7222,37 @@ module DataCache ( stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813) begin stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l813_1) begin stageB_dataReadRsp_0 <= ways_0_dataReadRsp; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812) begin stageB_wayInvalidate <= stageA_wayInvalidate; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_1) begin stageB_dataColisions <= stageA_dataColisions; end - if((! io_cpu_writeBack_isStuck))begin - stageB_unaligned <= (((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)) || ((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))); + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_3) begin stageB_waysHitsBeforeInvalidate <= stageA_wayHits; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l812_4) begin stageB_mask <= stageA_mask; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(_zz_18)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); - end - end - end - if(stageB_flusher_start)begin - stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; - end loader_valid_regNext <= loader_valid; end - always @ (posedge clk) begin + always @(posedge clk) begin if(reset) begin memCmdSent <= 1'b0; - stageB_flusher_valid <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; stageB_flusher_start <= 1'b1; loader_valid <= 1'b0; loader_counter_value <= 3'b000; @@ -6879,50 +7260,51 @@ module DataCache ( loader_error <= 1'b0; loader_killReg <= 1'b0; end else begin - if(io_mem_cmd_ready)begin + if(io_mem_cmd_fire) begin memCmdSent <= 1'b1; end - if((! io_cpu_writeBack_isStuck))begin + if(when_DataCache_l678) begin memCmdSent <= 1'b0; end - if(stageB_flusher_valid)begin - if(_zz_17)begin - if(! _zz_18) begin - stageB_flusher_valid <= 1'b0; - end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); end end - stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); - if(stageB_flusher_start)begin - stageB_flusher_valid <= 1'b1; + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; end `ifndef SYNTHESIS `ifdef FORMAL assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); `else if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin - $display("FAILURE writeBack stuck by another plugin is not allowed"); - $finish; + $display("ERROR writeBack stuck by another plugin is not allowed"); end `endif `endif - if(stageB_loaderValid)begin + if(stageB_loaderValid) begin loader_valid <= 1'b1; end loader_counter_value <= loader_counter_valueNext; - if(loader_kill)begin + if(loader_kill) begin loader_killReg <= 1'b1; end - if(_zz_14)begin + if(when_DataCache_l1075) begin loader_error <= (loader_error || io_mem_rsp_payload_error); end - if(loader_done)begin + if(loader_done) begin loader_valid <= 1'b0; loader_error <= 1'b0; loader_killReg <= 1'b0; end - if((! loader_valid))begin - loader_waysAllocator <= _zz_26[0:0]; + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; end end end @@ -6969,18 +7351,14 @@ module InstructionCache ( input io_mem_rsp_valid, input [31:0] io_mem_rsp_payload_data, input io_mem_rsp_payload_error, - input [2:0] _zz_9, - input [31:0] _zz_10, + input [2:0] _zz_when_Fetcher_l398, + input [31:0] _zz_io_cpu_fetch_data_regNextWhen, input clk, input reset ); - reg [31:0] _zz_11; - reg [22:0] _zz_12; - wire _zz_13; - wire _zz_14; - wire [0:0] _zz_15; - wire [0:0] _zz_16; - wire [22:0] _zz_17; + reg [31:0] _zz_banks_0_port1; + reg [22:0] _zz_ways_0_tags_port1; + wire [22:0] _zz_ways_0_tags_port; reg _zz_1; reg _zz_2; reg lineLoader_fire; @@ -6989,8 +7367,13 @@ module InstructionCache ( reg lineLoader_hadError; reg lineLoader_flushPending; reg [6:0] lineLoader_flushCounter; - reg _zz_3; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; reg lineLoader_wayToAllocate_willIncrement; wire lineLoader_wayToAllocate_willClear; wire lineLoader_wayToAllocate_willOverflowIfInc; @@ -7004,22 +7387,25 @@ module InstructionCache ( wire lineLoader_write_data_0_valid; wire [8:0] lineLoader_write_data_0_payload_address; wire [31:0] lineLoader_write_data_0_payload_data; - wire [8:0] _zz_4; - wire _zz_5; + wire when_InstructionCache_l401; + wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; wire [31:0] fetchStage_read_banksValue_0_dataMem; wire [31:0] fetchStage_read_banksValue_0_data; - wire [5:0] _zz_6; - wire _zz_7; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; wire fetchStage_read_waysValues_0_tag_valid; wire fetchStage_read_waysValues_0_tag_error; wire [20:0] fetchStage_read_waysValues_0_tag_address; - wire [22:0] _zz_8; + wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; wire fetchStage_hit_hits_0; wire fetchStage_hit_valid; wire fetchStage_hit_error; wire [31:0] fetchStage_hit_data; wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; reg [31:0] decodeStage_mmuRsp_physicalAddress; reg decodeStage_mmuRsp_isIoAccess; reg decodeStage_mmuRsp_isPaging; @@ -7029,82 +7415,86 @@ module InstructionCache ( reg decodeStage_mmuRsp_exception; reg decodeStage_mmuRsp_refilling; reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; reg decodeStage_hit_error; + wire when_Fetcher_l398; (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; - assign _zz_13 = (! lineLoader_flushCounter[6]); - assign _zz_14 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); - assign _zz_15 = _zz_8[0 : 0]; - assign _zz_16 = _zz_8[1 : 1]; - assign _zz_17 = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; - always @ (posedge clk) begin + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin if(_zz_1) begin banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; end end - always @ (posedge clk) begin - if(_zz_5) begin - _zz_11 <= banks_0[_zz_4]; + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; end end - always @ (posedge clk) begin + always @(posedge clk) begin if(_zz_2) begin - ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17; + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; end end - always @ (posedge clk) begin - if(_zz_7) begin - _zz_12 <= ways_0_tags[_zz_6]; + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; end end - always @ (*) begin + always @(*) begin _zz_1 = 1'b0; - if(lineLoader_write_data_0_valid)begin + if(lineLoader_write_data_0_valid) begin _zz_1 = 1'b1; end end - always @ (*) begin + always @(*) begin _zz_2 = 1'b0; - if(lineLoader_write_tag_0_valid)begin + if(lineLoader_write_tag_0_valid) begin _zz_2 = 1'b1; end end - always @ (*) begin + always @(*) begin lineLoader_fire = 1'b0; - if(io_mem_rsp_valid)begin - if((lineLoader_wordIndex == 3'b111))begin + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin lineLoader_fire = 1'b1; end end end - always @ (*) begin + always @(*) begin io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); - if(_zz_13)begin + if(when_InstructionCache_l338) begin io_cpu_prefetch_haltIt = 1'b1; end - if((! _zz_3))begin + if(when_InstructionCache_l342) begin io_cpu_prefetch_haltIt = 1'b1; end - if(io_flush)begin + if(io_flush) begin io_cpu_prefetch_haltIt = 1'b1; end end + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; assign io_mem_cmd_payload_size = 3'b101; - always @ (*) begin + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin lineLoader_wayToAllocate_willIncrement = 1'b0; - if((! lineLoader_valid))begin + if(when_Utils_l357) begin lineLoader_wayToAllocate_willIncrement = 1'b1; end end @@ -7120,30 +7510,36 @@ module InstructionCache ( assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; - assign _zz_4 = io_cpu_prefetch_pc[10 : 2]; - assign _zz_5 = (! io_cpu_fetch_isStuck); - assign fetchStage_read_banksValue_0_dataMem = _zz_11; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; - assign _zz_6 = io_cpu_prefetch_pc[10 : 5]; - assign _zz_7 = (! io_cpu_fetch_isStuck); - assign _zz_8 = _zz_12; - assign fetchStage_read_waysValues_0_tag_valid = _zz_15[0]; - assign fetchStage_read_waysValues_0_tag_error = _zz_16[0]; - assign fetchStage_read_waysValues_0_tag_address = _zz_8[22 : 2]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2]; assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; assign fetchStage_hit_word = fetchStage_hit_data; assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; - always @ (posedge clk) begin + assign when_Fetcher_l398 = (_zz_when_Fetcher_l398 != 3'b000); + always @(posedge clk) begin if(reset) begin lineLoader_valid <= 1'b0; lineLoader_hadError <= 1'b0; @@ -7151,51 +7547,51 @@ module InstructionCache ( lineLoader_cmdSent <= 1'b0; lineLoader_wordIndex <= 3'b000; end else begin - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_valid <= 1'b0; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_hadError <= 1'b0; end - if(io_cpu_fill_valid)begin + if(io_cpu_fill_valid) begin lineLoader_valid <= 1'b1; end - if(io_flush)begin + if(io_flush) begin lineLoader_flushPending <= 1'b1; end - if(_zz_14)begin + if(when_InstructionCache_l351) begin lineLoader_flushPending <= 1'b0; end - if((io_mem_cmd_valid && io_mem_cmd_ready))begin + if(io_mem_cmd_fire) begin lineLoader_cmdSent <= 1'b1; end - if(lineLoader_fire)begin + if(lineLoader_fire) begin lineLoader_cmdSent <= 1'b0; end - if(io_mem_rsp_valid)begin + if(io_mem_rsp_valid) begin lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); - if(io_mem_rsp_payload_error)begin + if(io_mem_rsp_payload_error) begin lineLoader_hadError <= 1'b1; end end end end - always @ (posedge clk) begin - if(io_cpu_fill_valid)begin + always @(posedge clk) begin + if(io_cpu_fill_valid) begin lineLoader_address <= io_cpu_fill_payload; end - if(_zz_13)begin + if(when_InstructionCache_l338) begin lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); end - _zz_3 <= lineLoader_flushCounter[6]; - if(_zz_14)begin + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin lineLoader_flushCounter <= 7'h0; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l435) begin io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459) begin decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; @@ -7206,14 +7602,14 @@ module InstructionCache ( decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_1) begin decodeStage_hit_valid <= fetchStage_hit_valid; end - if((! io_cpu_decode_isStuck))begin + if(when_InstructionCache_l459_2) begin decodeStage_hit_error <= fetchStage_hit_error; end - if((_zz_9 != 3'b000))begin - io_cpu_fetch_data_regNextWhen <= _zz_10; + if(when_Fetcher_l398) begin + io_cpu_fetch_data_regNextWhen <= _zz_io_cpu_fetch_data_regNextWhen; end end From 6f2afa7a1e6bd4ca7cdea67d2e078179c183b833 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Wed, 29 Sep 2021 14:10:13 -0700 Subject: [PATCH 27/30] Add 'slim' variant for completeness. Also remove obsolete genWrapper.py script. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 3 + .../verilog/VexRiscv_Slim.v | 6671 +++++++++++++++++ .../verilog/VexRiscv_Slim.yaml | 4 + pythondata_cpu_vexriscv/verilog/genWrapper.py | 115 - 4 files changed, 6678 insertions(+), 115 deletions(-) create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.v create mode 100644 pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.yaml delete mode 100755 pythondata_cpu_vexriscv/verilog/genWrapper.py diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index c504f76..682a147 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -50,6 +50,9 @@ VexRiscv_PerfCfu.v: $(SRC) VexRiscv_PerfCfuDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_PerfCfuDebug" +VexRiscv_Slim.v: $(SRC) + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all --outputFile VexRiscv_Slim" + VexRiscv_SlimCfu.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 4096 --iCacheSize 2048 --csrPluginConfig all --cfu true --outputFile VexRiscv_SlimCfu" diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.v new file mode 100644 index 0000000..0bb024f --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.v @@ -0,0 +1,6671 @@ +// Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 +// Component : VexRiscv +// Git hash : 9f85993307e913719381223ade365fdc0b477d2e + + +`define EnvCtrlEnum_binary_sequential_type [1:0] +`define EnvCtrlEnum_binary_sequential_NONE 2'b00 +`define EnvCtrlEnum_binary_sequential_XRET 2'b01 +`define EnvCtrlEnum_binary_sequential_WFI 2'b10 +`define EnvCtrlEnum_binary_sequential_ECALL 2'b11 + +`define BranchCtrlEnum_binary_sequential_type [1:0] +`define BranchCtrlEnum_binary_sequential_INC 2'b00 +`define BranchCtrlEnum_binary_sequential_B 2'b01 +`define BranchCtrlEnum_binary_sequential_JAL 2'b10 +`define BranchCtrlEnum_binary_sequential_JALR 2'b11 + +`define ShiftCtrlEnum_binary_sequential_type [1:0] +`define ShiftCtrlEnum_binary_sequential_DISABLE_1 2'b00 +`define ShiftCtrlEnum_binary_sequential_SLL_1 2'b01 +`define ShiftCtrlEnum_binary_sequential_SRL_1 2'b10 +`define ShiftCtrlEnum_binary_sequential_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_binary_sequential_type [1:0] +`define AluBitwiseCtrlEnum_binary_sequential_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_binary_sequential_OR_1 2'b01 +`define AluBitwiseCtrlEnum_binary_sequential_AND_1 2'b10 + +`define Src2CtrlEnum_binary_sequential_type [1:0] +`define Src2CtrlEnum_binary_sequential_RS 2'b00 +`define Src2CtrlEnum_binary_sequential_IMI 2'b01 +`define Src2CtrlEnum_binary_sequential_IMS 2'b10 +`define Src2CtrlEnum_binary_sequential_PC 2'b11 + +`define AluCtrlEnum_binary_sequential_type [1:0] +`define AluCtrlEnum_binary_sequential_ADD_SUB 2'b00 +`define AluCtrlEnum_binary_sequential_SLT_SLTU 2'b01 +`define AluCtrlEnum_binary_sequential_BITWISE 2'b10 + +`define Src1CtrlEnum_binary_sequential_type [1:0] +`define Src1CtrlEnum_binary_sequential_RS 2'b00 +`define Src1CtrlEnum_binary_sequential_IMU 2'b01 +`define Src1CtrlEnum_binary_sequential_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_binary_sequential_URS1 2'b11 + + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [2:0] iBusWishbone_CTI, + output [1:0] iBusWishbone_BTE, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [2:0] dBusWishbone_CTI, + output [1:0] dBusWishbone_BTE, + input clk, + input reset +); + wire IBusCachedPlugin_cache_io_flush; + wire IBusCachedPlugin_cache_io_cpu_prefetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isValid; + wire IBusCachedPlugin_cache_io_cpu_fetch_isStuck; + wire IBusCachedPlugin_cache_io_cpu_fetch_isRemoved; + wire IBusCachedPlugin_cache_io_cpu_decode_isValid; + wire IBusCachedPlugin_cache_io_cpu_decode_isStuck; + wire IBusCachedPlugin_cache_io_cpu_decode_isUser; + reg IBusCachedPlugin_cache_io_cpu_fill_valid; + wire dataCache_1_io_cpu_execute_isValid; + wire [31:0] dataCache_1_io_cpu_execute_address; + wire dataCache_1_io_cpu_memory_isValid; + wire [31:0] dataCache_1_io_cpu_memory_address; + reg dataCache_1_io_cpu_memory_mmuRsp_isIoAccess; + reg dataCache_1_io_cpu_writeBack_isValid; + wire dataCache_1_io_cpu_writeBack_isUser; + wire [31:0] dataCache_1_io_cpu_writeBack_storeData; + wire [31:0] dataCache_1_io_cpu_writeBack_address; + wire dataCache_1_io_cpu_writeBack_fence_SW; + wire dataCache_1_io_cpu_writeBack_fence_SR; + wire dataCache_1_io_cpu_writeBack_fence_SO; + wire dataCache_1_io_cpu_writeBack_fence_SI; + wire dataCache_1_io_cpu_writeBack_fence_PW; + wire dataCache_1_io_cpu_writeBack_fence_PR; + wire dataCache_1_io_cpu_writeBack_fence_PO; + wire dataCache_1_io_cpu_writeBack_fence_PI; + wire [3:0] dataCache_1_io_cpu_writeBack_fence_FM; + wire dataCache_1_io_cpu_flush_valid; + wire dataCache_1_io_mem_cmd_ready; + reg [31:0] _zz_RegFilePlugin_regFile_port0; + reg [31:0] _zz_RegFilePlugin_regFile_port1; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1_io_cpu_execute_haltIt; + wire dataCache_1_io_cpu_execute_refilling; + wire dataCache_1_io_cpu_memory_isWrite; + wire dataCache_1_io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1_io_cpu_writeBack_data; + wire dataCache_1_io_cpu_writeBack_mmuException; + wire dataCache_1_io_cpu_writeBack_unalignedAccess; + wire dataCache_1_io_cpu_writeBack_accessError; + wire dataCache_1_io_cpu_writeBack_isWrite; + wire dataCache_1_io_cpu_writeBack_keepMemRspData; + wire dataCache_1_io_cpu_writeBack_exclusiveOk; + wire dataCache_1_io_cpu_flush_ready; + wire dataCache_1_io_cpu_redo; + wire dataCache_1_io_mem_cmd_valid; + wire dataCache_1_io_mem_cmd_payload_wr; + wire dataCache_1_io_mem_cmd_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_payload_size; + wire dataCache_1_io_mem_cmd_payload_last; + wire [51:0] _zz_memory_MUL_LOW; + wire [51:0] _zz_memory_MUL_LOW_1; + wire [51:0] _zz_memory_MUL_LOW_2; + wire [51:0] _zz_memory_MUL_LOW_3; + wire [32:0] _zz_memory_MUL_LOW_4; + wire [51:0] _zz_memory_MUL_LOW_5; + wire [49:0] _zz_memory_MUL_LOW_6; + wire [51:0] _zz_memory_MUL_LOW_7; + wire [49:0] _zz_memory_MUL_LOW_8; + wire [31:0] _zz_execute_SHIFT_RIGHT; + wire [32:0] _zz_execute_SHIFT_RIGHT_1; + wire [32:0] _zz_execute_SHIFT_RIGHT_2; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_1; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_2; + wire _zz_decode_LEGAL_INSTRUCTION_3; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_4; + wire [13:0] _zz_decode_LEGAL_INSTRUCTION_5; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_6; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_7; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_8; + wire _zz_decode_LEGAL_INSTRUCTION_9; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_10; + wire [7:0] _zz_decode_LEGAL_INSTRUCTION_11; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_12; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_13; + wire [31:0] _zz_decode_LEGAL_INSTRUCTION_14; + wire _zz_decode_LEGAL_INSTRUCTION_15; + wire [0:0] _zz_decode_LEGAL_INSTRUCTION_16; + wire [1:0] _zz_decode_LEGAL_INSTRUCTION_17; + wire [3:0] _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1; + reg [31:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + wire [1:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_6; + wire [31:0] _zz_IBusCachedPlugin_fetchPc_pc; + wire [2:0] _zz_IBusCachedPlugin_fetchPc_pc_1; + wire [11:0] _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire [31:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2; + wire [19:0] _zz__zz_2; + wire [11:0] _zz__zz_4; + wire [31:0] _zz__zz_6; + wire [31:0] _zz__zz_6_1; + wire [19:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload; + wire [11:0] _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_4; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_5; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_6; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code; + wire [2:0] _zz_DBusCachedPlugin_exceptionBus_payload_code_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted; + wire [1:0] _zz_writeBack_DBusCachedPlugin_rspShifted_1; + reg [7:0] _zz_writeBack_DBusCachedPlugin_rspShifted_2; + wire [0:0] _zz_writeBack_DBusCachedPlugin_rspShifted_3; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_1; + wire _zz__zz_decode_IS_RS2_SIGNED_2; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_3; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_4; + wire _zz__zz_decode_IS_RS2_SIGNED_5; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_6; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_7; + wire _zz__zz_decode_IS_RS2_SIGNED_8; + wire _zz__zz_decode_IS_RS2_SIGNED_9; + wire [24:0] _zz__zz_decode_IS_RS2_SIGNED_10; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_11; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_12; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_13; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_14; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_15; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_16; + wire _zz__zz_decode_IS_RS2_SIGNED_17; + wire _zz__zz_decode_IS_RS2_SIGNED_18; + wire _zz__zz_decode_IS_RS2_SIGNED_19; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_20; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_21; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_22; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_23; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_24; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_25; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_26; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_27; + wire [20:0] _zz__zz_decode_IS_RS2_SIGNED_28; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_29; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_30; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_31; + wire _zz__zz_decode_IS_RS2_SIGNED_32; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_33; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_34; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_35; + wire _zz__zz_decode_IS_RS2_SIGNED_36; + wire [17:0] _zz__zz_decode_IS_RS2_SIGNED_37; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_38; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_39; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_40; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_41; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_42; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_43; + wire _zz__zz_decode_IS_RS2_SIGNED_44; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_45; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_46; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_47; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_48; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_49; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_50; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_51; + wire [14:0] _zz__zz_decode_IS_RS2_SIGNED_52; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_53; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_54; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_55; + wire _zz__zz_decode_IS_RS2_SIGNED_56; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_57; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_58; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_59; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_60; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_61; + wire _zz__zz_decode_IS_RS2_SIGNED_62; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_63; + wire _zz__zz_decode_IS_RS2_SIGNED_64; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_65; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_66; + wire _zz__zz_decode_IS_RS2_SIGNED_67; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_68; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_69; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_70; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_71; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_72; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_73; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_74; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_75; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_76; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_77; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_78; + wire _zz__zz_decode_IS_RS2_SIGNED_79; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_80; + wire _zz__zz_decode_IS_RS2_SIGNED_81; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_82; + wire [11:0] _zz__zz_decode_IS_RS2_SIGNED_83; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_84; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_85; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_86; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_87; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_88; + wire _zz__zz_decode_IS_RS2_SIGNED_89; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_90; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_91; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_92; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_93; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_94; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_95; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_96; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_97; + wire _zz__zz_decode_IS_RS2_SIGNED_98; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_99; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_100; + wire _zz__zz_decode_IS_RS2_SIGNED_101; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_102; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_103; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_104; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_105; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_106; + wire _zz__zz_decode_IS_RS2_SIGNED_107; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_108; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_109; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_110; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_111; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_112; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_113; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_114; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_115; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_116; + wire _zz__zz_decode_IS_RS2_SIGNED_117; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_118; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_119; + wire [8:0] _zz__zz_decode_IS_RS2_SIGNED_120; + wire _zz__zz_decode_IS_RS2_SIGNED_121; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_122; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_123; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_124; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_125; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_126; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_127; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_128; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_129; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_130; + wire [6:0] _zz__zz_decode_IS_RS2_SIGNED_131; + wire _zz__zz_decode_IS_RS2_SIGNED_132; + wire _zz__zz_decode_IS_RS2_SIGNED_133; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_134; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_135; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_136; + wire _zz__zz_decode_IS_RS2_SIGNED_137; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_138; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_139; + wire [1:0] _zz__zz_decode_IS_RS2_SIGNED_140; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_141; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_142; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_143; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_144; + wire [3:0] _zz__zz_decode_IS_RS2_SIGNED_145; + wire [4:0] _zz__zz_decode_IS_RS2_SIGNED_146; + wire _zz__zz_decode_IS_RS2_SIGNED_147; + wire _zz__zz_decode_IS_RS2_SIGNED_148; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_149; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_150; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_151; + wire [31:0] _zz__zz_decode_IS_RS2_SIGNED_152; + wire _zz__zz_decode_IS_RS2_SIGNED_153; + wire _zz__zz_decode_IS_RS2_SIGNED_154; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_155; + wire [2:0] _zz__zz_decode_IS_RS2_SIGNED_156; + wire _zz__zz_decode_IS_RS2_SIGNED_157; + wire _zz__zz_decode_IS_RS2_SIGNED_158; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_159; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_160; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_161; + wire [0:0] _zz__zz_decode_IS_RS2_SIGNED_162; + wire _zz__zz_decode_IS_RS2_SIGNED_163; + wire _zz_RegFilePlugin_regFile_port; + wire _zz_decode_RegFilePlugin_rs1Data; + wire _zz_RegFilePlugin_regFile_port_1; + wire _zz_decode_RegFilePlugin_rs2Data; + wire [0:0] _zz__zz_execute_REGFILE_WRITE_DATA; + wire [2:0] _zz__zz_execute_SRC1; + wire [4:0] _zz__zz_execute_SRC1_1; + wire [11:0] _zz__zz_execute_SRC2_3; + wire [31:0] _zz_execute_SrcPlugin_addSub; + wire [31:0] _zz_execute_SrcPlugin_addSub_1; + wire [31:0] _zz_execute_SrcPlugin_addSub_2; + wire [31:0] _zz_execute_SrcPlugin_addSub_3; + wire [31:0] _zz_execute_SrcPlugin_addSub_4; + wire [31:0] _zz_execute_SrcPlugin_addSub_5; + wire [31:0] _zz_execute_SrcPlugin_addSub_6; + wire [19:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_2; + wire [11:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_4; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1; + wire [31:0] _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2; + wire [19:0] _zz__zz_execute_BranchPlugin_branch_src2_2; + wire [11:0] _zz__zz_execute_BranchPlugin_branch_src2_4; + wire _zz_execute_BranchPlugin_branch_src2_6; + wire _zz_execute_BranchPlugin_branch_src2_7; + wire _zz_execute_BranchPlugin_branch_src2_8; + wire [2:0] _zz_execute_BranchPlugin_branch_src2_9; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire [1:0] _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1; + wire _zz_when; + wire [65:0] _zz_writeBack_MulPlugin_result; + wire [65:0] _zz_writeBack_MulPlugin_result_1; + wire [31:0] _zz__zz_decode_RS2_2; + wire [31:0] _zz__zz_decode_RS2_2_1; + wire [5:0] _zz_memory_DivPlugin_div_counter_valueNext; + wire [0:0] _zz_memory_DivPlugin_div_counter_valueNext_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_outRemainder_1; + wire [32:0] _zz_memory_DivPlugin_div_stage_0_outNumerator; + wire [32:0] _zz_memory_DivPlugin_div_result_1; + wire [32:0] _zz_memory_DivPlugin_div_result_2; + wire [32:0] _zz_memory_DivPlugin_div_result_3; + wire [32:0] _zz_memory_DivPlugin_div_result_4; + wire [0:0] _zz_memory_DivPlugin_div_result_5; + wire [32:0] _zz_memory_DivPlugin_rs1_2; + wire [0:0] _zz_memory_DivPlugin_rs1_3; + wire [31:0] _zz_memory_DivPlugin_rs2_1; + wire [0:0] _zz_memory_DivPlugin_rs2_2; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; + wire [26:0] _zz_iBusWishbone_ADR_1; + wire [51:0] memory_MUL_LOW; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [33:0] execute_MUL_HL; + wire [33:0] execute_MUL_LH; + wire [31:0] execute_MUL_LL; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] execute_SHIFT_RIGHT; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] memory_MEMORY_STORE_DATA_RF; + wire [31:0] execute_MEMORY_STORE_DATA_RF; + wire decode_CSR_READ_OPCODE; + wire decode_CSR_WRITE_OPCODE; + wire decode_PREDICTION_HAD_BRANCHED2; + wire decode_SRC2_FORCE_ZERO; + wire decode_IS_RS2_SIGNED; + wire decode_IS_RS1_SIGNED; + wire decode_IS_DIV; + wire memory_IS_MUL; + wire execute_IS_MUL; + wire decode_IS_MUL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_to_writeBack_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_to_memory_ENV_CTRL_1; + wire `EnvCtrlEnum_binary_sequential_type decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_to_execute_ENV_CTRL_1; + wire decode_IS_CSR; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_to_execute_BRANCH_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_to_memory_SHIFT_CTRL_1; + wire `ShiftCtrlEnum_binary_sequential_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_to_execute_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + wire decode_SRC_LESS_UNSIGNED; + wire decode_MEMORY_MANAGMENT; + wire memory_MEMORY_WR; + wire decode_MEMORY_WR; + wire execute_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_MEMORY_STAGE; + wire decode_BYPASSABLE_EXECUTE_STAGE; + wire `Src2CtrlEnum_binary_sequential_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_to_execute_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_to_execute_SRC1_CTRL_1; + wire decode_MEMORY_FORCE_CONSTISTENCY; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire [31:0] memory_PC; + wire execute_IS_RS1_SIGNED; + wire execute_IS_DIV; + wire execute_IS_RS2_SIGNED; + wire memory_IS_DIV; + wire writeBack_IS_MUL; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire `EnvCtrlEnum_binary_sequential_type memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_memory_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_execute_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type writeBack_ENV_CTRL; + wire `EnvCtrlEnum_binary_sequential_type _zz_writeBack_ENV_CTRL; + wire [31:0] memory_BRANCH_CALC; + wire memory_BRANCH_DO; + wire [31:0] execute_PC; + wire execute_PREDICTION_HAD_BRANCHED2; + (* keep , syn_keep *) wire [31:0] execute_RS1 /* synthesis syn_keep = 1 */ ; + wire execute_BRANCH_COND_RESULT; + wire `BranchCtrlEnum_binary_sequential_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_execute_BRANCH_CTRL; + wire decode_RS2_USE; + wire decode_RS1_USE; + reg [31:0] _zz_decode_RS2; + wire execute_REGFILE_WRITE_VALID; + wire execute_BYPASSABLE_EXECUTE_STAGE; + wire memory_REGFILE_WRITE_VALID; + wire [31:0] memory_INSTRUCTION; + wire memory_BYPASSABLE_MEMORY_STAGE; + wire writeBack_REGFILE_WRITE_VALID; + reg [31:0] decode_RS2; + reg [31:0] decode_RS1; + wire [31:0] memory_SHIFT_RIGHT; + reg [31:0] _zz_decode_RS2_1; + wire `ShiftCtrlEnum_binary_sequential_type memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_memory_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_execute_SHIFT_CTRL; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire [31:0] _zz_execute_SRC2; + wire `Src2CtrlEnum_binary_sequential_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_binary_sequential_type _zz_execute_SRC2_CTRL; + wire `Src1CtrlEnum_binary_sequential_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_binary_sequential_type _zz_execute_SRC1_CTRL; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_binary_sequential_type execute_ALU_CTRL; + wire `AluCtrlEnum_binary_sequential_type _zz_execute_ALU_CTRL; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_binary_sequential_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_execute_ALU_BITWISE_CTRL; + wire [31:0] _zz_lastStageRegFileWrite_payload_address; + wire _zz_lastStageRegFileWrite_valid; + reg _zz_1; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_1; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_1; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_1; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_1; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_1; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_1; + reg [31:0] _zz_decode_RS2_2; + wire writeBack_MEMORY_WR; + wire [31:0] writeBack_MEMORY_STORE_DATA_RF; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + wire execute_MEMORY_FORCE_CONSTISTENCY; + wire execute_MEMORY_MANAGMENT; + (* keep , syn_keep *) wire [31:0] execute_RS2 /* synthesis syn_keep = 1 */ ; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire [31:0] execute_INSTRUCTION; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected_4; + reg IBusCachedPlugin_rsp_issueDetected_3; + reg IBusCachedPlugin_rsp_issueDetected_2; + reg IBusCachedPlugin_rsp_issueDetected_1; + wire `BranchCtrlEnum_binary_sequential_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_1; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] _zz_decode_to_execute_FORMAL_PC_NEXT; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + reg decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + reg execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_predictionJumpInterface_valid; + (* keep , syn_keep *) wire [31:0] IBusCachedPlugin_predictionJumpInterface_payload /* synthesis syn_keep = 1 */ ; + reg IBusCachedPlugin_decodePrediction_cmd_hadBranch; + wire IBusCachedPlugin_decodePrediction_rsp_wasWrong; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + wire IBusCachedPlugin_mmuBus_cmd_0_isValid; + wire IBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_isPaging; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire dBus_cmd_payload_uncached; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_size; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire dBus_rsp_payload_last; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire DBusCachedPlugin_mmuBus_cmd_0_isValid; + wire DBusCachedPlugin_mmuBus_cmd_0_isStuck; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_isPaging; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_rsp_bypassTranslation; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + wire [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire [31:0] CsrPlugin_csrMapping_readDataSignal; + wire [31:0] CsrPlugin_csrMapping_readDataInit; + wire [31:0] CsrPlugin_csrMapping_writeDataSignal; + wire CsrPlugin_csrMapping_allowCsrSignal; + wire CsrPlugin_csrMapping_hazardFree; + reg CsrPlugin_inWfi /* verilator public */ ; + wire CsrPlugin_thirdPartyWake; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire CsrPlugin_exceptionPendings_2; + wire CsrPlugin_exceptionPendings_3; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire CsrPlugin_allowEbreakException; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload; + wire [3:0] _zz_IBusCachedPlugin_jump_pcLoad_payload_1; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_2; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_3; + wire _zz_IBusCachedPlugin_jump_pcLoad_payload_4; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_output_fire; + wire IBusCachedPlugin_fetchPc_corrected; + reg IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + wire when_Fetcher_l131; + wire IBusCachedPlugin_fetchPc_output_fire_1; + wire when_Fetcher_l131_1; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + wire when_Fetcher_l158; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + reg _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + reg [31:0] _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + wire when_Fetcher_l240; + wire when_Fetcher_l320; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + wire when_Fetcher_l329; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + wire when_Fetcher_l329_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + wire when_Fetcher_l329_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + wire when_Fetcher_l329_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire when_Fetcher_l329_4; + wire _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + reg [18:0] _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1; + wire _zz_2; + reg [10:0] _zz_3; + wire _zz_4; + reg [18:0] _zz_5; + reg _zz_6; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload; + reg [10:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_1; + wire _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + reg [18:0] _zz_IBusCachedPlugin_predictionJumpInterface_payload_3; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_IBusCachedPlugin_rspCounter; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire when_IBusCachedPlugin_l239; + wire when_IBusCachedPlugin_l244; + wire when_IBusCachedPlugin_l250; + wire when_IBusCachedPlugin_l256; + wire when_IBusCachedPlugin_l267; + wire dataCache_1_io_mem_cmd_s2mPipe_valid; + reg dataCache_1_io_mem_cmd_s2mPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_payload_last; + reg dataCache_1_io_mem_cmd_rValid; + reg dataCache_1_io_mem_cmd_rData_wr; + reg dataCache_1_io_mem_cmd_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_rData_size; + reg dataCache_1_io_mem_cmd_rData_last; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + wire [31:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + wire [3:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + wire [2:0] dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + wire dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + reg dataCache_1_io_mem_cmd_s2mPipe_rValid; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_address; + reg [31:0] dataCache_1_io_mem_cmd_s2mPipe_rData_data; + reg [3:0] dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + reg [2:0] dataCache_1_io_mem_cmd_s2mPipe_rData_size; + reg dataCache_1_io_mem_cmd_s2mPipe_rData_last; + wire when_Stream_l342; + wire [31:0] _zz_DBusCachedPlugin_rspCounter; + reg [31:0] DBusCachedPlugin_rspCounter; + wire when_DBusCachedPlugin_l303; + wire [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_execute_MEMORY_STORE_DATA_RF; + wire dataCache_1_io_cpu_flush_isStall; + wire when_DBusCachedPlugin_l343; + wire when_DBusCachedPlugin_l359; + wire when_DBusCachedPlugin_l386; + wire when_DBusCachedPlugin_l438; + wire when_DBusCachedPlugin_l458; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_0; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_1; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_2; + wire [7:0] writeBack_DBusCachedPlugin_rspSplits_3; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + wire [31:0] writeBack_DBusCachedPlugin_rspRf; + wire [1:0] switch_Misc_l200; + wire _zz_writeBack_DBusCachedPlugin_rspFormated; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_1; + wire _zz_writeBack_DBusCachedPlugin_rspFormated_2; + reg [31:0] _zz_writeBack_DBusCachedPlugin_rspFormated_3; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + wire when_DBusCachedPlugin_l484; + wire [31:0] _zz_decode_IS_RS2_SIGNED; + wire _zz_decode_IS_RS2_SIGNED_1; + wire _zz_decode_IS_RS2_SIGNED_2; + wire _zz_decode_IS_RS2_SIGNED_3; + wire _zz_decode_IS_RS2_SIGNED_4; + wire `Src1CtrlEnum_binary_sequential_type _zz_decode_SRC1_CTRL_2; + wire `AluCtrlEnum_binary_sequential_type _zz_decode_ALU_CTRL_2; + wire `Src2CtrlEnum_binary_sequential_type _zz_decode_SRC2_CTRL_2; + wire `AluBitwiseCtrlEnum_binary_sequential_type _zz_decode_ALU_BITWISE_CTRL_2; + wire `ShiftCtrlEnum_binary_sequential_type _zz_decode_SHIFT_CTRL_2; + wire `BranchCtrlEnum_binary_sequential_type _zz_decode_BRANCH_CTRL_2; + wire `EnvCtrlEnum_binary_sequential_type _zz_decode_ENV_CTRL_2; + wire when_RegFilePlugin_l63; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_rs1Data; + wire [31:0] decode_RegFilePlugin_rs2Data; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + reg _zz_7; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_execute_REGFILE_WRITE_DATA; + reg [31:0] _zz_execute_SRC1; + wire _zz_execute_SRC2_1; + reg [19:0] _zz_execute_SRC2_2; + wire _zz_execute_SRC2_3; + reg [19:0] _zz_execute_SRC2_4; + reg [31:0] _zz_execute_SRC2_5; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + wire [4:0] execute_FullBarrelShifterPlugin_amplitude; + reg [31:0] _zz_execute_FullBarrelShifterPlugin_reversed; + wire [31:0] execute_FullBarrelShifterPlugin_reversed; + reg [31:0] _zz_decode_RS2_3; + reg HazardSimplePlugin_src0Hazard; + reg HazardSimplePlugin_src1Hazard; + wire HazardSimplePlugin_writeBackWrites_valid; + wire [4:0] HazardSimplePlugin_writeBackWrites_payload_address; + wire [31:0] HazardSimplePlugin_writeBackWrites_payload_data; + reg HazardSimplePlugin_writeBackBuffer_valid; + reg [4:0] HazardSimplePlugin_writeBackBuffer_payload_address; + reg [31:0] HazardSimplePlugin_writeBackBuffer_payload_data; + wire HazardSimplePlugin_addr0Match; + wire HazardSimplePlugin_addr1Match; + wire when_HazardSimplePlugin_l47; + wire when_HazardSimplePlugin_l48; + wire when_HazardSimplePlugin_l51; + wire when_HazardSimplePlugin_l45; + wire when_HazardSimplePlugin_l57; + wire when_HazardSimplePlugin_l58; + wire when_HazardSimplePlugin_l48_1; + wire when_HazardSimplePlugin_l51_1; + wire when_HazardSimplePlugin_l45_1; + wire when_HazardSimplePlugin_l57_1; + wire when_HazardSimplePlugin_l58_1; + wire when_HazardSimplePlugin_l48_2; + wire when_HazardSimplePlugin_l51_2; + wire when_HazardSimplePlugin_l45_2; + wire when_HazardSimplePlugin_l57_2; + wire when_HazardSimplePlugin_l58_2; + wire when_HazardSimplePlugin_l105; + wire when_HazardSimplePlugin_l108; + wire when_HazardSimplePlugin_l113; + wire execute_BranchPlugin_eq; + wire [2:0] switch_Misc_l200_1; + reg _zz_execute_BRANCH_COND_RESULT; + reg _zz_execute_BRANCH_COND_RESULT_1; + wire _zz_execute_BranchPlugin_missAlignedTarget; + reg [19:0] _zz_execute_BranchPlugin_missAlignedTarget_1; + wire _zz_execute_BranchPlugin_missAlignedTarget_2; + reg [10:0] _zz_execute_BranchPlugin_missAlignedTarget_3; + wire _zz_execute_BranchPlugin_missAlignedTarget_4; + reg [18:0] _zz_execute_BranchPlugin_missAlignedTarget_5; + reg _zz_execute_BranchPlugin_missAlignedTarget_6; + wire execute_BranchPlugin_missAlignedTarget; + reg [31:0] execute_BranchPlugin_branch_src1; + reg [31:0] execute_BranchPlugin_branch_src2; + wire _zz_execute_BranchPlugin_branch_src2; + reg [19:0] _zz_execute_BranchPlugin_branch_src2_1; + wire _zz_execute_BranchPlugin_branch_src2_2; + reg [10:0] _zz_execute_BranchPlugin_branch_src2_3; + wire _zz_execute_BranchPlugin_branch_src2_4; + reg [18:0] _zz_execute_BranchPlugin_branch_src2_5; + wire [31:0] execute_BranchPlugin_branchAdder; + reg [1:0] CsrPlugin_misa_base; + reg [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + wire _zz_when_CsrPlugin_l952; + wire _zz_when_CsrPlugin_l952_1; + wire _zz_when_CsrPlugin_l952_2; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code; + wire _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1; + wire when_CsrPlugin_l909; + wire when_CsrPlugin_l909_1; + wire when_CsrPlugin_l909_2; + wire when_CsrPlugin_l909_3; + wire when_CsrPlugin_l922; + reg CsrPlugin_interrupt_valid; + reg [3:0] CsrPlugin_interrupt_code /* verilator public */ ; + reg [1:0] CsrPlugin_interrupt_targetPrivilege; + wire when_CsrPlugin_l946; + wire when_CsrPlugin_l952; + wire when_CsrPlugin_l952_1; + wire when_CsrPlugin_l952_2; + wire CsrPlugin_exception; + reg CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_pcValids_0; + reg CsrPlugin_pipelineLiberator_pcValids_1; + reg CsrPlugin_pipelineLiberator_pcValids_2; + wire CsrPlugin_pipelineLiberator_active; + wire when_CsrPlugin_l980; + wire when_CsrPlugin_l980_1; + wire when_CsrPlugin_l980_2; + wire when_CsrPlugin_l985; + reg CsrPlugin_pipelineLiberator_done; + wire when_CsrPlugin_l991; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException /* verilator public */ ; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire when_CsrPlugin_l1019; + wire when_CsrPlugin_l1064; + wire [1:0] switch_CsrPlugin_l1068; + reg execute_CsrPlugin_wfiWake; + wire when_CsrPlugin_l1108; + wire when_CsrPlugin_l1110; + wire when_CsrPlugin_l1116; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + wire when_CsrPlugin_l1129; + wire when_CsrPlugin_l1136; + wire when_CsrPlugin_l1137; + wire when_CsrPlugin_l1144; + reg execute_CsrPlugin_writeInstruction; + reg execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + wire switch_Misc_l200_2; + reg [31:0] _zz_CsrPlugin_csrMapping_writeDataSignal; + wire when_CsrPlugin_l1176; + wire when_CsrPlugin_l1180; + wire [11:0] execute_CsrPlugin_csrAddress; + reg execute_MulPlugin_aSigned; + reg execute_MulPlugin_bSigned; + wire [31:0] execute_MulPlugin_a; + wire [31:0] execute_MulPlugin_b; + wire [1:0] switch_MulPlugin_l87; + wire [15:0] execute_MulPlugin_aULow; + wire [15:0] execute_MulPlugin_bULow; + wire [16:0] execute_MulPlugin_aSLow; + wire [16:0] execute_MulPlugin_bSLow; + wire [16:0] execute_MulPlugin_aHigh; + wire [16:0] execute_MulPlugin_bHigh; + wire [65:0] writeBack_MulPlugin_result; + wire when_MulPlugin_l147; + wire [1:0] switch_MulPlugin_l148; + reg [32:0] memory_DivPlugin_rs1; + reg [31:0] memory_DivPlugin_rs2; + reg [64:0] memory_DivPlugin_accumulator; + wire memory_DivPlugin_frontendOk; + reg memory_DivPlugin_div_needRevert; + reg memory_DivPlugin_div_counter_willIncrement; + reg memory_DivPlugin_div_counter_willClear; + reg [5:0] memory_DivPlugin_div_counter_valueNext; + reg [5:0] memory_DivPlugin_div_counter_value; + wire memory_DivPlugin_div_counter_willOverflowIfInc; + wire memory_DivPlugin_div_counter_willOverflow; + reg memory_DivPlugin_div_done; + wire when_MulDivIterativePlugin_l126; + wire when_MulDivIterativePlugin_l126_1; + reg [31:0] memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l128; + wire when_MulDivIterativePlugin_l129; + wire when_MulDivIterativePlugin_l132; + wire [31:0] _zz_memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderShifted; + wire [32:0] memory_DivPlugin_div_stage_0_remainderMinusDenominator; + wire [31:0] memory_DivPlugin_div_stage_0_outRemainder; + wire [31:0] memory_DivPlugin_div_stage_0_outNumerator; + wire when_MulDivIterativePlugin_l151; + wire [31:0] _zz_memory_DivPlugin_div_result; + wire when_MulDivIterativePlugin_l162; + wire _zz_memory_DivPlugin_rs2; + wire _zz_memory_DivPlugin_rs1; + reg [32:0] _zz_memory_DivPlugin_rs1_1; + reg [31:0] externalInterruptArray_regNext; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_1; + wire when_Pipeline_l124; + reg [31:0] decode_to_execute_PC; + wire when_Pipeline_l124_1; + reg [31:0] execute_to_memory_PC; + wire when_Pipeline_l124_2; + reg [31:0] memory_to_writeBack_PC; + wire when_Pipeline_l124_3; + reg [31:0] decode_to_execute_INSTRUCTION; + wire when_Pipeline_l124_4; + reg [31:0] execute_to_memory_INSTRUCTION; + wire when_Pipeline_l124_5; + reg [31:0] memory_to_writeBack_INSTRUCTION; + wire when_Pipeline_l124_6; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + wire when_Pipeline_l124_7; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + wire when_Pipeline_l124_8; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + wire when_Pipeline_l124_9; + reg decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + wire when_Pipeline_l124_10; + reg `Src1CtrlEnum_binary_sequential_type decode_to_execute_SRC1_CTRL; + wire when_Pipeline_l124_11; + reg decode_to_execute_SRC_USE_SUB_LESS; + wire when_Pipeline_l124_12; + reg decode_to_execute_MEMORY_ENABLE; + wire when_Pipeline_l124_13; + reg execute_to_memory_MEMORY_ENABLE; + wire when_Pipeline_l124_14; + reg memory_to_writeBack_MEMORY_ENABLE; + wire when_Pipeline_l124_15; + reg `AluCtrlEnum_binary_sequential_type decode_to_execute_ALU_CTRL; + wire when_Pipeline_l124_16; + reg `Src2CtrlEnum_binary_sequential_type decode_to_execute_SRC2_CTRL; + wire when_Pipeline_l124_17; + reg decode_to_execute_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_18; + reg execute_to_memory_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_19; + reg memory_to_writeBack_REGFILE_WRITE_VALID; + wire when_Pipeline_l124_20; + reg decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + wire when_Pipeline_l124_21; + reg decode_to_execute_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_22; + reg execute_to_memory_BYPASSABLE_MEMORY_STAGE; + wire when_Pipeline_l124_23; + reg decode_to_execute_MEMORY_WR; + wire when_Pipeline_l124_24; + reg execute_to_memory_MEMORY_WR; + wire when_Pipeline_l124_25; + reg memory_to_writeBack_MEMORY_WR; + wire when_Pipeline_l124_26; + reg decode_to_execute_MEMORY_MANAGMENT; + wire when_Pipeline_l124_27; + reg decode_to_execute_SRC_LESS_UNSIGNED; + wire when_Pipeline_l124_28; + reg `AluBitwiseCtrlEnum_binary_sequential_type decode_to_execute_ALU_BITWISE_CTRL; + wire when_Pipeline_l124_29; + reg `ShiftCtrlEnum_binary_sequential_type decode_to_execute_SHIFT_CTRL; + wire when_Pipeline_l124_30; + reg `ShiftCtrlEnum_binary_sequential_type execute_to_memory_SHIFT_CTRL; + wire when_Pipeline_l124_31; + reg `BranchCtrlEnum_binary_sequential_type decode_to_execute_BRANCH_CTRL; + wire when_Pipeline_l124_32; + reg decode_to_execute_IS_CSR; + wire when_Pipeline_l124_33; + reg `EnvCtrlEnum_binary_sequential_type decode_to_execute_ENV_CTRL; + wire when_Pipeline_l124_34; + reg `EnvCtrlEnum_binary_sequential_type execute_to_memory_ENV_CTRL; + wire when_Pipeline_l124_35; + reg `EnvCtrlEnum_binary_sequential_type memory_to_writeBack_ENV_CTRL; + wire when_Pipeline_l124_36; + reg decode_to_execute_IS_MUL; + wire when_Pipeline_l124_37; + reg execute_to_memory_IS_MUL; + wire when_Pipeline_l124_38; + reg memory_to_writeBack_IS_MUL; + wire when_Pipeline_l124_39; + reg decode_to_execute_IS_DIV; + wire when_Pipeline_l124_40; + reg execute_to_memory_IS_DIV; + wire when_Pipeline_l124_41; + reg decode_to_execute_IS_RS1_SIGNED; + wire when_Pipeline_l124_42; + reg decode_to_execute_IS_RS2_SIGNED; + wire when_Pipeline_l124_43; + reg [31:0] decode_to_execute_RS1; + wire when_Pipeline_l124_44; + reg [31:0] decode_to_execute_RS2; + wire when_Pipeline_l124_45; + reg decode_to_execute_SRC2_FORCE_ZERO; + wire when_Pipeline_l124_46; + reg decode_to_execute_PREDICTION_HAD_BRANCHED2; + wire when_Pipeline_l124_47; + reg decode_to_execute_CSR_WRITE_OPCODE; + wire when_Pipeline_l124_48; + reg decode_to_execute_CSR_READ_OPCODE; + wire when_Pipeline_l124_49; + reg [31:0] execute_to_memory_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_50; + reg [31:0] memory_to_writeBack_MEMORY_STORE_DATA_RF; + wire when_Pipeline_l124_51; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_52; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + wire when_Pipeline_l124_53; + reg [31:0] execute_to_memory_SHIFT_RIGHT; + wire when_Pipeline_l124_54; + reg execute_to_memory_BRANCH_DO; + wire when_Pipeline_l124_55; + reg [31:0] execute_to_memory_BRANCH_CALC; + wire when_Pipeline_l124_56; + reg [31:0] execute_to_memory_MUL_LL; + wire when_Pipeline_l124_57; + reg [33:0] execute_to_memory_MUL_LH; + wire when_Pipeline_l124_58; + reg [33:0] execute_to_memory_MUL_HL; + wire when_Pipeline_l124_59; + reg [33:0] execute_to_memory_MUL_HH; + wire when_Pipeline_l124_60; + reg [33:0] memory_to_writeBack_MUL_HH; + wire when_Pipeline_l124_61; + reg [51:0] memory_to_writeBack_MUL_LOW; + wire when_Pipeline_l151; + wire when_Pipeline_l154; + wire when_Pipeline_l151_1; + wire when_Pipeline_l154_1; + wire when_Pipeline_l151_2; + wire when_Pipeline_l154_2; + wire when_CsrPlugin_l1264; + reg execute_CsrPlugin_csr_3264; + wire when_CsrPlugin_l1264_1; + reg execute_CsrPlugin_csr_3857; + wire when_CsrPlugin_l1264_2; + reg execute_CsrPlugin_csr_3858; + wire when_CsrPlugin_l1264_3; + reg execute_CsrPlugin_csr_3859; + wire when_CsrPlugin_l1264_4; + reg execute_CsrPlugin_csr_3860; + wire when_CsrPlugin_l1264_5; + reg execute_CsrPlugin_csr_769; + wire when_CsrPlugin_l1264_6; + reg execute_CsrPlugin_csr_768; + wire when_CsrPlugin_l1264_7; + reg execute_CsrPlugin_csr_836; + wire when_CsrPlugin_l1264_8; + reg execute_CsrPlugin_csr_772; + wire when_CsrPlugin_l1264_9; + reg execute_CsrPlugin_csr_773; + wire when_CsrPlugin_l1264_10; + reg execute_CsrPlugin_csr_833; + wire when_CsrPlugin_l1264_11; + reg execute_CsrPlugin_csr_832; + wire when_CsrPlugin_l1264_12; + reg execute_CsrPlugin_csr_834; + wire when_CsrPlugin_l1264_13; + reg execute_CsrPlugin_csr_835; + wire when_CsrPlugin_l1264_14; + reg execute_CsrPlugin_csr_2816; + wire when_CsrPlugin_l1264_15; + reg execute_CsrPlugin_csr_2944; + wire when_CsrPlugin_l1264_16; + reg execute_CsrPlugin_csr_2818; + wire when_CsrPlugin_l1264_17; + reg execute_CsrPlugin_csr_2946; + wire when_CsrPlugin_l1264_18; + reg execute_CsrPlugin_csr_3072; + wire when_CsrPlugin_l1264_19; + reg execute_CsrPlugin_csr_3200; + wire when_CsrPlugin_l1264_20; + reg execute_CsrPlugin_csr_3074; + wire when_CsrPlugin_l1264_21; + reg execute_CsrPlugin_csr_3202; + wire when_CsrPlugin_l1264_22; + reg execute_CsrPlugin_csr_3008; + wire when_CsrPlugin_l1264_23; + reg execute_CsrPlugin_csr_4032; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_13; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_14; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_15; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_16; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_17; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_18; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_19; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_20; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_21; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; + wire when_CsrPlugin_l1297; + wire when_CsrPlugin_l1302; + reg [2:0] _zz_iBusWishbone_ADR; + wire when_InstructionCache_l239; + reg _zz_iBus_rsp_valid; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + reg [2:0] _zz_dBus_cmd_ready; + wire _zz_dBus_cmd_ready_1; + wire _zz_dBus_cmd_ready_2; + wire _zz_dBus_cmd_ready_3; + wire _zz_dBus_cmd_ready_4; + wire _zz_dBus_cmd_ready_5; + reg _zz_dBus_rsp_valid; + reg [31:0] dBusWishbone_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_string; + reg [39:0] _zz_memory_to_writeBack_ENV_CTRL_1_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_string; + reg [39:0] _zz_execute_to_memory_ENV_CTRL_1_string; + reg [39:0] decode_ENV_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_string; + reg [39:0] _zz_decode_to_execute_ENV_CTRL_1_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_string; + reg [31:0] _zz_decode_to_execute_BRANCH_CTRL_1_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_string; + reg [71:0] _zz_execute_to_memory_SHIFT_CTRL_1_string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_string; + reg [71:0] _zz_decode_to_execute_SHIFT_CTRL_1_string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_string; + reg [23:0] _zz_decode_to_execute_SRC2_CTRL_1_string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_decode_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_string; + reg [63:0] _zz_decode_to_execute_ALU_CTRL_1_string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_string; + reg [95:0] _zz_decode_to_execute_SRC1_CTRL_1_string; + reg [39:0] memory_ENV_CTRL_string; + reg [39:0] _zz_memory_ENV_CTRL_string; + reg [39:0] execute_ENV_CTRL_string; + reg [39:0] _zz_execute_ENV_CTRL_string; + reg [39:0] writeBack_ENV_CTRL_string; + reg [39:0] _zz_writeBack_ENV_CTRL_string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_execute_BRANCH_CTRL_string; + reg [71:0] memory_SHIFT_CTRL_string; + reg [71:0] _zz_memory_SHIFT_CTRL_string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_execute_SHIFT_CTRL_string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_execute_SRC2_CTRL_string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_execute_SRC1_CTRL_string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_execute_ALU_CTRL_string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_decode_ENV_CTRL_1_string; + reg [31:0] _zz_decode_BRANCH_CTRL_string; + reg [71:0] _zz_decode_SHIFT_CTRL_1_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_1_string; + reg [23:0] _zz_decode_SRC2_CTRL_1_string; + reg [63:0] _zz_decode_ALU_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_1_string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_decode_BRANCH_CTRL_1_string; + reg [95:0] _zz_decode_SRC1_CTRL_2_string; + reg [63:0] _zz_decode_ALU_CTRL_2_string; + reg [23:0] _zz_decode_SRC2_CTRL_2_string; + reg [39:0] _zz_decode_ALU_BITWISE_CTRL_2_string; + reg [71:0] _zz_decode_SHIFT_CTRL_2_string; + reg [31:0] _zz_decode_BRANCH_CTRL_2_string; + reg [39:0] _zz_decode_ENV_CTRL_2_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [71:0] execute_to_memory_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [39:0] decode_to_execute_ENV_CTRL_string; + reg [39:0] execute_to_memory_ENV_CTRL_string; + reg [39:0] memory_to_writeBack_ENV_CTRL_string; + `endif + + (* ram_style = "block" *) reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + + assign _zz_when = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != 2'b00); + assign _zz_memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW_1) + $signed(_zz_memory_MUL_LOW_5)); + assign _zz_memory_MUL_LOW_1 = ($signed(_zz_memory_MUL_LOW_2) + $signed(_zz_memory_MUL_LOW_3)); + assign _zz_memory_MUL_LOW_2 = 52'h0; + assign _zz_memory_MUL_LOW_4 = {1'b0,memory_MUL_LL}; + assign _zz_memory_MUL_LOW_3 = {{19{_zz_memory_MUL_LOW_4[32]}}, _zz_memory_MUL_LOW_4}; + assign _zz_memory_MUL_LOW_6 = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_memory_MUL_LOW_5 = {{2{_zz_memory_MUL_LOW_6[49]}}, _zz_memory_MUL_LOW_6}; + assign _zz_memory_MUL_LOW_8 = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_memory_MUL_LOW_7 = {{2{_zz_memory_MUL_LOW_8[49]}}, _zz_memory_MUL_LOW_8}; + assign _zz_execute_SHIFT_RIGHT_1 = ($signed(_zz_execute_SHIFT_RIGHT_2) >>> execute_FullBarrelShifterPlugin_amplitude); + assign _zz_execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT_1[31 : 0]; + assign _zz_execute_SHIFT_RIGHT_2 = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SRA_1) && execute_FullBarrelShifterPlugin_reversed[31]),execute_FullBarrelShifterPlugin_reversed}; + assign _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload - 4'b0001); + assign _zz_IBusCachedPlugin_fetchPc_pc_1 = {IBusCachedPlugin_fetchPc_inc,2'b00}; + assign _zz_IBusCachedPlugin_fetchPc_pc = {29'd0, _zz_IBusCachedPlugin_fetchPc_pc_1}; + assign _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2 = {{_zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_4 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz__zz_6 = {{_zz_3,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_6_1 = {{_zz_5,{{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}; + assign _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = {{{decode_INSTRUCTION[31],decode_INSTRUCTION[7]},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}; + assign _zz_DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 3'b111 : 3'b101); + assign _zz_DBusCachedPlugin_exceptionBus_payload_code_1 = (writeBack_MEMORY_WR ? 3'b110 : 3'b100); + assign _zz__zz_execute_REGFILE_WRITE_DATA = execute_SRC_LESS; + assign _zz__zz_execute_SRC1 = 3'b100; + assign _zz__zz_execute_SRC1_1 = execute_INSTRUCTION[19 : 15]; + assign _zz__zz_execute_SRC2_3 = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_execute_SrcPlugin_addSub = ($signed(_zz_execute_SrcPlugin_addSub_1) + $signed(_zz_execute_SrcPlugin_addSub_4)); + assign _zz_execute_SrcPlugin_addSub_1 = ($signed(_zz_execute_SrcPlugin_addSub_2) + $signed(_zz_execute_SrcPlugin_addSub_3)); + assign _zz_execute_SrcPlugin_addSub_2 = execute_SRC1; + assign _zz_execute_SrcPlugin_addSub_3 = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_execute_SrcPlugin_addSub_4 = (execute_SRC_USE_SUB_LESS ? _zz_execute_SrcPlugin_addSub_5 : _zz_execute_SrcPlugin_addSub_6); + assign _zz_execute_SrcPlugin_addSub_5 = 32'h00000001; + assign _zz_execute_SrcPlugin_addSub_6 = 32'h0; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6 = {_zz_execute_BranchPlugin_missAlignedTarget_1,execute_INSTRUCTION[31 : 20]}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1 = {{_zz_execute_BranchPlugin_missAlignedTarget_3,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2 = {{_zz_execute_BranchPlugin_missAlignedTarget_5,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + assign _zz__zz_execute_BranchPlugin_branch_src2_2 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz__zz_execute_BranchPlugin_branch_src2_4 = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_execute_BranchPlugin_branch_src2_9 = 3'b100; + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code & (~ _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1)); + assign _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1_1 = (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code - 2'b01); + assign _zz_writeBack_MulPlugin_result = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_writeBack_MulPlugin_result_1 = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz__zz_decode_RS2_2 = writeBack_MUL_LOW[31 : 0]; + assign _zz__zz_decode_RS2_2_1 = writeBack_MulPlugin_result[63 : 32]; + assign _zz_memory_DivPlugin_div_counter_valueNext_1 = memory_DivPlugin_div_counter_willIncrement; + assign _zz_memory_DivPlugin_div_counter_valueNext = {5'd0, _zz_memory_DivPlugin_div_counter_valueNext_1}; + assign _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator = {1'd0, memory_DivPlugin_rs2}; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder = memory_DivPlugin_div_stage_0_remainderMinusDenominator[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outRemainder_1 = memory_DivPlugin_div_stage_0_remainderShifted[31:0]; + assign _zz_memory_DivPlugin_div_stage_0_outNumerator = {_zz_memory_DivPlugin_div_stage_0_remainderShifted,(! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32])}; + assign _zz_memory_DivPlugin_div_result_1 = _zz_memory_DivPlugin_div_result_2; + assign _zz_memory_DivPlugin_div_result_2 = _zz_memory_DivPlugin_div_result_3; + assign _zz_memory_DivPlugin_div_result_3 = ({memory_DivPlugin_div_needRevert,(memory_DivPlugin_div_needRevert ? (~ _zz_memory_DivPlugin_div_result) : _zz_memory_DivPlugin_div_result)} + _zz_memory_DivPlugin_div_result_4); + assign _zz_memory_DivPlugin_div_result_5 = memory_DivPlugin_div_needRevert; + assign _zz_memory_DivPlugin_div_result_4 = {32'd0, _zz_memory_DivPlugin_div_result_5}; + assign _zz_memory_DivPlugin_rs1_3 = _zz_memory_DivPlugin_rs1; + assign _zz_memory_DivPlugin_rs1_2 = {32'd0, _zz_memory_DivPlugin_rs1_3}; + assign _zz_memory_DivPlugin_rs2_2 = _zz_memory_DivPlugin_rs2; + assign _zz_memory_DivPlugin_rs2_1 = {31'd0, _zz_memory_DivPlugin_rs2_2}; + assign _zz_iBusWishbone_ADR_1 = (iBus_cmd_payload_address >>> 5); + assign _zz_decode_RegFilePlugin_rs1Data = 1'b1; + assign _zz_decode_RegFilePlugin_rs2Data = 1'b1; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_6 = {_zz_IBusCachedPlugin_jump_pcLoad_payload_4,_zz_IBusCachedPlugin_jump_pcLoad_payload_3}; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_1 = dataCache_1_io_cpu_writeBack_address[1 : 0]; + assign _zz_writeBack_DBusCachedPlugin_rspShifted_3 = dataCache_1_io_cpu_writeBack_address[1 : 1]; + assign _zz_decode_LEGAL_INSTRUCTION = 32'h0000107f; + assign _zz_decode_LEGAL_INSTRUCTION_1 = (decode_INSTRUCTION & 32'h0000207f); + assign _zz_decode_LEGAL_INSTRUCTION_2 = 32'h00002073; + assign _zz_decode_LEGAL_INSTRUCTION_3 = ((decode_INSTRUCTION & 32'h0000407f) == 32'h00004063); + assign _zz_decode_LEGAL_INSTRUCTION_4 = ((decode_INSTRUCTION & 32'h0000207f) == 32'h00002013); + assign _zz_decode_LEGAL_INSTRUCTION_5 = {((decode_INSTRUCTION & 32'h0000603f) == 32'h00000023),{((decode_INSTRUCTION & 32'h0000207f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_6) == 32'h00000003),{(_zz_decode_LEGAL_INSTRUCTION_7 == _zz_decode_LEGAL_INSTRUCTION_8),{_zz_decode_LEGAL_INSTRUCTION_9,{_zz_decode_LEGAL_INSTRUCTION_10,_zz_decode_LEGAL_INSTRUCTION_11}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_6 = 32'h0000505f; + assign _zz_decode_LEGAL_INSTRUCTION_7 = (decode_INSTRUCTION & 32'h0000707b); + assign _zz_decode_LEGAL_INSTRUCTION_8 = 32'h00000063; + assign _zz_decode_LEGAL_INSTRUCTION_9 = ((decode_INSTRUCTION & 32'h0000607f) == 32'h0000000f); + assign _zz_decode_LEGAL_INSTRUCTION_10 = ((decode_INSTRUCTION & 32'hfc00007f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_11 = {((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f),{((decode_INSTRUCTION & 32'hbc00707f) == 32'h00005013),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION_12) == 32'h00001013),{(_zz_decode_LEGAL_INSTRUCTION_13 == _zz_decode_LEGAL_INSTRUCTION_14),{_zz_decode_LEGAL_INSTRUCTION_15,{_zz_decode_LEGAL_INSTRUCTION_16,_zz_decode_LEGAL_INSTRUCTION_17}}}}}}; + assign _zz_decode_LEGAL_INSTRUCTION_12 = 32'hfc00307f; + assign _zz_decode_LEGAL_INSTRUCTION_13 = (decode_INSTRUCTION & 32'hbe00707f); + assign _zz_decode_LEGAL_INSTRUCTION_14 = 32'h00005033; + assign _zz_decode_LEGAL_INSTRUCTION_15 = ((decode_INSTRUCTION & 32'hbe00707f) == 32'h00000033); + assign _zz_decode_LEGAL_INSTRUCTION_16 = ((decode_INSTRUCTION & 32'hdfffffff) == 32'h10200073); + assign _zz_decode_LEGAL_INSTRUCTION_17 = {((decode_INSTRUCTION & 32'hffffffff) == 32'h10500073),((decode_INSTRUCTION & 32'hffffffff) == 32'h00000073)}; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_4 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_5 = decode_INSTRUCTION[31]; + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_6 = decode_INSTRUCTION[7]; + assign _zz__zz_decode_IS_RS2_SIGNED = (decode_INSTRUCTION & 32'h02004064); + assign _zz__zz_decode_IS_RS2_SIGNED_1 = 32'h02004020; + assign _zz__zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h02004074) == 32'h02000030); + assign _zz__zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00203050) == 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_4 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_5 = (((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_6) == 32'h00000050) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_7 = ({_zz__zz_decode_IS_RS2_SIGNED_8,_zz__zz_decode_IS_RS2_SIGNED_9} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_10 = {({_zz__zz_decode_IS_RS2_SIGNED_11,_zz__zz_decode_IS_RS2_SIGNED_12} != 2'b00),{(_zz__zz_decode_IS_RS2_SIGNED_14 != _zz__zz_decode_IS_RS2_SIGNED_16),{_zz__zz_decode_IS_RS2_SIGNED_17,{_zz__zz_decode_IS_RS2_SIGNED_20,_zz__zz_decode_IS_RS2_SIGNED_28}}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_6 = 32'h00403050; + assign _zz__zz_decode_IS_RS2_SIGNED_8 = ((decode_INSTRUCTION & 32'h00001050) == 32'h00001050); + assign _zz__zz_decode_IS_RS2_SIGNED_9 = ((decode_INSTRUCTION & 32'h00002050) == 32'h00002050); + assign _zz__zz_decode_IS_RS2_SIGNED_11 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_12 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_13) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_14 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_15) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_16 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_17 = ({_zz__zz_decode_IS_RS2_SIGNED_18,_zz__zz_decode_IS_RS2_SIGNED_19} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_20 = ({_zz__zz_decode_IS_RS2_SIGNED_21,_zz__zz_decode_IS_RS2_SIGNED_23} != 3'b000); + assign _zz__zz_decode_IS_RS2_SIGNED_28 = {(_zz__zz_decode_IS_RS2_SIGNED_29 != _zz__zz_decode_IS_RS2_SIGNED_31),{_zz__zz_decode_IS_RS2_SIGNED_32,{_zz__zz_decode_IS_RS2_SIGNED_35,_zz__zz_decode_IS_RS2_SIGNED_37}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_13 = 32'h0000001c; + assign _zz__zz_decode_IS_RS2_SIGNED_15 = 32'h00000058; + assign _zz__zz_decode_IS_RS2_SIGNED_18 = ((decode_INSTRUCTION & 32'h00007034) == 32'h00005010); + assign _zz__zz_decode_IS_RS2_SIGNED_19 = ((decode_INSTRUCTION & 32'h02007064) == 32'h00005020); + assign _zz__zz_decode_IS_RS2_SIGNED_21 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_22) == 32'h40001010); + assign _zz__zz_decode_IS_RS2_SIGNED_23 = {(_zz__zz_decode_IS_RS2_SIGNED_24 == _zz__zz_decode_IS_RS2_SIGNED_25),(_zz__zz_decode_IS_RS2_SIGNED_26 == _zz__zz_decode_IS_RS2_SIGNED_27)}; + assign _zz__zz_decode_IS_RS2_SIGNED_29 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_30) == 32'h00000024); + assign _zz__zz_decode_IS_RS2_SIGNED_31 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_32 = ((_zz__zz_decode_IS_RS2_SIGNED_33 == _zz__zz_decode_IS_RS2_SIGNED_34) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_35 = (_zz__zz_decode_IS_RS2_SIGNED_36 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_37 = {(_zz__zz_decode_IS_RS2_SIGNED_38 != _zz__zz_decode_IS_RS2_SIGNED_43),{_zz__zz_decode_IS_RS2_SIGNED_44,{_zz__zz_decode_IS_RS2_SIGNED_47,_zz__zz_decode_IS_RS2_SIGNED_52}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_22 = 32'h40003054; + assign _zz__zz_decode_IS_RS2_SIGNED_24 = (decode_INSTRUCTION & 32'h00007034); + assign _zz__zz_decode_IS_RS2_SIGNED_25 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_26 = (decode_INSTRUCTION & 32'h02007054); + assign _zz__zz_decode_IS_RS2_SIGNED_27 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_30 = 32'h00000064; + assign _zz__zz_decode_IS_RS2_SIGNED_33 = (decode_INSTRUCTION & 32'h00001000); + assign _zz__zz_decode_IS_RS2_SIGNED_34 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_36 = ((decode_INSTRUCTION & 32'h00003000) == 32'h00002000); + assign _zz__zz_decode_IS_RS2_SIGNED_38 = {(_zz__zz_decode_IS_RS2_SIGNED_39 == _zz__zz_decode_IS_RS2_SIGNED_40),(_zz__zz_decode_IS_RS2_SIGNED_41 == _zz__zz_decode_IS_RS2_SIGNED_42)}; + assign _zz__zz_decode_IS_RS2_SIGNED_43 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_44 = ((_zz__zz_decode_IS_RS2_SIGNED_45 == _zz__zz_decode_IS_RS2_SIGNED_46) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_47 = ({_zz__zz_decode_IS_RS2_SIGNED_48,_zz__zz_decode_IS_RS2_SIGNED_50} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_52 = {(_zz__zz_decode_IS_RS2_SIGNED_53 != _zz__zz_decode_IS_RS2_SIGNED_66),{_zz__zz_decode_IS_RS2_SIGNED_67,{_zz__zz_decode_IS_RS2_SIGNED_70,_zz__zz_decode_IS_RS2_SIGNED_83}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_39 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_40 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_41 = (decode_INSTRUCTION & 32'h00005000); + assign _zz__zz_decode_IS_RS2_SIGNED_42 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_45 = (decode_INSTRUCTION & 32'h00004048); + assign _zz__zz_decode_IS_RS2_SIGNED_46 = 32'h00004008; + assign _zz__zz_decode_IS_RS2_SIGNED_48 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_49) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_50 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_51) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_53 = {(_zz__zz_decode_IS_RS2_SIGNED_54 == _zz__zz_decode_IS_RS2_SIGNED_55),{_zz__zz_decode_IS_RS2_SIGNED_56,{_zz__zz_decode_IS_RS2_SIGNED_58,_zz__zz_decode_IS_RS2_SIGNED_61}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_66 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_67 = ((_zz__zz_decode_IS_RS2_SIGNED_68 == _zz__zz_decode_IS_RS2_SIGNED_69) != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_70 = ({_zz__zz_decode_IS_RS2_SIGNED_71,_zz__zz_decode_IS_RS2_SIGNED_74} != 5'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_83 = {(_zz__zz_decode_IS_RS2_SIGNED_84 != _zz__zz_decode_IS_RS2_SIGNED_97),{_zz__zz_decode_IS_RS2_SIGNED_98,{_zz__zz_decode_IS_RS2_SIGNED_115,_zz__zz_decode_IS_RS2_SIGNED_120}}}; + assign _zz__zz_decode_IS_RS2_SIGNED_49 = 32'h00000034; + assign _zz__zz_decode_IS_RS2_SIGNED_51 = 32'h00000064; + assign _zz__zz_decode_IS_RS2_SIGNED_54 = (decode_INSTRUCTION & 32'h00002040); + assign _zz__zz_decode_IS_RS2_SIGNED_55 = 32'h00002040; + assign _zz__zz_decode_IS_RS2_SIGNED_56 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_57) == 32'h00001040); + assign _zz__zz_decode_IS_RS2_SIGNED_58 = (_zz__zz_decode_IS_RS2_SIGNED_59 == _zz__zz_decode_IS_RS2_SIGNED_60); + assign _zz__zz_decode_IS_RS2_SIGNED_61 = {_zz__zz_decode_IS_RS2_SIGNED_62,_zz__zz_decode_IS_RS2_SIGNED_64}; + assign _zz__zz_decode_IS_RS2_SIGNED_68 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_69 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_71 = (_zz__zz_decode_IS_RS2_SIGNED_72 == _zz__zz_decode_IS_RS2_SIGNED_73); + assign _zz__zz_decode_IS_RS2_SIGNED_74 = {_zz_decode_IS_RS2_SIGNED_2,{_zz__zz_decode_IS_RS2_SIGNED_75,_zz__zz_decode_IS_RS2_SIGNED_78}}; + assign _zz__zz_decode_IS_RS2_SIGNED_84 = {_zz_decode_IS_RS2_SIGNED_2,{_zz__zz_decode_IS_RS2_SIGNED_85,_zz__zz_decode_IS_RS2_SIGNED_88}}; + assign _zz__zz_decode_IS_RS2_SIGNED_97 = 5'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_98 = ({_zz__zz_decode_IS_RS2_SIGNED_99,_zz__zz_decode_IS_RS2_SIGNED_100} != 6'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_115 = (_zz__zz_decode_IS_RS2_SIGNED_116 != _zz__zz_decode_IS_RS2_SIGNED_119); + assign _zz__zz_decode_IS_RS2_SIGNED_120 = {_zz__zz_decode_IS_RS2_SIGNED_121,{_zz__zz_decode_IS_RS2_SIGNED_126,_zz__zz_decode_IS_RS2_SIGNED_131}}; + assign _zz__zz_decode_IS_RS2_SIGNED_57 = 32'h00001040; + assign _zz__zz_decode_IS_RS2_SIGNED_59 = (decode_INSTRUCTION & 32'h00000050); + assign _zz__zz_decode_IS_RS2_SIGNED_60 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_62 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_63) == 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_64 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_65) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_72 = (decode_INSTRUCTION & 32'h00000040); + assign _zz__zz_decode_IS_RS2_SIGNED_73 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_75 = (_zz__zz_decode_IS_RS2_SIGNED_76 == _zz__zz_decode_IS_RS2_SIGNED_77); + assign _zz__zz_decode_IS_RS2_SIGNED_78 = {_zz__zz_decode_IS_RS2_SIGNED_79,_zz__zz_decode_IS_RS2_SIGNED_81}; + assign _zz__zz_decode_IS_RS2_SIGNED_85 = (_zz__zz_decode_IS_RS2_SIGNED_86 == _zz__zz_decode_IS_RS2_SIGNED_87); + assign _zz__zz_decode_IS_RS2_SIGNED_88 = {_zz__zz_decode_IS_RS2_SIGNED_89,{_zz__zz_decode_IS_RS2_SIGNED_91,_zz__zz_decode_IS_RS2_SIGNED_94}}; + assign _zz__zz_decode_IS_RS2_SIGNED_99 = _zz_decode_IS_RS2_SIGNED_3; + assign _zz__zz_decode_IS_RS2_SIGNED_100 = {_zz__zz_decode_IS_RS2_SIGNED_101,{_zz__zz_decode_IS_RS2_SIGNED_103,_zz__zz_decode_IS_RS2_SIGNED_106}}; + assign _zz__zz_decode_IS_RS2_SIGNED_116 = {_zz_decode_IS_RS2_SIGNED_2,_zz__zz_decode_IS_RS2_SIGNED_117}; + assign _zz__zz_decode_IS_RS2_SIGNED_119 = 2'b00; + assign _zz__zz_decode_IS_RS2_SIGNED_121 = ({_zz__zz_decode_IS_RS2_SIGNED_122,_zz__zz_decode_IS_RS2_SIGNED_123} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_126 = (_zz__zz_decode_IS_RS2_SIGNED_127 != _zz__zz_decode_IS_RS2_SIGNED_130); + assign _zz__zz_decode_IS_RS2_SIGNED_131 = {_zz__zz_decode_IS_RS2_SIGNED_132,{_zz__zz_decode_IS_RS2_SIGNED_135,_zz__zz_decode_IS_RS2_SIGNED_146}}; + assign _zz__zz_decode_IS_RS2_SIGNED_63 = 32'h00400040; + assign _zz__zz_decode_IS_RS2_SIGNED_65 = 32'h00000038; + assign _zz__zz_decode_IS_RS2_SIGNED_76 = (decode_INSTRUCTION & 32'h00004020); + assign _zz__zz_decode_IS_RS2_SIGNED_77 = 32'h00004020; + assign _zz__zz_decode_IS_RS2_SIGNED_79 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_80) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_81 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_82) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_86 = (decode_INSTRUCTION & 32'h00002030); + assign _zz__zz_decode_IS_RS2_SIGNED_87 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_89 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_90) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_91 = (_zz__zz_decode_IS_RS2_SIGNED_92 == _zz__zz_decode_IS_RS2_SIGNED_93); + assign _zz__zz_decode_IS_RS2_SIGNED_94 = (_zz__zz_decode_IS_RS2_SIGNED_95 == _zz__zz_decode_IS_RS2_SIGNED_96); + assign _zz__zz_decode_IS_RS2_SIGNED_101 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_102) == 32'h00001010); + assign _zz__zz_decode_IS_RS2_SIGNED_103 = (_zz__zz_decode_IS_RS2_SIGNED_104 == _zz__zz_decode_IS_RS2_SIGNED_105); + assign _zz__zz_decode_IS_RS2_SIGNED_106 = {_zz__zz_decode_IS_RS2_SIGNED_107,{_zz__zz_decode_IS_RS2_SIGNED_109,_zz__zz_decode_IS_RS2_SIGNED_112}}; + assign _zz__zz_decode_IS_RS2_SIGNED_117 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_118) == 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_122 = _zz_decode_IS_RS2_SIGNED_2; + assign _zz__zz_decode_IS_RS2_SIGNED_123 = (_zz__zz_decode_IS_RS2_SIGNED_124 == _zz__zz_decode_IS_RS2_SIGNED_125); + assign _zz__zz_decode_IS_RS2_SIGNED_127 = (_zz__zz_decode_IS_RS2_SIGNED_128 == _zz__zz_decode_IS_RS2_SIGNED_129); + assign _zz__zz_decode_IS_RS2_SIGNED_130 = 1'b0; + assign _zz__zz_decode_IS_RS2_SIGNED_132 = (_zz__zz_decode_IS_RS2_SIGNED_133 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_135 = (_zz__zz_decode_IS_RS2_SIGNED_136 != _zz__zz_decode_IS_RS2_SIGNED_145); + assign _zz__zz_decode_IS_RS2_SIGNED_146 = {_zz__zz_decode_IS_RS2_SIGNED_147,{_zz__zz_decode_IS_RS2_SIGNED_149,_zz__zz_decode_IS_RS2_SIGNED_156}}; + assign _zz__zz_decode_IS_RS2_SIGNED_80 = 32'h00000030; + assign _zz__zz_decode_IS_RS2_SIGNED_82 = 32'h02000020; + assign _zz__zz_decode_IS_RS2_SIGNED_90 = 32'h00001030; + assign _zz__zz_decode_IS_RS2_SIGNED_92 = (decode_INSTRUCTION & 32'h02002060); + assign _zz__zz_decode_IS_RS2_SIGNED_93 = 32'h00002020; + assign _zz__zz_decode_IS_RS2_SIGNED_95 = (decode_INSTRUCTION & 32'h02003020); + assign _zz__zz_decode_IS_RS2_SIGNED_96 = 32'h00000020; + assign _zz__zz_decode_IS_RS2_SIGNED_102 = 32'h00001010; + assign _zz__zz_decode_IS_RS2_SIGNED_104 = (decode_INSTRUCTION & 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_105 = 32'h00002010; + assign _zz__zz_decode_IS_RS2_SIGNED_107 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_108) == 32'h00000010); + assign _zz__zz_decode_IS_RS2_SIGNED_109 = (_zz__zz_decode_IS_RS2_SIGNED_110 == _zz__zz_decode_IS_RS2_SIGNED_111); + assign _zz__zz_decode_IS_RS2_SIGNED_112 = (_zz__zz_decode_IS_RS2_SIGNED_113 == _zz__zz_decode_IS_RS2_SIGNED_114); + assign _zz__zz_decode_IS_RS2_SIGNED_118 = 32'h00000070; + assign _zz__zz_decode_IS_RS2_SIGNED_124 = (decode_INSTRUCTION & 32'h00000020); + assign _zz__zz_decode_IS_RS2_SIGNED_125 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_128 = (decode_INSTRUCTION & 32'h00004014); + assign _zz__zz_decode_IS_RS2_SIGNED_129 = 32'h00004010; + assign _zz__zz_decode_IS_RS2_SIGNED_133 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_134) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_136 = {_zz__zz_decode_IS_RS2_SIGNED_137,{_zz__zz_decode_IS_RS2_SIGNED_138,_zz__zz_decode_IS_RS2_SIGNED_140}}; + assign _zz__zz_decode_IS_RS2_SIGNED_145 = 4'b0000; + assign _zz__zz_decode_IS_RS2_SIGNED_147 = (_zz__zz_decode_IS_RS2_SIGNED_148 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_149 = (_zz__zz_decode_IS_RS2_SIGNED_150 != _zz__zz_decode_IS_RS2_SIGNED_155); + assign _zz__zz_decode_IS_RS2_SIGNED_156 = {_zz__zz_decode_IS_RS2_SIGNED_157,{_zz__zz_decode_IS_RS2_SIGNED_159,_zz__zz_decode_IS_RS2_SIGNED_162}}; + assign _zz__zz_decode_IS_RS2_SIGNED_108 = 32'h00000050; + assign _zz__zz_decode_IS_RS2_SIGNED_110 = (decode_INSTRUCTION & 32'h0000000c); + assign _zz__zz_decode_IS_RS2_SIGNED_111 = 32'h00000004; + assign _zz__zz_decode_IS_RS2_SIGNED_113 = (decode_INSTRUCTION & 32'h00000028); + assign _zz__zz_decode_IS_RS2_SIGNED_114 = 32'h0; + assign _zz__zz_decode_IS_RS2_SIGNED_134 = 32'h00006014; + assign _zz__zz_decode_IS_RS2_SIGNED_137 = ((decode_INSTRUCTION & 32'h00000044) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_138 = ((decode_INSTRUCTION & _zz__zz_decode_IS_RS2_SIGNED_139) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_140 = {(_zz__zz_decode_IS_RS2_SIGNED_141 == _zz__zz_decode_IS_RS2_SIGNED_142),(_zz__zz_decode_IS_RS2_SIGNED_143 == _zz__zz_decode_IS_RS2_SIGNED_144)}; + assign _zz__zz_decode_IS_RS2_SIGNED_148 = ((decode_INSTRUCTION & 32'h00000058) == 32'h0); + assign _zz__zz_decode_IS_RS2_SIGNED_150 = {(_zz__zz_decode_IS_RS2_SIGNED_151 == _zz__zz_decode_IS_RS2_SIGNED_152),{_zz__zz_decode_IS_RS2_SIGNED_153,_zz__zz_decode_IS_RS2_SIGNED_154}}; + assign _zz__zz_decode_IS_RS2_SIGNED_155 = 3'b000; + assign _zz__zz_decode_IS_RS2_SIGNED_157 = ({_zz__zz_decode_IS_RS2_SIGNED_158,_zz_decode_IS_RS2_SIGNED_1} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_159 = ({_zz__zz_decode_IS_RS2_SIGNED_160,_zz__zz_decode_IS_RS2_SIGNED_161} != 2'b00); + assign _zz__zz_decode_IS_RS2_SIGNED_162 = (_zz__zz_decode_IS_RS2_SIGNED_163 != 1'b0); + assign _zz__zz_decode_IS_RS2_SIGNED_139 = 32'h00000018; + assign _zz__zz_decode_IS_RS2_SIGNED_141 = (decode_INSTRUCTION & 32'h00006004); + assign _zz__zz_decode_IS_RS2_SIGNED_142 = 32'h00002000; + assign _zz__zz_decode_IS_RS2_SIGNED_143 = (decode_INSTRUCTION & 32'h00005004); + assign _zz__zz_decode_IS_RS2_SIGNED_144 = 32'h00001000; + assign _zz__zz_decode_IS_RS2_SIGNED_151 = (decode_INSTRUCTION & 32'h00000044); + assign _zz__zz_decode_IS_RS2_SIGNED_152 = 32'h00000040; + assign _zz__zz_decode_IS_RS2_SIGNED_153 = ((decode_INSTRUCTION & 32'h00002014) == 32'h00002010); + assign _zz__zz_decode_IS_RS2_SIGNED_154 = ((decode_INSTRUCTION & 32'h40000034) == 32'h40000030); + assign _zz__zz_decode_IS_RS2_SIGNED_158 = ((decode_INSTRUCTION & 32'h00000014) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_160 = ((decode_INSTRUCTION & 32'h00000044) == 32'h00000004); + assign _zz__zz_decode_IS_RS2_SIGNED_161 = _zz_decode_IS_RS2_SIGNED_1; + assign _zz__zz_decode_IS_RS2_SIGNED_163 = ((decode_INSTRUCTION & 32'h00005048) == 32'h00001008); + assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; + assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; + assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs1Data) begin + _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @(posedge clk) begin + if(_zz_decode_RegFilePlugin_rs2Data) begin + _zz_RegFilePlugin_regFile_port1 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @(posedge clk) begin + if(_zz_1) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (IBusCachedPlugin_cache_io_flush ), //i + .io_cpu_prefetch_isValid (IBusCachedPlugin_cache_io_cpu_prefetch_isValid ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload ), //i + .io_cpu_fetch_isValid (IBusCachedPlugin_cache_io_cpu_fetch_isValid ), //i + .io_cpu_fetch_isStuck (IBusCachedPlugin_cache_io_cpu_fetch_isStuck ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_cache_io_cpu_fetch_isRemoved ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data ), //o + .io_cpu_fetch_mmuRsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_fetch_mmuRsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuRsp_isPaging (IBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_fetch_mmuRsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuRsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuRsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuRsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuRsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuRsp_bypassTranslation (IBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress ), //o + .io_cpu_decode_isValid (IBusCachedPlugin_cache_io_cpu_decode_isValid ), //i + .io_cpu_decode_isStuck (IBusCachedPlugin_cache_io_cpu_decode_isStuck ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (IBusCachedPlugin_cache_io_cpu_decode_isUser ), //i + .io_cpu_fill_valid (IBusCachedPlugin_cache_io_cpu_fill_valid ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1 ( + .io_cpu_execute_isValid (dataCache_1_io_cpu_execute_isValid ), //i + .io_cpu_execute_address (dataCache_1_io_cpu_execute_address ), //i + .io_cpu_execute_haltIt (dataCache_1_io_cpu_execute_haltIt ), //o + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size ), //i + .io_cpu_execute_args_totalyConsistent (execute_MEMORY_FORCE_CONSTISTENCY ), //i + .io_cpu_execute_refilling (dataCache_1_io_cpu_execute_refilling ), //o + .io_cpu_memory_isValid (dataCache_1_io_cpu_memory_isValid ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isWrite (dataCache_1_io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (dataCache_1_io_cpu_memory_address ), //i + .io_cpu_memory_mmuRsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress ), //i + .io_cpu_memory_mmuRsp_isIoAccess (dataCache_1_io_cpu_memory_mmuRsp_isIoAccess ), //i + .io_cpu_memory_mmuRsp_isPaging (DBusCachedPlugin_mmuBus_rsp_isPaging ), //i + .io_cpu_memory_mmuRsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuRsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuRsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuRsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuRsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuRsp_bypassTranslation (DBusCachedPlugin_mmuBus_rsp_bypassTranslation ), //i + .io_cpu_writeBack_isValid (dataCache_1_io_cpu_writeBack_isValid ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (dataCache_1_io_cpu_writeBack_isUser ), //i + .io_cpu_writeBack_haltIt (dataCache_1_io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1_io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_storeData (dataCache_1_io_cpu_writeBack_storeData ), //i + .io_cpu_writeBack_data (dataCache_1_io_cpu_writeBack_data ), //o + .io_cpu_writeBack_address (dataCache_1_io_cpu_writeBack_address ), //i + .io_cpu_writeBack_mmuException (dataCache_1_io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1_io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1_io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_keepMemRspData (dataCache_1_io_cpu_writeBack_keepMemRspData ), //o + .io_cpu_writeBack_fence_SW (dataCache_1_io_cpu_writeBack_fence_SW ), //i + .io_cpu_writeBack_fence_SR (dataCache_1_io_cpu_writeBack_fence_SR ), //i + .io_cpu_writeBack_fence_SO (dataCache_1_io_cpu_writeBack_fence_SO ), //i + .io_cpu_writeBack_fence_SI (dataCache_1_io_cpu_writeBack_fence_SI ), //i + .io_cpu_writeBack_fence_PW (dataCache_1_io_cpu_writeBack_fence_PW ), //i + .io_cpu_writeBack_fence_PR (dataCache_1_io_cpu_writeBack_fence_PR ), //i + .io_cpu_writeBack_fence_PO (dataCache_1_io_cpu_writeBack_fence_PO ), //i + .io_cpu_writeBack_fence_PI (dataCache_1_io_cpu_writeBack_fence_PI ), //i + .io_cpu_writeBack_fence_FM (dataCache_1_io_cpu_writeBack_fence_FM ), //i + .io_cpu_writeBack_exclusiveOk (dataCache_1_io_cpu_writeBack_exclusiveOk ), //o + .io_cpu_redo (dataCache_1_io_cpu_redo ), //o + .io_cpu_flush_valid (dataCache_1_io_cpu_flush_valid ), //i + .io_cpu_flush_ready (dataCache_1_io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (dataCache_1_io_mem_cmd_ready ), //i + .io_mem_cmd_payload_wr (dataCache_1_io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_uncached (dataCache_1_io_mem_cmd_payload_uncached ), //o + .io_mem_cmd_payload_address (dataCache_1_io_mem_cmd_payload_address ), //o + .io_mem_cmd_payload_data (dataCache_1_io_mem_cmd_payload_data ), //o + .io_mem_cmd_payload_mask (dataCache_1_io_mem_cmd_payload_mask ), //o + .io_mem_cmd_payload_size (dataCache_1_io_mem_cmd_payload_size ), //o + .io_mem_cmd_payload_last (dataCache_1_io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_last (dBus_rsp_payload_last ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_IBusCachedPlugin_jump_pcLoad_payload_6) + 2'b00 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = CsrPlugin_jumpInterface_payload; + end + 2'b10 : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = BranchPlugin_jumpInterface_payload; + end + default : begin + _zz_IBusCachedPlugin_jump_pcLoad_payload_5 = IBusCachedPlugin_predictionJumpInterface_payload; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_1) + 2'b00 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_0; + end + 2'b01 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_1; + end + 2'b10 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_2; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + always @(*) begin + case(_zz_writeBack_DBusCachedPlugin_rspShifted_3) + 1'b0 : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_1; + end + default : begin + _zz_writeBack_DBusCachedPlugin_rspShifted_2 = writeBack_DBusCachedPlugin_rspSplits_3; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_memory_to_writeBack_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_to_writeBack_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_to_writeBack_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_to_writeBack_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_to_writeBack_ENV_CTRL_1_string = "ECALL"; + default : _zz_memory_to_writeBack_ENV_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_to_memory_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_to_memory_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_to_memory_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_to_memory_ENV_CTRL_1_string = "ECALL"; + default : _zz_execute_to_memory_ENV_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_ENV_CTRL_string = "ECALL"; + default : decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_string = "ECALL"; + default : _zz_decode_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_to_execute_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_to_execute_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_to_execute_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_to_execute_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_to_execute_ENV_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_to_execute_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_to_execute_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_to_execute_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_to_execute_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_to_memory_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_to_memory_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_execute_to_memory_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_to_execute_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_to_execute_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_to_execute_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_string = "PC "; + default : _zz_decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_to_execute_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_to_execute_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_to_execute_SRC2_CTRL_1_string = "???"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_to_execute_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_to_execute_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_to_execute_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_to_execute_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_to_execute_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_to_execute_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_to_execute_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_to_execute_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_to_execute_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_to_execute_SRC1_CTRL_1_string = "????????????"; + endcase + end + always @(*) begin + case(memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_ENV_CTRL_string = "ECALL"; + default : memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_memory_ENV_CTRL_string = "ECALL"; + default : _zz_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_ENV_CTRL_string = "ECALL"; + default : execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_execute_ENV_CTRL_string = "ECALL"; + default : _zz_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : writeBack_ENV_CTRL_string = "ECALL"; + default : writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : _zz_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_writeBack_ENV_CTRL_string = "ECALL"; + default : _zz_writeBack_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_execute_BRANCH_CTRL_string = "JALR"; + default : _zz_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : memory_SHIFT_CTRL_string = "SRA_1 "; + default : memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_memory_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_execute_SHIFT_CTRL_string = "SRA_1 "; + default : _zz_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : _zz_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_execute_SRC2_CTRL_string = "PC "; + default : _zz_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : _zz_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_execute_SRC1_CTRL_string = "URS1 "; + default : _zz_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_execute_ALU_CTRL_string = "BITWISE "; + default : _zz_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : _zz_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_1) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_1_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_1_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_1_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_1_string = "ECALL"; + default : _zz_decode_ENV_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_1) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_1_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_1_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_1_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_1_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_1_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_1) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_1_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_1_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_1) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_1_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_1_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_1_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_1_string = "PC "; + default : _zz_decode_SRC2_CTRL_1_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_1) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_1_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_1_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_1_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_1_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_1) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_1_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_1_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_1_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_1_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_1_string = "????????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_1) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_1_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_1_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_1_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_1_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC1_CTRL_2) + `Src1CtrlEnum_binary_sequential_RS : _zz_decode_SRC1_CTRL_2_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : _zz_decode_SRC1_CTRL_2_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : _zz_decode_SRC1_CTRL_2_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : _zz_decode_SRC1_CTRL_2_string = "URS1 "; + default : _zz_decode_SRC1_CTRL_2_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_CTRL_2) + `AluCtrlEnum_binary_sequential_ADD_SUB : _zz_decode_ALU_CTRL_2_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : _zz_decode_ALU_CTRL_2_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : _zz_decode_ALU_CTRL_2_string = "BITWISE "; + default : _zz_decode_ALU_CTRL_2_string = "????????"; + endcase + end + always @(*) begin + case(_zz_decode_SRC2_CTRL_2) + `Src2CtrlEnum_binary_sequential_RS : _zz_decode_SRC2_CTRL_2_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : _zz_decode_SRC2_CTRL_2_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : _zz_decode_SRC2_CTRL_2_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : _zz_decode_SRC2_CTRL_2_string = "PC "; + default : _zz_decode_SRC2_CTRL_2_string = "???"; + endcase + end + always @(*) begin + case(_zz_decode_ALU_BITWISE_CTRL_2) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : _zz_decode_ALU_BITWISE_CTRL_2_string = "AND_1"; + default : _zz_decode_ALU_BITWISE_CTRL_2_string = "?????"; + endcase + end + always @(*) begin + case(_zz_decode_SHIFT_CTRL_2) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : _zz_decode_SHIFT_CTRL_2_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : _zz_decode_SHIFT_CTRL_2_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : _zz_decode_SHIFT_CTRL_2_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : _zz_decode_SHIFT_CTRL_2_string = "SRA_1 "; + default : _zz_decode_SHIFT_CTRL_2_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_decode_BRANCH_CTRL_2) + `BranchCtrlEnum_binary_sequential_INC : _zz_decode_BRANCH_CTRL_2_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : _zz_decode_BRANCH_CTRL_2_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : _zz_decode_BRANCH_CTRL_2_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : _zz_decode_BRANCH_CTRL_2_string = "JALR"; + default : _zz_decode_BRANCH_CTRL_2_string = "????"; + endcase + end + always @(*) begin + case(_zz_decode_ENV_CTRL_2) + `EnvCtrlEnum_binary_sequential_NONE : _zz_decode_ENV_CTRL_2_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : _zz_decode_ENV_CTRL_2_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : _zz_decode_ENV_CTRL_2_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : _zz_decode_ENV_CTRL_2_string = "ECALL"; + default : _zz_decode_ENV_CTRL_2_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_binary_sequential_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_binary_sequential_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_binary_sequential_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_binary_sequential_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_binary_sequential_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_binary_sequential_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_binary_sequential_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(execute_to_memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_DISABLE_1 : execute_to_memory_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_binary_sequential_SLL_1 : execute_to_memory_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_binary_sequential_SRL_1 : execute_to_memory_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_binary_sequential_SRA_1 : execute_to_memory_SHIFT_CTRL_string = "SRA_1 "; + default : execute_to_memory_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_binary_sequential_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_binary_sequential_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_binary_sequential_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : decode_to_execute_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL"; + default : decode_to_execute_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : execute_to_memory_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : execute_to_memory_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : execute_to_memory_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : execute_to_memory_ENV_CTRL_string = "ECALL"; + default : execute_to_memory_ENV_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_ENV_CTRL) + `EnvCtrlEnum_binary_sequential_NONE : memory_to_writeBack_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_binary_sequential_XRET : memory_to_writeBack_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_binary_sequential_WFI : memory_to_writeBack_ENV_CTRL_string = "WFI "; + `EnvCtrlEnum_binary_sequential_ECALL : memory_to_writeBack_ENV_CTRL_string = "ECALL"; + default : memory_to_writeBack_ENV_CTRL_string = "?????"; + endcase + end + `endif + + assign memory_MUL_LOW = ($signed(_zz_memory_MUL_LOW) + $signed(_zz_memory_MUL_LOW_7)); + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_HL = ($signed(execute_MulPlugin_aHigh) * $signed(execute_MulPlugin_bSLow)); + assign execute_MUL_LH = ($signed(execute_MulPlugin_aSLow) * $signed(execute_MulPlugin_bHigh)); + assign execute_MUL_LL = (execute_MulPlugin_aULow * execute_MulPlugin_bULow); + assign execute_BRANCH_CALC = {execute_BranchPlugin_branchAdder[31 : 1],1'b0}; + assign execute_BRANCH_DO = ((execute_PREDICTION_HAD_BRANCHED2 != execute_BRANCH_COND_RESULT) || execute_BranchPlugin_missAlignedTarget); + assign execute_SHIFT_RIGHT = _zz_execute_SHIFT_RIGHT; + assign execute_REGFILE_WRITE_DATA = _zz_execute_REGFILE_WRITE_DATA; + assign memory_MEMORY_STORE_DATA_RF = execute_to_memory_MEMORY_STORE_DATA_RF; + assign execute_MEMORY_STORE_DATA_RF = _zz_execute_MEMORY_STORE_DATA_RF; + assign decode_CSR_READ_OPCODE = (decode_INSTRUCTION[13 : 7] != 7'h20); + assign decode_CSR_WRITE_OPCODE = (! (((decode_INSTRUCTION[14 : 13] == 2'b01) && (decode_INSTRUCTION[19 : 15] == 5'h0)) || ((decode_INSTRUCTION[14 : 13] == 2'b11) && (decode_INSTRUCTION[19 : 15] == 5'h0)))); + assign decode_PREDICTION_HAD_BRANCHED2 = IBusCachedPlugin_decodePrediction_cmd_hadBranch; + assign decode_SRC2_FORCE_ZERO = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + assign decode_IS_RS2_SIGNED = _zz_decode_IS_RS2_SIGNED[31]; + assign decode_IS_RS1_SIGNED = _zz_decode_IS_RS2_SIGNED[30]; + assign decode_IS_DIV = _zz_decode_IS_RS2_SIGNED[29]; + assign memory_IS_MUL = execute_to_memory_IS_MUL; + assign execute_IS_MUL = decode_to_execute_IS_MUL; + assign decode_IS_MUL = _zz_decode_IS_RS2_SIGNED[28]; + assign _zz_memory_to_writeBack_ENV_CTRL = _zz_memory_to_writeBack_ENV_CTRL_1; + assign _zz_execute_to_memory_ENV_CTRL = _zz_execute_to_memory_ENV_CTRL_1; + assign decode_ENV_CTRL = _zz_decode_ENV_CTRL; + assign _zz_decode_to_execute_ENV_CTRL = _zz_decode_to_execute_ENV_CTRL_1; + assign decode_IS_CSR = _zz_decode_IS_RS2_SIGNED[25]; + assign _zz_decode_to_execute_BRANCH_CTRL = _zz_decode_to_execute_BRANCH_CTRL_1; + assign _zz_execute_to_memory_SHIFT_CTRL = _zz_execute_to_memory_SHIFT_CTRL_1; + assign decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL = _zz_decode_to_execute_SHIFT_CTRL_1; + assign decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_ALU_BITWISE_CTRL = _zz_decode_to_execute_ALU_BITWISE_CTRL_1; + assign decode_SRC_LESS_UNSIGNED = _zz_decode_IS_RS2_SIGNED[17]; + assign decode_MEMORY_MANAGMENT = _zz_decode_IS_RS2_SIGNED[16]; + assign memory_MEMORY_WR = execute_to_memory_MEMORY_WR; + assign decode_MEMORY_WR = _zz_decode_IS_RS2_SIGNED[13]; + assign execute_BYPASSABLE_MEMORY_STAGE = decode_to_execute_BYPASSABLE_MEMORY_STAGE; + assign decode_BYPASSABLE_MEMORY_STAGE = _zz_decode_IS_RS2_SIGNED[12]; + assign decode_BYPASSABLE_EXECUTE_STAGE = _zz_decode_IS_RS2_SIGNED[11]; + assign decode_SRC2_CTRL = _zz_decode_SRC2_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL = _zz_decode_to_execute_SRC2_CTRL_1; + assign decode_ALU_CTRL = _zz_decode_ALU_CTRL; + assign _zz_decode_to_execute_ALU_CTRL = _zz_decode_to_execute_ALU_CTRL_1; + assign decode_SRC1_CTRL = _zz_decode_SRC1_CTRL; + assign _zz_decode_to_execute_SRC1_CTRL = _zz_decode_to_execute_SRC1_CTRL_1; + assign decode_MEMORY_FORCE_CONSTISTENCY = 1'b0; + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign memory_PC = execute_to_memory_PC; + assign execute_IS_RS1_SIGNED = decode_to_execute_IS_RS1_SIGNED; + assign execute_IS_DIV = decode_to_execute_IS_DIV; + assign execute_IS_RS2_SIGNED = decode_to_execute_IS_RS2_SIGNED; + assign memory_IS_DIV = execute_to_memory_IS_DIV; + assign writeBack_IS_MUL = memory_to_writeBack_IS_MUL; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign memory_ENV_CTRL = _zz_memory_ENV_CTRL; + assign execute_ENV_CTRL = _zz_execute_ENV_CTRL; + assign writeBack_ENV_CTRL = _zz_writeBack_ENV_CTRL; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_PC = decode_to_execute_PC; + assign execute_PREDICTION_HAD_BRANCHED2 = decode_to_execute_PREDICTION_HAD_BRANCHED2; + assign execute_RS1 = decode_to_execute_RS1; + assign execute_BRANCH_COND_RESULT = _zz_execute_BRANCH_COND_RESULT_1; + assign execute_BRANCH_CTRL = _zz_execute_BRANCH_CTRL; + assign decode_RS2_USE = _zz_decode_IS_RS2_SIGNED[15]; + assign decode_RS1_USE = _zz_decode_IS_RS2_SIGNED[5]; + always @(*) begin + _zz_decode_RS2 = execute_REGFILE_WRITE_DATA; + if(when_CsrPlugin_l1176) begin + _zz_decode_RS2 = CsrPlugin_csrMapping_readDataSignal; + end + end + + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign execute_BYPASSABLE_EXECUTE_STAGE = decode_to_execute_BYPASSABLE_EXECUTE_STAGE; + assign memory_REGFILE_WRITE_VALID = execute_to_memory_REGFILE_WRITE_VALID; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_BYPASSABLE_MEMORY_STAGE = execute_to_memory_BYPASSABLE_MEMORY_STAGE; + assign writeBack_REGFILE_WRITE_VALID = memory_to_writeBack_REGFILE_WRITE_VALID; + always @(*) begin + decode_RS2 = decode_RegFilePlugin_rs2Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr1Match) begin + decode_RS2 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l51) begin + decode_RS2 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l51_1) begin + decode_RS2 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l51_2) begin + decode_RS2 = _zz_decode_RS2; + end + end + end + end + + always @(*) begin + decode_RS1 = decode_RegFilePlugin_rs1Data; + if(HazardSimplePlugin_writeBackBuffer_valid) begin + if(HazardSimplePlugin_addr0Match) begin + decode_RS1 = HazardSimplePlugin_writeBackBuffer_payload_data; + end + end + if(when_HazardSimplePlugin_l45) begin + if(when_HazardSimplePlugin_l47) begin + if(when_HazardSimplePlugin_l48) begin + decode_RS1 = _zz_decode_RS2_2; + end + end + end + if(when_HazardSimplePlugin_l45_1) begin + if(memory_BYPASSABLE_MEMORY_STAGE) begin + if(when_HazardSimplePlugin_l48_1) begin + decode_RS1 = _zz_decode_RS2_1; + end + end + end + if(when_HazardSimplePlugin_l45_2) begin + if(execute_BYPASSABLE_EXECUTE_STAGE) begin + if(when_HazardSimplePlugin_l48_2) begin + decode_RS1 = _zz_decode_RS2; + end + end + end + end + + assign memory_SHIFT_RIGHT = execute_to_memory_SHIFT_RIGHT; + always @(*) begin + _zz_decode_RS2_1 = memory_REGFILE_WRITE_DATA; + if(memory_arbitration_isValid) begin + case(memory_SHIFT_CTRL) + `ShiftCtrlEnum_binary_sequential_SLL_1 : begin + _zz_decode_RS2_1 = _zz_decode_RS2_3; + end + `ShiftCtrlEnum_binary_sequential_SRL_1, `ShiftCtrlEnum_binary_sequential_SRA_1 : begin + _zz_decode_RS2_1 = memory_SHIFT_RIGHT; + end + default : begin + end + endcase + end + if(when_MulDivIterativePlugin_l128) begin + _zz_decode_RS2_1 = memory_DivPlugin_div_result; + end + end + + assign memory_SHIFT_CTRL = _zz_memory_SHIFT_CTRL; + assign execute_SHIFT_CTRL = _zz_execute_SHIFT_CTRL; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign _zz_execute_SRC2 = execute_PC; + assign execute_SRC2_CTRL = _zz_execute_SRC2_CTRL; + assign execute_SRC1_CTRL = _zz_execute_SRC1_CTRL; + assign decode_SRC_USE_SUB_LESS = _zz_decode_IS_RS2_SIGNED[3]; + assign decode_SRC_ADD_ZERO = _zz_decode_IS_RS2_SIGNED[20]; + assign execute_SRC_ADD_SUB = execute_SrcPlugin_addSub; + assign execute_SRC_LESS = execute_SrcPlugin_less; + assign execute_ALU_CTRL = _zz_execute_ALU_CTRL; + assign execute_SRC2 = _zz_execute_SRC2_5; + assign execute_SRC1 = _zz_execute_SRC1; + assign execute_ALU_BITWISE_CTRL = _zz_execute_ALU_BITWISE_CTRL; + assign _zz_lastStageRegFileWrite_payload_address = writeBack_INSTRUCTION; + assign _zz_lastStageRegFileWrite_valid = writeBack_REGFILE_WRITE_VALID; + always @(*) begin + _zz_1 = 1'b0; + if(lastStageRegFileWrite_valid) begin + _zz_1 = 1'b1; + end + end + + assign decode_INSTRUCTION_ANTICIPATED = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + always @(*) begin + decode_REGFILE_WRITE_VALID = _zz_decode_IS_RS2_SIGNED[10]; + if(when_RegFilePlugin_l63) begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = ({((decode_INSTRUCTION & 32'h0000005f) == 32'h00000017),{((decode_INSTRUCTION & 32'h0000007f) == 32'h0000006f),{((decode_INSTRUCTION & 32'h0000106f) == 32'h00000003),{((decode_INSTRUCTION & _zz_decode_LEGAL_INSTRUCTION) == 32'h00001073),{(_zz_decode_LEGAL_INSTRUCTION_1 == _zz_decode_LEGAL_INSTRUCTION_2),{_zz_decode_LEGAL_INSTRUCTION_3,{_zz_decode_LEGAL_INSTRUCTION_4,_zz_decode_LEGAL_INSTRUCTION_5}}}}}}} != 21'h0); + always @(*) begin + _zz_decode_RS2_2 = writeBack_REGFILE_WRITE_DATA; + if(when_DBusCachedPlugin_l484) begin + _zz_decode_RS2_2 = writeBack_DBusCachedPlugin_rspFormated; + end + if(when_MulPlugin_l147) begin + case(switch_MulPlugin_l148) + 2'b00 : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2; + end + default : begin + _zz_decode_RS2_2 = _zz__zz_decode_RS2_2_1; + end + endcase + end + end + + assign writeBack_MEMORY_WR = memory_to_writeBack_MEMORY_WR; + assign writeBack_MEMORY_STORE_DATA_RF = memory_to_writeBack_MEMORY_STORE_DATA_RF; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_MEMORY_ENABLE; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_MEMORY_ENABLE; + assign execute_MEMORY_FORCE_CONSTISTENCY = decode_to_execute_MEMORY_FORCE_CONSTISTENCY; + assign execute_MEMORY_MANAGMENT = decode_to_execute_MEMORY_MANAGMENT; + assign execute_RS2 = decode_to_execute_RS2; + assign execute_MEMORY_WR = decode_to_execute_MEMORY_WR; + assign execute_SRC_ADD = execute_SrcPlugin_addSub; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign decode_MEMORY_ENABLE = _zz_decode_IS_RS2_SIGNED[4]; + assign decode_FLUSH_ALL = _zz_decode_IS_RS2_SIGNED[0]; + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_4 = IBusCachedPlugin_rsp_issueDetected_3; + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_rsp_issueDetected_4 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_3 = IBusCachedPlugin_rsp_issueDetected_2; + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_issueDetected_3 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_2 = IBusCachedPlugin_rsp_issueDetected_1; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_rsp_issueDetected_2 = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_rsp_issueDetected_1 = IBusCachedPlugin_rsp_issueDetected; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_issueDetected_1 = 1'b1; + end + end + + assign decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_1; + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + always @(*) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid) begin + _zz_memory_to_writeBack_FORMAL_PC_NEXT = BranchPlugin_jumpInterface_payload; + end + end + + always @(*) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + _zz_decode_to_execute_FORMAL_PC_NEXT = IBusCachedPlugin_predictionJumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @(*) begin + decode_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l303) begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @(*) begin + decode_arbitration_haltByOther = 1'b0; + if(when_HazardSimplePlugin_l113) begin + decode_arbitration_haltByOther = 1'b1; + end + if(CsrPlugin_pipelineLiberator_active) begin + decode_arbitration_haltByOther = 1'b1; + end + if(when_CsrPlugin_l1116) begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_when) begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed) begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + always @(*) begin + decode_arbitration_flushNext = 1'b0; + if(IBusCachedPlugin_predictionJumpInterface_valid) begin + decode_arbitration_flushNext = 1'b1; + end + if(_zz_when) begin + decode_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + execute_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l343) begin + execute_arbitration_haltItself = 1'b1; + end + if(when_CsrPlugin_l1108) begin + if(when_CsrPlugin_l1110) begin + execute_arbitration_haltItself = 1'b1; + end + end + if(when_CsrPlugin_l1180) begin + if(execute_CsrPlugin_blockedBySideEffects) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @(*) begin + execute_arbitration_haltByOther = 1'b0; + if(when_DBusCachedPlugin_l359) begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @(*) begin + execute_arbitration_removeIt = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_removeIt = 1'b1; + end + if(execute_arbitration_isFlushed) begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + always @(*) begin + execute_arbitration_flushNext = 1'b0; + if(CsrPlugin_selfException_valid) begin + execute_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + memory_arbitration_haltItself = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l129) begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @(*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_removeIt = 1'b1; + end + if(memory_arbitration_isFlushed) begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @(*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid) begin + memory_arbitration_flushNext = 1'b1; + end + if(BranchPlugin_branchExceptionPort_valid) begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_haltItself = 1'b0; + if(when_DBusCachedPlugin_l458) begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @(*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_removeIt = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @(*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1019) begin + writeBack_arbitration_flushNext = 1'b1; + end + if(when_CsrPlugin_l1064) begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @(*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(when_CsrPlugin_l922) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1019) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(when_CsrPlugin_l1064) begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if(when_Fetcher_l240) begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + assign CsrPlugin_csrMapping_allowCsrSignal = 1'b0; + assign CsrPlugin_csrMapping_readDataSignal = CsrPlugin_csrMapping_readDataInit; + always @(*) begin + CsrPlugin_inWfi = 1'b0; + if(when_CsrPlugin_l1108) begin + CsrPlugin_inWfi = 1'b1; + end + end + + assign CsrPlugin_thirdPartyWake = 1'b0; + always @(*) begin + CsrPlugin_jumpInterface_valid = 1'b0; + if(when_CsrPlugin_l1019) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + if(when_CsrPlugin_l1064) begin + CsrPlugin_jumpInterface_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_jumpInterface_payload = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(when_CsrPlugin_l1019) begin + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,2'b00}; + end + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign CsrPlugin_allowEbreakException = 1'b1; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != 4'b0000); + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,{DBusCachedPlugin_redoBranch_valid,IBusCachedPlugin_predictionJumpInterface_valid}}} != 4'b0000); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload = {IBusCachedPlugin_predictionJumpInterface_valid,{BranchPlugin_jumpInterface_valid,{CsrPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}}; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_1 = (_zz_IBusCachedPlugin_jump_pcLoad_payload & (~ _zz__zz_IBusCachedPlugin_jump_pcLoad_payload_1)); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_2 = _zz_IBusCachedPlugin_jump_pcLoad_payload_1[3]; + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_3 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[1] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign _zz_IBusCachedPlugin_jump_pcLoad_payload_4 = (_zz_IBusCachedPlugin_jump_pcLoad_payload_1[2] || _zz_IBusCachedPlugin_jump_pcLoad_payload_2); + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_IBusCachedPlugin_jump_pcLoad_payload_5; + always @(*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_fire = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + always @(*) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b1; + end + end + + assign when_Fetcher_l131 = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate); + assign IBusCachedPlugin_fetchPc_output_fire_1 = (IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready); + assign when_Fetcher_l131_1 = ((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready); + always @(*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_IBusCachedPlugin_fetchPc_pc); + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + always @(*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid) begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign when_Fetcher_l158 = (IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)); + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @(*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_0_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_mmuBus_busy) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if(when_IBusCachedPlugin_l267) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready; + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1 = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_1; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = IBusCachedPlugin_fetchPc_pcReg; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid)) || IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready); + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload = _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid; + assign IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_ready = IBusCachedPlugin_iBusRsp_stages_2_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload; + always @(*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if(when_Fetcher_l320) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign when_Fetcher_l240 = (IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid); + assign when_Fetcher_l320 = (! IBusCachedPlugin_pcValids_0); + assign when_Fetcher_l329 = (! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)); + assign when_Fetcher_l329_1 = (! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)); + assign when_Fetcher_l329_2 = (! execute_arbitration_isStuck); + assign when_Fetcher_l329_3 = (! memory_arbitration_isStuck); + assign when_Fetcher_l329_4 = (! writeBack_arbitration_isStuck); + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch = _zz__zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch[11]; + always @(*) begin + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[18] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[17] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[16] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[15] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[14] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[13] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[12] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[11] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[10] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[9] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[8] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[7] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[6] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[5] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[4] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[3] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[2] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[1] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_1[0] = _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch; + end + + always @(*) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) || ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_B) && _zz_IBusCachedPlugin_decodePrediction_cmd_hadBranch_2[31])); + if(_zz_6) begin + IBusCachedPlugin_decodePrediction_cmd_hadBranch = 1'b0; + end + end + + assign _zz_2 = _zz__zz_2[19]; + always @(*) begin + _zz_3[10] = _zz_2; + _zz_3[9] = _zz_2; + _zz_3[8] = _zz_2; + _zz_3[7] = _zz_2; + _zz_3[6] = _zz_2; + _zz_3[5] = _zz_2; + _zz_3[4] = _zz_2; + _zz_3[3] = _zz_2; + _zz_3[2] = _zz_2; + _zz_3[1] = _zz_2; + _zz_3[0] = _zz_2; + end + + assign _zz_4 = _zz__zz_4[11]; + always @(*) begin + _zz_5[18] = _zz_4; + _zz_5[17] = _zz_4; + _zz_5[16] = _zz_4; + _zz_5[15] = _zz_4; + _zz_5[14] = _zz_4; + _zz_5[13] = _zz_4; + _zz_5[12] = _zz_4; + _zz_5[11] = _zz_4; + _zz_5[10] = _zz_4; + _zz_5[9] = _zz_4; + _zz_5[8] = _zz_4; + _zz_5[7] = _zz_4; + _zz_5[6] = _zz_4; + _zz_5[5] = _zz_4; + _zz_5[4] = _zz_4; + _zz_5[3] = _zz_4; + _zz_5[2] = _zz_4; + _zz_5[1] = _zz_4; + _zz_5[0] = _zz_4; + end + + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_6 = _zz__zz_6[1]; + end + default : begin + _zz_6 = _zz__zz_6_1[1]; + end + endcase + end + + assign IBusCachedPlugin_predictionJumpInterface_valid = (decode_arbitration_isValid && IBusCachedPlugin_decodePrediction_cmd_hadBranch); + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload[19]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_1[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload; + end + + assign _zz_IBusCachedPlugin_predictionJumpInterface_payload_2 = _zz__zz_IBusCachedPlugin_predictionJumpInterface_payload_2[11]; + always @(*) begin + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[18] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[17] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[16] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[15] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[14] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[13] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[12] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[11] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[10] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[9] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[8] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[7] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[6] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[5] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[4] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[3] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[2] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[1] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + _zz_IBusCachedPlugin_predictionJumpInterface_payload_3[0] = _zz_IBusCachedPlugin_predictionJumpInterface_payload_2; + end + + assign IBusCachedPlugin_predictionJumpInterface_payload = (decode_PC + ((decode_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_1,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_4,decode_INSTRUCTION[19 : 12]},decode_INSTRUCTION[20]},decode_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_IBusCachedPlugin_predictionJumpInterface_payload_3,{{{_zz_IBusCachedPlugin_predictionJumpInterface_payload_5,_zz_IBusCachedPlugin_predictionJumpInterface_payload_6},decode_INSTRUCTION[30 : 25]},decode_INSTRUCTION[11 : 8]}},1'b0})); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @(*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign IBusCachedPlugin_cache_io_cpu_prefetch_isValid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isValid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_fetch_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_isValid = IBusCachedPlugin_cache_io_cpu_fetch_isValid; + assign IBusCachedPlugin_mmuBus_cmd_0_isStuck = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign IBusCachedPlugin_mmuBus_cmd_0_virtualAddress = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + assign IBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign IBusCachedPlugin_mmuBus_end = (IBusCachedPlugin_iBusRsp_stages_1_input_ready || IBusCachedPlugin_externalFlush); + assign IBusCachedPlugin_cache_io_cpu_decode_isValid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign IBusCachedPlugin_cache_io_cpu_decode_isStuck = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign IBusCachedPlugin_cache_io_cpu_decode_isUser = (CsrPlugin_privilege == 2'b00); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @(*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(when_IBusCachedPlugin_l239) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(when_IBusCachedPlugin_l250) begin + IBusCachedPlugin_cache_io_cpu_fill_valid = 1'b1; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @(*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'bxxxx; + if(when_IBusCachedPlugin_l244) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b1100; + end + if(when_IBusCachedPlugin_l256) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = 4'b0001; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],2'b00}; + assign when_IBusCachedPlugin_l239 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign when_IBusCachedPlugin_l244 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! IBusCachedPlugin_rsp_issueDetected_1)); + assign when_IBusCachedPlugin_l250 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! IBusCachedPlugin_rsp_issueDetected_2)); + assign when_IBusCachedPlugin_l256 = ((IBusCachedPlugin_cache_io_cpu_decode_isValid && IBusCachedPlugin_cache_io_cpu_decode_error) && (! IBusCachedPlugin_rsp_issueDetected_3)); + assign when_IBusCachedPlugin_l267 = (IBusCachedPlugin_rsp_issueDetected_4 || IBusCachedPlugin_rsp_iBusRspOutputHalt); + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + assign IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign IBusCachedPlugin_cache_io_flush = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign dataCache_1_io_mem_cmd_ready = (! dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_valid = (dataCache_1_io_mem_cmd_valid || dataCache_1_io_mem_cmd_rValid); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_wr = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_wr : dataCache_1_io_mem_cmd_payload_wr); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_uncached = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_uncached : dataCache_1_io_mem_cmd_payload_uncached); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_address = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_address : dataCache_1_io_mem_cmd_payload_address); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_data = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_data : dataCache_1_io_mem_cmd_payload_data); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_mask = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_mask : dataCache_1_io_mem_cmd_payload_mask); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_size = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_size : dataCache_1_io_mem_cmd_payload_size); + assign dataCache_1_io_mem_cmd_s2mPipe_payload_last = (dataCache_1_io_mem_cmd_rValid ? dataCache_1_io_mem_cmd_rData_last : dataCache_1_io_mem_cmd_payload_last); + always @(*) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready; + if(when_Stream_l342) begin + dataCache_1_io_mem_cmd_s2mPipe_ready = 1'b1; + end + end + + assign when_Stream_l342 = (! dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid); + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid = dataCache_1_io_mem_cmd_s2mPipe_rValid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_rData_wr; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_rData_uncached; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address = dataCache_1_io_mem_cmd_s2mPipe_rData_address; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data = dataCache_1_io_mem_cmd_s2mPipe_rData_data; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_rData_mask; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size = dataCache_1_io_mem_cmd_s2mPipe_rData_size; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last = dataCache_1_io_mem_cmd_s2mPipe_rData_last; + assign dBus_cmd_valid = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_valid; + assign dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_wr; + assign dBus_cmd_payload_uncached = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_uncached; + assign dBus_cmd_payload_address = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_mask; + assign dBus_cmd_payload_size = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_size; + assign dBus_cmd_payload_last = dataCache_1_io_mem_cmd_s2mPipe_m2sPipe_payload_last; + assign when_DBusCachedPlugin_l303 = ((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE); + assign execute_DBusCachedPlugin_size = execute_INSTRUCTION[13 : 12]; + assign dataCache_1_io_cpu_execute_isValid = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign dataCache_1_io_cpu_execute_address = execute_SRC_ADD; + always @(*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_execute_MEMORY_STORE_DATA_RF = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_execute_MEMORY_STORE_DATA_RF = execute_RS2[31 : 0]; + end + endcase + end + + assign dataCache_1_io_cpu_flush_valid = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + assign dataCache_1_io_cpu_flush_isStall = (dataCache_1_io_cpu_flush_valid && (! dataCache_1_io_cpu_flush_ready)); + assign when_DBusCachedPlugin_l343 = (dataCache_1_io_cpu_flush_isStall || dataCache_1_io_cpu_execute_haltIt); + assign when_DBusCachedPlugin_l359 = (dataCache_1_io_cpu_execute_refilling && execute_arbitration_isValid); + assign dataCache_1_io_cpu_memory_isValid = (memory_arbitration_isValid && memory_MEMORY_ENABLE); + assign dataCache_1_io_cpu_memory_address = memory_REGFILE_WRITE_DATA; + assign DBusCachedPlugin_mmuBus_cmd_0_isValid = dataCache_1_io_cpu_memory_isValid; + assign DBusCachedPlugin_mmuBus_cmd_0_isStuck = memory_arbitration_isStuck; + assign DBusCachedPlugin_mmuBus_cmd_0_virtualAddress = dataCache_1_io_cpu_memory_address; + assign DBusCachedPlugin_mmuBus_cmd_0_bypassTranslation = 1'b0; + assign DBusCachedPlugin_mmuBus_end = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + always @(*) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if(when_DBusCachedPlugin_l386) begin + dataCache_1_io_cpu_memory_mmuRsp_isIoAccess = 1'b1; + end + end + + assign when_DBusCachedPlugin_l386 = (1'b0 && (! dataCache_1_io_cpu_memory_isWrite)); + always @(*) begin + dataCache_1_io_cpu_writeBack_isValid = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + if(writeBack_arbitration_haltByOther) begin + dataCache_1_io_cpu_writeBack_isValid = 1'b0; + end + end + + assign dataCache_1_io_cpu_writeBack_isUser = (CsrPlugin_privilege == 2'b00); + assign dataCache_1_io_cpu_writeBack_address = writeBack_REGFILE_WRITE_DATA; + assign dataCache_1_io_cpu_writeBack_storeData[31 : 0] = writeBack_MEMORY_STORE_DATA_RF; + always @(*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @(*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1_io_cpu_redo) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_REGFILE_WRITE_DATA; + always @(*) begin + DBusCachedPlugin_exceptionBus_payload_code = 4'bxxxx; + if(when_DBusCachedPlugin_l438) begin + if(dataCache_1_io_cpu_writeBack_accessError) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code}; + end + if(dataCache_1_io_cpu_writeBack_mmuException) begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? 4'b1111 : 4'b1101); + end + if(dataCache_1_io_cpu_writeBack_unalignedAccess) begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_DBusCachedPlugin_exceptionBus_payload_code_1}; + end + end + end + + assign when_DBusCachedPlugin_l438 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign when_DBusCachedPlugin_l458 = (dataCache_1_io_cpu_writeBack_isValid && dataCache_1_io_cpu_writeBack_haltIt); + assign writeBack_DBusCachedPlugin_rspSplits_0 = dataCache_1_io_cpu_writeBack_data[7 : 0]; + assign writeBack_DBusCachedPlugin_rspSplits_1 = dataCache_1_io_cpu_writeBack_data[15 : 8]; + assign writeBack_DBusCachedPlugin_rspSplits_2 = dataCache_1_io_cpu_writeBack_data[23 : 16]; + assign writeBack_DBusCachedPlugin_rspSplits_3 = dataCache_1_io_cpu_writeBack_data[31 : 24]; + always @(*) begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = _zz_writeBack_DBusCachedPlugin_rspShifted; + writeBack_DBusCachedPlugin_rspShifted[15 : 8] = _zz_writeBack_DBusCachedPlugin_rspShifted_2; + writeBack_DBusCachedPlugin_rspShifted[23 : 16] = writeBack_DBusCachedPlugin_rspSplits_2; + writeBack_DBusCachedPlugin_rspShifted[31 : 24] = writeBack_DBusCachedPlugin_rspSplits_3; + end + + assign writeBack_DBusCachedPlugin_rspRf = writeBack_DBusCachedPlugin_rspShifted[31 : 0]; + assign switch_Misc_l200 = writeBack_INSTRUCTION[13 : 12]; + assign _zz_writeBack_DBusCachedPlugin_rspFormated = (writeBack_DBusCachedPlugin_rspRf[7] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_1[31] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[30] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[29] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[28] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[27] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[26] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[25] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[24] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[23] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[22] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[21] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[20] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[19] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[18] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[17] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[16] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[15] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[14] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[13] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[12] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[11] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[10] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[9] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[8] = _zz_writeBack_DBusCachedPlugin_rspFormated; + _zz_writeBack_DBusCachedPlugin_rspFormated_1[7 : 0] = writeBack_DBusCachedPlugin_rspRf[7 : 0]; + end + + assign _zz_writeBack_DBusCachedPlugin_rspFormated_2 = (writeBack_DBusCachedPlugin_rspRf[15] && (! writeBack_INSTRUCTION[14])); + always @(*) begin + _zz_writeBack_DBusCachedPlugin_rspFormated_3[31] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[30] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[29] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[28] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[27] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[26] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[25] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[24] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[23] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[22] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[21] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[20] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[19] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[18] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[17] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[16] = _zz_writeBack_DBusCachedPlugin_rspFormated_2; + _zz_writeBack_DBusCachedPlugin_rspFormated_3[15 : 0] = writeBack_DBusCachedPlugin_rspRf[15 : 0]; + end + + always @(*) begin + case(switch_Misc_l200) + 2'b00 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_1; + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspFormated = _zz_writeBack_DBusCachedPlugin_rspFormated_3; + end + default : begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspRf; + end + endcase + end + + assign when_DBusCachedPlugin_l484 = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = IBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign IBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_0_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = DBusCachedPlugin_mmuBus_rsp_physicalAddress[31]; + assign DBusCachedPlugin_mmuBus_rsp_isPaging = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_decode_IS_RS2_SIGNED_1 = ((decode_INSTRUCTION & 32'h00004050) == 32'h00004050); + assign _zz_decode_IS_RS2_SIGNED_2 = ((decode_INSTRUCTION & 32'h00000004) == 32'h00000004); + assign _zz_decode_IS_RS2_SIGNED_3 = ((decode_INSTRUCTION & 32'h00000048) == 32'h00000048); + assign _zz_decode_IS_RS2_SIGNED_4 = ((decode_INSTRUCTION & 32'h00001000) == 32'h0); + assign _zz_decode_IS_RS2_SIGNED = {(_zz_decode_IS_RS2_SIGNED_4 != 1'b0),{(_zz_decode_IS_RS2_SIGNED_4 != 1'b0),{((_zz__zz_decode_IS_RS2_SIGNED == _zz__zz_decode_IS_RS2_SIGNED_1) != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_2 != 1'b0),{(_zz__zz_decode_IS_RS2_SIGNED_3 != _zz__zz_decode_IS_RS2_SIGNED_4),{_zz__zz_decode_IS_RS2_SIGNED_5,{_zz__zz_decode_IS_RS2_SIGNED_7,_zz__zz_decode_IS_RS2_SIGNED_10}}}}}}}; + assign _zz_decode_SRC1_CTRL_2 = _zz_decode_IS_RS2_SIGNED[2 : 1]; + assign _zz_decode_SRC1_CTRL_1 = _zz_decode_SRC1_CTRL_2; + assign _zz_decode_ALU_CTRL_2 = _zz_decode_IS_RS2_SIGNED[7 : 6]; + assign _zz_decode_ALU_CTRL_1 = _zz_decode_ALU_CTRL_2; + assign _zz_decode_SRC2_CTRL_2 = _zz_decode_IS_RS2_SIGNED[9 : 8]; + assign _zz_decode_SRC2_CTRL_1 = _zz_decode_SRC2_CTRL_2; + assign _zz_decode_ALU_BITWISE_CTRL_2 = _zz_decode_IS_RS2_SIGNED[19 : 18]; + assign _zz_decode_ALU_BITWISE_CTRL_1 = _zz_decode_ALU_BITWISE_CTRL_2; + assign _zz_decode_SHIFT_CTRL_2 = _zz_decode_IS_RS2_SIGNED[22 : 21]; + assign _zz_decode_SHIFT_CTRL_1 = _zz_decode_SHIFT_CTRL_2; + assign _zz_decode_BRANCH_CTRL_2 = _zz_decode_IS_RS2_SIGNED[24 : 23]; + assign _zz_decode_BRANCH_CTRL = _zz_decode_BRANCH_CTRL_2; + assign _zz_decode_ENV_CTRL_2 = _zz_decode_IS_RS2_SIGNED[27 : 26]; + assign _zz_decode_ENV_CTRL_1 = _zz_decode_ENV_CTRL_2; + assign decodeExceptionPort_valid = (decode_arbitration_isValid && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = 4'b0010; + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign when_RegFilePlugin_l63 = (decode_INSTRUCTION[11 : 7] == 5'h0); + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[19 : 15]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[24 : 20]; + assign decode_RegFilePlugin_rs1Data = _zz_RegFilePlugin_regFile_port0; + assign decode_RegFilePlugin_rs2Data = _zz_RegFilePlugin_regFile_port1; + always @(*) begin + lastStageRegFileWrite_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + if(_zz_7) begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + if(_zz_7) begin + lastStageRegFileWrite_payload_address = 5'h0; + end + end + + always @(*) begin + lastStageRegFileWrite_payload_data = _zz_decode_RS2_2; + if(_zz_7) begin + lastStageRegFileWrite_payload_data = 32'h0; + end + end + + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_binary_sequential_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_binary_sequential_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_binary_sequential_BITWISE : begin + _zz_execute_REGFILE_WRITE_DATA = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_binary_sequential_SLT_SLTU : begin + _zz_execute_REGFILE_WRITE_DATA = {31'd0, _zz__zz_execute_REGFILE_WRITE_DATA}; + end + default : begin + _zz_execute_REGFILE_WRITE_DATA = execute_SRC_ADD_SUB; + end + endcase + end + + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC1 = execute_RS1; + end + `Src1CtrlEnum_binary_sequential_PC_INCREMENT : begin + _zz_execute_SRC1 = {29'd0, _zz__zz_execute_SRC1}; + end + `Src1CtrlEnum_binary_sequential_IMU : begin + _zz_execute_SRC1 = {execute_INSTRUCTION[31 : 12],12'h0}; + end + default : begin + _zz_execute_SRC1 = {27'd0, _zz__zz_execute_SRC1_1}; + end + endcase + end + + assign _zz_execute_SRC2_1 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_SRC2_2[19] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[18] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[17] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[16] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[15] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[14] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[13] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[12] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[11] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[10] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[9] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[8] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[7] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[6] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[5] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[4] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[3] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[2] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[1] = _zz_execute_SRC2_1; + _zz_execute_SRC2_2[0] = _zz_execute_SRC2_1; + end + + assign _zz_execute_SRC2_3 = _zz__zz_execute_SRC2_3[11]; + always @(*) begin + _zz_execute_SRC2_4[19] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[18] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[17] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[16] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[15] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[14] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[13] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[12] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[11] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[10] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[9] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[8] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[7] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[6] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[5] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[4] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[3] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[2] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[1] = _zz_execute_SRC2_3; + _zz_execute_SRC2_4[0] = _zz_execute_SRC2_3; + end + + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_binary_sequential_RS : begin + _zz_execute_SRC2_5 = execute_RS2; + end + `Src2CtrlEnum_binary_sequential_IMI : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_2,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_binary_sequential_IMS : begin + _zz_execute_SRC2_5 = {_zz_execute_SRC2_4,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_execute_SRC2_5 = _zz_execute_SRC2; + end + endcase + end + + always @(*) begin + execute_SrcPlugin_addSub = _zz_execute_SrcPlugin_addSub; + if(execute_SRC2_FORCE_ZERO) begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign execute_FullBarrelShifterPlugin_amplitude = execute_SRC2[4 : 0]; + always @(*) begin + _zz_execute_FullBarrelShifterPlugin_reversed[0] = execute_SRC1[31]; + _zz_execute_FullBarrelShifterPlugin_reversed[1] = execute_SRC1[30]; + _zz_execute_FullBarrelShifterPlugin_reversed[2] = execute_SRC1[29]; + _zz_execute_FullBarrelShifterPlugin_reversed[3] = execute_SRC1[28]; + _zz_execute_FullBarrelShifterPlugin_reversed[4] = execute_SRC1[27]; + _zz_execute_FullBarrelShifterPlugin_reversed[5] = execute_SRC1[26]; + _zz_execute_FullBarrelShifterPlugin_reversed[6] = execute_SRC1[25]; + _zz_execute_FullBarrelShifterPlugin_reversed[7] = execute_SRC1[24]; + _zz_execute_FullBarrelShifterPlugin_reversed[8] = execute_SRC1[23]; + _zz_execute_FullBarrelShifterPlugin_reversed[9] = execute_SRC1[22]; + _zz_execute_FullBarrelShifterPlugin_reversed[10] = execute_SRC1[21]; + _zz_execute_FullBarrelShifterPlugin_reversed[11] = execute_SRC1[20]; + _zz_execute_FullBarrelShifterPlugin_reversed[12] = execute_SRC1[19]; + _zz_execute_FullBarrelShifterPlugin_reversed[13] = execute_SRC1[18]; + _zz_execute_FullBarrelShifterPlugin_reversed[14] = execute_SRC1[17]; + _zz_execute_FullBarrelShifterPlugin_reversed[15] = execute_SRC1[16]; + _zz_execute_FullBarrelShifterPlugin_reversed[16] = execute_SRC1[15]; + _zz_execute_FullBarrelShifterPlugin_reversed[17] = execute_SRC1[14]; + _zz_execute_FullBarrelShifterPlugin_reversed[18] = execute_SRC1[13]; + _zz_execute_FullBarrelShifterPlugin_reversed[19] = execute_SRC1[12]; + _zz_execute_FullBarrelShifterPlugin_reversed[20] = execute_SRC1[11]; + _zz_execute_FullBarrelShifterPlugin_reversed[21] = execute_SRC1[10]; + _zz_execute_FullBarrelShifterPlugin_reversed[22] = execute_SRC1[9]; + _zz_execute_FullBarrelShifterPlugin_reversed[23] = execute_SRC1[8]; + _zz_execute_FullBarrelShifterPlugin_reversed[24] = execute_SRC1[7]; + _zz_execute_FullBarrelShifterPlugin_reversed[25] = execute_SRC1[6]; + _zz_execute_FullBarrelShifterPlugin_reversed[26] = execute_SRC1[5]; + _zz_execute_FullBarrelShifterPlugin_reversed[27] = execute_SRC1[4]; + _zz_execute_FullBarrelShifterPlugin_reversed[28] = execute_SRC1[3]; + _zz_execute_FullBarrelShifterPlugin_reversed[29] = execute_SRC1[2]; + _zz_execute_FullBarrelShifterPlugin_reversed[30] = execute_SRC1[1]; + _zz_execute_FullBarrelShifterPlugin_reversed[31] = execute_SRC1[0]; + end + + assign execute_FullBarrelShifterPlugin_reversed = ((execute_SHIFT_CTRL == `ShiftCtrlEnum_binary_sequential_SLL_1) ? _zz_execute_FullBarrelShifterPlugin_reversed : execute_SRC1); + always @(*) begin + _zz_decode_RS2_3[0] = memory_SHIFT_RIGHT[31]; + _zz_decode_RS2_3[1] = memory_SHIFT_RIGHT[30]; + _zz_decode_RS2_3[2] = memory_SHIFT_RIGHT[29]; + _zz_decode_RS2_3[3] = memory_SHIFT_RIGHT[28]; + _zz_decode_RS2_3[4] = memory_SHIFT_RIGHT[27]; + _zz_decode_RS2_3[5] = memory_SHIFT_RIGHT[26]; + _zz_decode_RS2_3[6] = memory_SHIFT_RIGHT[25]; + _zz_decode_RS2_3[7] = memory_SHIFT_RIGHT[24]; + _zz_decode_RS2_3[8] = memory_SHIFT_RIGHT[23]; + _zz_decode_RS2_3[9] = memory_SHIFT_RIGHT[22]; + _zz_decode_RS2_3[10] = memory_SHIFT_RIGHT[21]; + _zz_decode_RS2_3[11] = memory_SHIFT_RIGHT[20]; + _zz_decode_RS2_3[12] = memory_SHIFT_RIGHT[19]; + _zz_decode_RS2_3[13] = memory_SHIFT_RIGHT[18]; + _zz_decode_RS2_3[14] = memory_SHIFT_RIGHT[17]; + _zz_decode_RS2_3[15] = memory_SHIFT_RIGHT[16]; + _zz_decode_RS2_3[16] = memory_SHIFT_RIGHT[15]; + _zz_decode_RS2_3[17] = memory_SHIFT_RIGHT[14]; + _zz_decode_RS2_3[18] = memory_SHIFT_RIGHT[13]; + _zz_decode_RS2_3[19] = memory_SHIFT_RIGHT[12]; + _zz_decode_RS2_3[20] = memory_SHIFT_RIGHT[11]; + _zz_decode_RS2_3[21] = memory_SHIFT_RIGHT[10]; + _zz_decode_RS2_3[22] = memory_SHIFT_RIGHT[9]; + _zz_decode_RS2_3[23] = memory_SHIFT_RIGHT[8]; + _zz_decode_RS2_3[24] = memory_SHIFT_RIGHT[7]; + _zz_decode_RS2_3[25] = memory_SHIFT_RIGHT[6]; + _zz_decode_RS2_3[26] = memory_SHIFT_RIGHT[5]; + _zz_decode_RS2_3[27] = memory_SHIFT_RIGHT[4]; + _zz_decode_RS2_3[28] = memory_SHIFT_RIGHT[3]; + _zz_decode_RS2_3[29] = memory_SHIFT_RIGHT[2]; + _zz_decode_RS2_3[30] = memory_SHIFT_RIGHT[1]; + _zz_decode_RS2_3[31] = memory_SHIFT_RIGHT[0]; + end + + always @(*) begin + HazardSimplePlugin_src0Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l48) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l48_1) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l48_2) begin + HazardSimplePlugin_src0Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l105) begin + HazardSimplePlugin_src0Hazard = 1'b0; + end + end + + always @(*) begin + HazardSimplePlugin_src1Hazard = 1'b0; + if(when_HazardSimplePlugin_l57) begin + if(when_HazardSimplePlugin_l58) begin + if(when_HazardSimplePlugin_l51) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_1) begin + if(when_HazardSimplePlugin_l58_1) begin + if(when_HazardSimplePlugin_l51_1) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l57_2) begin + if(when_HazardSimplePlugin_l58_2) begin + if(when_HazardSimplePlugin_l51_2) begin + HazardSimplePlugin_src1Hazard = 1'b1; + end + end + end + if(when_HazardSimplePlugin_l108) begin + HazardSimplePlugin_src1Hazard = 1'b0; + end + end + + assign HazardSimplePlugin_writeBackWrites_valid = (_zz_lastStageRegFileWrite_valid && writeBack_arbitration_isFiring); + assign HazardSimplePlugin_writeBackWrites_payload_address = _zz_lastStageRegFileWrite_payload_address[11 : 7]; + assign HazardSimplePlugin_writeBackWrites_payload_data = _zz_decode_RS2_2; + assign HazardSimplePlugin_addr0Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[19 : 15]); + assign HazardSimplePlugin_addr1Match = (HazardSimplePlugin_writeBackBuffer_payload_address == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l47 = 1'b1; + assign when_HazardSimplePlugin_l48 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51 = (writeBack_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57 = (writeBack_arbitration_isValid && writeBack_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58 = (1'b0 || (! when_HazardSimplePlugin_l47)); + assign when_HazardSimplePlugin_l48_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_1 = (memory_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_1 = (memory_arbitration_isValid && memory_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_1 = (1'b0 || (! memory_BYPASSABLE_MEMORY_STAGE)); + assign when_HazardSimplePlugin_l48_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[19 : 15]); + assign when_HazardSimplePlugin_l51_2 = (execute_INSTRUCTION[11 : 7] == decode_INSTRUCTION[24 : 20]); + assign when_HazardSimplePlugin_l45_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l57_2 = (execute_arbitration_isValid && execute_REGFILE_WRITE_VALID); + assign when_HazardSimplePlugin_l58_2 = (1'b0 || (! execute_BYPASSABLE_EXECUTE_STAGE)); + assign when_HazardSimplePlugin_l105 = (! decode_RS1_USE); + assign when_HazardSimplePlugin_l108 = (! decode_RS2_USE); + assign when_HazardSimplePlugin_l113 = (decode_arbitration_isValid && (HazardSimplePlugin_src0Hazard || HazardSimplePlugin_src1Hazard)); + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign switch_Misc_l200_1 = execute_INSTRUCTION[14 : 12]; + always @(*) begin + casez(switch_Misc_l200_1) + 3'b000 : begin + _zz_execute_BRANCH_COND_RESULT = execute_BranchPlugin_eq; + end + 3'b001 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_BranchPlugin_eq); + end + 3'b1?1 : begin + _zz_execute_BRANCH_COND_RESULT = (! execute_SRC_LESS); + end + default : begin + _zz_execute_BRANCH_COND_RESULT = execute_SRC_LESS; + end + endcase + end + + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_INC : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b0; + end + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; + end + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BRANCH_COND_RESULT_1 = 1'b1; + end + default : begin + _zz_execute_BRANCH_COND_RESULT_1 = _zz_execute_BRANCH_COND_RESULT; + end + endcase + end + + assign _zz_execute_BranchPlugin_missAlignedTarget = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_1[19] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[18] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[17] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[16] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[15] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[14] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[13] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[12] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[11] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[10] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[9] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[8] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[7] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[6] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[5] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[4] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[3] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[2] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[1] = _zz_execute_BranchPlugin_missAlignedTarget; + _zz_execute_BranchPlugin_missAlignedTarget_1[0] = _zz_execute_BranchPlugin_missAlignedTarget; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_2 = _zz__zz_execute_BranchPlugin_missAlignedTarget_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_3[10] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[9] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[8] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[7] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[6] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[5] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[4] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[3] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[2] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[1] = _zz_execute_BranchPlugin_missAlignedTarget_2; + _zz_execute_BranchPlugin_missAlignedTarget_3[0] = _zz_execute_BranchPlugin_missAlignedTarget_2; + end + + assign _zz_execute_BranchPlugin_missAlignedTarget_4 = _zz__zz_execute_BranchPlugin_missAlignedTarget_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_missAlignedTarget_5[18] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[17] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[16] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[15] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[14] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[13] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[12] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[11] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[10] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[9] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[8] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[7] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[6] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[5] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[4] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[3] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[2] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[1] = _zz_execute_BranchPlugin_missAlignedTarget_4; + _zz_execute_BranchPlugin_missAlignedTarget_5[0] = _zz_execute_BranchPlugin_missAlignedTarget_4; + end + + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_JALR : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = (_zz__zz_execute_BranchPlugin_missAlignedTarget_6[1] ^ execute_RS1[1]); + end + `BranchCtrlEnum_binary_sequential_JAL : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_1[1]; + end + default : begin + _zz_execute_BranchPlugin_missAlignedTarget_6 = _zz__zz_execute_BranchPlugin_missAlignedTarget_6_2[1]; + end + endcase + end + + assign execute_BranchPlugin_missAlignedTarget = (execute_BRANCH_COND_RESULT && _zz_execute_BranchPlugin_missAlignedTarget_6); + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src1 = execute_RS1; + end + default : begin + execute_BranchPlugin_branch_src1 = execute_PC; + end + endcase + end + + assign _zz_execute_BranchPlugin_branch_src2 = execute_INSTRUCTION[31]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_1[19] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[18] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[17] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[16] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[15] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[14] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[13] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[12] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[11] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[10] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[9] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[8] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[7] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[6] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[5] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[4] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[3] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[2] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[1] = _zz_execute_BranchPlugin_branch_src2; + _zz_execute_BranchPlugin_branch_src2_1[0] = _zz_execute_BranchPlugin_branch_src2; + end + + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_binary_sequential_JALR : begin + execute_BranchPlugin_branch_src2 = {_zz_execute_BranchPlugin_branch_src2_1,execute_INSTRUCTION[31 : 20]}; + end + default : begin + execute_BranchPlugin_branch_src2 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_binary_sequential_JAL) ? {{_zz_execute_BranchPlugin_branch_src2_3,{{{_zz_execute_BranchPlugin_branch_src2_6,execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0} : {{_zz_execute_BranchPlugin_branch_src2_5,{{{_zz_execute_BranchPlugin_branch_src2_7,_zz_execute_BranchPlugin_branch_src2_8},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}); + if(execute_PREDICTION_HAD_BRANCHED2) begin + execute_BranchPlugin_branch_src2 = {29'd0, _zz_execute_BranchPlugin_branch_src2_9}; + end + end + endcase + end + + assign _zz_execute_BranchPlugin_branch_src2_2 = _zz__zz_execute_BranchPlugin_branch_src2_2[19]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_3[10] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[9] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[8] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[7] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[6] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[5] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[4] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[3] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[2] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[1] = _zz_execute_BranchPlugin_branch_src2_2; + _zz_execute_BranchPlugin_branch_src2_3[0] = _zz_execute_BranchPlugin_branch_src2_2; + end + + assign _zz_execute_BranchPlugin_branch_src2_4 = _zz__zz_execute_BranchPlugin_branch_src2_4[11]; + always @(*) begin + _zz_execute_BranchPlugin_branch_src2_5[18] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[17] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[16] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[15] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[14] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[13] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[12] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[11] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[10] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[9] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[8] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[7] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[6] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[5] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[4] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[3] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[2] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[1] = _zz_execute_BranchPlugin_branch_src2_4; + _zz_execute_BranchPlugin_branch_src2_5[0] = _zz_execute_BranchPlugin_branch_src2_4; + end + + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = memory_BRANCH_CALC; + assign BranchPlugin_branchExceptionPort_valid = (memory_arbitration_isValid && (memory_BRANCH_DO && memory_BRANCH_CALC[1])); + assign BranchPlugin_branchExceptionPort_payload_code = 4'b0000; + assign BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + assign IBusCachedPlugin_decodePrediction_rsp_wasWrong = BranchPlugin_jumpInterface_valid; + always @(*) begin + CsrPlugin_privilege = 2'b11; + if(CsrPlugin_forceMachineWire) begin + CsrPlugin_privilege = 2'b11; + end + end + + assign _zz_when_CsrPlugin_l952 = (CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE); + assign _zz_when_CsrPlugin_l952_1 = (CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE); + assign _zz_when_CsrPlugin_l952_2 = (CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = 2'b11; + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 = _zz__zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1[0]; + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @(*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + assign when_CsrPlugin_l909 = (! decode_arbitration_isStuck); + assign when_CsrPlugin_l909_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l909_2 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l909_3 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l922 = ({CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValids_memory,{CsrPlugin_exceptionPortCtrl_exceptionValids_execute,CsrPlugin_exceptionPortCtrl_exceptionValids_decode}}} != 4'b0000); + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign CsrPlugin_exceptionPendings_2 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign CsrPlugin_exceptionPendings_3 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign when_CsrPlugin_l946 = (CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < 2'b11)); + assign when_CsrPlugin_l952 = ((_zz_when_CsrPlugin_l952 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_1 = ((_zz_when_CsrPlugin_l952_1 && 1'b1) && (! 1'b0)); + assign when_CsrPlugin_l952_2 = ((_zz_when_CsrPlugin_l952_2 && 1'b1) && (! 1'b0)); + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack && CsrPlugin_allowException); + assign CsrPlugin_pipelineLiberator_active = ((CsrPlugin_interrupt_valid && CsrPlugin_allowInterrupts) && decode_arbitration_isValid); + assign when_CsrPlugin_l980 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l980_1 = (! memory_arbitration_isStuck); + assign when_CsrPlugin_l980_2 = (! writeBack_arbitration_isStuck); + assign when_CsrPlugin_l985 = ((! CsrPlugin_pipelineLiberator_active) || decode_arbitration_removeIt); + always @(*) begin + CsrPlugin_pipelineLiberator_done = CsrPlugin_pipelineLiberator_pcValids_2; + if(when_CsrPlugin_l991) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException) begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign when_CsrPlugin_l991 = ({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != 3'b000); + assign CsrPlugin_interruptJump = ((CsrPlugin_interrupt_valid && CsrPlugin_pipelineLiberator_done) && CsrPlugin_allowInterrupts); + always @(*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interrupt_targetPrivilege; + if(CsrPlugin_hadException) begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @(*) begin + CsrPlugin_trapCause = CsrPlugin_interrupt_code; + if(CsrPlugin_hadException) begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @(*) begin + CsrPlugin_xtvec_mode = 2'bxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + end + default : begin + end + endcase + end + + always @(*) begin + CsrPlugin_xtvec_base = 30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign when_CsrPlugin_l1019 = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign when_CsrPlugin_l1064 = (writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign switch_CsrPlugin_l1068 = writeBack_INSTRUCTION[29 : 28]; + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign when_CsrPlugin_l1108 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + assign when_CsrPlugin_l1110 = (! execute_CsrPlugin_wfiWake); + assign when_CsrPlugin_l1116 = ({(writeBack_arbitration_isValid && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),{(memory_arbitration_isValid && (memory_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)),(execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET))}} != 3'b000); + assign execute_CsrPlugin_blockedBySideEffects = (({writeBack_arbitration_isValid,memory_arbitration_isValid} != 2'b00) || 1'b0); + always @(*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + if(execute_CsrPlugin_csr_3264) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3857) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3858) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3859) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3860) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_769) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_768) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_836) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_772) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_773) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_833) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_832) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_834) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_835) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2816) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2944) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2818) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_2946) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_3072) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3200) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3074) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3202) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(execute_CsrPlugin_csr_3008) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(execute_CsrPlugin_csr_4032) begin + if(execute_CSR_READ_OPCODE) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + if(CsrPlugin_csrMapping_allowCsrSignal) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + if(when_CsrPlugin_l1297) begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(when_CsrPlugin_l1302) begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if(when_CsrPlugin_l1136) begin + if(when_CsrPlugin_l1137) begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @(*) begin + CsrPlugin_selfException_valid = 1'b0; + if(when_CsrPlugin_l1129) begin + CsrPlugin_selfException_valid = 1'b1; + end + if(when_CsrPlugin_l1144) begin + CsrPlugin_selfException_valid = 1'b1; + end + end + + always @(*) begin + CsrPlugin_selfException_payload_code = 4'bxxxx; + if(when_CsrPlugin_l1129) begin + CsrPlugin_selfException_payload_code = 4'b0010; + end + if(when_CsrPlugin_l1144) begin + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = 4'b1000; + end + default : begin + CsrPlugin_selfException_payload_code = 4'b1011; + end + endcase + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign when_CsrPlugin_l1129 = (execute_CsrPlugin_illegalAccess || execute_CsrPlugin_illegalInstruction); + assign when_CsrPlugin_l1136 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_XRET)); + assign when_CsrPlugin_l1137 = (CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]); + assign when_CsrPlugin_l1144 = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_binary_sequential_ECALL)); + always @(*) begin + execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + if(when_CsrPlugin_l1297) begin + execute_CsrPlugin_writeInstruction = 1'b0; + end + end + + always @(*) begin + execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + if(when_CsrPlugin_l1297) begin + execute_CsrPlugin_readInstruction = 1'b0; + end + end + + assign execute_CsrPlugin_writeEnable = (execute_CsrPlugin_writeInstruction && (! execute_arbitration_isStuck)); + assign execute_CsrPlugin_readEnable = (execute_CsrPlugin_readInstruction && (! execute_arbitration_isStuck)); + assign CsrPlugin_csrMapping_hazardFree = (! execute_CsrPlugin_blockedBySideEffects); + assign execute_CsrPlugin_readToWriteData = CsrPlugin_csrMapping_readDataSignal; + assign switch_Misc_l200_2 = execute_INSTRUCTION[13]; + always @(*) begin + case(switch_Misc_l200_2) + 1'b0 : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = execute_SRC1; + end + default : begin + _zz_CsrPlugin_csrMapping_writeDataSignal = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign CsrPlugin_csrMapping_writeDataSignal = _zz_CsrPlugin_csrMapping_writeDataSignal; + assign when_CsrPlugin_l1176 = (execute_arbitration_isValid && execute_IS_CSR); + assign when_CsrPlugin_l1180 = (execute_arbitration_isValid && (execute_IS_CSR || 1'b0)); + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign execute_MulPlugin_a = execute_RS1; + assign execute_MulPlugin_b = execute_RS2; + assign switch_MulPlugin_l87 = execute_INSTRUCTION[13 : 12]; + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_aSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_aSigned = 1'b1; + end + default : begin + execute_MulPlugin_aSigned = 1'b0; + end + endcase + end + + always @(*) begin + case(switch_MulPlugin_l87) + 2'b01 : begin + execute_MulPlugin_bSigned = 1'b1; + end + 2'b10 : begin + execute_MulPlugin_bSigned = 1'b0; + end + default : begin + execute_MulPlugin_bSigned = 1'b0; + end + endcase + end + + assign execute_MulPlugin_aULow = execute_MulPlugin_a[15 : 0]; + assign execute_MulPlugin_bULow = execute_MulPlugin_b[15 : 0]; + assign execute_MulPlugin_aSLow = {1'b0,execute_MulPlugin_a[15 : 0]}; + assign execute_MulPlugin_bSLow = {1'b0,execute_MulPlugin_b[15 : 0]}; + assign execute_MulPlugin_aHigh = {(execute_MulPlugin_aSigned && execute_MulPlugin_a[31]),execute_MulPlugin_a[31 : 16]}; + assign execute_MulPlugin_bHigh = {(execute_MulPlugin_bSigned && execute_MulPlugin_b[31]),execute_MulPlugin_b[31 : 16]}; + assign writeBack_MulPlugin_result = ($signed(_zz_writeBack_MulPlugin_result) + $signed(_zz_writeBack_MulPlugin_result_1)); + assign when_MulPlugin_l147 = (writeBack_arbitration_isValid && writeBack_IS_MUL); + assign switch_MulPlugin_l148 = writeBack_INSTRUCTION[13 : 12]; + assign memory_DivPlugin_frontendOk = 1'b1; + always @(*) begin + memory_DivPlugin_div_counter_willIncrement = 1'b0; + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_DivPlugin_div_counter_willIncrement = 1'b1; + end + end + end + + always @(*) begin + memory_DivPlugin_div_counter_willClear = 1'b0; + if(when_MulDivIterativePlugin_l162) begin + memory_DivPlugin_div_counter_willClear = 1'b1; + end + end + + assign memory_DivPlugin_div_counter_willOverflowIfInc = (memory_DivPlugin_div_counter_value == 6'h21); + assign memory_DivPlugin_div_counter_willOverflow = (memory_DivPlugin_div_counter_willOverflowIfInc && memory_DivPlugin_div_counter_willIncrement); + always @(*) begin + if(memory_DivPlugin_div_counter_willOverflow) begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end else begin + memory_DivPlugin_div_counter_valueNext = (memory_DivPlugin_div_counter_value + _zz_memory_DivPlugin_div_counter_valueNext); + end + if(memory_DivPlugin_div_counter_willClear) begin + memory_DivPlugin_div_counter_valueNext = 6'h0; + end + end + + assign when_MulDivIterativePlugin_l126 = (memory_DivPlugin_div_counter_value == 6'h20); + assign when_MulDivIterativePlugin_l126_1 = (! memory_arbitration_isStuck); + assign when_MulDivIterativePlugin_l128 = (memory_arbitration_isValid && memory_IS_DIV); + assign when_MulDivIterativePlugin_l129 = ((! memory_DivPlugin_frontendOk) || (! memory_DivPlugin_div_done)); + assign when_MulDivIterativePlugin_l132 = (memory_DivPlugin_frontendOk && (! memory_DivPlugin_div_done)); + assign _zz_memory_DivPlugin_div_stage_0_remainderShifted = memory_DivPlugin_rs1[31 : 0]; + assign memory_DivPlugin_div_stage_0_remainderShifted = {memory_DivPlugin_accumulator[31 : 0],_zz_memory_DivPlugin_div_stage_0_remainderShifted[31]}; + assign memory_DivPlugin_div_stage_0_remainderMinusDenominator = (memory_DivPlugin_div_stage_0_remainderShifted - _zz_memory_DivPlugin_div_stage_0_remainderMinusDenominator); + assign memory_DivPlugin_div_stage_0_outRemainder = ((! memory_DivPlugin_div_stage_0_remainderMinusDenominator[32]) ? _zz_memory_DivPlugin_div_stage_0_outRemainder : _zz_memory_DivPlugin_div_stage_0_outRemainder_1); + assign memory_DivPlugin_div_stage_0_outNumerator = _zz_memory_DivPlugin_div_stage_0_outNumerator[31:0]; + assign when_MulDivIterativePlugin_l151 = (memory_DivPlugin_div_counter_value == 6'h20); + assign _zz_memory_DivPlugin_div_result = (memory_INSTRUCTION[13] ? memory_DivPlugin_accumulator[31 : 0] : memory_DivPlugin_rs1[31 : 0]); + assign when_MulDivIterativePlugin_l162 = (! memory_arbitration_isStuck); + assign _zz_memory_DivPlugin_rs2 = (execute_RS2[31] && execute_IS_RS2_SIGNED); + assign _zz_memory_DivPlugin_rs1 = (1'b0 || ((execute_IS_DIV && execute_RS1[31]) && execute_IS_RS1_SIGNED)); + always @(*) begin + _zz_memory_DivPlugin_rs1_1[32] = (execute_IS_RS1_SIGNED && execute_RS1[31]); + _zz_memory_DivPlugin_rs1_1[31 : 0] = execute_RS1; + end + + assign _zz_CsrPlugin_csrMapping_readDataInit_1 = (_zz_CsrPlugin_csrMapping_readDataInit & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_CsrPlugin_csrMapping_readDataInit_1 != 32'h0); + assign when_Pipeline_l124 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); + assign when_Pipeline_l124_3 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_4 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_5 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_6 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_7 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_8 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_9 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_SRC1_CTRL_1 = decode_SRC1_CTRL; + assign _zz_decode_SRC1_CTRL = _zz_decode_SRC1_CTRL_1; + assign when_Pipeline_l124_10 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC1_CTRL = decode_to_execute_SRC1_CTRL; + assign when_Pipeline_l124_11 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_12 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_13 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_14 = (! writeBack_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_CTRL_1 = decode_ALU_CTRL; + assign _zz_decode_ALU_CTRL = _zz_decode_ALU_CTRL_1; + assign when_Pipeline_l124_15 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_CTRL = decode_to_execute_ALU_CTRL; + assign _zz_decode_to_execute_SRC2_CTRL_1 = decode_SRC2_CTRL; + assign _zz_decode_SRC2_CTRL = _zz_decode_SRC2_CTRL_1; + assign when_Pipeline_l124_16 = (! execute_arbitration_isStuck); + assign _zz_execute_SRC2_CTRL = decode_to_execute_SRC2_CTRL; + assign when_Pipeline_l124_17 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_18 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_19 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_20 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_21 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_22 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_23 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_24 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_25 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_26 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_27 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ALU_BITWISE_CTRL_1 = decode_ALU_BITWISE_CTRL; + assign _zz_decode_ALU_BITWISE_CTRL = _zz_decode_ALU_BITWISE_CTRL_1; + assign when_Pipeline_l124_28 = (! execute_arbitration_isStuck); + assign _zz_execute_ALU_BITWISE_CTRL = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_decode_to_execute_SHIFT_CTRL_1 = decode_SHIFT_CTRL; + assign _zz_execute_to_memory_SHIFT_CTRL_1 = execute_SHIFT_CTRL; + assign _zz_decode_SHIFT_CTRL = _zz_decode_SHIFT_CTRL_1; + assign when_Pipeline_l124_29 = (! execute_arbitration_isStuck); + assign _zz_execute_SHIFT_CTRL = decode_to_execute_SHIFT_CTRL; + assign when_Pipeline_l124_30 = (! memory_arbitration_isStuck); + assign _zz_memory_SHIFT_CTRL = execute_to_memory_SHIFT_CTRL; + assign _zz_decode_to_execute_BRANCH_CTRL_1 = decode_BRANCH_CTRL; + assign _zz_decode_BRANCH_CTRL_1 = _zz_decode_BRANCH_CTRL; + assign when_Pipeline_l124_31 = (! execute_arbitration_isStuck); + assign _zz_execute_BRANCH_CTRL = decode_to_execute_BRANCH_CTRL; + assign when_Pipeline_l124_32 = (! execute_arbitration_isStuck); + assign _zz_decode_to_execute_ENV_CTRL_1 = decode_ENV_CTRL; + assign _zz_execute_to_memory_ENV_CTRL_1 = execute_ENV_CTRL; + assign _zz_memory_to_writeBack_ENV_CTRL_1 = memory_ENV_CTRL; + assign _zz_decode_ENV_CTRL = _zz_decode_ENV_CTRL_1; + assign when_Pipeline_l124_33 = (! execute_arbitration_isStuck); + assign _zz_execute_ENV_CTRL = decode_to_execute_ENV_CTRL; + assign when_Pipeline_l124_34 = (! memory_arbitration_isStuck); + assign _zz_memory_ENV_CTRL = execute_to_memory_ENV_CTRL; + assign when_Pipeline_l124_35 = (! writeBack_arbitration_isStuck); + assign _zz_writeBack_ENV_CTRL = memory_to_writeBack_ENV_CTRL; + assign when_Pipeline_l124_36 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_37 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_38 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_39 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_40 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_41 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_42 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_43 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_44 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_45 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_46 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_47 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_48 = (! execute_arbitration_isStuck); + assign when_Pipeline_l124_49 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_50 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_51 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_52 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_53 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_54 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_55 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_56 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_57 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_58 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_59 = (! memory_arbitration_isStuck); + assign when_Pipeline_l124_60 = (! writeBack_arbitration_isStuck); + assign when_Pipeline_l124_61 = (! writeBack_arbitration_isStuck); + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != 3'b000) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != 4'b0000)); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != 2'b00) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != 3'b000)); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != 1'b0) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != 2'b00)); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != 1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + assign when_Pipeline_l151 = ((! execute_arbitration_isStuck) || execute_arbitration_removeIt); + assign when_Pipeline_l154 = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign when_Pipeline_l151_1 = ((! memory_arbitration_isStuck) || memory_arbitration_removeIt); + assign when_Pipeline_l154_1 = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign when_Pipeline_l151_2 = ((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt); + assign when_Pipeline_l154_2 = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign when_CsrPlugin_l1264 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_1 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_2 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_3 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_4 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_5 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_6 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_7 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_8 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_9 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_10 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_11 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_12 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_13 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_14 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_15 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_16 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_17 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_18 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_19 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_20 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); + assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; + if(execute_CsrPlugin_csr_3264) begin + _zz_CsrPlugin_csrMapping_readDataInit_2[12 : 0] = 13'h1000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; + if(execute_CsrPlugin_csr_3857) begin + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; + if(execute_CsrPlugin_csr_3858) begin + _zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; + if(execute_CsrPlugin_csr_3859) begin + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; + if(execute_CsrPlugin_csr_769) begin + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; + if(execute_CsrPlugin_csr_768) begin + _zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; + if(execute_CsrPlugin_csr_836) begin + _zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; + if(execute_CsrPlugin_csr_772) begin + _zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + if(execute_CsrPlugin_csr_773) begin + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + if(execute_CsrPlugin_csr_833) begin + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + if(execute_CsrPlugin_csr_832) begin + _zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + if(execute_CsrPlugin_csr_834) begin + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + if(execute_CsrPlugin_csr_835) begin + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + if(execute_CsrPlugin_csr_2816) begin + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + if(execute_CsrPlugin_csr_2944) begin + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + if(execute_CsrPlugin_csr_2818) begin + _zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + if(execute_CsrPlugin_csr_2946) begin + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + if(execute_CsrPlugin_csr_3072) begin + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0]; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + if(execute_CsrPlugin_csr_3200) begin + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32]; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + if(execute_CsrPlugin_csr_3074) begin + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0]; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + if(execute_CsrPlugin_csr_3202) begin + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32]; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + if(execute_CsrPlugin_csr_3008) begin + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; + end + end + + always @(*) begin + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + if(execute_CsrPlugin_csr_4032) begin + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; + end + end + + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))); + assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); + assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); + assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; + assign iBusWishbone_CTI = ((_zz_iBusWishbone_ADR == 3'b111) ? 3'b111 : 3'b010); + assign iBusWishbone_BTE = 2'b00; + assign iBusWishbone_SEL = 4'b1111; + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + always @(*) begin + iBusWishbone_CYC = 1'b0; + if(when_InstructionCache_l239) begin + iBusWishbone_CYC = 1'b1; + end + end + + always @(*) begin + iBusWishbone_STB = 1'b0; + if(when_InstructionCache_l239) begin + iBusWishbone_STB = 1'b1; + end + end + + assign when_InstructionCache_l239 = (iBus_cmd_valid || (_zz_iBusWishbone_ADR != 3'b000)); + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_iBus_rsp_valid; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_dBus_cmd_ready_5 = (dBus_cmd_payload_size == 3'b101); + assign _zz_dBus_cmd_ready_1 = dBus_cmd_valid; + assign _zz_dBus_cmd_ready_3 = dBus_cmd_payload_wr; + assign _zz_dBus_cmd_ready_4 = ((! _zz_dBus_cmd_ready_5) || (_zz_dBus_cmd_ready == 3'b111)); + assign dBus_cmd_ready = (_zz_dBus_cmd_ready_2 && (_zz_dBus_cmd_ready_3 || _zz_dBus_cmd_ready_4)); + assign dBusWishbone_ADR = ((_zz_dBus_cmd_ready_5 ? {{dBus_cmd_payload_address[31 : 5],_zz_dBus_cmd_ready},2'b00} : {dBus_cmd_payload_address[31 : 2],2'b00}) >>> 2); + assign dBusWishbone_CTI = (_zz_dBus_cmd_ready_5 ? (_zz_dBus_cmd_ready_4 ? 3'b111 : 3'b010) : 3'b000); + assign dBusWishbone_BTE = 2'b00; + assign dBusWishbone_SEL = (_zz_dBus_cmd_ready_3 ? dBus_cmd_payload_mask : 4'b1111); + assign dBusWishbone_WE = _zz_dBus_cmd_ready_3; + assign dBusWishbone_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_dBus_cmd_ready_2 = (_zz_dBus_cmd_ready_1 && dBusWishbone_ACK); + assign dBusWishbone_CYC = _zz_dBus_cmd_ready_1; + assign dBusWishbone_STB = _zz_dBus_cmd_ready_1; + assign dBus_rsp_valid = _zz_dBus_rsp_valid; + assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @(posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_IBusCachedPlugin_rspCounter; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1_io_mem_cmd_rValid <= 1'b0; + dataCache_1_io_mem_cmd_s2mPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_DBusCachedPlugin_rspCounter; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_7 <= 1'b1; + HazardSimplePlugin_writeBackBuffer_valid <= 1'b0; + CsrPlugin_misa_base <= 2'b01; + CsrPlugin_misa_extensions <= 26'h0000042; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= 2'b11; + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + CsrPlugin_interrupt_valid <= 1'b0; + CsrPlugin_lastStageWasWfi <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + CsrPlugin_hadException <= 1'b0; + execute_CsrPlugin_wfiWake <= 1'b0; + memory_DivPlugin_div_counter_value <= 6'h0; + _zz_CsrPlugin_csrMapping_readDataInit <= 32'h0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + _zz_iBusWishbone_ADR <= 3'b000; + _zz_iBus_rsp_valid <= 1'b0; + _zz_dBus_cmd_ready <= 3'b000; + _zz_dBus_rsp_valid <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_output_fire) begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if(when_Fetcher_l131) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_output_fire_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(when_Fetcher_l131_1) begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(when_Fetcher_l158) begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= 1'b0; + end + if(_zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_0_output_ready_2 <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_valid <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if(when_Fetcher_l329) begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(when_Fetcher_l329_1) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(when_Fetcher_l329_2) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(when_Fetcher_l329_3) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(when_Fetcher_l329_4) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed) begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid) begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(dataCache_1_io_mem_cmd_valid) begin + dataCache_1_io_mem_cmd_rValid <= 1'b1; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_rValid <= 1'b0; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rValid <= dataCache_1_io_mem_cmd_s2mPipe_valid; + end + if(dBus_rsp_valid) begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_7 <= 1'b0; + HazardSimplePlugin_writeBackBuffer_valid <= HazardSimplePlugin_writeBackWrites_valid; + if(when_CsrPlugin_l909) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if(when_CsrPlugin_l909_1) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if(when_CsrPlugin_l909_2) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= CsrPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if(when_CsrPlugin_l909_3) begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (CsrPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + CsrPlugin_interrupt_valid <= 1'b0; + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l952_1) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + if(when_CsrPlugin_l952_2) begin + CsrPlugin_interrupt_valid <= 1'b1; + end + end + CsrPlugin_lastStageWasWfi <= (writeBack_arbitration_isFiring && (writeBack_ENV_CTRL == `EnvCtrlEnum_binary_sequential_WFI)); + if(CsrPlugin_pipelineLiberator_active) begin + if(when_CsrPlugin_l980) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if(when_CsrPlugin_l980_1) begin + CsrPlugin_pipelineLiberator_pcValids_1 <= CsrPlugin_pipelineLiberator_pcValids_0; + end + if(when_CsrPlugin_l980_2) begin + CsrPlugin_pipelineLiberator_pcValids_2 <= CsrPlugin_pipelineLiberator_pcValids_1; + end + end + if(when_CsrPlugin_l985) begin + CsrPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + CsrPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + if(CsrPlugin_interruptJump) begin + CsrPlugin_interrupt_valid <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(when_CsrPlugin_l1019) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(when_CsrPlugin_l1064) begin + case(switch_CsrPlugin_l1068) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= 2'b00; + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + execute_CsrPlugin_wfiWake <= (({_zz_when_CsrPlugin_l952_2,{_zz_when_CsrPlugin_l952_1,_zz_when_CsrPlugin_l952}} != 3'b000) || CsrPlugin_thirdPartyWake); + memory_DivPlugin_div_counter_value <= memory_DivPlugin_div_counter_valueNext; + if(when_Pipeline_l151) begin + execute_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154) begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(when_Pipeline_l151_1) begin + memory_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_1) begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(when_Pipeline_l151_2) begin + writeBack_arbitration_isValid <= 1'b0; + end + if(when_Pipeline_l154_2) begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_CsrPlugin_csr_769) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_misa_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 30]; + CsrPlugin_misa_extensions <= CsrPlugin_csrMapping_writeDataSignal[25 : 0]; + end + end + if(execute_CsrPlugin_csr_768) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mstatus_MPP <= CsrPlugin_csrMapping_writeDataSignal[12 : 11]; + CsrPlugin_mstatus_MPIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mstatus_MIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + if(execute_CsrPlugin_csr_772) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mie_MEIE <= CsrPlugin_csrMapping_writeDataSignal[11]; + CsrPlugin_mie_MTIE <= CsrPlugin_csrMapping_writeDataSignal[7]; + CsrPlugin_mie_MSIE <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + if(execute_CsrPlugin_csr_3008) begin + if(execute_CsrPlugin_writeEnable) begin + _zz_CsrPlugin_csrMapping_readDataInit <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(when_InstructionCache_l239) begin + if(iBusWishbone_ACK) begin + _zz_iBusWishbone_ADR <= (_zz_iBusWishbone_ADR + 3'b001); + end + end + _zz_iBus_rsp_valid <= (iBusWishbone_CYC && iBusWishbone_ACK); + if((_zz_dBus_cmd_ready_1 && _zz_dBus_cmd_ready_2)) begin + _zz_dBus_cmd_ready <= (_zz_dBus_cmd_ready + 3'b001); + if(_zz_dBus_cmd_ready_4) begin + _zz_dBus_cmd_ready <= 3'b000; + end + end + _zz_dBus_rsp_valid <= ((_zz_dBus_cmd_ready_1 && (! dBusWishbone_WE)) && dBusWishbone_ACK); + end + end + + always @(posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready) begin + _zz_IBusCachedPlugin_iBusRsp_stages_1_output_m2sPipe_payload <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready) begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready) begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(dataCache_1_io_mem_cmd_ready) begin + dataCache_1_io_mem_cmd_rData_wr <= dataCache_1_io_mem_cmd_payload_wr; + dataCache_1_io_mem_cmd_rData_uncached <= dataCache_1_io_mem_cmd_payload_uncached; + dataCache_1_io_mem_cmd_rData_address <= dataCache_1_io_mem_cmd_payload_address; + dataCache_1_io_mem_cmd_rData_data <= dataCache_1_io_mem_cmd_payload_data; + dataCache_1_io_mem_cmd_rData_mask <= dataCache_1_io_mem_cmd_payload_mask; + dataCache_1_io_mem_cmd_rData_size <= dataCache_1_io_mem_cmd_payload_size; + dataCache_1_io_mem_cmd_rData_last <= dataCache_1_io_mem_cmd_payload_last; + end + if(dataCache_1_io_mem_cmd_s2mPipe_ready) begin + dataCache_1_io_mem_cmd_s2mPipe_rData_wr <= dataCache_1_io_mem_cmd_s2mPipe_payload_wr; + dataCache_1_io_mem_cmd_s2mPipe_rData_uncached <= dataCache_1_io_mem_cmd_s2mPipe_payload_uncached; + dataCache_1_io_mem_cmd_s2mPipe_rData_address <= dataCache_1_io_mem_cmd_s2mPipe_payload_address; + dataCache_1_io_mem_cmd_s2mPipe_rData_data <= dataCache_1_io_mem_cmd_s2mPipe_payload_data; + dataCache_1_io_mem_cmd_s2mPipe_rData_mask <= dataCache_1_io_mem_cmd_s2mPipe_payload_mask; + dataCache_1_io_mem_cmd_s2mPipe_rData_size <= dataCache_1_io_mem_cmd_s2mPipe_payload_size; + dataCache_1_io_mem_cmd_s2mPipe_rData_last <= dataCache_1_io_mem_cmd_s2mPipe_payload_last; + end + HazardSimplePlugin_writeBackBuffer_payload_address <= HazardSimplePlugin_writeBackWrites_payload_address; + HazardSimplePlugin_writeBackBuffer_payload_data <= HazardSimplePlugin_writeBackWrites_payload_data; + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + 64'h0000000000000001); + if(writeBack_arbitration_isFiring) begin + CsrPlugin_minstret <= (CsrPlugin_minstret + 64'h0000000000000001); + end + if(_zz_when) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_CsrPlugin_exceptionPortCtrl_exceptionContext_code_1 ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(CsrPlugin_selfException_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= CsrPlugin_selfException_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= CsrPlugin_selfException_payload_badAddr; + end + if(BranchPlugin_branchExceptionPort_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + end + if(DBusCachedPlugin_exceptionBus_valid) begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + end + if(when_CsrPlugin_l946) begin + if(when_CsrPlugin_l952) begin + CsrPlugin_interrupt_code <= 4'b0111; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l952_1) begin + CsrPlugin_interrupt_code <= 4'b0011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + if(when_CsrPlugin_l952_2) begin + CsrPlugin_interrupt_code <= 4'b1011; + CsrPlugin_interrupt_targetPrivilege <= 2'b11; + end + end + if(when_CsrPlugin_l1019) begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= writeBack_PC; + if(CsrPlugin_hadException) begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + if(when_MulDivIterativePlugin_l126) begin + memory_DivPlugin_div_done <= 1'b1; + end + if(when_MulDivIterativePlugin_l126_1) begin + memory_DivPlugin_div_done <= 1'b0; + end + if(when_MulDivIterativePlugin_l128) begin + if(when_MulDivIterativePlugin_l132) begin + memory_DivPlugin_rs1[31 : 0] <= memory_DivPlugin_div_stage_0_outNumerator; + memory_DivPlugin_accumulator[31 : 0] <= memory_DivPlugin_div_stage_0_outRemainder; + if(when_MulDivIterativePlugin_l151) begin + memory_DivPlugin_div_result <= _zz_memory_DivPlugin_div_result_1[31:0]; + end + end + end + if(when_MulDivIterativePlugin_l162) begin + memory_DivPlugin_accumulator <= 65'h0; + memory_DivPlugin_rs1 <= ((_zz_memory_DivPlugin_rs1 ? (~ _zz_memory_DivPlugin_rs1_1) : _zz_memory_DivPlugin_rs1_1) + _zz_memory_DivPlugin_rs1_2); + memory_DivPlugin_rs2 <= ((_zz_memory_DivPlugin_rs2 ? (~ execute_RS2) : execute_RS2) + _zz_memory_DivPlugin_rs2_1); + memory_DivPlugin_div_needRevert <= ((_zz_memory_DivPlugin_rs1 ^ (_zz_memory_DivPlugin_rs2 && (! execute_INSTRUCTION[13]))) && (! (((execute_RS2 == 32'h0) && execute_IS_RS2_SIGNED) && (! execute_INSTRUCTION[13])))); + end + externalInterruptArray_regNext <= externalInterruptArray; + if(when_Pipeline_l124) begin + decode_to_execute_PC <= decode_PC; + end + if(when_Pipeline_l124_1) begin + execute_to_memory_PC <= _zz_execute_SRC2; + end + if(when_Pipeline_l124_2) begin + memory_to_writeBack_PC <= memory_PC; + end + if(when_Pipeline_l124_3) begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if(when_Pipeline_l124_4) begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if(when_Pipeline_l124_5) begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(when_Pipeline_l124_6) begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_decode_to_execute_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_7) begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_8) begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_memory_to_writeBack_FORMAL_PC_NEXT; + end + if(when_Pipeline_l124_9) begin + decode_to_execute_MEMORY_FORCE_CONSTISTENCY <= decode_MEMORY_FORCE_CONSTISTENCY; + end + if(when_Pipeline_l124_10) begin + decode_to_execute_SRC1_CTRL <= _zz_decode_to_execute_SRC1_CTRL; + end + if(when_Pipeline_l124_11) begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if(when_Pipeline_l124_12) begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if(when_Pipeline_l124_13) begin + execute_to_memory_MEMORY_ENABLE <= execute_MEMORY_ENABLE; + end + if(when_Pipeline_l124_14) begin + memory_to_writeBack_MEMORY_ENABLE <= memory_MEMORY_ENABLE; + end + if(when_Pipeline_l124_15) begin + decode_to_execute_ALU_CTRL <= _zz_decode_to_execute_ALU_CTRL; + end + if(when_Pipeline_l124_16) begin + decode_to_execute_SRC2_CTRL <= _zz_decode_to_execute_SRC2_CTRL; + end + if(when_Pipeline_l124_17) begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_18) begin + execute_to_memory_REGFILE_WRITE_VALID <= execute_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_19) begin + memory_to_writeBack_REGFILE_WRITE_VALID <= memory_REGFILE_WRITE_VALID; + end + if(when_Pipeline_l124_20) begin + decode_to_execute_BYPASSABLE_EXECUTE_STAGE <= decode_BYPASSABLE_EXECUTE_STAGE; + end + if(when_Pipeline_l124_21) begin + decode_to_execute_BYPASSABLE_MEMORY_STAGE <= decode_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_22) begin + execute_to_memory_BYPASSABLE_MEMORY_STAGE <= execute_BYPASSABLE_MEMORY_STAGE; + end + if(when_Pipeline_l124_23) begin + decode_to_execute_MEMORY_WR <= decode_MEMORY_WR; + end + if(when_Pipeline_l124_24) begin + execute_to_memory_MEMORY_WR <= execute_MEMORY_WR; + end + if(when_Pipeline_l124_25) begin + memory_to_writeBack_MEMORY_WR <= memory_MEMORY_WR; + end + if(when_Pipeline_l124_26) begin + decode_to_execute_MEMORY_MANAGMENT <= decode_MEMORY_MANAGMENT; + end + if(when_Pipeline_l124_27) begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if(when_Pipeline_l124_28) begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_decode_to_execute_ALU_BITWISE_CTRL; + end + if(when_Pipeline_l124_29) begin + decode_to_execute_SHIFT_CTRL <= _zz_decode_to_execute_SHIFT_CTRL; + end + if(when_Pipeline_l124_30) begin + execute_to_memory_SHIFT_CTRL <= _zz_execute_to_memory_SHIFT_CTRL; + end + if(when_Pipeline_l124_31) begin + decode_to_execute_BRANCH_CTRL <= _zz_decode_to_execute_BRANCH_CTRL; + end + if(when_Pipeline_l124_32) begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if(when_Pipeline_l124_33) begin + decode_to_execute_ENV_CTRL <= _zz_decode_to_execute_ENV_CTRL; + end + if(when_Pipeline_l124_34) begin + execute_to_memory_ENV_CTRL <= _zz_execute_to_memory_ENV_CTRL; + end + if(when_Pipeline_l124_35) begin + memory_to_writeBack_ENV_CTRL <= _zz_memory_to_writeBack_ENV_CTRL; + end + if(when_Pipeline_l124_36) begin + decode_to_execute_IS_MUL <= decode_IS_MUL; + end + if(when_Pipeline_l124_37) begin + execute_to_memory_IS_MUL <= execute_IS_MUL; + end + if(when_Pipeline_l124_38) begin + memory_to_writeBack_IS_MUL <= memory_IS_MUL; + end + if(when_Pipeline_l124_39) begin + decode_to_execute_IS_DIV <= decode_IS_DIV; + end + if(when_Pipeline_l124_40) begin + execute_to_memory_IS_DIV <= execute_IS_DIV; + end + if(when_Pipeline_l124_41) begin + decode_to_execute_IS_RS1_SIGNED <= decode_IS_RS1_SIGNED; + end + if(when_Pipeline_l124_42) begin + decode_to_execute_IS_RS2_SIGNED <= decode_IS_RS2_SIGNED; + end + if(when_Pipeline_l124_43) begin + decode_to_execute_RS1 <= decode_RS1; + end + if(when_Pipeline_l124_44) begin + decode_to_execute_RS2 <= decode_RS2; + end + if(when_Pipeline_l124_45) begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if(when_Pipeline_l124_46) begin + decode_to_execute_PREDICTION_HAD_BRANCHED2 <= decode_PREDICTION_HAD_BRANCHED2; + end + if(when_Pipeline_l124_47) begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + if(when_Pipeline_l124_48) begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if(when_Pipeline_l124_49) begin + execute_to_memory_MEMORY_STORE_DATA_RF <= execute_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_50) begin + memory_to_writeBack_MEMORY_STORE_DATA_RF <= memory_MEMORY_STORE_DATA_RF; + end + if(when_Pipeline_l124_51) begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_decode_RS2; + end + if(when_Pipeline_l124_52) begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_decode_RS2_1; + end + if(when_Pipeline_l124_53) begin + execute_to_memory_SHIFT_RIGHT <= execute_SHIFT_RIGHT; + end + if(when_Pipeline_l124_54) begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if(when_Pipeline_l124_55) begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if(when_Pipeline_l124_56) begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if(when_Pipeline_l124_57) begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if(when_Pipeline_l124_58) begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if(when_Pipeline_l124_59) begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if(when_Pipeline_l124_60) begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if(when_Pipeline_l124_61) begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if(when_CsrPlugin_l1264) begin + execute_CsrPlugin_csr_3264 <= (decode_INSTRUCTION[31 : 20] == 12'hcc0); + end + if(when_CsrPlugin_l1264_1) begin + execute_CsrPlugin_csr_3857 <= (decode_INSTRUCTION[31 : 20] == 12'hf11); + end + if(when_CsrPlugin_l1264_2) begin + execute_CsrPlugin_csr_3858 <= (decode_INSTRUCTION[31 : 20] == 12'hf12); + end + if(when_CsrPlugin_l1264_3) begin + execute_CsrPlugin_csr_3859 <= (decode_INSTRUCTION[31 : 20] == 12'hf13); + end + if(when_CsrPlugin_l1264_4) begin + execute_CsrPlugin_csr_3860 <= (decode_INSTRUCTION[31 : 20] == 12'hf14); + end + if(when_CsrPlugin_l1264_5) begin + execute_CsrPlugin_csr_769 <= (decode_INSTRUCTION[31 : 20] == 12'h301); + end + if(when_CsrPlugin_l1264_6) begin + execute_CsrPlugin_csr_768 <= (decode_INSTRUCTION[31 : 20] == 12'h300); + end + if(when_CsrPlugin_l1264_7) begin + execute_CsrPlugin_csr_836 <= (decode_INSTRUCTION[31 : 20] == 12'h344); + end + if(when_CsrPlugin_l1264_8) begin + execute_CsrPlugin_csr_772 <= (decode_INSTRUCTION[31 : 20] == 12'h304); + end + if(when_CsrPlugin_l1264_9) begin + execute_CsrPlugin_csr_773 <= (decode_INSTRUCTION[31 : 20] == 12'h305); + end + if(when_CsrPlugin_l1264_10) begin + execute_CsrPlugin_csr_833 <= (decode_INSTRUCTION[31 : 20] == 12'h341); + end + if(when_CsrPlugin_l1264_11) begin + execute_CsrPlugin_csr_832 <= (decode_INSTRUCTION[31 : 20] == 12'h340); + end + if(when_CsrPlugin_l1264_12) begin + execute_CsrPlugin_csr_834 <= (decode_INSTRUCTION[31 : 20] == 12'h342); + end + if(when_CsrPlugin_l1264_13) begin + execute_CsrPlugin_csr_835 <= (decode_INSTRUCTION[31 : 20] == 12'h343); + end + if(when_CsrPlugin_l1264_14) begin + execute_CsrPlugin_csr_2816 <= (decode_INSTRUCTION[31 : 20] == 12'hb00); + end + if(when_CsrPlugin_l1264_15) begin + execute_CsrPlugin_csr_2944 <= (decode_INSTRUCTION[31 : 20] == 12'hb80); + end + if(when_CsrPlugin_l1264_16) begin + execute_CsrPlugin_csr_2818 <= (decode_INSTRUCTION[31 : 20] == 12'hb02); + end + if(when_CsrPlugin_l1264_17) begin + execute_CsrPlugin_csr_2946 <= (decode_INSTRUCTION[31 : 20] == 12'hb82); + end + if(when_CsrPlugin_l1264_18) begin + execute_CsrPlugin_csr_3072 <= (decode_INSTRUCTION[31 : 20] == 12'hc00); + end + if(when_CsrPlugin_l1264_19) begin + execute_CsrPlugin_csr_3200 <= (decode_INSTRUCTION[31 : 20] == 12'hc80); + end + if(when_CsrPlugin_l1264_20) begin + execute_CsrPlugin_csr_3074 <= (decode_INSTRUCTION[31 : 20] == 12'hc02); + end + if(when_CsrPlugin_l1264_21) begin + execute_CsrPlugin_csr_3202 <= (decode_INSTRUCTION[31 : 20] == 12'hc82); + end + if(when_CsrPlugin_l1264_22) begin + execute_CsrPlugin_csr_3008 <= (decode_INSTRUCTION[31 : 20] == 12'hbc0); + end + if(when_CsrPlugin_l1264_23) begin + execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); + end + if(execute_CsrPlugin_csr_836) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; + end + end + if(execute_CsrPlugin_csr_773) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtvec_base <= CsrPlugin_csrMapping_writeDataSignal[31 : 2]; + CsrPlugin_mtvec_mode <= CsrPlugin_csrMapping_writeDataSignal[1 : 0]; + end + end + if(execute_CsrPlugin_csr_833) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mepc <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_832) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mscratch <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_834) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcause_interrupt <= CsrPlugin_csrMapping_writeDataSignal[31]; + CsrPlugin_mcause_exceptionCode <= CsrPlugin_csrMapping_writeDataSignal[3 : 0]; + end + end + if(execute_CsrPlugin_csr_835) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mtval <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2816) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2944) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_mcycle[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2818) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[31 : 0] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + if(execute_CsrPlugin_csr_2946) begin + if(execute_CsrPlugin_writeEnable) begin + CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; + end + end + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + output reg io_cpu_execute_haltIt, + input io_cpu_execute_args_wr, + input [1:0] io_cpu_execute_args_size, + input io_cpu_execute_args_totalyConsistent, + output io_cpu_execute_refilling, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + input [31:0] io_cpu_memory_mmuRsp_physicalAddress, + input io_cpu_memory_mmuRsp_isIoAccess, + input io_cpu_memory_mmuRsp_isPaging, + input io_cpu_memory_mmuRsp_allowRead, + input io_cpu_memory_mmuRsp_allowWrite, + input io_cpu_memory_mmuRsp_allowExecute, + input io_cpu_memory_mmuRsp_exception, + input io_cpu_memory_mmuRsp_refilling, + input io_cpu_memory_mmuRsp_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + input [31:0] io_cpu_writeBack_storeData, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output io_cpu_writeBack_keepMemRspData, + input io_cpu_writeBack_fence_SW, + input io_cpu_writeBack_fence_SR, + input io_cpu_writeBack_fence_SO, + input io_cpu_writeBack_fence_SI, + input io_cpu_writeBack_fence_PW, + input io_cpu_writeBack_fence_PR, + input io_cpu_writeBack_fence_PO, + input io_cpu_writeBack_fence_PI, + input [3:0] io_cpu_writeBack_fence_FM, + output io_cpu_writeBack_exclusiveOk, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output io_mem_cmd_payload_uncached, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_size, + output io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input io_mem_rsp_payload_last, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_ways_0_tags_port0; + reg [31:0] _zz_ways_0_data_port0; + wire [21:0] _zz_ways_0_tags_port; + wire [9:0] _zz_stage0_dataColisions; + wire [9:0] _zz__zz_stageA_dataColisions; + wire [0:0] _zz_when; + wire [2:0] _zz_loader_counter_valueNext; + wire [0:0] _zz_loader_counter_valueNext_1; + wire [1:0] _zz_loader_waysAllocator; + reg _zz_1; + reg _zz_2; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_valid; + wire ways_0_tagsReadRsp_error; + wire [19:0] ways_0_tagsReadRsp_address; + wire [21:0] _zz_ways_0_tagsReadRsp_valid_1; + wire _zz_ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRspMem; + wire [31:0] ways_0_dataReadRsp; + wire when_DataCache_l634; + wire when_DataCache_l637; + wire when_DataCache_l656; + wire rspSync; + wire rspLast; + reg memCmdSent; + wire io_mem_cmd_fire; + wire when_DataCache_l678; + reg [3:0] _zz_stage0_mask; + wire [3:0] stage0_mask; + wire [0:0] stage0_dataColisions; + wire [0:0] stage0_wayInvalidate; + wire stage0_isAmo; + wire when_DataCache_l763; + reg stageA_request_wr; + reg [1:0] stageA_request_size; + reg stageA_request_totalyConsistent; + wire when_DataCache_l763_1; + reg [3:0] stageA_mask; + wire stageA_isAmo; + wire stageA_isLrsc; + wire [0:0] stageA_wayHits; + wire when_DataCache_l763_2; + reg [0:0] stageA_wayInvalidate; + wire when_DataCache_l763_3; + reg [0:0] stage0_dataColisions_regNextWhen; + wire [0:0] _zz_stageA_dataColisions; + wire [0:0] stageA_dataColisions; + wire when_DataCache_l814; + reg stageB_request_wr; + reg [1:0] stageB_request_size; + reg stageB_request_totalyConsistent; + reg stageB_mmuRspFreeze; + wire when_DataCache_l816; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_isPaging; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_mmuRsp_bypassTranslation; + wire when_DataCache_l813; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + wire when_DataCache_l813_1; + reg [31:0] stageB_dataReadRsp_0; + wire when_DataCache_l812; + reg [0:0] stageB_wayInvalidate; + wire stageB_consistancyHazard; + wire when_DataCache_l812_1; + reg [0:0] stageB_dataColisions; + wire when_DataCache_l812_2; + reg stageB_unaligned; + wire when_DataCache_l812_3; + reg [0:0] stageB_waysHitsBeforeInvalidate; + wire [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + wire when_DataCache_l812_4; + reg [3:0] stageB_mask; + reg stageB_loaderValid; + wire [31:0] stageB_ioMemRspMuxed; + reg stageB_flusher_waitDone; + wire stageB_flusher_hold; + reg [7:0] stageB_flusher_counter; + wire when_DataCache_l842; + wire when_DataCache_l848; + reg stageB_flusher_start; + wire stageB_isAmo; + wire stageB_isAmoCached; + wire stageB_isExternalLsrc; + wire stageB_isExternalAmo; + wire [31:0] stageB_requestDataBypass; + reg stageB_cpuWriteToCache; + wire when_DataCache_l911; + wire stageB_badPermissions; + wire stageB_loadStoreFault; + wire stageB_bypassCache; + wire when_DataCache_l980; + wire when_DataCache_l989; + wire when_DataCache_l994; + wire when_DataCache_l1005; + wire when_DataCache_l1017; + wire when_DataCache_l976; + wire when_DataCache_l1051; + wire when_DataCache_l1060; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + wire loader_kill; + reg loader_killReg; + wire when_DataCache_l1075; + wire loader_done; + wire when_DataCache_l1103; + reg loader_valid_regNext; + wire when_DataCache_l1107; + wire when_DataCache_l1110; + (* ram_style = "block" *) reg [21:0] ways_0_tags [0:127]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol0 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol1 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol2 [0:1023]; + (* ram_style = "block" *) reg [7:0] ways_0_data_symbol3 [0:1023]; + reg [7:0] _zz_ways_0_datasymbol_read; + reg [7:0] _zz_ways_0_datasymbol_read_1; + reg [7:0] _zz_ways_0_datasymbol_read_2; + reg [7:0] _zz_ways_0_datasymbol_read_3; + + assign _zz_stage0_dataColisions = (io_cpu_execute_address[11 : 2] >>> 0); + assign _zz__zz_stageA_dataColisions = (io_cpu_memory_address[11 : 2] >>> 0); + assign _zz_when = 1'b1; + assign _zz_loader_counter_valueNext_1 = loader_counter_willIncrement; + assign _zz_loader_counter_valueNext = {2'd0, _zz_loader_counter_valueNext_1}; + assign _zz_loader_waysAllocator = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_ways_0_tags_port = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_ways_0_tagsReadRsp_valid) begin + _zz_ways_0_tags_port0 <= ways_0_tags[tagsReadCmd_payload]; + end + end + + always @(posedge clk) begin + if(_zz_2) begin + ways_0_tags[tagsWriteCmd_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(*) begin + _zz_ways_0_data_port0 = {_zz_ways_0_datasymbol_read_3, _zz_ways_0_datasymbol_read_2, _zz_ways_0_datasymbol_read_1, _zz_ways_0_datasymbol_read}; + end + always @(posedge clk) begin + if(_zz_ways_0_dataReadRspMem) begin + _zz_ways_0_datasymbol_read <= ways_0_data_symbol0[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_1 <= ways_0_data_symbol1[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_2 <= ways_0_data_symbol2[dataReadCmd_payload]; + _zz_ways_0_datasymbol_read_3 <= ways_0_data_symbol3[dataReadCmd_payload]; + end + end + + always @(posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1) begin + ways_0_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1) begin + ways_0_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1) begin + ways_0_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1) begin + ways_0_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(when_DataCache_l637) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(when_DataCache_l634) begin + _zz_2 = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_ways_0_tagsReadRsp_valid = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_ways_0_tagsReadRsp_valid_1 = _zz_ways_0_tags_port0; + assign ways_0_tagsReadRsp_valid = _zz_ways_0_tagsReadRsp_valid_1[0]; + assign ways_0_tagsReadRsp_error = _zz_ways_0_tagsReadRsp_valid_1[1]; + assign ways_0_tagsReadRsp_address = _zz_ways_0_tagsReadRsp_valid_1[21 : 2]; + assign _zz_ways_0_dataReadRspMem = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign ways_0_dataReadRspMem = _zz_ways_0_data_port0; + assign ways_0_dataReadRsp = ways_0_dataReadRspMem[31 : 0]; + assign when_DataCache_l634 = (tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]); + assign when_DataCache_l637 = (dataWriteCmd_valid && dataWriteCmd_payload_way[0]); + always @(*) begin + tagsReadCmd_valid = 1'b0; + if(when_DataCache_l656) begin + tagsReadCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsReadCmd_payload = 7'bxxxxxxx; + if(when_DataCache_l656) begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @(*) begin + dataReadCmd_valid = 1'b0; + if(when_DataCache_l656) begin + dataReadCmd_valid = 1'b1; + end + end + + always @(*) begin + dataReadCmd_payload = 10'bxxxxxxxxxx; + if(when_DataCache_l656) begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @(*) begin + tagsWriteCmd_valid = 1'b0; + if(when_DataCache_l842) begin + tagsWriteCmd_valid = 1'b1; + end + if(when_DataCache_l1051) begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + tagsWriteCmd_payload_way = 1'bx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_way = 1'b1; + end + if(loader_done) begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + tagsWriteCmd_payload_address = 7'bxxxxxxx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_address = stageB_flusher_counter[6:0]; + end + if(loader_done) begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @(*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(when_DataCache_l842) begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_done) begin + tagsWriteCmd_payload_data_valid = (! (loader_kill || loader_killReg)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_done) begin + tagsWriteCmd_payload_data_error = (loader_error || (io_mem_rsp_valid && io_mem_rsp_payload_error)); + end + end + + always @(*) begin + tagsWriteCmd_payload_data_address = 20'bxxxxxxxxxxxxxxxxxxxx; + if(loader_done) begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @(*) begin + dataWriteCmd_valid = 1'b0; + if(stageB_cpuWriteToCache) begin + if(when_DataCache_l911) begin + dataWriteCmd_valid = 1'b1; + end + end + if(when_DataCache_l1051) begin + dataWriteCmd_valid = 1'b0; + end + if(when_DataCache_l1075) begin + dataWriteCmd_valid = 1'b1; + end + end + + always @(*) begin + dataWriteCmd_payload_way = 1'bx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_way = stageB_waysHits; + end + if(when_DataCache_l1075) begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @(*) begin + dataWriteCmd_payload_address = 10'bxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + if(when_DataCache_l1075) begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @(*) begin + dataWriteCmd_payload_data = 32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_data[31 : 0] = stageB_requestDataBypass; + end + if(when_DataCache_l1075) begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @(*) begin + dataWriteCmd_payload_mask = 4'bxxxx; + if(stageB_cpuWriteToCache) begin + dataWriteCmd_payload_mask = 4'b0000; + if(_zz_when[0]) begin + dataWriteCmd_payload_mask[3 : 0] = stageB_mask; + end + end + if(when_DataCache_l1075) begin + dataWriteCmd_payload_mask = 4'b1111; + end + end + + assign when_DataCache_l656 = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + always @(*) begin + io_cpu_execute_haltIt = 1'b0; + if(when_DataCache_l842) begin + io_cpu_execute_haltIt = 1'b1; + end + end + + assign rspSync = 1'b1; + assign rspLast = 1'b1; + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign when_DataCache_l678 = (! io_cpu_writeBack_isStuck); + always @(*) begin + _zz_stage0_mask = 4'bxxxx; + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_stage0_mask = 4'b0001; + end + 2'b01 : begin + _zz_stage0_mask = 4'b0011; + end + 2'b10 : begin + _zz_stage0_mask = 4'b1111; + end + default : begin + end + endcase + end + + assign stage0_mask = (_zz_stage0_mask <<< io_cpu_execute_address[1 : 0]); + assign stage0_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz_stage0_dataColisions)) && ((stage0_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stage0_wayInvalidate = 1'b0; + assign stage0_isAmo = 1'b0; + assign when_DataCache_l763 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_1 = (! io_cpu_memory_isStuck); + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_isAmo = 1'b0; + assign stageA_isLrsc = 1'b0; + assign stageA_wayHits = ((io_cpu_memory_mmuRsp_physicalAddress[31 : 12] == ways_0_tagsReadRsp_address) && ways_0_tagsReadRsp_valid); + assign when_DataCache_l763_2 = (! io_cpu_memory_isStuck); + assign when_DataCache_l763_3 = (! io_cpu_memory_isStuck); + assign _zz_stageA_dataColisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == _zz__zz_stageA_dataColisions)) && ((stageA_mask & dataWriteCmd_payload_mask[3 : 0]) != 4'b0000)); + assign stageA_dataColisions = (stage0_dataColisions_regNextWhen | _zz_stageA_dataColisions); + assign when_DataCache_l814 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_mmuRspFreeze = 1'b0; + if(when_DataCache_l1110) begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign when_DataCache_l816 = ((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)); + assign when_DataCache_l813 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l813_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812 = (! io_cpu_writeBack_isStuck); + assign stageB_consistancyHazard = 1'b0; + assign when_DataCache_l812_1 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_2 = (! io_cpu_writeBack_isStuck); + assign when_DataCache_l812_3 = (! io_cpu_writeBack_isStuck); + assign stageB_waysHits = (stageB_waysHitsBeforeInvalidate & (~ stageB_wayInvalidate)); + assign stageB_waysHit = (stageB_waysHits != 1'b0); + assign stageB_dataMux = stageB_dataReadRsp_0; + assign when_DataCache_l812_4 = (! io_cpu_writeBack_isStuck); + always @(*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + if(io_mem_cmd_ready) begin + stageB_loaderValid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1051) begin + stageB_loaderValid = 1'b0; + end + end + + assign stageB_ioMemRspMuxed = io_mem_rsp_payload_data[31 : 0]; + always @(*) begin + io_cpu_writeBack_haltIt = 1'b1; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + if(when_DataCache_l980) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(when_DataCache_l989) begin + if(when_DataCache_l994) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + end + if(when_DataCache_l1051) begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + assign stageB_flusher_hold = 1'b0; + assign when_DataCache_l842 = (! stageB_flusher_counter[7]); + assign when_DataCache_l848 = (! stageB_flusher_hold); + assign io_cpu_flush_ready = (stageB_flusher_waitDone && stageB_flusher_counter[7]); + assign stageB_isAmo = 1'b0; + assign stageB_isAmoCached = 1'b0; + assign stageB_isExternalLsrc = 1'b0; + assign stageB_isExternalAmo = 1'b0; + assign stageB_requestDataBypass = io_cpu_writeBack_storeData; + always @(*) begin + stageB_cpuWriteToCache = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + stageB_cpuWriteToCache = 1'b1; + end + end + end + end + end + + assign when_DataCache_l911 = (stageB_request_wr && stageB_waysHit); + assign stageB_badPermissions = (((! stageB_mmuRsp_allowWrite) && stageB_request_wr) || ((! stageB_mmuRsp_allowRead) && ((! stageB_request_wr) || stageB_isAmo))); + assign stageB_loadStoreFault = (io_cpu_writeBack_isValid && (stageB_mmuRsp_exception || stageB_badPermissions)); + always @(*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(when_DataCache_l989) begin + if(when_DataCache_l1005) begin + io_cpu_redo = 1'b1; + end + end + end + end + end + if(when_DataCache_l1060) begin + io_cpu_redo = 1'b1; + end + if(when_DataCache_l1107) begin + io_cpu_redo = 1'b1; + end + end + + always @(*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_bypassCache) begin + io_cpu_writeBack_accessError = ((((! stageB_request_wr) && 1'b1) && io_mem_rsp_valid) && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = (((stageB_waysHits & stageB_tagsReadRsp_0_error) != 1'b0) || (stageB_loadStoreFault && (! stageB_mmuRsp_isPaging))); + end + end + + assign io_cpu_writeBack_mmuException = (stageB_loadStoreFault && stageB_mmuRsp_isPaging); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && stageB_unaligned); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + always @(*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(when_DataCache_l976) begin + io_mem_cmd_valid = (! memCmdSent); + end else begin + if(when_DataCache_l989) begin + if(stageB_request_wr) begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if(when_DataCache_l1017) begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + end + if(when_DataCache_l1051) begin + io_mem_cmd_valid = 1'b0; + end + end + + always @(*) begin + io_mem_cmd_payload_address = stageB_mmuRsp_physicalAddress; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_address[4 : 0] = 5'h0; + end + end + end + end + end + + assign io_mem_cmd_payload_last = 1'b1; + always @(*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + assign io_mem_cmd_payload_uncached = stageB_mmuRsp_isIoAccess; + always @(*) begin + io_mem_cmd_payload_size = {1'd0, stageB_request_size}; + if(io_cpu_writeBack_isValid) begin + if(!stageB_isExternalAmo) begin + if(!when_DataCache_l976) begin + if(!when_DataCache_l989) begin + io_mem_cmd_payload_size = 3'b101; + end + end + end + end + end + + assign stageB_bypassCache = ((stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc) || stageB_isExternalAmo); + assign io_cpu_writeBack_keepMemRspData = 1'b0; + assign when_DataCache_l980 = ((! stageB_request_wr) ? (io_mem_rsp_valid && rspSync) : io_mem_cmd_ready); + assign when_DataCache_l989 = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmoCached))); + assign when_DataCache_l994 = ((! stageB_request_wr) || io_mem_cmd_ready); + assign when_DataCache_l1005 = (((! stageB_request_wr) || stageB_isAmoCached) && ((stageB_dataColisions & stageB_waysHits) != 1'b0)); + assign when_DataCache_l1017 = (! memCmdSent); + assign when_DataCache_l976 = (stageB_mmuRsp_isIoAccess || stageB_isExternalLsrc); + always @(*) begin + if(stageB_bypassCache) begin + io_cpu_writeBack_data = stageB_ioMemRspMuxed; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign when_DataCache_l1051 = ((((stageB_consistancyHazard || stageB_mmuRsp_refilling) || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess); + assign when_DataCache_l1060 = (io_cpu_writeBack_isValid && (stageB_mmuRsp_refilling || stageB_consistancyHazard)); + always @(*) begin + loader_counter_willIncrement = 1'b0; + if(when_DataCache_l1075) begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == 3'b111); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @(*) begin + loader_counter_valueNext = (loader_counter_value + _zz_loader_counter_valueNext); + if(loader_counter_willClear) begin + loader_counter_valueNext = 3'b000; + end + end + + assign loader_kill = 1'b0; + assign when_DataCache_l1075 = ((loader_valid && io_mem_rsp_valid) && rspLast); + assign loader_done = loader_counter_willOverflow; + assign when_DataCache_l1103 = (! loader_valid); + assign when_DataCache_l1107 = (loader_valid && (! loader_valid_regNext)); + assign io_cpu_execute_refilling = loader_valid; + assign when_DataCache_l1110 = (stageB_loaderValid || loader_valid); + always @(posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if(when_DataCache_l763) begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_size <= io_cpu_execute_args_size; + stageA_request_totalyConsistent <= io_cpu_execute_args_totalyConsistent; + end + if(when_DataCache_l763_1) begin + stageA_mask <= stage0_mask; + end + if(when_DataCache_l763_2) begin + stageA_wayInvalidate <= stage0_wayInvalidate; + end + if(when_DataCache_l763_3) begin + stage0_dataColisions_regNextWhen <= stage0_dataColisions; + end + if(when_DataCache_l814) begin + stageB_request_wr <= stageA_request_wr; + stageB_request_size <= stageA_request_size; + stageB_request_totalyConsistent <= stageA_request_totalyConsistent; + end + if(when_DataCache_l816) begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuRsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuRsp_isIoAccess; + stageB_mmuRsp_isPaging <= io_cpu_memory_mmuRsp_isPaging; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuRsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuRsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuRsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuRsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuRsp_refilling; + stageB_mmuRsp_bypassTranslation <= io_cpu_memory_mmuRsp_bypassTranslation; + end + if(when_DataCache_l813) begin + stageB_tagsReadRsp_0_valid <= ways_0_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= ways_0_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= ways_0_tagsReadRsp_address; + end + if(when_DataCache_l813_1) begin + stageB_dataReadRsp_0 <= ways_0_dataReadRsp; + end + if(when_DataCache_l812) begin + stageB_wayInvalidate <= stageA_wayInvalidate; + end + if(when_DataCache_l812_1) begin + stageB_dataColisions <= stageA_dataColisions; + end + if(when_DataCache_l812_2) begin + stageB_unaligned <= ({((stageA_request_size == 2'b10) && (io_cpu_memory_address[1 : 0] != 2'b00)),((stageA_request_size == 2'b01) && (io_cpu_memory_address[0 : 0] != 1'b0))} != 2'b00); + end + if(when_DataCache_l812_3) begin + stageB_waysHitsBeforeInvalidate <= stageA_wayHits; + end + if(when_DataCache_l812_4) begin + stageB_mask <= stageA_mask; + end + loader_valid_regNext <= loader_valid; + end + + always @(posedge clk) begin + if(reset) begin + memCmdSent <= 1'b0; + stageB_flusher_waitDone <= 1'b0; + stageB_flusher_counter <= 8'h0; + stageB_flusher_start <= 1'b1; + loader_valid <= 1'b0; + loader_counter_value <= 3'b000; + loader_waysAllocator <= 1'b1; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end else begin + if(io_mem_cmd_fire) begin + memCmdSent <= 1'b1; + end + if(when_DataCache_l678) begin + memCmdSent <= 1'b0; + end + if(io_cpu_flush_ready) begin + stageB_flusher_waitDone <= 1'b0; + end + if(when_DataCache_l842) begin + if(when_DataCache_l848) begin + stageB_flusher_counter <= (stageB_flusher_counter + 8'h01); + end + end + stageB_flusher_start <= (((((((! stageB_flusher_waitDone) && (! stageB_flusher_start)) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start) begin + stageB_flusher_waitDone <= 1'b1; + stageB_flusher_counter <= 8'h0; + end + `ifndef SYNTHESIS + `ifdef FORMAL + assert((! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))); + `else + if(!(! ((io_cpu_writeBack_isValid && (! io_cpu_writeBack_haltIt)) && io_cpu_writeBack_isStuck))) begin + $display("ERROR writeBack stuck by another plugin is not allowed"); + end + `endif + `endif + if(stageB_loaderValid) begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(loader_kill) begin + loader_killReg <= 1'b1; + end + if(when_DataCache_l1075) begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_done) begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + loader_killReg <= 1'b0; + end + if(when_DataCache_l1103) begin + loader_waysAllocator <= _zz_loader_waysAllocator[0:0]; + end + end + end + + +endmodule + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input [31:0] io_cpu_fetch_mmuRsp_physicalAddress, + input io_cpu_fetch_mmuRsp_isIoAccess, + input io_cpu_fetch_mmuRsp_isPaging, + input io_cpu_fetch_mmuRsp_allowRead, + input io_cpu_fetch_mmuRsp_allowWrite, + input io_cpu_fetch_mmuRsp_allowExecute, + input io_cpu_fetch_mmuRsp_exception, + input io_cpu_fetch_mmuRsp_refilling, + input io_cpu_fetch_mmuRsp_bypassTranslation, + output [31:0] io_cpu_fetch_physicalAddress, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [31:0] _zz_banks_0_port1; + reg [22:0] _zz_ways_0_tags_port1; + wire [22:0] _zz_ways_0_tags_port; + reg _zz_1; + reg _zz_2; + reg lineLoader_fire; + reg lineLoader_valid; + (* keep , syn_keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [6:0] lineLoader_flushCounter; + wire when_InstructionCache_l338; + reg _zz_when_InstructionCache_l342; + wire when_InstructionCache_l342; + wire when_InstructionCache_l351; + reg lineLoader_cmdSent; + wire io_mem_cmd_fire; + wire when_Utils_l357; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* keep , syn_keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [5:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [20:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [8:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire when_InstructionCache_l401; + wire [8:0] _zz_fetchStage_read_banksValue_0_dataMem; + wire _zz_fetchStage_read_banksValue_0_dataMem_1; + wire [31:0] fetchStage_read_banksValue_0_dataMem; + wire [31:0] fetchStage_read_banksValue_0_data; + wire [5:0] _zz_fetchStage_read_waysValues_0_tag_valid; + wire _zz_fetchStage_read_waysValues_0_tag_valid_1; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [20:0] fetchStage_read_waysValues_0_tag_address; + wire [22:0] _zz_fetchStage_read_waysValues_0_tag_valid_2; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + wire when_InstructionCache_l435; + reg [31:0] io_cpu_fetch_data_regNextWhen; + wire when_InstructionCache_l459; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_isPaging; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_mmuRsp_bypassTranslation; + wire when_InstructionCache_l459_1; + reg decodeStage_hit_valid; + wire when_InstructionCache_l459_2; + reg decodeStage_hit_error; + (* ram_style = "block" *) reg [31:0] banks_0 [0:511]; + (* ram_style = "block" *) reg [22:0] ways_0_tags [0:63]; + + assign _zz_ways_0_tags_port = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @(posedge clk) begin + if(_zz_1) begin + banks_0[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @(posedge clk) begin + if(_zz_fetchStage_read_banksValue_0_dataMem_1) begin + _zz_banks_0_port1 <= banks_0[_zz_fetchStage_read_banksValue_0_dataMem]; + end + end + + always @(posedge clk) begin + if(_zz_2) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_ways_0_tags_port; + end + end + + always @(posedge clk) begin + if(_zz_fetchStage_read_waysValues_0_tag_valid_1) begin + _zz_ways_0_tags_port1 <= ways_0_tags[_zz_fetchStage_read_waysValues_0_tag_valid]; + end + end + + always @(*) begin + _zz_1 = 1'b0; + if(lineLoader_write_data_0_valid) begin + _zz_1 = 1'b1; + end + end + + always @(*) begin + _zz_2 = 1'b0; + if(lineLoader_write_tag_0_valid) begin + _zz_2 = 1'b1; + end + end + + always @(*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid) begin + if(when_InstructionCache_l401) begin + lineLoader_fire = 1'b1; + end + end + end + + always @(*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(when_InstructionCache_l338) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(when_InstructionCache_l342) begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush) begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign when_InstructionCache_l338 = (! lineLoader_flushCounter[6]); + assign when_InstructionCache_l342 = (! _zz_when_InstructionCache_l342); + assign when_InstructionCache_l351 = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign io_mem_cmd_fire = (io_mem_cmd_valid && io_mem_cmd_ready); + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = 3'b101; + assign when_Utils_l357 = (! lineLoader_valid); + always @(*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(when_Utils_l357) begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign lineLoader_write_tag_0_valid = ((1'b1 && lineLoader_fire) || (! lineLoader_flushCounter[6])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[6] ? lineLoader_address[10 : 5] : lineLoader_flushCounter[5 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[6]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 11]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && 1'b1); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[10 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign when_InstructionCache_l401 = (lineLoader_wordIndex == 3'b111); + assign _zz_fetchStage_read_banksValue_0_dataMem = io_cpu_prefetch_pc[10 : 2]; + assign _zz_fetchStage_read_banksValue_0_dataMem_1 = (! io_cpu_fetch_isStuck); + assign fetchStage_read_banksValue_0_dataMem = _zz_banks_0_port1; + assign fetchStage_read_banksValue_0_data = fetchStage_read_banksValue_0_dataMem[31 : 0]; + assign _zz_fetchStage_read_waysValues_0_tag_valid = io_cpu_prefetch_pc[10 : 5]; + assign _zz_fetchStage_read_waysValues_0_tag_valid_1 = (! io_cpu_fetch_isStuck); + assign _zz_fetchStage_read_waysValues_0_tag_valid_2 = _zz_ways_0_tags_port1; + assign fetchStage_read_waysValues_0_tag_valid = _zz_fetchStage_read_waysValues_0_tag_valid_2[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_fetchStage_read_waysValues_0_tag_valid_2[1]; + assign fetchStage_read_waysValues_0_tag_address = _zz_fetchStage_read_waysValues_0_tag_valid_2[22 : 2]; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuRsp_physicalAddress[31 : 11])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != 1'b0); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_banksValue_0_data; + assign fetchStage_hit_word = fetchStage_hit_data; + assign io_cpu_fetch_data = fetchStage_hit_word; + assign when_InstructionCache_l435 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_data = io_cpu_fetch_data_regNextWhen; + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuRsp_physicalAddress; + assign when_InstructionCache_l459 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_1 = (! io_cpu_decode_isStuck); + assign when_InstructionCache_l459_2 = (! io_cpu_decode_isStuck); + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = (decodeStage_hit_error || ((! decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = (((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_isPaging) && (decodeStage_mmuRsp_exception || (! decodeStage_mmuRsp_allowExecute))); + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @(posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= 3'b000; + end else begin + if(lineLoader_fire) begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire) begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid) begin + lineLoader_valid <= 1'b1; + end + if(io_flush) begin + lineLoader_flushPending <= 1'b1; + end + if(when_InstructionCache_l351) begin + lineLoader_flushPending <= 1'b0; + end + if(io_mem_cmd_fire) begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire) begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid) begin + lineLoader_wordIndex <= (lineLoader_wordIndex + 3'b001); + if(io_mem_rsp_payload_error) begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @(posedge clk) begin + if(io_cpu_fill_valid) begin + lineLoader_address <= io_cpu_fill_payload; + end + if(when_InstructionCache_l338) begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 7'h01); + end + _zz_when_InstructionCache_l342 <= lineLoader_flushCounter[6]; + if(when_InstructionCache_l351) begin + lineLoader_flushCounter <= 7'h0; + end + if(when_InstructionCache_l435) begin + io_cpu_fetch_data_regNextWhen <= io_cpu_fetch_data; + end + if(when_InstructionCache_l459) begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuRsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuRsp_isIoAccess; + decodeStage_mmuRsp_isPaging <= io_cpu_fetch_mmuRsp_isPaging; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuRsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuRsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuRsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuRsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuRsp_refilling; + decodeStage_mmuRsp_bypassTranslation <= io_cpu_fetch_mmuRsp_bypassTranslation; + end + if(when_InstructionCache_l459_1) begin + decodeStage_hit_valid <= fetchStage_hit_valid; + end + if(when_InstructionCache_l459_2) begin + decodeStage_hit_error <= fetchStage_hit_error; + end + end + + +endmodule diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.yaml b/pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.yaml new file mode 100644 index 0000000..b55f8e5 --- /dev/null +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.yaml @@ -0,0 +1,4 @@ +iBus: !!vexriscv.BusReport + flushInstructions: [4111, 19, 19, 19] + info: !!vexriscv.CacheReport {bytePerLine: 32, size: 2048} + kind: cached diff --git a/pythondata_cpu_vexriscv/verilog/genWrapper.py b/pythondata_cpu_vexriscv/verilog/genWrapper.py deleted file mode 100755 index 5d2d549..0000000 --- a/pythondata_cpu_vexriscv/verilog/genWrapper.py +++ /dev/null @@ -1,115 +0,0 @@ -#!/usr/bin/env python3 - -import sys -import re - - -args = sys.argv -vexfilename = args[1] - -vexv = open(vexfilename, 'r') -lines = vexv.readlines() - - -# record port info -pnames = list() -pdirs = dict() -ppins = dict() -started = False; -for line in lines: - if not started: - if re.match('module VexRiscv', line): - started = True - else: - parts = line.split() - n = len(parts) - if n <= 1: - break - - pdir = parts[0] - pname = parts[-1] - pname = pname.rstrip(',') - - if re.match("\);$", pname): - pname.rstrip(");") - started = False - - pnames.append(pname) - - assert pdir == "input" or pdir == "output" - pdirs[pname] = pdir - - ppins[pname] = "" - if n == 4: - assert parts[1] == "reg" - ppins[pname] = parts[2] - if n == 3: - if parts[1] != "reg": - ppins[pname] = parts[1] - - - -# -# Wrapper port declaration -# -print("//") -print("// wrapper auto-generated from {}".format(vexfilename)) -print("//") -print("") -print("module VexRiscv (") -for pname in pnames: - if not re.match("CfuPlugin_bus", pname): - comma = "," if (pname != pnames[-1]) else "" - print(" {:10} {:10} {}{}".format(pdirs[pname], ppins[pname], pname, comma)) -print(");\n\n") - - - - -# -# CFU bus signals -# -for pname in pnames: - if re.match("CfuPlugin_bus", pname): - print(" wire {:10} {};".format(ppins[pname], pname)) - last_cfu_port = pname - if pname == "clk" or pname == "reset": - last_cfu_port = pname -print("\n\n") - - - -# -# inner VexRiscv instantiation -# -print("VexRiscv_inner VexRiscv_inner(") -for pname in pnames: - comma = "," if (pname != pnames[-1]) else "" - print(" .{}({}){}".format(pname, pname, comma)) -print(");\n\n") - - -# -# inner CFU instantiation -# -print("Cfu Cfu(") -for pname in pnames: - if re.match("CfuPlugin_bus_|^clk$|^reset$", pname): - parts = pname.split("_"); - if parts[0] == "CfuPlugin": - parts[0] = "io" - if parts[0] == "reset": - parts[0] = "rst" - cfu_pname = "_".join(parts) - comma = "," if (pname != last_cfu_port) else "" - print(" .{}({}){}".format(cfu_pname, pname, comma)) -print(");\n\n") - - -# -# finish wrapper modules -# -print("endmodule") - - - From 6dfdf25a9c18331ff2b9db78dbace32210430c39 Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Wed, 29 Sep 2021 21:04:14 -0700 Subject: [PATCH 28/30] Rebuild VexRiscv_Slim.v so it has correct hash in comment. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.v index 0bb024f..69e997f 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_Slim.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 9f85993307e913719381223ade365fdc0b477d2e +// Git hash : 6f2afa7a1e6bd4ca7cdea67d2e078179c183b833 `define EnvCtrlEnum_binary_sequential_type [1:0] From 7454d1ac406f4e81ba8a81e164d3d67822e1b45b Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Thu, 30 Sep 2021 12:18:01 -0700 Subject: [PATCH 29/30] Remove performance CSRs from 'FullCfu' variants. Signed-off-by: Tim Callahan --- pythondata_cpu_vexriscv/verilog/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/Makefile b/pythondata_cpu_vexriscv/verilog/Makefile index 682a147..73dad30 100644 --- a/pythondata_cpu_vexriscv/verilog/Makefile +++ b/pythondata_cpu_vexriscv/verilog/Makefile @@ -39,10 +39,10 @@ VexRiscv_FullDebug.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --csrPluginConfig all -d --outputFile VexRiscv_FullDebug" VexRiscv_FullCfu.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfu" + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --outputFile VexRiscv_FullCfu" VexRiscv_FullCfuDebug.v: $(SRC) - sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --perfCSRs 8 --outputFile VexRiscv_FullCfuDebug" + sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all -d --cfu true --outputFile VexRiscv_FullCfuDebug" VexRiscv_PerfCfu.v: $(SRC) sbt compile "runMain vexriscv.GenCoreDefault --dCacheSize 8192 --iCacheSize 8192 --csrPluginConfig all --cfu true --perfCSRs 8 --outputFile VexRiscv_PerfCfu" From 9a22d43df1478d773ce3793f6326bd0ce9c549ab Mon Sep 17 00:00:00 2001 From: Tim Callahan Date: Thu, 30 Sep 2021 13:14:48 -0700 Subject: [PATCH 30/30] Rebuild VexRiscv_FullCfu*.v at 7454d1ac. Signed-off-by: Tim Callahan --- .../verilog/VexRiscv_FullCfu.v | 496 +++--------------- .../verilog/VexRiscv_FullCfuDebug.v | 496 +++--------------- 2 files changed, 136 insertions(+), 856 deletions(-) diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v index 11834d9..c722c42 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a +// Git hash : 7454d1ac406f4e81ba8a81e164d3d67822e1b45b `define Input2Kind_binary_sequential_type [0:0] @@ -421,7 +421,7 @@ module VexRiscv ( wire [31:0] _zz_memory_DivPlugin_rs2_1; wire [0:0] _zz_memory_DivPlugin_rs2_2; wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; - wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_41; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire writeBack_CfuPlugin_CFU_IN_FLIGHT; @@ -1159,30 +1159,6 @@ module VexRiscv ( reg CfuPlugin_bus_rsp_rValid; reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; wire when_CfuPlugin_l208; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; - reg [31:0] _zz_when_GenCoreDefault_l367; - wire when_GenCoreDefault_l367; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; - reg [31:0] _zz_when_GenCoreDefault_l367_1; - wire when_GenCoreDefault_l367_1; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; - reg [31:0] _zz_when_GenCoreDefault_l367_2; - wire when_GenCoreDefault_l367_2; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; - reg [31:0] _zz_when_GenCoreDefault_l367_3; - wire when_GenCoreDefault_l367_3; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; - reg [31:0] _zz_when_GenCoreDefault_l367_4; - wire when_GenCoreDefault_l367_4; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; - reg [31:0] _zz_when_GenCoreDefault_l367_5; - wire when_GenCoreDefault_l367_5; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; - reg [31:0] _zz_when_GenCoreDefault_l367_6; - wire when_GenCoreDefault_l367_6; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; - reg [31:0] _zz_when_GenCoreDefault_l367_7; - wire when_GenCoreDefault_l367_7; wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; wire when_Pipeline_l124_1; @@ -1365,38 +1341,14 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3008; wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_4032; - wire when_CsrPlugin_l1264_24; - reg execute_CsrPlugin_csr_2820; - wire when_CsrPlugin_l1264_25; - reg execute_CsrPlugin_csr_2821; - wire when_CsrPlugin_l1264_26; - reg execute_CsrPlugin_csr_2822; - wire when_CsrPlugin_l1264_27; - reg execute_CsrPlugin_csr_2823; - wire when_CsrPlugin_l1264_28; - reg execute_CsrPlugin_csr_2824; - wire when_CsrPlugin_l1264_29; - reg execute_CsrPlugin_csr_2825; - wire when_CsrPlugin_l1264_30; - reg execute_CsrPlugin_csr_2826; - wire when_CsrPlugin_l1264_31; - reg execute_CsrPlugin_csr_2827; - wire when_CsrPlugin_l1264_32; - reg execute_CsrPlugin_csr_2828; - wire when_CsrPlugin_l1264_33; - reg execute_CsrPlugin_csr_2829; - wire when_CsrPlugin_l1264_34; - reg execute_CsrPlugin_csr_2830; - wire when_CsrPlugin_l1264_35; - reg execute_CsrPlugin_csr_2831; - wire when_CsrPlugin_l1264_36; - reg execute_CsrPlugin_csr_2832; - wire when_CsrPlugin_l1264_37; - reg execute_CsrPlugin_csr_2833; - wire when_CsrPlugin_l1264_38; - reg execute_CsrPlugin_csr_2834; - wire when_CsrPlugin_l1264_39; - reg execute_CsrPlugin_csr_2835; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; @@ -1412,22 +1364,6 @@ module VexRiscv ( reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_29; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_30; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_31; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_32; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_33; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_34; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_35; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_36; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_37; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_38; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_39; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_40; wire when_CsrPlugin_l1297; wire when_CsrPlugin_l1302; reg [2:0] _zz_iBusWishbone_ADR; @@ -1801,7 +1737,7 @@ module VexRiscv ( assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; - assign _zz_CsrPlugin_csrMapping_readDataInit_41 = 32'h0; + assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; always @(posedge clk) begin if(_zz_decode_RegFilePlugin_rs1Data) begin _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; @@ -4543,70 +4479,6 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2821) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2822) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2823) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2824) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2825) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2826) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2827) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2828) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2829) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2830) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2831) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2832) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2833) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2834) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2835) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end if(CsrPlugin_csrMapping_allowCsrSignal) begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -4844,14 +4716,6 @@ module VexRiscv ( end assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); - assign when_GenCoreDefault_l367 = _zz_when_GenCoreDefault_l367[0]; - assign when_GenCoreDefault_l367_1 = _zz_when_GenCoreDefault_l367_1[0]; - assign when_GenCoreDefault_l367_2 = _zz_when_GenCoreDefault_l367_2[0]; - assign when_GenCoreDefault_l367_3 = _zz_when_GenCoreDefault_l367_3[0]; - assign when_GenCoreDefault_l367_4 = _zz_when_GenCoreDefault_l367_4[0]; - assign when_GenCoreDefault_l367_5 = _zz_when_GenCoreDefault_l367_5[0]; - assign when_GenCoreDefault_l367_6 = _zz_when_GenCoreDefault_l367_6[0]; - assign when_GenCoreDefault_l367_7 = _zz_when_GenCoreDefault_l367_7[0]; assign when_Pipeline_l124 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); @@ -4996,250 +4860,178 @@ module VexRiscv ( assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_28 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_29 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_30 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_31 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_32 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_33 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_34 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_35 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_36 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_37 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_38 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_39 = (! execute_arbitration_isStuck); always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; if(execute_CsrPlugin_csr_3264) begin - _zz_CsrPlugin_csrMapping_readDataInit_10[13 : 0] = 14'h2000; - _zz_CsrPlugin_csrMapping_readDataInit_10[25 : 20] = 6'h20; + _zz_CsrPlugin_csrMapping_readDataInit_2[13 : 0] = 14'h2000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; if(execute_CsrPlugin_csr_3857) begin - _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 0] = 4'b1011; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; if(execute_CsrPlugin_csr_3858) begin - _zz_CsrPlugin_csrMapping_readDataInit_12[4 : 0] = 5'h16; + _zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; if(execute_CsrPlugin_csr_3859) begin - _zz_CsrPlugin_csrMapping_readDataInit_13[5 : 0] = 6'h21; + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; if(execute_CsrPlugin_csr_769) begin - _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 30] = CsrPlugin_misa_base; - _zz_CsrPlugin_csrMapping_readDataInit_14[25 : 0] = CsrPlugin_misa_extensions; + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; if(execute_CsrPlugin_csr_768) begin - _zz_CsrPlugin_csrMapping_readDataInit_15[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_CsrPlugin_csrMapping_readDataInit_15[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; if(execute_CsrPlugin_csr_836) begin - _zz_CsrPlugin_csrMapping_readDataInit_16[11 : 11] = CsrPlugin_mip_MEIP; - _zz_CsrPlugin_csrMapping_readDataInit_16[7 : 7] = CsrPlugin_mip_MTIP; - _zz_CsrPlugin_csrMapping_readDataInit_16[3 : 3] = CsrPlugin_mip_MSIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; if(execute_CsrPlugin_csr_772) begin - _zz_CsrPlugin_csrMapping_readDataInit_17[11 : 11] = CsrPlugin_mie_MEIE; - _zz_CsrPlugin_csrMapping_readDataInit_17[7 : 7] = CsrPlugin_mie_MTIE; - _zz_CsrPlugin_csrMapping_readDataInit_17[3 : 3] = CsrPlugin_mie_MSIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; if(execute_CsrPlugin_csr_773) begin - _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 2] = CsrPlugin_mtvec_base; - _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 0] = CsrPlugin_mtvec_mode; + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; if(execute_CsrPlugin_csr_833) begin - _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mepc; + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; if(execute_CsrPlugin_csr_832) begin - _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mscratch; + _zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; if(execute_CsrPlugin_csr_834) begin - _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_CsrPlugin_csrMapping_readDataInit_21[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; if(execute_CsrPlugin_csr_835) begin - _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_mtval; + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; if(execute_CsrPlugin_csr_2816) begin - _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; if(execute_CsrPlugin_csr_2944) begin - _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; if(execute_CsrPlugin_csr_2818) begin - _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; if(execute_CsrPlugin_csr_2946) begin - _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; if(execute_CsrPlugin_csr_3072) begin - _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; if(execute_CsrPlugin_csr_3200) begin - _zz_CsrPlugin_csrMapping_readDataInit_28[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_29 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; if(execute_CsrPlugin_csr_3074) begin - _zz_CsrPlugin_csrMapping_readDataInit_29[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_30 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; if(execute_CsrPlugin_csr_3202) begin - _zz_CsrPlugin_csrMapping_readDataInit_30[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_31 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; if(execute_CsrPlugin_csr_3008) begin - _zz_CsrPlugin_csrMapping_readDataInit_31[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_32 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; if(execute_CsrPlugin_csr_4032) begin - _zz_CsrPlugin_csrMapping_readDataInit_32[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_33 = 32'h0; - if(execute_CsrPlugin_csr_2820) begin - _zz_CsrPlugin_csrMapping_readDataInit_33[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_34 = 32'h0; - if(execute_CsrPlugin_csr_2822) begin - _zz_CsrPlugin_csrMapping_readDataInit_34[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_35 = 32'h0; - if(execute_CsrPlugin_csr_2824) begin - _zz_CsrPlugin_csrMapping_readDataInit_35[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_4; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_36 = 32'h0; - if(execute_CsrPlugin_csr_2826) begin - _zz_CsrPlugin_csrMapping_readDataInit_36[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_5; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_37 = 32'h0; - if(execute_CsrPlugin_csr_2828) begin - _zz_CsrPlugin_csrMapping_readDataInit_37[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_6; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_38 = 32'h0; - if(execute_CsrPlugin_csr_2830) begin - _zz_CsrPlugin_csrMapping_readDataInit_38[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_7; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_39 = 32'h0; - if(execute_CsrPlugin_csr_2832) begin - _zz_CsrPlugin_csrMapping_readDataInit_39[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_8; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_40 = 32'h0; - if(execute_CsrPlugin_csr_2834) begin - _zz_CsrPlugin_csrMapping_readDataInit_40[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_9; + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | (_zz_CsrPlugin_csrMapping_readDataInit_12 | _zz_CsrPlugin_csrMapping_readDataInit_13)) | ((_zz_CsrPlugin_csrMapping_readDataInit_41 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26) | (_zz_CsrPlugin_csrMapping_readDataInit_27 | _zz_CsrPlugin_csrMapping_readDataInit_28)) | ((_zz_CsrPlugin_csrMapping_readDataInit_29 | _zz_CsrPlugin_csrMapping_readDataInit_30) | (_zz_CsrPlugin_csrMapping_readDataInit_31 | _zz_CsrPlugin_csrMapping_readDataInit_32))) | (((_zz_CsrPlugin_csrMapping_readDataInit_33 | _zz_CsrPlugin_csrMapping_readDataInit_34) | (_zz_CsrPlugin_csrMapping_readDataInit_35 | _zz_CsrPlugin_csrMapping_readDataInit_36)) | ((_zz_CsrPlugin_csrMapping_readDataInit_37 | _zz_CsrPlugin_csrMapping_readDataInit_38) | (_zz_CsrPlugin_csrMapping_readDataInit_39 | _zz_CsrPlugin_csrMapping_readDataInit_40))))); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))); assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; @@ -5687,30 +5479,6 @@ module VexRiscv ( if(CfuPlugin_bus_rsp_ready) begin CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end - if(when_GenCoreDefault_l367) begin - _zz_CsrPlugin_csrMapping_readDataInit_2 <= (_zz_CsrPlugin_csrMapping_readDataInit_2 + 32'h00000001); - end - if(when_GenCoreDefault_l367_1) begin - _zz_CsrPlugin_csrMapping_readDataInit_3 <= (_zz_CsrPlugin_csrMapping_readDataInit_3 + 32'h00000001); - end - if(when_GenCoreDefault_l367_2) begin - _zz_CsrPlugin_csrMapping_readDataInit_4 <= (_zz_CsrPlugin_csrMapping_readDataInit_4 + 32'h00000001); - end - if(when_GenCoreDefault_l367_3) begin - _zz_CsrPlugin_csrMapping_readDataInit_5 <= (_zz_CsrPlugin_csrMapping_readDataInit_5 + 32'h00000001); - end - if(when_GenCoreDefault_l367_4) begin - _zz_CsrPlugin_csrMapping_readDataInit_6 <= (_zz_CsrPlugin_csrMapping_readDataInit_6 + 32'h00000001); - end - if(when_GenCoreDefault_l367_5) begin - _zz_CsrPlugin_csrMapping_readDataInit_7 <= (_zz_CsrPlugin_csrMapping_readDataInit_7 + 32'h00000001); - end - if(when_GenCoreDefault_l367_6) begin - _zz_CsrPlugin_csrMapping_readDataInit_8 <= (_zz_CsrPlugin_csrMapping_readDataInit_8 + 32'h00000001); - end - if(when_GenCoreDefault_l367_7) begin - _zz_CsrPlugin_csrMapping_readDataInit_9 <= (_zz_CsrPlugin_csrMapping_readDataInit_9 + 32'h00000001); - end if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end @@ -5972,54 +5740,6 @@ module VexRiscv ( if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(when_CsrPlugin_l1264_24) begin - execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); - end - if(when_CsrPlugin_l1264_25) begin - execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); - end - if(when_CsrPlugin_l1264_26) begin - execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); - end - if(when_CsrPlugin_l1264_27) begin - execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); - end - if(when_CsrPlugin_l1264_28) begin - execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); - end - if(when_CsrPlugin_l1264_29) begin - execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); - end - if(when_CsrPlugin_l1264_30) begin - execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); - end - if(when_CsrPlugin_l1264_31) begin - execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); - end - if(when_CsrPlugin_l1264_32) begin - execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); - end - if(when_CsrPlugin_l1264_33) begin - execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); - end - if(when_CsrPlugin_l1264_34) begin - execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); - end - if(when_CsrPlugin_l1264_35) begin - execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); - end - if(when_CsrPlugin_l1264_36) begin - execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); - end - if(when_CsrPlugin_l1264_37) begin - execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); - end - if(when_CsrPlugin_l1264_38) begin - execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); - end - if(when_CsrPlugin_l1264_39) begin - execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); - end if(execute_CsrPlugin_csr_836) begin if(execute_CsrPlugin_writeEnable) begin CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; @@ -6072,86 +5792,6 @@ module VexRiscv ( CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2820) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2821) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2822) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2823) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_1 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2824) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2825) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2826) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2827) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2828) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2829) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2830) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2831) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2832) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_8 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2833) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2834) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_9 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2835) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end diff --git a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v index 5a78830..adc7fff 100644 --- a/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v +++ b/pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v @@ -1,6 +1,6 @@ // Generator : SpinalHDL v1.6.0 git head : 73c8d8e2b86b45646e9d0b2e729291f2b65e6be3 // Component : VexRiscv -// Git hash : 593e180abf5ba39e7fa33d4f371646453f84496a +// Git hash : 7454d1ac406f4e81ba8a81e164d3d67822e1b45b `define Input2Kind_binary_sequential_type [0:0] @@ -431,7 +431,7 @@ module VexRiscv ( wire [31:0] _zz_memory_DivPlugin_rs2_1; wire [0:0] _zz_memory_DivPlugin_rs2_2; wire [9:0] _zz_execute_CfuPlugin_functionsIds_0; - wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_41; + wire [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; wire [26:0] _zz_iBusWishbone_ADR_1; wire [51:0] memory_MUL_LOW; wire writeBack_CfuPlugin_CFU_IN_FLIGHT; @@ -1205,30 +1205,6 @@ module VexRiscv ( reg CfuPlugin_bus_rsp_rValid; reg [31:0] CfuPlugin_bus_rsp_rData_outputs_0; wire when_CfuPlugin_l208; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; - reg [31:0] _zz_when_GenCoreDefault_l367; - wire when_GenCoreDefault_l367; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; - reg [31:0] _zz_when_GenCoreDefault_l367_1; - wire when_GenCoreDefault_l367_1; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; - reg [31:0] _zz_when_GenCoreDefault_l367_2; - wire when_GenCoreDefault_l367_2; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; - reg [31:0] _zz_when_GenCoreDefault_l367_3; - wire when_GenCoreDefault_l367_3; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; - reg [31:0] _zz_when_GenCoreDefault_l367_4; - wire when_GenCoreDefault_l367_4; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; - reg [31:0] _zz_when_GenCoreDefault_l367_5; - wire when_GenCoreDefault_l367_5; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; - reg [31:0] _zz_when_GenCoreDefault_l367_6; - wire when_GenCoreDefault_l367_6; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; - reg [31:0] _zz_when_GenCoreDefault_l367_7; - wire when_GenCoreDefault_l367_7; wire when_Pipeline_l124; reg [31:0] decode_to_execute_PC; wire when_Pipeline_l124_1; @@ -1415,38 +1391,14 @@ module VexRiscv ( reg execute_CsrPlugin_csr_3008; wire when_CsrPlugin_l1264_23; reg execute_CsrPlugin_csr_4032; - wire when_CsrPlugin_l1264_24; - reg execute_CsrPlugin_csr_2820; - wire when_CsrPlugin_l1264_25; - reg execute_CsrPlugin_csr_2821; - wire when_CsrPlugin_l1264_26; - reg execute_CsrPlugin_csr_2822; - wire when_CsrPlugin_l1264_27; - reg execute_CsrPlugin_csr_2823; - wire when_CsrPlugin_l1264_28; - reg execute_CsrPlugin_csr_2824; - wire when_CsrPlugin_l1264_29; - reg execute_CsrPlugin_csr_2825; - wire when_CsrPlugin_l1264_30; - reg execute_CsrPlugin_csr_2826; - wire when_CsrPlugin_l1264_31; - reg execute_CsrPlugin_csr_2827; - wire when_CsrPlugin_l1264_32; - reg execute_CsrPlugin_csr_2828; - wire when_CsrPlugin_l1264_33; - reg execute_CsrPlugin_csr_2829; - wire when_CsrPlugin_l1264_34; - reg execute_CsrPlugin_csr_2830; - wire when_CsrPlugin_l1264_35; - reg execute_CsrPlugin_csr_2831; - wire when_CsrPlugin_l1264_36; - reg execute_CsrPlugin_csr_2832; - wire when_CsrPlugin_l1264_37; - reg execute_CsrPlugin_csr_2833; - wire when_CsrPlugin_l1264_38; - reg execute_CsrPlugin_csr_2834; - wire when_CsrPlugin_l1264_39; - reg execute_CsrPlugin_csr_2835; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_2; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_3; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_4; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_5; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_6; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_7; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_8; + reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_9; reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_10; reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_11; reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_12; @@ -1462,22 +1414,6 @@ module VexRiscv ( reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_22; reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_23; reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_24; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_25; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_26; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_27; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_28; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_29; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_30; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_31; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_32; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_33; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_34; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_35; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_36; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_37; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_38; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_39; - reg [31:0] _zz_CsrPlugin_csrMapping_readDataInit_40; wire when_CsrPlugin_l1297; wire when_CsrPlugin_l1302; reg [2:0] _zz_iBusWishbone_ADR; @@ -1853,7 +1789,7 @@ module VexRiscv ( assign _zz_execute_BranchPlugin_branch_src2_6 = execute_INSTRUCTION[31]; assign _zz_execute_BranchPlugin_branch_src2_7 = execute_INSTRUCTION[31]; assign _zz_execute_BranchPlugin_branch_src2_8 = execute_INSTRUCTION[7]; - assign _zz_CsrPlugin_csrMapping_readDataInit_41 = 32'h0; + assign _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; always @(posedge clk) begin if(_zz_decode_RegFilePlugin_rs1Data) begin _zz_RegFilePlugin_regFile_port0 <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; @@ -4684,70 +4620,6 @@ module VexRiscv ( execute_CsrPlugin_illegalAccess = 1'b0; end end - if(execute_CsrPlugin_csr_2820) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2821) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2822) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2823) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2824) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2825) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2826) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2827) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2828) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2829) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2830) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2831) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2832) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2833) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end - if(execute_CsrPlugin_csr_2834) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - if(execute_CsrPlugin_csr_2835) begin - if(execute_CSR_WRITE_OPCODE) begin - execute_CsrPlugin_illegalAccess = 1'b0; - end - end if(CsrPlugin_csrMapping_allowCsrSignal) begin execute_CsrPlugin_illegalAccess = 1'b0; end @@ -5044,14 +4916,6 @@ module VexRiscv ( end assign when_CfuPlugin_l208 = (! CfuPlugin_bus_rsp_rsp_valid); - assign when_GenCoreDefault_l367 = _zz_when_GenCoreDefault_l367[0]; - assign when_GenCoreDefault_l367_1 = _zz_when_GenCoreDefault_l367_1[0]; - assign when_GenCoreDefault_l367_2 = _zz_when_GenCoreDefault_l367_2[0]; - assign when_GenCoreDefault_l367_3 = _zz_when_GenCoreDefault_l367_3[0]; - assign when_GenCoreDefault_l367_4 = _zz_when_GenCoreDefault_l367_4[0]; - assign when_GenCoreDefault_l367_5 = _zz_when_GenCoreDefault_l367_5[0]; - assign when_GenCoreDefault_l367_6 = _zz_when_GenCoreDefault_l367_6[0]; - assign when_GenCoreDefault_l367_7 = _zz_when_GenCoreDefault_l367_7[0]; assign when_Pipeline_l124 = (! execute_arbitration_isStuck); assign when_Pipeline_l124_1 = (! memory_arbitration_isStuck); assign when_Pipeline_l124_2 = ((! writeBack_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack)); @@ -5209,250 +5073,178 @@ module VexRiscv ( assign when_CsrPlugin_l1264_21 = (! execute_arbitration_isStuck); assign when_CsrPlugin_l1264_22 = (! execute_arbitration_isStuck); assign when_CsrPlugin_l1264_23 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_24 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_25 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_26 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_27 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_28 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_29 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_30 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_31 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_32 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_33 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_34 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_35 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_36 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_37 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_38 = (! execute_arbitration_isStuck); - assign when_CsrPlugin_l1264_39 = (! execute_arbitration_isStuck); always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_2 = 32'h0; if(execute_CsrPlugin_csr_3264) begin - _zz_CsrPlugin_csrMapping_readDataInit_10[13 : 0] = 14'h2000; - _zz_CsrPlugin_csrMapping_readDataInit_10[25 : 20] = 6'h20; + _zz_CsrPlugin_csrMapping_readDataInit_2[13 : 0] = 14'h2000; + _zz_CsrPlugin_csrMapping_readDataInit_2[25 : 20] = 6'h20; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_3 = 32'h0; if(execute_CsrPlugin_csr_3857) begin - _zz_CsrPlugin_csrMapping_readDataInit_11[3 : 0] = 4'b1011; + _zz_CsrPlugin_csrMapping_readDataInit_3[3 : 0] = 4'b1011; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_4 = 32'h0; if(execute_CsrPlugin_csr_3858) begin - _zz_CsrPlugin_csrMapping_readDataInit_12[4 : 0] = 5'h16; + _zz_CsrPlugin_csrMapping_readDataInit_4[4 : 0] = 5'h16; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_5 = 32'h0; if(execute_CsrPlugin_csr_3859) begin - _zz_CsrPlugin_csrMapping_readDataInit_13[5 : 0] = 6'h21; + _zz_CsrPlugin_csrMapping_readDataInit_5[5 : 0] = 6'h21; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_6 = 32'h0; if(execute_CsrPlugin_csr_769) begin - _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 30] = CsrPlugin_misa_base; - _zz_CsrPlugin_csrMapping_readDataInit_14[25 : 0] = CsrPlugin_misa_extensions; + _zz_CsrPlugin_csrMapping_readDataInit_6[31 : 30] = CsrPlugin_misa_base; + _zz_CsrPlugin_csrMapping_readDataInit_6[25 : 0] = CsrPlugin_misa_extensions; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_7 = 32'h0; if(execute_CsrPlugin_csr_768) begin - _zz_CsrPlugin_csrMapping_readDataInit_15[12 : 11] = CsrPlugin_mstatus_MPP; - _zz_CsrPlugin_csrMapping_readDataInit_15[7 : 7] = CsrPlugin_mstatus_MPIE; - _zz_CsrPlugin_csrMapping_readDataInit_15[3 : 3] = CsrPlugin_mstatus_MIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[12 : 11] = CsrPlugin_mstatus_MPP; + _zz_CsrPlugin_csrMapping_readDataInit_7[7 : 7] = CsrPlugin_mstatus_MPIE; + _zz_CsrPlugin_csrMapping_readDataInit_7[3 : 3] = CsrPlugin_mstatus_MIE; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_8 = 32'h0; if(execute_CsrPlugin_csr_836) begin - _zz_CsrPlugin_csrMapping_readDataInit_16[11 : 11] = CsrPlugin_mip_MEIP; - _zz_CsrPlugin_csrMapping_readDataInit_16[7 : 7] = CsrPlugin_mip_MTIP; - _zz_CsrPlugin_csrMapping_readDataInit_16[3 : 3] = CsrPlugin_mip_MSIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[11 : 11] = CsrPlugin_mip_MEIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[7 : 7] = CsrPlugin_mip_MTIP; + _zz_CsrPlugin_csrMapping_readDataInit_8[3 : 3] = CsrPlugin_mip_MSIP; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_9 = 32'h0; if(execute_CsrPlugin_csr_772) begin - _zz_CsrPlugin_csrMapping_readDataInit_17[11 : 11] = CsrPlugin_mie_MEIE; - _zz_CsrPlugin_csrMapping_readDataInit_17[7 : 7] = CsrPlugin_mie_MTIE; - _zz_CsrPlugin_csrMapping_readDataInit_17[3 : 3] = CsrPlugin_mie_MSIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[11 : 11] = CsrPlugin_mie_MEIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[7 : 7] = CsrPlugin_mie_MTIE; + _zz_CsrPlugin_csrMapping_readDataInit_9[3 : 3] = CsrPlugin_mie_MSIE; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_10 = 32'h0; if(execute_CsrPlugin_csr_773) begin - _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 2] = CsrPlugin_mtvec_base; - _zz_CsrPlugin_csrMapping_readDataInit_18[1 : 0] = CsrPlugin_mtvec_mode; + _zz_CsrPlugin_csrMapping_readDataInit_10[31 : 2] = CsrPlugin_mtvec_base; + _zz_CsrPlugin_csrMapping_readDataInit_10[1 : 0] = CsrPlugin_mtvec_mode; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_11 = 32'h0; if(execute_CsrPlugin_csr_833) begin - _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mepc; + _zz_CsrPlugin_csrMapping_readDataInit_11[31 : 0] = CsrPlugin_mepc; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_12 = 32'h0; if(execute_CsrPlugin_csr_832) begin - _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mscratch; + _zz_CsrPlugin_csrMapping_readDataInit_12[31 : 0] = CsrPlugin_mscratch; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_13 = 32'h0; if(execute_CsrPlugin_csr_834) begin - _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 31] = CsrPlugin_mcause_interrupt; - _zz_CsrPlugin_csrMapping_readDataInit_21[3 : 0] = CsrPlugin_mcause_exceptionCode; + _zz_CsrPlugin_csrMapping_readDataInit_13[31 : 31] = CsrPlugin_mcause_interrupt; + _zz_CsrPlugin_csrMapping_readDataInit_13[3 : 0] = CsrPlugin_mcause_exceptionCode; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_14 = 32'h0; if(execute_CsrPlugin_csr_835) begin - _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_mtval; + _zz_CsrPlugin_csrMapping_readDataInit_14[31 : 0] = CsrPlugin_mtval; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_15 = 32'h0; if(execute_CsrPlugin_csr_2816) begin - _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_CsrPlugin_csrMapping_readDataInit_15[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_16 = 32'h0; if(execute_CsrPlugin_csr_2944) begin - _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_CsrPlugin_csrMapping_readDataInit_16[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_25 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_17 = 32'h0; if(execute_CsrPlugin_csr_2818) begin - _zz_CsrPlugin_csrMapping_readDataInit_25[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_CsrPlugin_csrMapping_readDataInit_17[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_26 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_18 = 32'h0; if(execute_CsrPlugin_csr_2946) begin - _zz_CsrPlugin_csrMapping_readDataInit_26[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_CsrPlugin_csrMapping_readDataInit_18[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_27 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_19 = 32'h0; if(execute_CsrPlugin_csr_3072) begin - _zz_CsrPlugin_csrMapping_readDataInit_27[31 : 0] = CsrPlugin_mcycle[31 : 0]; + _zz_CsrPlugin_csrMapping_readDataInit_19[31 : 0] = CsrPlugin_mcycle[31 : 0]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_28 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_20 = 32'h0; if(execute_CsrPlugin_csr_3200) begin - _zz_CsrPlugin_csrMapping_readDataInit_28[31 : 0] = CsrPlugin_mcycle[63 : 32]; + _zz_CsrPlugin_csrMapping_readDataInit_20[31 : 0] = CsrPlugin_mcycle[63 : 32]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_29 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_21 = 32'h0; if(execute_CsrPlugin_csr_3074) begin - _zz_CsrPlugin_csrMapping_readDataInit_29[31 : 0] = CsrPlugin_minstret[31 : 0]; + _zz_CsrPlugin_csrMapping_readDataInit_21[31 : 0] = CsrPlugin_minstret[31 : 0]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_30 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_22 = 32'h0; if(execute_CsrPlugin_csr_3202) begin - _zz_CsrPlugin_csrMapping_readDataInit_30[31 : 0] = CsrPlugin_minstret[63 : 32]; + _zz_CsrPlugin_csrMapping_readDataInit_22[31 : 0] = CsrPlugin_minstret[63 : 32]; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_31 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_23 = 32'h0; if(execute_CsrPlugin_csr_3008) begin - _zz_CsrPlugin_csrMapping_readDataInit_31[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; + _zz_CsrPlugin_csrMapping_readDataInit_23[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit; end end always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_32 = 32'h0; + _zz_CsrPlugin_csrMapping_readDataInit_24 = 32'h0; if(execute_CsrPlugin_csr_4032) begin - _zz_CsrPlugin_csrMapping_readDataInit_32[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_33 = 32'h0; - if(execute_CsrPlugin_csr_2820) begin - _zz_CsrPlugin_csrMapping_readDataInit_33[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_2; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_34 = 32'h0; - if(execute_CsrPlugin_csr_2822) begin - _zz_CsrPlugin_csrMapping_readDataInit_34[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_3; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_35 = 32'h0; - if(execute_CsrPlugin_csr_2824) begin - _zz_CsrPlugin_csrMapping_readDataInit_35[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_4; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_36 = 32'h0; - if(execute_CsrPlugin_csr_2826) begin - _zz_CsrPlugin_csrMapping_readDataInit_36[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_5; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_37 = 32'h0; - if(execute_CsrPlugin_csr_2828) begin - _zz_CsrPlugin_csrMapping_readDataInit_37[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_6; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_38 = 32'h0; - if(execute_CsrPlugin_csr_2830) begin - _zz_CsrPlugin_csrMapping_readDataInit_38[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_7; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_39 = 32'h0; - if(execute_CsrPlugin_csr_2832) begin - _zz_CsrPlugin_csrMapping_readDataInit_39[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_8; - end - end - - always @(*) begin - _zz_CsrPlugin_csrMapping_readDataInit_40 = 32'h0; - if(execute_CsrPlugin_csr_2834) begin - _zz_CsrPlugin_csrMapping_readDataInit_40[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_9; + _zz_CsrPlugin_csrMapping_readDataInit_24[31 : 0] = _zz_CsrPlugin_csrMapping_readDataInit_1; end end - assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_10 | _zz_CsrPlugin_csrMapping_readDataInit_11) | (_zz_CsrPlugin_csrMapping_readDataInit_12 | _zz_CsrPlugin_csrMapping_readDataInit_13)) | ((_zz_CsrPlugin_csrMapping_readDataInit_41 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))) | ((((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_26) | (_zz_CsrPlugin_csrMapping_readDataInit_27 | _zz_CsrPlugin_csrMapping_readDataInit_28)) | ((_zz_CsrPlugin_csrMapping_readDataInit_29 | _zz_CsrPlugin_csrMapping_readDataInit_30) | (_zz_CsrPlugin_csrMapping_readDataInit_31 | _zz_CsrPlugin_csrMapping_readDataInit_32))) | (((_zz_CsrPlugin_csrMapping_readDataInit_33 | _zz_CsrPlugin_csrMapping_readDataInit_34) | (_zz_CsrPlugin_csrMapping_readDataInit_35 | _zz_CsrPlugin_csrMapping_readDataInit_36)) | ((_zz_CsrPlugin_csrMapping_readDataInit_37 | _zz_CsrPlugin_csrMapping_readDataInit_38) | (_zz_CsrPlugin_csrMapping_readDataInit_39 | _zz_CsrPlugin_csrMapping_readDataInit_40))))); + assign CsrPlugin_csrMapping_readDataInit = (((((_zz_CsrPlugin_csrMapping_readDataInit_2 | _zz_CsrPlugin_csrMapping_readDataInit_3) | (_zz_CsrPlugin_csrMapping_readDataInit_4 | _zz_CsrPlugin_csrMapping_readDataInit_5)) | ((_zz_CsrPlugin_csrMapping_readDataInit_25 | _zz_CsrPlugin_csrMapping_readDataInit_6) | (_zz_CsrPlugin_csrMapping_readDataInit_7 | _zz_CsrPlugin_csrMapping_readDataInit_8))) | (((_zz_CsrPlugin_csrMapping_readDataInit_9 | _zz_CsrPlugin_csrMapping_readDataInit_10) | (_zz_CsrPlugin_csrMapping_readDataInit_11 | _zz_CsrPlugin_csrMapping_readDataInit_12)) | ((_zz_CsrPlugin_csrMapping_readDataInit_13 | _zz_CsrPlugin_csrMapping_readDataInit_14) | (_zz_CsrPlugin_csrMapping_readDataInit_15 | _zz_CsrPlugin_csrMapping_readDataInit_16)))) | (((_zz_CsrPlugin_csrMapping_readDataInit_17 | _zz_CsrPlugin_csrMapping_readDataInit_18) | (_zz_CsrPlugin_csrMapping_readDataInit_19 | _zz_CsrPlugin_csrMapping_readDataInit_20)) | ((_zz_CsrPlugin_csrMapping_readDataInit_21 | _zz_CsrPlugin_csrMapping_readDataInit_22) | (_zz_CsrPlugin_csrMapping_readDataInit_23 | _zz_CsrPlugin_csrMapping_readDataInit_24)))); assign when_CsrPlugin_l1297 = (CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]); assign when_CsrPlugin_l1302 = ((! execute_arbitration_isValid) || (! execute_IS_CSR)); assign iBusWishbone_ADR = {_zz_iBusWishbone_ADR_1,_zz_iBusWishbone_ADR}; @@ -5924,30 +5716,6 @@ module VexRiscv ( if(CfuPlugin_bus_rsp_ready) begin CfuPlugin_bus_rsp_rData_outputs_0 <= CfuPlugin_bus_rsp_payload_outputs_0; end - if(when_GenCoreDefault_l367) begin - _zz_CsrPlugin_csrMapping_readDataInit_2 <= (_zz_CsrPlugin_csrMapping_readDataInit_2 + 32'h00000001); - end - if(when_GenCoreDefault_l367_1) begin - _zz_CsrPlugin_csrMapping_readDataInit_3 <= (_zz_CsrPlugin_csrMapping_readDataInit_3 + 32'h00000001); - end - if(when_GenCoreDefault_l367_2) begin - _zz_CsrPlugin_csrMapping_readDataInit_4 <= (_zz_CsrPlugin_csrMapping_readDataInit_4 + 32'h00000001); - end - if(when_GenCoreDefault_l367_3) begin - _zz_CsrPlugin_csrMapping_readDataInit_5 <= (_zz_CsrPlugin_csrMapping_readDataInit_5 + 32'h00000001); - end - if(when_GenCoreDefault_l367_4) begin - _zz_CsrPlugin_csrMapping_readDataInit_6 <= (_zz_CsrPlugin_csrMapping_readDataInit_6 + 32'h00000001); - end - if(when_GenCoreDefault_l367_5) begin - _zz_CsrPlugin_csrMapping_readDataInit_7 <= (_zz_CsrPlugin_csrMapping_readDataInit_7 + 32'h00000001); - end - if(when_GenCoreDefault_l367_6) begin - _zz_CsrPlugin_csrMapping_readDataInit_8 <= (_zz_CsrPlugin_csrMapping_readDataInit_8 + 32'h00000001); - end - if(when_GenCoreDefault_l367_7) begin - _zz_CsrPlugin_csrMapping_readDataInit_9 <= (_zz_CsrPlugin_csrMapping_readDataInit_9 + 32'h00000001); - end if(when_Pipeline_l124) begin decode_to_execute_PC <= decode_PC; end @@ -6212,54 +5980,6 @@ module VexRiscv ( if(when_CsrPlugin_l1264_23) begin execute_CsrPlugin_csr_4032 <= (decode_INSTRUCTION[31 : 20] == 12'hfc0); end - if(when_CsrPlugin_l1264_24) begin - execute_CsrPlugin_csr_2820 <= (decode_INSTRUCTION[31 : 20] == 12'hb04); - end - if(when_CsrPlugin_l1264_25) begin - execute_CsrPlugin_csr_2821 <= (decode_INSTRUCTION[31 : 20] == 12'hb05); - end - if(when_CsrPlugin_l1264_26) begin - execute_CsrPlugin_csr_2822 <= (decode_INSTRUCTION[31 : 20] == 12'hb06); - end - if(when_CsrPlugin_l1264_27) begin - execute_CsrPlugin_csr_2823 <= (decode_INSTRUCTION[31 : 20] == 12'hb07); - end - if(when_CsrPlugin_l1264_28) begin - execute_CsrPlugin_csr_2824 <= (decode_INSTRUCTION[31 : 20] == 12'hb08); - end - if(when_CsrPlugin_l1264_29) begin - execute_CsrPlugin_csr_2825 <= (decode_INSTRUCTION[31 : 20] == 12'hb09); - end - if(when_CsrPlugin_l1264_30) begin - execute_CsrPlugin_csr_2826 <= (decode_INSTRUCTION[31 : 20] == 12'hb0a); - end - if(when_CsrPlugin_l1264_31) begin - execute_CsrPlugin_csr_2827 <= (decode_INSTRUCTION[31 : 20] == 12'hb0b); - end - if(when_CsrPlugin_l1264_32) begin - execute_CsrPlugin_csr_2828 <= (decode_INSTRUCTION[31 : 20] == 12'hb0c); - end - if(when_CsrPlugin_l1264_33) begin - execute_CsrPlugin_csr_2829 <= (decode_INSTRUCTION[31 : 20] == 12'hb0d); - end - if(when_CsrPlugin_l1264_34) begin - execute_CsrPlugin_csr_2830 <= (decode_INSTRUCTION[31 : 20] == 12'hb0e); - end - if(when_CsrPlugin_l1264_35) begin - execute_CsrPlugin_csr_2831 <= (decode_INSTRUCTION[31 : 20] == 12'hb0f); - end - if(when_CsrPlugin_l1264_36) begin - execute_CsrPlugin_csr_2832 <= (decode_INSTRUCTION[31 : 20] == 12'hb10); - end - if(when_CsrPlugin_l1264_37) begin - execute_CsrPlugin_csr_2833 <= (decode_INSTRUCTION[31 : 20] == 12'hb11); - end - if(when_CsrPlugin_l1264_38) begin - execute_CsrPlugin_csr_2834 <= (decode_INSTRUCTION[31 : 20] == 12'hb12); - end - if(when_CsrPlugin_l1264_39) begin - execute_CsrPlugin_csr_2835 <= (decode_INSTRUCTION[31 : 20] == 12'hb13); - end if(execute_CsrPlugin_csr_836) begin if(execute_CsrPlugin_writeEnable) begin CsrPlugin_mip_MSIP <= CsrPlugin_csrMapping_writeDataSignal[3]; @@ -6312,86 +6032,6 @@ module VexRiscv ( CsrPlugin_minstret[63 : 32] <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; end end - if(execute_CsrPlugin_csr_2820) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2821) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2822) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2823) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_1 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2824) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2825) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_2 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2826) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2827) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_3 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2828) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2829) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_4 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2830) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2831) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_5 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2832) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_8 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2833) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_6 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2834) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_CsrPlugin_csrMapping_readDataInit_9 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end - if(execute_CsrPlugin_csr_2835) begin - if(execute_CsrPlugin_writeEnable) begin - _zz_when_GenCoreDefault_l367_7 <= CsrPlugin_csrMapping_writeDataSignal[31 : 0]; - end - end iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; dBusWishbone_DAT_MISO_regNext <= dBusWishbone_DAT_MISO; end